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#include <bits/stdc++.h> using namespace std; class Solution { public: void solve(std::istream& in, std::ostream& out) { long long n, k, b, c, a, d; in >> n >> k >> b >> c; b = min(b, 5 * c); vector<pair<long long, long long>> x(n); for (int i = 0; i < n; i++) { in >> a; x[i] = make_pair(a, 0); } for (int i = 0; i < n; i++) { for (int j = 1; j < 5; j++) { x.push_back(make_pair(x[i].first + j, -j)); } } n = x.size(); vector<vector<pair<long long, long long>>> y(5), z(5); for (int i = 0; i < n; i++) { a = x[i].first % 5; if (a < 0) { a = a + 5; } y[a].push_back(x[i]); } for (int i = 0; i < 5; i++) { sort(begin(y[i]), end(y[i])); int t = y[i].size(); long long h = y[i].back().first; z[i] = vector<pair<long long, long long>>(t); for (int j = 0; j < t; j++) { z[i][j] = make_pair(-((h - y[i][j].first) / 5 * b - y[i][j].second * c), j); } sort(begin(z[i]), end(z[i])); } long long m = 100000000000000000; for (int i = 0; i < 5; i++) { int t = y[i].size(); priority_queue<pair<int, int>> q; long long p = 0; int l = t - 1, r = t - 1; long long h; while (l >= 0) { if (r < 0) break; d = y[i][r].first; if (q.size()) { a = q.top().first; p -= (h - a) / 5 * b * q.size(); h = a; } while (q.size() && d < q.top().first) { p += q.top().second * c; q.pop(); if (q.size()) { a = q.top().first; p -= (h - a) / 5 * b * q.size(); h = a; } else p = 0; } if (q.size()) { a = q.top().first; p += (d - a) / 5 * b * q.size(); } while (l >= 0 && q.size() < k) { a = z[i][l].second; if (y[i][a].first > d) { l--; continue; } p -= y[i][a].second * c; p += (d - y[i][a].first) / 5 * b; q.push(y[i][a]); l--; } if (q.size() == k) m = min(m, p); h = d; r--; while (r >= 0 && y[i][r].first == y[i][r + 1].first) r--; } } out << m; } }; void solve(std::istream& in, std::ostream& out) { out << std::setprecision(12); Solution solution; solution.solve(in, out); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); istream& in = cin; ostream& out = cout; solve(in, out); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NOR2_TB_V
`define SKY130_FD_SC_HVL__NOR2_TB_V
/**
* nor2: 2-input NOR.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__nor2.v"
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hvl__nor2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NOR2_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFSBP_2_V
`define SKY130_FD_SC_HDLL__SDFSBP_2_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog wrapper for sdfsbp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__sdfsbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sdfsbp_2 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__sdfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sdfsbp_2 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__sdfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFSBP_2_V
|
#include <bits/stdc++.h> using namespace std; int prime[100010]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n; cin >> n; int cnt = 0; for (int i = 2; i <= n; i++) { if (!prime[i]) { cnt++; for (int j = i; j <= n; j += i) prime[j] = cnt; } } for (int i = 2; i <= n; i++) cout << prime[i] << ; cout << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; using vi = vector<long long>; template <typename T> std::istream& operator>>(std::istream& input, std::pair<T, T>& data) { input >> data.first >> data.second; return input; } template <typename T> std::istream& operator>>(std::istream& input, std::vector<T>& data) { for (T& first : data) input >> first; return input; } template <typename T> std::ostream& operator<<(std::ostream& output, const pair<T, T>& data) { output << ( << data.first << , << data.second << ) ; return output; } template <typename T> std::ostream& operator<<(std::ostream& output, const std::vector<T>& data) { for (const T& first : data) output << first << ; return output; } std::ostream& operator<<(std::ostream& output, const __int128& first) { __int128 n = first; if (n == 0) { output << 0 ; return output; } if (n < 0) { n = -n; output << - ; } string s; while (n) { s += 0 + (n % 10); n /= 10; } reverse(s.begin(), s.end()); cout << s; return output; } long long div_up(long long a, long long b) { return a / b + ((a ^ b) > 0 && a % b); } long long div_down(long long a, long long b) { return a / b - ((a ^ b) < 0 && a % b); } long long math_mod(long long a, long long b) { return a - b * div_down(a, b); } template <class T> using V = vector<T>; template <class T> bool ckmin(T& a, const T& b) { return b < a ? a = b, 1 : 0; } template <class T> bool ckmax(T& a, const T& b) { return a < b ? a = b, 1 : 0; } long long gcd(long long a, long long b) { while (b) { tie(a, b) = make_pair(b, a % b); } return a; } long long Bit(long long mask, long long bit) { return (mask >> bit) & 1; } template <long long MOD, long long RT> struct mint { static const long long mod = MOD; static constexpr mint rt() { return RT; } long long v; explicit operator long long() const { return v; } mint() { v = 0; } mint(long long _v) { v = (long long)((-MOD < _v && _v < MOD) ? _v : _v % MOD); if (v < 0) v += MOD; } friend bool operator==(const mint& a, const mint& b) { return a.v == b.v; } friend bool operator!=(const mint& a, const mint& b) { return !(a == b); } friend bool operator<(const mint& a, const mint& b) { return a.v < b.v; } friend string ts(mint a) { return to_string(a.v); } mint& operator+=(const mint& m) { if ((v += m.v) >= MOD) v -= MOD; return *this; } mint& operator-=(const mint& m) { if ((v -= m.v) < 0) v += MOD; return *this; } mint& operator*=(const mint& m) { v = (long long)((long long)v * m.v % MOD); return *this; } mint& operator/=(const mint& m) { return (*this) *= inv(m); } friend mint pow(mint a, long long p) { mint ans = 1; assert(p >= 0); for (; p; p /= 2, a *= a) if (p & 1) ans *= a; return ans; } mint& operator^=(const long long& p) { return (*this) = pow(this, p); } friend mint inv(const mint& a) { assert(a.v != 0); return pow(a, MOD - 2); } mint operator-() const { return mint(-v); } mint& operator++() { return *this += 1; } mint& operator--() { return *this -= 1; } friend mint operator+(mint a, const mint& b) { return a += b; } friend mint operator-(mint a, const mint& b) { return a -= b; } friend mint operator*(mint a, const mint& b) { return a *= b; } friend mint operator/(mint a, const mint& b) { return a /= b; } friend mint operator^(mint a, const long long p) { return pow(a, p); } }; const long long MOD = 1e9 + 7; typedef mint<MOD, 5> mi; std::ostream& operator<<(std::ostream& o, const mi& a) { cout << a.v; return o; } vector<vector<mi> > scmb; void genComb(long long SZ) { scmb.assign(SZ, vector<mi>(SZ)); scmb[0][0] = 1; for (long long i = (1); i < (SZ); ++i) for (long long j = (0); j < (i + 1); ++j) scmb[i][j] = scmb[i - 1][j] + (j ? scmb[i - 1][j - 1] : 0); } vector<mi> invs, fac, ifac; void genFac(long long SZ) { invs.resize(SZ), fac.resize(SZ), ifac.resize(SZ); invs[1] = fac[0] = ifac[0] = 1; for (long long i = (2); i < (SZ); ++i) invs[i] = mi(-(long long)MOD / i * (long long)invs[MOD % i]); for (long long i = (1); i < (SZ); ++i) { fac[i] = fac[i - 1] * i; ifac[i] = ifac[i - 1] * invs[i]; } } mi comb(long long a, long long b) { if (a < b || b < 0) return 0; assert(a < fac.size()); return fac[a] * ifac[b] * ifac[a - b]; } const long long N = 507; long long link[N]; const long long K = 1 << 16; void ANDConvolution(mi v[K]) { for (long long step = K; step > 1; step /= 2) { for (long long start = 0; start < K; start += step) { for (long long w = 0; w < step / 2; w++) { v[start + w] += v[start + w + step / 2]; } } } } void inverseANDConvolution(mi v[K]) { for (long long step = K; step > 1; step /= 2) { for (long long start = 0; start < K; start += step) { for (long long w = 0; w < step / 2; w++) { v[start + w] -= v[start + w + step / 2]; } } } } void ORConvolution(mi v[K]) { for (long long step = K; step > 1; step /= 2) { for (long long start = 0; start < K; start += step) { for (long long w = 0; w < step / 2; w++) { v[start + step / 2 + w] += v[start + w]; } } } } void inverseORConvolution(mi v[K]) { for (long long step = K; step > 1; step /= 2) { for (long long start = 0; start < K; start += step) { for (long long w = 0; w < step / 2; w++) { v[start + step / 2 + w] -= v[start + w]; } } } } mi dp[N][1 << 16]; string s; mi A[K], B[K], C[K]; long long ptr = 0; long long solve(long long l, long long r) { long long v = ptr; ptr++; if (l == r) { long long who = -1, add = -1; if (s[l] == a ) { who = 0; add = 1; } else if (s[l] == A ) { who = 0; add = 0; } else if (s[l] == b ) { who = 1; add = 1; } else if (s[l] == B ) { who = 1; add = 0; } else if (s[l] == c ) { who = 2; add = 1; } else if (s[l] == C ) { who = 2; add = 0; } else if (s[l] == d ) { who = 3; add = 1; } else if (s[l] == D ) { who = 3; add = 0; } else { assert(s[l] == ? ); } if (who != -1) { long long foo = 0; for (long long mask = (0); mask < (16); ++mask) { if (Bit(mask, who) ^ add) { foo ^= 1 << mask; } } dp[v][foo] += 1; } else { for (long long who = (0); who < (4); ++who) { for (long long add = (0); add < (2); ++add) { long long foo = 0; for (long long mask = (0); mask < (16); ++mask) { if (Bit(mask, who) ^ add) { foo ^= 1 << mask; } } dp[v][foo] += 1; } } } return v; } long long L = solve(l + 1, link[l] - 1); long long nextb = link[l] + 2; long long R = solve(nextb + 1, link[nextb] - 1); if (s[nextb - 1] != & ) { for (long long i = (0); i < (K); ++i) { A[i] = dp[L][i]; B[i] = dp[R][i]; } ORConvolution(A); ORConvolution(B); for (long long i = 0; i < K; i++) { C[i] = A[i] * B[i]; } inverseORConvolution(C); for (long long i = (0); i < (K); ++i) { dp[v][i] += C[i]; } } if (s[nextb - 1] != | ) { for (long long i = (0); i < (K); ++i) { A[i] = dp[L][i]; B[i] = dp[R][i]; } ANDConvolution(A); ANDConvolution(B); for (long long i = 0; i < K; i++) { C[i] = A[i] * B[i]; } inverseANDConvolution(C); for (long long i = (0); i < (K); ++i) { dp[v][i] += C[i]; } } return v; } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> s; long long len = s.size(); vi sk; for (long long i = (0); i < (len); ++i) { if (s[i] == ( ) { sk.push_back(i); } else if (s[i] == ) ) { assert(sk.size()); link[sk.back()] = i; link[i] = sk.back(); sk.pop_back(); } } long long root = solve(0, len - 1); long long q; cin >> q; long long want = 0; long long know = 0; for (long long _ = (0); _ < (q); ++_) { long long bit = 0; for (long long i = (0); i < (4); ++i) { long long first; cin >> first; if (first) { bit ^= 1 << i; } } know ^= 1 << bit; long long res; cin >> res; if (res) { want ^= 1 << bit; } } mi ans = 0; for (long long mask = (0); mask < (1 << 16); ++mask) { bool ok = 1; for (long long bit = (0); bit < (16); ++bit) { if (Bit(know, bit)) { ok &= Bit(want, bit) == Bit(mask, bit); } } if (ok) { ans += dp[root][mask]; } } cout << ans << n ; } |
`timescale 1ns / 1ps
module testbench;
parameter SIZEIN = 16, SIZEOUT = 40;
reg clk, ce, rst;
reg signed [SIZEIN-1:0] a, b;
output signed [SIZEOUT-1:0] REF_accum_out, accum_out;
output REF_overflow, overflow;
integer errcount = 0;
reg ERROR_FLAG = 0;
task clkcycle;
begin
#5;
clk = ~clk;
#10;
clk = ~clk;
#2;
ERROR_FLAG = 0;
if (REF_accum_out !== accum_out) begin
$display("ERROR at %1t: REF_accum_out=%b UUT_accum_out=%b DIFF=%b", $time, REF_accum_out, accum_out, REF_accum_out ^ accum_out);
errcount = errcount + 1;
ERROR_FLAG = 1;
end
if (REF_overflow !== overflow) begin
$display("ERROR at %1t: REF_overflow=%b UUT_overflow=%b DIFF=%b", $time, REF_overflow, overflow, REF_overflow ^ overflow);
errcount = errcount + 1;
ERROR_FLAG = 1;
end
#3;
end
endtask
initial begin
//$dumpfile("test_macc.vcd");
//$dumpvars(0, testbench);
#2;
clk = 1'b0;
ce = 1'b0;
a = 0;
b = 0;
rst = 1'b1;
repeat (10) begin
#10;
clk = 1'b1;
#10;
clk = 1'b0;
#10;
clk = 1'b1;
#10;
clk = 1'b0;
end
rst = 1'b0;
repeat (10000) begin
clkcycle;
ce = 1; //$urandom & $urandom;
//rst = $urandom & $urandom & $urandom & $urandom & $urandom & $urandom;
a = $urandom & ~(1 << (SIZEIN-1));
b = $urandom & ~(1 << (SIZEIN-1));
end
if (errcount == 0) begin
$display("All tests passed.");
$finish;
end else begin
$display("Caught %1d errors.", errcount);
$stop;
end
end
macc2 ref (
.clk(clk),
.ce(ce),
.rst(rst),
.a(a),
.b(b),
.accum_out(REF_accum_out),
.overflow(REF_overflow)
);
macc2_uut uut (
.clk(clk),
.ce(ce),
.rst(rst),
.a(a),
.b(b),
.accum_out(accum_out),
.overflow(overflow)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O22A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__O22A_FUNCTIONAL_PP_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__o22a (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X , or0_out, or1_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O22A_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1.0); const int INF = 1000 * 1000 * 1000 + 7; const long long LINF = INF * (long long)INF; const int L = 22; int G[L]; int dp[1 << L]; int P[1 << L]; int M[1 << L]; int n; void print(int mask) { for (int i = (0); i < (n); i++) { if (mask & (1 << i)) { cout << 1 ; continue; } cout << 0 ; } cout << endl; } bool isClik(int mask) { for (int i = (0); i < (n); i++) { if ((1 << i) & mask) { mask ^= 1 << i; if ((mask & G[i]) != mask) return false; mask ^= 1 << i; } } return true; } int main() { ios::sync_with_stdio(false); cin.tie(0); int m; cin >> n >> m; for (int i = (0); i < (m); i++) { int a, b; cin >> a >> b; a--; b--; G[a] |= 1 << b; G[b] |= 1 << a; } for (int mask = (0); mask < (1 << n); mask++) { dp[mask] = INF; } for (int mask = (0); mask < (1 << n); mask++) { if (isClik(mask)) { dp[mask] = 0; } } for (int mask = (0); mask < (1 << n); mask++) { for (int k = (0); k < (n); k++) { if (!(mask & (1 << k))) continue; if (dp[mask | G[k]] > dp[mask] + 1) { dp[mask | G[k]] = dp[mask] + 1; P[mask | G[k]] = k; M[mask | G[k]] = mask; } dp[mask | G[k]] = min(dp[mask | G[k]], dp[mask] + 1); } } int ans = dp[(1 << n) - 1]; cout << ans << endl; vector<int> res; int mask = (1 << n) - 1; for (int i = (0); i < (ans); i++) { res.push_back(P[mask]); mask = M[mask]; } reverse(res.begin(), res.end()); for (int i = (0); i < ((int)res.size()); i++) { cout << res[i] + 1 << ; } cout << endl; } |
// --------------------------------------------------------------------
// Copyright (c) 2007 by Terasic Technologies Inc.
// --------------------------------------------------------------------
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// --------------------------------------------------------------------
//
// Terasic Technologies Inc
// 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
// HsinChu County, Taiwan
// 302
//
// web: http://www.terasic.com/
// email:
//
// --------------------------------------------------------------------
/*
Function:
WOLFSON WM8731 controller
I2C Configuration Requirements:
Master Mode
I2S, 16-bits
Clock:
18.432MHz to XTI/MCLK pin of WM8731
Revision:
1.0, 10/22/2007, Init by Richard
Compatibility:
Quartus 7.2
*/
module AUDIO_IF(
avs_s1_clk,
avs_s1_reset,
avs_s1_address,
avs_s1_read,
avs_s1_readdata,
avs_s1_write,
avs_s1_writedata,
//
avs_s1_export_BCLK,
avs_s1_export_DACLRC,
avs_s1_export_DACDAT,
avs_s1_export_ADCLRC,
avs_s1_export_ADCDAT
);
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
`define DAC_LFIFO_ADDR 0
`define DAC_RFIFO_ADDR 1
`define ADC_LFIFO_ADDR 2
`define ADC_RFIFO_ADDR 3
`define CMD_ADDR 4
`define STATUS_ADDR 5
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
input avs_s1_clk;
input avs_s1_reset;
input [2:0] avs_s1_address;
input avs_s1_read;
output [15:0] avs_s1_readdata;
input avs_s1_write;
input [15:0] avs_s1_writedata;
//
input avs_s1_export_BCLK;
input avs_s1_export_DACLRC;
output avs_s1_export_DACDAT;
input avs_s1_export_ADCLRC;
input avs_s1_export_ADCDAT;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// host
reg [15:0] reg_readdata;
reg fifo_clear;
// dac
wire dacfifo_full;
reg dacfifo_write;
reg [31:0] dacfifo_writedata;
// adc
wire adcfifo_empty;
reg adcfifo_read;
wire [31:0] adcfifo_readdata;
reg [31:0] data32_from_adcfifo;
reg [31:0] data32_from_adcfifo_2;
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
////////// fifo clear
always @ (posedge avs_s1_clk)
begin
if (avs_s1_reset)
fifo_clear <= 1'b0;
else if (avs_s1_write && (avs_s1_address == `CMD_ADDR))
fifo_clear <= avs_s1_writedata[0];
else if (fifo_clear)
fifo_clear <= 1'b0;
end
////////// write audio data(left&right) to dac-fifo
always @ (posedge avs_s1_clk)
begin
if (avs_s1_reset || fifo_clear)
begin
dacfifo_write <= 1'b0;
end
else if (avs_s1_write && (avs_s1_address == `DAC_LFIFO_ADDR))
begin
dacfifo_writedata[31:16] <= avs_s1_writedata;
dacfifo_write <= 1'b0;
end
else if (avs_s1_write && (avs_s1_address == `DAC_RFIFO_ADDR))
begin
dacfifo_writedata[15:0] <= avs_s1_writedata;
dacfifo_write <= 1'b1;
end
else
dacfifo_write <= 1'b0;
end
////////// response data to avalon-mm
always @ (negedge avs_s1_clk)
begin
if (avs_s1_reset || fifo_clear)
data32_from_adcfifo = 0;
else if (avs_s1_read && (avs_s1_address == `STATUS_ADDR))
reg_readdata <= {adcfifo_empty, dacfifo_full};
else if (avs_s1_read && (avs_s1_address == `ADC_LFIFO_ADDR))
reg_readdata <= data32_from_adcfifo[31:16];
else if (avs_s1_read && (avs_s1_address == `ADC_RFIFO_ADDR))
begin
reg_readdata <= data32_from_adcfifo[15:0];
data32_from_adcfifo <= data32_from_adcfifo_2;
end
end
////////// read audio data from adc fifo
always @ (negedge avs_s1_clk)
begin
if (avs_s1_reset)
begin
adcfifo_read <= 1'b0;
data32_from_adcfifo_2 <= 0;
end
else if ((avs_s1_address == `ADC_LFIFO_ADDR) & avs_s1_read & ~adcfifo_empty)
begin
adcfifo_read <= 1'b1;
end
else if (adcfifo_read)
begin
data32_from_adcfifo_2 = adcfifo_readdata;
adcfifo_read <= 1'b0;
end
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
assign avs_s1_readdata = reg_readdata;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
AUDIO_DAC DAC_Instance(
// host
.clk(avs_s1_clk),
.reset(avs_s1_reset),
.write(dacfifo_write),
.writedata(dacfifo_writedata),
.full(dacfifo_full),
.clear(fifo_clear),
// dac
.bclk(avs_s1_export_BCLK),
.daclrc(avs_s1_export_DACLRC),
.dacdat(avs_s1_export_DACDAT)
);
AUDIO_ADC ADC_Instance(
// host
.clk(avs_s1_clk),
.reset(avs_s1_reset),
.read(adcfifo_read),
.readdata(adcfifo_readdata),
.empty(adcfifo_empty),
.clear(fifo_clear),
// adc
.bclk(avs_s1_export_BCLK),
.adclrc(avs_s1_export_ADCLRC),
.adcdat(avs_s1_export_ADCDAT)
);
defparam
DAC_Instance.DATA_WIDTH = 32;
defparam
ADC_Instance.DATA_WIDTH = 32;
endmodule
|
#include <bits/stdc++.h> namespace fft { using namespace std; const double PI = std::atan2(0, -1); using dbl = double; struct num { dbl x, y; num(dbl x_ = 0, dbl y_ = 0) : x(x_), y(y_) {} }; inline num operator+(num a, num b) { return num(a.x + b.x, a.y + b.y); } inline num operator-(num a, num b) { return num(a.x - b.x, a.y - b.y); } inline num operator*(num a, num b) { return num(a.x * b.x - a.y * b.y, a.x * b.y + a.y * b.x); } inline num conj(num a) { return num(a.x, -a.y); } inline num inv(num a) { dbl n = (a.x * a.x + a.y * a.y); return num(a.x / n, -a.y / n); } using vn = vector<num>; vector<int> rev({0, 1}); vn rt(2, num(1)), fa, fb; inline void init(int n) { if (n <= (int)(rt).size()) return; rev.resize(n); for (int i = 0; i < (n); ++i) rev[i] = (rev[i >> 1] | ((i & 1) * n)) >> 1; rt.reserve(n); for (int k = (int)(rt).size(); k < n; k *= 2) { rt.resize(2 * k); double a = PI / k; num z(cos(a), sin(a)); for (int i = k / 2; i < (k); ++i) rt[2 * i] = rt[i], rt[2 * i + 1] = rt[i] * z; } } inline void fft(vector<num>& a, int n) { init(n); int s = __builtin_ctz((int)(rev).size() / n); for (int i = 0; i < (n); ++i) if (i < rev[i] >> s) swap(a[i], a[rev[i] >> s]); for (int k = 1; k < n; k *= 2) for (int i = 0; i < n; i += 2 * k) for (int j = 0; j < (k); ++j) { num t = rt[j + k] * a[i + j + k]; a[i + j + k] = a[i + j] - t; a[i + j] = a[i + j] + t; } } using vd = vector<double>; vd multiply(const vd& a, const vd& b) { int s = (int)(a).size() + (int)(b).size() - 1; if (s <= 0) return {}; int L = s > 1 ? 32 - __builtin_clz(s - 1) : 0, n = 1 << L; if ((int)(fa).size() < n) fa.resize(n); if ((int)(fb).size() < n) fb.resize(n); fill(fa.begin(), fa.begin() + n, 0); for (int i = 0; i < ((int)(a).size()); ++i) fa[i].x = a[i]; for (int i = 0; i < ((int)(b).size()); ++i) fa[i].y = b[i]; fft(fa, n); for (auto& x : fa) x = x * x; for (int i = 0; i < (n); ++i) fb[i] = fa[(n - i) & (n - 1)] - conj(fa[i]); fft(fb, n); vd r(s); for (int i = 0; i < (s); ++i) r[i] = fb[i].y / (4 * n); return r; } } // namespace fft int main() { using namespace std; ios_base::sync_with_stdio(false), cin.tie(nullptr); array<int, 2> N; int Q; cin >> N[0] >> N[1] >> Q; array<vector<int>, 2> A; for (int z = 0; z < 2; z++) { A[z].resize(N[z]); for (int& v : A[z]) cin >> v; } vector<int> queries(Q); for (auto& q : queries) cin >> q; const int X = int(1e5) + 100; array<vector<double>, 2> mults; for (int z = 0; z < 2; z++) { mults[z].assign(X, 0); for (int i = 0; i + 1 < N[z]; i++) { mults[z][min(A[z][i], A[z][i + 1])]--; mults[z][max(A[z][i], A[z][i + 1])]++; } } vector<long long> ans(2 * X - 1); vector<double> ans_double = fft::multiply(mults[0], mults[1]); for (int i = 0; i < 2 * X - 1; i++) { ans[i] = ((ans_double[i] > 0) - (ans_double[i] < 0)) * (long long)(abs(ans_double[i]) + 0.5); } for (int a : {A[0].front(), A[0].back()}) { for (int b : {A[1].front(), A[1].back()}) { ans[a + b]++; } } for (int i = 2 * X - 3; i >= 0; i--) { ans[i] += ans[i + 1]; } long long tot = ans[0]; for (auto& a : ans) { a = 2 * a - tot; a /= 4; } for (int q : queries) { cout << ans[q] << n ; } return 0; } |
`timescale 1ns/10ps
module hps_design_pll_0(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("normal"),
.number_of_clocks(1),
.output_clock_frequency0("100.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("0 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long i, j, m, a, s, c, b, n, x, y, ar[1001]; cin >> n; while (n--) { cin >> s >> a >> b >> c; x = s / c; y = x / a * b; cout << x + y << endl; } return 0; } |
/**
* $Id: red_pitaya_daisy_rx.v -01-21 11:40:39Z matej.oblak $
*
* @brief Red Pitaya daisy chain communication module. RX de-serializator.
*
* @Author Matej Oblak
*
* (c) Red Pitaya http://www.redpitaya.com
*
* This part of code is written in Verilog hardware description language (HDL).
* Please visit http://en.wikipedia.org/wiki/Verilog
* for more details on the language used herein.
*/
/**
* GENERAL DESCRIPTION:
*
* This module takes care of receiving serial data.
*
*
* /------\
* RX DAT ---> | SER |
* | -> | -------> RX PARALLEL
* RX CLK ---> | PAR |
* \------/
* |
* -------------< CFG
*
*
* Received clock is used to sample input serial data and de-serialize them
* using ISERDESE2. Same clock is also divided to make slower clock used for
* parallel data.
*
* Because unknown starting phase relation between serial and parallel clock
* there is need to allign input data. This is done with bitslip functionality
* (for 4-bits). In our case parallel data width is 16-bits so we need to slip
* also nibbles (par_cnt) to achive correct received data. To have this
* functionality working correctly module needs known received value. For now
* this value is 16'h00FF.
*
* When link is trained, software can disable trainig and regular data can be
* received (until connection is broken).
*
* Clock which is received is the same as transmitted (other board clock domain) !!!!
*
*/
module red_pitaya_daisy_rx
(
// serial ports
input ser_clk_i , //!< RX high-speed clock
input ser_dat_i , //!< RX high-speed data
// paralel ports
input cfg_en_i , //!< global module enable
input cfg_train_i , //!< enable training
output cfg_trained_o , //!< module trained
input dly_clk_i , //!< IDELAY clock
output par_clk_o , //!< parallel clock
output par_rstn_o , //!< parallel reset - active low
output reg par_dv_o , //!< parallel data enable
output reg [ 16-1: 0] par_dat_o //!< parallel data
);
//---------------------------------------------------------------------------------
//
// De-serialize - clock
wire ser_clk ;
wire ser_clk_dly = ser_clk_i;
wire par_clk ;
reg [16-1: 0] par_rstn_r ;
reg par_rstn ;
wire dly_rdy = 1'b1;
// // delay the input clock
//(* IODELAY_GROUP = "daisy_rx_clk_group" *)
//IDELAYE2
//# (
// .CINVCTRL_SEL ( "FALSE" ), // TRUE, FALSE
// .DELAY_SRC ( "IDATAIN" ), // IDATAIN, DATAIN
// .HIGH_PERFORMANCE_MODE ( "TRUE" ), // TRUE, FALSE
// .IDELAY_TYPE ( "FIXED" ), // FIXED, VARIABLE, or VAR_LOADABLE
// .IDELAY_VALUE ( 0 ), // 0 to 31
// .REFCLK_FREQUENCY ( 200.0 ),
// .PIPE_SEL ( "FALSE" ),
// .SIGNAL_PATTERN ( "CLOCK" ) // CLOCK, DATA
//)
//idelaye2_clk
//(
// .DATAOUT ( ser_clk_dly ), // Delayed clock
// .DATAIN ( 1'b0 ), // Data from FPGA logic
// .C ( 1'b0 ),
// .CE ( 1'b0 ),
// .INC ( 1'b0 ),
// .IDATAIN ( ser_clk_i ),
// .LD ( !cfg_en_i ),
// .LDPIPEEN ( 1'b0 ),
// .REGRST ( 1'b0 ),
// .CNTVALUEIN ( 5'b00000 ),
// .CNTVALUEOUT (),
// .CINVCTRL ( 1'b0 )
//);
//// IDELAYCTRL is needed for calibration
//(* IODELAY_GROUP = "daisy_rx_clk_group" *)
//IDELAYCTRL
//delayctrl (
// .RDY ( dly_rdy ),
// .REFCLK ( dly_clk_i ),
// .RST ( !cfg_en_i )
//);
// High Speed BUFIO clock buffer
BUFIO i_BUFIO_clk
(
.O ( ser_clk ),
.I ( ser_clk_dly )
);
// BUFR generates slow clock
BUFR #(.SIM_DEVICE("7SERIES"), .BUFR_DIVIDE("2")) i_BUFR_clk
(
.O ( par_clk ),
.CE ( 1'b1 ),
.CLR ( !cfg_en_i ),
.I ( ser_clk_dly )
);
// Reset on receive clock domain
always @(posedge par_clk or negedge cfg_en_i) begin
if (cfg_en_i == 1'b0) begin
par_rstn_r <= 16'h0 ;
par_rstn <= 1'b0 ;
end
else begin
par_rstn_r <= {par_rstn_r[16-2:0], dly_rdy} ;
par_rstn <= par_rstn_r[16-1];
end
end
//---------------------------------------------------------------------------------
//
// De-serialize - data
reg bitslip ;
reg [ 5-1: 0] bitslip_cnt ;
reg [ 3-1: 0] nibslip_cnt ;
wire [ 8-1: 0] rxp_dat ;
reg [ 4-1: 0] rxp_dat_1r ;
reg [ 4-1: 0] rxp_dat_2r ;
reg [ 4-1: 0] rxp_dat_3r ;
reg par_dv ;
reg [16-1: 0] par_dat ;
reg par_ok ;
reg [ 2-1: 0] par_cnt ;
reg par_val ;
ISERDESE2
#(
.DATA_RATE ( "DDR" ),
.DATA_WIDTH ( 4 ),
.INTERFACE_TYPE ( "NETWORKING" ),
.DYN_CLKDIV_INV_EN ( "FALSE" ),
.DYN_CLK_INV_EN ( "FALSE" ),
.NUM_CE ( 2 ),
.OFB_USED ( "FALSE" ),
.IOBDELAY ( "NONE" ), // Use input at D to output the data on Q
.SERDES_MODE ( "MASTER" )
)
i_iserdese
(
.Q1 ( rxp_dat[7] ),
.Q2 ( rxp_dat[6] ),
.Q3 ( rxp_dat[5] ),
.Q4 ( rxp_dat[4] ),
.Q5 ( rxp_dat[3] ),
.Q6 ( rxp_dat[2] ),
.Q7 ( rxp_dat[1] ),
.Q8 ( rxp_dat[0] ),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.BITSLIP ( bitslip ), // 1-bit Invoke Bitslip. This can be used with any DATA_WIDTH, cascaded or not.
// The amount of bitslip is fixed by the DATA_WIDTH selection.
.CE1 ( cfg_en_i ), // 1-bit Clock enable input
.CE2 ( cfg_en_i ), // 1-bit Clock enable input
.CLK ( ser_clk ), // Fast source synchronous clock driven by BUFIO
.CLKB ( !ser_clk ), // Locally inverted fast
.CLKDIV ( par_clk ), // Slow clock from BUFR.
.CLKDIVP ( 1'b0 ),
.D ( ser_dat_i ), // 1-bit Input signal from IOB
.DDLY ( 1'b0 ), // 1-bit Input from Input Delay component
.RST ( !par_rstn ), // 1-bit Asynchronous reset only.
.SHIFTIN1 ( 1'b0 ),
.SHIFTIN2 ( 1'b0 ),
.DYNCLKDIVSEL ( 1'b0 ),
.DYNCLKSEL ( 1'b0 ),
.OFB ( 1'b0 ),
.OCLK ( 1'b0 ),
.OCLKB ( 1'b0 ),
.O ()
);
//---------------------------------------------------------------------------------
//
// Data control
reg [ 2-1: 0] par_train_r ;
reg par_train ;
// synchronize training control
always @(posedge par_clk) begin
if (par_rstn == 1'b0) begin
par_train_r <= 2'h0 ;
par_train <= 1'b0 ;
end
else begin
par_train_r <= {par_train_r[0], cfg_train_i} ;
par_train <= par_train_r[1];
end
end
// connection training - bitslip and nibble "shift"
always @(posedge par_clk) begin
if (par_rstn == 1'b0) begin
bitslip <= 1'b0 ;
bitslip_cnt <= 5'b0 ;
nibslip_cnt <= 3'h0 ;
par_ok <= 1'b0 ;
par_cnt <= 2'h0 ;
par_val <= 1'b0 ;
end
else begin
// shifting input data by 1 bit
if (par_train)
bitslip_cnt <= bitslip_cnt + 5'h1 ;
else
bitslip_cnt <= 5'h0 ;
bitslip <= (bitslip_cnt[3:2] == 3'b10) && (par_dat != 16'h00FF) && par_dv && !par_ok ;
// shifting input data by 4bits every 8 bitslips
if (par_train && bitslip && !par_ok)
nibslip_cnt <= nibslip_cnt + 3'h1 ;
else if (!par_train || par_ok)
nibslip_cnt <= 3'h0 ;
if ((nibslip_cnt == 3'h7) && bitslip)
par_cnt <= par_cnt ; // "shift" input data by 4
else
par_cnt <= par_cnt + 2'h1 ;
par_val <= (par_cnt==2'b01) ;
// testing if connection is trained
if (par_train && (par_dat == 16'h00FF) && par_dv)
par_ok <= 1'b1 ;
else if ((bitslip_cnt[3:2] == 3'b10) && (par_dat != 16'h00FF) && par_dv)
par_ok <= 1'b0 ;
end
end
// combining data - concentrate 4 nibbles
always @(posedge par_clk) begin
if (par_rstn == 1'b0) begin
rxp_dat_1r <= 4'h0 ;
rxp_dat_2r <= 4'h0 ;
rxp_dat_3r <= 4'h0 ;
par_dv <= 1'b0 ;
par_dat <= 16'h0 ;
end
else begin
rxp_dat_1r <= rxp_dat[3:0];
rxp_dat_2r <= rxp_dat_1r ;
rxp_dat_3r <= rxp_dat_2r ;
par_dv <= par_val ;
if (par_val)
par_dat <= {rxp_dat, rxp_dat_1r, rxp_dat_2r, rxp_dat_3r};
par_dv_o = par_dv && par_ok && !par_train ;
par_dat_o = par_dat;
end
end
BUFG i_parclk_buf (.O(par_clk_o), .I(par_clk));
//assign par_clk_o = par_clk ;
assign par_rstn_o = par_rstn ;
assign cfg_trained_o = par_ok ;
endmodule
|
#include <bits/stdc++.h> using namespace std; int p[200007]; int c1[200007]; int c2[200007]; bool used[200007]; int main() { int n; cin >> n; for (int i = 0; i < n; ++i) { scanf( %d , &p[i]); } for (int i = 0; i < n; ++i) { scanf( %d , &c1[i]); c1[i]--; } for (int i = 0; i < n; ++i) { scanf( %d , &c2[i]); c2[i]--; } priority_queue<pair<int, int>> q[3]; for (int i = 0; i < n; ++i) { if (c1[i] == c2[i]) { q[c1[i]].push(make_pair(-p[i], i)); } else { q[c1[i]].push(make_pair(-p[i], i)); q[c2[i]].push(make_pair(-p[i], i)); } } int m, x; cin >> m; for (int i = 0; i < m; ++i) { scanf( %d , &x); x--; while (!q[x].empty() && used[q[x].top().second]) q[x].pop(); if (q[x].empty()) printf( -1 ); else { printf( %d , -q[x].top().first); used[q[x].top().second] = 1; q[x].pop(); } } } |
#include <bits/stdc++.h> using namespace std; const int P = 1e9 + 7, INF = 0x3f3f3f3f; long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } long long qpow(long long a, long long n) { long long r = 1 % P; for (a %= P; n; a = a * a % P, n >>= 1) if (n & 1) r = r * a % P; return r; } long long inv(long long first) { return first <= 1 ? 1 : inv(P % first) * (P - P / first) % P; } inline int rd() { int first = 0; char p = getchar(); while (p < 0 || p > 9 ) p = getchar(); while (p >= 0 && p <= 9 ) first = first * 10 + p - 0 , p = getchar(); return first; } const int N = 1e6 + 10; int n, a, b; struct _ { long long a, b, c; void pr() { printf( a=%lld,b=%lld n , a, b); } bool operator<(const _& rhs) const { return c > rhs.c; } } e[N]; long long ans; int vis[N]; int main() { scanf( %d%d%d , &n, &a, &b); for (int i = 1; i <= n; ++i) { scanf( %lld%lld , &e[i].a, &e[i].b); e[i].c = e[i].a - e[i].b; } for (int i = 1; i <= n; ++i) ans += e[i].b; if (!b) return printf( %lld n , ans), 0; if (b == 1) { long long t = 0; for (int i = 1; i <= n; ++i) t = max(t, (e[i].a << a) - e[i].b); return printf( %lld n , ans + t), 0; } sort(e + 1, e + 1 + n); for (int i = 1; i <= n; ++i) if (e[i].a > e[i].b) vis[i] = 1; int cnt = 0; for (int i = 1; i <= b; ++i) if (vis[i]) ans += e[i].a - e[i].b, ++cnt; long long t = 0; for (int i = 1; i <= b; ++i) { if (vis[i]) t = max(t, (e[i].a << a) - e[i].a); else t = max(t, (e[i].a << a) - e[i].b); } long long ret = ans + t; t = 0; for (int i = b + 1; i <= n; ++i) t = max(t, (e[i].a << a) - e[i].b); if (cnt < b) ret = max(ret, ans + t); else ret = max(ret, ans + t - e[b].a + e[b].b); printf( %lld n , ret); } |
#include <bits/stdc++.h> using namespace std; const int inf = 1e9 + 10; int main() { int n; cin >> n; int an[n]; vector<int> p; vector<pair<int, int> > st; int i = 0; for (int a = 0; a < n * 2; a++) { char sy; cin >> sy; if (sy == + ) { p.push_back(i++); st.push_back({0, 1}); } else { int x; scanf( %d , &x); if (st.size() and x > st.back().first) { int su = 0; while (st.size() and st.back().first < x) { su += st.back().second; st.pop_back(); } su--; if (su) st.push_back({x, su}); an[p.back()] = x; p.pop_back(); } else { cout << NO ; return 0; } } } cout << YES n ; for (int a = 0; a < n; a++) printf( %d , an[a]); } |
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_carry #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire S,
input wire DI,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign COUT = (CIN & S) | (DI & ~S);
end else begin : USE_FPGA
MUXCY and_inst
(
.O (COUT),
.CI (CIN),
.DI (DI),
.S (S)
);
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:34:01 05/26/2014
// Design Name:
// Module Name: mccu
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mccu (op, func, z, clock, resetn, wpc, wir, wmem, wreg, iord, regrt, m2reg, aluc, shift,alusrca, alusrcb, pcsource, jal, sext, state);
input [5:0] op, func;
input z, clock, resetn;
output reg wpc, wir, wmem, wreg, iord, regrt, m2reg;
output reg [3:0] aluc;
output reg [1:0] alusrcb, pcsource;
output reg shift, alusrca, jal, sext;
output reg [2:0] state;
reg [2:0] next_state;
parameter [2:0] sif = 3'b000, // IF state
sid = 3'b001, // ID state
sexe = 3'b010, // EXE state
smem = 3'b011, // MEM state
swb = 3'b100; // WB state
wire r_type,i_add,i_sub,i_and,i_or,i_xor,i_sll,i_srl,i_sra,i_jr;
wire i_addi,i_andi,i_ori,i_xori,i_lw,i_sw,i_beq,i_bne,i_lui,i_j,i_jal;
and(r_type,~op[5],~op[4],~op[3],~op[2],~op[1],~op[0]);
and(i_add,r_type, func[5],~func[4],~func[3],~func[2],~func[1],~func[0]);
and(i_sub,r_type, func[5],~func[4],~func[3],~func[2], func[1],~func[0]);
and(i_and,r_type, func[5],~func[4],~func[3], func[2],~func[1],~func[0]);
and(i_or, r_type, func[5],~func[4],~func[3], func[2],~func[1], func[0]);
and(i_xor,r_type, func[5],~func[4],~func[3], func[2], func[1],~func[0]);
and(i_sll,r_type,~func[5],~func[4],~func[3],~func[2],~func[1],~func[0]);
and(i_srl,r_type,~func[5],~func[4],~func[3],~func[2], func[1],~func[0]);
and(i_sra,r_type,~func[5],~func[4],~func[3],~func[2], func[1], func[0]);
and(i_jr, r_type,~func[5],~func[4], func[3],~func[2],~func[1],~func[0]);
and(i_addi,~op[5],~op[4], op[3],~op[2],~op[1],~op[0]);
and(i_andi,~op[5],~op[4], op[3], op[2],~op[1],~op[0]);
and(i_ori, ~op[5],~op[4], op[3], op[2],~op[1], op[0]);
and(i_xori,~op[5],~op[4], op[3], op[2], op[1],~op[0]);
and(i_lw, op[5],~op[4],~op[3],~op[2], op[1], op[0]);
and(i_sw, op[5],~op[4], op[3],~op[2], op[1], op[0]);
and(i_beq, ~op[5],~op[4],~op[3], op[2],~op[1],~op[0]);
and(i_bne, ~op[5],~op[4],~op[3], op[2],~op[1], op[0]);
and(i_lui, ~op[5],~op[4], op[3], op[2], op[1], op[0]);
and(i_j, ~op[5],~op[4],~op[3],~op[2], op[1],~op[0]);
and(i_jal, ~op[5],~op[4],~op[3],~op[2], op[1], op[0]);
wire i_shift;
or (i_shift,i_sll,i_srl,i_sra);
always @* begin // control signals' default outputs:
wpc = 0; // do not write pc
wir = 0; // do not write ir
wmem = 0; // do not write memory
wreg = 0; // do not write register file
iord = 0; // select pc as memory address
aluc = 4'bx000; // ALU operation: add
alusrca = 0; // ALU input a: reg a or sa
alusrcb = 2'h0; // ALU input b: reg b
regrt = 0; // reg dest no: rd
m2reg = 0; // select reg c
shift = 0; // select reg a
pcsource = 2'h0; // select alu output
jal = 0; // not a jal
sext = 1; // sign extend
case (state)
//-------------------------------------------------------- IF:
sif: begin // IF state
wpc = 1; // write PC
wir = 1; // write IR
alusrca = 1; // PC
alusrcb = 2'h1; // 4
next_state = sid; // next state: ID
end
//-------------------------------------------------------- ID:
sid: begin // ID state
if (i_j) begin // j instruction
pcsource = 2'h3; // jump address
wpc = 1; // write PC
next_state = sif; // next state: IF
end else if (i_jal) begin // jal instruction
pcsource = 2'h3; // jump address
wpc = 1; // write PC
jal = 1; // reg no = 31
wreg = 1; // save PC+4
next_state = sif; // next state: IF
end else if (i_jr) begin // jr instruction
pcsource = 2'h2; // jump register
wpc = 1; // write PC
next_state = sif; // next state: IF
end else begin // other instructions
aluc = 4'bx000; // add
alusrca = 1; // PC
alusrcb = 2'h3; // branch offset
next_state = sexe; // next state: EXE
end
end
//-------------------------------------------------------- EXE:
sexe: begin // EXE state
aluc[3] = i_sra;
aluc[2] = i_sub | i_or | i_srl | i_sra | i_ori | i_lui;
aluc[1] = i_xor | i_sll | i_srl | i_sra | i_xori | i_beq | i_bne | i_lui;
aluc[0] = i_and | i_or | i_sll | i_srl | i_sra | i_andi | i_ori;
if (i_beq || i_bne) begin // beq or bne instruction
pcsource = 2'h1; // branch address
wpc = i_beq & z | i_bne & ~z; // write PC
next_state = sif; // next state: IF
end else begin // other instruction
if (i_lw || i_sw) begin // lw or sw instruction
alusrcb = 2'h2; // select offset
next_state = smem; // next state: MEM
end else begin // other instruction
if (i_shift) shift = 1; // shift instruction
if (i_addi || i_andi || i_ori || i_xori || i_lui) alusrcb = 2'h2; // select immediate
if (i_andi || i_ori || i_xori) sext=0; // 0-extend
next_state = swb; // next state: WB
end
end
end
//-------------------------------------------------------- MEM:
smem: begin // MEM state
iord = 1; // memory address = C
if (i_lw) begin
next_state = swb; // next state: WB
end else begin // store
wmem = 1; // write memory
next_state = sif; // next state: IF
end
end
//-------------------------------------------------------- WB:
swb: begin // WB state
if (i_lw) m2reg = 1; // select memory data
if (i_lw || i_addi || i_andi || i_ori || i_xori || i_lui) regrt = 1; // reg dest no: rt
wreg = 1; // write register file
next_state = sif; // next state: IF
end
//-------------------------------------------------------- END
default: begin
next_state = sif; // default state
end
endcase
end
always @ (posedge clock or negedge resetn) begin // state registers
if (resetn == 0) begin
state <= sif;
end else begin
state <= next_state;
end
end
endmodule |
#include <bits/stdc++.h> using namespace std; int arr[10] = {6, 2, 5, 5, 4, 5, 6, 3, 7, 6}; void solve() { int d, x; int a, b; cin >> a >> b; int ans = 0; for (int i = a; i <= b; i++) { x = i; while (x) { d = x % 10; x = x / 10; ans += arr[d]; } } cout << ans << endl; } int main() { int t = 1; while (t--) { solve(); } } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: cpx_databuf_ca2.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module cpx_databuf_ca2(/*AUTOARG*/
// Outputs
sctag_cpx_data_buf_pa,
// Inputs
sctag_cpx_data_pa
);
output [144:0] sctag_cpx_data_buf_pa;
input [144:0] sctag_cpx_data_pa;
assign sctag_cpx_data_buf_pa = sctag_cpx_data_pa;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c, n; cin >> a >> b >> c >> n; int tot = n - a - b + c; if (tot <= 0 || a < c || b < c) return 0 * puts( -1 ); cout << tot << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; struct Node { vector<Node*> next; Node() : next(26, nullptr) {} }; Node* root = new Node; void insert(string& s, int i, Node* c) { if (i >= s.length()) return; if (c->next[s[i] - a ] == nullptr) { c->next[s[i] - a ] = new Node; } insert(s, i + 1, c->next[s[i] - a ]); } bool traverseWin(Node* c) { bool curWin = false; for (auto n : c->next) if (n != nullptr) { if (!traverseWin(n)) curWin = true; } return curWin; } bool traverseLose(Node* c) { bool curLose = false; int i = 0; for (auto n : c->next) if (n != nullptr) { ++i; if (!traverseLose(n)) curLose = true; } return curLose || (i == 0); } int main(int, char**) { std::ios::sync_with_stdio(false); int n, k; cin >> n >> k; for (int i = 0; i < n; ++i) { string s; cin >> s; insert(s, 0, root); } bool w = traverseWin(root); bool l = traverseLose(root); if (!w) { cout << Second << endl; } else { if (!l) { cout << (k % 2 == 0 ? Second : First ) << endl; } else { cout << First << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { if ((a == 0) || (b == 0)) return a + b; return gcd(b, a % b); } long long pow_mod(long long a, long long b) { long long res = 1; while (b) { if (b & 1) res = (res * a) % 1000000007; a = (a * a) % 1000000007; b >>= 1; } return (res % 1000000007); } long long pow_2(long long a, long long b) { long long res = 1; while (b) { if (b & 1) res = (res * a); a = (a * a); b >>= 1; } return res; } bool isPrime(long long a) { for (int i = 3; (i * i) <= a; i += 2) { if ((a % i) == 0) return false; } if ((a != 2) && ((a % 2) == 0)) return false; if (a == 1) return false; return true; } string con_ll_to_str(int a) { stringstream mystr; mystr << a; return mystr.str(); } long long con_str_to_ll(string st) { long long numb = 0; int len = st.size(), i, j = 0; for (i = len - 1; i >= 0; i--) { numb += (pow_2(10, j) * (st[i] - 0 )); j++; } return numb; } long long baseno_to_decimal(string st, long long basee) { long long i = 0, j, anss = 0; for (j = (int)st.length() - 1; j >= 0; j--) { anss += (st[j] - 0 ) * pow_2(basee, i); i++; } return anss; } string decimal_to_string(long long num, long long basee) { long long i = 0, j, opop; string anss = ; vector<string> stri; stri.push_back( 0 ); stri.push_back( 1 ); stri.push_back( 2 ); stri.push_back( 3 ); stri.push_back( 4 ); stri.push_back( 5 ); stri.push_back( 6 ); stri.push_back( 7 ); stri.push_back( 8 ); stri.push_back( 9 ); stri.push_back( A ); stri.push_back( B ); stri.push_back( C ); stri.push_back( D ); stri.push_back( E ); stri.push_back( F ); if (num == 0) { return 0 ; } while (num) { opop = num % basee; anss += stri[opop]; num /= basee; } reverse(anss.begin(), anss.end()); return anss; } const int dx[] = {0, 1, 1, 1, 0, -1, -1, -1}; const int dy[] = {1, 1, 0, -1, -1, -1, 0, 1}; long long arr[100010]; int main() { ios_base::sync_with_stdio(false); cin.tie(0); long long T, N, K, i, j; string st = ; cin >> N >> K; if (K > N) { cout << -1 ; return 0; } if (K == 1 && N > 1) { cout << -1 ; return 0; } if (N == 1) { cout << a ; return 0; } long long opop = (N - K + 2); for (i = 1; i <= opop; i++) { if (i % 2) { st.push_back( a ); } else { st.push_back( b ); } } long long po = st.length(), pu = 0; for (i = po + 1; i <= N; i++) { st.push_back( c + pu); pu++; } cout << st; return 0; } |
#include <bits/stdc++.h> using namespace std; int a[210][210], n, m, s[110]; bool dop(int x, int y) { return (x >= 0 && y >= 0 && x < 2 * n && y < 2 * m); } void dfs(int x, int y, int cur) { s[cur]++; a[x][y] = cur; if (dop(x + 2, y) && a[x + 1][y] != -1 && a[x + 2][y] != cur) { dfs(x + 2, y, cur); } if (dop(x - 2, y) && a[x - 1][y] != -1 && a[x - 2][y] != cur) { dfs(x - 2, y, cur); } if (dop(x, y + 2) && a[x][y + 1] != -1 && a[x][y + 2] != cur) { dfs(x, y + 2, cur); } if (dop(x, y - 2) && a[x][y - 1] != -1 && a[x][y - 2] != cur) { dfs(x, y - 2, cur); } } void qsort(int first, int last) { int i = first, j = last, x = s[(i + j) / 2]; do { while (s[i] < x) { i++; } while (s[j] > x) { j--; } if (i <= j) { if (i != j) { swap(s[i], s[j]); } i++; j--; } } while (i <= j); if (i < last) { qsort(i, last); } if (j > first) { qsort(first, j); } } int main() { int x1, x2, y1, y2, t, i, j; cin >> n >> m >> t; for (i = 0; i < n * 2; i++) { for (j = 0; j < m * 2; j++) { a[i][j] = 0; } } for (i = 0; i < t; i++) { cin >> x1 >> y1 >> x2 >> y2; if (x1 == x2) { if (y1 > y2) { swap(y1, y2); } for (j = y1 * 2; j < y2 * 2; j++) { a[x1 * 2][j] = -1; } } else { if (x1 > x2) { swap(x1, x2); } for (j = x1 * 2; j < x2 * 2; j++) { a[j][y1 * 2] = -1; } } } for (i = 0; i < 100; i++) { s[i] = 0; } int curcol = 1; for (i = 1; i < 2 * n; i += 2) { for (j = 1; j < 2 * m; j += 2) { if (a[i][j] == 0) { dfs(i, j, curcol); curcol++; } } } qsort(1, curcol - 1); for (i = 1; i < curcol; i++) { cout << s[i] << ; } return 0; } |
`timescale 1ns / 1ps
module ps2_TB;
reg Rx;
reg CLKOUT;
ps2 uut(.CLKOUT(CLKOUT),.Rx(Rx));
always
begin
CLKOUT =1'b1;
#1;
CLKOUT =1'b0;
#1;
end
initial
begin
Rx=1;
#10;
Rx=0;
#2;
Rx=0;//1
#2;
Rx=0;
#2;
Rx=0;
#2;
Rx=1;
#2;
Rx=1;
#2;
Rx=1;
#2;
Rx=0;
#2;
Rx=0;//8
#2;
Rx=1;
#2;
Rx=1;
#2;
Rx=1;
#10;
// Otro
Rx=0;
#2;
Rx=0;//1
#2;
Rx=0;
#2;
Rx=1;
#2;
Rx=1;
#2;
Rx=0;
#2;
Rx=0;
#2;
Rx=1;
#2;
Rx=0;//8
#2;
Rx=1;
#2;
Rx=1;
#2;
Rx=1;
#10;
// Seguidos
Rx=0;
#2;
Rx=1;//1
#2;
Rx=0;
#2;
Rx=0;
#2;
Rx=1;
#2;
Rx=0;
#2;
Rx=0;
#2;
Rx=1;
#2;
Rx=1;//8
#2;
Rx=1;
#2;
// Continuación
Rx=0;
#2;
Rx=1;//1
#2;
Rx=1;
#2;
Rx=1;
#2;
Rx=0;
#2;
Rx=0;
#2;
Rx=0;
#2;
Rx=0;
#2;
Rx=0;//8
#2;
Rx=1;
#2;
// Continuación
Rx=0;
#2;
Rx=0;//1
#2;
Rx=0;
#2;
Rx=1;
#2;
Rx=1;
#2;
Rx=0;
#2;
Rx=0;
#2;
Rx=1;
#2;
Rx=0;//8
#2;
Rx=1;
#2;
// Continuación
Rx=0;
#2;
Rx=0;//1
#2;
Rx=0;
#2;
Rx=1;
#2;
Rx=1;
#2;
Rx=0;
#2;
Rx=0;
#2;
Rx=1;
#2;
Rx=0;//8
#2;
Rx=1;
#2;
end
initial begin: TEST_CASE
$dumpfile("ps2_TB.vcd");
$dumpvars(-1, uut);
#(400) $finish;
end
endmodule //
|
#include <bits/stdc++.h> using namespace std; int n, q; string a[50]; string b[50]; int dfs(char c, int dep) { if (dep == n - 1) { return 1; } int ans = 0; for (long long int i = 1; i <= q; i++) { if (b[i][0] == c) { ans += dfs(a[i][0], dep + 1); } } return ans; } int main() { ios::sync_with_stdio(0); cin >> n >> q; for (long long int i = 1; i <= q; i++) { cin >> a[i] >> b[i]; } cout << dfs( a , 0); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, d; while (cin >> n >> d) { int A[n], ans = 0; for (int i = 0; i < n; i++) cin >> A[i]; for (int i = 1; i < n; i++) { if (A[i] <= A[i - 1]) { int rest = A[i - 1] - A[i], cnt = (rest / d) + 1; A[i] += cnt * d; ans += cnt; } } cout << ans << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, k; int dist[200002]; vector<pair<int, int>> v[200002]; vector<int> nes[200002]; char s[200002]; vector<string> ans; void dfs(int d) { if (ans.size() >= k) return; if (d > n) { ans.push_back(s); return; } for (auto i : nes[d]) { s[i] = 1 ; dfs(d + 1); s[i] = 0 ; } } int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n >> m >> k; for (int i = 0; i < m; ++i) { int a, b; cin >> a >> b; v[a].push_back({b, i}); v[b].push_back({a, i}); } queue<int> q; q.push(1); dist[1] = 1; while (q.size()) { int x = q.front(); q.pop(); for (auto i : v[x]) { if (dist[i.first]) continue; dist[i.first] = dist[x] + 1; q.push(i.first); } } for (int i = 2; i <= n; ++i) { for (auto j : v[i]) { if (dist[j.first] + 1 == dist[i]) nes[i].push_back(j.second); } } fill(s, s + m, 0 ); dfs(2); cout << ans.size() << n ; for (auto i : ans) cout << i << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int sum(int a) { int sum = a; while (a) { sum += a % 10; a /= 10; } return sum; } int main() { vector<int> v; int a; cin >> a; int b = a; while (a) { int check = sum(a); if (check == b) v.push_back(a); else if (check + 100 < b) break; a--; } cout << v.size() << endl; reverse(v.begin(), v.end()); for (auto i : v) { cout << i << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> inline T BM(T p, T e, T M) { long long int ret = 1; for (; e > 0; e >>= 1) { if (e & 1) ret = (ret * p) % M; p = (p * p) % M; } return (T)ret; } template <class T> inline T gcd(T a, T b) { if (b == 0) return a; return gcd(b, a % b); } template <class T> inline T MDINV(T a, T M) { return BM(a, M - 2, M); } template <class T> inline T PW(T p, T e) { long long int ret = 1; for (; e > 0; e >>= 1) { if (e & 1) ret = (ret * p); p = (p * p); } return (T)ret; } template <class T> string NTS(T Number) { stringstream ss; ss << Number; return ss.str(); } template <class T> T stringtonumber(const string &Text) { istringstream ss(Text); T result; return ss >> result ? result : 0; } template <class T> bool ISLEFT(T a, T b, T c) { if (((a.first - b.first) * (b.second - c.second) - (b.first - c.first) * (a.second - b.second)) < 0.0) return 1; else return 0; } char a[10009]; int z[10009]; char ch[5000 + 2]; int ar[5000 + 2][5000 + 2]; int res[5000 + 2][5000 + 2]; void zalgo() { int l, r; l = r = 0; z[0] = strlen(a); for (int i = 1; i < z[0]; i++) { if (i > r) { l = r = i; for (int j = i; j < z[0]; j++) { if (a[j - i] != a[j]) break; else r = j; } if (a[i] != a[0]) z[i] = 0; else z[i] = r - l + 1; } else { int k = i - l; if (z[k] < r - i + 1) { z[i] = z[k]; } else { l = i; for (int j = r + 1; j < z[0]; j++) { if (a[j - l] != a[j]) break; else r = j; } z[i] = r - l + 1; } } } } int dp[5009][5009]; void update(int x1, int y1, int val) { while (y1 <= 5002) { dp[x1][y1] = (dp[x1][y1] + val) % 1000000007; y1 += (y1 & -y1); } } int query(int x1, int y1) { int sum1 = 0; while (y1 > 0) { sum1 = (sum1 + dp[x1][y1]) % 1000000007; y1 -= (y1 & -y1); } return sum1; } int main() { int n; scanf( %d , &n); scanf( %s , ch + 1); for (int i = 1; i <= n; i++) { int sz = 0; for (int j = i; j <= n; j++) { a[sz++] = ch[j]; } int len = sz; for (int j = i + 1; j <= n; j++) { a[sz++] = ch[j]; } a[sz] = 0 ; zalgo(); for (int j = i + 1; j <= n; j++) { ar[i][j] = z[len + (j - i - 1)]; } } res[0][0] = 1; for (int i = 1; i <= n; i++) { if (ch[i] == 0 ) continue; for (int j = i; j <= n; j++) { if (i == 1) res[i][j] = 1; else { int ga = j - i; int x = i - 1 - ga; int y = i - 1; x = max(1, x); if (y - x == ga) { int in = x; int mil = ar[x][i]; if (mil < (ga + 1)) { if (ch[x + mil] < ch[i + mil]) { in = x - 1; } } int sum = query(y, y) - query(y, in); if (sum < 0) sum += 1000000007; res[i][j] = sum; } else { int sum = query(y, y) - query(y, x - 1); if (sum < 0) sum += 1000000007; res[i][j] = sum; } } update(j, i, res[i][j]); } } int su = 0; for (int i = 1; i <= n; i++) { su = (su + res[i][n]) % 1000000007; } printf( %d n , su); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 4e5 + 10, INF = 1e9; int l[N], r[N], ps[N]; map<int, int> mp; int cnt, seg[4 * N], lazy[4 * N]; inline void shift(int id) { seg[2 * id] += lazy[id]; lazy[2 * id] += lazy[id]; seg[2 * id + 1] += lazy[id]; lazy[2 * id + 1] += lazy[id]; lazy[id] = 0; return; } void add(int id, int L, int R, int s = 0, int e = cnt) { if (L <= s && e <= R) { seg[id]++; lazy[id]++; return; } if (L >= e || s >= R) return; int mid = (s + e) / 2; shift(id); add(2 * id, L, R, s, mid); add(2 * id + 1, L, R, mid, e); seg[id] = min(seg[2 * id], seg[2 * id + 1]); return; } int get(int id, int L, int R, int s = 0, int e = cnt) { if (L <= s && e <= R) return seg[id]; if (L >= e || s >= R) return INF; int mid = (s + e) / 2; shift(id); return min(get(2 * id, L, R, s, mid), get(2 * id + 1, L, R, mid, e)); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n; cin >> n; for (int i = 0; i < n; i++) { cin >> l[i] >> r[i]; r[i]++; mp[l[i]] = mp[r[i]] = 0; } for (auto X : mp) mp[X.first] = cnt++; for (int i = 0; i < n; i++) { l[i] = mp[l[i]]; r[i] = mp[r[i]]; } for (int i = 0; i < n; i++) add(1, l[i], r[i]); for (int i = 0; i < n; i++) { int mn = get(1, l[i], r[i]); if (mn > 1) return cout << i + 1 << endl, 0; } return cout << -1 << endl, 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A211O_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__A211O_PP_BLACKBOX_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a211o (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A211O_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; long long tg, ans[22]; int state[22][22], fa_inc[22][22], fa_n4[22][22], fa_n7[22][22]; int t, cs = 0, dg[22]; int main() { scanf( %d , &t); for (cs = 1; cs <= t; ++cs) { scanf( %I64d , &tg); for (int i = 0; i < 19; ++i) dg[i] = tg % 10, tg /= 10; state[0][0] = cs; for (int i = 0; i < 19; ++i) { for (int j = 0; j < 10; ++j) { if (state[i][j] != cs) continue; for (int n4 = 0; n4 <= 6; ++n4) { for (int n7 = 0; n7 + n4 <= 6; ++n7) { int nj = (j + n4 * 4 + n7 * 7); if (nj % 10 == dg[i]) { state[i + 1][nj / 10] = cs; fa_inc[i + 1][nj / 10] = j; fa_n4[i + 1][nj / 10] = n4; fa_n7[i + 1][nj / 10] = n7; } } } } } if (state[19][0] == cs) { for (int i = 0; i < 6; ++i) ans[i] = 0; for (int i = 19, j = 0; i > 0; --i) { int n4 = fa_n4[i][j], n7 = fa_n7[i][j]; for (int pos = 0; pos < 6; ++pos) { ans[pos] *= 10; if (pos < n4) ans[pos] += 4; else if (pos < n4 + n7) ans[pos] += 7; } j = fa_inc[i][j]; } for (int i = 0; i < 5; ++i) printf( %I64d , ans[i]); printf( %I64d n , ans[5]); } else puts( -1 ); } return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
/*verilator no_inline_module*/ // So we'll get hiearachy we can test
input clk;
sub sub (/*AUTOINST*/
// Inputs
.clk (clk));
endmodule
module sub (/*AUTOARG*/
// Inputs
clk
);
input clk;
/*verilator no_inline_module*/ // So we'll get hiearachy we can test
integer cyc=0;
reg [127:0] save128;
reg [47:0] save48;
reg [1:0] save2;
reg [255:0] cycdone; // Make sure each cycle executes exactly once
reg [31:0] vec[2:1][2:1];
real r;
string s,s2;
string si;
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d\n",$time, cyc);
`endif
si = "siimmed";
cyc <= cyc + 1;
if (cycdone[cyc[7:0]]) $stop;
cycdone[cyc[7:0]] <= '1;
if (cyc==0) begin
// Setup
save128 <= 128'hc77bb9b3784ea0914afe43fb79d7b71e;
save48 <= 48'h4afe43fb79d7;
save2 <= 2'b10;
vec[1][1] <= 32'h0101;
vec[1][2] <= 32'h0102;
vec[2][1] <= 32'h0201;
vec[2][2] <= 32'h0202;
r <= 1.234;
s <= "hello";
end
if (cyc==1) begin
if ($test$plusargs("save_restore")!=0) begin
// Don't allow the restored model to run from time 0, it must run from a restore
$write("%%Error: didn't really restore\n");
$stop;
end
end
else if (cyc==99) begin
if (save128 !== 128'hc77bb9b3784ea0914afe43fb79d7b71e) $stop;
if (save48 !== 48'h4afe43fb79d7) $stop;
if (save2 !== 2'b10) $stop;
if (cycdone !== {{(256-99){1'b0}}, {99{1'b1}}}) $stop;
if (vec[1][1] !== 32'h0101) $stop;
if (vec[1][2] !== 32'h0102) $stop;
if (vec[2][1] !== 32'h0201) $stop;
if (vec[2][2] !== 32'h0202) $stop;
if (r != 1.234) $stop;
$display("%s",s);
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int Maxn = 200005; struct M { int val, pos; }; M a[Maxn], b[Maxn]; int idx[Maxn], idy[Maxn], Nx[Maxn], Ny[Maxn]; int read() { int sum = 0, t = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) t = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { sum = sum * 10 + c - 0 ; c = getchar(); } return sum * t; } bool cmp(M x, M y) { return (x.val < y.val || (x.val == y.val && b[x.pos].val < b[y.pos].val)); } long long C2(long long x) { return 1ll * x * (x - 1) / 2; } int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; ++i) { a[i].val = read(), b[i].val = read(); a[i].pos = b[i].pos = i; } sort(a + 1, a + n + 1, cmp); int cnt = 0, same = 1; long long res = 0; a[0].val = b[0].val = -0x3f3f3f3f; cnt = 0; for (int i = 1; i <= n; ++i) { if (a[i].val != a[i - 1].val) cnt++, res += C2(same), same = 1; else { if (b[a[i].pos].val == b[a[i - 1].pos].val) same++; else res += C2(same), same = 1; } idx[a[i].pos] = cnt; } res += C2(same); sort(b + 1, b + n + 1, cmp); cnt = 0; for (int i = 1; i <= n; ++i) { if (b[i].val != b[i - 1].val) cnt++; idy[b[i].pos] = cnt; } for (int i = 1; i <= n; ++i) { Nx[idx[i]]++; Ny[idy[i]]++; } long long ans = 0; for (int i = 1; i <= n; ++i) { ans += C2(Nx[i]) + C2(Ny[i]); } ans -= res; printf( %lld , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> inline bool Up(T &a, const T &b) { if (a < b) { a = b; return true; } return false; } template <class T> inline bool Down(T &a, const T &b) { if (a > b) { a = b; return true; } return false; } const int MAXN = 100023; int N, M, color[MAXN], ans[MAXN]; vector<int> fir[MAXN], side[2]; int tot = 2; void BFS() { static int Q[MAXN]; int head = 0, tail = 0; memset(color, -1, sizeof(color)); for (int S = (1); S <= (N); ++S) if (color[S] == -1) for (color[S] = 0, Q[++tail] = S; head < tail;) { int x = Q[++head], y; side[color[x]].push_back(x); for (vector<int>::iterator itr(fir[x].begin()); itr != fir[x].end(); ++itr) if (color[y = *itr] == -1) { Q[++tail] = y; color[y] = color[x] ^ 1; } } } void Print() { for (int c = (0); c <= (1); ++c) for (vector<int>::iterator itr(side[c].begin()); itr != side[c].end(); ++itr) { int x = *itr; if (!ans[x]) ans[x] = ++tot; } puts( YES ); for (int i = (1); i <= (N); ++i) printf( %d%c , ans[i] / 3, i == N ? n : ); } void Paint(int x) { static int forbid[MAXN]; memset(forbid, 0, sizeof(forbid)); for (vector<int>::iterator itr(fir[x].begin()); itr != fir[x].end(); ++itr) forbid[*itr] = 1; int cnt = 0; ans[x] = ++tot; for (vector<int>::iterator itr(side[color[x] ^ 1].begin()); itr != side[color[x] ^ 1].end(); ++itr) { int y = *itr; if (!ans[y] && !forbid[y]) { ans[y] = ++tot; if (++cnt == 2) break; } } } int main() { memset(ans, 0, sizeof(ans)); scanf( %d %d , &N, &M); for (int i = (1); i <= (M); ++i) { int a, b; scanf( %d %d , &a, &b); fir[a].push_back(b); fir[b].push_back(a); } BFS(); if (side[0].size() % 3 == 0) { Print(); return 0; } if (side[0].size() % 3 == 2) { side[0].swap(side[1]); for (int i = (1); i <= (N); ++i) color[i] ^= 1; } for (vector<int>::iterator itr(side[0].begin()); itr != side[0].end(); ++itr) { int x = *itr; if (fir[x].size() + 2 <= side[1].size()) { Paint(x); Print(); return 0; } } int cnt = 0; for (vector<int>::iterator itr(side[1].begin()); itr != side[1].end(); ++itr) { int x = *itr; if (fir[x].size() + 2 <= side[0].size()) { Paint(x); if (++cnt == 2) { Print(); return 0; } } } puts( NO ); return 0; } |
#include <bits/stdc++.h> using namespace std; long long gcd(long long x, long long y) { return x ? gcd(y % x, x) : y; } int N; int a[2010], b[2010], c[2010]; vector<pair<long long, long long> > v; long long func(void) { int i, j; int ans = 0; i = 0; while (i < v.size()) { for (j = i; j < v.size(); j++) if (v[j] != v[i]) break; int d = j - i; ans += d * (d - 1) / 2; i = j; } return ans; } int main(void) { int i, j; cin >> N; for ((i) = 0; (i) < (int)(N); (i)++) scanf( %d%d%d , &a[i], &b[i], &c[i]); long long ans = 0; int zero = 0; for ((i) = 0; (i) < (int)(N); (i)++) if (c[i] == 0) zero++; if (zero == 2) ans += N - 2; for ((i) = 0; (i) < (int)(N); (i)++) if (c[i] != 0) { v.clear(); long long px = a[i] * a[i] + b[i] * b[i]; long long qx = a[i] * c[i]; long long py = a[i] * a[i] + b[i] * b[i]; long long qy = b[i] * c[i]; for ((j) = 0; (j) < (int)(i); (j)++) if (c[j] != 0) { long long px2 = a[j] * a[j] + b[j] * b[j]; long long qx2 = a[j] * c[j]; long long py2 = a[j] * a[j] + b[j] * b[j]; long long qy2 = b[j] * c[j]; long long rx = px * px2; long long sx = qx * px2 - px * qx2; long long ry = py * py2; long long sy = qy * py2 - py * qy2; long long g = gcd(((sx) > 0 ? (sx) : -(sx)), ((sy) > 0 ? (sy) : -(sy))); sx /= g; sy /= g; if (sx < 0 || (sx == 0 && sy < 0)) { sx = -sx; sy = -sy; } v.push_back(make_pair(sx, sy)); } sort(v.begin(), v.end()); long long tmp = func(); ans += tmp; } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int lsone(int n) { return (n & -n); } void mult(long long int a[25][25], long long int b[25][25], long long int c[25][25], int m, int n, int p) { for (int i = 1; i <= m; i++) { for (int j = 1; j <= p; j++) { c[i][j] = 0; for (int k = 1; k <= n; k++) { c[i][j] += (a[i][k] * b[k][j]) % 1000000007; c[i][j] %= 1000000007; } } } } void mat_pow(long long int a[25][25], long long int c[25][25], int n, long long int p) { if (p == 0) { for (int i = 1; i <= n; i++) c[i][i] = 1; } else if (p == 1) { for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) c[i][j] = a[i][j]; } } else { long long int d[25][25]; mat_pow(a, d, n, p / 2); if (p % 2) { long long int e[25][25]; mult(d, d, e, n, n, n); mult(e, a, c, n, n, n); } else { mult(d, d, c, n, n, n); } } } long long int pow1(long long int a, long long int b) { if (b == 0) return 1ll; else if (b == 1) return a; else { long long int x = pow1(a, b / 2); x *= x; x %= 1000000007; if (b % 2) { x *= a; x %= 1000000007; } return x; } } int n, ans[110000]; int s(int y) { int ans = 0; while (y) { y /= 10; ans++; } return ans; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; ans[1] = 1; for (int i = 2; i <= 1e5; i++) { ans[i] = ans[i - 1] * 10; ans[i] %= 210; } cin >> n; int req = (210 - ans[n]) % 210; if (n <= 2) { cout << -1 << n ; } else if (n == 3) cout << 210 << n ; else { int numdig = s(req); cout << 1; for (int i = 0; i < n - numdig - 1; i++) cout << 0; cout << req << n ; } return 0; } |
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title :
// File :
// Author : Jim MacLeod
// Created : 01-Dec-2011
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module flt_div
(
input clk,
input rstn,
input [63:0] numer_denom,
output [31:0] div_result
);
wire [31:0] numer_d_fp;
wire [31:0] quot_fp;
// Float Divide (Seven Clock Cycles).
flt_recip u0_flt_recip(.clk(clk), .denom(numer_denom[31:0]), .recip(quot_fp));
gen_pipe #(32, 6) u0_gen_pipe(.clk(clk), .din(numer_denom[63:32]), .dout(numer_d_fp));
flt_mult u2_flt_mult(clk, rstn, numer_d_fp, quot_fp, div_result);
endmodule
|
/*
* Copyright (c) 2015-2018 The Ultiparc Project. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* Long integer division
*/
`include "uparc_cpu_config.vh"
`include "uparc_cpu_common.vh"
`include "uparc_cpu_const.vh"
/* Division */
module uparc_long_idiv(
clk,
nrst,
dividend,
divider,
start,
signd,
ready,
remquot
);
input wire clk;
input wire nrst;
input wire [`UPARC_REG_WIDTH-1:0] dividend;
input wire [`UPARC_REG_WIDTH-1:0] divider;
input wire start;
input wire signd;
output wire ready;
output wire [2*`UPARC_REG_WIDTH-1:0] remquot;
/* Local registers and wires */
reg [2*`UPARC_REG_WIDTH-1:0] qr;
reg [5:0] nbit;
wire [`UPARC_REG_WIDTH:0] diff;
reg [`UPARC_REG_WIDTH-1:0] abs_divider;
assign ready = !(|nbit) && !start;
/* Result: remainder and quotient */
assign remquot[2*`UPARC_REG_WIDTH-1:`UPARC_REG_WIDTH] =
(signd && dividend[`UPARC_REG_WIDTH-1]) ?
-qr[2*`UPARC_REG_WIDTH-1:`UPARC_REG_WIDTH] :
qr[2*`UPARC_REG_WIDTH-1:`UPARC_REG_WIDTH];
assign remquot[`UPARC_REG_WIDTH-1:0] =
(signd && (dividend[`UPARC_REG_WIDTH-1] ^ divider[`UPARC_REG_WIDTH-1])) ?
-qr[`UPARC_REG_WIDTH-1:0] : qr[`UPARC_REG_WIDTH-1:0];
/* Difference between divider and working portion of dividend */
assign diff = qr[2*`UPARC_REG_WIDTH-1:`UPARC_REG_WIDTH-1] - { 1'b0, abs_divider };
always @(posedge clk or negedge nrst)
begin
if(!nrst)
begin
qr <= {(2*`UPARC_REG_WIDTH){1'b0}};
nbit <= 6'b0;
abs_divider <= {(`UPARC_REG_WIDTH){1'b0}};
end
else if(start)
begin
if(!(|dividend) || !(|divider))
begin
qr <= {(2*`UPARC_REG_WIDTH){1'b0}};
nbit <= 6'b0;
end
else
begin
nbit <= 6'd`UPARC_REG_WIDTH;
qr <= { {(`UPARC_REG_WIDTH){1'b0}}, signd && dividend[`UPARC_REG_WIDTH-1] ?
-dividend : dividend };
abs_divider <= signd && divider[`UPARC_REG_WIDTH-1] ? -divider : divider;
end
end
else if(|nbit)
begin
nbit <= nbit - 1'b1;
if(diff[`UPARC_REG_WIDTH])
qr <= { qr[2*`UPARC_REG_WIDTH-2:0], 1'b0 };
else
qr <= { diff[`UPARC_REG_WIDTH-1:0], qr[`UPARC_REG_WIDTH-2:0], 1'b1 };
end
end
endmodule /* uparc_long_idiv */
|
#include <bits/stdc++.h> using namespace std; namespace jumpmelon { const int MAXN = 52; int A[MAXN + 1], B[MAXN + 1]; bool F[MAXN + 1]; void work() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &A[i]); vector<vector<int>> Ans; while (1) { memset(F + 1, 0, sizeof(bool[n])); for (int i = 1; i < n; i++) if (A[i] + 1 == A[i + 1]) F[i] = 1; int x = 0, y = 0; for (int i = 1; i <= n; i++) if (!F[i]) for (int j = 1; j < i; j++) if (A[j] == A[i] + 1) { x = i; y = j; } if (x == 0 && y == 0) break; int p = x; while (p > 1 && F[p - 1]) p--; vector<int> D; if (y > 1) D.push_back(y - 1); D.push_back(p - y); D.push_back(x - p + 1); if (x < n) D.push_back(n - x); Ans.push_back(D); int l = 1, r = n; for (int v : D) { r -= v; for (int i = 1; i <= v; i++) B[r + i] = A[l + i - 1]; l += v; } memcpy(A + 1, B + 1, sizeof(int[n])); } printf( %d n , (int)Ans.size()); for (auto &&D : Ans) { printf( %d , (int)D.size()); for (int v : D) printf( %d , v); putchar( n ); } } } // namespace jumpmelon int main() { jumpmelon::work(); return 0; } |
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// This module implements exponent extraction and returns the adjusted exponent as integer.
// Adjusted means that we remove the bias implicit in the FP numbers. That is exp=127 that represents exponent of 0
// is returned as 0.
module acl_fp_extract_exp( clock, resetn, enable, valid_in, valid_out, stall_in, stall_out, dataa, result);
parameter WIDTH = 32;
parameter HIGH_CAPACITY = 1;
input clock, resetn;
input enable, valid_in, stall_in;
output valid_out, stall_out;
input [WIDTH-1:0] dataa;
output [31:0] result;
// Simply extract the mantissa and at the most shift it to the right by one position.
reg c1_valid;
wire c1_stall;
wire c1_enable = (HIGH_CAPACITY == 1) ? (~c1_valid | ~c1_stall) : enable;
assign stall_out = c1_valid & c1_stall;
reg [31:0] c1_exponent;
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c1_valid <= 1'b0;
c1_exponent <= 32'dx;
end
else if (c1_enable)
begin
c1_valid <= valid_in;
if (WIDTH==32)
begin
if ((~(|dataa[WIDTH-2:WIDTH-9])) || (&dataa[WIDTH-2:WIDTH-9]))
begin
c1_exponent <= 32'h7fffffff;
end
else
begin
c1_exponent <= {1'b0, dataa[WIDTH-2:WIDTH-9]} - 9'd127;
end
end
else
begin
if ((~(|dataa[WIDTH-2:WIDTH-12])) || (&dataa[WIDTH-2:WIDTH-12]))
begin
c1_exponent <= 32'h7fffffff;
end
else
begin
c1_exponent <= {1'b0, dataa[WIDTH-2:WIDTH-12]} - 12'd1023;
end
end
end
end
assign c1_stall = stall_in;
assign valid_out = c1_valid;
assign result = c1_exponent;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, t; cin >> n >> t; if (t == 10) { if (n == 1) { cout << -1 ; } else { for (int i = 0; i < n - 1; i++) { cout << 1 ; } cout << 0 ; } } else { for (int i = 0; i < n; i++) { cout << t; } cout << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename item> item abs(item i) { if (i < 0) i = -i; return i; } char *s; int n; int pos; int main() { cin >> n; cin >> pos; s = new char[n + 2]; cin >> s + 1; int cnt = 0; if (n == 1) { cout << 0; return 0; } if (n % 2 == 1 and pos == n / 2 + 1) pos++, cnt++; if (pos > n / 2) pos = n - pos + 1; int last = n / 2, fst = 1; while (fst < n - fst + 1 and s[fst] == s[n - fst + 1]) fst++; while (last > 0 and s[last] == s[n + 1 - last]) last--; if (pos >= fst and pos <= last) { int a = pos - fst, b = last - pos; cnt += 2 * (min(a, b)) + max(a, b); } else if (pos >= fst and pos >= last) cnt += pos - min(fst, last); else if (pos <= last and pos <= fst) cnt += max(fst, last) - pos; for (int i = 1; i <= n / 2; i++) { int cmp = n - i + 1; if (s[i] > s[cmp]) swap(s[i], s[cmp]); int a = abs((int)(s[i] - s[cmp])), b = z - s[cmp] + s[i] - a + 1; cnt += min(a, b); } cout << cnt; } |
#include <bits/stdc++.h> using namespace std; const int N = 300000 + 7; int n, q; long long val[N]; struct edge { int to, nex; long long wei; } e[N << 1]; int fir[N], eid; int siz[N], dep[N], fa[N], son[N], ltp[N]; long long faw[N]; int dfn[N], inx; long long f[N], g[N]; long long bit[N]; void addedge(int u, int v, int w); void dfs1(int s); void dfs2(int s); void dfs3(int s, long long up); void build(); int lca(int x, int y); long long get(int x, int z); void add(int i, long long v); long long sum(int i); int main() { scanf( %d%d , &n, &q); for (int i = 1; i <= n; ++i) scanf( %lld , val + i); for (int i = 1, u, v, w; i < n; ++i) scanf( %d%d%d , &u, &v, &w), addedge(u, v, w), addedge(v, u, w); dfs1(1); ltp[1] = 1; dfs2(1); dfs3(1, 0); build(); for (int x, y, z; q; --q) { scanf( %d%d , &x, &y); if (x == y) printf( %lld n , g[x]); else z = lca(x, y), printf( %lld n , g[z] + get(x, z) + get(y, z)); } return 0; } void addedge(int u, int v, int w) { e[++eid] = (edge){v, fir[u], 1ll * w}; fir[u] = eid; } void dfs1(int s) { siz[s] = 1; f[s] = val[s]; for (int i = fir[s]; i; i = e[i].nex) { if (e[i].to == fa[s]) continue; fa[e[i].to] = s; faw[e[i].to] = e[i].wei; dep[e[i].to] = dep[s] + 1; dfs1(e[i].to); siz[s] += siz[e[i].to]; son[s] = siz[e[i].to] > siz[son[s]] ? e[i].to : son[s]; f[s] += max(0ll, f[e[i].to] - 2 * e[i].wei); } } void dfs2(int s) { dfn[s] = ++inx; if (!son[s]) return; ltp[son[s]] = ltp[s]; dfs2(son[s]); for (int i = fir[s]; i; i = e[i].nex) if (e[i].to != fa[s] && e[i].to != son[s]) ltp[e[i].to] = e[i].to, dfs2(e[i].to); } void dfs3(int s, long long up) { g[s] = f[s] + max(0ll, up); for (int i = fir[s]; i; i = e[i].nex) if (e[i].to != fa[s]) dfs3(e[i].to, g[s] - max(0ll, f[e[i].to] - 2 * e[i].wei) - 2 * e[i].wei); } void build() { for (int i = 1; i <= n; ++i) add(dfn[i], f[i] - max(0ll, f[i] - 2 * faw[i]) - faw[i]); } int lca(int x, int y) { for (; ltp[x] != ltp[y]; x = fa[ltp[x]]) if (dep[ltp[x]] < dep[ltp[y]]) swap(x, y); return dep[x] < dep[y] ? x : y; } long long get(int x, int z) { long long t = 0; for (; ltp[x] != ltp[z]; x = fa[ltp[x]]) t += sum(dfn[x]) - sum(dfn[ltp[x]] - 1); return t + sum(dfn[x]) - sum(dfn[z]); } void add(int i, long long v) { for (; i <= n; i += i & -i) bit[i] += v; } long long sum(int i) { long long t = 0; for (; i; i -= i & -i) t += bit[i]; return t; } |
#include <bits/stdc++.h> using namespace std; template <typename T> inline T read() { T x = 0, f = 1; char c = getchar(); while (!isdigit(c)) { if (c == - ) f = -f; c = getchar(); } while (isdigit(c)) { x = (x << 3) + (x << 1) + (c - 48); c = getchar(); } return x * f; } const int inf = 1e9 + 1e7, MAXN = 2e5 + 1e1; int a[MAXN], b[MAXN], q0[MAXN], q1[MAXN], n, ans, cnt, a0, a1, l0, r0, l1, r1; void Solve() { n = read<int>(), ans = cnt = a0 = a1 = l0 = r0 = l1 = r1 = 0; for (int i = 1; i <= n; i++) scanf( %1d , &a[i]); for (int i = 1; i <= n; i++) { if (a[i]) { if (a1) --a1, ++a0, b[i] = q1[l1], q0[r0++] = q1[l1++]; else ++ans, ++a0, b[i] = (++cnt), q0[r0++] = cnt; } else { if (a0) --a0, ++a1, b[i] = q0[l0], q1[r1++] = q0[l0++]; else ++ans, ++a1, b[i] = (++cnt), q1[r1++] = cnt; } } printf( %d n , ans); for (int i = 1; i <= n; i++) printf( %d , b[i]); printf( n ); return; } int main(void) { int t = read<int>(); while (t--) Solve(); return 0; } |
`define CONN_INTERNAL_BITS
`define PINTYPE 6'b010000
// `define IOSTANDARD "SB_LVCMOS"
`define IOSTANDARD "SB_LVDS_INPUT"
// The following IO standards are just aliases for SB_LVCMOS
// `define IOSTANDARD "SB_LVCMOS25_16"
// `define IOSTANDARD "SB_LVCMOS25_12"
// `define IOSTANDARD "SB_LVCMOS25_8"
// `define IOSTANDARD "SB_LVCMOS25_4"
// `define IOSTANDARD "SB_LVCMOS18_10"
// `define IOSTANDARD "SB_LVCMOS18_8"
// `define IOSTANDARD "SB_LVCMOS18_4"
// `define IOSTANDARD "SB_LVCMOS18_2"
// `define IOSTANDARD "SB_LVCMOS15_4"
// `define IOSTANDARD "SB_LVCMOS15_2"
// `define IOSTANDARD "SB_MDDR10"
// `define IOSTANDARD "SB_MDDR8"
// `define IOSTANDARD "SB_MDDR4"
// `define IOSTANDARD "SB_MDDR2"
`ifdef CONN_INTERNAL_BITS
module top (
inout pin,
input latch_in,
input clk_in,
input clk_out,
input oen,
input dout_0,
input dout_1,
output din_0,
output din_1
);
`else
module top(pin);
inout pin;
wire latch_in = 0;
wire clk_in = 0;
wire clk_out = 0;
wire oen = 0;
wire dout_0 = 0;
wire dout_1 = 0;
wire din_0;
wire din_1;
`endif
SB_IO #(
.PIN_TYPE(`PINTYPE),
.PULLUP(1'b0),
.NEG_TRIGGER(1'b0),
.IO_STANDARD(`IOSTANDARD)
) IO_PIN_I (
.PACKAGE_PIN(pin),
.LATCH_INPUT_VALUE(latch_in),
.CLOCK_ENABLE(clk_en),
.INPUT_CLK(clk_in),
.OUTPUT_CLK(clk_out),
.OUTPUT_ENABLE(oen),
.D_OUT_0(dout_0),
.D_OUT_1(dout_1),
.D_IN_0(din_0),
.D_IN_1(din_1)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; struct Edge { int v; int w; Edge* next; void add(int v, int w, Edge*& head) { this->v = v; this->w = w; this->next = head; head = this; } } edges[200100]; Edge* h[100100]; struct Q { int v; int t; bool operator<(const Q& q) const { return v < q.v || v == q.v && t < q.t; } void init(int v, int t) { this->v = v; this->t = t; } } q[100100], q0; void addEdge(int v1, int v2, int w) { static Edge* e = edges; (e++)->add(v2, w, h[v1]); (e++)->add(v1, w, h[v2]); } int d[100010]; struct CMP { bool operator()(int a, int b) const { return d[a] < d[b] || d[a] == d[b] && a < b; } }; set<int, CMP> heap; int main() { int n, m; scanf( %d %d , &n, &m); for (int i = 0; i < m; i++) { int v1, v2, w; scanf( %d %d %d , &v1, &v2, &w); v1--, v2--; addEdge(v1, v2, w); } int u = 0; for (int i = 0; i < n; i++) { int k; scanf( %d , &k); for (int j = 0; j < k; j++) { int t; scanf( %d , &t); q[u++].init(i, t); } } memset(d, 127, sizeof(d)); d[0] = 0; heap.insert(0); while (!heap.empty()) { int v = *heap.begin(); heap.erase(heap.begin()); if (v == n - 1) { printf( %d n , d[v]); return 0; } int dist = d[v]; q0.init(v, dist); Q* qi = lower_bound(q, q + u, q0); while (qi < q + u && qi->v == v && qi->t == dist) { dist++; qi++; } for (Edge* e = h[v]; e; e = e->next) { if (d[e->v] > dist + e->w) { heap.erase(e->v); d[e->v] = dist + e->w; heap.insert(e->v); } } } printf( -1 n ); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O2111A_FUNCTIONAL_V
`define SKY130_FD_SC_HS__O2111A_FUNCTIONAL_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o2111a (
VPWR,
VGND,
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
// Local signals
wire C1 or0_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X , B1, C1, or0_out, D1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O2111A_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; const long long N = 2e5 + 5; const long long inf = 1e16 + 7; long long m, n, h; long long ans = 0; long long seg[4 * N]; long long lazy[4 * N]; long long ind[N]; vector<long long> b; vector<long long> a; void build(long long p, long long val, long long v = 1, long long s = 0, long long e = n + 1) { if (e - s == 1) { seg[v] = val; return; } long long mid = (e + s) / 2; long long lc = 2 * v; long long rc = lc + 1; if (p < mid) { build(p, val, lc, s, mid); } else { build(p, val, rc, mid, e); } seg[v] = min(seg[lc], seg[rc]); } void shift(long long v, long long s, long long e) { long long mid = (s + e) / 2; long long lc = 2 * v; long long rc = lc + 1; seg[lc] += lazy[v]; seg[rc] += lazy[v]; lazy[lc] += lazy[v]; lazy[rc] += lazy[v]; lazy[v] = 0; } void add(long long l, long long r, long long val, long long v = 1, long long s = 0, long long e = n + 1) { if (r <= s || e <= l) { return; } if (l <= s && e <= r) { seg[v] += val; lazy[v] += val; return; } shift(v, s, e); long long mid = (s + e) / 2; long long lc = 2 * v; long long rc = lc + 1; add(l, r, val, lc, s, mid); add(l, r, val, rc, mid, e); seg[v] = min(seg[lc], seg[rc]); } long long get(long long l, long long r, long long v = 1, long long s = 0, long long e = n + 1) { if (r <= s || e <= l) { return inf; } if (l <= s && e <= r) { return seg[v]; } shift(v, s, e); long long mid = (s + e) / 2; long long lc = 2 * v; long long rc = lc + 1; return min(get(l, r, lc, s, mid), get(l, r, rc, mid, e)); } int main() { memset(seg, 127, sizeof seg); cin >> m >> n >> h; for (long long i = 0; i < n; i++) { long long tmp; cin >> tmp; b.push_back(tmp); } for (long long i = 0; i < m; i++) { long long tmp; cin >> tmp; a.push_back(tmp); } sort(b.begin(), b.end()); for (long long i = 0; i < m; i++) { ind[i] = lower_bound(b.begin(), b.end(), h - a[i]) - b.begin(); } for (long long i = 0; i <= n; i++) { build(i, n - i); } for (long long i = 0; i <= n; i++) { } for (long long i = 0; i < n; i++) { add(0, ind[i] + 1, -1); } if (get(0, n + 1) >= 0) { ans++; } for (long long i = n; i < m; i++) { add(0, ind[i - n] + 1, +1); add(0, ind[i] + 1, -1); if (get(0, n + 1) >= 0) { ans++; } } cout << ans << endl; } |
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always assign reg_lvalue = constant ;
// D: Note that initial has to be before always to execute!
module main ;
reg [3:0] value1 ;
initial
if(value1 != 4'h5)
$display("FAILED - 3.1.3A always assign reg_lvalue = constant\n");
else
begin
$display("PASSED\n");
$finish;
end
always assign value1 = 4'h5 ;
endmodule
|
//---------------------------------------------------------------------------
//-- Copyright 2015 - 2017 Systems Group, ETH Zurich
//--
//-- This hardware module is free software: you can redistribute it and/or
//-- modify it under the terms of the GNU General Public License as published
//-- by the Free Software Foundation, either version 3 of the License, or
//-- (at your option) any later version.
//--
//-- This program is distributed in the hope that it will be useful,
//-- but WITHOUT ANY WARRANTY; without even the implied warranty of
//-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
//-- GNU General Public License for more details.
//--
//-- You should have received a copy of the GNU General Public License
//-- along with this program. If not, see <http://www.gnu.org/licenses/>.
//---------------------------------------------------------------------------
module nukv_HT_Read_v2 #(
parameter KEY_WIDTH = 128,
parameter META_WIDTH = 96,
parameter HASHADDR_WIDTH = 64,
parameter MEMADDR_WIDTH = 21
)
(
// Clock
input wire clk,
input wire rst,
input wire [KEY_WIDTH+META_WIDTH+HASHADDR_WIDTH-1:0] input_data,
input wire input_valid,
output wire input_ready,
input wire [KEY_WIDTH+META_WIDTH+HASHADDR_WIDTH-1:0] feedback_data,
input wire feedback_valid,
output wire feedback_ready,
output reg [KEY_WIDTH+META_WIDTH+HASHADDR_WIDTH-1:0] output_data,
output reg output_valid,
input wire output_ready,
output reg [31:0] rdcmd_data,
output reg rdcmd_valid,
input wire rdcmd_ready
);
reg selectInputNext;
reg selectInput; //1 == input, 0==feedback
localparam [2:0]
ST_IDLE = 0,
ST_ISSUE_READ_ONE = 1,
ST_ISSUE_READ_TWO = 2,
ST_OUTPUT_KEY = 3;
reg [2:0] state;
wire[HASHADDR_WIDTH+KEY_WIDTH+META_WIDTH-1:0] in_data;
wire in_valid;
reg in_ready;
wire[HASHADDR_WIDTH-1:0] hash_data;
assign in_data = (selectInput==1) ? input_data : feedback_data;
assign in_valid = (selectInput==1) ? input_valid : feedback_valid;
assign input_ready = (selectInput==1) ? in_ready : 0;
assign feedback_ready = (selectInput==1) ? 0 : in_ready;
assign hash_data = (selectInput==1) ? input_data[KEY_WIDTH+META_WIDTH+HASHADDR_WIDTH-1:KEY_WIDTH+META_WIDTH] : feedback_data[KEY_WIDTH+META_WIDTH+HASHADDR_WIDTH-1:KEY_WIDTH+META_WIDTH];
wire[MEMADDR_WIDTH-1:0] addr1;
wire[MEMADDR_WIDTH-1:0] addr2;
assign addr1 = hash_data[0 +: HASHADDR_WIDTH/2];
assign addr2 = hash_data[HASHADDR_WIDTH/2 +: HASHADDR_WIDTH/2];
always @(posedge clk) begin
if (rst) begin
selectInput <= 1;
selectInputNext <= 0;
state <= ST_IDLE;
in_ready <= 0;
rdcmd_valid <= 0;
output_valid <= 0;
end
else begin
if (rdcmd_ready==1 && rdcmd_valid==1) begin
rdcmd_valid <= 0;
end
if (output_ready==1 && output_valid==1) begin
output_valid <= 0;
end
in_ready <= 0;
case (state)
ST_IDLE : begin
if (output_ready==1 && rdcmd_ready==1) begin
selectInput <= selectInputNext;
selectInputNext <= ~selectInputNext;
if (selectInputNext==1 && input_valid==0 && feedback_valid==1) begin
selectInput <= 0;
selectInputNext <= 1;
end
if (selectInputNext==0 && input_valid==1 && feedback_valid==0) begin
selectInput <= 1;
selectInputNext <= 0;
end
if (selectInput==1 && input_valid==1) begin
state <= ST_ISSUE_READ_ONE;
end
if (selectInput==0 && feedback_valid==1) begin
state <= ST_ISSUE_READ_ONE;
end
end
end
ST_ISSUE_READ_ONE: begin
state <= ST_ISSUE_READ_TWO;
output_data <= in_data;
rdcmd_data[MEMADDR_WIDTH-1:0] <= addr1[MEMADDR_WIDTH-1:0];
rdcmd_valid <= 1;
rdcmd_data[31:MEMADDR_WIDTH] <= 0;
end
ST_ISSUE_READ_TWO: begin
if (rdcmd_ready==1) begin
state <= ST_OUTPUT_KEY;
in_ready <= 1;
rdcmd_data[MEMADDR_WIDTH-1:0] <= addr2[MEMADDR_WIDTH-1:0];
rdcmd_valid <= 1;
rdcmd_data[31:MEMADDR_WIDTH] <= 0;
end
end
ST_OUTPUT_KEY: begin
if (output_ready==1) begin
output_valid <= 1;
state <= ST_IDLE;
end
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 300500; int n, a[N]; vector<int> v; int cnt[N]; vector<int> all; int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) { scanf( %d , &a[i]); v.push_back(a[i]); } sort(v.begin(), v.end()); v.resize(unique(v.begin(), v.end()) - v.begin()); if (n == (int)v.size()) { cout << -1; return 0; } for (int i = 1; i <= n; ++i) { a[i] = lower_bound(v.begin(), v.end(), a[i]) - v.begin() + 1; } vector<pair<int, int> > ans; for (int i = 1; i <= n; ++i) { int id = -1; for (int j = i; j <= n; ++j) { if (cnt[a[j]]) { id = j; break; } ++cnt[a[j]]; } if (id == -1) { ans[(int)ans.size() - 1].second = n; break; } else { ans.push_back(make_pair(i, id)); for (int j = i; j <= id; ++j) cnt[a[j]] = 0; i = id; } } printf( %d n , (int)ans.size()); for (int i = 0; i < (int)ans.size(); ++i) printf( %d %d n , ans[i].first, ans[i].second); return 0; } |
// file: sys_mon.v
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
`timescale 1ns / 1 ps
(* X_CORE_INFO = "sysmon_wiz_v2_1, Coregen 12.4" *)
module sys_mon
(
DADDR_IN, // Address bus for the dynamic reconfiguration port
DCLK_IN, // Clock input for the dynamic reconfiguration port
DEN_IN, // Enable Signal for the dynamic reconfiguration port
DI_IN, // Input data bus for the dynamic reconfiguration port
DWE_IN, // Write Enable for the dynamic reconfiguration port
VAUXP12, // Auxiliary channel 12
VAUXN12,
VAUXP13, // Auxiliary channel 13
VAUXN13,
DO_OUT, // Output data bus for dynamic reconfiguration port
DRDY_OUT, // Data ready signal for the dynamic reconfiguration port
VP_IN, // Dedicated Analog Input Pair
VN_IN);
input [6:0] DADDR_IN;
input DCLK_IN;
input DEN_IN;
input [15:0] DI_IN;
input DWE_IN;
input VAUXP12;
input VAUXN12;
input VAUXP13;
input VAUXN13;
input VP_IN;
input VN_IN;
output [15:0] DO_OUT;
output DRDY_OUT;
wire FLOAT_VCCAUX;
wire FLOAT_VCCINT;
wire FLOAT_TEMP;
wire GND_BIT;
wire [2:0] GND_BUS3;
assign GND_BIT = 0;
wire [15:0] aux_channel_p;
wire [15:0] aux_channel_n;
assign aux_channel_p[0] = 1'b0;
assign aux_channel_n[0] = 1'b0;
assign aux_channel_p[1] = 1'b0;
assign aux_channel_n[1] = 1'b0;
assign aux_channel_p[2] = 1'b0;
assign aux_channel_n[2] = 1'b0;
assign aux_channel_p[3] = 1'b0;
assign aux_channel_n[3] = 1'b0;
assign aux_channel_p[4] = 1'b0;
assign aux_channel_n[4] = 1'b0;
assign aux_channel_p[5] = 1'b0;
assign aux_channel_n[5] = 1'b0;
assign aux_channel_p[6] = 1'b0;
assign aux_channel_n[6] = 1'b0;
assign aux_channel_p[7] = 1'b0;
assign aux_channel_n[7] = 1'b0;
assign aux_channel_p[8] = 1'b0;
assign aux_channel_n[8] = 1'b0;
assign aux_channel_p[9] = 1'b0;
assign aux_channel_n[9] = 1'b0;
assign aux_channel_p[10] = 1'b0;
assign aux_channel_n[10] = 1'b0;
assign aux_channel_p[11] = 1'b0;
assign aux_channel_n[11] = 1'b0;
assign aux_channel_p[12] = VAUXP12;
assign aux_channel_n[12] = VAUXN12;
assign aux_channel_p[13] = VAUXP13;
assign aux_channel_n[13] = VAUXN13;
assign aux_channel_p[14] = 1'b0;
assign aux_channel_n[14] = 1'b0;
assign aux_channel_p[15] = 1'b0;
assign aux_channel_n[15] = 1'b0;
SYSMON #(
.INIT_40(16'h1000), // config reg 0
.INIT_41(16'h20ff), // config reg 1
.INIT_42(16'h0a00), // config reg 2
.INIT_48(16'h0f00), // Sequencer channel selection
.INIT_49(16'h3000), // Sequencer channel selection
.INIT_4A(16'h0f00), // Sequencer Average selection
.INIT_4B(16'h3000), // Sequencer Average selection
.INIT_4C(16'h0000), // Sequencer Bipolar selection
.INIT_4D(16'h0000), // Sequencer Bipolar selection
.INIT_4E(16'h0000), // Sequencer Acq time selection
.INIT_4F(16'h0000), // Sequencer Acq time selection
.INIT_50(16'hb5ed), // Temp alarm trigger
.INIT_51(16'h5999), // Vccint upper alarm limit
.INIT_52(16'he000), // Vccaux upper alarm limit
.INIT_53(16'hca33), // Temp alarm OT upper
.INIT_54(16'ha93a), // Temp alarm reset
.INIT_55(16'h5111), // Vccint lower alarm limit
.INIT_56(16'hcaaa), // Vccaux lower alarm limit
.INIT_57(16'hae4e), // Temp alarm OT reset
.SIM_DEVICE("VIRTEX6"),
.SIM_MONITOR_FILE("sys_mon.txt")
)
SYSMON_INST (
.CONVST(GND_BIT),
.CONVSTCLK(GND_BIT),
.DADDR(DADDR_IN[6:0]),
.DCLK(DCLK_IN),
.DEN(DEN_IN),
.DI(DI_IN[15:0]),
.DWE(DWE_IN),
.RESET(GND_BIT),
.VAUXN(aux_channel_n[15:0]),
.VAUXP(aux_channel_p[15:0]),
.ALM({FLOAT_VCCAUX, FLOAT_VCCINT, FLOAT_TEMP}),
.BUSY(),
.CHANNEL(),
.DO(DO_OUT[15:0]),
.DRDY(DRDY_OUT),
.EOC(),
.EOS(),
.JTAGBUSY(),
.JTAGLOCKED(),
.JTAGMODIFIED(),
.OT(),
.VP(VP_IN),
.VN(VN_IN)
);
endmodule
|
#include<bits/stdc++.h> using namespace std; #define ll long long #define mod 1000000007 void solve() { int k,n,m; cin >> k >> n >> m; vector<int> a(n); for(auto &i:a) { cin >> i; } vector<int> b(m); for(auto &i:b) { cin >> i; } vector<int> res(n+m); int i=0,j=0,ind=0; while(i!=n && j!=m) { if(a[i]==0) { res[ind]=0; ind++; i++; k++; } else if(b[j]==0) { res[ind]=0; ind++; j++; k++; } else if(a[i]<=b[j] && a[i]<=k) { res[ind]=a[i]; ind++; i++; } else if(a[i]>=b[j] && b[j]<=k) { res[ind]=b[j]; ind++; j++; } else { cout << -1 << endl; return; } } while(i!=n) { if(a[i]==0) { res[ind]=0; ind++; i++; k++; } else{ if(a[i]>k) { cout << -1 << endl; return; } res[ind]=a[i]; ind++; i++; } } while(j!=m) { if(b[j]==0) { res[ind]=0; ind++; j++; k++; } else{ if(b[j]>k) { cout << -1 << endl; return; } res[ind]=b[j]; ind++; j++;} } for(auto x:res) cout << x << ; cout << endl; } int main() { int t; cin >> t; while(t--) { solve(); } } |
module dec_5to32 (
input [4:0] a,
output [31:0] b);
and (b[0 ], ~a[4], ~a[3], ~a[2], ~a[1], ~a[0]);
and (b[1 ], ~a[4], ~a[3], ~a[2], ~a[1], a[0]);
and (b[2 ], ~a[4], ~a[3], ~a[2], a[1], ~a[0]);
and (b[3 ], ~a[4], ~a[3], ~a[2], a[1], a[0]);
and (b[4 ], ~a[4], ~a[3], a[2], ~a[1], ~a[0]);
and (b[5 ], ~a[4], ~a[3], a[2], ~a[1], a[0]);
and (b[6 ], ~a[4], ~a[3], a[2], a[1], ~a[0]);
and (b[7 ], ~a[4], ~a[3], a[2], a[1], a[0]);
and (b[8 ], ~a[4], a[3], ~a[2], ~a[1], ~a[0]);
and (b[9 ], ~a[4], a[3], ~a[2], ~a[1], a[0]);
and (b[10], ~a[4], a[3], ~a[2], a[1], ~a[0]);
and (b[11], ~a[4], a[3], ~a[2], a[1], a[0]);
and (b[12], ~a[4], a[3], a[2], ~a[1], ~a[0]);
and (b[13], ~a[4], a[3], a[2], ~a[1], a[0]);
and (b[14], ~a[4], a[3], a[2], a[1], ~a[0]);
and (b[15], ~a[4], a[3], a[2], a[1], a[0]);
and (b[16], a[4], ~a[3], ~a[2], ~a[1], ~a[0]);
and (b[17], a[4], ~a[3], ~a[2], ~a[1], a[0]);
and (b[18], a[4], ~a[3], ~a[2], a[1], ~a[0]);
and (b[19], a[4], ~a[3], ~a[2], a[1], a[0]);
and (b[20], a[4], ~a[3], a[2], ~a[1], ~a[0]);
and (b[21], a[4], ~a[3], a[2], ~a[1], a[0]);
and (b[22], a[4], ~a[3], a[2], a[1], ~a[0]);
and (b[23], a[4], ~a[3], a[2], a[1], a[0]);
and (b[24], a[4], a[3], ~a[2], ~a[1], ~a[0]);
and (b[25], a[4], a[3], ~a[2], ~a[1], a[0]);
and (b[26], a[4], a[3], ~a[2], a[1], ~a[0]);
and (b[27], a[4], a[3], ~a[2], a[1], a[0]);
and (b[28], a[4], a[3], a[2], ~a[1], ~a[0]);
and (b[29], a[4], a[3], a[2], ~a[1], a[0]);
and (b[30], a[4], a[3], a[2], a[1], ~a[0]);
and (b[31], a[4], a[3], a[2], a[1], a[0]);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, flag; int ar[101][101], ars[101][101], c[101][101], q[101][101]; int fu() { int y = 1; for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) if (ars[i][j] != c[i][j]) y = 0; return y; } void f() { flag = max(flag, fu()); for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) q[i][j] = c[j][n - i - 1]; for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) c[i][j] = q[i][j]; flag = max(flag, fu()); for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) q[i][j] = c[j][n - i - 1]; for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) c[i][j] = q[i][j]; flag = max(flag, fu()); for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) q[i][j] = c[j][n - i - 1]; for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) c[i][j] = q[i][j]; flag = max(flag, fu()); } int main() { cin >> n; for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) { char a; cin >> a; if (a == X ) ar[i][j] = 0; else ar[i][j] = 1; c[i][j] = ar[i][j]; } for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) { char a; cin >> a; if (a == X ) ars[i][j] = 0; else ars[i][j] = 1; } f(); for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) c[i][j] = ar[n - i - 1][j]; f(); for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) c[i][j] = ar[i][n - j - 1]; f(); if (flag) { cout << Yes ; } else cout << No ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND3_BLACKBOX_V
`define SKY130_FD_SC_HDLL__AND3_BLACKBOX_V
/**
* and3: 3-input AND.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__and3 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND3_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLRTP_BLACKBOX_V
`define SKY130_FD_SC_LP__DLRTP_BLACKBOX_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlrtp (
Q ,
RESET_B,
D ,
GATE
);
output Q ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLRTP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; #pragma warning(disable : 4996) int a[100010], cnt[100010]; int queries[100010][2]; bool res[100010]; bool xpeHb[100010]; int main() { int t; scanf( %d , &t); for (int y = 0; y < t; y++) { int m, k; scanf( %d %d , &m, &k); for (int i = 1; i <= k; i++) { scanf( %d , &a[i]); } int t, r; int count = 0; bool flag = false; for (int i = 0; i < m - 1; i++) { scanf( %d %d , &queries[i][0], &queries[i][1]); if (queries[i][1] == 1) flag = true; if (flag) { if (queries[i][0]) xpeHb[queries[i][0]] = true; } } flag = true; for (int i = 0; i < m - 1; i++) { t = queries[i][0]; r = queries[i][1]; if (r == 1 && flag) { flag = false; int max = 0; for (int j = 1; j <= k; j++) { if (cnt[j] + count >= a[j] && !xpeHb[j]) { res[j] = true; if (max < cnt[j] + count - a[j]) max = cnt[j] + count - a[j]; } } count = max; } if (t == 0) count++; else { cnt[t]++; } } for (int j = 1; j <= k; j++) { if (cnt[j] + count >= a[j]) { res[j] = true; } if (res[j]) printf( Y ); else printf( N ); } printf( n ); memset(cnt, 0, (k + 1) * 4); memset(res, 0, (k + 1) * 1); memset(a, 0, (k + 1) * 4); memset(xpeHb, 0, (k + 1) * 1); memset(queries[0], 0, (m + 1) * 4); memset(queries[1], 0, (m + 1) * 4); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_PWRGOOD_L_PP_PG_TB_V
`define SKY130_FD_SC_HD__UDP_PWRGOOD_L_PP_PG_TB_V
/**
* UDP_OUT :=x when VPWR!=1 or VGND!=0
* UDP_OUT :=UDP_IN when VPWR==1 and VGND==0
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__udp_pwrgood_l_pp_pg.v"
module top();
// Inputs are registered
reg UDP_IN;
reg VPWR;
reg VGND;
// Outputs are wires
wire UDP_OUT;
initial
begin
// Initial state is x for all inputs.
UDP_IN = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 UDP_IN = 1'b0;
#40 VGND = 1'b0;
#60 VPWR = 1'b0;
#80 UDP_IN = 1'b1;
#100 VGND = 1'b1;
#120 VPWR = 1'b1;
#140 UDP_IN = 1'b0;
#160 VGND = 1'b0;
#180 VPWR = 1'b0;
#200 VPWR = 1'b1;
#220 VGND = 1'b1;
#240 UDP_IN = 1'b1;
#260 VPWR = 1'bx;
#280 VGND = 1'bx;
#300 UDP_IN = 1'bx;
end
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG dut (.UDP_IN(UDP_IN), .VPWR(VPWR), .VGND(VGND), .UDP_OUT(UDP_OUT));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_PWRGOOD_L_PP_PG_TB_V
|
#include <bits/stdc++.h> using namespace std; int main() { int T, n; cin >> T; while (T--) { cin >> n; long long ans = 0; for (int i = 1; i <= n / 2; i++) { ans += i * 1ll * i; } cout << ans * 8 << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; short p[402][402 * 402]; int a[402][402], n, m, l, r, j, i, d[402][402], f[402][402], ans; int main() { scanf( %d%d , &n, &m); for (i = 1; i <= n; ++i) for (j = 1; j <= m; ++j) scanf( %d , &a[i][j]); for (j = 1; j <= m; ++j) { for (l = n; l >= 1; --l) for (r = l; r <= n; ++r) { f[l][r] = max((int)max(p[r][a[l][j]], p[l][a[r][j]]), max(f[l + 1][r], f[l][r - 1])); if (l != r && a[l][j] == a[r][j]) f[l][r] = j; d[l][r] = max(d[l][r], f[l][r]); ans = max(ans, (r - l + 1) * (j - d[l][r])); } for (i = 1; i <= n; ++i) p[i][a[i][j]] = j; } printf( %d n , ans); } |
#include <bits/stdc++.h> using namespace std; int n, m, ans, tot; int b[200010], rt[200010]; struct nu { int val, id; } a[200010]; char s[200010]; struct node { int ls, rs, sum; } tree[200010 * 20]; inline bool cmp(const nu &x, const nu &y) { if (x.val == y.val) return x.id < y.id; else return x.val > y.val; } inline void insert(int num, int &x, int l, int r) { tree[++tot] = tree[x]; x = tot; ++tree[x].sum; if (l == r) return; int mid = (l + r) >> 1; if (num <= mid) insert(num, tree[x].ls, l, mid); else insert(num, tree[x].rs, mid + 1, r); } inline void prework() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i].val), a[i].id = i, b[i] = a[i].val; sort(a + 1, a + 1 + n, cmp); tot = 0; for (int i = 1; i <= n; i++) { rt[i] = rt[i - 1]; insert(a[i].id, rt[i], 1, n); } } inline int query(int i, int j, int k, int l, int r) { if (l == r) return l; int tp = tree[tree[j].ls].sum - tree[tree[i].ls].sum; int mid = (l + r) >> 1; if (k <= tp) return query(tree[i].ls, tree[j].ls, k, l, mid); else return query(tree[i].rs, tree[j].rs, k - tp, mid + 1, r); } inline void mainwork() { scanf( %d , &m); int k, pos; for (int i = 1; i <= m; i++) { scanf( %d%d , &k, &pos); ans = query(rt[0], rt[k], pos, 1, n); printf( %d n , b[ans]); } } inline void print() {} int main() { int t = 1; for (int i = 1; i <= t; i++) { prework(); mainwork(); print(); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSHOLD0_1_V
`define SKY130_FD_SC_LP__BUSHOLD0_1_V
/**
* bushold0: Bus signal holder (back-to-back inverter) with
* noninverting reset (gates internal node weak driver).
*
* Verilog wrapper for bushold0 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__bushold0.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__bushold0_1 (
X ,
RESET,
VPWR ,
VGND ,
VPB ,
VNB
);
inout X ;
input RESET;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__bushold0 base (
.X(X),
.RESET(RESET),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__bushold0_1 (
X ,
RESET
);
inout X ;
input RESET;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__bushold0 base (
.X(X),
.RESET(RESET)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSHOLD0_1_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04/27/2016 08:14:07 AM
// Design Name:
// Module Name: FPU_UART
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FPU_UART
#(parameter W = 32, parameter EW = 8, parameter SW = 23, parameter SWR=26, parameter EWR = 5)//-- Single Precision*/
/*#(parameter W = 64, parameter EW = 11, parameter SW = 52, parameter SWR = 55, parameter EWR = 6) //-- Double Precision */
(
input wire clk,
input wire rst,
output wire TX
);
//local parameters
localparam shift_region = 2'b00;
localparam N = 2; //2 para 32 bits, 3 para 64 bits
localparam op = 1'b0;
localparam d = 0;
localparam r_mode=2'b00;
//signal declaration
wire ready_op;
wire max_tick_address;
wire max_tick_ch;
wire TX_DONE;
wire beg_op;
wire ack_op;
wire load_address;
wire enab_address;
wire enab_ch;
wire load_ch;
wire TX_START;
wire [W-1:0] Data_X;
wire [W-1:0] Data_Y;
wire [W-1:0] final_result_ieee;
wire [7:0] TX_DATA;
wire [9:0] cont_address_sig;
wire [N-1:0] cont_ch;
FSM_test fsm_test_uart
(
.clk(clk),
.rst(rst),
.ready_op(ready_op),
.max_tick_address(max_tick_address),
.max_tick_ch(max_tick_ch),
.TX_DONE(TX_DONE),
.beg_op(beg_op),
.ack_op(ack_op),
.load_address(load_address),
.enab_address(enab_address),
.enab_ch(enab_ch),
.load_ch(load_ch),
.TX_START(TX_START)
);
//Adder-Subtract//////////////////////////////////////////////////////////////////////////////
FPU_Add_Subtract_Function #(.W(W),.EW(EW),.SW(SW),.SWR(SWR),.EWR(EWR)) Add_Subt_uart(
.clk(clk), //System clock
.rst(rst), //System reset
.beg_FSM(beg_op), //Start operation control signal
.ack_FSM(ack_op), //Acknoledge control signal
.Data_X(Data_X), //Data_X
.Data_Y(Data_Y), //Data_Y
.add_subt(op), //1'b0 =Adder, 1'b1=Substract
.r_mode(r_mode), //Rounding control signal. 2'b00=no round, 2'b01= -infinite round , 2'b10 +infinite round
//.overflow_flag,
//.underflow_flag,
.ready(ready_op), //Ready flag
.final_result_ieee(final_result_ieee) //Result of the operation
);//*/
//Multiplication
/*FPU_Multiplication_Function #(.W(W),.EW(EW),.SW(SW)) Multiplication_uart(
.clk(clk),
.rst(rst),
.beg_FSM(beg_op),
.ack_FSM(ack_op),
.Data_MX(Data_X),
.Data_MY(Data_Y),
.round_mode(r_mode),
//.overflow_flag,
//.underflow_flag,
.ready(ready_op),
.final_result_ieee(final_result_ieee)
);
//*/
Uart uart_mod
(
.RST(rst),
.CLK(clk),
.TX_START(TX_START),
.TX_DATA(TX_DATA),
.TX(TX),
.TX_DONE(TX_DONE)
);
///Data file ROM
ROM_test #(.W(W),.N(0)) rom_test_uart_X
(
.address(cont_address_sig),
.data(Data_X)
);
ROM_test #(.W(W),.N(1)) rom_test_uart_Y
(
.address(cont_address_sig),
.data(Data_Y)
);
cont_test #(.W(10)) cont_address
(
.clk(clk),
.rst(rst),
.load(load_address),
.enable(enab_address),
.d(d),
.max_tick(max_tick_address),
.q(cont_address_sig)
);
cont_test #(.W(N)) con_mux_data
(
.clk(clk),
.rst(rst),
.load(load_ch),
.enable(enab_ch),
.d(d),
.max_tick(max_tick_ch),
.q(cont_ch)
);
generate
case(W)
32:
begin
Mux_4x1 mux_32_uart
(
.select(cont_ch),
.ch_0(final_result_ieee[7:0]),
.ch_1(final_result_ieee[15:8]),
.ch_2(final_result_ieee[23:16]),
.ch_3(final_result_ieee[31:24]),
.data_out(TX_DATA)
);
end
64:
begin
Mux_8x1 mux_64_uart
(
.select(cont_ch),
.ch_0(final_result_ieee[7:0]),
.ch_1(final_result_ieee[15:8]),
.ch_2(final_result_ieee[23:16]),
.ch_3(final_result_ieee[31:24]),
.ch_4(final_result_ieee[39:32]),
.ch_5(final_result_ieee[47:40]),
.ch_6(final_result_ieee[55:48]),
.ch_7(final_result_ieee[63:56]),
.data_out(TX_DATA)
);
end
default:
begin
Mux_4x1 mux_32_uart
(
.select(cont_ch),
.ch_0(final_result_ieee[7:0]),
.ch_1(final_result_ieee[15:8]),
.ch_2(final_result_ieee[23:16]),
.ch_3(final_result_ieee[31:24]),
.data_out(TX_DATA)
);
end
endcase
endgenerate
endmodule |
module main;
reg [2:0] Q;
reg clk, clr, up, down;
reg flag;
(*ivl_synthesis_off *)
initial begin
clk = 0;
up = 0;
down = 0;
clr = 1;
#1 clk = 1;
#1 clk = 0;
if (Q !== 0) begin
$display("FAILED");
$finish;
end
if (flag !== 0) begin
$display("FAILED");
$finish;
end
up = 1;
clr = 0;
#1 clk = 1;
#1 clk = 0;
#1 clk = 1;
#1 clk = 0;
if (Q !== 3'b010) begin
$display("FAILED");
$finish;
end
if (flag !== 0) begin
$display("FAILED");
$finish;
end
up = 0;
down = 1;
#1 clk = 1;
#1 clk = 0;
if (Q !== 3'b001) begin
$display("FAILED");
$finish;
end
if (flag !== 0) begin
$display("FAILED");
$finish;
end
down = 0;
#1 clk = 1;
#1 clk = 0;
if (Q !== 3'b001) begin
$display("FAILED");
$finish;
end
if (flag !== 1) begin
$display("FAILED");
$finish;
end
$display("PASSED");
$finish;
end
/*
* This statement models a snythesizable UP/DOWN counter. The up
* and down cases are enabled by up and down signals. If both
* signals are absent, the synthesizer should take the implicit
* case that Q <= Q;
*/
(* ivl_synthesis_on *)
always @(posedge clk, posedge clr)
if (clr) begin
Q <= 0;
flag <= 0;
end else begin
if (up)
Q <= Q + 1;
else if (down)
Q <= Q - 1;
else
flag <= 1;
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long i, T, n; cin >> T; while (T--) { double h, c, t, ans; cin >> h >> c >> t; double res = h, freq = 1.0, diff = fabs(((h + c) / 2) - t); if (h == t) { cout << 1 << n ; continue; } if ((h + c) / 2 >= t) { cout << 2 << n ; continue; } freq = 1 + 2 * ceil((t - h) / (h + c - 2 * t)); double freq2 = freq - 2; if (fabs((h + (h + c) * ((freq - 1) / 2)) / (freq)-t) < fabs((h + (h + c) * ((freq2 - 1) / 2)) / (freq2)-t)) { if (diff < fabs((h + (h + c) * (freq / 2)) / (1 + freq) - t)) { cout << 2 << n ; } else { cout << freq << n ; } } else { if (diff < fabs((h + (h + c) * (freq2 / 2)) / (1 + freq2) - t)) { cout << 2 << n ; } else { cout << freq2 << n ; } } } return 0; } |
#include <bits/stdc++.h> using namespace std; void debug_out() { cerr << n ; } template <typename H, typename... T> void debug_out(H h, T... t) { cerr << << (h); debug_out(t...); } int n; string a, b; char flip(char ch) { return (char)( 0 + ( 1 - ch)); } char ch(int i, int cnt) { return (char)( 0 + ((a[i] - 0 + cnt) % 2)); } void solve() { cin >> n >> a >> b; vector<int> res; int first = 0; int last = n - 1; int cnt = 0; for (int i = n - 1; i >= 0; i--) { if (ch(last, cnt) != b[i]) { if (ch(first, cnt) == b[i]) { res.push_back(1); a[first] = flip(a[first]); } if (i or ch(first, cnt) != b[i]) { res.push_back(i + 1); cnt++; swap(first, last); } } if (cnt % 2) { last++; } else { last--; } } cout << res.size(); for (auto i : res) cout << << i; cout << n ; } int main() { int t; cin >> t; while (t--) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const int inf = 0x3f3f3f3f; const int maxn = 1e5 + 5; void Solution() { int n; cin >> n; cout << (n / 2) + 1 << n ; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) Solution(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int iinf = 1e9 + 7; const long long linf = 1ll << 60; const double dinf = 1e60; template <typename T> inline void scf(T &x) { bool f = 0; x = 0; char c = getchar(); while ((c < 0 || c > 9 ) && c != - ) c = getchar(); if (c == - ) { f = 1; c = getchar(); } while (c >= 0 && c <= 9 ) { x = x * 10 + c - 0 ; c = getchar(); } if (f) x = -x; return; } template <typename T1, typename T2> void scf(T1 &x, T2 &y) { scf(x); return scf(y); } template <typename T1, typename T2, typename T3> void scf(T1 &x, T2 &y, T3 &z) { scf(x); scf(y); return scf(z); } template <typename T1, typename T2, typename T3, typename T4> void scf(T1 &x, T2 &y, T3 &z, T4 &w) { scf(x); scf(y); scf(z); return scf(w); } inline char mygetchar() { char c = getchar(); while (c == || c == n ) c = getchar(); return c; } template <typename T> void chkmax(T &x, const T &y) { if (y > x) x = y; return; } template <typename T> void chkmin(T &x, const T &y) { if (y < x) x = y; return; } const int N = 20; int n, dig[N]; long long dp[N][N][2], g[65540][N][N]; long long table[65540]; int get(char c) { return c - (c >= a ? a - 10 : 0 ); } bool check(long long x) { long long ret = x, y = 0; while (x) { y |= (1ll << (x & 15)); x >>= 4; } return (ret ^ y) < ret; } void MEI() { for (int x = 0; x < (65536); ++x) { if (x) table[x] = table[x - 1]; table[x] += check(x); } for (int x = 0; x < (65536); ++x) { int y = x, mx = 0; while (y) { chkmax(mx, y & 15); y >>= 4; } for (int mx_front = 0; mx_front < (16); ++mx_front) { if ((x >> max(mx_front, mx)) & 1) { g[x][mx][mx_front]++; } } } for (int x = (1); x <= (65535); ++x) for (int mx1 = 0; mx1 < (16); ++mx1) for (int mx2 = 0; mx2 < (16); ++mx2) g[x][mx1][mx2] += g[x - 1][mx1][mx2]; return; } long long solve(long long x) { memset((dp), (0), sizeof((dp))); ; if (x < 65536) return table[x]; long long y = x & 65535, ans = 0; n = 0; while (x) dig[n++] = x & 15, x >>= 4; dp[n][0][1] = 1; for (int i = (n); i >= (5); --i) for (int mx = 0; mx < (16); ++mx) for (int f = 0; f < (2); ++f) if (dp[i][mx][f]) { long long &t = dp[i][mx][f]; for (int y = 0; y < (16); ++y) { if (f && y > dig[i - 1]) break; dp[i - 1][max(mx, y)][f && y == dig[i - 1]] += t; } } for (int mx1 = 0; mx1 < (16); ++mx1) for (int mx2 = 0; mx2 < (16); ++mx2) { ans += dp[4][mx1][0] * g[65535][mx2][mx1] + dp[4][mx1][1] * g[y][mx2][mx1]; } return ans; } void ZI() { int q; scf(q); while (q--) { char s[N]; long long x = 0, res; scanf( %s , s); int n = strlen(s); for (int i = 0; i < (n); ++i) x = x * 16 + get(s[i]); res = -solve(x - 1); scanf( %s , s); n = strlen(s); x = 0; for (int i = 0; i < (n); ++i) x = x * 16 + get(s[i]); res += solve(x); printf( %I64d n , res); } return; } int main() { MEI(); ZI(); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND4BB_BEHAVIORAL_V
`define SKY130_FD_SC_LS__NAND4BB_BEHAVIORAL_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__nand4bb (
Y ,
A_N,
B_N,
C ,
D
);
// Module ports
output Y ;
input A_N;
input B_N;
input C ;
input D ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out;
wire or0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out, D, C );
or or0 (or0_out_Y, B_N, A_N, nand0_out);
buf buf0 (Y , or0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND4BB_BEHAVIORAL_V |
module interstage_buffer_if_id(clock);
register#(4) id_control_signals_buffer(if_control_signals,
clock,
id_control_signals);
register#(4) ex_control_signals_buffer(id_control_signals,
clock,
ex_control_signals);
register#(4) mem_control_signals_buffer(ex_control_signals,
clock,
mem_control_signals);
register#(4) wb_control_signals_buffer(mem_control_signals,
clock,
wb_control_signals);
endmodule
module interstage_buffer_id_ex(clock);
register#(4) ex_control_signals_buffer(id_control_signals,
clock,
ex_control_signals);
register#(4) mem_control_signals_buffer(ex_control_signals,
clock,
mem_control_signals);
register#(4) wb_control_signals_buffer(mem_control_signals,
clock,
wb_control_signals);
endmodule
module interstage_buffer_ex_mem(clock);
register#(4) mem_control_signals_buffer(ex_control_signals,
clock,
mem_control_signals);
register#(4) wb_control_signals_buffer(mem_control_signals,
clock,
wb_control_signals);
endmodule
module interstage_buffer_mem_wb(clock);
register#(4) wb_control_signals_buffer(mem_control_signals,
clock,
wb_control_signals);
endmodule
|
#include <bits/stdc++.h> using namespace std; const double pi = acos(-1); int main() { ios::sync_with_stdio(false); int m, n, k; while (cin >> m >> n >> k) { k *= 2; if (m >= k && n >= k) { cout << First << endl; } else { cout << Second << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; const long long inf2 = 0x3f3f3f3f3f3f3f3f; const double eps = 1e-6; const int mod = 1000000007; namespace fastio { char in[100000]; int itr = 0, llen = 0; char get() { if (itr == llen) llen = fread(in, 1, 100000, stdin), itr = 0; if (llen == 0) return EOF; return in[itr++]; } char out[100000]; int itr2 = 0; void put(char c) { out[itr2++] = c; if (itr2 == 100000) { fwrite(out, 1, 100000, stdout); itr2 = 0; } } int clear() { fwrite(out, 1, itr2, stdout); itr2 = 0; return 0; } int getint() { int r = 0; bool ng = 0; char c; c = get(); while (c != - && (c < 0 || c > 9 )) c = get(); if (c == - ) ng = 1, c = get(); while (c >= 0 && c <= 9 ) r = r * 10 + c - 0 , c = get(); return ng ? -r : r; } string getstr() { string ret = ; char ch = get(); while (ch == || ch == n ) ch = get(); while (ch != && ch != n ) ret.push_back(ch), ch = get(); return ret; } void putstr(string s) { for (int i = 0; i < s.size(); i++) put(s[i]); } void putint(int x) { if (x < 0) { put( - ); x = -x; } if (x == 0) { put( 0 ); return; } char c[20]; int pos = 0; while (x) { c[pos++] = 0 + x % 10; x /= 10; } for (int i = pos - 1; i >= 0; i--) put(c[i]); } void getarr(int arrname[], int size) { for (int i = 0; i < size; i++) arrname[i] = getint(); } } // namespace fastio using namespace fastio; int number[1000005], BITN = 1e6; void modify(int x, int y) { while (x <= BITN) { number[x] += y; x += x & -x; } } int sum(int x) { int ret = 0; while (x) { ret += number[x]; x &= x - 1; } return ret; } void add(int l, int r, int v) { modify(l, v); modify(r, -v); } int qry(int x) { return sum(x); } int n, k; vector<int> g[1000005]; vector<int> ord; int pos[1000005]; bool used[1000005]; int par[1000005]; int sz[1000005], depth[1000005]; void dfs(int x, int pr) { depth[x] = x == n ? 0 : depth[pr] + 1; pos[x] = ord.size() + 1; ord.push_back(x); sz[x] = 1; for (auto to : g[x]) if (to != pr) par[to] = x, dfs(to, x), sz[x] += sz[to]; } int main() { n = getint(); k = getint(); for (int i = 1; i < n; i++) { int a = getint(), b = getint(); g[a].push_back(b); g[b].push_back(a); } dfs(n, 0); for (int i = 0; i < ord.size(); i++) { modify(i + 1, depth[ord[i]] - (i == 0 ? 0 : depth[ord[i - 1]])); } used[n] = true; int rest = n - k - 1; for (int v = n - 1; v > 0 && rest; v--) { if (used[v]) continue; int len = qry(pos[v]); if (len <= rest) { int cur = v; while (!used[cur]) { used[cur] = true; add(pos[cur], pos[cur] + sz[cur], -1); cur = par[cur]; rest--; } } } vector<int> ans; for (int i = 1; i <= n; i++) if (!used[i]) ans.push_back(i); for (int i = 0; i < ans.size(); i++) putint(ans[i]), put( ); clear(); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { double n; cin >> n; double sum = 0, y; for (int i = 0; i < n; i++) { cin >> y >> y; sum += y; } sum = sum / n; cout << sum + 5 << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long int n, m, a, n2, m2; cin >> n >> m >> a; if ((a * (n / a)) == n) n2 = n / a; else n2 = (n / a) + 1; if ((a * (m / a)) == m) m2 = m / a; else m2 = (m / a) + 1; cout << n2 * m2 << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; pair<int, int> a[n], b[m]; for (int i = 0; i < n; i++) { cin >> a[i].first >> a[i].second; } for (int i = 0; i < m; i++) { cin >> b[i].first >> b[i].second; } set<int> s; for (int i = 0; i < n; i++) { int f = 0; for (int j = 0; j < m; j++) { if (((a[i].first == b[j].first) || (a[i].first == b[j].second)) && ((a[i].second == b[j].first) || (a[i].second == b[j].second))) { continue; } else if ((a[i].first == b[j].first) || (a[i].first == b[j].second)) { f = 1; } } int tr = 1; if (f) { s.insert(a[i].first); tr = 0; } for (int j = 0; j < m; j++) { if (((a[i].first == b[j].first) || (a[i].first == b[j].second)) && ((a[i].second == b[j].first) || (a[i].second == b[j].second))) { continue; } else if ((a[i].second == b[j].first) || (a[i].second == b[j].second)) { f += 1; break; } } if (f > 1) { cout << -1 n ; exit(0); } if (f && tr) { s.insert(a[i].second); } } for (int j = 0; j < m; j++) { int f = 0; int tr = 1; for (int i = 0; i < n; i++) { if (((a[i].first == b[j].first) || (a[i].first == b[j].second)) && ((a[i].second == b[j].first) || (a[i].second == b[j].second))) { continue; } else if ((b[j].first == a[i].first) || (b[j].first == a[i].second)) { f = 1; } } if (f) { s.insert(b[j].first); tr = 0; } for (int i = 0; i < n; i++) { if (((a[i].first == b[j].first) || (a[i].first == b[j].second)) && ((a[i].second == b[j].first) || (a[i].second == b[j].second))) { continue; } else if ((b[j].second == a[i].first) || (b[j].second == a[i].second)) { f += 1; break; } } if (f > 1) { cout << -1 n ; exit(0); } if (f && tr) { s.insert(b[j].second); } } if (s.size() == 1) { auto it = s.begin(); cout << (*it); } else { cout << 0 ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const bool DEBUG = false; int main() { ios::sync_with_stdio(0); cin.tie(0); bool puede = true; int N, M; cin >> N >> M; unordered_set<int> conj; vector<string> cad(N); vector<int> index(M); for (int i = 0; i < N; i++) { cin >> cad[i]; conj.insert(i); } for (int i = 0; i < M; i++) { cin >> index[i]; index[i]--; conj.erase(index[i]); } for (int i = 0; i < M - 1; i++) { if (cad[index[i]].size() != cad[index[i + 1]].size()) puede = false; } if (!puede) { cout << No n ; return 0; } bool band; string patron = ; int sz = cad[index[0]].size(); if (DEBUG) { cout << cad[index[0]] << endl; cout << SZ: << sz << endl; } for (int i = 0; i < sz; i++) { band = true; for (int j = 0; j < M - 1; j++) { if (cad[index[j]][i] != cad[index[j + 1]][i]) { patron += ? ; band = false; } if (!band) break; } if (band) patron += cad[index[0]][i]; } for (auto &it : conj) { band = true; if (cad[it].size() != patron.size()) continue; for (int i = 0; i < patron.size(); i++) { if (patron[i] == ? ) continue; if (patron[i] == cad[it][i]) continue; band = false; break; } if (band) { cout << No n ; return 0; } } cout << Yes n << patron << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, K; int pover[64000]; int ipover[64000]; int dt[503][503]; int lsum[2][503][503]; const int mod = 1000000007; int main() { scanf( %d%d , &n, &K); int maxval = 0; pover[0] = 1; for (int i = 1; i < 64000; i++) { pover[i] = (pover[i - 1] * (long long)2) % mod; } ipover[0] = 1; for (int i = 1; i < 64000; i++) { ipover[i] = (ipover[i - 1] * (long long)500000004) % mod; } for (int j = 0; j <= 0; j++) { dt[0][j] = 1; } for (int k = 0; k <= n; k++) { long long ksum = 0; for (int j = 0; j < k; j++) { long long mul = pover[(k - j) * (n - k + 1)]; ksum = (ksum + dt[0][j] * mul) % mod; lsum[1][j][k] = ksum; } } for (int i = 1; i <= K; i++) { int ci = i % 2; for (int j = 1; j <= n; j++) { for (int k = 1; k <= j; k++) { long long baseCnt = lsum[ci][k - 1][j]; long long tot = baseCnt * ipover[j - k + 1] % mod; dt[i][j] = (dt[i][j] + tot) % mod; } } int ni = 1 - i % 2; memset(lsum[ni], 0, sizeof(lsum[0])); for (int k = 0; k <= n; k++) { long long ksum = 0; for (int j = 0; j < k; j++) { long long mul = pover[(k - j) * (n - k + 1)]; ksum = (ksum + dt[i][j] * mul) % mod; lsum[ni][j][k] = ksum; } } } long long ans = 0; for (int i = 0; i <= n; i++) { ans += dt[K][i]; ans %= mod; } ans %= mod; printf( %d n , (int)ans); return 0; } |
#include <bits/stdc++.h> using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); const double INF = 1e20; const int N = 102; const int M = 1010; const int K = 10; int n; double C, T; const double Y = 1. / 0.9; pair<int, int> a[N]; double dp[N][M]; void read() { scanf( %d , &n); scanf( %lf%lf , &C, &T); for (int i = 0; i < n; i++) scanf( %d%d , &a[i].first, &a[i].second); sort(a, a + n); } int solve() { read(); dp[0][0] = 0; for (int it = 1; it <= n; it++) { for (int j = 0; j <= it * K; j++) dp[it][j] = INF; for (int i = it - 1; i >= 0; i--) for (int j = 0; j <= i * K; j++) { if (dp[i][j] >= INF / 2) continue; dp[i + 1][j + a[it - 1].second] = min(dp[i + 1][j + a[it - 1].second], dp[i][j] * Y + a[it - 1].first); } } for (int x = n * K; x >= 0; x--) for (int p = 0; p <= n; p++) { if (p * K < x || dp[p][x] >= INF / 2) continue; double X = dp[p][x] * Y; double t = X; if (C * X >= 1) t = 2 * sqrt(X / C) - 1. / C; t += p * 10; if (t <= T) return x; } throw; } int main() { int t; scanf( %d , &t); while (t--) printf( %d n , solve()); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int q; scanf( %d , &q); while (q--) { int n; scanf( %d , &n); vector<int> a(n); for (int i = 0; i < n; i++) scanf( %d , &a[i]); sort(a.begin(), a.end()); a.erase(unique(a.begin(), a.end()), a.end()); n = a.size(); int ans = a.back(); for (int i = n - 1; i >= 0; i--) { if (i >= 2) { if (ans > a[i] + a[i - 1] + a[i - 2]) break; } for (int j = i - 1; j >= 0; j--) { if (j >= 1) { if (ans > a[i] + a[j] + a[j - 1]) break; } if (a[i] % a[j]) { ans = max(ans, a[i] + a[j]); for (int k = j - 1; k >= 0; k--) { if (ans > a[i] + a[j] + a[k]) break; if ((a[i] % a[k]) && (a[j] % a[k])) { ans = max(ans, a[i] + a[j] + a[k]); break; } } } } } cout << ans << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 200000; int a[N], n, m, k; int check(int x) { int cnt = 1, space = k; for (int i = x; i < n; i++) { if (a[i] <= space) space -= a[i]; else { if (cnt == m) return 0; ++cnt, space = k - a[i]; } } return 1; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> n >> m >> k; for (int i = 0; i < n; i++) cin >> a[i]; int l = 0, r = n - 1, mid; while (l != r) { mid = (l + r) / 2; check(mid) ? r = mid : l = mid + 1; } cout << n - l << n ; return 0; } |
// Double buffering with dual-port RAM
// Uses single-port RAM to write switches to a section while reading from the same section to control LEDs,
// so each switch acts as if connected directly to the corresponding LED.
// Flip SW0 to change sections.
module top (
input clk,
input [15:0] sw,
output [15:0] led,
// not used
input rx,
output tx
);
assign tx = rx; // TODO(#658): Remove this work-around
wire [5:0] addr;
wire ram_out;
wire ram_in;
RAM_SHIFTER #(
.IO_WIDTH(16),
.ADDR_WIDTH(6)
) shifter (
.clk(clk),
.in(sw),
.out(led),
.addr(addr),
.ram_out(ram_out),
.ram_in(ram_in)
);
RAM128X1S #(
.INIT(128'h96A5_96A5_96A5_96A5_96A5_96A5_96A5_96A5)
) ram0 (
.WCLK(clk),
.A6(sw[0]),
.A5(addr[5]),
.A4(addr[4]),
.A3(addr[3]),
.A2(addr[2]),
.A1(addr[1]),
.A0(addr[0]),
.O(ram_out),
.D(ram_in),
.WE(1'b1)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKBUF_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__CLKBUF_FUNCTIONAL_PP_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__clkbuf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKBUF_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; map<long long int, map<long long int, bool> > my; int main() { long long int n; cin >> n; my[1][n] = 1; if (n % 2 == 0) { cout << white << endl; cout << 1 << << 2 << endl; } else cout << black << endl; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFBBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__DFBBP_FUNCTIONAL_PP_V
/**
* dfbbp: Delay flop, inverted set, inverted reset,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dfb_setdom_pg/sky130_fd_sc_hs__u_dfb_setdom_pg.v"
`celldefine
module sky130_fd_sc_hs__dfbbp (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
// Local signals
wire RESET ;
wire SET ;
wire buf_Q ;
wire CLK_delayed ;
wire RESET_B_delayed;
wire SET_B_delayed ;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
sky130_fd_sc_hs__u_dfb_setdom_pg `UNIT_DELAY u_dfb_setdom_pg0 (buf_Q , SET, RESET, CLK, D, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFBBP_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; int main() { int n, tmp, curr = 0; cin >> n; int v[n], res[n]; for (int i = 0; i < n; i++) { cin >> tmp; v[tmp] = i + 1; } for (int i = 0; i < n; i++) { cin >> tmp; if (v[tmp] > curr) { res[i] = v[tmp] - curr; curr = v[tmp]; } else res[i] = 0; } for (int i = 0; i < n; i++) cout << res[i] << ; } |
#include <bits/stdc++.h> using namespace std; long long int modularPower(long long int x, unsigned long long int y, long long int mod) { long long int res = 1; x %= mod; while (y > 0) { if (y & 1) res = (res * x) % mod; y >>= 1; x = (x * x) % mod; } return res; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cerr.tie(NULL); cout.tie(NULL); ; int height; cin >> height; vector<int> v(height + 5); vector<int> sum(height + 5); int posOfChange = 0; for (int i = 0; i <= height; ++i) { int foo; cin >> foo; v[i] = foo; } while (posOfChange < height and (v[posOfChange] == 1 or v[posOfChange + 1] == 1)) posOfChange++; if (posOfChange == height) { cout << perfect ; return 0; } sum[0] = 1; for (int i = 1; i < v.size(); ++i) { sum[i] = sum[i - 1] + v[i - 1]; } cout << ambiguous << n ; cout << 0 << ; for (int i = 1; i <= height; ++i) { for (int j = 0; j < v[i]; ++j) { cout << sum[i - 1] << ; } } cout << n << 0 << ; for (int i = 1; i <= height; ++i) { if (i == posOfChange + 1) { cout << sum[i - 1] + 1 << ; for (int j = 1; j < v[i]; ++j) { cout << sum[i - 1] << ; } } else { for (int j = 0; j < v[i]; ++j) { cout << sum[i - 1] << ; } } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 100100; int n; vector<pair<int, int>> a; int main() { scanf( %d , &n); for (int i = 0; i < n; ++i) { int x, y; scanf( %d%d , &x, &y); a.emplace_back(x, 1); a.emplace_back(y + 1, -1); } sort(a.begin(), a.end()); int k = 0; for (auto p : a) { k += p.second; if (k > 2) { puts( NO ); return 0; } } puts( YES ); return 0; } |
// cpu interface
module cpu_if
(
input CLK,
input RESET_X,
// CPU
input [7:0] ADR,
output reg [31:0] RDATA,
input RD,
input WR,
input [31:0] WDATA,
output reg INT,
//REGISTERS
output reg SOFT_RESET,
output reg START,
input FINISH,
//input RUNNING
output reg [1:0] OP, // 0:ADD 1:MUL 2:RQT
output reg [1:0] MSEL_INPUTA_SEL,
output reg [1:0] MSEL_INPUTB_SEL,
output reg [1:0] MSEL_OUTPUTC_SEL,
output reg INV_ASEL,
output reg INV_BSEL,
output reg [31:0] M0VAL,
output reg [9:0] M1POS,
output reg [9:0] M1SIZE,
output reg [9:0] M2POS,
output reg [9:0] M2SIZE,
output reg [9:0] M3POS,
output reg [9:0] M3SIZE,
//ADD
output reg [31:0] AD_GAIN,
output reg [31:0] AD_QPARAM,
//MULL CORE
output reg [31:0] MLC_GAGB,
output reg [31:0] MLC_GAOB,
output reg [31:0] MLC_GBOA,
// MULL ADD1
output reg [31:0] ML1_GAIN,
output reg [31:0] ML1_QPARAM,
output reg [31:0] ML2_GAIN,
output reg [31:0] ML2_QPARAM,
output reg [7:0] REQ_MID,
output reg [31:0] REQ_GAIN,
input [15:0] RMAX,
input [15:0] RMIN
);
reg run_r;
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
INT <= 0;
end else begin
INT <= FINISH;
end
end
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
START <= 0;
SOFT_RESET <= 0;
end else begin
if((ADR==8'h00) && WR)begin
START <= WDATA[1];
SOFT_RESET <= WDATA[0];
end else begin
START <= 0;
SOFT_RESET <= 0;
end
end
end
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
run_r <= 0;
end else begin
if(START)begin
run_r <= 1;
end else if(FINISH)begin
run_r <= 0;
end
end
end
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
OP <= 0;
end else begin
if((ADR==8'h08) && WR)begin
OP <= WDATA[1:0];
end
end
end
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
MSEL_INPUTA_SEL <= 0;
MSEL_INPUTB_SEL <= 0;
MSEL_OUTPUTC_SEL <= 0;
end else begin
if((ADR==8'h0C) && WR)begin
MSEL_INPUTA_SEL <= WDATA[1:0];
MSEL_INPUTB_SEL <= WDATA[3:2];
MSEL_OUTPUTC_SEL <= WDATA[5:4];
end
end
end
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
INV_ASEL <= 0;
INV_BSEL <= 0;
end else begin
if((ADR==8'h10) && WR)begin
INV_ASEL <= WDATA[0];
INV_BSEL <= WDATA[1];
end
end
end
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
M0VAL <= 0;
end else begin
if((ADR==8'h14) && WR)begin
M0VAL <= 0;
end
end
end
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
M1POS <= 0;
end else begin
if((ADR==8'h20) && WR)begin
M1POS <= WDATA[9:0];
end
end
end
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
M1SIZE <= 0;
end else begin
if((ADR==8'h24) && WR)begin
M1SIZE <= WDATA[9:0];
end
end
end
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
M2POS <= 0;
end else begin
if((ADR==8'h30) && WR)begin
M2POS <= WDATA[9:0];
end
end
end
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
M2SIZE <= 0;
end else begin
if((ADR==8'h34) && WR)begin
M2SIZE <= WDATA[9:0];
end
end
end
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
M3POS <= 0;
end else begin
if((ADR==8'h40) && WR)begin
M2POS <= WDATA[9:0];
end
end
end
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
M3SIZE <= 0;
end else begin
if((ADR==8'h44) && WR)begin
M3SIZE <= WDATA[9:0];
end
end
end
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
AD_GAIN <= 0;
end else begin
if((ADR==8'h50) && WR)begin
AD_GAIN <= WDATA;
end
end
end
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
AD_QPARAM <= 0;
end else begin
if((ADR==8'h54) && WR)begin
AD_QPARAM <= WDATA;
end
end
end
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
MLC_GAGB <= 0;
end else begin
if((ADR==8'h60) && WR)begin
MLC_GAGB <= WDATA;
end
end
end
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
MLC_GAOB <= 0;
end else begin
if((ADR==8'h64) && WR)begin
MLC_GAOB <= WDATA;
end
end
end
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
MLC_GBOA <= 0;
end else begin
if((ADR==8'h68) && WR)begin
MLC_GBOA <= WDATA;
end
end
end
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
ML1_GAIN <= 0;
end else begin
if((ADR==8'h70) && WR)begin
ML1_GAIN <= WDATA;
end
end
end
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
ML1_QPARAM <= 0;
end else begin
if((ADR==8'h74) && WR)begin
ML1_QPARAM <= WDATA;
end
end
end
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
ML2_GAIN <= 0;
end else begin
if((ADR==8'h78) && WR)begin
ML2_GAIN <= WDATA;
end
end
end
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
ML2_QPARAM <= 0;
end else begin
if((ADR==8'h7C) && WR)begin
ML2_QPARAM <= WDATA;
end
end
end
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
REQ_MID <= 0;
end else begin
if((ADR==8'h80) && WR)begin
REQ_MID <= WDATA[7:0];
end
end
end
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
REQ_GAIN <= 0;
end else begin
if((ADR==8'h84) && WR)begin
REQ_GAIN <= WDATA;
end
end
end
// RDATA
always @ (posedge CLK or negedge RESET_X) begin
if (RESET_X==0)begin
RDATA <= 0;
end else begin
if(RD)begin
case (ADR)
8'h04:begin
RDATA[31:2] <= 30'h00000000;
RDATA[1] <= run_r;
RDATA[0] <= FINISH;
end
8'hC0: begin
RDATA[31:16] <= 24'h000000;
RDATA[15:0] <= RMAX;
end
8'hC4: begin
RDATA[31:16] <= 24'h000000;
RDATA[15:0] <= RMIN;
end
default: RDATA <= 0;
endcase // case ADR
end
end
end
endmodule // cpu_if
|
`timescale 1ns / 1ns
module menc_parser
(input c,
input [7:0] rxd,
input rxdv,
input direction,
output [31:0] enc_usecs,
output [31:0] enc_angle,
output [31:0] enc_vel,
output [15:0] enc_raw,
output [2:0] halls,
output [31:0] temp_celsius);
wire [6:0] byte_cnt;
r #(7) byte_cnt_r
(.c(c), .en(rxdv), .rst(~rxdv), .d(byte_cnt+1'b1), .q(byte_cnt));
wire [31:0] shift;
r #(32) shift_r
(.c(c), .rst(1'b0), .en(1'b1), .d({rxd, shift[31:8]}), .q(shift));
r #(32) enc_usecs_r
(.c(c), .rst(1'b0), .en(byte_cnt == 7'd8), .d(shift), .q(enc_usecs));
r #(32) enc_angle_r
(.c(c), .rst(1'b0), .en(byte_cnt == 7'd20), .d(shift), .q(enc_angle));
r #(32) enc_vel_r
(.c(c), .rst(1'b0), .en(byte_cnt == 7'd24), .d(shift), .q(enc_vel));
r #(16) enc_raw_r
(.c(c), .rst(1'b0), .en(byte_cnt == 7'd36),
.d(direction ? 16'd16383 - shift[15:0] : shift[15:0]), .q(enc_raw));
r #(3) halls_r
(.c(c), .rst(1'b0), .en(byte_cnt == 7'd40), .d(shift[2:0]), .q(halls));
r #(32) temp_celsius_r
(.c(c), .rst(1'b0), .en(byte_cnt == 7'd44), .d(shift), .q(temp_celsius));
endmodule
|
/*
* BCH Encode/Decoder Modules
*
* Copyright 2014 - Russ Dill <>
* Distributed under 2-clause BSD license as contained in COPYING file.
*/
`timescale 1ns / 1ps
`include "config.vh"
`include "bch_defs.vh"
/*
* Calculate syndrome method 1:
*
* S_j = r_0 + alpha^j * (r_1 + alpha^j * ...(r_(n-2) + alpha^j * r_(n-1))...)
*
* 0: z = n - 1, accumulator = 0
* 1: accumulator += r_z
* 2: accumulator *= alpha^j
* 3: z = z - 1
* 4: z >= 0 -> goto 1
*
* takes n cycles
*/
module dsynN_method1 #(
parameter [`BCH_PARAM_SZ-1:0] P = `BCH_SANE,
parameter SYN = 0,
parameter BITS = 1,
parameter REG_RATIO = BITS > 8 ? 8 : BITS,
parameter PIPELINE_STAGES = 0
) (
input clk,
input start, /* Accept first bit of syndrome */
input start_pipelined, /* Start delayed by one if there are
* two pipeline stages */
input ce,
input [BITS-1:0] data_pipelined, /* One stage delay (if necessary) */
output reg [`BCH_M(P)-1:0] synN = 0
);
`include "bch.vh"
localparam TCQ = 1;
localparam M = `BCH_M(P);
localparam signed SKIP = `BCH_K(P) - `BCH_DATA_BITS(P);
localparam LPOW_S_BITS = lpow(M, `BCH_N(P) - (SYN * BITS) % `BCH_N(P));
localparam REGS = (BITS + REG_RATIO - 1) / REG_RATIO;
if (PIPELINE_STAGES > 2)
dsynN_method1_only_supports_2_pipeline_stage u_dm1os2ps();
if (REG_RATIO > BITS)
syndrome_reg_ratio_must_be_less_than_or_equal_to_bits u_srrmbltoeqb();
function [REGS*M-1:0] pow_initial;
input dummy;
integer i;
begin
for (i = 0; i < REGS; i = i + 1)
pow_initial[i*M+:M] = lpow(M, `BCH_N(P) - (SYN * (SKIP + BITS - i * REG_RATIO)) % `BCH_N(P));
end
endfunction
localparam [REGS*M-1:0] POW_INITIAL = pow_initial(0);
/*
* Reduce pow reg size by only having a reg for every other,
* or every 4th, etc register, filling in the others with async logic
*/
reg [REGS*M-1:0] pow = POW_INITIAL;
wire [REGS*M-1:0] pow_next;
wire [REGS*M-1:0] pow_curr;
wire [BITS*M-1:0] pow_all;
wire [BITS*M-1:0] terms;
wire [M-1:0] terms_summed;
wire [M-1:0] terms_summed_pipelined;
genvar i;
/* Not enough pipeline stages for set/reset, must use mux */
assign pow_curr = (PIPELINE_STAGES < 2 && start) ? POW_INITIAL : pow;
for (i = 0; i < BITS; i = i + 1) begin : GEN_TERMS
wire [M-1:0] curr = pow_curr[(i/REG_RATIO)*M+:M];
if (!(i % REG_RATIO))
assign pow_all[i*M+:M] = curr;
else begin
localparam [M-1:0] LPOW = lpow(M, (SYN * (i % REG_RATIO)) % `BCH_N(P));
if (`CONFIG_CONST_OP)
parallel_standard_multiplier_const1 #(M, LPOW) u_mult(
.standard_in(curr),
.standard_out(pow_all[i*M+:M])
);
else
parallel_standard_multiplier #(M) u_mult(
.standard_in1(LPOW),
.standard_in2(curr),
.standard_out(pow_all[i*M+:M])
);
end
assign terms[i*M+:M] = data_pipelined[i] ? pow_all[i*M+:M] : 0;
end
if (`CONFIG_CONST_OP)
parallel_standard_multiplier_const1 #(M, LPOW_S_BITS[M-1:0]) u_mult [REGS-1:0] (
.standard_in(pow_curr),
.standard_out(pow_next)
);
else
parallel_standard_multiplier #(M) u_mult [REGS-1:0] (
.standard_in1(LPOW_S_BITS[M-1:0]),
.standard_in2(pow_curr),
.standard_out(pow_next)
);
finite_parallel_adder #(M, BITS) u_adder(
.in(terms),
.out(terms_summed)
);
pipeline_ce #(PIPELINE_STAGES > 0) u_summed_pipeline [M-1:0] (
.clk(clk),
.ce(ce),
.i(terms_summed),
.o(terms_summed_pipelined)
);
always @(posedge clk) begin
if (ce) begin
/* Utilize set/reset signal if possible */
pow <= #TCQ (PIPELINE_STAGES > 1 && start) ? POW_INITIAL : pow_next;
if (start_pipelined)
synN <= #TCQ PIPELINE_STAGES ? 0 : terms_summed_pipelined;
else
synN <= #TCQ synN ^ terms_summed_pipelined;
end
end
endmodule
module syndrome_expand_method1 #(
parameter [`BCH_PARAM_SZ-1:0] P = `BCH_SANE
) (
input [`BCH_M(P)-1:0] in,
output [`BCH_M(P)-1:0] out
);
localparam M = `BCH_M(P);
assign out = in;
endmodule
|
`define Rotary_NOP 4'h0
`define Rotary_RDLS 4'h1
`define Rotary_RDRS 4'h2
`define Rotary_State_Reset 2'h0
`define Rotary_State_Ready 2'h1
`define Rotary_State_Error 2'h2
module Rotary(clock,reset,inst,inst_en,rotary,rotary_left_status,rotary_right_status);
input wire clock;
input wire reset;
input wire [11:0] inst;
input wire inst_en;
input wire [1:0] rotary;
output wire rotary_left_status;
output wire rotary_right_status;
reg [1:0] s_State;
reg s_IntRotaryLeftStatus;
reg s_OutRotaryLeftStatus;
reg s_IntRotaryRightStatus;
reg s_OutRotaryRightStatus;
wire [3:0] w_InstCode;
wire rotaryint_rotary_left;
wire rotaryint_rotary_right;
reg [256*8-1:0] d_Input;
reg [256*8-1:0] d_State;
assign rotary_left_status = s_OutRotaryLeftStatus;
assign rotary_right_status = s_OutRotaryRightStatus;
assign w_InstCode = inst[11:8];
RotaryInterface
rotaryint (.clock(clock),
.reset(reset),
.rotary(rotary),
.rotary_left(rotaryint_rotary_left),
.rotary_right(rotaryint_rotary_right));
always @ (posedge clock) begin
if (reset) begin
s_State <= `Rotary_State_Reset;
s_IntRotaryLeftStatus <= 0;
s_OutRotaryLeftStatus <= 0;
s_IntRotaryRightStatus <= 0;
s_OutRotaryRightStatus <= 0;
end
else begin
case (s_State)
`Rotary_State_Reset: begin
s_State <= `Rotary_State_Ready;
s_IntRotaryLeftStatus <= 0;
s_OutRotaryLeftStatus <= 0;
s_IntRotaryRightStatus <= 0;
s_OutRotaryRightStatus <= 0;
end
`Rotary_State_Ready: begin
if (inst_en) begin
case (w_InstCode)
`Rotary_NOP: begin
s_State <= `Rotary_State_Ready;
s_IntRotaryLeftStatus <= rotaryint_rotary_left | s_IntRotaryLeftStatus;
s_OutRotaryLeftStatus <= s_OutRotaryLeftStatus;
s_IntRotaryRightStatus <= rotaryint_rotary_right | s_IntRotaryRightStatus;
s_OutRotaryRightStatus <= s_OutRotaryRightStatus;
end
`Rotary_RDLS: begin
s_State <= `Rotary_State_Ready;
s_IntRotaryLeftStatus <= rotaryint_rotary_left | 0;
s_OutRotaryLeftStatus <= s_IntRotaryLeftStatus;
s_IntRotaryRightStatus <= rotaryint_rotary_right | s_IntRotaryRightStatus;
s_OutRotaryRightStatus <= s_OutRotaryRightStatus;
end
`Rotary_RDRS: begin
s_State <= `Rotary_State_Ready;
s_IntRotaryLeftStatus <= rotaryint_rotary_left | s_IntRotaryLeftStatus;
s_OutRotaryLeftStatus <= s_OutRotaryLeftStatus;
s_IntRotaryRightStatus <= rotaryint_rotary_right | 0;
s_OutRotaryRightStatus <= s_IntRotaryRightStatus;
end
default: begin
s_State <= `Rotary_State_Error;
s_IntRotaryLeftStatus <= 0;
s_OutRotaryLeftStatus <= 0;
s_IntRotaryRightStatus <= 0;
s_OutRotaryRightStatus <= 0;
end
endcase // case (w_InstCode)
end // if (inst_en)
else begin
s_State <= `Rotary_State_Ready;
s_IntRotaryLeftStatus <= rotaryint_rotary_left | s_IntRotaryLeftStatus;
s_OutRotaryLeftStatus <= s_OutRotaryLeftStatus;
s_IntRotaryRightStatus <= rotaryint_rotary_right | s_IntRotaryRightStatus;
s_OutRotaryRightStatus <= s_OutRotaryRightStatus;
end // else: !if(inst_en)
end // case: `Rotary_State_Ready
`Rotary_State_Error: begin
s_State <= `Rotary_State_Error;
s_IntRotaryLeftStatus <= 0;
s_OutRotaryLeftStatus <= 0;
s_IntRotaryRightStatus <= 0;
s_OutRotaryRightStatus <= 0;
end
default: begin
s_State <= `Rotary_State_Error;
s_IntRotaryLeftStatus <= 0;
s_OutRotaryLeftStatus <= 0;
s_IntRotaryRightStatus <= 0;
s_OutRotaryRightStatus <= 0;
end
endcase // case (s_State)
end // else: !if(reset)
end // always @ (posedge clock)
`ifdef SIM
always @ * begin
if (inst_en) begin
case (w_InstCode)
`Rotary_NOP: begin
$sformat(d_Input,"EN NOP");
end
`Rotary_RDLS: begin
$sformat(d_Input,"EN RDLS");
end
`Rotary_RDRS: begin
$sformat(d_Input,"EN RDRS");
end
default: begin
$sformat(d_Input,"EN (? %2X)",inst[7:0]);
end
endcase // case (w_InstCode)
end // if (inst_en)
else begin
$sformat(d_Input,"NN");
end // else: !if(inst_en)
end // always @ *
always @ * begin
case (s_State)
`Rotary_State_Reset: begin
$sformat(d_State,"X");
end
`Rotary_State_Ready: begin
case ({s_IntRotaryLeftStatus,s_OutRotaryLeftStatus,s_IntRotaryRightStatus,s_OutRotaryRightStatus})
4'b0000: begin
$sformat(d_State,"R F F F F %2B %1B %1B",rotary,rotaryint_rotary_left,rotaryint_rotary_right);
end
4'b0001: begin
$sformat(d_State,"R F F F T %2B %1B %1B",rotary,rotaryint_rotary_left,rotaryint_rotary_right);
end
4'b0010: begin
$sformat(d_State,"R F F T F %2B %1B %1B",rotary,rotaryint_rotary_left,rotaryint_rotary_right);
end
4'b0011: begin
$sformat(d_State,"R F F T T %2B %1B %1B",rotary,rotaryint_rotary_left,rotaryint_rotary_right);
end
4'b0100: begin
$sformat(d_State,"R F T F F %2B %1B %1B",rotary,rotaryint_rotary_left,rotaryint_rotary_right);
end
4'b0101: begin
$sformat(d_State,"R F T F T %2B %1B %1B",rotary,rotaryint_rotary_left,rotaryint_rotary_right);
end
4'b0110: begin
$sformat(d_State,"R F T T F %2B %1B %1B",rotary,rotaryint_rotary_left,rotaryint_rotary_right);
end
4'b0111: begin
$sformat(d_State,"R F T T T %2B %1B %1B",rotary,rotaryint_rotary_left,rotaryint_rotary_right);
end
4'b1000: begin
$sformat(d_State,"R T F F F %2B %1B %1B",rotary,rotaryint_rotary_left,rotaryint_rotary_right);
end
4'b1001: begin
$sformat(d_State,"R T F F T %2B %1B %1B",rotary,rotaryint_rotary_left,rotaryint_rotary_right);
end
4'b1010: begin
$sformat(d_State,"R T F T F %2B %1B %1B",rotary,rotaryint_rotary_left,rotaryint_rotary_right);
end
4'b1011: begin
$sformat(d_State,"R T F T T %2B %1B %1B",rotary,rotaryint_rotary_left,rotaryint_rotary_right);
end
4'b1100: begin
$sformat(d_State,"R T T F F %2B %1B %1B",rotary,rotaryint_rotary_left,rotaryint_rotary_right);
end
4'b1101: begin
$sformat(d_State,"R T T F T %2B %1B %1B",rotary,rotaryint_rotary_left,rotaryint_rotary_right);
end
4'b1110: begin
$sformat(d_State,"R T T T F %2B %1B %1B",rotary,rotaryint_rotary_left,rotaryint_rotary_right);
end
4'b1111: begin
$sformat(d_State,"R T T T T %2B %1B %1B",rotary,rotaryint_rotary_left,rotaryint_rotary_right);
end
endcase // case ({s_IntRotaryLeftStatus,s_OutRotaryLeftStatus,s_IntRotaryRightStatus,s_OutRotaryRightStatus})
end // case: `Rotary_State_Ready
`Rotary_State_Error: begin
$sformat(d_State,"E");
end
default: begin
$sformat(d_State,"?");
end
endcase // case (s_State)
end // always @ *
`endif // `ifdef SIM
endmodule // Rotary
|
/*
File: eproto_tx.v
This file is part of the Parallella Project.
Copyright (C) 2014 Adapteva, Inc.
Contributed by Fred Huettig <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
/*
########################################################################
EPIPHANY eLink TX Protocol block
########################################################################
This block takes standard eMesh protocol (104-bit transactions) and
encodes the bytes into 8-byte parallel outputs for the output
serializers.
*/
module eproto_tx (/*AUTOARG*/
// Outputs
emtx_rd_wait, emtx_wr_wait, emtx_ack, txframe_p, txdata_p,
// Inputs
reset, emtx_access, emtx_write, emtx_datamode, emtx_ctrlmode,
emtx_dstaddr, emtx_srcaddr, emtx_data, txlclk_p, tx_rd_wait,
tx_wr_wait
);
// System reset input
input reset;
// Input from TX Arbiter
input emtx_access;
input emtx_write;
input [1:0] emtx_datamode;
input [3:0] emtx_ctrlmode;
input [31:0] emtx_dstaddr;
input [31:0] emtx_srcaddr;
input [31:0] emtx_data;
output emtx_rd_wait;
output emtx_wr_wait;
output emtx_ack;
// Parallel interface, 8 eLink bytes at a time
input txlclk_p; // Parallel-rate clock from eClock block
output [7:0] txframe_p;
output [63:0] txdata_p;
input tx_rd_wait; // The wait signals are passed through
input tx_wr_wait; // to the emesh interfaces
//#############
//# Configuration bits
//#############
//############
//# Local regs & wires
//############
reg emtx_ack; // Acknowledge transaction
reg [7:0] txframe_p;
reg [63:0] txdata_p;
//############
//# Logic
//############
// TODO: Bursts
always @( posedge txlclk_p or posedge reset ) begin
if( reset ) begin
emtx_ack <= 1'b0;
txframe_p <= 'd0;
txdata_p <= 'd0;
end else begin
if( emtx_access & ~emtx_ack ) begin
emtx_ack <= 1'b1;
txframe_p <= 8'h3F;
txdata_p <=
{ 8'd0, // Not used
8'd0,
~emtx_write, 7'd0, // B0- TODO: For bursts, add the inc bit
emtx_ctrlmode, emtx_dstaddr[31:28], // B1
emtx_dstaddr[27:4], // B2, B3, B4
emtx_dstaddr[3:0], emtx_datamode, emtx_write, emtx_access // B5
};
end else if( emtx_ack ) begin // if ( emtx_access & ~emtx_ack )
emtx_ack <= 1'b0;
txframe_p <= 8'hFF;
txdata_p <= { emtx_data, emtx_srcaddr };
end else begin
emtx_ack <= 1'b0;
txframe_p <= 8'h00;
txdata_p <= 64'd0;
end
end // else: !if( reset )
end // always @ ( posedge txlclk_p or reset )
//#############################
//# Wait signals
//#############################
reg rd_wait_sync;
reg wr_wait_sync;
reg emtx_rd_wait;
reg emtx_wr_wait;
always @( posedge txlclk_p ) begin
rd_wait_sync <= tx_rd_wait;
emtx_rd_wait <= rd_wait_sync;
wr_wait_sync <= tx_wr_wait;
emtx_wr_wait <= wr_wait_sync;
end
endmodule // eproto_tx
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_nios2_qsys_0_jtag_debug_slave_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
nios_system_nios2_qsys_0_jtag_debug_slave_tck the_nios_system_nios2_qsys_0_jtag_debug_slave_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
nios_system_nios2_qsys_0_jtag_debug_slave_sysclk the_nios_system_nios2_qsys_0_jtag_debug_slave_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic nios_system_nios2_qsys_0_jtag_debug_slave_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam nios_system_nios2_qsys_0_jtag_debug_slave_phy.sld_auto_instance_index = "YES",
// nios_system_nios2_qsys_0_jtag_debug_slave_phy.sld_instance_index = 0,
// nios_system_nios2_qsys_0_jtag_debug_slave_phy.sld_ir_width = 2,
// nios_system_nios2_qsys_0_jtag_debug_slave_phy.sld_mfg_id = 70,
// nios_system_nios2_qsys_0_jtag_debug_slave_phy.sld_sim_action = "",
// nios_system_nios2_qsys_0_jtag_debug_slave_phy.sld_sim_n_scan = 0,
// nios_system_nios2_qsys_0_jtag_debug_slave_phy.sld_sim_total_length = 0,
// nios_system_nios2_qsys_0_jtag_debug_slave_phy.sld_type_id = 34,
// nios_system_nios2_qsys_0_jtag_debug_slave_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
#include <bits/stdc++.h> using namespace std; bool debug; const int inf = 1e9 + 5; const int nax = 205; int k; namespace MinCost { struct Edge { int w, c, v, rev; Edge(int _w, int _c, int _v, int _rev) : w(_w), c(_c), v(_v), rev(_rev) {} }; int odl[nax], pot[nax], pop[nax], pop_kraw[nax]; vector<Edge> v[nax]; bool bylo[nax]; void init(int n) { for (int i = 0; i <= n; ++i) v[i].clear(); } void AddEdge(int a, int b, int cap, int cost) { v[a].push_back(Edge(b, cap, cost, int(v[b].size()) + (a == b))); v[b].push_back(Edge(a, 0, -cost, int(v[a].size() - 1))); } pair<int, int> MinCostMaxFlow(int s, int t, int n) { int flow = 0, cost = 0; for (int i = 0; i <= n; ++i) pot[i] = 0; while (true) { for (int i = 0; i <= n; ++i) { odl[i] = inf; bylo[i] = false; } odl[s] = 0; for (int k = 0; k <= (n)-1; ++k) { int x = 0; int najm = inf; for (int i = 0; i <= n; ++i) if (!bylo[i] && najm > odl[i]) { x = i; najm = odl[i]; } bylo[x] = true; int dl = v[x].size(); for (int i = 0; i <= (dl)-1; ++i) if (v[x][i].c > 0 && odl[v[x][i].w] > odl[x] + pot[x] - pot[v[x][i].w] + v[x][i].v) { odl[v[x][i].w] = odl[x] + pot[x] - pot[v[x][i].w] + v[x][i].v; pop[v[x][i].w] = x; pop_kraw[v[x][i].w] = i; } } if (odl[t] == inf) break; for (int i = 0; i <= n; ++i) pot[i] += odl[i]; int x = t; int cap = inf; while (x != s) { cap = min(cap, v[pop[x]][pop_kraw[x]].c); x = pop[x]; } x = t; int one_path_cost = 0; while (x != s) { one_path_cost += v[pop[x]][pop_kraw[x]].v; v[pop[x]][pop_kraw[x]].c -= cap; v[x][v[pop[x]][pop_kraw[x]].rev].c += cap; x = pop[x]; } int ile_zmiesci = one_path_cost ? (k - cost) / one_path_cost : inf; cost += min(cap, ile_zmiesci) * one_path_cost; flow += min(cap, ile_zmiesci); if (ile_zmiesci < cap) break; } return make_pair(flow, cost); } }; // namespace MinCost using namespace MinCost; int n, a; int main(int argc, char* argv[]) { scanf( %d%d , &n, &k); init(n - 1); for (int i = 0; i <= (n)-1; ++i) for (int j = 0; j <= (n)-1; ++j) { scanf( %d , &a); if (a > 0) { AddEdge(i, j, a, 0); AddEdge(i, j, k, 1); } } printf( %d n , MinCostMaxFlow(0, n - 1, n - 1).first); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A31OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__A31OI_FUNCTIONAL_PP_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__a31oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y , B1, and0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A31OI_FUNCTIONAL_PP_V |
module top;
reg pass = 1'b1;
reg signed [7:0] arr [0:7];
integer idx;
reg signed [1:0] idx2;
reg [7:0] res;
real rarr [0:7];
real rres;
reg signed [2:0] a [0:3];
wire signed [2:0] n [0:3];
assign n[3] = 0;
assign n[0] = -1;
initial for (idx = 0; idx < 8 ; idx = idx + 1) rarr[idx] = idx+1.0;
initial for (idx = 0; idx < 8 ; idx = idx + 1) arr[idx] = idx+1;
initial begin
#1;
idx = 'bx;
// Test %load/ar
rres = rarr[idx];
if (rres != 0.0) begin
$display("Failed simple real array test, got %f.", rres);
pass = 1'b0;
end
// Test %load/av
res = arr[idx];
if (res !== 8'bx) begin
$display("Failed simple array vector test, got %b.", res);
pass = 1'b0;
end
// Test %load/avp0
res = arr[idx]+8'b1;
if (res !== 8'bx) begin
$display("Failed array vector plus constant test, got %b.", res);
pass = 1'b0;
end
// Test %load/avp0/s
res = arr[idx]+8'sb1;
if (res !== 8'bx) begin
$display("Failed array vector plus signed constant test, got %b.", res);
pass = 1'b0;
end
// Test %load/avx.p with a 'bx array select.
res = arr[idx][0];
if (res !== 8'b0x) begin
$display("Failed array vector bit select test 1, got %b.", res);
pass = 1'b0;
end
// Test %load/avx.p with a 'bx bit select.
res = arr[0][idx];
if (res !== 8'b0x) begin
$display("Failed array vector bit select test 2, got %b.", res);
pass = 1'b0;
end
// Test %load/avx.p with a negative bit select.
idx2 = -1;
res = arr[0][idx2];
if (res !== 8'b0x) begin
$display("Failed array vector bit select test 3, got %b.", res);
pass = 1'b0;
end
// This should be out of bounds and should be 'bx, but if this
// is being loaded as an unsigned value it will return 1.
idx2 = -1;
a[3] = 0;
a[0] = -1;
res = arr[a[idx2]];
if (res !== 8'bx) begin
$display("Failed: reg array select driving array select, got %b", res);
pass = 1'b0;
end
// The same here, but check a net array.
res = arr[n[idx2]];
if (res !== 8'bx) begin
$display("Failed: wire array select driving array select, got %b", res);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A41O_LP_V
`define SKY130_FD_SC_LP__A41O_LP_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog wrapper for a41o with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a41o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a41o_lp (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a41o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a41o_lp (
X ,
A1,
A2,
A3,
A4,
B1
);
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a41o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A41O_LP_V
|
Subsets and Splits