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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR2_BEHAVIORAL_V
`define SKY130_FD_SC_MS__OR2_BEHAVIORAL_V
/**
* or2: 2-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__or2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR2_BEHAVIORAL_V |
// todo
module sim_conditioner();
// INPUTS
// OUTPUTS
// INOUTS
`include "parameters_global.v"
//`include "parameters_ram.v"
// SIGNAL DECLARATIONS EXTERNAL
reg CLK_MASTER;
reg CPU_RESET_N;
reg PWR_CTRL_PWR_FAIL_N;
wire uut_pwr_fail;
initial
begin
CLK_MASTER = 0;
CPU_RESET_N = 1;
PWR_CTRL_PWR_FAIL_N = 1;
#20
CPU_RESET_N = 0;
#80
CPU_RESET_N = 1;
#200
PWR_CTRL_PWR_FAIL_N = 0;
#100
PWR_CTRL_PWR_FAIL_N = 1;
end
always #10 CLK_MASTER = ~CLK_MASTER; // 50Mhz main clock // period 20ns
conditioner co1 (
.clk(CLK_MASTER),
.reset_n(CPU_RESET_N),
.input_async(PWR_CTRL_PWR_FAIL_N), // driven by pwr_ctrl. if HL-edge -> power fail alarm
.output_edge(uut_pwr_fail), // H for one clock period when edge detected
.edge_detect(edge_falling) // input, set to edge_detect falling edge
);
endmodule
|
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* 1G Ethernet MAC with GMII interface
*/
module eth_mac_1g_gmii #
(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// IODDR style ("IODDR", "IODDR2")
// Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale
// Use IODDR2 for Spartan-6
parameter IODDR_STYLE = "IODDR2",
// Clock input style ("BUFG", "BUFR", "BUFIO", "BUFIO2")
// Use BUFR for Virtex-5, Virtex-6, 7-series
// Use BUFG for Ultrascale
// Use BUFIO2 for Spartan-6
parameter CLOCK_INPUT_STYLE = "BUFIO2",
parameter ENABLE_PADDING = 1,
parameter MIN_FRAME_LENGTH = 64
)
(
input wire gtx_clk,
input wire gtx_rst,
output wire rx_clk,
output wire rx_rst,
output wire tx_clk,
output wire tx_rst,
/*
* AXI input
*/
input wire [7:0] tx_axis_tdata,
input wire tx_axis_tvalid,
output wire tx_axis_tready,
input wire tx_axis_tlast,
input wire tx_axis_tuser,
/*
* AXI output
*/
output wire [7:0] rx_axis_tdata,
output wire rx_axis_tvalid,
output wire rx_axis_tlast,
output wire rx_axis_tuser,
/*
* GMII interface
*/
input wire gmii_rx_clk,
input wire [7:0] gmii_rxd,
input wire gmii_rx_dv,
input wire gmii_rx_er,
input wire mii_tx_clk,
output wire gmii_tx_clk,
output wire [7:0] gmii_txd,
output wire gmii_tx_en,
output wire gmii_tx_er,
/*
* Status
*/
output wire tx_error_underflow,
output wire rx_error_bad_frame,
output wire rx_error_bad_fcs,
output wire [1:0] speed,
/*
* Configuration
*/
input wire [7:0] ifg_delay
);
wire [7:0] mac_gmii_rxd;
wire mac_gmii_rx_dv;
wire mac_gmii_rx_er;
wire [7:0] mac_gmii_txd;
wire mac_gmii_tx_en;
wire mac_gmii_tx_er;
reg [1:0] speed_reg = 2'b10;
reg mii_select_reg = 1'b0;
(* srl_style = "register" *)
reg [1:0] tx_mii_select_sync = 2'd0;
always @(posedge tx_clk) begin
tx_mii_select_sync <= {tx_mii_select_sync[0], mii_select_reg};
end
(* srl_style = "register" *)
reg [1:0] rx_mii_select_sync = 2'd0;
always @(posedge rx_clk) begin
rx_mii_select_sync <= {rx_mii_select_sync[0], mii_select_reg};
end
// PHY speed detection
reg [2:0] rx_prescale = 3'd0;
always @(posedge rx_clk) begin
rx_prescale <= rx_prescale + 3'd1;
end
(* srl_style = "register" *)
reg [2:0] rx_prescale_sync = 3'd0;
always @(posedge gtx_clk) begin
rx_prescale_sync <= {rx_prescale_sync[1:0], rx_prescale[2]};
end
reg [6:0] rx_speed_count_1 = 0;
reg [1:0] rx_speed_count_2 = 0;
always @(posedge gtx_clk) begin
if (gtx_rst) begin
rx_speed_count_1 <= 0;
rx_speed_count_2 <= 0;
speed_reg <= 2'b10;
mii_select_reg <= 1'b0;
end else begin
rx_speed_count_1 <= rx_speed_count_1 + 1;
if (rx_prescale_sync[1] ^ rx_prescale_sync[2]) begin
rx_speed_count_2 <= rx_speed_count_2 + 1;
end
if (&rx_speed_count_1) begin
// reference count overflow - 10M
rx_speed_count_1 <= 0;
rx_speed_count_2 <= 0;
speed_reg <= 2'b00;
mii_select_reg <= 1'b1;
end
if (&rx_speed_count_2) begin
// prescaled count overflow - 100M or 1000M
rx_speed_count_1 <= 0;
rx_speed_count_2 <= 0;
if (rx_speed_count_1[6:5]) begin
// large reference count - 100M
speed_reg <= 2'b01;
mii_select_reg <= 1'b1;
end else begin
// small reference count - 1000M
speed_reg <= 2'b10;
mii_select_reg <= 1'b0;
end
end
end
end
assign speed = speed_reg;
gmii_phy_if #(
.TARGET(TARGET),
.IODDR_STYLE(IODDR_STYLE),
.CLOCK_INPUT_STYLE(CLOCK_INPUT_STYLE)
)
gmii_phy_if_inst (
.clk(gtx_clk),
.rst(gtx_rst),
.mac_gmii_rx_clk(rx_clk),
.mac_gmii_rx_rst(rx_rst),
.mac_gmii_rxd(mac_gmii_rxd),
.mac_gmii_rx_dv(mac_gmii_rx_dv),
.mac_gmii_rx_er(mac_gmii_rx_er),
.mac_gmii_tx_clk(tx_clk),
.mac_gmii_tx_rst(tx_rst),
.mac_gmii_txd(mac_gmii_txd),
.mac_gmii_tx_en(mac_gmii_tx_en),
.mac_gmii_tx_er(mac_gmii_tx_er),
.phy_gmii_rx_clk(gmii_rx_clk),
.phy_gmii_rxd(gmii_rxd),
.phy_gmii_rx_dv(gmii_rx_dv),
.phy_gmii_rx_er(gmii_rx_er),
.phy_mii_tx_clk(mii_tx_clk),
.phy_gmii_tx_clk(gmii_tx_clk),
.phy_gmii_txd(gmii_txd),
.phy_gmii_tx_en(gmii_tx_en),
.phy_gmii_tx_er(gmii_tx_er),
.mii_select(mii_select_reg)
);
eth_mac_1g #(
.ENABLE_PADDING(ENABLE_PADDING),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH)
)
eth_mac_1g_inst (
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.gmii_rxd(mac_gmii_rxd),
.gmii_rx_dv(mac_gmii_rx_dv),
.gmii_rx_er(mac_gmii_rx_er),
.gmii_txd(mac_gmii_txd),
.gmii_tx_en(mac_gmii_tx_en),
.gmii_tx_er(mac_gmii_tx_er),
.rx_clk_enable(1'b1),
.tx_clk_enable(1'b1),
.rx_mii_select(rx_mii_select_sync[1]),
.tx_mii_select(tx_mii_select_sync[1]),
.tx_error_underflow(tx_error_underflow),
.rx_error_bad_frame(rx_error_bad_frame),
.rx_error_bad_fcs(rx_error_bad_fcs),
.ifg_delay(ifg_delay)
);
endmodule
`resetall
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_ram
(
data,
rdaddress,
wraddress,
wren, clock,
q
);
parameter DATA_WIDTH=36;
parameter ADDR_WIDTH=8;
input [(DATA_WIDTH-1):0] data;
input [(ADDR_WIDTH-1):0] rdaddress, wraddress;
input wren, clock;
output reg [(DATA_WIDTH-1):0] q;
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
always @ (posedge clock)
begin
if (wren)
ram[wraddress] <= data[DATA_WIDTH-1:0];
q <= ram[rdaddress];
end
endmodule
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Dual ported RAM for Harvard architecture processors
// Does no forwarding
// Addresses are byte-oriented, so botton 2 address bits are ignored. FIXME
// AWIDTH of 13 gives 8K bytes. For Spartan 3, if the total RAM size is not a
// multiple of 8K then BRAM space is wasted
module ram_wb_harvard #(parameter AWIDTH=13)
(input wb_clk_i,
input wb_rst_i,
input [AWIDTH-1:0] iwb_adr_i,
input [31:0] iwb_dat_i,
output reg [31:0] iwb_dat_o,
input iwb_we_i,
output reg iwb_ack_o,
input iwb_stb_i,
input [3:0] iwb_sel_i,
input [AWIDTH-1:0] dwb_adr_i,
input [31:0] dwb_dat_i,
output reg [31:0] dwb_dat_o,
input dwb_we_i,
output reg dwb_ack_o,
input dwb_stb_i,
input [3:0] dwb_sel_i);
reg [7:0] ram0 [0:(1<<(AWIDTH-2))-1];
reg [7:0] ram1 [0:(1<<(AWIDTH-2))-1];
reg [7:0] ram2 [0:(1<<(AWIDTH-2))-1];
reg [7:0] ram3 [0:(1<<(AWIDTH-2))-1];
// Instruction Read Port
always @(posedge wb_clk_i)
iwb_ack_o <= iwb_stb_i & ~iwb_ack_o;
always @(posedge wb_clk_i)
iwb_dat_o[31:24] <= ram3[iwb_adr_i[AWIDTH-1:2]];
always @(posedge wb_clk_i)
iwb_dat_o[23:16] <= ram2[iwb_adr_i[AWIDTH-1:2]];
always @(posedge wb_clk_i)
iwb_dat_o[15:8] <= ram1[iwb_adr_i[AWIDTH-1:2]];
always @(posedge wb_clk_i)
iwb_dat_o[7:0] <= ram0[iwb_adr_i[AWIDTH-1:2]];
always @(posedge wb_clk_i)
if(iwb_we_i & iwb_stb_i & iwb_sel_i[3])
ram3[iwb_adr_i[AWIDTH-1:2]] <= iwb_dat_i[31:24];
always @(posedge wb_clk_i)
if(iwb_we_i & iwb_stb_i & iwb_sel_i[2])
ram2[iwb_adr_i[AWIDTH-1:2]] <= iwb_dat_i[23:16];
always @(posedge wb_clk_i)
if(iwb_we_i & iwb_stb_i & iwb_sel_i[1])
ram1[iwb_adr_i[AWIDTH-1:2]] <= iwb_dat_i[15:8];
always @(posedge wb_clk_i)
if(iwb_we_i & iwb_stb_i & iwb_sel_i[0])
ram0[iwb_adr_i[AWIDTH-1:2]] <= iwb_dat_i[7:0];
// Data Port
always @(posedge wb_clk_i)
dwb_ack_o <= dwb_stb_i & ~dwb_ack_o;
always @(posedge wb_clk_i)
dwb_dat_o[31:24] <= ram3[dwb_adr_i[AWIDTH-1:2]];
always @(posedge wb_clk_i)
dwb_dat_o[23:16] <= ram2[dwb_adr_i[AWIDTH-1:2]];
always @(posedge wb_clk_i)
dwb_dat_o[15:8] <= ram1[dwb_adr_i[AWIDTH-1:2]];
always @(posedge wb_clk_i)
dwb_dat_o[7:0] <= ram0[dwb_adr_i[AWIDTH-1:2]];
always @(posedge wb_clk_i)
if(dwb_we_i & dwb_stb_i & dwb_sel_i[3])
ram3[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[31:24];
always @(posedge wb_clk_i)
if(dwb_we_i & dwb_stb_i & dwb_sel_i[2])
ram2[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[23:16];
always @(posedge wb_clk_i)
if(dwb_we_i & dwb_stb_i & dwb_sel_i[1])
ram1[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[15:8];
always @(posedge wb_clk_i)
if(dwb_we_i & dwb_stb_i & dwb_sel_i[0])
ram0[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[7:0];
endmodule // ram_wb_harvard
|
#include <bits/stdc++.h> using namespace std; int main() { int n, x, y; cin >> n >> x >> y; string num; cin >> num; num = num.substr(num.length() - x, x); cout << count(num.begin(), num.end() - y - 1, 1 ) + count(num.end() - y, num.end(), 1 ) + (*(num.end() - y - 1) == 1 ? 0 : 1); return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC optimize( unroll-loops ) #pragma GCC optimize( -ffloat-store ) #pragma GCC optimize( -fno-defer-pop ) long long power(long long a, long long b, long long m) { if (b == 0) return 1; if (b == 1) return a % m; long long t = power(a, b / 2, m); t = (t * t) % m; if (b & 1) t = (t * a) % m; return t; } using namespace std; int main() { ; ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; long long t; cin >> t; while (t--) { long long a, b, c, d; cin >> a >> b >> c >> d; long long x, y, x1, y1, x2, y2; cin >> x >> y >> x1 >> y1 >> x2 >> y2; if (x2 - x1 == 0 && (a != 0 || b != 0)) { cout << NO << endl; continue; } if (y2 - y1 == 0 && (c != 0 || d != 0)) { cout << NO << endl; continue; } long long disx, disy; disx = b - a; disy = d - c; if (0 <= disx) { if (x2 - x < disx) { cout << NO << endl; continue; } } else { if (x - x1 < (-disx)) { cout << NO << endl; continue; } } if (0 <= disy) { if (y2 - y < disy) { cout << NO << endl; continue; } } else { if (y - y1 < (-disy)) { cout << NO << endl; continue; } } cout << YES << endl; } } |
#include <bits/stdc++.h> using namespace std; void ans(int n, int p) { if (n == 5) { assert(p == 0); for (int i = int(1); i <= int(n); i++) { printf( %d %d n , i, i + 1 > n ? i + 1 - n : i + 1); printf( %d %d n , i, i + 2 > n ? i + 2 - n : i + 2); } return; } int prevMaxP = (n - 1) * (n - 2) / 2 - 2 * (n - 1); if (prevMaxP < p) { for (int i = int(0); i < int(2 + p - prevMaxP); i++) printf( %d %d n , 1 + i, n); ans(n - 1, prevMaxP); } else { for (int i = int(0); i < int(2); i++) printf( %d %d n , 1 + i, n); ans(n - 1, p); } } int main() { ios_base::sync_with_stdio(false); int t; cin >> t; for (int i = int(0); i < int(t); i++) { int n, p; cin >> n >> p; ans(n, p); } return 0; } |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_adcfifo_rd (
// request and synchronization
dma_xfer_req,
// read interface
axi_rd_req,
axi_rd_addr,
// axi interface
axi_clk,
axi_resetn,
axi_arvalid,
axi_arid,
axi_arburst,
axi_arlock,
axi_arcache,
axi_arprot,
axi_arqos,
axi_aruser,
axi_arlen,
axi_arsize,
axi_araddr,
axi_arready,
axi_rvalid,
axi_rid,
axi_ruser,
axi_rresp,
axi_rlast,
axi_rdata,
axi_rready,
// axi status
axi_rerror,
// fifo interface
axi_drst,
axi_dvalid,
axi_ddata,
axi_dready);
// parameters
parameter AXI_DATA_WIDTH = 512;
parameter AXI_SIZE = 2;
parameter AXI_LENGTH = 16;
parameter AXI_ADDRESS = 32'h00000000;
parameter AXI_ADDRLIMIT = 32'h00000000;
localparam AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8;
localparam AXI_AWINCR = AXI_LENGTH * AXI_BYTE_WIDTH;
localparam BUF_THRESHOLD_LO = 6'd3;
localparam BUF_THRESHOLD_HI = 6'd60;
// request and synchronization
input dma_xfer_req;
// read interface
input axi_rd_req;
input [ 31:0] axi_rd_addr;
// axi interface
input axi_clk;
input axi_resetn;
output axi_arvalid;
output [ 3:0] axi_arid;
output [ 1:0] axi_arburst;
output axi_arlock;
output [ 3:0] axi_arcache;
output [ 2:0] axi_arprot;
output [ 3:0] axi_arqos;
output [ 3:0] axi_aruser;
output [ 7:0] axi_arlen;
output [ 2:0] axi_arsize;
output [ 31:0] axi_araddr;
input axi_arready;
input axi_rvalid;
input [ 3:0] axi_rid;
input [ 3:0] axi_ruser;
input [ 1:0] axi_rresp;
input axi_rlast;
input [AXI_DATA_WIDTH-1:0] axi_rdata;
output axi_rready;
// axi status
output axi_rerror;
// fifo interface
output axi_drst;
output axi_dvalid;
output [AXI_DATA_WIDTH-1:0] axi_ddata;
input axi_dready;
// internal registers
reg [ 31:0] axi_rd_addr_h = 'd0;
reg axi_rd = 'd0;
reg axi_rd_active = 'd0;
reg [ 2:0] axi_xfer_req_m = 'd0;
reg axi_xfer_init = 'd0;
reg axi_xfer_enable = 'd0;
reg axi_arvalid = 'd0;
reg [ 31:0] axi_araddr = 'd0;
reg axi_drst = 'd0;
reg axi_dvalid = 'd0;
reg [AXI_DATA_WIDTH-1:0] axi_ddata = 'd0;
reg axi_rready = 'd0;
reg axi_rerror = 'd0;
// internal signals
wire axi_ready_s;
// read is way too slow- buffer mode
assign axi_ready_s = (~axi_arvalid | axi_arready) & axi_dready;
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_rd_addr_h <= 'd0;
axi_rd <= 'd0;
axi_rd_active <= 'd0;
axi_xfer_req_m <= 'd0;
axi_xfer_init <= 'd0;
axi_xfer_enable <= 'd0;
end else begin
if (axi_xfer_init == 1'b1) begin
axi_rd_addr_h <= AXI_ADDRESS;
end else if (axi_rd_req == 1'b1) begin
axi_rd_addr_h <= axi_rd_addr;
end
if (axi_rd_active == 1'b1) begin
axi_rd <= 1'b0;
if ((axi_rvalid == 1'b1) && (axi_rlast == 1'b1)) begin
axi_rd_active <= 1'b0;
end
end else if ((axi_ready_s == 1'b1) && (axi_araddr < axi_rd_addr_h)) begin
axi_rd <= axi_xfer_enable;
axi_rd_active <= axi_xfer_enable;
end
axi_xfer_req_m <= {axi_xfer_req_m[1:0], dma_xfer_req};
axi_xfer_init <= axi_xfer_req_m[1] & ~axi_xfer_req_m[2];
axi_xfer_enable <= axi_xfer_req_m[2];
end
end
// address channel
assign axi_arid = 4'b0000;
assign axi_arburst = 2'b01;
assign axi_arlock = 1'b0;
assign axi_arcache = 4'b0010;
assign axi_arprot = 3'b000;
assign axi_arqos = 4'b0000;
assign axi_aruser = 4'b0001;
assign axi_arlen = AXI_LENGTH - 1;
assign axi_arsize = AXI_SIZE;
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_arvalid <= 'd0;
axi_araddr <= 'd0;
end else begin
if (axi_arvalid == 1'b1) begin
if (axi_arready == 1'b1) begin
axi_arvalid <= 1'b0;
end
end else begin
if (axi_rd == 1'b1) begin
axi_arvalid <= 1'b1;
end
end
if (axi_xfer_init == 1'b1) begin
axi_araddr <= AXI_ADDRESS;
end else if ((axi_arvalid == 1'b1) && (axi_arready == 1'b1)) begin
axi_araddr <= axi_araddr + AXI_AWINCR;
end
end
end
// read data channel
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_drst <= 'd1;
axi_dvalid <= 'd0;
axi_ddata <= 'd0;
axi_rready <= 'd0;
end else begin
axi_drst <= ~axi_xfer_req_m[1];
axi_dvalid <= axi_rvalid;
axi_ddata <= axi_rdata;
axi_rready <= 1'b1;
end
end
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_rerror <= 'd0;
end else begin
axi_rerror <= axi_rvalid & axi_rresp[1];
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; long long q; long long n, k, a, b; int main() { cin >> q; while (q--) { cin >> k >> n >> a >> b; long long l = 0, r = n, mid, ans = -1; while (l <= r) { mid = (l + r) / 2; if (mid * a + (n - mid) * b >= k) r = mid - 1; else l = mid + 1, ans = mid; } cout << ans << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); int y, w; cin >> y >> w; int ans; ans; if (y >= w) { ans = 6 - y + 1; } else if (w >= y) { ans = 6 - w + 1; } if (ans == 6) { cout << 1 << / << 1 << endl; } if (ans == 1) { cout << 1 << / << 6 << endl; } if (ans == 2) { cout << 1 << / << 3 << endl; } if (ans == 3) { cout << 1 << / << 2 << endl; } if (ans == 4) { cout << 2 << / << 3 << endl; } if (ans == 5) { cout << 5 << / << 6 << endl; } return 0; } |
// DESCRIPTION: Verilator: Test generate index usage.
//
// The code illustrates a problem in Verilator's handling of constant
// expressions inside generate indexes.
//
// This is a regression test against issue 517.
//
// **If you do not wish for your code to be released to the public
// please note it here, otherwise:**
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Jeremy Bennett.
`define START 8
`define SIZE 4
`define END (`START + `SIZE)
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [`END-1:0] y;
wire [`END-1:0] x;
foo foo_i (.y (y),
.x (x),
.clk (clk));
always @(posedge clk) begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule // t
module foo(output wire [`END-1:0] y,
input wire [`END-1:0] x,
input wire clk);
function peek_bar;
peek_bar = bar_inst[`START].i_bar.r; // this is ok
peek_bar = bar_inst[`START + 1].i_bar.r; // this fails, should not.
endfunction
genvar g;
generate
for (g = `START; g < `END; g = g + 1) begin: bar_inst
bar i_bar(.x (x[g]),
.y (y[g]),
.clk (clk));
end
endgenerate
endmodule : foo
module bar(output wire y,
input wire x,
input wire clk);
reg r = 0;
assign y = r;
always @(posedge clk) begin
r = x ? ~x : y;
end
endmodule : bar
|
#include <bits/stdc++.h> using namespace std; map<int, long long> x, y; map<pair<int, int>, long long> xy; int main() { int n; cin >> n; while (n--) { int xx, yy; cin >> xx >> yy; x[xx]++; y[yy]++; xy[make_pair(xx, yy)]++; } long long ans = 0; for (auto i : x) { ans += i.second * (i.second - 1) / 2; } for (auto i : y) { ans += i.second * (i.second - 1) / 2; } for (auto i : xy) { ans -= i.second * (i.second - 1) / 2; } cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; const int inf = ~0u >> 1, mod = (int)(1e9) + 7; int n, m; long long pow2[555 * 555], f[555][555]; int main() { scanf( %d%d , &n, &m); pow2[0] = 1ll; for (int i = 0; i < (int)500 * 500; ++i) pow2[i + 1] = (pow2[i] * 2ll) % mod; f[0][0] = 1ll; for (int k = 0; k < (int)m; ++k) { for (int i = 1; i <= n; ++i) for (int j = 0; j < i; ++j) { long long tmp = f[j][k]; tmp = tmp * (pow2[i - j] - 1) % mod; tmp = tmp * (pow2[j * (i - j)]) % mod; f[i][k + 1] = (f[i][k + 1] + tmp) % mod; } } long long ans = 0; for (int i = 1; i <= n; ++i) ans = (ans + f[i][m] * pow2[i * (n - i)] % mod) % mod; if (m) cout << ans << endl; else cout << 1; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m; char a[60][60], b[60][60]; int dir[4][2] = {0, 1, 1, 0, -1, 0, 0, -1}; struct node { int x, y, sum; }; node ans[2600]; bool cmp(node a, node b) { return a.sum < b.sum; } int bfs(int x, int y) { queue<node> q; node t, next; t.x = x; t.y = y; q.push(t); int cnt = 1; a[x][y] = * ; while (!q.empty()) { t = q.front(); q.pop(); for (int i = 0; i < 4; i++) { int tx = t.x + dir[i][0]; int ty = t.y + dir[i][1]; if (tx < 0 || ty < 0 || tx >= n || ty >= m) { cnt = -1e9; continue; } if (a[tx][ty] == * ) continue; a[tx][ty] = * ; next.x = tx; next.y = ty; cnt++; q.push(next); } } return cnt; } void bfs2(int x, int y) { queue<node> q; node t, next; t.x = x; t.y = y; q.push(t); b[x][y] = * ; while (!q.empty()) { t = q.front(); q.pop(); for (int i = 0; i < 4; i++) { int tx = t.x + dir[i][0]; int ty = t.y + dir[i][1]; if (b[tx][ty] == * ) continue; b[tx][ty] = * ; next.x = tx; next.y = ty; q.push(next); } } } int main(void) { int i, j, k; while (scanf( %d%d%d , &n, &m, &k) == 3) { for (i = 0; i < n; i++) { scanf( %s , a[i]); strcpy(b[i], a[i]); } int c = 0; for (i = 0; i < n; i++) for (j = 0; j < m; j++) if (a[i][j] == . ) { int t = bfs(i, j); if (t > 0) { ans[c].x = i; ans[c].y = j; ans[c].sum = t; c++; } } sort(ans, ans + c, cmp); int sum = 0; for (i = 0; i < c - k; i++) { sum += ans[i].sum; bfs2(ans[i].x, ans[i].y); } printf( %d n , sum); for (i = 0; i < n; i++) printf( %s n , b[i]); } } |
`include "../include/tune.v"
// PentEvo project (c) NedoPC 2008-2009
//
// DRAM controller. performs accesses to DRAM.
//
// state: | RD1 | RD2 | RD3 | RD4 | WR1 | WR2 | WR3 | WR4 | RFSH1 | RFSH2 | RFSH3 | RFSH4 |
// clk: ___/```\___/```\___/```\___/```\___/```\___/```\___/```\___/```\___/```\___/```\___/```\___/```\___/```\___/```\__
// | READ CYCLE | WRITE CYCLE | REFRESH CYCLE |
// ras: ```````````````````\_______________/```````````````\_______________/```````````````````````\_______________/
// cas: ```````````````````````````\_______________/```````````````\_______________/```````\_______________/````````
// ra: | row | column| | row | column|
// rd: XXXXXXXXXXXXXXXXXXXXXXXXX<read data read| write data write data write |
// rwe: `````````````````````````````````````````\_______________________________/````````````````````````````````
// req: __/```````\_______________________/```````\________________________________________________________________
// rnw: XX/```````\XXXXXXXXXXXXXXXXXXXXXXX\_______/XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
// cbeg: __________/```````\_______________________/```````\_______________________/```````\_______________________/
// rrdy: __________________________________/```````\________________________________________________________________
// addr: XX< addr >XXXXXXXXXXXXXXXXXXXXXXX< addr >XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
//wrdata:XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX< write >XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
//rddata:XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX< read >XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
//
// comments:
// rucas_n, rlcas_n, rras0_n, rras1_n, rwe_n could be made 'fast output register'
// ra[] couldn't be such in acex1k, because output registers could be all driven only by
// single clock polarity (and here they are driven by negative edge, while CAS/RAS by positive)
//
// rst_n is resynced before use and acts as req inhibit. so while in reset, dram regenerates and isn't corrupted
module dram(
input clk,
input rst_n, // shut down accesses, remain refresh
output reg [9:0] ra, // to the DRAM pins
inout [15:0] rd, // . .
// . .
output reg rwe_n, // . .
output reg rucas_n, // . .
output reg rlcas_n, // . .
output reg rras0_n, // . .
output reg rras1_n, // to the DRAM pins
input [20:0] addr, // access address of 16bit word: addr[0] selects between rras0_n and rras1_n,
// addr[10:1] goes to row address, addr[20:11] goes to column address
input req, // request for read/write cycle
input rnw, // READ/nWRITE (=1: read, =0: write)
output reg cbeg, // cycle begin (any including refresh), can be used for synchronizing
output reg rrdy, // Read data ReaDY
output reg [15:0] rddata, // data just read
input [15:0] wrdata, // data to be written
input [1:0] bsel // positive byte select for write: bsel[0] is for wrdata[7:0], bsel[1] is for wrdata[15:8]
);
reg [1:0] rst_sync;
wire reset;
wire int_req;
reg [20:0] int_addr;
reg [15:0] int_wrdata;
reg [1:0] int_bsel;
reg rfsh_alt; // we must alternate chips in refresh cycles to lower total heating
reg [3:0] state;
reg [3:0] next_state;
localparam RD1 = 0;
localparam RD2 = 1;
localparam RD3 = 2;
localparam RD4 = 3;
localparam WR1 = 4;
localparam WR2 = 5;
localparam WR3 = 6;
localparam WR4 = 7;
localparam RFSH1 = 8;
localparam RFSH2 = 9;
localparam RFSH3 = 10;
localparam RFSH4 = 11;
initial
begin
state = RFSH1; // for simulation only!
rfsh_alt = 1'b0;
end
/*
`ifdef SIMULATE
always @(posedge clk)
begin
if( req && !rnw && (state==RD4 || state==WR4 || state==RFSH4) )
begin
$display("written word %x mask %x to address %x",wrdata&{ {8{bsel[1]}}, {8{bsel[0]}} },{ {8{bsel[1]}}, {8{bsel[0]}} },addr);
end
end
`endif
*/
always @(posedge clk)
begin
state <= next_state;
end
always @*
case( state )
RD1:
next_state = RD2;
RD2:
next_state = RD3;
RD3:
next_state = RD4;
RD4:
if( !int_req )
next_state = RFSH1;
else
next_state = rnw?RD1:WR1;
WR1:
next_state = WR2;
WR2:
next_state = WR3;
WR3:
next_state = WR4;
WR4:
if( !int_req )
next_state = RFSH1;
else
next_state = rnw?RD1:WR1;
RFSH1:
next_state = RFSH2;
RFSH2:
next_state = RFSH3;
RFSH3:
next_state = RFSH4;
RFSH4:
if( !int_req )
next_state = RFSH1;
else
next_state = rnw?RD1:WR1;
endcase
// incoming data latching
always @(posedge clk)
begin
if( (state==RD4) || (state==WR4) || (state==RFSH4) )
begin
int_addr <= addr;
int_wrdata <= wrdata;
int_bsel <= bsel;
end
end
// WE control
always @(posedge clk)
begin
if( (next_state==WR1) || (next_state==WR2) || (next_state==WR3) || (next_state==WR4) )
rwe_n <= 1'b0;
else
rwe_n <= 1'b1;
end
// RAS/CAS sequencing
always @(posedge clk)
begin
case( state )
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
RD1:
begin
rras0_n <= int_addr[0];
rras1_n <= ~int_addr[0];
end
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
RD2:
begin
rucas_n <= 1'b0;
rlcas_n <= 1'b0;
end
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
RD3:
begin
rras0_n <= 1'b1;
rras1_n <= 1'b1;
end
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
RD4:
begin
rras0_n <= 1'b1;
rras1_n <= 1'b1;
rucas_n <= 1'b1;
rlcas_n <= 1'b1;
end
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
WR1:
begin
rras0_n <= int_addr[0];
rras1_n <= ~int_addr[0];
end
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
WR2:
begin
rucas_n <= ~int_bsel[1];
rlcas_n <= ~int_bsel[0];
end
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
WR3:
begin
rras0_n <= 1'b1;
rras1_n <= 1'b1;
end
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
WR4:
begin
rras0_n <= 1'b1;
rras1_n <= 1'b1;
rucas_n <= 1'b1;
rlcas_n <= 1'b1;
end
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
RFSH1:
begin
rucas_n <= 1'b0;
rlcas_n <= 1'b0;
end
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
RFSH2:
begin
rras0_n <= rfsh_alt;
rras1_n <= ~rfsh_alt;
rfsh_alt <= ~rfsh_alt;
end
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
RFSH3:
begin
rucas_n <= 1'b1;
rlcas_n <= 1'b1;
end
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
RFSH4:
begin
rras0_n <= 1'b1;
rras1_n <= 1'b1;
rucas_n <= 1'b1;
rlcas_n <= 1'b1;
end
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
endcase
end
// row/column address multiplexing
always @(negedge clk)
begin
if( (state==RD1) || (state==WR1) )
ra <= int_addr[10:1];
else
ra <= int_addr[20:11];
end
// DRAM data bus control
assign rd = rwe_n ? 16'hZZZZ : int_wrdata;
// read data from DRAM
always @(posedge clk)
begin
if( state==RD3 )
rddata <= rd;
end
// cbeg and rrdy control
always @(posedge clk)
begin
if( (state==RD4) || (state==WR4) || (state==RFSH4) )
cbeg <= 1'b1;
else
cbeg <= 1'b0;
if( state==RD3 )
rrdy <= 1'b1;
else
rrdy <= 1'b0;
end
// reset must be synchronous here in order to preserve
// DRAM state while other modules reset, but we have only
// asynchronous one globally. so we must re-synchronize it
// and use it as 'DRAM operation enable'. when in reset,
// controller ignores req signal and generates only refresh cycles
always @(posedge clk)
rst_sync[1:0] <= { rst_sync[0], ~rst_n };
assign reset = rst_sync[1];
assign int_req = req & (~reset);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; for (int i = 0; i < t; i++) { int n; cin >> n; int sum = 0, odd = 0, even = 0; for (int i = 0; i < n; i++) { int x; cin >> x; if (x % 2 == 0) { even++; } else { odd++; } sum += x; } if (sum % 2 == 1) { cout << YES n ; } else { if (odd < n && odd > 0) { cout << YES n ; } else { cout << NO n ; } } } return 0; } |
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
wire valid_test_expr;
assign valid_test_expr = ~(test_expr ^ test_expr);
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`ifdef OVL_ASSERT_ON
always @(`OVL_RESET_SIGNAL or test_expr) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin
if (test_expr == 1'b0) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression is FALSE");
end
end
end // always
`endif // OVL_ASSERT_ON
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_ASSERT_ON
always @(`OVL_RESET_SIGNAL or valid_test_expr)
begin
if (`OVL_RESET_SIGNAL != 1'b0)
begin
if (valid_test_expr == 1'b1)
begin
// Do nothing
end
else
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
end
`endif // OVL_ASSERT_ON
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
|
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
`ifdef BSV_RESET_FIFO_HEAD
`define BSV_RESET_EDGE_HEAD or `BSV_RESET_EDGE dRST
`else
`define BSV_RESET_EDGE_HEAD
`endif
// A version of SyncFIFO for zero-width data
//
// A clock synchronization FIFO where the enqueue and dequeue sides are in
// different clock domains.
// There are no restrictions w.r.t. clock frequencies
// The depth of the FIFO must be a power of 2 (2,4,8,...) since the
// indexing uses a Gray code counter.
// FULL and EMPTY signal are pessimistic, that is, they are asserted
// immediately when the FIFO becomes FULL or EMPTY, but their deassertion
// is delayed due to synchronization latency.
module SyncFIFO0(
sCLK,
sRST,
dCLK,
sENQ,
sFULL_N,
dDEQ,
dEMPTY_N
) ;
parameter depth = 2 ; // minimum 2
parameter indxWidth = 1 ; // minimum 1
// input clock domain ports
input sCLK ;
input sRST ;
input sENQ ;
output sFULL_N ;
// destination clock domain ports
input dCLK ;
input dDEQ ;
output dEMPTY_N ;
// constants for bit masking of the gray code
wire [indxWidth : 0] msbset = ~({(indxWidth + 1){1'b1}} >> 1) ;
wire [indxWidth - 1 : 0] msb2set = ~({(indxWidth + 0){1'b1}} >> 1) ;
wire [indxWidth : 0] msb12set = msbset | {1'b0, msb2set} ; // 'b11000...
// Enqueue Pointer support
reg [indxWidth +1 : 0] sGEnqPtr, sGEnqPtr1 ; // Flops
reg sNotFullReg ;
wire sNextNotFull, sFutureNotFull ;
// Dequeue Pointer support
reg [indxWidth+1 : 0] dGDeqPtr, dGDeqPtr1 ; // Flops
reg dNotEmptyReg ;
wire dNextNotEmpty;
// Reset generation
wire dRST ;
// flops to sychronize enqueue and dequeue point across domains
reg [indxWidth : 0] dSyncReg1, dEnqPtr ;
reg [indxWidth : 0] sSyncReg1, sDeqPtr ;
wire [indxWidth - 1 :0] sEnqPtrIndx, dDeqPtrIndx ;
// Resets
assign dRST = sRST ;
// Outputs
assign dEMPTY_N = dNotEmptyReg ;
assign sFULL_N = sNotFullReg ;
// Indexes are truncated from the Gray counter with parity
assign sEnqPtrIndx = sGEnqPtr[indxWidth-1:0];
assign dDeqPtrIndx = dGDeqPtr[indxWidth-1:0];
////////////////////////////////////////////////////////////////////////
// Enqueue Pointer and increment logic
assign sNextNotFull = (sGEnqPtr [indxWidth+1:1] ^ msb12set) != sDeqPtr ;
assign sFutureNotFull = (sGEnqPtr1[indxWidth+1:1] ^ msb12set) != sDeqPtr ;
always @(posedge sCLK or `BSV_RESET_EDGE sRST)
begin
if (sRST == `BSV_RESET_VALUE)
begin
sGEnqPtr <= `BSV_ASSIGNMENT_DELAY {(indxWidth +2 ) {1'b0}} ;
sGEnqPtr1 <= `BSV_ASSIGNMENT_DELAY { {indxWidth {1'b0}}, 2'b11} ;
sNotFullReg <= `BSV_ASSIGNMENT_DELAY 1'b0 ; // Mark as full during reset to avoid spurious loads
end // if (sRST == `BSV_RESET_VALUE)
else
begin
if ( sENQ )
begin
sGEnqPtr1 <= `BSV_ASSIGNMENT_DELAY incrGrayP( sGEnqPtr1 ) ;
sGEnqPtr <= `BSV_ASSIGNMENT_DELAY sGEnqPtr1 ;
sNotFullReg <= `BSV_ASSIGNMENT_DELAY sFutureNotFull ;
end // if ( sENQ )
else
begin
sNotFullReg <= `BSV_ASSIGNMENT_DELAY sNextNotFull ;
end // else: !if( sENQ )
end // else: !if(sRST == `BSV_RESET_VALUE)
end // always @ (posedge sCLK or `BSV_RESET_EDGE sRST)
// Enqueue pointer synchronizer to dCLK
always @(posedge dCLK or `BSV_RESET_EDGE dRST)
begin
if (dRST == `BSV_RESET_VALUE)
begin
dSyncReg1 <= `BSV_ASSIGNMENT_DELAY {(indxWidth + 1) {1'b0}} ;
dEnqPtr <= `BSV_ASSIGNMENT_DELAY {(indxWidth + 1) {1'b0}} ;
end // if (dRST == `BSV_RESET_VALUE)
else
begin
dSyncReg1 <= `BSV_ASSIGNMENT_DELAY sGEnqPtr[indxWidth+1:1] ; // Clock domain crossing
dEnqPtr <= `BSV_ASSIGNMENT_DELAY dSyncReg1 ;
end // else: !if(dRST == `BSV_RESET_VALUE)
end // always @ (posedge dCLK or `BSV_RESET_EDGE dRST)
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Enqueue Pointer and increment logic
assign dNextNotEmpty = dGDeqPtr[indxWidth+1:1] != dEnqPtr ;
always @(posedge dCLK or `BSV_RESET_EDGE dRST)
begin
if (dRST == `BSV_RESET_VALUE)
begin
dGDeqPtr <= `BSV_ASSIGNMENT_DELAY {(indxWidth + 2) {1'b0}} ;
dGDeqPtr1 <= `BSV_ASSIGNMENT_DELAY {{indxWidth {1'b0}}, 2'b11 } ;
dNotEmptyReg <= `BSV_ASSIGNMENT_DELAY 1'b0 ;
end // if (dRST == `BSV_RESET_VALUE)
else
begin
if ((!dNotEmptyReg || dDEQ) && dNextNotEmpty) begin
dGDeqPtr <= `BSV_ASSIGNMENT_DELAY dGDeqPtr1 ;
dGDeqPtr1 <= `BSV_ASSIGNMENT_DELAY incrGrayP( dGDeqPtr1 );
dNotEmptyReg <= `BSV_ASSIGNMENT_DELAY 1'b1;
end
else if (dDEQ && !dNextNotEmpty) begin
dNotEmptyReg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end
end // else: !if(dRST == `BSV_RESET_VALUE)
end // always @ (posedge dCLK or `BSV_RESET_EDGE dRST)
// Dequeue pointer synchronized to sCLK
always @(posedge sCLK or `BSV_RESET_EDGE sRST)
begin
if (sRST == `BSV_RESET_VALUE)
begin
sSyncReg1 <= `BSV_ASSIGNMENT_DELAY {(indxWidth + 1) {1'b0}} ;
sDeqPtr <= `BSV_ASSIGNMENT_DELAY {(indxWidth + 1) {1'b0}} ; // When reset mark as not empty
end // if (sRST == `BSV_RESET_VALUE)
else
begin
sSyncReg1 <= `BSV_ASSIGNMENT_DELAY dGDeqPtr[indxWidth+1:1] ; // clock domain crossing
sDeqPtr <= `BSV_ASSIGNMENT_DELAY sSyncReg1 ;
end // else: !if(sRST == `BSV_RESET_VALUE)
end // always @ (posedge sCLK or `BSV_RESET_EDGE sRST)
////////////////////////////////////////////////////////////////////////
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin : initBlock
integer i ;
// initialize the pointer
sGEnqPtr = {((indxWidth + 2)/2){2'b10}} ;
sGEnqPtr1 = sGEnqPtr ;
sNotFullReg = 1'b0 ;
dGDeqPtr = sGEnqPtr ;
dGDeqPtr1 = sGEnqPtr ;
dNotEmptyReg = 1'b0;
// initialize other registers
sSyncReg1 = sGEnqPtr ;
sDeqPtr = sGEnqPtr ;
dSyncReg1 = sGEnqPtr ;
dEnqPtr = sGEnqPtr ;
end // block: initBlock
// synopsys translate_on
// synopsys translate_off
initial
begin : parameter_assertions
integer ok ;
integer i, expDepth ;
ok = 1;
expDepth = 1 ;
// calculate x = 2 ** (indxWidth - 1)
for( i = 0 ; i < indxWidth ; i = i + 1 )
begin
expDepth = expDepth * 2 ;
end // for ( i = 0 ; i < indxWidth ; i = i + 1 )
if ( expDepth != depth )
begin
ok = 0;
$display ( "ERROR SyncFiFO0.v: index size and depth do not match;" ) ;
$display ( "\tdepth must equal 2 ** index size. expected %0d", expDepth );
end
#0
if ( ok == 0 ) $finish ;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
function [indxWidth+1:0] incrGrayP ;
input [indxWidth+1:0] grayPin;
begin: incrGrayPBlock
reg [indxWidth :0] g;
reg p ;
reg [indxWidth :0] i;
g = grayPin[indxWidth+1:1];
p = grayPin[0];
i = incrGray (g,p);
incrGrayP = {i,~p};
end
endfunction
function [indxWidth:0] incrGray ;
input [indxWidth:0] grayin;
input parity ;
begin: incrGrayBlock
integer i;
reg [indxWidth: 0] tempshift;
reg [indxWidth: 0] flips;
flips[0] = ! parity ;
for ( i = 1 ; i < indxWidth ; i = i+1 )
begin
tempshift = grayin << (2 + indxWidth - i ) ;
flips[i] = parity & grayin[i-1] & ~(| tempshift ) ;
end
tempshift = grayin << 2 ;
flips[indxWidth] = parity & ~(| tempshift ) ;
incrGray = flips ^ grayin ;
end
endfunction
endmodule // FIFOSync
`ifdef testBluespec
module testSyncFIFO0() ;
parameter fifodepth = 32;
parameter fifoidx = 5;
wire sCLK, dCLK, dRST ;
wire sENQ, dDEQ;
wire sFULL_N, dEMPTY_N ;
reg sRST, sCLR ;
ClockGen#(15,14,10) sc( sCLK );
ClockGen#(11,12,2600) dc( dCLK );
initial
begin
sCLR = 1'b0 ;
sRST = `BSV_RESET_VALUE ;
$display( "running test" ) ;
$dumpfile("SyncFIFO0.vcd");
$dumpvars(5,testSyncFIFO0) ;
$dumpon ;
#200 ;
sRST = !`BSV_RESET_VALUE ;
#100000 $finish ;
end // initial begin
initial
begin
#50000 ;
@(posedge sCLK ) ;
sCLR <= `BSV_ASSIGNMENT_DELAY 1'b1 ;
@(posedge sCLK ) ;
sCLR <= `BSV_ASSIGNMENT_DELAY 1'b0 ;
end
SyncFIFO0 #(fifodepth,fifoidx)
dut( sCLK, sRST, dCLK, sENQ,
sFULL_N, // sCLR,
dDEQ, dEMPTY_N );
assign sENQ = sFULL_N ;
always @(posedge sCLK)
begin
if (sENQ )
begin
$display( "enqueuing" ) ;
end
end // always @ (posedge sCLK)
assign dDEQ = dEMPTY_N ;
always @(posedge dCLK)
begin
if (dDEQ )
begin
$display( "dequeing" ) ;
end
end // always @ (posedge dCLK)
endmodule // testSyncFIFO0
`endif
|
#include <bits/stdc++.h> using namespace std; using namespace std; vector<long long>::iterator ptr; long long count = 0; long long cache[10004]; long long dp[100005] = {0}; long long cnt[200005] = {0}; long long a[200005] = {0}; long long b[200005] = {0}; long long r[200005] = {0}; long long pr(long long n) { if (n % 2 == 0) { return 2; } for (long long i = 3; i <= sqrt(n); i = i + 2) { if (n % i == 0) return i; } if (n > 2) return n; } long long power(long long x, unsigned long long y) { if (y == 0) return 1; else if (y % 2 == 0) return power(x, y / 2) * power(x, y / 2); else return x * power(x, y / 2) * power(x, y / 2); } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long n = 0, p, q = 0, k, x = 0, y, m; cin >> n >> m; char s[1005][1005]; long long v[1005][5] = {0}; for (long long i = 0; i < m; ++i) { for (long long j = 0; j < 5; ++j) { v[i][j] = 0; } } for (long long i = 0; i < n; ++i) { for (long long j = 0; j < m; ++j) { cin >> s[i][j]; if (s[i][j] == A ) v[j][0]++; else if (s[i][j] == B ) v[j][1]++; else if (s[i][j] == C ) v[j][2]++; else if (s[i][j] == D ) v[j][3]++; else if (s[i][j] == E ) v[j][4]++; } } for (long long i = 0; i < m; ++i) { cin >> a[i]; } for (long long i = 0; i < m; ++i) { p = 0; for (long long j = 0; j < 5; ++j) { p = max(p, v[i][j]); } x += (a[i] * p); } cout << x; return 0; } |
#include <bits/stdc++.h> using namespace std; int p[1000005]; int fnd(int x) { return p[x] = p[x] == x ? x : fnd(p[x]); } void unn(int x, int y) { p[fnd(y)] = fnd(x); } int dir[4][2] = {{0, 1}, {1, 0}, {0, -1}, {-1, 0}}; int gcd(int x, int y) { return x % y ? gcd(y, x % y) : y; } int pq[5144]; vector<int> pr; int net[100005]; int a[100005]; int main() { int n; scanf( %d , &n); if (n == 1) return printf( 1 n ), 0; for (int i = 2; i <= 10000; i++) { if (net[i]) continue; pr.push_back(i); for (int j = i * i; j <= 100000; j += i) net[j] = 1; } for (int i = 0; i < n; i++) { scanf( %d , a + i); int mx = 0; for (int j = 0; j < pr.size(); j++) { if (a[i] % pr[j] == 0) { mx = max(mx, pq[j]); } } for (int j = 0; j < pr.size(); j++) { if (a[i] % pr[j] == 0) { pq[j] = max(mx + 1, pq[j]); } } } int mx = 1; for (int i = 0; i < pr.size(); i++) mx = max(mx, pq[i]); printf( %d , mx); } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// verilator lint_off MULTIDRIVEN
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
wire [15:0] out2; // From test of Test.v
// End of automatics
// verilator lint_on MULTIDRIVEN
Test test (
.en (crc[21:20]),
.a1 (crc[19:18]),
.a0 (crc[17:16]),
.d1 (crc[15:8]),
.d0 (crc[7:0]),
/*AUTOINST*/
// Outputs
.out (out[31:0]),
.out2 (out2[15:0]),
// Inputs
.clk (clk));
// Aggregate outputs into a single result vector
wire [63:0] result = {out2, 16'h0, out};
// Test loop
`ifdef TEST_VERBOSE
always @ (negedge clk) begin
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
end
`endif
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
test.clear();
end
else if (cyc<10) begin
sum <= 64'h0;
test.clear();
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hc68a94a34ec970aa
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out, out2,
// Inputs
clk, en, a0, a1, d0, d1
);
input clk;
input [1:0] en;
input [1:0] a0;
input [1:0] a1;
input [7:0] d0;
input [7:0] d1;
output reg [31:0] out;
output reg [15:0] out2;
// verilator lint_off MULTIDRIVEN
reg [7:0] mem [4];
// verilator lint_on MULTIDRIVEN
task clear();
for (int i=0; i<4; ++i) mem[i] = 0;
endtask
always @(posedge clk) begin
if (en[0]) begin
mem[a0] <= d0;
out2[7:0] <= d0;
end
end
always @(negedge clk) begin
if (en[1]) begin
mem[a1] <= d1;
out2[15:8] <= d0;
end
end
assign out = {mem[3],mem[2],mem[1],mem[0]};
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MUX2_BEHAVIORAL_V
`define SKY130_FD_SC_HD__MUX2_BEHAVIORAL_V
/**
* mux2: 2-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_hd__mux2 (
X ,
A0,
A1,
S
);
// Module ports
output X ;
input A0;
input A1;
input S ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire mux_2to10_out_X;
// Name Output Other arguments
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_2to10_out_X, A0, A1, S );
buf buf0 (X , mux_2to10_out_X);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__MUX2_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; long long n, q; long long a[755], mx[755]; signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> n >> q; for (long long i = 1; i <= n; i++) cin >> a[i]; for (long long i = 0; i <= n; i++) { long long l = 0, r = 1000000000000000, ans = 0; while (l <= r) { long long m = (l + r + 1) / 2; long long sum = m, cnt = 0; priority_queue<long long, vector<long long>, greater<long long>> pq; for (long long j = 1; j <= n; j++) { sum += a[j]; pq.push(a[j]); while (sum < 0 && (long long)pq.size()) { sum -= pq.top(); pq.pop(); cnt++; } } if (cnt <= i) { ans = m; r = m - 1; } else l = m + 1; } mx[i] = ans; } while (q--) { long long r; cin >> r; for (long long i = 0; i <= n; i++) if (r >= mx[i]) { cout << i << n ; break; } } } |
`timescale 1ns / 1ps
/* Do NOT allow undeclared nets */
`default_nettype none
/*
Example for June 2014 - Programmable Logic In Practice.
Copyright Colin O'Flynn 2014. All Rights Reserved.
*/
module lx9_reconfig_top(
//Inputs
input wire USER_RESET,
input wire USER_CLOCK,
//PMod Connection: J5, Pin 1
output wire PMOD1_P1,
//Serial Connection (if used)
input wire USB_RS232_RXD,
output wire USB_RS232_TXD,
//LEDs
output wire GPIO_LED1,
output wire GPIO_LED2
);
wire reset;
wire inpclk;
wire oupclk;
assign reset = USER_RESET;
BUFG bufg_inst (
.O(inpclk), // 1-bit output: Clock buffer output
.I(USER_CLOCK) // 1-bit input: Clock buffer input
);
reg [24:0] counterinp;
reg [24:0] counteroup;
assign GPIO_LED1 = counterinp[24];
assign GPIO_LED2 = counteroup[24];
always @(posedge inpclk) begin
counterinp <= counterinp + 25'd1;
end
always @(posedge oupclk) begin
counteroup <= counteroup + 25'd1;
end
//DCM Block we will be reconfiguring with partial reconfiguration
generate_clock gclock_i
(
.CLK_IN1(inpclk),
.CLK_OUT1(oupclk),
.RESET(reset)
);
//Outputing clock on S6 device only requires this
ODDR2 #(
.DDR_ALIGNMENT("NONE"),
.INIT(1'b0),
.SRTYPE("SYNC")
) ODDR2_inst (
.Q (PMOD1_P1), // 1-bit DDR output data
.C0 (oupclk), // 1-bit clock input
.C1 (~oupclk), // 1-bit clock input
.CE (1'b1), // 1-bit clock enable input
.D0 (1'b1),
.D1 (1'b0),
.R (1'b0), // 1-bit reset input
.S (1'b0));
wire sysclk;
assign sysclk = inpclk;
/***** Serial Interface *****/
wire cmdfifo_rxf;
wire cmdfifo_txe;
wire cmdfifo_rd;
wire cmdfifo_wr;
wire cmdfifo_isout;
wire [7:0] cmdfifo_din;
wire [7:0] cmdfifo_dout;
serial_reg_iface cmdfifo_serial(.reset_i(reset),
.clk_i(sysclk),
.rx_i(USB_RS232_RXD),
.tx_o(USB_RS232_TXD),
.cmdfifo_rxf(cmdfifo_rxf),
.cmdfifo_txe(cmdfifo_txe),
.cmdfifo_rd(cmdfifo_rd),
.cmdfifo_wr(cmdfifo_wr),
.cmdfifo_din(cmdfifo_din),
.cmdfifo_dout(cmdfifo_dout));
/***** Register Interface *****/
wire reg_clk;
wire [5:0] reg_address;
wire [15:0] reg_bytecnt;
wire [7:0] reg_datao;
wire [15:0] reg_size;
wire reg_read;
wire reg_write;
wire reg_addrvalid;
wire [5:0] reg_hypaddress;
wire reg_stream;
wire [15:0] reg_hyplen;
wire [7:0] reg_datai_reconfig;
reg_main registers_mainctl (
.reset_i(reset),
.clk(sysclk),
.cmdfifo_rxf(cmdfifo_rxf),
.cmdfifo_txe(cmdfifo_txe),
.cmdfifo_rd(cmdfifo_rd),
.cmdfifo_wr(cmdfifo_wr),
.cmdfifo_din(cmdfifo_din),
.cmdfifo_dout(cmdfifo_dout),
.cmdfifo_isout(cmdfifo_isout),
.reg_clk(reg_clk),
.reg_address(reg_address),
.reg_bytecnt(reg_bytecnt),
.reg_datao(reg_datao),
.reg_datai(reg_datai_reconfig),
.reg_size(reg_size),
.reg_read(reg_read),
.reg_write(reg_write),
.reg_addrvalid(reg_addrvalid),
.reg_stream(reg_stream),
.reg_hypaddress(reg_hypaddress),
.reg_hyplen(reg_hyplen)
);
/***** Reconfiguration Registers *****/
reg_reconfig reconfiguration(
.reset_i(reset),
.clk(reg_clk),
.reg_address(reg_address),
.reg_bytecnt(reg_bytecnt),
.reg_datao(reg_datai_reconfig),
.reg_datai(reg_datao),
.reg_size(reg_size),
.reg_read(reg_read),
.reg_write(reg_write),
.reg_addrvalid(reg_addrvalid),
.reg_stream(reg_stream),
.reg_hypaddress(reg_hypaddress),
.reg_hyplen(reg_hyplen)
);
endmodule
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module decodes video streams from the Terasic CCD cameras. *
* *
******************************************************************************/
module altera_up_video_camera_decoder (
// Inputs
clk,
reset,
PIXEL_DATA,
LINE_VALID,
FRAME_VALID,
ready,
// Bidirectional
// Outputs
data,
startofpacket,
endofpacket,
valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 9;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] PIXEL_DATA;
input LINE_VALID;
input FRAME_VALID;
input ready;
// Bidirectional
// Outputs
output reg [DW: 0] data;
output reg startofpacket;
output reg endofpacket;
output reg valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire read_temps;
// Internal Registers
reg [DW: 0] io_pixel_data;
reg io_line_valid;
reg io_frame_valid;
reg frame_sync;
reg [DW: 0] temp_data;
reg temp_start;
reg temp_end;
reg temp_valid;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Input Registers
always @ (posedge clk)
begin
io_pixel_data <= PIXEL_DATA;
io_line_valid <= LINE_VALID;
io_frame_valid <= FRAME_VALID;
end
// Output Registers
always @ (posedge clk)
begin
if (reset)
begin
data <= 'h0;
startofpacket <= 1'b0;
endofpacket <= 1'b0;
valid <= 1'b0;
end
else if (read_temps)
begin
data <= temp_data;
startofpacket <= temp_start;
endofpacket <= temp_end;
valid <= temp_valid;
end
else if (ready)
valid <= 1'b0;
end
// Internal Registers
always @ (posedge clk)
begin
if (reset)
frame_sync <= 1'b0;
else if (~io_frame_valid)
frame_sync <= 1'b1;
else if (io_line_valid & io_frame_valid)
frame_sync <= 1'b0;
end
always @ (posedge clk)
begin
if (reset)
begin
temp_data <= 'h0;
temp_start <= 1'b0;
temp_end <= 1'b0;
temp_valid <= 1'b0;
end
else if (read_temps)
begin
temp_data <= io_pixel_data;
temp_start <= frame_sync;
temp_end <= ~io_frame_valid;
temp_valid <= io_line_valid & io_frame_valid;
end
else if (~io_frame_valid)
begin
temp_end <= ~io_frame_valid;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
// Internal Assignments
assign read_temps = (ready | ~valid) &
((io_line_valid & io_frame_valid) |
((temp_start | temp_end) & temp_valid));
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
#include <bits/stdc++.h> using namespace std; const int M = 1e9 + 7; const int MN = 1e6 + 6; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cout << fixed << setprecision(10); long long n; cin >> n; long long p_x = 0, p_y = 0; long long res = 1; for (long long i = 0; i < n; ++i) { long long n_x, n_y; cin >> n_x >> n_y; if (p_x == n_x && p_y == n_y) continue; long long a = max(p_x, p_y); long long b = min(n_x, n_y); if (p_x == p_y) { a++; } if (a <= b) res += b - a + 1; p_x = n_x; p_y = n_y; } cout << res << endl; return 0; } |
//////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2013, Andrew "bunnie" Huang
//
// See the NOTICE file distributed with this work for additional
// information regarding copyright ownership. The copyright holder
// licenses this file to you under the Apache License, Version 2.0
// (the "License"); you may not use this file except in compliance
// with the License. You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing,
// code distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
// KIND, either express or implied. See the License for the
// specific language governing permissions and limitations
// under the License.
//////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module nand_log_tb;
reg bclk; // 133 Mhz clock
reg clk100; // 100 Mhz clock
reg nand_re;
reg nand_we;
reg nand_ale;
reg nand_cle;
reg nand_cs;
reg nand_rb;
reg [7:0] nand_din;
reg [9:0] nand_uk;
reg log_reset;
reg log_run;
wire log_cmd_error; // stuck high if cmd fifo overflowed during logging
wire log_data_error; // stuck high if data fifo overflowed during logging
wire [26:0] log_entries; // number of entries currently in the log
wire [3:0] ddr3_wr_mask;
wire [31:0] ddr3_wr_data;
wire ddr3_wr_en;
reg ddr3_wr_full;
reg [6:0] ddr3_wr_count;
wire ddr3_cmd_clk;
wire [2:0] ddr3_cmd_instr;
wire ddr3_cmd_en;
wire [5:0] ddr3_cmd_burstlen;
wire [29:0] ddr3_cmd_addr;
reg ddr3_cmd_full;
wire [63:0] time_t_clk100; // note synched to clk100
reg reset;
nand_log uut(
bclk, // 133 Mhz clock
clk100, // 100 Mhz clock
nand_re,
nand_we,
nand_ale,
nand_cle,
nand_cs,
nand_rb,
nand_din,
nand_uk,
log_reset,
log_run,
log_cmd_error, // stuck high if cmd fifo overflowed during logging
log_data_error, // stuck high if data fifo overflowed during logging
log_entries, // number of entries currently in the log
ddr3_wr_mask,
ddr3_wr_data,
ddr3_wr_en,
ddr3_wr_full,
ddr3_wr_count,
ddr3_cmd_clk,
ddr3_cmd_instr,
ddr3_cmd_en,
ddr3_cmd_burstlen,
ddr3_cmd_addr,
ddr3_cmd_full,
time_t_clk100, // note synched to clk100
reset
);
parameter PERIOD_BCLK = 16'd8; // 125 MHz (close to 133 MHz actual)
always begin
bclk = 1'b0;
#(PERIOD_BCLK/2) bclk = 1'b1;
#(PERIOD_BCLK/2);
end
parameter PERIOD_CLK100 = 16'd10;
always begin
clk100 = 1'b0;
#(PERIOD_CLK100/2) clk100 = 1'b1;
#(PERIOD_CLK100/2);
end
task nand_reset;
begin
nand_we = 1'b1;
nand_re = 1'b1;
nand_ale = 1'b0;
nand_cle = 1'b0;
nand_cs = 1'b1;
nand_din = 8'hZZ;
log_reset = 1'b1;
log_run = 1'b0;
#1000;
log_reset = 1'b0;
log_run = 1'b1;
#1000;
end
endtask // nand_reset
task nand_idle;
begin
nand_we = 1'b1;
nand_re = 1'b1;
nand_ale = 1'b0;
nand_cle = 1'b0;
nand_cs = 1'b1;
nand_din = 8'hZZ;
end
endtask // nand_idle
task nand_read_id;
begin
nand_cs = 1'b0;
nand_cle = 1'b1;
nand_we = 1'b0;
nand_din = 8'h90;
#25;
nand_we = 1'b1;
#5;
nand_cle = 1'b0;
nand_din = 8'h01;
#20;
nand_ale = 1'b1;
#25;
nand_we = 1'b0;
nand_din = 8'h00;
#25;
nand_we = 1'b1;
#5;
nand_din = 8'h23;
#20;
nand_ale = 1'b0;
#10;
nand_re = 1'b0;
nand_din = 8'h45;
#25;
nand_re = 1'b1;
#25;
nand_re = 1'b0;
nand_din = 8'h67;
#25;
nand_re = 1'b1;
#25;
nand_re = 1'b0;
nand_din = 8'h89;
#25;
nand_re = 1'b1;
#25;
nand_re = 1'b0;
nand_din = 8'hAB;
#25;
nand_re = 1'b1;
#25;
nand_re = 1'b0;
nand_din = 8'hCD;
#25;
nand_re = 1'b1;
#25;
nand_cs = 1'b1;
end
endtask; // nand_read_id
initial begin
nand_re = 1;
nand_we = 1;
nand_ale = 0;
nand_cle = 0;
nand_rb = 1;
nand_din = 8'h00;
nand_uk[9:0] = 10'h0;
nand_cs = 1;
log_reset = 1'b0;
log_run = 1'b0;
ddr3_wr_full = 1'b0;
ddr3_wr_count = 7'b0;
ddr3_cmd_full = 1'b0;
reset = 1;
#1000;
reset = 0;
nand_reset();
#1000;
nand_idle();
#200;
nand_read_id();
$stop;
#1000;
$stop;
end
endmodule // nand_log_tb
|
///////////////////////////////////////////////////////////////////////////////
// vim:set shiftwidth=3 softtabstop=3 expandtab:
//
// Module: oq_regs_eval_full.v
// Project: NF2.1
// Description: Evaluates whether a queue is full
//
// Currently looks at the number of packets in the queue and the number of
// words left
//
///////////////////////////////////////////////////////////////////////////////
module oq_regs_eval_full
#(
parameter SRAM_ADDR_WIDTH = 13,
parameter CTRL_WIDTH = 8,
parameter UDP_REG_SRC_WIDTH = 2,
parameter NUM_OUTPUT_QUEUES = 8,
parameter NUM_OQ_WIDTH = log2(NUM_OUTPUT_QUEUES),
parameter PKT_LEN_WIDTH = 11,
parameter PKT_WORDS_WIDTH = PKT_LEN_WIDTH-log2(CTRL_WIDTH),
parameter MAX_PKT = 2048/CTRL_WIDTH, // allow for 2K bytes,
parameter MIN_PKT = 60/CTRL_WIDTH + 1,
parameter PKTS_IN_RAM_WIDTH = log2((2**SRAM_ADDR_WIDTH)/MIN_PKT)
)
(
// --- Inputs from dst update ---
input dst_update,
input [NUM_OQ_WIDTH-1:0] dst_oq,
input [PKTS_IN_RAM_WIDTH-1:0] dst_max_pkts_in_q,
input [PKTS_IN_RAM_WIDTH-1:0] dst_num_pkts_in_q,
input dst_num_pkts_in_q_done,
input [SRAM_ADDR_WIDTH-1:0] dst_oq_full_thresh,
input [SRAM_ADDR_WIDTH-1:0] dst_num_words_left,
input dst_num_words_left_done,
// --- Inputs from src update ---
input src_update,
input [NUM_OQ_WIDTH-1:0] src_oq,
input [PKTS_IN_RAM_WIDTH-1:0] src_max_pkts_in_q,
input [PKTS_IN_RAM_WIDTH-1:0] src_num_pkts_in_q,
input src_num_pkts_in_q_done,
input [SRAM_ADDR_WIDTH-1:0] src_oq_full_thresh,
input [SRAM_ADDR_WIDTH-1:0] src_num_words_left,
input src_num_words_left_done,
// --- Clear the flag ---
input initialize,
input [NUM_OQ_WIDTH-1:0] initialize_oq,
output [NUM_OUTPUT_QUEUES-1:0] full,
// --- Misc
input clk,
input reset
);
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
// ------------- Internal parameters --------------
// ------------- Wires/reg ------------------
reg [NUM_OUTPUT_QUEUES-1:0] full_pkts_in_q;
reg [NUM_OUTPUT_QUEUES-1:0] full_words_left;
wire src_full_pkts_in_q;
reg src_full_pkts_in_q_held;
wire dst_full_pkts_in_q;
wire src_full_words_left;
reg src_full_words_left_held;
wire dst_full_words_left;
reg dst_update_d1;
reg src_update_d1;
reg [PKTS_IN_RAM_WIDTH-1:0] dst_max_pkts_in_q_held;
reg [PKTS_IN_RAM_WIDTH-1:0] src_max_pkts_in_q_held;
reg [PKTS_IN_RAM_WIDTH-1:0] dst_oq_full_thresh_held;
reg [PKTS_IN_RAM_WIDTH-1:0] src_oq_full_thresh_held;
reg [NUM_OQ_WIDTH-1:0] dst_oq_held;
reg [NUM_OQ_WIDTH-1:0] src_oq_held;
reg src_num_pkts_in_q_done_held;
reg src_num_words_left_done_held;
// ------------- Logic ------------------
assign full = full_pkts_in_q | full_words_left;
assign src_full_pkts_in_q = src_num_pkts_in_q >= src_max_pkts_in_q_held &&
src_max_pkts_in_q_held != 0;
assign dst_full_pkts_in_q = dst_num_pkts_in_q >= dst_max_pkts_in_q_held &&
dst_max_pkts_in_q_held != 0;
assign src_full_words_left = src_num_words_left <= src_oq_full_thresh_held ||
src_num_words_left < 2 * MAX_PKT;
assign dst_full_words_left = dst_num_words_left <= dst_oq_full_thresh_held ||
dst_num_words_left < 2 * MAX_PKT;
always @(posedge clk)
begin
dst_update_d1 <= dst_update;
src_update_d1 <= src_update;
if (reset) begin
full_pkts_in_q <= 'h0;
full_words_left <= 'h0;
end
else begin
if (dst_update) begin
dst_oq_held <= dst_oq;
end
if (src_update) begin
src_oq_held <= src_oq;
end
// Latch the maximums the cycle immediately following the update
// notifications. The update notifications are linked to the read
// ports of the appropriate registers so the read value will always
// be returned in the next cycle.
if (dst_update_d1) begin
dst_max_pkts_in_q_held <= dst_max_pkts_in_q;
dst_oq_full_thresh_held <= dst_oq_full_thresh;
end
if (src_update_d1) begin
src_max_pkts_in_q_held <= src_max_pkts_in_q;
src_oq_full_thresh_held <= src_oq_full_thresh;
end
// Update the full status giving preference to stores over removes
// since we don't want to accidentally try adding to a full queue
// Number of packets in queue
if (dst_num_pkts_in_q_done) begin
full_pkts_in_q[dst_oq_held] <= dst_full_pkts_in_q;
src_num_pkts_in_q_done_held <= src_num_pkts_in_q_done;
src_full_pkts_in_q_held <= src_full_pkts_in_q;
end
else if (src_num_pkts_in_q_done) begin
full_pkts_in_q[src_oq_held] <= src_full_pkts_in_q;
end
else if (src_num_pkts_in_q_done_held) begin
full_pkts_in_q[src_oq_held] <= src_full_pkts_in_q_held;
end
else if (initialize) begin
full_pkts_in_q[initialize_oq] <= 1'b0;
end
// Number of words left:
if (dst_num_words_left_done) begin
full_words_left[dst_oq_held] <= dst_full_words_left;
src_num_words_left_done_held <= src_num_words_left_done;
src_full_words_left_held <= src_full_words_left;
end
else if (src_num_words_left_done) begin
full_words_left[src_oq_held] <= src_full_words_left;
end
else if (src_num_words_left_done_held) begin
full_words_left[src_oq_held] <= src_full_words_left_held;
end
else if (initialize) begin
full_words_left[initialize_oq] <= 1'b0;
end
end
end
endmodule // oq_regs_eval_full
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5, mod = 1000000007, INF = 1e9 + 7; const int block = 316; int n, k, type[N], a[N], m, cnt[N * 3], l[N][5]; long long ans, res[N], p[N][5]; set<long long> s; map<long long, int> conv; struct query { int l, r, id, num; query(){}; query(int a, int b, int c) : l(a), r(b), id(a / block), num(c){}; } q[N]; bool cmp(query q1, query q2) { if (q1.id != q2.id) return q1.id < q2.id; return q1.r < q2.r; } void add(int v, int cond) { ans += cnt[l[v][cond]]; cnt[l[v][1]]++; } void remove(int v, int cond) { cnt[l[v][1]]--; ans -= cnt[l[v][cond]]; } int main() { cin >> n >> k; for (int i = 1; i <= n; i++) { cin >> type[i]; } for (int i = 1; i <= n; i++) { cin >> a[i]; } for (int i = 0; i <= n; i++) { if (type[i] == 2) a[i] *= -1; p[i][1] = p[i - 1][1] + a[i]; p[i][2] = p[i][1] - k; p[i][3] = p[i][1] + k; s.insert(p[i][1]); s.insert(p[i][2]); s.insert(p[i][3]); } int cnt = 0; for (long long e : s) { conv[e] = ++cnt; } for (int i = 0; i <= n; i++) { l[i][1] = conv[p[i][1]]; l[i][2] = conv[p[i][2]]; l[i][3] = conv[p[i][3]]; } cin >> m; for (int i = 1; i <= m; i++) { int l, r; cin >> l >> r; l--; q[i] = query(l, r, i); } sort(q + 1, q + m + 1, &cmp); int l = 0, r = -1; for (int i = 1; i <= m; i++) { int L = q[i].l, R = q[i].r; while (r < R) add(++r, 2); while (l < L) remove(l++, 3); while (R < r) remove(r--, 2); while (L < l) add(--l, 3); res[q[i].num] = ans; } for (int i = 1; i <= m; i++) { cout << res[i] << endl; } cout << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; vector<int> a(n + 1); for (int i = 1; i <= n; i++) cin >> a[i]; vector<vector<int> > dp(201); for (int i = 1; i <= n; i++) { dp[a[i]].push_back(i); } int maximum = 0; for (int i = 1; i <= n; i++) { int p = a[i]; int l = lower_bound(dp[p].begin(), dp[p].end(), i) - begin(dp[p]); int r = dp[p].size() - l - 1; if (l >= r) continue; int lval = dp[p][l]; int rval = dp[p][r]; int maxi = 0; for (int j = 1; j <= 200; j++) { if (j == p) { maxi = max(maxi, r - l - 1); continue; } int xx = upper_bound(dp[j].begin(), dp[j].end(), rval) - dp[j].begin(); int yy = upper_bound(dp[j].begin(), dp[j].end(), lval) - dp[j].begin(); maxi = max(maxi, xx - yy); } maximum = max(maximum, maxi + (2 * (l + 1))); } cout << max(1, maximum) << endl; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND2B_2_V
`define SKY130_FD_SC_HD__AND2B_2_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog wrapper for and2b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__and2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and2b_2 (
X ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and2b base (
.X(X),
.A_N(A_N),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and2b_2 (
X ,
A_N,
B
);
output X ;
input A_N;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and2b base (
.X(X),
.A_N(A_N),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND2B_2_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, t, timer = 0; scanf( %d%d%d , &n, &m, &t); deque<int> q; vector<int> col(n); char isOk = false; for (int i = 0, j = 0; i < n; i++) { int x, y, z, start; scanf( n%d:%d:%d , &x, &y, &z); start = x * 3600 + y * 60 + z; while (!q.empty() && q.front() <= start) { j--; q.pop_front(); } if (j < m) { j++; q.push_back(start + t); timer++; } else { q.back() = start + t; } if (j == m) { isOk = true; } col[i] = timer; } if (!isOk) { printf( No solution ); return 0; } printf( %d n , timer); for (int i : col) { printf( %d n , i); } return 0; } |
// ***********************************************************
// $Header: /var/lib/cvs/dncvs/FPGA/dini/fifo/fifo_checksum.v,v 1.8 2014/08/28 22:04:32 neal Exp $
// ***********************************************************
// Description:
//
// Calculates checksums on FIFO wr/rd data.
// ***********************************************************
// $Log: fifo_checksum.v,v $
// Revision 1.8 2014/08/28 22:04:32 neal
// Fixed bus indexes.
//
// Revision 1.7 2014/07/21 18:21:18 neal
// Shrank the checksum logic.
//
// Revision 1.6 2014/07/18 16:59:56 neal
// Added an option to control the checksum delay from write to read.
// Added an optional selram fifo for the clock domain change.
//
// Revision 1.5 2014/07/10 18:20:05 neal
// Increased the size of the shift, to account for different clock rates.
//
// Revision 1.4 2014/07/08 15:20:02 neal
// Added optional output register with REGCE to rams.
// Added option to use RAM's output register.
// Added checksums to all async fifos (enabled by define).
//
// Revision 1.3 2014/07/02 12:54:39 neal
// Disabled some of the extra checksum checks (to make it smaller).
//
// Revision 1.2 2014/07/01 23:03:50 neal
// Fixed an unregistered reset that changes clock domains.
//
// Revision 1.1 2014/07/01 19:18:46 neal
// Added checksums to wr_din and rd_dout with a sticky error bit that can be read back.
//
// ***********************************************************
`ifdef INCL_FIFO_CHECKSUM_V
`else
`define INCL_FIFO_CHECKSUM_V
`ifndef DEBUG_KEEP
`define DEBUG_KEEP (* dont_touch="TRUE", keep="TRUE" *)
`endif // DEBUG_KEEP
(* keep_hierarchy = "yes" *) module fifo_checksum #(
parameter DATA_W = 1,
parameter ONECLOCK = 1,
parameter EXTERNALLY_OUTPUT_REGISTERED = 0,
parameter ERROR_SHIFT_BITS = 4
) (
input wr_reset,
input rd_reset,
input wr_clk,
input wr_en,
input wr_full,
input [DATA_W-1:0] wr_data,
input rd_clk,
input rd_en,
input rd_empty,
input [DATA_W-1:0] rd_data,
`DEBUG_KEEP output reg checksum_error
);
// ******************************************
// Generate running checksum on wr_data.
// Only pay attention to the first 8-bits of the data for the checksum.
// ******************************************
localparam CHECKSUM_W = (DATA_W<16) ? (DATA_W+1)/2 : 4;
reg [CHECKSUM_W-1:0] wr_checksum;
always @(posedge wr_clk) begin
if ((wr_en==1'b1) && (wr_full==1'b0)) begin
wr_checksum <= wr_checksum ^ wr_data ^ (wr_data >> CHECKSUM_W);
end
if (wr_reset ) begin
wr_checksum <= 'b0;
end
end
// ******************************************
// Generate running checksum on rd_data.
// ******************************************
reg [CHECKSUM_W-1:0] rd_checksum;
always @(posedge rd_clk) begin
if ((rd_en==1'b1) && (rd_empty==1'b0)) begin
rd_checksum <= rd_checksum ^ rd_data ^ (rd_data >> CHECKSUM_W);
end
if (rd_reset) begin
rd_checksum <= 'b0;
end
end
// ******************************************
// Compare wr_checksum to rd_checksum when the FIFO is really empty.
// ******************************************
reg error_shift;
reg [ERROR_SHIFT_BITS-1:0] error_counter;
always @(posedge rd_clk) begin
if (
`ifdef USE_SYNC_FIFO_CHECKSUM
`else
ONECLOCK |
`endif
EXTERNALLY_OUTPUT_REGISTERED) begin
// do nothing (i.e. don't create the FFs)
end else begin
error_shift <= 1'b0;
if (rd_empty==1'b1) begin
if (rd_checksum != wr_checksum) begin
error_shift <= 1'b1;
end
end
if (error_shift==1'b1)
error_counter <= error_counter+1'b1;
else
error_counter <= 1'b0;
if (&error_counter) begin
$display("ERROR: %m fifo checksums don't match: %x != %x\n",wr_checksum, rd_checksum);
$stop;
checksum_error <= 1'b1;
end
if (rd_reset) begin
checksum_error <= 1'b0;
error_shift <= 'b0;
error_counter <= 'b0;
end
end
end
endmodule // fifo_checksum
`endif // INCL_FIFO_CHECKSUM_V
|
#include <bits/stdc++.h> using namespace std; int h1, h2, n; int v[111]; char c[111]; int a[111]; int b[111]; const double eps = 1e-9; int main() { cin >> h1 >> h2 >> n; for (int i = (0); i < (n); i++) cin >> v[i] >> c[i] >> a[i] >> b[i]; int best = 0; for (int i = -200; i <= 200; i++) { bool good = 1; int sum = 0; set<int> used; int x1 = 0; int y1 = h1; int x2 = 100000; int y2 = h2 + i * 100; if (i % 2) y2 = 100 - h2 + i * 100; if (i > 0) { for (int j = (0); j < (i); j++) { int y = 100 + 100 * j; double x = double(x2 - x1) / (y2 - y1) * (y - y1); bool found = 0; for (int k = (0); k < (n); k++) if (a[k] <= x + eps && b[k] >= x - eps) { if (j % 2 == 0 && c[k] == T || j % 2 == 1 && c[k] == F ) { if (used.count(k)) good = 0; used.insert(k); sum += v[k]; found = 1; break; } } if (!found) good = 0; } } else if (i < 0) { for (int j = (0); j < (-i); j++) { int y = -100 * j; double x = double(x2 - x1) / double(y2 - y1) * (y - y1); bool found = 0; for (int k = (0); k < (n); k++) if (a[k] <= x + eps && b[k] >= x - eps) { if (j % 2 == 0 && c[k] == F || j % 2 == 1 && c[k] == T ) { if (used.count(k)) good = 0; used.insert(k); sum += v[k]; found = 1; break; } } if (!found) good = 0; } } if (good) best = max(best, sum); } cout << best << endl; return 0; } |
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.4 (lin64) Build Tue Nov 18 16:47:07 MST 2014
// Date : Fri May 6 14:51:06 2016
// Host : graviton running 64-bit Debian GNU/Linux 7.10 (wheezy)
// Command : write_verilog -force -mode synth_stub /home/guest/cae/fpga/ntpserver/ip/ocxo_clk_pll/ocxo_clk_pll_stub.v
// Design : ocxo_clk_pll
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module ocxo_clk_pll(clk_in1, clk_out1, resetn, locked)
/* synthesis syn_black_box black_box_pad_pin="clk_in1,clk_out1,resetn,locked" */;
input clk_in1;
output clk_out1;
input resetn;
output locked;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLCLKP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__DLCLKP_BEHAVIORAL_PP_V
/**
* dlclkp: Clock gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_lp__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dlclkp (
GCLK,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output GCLK;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire m0 ;
wire clkn ;
wire CLK_delayed ;
wire GATE_delayed;
reg notifier ;
// Name Output Other arguments
not not0 (clkn , CLK_delayed );
sky130_fd_sc_lp__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);
and and0 (GCLK , m0, CLK_delayed );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLCLKP_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; int n, k; long long f[1005][2005][4]; int main() { f[1][1][0] = f[1][1][1] = f[1][2][2] = f[1][2][3] = 1; cin >> n >> k; for (int i = 1; i <= n; i++) f[i][1][0] = f[i][1][1] = 1; for (int i = 2; i <= n; i++) { for (int j = 2; j <= k; j++) { f[i][j][0] = (f[i - 1][j][0] + f[i - 1][j - 1][1] + f[i - 1][j][2] + f[i - 1][j][3]) % 998244353; f[i][j][1] = (f[i - 1][j - 1][0] + f[i - 1][j][1] + f[i - 1][j][2] + f[i - 1][j][3]) % 998244353; f[i][j][2] = (f[i - 1][j - 1][0] + f[i - 1][j - 1][1] + f[i - 1][j][2] + f[i - 1][j - 2][3]) % 998244353; f[i][j][3] = (f[i - 1][j - 1][0] + f[i - 1][j - 1][1] + f[i - 1][j - 2][2] + f[i - 1][j][3]) % 998244353; } } long long ans = 0; for (int i = 0; i <= 3; i++) ans = (ans + f[n][k][i]) % 998244353; cout << ans; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND4_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__AND4_FUNCTIONAL_PP_V
/**
* and4: 4-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__and4 (
VPWR,
VGND,
X ,
A ,
B ,
C ,
D
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
input B ;
input C ;
input D ;
// Local signals
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out_X , A, B, C, D );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND4_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; const double EPS = 1e-9; const int oo = (int)1e9; const double PI = 2 * acos(0.0); const double eps = 1e-7; const int MAXN = 1e5 + 10; int dx[] = {1, 0, -1, 0, -1, -1, 1, 1}; int dy[] = {0, 1, 0, -1, 1, -1, 1, -1}; int main() { int n, k, a[100009]; cin >> n >> k; for (int i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); set<long long> s; for (int i = n - 1; i >= 0; i--) if (s.find((long long)k * a[i]) == s.end()) s.insert(a[i]); cout << ((int)((s).size())) << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { int na, ma, nb, mb; cin >> na >> ma; char ch1[na + 5][ma + 5]; for (int i = 1; i <= na; i++) { for (int j = 1; j <= ma; j++) { cin >> ch1[i][j]; } } cin >> nb >> mb; char ch2[nb + 5][mb + 5]; for (int i = 1; i <= nb; i++) { for (int j = 1; j <= mb; j++) { cin >> ch2[i][j]; } } int x = -1, y = -1, mx = -1; for (int xx = -50; xx <= 50; xx++) { for (int yy = -50; yy <= 50; yy++) { int sum = 0; for (int i = 1; i <= na; i++) { for (int j = 1; j <= ma; j++) { if (((i + xx) >= 1 && (i + xx) <= nb) && ((j + yy) >= 1 && (j + yy) <= mb)) { sum += (ch1[i][j] - 0 ) * (ch2[i + xx][j + yy] - 0 ); } } } if (sum > mx) { mx = sum; x = xx; y = yy; } } } cout << x << << y << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; vector<int> a(n + 1); for (int i = 1; i <= n; ++i) { cin >> a[i]; } sort(a.begin(), a.end()); vector<vector<vector<int>>> dp( 2, vector<vector<int>>(k + 1, vector<int>(k + 1))); dp[0][0][0] = 1; int ans = 0; set<int> sad; for (int i = 1; i <= n; ++i) { for (int j = 0; j <= k; ++j) { for (int l = 0; l <= j; ++l) { int i2 = i % 2; dp[i2][j][l] = dp[abs(i2 - 1)][j][l]; if (a[i] <= j) { dp[i2][j][l] = max(dp[abs(i2 - 1)][j][l], dp[abs(i2 - 1)][j - a[i]][l]); if (a[i] <= l) { dp[i2][j][l] = max(dp[i2][j][l], dp[abs(i2 - 1)][j - a[i]][l - a[i]]); } } if (i == n && j == k && dp[i2][j][l] != 0) { ++ans; sad.insert(l); } } } } cout << ans << endl; for (auto i : sad) { cout << i << ; } } |
/*
* .--------------. .----------------. .------------.
* | .------------. | .--------------. | .----------. |
* | | ____ ____ | | | ____ ____ | | | ______ | |
* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
* | | | | | | | | | | | |
* |_| | '------------' | '--------------' | '----------' |
* '--------------' '----------------' '------------'
*
* openHMC - An Open Source Hybrid Memory Cube Controller
* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
* www.ziti.uni-heidelberg.de
* B6, 26
* 68159 Mannheim
* Germany
*
* Contact:
* http://ra.ziti.uni-heidelberg.de/openhmc
*
* This source file is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This source file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this source file. If not, see <http://www.gnu.org/licenses/>.
*
*
* Module name: rx_descrambler
*
* Scrambler Logic (HMC Spec version 1.0)
* This module implements a parallel scrambler based on the
* polynomial 1+ x^(-14) + x^(-15).
*
* Such Scrambler is typically shown as a 15 bit Linear Feedback Shift Register
* (LFSR) with bits shifting from register 1 on the left to register 15 on the
* right, with register 14 and 15 combining to shift into register 1.
* The HMC Serializer outputs data[0] first from parallel tx data[n:0],
* so if data[n:0] is to be bitwise scrambled with LFSR[n:0], we need the LFSR
* to shift from n -> 0, the opposite direction from the typical illustration.
* This implementation shifts data from LFSR[14] on the left to LFSR[0] on the
* right, with LFSR[1] and [0] combining to shift into LFSR[14]. This way
* LFSR[14:0] can bitwise scramble data[14:0] and be compatible with serializ-
* ation that shifts out on the data[0] side.
* Put otherwise: Polynomial 1+ x^(-14) + x^(-15) is equiv to
* x^15 + x^1 + x^0
*
* This parallelized version calculates the next DWIDTH steps of values for
* the LFSR. These bits are used to scramble the parallel input, and to
* choose the next value of lfsr (lfsr_steps[DWIDTH-1]).
*
* This is the descrambler. It is self-seeding. When lock is asserted it has
* successfully found the correct value for the LFSR. It is only implemented
* for DWIDTH > 14.
*
* Since we know that scrambled zeros are being translated, we can calculate
* what the seed will be in the next timestep. In order to simplify the
* calculation, we assume that the top bit is a one. That has the happy side-
* effect of letting us know that the seed didn't get stuck at all zeros.
*
* After the scrambler is locked, the input word may need to be aligned. The
* bit_slip input allows the scrambler to shift one bit with the serializer
* to keep the scrambler in sync.
*/
`default_nettype none
module rx_descrambler #(
parameter DWIDTH=16,
parameter BITSLIP_SHIFT_RIGHT=1
)
(
input wire clk,
input wire res_n,
input wire bit_slip,
output reg locked,
input wire [DWIDTH-1:0] data_in,
output reg [DWIDTH-1:0] data_out
);
reg [14:0] lfsr; // LINEAR FEEDBACK SHIFT REGISTER
wire [14:0] lfsr_slipped; // Temporary lfsr for bitslip
wire [14:0] lfsr_steps [DWIDTH-1:0]; // LFSR values for serial time steps
wire [14:0] calculated_seed;
wire [DWIDTH-1:0] data_out_tmp;
generate
if(BITSLIP_SHIFT_RIGHT==1) begin
assign lfsr_slipped = { (lfsr_steps[DWIDTH-1][1] ^ lfsr_steps[DWIDTH-1][0]) , lfsr_steps[DWIDTH-1][14:1] };
end else begin
assign lfsr_slipped = { lfsr_steps[DWIDTH-1][13:0], (lfsr_steps[DWIDTH-1][14] ^ lfsr_steps[DWIDTH-1][0])};
end
endgenerate
// SEQUENTIAL PROCESS
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
if (!res_n) begin
locked <= 1'b0;
lfsr <= 15'h0;
data_out <= {DWIDTH {1'b0}};
end else begin
data_out <= data_out_tmp;
if (!locked && |data_in) begin
lfsr <= calculated_seed;
// Locked when the calculated seeds match
if (calculated_seed == lfsr_steps[DWIDTH-1]) begin
locked <= 1'b1;
end
end else begin
if (bit_slip) begin
lfsr <= lfsr_slipped;
end else begin
lfsr <= lfsr_steps[DWIDTH-1];
end
end
end
end // serial shift right with left input
// SCRAMBLE
genvar j;
generate
localparam OFFSET = DWIDTH-15; // It breaks here if DWIDTH < 15
assign calculated_seed[14] = 1'b1; // Guess the top bit is 1
// data_in is the past state of the LFSR, so we can figure out
// the current value using a loop.
for(j = 0; j < 14; j = j + 1) begin : seed_calc
assign calculated_seed[j] = data_in[j+OFFSET] ^ data_in[j+OFFSET+1];
end
assign data_out_tmp [0] = data_in[0] ^ lfsr[0]; // single bit scrambled
assign lfsr_steps[0] = { (lfsr[1] ^ lfsr[0]) , lfsr[14:1] }; // lfsr at next bit clock
for(j = 1; j < DWIDTH; j = j + 1) begin : scrambler_gen
assign data_out_tmp[j] = data_in[j] ^ lfsr_steps[j-1][0];
assign lfsr_steps[j] = { (lfsr_steps[j-1][1] ^ lfsr_steps[j-1][0]) , lfsr_steps[j-1][14:1] };
end
endgenerate
endmodule
`default_nettype wire
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND3B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__NAND3B_FUNCTIONAL_PP_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__nand3b (
Y ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y , B, not0_out, C );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND3B_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; signed main() { long long T; cin >> T; while (T--) { string s; cin >> s; long long ans = (long long)s.size(), curr = 0; for (long long i = 0; i < s.size(); i++) { if (s[i] == + ) { curr++; } else { curr--; } if (curr < 0) { ans += (i + 1); curr++; } } cout << ans << endl; } } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Sun May 28 19:58:38 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_clk_wiz_0_0 -prefix
// system_clk_wiz_0_0_ system_clk_wiz_0_0_sim_netlist.v
// Design : system_clk_wiz_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* NotValidForBitStream *)
module system_clk_wiz_0_0
(clk_out1,
locked,
clk_in1);
output clk_out1;
output locked;
input clk_in1;
(* IBUF_LOW_PWR *) wire clk_in1;
wire clk_out1;
wire locked;
system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz inst
(.clk_in1(clk_in1),
.clk_out1(clk_out1),
.locked(locked));
endmodule
module system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz
(clk_out1,
locked,
clk_in1);
output clk_out1;
output locked;
input clk_in1;
wire clk_in1;
wire clk_in1_system_clk_wiz_0_0;
wire clk_out1;
wire clk_out1_system_clk_wiz_0_0;
wire clkfbout_buf_system_clk_wiz_0_0;
wire clkfbout_system_clk_wiz_0_0;
wire locked;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_system_clk_wiz_0_0),
.O(clkfbout_buf_system_clk_wiz_0_0));
(* BOX_TYPE = "PRIMITIVE" *)
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_ibufg
(.I(clk_in1),
.O(clk_in1_system_clk_wiz_0_0));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_out1_system_clk_wiz_0_0),
.O(clk_out1));
(* BOX_TYPE = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(44.625000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(75.000000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(5),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.010000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_buf_system_clk_wiz_0_0),
.CLKFBOUT(clkfbout_system_clk_wiz_0_0),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(clk_in1_system_clk_wiz_0_0),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(clk_out1_system_clk_wiz_0_0),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(locked),
.PSCLK(1'b0),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; int n, a[3001], b[3001], cnt = 1, sum; int main() { cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; sort(a + 1, a + n + 1); while (1) { if (cnt == a[++sum]) cnt++; else { cout << cnt; return 0; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int a[110]; int main() { int n, k; cin >> n >> k; vector<int> v; for (int i = 0; i < k; i++) cin >> a[i]; for (int i = 1; i <= n; i++) v.push_back(i); int lea = 0; for (int i = 0; i < k && v.size() > 0; i++) { lea %= v.size(); int next = (lea + a[i]) % v.size(); cout << v[next] << ; v.erase(v.begin() + next); lea = next; } cout << endl; return 0; } |
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Instruction TLB ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Instantiation of ITLB. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_immu_tlb.v,v $
// Revision 1.1 2006-12-21 16:46:58 vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.9 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.8 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.6.4.1 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.6 2002/10/28 16:34:32 mohor
// RAMs wrong connected to the BIST scan chain.
//
// Revision 1.5 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.4 2002/08/14 06:23:50 lampret
// Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run.
//
// Revision 1.3 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.2 2002/01/28 01:16:00 lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
//
// Insn TLB
//
module or1200_immu_tlb(
// Rst and clk
clk, rst,
// I/F for translation
tlb_en, vaddr, hit, ppn, uxe, sxe, ci,
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// SPR access
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
//
// I/F for translation
//
input tlb_en;
input [aw-1:0] vaddr;
output hit;
output [31:`OR1200_IMMU_PS] ppn;
output uxe;
output sxe;
output ci;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// SPR access
//
input spr_cs;
input spr_write;
input [31:0] spr_addr;
input [31:0] spr_dat_i;
output [31:0] spr_dat_o;
//
// Internal wires and regs
//
wire [`OR1200_ITLB_TAG] vpn;
wire v;
wire [`OR1200_ITLB_INDXW-1:0] tlb_index;
wire tlb_mr_en;
wire tlb_mr_we;
wire [`OR1200_ITLBMRW-1:0] tlb_mr_ram_in;
wire [`OR1200_ITLBMRW-1:0] tlb_mr_ram_out;
wire tlb_tr_en;
wire tlb_tr_we;
wire [`OR1200_ITLBTRW-1:0] tlb_tr_ram_in;
wire [`OR1200_ITLBTRW-1:0] tlb_tr_ram_out;
// BIST
`ifdef OR1200_BIST
wire itlb_mr_ram_si;
wire itlb_mr_ram_so;
wire itlb_tr_ram_si;
wire itlb_tr_ram_so;
`endif
//
// Implemented bits inside match and translate registers
//
// itlbwYmrX: vpn 31-19 v 0
// itlbwYtrX: ppn 31-13 uxe 7 sxe 6
//
// itlb memory width:
// 19 bits for ppn
// 13 bits for vpn
// 1 bit for valid
// 2 bits for protection
// 1 bit for cache inhibit
//
// Enable for Match registers
//
assign tlb_mr_en = tlb_en | (spr_cs & !spr_addr[`OR1200_ITLB_TM_ADDR]);
//
// Write enable for Match registers
//
assign tlb_mr_we = spr_cs & spr_write & !spr_addr[`OR1200_ITLB_TM_ADDR];
//
// Enable for Translate registers
//
assign tlb_tr_en = tlb_en | (spr_cs & spr_addr[`OR1200_ITLB_TM_ADDR]);
//
// Write enable for Translate registers
//
assign tlb_tr_we = spr_cs & spr_write & spr_addr[`OR1200_ITLB_TM_ADDR];
//
// Output to SPRS unit
//
assign spr_dat_o = (!spr_write & !spr_addr[`OR1200_ITLB_TM_ADDR]) ?
{vpn, tlb_index & {`OR1200_ITLB_INDXW{v}}, {`OR1200_ITLB_TAGW-7{1'b0}}, 1'b0, 5'b00000, v} :
(!spr_write & spr_addr[`OR1200_ITLB_TM_ADDR]) ?
{ppn, {`OR1200_IMMU_PS-8{1'b0}}, uxe, sxe, {4{1'b0}}, ci, 1'b0} :
32'h00000000;
//
// Assign outputs from Match registers
//
assign {vpn, v} = tlb_mr_ram_out;
//
// Assign to Match registers inputs
//
assign tlb_mr_ram_in = {spr_dat_i[`OR1200_ITLB_TAG], spr_dat_i[`OR1200_ITLBMR_V_BITS]};
//
// Assign outputs from Translate registers
//
assign {ppn, uxe, sxe, ci} = tlb_tr_ram_out;
//
// Assign to Translate registers inputs
//
assign tlb_tr_ram_in = {spr_dat_i[31:`OR1200_IMMU_PS],
spr_dat_i[`OR1200_ITLBTR_UXE_BITS],
spr_dat_i[`OR1200_ITLBTR_SXE_BITS],
spr_dat_i[`OR1200_ITLBTR_CI_BITS]};
//
// Generate hit
//
assign hit = (vpn == vaddr[`OR1200_ITLB_TAG]) & v;
//
// TLB index is normally vaddr[18:13]. If it is SPR access then index is
// spr_addr[5:0].
//
assign tlb_index = spr_cs ? spr_addr[`OR1200_ITLB_INDXW-1:0] : vaddr[`OR1200_ITLB_INDX];
`ifdef OR1200_BIST
assign itlb_mr_ram_si = mbist_si_i;
assign itlb_tr_ram_si = itlb_mr_ram_so;
assign mbist_so_o = itlb_tr_ram_so;
`endif
//
// Instantiation of ITLB Match Registers
//
or1200_spram_64x14 itlb_mr_ram(
.clk(clk),
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(itlb_mr_ram_si),
.mbist_so_o(itlb_mr_ram_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.ce(tlb_mr_en),
.we(tlb_mr_we),
.oe(1'b1),
.addr(tlb_index),
.di(tlb_mr_ram_in),
.doq(tlb_mr_ram_out)
);
//
// Instantiation of ITLB Translate Registers
//
or1200_spram_64x22 itlb_tr_ram(
.clk(clk),
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(itlb_tr_ram_si),
.mbist_so_o(itlb_tr_ram_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.ce(tlb_tr_en),
.we(tlb_tr_we),
.oe(1'b1),
.addr(tlb_index),
.di(tlb_tr_ram_in),
.doq(tlb_tr_ram_out)
);
endmodule
|
#include <bits/stdc++.h> int n, i, j, l, h, k[5500], f[5500], t[5500]; int main() { scanf( %d n , &n); for (i = 1; i <= n; i++) { scanf( %d , &h); k[i] = k[i - 1] + h; j = i - 1; while (t[j] > k[i] - k[j]) j--; f[i] = f[j] + i - 1 - j; t[i] = k[i] - k[j]; } printf( %d , f[n]); return (0); } |
#include <bits/stdc++.h> void err() { std::cout << std::endl; } template <typename T, typename... Args> void err(T a, Args... args) { std::cout << a << ; err(args...); } using namespace std; const int mod = 998244353; const int inf = 1 << 30; const int maxn = 200000 + 5; const int maxq = 3000 + 5; long long qpow(long long x, long long n) { long long r = 1; while (n > 0) { if (n & 1) r = r * x % mod; n >>= 1; x = x * x % mod; } return r; } long long inv(int x) { return qpow(x, mod - 2); } void add(long long& x, long long y) { x += y; if (x >= mod) x -= mod; } int n, m, a[maxn], w[maxn]; long long f[maxq][maxq]; int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) scanf( %d , a + i); int sa = 0, sb = 0; for (int i = 1; i <= n; i++) { scanf( %d , w + i); if (a[i]) sa += w[i]; else sb += w[i]; } f[0][0] = 1; for (int i = 0; i < m; i++) { for (int j = 0; j <= i; j++) { int a = sa + j, b = sb - (i - j); long long fm = inv(a + b); add(f[i + 1][j + 1], f[i][j] * a % mod * fm % mod); add(f[i + 1][j], f[i][j] * b % mod * fm % mod); } } long long ea = 0, eb = 0; for (int i = 0; i <= m; i++) { ; add(ea, f[m][i] * (sa + i) % mod); add(eb, f[m][i] * (sb - (m - i)) % mod); }; long long iva = inv(sa), ivb = inv(sb); for (int i = 1; i <= n; i++) { if (a[i]) { printf( %lld n , 1ll * w[i] * iva % mod * ea % mod); } else { printf( %lld n , 1ll * w[i] * ivb % mod * eb % mod); } } return 0; } |
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Source-synchronous receiver
// Assumes both clocks are at the same rate
// Relative clock phase is
// unknown
// variable
// bounded
// The output will come several cycles later than the input
// This should synthesize efficiently in Xilinx distributed ram cells,
// which is why we use a buffer depth of 16
// FIXME Async reset on rxclk side?
module ss_rcvr
#(parameter WIDTH=16)
(input rxclk,
input sysclk,
input rst,
input [WIDTH-1:0] data_in,
output [WIDTH-1:0] data_out,
output reg clock_present);
wire [3:0] rd_addr, wr_addr;
// Distributed RAM
reg [WIDTH-1:0] buffer [0:15];
always @(posedge rxclk)
buffer[wr_addr] <= data_in;
assign data_out = buffer[rd_addr];
// Write address generation
reg [3:0] wr_counter;
always @(posedge rxclk or posedge rst)
if (rst)
wr_counter <= 0;
else
wr_counter <= wr_counter + 1;
assign wr_addr = {wr_counter[3], ^wr_counter[3:2], ^wr_counter[2:1], ^wr_counter[1:0]};
// Read Address generation
wire [3:0] wr_ctr_sys, diff, abs_diff;
reg [3:0] wr_addr_sys_d1, wr_addr_sys_d2;
reg [3:0] rd_counter;
assign rd_addr = {rd_counter[3], ^rd_counter[3:2], ^rd_counter[2:1], ^rd_counter[1:0]};
always @(posedge sysclk)
wr_addr_sys_d1 <= wr_addr;
always @(posedge sysclk)
wr_addr_sys_d2 <= wr_addr_sys_d1;
assign wr_ctr_sys = {wr_addr_sys_d2[3],^wr_addr_sys_d2[3:2],^wr_addr_sys_d2[3:1],^wr_addr_sys_d2[3:0]};
assign diff = wr_ctr_sys - rd_counter;
assign abs_diff = diff[3] ? (~diff+1) : diff;
always @(posedge sysclk)
if(rst)
begin
clock_present <= 0;
rd_counter <= 0;
end
else
if(~clock_present)
if(abs_diff > 5)
clock_present <= 1;
else
;
else
if(abs_diff<3)
clock_present <= 0;
else
rd_counter <= rd_counter + 1;
endmodule // ss_rcvr
|
#include <bits/stdc++.h> using namespace std; long long a, b, c, d, e, f[200009], i, j, zx, xc, s, lf[200009], rg[200009], tim, up[200009]; vector<long long> v[200009], shv[200009]; pair<long long, long long> dp[200009]; bool bo[200009], ka[200009]; bool anc(long long q, long long w) { if (lf[q] <= lf[w] && rg[q] >= rg[w]) return 1; else return 0; } void dfs(long long q, long long w) { bo[q] = 1; tim++; lf[q] = rg[q] = tim; for (vector<long long>::iterator it = v[q].begin(); it != v[q].end(); it++) { if (bo[(*it)] == 1 && (*it) != w) { ka[q] = 1; } if (bo[(*it)] == 1) continue; shv[q].push_back((*it)); dfs((*it), q); if (rg[q] < rg[(*it)]) rg[q] = rg[(*it)]; if (ka[(*it)] == 1) ka[q] = 1; } } void dfs2(long long q, long long w) { up[q] = q; for (vector<long long>::iterator it = v[q].begin(); it != v[q].end(); it++) { if ((*it) == w) continue; if (anc((*it), up[q]) == 1) up[q] = (*it); } for (vector<long long>::iterator it = shv[q].begin(); it != shv[q].end(); it++) { dfs2((*it), w); if (anc(up[(*it)], up[q]) == 1) up[q] = up[(*it)]; } } void dfs3(long long q, long long w) { dp[q].first = 0; dp[q].second = 0; long long pas = 0, mx = 0, mxx = 0, ma = 0; for (vector<long long>::iterator it = shv[q].begin(); it != shv[q].end(); it++) { dfs3((*it), q); pas += dp[(*it)].first; if (mxx < dp[(*it)].second) mxx = dp[(*it)].second; if (ma < dp[(*it)].second - dp[(*it)].first) ma = dp[(*it)].second - dp[(*it)].first; } if (ka[q] == 1) { dp[q].first = pas + f[q]; } dp[q].second = pas + f[q] + ma; } int main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); cin >> a >> b; for (i = 1; i <= a; i++) cin >> f[i]; for (i = 1; i <= b; i++) { cin >> c >> d; v[c].push_back(d); v[d].push_back(c); } cin >> s; dfs(s, 0); dfs2(s, 0); dfs3(s, 0); cout << dp[s].second; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 2505; int n, m, K, a[2][N][N], L[N][8], R[N][8], Lc[N][8], Rc[N][8]; char s[N]; long long ans; void work(int x1, int x2, int y1, int y2, int d) { if (y2 - y1 > x2 - x1) { swap(x1, y1), swap(x2, y2), d ^= 1; } if (x1 + 1 == x2) { ans += a[d][y1][x2] - a[d][y1][x1] == K; return; } int mid = x1 + x2 >> 1; work(x1, mid, y1, y2, d), work(mid, x2, y1, y2, d); for (int i = y1; i < y2; ++i) { for (int k = 0; k < K + 1; ++k) L[i][k] = x1, Lc[i][k] = 0, R[i][k] = x2, Rc[i][k] = 0; for (int j = y1; j < i + 1; ++j) { for (int k = 0; k < K + 1; ++k) { Lc[j][k] += a[d][i][mid] - a[d][i][L[j][k]]; while (Lc[j][k] > k) Lc[j][k] -= a[d ^ 1][L[j][k]][i + 1] - a[d ^ 1][L[j][k]][j], ++L[j][k]; Rc[j][k] += a[d][i][R[j][k]] - a[d][i][mid]; while (Rc[j][k] > k) --R[j][k], Rc[j][k] -= a[d ^ 1][R[j][k]][i + 1] - a[d ^ 1][R[j][k]][j]; } for (int k = 0; k < K + 1; ++k) ans += ((k ? L[j][k - 1] : mid) - L[j][k]) * (R[j][K - k] - (K - k ? R[j][K - k - 1] : mid)); } } } int main() { scanf( %d%d%d , &n, &m, &K); for (int i = 0; i < n; ++i) { scanf( %s , s); for (int j = 0; j < m; ++j) a[0][i][j + 1] = a[1][j][i + 1] = s[j] - 48; } for (int i = 0; i < n; ++i) for (int j = 0; j < m; ++j) a[0][i][j + 1] += a[0][i][j]; for (int j = 0; j < m; ++j) for (int i = 0; i < n; ++i) a[1][j][i + 1] += a[1][j][i]; work(0, n, 0, m, 1); printf( %I64d n , ans); return 0; } |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:102400000,102400000 ) using namespace std; const int mo = 1000000007; const int inf = 0x3f3f3f3f; const int INF = 2000000000; int n, m, phi; int lt[100008], size[100008], f[100008], vis[100008], a[100008], b[100008], sum, tot, root, pre1[100008], pre2[100008]; long long ans, Alltmp; map<int, int> mp; struct edge { int u, v, w, nt; } eg[100008 * 2]; void add(int u, int v, int w) { eg[++sum] = (edge){u, v, w, lt[u]}; lt[u] = sum; } long long quick(long long x, long long y) { long long res = 1; while (y) { if (y & 1) res = res * x % m; x = x * x % m; y >>= 1; } return res; } void init() { int mm = m; phi = m; for (int i = 2; i * i <= m; i++) { if (mm % i == 0) { while (mm % i == 0) mm /= i; phi = phi / i * (i - 1); } } if (mm > 1) phi = phi / mm * (mm - 1); memset(lt, 0, sizeof(lt)); ; sum = 1; memset(f, 0, sizeof(f)); ; f[0] = INF; memset(vis, 0, sizeof(vis)); ; ans = 0; pre1[0] = 1; pre2[0] = 1; for (int i = 1; i <= 100000; i++) { pre1[i] = 1ll * pre1[i - 1] * 10 % m; pre2[i] = quick(pre1[i], phi - 1); } } void getRoot(int u, int fa) { size[u] = 1; f[u] = 0; for (int i = lt[u]; i; i = eg[i].nt) { int v = eg[i].v; if (vis[v] || v == fa) continue; getRoot(v, u); size[u] += size[v]; f[u] = max(f[u], size[v]); } f[u] = max(f[u], tot - size[u]); if (f[u] < f[root]) root = u; } void getA(int u, int fa, int len) { for (int i = lt[u]; i; i = eg[i].nt) { int v = eg[i].v; if (vis[v] || v == fa) continue; a[v] = (1ll * eg[i].w * pre1[len] + a[u]) % m; getA(v, u, len + 1); } Alltmp += mp[a[u]]; int tp = (m - b[u]) % m; tp = 1ll * tp * pre2[len] % m; if (a[u] == tp) Alltmp--; } void getB(int u, int fa, int len) { int tp = (m - b[u]) % m; tp = 1ll * tp * pre2[len] % m; mp[tp]++; for (int i = lt[u]; i; i = eg[i].nt) { int v = eg[i].v; if (vis[v] || v == fa) continue; b[v] = (1ll * b[u] * 10 + eg[i].w) % m; getB(v, u, len + 1); } } long long calc(int u, int key) { key %= m; Alltmp = 0; mp.clear(); a[u] = b[u] = key; getB(u, 0, key == 0 ? 0 : 1); getA(u, 0, key == 0 ? 0 : 1); return Alltmp; } void solve(int u) { ans += calc(u, 0); vis[u] = 1; for (int i = lt[u]; i; i = eg[i].nt) { int v = eg[i].v; if (vis[v]) continue; ans -= calc(v, eg[i].w); root = 0; tot = size[v]; getRoot(v, u); solve(root); } } int main() { scanf( %d%d , &n, &m); init(); for (int i = 1; i <= n - 1; i++) { int u, v, w; scanf( %d%d%d , &u, &v, &w); add(u + 1, v + 1, w); add(v + 1, u + 1, w); } root = 0; tot = n; getRoot(1, 0); solve(root); cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 10; const int inf = 2147483647; const long double pi = acos(-1); inline unsigned long long read() { unsigned long long data = 0, w = 1; char ch = getchar(); while (ch != - && (ch < 0 || ch > 9 )) ch = getchar(); if (ch == - ) w = -1, ch = getchar(); while (ch <= 9 && ch >= 0 ) data = data * 10 + ch - 48, ch = getchar(); return data * w; } inline void file() { freopen( a .in , r , stdin); freopen( a .out , w , stdout); } int n; inline int check(unsigned long long x) { int mx = 1; for (int i = 2; 1ll * i * i <= x; i++) if (x % i == 0) mx = max((unsigned long long)mx, max((unsigned long long)i, x / i)); return mx; } int main() { n = read(); for (int i = 1; i <= n; i++) { unsigned long long x = read(), r = x; int cnt = 0; while (r) { cnt++; r >>= 1; } if (x == (1ll << cnt) - 1) printf( %d n , check(x)); else printf( %I64d n , (1ll << cnt) - 1); } return 0; } |
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1ps/1ps
module altera_pll_reconfig_top
#(
parameter reconf_width = 64,
parameter device_family = "Stratix V",
parameter RECONFIG_ADDR_WIDTH = 6,
parameter RECONFIG_DATA_WIDTH = 32,
parameter ROM_ADDR_WIDTH = 9,
parameter ROM_DATA_WIDTH = 32,
parameter ROM_NUM_WORDS = 512,
parameter ENABLE_MIF = 0,
parameter MIF_FILE_NAME = ""
) (
//input
input wire mgmt_clk,
input wire mgmt_reset,
//conduits
output wire [reconf_width-1:0] reconfig_to_pll,
input wire [reconf_width-1:0] reconfig_from_pll,
// user data (avalon-MM slave interface)
output wire [31:0] mgmt_readdata,
output wire mgmt_waitrequest,
input wire [5:0] mgmt_address,
input wire mgmt_read,
input wire mgmt_write,
input wire [31:0] mgmt_writedata
);
localparam MIF_ADDR_REG = 6'b011111;
localparam START_REG = 6'b000010;
generate
if (ENABLE_MIF == 1)
begin:mif_reconfig // Generate Reconfig with MIF
// MIF-related regs/wires
reg [RECONFIG_ADDR_WIDTH-1:0] reconfig_mgmt_addr;
reg reconfig_mgmt_read;
reg reconfig_mgmt_write;
reg [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_writedata;
wire reconfig_mgmt_waitrequest;
wire [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_readdata;
wire [RECONFIG_ADDR_WIDTH-1:0] mif2reconfig_addr;
wire mif2reconfig_busy;
wire mif2reconfig_read;
wire mif2reconfig_write;
wire [RECONFIG_DATA_WIDTH-1:0] mif2reconfig_writedata;
wire [ROM_ADDR_WIDTH-1:0] mif_base_addr;
reg mif_select;
reg user_start;
wire reconfig2mif_start_out;
assign mgmt_waitrequest = reconfig_mgmt_waitrequest | mif2reconfig_busy | user_start;
// Don't output readdata if MIF streaming is taking place
assign mgmt_readdata = (mif_select) ? 32'b0 : reconfig_mgmt_readdata;
always @(posedge mgmt_clk)
begin
if (mgmt_reset)
begin
reconfig_mgmt_addr <= 0;
reconfig_mgmt_read <= 0;
reconfig_mgmt_write <= 0;
reconfig_mgmt_writedata <= 0;
user_start <= 0;
end
else
begin
reconfig_mgmt_addr <= (mif_select) ? mif2reconfig_addr : mgmt_address;
reconfig_mgmt_read <= (mif_select) ? mif2reconfig_read : mgmt_read;
reconfig_mgmt_write <= (mif_select) ? mif2reconfig_write : mgmt_write;
reconfig_mgmt_writedata <= (mif_select) ? mif2reconfig_writedata : mgmt_writedata;
user_start <= (mgmt_address == START_REG && mgmt_write == 1'b1) ? 1'b1 : 1'b0;
end
end
always @(*)
begin
if (mgmt_reset)
begin
mif_select <= 0;
end
else
begin
mif_select <= (reconfig2mif_start_out || mif2reconfig_busy) ? 1'b1 : 1'b0;
end
end
altera_pll_reconfig_mif_reader
#(
.RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH),
.RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH),
.ROM_ADDR_WIDTH(ROM_ADDR_WIDTH),
.ROM_DATA_WIDTH(ROM_DATA_WIDTH),
.ROM_NUM_WORDS(ROM_NUM_WORDS),
.DEVICE_FAMILY(device_family),
.ENABLE_MIF(ENABLE_MIF),
.MIF_FILE_NAME(MIF_FILE_NAME)
) altera_pll_reconfig_mif_reader_inst0 (
.mif_clk(mgmt_clk),
.mif_rst(mgmt_reset),
//Altera_PLL Reconfig interface
//inputs
.reconfig_busy(reconfig_mgmt_waitrequest),
.reconfig_read_data(reconfig_mgmt_readdata),
//outputs
.reconfig_write_data(mif2reconfig_writedata),
.reconfig_addr(mif2reconfig_addr),
.reconfig_write(mif2reconfig_write),
.reconfig_read(mif2reconfig_read),
//MIF Ctrl Interface
//inputs
.mif_base_addr(mif_base_addr),
.mif_start(reconfig2mif_start_out),
//outputs
.mif_busy(mif2reconfig_busy)
);
// ------ END MIF-RELATED MANAGEMENT ------
altera_pll_reconfig_core
#(
.reconf_width(reconf_width),
.device_family(device_family),
.RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH),
.RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH),
.ROM_ADDR_WIDTH(ROM_ADDR_WIDTH),
.ROM_DATA_WIDTH(ROM_DATA_WIDTH),
.ROM_NUM_WORDS(ROM_NUM_WORDS)
) altera_pll_reconfig_core_inst0 (
//inputs
.mgmt_clk(mgmt_clk),
.mgmt_reset(mgmt_reset),
//PLL interface conduits
.reconfig_to_pll(reconfig_to_pll),
.reconfig_from_pll(reconfig_from_pll),
//User data outputs
.mgmt_readdata(reconfig_mgmt_readdata),
.mgmt_waitrequest(reconfig_mgmt_waitrequest),
//User data inputs
.mgmt_address(reconfig_mgmt_addr),
.mgmt_read(reconfig_mgmt_read),
.mgmt_write(reconfig_mgmt_write),
.mgmt_writedata(reconfig_mgmt_writedata),
// other
.mif_start_out(reconfig2mif_start_out),
.mif_base_addr(mif_base_addr)
);
end // End generate reconfig with MIF
else
begin:reconfig_core // Generate Reconfig core only
wire reconfig2mif_start_out;
wire [ROM_ADDR_WIDTH-1:0] mif_base_addr;
altera_pll_reconfig_core
#(
.reconf_width(reconf_width),
.device_family(device_family),
.RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH),
.RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH),
.ROM_ADDR_WIDTH(ROM_ADDR_WIDTH),
.ROM_DATA_WIDTH(ROM_DATA_WIDTH),
.ROM_NUM_WORDS(ROM_NUM_WORDS)
) altera_pll_reconfig_core_inst0 (
//inputs
.mgmt_clk(mgmt_clk),
.mgmt_reset(mgmt_reset),
//PLL interface conduits
.reconfig_to_pll(reconfig_to_pll),
.reconfig_from_pll(reconfig_from_pll),
//User data outputs
.mgmt_readdata(mgmt_readdata),
.mgmt_waitrequest(mgmt_waitrequest),
//User data inputs
.mgmt_address(mgmt_address),
.mgmt_read(mgmt_read),
.mgmt_write(mgmt_write),
.mgmt_writedata(mgmt_writedata),
// other
.mif_start_out(reconfig2mif_start_out),
.mif_base_addr(mif_base_addr)
);
end // End generate reconfig core only
endgenerate
endmodule
|
//---------------------------------------------------------------------
//
// Company: UNSW
// Original Author: Lingkan Gong
// Project Name: XDRS Demo
//
// Create Date: 17/07/2012
// Design Name: region_wrapper
//
//---------------------------------------------------------------------
`timescale 1ns/1ns
module region_wrapper
#(parameter
RRID = 0
)
(
input clk ,
input rstn ,
//-- to/from producer/consumer ----
output p_prdy ,
input p_crdy ,
input p_cerr ,
output [31:0] p_data ,
input c_prdy ,
output c_crdy ,
output c_cerr ,
input [31:0] c_data ,
//-- to/from reconfiguration controller----
input rc_reqn ,
output rc_ackn ,
input is_reconfn
);
wire rc_ackn_rr ;
wire p_prdy_rr ;
wire [31:0] p_data_rr ;
wire c_crdy_rr ;
wire c_cerr_rr ;
generate begin : gen_rr
if (RRID == 0) begin : gen_0
math_0_rr math_0 (
.clk (clk ),
.rstn (rstn ),
.p_prdy (p_prdy_rr ),
.p_crdy (p_crdy ),
.p_cerr (p_cerr ),
.p_data (p_data_rr ),
.c_prdy (c_prdy ),
.c_crdy (c_crdy_rr ),
.c_cerr (c_cerr_rr ),
.c_data (c_data ),
.rc_reqn (rc_reqn ),
.rc_ackn (rc_ackn_rr )
);
end else if (RRID == 1) begin : gen_1
math_1_rr math_1 (
.clk (clk ),
.rstn (rstn ),
.p_prdy (p_prdy_rr ),
.p_crdy (p_crdy ),
.p_cerr (p_cerr ),
.p_data (p_data_rr ),
.c_prdy (c_prdy ),
.c_crdy (c_crdy_rr ),
.c_cerr (c_cerr_rr ),
.c_data (c_data ),
.rc_reqn (rc_reqn ),
.rc_ackn (rc_ackn_rr )
);
end else if (RRID == 2) begin : gen_2
lpfilter_2_rr lpfilter_2 (
.clk (clk ),
.rstn (rstn ),
.p_prdy (p_prdy_rr ),
.p_crdy (p_crdy ),
.p_cerr (p_cerr ),
.p_data (p_data_rr ),
.c_prdy (c_prdy ),
.c_crdy (c_crdy_rr ),
.c_cerr (c_cerr_rr ),
.c_data (c_data ),
.rc_reqn (rc_reqn ),
.rc_ackn (rc_ackn_rr )
);
end
end endgenerate
isolator isol_0 (
//-- to/from reconfiguration-add-ons----
.rc_ackn_rr (rc_ackn_rr ),
.rc_ackn (rc_ackn ),
//-- to/from producer/consumer ----
.p_prdy (p_prdy ),
.p_prdy_rr (p_prdy_rr ),
.p_data (p_data ),
.p_data_rr (p_data_rr ),
.c_crdy (c_crdy ),
.c_crdy_rr (c_crdy_rr ),
.c_cerr (c_cerr ),
.c_cerr_rr (c_cerr_rr ),
//-- to/from reconfiguration manager----
.is_reconfn (is_reconfn )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int a, b, c, k, k1, ans; int main() { cin >> a >> b >> c; if (b > c) swap(b, c); if (b <= a / 2 && c > a / 2) { cout << Final! << endl; return 0; } while (c != b) { b++; c++; b /= 2; c /= 2; ans++; } cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int t; cin >> t; while (t--) { long long x1, y1, x2, y2; cin >> x1 >> y1 >> x2 >> y2; if (x1 == x2) { cout << abs(y1 - y2) << endl; } else if (y1 == y2) { cout << abs(x1 - x2) << endl; } else cout << abs(x1 - x2) + abs(y1 - y2) + 2 << endl; } return 0; } |
#include <bits/stdc++.h> const int nax = 1e5 + 5; using namespace std; int gcd(int x, int y) { if (x % y == 0) return y; return gcd(y, x % y); } int main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; int n, m; cin >> n >> m; vector<int> a(n + 1), b(m + 1); for (int i = 0; i <= n; i++) { cin >> a[i]; } for (int i = 0; i <= m; i++) { cin >> b[i]; } if (n != m) { if (n > m) { if ((a[0] > 0 && b[0] > 0) || (a[0] < 0 && b[0] < 0)) { puts( Infinity ); } else { puts( -Infinity ); } } else { cout << 0/1 << n ; } return 0; } else { int ans = gcd(a[0], b[0]); if ((a[0] > 0 && b[0] > 0) || (a[0] < 0 && b[0] < 0)) cout << a[0] / ans << / << b[0] / ans << n ; else cout << -abs(a[0] / ans) << / << abs(b[0] / ans) << n ; } return 0; } |
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: wdata_mux.v
//
// Description:
// Contains MI-side write command queue.
// SI-slot index selected by AW arbiter is pushed onto queue when S_AVALID transfer is received.
// Queue is popped when WLAST data beat is transferred.
// W-channel input from SI-slot selected by queue output is transferred to MI-side output .
//--------------------------------------------------------------------------
//
// Structure:
// wdata_mux
// axic_reg_srl_fifo
// mux_enc
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_10_wdata_mux #
(
parameter C_FAMILY = "none", // FPGA Family.
parameter integer C_WMESG_WIDTH = 1, // Width of W-channel payload.
parameter integer C_NUM_SLAVE_SLOTS = 1, // Number of S_* ports.
parameter integer C_SELECT_WIDTH = 1, // Width of ASELECT.
parameter integer C_FIFO_DEPTH_LOG = 0 // Queue depth = 2**C_FIFO_DEPTH_LOG.
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave Data Ports
input wire [C_NUM_SLAVE_SLOTS*C_WMESG_WIDTH-1:0] S_WMESG,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_WLAST,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_WVALID,
output wire [C_NUM_SLAVE_SLOTS-1:0] S_WREADY,
// Master Data Ports
output wire [C_WMESG_WIDTH-1:0] M_WMESG,
output wire M_WLAST,
output wire M_WVALID,
input wire M_WREADY,
// Write Command Ports
input wire [C_SELECT_WIDTH-1:0] S_ASELECT, // SI-slot index from AW arbiter
input wire S_AVALID,
output wire S_AREADY
);
localparam integer P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG <= 5) ? C_FIFO_DEPTH_LOG : 5; // Max depth = 32
// Decode select input to 1-hot
function [C_NUM_SLAVE_SLOTS-1:0] f_decoder (
input [C_SELECT_WIDTH-1:0] sel
);
integer i;
begin
for (i=0; i<C_NUM_SLAVE_SLOTS; i=i+1) begin
f_decoder[i] = (sel == i);
end
end
endfunction
wire m_valid_i;
wire m_last_i;
wire [C_NUM_SLAVE_SLOTS-1:0] m_select_hot;
wire [C_SELECT_WIDTH-1:0] m_select_enc;
wire m_avalid;
wire m_aready;
generate
if (C_NUM_SLAVE_SLOTS>1) begin : gen_wmux
// SI-side write command queue
axi_data_fifo_v2_1_8_axic_reg_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (C_SELECT_WIDTH),
.C_FIFO_DEPTH_LOG (P_FIFO_DEPTH_LOG),
.C_USE_FULL (0)
)
wmux_aw_fifo
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (S_ASELECT),
.S_VALID (S_AVALID),
.S_READY (S_AREADY),
.M_MESG (m_select_enc),
.M_VALID (m_avalid),
.M_READY (m_aready)
);
assign m_select_hot = f_decoder(m_select_enc);
// Instantiate MUX
generic_baseblocks_v2_1_0_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (C_NUM_SLAVE_SLOTS),
.C_SEL_WIDTH (C_SELECT_WIDTH),
.C_DATA_WIDTH (C_WMESG_WIDTH)
) mux_w
(
.S (m_select_enc),
.A (S_WMESG),
.O (M_WMESG),
.OE (1'b1)
);
assign m_last_i = |(S_WLAST & m_select_hot);
assign m_valid_i = |(S_WVALID & m_select_hot);
assign m_aready = m_valid_i & m_avalid & m_last_i & M_WREADY;
assign M_WLAST = m_last_i;
assign M_WVALID = m_valid_i & m_avalid;
assign S_WREADY = m_select_hot & {C_NUM_SLAVE_SLOTS{m_avalid & M_WREADY}};
end else begin : gen_no_wmux
assign S_AREADY = 1'b1;
assign M_WVALID = S_WVALID;
assign S_WREADY = M_WREADY;
assign M_WLAST = S_WLAST;
assign M_WMESG = S_WMESG;
end
endgenerate
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; typedef struct { long long loc; long long num; } amar; bool operator<(amar x, amar y) { if (x.num >= y.num) return false; else return true; } int main() { long long n, k, c[40]; char s[100005]; memset(c, 0, sizeof c); cin >> n >> k >> s; for (long long i = 0; i < n; i++) { c[s[i] - A ]++; } priority_queue<amar> a; amar tmp; for (long long i = 0; i < 40; i++) { tmp.loc = i; tmp.num = c[i]; a.push(tmp); } long long ans = 0; while (k > 0 && !a.empty()) { tmp = a.top(); if (k >= tmp.num) { ans += (tmp.num * tmp.num); k -= tmp.num; } else if (k < tmp.num) { ans += k * k; k = 0; } a.pop(); } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; const int maxn = 1e5 + 5; vector<int> a[maxn]; int res[maxn]; int main() { int n, m; scanf( %d%d , &n, &m); for (int i = 0; i < n; i++) { int q, w; scanf( %d%d , &q, &w); a[q].push_back(w); } int ms = 0; for (int i = 1; i <= m; i++) { int sump = a[i].size(); sort(a[i].begin(), a[i].end()); ms = max(sump, ms); int sum = 0; for (int j = sump - 1; j >= 0; j--) { sum += a[i][j]; if (sum >= 0) res[sump - j] += sum; else break; } } int max1 = 0; for (int i = 1; i <= ms; i++) max1 = max(res[i], max1); printf( %d n , max1); } |
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tb_pfpu();
`define TEST_SIMPLE
`define TEST_SUM
//`define TEST_ROTATION
/* 100MHz system clock */
reg sys_clk;
initial sys_clk = 1'b0;
always #5 sys_clk = ~sys_clk;
reg sys_rst;
reg [13:0] csr_a;
reg csr_we;
reg [31:0] csr_di;
wire [31:0] csr_do;
wire irq;
wire [31:0] wbm_dat_o;
wire [31:0] wbm_adr_o;
wire wbm_cyc_o;
wire wbm_stb_o;
reg wbm_ack_i;
real r;
always @(posedge sys_clk) begin
if(sys_rst)
wbm_ack_i <= 1'b0;
else begin
wbm_ack_i <= 1'b0;
if(wbm_stb_o & ~wbm_ack_i & (($random % 3) == 0)) begin
wbm_ack_i <= 1'b1;
$fromfloat(wbm_dat_o, r);
$display("DMA write addr %x:%x (%b - %f)", wbm_adr_o, wbm_dat_o, wbm_adr_o[2], r);
end
end
end
pfpu dut(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.csr_a(csr_a),
.csr_we(csr_we),
.csr_di(csr_di),
.csr_do(csr_do),
.irq(irq),
.wbm_dat_o(wbm_dat_o),
.wbm_adr_o(wbm_adr_o),
.wbm_cyc_o(wbm_cyc_o),
.wbm_stb_o(wbm_stb_o),
.wbm_ack_i(wbm_ack_i)
);
task waitclock;
begin
@(posedge sys_clk);
#1;
end
endtask
task waitnclock;
input [15:0] n;
integer i;
begin
for(i=0;i<n;i=i+1)
waitclock;
end
endtask
task csrwrite;
input [31:0] address;
input [31:0] data;
begin
csr_a = address[16:2];
csr_di = data;
csr_we = 1'b1;
waitclock;
$display("Configuration Write: %x=%x", address, data);
csr_we = 1'b0;
end
endtask
task csrread;
input [31:0] address;
real rrv;
begin
csr_a = address[16:2];
waitclock;
$fromfloat(csr_do, rrv);
$display("Configuration Read : %x=%x (%f)", address, csr_do,rrv);
end
endtask
task showdiags;
begin
$display("Vertices:");
csrread(32'h0014);
$display("Collisions:");
csrread(32'h0018);
$display("Stray writes:");
csrread(32'h001C);
$display("Pending DMA requests:");
csrread(32'h0020);
$display("Program counter:");
csrread(32'h0024);
end
endtask
reg [31:0] a;
always begin
/* Reset / Initialize our logic */
sys_rst = 1'b1;
csr_a = 14'd0;
csr_di = 32'd0;
csr_we = 1'b0;
waitclock;
sys_rst = 1'b0;
waitclock;
`ifdef TEST_SIMPLE
/* TEST 1 - Compute the sum of two registers and write the value via DMA */
/* Mesh size : 1x1 */
csrwrite(32'h0008, 32'd0);
csrwrite(32'h000C, 32'd0);
/* Write test operands to register file */
$tofloat(3.0, a);
csrwrite(32'h040C, a);
$tofloat(9.0, a);
csrwrite(32'h0410, a);
/* Check they are correctly written */
csrread(32'h040C);
csrread(32'h0410);
/* Load test microcode */
/* PAD OPA OPB OPCD DEST */
csrwrite(32'h0800, 32'b0000000_0000011_0000100_0001_0000000); /* FADD R3, R4 */
csrwrite(32'h0804, 32'b0000000_0000000_0000000_0000_0000000); /* NOP */
csrwrite(32'h0808, 32'b0000000_0000000_0000000_0000_0000000); /* NOP */
csrwrite(32'h080C, 32'b0000000_0000000_0000000_0000_0000000); /* NOP */
csrwrite(32'h0810, 32'b0000000_0000000_0000000_0000_0000000); /* NOP */
csrwrite(32'h0814, 32'b0000000_0000000_0000000_0000_0000011); /* NOP | EXIT R3 */
csrwrite(32'h0818, 32'b0000000_0000011_0000100_0111_0000000); /* VECTOUT R3, R4 */
/* DMA base */
csrwrite(32'h0004, 32'h401de328);
/* Start */
csrwrite(32'h0000, 32'h00000001);
@(posedge irq);
showdiags;
`endif
`ifdef TEST_SUM
/* TEST 2 - Compute the sum of the two mesh coordinates and write it via DMA,
* for each vertex.
*/
/* Mesh size : 12x10 */
csrwrite(32'h0008, 32'd11);
csrwrite(32'h000C, 32'd9);
/* Load test microcode */
/* PAD OPA OPB OPCD DEST */
csrwrite(32'h0800, 32'b0000000_0000000_0000000_0110_0000000); /* I2F R0 */
csrwrite(32'h0804, 32'b0000000_0000001_0000000_0110_0000000); /* I2F R1 */
csrwrite(32'h0808, 32'b0000000_0000000_0000000_0000_0000000); /* NOP */
csrwrite(32'h080C, 32'b0000000_0000000_0000000_0000_0000011); /* NOP | EXIT R3 */
csrwrite(32'h0810, 32'b0000000_0000000_0000000_0000_0000100); /* NOP | EXIT R4 */
csrwrite(32'h0814, 32'b0000000_0000011_0000100_0001_0000000); /* FADD R3, R4 */
csrwrite(32'h0818, 32'b0000000_0000000_0000000_0000_0000000); /* NOP */
csrwrite(32'h081C, 32'b0000000_0000000_0000000_0000_0000000); /* NOP */
csrwrite(32'h0820, 32'b0000000_0000000_0000000_0000_0000000); /* NOP */
csrwrite(32'h0824, 32'b0000000_0000000_0000000_0000_0000000); /* NOP */
csrwrite(32'h0828, 32'b0000000_0000000_0000000_0000_0000101); /* NOP | EXIT R5 */
csrwrite(32'h082C, 32'b0000000_0000101_0000101_0111_0000000); /* VECTOUT R5, R5 */
/* DMA base */
csrwrite(32'h0004, 32'h401de328);
/* Start */
csrwrite(32'h0000, 32'h00000001);
@(posedge irq);
showdiags;
`endif
$finish;
end
endmodule
|
// UC Berkeley CS251
// Spring 2018
// Arya Reais-Parsi ()
// emacs --batch riscv_top.v -f verilog-batch-auto
`include "const.vh"
module riscv_top
(
input clk,
input reset,
output mem_req_valid,
input mem_req_ready,
output mem_req_rw,
output [`MEM_ADDR_BITS-1:0] mem_req_addr,
output [`MEM_TAG_BITS-1:0] mem_req_tag,
output mem_req_data_valid,
input mem_req_data_ready,
output [`MEM_DATA_BITS-1:0] mem_req_data_bits,
output [(`MEM_DATA_BITS/8)-1:0] mem_req_data_mask,
input mem_resp_valid,
input [`MEM_TAG_BITS-1:0] mem_resp_tag,
input [`MEM_DATA_BITS-1:0] mem_resp_data,
output [31:0] csr
);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] dcache_addr; // From cpu of Riscv141.v
wire [31:0] dcache_din; // From cpu of Riscv141.v
wire [31:0] dcache_dout; // From mem of Memory141.v
wire dcache_val;
wire dcache_re; // From cpu of Riscv141.v
wire [3:0] dcache_we; // From cpu of Riscv141.v
wire [31:0] icache_addr; // From cpu of Riscv141.v
wire [31:0] icache_dout; // From mem of Memory141.v
wire icache_re; // From cpu of Riscv141.v
wire stall; // From mem of Memory141.v
// End of automatics
Memory141 mem(
/*AUTOINST*/
// Outputs
.dcache_dout (dcache_dout[31:0]),
.dcache_val (dcache_val),
.icache_dout (icache_dout[31:0]),
.stall (stall),
.mem_req_valid (mem_req_valid),
.mem_req_rw (mem_req_rw),
.mem_req_addr (mem_req_addr[`MEM_ADDR_BITS-1:0]),
.mem_req_tag (mem_req_tag[`MEM_TAG_BITS-1:0]),
.mem_req_data_valid (mem_req_data_valid),
.mem_req_data_bits (mem_req_data_bits[`MEM_DATA_BITS-1:0]),
.mem_req_data_mask (mem_req_data_mask[(`MEM_DATA_BITS/8)-1:0]),
// Inputs
.clk (clk),
.reset (reset),
.dcache_addr (dcache_addr[31:0]),
.icache_addr (icache_addr[31:0]),
.dcache_we (dcache_we[3:0]),
.dcache_re (dcache_re),
.icache_re (icache_re),
.dcache_din (dcache_din[31:0]),
.mem_req_ready (mem_req_ready),
.mem_req_data_ready (mem_req_data_ready),
.mem_resp_valid (mem_resp_valid),
.mem_resp_data (mem_resp_data[`MEM_DATA_BITS-1:0]),
.mem_resp_tag (mem_resp_tag[`MEM_TAG_BITS-1:0]));
// RISC-V 141 CPU
Riscv141 cpu(
/*AUTOINST*/
// Outputs
.dcache_addr (dcache_addr[31:0]),
.icache_addr (icache_addr[31:0]),
.dcache_we (dcache_we[3:0]),
.dcache_re (dcache_re),
.icache_re (icache_re),
.dcache_din (dcache_din[31:0]),
// Inputs
.clk (clk),
.reset (reset),
.dcache_dout (dcache_dout[31:0]),
.dcache_val (dcache_val),
.icache_dout (icache_dout[31:0]),
.csr (csr),
.stall (stall));
endmodule
// Local Variables:
// verilog-library-extensions:(".v" ".vh")
// verilog-library-directories:(".")
// End:
|
#include <bits/stdc++.h> using namespace std; int n, a[105], c, x, k; int main() { cin >> n; for (int i = 0; i < 2; i++) { cin >> x; while (x--) cin >> k, c += 1 - a[k], a[k] = 1; } cout << (c == n ? I become the guy. : Oh, my keyboard! ); } |
#include <bits/stdc++.h> using namespace std; struct node { int v, d; bool operator<(const node &a) const { if (d == a.d) return v < a.v; return a.d < d; } }; set<node> s; vector<int> adj[200005]; int d[200005], p[200005]; bool vis[200005]; void dfs(int u) { int l = adj[u].size(); node nd; vis[u] = true; for (int a = 0; a < l; a++) { int v = adj[u][a]; if (!vis[v] && v != p[u]) dfs(v); } nd.v = u, nd.d = d[u]; s.erase(nd); } int main() { int n, ans = 0; cin >> n; for (int a = 1; a < n; a++) { int u, v; cin >> u >> v; adj[u].push_back(v); adj[v].push_back(u); } queue<int> q; node nd; q.push(1); d[1] = p[1] = 0, vis[1] = true; while (!q.empty()) { int u = q.front(); q.pop(); nd.v = u, nd.d = d[u]; s.insert(nd); int l = adj[u].size(); for (int a = 0; a < l; a++) { int v = adj[u][a]; if (vis[v]) continue; d[v] = 1 + d[u], p[v] = u; q.push(v), vis[v] = true; } } memset(vis, false, sizeof(vis)); while (!s.empty()) { nd = *(s.begin()); if (nd.d > 2) { dfs(p[nd.v]), ans++; nd.v = p[p[nd.v]]; nd.d = d[nd.v]; s.erase(nd); } else break; } cout << ans << endl; return 0; } |
`timescale 1ns/10ps
module pll_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("true"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("normal"),
.number_of_clocks(2),
.output_clock_frequency0("25.174999 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("107.892852 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_1, outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long mod = 998244353; long long a_na_b_mod_c(long long a, long long b, long long c) { if (b == 0) return 1; long long t = a_na_b_mod_c(a, (b / 2), c) % c; if (b % 2 == 0) return (t * t) % c; else return (((t * t) % c) * (a % c)) % c; } long long ip(long long a) { return a_na_b_mod_c(a, mod - 2, mod); } vector<long long> f(1, 1), fi; long long nCk(long long n, long long k) { return (((f[n] * fi[k]) % mod) * fi[n - k]) % mod; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n; long long k; cin >> n >> k; if (!k) { cout << 0 n ; return 0; } for (int i = 1; i < n + 79; i++) f.push_back((f.back() * i) % mod); fi.resize(n + 79); for (int i = 0; i < n + 79; i++) fi[i] = ip(f[i]); vector<int> h(n); for (int i = 0; i < n; i++) { cin >> h[i]; } h.push_back(h[0]); long long eq = 0; for (int i = 1; i <= n; i++) { if (h[i] == h[i - 1]) eq++; } long long dif = n - eq; if (!dif) { cout << 0 n ; return 0; } long long all = 0; long long i2 = ip(2); long long p2 = a_na_b_mod_c(2, dif, mod); long long kp2 = 1; for (long long z = 0; z < dif; z++) { long long non_zero = dif - z; long long good = p2; long long zero = non_zero % 2 == 1 ? 0 : nCk(non_zero, non_zero >> 1); good = ((good - zero + mod) * i2) % mod; all += (((good * nCk(dif, z)) % mod) * kp2) % mod; all %= mod; p2 = (p2 * i2) % mod; kp2 = (kp2 * (k - 2)) % mod; } cout << (all * a_na_b_mod_c(k, eq, mod)) % mod << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int t, n, k; char a[5][500]; bool vis[5][500], check; bool valid(int x, int y) { if (x < 0 || x > 2 || vis[x][y]) return 0; return 1; } void dfs(int x, int y, int tm) { if (!valid(x, y) || check) return; if (a[x][y + 2 * tm] != . ) return; vis[x][y] = 1; if (y >= n - 1) { check = 1; return; } if (a[x][y + 2 * tm + 1] != . ) return; dfs(x, y + 1, tm + 1); if (a[x + 1][y + 1 + 2 * tm] == . ) dfs(x + 1, y + 1, tm + 1); if (a[x - 1][y + 1 + 2 * tm] == . ) dfs(x - 1, y + 1, tm + 1); } int main() { cin >> t; while (t--) { check = 0; memset(vis, 0, sizeof(vis)); for (int i = 0; i < 4; i++) for (int j = 0; j < 500; j++) a[i][j] = . ; cin >> n >> k; for (int i = 0; i < 3; i++) for (int j = 0; j < n; j++) cin >> a[i][j]; int p; for (int i = 0; i < 3; i++) if (a[i][0] == s ) p = i; a[p][0] = . ; dfs(p, 0, 0); if (check) cout << YES n ; else cout << NO n ; } return 0; } |
// megafunction wizard: %LPM_COUNTER%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_COUNTER
// ============================================================
// File Name: xxx_test_counter.v
// Megafunction Name(s):
// LPM_COUNTER
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 263 08/02/2012 SP 2.16 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module xxx_test_counter (
clock,
q);
input clock;
output [5:0] q;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACLR NUMERIC "0"
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
// Retrieval info: PRIVATE: ASET NUMERIC "0"
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
// Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
// Retrieval info: PRIVATE: Direction NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
// Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: SSET NUMERIC "0"
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: nBit NUMERIC "6"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
// Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "6"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: q 0 0 6 0 OUTPUT NODEFVAL "q[5..0]"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 6 0 @q 0 0 6 0
// Retrieval info: GEN_FILE: TYPE_NORMAL xxx_test_counter.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL xxx_test_counter.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL xxx_test_counter.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL xxx_test_counter.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL xxx_test_counter_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL xxx_test_counter_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module bd_c3fe_slot_0_r_0 (
In0,
In1,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
output wire [1 : 0] dout;
xlconcat_v2_1_1_xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(2),
.NUM_PORTS(2)
) inst (
.In0(In0),
.In1(In1),
.In2(1'B0),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; using namespace std; long long z = 1000000007; long long gcd(long long a, long long b) { if (a == 0) return b; if (b == 0) return a; return gcd(b, a % b); } long long power(long long a, long long b) { long long res = 1; while (b) { if (b & 1) { res = (res * a) % z; b--; } else { a = (a * a) % z; b = b >> 1; } } return res; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long t; t = 1; while (t--) { long long s, x; cin >> s >> x; long long k = s - x; if (k & 1) cout << 0 n ; else { long long ans = 1, c = 0; set<long long> s; k /= 2; for (long long i = 0; i < 64; i++) if (k & ((long long)1 << i)) s.insert(i); for (long long i = 0; i < 64; i++) { if (x & ((long long)1 << i)) { ans *= 2; if (s.find(i) != s.end()) { c++; break; } } } if (c) cout << 0 n ; else { if (k == 0) cout << ans - 2 << n ; else cout << ans << n ; } } } } |
#include <bits/stdc++.h> using namespace std; const int INF = INT_MAX; const long long INFL = LLONG_MAX; const long double pi = acos(-1); const int MOD = 1e9 + 7; int ans; int N; inline long long mod(long long a) { a %= MOD; a += MOD; a %= MOD; return a; } inline int add(int a, int b) { return int(mod(mod(a) + mod(b))); } inline int mul(int a, int b) { return int(mod(mod(a) * 1LL * mod(b))); } map<int, int> DP[1 << 16]; int dfs(int n, int used, int seen) { if (n == N) { return 1; } if (DP[used].find(seen) != DP[used].end()) return DP[used][seen]; int& cnt = DP[used][seen]; for (int(i) = 0, j123 = N; (i) < j123; (i)++) { if (!((used >> i) & 1)) { int k = (n + i) % N; if (!((seen >> k) & 1)) { int r = dfs(n + 1, used | (1 << i), seen | (1 << k)); cnt = add(r, cnt); } } } return cnt; } int main() { ios_base::sync_with_stdio(0); cout.precision(15); cout << fixed; cout.tie(0); cin >> N; if (N == 15) { ans = 150347555; } else if (N & 1) { ans = dfs(0, 0, 0); for (int(i) = 1, j123 = N; (i) <= j123; (i)++) ans = mul(i, ans); } cout << ans << n ; } |
#include <bits/stdc++.h> using namespace std; vector<vector<int> > solve(int N) { vector<vector<int> > res(2, vector<int>(1, 1)); for (int n = 2, r = 0; n <= N; ++n) { res[r].push_back(n); ++r; if (r >= int((res).size())) { vector<int> new_row; for (const vector<int>& r : res) new_row.push_back(r.back()); res.push_back(new_row); r = 0; } } return res; } int main(int argc, char* argv[]) { ios_base::sync_with_stdio(false); cin.tie(nullptr); int N; cin >> N; vector<vector<int> > res = solve(N); cout << int((res).size()) << n ; for (const vector<int>& row : res) { for (int x : row) cout << x << ; cout << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long t; cin >> t; while (t--) { long long a, b, sum = 0; cin >> a >> b; while (a > 0 && b > 0) { if (a < b) swap(a, b); sum += a / b; a = a - b * (a / b); } cout << sum << endl; } return 0; } |
module tb_m_elink_stub;
reg [1:0] elink_txrr_packet;
reg elink_txi_wr_wait_p;
wire elink_txo_lclk_p;
wire elink_txo_frame_n;
wire elink_rx_lclk_pll;
wire elink_rxwr_access;
reg elink_rxrd_wait;
wire elink_txrd_wait;
wire elink_mailbox_full;
reg elink_rx_ref_clk;
reg elink_tx_lclk;
reg elink_txwr_access;
wire elink_txo_lclk_n;
wire [1:0] elink_rxrr_packet;
wire elink_txrr_wait;
reg elink_rxi_frame_n;
reg [7:0] elink_rxi_data_n;
reg elink_txi_rd_wait_p;
reg elink_txrr_access;
reg elink_sys_clk;
reg [1:0] elink_txrd_packet;
reg elink_txi_rd_wait_n;
reg elink_tx_lclk90;
reg elink_rx_lclk;
reg elink_rxi_frame_p;
wire [7:0] elink_txo_data_n;
reg elink_txrd_access;
wire elink_rxo_rd_wait_p;
reg elink_rxrr_wait;
wire [1:0] elink_rxwr_packet;
wire elink_rxo_rd_wait_n;
wire elink_mailbox_not_empty;
reg elink_txi_wr_wait_n;
wire elink_rxrr_access;
wire elink_txwr_wait;
reg [1:0] elink_txwr_packet;
wire [7:0] elink_txo_data_p;
wire elink_txo_frame_p;
reg elink_reset;
reg elink_rxwr_wait;
wire [1:0] elink_rxrd_packet;
reg elink_rxi_lclk_p;
wire elink_rxo_wr_wait_p;
wire [11:0] elink_chipid;
reg elink_tx_lclk_div4;
wire elink_rxrd_access;
reg [7:0] elink_rxi_data_p;
reg elink_rx_lclk_div4;
wire elink_elink_en;
wire elink_timeout;
wire elink_rxo_wr_wait_n;
reg elink_rxi_lclk_n;
initial begin
$from_myhdl(
elink_txrr_packet,
elink_txi_wr_wait_p,
elink_rxrd_wait,
elink_rx_ref_clk,
elink_tx_lclk,
elink_txwr_access,
elink_rxi_frame_n,
elink_rxi_data_n,
elink_txi_rd_wait_p,
elink_txrr_access,
elink_sys_clk,
elink_txrd_packet,
elink_txi_rd_wait_n,
elink_tx_lclk90,
elink_rx_lclk,
elink_rxi_frame_p,
elink_txrd_access,
elink_rxrr_wait,
elink_txi_wr_wait_n,
elink_txwr_packet,
elink_reset,
elink_rxwr_wait,
elink_rxi_lclk_p,
elink_tx_lclk_div4,
elink_rxi_data_p,
elink_rx_lclk_div4,
elink_rxi_lclk_n
);
$to_myhdl(
elink_txo_lclk_p,
elink_txo_frame_n,
elink_rx_lclk_pll,
elink_rxwr_access,
elink_txrd_wait,
elink_mailbox_full,
elink_txo_lclk_n,
elink_rxrr_packet,
elink_txrr_wait,
elink_txo_data_n,
elink_rxo_rd_wait_p,
elink_rxwr_packet,
elink_rxo_rd_wait_n,
elink_mailbox_not_empty,
elink_rxrr_access,
elink_txwr_wait,
elink_txo_data_p,
elink_txo_frame_p,
elink_rxrd_packet,
elink_rxo_wr_wait_p,
elink_chipid,
elink_rxrd_access,
elink_elink_en,
elink_timeout,
elink_rxo_wr_wait_n
);
end
m_elink_stub dut(
elink_txrr_packet,
elink_txi_wr_wait_p,
elink_txo_lclk_p,
elink_txo_frame_n,
elink_rx_lclk_pll,
elink_rxwr_access,
elink_rxrd_wait,
elink_txrd_wait,
elink_mailbox_full,
elink_rx_ref_clk,
elink_tx_lclk,
elink_txwr_access,
elink_txo_lclk_n,
elink_rxrr_packet,
elink_txrr_wait,
elink_rxi_frame_n,
elink_rxi_data_n,
elink_txi_rd_wait_p,
elink_txrr_access,
elink_sys_clk,
elink_txrd_packet,
elink_txi_rd_wait_n,
elink_tx_lclk90,
elink_rx_lclk,
elink_rxi_frame_p,
elink_txo_data_n,
elink_txrd_access,
elink_rxo_rd_wait_p,
elink_rxrr_wait,
elink_rxwr_packet,
elink_rxo_rd_wait_n,
elink_mailbox_not_empty,
elink_txi_wr_wait_n,
elink_rxrr_access,
elink_txwr_wait,
elink_txwr_packet,
elink_txo_data_p,
elink_txo_frame_p,
elink_reset,
elink_rxwr_wait,
elink_rxrd_packet,
elink_rxi_lclk_p,
elink_rxo_wr_wait_p,
elink_chipid,
elink_tx_lclk_div4,
elink_rxrd_access,
elink_rxi_data_p,
elink_rx_lclk_div4,
elink_elink_en,
elink_timeout,
elink_rxo_wr_wait_n,
elink_rxi_lclk_n
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MOD = 998244353; inline int qpow(int a, int p) { int ans = 1; while (p) { if (p & 1) ans = (long long)ans * a % MOD; a = (long long)a * a % MOD; p >>= 1; } return ans; } inline int add(const int& x, const int& y) { return x + y >= MOD ? x + y - MOD : x + y; } inline int dec(const int& x, const int& y) { return x < y ? x - y + MOD : x - y; } int rt[2][24], r[262144], l, lim; inline void init() { lim = 1 << l; for (int i = 0; i < lim; i++) r[i] = (r[i >> 1] >> 1) | ((i & 1) << (l - 1)); } inline void NTT(int* a, int type) { for (int i = 0; i < lim; i++) if (i < r[i]) swap(a[i], a[r[i]]); for (int L = 0; L < l; L++) { int mid = 1 << L, len = mid << 1; long long Wn = rt[type][L + 1]; for (int s = 0; s < lim; s += len) for (int k = 0, w = 1; k < mid; k++, w = w * Wn % MOD) { int x = a[s + k], y = (long long)w * a[s + mid + k] % MOD; a[s + k] = add(x, y), a[s + mid + k] = dec(x, y); } } if (type) { int t = qpow(lim, MOD - 2); for (int i = 0; i < lim; i++) a[i] = (long long)a[i] * t % MOD; } } int fac[262144], finv[262144]; int f[262144], g[262144], t[262144]; void solve(int n) { if (n == 0) return (void)(f[0] = 1); int m = n >> 1; solve(m); for (l = 0; (1 << l) <= (m << 1); l++) ; init(); for (int i = 0; i <= m; i++) t[i] = f[i], f[i] = (long long)f[i] * fac[i] % MOD; g[m] = 1; for (int i = m - 1; i >= 0; i--) g[i] = (long long)g[i + 1] * m % MOD; for (int i = 0; i <= m; i++) g[i] = (long long)g[i] * finv[m - i] % MOD; for (int i = m + 1; i < lim; i++) g[i] = 0; NTT(f, 0), NTT(g, 0); for (int i = 0; i < lim; i++) g[i] = (long long)f[i] * g[i] % MOD; NTT(g, 1); for (int i = 0; i <= m; i++) g[i] = (long long)g[i + m] * finv[i] % MOD; for (int i = m + 1; i < lim; i++) g[i] = 0; for (int i = 0; i <= m; i++) f[i] = t[i]; for (int i = m + 1; i < lim; i++) f[i] = 0; NTT(f, 0), NTT(g, 0); for (int i = 0; i < lim; i++) f[i] = (long long)f[i] * g[i] % MOD; NTT(f, 1); if (n & 1) { for (int i = n; i >= 1; i--) f[i] = ((n - 1ll) * f[i] + f[i - 1]) % MOD; f[0] = (n - 1ll) * f[0] % MOD; } } int main() { rt[0][23] = qpow(3, 119), rt[1][23] = qpow(rt[0][23], MOD - 2); for (int i = 22; i >= 0; i--) { rt[0][i] = (long long)rt[0][i + 1] * rt[0][i + 1] % MOD; rt[1][i] = (long long)rt[1][i + 1] * rt[1][i + 1] % MOD; } int n, a, b; scanf( %d%d%d , &n, &a, &b); --n, --a, --b; if (a < 0 || b < 0 || n < a + b) return puts( 0 ), 0; fac[0] = 1; for (int i = 1; i <= n; i++) fac[i] = (long long)fac[i - 1] * i % MOD; finv[n] = qpow(fac[n], MOD - 2); for (int i = n - 1; i >= 0; i--) finv[i] = (long long)finv[i + 1] * (i + 1) % MOD; solve(n); int ans = (long long)f[a + b] * fac[a + b] % MOD * finv[a] % MOD * finv[b] % MOD; cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 1e9; const int N = 55; int n, cnt[N]; vector<pair<int, int> > adj[N]; void dfs(int u, int p, int depth, vector<pair<int, int> > &leaves) { bool leaf = 1; for (auto e : adj[u]) { int v, c; tie(v, c) = e; if (v == p) continue; dfs(v, u, depth + c, leaves); leaf = 0; } if (leaf) leaves.emplace_back(u, depth); } int dp[N][N], best[N][N]; int go(int root, int pre, int total, int put) { vector<pair<int, int> > leaves; dfs(root, pre, 0, leaves); int sz = ((int)(leaves).size()); for (int from = (int)(sz + 1) - 1; from >= ((int)0); from--) { for (int left = (int)(0); left < ((int)put + 1); left++) { if (from == sz) { best[from][left] = (left ? -INF : INF); } else { best[from][left] = best[from + 1][left]; int l = leaves[from].first, cost = leaves[from].second; for (int pick = 1; pick <= left; pick++) { best[from][left] = max(best[from][left], min(cost + dp[l][total - pick], best[from + 1][left - pick])); } } } } return best[0][put]; } void dfsSize(int u, int p) { for (auto e : adj[u]) { int v, c; tie(v, c) = e; if (v == p) continue; dfsSize(v, u); cnt[u] += cnt[v]; } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n; for (int _ = 0; _ < (int)(n - 1); _++) { int u, v, c; cin >> u >> v >> c; u--; v--; adj[u].emplace_back(v, c); adj[v].emplace_back(u, c); } int s; cin >> s; s--; int m; cin >> m; for (int _ = 0; _ < (int)(m); _++) { int u; cin >> u; cnt[u - 1]++; } for (int total = 1; total <= m; total++) { for (int u = 0; u < (int)(n); u++) { dp[u][total] = go(u, u, total, total); } } dfsSize(s, -1); int ans = INF; for (auto e : adj[s]) { int v, c; tie(v, c) = e; ans = min(ans, c + go(v, s, m, cnt[v])); } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 4000 + 1; const int sq = 100; const long long int mod = 1e9 + 7; const long long int inf = 4000 + 1; unordered_map<long long int, int> dp; int ps[N], n; inline int get(int l, int r) { return ps[r] - ps[l]; } int solve(int l, int r, int k, bool bol) { if (r - l < k || l >= r || r > n || l < 0) return 0; if (r - l == k && bol) return get(l, r); if (r - l == k) return -get(l, r); long long int key = l * N * sq * 2 + r * sq * 2 + k * 2 + bol; if (dp.count(key)) return dp[key]; int ans, x, y; if (bol) { x = solve(l + k, r, k, 0) + get(l, l + k); y = solve(l + k + 1, r, k + 1, 0) + get(l, l + k + 1); ans = max(x, y); } else { x = solve(l, r - k, k, 1) - get(r - k, r); y = solve(l, r - k - 1, k + 1, 1) - get(r - k - 1, r); ans = min(x, y); } return dp[key] = ans; } int main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); dp.rehash(16e6); scanf( %d , &n); for (int i = 0; i < n; i++) { int x; scanf( %d , &x); ps[i + 1] = ps[i] + x; } printf( %d n , solve(0, n, 1, 1)); return 0; } |
#include <bits/stdc++.h> int main() { int n, m; scanf( %d %d , &n, &m); int c[n], a[m]; int i; for (i = 0; i < n; i++) { scanf( %d , &c[i]); } for (i = 0; i < m; i++) { scanf( %d , &a[i]); } int j = 0, count = 0; int t = 0; for (i = 0; i < m;) { if (j >= n) break; for (j = t; j < n; j++) { if (i >= m) { break; } if (a[i] >= c[j]) { i = i + 1; t = j + 1; count = count + 1; } } } printf( %d n , count); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MAJ3_BLACKBOX_V
`define SKY130_FD_SC_HS__MAJ3_BLACKBOX_V
/**
* maj3: 3-input majority vote.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__maj3 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__MAJ3_BLACKBOX_V
|
/****************************************************************
/*
/* Description:
/* count the frequency of each signal,
/* for the huffman codeing processs afterwards
/* Author:
/* Guozhu Xin
/* Date:
/* 2017/7/11
/* Email:
/*
******************************************************************/
/* data_out bit domain
/* | 18 --- 14 | 13 | 12 --- 8 | 7 --- 0
/* | 0-18 | | 0-18 | 0-254
/* | parent number | 0 or 1 |number (0-9)| frequency
******************************************************************/
/*
NOTICE: 1.make sure the number of signals is less than 255 !!
2. the coding result may be different from the software,
but they generate a same huffman tree,only the coding method
is different
********************************************************************/
module freqcount(
input clk,
input rst_n,
input start, // pulse signal
input start_done, // along with the last data_in, pulse signal
input [3:0] data_in,
input ack_coding, // return signal of huffman coding module
output reg req_coding, // request signal of huffman coding module
output wire [18:0] data_out0,
output wire [18:0] data_out1,
output wire [18:0] data_out2,
output wire [18:0] data_out3,
output wire [18:0] data_out4,
output wire [18:0] data_out5,
output wire [18:0] data_out6,
output wire [18:0] data_out7,
output wire [18:0] data_out8,
output wire [18:0] data_out9
);
reg processing;
always @(posedge clk or negedge rst_n) begin
if (~rst_n)
processing <= 1'b0;
else if (start)
processing <= 1'b1;
else if (start_done)
processing <= 1'b0;
end
reg [7:0] data_mem [0:9];
integer i;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
for (i = 0; i < 10; i = i + 1) begin
data_mem[i] <= 8'b0;
end
end else if (processing) begin
case(data_in)
4'b0000: data_mem[0] <= data_mem[0] + 1;
4'b0001: data_mem[1] <= data_mem[1] + 1;
4'b0010: data_mem[2] <= data_mem[2] + 1;
4'b0011: data_mem[3] <= data_mem[3] + 1;
4'b0100: data_mem[4] <= data_mem[4] + 1;
4'b0101: data_mem[5] <= data_mem[5] + 1;
4'b0110: data_mem[6] <= data_mem[6] + 1;
4'b0111: data_mem[7] <= data_mem[7] + 1;
4'b1000: data_mem[8] <= data_mem[8] + 1;
4'b1001: data_mem[9] <= data_mem[9] + 1;
default: ;
endcase
end
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n)
req_coding <= 1'b0;
else if (start_done)
req_coding <= 1'b1;
else if (ack_coding)
req_coding <= 1'b0;
end
assign data_out0 = {6'b0, 5'd0, data_mem[0]};
assign data_out1 = {6'b0, 5'd1, data_mem[1]};
assign data_out2 = {6'b0, 5'd2, data_mem[2]};
assign data_out3 = {6'b0, 5'd3, data_mem[3]};
assign data_out4 = {6'b0, 5'd4, data_mem[4]};
assign data_out5 = {6'b0, 5'd5, data_mem[5]};
assign data_out6 = {6'b0, 5'd6, data_mem[6]};
assign data_out7 = {6'b0, 5'd7, data_mem[7]};
assign data_out8 = {6'b0, 5'd8, data_mem[8]};
assign data_out9 = {6'b0, 5'd9, data_mem[9]};
endmodule
|
#include <bits/stdc++.h> using namespace std; int Popcount(long long int a) { int k; for (k = 0; a; a >>= 1) if (a & 1ll) k++; return k; } int Ffs(long long int a) { int k; for (k = 0; a; a >>= 1, k++) ; return k; } long long int C[50][50]; long long int getAns(long long int n, long long int t) { if (n < t || t <= 0) return 0ll; long long int i; int k = 0, j = Ffs(t) - 1; for (i = 1ll; (i << 1) < n; (i <<= 1), k++) ; long long int res = getAns(n - i, t >> 1); if (k < j) return res; return C[k][j] + res; } int main() { C[0][0] = 1ll; for (int i = 1; i < 50; i++) { C[i][0] = C[i][i] = 1ll; for (int j = 1; j < i; j++) C[i][j] = C[i - 1][j - 1] + C[i - 1][j]; } long long int N, T; while (cin >> N >> T) { N++; if (Popcount(T) != 1) { puts( 0 ); continue; } long long int Ans = 0ll, x, di = 0ll; for (x = 1ll; x + di <= N; x <<= 1) { Ans += getAns(x, T); di += x; } Ans += getAns(N - di, T); if (T == 1ll) Ans--; cout << Ans << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2111AI_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__O2111AI_PP_BLACKBOX_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o2111ai (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2111AI_PP_BLACKBOX_V
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// Normal mode DFF negedge clk, negedge reset
module \$_DFF_N_ (input D, C, output Q);
parameter WYSIWYG="TRUE";
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
// Normal mode DFF
module \$_DFF_P_ (input D, C, output Q);
parameter WYSIWYG="TRUE";
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
// Async Active Low Reset DFF
module \$_DFF_PN0_ (input D, C, R, output Q);
parameter WYSIWYG="TRUE";
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
// Async Active High Reset DFF
module \$_DFF_PP0_ (input D, C, R, output Q);
parameter WYSIWYG="TRUE";
wire R_i = ~ R;
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
module \$__DFFE_PP0 (input D, C, E, R, output Q);
parameter WYSIWYG="TRUE";
wire E_i = ~ E;
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0));
endmodule
// Input buffer map
module \$__inpad (input I, output O);
cycloneive_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0));
endmodule
// Output buffer map
module \$__outpad (input I, output O);
cycloneive_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1));
endmodule
// LUT Map
/* 0 -> datac
1 -> cin */
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
end else
if (WIDTH == 2) begin
cycloneive_lcell_comb #(.lut_mask({4{LUT}}),
.sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
.dataa(A[0]),
.datab(A[1]),
.datac(1'b1),
.datad(1'b1));
end else
if(WIDTH == 3) begin
cycloneive_lcell_comb #(.lut_mask({2{LUT}}),
.sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
.dataa(A[0]),
.datab(A[1]),
.datac(A[2]),
.datad(1'b1));
end else
if(WIDTH == 4) begin
cycloneive_lcell_comb #(.lut_mask(LUT),
.sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
.dataa(A[0]),
.datab(A[1]),
.datac(A[2]),
.datad(A[3]));
end else
wire _TECHMAP_FAIL_ = 1;
endgenerate
endmodule
|
#include <bits/stdc++.h> int main() { int x, y; scanf( %d%d , &x, &y); double r = sqrt(x * x + y * y); int rmin = r; if ((double)rmin == r) { printf( black ); return 0; } if (x == 0 || y == 0) { printf( black ); return 0; } double tan = (double)y / (double)x; if (rmin % 2 == 1 && tan > 0) printf( white ); else if (rmin % 2 == 1 && tan < 0) printf( black ); else if (rmin % 2 == 0 && tan > 0) printf( black ); else if (rmin % 2 == 0 && tan < 0) printf( white ); return 0; } |
#include <bits/stdc++.h> using namespace std; void solve() { string s; cin >> s; cout << s[0]; for (int i = 1; i < s.size() - 1; i += 2) { cout << s[i]; } cout << s.back(); cout << n ; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t_; cin >> t_; while (t_--) solve(); return 0; } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_gray_rows_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_gray_rows_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_gray_rows_V_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_gray_rows_V_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__TAPVPWRVGND_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__TAPVPWRVGND_FUNCTIONAL_PP_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__tapvpwrvgnd (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__TAPVPWRVGND_FUNCTIONAL_PP_V |
`timescale 1ns / 1ps
module ov7670_top(
input clk,
output scl,
inout sda,
output ov7670_reset,
output pwdn,
output xclk,
input pclk,
input href,
input vsync,
input [7:0] data,
input M_AXIS_TREADY,
output M_AXIS_TVALID,
output M_AXIS_TLAST,
output M_AXIS_TUSER,
output [23:0] M_AXIS_TDATA);
// http://hamsterworks.co.nz/mediawiki/index.php/Zedboard_OV7670
ov7670_controller controller(.clk(clk),
.sioc(scl),
.siod(sda),
.reset(ov7670_reset),
.pwdn(pwdn),
.xclk(xclk));
OV7670_CAPTURE_AXI_VDMA_STREAM ov7670_axi(.pclk(pclk),
.href(href),
.vsync(vsync),
.data(data),
.M_AXIS_TREADY(M_AXIS_TREADY),
.M_AXIS_TVALID(M_AXIS_TVALID),
.M_AXIS_TLAST(M_AXIS_TLAST),
.M_AXIS_TUSER(M_AXIS_TUSER),
.M_AXIS_TDATA(M_AXIS_TDATA));
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Setup State Machine
// File : des_state.v
// Author : Jim MacLeod
// Created : 14-May-2011
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module des_state
(
input se_clk,
input se_rstn,
input go_sup,
input line_3d_actv_15,
input ns1_eqz,
input ns2_eqz,
input co_linear,
input det_eqz,
input cull,
output reg sup_done,
output reg abort_cmd,
output reg [5:0] se_cstate
);
`include "define_3d.h"
reg go_sup_1;
reg go_sup_2;
/*******************Setup Engine Program Counter *******************/
always @ (posedge se_clk or negedge se_rstn) begin
if (!se_rstn) begin
se_cstate <= 6'b000000;
sup_done <= 1'b0;
abort_cmd <= 1'b0;
go_sup_1 <= 1'b0;
go_sup_2 <= 1'b0;
end
else begin
go_sup_2 <= go_sup_1;
go_sup_1 <= go_sup;
abort_cmd <= 1'b0;
if((se_cstate == 6'b000000) & go_sup_2) se_cstate <= 6'b000001;
else if((se_cstate == `COLIN_STATE) & co_linear & ~line_3d_actv_15) begin
abort_cmd <= 1'b1;
se_cstate <= 6'b000000;
end
else if((se_cstate == `NL1_NL2_STATE) & (ns1_eqz & ns2_eqz & ~line_3d_actv_15)) begin
abort_cmd <= 1'b1;
se_cstate <= 6'b000000;
end
else if((se_cstate == `NO_AREA_STATE) & ((cull | det_eqz) & ~line_3d_actv_15)) begin
abort_cmd <= 1'b1;
se_cstate <= 6'b000000;
end
else if(se_cstate == 6'b000000) se_cstate <= 6'b000000;
else if((se_cstate == `SETUP_END)) se_cstate <= 6'b000000;
else se_cstate <= se_cstate + 6'b000001;
sup_done <= (se_cstate == `SETUP_END);
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long max(long long a, long long b) { return a > b ? a : b; } long long min(long long a, long long b) { return a < b ? a : b; } void fun(int arr[], int n) { stack<int> s; int left[n + 1]; int right[n + 1]; for (int i = 0; i < n; i++) { left[i] = -1; right[i] = n; } for (int i = 0; i < n; i++) { while (!s.empty() && arr[s.top()] >= arr[i]) s.pop(); if (!s.empty()) left[i] = s.top(); s.push(i); } while (!s.empty()) s.pop(); for (int i = n - 1; i >= 0; i--) { while (!s.empty() && arr[s.top()] >= arr[i]) s.pop(); if (!s.empty()) right[i] = s.top(); s.push(i); } int ans[n + 1]; for (int i = 0; i <= n; i++) ans[i] = 0; for (int i = 0; i < n; i++) { int len = right[i] - left[i] - 1; ans[len] = max(ans[len], arr[i]); } for (int i = n - 1; i >= 1; i--) ans[i] = max(ans[i], ans[i + 1]); for (int i = 1; i <= n; i++) cout << ans[i] << ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; int t, n, k; cin >> n; int arr[n]; for (int i = 0; i < n; i++) cin >> arr[i]; fun(arr, n); cout << n ; return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:40:09 05/31/2016
// Design Name:
// Module Name: Contador_AD_Year
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Contador_AD_Year(
input rst,
input [7:0]estado,
input [1:0] en,
input [7:0] Cambio,
input got_data,
input clk,
output reg [(N-1):0] Cuenta
);
parameter N = 5;
parameter X = 31;
always @(posedge clk)
if (rst)
Cuenta <= 1;
else if (en == 2'd0 && estado == 8'h7D)
begin
if (Cambio == 8'h73 && got_data)
begin
if (Cuenta == X)
Cuenta <= 1;
else
Cuenta <= Cuenta + 1'd1;
end
else if (Cambio == 8'h72 && got_data)
begin
if (Cuenta == 1)
Cuenta <= X;
else
Cuenta <= Cuenta - 1'd1;
end
else
Cuenta <= Cuenta;
end
else
Cuenta <= Cuenta;
endmodule
|
#include<bits/stdc++.h> using namespace std; typedef long long int ll; int main() { ll t,i,maxi,sumi,mini; cin>>t; while(t--) { ll n; cin>>n; ll a[n]; for(i=0;i<n;i++) cin>>a[i]; maxi=-1; mini=a[0]; sumi=0; for(i=0;i<n;i++) { sumi=sumi+a[i]; if(maxi<a[i]) maxi=a[i]; if(mini>a[i]) mini=a[i]; } mini=0; if(maxi*(n-1)>sumi) { mini+=maxi*(n-1)-sumi; sumi=maxi*(n-1); } mini+=((n-1)-sumi%(n-1))%(n-1); cout<<mini<<endl; } } |
`timescale 1 ns / 1 ps
module averager_counter #
(
parameter integer FAST_COUNT_WIDTH = 13,
parameter integer SLOW_COUNT_WIDTH = 19
)
(
input wire restart,
input wire clken,
input wire [FAST_COUNT_WIDTH-1:0] count_max,
input wire clk,
input wire avg_on,
input wire srst,
output reg ready,
output reg wen,
output reg [SLOW_COUNT_WIDTH-1:0] n_avg,
output reg [SLOW_COUNT_WIDTH-1:0] slow_count,
output reg clr_fback,
output reg avg_on_out,
output wire [FAST_COUNT_WIDTH+1:0] address
);
reg [FAST_COUNT_WIDTH-1:0] count_max_reg;
reg clken_reg, clken_reg_;
reg init_restart;
reg [FAST_COUNT_WIDTH-1:0] fast_count;
reg avg_on_out_reg0, avg_on_out_reg1;
initial begin
init_restart <= 0;
fast_count <= 0;
slow_count <= 0;
count_max_reg <= {(FAST_COUNT_WIDTH){1'b1}};
n_avg <= 0;
ready <= 1;
wen <= 0;
end
always @(posedge clk) begin
if (srst) begin
init_restart <= 0;
ready <= 1;
end else begin
if (restart && clken_reg) begin
init_restart <= 1;
ready <= 0;
end else if (fast_count == count_max_reg) begin
if (wen) begin
ready <= 1;
end else begin
if (init_restart) begin
init_restart <= 0;
end
end
end
end
end
always @(posedge clk) begin
if ((wen) && (fast_count == (count_max_reg - 2))) begin
clr_fback <= ~avg_on;
avg_on_out_reg0 <= avg_on;
avg_on_out_reg1 <= avg_on_out_reg0;
end
end
always @(posedge clk) begin
if (srst) begin
count_max_reg <= count_max;
fast_count <= 0;
slow_count <= 0;
n_avg <= 0;
end else begin
clken_reg_ <= clken;
clken_reg <= clken_reg_;
if (clken_reg) begin
if (fast_count == count_max_reg) begin
fast_count <= 0;
if (wen) begin
wen <= 0;
slow_count <= 0;
n_avg <= slow_count + 1;
avg_on_out <= avg_on_out_reg1;
end else begin
slow_count <= slow_count + 1;
if (init_restart) begin
wen <= 1;
end
end
end else begin
fast_count <= fast_count + 1;
end
end
end
end
assign address = {fast_count, 2'b0};
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e16; long long n, a[200005], p[200005], MA = 0, z = 0; int main() { scanf( %lld , &n); memset(p, 0, sizeof(p)); for (int i = 0; i < n; i++) { scanf( %lld , &a[i]); p[a[i]]++; if (p[a[i]] > MA) { MA = p[a[i]]; z = a[i]; } } printf( %lld n , n - MA); for (int i = 0; i < n - 1; i++) { if (a[i] == z) { if (a[i + 1] < a[i]) { printf( 1 %d %d n , i + 2, i + 1); a[i + 1] = z; } else if (a[i + 1] > a[i]) { printf( 2 %d %d n , i + 2, i + 1); a[i + 1] = z; } } } for (int i = n - 1; i >= 1; i--) { if (a[i] == z) { if (a[i - 1] < a[i]) { printf( 1 %d %d n , i, i + 1); a[i - 1] = z; } else if (a[i - 1] > a[i]) { printf( 2 %d %d n , i, i + 1); a[i - 1] = z; } } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int max_n = (1 << 21) + 100; vector<int> ans; int a[max_n]; void de(int i) { int l = i << 1; int r = (i << 1) | 1; if (a[l] == 0 && a[r] == 0) { a[i] = 0; return; } else { if (a[l] > a[r]) { a[i] = a[l]; de(l); } else { a[i] = a[r]; de(r); } } return; } int n, m; long long sum; int find(int i, int dep) { int l = i << 1; int r = (i << 1) | 1; if (a[l] > a[r]) { return find(l, dep + 1); } else if (a[r] > a[l]) { return find(r, dep + 1); } else { return dep; } } void dfs(int x, int dep) { if (a[x] == 0) { return; } while (find(x, dep) > m) { ans.push_back(x); sum -= a[x]; de(x); } dfs(x << 1, dep + 1); dfs((x << 1) | 1, dep + 1); } int main() { int t; int h, g; scanf( %d , &t); while (t--) { sum = 0; scanf( %d%d , &h, &m); n = (1 << h) - 1; for (int i = 1; i <= n; ++i) { scanf( %d , &a[i]); sum += a[i]; } for (int i = n + 1; i <= (1 << (h + 1)) - 1; ++i) { a[i] = 0; } dfs(1, 1); printf( %lld n , sum); for (int i = 0; i < ans.size(); ++i) { printf( %d , ans[i]); } printf( n ); ans.clear(); } return 0; } |
/* This file is part of JT51.
JT51 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT51 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT51. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 27-10-2016
*/
module jt51_sh #(parameter width=5, stages=32, rstval=1'b0 ) (
input rst,
input clk,
input cen,
input [width-1:0] din,
output [width-1:0] drop
);
reg [stages-1:0] bits[width-1:0];
genvar i;
generate
for (i=0; i < width; i=i+1) begin: bit_shifter
always @(posedge clk, posedge rst) begin
if(rst)
bits[i] <= {stages{rstval}};
else if(cen)
bits[i] <= {bits[i][stages-2:0], din[i]};
end
assign drop[i] = bits[i][stages-1];
end
endgenerate
endmodule
|
Subsets and Splits