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// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module mult_ena (
input wire CLK,
input wire ENA,
input wire [ 8:0] A,
input wire [ 8:0] B,
output wire [17:0] Z
);
reg [8:0] ra;
always @(posedge CLK)
if (ENA) ra <= A;
MULT9X9 # (
.REGINPUTA("BYPASS"),
.REGINPUTB("BYPASS"),
.REGOUTPUT("BYPASS")
) mult (
.A (ra),
.B (B),
.Z (Z)
);
endmodule
module mult_arst (
input wire CLK,
input wire RST,
input wire [ 8:0] A,
input wire [ 8:0] B,
output wire [17:0] Z
);
reg [8:0] ra;
always @(posedge CLK or posedge RST)
if (RST) ra <= 0;
else ra <= A;
MULT9X9 # (
.REGINPUTA("BYPASS"),
.REGINPUTB("BYPASS"),
.REGOUTPUT("BYPASS")
) mult (
.A (ra),
.B (B),
.Z (Z)
);
endmodule
module mult_arst_ena (
input wire CLK,
input wire RST,
input wire ENA,
input wire [ 8:0] A,
input wire [ 8:0] B,
output wire [17:0] Z
);
reg [8:0] ra;
always @(posedge CLK or posedge RST)
if (RST) ra <= 0;
else if (ENA) ra <= A;
MULT9X9 # (
.REGINPUTA("BYPASS"),
.REGINPUTB("BYPASS"),
.REGOUTPUT("BYPASS")
) mult (
.A (ra),
.B (B),
.Z (Z)
);
endmodule
module mult_srst (
input wire CLK,
input wire RST,
input wire [ 8:0] A,
input wire [ 8:0] B,
output wire [17:0] Z
);
reg [8:0] ra;
always @(posedge CLK)
if (RST) ra <= 0;
else ra <= A;
MULT9X9 # (
.REGINPUTA("BYPASS"),
.REGINPUTB("BYPASS"),
.REGOUTPUT("BYPASS")
) mult (
.A (ra),
.B (B),
.Z (Z)
);
endmodule
module mult_srst_ena (
input wire CLK,
input wire RST,
input wire ENA,
input wire [ 8:0] A,
input wire [ 8:0] B,
output wire [17:0] Z
);
reg [8:0] ra;
always @(posedge CLK)
if (RST) ra <= 0;
else if (ENA) ra <= A;
MULT9X9 # (
.REGINPUTA("BYPASS"),
.REGINPUTB("BYPASS"),
.REGOUTPUT("BYPASS")
) mult (
.A (ra),
.B (B),
.Z (Z)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[200], b[200], res[200]; int main() { int n, count, i, j, m, k, ans; cin >> n >> m >> k; for (i = 0; i < m; i++) cin >> a[i]; for (i = 0; i < k; i++) cin >> b[i]; for (i = 0; i < m; i++) { for (j = 0; j < k; j++) { if (b[j] % a[i] == 0) res[i]++; } } ans = res[0]; for (i = 0; i < m; i++) ans = min(res[i], ans); count = 0; for (i = 0; i < m; i++) if (res[i] == ans) count++; cout << count << n ; for (i = 0; i < m; i++) if (ans == res[i]) cout << i + 1 << ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, mncnt = 1000000000, cnt; string a; string c = ACTG ; cin >> n >> a; for (int i = 0; i <= n - 4; i++) { cnt = 0; string b = a.substr(i, 4); for (int j = 0; j < 4; j++) { int x = c[j] - A ; int y = b[j] - A ; if (abs(y - x) <= 13) cnt += abs(y - x); else cnt += 26 - (abs(y - x)); } mncnt = min(mncnt, cnt); } cout << mncnt << endl; } |
#include <bits/stdc++.h> using namespace std; int v[100001]; int acum[100001]; long long cnt = 0, ans[100001]; struct Q { int i, j, p; Q(int a, int b, int c) : i(a), j(b), p(c){}; Q() {} bool operator<(const Q &other) const { if (i / 300 == other.i / 300) return j < other.j; return i / 300 < other.i / 300; } }; vector<Q> queries; int freq[(1 << 20) - 1 + 1]; int main() { int n, m, k; scanf( %d %d %d , &n, &m, &k); for (int i = 1; i <= n; i++) { scanf( %d , v + i); acum[i] = v[i] ^ acum[i - 1]; } for (int k = 0; k < m; k++) { int i, j; scanf( %d %d , &i, &j); queries.push_back(Q(i - 1, j, k)); } sort(queries.begin(), queries.end()); int l = 0, r = 0; freq[0] = 1; for (int q = 0; q < m; q++) { int i = queries[q].i, j = queries[q].j, p = queries[q].p; while (l < i) { freq[acum[l]]--; cnt -= freq[acum[l] ^ k]; l++; } while (l > i) { --l; cnt += freq[acum[l] ^ k]; freq[acum[l]]++; } while (r < j) { r++; cnt += freq[acum[r] ^ k]; freq[acum[r]]++; } while (r > j) { freq[acum[r]]--; cnt -= freq[acum[r] ^ k]; r--; } ans[p] = cnt; } for (int i = 0; i < m; i++) printf( %lld n , ans[i]); return 0; } |
#include <bits/stdc++.h> using namespace std; const double EPS = 1e-9; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n; double u, v, w, x, y, l = 1e9, r = 0; cin >> n >> w >> v >> u; while (n--) { cin >> x >> y; l = min(l, x - y / u * v); r = max(r, x - y / u * v); } cout << fixed << setprecision(6) << w / u + r / v * (l < 0); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVERNOVLPSLEEP_FUNCTIONAL_V
`define SKY130_FD_SC_LP__BUSDRIVERNOVLPSLEEP_FUNCTIONAL_V
/**
* busdrivernovlpsleep: Bus driver, enable gates pulldown only,
* non-inverted sleep input (on kapwr rail).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__busdrivernovlpsleep (
Z ,
A ,
TE_B ,
SLEEP
);
// Module ports
output Z ;
input A ;
input TE_B ;
input SLEEP;
// Local signals
wire nor_teb_SLEEP;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVERNOVLPSLEEP_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__INV_8_V
`define SKY130_FD_SC_MS__INV_8_V
/**
* inv: Inverter.
*
* Verilog wrapper for inv with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__inv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__inv_8 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__inv_8 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__inv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__INV_8_V
|
#include <bits/stdc++.h> using namespace std; int n, m, k; int a[111][111][111]; int color[111][111][111], cc; char second[111]; void visit(queue<pair<pair<int, int>, int> >* q, int x, int y, int z) { if (a[x][y][z] == 1 && color[x][y][z] != cc) { color[x][y][z] = cc; q->push(make_pair(make_pair(x, y), z)); } } void go(int x, int y, int z, int mx, int my, int mz) { assert(a[x][y][z] == 1); if (mx > n) mx = n; if (my > m) my = m; if (mz > k) mz = k; ++cc; queue<pair<pair<int, int>, int> > q; color[x][y][z] = cc; q.push(make_pair(make_pair(x, y), z)); while (!q.empty()) { pair<pair<int, int>, int> fr = q.front(); q.pop(); int x = fr.first.first; int y = fr.first.second; int z = fr.second; if (x + 1 <= mx) visit(&q, x + 1, y, z); if (y + 1 <= my) visit(&q, x, y + 1, z); if (z + 1 <= mz) visit(&q, x, y, z + 1); } } bool reachable(int x, int y, int z) { if (x + 1 < n && a[x + 1][y][z] == 1 && color[x + 1][y][z] != cc) { return false; } if (y + 1 < m && a[x][y + 1][z] == 1 && color[x][y + 1][z] != cc) { return false; } if (z + 1 < k && a[x][y][z + 1] == 1 && color[x][y][z + 1] != cc) { return false; } return true; } bool critical(int x, int y, int z) { if (x > 0 && a[x - 1][y][z] == 1) { go(x - 1, y, z, x + 1, y + 1, z + 1); if (!reachable(x, y, z)) { return true; } } if (y > 0 && a[x][y - 1][z] == 1) { go(x, y - 1, z, x + 1, y + 1, z + 1); if (!reachable(x, y, z)) { return true; } } if (z > 0 && a[x][y][z - 1] == 1) { go(x, y, z - 1, x + 1, y + 1, z + 1); if (!reachable(x, y, z)) { return true; } } return false; } int main() { scanf( %d%d%d , &n, &m, &k); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { scanf( %s , second); for (int t = 0; t < k; t++) { a[i][j][t] = (second[t] == 1 ); } } } int res = 0; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { for (int t = 0; t < k; t++) { if (a[i][j][t] == 1) { a[i][j][t] = 0; res += critical(i, j, t); a[i][j][t] = 1; } } } } printf( %d n , res); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, q; const long long N = 2e5 + 100; vector<long long> v[N]; long long dfn[N], num[N], val[N], sz[N], hs[N], tp[N], dep[N], f[N]; inline void dfs(long long x, long long fa) { sz[x] = 1; long long num = 0; dep[x] = dep[fa] + 1; f[x] = fa; for (auto y : v[x]) { if (y == fa) continue; dfs(y, x); sz[x] += sz[y]; if (num < sz[y]) hs[x] = y, num = sz[y]; } } long long cnt; inline void redfs(long long x, long long fa, long long top) { tp[x] = top; dfn[x] = ++cnt; num[cnt] = x; if (hs[x]) redfs(hs[x], x, top); for (auto y : v[x]) { if (y == fa || y == hs[x]) continue; redfs(y, x, y); } } struct seg { long long l, r, v; } t[N << 2]; long long a[N]; inline void build(long long p, long long l, long long r) { t[p].l = l, t[p].r = r; if (l == r) { t[p].v = abs(val[num[l]]); return; } long long mid = l + r >> 1; build(p << 1, l, mid), build(p << 1 | 1, mid + 1, r); t[p].v = t[p << 1].v + t[p << 1 | 1].v; } inline void modify(long long p, long long x, long long v) { if (t[p].l == t[p].r) { t[p].v = v; return; } long long mid = t[p].l + t[p].r >> 1; if (x <= mid) modify(p << 1, x, v); else modify(p << 1 | 1, x, v); t[p].v = t[p << 1].v + t[p << 1 | 1].v; } inline long long query(long long p, long long x, long long y) { if (x <= t[p].l && t[p].r <= y) { return t[p].v; } long long mid = t[p].l + t[p].r >> 1; if (y <= mid) return query(p << 1, x, y); if (x > mid) return query(p << 1 | 1, x, y); return query(p << 1, x, y) + query(p << 1 | 1, x, y); } signed main() { ios::sync_with_stdio(false); cin >> n >> q; for (long long i = 1; i <= n; i++) cin >> val[i], val[i] = abs(val[i]); for (long long i = 1; i <= n - 1; i++) { long long x, y; cin >> x >> y; v[x].push_back(y), v[y].push_back(x); } dfs(1, 0); redfs(1, 0, 1); build(1, 1, n); for (long long i = 1; i <= q; i++) { long long opt, x, y; cin >> opt >> x >> y; if (opt == 1) { modify(1, dfn[x], abs(y)); val[x] = abs(y); } else { long long ans = 0, X = x, Y = y; ; while (tp[x] != tp[y]) { if (dep[tp[x]] < dep[tp[y]]) swap(x, y); ans += query(1, dfn[tp[x]], dfn[x]); x = f[tp[x]]; } if (dep[x] < dep[y]) swap(x, y); ans += query(1, dfn[y], dfn[x]); cout << ans * 2 - val[X] - val[Y] << n ; } } } |
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/14.1/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_handshake_clock_crosser.v $
// $Revision: #1 $
// $Date: 2014/10/06 $
// $Author: swbranch $
//------------------------------------------------------------------------------
// Clock crosser module with handshaking mechanism
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_handshake_clock_crosser
#(
parameter DATA_WIDTH = 8,
BITS_PER_SYMBOL = 8,
USE_PACKETS = 0,
// ------------------------------
// Optional signal widths
// ------------------------------
USE_CHANNEL = 0,
CHANNEL_WIDTH = 1,
USE_ERROR = 0,
ERROR_WIDTH = 1,
VALID_SYNC_DEPTH = 2,
READY_SYNC_DEPTH = 2,
USE_OUTPUT_PIPELINE = 1,
// ------------------------------
// Derived parameters
// ------------------------------
SYMBOLS_PER_BEAT = DATA_WIDTH / BITS_PER_SYMBOL,
EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
input in_clk,
input in_reset,
input out_clk,
input out_reset,
output in_ready,
input in_valid,
input [DATA_WIDTH - 1 : 0] in_data,
input [CHANNEL_WIDTH - 1 : 0] in_channel,
input [ERROR_WIDTH - 1 : 0] in_error,
input in_startofpacket,
input in_endofpacket,
input [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] in_empty,
input out_ready,
output out_valid,
output [DATA_WIDTH - 1 : 0] out_data,
output [CHANNEL_WIDTH - 1 : 0] out_channel,
output [ERROR_WIDTH - 1 : 0] out_error,
output out_startofpacket,
output out_endofpacket,
output [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] out_empty
);
// ------------------------------
// Payload-specific widths
// ------------------------------
localparam PACKET_WIDTH = (USE_PACKETS) ? 2 + EMPTY_WIDTH : 0;
localparam PCHANNEL_W = (USE_CHANNEL) ? CHANNEL_WIDTH : 0;
localparam PERROR_W = (USE_ERROR) ? ERROR_WIDTH : 0;
localparam PAYLOAD_WIDTH = DATA_WIDTH +
PACKET_WIDTH +
PCHANNEL_W +
EMPTY_WIDTH +
PERROR_W;
wire [PAYLOAD_WIDTH - 1: 0] in_payload;
wire [PAYLOAD_WIDTH - 1: 0] out_payload;
// ------------------------------
// Assign in_data and other optional sink interface
// signals to in_payload.
// ------------------------------
assign in_payload[DATA_WIDTH - 1 : 0] = in_data;
generate
// optional packet inputs
if (PACKET_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH - 1 :
DATA_WIDTH
] = {in_startofpacket, in_endofpacket};
end
// optional channel input
if (USE_CHANNEL) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W - 1 :
DATA_WIDTH + PACKET_WIDTH
] = in_channel;
end
// optional empty input
if (EMPTY_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W
] = in_empty;
end
// optional error input
if (USE_ERROR) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH + PERROR_W - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH
] = in_error;
end
endgenerate
// --------------------------------------------------
// Pipe the input payload to our inner module which handles the
// actual clock crossing
// --------------------------------------------------
altera_avalon_st_clock_crosser
#(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (PAYLOAD_WIDTH),
.FORWARD_SYNC_DEPTH (VALID_SYNC_DEPTH),
.BACKWARD_SYNC_DEPTH (READY_SYNC_DEPTH),
.USE_OUTPUT_PIPELINE (USE_OUTPUT_PIPELINE)
) clock_xer (
.in_clk (in_clk ),
.in_reset (in_reset ),
.in_ready (in_ready ),
.in_valid (in_valid ),
.in_data (in_payload ),
.out_clk (out_clk ),
.out_reset (out_reset ),
.out_ready (out_ready ),
.out_valid (out_valid ),
.out_data (out_payload )
);
// --------------------------------------------------
// Split out_payload into the output signals.
// --------------------------------------------------
assign out_data = out_payload[DATA_WIDTH - 1 : 0];
generate
// optional packet outputs
if (USE_PACKETS) begin
assign {out_startofpacket, out_endofpacket} =
out_payload[DATA_WIDTH + PACKET_WIDTH - 1 : DATA_WIDTH];
end else begin
// avoid a "has no driver" warning.
assign {out_startofpacket, out_endofpacket} = 2'b0;
end
// optional channel output
if (USE_CHANNEL) begin
assign out_channel = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W - 1 :
DATA_WIDTH + PACKET_WIDTH
];
end else begin
// avoid a "has no driver" warning.
assign out_channel = 1'b0;
end
// optional empty output
if (EMPTY_WIDTH) begin
assign out_empty = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W
];
end else begin
// avoid a "has no driver" warning.
assign out_empty = 1'b0;
end
// optional error output
if (USE_ERROR) begin
assign out_error = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH + PERROR_W - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH
];
end else begin
// avoid a "has no driver" warning.
assign out_error = 1'b0;
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value.
// --------------------------------------------------
function integer log2ceil;
input integer val;
integer i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, x, y; cin >> n >> m; vector<int> deg(n, 0), uf(n), uf_cnt(n, 1); for (int i = 0; i < n; ++i) uf[i] = i; for (int i = 0; i < m; ++i) { cin >> x >> y; deg[--x]++; deg[--y]++; while (x != uf[x]) x = uf[x]; while (y != uf[y]) y = uf[y]; if (x < y) { uf_cnt[x] += uf_cnt[y]; uf_cnt[y] = 0; uf[y] = x; } if (y < x) { uf_cnt[y] += uf_cnt[x]; uf_cnt[x] = 0; uf[x] = y; } } for (int i = 0; i < n; ++i) { int j = i; while (j != uf[j]) j = uf[j]; if (deg[i] + 1 != uf_cnt[j]) { cout << NO n ; return 0; } } cout << YES n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 4005; int f[maxn][maxn], prea[maxn][26], preb[maxn][26]; char a[maxn], b[maxn]; int n, m, ti, td, tr, te; int main() { int i, j, x, y; scanf( %d%d%d%d , &ti, &td, &tr, &te); scanf( %s%s , a + 1, b + 1); n = strlen(a + 1); m = strlen(b + 1); for (i = 1; i <= n; ++i) { memcpy(prea[i], prea[i - 1], sizeof prea[0]); prea[i][a[i] - a ] = i; f[i][0] = i * td; } for (i = 1; i <= m; ++i) { memcpy(preb[i], preb[i - 1], sizeof preb[0]); preb[i][b[i] - a ] = i; f[0][i] = i * ti; } for (i = 1; i <= n; ++i) for (j = 1; j <= m; ++j) { f[i][j] = min(f[i - 1][j] + td, f[i][j - 1] + ti); f[i][j] = min(f[i][j], f[i - 1][j - 1] + (a[i] != b[j] ? tr : 0)); x = prea[i - 1][b[j] - a ]; y = preb[j - 1][a[i] - a ]; if (x && y) f[i][j] = min(f[i][j], f[x - 1][y - 1] + te + (i - x - 1) * td + (j - y - 1) * ti); } printf( %d n , f[n][m]); return 0; } |
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { return b == 0 ? a : gcd(b, a % b); } const int MAXN = 2500; struct P { int x, y; P() {} P(int x, int y) : x(x), y(y) {} }; long long operator^(const P& a, const P& b) { return (long long)a.x * b.y - (long long)a.y * b.x; } P operator-(const P& a, const P& b) { return P(a.x - b.x, a.y - b.y); } bool operator<(const P& a, const P& b) { bool apos = a.y > 0 || a.y == 0 && a.x > 0; bool bpos = b.y > 0 || b.y == 0 && b.x > 0; if (apos != bpos) return apos; return (a ^ b) > 0; } int n; P p[MAXN]; long long C[MAXN + 1][5 + 1]; P q[2 * (MAXN - 1)]; int nq; long long solve() { for (int i = (0); i <= (n); ++i) for (int j = (0); j <= (5); ++j) C[i][j] = 0; for (int i = (0); i <= (n); ++i) { C[i][0] = 1; for (int j = (1); j <= (min(5, i)); ++j) C[i][j] = C[i - 1][j - 1] + C[i - 1][j]; } long long cnttot = C[n][5]; long long cntside = 0; for (int i = (0); i < (n); ++i) { nq = 0; for (int j = (0); j < (n); ++j) if (j != i) q[nq++] = p[j] - p[i]; sort(q, q + nq); for (int j = (0); j < (nq); ++j) q[nq + j] = q[j]; int to = 0; for (int at = (0); at < (nq); ++at) { to = max(to, at + 1); while (to - at < nq && (q[at] ^ q[to]) > 0) ++to; int cur = to - at - 1; cntside += C[cur][3]; } } return 5 * cnttot - cntside; } void run() { scanf( %d , &n); for (int i = (0); i < (n); ++i) scanf( %d%d , &p[i].x, &p[i].y); printf( %lld n , solve()); } int main() { run(); return 0; } |
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module splitter #(
parameter NUM_M = 2)(
input clk,
input resetn,
input s_valid,
output s_ready,
output [NUM_M-1:0] m_valid,
input [NUM_M-1:0] m_ready
);
reg [NUM_M-1:0] acked;
assign s_ready = &(m_ready | acked);
assign m_valid = s_valid ? ~acked : {NUM_M{1'b0}};
always @(posedge clk)
begin
if (resetn == 1'b0) begin
acked <= {NUM_M{1'b0}};
end else begin
if (s_valid & s_ready)
acked <= {NUM_M{1'b0}};
else
acked <= acked | (m_ready & m_valid);
end
end
endmodule
|
#include <bits/stdc++.h> int read() { int x = 0, c = getchar(); while (!isdigit(c)) c = getchar(); while (isdigit(c)) x = x * 10 + c - 0 , c = getchar(); return x; } const int maxn = 205, mod = 1000000009; std::vector<int> G[maxn]; int ins[maxn]; int stack[maxn], sp; int dfn[maxn], low[maxn], ip; int bl[maxn], bsz[maxn], bp; bool blin[maxn][maxn]; void dfs(int u, int fa) { low[u] = dfn[u] = ++ip; stack[++sp] = u; ins[u] = 1; for (size_t i = 0, sz = G[u].size(); i < sz; i++) { int v = G[u][i]; if (v == fa) continue; if (!dfn[v]) { dfs(v, u); low[u] = std::min(low[u], low[v]); } else if (ins[v]) low[u] = std::min(low[u], dfn[v]); } if (low[u] == dfn[u]) { ++bp; while (stack[sp + 1] != u) { int x = stack[sp--]; ins[x] = 0; ++bsz[bp]; bl[x] = bp; } } } bool vis[maxn]; int key[maxn]; std::vector<int> T[maxn]; void get(int u, int fa) { bool ok = bsz[u] == 1; for (int v = 1; v <= bp; v++) if (blin[u][v] and v != fa and v != u) { get(v, u); ok &= key[v] == 1; } if (ok) { key[u] = 1; for (int v = 1; v <= bp; v++) if (blin[u][v] and v != fa) { key[v] = -1; T[u].push_back(v); } } else key[u] = -1; } long long C[maxn][maxn]; long long f[maxn][maxn], g[maxn][maxn], h[maxn][maxn]; long long ans[maxn], tmp[maxn]; int size[maxn]; void dp1(int u) { size[u] = 1; f[u][0] = 1; for (size_t i = 0, sz = T[u].size(); i < sz; i++) { int v = T[u][i]; dp1(v); for (int i = size[u]; i >= 0; i--) for (int j = 1; j <= size[v]; j++) (f[u][i + j] += f[u][i] * f[v][j] % mod * C[i + j][i]) %= mod; size[u] += size[v]; } f[u][size[u]] = f[u][size[u] - 1]; } void dp2(int u, int n) { for (int i = 0; i < size[u]; i++) for (int j = 0; j <= n - size[u]; j++) (h[u][i + j] += f[u][i] * g[u][j] % mod * C[i + j][i]) %= mod; for (size_t i = 0, sz = T[u].size(); i < sz; i++) { int v = T[u][i]; for (int i = 0; i < n; i++) g[v][i] = h[u][i]; for (int i = 0; i < n - size[v]; i++) for (int j = 1; j <= size[v]; j++) (g[v][i + j] += (mod - g[v][i]) * f[v][j] % mod * C[i + j][i]) %= mod; g[v][n - size[v]] = g[v][n - size[v] - 1]; dp2(v, n); } for (int i = 0; i <= n - size[u]; i++) (tmp[size[u] + i] += f[u][size[u] - 1] * g[u][i] % mod * C[size[u] - 1 + i][i]) %= mod; for (size_t i = 0, sz = T[u].size(); i < sz; i++) { int v = T[u][i]; for (int i = 0; i < size[v]; i++) (tmp[n - size[v] + i] += g[v][n - size[v] - 1] * f[v][i] % mod * C[n - size[v] - 1 + i][i]) %= mod; } } int main() { int n = read(), m = read(); for (int i = 1; i <= m; i++) { int u = read(), v = read(); G[u].push_back(v); G[v].push_back(u); } for (int u = 1; u <= n; u++) if (!dfn[u]) dfs(u, 0); for (int u = 1; u <= n; u++) for (size_t i = 0, sz = G[u].size(); i < sz; i++) blin[bl[u]][bl[G[u][i]]] = 1; for (int i = 0; i <= n; i++) { C[i][0] = 1; for (int j = 1; j <= i; j++) C[i][j] = (C[i - 1][j] + C[i - 1][j - 1]) % mod; } ans[0] = 1; for (int i = 1; i <= bp; i++) if (!key[i] and bsz[i] > 1) get(i, 0); for (int u = 1; u <= bp; u++) if (key[u] == 1) { key[u] = -1; dp1(u); for (int i = n; i >= 0; i--) for (int j = 1; j <= size[u]; j++) (ans[i + j] += ans[i] * f[u][j] % mod * C[i + j][i]) %= mod; } for (int i = 1; i <= bp; i++) if (!key[i] and bsz[i] == 1) get(i, 0); for (int u = 1; u <= bp; u++) if (key[u] == 1) { key[u] = -1; dp1(u); g[u][0] = 1; tmp[0] = 1; for (int i = 1; i <= size[u]; i++) tmp[i] = 0; dp2(u, size[u]); for (int i = n; i >= 0; i--) for (int j = 1; j <= size[u]; j++) (ans[i + j] += ans[i] * tmp[j] % mod * C[i + j][i]) %= mod; } for (int i = 0; i <= n; i++) printf( %lld n , ans[i]); } |
#include <bits/stdc++.h> using namespace std; int main() { int n, a, odd = 0, even = 0; cin >> n; while (n--) { cin >> a; if (a % 2 == 0) { even += 1; } else { odd += 1; } } cout << (odd % 2 == 1 ? odd : even) << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A311OI_SYMBOL_V
`define SKY130_FD_SC_LP__A311OI_SYMBOL_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a311oi (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
input C1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A311OI_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; long long int dp[(1ll << 19)][19]; long long int n, T; long long int t[19], g[19]; long long int ans = 0; long long int solve(long long int mask, long long int cnt, long long int last) { if (cnt > T) return 0; if (cnt == T) return 1; if (dp[mask][last] != -1) return dp[mask][last]; long long int res = 0; for (long long int i = 0; i < n; i++) { if ((mask & (1 << i)) == 0 && g[i] != last) { res += solve(mask | (1 << i), cnt + t[i], g[i]); res %= 1000000007; } } return dp[mask][last] = res; } int32_t main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); memset(dp, -1, sizeof dp); cin >> n >> T; long long int i; for (i = 0; i < n; i++) { cin >> t[i] >> g[i]; } ans = solve(0, 0, 0); cout << ans; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m, c, e; char s[100]; scanf( %d%d%*d.%d , &n, &m, &c); map<string, int> u; for (int i = 0; i < n; i++) { scanf( %s%d , s, &e); if (e * c / 100 >= 100) u[s] = e * c / 100; } for (int i = 0; i < m; i++) { scanf( %s , s); u[s]; } printf( %d n , int(u.size())); for (auto& x : u) printf( %s %d n , x.first.c_str(), x.second); } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND3B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__NAND3B_BEHAVIORAL_PP_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nand3b (
VPWR,
VGND,
Y ,
A_N ,
B ,
C
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A_N ;
input B ;
input C ;
// Local signals
wire not0_out ;
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y , B, not0_out, C );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND3B_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> const int maxn = 100001; int n, a[maxn]; struct Segment { int val, tag; } seg[maxn << 1 | 1]; inline int seg_idx(int L, int R) { return (L + R) | (L < R); } void seg_down(int rt, int lch, int rch) { if (!seg[rt].tag) return; seg[lch].val += seg[rt].tag; seg[lch].tag += seg[rt].tag; seg[rch].val += seg[rt].tag; seg[rch].tag += seg[rt].tag; seg[rt].tag = 0; } void seg_up(int rt, int lch, int rch) { seg[rt].val = std::max(seg[lch].val, seg[rch].val); } void seg_upd(int L, int R, int x, int v) { int rt = seg_idx(L, R); if (R <= x) { seg[rt].val += v; seg[rt].tag += v; return; } int M = (L + R) >> 1, lch = seg_idx(L, M), rch = seg_idx(M + 1, R); seg_down(rt, lch, rch); seg_upd(L, M, x, v); if (x > M) seg_upd(M + 1, R, x, v); seg_up(rt, lch, rch); } int seg_que(int L, int R) { int rt = seg_idx(L, R); if (L == R) return L; int M = (L + R) >> 1, lch = seg_idx(L, M), rch = seg_idx(M + 1, R), ret; seg_down(rt, lch, rch); ret = seg[rch].val <= 0 ? seg_que(L, M) : seg_que(M + 1, R); seg_up(rt, lch, rch); return ret; } int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) { int pos, typ; scanf( %d%d , &pos, &typ); if (typ == 1) { scanf( %d , a + pos); seg_upd(1, n, pos, 1); } else seg_upd(1, n, pos, -1); if (seg[seg_idx(1, n)].val <= 0) puts( -1 ); else printf( %d n , a[seg_que(1, n)]); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int t, n, i; string a, b; cin >> t; while (t--) { vector<int> k; cin >> n >> a >> b; for (i = 0; i < n; i++) { if (a[i] != b[i]) { k.push_back(i + 1); k.push_back(1); k.push_back(i + 1); } } cout << k.size() << ; for (auto x : k) cout << x << ; } } |
#include <bits/stdc++.h> using namespace std; int main() { long long N; cin >> N; cout << 3 * (N - 2) - 2 + (N - 4) * (N - 3) << endl; return 0; } |
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module controls VGA output for Altera's DE1 and DE2 Boards. *
* *
******************************************************************************/
module video_sys_VGA_Controller (
// Inputs
clk,
reset,
data,
startofpacket,
endofpacket,
empty,
valid,
// Bidirectionals
// Outputs
ready,
VGA_CLK,
VGA_BLANK,
VGA_SYNC,
VGA_HS,
VGA_VS,
VGA_R,
VGA_G,
VGA_B
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 9;
parameter DW = 29;
parameter R_UI = 29;
parameter R_LI = 20;
parameter G_UI = 19;
parameter G_LI = 10;
parameter B_UI = 9;
parameter B_LI = 0;
/* Number of pixels */
parameter H_ACTIVE = 640;
parameter H_FRONT_PORCH = 16;
parameter H_SYNC = 96;
parameter H_BACK_PORCH = 48;
parameter H_TOTAL = 800;
/* Number of lines */
parameter V_ACTIVE = 480;
parameter V_FRONT_PORCH = 10;
parameter V_SYNC = 2;
parameter V_BACK_PORCH = 33;
parameter V_TOTAL = 525;
parameter LW = 10;
parameter LINE_COUNTER_INCREMENT = 10'h001;
parameter PW = 10;
parameter PIXEL_COUNTER_INCREMENT = 10'h001;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] data;
input startofpacket;
input endofpacket;
input [ 1: 0] empty;
input valid;
// Bidirectionals
// Outputs
output ready;
output VGA_CLK;
output reg VGA_BLANK;
output reg VGA_SYNC;
output reg VGA_HS;
output reg VGA_VS;
output reg [CW: 0] VGA_R;
output reg [CW: 0] VGA_G;
output reg [CW: 0] VGA_B;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// States
localparam STATE_0_SYNC_FRAME = 1'b0,
STATE_1_DISPLAY = 1'b1;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire read_enable;
wire end_of_active_frame;
wire vga_blank_sync;
wire vga_c_sync;
wire vga_h_sync;
wire vga_v_sync;
wire vga_data_enable;
wire [CW: 0] vga_red;
wire [CW: 0] vga_green;
wire [CW: 0] vga_blue;
wire [CW: 0] vga_color_data;
// Internal Registers
reg [ 3: 0] color_select; // Use for the TRDB_LCM
// State Machine Registers
reg ns_mode;
reg s_mode;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk) // sync reset
begin
if (reset == 1'b1)
s_mode <= STATE_0_SYNC_FRAME;
else
s_mode <= ns_mode;
end
always @(*)
begin
// Defaults
ns_mode = STATE_0_SYNC_FRAME;
case (s_mode)
STATE_0_SYNC_FRAME:
begin
if (valid & startofpacket)
ns_mode = STATE_1_DISPLAY;
else
ns_mode = STATE_0_SYNC_FRAME;
end
STATE_1_DISPLAY:
begin
if (end_of_active_frame)
ns_mode = STATE_0_SYNC_FRAME;
else
ns_mode = STATE_1_DISPLAY;
end
default:
begin
ns_mode = STATE_0_SYNC_FRAME;
end
endcase
end
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
VGA_BLANK <= vga_blank_sync;
VGA_SYNC <= 1'b0;
VGA_HS <= vga_h_sync;
VGA_VS <= vga_v_sync;
VGA_R <= vga_red;
VGA_G <= vga_green;
VGA_B <= vga_blue;
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
color_select <= 4'h1;
else if (s_mode == STATE_0_SYNC_FRAME)
color_select <= 4'h1;
else if (~read_enable)
color_select <= {color_select[2:0], color_select[3]};
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign ready =
(s_mode == STATE_0_SYNC_FRAME) ?
valid & ~startofpacket :
read_enable;
assign VGA_CLK = ~clk;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_avalon_video_vga_timing VGA_Timing (
// Inputs
.clk (clk),
.reset (reset),
.red_to_vga_display (data[R_UI:R_LI]),
.green_to_vga_display (data[G_UI:G_LI]),
.blue_to_vga_display (data[B_UI:B_LI]),
.color_select (color_select),
// .data_valid (1'b1),
// Bidirectionals
// Outputs
.read_enable (read_enable),
.end_of_active_frame (end_of_active_frame),
.end_of_frame (), // (end_of_frame),
// dac pins
.vga_blank (vga_blank_sync),
.vga_c_sync (vga_c_sync),
.vga_h_sync (vga_h_sync),
.vga_v_sync (vga_v_sync),
.vga_data_enable (vga_data_enable),
.vga_red (vga_red),
.vga_green (vga_green),
.vga_blue (vga_blue),
.vga_color_data (vga_color_data)
);
defparam
VGA_Timing.CW = CW,
VGA_Timing.H_ACTIVE = H_ACTIVE,
VGA_Timing.H_FRONT_PORCH = H_FRONT_PORCH,
VGA_Timing.H_SYNC = H_SYNC,
VGA_Timing.H_BACK_PORCH = H_BACK_PORCH,
VGA_Timing.H_TOTAL = H_TOTAL,
VGA_Timing.V_ACTIVE = V_ACTIVE,
VGA_Timing.V_FRONT_PORCH = V_FRONT_PORCH,
VGA_Timing.V_SYNC = V_SYNC,
VGA_Timing.V_BACK_PORCH = V_BACK_PORCH,
VGA_Timing.V_TOTAL = V_TOTAL,
VGA_Timing.LW = LW,
VGA_Timing.LINE_COUNTER_INCREMENT = LINE_COUNTER_INCREMENT,
VGA_Timing.PW = PW,
VGA_Timing.PIXEL_COUNTER_INCREMENT = PIXEL_COUNTER_INCREMENT;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, i, k, u, v, cnt; int head[300005], a[300005]; long long f[300005], ans; struct ff { int to, nxt; } e[2 * 300005]; int fast() { int res = 0, fl = 1; char c = getchar(); while (c < 48 || c > 57) { if (c == - ) fl = -1; c = getchar(); } while (c >= 48 && c <= 57) res = res * 10 + c - 48, c = getchar(); return res * fl; } void write(long long x) { if (x > 9) write(x / 10); putchar(x % 10 + 48); } void add(int u, int v) { e[++cnt] = (ff){v, head[u]}; head[u] = cnt; } void dfs(int now, int fa, int fl) { f[now] = a[now]; for (int i = head[now]; i; i = e[i].nxt) { int v = e[i].to; if (v == fa) continue; dfs(v, now, fl); if (f[v] > 0) f[now] += f[v]; } if (fl) ans = max(ans, f[now]); else if (ans == f[now]) k++, f[now] = -1; } int main() { n = fast(); for (i = 1; i <= n; i++) a[i] = fast(); for (i = 1; i < n; i++) { u = fast(), v = fast(); add(u, v), add(v, u); } ans = -(long long)1e16; dfs(1, 0, 1); dfs(1, 0, 0); printf( %lld %d n , ans * k, k); return 0; } |
#include <bits/stdc++.h> using namespace std; using namespace std; const int N = 3e6 + 5; int a[55][55], b[55][55], aa[55][55], bb[55][55]; int row(int x, int y) { for (int i = 1; i <= x; i++) { int k = 1; for (int j = 2; j <= y; j++) { if (a[i][j] > a[i][k]) { k = j; } else return 0; } } for (int i = 1; i <= x; i++) { int k = 1; for (int j = 2; j <= y; j++) { if (b[i][j] > b[i][k]) { k = j; } else return 0; } } return 1; } int col(int x, int y) { for (int i = 1; i <= y; i++) { int k = 1; for (int j = 2; j <= x; j++) { if (a[j][i] > a[k][i]) { k = j; } else return 0; } } for (int i = 1; i <= y; i++) { int k = 1; for (int j = 2; j <= x; j++) { if (b[j][i] > b[k][i]) { k = j; } else return 0; } } return 1; } int main() { int n, m; cin >> n >> m; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { cin >> aa[i][j]; } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { cin >> bb[i][j]; } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { a[i][j] = min(aa[i][j], bb[i][j]); b[i][j] = max(aa[i][j], bb[i][j]); } } if (row(n, m) && col(n, m)) cout << Possible ; else cout << Impossible ; return 0; } |
#include <bits/stdc++.h> int main() { int num = 0; int a[100]; int i = 0; int m = 0; int yushu; char hex[16] = { 0 , 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 , A , B , C , D , E , F }; scanf( %d , &num); if (num == 0) { printf( 1 n ); return 0; } while (num > 0) { yushu = num % 16; a[i++] = yushu; num = num / 16; } int output = 0; for (i = i - 1; i >= 0; i--) { m = a[i]; if (hex[m] == 0 ) output++; if (hex[m] == 4 ) output++; if (hex[m] == 6 ) output++; if (hex[m] == 8 ) output += 2; if (hex[m] == 9 ) output++; if (hex[m] == A ) output++; if (hex[m] == B ) output += 2; if (hex[m] == D ) output++; } printf( %d n , output); } |
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; const int RLEN = 1 << 20 | 1; inline char gc() { static char ibuf[RLEN], *ib, *ob; (ob == ib) && (ob = (ib = ibuf) + fread(ibuf, 1, RLEN, stdin)); return (ob == ib) ? EOF : *ib++; } inline int read() { char ch = getchar(); int res = 0, f = 1; while (!isdigit(ch)) f ^= ch == - , ch = getchar(); while (isdigit(ch)) res = (res + (res << 2) << 1) + (ch ^ 48), ch = getchar(); return f ? res : -res; } inline void chemx(int &a, int b) { a < b ? a = b : 0; } inline void chemn(int &a, int b) { a > b ? a = b : 0; } struct node { int s, m, r, t; node(int _s = 0, int _m = 0, int _r = 0, int _t = 0) : s(_s), m(_m), r(_r), t(_t) {} friend inline bool operator<(const node &a, const node &b) { return a.t < b.t; } friend inline bool operator==(const node &a, const node &b) { return a.t == b.t; } friend inline bool operator>(const node &a, const node &b) { return a.t > b.t; } friend inline bool operator<=(const node &a, const node &b) { return a.t <= b.t; } friend inline bool operator>=(const node &a, const node &b) { return a.t >= b.t; } friend inline bool operator!=(const node &a, const node &b) { return a.t != b.t; } }; const int N = 100005, inf = 2e9; node a[N]; int n, q; struct Tr { vector<node> v; vector<long long> sl, sr; int last; inline void init(int l, int r) { int len = r - l + 1; for (int i = l; i <= r; i++) v.push_back(a[i]); sort(v.begin(), v.end()); sl.resize(len), sr.resize(len); sl[0] = v[0].m, sr[len - 1] = v[len - 1].r; for (int i = 1; i < len; i++) sl[i] = sl[i - 1] + v[i].m; for (int i = len - 2; ~i; i--) sr[i] = sr[i + 1] + v[i].r; } inline long long query(int t) { int tim = t - last; int pos = lower_bound(v.begin(), v.end(), node(0, 0, 0, tim)) - v.begin() - 1; long long res = 0; if (~pos) res += sl[pos]; if (pos + 1 < (int)v.size()) res += sr[pos + 1] * tim; last = t; return res; } }; namespace Seg { Tr tr[N << 2]; void build(int u, int l, int r) { tr[u].last = -2, tr[u].init(l, r); if (l == r) return; build((u << 1), l, ((l + r) >> 1)), build(((u << 1) | 1), ((l + r) >> 1) + 1, r); } inline void pushup(int u) { if (tr[(u << 1)].last == tr[((u << 1) | 1)].last) if (tr[(u << 1)].last >= 0) { tr[u].last = tr[(u << 1)].last; return; } else if (tr[(u << 1)].last == -2) { tr[u].last = -2; return; } tr[u].last = -1; } inline void pushdown(int u) { if (tr[u].last >= 0) tr[(u << 1)].last = tr[((u << 1) | 1)].last = tr[u].last; } long long query(int u, int l, int r, int st, int des, int k) { if (l == r && tr[u].last == -2) { tr[u].last = k; return min(1ll * a[l].m, 1ll * a[l].s + 1ll * a[l].r * k); } if (st <= l && r <= des && tr[u].last >= 0) return tr[u].query(k); long long res = 0; pushdown(u); if (st <= ((l + r) >> 1)) res += query((u << 1), l, ((l + r) >> 1), st, des, k); if (((l + r) >> 1) < des) res += query(((u << 1) | 1), ((l + r) >> 1) + 1, r, st, des, k); pushup(u); return res; } } // namespace Seg int main() { n = read(); for (int i = 1; i <= n; i++) { a[i].s = read(), a[i].m = read(), a[i].r = read(), a[i].t = a[i].r == 0 ? inf : a[i].m / a[i].r; } Seg::build(1, 1, n); q = read(); while (q--) { int t = read(), l = read(), r = read(); cout << Seg::query(1, 1, n, l, r, t) << n ; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_IO__TOP_GPIO_OVTV2_PP_BLACKBOX_V
`define SKY130_FD_IO__TOP_GPIO_OVTV2_PP_BLACKBOX_V
/**
* top_gpio_ovtv2: General Purpose I/0.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_io__top_gpio_ovtv2 (
OUT ,
OE_N ,
HLD_H_N ,
ENABLE_H ,
ENABLE_INP_H ,
ENABLE_VDDA_H ,
ENABLE_VDDIO ,
ENABLE_VSWITCH_H,
INP_DIS ,
VTRIP_SEL ,
HYS_TRIM ,
SLOW ,
SLEW_CTL ,
HLD_OVR ,
ANALOG_EN ,
ANALOG_SEL ,
ANALOG_POL ,
DM ,
IB_MODE_SEL ,
VINREF ,
PAD ,
PAD_A_NOESD_H ,
PAD_A_ESD_0_H ,
PAD_A_ESD_1_H ,
AMUXBUS_A ,
AMUXBUS_B ,
IN ,
IN_H ,
TIE_HI_ESD ,
TIE_LO_ESD ,
VDDIO ,
VDDIO_Q ,
VDDA ,
VCCD ,
VSWITCH ,
VCCHIB ,
VSSA ,
VSSD ,
VSSIO_Q ,
VSSIO
);
input OUT ;
input OE_N ;
input HLD_H_N ;
input ENABLE_H ;
input ENABLE_INP_H ;
input ENABLE_VDDA_H ;
input ENABLE_VDDIO ;
input ENABLE_VSWITCH_H;
input INP_DIS ;
input VTRIP_SEL ;
input HYS_TRIM ;
input SLOW ;
input [1:0] SLEW_CTL ;
input HLD_OVR ;
input ANALOG_EN ;
input ANALOG_SEL ;
input ANALOG_POL ;
input [2:0] DM ;
input [1:0] IB_MODE_SEL ;
input VINREF ;
inout PAD ;
inout PAD_A_NOESD_H ;
inout PAD_A_ESD_0_H ;
inout PAD_A_ESD_1_H ;
inout AMUXBUS_A ;
inout AMUXBUS_B ;
output IN ;
output IN_H ;
output TIE_HI_ESD ;
output TIE_LO_ESD ;
inout VDDIO ;
inout VDDIO_Q ;
inout VDDA ;
inout VCCD ;
inout VSWITCH ;
inout VCCHIB ;
inout VSSA ;
inout VSSD ;
inout VSSIO_Q ;
inout VSSIO ;
endmodule
`default_nettype wire
`endif // SKY130_FD_IO__TOP_GPIO_OVTV2_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND3_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__AND3_FUNCTIONAL_V
/**
* and3: 3-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__and3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, C, A, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND3_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; long long K = 1000000007; long long gcd(long long a, long long b, long long& x, long long& y) { if (a == 0) { x = 0; y = 1; return b; } long long x1, y1; long long d = gcd(b % a, a, x1, y1); x = y1 - (b / a) * x1; y = x1; return d; } int32_t main() { long long n, m; cin >> n >> m; long long ans = n + 1 - m; for (long long i = 0; i < m; i++) { ans *= (2 * n + 2); ans %= K; } long long x, y; gcd(n + 1, K, x, y); x *= ans; x %= K; if (x < 0) x += K; cout << x << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 400005; int n, m, h[N], p[N]; set<int> S; set<int>::iterator it; inline void read(int &i) { i = 0; char c = getchar(); bool j = 0; for (; !isdigit(c); c = getchar()) if (c == - ) j = 1; for (; isdigit(c); c = getchar()) i = (i << 1) + (i << 3) + c - 0 ; i = j ? -i : i; } struct Segment_Tree { int sz, mx[N << 2]; inline void mdf(int u, int l, int r, int x, int y) { if (l == r) { mx[u] = y; return; } int mid = (l + r) >> 1; if (x <= mid) mdf(u << 1, l, mid, x, y); else mdf(u << 1 | 1, mid + 1, r, x, y); mx[u] = max(mx[u << 1], mx[u << 1 | 1]); } inline int qry(int u, int l, int r, int L, int R) { if (L <= l && r <= R) return mx[u]; int mid = (l + r) >> 1, as = 0; if (L <= mid) as = max(as, qry(u << 1, l, mid, L, R)); if (mid < R) as = max(as, qry(u << 1 | 1, mid + 1, r, L, R)); return as; } inline void mdf(int x, int y) { mdf(1, 0, sz, x, y); } inline int qry(int l, int r) { return qry(1, 0, sz, l, r); } } A, B; int main() { read(n); read(m); A.sz = n + 100; B.sz = m + 200; int op, x, y; for (int tim = 1; tim <= m; ++tim) { read(op), read(x); if (op == 1) { x = n + 1 - x; read(y); y = tim + 10 - y; p[y] = x; h[x] = y; S.insert(x); for (int i = y + 1; i <= y + 9; ++i) if (p[i]) A.mdf(p[i], 0); for (int i = y; i <= y + 9; ++i) if (p[i]) { int f = A.qry(0, p[i] - 1) + 1; A.mdf(p[i], f); B.mdf(i, f); } } else { it = S.end(); while (x--) it--, B.mdf(h[*it], 0); int del = *it; A.mdf(*it, 0); it++; for (; it != S.end(); it++) { int f = B.qry(0, h[*it] - 1) + 1; B.mdf(h[*it], f); A.mdf(*it, f); } S.erase(del); p[h[del]] = 0; h[del] = 0; } printf( %d n , A.qry(1, n)); } return 0; } |
// Copyright (c) 2000-2012 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 29441 $
// $Date: 2012-08-27 21:58:03 +0000 (Mon, 27 Aug 2012) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
// N -bit counter with load, set and 2 increment
module Counter(CLK,
RST,
Q_OUT,
DATA_A, ADDA,
DATA_B, ADDB,
DATA_C, SETC,
DATA_F, SETF);
parameter width = 1;
parameter init = 0;
input CLK;
input RST;
input [width - 1 : 0] DATA_A;
input ADDA;
input [width - 1 : 0] DATA_B;
input ADDB;
input [width - 1 : 0] DATA_C;
input SETC;
input [width - 1 : 0] DATA_F;
input SETF;
output [width - 1 : 0] Q_OUT;
reg [width - 1 : 0] q_state ;
assign Q_OUT = q_state ;
always@(posedge CLK /*or `BSV_RESET_EDGE RST*/ ) begin
if (RST == `BSV_RESET_VALUE)
q_state <= `BSV_ASSIGNMENT_DELAY init;
else
begin
if ( SETF )
q_state <= `BSV_ASSIGNMENT_DELAY DATA_F ;
else
q_state <= `BSV_ASSIGNMENT_DELAY (SETC ? DATA_C : q_state ) + (ADDA ? DATA_A : {width {1'b0}}) + (ADDB ? DATA_B : {width {1'b0}} ) ;
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK)
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial begin
q_state = {((width + 1)/2){2'b10}} ;
end
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<long long> tree; void build(vector<long long> &arr, long long ind, long long l, long long r) { if (l == r) { tree[ind] = arr[l]; return; } long long mid = (l + r) / 2; build(arr, ind * 2, l, mid); build(arr, ind * 2 + 1, mid + 1, r); tree[ind] = max(tree[ind * 2], tree[ind * 2 + 1]); } long long getMax(long long ind, long long tl, long long tr, long long l, long long r) { if (l > r) return 0; if (l == tl && r == tr) return tree[ind]; long long tm = (tl + tr) / 2; long long a = getMax(ind * 2, tl, tm, l, min(r, tm)); long long b = getMax(ind * 2 + 1, tm + 1, tr, max(l, tm + 1), r); return max(a, b); } int main() { ios::sync_with_stdio(false); cin.tie(0); long long n; cin >> n; vector<long long> a(n); for (int i = 0; i < n; i++) { cin >> a[i]; } long long count = 1; for (int i = n - 2; i >= 0; i--) { if (a[i] < a[i + 1]) { count++; } else { break; } } cout << n - count; return 0; } |
#include <bits/stdc++.h> using namespace std; #define pb push_back #define mp make_pair #define x first #define y second #define LL long long #define LD long double #define Complex complex<double> #define y1 ___y1 #define next ___next #define left ___left #define right ___right #define pii pair<int, int> #define pll pair<LL, LL> #define pdd pair<double, double> #define pldld pair<LD, LD> #define vi vector<int> #define vl vector<LL> #define vii vector<pii> #define vll vector<pll> #define PQ priority_queue #define ffo fflush(stdout) #define gch getchar() #define e (int)(1e9 + 7) #define e2 (double)2.71828182846 #define pi (double)3.14159265358979 #define ri(X) scanf( %d , &(X)) #define rii(X, Y) scanf( %d%d , &(X), &(Y)) #define riii(X, Y, Z) scanf( %d%d%d , &(X), &(Y), &(Z)) #define rl(X) scanf( %lld , &(X)) #define rll(X, Y) scanf( %lld%lld , &(X), &(Y)) #define rlll(X, Y, Z) scanf( %lld%lld%lld , &(X), &(Y), &(Z)) #define printi(X) printf( %d , (int)(X)) #define printii(X, Y) printf( %d %d , (int)(X), (int)(Y)) #define printiii(X, Y, Z) printf( %d %d %d , (int)(X), (int)(Y), (int)(Z)) #define printl(X) printf( %lld , (LL)(X)) #define printll(X, Y) printf( %lld %lld , (LL)(X), (LL)(Y)) #define printlll(X, Y, Z) printf( %lld %lld %lld , (LL)(X), (LL)(Y), (LL)(Z)) #define enter printf( n ) #define space printf( ) struct matrix { int sz; LL a[105][105]; matrix& operator = (const matrix &T) { sz = T.sz; for (int i = 1; i <= sz; i++) { for (int j = 1; j <= sz; j++) { a[i][j] = T.a[i][j]; } } return *this; } matrix operator + (const matrix &T) const { matrix ans; ans.sz = sz; for (int i = 1; i <= sz; i++) { for (int j = 1; j <= sz; j++) { ans.a[i][j] = a[i][j] + T.a[i][j]; ans.a[i][j] %= e; } } return ans; } matrix operator * (const matrix &T) const { matrix ans; ans.sz = sz; for (int i = 1; i <= sz; i++) { for (int j = 1; j <= sz; j++) { ans.a[i][j] = 0; for (int k = 1; k <= sz; k++) { ans.a[i][j] += a[i][k] * T.a[k][j]; ans.a[i][j] %= e; } } } return ans; } matrix I() { matrix ans; ans.sz = sz; for (int i = 1; i <= sz; i++) { for (int j = 1; j <= sz; j++) { if (i == j) ans.a[i][j] = 1; else ans.a[i][j] = 0; } } return ans; } matrix power(LL p) { if (p == 0) return I(); if (p == 1) return *this; matrix tmp = power(p / 2); if (p % 2) tmp = tmp * tmp * (*this); else tmp = tmp * tmp; return tmp; } void print() { for (int i = 1; i <= sz; i++) { for (int j = 1; j <= sz; j++) { printf(j == sz? %lld n : %lld , a[i][j]); } } return; } }; struct polynomial { vector<Complex> v; int sz; polynomial operator * (const polynomial &T) const { polynomial ans; if (sz >= T.sz) { ans = *this; for (int i = 0; i < T.sz; i++) { ans.v[i] *= T.v[i]; } } else { ans = T; for (int i = 0; i < sz; i++) { ans.v[i] *= v[i]; } } return ans; } }; polynomial FFT(polynomial a) { if (a.sz <= 1) return a; polynomial even, odd; even.sz = odd.sz = 0; for (int i = 0; i < a.sz; i += 2) { even.v.pb(a.v[i]); even.sz++; } for (int i = 1; i < a.sz; i += 2) { odd.v.pb(a.v[i]); odd.sz++; } polynomial Even = FFT(even); polynomial Odd = FFT(odd); polynomial ans; ans.sz = a.sz; for (int i = 0; i < ans.sz; i++) { ans.v.pb(0); } for (int i = 0; i < a.sz / 2; i++) { Complex w = polar(1.0, -2 * pi * i / a.sz) * Odd.v[i]; ans.v[i] = Even.v[i] + w; ans.v[i + a.sz / 2] = Even.v[i] - w; } return ans; } polynomial IFFT(polynomial a) { for (int i = 0; i < a.sz; i++) { a.v[i] = conj(a.v[i]); } polynomial ans = FFT(a); for (int i = 0; i < a.sz; i++) { ans.v[i] = conj(ans.v[i]); ans.v[i] /= ans.sz; } return ans; } struct polygon { int n; pii a[1005]; double area() { double d1 = 0, d2 = 0; for (int i = 0; i < n; i++) { d1 += a[i].x * a[(i + 1) % n].y; d2 += a[(i + 1) % n].x * a[i].y; } return (d1 - d2) / 2; } bool inside(pldld p) { int ct = 0; LD d; pldld p1 = a[0]; for (int i = 1; i <= n; i++) { pldld p2 = a[i % n]; if (p.y > min(p1.y, p2.y) && p.y <= max(p1.y, p2.y) && p.x <= max(p1.x, p2.x) && p1.y != p2.y) { d = (p.y - p1.y) * (p2.x - p1.x) / (p2.y - p1.y) + p1.x; if (p1.x == p2.x || p.x <= d) ct++; } p1 = p2; } return ct % 2; } }; struct segtree { int l, r, mid; LL val = 0, lazy = 0; segtree *lc, *rc; segtree(int L, int R) { l = L; r = R; mid = (l + r) / 2; if (l != r) { lc = new segtree(l, mid); rc = new segtree(mid + 1, r); } } void apply(LL X) { val += X; // val += X * (r - l + 1); lazy += X; } void push() { if (l == r) return; lc->apply(lazy); rc->apply(lazy); lazy = 0; } void update(int L, int R, LL X) { push(); if (l == L && r == R) { apply(X); return; } else if (R <= mid) lc->update(L, R, X); else if (L >= mid + 1) rc->update(L, R, X); else { lc->update(L, mid, X); rc->update(mid + 1, R, X); } val = min(lc->val, rc->val); // val = lc->val + rc->val; } LL query(int L, int R) { push(); if (l == L && r == R) return val; else if (R <= mid) return lc->query(L, R); else if (L >= mid + 1) return rc->query(L, R); else { return min(lc->query(L, mid), rc->query(mid + 1, R)); // return lc->query(L, mid) + rc->query(mid + 1, R); } } //segroot = new segtree(0, n - 1) } *segroot; LL power(LL a, LL p) { if (p == 0) return 1; if (p == 1) return a; LL tmp = power(a, p / 2); if (p % 2) tmp = tmp * tmp % e * a; else tmp *= tmp; return tmp % e; } struct node { int num; int l, r; }; int T; int n, a[200005]; node p[200005]; void solve(int CASE) { ri(n); for (int i = 1; i <= n; i++) { ri(a[i]); } int small = 0; int big = 0; int sz = 3; p[3].l = 1; p[3].r = 2; p[3].num = a[1]; int pl = 3; for (int i = 2; i <= n; i++) { if (a[i] == p[pl].num) { } else if (a[i] > p[pl].num) { if (p[pl].r == 2) { int next = ++sz; p[pl].r = next; p[next].num = a[i]; p[next].l = pl; p[next].r = 2; pl = next; } else if (p[p[pl].r].num == a[i]) { pl = p[pl].r; } else if (p[p[pl].r].num > a[i]) { int next = ++sz; p[next].num = a[i]; p[next].l = pl; p[next].r = p[pl].r; p[p[next].r].l = next; p[pl].r = next; pl = next; } else { printf( NO n ); return; } } else { if (p[pl].l == 1) { int next = ++sz; p[pl].l = next; p[next].num = a[i]; p[next].l = 1; p[next].r = pl; pl = next; } else if (p[p[pl].l].num == a[i]) { pl = p[pl].l; } else if (p[p[pl].l].num < a[i]) { int next = ++sz; p[next].num = a[i]; p[next].r = pl; p[next].l = p[pl].l; p[p[next].l].r = next; p[pl].l = next; pl = next; } else { printf( NO n ); return; } } } printf( YES n ); return; } int main() { // ios::sync_with_stdio(false); // cin.tie(NULL), cout.tie(NULL); T = 1; ri(T); // delete if one test case for (int _ = 1; _ <= T; _++) { solve(_); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int T; cin >> T; while (T--) { string a, b, c; cin >> a >> b >> c; int n = a.size(); bool Ok = true; for (int i = 0; i < n; i++) Ok &= (c[i] == a[i] || b[i] == c[i]); puts(Ok ? YES : NO ); } } |
#include <bits/stdc++.h> using namespace std; const int maxN = 300, maxTreeSize = 1 << 10; struct Tree { private: bool active[maxTreeSize]; int Min[maxTreeSize], Max[maxTreeSize], offset; public: void resize(int n) { offset = 1; while (offset < n) offset *= 2; } void add(int v, int val) { v += offset; active[v] = true; Min[v] = Max[v] = val; while (v > 1) { v /= 2; active[v] = true; if (active[v * 2] and active[v * 2 + 1]) { Min[v] = min(Min[v * 2], Min[v * 2 + 1]); Max[v] = max(Max[v * 2], Max[v * 2 + 1]); } else if (active[v * 2]) { Min[v] = Min[v * 2]; Max[v] = Max[v * 2]; } else { Min[v] = Min[v * 2 + 1]; Max[v] = Max[v * 2 + 1]; } } } pair<int, int> query(int val) { int v = 1; while (v < offset) { if (!active[v * 2] or !active[v * 2 + 1]) { v = active[v * 2] ? v * 2 : v * 2 + 1; continue; } if (val <= Max[v * 2]) { v = v * 2; continue; } if (Min[v * 2 + 1] <= val) { v = v * 2 + 1; continue; } int diff1 = abs(Max[v * 2] - val), diff2 = abs(Min[v * 2 + 1] - val); v = (diff1 <= diff2) ? v * 2 : v * 2 + 1; } return make_pair(v - offset, abs(val - Max[v])); } void clear() { for (int i = 1; i < offset * 2; i++) active[i] = false; } }; int sumpUp[maxN + 1][maxN + 1], sumpDown[maxN + 1][maxN + 1], sumpLeft[maxN + 1][maxN + 1], sumpRight[maxN + 1][maxN + 1], sump1[maxN + 1], sump2[maxN + 1], T[maxN + 1][maxN + 1]; int tp, tu, td, ord_in_tree[maxN + 1]; pair<int, int> temp[maxN]; int cost_of_step(int a, int b) { if (a == b) return tp; if (a < b) return tu; if (a > b) return td; } Tree tree; int main() { int n, m, ts; scanf( %d%d%d%d%d%d , &n, &m, &ts, &tp, &tu, &td); for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) scanf( %d , &T[i][j]); } for (int i = 1; i <= n; i++) { for (int j = 2; j <= m; j++) sumpLeft[i][j] = sumpLeft[i][j - 1] + cost_of_step(T[i][j - 1], T[i][j]); for (int j = m - 1; j > 0; j--) sumpRight[i][j] = sumpRight[i][j + 1] + cost_of_step(T[i][j + 1], T[i][j]); } for (int j = 1; j <= m; j++) { for (int i = 2; i <= n; i++) sumpUp[i][j] = sumpUp[i - 1][j] + cost_of_step(T[i - 1][j], T[i][j]); for (int i = n - 1; i > 0; i--) sumpDown[i][j] = sumpDown[i + 1][j] + cost_of_step(T[i + 1][j], T[i][j]); } tree.resize(m); int min_diff = 1000000000; int i1, j1, i2, j2; for (int a = 1; a <= n; a++) { for (int b = a + 2; b <= n; b++) { for (int j = 1; j <= m; j++) { sump1[j] = sumpLeft[a][j] + (sumpUp[b][j] - sumpUp[a][j]) + sumpRight[b][1] - sumpRight[b][j]; sump2[j] = sumpLeft[a][j] - (sumpDown[a][j] - sumpDown[b][j]) + (sumpRight[b][1] - sumpRight[b][j]); temp[j - 1] = make_pair(sump2[j], j); } sort(temp, temp + m); for (int j = 0; j < m; j++) ord_in_tree[temp[j].second] = j; tree.add(ord_in_tree[1], sump2[1]); for (int j = 3; j <= m; j++) { pair<int, int> res_temp = tree.query(sump1[j] - ts); if (res_temp.second < min_diff) { min_diff = res_temp.second; i1 = a; j1 = temp[res_temp.first].second; i2 = b; j2 = j; } tree.add(ord_in_tree[j - 1], sump2[j - 1]); } tree.clear(); } } printf( %d %d %d %d n , i1, j1, i2, j2); return 0; } |
#include <bits/stdc++.h> using namespace std; long long int dp[20][1 << 20]; long long int len[1 << 21] = {0}; std::vector<int> v[1000000]; int n; int r[21][21]; long long int solve(int last, int mask, int pa) { long long int sol = 0; if (r[last][pa] == 1 && len[mask] >= 3) { sol += 1; } if (dp[last][mask]) { return dp[last][mask]; } for (int i = 0; i < v[last].size(); i++) { if ((mask & (1 << v[last][i])) == 0 && v[last][i] > pa) { sol += solve(v[last][i], mask | (1 << v[last][i]), pa); } } return dp[last][mask] = sol; } int main() { int x, y, m; cin >> n >> m; while (m--) { cin >> x >> y; x--; y--; v[x].push_back(y); v[y].push_back(x); r[x][y] = 1; r[y][x] = 1; } for (int i = 1; i <= (1 << (n)); i++) { x = 0; for (int j = 0; j < n; j++) { if ((i >> j) & 1) x++; } len[i] = x; } long long int sol = 0; for (int i = 0; i < n; i++) { sol += solve(i, 0 | (1 << i), i); } cout << fixed; cout << setprecision(0) << sol / 2 << endl; } |
#include <bits/stdc++.h> using namespace std; char s[2000][2000]; int n, m; bool h[300][300]; bool v[300][300]; const long long mod = 1000000007; void get(int x, int y, bool& h, bool& v) { int cnt = 0; for (int i = 0; i < 3; i++) for (int j = 0; j < 3; j++) { if (s[x + i][y + j] == O ) cnt++; } if (cnt == 5 || cnt == 4 || cnt == 1 || cnt == 0) { v = h = true; return; } if (cnt == 2 || cnt == 3) { h = s[x][y] == O ; v = !h; return; } h = (s[x][y + 1] == O ); v = !h; } long long calc1(int y) { if (n % 2 != 0) return 0; for (int i = 0; i < n; i++) if (!v[i][y]) return 0; return 1; } long long tmp[300]; long long dp[300]; long long calc2(int y) { if (y + 1 >= m) return 0; for (int i = 0; i <= n; i++) tmp[i] = 0; tmp[0] = 1; for (int i = 0; i < n; i++) { if (h[i][y] && h[i][y + 1]) { tmp[i + 1] += tmp[i]; tmp[i + 1] %= mod; } if (i < n - 1 && v[i][y] && v[i + 1][y] && v[i + 1][y + 1] && v[i][y + 1]) { tmp[i + 2] += tmp[i]; tmp[i + 2] %= mod; } } if (calc1(y) && calc1(y + 1)) tmp[n] = (tmp[n] - 1 + mod) % mod; return tmp[n]; } int main() { scanf( %d %d n , &n, &m); for (int i = 0; i < 4 * n + 1; i++) { gets(s[i]); } for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) get(4 * i + 1, 4 * j + 1, h[i][j], v[i][j]); dp[0] = 1; for (int i = 0; i < m; i++) { dp[i + 1] += dp[i] * calc1(i); dp[i + 2] += dp[i] * calc2(i); dp[i + 1] %= mod; dp[i + 2] %= mod; } cout << dp[m] << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; inline void read(int &x) { register char c = getchar(); x = 0; for (; c < 0 || c > 9 ; c = getchar()) ; for (; c >= 0 && c <= 9 ; c = getchar()) x = (x << 1) + (x << 3) + c - 0 ; } priority_queue<int> q; int main() { priority_queue<int> pq; int n, a, b, c, d; long long z = 0; read(n); while (n--) { read(a); read(b); read(c); read(d); if (a + b < c + d) z += max(0, a - d) - max(0, b - c); else { z += a + c; q.push(a + b); q.push(c + d); } } while (!q.empty()) { q.pop(); z -= q.top(); q.pop(); } printf( %I64d , z); } |
#include <bits/stdc++.h> using namespace std; template <typename T> ostream& operator<<(ostream& os, const vector<T>& v) { for (auto i : v) os << i << ; return os; } template <typename T> ostream& operator<<(ostream& os, const set<T>& v) { for (auto i : v) os << i << ; return os; } template <typename T> T read() { char c = getchar(); T sgn = 1; T t = 0; while (!isdigit(c)) { if (c == - ) sgn = -sgn; c = getchar(); } while (isdigit(c)) { t *= 10; t += c - 0 ; c = getchar(); } return t * sgn; } const int N = 1e5; vector<int> atk, def, had; bool used[N]; int main() { int n = read<int>(); int m = read<int>(); for (int i = 0; i < n; ++i) { char s[10]; int val; scanf( %s %d , s, &val); getchar(); if (s[0] == A ) atk.push_back(val); if (s[0] == D ) def.push_back(val); } for (int i = 0; i < m; ++i) had.push_back(read<int>()); sort(atk.begin(), atk.end()); sort(def.begin(), def.end()); sort(had.begin(), had.end()); int ans = 0; for (int i = m - 1; i >= 0; --i) { int cur = 0; for (int j = 0, t = atk.size(); j < m - i && j < t; ++j) if (had[i + j] >= atk[j]) cur += had[i + j] - atk[j]; ans = max(ans, cur); } int p = 0; for (auto i : def) { while (p < m && had[p] <= i) p++; if (p == m) { printf( %d n , ans); exit(0); } used[p] = true; p++; } p = m - 1; int ans2 = 0; for (int i = atk.size() - 1; i >= 0; --i) { int j = atk[i]; while (p >= 0 && used[p]) p--; if (p == -1 || had[p] < j) { printf( %d n , ans); exit(0); } ans2 += had[p] - j; used[p] = true; p--; } for (int i = 0; i < m; ++i) if (!used[i]) ans2 += had[i]; printf( %d n , max(ans, ans2)); return 0; } |
#include <bits/stdc++.h> using namespace std; int marcg[112], marcb[112], n, m, b, g, xi; int main() { scanf( %d %d , &n, &m); scanf( %d , &b); for (int i = 0; i < b; i++) { scanf( %d , &xi); marcb[xi] = 1; } scanf( %d , &g); for (int i = 0; i < g; i++) { scanf( %d , &xi); marcg[xi] = 1; } int mud = 1; while (mud != 0) { mud = 0; for (int i = 0; i < n * m; i++) { if (marcg[i % m] == marcb[i % n]) continue; marcg[i % m] = 1; marcb[i % n] = 1; mud = 1; } } int ok = 0; for (int i = 0; i < m; i++) { if (marcg[i] == 0) ok = 1; } if (ok != 0) { printf( No n ); return 0; } for (int i = 0; i < n; i++) { if (marcb[i] == 0) ok = 1; } if (ok != 0) { printf( No n ); return 0; } printf( Yes n ); } |
`default_nettype none
module l1_inst_cache_counter(
input wire iCLOCK,
input wire inRESET,
//Hit Infomation
input wire iCACHE_VALID,
input wire iCACHE_HIT,
//Infomation
output wire [6:0] oINFO_COUNT
);
reg [99:0] b_counter;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_counter <= 100'h0;
end
else begin
if(iCACHE_VALID)begin
b_counter <= {b_counter[98:0], iCACHE_HIT};
end
end
end
reg [3:0] b_buffer0[0:9]; //10*10
reg [5:0] b_buffer1[0:1]; //50*2
reg [6:0] b_buffer2; //100*1
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_buffer0[0] <= 4'h0;
b_buffer0[1] <= 4'h0;
b_buffer0[2] <= 4'h0;
b_buffer0[3] <= 4'h0;
b_buffer0[4] <= 4'h0;
b_buffer0[5] <= 4'h0;
b_buffer0[6] <= 4'h0;
b_buffer0[7] <= 4'h0;
b_buffer0[8] <= 4'h0;
b_buffer0[9] <= 4'h0;
b_buffer1[0] <= 6'h0;
b_buffer1[1] <= 6'h1;
b_buffer2 <= 7'h0;
end
else begin
//Buffer0
b_buffer0[0] <= 4'h0
+ b_counter[0] + b_counter[1] + b_counter[2] + b_counter[3] + b_counter[4]
+ b_counter[5] + b_counter[6] + b_counter[7] + b_counter[8] + b_counter[9];
b_buffer0[1] <= 4'h0
+ b_counter[10] + b_counter[11] + b_counter[12] + b_counter[13] + b_counter[14]
+ b_counter[15] + b_counter[16] + b_counter[17] + b_counter[18] + b_counter[19];
b_buffer0[2] <= 4'h0
+ b_counter[20] + b_counter[21] + b_counter[22] + b_counter[23] + b_counter[24]
+ b_counter[25] + b_counter[26] + b_counter[27] + b_counter[28] + b_counter[29];
b_buffer0[3] <= 4'h0
+ b_counter[30] + b_counter[31] + b_counter[32] + b_counter[33] + b_counter[34]
+ b_counter[35] + b_counter[36] + b_counter[37] + b_counter[38] + b_counter[39];
b_buffer0[4] <= 4'h0
+ b_counter[40] + b_counter[41] + b_counter[42] + b_counter[43] + b_counter[44]
+ b_counter[45] + b_counter[46] + b_counter[47] + b_counter[48] + b_counter[49];
b_buffer0[5] <= 4'h0
+ b_counter[50] + b_counter[51] + b_counter[52] + b_counter[53] + b_counter[54]
+ b_counter[55] + b_counter[56] + b_counter[57] + b_counter[58] + b_counter[59];
b_buffer0[6] <= 4'h0
+ b_counter[60] + b_counter[61] + b_counter[62] + b_counter[63] + b_counter[64]
+ b_counter[65] + b_counter[66] + b_counter[67] + b_counter[68] + b_counter[69];
b_buffer0[7] <= 4'h0
+ b_counter[70] + b_counter[71] + b_counter[72] + b_counter[73] + b_counter[74]
+ b_counter[75] + b_counter[76] + b_counter[77] + b_counter[78] + b_counter[79];
b_buffer0[8] <= 4'h0
+ b_counter[80] + b_counter[81] + b_counter[82] + b_counter[83] + b_counter[84]
+ b_counter[85] + b_counter[86] + b_counter[87] + b_counter[88] + b_counter[89];
b_buffer0[9] <= 4'h0
+ b_counter[90] + b_counter[91] + b_counter[92] + b_counter[93] + b_counter[94]
+ b_counter[95] + b_counter[96] + b_counter[97] + b_counter[98] + b_counter[99];
b_buffer1[0] <= 6'h0 + b_buffer0[0] + b_buffer0[1] + b_buffer0[2] + b_buffer0[3] + b_buffer0[4];
b_buffer1[1] <= 6'h0 + b_buffer0[5] + b_buffer0[6] + b_buffer0[7] + b_buffer0[8] + b_buffer0[9];
b_buffer2 <= b_buffer1[0] + b_buffer1[1];
end
end
assign oINFO_COUNT = b_buffer2;
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; vector<string> split(const string& s, char c) { vector<string> v; stringstream ss(s); string x; while (getline(ss, x, c)) { v.emplace_back(x); } return move(v); } void err(vector<string>::iterator it) {} template <typename T, typename... Args> void err(vector<string>::iterator it, T a, Args... args) { cerr << it->substr((*it)[0] == , it->length()) << = << a << , ; err(++it, args...); } vector<pair<int, int>> vt[101]; int dp[101][101][26][2]; bool rec(int u, int v, int ch, int side) { if (dp[u][v][ch][side] != -1) return dp[u][v][ch][side]; int ans = 0; if (side) { for (auto g : vt[v]) { if (g.second >= ch) ans |= !rec(u, g.first, g.second, side ^ 1); } } else { for (auto g : vt[u]) { if (g.second >= ch) ans |= !rec(g.first, v, g.second, side ^ 1); } } return dp[u][v][ch][side] = ans; } int main() { memset(dp, -1, sizeof dp); int n, m, i, j, u, v; cin >> n >> m; char c; for (i = 0; i < m; ++i) { cin >> u >> v >> c; vt[u].push_back({v, c - a }); } for (i = 1; i <= n; ++i) { for (j = 1; j <= n; ++j) { if (rec(i, j, 0, 0)) printf( A ); else printf( B ); } puts( ); } } |
// --------------------------------------------------
//
// Generic round robin arbiter
//
// A generic round robin arbiter with parameterizeable number of clients
//
// --------------------------------------------------
module rr_arb
#( parameter CLIENTS=2 )
(
input wire clk,
input wire reset,
input wire cycle,
input wire [CLIENTS-1:0] req,
output reg [CLIENTS-1:0] gnt
);
wire active_req;
reg [CLIENTS-1:0] previous_winner;
wire [2*CLIENTS-1:0] start_array;
assign active_req = cycle && |req;
integer index;
integer allowed;
assign start_array = {{CLIENTS{1'b0}},previous_winner};
always @ (*) begin
gnt = 0;
if( active_req ) begin
for(allowed=0, index=0; index<2*CLIENTS; index=index+1) begin
if( start_array[index] == 1 ) begin
allowed = 1;
end
if( (allowed == 1) && (req[index] == 1) ) begin
allowed = 0;
gnt[index%CLIENTS] = 1;
end
end
end
end
always @ (posedge clk) begin
if( reset ) begin
previous_winner <= #0 1;
end
else begin
if( active_req ) begin
previous_winner <= #0 gnt;
end
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2014 ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
// Module: ex_mem
// File: ex_mem.v
// Author: Lei Silei
// E-mail:
// Description: EX/MEM½×¶ÎµÄ¼Ä´æÆ÷
// Revision: 1.0
//////////////////////////////////////////////////////////////////////
`include "defines.v"
module ex_mem(
input wire clk,
input wire rst,
//À´×Ô¿ØÖÆÄ£¿éµÄÐÅÏ¢
input wire[5:0] stall,
input wire flush,
//À´×ÔÖ´Ðн׶εÄÐÅÏ¢
input wire[`RegAddrBus] ex_wd,
input wire ex_wreg,
input wire[`RegBus] ex_wdata,
input wire[`RegBus] ex_hi,
input wire[`RegBus] ex_lo,
input wire ex_whilo,
//ΪʵÏÖ¼ÓÔØ¡¢·Ã´æÖ¸Áî¶øÌí¼Ó
input wire[`AluOpBus] ex_aluop,
input wire[`RegBus] ex_mem_addr,
input wire[`RegBus] ex_reg2,
input wire[`DoubleRegBus] hilo_i,
input wire[1:0] cnt_i,
input wire ex_cp0_reg_we,
input wire[4:0] ex_cp0_reg_write_addr,
input wire[`RegBus] ex_cp0_reg_data,
input wire[31:0] ex_excepttype,
input wire ex_is_in_delayslot,
input wire[`RegBus] ex_current_inst_address,
//Ë͵½·Ã´æ½×¶ÎµÄÐÅÏ¢
output reg[`RegAddrBus] mem_wd,
output reg mem_wreg,
output reg[`RegBus] mem_wdata,
output reg[`RegBus] mem_hi,
output reg[`RegBus] mem_lo,
output reg mem_whilo,
//ΪʵÏÖ¼ÓÔØ¡¢·Ã´æÖ¸Áî¶øÌí¼Ó
output reg[`AluOpBus] mem_aluop,
output reg[`RegBus] mem_mem_addr,
output reg[`RegBus] mem_reg2,
output reg mem_cp0_reg_we,
output reg[4:0] mem_cp0_reg_write_addr,
output reg[`RegBus] mem_cp0_reg_data,
output reg[31:0] mem_excepttype,
output reg mem_is_in_delayslot,
output reg[`RegBus] mem_current_inst_address,
output reg[`DoubleRegBus] hilo_o,
output reg[1:0] cnt_o
);
always @ (posedge clk) begin
if(rst == `RstEnable) begin
mem_wd <= `NOPRegAddr;
mem_wreg <= `WriteDisable;
mem_wdata <= `ZeroWord;
mem_hi <= `ZeroWord;
mem_lo <= `ZeroWord;
mem_whilo <= `WriteDisable;
hilo_o <= {`ZeroWord, `ZeroWord};
cnt_o <= 2'b00;
mem_aluop <= `EXE_NOP_OP;
mem_mem_addr <= `ZeroWord;
mem_reg2 <= `ZeroWord;
mem_cp0_reg_we <= `WriteDisable;
mem_cp0_reg_write_addr <= 5'b00000;
mem_cp0_reg_data <= `ZeroWord;
mem_excepttype <= `ZeroWord;
mem_is_in_delayslot <= `NotInDelaySlot;
mem_current_inst_address <= `ZeroWord;
end else if(flush == 1'b1 ) begin
mem_wd <= `NOPRegAddr;
mem_wreg <= `WriteDisable;
mem_wdata <= `ZeroWord;
mem_hi <= `ZeroWord;
mem_lo <= `ZeroWord;
mem_whilo <= `WriteDisable;
mem_aluop <= `EXE_NOP_OP;
mem_mem_addr <= `ZeroWord;
mem_reg2 <= `ZeroWord;
mem_cp0_reg_we <= `WriteDisable;
mem_cp0_reg_write_addr <= 5'b00000;
mem_cp0_reg_data <= `ZeroWord;
mem_excepttype <= `ZeroWord;
mem_is_in_delayslot <= `NotInDelaySlot;
mem_current_inst_address <= `ZeroWord;
hilo_o <= {`ZeroWord, `ZeroWord};
cnt_o <= 2'b00;
end else if(stall[3] == `Stop && stall[4] == `NoStop) begin
mem_wd <= `NOPRegAddr;
mem_wreg <= `WriteDisable;
mem_wdata <= `ZeroWord;
mem_hi <= `ZeroWord;
mem_lo <= `ZeroWord;
mem_whilo <= `WriteDisable;
hilo_o <= hilo_i;
cnt_o <= cnt_i;
mem_aluop <= `EXE_NOP_OP;
mem_mem_addr <= `ZeroWord;
mem_reg2 <= `ZeroWord;
mem_cp0_reg_we <= `WriteDisable;
mem_cp0_reg_write_addr <= 5'b00000;
mem_cp0_reg_data <= `ZeroWord;
mem_excepttype <= `ZeroWord;
mem_is_in_delayslot <= `NotInDelaySlot;
mem_current_inst_address <= `ZeroWord;
end else if(stall[3] == `NoStop) begin
mem_wd <= ex_wd;
mem_wreg <= ex_wreg;
mem_wdata <= ex_wdata;
mem_hi <= ex_hi;
mem_lo <= ex_lo;
mem_whilo <= ex_whilo;
hilo_o <= {`ZeroWord, `ZeroWord};
cnt_o <= 2'b00;
mem_aluop <= ex_aluop;
mem_mem_addr <= ex_mem_addr;
mem_reg2 <= ex_reg2;
mem_cp0_reg_we <= ex_cp0_reg_we;
mem_cp0_reg_write_addr <= ex_cp0_reg_write_addr;
mem_cp0_reg_data <= ex_cp0_reg_data;
mem_excepttype <= ex_excepttype;
mem_is_in_delayslot <= ex_is_in_delayslot;
mem_current_inst_address <= ex_current_inst_address;
end else begin
hilo_o <= hilo_i;
cnt_o <= cnt_i;
end //if
end //always
endmodule |
#include <bits/stdc++.h> using namespace std; const int MOD = int(1e9 + 7), maxK = 23, maxN = 107; vector<int> a[maxN]; int n, k; int f[maxN][maxK][maxK], g[2][maxK][maxK]; inline void add(int &a, long long b) { a = (a + b) % MOD; } void calculate(int u, int par) { memset(g, 0, sizeof g); bool first = true; int G = 1, nj, np, cur = 1, prev = 0; memset(g[cur], 0, sizeof g[cur]); g[cur][k + 1][1] = 1; for (int v : a[u]) if (v != par) { int sg = 0; swap(cur, prev); memset(g[cur], 0, sizeof g[cur]); for (int j = 0; j <= k + 1; j++) for (int p = 0; p <= k + 1; p++) { if (p <= k) add(sg, f[v][j][p]); for (int jj = 0; jj <= k + 1; jj++) for (int pp = 0; pp <= k + 1; pp++) { nj = min(j, jj + 1); if (jj + p > k) np = p; else np = 0; if (j + pp > k && pp > 0) np = max(np, pp + 1); add(g[cur][nj][np], 1LL * g[prev][j][p] * f[v][jj][pp]); } } G = (1LL * G * sg) % MOD; } g[cur][0][0] = G; for (int j = 0; j <= k + 1; j++) for (int p = 0; p <= k + 1; p++) { f[u][j][p] = g[cur][j][p]; } } void visit(int u, int par = -1) { for (int v : a[u]) if (v != par) { visit(v, u); } calculate(u, par); } int main() { scanf( %d%d , &n, &k); for (int i = 0; i < n - 1; i++) { int u, v; scanf( %d%d , &u, &v); a[u].push_back(v); a[v].push_back(u); } memset(f, 0, sizeof f); visit(1, -1); int res = 0; for (int j = 0; j <= k + 1; j++) add(res, f[1][j][0]); printf( %d n , res); return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 10; int b[maxn]; char a[maxn]; int num[2 * maxn]; int main() { int n; scanf( %d , &n); int count0 = 0, count1 = 0; memset(num, -1, sizeof(num)); int len = 0, maxlen = 0; scanf( %s , a + 1); for (int i = 1; i <= n; i++) { if (a[i] == 0 ) count0++; else count1++; b[i] = count1 - count0; if (b[i] == 0) { if (maxlen < i) maxlen = i; continue; } if (num[b[i] + maxn] == -1) num[b[i] + maxn] = i; else { len = i - num[b[i] + maxn]; if (maxlen < len) maxlen = len; } } printf( %d n , maxlen); return 0; } |
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module is a FIFO with same clock for both reads and writes. *
* *
******************************************************************************/
module altera_up_sync_fifo (
// Inputs
clk,
reset,
write_en,
write_data,
read_en,
// Bidirectionals
// Outputs
fifo_is_empty,
fifo_is_full,
words_used,
read_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 31; // Data width
parameter DATA_DEPTH = 128;
parameter AW = 6; // Address width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input write_en;
input [DW: 0] write_data;
input read_en;
// Bidirectionals
// Outputs
output fifo_is_empty;
output fifo_is_full;
output [AW: 0] words_used;
output [DW: 0] read_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
scfifo Sync_FIFO (
// Inputs
.clock (clk),
.sclr (reset),
.data (write_data),
.wrreq (write_en),
.rdreq (read_en),
// Bidirectionals
// Outputs
.empty (fifo_is_empty),
.full (fifo_is_full),
.usedw (words_used),
.q (read_data),
// Unused
// synopsys translate_off
.aclr (),
.almost_empty (),
.almost_full ()
// synopsys translate_on
);
defparam
Sync_FIFO.add_ram_output_register = "OFF",
Sync_FIFO.intended_device_family = "Cyclone II",
Sync_FIFO.lpm_numwords = DATA_DEPTH,
Sync_FIFO.lpm_showahead = "ON",
Sync_FIFO.lpm_type = "scfifo",
Sync_FIFO.lpm_width = DW + 1,
Sync_FIFO.lpm_widthu = AW + 1,
Sync_FIFO.overflow_checking = "OFF",
Sync_FIFO.underflow_checking = "OFF",
Sync_FIFO.use_eab = "ON";
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND4BB_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__AND4BB_BEHAVIORAL_PP_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__and4bb (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nor nor0 (nor0_out , A_N, B_N );
and and0 (and0_out_X , nor0_out, C, D );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND4BB_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; const double pi = acos(-1.0); const double eps = 1e-11; template <class T> T sqr(const T &x) { return x * x; } template <class T> T lowbit(const T &x) { return (x ^ (x - 1)) & x; } inline long long mlog2(long long n) { long long c = 0; c += 64 - __builtin_clzll(n); return c - 1; } void fun(int a, int b) { for (b = 0; b < 5; b++) a++; } bool arr[15][15] = {0}; int k; bool check(int a, int b, int c, int d) { int i, j, tp = 0; for (i = a; i <= b; i++) for (j = c; j <= d; j++) { if (arr[i][j] == 1) tp++; if (tp >= k) return 1; } return 0; } int main() { int r, c, n, i, j, p, q, cou = 0, x, y; cin >> r >> c >> n >> k; for (i = 0; i < n; i++) { cin >> x >> y; x--; y--; arr[x][y] = 1; } for (i = 0; i < r; i++) { for (j = i; j < r; j++) { for (p = 0; p < c; p++) { for (q = p; q < c; q++) { if (check(i, j, p, q)) cou++; } } } } cout << cou; } |
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_timer_0 (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 15: 0] readdata;
input [ 2: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 15: 0] writedata;
wire clk_en;
wire control_continuous;
wire control_interrupt_enable;
reg [ 3: 0] control_register;
wire control_wr_strobe;
reg counter_is_running;
wire counter_is_zero;
wire [ 31: 0] counter_load_value;
reg [ 31: 0] counter_snapshot;
reg delayed_unxcounter_is_zeroxx0;
wire do_start_counter;
wire do_stop_counter;
reg force_reload;
reg [ 31: 0] internal_counter;
wire irq;
reg [ 15: 0] period_h_register;
wire period_h_wr_strobe;
reg [ 15: 0] period_l_register;
wire period_l_wr_strobe;
wire [ 15: 0] read_mux_out;
reg [ 15: 0] readdata;
wire snap_h_wr_strobe;
wire snap_l_wr_strobe;
wire [ 31: 0] snap_read_value;
wire snap_strobe;
wire start_strobe;
wire status_wr_strobe;
wire stop_strobe;
wire timeout_event;
reg timeout_occurred;
assign clk_en = 1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
internal_counter <= 32'hC34F;
else if (counter_is_running || force_reload)
if (counter_is_zero || force_reload)
internal_counter <= counter_load_value;
else
internal_counter <= internal_counter - 1;
end
assign counter_is_zero = internal_counter == 0;
assign counter_load_value = {period_h_register,
period_l_register};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
force_reload <= 0;
else if (clk_en)
force_reload <= period_h_wr_strobe || period_l_wr_strobe;
end
assign do_start_counter = start_strobe;
assign do_stop_counter = (stop_strobe ) ||
(force_reload ) ||
(counter_is_zero && ~control_continuous );
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter_is_running <= 1'b0;
else if (clk_en)
if (do_start_counter)
counter_is_running <= -1;
else if (do_stop_counter)
counter_is_running <= 0;
end
//delayed_unxcounter_is_zeroxx0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxcounter_is_zeroxx0 <= 0;
else if (clk_en)
delayed_unxcounter_is_zeroxx0 <= counter_is_zero;
end
assign timeout_event = (counter_is_zero) & ~(delayed_unxcounter_is_zeroxx0);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
timeout_occurred <= 0;
else if (clk_en)
if (status_wr_strobe)
timeout_occurred <= 0;
else if (timeout_event)
timeout_occurred <= -1;
end
assign irq = timeout_occurred && control_interrupt_enable;
//s1, which is an e_avalon_slave
assign read_mux_out = ({16 {(address == 2)}} & period_l_register) |
({16 {(address == 3)}} & period_h_register) |
({16 {(address == 4)}} & snap_read_value[15 : 0]) |
({16 {(address == 5)}} & snap_read_value[31 : 16]) |
({16 {(address == 1)}} & control_register) |
({16 {(address == 0)}} & {counter_is_running,
timeout_occurred});
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= read_mux_out;
end
assign period_l_wr_strobe = chipselect && ~write_n && (address == 2);
assign period_h_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
period_l_register <= 49999;
else if (period_l_wr_strobe)
period_l_register <= writedata;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
period_h_register <= 0;
else if (period_h_wr_strobe)
period_h_register <= writedata;
end
assign snap_l_wr_strobe = chipselect && ~write_n && (address == 4);
assign snap_h_wr_strobe = chipselect && ~write_n && (address == 5);
assign snap_strobe = snap_l_wr_strobe || snap_h_wr_strobe;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter_snapshot <= 0;
else if (snap_strobe)
counter_snapshot <= internal_counter;
end
assign snap_read_value = counter_snapshot;
assign control_wr_strobe = chipselect && ~write_n && (address == 1);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
control_register <= 0;
else if (control_wr_strobe)
control_register <= writedata[3 : 0];
end
assign stop_strobe = writedata[3] && control_wr_strobe;
assign start_strobe = writedata[2] && control_wr_strobe;
assign control_continuous = control_register[1];
assign control_interrupt_enable = control_register;
assign status_wr_strobe = chipselect && ~write_n && (address == 0);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__BUF_PP_SYMBOL_V
`define SKY130_FD_SC_MS__BUF_PP_SYMBOL_V
/**
* buf: Buffer.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__buf (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__BUF_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int t = 0; int d[300000]; int par[300000]; int t1[300000]; int t2[300000]; void dfs(int s, vector<vector<int> > &ed, int y) { d[s] = y; t1[s] = t++; for (int i = 0; i < ed[s].size(); i++) { if (ed[s][i] != par[s]) { par[ed[s][i]] = s; dfs(ed[s][i], ed, y + 1); } } t2[s] = t++; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n, m; cin >> n >> m; vector<vector<int> > v(n); int f, s; for (int i = 1; i < n; i++) { cin >> f >> s; f--; s--; v[f].push_back(s); v[s].push_back(f); } for (int i = 0; i < n; i++) { sort(v[i].begin(), v[i].end()); } par[0] = -1; dfs(0, v, 0); for (int i = 0; i < m; i++) { cin >> f; vector<int> h(f); for (int j = 0; j < f; j++) { cin >> h[j]; h[j]--; } int u = 0; for (int j = 0; j < f; j++) { if (d[h[j]] > d[u]) { u = h[j]; } } int flag = 1; for (int j = 0; j < f; j++) { if (!((t1[h[j]] <= t1[u] && t2[h[j]] >= t2[u]) || (t1[par[h[j]]] <= t1[u] && t2[par[h[j]]] >= t2[u]))) { flag = 0; break; } } if (flag == 0) { cout << NO n ; } else { cout << YES n ; } } return 0; } |
//Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module jaxa_statisticalInformation_1 (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 7: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 7: 0] data_out;
wire [ 7: 0] out_port;
wire [ 7: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[7 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
#include <bits/stdc++.h> using namespace std; inline int dblcmp(double x) { if (abs(x) < 1e-8) return 0; return (x > 0) ? 1 : -1; } inline double sqr(double x) { return x * x; } const double pi = acos(-1.0); struct point { double x, y; point() {} point(double _x, double _y) : x(_x), y(_y){}; void input() { scanf( %lf%lf , &x, &y); } void output() { printf( %.2f %.2f n , x, y); } bool operator==(point a) const { return dblcmp(a.x - x) == 0 && dblcmp(a.y - y) == 0; } bool operator<(point a) const { return dblcmp(a.x - x) == 0 ? dblcmp(y - a.y) < 0 : x < a.x; } double len() { return hypot(x, y); } double len2() { return x * x + y * y; } double distance(point p) { return hypot(x - p.x, y - p.y); } point add(point p) { return point(x + p.x, y + p.y); } point sub(point p) { return point(x - p.x, y - p.y); } point mul(double b) { return point(x * b, y * b); } point div(double b) { return point(x / b, y / b); } double dot(point p) { return x * p.x + y * p.y; } double det(point p) { return x * p.y - y * p.x; } double rad(point a, point b) { point p = *this; return fabs(atan2(fabs(a.sub(p).det(b.sub(p))), a.sub(p).dot(b.sub(p)))); } point trunc(double r) { double l = len(); if (!dblcmp(l)) return *this; r /= l; return point(x * r, y * r); } point rotleft() { return point(-y, x); } point rotright() { return point(y, -x); } point rotate(point p, double angle) { point v = this->sub(p); double c = cos(angle), s = sin(angle); return point(p.x + v.x * c - v.y * s, p.y + v.x * s + v.y * c); } }; struct line { point a, b; line() {} line(point _a, point _b) { a = _a; b = _b; } bool operator==(line v) { return (a == v.a) && (b == v.b); } line(point p, double angle) { a = p; if (dblcmp(angle - pi / 2) == 0) { b = a.add(point(0, 1)); } else { b = a.add(point(1, tan(angle))); } } line(double _a, double _b, double _c) { if (dblcmp(_a) == 0) { a = point(0, -_c / _b); b = point(1, -_c / _b); } else if (dblcmp(_b) == 0) { a = point(-_c / _a, 0); b = point(-_c / _a, 1); } else { a = point(0, -_c / _b); b = point(1, (-_c - _a) / _b); } } void input() { a.input(); b.input(); } void adjust() { if (b < a) swap(a, b); } double length() { return a.distance(b); } double angle() { double k = atan2(b.y - a.y, b.x - a.x); if (dblcmp(k) < 0) k += pi; if (dblcmp(k - pi) == 0) k -= pi; return k; } int relation(point p) { int c = dblcmp(p.sub(a).det(b.sub(a))); if (c < 0) return 1; if (c > 0) return 2; return 3; } bool pointonseg(point p) { return dblcmp(p.sub(a).det(b.sub(a))) == 0 && dblcmp(p.sub(a).dot(p.sub(b))) <= 0; } bool parallel(line v) { return dblcmp(b.sub(a).det(v.b.sub(v.a))) == 0; } int segcrossseg(line v) { int d1 = dblcmp(b.sub(a).det(v.a.sub(a))); int d2 = dblcmp(b.sub(a).det(v.b.sub(a))); int d3 = dblcmp(v.b.sub(v.a).det(a.sub(v.a))); int d4 = dblcmp(v.b.sub(v.a).det(b.sub(v.a))); if ((d1 ^ d2) == -2 && (d3 ^ d4) == -2) return 2; return (d1 == 0 && dblcmp(v.a.sub(a).dot(v.a.sub(b))) <= 0 || d2 == 0 && dblcmp(v.b.sub(a).dot(v.b.sub(b))) <= 0 || d3 == 0 && dblcmp(a.sub(v.a).dot(a.sub(v.b))) <= 0 || d4 == 0 && dblcmp(b.sub(v.a).dot(b.sub(v.b))) <= 0); } int linecrossseg(line v) { int d1 = dblcmp(b.sub(a).det(v.a.sub(a))); int d2 = dblcmp(b.sub(a).det(v.b.sub(a))); if ((d1 ^ d2) == -2) return 2; return (d1 == 0 || d2 == 0); } int linecrossline(line v) { if ((*this).parallel(v)) { return v.relation(a) == 3; } return 2; } point crosspoint(line v) { double a1 = v.b.sub(v.a).det(a.sub(v.a)); double a2 = v.b.sub(v.a).det(b.sub(v.a)); return point((a.x * a2 - b.x * a1) / (a2 - a1), (a.y * a2 - b.y * a1) / (a2 - a1)); } double dispointtoline(point p) { return fabs(p.sub(a).det(b.sub(a))) / length(); } double dispointtoseg(point p) { if (dblcmp(p.sub(b).dot(a.sub(b))) < 0 || dblcmp(p.sub(a).dot(b.sub(a))) < 0) { return min(p.distance(a), p.distance(b)); } return dispointtoline(p); } point lineprog(point p) { return a.add(b.sub(a).mul(b.sub(a).dot(p.sub(a)) / b.sub(a).len2())); } point symmetrypoint(point p) { point q = lineprog(p); return point(2 * q.x - p.x, 2 * q.y - p.y); } }; int N; line bas[110]; point ret[110]; int main() { scanf( %d , &N); if (N < 5) { puts( No solution ); return 0; } double minOO = 249.66 / tan(acos(-1.0) / N); double maxOO = 250.33 / tan(acos(-1.0) / N); int i; srand(23333); for (i = 1; i <= N; i++) { int factor = rand(); double len = (maxOO * factor + minOO * (32768 - factor)) / 32768; bas[i] = line(point(0, 0), point(len * cos(2 * pi / N * i), len * sin(2 * pi / N * i))); bas[i].a = bas[i].a.rotate(bas[i].b, pi / 2); } for (i = 1; i <= N; i++) { ret[i] = bas[i].crosspoint(bas[i % N + 1]); printf( %.6f %.6f n , ret[i].x, ret[i].y); } } |
////////////////////////////////////////////////////////////////////////////////
//
// Filename: firtap.v
//
// Project: DSP Filtering Example Project
//
// Purpose: Implements a single tap within a FIR filter. This particular
// FIR tap design is specifically designed to make it easier
// for the parent module to add (or remove) taps. Hence, by stringing
// N of these components together, an N tap filter can be created.
//
// This fir tap is a component of genericfir.v, the high speed (1-sample
// per clock, adjustable tap) FIR filter.
//
// Be aware, implementing a FIR tap in this manner can be a very expensive
// use of FPGA resources, very quickly necessitating a large FPGA for
// even the smallest (128 tap) filters.
//
// Resource usage may be minimized by minizing the number of taps,
// minimizing the number of bits in each tap, and/or the number of bits
// in the input (and output) samples.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2017-2018, Gisselquist Technology, LLC
//
// This file is part of the DSP filtering set of designs.
//
// The DSP filtering designs are free RTL designs: you can redistribute them
// and/or modify any of them under the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation, either version 3 of
// the License, or (at your option) any later version.
//
// The DSP filtering designs are distributed in the hope that they will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTIBILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser
// General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with these designs. (It's in the $(ROOT)/doc directory. Run make
// with no target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: LGPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/lgpl.html
//
////////////////////////////////////////////////////////////////////////////////
//
//
`default_nettype none
//
module firtap(i_clk, i_reset, i_tap_wr, i_tap, o_tap,
i_ce, i_sample, o_sample,
i_partial_acc, o_acc);
parameter IW=16, TW=IW, OW=IW+TW+8;
parameter [0:0] FIXED_TAPS=0;
parameter [(TW-1):0] INITIAL_VALUE=0;
//
input wire i_clk, i_reset;
//
input wire i_tap_wr;
input wire [(TW-1):0] i_tap;
output wire signed [(TW-1):0] o_tap;
//
input wire i_ce;
input wire signed [(IW-1):0] i_sample;
output wire [(IW-1):0] o_sample;
//
input wire [(OW-1):0] i_partial_acc;
output wire [(OW-1):0] o_acc;
//
reg [(IW-1):0] delayed_sample;
reg signed [(TW+IW-1):0] product;
// Determine the tap we are using
generate
if (FIXED_TAPS != 0)
// If our taps are fixed, the tap is given by the i_tap
// external input. This allows the parent module to be
// able to use readmemh to set all of the taps in a filter
assign o_tap = i_tap;
else begin
// If the taps are adjustable, then use the i_tap_wr signal
// to know when to adjust the tap. In this case, taps are
// strung together through the filter structure--our output
// tap becomes the input tap of the next tap module, and
// i_tap_wr causes all of them to shift forward by one.
reg [(TW-1):0] tap;
initial tap = INITIAL_VALUE;
always @(posedge i_clk)
if (i_tap_wr)
tap <= i_tap;
assign o_tap = tap;
end endgenerate
// Forward the sample on down the line, to be the input sample for the
// next component
initial o_sample = 0;
initial delayed_sample = 0;
always @(posedge i_clk)
if (i_reset)
begin
delayed_sample <= 0;
o_sample <= 0;
end else if (i_ce)
begin
// Note the two sample delay in this forwarding
// structure. This aligns the inputs up so that the
// accumulator structure (below) works.
delayed_sample <= i_sample;
o_sample <= delayed_sample;
end
`ifndef FORMAL
// Multiply the filter tap by the incoming sample
always @(posedge i_clk)
if (i_reset)
product <= 0;
else if (i_ce)
product <= o_tap * i_sample;
`else
wire [(TW+IW-1):0] w_pre_product;
abs_mpy #(.AW(TW), .BW(IW), .OPT_SIGNED(1'b1))
abs_bypass(i_clk, i_reset, o_tap, i_sample, w_pre_product);
initial product = 0;
always @(posedge i_clk)
if (i_reset)
product <= 0;
else if (i_ce)
product <= w_pre_product;
`endif
// Continue summing together the output components of the FIR filter
initial o_acc = 0;
always @(posedge i_clk)
if (i_reset)
o_acc <= 0;
else if (i_ce)
o_acc <= i_partial_acc
+ { {(OW-(TW+IW)){product[(TW+IW-1)]}},
product };
// Make verilator happy
// verilate lint_on UNUSED
wire unused;
assign unused = i_tap_wr;
// verilate lint_off UNUSED
endmodule
////////////////////////////////////////////////////////////////////////////////
//
// Filename: genericfir.v
//
// Project: DSP Filtering Example Project
//
// Purpose: Implement a high speed (1-output per clock), adjustable tap FIR
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2017-2018, Gisselquist Technology, LLC
//
// This file is part of the DSP filtering set of designs.
//
// The DSP filtering designs are free RTL designs: you can redistribute them
// and/or modify any of them under the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation, either version 3 of
// the License, or (at your option) any later version.
//
// The DSP filtering designs are distributed in the hope that they will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTIBILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser
// General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with these designs. (It's in the $(ROOT)/doc directory. Run make
// with no target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: LGPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/lgpl.html
//
////////////////////////////////////////////////////////////////////////////////
//
//
`default_nettype none
//
module genericfir(i_clk, i_reset, i_tap_wr, i_tap, i_ce, i_sample, o_result);
parameter NTAPS=128, IW=12, TW=IW, OW=2*IW+7;
parameter [0:0] FIXED_TAPS=0;
input wire i_clk, i_reset;
//
input wire i_tap_wr; // Ignored if FIXED_TAPS
input wire [(TW-1):0] i_tap; // Ignored if FIXED_TAPS
//
input wire i_ce;
input wire [(IW-1):0] i_sample;
output wire [(OW-1):0] o_result;
wire [(TW-1):0] tap [NTAPS:0];
wire [(TW-1):0] tapout [NTAPS:0];
wire [(IW-1):0] sample [NTAPS:0];
wire [(OW-1):0] result [NTAPS:0];
wire tap_wr;
// The first sample in our sample chain is the sample we are given
assign sample[0] = i_sample;
// Initialize the partial summing accumulator with zero
assign result[0] = 0;
genvar k;
generate
if(FIXED_TAPS)
begin
initial $readmemh("taps.hex", tap);
assign tap_wr = 1'b0;
end else begin
assign tap_wr = i_tap_wr;
assign tap[0] = i_tap;
end
for(k=0; k<NTAPS; k=k+1)
begin: FILTER
firtap #(.FIXED_TAPS(FIXED_TAPS),
.IW(IW), .OW(OW), .TW(TW),
.INITIAL_VALUE(0))
tapk(i_clk, i_reset,
// Tap update circuitry
tap_wr, tap[NTAPS-1-k], tapout[k],
// Sample delay line
i_ce, sample[k], sample[k+1],
// The output accumulator
result[k], result[k+1]);
if (!FIXED_TAPS)
assign tap[NTAPS-1-k] = tapout[k+1];
// Make verilator happy
// verilator lint_off UNUSED
wire [(TW-1):0] unused_tap;
if (FIXED_TAPS)
assign unused_tap = tapout[k];
// verilator lint_on UNUSED
end endgenerate
assign o_result = result[NTAPS];
// Make verilator happy
// verilator lint_off UNUSED
wire [(TW):0] unused;
assign unused = { i_tap_wr, i_tap };
// verilator lint_on UNUSED
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int cost(long long int x[], long long int a, long long int n, long long int r, long long int m, long long int val) { long long int pos = 0; long long int neg = 0; for (int i = 0; i < n; i++) { if (x[i] > val) pos += x[i] - val; else neg += val - x[i]; } if (a + r < m) return a * neg + r * pos; else { if (pos > neg) return neg * m + (pos - neg) * r; else return pos * m + (neg - pos) * a; } } long long int binary(long long int x[], long long int a, long long int n, long long int r, long long int m, long long int min, long long int max) { if (min > max) return -1; else { long long int mid = (min + max) / 2; long long int q = cost(x, a, n, r, m, mid); long long int w = cost(x, a, n, r, m, mid - 1); long long int e = cost(x, a, n, r, m, mid + 1); if (q <= w && q <= e) { return q; } else if (w > q && q > e) return binary(x, a, n, r, m, mid + 1, max); else return binary(x, a, n, r, m, min, mid - 1); } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int n, a, r, m; cin >> n >> a >> r >> m; long long int *x = new long long int[n]; long long int min = 100000001; long long int max = 0; for (int i = 0; i < n; i++) { cin >> x[i]; if (x[i] > max) max = x[i]; if (x[i] < min) min = x[i]; } long long int sum = binary(x, a, n, r, m, min, max); cout << sum << n ; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_BLACKBOX_V
`define SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_BLACKBOX_V
/**
* sleep_sergate_plv: connect vpr to virtpwr when not in sleep mode.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sleep_sergate_plv (
VIRTPWR,
SLEEP
);
output VIRTPWR;
input SLEEP ;
// Voltage supply signals
supply1 VPWR;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_BLACKBOX_V
|
`timescale 1ns/1ns
module axi_ms_tb;
reg clk, rst;
wire [31:0] ARADDR;
wire ARVALID;
wire ARREADY;
wire [7:0] ARLEN;
wire [2:0] ARSIZE;
wire RVALID;
wire [31:0] RDATA;
wire RREADY;
wire RLAST;
wire [31:0] AWADDR;
wire AWVALID;
wire AWREADY;
wire [7:0] AWLEN;
wire [2:0] AWSIZE;
wire WVALID;
wire WREADY;
wire [31:0] WDATA;
wire WLAST;
wire BVALID;
wire BREADY;
wire [1:0] BRESP;
initial begin
clk <= 0;
rst <= 1;
#15
rst <= ~rst;
#10000
$finish;
end
always begin
#10 clk = ~clk;
end
mod_main main_inst(.clk(clk), .rst(rst),
.a_ARADDR(ARADDR), .b_ARADDR(ARADDR),
.a_ARVALID(ARVALID),. b_ARVALID(ARVALID),
.a_ARREADY(ARREADY), .b_ARREADY(ARREADY),
.a_ARLEN(ARLEN), .b_ARLEN(ARLEN),
.a_ARSIZE(ARSIZE), .b_ARSIZE(ARSIZE),
.a_RVALID(RVALID), .b_RVALID(RVALID),
.a_RDATA(RDATA), .b_RDATA(RDATA),
.a_RREADY(RREADY), .b_RREADY(RREADY),
.a_RLAST(RLAST), .b_RLAST(RLAST),
.a_AWADDR(AWADDR), .b_AWADDR(AWADDR),
.a_AWVALID(AWVALID), .b_AWVALID(AWVALID),
.a_AWREADY(AWREADY), .b_AWREADY(AWREADY),
.a_AWLEN(AWLEN), .b_AWLEN(AWLEN),
.a_AWSIZE(AWSIZE), .b_AWSIZE(AWSIZE),
.a_WVALID(WVALID), .b_WVALID(WVALID),
.a_WREADY(WREADY), .b_WREADY(WREADY),
.a_WDATA(WDATA), .b_WDATA(WDATA),
.a_WLAST(WLAST), .b_WLAST(WLAST),
.a_BVALID(BVALID), .b_BVALID(BVALID),
.a_BREADY(BREADY), .b_BREADY(BREADY),
.a_BRESP(BRESP), .b_BRESP(BRESP)
);
endmodule // axi_ms_tb
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx_dp_maca_r.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of PCX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module pcx_dp_maca_r(/*AUTOARG*/
// Outputs
data_out_px_l, scan_out, shiftenable_buf,
// Inputs
arb_pcxdp_qsel1_pa, arb_pcxdp_qsel0_pa, arb_pcxdp_grant_pa,
arb_pcxdp_shift_px, arb_pcxdp_q0_hold_pa, src_pcx_data_pa, rclk,
scan_in, shiftenable
);
output [129:0] data_out_px_l; // pcx to destination pkt
output scan_out;
output shiftenable_buf;
input arb_pcxdp_qsel1_pa; // queue write sel
input arb_pcxdp_qsel0_pa; // queue write sel
input arb_pcxdp_grant_pa;//grant signal
input arb_pcxdp_shift_px;//grant signal
input arb_pcxdp_q0_hold_pa;//grant signal
input [129:0] src_pcx_data_pa; // spache to pcx data
input rclk;
//input tmb_l;
input scan_in;
input shiftenable;
wire grant_px;
wire [129:0] q0_datain_pa;
wire [129:0] q1_dataout, q0_dataout;
wire clkq0, clkq1;
reg clkenq0, clkenq1;
//HEADER SECTION
// Generate gated clocks for hold function
assign shiftenable_buf = shiftenable;
//replace tmb_l w/ ~se
wire se_l ;
assign se_l = ~shiftenable ;
clken_buf ck0 (
.clk (clkq0),
.rclk (rclk),
.enb_l(~arb_pcxdp_q0_hold_pa),
.tmb_l(se_l));
clken_buf ck1 (
.clk (clkq1),
.rclk (rclk),
.enb_l(~arb_pcxdp_qsel1_pa),
.tmb_l(se_l));
// Latch and drive grant signal
dff_s #(1) dff_pcx_grin_r(
.din (arb_pcxdp_grant_pa),
.q (grant_px),
.clk (rclk),
.se (1'b0),
.si (1'b0),
.so ());
//DATAPATH SECTION
dff_s #(130) dff_pcx_datain_q1(
.din (src_pcx_data_pa[129:0]),
.q (q1_dataout[129:0]),
.clk (clkq1),
.se (1'b0),
.si (),
.so ());
assign q0_datain_pa[129:0] =
(arb_pcxdp_qsel0_pa ? src_pcx_data_pa[129:0] : 130'd0) |
(arb_pcxdp_shift_px ? q1_dataout[129:0] : 130'd0) ;
dff_s #(130) dff_pcx_datain_q0(
.din (q0_datain_pa[129:0]),
.q (q0_dataout[129:0]),
.clk (clkq0),
.se (1'b0),
.si (),
.so ());
assign data_out_px_l[129:0] = ~(grant_px ? q0_dataout[129:0]:130'd0);
// Global Variables:
// verilog-library-directories:("." "../../../../../common/rtl" "../rtl")
// End:
// Code start here
//
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tmu2_alpha #(
parameter fml_depth = 26
) (
input sys_clk,
input sys_rst,
output busy,
input [5:0] alpha,
input pipe_stb_i,
output pipe_ack_o,
input [15:0] color,
input [fml_depth-1-1:0] dadr, /* in 16-bit words */
input [15:0] dcolor,
output pipe_stb_o,
input pipe_ack_i,
output reg [fml_depth-1-1:0] dadr_f,
output [15:0] acolor
);
wire en;
reg valid_1;
reg valid_2;
reg valid_3;
always @(posedge sys_clk) begin
if(sys_rst) begin
valid_1 <= 1'b0;
valid_2 <= 1'b0;
valid_3 <= 1'b0;
end else if(en) begin
valid_1 <= pipe_stb_i;
valid_2 <= valid_1;
valid_3 <= valid_2;
end
end
/* Pipeline operation on three stages. */
reg [fml_depth-1-1:0] dadr_1;
reg [fml_depth-1-1:0] dadr_2;
wire [4:0] r = color[15:11];
wire [5:0] g = color[10:5];
wire [4:0] b = color[4:0];
wire [4:0] dr = dcolor[15:11];
wire [5:0] dg = dcolor[10:5];
wire [4:0] db = dcolor[4:0];
reg [10:0] r_1;
reg [11:0] g_1;
reg [10:0] b_1;
reg [10:0] dr_1;
reg [11:0] dg_1;
reg [10:0] db_1;
reg [10:0] r_2;
reg [11:0] g_2;
reg [10:0] b_2;
reg [10:0] dr_2;
reg [11:0] dg_2;
reg [10:0] db_2;
reg [10:0] r_3;
reg [11:0] g_3;
reg [10:0] b_3;
always @(posedge sys_clk) begin
if(en) begin
dadr_1 <= dadr;
dadr_2 <= dadr_1;
dadr_f <= dadr_2;
r_1 <= ({1'b0, alpha} + 7'd1)*r;
g_1 <= ({1'b0, alpha} + 7'd1)*g;
b_1 <= ({1'b0, alpha} + 7'd1)*b;
dr_1 <= (6'd63 - alpha)*dr;
dg_1 <= (6'd63 - alpha)*dg;
db_1 <= (6'd63 - alpha)*db;
r_2 <= r_1;
g_2 <= g_1;
b_2 <= b_1;
dr_2 <= dr_1;
dg_2 <= dg_1;
db_2 <= db_1;
r_3 <= r_2 + dr_2;
g_3 <= g_2 + dg_2;
b_3 <= b_2 + db_2;
end
end
assign acolor = {r_3[10:6], g_3[11:6], b_3[10:6]};
/* Pipeline management */
assign busy = valid_1 | valid_2 | valid_3;
assign pipe_ack_o = ~valid_3 | pipe_ack_i;
assign en = ~valid_3 | pipe_ack_i;
assign pipe_stb_o = valid_3;
endmodule
|
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:32:05 11/08/2015
// Design Name:
// Module Name: jace_logic
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module jace_logic (
input wire clk,
// CPU interface
input wire [15:0] cpu_addr,
input wire mreq_n,
input wire iorq_n,
input wire rd_n,
input wire wr_n,
input wire [7:0] data_from_cpu,
output reg [7:0] data_to_cpu,
output reg data_to_cpu_oe,
output reg wait_n,
output wire int_n,
// CPU-RAM interface
output reg rom_enable,
output reg sram_enable,
output reg cram_enable,
output reg uram_enable,
output reg xram_enable,
output reg eram_enable,
// Screen RAM and Char RAM interface
output wire [9:0] screen_addr,
input wire [7:0] screen_data,
output wire [9:0] char_addr,
input wire [7:0] char_data,
// Devices
input wire [4:0] kbdcols,
input wire ear,
output reg spk,
output reg mic,
output wire video,
output wire hsync_pal,
output wire vsync_pal
);
initial begin
wait_n = 1'b1;
spk = 1'b0;
mic = 1'b0;
end
reg [8:0] cntpix = 9'd0;
reg [8:0] cntscn = 9'd0;
wire [17:0] cnt = {cntscn, cntpix};
always @(posedge clk) begin
if (cntpix != 9'd415)
cntpix <= cntpix + 9'd1;
else begin
cntpix <= 9'd0;
if (cntscn != 9'd311)
cntscn <= cntscn + 9'd1;
else
cntscn <= 9'd0;
end
end
reg vsync; // FIELD signal in schematic
always @* begin
if (cntscn >= 9'd248 && cntscn <= 9'd255)
vsync = 1'b0;
else
vsync = 1'b1;
end
assign int_n = vsync;
reg hsync; // LINE signal in schematic
always @* begin
if (cntpix >= 9'd320 && cntpix <= 9'd351)
hsync = 1'b0;
else
hsync = 1'b1;
end
//assign csync = hsync & vsync;
assign hsync_pal = hsync;
assign vsync_pal = vsync;
reg viden; // VIDEN signal in schematic
always @* begin
if (cntpix >= 9'd0 && cntpix <= 9'd255 &&
cntscn >= 9'd0 && cntscn <= 9'd191)
viden = 1'b1;
else
viden = 1'b0;
end
// SHIFT/LOAD signal to 74LS166
reg shiftload;
always @* begin
if (cnt[2:0] == 3'b000 && viden == 1'b1)
shiftload = 1'b1;
else
shiftload = 1'b0;
end
assign screen_addr = {cnt[16:12], cnt[7:3]};
assign char_addr = {screen_data[6:0], cnt[11:9]};
// 74LS166
reg [7:0] shiftreg = 8'h00;
always @(posedge clk) begin
if (shiftload == 1'b1)
shiftreg <= char_data;
else
shiftreg <= {shiftreg[6:0], 1'b0};
end
// Pixel inverter reg and video output stage
reg pixinverter = 1'b0;
always @(posedge clk) begin
if (cnt[2:0] == 3'b000)
pixinverter <= viden & screen_data[7];
end
assign video = shiftreg[7] ^ pixinverter;
// Address decoder
reg fast_access;
always @* begin
rom_enable = 1'b0;
sram_enable = 1'b0;
cram_enable = 1'b0;
uram_enable = 1'b0;
xram_enable = 1'b0;
eram_enable = 1'b0;
fast_access = 1'b1;
if (mreq_n == 1'b0) begin
if (cpu_addr >= 16'h0000 && cpu_addr <= 16'h1FFF)
rom_enable = 1'b1;
else if (cpu_addr >= 16'h2000 && cpu_addr <= 16'h27FF) begin
sram_enable = 1'b1;
if (cpu_addr >= 16'h2400 && cpu_addr <= 16'h27FF)
fast_access = 1'b0;
end
else if (cpu_addr >= 16'h2800 && cpu_addr <= 16'h2FFF) begin
cram_enable = 1'b1;
if (cpu_addr >= 16'h2C00 && cpu_addr <= 16'h2FFF)
fast_access = 1'b0;
end
else if (cpu_addr >= 16'h3000 && cpu_addr <= 16'h3FFF)
uram_enable = 1'b1;
else if (cpu_addr >= 16'h4000 && cpu_addr <= 16'h7FFF)
xram_enable = 1'b1;
else
eram_enable = 1'b1;
end
end
// CPU arbitration to share memory with video generator
always @(posedge clk) begin
if ((sram_enable == 1'b1 || cram_enable == 1'b1) && viden == 1'b1 && fast_access == 1'b0)
wait_n <= 1'b0;
else if (viden == 1'b0)
wait_n <= 1'b1;
end
// IO devices
always @* begin
data_to_cpu_oe = 1'b0;
data_to_cpu = {2'b11, ear, kbdcols};
if (iorq_n == 1'b0 && cpu_addr[0] == 1'b0 && rd_n == 1'b0) begin
data_to_cpu_oe = 1'b1;
end
end
always @(posedge clk) begin
if (iorq_n == 1'b0 && cpu_addr[0] == 1'b0) begin
if (rd_n == 1'b0 && wr_n == 1'b1)
spk <= 1'b0;
else if (rd_n == 1'b1 && wr_n == 1'b0)
spk <= 1'b1;
if (wr_n == 1'b0)
mic <= data_from_cpu[3];
end
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: cpx_datacx2_ff.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module cpx_datacx2_ff(/*AUTOARG*/
// Outputs
cpx_spc_data_cx2, cpx_spc_data_rdy_cx2, so,
// Inputs
cpx_spc_data_cx_l, cpx_spc_data_rdy_cx, rclk, si, se
);
output [`CPX_WIDTH-1:0] cpx_spc_data_cx2;
output cpx_spc_data_rdy_cx2;
output so;
input [`CPX_WIDTH-1:0] cpx_spc_data_cx_l;
input cpx_spc_data_rdy_cx;
input rclk;
input si;
input se;
wire [`CPX_WIDTH-1:0] cpx_spc_data_cx2_l;
dff_s #(`CPX_WIDTH) dff_ccx_data_spc(
.din (cpx_spc_data_cx_l[`CPX_WIDTH-1:0]),
.q (cpx_spc_data_cx2_l[`CPX_WIDTH-1:0]),
.clk (rclk),
.se (1'b0),
.si (`CPX_WIDTH'd0),
.so ());
assign cpx_spc_data_cx2 = ~cpx_spc_data_cx2_l;
dff_s #(1) dff_ccx_datardy_spc(
.din (cpx_spc_data_rdy_cx),
.q (cpx_spc_data_rdy_cx2),
.clk (rclk),
.se (1'b0),
.si (1'd0),
.so ());
endmodule // cpx_grant_ff
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2016 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file dataMemory.v when simulating
// the core, dataMemory. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module dataMemory(
clka,
rsta,
ena,
wea,
addra,
dina,
douta
);
input clka;
input rsta;
input ena;
input [3 : 0] wea;
input [31 : 0] addra;
input [31 : 0] dina;
output [31 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(32),
.C_ADDRB_WIDTH(32),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(8),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(1),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(1),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(1),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("dataMemory.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(0),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(64),
.C_READ_DEPTH_B(64),
.C_READ_WIDTH_A(32),
.C_READ_WIDTH_B(32),
.C_RST_PRIORITY_A("SR"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(1),
.C_USE_BYTE_WEB(1),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(4),
.C_WEB_WIDTH(4),
.C_WRITE_DEPTH_A(64),
.C_WRITE_DEPTH_B(64),
.C_WRITE_MODE_A("READ_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.RSTA(rsta),
.ENA(ena),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.REGCEA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
//
// bv_count module
//
// bv2.0_programmable
//
// Created by LiJunnan on 16/9/16.
// Copyright (c) 2016year LiJunnan. All rights reserved.
`timescale 1ns/1ps
module bv_count(
reset,
clk,
bv_valid,
bv,
count,
bv_out_valid,
bv_out,
count_out
);
parameter width = 64;
parameter width_count = 6;
parameter stage = 1;
parameter range_end = 1;
input reset;
input clk;
input bv_valid;
input [width-1:0] bv;
input [width_count-1:0] count;
output reg bv_out_valid;
output reg [width-1:0] bv_out;
output reg [width_count-1:0] count_out;
always @ (posedge clk)begin
if(bv_valid == 1'b1)begin
bv_out_valid <= 1'b1;
if(bv[range_end-1:0])begin
bv_out <= bv;
count_out <= count;
end
else begin
bv_out <= bv >> range_end;
count_out <= count + range_end;
end
end
else begin
bv_out_valid <= 1'b0;
bv_out <= {width{1'b0}};
count_out <= {width_count{1'b0}};
end
end
endmodule
|
/**
Based on: https://github.com/dirjud/Nitro-Parts-lib-Xilinx
*/
`timescale 1ps/1ps
`default_nettype none
module clock_divider_sim #(
parameter DIVISOR = 2
) (
input wire CLK,
output reg CLOCK
);
integer cnt;
initial cnt = 0;
wire [31:0] DIV;
assign DIV = DIVISOR;
always @(posedge CLK)
if(cnt == DIVISOR -1)
cnt <= 0;
else
cnt <= cnt + 1;
initial CLOCK = 0;
always @(posedge CLK or negedge CLK) begin
if(cnt == DIVISOR-1 && CLK == 1'b1) // posedge
CLOCK <= 1;
else if (cnt == DIVISOR/2-1 && DIV[0] == 0 && CLK == 1'b1) // posedge
CLOCK <= 0;
else if (cnt == DIVISOR/2 && DIV[0] == 1 && CLK == 1'b0) // negedge
CLOCK <= 0;
end
endmodule
module DCM #(
parameter CLKFX_MULTIPLY = 4,
parameter CLKFX_DIVIDE = 1,
parameter CLKDV_DIVIDE = 2,
parameter CLKIN_PERIOD = 10,
parameter CLK_FEEDBACK = 0,
parameter CLKOUT_PHASE_SHIFT = 0,
parameter CLKIN_DIVIDE_BY_2 = "FALSE",
parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS",
parameter DFS_FREQUENCY_MODE = "LOW",
parameter DLL_FREQUENCY_MODE = "LOW",
parameter DUTY_CYCLE_CORRECTION = "TRUE",
parameter FACTORY_JF = 16'hC080,
parameter PHASE_SHIFT = 0,
parameter STARTUP_WAIT = "TRUE"
) (
CLK0,
CLK180,
CLK270,
CLK2X,
CLK2X180,
CLK90,
CLKDV,
CLKFX,
CLKFX180,
LOCKED,
PSDONE,
STATUS,
CLKFB,
CLKIN,
DSSEN,
PSCLK,
PSEN,
PSINCDEC,
RST
);
input wire CLKFB, CLKIN, DSSEN;
input wire PSCLK, PSEN, PSINCDEC, RST;
output wire CLKDV, CLKFX, CLKFX180, LOCKED, PSDONE;
output wire CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90;
output wire [7:0] STATUS;
assign STATUS = 0;
assign CLK0 = CLKIN;
assign CLK180 = ~CLKIN;
assign CLK270 = ~CLK90;
assign CLK2X180 = ~CLK2X;
assign CLKFX180 = ~CLKFX;
wire resetb = ~RST;
wire clk2x;
clock_multiplier #(
.MULTIPLIER(2)
) i_clock_multiplier_two(
.CLK(CLKIN),
.CLOCK(clk2x)
);
reg clk90;
reg [1:0] cnt;
always @(posedge clk2x or negedge clk2x or negedge resetb) begin
if (!resetb) begin
clk90 <= 0;
cnt <= 0;
end else begin
cnt <= cnt + 1;
if (!cnt[0]) clk90 <= ~clk90;
end
end
assign CLK2X = clk2x;
assign CLK90 = clk90;
generate
if (CLKFX_MULTIPLY==2 && CLKFX_DIVIDE==1) begin
assign CLKFX = clk2x;
end else begin
wire CLKINM;
clock_multiplier #( .MULTIPLIER(CLKFX_MULTIPLY) ) i_clock_multiplier(.CLK(CLKIN),.CLOCK(CLKINM));
clock_divider_sim #(.DIVISOR(CLKFX_DIVIDE)) i_clock_divisor_rx (.CLK(CLKINM), .CLOCK(CLKFX));
end
endgenerate
clock_divider_sim #(
.DIVISOR(CLKDV_DIVIDE)
) i_clock_divisor_dv (
.CLK(CLKIN),
.CLOCK(CLKDV)
);
assign LOCKED = 1'b1;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, r, x, s = 0; cin >> n >> r >> x; int a[r + 1]; for (int i = 1; i <= r; i++) { a[i] = 10000000; } while (n--) { int l, m; cin >> l >> m; a[l] = min(a[l], m); } for (int i = 1; i <= r; i++) { s += a[i]; } cout << min(s, x); return 0; } |
#include <bits/stdc++.h> using namespace std; long long findGCD(long long a, long long b) { return ((b == 0) ? a : findGCD(b, a % b)); } map<long long, long long> width; long long wit = 0; vector<pair<long long, long long> > rect[200005]; int main() { long long n; scanf( %lld , &n); for (long long i = (1); i <= (n); i += (1)) { long long w, h, f; scanf( %lld %lld %lld , &h, &w, &f); if (width.find(w) == width.end()) { width[w] = ++wit; } rect[width[w]].push_back({h, f}); } sort(rect[1].begin(), rect[1].end()); for (long long i = (2); i <= (wit); i += (1)) { if (rect[i - 1].size() != rect[i].size()) { printf( 0 n ); return 0; } sort(rect[i].begin(), rect[i].end()); for (long long j = (0); j <= ((long long)rect[i].size() - 1); j += (1)) { if (rect[i - 1][j].first != rect[i][j].first) { printf( 0 n ); return 0; } } long long gcd = findGCD(rect[i - 1][0].second, rect[i][0].second); long long n = rect[i - 1][0].second / gcd, dn = rect[i][0].second / gcd; for (long long j = (1); j <= ((long long)rect[i].size() - 1); j += (1)) { gcd = findGCD(rect[i - 1][j].second, rect[i][j].second); if (rect[i - 1][j].second / gcd != n || rect[i][j].second / dn != gcd) { printf( 0 n ); return 0; } } } long long tgcd = -1; for (long long j = (0); j <= ((long long)rect[1].size() - 1); j += (1)) { long long gcd = rect[1][j].second; for (long long i = (2); i <= (wit); i += (1)) { gcd = findGCD(gcd, rect[i][j].second); } if (tgcd == -1) tgcd = gcd; else tgcd = findGCD(tgcd, gcd); } long long ans = 0; for (long long i = (1); i <= (sqrt(tgcd)); i += (1)) { if (tgcd % i == 0) { if (tgcd == i * i) ans++; else ans += 2; } } printf( %lld n , ans); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MUX2_PP_SYMBOL_V
`define SKY130_FD_SC_HD__MUX2_PP_SYMBOL_V
/**
* mux2: 2-input multiplexer.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__mux2 (
//# {{data|Data Signals}}
input A0 ,
input A1 ,
output X ,
//# {{control|Control Signals}}
input S ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__MUX2_PP_SYMBOL_V
|
module module2(clk_, rst_, bar0, bar1, foo0, foo1);
input clk_;
input rst_;
input [1:0] bar0;
input [1:0] bar1;
output [1:0] foo0;
output [1:0] foo1;
parameter poser_tied = 1'b1;
parameter poser_width_in = 0+1-0+1+1-0+1;
parameter poser_width_out = 0+1-0+1+1-0+1;
parameter poser_grid_width = 5;
parameter poser_grid_depth = 9;
parameter [poser_grid_width-1:0] cellTypes [0:poser_grid_depth-1] = '{ 5'b11111,5'b11111,5'b11111,5'b11111,5'b11111,5'b11111,5'b11111,5'b11111,5'b11111 };
wire [poser_width_in-1:0] poser_inputs;
assign poser_inputs = { bar0,bar1 };
wire [poser_width_out-1:0] poser_outputs;
assign { foo0,foo1 } = poser_outputs;
wire [poser_grid_width-1:0] poser_grid_output [0:poser_grid_depth-1];
wire poser_clk;
assign poser_clk = clk_;
wire poser_rst;
assign poser_rst = rst_;
for (genvar D = 0; D < poser_grid_depth; D++) begin
for (genvar W = 0; W < poser_grid_width; W++) begin
if (D == 0) begin
if (W == 0) begin
poserCell #(.cellType(cellTypes[D][W]), .activeRst(0)) pc (.clk(poser_clk),
.rst(poser_rst),
.i(^{ poser_tied ,
poser_inputs[W%poser_width_in] }),
.o(poser_grid_output[D][W]));
end else begin
poserCell #(.cellType(cellTypes[D][W]), .activeRst(0)) pc (.clk(poser_clk),
.rst(poser_rst),
.i(^{ poser_grid_output[D][W-1],
poser_inputs[W%poser_width_in] }),
.o(poser_grid_output[D][W]));
end
end else begin
if (W == 0) begin
poserCell #(.cellType(cellTypes[D][W]), .activeRst(0)) pc (.clk(poser_clk),
.rst(poser_rst),
.i(^{ poser_grid_output[D-1][W],
poser_grid_output[D-1][poser_grid_depth-1] }),
.o(poser_grid_output[D][W]));
end else begin
poserCell #(.cellType(cellTypes[D][W]), .activeRst(0)) pc (.clk(poser_clk),
.rst(poser_rst),
.i(^{ poser_grid_output[D-1][W],
poser_grid_output[D][W-1] }),
.o(poser_grid_output[D][W]));
end
end
end
end
generate
if (poser_width_out == 1) begin
poserMux #(.poser_mux_width_in(poser_grid_width)) pm (.i(poser_grid_output[poser_grid_depth-1]),
.o(poser_outputs));
end
else if (poser_grid_width == poser_width_out) begin
assign poser_outputs = poser_grid_output[poser_grid_depth-1];
end
else if (poser_grid_width > poser_width_out) begin
wire [poser_grid_width-1:0] poser_grid_output_last;
assign poser_grid_output_last = poser_grid_output[poser_grid_depth-1];
poserMux #(.poser_mux_width_in((poser_grid_width - poser_width_out) + 1)) pm (.i(poser_grid_output_last[poser_grid_width-1:poser_width_out-1]),
.o(poser_outputs[poser_width_out-1]));
assign poser_outputs[poser_width_out-2:0] = poser_grid_output_last[poser_width_out-2:0];
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int i, t, m, n; cin >> t; int arr[t]; for (i = 0; i < t; i++) { int sum = 0, k = 0; cin >> n >> m; int arr1[n]; for (int j = 0; j < n; j++) { cin >> arr1[j]; if (j != 0) sum += arr1[j]; } k = arr1[0]; while (k < m) { if (sum != 0) { k++; sum--; } else break; } arr[i] = k; } for (i = 0; i < t; i++) cout << arr[i] << n ; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:09:39 08/25/2015
// Design Name:
// Module Name: FSM_Add_Subtract
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FSM_Add_Subtract
(
//INPUTS
input wire clk, //system clock
input wire rst, //system reset
input wire rst_FSM,
input wire beg_FSM, //Begin Finite State Machine
//**REVISAD
//////////////////////////////////////////////////////////////////////////////
//Oper_Start_In evaluation signals
input wire zero_flag_i,
//Exp_operation evaluation signals
input wire norm_iteration_i,
//Barrel_Shifter evaluation signals
//None
//Add_Subt_Sgf evaluation signals
input wire add_overflow_i,
//LZA evaluation signals
//None
//Deco_round evaluation Signals
input wire round_i,
//Final_result evaluation signals
//None
//OUTPUT SIGNALS
////////////////////////////////////////////////////////////////////////////////////
//Oper_Start_In control signals
output wire load_1_o,//Enable input registers
output wire load_2_o,//Enable output registers
//Exp_operation control signals
output reg load_3_o, //Enable Output registers
output reg load_8_o,
output reg A_S_op_o, //Select operation for exponent normalization(Subt for left shift, Add for right shift)
//Barrel shifter control signals
output reg load_4_o, //Enable Output registers
output reg left_right_o, //Select direction shift (right=0, left=1)
output reg bit_shift_o, //bit input for shifts fills
//Add_Subt_sgf control signals
output reg load_5_o, //Enables Output registers
//LZA control signals
output reg load_6_o, //Enables Output registers
//Deco_Round control signals
//None
//Final_Result control signals
output reg load_7_o,
///////////////////////////////\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
//Multiplexer selector for Exp_operation's OPER_A
output reg ctrl_a_o,
//Multiplexer selector for Exp_operation's OPER_B & Barrel_Shifter's Shift value
output reg [1:0] ctrl_b_o,
output reg ctrl_b_load_o,
//Multiplexer selector for Data shift
output reg ctrl_c_o,
//Multiplexer selector for Add_Subt_Sgf's inputs
output reg ctrl_d_o,
//Internal reset signal
output reg rst_int,
//Ready Signal
output reg ready
);
localparam [3:0]
//First I'm going to declarate the registers of the first phase of execution
start = 4'd0, //This state evaluates the beg_FSM to begin operations
load_oper = 4'd1, //This state enables the registers that contains
//both operands and the operator
zero_info_state = 4'd2, //Evaluate zero condition
load_diff_exp = 4'd3, //Enable registers for the exponent on the small value normalization and for the first
//result normalization
extra1_64= 4'd4,
norm_sgf_first= 4'd5, //Enable the barrel shifter's registers and evaluate if it's the first time (small operand) or the
//second time (result normalization)
add_subt = 4'd6, //Enable the add_subt_sgf's registers
add_subt_r = 4'd7, //Enable the add_subt_sgf's registers for round condition
overflow_add = 4'd8,
round_sgf = 4'd9, //Evaluate the significand round condition
overflow_add_r = 4'd10,
extra2_64= 4'd11, //Enable registers for the exponent normalization on round condition
norm_sgf_r = 4'd12, //Enable the barrel shifter's registers for round condition
load_final_result = 4'd13, //Load the final_result's register with the result
ready_flag = 4'd14; //Enable the ready flag with the final result
//**********************REVISADO
reg [3:0] state_reg, state_next ; //state registers declaration
////////////////////////Logic outputs///////////////77
assign load_1_o= (state_reg==load_oper);
assign load_2_o= (state_reg==zero_info_state);
////
always @(posedge clk, posedge rst)
if (rst) begin
state_reg <= start;
end
else begin
state_reg <= state_next;
end
///
always @*
begin
state_next = state_reg;
rst_int = 0;
//Oper_Start_In control signals
//load_1_o=0;
//load_2_o=0;
//Exp_operation control signals
load_3_o=0;
load_8_o=0;
A_S_op_o=1;
//Barrel shifter control signals
load_4_o=0;
left_right_o=0;
bit_shift_o=0; //bit input for shifts fills
//Add_Subt_sgf control signals
load_5_o=0;
//LZA control signals
load_6_o=0;
//Deco_Round control signals
//None
//Final_Result control signals
load_7_o=0;
///////////////////////////////\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
//Multiplexer selector for Exp_operation's OPER_A
ctrl_a_o=0;
//Multiplexer selector for Exp_operation's OPER_B
ctrl_b_o=2'b00;
ctrl_b_load_o=0;
//Multiplexer selector for Barrel_Shifter's Data shift
ctrl_c_o=0;
//Multiplexer selector for Barrel_Shifter's Shift value
//Multiplexer selector for Add_Subt_Sgf's inputs
ctrl_d_o=0;
//Ready Phase
ready = 0;
//**REVISADO
rst_int = 0;
case(state_reg)
//FPU reset
start: begin
rst_int=1;
if(beg_FSM) begin
state_next = load_oper;
end
end
load_oper: //Load input registers for Oper_star in evaluation
begin
// load_1_o = 1;
state_next = zero_info_state;
end
zero_info_state: //In case of zero condition, go to final result for ready flag. Else, continue with the calculation
begin
if (zero_flag_i)begin
state_next = ready_flag;end
else begin
//load_2_o = 1;
state_next = load_diff_exp;end
end
load_diff_exp: //in first instance, Calculate DMP - DmP exponents, in other iteration, evaluation in
begin
load_3_o = 1;
/*
if ()*/
state_next = extra1_64;
end
extra1_64:
begin
load_3_o = 1;
if (norm_iteration_i)begin
load_8_o=1;
if(add_overflow_i)begin
A_S_op_o=0;
left_right_o=0;
bit_shift_o=1;
end
else begin
A_S_op_o=1;
left_right_o=1;
bit_shift_o=0;
end
end
state_next = norm_sgf_first;
end
norm_sgf_first: //
begin
load_4_o = 1;
if (norm_iteration_i)begin
if(add_overflow_i)begin
left_right_o=0;
bit_shift_o=1;
state_next = round_sgf;
end
else begin
left_right_o=1;
bit_shift_o=0;
state_next = round_sgf;end
end
else
state_next = add_subt;
end
add_subt:
begin
//Reg enables
load_5_o = 1;
ctrl_c_o = 1;
state_next = overflow_add;
end
overflow_add:
begin
//Reg enables/Disables
load_6_o=1;
ctrl_b_load_o=1;
if ( add_overflow_i)begin
ctrl_b_o=2'b10;
end
else begin
A_S_op_o=1;
ctrl_b_o=2'b01;
end
//state_next = load_exp_oper_over;
state_next = extra1_64;
end
round_sgf:
begin
load_4_o = 0;
if(round_i) begin
ctrl_d_o =1;
ctrl_a_o = 1;
state_next = add_subt_r; end
else begin
state_next = load_final_result; end
end
add_subt_r:
begin
load_5_o = 1;
state_next = overflow_add_r;
end
overflow_add_r:
begin
ctrl_b_load_o=1;
if ( add_overflow_i)begin
ctrl_b_o=2'b10;
end
else begin
ctrl_b_o=2'b11;
end
state_next = extra2_64;
end
extra2_64:
begin
load_3_o = 1;
load_8_o = 1;
if ( add_overflow_i)begin
A_S_op_o=0;
bit_shift_o=1;
end
state_next = norm_sgf_r;
end
norm_sgf_r:
begin
load_4_o = 1;
if ( add_overflow_i)begin
left_right_o=0;
bit_shift_o=1;
end
state_next = load_final_result;
end
load_final_result:
begin
load_7_o = 1;
state_next = ready_flag;
end
ready_flag:
begin
ready = 1;
if(rst_FSM) begin
state_next = start;end
end
default:
begin
state_next =start;end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXL = 1e5; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; long long int k, p; long long int ans = 0; cin >> k >> p; for (int i = 1; i <= k; i++) { int x = i; string str1, str2; while (x) { str1 += (x % 10 + 0 ); x /= 10; } for (int j = str1.size() - 1; j >= 0; j--) str2 += str1[j]; str2 += str1; long long int sum = 0; for (int j = 0; j < str2.size(); j++) sum = sum * 10 + str2[j] - 0 ; ans = (ans + sum) % p; } cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1000005, mod = 1000000007; vector<int> pri; bool vis[80]; int pos[80], a[maxn], n; long long w[80]; long long dp[1 << 21], dp2[1 << 21], f[maxn]; void prework() { for (int i = 2; i < (71); ++i) { if (!vis[i]) { pri.push_back(i); pos[i] = (int)pri.size() - 1; for (int j = i; j <= 70; j += i) vis[j] = 1; } } f[0] = 1; for (int i = 1; i < (maxn); ++i) f[i] = 2 * f[i - 1] % mod; } void init() { scanf( %d , &n); for (int i = 0; i < (n); ++i) { scanf( %d , &a[i]); w[a[i]]++; } } int gao(int n) { int tmp[30] = {0}; for (int i = 2; i <= n; ++i) { while (n % i == 0) { n /= i; tmp[pos[i]] ^= 1; } } if (n > 1) tmp[pos[n]] ^= 1; int res = 0; for (int i = 0; i < (21); ++i) if (tmp[i]) res |= (1 << i); return res; } inline int get_nx(int st1, int st2) { return st1 ^ st2; } void solve() { dp[0] = 1; for (int i = 2; i < (71); ++i) { if (!w[i]) continue; int st = gao(i); for (int pre = 0; pre < (1 << 19); ++pre) { int nx_st = get_nx(st, pre); dp2[nx_st] += dp[pre] * f[w[i] - 1] % mod; dp2[pre] += dp[pre] * f[w[i] - 1] % mod; dp2[nx_st] %= mod; dp2[pre] %= mod; } for (int k = 0; k < (1 << 19); ++k) dp[k] = dp2[k], dp2[k] = 0; } long long ans = dp[0] - 1; if (w[1]) ans = (f[w[1]]) * ans % mod + f[w[1]] - 1; cout << ans % mod << endl; } int main() { prework(); init(); solve(); } |
#include <bits/stdc++.h> using namespace std; void __print(int x) {cerr << x;} void __print(long x) {cerr << x;} void __print(long long x) {cerr << x;} void __print(unsigned x) {cerr << x;} void __print(unsigned long x) {cerr << x;} void __print(unsigned long long x) {cerr << x;} void __print(float x) {cerr << x;} void __print(double x) {cerr << x;} void __print(long double x) {cerr << x;} void __print(char x) {cerr << << x << ;} void __print(const char *x) {cerr << << x << ;} void __print(const string &x) {cerr << << x << ;} void __print(bool x) {cerr << (x ? true : false );} template<typename T, typename V> void __print(const pair<T, V> &x) {cerr << { ; __print(x.first); cerr << , ; __print(x.second); cerr << } ;} template<typename T> void __print(const T &x) {int f = 0; cerr << { ; for (auto &i: x) cerr << (f++ ? , : ), __print(i); cerr << } ;} void _print() {cerr << ] n ;} template <typename T, typename... V> void _print(T t, V... v) {__print(t); if (sizeof...(v)) cerr << , ; _print(v...);} #ifndef ONLINE_JUDGE #define debug(x...) cerr << [ << #x << ] = [ ; _print(x) #else #define debug(x...) #endif #define ll long long int const int mod = 1000000007; int mpow(int b, int e); void solve(){ int n; cin>>n; vector<int> even, odd; for(int i=0; i<n;i++){ int x; cin>>x; if(x&1) odd.push_back(x); else even.push_back(x); } for(auto i:odd) cout<<i<< ; for(auto i:even) cout<<i<< ; cout<<endl; } int main(){ ios_base::sync_with_stdio(false); cin.tie(0);cout.tie(0); int t=1; cin>>t; for(int tt=1; tt<=t; tt++){ //cout << Case # <<tt<< : ; solve(); } return 0; } //modular exponentiation int mpow(int base, int exp) { base %= mod; int result = 1; while (exp > 0) { if (exp & 1) result = ((ll)result * base) % mod; base = ((ll)base * base) % mod; exp >>= 1; } return result; } |
#include <bits/stdc++.h> using namespace std; void init() {} const int N = 63e5 + 34; const long long INF = 2e9 + 34; int MD = 30; string sym = AHIMOTUVWXYovwx ; void fail() { cout << NIE ; exit(0); } int main() { init(); string s; cin >> s; int n = s.length(); if (n % 2 && sym.find(s[n / 2]) > 3000) fail(); for (int i = 0; i < n / 2; i++) { if (sym.find(s[i]) < 3000 && sym.find(s[n - i - 1]) < 300 && s[i] == s[n - i - 1]) continue; if (s[i] == b && s[n - i - 1] == d ) continue; if (s[i] == d && s[n - i - 1] == b ) continue; if (s[i] == p && s[n - i - 1] == q ) continue; if (s[i] == q && s[n - i - 1] == p ) continue; fail(); } cout << TAK ; return 0; } |
`timescale 1ns / 1ps
// nexys3MIPSSoC is a MIPS implementation originated from COAD projects
// Copyright (C) 2014 @Wenri, @dtopn, @Speed
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
module Muliti_cycle_Cpu( clk,
reset,
MIO_ready,
pc_out, //TEST
Inst, //TEST
mem_w,
Addr_out,
data_out,
data_in,
breq_o,
CPU_MIO,
state,
Ireq,
Iack,
Enable_i
);
input clk,reset,MIO_ready,Ireq,Enable_i;
output [31:0] pc_out;
output [31:0] Inst;
output mem_w, breq_o, CPU_MIO,Iack;
output [31:0] Addr_out;
output [31:0] data_out;
output [4:0] state;
input [31:0] data_in;
wire [31:0] Inst,Addr_out,PC_Current,pc_out,data_in,data_out;
wire [15:0] imm;
wire [4:0] state;
wire [2:0] ALU_operation,MemtoReg,PCSource;
wire [1:0] RegDst,ALUSrcB,IntCause;
wire breq_o,CPU_MIO,MemRead,MemWrite,IorD,IRWrite,RegWrite,ALUSrcA,PCWrite,PCWriteCond,Beq,CauseWrite,EPCWrite,Co0Write;
wire reset,MIO_ready, mem_w,zero,overflow,Ireq,Iack,Enable_i;
// assign rst=reset;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++=
ctrl x_ctrl(.clk(clk),
.reset(reset),
.Inst_in(Inst),
.zero(zero),
.overflow(overflow),
.MIO_ready(MIO_ready),
.MemRead(MemRead),
.MemWrite(MemWrite),
.ALU_operation(ALU_operation),
.state_out(state),
.CPU_MIO(CPU_MIO),
.IorD(IorD),
.IRWrite(IRWrite),
.RegDst(RegDst),
.RegWrite(RegWrite),
.MemtoReg(MemtoReg),
.ALUSrcA(ALUSrcA),
.ALUSrcB(ALUSrcB),
.PCSource(PCSource),
.PCWrite(PCWrite),
.PCWriteCond(PCWriteCond),
.Beq(Beq),
.CauseWrite(CauseWrite),
.IntCause(IntCause),
.EPCWrite(EPCWrite),
.Co0Write(Co0Write),
.Ireq(Ireq),
.Iack(Iack),
.Enable_i(Enable_i)
);
data_path x_datapath(.clk(clk),
.reset(reset),
.MIO_ready(MIO_ready),
.IorD(IorD),
.IRWrite(IRWrite),
.RegDst(RegDst),
.RegWrite(RegWrite),
.MemtoReg(MemtoReg),
.ALUSrcA(ALUSrcA),
.ALUSrcB(ALUSrcB),
.PCSource(PCSource),
.PCWrite(PCWrite),
.PCWriteCond(PCWriteCond),
.Beq(Beq),
.ALU_operation(ALU_operation),
.PC_Current(PC_Current),
.data2CPU(data_in),
.Inst_R(Inst),
.data_out(data_out),
.M_addr(Addr_out),
.zero(zero),
.overflow(overflow),
.CauseWrite(CauseWrite),
.IntCause(IntCause),
.EPCWrite(EPCWrite),
.Co0Write(Co0Write)
);
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++==
assign mem_w=MemWrite&&(~MemRead);
assign breq_o=MemRead|MemWrite;
assign pc_out=PC_Current;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFSTP_BLACKBOX_V
`define SKY130_FD_SC_HS__DFSTP_BLACKBOX_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dfstp (
CLK ,
D ,
Q ,
SET_B
);
input CLK ;
input D ;
output Q ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFSTP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int N = 100000 + 7; int n; int val[N]; struct edge { int to, nex; } e[N << 1]; int fir[N], eid; int siz[N], fa[N], son[N]; int dfn[N], pos[N], inx; int cnt[N], res[N]; long long mul[N], ans[N]; void addedge(int u, int v) { e[++eid] = (edge){v, fir[u]}; fir[u] = eid; } void hld(int s) { siz[s] = 1; pos[dfn[s] = ++inx] = s; for (int i = fir[s]; i; i = e[i].nex) if (e[i].to != fa[s]) fa[e[i].to] = s, hld(e[i].to), siz[s] += siz[e[i].to], son[s] = siz[e[i].to] > siz[son[s]] ? e[i].to : son[s]; } void dfs(int s, int rem) { for (int i = fir[s]; i; i = e[i].nex) if (e[i].to != fa[s] && e[i].to != son[s]) dfs(e[i].to, 0); if (son[s]) dfs(son[s], 1); int c = val[s]; mul[cnt[c]] -= c, mul[++cnt[c]] += c, res[s] = max(res[son[s]], cnt[c]); for (int i = fir[s]; i; i = e[i].nex) { if (e[i].to == fa[s] || e[i].to == son[s]) continue; for (int j = dfn[e[i].to], c; j < dfn[e[i].to] + siz[e[i].to]; ++j) c = val[pos[j]], mul[cnt[c]] -= c, mul[++cnt[c]] += c, res[s] = max(res[s], cnt[c]); } ans[s] = mul[res[s]]; if (rem) return; memset(cnt, 0, sizeof(int) * (n + 2)); memset(mul, 0, sizeof(long long) * (res[s] + 2)); } int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) scanf( %d , val + i); for (int i = 1, u, v; i < n; ++i) scanf( %d%d , &u, &v), addedge(u, v), addedge(v, u); hld(1); dfs(1, 1); for (int i = 1; i <= n; ++i) printf( %I64d , ans[i]); return 0; } |
module j1soc#(
//parameter bootram_file = "../../firmware/hello_world/j1.mem" // For synthesis
parameter bootram_file = "../firmware/Hello_World/j1.mem" // For simulation
)(
uart_tx, ledout,
sys_clk_i, sys_rst_i
);
input sys_clk_i, sys_rst_i;
output uart_tx;
output ledout;
//------------------------------------ regs and wires-------------------------------
wire j1_io_rd;//********************** J1
wire j1_io_wr;//********************** J1
wire [15:0] j1_io_addr;//************* J1
reg [15:0] j1_io_din;//************** J1
wire [15:0] j1_io_dout;//************* J1
reg [1:4]cs; // CHIP-SELECT
wire [15:0] mult_dout;
wire [15:0] div_dout;
wire uart_dout; // misma señal que uart_busy from uart.v
wire [15:0] dp_ram_dout;
//------------------------------------ regs and wires-------------------------------
j1 #(bootram_file) cpu0(sys_clk_i, sys_rst_i, j1_io_din, j1_io_rd, j1_io_wr, j1_io_addr, j1_io_dout);
peripheral_mult per_m (.clk(sys_clk_i), .rst(sys_rst_i), .d_in(j1_io_dout), .cs(cs[1]), .addr(j1_io_addr[3:0]), .rd(j1_io_rd), .wr(j1_io_wr), .d_out(mult_dout) );
peripheral_div per_d (.clk(sys_clk_i), .rst(sys_rst_i), .d_in(j1_io_dout), .cs(cs[2]), .addr(j1_io_addr[3:0]), .rd(j1_io_rd), .wr(j1_io_wr), .d_out(div_dout));
peripheral_uart per_u (.clk(sys_clk_i), .rst(sys_rst_i), .d_in(j1_io_dout), .cs(cs[3]), .addr(j1_io_addr[3:0]), .rd(j1_io_rd), .wr(j1_io_wr), .d_out(uart_dout), .uart_tx(uart_tx), .ledout(ledout));
dpRAM_interface dpRm(.clk(sys_clk_i), .d_in(j1_io_dout), .cs(cs[4]), .addr(j1_io_addr[7:0]), .rd(j1_io_rd), .wr(j1_io_wr), .d_out(dp_ram_dout));
// ============== Chip_Select (Addres decoder) ======================== // se hace con los 8 bits mas significativos de j1_io_addr
always @*
begin
case (j1_io_addr[15:8]) // direcciones - chip_select
8'h67: cs= 4'b1000; //mult
8'h68: cs= 4'b0100; //div
8'h69: cs= 4'b0010; //uart
8'h70: cs= 4'b0001; //dp_ram
default: cs= 3'b000;
endcase
end
// ============== Chip_Select (Addres decoder) ======================== //
// ============== MUX ======================== // se encarga de lecturas del J1
always @*
begin
case (cs)
4'b1000: j1_io_din = mult_dout;
4'b0100: j1_io_din = div_dout;
4'b0010: j1_io_din = uart_dout;
4'b0001: j1_io_din = dp_ram_dout;
default: j1_io_din = 16'h0666;
endcase
end
// ============== MUX ======================== //
endmodule // top
|
#include <bits/stdc++.h> using namespace std; char c[100003], b[100003]; int ggg[100003]; string a; long long d, e, f, g, ming, oo, ksa, lxy; bool nn, o; int main() { gets(c); c[strlen(c)] = ; a = c; for (int i = 0; i <= a.length(); i++) { if (a.substr(i, 1) == ) { if (o == 0) { if (i >= 5 && a.substr(i - 5, 5) == liala ) nn = 1; else if (i >= 4 && a.substr(i - 4, 4) == etra ) nn = 1; else if (i >= 6 && a.substr(i - 6, 6) == inites ) nn = 1; o = 1; } if (!nn) { if (i >= 3 && a.substr(i - 3, 3) == etr ) { ming += 1; g++; ggg[g] = 2; } else if (i >= 6 && a.substr(i - 6, 6) == initis ) { g++; ggg[g] = 3; } else if (i >= 4 && a.substr(i - 4, 4) == lios ) { g++; ggg[g] = 1; } else { cout << NO << endl; return 0; } } if (nn) { if (i >= 4 && a.substr(i - 4, 4) == etra ) { g++; ggg[g] = 2; ming += 1; } else if (i >= 6 && a.substr(i - 6, 6) == inites ) { g++; ggg[g] = 3; } else if (i >= 5 && a.substr(i - 5, 5) == liala ) { g++; ggg[g] = 1; } else { cout << NO << endl; return 0; } } oo++; } } if (oo == 1) { if (a.length() >= 5 && a.substr(a.length() - 5, 4) == lios ) ming = 1; if (a.length() >= 4 && a.substr(a.length() - 4, 3) == etr ) ming = 1; if (a.length() >= 7 && a.substr(a.length() - 7, 6) == inites ) ming = 1; if (a.length() >= 7 && a.substr(a.length() - 7, 6) == initis ) ming = 1; if (a.length() >= 6 && a.substr(a.length() - 6, 5) == liala ) ming = 1; if (a.length() >= 5 && a.substr(a.length() - 5, 4) == etra ) ming = 1; } for (int i = 1; i <= 100002; i++) { if (ggg[i] == 0) { ksa = 1; break; } if (ggg[i] < ggg[i - 1]) break; } if (ming == 1 && oo == 1) { cout << YES << endl; return 0; } else if (oo == 1) { cout << NO << endl; return 0; } if (ming == 1 && ksa == 1) cout << YES << endl; else cout << NO << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int in; int a[105][105]; int b[100000]; int max(int l, int n) { int m = a[l][0]; int in = 0; for (int x = 0; x < n; x++) { if (m < a[l][x]) { m = a[l][x]; in = x; } } return in; } int main() { int n, m; cin >> n >> m; int i, j; for (i = 0; i < m; ++i) for (j = 0; j < n; ++j) cin >> a[i][j]; for (j = 0; j < m; ++j) { b[max(j, n)] += 1; } int m1 = b[0]; if (m != 1) for (i = 1; i < m; ++i) { if (m1 < b[i]) { m1 = b[i]; in = i; } } else in = max(0, n); cout << (in + 1); } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EBUFN_BEHAVIORAL_V
`define SKY130_FD_SC_MS__EBUFN_BEHAVIORAL_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__ebufn (
Z ,
A ,
TE_B
);
// Module ports
output Z ;
input A ;
input TE_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
bufif0 bufif00 (Z , A, TE_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__EBUFN_BEHAVIORAL_V |
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2005,2006 Matt Ettus
// Copyright (C) 2008 Corgan Enterprises LLC
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
`include "../../../../usrp/firmware/include/fpga_regs_common.v"
`include "../../../../usrp/firmware/include/fpga_regs_standard.v"
module io_pins
( inout wire [15:0] io_0, inout wire [15:0] io_1, inout wire [15:0] io_2, inout wire [15:0] io_3,
input wire [15:0] reg_0, input wire [15:0] reg_1, input wire [15:0] reg_2, input wire [15:0] reg_3,
input wire [15:0] io_0_force_output, input wire [15:0] io_2_force_output,
input wire [15:0] io_1_force_input, input wire [15:0] io_3_force_input,
input clock, input rx_reset, input tx_reset,
input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe);
reg [15:0] io_0_oe,io_1_oe,io_2_oe,io_3_oe;
bidir_reg bidir_reg_0 (.tristate(io_0),.oe(io_0_oe | io_0_force_output),.reg_val(reg_0));
bidir_reg bidir_reg_1 (.tristate(io_1),.oe(io_1_oe & (~io_1_force_input)),.reg_val(reg_1));
bidir_reg bidir_reg_2 (.tristate(io_2),.oe(io_2_oe | io_2_force_output),.reg_val(reg_2));
bidir_reg bidir_reg_3 (.tristate(io_3),.oe(io_3_oe & (~io_3_force_input)),.reg_val(reg_3));
// Upper 16 bits are mask for lower 16
always @(posedge clock)
if(serial_strobe)
case(serial_addr)
`FR_OE_0 : io_0_oe
<= #1 (io_0_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
`FR_OE_1 : io_1_oe
<= #1 (io_1_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
`FR_OE_2 : io_2_oe
<= #1 (io_2_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
`FR_OE_3 : io_3_oe
<= #1 (io_3_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
endcase // case(serial_addr)
endmodule // io_pins
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 7; long long a[N], b[N]; deque<int> mx, mn; int main() { long long n; cin >> n; long long i; for (i = 1; i <= n; i++) cin >> a[i]; for (i = 1; i <= n; i++) cin >> b[i]; long long j, ans = 0; for (j = 1, i = 1; i <= n; i++) { while (!mx.empty() and a[mx.back()] <= a[i]) mx.pop_back(); while (!mn.empty() and b[mn.back()] >= b[i]) mn.pop_back(); mx.push_back(i), mn.push_back(i); while (j <= i and a[mx.front()] - b[mn.front()] > 0) { j++; while (!mx.empty() and mx.front() < j) mx.pop_front(); while (!mn.empty() and mn.front() < j) mn.pop_front(); } if (!mx.empty() and !mn.empty() and a[mx.front()] == b[mn.front()]) ans += min(mx.front(), mn.front()) - j + 1; } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; map<string, int> ma; int main() { string s; int n; cin >> n; ma.clear(); while (n--) { cin >> s; if (ma[s] == 0) printf( NO n ); else printf( YES n ); ma[s]++; } return 0; } |
#include <bits/stdc++.h> using namespace std; int n; int a[100100], b[100100]; int id[100100], p[100100]; int main() { int T = 1; while (T--) { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); id[a[i]] = i; } for (int i = 1; i <= n; i++) { scanf( %d , &b[i]); } for (int i = 1; i <= n; i++) { int x = b[i]; int op = id[x]; p[i] = op; } for (int i = 1; i <= n; i++) printf( %d , p[i]); } } |
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7, siz = 1e6 + 5; long long t, n, m, k, a[siz], inp[siz], cnt, co[siz], less_right[siz], less_left[siz], tree[siz][2]; pair<long long, long long> p[siz]; long long get(long long ind, long long id) { long long ret = 0; for (; ind; ind -= ind & -ind) ret += tree[ind][id]; return ret; } void upd(long long id, long long ind, long long val) { for (; ind <= cnt; ind += ind & -ind) tree[ind][id] += val; } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n; for (long long i = 1; i <= n; i++) cin >> p[i].first, p[i].second = i; sort(p + 1, p + 1 + n); for (long long i = 1; i <= n; i++) { a[p[i].second] = ++cnt; inp[p[i].second] = p[i].first; } for (long long i = 1; i <= n; i++) { less_left[i] = get(a[i], 0); upd(0, a[i], i); } for (long long i = n; i >= 1; i--) { less_right[i] = get(a[i], 1); upd(1, a[i], n - i + 1); } long long ans = 0; for (long long i = 1; i <= n; i++) { co[i] = i * (n - i + 1); co[i] += less_left[i] * (n - i + 1) + less_right[i] * i; co[i] %= mod; long long toadd = (co[i] * inp[i]) % mod; (ans += toadd) %= mod; } cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; int main(int argc, char** argv) { char s[3][3]; bool is = false; for (int i = 0; i < 3; i++) { for (int j = 0; j < 3; j++) { cin >> s[i][j]; if (s[i][j] == X ) is = true; } } int i = 0, j = 0; bool isY = true; for (int i = 0; i < 3; i++) { for (int j = 0; j < 3; j++) if (s[i][j] != s[2 - i][2 - j]) isY = false; } if (isY) cout << YES ; else cout << NO ; return 0; } |
//--------------------------------------------------------------------------------
//--
//-- This file is owned and controlled by Xilinx and must be used solely
//-- for design, simulation, implementation and creation of design files
//-- limited to Xilinx devices or technologies. Use with non-Xilinx
//-- devices or technologies is expressly prohibited and immediately
//-- terminates your license.
//--
//-- Xilinx products are not intended for use in life support
//-- appliances, devices, or systems. Use in such applications is
//-- expressly prohibited.
//--
//-- **************************************
//-- ** Copyright (C) 2005, Xilinx, Inc. **
//-- ** All Rights Reserved. **
//-- **************************************
//--
//--------------------------------------------------------------------------------
//-- Filename: BMD_TO_CTRL.v
//--
//-- Description: Turn-off Control Unit.
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module BMD_TO_CTRL (
clk,
rst_n,
req_compl_i,
compl_done_i,
cfg_to_turnoff_n,
cfg_turnoff_ok_n
);
input clk;
input rst_n;
input req_compl_i;
input compl_done_i;
input cfg_to_turnoff_n;
output cfg_turnoff_ok_n;
reg trn_pending;
reg cfg_turnoff_ok_n;
/*
* Check if completion is pending
*/
always @ ( posedge clk ) begin
if (!rst_n ) begin
trn_pending <= 0;
end else begin
if (!trn_pending && req_compl_i)
trn_pending <= 1'b1;
else if (compl_done_i)
trn_pending <= 1'b0;
end
end
/*
* Turn-off OK if requested and no transaction is pending
*/
always @ ( posedge clk ) begin
if (!rst_n ) begin
cfg_turnoff_ok_n <= 1'b1;
end else begin
if ( !cfg_to_turnoff_n && !trn_pending )
cfg_turnoff_ok_n <= 1'b0;
else
cfg_turnoff_ok_n <= 1'b1;
end
end
endmodule // BMD_TO_CTRL
|
// ******************************************************************************* //
// ** General Information ** //
// ******************************************************************************* //
// ** Module : QM_FIR.v ** //
// ** Project : ISAAC NEWTON ** //
// ** Original Author : Kayla Nguyen ** //
// ** First Release Date : August 13, 2008 ** //
// ** Description : Quadrature Modulation and Polyphase Decimation. ** //
// ** This module gives both the real part and the ** //
// ** ofimaginary part the along with their polyphase ** //
// ** decimation. ** //
// ******************************************************************************* //
// ** Revision History ** //
// ******************************************************************************* //
// ** ** //
// ** File : QM_FIR.v ** //
// ** Revision : 1 ** //
// ** Author : kaylangu ** //
// ** Date : August 13, 2008 ** //
// ** FileName : ** //
// ** Notes : Initial Release for ISAAC demo ** //
// ** ** //
// ** File : QM_FIR.v ** //
// ** Revision : 2 ** //
// ** Author : kaylangu ** //
// ** Date : February 9, 2009 ** //
// ** FileName : ** //
// ** Notes : Revise for 240MHZ implementation ** //
// ** ** //
// ******************************************************************************* //
`timescale 1 ns / 100 ps
module QM_FIR(/*AUTOARG*/
// Outputs
RealOut1, RealOut2, RealOut3, ImagOut1, ImagOut2, ImagOut3,
DataValid,
// Inputs
CLK, ARST, InputValid, dsp_in0, dsp_in1, dsp_in2, dsp_in3, freq,
newFreq, freq1, freq2, freq3
);
//*****************************************************************************//
//* Declarations *//
//*****************************************************************************//
// DATA TYPE - PARAMETERS
parameter OWIDTH = 16;
parameter IWIDTH = 8;
parameter ACCUMWIDTH = 32;
// DATA TYPE - INPUTS AND OUTPUTS
output signed [(OWIDTH-1):0] RealOut1, RealOut2, RealOut3;
output signed [(OWIDTH-1):0] ImagOut1, ImagOut2, ImagOut3;
output DataValid;
input CLK;
input ARST;
input InputValid;
input signed [(IWIDTH-1):0] dsp_in0;
input signed [(IWIDTH-1):0] dsp_in1;
input signed [(IWIDTH-1):0] dsp_in2;
input signed [(IWIDTH-1):0] dsp_in3;
input [6:0] freq;
input newFreq;
input [6:0] freq1;
input [6:0] freq2;
input [6:0] freq3;
// DATA TYPE - WIRES
wire OutputValid_QM;
wire signed [(OWIDTH-1):0] Real1, Real2, Real3;
wire signed [(OWIDTH-1):0] Imag1, Imag2, Imag3;
//*****************************************************************************//
//* Submodules *//
//*****************************************************************************//
//Quadrature Modulation and FIR0
FIR0QM FIR0QM
(//Inputs
.clk(CLK),
.rst(ARST),
.freq(freq),
.freq1(freq1),
.freq2(freq2),
.freq3(freq3),
.newFreq(newFreq),
.InputValid(InputValid),
.dsp_in0(dsp_in0),
.dsp_in1(dsp_in1),
.dsp_in2(dsp_in2),
.dsp_in3(dsp_in3),
//Outputs
.Real1(Real1),
.Real2(Real2),
.Real3(Real3),
.Imag1(Imag1),
.Imag2(Imag2),
.Imag3(Imag3),
.OutputValid(OutputValid_QM)
);
//Firdecim 1st channel Real Filter
firdecim firdecimR1
(//Inputs
.CLK (CLK),
.ARST (ARST),
.InputValid (OutputValid_QM),
.SigIn (Real1),
//Outputs
.SigOut (RealOut1),
.DataValid (DataValid)
);
//Firdecim 1st channel Imaginary Filter
firdecim firdecimI1
(//Inputs
.CLK (CLK),
.ARST (ARST),
.InputValid (OutputValid_QM),
.SigIn (Imag1),
//Outputs
.SigOut (ImagOut1)
);
//Firdecim noise channel Real Filter
firdecim firdecimR2
(//Inputs
.CLK (CLK),
.ARST (ARST),
.InputValid (OutputValid_QM),
.SigIn (Real2),
//Outputs
.SigOut (RealOut2)
);
//Firdecim noise channel Imaginary Filter
firdecim firdecimI2
(//Inputs
.CLK (CLK),
.ARST (ARST),
.InputValid (OutputValid_QM),
.SigIn (Imag2),
//Outputs
.SigOut (ImagOut2)
);
//Firdecim 2nd channel Real Filter
firdecim firdecimR3
(//Inputs
.CLK (CLK),
.ARST (ARST),
.InputValid (OutputValid_QM),
.SigIn (Real3),
//Outputs
.SigOut (RealOut3)
);
//Firdecim 2nd channel Imaginary Filter
firdecim firdecimI3
(//Inputs
.CLK (CLK),
.ARST (ARST),
.InputValid (OutputValid_QM),
.SigIn (Imag3),
//Outputs
.SigOut (ImagOut3)
);
endmodule // QM_FIR
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21.02.2016 16:25:28
// Design Name:
// Module Name: SPI_MASTER
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SPI_MASTER#
(
parameter integer m = 15 // Data packet size
)
(
input clk,
input wire RST,
output reg EN_TX=0,
input ce,
output wire LOAD,
input st,
output wire SCLK,
input MISO,
output wire MOSI,
input [m-1:0] TX_MD,
output reg [m-1:0] RX_SD=0,
input LEFT,
output wire CEfront,
output wire CEspad
);
reg [m-1:0] MQ=0 ; //Ðåãèñòð ñäâèãà âûõîäíûõ äàííûõ MASTER-à
reg [m-1:0] MRX=0 ; //Ðåãèñòð ñäâèãà âõîäíûõ äàííûõ MASTER-à
reg ss = 0;
reg [5:0] T_del = 0;
reg [3:0] cb_bit=0; //Ñ÷åò÷èê áèò
assign MOSI = LEFT ? MQ[m-1] : MQ[0] ; // Âûõîäíûå äàííûå MASTER-à
assign LOAD = !EN_TX; // Èíòåðâàë ïåðåäà÷è/ïðèåìà
assign SCLK = EN_TX & ce;
reg st_buf = 1'b0;
always @(posedge ce) begin
if (!EN_TX & st) begin
st_buf <= 1'b1;
end
else begin
st_buf <= 1'b0;
end
end
always @(negedge ce) begin
MQ <= st_buf? TX_MD : LEFT ? MQ<<1 : MQ>>1;
EN_TX <= (cb_bit == (m-1))? 0 : st_buf? 1'b1 : EN_TX;
cb_bit <= st_buf? 0 : cb_bit + 4'd1 ;
end
reg wready = 1'b0;
always @(posedge ce) begin
MRX <= (EN_TX == 1'b1) ? MRX<<1 | MISO : 0;
if (RST == 1'b1) begin
RX_SD <= 0;
wready <= 1'b0;
end
else if (EN_TX == 1'b0) begin
if (wready == 1'b0) begin
RX_SD <= MRX;
end
wready <= 1'b1;
end
else begin
wready <= 1'b0;
RX_SD <= RX_SD;
end
end
//always @(posedge LOAD) begin
//end
endmodule |
#include <bits/stdc++.h> int main() { int x1, y1, r1, x2, y2, r2; scanf( %d %d %d %d %d %d , &x1, &y1, &r1, &x2, &y2, &r2); double ans; ans = (sqrt((x2 - x1) * (x2 - x1) + (y2 - y1) * (y2 - y1)) - r1 - r2) / 2; if (ans < 0) if (r1 > r2) ans = (r1 - r2 - sqrt((x2 - x1) * (x2 - x1) + (y2 - y1) * (y2 - y1))) / 2; else ans = ans = (r2 - r1 - sqrt((x2 - x1) * (x2 - x1) + (y2 - y1) * (y2 - y1))) / 2; if (ans < 0) printf( 0.000000000 ); else printf( %lf , ans); return 0; } |
module mod_grid_display(
input in_pix_clk, // Clock to sync all pixel inputs/outputs to
input [9:0] in_pix_x, // Current pixel output position (x,y)
input [9:0] in_pix_y,
input in_latch,
input [7:0] in_pixel_r, // Parent video pixel data to overlay on
input [7:0] in_pixel_g,
input [7:0] in_pixel_b,
output [7:0] out_pixel_r, // Video pixel data after overlay
output [7:0] out_pixel_g,
output [7:0] out_pixel_b
);
reg is_overlay;
reg [7:0] pixel_r;
reg [7:0] pixel_g;
reg [7:0] pixel_b;
always @(posedge in_pix_clk) begin
if (in_pix_y[3:0] == 4'b0000 || in_pix_y[3:0] == 4'b1111) begin
is_overlay <= 1'b1;
end else if (in_pix_x[3:0] == 4'b0000 || in_pix_x[3:0] == 4'b1111) begin
is_overlay <= 1'b1;
end else begin
is_overlay <= 1'b0;
end
pixel_r <= 8'b00000000;
pixel_g <= 8'b00000000;
pixel_b <= 8'b11111111;
end
assign out_pixel_r = is_overlay ? pixel_r : in_pixel_r;
assign out_pixel_g = is_overlay ? pixel_g : in_pixel_g;
assign out_pixel_b = is_overlay ? pixel_b : in_pixel_b;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 200018; int arr[N]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; map<long long, int> mp; long long sum1 = 0; for (int i = 1; i <= n; i++) { cin >> arr[i], sum1 += arr[i]; mp[sum1] = i; } long long sum3 = 0, ans = 0; for (int i = n; i >= 1; i--) { sum3 += arr[i]; if (mp[sum3] && mp[sum3] < i) { ans = sum3; } } cout << ans; } |
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_SystemID (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? : 255;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int i; string a[3]; cin >> a[0] >> a[1] >> a[2]; for (i = 0; i < 3; i++) { if ((a[i] == rock ) && (a[(i + 1) % 3] == scissors ) && (a[(i + 2) % 3] == scissors )) { break; } if ((a[i] == scissors ) && (a[(i + 1) % 3] == paper ) && (a[(i + 2) % 3] == paper )) { break; } if ((a[i] == paper ) && (a[(i + 1) % 3] == rock ) && (a[(i + 2) % 3] == rock )) { break; } } if (i == 0) { cout << F << endl; } else if (i == 1) { cout << M << endl; } else if (i == 2) { cout << S << endl; } else { cout << ? << endl; } } |
//////////////////////////////////////////////////////////////////////////////////
//
// This file is part of the N64 RGB/YPbPr DAC project.
//
// Copyright (C) 2016-2018 by Peter Bartmann <>
//
// N64 RGB/YPbPr DAC is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//////////////////////////////////////////////////////////////////////////////////
//
// Company: Circuit-Board.de
// Engineer: borti4938
// (initial design file by Ikari_01)
//
// Module Name: n64rgbv2_top
// Project Name: N64 RGB DAC Mod
// Target Devices: several MaxII & MaxV devices
// Tool versions: Altera Quartus Prime
//
// Revision: 3.0
//
// Description:
//
// short description of N64s RGB and sync data demux
// -------------------------------------------------
//
// pulse shapes and their realtion to each other:
// VCLK (~50MHz, Numbers representing posedge count)
// ---. 3 .---. 0 .---. 1 .---. 2 .---. 3 .---
// |___| |___| |___| |___| |___|
// nDSYNC (~12.5MHz) .....
// -------. .-------------------.
// |_______| |_______
//
// more info: http://members.optusnet.com.au/eviltim/n64rgb/n64rgb.html
//
//
//////////////////////////////////////////////////////////////////////////////////
module n64rgbv2_top (
// N64 Video Input
VCLK,
nDSYNC,
D_i,
// Controller and Reset
nRST_io,
CTRL_i,
// Jumper
nSYNC_ON_GREEN,
n16bit_mode_t,
nVIDeBlur_t,
en_IGR_Rst_Func,
en_IGR_DeBl_16b_Func,
// Video output
nHSYNC,
nVSYNC,
nCSYNC,
nCLAMP,
R_o, // red data vector
G_o, // green data vector
B_o, // blue data vector
CLK_ADV712x,
nCSYNC_ADV712x,
nBLANK_ADV712x,
dummy_i
);
`include "vh/n64rgb_params.vh"
input VCLK;
input nDSYNC;
input [color_width-1:0] D_i;
inout nRST_io;
input CTRL_i;
input nSYNC_ON_GREEN;
input n16bit_mode_t;
input nVIDeBlur_t;
input en_IGR_Rst_Func;
input en_IGR_DeBl_16b_Func;
output reg nHSYNC;
output reg nVSYNC;
output reg nCSYNC;
output reg nCLAMP;
output reg [color_width:0] R_o;
output reg [color_width:0] G_o;
output reg [color_width:0] B_o;
output reg CLK_ADV712x;
output reg nCSYNC_ADV712x;
output reg nBLANK_ADV712x;
input [4:0] dummy_i;
// start of rtl
wire DRV_RST, n16bit_mode_o, nDeBlur_o;
wire nRST_int = nRST_io;
wire [3:0] vinfo_pass;
wire [`VDATA_FU_SLICE] vdata_r[0:1];
// housekeeping
// ============
n64rgb_hk hk_u(
.VCLK(VCLK),
.nRST(nRST_int),
.DRV_RST(DRV_RST),
.CTRL_i(CTRL_i),
.n64_480i(vinfo_pass[0]),
.n16bit_mode_t(n16bit_mode_t),
.nVIDeBlur_t(nVIDeBlur_t),
.en_IGR_Rst_Func(en_IGR_Rst_Func),
.en_IGR_DeBl_16b_Func(en_IGR_DeBl_16b_Func),
.n16bit_o(n16bit_mode_o),
.nDeBlur_o(nDeBlur_o)
);
// acquire vinfo
// =============
n64_vinfo_ext get_vinfo(
.VCLK(VCLK),
.nDSYNC(nDSYNC),
.Sync_pre(vdata_r[0][`VDATA_SY_SLICE]),
.Sync_cur(D_i[3:0]),
.vinfo_o(vinfo_pass)
);
// video data demux
// ================
n64_vdemux video_demux(
.VCLK(VCLK),
.nDSYNC(nDSYNC),
.D_i(D_i),
.demuxparams_i({vinfo_pass[3:1],nDeBlur_o,n16bit_mode_o}),
.vdata_r_0(vdata_r[0]),
.vdata_r_1(vdata_r[1])
);
// assign final outputs
// ====================
assign nRST_io = DRV_RST ? 1'b0 : 1'bz;
always @(*) begin
{nVSYNC,nCLAMP,nHSYNC,nCSYNC} <= vdata_r[1][`VDATA_SY_SLICE];
R_o <= {vdata_r[1][`VDATA_RE_SLICE],vdata_r[1][3*color_width-1]};
G_o <= {vdata_r[1][`VDATA_GR_SLICE],vdata_r[1][2*color_width-1]};
B_o <= {vdata_r[1][`VDATA_BL_SLICE],vdata_r[1][ color_width-1]};
CLK_ADV712x <= VCLK;
nCSYNC_ADV712x <= nSYNC_ON_GREEN ? 1'b0 : vdata_r[1][vdata_width-4];
nBLANK_ADV712x <= 1'b1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; double max(double a, double b) { if (a >= b) return a; else return b; } int main() { double m[5], s, u; for (int i = 0; i < 5; i++) cin >> m[i]; double sum = 0, sum1; for (int i = 0; i < 5; i++) { sum1 = 0; double x; cin >> x; sum1 += ((250 - m[i]) / 250.0) * (500) * float(i + 1); sum1 -= 50 * x; sum += max(sum1, double(0.3 * double(i + 1) * 500.0)); } cin >> s >> u; cout << sum + 100 * s - 50 * u; return 0; } |
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