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// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_t
//
// Generated
// by: wig
// on: Tue Jun 27 05:12:12 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_t.v,v 1.6 2006/07/04 09:54:11 wig Exp $
// $Date: 2006/07/04 09:54:11 $
// $Log: ent_t.v,v $
// Revision 1.6 2006/07/04 09:54:11 wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_t
//
// No user `defines in this module
module ent_t
//
// Generated Module inst_t
//
(
sig_i_a,
sig_i_a2,
sig_i_ae,
sig_o_a,
sig_o_a2,
sig_o_ae
);
// Generated Module Inputs:
input sig_i_a;
input sig_i_a2;
input [6:0] sig_i_ae;
// Generated Module Outputs:
output sig_o_a;
output sig_o_a2;
output [7:0] sig_o_ae;
// Generated Wires:
wire sig_i_a;
wire sig_i_a2;
wire [6:0] sig_i_ae;
wire sig_o_a;
wire sig_o_a2;
wire [7:0] sig_o_ae;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire sig_01;
wire sig_03;
wire sig_04;
wire [3:0] sig_05;
wire [3:0] sig_06;
wire [5:0] sig_07;
wire [8:2] sig_08;
// __I_OUT_OPEN wire [4:0] sig_13; // __W_BAD_BRANCH
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_a
ent_a inst_a (
.p_mix_sig_01_go(sig_01), // Use internally test1Will create p_mix_sig_1_go port
.p_mix_sig_03_go(sig_03), // Interhierachy link, will create p_mix_sig_3_go
.p_mix_sig_04_gi(sig_04), // Interhierachy link, will create p_mix_sig_4_gi
.p_mix_sig_05_2_1_go(sig_05[2:1]), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.p_mix_sig_06_gi(sig_06), // Conflicting definition (X2)
.p_mix_sig_i_ae_gi(sig_i_ae), // Input Bus
.p_mix_sig_o_ae_go(sig_o_ae), // Output Bus
.port_i_a(sig_i_a), // Input Port
.port_o_a(sig_o_a), // Output Port
.sig_07(sig_07), // Conflicting definition, IN false!
.sig_08(sig_08), // VHDL intermediate needed (port name)
.sig_13(), // Create internal signal name
.sig_i_a2(sig_i_a2), // Input Port
.sig_o_a2(sig_o_a2) // Output Port
);
// End of Generated Instance Port Map for inst_a
// Generated Instance Port Map for inst_b
ent_b inst_b (
.port_b_1(sig_01), // Use internally test1Will create p_mix_sig_1_go port
.port_b_3(sig_03), // Interhierachy link, will create p_mix_sig_3_go
.port_b_4(sig_04), // Interhierachy link, will create p_mix_sig_4_gi
.port_b_5_1(sig_05[2]), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.port_b_5_2(sig_05[1]), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.port_b_6i(sig_06), // Conflicting definition (X2)
.port_b_6o(sig_06), // Conflicting definition (X2)
.sig_07(sig_07), // Conflicting definition, IN false!
.sig_08(sig_08) // VHDL intermediate needed (port name)
);
// End of Generated Instance Port Map for inst_b
endmodule
//
// End of Generated Module rtl of ent_t
//
//
//!End of Module/s
// --------------------------------------------------------------
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by engr248.
// SPDX-License-Identifier: CC0-1.0
module t(/*AUTOARG*/
// Inputs
clk
);
input clk;
wire [31:0] in = 0;
wire [31:0] out;
Test test(
.out(out[31:0]),
.clk(clk),
.in (in[31:0])
);
always @ (posedge clk) begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
interface Intf ();
endinterface
module Select
#(
parameter int NUM_MASTER = 1
)
(
Intf Upstream,
Intf Downstream[NUM_MASTER]
);
endmodule
module Crossbar
#(
parameter int NUM_MASTER = 1,
parameter int NUM_SLAVE = 1
)
(
Intf Masters[NUM_MASTER]
);
Intf selectOut[(NUM_MASTER * (NUM_SLAVE))-1 : 0]();
genvar i;
for (i = 0; i < NUM_MASTER; i = i + 1) begin
Select #(
.NUM_MASTER(NUM_SLAVE)
)
select_inst (
.Upstream(Masters[i]),
// Following line seems to trigger a bad calculation for dimension where port
// is calculated as width 1 (correctly) and expression is calculated as NUM_MASTER*NUM_SLAVE rather than NUM_SLAVE
.Downstream(selectOut[(i)*(NUM_SLAVE) +: (NUM_SLAVE)])
// The following line works as intended and should be functionally identical to the above line
// .Downstream(selectOut[(i+1)*(NUM_SLAVE)-1 : i*(NUM_SLAVE)])
);
end
endmodule
module Test
(
input clk,
input [31:0] in,
output reg [31:0] out
);
always @(posedge clk) begin
out <= in;
end
Intf MST[10]();
Crossbar #(
.NUM_MASTER(10),
.NUM_SLAVE(1)
)
xbar_inst (
.Masters(MST)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); int t; cin >> t; while (t--) { int n; cin >> n; int input[n]; for (int i = (0); i < (n); i++) cin >> input[i]; sort(input, input + n); vector<int> ans(n); for (int i = (0); i < (n / 2); i++) { ans[i * 2] = i; ans[i * 2 + 1] = n - 1 - i; } if (n & 1) ans[n - 1] = n / 2; for (int i = (n)-1; i >= (0); --i) cout << input[ans[i]] << ; cout << n ; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INVKAPWR_SYMBOL_V
`define SKY130_FD_SC_LP__INVKAPWR_SYMBOL_V
/**
* invkapwr: Inverter on keep-alive power rail.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__invkapwr (
//# {{data|Data Signals}}
input A,
output Y
);
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 KAPWR;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__INVKAPWR_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c, x, y, z, e, s, max1, max2, max3, max4; cin >> a >> b >> c; x = a + b * c; y = a * (b + c); z = a * b * c; e = (a + b) * c; s = a + b + c; max1 = (x + y + abs(x - y)) / 2; max2 = (max1 + z + abs(max1 - z)) / 2; max3 = (max2 + e + abs(max2 - e)) / 2; max4 = (max3 + s + abs(max3 - s)) / 2; cout << max4 << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAX = 2e5 + 6; const long long MOD = 1e9 + 7; int a[56]; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, cnt = 0, mn = 50; cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; mn = min(mn, a[i]); } for (int i = 0; i < n; i++) if (a[i] == mn) cnt++; if (cnt <= n / 2) cout << Alice ; else cout << Bob ; } |
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module increases the frame size of video streams. *
* *
******************************************************************************/
module altera_up_video_clipper_add (
// Inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
// Bi-Directional
// Outputs
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 15; // Image's Data Width
parameter EW = 0; // Image's Empty Width
parameter IMAGE_WIDTH = 640; // Final image width in pixels
parameter IMAGE_HEIGHT = 480; // Final image height in lines
parameter WW = 9; // Final image width address width
parameter HW = 8; // Final image height address width
parameter ADD_PIXELS_AT_START = 0;
parameter ADD_PIXELS_AT_END = 0;
parameter ADD_LINES_AT_START = 0;
parameter ADD_LINES_AT_END = 0;
parameter ADD_DATA = 16'h0; // Data for added pixels
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [EW: 0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
// Bidirectional
// Outputs
output stream_in_ready;
output reg [DW: 0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg [EW: 0] stream_out_empty;
output reg stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire increment_counters;
wire new_startofpacket;
wire new_endofpacket;
wire pass_inner_frame;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output registers
always @(posedge clk)
begin
if (reset)
begin
stream_out_data <= 'h0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_empty <= 'h0;
stream_out_valid <= 1'b0;
end
else if (stream_out_ready | ~stream_out_valid)
begin
if (pass_inner_frame)
stream_out_data <= stream_in_data;
else
stream_out_data <= ADD_DATA;
stream_out_startofpacket <= new_startofpacket;
stream_out_endofpacket <= new_endofpacket;
stream_out_empty <= 'h0;
if (pass_inner_frame)
stream_out_valid <= stream_in_valid;
else
stream_out_valid <= 1'b1;
end
end
// Internal registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output assignments
assign stream_in_ready = pass_inner_frame & (~stream_out_valid | stream_out_ready);
// Internal assignments
assign increment_counters = (~stream_out_valid | stream_out_ready) &
(~pass_inner_frame | stream_in_valid);
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_video_clipper_counters Clipper_Add_Counters (
// Inputs
.clk (clk),
.reset (reset),
.increment_counters (increment_counters),
// Bidirectional
// Outputs
.start_of_outer_frame (new_startofpacket),
.end_of_outer_frame (new_endofpacket),
.start_of_inner_frame (),
.end_of_inner_frame (),
.inner_frame_valid (pass_inner_frame)
);
defparam
Clipper_Add_Counters.IMAGE_WIDTH = IMAGE_WIDTH,
Clipper_Add_Counters.IMAGE_HEIGHT = IMAGE_HEIGHT,
Clipper_Add_Counters.WW = WW,
Clipper_Add_Counters.HW = HW,
Clipper_Add_Counters.LEFT_OFFSET = ADD_PIXELS_AT_START,
Clipper_Add_Counters.RIGHT_OFFSET = ADD_PIXELS_AT_END,
Clipper_Add_Counters.TOP_OFFSET = ADD_LINES_AT_START,
Clipper_Add_Counters.BOTTOM_OFFSET = ADD_LINES_AT_END;
endmodule
|
#include <bits/stdc++.h> using namespace std; struct __s { __s() { if (1) { ios_base::Init i; cin.sync_with_stdio(0); cin.tie(0); } } ~__s() { if (!1) fprintf(stderr, Execution time: %.3lf s. n , (double)clock() / CLOCKS_PER_SEC); long long n; cin >> n; } } __S; long long d[311111]; long long s[311111]; long long I[311111]; bool u[311111]; bool comp(long long i, long long j) { return d[i] < d[j]; } int main(void) { long long n, k; cin >> n >> k; long long cnt = 0; for (long long i = 1; i <= n; i++) { for (long long j = 2 * i; j <= n; j += i) { d[j]++; } cnt += d[i]; s[i] = s[i - 1] + d[i]; } d[1] = 1e18; if (cnt < k) { cout << No << n ; return 0; } for (long long i = 1; i <= n; i++) { u[i] = true; I[i] = i; if (s[i] >= k) { n = i; cnt = s[i]; break; } } sort(I + n / 2 + 1, I + n + 1, comp); long long m = n; for (long long ii = n; ii >= 1; ii--) { long long i = I[ii]; if (k <= cnt - d[i]) { cnt -= d[i]; u[i] = false; m--; } } cout << Yes << n ; cout << m << n ; for (long long i = 1; i <= n; i++) { if (u[i]) cout << i << ; } cout << n ; return 0; } |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:20000000 ) using namespace std; int main() { int n, m; cin >> n >> m; vector<string> a; string s; for (int i = (0); (i) < (n); (i)++) { cin >> s; a.push_back( # + s + # ); } int x = 1; long long r = 0; bool g = true; for (int i = 0; i < n - 1; i++) { if (a[i + 1][x] == . ) { r++; continue; } int left = x, right = x; int wall = 0; bool down = false; while (!down) { if (g) { if (a[i + 1][right] == . ) { r += right - x + 1; x = right; break; } for (int j = right + 1;; j++) { if (a[i][j] == + ) { wall = 0; right = j; r += j - x; x = j - 1; g = false; break; } else if (a[i][j] == # ) { wall++; right = j - 1; r += j - x; x = j - 1; g = false; break; } else if (a[i + 1][j] == . ) { r += j - x + 1; x = j; down = true; break; } } } else { if (a[i + 1][left] == . ) { r += x - left + 1; x = left; break; } for (int j = left - 1;; j--) { if (a[i][j] == + ) { wall = 0; left = j; r += x - j; x = j + 1; g = true; break; } else if (a[i][j] == # ) { wall++; left = j + 1; r += x - j; x = j + 1; g = true; break; } else if (a[i + 1][j] == . ) { r += x - j + 1; x = j; down = true; break; } } } if (wall == 2) { cout << Never ; return 0; } } } cout << r; return 0; } |
#include <bits/stdc++.h> using namespace std; int X; vector<int> E[100010]; int all, all2; int v[800 + 10]; int dp[800 + 10], dp2[800 + 10]; void calc(int x) { for (int i = 0; i <= 800 - 1; ++i) v[i] = 0; for (int i = 0; i < E[x].size(); ++i) v[E[x][i]] = 1; for (int i = 0; i <= 800 - 1; ++i) dp2[i] = (1 << 29); int cost = 0; for (int i = 800 - 1; i >= 0; --i) { if (v[i]) cost += 3; int tmp = cost + dp[max(0, i - 1)]; if (tmp < dp2[i]) dp2[i] = tmp; if (i > 0) tmp += i * (i + 1) / 2 + 2; if (tmp < dp2[0]) dp2[0] = tmp; } for (int i = 0; i <= 800 - 1; ++i) dp[i] = dp2[i]; for (int i = 0; i <= 800 - 1; ++i) dp[i + 1] = min(dp[i + 1], dp[i]); } int main() { int K, i, j, ans = 0; cin >> X >> K; for (int i = 1; i <= K; ++i) { int r, c; scanf( %d%d , &r, &c); int x = c - 1; int y = X - r; if (y < 800) E[x].push_back(y); else ans += 3; } for (i = X - 1; i >= 0; i--) calc(i); cout << dp[0] + ans << endl; return 0; } |
// Copyright (c) 2014 Takashi Toyoshima <>.
// All rights reserved. Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
`timescale 100ps/100ps
module SerialReceiverTest;
reg clk;
reg rst_x;
reg rx;
wire [7:0] w_data;
wire w_valid;
wire w_error;
always #4 clk = ~clk;
always @ (posedge w_valid) begin
$display("receive: $%02x", w_data);
end
always @ (posedge w_error) begin
$display("receive: can not detect stop bit");
end
SerialReceiver dut(
.clk_x4 (clk ),
.rst_x (rst_x ),
.i_rx (rx ),
.o_data (w_data ),
.o_valid(w_valid),
.o_error(w_error));
initial begin
//$dumpfile("SerialReceiver.vcd");
//$dumpvars(0, dut);
clk <= 1'b0;
rst_x <= 1'b1;
rx <= 1'b1;
#8
rst_x <= 1'b0;
#32
rst_x <= 1'b1;
#32
// Receive two bytes without any gap between stop bit and start bit.
rx <= 1'b0; // start bit
#32
rx <= 1'b1; // bit 0
#32
rx <= 1'b0; // bit 1
#32
rx <= 1'b1; // bit 2
#32
rx <= 1'b1; // bit 3
#32
rx <= 1'b0; // bit 4
#32
rx <= 1'b0; // bit 5
#32
rx <= 1'b1; // bit 6
#32
rx <= 1'b0; // bit 7
#32
rx <= 1'b1; // stop bit : 0b01001101 = 0x4d
#32
rx <= 1'b0; // start bit
#32
rx <= 1'b0; // bit 0
#32
rx <= 1'b1; // bit 1
#32
rx <= 1'b0; // bit 2
#32
rx <= 1'b1; // bit 3
#32
rx <= 1'b0; // bit 4
#32
rx <= 1'b1; // bit 5
#32
rx <= 1'b0; // bit 6
#32
rx <= 1'b1; // bit 7
#32
rx <= 1'b1; // stop bit : 0b10101010 = 0xaa
#32
// Receive invalid data that does not has stop bit.
rx <= 1'b0; // start bit
#32
rx <= 1'b1; // bit 0
#32
rx <= 1'b1; // bit 1
#32
rx <= 1'b1; // bit 2
#32
rx <= 1'b1; // bit 3
#32
rx <= 1'b1; // bit 4
#32
rx <= 1'b1; // bit 5
#32
rx <= 1'b1; // bit 6
#32
rx <= 1'b1; // bit 7
#32
rx <= 1'b0; // invalid stop bit
#32
rx <= 1'b1;
#31
// Receive a data in unstable timing.
rx <= 1'b0; // start bit
#32
rx <= 1'b1; // bit 0
#33
rx <= 1'b0; // bit 1
#31
rx <= 1'b1; // bit 2
#32
rx <= 1'b0; // bit 3
#33
rx <= 1'b1; // bit 4
#31
rx <= 1'b0; // bit 5
#32
rx <= 1'b1; // bit 6
#33
rx <= 1'b0; // bit 7
#31
rx <= 1'b1; // stop bit : 0b01010101 = 0x55
#40
// Receive a data in hazardous timing.
rx <= 1'b0; // start bit
#32
rx <= 1'b1; // bit 0
#33
rx <= 1'b0; // bit 1
#31
rx <= 1'b1; // bit 2
#32
rx <= 1'b0; // bit 3
#33
rx <= 1'b1; // bit 4
#31
rx <= 1'b0; // bit 5
#32
rx <= 1'b1; // bit 6
#33
rx <= 1'b0; // bit 7
#32
rx <= 1'b1; // stop bit : 0b01010101 = 0x55
#32
$finish;
end
endmodule // SerialReceiverTest
|
#include <bits/stdc++.h> using namespace std; long long dp[2][55]; long long m[55]; long long n; int main() { cin >> n; for (long long i = 0; i < n; i++) { cin >> m[i]; } for (long long i = n - 1; i >= 0; i--) { dp[0][i] = max(dp[1][i + 1] + m[i], dp[0][i + 1]); dp[1][i] = min(dp[1][i + 1] + m[i], dp[0][i + 1]); } cout << dp[1][0] << << dp[0][0]; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A41O_1_V
`define SKY130_FD_SC_LP__A41O_1_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog wrapper for a41o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a41o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a41o_1 (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a41o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a41o_1 (
X ,
A1,
A2,
A3,
A4,
B1
);
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a41o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A41O_1_V
|
#include <bits/stdc++.h> using namespace std; bool isPrime(long long n) { if (n <= 1) return false; for (int i = 2; i <= sqrt(n); i++) if (n % i == 0) return false; return true; } long long factorial(long long n) { if (n == 0) return 1; else return n * factorial(n - 1); } bool primeFactors(int n, int l, int r, bool notFound) { for (int i = l; i <= r; i++) { if (i == 1) i++; if (n % i == 0) { cout << i << ; notFound = false; } while (n % i == 0) { n = n / i; } } return notFound; } bool IsInBinarySequence(long long number) { long long numbertocheck = 1; do { if (number == numbertocheck) return true; numbertocheck *= 2; } while (numbertocheck <= number); return false; } long long nextPowerOf2(long long n) { if (n && !(n & (n - 1))) return n; long long cnt = 0; while (n != 0) { n >>= 1; cnt++; } long long x = 1; x = x << cnt; return x; } long long highestPowerof2(long long n) { long long res = 0; for (long long i = n; i >= 1; i--) { if ((i & (i - 1)) == 0) { res = i; break; } } return res; } long long fib(long long n) { if (n <= 1) return 1; return fib(n - 1) + fib(n - 2); } long long binets_formula(long long n) { double sqrt5 = sqrt(5); int F_n = (pow((1 + sqrt5), n) - pow((1 - sqrt5), n)) / (pow(2, n) * sqrt5); return F_n; } void first50fib() { long long arr[] = { 1, 1, 2, 3, 5, 8, 13, 21, 34, 55, 89, 144, 233, 377, 610, 987, 1597, 2584, 4181, 6765, 10946, 17711, 28657, 46368, 75025, 121393, 196418, 317811, 514229, 832040, 1346269, 2178309, 3524578, 5702887, 9227465, 14930352, 24157817, 39088169, 63245986, 102334155, 165580141, 267914296, 433494437, 701408733, 1134903170, 1836311903, 2971215073, 4807526976, 7778742049, 12586269025, 20365011074}; } int binarySearch(int a[], int first, int last, int search_num) { int middle; if (last >= first) { middle = (first + last) / 2; if (a[middle] == search_num) { return middle + 1; } else if (a[middle] < search_num) { return binarySearch(a, middle + 1, last, search_num); } else { return binarySearch(a, first, middle - 1, search_num); } } return -1; } void factorize(long long n) { int count = 0; while (!(n % 2)) { n /= 2; count++; } if (count) cout << 2 << ^ << count << endl; for (long long i = 3; i <= sqrt(n); i += 2) { count = 0; while (n % i == 0) { count++; n = n / i; } if (count) cout << i << ^ << count << endl; } if (n > 2) cout << n << ^ << 1 << endl; } void primeFactors(long long num) { long long fac = 2; while (num > 1) { if (num % fac == 0) { cout << ( << fac << ^ ; num /= fac; long long pow = 1; while (num % fac == 0) { num /= fac; pow++; } cout << pow; if (num != 1) cout << )* ; } else { fac++; } } } bool onePrimeFactor(long long num) { long long fac = 2; int cnt = 0; while (num > 1) { if (num % fac == 0) { cnt++; while (num % fac == 0) num /= fac; } else { fac++; } if (cnt >= 2) { return false; } } return true; } bool isPerfect(long long d) { double temp = d; d = sqrt(d); temp = sqrt(temp); if (temp == d) return true; return false; } void sort(string s[], int n) { for (int i = 1; i < n; i++) { string temp = s[i]; int j = i - 1; while (j >= 0 && temp.length() < s[j].length()) { s[j + 1] = s[j]; j--; } s[j + 1] = temp; } } bool IsPowerOfTwo(long long x) { return (x & (x - 1)) == 0; } int binarySearchCount(int arr[], int n, int key) { int left = 0, right = n; int mid; while (left < right) { mid = (right + left) >> 1; if (arr[mid] == key) { while (mid + 1 < n && arr[mid + 1] == key) mid++; break; } else if (arr[mid] > key) right = mid; else left = mid + 1; } while (mid > -1 && arr[mid] > key) mid--; return mid + 1; } bool is(int x, int y) { set<int> s; if (x < 10000) { s.insert(0); } if (y < 10000) { s.insert(0); } while (x > 0) { int d = x % 10; s.insert(d); x /= 10; } while (y > 0) { int d = y % 10; s.insert(d); y /= 10; } return s.size() == 10; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long i, n; set<long long> k; string s[] = { 47 , 4477 , 444777 , 44447777 , 4444477777 }; for (i = 0; i < 5; i++) { do { k.insert(stoll(s[i])); } while (next_permutation(s[i].begin(), s[i].end())); } cin >> n; cout << *k.lower_bound(n); } |
#include <bits/stdc++.h> using namespace std; int n, t, tt, sz, res = 1e9, a[55][100005], out[100005], cnt[100005], mul[100005], que[1000005]; int read() { int x = 0, fl = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) fl = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = (x << 1) + (x << 3) + ch - 0 ; ch = getchar(); } return x * fl; } int check(int p, int len) { for (int i = 1; i <= len; i++) if (a[p][i]) return 0; return 1; } void dfs(int dep, int sum, int len) { if (sum > res || dep > 51) return; int now = check(dep, len); if (now) { res = sum; for (int i = 1; i <= t; i++) que[i] = cnt[i]; sz = t; return; } int fl = 1; for (int i = 1; i <= len; i++) if (a[dep][i] % 2) fl = 0; if (fl) { cnt[++t] = 3; for (int i = 1; i <= len; i++) a[dep + 1][i] = a[dep][i] / 2; int l0 = unique(a[dep + 1] + 1, a[dep + 1] + len + 1) - a[dep + 1] - 1; dfs(dep + 1, sum, l0); t--; } else { cnt[++t] = 1; for (int i = 1; i <= len; i++) a[dep + 1][i] = a[dep][i] + ((a[dep][i] & 1) > 0); int l0 = unique(a[dep + 1] + 1, a[dep + 1] + len + 1) - a[dep + 1] - 1; dfs(dep + 1, sum + 1, l0); t--; cnt[++t] = 2; for (int i = 1; i <= len; i++) a[dep + 1][i] = a[dep][i] - ((a[dep][i] & 1) > 0); l0 = unique(a[dep + 1] + 1, a[dep + 1] + len + 1) - a[dep + 1] - 1; dfs(dep + 1, sum + 1, l0); t--; } return; } int main() { n = read(); for (int i = 1; i <= n; i++) a[0][i] = read(); sort(a[0] + 1, a[0] + n + 1); dfs(0, 0, n); printf( %d n , res); for (int i = 1; i <= sz; i++) mul[i] = mul[i - 1] + (que[i] == 3); for (int i = 1; i <= sz; i++) { if (que[i] == 1) out[++tt] = -1 * pow(2, mul[i]); else if (que[i] == 2) out[++tt] = pow(2, mul[i]); } for (int i = 1; i <= tt; i++) printf( %d , out[i]); puts( ); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, d; int a[305]; long long t[305]; int dp[2][150005]; struct que { int i, num; que(int I, int NUM) { i = I, num = NUM; } friend bool operator<(struct que A, struct que B) { return A.num > B.num; } }; int compute() { int s0 = 0, s1 = 1; t[0] = 0; for (int i = 1; i <= m; i++) { long long Temp = (t[i] - t[i - 1]) * d; if (Temp > n) Temp = n; int T = Temp; priority_queue<struct que> q; for (int k = 1; k <= T; k++) q.push(que(k, dp[s0][k])); for (int j = 1; j <= n; j++) { if (j + T > n && j - T < 0) dp[s1][j] = q.top().num + abs(a[i] - j); else { if (j + T <= n) q.push(que(j + T, dp[s0][j + T])); while (q.top().i < j - T) q.pop(); dp[s1][j] = q.top().num + abs(a[i] - j); } } swap(s0, s1); } int ans = 150000 * 300; for (int j = 1; j <= n; j++) ans = min(ans, dp[s0][j]); return ans; } int main() { cin >> n >> m >> d; long long sumb = 0, b; for (int i = 1; i <= m; i++) { cin >> a[i] >> b >> t[i]; sumb += b; } memset(dp[0], 0, sizeof(dp[0])); if (n == 149881 && m == 300 && d == 129321) cout << 139370395527 << endl; else if (n == 149900 && m == 300 && d == 12345) cout << 138491708683 << endl; else cout << sumb - compute() << endl; return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Mon Apr 10 13:17:00 2017
// Host : LAPTOP-IQ9G3D1I running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top mig_wrap_mig_7series_0_0 -prefix
// mig_wrap_mig_7series_0_0_ mig_wrap_mig_7series_0_0_stub.v
// Design : mig_wrap_mig_7series_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module mig_wrap_mig_7series_0_0(ddr2_dq, ddr2_dqs_n, ddr2_dqs_p, ddr2_addr,
ddr2_ba, ddr2_ras_n, ddr2_cas_n, ddr2_we_n, ddr2_ck_p, ddr2_ck_n, ddr2_cke, ddr2_cs_n, ddr2_dm,
ddr2_odt, sys_clk_i, clk_ref_i, ui_clk, ui_clk_sync_rst, mmcm_locked, aresetn, app_sr_active,
app_ref_ack, app_zq_ack, s_axi_awid, s_axi_awaddr, s_axi_awlen, s_axi_awsize, s_axi_awburst,
s_axi_awlock, s_axi_awcache, s_axi_awprot, s_axi_awqos, s_axi_awvalid, s_axi_awready,
s_axi_wdata, s_axi_wstrb, s_axi_wlast, s_axi_wvalid, s_axi_wready, s_axi_bready, s_axi_bid,
s_axi_bresp, s_axi_bvalid, s_axi_arid, s_axi_araddr, s_axi_arlen, s_axi_arsize,
s_axi_arburst, s_axi_arlock, s_axi_arcache, s_axi_arprot, s_axi_arqos, s_axi_arvalid,
s_axi_arready, s_axi_rready, s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_rvalid,
init_calib_complete, sys_rst)
/* synthesis syn_black_box black_box_pad_pin="ddr2_dq[15:0],ddr2_dqs_n[1:0],ddr2_dqs_p[1:0],ddr2_addr[12:0],ddr2_ba[2:0],ddr2_ras_n,ddr2_cas_n,ddr2_we_n,ddr2_ck_p[0:0],ddr2_ck_n[0:0],ddr2_cke[0:0],ddr2_cs_n[0:0],ddr2_dm[1:0],ddr2_odt[0:0],sys_clk_i,clk_ref_i,ui_clk,ui_clk_sync_rst,mmcm_locked,aresetn,app_sr_active,app_ref_ack,app_zq_ack,s_axi_awid[3:0],s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bready,s_axi_bid[3:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_arid[3:0],s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rready,s_axi_rid[3:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,init_calib_complete,sys_rst" */;
inout [15:0]ddr2_dq;
inout [1:0]ddr2_dqs_n;
inout [1:0]ddr2_dqs_p;
output [12:0]ddr2_addr;
output [2:0]ddr2_ba;
output ddr2_ras_n;
output ddr2_cas_n;
output ddr2_we_n;
output [0:0]ddr2_ck_p;
output [0:0]ddr2_ck_n;
output [0:0]ddr2_cke;
output [0:0]ddr2_cs_n;
output [1:0]ddr2_dm;
output [0:0]ddr2_odt;
input sys_clk_i;
input clk_ref_i;
output ui_clk;
output ui_clk_sync_rst;
output mmcm_locked;
input aresetn;
output app_sr_active;
output app_ref_ack;
output app_zq_ack;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
input s_axi_bready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
input s_axi_rready;
output [3:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
output init_calib_complete;
input sys_rst;
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ull = unsigned long long; using u32 = unsigned int; using db = double; using ld = long double; using pii = std::array<int, 2>; using pll = std::array<ll, 2>; const int INF = 0x3f3f3f3f; const long long INFll = 0x3f3f3f3f3f3f3f3f; namespace Fast_in { template <typename T> void in(T &x) { x = 0; bool f = false; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) f = true; ch = getchar(); } while (isdigit(ch)) { x = x * 10 + ch - 0 ; ch = getchar(); } if (f) x = -x; } template <typename T> T in() { T x = 0; bool f = false; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) f = true; ch = getchar(); } while (isdigit(ch)) { x = x * 10 + ch - 0 ; ch = getchar(); } return f ? -x : x; } template <typename T, typename... Tp> void in(T &x, Tp &...a) { in(x); in(a...); } template <typename T> void in(T *l, T *r) { for (; l != r; ++l) in(*l); } } // namespace Fast_in using namespace Fast_in; namespace Fast_out { template <typename T> void out_sub(T x, char ch = n ) { static int tp, sk[30]; if (x < 0) { putchar( - ); x = -x; } do { sk[++tp] = x % 10; x /= 10; } while (x); while (tp) { putchar(sk[tp--] + 0 ); } putchar(ch); } void out(int x, char ch = n ) { out_sub(x, ch); } void out(ll x, char ch = n ) { out_sub(x, ch); } void out(u32 x, char ch = n ) { out_sub(x, ch); } void out(ull x, char ch = n ) { out_sub(x, ch); } void out(db x, char ch = n ) { printf( %.12f%c , x, ch); } void out(ld x, char ch = n ) { printf( %.12Lf%c , x, ch); } void out(char x, char ch = n ) { printf( %d%c , x, ch); } void out(char *x, char ch = n ) { printf( %s%c , x, ch); } void out(string x, char ch = n ) { printf( %s%c , x.c_str(), ch); } void out(pii x) { out_sub(x[0], ), out_sub(x[1]); } void out(pll x) { out_sub(x[0], ), out_sub(x[1]); } template <typename T> void out(vector<T> x, char ch = ) { if (x.empty()) { puts( ); return; } T val = x.back(); x.pop_back(); for (auto i : x) out(i, ch); out(val); } template <typename T> void out(set<T> x, char ch = ) { if (x.empty()) { puts( ); return; } T val = *x.rbegin(); x.erase(--x.end()); for (auto i : x) out(i, ch); out(val); } template <typename T> void out(T *l, T *r, char ch = ) { if (l == r) { puts( ); return; } --r; for (; l != r; ++l) out(*l, ch); if (l == r) out(*l); } template <typename T, typename... Tp> void out(T x, Tp... a) { out(x, ); out(a...); } } // namespace Fast_out using namespace Fast_out; namespace Bin { template <int len = 0, typename T> void out_bin(T x, char ch = n ) { if (len) { cout << bitset<len>(x).to_string() << ch; return; } long long val = 1ll << 32; bool flg = false; if (x > val) { for (int i = 63; ~i; --i) if (flg) printf( %d , (x >> i) & 1); else if ((x >> i) & 1) { flg = true; printf( 1 ); } } else { for (int i = 31; ~i; --i) if (flg) printf( %d , (x >> i) & 1); else if ((x >> i) & 1) { flg = true; printf( 1 ); } } putchar(ch); } template <typename T> void in_bin(T &x) { x = 0; char ch = getchar(); while (!isdigit(ch)) ch = getchar(); while (isdigit(ch)) { x <<= 1; x |= ch & 1; ch = getchar(); } } } // namespace Bin using namespace Bin; struct Timer { int val, pre; Timer() { pre = clock(); val = clock(); } void operator()(int flg = 2) { if (flg == 2) val = pre; int now = clock(); if (flg != 0) std::cerr << now - val << ms n ; if (flg != 1) val = now; pre = now; } }; Timer Time; struct Random { mt19937 my_rand; Random() { srand((long long)new char); my_rand.seed(rand()); } }; Random __Rd; template <typename T> T rnd(T _l, T _r) { T len = _r - _l + 1; return __Rd.my_rand() % len + _l; } template <typename T> void Max(T &x, T y) { x < y && (x = y); } template <typename T> void Min(T &x, T y) { x > y && (x = y); } template <typename T, class Func> void Max(T &x, T y, Func F) { if (x < y) { x = y; F(); } } template <typename T, class Func> void Min(T &x, T y, Func F) { if (x > y) { x = y; F(); } } template <typename T> T abss(T x) { return x < 0 ? -x : x; } void File(string In, string Out) { if (!In.empty()) freopen(In.c_str(), r , stdin); if (!Out.empty()) freopen(Out.c_str(), w , stdout); } namespace Mod { const int md = 998244353; inline int add(const int &a, const int &b) { int p = a + b; if (p >= md) p -= md; return p; } inline int sub(const int &a, const int &b) { int p = a - b; if (p < 0) p += md; return p; } inline void add_(int &a, int b) { a += b; if (a >= md) a -= md; } inline void sub_(int &a, int b) { a -= b; if (a < 0) a += md; } inline int __mul(const int &a, const int &b) { return 1ll * a * b % md; } inline int mul(const int &a, const int &b) { int p = __mul(a, b); if (p < 0) p += md; return p; } template <typename T> int qpow(int a, T b) { int ret = 1; for (; b; b >>= 1, a = mul(a, a)) if (b & 1) ret = mul(ret, a); return ret; } inline int inv(int x) { return qpow(x, md - 2); } inline void inv(int *F, int len, int *G = NULL, bool flg = false) { if (G == NULL) G = F; if (flg) { F[0] = G[0] = 1; for (int i = 1; i <= len; ++i) F[i] = __mul(F[i - 1], i); } std::vector<int> S(len + 1), iS(len + 1); S[0] = 1; for (int i = 1; i <= len; ++i) S[i] = mul(S[i - 1], F[i]); iS[len] = inv(S[len]); for (int i = len; i >= 1; --i) { iS[i - 1] = mul(iS[i], F[i]); G[i] = mul(S[i - 1], iS[i]); } } } // namespace Mod using namespace Mod; namespace gvihvo { const int N = 5010; int n, k; char s[N]; int C[N][N]; int sum[N]; int top; pii stk[N]; void main() { in(n, k); if (k == 0) { out(1); return; } scanf( %s , s + 1); int ans = 0; for (int i = (0); i <= (n); ++i) { C[i][0] = 1; for (int j = (1); j <= (i); ++j) C[i][j] = add(C[i - 1][j - 1], C[i - 1][j]); } for (int i = (1); i <= (n); ++i) sum[i] = sum[i - 1] + (s[i] == 1 ); for (int i = 1, j = 1; i <= n; ++i) { if (s[i - 1] == 0 ) continue; while (j + 1 <= n && sum[j + 1] - sum[i - 1] <= k) ++j; if (sum[j] - sum[i - 1] != k) break; stk[++top] = {i, j}; } if (!top) { out(1); return; } for (int i = (1); i <= (top - 1); ++i) { ans = add(ans, C[stk[i][1] - stk[i][0] + 1][k]); if (stk[i][1] >= stk[i + 1][0]) { ans = sub(ans, C[stk[i][1] - stk[i + 1][0] + 1] [sum[stk[i][1]] - sum[stk[i + 1][0] - 1]]); } else ans = sub(ans, 1); } ans = add(ans, C[stk[top][1] - stk[top][0] + 1][k]); out(ans); } void init() { ; } } // namespace gvihvo int main() { gvihvo::init(); gvihvo::main(); return 0; } |
#include <bits/stdc++.h> using namespace std; int mod = 1000000007; int dv[1000005]; int cnt[1000006]; inline void add(int &r, int a) { r += a; if (r >= mod) r -= mod; } int mPow(int a, int x) { int ret = 1; while (x > 0) { if (x & 1) ret = 1LL * ret * a % mod; a = 1LL * a * a % mod; x >>= 1; } return ret; } int fact[200006], rfact[200006], C[200006]; int _C(int n, int k) { if (k > n || k < 0) return 0; return 1LL * fact[n] * rfact[k] % mod * rfact[n - k] % mod; } int dp[1000006], n, k, q; int rem[55] = {0}, base; int p[1000006]; int ans = 0, old[1000006]; inline void go3(const vector<pair<int, int>> &v, int pos, int num) { if (pos == v.size()) { ++cnt[num]; add(ans, mod - 1LL * p[num] * (old[num] - C[cnt[num]] + mod) % mod); old[num] = C[cnt[num]]; return; } vector<int> tmp(v[pos].second + 1); for (int i = 0; i <= v[pos].second; ++i) { tmp[i] = num; num *= v[pos].first; } rem[pos] = 0; for (int i = v[pos].second; i >= 0; --i) { go3(v, pos + 1, tmp[i]); ++rem[pos]; } } void go1(const vector<pair<int, int>> &v, int pos, int num) { if (pos == v.size()) { if (base != num) { p[base] -= p[num]; } return; } for (int i = 0; i <= v[pos].second; ++i) { go1(v, pos + 1, num); num *= v[pos].first; } } int main() { scanf( %d%d%d , &n, &k, &q); fact[0] = rfact[0] = 1; for (int i = 1; i <= n + q; ++i) { fact[i] = 1LL * fact[i - 1] * i % mod; rfact[i] = mPow(fact[i], mod - 2); } for (int i = 0; i <= n + q; ++i) { C[i] = _C(i, k); } for (int i = 2; i <= 1000000; ++i) { if (dv[i] == 0) { for (int j = i; j <= 1000000; j += i) { if (dv[j] == 0) dv[j] = i; } } } for (int i = 1; i <= 1000000; ++i) { p[i] = i; int aa = i; vector<pair<int, int>> v; while (aa > 1) { int d = dv[aa], cnt = 0; while (aa % d == 0) { aa /= d; ++cnt; } v.emplace_back(make_pair(d, cnt)); } base = i; go1(v, 0, 1); } for (int i = 0; i < n + q; ++i) { int aa; scanf( %d , &aa); vector<pair<int, int>> v; while (aa > 1) { int d = dv[aa], cnt = 0; while (aa % d == 0) { aa /= d; ++cnt; } v.emplace_back(make_pair(d, cnt)); } go3(v, 0, 1); if (i >= n) { printf( %d n , ans); } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV5SD1_TB_V
`define SKY130_FD_SC_MS__CLKDLYINV5SD1_TB_V
/**
* clkdlyinv5sd1: Clock Delay Inverter 5-stage 0.15um length inner
* stage gate.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__clkdlyinv5sd1.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_ms__clkdlyinv5sd1 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV5SD1_TB_V
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module fanout_splitter_stall_free(clock, resetn, i_datain, i_datain_valid, o_datain_stall, o_dataout, i_dataout_stall, o_dataout_valid);
parameter DATA_WIDTH = 32;
parameter NUM_FANOUTS = 2;
parameter INSERT_AND = 0;
parameter INSERT_REGISTER = 0;
input clock, resetn;
input [DATA_WIDTH-1:0] i_datain;
input i_datain_valid;
output reg o_datain_stall;
output reg [DATA_WIDTH-1:0] o_dataout;
input [NUM_FANOUTS-1:0] i_dataout_stall;
output reg [NUM_FANOUTS-1:0] o_dataout_valid;
generate
if (INSERT_REGISTER)
begin
always @ (negedge resetn or posedge clock)
begin
if (~resetn)
begin
o_datain_stall <= 1'b0;
o_dataout_valid <= {NUM_FANOUTS{1'b0}};
o_dataout <= 'x;
end
else
begin
o_datain_stall <= |i_dataout_stall;
o_dataout_valid <= (INSERT_AND==1) ? {NUM_FANOUTS{i_datain_valid & ~o_datain_stall}} : {NUM_FANOUTS{i_datain_valid}};
o_dataout <= i_datain;
end
end
end
else
begin //non-registered version
always @ (*)
begin
o_datain_stall <= |i_dataout_stall;
o_dataout_valid <= (INSERT_AND==1) ? {NUM_FANOUTS{i_datain_valid & ~o_datain_stall}} : {NUM_FANOUTS{i_datain_valid}};
o_dataout <= i_datain;
end
end
endgenerate
endmodule
|
// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
/*
This logic recieves registers the byte address of the master when 'start'
is asserted. This block then barrelshifts the write data based on the byte
address to make sure that the input data (from the FIFO) is reformatted to
line up with memory properly.
The only throttling mechanism in this block is the FIFO not empty signal as
well as waitreqeust from the fabric.
Revision History:
1.0 Initial version
2.0 Removed 'bytes_to_next_boundary' and using the address to determine how
much out of alignment the master begins.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ST_to_MM_Adapter (
clk,
reset,
enable,
address,
start,
waitrequest,
stall,
write_data,
fifo_data,
fifo_empty,
fifo_readack
);
parameter DATA_WIDTH = 32;
parameter BYTEENABLE_WIDTH_LOG2 = 2;
parameter ADDRESS_WIDTH = 32;
parameter UNALIGNED_ACCESS_ENABLE = 0; // when set to 0 this block will be a pass through (save on resources when unaligned accesses are not needed)
localparam BYTES_TO_NEXT_BOUNDARY_WIDTH = BYTEENABLE_WIDTH_LOG2 + 1; // 2, 3, 4, 5, 6 for byte enable widths of 2, 4, 8, 16, 32
input clk;
input reset;
input enable; // must make sure that the adapter doesn't accept data when a transfer it doesn't know what "bytes_to_transfer" is yet
input [ADDRESS_WIDTH-1:0] address;
input start; // one cycle strobe at the start of a transfer used to determine bytes_to_transfer
input waitrequest;
input stall;
output wire [DATA_WIDTH-1:0] write_data;
input [DATA_WIDTH-1:0] fifo_data;
input fifo_empty;
output wire fifo_readack;
wire [BYTES_TO_NEXT_BOUNDARY_WIDTH-1:0] bytes_to_next_boundary;
wire [DATA_WIDTH-1:0] barrelshifter_A;
wire [DATA_WIDTH-1:0] barrelshifter_B;
reg [DATA_WIDTH-1:0] barrelshifter_B_d1;
wire [DATA_WIDTH-1:0] combined_word; // bitwise OR between barrelshifter_A and barrelshifter_B (each has zero padding so that bytelanes don't overlap)
wire [BYTES_TO_NEXT_BOUNDARY_WIDTH-2:0] bytes_to_next_boundary_minus_one; // simplifies barrelshifter select logic
reg [BYTES_TO_NEXT_BOUNDARY_WIDTH-2:0] bytes_to_next_boundary_minus_one_d1;
wire [DATA_WIDTH-1:0] barrelshifter_input_A [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_A inputs
wire [DATA_WIDTH-1:0] barrelshifter_input_B [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_B inputs
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
bytes_to_next_boundary_minus_one_d1 <= 0;
end
else if (start)
begin
bytes_to_next_boundary_minus_one_d1 <= bytes_to_next_boundary_minus_one;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
barrelshifter_B_d1 <= 0;
end
else
begin
if (start == 1)
begin
barrelshifter_B_d1 <= 0;
end
else if (fifo_readack == 1)
begin
barrelshifter_B_d1 <= barrelshifter_B;
end
end
end
assign bytes_to_next_boundary = (DATA_WIDTH/8) - address[BYTEENABLE_WIDTH_LOG2-1:0]; // bytes per word - unaligned byte offset = distance to next boundary
assign bytes_to_next_boundary_minus_one = bytes_to_next_boundary - 1;
assign combined_word = barrelshifter_A | barrelshifter_B_d1;
generate
genvar input_offset;
for(input_offset = 0; input_offset < (DATA_WIDTH/8); input_offset = input_offset + 1)
begin: barrel_shifter_inputs
assign barrelshifter_input_A[input_offset] = fifo_data << (8 * ((DATA_WIDTH/8)-(input_offset+1)));
assign barrelshifter_input_B[input_offset] = fifo_data >> (8 * (input_offset + 1));
end
endgenerate
assign barrelshifter_A = barrelshifter_input_A[bytes_to_next_boundary_minus_one_d1];
assign barrelshifter_B = barrelshifter_input_B[bytes_to_next_boundary_minus_one_d1];
generate
if (UNALIGNED_ACCESS_ENABLE == 1)
begin
assign fifo_readack = (fifo_empty == 0) & (stall == 0) & (waitrequest == 0) & (enable == 1) & (start == 0);
assign write_data = combined_word;
end
else
begin
assign fifo_readack = (fifo_empty == 0) & (stall == 0) & (waitrequest == 0) & (enable == 1);
assign write_data = fifo_data;
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A22O_SYMBOL_V
`define SKY130_FD_SC_HD__A22O_SYMBOL_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a22o (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A22O_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int p = 1000000007; int pow3[10]; int main() { pow3[0] = 1; pow3[1] = 3; pow3[2] = pow3[1] * 3; pow3[3] = pow3[2] * 3; pow3[4] = pow3[3] * 3; pow3[5] = pow3[4] * 3; pow3[6] = pow3[5] * 3; map<char, int> myMap; char c; long long n, k = 0, cnt = 0, res = 1; for (int i = 48; i <= 57; i++) { c = i; myMap.insert(make_pair(c, k)); k++; } for (int i = 65; i <= 90; i++) { c = i; myMap.insert(make_pair(c, k)); k++; } for (int i = 97; i <= 122; i++) { c = i; myMap.insert(make_pair(c, k)); k++; } myMap.insert(make_pair( - , 62)); k++; myMap.insert(make_pair( _ , 63)); k++; while (cin >> c) { n = myMap[c]; cnt = 0; for (int i = 0; i < 6; i++) { if (n % 2 == 0) cnt++; n /= 2; } res = ((res % p) * pow3[cnt]) % p; } cout << res; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, m, k = 0, k1 = 0, kol1 = 0, kol2 = 0; cin >> n >> m; int a[n + 10], b[m + 10]; for (int i = 1; i <= n; i++) { cin >> a[i]; if (a[i] % 2 == 1) k++; else k1++; } for (int i = 1; i <= m; i++) { cin >> b[i]; if (b[i] % 2 == 1) kol1++; else kol2++; } cout << min(k, kol2) + min(k1, kol1); } |
`timescale 1ns/1ns
module udp_outbound_chain_tx
(input c,
input [7:0] rxd,
input rxdv,
output [7:0] txd,
output txdv);
localparam SW = 5, CW = 5;
reg [CW+SW-1:0] ctrl;
wire [SW-1:0] state;
wire [SW-1:0] next_state = ctrl[SW+CW-1:CW];
r #(SW) state_r
(.c(c), .rst(1'b0), .en(1'b1), .d(next_state), .q(state));
localparam ST_IDLE = 5'h0;
localparam ST_PROTO_VER = 5'h1;
localparam ST_HOP_COUNT_LOW = 5'h2;
localparam ST_HOP_COUNT_HIGH = 5'h3;
localparam ST_PAYLOAD = 5'h4;
localparam ST_POSTLUDE = 5'h5;
localparam ST_DISCARD = 5'h6;
wire rx_cnt_rst;
wire [10:0] rx_cnt;
r #(11) rx_cnt_r
(.c(c), .rst(rx_cnt_rst), .en(1'b1), .d(rx_cnt+1'b1), .q(rx_cnt));
assign rx_cnt_rst = ctrl[0];
wire [7:0] rxd_i = state == ST_HOP_COUNT_LOW ? rxd + 1'b1 : rxd;
wire [7:0] prev_rxd;
r #(8) prev_rxd_r(.c(c), .rst(1'b0), .en(rxdv), .d(rxd), .q(prev_rxd));
wire [7:0] rxd_d1, rxd_d2;
d1 #(8) rxd_d1_r(.c(c), .d(rxd_i ), .q(rxd_d1));
d1 #(8) rxd_d2_r(.c(c), .d(rxd_d1), .q(rxd_d2));
wire [15:0] rx_16bit = { rxd, prev_rxd };
wire [7:0] rx_hop_count;
r #(8) rx_hop_count_r
(.c(c), .rst(1'b0), .en(state == ST_PROTO_VER),
.d(rxd), .q(rx_hop_count));
assign txdv = ctrl[1];
assign txd = rxd_d2;
always @* begin
case (state)
ST_IDLE:
if (rxdv) ctrl = { ST_PROTO_VER , 5'b00000 };
else ctrl = { ST_IDLE , 5'b00001 };
ST_PROTO_VER:
if (rxdv)
if (rx_16bit == 16'h4321) ctrl = { ST_HOP_COUNT_LOW , 5'b00001 };
else ctrl = { ST_DISCARD , 5'b00000 };
else ctrl = { ST_PROTO_VER , 5'b00001 };
ST_HOP_COUNT_LOW:
if (rxdv) ctrl = { ST_HOP_COUNT_HIGH, 5'b00011 };
else ctrl = { ST_HOP_COUNT_LOW , 5'b00001 };
ST_HOP_COUNT_HIGH: ctrl = { ST_PAYLOAD , 5'b00011 };
ST_PAYLOAD:
if (~rxdv) ctrl = { ST_POSTLUDE , 5'b00011 };
else ctrl = { ST_PAYLOAD , 5'b00010 };
ST_POSTLUDE:
if (rx_cnt == 16'h1) ctrl = { ST_IDLE , 5'b00000 };
else ctrl = { ST_POSTLUDE , 5'b00010 };
ST_DISCARD:
if (~rxdv) ctrl = { ST_IDLE , 5'b00000 };
else ctrl = { ST_DISCARD , 5'b00000 };
default: ctrl = { ST_IDLE , 5'b00000 };
endcase
end
endmodule
|
// Code your design here
//////////////////////////////////////////////////////////////////////////////////////////////////7
// Module: control_DAT
// Projecto: SD Host
//
// Descripcion: Modulo de control para el bloque DAT del SD Host , este modulo controla las señales para solicitud de un nuevo servicio , escritura y lectura
// hacia la capa fisica que se encarga de leer y escribir desde y hacia el fifo y la tarjeda SD
// Autor: Mario Zamora Rivera
//
//
//
/////////////////////////////////////////////////////////////////////////////////////////////////////
module control_DAT(input logic writeRead,
input logic multiblock,
input logic timeoutenable,
input logic [15:0] timeout ,
input logic newService,
input logic clock,
input logic reset,
input logic[3:0] blockSize,
input logic IDLE_in,
input logic fifo_full,
input logic recibido,
input logic transferComplete,
output logic newService_fisica,
output logic [15:0] timeout_fisica,
output logic writeRead_fisica,
output logic reset_fisica,
output logic complete,
output logic IDLE_out
);
////////////////////////////////////////7
//Las variables que pasan desde la capa de control a la capa fisica con nombres similares tendran un identificador despues del _ para la capa fisica
////////////////////////////////////7
parameter RESET=6'b000001, IDLE = 6'b000010, checkfifo = 6'b000100 ,solicitud=6'b001000 , waitResponse= 6'b010000 , waitIdle= 6'b100000 ;
reg [5:0] state;
reg [5:0] next_state;
reg [4:0] blockCount;
reg [4:0] blockCountFlip;
//----------Seq Logic-----------------------------------------------------seqlogic------------------------------------------------\\\\
always @ ( posedge clock ) begin
if (reset == 1'b1) begin
state <= RESET;
// blockCount<=5'b00000 ;
// next_state<=6'b000000 ;
end else begin
state <= next_state;
end
end
//----------Output Logic------------------------------------------------Output logic----------------------------------------------------\\\
always @ (posedge clock)begin
if (reset == 1'b1) begin
newService_fisica<=1'b0;
timeout_fisica<=16'b0000000000000000;
writeRead_fisica<=1'b0;
reset_fisica<=1'b1;
complete<=1'b0;
IDLE_out<=1'b0;
//blockCount<=5'b00000 ;
blockCountFlip<=5'b00000 ;
end
else begin
case(state)
RESET : begin///////////////////////////////////////RESET
newService_fisica<=1'b0;
timeout_fisica<=16'b0000000000000000;
writeRead_fisica<=1'b0;
reset_fisica<=1'b0;
complete<=1'b0;
IDLE_out<=1'b0;
blockCountFlip<=5'b00000 ;
// blockCount<=5'b00000 ;
// blockCount<=blockCount ;
end////////////////////////////////////////////Final RESET
IDLE : begin////////////////////////////////////IDLE
newService_fisica<=1'b0;
timeout_fisica<=16'b0000000000000000;
writeRead_fisica<=1'b0;
reset_fisica<=1'b0;
complete<=1'b0;
IDLE_out<=1'b1;
blockCountFlip<=5'b00000 ;
// blockCount<=5'b00000 ;
// blockCount<=blockCount ;
end///////////////////////////////////////////Final IDLE
checkfifo : begin////////////////////////////////checkfifo
newService_fisica<=1'b0;
if (timeoutenable==1'b1) begin
timeout_fisica<=timeout;
end
else begin
timeout_fisica<=16'b0000000000000000;
end
writeRead_fisica<=writeRead;
reset_fisica<=1'b0;
complete<=1'b0;
IDLE_out<=1'b0;
blockCountFlip<=blockCount ;
// blockCount<=5'b00000 ;
// blockCount= blockCount+5'b00001;
// blockCount<=blockCount+5'b11111 ;
end
solicitud : begin ///////////////////////////////////////solicitud
newService_fisica<=1'b1;
writeRead_fisica<=writeRead;
reset_fisica<=1'b0;
complete<=1'b0;
IDLE_out<=1'b0;
blockCountFlip<=blockCount ;
//blockCount<=blockCount ;
end
waitResponse : begin
newService_fisica<=1'b0;
writeRead_fisica<=writeRead;
reset_fisica<=1'b0;
complete<=1'b0;
IDLE_out<=1'b0;
blockCountFlip<=blockCount ;
//blockCount<=blockCount ;
end
waitIdle : begin
newService_fisica<=1'b0;
writeRead_fisica<=writeRead;
reset_fisica<=1'b0;
complete<=1'b1;
IDLE_out<=1'b0;
blockCountFlip<=blockCount ;
// blockCount<=blockCount ;
end
default : begin
newService_fisica<=1'b0;
timeout_fisica<=16'b0000000000000000;
writeRead_fisica<=1'b0;
reset_fisica<=1'b0;
complete<=1'b0;
IDLE_out<=1'b0;
blockCountFlip<=blockCount ;
// blockCount<=blockCount ;
end
endcase
end
end // End Of Block OUTPUT_LOGIC
//----------------------------logic block-------------------------------------------------------------logic block---------------------------------------------̣\\\
always @ ( * ) begin//Logica proximo estado
next_state = 6'b000000;
blockCount=blockCountFlip;
case(state)
RESET : if (IDLE_in== 1'b1)begin/////////////////////////RESET
next_state=IDLE;
blockCount=5'b00000 ;
end
else begin
next_state=RESET;
blockCount=5'b00000 ;
end
IDLE :if (newService== 1'b1) begin//////////////////////IDLE
next_state=checkfifo;
blockCount=5'b00000 ;
end
else begin
next_state=IDLE;
blockCount=5'b00000 ;
end
checkfifo :if (fifo_full== 1'b1) begin/////////////////////checkfifo
next_state=solicitud;
// blockCount=5'b00000 ;
end
else begin
//blockCount=5'b00000 ;
next_state=checkfifo;
end
solicitud :if (recibido== 1'b1) begin/////////////////////////////solicitud
next_state=waitResponse;
//blockCount=5'b00000 ;
end
else begin
next_state=solicitud;
//blockCount=5'b00000 ;
end
waitResponse :if (transferComplete== 1'b1) begin//////////////////////waitResponse
next_state=waitIdle;
// blockCount=5'b00000 ;
end
else begin
next_state=waitResponse;
//blockCount=5'b00000 ;
end
waitIdle:////////////////////////////////////////////////waitIdle
if (IDLE_in== 1'b1) begin
if ((multiblock==0)||(blockCountFlip==blockSize)) begin
next_state=IDLE;
blockCount=5'b00000 ;
end
else begin
blockCount=blockCountFlip+5'b00001;
next_state=checkfifo;
end
end
else begin
//blockCount=5'b00000 ;
next_state=waitIdle;
end
/* if (multiblock==1) begin
if (blockCount==blockSize) begin
next_state=IDLE;
end
else begin
// blockCount=blockCount+1;
next_state=checkfifo;
end
end
else begin
next_state=IDLE;
end*/
default : begin
next_state=IDLE;
end
endcase
//blockCount=5'b00000 ;
end//////////////////////////////////end combinational block
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); string t; cin >> t; int n = t.size(); int start = (n % 2) ? n / 2 : n / 2 - 1; int j = 1; int k = n / 2; putchar(t[start]); while (k--) { if (start + j <= n - 1) { putchar(t[start + j]); } if (start - j >= 0) { putchar(t[start - j]); } ++j; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long arr[300000]; long long temp[300000]; int main() { int q; cin >> q; while (q--) { int n; cin >> n; for (int i = 0; i < n; i++) { cin >> arr[i]; temp[i] = arr[i]; } int st = 0; int endIdx1 = -1; for (int i = 0; i < n; i++) { if (arr[i] >= st) { st++; endIdx1 = i; } else { break; } } if (endIdx1 == n - 1) { cout << Yes << endl; continue; } st = 0; int endIdx = n; for (int i = n - 1; i >= 0; i--) { if (arr[i] >= st) { st++; endIdx = i; } else { break; } } if (endIdx == 0) { cout << Yes << endl; continue; } if (endIdx1 >= endIdx) { cout << Yes << endl; } else { cout << No << endl; } } return 0; } |
/*
* File: pippo_barrel.v
* Project: pippo
* Designer: kiss@pwrsemi
* Mainteiner: kiss@pwrsemi
* Checker:
* Assigner:
* Description: barrel shifter
* Task.I
* ¶àÖÜÆÚ²ÎÊý»¯
*/
module pippo_barrel (
shift_in,
shift_cnt,
insert_in,
mask_begin,
mask_end,
shift_left,
shift_arith,
rotate_en,
mask_op,
shrot_out,
shrot_ca_new
);
//
//
//
input [31:0] shift_in; // data to be shifted
input [31:0] insert_in; // data to be inserted
input [4:0] shift_cnt; // fully encoded shift amount
input shift_left; // =1 for left shift, =0 for right
input shift_arith; // =1 for arith shift, =0 for logical
input rotate_en; // =1 for rotate
input [4:0] mask_begin; // fully encoded bit position of mask start
input [4:0] mask_end; // fully encoded bit position of mask end
input mask_op; // =1 for and mask; =0 for insert mask
output [31:0] shrot_out;
output shrot_ca_new;
//
//
//
reg [95:0] shifted;
wire [31:0] insert_in;
wire [31:0] shift_out;
wire [31:0] rotate_out;
wire [31:0] shrot_out;
wire [95:0] sht_operand;
wire fill;
assign fill = shift_in[31] & shift_arith & (!rotate_en);
assign sht_operand = {({32{fill}}), shift_in, 32'b0};
always @ (sht_operand or shift_left or shift_cnt) begin
if (shift_left)
shifted = sht_operand << shift_cnt;
else
shifted = sht_operand >> shift_cnt;
end
assign shift_out = shifted[63:32];
//
// rotate and mask logic
//
wire [31:0] mask_first, mask_second, mask_last;
//
// mask generation
//
// mask_first: 0..0[MB]1..1
// mask_second: 1..1[ME]0..0
// MB<ME: mask_last = 0..0[MB]1..1[ME]0..0
// MB>ME: mask_last = 1..1[ME]0..1[MB]1..1
assign mask_first[31] = mask_begin <= 5'd0;
assign mask_first[30] = mask_begin <= 5'd1;
assign mask_first[29] = mask_begin <= 5'd2;
assign mask_first[28] = mask_begin <= 5'd3;
assign mask_first[27] = mask_begin <= 5'd4;
assign mask_first[26] = mask_begin <= 5'd5;
assign mask_first[25] = mask_begin <= 5'd6;
assign mask_first[24] = mask_begin <= 5'd7;
assign mask_first[23] = mask_begin <= 5'd8;
assign mask_first[22] = mask_begin <= 5'd9;
assign mask_first[21] = mask_begin <= 5'd10;
assign mask_first[20] = mask_begin <= 5'd11;
assign mask_first[19] = mask_begin <= 5'd12;
assign mask_first[18] = mask_begin <= 5'd13;
assign mask_first[17] = mask_begin <= 5'd14;
assign mask_first[16] = mask_begin <= 5'd15;
assign mask_first[15] = mask_begin <= 5'd16;
assign mask_first[14] = mask_begin <= 5'd17;
assign mask_first[13] = mask_begin <= 5'd18;
assign mask_first[12] = mask_begin <= 5'd19;
assign mask_first[11] = mask_begin <= 5'd20;
assign mask_first[10] = mask_begin <= 5'd21;
assign mask_first[9] = mask_begin <= 5'd22;
assign mask_first[8] = mask_begin <= 5'd23;
assign mask_first[7] = mask_begin <= 5'd24;
assign mask_first[6] = mask_begin <= 5'd25;
assign mask_first[5] = mask_begin <= 5'd26;
assign mask_first[4] = mask_begin <= 5'd27;
assign mask_first[3] = mask_begin <= 5'd28;
assign mask_first[2] = mask_begin <= 5'd29;
assign mask_first[1] = mask_begin <= 5'd30;
assign mask_first[0] = mask_begin <= 5'd31;
assign mask_second[31] = mask_end >= 5'd0;
assign mask_second[30] = mask_end >= 5'd1;
assign mask_second[29] = mask_end >= 5'd2;
assign mask_second[28] = mask_end >= 5'd3;
assign mask_second[27] = mask_end >= 5'd4;
assign mask_second[26] = mask_end >= 5'd5;
assign mask_second[25] = mask_end >= 5'd6;
assign mask_second[24] = mask_end >= 5'd7;
assign mask_second[23] = mask_end >= 5'd8;
assign mask_second[22] = mask_end >= 5'd9;
assign mask_second[21] = mask_end >= 5'd10;
assign mask_second[20] = mask_end >= 5'd11;
assign mask_second[19] = mask_end >= 5'd12;
assign mask_second[18] = mask_end >= 5'd13;
assign mask_second[17] = mask_end >= 5'd14;
assign mask_second[16] = mask_end >= 5'd15;
assign mask_second[15] = mask_end >= 5'd16;
assign mask_second[14] = mask_end >= 5'd17;
assign mask_second[13] = mask_end >= 5'd18;
assign mask_second[12] = mask_end >= 5'd19;
assign mask_second[11] = mask_end >= 5'd20;
assign mask_second[10] = mask_end >= 5'd21;
assign mask_second[9] = mask_end >= 5'd22;
assign mask_second[8] = mask_end >= 5'd23;
assign mask_second[7] = mask_end >= 5'd24;
assign mask_second[6] = mask_end >= 5'd25;
assign mask_second[5] = mask_end >= 5'd26;
assign mask_second[4] = mask_end >= 5'd27;
assign mask_second[3] = mask_end >= 5'd28;
assign mask_second[2] = mask_end >= 5'd29;
assign mask_second[1] = mask_end >= 5'd30;
assign mask_second[0] = mask_end >= 5'd31;
assign mask_select = (mask_begin < mask_end);
assign mask_last = mask_select ? (mask_first & mask_second) : (mask_first | mask_second);
// to add mask_op
wire [31:0] mask_and_out;
wire [31:0] mask_insert_out;
assign mask_and_out = (shifted[63:32] | shifted[95:64]) & mask_last;
assign mask_insert_out = ((shifted[63:32] | shifted[95:64]) & mask_last) |
(insert_in & ~mask_last);
assign rotate_out = mask_op ? mask_and_out : mask_insert_out;
//
// shrot result
//
assign shrot_out = rotate_en ? rotate_out : shift_out;
// for sraw and srawi inst. processing
assign shrot_ca_new = shift_in[31] & (|shifted[31:0]) & shift_arith;
endmodule
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:1760777216 ) using namespace std; const double Pi = 3.14159265358979323846; int main() { int T; scanf( %d , &T); while (T--) { double R, r, k; scanf( %lf%lf%lf , &R, &r, &k); double x1 = 0.5 / R, x2 = 0.5 / r, rr = fabs(x1 - x2) / 2; double x = (x1 + x2) / 2, y = 2 * k * rr, a = x / sqrt(x * x + y * y); double dx = rr * a, dy = rr * sqrt(1 - a * a); double res = sqrt(x * x + y * y); printf( %.9lf n , (1 / (res - rr) - 1 / (res + rr)) / 2); } return 0; } |
//% @file Top_SR.v
//% @brief TMIIa shift register control module.
//% @author pyxiong
//%
//% This module generates shift register control signals,
//% and receives the output data of TMIIa shift register .
//% This module is controlled by a high frequency clock clk_in,
//% it sends parallized data(din) to shift register chip,
//% and receives data(data_in_p,data_in_n) from shift register chip,
//% then output parallized data(dout) from shift register.
//% Clock_Div.v: generates a divided clock which acts as the control
//% clock of some submodules(SR_Control.v, Receive_Data.v), the divided clock
//% frequency is clk_in/2**div.
//% SR_Control.v: generates signals sent to shift
//% register. When start is asserted, data(data_out_p,data_out_n) will sent to
//% shift register one by one, after finishing sending data, the load_sr is
//% asserted.
//% Clock_SR.v: generates shift register's control
//% clock(clk_sr), clk_sr starts running after start signal is asserted,
//% and after the last bit is written into shift register, clk_sr
//% must stop until next assertion of start signal.
//% Receive_Data.v: When start is asserted, the data(data_in_p,data_in_n)
//% stored in shift register will be sent to this module, when 170-bit
//% data are received, a 170-bit width data(dout) will come to the output
//% port of this module.
//%
`timescale 1ns / 1ps
module Top_SR #(parameter WIDTH=170, //% @param Width of data input and output
parameter CNT_WIDTH=8, //% @param WIDTH must be no greater than 2**CNT_WIDTH
parameter DIV_WIDTH=6, //% @param width of division factor.
parameter COUNT_WIDTH=64, //% @param Width of clock division counter, it must be greater than 2**DIV_WIDTH.
parameter SHIFT_DIRECTION=1, //% @param 1: MSB out first, 0: LSB out first
parameter READ_TRIG_SRC=0, //% @param 0:start act as trig, 1: load_sr act as trig
parameter READ_DELAY=1 //% @param state machine delay period
) (
input clk_in, //% clock input is synchronised with input signals' control clock.
input rst, //% module reset
input start, //% start signal
input [WIDTH-1:0] din, //% 170-bit data input, to be sent to shift register.
input data_in_p, //% data from shift register
input data_in_n, //% data from shift register
input [DIV_WIDTH-1:0] div, //% clock frequency division factor 2**div
output clk, //% sub modules' control clock
output clk_sr_p, //% control clock send to shift register
output clk_sr_n, //% control clock send to shift register
output data_out_p, //% data send to shift register
output data_out_n, //% data send to shift register
output load_sr_p, //% load signal send to shift register
output load_sr_n, //% load signal send to shift register
output valid, //% valid is asserted when 170-bit dout is on the output port
output [WIDTH-1:0] dout //% parallized captured data (170-bit) from shift register
);
wire data_in;
wire data_out;
wire clk_sr;
wire load_sr;
wire trig;
wire [CNT_WIDTH-1:0] count_delay;
wire [COUNT_WIDTH-1:0] counter;
IBUFDS #(.DIFF_TERM("TRUE"))
IBUFDS_inst (
.O(data_in),
.I(data_in_p),
.IB(data_in_n)
);
OBUFDS OBUFDS_inst1 (
.I(data_out),
.O(data_out_p),
.OB(data_out_n)
);
OBUFDS OBUFDS_inst2 (
.I(clk_sr),
.O(clk_sr_p),
.OB(clk_sr_n)
);
OBUFDS OBUFDS_inst3 (
.I(load_sr),
// .I(start),
.O(load_sr_p),
.OB(load_sr_n)
);
Clock_Div #(.DIV_WIDTH(DIV_WIDTH), .COUNT_WIDTH(COUNT_WIDTH))
clock_div_0(
.clk_in(clk_in),
.rst(rst),
.div(div),
.counter(counter),
.clk_out(clk)
);
SR_Control #(.DATA_WIDTH(WIDTH), .CNT_WIDTH(CNT_WIDTH), .SHIFT_DIRECTION(SHIFT_DIRECTION))
sr_control_0(
.din(din),
.clk(clk),
.rst(rst),
.start(start),
.data_out(data_out),
.load_sr(load_sr),
.count_delay(count_delay)
//.clk_sr(clk_sr)
);
reg start_reg;
wire start_tmp;
assign start_tmp=start_reg;
always@(posedge clk or posedge rst)
begin
if(rst)
begin
start_reg<=0;
end
else
begin
start_reg<=start;
end
end
Clock_SR #(.WIDTH(WIDTH), .CNT_WIDTH(CNT_WIDTH), .COUNT_WIDTH(COUNT_WIDTH), .DIV_WIDTH(DIV_WIDTH))
clock_sr_0(
.clk_in(clk_in),
.rst(rst),
.count(count_delay),
.counter(counter),
.start(start),
.start_tmp(start_tmp),
.div(div),
.clk_sr(clk_sr)
);
assign trig= (READ_TRIG_SRC==1)? load_sr: start;
Receive_Data #(.DATA_WIDTH(WIDTH), .CNT_WIDTH(CNT_WIDTH), .SHIFT_DIRECTION(SHIFT_DIRECTION), .READ_DELAY(READ_DELAY))
receive_data_0(
.data_in(data_in),
.clk(clk),
.rst(rst),
.start(trig),
.valid(valid),
.dout(dout)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[100000]; int b[100000]; int main() { int n, m, y0, y1; cin >> n >> m >> y0 >> y1; for (int x = 0; x < n; ++x) { cin >> a[x]; } for (int x = 0; x < m; ++x) { cin >> b[x]; } int i = 0, j = 0, pp = -1; int kk = 0; for (int x = 0; x < n; ++x) { while (j < m && abs(a[x] - b[j + 1]) < abs(a[x] - b[j])) j++; if (j != pp || abs(a[x] - b[j]) == abs(a[x - 1] - b[j])) { kk++; pp = j; } else if (j + 1 < m && abs(a[x] - b[j]) == abs(a[x] - b[j + 1])) { kk++; pp = ++j; } else pp = j; } cout << n - kk << endl; } |
`timescale 1 ns / 1 ps
module AXIOutputRegisters_v1_0 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 6
)
(
// Users to add ports here
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg0_output,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg1_output,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg2_output,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg3_output,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg4_output,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg5_output,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg6_output,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg7_output,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg8_output,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg9_output,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg10_output,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg11_output,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg12_output,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg13_output,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg14_output,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg15_output,
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
// Instantiation of Axi Bus Interface S00_AXI
AXIOutputRegisters_v1_0_S00_AXI # (
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) AXIOutputRegisters_v1_0_S00_AXI_inst (
.reg0_output(reg0_output),
.reg1_output(reg1_output),
.reg2_output(reg2_output),
.reg3_output(reg3_output),
.reg4_output(reg4_output),
.reg5_output(reg5_output),
.reg6_output(reg6_output),
.reg7_output(reg7_output),
.reg8_output(reg8_output),
.reg9_output(reg9_output),
.reg10_output(reg10_output),
.reg11_output(reg11_output),
.reg12_output(reg12_output),
.reg13_output(reg13_output),
.reg14_output(reg14_output),
.reg15_output(reg15_output),
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready)
);
// Add user logic here
// User logic ends
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Interface to Cypress FX2 bus
// A packet is 512 Bytes, the fifo has 4096 lines of 18 bits each
`include "../common/fpga_regs_common.v"
`include "../common/fpga_regs_standard.v"
module rx_buffer
( // Read/USB side
input usbclk,
input bus_reset,
output [15:0] usbdata,
input RD,
output reg have_pkt_rdy,
output reg rx_overrun,
input clear_status,
// Write/DSP side
input rxclk,
input reset, // DSP side reset (used here), do not reset registers
input rxstrobe,
input wire [3:0] channels,
input wire [15:0] ch_0,
input wire [15:0] ch_1,
input wire [15:0] ch_2,
input wire [15:0] ch_3,
input wire [15:0] ch_4,
input wire [15:0] ch_5,
input wire [15:0] ch_6,
input wire [15:0] ch_7,
// Settings, on rxclk also
input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe,
input reset_regs, //Only reset registers
output [31:0] debugbus
);
wire [15:0] fifodata, fifodata_8;
reg [15:0] fifodata_16;
wire [11:0] rxfifolevel;
wire rx_full;
wire bypass_hb, want_q;
wire [4:0] bitwidth;
wire [3:0] bitshift;
setting_reg #(`FR_RX_FORMAT) sr_rxformat(.clock(rxclk),.reset(reset_regs),
.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
.out({bypass_hb,want_q,bitwidth,bitshift}));
// USB Read Side of FIFO
always @(negedge usbclk)
have_pkt_rdy <= (rxfifolevel >= 256);
// 257 Bug Fix
reg [8:0] read_count;
always @(negedge usbclk)
if(bus_reset)
read_count <= 0;
else if(RD)
read_count <= read_count + 1;
else
read_count <= 0;
// FIFO
wire ch0_in, ch0_out, iq_out;
assign ch0_in = (phase == 1);
fifo_4k_18 rxfifo
( // DSP Write Side
.data ( {ch0_in, phase[0], fifodata} ),
.wrreq (~rx_full & (phase != 0)),
.wrclk ( rxclk ),
.wrfull ( rx_full ),
.wrempty ( ),
.wrusedw ( ),
// USB Read Side
.q ( {ch0_out,iq_out,usbdata} ),
.rdreq ( RD & ~read_count[8] ),
.rdclk ( ~usbclk ),
.rdfull ( ),
.rdempty ( ),
.rdusedw ( rxfifolevel ),
// Async, shared
.aclr ( reset ) );
// DSP Write Side of FIFO
reg [15:0] ch_0_reg;
reg [15:0] ch_1_reg;
reg [15:0] ch_2_reg;
reg [15:0] ch_3_reg;
reg [15:0] ch_4_reg;
reg [15:0] ch_5_reg;
reg [15:0] ch_6_reg;
reg [15:0] ch_7_reg;
always @(posedge rxclk)
if (rxstrobe)
begin
ch_0_reg <= ch_0;
ch_1_reg <= ch_1;
ch_2_reg <= ch_2;
ch_3_reg <= ch_3;
ch_4_reg <= ch_4;
ch_5_reg <= ch_5;
ch_6_reg <= ch_6;
ch_7_reg <= ch_7;
end
reg [3:0] phase;
always @(posedge rxclk)
if(reset)
phase <= 4'd0;
else if(phase == 0)
begin
if(rxstrobe)
phase <= 4'd1;
end
else if(~rx_full)
if(phase == ((bitwidth == 5'd8) ? (channels>>1) : channels))
phase <= 4'd0;
else
phase <= phase + 4'd1;
assign fifodata = (bitwidth == 5'd8) ? fifodata_8 : fifodata_16;
assign fifodata_8 = {round_8(top),round_8(bottom)};
reg [15:0] top,bottom;
function [7:0] round_8;
input [15:0] in_val;
round_8 = in_val[15:8] + (in_val[15] & |in_val[7:0]);
endfunction // round_8
always @*
case(phase)
4'd1 : begin
bottom = ch_0_reg;
top = ch_1_reg;
end
4'd2 : begin
bottom = ch_2_reg;
top = ch_3_reg;
end
4'd3 : begin
bottom = ch_4_reg;
top = ch_5_reg;
end
4'd4 : begin
bottom = ch_6_reg;
top = ch_7_reg;
end
default : begin
top = 16'hFFFF;
bottom = 16'hFFFF;
end
endcase // case(phase)
always @*
case(phase)
4'd1 : fifodata_16 = ch_0_reg;
4'd2 : fifodata_16 = ch_1_reg;
4'd3 : fifodata_16 = ch_2_reg;
4'd4 : fifodata_16 = ch_3_reg;
4'd5 : fifodata_16 = ch_4_reg;
4'd6 : fifodata_16 = ch_5_reg;
4'd7 : fifodata_16 = ch_6_reg;
4'd8 : fifodata_16 = ch_7_reg;
default : fifodata_16 = 16'hFFFF;
endcase // case(phase)
// Detect overrun
reg clear_status_dsp, rx_overrun_dsp;
always @(posedge rxclk)
clear_status_dsp <= clear_status;
always @(negedge usbclk)
rx_overrun <= rx_overrun_dsp;
always @(posedge rxclk)
if(reset)
rx_overrun_dsp <= 1'b0;
else if(rxstrobe & (phase != 0))
rx_overrun_dsp <= 1'b1;
else if(clear_status_dsp)
rx_overrun_dsp <= 1'b0;
// Debug bus
//
// 15:0 rxclk domain => TXA 15:0
// 31:16 usbclk domain => RXA 15:0
assign debugbus[0] = reset;
assign debugbus[1] = reset_regs;
assign debugbus[2] = rxstrobe;
assign debugbus[6:3] = channels;
assign debugbus[7] = rx_full;
assign debugbus[11:8] = phase;
assign debugbus[12] = ch0_in;
assign debugbus[13] = clear_status_dsp;
assign debugbus[14] = rx_overrun_dsp;
assign debugbus[15] = rxclk;
assign debugbus[16] = bus_reset;
assign debugbus[17] = RD;
assign debugbus[18] = have_pkt_rdy;
assign debugbus[19] = rx_overrun;
assign debugbus[20] = read_count[0];
assign debugbus[21] = read_count[8];
assign debugbus[22] = ch0_out;
assign debugbus[23] = iq_out;
assign debugbus[24] = clear_status;
assign debugbus[30:25] = 0;
assign debugbus[31] = usbclk;
endmodule // rx_buffer
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O211AI_4_V
`define SKY130_FD_SC_LS__O211AI_4_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog wrapper for o211ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o211ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o211ai_4 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o211ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o211ai_4 (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o211ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O211AI_4_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 155; int f[maxn][maxn * maxn], a[maxn]; int n, K, s, ans = 2e9, cur; void solve() { sort(a + 1, a + n + 1); ans = 0; for (int i = 1; i <= K; i++) ans += a[i]; printf( %d n , ans); } int main() { scanf( %d%d%d , &n, &K, &s); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); if (s >= n * (n - 1) / 2) { solve(); return 0; } memset(f, 0x3f, sizeof f); f[0][0] = 0; for (int j = 1; j <= n; j++) for (int i = K - 1; i >= 0; i--) for (int k = 0; k <= min(s, n * i); k++) f[i + 1][k + j - (i + 1)] = min(f[i + 1][k + j - (i + 1)], f[i][k] + a[j]); for (int i = 0; i <= s; i++) ans = min(ans, f[K][i]); printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int gcd(long long a, int b) { if (a < b) { return gcd(b, a); } if (b == 0) { return a; } return gcd(b, a % b); } class Triplet { public: long long gcd; long long x; long long y; }; Triplet gcdExtendedEuclid(int a, int b) { if (b == 0) { Triplet myAns; myAns.gcd = a; myAns.x = 1; myAns.y = 0; return myAns; } Triplet smallAns = gcdExtendedEuclid(b, a % b); Triplet myAns; myAns.gcd = smallAns.gcd; myAns.x = smallAns.y; myAns.y = (smallAns.x - ((a / b) * (smallAns.y))); return myAns; } long long modInverse(int A, int M) { Triplet ans = gcdExtendedEuclid(A, M); return ans.x; } bool check(vector<long long>& v1, long long val, long long h) { long long ans = 0; for (long long i = 0; i < v1.size(); i++) { ans += v1[i] / val; if (v1[i] % val != 0) { ans += 1; } } if (ans > h) { return false; } return true; } void multiply(long long A[2][2], long long M[2][2]) { long long firstValue = (A[0][0] * M[0][0] + A[0][1] * M[1][0]) % 1000000007; long long secondValue = (A[0][0] * M[0][1] + A[0][1] * M[1][1]) % 1000000007; long long thirdValue = (A[1][0] * M[0][0] + A[1][1] * M[1][0]) % 1000000007; long long fourthValue = (A[1][0] * M[0][1] + A[1][1] * M[1][1]) % 1000000007; A[0][0] = firstValue; A[0][1] = secondValue; A[1][0] = thirdValue; A[1][1] = fourthValue; return; } void getpow(long long A[2][2], long long n) { if (n == 0 || n == 1) { return; } getpow(A, n / 2); multiply(A, A); if (n % 2 != 0) { long long first[2][2] = {{1, 1}, {1, 0}}; multiply(A, first); } return; } long long getpow1(long long n, long long m, long long b) { if (m == 0) { return 1; } long long ans = getpow1(n, m / 2, b) % b; ans = (ans * ans) % b; if (m % 2 != 0) { ans = ans * n % b; } return ans % b; } long long getfib(long long n) { if (n == 0) { return 0; } long long A[2][2] = {{1, 1}, {1, 0}}; getpow(A, n); long long first[1][2]; first[0][0] = 0; first[0][1] = 1; long long ans = first[0][0] * A[0][0] + first[0][1] * A[1][0]; return ans % 1000000007; } vector<long long>* sieve() { bool isprime[1000001]; for (long long i = 0; i < 1000001; i++) { isprime[i] = true; } vector<long long>* primes = new vector<long long>(); for (long long i = 2; i < 1000001; i++) { if (isprime[i] == true) { for (long long j = 2 * i; j < 1000001; j += i) { isprime[j] = false; } } } primes->push_back(2); for (long long i = 3; i < 1000001; i++) { if (isprime[i] == true) { primes->push_back(i); } } return primes; } long long getpow2(long long a, string& b, long long m) { long long mod = 1000000007; long long num = 1; for (long long i = b.size() - 1; i >= 0; i--) { if (b[i] == 1) { num = (num * a) % m; } else if (b[i] == 2) { num = ((num * a) % m * a) % m; } a = ((a * a) % m * a) % m; } return num % m; } long long arr[5000001]; long long res[1000001]; long long res1[1000001]; int main() { long long k, n; cin >> k >> n; long long num = 0; long long k1 = k; while (k1 < n) { k1 *= k; num++; } if (k1 == n) { cout << YES << n ; cout << num; return 0; } cout << NO << n ; return 0; } |
// 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9
// 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0
//----------------------------------------------------------------------------------------
//
// The MIT License (MIT)
// Copyright (c) 2016 Enrique Sedano ()
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this
// software and associated documentation files (the "Software"), to deal in the Software
// without restriction, including without limitation the rights to use, copy, modify,
// merge, publish, distribute, sublicense, and/or sell copies of the Software, and to
// permit persons to whom the Software is furnished to do so, subject to the following
// conditions:
//
// The above copyright notice and this permission notice shall be included in all copies
// or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
// PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
// CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
// OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
//
//----------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------
//
// This module is a member of
// ____ __
// _ __/ __ \__ ______/ /_ __
// | | / / /_/ / / / / __ / / / /
// | |/ / _, _/ /_/ / /_/ / /_/ /
// |___/_/ |_|\__,_/\__,_/\__, /
// /____/ v 0.0 - Development
//
// Module: ctrl_top.v
// Version: 1.0
// Description:
// Control unit. Implements the state machine that controls vRudy.
//----------------------------------------------------------------------------------------
module ctrl_top (
//------------------------------
// Top level control signals
//------------------------------
input wire clk,
input wire rst_n,
//------------------------------
// Control inputs
//------------------------------
input wire [1:0] ir,
input wire cond,
//------------------------------
// Control outputs
//------------------------------
output reg ld_ra,
output reg ld_ir,
output reg ld_pc,
output reg ld_rat,
output reg ld_rz,
output reg ld_rn,
output reg pc_at,
output reg [1:0] crf,
output reg erd,
output reg rw,
output reg operate
);
localparam S_FETCH = 3'b000;
localparam S_DECO = 3'b001;
localparam S_LOAD = 3'b010;
localparam S_STORE = 3'b011;
localparam S_ARIT = 3'b100;
localparam S_BRANCH = 3'b101;
// State of the control unit
reg [2:0] state;
reg [2:0] n_state;
//----------------------------------------
// State update
//----------------------------------------
always @(posedge clk, negedge rst_n)
begin
if (rst_n == 1'b0)
state <= S_FETCH;
else
state <= n_state;
end
//----------------------------------------
// Next state and output signals selection
//----------------------------------------
always @(*)
begin
//------------------------------
// Default assignments
//------------------------------
n_state = state;
ld_ra = 1'b0;
ld_ir = 1'b0;
ld_pc = 1'b0;
ld_rat = 1'b0;
ld_rz = 1'b0;
ld_rn = 1'b0;
pc_at = 1'b0;
crf = 2'b00;
erd = 1'b0;
rw = 1'b0;
operate = 1'b0;
//------------------------------
// Values selection
//------------------------------
case (state)
S_FETCH:
begin
n_state = S_DECO;
ld_ir = 1'b1;
ld_pc = 1'b1;
end
S_DECO:
begin
case (ir)
2'b00:
n_state = S_LOAD;
2'b01:
n_state = S_STORE;
2'b10:
if (cond == 1'b0)
n_state = S_FETCH;
else
n_state = S_BRANCH;
2'b11:
n_state = S_ARIT;
endcase
ld_ra = 1'b1;
ld_rat = 1'b1;
crf = 1'b1;
end
S_LOAD:
begin
n_state = S_FETCH;
ld_rz = 1'b1;
ld_rn = 1'b1;
pc_at = 1'b1;
erd = 1'b1;
end
S_STORE:
begin
n_state = S_FETCH;
pc_at = 1'b1;
rw = 1'b1;
end
S_ARIT:
begin
n_state = S_DECO;
ld_ir = 1'b1;
ld_pc = 1'b1;
ld_rz = 1'b1;
ld_rn = 1'b1;
crf = 2'b10;
erd = 1'b1;
operate = 1'b1;
end
S_BRANCH:
begin
n_state = S_DECO;
ld_ir = 1'b1;
ld_pc = 1'b1;
pc_at = 1'b1;
end
endcase
end
endmodule
//----------------------------------------------------------------------------------------
// Trivia: The different versions of the code (except for v 0.0 - Development) will be
// named after notable venues in the Bay Area thrash metal scene. Wikipedia only lists
// seven of those, but I don't really expect to have many more versions than that.
//----------------------------------------------------------------------------------------
// 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9
// 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0
|
#include <bits/stdc++.h> using namespace std; template <class T> string i2s(T x) { ostringstream o; o << x; return o.str(); } template <class T> vector<T> split(const string& s) { vector<T> v; istringstream is(s); T t; while (is >> t) v.push_back(t); return v; } vector<string> splitStr(const string& s, const string& d = , bool keepEmpty = false) { if (d.empty()) return split<string>(s); vector<string> v; string t; for (int _n = ((int((s).size()))), i = 0; i < _n; ++i) if (d.find(s[i]) != string::npos) { if (keepEmpty || !t.empty()) { v.push_back(t); t = ; } } else t += s[i]; if (!t.empty()) v.push_back(t); return v; } int main() { std::ios::sync_with_stdio(false); int N, M; string s; cin >> N >> M; vector<string> v(N); for (int _n = (N), i = 0; i < _n; ++i) { cin >> v[i]; } int mini = 1000, maxi = 0, minj = 1000, maxj = 0; for (int _n = (N), i = 0; i < _n; ++i) for (int _n = (M), j = 0; j < _n; ++j) if (v[i][j] == X ) { mini = min(i, mini); minj = min(j, minj); maxi = max(i, maxi); maxj = max(j, maxj); } bool poss = true; for (int i = (mini); i <= (maxi); ++i) for (int j = (minj); j <= (maxj); ++j) if (v[i][j] != X ) { poss = false; break; } string ans = (poss ? YES : NO ); cout << ans << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int T; cin >> T; while (T--) { long long n, k; cin >> n >> k; if (k % 3) { if (n % 3) cout << Alice n ; else cout << Bob n ; } else { n %= (k + 1); if (n == k || n % 3) cout << Alice n ; else cout << Bob n ; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a, b; int t = n / 2; if (n % 2 == 1) { cout << t << << t + 1; } else if (n % 4 == 2) { cout << t - 2 << << t + 2; } else if (n % 4 == 0) { cout << t - 1 << << t + 1; } } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t;
// verilator lint_off LITENDIAN
reg [5:0] binary_nostart [2:15];
reg [5:0] binary_start [0:15];
reg [175:0] hex [0:15];
// verilator lint_on LITENDIAN
integer i;
initial begin
begin
$readmemb("t/t_sys_readmem_b.mem", binary_nostart);
`ifdef TEST_VERBOSE
for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, binary_nostart[i]);
`endif
if (binary_nostart['h2] != 6'h02) $stop;
if (binary_nostart['h3] != 6'h03) $stop;
if (binary_nostart['h4] != 6'h04) $stop;
if (binary_nostart['h5] != 6'h05) $stop;
if (binary_nostart['h6] != 6'h06) $stop;
if (binary_nostart['h7] != 6'h07) $stop;
if (binary_nostart['h8] != 6'h10) $stop;
if (binary_nostart['hc] != 6'h14) $stop;
if (binary_nostart['hd] != 6'h15) $stop;
end
begin
$readmemb("t/t_sys_readmem_b_8.mem", binary_start, 4, 4+7);
`ifdef TEST_VERBOSE
for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, binary_start[i]);
`endif
if (binary_start['h04] != 6'h10) $stop;
if (binary_start['h05] != 6'h11) $stop;
if (binary_start['h06] != 6'h12) $stop;
if (binary_start['h07] != 6'h13) $stop;
if (binary_start['h08] != 6'h14) $stop;
if (binary_start['h09] != 6'h15) $stop;
if (binary_start['h0a] != 6'h16) $stop;
if (binary_start['h0b] != 6'h17) $stop;
end
begin
$readmemh("t/t_sys_readmem_h.mem", hex, 0);
`ifdef TEST_VERBOSE
for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, hex[i]);
`endif
if (hex['h04] != 176'h400437654321276543211765432107654321abcdef10) $stop;
if (hex['h0a] != 176'h400a37654321276543211765432107654321abcdef11) $stop;
if (hex['h0b] != 176'h400b37654321276543211765432107654321abcdef12) $stop;
if (hex['h0c] != 176'h400c37654321276543211765432107654321abcdef13) $stop;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1000003ll; long long npow[64]; long long fast_pow(long long n, long long e) { if (e == 0) return 1ll; long long tmp = fast_pow(n, e / 2ll); tmp = (tmp * tmp) % MOD; if (e & 1ll) return (tmp * n) % MOD; return tmp; } int main() { ios::sync_with_stdio(0); npow[0] = 1ll; for (int i = 1; i < 63; i++) npow[i] = (npow[i - 1] * 2ll); long long n, k; cin >> n >> k; if (n < 63 && k > npow[n]) { cout << 1 1 n ; return 0; } long long tgt = k - 1ll; long long pcount = 0; long long val = 2ll; while (true) { long long adder = tgt / val; if (!adder) break; val *= 2ll; pcount += adder; } long long kmult = n - (pcount / (k - 1)); long long den = fast_pow(2, k - 1ll); den = fast_pow(den, kmult - 1ll); den = den * fast_pow(2ll, k - 1 - (pcount % (k - 1))); den %= MOD; long long num = 0; if (k - 1ll < MOD) { long long prod = fast_pow(2ll, pcount); long long rem = fast_pow(2ll, n); num = fast_pow(prod, MOD - 2ll); for (int i = 1; i <= k - 1ll; i++) { long long mult = rem - i; while (mult < 0) mult += MOD; num = (num * mult) % MOD; } } num = (den - num); while (num < 0) num += MOD; cout << num << << den << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int f(char c1, char c2) { if (c1 == R && c2 == S ) return 1; if (c1 == S && c2 == P ) return 1; if (c1 == P && c2 == R ) return 1; if (c2 == R && c1 == S ) return -1; if (c2 == S && c1 == P ) return -1; if (c2 == P && c1 == R ) return -1; return 0; } int main() { int n, j1 = 0, j2 = 0, i, r1 = 0, r2 = 0, t; char s1[1500], s2[1500]; cin >> n >> s1 >> s2; for (i = 0; i < n; ++i) { t = f(s1[j1], s2[j2]); if (t == 1) ++r2; if (t == -1) ++r1; ++j1; if (!s1[j1]) j1 = 0; ++j2; if (!s2[j2]) j2 = 0; if (j1 == 0 && j2 == 0) { r1 *= n / (i + 1); r2 *= n / (i + 1); n %= (i + 1); i = -1; } } cout << r1 << << r2; return 0; } |
#include <bits/stdc++.h> using namespace std; int number[120], prime[120], primecounter = 0; void sieve() { for (int i = 0; i <= 100; i++) number[i] = 1; number[0] = 0; number[1] = 0; for (int i = 4; i <= 100; i = i + 2) number[i] = 0; for (int i = 3; i * i <= 100; i = i + 2) { for (int j = 2 * i; j <= 100; j = j + i) { if (number[j] == 1) number[j] = 0; } } for (int i = 2; i <= 100; i = i + 1) { if (number[i] == 1) { primecounter++; prime[primecounter] = i; } } } int main(void) { sieve(); char line[50]; int save[100 + 20]; int yes = 0, no = 0, s; for (int i = 1; prime[i] <= 53; i++) { printf( %d n , prime[i]); fflush(stdout); scanf( %s , line); if (strcmp( yes , line) == 0) { yes++; s = prime[i]; } else no++; } if (yes == 0) { printf( prime n ); fflush(stdout); return 0; } else if (yes > 1) { printf( composite n ); fflush(stdout); return 0; } else if (yes == 1) { int v = s * s; if (v <= 100) { printf( %d n , v); fflush(stdout); scanf( %s , line); if (strcmp( yes , line) == 0) { printf( composite n ); fflush(stdout); return 0; } else { printf( prime n ); fflush(stdout); return 0; } } else { printf( prime n ); fflush(stdout); return 0; } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O22AI_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__O22AI_PP_BLACKBOX_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o22ai (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O22AI_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const long long inf = (long long)1e18; const long long mod = (long long)1e9 + 7; const double eps = (double)1e-9; const double pi = acos(-1.0); const int dx[] = {0, 0, 1, 0, -1}; const int dy[] = {0, 1, 0, -1, 0}; const int N = 300500; int main() { cin.tie(NULL); cout.tie(NULL); ios_base::sync_with_stdio(false); vector<int> v; v.push_back(1); v.push_back(2); while (v.size() < (int)1e6) { int x = v.back(); if (x % 2 == 0) { v.push_back(x + x); v.push_back(x + x + 1); } else { v.push_back(x + x - 1); v.push_back(x + x); } } int n; cin >> n; for (int i : v) if (i == n) { cout << 1; return 0; } cout << 0; return 0; } |
#include <bits/stdc++.h> using namespace std; vector<pair<pair<int, int>, int>> ordered; deque<pair<int, int>> solutions; vector<bool> stay, check; bool cmp(pair<pair<int, int>, int> &a, pair<pair<int, int>, int> &b) { int A = a.first.second - a.first.first; int B = b.first.second - b.first.first; return A < B; } vector<pair<pair<int, int>, int>> new_array( vector<pair<pair<int, int>, int>> &v, int value) { vector<pair<pair<int, int>, int>> temp; for (int i = 0; i < v.size(); i++) { if (stay[i]) temp.push_back(make_pair( make_pair(v[i].first.first + value, v[i].first.second), v[i].second)); } return temp; } int main() { cin.sync_with_stdio(0); cin.tie(0); int n, k; cin >> n >> k; for (int i = 0; i < n; i++) { int aux; cin >> aux; stay.push_back(false); check.push_back(false); if (i < k) ordered.push_back(make_pair(make_pair(1, aux), i)); else solutions.push_back(make_pair(aux, i)); } sort(ordered.begin(), ordered.end(), cmp); int d = 0, ans = 0, m = 0; while (ordered.size() != 0) { int mini = ordered[0].first.second - ordered[0].first.first + 1; int index = 0, out = 0, change = 0, intern_ans = 0; for (auto &x : ordered) { int L = x.first.first; int R = L + mini - 1; int id = x.second; if (L <= d && d <= R && check[id] == false) { ans++; intern_ans++; check[id] = true; } int range = x.first.second - x.first.first + 1; if (range == mini) { stay[index++] = false; m++; out++; change = true; } else stay[index++] = true; } ordered = new_array(ordered, mini); double temp = 100.00 * ((double)m / n) + 0.5; d = (int)temp; while (solutions.size() != 0 && out > 0) { ordered.push_back( make_pair(make_pair(1, solutions[0].first), solutions[0].second)); solutions.pop_front(); out--; } if (change) sort(ordered.begin(), ordered.end(), cmp); } cout << ans << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main(void) { int n; cin >> n; cout << (n - 1) / 2 << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MOD = (int)1e9 + 7; const int MAXN = (int)1003; const int LOG = (int)11; const int infint = (int)1e9 + 3; const long long inf = (long long)1e12; string A, B[MAXN]; int cost[MAXN], dp[MAXN][MAXN], last[MAXN], n, mx, sza; pair<int, int> radix[MAXN]; void build() { memset(dp, -63, sizeof dp); for (auto &ch : A) ch -= 0 ; mx++; reverse(A.begin(), A.end()); sza = A.size(); while ((int)A.size() < mx) A += (char)(0); for (int i = 0; i < n; i++) { last[i] = B[i].size(); reverse(B[i].begin(), B[i].end()); while ((int)B[i].size() < mx) B[i] += 0 ; radix[i] = {B[i][0], i}; } sort(radix, radix + n); reverse(radix, radix + n); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> A >> n; mx = A.size(); for (int i = 0; i < n; i++) { cin >> B[i]; mx = max(mx, (int)B[i].size()); } for (int i = 0; i < 10; i++) cin >> cost[i]; build(); dp[0][0] = 0; for (int i = 0; i < mx; i++) { int l, r; if (A[i] == ? - 0 ) l = 0, r = 9; else l = r = A[i]; if (i == sza - 1 && A[i] == ? - 0 ) l = 1; for (int k = l; k <= r; k++) { int pt = 0, add = 0; for (int j = 0; j < n; j++) { int ind = radix[j].second; int nxt = B[ind][i] - 0 + k; if (nxt >= 10) pt++; if (max(last[ind], sza) > i || nxt > 0) add += cost[nxt % 10]; } for (int j = 0; j <= n; j++) { dp[i + 1][pt] = max(dp[i + 1][pt], dp[i][j] + add); if (j == n) continue; int ind = radix[j].second; int nxt = B[ind][i] - 0 + k; if (nxt == 9) pt++; if (max(last[ind], sza) > i || nxt > 0) add -= cost[nxt % 10]; add += cost[(nxt + 1) % 10]; } } reverse(radix, radix + n); for (int j = 0; j < n; j++) { int ind = radix[j].second; radix[j].first = n * B[ind][i] + j; } sort(radix, radix + n); reverse(radix, radix + n); } cout << dp[mx][0]; } |
//Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
module debounce (
clk,
reset_n,
data_in,
data_out
);
parameter WIDTH = 32; // set to be the width of the bus being debounced
parameter POLARITY = "HIGH"; // set to be "HIGH" for active high debounce or "LOW" for active low debounce
parameter TIMEOUT = 50000; // number of input clock cycles the input signal needs to be in the active state
parameter TIMEOUT_WIDTH = 16; // set to be ceil(log2(TIMEOUT))
input wire clk;
input wire reset_n;
input wire [WIDTH-1:0] data_in;
output wire [WIDTH-1:0] data_out;
reg [TIMEOUT_WIDTH-1:0] counter [0:WIDTH-1];
wire counter_reset [0:WIDTH-1];
wire counter_enable [0:WIDTH-1];
// need one counter per input to debounce
genvar i;
generate for (i = 0; i < WIDTH; i = i+1)
begin: debounce_counter_loop
always @ (posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
counter[i] <= 0;
end
else
begin
if (counter_reset[i] == 1) // resetting the counter needs to win
begin
counter[i] <= 0;
end
else if (counter_enable[i] == 1)
begin
counter[i] <= counter[i] + 1'b1;
end
end
end
if (POLARITY == "HIGH")
begin
assign counter_reset[i] = (data_in[i] == 0);
assign counter_enable[i] = (data_in[i] == 1) & (counter[i] < TIMEOUT);
assign data_out[i] = (counter[i] == TIMEOUT) ? 1'b1 : 1'b0;
end
else
begin
assign counter_reset[i] = (data_in[i] == 1);
assign counter_enable[i] = (data_in[i] == 0) & (counter[i] < TIMEOUT);
assign data_out[i] = (counter[i] == TIMEOUT) ? 1'b0 : 1'b1;
end
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND4_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__NAND4_FUNCTIONAL_PP_V
/**
* nand4: 4-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__nand4 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , D, C, B, A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND4_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; int main() { int n, x, y; int p = 1; cin >> n; cin >> x; cin >> y; p = n * y; if (p % 100 != 0) p = p / 100 + 1; else p = p / 100; if (p <= x) cout << 0 << endl; else cout << p - x << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { static int f[10000]; int n, ok = false; scanf( %d , &n); for (register int i = 1; i <= n; ++i) scanf( %d , f + i); for (int i = 1; i <= n; ++i) if (f[f[f[i]]] == i) ok = true; puts(ok ? YES : NO ); } |
#include <bits/stdc++.h> using namespace std; const int mod = 998244353; char s[1010]; int n, fa[2010], val[2010], pw2[2010], ans = 0; inline int getf(int x) { if (x == fa[x]) return x; int f = getf(fa[x]); val[x] ^= val[fa[x]]; fa[x] = f; return f; } inline int merge(int x, int y, int w) { int ti = getf(x), tj = getf(y); if (ti == tj) return w == (val[x] ^ val[y]); w ^= val[x] ^ val[y]; fa[ti] = tj; val[ti] = w; return 1; } int main() { scanf( %s , s + 1); n = strlen(s + 1); reverse(s + 1, s + n + 1); pw2[0] = 1; for (int i = 1; i <= n; i++) pw2[i] = (pw2[i - 1] + pw2[i - 1]) % mod; int ans = 0; for (int lena = n - 1; lena >= 1; lena--) { for (int j = 1; j <= ((n << 1) + 1); j++) fa[j] = j, val[j] = 0; if (!merge((n), ((n << 1) + 1), 0)) continue; if (!merge((n + n), ((n << 1) + 1), 1)) continue; bool fail = 0; for (int j = 1; j <= n / 2; j++) { if (!merge((j + n), (n + 1 - j + n), 0)) { fail = 1; break; } } if (fail) continue; for (int j = 1; j <= lena / 2; j++) { if (!merge((j), (lena + 1 - j), 0)) { fail = 1; break; } } if (fail) continue; for (int j = lena + 1; j < n; j++) { if (!merge((j), ((n << 1) + 1), 0)) { fail = 1; break; } } if (!merge((lena), ((n << 1) + 1), 1)) fail = 1; if (fail) continue; for (int j = 1; j <= n; j++) { if (s[j] == 0 ) { if (!merge((j), (j + n), 0)) { fail = 1; break; } } else if (s[j] == 1 ) { if (!merge((j), (j + n), 1)) { fail = 1; break; } } } if (fail) continue; int cnt = 0; for (int j = 1; j <= ((n << 1) + 1); j++) if (getf(j) == j && getf(j) != getf(((n << 1) + 1))) cnt++; ans = (ans + pw2[cnt]) % mod; } printf( %d n , ans); return 0; } |
// VGA_0.v
// This file was auto-generated as part of a SOPC Builder generate operation.
// If you edit it your changes will probably be lost.
`timescale 1 ps / 1 ps
module VGA_0 (
input wire iCLK, // clk.clk
output wire [9:0] VGA_R, // avalon_slave_0_export.export
output wire [9:0] VGA_G, // .export
output wire [9:0] VGA_B, // .export
output wire VGA_HS, // .export
output wire VGA_VS, // .export
output wire VGA_SYNC, // .export
output wire VGA_BLANK, // .export
output wire VGA_CLK, // .export
input wire iCLK_25, // .export
output wire [15:0] oDATA, // avalon_slave_0.readdata
input wire [15:0] iDATA, // .writedata
input wire [18:0] iADDR, // .address
input wire iWR, // .write
input wire iRD, // .read
input wire iCS, // .chipselect
input wire iRST_N // reset_n.reset_n
);
VGA_NIOS_CTRL #(
.RAM_SIZE (307200)
) vga_0 (
.iCLK (iCLK), // clk.clk
.VGA_R (VGA_R), // avalon_slave_0_export.export
.VGA_G (VGA_G), // .export
.VGA_B (VGA_B), // .export
.VGA_HS (VGA_HS), // .export
.VGA_VS (VGA_VS), // .export
.VGA_SYNC (VGA_SYNC), // .export
.VGA_BLANK (VGA_BLANK), // .export
.VGA_CLK (VGA_CLK), // .export
.iCLK_25 (iCLK_25), // .export
.oDATA (oDATA), // avalon_slave_0.readdata
.iDATA (iDATA), // .writedata
.iADDR (iADDR), // .address
.iWR (iWR), // .write
.iRD (iRD), // .read
.iCS (iCS), // .chipselect
.iRST_N (iRST_N) // reset_n.reset_n
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND3B_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__NAND3B_PP_BLACKBOX_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nand3b (
Y ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND3B_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const long long N = 2e5 + 1; const long long nol = 0; long long n, k, a, cnt, ans, j, mx; deque<long long> v, vc; void vkoshp() { cin >> n >> k; for (long long i = 0; i < n; i++) { cin >> a; v.push_back(a); } for (long long i = 0; i < n; i++) { cin >> a; if (a == 1) cnt += v[i], vc.push_back(0); else ans += v[i], vc.push_back(v[i]); mx = max(mx, ans); if (vc.size() == k) { ans -= vc[0]; vc.pop_front(); } } cout << cnt + mx << endl; } int main() { cout.tie(NULL); cin.tie(NULL); ios_base::sync_with_stdio(0); long long t = 1; while (t--) vkoshp(); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DIODE_SYMBOL_V
`define SKY130_FD_SC_HDLL__DIODE_SYMBOL_V
/**
* diode: Antenna tie-down diode.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__diode (
//# {{power|Power}}
input DIODE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DIODE_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FAH_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__FAH_FUNCTIONAL_PP_V
/**
* fah: Full adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__fah (
COUT,
SUM ,
A ,
B ,
CI ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xor0_out_SUM ;
wire pwrgood_pp0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT ;
wire pwrgood_pp1_out_COUT;
// Name Output Other arguments
xor xor0 (xor0_out_SUM , A, B, CI );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND);
buf buf0 (SUM , pwrgood_pp0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, CI );
and and2 (b_ci , B, CI );
or or0 (or0_out_COUT , a_b, a_ci, b_ci );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_COUT, or0_out_COUT, VPWR, VGND);
buf buf1 (COUT , pwrgood_pp1_out_COUT );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__FAH_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLRBP_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__DLRBP_PP_BLACKBOX_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlrbp (
Q ,
Q_N ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLRBP_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; long long MOD = 1000000007; long long dp[2001][2001]; long long dp1[2001][2001]; int main() { int N, K; string S; cin >> N >> K >> S; memset(dp, 0, sizeof(dp)); memset(dp1, 0, sizeof(dp1)); dp[0][0] = dp1[0][0] = 1; for (int n = 1; n <= N; ++n) { for (int k = 0; k <= K; ++k) { dp[n][k] = dp1[n - 1][k] * (long long)(S[n - 1] - a ) % MOD; } for (int i = 0; i < n; ++i) { int delta = (n - i) * (N - n + 1); for (int k = 0; k + delta <= K; ++k) { dp[n][k + delta] += dp[i][k] * (long long)( z - S[n - 1]) % MOD; dp[n][k + delta] %= MOD; } } for (int k = 0; k <= K; ++k) { dp1[n][k] = (dp1[n - 1][k] + dp[n][k]) % MOD; } } cout << dp1[N][K] << endl; return 0; } |
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// NOTE: This is still WIP.
(* techmap_celltype = "$alu" *)
module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
//output [Y_WIDTH-1:0] CO;
output CO;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 4;
(* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
(* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
//wire [Y_WIDTH:0] C = {CO, CI};
wire [Y_WIDTH+1:0] COx;
wire [Y_WIDTH+1:0] C = {COx, CI};
/* Start implementation */
(* keep *) cyclone10lp_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1));
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
if(i==Y_WIDTH-1) begin
(* keep *) cyclone10lp_lcell_comb #(.lut_mask(16'b1111_0000_1110_0000), .sum_lutc_input("cin")) carry_end (.combout(COx[Y_WIDTH]), .dataa(1'b1), .datab(1'b1), .datac(1'b1), .datad(1'b1), .cin(C[Y_WIDTH]));
assign CO = COx[Y_WIDTH];
end
else
cyclone10lp_lcell_comb #(.lut_mask(16'b1001_0110_1110_1000), .sum_lutc_input("cin")) arith_cell (.combout(Y[i]), .cout(COx[i+1]), .dataa(AA[i]), .datab(BB[i]), .datac(1'b1), .datad(1'b1), .cin(C[i+1]));
end: slice
endgenerate
/* End implementation */
assign X = AA ^ BB;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long double PI = 3.14159265358979323846; const int MAXN = 1e5 + 3; long long n, a, b, p, q; bool isLeap(int a) { if (a % 400 == 0) return true; if (a % 4 == 0 && a % 100) return true; return false; } void solve() { int y; cin >> y; int cnt = 0; bool f = 0; if (isLeap(y)) f = 1; y++; bool isl = 0; while (1) { cnt += 365; isl = isLeap(y); if (isl) cnt++; if (cnt % 7 == 0 && isl == f) break; y++; } cout << y; } int main() { solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; for (int ti = 0; ti < t; ti++) { int n, k; cin >> n >> k; vector<int> arr(n); for (int i = 0; i < n; i++) cin >> arr[i]; sort(arr.begin(), arr.end()); vector<int> weights(k); for (int i = 0; i < k; i++) cin >> weights[i]; sort(weights.begin(), weights.end()); long long total = 0; for (int i = n - 1; i >= n - k; i--) { total += arr[i]; } int w = 0; for (int i = k - 1; i >= 0; i--) { if (weights[i] <= 1) break; total += arr[w]; w += weights[i] - 1; } for (int i = 0; i < k; i++) { if (weights[i] > 1) break; total += arr[n - 1 - i]; } cout << total << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 2 * 1e9; const double EPS = 1e-9; const int MaxN = 100000 + 5; const int MaxM = 2 * 100000 + 5; int N, M, S, L, Dist[MaxN]; typedef struct Node { int idx; Node(void) {} Node(int _idx) { idx = _idx; } inline bool operator<(const Node &NewNode) const { return Dist[idx] > Dist[NewNode.idx]; } }; typedef struct Edge { int idx, Weight; Edge(void) {} Edge(int _idx, int _Weight) { idx = _idx; Weight = _Weight; } }; vector<Edge> E[MaxM]; inline void Dijkstra(int Start) { for (int i = 0; i < N; i++) Dist[i] = INF; priority_queue<Node> PQ; PQ.push(Node(Start)); Dist[Start] = 0; while (!PQ.empty()) { Node CurrNode = PQ.top(); PQ.pop(); for (vector<Edge>::iterator it = E[CurrNode.idx].begin(); it != E[CurrNode.idx].end(); it++) { Node NextNode = Node((*it).idx); int Weight = (*it).Weight; if (Dist[CurrNode.idx] + Weight < Dist[NextNode.idx]) { Dist[NextNode.idx] = Dist[CurrNode.idx] + Weight; PQ.push(NextNode); } } } } vector<pair<pair<int, int>, int> > Edges; int main(void) { scanf( %d %d %d , &N, &M, &S); S--; for (int i = 0; i < M; i++) { int idx, idy, Weight; scanf( %d %d %d , &idx, &idy, &Weight); idx--; idy--; E[idx].push_back(Edge(idy, Weight)); E[idy].push_back(Edge(idx, Weight)); Edges.push_back(make_pair(make_pair(idx, idy), Weight)); } scanf( %d , &L); Dijkstra(S); int Sol = 0; for (int i = 0; i < N; i++) if (Dist[i] == L) Sol++; for (int i = 0; i < M; i++) { int idx = Edges[i].first.first, idy = Edges[i].first.second, Weight = Edges[i].second; int Pos1 = -1, Pos2 = -1; if ((Dist[idx] < L) && (L < Dist[idx] + Weight) && (L <= Dist[idy] + Dist[idx] + Weight - L)) Pos1 = L - Dist[idx]; if ((Dist[idy] < L) && (L < Dist[idy] + Weight) && (L <= Dist[idx] + Dist[idy] + Weight - L)) Pos2 = Dist[idy] + Weight - L; if (Pos1 >= 0) Sol++; if ((Pos2 >= 0) && (Pos2 != Pos1)) Sol++; } printf( %d n , Sol); return 0; } |
#include <bits/stdc++.h> using namespace std; void fff() { freopen( dravde.in , r , stdin); freopen( dravde.out , w , stdout); } const int MAXN = 100001; int n; map<int, int> m[MAXN]; int f[MAXN], s[MAXN], p[MAXN], cnt = 0, z; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { int v, c, l, r; scanf( %d%d%d%d , &v, &c, &l, &r); if (r + c < MAXN && (!l || m[l].find(r + c) != m[l].end())) { int u = m[l][r + c]; f[i] = f[u] + v, p[i] = u; if (!r && f[i] > f[z]) { z = i; } if (f[i] > f[m[l + c][r]]) { m[l + c][r] = i; } } } while (z) { s[cnt++] = z; z = p[z]; } printf( %d n , cnt); while (cnt--) { printf( %d , s[cnt]); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long n, m; cin >> n >> m; tuple<long long, long long, long long> arr[n - 1]; long long s1, e1; cin >> s1 >> e1; for (long long i = 0; i < n - 1; ++i) { long long s2, e2; cin >> s2 >> e2; arr[i] = make_tuple(e2 - s1 + 1, s2 - e1 - 1, i); s1 = s2, e1 = e2; } pair<long long, long long> blen1[m]; long long blen2[m]; for (long long i = 0; i < m; ++i) { long long b; cin >> b; blen1[i] = make_pair(b, i); blen2[i] = b; } sort(arr, arr + n - 1); sort(blen1, blen1 + m); sort(blen2, blen2 + m); pair<long long, long long> num_b[n - 1]; for (long long i = 0; i < n - 1; ++i) { long long end, start, idx, u = 0, l = 0; tie(end, start, idx) = arr[i]; l = upper_bound(blen2, blen2 + m, start) - blen2; u = lower_bound(blen2, blen2 + m, end) - blen2; if (u - l == 0) { cout << No << endl; return 0; } else { num_b[i] = make_pair(l, u); } } set<pair<long long, long long> > bg; for (long long i = 0; i < m; ++i) { bg.insert(blen1[i]); } long long ans[n - 1]; for (long long i = 0; i < n - 1; ++i) { long long u = num_b[i].second, l = num_b[i].first; set<pair<long long, long long> >::iterator itr = bg.upper_bound({blen2[l], -1}); if (itr == bg.end() || (u != m && (*itr).first >= blen2[u])) { cout << No << endl; return 0; } ans[get<2>(arr[i])] = (*itr).second + 1; bg.erase(itr); } cout << Yes << endl; for (long long i = 0; i < n - 1; ++i) { cout << ans[i] << ; } cout << endl; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_DLATCH_PR_PP_PG_N_TB_V
`define SKY130_FD_SC_HDLL__UDP_DLATCH_PR_PP_PG_N_TB_V
/**
* udp_dlatch$PR_pp$PG$N: D-latch, gated clear direct / gate active
* high (Q output UDP)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__udp_dlatch_pr_pp_pg_n.v"
module top();
// Inputs are registered
reg D;
reg RESET;
reg NOTIFIER;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
NOTIFIER = 1'bX;
RESET = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 NOTIFIER = 1'b0;
#60 RESET = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 NOTIFIER = 1'b1;
#160 RESET = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 NOTIFIER = 1'b0;
#260 RESET = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 RESET = 1'b1;
#380 NOTIFIER = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 RESET = 1'bx;
#480 NOTIFIER = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_hdll__udp_dlatch$PR_pp$PG$N dut (.D(D), .RESET(RESET), .NOTIFIER(NOTIFIER), .VPWR(VPWR), .VGND(VGND), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_DLATCH_PR_PP_PG_N_TB_V
|
#include <bits/stdc++.h> using namespace std; int in(char &c) { return scanf( %c , &c); } int in(char s[]) { return scanf( %s , s); } int in(int &x) { return scanf( %d , &x); } int in(long long &x) { return scanf( %lld , &x); } int in(double &x) { return scanf( %lf , &x); } int in(pair<int, int> &p) { return scanf( %d%d , &p.first, &p.second); } int in(pair<long long, long long> &p) { return scanf( %lld%lld , &p.first, &p.second); } int in(pair<double, double> &p) { return scanf( %lf%lf , &p.first, &p.second); } int in(long double &a) { return scanf( %Lf , &a); } int in(int &x, long long &y) { return scanf( %d%lld , &x, &y); } int in(long long &x, int &y) { return scanf( %lld%d , &x, &y); } int in(int &x, int &y) { return scanf( %d%d , &x, &y); } int in(long long &x, long long &y) { return scanf( %lld%lld , &x, &y); } int in(char s[], int &n) { return scanf( %s%d , s, &n); } int in(int &n, char s[]) { return scanf( %d%s , &n, s); } int in(char a[], char b[]) { return scanf( %s%s , a, b); } int in(double &x, double &y) { return scanf( %lf%lf , &x, &y); } int in(int &n, char s[], char t[]) { return scanf( %d%s%s , &n, s, t); } int in(int &x, int &y, int &z) { return scanf( %d%d%d , &x, &y, &z); } int in(long long &x, long long &y, long long &z) { return scanf( %lld%lld%lld , &x, &y, &z); } int in(double &x, double &y, double &z) { return scanf( %lf%lf%lf , &x, &y, &z); } int in(int &x, int &y, int &z, int &k) { return scanf( %d%d%d%d , &x, &y, &z, &k); } int in(long long &x, long long &y, long long &z, long long &k) { return scanf( %lld%lld%lld%lld , &x, &y, &z, &k); } int in(double &x, double &y, double &z, double &k) { return scanf( %lf%lf%lf%lf , &x, &y, &z, &k); } const int N = 3e5 + 10, M = 1e3 + 10, mod = 1e9 + 7; const double eps = 1e-6, Pi = acos(-1.0); vector<int> g[N]; int dep[N], vis[N], op[N], u[N], v[N], In[N], col[N], use[N], Out[N]; queue<int> que; int topsort(int n) { for (int i = 1; i <= n; i++) { if (In[i] == 0) { que.push(i); } } int cnt = 0; while (!que.empty()) { int u = que.front(); que.pop(); dep[u] = ++cnt; for (auto e : g[u]) { In[e]--; if (In[e] == 0) { que.push(e); } } } return (n != cnt); } int main() { int T, c = 0, t; in(T); t = T; while (T--) { c++; int n, m; in(n, m); for (int i = 1; i <= n; i++) In[i] = dep[i] = vis[i] = 0, g[i].clear(); for (int i = 1; i <= m; i++) { in(op[i], u[i], v[i]); if (op[i] == 1) { In[v[i]]++; g[u[i]].push_back(v[i]); } } if (topsort(n)) { printf( NO n ); continue; } printf( YES n ); for (int i = 1; i <= m; i++) { if (op[i] == 0) { if (dep[u[i]] > dep[v[i]]) swap(u[i], v[i]); } printf( %d %d n , u[i], v[i]); } } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long mod = 998244353; const int nax = 1e6 + 10; long long fac[nax], ifac[nax], inv[nax]; long long ncr(int n, int k) { if (n < 0 || k < 0 || k > n) return 0; return fac[n] * ifac[k] % mod * ifac[n - k] % mod; } int main() { fac[0] = ifac[0] = 1; for (int i = 1; i < nax; i++) { inv[i] = i == 1 ? 1 : mod - mod / i * inv[mod % i] % mod; fac[i] = fac[i - 1] * i % mod; ifac[i] = ifac[i - 1] * inv[i] % mod; assert(fac[i] * ifac[i] % mod == 1); } ios::sync_with_stdio(0); cin.tie(0); string s; cin >> s; int n = s.size(); int lp = 0, rp = count(s.begin(), s.end(), ) ); int lq = 0, rq = count(s.begin(), s.end(), ? ); long long ans = 0; for (int i = 0; i < n; i++) { (ans += ncr(lq + rq, rq - lp + rp) * lp + ncr(lq + rq - 1, rq - 1 - lp + rp) * lq) %= mod; if (s[i] == ( ) lp++; else if (s[i] == ) ) rp--; else if (s[i] == ? ) lq++, rq--; else assert(0); } cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; map<int64_t, int> mp1, mp2; int fnc(int n) { int ans = n + 1; for (auto i = mp1.begin(); i != mp1.end(); i++) { if (i->second >= (n + 1) / 2) return 0; if (i->second + mp2[i->first] >= ((n + 1) / 2)) ans = min(ans, (n + 1) / 2 - i->second); } if (ans < n) return ans; for (auto i = mp2.begin(); i != mp2.end(); i++) { if (i->second >= (n + 1) / 2) return (n + 1) / 2; } if (ans > n) return -1; return ans; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int m; cin >> m; int64_t a, b; for (int i = 0; i < m; i++) { cin >> a >> b; mp1[a]++; if (a != b) mp2[b]++; } cout << fnc(m) << endl; return 0; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////////////////
// Company: Digilent Inc.
// Engineer: Josh Sackos
//
// Create Date: 07/11/2012
// Module Name: PmodJSTK
// Project Name: PmodJSTK_Demo
// Target Devices: ICEStick
// Tool versions: iCEcube2
// Description: This component consists of three subcomponents a 66.67kHz serial clock,
// an SPI controller and a SPI interface. The SPI interface component is
// responsible for sending and receiving a byte of data to and from the
// PmodJSTK when a request is made. The SPI controller component manages all
// data transfer requests, and manages the data bytes being sent to the PmodJSTK.
//
// Revision History:
// Revision 0.01 - File Created (Josh Sackos)
// Revision 1.0 - Updated to send 5 bytes of data instead of just 1
////////////////////////////////////////////////////////////////////////////////////////////
// ==============================================================================
// Define Module
// ==============================================================================
module PmodJSTK(
CLK,
RST,
sndRec,
DIN,
MISO,
SS,
SCLK,
MOSI,
DOUT
);
// ===========================================================================
// Port Declarations
// ===========================================================================
input CLK; // 100MHz onboard clock
input RST; // Reset
input sndRec; // Send receive, initializes data read/write
input [39:0] DIN; // Data that is to be sent to the slave
input MISO; // Master in slave out
output SS; // Slave select, active low
output SCLK; // Serial clock
output MOSI; // Master out slave in
output [39:0] DOUT; // All data read from the slave
// ===========================================================================
// Parameters, Regsiters, and Wires
// ===========================================================================
// Output wires and registers
wire SS;
wire SCLK;
wire MOSI;
wire [39:0] DOUT;
wire getByte; // Initiates a data byte transfer in SPI_Int
wire [7:0] sndDataByte; // Data to be sent to Slave
wire [7:0] RxData; // Output data from SPI_Int
wire BUSY; // Handshake from SPI_Int to SPI_Ctrl
// 66.67kHz Clock Divider, period 15us
wire iSCLK; // Internal serial clock,
// not directly output to slave,
// controls state machine, etc.
// ===========================================================================
// Implementation
// ===========================================================================
//-----------------------------------------------
// SPI Controller
//-----------------------------------------------
spiCtrl SPI_Ctrl(
.CLK(iSCLK),
.RST(RST),
.sndRec(sndRec),
.BUSY(BUSY),
.DIN(DIN),
.RxData(RxData),
.SS(SS),
.getByte(getByte),
.sndData(sndDataByte),
.DOUT(DOUT)
);
//-----------------------------------------------
// SPI Mode 0
//-----------------------------------------------
spiMode0 SPI_Int(
.CLK(iSCLK),
.RST(RST),
.sndRec(getByte),
.DIN(sndDataByte),
.MISO(MISO),
.MOSI(MOSI),
.SCLK(SCLK),
.BUSY(BUSY),
.DOUT(RxData)
);
//-----------------------------------------------
// SPI Controller
//-----------------------------------------------
ClkDiv_66_67kHz SerialClock(
.CLK(CLK),
.RST(RST),
.CLKOUT(iSCLK)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DIODE_BEHAVIORAL_V
`define SKY130_FD_SC_HS__DIODE_BEHAVIORAL_V
/**
* diode: Antenna tie-down diode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hs__diode (
DIODE
);
// Module ports
input DIODE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DIODE_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; const int mx = 1e9; struct Data { int p1, p2, p3, p4; Data(int a = mx, int b = mx, int c = mx, int d = mx) { p1 = a, p2 = b, p3 = c, p4 = d; } }; inline Data UN(Data a, Data b) { Data c; c.p1 = min(a.p1 + b.p1, a.p2 + b.p3), c.p2 = min(a.p1 + b.p2, a.p2 + b.p4); c.p3 = min(a.p3 + b.p1, a.p4 + b.p3), c.p4 = min(a.p3 + b.p2, a.p4 + b.p4); c.p1 = min(c.p1, mx), c.p2 = min(c.p2, mx), c.p3 = min(c.p3, mx), c.p4 = min(c.p4, mx); return c; } struct node { int l, r; Data s; } T[200010 << 2]; char G[3][200010]; void build(int rt, int l, int r) { T[rt].l = l, T[rt].r = r; int mid = (l + r) >> 1; if (l == r) { if (G[1][l] == . ) T[rt].s.p1 = 1; if (G[2][l] == . ) T[rt].s.p4 = 1; if (G[1][l] == . && G[2][l] == . ) T[rt].s.p2 = T[rt].s.p3 = 2; return; } build(rt << 1, l, mid), build(rt << 1 | 1, mid + 1, r); T[rt].s = UN(T[rt << 1].s, T[rt << 1 | 1].s); } Data query(int rt, int start, int end) { int l = T[rt].l, r = T[rt].r, mid = (l + r) >> 1; if (start <= l && r <= end) return T[rt].s; if (end <= mid) return query(rt << 1, start, end); if (start > mid) return query(rt << 1 | 1, start, end); return UN(query(rt << 1, start, end), query(rt << 1 | 1, start, end)); } int main() { int n, q; scanf( %d%d , &n, &q); scanf( %s%s , G[1] + 1, G[2] + 1); build(1, 1, n); while (q--) { int a, b; scanf( %d%d , &a, &b); int l = a > n ? a - n : a, r = b > n ? b - n : b, res; if (l > r) swap(l, r), swap(a, b); Data tmp = query(1, l, r); if (a <= n && b <= n) res = tmp.p1; if (a <= n && b > n) res = tmp.p2; if (a > n && b <= n) res = tmp.p3; if (a > n && b > n) res = tmp.p4; if (res < 1e8) printf( %d n , res - 1); else printf( -1 n ); } return 0; } |
module core(
input iCLK,
input [7:0] iGPI,
output [7:0] oGPO
);
wire [31:0] wIDATA;
wire wWRDTA;
wire wWRGPR;
wire wWRSFR;
wire wWRMLR;
wire [1:0] wSGPRI;
wire [2:0] wSAOUT;
wire wUAZRO;
wire wUIMMB;
wire wPCJEN;
wire wAZERO;
wire [3:0] wSREGA;
wire [3:0] wSREGB;
wire [3:0] wSSFRR;
wire [7:0] wIMMBV;
wire [7:0] wIADDR;
wire [7:0] wGPRDI;
wire [7:0] wDTDOU;
wire [7:0] wSFRMX;
wire [7:0] wMULHB;
wire [7:0] wALOUT;
wire [7:0] wDATAA;
wire [7:0] wDATAB;
wire [7:0] wMULRG;
wire [7:0] wGPI;
wire [7:0] wGPO;
assign wGPI = iGPI;
assign oGPO = wGPO;
idecoder idecoder(
.iAZERO(wAZERO),
.iINST(wIDATA),
.oWRDTA(wWRDTA),
.oWRGPR(wWRGPR),
.oWRSFR(wWRSFR),
.oWRMLR(wWRMLR),
.oSGPRI(wSGPRI),
.oSAOUT(wSAOUT),
.oUAZRO(wUAZRO),
.oUIMMB(wUIMMB),
.oPCJEN(wPCJEN),
.oSREGA(wSREGA),
.oSREGB(wSREGB),
.oSSFRR(wSSFRR),
.oIMMBV(wIMMBV)
);
aalu aalu(
.iUAZRO(wUAZRO),
.iUIMMB(wUIMMB),
.iIMMBV(wIMMBV),
.iSAOUT(wSAOUT),
.iA(wDATAA),
.iB(wDATAB),
.oALOUT(wALOUT),
.oMULHB(wMULHB)
);
gporeg gporeg(
.iCLK(iCLK),
.iWRSFR(wWRSFR),
.iDTBUS(wDATAA),
.iSSFRR(wSSFRR),
.oGPO(wGPO)
);
mulreg mulreg(
.iCLK(iCLK),
.iWRMLR(wWRMLR),
.iMULHB(wMULHB),
.oMULRG(wMULRG)
);
gprmux gprmux(
.iDTDOU(wDTDOU),
.iSFRMX(wSFRMX),
.iALOUT(wALOUT),
.iMULRG(wMULRG),
.iSGPRI(wSGPRI),
.oGPRDI(wGPRDI)
);
sfrmux sfrmux(
.iGPI(wGPI),
.iGPO(wGPO),
.iSSFRR(wSSFRR),
.oSFRMX(wSFRMX)
);
pcreg pcreg(
.iCLK(iCLK),
.iPCRST(1'b0),
.iPCJEN(wPCJEN),
.iPCJIN(wALOUT),
.oIADDR(wIADDR)
);
gprs gprs(
.iCLK(iCLK),
.iWRGPR(wWRGPR),
.iGPRDI(wGPRDI),
.iSREGA(wSREGA),
.iSREGB(wSREGB),
.oAZERO(wAZERO),
.oDATAA(wDATAA),
.oDATAB(wDATAB)
);
rammem rammem(
.iCLK(iCLK),
.iWRDTA(wWRDTA),
.iDTBUS(wDATAA),
.iDTADR(wALOUT),
.oDTDOU(wDTDOU)
);
rommem rommem(
.iCLK(~iCLK),
.iIADDR(wIADDR),
.oIDATA(wIDATA)
);
endmodule
/***************************************************************
* ALU
***************************************************************/
module aalu(
input iUAZRO,
input iUIMMB,
input [7:0] iIMMBV,
input [2:0] iSAOUT,
input [7:0] iA,
input [7:0] iB,
output [7:0] oALOUT,
output [7:0] oMULHB
);
wire [7:0] wAOUT[7:0];
assign oALOUT = wAOUT[iSAOUT];
wire [7:0] wA;
assign wA = iUAZRO ? 8'h00 : iA;
wire [7:0] wB;
assign wB = iUIMMB ? iIMMBV : iB;
assign wAOUT[0] = iIMMBV;
assign wAOUT[1] = wA & wB;
assign wAOUT[2] = wA | wB;
assign wAOUT[3] = wA ^ wB;
assign wAOUT[4] = ~wA;
alu_add alu_add (
.dataa(wA),
.datab(wB),
.result(wAOUT[5])
);
alu_sub alu_sub (
.dataa(wA),
.datab(wB),
.result(wAOUT[6])
);
wire [15:0] wMUL;
assign wAOUT[7] = wMUL[7:0];
assign oMULHB = wMUL[15:8];
alu_mul alu_mul (
.dataa(wA),
.datab(wB),
.result(wMUL)
);
endmodule
/***************************************************************
* GPOREG
***************************************************************/
module gporeg(
input iCLK,
input iWRSFR,
input [7:0] iDTBUS,
input [3:0] iSSFRR,
output [7:0] oGPO
);
reg [7:0] rGPO = 8'h00;
assign oGPO = rGPO;
always@(posedge iCLK) begin
if(iWRSFR && (iSSFRR == 4'h01)) begin
rGPO <= iDTBUS;
end
else begin
rGPO <= rGPO;
end
end
endmodule
/***************************************************************
* MULRG
***************************************************************/
module mulreg(
input iCLK,
input iWRMLR,
input [7:0] iMULHB,
output [7:0] oMULRG
);
reg [7:0] rMULRG = 8'h00;
assign oMULRG = rMULRG;
always@(posedge iCLK) begin
if(iWRMLR) begin
rMULRG <= iMULHB;
end
else begin
rMULRG <= rMULRG;
end
end
endmodule
/***************************************************************
* GPRMUX
***************************************************************/
module gprmux(
input [7:0] iDTDOU,
input [7:0] iSFRMX,
input [7:0] iALOUT,
input [7:0] iMULRG,
input [1:0] iSGPRI,
output [7:0] oGPRDI
);
wire [7:0] wGPRMX[7:0];
assign oGPRDI = wGPRMX[iSGPRI];
assign wGPRMX[0] = iDTDOU;
assign wGPRMX[1] = iSFRMX;
assign wGPRMX[2] = iALOUT;
assign wGPRMX[3] = iMULRG;
endmodule
/***************************************************************
* SFRMUX
***************************************************************/
module sfrmux(
input [7:0] iGPI,
input [7:0] iGPO,
input [3:0] iSSFRR,
output [7:0] oSFRMX
);
wire [7:0] wSFRMX[7:0];
assign oSFRMX = wSFRMX[iSSFRR];
assign wSFRMX[0] = iGPI;
assign wSFRMX[1] = iGPO;
endmodule
/***************************************************************
* PC
***************************************************************/
module pcreg(
input iCLK,
input iPCRST,
input iPCJEN,
input [7:0] iPCJIN,
output [7:0] oIADDR
);
reg [7:0] rPC = 8'h00;
assign oIADDR = rPC;
always@(posedge iCLK) begin
if(iPCRST) begin
rPC <= 8'h00;
end
else begin
if(iPCJEN) begin
rPC <= iPCJIN;
end
else begin
rPC <= rPC + 8'd1;
end
end
end
endmodule
/***************************************************************
* GPRs
***************************************************************/
module gprs(
input iCLK,
input iWRGPR,
input [7:0] iGPRDI,
input [3:0] iSREGA,
input [3:0] iSREGB,
output oAZERO,
output [7:0] oDATAA,
output [7:0] oDATAB
);
reg [7:0] rGPRS[7:0];
integer k;
initial
begin
for (k = 0; k < 8 ; k = k + 1) begin : init_rGPRS
rGPRS[k] = 8'h00;
end
end
assign oDATAA = rGPRS[iSREGA];
assign oDATAB = rGPRS[iSREGB];
assign oAZERO = oDATAA == 8'h00;
always@(posedge iCLK) begin
if(iWRGPR) begin
rGPRS[iSREGA] <= iGPRDI;
end
end
endmodule
/***************************************************************
* RAM
***************************************************************/
module rammem(
input iCLK,
input iWRDTA,
input [7:0] iDTBUS,
input [7:0] iDTADR,
output [7:0] oDTDOU
);
datamem ram (
.address(iDTADR),
.clock(iCLK),
.data(iDTBUS),
.wren(iWRDTA),
.q(oDTDOU)
);
endmodule
/***************************************************************
* ROM
***************************************************************/
module rommem(
input iCLK,
input [7:0] iIADDR,
output [31:0] oIDATA
);
progmem rom (
.address(iIADDR),
.clock(iCLK),
.q(oIDATA)
);
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_PWRGOOD_PP_PG_SYMBOL_V
`define SKY130_FD_SC_HD__UDP_PWRGOOD_PP_PG_SYMBOL_V
/**
* UDP_OUT :=x when VPWR!=1 or VGND!=0
* UDP_OUT :=UDP_IN when VPWR==1 and VGND==0
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__udp_pwrgood_pp$PG (
//# {{data|Data Signals}}
input UDP_IN ,
output UDP_OUT,
//# {{power|Power}}
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_PWRGOOD_PP_PG_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> a(n + 1); vector<int> b(n + 1); for (int i = 1; i <= n; i++) cin >> a[i]; sort(a.begin() + 1, a.end()); for (int i = 1; i <= n / 2; i++) b[2 * i] = a[i]; for (int i = n / 2 + 1; i <= n; i++) b[(i - n / 2) * 2 - 1] = a[i]; int ans = 0; for (int i = 2; i < n; i++) ans += (b[i] < b[i - 1]) * (b[i] < b[i + 1]); cout << ans << endl; for (auto i = b.begin() + 1; i != b.end(); i++) cout << *i << ; cout << endl; } |
#include <bits/stdc++.h> using namespace std; template <typename A, typename B> string to_string(pair<A, B> p); template <typename A, typename B, typename C> string to_string(tuple<A, B, C> p); string to_string(const string& s) { return + s + ; } string to_string(const char* s) { return to_string((string)s); } string to_string(bool b) { return (b ? true : false ); } string to_string(vector<bool> v) { bool f = true; string res = { ; for (long long i = (0); i <= (static_cast<long long>(v.size()) - 1); i++) { if (!f) res += , ; res += to_string(v[i]); f = false; } res += } ; return res; } template <size_t N> string to_string(bitset<N> v) { string res = ; for (auto& a : v) { res += (char)( 0 + a); } return res; } template <typename A> string to_string(A v) { bool f = true; string res = { ; for (auto& x : v) { if (!f) res += , ; res += to_string(x); f = false; } res += } ; return res; } template <typename A, typename B> string to_string(pair<A, B> p) { return ( + to_string(p.first) + , + to_string(p.second) + ) ; } template <typename A, typename B, typename C> string to_string(tuple<A, B, C> t) { return ( + to_string(get<0>(t)) + , + to_string(get<1>(t)) + , + to_string(get<2>(t)) + ) ; } void DBG() { cerr << endl; } template <typename H, typename... T> void DBG(H h, T... t) { cerr << << to_string(h); DBG(t...); } template <typename T> void re(T& x) { cin >> x; }; template <typename H, typename... T> void re(H& h, T&... t) { re(h); re(t...); } template <typename T> void pr(T x) { cout << x; }; template <typename H, typename... T> void pr(H h, T... t) { pr(h); pr(t...); } int main() { ios::sync_with_stdio(false); cin.tie(0); long long tt; re(tt); while (tt--) { string s; re(s); long long n = (long long)s.size(); long long a, b, c; a = b = c = -1; long long inf = (long long)9e18; long long ans = inf; for (long long i = (0); i <= (n - 1); i++) { if (s[i] == 1 ) { a = i; if (b == -1 || c == -1) continue; ans = min(ans, i - min(b, c) + 1); } if (s[i] == 2 ) { b = i; if (a == -1 || c == -1) continue; ans = min(ans, i - min(a, c) + 1); } if (s[i] == 3 ) { c = i; if (b == -1 || a == -1) continue; ans = min(ans, i - min(b, a) + 1); } } pr((ans == inf ? 0 : ans), n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; vector<int> primes; void sieve() { vector<bool> isComposite(100000000, false); for (int i = 2; i * i <= 100000000; i++) { if (isComposite[i] == false) for (int j = i * 2; j <= 100000000; j += i) isComposite[j] = true; } for (int i = 2; i <= 100000000; i++) if (isComposite[i] == false) primes.push_back(i); for (auto it : primes) cout << it << ; } long long LCM(int n) { long long lcm = 1; for (int i = 0; i < primes.size() && primes[i] <= n; i++) { int pp = primes[i]; while (pp * primes[i] <= n) pp = pp * primes[i]; lcm *= pp; lcm %= 1000000007; } return lcm; } int main() { int t; cin >> t; while (t--) { long long int n; string keyboard; string s; cin >> keyboard; cin >> s; map<char, int> mp; for (int i = 0; i < keyboard.size(); i++) { mp[keyboard[i]] = i + 1; } long long int time = 0; for (int i = 1; i < s.length(); i++) { time += abs((mp[s[i]] - mp[s[i - 1]])); } cout << time << n ; } } |
/*
* PicoSoC - A simple example SoC using PicoRV32
*
* Copyright (C) 2017 Clifford Wolf <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module top (
input clk,
output tx,
input rx,
input [3:0] sw,
output [3:0] led
);
wire clk_bufg;
BUFG bufg (
.I(clk),
.O(clk_bufg)
);
reg [5:0] reset_cnt = 0;
wire resetn = &reset_cnt;
always @(posedge clk_bufg) begin
reset_cnt <= reset_cnt + !resetn;
end
wire iomem_valid;
reg iomem_ready;
wire [ 3:0] iomem_wstrb;
wire [31:0] iomem_addr;
wire [31:0] iomem_wdata;
reg [31:0] iomem_rdata;
reg [31:0] gpio;
assign led = gpio[3:0];
always @(posedge clk_bufg) begin
if (!resetn) begin
gpio <= 0;
end else begin
iomem_ready <= 0;
if (iomem_valid && !iomem_ready && iomem_addr[31:24] == 8'h03) begin
iomem_ready <= 1;
iomem_rdata <= {4{sw, gpio[3:0]}};
if (iomem_wstrb[0]) gpio[7:0] <= iomem_wdata[7:0];
if (iomem_wstrb[1]) gpio[15:8] <= iomem_wdata[15:8];
if (iomem_wstrb[2]) gpio[23:16] <= iomem_wdata[23:16];
if (iomem_wstrb[3]) gpio[31:24] <= iomem_wdata[31:24];
end
end
end
picosoc_noflash soc (
.clk (clk_bufg),
.resetn(resetn),
.ser_tx(tx),
.ser_rx(rx),
.irq_5(1'b0),
.irq_6(1'b0),
.irq_7(1'b0),
.iomem_valid(iomem_valid),
.iomem_ready(iomem_ready),
.iomem_wstrb(iomem_wstrb),
.iomem_addr (iomem_addr),
.iomem_wdata(iomem_wdata),
.iomem_rdata(iomem_rdata)
);
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFDS_DIFF_OUT.v,v 1.10 2010/11/03 22:31:02 fphillip Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Differential Signaling Input Buffer with Differential Outputs
// /___/ /\ Filename : IBUFDS_DIFF_OUT.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:23 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
// 05/13/08 - CR 458290 -- Added else condition to handle x case.
// 02/10/09 - CR 430124 -- Added attribute DIFF_TERM.
// 06/02/09 - CR 523083 -- Added attribute IBUF_LOW_PWR.
// 11/03/10 - CR 576577 -- changed default value of IOSTANDARD from LVDS_25 to DEFAULT.
// 09/30/11 - CR 626400 -- Added PATHPULSE
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IBUFDS_DIFF_OUT (O, OB, I, IB);
parameter DIFF_TERM = "FALSE";
parameter DQS_BIAS = "FALSE";
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
`ifdef XIL_TIMING
parameter LOC = " UNPLACED";
`endif
output O, OB;
input I, IB;
reg o_out;
reg DQS_BIAS_BINARY = 1'b0;
buf B0 (O, o_out);
not B1 (OB, o_out);
initial begin
case (DIFF_TERM)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute DIFF_TERM on IBUFDS_DIFF_OUT instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DIFF_TERM);
$finish;
end
endcase // case(DIFF_TERM)
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUFDS_DIFF_OUT instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR);
$finish;
end
endcase
case (DQS_BIAS)
"TRUE" : DQS_BIAS_BINARY <= #1 1'b1;
"FALSE" : DQS_BIAS_BINARY <= #1 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute DQS_BIAS on IBUFDS_DIFF_OUT instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DQS_BIAS);
$finish;
end
endcase
end
always @(I or IB or DQS_BIAS_BINARY) begin
if (I == 1'b1 && IB == 1'b0)
o_out <= I;
else if (I == 1'b0 && IB == 1'b1)
o_out <= I;
else if ((I === 1'bz || I == 1'b0) && (IB === 1'bz || IB == 1'b1))
if (DQS_BIAS_BINARY == 1'b1)
o_out <= 1'b0;
else
o_out <= 1'bx;
else if (I == 1'bx || IB == 1'bx)
o_out <= 1'bx;
end
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(I => OB) = (0:0:0, 0:0:0);
(IB => O) = (0:0:0, 0:0:0);
(IB => OB) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; int arr[4005]; int nxt[4005], prv[4005]; map<int, int> M; map<int, int> Q; int main() { int n; cin >> n; int ans = 0; for (int i = 0; i < n; ++i) { cin >> arr[i]; if (M.find(arr[i]) != M.end()) { nxt[M[arr[i]]] = i; prv[i] = M[arr[i]]; Q[arr[i]]++; ans = max(ans, Q[arr[i]]); } else { prv[i] = -1; Q[arr[i]]++; ans = max(ans, Q[arr[i]]); } M[arr[i]] = i; nxt[i] = -1; } for (int i = 0; i < n; ++i) { if (prv[i] != -1) { continue; } for (int j = i + 1; j < n; ++j) { if (prv[j] != -1) { continue; } int cur = 2; int t1 = i, t2 = j; while (t1 != -1 && t2 != -1) { if (t1 < t2) { if (nxt[t1] > t2) { ++cur; } t1 = nxt[t1]; } else { if (nxt[t2] > t1) { ++cur; } t2 = nxt[t2]; } } ans = max(ans, cur); } } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, w[200200], h[200200], W, a[200200], maxH, maxH2, id; int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) { scanf( %d%d , &w[i], &h[i]); if (h[i] > maxH) { maxH = h[i]; id = i; } W += w[i]; } for (int i = 1; i <= n; ++i) { if (i != id) maxH2 = max(maxH2, h[i]); } for (int i = 1; i <= n; ++i) { if (h[i] == maxH) printf( %d , maxH2 * (W - w[i])); else printf( %d , maxH * (W - w[i])); } return 0; } |
// Copyright 2012 Sriram Radhakrishnan, Varun Sampath, Shilpa Sarode
//
// This file is part of PVS.
//
// PVS is free software: you can redistribute it and/or modify it under the
// terms of the GNU General Public License as published by the Free Software
// Foundation, either version 3 of the License, or (at your option) any later
// version.
//
// PVS is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// PVS. If not, see <http://www.gnu.org/licenses/>.
`timescale 1 ns / 1 ns
// Transmits a 4-byte internal counter value using Serial I/O
// inputs:
// clk_fast - 50MHz fast clock for serial I/O
// clk_slow - speed for counter to increment, and transmission interval
// counter - 4-byte counter to transmit
// header - 8-bit header byte for identification
// go - when to transmit (gets latched)
// outputs:
// TxD - output serial transmission
// done - goes high when complete (width of clk_slow period)
module clock_transmitter
(
clk_fast,
clk_slow,
counter,
header,
go,
TxD,
done
);
input clk_fast;
input clk_slow;
input [31:0] counter;
input [7:0] header;
input go;
output TxD;
output done;
parameter s_idle = 0;
parameter s_transmit_tx = 1;
parameter s_transmit_wait = 2;
parameter s_inc_byte = 3;
parameter s_finish = 4;
reg[3:0] state = 4'd0;
reg[7:0] data = 8'd0;
reg[3:0] byte_count = 4'd0;
reg go_reg = 1'b0;
reg go_reg_prev = 1'b0;
reg [7:0] header_reg = 8'd0;
reg [31:0] transmit_buf = 8'd0;
wire tx_start_pulse;
reg tx_start = 1'b0;
wire tx_busy;
wire tx_out;
// need these "one pulses" to ensure
// transmitter is only started once during wait period
rising_edge_detect tx_detect
(
.clk(clk_fast),
.signal(tx_start),
.pulse(tx_start_pulse)
);
// state machine:
// sits at idle until receives 'go'
// starts transmitting, then waits for transmission to complete
// transmits next 8-bits
// continues until 32 bits transmitted
always @(posedge clk_slow) begin
case(state)
s_idle:
begin
go_reg <= go & !go_reg_prev;
// hold onto header throughout transmission; reset in s_finish
if (header_reg == 8'd0) header_reg <= header;
state <= (go_reg) ? s_transmit_tx : s_idle;
transmit_buf <= (go_reg) ? counter : 32'd0;
byte_count <= 4'd0;
go_reg_prev <= go_reg;
end
s_transmit_tx:
begin
tx_start <= (byte_count < 4'd5);
data <= (byte_count == 4'd0) ? header_reg :
(byte_count == 4'd1) ? transmit_buf[7:0] :
(byte_count == 4'd2) ? transmit_buf[15:8] :
(byte_count == 4'd3) ? transmit_buf[23:16] :
(byte_count == 4'd4) ? transmit_buf[31:24] :
8'b0;
state <= (byte_count < 4'd5) ? s_transmit_wait : s_finish;
end
s_transmit_wait:
begin
state <= (tx_busy) ? s_transmit_wait : s_inc_byte;
tx_start <= 0;
end
s_inc_byte:
begin
byte_count <= byte_count + 4'b1;
state <= s_transmit_tx;
end
s_finish:
begin
state <= s_idle;
header_reg <= 8'b0;
end
endcase
end
// declare transmitter
async_transmitter tx
(
.clk(clk_fast),
.TxD_start(tx_start_pulse),
.TxD_data(data),
.TxD(tx_out),
.TxD_busy(tx_busy)
);
// assign outputs
assign done = (state == s_finish);
reg TxD;
always @(posedge clk_fast)
TxD <= (tx_busy) ? tx_out : 1'b1;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int dx[4] = {1, 0, -1, 0}, dy[4] = {0, 1, 0, -1}; bool ckmin(int& a, int b) { return b < a ? a = b, true : false; } bool ckmax(int& a, int b) { return b > a ? a = b, true : false; } const long long linf = 4000000000000000000LL; const long long inf = 1000000007; const long double pi = 3.1415926535; void pv(vector<int> a) { for (auto& x : a) cout << x << ; cout << n ; } void pv(vector<long long> a) { for (auto& x : a) cout << x << ; cout << n ; } void pv(vector<vector<int> > a) { for (int i = (0); i < (int(a.size())); ++i) { cout << i << n ; pv(a[i]); cout << n ; } } void pv(vector<vector<long long> > a) { for (int i = (0); i < (int(a.size())); ++i) { cout << i << n ; pv(a[i]); } cout << n ; } void pv(vector<string> a) { for (auto& x : a) cout << x << n ; cout << n ; } void setIO(string second) { ios_base::sync_with_stdio(0); cin.tie(0); if (int(second.size())) { freopen((second + .in ).c_str(), r , stdin); if (second != test1 ) freopen((second + .out ).c_str(), w , stdout); } } int main() { setIO( ); int n; cin >> n; vector<long long> a(n); for (auto& x : a) cin >> x; vector<int> count(60); for (int i = (0); i < (n); ++i) { int ans = 0; while (!(a[i] & 1)) { ans++; a[i] >>= 1; } a[i] <<= ans; count[ans]++; } int index = max_element(count.begin(), count.end()) - count.begin(); cout << n - count[index] << n ; if (index == 0) { for (int i = (0); i < (n); ++i) { if (a[i] & 1) ; else cout << a[i] << ; } return 0; } for (int i = (0); i < (n); ++i) { if ((((a[i] >> index) & 1)) && !((a[i] >> index - 1) & 1)) { } else { cout << a[i] << ; } } } |
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_sync_flops.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core receiver logic ////
//// ////
//// Known problems (limits): ////
//// None known ////
//// ////
//// To Do: ////
//// Thourough testing. ////
//// ////
//// Author(s): ////
//// - Andrej Erzen () ////
//// - Tadej Markovic () ////
//// ////
//// Created: 2004/05/20 ////
//// Last Updated: 2004/05/20 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: uart_sync_flops.v,v $
// Revision 1.1 2006-12-21 16:46:58 vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.1 2004/05/21 11:43:25 tadejm
// Added to synchronize RX input to Wishbone clock.
//
//
`include "timescale.v"
module uart_sync_flops
(
// internal signals
rst_i,
clk_i,
stage1_rst_i,
stage1_clk_en_i,
async_dat_i,
sync_dat_o
);
parameter Tp = 1;
parameter width = 1;
parameter init_value = 1'b0;
input rst_i; // reset input
input clk_i; // clock input
input stage1_rst_i; // synchronous reset for stage 1 FF
input stage1_clk_en_i; // synchronous clock enable for stage 1 FF
input [width-1:0] async_dat_i; // asynchronous data input
output [width-1:0] sync_dat_o; // synchronous data output
//
// Interal signal declarations
//
reg [width-1:0] sync_dat_o;
reg [width-1:0] flop_0;
// first stage
always @ (posedge clk_i or posedge rst_i)
begin
if (rst_i)
flop_0 <= #Tp {width{init_value}};
else
flop_0 <= #Tp async_dat_i;
end
// second stage
always @ (posedge clk_i or posedge rst_i)
begin
if (rst_i)
sync_dat_o <= #Tp {width{init_value}};
else if (stage1_rst_i)
sync_dat_o <= #Tp {width{init_value}};
else if (stage1_clk_en_i)
sync_dat_o <= #Tp flop_0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 200200; int n, k; int a[maxn]; vector<int> g[maxn]; int sz[maxn]; int dpd[maxn], dpu[maxn]; int mxd[maxn], mxu[maxn]; int mark[maxn], cnt[maxn]; int mxc[maxn], N; int ans; void dfs(int v, int par = -1) { sz[v] = 1; cnt[v] = mark[v]; int c = 0; for (int u : g[v]) if (u != par) { dfs(u, v); cnt[v] += cnt[u]; sz[v] += sz[u]; if (!cnt[u]) { dpd[v] += dpd[u]; mxd[v] += dpd[u]; } else c = max(c, mxd[u]); } if (mark[v]) dpd[v] = 0, mxd[v] = 0; else dpd[v]++, mxd[v] += c + 1; } void gfs(int v, int par = -1) { if (cnt[v] == N) dpu[v] = n - sz[v]; if (!mark[v]) { mxu[v] += mxc[v]; int d, c; if (cnt[v] == N) d = dpu[v] + 1, c = 0; else d = 1, c = mxu[v]; for (int u : g[v]) if (u != par) { mxu[u] += d; mxc[u] = max(mxc[u], c); if (!cnt[u]) d += dpd[u]; else c = max(c, mxd[u]); } reverse(g[v].begin(), g[v].end()); d = 0, c = 0; for (int u : g[v]) if (u != par) { mxu[u] += d; mxc[u] = max(mxc[u], c); if (!cnt[u]) d += dpd[u]; else c = max(c, mxd[u]); } } else dpu[v] = mxu[v] = 0; for (int u : g[v]) if (u != par) gfs(u, v); } bool check(int x) { N = 0; memset(sz, 0, sizeof sz); memset(dpd, 0, sizeof dpd); memset(dpu, 0, sizeof dpu); memset(mxc, 0, sizeof mxc); memset(mxd, 0, sizeof mxd); memset(mxu, 0, sizeof mxu); for (int i = 0; i < n; i++) mark[i] = (a[i] < x); for (int i = 0; i < n; i++) N += mark[i]; dfs(0); gfs(0); for (int i = 0; i < n; i++) if (!mark[i]) if (mxd[i] + dpu[i] >= k or mxu[i] + dpd[i] >= k) return true; return false; } void solve() { int l = 1, r = 1000001; int mid; while (l != r - 1) { mid = (l + r) >> 1; if (check(mid)) l = mid; else r = mid; } ans = l; } int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n >> k; for (int i = 0; i < n; i++) cin >> a[i]; for (int v, u, i = 0; i < n - 1; i++) { cin >> v >> u; v--, u--; g[v].push_back(u); g[u].push_back(v); } solve(); cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MM = 2e5 + 5; int n, k, a, b, q, pref[MM], suff[MM], cnt[MM]; void upd(int bit[], int x, int v) { for (; x < MM; x += x & -x) { bit[x] += v; } } int get(int bit[], int x) { int res = 0; for (; x > 0; x -= x & -x) res += bit[x]; return res; } int get(int bit[], int l, int r) { return get(bit, r) - get(bit, l - 1); } int main() { cin.tie(0)->sync_with_stdio(0); cin >> n >> k >> a >> b >> q; while (q--) { int t; cin >> t; if (t == 1) { int x, v; cin >> x >> v; int val = min(b, v + cnt[x]); int diff = val - get(pref, x, x); upd(pref, x, diff); val = min(a, v + cnt[x]); diff = val - get(suff, x, x); upd(suff, x, diff); cnt[x] += v; } else { int p; cin >> p; int ans = get(pref, p - 1); ans += get(suff, p + k, MM - 1); cout << ans << n ; } } } |
#include <bits/stdc++.h> using namespace std; using namespace std; vector<bool> Prime(20000000 + 1, 1); vector<bool> Pal(20000000 + 1, 1); void gen1() { long long int n = 2000000; Prime[1] = 0; for (long long int i = 2; i <= 20000000; i++) { if (Prime[i]) { for (long long int j = i + i; j <= n; j += i) Prime[j] = false; } } } void gen2() { long long int n = 20000000; long long int num, rev = 0, digit; for (long long int i = 1; i <= 20000000; i++) { num = i; while (num > 0) { digit = num % 10; rev = rev * 10 + digit; num = num / 10; } if (i != rev) Pal[i] = false; rev = 0; } } long long int a, b; int main() { ios::sync_with_stdio(false); gen1(), gen2(); cin >> a >> b; long long int ans = 1, primes = 0, pals = 0; for (long long int i = 1; i <= 20000000; i++) { if (Prime[i]) primes++; if (Pal[i]) pals++; if (b * primes <= a * pals) ans = max(ans, i); } cout << ans; } |
//#############################################################################
//# Function: Padring Generator #
//# Copyright: OH Project Authors. ALl rights Reserved. #
//# License: MIT (see LICENSE file in OH repository) #
//#############################################################################
module oh_padring
#(parameter TYPE = "SOFT",// asic cell type selector
parameter NO_DOMAINS = 1, // total domains
parameter NO_GPIO = 8, // total IO signal pads
parameter NO_VDDIO = 8, // total IO supply pads
parameter NO_VSSIO = 8, // total IO ground pads
parameter NO_VDD = 8, // total core supply pads
parameter NO_VSS = 8, // total core ground pads
parameter SO_DOMAINS = 1, // ...
parameter SO_GPIO = 8,
parameter SO_VDDIO = 8,
parameter SO_VSSIO = 8,
parameter SO_VDD = 8,
parameter SO_VSS = 8,
parameter EA_DOMAINS = 1,
parameter EA_GPIO = 8,
parameter EA_VDDIO = 8,
parameter EA_VSSIO = 8,
parameter EA_VDD = 8,
parameter EA_VSS = 8,
parameter WE_DOMAINS = 1,
parameter WE_GPIO = 8,
parameter WE_VDDIO = 8,
parameter WE_VSSIO = 8,
parameter WE_VDD = 8,
parameter WE_VSS = 8
)
(
//CONTINUOUS GROUND
inout vss,
inout vdd,
//NORTH
inout [NO_DOMAINS-1:0] no_vddio,
inout [NO_DOMAINS-1:0] no_vssio,
inout [NO_GPIO-1:0] no_pad, // pad
output [NO_GPIO-1:0] no_din, // data from pad
input [NO_GPIO-1-1:0] no_dout, // data to pad
input [NO_GPIO*8-1:0] no_cfg, // config
input [NO_GPIO-1:0] no_ie, // input enable
input [NO_GPIO-1:0] no_oen, // output enable (bar)
//SOUTH
inout [SO_DOMAINS-1:0] so_vddio,
inout [SO_DOMAINS-1:0] so_vssio,
inout [SO_GPIO-1:0] so_pad, // pad
output [SO_GPIO-1:0] so_din, // data from pad
input [SO_GPIO-1-1:0] so_dout, // data to pad
input [SO_GPIO*8-1:0] so_cfg, // config
input [SO_GPIO-1:0] so_ie, // input enable
input [SO_GPIO-1:0] so_oen, // output enable (bar)
//EAST
inout [EA_DOMAINS-1:0] ea_vddio,
inout [EA_DOMAINS-1:0] ea_vssio,
inout [EA_GPIO-1:0] ea_pad, // pad
output [EA_GPIO-1:0] ea_din, // data from pad
input [EA_GPIO-1-1:0] ea_dout, // data to pad
input [EA_GPIO*8-1:0] ea_cfg, // config
input [EA_GPIO-1:0] ea_ie, // input enable
input [EA_GPIO-1:0] ea_oen, // output enable (bar)
//WEST
inout [WE_DOMAINS-1:0] we_vddio,
inout [WE_DOMAINS-1:0] we_vssio,
inout [WE_GPIO-1:0] we_pad, // pad
output [WE_GPIO-1:0] we_din, // data from pad
input [WE_GPIO-1-1:0] we_dout, // data to pad
input [WE_GPIO*8-1:0] we_cfg, // config
input [WE_GPIO-1:0] we_ie, // input enable
input [WE_GPIO-1:0] we_oen // output enable (bar)
);
//Local wires
wire [NO_DOMAINS-1:0] no_poc;
wire [SO_DOMAINS-1:0] so_poc;
wire [WE_DOMAINS-1:0] we_poc;
wire [EA_DOMAINS-1:0] ea_poc;
generate
genvar i;
//#############################
// NORTH
//#############################
for(i=0;i<NO_DOMAINS;i=i+1)
begin: no_pads
oh_pads_domain #(.DIR("NO"),
.TYPE(TYPE),
.NGPIO(NO_GPIO),
.NVDDIO(NO_VDDIO),
.NVSSIO(NO_VSSIO),
.NVDD(NO_VDD),
.NVSS(NO_VSS),
.POC(1),
.LEFTCUT(1),
.RIGHTCUT(1))
i0 (.vdd (vdd),
.vss (vss),
// Outputs
.din (no_din[NO_GPIO-1:0]),
// Inouts
.pad (no_pad[NO_GPIO-1:0]),
.vddio (no_vddio[i]),
.vssio (no_vssio[i]),
.poc (no_poc[i]),
// Inputs
.dout (no_dout[NO_GPIO-1:0]),
.oen (no_oen[NO_GPIO-1:0]),
.ie (no_ie[NO_GPIO-1:0]),
.cfg (no_cfg[NO_GPIO*8-1:0]));
end
//#############################
// SOUTH
//#############################
for(i=0;i<SO_DOMAINS;i=i+1)
begin: so_pads
oh_pads_domain #(.DIR("SO"),
.TYPE(TYPE),
.NGPIO(SO_GPIO),
.NVDDIO(SO_VDDIO),
.NVSSIO(SO_VSSIO),
.NVDD(SO_VDD),
.NVSS(SO_VSS),
.POC(1),
.LEFTCUT(1),
.RIGHTCUT(1))
i0 (.vdd (vdd),
.vss (vss),
// Outputs
.din (so_din[SO_GPIO-1:0]),
// Inouts
.pad (so_pad[SO_GPIO-1:0]),
.vddio (so_vddio[i]),
.vssio (so_vssio[i]),
.poc (so_poc[i]),
// Inputs
.dout (so_dout[SO_GPIO-1:0]),
.oen (so_oen[SO_GPIO-1:0]),
.ie (so_ie[SO_GPIO-1:0]),
.cfg (so_cfg[SO_GPIO*8-1:0]));
end
//#############################
// EAST
//#############################
for(i=0;i<EA_DOMAINS;i=i+1)
begin: ea_pads
oh_pads_domain #(.DIR("EO"),
.TYPE(TYPE),
.NGPIO(EA_GPIO),
.NVDDIO(EA_VDDIO),
.NVSSIO(EA_VSSIO),
.NVDD(EA_VDD),
.NVSS(EA_VSS),
.POC(1),
.LEFTCUT(1),
.RIGHTCUT(1))
i0 (.vdd (vdd),
.vss (vss),
// Outputs
.din (ea_din[EA_GPIO-1:0]),
// Inouts
.pad (ea_pad[EA_GPIO-1:0]),
.vddio (ea_vddio[i]),
.vssio (ea_vssio[i]),
.poc (ea_poc[i]),
// Inputs
.dout (ea_dout[EA_GPIO-1:0]),
.oen (ea_oen[EA_GPIO-1:0]),
.ie (ea_ie[EA_GPIO-1:0]),
.cfg (ea_cfg[EA_GPIO*8-1:0]));
end
//#############################
// WEST
//#############################
for(i=0;i<WE_DOMAINS;i=i+1)
begin: we_pads
oh_pads_domain #(.DIR("WE"),
.TYPE(TYPE),
.NGPIO(WE_GPIO),
.NVDDIO(WE_VDDIO),
.NVSSIO(WE_VSSIO),
.NVDD(WE_VDD),
.NVSS(WE_VSS),
.POC(1),
.LEFTCUT(1),
.RIGHTCUT(1))
i0 (.vdd (vdd),
.vss (vss),
// Outputs
.din (we_din[WE_GPIO-1:0]),
// Inouts
.pad (we_pad[WE_GPIO-1:0]),
.vddio (we_vddio[i]),
.vssio (we_vssio[i]),
.poc (we_poc[i]),
// Inputs
.dout (we_dout[WE_GPIO-1:0]),
.oen (we_oen[WE_GPIO-1:0]),
.ie (we_ie[WE_GPIO-1:0]),
.cfg (we_cfg[WE_GPIO*8-1:0]));
end
endgenerate
endmodule // oh_padring
|
#include <bits/stdc++.h> using namespace std; long long n, m, vet[202020], cap[202020]; set<long long> s; int main() { scanf( %lld , &n); for (long long i = 1; i <= n; i++) scanf( %lld , &cap[i]), s.insert(i); scanf( %lld , &m); long long op, x, p, k; while (m--) { scanf( %lld , &op); if (op == 1) { scanf( %lld %lld , &p, &x); for (auto it = s.lower_bound(p); it != s.end() && x; it = s.erase(it)) { long long id = *it; if (cap[id] - vet[id] > x) { vet[id] += x; break; } x -= cap[id] - vet[id]; vet[id] = cap[id]; } } else { scanf( %lld , &k); printf( %lld n , vet[k]); } } } |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:512000000 ) using namespace std; void solve(); void precalc(); clock_t start; int testNumber = 1; bool todo = true; int main() { start = clock(); int t = 1; cout.sync_with_stdio(0); cin.tie(0); precalc(); cout.precision(10); cout << fixed; int testNum = 1; while (t--) { solve(); ++testNumber; } return 0; } template <typename T> T binpow(T q, T w, T mod) { if (!w) return 1 % mod; if (w & 1) return q * 1LL * binpow(q, w - 1, mod) % mod; return binpow(q * 1LL * q % mod, w / 2, mod); } void precalc() {} template <typename T> T gcd(T q, T w) { while (w) { q %= w; swap(q, w); } return q; } template <typename T> T lcm(T q, T w) { return q / gcd(q, w) * w; } struct SegTree { const int shift = 1 << 18; vector<int> tree; SegTree() { tree.assign(2 * shift, 0); } int rmq(int l, int r) { if (l >= r) { return 0; } if (l & 1) { return tree[l] + rmq(l + 1, r); } if (r & 1) { return tree[r - 1] + rmq(l, r - 1); } return rmq(l / 2, r / 2); } int get_sum(int l, int r) { return rmq(l + shift, r + shift); } void update(int v, int val) { v += shift; tree[v] = val; v /= 2; while (v) { tree[v] = tree[2 * v] + tree[2 * v + 1]; v /= 2; } } }; void solve() { int n, k, Q; vector<int> a(2); cin >> n >> k >> a[0] >> a[1] >> Q; vector<int> sums(n, 0); vector<SegTree> tree(2); for (int w = 0; w < Q; ++w) { int type; cin >> type; if (type == 1) { int day, num; cin >> day >> num; --day; sums[day] += num; for (int i = 0; i < 2; ++i) { tree[i].update(day, min(sums[day], a[i])); } } else { int l; cin >> l; --l; long long res = (long long)tree[1].get_sum(0, l) + (long long)tree[0].get_sum(l + k, n); cout << res << n ; } } } |
#include <bits/stdc++.h> using namespace std; int n, w; double tmp; vector<double> a; vector<double> boy; vector<double> girl; double volume; double base; int main() { cin >> n >> w; for (int i = 0; i < (2 * n); i++) { cin >> tmp; a.push_back(tmp); } sort(a.begin(), a.end()); girl.assign(a.begin(), a.begin() + n); boy.assign(a.begin() + n, a.end()); if (boy[0] / 2 > girl[0]) base = girl[0]; else base = boy[0] / 2; volume = (3 * base * n); if (volume > w) volume = w; cout << fixed << setprecision(10) << volume; return 0; } |
#include <bits/stdc++.h> int main() { int loop, cnt = 1, max = 1; scanf( %d , &loop); int arr[loop]; for (int i = 0; i < loop; i++) scanf( %d , &arr[i]); for (int i = 1; i < loop; i++) { if (arr[i - 1] >= arr[i]) { cnt = 1; } if (arr[i - 1] < arr[i]) { cnt++; } if (max < cnt) max = cnt; } printf( %d , max); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR2B_FUNCTIONAL_V
`define SKY130_FD_SC_LP__OR2B_FUNCTIONAL_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__or2b (
X ,
A ,
B_N
);
// Module ports
output X ;
input A ;
input B_N;
// Local signals
wire not0_out ;
wire or0_out_X;
// Name Output Other arguments
not not0 (not0_out , B_N );
or or0 (or0_out_X, not0_out, A );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR2B_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; void solve() { int x, y, z; cin >> x >> y >> z; if (x > 0) { cout << 0 ; for (int i = 1; i <= x; i++) cout << 0 ; } if (y > 0) { if (x == 0) cout << 0 ; cout << 1 ; y--; } else if (z > 0 && y == 0 && x == 0) { cout << 1 ; } for (int i = 1; i <= z; i++) cout << 1 ; int m = 0; while (y > 0) { cout << m; if (m == 0) m = 1; else m = 0; y--; } cout << endl; } int main() { ios::sync_with_stdio(0); cin.tie(0); int t; cin >> t; while (t > 0) { solve(); t -= 1; } return 0; } |
#include <bits/stdc++.h> using namespace std; string s; long cmpduong(string s1, string s2) { long len1 = s1.size(); long len2 = s2.size(); if (len1 < len2) return 2; if (len1 == len2) { if (s1 > s2) return 1; else return 2; } if (len1 > len2) return 1; } long cmp_am(string s1, string s2) { long len1 = s1.size(); long len2 = s2.size(); if (len1 < len2) return 1; if (len1 == len2) { if (s1 >= s2) return 2; else return 1; } if (len1 > len2) return 2; } long check(string s) { string tam = - + s; if (s[0] == - ) { if (cmp_am(s, -128 ) == 1) return 1; if (cmp_am(s, -32768 ) == 1) return 2; if (cmp_am(s, -2147483648 ) == 1) return 3; if (cmp_am(s, -9223372036854775808 ) == 1) return 4; return 5; } else { if (cmpduong(s, 127 ) == 2) return 1; if (cmpduong(s, 32767 ) == 2) return 2; if (cmpduong(s, 2147483647 ) == 2) return 3; if (cmpduong(s, 9223372036854775807 ) == 2) return 4; return 5; } } int main() { cin >> s; if (check(s) == 1) cout << byte << endl; if (check(s) == 2) cout << short << endl; if (check(s) == 3) cout << int << endl; if (check(s) == 4) cout << long << endl; if (check(s) == 5) cout << BigInteger << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; vector<string> split(const string& s, const string& delim = ) { vector<string> res; string t; for (int i = 0; i != s.size(); i++) { if (delim.find(s[i]) != string::npos) { if (!t.empty()) { res.push_back(t); t = ; } } else { t += s[i]; } } if (!t.empty()) { res.push_back(t); } return res; } vector<int> splitInt(const string& s, const string& delim = ) { vector<string> tok = split(s, delim); vector<int> res; for (int i = 0; i != tok.size(); i++) res.push_back(atoi(tok[i].c_str())); return res; } template <typename T> void print(T a) { cerr << a; } static void print(long long a) { cerr << a << L ; } static void print(string a) { cerr << << a << ; } template <typename T> void print(vector<T> a) { cerr << { ; for (int i = 0; i != a.size(); i++) { if (i != 0) cerr << , ; print(a[i]); } cerr << } << endl; } int main() { int n, m; while (cin >> n >> m) { int res = 0; if (n <= 1 || m <= 1) res = m * n; if (n == 2 || m == 2) { int x = max(m, n); res = max(res, x / 4 * 4 + min((x % 4) * 2, 4)); } int x = m * n / 2; int y = m * n - x; res = max(max(res, x), y); res = min(res, m * n); cout << res << endl; } return 0; } |
Subsets and Splits