text
stringlengths 59
71.4k
|
|---|
#include <bits/stdc++.h> using namespace std; void solve(); int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); solve(); return 0; } void sd() { int n; cin >> n; n = 2 * n; vector<vector<pair<int, long long>>> adj(n + 1); vector<int> cnt(n + 1, 1); int i; for (i = 0; i < n - 1; i++) { int u, v, t; cin >> u >> v >> t; adj[u].emplace_back(v, t); adj[v].emplace_back(u, t); } vector<int> parent(n + 1, -1), topo(1, 1); vector<long long> cost(n + 1, 0); parent[1] = 1; stack<int> st; st.push(1); while (!st.empty()) { int u = st.top(); st.pop(); for (auto [v, c] : adj[u]) { if (parent[v] == -1) { parent[v] = u; cost[v] = c; topo.push_back(v); st.push(v); } } } reverse(topo.begin(), topo.end()); long long G, B; G = B = 0; for (int u : topo) { cnt[parent[u]] += cnt[u]; B += cost[u] * min(cnt[u], n - cnt[u]); G += cost[u] * (cnt[u] % 2 == 1); } cout << G << << B << endl; } void solve() { int t; cin >> t; while (t--) { sd(); } } |
#include <bits/stdc++.h> using namespace std; const int N = 100010; string s; int n; int main() { cin >> s; n = s.length(); for (int i = 1; i < n - 1; i++) { if (s[i - 1] == . || s[i] == . || s[i + 1] == . ) continue; int c1 = s[i - 1] - A + 1; int c2 = s[i] - A + 1; int c3 = s[i + 1] - A + 1; int t = 0; if (c1 != c2 && c1 != c3) t++; if (c2 != c1 && c2 != c3) t++; if (c3 != c1 && c3 != c2) t++; if (t == 3) { cout << Yes ; return 0; } } cout << No ; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAP_BEHAVIORAL_V
`define SKY130_FD_SC_LS__TAP_BEHAVIORAL_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__tap ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAP_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_PWRGOOD_PP_PG_TB_V
`define SKY130_FD_SC_LP__UDP_PWRGOOD_PP_PG_TB_V
/**
* UDP_OUT :=x when VPWR!=1 or VGND!=0
* UDP_OUT :=UDP_IN when VPWR==1 and VGND==0
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
module top();
// Inputs are registered
reg UDP_IN;
reg VPWR;
reg VGND;
// Outputs are wires
wire UDP_OUT;
initial
begin
// Initial state is x for all inputs.
UDP_IN = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 UDP_IN = 1'b0;
#40 VGND = 1'b0;
#60 VPWR = 1'b0;
#80 UDP_IN = 1'b1;
#100 VGND = 1'b1;
#120 VPWR = 1'b1;
#140 UDP_IN = 1'b0;
#160 VGND = 1'b0;
#180 VPWR = 1'b0;
#200 VPWR = 1'b1;
#220 VGND = 1'b1;
#240 UDP_IN = 1'b1;
#260 VPWR = 1'bx;
#280 VGND = 1'bx;
#300 UDP_IN = 1'bx;
end
sky130_fd_sc_lp__udp_pwrgood_pp$PG dut (.UDP_IN(UDP_IN), .VPWR(VPWR), .VGND(VGND), .UDP_OUT(UDP_OUT));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_PWRGOOD_PP_PG_TB_V
|
// (C) 2001-2019 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/19.1std/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_clock_crosser.v $
// $Revision: #1 $
// $Date: 2018/11/07 $
// $Author: psgswbuild $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_clock_crosser(
in_clk,
in_reset,
in_ready,
in_valid,
in_data,
out_clk,
out_reset,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter FORWARD_SYNC_DEPTH = 2;
parameter BACKWARD_SYNC_DEPTH = 2;
parameter USE_OUTPUT_PIPELINE = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input in_clk;
input in_reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_clk;
input out_reset;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
// Data is guaranteed valid by control signal clock crossing. Cut data
// buffer false path.
(* altera_attribute = {"-name SUPPRESS_DA_RULE_INTERNAL \"D101,D102\""} *) reg [DATA_WIDTH-1:0] in_data_buffer;
reg [DATA_WIDTH-1:0] out_data_buffer;
reg in_data_toggle;
wire in_data_toggle_returned;
wire out_data_toggle;
reg out_data_toggle_flopped;
wire take_in_data;
wire out_data_taken;
wire out_valid_internal;
wire out_ready_internal;
assign in_ready = ~(in_data_toggle_returned ^ in_data_toggle);
assign take_in_data = in_valid & in_ready;
assign out_valid_internal = out_data_toggle ^ out_data_toggle_flopped;
assign out_data_taken = out_ready_internal & out_valid_internal;
always @(posedge in_clk or posedge in_reset) begin
if (in_reset) begin
in_data_buffer <= {DATA_WIDTH{1'b0}};
in_data_toggle <= 1'b0;
end else begin
if (take_in_data) begin
in_data_toggle <= ~in_data_toggle;
in_data_buffer <= in_data;
end
end //in_reset
end //in_clk always block
always @(posedge out_clk or posedge out_reset) begin
if (out_reset) begin
out_data_toggle_flopped <= 1'b0;
out_data_buffer <= {DATA_WIDTH{1'b0}};
end else begin
out_data_buffer <= in_data_buffer;
if (out_data_taken) begin
out_data_toggle_flopped <= out_data_toggle;
end
end //end if
end //out_clk always block
altera_std_synchronizer_nocut #(.depth(FORWARD_SYNC_DEPTH)) in_to_out_synchronizer (
.clk(out_clk),
.reset_n(~out_reset),
.din(in_data_toggle),
.dout(out_data_toggle)
);
altera_std_synchronizer_nocut #(.depth(BACKWARD_SYNC_DEPTH)) out_to_in_synchronizer (
.clk(in_clk),
.reset_n(~in_reset),
.din(out_data_toggle_flopped),
.dout(in_data_toggle_returned)
);
generate if (USE_OUTPUT_PIPELINE == 1) begin
altera_avalon_st_pipeline_base
#(
.BITS_PER_SYMBOL(BITS_PER_SYMBOL),
.SYMBOLS_PER_BEAT(SYMBOLS_PER_BEAT)
) output_stage (
.clk(out_clk),
.reset(out_reset),
.in_ready(out_ready_internal),
.in_valid(out_valid_internal),
.in_data(out_data_buffer),
.out_ready(out_ready),
.out_valid(out_valid),
.out_data(out_data)
);
end else begin
assign out_valid = out_valid_internal;
assign out_ready_internal = out_ready;
assign out_data = out_data_buffer;
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A221OI_BLACKBOX_V
`define SKY130_FD_SC_HDLL__A221OI_BLACKBOX_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a221oi (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A221OI_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; map<string, int> Map; char str[2200][22]; int p[2200], q[2200]; int main() { int num, n, k1, k2, cnt; char s1[22], s2[22]; while (scanf( %d , &n) != EOF) { memset(p, 0, sizeof(p)); memset(q, 0, sizeof(q)); cnt = 1; num = 0; while (n--) { scanf( %s %s , s1, s2); if (Map[s2] > 0) continue; if ((k1 = Map[s1]) > 0) { Map[s1] = 0; strcpy(str[cnt++], s2); p[q[k1]] = cnt - 1; q[cnt - 1] = q[k1]; Map[s2] = cnt - 1; } else { strcpy(str[cnt++], s1); strcpy(str[cnt++], s2); p[cnt - 2] = cnt - 1; q[cnt - 1] = cnt - 2; Map[s2] = cnt - 1; num++; } } printf( %d n , num); int i; for (i = 0; i < cnt; i++) if (p[i]) printf( %s %s n , str[i], str[p[i]]); } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; string s; long long nb, nc, ns, push_back, pc, ps, money, cntb, cntc, cnts, l, r, mid, mb, ms, mc; int main() { ios_base::sync_with_stdio(false); cin.tie(0), cout.tie(0); cin >> s >> nb >> ns >> nc >> push_back >> ps >> pc >> money; for (size_t i = 0; i < s.length(); i++) { if (s[i] == B ) cntb++; else if (s[i] == S ) cnts++; else cntc++; } l = 0; r = 1e14; while (l <= r) { mid = (l + r) / 2; mb = max(0ll, (cntb * mid - nb) * push_back); ms = max(0ll, (cnts * mid - ns) * ps); mc = max(0ll, (cntc * mid - nc) * pc); if (mc + mb + ms <= money) l = mid + 1; else r = mid - 1; } cout << r; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxx = 600010; const double pi = acos(-1.0); const double eps = 1e-15; stack<int> h; vector<int> g[maxx]; int t, n, m; int ans = 0, total = 0, sum = 0, cnt = 0; int a[maxx], bj[maxx], vis[maxx], dfn[maxx], low[maxx]; char ch[3111]; char c[3111][3111], s[3111][3111]; void tarjan(int x, int father) { dfn[x] = low[x] = ++cnt, vis[x] = 1, h.push(x); for (int i = 0; i < g[x].size(); i++) { int to = g[x][i]; if (to == father) continue; if (!dfn[to]) { tarjan(to, x); low[x] = min(low[x], low[to]); } else if (vis[to]) low[x] = min(low[x], dfn[to]); } if (low[x] == dfn[x]) { bj[x] = ++total, vis[x] = 0; while (h.top() != x) { bj[h.top()] = total, vis[h.top()] = 0, h.pop(); } h.pop(); } } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) scanf( %c , &c[i][j]); for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) scanf( %c , &s[i][j]); for (int i = 1; i <= n; i++) scanf( %c , &ch[i]); for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) { if (c[i][j] == 0 ) { if (s[i][j] == 1 ) { if (ch[j] == 0 && ch[i] == 0 ) { ans = -1; i = n + 1; break; } if (ch[j] == 0 && ch[i] == 1 ) g[j + 3 * n].push_back(j + n); if (ch[j] == 1 && ch[i] == 0 ) g[i + 2 * n].push_back(i); if (ch[j] == 1 && ch[i] == 1 ) g[i].push_back(j + 3 * n), g[j + 3 * n].push_back(i), g[i + 2 * n].push_back(j + n), g[j + n].push_back(i + 2 * n); } else { if (ch[j] == 0 && ch[i] == 1 ) g[j + n].push_back(j + 3 * n); if (ch[j] == 1 && ch[i] == 0 ) g[i].push_back(i + 2 * n); if (ch[j] == 1 && ch[i] == 1 ) g[i].push_back(j + n), g[j + n].push_back(i), g[i + 2 * n].push_back(j + 3 * n), g[j + 3 * n].push_back(i + 2 * n); } } else { if (s[i][j] == 1 ) { if (ch[j] == 0 && ch[i] == 1 ) g[j + n].push_back(j + 3 * n); if (ch[j] == 1 && ch[i] == 0 ) g[i].push_back(i + 2 * n); if (ch[j] == 1 && ch[i] == 1 ) g[i].push_back(j + n), g[i + 2 * n].push_back(j + 3 * n), g[j + n].push_back(i), g[j + 3 * n].push_back(i + 2 * n); } else { if (ch[j] == 0 && ch[i] == 0 ) { i = n + 1; ans = -1; break; } if (ch[j] == 0 && ch[i] == 1 ) g[j + 3 * n].push_back(j + n); if (ch[j] == 1 && ch[i] == 0 ) g[i + 2 * n].push_back(i); if (ch[j] == 1 && ch[i] == 1 ) g[j + n].push_back(i + 2 * n), g[i].push_back(j + 3 * n), g[i + 2 * n].push_back(j + n), g[j + 3 * n].push_back(i); } } } if (ans) printf( %d , ans); else { for (int i = 1; i <= 4 * n; i++) if (!dfn[i]) tarjan(i, i); for (int i = 1; i <= 2 * n; i++) if (bj[i] == bj[i + 2 * n]) { ans = 1; break; } if (ans) printf( -1 ); else { for (int i = 1; i <= n; i++) if (bj[i] < bj[i + 2 * n]) ans++; for (int i = n + 1; i <= 2 * n; i++) if (bj[i] < bj[i + 2 * n]) ans++; printf( %d n , ans); for (int i = 1; i <= n; i++) if (bj[i] < bj[i + 2 * n]) printf( row %d n , i - 1); for (int i = n + 1; i <= 2 * n; i++) if (bj[i] < bj[i + 2 * n]) printf( col %d n , i - n - 1); } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1000 + 5; map<string, int> mat; int fonction(string a, string b, string c) { int x = (mat[b] - mat[a] + 12) % 12; int y = (mat[c] - mat[b] + 12) % 12; int z = (mat[c] - mat[a] + 12) % 12; if (x == 4 && y == 3 && z == 7) return 1; if (x == 3 && y == 4) return 0; return -1; } int main() { mat[ C ] = 1; mat[ C# ] = 2; mat[ D ] = 3; mat[ D# ] = 4; mat[ E ] = 5; mat[ F ] = 6; mat[ F# ] = 7; mat[ G ] = 8; mat[ G# ] = 9; mat[ A ] = 10; mat[ B ] = 11; mat[ H ] = 12; string a, b, c; cin >> a; cin >> b; cin >> c; if (fonction(a, b, c) == 1 || fonction(a, c, b) == 1 || fonction(b, a, c) == 1 || fonction(b, c, a) == 1 || fonction(c, a, b) == 1 || fonction(c, b, a) == 1) cout << major ; else if (fonction(a, b, c) == 0 || fonction(a, c, b) == 0 || fonction(b, a, c) == 0 || fonction(b, c, a) == 0 || fonction(c, a, b) == 0 || fonction(c, b, a) == 0) cout << minor ; else cout << strange ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 15; const int M = 11005; const int mo1 = 317503; const int mo2 = 1000000007; const int BAS = 2333; const int P = 3000005; int n, m, k, Hash[N], bel[N], tot, matching[M][N][2], temp_matching[N][2], bin[N]; long long ans, jc[N]; vector<int> e[N]; int ls[mo1], nx[P], key[P], tot_hash; bool vis[N], trans[N][N][N][N], f[5005][N]; void add_hash(int *Hash) { int h1 = 0, h2 = 0; for (int i = 1; i <= n; i++) { h1 = ((long long)h1 * BAS + Hash[i]) % mo1; h2 = ((long long)h2 * BAS + Hash[i]) % mo2; } for (int i = ls[h1]; i; i = nx[i]) if (key[i] == h2) return; key[++tot_hash] = h2; nx[tot_hash] = ls[h1]; ls[h1] = tot_hash; } bool find_hash(int *Hash) { int h1 = 0, h2 = 0; for (int i = 1; i <= n; i++) { h1 = ((long long)h1 * BAS + Hash[i]) % mo1; h2 = ((long long)h2 * BAS + Hash[i]) % mo2; } for (int i = ls[h1]; i; i = nx[i]) if (key[i] == h2) return 1; return 0; } void dfs_matching(int x) { if (x > n / 2) { tot++; for (int i = 1; i <= n / 2; i++) { matching[tot][i][0] = temp_matching[i][0]; matching[tot][i][1] = temp_matching[i][1]; } return; } int u; for (int i = 1; i <= n; i++) if (!vis[i]) { u = i; vis[i] = 1; break; } temp_matching[x][0] = u; for (int j = u + 1; j <= n; j++) if (!vis[j]) { temp_matching[x][1] = j; vis[j] = 1; dfs_matching(x + 1); vis[j] = 0; } vis[u] = 0; } void dfs_half_divide(int x, int y, int id) { if (x > n / 2) { for (int i = 1; i <= n / 2; i++) Hash[matching[id][i][0]] = Hash[matching[id][i][1]] = bel[i]; add_hash(Hash); return; } for (int i = 1; i <= y; i++) { bel[x] = i; dfs_half_divide(x + 1, y, id); } bel[x] = y + 1; dfs_half_divide(x + 1, y + 1, id); } void dfs_divide(int x, int y) { if (x > n) { for (int i = 1; i <= n; i++) Hash[i] = bel[i]; if (find_hash(Hash) && y <= k) ans += jc[k] / jc[k - y]; return; } for (int i = 1; i <= y; i++) { bel[x] = i; dfs_divide(x + 1, y); } bel[x] = y + 1; dfs_divide(x + 1, y + 1); } void pre_matching() { bin[0] = 1; for (int i = 1; i <= n; i++) bin[i] = bin[i - 1] * 2; for (int u = 1; u <= n; u++) for (int v = 1; v <= n; v++) for (int i : e[u]) for (int j : e[v]) trans[u][v][i][j] = 1; for (int i = 1; i <= tot; i++) { memset(f, 0, sizeof(f)); for (int j = 1; j <= n / 2; j++) f[bin[j - 1]][j] = 1; for (int j = 1; j < bin[n / 2] - 1; j++) for (int k = 1; k <= n / 2; k++) { int u = matching[i][k][0], v = matching[i][k][1]; if (f[j][k]) { for (int l = 1; l <= n / 2; l++) if (!(j & bin[l - 1])) { int p = matching[i][l][0], q = matching[i][l][1]; f[j + bin[l - 1]][l] |= trans[u][v][p][q] | trans[u][v][q][p]; } } } bool tag = 0; for (int j = 1; j <= n / 2; j++) { int u = matching[i][j][0], v = matching[i][j][1]; tag |= f[bin[n / 2] - 1][j] & trans[u][v][v][u]; } if (tag) dfs_half_divide(1, 0, i); } } int main() { scanf( %d%d%d , &n, &m, &k); for (int i = 1; i <= m; i++) { int x, y; scanf( %d%d , &x, &y); e[x].push_back(y); e[y].push_back(x); } jc[0] = 1; for (int i = 1; i <= k; i++) jc[i] = jc[i - 1] * i; dfs_matching(1); pre_matching(); dfs_divide(1, 0); printf( %lld n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; vector<int> p; long long dp1[555555]; long long dp2[555555]; long long fp(long long x) { long long ret = 1; long long mul = 2; while (x) { if (x & 1) { ret *= mul; ret %= mod; } mul *= mul; mul %= mod; x >>= 1; } return ret; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); p.push_back(2); p.push_back(3); p.push_back(5); p.push_back(7); p.push_back(11); p.push_back(13); p.push_back(17); p.push_back(19); p.push_back(23); p.push_back(29); p.push_back(31); p.push_back(37); p.push_back(41); p.push_back(43); p.push_back(47); p.push_back(53); p.push_back(59); p.push_back(61); p.push_back(67); int k = p.size(); int cnt[80] = {}; int n; cin >> n; for (int i = 0; i < n; i++) { int add; cin >> add; cnt[add]++; } dp1[0] = 1; for (int i = 1; i < 70 + 1; i++) { if (!cnt[i]) continue; int shift = 0; int rem = i; for (int j = 0; j < k; j++) { while (rem % p[j] == 0) { shift ^= (1 << j); rem /= p[j]; } } memset(dp2, 0, sizeof(dp2)); ; long long add = fp(cnt[i] - 1); for (int j = 0; j < 1 << k; j++) { dp2[j] += dp1[j] * add % mod; dp2[j] %= mod; dp2[j ^ shift] += dp1[j] * add % mod; dp2[j ^ shift] %= mod; } for (int j = 0; j < 1 << k; j++) { dp1[j] = dp2[j]; } } cout << (dp1[0] + mod - 1) % mod << endl; } |
//-----------------------------------------------------------------------------
// Pretend to be an ISO 14443 tag. We will do this by alternately short-
// circuiting and open-circuiting the antenna coil, with the tri-state
// pins.
//
// We communicate over the SSP, as a bitstream (i.e., might as well be
// unframed, though we still generate the word sync signal). The output
// (ARM -> FPGA) tells us whether to modulate or not. The input (FPGA
// -> ARM) is us using the A/D as a fancy comparator; this is with
// (software-added) hysteresis, to undo the high-pass filter.
//
// At this point only Type A is implemented. This means that we are using a
// bit rate of 106 kbit/s, or fc/128. Oversample by 4, which ought to make
// things practical for the ARM (fc/32, 423.8 kbits/s, ~50 kbytes/s)
//
// Jonathan Westhues, October 2006
//-----------------------------------------------------------------------------
module hi_simulate(
pck0, ck_1356meg, ck_1356megb,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
cross_hi, cross_lo,
dbg,
mod_type
);
input pck0, ck_1356meg, ck_1356megb;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
input cross_hi, cross_lo;
output dbg;
input [2:0] mod_type;
// Power amp goes between LOW and tri-state, so pwr_hi (and pwr_lo) can
// always be low.
assign pwr_hi = 1'b0;
assign pwr_lo = 1'b0;
// The comparator with hysteresis on the output from the peak detector.
reg after_hysteresis;
assign adc_clk = ck_1356meg;
always @(negedge adc_clk)
begin
if(& adc_d[7:5]) after_hysteresis = 1'b1;
else if(~(| adc_d[7:5])) after_hysteresis = 1'b0;
end
// Divide 13.56 MHz by 32 to produce the SSP_CLK
// The register is bigger to allow higher division factors of up to /128
reg [10:0] ssp_clk_divider;
always @(posedge adc_clk)
ssp_clk_divider <= (ssp_clk_divider + 1);
reg ssp_clk;
reg ssp_frame;
always @(negedge adc_clk)
begin
//If we're in 101, we only need a new bit every 8th carrier bit (53Hz). Otherwise, get next bit at 424Khz
if(mod_type == 3'b101)
begin
if(ssp_clk_divider[7:0] == 8'b00000000)
ssp_clk <= 1'b0;
if(ssp_clk_divider[7:0] == 8'b10000000)
ssp_clk <= 1'b1;
end
else
begin
if(ssp_clk_divider[4:0] == 5'd0)//[4:0] == 5'b00000)
ssp_clk <= 1'b1;
if(ssp_clk_divider[4:0] == 5'd16) //[4:0] == 5'b10000)
ssp_clk <= 1'b0;
end
end
//assign ssp_clk = ssp_clk_divider[4];
// Divide SSP_CLK by 8 to produce the byte framing signal; the phase of
// this is arbitrary, because it's just a bitstream.
// One nasty issue, though: I can't make it work with both rx and tx at
// once. The phase wrt ssp_clk must be changed. TODO to find out why
// that is and make a better fix.
reg [2:0] ssp_frame_divider_to_arm;
always @(posedge ssp_clk)
ssp_frame_divider_to_arm <= (ssp_frame_divider_to_arm + 1);
reg [2:0] ssp_frame_divider_from_arm;
always @(negedge ssp_clk)
ssp_frame_divider_from_arm <= (ssp_frame_divider_from_arm + 1);
always @(ssp_frame_divider_to_arm or ssp_frame_divider_from_arm or mod_type)
if(mod_type == 3'b000) // not modulating, so listening, to ARM
ssp_frame = (ssp_frame_divider_to_arm == 3'b000);
else
ssp_frame = (ssp_frame_divider_from_arm == 3'b000);
// Synchronize up the after-hysteresis signal, to produce DIN.
reg ssp_din;
always @(posedge ssp_clk)
ssp_din = after_hysteresis;
// Modulating carrier frequency is fc/16, reuse ssp_clk divider for that
reg modulating_carrier;
always @(mod_type or ssp_clk or ssp_dout)
if(mod_type == 3'b000)
modulating_carrier <= 1'b0; // no modulation
else if(mod_type == 3'b001)
modulating_carrier <= ssp_dout ^ ssp_clk_divider[3]; // XOR means BPSK
else if(mod_type == 3'b010)
modulating_carrier <= ssp_dout & ssp_clk_divider[5]; // switch 212kHz subcarrier on/off
else if(mod_type == 3'b100 || mod_type == 3'b101)
modulating_carrier <= ssp_dout & ssp_clk_divider[4]; // switch 424kHz modulation on/off
else
modulating_carrier <= 1'b0; // yet unused
// This one is all LF, so doesn't matter
assign pwr_oe2 = modulating_carrier;
// Toggle only one of these, since we are already producing much deeper
// modulation than a real tag would.
assign pwr_oe1 = modulating_carrier;
assign pwr_oe4 = modulating_carrier;
// This one is always on, so that we can watch the carrier.
assign pwr_oe3 = 1'b0;
assign dbg = modulating_carrier;
//reg dbg;
//always @(ssp_dout)
// dbg <= ssp_dout;
endmodule
|
#include <bits/stdc++.h> using namespace std; unsigned long long l, r, x, y; unsigned long long gcd(unsigned long long a, unsigned long long b) { while (b > 0) { unsigned long long t = b; b = a % b; a = t; } return a; } int main() { cin >> l >> r >> x >> y; if (x == y) { if (x >= l && x <= r) { cout << 1; return 0; } } unsigned long long number = 0; l = 1 + ((l - 1) / x); l *= x; for (unsigned long long i = l; i * i <= x * y; i += x) { unsigned long long p = x * y / i; if (p * i == x * y && p >= l && p <= r && i <= r) { if (gcd(p, i) == x) { number += 2; if (i == p) number--; } } } cout << number; } |
#include <bits/stdc++.h> using namespace std; int n, a[200001], b[200001], m; int main() { cin >> n >> m; n = n + m; for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); } vector<int> vec; for (int i = 1; i <= n; i++) { scanf( %d , &b[i]); if (b[i] == 1) { vec.push_back(a[i]); } } vec.push_back(2e9 + 1); int l = 0, cnt = 0, r = 1, c = 0; while (l < vec.size() - 1 && r <= n) { if (b[r] == 0) { while (abs(a[r] - vec[l]) > abs(a[r] - vec[l + 1])) { cout << cnt << ; c++; l++; cnt = 0; } cnt++; } r++; } cout << cnt << ; for (int i = 0; i < vec.size() - 2 - c; i++) { cout << 0 ; } return 0; } |
#include <bits/stdc++.h> const int LG = 21; const int N = 1000005; const long long MOD = 1e9 + 7; const long long INF = 1e9; const long long INFLL = 1e18; using namespace std; int cx[4] = {-1, 0, 1, 0}; int cy[4] = {0, -1, 0, 1}; string Yes[2] = { No , Yes }; string YES[2] = { NO , YES }; long long inq(long long x, long long y) { if (!y) return 1 % MOD; long long l = inq(x, y / 2); if (y % 2) return l * l % MOD * x % MOD; return l * l % MOD; } long long rev(long long x) { return inq(x, MOD - 2); } bool __precomputed_combinatorics = 0; vector<long long> __fact, __ufact, __rev; void __precompute_combinatorics() { __precomputed_combinatorics = 1; __fact.resize(N); __ufact.resize(N); __rev.resize(N); __rev[1] = 1; for (int i = 2; i < N; i++) __rev[i] = MOD - __rev[MOD % i] * (MOD / i) % MOD; __fact[0] = 1, __ufact[0] = 1; for (int i = 1; i < N; i++) __fact[i] = __fact[i - 1] * i % MOD, __ufact[i] = __ufact[i - 1] * __rev[i] % MOD; } long long fact(int x) { if (!__precomputed_combinatorics) __precompute_combinatorics(); return __fact[x]; } long long cnk(int n, int k) { if (k < 0 || k > n) return 0; if (!__precomputed_combinatorics) __precompute_combinatorics(); return __fact[n] * __ufact[n - k] % MOD * __ufact[k] % MOD; } int Root(int x, vector<int> &root) { if (x == root[x]) return x; return root[x] = Root(root[x], root); } void Merge(int v, int u, vector<int> &root, vector<int> &sz) { v = Root(v, root), u = Root(u, root); if (v == u) return; if (sz[v] < sz[u]) { sz[u] += sz[v]; root[v] = u; } else { sz[v] += sz[u]; root[u] = v; } } int ok(int x, int n) { return 0 <= x && x < n; } void bfs(int v, vector<int> &dist, vector<vector<int> > &graph) { fill((dist).begin(), (dist).end(), -1); dist[v] = 0; vector<int> q = {v}; for (int i = 0; i < q.size(); i++) { for (auto u : graph[q[i]]) { if (dist[u] == -1) { dist[u] = dist[q[i]] + 1; q.push_back(u); } } } } vector<int> z_func(string &s) { vector<int> z(s.size()); z[0] = s.size(); int L = 0, R = 0; for (int i = 1; i < s.size(); i++) { z[i] = max(0, min(z[i - L], R - i)); while (i + z[i] < s.size() && s[i + z[i]] == s[z[i]]) z[i]++; if (i + z[i] > R) { R = i + z[i]; L = i; } } return z; } vector<int> p_func(string &s) { vector<int> p(s.size()); for (int i = 1; i < s.size(); i++) { int j = p[i - 1]; while (j > 0 && s[i] != s[j]) j = p[j - 1]; if (s[i] == s[j]) j++; p[i] = j; } return p; } vector<int> d1_func(string &s) { vector<int> d1(s.size()); int L = 0, R = -1; for (int i = 0; i < s.size(); i++) { int k = 0; if (i <= R) k = min(R - i + 1, d1[R - i + L]); while (i + k < s.size() && i - k >= 0 && s[i - k] == s[i + k]) k++; d1[i] = k--; if (i + k > R) { L = i - k; R = i + k; } } return d1; } vector<int> d2_func(string &s) { vector<int> d2(s.size()); int L = 0, R = -1; for (int i = 1; i < s.size(); i++) { int k = 0; if (i <= R) k = min(R - i + 1, d2[R - i + L + 1]); while (i + k < s.size() && i - k - 1 >= 0 && s[i - k - 1] == s[i + k]) k++; d2[i] = k--; if (i + k > R) { L = i - k - 1; R = i + k; } } return d2; } long long log10(long long x) { if (x < 10) return 1; return 1 + log10(x / 10); } long long ds(long long x) { if (x < 10) return x; return x % 10 + ds(x / 10); } double sqr(double x) { return x * x; } bool in(int bit, int mask) { return (mask & (1 << bit)) > 0; } void Del(vector<int> &v, int pos) { swap(v[pos], v[v.size() - 1]); v.pop_back(); } long long g(vector<long long> &p, int pos) { if (ok(pos, p.size())) return p[pos]; if (pos < 0 || p.size() == 0) return 0; return p.back(); } int g(vector<int> &p, int pos) { if (ok(pos, p.size())) return p[pos]; if (pos < 0 || p.size() == 0) return 0; return p.back(); } bool comp(pair<int, int> a, pair<int, int> b) { if (abs(a.first - a.second) == abs(b.first - b.second)) return a > b; return abs(a.first - a.second) > abs(b.first - b.second); } signed main() { srand(time(NULL)); ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, k; cin >> n >> k; int s = max(1, k / 2); vector<int> a(n, 1); for (int i = 0; i < n; i++) { int k = 1; int x = i; while (0 <= x && x < n / s) { for (int j = x * s; j < x * s + s; j++) { if (a[j]) { cout << ? << j + 1 << endl; string s; cin >> s; if (s == Y ) { a[j] = 0; } } } if (k % 2 == 1) x += k; else x -= k; k++; } cout << R << endl; } cout << ! << accumulate((a).begin(), (a).end(), 0) << endl; } |
#include <bits/stdc++.h> using namespace std; const int MX = 200200, MSK = (1 << 20) - 1; int T, n, m, i, x, y, z, pos, cnt, le, ri, h, fi[MX], lst[MX], s[MX], t[MX], ch[MX], a[18][MX], npw[MX], L[MX], R[MX], A[MX]; priority_queue<long long, vector<long long>, greater<long long>> q; long long seg[MX * 88], d[MX], sf, j; vector<int> g[MX], f[MX]; void dfs(int i, long long dep) { a[0][++T] = i; fi[i] = T; d[i] = dep; for (int j = 0; j < g[i].size(); j++) { dfs(g[i][j], dep + f[i][j]); a[0][++T] = i; } lst[i] = T; } int lca(int i, int j) { if (i > j) return lca(j, i); int len = npw[j - i + 1]; int le = a[len][i]; int ri = a[len][j - (1 << len) + 1]; if (d[le] <= d[ri]) return le; return ri; } int fndmax(int l, int r) { int res = max(A[l], A[r]), x, nxt; for (x = l;; x = nxt) { nxt = (x << 1) - (x & (x - 1)); if (nxt > r) break; res = max(res, L[x]); } res = max(res, A[x]); for (x = r;; x = nxt) { nxt = (x & (x - 1)); if (nxt < l) break; res = max(res, R[x]); } res = max(res, A[x]); return res; } void mdf(int i, int v) { A[i] = max(A[i], v); for (int x = i; x <= T; x = (x << 1) - (x & (x - 1))) R[x] = max(R[x], v); for (int x = i; x > 0; x &= x - 1) L[x] = max(L[x], v); } void printans(int i) { for (cnt = x = 0; x < i; x++) { y = (seg[x] >> 20) & MSK; if (t[seg[x] & MSK] + d[y] < q.top()) ++cnt; } printf( %I64d %d n , q.top(), cnt); } bool cmp(long long x, long long y) { if ((y >> 40) == 0) return false; if ((x >> 40) == 0) return true; return t[x >> 40] + d[(x >> 20) & MSK] < t[y >> 40] + d[(y >> 20) & MSK]; } int main() { scanf( %d%d , &n, &m); for (i = 1; i < n; i++) { scanf( %d%d%d , &x, &y, &z); g[x].push_back(y); f[x].push_back(z); } for (i = 1; i <= n; i++) ch[i] = int(g[i].size()) - 1; dfs(1, 0); for (x = 1; x < 18; x++) for (i = 1; i <= T; i++) { a[x][i] = a[x - 1][i]; y = i + (1 << (x - 1)); if (y <= T && d[a[x - 1][y]] < d[a[x][i]]) a[x][i] = a[x - 1][y]; } for (x = 1, y = -1, i = 1; i <= T; i++) { if (i == x) { x *= 2; y++; } npw[i] = y; } for (i = 1; i <= m; i++) { scanf( %d%d , &s[i], &t[i]); pos = fi[s[i]]; for (j = 1; j != s[i]; j = y) { z = fndmax(fi[j] + 1, lst[j]); if (z != 0) { j = lca(fi[s[z]], pos); if (j == s[i]) break; } y = g[j][ch[j]]; z = fndmax(fi[y], lst[y]); if (pos < fi[y] || pos > lst[y]) { le = 0; ri = int(g[j].size()) - 1; while (le < ri) { h = (le + ri) / 2; if (lst[g[j][h]] < pos) le = h + 1; else ri = h; } seg[cnt++] = ((((1LL * z) << 20) ^ j) << 20) ^ i; y = g[j][ch[j] = ri]; } } mdf(pos, i); } sort(seg, seg + cnt, cmp); for (j = i = 0; i < cnt; i++) { z = (seg[i] >> 40); y = (seg[i] >> 20) & MSK; sf = z ? t[z] + d[y] + 1 : 1; for (; j < sf && !q.empty(); j++) { if (q.top() < j) { printans(i); return 0; } q.pop(); } j = sf; q.push(t[seg[i] & MSK] + d[y]); } while (!q.empty()) { if (q.top() < j) { printans(cnt); return 0; } q.pop(); j++; } printf( -1 %d n , cnt); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { string str; cin >> str; int n = str.size(); int fl = 1; vector<char> v; for (int i = 0; i < str.size(); i++) { if (str[i] == / ) { while (str[i] == / ) { i++; } i--; v.push_back( / ); } else { v.push_back(str[i]); } } for (int i = 0; i < v.size(); i++) { if (v[i] != / ) { fl = 0; break; } } if (fl == 1) { cout << / << endl; } else { int t = v.size(); for (int i = 0; i < t; i++) { if (i == t - 1 && v[i] == / ) { continue; } else { cout << v[i]; } } } return 0; } |
#include <bits/stdc++.h> using namespace std; long n, m, a, b, ar[200][200], ans; long arp[10000], fl, l; void dfs(long v, long par) { arp[v] = 1; l++; for (int i = 1; i <= n; i++) if (ar[v][i] == 1) { if (i == par) continue; if (arp[i] == 1) { fl = 1; return; } dfs(i, v); } } int main() { ios_base::sync_with_stdio(0); cin >> n >> m; for (int i = 1; i <= m; i++) { cin >> a >> b; ar[a][b] = ar[b][a] = 1; } for (int i = 1; i <= n; i++) if (arp[i] == 0) { fl = 0; l = 0; dfs(i, -1); if (fl) if (l % 2) ++ans; } n -= ans; if (n % 2) ++ans; cout << ans << endl; cin.get(); cin.get(); return 0; } |
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ninja2.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ninja2 (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "./sprites/ninja2.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./sprites/ninja2.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./sprites/ninja2.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja2.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja2.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja2.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja2.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja2_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja2_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
//Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module jaxa_statisticalInformation_0 (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 31: 0] in_port;
input reset_n;
wire clk_en;
wire [ 31: 0] data_in;
wire [ 31: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {32 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 2e9; FILE* stream; mt19937 rng(1337); void solve() { int n; cin >> n; vector<int> a(n); for (int i = 0; i < int(n); i++) { cin >> a[i]; } vector<int> b(n); for (int i = 0; i < int(n); i++) { if (i % 2) { b[i] = a[i - 1]; } else { b[i] = -a[i + 1]; } } for (int i = 0; i < int(n); i++) cout << b[i] << ; cout << endl; return; } signed main() { int t; cin >> t; while (t--) solve(); return 0; } |
////////////////////////////////////////////////////////////////////////////////
//
// Filename: pipemem.v
//
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
//
// Purpose: A memory unit to support a CPU, this time one supporting
// pipelined wishbone memory accesses. The goal is to be able
// to issue one pipelined wishbone access per clock, and (given the memory
// is fast enough) to be able to read the results back at one access per
// clock. This renders on-chip memory fast enough to handle single cycle
// (pipelined) access.
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2017, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
`default_nettype none
//
module pipemem(i_clk, i_rst, i_pipe_stb, i_lock,
i_op, i_addr, i_data, i_oreg,
o_busy, o_pipe_stalled, o_valid, o_err, o_wreg, o_result,
o_wb_cyc_gbl, o_wb_cyc_lcl,
o_wb_stb_gbl, o_wb_stb_lcl,
o_wb_we, o_wb_addr, o_wb_data, o_wb_sel,
i_wb_ack, i_wb_stall, i_wb_err, i_wb_data);
parameter ADDRESS_WIDTH=30;
parameter [0:0] IMPLEMENT_LOCK=1'b0,
WITH_LOCAL_BUS=1'b1;
localparam AW=ADDRESS_WIDTH;
input wire i_clk, i_rst;
input wire i_pipe_stb, i_lock;
// CPU interface
input wire [2:0] i_op;
input wire [31:0] i_addr;
input wire [31:0] i_data;
input wire [4:0] i_oreg;
// CPU outputs
output wire o_busy;
output wire o_pipe_stalled;
output reg o_valid;
output reg o_err;
output reg [4:0] o_wreg;
output reg [31:0] o_result;
// Wishbone outputs
output wire o_wb_cyc_gbl;
output reg o_wb_stb_gbl;
output wire o_wb_cyc_lcl;
output reg o_wb_stb_lcl, o_wb_we;
output reg [(AW-1):0] o_wb_addr;
output reg [31:0] o_wb_data;
output reg [3:0] o_wb_sel;
// Wishbone inputs
input wire i_wb_ack, i_wb_stall, i_wb_err;
input wire [31:0] i_wb_data;
reg cyc;
reg r_wb_cyc_gbl, r_wb_cyc_lcl;
reg [3:0] rdaddr, wraddr;
wire [3:0] nxt_rdaddr;
reg [(4+5-1):0] fifo_oreg [0:15];
initial rdaddr = 0;
initial wraddr = 0;
always @(posedge i_clk)
fifo_oreg[wraddr] <= { i_oreg, i_op[2:1], i_addr[1:0] };
always @(posedge i_clk)
if ((i_rst)||(i_wb_err))
wraddr <= 0;
else if (i_pipe_stb)
wraddr <= wraddr + 1'b1;
always @(posedge i_clk)
if ((i_rst)||(i_wb_err))
rdaddr <= 0;
else if ((i_wb_ack)&&(cyc))
rdaddr <= rdaddr + 1'b1;
assign nxt_rdaddr = rdaddr + 1'b1;
wire gbl_stb, lcl_stb;
assign lcl_stb = (i_addr[31:24]==8'hff)&&(WITH_LOCAL_BUS);
assign gbl_stb = (!lcl_stb)||(!WITH_LOCAL_BUS);
//= ((i_addr[31:8]!=24'hc00000)||(i_addr[7:5]!=3'h0));
initial cyc = 0;
initial r_wb_cyc_lcl = 0;
initial r_wb_cyc_gbl = 0;
always @(posedge i_clk)
if (i_rst)
begin
r_wb_cyc_gbl <= 1'b0;
r_wb_cyc_lcl <= 1'b0;
o_wb_stb_gbl <= 1'b0;
o_wb_stb_lcl <= 1'b0;
cyc <= 1'b0;
end else if (cyc)
begin
if ((~i_wb_stall)&&(~i_pipe_stb))
begin
o_wb_stb_gbl <= 1'b0;
o_wb_stb_lcl <= 1'b0;
// end else if ((i_pipe_stb)&&(~i_wb_stall))
// begin
// o_wb_addr <= i_addr[(AW-1):0];
// o_wb_data <= i_data;
end
if (((i_wb_ack)&&(nxt_rdaddr == wraddr))||(i_wb_err))
begin
r_wb_cyc_gbl <= 1'b0;
r_wb_cyc_lcl <= 1'b0;
cyc <= 1'b0;
end
end else if (i_pipe_stb) // New memory operation
begin // Grab the wishbone
r_wb_cyc_lcl <= lcl_stb;
r_wb_cyc_gbl <= gbl_stb;
o_wb_stb_lcl <= lcl_stb;
o_wb_stb_gbl <= gbl_stb;
cyc <= 1'b1;
// o_wb_addr <= i_addr[(AW-1):0];
// o_wb_data <= i_data;
// o_wb_we <= i_op
end
always @(posedge i_clk)
if ((!cyc)||(!i_wb_stall))
begin
o_wb_addr <= i_addr[(AW+1):2];
if (!i_op[0]) // Always select everything on reads
o_wb_sel <= 4'b1111; // Op is even
else casez({ i_op[2:1], i_addr[1:0] })
4'b100?: o_wb_sel <= 4'b1100; // Op = 5
4'b101?: o_wb_sel <= 4'b0011; // Op = 5
4'b1100: o_wb_sel <= 4'b1000; // Op = 5
4'b1101: o_wb_sel <= 4'b0100; // Op = 7
4'b1110: o_wb_sel <= 4'b0010; // Op = 7
4'b1111: o_wb_sel <= 4'b0001; // Op = 7
default: o_wb_sel <= 4'b1111; // Op = 7
endcase
casez({ i_op[2:1], i_addr[1:0] })
4'b100?: o_wb_data <= { i_data[15:0], 16'h00 };
4'b101?: o_wb_data <= { 16'h00, i_data[15:0] };
4'b1100: o_wb_data <= { i_data[7:0], 24'h00 };
4'b1101: o_wb_data <= { 8'h00, i_data[7:0], 16'h00 };
4'b1110: o_wb_data <= { 16'h00, i_data[7:0], 8'h00 };
4'b1111: o_wb_data <= { 24'h00, i_data[7:0] };
default: o_wb_data <= i_data;
endcase
end
always @(posedge i_clk)
if ((i_pipe_stb)&&(~cyc))
o_wb_we <= i_op[0];
initial o_valid = 1'b0;
always @(posedge i_clk)
o_valid <= (cyc)&&(i_wb_ack)&&(~o_wb_we);
initial o_err = 1'b0;
always @(posedge i_clk)
o_err <= (cyc)&&(i_wb_err);
assign o_busy = cyc;
wire [8:0] w_wreg;
assign w_wreg = fifo_oreg[rdaddr];
always @(posedge i_clk)
o_wreg <= w_wreg[8:4];
always @(posedge i_clk)
casez(w_wreg[3:0])
4'b1100: o_result <= { 24'h00, i_wb_data[31:24] };
4'b1101: o_result <= { 24'h00, i_wb_data[23:16] };
4'b1110: o_result <= { 24'h00, i_wb_data[15: 8] };
4'b1111: o_result <= { 24'h00, i_wb_data[ 7: 0] };
4'b100?: o_result <= { 16'h00, i_wb_data[31:16] };
4'b101?: o_result <= { 16'h00, i_wb_data[15: 0] };
default: o_result <= i_wb_data[31:0];
endcase
assign o_pipe_stalled = (cyc)
&&((i_wb_stall)||((~o_wb_stb_lcl)&&(~o_wb_stb_gbl)));
generate
if (IMPLEMENT_LOCK != 0)
begin
reg lock_gbl, lock_lcl;
initial lock_gbl = 1'b0;
initial lock_lcl = 1'b0;
always @(posedge i_clk)
begin
lock_gbl <= (i_lock)&&((r_wb_cyc_gbl)||(lock_gbl));
lock_lcl <= (i_lock)&&((r_wb_cyc_lcl)||(lock_lcl));
end
assign o_wb_cyc_gbl = (r_wb_cyc_gbl)||(lock_gbl);
assign o_wb_cyc_lcl = (r_wb_cyc_lcl)||(lock_lcl);
end else begin
assign o_wb_cyc_gbl = (r_wb_cyc_gbl);
assign o_wb_cyc_lcl = (r_wb_cyc_lcl);
end endgenerate
// Make verilator happy
// verilator lint_off UNUSED
wire unused;
assign unused = i_lock;
// verilator lint_on UNUSED
endmodule
|
//Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module cpu_0_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
)
;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input test_ending;
input test_has_ended;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long i, i1, j, k, k1, t, n, m, res, flag[10], a, b, mt[110][110], s; char c; vector<array<long long, 6>> sl; vector<array<long long, 3>> cl; void mv(long long a, long long b, long long c, long long d, long long e, long long f) { sl.push_back({a, b, c, d, e, f}); mt[a][b] ^= 1; mt[c][d] ^= 1; mt[e][f] ^= 1; } void cl4(vector<long long> st) { long long i, l, x, s = 0; for (i = 1; i <= 4; i++) s += st[i]; if (s == 0) return; if (s == 3) { l = 0; cl.push_back({0, 0, 0}); x = cl.size(); x--; for (i = 1; i <= 4; i++) { if (st[i] == 1) { st[i] ^= 1; cl[x][l] = i; l++; } } } if (s == 2) { flag[1] = 0; l = 0; cl.push_back({0, 0, 0}); x = cl.size(); x--; for (i = 1; i <= 4; i++) { if (st[i] == 0 || (st[i] == 1 && flag[1] == 0)) { st[i] ^= 1; cl[x][l] = i; l++; if (st[i] == 0) flag[1] = 1; } } cl4(st); } if (s == 1) { flag[0] = 0; l = 0; cl.push_back({0, 0, 0}); x = cl.size(); x--; for (i = 1; i <= 4; i++) { if (st[i] == 1 || (st[i] == 0 && flag[0] < 2)) { st[i] ^= 1; cl[x][l] = i; l++; if (st[i] == 1) flag[0]++; } } cl4(st); } if (s == 4) { flag[1] = 0; l = 0; cl.push_back({0, 0, 0}); x = cl.size(); x--; for (i = 1; i <= 4; i++) { if (st[i] == 0 || (st[i] == 1 && flag[1] < 3)) { st[i] ^= 1; cl[x][l] = i; l++; if (st[i] == 0) flag[1]++; } } cl4(st); } } void init(vector<long long> st) { cl.clear(); cl4(st); } int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> t; while (t--) { cin >> n >> m; sl.clear(); for (i = 1; i <= n; i++) { for (j = 1; j <= m; j++) { cin >> c; if (c == 0 ) mt[i][j] = 0; else mt[i][j] = 1; } } for (i = 1; i <= n - 2; i++) { for (j = 1; j <= m - 1; j++) { if (mt[i][j] == 1 && mt[i][j + 1] == 1) { mv(i, j, i, j + 1, i + 1, j); } else if (mt[i][j] == 1 && mt[i][j + 1] == 0) { mv(i, j, i + 1, j, i + 1, j + 1); } else if (mt[i][j] == 0 && mt[i][j + 1] == 1) { mv(i, j + 1, i + 1, j, i + 1, j + 1); } } } if (m % 2) { if (mt[n - 1][m] == 1 && mt[n][m] == 1) { mv(n - 1, m, n, m - 1, n, m); } else if (mt[n - 1][m] == 1 && mt[n][m] == 0) { mv(n - 1, m - 1, n - 1, m, n, m - 1); } else if (mt[n - 1][m] == 0 && mt[n][m] == 1) { mv(n - 1, m - 1, n, m - 1, n, m); } } for (j = 1; j <= m - 1; j += 2) { vector<long long> st; vector<array<long long, 2>> fn; st.push_back(0); st.push_back(mt[n - 1][j]); st.push_back(mt[n - 1][j + 1]); st.push_back(mt[n][j]); st.push_back(mt[n][j + 1]); init(st); for (auto u : cl) { fn.clear(); for (i = 0; i < 3; i++) { if (u[i] == 1) fn.push_back({n - 1, j}); else if (u[i] == 2) fn.push_back({n - 1, j + 1}); else if (u[i] == 3) fn.push_back({n, j}); else if (u[i] == 4) fn.push_back({n, j + 1}); } sl.push_back({0, 0, 0, 0, 0, 0}); for (i = 0; i < 3; i++) { s = sl.size(); s--; sl[s][2 * i] = fn[i][0]; sl[s][2 * i + 1] = fn[i][1]; } } } s = sl.size(); cout << s << n ; for (auto u : sl) { for (i = 0; i < 6; i++) cout << u[i] << ; cout << n ; } } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EINVN_BEHAVIORAL_V
`define SKY130_FD_SC_HS__EINVN_BEHAVIORAL_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__einvn (
A ,
TE_B,
Z ,
VPWR,
VGND
);
// Module ports
input A ;
input TE_B;
output Z ;
input VPWR;
input VGND;
// Local signals
wire u_vpwr_vgnd0_out_A ;
wire u_vpwr_vgnd1_out_teb;
// Name Output Other arguments
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_A , A, VPWR, VGND );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd1 (u_vpwr_vgnd1_out_teb, TE_B, VPWR, VGND );
notif0 notif00 (Z , u_vpwr_vgnd0_out_A, u_vpwr_vgnd1_out_teb);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__EINVN_BEHAVIORAL_V |
// Double pumped single precision floating point multiply
// Latency = 7 kernel clocks
//
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_mul_dbl_pumped
#(
// Bit width of a single precision float
parameter WIDTH=32
)
(
input clock,
input clock2x,
input enable,
input [WIDTH-1:0] a1,
input [WIDTH-1:0] b1,
input [WIDTH-1:0] a2,
input [WIDTH-1:0] b2,
output reg [WIDTH-1:0] y1,
output reg [WIDTH-1:0] y2
);
reg [WIDTH-1:0] a1_reg;
reg [WIDTH-1:0] b1_reg;
reg [WIDTH-1:0] a2_reg;
reg [WIDTH-1:0] b2_reg;
// Prevent sharing of these registers across different instances
// (and even kernels!). The sharing may cause very long paths
// across the chip, which limits fmax of clock2x.
reg sel2x /* synthesis preserve */;
wire [WIDTH-1:0] fp_mul_inp_a;
wire [WIDTH-1:0] fp_mul_inp_b;
wire [WIDTH-1:0] fp_mul_res;
initial
begin
sel2x <= 1'b0;
end
always@(posedge clock2x)
if (enable)
sel2x<=~sel2x;
//Register before double pumping
reg selector, selector_2x;
always@(posedge clock)
begin
if (enable)
begin
a1_reg <= a1;
a2_reg <= a2;
b1_reg <= b1;
b2_reg <= b2;
selector <= sel2x;
end
end
reg [WIDTH-1:0] a1_reg_2x;
reg [WIDTH-1:0] a2_reg_2x;
reg [WIDTH-1:0] b1_reg_2x;
reg [WIDTH-1:0] b2_reg_2x;
// Clock domain transfer
always@(posedge clock2x)
if (enable)
begin
a1_reg_2x <= a1_reg;
a2_reg_2x <= a2_reg;
b1_reg_2x <= b1_reg;
b2_reg_2x <= b2_reg;
selector_2x <= selector;
end
assign fp_mul_inp_a = (sel2x) ? a2_reg_2x : a1_reg_2x;
assign fp_mul_inp_b = (sel2x) ? b2_reg_2x : b1_reg_2x;
generate
if (WIDTH == 32)
acl_fp_mul_fast the_mul(.clk_en(enable), .clock(clock2x), .dataa(fp_mul_inp_a), .datab(fp_mul_inp_b), .result(fp_mul_res));
else // WIDTH == 64
acl_fp_mul_fast_double the_mul(.clk_en(enable), .clock(clock2x), .dataa(fp_mul_inp_a), .datab(fp_mul_inp_b), .result(fp_mul_res));
endgenerate
reg [WIDTH-1:0] res1;
reg [WIDTH-1:0] res2;
reg [WIDTH-1:0] temp;
always@(posedge clock2x)
begin
if (enable)
begin
if (~sel2x == selector_2x)
begin
res1 <= (~selector_2x) ? temp : fp_mul_res;
res2 <= (~selector_2x) ? fp_mul_res : temp;
end
temp <= fp_mul_res;
end
end
always@(posedge clock)
begin
if (enable)
begin
y1 <= res1;
y2 <= res2;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFRBP_SYMBOL_V
`define SKY130_FD_SC_HD__SDFRBP_SYMBOL_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__sdfrbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFRBP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const long long N = 100010, M = 100010, inf = 1e18; long long m, n, p, d[N], a[M], f[M], sum[M], g[M], x[M], y[M]; inline long long read() { char ch = getchar(); long long as = 0, f = 1; for (; ch < 0 || ch > 9 ; ch = getchar()) if (ch == - ) f = -1; for (; ch >= 0 && ch <= 9 ; ch = getchar()) as = as * 10 + ch - 0 ; return as; } long long q[M << 1], l, r; long long as = inf; int main() { long long h, t; n = read(); m = read(); p = read(); for (long long i = 1; i < n; i++) d[i] = read(); for (long long i = n - 2; i; i--) d[i] += d[i + 1]; for (long long i = 1; i <= m; i++) { h = read(); t = read(); a[i] = t + d[h]; } sort(a + 1, a + m + 1); for (long long i = 1; i <= m; i++) sum[i] = sum[i - 1] + a[i], f[i] = inf; for (long long i = 1; i <= p; i++) { memcpy(g, f, sizeof(g)); l = M; r = M; for (long long j = 0; j <= m; j++) y[j] = g[j] + sum[j]; q[r] = 0; for (long long j = 1; j <= m; j++) { while (r > l) if ((y[q[l + 1]] - y[q[l]]) <= a[j] * (q[l + 1] - q[l])) l++; else break; f[j] = min(g[j], -a[j] * q[l] + y[q[l]] + a[j] * j - sum[j]); while (r > l) if ((y[q[r]] - y[q[r - 1]]) * (j - q[r]) >= (y[j] - y[q[r]]) * (q[r] - q[r - 1])) r--; else break; r++; q[r] = j; } as = min(as, f[m]); } printf( %lld , as); return 0; } |
#include <bits/stdc++.h> using namespace std; int nxt[500005], to[500005], head[500005], fa[500005], f[500005][22], dep[500005], ru[500005], tot; bool vis[500005], used[500005]; queue<int> q; vector<int> ei[500005]; void add(int u, int v) { nxt[++tot] = head[u]; head[u] = tot; to[tot] = v; nxt[++tot] = head[v]; head[v] = tot; to[tot] = u; } void dfs(int u, int p) { dep[u] = dep[p] + 1; f[u][0] = p; for (int i = 1; i <= 20; i++) f[u][i] = f[f[u][i - 1]][i - 1]; for (int e = head[u]; e; e = nxt[e]) { int v = to[e]; if (v == p) continue; dfs(v, u); } } int lca(int x, int y) { if (dep[x] < dep[y]) swap(x, y); for (int i = 20; i >= 0; i--) { if (dep[f[x][i]] >= dep[y]) { x = f[x][i]; } } if (x == y) return x; for (int i = 20; i >= 0; i--) { if (f[x][i] != f[y][i]) { x = f[x][i]; y = f[y][i]; } } return f[x][0]; } int find(int x) { if (x == fa[x]) return x; return fa[x] = find(fa[x]); } struct sad { int x, y; } a[500005]; int main() { int n, x, y, u, v; cin >> n; for (int i = 1; i <= n; i++) fa[i] = i; for (int i = 1; i <= n - 1; i++) { scanf( %d%d , &x, &y); add(x, y); } for (int i = 1; i <= n - 1; i++) { scanf( %d%d , &a[i].x, &a[i].y); ru[a[i].x]++; ru[a[i].y]++; ei[a[i].x].push_back(i); ei[a[i].y].push_back(i); } dfs(1, 0); for (int i = 1; i <= n - 1; i++) { if (ru[a[i].x] == 1 || ru[a[i].y] == 1) { used[i] = 1; q.push(i); } } int ans = 0; cout << n - 1 << endl; while (!q.empty()) { int eg = q.front(); q.pop(); u = a[eg].x; v = a[eg].y; if (ru[u] != 1) swap(u, v); int z = lca(u, v); int p = find(u); if (dep[p] > dep[z]) { ans++; fa[p] = find(f[p][0]); printf( %d %d %d %d n , p, f[p][0], a[eg].x, a[eg].y); } else { int t = v; for (int i = 20; i >= 0; i--) if (dep[f[t][i]] > dep[z] && find(f[t][i]) != p) t = f[t][i]; fa[t] = find(f[t][0]); printf( %d %d %d %d n , t, f[t][0], a[eg].x, a[eg].y); } ru[u]--; ru[v]--; if (ru[v] == 1) { int mm = ei[v].size(); for (int i = 0; i < mm; i++) { int ey = ei[v][i]; if (used[ey] == 0) q.push(ey), used[ey] = 1; } } } return 0; } |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2018 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2018.3
// \ \ Description : Xilinx Unified Simulation Library Component
// / / General Clock Buffer
// /___/ /\ Filename : BUFG.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 03/23/04 - Initial version.
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
// 12/13/11 - 524859 - Added `celldefine and `endcelldefine
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module BUFG
`ifdef XIL_TIMING
#(
parameter LOC = "UNPLACED"
)
`endif
(
output O,
input I
);
// define constants
localparam MODULE_NAME = "BUFG";
`ifdef XIL_TIMING
reg notifier;
`endif
// begin behavioral model
buf B1 (O, I);
// end behavioral model
`ifndef XIL_XECLIB
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
$period (negedge I, 0:0:0, notifier);
$period (posedge I, 0:0:0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
`endif
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; constexpr int maxn = 2e5 + 10, N = 260, M = 5e6 + 10; constexpr int MAX_INF = 0x3f3f3f3f; int mp[maxn]; int main() { int T; cin >> T; while (T--) { int n, m; scanf( %d%d , &n, &m); int root = 0; memset(mp, 0, sizeof(mp)); while (m--) { int a, b, c; scanf( %d%d%d , &a, &b, &c); mp[b] = 1; } for (int i = 1; i <= n; i++) { if (!mp[i]) { root = i; break; } } for (int i = 1; i <= n; i++) { if (i == root) continue; printf( %d %d n , i, root); } } } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Fri Jan 13 17:35:24 2017
// Host : KLight-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/win_1/win_stub.v
// Design : win
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
module win(clka, wea, addra, dina, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,wea[0:0],addra[13:0],dina[11:0],douta[11:0]" */;
input clka;
input [0:0]wea;
input [13:0]addra;
input [11:0]dina;
output [11:0]douta;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int M = 23e4 + 5; int sum[M], n, fen[M]; int Get(int p) { int u = p; int ans = 0; for (; p > 0; p -= p & -p) ans += fen[p]; for (u++; u < M; u += u & -u) fen[u]++; return ans; } int get(int p) { int cur = 0; for (int i = 17; ~i; i--) { int d = cur + (1 << i); if (fen[d] <= p) p -= fen[d], cur = d; } int u = cur; for (u++; u < M; u += u & -u) fen[u]--; return cur; } int32_t main() { scanf( %d , &n); int t = 2; while (t--) { memset(fen, 0, sizeof fen); for (int i = 0; i < n; i++) { int x; scanf( %d , &x); sum[i] += x - Get(x); } } int sb = 0; for (int i = n - 1; ~i; i--) { sum[i] += sb; int k = sum[i] % (n - i); sb = (sum[i] - k) / (n - i); sum[i] = k; } for (int i = 1; i < M; i++) fen[i] = i & -i; for (int i = 0; i < n; i++) printf( %d , get(sum[i])); return printf( n ), 0; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:41:46 03/26/2015
// Design Name: multiplier
// Module Name: /home/vka/Programming/VHDL/workspace/sysrek/martix_multiplier/tb_multiplier.v
// Project Name: martix_multiplier
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: multiplier
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_multiplier;
// Inputs
reg [12:0] A;
reg [12:0] B;
reg clk;
// Outputs
wire [26:0] Y;
wire [26:0] Z;
reg [10:0] i;
wire ok;
reg [26:0] Y_cmp;
reg [26:0] Z_cmp;
// Instantiate the Unit Under Test (UUT)
multiplier uut (
.clk(clk),
.A(A),
.B(B),
.Y(Y),
.Z(Z)
);
initial begin
// Initialize Inputs
A = 0;
B = 0;
i = 0;
clk = 0;
//ok = 0;
// Wait 100 ns for global reset to finish
#100;
end
always
begin
// -------------------------------
A = 13'b1111111111111;
B = 13'b1111111111111;
Y_cmp = 27'b111111111111111111111011101;
Z_cmp = 27'b000000000000000000010000010;
while(i < 16)
begin
#1 clk = ~clk;
i = i + 1;
end
i = 0;
// -------------------------------
A = 13'b0000000000000;
B = 13'b0000000000000;
Y_cmp = 27'b000000000000000000000000000;
Z_cmp = 27'b000000000000000000000000000;
while(i < 16)
begin
#1 clk = ~clk;
i = i + 1;
end
i = 0;
// -------------------------------
A = 13'b1111111111111;
B = 13'b0000000000000;
Y_cmp = 27'b000000000000000000000000010;
Z_cmp = 27'b111111111111111111111001110;
while(i < 16)
begin
#1 clk = ~clk;
i = i + 1;
end
i = 0;
// -------------------------------
A = 13'b0000000000000;
B = 13'b1111111111111;
Y_cmp = 27'b111111111111111111111011011;
Z_cmp = 27'b000000000000000000010110100;
while(i < 16)
begin
#1 clk = ~clk;
i = i + 1;
end
i = 0;
// -------------------------------
A = 13'b1010101010101;
B = 13'b1010111010101;
Y_cmp = 27'b111111111101001110100011111;
Z_cmp = 27'b000000001010001000011010110;
while(i < 16)
begin
#1 clk = ~clk;
i = i + 1;
end
i = 0;
// -------------------------------
A = 13'b0101010101010;
B = 13'b0101010001010;
Y_cmp = 27'b000000000010111000010011110;
Z_cmp = 27'b111111110101010110000101100;
while(i < 16)
begin
#1 clk = ~clk;
i = i + 1;
end
i = 0;
// -------------------------------
A = 13'b1111100000111;
B = 13'b1110000000011;
Y_cmp = 27'b111111111110110111001100001;
Z_cmp = 27'b000000000101001110101000010;
while(i < 16)
begin
#1 clk = ~clk;
i = i + 1;
end
i = 0;
// -------------------------------
A = 13'b0011110110111;
B = 13'b0010010101111;
Y_cmp = 27'b000000000001001110111011101;
Z_cmp = 27'b111111111100011011010110010;
while(i < 16)
begin
#1 clk = ~clk;
i = i + 1;
end
i = 0;
end
assign ok = (Y == Y_cmp && Z == Z_cmp) ? 1'b1 : 1'b0;
endmodule
|
#include <bits/stdc++.h> using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); const long long int mod = 1e9 + 7; long double dp[111][11111], ans; long long int a[111], n, k, x; int main(void) { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; int i, j, k; cin >> n >> x; dp[0][0] = 1; for (i = 1; i <= n; i++) cin >> a[i]; for (i = 1; i <= n; i++) for (j = i - 1; j >= 0; j--) for (k = 0; k <= 10000; k++) dp[j + 1][k + a[i]] += dp[j][k] * (j + 1) / (n - j); for (i = 1; i <= n; i++) for (j = 1; j <= 10000; j++) ans += min((1.0 * n / i + 1) * x / 2, 1.0 * j / i) * dp[i][j]; cout << fixed << setprecision(15) << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 100010; const int maxm = 100010; struct Arc { int to, next; } arcs[maxm]; int head[maxn], ne, out[maxn], ans[maxn]; inline void add_arc(int u, int v); priority_queue<int> Q; int main() { int n, m, i, u, v, k; while (scanf( %d%d , &n, &m) > 0) { memset(head, -1, sizeof(int) * (n + 1)); ne = 0; memset(out, 0, sizeof(int) * (n + 1)); for (i = 0; i < m; i++) { scanf( %d%d , &u, &v); add_arc(v, u); out[u]++; } while (!Q.empty()) Q.pop(); for (i = 1; i <= n; i++) { if (out[i] == 0) Q.push(i); } for (k = n; k >= 1; k--) { u = Q.top(); Q.pop(); ans[u] = k; for (i = head[u]; i != -1; i = arcs[i].next) { v = arcs[i].to; if (--out[v] == 0) Q.push(v); } } for (i = 1; i <= n; i++) printf( %d , ans[i]); printf( n ); } return 0; } inline void add_arc(int u, int v) { arcs[ne].to = v; arcs[ne].next = head[u]; head[u] = ne++; return; } |
#include <bits/stdc++.h> using namespace std; map<string, int> m; int main() { int n; cin >> n; string x, y; for (int i = 0; i < n; i++) { cin >> x >> y; m[y]++; } int t1, t2, temp, temp1; t1 = m[ hard ]; t2 = m[ soft ]; if (t1 > t2) { temp = t1; t1 = t2; t2 = temp; } for (int i = 1; i < 100; i++) { temp = i * i; temp1 = temp / 2; temp -= temp1; if (temp1 >= t1 && temp >= t2) { cout << i << endl; return 0; } } } |
#include <bits/stdc++.h> using namespace std; template <typename T> T cross(complex<T> a, complex<T> b) { return imag(conj(a) * b); } template <typename T> T dot(complex<T> a, complex<T> b) { return real(conj(a) * b); } struct __Query { static bool query; }; bool __Query::query = false; template <typename T> struct Point { complex<T> p; mutable function<const complex<T> *()> succ; bool operator<(const Point &rhs) const { const complex<T> &q = rhs.p; if (!__Query::query) { if (real(p) != real(q)) return real(p) < real(q); return imag(p) < imag(q); } const complex<T> *s = succ(); if (!s) return false; return dot(p - *s, q) < 0; } }; template <typename T, int turn> struct half_hull : public set<Point<T>> { using set<Point<T>>::begin; using set<Point<T>>::insert; using set<Point<T>>::end; using set<Point<T>>::lower_bound; using set<Point<T>>::empty; using set<Point<T>>::erase; using typename set<Point<T>>::iterator; complex<T> extreme(const complex<T> &p) const { assert(!empty() && turn * imag(p) >= 0); __Query::query = true; auto pos = lower_bound(Point<T>{p}); __Query::query = false; assert(pos != end()); return pos->p; } void insert(const complex<T> &p) { auto y = insert(Point<T>{p}).first; if (y == end()) return; y->succ = [=] { return next(y) == end() ? nullptr : &next(y)->p; }; if (bad(y)) { erase(y); return; } while (y != begin() && bad(prev(y))) erase(prev(y)); while (next(y) != end() && bad(next(y))) erase(next(y)); } private: bool bad(iterator y) { if (y == begin() || y == end()) return false; auto x = prev(y), z = next(y); if (z == end()) return false; return cross(y->p - x->p, z->p - x->p) * turn >= 0; } }; template <typename T> struct convex_hull_trick { void insert(const complex<T> &p) { lower_hull.insert(p); upper_hull.insert(p); } complex<T> extreme(const complex<T> &p) const { if (std::imag(p) < 0) return lower_hull.extreme(p); return upper_hull.extreme(p); } long long get(const complex<T> &p) const { if (upper_hull.empty()) return 0LL; return dot(p, extreme(p)); } private: half_hull<T, +1> upper_hull; half_hull<T, -1> lower_hull; }; long long solve(vector<vector<int>> &adj, int root = 0) { int n = adj.size(); vector<long long> sz(n), sz2(n), ssz(n); long long ans = 0; function<void(int, int)> dfs = [&](int u, int p) { sz[u] = 1; for (auto v : adj[u]) if (v != p) { dfs(v, u); sz[u] += sz[v]; } }; function<void(int, int)> dfs2 = [&](int u, int p) { sz2[u] += sz[u] * sz[u]; for (auto v : adj[u]) if (v != p) { sz2[v] += sz2[u]; ssz[v] += ssz[u] + sz[v] * sz[u]; dfs2(v, u); } }; function<long long(int, int)> dfs3 = [&](int u, int p) { convex_hull_trick<long long> cht; long long ret = -sz2[u] + ssz[u]; for (auto v : adj[u]) if (v != p) { long long temp = dfs3(v, u); ret = max(ret, temp); long long r = sz[v] * n + sz2[u] - ssz[v] + temp; ans = max(ans, r); ans = max(ans, r + cht.get({1LL, -sz[v]})); cht.insert({r, sz[v]}); } return ret; }; dfs(root, -1); dfs2(root, -1); dfs3(root, -1); return ans; } int main() { ios_base::sync_with_stdio(0), cin.tie(0); int n; cin >> n; vector<vector<int>> adj(n); for (int i = 1, u, v; i < n; ++i) { cin >> u >> v; --u, --v; adj[u].push_back(v); adj[v].push_back(u); } long long ans = n * (n - 1LL) / 2 + solve(adj); cout << ans << n ; return 0; } |
`ifdef __ICARUS__
`define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
`endif
/*
* Copyright (c) 2001 Stephan Boettcher <>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// $Id: memidxrng.v,v 1.1 2001/09/29 05:03:41 sib4 Exp $
// $Log: memidxrng.v,v $
// Revision 1.1 2001/09/29 05:03:41 sib4
// add memidxrng.v: memory address range check
//
module memidxrng;
reg mem[12:2];
reg [7:0] i;
integer errs = 0;
initial
begin
for (i=0; i<255; i=i+1) mem[i] <= ^i;
#1;
for (i=0; i<17; i=i+1)
$display("mem[%d] = %b \%b", i, mem[i], ^i);
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
if (mem[13] !== 1'bx)
begin
$display("FAILED: mem[13] = %b, expect x", mem[14]);
errs = errs + 1;
end
if (mem[1] !== 1'bx)
begin
$display("FAILED: mem[1] = %b, expect x", mem[1]);
errs = errs + 1;
end
`endif
if (errs===0)
$display("PASSED");
$finish;
end
endmodule
|
`default_nettype none
module thinpad_top(/*autoport*/
//inout
base_ram_data,
ext_ram_data,
flash_data,
sl811_data,
dm9k_data,
//output
base_ram_addr,
base_ram_be_n,
base_ram_ce_n,
base_ram_oe_n,
base_ram_we_n,
ext_ram_addr,
ext_ram_be_n,
ext_ram_ce_n,
ext_ram_oe_n,
ext_ram_we_n,
txd,
flash_address,
flash_rp_n,
flash_vpen,
flash_oe_n,
flash_ce,
flash_byte_n,
flash_we_n,
sl811_a0,
sl811_we_n,
sl811_rd_n,
sl811_cs_n,
sl811_rst_n,
sl811_drq,
dm9k_cmd,
dm9k_we_n,
dm9k_rd_n,
dm9k_cs_n,
dm9k_rst_n,
leds,
vga_pixel,
vga_hsync,
vga_vsync,
vga_clk,
vga_de,
//input
clk_in,
clk_uart_in,
rxd,
sl811_dack,
sl811_int,
dm9k_int,
dip_sw,
touch_btn);
input wire clk_in; //50MHz main clock input
input wire clk_uart_in; //11.0592MHz clock for UART
//Base memory signals
inout wire[31:0] base_ram_data;
output wire[19:0] base_ram_addr;
output wire[3:0] base_ram_be_n;
output wire base_ram_ce_n;
output wire base_ram_oe_n;
output wire base_ram_we_n;
assign base_ram_be_n=4'b0; //leave ByteEnable zero if you don't know what it is
//Extension memory signals
inout wire[31:0] ext_ram_data;
output wire[19:0] ext_ram_addr;
output wire[3:0] ext_ram_be_n;
output wire ext_ram_ce_n;
output wire ext_ram_oe_n;
output wire ext_ram_we_n;
assign ext_ram_be_n=4'b0;
//Serial port signals
output wire txd;
input wire rxd;
//Flash memory, JS28F640
output wire [21:0]flash_address;
output wire flash_rp_n;
output wire flash_vpen;
output wire flash_oe_n;
inout wire [15:0]flash_data;
output wire flash_ce;
output wire flash_byte_n;
output wire flash_we_n;
//SL811 USB controller signals
output wire sl811_a0;
inout wire[7:0] sl811_data;
output wire sl811_we_n;
output wire sl811_rd_n;
output wire sl811_cs_n;
output wire sl811_rst_n;
input wire sl811_dack;
input wire sl811_int;
output wire sl811_drq;
//DM9000 Ethernet controller signals
output wire dm9k_cmd;
inout wire[15:0] dm9k_data;
output wire dm9k_we_n;
output wire dm9k_rd_n;
output wire dm9k_cs_n;
output wire dm9k_rst_n;
input wire dm9k_int;
//LED, SegDisp, DIP SW, and BTN1~6
output wire[31:0] leds;
input wire[31:0] dip_sw;
input wire[5:0] touch_btn;
//Video output
output wire[7:0] vga_pixel;
output wire vga_hsync;
output wire vga_vsync;
output wire vga_clk;
output wire vga_de;
//flash
wire [22:0] flash_addr;
wire [7:0] number;
assign flash_ce = 1'b0;
assign flash_address = flash_addr[22:1];
//wire sram_sramEnable;
//wire sram_writeEnable;
//wire sram_readEnable;
//assign base_ram_we_n = sram_writeEnable;
//assign ext_ram_we_n = sram_writeEnable;
//assign base_ram_ce_n = sram_sramEnable;
//assign ext_ram_ce_n = sram_sramEnable;
//assign base_ram_oe_n = sram_readEnable;
//assign ext_ram_oe_n = sram_readEnable;
//LED & DIP switches test
reg[23:0] counter;
reg[15:0] led_bits;
always@(posedge clk_in) begin
if(touch_btn[5])begin //reset
counter<=0;
led_bits[15:0] <= dip_sw[15:0]^dip_sw[31:16];
end
else begin
counter<= counter+1;
if(&counter)
led_bits[15:0] <= {led_bits[14:0],led_bits[15]};
end
end
assign leds[15:0] = led_bits;
//Serial port receive and transmit, 115200 baudrate, no parity
//wire [7:0] RxD_data;
//wire RxD_data_ready;
//async_receiver #(.ClkFrequency(11059200),.Baud(115200))
// uart_r(.clk(clk_uart_in),.RxD(rxd),.RxD_data_ready(RxD_data_ready),.RxD_data(RxD_data));
//async_transmitter #(.ClkFrequency(11059200),.Baud(115200))
// uart_t(.clk(clk_uart_in),.TxD(txd),.TxD_start(RxD_data_ready),.TxD_data(RxD_data)); //transmit data back
//// 7-Segment display decoder
SEG7_LUT segL(.oSEG1({leds[23:22],leds[19:17],leds[20],leds[21],leds[16]}), .iDIG(number[3:0]));
SEG7_LUT segH(.oSEG1({leds[31:30],leds[27:25],leds[28],leds[29],leds[24]}), .iDIG(number[7:4]));
//always @(posedge clk_uart_in) begin
// if(RxD_data_ready)
// number <= RxD_data; //show received data on segment display
//end
//VGA display pattern generation
wire [2:0] red,green;
wire [1:0] blue;
assign vga_pixel = {red,green,blue};
assign vga_clk = clk_in;
vga #(12, 800, 856, 976, 1040, 600, 637, 643, 666, 1, 1) vga800x600at75 (
.clk(clk_in),
.hdata(red),
.vdata({blue,green}),
.hsync(vga_hsync),
.vsync(vga_vsync),
.data_enable(vga_de)
);
cpu top(
// .clk50(touch_btn[4]),
.clk50(clk_in),
.rst(!touch_btn[5]),
.sram_sramEnable_o(base_ram_ce_n),
.sram_writeEnable_o(base_ram_we_n),
.sram_readEnable_o(base_ram_oe_n),
.sram_addr_o(base_ram_addr),
.sram_data_io(base_ram_data),
.flash_flashByte_o(flash_byte_n),
.flash_flashVpen_o(flash_vpen),
.flash_flashRP_o(flash_rp_n),
.flash_flashSTS_o(1'b1),
.flash_flashEnable_o(),
.flash_flashCE1_o(),
.flash_flashCE2_o(),
.flash_readEnable_o(flash_oe_n),
.flash_writeEnable_o(flash_we_n),
.flash_addr_o(flash_addr),
.flash_data_io(flash_data),
.pc_output(number),
.led_o(),
.RxD(rxd),
.TxD(txd)
);
sram SRAM(
.addr_i(base_ram_addr),
//Enable
.en_i(base_ram_ce_n),
//Write
.we_i(base_ram_we_n),
//Output
.oe_i(base_ram_oe_n),
//Data
.data_io(base_ram_data)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long arr1[100][10000], arr[10000]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long t, i, j, k, n, m, x, y, z, a, b, mx; cin >> t; while (t--) { cin >> n; for (i = 0; i < n; i++) { cin >> arr[i]; } for (i = 1; i < 27; i++) { x = 0; for (j = 0; j < n; j++) { if (arr[j] == i) { x++; arr1[i][j] = x; } else { arr1[i][j] = x; } } } mx = 1; for (i = 0; i < n; i++) { for (j = i + 1; j < n; j++) { if (arr[j] == arr[i] && (arr1[arr[i]][i]) == (arr1[arr[i]][n - 1] - arr1[arr[i]][j] + 1)) { x = arr1[arr[i]][i] + arr1[arr[i]][n - 1] - arr1[arr[i]][j] + 1; for (k = 1; k <= 26; k++) { y = arr1[k][j - 1] - arr1[k][i]; z = x + y; mx = max(z, mx); } } } } cout << mx << endl; } } |
#include <bits/stdc++.h> using namespace std; int main() { int i, c, a, b; cin >> a >> b >> c; c -= 1; while (c) { c--; i = a + b; a = b; b = i; } cout << b << endl; } |
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
// Date : Thu May 22 15:29:26 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode synth_stub
// /home/keith/Documents/VHDL-lib/top/mono_radio/ip/fir_lp_800kHz_0/fir_lp_800kHz_stub.v
// Design : fir_lp_800kHz
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fir_compiler_v7_1,Vivado 2014.1" *)
module fir_lp_800kHz(aclk, s_axis_data_tvalid, s_axis_data_tready, s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata)
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[31:0],m_axis_data_tvalid,m_axis_data_tdata[95:0]" */;
input aclk;
input s_axis_data_tvalid;
output s_axis_data_tready;
input [31:0]s_axis_data_tdata;
output m_axis_data_tvalid;
output [95:0]m_axis_data_tdata;
endmodule
|
#include <bits/stdc++.h> using namespace std; using LL = long long; const int N = 2.5e5; vector<int> adj[N]; int dep[N], par[N]; bool leaf[N]; bool dfs(int u, int p = -1, int d = 1) { if (dep[u] > 0) return false; dep[u] = d; par[u] = p; leaf[u] = true; for (int v : adj[u]) { if (dfs(v, u, d + 1)) leaf[u] = false; } return true; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, m, k; cin >> n >> m >> k; for (int i = 0; i < m; i++) { int u, v; cin >> u >> v; u--, v--; adj[u].push_back(v); adj[v].push_back(u); } dfs(0); int r = 0; for (int u = 0; u < n; u++) { if (dep[u] > dep[r]) r = u; } dfs(r); const int plen = ((n + k - 1) / k); int leaves = 0; for (int u = 0; u < n; u++) { if (dep[u] >= plen) { cout << PATH n << dep[u] << n ; while (u != -1) { cout << (u + 1) << ; u = par[u]; } cout << n ; return 0; } if (leaf[u]) leaves++; } assert(leaves >= k); cout << CYCLES n ; int values[3]; vector<int> cy; cy.reserve(N); for (int u = 0; u < n && k > 0; u++) { if (!leaf[u]) continue; int top = -1; int id = 0; for (int v : adj[u]) { if (v == par[u]) continue; if ((dep[u] - dep[v]) >= 3 && (dep[u] - dep[v] + 1) % 3 != 0) { top = v; break; } values[id++] = v; if (id == 2) break; } if (top >= 0) { for (int v = u; v != top; v = par[v]) { cy.push_back(v); } cy.push_back(top); } else { cy.push_back(u); if (dep[values[0]] < dep[values[1]]) swap(values[0], values[1]); for (int v = values[0]; v != values[1]; v = par[v]) { cy.push_back(v); } cy.push_back(values[1]); } cout << cy.size() << n ; for (int u : cy) cout << (u + 1) << ; cout << n ; cy.clear(); k--; } return 0; } |
#include <bits/stdc++.h> using namespace std; signed main() { ios_base::sync_with_stdio(false); cin.tie(0); long long n, k; cin >> n >> k; long long ans[6][3] = {0, 1, 2, 1, 0, 2, 1, 2, 0, 2, 1, 0, 2, 0, 1, 0, 2, 1}; cout << ans[n % 6][k] << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int dp[2][2005]; int a[2005]; int cnt2[2005]; int main() { int n; cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = n; i >= 1; i--) { cnt2[i] = cnt2[i + 1]; if (a[i] == 2) cnt2[i]++; } for (int i = 0; i <= 2; i++) dp[i][0] = 1; for (int i = 1; i <= n; i++) { dp[0][i] = dp[1][i] = 1; for (int j = 1; j <= i - 1; j++) { if (a[i] >= a[j]) dp[0][i] = max(dp[0][j] + 1, dp[0][i]); if (a[i] <= a[j]) dp[1][i] = max(max(dp[0][j], dp[1][j]) + 1, dp[1][i]); } } int ans = 0; for (int i = 1; i <= n; i++) { ans = max(dp[1][i] + cnt2[i + 1], ans); } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> int main(int argc, char* argv[]) { int t, cups = 0, medals = 0, n, shelives_needed = 0; for (int i = 0; i < 3; i++) { scanf( %d , &t); cups += t; } for (int i = 0; i < 3; i++) { scanf( %d , &t); medals += t; } scanf( %d , &n); if (cups % 5 != 0) { shelives_needed += cups / 5 + 1; } else { shelives_needed += cups / 5; } if (medals % 10 != 0) { shelives_needed += medals / 10 + 1; } else { shelives_needed += medals / 10; } if (shelives_needed > n) { printf( NO n ); } else { printf( YES n ); } return 0; } |
module uart_tx
#(parameter BAUD_DIV=2,
parameter BAUD_DIV_WIDTH=8,
parameter W=8) // data width
(input c,
input [W-1:0] in,
input in_en,
output in_ack,
output out,
output busy);
// as implemented below, BAUD_DIV must be >= 2. Lower values are ignored.
wire tx_r_en, tx_sel;
wire [W+1:0] tx;
r #(W+2) tx_r
(.c(c), .en(tx_r_en), .rst(1'b0), .q(tx),
.d(tx_sel ? {1'b1, in, 1'b0} : {1'b0, tx[W+1:1]}));
wire [BAUD_DIV_WIDTH-1:0] baud_div_count;
r #(BAUD_DIV_WIDTH) baud_div_count_r
(.c(c), .en(1'b1), .rst(baud_div_count == BAUD_DIV-1),
.d(baud_div_count + 1'b1), .q(baud_div_count));
wire tx_edge = ~|baud_div_count;
localparam CW = 4;
localparam SW = 3;
localparam ST_IDLE = 3'd0;
localparam ST_SYNC = 3'd1; // line up with baud clock
localparam ST_TX = 3'd2; // this includes the start and stop bits in tx_r
reg [CW+SW-1:0] ctrl;
wire [SW-1:0] state;
wire [SW-1:0] next_state = ctrl[CW+SW-1:CW];
r #(SW) state_r(.c(c), .d(next_state), .rst(1'b0), .en(1'b1), .q(state));
always @* begin
case (state)
ST_IDLE:
if (in_en) ctrl = {ST_SYNC , 4'b0111};
else ctrl = {ST_IDLE , 4'b0000};
ST_SYNC:
if (tx_edge) ctrl = {ST_TX , 4'b0000};
else ctrl = {ST_SYNC , 4'b0000};
ST_TX:
if (tx_edge)
if (~|tx[W+1:1]) ctrl = {ST_IDLE, 4'b1001};
else ctrl = {ST_TX, 4'b1001};
else ctrl = {ST_TX, 4'b1000};
default: ctrl = {ST_IDLE , 4'b0000};
endcase
end
assign tx_r_en = ctrl[0];
assign in_ack = ctrl[1];
assign tx_sel = ctrl[2];
assign out = ctrl[3] ? tx[0] : 1'b1;
assign busy = (state != ST_IDLE);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Iztok Jeras.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// packed structures
struct packed {
logic e0;
logic [1:0] e1;
logic [3:0] e2;
logic [7:0] e3;
} struct_bg; // big endian structure
/* verilator lint_off LITENDIAN */
struct packed {
logic e0;
logic [0:1] e1;
logic [0:3] e2;
logic [0:7] e3;
} struct_lt; // little endian structure
/* verilator lint_on LITENDIAN */
integer cnt = 0;
// event counter
always @ (posedge clk)
begin
cnt <= cnt + 1;
end
// finish report
always @ (posedge clk)
if (cnt==2) begin
$write("*-* All Finished *-*\n");
$finish;
end
always @ (posedge clk)
if (cnt==1) begin
// big endian
if ($bits (struct_bg ) != 15) $stop;
if ($bits (struct_bg.e0) != 1) $stop;
if ($bits (struct_bg.e1) != 2) $stop;
if ($bits (struct_bg.e2) != 4) $stop;
if ($bits (struct_bg.e3) != 8) $stop;
if ($increment (struct_bg, 1) != 1) $stop;
// little endian
if ($bits (struct_lt ) != 15) $stop;
if ($bits (struct_lt.e0) != 1) $stop;
if ($bits (struct_lt.e1) != 2) $stop;
if ($bits (struct_lt.e2) != 4) $stop;
if ($bits (struct_lt.e3) != 8) $stop;
if ($increment (struct_lt, 1) != 1) $stop; // Structure itself always big numbered
end
endmodule
|
/*
* PCI Express to FIFO - Xilinx ADC interface
* Copyright (C) 2014 Harmon Instruments, LLC
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/
*
* din[15:0] DRP data
* din[24:16] DRP address
* din[31] DRP write enable
*
* dout[15:0] DRP data
* dout[16] busy
*
*/
`timescale 1ns / 1ps
module gt_drp
(
input clock,
input drp_clock,
input write,
input [63:0] din,
output reg [16:0] dout = 0,
// GT DRP
output reg [8:0] drp_address,
output drp_en,
output reg [15:0] drp_di,
input [15:0] drp_do,
input drp_ready,
output reg drp_we
);
reg [3:0] state = 0;
reg drp_en_clock = 0;
wire drp_ready_sync;
sync sync_ready (.clock(clock), .in(drp_ready), .out(drp_ready_sync));
sync_oneshot sync_en (.clock(drp_clock), .in(drp_en_clock), .out(drp_en));
always @ (posedge clock)
begin
dout[16] <= state != 0;
case(state)
0: state <= write;
12: state <= write ? 1'b1 : state + drp_ready_sync;
default: state <= state + 1'b1;
endcase
drp_en_clock <= (state > 1) && (state < 12);
if(write)
begin
drp_di <= din[15:0];
drp_address <= din[24:16];
drp_we <= din[31];
end
if(state == 13)
dout[15:0] <= drp_do;
end
endmodule
|
/*
* Copyright (c) 2001 Stephan Boettcher <>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// $Id: deposit.v,v 1.4 2001/11/22 04:36:33 sib4 Exp $
// Test for vpi_put_value() to properly propagate in structural context.
module deposit_test;
reg ck;
reg start;
initial start = 0;
`ifdef RTL
reg [3:0] cnt;
wire cnt_tc = &cnt;
always @(posedge ck)
if (start | ~cnt_tc)
cnt <= cnt + 1;
`else // !ifdef RTL
wire [3:0] cnt;
wire [3:0] cnt_1;
wire [3:0] cnt_c;
wire cnt_tc;
wire ne, e;
and (cnt_tc, cnt[0], cnt[1], cnt[2], cnt[3]);
not (ne, cnt_tc);
or (e, ne, start);
had A0 (cnt[0], 1'b1, cnt_c[0], cnt_1[0]);
had A1 (cnt[1], cnt_c[0], cnt_c[1], cnt_1[1]);
had A2 (cnt[2], cnt_c[1], cnt_c[2], cnt_1[2]);
had A3 (cnt[3], cnt_c[2], cnt_c[3], cnt_1[3]);
dffe C0 (ck, e, cnt_1[0], cnt[0]);
dffe C1 (ck, e, cnt_1[1], cnt[1]);
dffe C2 (ck, e, cnt_1[2], cnt[2]);
dffe C3 (ck, e, cnt_1[3], cnt[3]);
`endif // !ifdef RTL
integer r0; initial r0 = 0;
integer r1; initial r1 = 0;
always
begin
#5 ck <= 0;
#4;
$display("%b %b %d %d", cnt, cnt_tc, r0, r1);
if (cnt_tc === 1'b0) r0 = r0 + 1;
if (cnt_tc === 1'b1) r1 = r1 + 1;
#1 ck <= 1;
end
initial
begin
// $dumpfile("deposit.vcd");
// $dumpvars(0, deposit_test);
#22;
`ifdef RTL
cnt <= 4'b 1010;
`else
$deposit(C0.Q, 1'b0);
$deposit(C1.Q, 1'b1);
$deposit(C2.Q, 1'b0);
$deposit(C3.Q, 1'b1);
`endif
#1 if (cnt !== 4'b1010)
$display("FAILED");
#99;
$display("%d/%d", r0, r1);
if (r0===5 && r1===5)
$display("PASSED");
else
$display("FAILED");
$finish;
end
endmodule
`ifdef RTL
`else
module dffe (CK, E, D, Q);
input CK, E, D;
output Q;
wire qq;
UDP_dffe ff (qq, CK, E, D);
buf #1 (Q, qq);
endmodule
primitive UDP_dffe (q, cp, e, d);
output q;
reg q;
input cp, e, d;
table
(01) 1 1 : ? : 1 ;
(01) 1 0 : ? : 0 ;
* 0 ? : ? : - ;
* ? 1 : 1 : - ;
* ? 0 : 0 : - ;
(1x) ? ? : ? : - ;
(?0) ? ? : ? : - ;
? ? * : ? : - ;
? * ? : ? : - ;
endtable
endprimitive
module had (A, B, C, S);
input A, B;
output C, S;
xor s (S, A, B);
and c (C, A, B);
endmodule
`endif // !ifdef RTL
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Thu May 25 15:18:26 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_debounce_0_0/system_debounce_0_0_stub.v
// Design : system_debounce_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "debounce,Vivado 2016.4" *)
module system_debounce_0_0(clk, signal_in, signal_out)
/* synthesis syn_black_box black_box_pad_pin="clk,signal_in,signal_out" */;
input clk;
input signal_in;
output signal_out;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int n, k; int a[200005]; int main() { int t; scanf( %d , &t); while (t--) { scanf( %d%d , &n, &k); int pos = 0, mn = 1000000000; for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); if (i > k && a[i] - a[i - k] < mn) { mn = a[i] - a[i - k]; pos = i; } } printf( %d n , (a[pos] + a[pos - k]) / 2); } return 0; } |
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module Computer_System_Pushbuttons (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input [ 3: 0] in_port;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 3: 0] d1_data_in;
reg [ 3: 0] d2_data_in;
wire [ 3: 0] data_in;
reg [ 3: 0] edge_capture;
wire edge_capture_wr_strobe;
wire [ 3: 0] edge_detect;
wire irq;
reg [ 3: 0] irq_mask;
wire [ 3: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({4 {(address == 0)}} & data_in) |
({4 {(address == 2)}} & irq_mask) |
({4 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2))
irq_mask <= writedata[3 : 0];
end
assign irq = |(edge_capture & irq_mask);
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[0] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[0])
edge_capture[0] <= 0;
else if (edge_detect[0])
edge_capture[0] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[1] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[1])
edge_capture[1] <= 0;
else if (edge_detect[1])
edge_capture[1] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[2] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[2])
edge_capture[2] <= 0;
else if (edge_detect[2])
edge_capture[2] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[3] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[3])
edge_capture[3] <= 0;
else if (edge_detect[3])
edge_capture[3] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_data_in <= 0;
d2_data_in <= 0;
end
else if (clk_en)
begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = ~d1_data_in & d2_data_in;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); int tt; cin >> tt; while(tt--) { int n; cin >> n; vector<int> a(n); for(int i = 0; i < n; i++) { cin >> a[i]; } set<int> s; s.insert(a[0]); bool ok = true; for(int i = 1; i < n; i++) { int x = min(a[i], a[i - 1]); int y = max(a[i], a[i - 1]); if(s.upper_bound(x) != s.end()) { if(*s.upper_bound(x) < y) { ok = false; break; } } s.insert(a[i]); } cout << (ok ? YES : NO ) << n ; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR3_SYMBOL_V
`define SKY130_FD_SC_HS__OR3_SYMBOL_V
/**
* or3: 3-input OR.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__or3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR3_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 5; const int MAXM = 20; int n, m; int a[MAXN], b[MAXM]; int num[MAXM]; char ans[MAXN][MAXM]; set<int> states[MAXM]; int getState(int mask, int num[MAXM]) { int res = mask; for (int i = 0; i < n; ++i) { res = res * MAXN + num[i]; } return res; } bool dfs(int j, int lastState = 0) { if (j == m) { for (int i = 0; i < n; ++i) { if (num[i] != a[i]) { return false; } } return true; } if (j) { if (states[j].find(lastState) != states[j].end()) { return false; } states[j].insert(lastState); } int origin[MAXM]; memcpy(origin, num, sizeof(num)); for (int k = 0; k < (1 << n); ++k) { int cnt = 0; for (int i = 0; i < n; ++i) { if (k & (1 << i)) { ans[i][j] = * ; if (i == 0 || ans[i - 1][j] == . ) { ++cnt; } } else { ans[i][j] = . ; } } if (cnt != b[j]) { continue; } for (int i = 0; i < n; ++i) { if (ans[i][j] == * ) { if (j == 0 || ans[i][j - 1] == . ) { ++num[i]; } } } bool valid = true; for (int i = 0; i < n; ++i) { if (num[i] > a[i]) { valid = false; break; } if (ans[i][j] == * ) { if (a[i] - num[i] > (m - j - 1) / 2) { valid = false; break; } } else { if (a[i] - num[i] > (m - j) / 2) { valid = false; break; } } } if (valid) { if (dfs(j + 1, getState(k, num))) { return true; } } memcpy(num, origin, sizeof(origin)); } return false; } int main() { while (cin >> n >> m) { for (int i = 0; i < n; ++i) { cin >> a[i]; } for (int i = 0; i < m; ++i) { cin >> b[i]; } for (int i = 0; i < n; ++i) { states[i].clear(); } memset(num, 0, sizeof(num)); dfs(0); for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { cout << ans[i][j]; } cout << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 200200; vector<long long int> g[N], e[N]; set<pair<long long int, long long int> > S; int n, m; long long int d[N]; int main() { ios_base::sync_with_stdio(0); cin >> n >> m; for (int i = 1; i <= m; i++) { long long int x, y, z; cin >> x >> y >> z; g[x].push_back(y); e[x].push_back(z); g[y].push_back(x); e[y].push_back(z); } for (int i = 1; i <= n; i++) { cin >> d[i]; S.insert(make_pair(d[i], i)); } while (S.size() != 0) { int u = S.begin()->second; S.erase(S.begin()); for (int i = 0; i < g[u].size(); i++) { long long int v = g[u][i]; long long int cost = e[u][i]; if (cost * 2 + d[u] < d[v]) { S.erase(make_pair(d[v], v)); d[v] = cost * 2 + d[u]; S.insert(make_pair(d[v], v)); } } } for (int i = 1; i <= n; i++) { cout << d[i] << ; } return 0; } |
#include <bits/stdc++.h> const int maxn = 1000010; const int P = 1000000007; int k, w; int f[maxn], g[maxn]; int pow(int x, int y) { int e = 1; while (y) { if (y & 1) e = (long long)e * x % P; x = (long long)x * x % P; y >>= 1; } return e; } int main() { int i, d, t, s = 0; scanf( %d%d , &k, &w); for (f[0] = g[0] = 1, i = 1; i <= k; ++i) f[i] = (long long)f[i - 1] * i % P, g[i] = pow(f[i], P - 2); for (t = 1; t <= k; ++t) { d = (long long)f[k] * g[k - t] % P * g[k - t] % P; if (t <= w - 1) s = ((long long)d * t % P * f[k] % P * pow(k, w - t - 1) + s) % P; else s = ((long long)d * w % P * f[k - t + w - 1] + s) % P; } for (t = 1; t < k; ++t) { d = (long long)f[k] * g[k - t] % P * g[k - t - 1] % P; if (t + 1 <= w - 1) s = ((long long)d * t % P * f[k] % P * pow(k, w - t - 2) + s) % P; else s = ((long long)d * (w - 1) % P * f[k - t + w - 2] + s) % P; } printf( %d , s); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKBUF_BLACKBOX_V
`define SKY130_FD_SC_LS__CLKBUF_BLACKBOX_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__clkbuf (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKBUF_BLACKBOX_V
|
module busInterface (
input wire [31:0] mem_addr,
input wire [31:0] mem_rdata_gpio,
input wire [31:0] mem_rdata_uart,
input wire [31:0] mem_rdata_uartRx,
input wire [31:0] mem_rdata_timer,
input wire [31:0] mem_rdata_prng,
input wire [31:0] mem_rdata_memory,
input wire mem_ready_gpio,
input wire mem_ready_uart,
input wire mem_ready_uartRx,
input wire mem_ready_timer,
input wire mem_ready_prng,
input wire mem_ready_memory,
output wire mem_ready,
output wire [31:0] mem_rdata,
output wire [7:0] enables
);
always @(*) begin
enables = 0;
case (mem_addr[31:4])
28'hffff000: enables[0] = 1'd1;
28'hffff001: enables[1] = 1'd1;
28'hffff002: enables[2] = 1'd1;
28'hffff003: enables[3] = 1'd1;
28'hffff004: enables[4] = 1'd1;
28'hffff005: enables[5] = 1'd1;
28'hffff006: enables[6] = 1'd1;
default: enables[7] = 1;
endcase
case (mem_addr[31:4])
28'hffff000: mem_ready = mem_ready_memory;
28'hffff001: mem_ready = mem_ready_memory;
28'hffff002: mem_ready = mem_ready_uartRx;
28'hffff003: mem_ready = mem_ready_timer;
28'hffff004: mem_ready = mem_ready_uart;
28'hffff005: mem_ready = mem_ready_prng;
28'hffff006: mem_ready = mem_ready_gpio;
default: mem_ready = mem_ready_memory;
endcase
case (mem_addr[31:4])
28'hffff000: mem_rdata = mem_rdata_memory;
28'hffff001: mem_rdata = mem_rdata_memory;
28'hffff002: mem_rdata = mem_rdata_uartRx;
28'hffff003: mem_rdata = mem_rdata_timer;
28'hffff004: mem_rdata = mem_rdata_uart;
28'hffff005: mem_rdata = mem_rdata_prng;
28'hffff006: mem_rdata = mem_rdata_gpio;
default: mem_rdata = mem_rdata_memory;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; inline char gc() { static char buf[131072], *p1 = buf, *p2 = buf; return p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 131072, stdin), p1 == p2) ? EOF : *p1++; } inline void read(int& x) { x = 0; char c = gc(); while (c < 0 || c > 9 ) c = gc(); while (c >= 0 && c <= 9 ) { x = (x << 3) + (x << 1) + (c ^ 48); c = gc(); } } int fa[100003], son[100003][2], st[100003], a[100003], sum[100003], size[100003], tag[100003]; bool rev[100003]; int n, q; inline void pushup(int u) { sum[u] = sum[son[u][0]] + sum[son[u][1]] + a[u]; size[u] = size[son[u][0]] + size[son[u][1]] + 1; } inline bool notrt(const int& u) { return son[fa[u]][0] == u || son[fa[u]][1] == u; } inline void pushr(const int& u) { swap(son[u][0], son[u][1]); rev[u] ^= 1; } inline void pushc(const int& u, const int& k) { a[u] = tag[u] = k; sum[u] = k == 0 ? 0 : size[u]; } inline void pushdown(const int& u) { if (tag[u] != -1) { if (son[u][0]) pushc(son[u][0], tag[u]); if (son[u][1]) pushc(son[u][1], tag[u]); tag[u] = -1; } if (!rev[u]) return; if (son[u][0]) pushr(son[u][0]); if (son[u][1]) pushr(son[u][1]); rev[u] = 0; } inline void rotate(const int& x) { int y = fa[x], z = fa[y]; int k = son[y][1] == x, w = son[x][k ^ 1]; if (notrt(y)) son[z][son[z][1] == y] = x; son[x][k ^ 1] = y; son[y][k] = w; if (w) fa[w] = y; fa[y] = x, fa[x] = z; pushup(y); } inline void splay(const int& x) { register int y = x, z = 0; st[++z] = y; while (notrt(y)) st[++z] = y = fa[y]; while (z) pushdown(st[z--]); while (notrt(x)) { y = fa[x], z = fa[y]; if (notrt(y)) rotate((son[z][1] == y) == (son[y][1] == x) ? y : x); rotate(x); } pushup(x); } inline void access(int u) { for (register int v = 0; u; u = fa[u]) { splay(u), son[u][1] = v; pushup(u), v = u; } } inline void makeroot(int u) { access(u), splay(u); pushr(u); } inline void link(int u, int v) { makeroot(u); fa[u] = v; } inline void split(int u, int v) { makeroot(u); access(v), splay(v); } inline int check(int u1, int v1, int u2, int v2) { split(u1, v1), pushc(v1, 1); split(u2, v2); int res = sum[v2]; split(u1, v1), pushc(v1, 0); return res; } int main() { int x, y, z, ans; read(n), read(q); for (register int i = 1; i <= n; ++i) tag[i] = -1; for (register int i = 2; i <= n; ++i) { read(x); link(x, i); } while (q--) { read(x), read(y), read(z); ans = check(x, y, x, z); ans = max(ans, check(x, y, y, z)); ans = max(ans, check(x, z, y, z)); printf( %d n , ans); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, m; cin >> n >> m; int c[n], w[m]; for (int i = 0; i < n; i++) cin >> c[i]; for (int i = 0; i < m; i++) cin >> w[i]; int res = 0; int j = 0; for (int i = 0; i < n; i++) { if (j > m - 1) { break; } if (w[j] >= c[i]) { res++; j++; } } cout << res << n ; } |
#include <bits/stdc++.h> using namespace std; int ar[310]; bool mp[310][310]; int main() { int n; cin >> n; for (int i = 1; i <= n; i++) cin >> ar[i]; string str; for (int i = 1; i <= n; i++) { cin >> str; for (int j = 0; j < n; j++) if (str[j] == 1 ) mp[i][j + 1] = true; } for (int k = 1; k <= n; k++) for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) if (mp[i][k] && mp[k][j]) mp[i][j] = true; for (int i = 1; i < n; i++) for (int j = i + 1; j <= n; j++) if (ar[i] > ar[j] && mp[i][j]) swap(ar[i], ar[j]); cout << ar[1]; for (int i = 2; i <= n; i++) cout << << ar[i]; cout << n ; } |
#include <bits/stdc++.h> using namespace std; inline int gc() { static const int BUF = 1e7; static char buf[BUF], *bg = buf + BUF, *ed = bg; if (bg == ed) fread(bg = buf, 1, BUF, stdin); return *bg++; } inline int ri() { int x = 0, f = 1, c = gc(); for (; c < 48 || c > 57; f = c == - ? -1 : f, c = gc()) ; for (; c > 47 && c < 58; x = x * 10 + c - 48, c = gc()) ; return x * f; } const int inf = 0x3f3f3f3f; const long long infLL = 0x3f3f3f3f3f3f3f3fLL; const long long mod = 1e9 + 7; const int maxN = 1e5 + 7; int n; int a[maxN]; int ans[maxN]; int BinarySearch(vector<int>& x, int k) { if (x.size() == 0 || a[x[0]] >= k) return -1; int l = 0, r = x.size() - 1; int mid = (l + r) >> 1; while (l < r) { if (a[x[mid]] >= k) { r = mid - 1; mid = (l + r) >> 1; } else { l = mid + 1; if (a[x[l]] >= k) return x[mid]; mid = (l + r) >> 1; } } return x[r]; } int main() { while (cin >> n) { for (int i = (1); i <= (n); ++i) cin >> a[i]; vector<int> vi; for (int i = (1); i <= (n); ++i) { if (vi.empty() || a[i] > a[vi.back()]) { vi.push_back(i); } else if (a[i] <= a[vi.back()]) { vi.pop_back(); --i; } } for (int i = (1); i <= (n); ++i) { ans[i] = BinarySearch(vi, a[i]); ans[i] -= i + 1; if (ans[i] < 0) ans[i] = -1; cout << ans[i] << ; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, l, a[110], s, x, len; int main() { cin >> n >> l; for (int i = 1; i <= n; i++) { cin >> a[i]; if (a[i] > s) s = a[i]; } for (int i = l; i <= s; i++) { for (int j = 1; j <= n; j++) x += a[j] / i; if (len < i * x) len = i * x; x = 0; } cout << len << endl; return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize(3, Ofast , inline ) using namespace std; mt19937 rnd(chrono::high_resolution_clock::now().time_since_epoch().count()); const long long maxn = (long long)1e6 + 5; const long long mod = 998244353; const long long inf = 0x3f3f3f3f; long long T = 1; vector<long long> v[maxn], vec[maxn]; long long dep[maxn], pre[maxn]; long long maxx; void dfs(long long now) { maxx = max(maxx, dep[now]); vec[dep[now]].push_back(now); for (auto &to : v[now]) { if (dep[to]) continue; pre[to] = now; dep[to] = dep[now] + 1; dfs(to); } } void solve() { long long n, m; cin >> n >> m; maxx = 1; for (long long i = 1; i <= n; ++i) v[i].clear(), vec[i].clear(), dep[i] = 0; for (long long i = 1; i <= m; ++i) { long long x, y; cin >> x >> y; v[x].push_back(y); v[y].push_back(x); } dep[1] = 1; dfs(1); if (maxx > (n + 1) / 2) { cout << PATH n ; stack<long long> s; long long now = vec[maxx][0]; while (now) { s.push(now); now = pre[now]; } cout << s.size() << n ; while (!s.empty()) { cout << s.top() << ; s.pop(); } cout << n ; return; } cout << PAIRING n ; long long ans = 0; for (long long i = 1; i <= maxx; ++i) { ans += vec[i].size() / 2; } cout << ans << n ; for (long long i = 1; i <= maxx; ++i) { for (long long j = 0; j + 1 < vec[i].size(); j += 2) { cout << vec[i][j] << << vec[i][j + 1] << n ; } } } signed main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; cin >> T; while (T--) solve(); return 0; } |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:1024000000,1024000000 ) using namespace std; const int N = 1e5 + 10, INF = 0x3f3f3f3f, MOD = 1e9 + 7; int n, m; int u[N], v[N]; vector<int> G[N]; bool check(int m) { for (int i = 1; i <= n; ++i) G[i].clear(); vector<int> in(n + 1, 0); for (int i = 1; i <= m; ++i) { G[u[i]].push_back(v[i]); ++in[v[i]]; } queue<int> q; for (int i = 1; i <= n; ++i) if (!in[i]) q.push(i); while (q.size()) { int u = q.front(); q.pop(); if (q.size()) return false; for (int v : G[u]) if (--in[v] == 0) q.push(v); } return true; } int main() { ios_base::sync_with_stdio(0); scanf( %d%d , &n, &m); for (int i = 1; i <= m; ++i) scanf( %d%d , u + i, v + i); int l = 1, r = m; while (l <= r) { int m = l + r >> 1; if (check(m)) r = m - 1; else l = m + 1; } if (l == m + 1) l = -1; printf( %d n , l); return 0; } |
module io1_sub (/*AUTOARG*/);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [w-1:0] pin; // To/From MD31_pad of autoinst_lopaz_srpad.v
wire [2*w-1:0] pin_in; // From MD31_pad of autoinst_lopaz_srpad.v, ...
wire templated; // To/From MD31_pad of autoinst_lopaz_srpad.v
// End of automatics
autoinst_lopaz_srpad MD31_pad
(.*,
.foo (touch_this_not_my_pretty));
/* autoinst_lopaz_srpad AUTO_TEMPLATE (
); */
autoinst_lopaz_srpad MD31_pad
(.*);
/* autoinst_lopaz_srpad AUTO_TEMPLATE (
.pin (templated));
*/
autoinst_lopaz_srpad MD31_pad
(.*,
// Outputs
// Inouts
.pin (templated) // Templated
);
// And .name with auto inst
autoinst_lopaz_srpad MD31_pad22
(.pin,
.clk,
/*AUTOINST*/
// Outputs
.pin_in (pin_in[2*w-1:0]),
// Inputs
.pin_out (pin_out[w-1:0]),
.pin_outen (pin_outen));
always @(posedge clk) begin
$display ("This .* shouldn't expand.\n");
end
endmodule
|
#include <bits/stdc++.h> std::string input() { static char buf[1000]; scanf( %s , buf); return std::string(buf); } int main() { int inv[5] = {0, 1, 3, 2, 4}; int n, m; std::cin >> n >> m; static int a[500][1000]; for (int i = 0; i < m; i++) { a[i][i + n] = 1; } for (int i = 0; i < n; i++) { std::string s = input(); for (int j = 0; j < m; j++) { a[j][i] = s[j] - a ; } } const int h = m; const int w = n + m; int r = 0; for (int j = 0; j < n && r < h; j++) { int p = r; for (int i = r; i < h; i++) { if (a[i][j] != 0) { p = i; break; } } std::swap(a[p], a[r]); if (a[r][j] == 0) continue; for (int jj = j + 1; jj < w; jj++) { a[r][jj] = a[r][jj] * inv[a[r][j]] % 5; } a[r][j] = 1; for (int ii = 0; ii < h; ii++) { if (ii != r) { for (int jj = j + 1; jj < w; jj++) { a[ii][jj] += 2500 - a[ii][j] * a[r][jj]; a[ii][jj] %= 5; } a[ii][j] = 0; } } r++; } int q; std::cin >> q; while (q--) { std::string b = input(); std::vector<int> v(m); for (int i = 0; i < m; i++) { v[i] = b[i] - a ; } std::vector<int> u(m); for (int i = 0; i < m; i++) { for (int j = 0; j < m; j++) { u[i] += a[i][n + j] * v[j]; } u[i] %= 5; } bool any = false; for (int i = r; i < m; i++) { if (u[i] != 0) { any = true; } } constexpr long long MOD2 = 1e9 + 7; long long ans = 1; for (int i = r; i < n; i++) { ans *= 5; ans %= MOD2; } if (any) { puts( 0 ); continue; } printf( %d n , (int)ans); } } |
#include <bits/stdc++.h> using namespace std; const int MAX = 1e5 + 9; const int MAX1 = 1e6 + 9; const double pi = acos(-1); const long long int inf = 1e9; const long long mod = 1e9 + 7; bool prime[MAX]; int pfactors[MAX]; long long int fact[MAX]; long long int ifact[MAX]; long long int mexp(long long int a, long long int b) { long long int res = 1; while (b > 0) { if (b % 2) { res = (res * a); } a = (a * a); b = b / 2; } return res; } vector<int> totient() { long long tt[MAX]; for (int i = 1; i < MAX; i++) tt[i] = i; for (int i = 2; i < MAX; i++) { if (tt[i] == i) { for (int j = i; j < MAX; j += i) { tt[j] /= i; tt[j] *= i - 1; } } } vector<int> v; for (int i = 1; i < MAX; i++) v.push_back(tt[i]); return v; } vector<int> seive() { for (int i = 2; i < MAX; i++) prime[i] = false; int k = 0; vector<int> p; for (int i = 2; i < MAX; i++) { if (!prime[i]) { for (int j = 2 * i; j < MAX; j += i) prime[j] = true; } } for (int i = 2; i < MAX; i++) { if (!prime[i]) p.push_back(i); } return p; } string s; map<int, int> mp; int n; long long int dp[100][100]; int f[MAX]; int ans[MAX]; void dfs(int cur, int a, int b, long long int x) { if (a < 0 || b < 0) return; if (x > dp[a][b]) dp[a][b] = x; else return; if (cur == 2 * n) { for (int i = 0; i < 2 * n; i++) { ans[i] = f[i]; } return; } long long int c = 1, d = 1; for (int i = 0; i < a - 1; i++) c = c * 10; for (int i = 0; i < b - 1; i++) d = d * 10; f[cur] = 0; dfs(cur + 1, a - 1, b, x + c * (s[cur] - 0 )); f[cur] = 1; dfs(cur + 1, a, b - 1, x + d * (s[cur] - 0 )); } int main() { cin >> n; cin >> s; for (int i = 0; i <= 2 * n; i++) { for (int j = 0; j <= 2 * n; j++) dp[i][j] = -1; } for (int i = 0; i <= 2 * n; i++) { f[i] = -1; ans[i] = -1; } dfs(0, n, n, 0); for (int i = 0; i < 2 * n; i++) { if (ans[i] == 0) cout << H ; else if (ans[i] == 1) cout << M ; } } |
// File: FourToSeven.v
// Generated by MyHDL 0.8dev
// Date: Mon Mar 25 09:12:03 2013
`timescale 1ns/10ps
module FourToSeven (
ByteIn,
Enable,
Polarity,
SegOut
);
input [3:0] ByteIn;
input Enable;
input Polarity;
output [6:0] SegOut;
reg [6:0] SegOut;
always @(Polarity, ByteIn, Enable) begin: FOURTOSEVEN_COMB
reg [7-1:0] SegBuf;
SegBuf = 7'h0;
if ((Enable == 1)) begin
case (ByteIn)
0: SegBuf = 63;
1: SegBuf = 6;
2: SegBuf = 91;
3: SegBuf = 79;
4: SegBuf = 102;
5: SegBuf = 109;
6: SegBuf = 125;
7: SegBuf = 7;
8: SegBuf = 127;
9: SegBuf = 111;
10: SegBuf = 119;
11: SegBuf = 124;
12: SegBuf = 57;
13: SegBuf = 94;
14: SegBuf = 121;
default: SegBuf = 113;
endcase
end
if ((Polarity == 0)) begin
SegBuf = (~SegBuf);
end
SegOut = SegBuf;
end
endmodule
|
// Copyright (C) 2013 Simon Que
//
// This file is part of DuinoCube.
//
// DuinoCube is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// DuinoCube is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with DuinoCube. If not, see <http://www.gnu.org/licenses/>.
// A library of various basic logic elements.
// D flip-flop.
module CC_DFlipFlop(clk, en, reset, d, q);
parameter WIDTH=1;
input clk;
input en;
input reset;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
always @ (posedge clk or posedge reset)
if (reset)
q <= 0;
else if (en)
q <= d;
endmodule
// Chain of D flip-flops.
module CC_Delay(clk, reset, d, q);
parameter WIDTH=1;
parameter DELAY=1;
input clk;
input reset;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
wire [(WIDTH*DELAY)-1:0] reg_inputs;
wire [(WIDTH*DELAY)-1:0] reg_outputs;
genvar i;
generate
for (i = 0; i < DELAY; i = i + 1)
begin: DFF_CHAIN
CC_DFlipFlop #(WIDTH) chain_reg(.clk(clk),
.en(1'b1),
.reset(reset),
.d(reg_inputs[(i+1)*WIDTH-1:i*WIDTH]),
.q(reg_outputs[(i+1)*WIDTH-1:i*WIDTH]));
if (i < DELAY - 1) begin
assign reg_inputs[(i+2)*WIDTH-1:(i+1)*WIDTH] =
reg_outputs[(i+1)*WIDTH-1:i*WIDTH];
end
end
endgenerate
assign q = reg_outputs[(DELAY*WIDTH)-1:(DELAY-1)*WIDTH];
assign reg_inputs[WIDTH-1:0] = d;
endmodule
// D-type Latch.
module CC_DLatch(en, d, q);
parameter WIDTH=1;
input en;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
wire [WIDTH-1:0] reg_out;
CC_DFlipFlop #(WIDTH) r(.clk(~en), .en(1'b1), .reset(0), .d(d), .q(reg_out));
assign q = en ? d : reg_out;
endmodule
// Bidirectional I/O pin.
module CC_Bidir(sel_in, io, in, out);
parameter WIDTH=1;
input sel_in;
inout [WIDTH-1:0] io;
output [WIDTH-1:0] in;
input [WIDTH-1:0] out;
assign in = sel_in ? io : {WIDTH{1'bz}};
assign io = sel_in ? {WIDTH{1'bz}} : out;
endmodule
// Double D flip-flop with a 2:1 multiplexed output.
module CC_MuxReg(sel, clk, en, in_a, in_b, out);
parameter WIDTH=8;
input sel;
input clk;
input en;
input [WIDTH-1:0] in_a;
input [WIDTH-1:0] in_b;
output [WIDTH-1:0] out;
wire [WIDTH-1:0] out_a;
wire [WIDTH-1:0] out_b;
CC_DFlipFlop #(WIDTH) reg_a(clk, en, in_a, out_a);
CC_DFlipFlop #(WIDTH) reg_b(clk, en, in_b, out_b);
assign out = sel ? out_a : out_b;
endmodule
// N-to-2^N decoder/selector/demultiplexer.
module CC_Decoder(in, out);
parameter IN_WIDTH=8;
parameter OUT_WIDTH=(1 << IN_WIDTH);
input [IN_WIDTH-1:0] in;
output [OUT_WIDTH-1:0] out;
genvar i;
generate
for (i = 0; i < OUT_WIDTH; i = i + 1)
begin: SELECT
assign out[i] = (i == in) ? 1'b1 : 1'b0;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; long long pw(int x, int y, int z) { if (y == 0) return 1 % z; long long a = pw(x, y / 2, z); if (y % 2 == 0) return (a * a) % z; else return (((a * a) % z) * x % z) % z; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t--) { long long n; cin >> n; vector<vector<long long>> arr(n, vector<long long>(2)); for (int i = 0; i < n; ++i) cin >> arr[i][0] >> arr[i][1]; map<long long, long long> l, r; for (int i = 0; i < n; ++i) { l[arr[i][0]]++; r[arr[i][1]]++; } sort(arr.begin(), arr.end()); long long ans = (n * (n - 1) * (n - 2)) / 6; sort(arr.begin(), arr.end()); for (int i = 0; i < n; ++i) { long long curl = arr[i][0]; long long nos = l[curl]; long long othel = 0; if (nos >= 2) { for (int j = i; j < i + nos; ++j) { othel += (r[arr[j][1]] - 1); } } ans -= ((nos - 1) * othel); i += nos - 1; } cout << ans << endl; } } |
`include "constants.vh"
`include "alu_ops.vh"
`include "rv32_opcodes.vh"
`default_nettype none
module exunit_branch
(
input wire clk,
input wire reset,
input wire [`DATA_LEN-1:0] ex_src1,
input wire [`DATA_LEN-1:0] ex_src2,
input wire [`ADDR_LEN-1:0] pc,
input wire [`DATA_LEN-1:0] imm,
input wire dstval,
input wire [`ALU_OP_WIDTH-1:0] alu_op,
input wire [`SPECTAG_LEN-1:0] spectag,
input wire specbit,
input wire [`ADDR_LEN-1:0] praddr,
input wire [6:0] opcode,
input wire issue,
output wire [`DATA_LEN-1:0] result,
output wire rrf_we,
output wire rob_we, //set finish
output wire prsuccess,
output wire prmiss,
output wire [`ADDR_LEN-1:0] jmpaddr,
output wire [`ADDR_LEN-1:0] jmpaddr_taken,
output wire brcond,
output wire [`SPECTAG_LEN-1:0] tagregfix
);
reg busy;
wire [`DATA_LEN-1:0] comprslt;
wire addrmatch = (jmpaddr == praddr) ? 1'b1 : 1'b0;
assign rob_we = busy;
assign rrf_we = busy & dstval;
assign result = pc + 4;
assign prsuccess = busy & addrmatch;
assign prmiss = busy & ~addrmatch;
assign jmpaddr = brcond ? jmpaddr_taken : (pc + 4);
assign jmpaddr_taken = (((opcode == `RV32_JALR) ? ex_src1 : pc) + imm);
assign brcond = ((opcode == `RV32_JAL) || (opcode == `RV32_JALR)) ?
1'b1 : comprslt[0];
assign tagregfix = {spectag[0], spectag[`SPECTAG_LEN-1:1]};
always @ (posedge clk) begin
if (reset) begin
busy <= 0;
end else begin
busy <= issue;
end
end
alu comparator
(
.op(alu_op),
.in1(ex_src1),
.in2(ex_src2),
.out(comprslt)
);
endmodule // exunit_branch
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; long long INF = 1e18; int INFi = 2e9; double eps = 1e-6; long long mod = 1e9 + 7; vector<char> used; vector<vector<int>> edge; vector<int> p; vector<int> cnt; int sz = 0; void add(int beg, int end) { while (beg != end) { cnt[beg]++; beg = p[beg]; } } void sub(int beg) { while (used[beg] == 2) { cnt[beg]--; beg = p[beg]; } } void dfs(int v) { used[v] = 1; for (int u : edge[v]) { if (used[u] == -1) { continue; } if (used[u] == 2) { sub(u); continue; } if (used[u] == 1) { add(v, u); sz++; continue; } p[u] = v; dfs(u); } used[v] = 2; } int main() { cin.tie(0); cout.tie(0); ios_base::sync_with_stdio(false); int n, m; cin >> n >> m; edge.resize(n); used.resize(n); p.resize(n); cnt.resize(n); int t1, t2; for (int i = 0; i < m; i++) { cin >> t1 >> t2; t1--; t2--; edge[t1].push_back(t2); } for (int i = 0; i < n; i++) { if (!used[i]) dfs(i); for (int j = 0; j < n; j++) { if (used[j] == 2) used[j] = -1; } } for (int i = 0; i < n; i++) { if (cnt[i] == sz) { cout << YES n ; return 0; } } if (sz == 1) { cout << YES n ; } else { cout << NO n ; } return 0; } |
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module contains counter for the width and height of frames for the *
* video clipper core. *
* *
******************************************************************************/
module altera_up_video_clipper_counters (
// Inputs
clk,
reset,
increment_counters,
// Bi-Directional
// Outputs
start_of_outer_frame,
end_of_outer_frame,
start_of_inner_frame,
end_of_inner_frame,
inner_frame_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter IMAGE_WIDTH = 640; // Final image width in pixels
parameter IMAGE_HEIGHT = 480; // Final image height in lines
parameter WW = 9; // Final image width address width
parameter HW = 8; // Final image height address width
parameter LEFT_OFFSET = 0;
parameter RIGHT_OFFSET = 0;
parameter TOP_OFFSET = 0;
parameter BOTTOM_OFFSET = 0;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input increment_counters;
// Bi-Directional
// Outputs
output start_of_outer_frame;
output end_of_outer_frame;
output start_of_inner_frame;
output end_of_inner_frame;
output inner_frame_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
reg [WW: 0] width;
reg [HW: 0] height;
reg inner_width_valid;
reg inner_height_valid;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output registers
// Internal registers
always @(posedge clk)
begin
if (reset)
width <= 'h0;
else if (increment_counters & (width == (IMAGE_WIDTH - 1)))
width <= 'h0;
else if (increment_counters)
width <= width + 1;
end
always @(posedge clk)
begin
if (reset)
height <= 'h0;
else if (increment_counters & (width == (IMAGE_WIDTH - 1)))
begin
if (height == (IMAGE_HEIGHT - 1))
height <= 'h0;
else
height <= height + 1;
end
end
always @(posedge clk)
begin
if (reset)
inner_width_valid <= (LEFT_OFFSET == 0);
else if (increment_counters)
begin
if (width == (IMAGE_WIDTH - 1))
inner_width_valid <= (LEFT_OFFSET == 0);
else if (width == (IMAGE_WIDTH - RIGHT_OFFSET - 1))
inner_width_valid <= 1'b0;
else if (width == (LEFT_OFFSET - 1))
inner_width_valid <= 1'b1;
end
end
always @(posedge clk)
begin
if (reset)
inner_height_valid <= (TOP_OFFSET == 0);
else if (increment_counters & (width == (IMAGE_WIDTH - 1)))
begin
if (height == (IMAGE_HEIGHT - 1))
inner_height_valid <= (TOP_OFFSET == 0);
else if (height == (IMAGE_HEIGHT - BOTTOM_OFFSET - 1))
inner_height_valid <= 1'b0;
else if (height == (TOP_OFFSET - 1))
inner_height_valid <= 1'b1;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output assignments
assign start_of_outer_frame = (width == 'h0) & (height == 'h0);
assign end_of_outer_frame = (width == (IMAGE_WIDTH - 1)) &
(height == (IMAGE_HEIGHT - 1));
assign start_of_inner_frame = (width == LEFT_OFFSET) &
(height == TOP_OFFSET);
assign end_of_inner_frame = (width == (IMAGE_WIDTH - RIGHT_OFFSET - 1)) &
(height == (IMAGE_HEIGHT - BOTTOM_OFFSET - 1));
assign inner_frame_valid = inner_width_valid & inner_height_valid;
// Internal assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
module framebuffer
(input reset_n,
input vga_clk,
input next_n,
input fb_hblank,
input fb_vblank,
output reg [7:0] red,
output reg [7:0] green,
output reg [7:0] blue
);
reg wait_for_posedge;
reg [7:0] blue_shift;
always @(posedge vga_clk or negedge reset_n or posedge fb_vblank) begin
if(~reset_n || fb_vblank) begin
red <= 8'b0000_0000;
green <= 8'b0000_0000;
blue <= 8'b0000_0000;
blue_shift <= 8'b0000_0000;
wait_for_posedge <= 0;
end else begin
if(fb_hblank && ~wait_for_posedge) begin
// red updates every scanline
red <= red + 1;
// green resets on scanline
green <= 8'b0;
// blue resets but at a new value on the scanline
blue <= blue_shift;
blue_shift <= blue_shift + 1;
wait_for_posedge <= 1;
end else if(~fb_hblank && wait_for_posedge) begin
wait_for_posedge <= 0;
end
if(~fb_hblank && ~fb_vblank) begin
// blue and green step per pixel
green <= green + 1;
blue <= blue + 1;
end
end
end
//assign red = (red_counter == 0) ? 8'b0000_0001 : 8'b0;
//assign green = (green_counter == 0) ? 8'b0000_0001 : 8'b0;
//assign blue = (blue_counter == 0) ? 8'b0000_0001 : 8'b0;
//assign red = 8'b0000_0000;
//assign green = 8'b1;
//assign blue = 8'b0;
//assign blue = 8'b0000_0000;
endmodule |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 10; int n; pair<int, int> a[N]; pair<int, int> ra[N]; int ans[N]; pair<int, int> cross(pair<int, int> a, pair<int, int> b) { if (a > b) swap(a, b); return pair<int, int>(b.first, min(a.second, b.second)); } void solve() { ra[n] = pair<int, int>(a[n].first, a[n].first + a[n].second); for (int i = n - 1; i >= 1; i--) { ra[i] = cross(pair<int, int>(ra[i + 1].first - 1, ra[i + 1].second + 1), pair<int, int>(a[i].first, a[i].first + a[i].second)); if (ra[i].first > ra[i].second) { cout << -1 ; return; } } ans[1] = ra[1].second; for (int i = 2; i <= n; i++) { pair<int, int> cur = cross(pair<int, int>(ans[i - 1] - 1, ans[i - 1] + 1), ra[i]); ans[i] = cur.second; } long long sum = 0; for (int i = 1; i <= n; i++) sum += ans[i] - a[i].first; cout << sum << n ; for (int i = 1; i <= n; i++) cout << ans[i] << ; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d%d , &a[i].first, &a[i].second); solve(); } |
#include <bits/stdc++.h> using namespace std; int n, i, k, x; string s; int main() { cin >> n >> k >> s; for (i = 0; i < n; i++) { if (s[i] == # ) x++; else x = 0; if (x == k) { cout << NO ; return 0; } } cout << YES ; } |
`timescale 1ns / 1ps
/*
Group Members: Nikita Eisenhauer and Warren Seto
Lab Name: Adder Design
Design Description: Verilog test fixture to test the 64-bit look ahead adder
*/
module look_ahead_adder_test;
// Inputs
reg [63:0] A;
reg [63:0] B;
// Outputs
wire [63:0] SUM;
wire CARRY;
// Instantiate two counter variables for the test loop
integer count;
integer count2;
// Instantiate the Unit Under Test (UUT)
look_ahead_adder_64 uut
(
.A(A),
.B(B),
.SUM(SUM),
.CARRY(CARRY)
);
initial begin
$monitor("%d + %d = %d and carry %d", A, B, SUM, CARRY);
// Iterate through all possible combination of 0-32
count = 0;
count2 = 0;
A = 0;
B = 0;
// Loops over the possible combinations for the inputs A and B
for (count = 0; count <= 32; count = count + 1) begin
{A} = count;
for (count2 = 0; count2 <= 32; count2 = count2 + 1) begin
{B} = count2;
#1;
end
end
end
initial #4000 $finish; // The test will run for a total interval of 4000 nanoseconds
endmodule
|
#include <bits/stdc++.h> using namespace std; int mod = 998244353; const int M = 2e5 + 10; const int N = 5e2 + 10; inline long long read() { long long b = 1, sum = 0; char c = getchar(); while (!isdigit(c)) { if (c == - ) b = -1; c = getchar(); } while (isdigit(c)) { sum = sum * 10 + c - 0 ; c = getchar(); } return b * sum; } int hs, gs; int n, m, k, T; int h, g, a[1 << 22]; long long sum; vector<int> ans; void change(int x) { int l = 2 * x, r = 2 * x + 1; if (a[l] == 0 && a[r] == 0) { a[x] = 0; } else { if (a[l] > a[r]) { a[x] = a[l]; change(l); } else { a[x] = a[r]; change(r); } } } int pull(int x) { int l = 2 * x, r = 2 * x + 1; if (a[l] == 0 && a[r] == 0) { return x; } else { if (a[l] > a[r]) { return pull(l); } else { return pull(r); } } } void solv(int x) { if (a[x] == 0) return; int l = 2 * x, r = 2 * x + 1; while (pull(x) >= gs) { ans.push_back(x); sum -= a[x]; change(x); } solv(l); solv(r); } int main() { int i, j; T = read(); while (T--) { sum = 0; h = read(), g = read(); hs = (1 << h); gs = (1 << g); n = hs - gs; for (i = 1; i <= hs - 1; i++) { a[i] = read(); a[i + n] = a[i + 2 * n] = 0; sum += a[i]; } ans.clear(); solv(1); printf( %lld n , sum); for (i = 0; i < ans.size(); i++) { printf( %d , ans[i]); } printf( n ); } return 0; } |
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2009 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module writes data to the Audio DAC on the Altera DE1 board. *
* *
******************************************************************************/
module Altera_UP_Audio_Out_Serializer (
// Inputs
clk,
reset,
bit_clk_rising_edge,
bit_clk_falling_edge,
left_right_clk_rising_edge,
left_right_clk_falling_edge,
left_channel_data,
left_channel_data_en,
right_channel_data,
right_channel_data_en,
// Bidirectionals
// Outputs
left_channel_fifo_write_space,
right_channel_fifo_write_space,
serial_audio_out_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter AUDIO_DATA_WIDTH = 16;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input bit_clk_rising_edge;
input bit_clk_falling_edge;
input left_right_clk_rising_edge;
input left_right_clk_falling_edge;
input [AUDIO_DATA_WIDTH:1] left_channel_data;
input left_channel_data_en;
input [AUDIO_DATA_WIDTH:1] right_channel_data;
input right_channel_data_en;
// Bidirectionals
// Outputs
output reg [7:0] left_channel_fifo_write_space;
output reg [7:0] right_channel_fifo_write_space;
output reg serial_audio_out_data;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
wire read_left_channel;
wire read_right_channel;
wire left_channel_fifo_is_empty;
wire right_channel_fifo_is_empty;
wire left_channel_fifo_is_full;
wire right_channel_fifo_is_full;
wire [6:0] left_channel_fifo_used;
wire [6:0] right_channel_fifo_used;
wire [AUDIO_DATA_WIDTH:1] left_channel_from_fifo;
wire [AUDIO_DATA_WIDTH:1] right_channel_from_fifo;
// Internal Registers
reg left_channel_was_read;
reg [AUDIO_DATA_WIDTH:1] data_out_shift_reg;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
left_channel_fifo_write_space <= 8'h00;
else
left_channel_fifo_write_space <= 8'h80 - {left_channel_fifo_is_full,left_channel_fifo_used};
end
always @(posedge clk)
begin
if (reset == 1'b1)
right_channel_fifo_write_space <= 8'h00;
else
right_channel_fifo_write_space <= 8'h80 - {right_channel_fifo_is_full,right_channel_fifo_used};
end
always @(posedge clk)
begin
if (reset == 1'b1)
serial_audio_out_data <= 1'b0;
else
serial_audio_out_data <= data_out_shift_reg[AUDIO_DATA_WIDTH];
end
always @(posedge clk)
begin
if (reset == 1'b1)
left_channel_was_read <= 1'b0;
else if (read_left_channel)
left_channel_was_read <=1'b1;
else if (read_right_channel)
left_channel_was_read <=1'b0;
end
always @(posedge clk)
begin
if (reset == 1'b1)
data_out_shift_reg <= {AUDIO_DATA_WIDTH{1'b0}};
else if (read_left_channel)
data_out_shift_reg <= left_channel_from_fifo;
else if (read_right_channel)
data_out_shift_reg <= right_channel_from_fifo;
else if (left_right_clk_rising_edge | left_right_clk_falling_edge)
data_out_shift_reg <= {AUDIO_DATA_WIDTH{1'b0}};
else if (bit_clk_falling_edge)
data_out_shift_reg <=
{data_out_shift_reg[(AUDIO_DATA_WIDTH - 1):1], 1'b0};
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
assign read_left_channel = left_right_clk_rising_edge &
~left_channel_fifo_is_empty &
~right_channel_fifo_is_empty;
assign read_right_channel = left_right_clk_falling_edge &
left_channel_was_read;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
Altera_UP_SYNC_FIFO Audio_Out_Left_Channel_FIFO(
// Inputs
.clk (clk),
.reset (reset),
.write_en (left_channel_data_en & ~left_channel_fifo_is_full),
.write_data (left_channel_data),
.read_en (read_left_channel),
// Bidirectionals
// Outputs
.fifo_is_empty (left_channel_fifo_is_empty),
.fifo_is_full (left_channel_fifo_is_full),
.words_used (left_channel_fifo_used),
.read_data (left_channel_from_fifo)
);
defparam
Audio_Out_Left_Channel_FIFO.DATA_WIDTH = AUDIO_DATA_WIDTH,
Audio_Out_Left_Channel_FIFO.DATA_DEPTH = 128,
Audio_Out_Left_Channel_FIFO.ADDR_WIDTH = 7;
Altera_UP_SYNC_FIFO Audio_Out_Right_Channel_FIFO(
// Inputs
.clk (clk),
.reset (reset),
.write_en (right_channel_data_en & ~right_channel_fifo_is_full),
.write_data (right_channel_data),
.read_en (read_right_channel),
// Bidirectionals
// Outputs
.fifo_is_empty (right_channel_fifo_is_empty),
.fifo_is_full (right_channel_fifo_is_full),
.words_used (right_channel_fifo_used),
.read_data (right_channel_from_fifo)
);
defparam
Audio_Out_Right_Channel_FIFO.DATA_WIDTH = AUDIO_DATA_WIDTH,
Audio_Out_Right_Channel_FIFO.DATA_DEPTH = 128,
Audio_Out_Right_Channel_FIFO.ADDR_WIDTH = 7;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mod = 1000003; long double pi = 3.1415926536; const int mx = 1000003; long long gcd(long long x, long long y) { if (y == 0) return x; return gcd(y, x % y); } long long bp(long long a, long long b) { long long ans = 1; while (b > 0) { if (b & 1) ans = (ans * a) % mod; a = (a * a) % mod; b >>= 1; } return ans; } long long p(long long n) { for (long long i = 2; i * i <= n; i++) { if (n % i == 0) { return n / i; } } return 1; } void solve() { long long a, d, x, i = 1; cin >> a >> d; x = a++; while ((a % i) <= d) { x = (a - (a % i)); i *= 10; } cout << x - 1; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); solve(); } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2005 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc = 0;
reg [7:0] crc;
reg [223:0] sum;
wire [255:0] mglehy = {32{~crc}};
wire [215:0] drricx = {27{crc}};
wire [15:0] apqrli = {2{~crc}};
wire [2:0] szlfpf = crc[2:0];
wire [15:0] dzosui = {2{crc}};
wire [31:0] zndrba = {16{crc[1:0]}};
wire [223:0] bxiouf;
vliw vliw (
// Outputs
.bxiouf (bxiouf),
// Inputs
.mglehy (mglehy[255:0]),
.drricx (drricx[215:0]),
.apqrli (apqrli[15:0]),
.szlfpf (szlfpf[2:0]),
.dzosui (dzosui[15:0]),
.zndrba (zndrba[31:0]));
always @ (posedge clk) begin
cyc <= cyc + 1;
crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
if (cyc==0) begin
// Setup
crc <= 8'hed;
sum <= 224'h0;
end
else if (cyc<90) begin
//$write("[%0t] cyc==%0d BXI=%x\n", $time, cyc, bxiouf);
sum <= {sum[222:0],sum[223]} ^ bxiouf;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%b %x\n", $time, cyc, crc, sum);
if (crc !== 8'b01110000) $stop;
if (sum !== 224'h1fdff998855c3c38d467e28124847831f9ad6d4a09f2801098f032a8) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module vliw (
input[255:0] mglehy,
input[215:0] drricx,
input[15:0] apqrli,
input[2:0] szlfpf,
input[15:0] dzosui,
input[31:0] zndrba,
output wire [223:0] bxiouf
);
wire [463:0] zhknfc = ({29{~apqrli}} & {mglehy, drricx[215:8]})
| ({29{apqrli}} & {mglehy[247:0], drricx});
wire [335:0] umntwz = ({21{~dzosui}} & zhknfc[463:128])
| ({21{dzosui}} & zhknfc[335:0]);
wire [335:0] viuvoc = umntwz << {szlfpf, 4'b0000};
wire [223:0] rzyeut = viuvoc[335:112];
assign bxiouf = {rzyeut[7:0],
rzyeut[15:8],
rzyeut[23:16],
rzyeut[31:24],
rzyeut[39:32],
rzyeut[47:40],
rzyeut[55:48],
rzyeut[63:56],
rzyeut[71:64],
rzyeut[79:72],
rzyeut[87:80],
rzyeut[95:88],
rzyeut[103:96],
rzyeut[111:104],
rzyeut[119:112],
rzyeut[127:120],
rzyeut[135:128],
rzyeut[143:136],
rzyeut[151:144],
rzyeut[159:152],
rzyeut[167:160],
rzyeut[175:168],
rzyeut[183:176],
rzyeut[191:184],
rzyeut[199:192],
rzyeut[207:200],
rzyeut[215:208],
rzyeut[223:216]};
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// AXI4LiteSlaveInterfaceWriteChannel for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Kibin Park <>
// Yong Ho Song <>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Kibin Park <>
//
// Project Name: Cosmos OpenSSD
// Design Name: AXI4Lite slave interface write channel
// Module Name: AXI4LiteSlaveInterfaceWriteChannel
// File Name: AXI4LiteSlaveInterfaceWriteChannel.v
//
// Version: v1.0.0
//
// Description: Write channel control for AXI4-Lite compliant slave interface
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module AXI4LiteSlaveInterfaceWriteChannel
#
(
parameter AddressWidth = 32,
parameter DataWidth = 32
)
(
ACLK ,
ARESETN ,
AWVALID ,
AWREADY ,
AWADDR ,
AWPROT ,
WVALID ,
WREADY ,
WDATA ,
WSTRB ,
BVALID ,
BREADY ,
BRESP ,
oWriteAddress ,
oWriteData ,
oWriteValid ,
iWriteAck
);
input ACLK ;
input ARESETN ;
input AWVALID ;
output AWREADY ;
input [AddressWidth - 1:0] AWADDR ;
input [2:0] AWPROT ;
input WVALID ;
output WREADY ;
input [DataWidth - 1:0] WDATA ;
input [DataWidth/8 - 1:0] WSTRB ;
output BVALID ;
input BREADY ;
output [1:0] BRESP ;
output [AddressWidth - 1:0] oWriteAddress ;
output [DataWidth - 1:0] oWriteData ;
output oWriteValid ;
input iWriteAck ;
reg [AddressWidth - 1:0] rWriteAddress ;
reg [DataWidth - 1:0] rWriteData ;
localparam State_Idle = 2'b00;
localparam State_INCMDREQ = 2'b01;
localparam State_AXIWRESP = 2'b11;
reg [1:0] rCurState ;
reg [1:0] rNextState ;
always @ (posedge ACLK)
if (!ARESETN)
rCurState <= State_Idle;
else
rCurState <= rNextState;
always @ (*)
case (rCurState)
State_Idle:
rNextState <= (AWVALID && WVALID)?State_INCMDREQ:State_Idle;
State_INCMDREQ:
rNextState <= (iWriteAck)?State_AXIWRESP:State_INCMDREQ;
State_AXIWRESP:
rNextState <= (BREADY)?State_Idle:State_AXIWRESP;
default:
rNextState <= State_Idle;
endcase
assign AWREADY = ((rCurState == State_INCMDREQ) && iWriteAck);
assign WREADY = ((rCurState == State_INCMDREQ) && iWriteAck);
assign oWriteValid = (rCurState == State_INCMDREQ);
always @ (posedge ACLK)
if (!ARESETN)
rWriteAddress <= {(AddressWidth){1'b0}};
else
if (AWVALID)
rWriteAddress <= AWADDR;
always @ (posedge ACLK)
if (!ARESETN)
rWriteData <= {(DataWidth){1'b0}};
else
if (WVALID)
rWriteData <= WDATA;
assign oWriteAddress = rWriteAddress;
assign oWriteData = rWriteData;
assign BVALID = (rCurState == State_AXIWRESP);
assign BRESP = 2'b0;
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename A, typename B> inline void chmin(A &a, B b) { if (a > b) a = b; } template <typename A, typename B> inline void chmax(A &a, B b) { if (a < b) a = b; } struct UnionFindTree { vector<long long> par, sz; UnionFindTree(long long n) { par.resize(n); sz.resize(n); for (long long i = 0; i < n; i++) { par[i] = i; sz[i] = 1; } } long long find(long long x) { return x == par[x] ? x : par[x] = find(par[x]); } void unite(long long x, long long y) { x = find(x); y = find(y); if (x == y) return; if (sz[x] < sz[y]) swap(x, y); sz[x] += sz[y]; par[y] = x; } bool areSame(long long x, long long y) { return find(x) == find(y); } long long size(long long x) { return sz[find(x)]; } }; const long long SIZE = 1000000; long long N, M; long long A[SIZE], B[SIZE]; long long cnt[SIZE]; signed main() { scanf( %lld%lld , &N, &M); for (long long i = 0; i < (M); i++) scanf( %lld%lld , &A[i], &B[i]); vector<long long> vs; for (long long i = 0; i < (M); i++) { vs.push_back(A[i]); vs.push_back(B[i]); } sort((vs).begin(), (vs).end()); vs.erase(unique((vs).begin(), (vs).end()), vs.end()); for (long long i = 0; i < (M); i++) { A[i] = lower_bound((vs).begin(), (vs).end(), A[i]) - vs.begin(); B[i] = lower_bound((vs).begin(), (vs).end(), B[i]) - vs.begin(); } N = vs.size(); UnionFindTree uf(N); for (long long i = 0; i < (M); i++) uf.unite(A[i], B[i]); if (uf.size(0) != N) { puts( 0 ); return 0; } long long luz = 0; for (long long i = 0; i < (M); i++) { if (A[i] == B[i]) luz++; else { cnt[A[i]]++; cnt[B[i]]++; } } long long ans = 0; ans += luz * (M - luz); ans += luz * (luz - 1) / 2; for (long long i = 0; i < N; i++) ans += cnt[i] * (cnt[i] - 1) / 2; cout << ans << endl; return 0; } |
(** * Extraction: Extracting ML from Coq *)
(* $Date: 2013-01-16 20:29:57 -0700 (Wed, 16 Jan 2013) $ *)
(** * Basic Extraction *)
(** In its simplest form, program extraction from Coq is completely straightforward. *)
(** First we say what language we want to extract into. Options are OCaml (the
most mature), Haskell (which mostly works), and Scheme (a bit out
of date). *)
Extraction Language Ocaml.
(** Now we load up the Coq environment with some definitions, either
directly or by importing them from other modules. *)
Require Import SfLib.
Require Import ImpCEvalFun.
(** Finally, we tell Coq the name of a definition to extract and the
name of a file to put the extracted code into. *)
Extraction "imp1.ml" ceval_step.
(** When Coq processes this command, it generates a file [imp1.ml]
containing an extracted version of [ceval_step], together with
everything that it recursively depends on. Have a look at this
file now. *)
(* ############################################################## *)
(** * Controlling Extraction of Specific Types *)
(** We can tell Coq to extract certain [Inductive] definitions to
specific OCaml types. For each one, we must say
- how the Coq type itself should be represented in OCaml, and
- how each constructor should be translated. *)
Extract Inductive bool => "bool" [ "true" "false" ].
(** Also, for non-enumeration types (where the constructors take
arguments), we give an OCaml expression that can be used as a
"recursor" over elements of the type. (Think Church numerals.) *)
Extract Inductive nat => "int"
[ "0" "(fun x -> x + 1)" ]
"(fun zero succ n ->
if n=0 then zero () else succ (n-1))".
(** We can also extract defined constants to specific OCaml terms or
operators. *)
Extract Constant plus => "( + )".
Extract Constant mult => "( * )".
Extract Constant beq_nat => "( = )".
(** Important: It is entirely _your responsibility_ to make sure that
the translations you're proving make sense. For example, it might
be tempting to include this one
Extract Constant minus => "( - )".
but doing so could lead to serious confusion! (Why?)
*)
Extraction "imp2.ml" ceval_step.
(** Have a look at the file [imp2.ml]. Notice how the fundamental
definitions have changed from [imp1.ml]. *)
(* ############################################################## *)
(** * A Complete Example *)
(** To use our extracted evaluator to run Imp programs, all we need to
add is a tiny driver program that calls the evaluator and somehow
prints out the result.
For simplicity, we'll print results by dumping out the first four
memory locations in the final state.
Also, to make it easier to type in examples, let's extract a
parser from the [ImpParser] Coq module. To do this, we need a few
more declarations to set up the right correspondence between Coq
strings and lists of OCaml characters. *)
Require Import Ascii String.
Extract Inductive ascii => char
[
"(* If this appears, you're using Ascii internals. Please don't *) (fun (b0,b1,b2,b3,b4,b5,b6,b7) -> let f b i = if b then 1 lsl i else 0 in Char.chr (f b0 0 + f b1 1 + f b2 2 + f b3 3 + f b4 4 + f b5 5 + f b6 6 + f b7 7))"
]
"(* If this appears, you're using Ascii internals. Please don't *) (fun f c -> let n = Char.code c in let h i = (n land (1 lsl i)) <> 0 in f (h 0) (h 1) (h 2) (h 3) (h 4) (h 5) (h 6) (h 7))".
Extract Constant zero => "'\000'".
Extract Constant one => "'\001'".
Extract Constant shift =>
"fun b c -> Char.chr (((Char.code c) lsl 1) land 255 + if b then 1 else 0)".
Extract Inlined Constant ascii_dec => "(=)".
(** We also need one more variant of booleans. *)
Extract Inductive sumbool => "bool" ["true" "false"].
(** The extraction is the same as always. *)
Require Import Imp.
Require Import ImpParser.
Extraction "imp.ml" empty_state ceval_step parse.
(** Now let's run our generated Imp evaluator. First, have a look at
[impdriver.ml]. (This was written by hand, not extracted.)
Next, compile the driver together with the extracted code and
execute it, as follows.
<<
ocamlc -w -20 -w -26 -o impdriver imp.mli imp.ml impdriver.ml
./impdriver
>>
(The [-w] flags to [ocamlc] are just there to suppress a few
spurious warnings.) *)
(* ############################################################## *)
(** * Discussion *)
(** Since we've proved that the [ceval_step] function behaves the same
as the [ceval] relation in an appropriate sense, the extracted
program can be viewed as a _certified_ Imp interpreter. (Of
course, the parser is not certified in any interesting sense,
since we didn't prove anything about it.) *)
|
#include <bits/stdc++.h> int main() { int i, n, k; scanf( %d %d , &n, &k); int a[n]; int count = 0, j = 0; for (i = 0; i < n; i++) { scanf( %d , &a[i]); } for (i = 0; i < n; i++) { if (a[i] <= k) count++; else { j = 1; break; } } if (j != 0) { for (i = n - 1; i >= 0; i--) { if (a[i] <= k) count++; else break; } } printf( %d n , count); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; vector<long long> v[N]; long long vis[N]; long long col[N]; set<long long> che; void dfs(long long x) { vis[x] = 1; che.insert(x); for (auto it : v[x]) { if (!vis[it]) { dfs(it); } } } void solve() { long long n; cin >> n; long long i, x, y; vector<pair<long long, long long> > e, spe; for (i = 0; i < n - 1; i++) { cin >> x >> y; x--, y--; e.push_back(make_pair(x, y)); } for (i = 0; i < n; i++) { cin >> col[i]; } for (auto it : e) { if (col[it.first] != col[it.second]) { spe.push_back(make_pair(it.first, it.second)); } } long long m = spe.size(); long long f = 0, ind = 0; long long cnt[n]; memset(cnt, 0, sizeof(cnt)); if (m == 0) { cout << YES n1 ; return; } for (auto it : spe) { cnt[it.first]++; cnt[it.second]++; } for (i = 0; i < n; i++) { if (cnt[i] == m) { cout << YES n << i + 1; return; } } cout << NO n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); if (fopen( input.txt , r )) { freopen( input.txt , r , stdin); freopen( output.txt , w , stdout); } long long t = 1; while (t--) { solve(); } return 0; } |
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_design_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "nios_design_onchip_memory2_0.hex";
output [ 31: 0] readdata;
input [ 15: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [ 31: 0] writedata;
wire clocken0;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 50350,
the_altsyncram.numwords_a = 50350,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 16;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
#include <bits/stdc++.h> using namespace std; void solve() { int n; std::cin >> n; std::vector<int> v(101); for (int i = 0; i < n; ++i) { int temp; std::cin >> temp; v[temp]++; } int mex_A = -1; int mex_B = -1; bool flag1 = 1; for (int i = 0; i < n; ++i) { if (v[i] > 1 && flag1) { mex_A = mex_B = i; } else if (v[i] >= 1) { mex_A = i; flag1 = 0; } else if (v[i] == 0) { break; } } std::cout << ++mex_A + ++mex_B << n ; } int main() { int x; cin >> x; while (x--) solve(); return 0; } |
/*
Copyright (c) 2016-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* Generic source synchronous SDR input
*/
module ssio_sdr_in #
(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// Clock input style ("BUFG", "BUFR", "BUFIO", "BUFIO2")
// Use BUFR for Virtex-5, Virtex-6, 7-series
// Use BUFG for Ultrascale
// Use BUFIO2 for Spartan-6
parameter CLOCK_INPUT_STYLE = "BUFIO2",
// Width of register in bits
parameter WIDTH = 1
)
(
input wire input_clk,
input wire [WIDTH-1:0] input_d,
output wire output_clk,
output wire [WIDTH-1:0] output_q
);
wire clk_int;
wire clk_io;
generate
if (TARGET == "XILINX") begin
// use Xilinx clocking primitives
if (CLOCK_INPUT_STYLE == "BUFG") begin
// buffer RX clock
BUFG
clk_bufg (
.I(input_clk),
.O(clk_int)
);
// pass through RX clock to logic and input buffers
assign clk_io = clk_int;
assign output_clk = clk_int;
end else if (CLOCK_INPUT_STYLE == "BUFR") begin
assign clk_int = input_clk;
// pass through RX clock to input buffers
BUFIO
clk_bufio (
.I(clk_int),
.O(clk_io)
);
// pass through RX clock to logic
BUFR #(
.BUFR_DIVIDE("BYPASS")
)
clk_bufr (
.I(clk_int),
.O(output_clk),
.CE(1'b1),
.CLR(1'b0)
);
end else if (CLOCK_INPUT_STYLE == "BUFIO") begin
assign clk_int = input_clk;
// pass through RX clock to input buffers
BUFIO
clk_bufio (
.I(clk_int),
.O(clk_io)
);
// pass through RX clock to MAC
BUFG
clk_bufg (
.I(clk_int),
.O(output_clk)
);
end else if (CLOCK_INPUT_STYLE == "BUFIO2") begin
// pass through RX clock to input buffers
BUFIO2 #(
.DIVIDE(1),
.DIVIDE_BYPASS("TRUE"),
.I_INVERT("FALSE"),
.USE_DOUBLER("FALSE")
)
clk_bufio (
.I(input_clk),
.DIVCLK(clk_int),
.IOCLK(clk_io),
.SERDESSTROBE()
);
// pass through RX clock to MAC
BUFG
clk_bufg (
.I(clk_int),
.O(output_clk)
);
end
end else begin
// pass through RX clock to input buffers
assign clk_io = input_clk;
// pass through RX clock to logic
assign clk_int = input_clk;
assign output_clk = clk_int;
end
endgenerate
(* IOB = "TRUE" *)
reg [WIDTH-1:0] output_q_reg = {WIDTH{1'b0}};
assign output_q = output_q_reg;
always @(posedge clk_io) begin
output_q_reg <= input_d;
end
endmodule
`resetall
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MUX2_4_V
`define SKY130_FD_SC_LP__MUX2_4_V
/**
* mux2: 2-input multiplexer.
*
* Verilog wrapper for mux2 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__mux2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux2_4 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux2_4 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__MUX2_4_V
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { return b == 0 ? a : gcd(b, a % b); } long long qpow(long long a, long long b, long long m) { long long r = 1; a %= m; for (; b; b >>= 1) { if (b & 1) r = r * a % m; a = a * a % m; } return r; } const int inf = 0x7fffffff; const int maxn = 2e5 + 10; vector<pair<int, int> > g[maxn]; vector<int> ans; set<pair<int, int> > s; int n, k; int main() { ios::sync_with_stdio(false); cin >> n >> k; for (int i = 1; i <= n; i++) { int l, r; cin >> l >> r; g[l].push_back(pair<int, int>(r, i)); } for (int i = 1; i <= 200000; i++) { for (int j = 0; j < (int)(g[i]).size(); j++) s.insert(g[i][j]); while ((int)(s).size() > k) { set<pair<int, int> >::iterator it = s.end(); it--; ans.push_back(it->second); s.erase(it); } while (!s.empty() && (s.begin()->first) <= i) s.erase(s.begin()); } cout << (int)(ans).size() << endl; for (int i = 0; i < (int)(ans).size(); i++) { if (i) cout << ; cout << ans[i]; } cout << endl; return 0; } |
// $Id: c_scatter.v 5188 2012-08-30 00:31:31Z dub $
/*
Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// spread out bit vector into larger vector
//==============================================================================
module c_scatter
(data_in, dest_in, data_out);
// width of output data
parameter out_width = 32;
// population count function (count ones)
function integer pop_count(input [0:out_width-1] argument);
integer i;
begin
pop_count = 0;
for(i = 0; i < out_width; i = i + 1)
pop_count = pop_count + argument[i];
end
endfunction
// mask indicating at which positions to put the input vector's bits
parameter [0:out_width-1] mask = {out_width{1'b1}};
// width of input vector
localparam in_width = pop_count(mask);
// input vector
input [0:in_width-1] data_in;
// destination vector
input [0:out_width-1] dest_in;
// result
output [0:out_width-1] data_out;
reg [0:out_width-1] data_out;
integer idx1, idx2;
always @(data_in)
begin
idx2 = 0;
for(idx1 = 0; idx1 < out_width; idx1 = idx1 + 1)
if(mask[idx1] == 1'b1)
begin
data_out[idx1] = data_in[idx2];
idx2 = idx2 + 1;
end
else
data_out[idx1] = dest_in[idx1];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; inline int readInt() { char c; int tmp = 0, x = 1; c = getchar(); while (c > 9 || c < 0 ) { if (c == - ) x = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { tmp = tmp * 10 + c - 0 ; c = getchar(); } return tmp * x; } const int maxN = 2000 + 10; const int maxM = 100000 + 10; int Head[maxN], eg[maxM << 1], nxt[maxM << 1], tot = 1; void addEdge(int u, int v) { eg[++tot] = v; nxt[tot] = Head[u]; Head[u] = tot; eg[++tot] = u; nxt[tot] = Head[v]; Head[v] = tot; } bool isbri[maxM << 2]; int dfn[maxN], low[maxN], dfsclock = 0; void tarjan(int v, int InEdge) { dfn[v] = low[v] = ++dfsclock; for (int i = Head[v]; i; i = nxt[i]) { int u = eg[i]; if (!dfn[u]) { tarjan(u, i); low[v] = min(low[v], low[u]); if (low[u] > dfn[v]) isbri[i] = isbri[i ^ 1] = true; } else if (i != (InEdge ^ 1)) low[v] = min(low[v], dfn[u]); } } int bccno[maxN], num = 0, bccsiz[maxN]; void dfs(int v) { bccno[v] = num; bccsiz[num]++; for (int i = Head[v]; i; i = nxt[i]) { int u = eg[i]; if (!bccno[u] && !isbri[i]) dfs(u); } } vector<int> g[maxN]; void new_addEdge(int u, int v) { g[u].push_back(v); g[v].push_back(u); } bool vis[maxN], isLeaf[maxN]; int tmp = 0, tmpmax = -1, tmpleaf = 0, Leaf[maxN], siz[maxN], rot[maxN], cnt = 0, Fa[maxN], Belong[maxN]; void predfs(int v, int fa) { siz[v] = 1; Fa[v] = fa; Belong[v] = cnt; if ((int)g[v].size() == 0 || (int)g[v].size() == 1) Leaf[cnt]++, isLeaf[v] = true; for (int i = 0; i < (int)g[v].size(); i++) { int u = g[v][i]; if (u != fa) predfs(u, v), siz[v] += siz[u]; } } void FindLongest(int v, int fa, int D, int lev) { if (tmp < D) tmp = D, tmpmax = v, tmpleaf = lev; for (int i = 0; i < (int)g[v].size(); i++) { int u = g[v][i]; if (u != fa) FindLongest(u, v, D + (!isLeaf[u]), lev + isLeaf[u]); } } int FindDiameter(int v) { tmp = 0, tmpmax = -1; for (int i = 0; i < (int)g[v].size(); i++) { int u = g[v][i]; FindLongest(u, v, 1, 0); } if (!(~tmpmax)) return 0; int vv = tmpmax; tmp = 0, tmpmax = -1, tmpleaf = 0; FindLongest(vv, -1, 1, isLeaf[vv]); return tmp - tmpleaf; } int n, m; int main() { n = readInt(), m = readInt(); int u, v; for (int i = 1; i <= m; i++) { u = readInt(), v = readInt(); addEdge(u, v); } for (int i = 1; i <= n; i++) { if (!dfn[i]) tarjan(i, 0); } for (int i = 1; i <= n; i++) { if (!bccno[i]) { num++; dfs(i); } } for (int i = 2; i <= tot; i += 2) { if (bccno[eg[i]] != bccno[eg[i ^ 1]]) { new_addEdge(bccno[eg[i]], bccno[eg[i ^ 1]]); } } int ans = 0; for (int i = 1; i <= num; i++) ans += bccsiz[i] - 1; cnt = 0; for (int i = 1; i <= num; i++) { if (!Belong[i]) cnt++, rot[cnt] = i, predfs(i, -1); } ans += cnt - 1; for (int i = 1; i <= cnt; i++) { int d = FindDiameter(rot[i]); ans += siz[rot[i]] - d - Leaf[i]; } printf( %d n , ans); return 0; } |
Subsets and Splits