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#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; string s; cin >> s; int rc = 0, uc = 0, c = 0; for (int i = 0; i < n; i++) { if (s[i] == R ) rc++; else uc++; if (rc == uc && s[i] == s[i + 1]) c++; } cout << c << n ; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__OR2_BEHAVIORAL_PP_V
/**
* or2: 2-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__or2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out_X , B, A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR2_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> const int INF = 0x3f3f3f3f; const int maxn = 1e5 + 50; const int Mod = 1e6 + 3; using namespace std; const char YES[] = YES , NO[] = NO ; int n; int s[maxn]; bool find(int &st) { st = n - 2; if (st <= 0) return false; while (st > 0 && s[st] != 0) st--; return st > 0; } void solve() { if (s[n] == 1) { puts(NO); return; } if (n == 1 || s[n - 1] == 1) { puts(YES); for (int i = 1; i < n + 1; i++) { if (i == 1) printf( %d , s[i]); else printf( ->%d , s[i]); } puts( ); return; } int pos; if (!find(pos)) { puts(NO); return; } puts(YES); for (int i = 1; i < pos; i++) { if (i == 1) printf( %d , s[i]); else printf( ->%d , s[i]); } for (int i = pos; i < n + 1; i++) { if (i == n) printf( ))->%d , s[i]); else if (i == pos || i == pos + 1) { if (i == pos && pos == 1) printf( (%d , s[i]); else printf( ->(%d , s[i]); } else printf( ->%d , s[i]); } puts( ); } int main() { while (scanf( %d , &n) != EOF) { for (int i = 1; i < n + 1; i++) { scanf( %d , s + i); } solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; inline void proc_status() { ifstream t( /proc/self/status ); cerr << string(istreambuf_iterator<char>(t), istreambuf_iterator<char>()) << endl; } template <typename T> inline bool chkmin(T &a, const T &b) { return a > b ? a = b, 1 : 0; } template <typename T> inline bool chkmax(T &a, const T &b) { return a < b ? a = b, 1 : 0; } template <typename T> inline T read() { register T sum(0), fg(1); register char ch(getchar()); for (; !isdigit(ch); ch = getchar()) if (ch == - ) fg = -1; for (; isdigit(ch); ch = getchar()) sum = sum * 10 - 0 + ch; return sum * fg; } const int MOD = (int)1e9 + 7; const int MAXN = (int)1e6; int n; char s0[MAXN + 5]; inline void input() { scanf( %s , s0 + 1), n = strlen(s0 + 1); } namespace PAM { const int MAX_NODE = MAXN * 2, alpha = 26; int fail[MAX_NODE + 5], trans[MAX_NODE + 5][alpha], nxt[MAX_NODE + 5], cnt; int len[MAX_NODE + 5], delta[MAX_NODE + 5]; int rt0, rt1, lst; int S[MAX_NODE + 5], N = 0; inline void init() { S[0] = -1; cnt = 1, lst = 0; memset(trans[0], 0, sizeof trans[0]); memset(trans[1], 0, sizeof trans[1]); len[0] = 0, len[1] = -1; fail[0] = 1; } inline int new_node(int l) { len[++cnt] = l; fail[cnt] = 0; memset(trans[cnt], 0, sizeof trans[cnt]); return cnt; } inline int extend(int ch) { int p = lst; S[++N] = ch; while (S[N - len[p] - 1] != S[N]) p = fail[p]; int np = -1; if (!trans[p][ch]) { np = new_node(len[p] + 2); int t = fail[p]; while (S[N - len[t] - 1] != S[N]) t = fail[t]; fail[np] = trans[t][ch]; delta[np] = len[np] - len[fail[np]]; nxt[np] = delta[np] == delta[fail[np]] ? nxt[fail[np]] : fail[np]; trans[p][ch] = np; } else np = trans[p][ch]; return lst = np; } } // namespace PAM inline void solve() { static int s[MAXN + 5]; for (int i = 1; i <= n / 2; ++i) { s[i * 2 - 1] = s0[i] - a ; s[i * 2] = s0[n - i + 1] - a ; } static int nd[MAXN + 5]; PAM::init(); for (int i = 1; i <= n; ++i) nd[i] = PAM::extend(s[i]); static int f[MAXN + 5], g[MAXN + 5]; f[0] = 1; for (int i = 1; i <= n; ++i) for (int p = nd[i]; p; p = PAM::nxt[p]) { g[p] = f[i - PAM::len[PAM::nxt[p]] - PAM::delta[p]]; if (PAM::delta[p] == PAM::delta[PAM::fail[p]]) (g[p] += g[PAM::fail[p]]) %= MOD; if (i % 2 == 0) (f[i] += g[p]) %= MOD; } printf( %d n , (f[n] + MOD) % MOD); } int main() { input(); solve(); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:55:04 12/14/2010
// Design Name:
// Module Name: msu
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module msu(
input clkin,
input enable,
input [13:0] pgm_address,
input [7:0] pgm_data,
input pgm_we,
input [2:0] reg_addr,
input [7:0] reg_data_in,
output [7:0] reg_data_out,
input reg_oe_falling,
input reg_oe_rising,
input reg_we_rising,
output [7:0] status_out,
output [7:0] volume_out,
output volume_latch_out,
output [31:0] addr_out,
output [15:0] track_out,
input [5:0] status_reset_bits,
input [5:0] status_set_bits,
input status_reset_we,
input [13:0] msu_address_ext,
input msu_address_ext_write,
output DBG_msu_reg_oe_rising,
output DBG_msu_reg_oe_falling,
output DBG_msu_reg_we_rising,
output [13:0] DBG_msu_address,
output DBG_msu_address_ext_write_rising
);
reg [1:0] status_reset_we_r;
always @(posedge clkin) status_reset_we_r = {status_reset_we_r[0], status_reset_we};
wire status_reset_en = (status_reset_we_r == 2'b01);
reg [13:0] msu_address_r;
wire [13:0] msu_address = msu_address_r;
initial msu_address_r = 13'b0;
wire [7:0] msu_data;
reg [7:0] msu_data_r;
reg [2:0] msu_address_ext_write_sreg;
always @(posedge clkin)
msu_address_ext_write_sreg <= {msu_address_ext_write_sreg[1:0], msu_address_ext_write};
wire msu_address_ext_write_rising = (msu_address_ext_write_sreg[2:1] == 2'b01);
reg [31:0] addr_out_r;
assign addr_out = addr_out_r;
reg [15:0] track_out_r;
assign track_out = track_out_r;
reg [7:0] volume_r;
assign volume_out = volume_r;
reg volume_start_r;
assign volume_latch_out = volume_start_r;
reg audio_start_r;
reg audio_busy_r;
reg data_start_r;
reg data_busy_r;
reg ctrl_start_r;
reg audio_error_r;
reg [2:0] audio_ctrl_r;
reg [1:0] audio_status_r;
initial begin
audio_busy_r = 1'b1;
data_busy_r = 1'b1;
audio_error_r = 1'b0;
volume_r = 8'h00;
addr_out_r = 32'h00000000;
track_out_r = 16'h0000;
data_start_r = 1'b0;
audio_start_r = 1'b0;
end
assign DBG_msu_address = msu_address;
assign DBG_msu_reg_oe_rising = reg_oe_rising;
assign DBG_msu_reg_oe_falling = reg_oe_falling;
assign DBG_msu_reg_we_rising = reg_we_rising;
assign DBG_msu_address_ext_write_rising = msu_address_ext_write_rising;
assign status_out = {msu_address_r[13], // 7
audio_start_r, // 6
data_start_r, // 5
volume_start_r, // 4
audio_ctrl_r, // 3:1
ctrl_start_r}; // 0
initial msu_address_r = 14'h1234;
`ifdef MK2
msu_databuf snes_msu_databuf (
.clka(clkin),
.wea(~pgm_we), // Bus [0 : 0]
.addra(pgm_address), // Bus [13 : 0]
.dina(pgm_data), // Bus [7 : 0]
.clkb(clkin),
.addrb(msu_address), // Bus [13 : 0]
.doutb(msu_data)
); // Bus [7 : 0]
`endif
`ifdef MK3
msu_databuf snes_msu_databuf (
.clock(clkin),
.wren(~pgm_we), // Bus [0 : 0]
.wraddress(pgm_address), // Bus [13 : 0]
.data(pgm_data), // Bus [7 : 0]
.rdaddress(msu_address), // Bus [13 : 0]
.q(msu_data)
); // Bus [7 : 0]
`endif
reg [7:0] data_out_r;
assign reg_data_out = data_out_r;
always @(posedge clkin) begin
if(msu_address_ext_write_rising)
msu_address_r <= msu_address_ext;
else if(reg_oe_rising & enable & (reg_addr == 3'h1)) begin
msu_address_r <= msu_address_r + 1;
end
end
always @(posedge clkin) begin
if(reg_oe_falling & enable)
case(reg_addr)
3'h0: data_out_r <= {data_busy_r, audio_busy_r, audio_status_r, audio_error_r, 3'b001};
3'h1: data_out_r <= msu_data;
3'h2: data_out_r <= 8'h53;
3'h3: data_out_r <= 8'h2d;
3'h4: data_out_r <= 8'h4d;
3'h5: data_out_r <= 8'h53;
3'h6: data_out_r <= 8'h55;
3'h7: data_out_r <= 8'h31;
endcase
end
always @(posedge clkin) begin
if(reg_we_rising & enable) begin
case(reg_addr)
3'h0: addr_out_r[7:0] <= reg_data_in;
3'h1: addr_out_r[15:8] <= reg_data_in;
3'h2: addr_out_r[23:16] <= reg_data_in;
3'h3: begin
addr_out_r[31:24] <= reg_data_in;
data_start_r <= 1'b1;
data_busy_r <= 1'b1;
end
3'h4: begin
track_out_r[7:0] <= reg_data_in;
end
3'h5: begin
track_out_r[15:8] <= reg_data_in;
audio_start_r <= 1'b1;
audio_busy_r <= 1'b1;
end
3'h6: begin
volume_r <= reg_data_in;
volume_start_r <= 1'b1;
end
3'h7: begin
if(!audio_busy_r) begin
audio_ctrl_r <= reg_data_in[2:0];
ctrl_start_r <= 1'b1;
end
end
endcase
end else if (status_reset_en) begin
audio_busy_r <= (audio_busy_r | status_set_bits[5]) & ~status_reset_bits[5];
if(status_reset_bits[5]) audio_start_r <= 1'b0;
data_busy_r <= (data_busy_r | status_set_bits[4]) & ~status_reset_bits[4];
if(status_reset_bits[4]) data_start_r <= 1'b0;
audio_error_r <= (audio_error_r | status_set_bits[3]) & ~status_reset_bits[3];
audio_status_r <= (audio_status_r | status_set_bits[2:1]) & ~status_reset_bits[2:1];
ctrl_start_r <= (ctrl_start_r | status_set_bits[0]) & ~status_reset_bits[0];
end else begin
volume_start_r <= 1'b0;
end
end
endmodule
|
//======================================================================
//
// poly1305.v
// ----------
// Poly1305 Verilog behavioral model.
//
//
// Copyright (c) 2016, Secworks Sweden AB
// Joachim Strömbergson
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module poly1305();
// Global Poly1305 state registers.
reg [127 : 0] r_reg;
reg [127 : 0] s_reg;
reg [129 : 0] acc_reg;
reg [127 : 0] tag_reg;
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam R_CLAMP = 128'h0ffffffc0ffffffc0ffffffc0fffffff;
localparam POLY1305 = 130'h3fffffffffffffffffffffffffffffffb;
//----------------------------------------------------------------
// poly1305_init()
//
// Initialize the internal Poly1305 state.
//----------------------------------------------------------------
task poly1305_init(input [255 : 0] key);
begin : poly1305_init
r_reg = key[255 : 128] & R_CLAMP;
s_reg = key[127 : 0];
acc_reg = 130'h0;
end
endtask // poly1305_init
//----------------------------------------------------------------
// poly1305_update()
//
// Given a block, update the internal Poly1305 state.
//----------------------------------------------------------------
task poly1305_update(input [129 : 0] block);
begin : poly1305_update
reg [261 : 0] tmp;
$display("r: 0x%033x", r_reg);
$display("b: 0x%033x", block);
$display("acc: 0x%033x", acc_reg);
acc_reg = acc_reg + block;
$display("acc + b: 0x%033x", acc_reg);
tmp = acc_reg * r_reg;
$display("acc * r: 0x%066x", tmp);
acc_reg = tmp % POLY1305;
$display("acc mod p: 0x%033x", acc_reg);
$display("");
end
endtask // poly1305_init
//----------------------------------------------------------------
// poly1305_finalize()
//----------------------------------------------------------------
task poly1305_finalize;
begin : poly1305_update
acc_reg = acc_reg + s_reg;
tag_reg = acc_reg[127 : 0];
end
endtask // poly1305_init
//----------------------------------------------------------------
// test poly1305_init()
//----------------------------------------------------------------
task test_poly1305_init;
begin : test_poly1305_init
reg [255 : 0] key;
reg [127 : 0] expected;
key = {128'ha806d542fe52447f336d555778bed685, 128'h0};
expected = 128'h0806d5400e52447c036d555408bed685;
poly1305_init(key);
$display("key: 0x%064x", key);
$display("r: 0x%032x", r_reg);
if (r_reg == expected)
$display("r is correct.");
else
$display("r is incorrect. Expexted 0x%0x32", expected);
end
endtask // poly1305_init
//----------------------------------------------------------------
// test poly1305_update()
//----------------------------------------------------------------
task test_poly1305_update;
begin : test_poly1305_update
reg [128 : 0] block;
acc_reg = 130'h0;
r_reg = 128'h0806d5400e52447c036d555408bed685;
block = 129'h16f4620636968706172676f7470797243;
poly1305_update(block);
$display("acc after block1: 0x%033x", acc_reg);
block = 129'h16f7247206863726165736552206d7572;
poly1305_update(block);
$display("acc after block2: 0x%033x", acc_reg);
block = 129'h000000000000000000000000000017075;
poly1305_update(block);
$display("acc after block3: 0x%033x", acc_reg);
end
endtask // test_poly1305_update
//----------------------------------------------------------------
// poly1305_tests
//----------------------------------------------------------------
initial
begin : poly1305_tests
test_poly1305_init();
test_poly1305_update();
end // poly1305_tests
endmodule // poly1305
//======================================================================
// EOF poly1305
//======================================================================
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC optimize( unroll-loops ) #pragma GCC target( sse2 ) using namespace std; const int N = 2020; namespace Gause { static const int N = ::N; int equ, var; bitset<N> a[N]; int x[N]; int free_x[N]; int free_num; int l[N]; void ini(int n) { for (int i = (0); i < (n); ++i) x[i] = 0; for (int i = (0); i < (n); ++i) a[i].reset(); } int Gauss() { int max_r, col, k; free_num = 0; for (k = 0, col = 0; k < equ && col < var; k++, col++) { max_r = k; for (int i = k + 1; i < equ; i++) { if (abs(a[i][col]) > abs(a[max_r][col])) max_r = i; } if (a[max_r][col] == 0) { k--; free_x[free_num++] = col; continue; } l[k] = col; if (max_r != k) { swap(a[k], a[max_r]); } for (int i = k + 1; i < equ; i++) { if (a[i][col] != 0) a[i] ^= a[k]; } } for (int i = k; i < equ; i++) { if (a[i][col] != 0) return -1; } for (int i = k - 1; i >= 0; i--) { int t = l[i]; x[t] = a[i][var]; for (int j = t + 1; j < var; j++) x[t] ^= (a[i][j] & x[j]); } return 0; } } // namespace Gause int T, n, m, u, v; bool du[N], vis[N][N]; int main() { std::ios::sync_with_stdio(0); std::cin.tie(0); cin >> T; for (int cas = (0); cas < (T); ++cas) { cin >> n >> m; Gause ::ini(n); for (int i = (1); i < (n + 1); ++i) for (int j = (1); j < (n + 1); ++j) vis[i][j] = 0; for (int i = (1); i < (n + 1); ++i) du[i] = 0; for (int i = (1); i < (m + 1); ++i) { cin >> u >> v; du[u] ^= 1; du[v] ^= 1; vis[u][v] = vis[v][u] = 1; } Gause ::equ = Gause ::var = n; for (int i = (1); i < (n + 1); ++i) { vis[i][i] = du[i]; for (int j = (1); j < (n + 1); ++j) Gause ::a[i - 1][j - 1] = vis[i][j]; Gause ::a[i - 1][n] = du[i]; } Gause::Gauss(); bool Vis[2] = {0}; for (int i = (1); i < (n + 1); ++i) Vis[Gause::x[i - 1]] = 1; if (Vis[0] && Vis[1]) { cout << 2 << n ; } else { cout << 1 << n ; if (Vis[1]) for (int i = (1); i < (n + 1); ++i) Gause::x[i - 1] = 0; } for (int i = (1); i < (n + 1); ++i) cout << Gause::x[i - 1] + 1 << ; cout << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); int n; cin >> n; vector<vector<long long int>> grid(51, vector<long long int>(51, 0)); vector<pair<long long int, long long int>> a; int t1 = 4 * n + 1; while (t1--) { int u, v; cin >> u >> v; a.push_back({u, v}); grid[u][v] = 1; } t1 = 4 * n + 1; for (int stx = 0; stx < 50; stx++) { for (int enx = stx + 1; enx < 51; enx++) { for (int sty = 0; sty < 50; sty++) { for (int eny = sty + 1; eny < 51; eny++) { long long int cnt = 0, c1 = 0, c2 = 0, c3 = 0, c4 = 0; for (int j = sty; j <= eny; j++) { if (grid[stx][j] == 1) { cnt++; c1++; if (j == sty) { c2++; } if (j == eny) { c4++; } } if (grid[enx][j] == 1) { cnt++; c3++; if (j == sty) { c2++; } if (j == eny) { c4++; } } } for (int j = stx + 1; j <= enx - 1; j++) { if (grid[j][sty] == 1) { cnt++; c2++; } if (grid[j][eny] == 1) { cnt++; c4++; } } if (cnt == 4 * n && c1 >= n && c2 >= n && c3 >= n && c4 >= n) { for (int i = 0; i < a.size(); i++) { if (a[i].first != stx && a[i].first != enx && a[i].second != sty && a[i].second != eny) { cout << a[i].first << << a[i].second; return 0; } if (a[i].first == stx || a[i].first == enx) { if (a[i].second < sty || a[i].second > eny) { cout << a[i].first << << a[i].second; return 0; } } if (a[i].second == sty || a[i].second == eny) { if (a[i].first < stx || a[i].first > enx) { cout << a[i].first << << a[i].second; return 0; } } } } } } } } } |
#include <bits/stdc++.h> int compare(const void *a, const void *b) { long long la = *(long long *)a; long long lb = *(long long *)b; return la == lb ? 0 : la < lb ? -1 : 1; } long long aa[8], aa_[8]; int bb[8], dp[8][1 << (8 - 1)]; char pp[8]; int n, ans = 0x3f3f3f3f; void solve(int i) { int j; if (i == n) { int cnt, sum; cnt = 0, sum = 0; for (i = 0; i < n; i++) { int k; if (!pp[i]) cnt++; k = dp[i][bb[i]]; sum += k == 1 && bb[i] == 0 ? 1 : k + 1; } if (cnt >= 2) sum++; if (ans > sum) ans = sum; return; } solve(i + 1); pp[i] = 1; for (j = i + 1; j < n; j++) if (aa_[j] % aa[i] == 0) { aa_[j] /= aa[i], bb[j] ^= 1 << i; solve(i + 1); aa_[j] *= aa[i], bb[j] ^= 1 << i; } pp[i] = 0; } int main() { int i, j; scanf( %d , &n); for (i = 0; i < n; i++) scanf( %lld , &aa[i]); qsort(aa, n, sizeof *aa, compare); for (i = 0; i < n; i++) { long long a; int k, p, b; a = aa[i]; k = 0; for (p = 2; p <= a / p; p++) while (a % p == 0) { k++; a /= p; } if (a > 1) k++; dp[i][0] = k; for (b = 1; b < 1 << i; b++) { a = aa[i]; k = dp[i][0]; for (j = 0; j < i; j++) if ((b & 1 << j)) { if (a % aa[j] != 0) { k = -1; break; } a /= aa[j]; k -= dp[j][0]; } dp[i][b] = k; } } for (i = 0; i < n; i++) aa_[i] = aa[i]; solve(0); printf( %d n , ans); return 0; } |
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Automatic transmit/receive switching of control pins to daughterboards
// Store everything in registers for now, but could use a RAM for more
// complex state machines in the future
module atr_controller
(input clk_i, input rst_i,
input [5:0] adr_i, input [3:0] sel_i, input [31:0] dat_i, output reg [31:0] dat_o,
input we_i, input stb_i, input cyc_i, output reg ack_o,
input run_rx, input run_tx,
output [31:0] ctrl_lines);
reg [3:0] state;
reg [31:0] atr_ram [0:15]; // DP distributed RAM
// WB Interface
always @(posedge clk_i)
if(we_i & stb_i & cyc_i)
begin
if(sel_i[3])
atr_ram[adr_i[5:2]][31:24] <= dat_i[31:24];
if(sel_i[2])
atr_ram[adr_i[5:2]][23:16] <= dat_i[23:16];
if(sel_i[1])
atr_ram[adr_i[5:2]][15:8] <= dat_i[15:8];
if(sel_i[0])
atr_ram[adr_i[5:2]][7:0] <= dat_i[7:0];
end // if (we_i & stb_i & cyc_i)
// Removing readback allows ram to be synthesized as LUTs instead of regs
//always @(posedge clk_i)
// dat_o <= atr_ram[adr_i[5:2]];
always
dat_o <= 32'd0;
always @(posedge clk_i)
ack_o <= stb_i & cyc_i & ~ack_o;
// Control side of DP RAM
assign ctrl_lines = atr_ram[state];
// Put a more complex state machine with time delays and multiple states here
// if daughterboard requires more complex sequencing
localparam ATR_IDLE = 4'd0;
localparam ATR_TX = 4'd1;
localparam ATR_RX = 4'd2;
localparam ATR_FULL_DUPLEX = 4'd3;
always @(posedge clk_i)
if(rst_i)
state <= ATR_IDLE;
else
case ({run_rx,run_tx})
2'b00 : state <= ATR_IDLE;
2'b01 : state <= ATR_TX;
2'b10 : state <= ATR_RX;
2'b11 : state <= ATR_FULL_DUPLEX;
endcase // case({run_rx,run_tx})
endmodule // atr_controller
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O31AI_M_V
`define SKY130_FD_SC_LP__O31AI_M_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog wrapper for o31ai with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o31ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o31ai_m (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o31ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o31ai_m (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o31ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O31AI_M_V
|
// minako #include <bits/stdc++.h> using namespace std; #define endl n #define f first #define s second #define pb push_back #define pii pair<int,int> #define ll long long #define pll pair <ll,ll> #define faster ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); const ll M = 1e9 + 7; const int N = 2e5 + 5; const ll INF = 1e9; const ll INF2 = 1e18; const int K = 750; ll n,u,v,a[N],q; int main() { faster cin >> q; while (q--) { cin >> n >> u >> v; bool eq = 1,can = 0; for (int i = 1; i <= n; i++) { cin >> a[i]; if (a[i] != a[i - 1] && i > 1) eq = 0; if (abs(a[i] - a[i - 1]) > 1 && i > 1) can = 1; } if (can) cout << 0 << endl; else if (eq) cout << v + min(u,v) << endl; else cout << min(u,v) << endl;; } return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> inline void chmax(T &x, T &y) { if (x < y) swap(x, y); } template <class T> inline void chmin(T &x, T &y) { if (x > y) swap(x, y); } const long long INF = 0x3f3f3f3f3f3f; const long long MOD = 1e9 + 7; const double EPS = 10e-10; const long long P2LIM = (long long)2e18; const long long maxN = 1e9 + 10; void Solution() {} long long countSC(long long N) { long long res = (long long)sqrt(N) + (long long)cbrt(N) - (long long)(sqrt(cbrt(N))); return res; } int32_t main() { long long tc; cin >> tc; while (tc--) { long long n; cin >> n; cout << countSC(n) << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; const int N = 4e2 + 5; int n, f[N][N]; int main() { scanf( %d , &n); f[1][0] = f[1][1] = 1; for (int top = 1; top < n; ++top) { for (int i = 0; i <= n; ++i) { for (int j = 0; j <= n - i + 1; ++j) { int tmp = (long long)f[top][i] * f[top][j] % MOD; if (i + j <= n) f[top + 1][i + j] = (f[top + 1][i + j] + (long long)(2 * i + 2 * j + 1) * tmp % MOD) % MOD; if (i + j + 1 <= n) f[top + 1][i + j + 1] = (f[top + 1][i + j + 1] + tmp) % MOD; if (i + j - 1 <= n) f[top + 1][i + j - 1] = (f[top + 1][i + j - 1] + (long long)(i + j - 1) * (i + j) % MOD * tmp % MOD) % MOD; } } } printf( %d n , f[n][1]); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int a, b, n; cin >> a >> b >> n; a = a * 10; int f = 0; for (int i = 0; i < 10; i++) { if ((a + i) % b == 0) { cout << a + i; string s(n - 1, 0 ); cout << s << endl; f = 1; break; } } if (!f) cout << -1 << endl; } |
module shregmap_static_test(input i, clk, output [1:0] q);
reg head = 1'b0;
reg [3:0] shift1 = 4'b0000;
reg [3:0] shift2 = 4'b0000;
always @(posedge clk) begin
head <= i;
shift1 <= {shift1[2:0], head};
shift2 <= {shift2[2:0], head};
end
assign q = {shift2[3], shift1[3]};
endmodule
module $__SHREG_DFF_P_(input C, D, output Q);
parameter DEPTH = 2;
parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
reg [DEPTH-1:0] r = INIT;
always @(posedge C)
r <= { r[DEPTH-2:0], D };
assign Q = r[DEPTH-1];
endmodule
module shregmap_variable_test(input i, clk, input [1:0] l1, l2, output [1:0] q);
reg head = 1'b0;
reg [3:0] shift1 = 4'b0000;
reg [3:0] shift2 = 4'b0000;
always @(posedge clk) begin
head <= i;
shift1 <= {shift1[2:0], head};
shift2 <= {shift2[2:0], head};
end
assign q = {shift2[l2], shift1[l1]};
endmodule
module $__XILINX_SHREG_(input C, D, input [1:0] L, output Q);
parameter CLKPOL = 1;
parameter ENPOL = 1;
parameter DEPTH = 2;
parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
reg [DEPTH-1:0] r = INIT;
wire clk = C ^ CLKPOL;
always @(posedge C)
r <= { r[DEPTH-2:0], D };
assign Q = r[L];
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Interface to Cypress FX2 bus
// A packet is 512 Bytes. Each fifo line is 2 bytes
// Fifo has 1024 or 2048 lines
`include "../../firmware/include/fpga_regs_common.v"
`include "../../firmware/include/fpga_regs_standard.v"
module rx_buffer
( input usbclk,
input bus_reset, // Not used in RX
input reset, // DSP side reset (used here), do not reset registers
input reset_regs, //Only reset registers
output [15:0] usbdata,
input RD,
output wire have_pkt_rdy,
output reg rx_overrun,
input wire [3:0] channels,
input wire [15:0] ch_0,
input wire [15:0] ch_1,
input wire [15:0] ch_2,
input wire [15:0] ch_3,
input wire [15:0] ch_4,
input wire [15:0] ch_5,
input wire [15:0] ch_6,
input wire [15:0] ch_7,
input rxclk,
input rxstrobe,
input clear_status,
input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe,
output [15:0] debugbus
);
wire [15:0] fifodata, fifodata_8;
reg [15:0] fifodata_16;
wire [11:0] rxfifolevel;
wire rx_empty, rx_full;
wire bypass_hb, want_q;
wire [4:0] bitwidth;
wire [3:0] bitshift;
setting_reg #(`FR_RX_FORMAT) sr_rxformat(.clock(rxclk),.reset(reset_regs),
.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
.out({bypass_hb,want_q,bitwidth,bitshift}));
// Receive FIFO (ADC --> USB)
// 257 Bug Fix
reg [8:0] read_count;
always @(negedge usbclk)
if(bus_reset)
read_count <= #1 9'd0;
else if(RD & ~read_count[8])
read_count <= #1 read_count + 9'd1;
else
read_count <= #1 RD ? read_count : 9'b0;
// Detect overrun
always @(posedge rxclk)
if(reset)
rx_overrun <= 1'b0;
else if(rxstrobe & (store_next != 0))
rx_overrun <= 1'b1;
else if(clear_status)
rx_overrun <= 1'b0;
reg [3:0] store_next;
always @(posedge rxclk)
if(reset)
store_next <= #1 4'd0;
else if(rxstrobe & (store_next == 0))
store_next <= #1 4'd1;
else if(~rx_full & (store_next == channels))
store_next <= #1 4'd0;
else if(~rx_full & (bitwidth == 5'd8) & (store_next == (channels>>1)))
store_next <= #1 4'd0;
else if(~rx_full & (store_next != 0))
store_next <= #1 store_next + 4'd1;
assign fifodata = (bitwidth == 5'd8) ? fifodata_8 : fifodata_16;
assign fifodata_8 = {round_8(top),round_8(bottom)};
reg [15:0] top,bottom;
function [7:0] round_8;
input [15:0] in_val;
round_8 = in_val[15:8] + (in_val[15] & |in_val[7:0]);
endfunction // round_8
always @*
case(store_next)
4'd1 : begin
bottom = ch_0;
top = ch_1;
end
4'd2 : begin
bottom = ch_2;
top = ch_3;
end
4'd3 : begin
bottom = ch_4;
top = ch_5;
end
4'd4 : begin
bottom = ch_6;
top = ch_7;
end
default : begin
top = 16'hFFFF;
bottom = 16'hFFFF;
end
endcase // case(store_next)
always @*
case(store_next)
4'd1 : fifodata_16 = ch_0;
4'd2 : fifodata_16 = ch_1;
4'd3 : fifodata_16 = ch_2;
4'd4 : fifodata_16 = ch_3;
4'd5 : fifodata_16 = ch_4;
4'd6 : fifodata_16 = ch_5;
4'd7 : fifodata_16 = ch_6;
4'd8 : fifodata_16 = ch_7;
default : fifodata_16 = 16'hFFFF;
endcase // case(store_next)
fifo_4k rxfifo
( .data ( fifodata ),
.wrreq (~rx_full & (store_next != 0)),
.wrclk ( rxclk ),
.q ( usbdata ),
.rdreq ( RD & ~read_count[8] ),
.rdclk ( ~usbclk ),
.aclr ( reset ), // This one is asynchronous, so we can use either reset
.rdempty ( rx_empty ),
.rdusedw ( rxfifolevel ),
.wrfull ( rx_full ),
.wrusedw ( )
);
assign have_pkt_rdy = (rxfifolevel >= 256);
// Debugging Aids
assign debugbus[0] = RD;
assign debugbus[1] = rx_overrun;
assign debugbus[2] = read_count[8];
assign debugbus[3] = rx_full;
assign debugbus[4] = rxstrobe;
assign debugbus[5] = usbclk;
assign debugbus[6] = have_pkt_rdy;
assign debugbus[10:7] = store_next;
//assign debugbus[15:11] = rxfifolevel[4:0];
assign debugbus[15:11] = bitwidth;
endmodule // rx_buffer
|
/*
* Copyright (C) 2015 Harmon Instruments, LLC
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/
*
*/
`timescale 1ns / 1ps
// 6 clocks
module cosgen (input c, input [25:0] a, output signed [NBD-1:0] o);
parameter NBD = 23;
reg [23:0] a0 = 0;
reg s0 = 0;
always @ (posedge c) begin
a0 <= a[24] ? ~ a[23:0] : a[23:0];
s0 <= a[25] ^ a[24];
end
wire [34:0] rd0;
cosrom cosrom
(.c(c), .a0(a0[23:14]), .a1(10'd0), .d0(rd0), .d1());
cosine_int #(.NBO(NBD)) cos_0
(.c(c), .a(a0[13:0]), .rom_d(rd0), .s(s0), .o(o));
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1000000007; const int NMAX = 5005; const int INF = 2e5; int n; vector<int> arr; vector<vector<int>> dp(NMAX, vector<int>(NMAX, INF)); int rec(int i, int j) { if (dp[i][j] != INF) return dp[i][j]; if (i == j) return dp[i][j] = 0; if (arr[i] == arr[j]) return dp[i][j] = 1 + rec(i + 1, j - 1); return dp[i][j] = 1 + min(rec(i + 1, j), rec(i, j - 1)); } void solve() { cin >> n; for (int i = 0; i < n; i++) { int tmp; cin >> tmp; if (!i) arr.push_back(tmp); else if (tmp != arr[(int)(arr.size()) - 1]) arr.push_back(tmp); } n = (int)(arr.size()); cout << rec(0, n - 1) << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); int t; t = 1; while (t--) { int n; cin >> n; long long arr[n], c4 = 0, c2 = 0; long long i; map<long long, long long> make_pair; for (i = 0; i < n; i++) { cin >> arr[i]; c4 -= make_pair[arr[i]] / 4; c2 -= make_pair[arr[i]] / 2; make_pair[arr[i]]++; c4 += make_pair[arr[i]] / 4; c2 += make_pair[arr[i]] / 2; } long long q; cin >> q; for (i = 0; i < q; i++) { char c; long long x; cin >> c >> x; c4 -= make_pair[x] / 4; c2 -= make_pair[x] / 2; if (c == + ) { make_pair[x]++; } else { make_pair[x]--; } c4 += make_pair[x] / 4; c2 += make_pair[x] / 2; if (c4 >= 1 && c2 >= 4) { cout << YES << endl; } else { cout << NO << endl; } } } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long maxn = 3e5, N = 2e6 + 90, SQ = 300, base = 1999, mod = 1e9 + 7, INF = 1e9 + 1, lg = 30; const long double eps = 1e-4; long long n, a[maxn], b[maxn], c[maxn], d[maxn], cnt[maxn], s1, s2, tot; inline bool check() { for (long long i = 0; i < n; ++i) { for (long long j = 0; j < lg; ++j) { if (a[i] & (1ll << j)) { cnt[j]++; } } } for (long long i = 0; i < n; ++i) { long long res1 = 0, res2 = 0; for (long long j = 0; j < lg; ++j) { if (a[i] & (1ll << j)) { res1 += (cnt[j] * (1ll << j)); res2 += (n - cnt[j]) * (1ll << j); } res2 += (cnt[j] * (1ll << j)); } if (res1 != b[i] || res2 != c[i]) { return 0; } } return 1; } int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n; for (long long i = 0; i < n; ++i) { cin >> b[i]; s1 += b[i]; } for (long long i = 0; i < n; ++i) { cin >> c[i]; s2 += c[i]; } if ((s1 + s2) % (2 * n) != 0) { cout << -1 << n ; return 0; } tot = (s1 + s2) / (2 * n); for (long long i = 0; i < n; ++i) { d[i] = b[i] + c[i]; } for (long long i = 0; i < n; ++i) { a[i] = (d[i] - tot) / n; } if (check()) { for (long long i = 0; i < n; ++i) { cout << a[i] << ; } cout << n ; } else { cout << -1 << n ; } } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Create Date: 13:11:50 05/24/2012
// Module Name: fifo
// Description: fifo buffer
// Sourced from: Pong P. Chu, "FPGA Prototyping by Verilog Examples"
//////////////////////////////////////////////////////////////////////////////////
module fifo
#(
parameter B=8,
W=4
)
(
input wire clk, reset,
input wire rd, wr,
input wire [B-1:0] w_data,
output wire empty, full,
output wire [B-1:0] r_data
);
// signal declaration
reg [B-1:0] array_reg [2**W-1:0]; // register array
reg [W-1:0] w_ptr_reg, w_ptr_next, w_ptr_succ;
reg [W-1:0] r_ptr_reg, r_ptr_next, r_ptr_succ;
reg full_reg, empty_reg, full_next, empty_next;
wire wr_en;
// body
// register file write operation
always @(posedge clk)
if (wr_en)
array_reg [w_ptr_reg] <= w_data;
// register file read operation
assign r_data = array_reg[r_ptr_reg];
// write enabled only when FIFO is not full
assign wr_en = wr & ~full_reg;
//
// fifo control logic
// register for read and write pointers
always @(posedge clk)
if (reset)
begin
w_ptr_reg <= 0;
r_ptr_reg <= 0;
full_reg <= 1'b0;
empty_reg <= 1'b1;
end
else
begin
w_ptr_reg <= w_ptr_next;
r_ptr_reg <= r_ptr_next;
full_reg <= full_next;
empty_reg <= empty_next;
end
// next-state logic for read and write pointers
always @*
begin
// successive pointer values
w_ptr_succ = w_ptr_reg + 1;
r_ptr_succ = r_ptr_reg + 1;
// default: keep old values
w_ptr_next = w_ptr_reg;
r_ptr_next = r_ptr_reg;
full_next = full_reg;
empty_next = empty_reg;
case ({wr, rd})
// 2'b00: no op
2'b01: // read
if (~empty_reg) // not empty
begin
r_ptr_next = r_ptr_succ;
full_next = 1'b0;
if (r_ptr_succ==w_ptr_reg)
empty_next = 1'b1;
end
2'b10: // write
if (~full_reg) // not full
begin
w_ptr_next = w_ptr_succ ;
empty_next = 1'b0;
if (w_ptr_succ==r_ptr_reg)
full_next = 1'b1;
end
2'b11: // write and read
begin
w_ptr_next = w_ptr_succ;
r_ptr_next = r_ptr_succ;
end
endcase
end
// output
assign full = full_reg;
assign empty = empty_reg;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02/01/2016 11:58:07 AM
// Design Name:
// Module Name: FullAdder_NoError
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FullAdder_NoError(
input [3:0] A,
input [3:0] B,
input Operation,
output [4:0] S
);
wire detector; // accounts for the 5th bit of the sum
wire carry_out1, carry_out2, carry_out3, carry_out4, wire1;
AdderSliced Bit0 (
.A(A[0]),
.B(B[0] ^ Operation), // or try B[0] ^ Operation
.S(S[0]),
.Cout(carry_out1),
.Cin(Operation)
);
AdderSliced Bit1 (
.A(A[1]),
.B(B[1] ^ Operation),
.S(S[1]),
.Cout(carry_out2), //no overflow -> .Cout(S[2:0]),
.Cin(carry_out1)
);
AdderSliced Bit2 (
.A(A[2]),
.B(B[2] ^ Operation),
.S(S[2]),
.Cout(carry_out3), //no overflow -> .Cout(S[2:0]),
.Cin(carry_out2)
);
AdderSliced Bit3 (
.A(A[3]),
.B(B[3] ^ Operation),
.S(S[3]),
.Cout(detector ), //no overflow -> .Cout(S[2:0]),
.Cin(carry_out3)
);
AdderSliced Bit4 (
.A(A[3]),
.B(B[3] ^ Operation),
.S(S[4]),
.Cout(wire1),
.Cin(detector)
);
//assign S[4] = B[3] | A[3];
//assign S[4] = ~(Operation | detector);
//assign S[4] = ~(detector & B[3]);
//assign S[4] = (Operation ^ detector) ; //| (A[3] & B[3]) | ~(~A[3] & ~B[3]) ;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MOD = 998244353; int main() { string a, v[6]; cin >> a; for (int i = 1; i <= 5; ++i) { cin >> v[i]; if (v[i][0] == a[0] || v[i][1] == a[1]) { cout << YES n ; return 0; } } cout << NO n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYMETAL6S6S_BLACKBOX_V
`define SKY130_FD_SC_LS__DLYMETAL6S6S_BLACKBOX_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlymetal6s6s (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYMETAL6S6S_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; long long power(long long b, long long e, long long m) { long long p = 1; while (e > 0) { if (e & 1) p = (p * b) % m; e = e >> 1; b = (b * b) % m; } return p; } long long cnt[16] = {1, 0, 0, 0, 1, 0, 1, 0, 2, 1, 1, 2, 0, 1, 0, 0}; long long getAns(long long n) { long long ans = 0; if (n == 0) return cnt[0]; while (n) { ans += cnt[n % 16]; n /= 16; } return ans; } int main() { long long n, i = 0, j, m, h, h1, h2, q, k, l, r, ans; scanf( %lld , &n); printf( %lld n , getAns(n)); return 0; } |
#include <bits/stdc++.h> using namespace std; /* #include <ext/pb_ds/assoc_container.hpp> #include <ext/pb_ds/tree_policy.hpp> using namespace __gnu_pbds; #define ordered_set tree<int, null_type,less<int>, rb_tree_tag,tree_order_statistics_node_update> */ typedef long long ll; typedef long double ld; typedef unsigned long long ull; #define rep(i,a,b) for(ll i=a;i<=b;++i) #define rrep(i,a,b) for(ll i=a;i>=b;--i) #define FOR(i,n) for(ll i=0;i<n;i++) #define pb push_back #define mp make_pair #define PI 3.14159265358979323846 #define fi first #define se second #define all(x) x.begin(),x.end() #define IOS ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); const ll INF = 1e18+10; const ll mod = 1e9+7; const ll MAXN = 2e5+10; ll poww(ll a, ll b) { if(b<0) return 0LL; ll ans = 1; while (b) { if (b & 1)ans = ans * a; a = a * a; b >>= 1; } return ans; } ll binpow(ll a, ll b) { if (b < 0) return 0LL; if (a <= 0)return 0LL; a %= mod; ll ans = 1LL; while (b) { if (b & 1)ans = ans * a % mod; a = a * a % mod; b >>= 1; } return ans; } ll modinv(ll n) { return binpow(n, mod - 2); } void solve() { ll n; cin>>n; vector<ll> x; ll a[n]; FOR(i,n) { cin>>a[i]; x.pb(a[i]); } sort(all(x)); vector<ll> s(n,0); s[0] = x[0]; ll j = 0; vector<ll> inv(n,1); for(ll i=1; i<n; i++) { if(x[i]>s[i-1]) { for(ll k=i-1; k>=j; k--) { inv[k] = 0; } j = i; } s[i] = s[i-1] + x[i]; } map<ll,ll> mt; FOR(i,n) { if(inv[i]==1) mt[x[i]] = 1; } vector<ll> ans; FOR(i,n) { if(mt[a[i]]==1) ans.pb(i+1); } cout<<ans.size()<< n ; FOR(i,ans.size()) cout<<ans[i]<< ; cout<< n ; } int main() { IOS; #ifndef ONLINE_JUDGE freopen( input.txt , r , stdin); freopen( output.txt , w , stdout); #endif ll no_of_test_cases; cin>>no_of_test_cases; //ll no_of_test_cases = 1; //cout<<fixed<<setprecision(10); for(ll i=1; i<=no_of_test_cases; i++) { solve(); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21OI_SYMBOL_V
`define SKY130_FD_SC_HD__A21OI_SYMBOL_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a21oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21OI_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EINVP_BEHAVIORAL_V
`define SKY130_FD_SC_HD__EINVP_BEHAVIORAL_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__einvp (
Z ,
A ,
TE
);
// Module ports
output Z ;
input A ;
input TE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
notif1 notif10 (Z , A, TE );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__EINVP_BEHAVIORAL_V |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
module convolve_kernel_fcud
#(parameter
ID = 17,
NUM_STAGE = 5,
din0_WIDTH = 32,
din1_WIDTH = 32,
dout_WIDTH = 32
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [31:0] a_tdata;
wire b_tvalid;
wire [31:0] b_tdata;
wire r_tvalid;
wire [31:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
convolve_kernel_ap_fmul_3_max_dsp_32 convolve_kernel_ap_fmul_3_max_dsp_32_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; string s; cin >> s; vector<int> way(s.size()); way[0] = 0; for (int i = 1; i < (int)s.size(); i++) { if (s[i] == 0 ) way[i] = i; else way[i] = way[i - 1]; } int l = 0, r = n - 1; while (r - l > 1) { int m = (l + r) / 2; int cnt = k - 1; int now = 0; int last = 0; while (now < n && cnt > 0) { now += m; now = min(now, n - 1); now = way[now]; cnt--; last = max(last, now); } if (last == n - 1) { r = m; } else { l = m; } } cout << l << n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O221AI_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__O221AI_PP_BLACKBOX_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o221ai (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O221AI_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFXTP_4_V
`define SKY130_FD_SC_HDLL__SDFXTP_4_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog wrapper for sdfxtp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__sdfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sdfxtp_4 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sdfxtp_4 (
Q ,
CLK,
D ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFXTP_4_V
|
#include <bits/stdc++.h> using namespace std; template <typename T> T nextInt() { T x = 0, p = 1; char ch; do { ch = getchar(); } while (ch <= ); if (ch == - ) { p = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + (ch - 0 ); ch = getchar(); } return x * p; } const int maxN = (int)4e5 + 10; const int INF = (int)1e9; const int mod = (int)1e9 + 7; const long long LLINF = (long long)1e15; int fw[maxN]; int answer[maxN]; vector<pair<int, int> > g[maxN]; int get(int r) { int ret = 0; for (; r >= 0; r = (r & (r + 1)) - 1) { ret += fw[r]; } return ret; } void update(int r) { for (; r < maxN; r |= r + 1) { fw[r]++; } } int l[maxN]; int r[maxN]; int main() { ios_base::sync_with_stdio(0); int n; cin >> n; vector<int> x; for (int i = 0; i < n; ++i) { cin >> l[i] >> r[i]; x.push_back(l[i]); x.push_back(r[i]); } sort(x.begin(), x.end()); for (int i = 0; i < n; ++i) { l[i] = lower_bound(x.begin(), x.end(), l[i]) - x.begin(); r[i] = lower_bound(x.begin(), x.end(), r[i]) - x.begin(); g[r[i]].push_back(make_pair(l[i], i)); } for (int i = 0; i < maxN; ++i) { for (auto x : g[i]) { int l = x.first; int idx = x.second; answer[idx] = get(maxN - 1) - get(l); update(l); } } for (int i = 0; i < n; ++i) { cout << answer[i] << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; void _print(int t) { cerr << t; } void _print(string t) { cerr << t; } void _print(char t) { cerr << t; } void _print(long double t) { cerr << t; } void _print(double t) { cerr << t; } void _print(unsigned long long t) { cerr << t; } template <class T, class V> void _print(pair<T, V> p); template <class T> void _print(vector<T> v); template <class T> void _print(set<T> v); template <class T, class V> void _print(map<T, V> v); template <class T> void _print(multiset<T> v); template <class T, class V> void _print(pair<T, V> p) { cerr << { ; _print(p.first); cerr << , ; _print(p.second); cerr << } ; } template <class T> void _print(vector<T> v) { cerr << [ ; for (T i : v) { _print(i); cerr << ; } cerr << ] ; } template <class T> void _print(set<T> v) { cerr << [ ; for (T i : v) { _print(i); cerr << ; } cerr << ] ; } template <class T> void _print(multiset<T> v) { cerr << [ ; for (T i : v) { _print(i); cerr << ; } cerr << ] ; } template <class T, class V> void _print(map<T, V> v) { cerr << [ ; for (auto i : v) { _print(i); cerr << ; } cerr << ] ; } void init_code() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); } void solve() { string a; string b; cin >> a >> b; string ans; int n = ((int)(a).size()); int n1 = ((int)(b).size()); int j = n1 - 1; int flag = 0; int i = n - 1; while (i >= 0) { if (a[i] == b[j]) { i--; j--; } else { i -= 2; } if (j == -1) { flag = 1; break; } } if (flag) cout << YES ; else cout << NO ; cout << n ; } signed main() { init_code(); long long t = 1; cin >> t; while (t--) { solve(); } return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Tue Oct 17 02:50:46 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top RAT_slice_17_13_0 -prefix
// RAT_slice_17_13_0_ RAT_slice_17_13_0_stub.v
// Design : RAT_slice_17_13_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "xlslice,Vivado 2016.4" *)
module RAT_slice_17_13_0(Din, Dout)
/* synthesis syn_black_box black_box_pad_pin="Din[17:0],Dout[1:0]" */;
input [17:0]Din;
output [1:0]Dout;
endmodule
|
#include <bits/stdc++.h> using namespace std; char s[100004]; long long k, mod = 1000000007; long long qpow(long long n, long long m) { long long ans = 1; for (; m; m >>= 1) { if (m & 1) ans = ans * n % mod; n = n * n % mod; } return ans; } int main() { scanf( %s %lld , s, &k); int l = strlen(s); long long p = 0, q = 0; for (int i = 0; i < l; i++) if (s[i] == 0 || s[i] == 5 ) p = (p + qpow(2, i)) % mod; q = (qpow(2, k * l) - 1) * qpow(qpow(2, l) - 1, mod - 2) % mod; printf( %lld n , p * q % mod); } |
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1.0); const long long MOD = 1000000000 + 7; const int MAXN = 100000 + 5; long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } inline long long readLL() { char ch; bool flag = false; long long a = 0; while (!((((ch = getchar()) >= 0 ) && (ch <= 9 )) || (ch == - ))) ; if (ch != - ) { a *= 10; a += ch - 0 ; } else { flag = true; } while (((ch = getchar()) >= 0 ) && (ch <= 9 )) { a *= 10; a += ch - 0 ; } if (flag) a = -a; return a; } inline int read() { char ch; bool flag = false; int a = 0; while (!((((ch = getchar()) >= 0 ) && (ch <= 9 )) || (ch == - ))) ; if (ch != - ) { a *= 10; a += ch - 0 ; } else { flag = true; } while (((ch = getchar()) >= 0 ) && (ch <= 9 )) { a *= 10; a += ch - 0 ; } if (flag) a = -a; return a; } const int N = 1000000; long long prime[N]; bool check[N]; int totp; void Eular() { memset(check, false, sizeof(check)); totp = 0; for (int i = 2; i < N; i++) { if (!check[i]) prime[totp++] = i; for (int j = 0; j < totp; j++) { if (i * prime[j] >= N) break; check[i * prime[j]] = true; if (i % prime[j] == 0) break; } } } int totfj; long long fj[20]; int numfj[20]; void fenjie(long long n) { totfj = 0; for (int i = 0, __END__ = (int)(totp); i < __END__; i++) { if (n < prime[i]) break; if (n % prime[i] == 0) { numfj[totfj] = 0; fj[totfj] = prime[i]; while (n % prime[i] == 0) n /= prime[i], numfj[totfj]++; totfj++; } } if (n > 1) { fj[totfj++] = n; } } int totys; long long ys[10010]; void getys(long long n) { fenjie(n); totys = 0; ys[totys++] = 1; int tmp; long long mul; for (int i = 0, __END__ = (int)(totfj); i < __END__; i++) { tmp = totys; mul = 1; for (int j = 0, __END__ = (int)(numfj[i]); j < __END__; j++) { mul *= fj[i]; for (int k = 0, __END__ = (int)(tmp); k < __END__; k++) ys[totys++] = mul * ys[k]; } } } long long a[1010]; long long b[1010]; int dp[1010][10010]; pair<pair<int, int>, long long> path[1010][10010]; unordered_map<long long, int> zip; unordered_map<int, long long> unzip; const int inf = 100000; const long long infLL = 9000000000000000000LL; int main() { Eular(); int n; n = read(); long long k; k = readLL(); for (int i = 1, __END__ = (int)(n); i <= __END__; i++) a[i] = readLL(); for (int i = 1, __END__ = (int)(n); i <= __END__; i++) b[i] = gcd(k, a[i]); if (k == 1) { int ans = 1; for (int i = 1, __END__ = (int)(n); i <= __END__; i++) if (a[ans] > a[i]) ans = i; cout << 1 << endl; cout << ans << endl; return 0; } getys(k); if (totys >= 10010) return -1; for (int i = 0, __END__ = (int)(totys); i < __END__; i++) zip[ys[i]] = i, unzip[i] = ys[i]; for (int i = 0, __END__ = (int)(n + 1); i < __END__; i++) for (int j = 0, __END__ = (int)(totys); j < __END__; j++) dp[i][j] = inf; path[n][totys - 1] = make_pair(make_pair(inf, inf), infLL); path[0][0] = make_pair(make_pair(inf, inf), 0LL); long long now; long long nxt; int inow; int inxt; dp[0][0] = 0; for (int i = 0, __END__ = (int)(n); i < __END__; i++) { for (int j = 0, __END__ = (int)(totys); j < __END__; j++) if (dp[i][j] != inf) if (dp[i + 1][j] == dp[i][j]) { if (path[i + 1][j].second > path[i][j].second) path[i + 1][j] = path[i][j]; } for (int j = 0, __END__ = (int)(totys); j < __END__; j++) if (dp[i + 1][j] > dp[i][j]) { dp[i + 1][j] = dp[i][j]; path[i + 1][j] = path[i][j]; } for (int j = 0, __END__ = (int)(totys); j < __END__; j++) if (dp[i][j] != inf) { now = unzip[j]; nxt = gcd(k / b[i + 1], now) * b[i + 1]; inxt = zip[nxt]; if (dp[i + 1][inxt] == dp[i][j] + 1) { if (path[i + 1][inxt].second > path[i][j].second + a[i + 1]) path[i + 1][inxt] = make_pair(make_pair(i, j), path[i][j].second + a[i + 1]); } if (dp[i + 1][inxt] > dp[i][j] + 1) { dp[i + 1][inxt] = dp[i][j] + 1; path[i + 1][inxt] = make_pair(make_pair(i, j), path[i][j].second + a[i + 1]); } } } if (dp[n][totys - 1] == inf) { puts( -1 ); return 0; } printf( %d n , dp[n][totys - 1]); pair<int, int> pit(n, totys - 1); int flag = 1; while (pit.first != inf && pit.second != inf) { pit = path[pit.first][pit.second].first; if (pit.first == inf) break; if (flag) flag = 0; else printf( ); printf( %d , pit.first + 1); } puts( ); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long N = 2e5 + 5; const long long inf = 199999999999999999; const long long mod = 1e9 + 7; void read() { freopen( lifeguards.in , r , stdin); freopen( lifeguards.out , w , stdout); } void solve() { int coloured[N] = {}, pp[N] = {}, mx = 0, mx1 = 0, attribute = 0, cur = 0; long long n; cin >> n; vector<long long> v(n); for (auto &i : v) { cin >> i; if (i == cur) attribute = 1; cur = i; } if (v[0] == v[n - 1]) attribute = 1; if (is_sorted(v.begin(), v.end()) && v[0] == v[n - 1]) { cout << 1 n ; for (int i = 0; i < n; ++i) { cout << 1 ; } return; } if (n & 1 ^ 1) { cout << 2 n ; for (int i = 0; i < n; ++i) { if (i & 1) cout << 1 ; else cout << 2 ; } return; } else { if (attribute) { cout << 2 n ; long long op = 1, borely = 1; cur = 2; for (int i = 0; i < n; ++i) { if (v[i] == v[i - 1] && op) { if (cur == 2) cout << 2 , cur = 2; else cout << 1 , cur = 1; op ^= 1; continue; } if (cur == 2) cout << 1 , cur = 1; else cout << 2 , cur = 2; } } else { cout << 3 n ; for (int i = 0; i < n - 1; ++i) { if (i & 1) cout << 1 ; else cout << 2 ; } cout << 3; } } } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long T = 1; cin >> T; while (T--) { solve(); cout << n ; } cerr << nTime elapsed: << 1.0 * clock() / CLOCKS_PER_SEC << s. n ; } |
#include <bits/stdc++.h> using namespace std; const long long N = 1e5 + 10, M = 1e9, eps = 1e-7, MOD = 1e9 + 7; long long tab[N]; int main() { long long n, l; cin >> n >> l; n--; for (long long i = 1; i <= n; i++) cin >> tab[i]; long long pocz = 0; long long pot = 1 << 30; while (pot > 0) { long long moze = pot + pocz; if (moze > M) { pot /= 2; continue; } long long pom = 0; bool czujka = true; for (long long i = 1; i <= l; i++) pom += tab[i]; if (pom < moze) czujka = false; for (long long i = l + 1; i <= n; i++) { pom += tab[i]; pom -= tab[i - l]; if (pom < moze) czujka = false; } if (czujka) pocz = moze; pot /= 2; } cout << pocz; } |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 7; int Log[N], bin[21], ls[N], rs[N], root, a[N], n, i, j; set<int> s[N]; pair<int, int> mx[N][20]; long long ans; void merge(int x, int y) { if (s[x].size() < s[y].size()) swap(s[x], s[y]); for (auto& z : s[y]) s[x].insert(z); s[y].clear(); } void dfs(int x) { if (!x) return; dfs(ls[x]); dfs(rs[x]); if (s[ls[x]].size() > s[rs[x]].size()) swap(ls[x], rs[x]); for (auto& z : s[ls[x]]) if (s[rs[x]].count(a[x] - z)) ans++; s[x].insert(a[x]); merge(x, ls[x]); merge(x, rs[x]); } int query(int l, int r) { int t = Log[r - l + 1]; return max(mx[l][t], mx[r - bin[t] + 1][t]).second; } int build(int l, int r) { if (l > r) return 0; int x = query(l, r); ls[x] = build(l, x - 1); rs[x] = build(x + 1, r); return x; } int main() { for (scanf( %d , &n), i = 1; i <= n; ++i) scanf( %d , a + i); for (Log[0] = -1, i = 1; i <= n; ++i) Log[i] = Log[i >> 1] + 1; for (bin[0] = 1, i = 1; i < 20; ++i) bin[i] = bin[i - 1] << 1; for (i = 1; i <= n; ++i) mx[i][0] = pair<int, int>(a[i], i); for (j = 1; j <= Log[n]; ++j) for (i = 1; i + bin[j - 1] <= n; ++i) mx[i][j] = max(mx[i][j - 1], mx[i + bin[j - 1]][j - 1]); root = build(1, n); dfs(root); printf( %d n , ans); } |
// Copyright (c) 2000-2011 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 28325 $
// $Date: 2012-04-25 18:22:57 +0000 (Wed, 25 Apr 2012) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
// Single-Ported BRAM
module BRAM1Load(CLK,
EN,
WE,
ADDR,
DI,
DO
);
parameter FILENAME = "";
parameter PIPELINED = 0;
parameter ADDR_WIDTH = 1;
parameter DATA_WIDTH = 1;
parameter MEMSIZE = 1;
parameter BINARY = 0;
input CLK;
input EN;
input WE;
input [ADDR_WIDTH-1:0] ADDR;
input [DATA_WIDTH-1:0] DI;
output [DATA_WIDTH-1:0] DO;
reg [DATA_WIDTH-1:0] RAM[0:MEMSIZE-1];
reg [DATA_WIDTH-1:0] DO_R;
reg [DATA_WIDTH-1:0] DO_R2;
// synopsys translate_off
initial
begin : init_block
`ifdef BSV_NO_INITIAL_BLOCKS
`else
integer i;
for (i = 0; i < MEMSIZE; i = i + 1) begin
RAM[i] = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
DO_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DO_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
`endif // !`ifdef BSV_NO_INITIAL_BLOCKS
if (BINARY)
$readmemb(FILENAME, RAM, 0, MEMSIZE-1);
else
$readmemh(FILENAME, RAM, 0, MEMSIZE-1);
end
// synopsys translate_on
always @(posedge CLK) begin
if (EN) begin
if (WE) begin
RAM[ADDR] <= `BSV_ASSIGNMENT_DELAY DI;
DO_R <= `BSV_ASSIGNMENT_DELAY DI;
end
else begin
DO_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDR];
end
end
DO_R2 <= `BSV_ASSIGNMENT_DELAY DO_R;
end
// Output driver
assign DO = (PIPELINED) ? DO_R2 : DO_R;
endmodule // BRAM1Load
|
// ******************************************************************************* //
// ** General Information ** //
// ******************************************************************************* //
// ** Module : firdecim.v ** //
// ** Project : ISAAC NEWTON ** //
// ** Author : Kayla Nguyen ** //
// ** First Release Date : August 13, 2008 ** //
// ** Description : Polyphase Decimation Filter: 3 stages. ** //
// ** FIRDECIM1: M = 5, L = 15 ** //
// ** FIRDECIM1: M = 5, L = 20 ** //
// ** FIRDECIM1: M = 2, L = 50 ** //
// ******************************************************************************* //
// ** Revision History ** //
// ******************************************************************************* //
// ** ** //
// ** File : firdecim.v ** //
// ** Revision : 1 ** //
// ** Author : kaylangu ** //
// ** Date : August 13, 2008 ** //
// ** FileName : ** //
// ** Notes : Initial Release for ISAAC demo ** //
// ** ** //
// ** File : firdecim.v ** //
// ** Revision : 2 ** //
// ** Author : kaylangu ** //
// ** Date : February 9, 2009 ** //
// ** FileName : ** //
// ** Notes : Remove Sync signal ** //
// ** ** //
// ******************************************************************************* //
`timescale 1 ns / 100 ps
module firdecim
(/*AUTOARG*/
// Outputs
SigOut, DataValid, DataValid1, DataValid2, SigOut1, SigOut2,
// Inputs
CLK, ARST, InputValid, SigIn
);
//******************************************************************************//
//* Declarations *//
//******************************************************************************//
// DATA TYPE - PARAMETERS
parameter OWIDTH = 16;
parameter ACCUMWIDTH = 32;
parameter IWIDTH = 16;
// DATA TYPE - INPUTS AND OUTPUTS
output signed [(OWIDTH-1):0] SigOut ;
output signed [(ACCUMWIDTH-1):0] SigOut1;
output signed [(ACCUMWIDTH-1):0] SigOut2;
output DataValid;
output DataValid1;
output DataValid2;
input CLK;
input ARST;
input InputValid;
input signed [(IWIDTH-1):0] SigIn;
// DATA TYPE - WIRES
wire signed [(ACCUMWIDTH-1):0] SigOut_tmp;
//******************************************************************************//
//* Output Buffers *//
//******************************************************************************//
assign SigOut[(OWIDTH-1):0] = SigOut_tmp[(ACCUMWIDTH-3):(ACCUMWIDTH-OWIDTH-2)];
//******************************************************************************//
//* Submodules *//
//******************************************************************************//
firdecim_m5_n15 firdecim1
(//Inputs
.CLK (CLK),
.ARST (ARST),
.InputValid (InputValid),
.SigIn (SigIn[(IWIDTH-1):0]),
//Outputs
.DataValid (DataValid1),
.SigOut (SigOut1[(ACCUMWIDTH-1):0])
);
firdecim_m5_n25 firdecim2
(// Inputs
.CLK (CLK),
.ARST (ARST),
.InputValid (DataValid1),
.SigIn (SigOut1[(ACCUMWIDTH-3):(ACCUMWIDTH-OWIDTH-2)]),
// Outputs
.DataValid (DataValid2),
.SigOut (SigOut2[(ACCUMWIDTH-1):0])
);
firdecim_m2_n50 firdecim3
(// Inputs
.CLK (CLK),
.ARST (ARST),
.InputValid (DataValid2),
.SigIn (SigOut2[(ACCUMWIDTH-3):(ACCUMWIDTH-OWIDTH-2)]),
// Outputs
.DataValid (DataValid),
.SigOut (SigOut_tmp[(ACCUMWIDTH-1):0])
);
endmodule // firdecim
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O211AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__O211AI_BEHAVIORAL_PP_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__o211ai (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , C1, or0_out, B1 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O211AI_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; int a[1000005]; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int i, j, k, l, m, n, t, r, cnt; int flag = 0; long long ans = 0, an = 0; t = 1; while (t--) { cin >> n >> m; cout << min(n, m) + 1 << endl; int x, y; x = 0; y = m; while (x <= n && y >= 0) { cout << x << << y << endl; x++; y--; } } } |
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_64_16.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 16.0.0 Build 211 04/27/2016 SJ Standard Edition
// ************************************************************
//Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_64_16 (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [15:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [15:0] q;
output [5:0] usedw;
wire sub_wire0;
wire sub_wire1;
wire [15:0] sub_wire2;
wire [5:0] sub_wire3;
wire empty = sub_wire0;
wire full = sub_wire1;
wire [15:0] q = sub_wire2[15:0];
wire [5:0] usedw = sub_wire3[5:0];
scfifo scfifo_component (
.aclr (aclr),
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.empty (sub_wire0),
.full (sub_wire1),
.q (sub_wire2),
.usedw (sub_wire3),
.almost_empty (),
.almost_full (),
.eccstatus (),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Stratix V",
scfifo_component.lpm_numwords = 64,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 16,
scfifo_component.lpm_widthu = 6,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "64"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "16"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "64"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "6"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: usedw 0 0 6 0 OUTPUT NODEFVAL "usedw[5..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: usedw 0 0 6 0 @usedw 0 0 6 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_64_16.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_64_16.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_64_16.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_64_16.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_64_16_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_64_16_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; class Solution { public: long long maximize(vector<int>& nums, int x) { int n = nums.size(); vector<vector<long long>> dp(3, vector<long long>(n + 1, 0)); long long res = 0; for (int i = 0; i < n; ++i) { long long num = nums[i]; dp[0][i + 1] = max(0LL, dp[0][i] + num); dp[1][i + 1] = max(0LL, max(dp[0][i], dp[1][i]) + num * x); dp[2][i + 1] = max(0LL, max(dp[2][i], dp[1][i]) + num); } for (int j = 0; j < 3; ++j) { for (int i = 0; i <= n; ++i) { res = max(res, dp[j][i]); } } return res; } }; int main(int argc, char** argv) { ios::sync_with_stdio(false); cin.tie(0); Solution sol; int n, x; cin >> n >> x; vector<int> nums(n); for (int i = 0; i < n; ++i) { cin >> nums[i]; } cout << sol.maximize(nums, x) << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int tinf = (int)1e9 + 7; const long long inf = (long long)1e18 + 7; const int N = 1e5 + 5; long long n, x[10000], y[10000], ans; int main() { { ios ::sync_with_stdio(false); cin.tie(0); } cin >> n; for (int i = 0; i < n; i++) cin >> x[i] >> y[i]; for (int i = 1; i < n - 1; i++) if (y[i] > y[i - 1] && x[i + 1] < x[i]) ans++; else if (y[i] < y[i - 1] && x[i + 1] > x[i]) ans++; else if (x[i] > x[i - 1] && y[i + 1] > y[i]) ans++; else if (x[i] < x[i - 1] && y[i + 1] < y[i]) ans++; cout << ans; } |
module top;
/*AUTOLOGIC*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
logic sig1; // From u_x of x.v
logic [A-1:0] sig2; // From u_x of x.v
logic [A-1:0] [B-1:0] sig3; // From u_x of x.v
logic [A-1:0][B-1:0] [C-1:0] sig4; // From u_x of x.v
logic [A-1:0][B-1:0][C-1:0] [D-1:0] sig5; // From u_x of x.v
logic vsig1; // From u_x of x.v
logic vsig2 [W-1:0]; // From u_x of x.v
logic vsig3 [W-1:0][X-1:0]; // From u_x of x.v
logic vsig4 [W-1:0][X-1:0][Y-1:0];// From u_x of x.v
logic vsig5 [W-1:0][X-1:0][Y-1:0][Z-1:0];// From u_x of x.v
logic zsig1; // From u_x of x.v
logic [A-1:0] zsig2 [W-1:0]; // From u_x of x.v
logic [A-1:0] [B-1:0] zsig3 [W-1:0][X-1:0]; // From u_x of x.v
logic [A-1:0][B-1:0] [C-1:0] zsig4 [W-1:0][X-1:0][Y-1:0];// From u_x of x.v
logic [A-1:0][B-1:0][C-1:0] [D-1:0] zsig5 [W-1:0][X-1:0][Y-1:0][Z-1:0];// From u_x of x.v
// End of automatics
x u_x (/*AUTOINST*/
// Outputs
.sig1 (sig1),
.sig2 (sig2[A-1:0]),
.sig3 (sig3/*[A-1:0][B-1:0]*/),
.sig4 (sig4/*[A-1:0][B-1:0][C-1:0]*/),
.sig5 (sig5/*[A-1:0][B-1:0][C-1:0][D-1:0]*/),
.vsig1 (vsig1),
.vsig2 (vsig2/*.[W-1:0]*/),
.vsig3 (vsig3/*.[W-1:0][X-1:0]*/),
.vsig4 (vsig4/*.[W-1:0][X-1:0][Y-1:0]*/),
.vsig5 (vsig5/*.[W-1:0][X-1:0][Y-1:0][Z-1:0]*/),
.zsig1 (zsig1),
.zsig2 (zsig2/*[A-1:0].[W-1:0]*/),
.zsig3 (zsig3/*[A-1:0][B-1:0].[W-1:0][X-1:0]*/),
.zsig4 (zsig4/*[A-1:0][B-1:0][C-1:0].[W-1:0][X-1:0][Y-1:0]*/),
.zsig5 (zsig5/*[A-1:0][B-1:0][C-1:0][D-1:0].[W-1:0][X-1:0][Y-1:0][Z-1:0]*/));
endmodule // top
module x;
output sig1;
output [A-1:0] sig2;
output [A-1:0][B-1:0] sig3;
output [A-1:0][B-1:0][C-1:0] sig4;
output [A-1:0][B-1:0][C-1:0][D-1:0] sig5;
output vsig1;
output vsig2 [W-1:0];
output vsig3 [W-1:0][X-1:0];
output vsig4 [W-1:0][X-1:0][Y-1:0];
output vsig5 [W-1:0][X-1:0][Y-1:0][Z-1:0];
output zsig1;
output [A-1:0] zsig2 [W-1:0];
output [A-1:0][B-1:0] zsig3 [W-1:0][X-1:0];
output [A-1:0][B-1:0][C-1:0] zsig4 [W-1:0][X-1:0][Y-1:0];
output [A-1:0][B-1:0][C-1:0][D-1:0] zsig5 [W-1:0][X-1:0][Y-1:0][Z-1:0];
endmodule
|
//Legal Notice: (C)2019 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_dut_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "onchip_mem.hex";
output [ 31: 0] readdata;
input [ 10: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [ 31: 0] writedata;
wire clocken0;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 2048,
the_altsyncram.numwords_a = 2048,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 11;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: audio_fifo.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.2 Build 151 09/26/2007 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module audio_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input aclr;
input [31:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output rdempty;
output wrfull;
wire sub_wire0;
wire sub_wire1;
wire [31:0] sub_wire2;
wire rdempty = sub_wire0;
wire wrfull = sub_wire1;
wire [31:0] q = sub_wire2[31:0];
dcfifo dcfifo_component (
.wrclk (wrclk),
.rdreq (rdreq),
.aclr (aclr),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.rdempty (sub_wire0),
.wrfull (sub_wire1),
.q (sub_wire2)
// synopsys translate_off
,
.rdfull (),
.rdusedw (),
.wrempty (),
.wrusedw ()
// synopsys translate_on
);
defparam
dcfifo_component.intended_device_family = "Cyclone II",
dcfifo_component.lpm_hint = "MAXIMIZE_SPEED=7,",
dcfifo_component.lpm_numwords = 256,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 32,
dcfifo_component.lpm_widthu = 8,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 5,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "ON",
dcfifo_component.wrsync_delaypipe = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "32"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "32"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=7,"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL audio_fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL audio_fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL audio_fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL audio_fifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL audio_fifo_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL audio_fifo_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL audio_fifo_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL audio_fifo_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR4BB_SYMBOL_V
`define SKY130_FD_SC_LS__OR4BB_SYMBOL_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__or4bb (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N,
input D_N,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR4BB_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; map<string, int> mapp; int mina = 10000000, minb = 10000000, minc = 10000000, minab = 10000000, minac = 10000000, minbc = 10000000, min3 = 10000000; int x; string na; for (int i = 0; i < n; i++) { cin >> x >> na; sort(na.begin(), na.end()); if (na.length() == 3) { min3 = min(x, min3); } else if (na == A ) { mina = min(x, mina); } else if (na == B ) { minb = min(x, minb); } else if (na == C ) { minc = min(x, minc); } else if (na == AB ) { minab = min(x, minab); } else if (na == AC ) { minac = min(x, minac); } else if (na == BC ) { minbc = min(x, minbc); } } min3 = min(min3, minab + minc); min3 = min(min3, minac + minb); min3 = min(min3, minbc + mina); min3 = min(min3, mina + minb + minc); min3 = min(min3, minab + minbc); min3 = min(min3, minab + minac); min3 = min(min3, minac + minbc); if (min3 > 1000000) { cout << -1 << endl; } else { cout << min3 << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; map<char, char> q; int main() { char a[30], b[30]; scanf( %s , a); scanf( %s , b); q.clear(); for (int i = 0; i < 26; i++) { q[a[i]] = b[i]; q[a[i] - 32] = b[i] - 32; } char aim[2000]; scanf( %s , aim); for (int i = 0; aim[i]; i++) { if (q[aim[i]]) printf( %c , q[aim[i]]); else printf( %c , aim[i]); } printf( n ); } |
// DESCRIPTION: Verilator: Dotted reference that uses another dotted reference
// as the select expression
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
package Pkg;
localparam PKG_PARAM = 1;
endpackage
package PkgImp;
import Pkg::*;
export Pkg::*;
endpackage
class Cls;
int member = 1;
function void method;
endfunction
endclass
interface Iface;
logic ifsig;
modport mp(input ifsig);
endinterface
module t (/*AUTOARG*/
// Inputs
clk, in
);
input clk;
input in;
// verilator lint_off UNPACKED
typedef enum {
ZERO,
ONE = 1
} e_t;
typedef struct packed {
e_t a;
} ps_t;
typedef struct {
logic signed [2:0] a;
} us_t;
typedef union {
logic a;
} union_t;
const ps_t ps[3];
us_t us;
union_t unu;
int array[3];
initial array = '{1,2,3};
reg [15:0] pubflat /*verilator public_flat_rw @(posedge clk) */;
reg [15:0] pubflat_r;
wire [15:0] pubflat_w = pubflat;
int fd;
int i;
int q[$];
int assoc[string];
int dyn[];
task t;
$display("stmt");
endtask
function int f(input int v);
$display("stmt");
return v == 0 ? 99 : ~v + 1;
endfunction
sub sub();
initial begin
int other;
begin //unnamed
for (int i = 0; i < 3; ++i) begin
other = f(i);
$display("stmt %d %d", i, other);
t();
end
end
begin : named
$display("stmt");
end : named
end
final begin
$display("stmt");
end
always @ (in) begin
$display("stmt");
end
always @ (posedge clk) begin
$display("posedge clk");
pubflat_r <= pubflat_w;
end
always @ (negedge clk) begin
$display("negedge clk, pfr = %x", pubflat_r);
end
int cyc;
int fo;
int sum;
real r;
string str;
always_ff @ (posedge clk) begin
cyc <= cyc + 1;
r <= r + 0.01;
fo = cyc;
sub.inc(fo, sum);
sum = sub.f(sum);
$display("[%0t] sum = %d", $time, sum);
$display("a?= %d", $c(1) ? $c32(20) : $c32(30));
$c(";");
$display("%d", $c("0"));
fd = $fopen("/dev/null");
$fclose(fd);
fd = $fopen("/dev/null", "r");
$fgetc(fd); // stmt
$fflush(fd);
$fscanf(fd, "%d", sum);
$fdisplay("i = ", sum);
$fwrite(fd, "hello");
$readmemh(fd, array);
$readmemh(fd, array, 0);
$readmemh(fd, array, 0, 0);
sum = 0;
for (int i = 0; i < cyc; ++i) begin
sum += i;
if (sum > 10) break;
else sum += 1;
end
if (cyc == 99) $finish;
if (cyc == 100) $stop;
case (in) // synopsys full_case parallel_case
1: $display("1");
default: $display("default");
endcase
priority case (in)
1: $display("1");
default: $display("default");
endcase
unique case (in)
1: $display("1");
default: $display("default");
endcase
unique0 case (in)
1: $display("1");
default: $display("default");
endcase
if (in) $display("1"); else $display("0");
priority if (in) $display("1"); else $display("0");
unique if (in) $display("1"); else $display("0");
unique0 if (in) $display("1"); else $display("0");
$display($past(cyc), $past(cyc, 1));
str = $sformatf("cyc=%d", cyc);
$display("str = %s", str);
$display("%% [%t] [%t] to=%o td=%d", $time, $realtime, $time, $time);
$sscanf("foo=5", "foo=%d", i);
$printtimescale;
if (i != 5) $stop;
sum = $random;
sum = $random(10);
sum = $urandom;
sum = $urandom(10);
if (Pkg::PKG_PARAM != 1) $stop;
sub.r = 62.0;
$display("%g", $log10(r));
$display("%g", $ln(r));
$display("%g", $exp(r));
$display("%g", $sqrt(r));
$display("%g", $floor(r));
$display("%g", $ceil(r));
$display("%g", $sin(r));
$display("%g", $cos(r));
$display("%g", $tan(r));
$display("%g", $asin(r));
$display("%g", $acos(r));
$display("%g", $atan(r));
$display("%g", $sinh(r));
$display("%g", $cosh(r));
$display("%g", $tanh(r));
$display("%g", $asinh(r));
$display("%g", $acosh(r));
$display("%g", $atanh(r));
force sum = 10;
repeat (2) if (sum != 10) $stop;
release sum;
end
endmodule
module sub();
task inc(input int i, output int o);
o = {1'b0, i[31:1]} + 32'd1;
endtask
function int f(input int v);
if (v == 0) return 33;
return {31'd0, v[2]} + 32'd1;
endfunction
real r;
endmodule
package p;
logic pkgvar;
endpackage
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_MUX_2TO1_N_SYMBOL_V
`define SKY130_FD_SC_HS__UDP_MUX_2TO1_N_SYMBOL_V
/**
* udp_mux_2to1_N: Two to one multiplexer with inverting output
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_mux_2to1_N (
//# {{data|Data Signals}}
input A0,
input A1,
output Y ,
//# {{control|Control Signals}}
input S
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_MUX_2TO1_N_SYMBOL_V
|
`default_nettype none
module reset_test_gate (clk, reset, ctrl, din, sel, dout);
input wire clk;
input wire reset;
input wire [4:0] ctrl;
input wire [1:0] din;
input wire [0:0] sel;
output reg [31:0] dout;
reg [1:0] i;
wire [0:0] rval;
assign rval = {reset, 1'b0 };
always @(posedge clk)
begin
case (|(reset))
1'b 1:
begin
case (({(0)*(rval)})+(0))
0:
dout[31:0] <= 57005;
1:
dout[31:1] <= 57005;
2:
dout[31:2] <= 57005;
3:
dout[31:3] <= 57005;
4:
dout[31:4] <= 57005;
5:
dout[31:5] <= 57005;
6:
dout[31:6] <= 57005;
7:
dout[31:7] <= 57005;
8:
dout[31:8] <= 57005;
9:
dout[31:9] <= 57005;
10:
dout[31:10] <= 57005;
11:
dout[31:11] <= 57005;
12:
dout[31:12] <= 57005;
13:
dout[31:13] <= 57005;
14:
dout[31:14] <= 57005;
15:
dout[31:15] <= 57005;
16:
dout[31:16] <= 57005;
17:
dout[31:17] <= 57005;
18:
dout[31:18] <= 57005;
19:
dout[31:19] <= 57005;
20:
dout[31:20] <= 57005;
21:
dout[31:21] <= 57005;
22:
dout[31:22] <= 57005;
23:
dout[31:23] <= 57005;
24:
dout[31:24] <= 57005;
25:
dout[31:25] <= 57005;
26:
dout[31:26] <= 57005;
27:
dout[31:27] <= 57005;
28:
dout[31:28] <= 57005;
29:
dout[31:29] <= 57005;
30:
dout[31:30] <= 57005;
31:
dout[31:31] <= 57005;
endcase
i = 1;
end
endcase
case (({(ctrl)*(sel)})+(0))
0:
dout[31:0] <= din;
1:
dout[31:1] <= din;
2:
dout[31:2] <= din;
3:
dout[31:3] <= din;
4:
dout[31:4] <= din;
5:
dout[31:5] <= din;
6:
dout[31:6] <= din;
7:
dout[31:7] <= din;
8:
dout[31:8] <= din;
9:
dout[31:9] <= din;
10:
dout[31:10] <= din;
11:
dout[31:11] <= din;
12:
dout[31:12] <= din;
13:
dout[31:13] <= din;
14:
dout[31:14] <= din;
15:
dout[31:15] <= din;
16:
dout[31:16] <= din;
17:
dout[31:17] <= din;
18:
dout[31:18] <= din;
19:
dout[31:19] <= din;
20:
dout[31:20] <= din;
21:
dout[31:21] <= din;
22:
dout[31:22] <= din;
23:
dout[31:23] <= din;
24:
dout[31:24] <= din;
25:
dout[31:25] <= din;
26:
dout[31:26] <= din;
27:
dout[31:27] <= din;
28:
dout[31:28] <= din;
29:
dout[31:29] <= din;
30:
dout[31:30] <= din;
31:
dout[31:31] <= din;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; constexpr long long N = 600500; constexpr long long D = 2000010; constexpr long double EPS = 1e-8; ofstream fout; ifstream fin; int flag = -1; long long n, m, k; vector<vector<int> > v; vector<int> h; vector<int> was; bool comp(int a, int b) { return h[a] > h[b]; } multiset<int, bool (*)(int, int)> s(comp); void dfs(int x) { int o = 0; was[x] = 1; for (auto &y : (v[x])) { if (!was[y]) { dfs(y); o = max(o, h[y]); } } h[x] = o + 1; } void dfs1(int x) { was[x] = 1; int u, m = -1; for (auto &y : (v[x])) { if (!was[y]) { if (h[y] > m) { m = h[y]; u = y; } } } if (m == -1) return; for (auto &y : (v[x])) { if (!was[y]) { if (y == u) { dfs1(y); } else { s.insert(y); } } } } void solve() { long long a, b; cin >> n >> k; s.clear(); v.clear(); h.clear(); was.clear(); v.resize(n); h.resize(n); was.resize(n); for (long long i = 0; i < (n - 1); i++) { cin >> a >> b; a--; b--; v[a].push_back(b); v[b].push_back(a); } dfs(0); s.insert(0); fill(was.begin(), was.end(), 0); a = k; k = 0; while (k < a && !s.empty()) { k++; int x = *s.begin(); s.erase(s.begin()); dfs1(x); } long long mx = -((long long)1e15); long long e = count(was.begin(), was.end(), 1); if (k < a) { for (long long i = (k); i < (a + 1); i++) { mx = max(mx, (e - i) * (i)); } } else { mx = ((long long)1e15); long long p = count(was.begin(), was.end(), 0); for (long long i = (0); i < (p + 1); i++) { mx = min(mx, (e - a + (p - i)) * (a - i)); } } cout << mx << n ; } signed main(signed argc, char *argv[]) { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cout.precision(14); cout.fixed; srand(time(0)); fout.precision(14); fout.fixed; int tt = 1; while (tt--) { solve(); } fout.close(); fin.close(); } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); long long p, k; cin >> p >> k; long long d = (k - p) / k; if ((((k - p) % k) + k) % k == 0 || (d <= 0 && p > k)) d--; vector<long long> res; res.push_back(d); if (k > p) return cout << 1 n << p, 0; while (1) { long long r = res.back(); d = (k - r) / k; if ((((k - r) % k) + k) % k == 0 || d <= 0) d--; res.push_back(d); if (d < k && d >= 0) break; } cout << res.size() + 1 << endl; long long last = p; for (int i = 0; i < res.size(); i++) { cout << k * res[i] + last << ; last = res[i]; } cout << d; return 0; } |
`timescale 1ns / 1ns
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/06/2013 06:51:42 PM
// Design Name:
// Module Name: main
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module main (
// Clk Input
input clk_in,
// Data Pins
output reset,
output sclk, // Half the speed of data_clk, a 20,000th the speed of clk
output sdata,
output scmd,
// Power Pins
output vbat,
output vdd,
// LED String Data Pins
output status_led,
output light_clk,
output light_data
);
// GPIO OUT MAP
// 0 - VDD
// 1 - VBAT
// 2 - RESET
// 3 - SCLK
// 4 - SDATA
// 5 - SCMD
wire [31 : 0] gpio;
zynq_1_wrapper cpu(.gpio(gpio));
assign vdd = gpio[0];
assign vbat = gpio[1];
assign reset = gpio[2];
assign sclk = gpio[3];
assign sdata = gpio[4];
assign scmd = gpio[5];
assign status_led = gpio[6];
assign light_clk = gpio[7];
assign light_data = gpio[8];
wire clk;
IBUFG clk_buf(.I(clk_in), .O(clk)); // Clock Buffer Conversion
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__MAJ3_SYMBOL_V
`define SKY130_FD_SC_LS__MAJ3_SYMBOL_V
/**
* maj3: 3-input majority vote.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__maj3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__MAJ3_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EDFXTP_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__EDFXTP_PP_BLACKBOX_V
/**
* edfxtp: Delay flop with loopback enable, non-inverted clock,
* single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__edfxtp (
Q ,
CLK ,
D ,
DE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__EDFXTP_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int N, A, B, X, Ans = 0, C = 0; int main() { cin >> N >> A >> B; for (int i = 1; i <= N; i++) { cin >> X; if (X == 1) { if (A > 0) A--; else if (B > 0) C++, B--; else if (C > 0) C--; else Ans++; } else { if (B > 0) B--; else Ans += 2; } } cout << Ans; return 0; } |
#include <bits/stdc++.h> const int N = 60; const int M = 11; const int MOD = 1e9 + 7; int binom[N + 1][N + 1], n, a[N], parent[N], inDegree[N], v0[N], v1[N], msk1[N], dp[N + 1][1 << M]; int findRoot(int u) { if (parent[u] != u) { parent[u] = findRoot(parent[u]); } return parent[u]; } void add(int &x, int a) { x += a; if (x >= MOD) { x -= MOD; } } int solve(int n0, int n1) { assert(n0 <= M); for (int j = 0; j < n1; ++j) { msk1[j] = 0; } for (int i = 0; i < n0; ++i) { for (int j = 0; j < n1; ++j) { if (v1[j] % v0[i] == 0) { msk1[j] |= 1 << i; } } } for (int i = 1; i <= n1; ++i) { for (int msk = 0; msk < 1 << n0; ++msk) { dp[i][msk] = 0; } } for (int i = 0; i < n1; ++i) { add(dp[1][msk1[i]], 1); } for (int i = 1; i < n1; ++i) { for (int msk = 0; msk < 1 << n0; ++msk) { if (dp[i][msk]) { int cnt = 0; for (int j = 0; j < n1; ++j) { if ((msk1[j] & msk) == msk1[j]) { cnt++; } else if (msk1[j] & msk) { add(dp[i + 1][msk | msk1[j]], dp[i][msk]); } } if (i < cnt) { add(dp[i + 1][msk], 1LL * (cnt - i) * dp[i][msk] % MOD); } } } } return dp[n1][(1 << n0) - 1]; } int main() { for (int i = 0; i <= N; ++i) { binom[i][0] = 1; for (int j = 1; j <= i; ++j) { binom[i][j] = (binom[i - 1][j - 1] + binom[i - 1][j]) % MOD; } } while (scanf( %d , &n) == 1) { for (int i = 0; i < n; ++i) { scanf( %d , a + i); parent[i] = i; inDegree[i] = 0; } for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { if (i != j && a[j] % a[i] == 0) { if (findRoot(i) != findRoot(j)) { parent[findRoot(i)] = findRoot(j); } inDegree[j]++; } } } int result = 1, size = 0; for (int group = 0; group < n; ++group) { if (parent[group] == group) { int n0 = 0, n1 = 0; for (int i = 0; i < n; ++i) { if (findRoot(i) == group) { if (inDegree[i]) { v1[n1++] = a[i]; } else { v0[n0++] = a[i]; } } } if (n1) { size += n1 - 1; result = 1LL * result * binom[size][n1 - 1] % MOD * solve(n0, n1) % MOD; } } } printf( %d n , result); } } |
//Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module switch_pio (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 17: 0] in_port;
input reset_n;
wire clk_en;
wire [ 17: 0] data_in;
wire [ 17: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {18 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {{{32 - 18}{1'b0}},read_mux_out};
end
assign data_in = in_port;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MACRO_SPARECELL_FUNCTIONAL_V
`define SKY130_FD_SC_HD__MACRO_SPARECELL_FUNCTIONAL_V
/**
* macro_sparecell: Macro cell for metal-mask-only revisioning,
* containing inverter, 2-input NOR, 2-input NAND,
* and constant cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../conb/sky130_fd_sc_hd__conb.v"
`include "../nor2/sky130_fd_sc_hd__nor2.v"
`include "../inv/sky130_fd_sc_hd__inv.v"
`include "../nand2/sky130_fd_sc_hd__nand2.v"
`celldefine
module sky130_fd_sc_hd__macro_sparecell (
LO
);
// Module ports
output LO;
// Local signals
wire nor2left ;
wire invleft ;
wire nor2right;
wire invright ;
wire nd2left ;
wire nd2right ;
wire tielo ;
wire net7 ;
// Name Output Other arguments
sky130_fd_sc_hd__inv_2 inv0 (.A(nor2left) , .Y(invleft) );
sky130_fd_sc_hd__inv_2 inv1 (.A(nor2right), .Y(invright) );
sky130_fd_sc_hd__nor2_2 nor20 (.B(nd2left) , .A(nd2left), .Y(nor2left) );
sky130_fd_sc_hd__nor2_2 nor21 (.B(nd2right) , .A(nd2right), .Y(nor2right));
sky130_fd_sc_hd__nand2_2 nand20 (.B(tielo) , .A(tielo), .Y(nd2right) );
sky130_fd_sc_hd__nand2_2 nand21 (.B(tielo) , .A(tielo), .Y(nd2left) );
sky130_fd_sc_hd__conb_1 conb0 (.LO(tielo) , .HI(net7) );
buf buf0 (LO , tielo );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__MACRO_SPARECELL_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; const long long MAXN = 1e2 + 7; long long p[MAXN], dp[MAXN]; pair<long long, long long> fig[MAXN]; int32_t main() { long long n; cin >> n; for (long long i = 0; i < n; ++i) cin >> fig[i].second >> fig[i].first; sort(fig, fig + n); long long t; cin >> t; for (long long i = 1; i <= t; ++i) cin >> p[i]; p[t + 1] = (1LL << 60); long long pos = 1, ans = 0, sum = 0; for (long long i = 0; i < n; ++i) { while (fig[i].second) { if (p[pos] - sum > fig[i].second) { sum += fig[i].second; ans += fig[i].second * pos * fig[i].first; fig[i].second = 0; } else { ans += fig[i].first * (p[pos] - sum) * pos; fig[i].second -= p[pos] - sum; sum = p[pos]; pos++; } } } cout << ans << n ; } |
`timescale 1 ns / 1 ns
//////////////////////////////////////////////////////////////////////////////////
// Company: Rehkopf
// Engineer: Rehkopf
//
// Create Date: 01:13:46 05/09/2009
// Design Name:
// Module Name: address
// Project Name:
// Target Devices:
// Tool versions:
// Description: Address logic w/ SaveRAM masking
//
// Dependencies:
//
// Revision:
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module address(
input CLK,
input [15:0] featurebits, // peripheral enable/disable
input [2:0] MAPPER, // MCU detected mapper
input [23:0] SNES_ADDR, // requested address from SNES
input [7:0] SNES_PA, // peripheral address from SNES
input SNES_ROMSEL, // ROMSEL from SNES
output [23:0] ROM_ADDR, // Address to request from SRAM0
output ROM_HIT, // enable SRAM0
output IS_SAVERAM, // address/CS mapped as SRAM?
output IS_ROM, // address mapped as ROM?
output IS_WRITABLE, // address somehow mapped as writable area?
input [23:0] SAVERAM_MASK,
input [23:0] ROM_MASK,
output msu_enable,
output srtc_enable,
output use_bsx,
output bsx_tristate,
input [14:0] bsx_regs,
output dspx_enable,
output dspx_dp_enable,
output dspx_a0,
output r213f_enable,
output r2100_hit,
output snescmd_enable,
output nmicmd_enable,
output return_vector_enable,
output branch1_enable,
output branch2_enable,
output branch3_enable
);
/* feature bits. see src/fpga_spi.c for mapping */
parameter [2:0]
FEAT_DSPX = 0,
FEAT_ST0010 = 1,
FEAT_SRTC = 2,
FEAT_MSU1 = 3,
FEAT_213F = 4,
FEAT_2100 = 6
;
wire [23:0] SRAM_SNES_ADDR;
/* currently supported mappers:
Index Mapper
000 HiROM
001 LoROM
010 ExHiROM (48-64Mbit)
011 BS-X
100 ExLoROM (StarOCean and SFA2)
110 brainfuck interleaved 96MBit Star Ocean =)
111 menu (ROM in upper SRAM)
*/
// active high to select ROM in banks 00-3f,80-bf:8000-ffff and 40-7d,c0-ff:0000-ffff
// (decoded by SNES)
assign IS_ROM = ~SNES_ROMSEL;
// select backup RAM when
// ST0010 chip is present, SRAM is mapped to
assign IS_SAVERAM = SAVERAM_MASK[0]&(featurebits[FEAT_ST0010]?((SNES_ADDR[22:19] == 4'b1101) & &(~SNES_ADDR[15:12]) & SNES_ADDR[11])
// for HiROM, ExtHIROM or interleaved StarOcean -> $3X:[$6000-$7FFF] or $BX:[$6000-$7FFF]
:((MAPPER == 3'b000 || MAPPER == 3'b010 || MAPPER == 3'b110) ? (!SNES_ADDR[22] & SNES_ADDR[21] & &SNES_ADDR[14:13] & !SNES_ADDR[15])
// for ExtLoROM -> $7X:[$6000-$7FFF]
:(MAPPER == 3'b100) ? ((SNES_ADDR[23:19] == 5'b01110) && (SNES_ADDR[15:13] == 3'b011))
// LoROM: SRAM @ Bank 0x70-0x7d, 0xf0-0xff
// Offset 0000-7fff for ROM >= 32 MBit, otherwise 0000-ffff
:(MAPPER == 3'b001)? (&SNES_ADDR[22:20] & (~SNES_ROMSEL) & (~SNES_ADDR[15] | ~ROM_MASK[21]))
// BS-X: SRAM @ Bank 0x10-0x17 Offset 5000-5fff
:(MAPPER == 3'b011) ? ((SNES_ADDR[23:19] == 5'b00010) & (SNES_ADDR[15:12] == 4'b0101) )
// Menu mapper: 8Mbit "SRAM" @ Bank 0xf0-0xff (entire banks!)
:(MAPPER == 3'b111) ? (&SNES_ADDR[23:20])
: 1'b0));
// '1' to signal access to cartrigde writable range (Backup RAM or BS-X RAM)
assign IS_WRITABLE = IS_SAVERAM;
/* BSX regs:
Index Function
1 0=map flash to ROM area; 1=map PRAM to ROM area
2 1=HiROM; 0=LoROM
3 1=Mirror PRAM @60-6f:0000-ffff
5 1=DO NOT mirror PRAM @40-4f:0000-ffff
6 1=DO NOT mirror PRAM @50-5f:0000-ffff
7 1=map BSX cartridge ROM @00-1f:8000-ffff
8 1=map BSX cartridge ROM @80-9f:8000-ffff
*/
// HiROM
assign SRAM_SNES_ADDR = ((MAPPER == 3'b000) ? (IS_SAVERAM ? 24'hE00000 + ({SNES_ADDR[20:16], SNES_ADDR[12:0]} & SAVERAM_MASK)
: ({1'b0, SNES_ADDR[22:0]} & ROM_MASK))
// LoROM
:(MAPPER == 3'b001) ? (IS_SAVERAM ? 24'hE00000 + ({SNES_ADDR[20:16], SNES_ADDR[14:0]} & SAVERAM_MASK)
: ({1'b0, ~SNES_ADDR[23], SNES_ADDR[22:16], SNES_ADDR[14:0]} & ROM_MASK))
// ExtHiROM
:(MAPPER == 3'b010) ? (IS_SAVERAM ? 24'hE00000 + ({7'b0000000, SNES_ADDR[19:16], SNES_ADDR[12:0]} & SAVERAM_MASK)
: ({1'b0, !SNES_ADDR[23], SNES_ADDR[21:0]} & ROM_MASK))
// ExtLoROM
:(MAPPER == 3'b100) ? (IS_SAVERAM ? 24'hE00000 + ({7'b0000000, SNES_ADDR[19:16], SNES_ADDR[12:0]} & SAVERAM_MASK)
: ({1'b0, !SNES_ADDR[23], SNES_ADDR[21:0]} & ROM_MASK))
// interleaved StarOcean
:(MAPPER == 3'b110) ? (IS_SAVERAM ? 24'hE00000 + ((SNES_ADDR[14:0] - 15'h6000) & SAVERAM_MASK)
:(SNES_ADDR[15] ? ({1'b0, SNES_ADDR[23:16], SNES_ADDR[14:0]})
:({2'b10, SNES_ADDR[23], SNES_ADDR[21:16], SNES_ADDR[14:0]}) ) )
// menu
:(MAPPER == 3'b111) ? (IS_SAVERAM ? SNES_ADDR
: (({1'b0, SNES_ADDR[22:0]} & ROM_MASK) + 24'hC00000) )
: 24'b0);
assign ROM_ADDR = SRAM_SNES_ADDR;
// '1' when accesing PSRAM for ROM, Backup RAM, BS-X RAM
assign ROM_HIT = IS_ROM | IS_WRITABLE;
// '1' when accessing to MSU register map $2000:$2007
assign msu_enable = featurebits[FEAT_MSU1] & (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfff8) == 16'h2000));
// MAGNO -> disabled for S-DD1 core
//assign use_bsx = (MAPPER == 3'b011);
assign use_bsx = 1'b0;
// MAGNO -> disabled for S-DD1 core
//assign srtc_enable = featurebits[FEAT_SRTC] & (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfffe) == 16'h2800));
assign srtc_enable = 1'b0;
assign r213f_enable = featurebits[FEAT_213F] & (SNES_PA == 8'h3f);
assign r2100_hit = (SNES_PA == 8'h00);
assign snescmd_enable = ({SNES_ADDR[22], SNES_ADDR[15:9]} == 8'b0_0010101);
assign nmicmd_enable = (SNES_ADDR == 24'h002BF2);
assign return_vector_enable = (SNES_ADDR == 24'h002A6C);
assign branch1_enable = (SNES_ADDR == 24'h002A1F);
assign branch2_enable = (SNES_ADDR == 24'h002A59);
assign branch3_enable = (SNES_ADDR == 24'h002A5E);
endmodule
|
// $Id: rtr_next_hop_addr.v 5188 2012-08-30 00:31:31Z dub $
/*
Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// module to determine the address of the next hop router
//==============================================================================
module rtr_next_hop_addr
(router_address, dest_info, lar_info, next_router_address);
`include "c_functions.v"
`include "c_constants.v"
//---------------------------------------------------------------------------
// parameters
//---------------------------------------------------------------------------
// number of resource classes (e.g. minimal, adaptive)
parameter num_resource_classes = 2;
// number of routers in each dimension
parameter num_routers_per_dim = 4;
// number of dimensions in network
parameter num_dimensions = 2;
// number of nodes per router (a.k.a. consentration factor)
parameter num_nodes_per_router = 1;
// connectivity within each dimension
parameter connectivity = `CONNECTIVITY_LINE;
// select routing function type
parameter routing_type = `ROUTING_TYPE_PHASED_DOR;
//---------------------------------------------------------------------------
// derived parameters
//---------------------------------------------------------------------------
// width required to select individual resource class
localparam resource_class_idx_width = clogb(num_resource_classes);
// width required to select individual router in a dimension
localparam dim_addr_width = clogb(num_routers_per_dim);
// width required to select individual router in network
localparam router_addr_width = num_dimensions * dim_addr_width;
// width required to select individual node at current router
localparam node_addr_width = clogb(num_nodes_per_router);
// total number of bits required for storing routing information
localparam dest_info_width
= (routing_type == `ROUTING_TYPE_PHASED_DOR) ?
(num_resource_classes * router_addr_width + node_addr_width) :
-1;
// number of adjacent routers in each dimension
localparam num_neighbors_per_dim
= ((connectivity == `CONNECTIVITY_LINE) ||
(connectivity == `CONNECTIVITY_RING)) ?
2 :
(connectivity == `CONNECTIVITY_FULL) ?
(num_routers_per_dim - 1) :
-1;
// number of input and output ports on router
localparam num_ports
= num_dimensions * num_neighbors_per_dim + num_nodes_per_router;
// width required to select an individual port
localparam port_idx_width = clogb(num_ports);
// width required for lookahead routing information
localparam lar_info_width = port_idx_width + resource_class_idx_width;
//---------------------------------------------------------------------------
// interface
//---------------------------------------------------------------------------
// current router's address
input [0:router_addr_width-1] router_address;
// routing information
input [0:dest_info_width-1] dest_info;
// lookahead routing information
input [0:lar_info_width-1] lar_info;
// lookahead routing information for next router
output [0:router_addr_width-1] next_router_address;
wire [0:router_addr_width-1] next_router_address;
//---------------------------------------------------------------------------
// implementation
//---------------------------------------------------------------------------
wire [0:port_idx_width-1] route_port;
assign route_port = lar_info[0:port_idx_width-1];
generate
case(routing_type)
`ROUTING_TYPE_PHASED_DOR:
begin
wire [0:num_resource_classes*router_addr_width-1] dest_addr_orc;
assign dest_addr_orc
= dest_info[0:num_resource_classes*router_addr_width-1];
wire [0:router_addr_width-1] dest_addr;
if(num_resource_classes == 1)
assign dest_addr = dest_addr_orc;
else
begin
wire [0:resource_class_idx_width-1] route_rcsel;
assign route_rcsel
= lar_info[port_idx_width:
port_idx_width+resource_class_idx_width-1];
assign dest_addr
= dest_addr_orc[route_rcsel*router_addr_width +:
router_addr_width];
end
genvar dim;
for(dim = 0; dim < num_dimensions; dim = dim + 1)
begin:dims
wire [0:dim_addr_width-1] curr_dim_addr;
assign curr_dim_addr
= router_address[dim*dim_addr_width:
(dim+1)*dim_addr_width-1];
wire [0:dim_addr_width-1] next_dim_addr;
case(connectivity)
`CONNECTIVITY_LINE, `CONNECTIVITY_RING:
begin
// The first port in each dimension connects to
// neighbors with smaller addresses, while the second
// one connects to those with larger ones.
wire route_down;
assign route_down = (route_port == dim*2);
wire route_up;
assign route_up = (route_port == dim*2+1);
case(connectivity)
`CONNECTIVITY_LINE:
begin
// NOTE: In two's complement, +1 is represented
// by a one in the LSB and zeros in all other
// bits, while -1 is represented by ones in all
// bits (incl. the LSB).
wire [0:dim_addr_width-1] dim_addr_delta;
assign dim_addr_delta[dim_addr_width-1]
= route_down | route_up;
if(dim_addr_width > 1)
assign dim_addr_delta[0:dim_addr_width-2]
= {(dim_addr_width-1){route_down}};
// Because there are no wraparound links in
// line-based topologies, we don't have to
// worry about the cases where an underflow or
// overflow occurs.
assign next_dim_addr
= curr_dim_addr + dim_addr_delta;
end
`CONNECTIVITY_RING:
begin
wire [0:dim_addr_width-1] dim_addr_plus1;
c_incr
#(.width(dim_addr_width),
.min_value(0),
.max_value(num_routers_per_dim-1))
dim_addr_plus1_incr
(.data_in(curr_dim_addr),
.data_out(dim_addr_plus1));
wire [0:dim_addr_width-1] dim_addr_minus1;
c_decr
#(.width(dim_addr_width),
.min_value(0),
.max_value(num_routers_per_dim-1))
dim_addr_minus1_decr
(.data_in(curr_dim_addr),
.data_out(dim_addr_minus1));
assign next_dim_addr
= route_down ? dim_addr_minus1 :
route_up ? dim_addr_plus1 :
curr_dim_addr;
end
endcase
end
`CONNECTIVITY_FULL:
begin
wire route_dim;
assign route_dim
= (route_port >= dim*num_neighbors_per_dim) &&
(route_port < (dim+1)*num_neighbors_per_dim);
// In a topology with fully connected dimensions,
// every hop sets the corresponding part of the
// address to the respective part in of the
// destination address.
wire [0:dim_addr_width-1] dest_dim_addr;
assign dest_dim_addr
= dest_addr[dim*dim_addr_width:
(dim+1)*dim_addr_width-1];
assign next_dim_addr
= route_dim ? dest_dim_addr : curr_dim_addr;
// Alternatively, the destination address can be
// computed as follows:
/*
wire [0:port_idx_width-1] port_offset;
assign port_offset
= route_port - dim*num_neighbors_per_dim;
wire [0:dim_addr_width-1] dim_addr_offset;
assign dim_addr_offset
= port_offset[port_idx_width-dim_addr_width:
port_idx_width-1];
wire [0:dim_addr_width-1] dim_addr_thresh;
assign dim_addr_thresh
= num_routers_per_dim - curr_dim_addr;
wire wrap;
assign wrap = (dim_addr_offset >= dim_addr_thresh);
wire [0:dim_addr_width-1] next_dim_addr_nowrap;
assign next_dim_addr_nowrap
= curr_dim_addr + dim_addr_offset;
wire [0:dim_addr_width-1] next_dim_addr_wrap;
assign next_dim_addr_wrap
= dim_addr_offset - dim_addr_thresh;
assign next_dim_addr
= wrap ? next_dim_addr_wrap : next_dim_addr_nowrap;
*/
end
endcase
assign next_router_address[dim*dim_addr_width:
(dim+1)*dim_addr_width-1]
= next_dim_addr;
end
end
endcase
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; double x[1010], y[1010]; bool vis[1010]; int main() { int n, cnt = 0; double x0, y0; scanf( %d%lf%lf , &n, &x0, &y0); for (int i = 0; i < n; i++) { scanf( %lf%lf , &x[i], &y[i]); } for (int i = 0; i < n; i++) { double x1 = x[i], y1 = y[i]; if (vis[i]) continue; else cnt++; vis[i] = 1; for (int j = 0; j < n; j++) { if (vis[j]) continue; if (x1 == x0 && x[j] == x0) vis[j] = 1; else if (y1 == y0 && y[j] == y0) vis[j] = 1; else if (fabs((y[j] - y0) / (y1 - y0) - (x[j] - x0) / (x1 - x0)) < 1e-9) vis[j] = 1; } } printf( %d n , cnt); return 0; } |
#include <bits/stdc++.h> using namespace std; void main0(); int main() { clock_t start, end; ios::sync_with_stdio(false); cin.tie(0); main0(); return 0; } const int dx[8] = {0, 1, -1, 0, 1, 1, -1, -1}; const int dy[8] = {1, 0, 0, -1, 1, -1, -1, 1}; const int N = 5e5 + 5; const int M = 1e5; const int INF = 0x3f3f3f3f; const long long INFF = 0x3f3f3f3f3f3f3f3f; const int mod = 998244353; const int G = 3; const int Gi = 332748118; const double eps = 1e-6; mt19937 rnd( (unsigned int)chrono::steady_clock::now().time_since_epoch().count()); template <typename T> bool chkmin(T &x, T y) { return y < x ? x = y, 1 : 0; } template <typename T> bool chkmax(T &x, T y) { return y > x ? x = y, 1 : 0; } long long qpow(long long n, long long m) { long long ret = 1; while (m) { if (m & 1) ret = ret * n % mod; n = n * n % mod; m >>= 1; } return ret; } long long getinv(long long a) { return qpow(a, mod - 2); } int n; vector<int> e[N]; long long fac[N]; void init() { fac[0] = 1; for (int i = 1; i <= N - 1; ++i) { fac[i] = fac[i - 1] * i % mod; } } int r[N], lim; void ntt(vector<long long> &A, int type) { for (int i = 0; i <= lim - 1; ++i) { if (i < r[i]) swap(A[i], A[r[i]]); } for (int mid = 1; mid <= lim - 1; mid <<= 1) { long long Wn = qpow(type == 1 ? G : Gi, (mod - 1) / (mid << 1)); for (int j = 0; j <= lim - 1; j += (mid << 1)) { long long w = 1; for (int k = 0; k <= mid - 1; ++k, w = (w * Wn) % mod) { int x = A[j + k]; int y = w * A[j + mid + k] % mod; A[j + k] = (x + y) % mod; A[j + mid + k] = (x - y + mod) % mod; } } } if (type == -1) { long long tmp = getinv(lim); for (int i = 0; i <= lim - 1; ++i) { A[i] = A[i] * tmp % mod; } } } vector<long long> operator*(vector<long long> A, vector<long long> B) { int len = A.size() + B.size() - 1; lim = 1; while (lim <= len) lim <<= 1; for (int i = 0; i <= lim - 1; ++i) { r[i] = (r[i >> 1] >> 1) | ((i & 1) * (lim >> 1)); } A.resize(lim); B.resize(lim); ntt(A, 1); ntt(B, 1); for (int i = 0; i <= lim - 1; ++i) { A[i] = A[i] * B[i] % mod; } ntt(A, -1); A.resize(len); return A; } vector<long long> solve(int l, int r) { if (l == r) { vector<long long> tmp({1, (int)e[l].size() - (l != 1)}); return tmp; } int mid = (l + r) / 2; return solve(l, mid) * solve(mid + 1, r); } void main0() { init(); cin >> n; for (int i = 1; i <= n - 1; ++i) { int u, v; cin >> u >> v; e[u].push_back(v); e[v].push_back(u); } vector<long long> v = solve(1, n); long long ans = 0; for (int i = 0; i <= n - 1; ++i) { ans += (i & 1 ? -1 : 1) * v[i] * fac[n - i] % mod; ans %= mod; } ans += mod; ans %= mod; cout << ans << endl; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUF_M_V
`define SKY130_FD_SC_LP__BUF_M_V
/**
* buf: Buffer.
*
* Verilog wrapper for buf with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__buf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__buf_m (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__buf_m (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__buf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUF_M_V
|
#include <bits/stdc++.h> using namespace std; const int limN = 2e5 + 5; char s[limN]; char arr[2000]; int bu[400]; int main() { int t; scanf( %d , &t); for (int i = 0; i < t; i++) { scanf( %s , s); for (int j = 0; j < 2000; j++) arr[j] = . ; for (int j = 0; j < 400; j++) bu[j] = 0; int n = strlen(s); int ini = 500; int fin = 500; bool f = true; arr[ini] = s[0]; bu[s[0]]++; int pos = ini; for (int j = 1; j < n; j++) { if (j == 1) { fin++; arr[fin] = s[j]; bu[s[j]]++; pos = fin; continue; } if (arr[pos - 1] == s[j]) { pos--; continue; } if (arr[pos + 1] == s[j]) { pos++; continue; } if (bu[s[j]] > 0) { f = false; break; } else { if (pos == ini) { ini--; arr[ini] = s[j]; bu[s[j]]++; pos--; } else if (pos == fin) { fin++; arr[fin] = s[j]; bu[s[j]]++; pos++; } else { f = false; break; } } } if (!f) { printf( NO n ); } else { printf( YES n ); for (int j = ini; j <= fin; j++) { printf( %c , arr[j]); } for (int j = a ; j <= z ; j++) { if (bu[j] == 0) { printf( %c , j); } } printf( n ); } } return 0; } |
#include <bits/stdc++.h> using std::string; using std::vector; namespace Template { struct IN { template <class T> void fr(T& a) { T s = 0; int w = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) w = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) s = s * 10 + ch - 0 , ch = getchar(); a = w * s; } template <class T> T fr() { T a; fr(a); return a; } IN& operator>>(long long& x) { return fr(x), *this; } IN& operator>>(signed& x) { return fr(x), *this; } IN& operator>>(unsigned& x) { return fr(x), *this; } IN& operator>>(char& c) { while (isspace(c = getchar())) ; return *this; } IN& operator>>(string& str) { char ch; while (isspace(ch = getchar())) ; str = ch; while (!isspace(ch = getchar())) str += ch; return *this; } } cin; struct OUT { char D[1 << 27], *A = D - 1; ~OUT() { fwrite(D, 1, A - D + 1, stdout); } template <class T> void fw(T x) { static char C[20]; static int f; x < 0 ? * ++A = - , x = -x : 0; while (C[++f] = 48 + x % 10, x /= 10) ; while (*++A = C[f], --f) ; } OUT& operator<<(char c) { return *++A = c, *this; } OUT& operator<<(string str) { int len = str.length(); for (int i = 0; i < len; i++) *++A = str[i]; return *this; } OUT& operator<<(long long x) { return fw(x), *this; } OUT& operator<<(signed x) { return fw(x), *this; } OUT& operator<<(unsigned x) { return fw(x), *this; } } cout; char endl = n ; int DEBUG = 0; template <class T> T sqr(T a) { return a * a; } template <class T> T abs(T a) { return a < 0 ? -a : a; } template <class T> T cmin(T a, T b) { return a < b ? a : b; } template <class T> T cmax(T a, T b) { return a > b ? a : b; } template <class T> void cswp(T& a, T& b) { T t = a; a = b; b = t; } } // namespace Template using namespace Template; const int N = 1e5; int n, blo, tot = 0, fa[N + 10], len[N + 10], arr[N + 10]; vector<int> E[N + 10]; void adde(int u, int v) { E[u].push_back(v); } void dfs(int u, int f) { fa[u] = f, arr[++tot] = u; for (int v : E[u]) if (v != f) dfs(v, u); } int calc(int k) { int ret = 0; for (int i = 1; i <= n; i++) len[i] = 1; for (int i = n; i > 1; i--) { int u = arr[i], f = fa[u]; if (len[f] != -1 && len[u] != -1) { if (len[f] + len[u] >= k) ret++, len[f] = -1; else len[f] = cmax(len[f], len[u] + 1); } } return ret; } int main() { cin >> n; blo = sqrt(n * log2(n)); for (int i = 1; i < n; ++i) { int u, v; cin >> u >> v; adde(u, v), adde(v, u); } dfs(1, 0), cout << n << endl; for (int i = 2; i <= blo; i++) cout << calc(i) << endl; for (int i = blo + 1; i <= n;) { int f = calc(i), l = i, r = n, pos = 0; while (l <= r) { int mid = (l + r) >> 1; if (calc(mid) == f) l = mid + 1, pos = mid; else r = mid - 1; } for (; i <= pos; i++) cout << f << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> T abs(T x) { return x > 0 ? x : -x; } int m; int n; map<int, int> id; int rev[100500]; int a[2]; int w[100500], ans[100500]; set<int> s; set<int> ss; void go(int x) { w[x] = 1; x = rev[x]; s.insert(x); for (int i = 0; i < (2); i++) { int tmp = a[i] - x; if (ss.find(tmp) != s.end()) { int p = id[tmp]; if (!w[p]) go(p); } } } int check(set<int> s) { for (int i = 0; i < (2); i++) { int g = 1; for (set<int>::const_iterator it = s.begin(); it != s.end(); it++) { int tmp = a[i] - *it; if (s.find(tmp) == s.end()) { g = 0; break; } } if (g) { for (set<int>::const_iterator it = s.begin(); it != s.end(); it++) { ans[id[*it]] = i; } return 1; } } return 0; } int main() { cin >> n >> a[0] >> a[1]; for (int i = 0; i < (n); i++) { int x; cin >> x; id[x] = i; rev[i] = x; ss.insert(x); } for (int i = 0; i < (n); i++) if (!w[i]) { s.clear(); go(i); if (!check(s)) { cout << NO << endl; return 0; } } cout << YES << endl; for (int i = 0; i < (n); i++) cout << ans[i] << ; return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2014 by Wilson Snyder.
// bug823
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [6:0] in = crc[6:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [3:0] mask; // From test of Test.v
wire [3:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[3:0]),
.mask (mask[3:0]),
// Inputs
.clk (clk),
.in (in[6:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {60'h0, out & mask};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x out=%b mask=%b\n",$time, cyc, crc, out, mask);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= '0;
end
else if (cyc<10) begin
sum <= '0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h4e9d3a74e9d3f656
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out, mask,
// Inputs
clk, in
);
input clk;
input [6:0] in; // Note much wider than any index
output reg [3:0] out;
output reg [3:0] mask;
localparam [15:5] p = 11'h1ac;
always @(posedge clk) begin
// verilator lint_off WIDTH
out <= p[15 + in -: 5];
// verilator lint_on WIDTH
mask[3] <= ((15 + in - 5) < 12);
mask[2] <= ((15 + in - 5) < 13);
mask[1] <= ((15 + in - 5) < 14);
mask[0] <= ((15 + in - 5) < 15);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; char s[100005]; int main() { int n; scanf( %d , &n); scanf( %s , s); s[n] = # ; for (int i = 0; i < n; i++) { if (s[i] == a || s[i] == e || s[i] == i || s[i] == o || s[i] == u || s[i] == y ) { if (s[i] == e || s[i] == o ) { int same = 1; if (i != n - 1) { if (s[i + 1] == s[i]) same++; } if (same == 2) { if (i != n - 2) { if (s[i + 2] == s[i]) { printf( %c , s[i]); for (int j = i + 2; j <= n; j++) { if (s[j] != s[i]) { i = j - 1; break; } } } else { printf( %c%c , s[i], s[i]); i++; } } else { printf( %c%c , s[i], s[i]); i++; } } else printf( %c , s[i]); } else { printf( %c , s[i]); for (int j = i + 1; j <= n; j++) { if (s[i] != s[j]) { i = j - 1; break; } } } } else printf( %c , s[i]); } } |
/*
* Decoder for x86 memory access registers
* Copyright (C) 2010 Zeus Gomez Marmolejo <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module zet_memory_regs (
input [2:0] rm,
input [1:0] mod,
input [2:0] sovr_pr,
output reg [3:0] base,
output reg [3:0] index,
output [1:0] seg
);
// Register declaration
reg [1:0] s;
// Continuous assignments
assign seg = sovr_pr[2] ? sovr_pr[1:0] : s;
// Behaviour
always @(rm or mod)
case (rm)
3'b000: begin base <= 4'b0011; index <= 4'b0110; s <= 2'b11; end
3'b001: begin base <= 4'b0011; index <= 4'b0111; s <= 2'b11; end
3'b010: begin base <= 4'b0101; index <= 4'b0110; s <= 2'b10; end
3'b011: begin base <= 4'b0101; index <= 4'b0111; s <= 2'b10; end
3'b100: begin base <= 4'b1100; index <= 4'b0110; s <= 2'b11; end
3'b101: begin base <= 4'b1100; index <= 4'b0111; s <= 2'b11; end
3'b110: begin base <= mod ? 4'b0101 : 4'b1100; index <= 4'b1100;
s <= mod ? 2'b10 : 2'b11; end
3'b111: begin base <= 4'b0011; index <= 4'b1100; s <= 2'b11; end
endcase
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_arb_wr.v
*
* Date : 2012-11
*
* Description : Module that arbitrates between 2 write requests from 2 ports.
*
*****************************************************************************/
module processing_system7_bfm_v2_0_arb_wr(
rstn,
sw_clk,
qos1,
qos2,
prt_dv1,
prt_dv2,
prt_data1,
prt_data2,
prt_addr1,
prt_addr2,
prt_bytes1,
prt_bytes2,
prt_ack1,
prt_ack2,
prt_qos,
prt_req,
prt_data,
prt_addr,
prt_bytes,
prt_ack
);
`include "processing_system7_bfm_v2_0_local_params.v"
input rstn, sw_clk;
input [axi_qos_width-1:0] qos1,qos2;
input [max_burst_bits-1:0] prt_data1,prt_data2;
input [addr_width-1:0] prt_addr1,prt_addr2;
input [max_burst_bytes_width:0] prt_bytes1,prt_bytes2;
input prt_dv1, prt_dv2, prt_ack;
output reg prt_ack1,prt_ack2,prt_req;
output reg [max_burst_bits-1:0] prt_data;
output reg [addr_width-1:0] prt_addr;
output reg [max_burst_bytes_width:0] prt_bytes;
output reg [axi_qos_width-1:0] prt_qos;
parameter wait_req = 2'b00, serv_req1 = 2'b01, serv_req2 = 2'b10,wait_ack_low = 2'b11;
reg [1:0] state,temp_state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
state = wait_req;
prt_req = 1'b0;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_qos = 0;
end else begin
case(state)
wait_req:begin
state = wait_req;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_req = 1'b0;
if(prt_dv1 && !prt_dv2) begin
state = serv_req1;
prt_req = 1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
prt_qos = qos1;
end else if(!prt_dv1 && prt_dv2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_dv1 && prt_dv2) begin
if(qos1 > qos2) begin
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end else if(qos1 < qos2) begin
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
state = serv_req2;
end else begin
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end
end
end
serv_req1:begin
state = serv_req1;
prt_ack2 = 1'b0;
if(prt_ack) begin
prt_ack1 = 1'b1;
prt_req = 0;
if(prt_dv2) begin
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
state = serv_req2;
end else begin
// state = wait_req;
state = wait_ack_low;
end
end
end
serv_req2:begin
state = serv_req2;
prt_ack1 = 1'b0;
if(prt_ack) begin
prt_ack2 = 1'b1;
prt_req = 0;
if(prt_dv1) begin
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end else begin
state = wait_ack_low;
// state = wait_req;
end
end
end
wait_ack_low:begin
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
state = wait_ack_low;
if(!prt_ack)
state = wait_req;
end
endcase
end /// if else
end /// always
endmodule
|
/*
Text Mode Memory
Screen Memory is 16kB, and is organized into 128-bit cells.
Also has a 2kB fixed font.
*/
module ModTxtMemW(clock, reset,
pixCellIx, cellData,
fontGlyph, fontData,
busAddr, busData, busOE, busWR, busOK);
/* verilator lint_off UNUSED */
input clock;
input reset;
input[13:0] pixCellIx;
output[127:0] cellData;
input[15:0] fontGlyph;
output[63:0] fontData;
input[31:0] busAddr;
inout[31:0] busData;
input busOE;
input busWR;
output busOK;
reg tBusOK; //Read OK State
reg[31:0] tBusData; //Output Data
wire tBusCSel; //Bus Chip-Select (Addr Matches)
assign busOK = (busOE && tBusCSel) ? tBusOK : 1'bZ;
assign busData = (busOE && tBusCSel) ? tBusData : 32'hZZZZ_ZZZZ;
assign tBusCSel = (busAddr[31:16]==16'h0080);
reg[13:0] tPixCellIx; //base cell index
reg[13:0] nxtPixCellIx; //base cell index
(* ram_style="block" *) reg[31:0] scrCell1A[0:1023];
(* ram_style="block" *) reg[31:0] scrCell1B[0:1023];
(* ram_style="block" *) reg[31:0] scrCell1C[0:1023];
(* ram_style="block" *) reg[31:0] scrCell1D[0:1023];
reg[63:0] fontMem[255:0];
reg[63:0] fontGfx1Mem[127:0];
reg[63:0] fontGfx2Mem[127:0];
reg[31:0] scrRegCtrl[7:0]; //Control Registers
reg[127:0] tCell1;
reg[127:0] tNextCell1;
reg[15:0] tFontGlyph;
reg[63:0] tFontData1;
reg[63:0] tFontData2;
reg[63:0] tFontDataAsc1;
reg[63:0] tFontDataGfx1;
reg[63:0] tFontDataGfx2;
assign cellData = tCell1;
assign fontData = tFontData1;
initial begin
$readmemh("fontmem.txt", fontMem);
$readmemh("gfxfont0.txt", fontGfx1Mem);
$readmemh("gfxfont1.txt", fontGfx2Mem);
$readmemh("scrmem_1a.txt", scrCell1A);
$readmemh("scrmem_1b.txt", scrCell1B);
$readmemh("scrmem_1c.txt", scrCell1C);
$readmemh("scrmem_1d.txt", scrCell1D);
end
always @ (clock)
begin
nxtPixCellIx = pixCellIx;
tBusOK = 0;
tBusData = 0;
if(busOE && tBusCSel)
begin
nxtPixCellIx = busAddr[15:2];
if(busAddr[15:8]==255)
begin
tBusOK=1;
case(busAddr[6:2])
0: tBusData = scrRegCtrl[0];
1: tBusData = scrRegCtrl[1];
2: tBusData = scrRegCtrl[2];
3: tBusData = scrRegCtrl[3];
8: tBusData = {18'h0, pixCellIx};
endcase
end
else
begin
// tBusOK = tPixCellIx == busAddr[15:2];
// tBusData = tCell1;
tBusOK = tPixCellIx[11:0] == busAddr[15:4];
case(busAddr[3:2])
2'b00: tBusData = tCell1[ 31: 0];
2'b01: tBusData = tCell1[ 63:32];
2'b10: tBusData = tCell1[ 95:64];
2'b11: tBusData = tCell1[127:96];
endcase
end
end
tFontDataAsc1 = fontMem[tFontGlyph[7:0]];
tFontDataGfx1 = fontGfx1Mem[tFontGlyph[6:0]];
tFontDataGfx2 = fontGfx2Mem[tFontGlyph[6:0]];
case(tFontGlyph[9:7])
3'b000: tFontData2 = tFontDataAsc1;
3'b001: tFontData2 = tFontDataAsc1;
3'b010: tFontData2 = tFontDataGfx2;
3'b011: tFontData2 = tFontDataGfx1;
// 3'b100: tFontData2 = tFontDataAsc1;
// 3'b101: tFontData2 = tFontDataGfx2;
default: tFontData2 = tFontDataAsc1;
endcase
end
always @ (posedge clock)
begin
// tCell1 <= tNextCell1;
// tPixCellIx <= pixCellIx;
tPixCellIx <= nxtPixCellIx;
tCell1[ 31: 0] <= scrCell1A[tPixCellIx[9:0]];
tCell1[ 63:32] <= scrCell1B[tPixCellIx[9:0]];
tCell1[ 95:64] <= scrCell1C[tPixCellIx[9:0]];
tCell1[127:96] <= scrCell1D[tPixCellIx[9:0]];
tFontGlyph <= fontGlyph;
tFontData1 <= tFontData2;
if(tBusCSel && busOE)
tPixCellIx <= busAddr[15:2];
else
tPixCellIx <= pixCellIx;
if(tBusCSel && busWR && !busOE)
begin
if(busAddr[15:8]==255)
begin
scrRegCtrl[busAddr[4:2]] <= busData;
end
else
begin
// scrCell1[busAddr[11:2]] <= busData;
case(busAddr[3:2])
2'b00: scrCell1A[busAddr[13:4]] <= busData;
2'b01: scrCell1B[busAddr[13:4]] <= busData;
2'b10: scrCell1C[busAddr[13:4]] <= busData;
2'b11: scrCell1D[busAddr[13:4]] <= busData;
endcase
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2005 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
wire r1_en /*verilator public*/ = crc[12];
wire [1:0] r1_ad /*verilator public*/ = crc[9:8];
wire r2_en /*verilator public*/ = 1'b1;
wire [1:0] r2_ad /*verilator public*/ = crc[11:10];
wire w1_en /*verilator public*/ = crc[5];
wire [1:0] w1_a /*verilator public*/ = crc[1:0];
wire [63:0] w1_d /*verilator public*/ = {2{crc[63:32]}};
wire w2_en /*verilator public*/ = crc[4];
wire [1:0] w2_a /*verilator public*/ = crc[3:2];
wire [63:0] w2_d /*verilator public*/ = {2{~crc[63:32]}};
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [63:0] r1_d_d2r; // From file of file.v
wire [63:0] r2_d_d2r; // From file of file.v
// End of automatics
file file (/*AUTOINST*/
// Outputs
.r1_d_d2r (r1_d_d2r[63:0]),
.r2_d_d2r (r2_d_d2r[63:0]),
// Inputs
.clk (clk),
.r1_en (r1_en),
.r1_ad (r1_ad[1:0]),
.r2_en (r2_en),
.r2_ad (r2_ad[1:0]),
.w1_en (w1_en),
.w1_a (w1_a[1:0]),
.w1_d (w1_d[63:0]),
.w2_en (w2_en),
.w2_a (w2_a[1:0]),
.w2_d (w2_d[63:0]));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d EN=%b%b%b%b R0=%x R1=%x\n", $time, cyc, r1_en,r2_en,w1_en,w2_en, r1_d_d2r, r2_d_d2r);
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= {r1_d_d2r ^ r2_d_d2r} ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
// We've manually verified all X's are out of the design by this point
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$write("[%0t] cyc==%0d crc=%x %x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== 64'h5e9ea8c33a97f81e) $stop;
$finish;
end
end
endmodule
module file (/*AUTOARG*/
// Outputs
r1_d_d2r, r2_d_d2r,
// Inputs
clk, r1_en, r1_ad, r2_en, r2_ad, w1_en, w1_a, w1_d, w2_en, w2_a, w2_d
);
input clk;
input r1_en;
input [1:0] r1_ad;
output [63:0] r1_d_d2r;
input r2_en;
input [1:0] r2_ad;
output [63:0] r2_d_d2r;
input w1_en;
input [1:0] w1_a;
input [63:0] w1_d;
input w2_en;
input [1:0] w2_a;
input [63:0] w2_d;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
// End of automatics
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [63:0] r1_d_d2r;
reg [63:0] r2_d_d2r;
// End of automatics
// Writes
wire [3:0] m_w1_onehotwe = ({4{w1_en}} & (4'b1 << w1_a));
wire [3:0] m_w2_onehotwe = ({4{w2_en}} & (4'b1 << w2_a));
wire [63:0] rg0_wrdat = m_w1_onehotwe[0] ? w1_d : w2_d;
wire [63:0] rg1_wrdat = m_w1_onehotwe[1] ? w1_d : w2_d;
wire [63:0] rg2_wrdat = m_w1_onehotwe[2] ? w1_d : w2_d;
wire [63:0] rg3_wrdat = m_w1_onehotwe[3] ? w1_d : w2_d;
wire [3:0] m_w_onehotwe = m_w1_onehotwe | m_w2_onehotwe;
// Storage
reg [63:0] m_rg0_r;
reg [63:0] m_rg1_r;
reg [63:0] m_rg2_r;
reg [63:0] m_rg3_r;
always @ (posedge clk) begin
if (m_w_onehotwe[0]) m_rg0_r <= rg0_wrdat;
if (m_w_onehotwe[1]) m_rg1_r <= rg1_wrdat;
if (m_w_onehotwe[2]) m_rg2_r <= rg2_wrdat;
if (m_w_onehotwe[3]) m_rg3_r <= rg3_wrdat;
end
// Reads
reg [1:0] m_r1_ad_d1r;
reg [1:0] m_r2_ad_d1r;
reg [1:0] m_ren_d1r;
always @ (posedge clk) begin
if (r1_en) m_r1_ad_d1r <= r1_ad;
if (r2_en) m_r2_ad_d1r <= r2_ad;
m_ren_d1r <= {r2_en, r1_en};
end
// Scheme1: shift...
wire [3:0] m_r1_onehot_d1 = (4'b1 << m_r1_ad_d1r);
// Scheme2: bit mask
reg [3:0] m_r2_onehot_d1;
always @* begin
m_r2_onehot_d1 = 4'd0;
m_r2_onehot_d1[m_r2_ad_d1r] = 1'b1;
end
wire [63:0] m_r1_d_d1 = (({64{m_r1_onehot_d1[0]}} & m_rg0_r) |
({64{m_r1_onehot_d1[1]}} & m_rg1_r) |
({64{m_r1_onehot_d1[2]}} & m_rg2_r) |
({64{m_r1_onehot_d1[3]}} & m_rg3_r));
wire [63:0] m_r2_d_d1 = (({64{m_r2_onehot_d1[0]}} & m_rg0_r) |
({64{m_r2_onehot_d1[1]}} & m_rg1_r) |
({64{m_r2_onehot_d1[2]}} & m_rg2_r) |
({64{m_r2_onehot_d1[3]}} & m_rg3_r));
always @ (posedge clk) begin
if (m_ren_d1r[0]) r1_d_d2r <= m_r1_d_d1;
if (m_ren_d1r[1]) r2_d_d2r <= m_r2_d_d1;
end
endmodule
|
#include <bits/stdc++.h> const int MAXN = 100005; int n; char s[MAXN]; int B = 0, R = 0; int main() { while (scanf( %d , &n) != EOF) { scanf( %s , s); int res = 0; B = 0, R = 0; char pre; for (int i = 0; i < n; i++) { if (i == 0) { pre = s[0]; continue; } if (s[i] != pre) { pre = s[i]; continue; } if (s[i] == r ) { if (R == 0) { res++; pre = b ; B++; } else { pre = b ; R--; } } else { if (B == 0) { res++; pre = r ; R++; } else { pre = r ; B--; } } } int ans = res; res = 0; B = 0, R = 0; for (int i = 0; i < n; i++) { if (i == 0) { if (s[0] == b ) { pre = r ; R++; res++; } else { pre = b ; B++; res++; } continue; } if (s[i] != pre) { pre = s[i]; continue; } if (s[i] == r ) { if (R == 0) { res++; pre = b ; B++; } else { pre = b ; R--; } } else { if (B == 0) { res++; pre = r ; R++; } else { pre = r ; B--; } } } printf( %d n , res < ans ? res : ans); } } |
#include <bits/stdc++.h> using namespace std; const long long mod = 998244353; long long po[1000006]; long long sr[1000006]; long long a[1000006]; int main() { ios_base::sync_with_stdio(false); cin.tie(0); po[0] = 1; sr[0] = 1; for (int i = 1; i <= 1000002; i++) { po[i] = po[i - 1] * 2; po[i] %= mod; } sr[1] = 3; for (int i = 2; i <= 1000002; i++) { sr[i] = ((i + 2) * po[i - 1]) % mod; } long long n; cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; int pos = 0; long long ret = 0; for (int i = n - 1; i >= 0; i--) { long long co = sr[pos++]; long long temp = (co * a[i]) % mod; ret += temp; ret %= mod; } cout << ret << endl; } |
#include <bits/stdc++.h> #pragma GCC optimize(2) #pragma GCC optimize(3) #pragma GCC optimize( Ofast ) #pragma GCC optimize( inline ) #pragma GCC optimize( -fgcse ) #pragma GCC optimize( -fgcse-lm ) #pragma GCC optimize( -fipa-sra ) #pragma GCC optimize( -ftree-pre ) #pragma GCC optimize( -ftree-vrp ) #pragma GCC optimize( -fpeephole2 ) #pragma GCC optimize( -ffast-math ) #pragma GCC optimize( -fsched-spec ) #pragma GCC optimize( unroll-loops ) #pragma GCC optimize( -falign-jumps ) #pragma GCC optimize( -falign-loops ) #pragma GCC optimize( -falign-labels ) #pragma GCC optimize( -fdevirtualize ) #pragma GCC optimize( -fcaller-saves ) #pragma GCC optimize( -fcrossjumping ) #pragma GCC optimize( -fthread-jumps ) #pragma GCC optimize( -funroll-loops ) #pragma GCC optimize( -fwhole-program ) #pragma GCC optimize( -freorder-blocks ) #pragma GCC optimize( -fschedule-insns ) #pragma GCC optimize( inline-functions ) #pragma GCC optimize( -ftree-tail-merge ) #pragma GCC optimize( -fschedule-insns2 ) #pragma GCC optimize( -fstrict-aliasing ) #pragma GCC optimize( -fstrict-overflow ) #pragma GCC optimize( -falign-functions ) #pragma GCC optimize( -fcse-skip-blocks ) #pragma GCC optimize( -fcse-follow-jumps ) #pragma GCC optimize( -fsched-interblock ) #pragma GCC optimize( -fpartial-inlining ) #pragma GCC optimize( no-stack-protector ) #pragma GCC optimize( -freorder-functions ) #pragma GCC optimize( -findirect-inlining ) #pragma GCC optimize( -fhoist-adjacent-loads ) #pragma GCC optimize( -frerun-cse-after-loop ) #pragma GCC optimize( inline-small-functions ) #pragma GCC optimize( -finline-small-functions ) #pragma GCC optimize( -ftree-switch-conversion ) #pragma GCC optimize( -foptimize-sibling-calls ) #pragma GCC optimize( -fexpensive-optimizations ) #pragma GCC optimize( -funsafe-loop-optimizations ) #pragma GCC optimize( inline-functions-called-once ) #pragma GCC optimize( -fdelete-null-pointer-checks ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4.1,sse4.2,avx,avx2,popcnt,tune=native ) using namespace std; struct node { int next, to; } w[2000010]; int n, m, cnt = 1, ans[1000005], h[1000005], top, ln, op, c[1000005], dfn[1000005], timer, bj[1000005], v[1000005], id[2000005]; const int MAX_SIZE = 1 << 21; char *l, *r, buf[MAX_SIZE]; inline int gc() { if (l == r) if (l == (r = (l = buf) + fread(buf, 1, MAX_SIZE, stdin))) return -1; return *l++; } inline void read(int &x) { register char c = gc(); for (; c < 48 || c > 57; c = gc()) ; for (x = 0; c > 47 && c < 58; c = gc()) x = (x << 3) + (x << 1) + (c ^ 48); } inline void write(int x) { if (x > 9) write(x / 10); putchar(x % 10 + 0 ); } void add(int x, int y, int z) { cnt++; w[cnt].to = y; w[cnt].next = h[x]; id[cnt] = z; h[x] = cnt; } inline void DFS1(int u, int co, int tag) { register int i; c[u] = co; dfn[u] = ++timer; for (i = h[u]; i; i = w[i].next) { if (i == (tag ^ 1)) { continue; } int e = w[i].to; if (c[e] == 0) { DFS1(e, 3 - co, i); } else { if (dfn[u] < dfn[e]) { continue; } if (c[u] == c[e]) { op++; ln = i; bj[u]++; bj[e]--; } else { bj[u]--; bj[e]++; } } } } inline void DFS2(int u, int tag) { register int i; v[u] = 1; for (i = h[u]; i; i = w[i].next) { if (i == (tag ^ 1)) continue; int e = w[i].to; if (v[e] == 0) { DFS2(e, i); bj[u] += bj[e]; } } if (bj[u] == op) { top++; ans[top] = tag; } } int main() { register int i, x, y; read(n); read(m); for (i = 1; i <= m; i++) { read(x); read(y); if (x == y) { op++; add(0, 0, i); ln = cnt; continue; } add(x, y, i); add(y, x, i); } for (i = 1; i <= n; i++) { if (c[i] == 0) { DFS1(i, 1, 0); } } for (i = 1; i <= n; i++) { if (v[i] == 0) { DFS2(i, 0); } } if (op == 0) { write(m); putchar( n ); for (i = 1; i <= m; i++) { write(i); putchar( ); } } else { if (op == 1) { top++; ans[top] = ln; } write(top); putchar( n ); sort(ans + 1, ans + 1 + top); for (i = 1; i <= top; i++) { write(id[ans[i]]); putchar( ); } } } |
#include <bits/stdc++.h> using namespace std; using lint = long long int; constexpr int MOD = 1000000007; int main() { int T; cin >> T; for (int t = (0), t_end_ = (T); t < t_end_; t++) { int r, c, k; cin >> r >> c >> k; vector<string> map(r); for (int i = (0), i_end_ = (r); i < i_end_; i++) { cin >> map[i]; } int rice = 0; for (int i = (0), i_end_ = (r); i < i_end_; i++) { for (int j = (0), j_end_ = (c); j < j_end_; j++) { if (map[i][j] == R ) { rice++; } } } int a = rice / k; int b = rice % k; vector<int> ricelist(k, a); for (int i = (0), i_end_ = (b); i < i_end_; i++) { ricelist[i]++; } vector<vector<char>> ans(r, vector<char>(c)); int nowk = 0; for (int i = (0), i_end_ = (r); i < i_end_; i++) { if (i % 2 == 0) { for (int j = (0), j_end_ = (c); j < j_end_; j++) { if (nowk >= 36) { ans[i][j] = a + (nowk - 36); } else if (nowk >= 10) { ans[i][j] = A + (nowk - 10); } else { ans[i][j] = 0 + nowk; } if (map[i][j] == R ) { ricelist[nowk]--; } if (ricelist[nowk] == 0 && nowk != k - 1) { nowk++; } } } else { for (int j = (c)-1, j_begin_ = (0); j >= j_begin_; j--) { if (nowk >= 36) { ans[i][j] = a + (nowk - 36); } else if (nowk >= 10) { ans[i][j] = A + (nowk - 10); } else { ans[i][j] = 0 + nowk; } if (map[i][j] == R ) { ricelist[nowk]--; } if (ricelist[nowk] == 0 && nowk != k - 1) { nowk++; } } } } for (int i = (0), i_end_ = (r); i < i_end_; i++) { for (int j = (0), j_end_ = (c); j < j_end_; j++) { cout << ans[i][j]; } cout << endl; } } } |
#include <bits/stdc++.h> using namespace std; const double eps = 1e-8; const double pi = acos(-1.0); struct Q { int a, b, c; Q(int a, int b, int c) : a(a), b(b), c(c) {} bool operator<(const Q& o) const { if (a == o.a) return c < o.c; return a < o.a; } }; vector<pair<int, int> > ans; set<Q> q; int in[100000]; int main() { int n, i, a, b; scanf( %d , &n); for (i = 0; i < n; ++i) { scanf( %d%d , &a, &b); in[i] = a; if (a) q.insert(Q(a, b, i)); } while (!q.empty()) { Q u = *(q.begin()); q.erase(q.begin()); int cur = u.c; ans.push_back(make_pair(u.b, u.c)); in[u.b]--; in[u.c]--; u = *q.lower_bound(Q(in[u.b] + 1, 0, u.b)); q.erase(u); u.a--; u.b ^= cur; if (u.a) q.insert(u); } printf( %d n , ans.size()); for (i = 0; i < ans.size(); ++i) printf( %d %d n , ans[i].first, ans[i].second); return 0; } |
#include <bits/stdc++.h> using namespace std; const double h = 1e-6; const int MAX_ = 200005; inline long long int mul(long long int a, long long int b) { return (a * 1ll * b) % 1000000007; } inline long long int sub(long long int a, long long int b) { long long int c = a - b; if (c < 0) c += 1000000007; return c; } inline long long int add(long long int a, long long int b) { long long int c = a + b; if (c > 1000000007) c -= 1000000007; return c; } long long int sqr(long long int x) { return x * x; } long long int ncr[3050][3050]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); for (int i = 0; i < 3050; i++) { for (int j = 0; j <= i; j++) { if (i == 0 || j == 0) ncr[i][j] = 1; else ncr[i][j] = add(ncr[i - 1][j - 1], ncr[i - 1][j]); } } int k; cin >> k; long long int val; long long int ans = 1; int count = 0; for (long long int i = 0; i < k; i++) { cin >> val; ans = mul(ans, ncr[count + val - 1][val - 1]); ans %= 1000000007; count += val; } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int a, c, b, v, d, l, n; cin >> a >> b >> c; v = c / (b * 2); n = c % (b * 2); if (n > 0) { v += 1; } l = n / 2 + n % 2; if (l == 0) { l = b; } if (c % 2 == 0) { cout << v << << l << << R ; } else cout << v << << l << << L ; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, t, a = 0, b = 0; cin >> n; for (int i = 0; i < n; i++) { cin >> t; if (t == 25) a++; else if (t == 50) { b++; a--; if (a < 0 || b < 0) { cout << NO << endl; return 0; } } else if (t == 100) { if (b - 1 < 0) { a -= 3; } else { b--; a--; } if (a < 0) { cout << NO << endl; return 0; } } } cout << YES << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__MUX2_BLACKBOX_V
`define SKY130_FD_SC_HVL__MUX2_BLACKBOX_V
/**
* mux2: 2-input multiplexer.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__mux2 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__MUX2_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2111OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__A2111OI_FUNCTIONAL_PP_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__a2111oi (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , B1, C1, D1, and0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2111OI_FUNCTIONAL_PP_V |
/*
Copyright (c) 2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for axis_wb_master
*/
module test_axis_wb_master_8_32_imp;
// Parameters
parameter IMPLICIT_FRAMING = 1;
parameter COUNT_SIZE = 16;
parameter AXIS_DATA_WIDTH = 8;
parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8);
parameter WB_DATA_WIDTH = 32;
parameter WB_ADDR_WIDTH = 32;
parameter WB_SELECT_WIDTH = (WB_DATA_WIDTH/8);
parameter READ_REQ = 8'hA1;
parameter WRITE_REQ = 8'hA2;
parameter READ_RESP = 8'hA3;
parameter WRITE_RESP = 8'hA4;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [AXIS_DATA_WIDTH-1:0] input_axis_tdata = 0;
reg [AXIS_KEEP_WIDTH-1:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
reg output_axis_tready = 0;
reg [WB_DATA_WIDTH-1:0] wb_dat_i = 0;
reg wb_ack_i = 0;
reg wb_err_i = 0;
// Outputs
wire input_axis_tready;
wire [AXIS_DATA_WIDTH-1:0] output_axis_tdata;
wire [AXIS_KEEP_WIDTH-1:0] output_axis_tkeep;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
wire [WB_ADDR_WIDTH-1:0] wb_adr_o;
wire [WB_DATA_WIDTH-1:0] wb_dat_o;
wire wb_we_o;
wire [WB_SELECT_WIDTH-1:0] wb_sel_o;
wire wb_stb_o;
wire wb_cyc_o;
wire busy;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready,
wb_dat_i,
wb_ack_i,
wb_err_i
);
$to_myhdl(
input_axis_tready,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser,
wb_adr_o,
wb_dat_o,
wb_we_o,
wb_sel_o,
wb_stb_o,
wb_cyc_o,
busy
);
// dump file
$dumpfile("test_axis_wb_master_8_32_imp.lxt");
$dumpvars(0, test_axis_wb_master_8_32_imp);
end
axis_wb_master #(
.IMPLICIT_FRAMING(IMPLICIT_FRAMING),
.COUNT_SIZE(COUNT_SIZE),
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.WB_DATA_WIDTH(WB_DATA_WIDTH),
.WB_ADDR_WIDTH(WB_ADDR_WIDTH),
.WB_SELECT_WIDTH(WB_SELECT_WIDTH),
.READ_REQ(READ_REQ),
.WRITE_REQ(WRITE_REQ),
.READ_RESP(READ_RESP),
.WRITE_RESP(WRITE_RESP)
)
UUT (
.clk(clk),
.rst(rst),
.input_axis_tdata(input_axis_tdata),
.input_axis_tkeep(input_axis_tkeep),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tuser(input_axis_tuser),
.output_axis_tdata(output_axis_tdata),
.output_axis_tkeep(output_axis_tkeep),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser),
.wb_adr_o(wb_adr_o),
.wb_dat_i(wb_dat_i),
.wb_dat_o(wb_dat_o),
.wb_we_o(wb_we_o),
.wb_sel_o(wb_sel_o),
.wb_stb_o(wb_stb_o),
.wb_ack_i(wb_ack_i),
.wb_err_i(wb_err_i),
.wb_cyc_o(wb_cyc_o),
.busy(busy)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; using vl = vector<long long>; using vpl = vector<pair<long long, long long>>; using vs = vector<string>; using pl = pair<long long, long long>; using ll = long long int; using vb = vector<bool>; void printcase(ll x) { cout << Case # << x << : ; } void read(vector<ll> &v, ll &n) { for (ll i = 0; i < n; ++i) cin >> v[i]; } void read(ll a[], ll &n) { for (ll i = 0; i < n; ++i) cin >> a[i]; } void print() { cout << endl; } void write(vector<ll> &v, ll &n) { for (ll i = 0; i < n; ++i) cout << v[i] << ; cout << endl; } void write(vector<ll> &v) { ll n = v.size(); for (ll i = 0; i < n; ++i) cout << v[i] << ; cout << endl; } void write(ll a[], ll &n) { for (ll i = 0; i < n; ++i) cout << a[i] << ; cout << endl; } bool sorted(vl &v) { ll n = v.size(); for (int i = 0; i < n - 1; i++) { if (v[i] > v[i + 1]) return 0; } return 1; } bool solve() { ll n; cin >> n; vl v(n); read(v, n); if (n <= 2) return 1; vl suff(n), suffind(n), preind(n); suff[n - 1] = v[n - 1]; suffind[n - 1] = n - 1; preind[0] = 0; for (int i = 1; i < n; i++) { if (v[i] == v[i - 1]) preind[i] = preind[i - 1]; else preind[i] = i; } for (int i = n - 2; i >= 0; i--) { if (v[i] < suff[i + 1]) suffind[i] = i; else suffind[i] = suffind[i + 1]; suff[i] = min(v[i], suff[i + 1]); } for (int i = 0; i < n - 1; i++) { if (v[i] > v[i + 1]) { swap(v[preind[i]], v[suffind[i + 1]]); if (sorted(v)) return 1; else return 0; } } return 1; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; if (solve()) cout << YES << endl; else cout << NO << endl; return 0; } |
module alu_datapath(clk, alu_data, opcode_value, store_a, store_b, start, alu_done, result, overflow_def);
parameter DATA_WIDTH = 8;
input clk;
input alu_data;
input opcode_value;
input store_a;
input store_b;
input start;
output alu_done;
output result;
output overflow_def;
reg overflow_def;
wire clk;
wire [DATA_WIDTH-1:0] alu_data;
wire [1:0] opcode_value;
wire store_a;
wire store_b;
wire start;
reg alu_done;
reg start_def;
reg [DATA_WIDTH-1:0] result;
parameter ON = 1'b1;
parameter OFF = 1'b0;
parameter ADD = 2'b00;
parameter SUB = 2'b01;
parameter PAR = 2'b10;
parameter COMP = 2'b11;
reg [DATA_WIDTH-1:0] buf_a;
reg [DATA_WIDTH-1:0] buf_b;
wire done;
reg [DATA_WIDTH-1:0] add_a;
reg [DATA_WIDTH-1:0] add_b;
wire [DATA_WIDTH-1:0] add_sum;
reg add_carry_in;
wire add_overflow;
reg [DATA_WIDTH-1:0] sub_a;
reg [DATA_WIDTH-1:0] sub_b;
wire [DATA_WIDTH-1:0] sub_diff;
reg sub_borrow_in;
wire sub_borrow_out;
reg [DATA_WIDTH-1:0] par_a;
reg [DATA_WIDTH-1:0] par_b;
wire [DATA_WIDTH-1:0] par_parity;
reg [DATA_WIDTH-1:0] comp_a;
reg [DATA_WIDTH-1:0] comp_b;
wire [DATA_WIDTH-1:0] comp_comp;
always @(posedge clk or store_a or store_b or start)
begin
if(store_a)
begin
buf_a = alu_data;
end
else if(store_b)
begin
buf_b = alu_data;
end
else if(start)
begin
case(opcode_value)
ADD:
begin
add_a = buf_a;
add_b = buf_b;
add_carry_in = 1'b0;
start_def = 1'b1;
end
SUB:
begin
sub_a = buf_a;
sub_b = buf_b;
sub_borrow_in = 1'b0;
start_def = 1'b1;
end
PAR:
begin
par_a = buf_a;
par_b = buf_b;
start_def = 1'b1;
end
COMP:
begin
comp_a = buf_a;
comp_b = buf_b;
start_def = 1'b1;
end
endcase
end
end
always @(posedge clk or done)
begin
if(done)
begin
case(opcode_value)
ADD:
begin
result = add_sum;
overflow_def = add_overflow;
alu_done = ON;
end
SUB:
begin
result = sub_diff;
overflow_def = sub_borrow_out;
alu_done = ON;
end
PAR:
begin
result = par_parity;
alu_done = ON;
overflow_def = OFF;
end
COMP:
begin
result = comp_a ^~ comp_b;
alu_done = ON;
overflow_def = OFF;
end
endcase
end
else
begin
result = 0;
overflow_def = 0;
alu_done = OFF;
end
end
byte_adder #(DATA_WIDTH) adder_ex(
.byte_a(add_a),
.byte_b(add_b),
.byte_carry_in(add_carry_in),
.byte_sum(add_sum),
.byte_overflow(add_overflow),
.start(start_def),
.done(done)
);
byte_subtractor #(DATA_WIDTH) subtractor_ex(
.byte_a(sub_a),
.byte_b(sub_b),
.byte_borrow_in(sub_borrow_in),
.byte_diff(sub_diff),
.byte_borrow_out(sub_borrow_out),
.start(start_def),
.done(done)
);
byte_parity #(DATA_WIDTH) parity_ex(
.byte_a(par_a),
.byte_b(par_b),
.byte_parity(par_parity),
.start(start_def),
.done(done)
);
byte_comp #(DATA_WIDTH) comp_ex(
.byte_a(comp_a),
.byte_b(comp_b),
.byte_comp(comp_comp),
.start(start_def),
.done(done)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, m, l, r; vector<long long> A[200001]; set<pair<int, int> > se; void add(long long y) { for (auto b : A[y]) se.insert({b, y}); } void del(long long y) { for (auto b : A[y]) se.erase({b, y}); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> n >> m >> l >> r; for (long long i = 1; i <= 200000; ++i) for (long long j = i; j <= 200000; j += i) if (j <= 200000) A[j].push_back(i); long long L = m + 1; long long R = m; for (long long x = 1; x <= n; ++x) { long long L_ = (l + x - 1) / x; long long R_ = min(m, r / x); if (L_ > R_) goto L1; while (L > L_) add(--L); while (R > R_) del(R--); for (long long a : A[x]) { auto it = se.upper_bound({a + 1, 0}); if (it != se.end()) { long long b = it->first; long long y = it->second; if (x * b <= n * a) { cout << x << << y << << x * b / a << << y * a / b; goto L2; } } else goto L1; } L1: cout << -1; L2: cout << n ; } return 0; } |
//IEEE Floating Point to Integer Converter (Single Precision)
//Copyright (C) Jonathan P Dawson 2013
//2013-12-12
module float_to_int(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg [2:0] state;
parameter get_a = 3'd0,
special_cases = 3'd1,
unpack = 3'd2,
convert = 3'd3,
put_z = 3'd4;
reg [31:0] a_m, a, z;
reg [8:0] a_e;
reg a_s;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m[31:8] <= {1'b1, a[22 : 0]};
a_m[7:0] <= 0;
a_e <= a[30 : 23] - 127;
a_s <= a[31];
state <= special_cases;
end
special_cases:
begin
if ($signed(a_e) == -127) begin
z <= 0;
state <= put_z;
end else if ($signed(a_e) > 31) begin
z <= 32'h80000000;
state <= put_z;
end else begin
state <= convert;
end
end
convert:
begin
if ($signed(a_e) < 31 && a_m) begin
a_e <= a_e + 1;
a_m <= a_m >> 1;
end else begin
if (a_m[31]) begin
z <= 32'h80000000;
end else begin
z <= a_s ? -a_m : a_m;
end
state <= put_z;
end
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
|
`timescale 1ns/1ns
module usb_rx_sie
(input c,
input c_48,
input oe,
input vp,
input vm,
output [7:0] d,
output dv);
wire bit_d, bit_dv;
wire eop;
usb_rx_nrzi rx_nrzi_inst
(.c_48(c_48), .vp(vp), .vm(vm), .oe(oe), .d(bit_d), .dv(bit_dv), .eop(eop));
// todo: state machine to parse out the bytes and figure out when to
// expect crc16, etc., based on length of the inbound data stream
localparam ST_IDLE = 4'h0;
localparam ST_SYNC = 4'h1;
localparam ST_DATA = 4'h2;
localparam ST_EOP = 4'h3;
localparam ST_CHECK_CRC = 4'h4;
localparam ST_DRAIN = 4'h5; // drains the RX fifo out to busclk domain
localparam ST_DONE = 4'h6;
localparam ST_ERROR = 4'hf;
localparam SW=4, CW=5;
reg [CW+SW-1:0] ctrl;
wire [SW-1:0] state;
wire [SW-1:0] next_state = ctrl[SW+CW-1:CW];
r #(SW) state_r
(.c(c_48), .rst(oe), .en(1'b1), .d(next_state), .q(state));
wire [3:0] bit_cnt;
wire bit_cnt_rst;
r #(4) bit_cnt_r
(.c(c_48), .en(bit_dv), .rst(bit_cnt_rst), .d(bit_cnt+1'b1), .q(bit_cnt));
wire rx_byte_en = bit_dv;
wire [7:0] rx_byte;
r #(8) rx_byte_r
(.c(c_48), .en(rx_byte_en), .rst(1'b0),
.d({bit_d, rx_byte[7:1]}), .q(rx_byte));
wire [6:0] byte_cnt;
wire byte_cnt_en, byte_cnt_rst;
r #(7) byte_cnt_r
(.c(c_48), .en(byte_cnt_en), .rst(byte_cnt_rst),
.d(byte_cnt + 1'b1), .q(byte_cnt));
always @* begin
case (state)
ST_IDLE:
if (bit_dv) ctrl = { ST_SYNC , 5'b00000 };
else ctrl = { ST_IDLE , 5'b00001 };
ST_SYNC:
if (bit_cnt == 4'd8)
if (rx_byte == 8'h80 ) ctrl = { ST_DATA , 5'b00001 };
else ctrl = { ST_ERROR , 5'b00001 };
else ctrl = { ST_SYNC , 5'b00000 };
ST_DATA:
if (eop) ctrl = { ST_EOP , 5'b00001 };
else if (bit_cnt == 4'd8) ctrl = { ST_DATA , 5'b00011 };
else ctrl = { ST_DATA , 5'b00000 };
ST_EOP:
if (byte_cnt == 7'd0) ctrl = { ST_DONE , 5'b00000 }; // bad
else if (byte_cnt == 7'd1) ctrl = { ST_DRAIN , 5'b00100 }; // no crc
else ctrl = { ST_CHECK_CRC, 5'b00000 };
ST_CHECK_CRC: // TODO: actually check CRC
ctrl = { ST_DRAIN , 5'b00100 };
ST_DRAIN: ctrl = { ST_DONE , 5'b00000 };
ST_DONE: ctrl = { ST_IDLE , 5'b00000 };
ST_ERROR: ctrl = { ST_ERROR , 5'b00000 };
default: ctrl = { ST_IDLE , 5'b00000 };
endcase
end
assign bit_cnt_rst = ctrl[0];
wire fifo_wrreq = ctrl[1];
assign byte_cnt_en = ctrl[1];
assign byte_cnt_rst = state == ST_IDLE;
wire fifo_drain_start_48 = state == ST_DRAIN;
wire fifo_drain_start;
sync fifo_drain_start_sync_r
(.in(fifo_drain_start_48), .clk(c), .out(fifo_drain_start));
wire fifo_draining, fifo_rdempty;
r fifo_draining_r
(.c(c), .en(fifo_drain_start), .rst(fifo_rdempty),
.d(1'b1), .q(fifo_draining));
wire pkt_valid;
r pkt_valid_r
(.c(c_48), .en(ctrl[2]), .rst(state == ST_IDLE), .d(1'b1), .q(pkt_valid));
wire pkt_valid_s;
sync pkt_valid_sync_r(.in(pkt_valid), .clk(c), .out(pkt_valid_s));
wire pkt_valid_s_sticky;
r pkt_valid_s_sticky_r
(.c(c), .rst(fifo_rdempty), .en(pkt_valid_s),
.d(1'b1), .q(pkt_valid_s_sticky));
wire xclk_fifo_aclr;
sync xclk_fifo_aclr_sync_r
(.in(oe), .clk(c), .out(xclk_fifo_aclr));
wire [7:0] d_i;
dcfifo
#(.lpm_width(8), .lpm_widthu(7), .lpm_numwords(128), .lpm_showahead("ON"),
.use_eab("ON"), .intended_device_family("CYCLONE V")) xclk_fifo
(.wrclk(c_48), .data(rx_byte), .wrreq(fifo_wrreq),
.rdclk(c), .rdreq(fifo_draining & ~fifo_rdempty),
.q(d_i), .rdempty(fifo_rdempty),
.aclr(xclk_fifo_aclr)); //1'b0));
wire dv_i = pkt_valid_s_sticky & fifo_draining & ~fifo_rdempty;
// delay the output stream one clock to help timing
d1 dv_d1_r(.c(c), .d(dv_i), .q(dv));
d1 #(8) d_d1_r(.c(c), .d(d_i), .q(d));
endmodule
|
#include <bits/stdc++.h> using namespace std; int sol = (int)1e9 + 7; int op, lim; int ask(int r, int c) { op++; if (op == lim) { cout << ! << sol << endl; exit(0); } cout << ? << r << << c << endl; int x; cin >> x; sol = min(sol, x); return x; } int go = 1; void solve(int r1, int c1, int r2, int c2) { if (r1 > r2 || c1 > c2) { return; } if (r1 == r2 && c1 == c2) { ask(r1, c1); return; } int rm = (r1 + r2) / 2; vector<int> e; for (int j = max(go, c1); j <= c2; j++) { e.push_back(ask(rm, j)); } int mn = e[0]; for (auto &x : e) mn = min(mn, x); for (int j = c1; j <= c2; j++) if (e[j - c1] == mn) { solve(r1, c1, rm - 1, j); go = max(go, j); solve(rm + 1, j, r2, c2); return; } } int main() { int n, m; cin >> n >> m; lim = 4 * (n + m); solve(1, 1, n, m); cout << ! << sol << endl; } |
//
// ICBLBC functions
//
// Copyright (c) 2013-2014 Dominic Spill
//
// This file is part of Unambiguous Encapsulation.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; see the file COPYING. If not, write to
// the Free Software Foundation, Inc., 51 Franklin Street,
// Boston, MA 02110-1301, USA.
//
module hamming_distance (
input wire clock,
input wire [7:0] val_a, val_b,
output reg [3:0] distance
);
wire [7:0] bit_diff;
assign bit_diff = val_a ^ val_b;
always @(posedge clock) begin
// Unless I misunderstood him, Marshall said this should work
distance = bit_diff[0] + bit_diff[1] + bit_diff[2] + bit_diff[3]
+ bit_diff[4] + bit_diff[5] + bit_diff[6] + bit_diff[7];
end
endmodule
// Populate candidates module
module populate_candidates (
input wire clock,
input wire [7:0] code,
input wire [7:0] base_candidate_addr,
output reg [7:0] addr_candidates,
input wire [7:0] read_candidates,
input wire [7:0] candidate_len,
input wire [7:0] base_next_cand_addr,
output reg [7:0] addr_next_cand,
output reg [7:0] data_next_cand,
output wire wren_next_cand,
output reg [7:0] next_cand_len,
input wire [3:0] min_dist,
input wire start,
output wire complete
);
wire [3:0] distance;
reg [7:0] ham_in_a, ham_in_b;
hamming_distance hd (
.clock ( clock),
.val_a ( ham_in_a ),
.val_b ( ham_in_b ),
.distance ( distance )
);
reg done;
assign complete = (done == 1 || state == ST_DONE);
reg write_cand;
assign wren_next_cand = write_cand;
reg [7:0] icand, inext;
reg start_1, start_2;
reg [5:0] state;
parameter [5:0] ST_RST = 6'h00,
ST_IDLE = 6'h01,
ST_DONE = 6'h07;
always @(posedge clock) begin
{start_2, start_1} <= {start_1, start};
case(state)
ST_RST: begin
done <= 0;
state <= ST_IDLE;
end
ST_IDLE: begin
if( start_2 ) begin
ham_in_a <= code;
icand <= 0;
inext <= 0;
state <= 3;
done <= 0;
end
end
// Read next candidate
3: begin
addr_candidates <= base_candidate_addr + icand;
state <= 4;
end
//
4: begin
ham_in_b <= read_candidates;
state <= 5;
end
5: begin
if ( distance >= min_dist ) begin
data_next_cand <= read_candidates;
addr_next_cand <= base_next_cand_addr + inext;
write_cand <= 1;
end
state <= 6;
end
6: begin
// Unsure if I need to wait until here to increment inext
if ( distance >= min_dist ) begin
inext <= inext + 1;
end
write_cand <= 0;
icand <= icand + 1;
if ( icand > candidate_len ) begin
done <= 1;
next_cand_len <= inext;
state <= 7;
end else begin
state <= 3;
end
end
ST_DONE: begin
state <= ST_IDLE;
end
endcase
end
endmodule
module find_iso (
input clock,
input wire start,
output wire complete
);
reg start_1, start_2;
reg [5:0] state;
parameter [5:0] ST_RST = 6'h00,
ST_IDLE = 6'h01;
always @(posedge clock) begin
{start_2, start_1} <= {start_1, start};
case(state)
ST_RST: begin
state <= ST_IDLE;
end
ST_IDLE: begin
if( start_2 ) begin
state <= 3;
end
end
3: begin
state <= 4;
end
4: begin
state <= 5;
end
5: begin
state <= 6;
end
6: begin
state <= ST_IDLE;
end
endcase
end
endmodule
module find_best_iso (
input wire clock,
input wire [7:0] min_hd,
input wire [7:0] min_iso,
input wire start_process,
output reg complete
);
parameter n = 5;
parameter MAX_N = 8;
parameter MAX_CAND = 2**MAX_N;
reg [5:0] state;
parameter [5:0] ST_RST = 6'h00,
ST_IDLE = 6'h01;
reg [7:0] count, icand;
reg [7:0] a_len, min_b_len;
reg start_process_1, start_process_2;
// Storage for sets of codes
wire wren_codes;
wire [7:0] read_codes;
wire [10:0] addr_codes;
wire [7:0] data_codes;
icblbc_ram codes (
.address ( addr_codes ),
.clock ( clock ),
.data ( data_codes ),
.wren ( wren_codes ),
.q ( read_codes )
);
reg fi_en;
find_iso fi (
.clock ( clock ),
.start ( fi_en ),
.complete ( fi_done )
);
always @(posedge clock) begin
{start_process_2, start_process_1} <= {start_process_1, start_process};
case(state)
ST_RST: begin
state <= ST_IDLE;
end
ST_IDLE: begin
if( start_process_2 ) begin
state <= 3;
a_len <= 1<<(n-1);
min_b_len <= 2;
end
end
3: begin
state <= 4;
end
4: begin
state <= 5;
end
5: begin
state <= 10;
end
// Wait for find_iso() to finish
10: begin
fi_en <= 1;
state <= 11;
end
11: begin
if( fi_done ) begin
state <= 12;
end
end
12: begin
state <= 13;
end
20: begin
state <= ST_IDLE;
end
endcase
end
endmodule
|
/*
* Copyright (C) 2011 Kiel Friedt
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
//authors Kiel Friedt, Kevin McIntosh,Cody DeHaan
module HazardDetect(clk, reset, EX_MemRead, EX_Rt, EX_Rs, ID_Rt, ID_Rs, MuxCtl, PCWrite);
input EX_MemRead, clk, reset;
input [4:0] EX_Rt, ID_Rt, ID_Rs, EX_Rs;
output MuxCtl, PCWrite;
reg MuxCtl, PCWrite;
//set wires and registers
always @(clk or EX_Rs or EX_Rt or ID_Rs or ID_Rt )
begin
if(((EX_Rt == ID_Rt) && (EX_Rt != 0)) || ((EX_Rs == ID_Rs) && (EX_Rs != 0)))
begin
assign MuxCtl = 1;
assign PCWrite = 1;
end
else
begin
assign MuxCtl = 0;
assign PCWrite = 0;
end
end
initial begin
assign MuxCtl = 0;
assign PCWrite = 0;
end
endmodule |
Subsets and Splits