text
stringlengths 59
71.4k
|
|---|
#include <bits/stdc++.h> const long long mod = 998244853; long long C[5050][5050], n, m, g[5050], ans; signed main() { scanf( %lld%lld , &n, &m); for (long long i = 0; i <= n + m; i++) { C[i][0] = 1; for (long long j = 1; j <= i; j++) C[i][j] = (C[i - 1][j] + C[i - 1][j - 1]) % mod; } for (long long i = 0; i <= n; i++) if (i <= n - m) g[i] = C[n + m][n]; else g[i] = C[n + m][m + i]; for (long long i = 0; i <= n; i++) (ans += i * ((g[i] - g[i + 1] + mod) % mod) % mod) %= mod; printf( %lld n , ans); } |
#include <bits/stdc++.h> using namespace std; vector<int> a[30005]; int main() { int n, m, p, q, i, j; vector<int> v; cin >> n >> m; for (i = 0; i < m; i++) { scanf( %d%d , &p, &q); a[p].push_back(q); } for (i = 1; i < n; i++) sort(a[i].begin(), a[i].end()); for (i = 1; i <= n; i++) { v.push_back(i); j = i - 2; while (j >= 0) { if (binary_search(a[v[j]].begin(), a[v[j]].end(), i)) { swap(v[j], v[j + 1]); j--; } else break; } } for (i = 0; i < n - 1; i++) if (binary_search(a[v[i]].begin(), a[v[i]].end(), v[i + 1])) { cout << -1 << endl; return 0; } for (i = 0; i < n; i++) cout << v[i] << ; return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, m, k, ans = 0; int main() { cin >> n >> m >> k; if (n - 1 + m - 1 < k) { cout << -1 << endl; return 0; } long long buf = sqrt(n); buf++; for (int i = 0; i <= buf; i++) { long long x = n / (i + 1); if (k - i < 0) continue; long long y = m / (k - i + 1); ans = max(ans, x * y); } for (int i = 1; i <= buf; i++) { long long cut = n / i - 1; if (cut < 0) continue; long long left = k - cut; if (left < 0) left = 0; ans = max(ans, i * (m / (left + 1))); } cout << ans << endl; return 0; } |
/*
* Copyright (c) 2009 Zeus Gomez Marmolejo <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module hex_display (
input [15:0] num,
input en,
output [6:0] hex0,
output [6:0] hex1,
output [6:0] hex2,
output [6:0] hex3
);
// Module instantiations
seg_7 hex_group0 (
.num (num[3:0]),
.en (en),
.seg (hex0)
);
seg_7 hex_group1 (
.num (num[7:4]),
.en (en),
.seg (hex1)
);
seg_7 hex_group2 (
.num (num[11:8]),
.en (en),
.seg (hex2)
);
seg_7 hex_group3 (
.num (num[15:12]),
.en (en),
.seg (hex3)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND3B_BEHAVIORAL_V
`define SKY130_FD_SC_MS__NAND3B_BEHAVIORAL_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__nand3b (
Y ,
A_N,
B ,
C
);
// Module ports
output Y ;
input A_N;
input B ;
input C ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire nand0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y, B, not0_out, C );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND3B_BEHAVIORAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19.02.2016 18:21:15
// Design Name:
// Module Name: toplevelv
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module toplevel
(
GCLK,
DC,
RES,
SCLK,
SDIN,
VBAT,
VDD,
JA1,
JA2,
JA3,
JA4,
JA7,
JA8,
JA9,
JA10,
JB1,
JB2,
JB3,
JB4,
JB7,
JB8,
JB9,
JB10,
SW0,
SW1,
SW2,
SW3,
SW4,
SW5,
SW6,
SW7,
BTNC,
BTND,
BTNL,
BTNR,
BTNU,
LD0,
LD1,
LD2,
LD3,
LD4,
LD5,
LD6,
LD7
);
input wire GCLK;
output wire DC;
output wire RES;
output wire SCLK;
output wire SDIN;
output wire VBAT;
output wire VDD;
output wire JA1;
output wire JA2;
output wire JA3;
output wire JA4;
output wire JA7;
output wire JA8;
output wire JA9;
output wire JA10;
input wire JB1;
input wire JB2;
input wire JB3;
input wire JB4;
input wire JB7;
input wire JB8;
input wire JB9;
input wire JB10;
input wire SW0;
input wire SW1;
input wire SW2;
input wire SW3;
input wire SW4;
input wire SW5;
input wire SW6;
input wire SW7;
input wire BTNC;
input wire BTND;
input wire BTNL;
input wire BTNR;
input wire BTNU;
output wire LD0;
output wire LD1;
output wire LD2;
output wire LD3;
output wire LD4;
output wire LD5;
output wire LD6;
output wire LD7;
sandbox SANDBOX
(
.GCLK(GCLK),
.LD({LD7, LD6, LD5, LD4, LD3, LD2, LD1, LD0}),
.SW({SW7, SW6, SW5, SW4, SW3, SW2, SW1, SW0}),
.JA({JA10, JA9, JA8, JA7, JA4, JA3, JA2, JA1}),
.JB({JB10, JB9, JB8, JB7, JB4, JB3, JB2, JB1}),
.BTNC(BTNC),
.BTND(BTND),
.BTNL(BTNL),
.BTNR(BTNR),
.BTNU(BTNU)
);
endmodule |
#include <bits/stdc++.h> using namespace std; string to_string(string s) { return + s + ; } string to_string(char c) { return + string(1, c) + ; } string to_string(const char *s) { return to_string((string)s); } string to_string(bool b) { return (b ? true : false ); } template <typename A, typename B> string to_string(pair<A, B> p) { return ( + to_string(p.first) + , + to_string(p.second) + ) ; } template <typename A> string to_string(A v) { bool first = true; string res = { ; for (const auto &x : v) { if (!first) res += , ; first = false; res += to_string(x); } res += } ; return res; } void debug_out() { cerr << endl; } template <typename Head, typename... Tail> void debug_out(Head H, Tail... T) { cerr << << to_string(H); debug_out(T...); } const int dx[] = {0, 0, 1, -1}, dy[] = {1, -1, 0, 0}; string to_str(const int &n) { ostringstream stm; stm << n; return stm.str(); } string to_str(const long long &n) { ostringstream stm; stm << n; return stm.str(); } template <class T> string tostring(T x, int len = 0) { stringstream ss; ss << x; string r = ss.str(); if (int((r).size()) < len) r = string(len - int((r).size()), 0 ) + r; return r; } template <class T> void convert(string x, T &r) { stringstream ss(x); ss >> r; } long long powmod(long long a, long long b) { long long res = 1; a %= 1000000007; for (; b; b >>= 1) { if (b & 1) res = res * a % 1000000007; a = a * a % 1000000007; } return res; } long long modinv(long long a) { return powmod(a, 1000000007 - 2); } long long modinv(long long a, long long m) { return powmod(a, m - 2); } long long nCkMp(long long n, long long k) { long long numerator = 1, denominator = 1; for (int i = 0; i < k; i++) numerator = (numerator * (n - i)) % 1000000007; for (int i = 1; i <= k; i++) denominator = (denominator * i) % 1000000007; return (numerator * modinv(denominator)) % 1000000007; } long long gcd(long long a, long long b) { return b == 0 ? a : gcd(b, a % b); } long long lcm(long long a, long long b) { return a * (b / gcd(a, b)); } int TT = 1, tt; clock_t t1; void solve() { t1 = clock(); int n; long long a; long long b; (cin >> (n)); vector<int> x(n); for (auto i = (0); i < (n); i++) (cin >> (x[i])); sort((x).begin(), (x).end()); b = x[n - 1]; a = accumulate((x).begin(), (x).end(), 0ll) - b; (cout << (abs(a - b) + 1) << endl); } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); for (tt = 0; tt < TT; tt++) solve(); return EXIT_SUCCESS; } |
#include <bits/stdc++.h> using namespace std; inline int read() { int s = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) s = s * 10 + ch - 0 , ch = getchar(); return s * f; } const int maxn = 1e5 + 10; int n, tot, head[maxn], d[maxn], a[maxn], ans, sz[maxn]; struct data { int to, next, w; } edge[maxn]; void calc(int x) { sz[x] = 1; for (int i = head[x]; i; i = edge[i].next) { int y = edge[i].to; calc(y); sz[x] += sz[y]; } } void dfs(int x) { if (d[x] > a[x]) { ans += sz[x]; return; } for (int i = head[x]; i; i = edge[i].next) { int y = edge[i].to; d[y] = d[x] + edge[i].w; if (d[y] < 0) d[y] = 0; dfs(y); } } inline void make(int u, int v, int w) { edge[++tot] = (data){v, head[u], w}; head[u] = tot; } int main() { n = read(); for (int i = 1; i <= n; i++) a[i] = read(); for (int i = 2; i <= n; i++) { int x = read(), y = read(); make(x, i, y); } calc(1); dfs(1); cout << ans; return 0; } |
/******************************************************************************
* (C) Copyright 2014 AMIQ Consulting
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* NAME: amiq_eth_ve_top.sv
* PROJECT: amiq_eth
* Description: This file declares the top module from which the UVM flow is run
*******************************************************************************/
`ifndef __AMIQ_ETH_VE_TOP
`define __AMIQ_ETH_VE_TOP
`timescale 10ns/10ns
`include "amiq_eth_ve_pkg.sv"
import uvm_pkg::*;
import amiq_eth_ve_pkg::*;
//top module for starting the UVM flow
module amiq_eth_ve_top;
initial begin
run_test();
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; int gcd(int a, int b) { while (a && b) a > b ? a %= b : b %= a; return a + b; } long long lcm(long long a, long long b) { return (a * b) / gcd(a, b); } long long fast_exp(long long base, long long exp) { long long res = 1; while (exp > 0) { if (exp % 2 == 1) res = ((res % 1000000007) * (base % 1000000007)) % 1000000007; base = ((base % 1000000007) * (base % 1000000007)) % 1000000007; exp /= 2; } return res % 1000000007; } const int INF = INT_MAX; const long long INFL = LLONG_MAX; map<int, int> Z; const int size = 3e5 + 9; int ptr[size]; int main() { std::ios::sync_with_stdio(0); cin.tie(0); int n, q; cin >> n >> q; int unread = 0; vector<pair<int, int> > unr; int cnt = 0, i = 0; while (q--) { cnt++; int t, x; cin >> t >> x; if (t == 1) { unread++; unr.push_back(pair<int, int>(x, cnt)); Z[x]++; } else if (t == 2) { unread -= Z[x]; Z[x] = 0; ptr[x] = cnt; } else { while (i < x) { if (unr[i].second >= ptr[unr[i].first]) { unread--; ptr[unr[i].first] = unr[i].second; Z[unr[i].first]--; } i++; } } cout << unread << n ; } return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC target( avx,avx2,fma ) #pragma GCC optimization( unroll-loops ) using namespace std; const int maxn = 3e5 + 5; const long long mod = 998244353; const double eps = 1e-6L; struct node { int l, r; bool operator<(const node& k) const { if (l == k.l) return r > k.r; return l < k.l; } } a[maxn]; long long fac[maxn], f[maxn], inv[maxn]; void init() { fac[1] = 1; f[1] = 1; inv[1] = 1; for (long long i = 2; i <= maxn; i++) { fac[i] = fac[i - 1] * i % mod; f[i] = (mod - mod / i) * f[mod % i] % mod; inv[i] = inv[i - 1] * f[i] % mod; } } long long C(long long m, long long n) { if (m < n) return 0; if (n == 0 || m == n) return 1; return fac[m] * inv[n] % mod * inv[m - n] % mod; } int b[maxn]; int main() { int T = 1; init(); while (T--) { int n, k, m = 1; scanf( %d %d , &n, &k); for (int i = 0; i < n; i++) { scanf( %d %d , &a[i].l, &a[i].r); b[i] = a[i].r; } sort(a, a + n); sort(b, b + n); int left = a[0].l, right = a[0].r; long long ans = 0; bool flag = true; for (int i = n - 1; i >= 0; i--) { int num = i + 1 - (lower_bound(b, b + n, a[i].l) - b); ans = (ans + C(num - 1, k - 1)) % mod; } printf( %lld n , ans); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; bool zero = false; int *arr = new int[n]; for (int i = 0; i < n; i++) { cin >> arr[i]; } int neg = 0; for (int i = 0; i < n; i++) { if (arr[i] < 0) neg++; if (arr[i] == 0) { zero = true; } } for (int i = 0; k > 0 && i < neg;) { arr[i] = arr[i] * -1; k--; i++; } long long int ans = 0; for (int i = 0; i < n; i++) { ans += arr[i]; } int min = INT_MAX; for (int i = 0; i < n; i++) { if (arr[i] < min) { min = arr[i]; } } if (k % 2 == 0) { cout << ans; } else { cout << ans - 2 * min; } return 0; } |
`ifndef BSG_DEFINES_V
`define BSG_DEFINES_V
`define BSG_MAX(x,y) (((x)>(y)) ? (x) : (y))
`define BSG_MIN(x,y) (((x)<(y)) ? (x) : (y))
`define BSG_SIGN_EXTEND(sig, width) \
({{`BSG_MAX(width-$bits(sig),0){sig[$bits(sig)-1]}}, sig[0+:`BSG_MIN(width, $bits(sig))]})
`define BSG_ZERO_EXTEND(sig, width) \
({{`BSG_MAX(width-$bits(sig),0){1'b0}}, sig[0+:`BSG_MIN(width, $bits(sig))]})
// place this macro at the end of a verilog module file if that module has invalid parameters
// that must be specified by the user. this will prevent that module from becoming a top-level
// module per the discussion here: https://github.com/SymbiFlow/sv-tests/issues/1160 and the
// SystemVerilog Standard
// "Top-level modules are modules that are included in the SystemVerilog
// source text, but do not appear in any module instantiation statement, as
// described in 23.3.2. This applies even if the module instantiation appears
// in a generate block that is not itself instantiated (see 27.3). A design
// shall contain at least one top-level module. A top-level module is
// implicitly instantiated once, and its instance name is the same as the
// module name. Such an instance is called a top-level instance."
//
`define BSG_ABSTRACT_MODULE(fn) \
/*verilator lint_off PINMISSING*/ \
module fn``__abstract(); if (0) fn not_used(); endmodule \
/*verilator lint_on PINMISSING*/
// macro for defining invalid parameter; with the abstract module declaration
// it should be sufficient to omit the "inv" but we include this for tool portability
// if later we find that all tools are compatible, we can remove the use of this from BaseJump STL
`ifdef XCELIUM // Bare default parameters are incompatible as of 20.09.012
`define BSG_INV_PARAM(param) param = "inv"
`else // VIVADO, DC, VERILATOR, GENUS
`define BSG_INV_PARAM(param) param
`endif
// maps 1 --> 1 instead of to 0
`define BSG_SAFE_CLOG2(x) ( ((x)==1) ? 1 : $clog2((x)))
`define BSG_IS_POW2(x) ( (1 << $clog2(x)) == (x))
`define BSG_WIDTH(x) ($clog2(x+1))
`define BSG_SAFE_MINUS(x, y) (((x)<(y))) ? 0 : ((x)-(y))
// calculate ceil(x/y)
`define BSG_CDIV(x,y) (((x)+(y)-1)/(y))
`ifdef SYNTHESIS
`define BSG_UNDEFINED_IN_SIM(val) (val)
`else
`define BSG_UNDEFINED_IN_SIM(val) ('X)
`endif
`ifdef VERILATOR
`define BSG_HIDE_FROM_VERILATOR(val)
`else
`define BSG_HIDE_FROM_VERILATOR(val) val
`endif
`ifdef SYNTHESIS
`define BSG_DISCONNECTED_IN_SIM(val) (val)
`elsif VERILATOR
`define BSG_DISCONNECTED_IN_SIM(val) (val)
`else
`define BSG_DISCONNECTED_IN_SIM(val) ('z)
`endif
// Ufortunately per the Xilinx forums, Xilinx does not define
// any variable that indicates that Vivado Synthesis is running
// so as a result we identify Vivado merely as the exclusion of
// Synopsys Design Compiler (DC). Support beyond DC and Vivado
// will require modification of this macro.
`ifdef SYNTHESIS
`ifdef DC
`define BSG_VIVADO_SYNTH_FAILS
`else
`define BSG_VIVADO_SYNTH_FAILS this_module_is_not_synthesizeable_in_vivado
`endif
`else
`define BSG_VIVADO_SYNTH_FAILS
`endif
`define BSG_STRINGIFY(x) `"x`"
// using C-style shifts instead of a[i] allows the parameter of BSG_GET_BIT to be a parameter subrange
// e.g., parameter[4:1][1], which DC 2016.12 does not allow
`define BSG_GET_BIT(X,NUM) (((X)>>(NUM))&1'b1)
// This version of countones works in synthesis, but only up to 64 bits
// we do a funny thing where we propagate X's in simulation if it is more than 64 bits
// and in synthesis, go ahead and ignore the high bits
`define BSG_COUNTONES_SYNTH(y) (($bits(y) < 65) ? 1'b0 : `BSG_UNDEFINED_IN_SIM(1'b0)) + (`BSG_GET_BIT(y,0) +`BSG_GET_BIT(y,1) +`BSG_GET_BIT(y,2) +`BSG_GET_BIT(y,3) +`BSG_GET_BIT(y,4) +`BSG_GET_BIT(y,5) +`BSG_GET_BIT(y,6)+`BSG_GET_BIT(y,7) +`BSG_GET_BIT(y,8)+`BSG_GET_BIT(y,9) \
+`BSG_GET_BIT(y,10)+`BSG_GET_BIT(y,11)+`BSG_GET_BIT(y,12)+`BSG_GET_BIT(y,13)+`BSG_GET_BIT(y,14)+`BSG_GET_BIT(y,15)+`BSG_GET_BIT(y,16)+`BSG_GET_BIT(y,17)+`BSG_GET_BIT(y,18)+`BSG_GET_BIT(y,19) \
+`BSG_GET_BIT(y,20)+`BSG_GET_BIT(y,21)+`BSG_GET_BIT(y,22)+`BSG_GET_BIT(y,23)+`BSG_GET_BIT(y,24)+`BSG_GET_BIT(y,25)+`BSG_GET_BIT(y,26)+`BSG_GET_BIT(y,27)+`BSG_GET_BIT(y,28)+`BSG_GET_BIT(y,29) \
+`BSG_GET_BIT(y,30)+`BSG_GET_BIT(y,31)+`BSG_GET_BIT(y,32)+`BSG_GET_BIT(y,33)+`BSG_GET_BIT(y,34)+`BSG_GET_BIT(y,35)+`BSG_GET_BIT(y,36)+`BSG_GET_BIT(y,37)+`BSG_GET_BIT(y,38)+`BSG_GET_BIT(y,39) \
+`BSG_GET_BIT(y,40)+`BSG_GET_BIT(y,41)+`BSG_GET_BIT(y,42)+`BSG_GET_BIT(y,43)+`BSG_GET_BIT(y,44)+`BSG_GET_BIT(y,45)+`BSG_GET_BIT(y,46)+`BSG_GET_BIT(y,47)+`BSG_GET_BIT(y,48)+`BSG_GET_BIT(y,49) \
+`BSG_GET_BIT(y,50)+`BSG_GET_BIT(y,51)+`BSG_GET_BIT(y,52)+`BSG_GET_BIT(y,53)+`BSG_GET_BIT(y,54)+`BSG_GET_BIT(y,55)+`BSG_GET_BIT(y,56)+`BSG_GET_BIT(y,57)+`BSG_GET_BIT(y,58)+`BSG_GET_BIT(y,59) \
+`BSG_GET_BIT(y,60)+`BSG_GET_BIT(y,61)+`BSG_GET_BIT(y,62)+`BSG_GET_BIT(y,63))
// nullify rpgroups
`ifndef rpgroup
`define rpgroup(x)
`endif
`endif
|
/* SPDX-License-Identifier: MIT */
/* (c) Copyright 2018 David M. Koltak, all rights reserved. */
//
// RCN bus UART
//
// Registers -
// 0: Status : [rx_empty, rx_full, tx_empty, tx_full]
// 1: Data : 8-bit read/write
//
module rcn_uart
(
input clk,
input clk_50,
input rst,
input [68:0] rcn_in,
output [68:0] rcn_out,
output tx_req,
output rx_req,
output uart_tx,
input uart_rx
);
parameter ADDR_BASE = 0;
parameter SAMPLE_CLK_DIV = 6'd62; // Value for 115200 @ 50 MHz in
wire cs;
wire wr;
wire [3:0] mask;
wire [23:0] addr;
wire [31:0] wdata;
wire [31:0] rdata;
rcn_slave_fast #(.ADDR_BASE(ADDR_BASE), .ADDR_MASK(24'hFFFFFC)) rcn_slave
(
.rst(rst),
.clk(clk),
.rcn_in(rcn_in),
.rcn_out(rcn_out),
.cs(cs),
.wr(wr),
.mask(mask),
.addr(addr),
.wdata(wdata),
.rdata(rdata)
);
wire tx_busy;
wire tx_vld;
wire [7:0] tx_data;
wire rx_vld;
wire [7:0] rx_data;
rcn_uart_framer #(.SAMPLE_CLK_DIV(SAMPLE_CLK_DIV)) rcn_uart_framer
(
.clk_50(clk_50),
.rst(rst),
.tx_busy(tx_busy),
.tx_vld(tx_vld),
.tx_data(tx_data),
.rx_vld(rx_vld),
.rx_data(rx_data),
.rx_frame_error(),
.uart_tx(uart_tx),
.uart_rx(uart_rx)
);
wire tx_full;
wire tx_empty;
assign tx_req = !tx_full;
assign tx_vld = !tx_empty;
rcn_fifo_byte_async tx_fifo
(
.rst_in(rst),
.clk_in(clk),
.clk_out(clk_50),
.din(wdata[15:8]),
.push(cs && wr && mask[1]),
.full(tx_full),
.dout(tx_data),
.pop(!tx_busy),
.empty(tx_empty)
);
wire [7:0] rdata_byte;
wire rx_empty;
wire rx_full;
reg tx_empty_sync;
reg rx_full_sync;
assign rdata = {16'd0, rdata_byte, 4'd0, rx_empty, rx_full_sync,
tx_empty_sync, tx_full};
assign rx_req = !rx_empty;
rcn_fifo_byte_async rx_fifo
(
.rst_in(rst),
.clk_in(clk_50),
.clk_out(clk),
.din(rx_data),
.push(rx_vld),
.full(rx_full),
.dout(rdata_byte),
.pop(cs && !wr && mask[1]),
.empty(rx_empty)
);
always @ (posedge clk)
begin
rx_full_sync <= rx_full;
tx_empty_sync <= tx_empty;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:03:45 12/10/2012
// Design Name:
// Module Name: spim
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module spim(
input clk,
input rst,
input[7:0] din,
input wen,
input wdiv,
output rdy,
output reg SCLK,
output MOSI,
output reg SSbar
);
// SPI Master Mode 0 . http://elm-chan.org/docs/spi_e.html
wire tick;
reg[7:0] clk_div_count;
reg[1:0] state,n_state;
reg shift;
reg[7:0] div,data;
reg nSSr,SCLKr;
reg[3:0] bit_count;
reg bit_count_rst,bit_count_en;
always @(posedge clk or posedge rst) begin
if(rst) clk_div_count <= 0;
else
if(tick) clk_div_count <= 0;
else clk_div_count <= clk_div_count + 1;
end
assign tick = (clk_div_count == div);
assign rdy = (state == 0);
always @(posedge clk or posedge rst) begin
if(rst) begin
data <= 0;
div <= 0;
end
else begin
if(wen & rdy) data <= din;
else if(shift & tick) data <= { data[6:0] , 1'b0 };
if(wdiv) div <= din;
end
end
assign MOSI = data[7];
always @(posedge clk or posedge rst) begin
if(rst) begin
SSbar <= 1;
SCLK <= 0;
end
else begin
if(tick) begin
SSbar <= nSSr;
SCLK <= SCLKr;
end
end
end
always @(posedge clk or posedge rst) begin
if(rst) bit_count <= 0;
else
if(bit_count_rst) bit_count <= 0;
else if(tick & bit_count_en) bit_count <= bit_count + 1;
end
always @(posedge clk or posedge rst) begin
if(rst) state <= 0;
else state <= n_state;
end
always @(*) begin
n_state <= state;
nSSr <= 0;
bit_count_rst <= 0;
SCLKr <= 0;
shift <= 0;
bit_count_en <= 0;
case(state)
0: begin
nSSr <= 1;
if(wen) n_state <= 1;
end
1: begin
bit_count_rst <= 1;
if(tick) n_state <= 2;
end
2: begin
SCLKr <= 1;
if(tick) n_state <= 3;
end
3: begin
shift <= 1;
bit_count_en <= 1;
if(tick)
if(bit_count < 7) n_state <= 2;
else n_state <= 0;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const int N = 1e6 + 7; long long p[N]; int main() { int a, b, c, d; scanf( %d , &a), scanf( %d , &b), scanf( %d , &c), scanf( %d , &d); for (int i = a; i < (int)b + 1; i++) { p[i + b] += 1; p[i + c + 1] -= 1; } for (int i = 1; i < (int)N; i++) p[i] += p[i - 1]; for (int i = 1; i < (int)N; i++) p[i] += p[i - 1]; long long val = 0; for (int i = c; i < (int)d + 1; i++) val += p[N - 1] - p[i]; printf( %lld n , val); } |
// megafunction wizard: %LPM_CLSHIFT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_CLSHIFT
// ============================================================
// File Name: shift16.v
// Megafunction Name(s):
// LPM_CLSHIFT
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.1 Build 243 01/31/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module shift16 (
data,
direction,
distance,
result);
input [31:0] data;
input direction;
input [3:0] distance;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
lpm_clshift LPM_CLSHIFT_component (
.data (data),
.direction (direction),
.distance (distance),
.result (sub_wire0)
// synopsys translate_off
,
.aclr (),
.clken (),
.clock (),
.overflow (),
.underflow ()
// synopsys translate_on
);
defparam
LPM_CLSHIFT_component.lpm_shifttype = "LOGICAL",
LPM_CLSHIFT_component.lpm_type = "LPM_CLSHIFT",
LPM_CLSHIFT_component.lpm_width = 32,
LPM_CLSHIFT_component.lpm_widthdist = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: LPM_SHIFTTYPE NUMERIC "0"
// Retrieval info: PRIVATE: LPM_WIDTH NUMERIC "32"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: lpm_widthdist NUMERIC "4"
// Retrieval info: PRIVATE: lpm_widthdist_style NUMERIC "1"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: PRIVATE: port_direction NUMERIC "2"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_SHIFTTYPE STRING "LOGICAL"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CLSHIFT"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHDIST NUMERIC "4"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: direction 0 0 0 0 INPUT NODEFVAL "direction"
// Retrieval info: USED_PORT: distance 0 0 4 0 INPUT NODEFVAL "distance[3..0]"
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @direction 0 0 0 0 direction 0 0 0 0
// Retrieval info: CONNECT: @distance 0 0 4 0 distance 0 0 4 0
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL shift16.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL shift16.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL shift16.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL shift16.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL shift16_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL shift16_bb.v FALSE
|
`include "defines.vh"
/**
* @module associative_comparator
* @author sabertazimi
* @email
* @brief associative comparator for BTB
* @input src_tag tag to compare
* @input validx valid bit of line x in BTB
* @input tagx tag bits of line x in BTB
* @output hit flag imply hit or miss
* @output hit_line imply which line hit
*/
module associative_comparator
#(parameter DATA_WIDTH = 32)
(
input [DATA_WIDTH-1:0] src_tag,
input valid0,
input valid1,
input valid2,
input valid3,
input valid4,
input valid5,
input valid6,
input valid7,
input [DATA_WIDTH-1:0] tag0,
input [DATA_WIDTH-1:0] tag1,
input [DATA_WIDTH-1:0] tag2,
input [DATA_WIDTH-1:0] tag3,
input [DATA_WIDTH-1:0] tag4,
input [DATA_WIDTH-1:0] tag5,
input [DATA_WIDTH-1:0] tag6,
input [DATA_WIDTH-1:0] tag7,
output reg hit,
output reg [`BTB_LINE_SIZE-1:0] hit_line
);
wire hit0;
wire hit1;
wire hit2;
wire hit3;
wire hit4;
wire hit5;
wire hit6;
wire hit7;
assign hit0 = valid0 && (src_tag == tag0);
assign hit1 = valid1 && (src_tag == tag1);
assign hit2 = valid2 && (src_tag == tag2);
assign hit3 = valid3 && (src_tag == tag3);
assign hit4 = valid4 && (src_tag == tag4);
assign hit5 = valid5 && (src_tag == tag5);
assign hit6 = valid6 && (src_tag == tag6);
assign hit7 = valid7 && (src_tag == tag7);
always @ (hit0 or hit1 or hit2 or hit3 or hit4 or hit5 or hit6 or hit7) begin
if (hit0) begin
hit <= 1;
hit_line <= 3'd0;
end else if (hit1) begin
hit <= 1;
hit_line <= 3'd1;
end else if (hit2) begin
hit <= 1;
hit_line <= 3'd2;
end else if (hit3) begin
hit <= 1;
hit_line <= 3'd3;
end else if (hit4) begin
hit <= 1;
hit_line <= 3'd4;
end else if (hit5) begin
hit <= 1;
hit_line <= 3'd5;
end else if (hit6) begin
hit <= 1;
hit_line <= 3'd6;
end else if (hit7) begin
hit <= 1;
hit_line <= 3'd7;
end else begin
hit <= 0; // miss
hit_line <= 3'd0;
end
end
endmodule // associative_comparator
|
#include <bits/stdc++.h> using std::cerr; using std::endl; const int N = 2005, INF = 1e9, P = 998244353; int n, G[N][N]; char str[N]; int deg[N]; inline int binom(int x) { return x * (x - 1) / 2; } inline bool check() { std::sort(deg + 1, deg + n + 1); int sum = 0; for (int i = 1; i < n; ++i) { sum += deg[i]; if (sum == binom(i)) return 0; } return 1; } namespace SOL1 { inline bool Check(int s) { for (int i = 1; i <= n; ++i) deg[i] = 0; for (int i = 1; i <= n; ++i) for (int j = 1; j <= n; ++j) { int cnt = ((s >> (i - 1)) & 1) + ((s >> (j - 1)) & 1); if (cnt == 1) { if (G[i][j]) ++deg[i]; } else { if (G[j][i]) ++deg[i]; } } return check(); } inline void solve() { int min = INF, cnt = 0; for (int s = 0; s < 1 << n; ++s) { if (__builtin_popcount(s) > min) continue; if (Check(s)) { if (__builtin_popcount(s) < min) min = __builtin_popcount(s), cnt = 0; if (__builtin_popcount(s) == min) { ++cnt; } } } if (min == INF) puts( -1 ); else { for (int i = 1; i <= min; ++i) cnt = 1ll * cnt * i % P; printf( %d %d n , min, cnt); } } } // namespace SOL1 namespace SOL2 { int buc[N]; inline void solve() { for (int i = 1; i <= n; ++i) for (int j = 1; j <= n; ++j) if (G[j][i]) ++deg[i], ++buc[i]; if (check()) { std::cout << 0 << << 1 << std::endl; return; } int cnt = 0; for (int i = 1; i <= n; ++i) { for (int j = 1; j <= n; ++j) deg[j] = buc[j]; for (int j = 1; j <= n; ++j) { if (G[j][i]) --deg[i], ++deg[j]; if (G[i][j]) ++deg[i], --deg[j]; } cnt += check(); } std::cout << 1 << << cnt << std::endl; } } // namespace SOL2 int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) { scanf( %s , str + 1); for (int j = 1; j <= n; ++j) G[i][j] = str[j] - 0 ; } if (n <= 6) SOL1::solve(); else SOL2::solve(); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFRBP_BLACKBOX_V
`define SKY130_FD_SC_LS__DFRBP_BLACKBOX_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dfrbp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFRBP_BLACKBOX_V
|
#include <bits/stdc++.h> #pragma GCC optimize(2) #pragma GCC optimize(3) #pragma GCC optimize(4) using namespace std; const int N = 1000 + 7; const int inf = 0x3f3f3f3f; const long long INF = 0x3f3f3f3f3f3f3f3f; const int mod = 998244353; const double eps = 1e-8; const double PI = acos(-1); template <class T, class S> inline void add(T &a, S b) { a += b; if (a >= mod) a -= mod; } template <class T, class S> inline void sub(T &a, S b) { a -= b; if (a < 0) a += mod; } template <class T, class S> inline bool chkmax(T &a, S b) { return a < b ? a = b, true : false; } template <class T, class S> inline bool chkmin(T &a, S b) { return a > b ? a = b, true : false; } const int MN = 64; struct Vec { int a[MN]; Vec() { for (int i = 0; i < MN; i++) { a[i] = 0; } } }; struct Matrix { int a[MN][MN]; Matrix(int v = 0) { for (int i = 0; i < MN; i++) { for (int j = 0; j < MN; j++) { a[i][j] = (i == j) ? v : 0; } } } inline Matrix operator*(const Matrix &B) const { Matrix C(0); for (int i = 0; i < MN; i++) { for (int k = 0; k < MN; k++) { if (!a[i][k]) continue; for (int j = 0; j < MN; j++) { C.a[i][j] += 1LL * a[i][k] * B.a[k][j] % mod; if (C.a[i][j] >= mod) C.a[i][j] -= mod; } } } return C; } Vec operator*(const Vec &B) const { Vec C; for (int i = 0; i < MN; i++) { for (int j = 0; j < MN; j++) { add(C.a[i], 1LL * a[i][j] * B.a[j] % mod); } } return C; } } M[30], M2[4]; int n, m, a[N]; int ret[N][4]; vector<pair<int, int> > V[N]; int f[4][4]; int dp[N][4]; bool vis[4]; int v[3]; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); } scanf( %d , &m); for (int i = 1; i <= m; i++) { int x, y, c; scanf( %d%d%d , &x, &y, &c); V[x].push_back(make_pair(y, c)); } for (int i = 1; i <= n; i++) { sort((V[i]).begin(), (V[i]).end()); } for (int i = 1; i <= n; i++) { V[i].push_back(make_pair(a[i] + 1, 1)); } for (int i = 1; i <= 3; i++) { for (int j = 1; j <= 3; j++) { scanf( %d , &f[i][j]); } } for (int mask = 0; mask < MN; mask++) { for (int i = 0; i < 3; i++) { v[i] = mask >> (i * 2) & 3; } for (int color = 1; color <= 3; color++) { memset(vis, 0, sizeof(vis)); if (f[color][1]) vis[v[0]] = true; if (f[color][2]) vis[v[1]] = true; if (f[color][3]) vis[v[2]] = true; int sg = -1; for (int i = 0; i < 4; i++) { if (!vis[i]) { sg = i; break; } } int nmask = sg + (v[0] << 2) + (v[1] << 4); add(M[0].a[nmask][mask], 1); add(M2[color].a[nmask][mask], 1); } } for (int i = 1; i < 30; i++) { M[i] = M[i - 1] * M[i - 1]; } for (int i = 1; i <= n; i++) { Vec tmp; tmp.a[63] = 1; int last = 0; for (auto &t : V[i]) { int cnt = t.first - last - 1; for (int j = 0; j < 30; j++) { if (cnt >> j & 1) { tmp = M[j] * tmp; } } if (t.first != a[i] + 1) { tmp = M2[t.second] * tmp; } last = t.first; } for (int j = 0; j < MN; j++) { add(ret[i][j & 3], tmp.a[j]); } } dp[0][0] = 1; for (int i = 0; i < n; i++) { for (int j = 0; j < 4; j++) { for (int k = 0; k < 4; k++) { add(dp[i + 1][j ^ k], 1LL * dp[i][j] * ret[i + 1][k] % mod); } } } printf( %d n , dp[n][0]); return 0; } |
#include <bits/stdc++.h> using namespace std; int N, i, j, r[55]; long long m, f[55]; void solve(int n, int p, long long m) { if (n == 0) return; for (int i = 1; i <= n && i <= 2; i++) { if (m <= f[n - i]) { solve(n - i, p + i, m); for (int j = p + i; j <= N; j++) r[j] += i; for (int j = p + i - 1, k = 1; j >= p; j--, k++) r[j] = k; break; } else m -= f[n - i]; } } int main() { cin >> N >> m; for (f[0] = i = 1; i <= N; i++) for (j = 1; j <= i && j <= 2; j++) f[i] = min(m + 1, f[i] + f[i - j]); solve(N, 1, m); for (i = 1; i <= N; i++) printf( %d%c , r[i], i == N ? n : ); return 0; } |
`timescale 1ns / 1ps
/***********************************************************************************************************************
* *
* ANTIKERNEL v0.1 *
* *
* Copyright (c) 2012-2017 Andrew D. Zonenberg *
* All rights reserved. *
* *
* Redistribution and use in source and binary forms, with or without modification, are permitted provided that the *
* following conditions are met: *
* *
* * Redistributions of source code must retain the above copyright notice, this list of conditions, and the *
* following disclaimer. *
* *
* * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the *
* following disclaimer in the documentation and/or other materials provided with the distribution. *
* *
* * Neither the name of the author nor the names of any contributors may be used to endorse or promote products *
* derived from this software without specific prior written permission. *
* *
* THIS SOFTWARE IS PROVIDED BY THE AUTHORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL *
* THE AUTHORS BE HELD LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES *
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR *
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
* POSSIBILITY OF SUCH DAMAGE. *
* *
***********************************************************************************************************************/
/**
@file
@author Andrew D. Zonenberg
@brief A block of several SwitchDebouncers
*/
module SwitchDebouncerBlock #(
parameter WIDTH = 4,
parameter INIT_VAL = 0
) (
input wire clk,
input wire[WIDTH-1:0] din,
output wire[WIDTH-1:0] dout,
output wire[WIDTH-1:0] rising,
output wire[WIDTH-1:0] falling
);
genvar i;
generate
for(i=0; i<WIDTH; i = i+1) begin: debouncers
SwitchDebouncer #(
.INIT_VAL(INIT_VAL[i])
) debouncer (
.clk(clk),
.din(din[i]),
.dout(dout[i]),
.rising(rising[i]),
.falling(falling[i])
);
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR4_SYMBOL_V
`define SKY130_FD_SC_HD__NOR4_SYMBOL_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nor4 (
//# {{data|Data Signals}}
input A,
input B,
input C,
input D,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR4_SYMBOL_V
|
`timescale 1ns / 1ns
`define HALT 5'h1F
module opc3tb();
reg [15:0] mem [ 65535:0 ];
reg clk, reset_b;
wire [15:0] addr;
wire rnw ;
wire ceb = 1'b0;
wire oeb = !rnw;
wire [15:0] data = ( !ceb & rnw & !oeb ) ? mem[ addr ] : 16'bz ;
// OPC CPU instantiation
opc3cpu dut0_u (.address(addr), .data(data), .rnw(rnw), .clk(clk), .reset_b(reset_b));
initial
begin
$dumpvars;
$readmemh("test.hex", mem); // Problems with readmemb - use readmemh for now
clk = 0;
reset_b = 0;
#1005 reset_b = 1;
#180000000 $finish;
end
// Simple negedge synchronous memory to avoid messing with delays initially
always @ (negedge clk)
if (!rnw && !ceb && oeb && reset_b)
mem[addr] <= data;
always
begin
#500 clk = !clk;
//$display("%4x %2x %x", dut0_u.PC_q, dut0_u.ACC_q, dut0_u.LINK_q);
end
// Always stop simulation on encountering the halt pseudo instruction
always @ (negedge clk)
if (dut0_u.IR_q== `HALT)
begin
$display("Simulation terminated with halt instruction at time", $time);
$writememh("test.vdump",mem);
$finish;
end
endmodule
|
module SimpleMmu
#(
parameter ROM_SIZE = 256,
parameter RAM_SIZE = 512,
parameter BUS_WIDTH = 8,
parameter ADDRESS_WIDTH = 32,
parameter ROM_DELAY = 2,
parameter RAM_DELAY = 1,
parameter SHIFT = 0
)
(
input wire clk,
input wire reset,
input wire [ADDRESS_WIDTH-1:0] addrA,
input wire [ADDRESS_WIDTH-1:0] addrB,
input wire writeEnable,
input wire [BUS_WIDTH-1:0] dataIn,
input wire requestA,
input wire requestB,
output reg [BUS_WIDTH-1:0] outA,
output reg [BUS_WIDTH-1:0] outB,
output wire busyA,
output wire busyB,
output reg [BUS_WIDTH-1:0] mmioA,
output reg [BUS_WIDTH-1:0] mmioB,
output reg [ADDRESS_WIDTH-1:0] mmioAddrA,
output reg [ADDRESS_WIDTH-1:0] mmioAddrB,
output reg mmioWEA,
output reg mmioWEB
);
reg [ADDRESS_WIDTH-1:0] physAddrA = 0;
reg [ADDRESS_WIDTH-1:0] physAddrB = 0;
wire [BUS_WIDTH-1:0] ramOutA;
wire [BUS_WIDTH-1:0] ramOutB;
wire [BUS_WIDTH-1:0] romOutA;
wire [BUS_WIDTH-1:0] romOutB;
reg portABusy = 0;
reg portBBusy = 0;
reg regBusyA = 0;
reg regBusyB = 0;
assign busyA = regBusyA;
assign busyB = regBusyB;
wire ramBusyA;
wire ramBusyB;
wire ramWriteEnable;
SimpleRam #(.BUS_WIDTH(BUS_WIDTH), .SIZE(RAM_SIZE)) ram(clk, reset, physAddrA, dataIn, ramWriteEnable, physAddrB, ramOutA,
ramOutB, ramBusyA, ramBusyB);
SimpleRom #(.BUS_WIDTH(BUS_WIDTH), .SIZE(ROM_SIZE)) rom(clk, physAddrA, physAddrB, romOutA, romOutB);
reg [7:0] romCounter = 0;
reg srcA = 0;
reg srcB = 0;
assign ramWriteEnable = writeEnable & srcA;
always @(clk)
begin
if(requestA & ~regBusyA)
begin
if(addrA < ROM_SIZE)
begin
srcA = 0;
regBusyA = 1;
romCounter = 0;
physAddrA = addrA >> SHIFT;
end
else if(addrA >= 'hFFFFFD) // Access to the display
begin
mmioA = dataIn;
mmioAddrA = addrA - 'hFFFFFD;
mmioWEA = writeEnable;
end
else
begin
romCounter = 0;
srcA = 1;
regBusyA = 1;
physAddrA = (addrA - ROM_SIZE) >> SHIFT;
end
end
if(requestB & ~regBusyB)
begin
if(addrB < ROM_SIZE)
begin
srcB = 0;
regBusyB = 1;
romCounter = 0;
physAddrB = addrB >> SHIFT;
end
else
begin
romCounter = 0;
srcB = 1;
regBusyB = 1;
physAddrB = (addrB - ROM_SIZE) >> SHIFT;
end
end
if(srcA & regBusyA & romCounter >= RAM_DELAY)
begin
regBusyA = 0;
outA = ramOutA;
end
else if(~srcA & regBusyA & romCounter >= ROM_DELAY)
begin
regBusyA = 0;
outA = romOutA;
end
if(srcB & regBusyB & romCounter >= RAM_DELAY)
begin
regBusyB = 0;
outB = ramOutB;
end
else if(~srcB & regBusyB && romCounter >= ROM_DELAY)
begin
regBusyB = 0;
outB = romOutB;
end
romCounter = romCounter + 1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void fast() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); } const long long maxn = 100; long long mas[maxn], mas2[maxn]; vector<pair<long long, long long> > cur; vector<pair<long long, long long> > ans[maxn]; void split(long long n) { cur.clear(); long long a, b; a = 1, b = 1; for (long long i = 2; i <= n; i++) { if (mas[i] == mas[i - 1] + 1) { b = i; } else { cur.push_back({a, b}); a = i, b = i; } } cur.push_back({a, b}); } signed main() { fast(); long long n, i, j, p, k, a, b; cin >> n; for (i = 1; i <= n; i++) { cin >> mas[i]; } long long x; p = 0; while (true) { split(n); long long sz = cur.size(); if (sz == 1) { break; } p++; x = mas[n]; if (x == n) { x = mas[cur[sz - 2].second]; for (i = 1; i <= n; i++) { if (mas[i] == x + 1) { if (i != 1) { ans[p].push_back({1, i - 1}); } ans[p].push_back({i, cur[sz - 2].first - 1}); ans[p].push_back(cur[sz - 2]); ans[p].push_back(cur[sz - 1]); k = 1; for (j = cur[sz - 1].first; j <= cur[sz - 1].second; j++) { mas2[k] = mas[j]; k++; } for (j = cur[sz - 2].first; j <= cur[sz - 2].second; j++) { mas2[k] = mas[j]; k++; } for (j = i; j <= cur[sz - 2].first - 1; j++) { mas2[k] = mas[j]; k++; } if (i != 1) { for (j = 1; j <= i - 1; j++) { mas2[k] = mas[j]; k++; } } for (k = 1; k <= n; k++) { mas[k] = mas2[k]; } break; } } } else { for (i = 1; i <= n; i++) { if (mas[i] == x + 1) { if (i != 1) { ans[p].push_back({1, i - 1}); } ans[p].push_back({i, cur[sz - 1].first - 1}); ans[p].push_back(cur[sz - 1]); k = 1; for (j = cur[sz - 1].first; j <= cur[sz - 1].second; j++) { mas2[k] = mas[j]; k++; } for (j = i; j <= cur[sz - 1].first - 1; j++) { mas2[k] = mas[j]; k++; } if (i != 1) { for (j = 1; j <= i - 1; j++) { mas2[k] = mas[j]; k++; } } for (k = 1; k <= n; k++) { mas[k] = mas2[k]; } break; } } } } cout << p << endl; for (i = 1; i <= p; i++) { cout << ans[i].size() << ; for (j = 0; j < ans[i].size(); j++) { cout << ans[i][j].second - ans[i][j].first + 1 << ; } cout << endl; } return 0; } |
`timescale 1 ns / 1 ps
module axis_pps_counter #
(
parameter integer AXIS_TDATA_WIDTH = 32,
parameter integer CNTR_WIDTH = 32
)
(
// System signals
input wire aclk,
input wire aresetn,
input wire pps_data,
// Master side
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid
);
reg [CNTR_WIDTH-1:0] int_cntr_reg, int_cntr_next;
reg int_enbl_reg, int_enbl_next;
reg [2:0] int_data_reg;
wire int_edge_wire;
always @(posedge aclk)
begin
if(~aresetn)
begin
int_cntr_reg <= {(CNTR_WIDTH){1'b0}};
int_enbl_reg <= 1'b0;
int_data_reg <= 3'd0;
end
else
begin
int_cntr_reg <= int_cntr_next;
int_enbl_reg <= int_enbl_next;
int_data_reg <= {int_data_reg[1:0], pps_data};
end
end
assign int_edge_wire = ~int_data_reg[2] & int_data_reg[1];
always @*
begin
int_cntr_next = int_cntr_reg + 1'b1;
int_enbl_next = int_enbl_reg;
if(~int_enbl_reg & int_edge_wire)
begin
int_enbl_next = 1'b1;
end
if(int_edge_wire)
begin
int_cntr_next = {(CNTR_WIDTH){1'b0}};
end
end
assign m_axis_tdata = {{(AXIS_TDATA_WIDTH-CNTR_WIDTH){1'b0}}, int_cntr_reg};
assign m_axis_tvalid = int_enbl_reg & int_edge_wire;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, t; cin >> n >> t; if (t == 10) { if (n < 2) { cout << -1 n ; return 0; } cout << 1; for (int i = 0; i < n - 1; i++) cout << 0; cout << n ; return 0; } cout << t; for (int i = 0; i < n - 1; i++) cout << 0; cout << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int inf = 1.01e9; const double eps = 1e-9; const int N = 1e5 + 10; int t[N]; int mem[N]; int main() { int n; scanf( %d , &n); for (int i = 0; (i) < (n); ++i) scanf( %d , &t[i]); int s = 0; for (int i = 0; (i) < (n); ++i) { int v = s + 20; if (i) { int l = lower_bound(t, t + i, t[i] - 90 + 1) - t; v = min(v, mem[l] + 50); } if (i) { int l = lower_bound(t, t + i, t[i] - 1440 + 1) - t; v = min(v, mem[l] + 120); } mem[i + 1] = v; printf( %d n , v - s); s = v; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFRTN_SYMBOL_V
`define SKY130_FD_SC_LS__SDFRTN_SYMBOL_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__sdfrtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK_N
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFRTN_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int t, i, j, f, n; cin >> t; while (t--) { cin >> n; string s; cin >> s; f = 0; for (i = 0; i < n; i++) if (s[i] == 0 ) { f = 1; if (i >= n / 2) cout << 1 << << i + 1 << << 1 << << i << endl; else cout << i + 1 << << n << << i + 2 << << n << endl; break; } if (!f) cout << 1 << << n - 1 << << 2 << << n << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 3e5 + 100; vector<int> edge[N]; vector<long long> w[N]; int n, q, top[N], dfn[N], hson[N], siz[N]; int fa[N]; long long val[N], f[N], g[N]; long long a[N], dv[N]; long long dep[N], faw[N]; void dfs(int x) { f[x] = 0; siz[x] = 1; dv[x] = dv[fa[x]] + a[x]; for (int i = 0; i <= (int)edge[x].size() - 1; ++i) { int y = edge[x][i]; if (y == fa[x]) continue; fa[y] = x; dep[y] = dep[x] + w[x][i]; faw[y] = w[x][i]; dfs(y); siz[x] += siz[y]; if (siz[y] > siz[hson[x]]) hson[x] = y; f[x] = max(f[x], f[x] + f[y] - w[x][i] * 2 + a[y]); } for (int i = 0; i <= (int)edge[x].size() - 1; ++i) { int y = edge[x][i]; if (y == fa[x]) continue; if (f[y] - w[x][i] * 2 + a[y] > 0) val[y] = f[x] - f[y] + w[x][i] * 2 - a[y]; else val[y] = f[x]; } } int tot, an[N]; void dfs2(int x, int k) { top[x] = k; dfn[x] = ++tot; an[tot] = x; if (!hson[x]) return; dfs2(hson[x], k); for (int i = 0; i <= (int)edge[x].size() - 1; ++i) { int y = edge[x][i]; if (y == fa[x] || y == hson[x]) continue; dfs2(y, y); } } void dfs3(int x) { for (int i = 0; i <= (int)edge[x].size() - 1; ++i) { int y = edge[x][i]; if (y == fa[x]) continue; g[y] = g[x] + a[x] - 2 * w[x][i]; if (f[y] - w[x][i] * 2 + a[y] < 0) g[y] += f[x]; else g[y] += f[x] - f[y] + w[x][i] * 2 - a[y]; if (g[y] < 0) g[y] = 0; dfs3(y); } } inline int lca(int x, int y) { while (top[x] != top[y]) { if (dep[top[x]] < dep[top[y]]) swap(x, y); x = fa[top[x]]; } return (dep[x] < dep[y]) ? x : y; } long long st[N]; void init() { st[0] = 0; for (int i = 1; i <= n; ++i) st[i] = st[i - 1] + val[an[i]]; } inline long long rmq(int l, int r) { return st[r] - st[l - 1]; } int son; long long query(int x, int y) { long long res = 0; while (top[x] != top[y]) { res += rmq(dfn[top[x]], dfn[x]); if (fa[top[x]] == y) res -= val[top[x]], son = top[x]; x = fa[top[x]]; } if (!son) son = an[dfn[y] + 1]; if (dfn[y] + 2 <= dfn[x]) res += rmq(dfn[y] + 2, dfn[x]); return res; } int main() { scanf( %d%d , &n, &q); for (int i = 1; i <= n; ++i) scanf( %lld , a + i); for (int i = 1; i <= n - 1; ++i) { int u, v; long long z; scanf( %d%d%lld , &u, &v, &z); edge[u].push_back(v); edge[v].push_back(u); w[u].push_back(z); w[v].push_back(z); } fa[1] = dep[1] = 0; dfs(1); dfs2(1, 1); dfs3(1); init(); for (int i = 1; i <= q; ++i) { int x, y; scanf( %d%d , &x, &y); int w = lca(x, y); long long res = 0; son = 0; if (w == x) { if (w == y) res = f[w] + g[w]; else { res = query(y, w); res += val[son] + g[w] + f[y]; } } else if (w == y) { res = query(x, w); res += val[son] + g[w] + f[x]; } else { res = query(x, w) + g[w]; if (f[son] - 2 * faw[son] + a[son] > 0) res -= f[son] - 2 * faw[son] + a[son]; son = 0; res += query(y, w); res += val[son]; res += f[x] + f[y]; } res += dv[x] + dv[y] - dv[w] - dv[fa[w]] - dep[x] - dep[y] + dep[w] * 2; printf( %lld n , res); } return 0; } |
module premuat1_4(
i_0,
i_1,
i_2,
i_3,
o_0,
o_1,
o_2,
o_3
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input signed [18:0] i_0;
input signed [18:0] i_1;
input signed [18:0] i_2;
input signed [18:0] i_3;
output signed [18:0] o_0;
output signed [18:0] o_1;
output signed [18:0] o_2;
output signed [18:0] o_3;
// ********************************************
//
// Combinational Logic
//
// ********************************************
assign o_0=i_0;
assign o_1=i_2;
assign o_2=i_1;
assign o_3=i_3;
endmodule
|
//-----------------------------------------------------------------------------
// The way that we connect things in low-frequency simulation mode. In this
// case just pass everything through to the ARM, which can bit-bang this
// (because it is so slow).
//
// Jonathan Westhues, April 2006
//-----------------------------------------------------------------------------
module lo_edge_detect(
pck0, ck_1356meg, ck_1356megb,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
cross_hi, cross_lo,
dbg,
divisor,
lf_field
);
input pck0, ck_1356meg, ck_1356megb;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
input cross_hi, cross_lo;
output dbg;
input [7:0] divisor;
input lf_field;
// Divide the clock to be used for the ADC
reg [7:0] pck_divider;
reg clk_state;
wire tag_modulation;
assign tag_modulation = ssp_dout & !lf_field;
wire reader_modulation;
assign reader_modulation = !ssp_dout & lf_field & clk_state;
// No logic, straight through.
assign pwr_oe1 = 1'b0; // not used in LF mode
assign pwr_oe2 = tag_modulation;
assign pwr_oe3 = tag_modulation;
assign pwr_oe4 = tag_modulation;
assign ssp_clk = cross_lo;
assign pwr_lo = reader_modulation;
assign pwr_hi = 1'b0;
assign dbg = ssp_frame;
always @(posedge pck0)
begin
if(pck_divider == divisor[7:0])
begin
pck_divider <= 8'd0;
clk_state = !clk_state;
end
else
begin
pck_divider <= pck_divider + 1;
end
end
assign adc_clk = ~clk_state;
// Toggle the output with hysteresis
// Set to high if the ADC value is above 200
// Set to low if the ADC value is below 64
reg is_high;
reg is_low;
reg output_state;
always @(posedge pck0)
begin
if((pck_divider == 8'd7) && !clk_state) begin
is_high = (adc_d >= 8'd190);
is_low = (adc_d <= 8'd70);
end
end
always @(posedge is_high or posedge is_low)
begin
if(is_high)
output_state <= 1'd1;
else if(is_low)
output_state <= 1'd0;
end
assign ssp_frame = output_state;
endmodule
|
#include <bits/stdc++.h> using namespace std; bool prime[100000 + 5]; int ans[100000 + 5]; int main() { long long int n; cin >> n; for (int i = 0; i <= n; i++) prime[i] = true; long long int k = 1; for (int p = 2; p * p <= n; p++) { if (prime[p] == true) { ans[p] = k; for (int i = p * p; i <= n; i += p) { if (i <= n) { prime[i] = false; ans[i] = k; } } prime[p] = false; k++; } } for (int p = 2; p <= n; p++) { if (prime[p] == true) { for (int i = p; i <= n; i += p) { if (i <= n) { prime[i] = false; ans[i] = k; } } k++; } } for (int p = 2; p <= n; p++) cout << ans[p] << ; } |
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author:
* Description:
*
* Changes:
*/
`include "sd_host_defines.v"
`include "sd_host_stack_defines.v"
module sd_cmd_layer (
input clk,
input rst,
output o_sd_ready,
input i_crc_enable_flag,
input i_card_detect,
input [15:0] i_timeout,
input [31:0] i_block_sleep_count,
output reg o_error_flag,
output reg [7:0] o_error,
//User Command/Response Interface
input i_cmd_en,
output reg o_cmd_finished_en,
input [5:0] i_cmd,
input [31:0] i_cmd_arg,
//Flags
input i_rsp_long,
output [127:0] o_rsp,
//User control side
input i_data_txrx,
input i_data_write_flag,
input [23:0] i_data_size,
output reg o_data_txrx_finished,
input i_data_write_stb,
input i_data_read_stb,
input [2:0] i_func_addr,
input i_data_block_mode,
input [23:0] i_f0_block_size,
input [23:0] i_f1_block_size,
input [23:0] i_f2_block_size,
input [23:0] i_f3_block_size,
input [23:0] i_f4_block_size,
input [23:0] i_f5_block_size,
input [23:0] i_f6_block_size,
input [23:0] i_f7_block_size,
input [23:0] i_mem_block_size,
//Interrupt From the Card
output o_interrupt,
//PHY Layer
output reg o_phy_cmd_en ,
output reg [39:0] o_phy_cmd,
output [7:0] o_phy_cmd_len,
input i_phy_rsp_finished_en,
input [135:0] i_phy_rsp,
output [7:0] o_phy_rsp_len,
input i_phy_crc_bad,
output reg o_data_txrx_activate,
input i_data_txrx_finished,
output [11:0] o_data_byte_count,
output o_data_write_flag,
input i_data_crc_read_err
);
//local parameters
localparam IDLE = 4'h0;
localparam TXRX_BLOCK = 4'h1;
localparam WAIT_RESPONSE = 4'h2;
localparam BLOCK_SLEEP = 4'h3;
localparam FINISHED = 4'h4;
//registes/wires
reg [3:0] state;
reg [3:0] data_state;
reg [23:0] count;
reg infinite_data_txrx;
reg [23:0] transfer_count;
reg [23:0] block_count;
wire [23:0] func_block_size [0:7];
//submodules
//asynchronous logic
assign o_phy_cmd_len = 8'd40;
assign o_rsp = i_phy_rsp[127:0];
//assign o_data_byte_count = i_data_size[11:0];
assign o_data_byte_count = transfer_count[11:0];
assign o_data_write_flag = i_data_write_flag;
assign func_block_size[0] = i_f0_block_size;
assign func_block_size[1] = i_f1_block_size;
assign func_block_size[2] = i_f2_block_size;
assign func_block_size[3] = i_f3_block_size;
assign func_block_size[4] = i_f4_block_size;
assign func_block_size[5] = i_f5_block_size;
assign func_block_size[6] = i_f6_block_size;
assign func_block_size[7] = i_f7_block_size;
assign o_phy_rsp_len = i_rsp_long ? 8'd136 : 8'd40;
//synchronous logic
always @ (posedge clk) begin
//De-assert Strobes
o_phy_cmd_en <= 0;
if (rst) begin
state <= IDLE;
o_phy_cmd <= 0;
o_error <= `ERROR_NO_ERROR;
o_cmd_finished_en <= 0;
end
else begin
case (state)
IDLE: begin
o_phy_cmd_en <= 0;
o_cmd_finished_en <= 0;
o_error <= `ERROR_NO_ERROR;
if (i_cmd_en) begin
o_phy_cmd[39:38] <= 2'b01;
o_phy_cmd[37:32] <= i_cmd;
o_phy_cmd[31:0] <= i_cmd_arg;
o_phy_cmd_en <= 1;
state <= WAIT_RESPONSE;
end
end
WAIT_RESPONSE: begin
o_phy_cmd_en <= 1;
if (i_phy_rsp_finished_en) begin
if (i_crc_enable_flag && i_phy_crc_bad) begin
o_error <= `ERROR_CRC_FAIL;
end
o_phy_cmd_en <= 0;
state <= FINISHED;
end
end
FINISHED: begin
o_cmd_finished_en <= 1;
end
default: begin
end
endcase
//Whenever the host de-asserts command enable go back to IDLE, this way we
//Won't get stuck if something goes buggered
if (!i_cmd_en) begin
state <= IDLE;
end
end
end
always @ (posedge clk) begin
if (rst) begin
o_data_txrx_finished <= 0;
o_data_txrx_activate <= 0;
data_state <= IDLE;
count <= 0;
transfer_count <= 0;
infinite_data_txrx <= 0;
block_count <= 0;
end
else begin
case (data_state)
IDLE: begin
infinite_data_txrx <= 0;
o_data_txrx_finished <= 0;
o_data_txrx_activate <= 0;
count <= 0;
block_count <= 0;
if (i_data_txrx) begin
data_state <= TXRX_BLOCK;
if (i_data_block_mode) begin
if (i_data_size == 0) begin
infinite_data_txrx <= 1;
end
transfer_count <= func_block_size[i_func_addr];
end
else begin
transfer_count <= i_data_size;
end
end
end
TXRX_BLOCK: begin
count <= 0;
o_data_txrx_activate <= 1;
data_state <= WAIT_RESPONSE;
block_count <= block_count + 1;
end
WAIT_RESPONSE: begin
//if (i_data_write_stb || i_data_read_stb) begin
// count <= count + 1;
//end
if (i_data_txrx_finished) begin
o_data_txrx_activate <= 0;
if (i_data_block_mode) begin
if (infinite_data_txrx || (block_count < i_data_size)) begin
data_state <= BLOCK_SLEEP;
end
else begin
count <= 0;
data_state <= FINISHED;
end
end
else begin
data_state <= FINISHED;
end
end
end
BLOCK_SLEEP: begin
if (count < i_block_sleep_count) begin
count <= count + 1;
end
else begin
data_state <= TXRX_BLOCK;
end
end
FINISHED: begin
o_data_txrx_finished <= 1;
end
default: begin
end
endcase
if (!i_data_txrx) begin
data_state <= IDLE;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct Node { int v, index; } a[100005]; int n, h, big, small, tmp, diff, num; int ans[100005]; int cmp(const void *i, const void *j) { Node x = *(Node *)i; Node y = *(Node *)j; if (x.v == y.v) { return x.index > y.index ? 1 : -1; } else { return x.v > y.v ? 1 : -1; } } int main() { while (scanf( %d %d , &n, &h) != EOF) { for (int i = 0; i < n; i++) { scanf( %d , &a[i].v); a[i].index = i; } qsort(a, n, sizeof(a[0]), cmp); num = 0, diff = (a[n - 1].v + a[n - 2].v) - (a[0].v + a[1].v); for (int i = 1; i < n; i++) { small = a[0].v + a[1].v + h; if (i >= 2 && small > a[1].v + a[2].v) small = a[1].v + a[2].v; if (i != n - 1 && small > a[0].v + a[i + 1].v) small = a[0].v + a[i + 1].v; if (i == n - 1) big = a[i].v + a[0].v + h; else big = a[n - 1].v + a[i].v + h; if (big < a[n - 1].v + a[n - 2].v) big = a[n - 1].v + a[n - 2].v; if (diff > big - small) { diff = big - small; num = i; } } fill(ans, ans + n, 1); for (int i = 1; i <= num; i++) ans[a[i].index] = 2; printf( %d n , diff); for (int i = 0; i < n; i++) printf( %d%c , ans[i], i == n - 1 ? n : ); } return 0; } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ctu_clsp_clkgn_nstep.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
//
// Cluster Name: CTU
// Unit Name: ctu_clsp_clkgn_nstep
//
//-----------------------------------------------------------------------------
`include "sys.h"
module ctu_clsp_clkgn_nstep(/*AUTOARG*/
// Outputs
cmp_nstep_sel, jbus_nstep_sel, dram_nstep_sel,
// Inputs
io_pwron_rst_l, jtag_clock_dr_cmp, jtag_clock_dr_dram,
jtag_clock_dr_jbus, jtag_clsp_force_cken_jbus,
jtag_clsp_force_cken_dram, jtag_clsp_force_cken_cmp,
jtag_nstep_count, jtag_nstep_domain, jtag_nstep_vld, cmp_gclk_bypass,
dram_gclk_bypass, jbus_gclk_bypass, capture_l, start_clk_early_jl,
testmode_l, shadreg_div_cmult, shadreg_div_jmult, shadreg_div_dmult
);
input io_pwron_rst_l;
input jtag_clock_dr_cmp;
input jtag_clock_dr_dram;
input jtag_clock_dr_jbus;
input jtag_clsp_force_cken_jbus;
input jtag_clsp_force_cken_dram;
input jtag_clsp_force_cken_cmp;
input [3:0] jtag_nstep_count;
input [2:0] jtag_nstep_domain;
input jtag_nstep_vld;
input cmp_gclk_bypass;
input dram_gclk_bypass;
input jbus_gclk_bypass;
input capture_l;
input start_clk_early_jl;
input testmode_l;
input [13:0] shadreg_div_cmult;
input [9:0] shadreg_div_jmult;
input [9:0] shadreg_div_dmult;
output cmp_nstep_sel;
output jbus_nstep_sel;
output dram_nstep_sel;
/* ctu_clsp_clkgn_nstep_cnt AUTO_TEMPLATE (
.io_pwron_rst_l(io_pwron_rst_l),
.clk (cmp_gclk_bypass),
.jtag_clock_dr(jtag_clock_dr_cmp),
.jtag_nstep_count(jtag_nstep_count[]),
.jtag_nstep_domain(jtag_nstep_domain[0]),
.jtag_nstep_vld(jtag_nstep_vld),
.nstep_sel(cmp_nstep_sel),
.shadreg_div_mult(shadreg_div_cmult[13:0]),
.force_cken(jtag_clsp_force_cken_cmp),
);
*/
ctu_clsp_clkgn_nstep_cnt u_cmp(/*AUTOINST*/
// Outputs
.nstep_sel(cmp_nstep_sel), // Templated
// Inputs
.io_pwron_rst_l(io_pwron_rst_l), // Templated
.clk (cmp_gclk_bypass), // Templated
.jtag_clock_dr(jtag_clock_dr_cmp), // Templated
.jtag_nstep_count(jtag_nstep_count[3:0]), // Templated
.jtag_nstep_domain(jtag_nstep_domain[0]), // Templated
.jtag_nstep_vld(jtag_nstep_vld), // Templated
.capture_l(capture_l),
.testmode_l(testmode_l),
.start_clk_early_jl(start_clk_early_jl),
.shadreg_div_mult(shadreg_div_cmult[13:0]), // Templated
.force_cken(jtag_clsp_force_cken_cmp)); // Templated
/* ctu_clsp_clkgn_nstep_cnt AUTO_TEMPLATE (
.io_pwron_rst_l(io_pwron_rst_l),
.clk (jbus_gclk_bypass),
.jtag_clock_dr(jtag_clock_dr_jbus),
.jtag_nstep_count(jtag_nstep_count[]),
.jtag_nstep_domain(jtag_nstep_domain[2]),
.jtag_nstep_vld(jtag_nstep_vld),
.nstep_sel(jbus_nstep_sel),
.shadreg_div_mult({4'h0,shadreg_div_jmult[9:0]}),
.force_cken(jtag_clsp_force_cken_jbus),
);
*/
ctu_clsp_clkgn_nstep_cnt u_jbus(/*AUTOINST*/
// Outputs
.nstep_sel(jbus_nstep_sel), // Templated
// Inputs
.io_pwron_rst_l(io_pwron_rst_l), // Templated
.clk (jbus_gclk_bypass), // Templated
.jtag_clock_dr(jtag_clock_dr_jbus), // Templated
.jtag_nstep_count(jtag_nstep_count[3:0]), // Templated
.jtag_nstep_domain(jtag_nstep_domain[2]), // Templated
.jtag_nstep_vld(jtag_nstep_vld), // Templated
.capture_l(capture_l),
.testmode_l(testmode_l),
.start_clk_early_jl(start_clk_early_jl),
.shadreg_div_mult({4'h0,shadreg_div_jmult[9:0]}), // Templated
.force_cken(jtag_clsp_force_cken_jbus)); // Templated
/* ctu_clsp_clkgn_nstep_cnt AUTO_TEMPLATE (
.io_pwron_rst_l(io_pwron_rst_l),
.clk (dram_gclk_bypass),
.jtag_clock_dr(jtag_clock_dr_dram),
.jtag_nstep_count(jtag_nstep_count[]),
.jtag_nstep_domain(jtag_nstep_domain[1]),
.jtag_nstep_vld(jtag_nstep_vld),
.nstep_sel(dram_nstep_sel),
.shadreg_div_mult({4'h0,shadreg_div_dmult[9:0]}),
.force_cken(jtag_clsp_force_cken_dram),
);
*/
ctu_clsp_clkgn_nstep_cnt u_dram(/*AUTOINST*/
// Outputs
.nstep_sel(dram_nstep_sel), // Templated
// Inputs
.io_pwron_rst_l(io_pwron_rst_l), // Templated
.clk(dram_gclk_bypass), // Templated
.jtag_clock_dr(jtag_clock_dr_dram), // Templated
.jtag_nstep_count(jtag_nstep_count[3:0]), // Templated
.jtag_nstep_domain(jtag_nstep_domain[1]), // Templated
.jtag_nstep_vld(jtag_nstep_vld), // Templated
.capture_l(capture_l),
.testmode_l(testmode_l),
.start_clk_early_jl(start_clk_early_jl),
.shadreg_div_mult({4'h0,shadreg_div_dmult[9:0]}), // Templated
.force_cken(jtag_clsp_force_cken_dram)); // Templated
endmodule
// Local Variables:
// verilog-library-directories:("." "../../common/rtl")
// verilog-library-files: ("../../common/rtl/swrvr_clib.v")
// verilog-auto-sense-defines-constant:t
// End:
|
#include <bits/stdc++.h> using namespace std; const double pi = acos(-1); const int N = 1e5 + 5; int a[N]; int b[N]; int main() { ios_base::sync_with_stdio(false); int T; cin >> T; while (T--) { int n; cin >> n; vector<int> ve1, ve2; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) cin >> b[i]; for (int i = 0; i < n; i++) ve1.push_back(a[i]); for (int i = 0; i < n; i++) ve2.push_back(b[i]); sort(ve1.begin(), ve1.end()); sort(ve2.begin(), ve2.end()); multiset<pair<int, long long> > mse; bool res = true; for (int i = 0; i < (n + 1) / 2; i++) { int mn = min(a[i], a[n - i - 1]); int mx = max(a[i], a[n - i - 1]); mse.insert({mn, mx}); } for (int i = 0; i < (n + 1) / 2; i++) { int mn = min(b[i], b[n - i - 1]); int mx = max(b[i], b[n - i - 1]); pair<int, long long> x = {mn, mx}; if (mse.find(x) != mse.end()) { mse.erase(mse.find(x)); } else { res = false; } } if (res) cout << YES n ; else cout << NO n ; } return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; const int INF = 1e9, MOD = INF - 1755647; int gcd(int a, int b) { return (b ? gcd(b, a % b) : a); } int power(int a, int b) { return (!b ? 1 : power(a, b / 2) * power(a, b / 2) * (b % 2 ? a : 1)); } int mod(int a) { return (a % MOD + MOD) % MOD; } const int N = 2e5 + 20; struct node { int val = 0; bool marked = false; vector<int> adj; }; int a[N]; node g[N]; set<int> ans; void run(int src) { g[src].marked = true; queue<int> q; q.push(src); while (!q.empty()) { int v = q.front(); q.pop(); g[v].val++; ans.insert(v); for (int u : g[v].adj) { g[u].val++; if (!g[u].marked && g[u].val == a[u]) q.push(u); } } } int32_t main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); int n, m; cin >> n >> m; for (int i = 0; i < m; i++) { int v, u; cin >> v >> u; g[v].adj.push_back(u); g[u].adj.push_back(v); } for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 1; i <= n; i++) if (g[i].val == a[i]) run(i); cout << ans.size() << n ; for (int v : ans) cout << v << ; cout << n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYBUF4S25KAPWR_TB_V
`define SKY130_FD_SC_LP__DLYBUF4S25KAPWR_TB_V
/**
* dlybuf4s25kapwr: Delay Buffer 4-stage 0.25um length inner stage
* gates on keep-alive power rail.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlybuf4s25kapwr.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg KAPWR;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
KAPWR = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 KAPWR = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 KAPWR = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 KAPWR = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 KAPWR = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 KAPWR = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_lp__dlybuf4s25kapwr dut (.A(A), .VPWR(VPWR), .VGND(VGND), .KAPWR(KAPWR), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYBUF4S25KAPWR_TB_V
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact :
//-------------------------------------------------------------------
// Filename : ram_1p.v
// Author : Yibo FAN
// Created : 2012-04-01
// Description : Single Port Ram Model
//
// $Id$
//-------------------------------------------------------------------
`include "enc_defines.v"
module ram_1p (
clk ,
cen_i ,
oen_i ,
wen_i ,
addr_i ,
data_i ,
data_o
);
// ********************************************
//
// Parameter DECLARATION
//
// ********************************************
parameter Word_Width = 32;
parameter Addr_Width = 8;
// ********************************************
//
// Input/Output DECLARATION
//
// ********************************************
input clk; // clock input
input cen_i; // chip enable, low active
input oen_i; // data output enable, low active
input wen_i; // write enable, low active
input [Addr_Width-1:0] addr_i; // address input
input [Word_Width-1:0] data_i; // data input
output [Word_Width-1:0] data_o; // data output
// ********************************************
//
// Register DECLARATION
//
// ********************************************
reg [Word_Width-1:0] mem_array[(1<<Addr_Width)-1:0];
// ********************************************
//
// Wire DECLARATION
//
// ********************************************
reg [Word_Width-1:0] data_r;
// ********************************************
//
// Logic DECLARATION
//
// ********************************************
// mem write
always @(posedge clk) begin
if(!cen_i && !wen_i)
mem_array[addr_i] <= data_i;
end
// mem read
always @(posedge clk) begin
if (!cen_i && wen_i)
data_r <= mem_array[addr_i];
else
data_r <= 'bx;
end
assign data_o = oen_i ? 'bz : data_r;
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A21O_1_V
`define SKY130_FD_SC_HVL__A21O_1_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog wrapper for a21o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__a21o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__a21o_1 (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__a21o_1 (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A21O_1_V
|
#include <bits/stdc++.h> using namespace std; int NewMessages(int right, int left, int k, int size) { int right_border = min(right + k, size - 1); int left_border = max(min(left + k, size - 1), max(0, right - k - 1)); return right_border - left_border; } int main() { int n, k; cin >> n >> k; vector<int> messages(n); for (auto& x : messages) { cin >> x; --x; } vector<int> counts(n, 0); counts[0] = min(static_cast<int>(counts.size()) - 1, k) + 1; for (int i = 1; i < counts.size(); ++i) { if (messages[i] == -1) { counts[i] = min(static_cast<int>(counts.size()) - 1, i + k) - max(0, i - k) + 1; } else { counts[i] = counts[messages[i]] + NewMessages(i, messages[i], k, static_cast<int>(counts.size())); } } for (auto x : counts) { cout << x << ; } cout << n ; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYMETAL6S6S_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__DLYMETAL6S6S_BEHAVIORAL_PP_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__dlymetal6s6s (
VPWR,
VGND,
X ,
A
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
// Local signals
wire buf0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYMETAL6S6S_BEHAVIORAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FAH_FUNCTIONAL_V
`define SKY130_FD_SC_LS__FAH_FUNCTIONAL_V
/**
* fah: Full adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__fah (
COUT,
SUM ,
A ,
B ,
CI
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
// Local signals
wire xor0_out_SUM;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT;
// Name Output Other arguments
xor xor0 (xor0_out_SUM, A, B, CI );
buf buf0 (SUM , xor0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, CI );
and and2 (b_ci , B, CI );
or or0 (or0_out_COUT, a_b, a_ci, b_ci);
buf buf1 (COUT , or0_out_COUT );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__FAH_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; #define IOS ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); #define int long long int #define ld long double #define endl n #define rep(i,a,b) for(int i=a;i<b;i++) #define reprev(i,a,b) for(int i=b-1;i>=a;i--) #define all(c) c.begin(),c.end() #define sz(c) (int)c.size() #define ff first #define ss second #define pii pair<int,int> #define vi vector<int> #define vii vector<pii> #define vin(a,n) vi a(n); rep(k_,0,n) {cin>>a[k_];} #define vout(a) rep(k_,0,sz(a)) {cout<<a[k_]<< ;} cout<<endl; #define pb push_back #define mp make_pair #define mod 1000000007 #define mod2 998244353 #define inf 1e18 #define pi 3.1415926535897932384626 #define tr(container, it) for(auto it = container.begin(); it != container.end(); it++) int power(int x, unsigned int y, int p) { int res = 1; // Initialize result x = x % p; // Update x if it is more than or // equal to p if (x == 0) return 0; // In case x is divisible by p; while (y > 0) { // If y is odd, multiply x with result if (y & 1) res = (res*x) % p; // y must be even now y = y>>1; // y = y/2 x = (x*x) % p; } return res; } int ceill(int a,int b) { return (a+b-1)/b; } #define MAXN 100001 // stores smallest prime factor for every number int spf[MAXN]; // Calculating SPF (Smallest Prime Factor) for every // number till MAXN. // Time Complexity : O(nloglogn) void sieve() { spf[1] = 1; for (int i=2; i<MAXN; i++) // marking smallest prime factor for every // number to be itself. spf[i] = i; // separately marking spf for every even // number as 2 for (int i=4; i<MAXN; i+=2) spf[i] = 2; for (int i=3; i*i<MAXN; i++) { // checking if i is prime if (spf[i] == i) { // marking SPF for all numbers divisible by i for (int j=i*i; j<MAXN; j+=i) // marking spf[j] if it is not // previously marked if (spf[j]==j) spf[j] = i; } } } // A O(log n) function returning primefactorization // by dividing by smallest prime factor at every step vector<int> getFactorization(int x) { vector<int> ret; while (x != 1) { ret.push_back(spf[x]); x = x / spf[x]; } return ret; } int modInverse(int n, int p) { return power(n, p-2, p); } const int N=1000000; int fac[N+1]; void precomp(int p) { fac[0] = 1; for (int i=1 ; i<=N; i++) fac[i] = fac[i-1]*i%p; } // Returns nCr % p using Fermat s little // theorem. int nCrModPFermat(int n, int r, int p) { // Base case if (r==0) return 1; // Fill factorial array so that we // can find all factorial of r, n // and n-r return (fac[n]* modInverse(fac[r], p) % p * modInverse(fac[n-r], p) % p) % p; } signed main() { #ifndef ONLINE_JUDGE freopen( ./input.txt , r , stdin); freopen( ./output.txt , w , stdout); #endif IOS int T; cin>>T; precomp(mod); rep(t,1,T+1) { int n; cin>>n; vin(a,n); int and_val=a[0]; rep(i,1,n) and_val = and_val&a[i]; int freq=0; rep(i,0,n) { if(a[i]==and_val) freq++; } int ans = freq*(freq-1); ans%=mod; ans*=fac[n-2]; ans%=mod; cout<<ans<<endl; } return 0; } |
#include <stdio.h> #include <vector> #include <algorithm> #include <set> #define pii pair<int,int> #define ll long long using namespace std; vector<int> edge[200001]; vector<pii > pt[200001]; int depth[200001]; ll d[200001]; int a[200001],v[200001]; void dfs(int x) { for (auto nxt : edge[x]) { depth[nxt] = depth[x] + 1; dfs(nxt); } } int main() { int t; for (scanf( %d , &t); t--;) { int i, n; for (scanf( %d , &n), i = 1; i <= n; ++i) { edge[i].clear(); pt[i].clear(); d[i] = 0; } for (i = 2; i <= n; ++i) { scanf( %d ,v+i); edge[v[i]].push_back(i); } depth[1] = 1; dfs(1); for (i = 2; i <= n; ++i) { scanf( %d ,a+i); pt[depth[i]].push_back({a[i],i}); } pt[1].push_back({0,1}); for (i = 1; i <= n; ++i) sort(pt[i].begin(), pt[i].end()); int lev = 2; while (pt[lev].size()) { multiset < ll > l, r; for (auto p : pt[lev]) { int x = p.second; r.insert(d[v[x]]+a[x]); } for (auto p : pt[lev]) { int x = p.second; auto it = r.lower_bound(d[v[x]]+a[x]); r.erase(it); if (r.size()) { auto mx = prev(r.end()); d[x] = max(d[x], *mx - a[x]); int rightmost = pt[lev].back().first; d[x] = max(d[x], d[v[x]] + rightmost - a[x]); } if (l.size()) { auto mx = prev(l.end()); d[x] = max(d[x], a[x] + *mx); int leftmost = pt[lev][0].first; d[x] = max(d[x], d[v[x]] + a[x] - leftmost); } l.insert({d[v[x]]-a[x]}); } ++lev; } ll ans = 0; for (i = 1; i <= n; ++i) { if (ans < d[i]) ans = d[i]; } printf( %I64d n ,ans); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 200005, M = N * 4; int n, q, a[N], t, l, r, k; struct sgt { long long p[M], s[M]; void B(int l, int r, int k, bool t) { if (l == r) { if (((l & 1) && !t) || (!(l & 1) && t)) p[k] = min(0, a[l] - a[l - 1]), s[k] = a[l] - a[l - 1]; return; } int mid = l + r >> 1; B(l, mid, k << 1, t); B(mid + 1, r, k << 1 | 1, t); p[k] = min(p[k << 1], s[k << 1] + p[k << 1 | 1]); s[k] = s[k << 1] + s[k << 1 | 1]; } void C(int l, int r, int x, int y, int k) { if (l == r) { s[k] += y; p[k] = min(0ll, s[k]); return; } int mid = l + r >> 1; if (x <= mid) C(l, mid, x, y, k << 1); else C(mid + 1, r, x, y, k << 1 | 1); p[k] = min(p[k << 1], s[k << 1] + p[k << 1 | 1]); s[k] = s[k << 1] + s[k << 1 | 1]; } pair<int, int> G(int l, int r, int x, int y, int k) { if (l == x && y == r) return make_pair(p[k], s[k]); int mid = l + r >> 1; pair<int, int> L, R; if (y <= mid) return G(l, mid, x, y, k << 1); if (x > mid) return G(mid + 1, r, x, y, k << 1 | 1); L = G(l, mid, x, mid, k << 1); R = G(mid + 1, r, mid + 1, y, k << 1 | 1); return make_pair(min(L.first, L.second + R.first), L.second + R.second); } void C(int x, int y) { C(1, n, x, y, 1); } long long G(int x, int y) { return G(1, n, x, y, 1).first; } long long sum(int x, int y) { return G(1, n, x, y, 1).second; } }; struct s_t { sgt p0, p1; long long G(int x) { return p0.sum(1, x) + p1.sum(1, x); } void B() { p0.B(1, n, 1, 0); p1.B(1, n, 1, 1); } void C(int x, int y) { if (x > n) return; else if (x & 1) p0.C(x, y); else p1.C(x, y); } bool c(int l, int r) { long long val = G(l); if (l == r) { if (val > 1) return 0; else return 1; } if (l & 1) { long long tmp = G(r); if (!(r & 1)) tmp = 0; if (p1.sum(l + 1, r) != tmp) return 0; if (p1.G(l + 1, r) < 0) return 0; if (p0.G(l + 1, r) + val < 0) return 0; } else { long long tmp = G(r); if (r & 1) tmp = 0; if (p0.sum(l + 1, r) != tmp) return 0; if (p0.G(l + 1, r) < 0) return 0; if (p1.G(l + 1, r) + val < 0) return 0; } return 1; } } s; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]), a[i]--; s.B(), scanf( %d , &q); for (int _ = 1; _ <= q; _++) { scanf( %d , &t); scanf( %d , &l); scanf( %d , &r); l++, r++; if (t == 1) scanf( %d , &k), s.C(l, k), s.C(r + 1, -k); else printf( %d n , s.c(l, r)); } return 0; } |
#include <bits/stdc++.h> using namespace std; FILE *in; FILE *out; int n, m, k; char a[64][64]; int blocks[64][64]; int cell[64 * 64][2]; int dyn[64 * 64][4][2]; int dir[4][2] = {{-1, 0}, {0, 1}, {1, 0}, {0, -1}}; void fill(int row, int col, int color) { blocks[row][col] = color; for (int i = 0; i < 4; i++) { int nrow = row + dir[i][0]; if (nrow < 0 || nrow >= n) continue; int ncol = col + dir[i][1]; if (ncol < 0 || ncol >= m) continue; if (a[row][col] == a[nrow][ncol] && blocks[nrow][ncol] == -1) fill(nrow, ncol, color); } } void getBlocks() { int nextColor = 0; memset(blocks, -1, sizeof(blocks)); for (int i = 0; i < n; i++) { for (int c = 0; c < m; c++) { if (a[i][c] != 0 && blocks[i][c] == -1) { fill(i, c, nextColor); cell[nextColor][0] = i; cell[nextColor][1] = c; nextColor++; } } } } int main(void) { in = stdin; out = stdout; fscanf(in, %d %d , &n, &k); for (int i = 0; i < n; i++) fscanf(in, %s , a[i]); m = (int)strlen(a[0]); getBlocks(); memset(dyn, -1, sizeof(dyn)); int rem = k, cur = 0; int bp = 0, dp = 1, cp = 0; int foundCycle = 0; while (rem) { rem--; cur++; if (!foundCycle && dyn[bp][dp][cp] != -1) { foundCycle = 1; rem %= (cur - dyn[bp][dp][cp]); } dyn[bp][dp][cp] = cur; int row = cell[bp][0], col = cell[bp][1]; while (1) { int nrow = row + dir[dp][0]; if (nrow < 0 || nrow >= n) break; int ncol = col + dir[dp][1]; if (ncol < 0 || ncol >= m) break; if (a[nrow][ncol] != a[row][col]) break; row = nrow; col = ncol; } int dd = (cp ? ((dp + 1) % 4) : ((dp + 3) % 4)); while (1) { int nrow = row + dir[dd][0]; if (nrow < 0 || nrow >= n) break; int ncol = col + dir[dd][1]; if (ncol < 0 || ncol >= m) break; if (a[nrow][ncol] != a[row][col]) break; row = nrow; col = ncol; } int nrow = row + dir[dp][0]; int ncol = col + dir[dp][1]; if (nrow >= 0 && nrow < n && ncol >= 0 && ncol < m && a[nrow][ncol] != 0 ) { bp = blocks[nrow][ncol]; continue; } if (cp == 0) cp = 1; else { cp = 0; dp = (dp + 1) % 4; } } fprintf(out, %c n , a[cell[bp][0]][cell[bp][1]]); return 0; } |
#include <bits/stdc++.h> using namespace std; int abs(int x) { if (x < 0) return -x; return x; } int up[100005], lo[100005], a[100001][15]; int main() { int n, m, q; scanf( %d , &n), scanf( %d , &m); scanf( %d , &q); int i, j, x, y; for (i = (0); i < (n); i++) { for (j = (0); j < (m); j++) { scanf( %d , &a[i][j]); } } for (i = (0); i < (q); i++) { scanf( %d , &x), scanf( %d , &y); x--, y--; lo[x]--; up[y]++; } for (i = (0); i < (m); i++) { for (j = (0); j < (n); j++) { if (a[j][i]) lo[j] += up[i]; } } for (i = (0); i < (n); i++) { cout << lo[i] << ; } cout << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int q; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> q; while (q--) { bool ch = false; string s; cin >> s; if (s.size() == 1) { if (s[0] == ? ) cout << a ; else cout << s; } else { if (s[0] == ? ) { if (s[1] == a || s[1] == b ) s[0] = c ; else s[0] = a ; } for (int i = 1; i < s.size(); i++) { if (s[i] == ? ) { bool a = 0, b = 0, c = 0; if (s[i - 1] == a || s[i + 1] == a ) a = 1; if (s[i - 1] == b || s[i + 1] == b ) b = 1; if (s[i - 1] == c || s[i + 1] == c ) c = 1; if (!a) s[i] = a ; if (!b) s[i] = b ; if (!c) s[i] = c ; } } if (s[s.size() - 1] == ? ) { if (s[s.size() - 2] == a || s[s.size() - 2] == b ) s[s.size() - 1] = c ; else s[s.size() - 1] = a ; } for (int i = 0; i < s.size() - 1; i++) if (s[i] == s[i + 1]) ch = 1; if (!ch) cout << s; else cout << -1; } cout << n ; } } |
#include <bits/stdc++.h> using namespace std; int main() { int a1[3], a2[3], i; cin >> a1[0] >> a1[1] >> a1[2]; cin >> a2[0] >> a2[1] >> a2[2]; for (i = 0; i < 3; i++) { if (a1[i] == a2[i]) { cout << YES ; return 0; } } cout << NO ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 211, M = N * N / 2; int u[M], v[M], w[M]; int f[N][N]; bool check(int n, int m, int lim) { for (int i = 1; i <= m; i++) { vector<pair<int, int>> v; bool t = 1; for (int j = 1; j <= n; j++) { int l = f[j][u[i]], r = f[j][::v[i]]; if (lim >= l && lim >= r) { if (2 * lim - l - r >= w[i]) { v.push_back({0, 1}); v.push_back({w[i] + 1, -1}); } else { v.push_back({0, 1}); v.push_back({min(w[i], lim - l) + 1, -1}); v.push_back({w[i] - min(w[i], lim - r), 1}); v.push_back({w[i] + 1, -1}); } } else if (lim >= l) { v.push_back({0, 1}); v.push_back({min(w[i], lim - l) + 1, -1}); } else if (lim >= r) { v.push_back({w[i] - min(w[i], lim - r), 1}); v.push_back({w[i] + 1, -1}); } else { t = 0; break; } } if (!t) continue; sort(v.begin(), v.end()); int cnt = 0; for (auto e : v) { cnt += e.second; if (cnt == n) return 1; } } return 0; } int main() { ios ::sync_with_stdio(0); int n, m; cin >> n >> m; memset(f, 0x3f, sizeof f); for (int i = 1; i <= n; i++) f[i][i] = 0; for (int i = 1; i <= m; i++) { cin >> u[i] >> v[i] >> w[i]; w[i] *= 2; f[u[i]][v[i]] = f[v[i]][u[i]] = w[i]; } for (int k = 1; k <= n; k++) for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) f[i][j] = min(f[i][j], f[i][k] + f[k][j]); int l = 0, r = 1e8L; while (l + 1 < r) { int im = (l + r) / 2; if (check(n, m, im - 1)) r = im; else l = im; } cout << fixed << setprecision(1); cout << l / 2.0 << n ; } |
#include <bits/stdc++.h> using namespace std; int n, i, x, y, lsum = 1, root, tot, Ans1, Ans2; int head[400010], f[400010], size[400010], d[400010], p[400010], l[400010], g[400010], o[400010]; vector<int> son[400010]; map<int, int> M; struct Edge { int t, next, l; } e[400010 * 8]; inline int Find(int x) { return (x == p[x]) ? x : p[x] = Find(p[x]); } inline void Add(int s, int t) { e[lsum].t = t; e[lsum].next = head[s]; head[s] = lsum++; } inline int Abs(int x) { return (x < 0) ? -x : x; } inline void Swap(int &a, int &b) { a ^= b ^= a ^= b; } inline int Min(int a, int b) { return (a < b) ? a : b; } inline int Max(int a, int b) { return (a > b) ? a : b; } inline int read() { int p = 0, f = 1; char c = getchar(); while (c < 48 || c > 57) { if (c == - ) f = -1; c = getchar(); } while (c >= 48 && c <= 57) p = (p << 1) + (p << 3) + c - 48, c = getchar(); return p * f; } inline void Maketree(int x, int fa) { int i = 0; size[x] = 1; for (i = head[x]; i; i = e[i].next) { if (e[i].t == fa) continue; f[e[i].t] = x; son[x].push_back(e[i].t); Maketree(e[i].t, x); size[x] += size[e[i].t]; } } inline void Dfs(int x) { if (!son[x].size()) { o[p[x]] = 1; return; } for (auto i : son[x]) { Dfs(i); g[p[x]] += o[p[i]]; o[p[x]] += g[p[i]]; } if (g[p[x]] && o[p[x]]) Ans1 = 3; } int main() { n = read(); for (i = 1; i < n; i++) { x = read(); y = read(); Add(x, y); Add(y, x); d[x]++; d[y]++; } for (i = 1; i <= n; i++) if (d[i] > 1) { root = i; break; } Maketree(root, 0); for (i = 1; i <= n; i++) p[i] = n + i; for (i = 1; i <= n; i++) if (!son[i].size()) p[i] = p[f[i]]; for (i = 1; i <= n; i++) if (p[i] == n + i) p[i] = i; for (i = 1; i <= n; i++) if (!M[p[i]]) Ans2++, M[p[i]]++; Ans1 = 1; Dfs(root); printf( %d %d n , Ans1, Ans2 - 1); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, N, id[6100]; bool judge(int n) { if (n < 2) return false; for (int i = 2; i * i <= n; i++) if (n % i == 0) return false; return true; } void work() { if (judge(N)) return; if (N % 2 && !judge(N - 2)) N -= 3, id[3] = 3; for (int i = 1; i <= n; i++) { if (judge(i) && judge(N - i)) { id[i] = 2; break; } } } int main() { cin >> n; N = n * (n + 1) / 2; for (int i = 1; i <= n; i++) id[i] = 1; if (n == 1) puts( -1 ); work(); for (int i = 1; i <= n; i++) cout << id[i] << ; return 0; } |
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlslice:1.0
// IP Revision: 0
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xlslice_1_0 (
Din,
Dout
);
input wire [39 : 0] Din;
output wire [0 : 0] Dout;
xlslice #(
.DIN_WIDTH(40),
.DIN_FROM(0),
.DIN_TO(0)
) inst (
.Din(Din),
.Dout(Dout)
);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// vim:set shiftwidth=3 softtabstop=3 expandtab:
//
// Module: store_pkt.v
// Project: NF2.1
// Description: stores incoming packet into the SRAM, sends new wr addres to regs
//
// Note: Assumes that the length header is FIRST!
//
///////////////////////////////////////////////////////////////////////////////
module store_pkt
#(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH=DATA_WIDTH/8,
parameter NUM_OUTPUT_QUEUES = 5,
parameter SRAM_ADDR_WIDTH = 13,
parameter PKT_LEN_WIDTH = 11,
parameter PKT_WORDS_WIDTH = PKT_LEN_WIDTH-log2(CTRL_WIDTH),
parameter OQ_STAGE_NUM = 6,
parameter NUM_OQ_WIDTH = log2(NUM_OUTPUT_QUEUES)
)
( // --- Interface to header_parser
dst_oq_avail,
parsed_dst_oq,
parsed_pkt_byte_len,
parsed_pkt_word_len,
rd_dst_oq,
// --- Interface to registers
dst_oq_wr_addr_new,
pkt_stored,
pkt_dropped,
stored_pkt_data_length,
stored_pkt_overhead_length,
stored_pkt_total_word_length,
dst_oq,
rd_dst_addr,
dst_oq_high_addr,
dst_oq_low_addr,
dst_oq_wr_addr,
dst_oq_full,
// --- Interface to SRAM
wr_0_addr,
wr_0_req,
wr_0_ack,
wr_0_data,
// --- Interface to input fifo
input_fifo_rd_en,
input_fifo_empty,
input_fifo_data_out,
input_fifo_ctrl_out,
// --- misc
clk,
reset
);
input dst_oq_avail;
input [NUM_OQ_WIDTH-1:0] parsed_dst_oq;
input [PKT_LEN_WIDTH-1:0] parsed_pkt_byte_len;
input [PKT_WORDS_WIDTH-1:0] parsed_pkt_word_len;
output reg rd_dst_oq;
// --- Interface to registers
output reg [SRAM_ADDR_WIDTH-1:0] dst_oq_wr_addr_new;
output reg pkt_stored;
output reg pkt_dropped;
output reg [PKT_LEN_WIDTH-1:0] stored_pkt_data_length;
output reg [CTRL_WIDTH-1:0] stored_pkt_overhead_length;
output reg [PKT_WORDS_WIDTH-1:0] stored_pkt_total_word_length;
output reg [NUM_OQ_WIDTH-1:0] dst_oq;
output reg rd_dst_addr;
input [SRAM_ADDR_WIDTH-1:0] dst_oq_high_addr;
input [SRAM_ADDR_WIDTH-1:0] dst_oq_low_addr;
input [SRAM_ADDR_WIDTH-1:0] dst_oq_wr_addr;
input [NUM_OUTPUT_QUEUES-1:0] dst_oq_full;
// --- Interface to SRAM
output reg [SRAM_ADDR_WIDTH-1:0] wr_0_addr;
output reg wr_0_req;
input wr_0_ack;
output reg [DATA_WIDTH+CTRL_WIDTH-1:0] wr_0_data;
// --- Interface to input fifo
output reg input_fifo_rd_en;
input input_fifo_empty;
input [DATA_WIDTH-1:0] input_fifo_data_out;
input [CTRL_WIDTH-1:0] input_fifo_ctrl_out;
// --- misc
input clk;
input reset;
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
//--------------------- Internal parameters --------------------------
parameter NUM_STORE_STATES = 7;
parameter ST_WAIT_DST_PORT = 1;
parameter ST_READ_ADDR = 2;
parameter ST_LATCH_ADDR = 4;
parameter ST_MOVE_PKT = 8;
parameter ST_WAIT_FOR_DATA = 16;
parameter ST_WAIT_EOP = 32;
parameter ST_DROP_PKT = 64;
parameter COUNT_IDLE = 1;
parameter COUNT_HDRS = 2;
parameter COUNT_DATA = 4;
//------------------------ Wires/regs --------------------------------
reg [NUM_STORE_STATES-1:0] store_state;
reg [NUM_STORE_STATES-1:0] store_state_next;
wire [SRAM_ADDR_WIDTH-1:0] wr_0_addr_plus1;
reg [SRAM_ADDR_WIDTH-1:0] wr_0_addr_next;
reg [DATA_WIDTH+CTRL_WIDTH-1:0] wr_0_data_next;
reg wr_0_req_next;
wire eop;
reg input_fifo_ctrl_out_prev_is_0;
reg [NUM_OQ_WIDTH-1:0] dst_oq_next;
reg [PKT_LEN_WIDTH-1:0] pkt_byte_len;
reg [PKT_LEN_WIDTH-1:0] pkt_byte_len_next;
reg [PKT_WORDS_WIDTH-1:0] pkt_word_len;
reg [PKT_WORDS_WIDTH-1:0] pkt_word_len_next;
reg [SRAM_ADDR_WIDTH-1:0] lo_addr;
reg [SRAM_ADDR_WIDTH-1:0] lo_addr_next;
reg [SRAM_ADDR_WIDTH-1:0] hi_addr;
reg [SRAM_ADDR_WIDTH-1:0] hi_addr_next;
//-------------------------- Logic -----------------------------------
/* wrap around the address */
assign wr_0_addr_plus1 = (wr_0_addr >= hi_addr) ?
lo_addr : wr_0_addr + 1;
assign eop = (input_fifo_ctrl_out_prev_is_0 && input_fifo_ctrl_out!=0);
/*******************************************************
* wait until the dst port fifo has a destination
* then read the dst port, load the addresses to use,
* and start moving data from the input fifo to the
* sram queues. When the eop is reached, write the pkt
* length in the beginning of the pkt
* If the oq is full then drop pkt.
* Also generate pkt_stored and pkt_dropped signals
*******************************************************/
always @(*) begin
rd_dst_oq = 0;
rd_dst_addr = 0;
store_state_next = store_state;
wr_0_req_next = wr_0_req;
input_fifo_rd_en = 0;
pkt_dropped = 0;
wr_0_data_next = wr_0_data;
wr_0_addr_next = wr_0_addr;
dst_oq_wr_addr_new = wr_0_addr_plus1;
pkt_stored = 0;
dst_oq_next = dst_oq;
pkt_byte_len_next = pkt_byte_len;
pkt_word_len_next = pkt_word_len;
lo_addr_next = lo_addr;
hi_addr_next = hi_addr;
case(store_state)
/* wait until we have a destination port */
ST_WAIT_DST_PORT: begin
if(dst_oq_avail) begin
store_state_next = ST_READ_ADDR;
dst_oq_next = parsed_dst_oq;
pkt_byte_len_next = parsed_pkt_byte_len;
pkt_word_len_next = parsed_pkt_word_len;
rd_dst_oq = 1;
end
end
// Request the destination address
ST_READ_ADDR: begin
store_state_next = ST_LATCH_ADDR;
rd_dst_addr = 1;
end
// Latch the destination addresses (write pointer, lo and hi
// addresses)
ST_LATCH_ADDR: begin
if(!dst_oq_full[dst_oq]) begin
store_state_next = ST_MOVE_PKT;
wr_0_req_next = 1;
wr_0_addr_next = dst_oq_wr_addr;
lo_addr_next = dst_oq_low_addr;
hi_addr_next = dst_oq_high_addr;
/* fifos are first-word fallthrough so the data is already available at the output */
wr_0_data_next = {input_fifo_ctrl_out, input_fifo_data_out};
input_fifo_rd_en = 1;
end
else begin
store_state_next = ST_DROP_PKT;
input_fifo_rd_en = !input_fifo_empty;
end
end // case: ST_WAIT_DST_PORT
/* pipeline is full */
ST_MOVE_PKT: begin
if(wr_0_ack & !input_fifo_empty) begin
wr_0_req_next = 1;
wr_0_addr_next = wr_0_addr_plus1;
wr_0_data_next = {input_fifo_ctrl_out, input_fifo_data_out};
input_fifo_rd_en = 1;
if(eop) begin
store_state_next = ST_WAIT_EOP;
end
end
else if (wr_0_ack & input_fifo_empty) begin
store_state_next = ST_WAIT_FOR_DATA;
wr_0_req_next = 0;
end
end // case: ST_MOVE_PKT
/* Wait until the fifo is not empty */
ST_WAIT_FOR_DATA: begin
if(!input_fifo_empty) begin
wr_0_req_next = 1;
wr_0_addr_next = wr_0_addr_plus1;
wr_0_data_next = {input_fifo_ctrl_out, input_fifo_data_out};
input_fifo_rd_en = 1;
if(eop) begin
store_state_next = ST_WAIT_EOP;
end
else begin
store_state_next = ST_MOVE_PKT;
end
end // if (wr_0_ack)
end // case: ST_WAIT_FOR_DATA
ST_WAIT_EOP: begin
if(wr_0_ack) begin
wr_0_req_next = 0;
pkt_stored = 1;
store_state_next = ST_WAIT_DST_PORT;
end // if (wr_0_ack)
end // case: ST_WAIT_LEN
ST_DROP_PKT: begin
if(eop) begin
store_state_next = ST_WAIT_DST_PORT;
pkt_dropped = 1;
end
input_fifo_rd_en = !input_fifo_empty;
end
default: begin end
endcase // case(store_state)
end // always @ (*)
always @(posedge clk) begin
if(reset) begin
store_state <= ST_WAIT_DST_PORT;
input_fifo_ctrl_out_prev_is_0 <= 0;
wr_0_req <= 0;
wr_0_addr <= 0;
wr_0_data <= 0;
dst_oq <= 0;
pkt_byte_len <= 0;
pkt_word_len <= 0;
lo_addr <= 0;
hi_addr <= 0;
end
else begin
store_state <= store_state_next;
wr_0_req <= wr_0_req_next;
wr_0_addr <= wr_0_addr_next;
wr_0_data <= wr_0_data_next;
dst_oq <= dst_oq_next;
pkt_byte_len <= pkt_byte_len_next;
pkt_word_len <= pkt_word_len_next;
lo_addr <= lo_addr_next;
hi_addr <= hi_addr_next;
if(input_fifo_rd_en) begin
input_fifo_ctrl_out_prev_is_0 <= (input_fifo_ctrl_out==0);
end
end // else: !if(reset)
// synthesis translate_off
if(store_state_next == ST_DROP_PKT) begin
$display("%t %m WARNING: output queue %u is full. Pkt is being dropped.", $time, dst_oq);
end
// synthesis translate_on
end // always @ (posedge clk)
always @(posedge clk) begin
stored_pkt_data_length <= pkt_byte_len;
stored_pkt_overhead_length <= CTRL_WIDTH;
// Calculate the total WORD length
stored_pkt_total_word_length <= pkt_word_len + 1;
end
endmodule // store_pkt
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O31AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__O31AI_FUNCTIONAL_PP_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o31ai (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
A3 ,
B1
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
// Local signals
wire B1 or0_out ;
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O31AI_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; cout << fixed << setprecision(0) << powl(2, n + 1) - 2; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:24:43 06/12/2013
// Design Name: TopModule
// Module Name: D:/Xilinx_ISE_Pro/maju_ASIC_FPGA/SINGLECycle/main_Unit/testbnch.v
// Project Name: main_Unit
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: TopModule
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testbnch;
// Inputs
reg clk;
reg rst;
// Outputs
wire AN0;
wire AN1;
wire AN2;
wire AN3;
wire CA;
wire CB;
wire CC;
wire CD;
wire CE;
wire CF;
wire CG;
wire CDP;
wire clktick;
// Instantiate the Unit Under Test (UUT)
TopModule uut (
.clk(clk),
.rst(rst),
.AN0(AN0),
.AN1(AN1),
.AN2(AN2),
.AN3(AN3),
.CA(CA),
.CB(CB),
.CC(CC),
.CD(CD),
.CE(CE),
.CF(CF),
.CG(CG),
.CDP(CDP),
.clktick(clktick)
);
localparam T =20;
always begin
clk = 0;
#(T/2);
clk=1;
#(T/2);
end
initial begin
// Initialize Inputs
rst = 1;
// Wait 100 ns for global reset to finish
#100;
rst = 0;
#600;
rst = 1;
#20;
rst = 0;
// Add stimulus here
end
endmodule
|
#include <bits/stdc++.h> const int MaxN = 3e5; int n, m, a[MaxN], p[MaxN]; int leaf, tr[MaxN * 2]; void build(int n) { leaf = n; for (int i = 0; i < n; ++i) tr[i + leaf] = a[i] > a[i + 1]; for (int i = leaf - 1; i; --i) tr[i] = tr[i << 1] + tr[i << 1 | 1]; } void upd(int x, int val) { tr[x += leaf] += val; while (x >>= 1) tr[x] += val; } int find(int l, int r) { int ans = 0; for (l += leaf, r += leaf; l <= r; l >>= 1, r >>= 1) { if (l & 1) ans += tr[l++]; if (~r & 1) ans += tr[r--]; } return ans; } void adjust(int x) { int _x = x + leaf; if (x) { if (tr[_x - 1] && a[x - 1] < a[x]) upd(x - 1, -1); if (!tr[_x - 1] && a[x - 1] > a[x]) upd(x - 1, 1); } if (x < n - 1) { if (tr[_x] && a[x] < a[x + 1]) upd(x, -1); if (!tr[_x] && a[x] > a[x + 1]) upd(x, 1); } } int main() { scanf( %d , &n); for (int i = 0; i < n; ++i) { scanf( %d , p + i); a[--p[i]] = i; } build(n); scanf( %d , &m); for (int i = 0; i < m; ++i) { int type; scanf( %d , &type); if (type & 1) { int l, r; scanf( %d %d , &l, &r); printf( %d n , 1 + find(l - 1, r - 2)); } else { int x, y; scanf( %d %d , &x, &y); --x; --y; std::swap(a[p[x]], a[p[y]]); std::swap(p[x], p[y]); adjust(p[x]); adjust(p[y]); } } return 0; } |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / General Purpose Buffer
// /___/ /\ Filename : BUF.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:13 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module BUF (O, I);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output O;
input I;
buf B1 (O, I);
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; ifstream f( date.in ); queue<long long> q; long long n, k, fr[1000001]; long long GCD(long long x, long long y) { long long r; do { r = x % y; x = y; y = r; } while (y != 0); return x; } int main() { long long ans; cin >> n >> k; ans = k; for (int i = 1; i <= n; i++) { long long x; cin >> x; ans = GCD(x, ans); } cout << k / ans << n ; for (int i = 0; i < k / ans; i++) cout << i * ans << ; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, x; cin >> n; long ans = 0; vector<int> divisiors, dp(1e6 + 1); dp[0] = 1; for (int i = 0; i < n; i++) { cin >> x; divisiors.clear(); for (int j = 1; j * j <= x; j++) { if (x % j == 0) { divisiors.push_back(j); if (j != x / j) divisiors.push_back(x / j); } } sort(divisiors.begin(), divisiors.end()); reverse(divisiors.begin(), divisiors.end()); for (int z = 0; z < divisiors.size(); z++) { dp[divisiors[z]] += dp[divisiors[z] - 1]; dp[divisiors[z]] %= (int)1e9 + 7; } } for (int i = 1; i <= 1e6; i++) { ans += dp[i]; ans %= (int)1e9 + 7; } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; long long int a, b; long long int x, y; long long int n, t; bool flag = false; string str; int main() { long long int a[4]; cin >> a[0] >> a[1] >> a[2] >> a[3]; sort(a, a + 4); if ((a[0] + a[1] < a[2]) && (a[1] + a[2] < a[3])) str = IMPOSSIBLE ; else if (a[0] + a[1] > a[2] || a[1] + a[2] > a[3]) str = TRIANGLE ; else str = SEGMENT ; cout << str; return 0; } |
#include <bits/stdc++.h> int sta[1000001], head, ans[1000001]; char s[1000001]; int main() { int ans1 = 0, ans2 = 1; scanf( %s , s); for (int i = 0; s[i]; ++i) { if (s[i] == ) ) { if (!head) continue; head--; ans[i] = i - sta[head] + 1 + ans[sta[head] - 1]; if (ans1 == ans[i]) ans2++; else if (ans1 < ans[i]) { ans1 = ans[i]; ans2 = 1; } } else sta[head++] = i; } printf( %d %d , ans1, ans2); return 0; } |
/*
* MBus Copyright 2015 Regents of the University of Michigan
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
//*******************************************************************************************
//Author: ZhiYoong Foo ()
//Last Modified: Feb 25 2014
//Description: MBUS Layer Controller's Clock Generator
// Custom Block
//Update History: Feb 25 2014 - First commit
//*******************************************************************************************
module clkgen
(
//**************************************
//Power Domain
//Input - Layer Controller Domain
//Output - N/A
//**************************************
//Signals
//Input
CLK_RING_ENn, //Active Low
CLK_GATE, //Active High
CLK_TUNE, //Tuning Bits
//Output
CLK_OUT
);
input CLK_RING_ENn;
input CLK_GATE;
input [3:0] CLK_TUNE;
//Output
output reg CLK_OUT;
initial begin
CLK_OUT <= 1'b0;
end
always @ (CLK_RING_ENn or CLK_GATE or CLK_OUT) begin
if (~CLK_RING_ENn && ~CLK_GATE) begin
`CLK_HALF_PERIOD;
CLK_OUT <= ~CLK_OUT;
end
else begin
CLK_OUT <= 1'b0;
end
end
always @(CLK_TUNE) begin
$write("%c[1;34m",27);
$display("CLKGEN Input CLK_TUNE Has been changed to:%x", CLK_TUNE);
$write("%c[0m",27);
end
endmodule // clkgen
|
#include <bits/stdc++.h> using namespace std; vector<vector<int> > a; bool g[100][100]; bool used[100]; int n; void dfs(int v) { used[v] = true; for (int i = 0; i < n; i++) if (g[v][i] && !used[i]) dfs(i); } int main() { int m; cin >> n >> m; bool now = false; for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) g[i][j] = false; for (int i = 0; i < n; i++) used[i] = false; a.resize(n); for (int i = 0; i < n; i++) { int num; cin >> num; if (num != 0) now = true; a[i].resize(num); for (int j = 0; j < num; j++) { cin >> a[i][j]; a[i][j]--; } } for (int i = 0; i < n; i++) for (int j = i + 1; j < n; j++) for (int i1 = 0; i1 < a[i].size(); i1++) for (int j1 = 0; j1 < a[j].size(); j1++) if (a[i][i1] == a[j][j1]) { g[i][j] = true; g[j][i] = true; } int result = 0; for (int i = 0; i < n; i++) if (!used[i]) { dfs(i); result++; } if (!now) result++; cout << result - 1; } |
#include <bits/stdc++.h> int main() { int a, b, y, ans; scanf( %d%d , &a, &b); y = a * b; ans = y / 2; printf( %d , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int q; long long L, R; set<long long> s; long long v2[2000002], x; void precalculate() { long long LLMAX = 1e18; for (int i = 2; i <= 1000000; ++i) { long long x = 1LL * i * i * i; while (1) { if ((int)sqrt(x) != sqrt(x)) s.insert(x); if (x <= LLMAX / i) x = x * i; else break; } } for (set<long long>::iterator it = s.begin(); it != s.end(); ++it) v2[++x] = *it; v2[x + 1] = 2e18; } long long cb(long long nr) { int b = 1; int e = x; while (b <= e) { int m = (b + e) / 2; if (v2[m] <= nr && v2[m + 1] > nr) return m; if (v2[m] <= nr) b = m + 1; else e = m - 1; } return 0; } long long cb2(long long nr) { int b = 0; int e = 1e9; while (b <= e) { int m = (b + e) / 2; if (1LL * m * m <= nr && 1LL * (m + 1) * (m + 1) > nr) return m; if (1LL * m * m <= nr) b = m + 1; else e = m - 1; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> q; precalculate(); for (int i = 1; i <= q; ++i) { cin >> L >> R; long long sol = cb(R) - cb(L - 1) + cb2(R) - cb2(L - 1); cout << sol << n ; } return 0; } |
//
// Copyright (C) 2009-2012 Chris McClelland
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module
seven_seg#(
parameter
// This can be overridden to change the refresh rate. The anode pattern will change at a
// frequency given by F(clk_in) / (2**COUNTER_WIDTH). So for a 50MHz clk_in and
// COUNTER_WIDTH=18, the anode pattern changes at ~191Hz, which means each digit gets
// refreshed at ~48Hz.
COUNTER_WIDTH = 18
)(
input wire clk_in,
input wire[15:0] data_in,
input wire[3:0] dots_in,
output wire[7:0] segs_out,
output wire[3:0] anodes_out
);
reg[COUNTER_WIDTH-1:0] count = 0;
wire[COUNTER_WIDTH-1:0] count_next;
wire[1:0] anodeSelect;
wire[3:0] nibble;
wire[6:0] segs;
wire dot;
// Infer counter register
always @(posedge clk_in)
count <= count_next;
// Increment counter and derive anode select from top two bits
assign count_next = count + 1'b1;
assign anodeSelect = count[COUNTER_WIDTH-1:COUNTER_WIDTH-2];
// Drive anodes
assign anodes_out =
(anodeSelect == 2'b00) ? 4'b0111 :
(anodeSelect == 2'b01) ? 4'b1011 :
(anodeSelect == 2'b10) ? 4'b1101 :
4'b1110;
// Select the appropriate bit from dots_in
assign dot =
(anodeSelect == 2'b00) ? ~(dots_in[3]) :
(anodeSelect == 2'b01) ? ~(dots_in[2]) :
(anodeSelect == 2'b10) ? ~(dots_in[1]) :
~(dots_in[0]);
// Choose a nibble to display
assign nibble =
(anodeSelect == 2'b00) ? data_in[15:12] :
(anodeSelect == 2'b01) ? data_in[11:8] :
(anodeSelect == 2'b10) ? data_in[7:4] :
data_in[3:0];
// Decode chosen nibble
assign segs =
(nibble == 4'b0000) ? 7'b1000000 :
(nibble == 4'b0001) ? 7'b1111001 :
(nibble == 4'b0010) ? 7'b0100100 :
(nibble == 4'b0011) ? 7'b0110000 :
(nibble == 4'b0100) ? 7'b0011001 :
(nibble == 4'b0101) ? 7'b0010010 :
(nibble == 4'b0110) ? 7'b0000010 :
(nibble == 4'b0111) ? 7'b1111000 :
(nibble == 4'b1000) ? 7'b0000000 :
(nibble == 4'b1001) ? 7'b0010000 :
(nibble == 4'b1010) ? 7'b0001000 :
(nibble == 4'b1011) ? 7'b0000011 :
(nibble == 4'b1100) ? 7'b1000110 :
(nibble == 4'b1101) ? 7'b0100001 :
(nibble == 4'b1110) ? 7'b0000110 :
7'b0001110;
// Drive segs_out
assign segs_out = {dot, segs};
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR3B_4_V
`define SKY130_FD_SC_HD__OR3B_4_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog wrapper for or3b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__or3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__or3b_4 (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__or3b_4 (
X ,
A ,
B ,
C_N
);
output X ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR3B_4_V
|
`timescale 1ns/1ns
`define IDLE 2'b00
`define LOAD 2'b01
`define CNTING 2'b10
`define INT 2'b11
`define MODE_0 2'b00
`define MODE_1 2'b01
module coco_timer (clk_i,rst_i,add_i,we_i,dat_i,dat_o,irq);
input [3:2] add_i;
input clk_i,rst_i,we_i;
input [31:0] dat_i;
output [31:0] dat_o;
output irq;
reg [31:0] count;
reg [31:0] preset;
reg [31:0] ctrl;
reg _irq;
reg [1:0] curr_state,next_state;
assign dat_o=(add_i==2'b00)?ctrl:
(add_i==2'b01)?preset:
(add_i==2'b10)?count:
32'h12345678;
assign irq=_irq;
always @(posedge clk_i or posedge rst_i) begin
if (rst_i) begin
count<=31'h0000_0000;
preset<=31'h0000_0000;
ctrl<=31'h0000_0000;
_irq<=0;
curr_state<=`IDLE;
end // if(rst)
else if (we_i) begin
if (add_i==2'b00) begin
ctrl<=dat_i;
curr_state<=next_state;
end // if(dat_i)
else if (add_i==2'b01) begin
preset<=dat_i;
_irq<=0;
next_state<=`LOAD;
end // if(add_i=2'b01)
else if (add_i==2'b10) begin
count<=dat_i;
curr_state<=next_state;
end
else begin
curr_state<=next_state;
end
end // if(we)
else begin
curr_state<=next_state;
end
end // always @ (posedge clk_i or posedge rst_i)
always @(curr_state or ctrl or count) begin
next_state=`IDLE;
if (!ctrl[0]) begin
next_state=`IDLE;
end // if(ctrl[0])
else begin
case (curr_state)
`IDLE: begin
if (ctrl[2:1]==`MODE_1) begin
next_state=`LOAD;
end // if(ctrl[2:1])
//ctrl[2:1]==`MODE_0
else if (ctrl[0] && count>1) begin
next_state=`CNTING;
end
else begin
next_state=`IDLE;
end
end // case: IDLE
`LOAD: begin
next_state=`CNTING;
end
`CNTING: begin
if (count==1) begin
next_state=`INT;
end // if(count==1)
else begin
next_state=`CNTING;
end
end
default: begin
next_state=`IDLE;
end
endcase // case(curr_state)
end
end // always @ (curr_state)
always @(posedge clk_i or posedge rst_i) begin
case (next_state)
`CNTING: begin
count<=count-1;
end
`INT: begin
_irq<=(ctrl[3]&&ctrl[2:1]==`MODE_0);
end
`LOAD: begin
count<=preset;
_irq<=0;
end
default: begin
//do nothing
end
endcase // case(next_state)
end
endmodule // cp0
|
#include <bits/stdc++.h> using namespace std; const long long N = 1e6 + 5; long long n; long long a[N]; int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; cin >> n; if (n == 0) { cout << 1 1 ; return 0; } long long l = 1, r = n; for (long long cur = 1; cur <= n; cur += 2) { a[l++] = cur; a[r--] = cur; } l = n + 1; r = 2 * n - 1; for (long long cur = 2; cur <= n; cur += 2) { a[l++] = cur; a[r--] = cur; } for (long long i = 1; i <= 2 * n; i++) { if (a[i] == 0) a[i] = n; cout << a[i] << ; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_DLATCH_PR_SYMBOL_V
`define SKY130_FD_SC_HD__UDP_DLATCH_PR_SYMBOL_V
/**
* udp_dlatch$PR: D-latch, gated clear direct / gate active high
* (Q output UDP)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__udp_dlatch$PR (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET,
//# {{clocks|Clocking}}
input GATE
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_DLATCH_PR_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; vector<long long> pos, neg, a; for (int i = 0; i < n; i++) { long long x; cin >> x; a.push_back(x); if (x >= 0) pos.push_back(x); else neg.push_back(x); } sort((pos).begin(), (pos).end()); reverse((pos).begin(), (pos).end()); sort((neg).begin(), (neg).end()); long long ans = 1; for (int i = 0; i < 5; i++) { ans *= a[i]; } for (int m = 0; m <= 4 and m <= neg.size(); m += 2) { int p = 5 - m; if (p > pos.size()) continue; long long pro = 1; for (int i = 0; i < p; i++) pro *= pos[i]; for (int i = 0; i < m; i++) pro *= neg[i]; ans = max(ans, pro); } if (neg.size() >= 5) { reverse((neg).begin(), (neg).end()); long long temp = 1; for (int i = 0; i < 5; i++) { temp *= neg[i]; } ans = max(ans, temp); } cout << ans << endl; } } |
#include <bits/stdc++.h> using namespace std; int n, m; string str[110]; int rev[110]; bool counted[110]; stack<int> st; queue<int> q; int length; bool isRev(string s, string t) { for (int i = 0; i < m; i++) if (s[i] != t[m - i - 1]) return false; return true; } bool same(string s) { char c = s[0]; for (int i = 1; i < m; i++) if (c != s[i]) return false; return true; } bool loneRev(string s) { int i = 0, j = m - 1; while (i <= j) { if (s[i] != s[j]) return false; i++; j--; } return true; } int main() { cin >> n >> m; for (int i = 1; i <= n; i++) cin >> str[i]; for (int i = 1; i <= n; i++) { if (!rev[i]) { for (int j = i + 1; j <= n; j++) { if (isRev(str[i], str[j])) { rev[i] = j; rev[j] = i; break; } } } } for (int i = 1; i <= n; i++) { if (rev[i] && !counted[i]) { counted[i] = true; counted[rev[i]] = true; q.push(i); st.push(rev[i]); length += (2 * m); } } for (int i = 1; i <= n; i++) { if (!counted[i]) { if (same(str[i]) || loneRev(str[i])) { length += m; q.push(i); break; } } } while (st.size()) { int x = st.top(); st.pop(); q.push(x); } cout << length << endl; while (q.size()) { int x = q.front(); q.pop(); cout << str[x]; } } |
// file: Clock_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge LOCKED)
module Clock_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 20.0*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bits of the sampling counters
wire [4:1] COUNT;
// Status and control signals
wire LOCKED;
reg COUNTER_RESET = 0;
wire [4:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
reg [13:0] timeout_counter = 14'b00000000000000;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
$display ("Timing checks are not valid");
COUNTER_RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*19.5)
COUNTER_RESET = 0;
#(PER1*1)
$display ("Timing checks are valid");
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
always@(posedge CLK_IN1) begin
timeout_counter <= timeout_counter + 1'b1;
if (timeout_counter == 14'b10000000000000) begin
if (LOCKED != 1'b1) begin
$display("ERROR : NO LOCK signal");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
end
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
Clock_exdes
dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.LOCKED (LOCKED));
// Freq Check
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, arr[100005], has[100005], t; vector<int> v[100005]; int main() { cin >> n; for (int i = 1; i <= n; i++) { int a; cin >> a; arr[a]++; has[i] = arr[a]; v[has[i]].push_back(a); t = max(t, has[i]); } for (int i = 0; i < 100000; i++) { int p = v[i].size(); if (p != 0) { int tmp = 0; for (int j = 0; j < p; j++) { tmp += v[i][j]; } if (tmp != ((p * (p + 1)) / 2)) { cout << -1 << endl; return 0; } } } cout << t << endl; for (int i = 1; i <= n; i++) cout << has[i] << ; cout << endl; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYGATE4SD2_1_V
`define SKY130_FD_SC_HD__DLYGATE4SD2_1_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog wrapper for dlygate4sd2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dlygate4sd2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlygate4sd2_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlygate4sd2 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlygate4sd2_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlygate4sd2 base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYGATE4SD2_1_V
|
// ============================================================================
// Copyright (c) 2013 by Terasic Technologies Inc.
// ============================================================================
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// ============================================================================
//
// Terasic Technologies Inc
// 9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan
//
//
// web: http://www.terasic.com/
// email:
//
// ============================================================================
//Date: Thu Jul 11 11:26:45 2013
// ============================================================================
`define ENABLE_ADC
`define ENABLE_AUD
`define ENABLE_CLOCK2
`define ENABLE_CLOCK3
`define ENABLE_CLOCK4
`define ENABLE_CLOCK
`define ENABLE_DRAM
`define ENABLE_FAN
`define ENABLE_FPGA
`define ENABLE_GPIO
`define ENABLE_HEX
//`define ENABLE_HPS
`define ENABLE_IRDA
`define ENABLE_KEY
`define ENABLE_LEDR
`define ENABLE_PS2
`define ENABLE_SW
`define ENABLE_TD
`define ENABLE_VGA
module DE1_SOC_golden_top(
/* Enables ADC - 3.3V */
`ifdef ENABLE_ADC
output ADC_CONVST,
output ADC_DIN,
input ADC_DOUT,
output ADC_SCLK,
`endif
/* Enables AUD - 3.3V */
`ifdef ENABLE_AUD
input AUD_ADCDAT,
inout AUD_ADCLRCK,
inout AUD_BCLK,
output AUD_DACDAT,
inout AUD_DACLRCK,
output AUD_XCK,
`endif
/* Enables CLOCK2 */
`ifdef ENABLE_CLOCK2
input CLOCK2_50,
`endif
/* Enables CLOCK3 */
`ifdef ENABLE_CLOCK3
input CLOCK3_50,
`endif
/* Enables CLOCK4 */
`ifdef ENABLE_CLOCK4
input CLOCK4_50,
`endif
/* Enables CLOCK */
`ifdef ENABLE_CLOCK
input CLOCK_50,
`endif
/* Enables DRAM - 3.3V */
`ifdef ENABLE_DRAM
output [12:0] DRAM_ADDR,
output [1:0] DRAM_BA,
output DRAM_CAS_N,
output DRAM_CKE,
output DRAM_CLK,
output DRAM_CS_N,
inout [15:0] DRAM_DQ,
output DRAM_LDQM,
output DRAM_RAS_N,
output DRAM_UDQM,
output DRAM_WE_N,
`endif
/* Enables FAN - 3.3V */
`ifdef ENABLE_FAN
output FAN_CTRL,
`endif
/* Enables FPGA - 3.3V */
`ifdef ENABLE_FPGA
output FPGA_I2C_SCLK,
inout FPGA_I2C_SDAT,
`endif
/* Enables GPIO - 3.3V */
`ifdef ENABLE_GPIO
inout [35:0] GPIO_0,
inout [35:0] GPIO_1,
`endif
/* Enables HEX - 3.3V */
`ifdef ENABLE_HEX
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
`endif
/* Enables HPS */
`ifdef ENABLE_HPS
inout HPS_CONV_USB_N,
output [14:0] HPS_DDR3_ADDR,
output [2:0] HPS_DDR3_BA,
output HPS_DDR3_CAS_N,
output HPS_DDR3_CKE,
output HPS_DDR3_CK_N, //1.5V
output HPS_DDR3_CK_P, //1.5V
output HPS_DDR3_CS_N,
output [3:0] HPS_DDR3_DM,
inout [31:0] HPS_DDR3_DQ,
inout [3:0] HPS_DDR3_DQS_N,
inout [3:0] HPS_DDR3_DQS_P,
output HPS_DDR3_ODT,
output HPS_DDR3_RAS_N,
output HPS_DDR3_RESET_N,
input HPS_DDR3_RZQ,
output HPS_DDR3_WE_N,
output HPS_ENET_GTX_CLK,
inout HPS_ENET_INT_N,
output HPS_ENET_MDC,
inout HPS_ENET_MDIO,
input HPS_ENET_RX_CLK,
input [3:0] HPS_ENET_RX_DATA,
input HPS_ENET_RX_DV,
output [3:0] HPS_ENET_TX_DATA,
output HPS_ENET_TX_EN,
inout [3:0] HPS_FLASH_DATA,
output HPS_FLASH_DCLK,
output HPS_FLASH_NCSO,
inout HPS_GSENSOR_INT,
inout HPS_I2C1_SCLK,
inout HPS_I2C1_SDAT,
inout HPS_I2C2_SCLK,
inout HPS_I2C2_SDAT,
inout HPS_I2C_CONTROL,
inout HPS_KEY,
inout HPS_LED,
inout HPS_LTC_GPIO,
output HPS_SD_CLK,
inout HPS_SD_CMD,
inout [3:0] HPS_SD_DATA,
output HPS_SPIM_CLK,
input HPS_SPIM_MISO,
output HPS_SPIM_MOSI,
inout HPS_SPIM_SS,
input HPS_UART_RX,
output HPS_UART_TX,
input HPS_USB_CLKOUT,
inout [7:0] HPS_USB_DATA,
input HPS_USB_DIR,
input HPS_USB_NXT,
output HPS_USB_STP,
`endif
/* Enables IRDA - 3.3V */
`ifdef ENABLE_IRDA
input IRDA_RXD,
output IRDA_TXD,
`endif
/* Enables KEY - 3.3V */
`ifdef ENABLE_KEY
input [3:0] KEY,
`endif
/* Enables LEDR - 3.3V */
`ifdef ENABLE_LEDR
output [9:0] LEDR,
`endif
/* Enables PS2 - 3.3V */
`ifdef ENABLE_PS2
inout PS2_CLK,
inout PS2_CLK2,
inout PS2_DAT,
inout PS2_DAT2,
`endif
/* Enables SW - 3.3V */
`ifdef ENABLE_SW
input [9:0] SW,
`endif
/* Enables TD - 3.3V */
`ifdef ENABLE_TD
input TD_CLK27,
input [7:0] TD_DATA,
input TD_HS,
output TD_RESET_N,
input TD_VS,
`endif
/* Enables VGA - 3.3V */
`ifdef ENABLE_VGA
output [7:0] VGA_B,
output VGA_BLANK_N,
output VGA_CLK,
output [7:0] VGA_G,
output VGA_HS,
output [7:0] VGA_R,
output VGA_SYNC_N,
output VGA_VS
`endif
);
//=======================================================
// REG/WIRE declarations
//=======================================================
//=======================================================
// Structural coding
//=======================================================
endmodule
|
#include <bits/stdc++.h> using namespace std; struct pii { char C; int fi; int se; }; char A[1000][1000]; void p(int L) { cout << L << endl; for (int i = 1; i <= L; ++i) { for (int j = 1; j <= L; ++j) { cout << A[i][j]; } cout << endl; } } void prin1(pii a, pii b, pii c) { int L = a.se; for (int i = 1; i <= L; ++i) { for (int j = 1; j <= a.fi; ++j) { A[i][j] = a.C; } } for (int i = 1; i <= L; ++i) { for (int j = a.fi + 1; j <= a.fi + b.fi; ++j) { A[i][j] = b.C; } } for (int i = 1; i <= L; ++i) { for (int j = a.fi + b.fi + 1; j <= L; ++j) { A[i][j] = c.C; } } p(L); } void prin2(pii a, pii b, pii c) { int L = a.fi; for (int i = 1; i <= L; ++i) { for (int j = 1; j <= a.se; ++j) { A[j][i] = a.C; } } for (int i = 1; i <= L; ++i) { for (int j = a.se + 1; j <= a.se + b.se; ++j) { A[j][i] = b.C; } } for (int i = 1; i <= L; ++i) { for (int j = a.se + b.se + 1; j <= L; ++j) { A[j][i] = c.C; } } p(L); } void prin3(pii a, pii b, pii c) { int L = c.se; for (int i = 1; i <= a.fi; ++i) { for (int j = 1; j <= a.se; ++j) { A[i][j] = a.C; } } for (int i = 1; i <= b.fi; ++i) { for (int j = a.se + 1; j <= L; ++j) { A[i][j] = b.C; } } for (int i = a.fi + 1; i <= L; ++i) { for (int j = 1; j <= L; ++j) { A[i][j] = c.C; } } p(L); } void prin4(pii a, pii b, pii c) { int L = a.fi; for (int i = 1; i <= b.fi; ++i) { for (int j = a.se + 1; j <= L; ++j) { A[i][j] = b.C; } } for (int i = b.fi + 1; i <= L; ++i) { for (int j = a.se + 1; j <= L; ++j) { A[i][j] = c.C; } } for (int i = 1; i <= L; ++i) { for (int j = 1; j <= a.se; ++j) { A[i][j] = a.C; } } p(L); } bool check(pii a, pii b, pii c) { if (a.fi + b.fi + c.fi == a.se and a.se == b.se and b.se == c.se) { prin1(a, b, c); return 1; } if (a.fi == b.fi and b.fi == c.fi and a.fi == a.se + b.se + c.se) { prin2(a, b, c); return 1; } if (a.fi == b.fi + c.fi and a.fi == a.se + b.se and b.se == c.se) { prin4(a, b, c); return 1; } if (a.se + b.se == c.se and c.se == a.fi + c.fi and a.fi == b.fi) { prin3(a, b, c); return 1; } return 0; } int main() { vector<pii> temp; pii a, b, c; cin >> a.fi >> a.se; cin >> b.fi >> b.se; cin >> c.fi >> c.se; a.C = A ; b.C = B ; c.C = C ; vector<int> g; g.push_back(0); g.push_back(1); g.push_back(2); for (int mask = 0; mask < 8; ++mask) { if (mask & (1 << 0)) swap(a.fi, a.se); if (mask & (1 << 1)) swap(b.fi, b.se); if (mask & (1 << 2)) swap(c.fi, c.se); temp.clear(); sort(g.begin(), g.end()); temp.push_back(a); temp.push_back(b); temp.push_back(c); do { if (check(temp[g[0]], temp[g[1]], temp[g[2]])) return 0; } while (next_permutation(g.begin(), g.end())); if (mask & (1 << 0)) swap(a.fi, a.se); if (mask & (1 << 1)) swap(b.fi, b.se); if (mask & (1 << 2)) swap(c.fi, c.se); } cout << -1; } |
#include <bits/stdc++.h> const int inf = int(1e9); const int mod = inf + 7; const double PI = acos(-1.0); using namespace std; const int N = 1e5 + 155; template <typename T> inline void read(T& x) { x = 0; int f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } x *= f; } string toForm(char c, bool ok) { string ans = ; ans += char(60); if (!ok) ans += char(47); ans += (c); ans += char(62); return ans; } void solve() { string s; cin >> s; int cnt = 0; for (int i = 1; i < s.size(); i++) { if (s[i] != < && s[i] != > && s[i] != / ) { if (s[i - 1] != / ) { for (int i = 0; i < cnt; ++i) cout << ; cout << toForm(s[i], true); cout << n ; cnt++; } else { for (int i = 0; i < cnt - 1; ++i) cout << ; cout << toForm(s[i], false); cout << n ; cnt--; } } } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t = 1; while (t--) solve(); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Case Western Reserve University
// Engineer: Matt McConnell
//
// Create Date: 00:48:00 01/25/2017
// Project Name: EECS301 Digital Design
// Design Name: Lab #3 Project
// Module Name: CDC_Input_Synchronizer
// Target Devices: Altera Cyclone V
// Tool versions: Quartus v17.0
// Description: Clock Domain Crossing Synchronizer
//
// Dependencies:
//
//////////////////////////////////////////////////////////////////////////////////
module CDC_Input_Synchronizer
#(
parameter SYNC_REG_LEN = 2
)
(
// Input Signal
input ASYNC_IN,
// Output Signal
output SYNC_OUT,
// System Signals
input CLK
);
//
// Set a SDC False Path for the async input register so Quartus
// properly reconizes the synchronizer chain and calculates MTBF.
//
(* altera_attribute = {"-name SDC_STATEMENT \"set_false_path -to [get_registers {*|CDC_Input_Synchronizer:*|async_reg}]\""} *)
//
// Asynchronous Input Signal Register
//
reg async_reg;
always @(posedge CLK)
begin
async_reg <= ASYNC_IN;
end
//
// Synchronous Registers
//
genvar i;
generate
begin
if (SYNC_REG_LEN < 1)
begin
assign SYNC_OUT = async_reg;
end
else
begin
reg [SYNC_REG_LEN-1:0] sync_reg;
assign SYNC_OUT = sync_reg[SYNC_REG_LEN-1];
for (i=0; i < SYNC_REG_LEN; i=i+1)
begin : sync_reg_gen
if (i == 0)
begin
always @(posedge CLK)
begin
sync_reg[i] <= async_reg;
end
end
else
begin
always @(posedge CLK)
begin
sync_reg[i] <= sync_reg[i-1];
end
end
end
end
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int ts; cin >> ts; while (ts--) { int n; cin >> n; vector<int> v(n); vector<int> pos[2]; for (int i = 0; i < n; i++) { cin >> v[i]; pos[v[i]].push_back(i); } int x = 0; if (pos[0].size() >= n / 2) { x = 0; } else x = 1; if (x) { if (pos[x].size() % 2 != 0) { int k = pos[x].size() - 1; if (k < n / 2) { vector<int> vv; for (int i = 0; i < k; i++) vv.push_back(pos[x][i]); int f = lower_bound(pos[0].begin(), pos[0].end(), vv[vv.size() - 1]) - pos[0].begin(); int d = lower_bound(pos[0].begin(), pos[0].end(), vv[0]) - pos[0].begin(); if (pos[0].size() - f >= 2) { vv.push_back(pos[0][f]); vv.push_back(pos[0][f + 1]); cout << vv.size() << n ; for (int i = 0; i < vv.size(); i++) cout << v[vv[i]] << ; cout << endl; } else if (d >= 1) { vv.push_back(pos[0][d]); vv.push_back(pos[0][d - 1]); cout << vv.size() << n ; for (int i = vv.size() - 1; i >= 0; i--) { cout << v[vv[i]] << ; } cout << endl; } } else { cout << k << n ; for (int i = 0; i < k; i++) { cout << 1 << ; } cout << n ; } } else { cout << pos[x].size() << n ; for (int i = 0; i < pos[x].size(); i++) cout << 1 ; cout << endl; } } else { cout << pos[x].size() << n ; for (int i = 0; i < pos[x].size(); i++) cout << 0 ; cout << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { std::ios_base::sync_with_stdio(false); int n; long long l, first, second; cin >> n >> l >> first >> second; vector<long long> a(n); map<long long, bool> flag; for (int i = 0; i < int(n); i++) { cin >> a[i]; flag[a[i]] = true; } bool fx = false, fy = false; for (int i = n - 1; i >= 0; i--) { if (flag.count(a[i] - first)) fx = true; if (flag.count(a[i] - second)) fy = true; } if (!fx && !fy) { long long diff = second - first; for (int i = 0; i < n; i++) { if (flag.count(a[i] - diff)) { if (a[i] + first <= l) { cout << 1 << n ; cout << a[i] + first; return 0; } if (a[i] - second >= 0) { cout << 1 << n ; cout << a[i] - second; return 0; } } } long long add = first + second; for (int i = 0; i < n; i++) { if (flag.count(a[i] + add)) { if (a[i] + first <= l) { cout << 1 << n ; cout << a[i] + first; return 0; } } } cout << 2 << n ; cout << first << << second; } else if (!fx) { cout << 1 << n ; cout << first; } else if (!fy) { cout << 1 << n ; cout << second; } else cout << 0 n ; return 0; } |
`ifndef XILINX
module MULT18X18S
// The module was copied from the Ettus UHD code.
(output reg signed [35:0] P,
input signed [17:0] A,
input signed [17:0] B,
input C, // Clock
input CE, // Clock Enable
input R // Synchronous Reset
);
always @(posedge C)
if(R)
P <= 36'sd0;
else if(CE)
begin
P <= A * B;
end
endmodule
`endif
module multiply
#(
parameter WDTH = 0
)
(
input wire clk,
input wire rst_n,
input wire signed [WDTH-1:0] x,
input wire signed [WDTH-1:0] y,
output wire signed [WDTH-1:0] z
);
reg ce;
initial
ce <= 1'b1;
wire signed [17:0] xb;
wire signed [17:0] yb;
assign xb = x;
assign yb = y;
wire signed [35:0] xy;
MULT18X18S multer (.P(xy), .A(xb), .B(yb), .C(clk), .CE(ce), .R(~rst_n));
assign z = xy >>> (WDTH-1);
always @ (posedge clk)
begin
//xy <= xb * yb;
//z <= xy >>> (WDTH-2);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int num; cin >> num; for (int i = 1; i <= 2 * sqrt(num); i++) { int x = (i * (i + 1)) / 2; int tmp = num - x; int st = 1, en = 2 * sqrt(num); while (st <= en) { int mid = st + (en - st) / 2; int y = (mid * (mid + 1)) / 2; if (y == tmp) { cout << YES << endl; return 0; } else if (y < tmp) { st = mid + 1; } else { en = mid - 1; } } } cout << NO << endl; } |
//
// Copyright (c) 1999 Peter Monta ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
module main;
wire [3:0] a,b,c;
assign a=4'd5, b=4'd8, c=4'd12;
initial begin
#1;
if (a===4'd5 && b===4'd8 && c==4'd12)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21O_BEHAVIORAL_V
`define SKY130_FD_SC_LP__A21O_BEHAVIORAL_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__a21o (
X ,
A1,
A2,
B1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X, and0_out, B1 );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21O_BEHAVIORAL_V |
/*****************************************************************************
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2012, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: mig_interface_model
-- File: mig_interface_model.v
-- Author: Fredrik Ringhage - Aeroflex Gaisler AB
--
-- This is a interface model for Xilinx Virtex-7 MIG used on eval board
-- VC707 and KC705.
--
-------------------------------------------------------------------------------
*****************************************************************************/
`timescale 1ps/1ps
module mig_interface_model
(
// user interface signals
input [27:0] app_addr,
input [2:0] app_cmd,
input app_en,
input [511:0] app_wdf_data,
input app_wdf_end,
input [63:0] app_wdf_mask,
input app_wdf_wren,
output wire [511:0] app_rd_data,
output wire app_rd_data_end,
output wire app_rd_data_valid,
output wire app_rdy,
output wire app_wdf_rdy,
output reg ui_clk,
output reg ui_clk_sync_rst,
output reg init_calib_complete,
input sys_rst
);
parameter AddressSize = 28 - 12;
parameter WordSize = 512;
parameter MEM_SIZE = (1<<AddressSize);
reg app_rd_data_end_r;
reg app_rd_data_valid_r;
reg app_rdy_r;
reg app_wdf_rdy_r;
reg app_en_r;
reg app_wdf_wren_r;
reg app_wdf_end_r;
reg [27:0] app_addr_r;
reg [27:0] app_addr_r1;
reg [27:0] app_addr_r2;
reg [511:0] mask;
reg [WordSize-1:0] Mem [0:MEM_SIZE];
integer k;
wire [511:0] app_rd_data_hi_data;
wire [511:0] app_rd_data_hi;
wire [511:0] app_rd_data_lo;
wire test;
assign #100 app_rd_data_end = app_rd_data_end_r;
assign #100 app_rdy = app_rdy_r;
assign #100 app_wdf_rdy = app_wdf_rdy_r;
assign app_rd_data_valid = app_rd_data_valid_r;
assign #100 app_rd_data = Mem[app_addr_r >> 3];
// Clear memory
initial
begin
for (k = 0; k < MEM_SIZE ; k = k + 1)
begin
Mem[k] = 512'd0;
end
end
initial
begin
app_rd_data_valid_r = 1'b0;
app_rd_data_end_r = 1'b0;
app_rdy_r = 1'b1;
app_wdf_rdy_r = 1'b1;
init_calib_complete = 1'b0;
ui_clk_sync_rst = 1'b0;
ui_clk = 1'b0;
end
// Generate clocks
always
begin
forever begin
#5000;
ui_clk = ~ui_clk;
end
end
// Release reset and calibration
initial
begin
#10000;
$display("Reset release of simulation time is %d",$time);
@(posedge ui_clk) ui_clk_sync_rst = 1'b1;
#1000;
$display("Calibration release of simulation time is %d",$time);
@(posedge ui_clk) init_calib_complete = 1'b1;
end
// Write Process
always@(posedge app_wdf_wren)
begin
#100;
for (k = 0; k < 511 ; k = k + 1)
begin
mask[k] = ~ app_wdf_mask[k >> 3];
end
Mem[app_addr >> 3] = (app_wdf_data & mask) | (Mem[app_addr >> 3] & (~ mask) );
#10000;
if (app_wdf_wren) begin
#100;
for (k = 0; k < 512 ; k = k + 1)
begin
mask[k] = ~ app_wdf_mask[k >> 3];
end
Mem[app_addr >> 3] = (app_wdf_data & mask) | (Mem[app_addr >> 3] & (~ mask) );
end
end
// Read Process
always@(posedge app_en)
begin
#100;
if (app_cmd == 3'd1) begin
app_addr_r1 = app_addr;
#10000;
app_addr_r2 = app_addr;
#40000;
app_addr_r = app_addr_r1;
#100;
app_rd_data_valid_r = 1'b1;
#10000;
app_addr_r = app_addr_r2;
#10000;
app_rd_data_valid_r = 1'b0;
#10000;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISOLATCH_BEHAVIORAL_V
`define SKY130_FD_SC_LP__ISOLATCH_BEHAVIORAL_V
/**
* isolatch: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_isolatch_pp_pkg_sn/sky130_fd_sc_lp__udp_isolatch_pp_pkg_sn.v"
`celldefine
module sky130_fd_sc_lp__isolatch (
Q ,
D ,
SLEEP_B
);
// Module ports
output Q ;
input D ;
input SLEEP_B;
// Module supplies
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire SLEEP_B_delayed;
wire D_delayed ;
reg notifier ;
// Name Output Other arguments
sky130_fd_sc_lp__udp_isolatch_pp$PKG$sN isolatch_pp0 (buf_Q , D_delayed, SLEEP_B_delayed, notifier, KAPWR, VGND, VPWR);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISOLATCH_BEHAVIORAL_V |
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module fmlbrg_datamem #(
parameter depth = 11
) (
input sys_clk,
/* Primary port (read-write) */
input [depth-1:0] a,
input [7:0] we,
input [63:0] di,
output [63:0] do,
/* Secondary port (read-only) */
input [depth-1:0] a2,
output [63:0] do2
);
reg [7:0] ram0[0:(1 << depth)-1];
reg [7:0] ram1[0:(1 << depth)-1];
reg [7:0] ram2[0:(1 << depth)-1];
reg [7:0] ram3[0:(1 << depth)-1];
reg [7:0] ram4[0:(1 << depth)-1];
reg [7:0] ram5[0:(1 << depth)-1];
reg [7:0] ram6[0:(1 << depth)-1];
reg [7:0] ram7[0:(1 << depth)-1];
wire [7:0] ram0di;
wire [7:0] ram1di;
wire [7:0] ram2di;
wire [7:0] ram3di;
wire [7:0] ram4di;
wire [7:0] ram5di;
wire [7:0] ram6di;
wire [7:0] ram7di;
wire [7:0] ram0do;
wire [7:0] ram1do;
wire [7:0] ram2do;
wire [7:0] ram3do;
wire [7:0] ram4do;
wire [7:0] ram5do;
wire [7:0] ram6do;
wire [7:0] ram7do;
wire [7:0] ram0do2;
wire [7:0] ram1do2;
wire [7:0] ram2do2;
wire [7:0] ram3do2;
wire [7:0] ram4do2;
wire [7:0] ram5do2;
wire [7:0] ram6do2;
wire [7:0] ram7do2;
reg [depth-1:0] a_r;
reg [depth-1:0] a2_r;
always @(posedge sys_clk) begin
a_r <= a;
a2_r <= a2;
end
always @(posedge sys_clk) begin
if(we[0])
ram0[a] <= ram0di;
end
assign ram0do = ram0[a_r];
assign ram0do2 = ram0[a2_r];
always @(posedge sys_clk) begin
if(we[1])
ram1[a] <= ram1di;
end
assign ram1do = ram1[a_r];
assign ram1do2 = ram1[a2_r];
always @(posedge sys_clk) begin
if(we[2])
ram2[a] <= ram2di;
end
assign ram2do = ram2[a_r];
assign ram2do2 = ram2[a2_r];
always @(posedge sys_clk) begin
if(we[3])
ram3[a] <= ram3di;
end
assign ram3do = ram3[a_r];
assign ram3do2 = ram3[a2_r];
always @(posedge sys_clk) begin
if(we[4])
ram4[a] <= ram4di;
end
assign ram4do = ram4[a_r];
assign ram4do2 = ram4[a2_r];
always @(posedge sys_clk) begin
if(we[5])
ram5[a] <= ram5di;
end
assign ram5do = ram5[a_r];
assign ram5do2 = ram5[a2_r];
always @(posedge sys_clk) begin
if(we[6])
ram6[a] <= ram6di;
end
assign ram6do = ram6[a_r];
assign ram6do2 = ram6[a2_r];
always @(posedge sys_clk) begin
if(we[7])
ram7[a] <= ram7di;
end
assign ram7do = ram7[a_r];
assign ram7do2 = ram7[a2_r];
assign ram0di = di[7:0];
assign ram1di = di[15:8];
assign ram2di = di[23:16];
assign ram3di = di[31:24];
assign ram4di = di[39:32];
assign ram5di = di[47:40];
assign ram6di = di[55:48];
assign ram7di = di[63:56];
assign do = {ram7do, ram6do, ram5do, ram4do, ram3do, ram2do, ram1do, ram0do};
assign do2 = {ram7do2, ram6do2, ram5do2, ram4do2, ram3do2, ram2do2, ram1do2, ram0do2};
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long s, n, in; cin >> n; if (n == 1) cout << 1 << endl << 1 ; else { for (int i = 1; i <= n; i++) { s = i * (i + 1); s = s / 2; if (n < s) { in = i - 2; break; } } cout << in + 1 << endl; s = 0; for (int i = 1; i <= in; i++) { cout << i << ; s += i; } cout << n - s; } return 0; } |
module simple_alu(clk, reset_n, opcode_valid, opcode, data, done, result, overflow);
parameter DATA_WIDTH = 8;
input clk;
input reset_n;
input opcode_valid;
input opcode;
input [DATA_WIDTH-1:0] data;
output done;
output [DATA_WIDTH-1:0] result;
output overflow;
reg overflow;
wire overflow_buf;
reg done;
reg [DATA_WIDTH-1:0] result;
parameter ON = 1'b1;
parameter OFF = 1'b0;
parameter
RESET = 4'b0000,
IDLE = 4'b0001,
DATA_A = 4'b0010,
DATA_B = 4'b0011,
ADD = 4'b0100,
SUB = 4'b0101,
PAR = 4'b0110,
COMP = 4'b0111,
DONE = 4'b1000;
//parameter
// ADD = 2'b00,
// SUB = 2'b01,
// PAR = 2'b10,
// COMP = 2'b11;
reg [3:0] State, NextState;
reg [DATA_WIDTH-1:0] A_Data, B_Data;
reg [1:0] opcode_def;
reg store_a_def, store_b_def;
wire [DATA_WIDTH-1:0] result_def;
reg [1:0] opcode_buf;
reg store_a, store_b;
reg start;
wire alu_done;
reg first;
always @(posedge clk or reset_n)
begin
if(!reset_n)
begin
State = RESET;
end
else
begin
State = NextState;
end
end
always @(State or opcode_valid or reset_n or alu_done)
begin
case(State)
RESET:
begin
if(reset_n)
begin
NextState = IDLE;
end
else
begin
NextState = RESET;
end
end
IDLE:
begin
if(opcode_valid)
begin
NextState = DATA_A;
end
else
begin
NextState = IDLE;
end
end
DATA_A:
begin
if(opcode_valid)
begin
NextState = DATA_B;
opcode_buf[0] = opcode;
end
else
begin
NextState = IDLE;
end
end
DATA_B:
begin
opcode_buf[1] = opcode;
if(opcode_valid)
begin
case(opcode_buf)
2'b00:
begin
NextState = ADD;
end
2'b01:
begin
NextState = SUB;
end
2'b10:
begin
NextState = PAR;
end
2'b11:
begin
NextState = COMP;
end
endcase
end
else
begin
NextState = IDLE;
end
end
ADD:
begin
if(alu_done)
begin
NextState = DONE;
end
else
begin
NextState = ADD;
end
end
SUB:
begin
if(alu_done)
begin
NextState = DONE;
end
else
begin
NextState = SUB;
end
end
PAR:
begin
if(alu_done)
begin
NextState = DONE;
end
else
begin
NextState = PAR;
end
end
COMP:
begin
if(alu_done)
begin
NextState = DONE;
end
else
begin
NextState = COMP;
end
end
DONE:
begin
NextState = IDLE;
end
endcase
end
always @(State)
begin
case(State)
RESET:
begin
store_a_def = OFF;
store_b_def = OFF;
opcode_def = ADD;
start = OFF;
result = 0;
done = OFF;
overflow = OFF;
end
IDLE:
begin
store_a_def = OFF;
store_b_def = OFF;
opcode_def = ADD;
start = OFF;
result = 0;
done = OFF;
overflow = OFF;
end
DATA_A:
begin
store_a_def = ON;
store_b_def = OFF;
start = OFF;
result = 0;
done = OFF;
overflow = OFF;
end
DATA_B:
begin
store_a_def = OFF;
store_b_def = ON;
start = OFF;
result = 0;
done = OFF;
overflow = OFF;
end
ADD:
begin
store_a_def = OFF;
store_b_def = OFF;
opcode_def = ADD;
start = 1'b1;
result = 0;
done = OFF;
overflow = OFF;
end
SUB:
begin
store_a_def = OFF;
store_b_def = OFF;
opcode_def = SUB;
start = ON;
result = 0;
done = OFF;
overflow = OFF;
end
PAR:
begin
store_a_def = OFF;
store_b_def = OFF;
opcode_def = PAR;
start = ON;
result = 0;
done = OFF;
overflow = OFF;
end
COMP:
begin
store_a_def = OFF;
store_b_def = OFF;
opcode_def = COMP;
start = ON;
result = 0;
done = OFF;
overflow = OFF;
end
DONE:
begin
store_a_def = OFF;
store_b_def = OFF;
opcode_def = 2'b00;
start = OFF;
result = result_def;
done = ON;
overflow = overflow_buf;
end
endcase
end
alu_datapath #(DATA_WIDTH) alu_datapath (
.clk(clk),
.alu_data(data),
.opcode_value(opcode_def),
.store_a(store_a_def),
.store_b(store_b_def),
.start(start),
.alu_done(alu_done),
.result(result_def),
.overflow_def(overflow_buf)
);
endmodule
|
// +----------------------------------------------------------------------------
// GNU General Public License
// -----------------------------------------------------------------------------
// This file is part of uDLX (micro-DeLuX) soft IP-core.
//
// uDLX is free soft IP-core: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// uDLX soft core is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with uDLX. If not, see <http://www.gnu.org/licenses/>.
// +----------------------------------------------------------------------------
// PROJECT: uDLX core Processor
// ------------------------------------------------------------------------------
// FILE NAME : mem_wb_reg.v
// KEYWORDS : dlx, memory access, sdram, data memory
// -----------------------------------------------------------------------------
// PURPOSE: Top level module of Memory Access stage
// -----------------------------------------------------------------------------
module mem_wb_reg
#(
parameter DATA_WIDTH = 32,
parameter INSTRUCTION_WIDTH = 32,
parameter REG_ADDR_WIDTH = 5
)
(
input clk,
input rst_n,
input en,
input write_back_mux_sel_in,
input [DATA_WIDTH-1:0] alu_data_in,
input [DATA_WIDTH-1:0] hi_data_in,
// input reg_wr_en_in,
// input [REG_ADDR_WIDTH-1:0] reg_wr_addr_in,
input [REG_ADDR_WIDTH-1:0] reg_a_wr_addr_in,
input [REG_ADDR_WIDTH-1:0] reg_b_wr_addr_in,
input reg_a_wr_en_in,
input reg_b_wr_en_in,
input [INSTRUCTION_WIDTH-1:0] instruction_in,
output reg write_back_mux_sel_out,
output reg [DATA_WIDTH-1:0] alu_data_out,
output reg [DATA_WIDTH-1:0] hi_data_out,
// output reg reg_wr_en_out,
// output reg [REG_ADDR_WIDTH-1:0] reg_wr_addr_out,
output reg [REG_ADDR_WIDTH-1:0] reg_a_wr_addr_out,
output reg [REG_ADDR_WIDTH-1:0] reg_b_wr_addr_out,
output reg reg_a_wr_en_out,
output reg reg_b_wr_en_out,
output reg [INSTRUCTION_WIDTH-1:0] instruction_out
);
always@(posedge clk or negedge rst_n) begin
if(~rst_n) begin
write_back_mux_sel_out <= 0;
alu_data_out <= 0;
hi_data_out <= 0;
// reg_wr_en_out <= 0;
// reg_wr_addr_out <= 0;
reg_a_wr_addr_out <= 0;
reg_b_wr_addr_out <= 0;
reg_a_wr_en_out <= 0;
reg_b_wr_en_out <= 0;
instruction_out <= 0;
end
else if(en) begin
write_back_mux_sel_out <= write_back_mux_sel_in;
alu_data_out <= alu_data_in;
hi_data_out <= hi_data_in;
// reg_wr_en_out <= reg_wr_en_in;
// reg_wr_addr_out <= reg_wr_addr_in;
reg_a_wr_addr_out <= reg_a_wr_addr_in;
reg_b_wr_addr_out <= reg_b_wr_addr_in;
reg_a_wr_en_out <= reg_a_wr_en_in;
reg_b_wr_en_out <= reg_b_wr_en_in;
instruction_out <= instruction_in;
end
end
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: user.org:user:fmrv32im_axilm:1.0
// IP Revision: 4
(* X_CORE_INFO = "fmrv32im_axilm,Vivado 2017.2" *)
(* CHECK_LICENSE_TYPE = "fmrv32im_artya7_fmrv32im_axilm_0_0,fmrv32im_axilm,{}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module fmrv32im_artya7_fmrv32im_axilm_0_0 (
RST_N,
CLK,
M_AXI_AWADDR,
M_AXI_AWCACHE,
M_AXI_AWPROT,
M_AXI_AWVALID,
M_AXI_AWREADY,
M_AXI_WDATA,
M_AXI_WSTRB,
M_AXI_WVALID,
M_AXI_WREADY,
M_AXI_BVALID,
M_AXI_BREADY,
M_AXI_BRESP,
M_AXI_ARADDR,
M_AXI_ARCACHE,
M_AXI_ARPROT,
M_AXI_ARVALID,
M_AXI_ARREADY,
M_AXI_RDATA,
M_AXI_RRESP,
M_AXI_RVALID,
M_AXI_RREADY,
BUS_WAIT,
BUS_ENA,
BUS_WSTB,
BUS_ADDR,
BUS_WDATA,
BUS_RDATA
);
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST_N RST" *)
input wire RST_N;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire CLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] M_AXI_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] M_AXI_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] M_AXI_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire M_AXI_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire M_AXI_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] M_AXI_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] M_AXI_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire M_AXI_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire M_AXI_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire M_AXI_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire M_AXI_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] M_AXI_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] M_AXI_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] M_AXI_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] M_AXI_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire M_AXI_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire M_AXI_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] M_AXI_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] M_AXI_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire M_AXI_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire M_AXI_RREADY;
(* X_INTERFACE_INFO = "user.org:user:PERIPHERAL_BUS:1.0 PERIPHERAL_BUS BUS_WAIT" *)
output wire BUS_WAIT;
(* X_INTERFACE_INFO = "user.org:user:PERIPHERAL_BUS:1.0 PERIPHERAL_BUS BUS_ENA" *)
input wire BUS_ENA;
(* X_INTERFACE_INFO = "user.org:user:PERIPHERAL_BUS:1.0 PERIPHERAL_BUS BUS_WSTB" *)
input wire [3 : 0] BUS_WSTB;
(* X_INTERFACE_INFO = "user.org:user:PERIPHERAL_BUS:1.0 PERIPHERAL_BUS BUS_ADDR" *)
input wire [31 : 0] BUS_ADDR;
(* X_INTERFACE_INFO = "user.org:user:PERIPHERAL_BUS:1.0 PERIPHERAL_BUS BUS_WDATA" *)
input wire [31 : 0] BUS_WDATA;
(* X_INTERFACE_INFO = "user.org:user:PERIPHERAL_BUS:1.0 PERIPHERAL_BUS BUS_RDATA" *)
output wire [31 : 0] BUS_RDATA;
fmrv32im_axilm inst (
.RST_N(RST_N),
.CLK(CLK),
.M_AXI_AWADDR(M_AXI_AWADDR),
.M_AXI_AWCACHE(M_AXI_AWCACHE),
.M_AXI_AWPROT(M_AXI_AWPROT),
.M_AXI_AWVALID(M_AXI_AWVALID),
.M_AXI_AWREADY(M_AXI_AWREADY),
.M_AXI_WDATA(M_AXI_WDATA),
.M_AXI_WSTRB(M_AXI_WSTRB),
.M_AXI_WVALID(M_AXI_WVALID),
.M_AXI_WREADY(M_AXI_WREADY),
.M_AXI_BVALID(M_AXI_BVALID),
.M_AXI_BREADY(M_AXI_BREADY),
.M_AXI_BRESP(M_AXI_BRESP),
.M_AXI_ARADDR(M_AXI_ARADDR),
.M_AXI_ARCACHE(M_AXI_ARCACHE),
.M_AXI_ARPROT(M_AXI_ARPROT),
.M_AXI_ARVALID(M_AXI_ARVALID),
.M_AXI_ARREADY(M_AXI_ARREADY),
.M_AXI_RDATA(M_AXI_RDATA),
.M_AXI_RRESP(M_AXI_RRESP),
.M_AXI_RVALID(M_AXI_RVALID),
.M_AXI_RREADY(M_AXI_RREADY),
.BUS_WAIT(BUS_WAIT),
.BUS_ENA(BUS_ENA),
.BUS_WSTB(BUS_WSTB),
.BUS_ADDR(BUS_ADDR),
.BUS_WDATA(BUS_WDATA),
.BUS_RDATA(BUS_RDATA)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[1000005]; int main() { string s; int p = 1, q = 1, ans = 0, ansCount = 1; a[0] = -1; cin >> s; for (int i = 0, sz = s.length(); i < sz; i++) { if (s[i] == ( ) { a[p] = i; p++; } else { p--; if (p == 0) { a[0] = i; p = 1, q = 1; } else { int dis = i - a[p - 1]; if (dis > ans) { ans = dis, ansCount = 1; } else if (dis == ans) ansCount++; } } } cout << ans << << ansCount; return 0; } |
Subsets and Splits