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#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); int n; cin >> n; int a[2 * n], ans = 0; for (int i = 0; i <= 2 * n - 1; i++) cin >> a[i]; for (int i = 0; i < 2 * n; i += 2) { int j = i + 1; while (a[j] != a[i]) j++; ans += j - i - 1; for (int k = j; k >= i + 2; k--) a[k] = a[k - 1]; } cout << ans; return 0; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:10:50 05/23/2014
// Design Name: CPU_top
// Module Name: E://pipelinecpu/test.v
// Project Name: pipelinecpu
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: CPU_top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test;
// Inputs
reg clock;
reg memclock;
reg resetn;
// Outputs
wire [31:0] pc;
wire [31:0] inst;
wire [31:0] ealu;
wire [31:0] malu;
wire [31:0] walu;
// Instantiate the Unit Under Test (UUT)
CPU_top uut (
.clock(clock),
.memclock(memclock),
.resetn(resetn),
.pc(pc),
.inst(inst),
.ealu(ealu),
.malu(malu),
.walu(walu)
);
initial begin
// Initialize Inputs
resetn = 1;
clock=0;
memclock=0;
// Wait 100 ns for global reset to finish
#11; resetn= 0;
// Add stimulus here
end
initial forever begin
#1; memclock=~memclock;
#1;memclock=~memclock; clock=~clock;
end
endmodule
|
// part of NeoGS project (c) 2007-2008 NedoPC
//
// memmap is memory mapper for NGS. Physical memory divided in 16kb pages.
// At (a15=0,a14=0) there is always zero page of MEM, at (a15=0,a14=1) there is
// always third page of RAM, at (a15=1,a14=0) there is page of MEM determined by
// mode_pg0 input bus, at (a15=1,a14=1) - page of MEM determined by mode_pg1 input.
// When mode_norom=0, MEM is ROM, otherwise MEM is RAM.
// When mode_ramro=1, zero and first pages of RAM are read-only.
// Memory addressed by mema14..mema18 (total 512kb) and then by either
// romcs_n (only 512kb of ROM) or ram0cs_n..ram3cs_n (2Mb of RAM).
// Memory decoding is static - it depends on only a14,a15 and mode_pg0,1 inputs.
// memoe_n and memwe_n generated from only mreq_n, rd_n and wr_n with the
// exception of read-only page of RAM (no memwe_n). ROM is always read/write (flash).
module memmap(
a15,a14, // Z80 address signals
mreq_n, // Z80 bus control signals
rd_n, //
wr_n, //
mema14,mema15, // memory addresses
mema16,mema17, //
mema18,mema21, //
ram0cs_n, // four RAM /CS'es
ram1cs_n, //
ram2cs_n, //
ram3cs_n, // (total 512kb * 4 = 2Mb)
romcs_n, // ROM (flash) /CS
memoe_n, // memory /OE and /WE
memwe_n, //
mode_ramro, // 1 - zero page (32k) of ram is R/O
mode_norom, // 0 - ROM instead of RAM at everything except $4000-$7FFF
mode_pg0, // page at $0000-$3FFF
mode_pg1, // page at $4000-$7FFF
mode_pg2, // page at $8000-$BFFF
mode_pg3 // page at $C000-$FFFF
);
// inputs and outputs
input a15,a14;
input mreq_n,rd_n,wr_n;
output reg mema14, mema15, mema16, mema17, mema18, mema21;
output reg ram0cs_n,ram1cs_n,ram2cs_n,ram3cs_n;
output reg romcs_n;
output reg memoe_n,memwe_n;
input mode_ramro,mode_norom;
input [7:0] mode_pg0,mode_pg1,mode_pg2,mode_pg3;
// internal vars and regs
reg [7:0] high_addr;
// addresses mapping
always @*
begin
case( {a15,a14} )
2'b00: // $0000-$3FFF
high_addr <= mode_pg0;
2'b01: // $4000-$7FFF
high_addr <= mode_pg1;
2'b10: // $8000-$BFFF
high_addr <= mode_pg2;
2'b11: // $C000-$FFFF
high_addr <= mode_pg3;
endcase
end
// memory addresses
always @*
begin
{ mema21, mema18, mema17, mema16, mema15, mema14 } <= { high_addr[7], high_addr[4:0] };
end
// memory chip selects
always @*
begin
if( (mode_norom==1'b0) && ( {a15,a14}!=2'b01 ) ) // ROM selected
begin
romcs_n <= 1'b0;
ram0cs_n <= 1'b1;
ram1cs_n <= 1'b1;
ram2cs_n <= 1'b1;
ram3cs_n <= 1'b1;
end
else // RAM
begin
romcs_n <= 1'b1;
ram0cs_n <= ( high_addr[6:5]==2'b00 ) ? 1'b0 : 1'b1;
ram1cs_n <= ( high_addr[6:5]==2'b01 ) ? 1'b0 : 1'b1;
ram2cs_n <= ( high_addr[6:5]==2'b10 ) ? 1'b0 : 1'b1;
ram3cs_n <= ( high_addr[6:5]==2'b11 ) ? 1'b0 : 1'b1;
end
end
// memory /OE and /WE
always @*
begin
memoe_n <= mreq_n | rd_n;
if( (high_addr[6:1] == 6'd0) && (mode_ramro==1'b1) && (mode_norom==1'b1) ) // R/O
memwe_n <= 1'b1;
else // no R/O
memwe_n <= mreq_n | wr_n;
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_clk_cl_sctag_cmp.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_clk_cl_sctag_cmp (/*AUTOARG*/
// Outputs
dbginit_l, cluster_grst_l, rclk, so,
// Inputs
gclk, cluster_cken, arst_l, grst_l, adbginit_l, gdbginit_l, si,
se
);
input gclk;
input cluster_cken;
input arst_l;
input grst_l;
input adbginit_l;
input gdbginit_l;
output dbginit_l;
output cluster_grst_l;
output rclk;
input si;
input se;
output so;
cluster_header I0 (/*AUTOINST*/
// Outputs
.dbginit_l (dbginit_l),
.cluster_grst_l (cluster_grst_l),
.rclk (rclk),
.so (so),
// Inputs
.gclk (gclk),
.cluster_cken (cluster_cken),
.arst_l (arst_l),
.grst_l (grst_l),
.adbginit_l (adbginit_l),
.gdbginit_l (gdbginit_l),
.si (si),
.se (se));
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int w; w = 1; while (w--) { int n, maxi = -1, b = 0; vector<int> s, t[10]; bool f1 = true, f = false; cin >> n; while (n > 0) { int x = n % 10; s.push_back(x); maxi = max(maxi, x); n /= 10; } reverse(s.begin(), s.end()); while (f1) { f1 = false; f = false; for (int i = 0; i < s.size(); i++) { int y = s[i]; if (y > 0) { f1 = true; f = true; t[b].push_back(1); y--; s[i] = y; } else { if (f) t[b].push_back(0); } } b++; } string ans[maxi]; cout << maxi << endl; for (int i = 0; i < maxi; i++) { for (int j = 0; j < t[i].size(); j++) { char c = (char)(t[i][j] + 0 ); ans[i].push_back(c); } } for (int i = 0; i < maxi; i++) cout << ans[i] << ; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A22OI_SYMBOL_V
`define SKY130_FD_SC_HD__A22OI_SYMBOL_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a22oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A22OI_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2HV_HL_PP_BLACKBOX_V
`define SKY130_FD_SC_HVL__LSBUFHV2HV_HL_PP_BLACKBOX_V
/**
* lsbufhv2hv_hl: Level shifting buffer, High Voltage to High Voltage,
* Higher Voltage to Lower Voltage.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__lsbufhv2hv_hl (
X ,
A ,
VPWR ,
VGND ,
LOWHVPWR,
VPB ,
VNB
);
output X ;
input A ;
input VPWR ;
input VGND ;
input LOWHVPWR;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2HV_HL_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int Max = 2e5 + 10; int n, k; int v, u; vector<int> stl[Max]; struct node { long long cou; long long huo; node() { cou = huo = 0; } } point[Max]; int vis[Max]; long long tot = 0; void dfs(int idex, int cou) { vis[idex] = 1; point[idex].cou = cou; int flag = 0; for (int i = 0; i < stl[idex].size(); i++) { if (vis[stl[idex][i]] == 0) { dfs(stl[idex][i], cou + 1); flag = 1; } } if (!flag) { point[idex].huo = 1; return; } for (int i = 0; i < stl[idex].size(); i++) point[idex].huo += point[stl[idex][i]].huo; point[idex].huo++; } long long ans[Max]; int main() { cin >> n >> k; int flag = 1; for (int i = 1; i <= n - 1; i++) { cin >> v >> u; stl[v].push_back(u); stl[u].push_back(v); } dfs(1, 1); for (int i = 1; i <= n; i++) { ans[i] = point[i].cou - point[i].huo; } sort(ans + 1, ans + n + 1); for (int i = n; i > n - k; i--) { tot += ans[i]; } cout << tot << endl; return 0; } |
/*
*
* Clock, reset generation unit for Atlys board
*
* Implements clock generation according to design defines
*
` */
`include "orpsoc-defines.v"
module clkgen
(
// Main clocks in, depending on board
input sys_clk_pad_i,
// Asynchronous, active low reset in
input rst_n_pad_i,
// Input reset - through a buffer, asynchronous
output async_rst_o,
// Wishbone clock and reset out
output wb_clk_o,
output wb_rst_o,
// JTAG clock
// input tck_pad_i,
// output dbg_tck_o,
// VGA CLK
// output dvi_clk_o,
// Main memory clocks
output ddr2_if_clk_o,
output ddr2_if_rst_o
// output clk100_o
);
// First, deal with the asychronous reset
wire async_rst_n;
assign async_rst_n = ~rst_n_pad_i;//rst_n_pad_i;
// Everyone likes active-high reset signals...
//assign async_rst_o = ~async_rst_n;
reg rst_r;
reg wb_rst_r;
//assign dbg_tck_o = tck_pad_i;
//
// Declare synchronous reset wires here
//
// An active-low synchronous reset signal (usually a PLL lock signal)
//wire sync_wb_rst_n;
wire sync_ddr2_rst_n;
// An active-low synchronous reset from ethernet PLL
//wire sync_eth_rst_n;
wire sys_clk_pad_ibufg;
/* DCM0 wires */
wire dcm0_clk0_prebufg, dcm0_clk0;
wire dcm0_clk90_prebufg, dcm0_clk90;
wire dcm0_clkfx_prebufg, dcm0_clkfx;
wire dcm0_clkdv_prebufg, dcm0_clkdv;
//wire dcm0_clk2x_prebufg, dcm0_clk2x;
wire dcm0_locked;
//wire pll0_clkfb;
//wire pll0_locked;
//wire pll0_clk1_prebufg, pll0_clk1;
IBUFG sys_clk_in_ibufg (
.I (sys_clk_pad_i),
.O (sys_clk_pad_ibufg)
);
// DCM providing main system/Wishbone clock
DCM_SP #(
// Generate 200 MHz from CLKFX
.CLKFX_MULTIPLY (4),
.CLKFX_DIVIDE (1),
.CLKIN_PERIOD (20.0),
// Generate 25 MHz from CLKDV
.CLKDV_DIVIDE (2.0)
) dcm0 (
// Outputs
.CLK0 (dcm0_clk0_prebufg),
.CLK180 (),
.CLK270 (),
.CLK2X180 (),
.CLK2X (),//dcm0_clk2x_prebufg),
.CLK90 (),//dcm0_clk90_prebufg),
.CLKDV (dcm0_clkdv_prebufg),
.CLKFX180 (),//dcm0_clkfx_prebufg),
.CLKFX (dcm0_clkfx_prebufg),
.LOCKED (dcm0_locked),
// Inputs
.CLKFB (dcm0_clk0),
.CLKIN (sys_clk_pad_ibufg),
.PSEN (1'b0),
.RST (1'b0)//async_rst_o)
);
/*
// Daisy chain DCM-PLL to reduce jitter
PLL_BASE #(
.BANDWIDTH("OPTIMIZED"),
// .CLKFBOUT_MULT(8), // 80 MHz
.CLKFBOUT_MULT(8), // 50 MHz
.CLKFBOUT_PHASE(0.0),
.CLKIN_PERIOD(20),
.CLKOUT1_DIVIDE(16),
.CLKOUT2_DIVIDE(1),
.CLKOUT3_DIVIDE(1),
.CLKOUT4_DIVIDE(1),
.CLKOUT5_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_PHASE(0.0),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_PHASE(0.0),
.CLKOUT5_PHASE(0.0),
.CLK_FEEDBACK("CLKFBOUT"),
.COMPENSATION("DCM2PLL"),
.DIVCLK_DIVIDE(1),
.REF_JITTER(0.1),
.RESET_ON_LOSS_OF_LOCK("FALSE")
) pll0 (
.CLKFBOUT (pll0_clkfb),
.CLKOUT1 (pll0_clk1_prebufg),
.CLKOUT2 (),
.CLKOUT3 (CLKOUT3),
.CLKOUT4 (CLKOUT4),
.CLKOUT5 (CLKOUT5),
.LOCKED (pll0_locked),
.CLKFBIN (pll0_clkfb),
.CLKIN (sys_clk_pad_ibufg),////dcm0_clk90_prebufg),
.RST (async_rst_o)
);
*/
BUFG dcm0_clk0_bufg
(// Outputs
.O (dcm0_clk0),
// Inputs
.I (dcm0_clk0_prebufg)
);
/*
BUFG dcm0_clk2x_bufg
(// Outputs
.O (dcm0_clk2x),
// Inputs
.I (dcm0_clk2x_prebufg)
);
*/
BUFG dcm0_clkfx_bufg
(// Outputs
.O (dcm0_clkfx),
// Inputs
.I (dcm0_clkfx_prebufg)
);
/* This is buffered in dvi_gen*/
BUFG dcm0_clkdv_bufg
(// Outputs
.O (dcm0_clkdv),
// Inputs
.I (dcm0_clkdv_prebufg)
);
/*
BUFG pll0_clk1_bufg
(// Outputs
.O (pll0_clk1),
// Inputs
.I (pll0_clk1_prebufg));
*/
assign wb_clk_o = dcm0_clkdv; //pll0_clk1;
//assign sync_wb_rst_n = pll0_locked;
assign sync_ddr2_rst_n = dcm0_locked;
assign ddr2_if_clk_o = dcm0_clkfx; // 200MHz
//assign clk100_o = dcm0_clk0; // 100MHz
//assign dvi_clk_o = dcm0_clkdv_prebufg;
//
// Reset generation
//
//
always @(posedge wb_clk_o or negedge async_rst_n)
if (~async_rst_n)
rst_r <= 1'b1;
else
rst_r <= #1 1'b0;
assign async_rst_o = rst_r;
always @(posedge wb_clk_o)
wb_rst_r <= #1 async_rst_o;
assign wb_rst_o = wb_rst_r;
// Reset generation for wishbone
/*reg [15:0] wb_rst_shr;
always @(posedge wb_clk_o or posedge async_rst_o)
if (async_rst_o)
wb_rst_shr <= 16'hffff;
else
wb_rst_shr <= {wb_rst_shr[14:0], ~(sync_wb_rst_n)};
assign wb_rst_o = wb_rst_shr[15];
*/
assign ddr2_if_rst_o = async_rst_o;
endmodule // clkgen
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.2 (win64) Build 932637 Wed Jun 11 13:33:10 MDT 2014
// Date : Tue Sep 16 21:34:47 2014
// Host : ECE-411-6 running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub
// C:/Users/coltmw/Documents/GitHub/ecen4024-microphone-array/microphone-array/microphone-array.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v
// Design : clk_wiz_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module clk_wiz_0(clk_in1, clk_out1, reset, locked)
/* synthesis syn_black_box black_box_pad_pin="clk_in1,clk_out1,reset,locked" */;
input clk_in1;
output clk_out1;
input reset;
output locked;
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_hdr_fifo.v
// Version: 1.0
// Verilog Standard: Verilog-2001
//
// Description: The tx_hdr_fifo module implements a simple fifo for a packet
// (WR_TX_HDR) header and three metadata signals: WR_TX_HDR_ABLANKS,
// WR_TX_HDR_LEN, WR_TX_HDR_NOPAYLOAD. NOPAYLOAD indicates that the header is not
// followed by a payload. HDR_LEN indicates the length of the header in
// dwords. The ABLANKS signal indicates how many dwords should be inserted between
// the header and payload.
//
// The intended use for this module is between the interface specific tx formatter
// (TXC or TXR) and the alignment pipeline, in parallel with the tx_data_pipeline
// which contains a fifo for payloads.
//
// Author: Dustin Richmond (@darichmond)
// Co-Authors:
//----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "trellis.vh" // Defines the user-facing signal widths.
module tx_hdr_fifo
#(parameter C_DEPTH_PACKETS = 10,
parameter C_MAX_HDR_WIDTH = 128,
parameter C_PIPELINE_OUTPUT = 1,
parameter C_PIPELINE_INPUT = 1,
parameter C_VENDOR = "ALTERA"
)
(
// Interface: Clocks
input CLK,
// Interface: Reset
input RST_IN,
// Interface: WR_TX_HDR
input WR_TX_HDR_VALID,
input [(C_MAX_HDR_WIDTH)-1:0] WR_TX_HDR,
input [`SIG_LEN_W-1:0] WR_TX_HDR_PAYLOAD_LEN,
input [`SIG_NONPAY_W-1:0] WR_TX_HDR_NONPAY_LEN,
input [`SIG_PACKETLEN_W-1:0] WR_TX_HDR_PACKET_LEN,
input WR_TX_HDR_NOPAYLOAD,
output WR_TX_HDR_READY,
// Interface: RD_TX_HDR
output RD_TX_HDR_VALID,
output [(C_MAX_HDR_WIDTH)-1:0] RD_TX_HDR,
output [`SIG_LEN_W-1:0] RD_TX_HDR_PAYLOAD_LEN,
output [`SIG_NONPAY_W-1:0] RD_TX_HDR_NONPAY_LEN,
output [`SIG_PACKETLEN_W-1:0] RD_TX_HDR_PACKET_LEN,
output RD_TX_HDR_NOPAYLOAD,
input RD_TX_HDR_READY
);
// Size of the header, plus the three metadata signals
localparam C_WIDTH = (C_MAX_HDR_WIDTH) + `SIG_NONPAY_W + `SIG_PACKETLEN_W + 1 + `SIG_LEN_W;
wire RST;
wire wWrTxHdrReady;
wire wWrTxHdrValid;
wire [(C_MAX_HDR_WIDTH)-1:0] wWrTxHdr;
wire [`SIG_NONPAY_W-1:0] wWrTxHdrNonpayLen;
wire [`SIG_PACKETLEN_W-1:0] wWrTxHdrPacketLen;
wire [`SIG_LEN_W-1:0] wWrTxHdrPayloadLen;
wire wWrTxHdrNoPayload;
wire wRdTxHdrReady;
wire wRdTxHdrValid;
wire [C_MAX_HDR_WIDTH-1:0] wRdTxHdr;
wire [`SIG_NONPAY_W-1:0] wRdTxHdrNonpayLen;
wire [`SIG_PACKETLEN_W-1:0] wRdTxHdrPacketLen;
wire [`SIG_LEN_W-1:0] wRdTxHdrPayloadLen;
wire wRdTxHdrNoPayload;
assign RST = RST_IN;
pipeline
#(
.C_DEPTH (C_PIPELINE_INPUT?1:0),
.C_USE_MEMORY (0),
/*AUTOINSTPARAM*/
// Parameters
.C_WIDTH (C_WIDTH))
input_pipeline_inst
(
// Outputs
.WR_DATA_READY (WR_TX_HDR_READY),
.RD_DATA ({wWrTxHdr,wWrTxHdrNonpayLen,wWrTxHdrPacketLen,wWrTxHdrPayloadLen,wWrTxHdrNoPayload}),
.RD_DATA_VALID (wWrTxHdrValid),
// Inputs
.WR_DATA ({WR_TX_HDR,WR_TX_HDR_NONPAY_LEN,WR_TX_HDR_PACKET_LEN,WR_TX_HDR_PAYLOAD_LEN,WR_TX_HDR_NOPAYLOAD}),
.WR_DATA_VALID (WR_TX_HDR_VALID),
.RD_DATA_READY (wWrTxHdrReady),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
fifo
#(
// Parameters
.C_DELAY (0),
/*AUTOINSTPARAM*/
// Parameters
.C_WIDTH (C_WIDTH),
.C_DEPTH (C_DEPTH_PACKETS))
fifo_inst
(
// Outputs
.RD_DATA ({wRdTxHdr,wRdTxHdrNonpayLen,wRdTxHdrPacketLen,wRdTxHdrPayloadLen,wRdTxHdrNoPayload}),
.WR_READY (wWrTxHdrReady),
.RD_VALID (wRdTxHdrValid),
// Inputs
.WR_DATA ({wWrTxHdr,wWrTxHdrNonpayLen,wWrTxHdrPacketLen,wWrTxHdrPayloadLen,wWrTxHdrNoPayload}),
.WR_VALID (wWrTxHdrValid),
.RD_READY (wRdTxHdrReady),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST (RST));
pipeline
#(
.C_DEPTH (C_PIPELINE_OUTPUT?1:0),
.C_USE_MEMORY (0),
/*AUTOINSTPARAM*/
// Parameters
.C_WIDTH (C_WIDTH))
output_pipeline_inst
(
// Outputs
.WR_DATA_READY (wRdTxHdrReady),
.RD_DATA ({RD_TX_HDR,RD_TX_HDR_NONPAY_LEN,RD_TX_HDR_PACKET_LEN,RD_TX_HDR_PAYLOAD_LEN,RD_TX_HDR_NOPAYLOAD}),
.RD_DATA_VALID (RD_TX_HDR_VALID),
// Inputs
.WR_DATA ({wRdTxHdr,wRdTxHdrNonpayLen,wRdTxHdrPacketLen,wRdTxHdrPayloadLen,wRdTxHdrNoPayload}),
.WR_DATA_VALID (wRdTxHdrValid),
.RD_DATA_READY (RD_TX_HDR_READY),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
// Local Variables:
// verilog-library-directories:("." "../../common/")
// End:
|
#include <bits/stdc++.h> using namespace std; ifstream fin( test.in ); double i, j, sens, k, o, ta, tb, pasi, p, d, pl, haur, n; int a, b, t, f, c; int main() { cin >> a >> b >> t >> f >> c; k = 1000; ta = a / k; tb = b / k; p = a * t; sens = 1; while (p < c) { n = 0; while (p + a > d + b && p < c) { p += a; d += b; n += a; } while (p > d && p < c) { p += ta; d += tb; n += ta; } if (p < c && p != c) ++haur; d = 0; p += n + a * f; } cout << haur; return 0; } |
#include <bits/stdc++.h> using namespace std; const int inf = 1 << 30; char buf[1000]; string nextLine(int length = 100) { cin.getline(buf, length); string s(buf); return s; } string next(int length = 100) { string tmp; cin >> tmp; return tmp; } int nextInt() { int tmp; scanf( %d , &tmp); return tmp; } long long mod = 1E9 + 7; long long add(long long a, long long b) { return (a + b) % mod; } const int MAXN = 5010; string s1, s2; int m, n; long long dp[MAXN][MAXN]; long long get(int starta, int startb) { if (starta == m) return 0; if (startb == n) return 0; long long &ret = dp[starta][startb]; if (ret != -1) return ret; ret = 0; if (s2[startb] == s1[starta]) { ret++; ret = add(ret, get(starta + 1, startb + 1)); } ret = add(ret, get(starta, startb + 1)); return ret; } int main() { s1 = next(); s2 = next(); m = ((int)(s1).size()); n = ((int)(s2).size()); long long sum = 0; for (int i = 0, _i = (MAXN); i < _i; ++i) for (int j = 0, _j = (MAXN); j < _j; ++j) dp[i][j] = -1; for (int i = 0, _i = (m); i < _i; ++i) { sum = add(sum, get(i, 0)); } cout << sum << endl; } |
#include <bits/stdc++.h> using namespace std; const int N = 2e3 + 10, H = 2e5 + 10, MOD = 1e9 + 7; struct node { int x, y; } a[N]; long long fac[H], inv[H], f[N]; int h, w, n; long long popow(long long x, int y) { long long t = x, re = 1; while (y) { if (y & 1) re = re * t % MOD; t = t * t % MOD; y >>= 1; } return re; } void prepare() { fac[0] = inv[0] = 1; for (int i = 1; i <= 2e5; ++i) { fac[i] = fac[i - 1] * i % MOD; inv[i] = popow(fac[i], MOD - 2); } } bool cmp(const node &aa, const node &bb) { return aa.x < bb.x || (aa.x == bb.x && aa.y < bb.y); } long long calc(int aa, int bb) { if (aa < bb) return 0; return fac[aa] * inv[bb] % MOD * inv[aa - bb] % MOD; } int main() { prepare(); scanf( %d%d%d , &h, &w, &n); for (int i = 1; i <= n; ++i) scanf( %d%d , &a[i].x, &a[i].y); ++n; a[n].x = h; a[n].y = w; sort(&a[1], &a[1 + n], cmp); for (int i = 1; i <= n; ++i) { f[i] = calc(a[i].x + a[i].y - 2, a[i].x - 1); for (int j = 1; j < i; ++j) if (a[j].y <= a[i].y) { f[i] -= f[j] * calc(a[i].x + a[i].y - a[j].x - a[j].y, a[i].x - a[j].x); f[i] %= MOD; } } printf( %lld n , (f[n] + MOD) % MOD); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O211AI_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__O211AI_PP_BLACKBOX_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o211ai (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O211AI_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; int num = 0, num1, num2; for (int i = 0; i < s.size(); i++) { if (s[i] == A ) { num1 = 0; for (int j = 0; j < i; j++) if (s[j] == Q ) num1++; num2 = 0; for (int j = i + 1; j < s.size(); j++) if (s[j] == Q ) num2++; num += (num1 * num2); } } cout << num; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND3B_PP_SYMBOL_V
`define SKY130_FD_SC_HS__AND3B_PP_SYMBOL_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__and3b (
//# {{data|Data Signals}}
input A_N ,
input B ,
input C ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND3B_PP_SYMBOL_V
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_ecb_e
//
// Generated
// by: wig
// on: Mon Apr 10 13:27:22 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_ecb_e.v,v 1.1 2006/04/10 15:42:05 wig Exp $
// $Date: 2006/04/10 15:42:05 $
// $Log: inst_ecb_e.v,v $
// Revision 1.1 2006/04/10 15:42:05 wig
// Updated testcase (__TOP__)
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
//
// Generator: mix_0.pl Revision: 1.44 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of inst_ecb_e
//
// No user `defines in this module
module inst_ecb_e
//
// Generated module inst_ecb
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of inst_ecb_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
// -*- Mode: Verilog -*-
// Filename : test_00.v
// Description : Simple ADXL362 Test Case to bring environment to life
// Author : Philip Tracton
// Created On : Thu Jun 23 11:36:12 2016
// Last Modified By: Philip Tracton
// Last Modified On: Thu Jun 23 11:36:12 2016
// Update Count : 0
// Status : Unknown, Use with caution!
`include "timescale.v"
`include "simulation_includes.vh"
module test_case ();
//
// Test Configuration
// These parameters need to be set for each test case
//
parameter simulation_name = "simple";
defparam `ADXL362_ACCELEROMETER.XDATA_FILE = "accelerometer_00_xdata.txt";
defparam `ADXL362_ACCELEROMETER.YDATA_FILE = "accelerometer_00_ydata.txt";
defparam `ADXL362_ACCELEROMETER.ZDATA_FILE = "accelerometer_00_zdata.txt";
defparam `ADXL362_ACCELEROMETER.TEMPERATURE_FILE = "accelerometer_00_temperature_data.txt";
parameter number_of_tests = 1;
reg err;
reg [31:0] data_out;
integer i;
initial begin
$display("Simple 00 Case");
@(posedge `WB_RST);
@(negedge `WB_RST);
@(posedge `WB_CLK);
@(negedge `ADXL362_RESET);
// @(posedge spi_testbench.ncs);
// @(posedge spi_testbench.ncs);
// @(posedge spi_testbench.ncs);
// `TEST_COMPARE("TEMPERATURE", 16'h02A5, spi_testbench.dut.temperature);
#2000;
`SWITCHES <= 1;
#100000;
`TEST_COMPLETE;
end
endmodule // test_case
|
module top;
real q_tst [$];
real q_tmp [$];
real elem;
integer idx;
bit passed;
task automatic check_size(integer size,
string fname,
integer lineno);
if (q_tst.size !== size) begin
$display("%s:%0d: Failed: queue size != %0d (%0d)",
fname, lineno, size, q_tst.size);
passed = 1'b0;
end
endtask
task automatic check_idx_value(integer idx,
real expected,
string fname,
integer lineno);
if (q_tst[idx] != expected) begin
$display("%s:%0d: Failed: element [%0d] != %.1f (%.1f)",
fname, lineno, idx, expected, q_tst[idx]);
passed = 1'b0;
end
endtask
initial begin
passed = 1'b1;
q_tst.delete(0); // Warning: skip delete on an empty queue
check_size(0, `__FILE__, `__LINE__);
check_idx_value(0, 0.0, `__FILE__, `__LINE__);
elem = q_tst.pop_front(); // Warning: cannot pop_front() an empty queue
if (elem != 0.0) begin
$display("Failed: pop_front() != 0.0 (%.1f)", elem);
passed = 1'b0;
end
elem = q_tst.pop_back(); // Warning: cannot pop_back() an empty queue
if (elem != 0.0) begin
$display("Failed: pop_back() != 0.0 (%.1f)", elem);
passed = 1'b0;
end
q_tst.push_back(2.0);
q_tst.push_front(1.0);
q_tst.push_back(3.0);
q_tst.push_back(100.0);
q_tst.delete(3); // Should $ work here?
q_tst.delete(3); // Warning: skip an out of range delete()
q_tst.delete(-1); // Warning: skip delete with negative index
q_tst.delete('X); // Warning: skip delete with undefined index
check_size(3, `__FILE__, `__LINE__);
if (q_tst[0] != 1.0) begin
$display("Failed: element [0] != 1.0 (%.1f)", q_tst[0]);
passed = 1'b0;
end
if (q_tst[1] != 2.0) begin
$display("Failed: element [1] != 2.0 (%.1f)", q_tst[1]);
passed = 1'b0;
end
if (q_tst[2] != 3.0) begin
$display("Failed: element [2] != 3.0 (%.1f)", q_tst[2]);
passed = 1'b0;
end
if (q_tst[3] != 0.0) begin
$display("Failed: element [3] != 0.0 (%.1f)", q_tst[3]);
passed = 1'b0;
end
if (q_tst[-1] != 0.0) begin
$display("Failed: element [-1] != 0.0 (%.1f)", q_tst[-1]);
passed = 1'b0;
end
if (q_tst['X] != 0.0) begin
$display("Failed: element ['X] != 0.0 (%.1f)", q_tst['X]);
passed = 1'b0;
end
check_idx_value(-1, 0.0, `__FILE__, `__LINE__);
check_idx_value('X, 0.0, `__FILE__, `__LINE__);
elem = q_tst.pop_front();
if (elem != 1.0) begin
$display("Failed: element pop_front() != 1.0 (%.1f)", elem);
passed = 1'b0;
end
elem = q_tst.pop_back();
if (elem != 3.0) begin
$display("Failed: element pop_back() != 3.0 (%.1f)", elem);
passed = 1'b0;
end
check_size(1, `__FILE__, `__LINE__);
if ((q_tst[0] != q_tst[$]) || (q_tst[0] != 2.0)) begin
$display("Failed: q_tst[0](%.1f) != q_tst[$](%.1f) != 2.0",
q_tst[0], q_tst[$]);
passed = 1'b0;
end
q_tst.delete();
check_size(0, `__FILE__, `__LINE__);
q_tst.push_front(5.0);
q_tst.push_front(100.0);
q_tst.push_back(100.0);
elem = q_tst.pop_back;
elem = q_tst.pop_front;
check_size(1, `__FILE__, `__LINE__);
check_idx_value(0, 5.0, `__FILE__, `__LINE__);
q_tst[0] = 1.0;
q_tst[1] = 2.5;
q_tst[1] = 2.0;
q_tst[2] = 3.0;
q_tst[-1] = 10.0; // Warning: will not be added (negative index)
q_tst['X] = 10.0; // Warning: will not be added (undefined index)
q_tst[4] = 10.0; // Warning: will not be added (out of range index)
idx = -1;
q_tst[idx] = 10.0; // Warning: will not be added (negative index)
idx = 3'b0x1;
q_tst[idx] = 10.0; // Warning: will not be added (undefined index)
idx = 4;
q_tst[idx] = 10.0; // Warning: will not be added (out of range index)
check_size(3, `__FILE__, `__LINE__);
check_idx_value(0, 1.0, `__FILE__, `__LINE__);
check_idx_value(1, 2.0, `__FILE__, `__LINE__);
check_idx_value(2, 3.0, `__FILE__, `__LINE__);
q_tst.delete();
q_tst[0] = 2.0;
q_tst.insert(1, 4.0);
q_tst.insert(0, 1.0);
q_tst.insert(2, 3.0);
q_tst.insert(-1, 10.0); // Warning: will not be added (negative index)
q_tst.insert('X, 10.0); // Warning: will not be added (undefined index)
q_tst.insert(5, 10.0); // Warning: will not be added (out of range index)
check_size(4, `__FILE__, `__LINE__);
check_idx_value(0, 1.0, `__FILE__, `__LINE__);
check_idx_value(1, 2.0, `__FILE__, `__LINE__);
check_idx_value(2, 3.0, `__FILE__, `__LINE__);
check_idx_value(3, 4.0, `__FILE__, `__LINE__);
q_tst = '{3.0, 2.0, 1.0};
check_size(3, `__FILE__, `__LINE__);
check_idx_value(0, 3.0, `__FILE__, `__LINE__);
check_idx_value(1, 2.0, `__FILE__, `__LINE__);
check_idx_value(2, 1.0, `__FILE__, `__LINE__);
q_tmp = '{1.0, 2.0};
q_tst = q_tmp;
q_tmp[0] = 3.0;
q_tmp[2] = 1.0;
check_size(2, `__FILE__, `__LINE__);
check_idx_value(0, 1.0, `__FILE__, `__LINE__);
check_idx_value(1, 2.0, `__FILE__, `__LINE__);
q_tst[2] = 3.0;
check_size(3, `__FILE__, `__LINE__);
check_idx_value(2, 3.0, `__FILE__, `__LINE__);
q_tst = {1.0, 2.0};
check_size(2, `__FILE__, `__LINE__);
check_idx_value(0, 1.0, `__FILE__, `__LINE__);
check_idx_value(1, 2.0, `__FILE__, `__LINE__);
q_tst = '{};
check_size(0, `__FILE__, `__LINE__);
if (passed) $display("PASSED");
end
endmodule : top
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MUX2_TB_V
`define SKY130_FD_SC_MS__MUX2_TB_V
/**
* mux2: 2-input multiplexer.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__mux2.v"
module top();
// Inputs are registered
reg A0;
reg A1;
reg S;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A0 = 1'bX;
A1 = 1'bX;
S = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A0 = 1'b0;
#40 A1 = 1'b0;
#60 S = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A0 = 1'b1;
#180 A1 = 1'b1;
#200 S = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A0 = 1'b0;
#320 A1 = 1'b0;
#340 S = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 S = 1'b1;
#540 A1 = 1'b1;
#560 A0 = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 S = 1'bx;
#680 A1 = 1'bx;
#700 A0 = 1'bx;
end
sky130_fd_sc_ms__mux2 dut (.A0(A0), .A1(A1), .S(S), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__MUX2_TB_V
|
`timescale 1ns / 1ps
/////////////////////////////////////////////////////////////////
// Module Name: mux_vector
/////////////////////////////////////////////////////////////////
module mux_vector #(parameter C_SIZE = 4 , DELAY = 3, C_NUM_CHANNELS=2)(
input wire [C_SIZE-1:0] a,
input wire [C_SIZE-1:0] b,
input wire [C_SIZE-1:0] c,
input wire [C_SIZE-1:0] d,
input wire [C_SIZE-1:0] e,
input wire [C_SIZE-1:0] f,
input wire [C_SIZE-1:0] g,
input wire [C_SIZE-1:0] h,
input wire [2:0] sel,
output wire [C_SIZE-1:0] y
);
reg [C_SIZE-1:0] data;
always @(*) begin
case(C_NUM_CHANNELS)
2: begin
case(sel)
1'b0 : data[C_SIZE-1:0] <= a[C_SIZE-1:0] ;
1'b1 : data[C_SIZE-1:0] <= b[C_SIZE-1:0] ;
default : data[C_SIZE-1:0] <= a[C_SIZE-1:0] ;
endcase
end
4: begin
case(sel)
2'b00 : data[C_SIZE-1:0] <= a[C_SIZE-1:0] ;
2'b01 : data[C_SIZE-1:0] <= b[C_SIZE-1:0] ;
2'b10 : data[C_SIZE-1:0] <= c[C_SIZE-1:0] ;
2'b11 : data[C_SIZE-1:0] <= d[C_SIZE-1:0] ;
default : data[C_SIZE-1:0] <= a[C_SIZE-1:0] ;
endcase
end
8: begin
case(sel)
3'b000 : data[C_SIZE-1:0] <= a[C_SIZE-1:0] ;
3'b001 : data[C_SIZE-1:0] <= b[C_SIZE-1:0] ;
3'b010 : data[C_SIZE-1:0] <= c[C_SIZE-1:0] ;
3'b011 : data[C_SIZE-1:0] <= d[C_SIZE-1:0] ;
3'b100 : data[C_SIZE-1:0] <= e[C_SIZE-1:0] ;
3'b101 : data[C_SIZE-1:0] <= f[C_SIZE-1:0] ;
3'b110 : data[C_SIZE-1:0] <= g[C_SIZE-1:0] ;
3'b111 : data[C_SIZE-1:0] <= h[C_SIZE-1:0] ;
default : data[C_SIZE-1:0] <= a[C_SIZE-1:0] ;
endcase
end
endcase
end
assign #DELAY y[C_SIZE-1:0] = data[C_SIZE-1:0] ;
endmodule
|
`timescale 1ns / 1ps
/*
* File : uart_clock.v
* Creator(s) : Grant Ayers ()
*
* Modification History:
* Rev Date Initials Description of Change
* 1.0 24-May-2010 GEA Initial design.
*
* Standards/Formatting:
* Verilog 2001, 4 soft tab, wide column.
*
* Description:
* Generate synchronous pulses for 115200 baud and 16x 115200 baud (synchronized)
* from an uncorrelated input clock.
*
* This timing can be adjusted to allow for other baud rates.
*/
module uart_clock(
input clock,
output uart_tick,
output uart_tick_16x
);
/* Goal: Generate a pulse at 115200 Hz using an input clock
* that is not an even multiple of 115200.
*
* Method: Find constants 'a', 'b' such that clock / (2^a / b) ~= 115200.
* Accumulate 'b' each cycle and use the overflow bit 'a' for the pulse.
*
* 66 MHz: 66 MHz / (2^18 / 453) = 115203.857 Hz
* 100 MHz: 100 MHz / (2^17 / 151) = 115203.857 Hz
*
* We also need to extend this for a 16x pulse to over-sample:
*
* 66 MHz: 66 MHz / (2^14 / 453) = 115203.857 Hz * 16
* 100 MHz: 100 MHz / (2^13 / 151) = 115203.857 Hz * 16
*/
// 16x Pulse Generation
// 66 MHz version
reg [14:0] accumulator = 15'h0000;
always @(posedge clock) begin
accumulator <= accumulator[13:0] + 453;
end
assign uart_tick_16x = accumulator[14];
/*
// 100 MHz version
reg [13:0] accumulator = 14'h0000;
always @(posedge clock) begin
accumulator <= accumulator[12:0] + 151;
end
assign uart_tick_16x = accumulator[13];
*/
// 1x Pulse Generation (115200 Hz)
reg [3:0] uart_16x_count = 4'h0;
always @(posedge clock) begin
uart_16x_count <= (uart_tick_16x) ? uart_16x_count + 1'b1 : uart_16x_count;
end
assign uart_tick = (uart_tick_16x==1'b1 && (uart_16x_count == 4'b1111));
endmodule
|
`timescale 1ns/1ps
`include "test.svh"
module tb_Top ();
parameter WIDTH = 8, DEPTH = 32 , DEPTH2 = 2*DEPTH;
parameter clk_period = 2;
parameter half_period = 1;
//parameter SIZE = 3 ;
`define SIZE = DEPTH
/*integer [7:0] A [2:0][2:0];
integer [7:0] B [2:0][2:0];
integer [7:0] C [2:0][2:0];*/
byte unsigned A[DEPTH-1:0][DEPTH-1:0];
byte unsigned B[DEPTH-1:0][DEPTH-1:0];
byte unsigned C[DEPTH-1:0][DEPTH-1:0];
reg CLK;
reg RESET;
reg RESET_sram;
reg [WIDTH-1:0] data_in_dram [DEPTH-1:0];
reg DRAM;
reg valid;
reg WEN;
reg REN;
reg REN_q;
wire [DEPTH-1:0] Full_out;
wire [DEPTH-1:0] Empty_out;
reg [WIDTH-1:0] w_in [0:DEPTH-1];
reg stall;
reg set_w;
reg [WIDTH-1:0] temp ;
`TB_ARG_STR(weights, "values.raw/features_layer9_fire_squeeze_Conv2D_eightbit_quantized_conv/1/lhs_169_256.trunc");
`TB_ARG_STR(inputval, "values.raw/features_layer9_fire_squeeze_Conv2D_eightbit_quantized_conv/1/rhs_256_48.trunc");
`TB_ARG_INT(mode, "0");
Top #(.DEPTH(DEPTH),.ADDRESS_WIDTH(5), .WIDTH(WIDTH))ITop (.CLK(CLK), .RESET_sram(RESET_sram),.RESET(RESET),.data_in_dram(data_in_dram),.DRAM(DRAM),.valid(valid),.REN(REN),.WEN(WEN),.Full_out(Full_out),.Empty_out(Empty_out),.w_in(w_in),.stall(stall),.set_w(set_w),.REN_q(REN_q));
always begin
#half_period
CLK = ~CLK;
end
initial begin
CLK=0;
RESET = 0;
RESET_sram=0;
DRAM=1;
valid =0;
REN =0;
REN_q =0;
WEN=0;
stall=0;
set_w=0;
for(integer j=0;j<DEPTH;j++) begin
w_in[j] = 8'h00;
data_in_dram[j] = 8'h00;
end
$fsdbDumpfile("test.fsdb");
$fsdbDumpvars(1,Top);
$fsdbDumpMDA(1,Top);
/*for (integer idx = 0; idx < DEPTH; idx = idx + 1) begin
$dumpvars(0, data_in_dram[idx]);
$dumpvars(0, w_in[idx]);
end*/
//randominputs();
TFinputs();
//loadInputAndWeights();
if (mode == 1) begin
loadWeights();
end else if (mode == 2) begin
loadInputs();
end
else begin
loadInputAndWeights();
end
#20
multiply();
#50
REN_q = 1'b1;
#DEPTH2 REN_q =1'b0;
#200 $finish;
end
task randominputs;
for (integer i=0;i<DEPTH;i++) begin
for(integer j=0;j<DEPTH;j++) begin
#0 A[i][j] = $urandom_range(DEPTH-1,0);
#0 B[i][j] = $urandom_range(DEPTH-1,0);
end
end
for (integer i=0;i<DEPTH;i++) begin
for(integer j=0;j<DEPTH;j++) begin
C[i][j] = 0;
for (integer k=0;k<DEPTH;k++) begin
#0 C[i][j] = C[i][j]+ (A[i][k]*B[k][j]);
end
end
end
endtask
task TFinputs;
integer In_File_ID,In_A,W_File_ID,W_B;
//In_File_ID = $fopen("values.raw/features_layer9_fire_squeeze_Conv2D_eightbit_quantized_conv/1/lhs_169_DEPTH.trunc", "rb");
In_File_ID = $fopen(weights,"rb");
//In_A = $fread(A, In_File_ID);
//W_File_ID = $fopen("values.raw/features_layer9_fire_squeeze_Conv2D_eightbit_quantized_conv/1/rhs_DEPTH_48.trunc", "rb");
W_File_ID = $fopen(inputval,"rb");
//W_B = $fread(B, W_File_ID);
for (integer i=0;i<DEPTH;i++) begin
for(integer j=0;j<DEPTH;j++) begin
$fread(temp,In_File_ID);
A[i][j] = temp ;
$fread(temp,W_File_ID);
B[i][j] = temp ;
end
end
$fclose(In_File_ID);
$fclose(W_File_ID);
for (integer i=0;i<DEPTH;i++) begin
for(integer j=0;j<DEPTH;j++) begin
C[i][j] = 0;
for (integer k=0;k<DEPTH;k++) begin
#0 C[i][j] = C[i][j]+ (A[i][k]*B[k][j]);
end
end
end
endtask
task displayIO;
for (integer i=0;i<DEPTH-1;i++) begin
for(integer j=0;j<DEPTH-1;j++) begin
$write("%d\t",A[i][j]);
end
$display("");
end
$display("");
for (integer i=0;i<DEPTH-1;i++) begin
for(integer j=0;j<DEPTH-1;j++) begin
$write("%d\t",B[i][j]);
end
$display("");
end
$display("");
for (integer i=0;i<DEPTH-1;i++) begin
for(integer j=0;j<DEPTH-1;j++) begin
$write("%d\t",C[i][j]);
end
$display("");
end
endtask
task loadInputAndWeights;
@(posedge CLK) RESET=1; RESET_sram =1'b1;
@(posedge CLK) RESET=1; RESET_sram =1'b1;
@(posedge CLK) RESET=1; RESET_sram =1'b1;
@(posedge CLK) RESET=0; RESET_sram =1'b0;
@(posedge CLK) RESET=0; RESET_sram =1'b0;
for(integer i=DEPTH-1,j=0;i>=0;i--,j++) begin
@(posedge CLK) begin
set_w <= 1'b1;
WEN <= 1'b1;
for(integer k=0,l=DEPTH;k<DEPTH-1;k++,l--) begin
w_in[k] <= B[i][k];
data_in_dram[l] <= A[k][i];
end
end
end
@(posedge CLK)
set_w <=1'b0;
WEN <=1'b0;
endtask
task multiply;
@(posedge CLK) RESET=1'b1;
@(posedge CLK) RESET=1'b0;
@(posedge CLK)
REN <=1'b1;
valid <= 1'b1;
repeat (DEPTH) begin
@(posedge CLK) valid <=1'b1;
end
repeat (2*DEPTH) begin
@(posedge CLK) valid <= 1'b0;
end
@(posedge CLK)
valid <= 1'b0;
REN <= 1'b0;
endtask
task loadWeights;
@(posedge CLK) RESET=1; RESET_sram =1'b1;
@(posedge CLK) RESET=1; RESET_sram =1'b1;
@(posedge CLK) RESET=1; RESET_sram =1'b1;
@(posedge CLK) RESET=0; RESET_sram =1'b0;
@(posedge CLK) RESET=0; RESET_sram =1'b0;
for(integer i=DEPTH-1,j=0;i>=0;i--,j++) begin
@(posedge CLK) begin
set_w <= 1'b1;
//WEN <= 1'b1;
for(integer k=0,l=DEPTH-1;k<DEPTH;k++,l--) begin
w_in[k] <= B[i][k];
//data_in_dram[l] <= A[k][i];
end
end
end
@(posedge CLK)
set_w <=1'b0;
WEN <=1'b0;
endtask
task loadInputs;
@(posedge CLK) RESET=1; RESET_sram =1'b1;
@(posedge CLK) RESET=1; RESET_sram =1'b1;
@(posedge CLK) RESET=1; RESET_sram =1'b1;
@(posedge CLK) RESET=0; RESET_sram =1'b0;
@(posedge CLK) RESET=0; RESET_sram =1'b0;
for(integer i=DEPTH-1,j=0;i>=0;i--,j++) begin
@(posedge CLK) begin
//set_w <= 1'b1;
WEN <= 1'b1;
for(integer k=0,l=DEPTH-1;k<DEPTH;k++,l--) begin
//w_in[k] <= B[i][k];
data_in_dram[l] <= A[k][i];
end
end
end
@(posedge CLK)
set_w <=1'b0;
WEN <=1'b0;
endtask
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 500000; const int M = 70; const int C = 300; const int MOD = 1e9 + 7; struct Point { int x[5]; Point() { for (int i = 0; i < 5; i++) x[i] = 0; } }; int n; Point a[N]; vector<int> res; Point diff(const Point &a, const Point &b) { Point res = Point(); for (int i = 0; i < 5; i++) res.x[i] = a.x[i] - b.x[i]; return res; } bool check(const Point &a, const Point &b) { int val = 0; for (int i = 0; i < 5; i++) val += a.x[i] * b.x[i]; return (val > 0); } int main() { scanf( %d , &n); for (int i = 0; i < n; i++) { for (int j = 0; j < 5; j++) scanf( %d , &a[i].x[j]); } int ans = 0; if (n <= C) { for (int i = 0; i < n; i++) { bool flag = true; for (int j = 0; j < n; j++) { for (int k = j + 1; k < n; k++) { if (j == i || k == i) continue; if (check(diff(a[j], a[i]), diff(a[k], a[i]))) { flag = false; break; } } } if (flag) { ans++; res.push_back(i + 1); } } } cout << ans << endl; for (int i = 0; i < res.size(); i++) cout << res[i] << ; return 0; } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx_buf_pdr_odd.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
`include "sys.h"
`include "iop.h"
module pcx_buf_pdr_odd(/*AUTOARG*/
// Outputs
arbpc1_pcxdp_grant_pa, arbpc1_pcxdp_q0_hold_pa_l,
arbpc1_pcxdp_qsel0_pa, arbpc1_pcxdp_qsel1_pa_l,
arbpc1_pcxdp_shift_px, arbpc3_pcxdp_grant_pa,
arbpc3_pcxdp_q0_hold_pa_l, arbpc3_pcxdp_qsel0_pa,
arbpc3_pcxdp_qsel1_pa_l, arbpc3_pcxdp_shift_px,
arbpc4_pcxdp_grant_pa, arbpc4_pcxdp_q0_hold_pa_l,
arbpc4_pcxdp_qsel0_pa, arbpc4_pcxdp_qsel1_pa_l,
arbpc4_pcxdp_shift_px,
// Inputs
arbpc1_pcxdp_grant_bufp3_pa_l, arbpc1_pcxdp_q0_hold_bufp3_pa,
arbpc1_pcxdp_qsel0_bufp3_pa_l, arbpc1_pcxdp_qsel1_bufp3_pa,
arbpc1_pcxdp_shift_bufp3_px_l, arbpc3_pcxdp_grant_bufp3_pa_l,
arbpc3_pcxdp_q0_hold_bufp3_pa, arbpc3_pcxdp_qsel0_bufp3_pa_l,
arbpc3_pcxdp_qsel1_bufp3_pa, arbpc3_pcxdp_shift_bufp3_px_l,
arbpc4_pcxdp_grant_bufp3_pa_l, arbpc4_pcxdp_q0_hold_bufp3_pa,
arbpc4_pcxdp_qsel0_bufp3_pa_l, arbpc4_pcxdp_qsel1_bufp3_pa,
arbpc4_pcxdp_shift_bufp3_px_l
);
output arbpc1_pcxdp_grant_pa ;
output arbpc1_pcxdp_q0_hold_pa_l ;
output arbpc1_pcxdp_qsel0_pa ;
output arbpc1_pcxdp_qsel1_pa_l ;
output arbpc1_pcxdp_shift_px ;
output arbpc3_pcxdp_grant_pa ;
output arbpc3_pcxdp_q0_hold_pa_l ;
output arbpc3_pcxdp_qsel0_pa ;
output arbpc3_pcxdp_qsel1_pa_l ;
output arbpc3_pcxdp_shift_px ;
output arbpc4_pcxdp_grant_pa ;
output arbpc4_pcxdp_q0_hold_pa_l ;
output arbpc4_pcxdp_qsel0_pa ;
output arbpc4_pcxdp_qsel1_pa_l ;
output arbpc4_pcxdp_shift_px ;
input arbpc1_pcxdp_grant_bufp3_pa_l;
input arbpc1_pcxdp_q0_hold_bufp3_pa;
input arbpc1_pcxdp_qsel0_bufp3_pa_l;
input arbpc1_pcxdp_qsel1_bufp3_pa;
input arbpc1_pcxdp_shift_bufp3_px_l;
input arbpc3_pcxdp_grant_bufp3_pa_l;
input arbpc3_pcxdp_q0_hold_bufp3_pa;
input arbpc3_pcxdp_qsel0_bufp3_pa_l;
input arbpc3_pcxdp_qsel1_bufp3_pa;
input arbpc3_pcxdp_shift_bufp3_px_l;
input arbpc4_pcxdp_grant_bufp3_pa_l;
input arbpc4_pcxdp_q0_hold_bufp3_pa;
input arbpc4_pcxdp_qsel0_bufp3_pa_l;
input arbpc4_pcxdp_qsel1_bufp3_pa;
input arbpc4_pcxdp_shift_bufp3_px_l;
assign arbpc1_pcxdp_grant_pa = ~arbpc1_pcxdp_grant_bufp3_pa_l;
assign arbpc1_pcxdp_q0_hold_pa_l = ~arbpc1_pcxdp_q0_hold_bufp3_pa;
assign arbpc1_pcxdp_qsel0_pa = ~arbpc1_pcxdp_qsel0_bufp3_pa_l;
assign arbpc1_pcxdp_qsel1_pa_l = ~arbpc1_pcxdp_qsel1_bufp3_pa;
assign arbpc1_pcxdp_shift_px = ~arbpc1_pcxdp_shift_bufp3_px_l;
assign arbpc3_pcxdp_grant_pa = ~arbpc3_pcxdp_grant_bufp3_pa_l;
assign arbpc3_pcxdp_q0_hold_pa_l = ~arbpc3_pcxdp_q0_hold_bufp3_pa;
assign arbpc3_pcxdp_qsel0_pa = ~arbpc3_pcxdp_qsel0_bufp3_pa_l;
assign arbpc3_pcxdp_qsel1_pa_l = ~arbpc3_pcxdp_qsel1_bufp3_pa;
assign arbpc3_pcxdp_shift_px = ~arbpc3_pcxdp_shift_bufp3_px_l;
assign arbpc4_pcxdp_grant_pa = ~arbpc4_pcxdp_grant_bufp3_pa_l;
assign arbpc4_pcxdp_q0_hold_pa_l = ~arbpc4_pcxdp_q0_hold_bufp3_pa;
assign arbpc4_pcxdp_qsel0_pa = ~arbpc4_pcxdp_qsel0_bufp3_pa_l;
assign arbpc4_pcxdp_qsel1_pa_l = ~arbpc4_pcxdp_qsel1_bufp3_pa;
assign arbpc4_pcxdp_shift_px = ~arbpc4_pcxdp_shift_bufp3_px_l;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__PROBEC_P_8_V
`define SKY130_FD_SC_HVL__PROBEC_P_8_V
/**
* probec_p: Virtual current probe point.
*
* Verilog wrapper for probec_p with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__probec_p.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__probec_p_8 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__probec_p base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__probec_p_8 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__probec_p base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__PROBEC_P_8_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: fpu_out_dp.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
///////////////////////////////////////////////////////////////////////////////
//
// FPU output datapath.
//
///////////////////////////////////////////////////////////////////////////////
module fpu_out_dp (
dest_rdy,
req_thread,
div_exc_out,
d8stg_fdivd,
d8stg_fdivs,
div_sign_out,
div_exp_out,
div_frac_out,
mul_exc_out,
m6stg_fmul_dbl_dst,
m6stg_fmuls,
mul_sign_out,
mul_exp_out,
mul_frac_out,
add_exc_out,
a6stg_fcmpop,
add_cc_out,
add_fcc_out,
a6stg_dbl_dst,
a6stg_sng_dst,
a6stg_long_dst,
a6stg_int_dst,
add_sign_out,
add_exp_out,
add_frac_out,
rclk,
fp_cpx_data_ca,
se,
si,
so
);
input [2:0] dest_rdy; // pipe with result request this cycle
input [1:0] req_thread; // thread ID of result req this cycle
input [4:0] div_exc_out; // divide pipe result- exception flags
input d8stg_fdivd; // divide double- divide stage 8
input d8stg_fdivs; // divide single- divide stage 8
input div_sign_out; // divide sign output
input [10:0] div_exp_out; // divide exponent output
input [51:0] div_frac_out; // divide fraction output
input [4:0] mul_exc_out; // multiply pipe result- exception flags
input m6stg_fmul_dbl_dst; // double precision multiply result
input m6stg_fmuls; // fmuls- multiply 6 stage
input mul_sign_out; // multiply sign output
input [10:0] mul_exp_out; // multiply exponent output
input [51:0] mul_frac_out; // multiply fraction output
input [4:0] add_exc_out; // add pipe result- exception flags
input a6stg_fcmpop; // compare- add 6 stage
input [1:0] add_cc_out; // add pipe result- condition
input [1:0] add_fcc_out; // add pipe input fcc passed through
input a6stg_dbl_dst; // float double result- add 6 stage
input a6stg_sng_dst; // float single result- add 6 stage
input a6stg_long_dst; // 64bit integer result- add 6 stage
input a6stg_int_dst; // 32bit integer result- add 6 stage
input add_sign_out; // add sign output
input [10:0] add_exp_out; // add exponent output
input [63:0] add_frac_out; // add fraction output
input rclk; // global clock
output [144:0] fp_cpx_data_ca; // FPU result to CPX
input se; // scan_enable
input si; // scan in
output so; // scan out
wire [63:0] add_out;
wire [63:0] mul_out;
wire [63:0] div_out;
wire [7:0] fp_cpx_data_ca_84_77_in;
wire [76:0] fp_cpx_data_ca_76_0_in;
wire [7:0] fp_cpx_data_ca_84_77;
wire [76:0] fp_cpx_data_ca_76_0;
wire [144:0] fp_cpx_data_ca;
wire se_l;
assign se_l = ~se;
clken_buf ckbuf_out_dp (
.clk(clk),
.rclk(rclk),
.enb_l(1'b0),
.tmb_l(se_l)
);
///////////////////////////////////////////////////////////////////////////////
//
// Add pipe output.
//
///////////////////////////////////////////////////////////////////////////////
assign add_out[63:0]= ({64{a6stg_dbl_dst}}
& {add_sign_out, add_exp_out[10:0],
add_frac_out[62:11]})
| ({64{a6stg_sng_dst}}
& {add_sign_out, add_exp_out[7:0],
add_frac_out[62:40], 32'b0})
| ({64{a6stg_long_dst}}
& add_frac_out[63:0])
| ({64{a6stg_int_dst}}
& {add_frac_out[63:32], 32'b0});
///////////////////////////////////////////////////////////////////////////////
//
// Multiply output.
//
///////////////////////////////////////////////////////////////////////////////
assign mul_out[63:0]= ({64{m6stg_fmul_dbl_dst}}
& {mul_sign_out, mul_exp_out[10:0],
mul_frac_out[51:0]})
| ({64{m6stg_fmuls}}
& {mul_sign_out, mul_exp_out[7:0],
mul_frac_out[51:29], 32'b0});
///////////////////////////////////////////////////////////////////////////////
//
// Divide output.
//
///////////////////////////////////////////////////////////////////////////////
assign div_out[63:0]= ({64{d8stg_fdivd}}
& {div_sign_out, div_exp_out[10:0],
div_frac_out[51:0]})
| ({64{d8stg_fdivs}}
& {div_sign_out, div_exp_out[7:0],
div_frac_out[51:29], 32'b0});
///////////////////////////////////////////////////////////////////////////////
//
// Choose the output data.
//
// Input to the CPX data (CA) stage.
//
///////////////////////////////////////////////////////////////////////////////
assign fp_cpx_data_ca_84_77_in[7:0]= ({8{(|dest_rdy)}}
& {1'b1, 4'b1000, 1'b0, req_thread[1:0]});
assign fp_cpx_data_ca_76_0_in[76:0]= ({77{dest_rdy[2]}}
& {div_exc_out[4:0], 8'b0, div_out[63:0]})
| ({77{dest_rdy[1]}}
& {mul_exc_out[4:0], 8'b0, mul_out[63:0]})
| ({77{dest_rdy[0]}}
& {add_exc_out[4:0], 2'b0, a6stg_fcmpop,
add_cc_out[1:0], add_fcc_out[1:0], 1'b0,
add_out[63:0]});
dff_s #(8) i_fp_cpx_data_ca_84_77 (
.din (fp_cpx_data_ca_84_77_in[7:0]),
.clk (clk),
.q (fp_cpx_data_ca_84_77[7:0]),
.se (se),
.si (),
.so ()
);
dff_s #(77) i_fp_cpx_data_ca_76_0 (
.din (fp_cpx_data_ca_76_0_in[76:0]),
.clk (clk),
.q (fp_cpx_data_ca_76_0[76:0]),
.se (se),
.si (),
.so ()
);
assign fp_cpx_data_ca[144:0]= {fp_cpx_data_ca_84_77[7:3],
3'b0,
fp_cpx_data_ca_84_77[2:0],
57'b0,
fp_cpx_data_ca_76_0[76:0]};
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int ans = 0; for (int i = 0; i < n; i++) { int val; cin >> val; if (val >= 0) ans += val; else ans -= val; } cout << ans << endl; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUFLP_M_V
`define SKY130_FD_SC_LP__BUFLP_M_V
/**
* buflp: Buffer, Low Power.
*
* Verilog wrapper for buflp with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__buflp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__buflp_m (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__buflp base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__buflp_m (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__buflp base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUFLP_M_V
|
#include <bits/stdc++.h> using namespace std; long long n, yu, one, sum, cnt = 3; long long ans[4]; long long gcd(long long a, long long b) { return !b ? a : gcd(b, a % b); } int main() { scanf( %I64d , &n); if (!(n % 3)) printf( 1 1 %I64d , n - 2); else printf( 1 2 %I64d , n - 3); return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 100086; int z[maxn], n, m, num, order[maxn][2], last[maxn], ans[maxn], len, in[maxn]; bool flag, ok[maxn]; char s[2]; int main() { scanf( %d %d , &n, &m); for (int i = 1; i <= m; i++) { scanf( %s , s); scanf( %d , &num); if (s[0] == - ) { if (z[num] == 0) z[num] = -1; order[i][0] = -1; order[i][1] = num; } else { if (z[num] == 0) z[num] = 1; order[i][0] = 1; order[i][1] = num; } } num = 0; for (int i = 1; i <= n; i++) { if (z[i] == 0) ans[++len] = i; else { if (z[i] == -1) { in[i] = 1; num++; } ok[i] = 1; } } for (int i = 1; i <= m; i++) { if (order[i][0] == -1) { num--; in[order[i][1]] = 0; if (num) ok[order[i][1]] = 0; last[order[i][1]] = i; if ((i != m) && (order[i + 1][1] != order[i][1])) ok[order[i][1]] = 0; } else { in[order[i][1]] = 1; if (num) ok[order[i][1]] = 0; if (last[order[i][1]] != i - 1) ok[order[i][1]] = 0; num++; last[order[i][1]] = i; } } for (int i = 1; i <= n; i++) if (ok[i]) ans[++len] = i; sort(ans + 1, ans + 1 + len); printf( %d n , len); if (len) { for (int i = 1; i < len; i++) printf( %d , ans[i]); printf( %d , ans[len]); printf( n ); } return 0; } |
`include "common.vh"
`timescale 1ns/10ps
module Top();
reg clk = 1;
reg rhalt = 1;
reg reset = 1;
always #(`CLOCKPERIOD / 2) clk = ~clk;
wire halt = 0;
// rhalt and reset timing should be independent of each other, and
// do indeed appear to be so.
initial #(1 * 4 * `CLOCKPERIOD) rhalt = 0;
initial #(1 * 3 * `CLOCKPERIOD) reset = 0;
Tenyr tenyr(.clk, .reset, .halt);
task end_simulation;
begin
integer row, col, i;
if ($test$plusargs("DUMPENDSTATE")) begin
for (row = 0; row < 3; row = row + 1) begin
$write("state: ");
for (col = 0; col < 6 && row * 6 + col < 16; col = col + 1) begin
i = row * 6 + col;
$write("%c %08x ", 65 + i, tenyr.core.regs.store[i]);
end
$write("\n");
end
end
$finish;
end
endtask
`ifdef __ICARUS__
// TODO The `ifdef guard should really be controlling for VPI availability
reg [8 * 4096:0] filename;
reg [8 * 4096:0] logfile = "Top.vcd";
integer periods = 32'hffffffff;
integer clk_count = 0;
integer insn_count = 0;
integer temp;
integer failure = 0;
initial #0 begin
if ($value$plusargs("LOAD=%s", filename)) begin
$tenyr_load(filename, failure); // replace with $readmemh ?
if (failure) begin
$display("Could not load file %0s", filename);
$stop;
end
end
if ($value$plusargs("PERIODS=%d", temp))
periods = temp;
if ($value$plusargs("LOGFILE=%s", filename))
logfile = filename;
if ($test$plusargs("DUMP_ALL")) begin
$dumpfile(logfile);
$dumpvars(0, Top);
end
#(periods * `CLOCKPERIOD) end_simulation();
end
`endif
always #`CLOCKPERIOD begin
if (tenyr.core.insn == 32'hffffffff)
end_simulation();
clk_count = clk_count + 1;
if (tenyr.core.state == tenyr.core.s3) begin
insn_count = insn_count + 1;
end
end
endmodule
|
// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 24080 $
// $Date: 2011-05-18 19:32:52 +0000 (Wed, 18 May 2011) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module RWire(WGET, WHAS, WVAL, WSET);
parameter width = 1;
input [width - 1 : 0] WVAL;
input WSET;
output [width - 1 : 0] WGET;
output WHAS;
assign WGET = WVAL;
assign WHAS = WSET;
endmodule
|
#include <bits/stdc++.h> using namespace std; struct BIT { vector<pair<int, int> > f; void init() { f.push_back(make_pair(-1e9, 0)); f.push_back(make_pair(0, 0)); f.push_back(make_pair(1e9, 0)); sort(f.begin(), f.end()); } void update(int i, int val, bool fake = 0) { if (fake) { f.push_back(make_pair(i, 0)); return; } i = lower_bound(f.begin(), f.end(), make_pair(i, 0)) - f.begin(); for (; i < f.size(); i += i & -i) f[i].second = max(f[i].second, val); } int get(int i, bool fake = 0) { if (fake) { f.push_back(make_pair(i, 0)); return 0; } i = lower_bound(f.begin(), f.end(), make_pair(i, 0)) - f.begin(); int ret = 0; for (; i; i -= i & -i) ret = max(ret, f[i].second); return ret; } } f[100005]; struct data { int u, v, c; data(int _u, int _v, int _c) : u(_u), v(_v), c(_c){}; }; int n, m; vector<data> e; signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> m; for (int i = 1; i <= m; i++) { int u, v, c; cin >> u >> v >> c; e.push_back(data(u, v, c)); } for (auto &it : e) { f[it.u].get(it.c - 1, 1); f[it.v].update(it.c, 0, 1); } for (int i = 1; i <= n; i++) f[i].init(); int ans = 0; for (auto &it : e) { int rec = f[it.u].get(it.c - 1); ans = max(ans, rec + 1); f[it.v].update(it.c, rec + 1); } cout << ans << n ; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EBUFN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__EBUFN_BEHAVIORAL_PP_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__ebufn (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_teb;
// Name Output Other arguments
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND );
bufif0 bufif00 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__EBUFN_BEHAVIORAL_PP_V |
module top;
reg a;
reg q, d;
event foo;
real rl;
int ar [];
int start = 0;
int stop = 1;
int step = 1;
int done = 0;
task a_task;
real trl;
event tevt;
reg tvr;
$display("user task");
endtask
always_comb begin: blk_name
event int1, int2;
real intrl;
q <= d;
-> foo;
rl = 0.0;
rl <= 1.0;
ar = new [2];
for (int idx = start; idx < stop; idx += step) $display("For: %0d", idx);
for (int idx = 0; done; idx = done + 1) $display("Should never run!");
for (int idx = 0; idx; done = done + 1) $display("Should never run!");
for (int idx = 0; idx; {done, idx} = done + 1) $display("Should never run!");
for (int idx = 0; idx; idx <<= 1) $display("Should never run!");
for (int idx = 0; idx; idx = idx << 1) $display("Should never run!");
$display("array size: %0d", ar.size());
ar.delete();
$display("array size: %0d", ar.size());
a_task;
assign a = 1'b0;
deassign a;
do $display("do/while");
while (a);
force a = 1'b1;
release a;
while(a) begin
$display("while");
a = 1'b0;
end
repeat(2) $display("repeat");
disable out_name;
forever begin
$display("forever");
disable blk_name; // This one should not generate a warning
end
end
initial #1 $display("Expect compile warnings!\nPASSED");
initial begin: out_name
#2 $display("FAILED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; double x, sum = 0; cin >> t; for (int i = 1; i <= t; i++) { cin >> x; sum += x; } cout << (sum / t) << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; long long power(long long x, long long n) { long long ans = 1; for (int i = 1; i <= n; i++) ans *= x; return ans; } long long gcd(long long x, long long y) { return (x % y == 0) ? y : gcd(y, x % y); } long long n, l, r; int main() { cin >> n >> l >> r; if (n == 1) cout << r - l + 1; else if (n == 2) { cout << (r - l + 1) * (r - l); } else if (n > 30) { cout << 0; } else { long long ans = 0; for (int i = 2; i < r; i++) { int p = i, R = r / power(p, n - 1); if (R == 0) break; for (int j = 1; j < p; j++) { int q = j; int L = (l - 1) / power(q, n - 1) + 1; if (L > R) continue; if (gcd(p, q) == 1) { ans += (R - L + 1); } } } cout << ans * 2 << endl; } } |
#include <bits/stdc++.h> using namespace std; int n, m; bool cmp(pair<int, int> a, pair<int, int> b) { if (a.first != b.first) return a.first > b.first; return a.second < b.second; } bool cmp2(pair<int, int> a, pair<int, int> b) { return a.second < b.second; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; vector<pair<int, int> > v; for (int i = 1; i <= n; i++) { int x; cin >> x; v.push_back({x, i}); } sort(v.begin(), v.end(), cmp); cin >> m; while (m--) { int k, pos; cin >> k >> pos; vector<pair<int, int> > res; for (int i = 0; i < k; i++) { res.push_back(v[i]); } sort(res.begin(), res.end(), cmp2); cout << res[pos - 1].first << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, k; int l, MOD; map<long long, int> mp; int fib(long long n) { if (mp.count(n)) return mp[n]; if (n & 1) return mp[n] = 1LL * fib(n / 2) * (fib(n / 2 - 1) + fib(n / 2 + 1)) % MOD; return mp[n] = (1LL * fib(n / 2) * fib(n / 2) + 1LL * fib(n / 2 - 1) * fib(n / 2 - 1)) % MOD; } int bpow(int a, long long b) { int ans = 1; while (b) { if (b & 1) ans = 1LL * ans * a % MOD; b >>= 1; a = 1LL * a * a % MOD; } return ans; } int main() { ios::sync_with_stdio(false); cin >> n >> k >> l >> MOD; if (k >= (1LL << min(l, 62))) { cout << 0 n ; return 0; } mp[0] = 1 % MOD; mp[1] = 1 % MOD; int zero = fib(n + 1); int one = (bpow(2, n) - zero + MOD) % MOD; int ans = 1 % MOD; for (int i = 0; i < min(l, 62); i++) if ((1LL << i) & k) ans = 1LL * ans * one % MOD; else ans = 1LL * ans * zero % MOD; for (int i = 62; i < l; i++) ans = 1LL * ans * zero % MOD; cout << ans << endl; return 0; } |
/*
* Copyright 2020-2022 F4PGA Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`include "routing/rmux.sim.v"
`include "../logicbox/logicbox.sim.v"
module USE_MUX (a, b, c, o1, o2);
input wire a;
input wire b;
input wire c;
output wire o1;
output wire o2;
wire logic_a;
wire logic_b;
wire logic_c;
LOGICBOX lboxa (.I(a), .O(logic_a));
LOGICBOX lboxb (.I(b), .O(logic_b));
LOGICBOX lboxc (.I(c), .O(logic_c));
parameter FASM_MUX1 = "I0";
RMUX #(.MODE(FASM_MUX1)) mux1 (.I0(logic_a), .I1(logic_b), .O(o1));
parameter FASM_MUX2 = "I0";
RMUX #(.MODE(FASM_MUX2)) mux2 (.I0(logic_a), .I1(logic_c), .O(o2));
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// DCFIFO_36x16_DR for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Kibin Park <>
// Yong Ho Song <>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Kibin Park <>
//
// Project Name: Cosmos OpenSSD
// Design Name: Dual clock distributed ram FIFO (36 width, 16 depth) wrapper
// Module Name: DCFIFO_36x16_DR
// File Name: DCFIFO_36x16_DR.v
//
// Version: v1.0.0
//
// Description: Standard FIFO, 1 cycle data out latency
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module DCFIFO_36x16_DR
(
input iWClock ,
input iWReset ,
input [35:0] iPushData ,
input iPushEnable ,
output oIsFull ,
input iRClock ,
input iRReset ,
output [35:0] oPopData ,
input iPopEnable ,
output oIsEmpty
);
DPBDCFIFO36x16DR
Inst_DPBDCFIFO36x16DR
(
.wr_clk (iWClock ),
.wr_rst (iWReset ),
.din (iPushData ),
.wr_en (iPushEnable ),
.full (oIsFull ),
.rd_clk (iRClock ),
.rd_rst (iRReset ),
.dout (oPopData ),
.rd_en (iPopEnable ),
.empty (oIsEmpty )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename Arg1> void __f(const char* name, Arg1&& arg1) { cerr << name << : << arg1 << std::endl; } template <typename Arg1, typename... Args> void __f(const char* names, Arg1&& arg1, Args&&... args) { const char* comma = strchr(names + 1, , ); cerr.write(names, comma - names) << : << arg1 << | ; __f(comma + 1, args...); } const int N = int(2e5) + 10; const int M = int(1e5) + 5; const int INF = int(1e9); int U[N], V[N], W[N], vis[N], D[N], comp[N], val[N], ans[N], parent; vector<int> g[N], rg[N], G[N], nodes; int n, m; int adj(int u, int e) { return U[e] ^ V[e] ^ u; } void get(int u) { nodes.push_back(u); nodes.push_back(u + M); vis[u] = 1; for (auto e : G[u]) { int w = adj(u, e); if (vis[w]) continue; get(w); } } int NOT(int u) { if (u < M) return u + M; else return u - M; } void addEdge(int u, int v) { u = NOT(u); g[u].push_back(v); rg[v].push_back(u); u = NOT(u); v = NOT(v); swap(u, v); g[u].push_back(v); rg[v].push_back(u); } void clear(int u) { g[u].clear(), rg[u].clear(), vis[u] = 0, val[u] = 0, comp[u] = 0; for (auto e : G[u]) D[e] = 0; } vector<int> order, component; void dfs1(int u) { vis[u] = 1; for (auto w : g[u]) if (!vis[w]) dfs1(w); order.push_back(u); } void dfs2(int u) { vis[u] = 1; comp[u] = parent; for (auto w : rg[u]) if (!vis[w]) dfs2(w); } int go(int t) { for (auto u : nodes) clear(u); for (auto u : nodes) for (auto e : G[u]) if (!D[e]) { D[e] = 1; if (W[e] == t) addEdge(U[e], V[e]), addEdge(NOT(U[e]), NOT(V[e])); else addEdge(U[e], NOT(V[e])), addEdge(NOT(U[e]), V[e]); } order.clear(); for (auto i : nodes) if (!vis[i]) dfs1(i); for (auto u : nodes) vis[u] = 0; reverse(order.begin(), order.end()); vector<int> Cmp; for (auto i : order) { if (!vis[i]) parent = i, Cmp.push_back(i), dfs2(i); } for (auto u : nodes) { if (comp[u] == comp[NOT(u)]) return INF; } reverse(Cmp.begin(), Cmp.end()); int a = 0, b = 0; for (auto u : Cmp) { if (!val[u]) { val[u] = 1; val[comp[NOT(u)]] = -1; } } for (auto u : nodes) if (u < M) (val[comp[u]] == 1) ? a++ : b++; int V = (a > b ? 0 : 1); for (auto u : nodes) if (u < M && val[comp[u]] == 1) ans[u] = V; else if (u < M) ans[u] = 1 - V; return min(a, b); } int main() { scanf( %d %d , &n, &m); for (int i = 1; i <= m; i++) { char x; scanf( %d %d %c , U + i, V + i, &x); G[U[i]].push_back(i); G[V[i]].push_back(i); W[i] = (x == R ? 1 : 0); } long long int Ans1 = 0, Ans2 = 0; for (int i = 1; i <= n; i++) if (!vis[i]) { nodes.clear(); get(i); Ans1 += go(0); Ans2 += go(1); } long long int Ans = min(Ans1, Ans2); if (Ans >= INF) puts( -1 ); else { printf( %lld n , Ans); int t = (Ans == Ans1 ? 0 : 1); memset(vis, 0, sizeof(vis)); for (int i = 1; i <= n; i++) if (!vis[i]) { nodes.clear(); get(i); go(t); } for (int i = 1; i <= n; i++) if (ans[i]) printf( %d , i); puts( ); } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long sz = 2e6 + 5, mod = 1e9 + 9; long long t, n, m, k, q; const long long inf = 3e18; long long dx[] = {1, 0, -1, 0}; long long dy[] = {0, 1, 0, -1}; bool vis[sz]; vector<vector<long long> > gr(sz); vector<long long> cnt(sz, 0); void DFS(long long s) { vis[s] = 1; for (auto i : gr[s]) { if (!vis[i]) DFS(i); } return; } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); t = 1; while (t--) { cin >> n >> m; for (long long i = 0; i < m; i++) { long long a, b; cin >> a >> b; if (a == b) { cnt[a]++; continue; } gr[a].push_back(b); gr[b].push_back(a); } long long cnt1 = 0; for (long long i = 1; i <= n; i++) { cnt1 += cnt[i]; } long long c = 0; for (long long i = 1; i <= n; i++) { if (!vis[i] && gr[i].size()) DFS(i), c++; else if (!vis[i]) { if (cnt[i]) c++; } } if (c > 1) { cout << 0 << n ; return 0; } long long ans = 0; ans += cnt1 * (cnt1 - 1) / 2; ans += cnt1 * (m - cnt1); for (long long i = 1; i <= n; i++) { ans += gr[i].size() * (gr[i].size() - 1) / 2; } cout << ans << n ; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DLXTP_BLACKBOX_V
`define SKY130_FD_SC_HVL__DLXTP_BLACKBOX_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__dlxtp (
Q ,
D ,
GATE
);
output Q ;
input D ;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DLXTP_BLACKBOX_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011 (c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; Loos OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE PoosIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
module axi_hdmi_rx (
// hdmi interface
hdmi_rx_clk,
hdmi_rx_data,
// dma interface
hdmi_clk,
hdmi_dma_sof,
hdmi_dma_de,
hdmi_dma_data,
hdmi_dma_ovf,
hdmi_dma_unf,
// processor interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready);
// parameters
parameter PCORE_ID = 0;
// hdmi interface
input hdmi_rx_clk;
input [15:0] hdmi_rx_data;
// vdma interface
output hdmi_clk;
output hdmi_dma_sof;
output hdmi_dma_de;
output [63:0] hdmi_dma_data;
input hdmi_dma_ovf;
input hdmi_dma_unf;
// processor interface
input s_axi_aresetn;
input s_axi_aclk;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
input s_axi_rready;
// internal signals
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
wire up_wack_s;
wire up_rreq_s;
wire [13:0] up_raddr_s;
wire [31:0] up_rdata_s;
wire up_rack_s;
wire hdmi_edge_sel_s;
wire hdmi_bgr_s;
wire hdmi_packed_s;
wire hdmi_csc_bypass_s;
wire [15:0] hdmi_vs_count_s;
wire [15:0] hdmi_hs_count_s;
wire hdmi_tpm_oos_s;
wire hdmi_vs_oos_s;
wire hdmi_hs_oos_s;
wire hdmi_vs_mismatch_s;
wire hdmi_hs_mismatch_s;
wire [15:0] hdmi_vs_s;
wire [15:0] hdmi_hs_s;
wire hdmi_rst;
wire [15:0] hdmi_data;
// signal name changes
assign hdmi_clk = hdmi_rx_clk;
assign hdmi_data = hdmi_rx_data;
assign up_rstn = s_axi_aresetn;
assign up_clk = s_axi_aclk;
// axi interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
// processor interface
up_hdmi_rx i_up (
.hdmi_clk (hdmi_clk),
.hdmi_rst (hdmi_rst),
.hdmi_edge_sel (hdmi_edge_sel_s),
.hdmi_bgr (hdmi_bgr_s),
.hdmi_packed (hdmi_packed_s),
.hdmi_csc_bypass (hdmi_csc_bypass_s),
.hdmi_vs_count (hdmi_vs_count_s),
.hdmi_hs_count (hdmi_hs_count_s),
.hdmi_dma_ovf (hdmi_dma_ovf),
.hdmi_dma_unf (hdmi_dma_unf),
.hdmi_tpm_oos (hdmi_tpm_oos_s),
.hdmi_vs_oos (hdmi_vs_oos_s),
.hdmi_hs_oos (hdmi_hs_oos_s),
.hdmi_vs_mismatch (hdmi_vs_mismatch_s),
.hdmi_hs_mismatch (hdmi_hs_mismatch_s),
.hdmi_vs (hdmi_vs_s),
.hdmi_hs (hdmi_hs_s),
.hdmi_clk_ratio (32'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
// hdmi interface
axi_hdmi_rx_core i_rx_core (
.hdmi_clk (hdmi_clk),
.hdmi_rst (hdmi_rst),
.hdmi_data (hdmi_data),
.hdmi_edge_sel (hdmi_edge_sel_s),
.hdmi_bgr (hdmi_bgr_s),
.hdmi_packed (hdmi_packed_s),
.hdmi_csc_bypass (hdmi_csc_bypass_s),
.hdmi_vs_count (hdmi_vs_count_s),
.hdmi_hs_count (hdmi_hs_count_s),
.hdmi_tpm_oos (hdmi_tpm_oos_s),
.hdmi_vs_oos (hdmi_vs_oos_s),
.hdmi_hs_oos (hdmi_hs_oos_s),
.hdmi_vs_mismatch (hdmi_vs_mismatch_s),
.hdmi_hs_mismatch (hdmi_hs_mismatch_s),
.hdmi_vs (hdmi_vs_s),
.hdmi_hs (hdmi_hs_s),
.hdmi_dma_sof (hdmi_dma_sof),
.hdmi_dma_de (hdmi_dma_de),
.hdmi_dma_data (hdmi_dma_data));
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; const int Mod = 1000000000 + 7; const int MAXK = 1000000; int power(int x, int k) { int ret = 1; while (k) { if (k & 1) ret = 1LL * ret * x % Mod; x = 1LL * x * x % Mod; k >>= 1; } return ret; } int n, k, ans; int f[MAXK + 10]; void init() { cin >> n >> k; if (n <= k + 10) { for (int i = 1; i <= n; i++) ans = (power(i, k) + ans) % Mod; cout << ans; } else { for (int i = 1; i <= k + 2; i++) f[i] = (f[i - 1] + power(i, k)) % Mod; int s = 1, m = 1; for (int j = 2; j <= k + 2; j++) s = 1LL * s * (n - j) % Mod; for (int j = 2; j <= k + 2; j++) m = 1LL * m * ((1 - j) + Mod) % Mod; int l = -(k + 1), r = 1; for (int i = 1; i <= k + 2; i++) { ans = (1LL * f[i] * s % Mod * power(m, Mod - 2) % Mod + ans) % Mod; s = 1LL * s * (n - i) % Mod * power(n - (i + 1), Mod - 2) % Mod; m = 1LL * m * r % Mod * power(l + Mod, Mod - 2) % Mod; l++, r++; } cout << ans; } return; } int main() { init(); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__INV_TB_V
`define SKY130_FD_SC_HD__INV_TB_V
/**
* inv: Inverter.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__inv.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hd__inv dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__INV_TB_V
|
//-----------------------------------------------------------------------------
// Title : MIPS Single-Cycle Control Unit
// Project : ECE 313 - Computer Organization
//-----------------------------------------------------------------------------
// File : control_single.v
// Author : John Nestor <>
// Organization : Lafayette College
//
// Created : October 2002
// Last modified : 7 January 2005
//-----------------------------------------------------------------------------
// Description :
// Control unit for the MIPS "Single Cycle" processor implementation described
// Section 5.4 of "Computer Organization and Design, 3rd ed."
// by David Patterson & John Hennessey, Morgan Kaufmann, 2004 (COD3e).
//
// It implements the function specified in Figure 5.18 on p. 308 of COD3e.
//
//-----------------------------------------------------------------------------
module control_single(opcode, RegDst, ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, Branch, Jmp, ALUOp);
input [5:0] opcode;
output RegDst, ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, Branch, Jmp;
output [1:0] ALUOp;
reg RegDst, ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, Branch, Jmp;
reg [1:0] ALUOp;
parameter R_FORMAT = 6'd0;
parameter LW = 6'd35;
parameter SW = 6'd43;
parameter BEQ = 6'd4;
parameter ADDI = 6'd8;
parameter BNE = 6'd5;
parameter J = 6'd2;
always @(opcode)
begin
case (opcode)
R_FORMAT :
begin
RegDst=1'b1; ALUSrc=1'b0; MemtoReg=1'b0; RegWrite=1'b1; MemRead=1'b0;
MemWrite=1'b0; Branch=1'b0; Jmp=1'b0; ALUOp = 2'b10;
end
LW :
begin
RegDst=1'b0; ALUSrc=1'b1; MemtoReg=1'b1; RegWrite=1'b1; MemRead=1'b1;
MemWrite=1'b0; Branch=1'b0; Jmp=1'b0; ALUOp = 2'b00;
end
SW :
begin
RegDst=1'bx; ALUSrc=1'b1; MemtoReg=1'bx; RegWrite=1'b0; MemRead=1'b0;
MemWrite=1'b1; Branch=1'b0; Jmp=1'b0; ALUOp = 2'b00;
end
BEQ :
begin
RegDst=1'bx; ALUSrc=1'b0; MemtoReg=1'bx; RegWrite=1'b0; MemRead=1'b0;
MemWrite=1'b0; Branch=1'b1; Jmp=1'b0; ALUOp = 2'b01;
end
ADDI :
begin
RegDst=1'b0; ALUSrc=1'b1; MemtoReg=1'b0; RegWrite=1'b1; MemRead=1'b0;
MemWrite=1'bx; Branch=1'b0; Jmp=1'b0; ALUOp = 2'b00;
end
BNE :
begin
RegDst=1'bx; ALUSrc=1'b0; MemtoReg=1'bx; RegWrite=1'b0; MemRead=1'b0;
MemWrite=1'b0; Branch=1'b1; Jmp=1'b0; ALUOp = 2'b01;
end
J :
begin
RegDst=1'bx; ALUSrc=1'bx; MemtoReg=1'bx; RegWrite=1'bx; MemRead=1'bx;
MemWrite=1'b0; Branch=1'b0; Jmp=1'b1; ALUOp = 2'bxx;
end
default
begin
$display("control_single unimplemented opcode %d", opcode);
RegDst=1'bx; ALUSrc=1'bx; MemtoReg=1'bx; RegWrite=1'bx; MemRead=1'bx;
MemWrite=1'bx; Branch=1'bx; Jmp=1'b0; ALUOp = 2'bxx;
end
endcase
end
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// NPhy_Toggle_Top_DDR100 for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Ilyong Jung <>
// Yong Ho Song <>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Ilyong Jung <>
//
// Project Name: Cosmos OpenSSD
// Design Name: NPhy_Toggle_Top_DDR100
// Module Name: NPhy_Toggle_Top_DDR100
// File Name: NPhy_Toggle_Top_DDR100.v
//
// Version: v1.0.0
//
// Description: NFC phy top
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module NPhy_Toggle_Top_DDR100
#
(
parameter IDelayValue = 7,
parameter InputClockBufferType = 0,
parameter NumberOfWays = 4
)
(
iSystemClock ,
iDelayRefClock ,
iOutputDrivingClock ,
iPI_Reset ,
iPI_BUFF_Reset ,
iPO_Reset ,
iPI_BUFF_RE ,
iPI_BUFF_WE ,
iPI_BUFF_OutSel ,
oPI_BUFF_Empty ,
oPI_DQ ,
oPI_ValidFlag ,
iPIDelayTapLoad ,
iPIDelayTap ,
oPIDelayReady ,
iDQSOutEnable ,
iDQOutEnable ,
iPO_DQStrobe ,
iPO_DQ ,
iPO_ChipEnable ,
iPO_ReadEnable ,
iPO_WriteEnable ,
iPO_AddressLatchEnable ,
iPO_CommandLatchEnable ,
oReadyBusy ,
iWriteProtect ,
IO_NAND_DQS_P ,
IO_NAND_DQS_N ,
IO_NAND_DQ ,
O_NAND_CE ,
O_NAND_WE ,
O_NAND_RE_P ,
O_NAND_RE_N ,
O_NAND_ALE ,
O_NAND_CLE ,
I_NAND_RB ,
O_NAND_WP
);
// NPhy_Toggle Interface - PO Interface
// All signals are active high.
// CE/RE/WE are inverted in OSERDESE2 module.
// NPhy_Toggle Interface - Pad Interface
// Direction Select: 0-Read from NAND, 1-Write to NAND
// future -> add parameter: data width, resolution
input iSystemClock ; // SDR 100MHz
input iDelayRefClock ; // SDR 200MHz
input iOutputDrivingClock ; // SDR 200Mhz
input iPI_Reset ;
input iPI_BUFF_Reset ;
input iPO_Reset ;
input iPI_BUFF_RE ;
input iPI_BUFF_WE ;
input [2:0] iPI_BUFF_OutSel ;
output oPI_BUFF_Empty ;
output [31:0] oPI_DQ ;
output [3:0] oPI_ValidFlag ;
input iPIDelayTapLoad ;
input [4:0] iPIDelayTap ;
output oPIDelayReady ;
input iDQSOutEnable ;
input iDQOutEnable ;
input [7:0] iPO_DQStrobe ;
input [31:0] iPO_DQ ;
input [2*NumberOfWays - 1:0] iPO_ChipEnable ;
input [3:0] iPO_ReadEnable ;
input [3:0] iPO_WriteEnable ;
input [3:0] iPO_AddressLatchEnable ;
input [3:0] iPO_CommandLatchEnable ;
output [NumberOfWays - 1:0] oReadyBusy ;
input iWriteProtect ;
inout IO_NAND_DQS_P ; // Differential: Positive
inout IO_NAND_DQS_N ; // Differential: Negative
inout [7:0] IO_NAND_DQ ;
output [NumberOfWays - 1:0] O_NAND_CE ;
output O_NAND_WE ;
output O_NAND_RE_P ; // Differential: Positive
output O_NAND_RE_N ; // Differential: Negative
output O_NAND_ALE ;
output O_NAND_CLE ;
input [NumberOfWays - 1:0] I_NAND_RB ;
output O_NAND_WP ;
// Internal Wires/Regs
wire wDQSOutEnableToPinpad ;
wire [7:0] wDQOutEnableToPinpad ;
wire wDQSFromNAND ;
wire wDQSToNAND ;
wire [7:0] wDQFromNAND ;
wire [7:0] wDQToNAND ;
wire [NumberOfWays - 1:0] wCEToNAND ;
wire wWEToNAND ;
wire wREToNAND ;
wire wALEToNAND ;
wire wCLEToNAND ;
wire wWPToNAND ;
wire [NumberOfWays - 1:0] wReadyBusyFromNAND ;
reg [NumberOfWays - 1:0] rReadyBusyCDCBuf0 ;
reg [NumberOfWays - 1:0] rReadyBusyCDCBuf1 ;
// Input
NPhy_Toggle_Physical_Input_DDR100
#
(
.IDelayValue (IDelayValue ),
.InputClockBufferType (InputClockBufferType )
)
Inst_NPhy_Toggle_Physical_Input
(
.iSystemClock (iSystemClock ),
.iDelayRefClock (iDelayRefClock ),
.iModuleReset (iPI_Reset ),
.iBufferReset (iPI_BUFF_Reset ),
// PI Interface
.iPI_Buff_RE (iPI_BUFF_RE ),
.iPI_Buff_WE (iPI_BUFF_WE ),
.iPI_Buff_OutSel (iPI_BUFF_OutSel ),
.oPI_Buff_Empty (oPI_BUFF_Empty ),
.oPI_DQ (oPI_DQ ),
.oPI_ValidFlag (oPI_ValidFlag ),
.iPI_DelayTapLoad (iPIDelayTapLoad ),
.iPI_DelayTap (iPIDelayTap ),
.oPI_DelayReady (oPIDelayReady ),
// Pad Interface
.iDQSFromNAND (wDQSFromNAND ),
.iDQFromNAND (wDQFromNAND )
);
// Output
NPhy_Toggle_Physical_Output_DDR100
#
(
.NumberOfWays (NumberOfWays )
)
Inst_NPhy_Toggle_Physical_Output
(
.iSystemClock (iSystemClock ),
.iOutputDrivingClock (iOutputDrivingClock ),
.iModuleReset (iPO_Reset ),
// PO Interface
.iDQSOutEnable (iDQSOutEnable ),
.iDQOutEnable (iDQOutEnable ),
.iPO_DQStrobe (iPO_DQStrobe ),
.iPO_DQ (iPO_DQ ),
.iPO_ChipEnable (iPO_ChipEnable ),
.iPO_ReadEnable (iPO_ReadEnable ),
.iPO_WriteEnable (iPO_WriteEnable ),
.iPO_AddressLatchEnable (iPO_AddressLatchEnable ),
.iPO_CommandLatchEnable (iPO_CommandLatchEnable ),
// Pad Interface
.oDQSOutEnableToPinpad (wDQSOutEnableToPinpad ),
.oDQOutEnableToPinpad (wDQOutEnableToPinpad ),
.oDQSToNAND (wDQSToNAND ),
.oDQToNAND (wDQToNAND ),
.oCEToNAND (wCEToNAND ),
.oWEToNAND (wWEToNAND ),
.oREToNAND (wREToNAND ),
.oALEToNAND (wALEToNAND ),
.oCLEToNAND (wCLEToNAND )
);
assign wWPToNAND = ~iWriteProtect; // convert WP to WP-
always @ (posedge iSystemClock)
begin
if (iPI_Reset)
begin
rReadyBusyCDCBuf0 <= {(NumberOfWays){1'b0}};
rReadyBusyCDCBuf1 <= {(NumberOfWays){1'b0}};
end
else
begin
rReadyBusyCDCBuf0 <= rReadyBusyCDCBuf1;
rReadyBusyCDCBuf1 <= wReadyBusyFromNAND;
end
end
assign oReadyBusy = rReadyBusyCDCBuf0;
// Pinpad
NPhy_Toggle_Pinpad
#
(
.NumberOfWays (NumberOfWays )
)
Inst_NPhy_Toggle_Pinpad
(
// Pad Interface
.iDQSOutEnable (wDQSOutEnableToPinpad ),
.iDQSToNAND (wDQSToNAND ),
.oDQSFromNAND (wDQSFromNAND ),
.iDQOutEnable (wDQOutEnableToPinpad ),
.iDQToNAND (wDQToNAND ),
.oDQFromNAND (wDQFromNAND ),
.iCEToNAND (wCEToNAND ),
.iWEToNAND (wWEToNAND ),
.iREToNAND (wREToNAND ),
.iALEToNAND (wALEToNAND ),
.iCLEToNAND (wCLEToNAND ),
.oRBFromNAND (wReadyBusyFromNAND ), // bypass
.iWPToNAND (wWPToNAND ), // bypass
// NAND Interface
.IO_NAND_DQS_P (IO_NAND_DQS_P ), // Differential: Positive
.IO_NAND_DQS_N (IO_NAND_DQS_N ), // Differential: Negative
.IO_NAND_DQ (IO_NAND_DQ ),
.O_NAND_CE (O_NAND_CE ),
.O_NAND_WE (O_NAND_WE ),
.O_NAND_RE_P (O_NAND_RE_P ), // Differential: Positive
.O_NAND_RE_N (O_NAND_RE_N ), // Differential: Negative
.O_NAND_ALE (O_NAND_ALE ),
.O_NAND_CLE (O_NAND_CLE ),
.I_NAND_RB (I_NAND_RB ),
.O_NAND_WP (O_NAND_WP )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; pair<int, int> a[100005]; int n, t, v[100005], c[100005]; int main() { cin >> n; for (int i = 0; i < n - 1; ++i) cin >> a[i].first >> a[i].second; for (int i = 0; i < n; ++i) cin >> c[i + 1]; for (int i = 0; i < n - 1; ++i) { if (c[a[i].first] != c[a[i].second]) { t++; v[a[i].first]++; v[a[i].second]++; } } for (int i = 1; i <= n; ++i) { if (v[i] == t) { cout << YES n << i << n ; return 0; } } cout << NO n ; return 0; } |
#include <bits/stdc++.h> using namespace std; inline int add(int a, int b, int c) { a += b; if (a >= c) a -= c; else if (a < 0) a += c; return a; } inline int mul(int a, int b, int c) { return (long long)a * b % c; } int pow(int a, long long b, int c) { int res = 1; for (; b; b /= 2) { if (b % 2) res = mul(res, a, c); a = mul(a, a, c); } return res; } int main() { int t; scanf( %d , &t); while (t--) { int k, p; long long l, r; scanf( %d%I64d%I64d%d , &k, &l, &r, &p); if (p == 2) { printf( %d n , !(k % 2)); continue; } int prod = 1; if (k % p) { int e = pow(2, l, p - 1); int t = pow(k, e, p); if (t == 1) prod = pow(2, r - l + 1, p); else { int inv = pow(add(t, -1, p), p - 2, p); int num = add(pow(t, add(pow(2, r - l + 1, p - 1), -1, p - 1), p), -1, p); prod = add(mul(t, mul(num, inv, p), p), 1, p); } } if (k % 2) prod = mul(prod, pow(2, add(l % (p - 1), -(r % (p - 1)), p - 1), p), p); printf( %d n , prod); } return 0; } |
`default_nettype none
module pulse_control(
input clk,
input RS232_Rx,
output RS232_Tx,
output [31:0] per,
output [15:0] p1wid,
output [15:0] del,
output [15:0] p2wid,
output [7:0] nut_w,
output [15:0] nut_d,
// output [6:0] pr_att,
// output [6:0] po_att,
output [7:0] cp,
output [7:0] p_bl,
output [15:0] p_bl_off,
output bl,
output rxd
);
// Control the pulses
// Running at a 201-MHz clock, our time step is ~5 (4.975) ns.
// All the times are thus divided by 4.975 ns to get cycles.
// 32-bit allows times up to 21 seconds
parameter stperiod = 15; // 1 ms period
parameter stp1width = 30; // 150 ns
parameter stp2width = 30;
parameter stdelay = 200; // 1 us delay
parameter stblock = 100; // 500 ns block open
parameter stcpmg = 3;
parameter stnutdel = 100;
parameter stnutwid = 100;
reg [31:0] period = stperiod << 16;
reg [15:0] p1width = stp1width;
reg [15:0] delay = stdelay;
reg [15:0] p2width = stp2width;
reg [7:0] pulse_block = 8'd50;
reg [15:0] pulse_block_off = stblock;
reg [7:0] cpmg = stcpmg;
reg block = 1;
reg rx_done = 0;
reg [15:0] nut_del = stnutdel;
reg [7:0] nut_wid = stnutdel;
// Control the attenuators
// parameter att_pre_val = 7'd1;
// parameter att_post_val = 7'd0;
// reg [6:0] pre_att = att_pre_val;
// reg [6:0] post_att = att_post_val;
assign per = period;
assign p1wid = p1width;
assign p2wid = p2width;
assign del = delay;
// assign pr_att = pre_att;
// assign po_att = post_att;
assign cp = cpmg;
assign p_bl = pulse_block;
assign p_bl_off = pulse_block_off;
assign bl = block;
assign rxd = rx_done;
assign nut_d = nut_del;
assign nut_w = nut_wid;
// Setup necessary for UART
wire reset = 0;
reg transmit;
reg [7:0] tx_byte;
wire received;
wire [7:0] rx_byte;
wire is_receiving;
wire is_transmitting;
wire recv_error;
// UART module, from https://github.com/cyrozap/osdvu
uart uart0( //testing with 115200 baud and 50 MHz clock from sim_tb
.clk(clk), // The master clock for this module
.rst(reset), // Synchronous reset
.rx(RS232_Rx), // Incoming serial line
.tx(RS232_Tx), // Outgoing serial line
.transmit(transmit), // Signal to transmit
.tx_byte(tx_byte), // Byte to transmit
.received(received), // Indicated that a byte has been received
.rx_byte(rx_byte), // Byte received
.is_receiving(is_receiving), // Low when receive line is idle
.is_transmitting(is_transmitting),// Low when transmit line is idle
.recv_error(recv_error) // Indicates error in receiving packet.
);
// input and output to be communicated
reg [31:0] vinput; // input and output are reserved keywords
reg [7:0] vcontrol; // Control byte, the MSB (most significant byte) of the transmission
reg [7:0] voutput;
reg [7:0] vcheck; // Checksum byte; the input bytes are summed and sent back as output
// We need to receive multiple bytes sequentially, so this sets up both
// reading and writing. Adapted from the uart-adder from
// https://github.com/cyrozap/iCEstick-UART-Demo/pull/3/files
parameter read_A = 1'd0;
parameter read_wait = 1'd1;
parameter write_A = 1'd0;
parameter write_done = 1'd1;
reg writestate = write_A;
reg [5:0] writecount = 0;
reg [1:0] readstate = read_A;
reg [5:0] readcount = 0;
parameter STATE_RECEIVING = 2'd0;
parameter STATE_CALCULATING = 2'd1;
parameter STATE_SENDING = 2'd2;
// These set the behavior based on the control byte
parameter CONT_SET_DELAY = 8'd0;
parameter CONT_SET_PERIOD = 8'd1;
parameter CONT_SET_PULSE1 = 8'd2;
parameter CONT_SET_PULSE2 = 8'd3;
parameter CONT_TOGGLE_PULSE1 = 8'd4;
parameter CONT_SET_CPMG = 8'd5;
parameter CONT_SET_ATT = 8'd6;
parameter CONT_SET_NUTW = 8'd7;
parameter CONT_SET_NUTD = 8'd8;
reg [2:0] state = STATE_RECEIVING;
// The communication runs at the 12 MHz clock rather than the 200 MHz clock.
always @(posedge clk) begin
case (state)
STATE_RECEIVING: begin
transmit <= 0;
case (readstate)
read_A: begin
if(received) begin
if(readcount == 6'd32) begin // Last byte in the transmission
vcontrol <= rx_byte;
state<=STATE_CALCULATING;
readcount <= 0;
readstate <= read_A;
end
else begin // Read the first bytes into vinput
vinput[readcount +: 8]=rx_byte;
readcount <= readcount + 8;
readstate <= read_wait;
end
end
end // case: read_A
read_wait: begin // Wait for the next byte to arrive
if(~received) begin
readstate <= read_A;
end
end
endcase // case (readstate)
end // case: STATE_RECEIVING
// Based on the control byte, assign a new value to the desired pulse parameter
STATE_CALCULATING: begin
writestate <= write_A;
voutput = vinput[31:24] + vinput[23:16] + vinput[15:8] + vinput[7:0];
case (vcontrol)
CONT_SET_DELAY: begin
delay <= vinput[15:0];
end
CONT_SET_PERIOD: begin
period <= vinput;
end
CONT_SET_PULSE1: begin
p1width <= vinput[15:0];
end
CONT_SET_PULSE2: begin
p2width <= vinput[15:0];
end
CONT_TOGGLE_PULSE1: begin
block <= vinput[1];
pulse_block <= vinput[15:8];
// pulse_block_off <= vinput[31:16];
end
CONT_SET_CPMG: begin
cpmg <= vinput[7:0];
end
CONT_SET_NUTD: begin
nut_del <= vinput[15:0];
end
CONT_SET_NUTW: begin
nut_wid <= vinput[7:0];
end
// CONT_SET_ATT: begin
// pre_att <= vinput[7:0];
// post_att <= vinput[15:8];
// end
endcase // case (vcontrol)
state <= STATE_SENDING;
end
STATE_SENDING: begin
case (writestate)
write_A: begin
rx_done = 1;
if (~ is_transmitting) begin
transmit <= 1;
writestate <= write_done;
tx_byte <= voutput;
state <= STATE_SENDING;
end
end
write_done: begin
rx_done = 0;
if (~ is_transmitting) begin
writestate <= write_A;
state <= STATE_RECEIVING;
transmit <= 0;
end
end
endcase
end
default: begin
// should not be reached
state <= STATE_RECEIVING;
readcount <= read_A;
end
endcase // case (state)
end // always @ (posedge iCE_CLK)
endmodule // pulse_control
|
#include <bits/stdc++.h> using namespace std; long long n, m, k; long long ans; int main() { cin >> n >> m >> k; if (k > n + m - 2) { cout << -1 << endl; return 0; } if (k > n - 1) { long long x = k; x -= (n - 1); ans = m / (x + 1); } else ans = n / (k + 1) * m; if (k > m - 1) { long long x = k; x -= (m - 1); ans = max(ans, (n / (x + 1))); } else ans = max(ans, (m / (k + 1) * n)); cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int a[51][51], b[51][51]; int main() { int n, m; cin >> n >> m; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { cin >> a[i][j]; } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { cin >> b[i][j]; if (a[i][j] > b[i][j]) { int temp; temp = a[i][j]; a[i][j] = b[i][j]; b[i][j] = temp; } } } for (int i = 1; i <= n; i++) { for (int j = 2; j <= m; j++) { if (a[i][j] <= a[i][j - 1] || b[i][j] <= b[i][j - 1]) { cout << Impossible << endl; return 0; } } } for (int j = 1; j <= m; j++) { for (int i = 2; i <= n; i++) { if (a[i][j] <= a[i - 1][j] || b[i][j] <= b[i - 1][j]) { cout << Impossible << endl; return 0; } } } cout << Possible << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int t; cin >> t; while (t--) { long long int a[3]; cin >> a[0] >> a[1] >> a[2]; sort(a, a + 3, greater<long long int>()); if (a[0] != a[1]) { cout << NO << n ; } else { cout << YES << n ; cout << a[0] << << a[2] << << a[2] << n ; } } } |
#include <bits/stdc++.h> const int maxn = 5e5 + 5; std::vector<std::pair<int, int>> G[maxn]; std::vector<std::tuple<int, int, int>> q[maxn]; int in[maxn], out[maxn], id[maxn], tot, n, m; long long dis[maxn], ans[maxn]; struct SegTree { long long sum[maxn << 2], lazy[maxn << 2]; void pushdown(int o) { if (lazy[o]) { sum[o << 1] += lazy[o]; sum[o << 1 | 1] += lazy[o]; lazy[o << 1] += lazy[o]; lazy[o << 1 | 1] += lazy[o]; lazy[o] = 0; } } void build(int o, int l, int r) { if (l == r) { sum[o] = dis[l]; return; } int m = (l + r) >> 1; build(o << 1, l, m); build(o << 1 | 1, m + 1, r); sum[o] = std::min(sum[o << 1], sum[o << 1 | 1]); } void update(int o, int l, int r, int ql, int qr, int val) { if (ql <= l && r <= qr) { sum[o] += val; lazy[o] += val; return; } int m = (l + r) >> 1; pushdown(o); if (ql <= m) update(o << 1, l, m, ql, qr, val); if (qr > m) update(o << 1 | 1, m + 1, r, ql, qr, val); sum[o] = std::min(sum[o << 1], sum[o << 1 | 1]); } long long query(int o, int l, int r, int ql, int qr) { if (ql <= l && r <= qr) { return sum[o]; } int m = (l + r) >> 1; long long ans = 0x3f3f3f3f3f3f3f3f; pushdown(o); if (ql <= m) ans = std::min(ans, query(o << 1, l, m, ql, qr)); if (qr > m) ans = std::min(ans, query(o << 1 | 1, m + 1, r, ql, qr)); return ans; } } st; void dfs1(int u, long long d) { in[u] = ++tot; for (auto &it : G[u]) dfs1(it.first, it.second + d); if (G[u].empty()) dis[u] = d; else dis[u] = 0x3f3f3f3f3f3f3f3f; out[u] = tot; } void dfs2(int u, long long d) { for (auto &it : q[u]) ans[std::get<2>(it)] = st.query(1, 1, n, std::get<0>(it), std::get<1>(it)) + d; for (auto &it : G[u]) { st.update(1, 1, n, in[it.first], out[it.first], -2 * it.second); dfs2(it.first, it.second + d); st.update(1, 1, n, in[it.first], out[it.first], 2 * it.second); } } int main() { scanf( %d%d , &n, &m); for (int i = 2; i <= n; i++) { int u, w; scanf( %d%d , &u, &w); G[u].emplace_back(i, w); } dfs1(1, 0); st.build(1, 1, n); for (int i = 1; i <= m; i++) { int v, l, r; scanf( %d%d%d , &v, &l, &r); q[v].emplace_back(l, r, i); } dfs2(1, 0); for (int i = 1; i <= m; i++) printf( %lld n , ans[i]); return 0; } |
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo_mixed_widths
// ============================================================
// File Name: rxlengthfifo_128x13.v
// Megafunction Name(s):
// dcfifo_mixed_widths
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 173 11/01/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module rxlengthfifo_128x13 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input aclr;
input [14:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [14:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire [14:0] sub_wire1;
wire sub_wire2;
wire wrfull = sub_wire0;
wire [14:0] q = sub_wire1[14:0];
wire rdempty = sub_wire2;
dcfifo_mixed_widths dcfifo_mixed_widths_component (
.rdclk (rdclk),
.wrclk (wrclk),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.wrfull (sub_wire0),
.q (sub_wire1),
.rdempty (sub_wire2),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrusedw ());
defparam
dcfifo_mixed_widths_component.intended_device_family = "Stratix IV",
dcfifo_mixed_widths_component.lpm_numwords = 512,
dcfifo_mixed_widths_component.lpm_showahead = "OFF",
dcfifo_mixed_widths_component.lpm_type = "dcfifo_mixed_widths",
dcfifo_mixed_widths_component.lpm_width = 15,
dcfifo_mixed_widths_component.lpm_widthu = 9,
dcfifo_mixed_widths_component.lpm_widthu_r = 9,
dcfifo_mixed_widths_component.lpm_width_r = 15,
dcfifo_mixed_widths_component.overflow_checking = "ON",
dcfifo_mixed_widths_component.rdsync_delaypipe = 4,
dcfifo_mixed_widths_component.underflow_checking = "ON",
dcfifo_mixed_widths_component.use_eab = "ON",
dcfifo_mixed_widths_component.write_aclr_synch = "OFF",
dcfifo_mixed_widths_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "512"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "15"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "1"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "15"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "15"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
// Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "9"
// Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "15"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 15 0 INPUT NODEFVAL "data[14..0]"
// Retrieval info: USED_PORT: q 0 0 15 0 OUTPUT NODEFVAL "q[14..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 15 0 data 0 0 15 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 15 0 @q 0 0 15 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL rxlengthfifo_128x13.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rxlengthfifo_128x13.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rxlengthfifo_128x13.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rxlengthfifo_128x13.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rxlengthfifo_128x13_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rxlengthfifo_128x13_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A31O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__A31O_BEHAVIORAL_PP_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__a31o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A31O_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; int n; struct hdm { int first, second, id; hdm(){}; hdm(int first, int second, int id) : first(first), second(second), id(id){}; }; vector<hdm> v1, v2; bool cmp1(hdm A, hdm B) { return (A.second < B.second); } bool cmp2(hdm A, hdm B) { return (A.first > B.first); } int main() { ios::sync_with_stdio(0); cin >> n; for (int i = 1; i <= n; i++) { int A, B; cin >> A >> B; pair<int, int> p = make_pair(A, B); if (A > B) { v1.push_back(hdm(A, B, i)); } else { v2.push_back(hdm(A, B, i)); } } sort(v1.begin(), v1.end(), cmp1); sort(v2.begin(), v2.end(), cmp2); int rs1 = (int)v1.size(); int rs2 = (int)v2.size(); if (rs1 >= rs2) { cout << rs1 << n ; for (int i = 0; i < v1.size(); i++) cout << v1[i].id << ; } else { cout << rs2 << n ; for (int i = 0; i < v2.size(); i++) cout << v2[i].id << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long powmod(long long a, long long b) { long long res = 1; a %= 1000000007; for (; b; b >>= 1) { if (b & 1) res = res * a % 1000000007; a = a * a % 1000000007; } return res; } template <typename T> inline bool chkmin(T &a, const T &b) { return a > b ? a = b, 1 : 0; } template <typename T> inline bool chkmax(T &a, const T &b) { return a < b ? a = b, 1 : 0; } int read() { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } int a[100005], n; const int mx = 30; long long m; struct trie_node { int num[30], siz, ch[2]; } t[100005 * 20]; const int head = 1; int tot = 1; void insert(int x) { int p = head; for (int i = mx - 1; i >= 0; i--) { int bit = x >> i & 1; if (!t[p].ch[bit]) t[p].ch[bit] = ++tot; p = t[p].ch[bit]; for (int i = 0; i < mx; i++) t[p].num[i] += x >> i & 1; t[p].siz++; } } int now[100005]; int num[30], all[30]; int main() { scanf( %d%lld , &n, &m); m <<= 1; for (int i = 1; i <= n; i++) scanf( %d , &a[i]), insert(a[i]); for (int i = 1; i <= n; i++) now[i] = head; memset(num, 0, sizeof num); for (int i = mx - 1; i >= 0; i--) { long long tmp = 0; for (int j = 1; j <= n; j++) tmp += t[t[now[j]].ch[!(a[j] >> i & 1)]].siz; if (tmp <= m) { for (int j = 1; j <= n; j++) { for (int k = mx - 1; k >= 0; k--) { if (a[j] >> k & 1) num[k] += t[t[now[j]].ch[!(a[j] >> i & 1)]].siz - t[t[now[j]].ch[!(a[j] >> i & 1)]].num[k]; else num[k] += t[t[now[j]].ch[!(a[j] >> i & 1)]].num[k]; } now[j] = t[now[j]].ch[a[j] >> i & 1]; } m -= tmp; } else { for (int j = 1; j <= n; j++) now[j] = t[now[j]].ch[!(a[j] >> i & 1)], all[i] = 1; } } for (int i = 0; i < mx; i++) num[i] += all[i] * m; long long ans = 0; for (int i = 0; i < mx; i++) { ans += (1LL << i) * (num[i] / 2); } ans %= 1000000007; printf( %lld n , ans); return 0; } |
///////////////////////////////////////////////////////
// Copyright (c) 2009 Xilinx Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 12.1
// \ \ Description :
// / /
// /__/ /\ Filename : BUFMRCE.v
// \ \ / \
// \__\/\__ \
//
// Revision: 1.0
// 05/24/12 - 661573 - Remove 100 ps delay
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module BUFMRCE #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter CE_TYPE = "SYNC",
parameter integer INIT_OUT = 0,
parameter [0:0] IS_CE_INVERTED = 1'b0
)(
output O,
input CE,
input I
);
wire NCE, o_bufg_o, o_bufg1_o;
reg CE_TYPE_BINARY;
reg INIT_OUT_BINARY;
reg IS_CE_INVERTED_BIN = IS_CE_INVERTED;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
wire O_OUT;
wire delay_CE;
wire delay_I;
initial begin
case (CE_TYPE)
"SYNC" : CE_TYPE_BINARY = 1'b0;
"ASYNC" : CE_TYPE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute CE_TYPE on BUFMRCE instance %m is set to %s. Legal values for this attribute are SYNC, or ASYNC.", CE_TYPE);
#1 $finish;
end
endcase
if ((INIT_OUT >= 0) && (INIT_OUT <= 1))
INIT_OUT_BINARY = INIT_OUT;
else begin
$display("Attribute Syntax Error : The Attribute INIT_OUT on BUFMRCE instance %m is set to %d. Legal values for this attribute are 0 to 1.", INIT_OUT);
#1 $finish;
end
end
BUFGCTRL #(.INIT_OUT(1'b0), .PRESELECT_I0("TRUE"), .PRESELECT_I1("FALSE")) B1
(.O(o_bufg_o), .CE0(~NCE), .CE1(NCE), .I0(delay_I), .I1(1'b0), .IGNORE0(1'b0), .IGNORE1(1'b0), .S0(1'b1), .S1(1'b1));
INV I1 (.I(delay_CE ^ IS_CE_INVERTED_BIN), .O(NCE));
BUFGCTRL #(.INIT_OUT(1'b1), .PRESELECT_I0("TRUE"), .PRESELECT_I1("FALSE")) B2
(.O(o_bufg1_o), .CE0(~NCE), .CE1(NCE), .I0(delay_I), .I1(1'b1), .IGNORE0(1'b0), .IGNORE1(1'b0), .S0(1'b1), .S1(1'b1));
assign O = (INIT_OUT == 1) ? o_bufg1_o : o_bufg_o;
`ifndef XIL_TIMING
assign delay_I = I;
assign delay_CE = CE;
`endif
specify
( I => O) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING
$period (posedge I, 0:0:0, notifier);
$setuphold (negedge I, negedge CE, 0:0:0, 0:0:0, notifier,,, delay_I, delay_CE);
$setuphold (negedge I, posedge CE, 0:0:0, 0:0:0, notifier,,, delay_I, delay_CE);
$setuphold (posedge I, negedge CE, 0:0:0, 0:0:0, notifier,,, delay_I, delay_CE);
$setuphold (posedge I, posedge CE, 0:0:0, 0:0:0, notifier,,, delay_I, delay_CE);
`endif // `ifdef XIL_TIMING
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
#include <bits/stdc++.h> #pragma GCC optimize(3) #pragma GCC optimize(2) using namespace std; int n, r; bool dp[666][666]; int fang[666][666]; pair<int, int> ku[666]; void dfs(int x, int y) { if (x == y) cout << () ; else if (fang[x][y] == -1) { cout << ( ; dfs(x + 1, y); cout << ) ; } else { dfs(x, fang[x][y]); dfs(fang[x][y] + 1, y); } } signed main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); memset(dp, 0, sizeof dp); cin >> n; for (register int i = 1; (1 < n) ? (i <= n) : (i >= n); i += (1 < n) ? 1 : (-1)) cin >> ku[i].first >> ku[i].second; for (register int i = 1; (1 < n) ? (i <= n) : (i >= n); i += (1 < n) ? 1 : (-1)) dp[i][i] = (bool)(ku[i].first == 1); for (register int i = 2; (2 < n) ? (i <= n) : (i >= n); i += (2 < n) ? 1 : (-1)) { for (register int l = 1; (1 < n - i + 1) ? (l <= n - i + 1) : (l >= n - i + 1); l += (1 < n - i + 1) ? 1 : (-1)) { r = l + i - 1; if (dp[l + 1][r] && ku[l].first - 1 <= (r - l) * 2 && (r - l) * 2 <= ku[l].second - 1) { dp[l][r] = 1; fang[l][r] = -1; } else { for (register int k = l; (l < r - 1) ? (k <= r - 1) : (k >= r - 1); k += (l < r - 1) ? 1 : (-1)) { if (dp[l][k] && dp[k + 1][r]) { dp[l][r] = 1; fang[l][r] = k; break; } } } } } if (dp[1][n]) { dfs(1, n); cout << endl; } else cout << IMPOSSIBLE << endl; return 0; } |
#include <bits/stdc++.h> char *fs, *ft, buf[1 << 20]; inline int read() { int x = 0, f = 1; char ch = (fs == ft && (ft = (fs = buf) + fread(buf, 1, 1 << 20, stdin), fs == ft)) ? 0 : *fs++; ; while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = (fs == ft && (ft = (fs = buf) + fread(buf, 1, 1 << 20, stdin), fs == ft)) ? 0 : *fs++; ; } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = (fs == ft && (ft = (fs = buf) + fread(buf, 1, 1 << 20, stdin), fs == ft)) ? 0 : *fs++; ; } return x * f; } using namespace std; int a[1009]; int main() { int t; cin >> t; while (t--) { int n; int z0 = 0, z1 = 0, bo = 0; cin >> n; cin >> a[1]; for (int i = 2; i <= n; i++) { cin >> a[i]; if (a[i] < a[i - 1]) bo = 1; } for (int i = 1; i <= n; i++) { int k; cin >> k; if (k == 0) z0++; else z1++; } if (bo == 0) { cout << Yes << endl; continue; } else { if (z0 == 0 || z1 == 0) cout << No << endl; else cout << Yes << endl; } } return 0; } |
module DoubleRegisters(
clk,
bus_in, bus_out1, bus_out2,
num1, num2,
cs_h_in, cs_l_in, cs_16_in,
cs_h_out1, cs_l_out1, cs_16_out1,
cs_h_out2, cs_l_out2, cs_16_out2);
input [15:0] bus_in;
output reg [15:0] bus_out1, bus_out2;
input [1:0] num1, num2;
input cs_h_in, cs_l_in, cs_16_in;
input cs_h_out1, cs_l_out1, cs_16_out1;
input cs_h_out2, cs_l_out2, cs_16_out2;
input clk;
(* ram_style="block" *)
reg [7:0] store_h[3:0] /* verilator public_flat */;
(* ram_style="block" *)
reg [7:0] store_l[3:0] /* verilator public_flat */;
always @ (posedge clk)
if (cs_h_out1)
bus_out1 <= {8'h00, store_h[num1]};
else if (cs_l_out1)
bus_out1 <= {8'h00, store_l[num1]};
else if (cs_16_out1)
bus_out1 <= {store_h[num1], store_l[num1]};
else
bus_out1 <= 16'bz;
always @ (posedge clk)
if (cs_h_out2)
bus_out2 <= {8'h00, store_h[num2]};
else if (cs_l_out2)
bus_out2 <= {8'h00, store_l[num2]};
else if (cs_16_out2)
bus_out2 <= {store_h[num2], store_l[num2]};
else
bus_out2 <= 16'bz;
always @(posedge clk)
if (cs_h_in)
store_h[num1] <= bus_in[7:0];
else if (cs_16_in) begin
store_h[num1] <= bus_in[15:8];
end
always @(posedge clk)
if (cs_l_in)
store_l[num1] <= bus_in[7:0];
else if (cs_16_in) begin
store_l[num1] <= bus_in[7:0];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; const long long INF = 1e9 + 9; const long long N = 500500; char s[4][4]; long long dot, cross, nought, first_wins, second_wins; long long first_win_rows, first_win_col, second_win_row, second_win_col; long long total; signed main() { ios_base::sync_with_stdio(false); cin.tie(0); for (long long i = 1; i <= 3; i++) { for (long long j = 1; j <= 3; j++) { cin >> s[i][j]; if (s[i][j] == . ) dot++; if (s[i][j] == X ) cross++; if (s[i][j] == 0 ) nought++; } } total += cross + nought; if (!(cross == nought || cross == nought + 1)) { cout << illegal ; return 0; } for (long long i = 1; i <= 3; i++) { set<char> st; for (long long j = 1; j <= 3; j++) { st.insert(s[i][j]); } if (st.size() == 1 && *st.begin() == X ) { first_wins++; } if (st.size() == 1 && *st.begin() == 0 ) { second_wins++; } } for (long long j = 1; j <= 3; j++) { set<char> st; for (long long i = 1; i <= 3; i++) { st.insert(s[i][j]); } if (st.size() == 1 && *st.begin() == X ) { first_wins++; } if (st.size() == 1 && *st.begin() == 0 ) { second_wins++; } } set<char> st; st.insert(s[1][1]); st.insert(s[2][2]); st.insert(s[3][3]); if (st.size() == 1 && *st.begin() == X ) { first_wins++; } if (st.size() == 1 && *st.begin() == 0 ) { second_wins++; } st.clear(); st.insert(s[1][3]); st.insert(s[2][2]); st.insert(s[3][1]); if (st.size() == 1 && *st.begin() == X ) { first_wins++; } if (st.size() == 1 && *st.begin() == 0 ) { second_wins++; } if (first_wins > 0 && second_wins > 0) { cout << illegal ; return 0; } if (first_wins > 0 || second_wins > 0) { if (first_wins == 1 && total & 1) { cout << the first player won ; } else if (second_wins == 1 && total % 2 == 0) { cout << the second player won ; } else if (first_wins == 2 && total & 1) { if (first_win_col == 2 || first_win_rows == 2) { cout << illegal ; } else { cout << the first player won ; } } else if (second_wins == 2 && total % 2 == 0) { if (second_win_col == 2 || second_win_row == 2) { cout << illegal ; } else { cout << the second player won ; } } else { cout << illegal ; } return 0; } if (dot > 0) { if (cross == nought) cout << first ; else cout << second ; } else { cout << draw ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 3e5 + 10; int N; int A[MAXN]; int B[MAXN]; int ans[MAXN]; bool is_permutation() { sort(B + 1, B + 1 + N); for (int i = 1; i <= N; ++i) if (B[i] != i) return false; return true; } void solve(bool has_one) { for (int i = 1; i <= N; ++i) ans[i] = 0; if (!has_one) return; map<int, int> freq; for (int i = 1; i <= N; ++i) ++freq[A[i]]; int L = 1; int R = N; int cur; for (cur = 1; cur <= N; ++cur) { if (freq[cur] != 1) break; if (A[L] == cur) ++L; else if (A[R] == cur) --R; else break; } if (is_permutation()) ans[1] = 1; if (L > R) { for (int k = 2; k <= N; ++k) ans[k] = 1; return; } int len = R - L + 1; if (!freq[cur]) ++len; for (int k = len; k <= N; ++k) ans[k] = 1; } int main() { cin.sync_with_stdio(false); cin.tie(0); int t; cin >> t; while (t--) { cin >> N; bool has_one = false; for (int i = 1; i <= N; ++i) { cin >> A[i]; B[i] = A[i]; if (A[i] == 1) has_one = true; } solve(has_one); for (int i = 1; i <= N; ++i) cout << ans[i]; cout << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m; int l[200000], r[200000], p[200001]; vector<int> beg[200001], ed[200001]; map<unsigned long long, unsigned long long> cnt, sum; unsigned long long h[200000], all; mt19937_64 mt(time(0)); int main() { scanf( %d%d , &n, &m); all = 0; for (int i = 0; i < (int)(n); ++i) { scanf( %d%d , l + i, r + i); --l[i], --r[i]; ++p[l[i]]; --p[r[i] + 1]; beg[l[i]].push_back(i); ed[r[i] + 1].push_back(i); h[i] = mt(); all ^= h[i]; } unsigned long long mask = 0, bmask = all, emask = 0, change = 0, ans = 0; for (int i = 0; i < (int)(m + 1); ++i) { for (int x : ed[i]) { emask ^= h[x]; } mask ^= change; ans += cnt[mask ^ all ^ bmask] * i - sum[mask ^ all ^ bmask]; ++cnt[mask ^ emask]; sum[mask ^ emask] += i; for (int x : beg[i]) { change ^= h[x]; bmask ^= h[x]; } for (int x : ed[i]) { change ^= h[x]; } } int t = 0, c = 0; for (int i = 0; i < (int)(m); ++i) { t += p[i]; if (t > 0) { c = 0; } else { ++c; ans -= (unsigned long long)c * (c + 1) / 2; } } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 200005; int a[maxn]; int main() { int n; scanf( %d , &n); for (int i = 0; i < n * 2; i++) scanf( %d , &a[i]); sort(a, a + n * 2); long long area = 1ll * (a[n - 1] - a[0]) * (a[n * 2 - 1] - a[n]); for (int i = 1; i < n; i++) { area = min(area, 1ll * (a[i + n - 1] - a[i]) * (a[n * 2 - 1] - a[0])); } printf( %I64d , area); return 0; } |
// ==================================================================
// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ------------------------------------------------------------------
// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// ------------------------------------------------------------------
//
// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
//
// Permission:
//
// Lattice Semiconductor grants permission to use this code
// pursuant to the terms of the Lattice Semiconductor Corporation
// Open Source License Agreement.
//
// Disclaimer:
//
// Lattice Semiconductor provides no warranty regarding the use or
// functionality of this code. It is the user's responsibility to
// verify the users design for consistency and functionality through
// the use of formal verification methods.
//
// --------------------------------------------------------------------
//
// Lattice Semiconductor Corporation
// 5555 NE Moore Court
// Hillsboro, OR 97214
// U.S.A
//
// TEL: 1-800-Lattice (USA and Canada)
// (other locations)
//
// web: http://www.latticesemi.com/
// email:
//
// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_multiplier.v
// Title : Pipelined multiplier.
// Dependencies : lm32_include.v
// Version : 6.1.17
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : No Change
// =============================================================================
`include "lm32_include.v"
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module lm32_multiplier (
// ----- Inputs -----
clk_i,
rst_i,
stall_x,
stall_m,
operand_0,
operand_1,
// ----- Ouputs -----
result
);
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input clk_i; // Clock
input rst_i; // Reset
input stall_x; // Stall instruction in X stage
input stall_m; // Stall instruction in M stage
input [`LM32_WORD_RNG] operand_0; // Muliplicand
input [`LM32_WORD_RNG] operand_1; // Multiplier
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
output [`LM32_WORD_RNG] result; // Product of multiplication
reg [`LM32_WORD_RNG] result;
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
reg [`LM32_WORD_RNG] muliplicand;
reg [`LM32_WORD_RNG] multiplier;
reg [`LM32_WORD_RNG] product;
/////////////////////////////////////////////////////
// Sequential logic
/////////////////////////////////////////////////////
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
muliplicand <= #1 {`LM32_WORD_WIDTH{1'b0}};
multiplier <= #1 {`LM32_WORD_WIDTH{1'b0}};
product <= #1 {`LM32_WORD_WIDTH{1'b0}};
result <= #1 {`LM32_WORD_WIDTH{1'b0}};
end
else
begin
if (stall_x == `FALSE)
begin
muliplicand <= #1 operand_0;
multiplier <= #1 operand_1;
end
if (stall_m == `FALSE)
product <= #1 muliplicand * multiplier;
result <= #1 product;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 3e5 + 6; namespace AC { int tot, tr[N][26]; int fail[N]; int cnt[N]; int sid[N]; int next[N]; bool vis[N]; int isend[N]; int in[N]; int val[N]; int victim[N]; queue<int> q; void init() { memset(fail, 0, sizeof(fail)); memset(tr, 0, sizeof(tr)); memset(cnt, 0, sizeof(cnt)); memset(vis, false, sizeof vis); memset(sid, 0, sizeof sid); memset(val, 0, sizeof val); memset(isend, 0, sizeof isend); memset(victim, 0, sizeof victim); memset(next, 0, sizeof next); tot = 0; } void insert(char *s, int id) { int u = 0; for (int i = 1; s[i]; i++) { if (!tr[u][s[i] - a ]) tr[u][s[i] - a ] = ++tot; u = tr[u][s[i] - a ]; } sid[id] = u; isend[u] = true; } void build() { next[0] = 0; for (int i = 0; i < 26; i++) if (tr[0][i]) q.push(tr[0][i]); while (q.size()) { int u = q.front(); q.pop(); for (int i = 0; i < 26; i++) { if (tr[u][i]) { fail[tr[u][i]] = tr[fail[u]][i], q.push(tr[u][i]); in[fail[tr[u][i]]] += 1; } else tr[u][i] = tr[fail[u]][i]; next[tr[u][i]] = isend[fail[tr[u][i]]] ? fail[tr[u][i]] : next[fail[tr[u][i]]]; } } } int query(char *t) { int u = 0, res = -1; for (int i = 1; t[i]; i++) { u = tr[u][t[i] - a ]; for (int x = u; x; x = next[x]) { if (isend[x]) { res = max(res, victim[x]); } } } return res; } void query(char *t, int) { int u = 0; for (int i = 1; t[i]; i++) { u = tr[u][t[i] - a ]; val[u] += 1; } } void topoSort() { for (int i = 0; i < N; ++i) if (in[i] == 0) q.push(i); while (!q.empty()) { int u = q.front(); q.pop(); int v = fail[u]; in[v]--; val[v] += val[u]; if (in[v] == 0) q.push(v); } } } // namespace AC char s[N]; int val[N]; map<int, int> mp[N]; int main() { int ans = 0; int n, m; cin >> n >> m; AC::init(); for (int i = 0; i < n; i++) { scanf( %s , s + 1); AC::insert(s, i); mp[AC::sid[i]][0] += 1; } AC::build(); while (m--) { int x, c, v; scanf( %d , &x); if (x == 1) { scanf( %d %d , &c, &v); mp[AC::sid[c - 1]][val[c - 1]] -= 1; if (mp[AC::sid[c - 1]][val[c - 1]] == 0) { mp[AC::sid[c - 1]].erase(val[c - 1]); } val[c - 1] = v; mp[AC::sid[c - 1]][v] += 1; AC::victim[AC::sid[c - 1]] = (*--mp[AC::sid[c - 1]].end()).first; continue; } scanf( %s , s + 1); cout << AC::query(s) << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 3e5 + 123; const int mod = 1e9 + 9; int n; long long k, d; int a[maxn]; int m; int L[maxn]; long long t[maxn * 4]; long long ad[maxn * 4]; void build(int v, int l, int r) { ad[v] = 0; t[v] = 0; if (l == r) { } else { int mid = (l + r) / 2; build(v * 2, l, mid); build(v * 2 + 1, mid + 1, r); } } void push(int v, int tl, int tr) { if (tl == tr) return; t[v * 2] += ad[v]; t[v * 2 + 1] += ad[v]; ad[v * 2] += ad[v]; ad[v * 2 + 1] += ad[v]; ad[v] = 0; } int get(int v, int tl, int tr, int l, int r, long long k) { push(v, tl, tr); if (tl > r || l > tr) { return -1; } if (t[v] > k) { return -1; } if (tl == tr) { return tl; } int mid = (tl + tr) / 2; int res = get(v * 2, tl, mid, l, r, k); if (res != -1) return res; return get(v * 2 + 1, mid + 1, tr, l, r, k); } void add(int v, int tl, int tr, int l, int r, long long d) { push(v, tl, tr); if (tl > r || l > tr) { return; } if (l <= tl && tr <= r) { t[v] += d; ad[v] += d; return; } int mid = (tl + tr) / 2; add(v * 2, tl, mid, l, r, d); add(v * 2 + 1, mid + 1, tr, l, r, d); t[v] = min(t[v * 2], t[v * 2 + 1]); } pair<int, int> calc(vector<int> b) { m = b.size(); map<int, int> c; for (int i = 0; i < m; i++) { if (c.count(b[i]) == 0) { L[i] = 0; } else { L[i] = c[b[i]] + 1; } c[b[i]] = i; } for (int i = 1; i < m; i++) { L[i] = max(L[i], L[i - 1]); } build(1, 0, m - 1); vector<int> mx; vector<int> mi; pair<int, int> ans = make_pair(0, 0); for (int i = 0; i < m; i++) { while (mx.size() > 0 && b[mx.back()] < b[i]) { int cur = mx.back(); mx.pop_back(); if (mx.size() > 0) { add(1, 0, m - 1, mx.back() + 1, cur, -b[cur]); } else { add(1, 0, m - 1, 0, cur, -b[cur]); } } if (mx.size() > 0) { add(1, 0, m - 1, mx.back() + 1, i, b[i]); } else { add(1, 0, m - 1, 0, i, b[i]); } mx.push_back(i); while (mi.size() > 0 && b[mi.back()] > b[i]) { int cur = mi.back(); mi.pop_back(); if (mi.size() > 0) { add(1, 0, m - 1, mi.back() + 1, cur, b[cur]); } else { add(1, 0, m - 1, 0, cur, b[cur]); } } if (mi.size() > 0) { add(1, 0, m - 1, mi.back() + 1, i, -b[i]); } else { add(1, 0, m - 1, 0, i, -b[i]); } mi.push_back(i); int cnt = i - get(1, 0, m - 1, L[i], i, k) + 1; if (ans.first < cnt) { ans.first = cnt; ans.second = i; } add(1, 0, m - 1, 0, i, -1); } return ans; } void solve() { cin >> n >> k >> d; for (int i = 0; i < n; i++) { cin >> a[i]; } int mi = *min_element(a, a + n); for (int i = 0; i < n; i++) { a[i] -= mi; } pair<int, int> ans = make_pair(0, 0); if (d == 0) { int cnt = 1; for (int i = 1; i < n; i++) { if (a[i] != a[i - 1]) { if (ans.first < cnt) { ans.first = cnt; ans.second = i - 1; } cnt = 1; } else { cnt++; } } if (ans.first < cnt) { ans.first = cnt; ans.second = n - 1; } cout << ans.second - ans.first + 2 << << ans.second + 1 << n ; return; } for (int i = 0; i < n;) { int j = i; vector<int> cur; while (i < n && a[j] % d == a[i] % d) { cur.push_back(a[i] / d); i++; } pair<int, int> res = calc(cur); res.second += j; if (res.first > ans.first) { ans = res; } } cout << ans.second - ans.first + 2 << << ans.second + 1 << n ; } int main() { int t = 1; for (int i = 1; i <= t; i++) { solve(); } return 0; } |
/*
-- ============================================================================
-- FILE NAME : id_reg.v
-- DESCRIPTION : ID¥¹¥Æ©`¥¸¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito ÐÂÒ×÷³É
-- ============================================================================
*/
/********** ¹²Í¨¥Ø¥Ã¥À¥Õ¥¡¥¤¥ë **********/
`include "nettype.h"
`include "global_config.h"
`include "stddef.h"
/********** e¥Ø¥Ã¥À¥Õ¥¡¥¤¥ë **********/
`include "isa.h"
`include "cpu.h"
/********** ¥â¥¸¥å©`¥ë **********/
module id_reg (
/********** ¥¯¥í¥Ã¥¯ & ¥ê¥»¥Ã¥È **********/
input wire clk, // ¥¯¥í¥Ã¥¯
input wire reset, // ·ÇͬÆڥꥻ¥Ã¥È
/********** ¥Ç¥³©`¥É½Y¹û **********/
input wire [`AluOpBus] alu_op, // ALU¥ª¥Ú¥ì©`¥·¥ç¥ó
input wire [`WordDataBus] alu_in_0, // ALUÈëÁ¦ 0
input wire [`WordDataBus] alu_in_1, // ALUÈëÁ¦ 1
input wire br_flag, // ·Ö᪥ե饰
input wire [`MemOpBus] mem_op, // ¥á¥â¥ê¥ª¥Ú¥ì©`¥·¥ç¥ó
input wire [`WordDataBus] mem_wr_data, // ¥á¥â¥êø¤Þz¤ß¥Ç©`¥¿
input wire [`CtrlOpBus] ctrl_op, // ÖÆÓù¥ª¥Ú¥ì©`¥·¥ç¥ó
input wire [`RegAddrBus] dst_addr, // øÓå쥸¥¹¥¿ø¤Þz¤ß¥¢¥É¥ì¥¹
input wire gpr_we_, // øÓå쥸¥¹¥¿ø¤Þz¤ßÓп
input wire [`IsaExpBus] exp_code, // ÀýÍ⥳©`¥É
/********** ¥Ñ¥¤¥×¥é¥¤¥óÖÆÓùÐźŠ**********/
input wire stall, // ¥¹¥È©`¥ë
input wire flush, // ¥Õ¥é¥Ã¥·¥å
/********** IF/ID¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
input wire [`WordAddrBus] if_pc, // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
input wire if_en, // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
/********** ID/EX¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
output reg [`WordAddrBus] id_pc, // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
output reg id_en, // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
output reg [`AluOpBus] id_alu_op, // ALU¥ª¥Ú¥ì©`¥·¥ç¥ó
output reg [`WordDataBus] id_alu_in_0, // ALUÈëÁ¦ 0
output reg [`WordDataBus] id_alu_in_1, // ALUÈëÁ¦ 1
output reg id_br_flag, // ·Ö᪥ե饰
output reg [`MemOpBus] id_mem_op, // ¥á¥â¥ê¥ª¥Ú¥ì©`¥·¥ç¥ó
output reg [`WordDataBus] id_mem_wr_data, // ¥á¥â¥êø¤Þz¤ß¥Ç©`¥¿
output reg [`CtrlOpBus] id_ctrl_op, // ÖÆÓù¥ª¥Ú¥ì©`¥·¥ç¥ó
output reg [`RegAddrBus] id_dst_addr, // øÓå쥸¥¹¥¿ø¤Þz¤ß¥¢¥É¥ì¥¹
output reg id_gpr_we_, // øÓå쥸¥¹¥¿ø¤Þz¤ßÓп
output reg [`IsaExpBus] id_exp_code // ÀýÍ⥳©`¥É
);
/********** ¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
always @(posedge clk or `RESET_EDGE reset) begin
if (reset == `RESET_ENABLE) begin
/* ·ÇͬÆڥꥻ¥Ã¥È */
id_pc <= #1 `WORD_ADDR_W'h0;
id_en <= #1 `DISABLE;
id_alu_op <= #1 `ALU_OP_NOP;
id_alu_in_0 <= #1 `WORD_DATA_W'h0;
id_alu_in_1 <= #1 `WORD_DATA_W'h0;
id_br_flag <= #1 `DISABLE;
id_mem_op <= #1 `MEM_OP_NOP;
id_mem_wr_data <= #1 `WORD_DATA_W'h0;
id_ctrl_op <= #1 `CTRL_OP_NOP;
id_dst_addr <= #1 `REG_ADDR_W'd0;
id_gpr_we_ <= #1 `DISABLE_;
id_exp_code <= #1 `ISA_EXP_NO_EXP;
end else begin
/* ¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿¤Î¸üР*/
if (stall == `DISABLE) begin
if (flush == `ENABLE) begin // ¥Õ¥é¥Ã¥·¥å
id_pc <= #1 `WORD_ADDR_W'h0;
id_en <= #1 `DISABLE;
id_alu_op <= #1 `ALU_OP_NOP;
id_alu_in_0 <= #1 `WORD_DATA_W'h0;
id_alu_in_1 <= #1 `WORD_DATA_W'h0;
id_br_flag <= #1 `DISABLE;
id_mem_op <= #1 `MEM_OP_NOP;
id_mem_wr_data <= #1 `WORD_DATA_W'h0;
id_ctrl_op <= #1 `CTRL_OP_NOP;
id_dst_addr <= #1 `REG_ADDR_W'd0;
id_gpr_we_ <= #1 `DISABLE_;
id_exp_code <= #1 `ISA_EXP_NO_EXP;
end else begin // ´Î¤Î¥Ç©`¥¿
id_pc <= #1 if_pc;
id_en <= #1 if_en;
id_alu_op <= #1 alu_op;
id_alu_in_0 <= #1 alu_in_0;
id_alu_in_1 <= #1 alu_in_1;
id_br_flag <= #1 br_flag;
id_mem_op <= #1 mem_op;
id_mem_wr_data <= #1 mem_wr_data;
id_ctrl_op <= #1 ctrl_op;
id_dst_addr <= #1 dst_addr;
id_gpr_we_ <= #1 gpr_we_;
id_exp_code <= #1 exp_code;
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const double pi = acos(-1.0); const long long MAX = 2e9 + 7; const long long mod = 1e9 + 7; const long long maxn = 1e3 + 7; int n; string s[maxn]; set<string> ss; int jude(string s) { set<char> q; int a = s.size(); for (int i = 0; i < s.size(); i++) q.insert(s[i]); if (q.size() == a) return 1; else return 0; } int main() { cin >> n; int k = 0; for (int i = 0; i < n; i++) { cin >> s[i]; sort(s[i].begin(), s[i].end()); s[i].erase(unique(s[i].begin(), s[i].end()), s[i].end()); int flag = 1; if (jude(s[i])) ss.insert(s[i]); } cout << ss.size() << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; struct point{ public: int x, y; }; bool cmpx(point a, point b){ return a.x<b.x; } bool cmpy(point a, point b){ return a.y<b.y; } int main(){ int t, i, j, x1, x2, y1, y2, d; point ptsx[4], ptsy[4]; cin>>t; for(j=0; j<t; j++){ for(i=0; i<4; i++) cin>>ptsx[i].x>>ptsx[i].y; sort(ptsx, ptsx+4, cmpx); for(i=0; i<4; i++) ptsy[i]=ptsx[i]; sort(ptsy, ptsy+4, cmpy); x1=ptsx[1].x; x2=ptsx[2].x; y1=ptsy[1].y; y2=ptsy[2].y; if(x2-x1>=y2-y1){ d=x2-x1-y2+y1; y2=min(y2+d, ptsy[3].y); d=x2-x1-y2+y1; y1-=d; cout<<x1-ptsx[0].x+ptsx[3].x-x2+min(abs(ptsx[0].y-y1)+abs(ptsx[1].y-y2), abs(ptsx[0].y-y2)+abs(ptsx[1].y-y1))+min(abs(ptsx[2].y-y1)+abs(ptsx[3].y-y2), abs(ptsx[2].y-y2)+abs(ptsx[3].y-y1))<<endl; } else{ d=y2-y1-x2+x1; x2=min(x2+d, ptsx[3].x); d=y2-y1-x2+x1; x1-=d; cout<<y1-ptsy[0].y+ptsy[3].y-y2+min(abs(ptsy[0].x-x1)+abs(ptsy[1].x-x2), abs(ptsy[0].x-x2)+abs(ptsy[1].x-x1))+min(abs(ptsy[2].x-x1)+abs(ptsy[3].x-x2), abs(ptsy[2].x-x2)+abs(ptsy[3].x-x1))<<endl; } } } |
#include <bits/stdc++.h> using namespace std; long long N, L, W; vector<long long> neg, pos; long long INF32 = 0x7fffffff; inline long long div_floor(long long a, long long b) { if (b == 0) return (a > 0 ? +INF32 : -INF32); if (a % b < 0) a -= (b + a % b); return a / b; } int main() { cin >> N >> L >> W; for (int i = 0; i < N; ++i) { long long x, d; cin >> x >> d; (d == 1 ? pos : neg).push_back(d == 1 ? x : x + L); } sort(pos.begin(), pos.end()); sort(neg.begin(), neg.end()); long long ans = 0; for (auto x : pos) { long long lval = max(-x - 1, x); if (W == 1) { if (x < 0) { } else { lval = INF32; } } else { lval = max(lval, div_floor(((W + 1) * x), (W - 1))); } auto l = upper_bound(neg.begin(), neg.end(), lval); ans += int(neg.end() - l); lval = max(x, div_floor((W - 1) * x, (W + 1))); long long rval = -x; l = upper_bound(neg.begin(), neg.end(), lval); auto r = lower_bound(neg.begin(), neg.end(), rval); ans += max(0, int(r - l)); } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, Q; set<int> cut[2]; map<int, int> mx[2]; long long getmx() { map<int, int>::iterator it; it = mx[0].end(); it--; int u = (*it).first; it = mx[1].end(); it--; int v = (*it).first; return 1ll * u * v; } void Insert(int t, int x) { int u, v; set<int>::iterator it = cut[t].lower_bound(x); v = *it; it--; u = *it; mx[t][v - u]--; if (mx[t][v - u] == 0) mx[t].erase(v - u); cut[t].insert(x); mx[t][x - u]++; mx[t][v - x]++; } int main() { char t; int x; scanf( %d %d %d , &n, &m, &Q); cut[0].insert(0); cut[0].insert(n); mx[0][n]++; cut[1].insert(0); cut[1].insert(m); mx[1][m]++; for (int i = 1; i <= Q; i++) { scanf( %c %d , &t, &x); if (t == V ) Insert(0, x); if (t == H ) Insert(1, x); printf( %I64d n , getmx()); } return 0; } |
#include <bits/stdc++.h> using namespace std; long long j, k, s, l, m, n, t, d; long long e[111][33333], a, b, i, p, c; map<string, long long> y; string q, r, w; int main() { cin >> n >> a >> b >> c; n *= 2; for (i = 0; i <= a; i++) { for (j = 0; j <= b; j++) { k = n - i - 2 * j; if (k % 4 == 0 && k / 4 <= c && k >= 0) s++; } } cout << s; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_NSR_PP_PG_TB_V
`define SKY130_FD_SC_HS__UDP_DFF_NSR_PP_PG_TB_V
/**
* udp_dff$NSR_pp$PG: Negative edge triggered D flip-flop
* (Q output UDP) with both active high reset and
* set (set dominate). Includes VPWR and VGND power
* pins.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__udp_dff_nsr_pp_pg.v"
module top();
// Inputs are registered
reg SET;
reg RESET;
reg D;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET = 1'bX;
SET = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET = 1'b0;
#60 SET = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 RESET = 1'b1;
#160 SET = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 RESET = 1'b0;
#260 SET = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 SET = 1'b1;
#380 RESET = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 SET = 1'bx;
#480 RESET = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg CLK_N;
initial
begin
CLK_N = 1'b0;
end
always
begin
#5 CLK_N = ~CLK_N;
end
sky130_fd_sc_hs__udp_dff$NSR_pp$PG dut (.SET(SET), .RESET(RESET), .D(D), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK_N(CLK_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_NSR_PP_PG_TB_V
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:256000000 ) using namespace std; const int maxN = 2000; const int S_CNT = 9; const int M_CNT = 25; const int DIST = 60 * 60; int n, m; int a[maxN][maxN]; int t[maxN][maxN]; int used[maxN][maxN]; int rc[maxN][maxN]; int is_in(int x, int y) { return x >= 0 && x < n && y >= 0 && y < m; } int get(int x, int y) { int cnt = 0; for (int i = x - 2; i <= x + 2; ++i) { for (int j = y - 2; j <= y + 2; ++j) { if (is_in(i, j)) { cnt += a[i][j]; } } } return cnt; } pair<int, int> choose_max(int x, int y) { pair<int, int> res = make_pair(-1, -1); int rs = -1; for (int i = x - 2; i <= x + 2; ++i) { for (int j = y - 2; j <= y + 2; ++j) { if (is_in(i, j)) { if (t[i][j] > rs) { rs = t[i][j]; res = make_pair(i, j); } } } } return res; } void change_used(int x, int y, int num) { for (int i = x - 2; i <= x + 2; ++i) { for (int j = y - 2; j <= y + 2; ++j) { if (is_in(i, j)) { used[i][j] = num; } } } } int dist(pair<int, int> a, pair<int, int> b) { return (a.first - b.first) * (a.first - b.first) + (a.second - b.second) * (a.second - b.second); } pair<int, int> choose_long(int cx, int cy, int x, int y, int step) { pair<int, int> res = make_pair(cx, cy); int rs = -1; for (int i = cx - 2; i <= cx + 2; ++i) { for (int j = cy - 2; j <= cy + 2; ++j) { if (is_in(i, j) && a[i][j] && used[i][j] != step) { if (dist(make_pair(i, j), make_pair(x, y)) > rs) { rs = dist(make_pair(i, j), make_pair(x, y)); res = make_pair(i, j); } } } } return res; } void dfs(int x, int y, int color) { if (rc[x][y] != 0) return; rc[x][y] = color; if (is_in(x + 1, y) && a[x + 1][y]) dfs(x + 1, y, color); if (is_in(x - 1, y) && a[x - 1][y]) dfs(x - 1, y, color); if (is_in(x, y + 1) && a[x][y + 1]) dfs(x, y + 1, color); if (is_in(x, y - 1) && a[x][y - 1]) dfs(x, y - 1, color); } int main() { scanf( %d%d , &n, &m); for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { scanf( %d , &a[i][j]); } } int c_col = 0; for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { if (a[i][j] && !rc[i][j]) { ++c_col; dfs(i, j, c_col); } } } for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { if (a[i][j]) { t[i][j] = get(i, j); } } } vector<pair<int, int> > cur; int step = 1; for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { if (a[i][j] && !used[i][j] && t[i][j] == S_CNT) { ++step; int cx = i, cy = j; change_used(cx, cy, step); cur.push_back(make_pair(cx, cy)); } } } vector<int> col(cur.size(), 0); for (int i = 0; i < col.size(); ++i) { col[i] = rc[cur[i].first][cur[i].second]; } map<int, int> res; for (int i = 0; i < col.size(); ++i) { ++res[col[i]]; } cout << res.size() << endl; vector<int> ans; for (map<int, int>::iterator it = res.begin(); it != res.end(); ++it) { ans.push_back(it->second); } sort(ans.begin(), ans.end()); for (int i = 0; i < ans.size(); ++i) { cout << ans[i] << ; } cout << endl; return 0; } |
module system (
input clk100,
output led1,
output led2,
output led3,
output led4,
input sw1_1,
input sw1_2,
input sw2_1,
input sw2_2,
input sw3,
input sw4,
output RAMWE_b,
output RAMOE_b,
output RAMCS_b,
output [17:0] ADR,
inout [15:0] DAT,
input rxd,
output txd);
// CLKSPEED is the main clock speed
parameter CLKSPEED = 50000000;
// BAUD is the desired serial baud rate
parameter BAUD = 115200;
// RAMSIZE is the size of the RAM address bus
parameter RAMSIZE = 12;
// CPU signals
wire clk;
wire [31:0] cpu_din;
wire [31:0] cpu_dout;
wire [31:0] ram_dout;
wire [31:0] ext_dout;
wire [15:0] uart_dout;
wire [19:0] address;
wire rnw;
wire vpa;
wire vda;
wire vio;
wire ramclken; // clken signal for a internal ram access
wire extclken; // clken signal for a external ram access
reg ramclken_old = 0;
wire cpuclken;
reg sw4_sync;
reg reset_b;
// Map the RAM everywhere in IO space (for performance)
wire uart_cs_b = !(vio);
// Map the RAM at both the bottom of memory (uart_cs_b takes priority)
wire ram_cs_b = !((vpa || vda) && (address[19:8] < 12'h00E));
// wire ram_cs_b = !((vpa || vda) && (|address[19:RAMSIZE] == 1'b0));
// Everywhere else is external RAM
wire ext_cs_b = !((vpa || vda) && (address[19:8] >= 12'h00E));
// wire ext_cs_b = !((vpa || vda) && (|address[19:RAMSIZE] == 1'b1));
// External RAM signals
wire [15:0] ext_data_in;
wire [15:0] ext_data_out;
wire ext_data_oe;
`ifdef simulate
assign ext_data_in = DAT;
assign DAT = ext_data_oe ? ext_data_out : 16'hZZZZ;
`else
SB_IO #(
.PIN_TYPE(6'b 1010_01),
) sram_data_pins [15:0] (
.PACKAGE_PIN(DAT),
.OUTPUT_ENABLE(ext_data_oe),
.D_OUT_0(ext_data_out),
.D_IN_0(ext_data_in),
);
`endif
// Data Multiplexor
assign cpu_din = uart_cs_b ? (ram_cs_b ? ext_dout : ram_dout) : {16'b0, uart_dout};
reg [1:0] clkdiv = 2'b00;
always @(posedge clk100)
begin
clkdiv <= clkdiv + 1;
end
assign clk = clkdiv[0];
// Reset generation
reg [9:0] pwr_up_reset_counter = 0; // hold reset low for ~1000 cycles
wire pwr_up_reset_b = &pwr_up_reset_counter;
always @(posedge clk)
begin
ramclken_old <= ramclken;
if (!pwr_up_reset_b)
pwr_up_reset_counter <= pwr_up_reset_counter + 1;
sw4_sync <= sw4;
reset_b <= sw4_sync & pwr_up_reset_b;
end
assign ramclken = !ramclken_old | ram_cs_b;
assign cpuclken = !reset_b | (ext_cs_b ? ramclken : extclken);
assign led1 = 0; // blue
assign led2 = 1; // green
assign led3 = !rxd; // yellow
assign led4 = !txd; // red
// The CPU
opc7cpu CPU
(
.din(cpu_din),
.clk(clk),
.reset_b(reset_b),
.int_b(2'b11),
.clken(cpuclken),
.vpa(vpa),
.vda(vda),
.vio(vio),
.dout(cpu_dout),
.address(address),
.rnw(rnw)
);
memory_controller #
(
.DSIZE(32),
.ASIZE(20)
)
MEMC
(
.clock (clk),
.reset_b (reset_b),
.ext_cs_b (ext_cs_b),
.cpu_rnw (rnw),
.cpu_clken (extclken),
.cpu_addr (address),
.cpu_dout (cpu_dout),
.ext_dout (ext_dout),
.ram_cs_b (RAMCS_b),
.ram_oe_b (RAMOE_b),
.ram_we_b (RAMWE_b),
.ram_data_in (ext_data_in),
.ram_data_out (ext_data_out),
.ram_data_oe (ext_data_oe),
.ram_addr (ADR)
);
// A block RAM - clocked off negative edge to mask output register
ram RAM
(
.din(cpu_dout),
.dout(ram_dout),
.address(address[RAMSIZE-1:0]),
.rnw(rnw),
.clk(clk),
.cs_b(ram_cs_b)
);
// A simple 115200 baud UART
uart #(CLKSPEED, BAUD) UART
(
.din(cpu_dout[15:0]),
.dout(uart_dout),
.a0(address[0]),
.rnw(rnw),
.clk(clk),
.reset_b(reset_b),
.cs_b(uart_cs_b),
.rxd(rxd),
.txd(txd)
);
endmodule
|
/* FIFOs with a variety of interfaces.
*
* Copyright (c) 2016, Stephen Longfield, stephenlongfield.com
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
// D flip-flop with synchronous reset
module dff(clk, rst, inp, outp);
parameter WIDTH = 1;
input wire clk;
input wire rst;
input wire [WIDTH-1:0] inp;
output reg [WIDTH-1:0] outp;
always @(posedge clk) begin
outp <= rst ? 0 : inp;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:08:31 04/18/2014
// Design Name:
// Module Name: CPU_top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module CPU_top(
input wire stp,rst,clk,
input wire [1:0] dptype,
input wire [4:0] regselect,
output wire exec, //on execution, LED on
output wire [5:0] initype,
//use LED to display opcode of current instruction
output wire [3:0] node,
output wire [7:0] segment //digit tube
);
wire stp_out,rst_out,zf;
wire [31:0] i_pc;
wire [31:0] dpdata;
wire [31:0] o_pc;
wire [31:0] o_ins;
wire [31:0] o_sign,aluinputb;
wire [4:0] w1;
wire [31:0] pc_add4,add_branch,not_jump;
wire [31:0]Wdata,Adat,Bdat,mem_data,alu_res;
wire RegDst,ALUsrcB,MemToReg,WriteReg,MemWrite,Branch,ALUop1,ALUop0,JMP;
//signals of CPU controllor
wire [2:0] aluoper;
reg [15:0] digit,count=0; //count=number of instructions excuted
pbdebounce p0(clk,stp,stp_out);
always @(posedge stp_out) count=count+1;
pbdebounce p1(clk,rst,rst_out);
single_pc PC0(stp_out,rst_out,i_pc,o_pc);
Ins_Mem ins (o_pc[11:2],o_ins);
RegFile regfile(stp_out,o_ins[25:21], o_ins[20:16],regselect, w1, Wdata, WriteReg, Adat, Bdat, dpdata);
Data_Mem data_mem (alu_res[7:2], Bdat,stp_out,MemWrite,mem_data); //memory address=address/4
cpu_ctr cpuctr(o_ins[31:26],RegDst,ALUsrcB,MemToReg,WriteReg,MemWrite,Branch,ALUop1,ALUop0,JMP );
aluc alucontrol ({ALUop1,ALUop0}, o_ins[3:0], aluoper);
alu alut(Adat, aluinputb, aluoper, zf, alu_res);
sign_extend sign(o_ins[15:0],o_sign);
display dp(clk,digit,node,segment);
add a1(o_pc,32'h4,pc_add4); //pc_add4=o_pc+4
add a2(pc_add4,{o_sign[29:0],2'b00},add_branch);
//following code implement multiplexers on the above chart
assign w1=(RegDst==1)?o_ins[15:11]:o_ins[20:16];
assign not_jump=(Branch & zf)?add_branch:pc_add4;//branch?
assign i_pc=(JMP==1)?{pc_add4[31:29],o_ins[25:0],2'b00}:not_jump;// jump?
assign aluinputb=(ALUsrcB==1)?o_sign:Bdat;
assign Wdata=(MemToReg==1)?mem_data:alu_res;
always @* begin
case (dptype) //which info to display
2'b00:digit<=dpdata[15:0];
2'b01:digit<=dpdata[31:16];
2'b10:digit<=o_pc[15:0];
2'b11:digit<=count;
endcase
end
assign exec=stp_out;
assign initype=o_ins[31:26]; //opcode of current instruction
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { { long long int i, j, k, y, n, x, m, a, b, ans = 0, sum = 0, cnt = 0; long long int c, mx = 0; string s, z, taj = YES ; cin >> s; map<char, long long int> mp; n = s.size(); for (i = 0; i < n; i++) mp[s[i]]++; if (!mp[ 4 ] and !mp[ 7 ]) cout << -1; else if (mp[ 4 ] >= mp[ 7 ]) cout << 4; else cout << 7; printf( n ); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__ISOBUFSRC_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__ISOBUFSRC_PP_SYMBOL_V
/**
* isobufsrc: Input isolation, noninverted sleep.
*
* X = (!A | SLEEP)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__isobufsrc (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input SLEEP,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__ISOBUFSRC_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1.e9 + 7; const int MAXN = 1000000; int fact[MAXN + 5], inv[MAXN + 5]; int lgput(int a, int b) { int ans = 1; for (; b; b >>= 1) { if (b & 1) ans = 1LL * ans * a % MOD; a = 1LL * a * a % MOD; } return ans; } void prec() { fact[0] = 1; for (int i = 1; i <= MAXN; ++i) fact[i] = 1LL * fact[i - 1] * i % MOD; inv[MAXN] = lgput(fact[MAXN], MOD - 2); for (int i = MAXN; i >= 1; --i) inv[i - 1] = 1LL * inv[i] * i % MOD; } int comb(int n, int k) { return 1LL * fact[n] * inv[k] % MOD * inv[n - k] % MOD; } int f(int n, int k) { if (k == 0) return 1; return 1LL * n * lgput(n + k, k - 1) % MOD; } int main() { prec(); int n, m, a, b; scanf( %d%d%d%d , &n, &m, &a, &b); int ans = 0; for (int i = 0; i <= n - 2; ++i) { if (m < i + 1) break; int aux = 1LL * comb(m - 1, i) * comb(n - 2, i) % MOD * fact[i] % MOD; aux = 1LL * aux * lgput(m, n - 2 - i) % MOD * f(i + 2, n - i - 2) % MOD; ans += aux; if (ans >= MOD) ans -= MOD; } printf( %d n , ans); return 0; } |
/*
Copyright (c) 2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for i2c_master_wbs_16
*/
module test_i2c_master_wbs_16;
// Parameters
parameter DEFAULT_PRESCALE = 1;
parameter FIXED_PRESCALE = 0;
parameter CMD_FIFO = 1;
parameter CMD_FIFO_ADDR_WIDTH = 5;
parameter WRITE_FIFO = 1;
parameter WRITE_FIFO_ADDR_WIDTH = 5;
parameter READ_FIFO = 1;
parameter READ_FIFO_ADDR_WIDTH = 5;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [2:0] wbs_adr_i = 0;
reg [15:0] wbs_dat_i = 0;
reg wbs_we_i = 0;
reg [1:0] wbs_sel_i = 0;
reg wbs_stb_i = 0;
reg wbs_cyc_i = 0;
reg i2c_scl_i = 1;
reg i2c_sda_i = 1;
// Outputs
wire [15:0] wbs_dat_o;
wire wbs_ack_o;
wire i2c_scl_o;
wire i2c_scl_t;
wire i2c_sda_o;
wire i2c_sda_t;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
wbs_adr_i,
wbs_dat_i,
wbs_we_i,
wbs_sel_i,
wbs_stb_i,
wbs_cyc_i,
i2c_scl_i,
i2c_sda_i
);
$to_myhdl(
wbs_dat_o,
wbs_ack_o,
i2c_scl_o,
i2c_scl_t,
i2c_sda_o,
i2c_sda_t
);
// dump file
$dumpfile("test_i2c_master_wbs_16.lxt");
$dumpvars(0, test_i2c_master_wbs_16);
end
i2c_master_wbs_16 #(
.DEFAULT_PRESCALE(DEFAULT_PRESCALE),
.FIXED_PRESCALE(FIXED_PRESCALE),
.CMD_FIFO(CMD_FIFO),
.CMD_FIFO_ADDR_WIDTH(CMD_FIFO_ADDR_WIDTH),
.WRITE_FIFO(WRITE_FIFO),
.WRITE_FIFO_ADDR_WIDTH(WRITE_FIFO_ADDR_WIDTH),
.READ_FIFO(READ_FIFO),
.READ_FIFO_ADDR_WIDTH(READ_FIFO_ADDR_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
.wbs_adr_i(wbs_adr_i),
.wbs_dat_i(wbs_dat_i),
.wbs_dat_o(wbs_dat_o),
.wbs_we_i(wbs_we_i),
.wbs_sel_i(wbs_sel_i),
.wbs_stb_i(wbs_stb_i),
.wbs_ack_o(wbs_ack_o),
.wbs_cyc_i(wbs_cyc_i),
.i2c_scl_i(i2c_scl_i),
.i2c_scl_o(i2c_scl_o),
.i2c_scl_t(i2c_scl_t),
.i2c_sda_i(i2c_sda_i),
.i2c_sda_o(i2c_sda_o),
.i2c_sda_t(i2c_sda_t)
);
endmodule
|
// ---------------------------------------------------------------------------
// -- --
// -- (C) 2016-2022 Revanth Kamaraj (krevanth) --
// -- --
// -- ------------------------------------------------------------------------
// -- --
// -- This program is free software; you can redistribute it and/or --
// -- modify it under the terms of the GNU General Public License --
// -- as published by the Free Software Foundation; either version 2 --
// -- of the License, or (at your option) any later version. --
// -- --
// -- This program is distributed in the hope that it will be useful, --
// -- but WITHOUT ANY WARRANTY; without even the implied warranty of --
// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
// -- GNU General Public License for more details. --
// -- --
// -- You should have received a copy of the GNU General Public License --
// -- along with this program; if not, write to the Free Software --
// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA --
// -- 02110-1301, USA. --
// -- --
// ---------------------------------------------------------------------------
// -- --
// -- Implements a simple coprocessor interface for the ZAP core. The i/f --
// -- is low bandwidth and thus is suited only for coprocessor that do not --
// -- perform large data exchanges. Note that the translate function must be--
// -- present in the coprocessor to account for CPU modes. --
// -- --
// ---------------------------------------------------------------------------
`default_nettype none
module zap_predecode_coproc #(
parameter PHY_REGS = 46
)
(
input wire i_clk,
input wire i_reset,
// Instruction and valid qualifier.
input wire [34:0] i_instruction,
input wire i_valid,
// CPSR Thumb Bit.
input wire i_cpsr_ff_t,
input wire [4:0] i_cpsr_ff_mode,
// Interrupts.
input wire i_irq,
input wire i_fiq,
// Clear and stall signals.
input wire i_clear_from_writeback, // | High Priority
input wire i_data_stall, // |
input wire i_clear_from_alu, // |
input wire i_stall_from_shifter, // |
input wire i_stall_from_issue, // V Low Priority
// Pipeline Valid. Must become 0 when every stage of the pipeline
// is invalid.
input wire i_pipeline_dav,
// Coprocessor done signal.
input wire i_copro_done,
// Interrupts output.
output reg o_irq,
output reg o_fiq,
// Instruction and valid qualifier.
output reg [34:0] o_instruction,
output reg o_valid,
// We can generate stall if coprocessor is slow. We also have
// some minimal latency.
output reg o_stall_from_decode,
// Are we really asking for the coprocessor ?
output reg o_copro_dav_ff,
// The entire instruction is passed to the coprocessor.
output reg [31:0] o_copro_word_ff
);
///////////////////////////////////////////////////////////////////////////////
`include "zap_defines.vh"
`include "zap_localparams.vh"
`include "zap_functions.vh"
///////////////////////////////////////////////////////////////////////////////
localparam IDLE = 0;
localparam BUSY = 1;
///////////////////////////////////////////////////////////////////////////////
// State register.
reg state_ff, state_nxt;
// Output registers.
reg cp_dav_ff, cp_dav_nxt;
reg [31:0] cp_word_ff, cp_word_nxt;
///////////////////////////////////////////////////////////////////////////////
// Connect output registers to output.
always @*
begin
o_copro_word_ff = cp_word_ff;
o_copro_dav_ff = cp_dav_ff;
end
///////////////////////////////////////////////////////////////////////////////
wire c1 = !i_cpsr_ff_t;
wire c2 = i_cpsr_ff_mode != USR;
wire c3 = i_instruction[11:8] == 4'b1111;
wire c4 = i_instruction[34:32] == 3'd0;
wire c5 = c1 & c2 & c3 & c4;
reg eclass;
// Next state logic.
always @*
begin
// Default values.
cp_dav_nxt = cp_dav_ff;
cp_word_nxt = cp_word_ff;
o_stall_from_decode = 1'd0;
o_instruction = i_instruction;
o_valid = i_valid;
state_nxt = state_ff;
o_irq = i_irq;
o_fiq = i_fiq;
eclass = 0;
case ( state_ff )
IDLE:
// Activate only if no thumb, not in USER mode and CP15 access is requested.
casez ( (!i_cpsr_ff_t && (i_instruction[34:32] == 3'd0) && i_valid) ? i_instruction[31:0] : 35'd0 )
MRC, MCR, LDC, STC, CDP, MRC2, MCR2, LDC2, STC2:
begin
if ( i_instruction[11:8] == 4'b1111 && i_cpsr_ff_mode != USR ) // CP15 and root access -- perfectly fine.
begin
// Send ANDNV R0, R0, R0 instruction.
o_instruction = {4'b1111, 28'd0};
o_valid = 1'd0;
o_irq = 1'd0;
o_fiq = 1'd0;
// As long as there is an instruction to process...
if ( i_pipeline_dav )
begin
// Do not impose any output. However, continue
// to stall all before this unit in the
// pipeline.
o_valid = 1'd0;
o_stall_from_decode = 1'd1;
cp_dav_nxt = 1'd0;
cp_word_nxt = 32'd0;
end
else
begin
// Prepare to move to BUSY. Continue holding
// stall. Send out 0s.
o_valid = 1'd0;
o_stall_from_decode = 1'd1;
cp_word_nxt = i_instruction;
cp_dav_nxt = 1'd1;
state_nxt = BUSY;
end
end
else // Warning...
begin
if ( i_instruction[11:8] != 4'b1111 )
eclass = 1;
else
eclass = 2;
// Remain transparent since this is not a coprocessor
// instruction.
o_valid = i_valid;
o_instruction = i_instruction;
o_irq = i_irq;
o_fiq = i_fiq;
cp_dav_nxt = 0;
o_stall_from_decode = 0;
cp_word_nxt = {32{1'dx}}; // Don't care. This is perfectly OK - synth will optimize.
end
end
default:
begin
// Remain transparent since this is not a coprocessor
// instruction.
o_valid = i_valid;
o_instruction = i_instruction;
o_irq = i_irq;
o_fiq = i_fiq;
cp_dav_nxt = 0;
o_stall_from_decode = 0;
cp_word_nxt = {32{1'dx}}; // Don't care. This is perfectly OK - synth will optimize.
end
endcase
BUSY:
begin
// Provide coprocessor word and valid to the coprocessor.
cp_word_nxt = cp_word_ff;
cp_dav_nxt = cp_dav_ff;
// Continue holding stall.
o_stall_from_decode = 1'd1;
// Send out nothing.
o_valid = 1'd0;
o_instruction = 32'd0;
// Block interrupts.
o_irq = 1'd0;
o_fiq = 1'd0;
// If we get a response, we can move back to IDLE. Release
// the stall so that processor can continue.
if ( i_copro_done )
begin
cp_dav_nxt = 1'd0;
cp_word_nxt = 32'd0;
state_nxt = IDLE;
o_stall_from_decode = 1'd0;
end
end
endcase
end
always @ (posedge i_clk)
begin
if ( i_reset )
begin
cp_word_ff <= 0;
clear;
end
else if ( i_clear_from_writeback )
begin
clear;
end
else if ( i_data_stall )
begin
// Preserve values.
end
else if ( i_clear_from_alu )
begin
clear;
end
else if ( i_stall_from_shifter )
begin
// Preserve values.
end
else if ( i_stall_from_issue )
begin
// Preserve values.
end
else
begin
state_ff <= state_nxt;
cp_word_ff <= cp_word_nxt;
cp_dav_ff <= cp_dav_nxt;
end
end
// Clear out the unit.
task clear;
begin
state_ff <= IDLE;
cp_dav_ff <= 1'd0;
end
endtask
endmodule
`default_nettype wire
// ----------------------------------------------------------------------------
// EOF
// ----------------------------------------------------------------------------
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:45:15 09/30/2016
// Design Name:
// Module Name: painter_chooser
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module painter_chooser(
input [9:0] hc,
input [9:0] vc,
input [9:0] mouse_x,
input [8:0] mouse_y,
input [7:0] rgb_background,
input [7:0] line_code,
output reg [9:0] hpos,
output reg [8:0] vpos,
output reg [4:0] line_number,
output reg [7:0] rgb
);
parameter [7:0]hbp = 144; // Fin del "back-porch" horizontal
parameter [4:0]vbp = 31; // Fin del "back-porch" vertical
parameter [7:0]black = 8'b00000000;
parameter [7:0]lblue = 8'b00001011;
parameter [7:0]lred = 8'b10000000;
always @(*)
begin
vpos = {vc - vbp}[8:0];
hpos = hc - hbp;
line_number = 0;
rgb = rgb_background;
if( hpos >= mouse_x && hpos < (mouse_x + 8) // Inicio: dibuja mouse
&& vpos >= mouse_y && vpos < (mouse_y + 11))
begin
line_number = {vpos - mouse_y}[4:0];
if(line_code[hpos-mouse_x])
rgb = black;
end // Fin: dibuja mouse
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, ans = 0; cin >> n; long long a[n + 1]; vector<long long> last; last.push_back(-1); for (int i = 0; i < n; i++) { cin >> a[i]; if (i > 0 && a[i] <= a[i - 1]) last.push_back(i - 1); } last.push_back(n - 1); for (int i = 1; i < (int)last.size(); i++) { if (last[i - 1] == -1) ans = max(last[i] + 1, ans); else ans = max(ans, last[i] - last[i - 1]); if (i < (int)last.size() - 1 && (a[last[i] + 1] > a[last[i] - 1] || a[last[i] + 2] > a[last[i]])) { if (i > 1) ans = max(last[i + 1] - last[i - 1] - 1, ans); else ans = max(ans, last[i + 1]); } } cout << ans; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O32A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__O32A_BEHAVIORAL_PP_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o32a (
VPWR,
VGND,
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
// Local signals
wire B1 or0_out ;
wire B1 or1_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X , or0_out, or1_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O32A_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; long long C(int a, int b) { long long ans = 1; for (int i = 0; i < b; ++i) ans *= (a - i), ans /= (i + 1); return ans; } int main() { int n; while (cin >> n) cout << C(n + 4, 5) * C(n + 2, 3) << endl; } |
#include <bits/stdc++.h> using namespace std; long long int a, b, c, d; int main() { cin >> a >> b >> c >> d; if (a + 8 * c >= b) cout << 0 ; else if (c > d) { int num = b - a - 8 * c, den = 12 * (c - d); cout << (num + den - 1) / den; } else cout << -1 ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 200005; int n, a, b, k, pr[N], seq[N]; char s[200005]; int main() { scanf( %d%d%d%d , &n, &a, &b, &k); scanf( %s , s + 1); int len = strlen(s + 1), lst = 0, cur = 0; for (int i = 1; i <= len; ++i) { if (s[i] == 1 ) { cur += (i - lst - 1) / b; lst = i; } } if (s[len] != 1 ) cur += (len - lst) / b; int ans = 0, now = 0, da = 0; for (int i = 1; i <= len; ++i) { now++; if (s[i] == 1 ) now = 0; if (now == b) { now = 0; ans++; seq[ans] = i; if (cur - ans < a) break; } } printf( %d n , ans); for (int i = 1; i <= ans; ++i) printf( %d , seq[i]); return 0; } |
// soc_system.v
// Generated using ACDS version 16.1 196
`timescale 1 ps / 1 ps
module soc_system (
input wire clk_clk, // clk.clk
input wire [28:0] hps_0_f2h_sdram0_data_address, // hps_0_f2h_sdram0_data.address
input wire [7:0] hps_0_f2h_sdram0_data_burstcount, // .burstcount
output wire hps_0_f2h_sdram0_data_waitrequest, // .waitrequest
output wire [63:0] hps_0_f2h_sdram0_data_readdata, // .readdata
output wire hps_0_f2h_sdram0_data_readdatavalid, // .readdatavalid
input wire hps_0_f2h_sdram0_data_read, // .read
input wire [28:0] hps_0_f2h_sdram1_data_address, // hps_0_f2h_sdram1_data.address
input wire [7:0] hps_0_f2h_sdram1_data_burstcount, // .burstcount
output wire hps_0_f2h_sdram1_data_waitrequest, // .waitrequest
output wire [63:0] hps_0_f2h_sdram1_data_readdata, // .readdata
output wire hps_0_f2h_sdram1_data_readdatavalid, // .readdatavalid
input wire hps_0_f2h_sdram1_data_read, // .read
input wire [28:0] hps_0_f2h_sdram2_data_address, // hps_0_f2h_sdram2_data.address
input wire [7:0] hps_0_f2h_sdram2_data_burstcount, // .burstcount
output wire hps_0_f2h_sdram2_data_waitrequest, // .waitrequest
output wire [63:0] hps_0_f2h_sdram2_data_readdata, // .readdata
output wire hps_0_f2h_sdram2_data_readdatavalid, // .readdatavalid
input wire hps_0_f2h_sdram2_data_read, // .read
input wire [28:0] hps_0_f2h_sdram3_data_address, // hps_0_f2h_sdram3_data.address
input wire [7:0] hps_0_f2h_sdram3_data_burstcount, // .burstcount
output wire hps_0_f2h_sdram3_data_waitrequest, // .waitrequest
input wire [63:0] hps_0_f2h_sdram3_data_writedata, // .writedata
input wire [7:0] hps_0_f2h_sdram3_data_byteenable, // .byteenable
input wire hps_0_f2h_sdram3_data_write, // .write
input wire [28:0] hps_0_f2h_sdram4_data_address, // hps_0_f2h_sdram4_data.address
input wire [7:0] hps_0_f2h_sdram4_data_burstcount, // .burstcount
output wire hps_0_f2h_sdram4_data_waitrequest, // .waitrequest
input wire [63:0] hps_0_f2h_sdram4_data_writedata, // .writedata
input wire [7:0] hps_0_f2h_sdram4_data_byteenable, // .byteenable
input wire hps_0_f2h_sdram4_data_write, // .write
output wire hps_0_i2c1_out_data, // hps_0_i2c1.out_data
input wire hps_0_i2c1_sda, // .sda
output wire hps_0_i2c1_clk_clk, // hps_0_i2c1_clk.clk
input wire hps_0_i2c1_scl_in_clk, // hps_0_i2c1_scl_in.clk
output wire [14:0] memory_mem_a, // memory.mem_a
output wire [2:0] memory_mem_ba, // .mem_ba
output wire memory_mem_ck, // .mem_ck
output wire memory_mem_ck_n, // .mem_ck_n
output wire memory_mem_cke, // .mem_cke
output wire memory_mem_cs_n, // .mem_cs_n
output wire memory_mem_ras_n, // .mem_ras_n
output wire memory_mem_cas_n, // .mem_cas_n
output wire memory_mem_we_n, // .mem_we_n
output wire memory_mem_reset_n, // .mem_reset_n
inout wire [31:0] memory_mem_dq, // .mem_dq
inout wire [3:0] memory_mem_dqs, // .mem_dqs
inout wire [3:0] memory_mem_dqs_n, // .mem_dqs_n
output wire memory_mem_odt, // .mem_odt
output wire [3:0] memory_mem_dm, // .mem_dm
input wire memory_oct_rzqin, // .oct_rzqin
input wire reset_reset_n // reset.reset_n
);
soc_system_hps_0 #(
.F2S_Width (0),
.S2F_Width (0)
) hps_0 (
.i2c1_scl (hps_0_i2c1_scl_in_clk), // i2c1_scl_in.clk
.i2c1_out_clk (hps_0_i2c1_clk_clk), // i2c1_clk.clk
.i2c1_out_data (hps_0_i2c1_out_data), // i2c1.out_data
.i2c1_sda (hps_0_i2c1_sda), // .sda
.mem_a (memory_mem_a), // memory.mem_a
.mem_ba (memory_mem_ba), // .mem_ba
.mem_ck (memory_mem_ck), // .mem_ck
.mem_ck_n (memory_mem_ck_n), // .mem_ck_n
.mem_cke (memory_mem_cke), // .mem_cke
.mem_cs_n (memory_mem_cs_n), // .mem_cs_n
.mem_ras_n (memory_mem_ras_n), // .mem_ras_n
.mem_cas_n (memory_mem_cas_n), // .mem_cas_n
.mem_we_n (memory_mem_we_n), // .mem_we_n
.mem_reset_n (memory_mem_reset_n), // .mem_reset_n
.mem_dq (memory_mem_dq), // .mem_dq
.mem_dqs (memory_mem_dqs), // .mem_dqs
.mem_dqs_n (memory_mem_dqs_n), // .mem_dqs_n
.mem_odt (memory_mem_odt), // .mem_odt
.mem_dm (memory_mem_dm), // .mem_dm
.oct_rzqin (memory_oct_rzqin), // .oct_rzqin
.h2f_rst_n (), // h2f_reset.reset_n
.f2h_sdram0_clk (clk_clk), // f2h_sdram0_clock.clk
.f2h_sdram0_ADDRESS (hps_0_f2h_sdram0_data_address), // f2h_sdram0_data.address
.f2h_sdram0_BURSTCOUNT (hps_0_f2h_sdram0_data_burstcount), // .burstcount
.f2h_sdram0_WAITREQUEST (hps_0_f2h_sdram0_data_waitrequest), // .waitrequest
.f2h_sdram0_READDATA (hps_0_f2h_sdram0_data_readdata), // .readdata
.f2h_sdram0_READDATAVALID (hps_0_f2h_sdram0_data_readdatavalid), // .readdatavalid
.f2h_sdram0_READ (hps_0_f2h_sdram0_data_read), // .read
.f2h_sdram1_clk (clk_clk), // f2h_sdram1_clock.clk
.f2h_sdram1_ADDRESS (hps_0_f2h_sdram1_data_address), // f2h_sdram1_data.address
.f2h_sdram1_BURSTCOUNT (hps_0_f2h_sdram1_data_burstcount), // .burstcount
.f2h_sdram1_WAITREQUEST (hps_0_f2h_sdram1_data_waitrequest), // .waitrequest
.f2h_sdram1_READDATA (hps_0_f2h_sdram1_data_readdata), // .readdata
.f2h_sdram1_READDATAVALID (hps_0_f2h_sdram1_data_readdatavalid), // .readdatavalid
.f2h_sdram1_READ (hps_0_f2h_sdram1_data_read), // .read
.f2h_sdram2_clk (clk_clk), // f2h_sdram2_clock.clk
.f2h_sdram2_ADDRESS (hps_0_f2h_sdram2_data_address), // f2h_sdram2_data.address
.f2h_sdram2_BURSTCOUNT (hps_0_f2h_sdram2_data_burstcount), // .burstcount
.f2h_sdram2_WAITREQUEST (hps_0_f2h_sdram2_data_waitrequest), // .waitrequest
.f2h_sdram2_READDATA (hps_0_f2h_sdram2_data_readdata), // .readdata
.f2h_sdram2_READDATAVALID (hps_0_f2h_sdram2_data_readdatavalid), // .readdatavalid
.f2h_sdram2_READ (hps_0_f2h_sdram2_data_read), // .read
.f2h_sdram3_clk (clk_clk), // f2h_sdram3_clock.clk
.f2h_sdram3_ADDRESS (hps_0_f2h_sdram3_data_address), // f2h_sdram3_data.address
.f2h_sdram3_BURSTCOUNT (hps_0_f2h_sdram3_data_burstcount), // .burstcount
.f2h_sdram3_WAITREQUEST (hps_0_f2h_sdram3_data_waitrequest), // .waitrequest
.f2h_sdram3_WRITEDATA (hps_0_f2h_sdram3_data_writedata), // .writedata
.f2h_sdram3_BYTEENABLE (hps_0_f2h_sdram3_data_byteenable), // .byteenable
.f2h_sdram3_WRITE (hps_0_f2h_sdram3_data_write), // .write
.f2h_sdram4_clk (clk_clk), // f2h_sdram4_clock.clk
.f2h_sdram4_ADDRESS (hps_0_f2h_sdram4_data_address), // f2h_sdram4_data.address
.f2h_sdram4_BURSTCOUNT (hps_0_f2h_sdram4_data_burstcount), // .burstcount
.f2h_sdram4_WAITREQUEST (hps_0_f2h_sdram4_data_waitrequest), // .waitrequest
.f2h_sdram4_WRITEDATA (hps_0_f2h_sdram4_data_writedata), // .writedata
.f2h_sdram4_BYTEENABLE (hps_0_f2h_sdram4_data_byteenable), // .byteenable
.f2h_sdram4_WRITE (hps_0_f2h_sdram4_data_write) // .write
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int bit[1000010] = {0}; long long int get_sum(int i) { long long int ans = 0; while (i > 0) { ans += bit[i]; i -= i & (-i); } return ans; } void update(int i, int n) { while (i <= n) { bit[i] += 1; i += i & (-i); } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n; cin >> n; long long int arr[n], small[n], big[n], tmp[n]; long long int max1 = 0; for (int i = 0; i < n; i++) { cin >> arr[i]; tmp[i] = arr[i]; } sort(tmp, tmp + n); for (int i = 0; i < n; i++) { arr[i] = lower_bound(tmp, tmp + n, arr[i]) - tmp + 1; if (arr[i] > max1) max1 = arr[i]; } long long int ans = 0; for (int i = (n - 1); i >= 0; i--) { small[i] = get_sum(arr[i] - 1); update(arr[i], max1); } for (int i = 0; i <= max1; i++) bit[i] = 0; for (int i = 0; i < n; i++) { big[i] = i - get_sum(arr[i]); update(arr[i], max1); ans += big[i] * small[i]; } cout << ans; return 0; } |
#include<bits/stdc++.h> using namespace std; struct _field { bool white = false; }; int mod = 998244353; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); #ifndef ONLINE_JUDGE freopen( input.txt , r , stdin); //freopen( a.out , w ,stdout); // console output is better (in most cases) #else // add i/o method of specific testing system #endif int n, m; cin >> n >> m; vector<vector<_field>> field(m + 1, vector<_field>(n + 1)); for(int y = 1; y <= n; ++y) { for(int x = 1; x <= m; ++x) { char temp; cin >> temp; if(temp == * ) { field[x][y].white = false; } if(temp == o ) { field[x][y].white = true; } } } long long sol = 0; // value long long v = 0; // value long long h = 0; // combinations that have a half to the left long long e = 0; // combinations that are ended on the left long long c = 1; // #combinations for(int y = 0; y <= n; ++y) { for(int x = 0; x <= m; ++x) { long long nh = 0; long long ne = 0; // count if we match the color nh = (c + e) % mod; ne = h; c = ((c + e) % mod + h) % mod; if(field[x][y].white) { v = ((v * 2) % mod + ne) % mod; } else { nh = 0; ne = 0; } h = nh; e = ne; } } sol = v; int sol1 = v; v = 0; h = 0; // combinations that have a half to the left e = 0; // combinations that are ended on the left c = 1; // black ones for(int x = 0; x <= m; ++x) { for(int y = 0; y <= n; ++y) { long long nh = 0; long long ne = 0; // count if we match the color nh = (c + e) % mod; ne = h; c = ((c + e) % mod + h) % mod; if(field[x][y].white) { v = ((v * 2) % mod + ne) % mod; } else { nh = 0; ne = 0; } h = nh; e = ne; } } int sol2 = v; sol = (sol + v) % mod; //cout << sol1 << n ; //cout << sol2 << n ; cout << sol << n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2111A_2_V
`define SKY130_FD_SC_MS__O2111A_2_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog wrapper for o2111a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o2111a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o2111a_2 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o2111a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o2111a_2 (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o2111a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2111A_2_V
|
#include<bits/stdc++.h> using namespace std; typedef long long ll; typedef long double lf; typedef unsigned long long ull; typedef pair<ll,int>P; const int inf = 0x7f7f7f7f; const ll INF = 1e16; const int N = 2e5+10; const ull base = 131; const ll mod = 1e9+7; const double PI = acos(-1.0); const double eps = 1e-4; inline int read(){int x=0,f=1;char ch=getchar();while(ch< 0 ||ch> 9 ){if(ch== - )f=-1;ch=getchar();}while(ch>= 0 &&ch<= 9 ){x=x*10+ch- 0 ;ch=getchar();}return x*f;} inline string readstring(){string str;char s=getchar();while(s== ||s== n ||s== r ){s=getchar();}while(s!= &&s!= n &&s!= r ){str+=s;s=getchar();}return str;} int random(int n){return (int)(rand()*rand())%n;} void writestring(string s){int n = s.size();for(int i = 0;i < n;i++){printf( %c ,s[i]);}} int a[N]; int b[N],c[N]; void solve(){ int n = read(); memset(b,0,sizeof b); memset(c,0,sizeof c); set<int>st1,st2; for(int i = 1;i <= n;i++){ st1.insert(i); st2.insert(i); } for(int i = 1;i <= n;i++){ a[i] = read(); } b[1] = c[1] = a[1]; st1.erase(a[1]); st2.erase(a[1]); for(int i = 2;i <= n;i++){ if(a[i] != a[i-1]){ b[i] = c[i] = a[i]; st1.erase(a[i]); st2.erase(a[i]); } } for(int i = 1;i <= n;i++){ if(b[i] == 0){ int x = *st1.begin(); b[i] = x; //cout<<x<<endl; st1.erase(x); } if(c[i] == 0){ auto it = st2.upper_bound(c[i-1]); it--; c[i] = *it; st2.erase(c[i]); } } for(int i = 1;i <= n;i++){ printf( %d ,b[i]); } puts( ); for(int i = 1;i <= n;i++){ printf( %d ,c[i]); } puts( ); } int main(){ int t = read(); while(t--){ solve(); } return 0; } |
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