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module counterDiagnosticVersion (clk,sig,f,n_clk_out);
/*This module takes an input signal and implements a period counter,
taking the reciprocal to deliver the frequency in kHz.
USAGE:
counter c(clk,sig,f);
clk and sig are 1-bit inputs representing the clock and RF signal whose frequency
is to be measured.
f is a 4-bit output corresponding to the frequency of sig, IN UNITS OF HUNDREDS
OF Hz. This is because hundreds of Hz is the highest requeired frequency
resolution, and we want to use integer arithmetic.
Reference: Agilent Technologies. "Fundamentals of the Electronic Counters".
Application Note 200, Electronic Counter Series.
Design notes:
In a period counter, pulses of the clock are counted in a register, with the
totaling (counting) action gated by pulses from the RF input whose frequency
is being measured. Averaging over multiple RF cycles reduces error.
The total time elapsed between RF edges will be
n_clk*tau_c+err = m/f
=>f= m/(n_clk*tau_c+err)
where tau_c is the clock period, n_clk is the number of clock cycles actually counted
by the register, err is the error in the time estimate, m is the number of RF
positive edges, and f is the RF frequency.
Contributions to error include the +-1 count error, timebase deviations, etc.
The +-1 count error, or quantization error, arises because time is only measured
in discrete steps, and a measurement of four clock time units may be produced by
RF pulses which are acutally separated by 3+delta or 5-delta clock units.
The nominal frequency estimate
f_nominal=m/(n_clk*tau_c)
converges with the value that would arise from an average after many cycles
if n_clk is very large.
With just the +-1 count error, the spread in maximum and minimum possible
frequency estimates
fmax-fmin=m/tau_c*(1/(n_clk-1)-1/(n_clk+1))=2*m/tau_c * 1/(n_clk^2-1) ~= 2*f_nom^2*tau_c/m
=2*f_nom^2/(f_clk*m)
The error increases with frequency for a fixed number of RF pulses, but decreases
as the clock frequency increases and as the number of RF pulses averaged over
increases.
We require about 3 kHz resolution at the highest frequencies (around 300 kHz)
and about 500 Hz resolution at the lowest frequencies - these values are about
half the frequency interval between adjacent bins in these sub-bands. With
a clock speed of 4 MHz,
m=2*f_high^2/(f_clk*Delta_f_high)=2*(3E5^2)/(4E6*3E3)=18E10/(12E9)=15
with m=15, at the lower frequencies,
fmax-fmin=2*5E4^2/(4E6*15) = Delta_f_high/36 ~= 83 Hz
while m/5E4=15/5E4=3.0E-4=300 us is the maximum time elapsed per measurement.
At high frequency, Delta_t = m/300E3=50 us.
Since we are willing to accept a reaction time on the order of 1 ms, we can
actually improve accuracy by increasing m such that Delta_t_max = 1 ms = m/5E4
=>m=50.
So choose m=50, which gives fmax-fmin~=900 Hz at f_rf=300 kHz.
f_nom = m*f_clk/n_clk => n_clk = m*f_clk/f_nom,
n_clk_max=50*4E6/5E4=80E2=4000
=>n_clk needs to be at least 12 bits. Make 13.
//Error (10239): Verilog HDL Always Construct error at counter.v(102): event control cannot test for both positive and negative edges of variable "clk"
*/
//11 Jan 2012: THIS VERSION OUTPUTS THE CLK COUNTER TO SEE WHETHER THE INPUT TO THE DIVISION, IN ADDITION TO THE OUTPUT, IS UNSTABLE. TED GOLFINOPOULOS
input clk,sig;
output reg [13:0] f; //Output frequency in hundreds of Hz.
reg [13:0] n_clk; //Register to hold number of clock counts between RF signal.
reg [13:0] n_clk_last; //Clock sub-counter. Increment clock in 3's
//reg firstPassComplete; //Flag indicating that a legitimate n_clk_last is available.
output reg [13:0] n_clk_out; //Only update this counter when the frequency is computed.
reg [6:0] n_sig; //Register to count the number of RF cycles.
reg cnt_flg; //Counter flag.
reg hold_n_clk; //Gate for increment action for n_clk - count when 0, don't count when 1.
reg reset; //Internal flag to reset clock counter.
`define CLK_COUNTER_SIZE 14 //Number of bits in clock edge counter.
`define SIG_COUNTER_SIZE 7 //Number of bits in signal edge counter.
//Clock frequency in hundreds of Hz.
//parameter F_CLK=40000;
parameter F_CLK=35795; //This clock was used to test whether incorrect firing of state happens at different frequencies depending on clock frequency and precession of this with sync signal freq.
//Number of cycles of RF signal over which to average period.
parameter M=50; //Double M and increase sample time, and throw away lowest bits (jitter).
//parameter MIN_CHANGE=`CLK_COUNTER_SIZE'b10; //n_clk must change by at least this about (up or down) from last n_clk in order for a change in computed frequency to be allowed.
parameter MIN_CHANGE=`CLK_COUNTER_SIZE'b10;
//parameter ROUND_RANGE=3; //Round in triplets according to floor(n/ROUND_RANGE)*ROUND_RANGE+1.
//Define macros to set counter sizes for convenience (so that don't have to make multiple changes if counter size needs to be adjusted).
initial begin
#0
n_clk=`CLK_COUNTER_SIZE'b0; //Initialize clock edge counter.
n_sig=`SIG_COUNTER_SIZE'b0; //RF Cycle counter.
n_clk_last=`CLK_COUNTER_SIZE'b0; //Initialize storage for last clock counter value.
reset=1'b1; //Initialize reset flag to block clock counter until signal counter gate opens.
hold_n_clk=1'b0; //Initialize hold on increment action for clock counter to OFF.
end
//Clock loop
//always @(posedge clk) begin //Triggering on reset was there in case there were two sig edges before the next clk edge, in which case the reset call would get skipped. But maybe false triggers are causing clock count to drift or flicker. Remove this edge detector and see what happens. Result - no, that didn't fix the problem.
always @(posedge clk or posedge reset) begin
if (reset) begin
n_clk=`CLK_COUNTER_SIZE'b0; //Reset clk counter.
// end else if(!hold_n_clk) begin
end else begin
n_clk=n_clk+`CLK_COUNTER_SIZE'b1; //Increment clk counter.
end
end
//Gate on positive edges of signal
always @(posedge sig) begin
//Initially, the gate is closed and n_sig=0.
//When the gate is opened, n_sig is incremented, so n_sig=1.
//The gate is closed again at the (M+1)th positive edge on n_sig, but before n_sig is incremented,
//so n_sig=M still.
//As such, the gate is open between the 1st and (M+1)th positive edges of n_sig, corresponding to M sig intervals.
//The gate is closed between the (M+1)th=0th and 1st signal edges.
//THEN dt = (M)*tau_sig = (M)/f_sig = (n_clk-1+[-0+2])/f_clk
//It is n_clk-1 because this is the number of clock time intervals in n_clk positive edges.
// [-0+2]=error on time measurement - time is at least (n_clk-1)*tau_c, but could be as much as
// (n_clk-1+2-delta)*tau_c, so on average, elapsed time is actually (n_clk-1 - (average error = (0+2)/2=1))*tau_c
// => f_sig = f_clk * (M)/(n_clk-1-(0+2)/2) = f_clk * (M)/n_clk
if (n_sig==M) begin //This is actually the M+1th edge, and the Mth interval
// hold_n_clk=1'b1; //Turn on flag to arrest incrementing of n_clk, but do not reset yet. Compute on next sig edge.
// n_sig=n_sig+`SIG_COUNTER_SIZE'b1;
// end else if(n_sig==(M+1)) begin //Now, compute with the (hopefully-settled) counters.
//First, round n_clk to triplets, as described below.
//n_clk = (n_clk/ROUND_RANGE)*ROUND_RANGE+`CLK_COUNTER_SIZE'b1;
//f=((M*F_CLK)/(ROUND_RANGE*n_clk))*ROUND_RANGE+`CLK_COUNTER_SIZE'b1; //Compute RF frequency.
//After M sig edges and n_clk clock edges,
//Handle case where n_clk=0 by saturating frequency at f=M*F_CLK.
if(n_clk==`CLK_COUNTER_SIZE'b0) f=(M)*F_CLK; //Case where no counts on clock are registered.
//Round triplets to center values, so count 1, 4, 7, ... This is to avoid noise from +[0,1] count error,
//i.e. in general, when M*tau_sig != n*tau_c, M and n integers,
//the phase between the sig and clock signals will not be constant,
//but one will precess about the other. As such, n_clk will register
//floor(M*tau_s/tau_c) some of the time, and floor(M*tau_s/tau_c)+1
//some of the time. To avoid this, count by threes and round to the
//middle of the triplets, so that the natural oscillation will be ignored.
//Disallow jitter from changes in n_clk by +-2; only update frequency when clock counter is different by a number other than +-1.
//Also, add in another do-nothing sig cycle during which time the clk counter is gated off
//to make sure clk counter is settled.
// else if (n_clk!=n_clk_last && ((n_clk>n_clk_last && n_clk-n_clk_last>`CLK_COUNTER_SIZE'b10) || ( n_clk_last>n_clk && n_clk_last-n_clk>`CLK_COUNTER_SIZE'b10) )) begin
else if ((n_clk>n_clk_last && n_clk-n_clk_last>MIN_CHANGE) || ( n_clk_last>n_clk && n_clk_last-n_clk>MIN_CHANGE) ) begin
n_clk_last=n_clk; //Store clock counter at last frequency change.
f=(M*F_CLK)/n_clk_last; //Re-compute RF frequency.
end
n_sig=`SIG_COUNTER_SIZE'b0; //Zero out rf cycle counter.
reset=1'b1; //Set reset flag high to restart clock counter.
n_clk_out=n_clk_last;
end else begin //Start incrementing signal positive edge counter.
hold_n_clk = 1'b0; //Set hold for clock-counter to zero and start counting clock cycles again.
reset=1'b0; //Set reset low and start counting clock cycles again.
n_sig=n_sig+`SIG_COUNTER_SIZE'b1; //Increment RF cycle counter.
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A21BOI_PP_SYMBOL_V
`define SKY130_FD_SC_MS__A21BOI_PP_SYMBOL_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a21boi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1_N,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A21BOI_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int N = 30; class Solution; class LinearBasis { public: friend class Solution; LinearBasis() : size(0) { fill(begin(bs), end(bs), 0); } LinearBasis& operator=(const LinearBasis& other) { copy(begin(other.bs), end(other.bs), begin(bs)); size = other.size; return *this; } void add(int num) { for (int i = 0; i < N; ++i) { if (num & (1 << i)) { if (bs[i] == 0) { bs[i] = num; ++size; break; } else { num ^= bs[i]; } } } } bool isValid(int num) { if (num == 0) { return true; } for (int i = 0; i < N; ++i) { if (num & (1 << i)) { num ^= bs[i]; if (num == 0) { return true; } } } return false; } protected: int bs[N]; int size; }; class Solution { public: Solution(vector<int>& _A, int n) : nums(_A), size(n) { init(); } int query(int l, int x) { if (l <= 0) { return 0; } l = min(l, size); if (lbs[l].isValid(x)) { return powM(2, l - lbs[l].size); } else { return 0; } } private: int size; vector<int> nums; vector<LinearBasis> lbs; const int M = 1e9 + 7; void init() { lbs.clear(); lbs.resize(size + 1); for (int i = 0; i < size; ++i) { int a = nums[i]; lbs[i + 1] = lbs[i]; lbs[i + 1].add(a); } } long long normalize(long long a) { a %= M; if (a < 0) { a += M; } return a; } long long addM(long long a, long long b) { return normalize(a + b); } long long mulM(long long a, long long b) { return normalize(a * b); } long long powM(long long x, long long e) { long long res = 1; while (e > 0) { if (e & 0x1) { res = mulM(res, x); } x = mulM(x, x); e >>= 1; } return res; } }; int main(int argc, char** argv) { ios::sync_with_stdio(false); cin.tie(0); int n, q; cin >> n >> q; vector<int> nums(n); for (int i = 0; i < n; ++i) { cin >> nums[i]; } Solution sol(nums, n); for (int i = 0, l = 0, x = 0; i < q; ++i) { cin >> l >> x; cout << sol.query(l, x) << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int mod = 256; int getNum(char tch) { int num = tch; char ch[10]; int cnt = 0; while (cnt < 8) { ch[cnt++] = num % 2 + 0 ; num /= 2; } num = 0; for (int i = 0; i < 8; i++) { num = num * 2 + (ch[i] - 0 ); } return num; } int main() { char ch[1000]; gets(ch); int len = strlen(ch); int pre = 0; for (int i = 0; i < len; i++) { int tmp = getNum(ch[i]); cout << (pre - tmp + 10 * 256) % mod << endl; pre = tmp; } return 0; } |
// binary_vga.v
// This file was auto-generated as part of a generation operation.
// If you edit it your changes will probably be lost.
`timescale 1 ps / 1 ps
module binary_vga (
input wire iCLK, // clk.clk
output wire [9:0] VGA_R, // avalon_slave_0_export.export
output wire [9:0] VGA_G, // .export
output wire [9:0] VGA_B, // .export
output wire VGA_HS, // .export
output wire VGA_VS, // .export
output wire VGA_SYNC, // .export
output wire VGA_BLANK, // .export
output wire VGA_CLK, // .export
input wire iCLK_25, // .export
output wire [15:0] oDATA, // avalon_slave_0.readdata
input wire [15:0] iDATA, // .writedata
input wire [18:0] iADDR, // .address
input wire iWR, // .write
input wire iRD, // .read
input wire iCS, // .chipselect
input wire iRST_N // reset_n.reset_n
);
VGA_NIOS_CTRL #(
.RAM_SIZE (307200)
) binary_vga (
.iCLK (iCLK), // clk.clk
.VGA_R (VGA_R), // avalon_slave_0_export.export
.VGA_G (VGA_G), // .export
.VGA_B (VGA_B), // .export
.VGA_HS (VGA_HS), // .export
.VGA_VS (VGA_VS), // .export
.VGA_SYNC (VGA_SYNC), // .export
.VGA_BLANK (VGA_BLANK), // .export
.VGA_CLK (VGA_CLK), // .export
.iCLK_25 (iCLK_25), // .export
.oDATA (oDATA), // avalon_slave_0.readdata
.iDATA (iDATA), // .writedata
.iADDR (iADDR), // .address
.iWR (iWR), // .write
.iRD (iRD), // .read
.iCS (iCS), // .chipselect
.iRST_N (iRST_N) // reset_n.reset_n
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, t; int dp[22][7][7][12][12]; int main() { cin >> n >> t; if (n <= 2) { cout << 0 << endl; return 0; } for (int i = 1; i <= 4; i++) for (int j = 1; j <= 4; j++) if (i != j) dp[2][i][j][0][0] = 1; for (int i = 2; i < n; i++) { for (int j = 0; j <= t; j++) { for (int k = 0; k < t; k++) { for (int a1 = 1; a1 <= 4; a1++) { for (int a2 = 1; a2 <= 4; a2++) { for (int a3 = 1; a3 <= 4; a3++) { if (a1 == a2 || a2 == a3) continue; else if (a1 > a2 && a2 < a3) dp[i + 1][a2][a3][j][k + 1] += dp[i][a1][a2][j][k]; else if (a1 < a2 && a2 > a3) dp[i + 1][a2][a3][j + 1][k] += dp[i][a1][a2][j][k]; else dp[i + 1][a2][a3][j][k] += dp[i][a1][a2][j][k]; } } } } } } int ans = 0; for (int i = 1; i <= 4; i++) for (int j = 1; j <= 4; j++) { ans += dp[n][i][j][t][t - 1]; } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; inline int read() { int l = 0, f = 1; char a = getchar(); for (; a < 0 || a > 9 ; a = getchar()) if (a == - ) f = -1; for (; a >= 0 && a <= 9 ; a = getchar()) l = l * 10 + a - 48; return l * f; } const int N = 300005; int n, ans = 1, last, a[N]; int main(int argc, char const *argv[]) { n = read(); last = n; printf( 1 ); for (int i = 1; i <= n; ++i) { int x = read(); a[x] = 1, ans++; while (a[last]) --last, --ans; printf( %d , ans); } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FA_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__FA_FUNCTIONAL_PP_V
/**
* fa: Full adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__fa (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out ;
wire and1_out ;
wire and2_out ;
wire nor0_out ;
wire nor1_out ;
wire or1_out_COUT ;
wire pwrgood_pp0_out_COUT;
wire or2_out_SUM ;
wire pwrgood_pp1_out_SUM ;
// Name Output Other arguments
or or0 (or0_out , CIN, B );
and and0 (and0_out , or0_out, A );
and and1 (and1_out , B, CIN );
or or1 (or1_out_COUT , and1_out, and0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_COUT, or1_out_COUT, VPWR, VGND);
buf buf0 (COUT , pwrgood_pp0_out_COUT );
and and2 (and2_out , CIN, A, B );
nor nor0 (nor0_out , A, or0_out );
nor nor1 (nor1_out , nor0_out, COUT );
or or2 (or2_out_SUM , nor1_out, and2_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_SUM , or2_out_SUM, VPWR, VGND );
buf buf1 (SUM , pwrgood_pp1_out_SUM );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__FA_FUNCTIONAL_PP_V |
/**************************************************************************
Sync FIFO
-parameter P_N
Queue data vector width
Example : DATA[3:0] is P_N=4
-parameter P_DEPTH
Queue entry depth
Example P_DEPTH 16 is P_DEPTH=16
-parameter P_DEPTH_N
Queue entry depth n size
Example PARAMETER_DEPTH16 is 4
-Make : 2013/2/13
-Update :
Takahiro Ito
**************************************************************************/
`default_nettype none
module gci_std_display_sync_fifo #(
parameter P_N = 16,
parameter P_DEPTH = 4,
parameter P_DEPTH_N = 2
)(
//System
input iCLOCK,
input inRESET,
input iREMOVE,
//Counter
output [P_DEPTH_N:0] oCOUNT,
//WR
input iWR_EN,
input [P_N-1:0] iWR_DATA,
output oWR_FULL,
output oWR_ALMOST_FULL,
//RD
input iRD_EN,
output [P_N-1:0] oRD_DATA,
output oRD_EMPTY,
output oRD_ALMOST_EMPTY
);
//Reg
reg [P_DEPTH_N:0] b_write_pointer;
reg [P_DEPTH_N:0] b_read_pointer;
reg [P_N-1:0] b_memory [0:P_DEPTH-1];
//Wire
wire [P_DEPTH_N:0] count = b_write_pointer - b_read_pointer;
wire full = count[P_DEPTH_N];
wire empty = (count == {P_DEPTH_N+1{1'b0}})? 1'b1 : 1'b0;
wire almost_full = full || (count[P_DEPTH_N-1:0] == {P_DEPTH_N{1'b1}});
wire almost_empty = empty || (count[P_DEPTH_N:0] == {{P_DEPTH_N{1'b0}}, 1'b1});
wire read_condition = iRD_EN && !empty;
wire write_condition = iWR_EN && !full;
/****************************************
Memory / Counter
****************************************/
//Memory
always@(posedge iCLOCK)begin
if(write_condition)begin
b_memory [b_write_pointer[P_DEPTH_N-1:0]] <= iWR_DATA;
end
end //Memory
//Write
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_write_pointer <= {P_DEPTH_N+1{1'b0}};
end
else if(iREMOVE)begin
b_write_pointer <= {P_DEPTH_N+1{1'b0}};
end
else begin
if(write_condition)begin
b_write_pointer <= b_write_pointer + {{P_DEPTH_N-1{1'b0}}, 1'b1};
end
end
end //Write always
//Read
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_read_pointer <= {P_DEPTH_N+1{1'b0}};
end
else if(iREMOVE)begin
b_read_pointer <= {P_DEPTH_N+1{1'b0}};
end
else begin
if(read_condition)begin
b_read_pointer <= b_read_pointer + {{P_DEPTH_N-1{1'b0}}, 1'b1};
end
end
end //Read always
//Assign
assign oRD_DATA = b_memory[b_read_pointer[P_DEPTH_N-1:0]];
assign oRD_EMPTY = empty;
assign oRD_ALMOST_EMPTY = almost_empty;
assign oWR_FULL = full;
assign oWR_ALMOST_FULL = almost_full;
assign oCOUNT = count[P_DEPTH_N:0];
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1000000007; const long long INF = (long long)1000000007 * 1000000007; const long double eps = 1e-8; const long double pi = acos(-1.0); int dx[4] = {1, -1, 0, 0}; int dy[4] = {0, 0, 1, -1}; int n, m, t[200010]; set<int> se[200010]; int e = 0; void merge(int a, int b) { if (se[a].size() < se[b].size()) { swap(se[a], se[b]); } for (int s : se[b]) { auto it1 = se[a].lower_bound(s + 1); if (it1 != se[a].end()) { if (*it1 == s + 1) e -= 1; } auto it2 = se[a].lower_bound(s - 1); if (it2 != se[a].end()) { if (*it2 == s - 1) e -= 1; } } auto it = se[b].begin(); while (!se[b].empty()) { se[a].insert(*it); it = se[b].erase(it); } } void solve() { scanf( %d%d , &n, &m); for (int i = 0; i < n; i++) { scanf( %d , &t[i]); t[i]--; se[t[i]].insert(i); } for (int i = 0; i < n - 1; i++) { e += (t[i] != t[i + 1]); } cout << e << endl; for (int i = 0; i < m - 1; i++) { int a, b; scanf( %d%d , &a, &b); a--; b--; merge(a, b); printf( %d n , e); } } int main() { ios::sync_with_stdio(false); cin.tie(0); cout << fixed << setprecision(50); solve(); } |
(* %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% *)
(* Mainly borrowed from Sofware Foundations, v.4
$Date: 2015-12-11 17:17:29 -0500 (Fri, 11 Dec 2015) $
Last Update: Tue, 30 May 2017
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% *)
(* ***************************************************************** *)
(** * Maps: Total and Partial Maps *)
(* ***************************************************************** *)
(* ***************************************************************** *)
Require Import Identifier.
Require Import Coq.Arith.Arith.
Require Import Coq.Bool.Bool.
Require Import Coq.Logic.FunctionalExtensionality.
(* for t_update proof *)
Require Import Coq.MSets.MSets.
(** Maps (or dictionaries) are ubiquitous data structures, both in
software construction generally and in the theory of programming
languages in particular.
We'll define two flavors of maps: _total_ maps, which include a
"default" element to be returned when a key being looked up
doesn't exist, and _partial_ maps, which return an [option] to
indicate success or failure. The latter is defined in terms of
the former, using [None] as the default element. *)
(* ################################################################# *)
(** * Total Maps *)
(* ################################################################# *)
(** We build partial maps in two steps. First, we define a type of
_total maps_ that return a default value when we look up a key
that is not present in the map. *)
Definition total_map (A : Type) := id -> A.
(** Intuitively, a total map over an element type [A] _is_ just a
function that can be used to look up [id]s, yielding [A]s.
The function [t_empty] yields an empty total map, given a default
element; this map always returns the default element when applied
to any id. *)
Definition t_empty {A : Type} (v : A) : total_map A :=
(fun _ => v).
(** More interesting is the [update] function, which (as before) takes
a map [m], a key [x], and a value [v] and returns a new map that
takes [x] to [v] and takes every other key to whatever [m] does. *)
Definition t_update {A : Type} (m : total_map A)
(x : id) (v : A)
:= fun x' => if beq_id x x' then v else m x'.
(** For building examples easier, we define a function that creates
total map from a list of pairs.
[xs] : list of pairs, [dv] : default value.
*)
Definition t_from_list {A : Type} (xs : list (id * A)) (dv : A) : total_map A
:= fold_left
(fun m xv => match xv with (x, v) => t_update m x v end)
xs (t_empty dv).
(* ----------------------------------------------------------------- *)
(** ** Properties of Total Maps *)
(* ----------------------------------------------------------------- *)
(** First, the empty map returns its default element for all keys: *)
Lemma t_apply_empty: forall A x v, @t_empty A v x = v.
Proof.
intros A x v.
unfold t_empty. reflexivity.
Qed.
(** Next, if we update a map [m] at a key [x] with a new value [v]
and then look up [x] in the map resulting from the [update], we
get back [v]: *)
Lemma t_update_eq : forall A (m : total_map A) x v,
(t_update m x v) x = v.
Proof.
intros A m x v.
unfold t_update. rewrite <- beq_id_refl. reflexivity.
Qed.
(** On the other hand, if we update a map [m] at a key [x1] and then
look up a _different_ key [x2] in the resulting map, we get the
same result that [m] would have given: *)
Theorem t_update_neq : forall (X : Type) v x1 x2
(m : total_map X),
x1 <> x2 ->
(t_update m x1 v) x2 = m x2.
Proof.
intros X v x1 x2 m.
intros neq. unfold t_update.
apply false_beq_id in neq. rewrite -> neq. reflexivity.
Qed.
(** If we update a map [m] at a key [x] with a value [v1] and then
update again with the same key [x] and another value [v2], the
resulting map behaves the same (gives the same result when applied
to any key) as the simpler map obtained by performing just
the second [update] on [m]: *)
Lemma t_update_shadow : forall A (m : total_map A) v1 v2 x,
t_update (t_update m x v1) x v2
= t_update m x v2.
Proof.
intros A M v1 v2 x.
unfold t_update.
apply functional_extensionality. intros x'.
destruct (beq_id x x') eqn:H.
- (* x = x' *) reflexivity.
- (* x <> x' *) reflexivity.
Qed.
(** Using the example in chapter [IndProp] as a template, use
[beq_idP] to prove the following theorem, which states that if we
update a map to assign key [x] the same value as it already has in
[m], then the result is equal to [m]: *)
Theorem t_update_same : forall X x (m : total_map X),
t_update m x (m x) = m.
Proof.
intros X x m. unfold t_update.
apply functional_extensionality. intro x'.
destruct (beq_idP x x') as [H | H].
- rewrite H. reflexivity.
- reflexivity.
Qed.
(** Use [beq_idP] to prove one final property of the [update]
function: If we update a map [m] at two distinct keys, it doesn't
matter in which order we do the updates. *)
Theorem t_update_permute : forall (X:Type) v1 v2 x1 x2
(m : total_map X),
x2 <> x1 ->
(t_update (t_update m x2 v2) x1 v1)
= (t_update (t_update m x1 v1) x2 v2).
Proof.
intros X v1 v2 x1 x2 m.
intros H. apply beq_id_false_iff in H as H'.
unfold t_update. apply functional_extensionality.
intros x. destruct (beq_idP x1 x) as [H1 | H1].
- destruct (beq_idP x2 x) as [H2 | H2].
+ rewrite <- H1 in H2. apply H in H2. inversion H2.
+ reflexivity.
- destruct (beq_idP x2 x) as [H2 | H2].
+ reflexivity.
+ reflexivity.
Qed.
(* ################################################################# *)
(** * Partial Maps *)
(* ################################################################# *)
(** Finally, we define _partial maps_ on top of total maps. A partial
map with elements of type [A] is simply a total map with elements
of type [option A] and default element [None]. *)
Definition partial_map (A : Type) := total_map (option A).
Definition empty {A : Type} : partial_map A :=
t_empty None.
Definition update {A : Type} (m : partial_map A)
(x : id) (v : A) :=
t_update m x (Some v).
(** Similarly to total maps, we define a function for creating
maps from lists. *)
Definition from_list {A : Type} (xs : list (id * A)) : partial_map A
:= fold_left
(fun m xv => match xv with (x, v) => update m x v end)
xs empty.
(** We can now lift all of the basic lemmas about total maps to
partial maps. *)
Lemma apply_empty : forall A x, @empty A x = None.
Proof.
intros. unfold empty. rewrite t_apply_empty.
reflexivity.
Qed.
Lemma update_eq : forall A (m: partial_map A) x v,
(update m x v) x = Some v.
Proof.
intros. unfold update. rewrite t_update_eq.
reflexivity.
Qed.
Theorem update_neq : forall (X:Type) v x1 x2
(m : partial_map X),
x2 <> x1 ->
(update m x2 v) x1 = m x1.
Proof.
intros X v x1 x2 m H.
unfold update. rewrite t_update_neq. reflexivity.
apply H. Qed.
Lemma update_shadow : forall A (m: partial_map A) v1 v2 x,
update (update m x v1) x v2 = update m x v2.
Proof.
intros A m v1 v2 x1. unfold update. rewrite t_update_shadow.
reflexivity.
Qed.
Theorem update_same : forall X v x (m : partial_map X),
m x = Some v ->
update m x v = m.
Proof.
intros X v x m H. unfold update. rewrite <- H.
apply t_update_same.
Qed.
Theorem update_permute : forall (X:Type) v1 v2 x1 x2
(m : partial_map X),
x2 <> x1 ->
(update (update m x2 v2) x1 v1)
= (update (update m x1 v1) x2 v2).
Proof.
intros X v1 v2 x1 x2 m. unfold update.
apply t_update_permute.
Qed.
Theorem update_permute_get :
forall (X : Type) v1 v2 x1 x2 (m : partial_map X) z,
x2 <> x1 ->
(update (update m x2 v2) x1 v1) z
= (update (update m x1 v1) x2 v2) z.
Proof.
intros X v1 v2 x1 x2 m z.
intros Hneq.
rewrite update_permute. reflexivity. assumption.
Qed.
Theorem update_none :
forall (X : Type) x v (m : partial_map X) y,
(update m x v) y = None ->
m y = None.
Proof.
intros X x v m y H.
destruct (beq_idP x y).
+ subst. rewrite update_eq in H.
inversion H.
+ rewrite update_neq in H; assumption.
Qed.
Theorem eq_Some_not_None :
forall (X : Type) x v (m : partial_map X),
m x = Some v -> m x <> None.
Proof.
intros X x v m Heq contra.
rewrite Heq in contra.
inversion contra.
Qed. |
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//-----------------------------------------------------------------------------
//
// Description: AxiLite Slave Conversion
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axilite_conv
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_7_axilite_conv #
(
parameter C_FAMILY = "virtex6",
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_WRITE = 1,
parameter integer C_AXI_SUPPORTS_READ = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1
)
(
// System Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [3-1:0] S_AXI_AWPROT,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER, // Constant =0
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [3-1:0] S_AXI_ARPROT,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST, // Constant =1
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER, // Constant =0
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [3-1:0] M_AXI_AWPROT,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [2-1:0] M_AXI_BRESP,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [3-1:0] M_AXI_ARPROT,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY
);
wire s_awvalid_i;
wire s_arvalid_i;
wire [C_AXI_ADDR_WIDTH-1:0] m_axaddr;
// Arbiter
reg read_active;
reg write_active;
reg busy;
wire read_req;
wire write_req;
wire read_complete;
wire write_complete;
reg [1:0] areset_d; // Reset delay register
always @(posedge ACLK) begin
areset_d <= {areset_d[0], ~ARESETN};
end
assign s_awvalid_i = S_AXI_AWVALID & (C_AXI_SUPPORTS_WRITE != 0);
assign s_arvalid_i = S_AXI_ARVALID & (C_AXI_SUPPORTS_READ != 0);
assign read_req = s_arvalid_i & ~busy & ~|areset_d & ~write_active;
assign write_req = s_awvalid_i & ~busy & ~|areset_d & ((~read_active & ~s_arvalid_i) | write_active);
assign read_complete = M_AXI_RVALID & S_AXI_RREADY;
assign write_complete = M_AXI_BVALID & S_AXI_BREADY;
always @(posedge ACLK) begin : arbiter_read_ff
if (|areset_d)
read_active <= 1'b0;
else if (read_complete)
read_active <= 1'b0;
else if (read_req)
read_active <= 1'b1;
end
always @(posedge ACLK) begin : arbiter_write_ff
if (|areset_d)
write_active <= 1'b0;
else if (write_complete)
write_active <= 1'b0;
else if (write_req)
write_active <= 1'b1;
end
always @(posedge ACLK) begin : arbiter_busy_ff
if (|areset_d)
busy <= 1'b0;
else if (read_complete | write_complete)
busy <= 1'b0;
else if ((write_req & M_AXI_AWREADY) | (read_req & M_AXI_ARREADY))
busy <= 1'b1;
end
assign M_AXI_ARVALID = read_req;
assign S_AXI_ARREADY = M_AXI_ARREADY & read_req;
assign M_AXI_AWVALID = write_req;
assign S_AXI_AWREADY = M_AXI_AWREADY & write_req;
assign M_AXI_RREADY = S_AXI_RREADY & read_active;
assign S_AXI_RVALID = M_AXI_RVALID & read_active;
assign M_AXI_BREADY = S_AXI_BREADY & write_active;
assign S_AXI_BVALID = M_AXI_BVALID & write_active;
// Address multiplexer
assign m_axaddr = (read_req | (C_AXI_SUPPORTS_WRITE == 0)) ? S_AXI_ARADDR : S_AXI_AWADDR;
// Id multiplexer and flip-flop
reg [C_AXI_ID_WIDTH-1:0] s_axid;
always @(posedge ACLK) begin : axid
if (read_req) s_axid <= S_AXI_ARID;
else if (write_req) s_axid <= S_AXI_AWID;
end
assign S_AXI_BID = s_axid;
assign S_AXI_RID = s_axid;
assign M_AXI_AWADDR = m_axaddr;
assign M_AXI_ARADDR = m_axaddr;
// Feed-through signals
assign S_AXI_WREADY = M_AXI_WREADY & ~|areset_d;
assign S_AXI_BRESP = M_AXI_BRESP;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RLAST = 1'b1;
assign S_AXI_BUSER = {C_AXI_BUSER_WIDTH{1'b0}};
assign S_AXI_RUSER = {C_AXI_RUSER_WIDTH{1'b0}};
assign M_AXI_AWPROT = S_AXI_AWPROT;
assign M_AXI_WVALID = S_AXI_WVALID & ~|areset_d;
assign M_AXI_WDATA = S_AXI_WDATA;
assign M_AXI_WSTRB = S_AXI_WSTRB;
assign M_AXI_ARPROT = S_AXI_ARPROT;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long t1, n, zero, one, cnt, cnt1, i, j; string s; cin >> t1; while (t1--) { cin >> n; cnt = 0, zero = 0, one = 0; for (i = 0; i < n; i++) { cin >> s; for (j = 0; j < s.length(); j++) { if (s[j] == 0 ) zero++; else one++; } if (s.length() % 2 != 0) cnt++; } cnt1 = 0; if (zero % 2 != 0) cnt1++; if (one % 2 != 0) cnt1++; if (cnt >= cnt1) cout << n << endl; else cout << n - 1 << endl; } } |
#include <bits/stdc++.h> using namespace std; int k; int n1, n2, n3; int t1, t2, t3; int v1[3000]; int v2[3030]; int v3[3030]; int main() { ios::sync_with_stdio(false); cin >> k >> n1 >> n2 >> n3 >> t1 >> t2 >> t3; int time = t1 + t2 + t3 - 1; int pos = 0; int res = 0; for (int i = 0; i <= time + 1; i++) { v1[i] = 0; v2[i] = 0; v3[i] = 0; } for (int i = 1; i <= k; i++) { int posnew = -1; for (int j = pos; j <= pos + time + 1; j++) { int kk = j - pos; if ((v1[kk] + 1 <= n1) && ((kk + t1 > time + 1) || (v2[kk + t1] + 1 <= n2)) && ((kk + t1 + t2 > time + 1) || (v3[kk + t1 + t2] + 1 <= n3))) { posnew = j; break; } } int t = min(pos + time + 1, posnew + time); for (int j = posnew; j <= t; j++) { if (j <= posnew + t1 - 1) v1[j - pos]++; else if (j <= posnew + t1 + t2 - 1) v2[j - pos]++; else v3[j - pos]++; v1[j - posnew] = v1[j - pos]; v2[j - posnew] = v2[j - pos]; v3[j - posnew] = v3[j - pos]; } for (int j = t + 1; j <= posnew + time; j++) { if (j <= posnew + t1 - 1) { v1[j - posnew] = 1; v2[j - posnew] = 0; v3[j - posnew] = 0; } else if (j <= posnew + t1 + t2 - 1) { v2[j - posnew] = 1; v1[j - posnew] = 0; v3[j - posnew] = 0; } else { v3[j - posnew] = 1; v1[j - posnew] = 0; v2[j - posnew] = 0; } } v1[time + 1] = 0; v2[time + 1] = 0; v3[time + 1] = 0; res = posnew + time; pos = posnew; } cout << res + 1; return 0; } |
#include <bits/stdc++.h> using namespace std; const double g = 9.8; const double eps = 1e-9; int n, m, v; struct Ques { double angle; int id; } ques[10010]; struct Wall { double x, y; } wall[100010]; double ans_x[10010], ans_y[10010]; bool cmp(const Ques &a, const Ques &b) { return a.angle < b.angle; } bool cmp2(const Wall &a, const Wall &b) { return a.x < b.x; } int main() { scanf( %d%d , &n, &v); for (int i = 1; i <= n; i++) { scanf( %lf , &ques[i].angle); ques[i].id = i; } scanf( %d , &m); for (int i = 1; i <= m; i++) scanf( %lf%lf , &wall[i].x, &wall[i].y); sort(ques + 1, ques + n + 1, cmp); sort(wall + 1, wall + m + 1, cmp2); int h = 1; for (int i = 1; i <= n; i++) { double v_y = v * sin(ques[i].angle), v_x = v * cos(ques[i].angle); while (h <= m) { double time = wall[h].x / v_x; double y = v_y * time - 0.5 * g * time * time; if (y < eps) { ans_x[ques[i].id] = v_x * (v_y / (0.5 * g)); ans_y[ques[i].id] = 0; break; } else if (y < wall[h].y + eps) { ans_x[ques[i].id] = wall[h].x; ans_y[ques[i].id] = y; break; } else h++; } } for (int i = 1; i <= n; i++) if (ans_x[ques[i].id] < eps) { double v_y = v * sin(ques[i].angle), v_x = v * cos(ques[i].angle); ans_x[ques[i].id] = v_x * (v_y / (0.5 * g)); ans_y[ques[i].id] = 0; } for (int i = 1; i <= n; i++) printf( %.9lf %.9lf n , ans_x[i], ans_y[i]); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int t; cin >> t; while (t--) { long long int n, a, b, x, y; cin >> n; x = 1 + (n - 1) / 3; long long int sum = 0, k = 1; while (sum < x) { sum += k; k <<= 2; } k >>= 2; sum -= k; y = a = (x - sum - 1 + k); int c[] = {0, 2, 3, 1}; k = 1, b = 0; while (y) { b += c[y % 4] * k; k <<= 2; y >>= 2; } x = a ^ b; if (n % 3 == 1) { cout << a << endl; } else if (n % 3 == 2) { cout << b << endl; } else cout << x << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; struct Node { pair<int, int> A; int x, y; Node() {} Node(pair<int, int> A, int x, int y) { this->A = A; this->x = x; this->y = y; } }; char s[1001][1001]; int sp[10], cur, ans[10]; Node heap[1000001]; void swap(Node& a, Node& b) { Node t = a; a = b; b = t; } bool cmp(Node a, Node b) { int val_a = a.A.first / sp[a.A.second]; int val_b = b.A.first / sp[b.A.second]; if (val_a != val_b) return val_a < val_b; else if (a.A.second != b.A.second) return a.A.second < b.A.second; else return a.A.first < b.A.first; } void push(Node x) { int now = cur++; heap[now] = x; while (now > 1) { int par = now / 2; if (cmp(heap[now], heap[par])) swap(heap[now], heap[par]); else break; now = par; } return; } Node pop() { Node ret = heap[1]; heap[1] = heap[--cur]; int now = 1; while (now * 2 < cur) { int l = now * 2, r = now * 2 + 1, t; if (r == cur) r = l; if (cmp(heap[l], heap[r])) t = l; else t = r; if (cmp(heap[t], heap[now])) swap(heap[t], heap[now]); else break; now = t; } return ret; } int dx[4] = {1, 0, 0, -1}; int dy[4] = {0, 1, -1, 0}; int main() { int n, m, p; cur = 1; scanf( %d %d %d , &n, &m, &p); for (int i = 1; i <= p; i++) scanf( %d , &sp[i]); for (int i = 0; i < n; i++) scanf( %s , s[i]); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { if (s[i][j] >= 0 && s[i][j] <= 9 ) { push(Node(pair<int, int>(0, s[i][j] - 0 ), i, j)); } } while (cur > 1) { Node now = pop(); pair<int, int> A = now.A; int x = now.x, y = now.y; int cnt = A.first, who = A.second; for (int i = 0; i < 4; i++) { int nx = x + dx[i], ny = y + dy[i]; if (nx < 0 || ny < 0 || nx >= n || ny >= m || s[nx][ny] != . ) continue; s[nx][ny] = 0 + who; push(Node(pair<int, int>(cnt + 1, who), nx, ny)); } } for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { if (s[i][j] >= 0 && s[i][j] <= 9 ) { ans[s[i][j] - 0 ]++; } } for (int i = 1; i <= p; i++) printf( %d , ans[i]); return 0; } |
#include <bits/stdc++.h> using namespace std; int b[10][10]; char c[10][4][4]; int main() { char ch; int x = 1, y = 1, x1, y1, l, z, i, j, r; x1 = 3, y1 = 3; for (i = 1; i <= 9; ++i) { if (i > x1) ++x, x1 += 3; y1 = 3; y = 1; for (j = 1; j <= 9; ++j) { if (j % 3 == 0) r = 3; else r = j % 3; if (i % 3 == 0) l = 3; else l = i % 3; if (j > y1) ++y, y1 += 3; cin >> c[x * 3 - (3 - y)][l][r]; } } cin >> x >> y; if (x % 3 == 0) x = 3; else x %= 3; if (y % 3 == 0) y = 3; else y %= 3; bool nu = 1; for (i = 1; i <= 3 && nu; ++i) { for (j = 1; j < 3; ++j) { if (c[x * 3 - (3 - y)][i][j] == . ) nu = 0; } } if (nu) { x1 = 3, y1 = 3; x = y = 1; for (i = 1; i <= 9; ++i) { if (i > x1) ++x, x1 += 3, cout << n ; y1 = 3; y = 1; for (j = 1; j <= 9; ++j) { if (j % 3 == 0) r = 3; else r = j % 3; if (i % 3 == 0) l = 3; else l = i % 3; if (j > y1) ++y, y1 += 3, cout << ; if (c[x * 3 - (3 - y)][l][r] == . ) cout << ! ; else cout << c[x * 3 - (3 - y)][l][r]; } cout << n ; } } else { int x3 = x, y3 = y; x1 = 3, y1 = 3; x = y = 1; for (i = 1; i <= 9; ++i) { if (i > x1) ++x, x1 += 3, cout << n ; y1 = 3; y = 1; for (j = 1; j <= 9; ++j) { if (j % 3 == 0) r = 3; else r = j % 3; if (i % 3 == 0) l = 3; else l = i % 3; if (j > y1) ++y, y1 += 3, cout << ; if (x3 == x && y3 == y) { if (c[x * 3 - (3 - y)][l][r] == . ) cout << ! ; else cout << c[x * 3 - (3 - y)][l][r]; } else cout << c[x * 3 - (3 - y)][l][r]; } cout << n ; } } return 0; } |
//////////////////////////////////////////////////////////////////
// //
// Register Bank for Amber Core //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// Contains 37 32-bit registers, 16 of which are visible //
// ina any one operating mode. Registers use real flipflops, //
// rather than SRAM. This makes sense for an FPGA //
// implementation, where flipflops are plentiful. //
// //
// Author(s): //
// - Conor Santifort, //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
module a23_register_bank (
input i_clk,
input i_rst,
input [3:0] i_rm_sel,
input [3:0] i_rds_sel,
input [3:0] i_rn_sel,
input i_pc_wen,
input [14:0] i_reg_bank_wen,
input [23:0] i_pc, // program counter [25:2]
input [31:0] i_reg,
input [3:0] i_status_bits_flags,
output [31:0] o_rm,
output reg [31:0] o_rs,
output reg [31:0] o_rd,
output [31:0] o_rn,
output [31:0] o_pc
);
`include "a23_localparams.vh"
`include "a23_functions.vh"
reg [31:0] r0 ;
reg [31:0] r1 ;
reg [31:0] r2 ;
reg [31:0] r3 ;
reg [31:0] r4 ;
reg [31:0] r5 ;
reg [31:0] r6 ;
reg [31:0] r7 ;
reg [31:0] r8 ;
reg [31:0] r9 ;
reg [31:0] r10 ;
reg [31:0] r11 ;
reg [31:0] r12 ;
reg [31:0] r13 ;
reg [31:0] r14 ;
reg [23:0] r15 ;
wire [31:0] r0_out;
wire [31:0] r1_out;
wire [31:0] r2_out;
wire [31:0] r3_out;
wire [31:0] r4_out;
wire [31:0] r5_out;
wire [31:0] r6_out;
wire [31:0] r7_out;
wire [31:0] r8_out;
wire [31:0] r9_out;
wire [31:0] r10_out;
wire [31:0] r11_out;
wire [31:0] r12_out;
wire [31:0] r13_out;
wire [31:0] r14_out;
wire [31:0] r15_out_rm;
wire [31:0] r15_out_rm_nxt;
wire [31:0] r15_out_rn;
wire [31:0] r8_rds;
wire [31:0] r9_rds;
wire [31:0] r10_rds;
wire [31:0] r11_rds;
wire [31:0] r12_rds;
wire [31:0] r13_rds;
wire [31:0] r14_rds;
// ========================================================
// Register Update
// ========================================================
always @ ( posedge i_clk or posedge i_rst)
if (i_rst) begin
r0 <= 'd0;
r1 <= 'd0;
r2 <= 'd0;
r3 <= 'd0;
r4 <= 'd0;
r5 <= 'd0;
r6 <= 'd0;
r7 <= 'd0;
r8 <= 'd0;
r9 <= 'd0;
r10 <= 'd0;
r11 <= 'd0;
r12 <= 'd0;
r13 <= 'd0;
r14 <= 'd0;
r15 <= 24'h0;
end else begin
r0 <= i_reg_bank_wen[0 ] ? i_reg : r0;
r1 <= i_reg_bank_wen[1 ] ? i_reg : r1;
r2 <= i_reg_bank_wen[2 ] ? i_reg : r2;
r3 <= i_reg_bank_wen[3 ] ? i_reg : r3;
r4 <= i_reg_bank_wen[4 ] ? i_reg : r4;
r5 <= i_reg_bank_wen[5 ] ? i_reg : r5;
r6 <= i_reg_bank_wen[6 ] ? i_reg : r6;
r7 <= i_reg_bank_wen[7 ] ? i_reg : r7;
r8 <= i_reg_bank_wen[8 ] ? i_reg : r8;
r9 <= i_reg_bank_wen[9 ] ? i_reg : r9;
r10 <= i_reg_bank_wen[10] ? i_reg : r10;
r11 <= i_reg_bank_wen[11] ? i_reg : r11;
r12 <= i_reg_bank_wen[12] ? i_reg : r12;
r13 <= i_reg_bank_wen[13] ? i_reg : r13;
r14 <= i_reg_bank_wen[14] ? i_reg : r14;
r15 <= i_pc_wen ? i_pc : r15;
end
// ========================================================
// Register Read based on Mode
// ========================================================
assign r0_out = r0;
assign r1_out = r1;
assign r2_out = r2;
assign r3_out = r3;
assign r4_out = r4;
assign r5_out = r5;
assign r6_out = r6;
assign r7_out = r7;
assign r8_out = r8;
assign r9_out = r9;
assign r10_out = r10;
assign r11_out = r11;
assign r12_out = r12;
assign r13_out = r13;
assign r14_out = r14;
assign r15_out_rm = { i_status_bits_flags,
1'b1,
1'b1,
r15,
2'b0};
assign r15_out_rm_nxt = { i_status_bits_flags,
1'b1,
1'b1,
i_pc,
2'b0};
assign r15_out_rn = {6'd0, r15, 2'd0};
// rds outputs
assign r8_rds = r8;
assign r9_rds = r9;
assign r10_rds = r10;
assign r11_rds = r11;
assign r12_rds = r12;
assign r13_rds = r13;
assign r14_rds = r14;
// ========================================================
// Program Counter out
// ========================================================
assign o_pc = r15_out_rn;
// ========================================================
// Rm Selector
// ========================================================
assign o_rm = i_rm_sel == 4'd0 ? r0_out :
i_rm_sel == 4'd1 ? r1_out :
i_rm_sel == 4'd2 ? r2_out :
i_rm_sel == 4'd3 ? r3_out :
i_rm_sel == 4'd4 ? r4_out :
i_rm_sel == 4'd5 ? r5_out :
i_rm_sel == 4'd6 ? r6_out :
i_rm_sel == 4'd7 ? r7_out :
i_rm_sel == 4'd8 ? r8_out :
i_rm_sel == 4'd9 ? r9_out :
i_rm_sel == 4'd10 ? r10_out :
i_rm_sel == 4'd11 ? r11_out :
i_rm_sel == 4'd12 ? r12_out :
i_rm_sel == 4'd13 ? r13_out :
i_rm_sel == 4'd14 ? r14_out :
r15_out_rm ;
// ========================================================
// Rds Selector
// ========================================================
always @*
case (i_rds_sel)
4'd0 : o_rs = r0_out ;
4'd1 : o_rs = r1_out ;
4'd2 : o_rs = r2_out ;
4'd3 : o_rs = r3_out ;
4'd4 : o_rs = r4_out ;
4'd5 : o_rs = r5_out ;
4'd6 : o_rs = r6_out ;
4'd7 : o_rs = r7_out ;
4'd8 : o_rs = r8_rds ;
4'd9 : o_rs = r9_rds ;
4'd10 : o_rs = r10_rds ;
4'd11 : o_rs = r11_rds ;
4'd12 : o_rs = r12_rds ;
4'd13 : o_rs = r13_rds ;
4'd14 : o_rs = r14_rds ;
default: o_rs = r15_out_rn ;
endcase
// ========================================================
// Rd Selector
// ========================================================
always @*
case (i_rds_sel)
4'd0 : o_rd = r0_out ;
4'd1 : o_rd = r1_out ;
4'd2 : o_rd = r2_out ;
4'd3 : o_rd = r3_out ;
4'd4 : o_rd = r4_out ;
4'd5 : o_rd = r5_out ;
4'd6 : o_rd = r6_out ;
4'd7 : o_rd = r7_out ;
4'd8 : o_rd = r8_rds ;
4'd9 : o_rd = r9_rds ;
4'd10 : o_rd = r10_rds ;
4'd11 : o_rd = r11_rds ;
4'd12 : o_rd = r12_rds ;
4'd13 : o_rd = r13_rds ;
4'd14 : o_rd = r14_rds ;
default: o_rd = r15_out_rm_nxt ;
endcase
// ========================================================
// Rn Selector
// ========================================================
assign o_rn = i_rn_sel == 4'd0 ? r0_out :
i_rn_sel == 4'd1 ? r1_out :
i_rn_sel == 4'd2 ? r2_out :
i_rn_sel == 4'd3 ? r3_out :
i_rn_sel == 4'd4 ? r4_out :
i_rn_sel == 4'd5 ? r5_out :
i_rn_sel == 4'd6 ? r6_out :
i_rn_sel == 4'd7 ? r7_out :
i_rn_sel == 4'd8 ? r8_out :
i_rn_sel == 4'd9 ? r9_out :
i_rn_sel == 4'd10 ? r10_out :
i_rn_sel == 4'd11 ? r11_out :
i_rn_sel == 4'd12 ? r12_out :
i_rn_sel == 4'd13 ? r13_out :
i_rn_sel == 4'd14 ? r14_out :
r15_out_rn ;
endmodule
|
// cog_ctr
/*
-------------------------------------------------------------------------------
Copyright 2014 Parallax Inc.
This file is part of the hardware description for the Propeller 1 Design.
The Propeller 1 Design is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by the
Free Software Foundation, either version 3 of the License, or (at your option)
any later version.
The Propeller 1 Design is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
the Propeller 1 Design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
*/
module cog_ctr
(
input clk_cog,
input clk_pll,
input ena,
input setctr,
input setfrq,
input setphs,
input [31:0] data,
input [31:0] pin_in,
output reg [32:0] phs,
output [31:0] pin_out,
output pll
);
// control
reg [31:0] ctr;
reg [31:0] frq;
always @(posedge clk_cog or negedge ena)
if (!ena)
ctr <= 32'b0;
else if (setctr)
ctr <= data;
always @(posedge clk_cog)
if (setfrq)
frq <= data;
always @(posedge clk_cog)
if (setphs || trig)
phs <= setphs ? {1'b0, data} : {1'b0, phs[31:0]} + {1'b0, frq};
// input pins
reg [1:0] dly;
always @(posedge clk_cog)
if (|ctr[30:29])
dly <= {ctr[30] ? pin_in[ctr[13:9]] : dly[0], pin_in[ctr[4:0]]};
// trigger, outputs
// trigger outb outa
wire [15:0][2:0] tp = { dly == 2'b10, !dly[0], 1'b0, // neg edge w/feedback
dly == 2'b10, 1'b0, 1'b0, // neg edge
!dly[0], !dly[0], 1'b0, // neg w/feedback
!dly[0], 1'b0, 1'b0, // neg
dly == 2'b01, !dly[0], 1'b0, // pos edge w/feedback
dly == 2'b01, 1'b0, 1'b0, // pos edge
dly[0], !dly[0], 1'b0, // pos w/feedback
dly[0], 1'b0, 1'b0, // pos
1'b1, !phs[32], phs[32], // duty differential
1'b1, 1'b0, phs[32], // duty single
1'b1, !phs[31], phs[31], // nco differential
1'b1, 1'b0, phs[31], // nco single
1'b1, !pll, pll, // pll differential
1'b1, 1'b0, pll, // pll single
1'b1, 1'b0, 1'b0, // pll internal
1'b0, 1'b0, 1'b0 }; // off
wire [3:0] pick = ctr[29:26];
wire [2:0] tba = tp[pick];
wire trig = ctr[30] ? pick[dly] : tba[2]; // trigger
wire outb = ctr[30] ? 1'b0 : tba[1]; // outb
wire outa = ctr[30] ? 1'b0 : tba[0]; // outa
// output pins
assign pin_out = outb << ctr[13:9] | outa << ctr[4:0];
// pll simulator
reg [35:0] pll_fake;
always @(posedge clk_pll)
if (~|ctr[30:28] && |ctr[27:26])
pll_fake <= pll_fake + {4'b0, frq};
wire [7:0] pll_taps = pll_fake[35:28];
assign pll = pll_taps[~ctr[25:23]];
endmodule
|
//Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2016.2 (lin64) Build Thu Jun 2 16:32:35 MDT 2016
//Date : Wed Jul 20 13:44:49 2016
//Host : andrewandrepowell2-desktop running 64-bit Ubuntu 16.04 LTS
//Command : generate_target block_design_wrapper.bd
//Design : block_design_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module block_design_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
leds,
pbs,
sws);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
output [3:0]leds;
input [3:0]pbs;
input [3:0]sws;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
wire [3:0]leds;
wire [3:0]pbs;
wire [3:0]sws;
block_design block_design_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
.leds(leds),
.pbs(pbs),
.sws(sws));
endmodule
|
`timescale 1 ns / 1 ps
module myip_v1_0 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 4,
// Parameters of Axi Slave Bus Interface S01_AXI
parameter integer C_S01_AXI_ID_WIDTH = 1,
parameter integer C_S01_AXI_DATA_WIDTH = 32,
parameter integer C_S01_AXI_ADDR_WIDTH = 6,
parameter integer C_S01_AXI_AWUSER_WIDTH = 0,
parameter integer C_S01_AXI_ARUSER_WIDTH = 0,
parameter integer C_S01_AXI_WUSER_WIDTH = 0,
parameter integer C_S01_AXI_RUSER_WIDTH = 0,
parameter integer C_S01_AXI_BUSER_WIDTH = 0
)
(
// Users to add ports here
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready,
// Ports of Axi Slave Bus Interface S01_AXI
input wire s01_axi_aclk,
input wire s01_axi_aresetn,
input wire [C_S01_AXI_ID_WIDTH-1 : 0] s01_axi_awid,
input wire [C_S01_AXI_ADDR_WIDTH-1 : 0] s01_axi_awaddr,
input wire [7 : 0] s01_axi_awlen,
input wire [2 : 0] s01_axi_awsize,
input wire [1 : 0] s01_axi_awburst,
input wire s01_axi_awlock,
input wire [3 : 0] s01_axi_awcache,
input wire [2 : 0] s01_axi_awprot,
input wire [3 : 0] s01_axi_awqos,
input wire [3 : 0] s01_axi_awregion,
input wire [C_S01_AXI_AWUSER_WIDTH-1 : 0] s01_axi_awuser,
input wire s01_axi_awvalid,
output wire s01_axi_awready,
input wire [C_S01_AXI_DATA_WIDTH-1 : 0] s01_axi_wdata,
input wire [(C_S01_AXI_DATA_WIDTH/8)-1 : 0] s01_axi_wstrb,
input wire s01_axi_wlast,
input wire [C_S01_AXI_WUSER_WIDTH-1 : 0] s01_axi_wuser,
input wire s01_axi_wvalid,
output wire s01_axi_wready,
output wire [C_S01_AXI_ID_WIDTH-1 : 0] s01_axi_bid,
output wire [1 : 0] s01_axi_bresp,
output wire [C_S01_AXI_BUSER_WIDTH-1 : 0] s01_axi_buser,
output wire s01_axi_bvalid,
input wire s01_axi_bready,
input wire [C_S01_AXI_ID_WIDTH-1 : 0] s01_axi_arid,
input wire [C_S01_AXI_ADDR_WIDTH-1 : 0] s01_axi_araddr,
input wire [7 : 0] s01_axi_arlen,
input wire [2 : 0] s01_axi_arsize,
input wire [1 : 0] s01_axi_arburst,
input wire s01_axi_arlock,
input wire [3 : 0] s01_axi_arcache,
input wire [2 : 0] s01_axi_arprot,
input wire [3 : 0] s01_axi_arqos,
input wire [3 : 0] s01_axi_arregion,
input wire [C_S01_AXI_ARUSER_WIDTH-1 : 0] s01_axi_aruser,
input wire s01_axi_arvalid,
output wire s01_axi_arready,
output wire [C_S01_AXI_ID_WIDTH-1 : 0] s01_axi_rid,
output wire [C_S01_AXI_DATA_WIDTH-1 : 0] s01_axi_rdata,
output wire [1 : 0] s01_axi_rresp,
output wire s01_axi_rlast,
output wire [C_S01_AXI_RUSER_WIDTH-1 : 0] s01_axi_ruser,
output wire s01_axi_rvalid,
input wire s01_axi_rready
);
// Instantiation of Axi Bus Interface S00_AXI
myip_v1_0_S00_AXI # (
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) myip_v1_0_S00_AXI_inst (
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready)
);
// Instantiation of Axi Bus Interface S01_AXI
myip_v1_0_S01_AXI # (
.C_S_AXI_ID_WIDTH(C_S01_AXI_ID_WIDTH),
.C_S_AXI_DATA_WIDTH(C_S01_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S01_AXI_ADDR_WIDTH),
.C_S_AXI_AWUSER_WIDTH(C_S01_AXI_AWUSER_WIDTH),
.C_S_AXI_ARUSER_WIDTH(C_S01_AXI_ARUSER_WIDTH),
.C_S_AXI_WUSER_WIDTH(C_S01_AXI_WUSER_WIDTH),
.C_S_AXI_RUSER_WIDTH(C_S01_AXI_RUSER_WIDTH),
.C_S_AXI_BUSER_WIDTH(C_S01_AXI_BUSER_WIDTH)
) myip_v1_0_S01_AXI_inst (
.S_AXI_ACLK(s01_axi_aclk),
.S_AXI_ARESETN(s01_axi_aresetn),
.S_AXI_AWID(s01_axi_awid),
.S_AXI_AWADDR(s01_axi_awaddr),
.S_AXI_AWLEN(s01_axi_awlen),
.S_AXI_AWSIZE(s01_axi_awsize),
.S_AXI_AWBURST(s01_axi_awburst),
.S_AXI_AWLOCK(s01_axi_awlock),
.S_AXI_AWCACHE(s01_axi_awcache),
.S_AXI_AWPROT(s01_axi_awprot),
.S_AXI_AWQOS(s01_axi_awqos),
.S_AXI_AWREGION(s01_axi_awregion),
.S_AXI_AWUSER(s01_axi_awuser),
.S_AXI_AWVALID(s01_axi_awvalid),
.S_AXI_AWREADY(s01_axi_awready),
.S_AXI_WDATA(s01_axi_wdata),
.S_AXI_WSTRB(s01_axi_wstrb),
.S_AXI_WLAST(s01_axi_wlast),
.S_AXI_WUSER(s01_axi_wuser),
.S_AXI_WVALID(s01_axi_wvalid),
.S_AXI_WREADY(s01_axi_wready),
.S_AXI_BID(s01_axi_bid),
.S_AXI_BRESP(s01_axi_bresp),
.S_AXI_BUSER(s01_axi_buser),
.S_AXI_BVALID(s01_axi_bvalid),
.S_AXI_BREADY(s01_axi_bready),
.S_AXI_ARID(s01_axi_arid),
.S_AXI_ARADDR(s01_axi_araddr),
.S_AXI_ARLEN(s01_axi_arlen),
.S_AXI_ARSIZE(s01_axi_arsize),
.S_AXI_ARBURST(s01_axi_arburst),
.S_AXI_ARLOCK(s01_axi_arlock),
.S_AXI_ARCACHE(s01_axi_arcache),
.S_AXI_ARPROT(s01_axi_arprot),
.S_AXI_ARQOS(s01_axi_arqos),
.S_AXI_ARREGION(s01_axi_arregion),
.S_AXI_ARUSER(s01_axi_aruser),
.S_AXI_ARVALID(s01_axi_arvalid),
.S_AXI_ARREADY(s01_axi_arready),
.S_AXI_RID(s01_axi_rid),
.S_AXI_RDATA(s01_axi_rdata),
.S_AXI_RRESP(s01_axi_rresp),
.S_AXI_RLAST(s01_axi_rlast),
.S_AXI_RUSER(s01_axi_ruser),
.S_AXI_RVALID(s01_axi_rvalid),
.S_AXI_RREADY(s01_axi_rready)
);
// Add user logic here
// User logic ends
endmodule
|
#include <bits/stdc++.h> const long long MOD1 = 998244353, MOD2 = 1000000007; long long POWER_MOD1[300001], POWER_MOD2[300001]; struct node { long long hash1_MOD1, hash1_MOD2, hash2_MOD1, hash2_MOD2; int len; } T[1048576], single[2] = {(node){0, 0, 0, 0, 1}, (node){1, 1, 1, 1, 1}}; inline node operator+(const node &a, const node &b) { return (node){(a.hash1_MOD1 + POWER_MOD1[a.len] * b.hash1_MOD1) % MOD1, (a.hash1_MOD2 + POWER_MOD2[a.len] * b.hash1_MOD2) % MOD2, (b.hash2_MOD1 + POWER_MOD1[b.len] * a.hash2_MOD1) % MOD1, (b.hash2_MOD2 + POWER_MOD2[b.len] * a.hash2_MOD2) % MOD2, a.len + b.len}; } int N, a[300001]; node G(int p, int l, int r, int L, int R) { if (L <= l && r <= R) return T[p]; int m = l + r >> 1; if (R <= m) return G(p << 1, l, m, L, R); if (L > m) return G(p << 1 | 1, m + 1, r, L, R); return G(p << 1, l, m, L, R) + G(p << 1 | 1, m + 1, r, L, R); } void P(int x, int w) { int p = 1, l = 1, r = N; while (l < r) { int m = l + r >> 1; if (x <= m) p <<= 1, r = m; else p = p << 1 | 1, l = m + 1; } T[p] = single[w]; while (p >>= 1) T[p] = T[p << 1] + T[p << 1 | 1]; } void build(int p, int l, int r) { if (l == r) { T[p] = single[0]; return; } int m = l + r >> 1; build(p << 1, l, m); build(p << 1 | 1, m + 1, r); T[p] = T[p << 1] + T[p << 1 | 1]; } int main() { scanf( %d , &N); POWER_MOD1[0] = POWER_MOD2[0] = 1; for (int i = 1; i <= N; i++) { scanf( %d , a + i); POWER_MOD1[i] = POWER_MOD1[i - 1] * 2 % MOD1; POWER_MOD2[i] = POWER_MOD2[i - 1] * 2 % MOD2; } build(1, 1, N); for (int i = 1; i <= N; i++) { int len = std::min(a[i] - 1, N - a[i]); node H = G(1, 1, N, a[i] - len, a[i] + len); if (H.hash1_MOD1 != H.hash2_MOD1 || H.hash1_MOD2 != H.hash2_MOD2) { puts( YES ); return 0; } P(a[i], 1); } puts( NO ); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int x, y, z; cin >> x >> y >> z; if (x > y + z) cout << + << endl; else if (y > x + z) cout << - << endl; else if (x == y && z == 0) cout << 0 << endl; else cout << ? << endl; return 0; } |
// MBT 11/10/14
//
// bsg_round_robin_n_to_1
//
// this is intended to merge the outputs of several fifos
// together to act as one.
//
// assumes a valid yumi interface
//
// strict_p: determines whether the round_robin
// module blocks until the head FIFO is valid, or if it just
// goes to the next one.
//
//
`include "bsg_defines.v"
module bsg_round_robin_n_to_1 #(parameter `BSG_INV_PARAM(width_p )
,parameter `BSG_INV_PARAM(num_in_p )
,parameter `BSG_INV_PARAM(strict_p )
,parameter use_scan_p = 0
,parameter tag_width_lp = `BSG_SAFE_CLOG2(num_in_p)
)
(input clk_i
, input reset_i
// to fifos
, input [num_in_p-1:0][width_p-1:0] data_i
, input [num_in_p-1:0] v_i
, output [num_in_p-1:0] yumi_o
// to downstream
, output v_o
, output [width_p-1:0] data_o
, output [tag_width_lp-1:0] tag_o
, input yumi_i
);
if (strict_p)
begin : strict
wire [tag_width_lp-1:0] ptr_r;
bsg_circular_ptr #(.slots_p(num_in_p)
,.max_add_p(1)
) circular_ptr
(.clk (clk_i )
,.reset_i(reset_i)
,.add_i (yumi_i )
,.o (ptr_r )
,.n_o ()
);
assign v_o = v_i [ptr_r];
assign data_o = data_i [ptr_r];
assign tag_o = ptr_r;
// binary to one hot
assign yumi_o = (num_in_p) ' (yumi_i << tag_o);
end
else
begin : greedy
wire [num_in_p-1:0] grants_lo;
// we have valid output if any input is valid
// we do not need the arb to determine this
// the signal yumi_i is computed from this
// assign v_o = | v_i;
if (use_scan_p) begin: scan1
// scan version
bsg_arb_round_robin #(
.width_p(num_in_p)
) rr (
.clk_i (clk_i)
,.reset_i (reset_i)
,.reqs_i (v_i)
,.grants_o (grants_lo)
,.yumi_i (yumi_i)
);
assign v_o = | v_i;
bsg_encode_one_hot #(
.width_p(num_in_p)
) enc (
.i(grants_lo)
,.addr_o(tag_o)
,.v_o()
);
end
else begin: scan0
bsg_round_robin_arb #(.inputs_p(num_in_p))
rr_arb_ctrl
(.clk_i
,.reset_i
,.grants_en_i(1'b1)
// "data plane"
,.reqs_i (v_i ) // from each of the nodes
,.grants_o (grants_lo)
,.sel_one_hot_o()
,.v_o ( v_o )
,.tag_o (tag_o )
,.yumi_i (yumi_i & v_o ) // based on v_o, downstream
// node decides if it will accept
);
end
bsg_crossbar_o_by_i #(.i_els_p (num_in_p)
,.o_els_p(1 )
,.width_p(width_p)
) xbar
(.i (data_i )
,.sel_oi_one_hot_i(grants_lo)
,.o (data_o )
);
// mask grants with yumi signal
assign yumi_o = grants_lo & { num_in_p { yumi_i }};
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_round_robin_n_to_1)
|
#include <bits/stdc++.h> using namespace std; int main() { long long n; cin >> n; if (n == 1) { cout << 1 n0 1 n0 n1 ; return 0; } vector<long long> p1, p2; p1.push_back(1); p1.push_back(0); p2.push_back(1); for (long long i = 1; i < n; i++) { vector<long long> temp = p1; p1.push_back(0); for (long long j = 0; j < p2.size(); j++) { p1[j + 2] += p2[j]; p1[j + 2] %= 2LL; } p2 = temp; } reverse(p1.begin(), p1.end()); reverse(p2.begin(), p2.end()); cout << p1.size() - 1 << n ; for (long long i = 0; i < p1.size(); i++) cout << p1[i] << ; cout << n ; cout << p2.size() - 1 << n ; for (long long i = 0; i < p2.size(); i++) cout << p2[i] << ; } |
#include <bits/stdc++.h> using namespace std; int t, a, b; void fn() { cin >> a >> b; if (a < b) swap(a, b); a -= b; int ans = a / 5; a %= 5; if (a == 1 || a == 2) ans++; else if (a == 3 || a == 4) ans += 2; cout << ans << endl; } int main() { cin >> t; while (t--) fn(); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__TAPVGND2_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__TAPVGND2_BEHAVIORAL_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection 2
* rows down.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__tapvgnd2 ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__TAPVGND2_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; const long double eps = 1e-9; const int inf = (1 << 30) - 1; const long long inf64 = ((long long)1 << 62) - 1; const long double pi = acos(-1); template <class T> T sqr(T x) { return x * x; } template <class T> T abs(T x) { return x < 0 ? -x : x; } template <class T> vector<T> ReadVector(int n) { vector<T> a(n); for (int i = 0; i < n; ++i) { cin >> a[i]; } return a; } template <class T> void WriteVector(const vector<T>& a) { for (int i = 0; i < ((int)(a).size()); ++i) { cout << a[i] << (i + 1 < ((int)(a).size()) ? : n ); } } void Solve() { long long x; cin >> x; vector<long long> a; a.push_back(x); vector<string> res; while (a[0] != 1) { long long val = -1; for (int i = 0; i < ((int)(a).size()); ++i) { for (int j = 0; j <= i; ++j) { long long tmp = a[i] + a[j]; val = tmp; for (int k = ((int)(a).size()) - 1; k >= 0; --k) { tmp = min(tmp, tmp ^ a[k]); } if (tmp > 0) { res.push_back(to_string(a[i]) + + + to_string(a[j])); break; } val = -1; } if (val > 0) { break; } } for (int i = ((int)(a).size()) - 1; i >= 0; --i) { if ((val ^ a[i]) < val) { res.push_back(to_string(a[i]) + ^ + to_string(val)); val ^= a[i]; } } for (int i = 0; i < ((int)(a).size()); ++i) { if ((a[i] ^ val) < a[i]) { res.push_back(to_string(a[i]) + ^ + to_string(val)); a[i] ^= val; } } a.push_back(val); sort((a).begin(), (a).end()); } cout << ((int)(res).size()) << n ; for (int i = 0; i < ((int)(res).size()); ++i) { cout << res[i] << n ; } } int main() { ios_base::sync_with_stdio(0); std::cin.tie(nullptr); int tc = 1; for (int ti = 0; ti < tc; ++ti) { Solve(); } return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire RBL2; // From t of Test.v
// End of automatics
wire RWL1 = crc[2];
wire RWL2 = crc[3];
Test t (/*AUTOINST*/
// Outputs
.RBL2 (RBL2),
// Inputs
.RWL1 (RWL1),
.RWL2 (RWL2));
// Aggregate outputs into a single result vector
wire [63:0] result = {63'h0, RBL2};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hb6d6b86aa20a882a
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (
output RBL2,
input RWL1, RWL2);
// verilator lint_off IMPLICIT
not I1 (RWL2_n, RWL2);
bufif1 I2 (RBL2, n3, 1'b1);
Mxor I3 (n3, RWL1, RWL2_n);
// verilator lint_on IMPLICIT
endmodule
module Mxor (output out, input a, b);
assign out = (a ^ b);
endmodule
|
module c3dClkGen2 (
input CLKIN,
output SYSTEM_CLK,
output SYNC_CLK,
output C2C_CLK,
output C2C_CLK180,
output PLL0_LOCK
// Other clocks i.e. for DDR if required
);
// PLL for C2C and B2B modules
PLL_BASE #(.BANDWIDTH("OPTIMIZED"), // "HIGH", "LOW" or "OPTIMIZED"
.CLKFBOUT_MULT(2), // Multiplication factor for all output clocks
.CLKFBOUT_PHASE(0.0), // Phase shift (degrees) of all output clocks
.CLKIN_PERIOD(3.2), // Clock period (ns) of input clock on CLKIN
.CLKOUT0_DIVIDE(4), // Division factor for CLKOUT0 (1 to 128)
.CLKOUT0_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.01 to 0.99)
.CLKOUT0_PHASE(0.0), // Phase shift (degrees) for CLKOUT0 (0.0 to 360.0)
.CLKOUT1_DIVIDE(2), // Division factor for CLKOUT1 (1 to 128)
.CLKOUT1_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT1 (0.01 to 0.99)
.CLKOUT1_PHASE(0.0), // Phase shift (degrees) for CLKOUT1 (0.0 to 360.0)
.CLKOUT2_DIVIDE(16), // Division factor for CLKOUT2 (1 to 128)
.CLKOUT2_DUTY_CYCLE(0.375), // Duty cycle for CLKOUT2 (0.01 to 0.99)
.CLKOUT2_PHASE(0.0), // Phase shift (degrees) for CLKOUT2 (0.0 to 360.0)
.CLKOUT3_DIVIDE(4), // Division factor for CLKOUT3 (1 to 128)
.CLKOUT3_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT3 (0.01 to 0.99)
.CLKOUT3_PHASE(180.0), // Phase shift (degrees) for CLKOUT3 (0.0 to 360.0)
.CLKOUT4_DIVIDE(8), // Division factor for CLKOUT4 (1 to 128)
.CLKOUT4_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT4 (0.01 to 0.99)
.CLKOUT4_PHASE(0.0), // Phase shift (degrees) for CLKOUT4 (0.0 to 360.0)
.CLKOUT5_DIVIDE(4), // Division factor for CLKOUT5 (1 to 128)
.CLKOUT5_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT5 (0.01 to 0.99)
.CLKOUT5_PHASE(180.0), // Phase shift (degrees) for CLKOUT5 (0.0 to 360.0)
.COMPENSATION("SYSTEM_SYNCHRONOUS"), // "SYSTEM_SYNCHRONOUS",
.DIVCLK_DIVIDE(1), // Division factor for all clocks (1 to 52)
.REF_JITTER(0.100)) // Input reference jitter (0.000 to 0.999 UI%)
pll_0 (.CLKFBOUT(pll0_fb ), // General output feedback signal
.CLKOUT0 (pll0_0 ), // 156.25 MHz system clock before buffering
.CLKOUT1 (pll0_1 ), // 312.5 MHz clock for GTP TXUSRCLK
.CLKOUT2 ( ), //
.CLKOUT3 (C2C_CLK180 ), // 156.25 MHz system clock before buffering, 180deg
.CLKOUT4 ( ), //
.CLKOUT5 ( ), //
.LOCKED (PLL0_LOCK ), // Active high PLL lock signal
.CLKFBIN (pll0_fb ), // Clock feedback input
.CLKIN (CLKIN ), // 312.5 MHz clock input from GTP
.RST (1'b0 )
);
BUFG bufg_0_0 (.I(pll0_0), .O(SYSTEM_CLK));
BUFG bufg_0_1 (.I(pll0_1), .O(SYNC_CLK));
assign C2C_CLK = pll0_0;
// 2nd PLL for DDR if required
//This PLL generates MCLK and MCLK90 at whatever frequency we want.
PLL_BASE #(.BANDWIDTH("OPTIMIZED"), // "HIGH", "LOW" or "OPTIMIZED"
.CLKFBOUT_MULT(20), // Multiplication factor for all output clocks
.CLKFBOUT_PHASE(0.0), // Phase shift (degrees) of all output clocks
.CLKIN_PERIOD(10.0), // Clock period (ns) of input clock on CLKIN
.CLKOUT0_DIVIDE(4), // Division factor for MCLK (1 to 128)
.CLKOUT0_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.01 to 0.99)
.CLKOUT0_PHASE(0.0), // Phase shift (degrees) for CLKOUT0 (0.0 to 360.0)
.CLKOUT1_DIVIDE(4), // Division factor for MCLK90 (1 to 128)
.CLKOUT1_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT1 (0.01 to 0.99)
.CLKOUT1_PHASE(90.0), // Phase shift (degrees) for CLKOUT1 (0.0 to 360.0)
.CLKOUT2_DIVIDE(16), // Division factor for Ph0 (1 to 128)
.CLKOUT2_DUTY_CYCLE(0.375), // Duty cycle for CLKOUT2 (0.01 to 0.99)
.CLKOUT2_PHASE(0.0), // Phase shift (degrees) for CLKOUT2 (0.0 to 360.0)
.CLKOUT3_DIVIDE(4), // Division factor for MCLK180 (1 to 128)
.CLKOUT3_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT3 (0.01 to 0.99)
.CLKOUT3_PHASE(180.0), // Phase shift (degrees) for CLKOUT3 (0.0 to 360.0)
.CLKOUT4_DIVIDE(8), // Division factor for CLK (1 to 128)
.CLKOUT4_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT4 (0.01 to 0.99)
.CLKOUT4_PHASE(0.0), // Phase shift (degrees) for CLKOUT4 (0.0 to 360.0)
.CLKOUT5_DIVIDE(4), // Division factor for CLK200 (1 to 128)
.CLKOUT5_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT5 (0.01 to 0.99)
.CLKOUT5_PHASE(180.0), // Phase shift (degrees) for CLKOUT5 (0.0 to 360.0)
.COMPENSATION("SYSTEM_SYNCHRONOUS"), // "SYSTEM_SYNCHRONOUS",
.DIVCLK_DIVIDE(2), // Division factor for all clocks (1 to 52)
.REF_JITTER(0.100)) // Input reference jitter (0.000 to 0.999 UI%)
pll1 (.CLKFBOUT(pll1_fb ), // General output feedback signal
.CLKOUT0 (pll1_0 ), // 266 MHz
.CLKOUT1 (pll1_1 ), // 266 MHz, 90 degree shift
.CLKOUT2 (pll1_2 ), // MCLK/4
.CLKOUT3 (pll1_3 ),
.CLKOUT4 (pll1_4 ), // MCLK/2
.CLKOUT5 ( ),
.LOCKED (PLL1_LOCK), // Active high PLL lock signal
.CLKFBIN (pll1_fb ), // Clock feedback input
.CLKIN (CLK_IN ), // Clock input
.RST (1'b0 )
);
BUFG bufg_1_0 (.I(pll1_0), .O(PLL1_OUT0)); // MCLK
BUFG bufg_1_1 (.I(pll1_1), .O(PLL1_OUT1)); // MCLK90
BUFG pufg_1_2 (.I(pll1_2), .O(PLL1_OUT2)); // PH0
BUFG bufg_1_3 (.I(pll1_4), .O(PLL1_OUT4)); // CLK
//BUFG bufg_1_4 (.I(MCLKx), .O(RingCLK));
//BUFGMUX_CTRL swClkbuf (
//.O(swClock), // Clock MUX output
//.I0(MCLKx), // Clock0 input
//.I1(MCLK180x), // Clock1 input
//.S(switchClock) // Clock select input
//);
endmodule
|
// Ten basic tests in here:
// 1. byte must be initialised before any initial or always block
// 2. assignments to (unsigned) bytes with random numbers
// 3. assignments to (unsigned) bytes with random values including X and Z
// 4. converting unsigned integers to unsigned bytes
// 5. converting signed integers to unsigned bytes
// 6. converting integers including X and Z states to unsigned bytes
// 7. trying unsigned sums (procedural, function, task and module)
// 8. trying unsigned (truncated) mults (procedural, function and task)
// 9. trying relational operators
// 10. smaller signed number to unsigned bytes (sign extension)
module mu_add (input byte unsigned a, b, output byte unsigned sc, ss);
assign sc = a + b;
always @(a, b) ss = a + b;
endmodule
module main;
parameter N_REPS = 500; // repetition with random numbers
parameter XZ_REPS = 500; // repetition with 'x 'z values
parameter MAX = 256;
parameter LEN = 8;
// variables used as golden references
reg unsigned [LEN-1:0] ar; // holds numbers
reg unsigned [LEN-1:0] ar_xz; // holds 'x and/or 'z in random positions
reg unsigned [LEN-1:0] ar_expected;
integer unsigned ui;
integer signed si;
reg signed [LEN/2-1:0] slice;
// types to be tested
byte unsigned bu; // holds numbers
byte unsigned bu_xz; // 'x and 'z are attempted on this
byte unsigned bresult; // hold results from sums and mults
byte unsigned mcaresult; // this is permanently wired to a module
byte unsigned mabresult; // this is permanently wired to a module
integer i;
// continuous assigments
// type LHS type RHS
// --------- ---------
// byte 4-value logic
assign bu = ar;
assign bu_xz = ar_xz;
// module instantiation
mu_add duv (.a(bu), .b(bu_xz), .sc(mcaresult), .ss(mabresult) );
// all test
initial begin
// time 0 checkings (Section 6.4 of IEEE 1850 LRM)
if ( bu !== 8'b0 || bu_xz !== 8'b0 || bresult !== 8'b0 || mcaresult !== 8'b0 || mabresult !== 8'b0)
begin
$display ("FAILED - time zero initialisation incorrect: %b %b", bu, bu_xz);
$finish;
end
// driving byte type with unsigned random numbers from a variable
for (i = 0; i< N_REPS; i = i+1)
begin
#1;
ar = {$random} % MAX;
#1;
if (bu !== ar)
begin
$display ("FAILED - incorrect assigment to byte: %b", bu);
$finish;
end
end
# 1;
// attempting to drive variables having 'x 'z values into type unsigned bytes
// 'x 'z injections (Section 4.3.2 of IEEE 1850 LRM)
for (i = 0; i< XZ_REPS; i = i+1)
begin
#1;
ar = {$random} % MAX;
ar_xz = xz_inject (ar);
ar_expected = xz_expected (ar_xz);
#1;
if (bu_xz !== ar_expected) // 'x -> '0, 'z -> '0
begin
$display ("FAILED - incorrect assigment to byte (when 'x 'z): %b", bu);
$finish;
end
end
// converting unsigned integers to unsigned bytes
// truncation expected (Section 4.3.2 of IEEE 1850 LRM)
for (i = 0; i< N_REPS; i = i+1)
begin
#1;
ui = {$random};
#1;
force bu = ui;
#1;
if (bu !== ui[LEN-1:0])
begin
$display ("FAILED - incorrect truncation from unsigned integer to byte: %b", bu);
$finish;
end
end
release bu;
// converting signed integers to unsigned bytes
// truncation expected (Section 4.3.2 of IEEE 1850 LRM)
for (i = 0; i< N_REPS; i = i+1)
begin
#1;
si = $random % MAX/2;
#1;
force bu = si;
#1;
if (bu !== si[LEN-1:0])
begin
$display ("FAILED - incorrect truncation from signed integer to byte: %b mismatchs %b", bu, si[7:0]);
$finish;
end
end
release bu;
// converting signed integers having 'x 'z values into type unsigned bytes
// 'x 'z injections (Section 4.3.2 of IEEE 1850 LRM)
// truncation and coercion to zero expected
for (i = 0; i< XZ_REPS; i = i+1)
begin
#1;
si = $random;
ar_xz = xz_inject (si[LEN-1:0]);
si = {si[31:LEN], ar_xz};
ar_expected = xz_expected (ar_xz);
#1;
force bu_xz = si;
#1;
if (bu_xz !== ar_expected) // 'x -> '0, 'z -> '0
begin
$display ("FAILED - incorrect conversion from integer (with 'x 'z) to byte: %b mismatchs %b", bu_xz, ar_expected);
$finish;
end
end
release bu_xz;
// trying unsigned sums
for (i = 0; i< N_REPS; i = i+1)
begin
#1;
ar = {$random} % MAX;
ar_xz = {$random} % MAX;
#1;
bresult = bu + bu_xz;
#1;
if ( bresult !== u_sum(ar, ar_xz) )
begin
$display ("FAILED - incorrect addition of unsigned bytes: %0d mismatchs %0d", bresult, u_sum(ar, ar_xz));
$finish;
end
// invoking byte sum function
if ( fu_sum (bu, bu_xz) !== u_sum(ar, ar_xz) )
begin
$display ("FAILED - incorrect addition of unsigned bytes in function");
$finish;
end
// invoking byte sum task
tu_sum (bu, bu_xz, bresult);
if ( bresult !== u_sum(ar, ar_xz) )
begin
$display ("FAILED - incorrect addition of unsigned bytes in task: %0d mismatchs %0d", bresult, u_sum(ar, ar_xz));
$finish;
end
// checking byte sum from module
if ( mcaresult !== u_sum(ar, ar_xz) || mabresult !== u_sum(ar, ar_xz))
begin
$display ("FAILED - incorrect addition of unsigned bytes from module");
$finish;
end
end
// trying unsigned mults: trucation is forced
for (i = 0; i< N_REPS; i = i+1)
begin
#1;
ar = ({$random} % MAX) << LEN/2;
ar_xz = ({$random} % MAX) << (LEN/2 -1);
#1;
bresult = bu * bu_xz;
#1;
if ( bresult !== u_mul(ar, ar_xz) )
begin
$display ("FAILED - incorrect addition of unsigned bytes: %0d mismatchs %0d", bresult, u_mul(ar, ar_xz));
$finish;
end
// invoking byte mult function
if ( fu_mul (bu, bu_xz) !== u_mul(ar, ar_xz) )
begin
$display ("FAILED - incorrect product of unsigned bytes in function");
$finish;
end
// invoking byte mult task
tu_mul (bu, bu_xz, bresult);
if ( bresult !== u_mul(ar, ar_xz) )
begin
$display ("FAILED - incorrect product of unsigned bytes in task: %0d mismatchs %0d", bresult, u_mul(ar, ar_xz));
$finish;
end
end
// trying relational operators
for (i = 0; i< N_REPS; i = i+1)
begin
#1;
ar = {$random} % MAX;
ar_xz = {$random} % MAX;
#1;
if ( (bu < bu_xz ) !== (ar < ar_xz) )
begin
$display ("FAILED - incorrect 'less than' on unsigned bytes");
$finish;
end
if ( (bu <= bu_xz ) !== (ar <= ar_xz) )
begin
$display ("FAILED - incorrect 'less than or equal' on unsigned bytes");
$finish;
end
if ( (bu > bu_xz ) !== (ar > ar_xz) )
begin
$display ("FAILED - incorrect 'greater than' on unsigned bytes");
$finish;
end
if ( (bu >= bu_xz ) !== (ar >= ar_xz) )
begin
$display ("FAILED - incorrect 'greater than or equal' than on unsigned bytes");
$finish;
end
if ( (bu == bu_xz ) !== (ar == ar_xz) )
begin
$display ("FAILED - incorrect 'equal to' on unsigned bytes");
$finish;
end
if ( (bu != bu_xz ) !== (ar != ar_xz) )
begin
$display ("FAILED - incorrect 'not equal to' on unsigned bytes");
$finish;
end
end
# 1;
// signed small number to unsigned byte
for (i = 0; i < (1<<LEN/2); i = i+1)
begin
#1;
slice = $random % 'h7;
force bu = slice;
ar = slice;
#1;
if (bu !== ar)
begin
$display ("FAILED - incorrect signed extend to unsigned bytes");
$finish;
end
end
release bu;
$display("PASSED");
end
// this returns X and Z states into bit random positions for a value
function [LEN-1:0] xz_inject (input unsigned [LEN-1:0] value);
integer i, temp;
begin
temp = {$random} % MAX;
for (i=0; i<LEN; i=i+1)
begin
if (temp[i] == 1'b1)
begin
temp = $random % MAX;
if (temp <= 0)
value[i] = 1'bx; // 'x noise
else
value[i] = 1'bz; // 'z noise
end
end
xz_inject = value;
end
endfunction
// this function returns bit positions with either X or Z to 0 for an input value
function [LEN-1:0] xz_expected (input unsigned [LEN-1:0] value_xz);
integer i;
begin
for (i=0; i<LEN; i=i+1)
begin
if (value_xz[i] === 1'bx || value_xz[i] === 1'bz )
value_xz[i] = 1'b0; // forced to zero
end
xz_expected = value_xz;
end
endfunction
// unsigned 4-value sum
function unsigned [LEN-1:0] u_sum (input unsigned [LEN-1:0] a, b);
u_sum = a + b;
endfunction
// unsigned byte sum as function
function byte unsigned fu_sum (input byte unsigned a, b);
fu_sum = a + b;
endfunction
// unsigned byte sum as task
task tu_sum (input byte unsigned a, b, output byte unsigned c);
c = a + b;
endtask
// unsigned 4-value mults
function unsigned [LEN-1:0] u_mul (input unsigned [LEN-1:0] a, b);
u_mul = a * b;
endfunction
// unsigned byte mults
function byte unsigned fu_mul (input byte unsigned a, b);
fu_mul = a * b;
endfunction
// unsigned byte mult as task
task tu_mul (input byte unsigned a, b, output byte unsigned c);
c = a * b;
endtask
endmodule
|
/*------------------------------------------------------------------------
Purpose
- Data serializing;
- bit staffing;
- nrzi encoding;
- remote wakeup signaling.
------------------------------------------------------------------------*/
module usb_encoder (
input clk,
input rst0_async,
input rst0_sync,
//USB
output reg dtx_plus,
output reg dtx_minus,
output reg dtx_oe,
//DECODER
input usb_interpack,
//ENCFIFO
input encfifo_wr,
input encfifo_wdata,
output encfifo_full,
input remote_wakeup,
input speed
);
wire usb_j;
wire usb_k;
wire encfifo_empty;
reg encfifo_rd;
wire encfifo_rdata;
reg[17:0] counter;
reg[2:0] stuffbit;
reg[3:0] enc_state;
localparam ENC_IDLE=4'd0,
ENC_TIME1=4'd1,
ENC_DRIVE=4'd2,
ENC_STUFF=4'd3,
ENC_SE0=4'd4,
ENC_TIME2=4'd5,
ENC_DRIVEJ=4'd6,
ENC_TIME3=4'd7,
ENC_DRIVEK=4'd8;
usb_fifo_sync #(.ADDR_WIDTH(1'd1),.WDATA_WIDTH(1'd0),.RDATA_WIDTH(1'd0))
i_encfifo
(
.clk(clk),
.rst0_async(rst0_async),
.rst0_sync(rst0_sync),
.wr_en(encfifo_wr),
.wr_data(encfifo_wdata),
.rd_en(encfifo_rd),
.rd_data(encfifo_rdata),
.fifo_full(encfifo_full),
.fifo_empty(encfifo_empty)
);
assign usb_j= speed ? 1'b1 : 1'b0;
assign usb_k= speed ? 1'b0 : 1'b1;
always @(posedge clk, negedge rst0_async)
begin
if(!rst0_async)
begin
dtx_plus<=1'b1;
dtx_minus<=1'b0;
dtx_oe<=1'b0;
encfifo_rd<=1'b0;
counter<=18'd0;
stuffbit<=3'd0;
enc_state<=ENC_IDLE;
end
else if(!rst0_sync)
begin
dtx_plus<=1'b1;
dtx_minus<=1'b0;
dtx_oe<=1'b0;
encfifo_rd<=1'b0;
counter<=18'd0;
stuffbit<=3'd0;
enc_state<=ENC_IDLE;
end
else
begin
case(enc_state)
ENC_IDLE:
begin
stuffbit<=3'd0;
counter<=18'd0;
encfifo_rd<=1'b0;
dtx_plus<= usb_j;
dtx_minus<= ~usb_j;
dtx_oe<= (!encfifo_empty & usb_interpack) |
remote_wakeup ? 1'b1 : 1'b0;
enc_state<= remote_wakeup ? ENC_DRIVEK :
!encfifo_empty & usb_interpack ? ENC_TIME1 :
enc_state;
end
ENC_TIME1:
begin
counter<= counter+1'b1;
encfifo_rd<= counter==18'd2 & stuffbit!=3'd6 &
!encfifo_empty ? 1'b1 :
1'b0;
enc_state<= counter==18'd2 & stuffbit==3'd6 ? ENC_STUFF :
counter==18'd2 & encfifo_empty ? ENC_SE0 :
counter==18'd2 ? ENC_DRIVE :
enc_state;
end
ENC_DRIVE:
begin
counter<=18'd0;
encfifo_rd<=1'b0;
stuffbit<= encfifo_rdata ? stuffbit+1'b1 : 3'd0;
dtx_plus<= encfifo_rdata ? dtx_plus : ~dtx_plus;
dtx_minus<= encfifo_rdata ? ~dtx_plus : dtx_plus;
enc_state<= ENC_TIME1;
end
ENC_STUFF:
begin
counter<=18'd0;
stuffbit<=3'd0;
dtx_plus<= ~dtx_plus;
dtx_minus<= dtx_plus;
enc_state<= ENC_TIME1;
end
ENC_SE0:
begin
counter<=18'd0;
dtx_plus<=1'b0;
dtx_minus<=1'b0;
enc_state<= ENC_TIME2;
end
ENC_TIME2:
begin
counter<= counter+1'b1;
enc_state<= counter==18'd6 ? ENC_DRIVEJ :
enc_state;
end
ENC_DRIVEJ:
begin
counter<=18'd0;
dtx_plus<= usb_j;
dtx_minus<= ~usb_j;
enc_state<= ENC_TIME3;
end
ENC_TIME3:
begin
counter<= counter+1'b1;
enc_state<= counter==18'd2 ? ENC_IDLE :
enc_state;
end
ENC_DRIVEK:
begin
counter<= counter+1'b1;
dtx_plus<= usb_k;
dtx_minus<= ~usb_k;
//REMOTE WAKEUP SIGNALING:
// ~145000 CYCLES ~2,9ms (FULL SPEED)
// ~18000 CYCLES ~3ms (LOW SPEED)
enc_state<= (speed & counter==18'd145000) |
(!speed & counter==18'd18000) ? ENC_IDLE : enc_state;
end
default:
begin
dtx_plus<=1'b1;
dtx_minus<=1'b0;
dtx_oe<=1'b0;
encfifo_rd<=1'b0;
counter<=18'd0;
stuffbit<=3'd0;
enc_state<=ENC_IDLE;
end
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRDLRTP_TB_V
`define SKY130_FD_SC_LP__SRDLRTP_TB_V
/**
* srdlrtp: ????.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__srdlrtp.v"
module top();
// Inputs are registered
reg RESET_B;
reg D;
reg SLEEP_B;
reg KAPWR;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
KAPWR = 1'bX;
RESET_B = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 KAPWR = 1'b0;
#60 RESET_B = 1'b0;
#80 SLEEP_B = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 D = 1'b1;
#200 KAPWR = 1'b1;
#220 RESET_B = 1'b1;
#240 SLEEP_B = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 D = 1'b0;
#360 KAPWR = 1'b0;
#380 RESET_B = 1'b0;
#400 SLEEP_B = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 SLEEP_B = 1'b1;
#600 RESET_B = 1'b1;
#620 KAPWR = 1'b1;
#640 D = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 SLEEP_B = 1'bx;
#760 RESET_B = 1'bx;
#780 KAPWR = 1'bx;
#800 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_lp__srdlrtp dut (.RESET_B(RESET_B), .D(D), .SLEEP_B(SLEEP_B), .KAPWR(KAPWR), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRDLRTP_TB_V
|
#include <bits/stdc++.h> using namespace std; int a, b, n, k, y, x, i, j, h, ans, c, d[100005], f[10]; char s[105], s1[105]; int main() { scanf( %d%d%s , &n, &k, s); for (i = 1; i <= k; i++) { int f[1000] = {0}; scanf( %d %d , &a, &b); x = 0; int DP = 1, CP = 0, lens1 = 0; int p1 = 0; int p2 = -1; for (j = a - 1; j < b; j++) { s1[lens1++] = s[j]; } while (CP < lens1 && CP >= 0) { if (s1[CP] >= 48 && s1[CP] <= 57) { f[s1[CP] - 48]++; if (s1[CP] >= 48 && s1[CP] <= 57) { s1[CP]--; } p1 = 1; p2 = CP; } else if (s1[CP] == < || s1[CP] == > ) { if (p1 == 2) { s1[p2] = 47; } if (s1[CP] == > ) { DP = 1; } else { DP = -1; } p1 = 2; p2 = CP; } if (DP == 1) { CP++; } else CP--; } for (j = 0; j < 10; j++) { printf( %d , f[j]); } printf( n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; const int idata = 2e5 + 7; int i, j, k; int judge, flag; long long step[idata]; long long temp; int n, m, t; double maxx = 0, minn = inf; long long cnt, len, sum, ans; long long high, wigh; map<long long, int> pre[2]; signed main() { while (cin >> n >> k) { memset(step, 0, sizeof step); for (i = 1; i <= n; i++) { cin >> step[i]; pre[0][step[i]]++; } for (i = 1; i <= n; i++) { pre[0][step[i]]--; if (step[i] % k == 0) { ans += (long long)pre[1][step[i] / k] * pre[0][step[i] * k]; } pre[1][step[i]]++; } cout << ans << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int mxN = 302; bool ar[mxN]; int p, n; void solve() { cin >> p >> n; for (int i = 0; i < n; i++) { int a; cin >> a; int temp = a % p; if (ar[temp] == 0) { ar[temp] = 1; } else { cout << i + 1; return; } } cout << -1; } int main() { ios::sync_with_stdio(0); cin.tie(0); int t = 1, i = 1; while (t--) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; long long add(int a, int b) { return (a % 1000000007 + b % 1000000007 + ((8000000000000000064LL) / 1000000007) * 1000000007) % 1000000007; } long long sub(long long a, long long b) { return (a % 1000000007 - b % 1000000007 + ((8000000000000000064LL) / 1000000007) * 1000000007) % 1000000007; } long long mul(long long a, long long b) { return ((a % 1000000007) * (b % 1000000007) + ((8000000000000000064LL) / 1000000007) * 1000000007) % 1000000007; } long long binpow(long long a, long long b) { long long res = 1; while (b > 0) { if (b & 1) res = res * a; a = a * a; b >>= 1; } return res; } int const N = 1e3 + 9; long long const INF = 2e18 + 5; long long dx[8] = {0, 0, 1, -1, 1, 1, -1, -1}; long long dy[8] = {1, -1, 0, 0, -1, 1, -1, 1}; char dr[4] = { R , L , D , U }; vector<vector<long long>> v; void solve() { long long n; cin >> n; long long a[n]; for (long long i = 0; i < n; i++) cin >> a[i]; v = vector<vector<long long>>(n + 1); queue<long long> q; q.push(1); long long i = 1; while (!q.empty()) { if (i == n) { break; } long long t = a[i], k = q.front(); q.pop(); while (a[i] >= t && i < n) { q.push(a[i]); v[k].push_back(a[i]); t = a[i]; i++; } } queue<pair<long long, long long>> Q; Q.push({1, 0}); long long ans = 0; while (!Q.empty()) { long long k = Q.front().first, t = Q.front().second; ans = max(ans, t); Q.pop(); for (auto x : v[k]) { Q.push({x, t + 1}); } } cout << ans << n ; } int main() { ios_base ::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); long long t; cin >> t; while (t--) { solve(); } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND2B_BEHAVIORAL_V
`define SKY130_FD_SC_HS__AND2B_BEHAVIORAL_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__and2b (
X ,
A_N ,
B ,
VPWR,
VGND
);
// Module ports
output X ;
input A_N ;
input B ;
input VPWR;
input VGND;
// Local signals
wire X not0_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X , not0_out, B );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND2B_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; int m[120], n, k = 0; int main() { cin >> n; char a, b; getchar(); for (int i = 1; i < n; i++) { a = getchar(); b = getchar(); m[a - a ]++; if (m[b - A ] > 0) { m[b - A ]--; } else { k++; } } cout << k << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A31OI_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__A31OI_PP_BLACKBOX_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a31oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A31OI_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int N = 32005; int n, m, i, j, f; int a[N]; long long ans; int main() { scanf( %d%d , &n, &m); for (i = m + 1; i <= (n + 1) / 2; i++) { for (j = m + 1; j < 2 * i; j++) { f = (i * (2 * i - j) + (n + 1) * (2 * j - i)) / (i + j); f = max(f, m); if (f > n - m) continue; a[i] += n - m - f; } } for (i = m + 1; i <= (n + 1) / 2; i++) ans += 2 * a[i]; if (n & 1) ans -= a[i - 1]; printf( %I64d n , 3 * ans); return 0; } |
#include <bits/stdc++.h> using namespace std; char str[100003]; struct Node { int val; int val2; Node* pt[26]; } node[100003]; int cnt; int mex(Node* node) { if (node->val != -1) return node->val; int f[30] = {}; for (int i = 0; i < 26; ++i) if (node->pt[i]) f[mex(node->pt[i])] = 1; for (int i = 0; i < 30; ++i) if (f[i] == 0) return node->val = i; } int mex2(Node* node) { if (node->val2 != -1) return node->val2; int f[30] = {}; int flag = 0; for (int i = 0; i < 26; ++i) if (node->pt[i]) { f[mex2(node->pt[i])] = 1; flag = 1; } if (!flag) return node->val2 = 1; for (int i = 0; i < 30; ++i) if (f[i] == 0) return node->val2 = i; } int main() { cnt = 27; int N, K; cin >> N >> K; for (int i = 0; i < 100003; ++i) node[i].val = node[i].val2 = -1; for (int i = 0; i < N; ++i) { cin >> str; Node* now = node; now->pt[str[0] - a ] = node + str[0] - a + 1; for (int j = 0; str[j]; ++j) if (now->pt[str[j] - a ]) now = now->pt[str[j] - a ]; else now = now->pt[str[j] - a ] = node + cnt++; } if (mex(node) == 0) cout << Second << endl; else if (K % 2 == 1 || mex2(node)) cout << First << endl; else cout << Second << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYGATE4SD3_SYMBOL_V
`define SKY130_FD_SC_LS__DLYGATE4SD3_SYMBOL_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlygate4sd3 (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYGATE4SD3_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; double cooy1, cooy2, cooyw, cooxb, cooyb, r; double s1, s2; int main() { ios_base::sync_with_stdio(false); cin >> cooy1 >> cooy2 >> cooyw >> cooxb >> cooyb >> r; cooy1 += r; cooy2 -= r; cooyw -= r; s1 = 2 * cooyw - cooy1; s2 = 2 * cooyw - cooy2; double xx1 = cooxb * (cooyw - s1) / (cooyb - s1); double xx2 = cooxb * (cooyw - s2) / (cooyb - s2); double dd1 = sqrt(cooxb * cooxb + (s1 - cooyb) * (s1 - cooyb)) * r / cooxb; double dd2 = sqrt(cooxb * cooxb + (s2 - cooyb) * (s2 - cooyb)) * r / cooxb; if (s1 - dd1 < s2 - r) { if (s2 - dd2 < s2 - r) { cout << -1; return 0; } cout.precision(30); cout << xx2; return 0; } else { cout.precision(30); cout << xx1; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLXBN_BLACKBOX_V
`define SKY130_FD_SC_MS__DLXBN_BLACKBOX_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlxbn (
Q ,
Q_N ,
D ,
GATE_N
);
output Q ;
output Q_N ;
input D ;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLXBN_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; void solution() { int n, k; cin >> n >> k; vector<long long> v(n * k + 1, 0), brr(n * k + 1, 0); long long sum = 0; for (int i = 1; i <= n * k; i++) { cin >> v[i]; brr[i] = v[i]; } brr[0] = INT_MAX; sort(brr.rbegin(), brr.rend()); if (n % 2 == 0) { int right = n / 2 + 1; int i = right; int j = 0; while (j < k) { sum = sum + brr[i]; i = i + right; j++; } } else { int right = n / 2 + n % 2; int i = right; int j = 0; while (j < k) { sum = sum + brr[i]; i = i + right; j++; } } cout << sum << endl; } int main() { int t; cin >> t; while (t--) { solution(); } return 0; } |
#include <bits/stdc++.h> using namespace std; typedef long long ll; int main() { ll t; cin >> t; while (t--) { ll cnt3, cnt2; cnt2 = cnt3 = 0; ll n; cin >> n; while (n % 2 == 0) { n = n / 2; cnt2++; } while (n % 3 == 0) { n = n / 3; cnt3++; } if (n != 1 || cnt2 > cnt3) cout << -1 << n ; else { ll ans = cnt2 + (cnt3 - cnt2) * 2; cout << ans << n ; } } return 0; } |
// megafunction wizard: %LPM_MULT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_mult
// ============================================================
// File Name: mult16.v
// Megafunction Name(s):
// lpm_mult
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.1 Build 243 01/31/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module mult16 (
dataa,
datab,
result);
input [15:0] dataa;
input [15:0] datab;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
lpm_mult lpm_mult_component (
.dataa (dataa),
.datab (datab),
.result (sub_wire0),
.aclr (1'b0),
.clken (1'b1),
.clock (1'b0),
.sum (1'b0));
defparam
lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=5",
lpm_mult_component.lpm_representation = "UNSIGNED",
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_widtha = 16,
lpm_mult_component.lpm_widthb = 16,
lpm_mult_component.lpm_widthp = 32;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
// Retrieval info: PRIVATE: Latency NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "0"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
// Retrieval info: PRIVATE: WidthA NUMERIC "16"
// Retrieval info: PRIVATE: WidthB NUMERIC "16"
// Retrieval info: PRIVATE: WidthP NUMERIC "32"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: PRIVATE: optimize NUMERIC "0"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=5"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "32"
// Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL "dataa[15..0]"
// Retrieval info: USED_PORT: datab 0 0 16 0 INPUT NODEFVAL "datab[15..0]"
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
// Retrieval info: CONNECT: @dataa 0 0 16 0 dataa 0 0 16 0
// Retrieval info: CONNECT: @datab 0 0 16 0 datab 0 0 16 0
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL mult16.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult16.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult16.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult16.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult16_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult16_bb.v FALSE
// Retrieval info: LIB_FILE: lpm
|
#include <bits/stdc++.h> using namespace std; int n, m; vector<vector<int> > G; double dfs(int u, int p = -1) { double res = 0; int cnt = 0; for (int i = 0; i < G[u].size(); ++i) { int v = G[u][i]; if (v == p) continue; cnt++; res += dfs(v, u); } return (cnt ? res / cnt + 1 : 0); } int main() { cin >> n; m = n - 1; G.resize(n + 1); for (int i = 0; i < m; ++i) { int u, v; cin >> u >> v; G[u].push_back(v); G[v].push_back(u); } cout << setprecision(7) << fixed << dfs(1); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDLCLKP_4_V
`define SKY130_FD_SC_MS__SDLCLKP_4_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog wrapper for sdlclkp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__sdlclkp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sdlclkp_4 (
GCLK,
SCE ,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__sdlclkp base (
.GCLK(GCLK),
.SCE(SCE),
.GATE(GATE),
.CLK(CLK),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sdlclkp_4 (
GCLK,
SCE ,
GATE,
CLK
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__sdlclkp base (
.GCLK(GCLK),
.SCE(SCE),
.GATE(GATE),
.CLK(CLK)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDLCLKP_4_V
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; const int maxn = 222222; int main(int argc, char const *argv[]) { long long s, x; cin >> s >> x; if (s < x || (s - x) % 2) { puts( 0 ); } else { long long c = (s - x) / 2; long long ans = 1; for (int i = 0; i < 40; ++i) { long long b1 = (x >> i) & 1; long long b2 = (c >> i) & 1; if (b1 && b2) ans = 0; else if (b1) ans *= 2L; } if (c == 0) ans -= 2; cout << (ans) << endl; } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:23:14 11/09/2016
// Design Name:
// Module Name: Sprite
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Sprite_Controller # ( parameter SizeX= 32, parameter SizeY=32) (
input wire [9:0] iColumnCount,
input wire[9:0] iRowCount,
input wire imask,
input wire iEnable,
input wire [9:0] iPosX,
input wire [9:0] iPosY,
input wire [2:0] iColorSprite,
input wire [2:0] iColorBack ,
output reg [2:0] oRGB
);
always @ (*)
begin
if(iColumnCount <= SizeX + iPosX && iRowCount <= SizeY + iPosY
&& iColumnCount >= iPosX && iRowCount >= iPosY && iEnable == 1 && imask == 1 )
begin
oRGB <= iColorSprite;
end
else
begin
oRGB <= iColorBack;
end
end
endmodule
|
`timescale 1 ns / 1 ps
module esaxi_v1_0 #
(
// Users to add parameters here
parameter [11:0] C_READ_TAG_ADDR = 12'h810,
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_ID_WIDTH = 1,
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 30,
parameter integer C_S00_AXI_AWUSER_WIDTH = 0,
parameter integer C_S00_AXI_ARUSER_WIDTH = 0,
parameter integer C_S00_AXI_WUSER_WIDTH = 0,
parameter integer C_S00_AXI_RUSER_WIDTH = 0,
parameter integer C_S00_AXI_BUSER_WIDTH = 0
)
(
// Users to add ports here
// FIFO write port, write requests
output wire [102:0] emwr_wr_data,
output wire emwr_wr_en,
input wire emwr_full,
input wire emwr_prog_full,
// FIFO write port, read requests
output wire [102:0] emrq_wr_data,
output wire emrq_wr_en,
input wire emrq_full,
input wire emrq_prog_full,
// FIFO read port, read responses
input wire [102:0] emrr_rd_data,
output wire emrr_rd_en,
input wire emrr_empty,
// Control bits from eConfig
input wire [3:0] ecfg_tx_ctrl_mode,
input wire [11:0] ecfg_coreid,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ID_WIDTH-1 : 0] s00_axi_awid,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [7 : 0] s00_axi_awlen,
input wire [2 : 0] s00_axi_awsize,
input wire [1 : 0] s00_axi_awburst,
input wire s00_axi_awlock,
input wire [3 : 0] s00_axi_awcache,
input wire [2 : 0] s00_axi_awprot,
input wire [3 : 0] s00_axi_awqos,
input wire [3 : 0] s00_axi_awregion,
input wire [C_S00_AXI_AWUSER_WIDTH-1 : 0] s00_axi_awuser,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wlast,
input wire [C_S00_AXI_WUSER_WIDTH-1 : 0] s00_axi_wuser,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [C_S00_AXI_ID_WIDTH-1 : 0] s00_axi_bid,
output wire [1 : 0] s00_axi_bresp,
output wire [C_S00_AXI_BUSER_WIDTH-1 : 0] s00_axi_buser,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ID_WIDTH-1 : 0] s00_axi_arid,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [7 : 0] s00_axi_arlen,
input wire [2 : 0] s00_axi_arsize,
input wire [1 : 0] s00_axi_arburst,
input wire s00_axi_arlock,
input wire [3 : 0] s00_axi_arcache,
input wire [2 : 0] s00_axi_arprot,
input wire [3 : 0] s00_axi_arqos,
input wire [3 : 0] s00_axi_arregion,
input wire [C_S00_AXI_ARUSER_WIDTH-1 : 0] s00_axi_aruser,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_ID_WIDTH-1 : 0] s00_axi_rid,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rlast,
output wire [C_S00_AXI_RUSER_WIDTH-1 : 0] s00_axi_ruser,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
// Instantiation of Axi Bus Interface S00_AXI
esaxi_v1_0_S00_AXI # (
.C_READ_TAG_ADDR(C_READ_TAG_ADDR),
.C_S_AXI_ID_WIDTH(C_S00_AXI_ID_WIDTH),
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH),
.C_S_AXI_AWUSER_WIDTH(C_S00_AXI_AWUSER_WIDTH),
.C_S_AXI_ARUSER_WIDTH(C_S00_AXI_ARUSER_WIDTH),
.C_S_AXI_WUSER_WIDTH(C_S00_AXI_WUSER_WIDTH),
.C_S_AXI_RUSER_WIDTH(C_S00_AXI_RUSER_WIDTH),
.C_S_AXI_BUSER_WIDTH(C_S00_AXI_BUSER_WIDTH)
) esaxi_v1_0_S00_AXI_inst (
.emwr_wr_data (emwr_wr_data),
.emwr_wr_en (emwr_wr_en),
.emwr_full (emwr_full),
.emwr_prog_full (emwr_prog_full),
.emrq_wr_data (emrq_wr_data),
.emrq_wr_en (emrq_wr_en),
.emrq_full (emrq_full),
.emrq_prog_full (emrq_prog_full),
.emrr_rd_data (emrr_rd_data),
.emrr_rd_en (emrr_rd_en),
.emrr_empty (emrr_empty),
.ecfg_tx_ctrl_mode (ecfg_tx_ctrl_mode),
.ecfg_coreid (ecfg_coreid),
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWID(s00_axi_awid),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWLEN(s00_axi_awlen),
.S_AXI_AWSIZE(s00_axi_awsize),
.S_AXI_AWBURST(s00_axi_awburst),
.S_AXI_AWLOCK(s00_axi_awlock),
.S_AXI_AWCACHE(s00_axi_awcache),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWQOS(s00_axi_awqos),
.S_AXI_AWREGION(s00_axi_awregion),
.S_AXI_AWUSER(s00_axi_awuser),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WLAST(s00_axi_wlast),
.S_AXI_WUSER(s00_axi_wuser),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BID(s00_axi_bid),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BUSER(s00_axi_buser),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARID(s00_axi_arid),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARLEN(s00_axi_arlen),
.S_AXI_ARSIZE(s00_axi_arsize),
.S_AXI_ARBURST(s00_axi_arburst),
.S_AXI_ARLOCK(s00_axi_arlock),
.S_AXI_ARCACHE(s00_axi_arcache),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARQOS(s00_axi_arqos),
.S_AXI_ARREGION(s00_axi_arregion),
.S_AXI_ARUSER(s00_axi_aruser),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RID(s00_axi_rid),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RLAST(s00_axi_rlast),
.S_AXI_RUSER(s00_axi_ruser),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready)
);
// Add user logic here
// User logic ends
endmodule
|
#include <bits/stdc++.h> using namespace std; int t[200001]; int main() { memset(t, 0x3f, sizeof(t)); int n, k; string str; cin >> n >> k >> str; for (int x = 0; x < n; x++) if (str[x] == str[(x + 1) % n] || str[x] == str[(x - 1 + n) % n]) t[x] = 0; for (int x = 0; x < 2 * n; x++) t[x % n] = min(t[x % n], t[(x - 1 + n) % n] + 1); for (int x = 2 * n - 1; x >= 0; x--) t[x % n] = min(t[x % n], t[(x + 1) % n] + 1); for (int x = 0; x < n; x++) if (min(t[x], k) % 2) str[x] = 153 - str[x]; cout << str << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, s, ans, x, y, a; bool flag = false; cin >> n >> s; s = s * 100; ans = -1; for (int i = 0; i < n; i++) { cin >> x >> y; a = x * 100 + y; if (a <= s) { ans = max(ans, (100 - a % 100) % 100); } } cout << ans; return 0; } |
#include <bits/stdc++.h> const int INF = 0x3f3f3f3f; int n, m; int f[55][405][405], s[405]; void DP() { int i, j, k, mx, my, ans = 0; memset(f, 0, sizeof(f)); for (i = 1, s[0] = 0; i <= n; i++) { scanf( %d , &s[i]); s[i] += s[i - 1]; } for (k = 2; k <= m; k++) { mx = my = -INF; for (i = 1; i <= n; i++) { for (j = i; j <= n; j++) f[k][i][j] = mx + s[j] - s[i - 1] > my - (s[j] - s[i - 1]) ? mx + s[j] - s[i - 1] : my - (s[j] - s[i - 1]); for (j = 1; j <= i; j++) { mx = mx > f[k - 1][j][i] - (s[i] - s[j - 1]) ? mx : f[k - 1][j][i] - (s[i] - s[j - 1]); my = my > f[k - 1][j][i] + (s[i] - s[j - 1]) ? my : f[k - 1][j][i] + (s[i] - s[j - 1]); } } } for (i = 1; i <= n; i++) for (j = 1; j <= n; j++) ans = ans > f[m][i][j] ? ans : f[m][i][j]; printf( %d n , ans); } int main() { while (~scanf( %d%d , &n, &m)) DP(); return 0; } |
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module hps_sdram_p0_generic_ddio(
datain,
halfratebypass,
dataout,
clk_hr,
clk_fr
);
parameter WIDTH = 1;
localparam DATA_IN_WIDTH = 4 * WIDTH;
localparam DATA_OUT_WIDTH = WIDTH;
input [DATA_IN_WIDTH-1:0] datain;
input halfratebypass;
input [WIDTH-1:0] clk_hr;
input [WIDTH-1:0] clk_fr;
output [DATA_OUT_WIDTH-1:0] dataout;
generate
genvar pin;
for (pin = 0; pin < WIDTH; pin = pin + 1)
begin:acblock
wire fr_data_hi;
wire fr_data_lo;
cyclonev_ddio_out
#(
.half_rate_mode("true"),
.use_new_clocking_model("true"),
.async_mode("none")
) hr_to_fr_hi (
.datainhi(datain[pin * 4]),
.datainlo(datain[pin * 4 + 2]),
.dataout(fr_data_hi),
.clkhi (clk_hr[pin]),
.clklo (clk_hr[pin]),
.hrbypass(halfratebypass),
.muxsel (clk_hr[pin])
);
cyclonev_ddio_out
#(
.half_rate_mode("true"),
.use_new_clocking_model("true"),
.async_mode("none")
) hr_to_fr_lo (
.datainhi(datain[pin * 4 + 1]),
.datainlo(datain[pin * 4 + 3]),
.dataout(fr_data_lo),
.clkhi (clk_hr[pin]),
.clklo (clk_hr[pin]),
.hrbypass(halfratebypass),
.muxsel (clk_hr[pin])
);
cyclonev_ddio_out
#(
.async_mode("none"),
.half_rate_mode("false"),
.sync_mode("none"),
.use_new_clocking_model("true")
) ddio_out (
.datainhi(fr_data_hi),
.datainlo(fr_data_lo),
.dataout(dataout[pin]),
.clkhi (clk_fr[pin]),
.clklo (clk_fr[pin]),
.muxsel (clk_fr[pin])
);
end
endgenerate
endmodule
|
//top file
module Floating_Point_Addition(clk,reset,x,y);
input clk,reset;
input [31:0] x,y;
//???????????????
wire[8:0] exp_diff; //????????????
wire mux_1_en; //???1 ????
wire mux_2_en; //???2 ????
wire mux_3_en; //???3 ????
wire[7:0] mux_1_output; //???1 ?????
wire[31:0] mux_2_output; //???2 ?????
wire[31:0] mux_3_output; //???3 ?????
wire[7:0] shift_right_bit; //????????????????
wire[26:0] shift_right_output; //?????????
wire[27:0] big_alu_result; //????????????
wire[7:0] shift_right_bits; //?????????????
wire[7:0] shift_left_bits; //?????????????
wire shift_right_en; //???????????????
wire shift_left_en; //???????????????
wire[27:0] mux_4_output; //???4 ?????
wire mux_4_en; //???4 ????
wire[27:0] shift_left_right_output; //??????????????????
wire[7:0] incre_bit; //??????????
wire[7:0] decre_bit; //??????????
wire incre_en; //????????????
wire decre_en; //????????????
wire mux_5_en; //???5 ????
wire[7:0] mux_5_output; //???5 ?????
wire[7:0] rounding_exp_result; //????????????
wire[8:0] incre_decre_output; //??????????????
wire[27:0] fra_result; //????
wire[31:0] result;
wire overflow; //?????
//?????????????????
Small_Alu
Small_Alu_instance(
//????
clk,
reset,
x,
y,
//????
exp_diff //????????????????
);
//???
Control
Control_instance(
clk,
reset,
exp_diff,
big_alu_result,
fra_result,
shift_right_bits,
shift_left_bits,
shift_right_en,
shift_left_en,
shift_right_bit,
incre_bit,
decre_bit,
incre_en,
decre_en,
mux_1_en,
mux_2_en,
mux_3_en,
mux_4_en,
mux_5_en
);
//???1
Mux_1
Mux_1_instance(
clk,
reset,
x,
y,
mux_1_en,
mux_1_output
);
//???2
Mux_2
Mux_2_instance(
clk,
reset,
x,
y,
mux_2_en,
mux_2_output
);
//???3
Mux_3
Mux_3_instance(
clk,
reset,
x,
y,
mux_3_en,
mux_3_output
);
Shift_Right //????????????????
Shift_Right_instance(
clk,
reset,
shift_right_bit,
mux_2_output,
shift_right_output //??shift_right_bit??mux_2_output ????
);
//???????????
Big_Alu
Big_Alu_instance(
clk,
reset,
shift_right_output,
mux_3_output,
big_alu_result //mux_3_output ?shift_right_output ????????big_alu_result
);
//???4
Mux_4
Mux_4_instance(
clk,
reset,
mux_4_en,
big_alu_result,
fra_result,
mux_4_output
);
Shift_Left_Right //???????????
Shift_Left_Right_instance(
clk,
reset,
shift_left_bits,
shift_right_bits,
shift_left_en,
shift_right_en,
mux_4_output,
shift_left_right_output
);
//???5
Mux_5
Mux_5_instance(
clk,
reset,
mux_5_en,
mux_1_output,
rounding_exp_result,
mux_5_output
);
Incre_Decre //???????????
Incre_Decre_instance(
clk,
reset,
incre_bit,
decre_bit,
incre_en,
decre_en,
mux_5_output,
incre_decre_output //??incre_bit ?incre_en??mux_5_output??????decre_bit ?decre_en??mux_5_output ???
);
//??????
Rounding
Rounding_instance(
clk,
reset,
shift_left_right_output,
incre_decre_output,
rounding_exp_result,
fra_result, //????
result,
overflow //????
);
endmodule |
//Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2014.4 (lin64) Build Tue Nov 18 16:47:07 MST 2014
//Date : Sun Apr 3 12:37:39 2016
//Host : ubuntu-desktop running 64-bit Ubuntu 14.04.4 LTS
//Command : generate_target design_1_wrapper.bd
//Design : design_1_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module design_1_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
design_1 design_1_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb));
endmodule
|
/*
* University of Illinois/NCSA
* Open Source License
*
* Copyright (c) 2007-2014,The Board of Trustees of the University of
* Illinois. All rights reserved.
*
* Copyright (c) 2014 Matthew Hicks
*
* Developed by:
*
* Matthew Hicks in the Department of Computer Science
* The University of Illinois at Urbana-Champaign
* http://www.impedimentToProgress.com
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated
* documentation files (the "Software"), to deal with the
* Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute,
* sublicense, and/or sell copies of the Software, and to permit
* persons to whom the Software is furnished to do so, subject
* to the following conditions:
*
* Redistributions of source code must retain the above
* copyright notice, this list of conditions and the
* following disclaimers.
*
* Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the
* following disclaimers in the documentation and/or other
* materials provided with the distribution.
*
* Neither the names of Sam King, the University of Illinois,
* nor the names of its contributors may be used to endorse
* or promote products derived from this Software without
* specific prior written permission.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE CONTRIBUTORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS WITH THE SOFTWARE.
*/
module ovl_always_on_edge_wrapped(
clk,
rst,
enable,
sampling_event,
test_expr,
prevConfigInvalid,
out
);
input clk;
input rst;
input enable;
input sampling_event;
input test_expr;
input prevConfigInvalid;
output out;
wire [2:0] result_3bit;
wire [2:0] result_3bit_comb;
ovl_always_on_edge ovl_always_on_edge(
.clock(clk),
.reset(rst),
.enable(enable),
.sampling_event(sampling_event),
.test_expr(test_expr),
.fire(result_3bit),
.fire_comb(result_3bit_comb)
);
assign out = result_3bit_comb[0] & ~prevConfigInvalid;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; for (int i = 0; i < t; i++) { int a, b, c; cin >> a >> b >> c; cout << a + b + c - (2 * (min(min(a, b), min(b, c)))) << endl; } } |
#include <bits/stdc++.h> using namespace std; const int M = 1e9 + 7; const int N = 2e5 + 1; const int oo = 1e9; const double pi = acos(-1); int main() { int t; cin >> t; while (t--) { int a, b, n; cin >> a >> b >> n; if (b < a) swap(a, b); int ans = 0; while (a <= n && b <= n) { ++ans; if (ans % 2) a += b; else b += a; } cout << ans << endl; } return 0; } |
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
//// ////
//// Description ////
//// This block is a wrapper with common single-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// single-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Supported ASIC RAMs are: ////
//// - Artisan Single-Port Sync RAM ////
//// - Avant! Two-Port Sync RAM (*) ////
//// - Virage Single-Port Sync RAM ////
//// - Virtual Silicon Single-Port Sync RAM ////
//// ////
//// Supported FPGA RAMs are: ////
//// - Xilinx Virtex RAMB16 ////
//// - Xilinx Virtex RAMB4 ////
//// - Altera LPM ////
//// ////
//// To Do: ////
//// - xilinx rams need external tri-state logic ////
//// - fix avant! two-port ram ////
//// - add additional RAMs ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2004/06/08 18:15:32 lampret
// Changed behavior of the simulation generic models
//
// Revision 1.1 2004/04/08 11:00:46 simont
// Add support for 512B instruction cache.
//
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_spram_32x24(
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, doq
);
//
// Default address and data buses width
//
parameter aw = 5;
parameter dw = 24;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
input rst; // Reset
input ce; // Chip enable input
input we; // Write enable input
input oe; // Output enable input
input [aw-1:0] addr; // address bus inputs
input [dw-1:0] di; // input data bus
output [dw-1:0] doq; // output data bus
//
// Internal wires and registers
//
`ifdef OR1200_XILINX_RAMB4
wire [31:24] unconnected;
`else
`ifdef OR1200_XILINX_RAMB16
wire [31:24] unconnected;
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
`endif
`endif
`endif
`ifdef OR1200_ARTISAN_SSP
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
`else
`ifdef OR1200_BIST
`else
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
`endif
`else
`ifdef OR1200_AVANT_ATP
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
`else
`ifdef OR1200_VIRAGE_SSP
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
`else
`ifdef OR1200_VIRTUALSILICON_SSP
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
`else
`ifdef OR1200_BIST
`else
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
`endif
`else
`ifdef OR1200_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
//
// Block 0
//
RAMB4_S16 ramb4_s16_0(
.CLK(clk),
.RST(rst),
.ADDR({3'h0, addr}),
.DI(di[15:0]),
.EN(ce),
.WE(we),
.DO(doq[15:0])
);
//
// Block 1
//
RAMB4_S16 ramb4_s16_1(
.CLK(clk),
.RST(rst),
.ADDR({3'h0, addr}),
.DI({8'h00, di[23:16]}),
.EN(ce),
.WE(we),
.DO({unconnected, doq[23:16]})
);
`else
`ifdef OR1200_XILINX_RAMB16
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
// Added By Nir Mor
//
RAMB16_S36 ramb16_s36(
.CLK(clk),
.SSR(rst),
.ADDR({4'b0000, addr}),
.DI({8'h00, di}),
.DIP(4'h0),
.EN(ce),
.WE(we),
.DO({unconnected, doq}),
.DOP()
);
`else
`ifdef OR1200_ALTERA_LPM
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
`else
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [aw-1:0] addr_reg; // RAM address register
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
//
// RAM address register
//
always @(posedge clk or posedge rst)
if (rst)
addr_reg <= #1 {aw{1'b0}};
else if (ce)
addr_reg <= #1 addr;
//
// RAM write
//
always @(posedge clk)
if (ce && we)
mem[addr] <= #1 di;
`endif // !OR1200_ALTERA_LPM
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`endif // !OR1200_VIRTUALSILICON_SSP
`endif // !OR1200_VIRAGE_SSP
`endif // !OR1200_AVANT_ATP
`endif // !OR1200_ARTISAN_SSP
endmodule
|
#include <bits/stdc++.h> int main() { float h, l; scanf( %f %f , &h, &l); float x = (l * l + h * h) / (2 * h) - h; printf( %f n , x); return 0; } |
`timescale 1ns / 1ps
module PS2_Controller #(parameter INITIALIZE_MOUSE = 0) (
// Inputs
CLOCK_50,
reset,
the_command,
send_command,
// Bidirectionals
PS2_CLK, // PS2 Clock
PS2_DAT, // PS2 Data
// Outputs
command_was_sent,
error_communication_timed_out,
received_data,
received_data_en // If 1 - new data has been received
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input CLOCK_50;
input reset;
input [7:0] the_command;
input send_command;
// Bidirectionals
inout PS2_CLK;
inout PS2_DAT;
// Outputs
output command_was_sent;
output error_communication_timed_out;
output [7:0] received_data;
output received_data_en;
wire [7:0] the_command_w;
wire send_command_w, command_was_sent_w, error_communication_timed_out_w;
generate
if(INITIALIZE_MOUSE) begin
assign the_command_w = init_done ? the_command : 8'hf4;
assign send_command_w = init_done ? send_command : (!command_was_sent_w && !error_communication_timed_out_w);
assign command_was_sent = init_done ? command_was_sent_w : 0;
assign error_communication_timed_out = init_done ? error_communication_timed_out_w : 1;
reg init_done;
always @(posedge CLOCK_50)
if(reset) init_done <= 0;
else if(command_was_sent_w) init_done <= 1;
end else begin
assign the_command_w = the_command;
assign send_command_w = send_command;
assign command_was_sent = command_was_sent_w;
assign error_communication_timed_out = error_communication_timed_out_w;
end
endgenerate
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// states
localparam PS2_STATE_0_IDLE = 3'h0,
PS2_STATE_1_DATA_IN = 3'h1,
PS2_STATE_2_COMMAND_OUT = 3'h2,
PS2_STATE_3_END_TRANSFER = 3'h3,
PS2_STATE_4_END_DELAYED = 3'h4;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
wire ps2_clk_posedge;
wire ps2_clk_negedge;
wire start_receiving_data;
wire wait_for_incoming_data;
// Internal Registers
reg [7:0] idle_counter;
reg ps2_clk_reg;
reg ps2_data_reg;
reg last_ps2_clk;
// State Machine Registers
reg [2:0] ns_ps2_transceiver;
reg [2:0] s_ps2_transceiver;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge CLOCK_50)
begin
if (reset == 1'b1)
s_ps2_transceiver <= PS2_STATE_0_IDLE;
else
s_ps2_transceiver <= ns_ps2_transceiver;
end
always @(*)
begin
// Defaults
ns_ps2_transceiver = PS2_STATE_0_IDLE;
case (s_ps2_transceiver)
PS2_STATE_0_IDLE:
begin
if ((idle_counter == 8'hFF) &&
(send_command == 1'b1))
ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
else if ((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_transceiver = PS2_STATE_1_DATA_IN;
else
ns_ps2_transceiver = PS2_STATE_0_IDLE;
end
PS2_STATE_1_DATA_IN:
begin
if ((received_data_en == 1'b1)/* && (ps2_clk_posedge == 1'b1)*/)
ns_ps2_transceiver = PS2_STATE_0_IDLE;
else
ns_ps2_transceiver = PS2_STATE_1_DATA_IN;
end
PS2_STATE_2_COMMAND_OUT:
begin
if ((command_was_sent == 1'b1) ||
(error_communication_timed_out == 1'b1))
ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
else
ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
end
PS2_STATE_3_END_TRANSFER:
begin
if (send_command == 1'b0)
ns_ps2_transceiver = PS2_STATE_0_IDLE;
else if ((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
else
ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
end
PS2_STATE_4_END_DELAYED:
begin
if (received_data_en == 1'b1)
begin
if (send_command == 1'b0)
ns_ps2_transceiver = PS2_STATE_0_IDLE;
else
ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
end
else
ns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
end
default:
ns_ps2_transceiver = PS2_STATE_0_IDLE;
endcase
end
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
always @(posedge CLOCK_50)
begin
if (reset == 1'b1)
begin
last_ps2_clk <= 1'b1;
ps2_clk_reg <= 1'b1;
ps2_data_reg <= 1'b1;
end
else
begin
last_ps2_clk <= ps2_clk_reg;
ps2_clk_reg <= PS2_CLK;
ps2_data_reg <= PS2_DAT;
end
end
always @(posedge CLOCK_50)
begin
if (reset == 1'b1)
idle_counter <= 6'h00;
else if ((s_ps2_transceiver == PS2_STATE_0_IDLE) &&
(idle_counter != 8'hFF))
idle_counter <= idle_counter + 6'h01;
else if (s_ps2_transceiver != PS2_STATE_0_IDLE)
idle_counter <= 6'h00;
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
assign ps2_clk_posedge =
((ps2_clk_reg == 1'b1) && (last_ps2_clk == 1'b0)) ? 1'b1 : 1'b0;
assign ps2_clk_negedge =
((ps2_clk_reg == 1'b0) && (last_ps2_clk == 1'b1)) ? 1'b1 : 1'b0;
assign start_receiving_data = (s_ps2_transceiver == PS2_STATE_1_DATA_IN);
assign wait_for_incoming_data =
(s_ps2_transceiver == PS2_STATE_3_END_TRANSFER);
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
Altera_UP_PS2_Data_In PS2_Data_In (
// Inputs
.clk (CLOCK_50),
.reset (reset),
.wait_for_incoming_data (wait_for_incoming_data),
.start_receiving_data (start_receiving_data),
.ps2_clk_posedge (ps2_clk_posedge),
.ps2_clk_negedge (ps2_clk_negedge),
.ps2_data (ps2_data_reg),
// Bidirectionals
// Outputs
.received_data (received_data),
.received_data_en (received_data_en)
);
Altera_UP_PS2_Command_Out PS2_Command_Out (
// Inputs
.clk (CLOCK_50),
.reset (reset),
.the_command (the_command_w),
.send_command (send_command_w),
.ps2_clk_posedge (ps2_clk_posedge),
.ps2_clk_negedge (ps2_clk_negedge),
// Bidirectionals
.PS2_CLK (PS2_CLK),
.PS2_DAT (PS2_DAT),
// Outputs
.command_was_sent (command_was_sent_w),
.error_communication_timed_out (error_communication_timed_out_w)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; char s[5050], t[5050], goal[5050]; int cnt[200], l, l2; bool dfs(int p, bool v) { if (p == l2) { if (v) return puts(goal), 1; else return 0; } if (v) { for (int i = a ; i < z + 1; i++) if (cnt[i] > 0) { cnt[i] -= 1; goal[p] = i; return dfs(p + 1, v); } return 1; } else { for (int i = a ; i < z + 1; i++) if (cnt[i] > 0 && i >= t[p]) { cnt[i] -= 1; goal[p] = i; if (dfs(p + 1, v | (i > t[p]))) return 1; cnt[i] += 1; } } return 0; } int main() { scanf( %s%s , s, t); l = strlen(t); l2 = strlen(s); for (int i = 0; i < l2; i++) cnt[s[i]]++; if (!dfs(0, 0)) puts( -1 ); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2BB2AI_SYMBOL_V
`define SKY130_FD_SC_MS__O2BB2AI_SYMBOL_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o2bb2ai (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2BB2AI_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLXBN_1_V
`define SKY130_FD_SC_HS__DLXBN_1_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Verilog wrapper for dlxbn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dlxbn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlxbn_1 (
Q ,
Q_N ,
D ,
GATE_N,
VPWR ,
VGND
);
output Q ;
output Q_N ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__dlxbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlxbn_1 (
Q ,
Q_N ,
D ,
GATE_N
);
output Q ;
output Q_N ;
input D ;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__dlxbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLXBN_1_V
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2018 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2018.3
// \ \ Description : Xilinx Unified Simulation Library Component
// / / OBUFDS_GTM_ADV
// /___/ /\ Filename : OBUFDS_GTM_ADV.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module OBUFDS_GTM_ADV #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [0:0] REFCLK_EN_TX_PATH = 1'b0,
parameter integer REFCLK_ICNTL_TX = 0,
parameter [1:0] RXRECCLK_SEL = 2'b00
)(
output O,
output OB,
input CEB,
input [3:0] I
);
// define constants
localparam MODULE_NAME = "OBUFDS_GTM_ADV";
reg trig_attr;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "OBUFDS_GTM_ADV_dr.v"
`else
reg [0:0] REFCLK_EN_TX_PATH_REG = REFCLK_EN_TX_PATH;
reg [31:0] REFCLK_ICNTL_TX_REG = REFCLK_ICNTL_TX;
reg [1:0] RXRECCLK_SEL_REG = RXRECCLK_SEL;
`endif
`ifdef XIL_XECLIB
wire [3:0] REFCLK_ICNTL_TX_BIN;
`else
reg [3:0] REFCLK_ICNTL_TX_BIN;
`endif
`ifdef XIL_XECLIB
reg glblGSR = 1'b0;
reg glblGTS = 1'b0;
`else
tri0 glblGSR = glbl.GSR;
tri0 glblGTS = glbl.GTS;
`endif
`ifndef XIL_XECLIB
reg attr_test;
reg attr_err;
initial begin
trig_attr = 1'b0;
`ifdef XIL_ATTR_TEST
attr_test = 1'b1;
`else
attr_test = 1'b0;
`endif
attr_err = 1'b0;
#1;
trig_attr = ~trig_attr;
end
`endif
`ifdef XIL_XECLIB
assign REFCLK_ICNTL_TX_BIN = REFCLK_ICNTL_TX_REG[3:0];
`else
always @ (trig_attr) begin
#1;
REFCLK_ICNTL_TX_BIN = REFCLK_ICNTL_TX_REG[3:0];
end
`endif
`ifndef XIL_XECLIB
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((REFCLK_ICNTL_TX_REG != 0) &&
(REFCLK_ICNTL_TX_REG != 1) &&
(REFCLK_ICNTL_TX_REG != 3) &&
(REFCLK_ICNTL_TX_REG != 7) &&
(REFCLK_ICNTL_TX_REG != 15))) begin
$display("Error: [Unisim %s-102] REFCLK_ICNTL_TX attribute is set to %d. Legal values for this attribute are 0, 1, 3, 7 or 15. Instance: %m", MODULE_NAME, REFCLK_ICNTL_TX_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
`endif
// begin behavioral model
reg I_sel = 1'b0;
// =====================
// Generate I_sel
// =====================
always @(*) begin
case (RXRECCLK_SEL_REG)
2'b00: I_sel <= I[0];
2'b01: I_sel <= I[1];
2'b10: I_sel <= I[2];
2'b11: I_sel <= I[3];
default : I_sel <= I[0];
endcase
end
// =====================
// Generate O
// =====================
assign O = (~REFCLK_EN_TX_PATH_REG || (CEB === 1'b1) || glblGTS) ? 1'bz : I_sel;
assign OB = (~REFCLK_EN_TX_PATH_REG || (CEB === 1'b1) || glblGTS) ? 1'bz : ~I_sel;
`ifndef XIL_XECLIB
`ifdef XIL_TIMING
specify
(CEB => O) = (0:0:0, 0:0:0);
(CEB => OB) = (0:0:0, 0:0:0);
(I[0] => O) = (0:0:0, 0:0:0);
(I[0] => OB) = (0:0:0, 0:0:0);
(I[1] => O) = (0:0:0, 0:0:0);
(I[1] => OB) = (0:0:0, 0:0:0);
(I[2] => O) = (0:0:0, 0:0:0);
(I[2] => OB) = (0:0:0, 0:0:0);
(I[3] => O) = (0:0:0, 0:0:0);
(I[3] => OB) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
`endif
// end behavioral model
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; int a = 0; for (int i = 0; i < s.size(); i++) { if (s[i] == a ) a++; } for (int i = s.size(); i >= a; i--) { if (a > (i / 2)) { cout << i << endl; exit(0); } } } |
module example;
reg [7:0] vec;
reg [3:0] ix;
wire vix = vec[ix];
initial begin
$display( " time ix vix vec" );
$display( " ---- ---- --- --------" );
$monitor( "%T %b %b %b", $time, ix, vix, vec );
vec = 8'b00000000;
ix = 0; // 0
#100 ix = 1; // 100
#100 ix = 2; // 200
#100 ix = 3; // 300
#100 ix = 4; // 400
#100 ix = 5; // 500
#100 ix = 6; // 600
#100 ix = 7; // 700
#100 ix = 8; // 800
#100 ix = 4'b001x; // 900
#100 ix = 4'b01x0; // 1000
#100 ix = 4'b0x01; // 1100
#100 ix = 0; // 1200
#100 vec[ix] <= 1'b1; // 1300
#100 vec[ix] <= 1'b0; // 1400
#100 ix = 3; // 1500
#100 vec[ix] <= 1'b1; // 1600
#100 vec[ix] <= 1'b0; // 1700
#100 ix = 6; // 1800
#100 vec[ix] <= 1'b1; // 1900
#100 vec[ix] <= 1'b0; // 2000
#100 ix = 8; // 2100
#100 vec[ix] <= 1'b1; // 2200
#100 vec[ix] <= 1'b0; // 2300
#100 ix = 4'b010x; // 2400
#100 vec[ix] <= 1'b1; // 2500
#100 vec[ix] <= 1'b0; // 2600
#100 ix = 4'b00x1; // 2700
#100 vec[ix] <= 1'b1; // 2800
#100 vec[ix] <= 1'b0; // 2900
#100 ix = 4'b0x10; // 3000
#100 vec[ix] <= 1'b1; // 3100
#100 vec[ix] <= 1'b0; // 3200
#100 ix = 4'bxxxx; // 3300
#100 vec[ix] <= 1'b1; // 3400
#100 vec[ix] <= 1'b0; // 3500
#100 $display( "Finish at time %T", $time );
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int q, n; int par[1 << 20][32], dep[1 << 20]; int da[500000]; void add(int v) { par[n][0] = par[n + 1][0] = v; dep[n] = dep[n + 1] = dep[v] + 1; for (int i = (int)(0); i < (int)(20); i++) par[n][i + 1] = par[n + 1][i + 1] = par[par[n][i]][i]; } int lca(int u, int v) { if (dep[u] > dep[v]) swap(u, v); int dif = dep[v] - dep[u]; for (int i = (int)(0); i < (int)(21); i++) if (dif & (1 << i)) v = par[v][i]; if (u == v) return u; for (int i = 20; i >= 0; i--) if (par[u][i] != par[v][i]) { u = par[u][i]; v = par[v][i]; } return par[u][0]; } int dist(int u, int v) { return dep[u] + dep[v] - 2 * dep[lca(u, v)]; } void solve() { int u = 2, v = 3, d = 2, x, i = 0, jos = q; ; dep[2] = dep[3] = dep[4] = 1; par[2][0] = par[3][0] = par[4][0] = 1; n = 5; while (q--) { scanf( %d , &x); add(x); int du = dist(n, u), dv = dist(n, v); if (du > d) v = n, d = du; else if (dv > d) u = n, d = dv; n += 2; da[i] = d; i++; } int j; for (j = 0; j < jos; j++) { printf( %d n , da[j]); } } int main() { scanf( %d , &q); solve(); return 0; } |
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// The PLL module, need to be replaced with real PLL in ASIC flow
//
// ====================================================================
`include "e203_defines.v"
module e203_subsys_pllclkdiv(
input rst_n,
input test_mode,
input divby1,
input [5:0] div,
input clk,// The PLL clock
output clkout // The divided Clock
);
wire [5:0] div_cnt_r;
wire div_cnt_sat = (div_cnt_r == div);
wire [5:0] div_cnt_nxt = div_cnt_sat ? 6'b0 : (div_cnt_r + 1'b1);
wire div_cnt_ena = (~divby1);
sirv_gnrl_dfflr #(6) div_cnt_dfflr (div_cnt_ena, div_cnt_nxt, div_cnt_r, clk, rst_n);
wire flag_r;
wire flag_nxt = ~flag_r;
wire flag_ena = div_cnt_ena & div_cnt_sat;
sirv_gnrl_dfflr #(1) flag_dfflr (flag_ena, flag_nxt, flag_r, clk, rst_n);
wire plloutdiv_en = divby1 |
((~flag_r) & div_cnt_sat);
e203_clkgate u_pllclkdiv_clkgate(
.clk_in (clk ),
.test_mode(test_mode ),
.clock_en (plloutdiv_en),
.clk_out (clkout)
);
endmodule
|
/*******************************************************************
*****串口发送模块
*****
*****
*******************************************************************/
module Uart_tx(
input clk,
input rst_n,
input [3:0] num, //一帧数据有几位由num来决定
input sel_data, //波特率技计数中心点（采集数据的使能信号）
input [7:0] rx_data,
output reg rs232_tx
);
always @(posedge clk or negedge rst_n)
if(!rst_n)
rs232_tx <= 1'b1;
else
if(sel_data) //检测波特率采样中心点（使能信号）
case(num) //检测要发送的一帧数据有几位？
0: rs232_tx <= 1'b0; //开始位为低电平
1: rs232_tx <= rx_data[0];
2: rs232_tx <= rx_data[1];
3: rs232_tx <= rx_data[2];
4: rs232_tx <= rx_data[3];
5: rs232_tx <= rx_data[4];
6: rs232_tx <= rx_data[5];
7: rs232_tx <= rx_data[6];
8: rs232_tx <= rx_data[7];
9: rs232_tx <= 1'b1; //结束位为高电平
default: rs232_tx <= 1'b1; //在其他情况下一直处于拉高电平状态
endcase
endmodule |
#include <bits/stdc++.h> using namespace std; int type[100005]; int lead[100005], degree[100005]; vector<int> go(int n) { vector<int> v; while (true) { if (degree[n] > 1) { return v; } else if (lead[n] == -1) { v.push_back(n); return v; } v.push_back(n); n = lead[n]; } } int main() { int n; cin >> n; for (int i = 0; i < n; ++i) cin >> type[i]; for (int i = 0; i < n; ++i) { cin >> lead[i]; --lead[i]; if (lead[i] >= 0) ++degree[lead[i]]; } vector<int> best; for (int i = 0; i < n; ++i) { vector<int> cur; if (type[i]) cur = go(i); if (cur.size() > best.size()) best = cur; } reverse(best.begin(), best.end()); cout << best.size() << n ; for (int i = 0; i < best.size(); ++i) { cout << best[i] + 1 << ; } cout << endl; } |
#include <bits/stdc++.h> using namespace std; void smain(); int main() { ios::sync_with_stdio(false); smain(); return 0; } const int maxn = 300000 + 10; int num[maxn]; int num1[maxn], num2[maxn]; int tot = 1; int min1[maxn], min2[maxn]; int la1[maxn], la2[maxn]; int flo(int a, int b) { int ans = a / b; if (a % b != 0) ans++; return ans; } const int INF = 2e9; int a1[maxn], a2[maxn]; int flag[maxn]; bool cal(int n, int *Min, int *La, int *This, int *a1, int *a2) { bool flagg = false; int A1, A2; for (int i = (2); i <= (n); ++i) { if (Min[i - 1] == INF || This[i] == INF) continue; if (Min[i - 1] + This[i] <= i) { flagg = true; A1 = La[i - 1]; A2 = i; break; } } if (!flagg) return false; a1[0] = Min[A1]; a2[0] = This[A2]; int i = 1, j = 1; for (j = 1; j < a1[0]; ++i) { a1[j] = flag[i]; ++j; } a1[j] = flag[A1]; for (j = 1; j < a2[0]; ++i) { if (i == A1) continue; a2[j] = flag[i]; ++j; } a2[j] = flag[A2]; return true; } struct Node { int o, flag; } node[maxn]; bool cmp(Node a, Node b) { return a.o > b.o; } void smain() { int n, x1, x2; cin >> n >> x1 >> x2; for (int i = (1); i <= (n); ++i) cin >> num[i]; for (int i = (1); i <= (n); ++i) node[i].o = num[i], node[i].flag = i; sort(node + 1, node + n + 1, cmp); for (int i = (1); i <= (n); ++i) num[i] = node[i].o, flag[i] = node[i].flag; int tmp; for (int i = (1); i <= (n); ++i) { tmp = flo(x1, num[i]); if (tmp > i) tmp = INF; min1[i] = num1[i] = tmp; tmp = flo(x2, num[i]); if (tmp > i) tmp = INF; min2[i] = num2[i] = tmp; la1[i] = la2[i] = i; } for (int i = (2); i <= (n); ++i) { if (min1[i - 1] <= min1[i]) { min1[i] = min1[i - 1]; la1[i] = la1[i - 1]; } if (min2[i - 1] <= min2[i]) { min2[i] = min2[i - 1]; la2[i] = la2[i - 1]; } } int ans1 = -1, ans2 = -1; if (cal(n, min1, la1, num2, a1, a2)) { } else if (cal(n, min2, la2, num1, a2, a1)) { } else { cout << No << endl; return; } cout << Yes << endl; cout << a1[0] << << a2[0] << endl; for (int i = 1; a1[i] != 0; ++i) cout << a1[i] << ; cout << endl; for (int i = 1; a2[i] != 0; ++i) cout << a2[i] << ; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 100; int n, p[4], bx[N], wx, by[N], wy, sum[N][4]; vector<int> wh[N]; struct node { int x, y, c; } sh[N]; bool cmp(node a, node b) { return a.x < b.x; } inline int read() { int f = 1, x = 0; char s = getchar(); while (s < 0 || s > 9 ) { if (s == - ) f = -1; s = getchar(); } while (s >= 0 && s <= 9 ) { x = x * 10 + s - 0 ; s = getchar(); } return x * f; } struct bit { int sh[N]; void init() { memset(sh, 0, sizeof(sh)); } int lowbit(int x) { return x & (-x); } void change(int x, int v) { while (x <= n) sh[x] += v, x += lowbit(x); } int query(int x) { int ans = 0; while (x) ans += sh[x], x -= lowbit(x); return ans; } int ask(int l, int r) { return query(r) - query(l - 1); } } T[4]; int g(int l, int r, int c) { return sum[r][c] - sum[l - 1][c]; } void init() { memset(sum, 0, sizeof(sum)); wx = wy = 0; for (int i = 1; i <= n; i++) bx[++wx] = sh[i].x; sort(bx + 1, bx + 1 + wx); wx = unique(bx + 1, bx + 1 + wx) - bx - 1; for (int i = 1; i <= n; i++) sh[i].x = lower_bound(bx + 1, bx + 1 + wx, sh[i].x) - bx; for (int i = 1; i <= n; i++) by[++wy] = sh[i].y; sort(by + 1, by + 1 + wy); wy = unique(by + 1, by + 1 + wy) - by - 1; for (int i = 1; i <= n; i++) sh[i].y = lower_bound(by + 1, by + 1 + wy, sh[i].y) - by; sort(sh + 1, sh + 1 + n, cmp); for (int i = 1; i <= n; i++) sum[sh[i].x][sh[i].c]++; for (int i = 1; i <= wx; i++) for (int j = 1; j <= 3; j++) sum[i][j] += sum[i - 1][j]; } int solve() { for (int i = 1; i <= wx; i++) wh[i].clear(); for (int i = 1; i <= n; i++) wh[sh[i].x].push_back(i); for (int i = 1; i <= 3; i++) p[i] = i; int ans = 1; do { for (int i = 2; i <= wx; i++) { int A = sum[i - 1][p[1]], l = i, r = wx - 1; while (l < r) { int mid = l + ((r - l + 1) >> 1); if (g(i, mid, p[2]) <= g(mid + 1, wx, p[3])) l = mid; else r = mid - 1; } ans = max(ans, min({A, g(i, l, p[2]), g(l + 1, wx, p[3])})); l++; ans = max(ans, min({A, g(i, l, p[2]), g(l + 1, wx, p[3])})); } } while (next_permutation(p + 1, p + 4)); for (int i = 1; i <= 3; i++) p[i] = i; auto find = [](int A, int &ans) { int l = 1, r = wy - 1; while (l < r) { int mid = l + ((r - l + 1) >> 1); if (T[p[2]].ask(1, mid) <= T[p[3]].ask(mid + 1, wy)) l = mid; else r = mid - 1; } ans = max(ans, min({A, T[p[2]].ask(1, l), T[p[3]].ask(l + 1, wy)})); l++; ans = max(ans, min({A, T[p[2]].ask(1, l), T[p[3]].ask(l + 1, wy)})); }; do { T[p[2]].init(); T[p[3]].init(); for (int i = wx; i >= 1; i--) { int A = g(1, i, p[1]); find(A, ans); for (int j : wh[i]) if (sh[j].c != p[1]) T[sh[j].c].change(sh[j].y, 1); } } while (next_permutation(p + 1, p + 4)); for (int i = 1; i <= 3; i++) p[i] = i; do { T[p[2]].init(); T[p[3]].init(); for (int i = 1; i <= wx; i++) { int A = g(i, wx, p[1]); find(A, ans); for (int j : wh[i]) if (sh[j].c != p[1]) T[sh[j].c].change(sh[j].y, 1); } } while (next_permutation(p + 1, p + 4)); return ans; } signed main() { n = read(); for (int i = 1; i <= n; i++) sh[i] = (node){read(), read(), read()}; init(); int ans = solve(); for (int i = 1; i <= n; i++) swap(sh[i].x, sh[i].y); init(); ans = max(ans, solve()); printf( %d n , ans * 3); } |
#include <bits/stdc++.h> using namespace std; long long ans[60]; int main() { long long t, a, n, m, b, v, xmin, xmax, act, sum, i, vmi; cin >> t; while (t--) { cin >> a >> b >> m; if (a == b) { cout << 1 << a << n ; continue; } for (n = 2; n <= 50; n++) { v = ((1ll) << (n - 2)); xmin = v * a + v; xmax = v * a + v * m; if (xmin > b) { n = 51; break; } if (b <= xmax) { act = xmax; ans[1] = a; sum = ans[1]; for (i = 2; i <= n; i++) { v = ((1ll) << (max(n - i - 1, 0ll))); vmi = m - (act - b) / v; vmi = max(vmi, 1ll); ans[i] = sum + vmi; sum = sum + ans[i]; act -= (m - vmi) * v; } if (i <= n || ans[n] != b) continue; cout << n << ; for (i = 1; i <= n; i++) cout << ans[i] << ; cout << n ; break; } } if (n == 51) { cout << -1 << n ; } } return 0; } |
/*
* University of Illinois/NCSA
* Open Source License
*
* Copyright (c) 2007-2014,The Board of Trustees of the University of
* Illinois. All rights reserved.
*
* Copyright (c) 2014 Matthew Hicks
*
* Developed by:
*
* Matthew Hicks in the Department of Computer Science
* The University of Illinois at Urbana-Champaign
* http://www.impedimentToProgress.com
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated
* documentation files (the "Software"), to deal with the
* Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute,
* sublicense, and/or sell copies of the Software, and to permit
* persons to whom the Software is furnished to do so, subject
* to the following conditions:
*
* Redistributions of source code must retain the above
* copyright notice, this list of conditions and the
* following disclaimers.
*
* Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the
* following disclaimers in the documentation and/or other
* materials provided with the distribution.
*
* Neither the names of Sam King, the University of Illinois,
* nor the names of its contributors may be used to endorse
* or promote products derived from this Software without
* specific prior written permission.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE CONTRIBUTORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS WITH THE SOFTWARE.
*/
`ifdef SMV
`include "ovl_ported/std_ovl_defines.h"
`else
`include "std_ovl_defines.h"
`endif
`module ovl_combo (clock, reset, enable, num_cks, start_event, test_expr, select, fire_comb);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter check_overlapping = 1;
parameter check_missing_start = 0;
parameter num_cks_max = 7;
parameter num_cks_width = 3;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input [num_cks_width-1:0] num_cks;
input start_event, test_expr;
input [1:0] select;
output [`OVL_FIRE_WIDTH-1:0] fire_comb;
// Parameters that should not be edited
parameter assert_name = "OVL_COMBO";
`ifdef SMV
`include "ovl_ported/std_ovl_reset.h"
`include "ovl_ported/std_ovl_clock.h"
`include "ovl_ported/std_ovl_cover.h"
`include "ovl_ported/std_ovl_init.h"
`else
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`endif // !`ifdef SMV
`ifdef SMV
`include "./ovl_ported/vlog95/ovl_combo_logic.v"
`else
`include "./vlog95/ovl_combo_logic.v"
`endif
assign fire_comb = {2'b0, fire_2state_comb};
`endmodule |
module signed_logic_operators_bug();
reg [7:0] a, b;
wire [15:0] yuu, yus, ysu, yss;
wire [15:0] zuu, zus, zsu, zss;
initial begin
// Example vector
a = 8'b10110110;
b = 8'b10010010;
// Wait for results to be calculated
#1;
// Display results
$display("a = %b", a);
$display("b = %b", b);
$display("yuu = %b", yuu);
$display("zuu = %b", zuu);
$display("yus = %b", yus);
$display("zus = %b", zus);
$display("ysu = %b", ysu);
$display("zsu = %b", zsu);
$display("yss = %b", yss);
$display("zss = %b", zss);
// Finished
$finish;
end
// Calculate signed logical OR
manually_extended_logical_or INST1(.a(a), .b(b), .yuu(yuu), .yus(yus), .ysu(ysu), .yss(yss));
signed_logical_or INST2(.a(a), .b(b), .yuu(zuu), .yus(zus), .ysu(zsu), .yss(zss));
endmodule
module manually_extended_logical_or(a, b, yuu, yus, ysu, yss);
input [7:0] a, b;
output [15:0] yuu, yus, ysu, yss;
// Manually zero or sign extend operands before logic OR
// - Note the operands are zero extended in "yuu", "yus" and "ysu"
// - The operands are sign extended in "yss"
assign yuu = {{8{1'b0}}, a} | {{8{1'b0}}, b};
assign yus = {{8{1'b0}}, a} | {{8{1'b0}}, b};
assign ysu = {{8{1'b0}}, a} | {{8{1'b0}}, b};
assign yss = {{8{a[7]}}, a} | {{8{b[7]}}, b};
endmodule
module signed_logical_or(a, b, yuu, yus, ysu, yss);
input [7:0] a, b;
output [15:0] yuu, yus, ysu, yss;
// Note that the operation is only consider signed if ALL data operands are signed
// - Therefore $signed(a) does NOT sign extend "a" in expression "ysu"
// - But "a" and "b" are both sign extended before the OR in expression "yss"
assign yuu = a | b ;
assign yus = a | $signed(b);
assign ysu = $signed(a) | b ;
assign yss = $signed(a) | $signed(b);
endmodule
|
/* SPDX-License-Identifier: MIT */
/* (c) Copyright 2018 David M. Koltak, all rights reserved. */
/*
* rcn bus slave interface - zero cycle read delay (aka "fast")
*
*/
module rcn_slave_fast
(
input rst,
input clk,
input [68:0] rcn_in,
output [68:0] rcn_out,
output cs,
output wr,
output [3:0] mask,
output [23:0] addr,
output [31:0] wdata,
input [31:0] rdata
);
parameter ADDR_MASK = 0;
parameter ADDR_BASE = 1;
reg [68:0] rin;
reg [68:0] rout;
assign rcn_out = rout;
wire [23:0] my_mask = ADDR_MASK;
wire [23:0] my_base = ADDR_BASE;
wire my_req = rin[68] && rin[67] && ((rin[55:34] & my_mask[23:2]) == my_base[23:2]);
wire [68:0] my_resp;
always @ (posedge clk or posedge rst)
if (rst)
begin
rin <= 68'd0;
rout <= 68'd0;
end
else
begin
rin <= rcn_in;
rout <= (my_req) ? my_resp : rin;
end
assign cs = my_req;
assign wr = rin[66];
assign mask = rin[59:56];
assign addr = {rin[55:34], 2'd0};
assign wdata = rin[31:0];
assign my_resp = {1'b1, 1'b0, rin[66:32], rdata};
endmodule
|
#include <bits/stdc++.h> using namespace std; const signed long long Infinity = 1000000100; const long double Epsilon = 1e-9; template <typename T, typename U> ostream& operator<<(ostream& os, const pair<T, U>& p) { return os << ( << p.first << , << p.second << ) ; } template <typename T> ostream& operator<<(ostream& os, const vector<T>& V) { os << [ ; for (int(i) = (0); (i) < (int(V.size())); (i)++) os << V[i] << ((i == int(V.size()) - 1) ? : , ); return os << ] ; } template <typename T> ostream& operator<<(ostream& os, const set<T>& S) { os << ( ; for (__typeof(S.begin()) i = S.begin(); i != S.end(); ++i) os << *i << (*i == *S.rbegin() ? : , ); return os << ) ; } template <typename T, typename U> ostream& operator<<(ostream& os, const map<T, U>& M) { os << { ; for (__typeof(M.begin()) i = M.begin(); i != M.end(); ++i) os << *i << (*i.first == M.rbegin()->first ? : , ); return os << } ; } int Rep[555][555]; int REP[555 * 555]; int Siz[555 * 555]; int Find(int a) { if (REP[a] != a) REP[a] = Find(REP[a]); return REP[a]; } void Union(int a, int b) { a = Find(a); b = Find(b); if (a == b) return; REP[a] = b; Siz[b] += Siz[a]; } char T[555][555]; int dx[] = {1, -1, 0, 0}; int dy[] = {0, 0, 1, -1}; void U(int a, int b) { if (T[a][b] == X ) return; for (int(i) = (0); (i) <= (3); (i)++) { if (T[a + dx[i]][b + dy[i]] == X ) continue; Union(Rep[a][b], Rep[a + dx[i]][b + dy[i]]); Rep[a + dx[i]][b + dy[i]] = Rep[a][b] = Find(Rep[a][b]); } } int state[555 * 555]; int sum; int ans; void add(int a) { if (state[a] == 0) sum += Siz[a]; state[a]++; } void rem(int a) { state[a]--; if (state[a] == 0) sum -= Siz[a]; } int n; void a(int a, int b) { if (T[a][b] == X and a != 0 and b != 0 and a != n + 1 and b != n + 1) sum++; } void r(int a, int b) { if (T[a][b] == X and a != 0 and b != 0 and a != n + 1 and b != n + 1) sum--; } int main() { int k; scanf( %d%d , &n, &k); for (int(i) = (1); (i) <= (n); (i)++) for (int(j) = (1); (j) <= (n); (j)++) { scanf( %c , &T[i][j]); Rep[i][j] = i + (j - 1) * n; REP[i + (j - 1) * n] = i + (j - 1) * n; Siz[i + (j - 1) * n] = T[i][j] != X ; } for (int(i) = (0); (i) <= (n + 1); (i)++) T[i][0] = T[0][i] = T[i][n + 1] = T[n + 1][i] = X ; for (int(i) = (1); (i) <= (n); (i)++) for (int(j) = (1); (j) <= (n); (j)++) U(i, j); for (int(i) = (0); (i) <= (n); (i)++) { if (i + k + 1 > n + 1) break; for (int(j) = (0); (j) <= (555 * 555 - 1); (j)++) state[j] = 0; sum = 0; for (int(j) = (0); (j) <= (n + 1); (j)++) { for (int(l) = (1); (l) <= (k); (l)++) add(Find(Rep[i + l][j])); if (j > 0) add(Find(Rep[i][j - 1])); if (j > 0) add(Find(Rep[i + k + 1][j - 1])); if (j > 0) for (int(l) = (1); (l) <= (k); (l)++) a(i + l, j - 1); if (j - k - 2 >= 0) for (int(l) = (1); (l) <= (k); (l)++) rem(Find(Rep[i + l][j - k - 2])); if (j - k - 1 >= 0) rem(Find(Rep[i][j - k - 1])); if (j - k - 1 >= 0) rem(Find(Rep[i + k + 1][j - k - 1])); if (j - k - 1 >= 0) for (int(l) = (1); (l) <= (k); (l)++) r(i + l, j - k - 1); ans = max(ans, sum); } } printf( %d n , ans); return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Sun May 28 20:04:14 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_clk_wiz_1_0 -prefix
// system_clk_wiz_1_0_ system_clk_wiz_1_0_stub.v
// Design : system_clk_wiz_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module system_clk_wiz_1_0(clk_out1, locked, clk_in1)
/* synthesis syn_black_box black_box_pad_pin="clk_out1,locked,clk_in1" */;
output clk_out1;
output locked;
input clk_in1;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INV_8_V
`define SKY130_FD_SC_LP__INV_8_V
/**
* inv: Inverter.
*
* Verilog wrapper for inv with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__inv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__inv_8 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__inv_8 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__inv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__INV_8_V
|
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_protocol_converter_v2_1_7_b2s_r_channel.v
//
// Description:
// Read data channel module to buffer read data from MC, ignore
// extra data in case of BL8 and send the data to AXI.
// The MC will send out the read data as it is ready and it has to be
// accepted. The read data FIFO in the axi_protocol_converter_v2_1_7_b2s_r_channel module will buffer
// the data before being sent to AXI. The address channel module will
// send the transaction information for every command that is sent to the
// MC. The transaction information will be buffered in a transaction FIFO.
// Based on the transaction FIFO information data will be ignored in
// BL8 mode and the last signal to the AXI will be asserted.
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_7_b2s_r_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of ID signals.
// Range: >= 1.
parameter integer C_ID_WIDTH = 4,
// Width of AXI xDATA and MCB xx_data
// Range: 32, 64, 128.
parameter integer C_DATA_WIDTH = 32
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire reset ,
output wire [C_ID_WIDTH-1:0] s_rid ,
output wire [C_DATA_WIDTH-1:0] s_rdata ,
output wire [1:0] s_rresp ,
output wire s_rlast ,
output wire s_rvalid ,
input wire s_rready ,
input wire [C_DATA_WIDTH-1:0] m_rdata ,
input wire [1:0] m_rresp ,
input wire m_rvalid ,
output wire m_rready ,
// Connections to/from axi_protocol_converter_v2_1_7_b2s_ar_channel module
input wire r_push ,
output wire r_full ,
// length not needed. Can be removed.
input wire [C_ID_WIDTH-1:0] r_arid ,
input wire r_rlast
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam P_WIDTH = 1+C_ID_WIDTH;
localparam P_DEPTH = 32;
localparam P_AWIDTH = 5;
localparam P_D_WIDTH = C_DATA_WIDTH + 2;
// rd data FIFO depth varies based on burst length.
// For Bl8 it is two times the size of transaction FIFO.
// Only in 2:1 mode BL8 transactions will happen which results in
// two beats of read data per read transaction.
localparam P_D_DEPTH = 32;
localparam P_D_AWIDTH = 5;
////////////////////////////////////////////////////////////////////////////////
// Wire and register declarations
////////////////////////////////////////////////////////////////////////////////
wire [C_ID_WIDTH+1-1:0] trans_in;
wire [C_ID_WIDTH+1-1:0] trans_out;
wire tr_empty;
wire rhandshake;
wire r_valid_i;
wire [P_D_WIDTH-1:0] rd_data_fifo_in;
wire [P_D_WIDTH-1:0] rd_data_fifo_out;
wire rd_en;
wire rd_full;
wire rd_empty;
wire rd_a_full;
wire fifo_a_full;
reg [C_ID_WIDTH-1:0] r_arid_r;
reg r_rlast_r;
reg r_push_r;
wire fifo_full;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
assign s_rresp = rd_data_fifo_out[P_D_WIDTH-1:C_DATA_WIDTH];
assign s_rid = trans_out[1+:C_ID_WIDTH];
assign s_rdata = rd_data_fifo_out[C_DATA_WIDTH-1:0];
assign s_rlast = trans_out[0];
assign s_rvalid = ~rd_empty & ~tr_empty;
// assign MCB outputs
assign rd_en = rhandshake & (~rd_empty);
assign rhandshake =(s_rvalid & s_rready);
// register for timing
always @(posedge clk) begin
r_arid_r <= r_arid;
r_rlast_r <= r_rlast;
r_push_r <= r_push;
end
assign trans_in[0] = r_rlast_r;
assign trans_in[1+:C_ID_WIDTH] = r_arid_r;
// rd data fifo
axi_protocol_converter_v2_1_7_b2s_simple_fifo #(
.C_WIDTH (P_D_WIDTH),
.C_AWIDTH (P_D_AWIDTH),
.C_DEPTH (P_D_DEPTH)
)
rd_data_fifo_0
(
.clk ( clk ) ,
.rst ( reset ) ,
.wr_en ( m_rvalid & m_rready ) ,
.rd_en ( rd_en ) ,
.din ( rd_data_fifo_in ) ,
.dout ( rd_data_fifo_out ) ,
.a_full ( rd_a_full ) ,
.full ( rd_full ) ,
.a_empty ( ) ,
.empty ( rd_empty )
);
assign rd_data_fifo_in = {m_rresp, m_rdata};
axi_protocol_converter_v2_1_7_b2s_simple_fifo #(
.C_WIDTH (P_WIDTH),
.C_AWIDTH (P_AWIDTH),
.C_DEPTH (P_DEPTH)
)
transaction_fifo_0
(
.clk ( clk ) ,
.rst ( reset ) ,
.wr_en ( r_push_r ) ,
.rd_en ( rd_en ) ,
.din ( trans_in ) ,
.dout ( trans_out ) ,
.a_full ( fifo_a_full ) ,
.full ( ) ,
.a_empty ( ) ,
.empty ( tr_empty )
);
assign fifo_full = fifo_a_full | rd_a_full ;
assign r_full = fifo_full ;
assign m_rready = ~rd_a_full;
endmodule
`default_nettype wire
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__A21O_BEHAVIORAL_PP_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__a21o (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21O_BEHAVIORAL_PP_V |
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module double_buffer
#(parameter BUF_SIZE = 9)
(input clk, input reset, input clear,
// Random access interface to RAM
input access_we,
input access_stb,
output access_ok,
input access_done,
input access_skip_read,
input [BUF_SIZE-1:0] access_adr,
output [BUF_SIZE-1:0] access_len,
input [35:0] access_dat_i,
output [35:0] access_dat_o,
// Write FIFO Interface
input [35:0] data_i,
input src_rdy_i,
output dst_rdy_o,
// Read FIFO Interface
output [35:0] data_o,
output src_rdy_o,
input dst_rdy_i
);
wire [35:0] data_o_0, data_o_1;
wire read, read_ok, read_ptr, read_done;
wire write, write_ok, write_ptr, write_done;
wire [BUF_SIZE-1:0] rw0_adr, rw1_adr;
reg [BUF_SIZE-1:0] read_adr, write_adr;
reg [BUF_SIZE-1:0] len0, len1;
assign data_o = read_ptr ? data_o_1 : data_o_0;
assign rw0_adr = (write_ok & ~write_ptr) ? write_adr : read_adr;
assign rw1_adr = (write_ok & write_ptr) ? write_adr : read_adr;
wire [35:0] access_dat_o_0, access_dat_o_1;
wire access_ptr;
assign access_dat_o = access_ptr? access_dat_o_1 : access_dat_o_0;
dbsm dbsm
(.clk(clk), .reset(reset), .clear(clear),
.write_ok(write_ok), .write_ptr(write_ptr), .write_done(write_done),
.access_ok(access_ok), .access_ptr(access_ptr), .access_done(access_done), .access_skip_read(access_skip_read),
.read_ok(read_ok), .read_ptr(read_ptr), .read_done(read_done));
// Port A for random access, Port B for FIFO read and write
ram_2port #(.DWIDTH(36),.AWIDTH(BUF_SIZE)) buffer0
(.clka(clk),.ena(access_stb & access_ok & (access_ptr == 0)),.wea(access_we),
.addra(access_adr),.dia(access_dat_i),.doa(access_dat_o_0),
.clkb(clk),.enb((read & read_ok & ~read_ptr)|(write & write_ok & ~write_ptr) ),.web(write&write_ok&~write_ptr),
.addrb(rw0_adr),.dib(data_i),.dob(data_o_0));
ram_2port #(.DWIDTH(36),.AWIDTH(BUF_SIZE)) buffer1
(.clka(clk),.ena(access_stb & access_ok & (access_ptr == 1)),.wea(access_we),
.addra(access_adr),.dia(access_dat_i),.doa(access_dat_o_1),
.clkb(clk),.enb((read & read_ok & read_ptr)|(write & write_ok & write_ptr) ),.web(write&write_ok&write_ptr),
.addrb(rw1_adr),.dib(data_i),.dob(data_o_1));
// Write into buffers
assign dst_rdy_o = write_ok;
assign write = src_rdy_i & write_ok;
assign write_done = write & data_i[33]; // done
always @(posedge clk)
if(reset | clear)
write_adr <= 0;
else
if(write_done)
begin
write_adr <= 0;
if(write_ptr)
len1 <= write_adr + 1;
else
len0 <= write_adr + 1;
end
else if(write)
write_adr <= write_adr + 1;
assign access_len = access_ptr ? len1 : len0;
reg [1:0] read_state;
localparam IDLE = 0;
localparam PRE_READ = 1;
localparam READING = 2;
always @(posedge clk)
if(reset | clear)
begin
read_state <= IDLE;
read_adr <= 0;
end
else
case(read_state)
IDLE :
begin
read_adr <= 0;
if(read_ok)
read_state <= PRE_READ;
end
PRE_READ :
begin
read_state <= READING;
read_adr <= 1;
end
READING :
if(dst_rdy_i)
begin
read_adr <= read_adr + 1;
if(data_o[33])
read_state <= IDLE;
end
endcase // case (read_state)
assign read = ~((read_state==READING)& ~dst_rdy_i);
assign read_done = data_o[33] & dst_rdy_i & src_rdy_o;
assign src_rdy_o = (read_state == READING);
endmodule // double_buffer
|
#include <bits/stdc++.h> using namespace std; long long n, q; const long long MXN = 200005; long long arr[MXN]; long long seg[MXN * 4]; void build(long long ind, long long l, long long r) { if (l == r) { seg[ind] = arr[l]; return; } long long m = (l + r) / 2; build(ind << 1, l, m); build((ind << 1) | 1, m + 1, r); seg[ind] = seg[ind * 2] + seg[ind * 2 + 1]; } void upd(long long ind, long long l, long long r, long long pos, long long to) { if (l == r) { seg[ind] = to; return; } long long m = (l + r) / 2; if (pos <= m) upd(ind << 1, l, m, pos, to); else upd((ind << 1) | 1, m + 1, r, pos, to); seg[ind] = seg[ind * 2] + seg[ind * 2 + 1]; } long long qry(long long ind, long long l, long long r, long long ql, long long qr) { if (ql <= l && r <= qr) { return seg[ind]; } if (ql > r || qr < l) { return 0; } long long m = (l + r) / 2; return qry(ind << 1, l, m, ql, qr) + qry((ind << 1) | 1, m + 1, r, ql, qr); } long long fact[MXN]; set<long long> rm; long long T(long long dv) { auto x = rm.begin(); for (long long j = 0; j < dv; j++) x++; return *x; } vector<long long> wh; void sep(long long kth) { for (long long i = 1; i <= n; i++) { rm.insert(i); } for (long long pl = n - 1; pl >= 0; pl--) { long long dv = kth / fact[pl]; kth %= fact[pl]; long long K = T(dv); wh.push_back(K); rm.erase(K); } for (long long i = 1; i <= n; i++) { arr[i] = wh[i - 1]; } wh.clear(); } long long SP = 0; void rew(long long kth) { if (SP == kth) return; if (n <= 15) { sep(kth); } else { for (long long i = 1; i <= 15; i++) { rm.insert(i); } for (long long pl = 15 - 1; pl >= 0; pl--) { long long dv = kth / fact[pl]; kth %= fact[pl]; long long K = T(dv); wh.push_back(K); rm.erase(K); } for (long long i = 1; i <= 15; i++) { arr[n - 15 + i] = n - 15 + wh[i - 1]; } wh.clear(); } SP = kth; } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); fact[0] = 1; cin >> n >> q; for (long long i = 1; i <= n; i++) arr[i] = i; for (long long i = 1; i <= 20; i++) { fact[i] = fact[i - 1] * i; } long long k = 0; build(1, 1, n); for (long long i = 0; i < q; i++) { long long t; cin >> t; if (t == 1) { rew(k); for (long long i = max(1ll, n - 20); i <= n; i++) { upd(1, 1, n, i, arr[i]); } long long l, r; cin >> l >> r; cout << qry(1, 1, n, l, r) << n ; } else { long long w; cin >> w; k += w; } } } |
#include <bits/stdc++.h> using namespace std; using ll = long long; using ii = pair<ll, ll>; inline int get_state(ll s, int x) { return ((s >> (5 * x)) & 0x1f); } inline ll set_state(ll s, ll v, int x) { return ((s & ~(0x1fLL << (5 * x))) | (v << (5 * x))); } int cs[10]; map<ll, int> st; map<ll, ii> ps; bool kill_all(ll s, int n, int a, int b) { for (int i = 2; i <= n - 1; ++i) if (cs[i] > b * get_state(s, i - 1) + a * get_state(s, i) + b * get_state(s, i + 1)) return false; return true; } bool all_dead(ll s, int pos, int a, int b) { for (int i = pos - 1; i <= pos + 1; ++i) { if (cs[i] > b * get_state(s, i - 1) + a * get_state(s, i) + b * get_state(s, i + 1)) return false; } return true; } int dp(ll s, int n, int a, int b) { if (s == 0) return 0; auto it = st.find(s); if (it != st.end()) { return it->second; } auto res = 1000000000; for (int i = 2; i <= n - 1; ++i) { if (get_state(s, i - 1) or get_state(s, i) or get_state(s, i + 1)) { auto r = set_state(s, max(get_state(s, i) - a, 0), i); r = set_state(r, max(get_state(r, i - 1) - b, 0), i - 1); r = set_state(r, max(get_state(r, i + 1) - b, 0), i + 1); auto value = dp(r, n, a, b) + 1; if (value < res) { res = value; ps[s] = ii(r, i); } } } st[s] = res; return res; } vector<int> solve(int n, int a, int b) { vector<int> shoots; ll s = 0; for (int i = 1; i <= n; ++i) s = set_state(s, cs[i], i); while (cs[1] > 0) { shoots.push_back(2); cs[1] -= b; cs[2] -= a; cs[3] -= b; s = set_state(s, max(get_state(s, 1) - b, 0), 1); s = set_state(s, max(get_state(s, 2) - a, 0), 2); s = set_state(s, max(get_state(s, 3) - b, 0), 3); } while (cs[n] > 0) { shoots.push_back(n - 1); cs[n] -= b; cs[n - 1] -= a; cs[n - 2] -= b; s = set_state(s, max(get_state(s, n - 2) - b, 0), n - 2); s = set_state(s, max(get_state(s, n - 1) - a, 0), n - 1); s = set_state(s, max(get_state(s, n) - b, 0), n); } dp(s, n, a, b); auto it = ps.find(s); while (it != ps.end()) { s = it->second.first; shoots.push_back(it->second.second); it = ps.find(s); } for (int i = 2; i <= n - 1; ++i) for (int j = 0; j < get_state(s, i); ++j) shoots.push_back(i); return shoots; } int main() { int n, a, b; cin >> n >> a >> b; for (int i = 1; i <= n; ++i) { cin >> cs[i]; ++cs[i]; } auto shoots = solve(n, a, b); cout << shoots.size() << endl; for (size_t i = 0; i < shoots.size(); ++i) printf( %d%c , shoots[i], n [i + 1 == shoots.size()]); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long maxn = 2e5 + 5, mod = 1e9 + 7, inf = 1e18; long long n, m, ans[maxn], h[maxn], par[20][maxn], mx[20][maxn], pw2[20], p[maxn], sz[maxn], ip[maxn]; vector<pair<long long, long long>> v1[maxn], v2[maxn]; vector<pair<long long, pair<long long, long long>>> adj[maxn], g[maxn]; vector<pair<pair<long long, long long>, pair<long long, long long>>> vec; set<pair<long long, long long>> s[maxn]; long long get_par(long long u) { if (p[u] == 0) return u; p[u] = get_par(p[u]); return p[u]; } bool merge(long long u, long long v) { u = get_par(u); v = get_par(v); if (u == v) return 0; if (sz[u] < sz[v]) swap(u, v); p[v] = u; sz[u] += sz[v]; return 1; } void dfs(long long u) { for (long long i = 1; i < 20; i++) { long long v = par[i - 1][u]; if ((v == 0) || (par[i - 1][v] == 0)) break; par[i][u] = par[i - 1][v]; mx[i][u] = max(mx[i - 1][u], mx[i - 1][v]); } for (auto j : g[u]) { long long v = j.first, w = j.second.first; if (j.first == par[0][u]) continue; ip[v] = j.second.second; mx[0][v] = w; par[0][v] = u; h[v] = h[u] + 1ll; dfs(v); } } void build_mst() { sort(vec.begin(), vec.end()); for (auto i : vec) { long long u = i.second.first, v = i.second.second, w = i.first.first; if (merge(u, v)) { g[u].push_back({v, {w, i.first.second}}); g[v].push_back({u, {w, i.first.second}}); } } dfs(1); } long long get_pr(long long v, long long d) { for (long long i = 0; i < 20; i++) { if ((pw2[i] & d) == 0) continue; v = par[i][v]; } return v; } long long get_mx(long long v, long long d) { long long MX = 0; for (long long i = 0; i < 20; i++) { if ((pw2[i] & d) == 0) continue; MX = max(MX, mx[i][v]); v = par[i][v]; } return MX; } long long get_lca(long long u, long long v) { if (h[u] > h[v]) swap(u, v); if (h[u] != h[v]) v = get_pr(v, h[v] - h[u]); if (u == v) return u; for (long long i = 19; i >= 0; i--) { if (par[i][v] == par[i][u]) continue; u = par[i][u]; v = par[i][v]; } return par[0][u]; } void DFS(long long u) { for (pair<long long, long long> i : v1[u]) s[u].insert(i); for (auto j : g[u]) { if (j.first == par[0][u]) continue; DFS(j.first); if (s[j.first].size() == 0) continue; if (s[j.first].size() > s[u].size()) s[u].swap(s[j.first]); for (auto j2 : s[j.first]) s[u].insert(j2); s[j.first].clear(); } for (pair<long long, long long> i : v2[u]) s[u].erase(i); if (u == 1) return; if (s[u].size() == 0) { ans[ip[u]] = -1; return; } ans[ip[u]] = (*s[u].begin()).first - 1ll; } int main() { ios::sync_with_stdio(false), cin.tie(0), cout.tie(0); pw2[0] = 1; for (long long i = 1; i < 20; i++) pw2[i] = (pw2[i - 1] * 2ll); cin >> n >> m; for (long long i = 0; i < m; i++) { long long u, v, w; cin >> u >> v >> w; adj[u].push_back({v, {w, i}}); adj[v].push_back({u, {w, i}}); vec.push_back({{w, i}, {u, v}}); } build_mst(); for (auto j : vec) { long long u = j.second.first, v = j.second.second, w = j.first.first, i = j.first.second; if (h[u] > h[v]) swap(u, v); if (par[0][v] == u) continue; long long lca = get_lca(u, v); v1[u].push_back({w, v}); v1[v].push_back({w, u}); v2[lca].push_back({w, v}); v2[lca].push_back({w, u}); ans[i] = max(get_mx(u, h[u] - h[lca]), get_mx(v, h[v] - h[lca])) - 1; } DFS(1); for (long long i = 0; i < m; i++) cout << ans[i] << ; } |
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (win64) Build 881834 Fri Apr 4 14:15:54 MDT 2014
// Date : Thu Jul 24 13:39:23 2014
// Host : CE-2013-124 running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub
// D:/SHS/Research/AutoEnetGway/Mine/xc702/aes_xc702/aes_xc702.srcs/sources_1/ip/fifo_generator_1/fifo_generator_1_stub.v
// Design : fifo_generator_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v12_0,Vivado 2014.1" *)
module fifo_generator_1(clk, rst, din, wr_en, rd_en, dout, full, empty)
/* synthesis syn_black_box black_box_pad_pin="clk,rst,din[93:0],wr_en,rd_en,dout[93:0],full,empty" */;
input clk;
input rst;
input [93:0]din;
input wr_en;
input rd_en;
output [93:0]dout;
output full;
output empty;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A21O_4_V
`define SKY130_FD_SC_HS__A21O_4_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog wrapper for a21o with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a21o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a21o_4 (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a21o_4 (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A21O_4_V
|
module encoder(in,out);
input [39:0] in;
output [5:0] out;
assign out = (in[0]==1'b1)?6'd0:
(in[1]==1'b1)?6'd1:
(in[2]==1'b1)?6'd2:
(in[3]==1'b1)?6'd3:
(in[4]==1'b1)?6'd4:
(in[5]==1'b1)?6'd5:
(in[6]==1'b1)?6'd6:
(in[7]==1'b1)?6'd7:
(in[8]==1'b1)?6'd8:
(in[9]==1'b1)?6'd9:
(in[10]==1'b1)?6'd10:
(in[11]==1'b1)?6'd11:
(in[12]==1'b1)?6'd12:
(in[13]==1'b1)?6'd13:
(in[14]==1'b1)?6'd14:
(in[15]==1'b1)?6'd15:
(in[16]==1'b1)?6'd16:
(in[17]==1'b1)?6'd17:
(in[18]==1'b1)?6'd18:
(in[19]==1'b1)?6'd19:
(in[20]==1'b1)?6'd20:
(in[21]==1'b1)?6'd21:
(in[22]==1'b1)?6'd22:
(in[23]==1'b1)?6'd23:
(in[24]==1'b1)?6'd24:
(in[25]==1'b1)?6'd25:
(in[26]==1'b1)?6'd26:
(in[27]==1'b1)?6'd27:
(in[28]==1'b1)?6'd28:
(in[29]==1'b1)?6'd29:
(in[30]==1'b1)?6'd30:
(in[31]==1'b1)?6'd31:
(in[32]==1'b1)?6'd32:
(in[33]==1'b1)?6'd33:
(in[34]==1'b1)?6'd34:
(in[35]==1'b1)?6'd35:
(in[36]==1'b1)?6'd36:
(in[37]==1'b1)?6'd37:
(in[38]==1'b1)?6'd38:
(in[30]==1'b1)?6'd39:
6'b000000;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int h, m, m2; char c; scanf( %d %c %d , &h, &c, &m); scanf( %d , &m2); m2 += m; int h2 = (int)(m2 / 60); h2 += h; h2 %= 24; m2 = m2 % 60; if (h2 >= 0 && h2 <= 9) printf( 0 ); printf( %d: , h2); if (m2 >= 0 && m2 <= 9) printf( 0 ); printf( %d n , m2); return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 40; const int MAXM = 210; int n, m, A[MAXN]; double p[MAXM][MAXN][MAXN]; void lucky() { scanf( %d %d , &n, &m); for (int i = 1; i <= n; i++) scanf( %d , &A[i]); } int main() { lucky(); for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) p[0][i][j] = (A[i] > A[j]); double rat = 1.0 / (0.5 * n * (n + 1)); for (int R = 1; R <= m; R++) for (int l = 1; l <= n; l++) for (int r = l; r <= n; r++) { for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) { int x = (l <= i && i <= r) ? l + r - i : i; int y = (l <= j && j <= r) ? l + r - j : j; p[R][i][j] += rat * p[R - 1][x][y]; } } double ans = 0; for (int i = 1; i <= n; i++) for (int j = i + 1; j <= n; j++) ans += p[m][i][j]; printf( %.10lf n , ans); return 0; } |
//flash interface
module flash_int(reset, clock, op, address, wdata, rdata, busy, flash_data,
flash_address, flash_ce_b, flash_oe_b, flash_we_b,
flash_reset_b, flash_sts, flash_byte_b);
parameter access_cycles = 5;
parameter reset_assert_cycles = 1000;
parameter reset_recovery_cycles = 30;
input reset, clock; // Reset and clock for the flash interface
input [1:0] op; // Flash operation select (read, write, idle)
input [22:0] address;
input [15:0] wdata;
output [15:0] rdata;
output busy;
inout [15:0] flash_data;
output [23:0] flash_address;
output flash_ce_b, flash_oe_b, flash_we_b;
output flash_reset_b, flash_byte_b;
input flash_sts;
reg [1:0] lop;
reg [15:0] rdata;
reg busy;
reg [15:0] flash_wdata;
reg flash_ddata;
reg [23:0] flash_address;
reg flash_oe_b, flash_we_b, flash_reset_b;
assign flash_ce_b = flash_oe_b && flash_we_b;
assign flash_byte_b = 1; // 1 = 16-bit mode (A0 ignored)
assign flash_data = flash_ddata ? flash_wdata : 16'hZ;
initial
flash_reset_b <= 1'b1;
reg [9:0] state;
always @(posedge clock)
if (reset)
begin
state <= 0;
flash_reset_b <= 0;
flash_we_b <= 1;
flash_oe_b <= 1;
flash_ddata <= 0;
busy <= 1;
end
else if (flash_reset_b == 0)
if (state == reset_assert_cycles)
begin
flash_reset_b <= 1;
state <= 1023-reset_recovery_cycles;
end
else
state <= state+1;
else if ((state == 0) && !busy)
// The flash chip and this state machine are both idle. Latch the user's
// address and write data inputs. Deassert OE and WE, and stop driving
// the data buss ourselves. If a flash operation (read or write) is
// requested, move to the next state.
begin
flash_address <= {address, 1'b0};
flash_we_b <= 1;
flash_oe_b <= 1;
flash_ddata <= 0;
flash_wdata <= wdata;
lop <= op;
if (op != `FLASHOP_IDLE)
begin
busy <= 1;
state <= state+1;
end
else
busy <= 0;
end
else if ((state==0) && flash_sts)
busy <= 0;
else if (state == 1)
// The first stage of a flash operation. The address bus is already set,
// so, if this is a read, we assert OE. For a write, we start driving
// the user's data onto the flash databus (the value was latched in the
// previous state.
begin
if (lop == `FLASHOP_WRITE)
flash_ddata <= 1;
else if (lop == `FLASHOP_READ)
flash_oe_b <= 0;
state <= state+1;
end
else if (state == 2)
// The second stage of a flash operation. Nothing to do for a read. For
// a write, we assert WE.
begin
if (lop == `FLASHOP_WRITE)
flash_we_b <= 0;
state <= state+1;
end
else if (state == access_cycles+1)
// The third stage of a flash operation. For a read, we latch the data
// from the flash chip. For a write, we deassert WE.
begin
if (lop == `FLASHOP_WRITE)
flash_we_b <= 1;
if (lop == `FLASHOP_READ)
rdata <= flash_data;
state <= 0;
end
else
begin
if (!flash_sts)
busy <= 1;
state <= state+1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; string removeZero(string s) { int i = 0, m = 0, j = s.size() - 1; if (s[i] == 0 ) { while (s[i] == 0 ) { i++; } } s.erase(0, i); if (s[j] == 0 ) { while (s[j] == 0 ) { m++; j--; } } s.erase(j + 1, s.size() - j); return s; } int main() { string s; cin >> s; s = removeZero(s); int x = 0, o = s.size() - 1, flag = 0; while (x <= s.size() - 1) { if (s[x] != s[o]) { flag = 1; cout << NO ; break; } x++; o--; } if (flag == 0) cout << YES ; return 0; } |
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* 10G Ethernet MAC/PHY combination
*/
module eth_mac_phy_10g #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter HDR_WIDTH = (DATA_WIDTH/32),
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter PTP_PERIOD_NS = 4'h6,
parameter PTP_PERIOD_FNS = 16'h6666,
parameter TX_PTP_TS_ENABLE = 0,
parameter TX_PTP_TS_WIDTH = 96,
parameter TX_PTP_TAG_ENABLE = TX_PTP_TS_ENABLE,
parameter TX_PTP_TAG_WIDTH = 16,
parameter RX_PTP_TS_ENABLE = 0,
parameter RX_PTP_TS_WIDTH = 96,
parameter TX_USER_WIDTH = (TX_PTP_TAG_ENABLE ? TX_PTP_TAG_WIDTH : 0) + 1,
parameter RX_USER_WIDTH = (RX_PTP_TS_ENABLE ? RX_PTP_TS_WIDTH : 0) + 1,
parameter BIT_REVERSE = 0,
parameter SCRAMBLER_DISABLE = 0,
parameter PRBS31_ENABLE = 0,
parameter TX_SERDES_PIPELINE = 0,
parameter RX_SERDES_PIPELINE = 0,
parameter BITSLIP_HIGH_CYCLES = 1,
parameter BITSLIP_LOW_CYCLES = 8,
parameter COUNT_125US = 125000/6.4
)
(
input wire rx_clk,
input wire rx_rst,
input wire tx_clk,
input wire tx_rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] tx_axis_tdata,
input wire [KEEP_WIDTH-1:0] tx_axis_tkeep,
input wire tx_axis_tvalid,
output wire tx_axis_tready,
input wire tx_axis_tlast,
input wire [TX_USER_WIDTH-1:0] tx_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] rx_axis_tdata,
output wire [KEEP_WIDTH-1:0] rx_axis_tkeep,
output wire rx_axis_tvalid,
output wire rx_axis_tlast,
output wire [RX_USER_WIDTH-1:0] rx_axis_tuser,
/*
* SERDES interface
*/
output wire [DATA_WIDTH-1:0] serdes_tx_data,
output wire [HDR_WIDTH-1:0] serdes_tx_hdr,
input wire [DATA_WIDTH-1:0] serdes_rx_data,
input wire [HDR_WIDTH-1:0] serdes_rx_hdr,
output wire serdes_rx_bitslip,
/*
* PTP
*/
input wire [TX_PTP_TS_WIDTH-1:0] tx_ptp_ts,
input wire [RX_PTP_TS_WIDTH-1:0] rx_ptp_ts,
output wire [TX_PTP_TS_WIDTH-1:0] tx_axis_ptp_ts,
output wire [TX_PTP_TAG_WIDTH-1:0] tx_axis_ptp_ts_tag,
output wire tx_axis_ptp_ts_valid,
/*
* Status
*/
output wire [1:0] tx_start_packet,
output wire tx_error_underflow,
output wire [1:0] rx_start_packet,
output wire [6:0] rx_error_count,
output wire rx_error_bad_frame,
output wire rx_error_bad_fcs,
output wire rx_bad_block,
output wire rx_block_lock,
output wire rx_high_ber,
/*
* Configuration
*/
input wire [7:0] ifg_delay,
input wire tx_prbs31_enable,
input wire rx_prbs31_enable
);
eth_mac_phy_10g_rx #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_TS_ENABLE(RX_PTP_TS_ENABLE),
.PTP_TS_WIDTH(RX_PTP_TS_WIDTH),
.USER_WIDTH(RX_USER_WIDTH),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_ENABLE(PRBS31_ENABLE),
.SERDES_PIPELINE(RX_SERDES_PIPELINE),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US)
)
eth_mac_phy_10g_rx_inst (
.clk(rx_clk),
.rst(rx_rst),
.m_axis_tdata(rx_axis_tdata),
.m_axis_tkeep(rx_axis_tkeep),
.m_axis_tvalid(rx_axis_tvalid),
.m_axis_tlast(rx_axis_tlast),
.m_axis_tuser(rx_axis_tuser),
.serdes_rx_data(serdes_rx_data),
.serdes_rx_hdr(serdes_rx_hdr),
.serdes_rx_bitslip(serdes_rx_bitslip),
.ptp_ts(rx_ptp_ts),
.rx_start_packet(rx_start_packet),
.rx_error_count(rx_error_count),
.rx_error_bad_frame(rx_error_bad_frame),
.rx_error_bad_fcs(rx_error_bad_fcs),
.rx_bad_block(rx_bad_block),
.rx_block_lock(rx_block_lock),
.rx_high_ber(rx_high_ber),
.rx_prbs31_enable(rx_prbs31_enable)
);
eth_mac_phy_10g_tx #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_TS_ENABLE(TX_PTP_TS_ENABLE),
.PTP_TS_WIDTH(TX_PTP_TS_WIDTH),
.PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE),
.PTP_TAG_WIDTH(TX_PTP_TAG_WIDTH),
.USER_WIDTH(TX_USER_WIDTH),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_ENABLE(PRBS31_ENABLE),
.SERDES_PIPELINE(TX_SERDES_PIPELINE)
)
eth_mac_phy_10g_tx_inst (
.clk(tx_clk),
.rst(tx_rst),
.s_axis_tdata(tx_axis_tdata),
.s_axis_tkeep(tx_axis_tkeep),
.s_axis_tvalid(tx_axis_tvalid),
.s_axis_tready(tx_axis_tready),
.s_axis_tlast(tx_axis_tlast),
.s_axis_tuser(tx_axis_tuser),
.serdes_tx_data(serdes_tx_data),
.serdes_tx_hdr(serdes_tx_hdr),
.ptp_ts(tx_ptp_ts),
.m_axis_ptp_ts(tx_axis_ptp_ts),
.m_axis_ptp_ts_tag(tx_axis_ptp_ts_tag),
.m_axis_ptp_ts_valid(tx_axis_ptp_ts_valid),
.tx_start_packet(tx_start_packet),
.tx_error_underflow(tx_error_underflow),
.ifg_delay(ifg_delay),
.tx_prbs31_enable(tx_prbs31_enable)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; void solve() { int n, m; cin >> n >> m; vector<pair<int, int> > v; v.resize(n * m); for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { v[m * (i - 1) + j - 1] = {i, j}; } } bool low = true; int l = 0, r = m * n - 1; while (r >= l) { pair<int, int> u; if (low) { u = v[l]; l++; low = false; } else { u = v[r]; r--; low = true; } cout << u.first << << u.second << n ; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t = 1; for (int i = 0; i < t; ++i) { solve(); } } |
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