text
stringlengths 59
71.4k
|
|---|
#include <bits/stdc++.h> using namespace std; const int N = 5010; const int MOD = 1000000007; int n, x[N], y[N], w[N][N], vis[N]; inline void dfs(int v, int val) { for (int u = 0; u < n; u++) { if (w[v][u] > val) { if (vis[u] == vis[v]) throw 0; if (vis[u] != -1) continue; vis[u] = !vis[v]; dfs(u, val); } } } inline int check(int val) { memset(vis, -1, sizeof vis); int ans = 1; for (int i = 0; i < n; i++) if (vis[i] == -1) { try { vis[i] = 0; dfs(i, val); } catch (...) { return 0; } ans += ans; if (ans >= MOD) ans -= MOD; } return ans; } int main() { scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d%d , x + i, y + i); for (int i = 0; i < n; i++) for (int j = i + 1; j < n; j++) w[i][j] = w[j][i] = abs(x[i] - x[j]) + abs(y[i] - y[j]); int lo = 0, hi = 10050, mid; while (lo < hi) { mid = lo + hi >> 1; if (check(mid)) hi = mid; else lo = mid + 1; } cout << hi << n << check(hi) << n ; return 0; } |
//
// Copyright (c) 1999 Stephan Boettcher ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - PR 204 report - validates correct use of blank ports.
module none;
reg x;
endmodule // none
module empty();
reg x;
endmodule // none
module one (a);
input a;
reg x;
endmodule // one
module two (a, b);
input a, b;
reg x;
endmodule // two
module three (a, b, c);
input a, b, c;
reg x;
endmodule // two
module main;
wire w1, w2, w3, w4, w5, w6, w7, w8, w9;
none U1 ();
empty U2 ();
one U3 ();
one U4 (w1);
one U5 (.a(w2));
two U6 ();
two U7 (,);
two U8 (w3,);
two U9 (,w4);
two Ua (w5,w6);
two Ub (.a(w7));
two Uc (.b(w8));
two Ud (.b(w8),.a(w9));
three Ue ();
//three Uf (,); //XXXX I doubt this is legal... ?
three Ug (,,);
initial $display("PASSED");
endmodule // main
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [63:0] crc;
reg [63:0] sum;
wire r1_en /*verilator public*/ = crc[12];
wire [1:0] r1_ad /*verilator public*/ = crc[9:8];
wire r2_en /*verilator public*/ = 1'b1;
wire [1:0] r2_ad /*verilator public*/ = crc[11:10];
wire w1_en /*verilator public*/ = crc[5];
wire [1:0] w1_a /*verilator public*/ = crc[1:0];
wire [63:0] w1_d /*verilator public*/ = {2{crc[63:32]}};
wire w2_en /*verilator public*/ = crc[4];
wire [1:0] w2_a /*verilator public*/ = crc[3:2];
wire [63:0] w2_d /*verilator public*/ = {2{~crc[63:32]}};
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [63:0] r1_d_d2r; // From file of file.v
wire [63:0] r2_d_d2r; // From file of file.v
// End of automatics
file file (/*AUTOINST*/
// Outputs
.r1_d_d2r (r1_d_d2r[63:0]),
.r2_d_d2r (r2_d_d2r[63:0]),
// Inputs
.clk (clk),
.r1_en (r1_en),
.r1_ad (r1_ad[1:0]),
.r2_en (r2_en),
.r2_ad (r2_ad[1:0]),
.w1_en (w1_en),
.w1_a (w1_a[1:0]),
.w1_d (w1_d[63:0]),
.w2_en (w2_en),
.w2_a (w2_a[1:0]),
.w2_d (w2_d[63:0]));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d EN=%b%b%b%b R0=%x R1=%x\n",$time, cyc, r1_en,r2_en,w1_en,w2_en, r1_d_d2r, r2_d_d2r);
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= {r1_d_d2r ^ r2_d_d2r} ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
// We've manually verified all X's are out of the design by this point
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$write("[%0t] cyc==%0d crc=%x %x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== 64'h5e9ea8c33a97f81e) $stop;
$finish;
end
end
endmodule
module file (/*AUTOARG*/
// Outputs
r1_d_d2r, r2_d_d2r,
// Inputs
clk, r1_en, r1_ad, r2_en, r2_ad, w1_en, w1_a, w1_d, w2_en, w2_a, w2_d
);
input clk;
input r1_en;
input [1:0] r1_ad;
output [63:0] r1_d_d2r;
input r2_en;
input [1:0] r2_ad;
output [63:0] r2_d_d2r;
input w1_en;
input [1:0] w1_a;
input [63:0] w1_d;
input w2_en;
input [1:0] w2_a;
input [63:0] w2_d;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
// End of automatics
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [63:0] r1_d_d2r;
reg [63:0] r2_d_d2r;
// End of automatics
// Writes
wire [3:0] m_w1_onehotwe = ({4{w1_en}} & (4'b1 << w1_a));
wire [3:0] m_w2_onehotwe = ({4{w2_en}} & (4'b1 << w2_a));
wire [63:0] rg0_wrdat = m_w1_onehotwe[0] ? w1_d : w2_d;
wire [63:0] rg1_wrdat = m_w1_onehotwe[1] ? w1_d : w2_d;
wire [63:0] rg2_wrdat = m_w1_onehotwe[2] ? w1_d : w2_d;
wire [63:0] rg3_wrdat = m_w1_onehotwe[3] ? w1_d : w2_d;
wire [3:0] m_w_onehotwe = m_w1_onehotwe | m_w2_onehotwe;
// Storage
reg [63:0] m_rg0_r;
reg [63:0] m_rg1_r;
reg [63:0] m_rg2_r;
reg [63:0] m_rg3_r;
always @ (posedge clk) begin
if (m_w_onehotwe[0]) m_rg0_r <= rg0_wrdat;
if (m_w_onehotwe[1]) m_rg1_r <= rg1_wrdat;
if (m_w_onehotwe[2]) m_rg2_r <= rg2_wrdat;
if (m_w_onehotwe[3]) m_rg3_r <= rg3_wrdat;
end
// Reads
reg [1:0] m_r1_ad_d1r;
reg [1:0] m_r2_ad_d1r;
reg [1:0] m_ren_d1r;
always @ (posedge clk) begin
if (r1_en) m_r1_ad_d1r <= r1_ad;
if (r2_en) m_r2_ad_d1r <= r2_ad;
m_ren_d1r <= {r2_en, r1_en};
end
// Scheme1: shift...
wire [3:0] m_r1_onehot_d1 = (4'b1 << m_r1_ad_d1r);
// Scheme2: bit mask
reg [3:0] m_r2_onehot_d1;
always @* begin
m_r2_onehot_d1 = 4'd0;
m_r2_onehot_d1[m_r2_ad_d1r] = 1'b1;
end
wire [63:0] m_r1_d_d1 = (({64{m_r1_onehot_d1[0]}} & m_rg0_r) |
({64{m_r1_onehot_d1[1]}} & m_rg1_r) |
({64{m_r1_onehot_d1[2]}} & m_rg2_r) |
({64{m_r1_onehot_d1[3]}} & m_rg3_r));
wire [63:0] m_r2_d_d1 = (({64{m_r2_onehot_d1[0]}} & m_rg0_r) |
({64{m_r2_onehot_d1[1]}} & m_rg1_r) |
({64{m_r2_onehot_d1[2]}} & m_rg2_r) |
({64{m_r2_onehot_d1[3]}} & m_rg3_r));
always @ (posedge clk) begin
if (m_ren_d1r[0]) r1_d_d2r <= m_r1_d_d1;
if (m_ren_d1r[1]) r2_d_d2r <= m_r2_d_d1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; mt19937 rnd(chrono::high_resolution_clock::now().time_since_epoch().count()); const int N = (int)(5e5) + 7; int cnt[N]; int last[N]; int slast[N]; int pcnt[N]; long long psum[N]; int main() { ios::sync_with_stdio(0); cin.tie(0); int n; cin >> n; for (int i = 0; i < n; i++) { int x; cin >> x; cnt[x]++; pcnt[x]++; psum[x] += x; } for (int i = 0; i < N; i++) { if (i) pcnt[i] += pcnt[i - 1]; if (i) psum[i] += psum[i - 1]; } int mda = -1; int tmda = -1; for (int i = 0; i < N; i++) { if (cnt[i]) { tmda = mda; mda = i; } if (cnt[i] >= 2) { tmda = i; } last[i] = mda; slast[i] = tmda; } auto as = [&](int x, int y) { long long value = (long long)(1e18) + 7; for (int i = 0; i < N; i += y) { int l = i, r = min(N - 1, i + y - 1); if (last[r] >= x) { value = min(value, (long long)(last[r] / y - (last[r] - x) / y)); } } return value; }; auto ans_two = [&](int x, int y) { long long best_a = (long long)(1e18) + 7; long long best_b = (long long)(1e18) + 7; for (int i = 0; i < N; i += y) { int l = i, r = min(N - 1, i + y - 1); if (last[r] >= l && last[r] >= x) { long long value = last[r] / y - (last[r] - x) / y; if (value < best_a) { swap(value, best_a); } if (value < best_b) { swap(value, best_b); } } if (slast[r] >= l && slast[r] >= x) { long long value = slast[r] / y - (slast[r] - x) / y; if (value < best_a) { swap(value, best_a); } if (value < best_b) { swap(value, best_b); } } } return best_a + best_b; }; auto check = [&](long long x, int y, long long s) { if (x >= N) { return false; } if (s - as(2 * x, y) >= x) { return true; } if (s - ans_two(x, y) >= x) { return true; } return false; }; long long ans = 4; vector<int> ord_y; for (int y = 2; y < N; y++) { ord_y.push_back(y); } shuffle(ord_y.begin(), ord_y.end(), rnd); auto seg_sum = [&](int l, int r) { return psum[r] - (l ? psum[l - 1] : 0); }; auto seg_cnt = [&](int l, int r) { return pcnt[r] - (l ? pcnt[l - 1] : 0); }; auto get_sum = [&](int y) { long long sum = 0; for (int i = 0; i < N; i += y) { int l = i, r = min(N - 1, i + y - 1); sum += seg_cnt(l, r) * (long long)(i / y); } return sum; }; for (int y : ord_y) { long long s = get_sum(y); long long vl = max(2ll, ans / y + 1); if (check(vl, y, s)) { int vr = N; while (vl < vr - 1) { int vm = (vl + vr) / 2; if (check(vm, y, s)) { vl = vm; } else { vr = vm; } } ans = vl * (long long)y; } } cout << ans << n ; } |
`include "hrfp_defs.vh"
module hrfp_add
#(parameter PIPELINESTAGES=5)
(input wire clk,
input wire [`MSBBIT:0] op3_a, op3_b,
input wire [30:0] mantissa_3_align0, mantissa_3_align1,
input wire expdiff_msb_3,
output reg [`MSBBIT:0] result_4,
output reg [30:0] mantissa_4,
output reg [7:0] zeroesmask_4);
reg [`MSBBIT:0] result_4_comb;
reg [30:0] mantissa_4_comb;
reg [7:0] zeroesmask_4_comb;
reg [30:0] aligned_mantissa;
always @* begin
if(expdiff_msb_3) begin
aligned_mantissa <= mantissa_3_align1;
end else begin
aligned_mantissa <= mantissa_3_align0;
end
end
always @* begin
result_4_comb = op3_a; // Exponent and sign
if(op3_b`SIGN == op3_a`SIGN) begin
mantissa_4_comb = ({op3_a`MANTISSA,3'b0} + aligned_mantissa);
end else begin
mantissa_4_comb = ({op3_a`MANTISSA,3'b0} - aligned_mantissa);
end
zeroesmask_4_comb = 8'hff;
end
generate
if (PIPELINESTAGES==5) begin : ADDREG
always @(posedge clk) begin
result_4 <= result_4_comb;
mantissa_4 <= mantissa_4_comb;
zeroesmask_4 <= zeroesmask_4_comb;
end
end else begin // FIXME - check number of pipeline stages!
always @* begin
result_4 <= result_4_comb;
mantissa_4 <= mantissa_4_comb;
zeroesmask_4 <= zeroesmask_4_comb;
end // else: !if(PIPELINESTAGES==5)
end // else: !if(PIPELINESTAGES==5)
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD1_FUNCTIONAL_V
`define SKY130_FD_SC_LS__CLKDLYINV3SD1_FUNCTIONAL_V
/**
* clkdlyinv3sd1: Clock Delay Inverter 3-stage 0.15um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__clkdlyinv3sd1 (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV3SD1_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; struct point { int x, y; point() : x(0), y(0) {} point(int x, int y) : x(x), y(y) {} point operator-(const point& p) const { return point(x - p.x, y - p.y); } int dot(const point& p) const { return x * p.x + y * p.y; } int cross(const point& p) const { return x * p.y - y * p.x; } }; istream& operator>>(istream& is, point& p) { return is >> p.x >> p.y; } bool pointInSegment(const point& a, const point& b, const point& p) { return (p - a).cross(b - a) == 0 && (a - p).dot(b - p) <= 0; } bool pointInPerimeter(const vector<point>& P, const point& p) { int n = P.size(); for (int i = 0; i < n; i++) { if (pointInSegment(P[i], P[(i + 1) % n], p)) { return true; } } return false; } bool crossesRay(const point& a, const point& b, const point& p) { return ((b.y >= p.y) - (a.y >= p.y)) * (a - p).cross(b - p) >= 0; } bool pointInPolygon(const vector<point>& P, const point& p) { if (pointInPerimeter(P, p)) { return true; } int n = P.size(); int rays = 0; for (int i = 0; i < n; i++) { rays += crossesRay(P[i], P[(i + 1) % n], p); } return rays & 1; } int sgn(int x) { if (x > 0) return 1; if (x < 0) return -1; return 0; } int intersectSegmentsInfo(const point& a, const point& b, const point& c, const point& d) { point v1 = b - a, v2 = d - c; int t = sgn(v1.cross(c - a)), u = sgn(v1.cross(d - a)); if (t == u) { if (t == 0) { if (pointInSegment(a, b, c) || pointInSegment(a, b, d) || pointInSegment(c, d, a) || pointInSegment(c, d, b)) { return -1; } else { return 0; } } else { return 0; } } else { return sgn(v2.cross(a - c)) != sgn(v2.cross(b - c)); } } int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); vector<point> a(4), b(4); for (point& p : a) cin >> p; for (point& p : b) cin >> p; bool ans = false; for (const point& p : a) { ans = ans | pointInPolygon(b, p); } for (const point& p : b) { ans = ans | pointInPolygon(a, p); } for (int i = 0; i < 4; ++i) { for (int j = 0; j < 4; ++j) { ans = ans | (intersectSegmentsInfo(a[i], a[(i + 1) % 4], b[j], b[(j + 1) % 4]) != 0); } } cout << (ans ? YES : NO ) << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAX = 200200; vector<int> adj[MAX]; int ch[MAX], sz, from[MAX], dpthMx[MAX], dpthMn[MAX], n; void dfs(int cur, int par) { for (auto i : adj[cur]) if (i != par) { dfs(i, cur); dpthMn[cur] = min(dpthMn[cur], dpthMn[i] + 1); dpthMx[cur] = max(dpthMx[cur], dpthMx[i] + 1); } if (dpthMn[cur] == MAX) dpthMn[cur] = 0; } pair<int, int> dfs0(int cur, int par, int d) { from[cur] = par; pair<int, int> ret(d, cur); for (auto i : adj[cur]) if (i != par) ret = max(ret, dfs0(i, cur, d + 1)); return ret; } int main() { scanf( %d , &n); fill(dpthMn, dpthMn + n + 1, MAX); for (int i = 1, u, v; i < n; ++i) { scanf( %d%d , &u, &v); adj[u].push_back(v); adj[v].push_back(u); } pair<int, int> diam = dfs0(dfs0(1, 0, 0).second, 0, 0); while (diam.first > 0) diam.first -= 2, diam.second = from[diam.second]; dfs(diam.second, 0); for (auto i : adj[diam.second]) { if (dpthMx[i] != dpthMn[i]) return puts( -1 ), 0; ch[sz++] = dpthMx[i] + 1; } sort(ch, ch + sz); sz = unique(ch, ch + sz) - ch; if (sz > 2) return puts( -1 ), 0; ch[sz] = 0; int ans = ch[0] + ch[1]; while (!(ans & 1)) ans >>= 1; printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; struct node { long long c, f, l; }; bool operator<(node a, node b) { return a.f < b.f; } long long n, dx, fx, bn, tot, i, tf, fn, first, xn, sum, xx; node a[100004], b[100004]; bool can; int main() { cin >> n >> dx >> fx; bn = -1; tot = 0; for (i = 0; i < n; i++) { cin >> a[i].c >> a[i].f >> a[i].l; tot += a[i].c; if (a[i].l >= dx) { bn++; b[bn] = a[i]; } } bn++; sort(b, b + bn); can = false; tf = 0; fn = 0; first = -1; for (i = 0; i < bn; i++) { if (tf + b[i].f <= fx) { tf += b[i].f; if (b[i].c != 0 && first == -1) { first = i; can = true; } fn++; } } if (can == false) { first = -1; for (i = 0; i < bn; i++) { if (b[i].c != 0) { first = i; break; } } if (first != -1) { if (b[first].f <= fx) { tf = b[first].f; xx = 0; for (i = 0; i < bn; i++) { if (tf + b[i].f > fx) break; tf += b[i].f; xx++; } if (tot + xx + 1 > fn) { can = true; fn = xx + 1; } } } } if (can == true) { if (tot + fn > n) { cout << n << ; xn = n - tot; if (xn - 1 < first) { sum = 0; for (i = 0; i <= xn - 2; i++) sum += b[i].f; sum += b[first].f; } else { sum = 0; for (i = 0; i < xn; i++) sum += b[i].f; } cout << sum << endl; } else { cout << tot + fn << ; if (fn - 1 < first) { sum = 0; for (i = 0; i < fn - 1; i++) sum += b[i].f; sum += b[first].f; } else { sum = 0; for (i = 0; i < fn; i++) sum += b[i].f; } cout << sum << endl; } } else { cout << fn << ; sum = 0; for (i = 0; i < fn; i++) sum += b[i].f; cout << sum << endl; } return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( O2,unroll-loops ) using namespace std; const int mod = 1000000007, N = 17; int n, x, ans; int A[1 << N], B[N + 1][1 << N], C[N + 1][1 << N], D[1 << N], E[1 << N]; long long fib[1 << N]; inline void fix(int& x) { if (x >= mod) x -= mod; if (x < 0) x += mod; } void SOS1(int* A, int inv) { for (int j = 0; j < N; j++) for (int mask = 0; mask < (1 << N); mask++) if (mask & (1 << j)) fix(A[mask] += inv * A[mask ^ (1 << j)]); } void SOS2(int* A, int inv) { for (int j = 0; j < N; j++) for (int mask = 0; mask < (1 << N); mask++) if (mask & (1 << j)) fix(A[mask ^ (1 << j)] += inv * A[mask]); } void XOR(int* A, bool inv) { for (int j = 0; j < N; j++) for (int mask = 0; mask < (1 << N); mask++) if (mask & (1 << j)) { int a = A[mask ^ (1 << j)], b = A[mask]; fix(A[mask ^ (1 << j)] = a + b); fix(A[mask] = a - b); } if (inv) { long long tmp = 1, inv2 = (mod + 1) / 2; for (int i = 0; i < N; i++) tmp = tmp * inv2 % mod; for (int mask = 0; mask < (1 << N); mask++) A[mask] = A[mask] * tmp % mod; } } int main() { fib[1] = 1; for (int i = 2; i < (1 << N); i++) fib[i] = (fib[i - 1] + fib[i - 2]) % mod; scanf( %d , &n); while (n--) scanf( %d , &x), A[x]++; for (int i = 0; i <= N; i++) { for (int mask = 0; mask < (1 << N); mask++) if (__builtin_popcount(mask) == i) B[i][mask] = A[mask]; SOS1(B[i], +1); } for (int i = 0; i <= N; i++) for (int j = 0; i + j <= N; j++) { for (int mask = 0; mask < (1 << N); mask++) C[i + j][mask] = (C[i + j][mask] + 1ll * B[i][mask] * B[j][mask]) % mod; } for (int i = 0; i <= N; i++) SOS1(C[i], -1); for (int mask = 0; mask < (1 << N); mask++) D[mask] = C[__builtin_popcount(mask)][mask] * fib[mask] % mod; for (int mask = 0; mask < (1 << N); mask++) { E[mask] = A[mask]; A[mask] = A[mask] * fib[mask] % mod; } XOR(E, 0); for (int mask = 0; mask < (1 << N); mask++) E[mask] = 1ll * E[mask] * E[mask] % mod; XOR(E, 1); for (int mask = 0; mask < (1 << N); mask++) E[mask] = E[mask] * fib[mask] % mod; SOS2(A, +1); SOS2(D, +1); SOS2(E, +1); for (int mask = 0; mask < (1 << N); mask++) A[mask] = 1ll * A[mask] * D[mask] % mod * E[mask] % mod; SOS2(A, -1); for (int i = 0; i < N; i++) fix(ans += A[1 << i]); if (ans < 0) ans += mod; printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long int N = 100005; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); { long long int i, j, k, n, m, ans = 0, cnt = 0, sum = 0; cin >> n; vector<long long int> v; cout << n << ; i = n - 1; while (i > 0) { if (n % i == 0) { cout << i << ; n = i; i = n - 1; } else { i--; } } } } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m, a, b; cin >> n >> m; if (m == n) { vector<bool> rev(n, false); vector<vector<int> > mat(n + 1); for (int i = 0; i < m; i++) { cin >> a >> b; mat[a].push_back(b); mat[b].push_back(a); } int cont = 0; for (int i = 1; i <= m; i++) { if (!rev[i]) { cont++; queue<int> COLA; COLA.push(i); rev[i] = true; while (!COLA.empty()) { int j = COLA.front(); COLA.pop(); for (int k = 0; k < mat[j].size(); k++) { if (!rev[mat[j][k]]) { rev[mat[j][k]] = 1; COLA.push(mat[j][k]); } } } } } if (cont == 1) cout << FHTAGN! n ; else cout << NO n ; } else cout << NO n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MOD = (int)1e9 + 7; const int INF = (int)1e9; const long long LINF = (long long)1e18; const long double PI = acos((long double)-1); const long double EPS = 1e-9; inline long long gcd(long long a, long long b) { long long r; while (b) { r = a % b; a = b; b = r; } return a; } inline long long lcm(long long a, long long b) { return a / gcd(a, b) * b; } inline long long fpow(long long n, long long k, int p = MOD) { long long r = 1; for (; k; k >>= 1) { if (k & 1) r = r * n % p; n = n * n % p; } return r; } template <class T> inline int chkmin(T& a, const T& val) { return val < a ? a = val, 1 : 0; } template <class T> inline int chkmax(T& a, const T& val) { return a < val ? a = val, 1 : 0; } template <class T> inline T isqrt(T k) { T r = sqrt(k) + 1; while (r * r > k) r--; return r; } template <class T> inline T icbrt(T k) { T r = cbrt(k) + 1; while (r * r * r > k) r--; return r; } inline void addmod(int& a, int val, int p = MOD) { if ((a = (a + val)) >= p) a -= p; } inline void submod(int& a, int val, int p = MOD) { if ((a = (a - val)) < 0) a += p; } inline int mult(int a, int b, int p = MOD) { return (long long)a * b % p; } inline int inv(int a, int p = MOD) { return fpow(a, p - 2, p); } void solve() { long long r, h; cin >> r >> h; long double rr = r, hh = h; long long ans = 0; if (2 * h >= r) { long long tmp = (long long)floor((hh - rr / 2) / rr + EPS) + 1; long double z = hh - rr / 2 - tmp * rr; chkmax(ans, 2 * tmp); if (z >= rr * (sqrt(3) / 2 - 0.5) - EPS) { chkmax(ans, 2 * tmp + 1); } } hh += rr * (1 - sqrt(3) / 2); long long tmp = (long long)floor(hh / rr + EPS); long double z = hh - tmp * rr; chkmax(ans, 2 * tmp + 1); cout << ans << n ; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); solve(); return 0; } |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2016 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2017.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / D Flip-Flop with Clock Enable and Asynchronous Clear
// /___/ /\ Filename : FDCE.v
// \ \ / \
// \___\/\___\
//
// Revision:
// 08/24/10 - Initial version.
// 10/20/10 - remove unused pin line from table.
// 11/01/11 - Disable timing check when set reset active (CR632017)
// 12/08/11 - add MSGON and XON attributes (CR636891)
// 01/16/12 - 640813 - add MSGON and XON functionality
// 04/16/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module FDCE #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
parameter MSGON = "TRUE",
parameter XON = "TRUE",
`endif
parameter [0:0] INIT = 1'b0,
parameter [0:0] IS_CLR_INVERTED = 1'b0,
parameter [0:0] IS_C_INVERTED = 1'b0,
parameter [0:0] IS_D_INVERTED = 1'b0
)(
output Q,
input C,
input CE,
input CLR,
input D
);
reg [0:0] IS_CLR_INVERTED_REG = IS_CLR_INVERTED;
reg [0:0] IS_C_INVERTED_REG = IS_C_INVERTED;
reg [0:0] IS_D_INVERTED_REG = IS_D_INVERTED;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING
wire D_dly, C_dly, CE_dly;
wire CLR_dly;
`endif
wire CLR_in;
`ifdef XIL_TIMING
assign CLR_in = (CLR_dly ^ IS_CLR_INVERTED_REG) && (CLR !== 1'bz);
`else
assign CLR_in = (CLR ^ IS_CLR_INVERTED_REG) && (CLR !== 1'bz);
`endif
// begin behavioral model
reg Q_out;
assign #100 Q = Q_out;
always @(glblGSR or CLR_in)
if (glblGSR)
assign Q_out = INIT;
else if (CLR_in === 1'b1)
assign Q_out = 1'b0;
else if (CLR_in === 1'bx)
assign Q_out = 1'bx;
else
deassign Q_out;
`ifdef XIL_TIMING
generate
if (IS_C_INVERTED == 1'b0) begin : generate_block1
always @(posedge C_dly or posedge CLR_in)
if (CLR_in || (CLR === 1'bx && Q_out == 1'b0))
Q_out <= 1'b0;
else if (CE_dly || (CE === 1'bz) || ((CE === 1'bx) && (Q_out == (D_dly ^ IS_D_INVERTED_REG))))
Q_out <= D_dly ^ IS_D_INVERTED_REG;
end else begin : generate_block1
always @(negedge C_dly or posedge CLR_in)
if (CLR_in || (CLR === 1'bx && Q_out == 1'b0))
Q_out <= 1'b0;
else if (CE_dly || (CE === 1'bz) || ((CE === 1'bx) && (Q_out == (D_dly ^ IS_D_INVERTED_REG))))
Q_out <= D_dly ^ IS_D_INVERTED_REG;
end
endgenerate
`else
generate
if (IS_C_INVERTED == 1'b0) begin : generate_block1
always @(posedge C or posedge CLR_in)
if (CLR_in || (CLR === 1'bx && Q_out == 1'b0))
Q_out <= 1'b0;
else if (CE || (CE === 1'bz) || ((CE === 1'bx) && (Q_out == (D ^ IS_D_INVERTED_REG))))
Q_out <= D ^ IS_D_INVERTED_REG;
end else begin : generate_block1
always @(negedge C or posedge CLR_in)
if (CLR_in || (CLR === 1'bx && Q_out == 1'b0))
Q_out <= 1'b0;
else if (CE || (CE === 1'bz) || ((CE === 1'bx) && (Q_out == (D ^ IS_D_INVERTED_REG))))
Q_out <= D ^ IS_D_INVERTED_REG;
end
endgenerate
`endif
`ifdef XIL_TIMING
reg notifier;
wire notifier1;
`endif
`ifdef XIL_TIMING
wire ngsr, in_out;
wire nrst;
wire in_clk_enable, in_clk_enable_p, in_clk_enable_n;
wire ce_clk_enable, ce_clk_enable_p, ce_clk_enable_n;
reg init_enable = 1'b1;
wire rst_clk_enable, rst_clk_enable_p, rst_clk_enable_n;
`endif
`ifdef XIL_TIMING
not (ngsr, glblGSR);
xor (in_out, D_dly, IS_D_INVERTED_REG, Q_out);
not (nrst, (CLR_dly ^ IS_CLR_INVERTED_REG) && (CLR !== 1'bz));
and (in_clk_enable, ngsr, nrst, CE || (CE === 1'bz));
and (ce_clk_enable, ngsr, nrst, in_out);
and (rst_clk_enable, ngsr, CE || (CE === 1'bz), D ^ IS_D_INVERTED_REG);
always @(negedge nrst) init_enable = (MSGON =="TRUE") && ~glblGSR && (Q_out ^ INIT);
assign notifier1 = (XON == "FALSE") ? 1'bx : notifier;
assign ce_clk_enable_n = (MSGON =="TRUE") && ce_clk_enable && (IS_C_INVERTED == 1'b1);
assign in_clk_enable_n = (MSGON =="TRUE") && in_clk_enable && (IS_C_INVERTED == 1'b1);
assign rst_clk_enable_n = (MSGON =="TRUE") && rst_clk_enable && (IS_C_INVERTED == 1'b1);
assign ce_clk_enable_p = (MSGON =="TRUE") && ce_clk_enable && (IS_C_INVERTED == 1'b0);
assign in_clk_enable_p = (MSGON =="TRUE") && in_clk_enable && (IS_C_INVERTED == 1'b0);
assign rst_clk_enable_p = (MSGON =="TRUE") && rst_clk_enable && (IS_C_INVERTED == 1'b0);
`endif
// end behavioral model
`ifdef XIL_TIMING
specify
(C => Q) = (100:100:100, 100:100:100);
(negedge CLR => (Q +: 0)) = (0:0:0, 0:0:0);
(posedge CLR => (Q +: 0)) = (0:0:0, 0:0:0);
(CLR => Q) = (0:0:0, 0:0:0);
$period (negedge C &&& CE, 0:0:0, notifier);
$period (posedge C &&& CE, 0:0:0, notifier);
$recrem (negedge CLR, negedge C, 0:0:0, 0:0:0, notifier,rst_clk_enable_n,rst_clk_enable_n,CLR_dly, C_dly);
$recrem (negedge CLR, posedge C, 0:0:0, 0:0:0, notifier,rst_clk_enable_p,rst_clk_enable_p,CLR_dly, C_dly);
$recrem (posedge CLR, negedge C, 0:0:0, 0:0:0, notifier,rst_clk_enable_n,rst_clk_enable_n,CLR_dly, C_dly);
$recrem (posedge CLR, posedge C, 0:0:0, 0:0:0, notifier,rst_clk_enable_p,rst_clk_enable_p,CLR_dly, C_dly);
$setuphold (negedge C, negedge CE, 0:0:0, 0:0:0, notifier,ce_clk_enable_n,ce_clk_enable_n,C_dly,CE_dly);
$setuphold (negedge C, negedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_n,in_clk_enable_n,C_dly,D_dly);
$setuphold (negedge C, posedge CE, 0:0:0, 0:0:0, notifier,ce_clk_enable_n,ce_clk_enable_n,C_dly,CE_dly);
$setuphold (negedge C, posedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_n,in_clk_enable_n,C_dly,D_dly);
$setuphold (posedge C, negedge CE, 0:0:0, 0:0:0, notifier,ce_clk_enable_p,ce_clk_enable_p,C_dly,CE_dly);
$setuphold (posedge C, negedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_p,in_clk_enable_p,C_dly,D_dly);
$setuphold (posedge C, posedge CE, 0:0:0, 0:0:0, notifier,ce_clk_enable_p,ce_clk_enable_p,C_dly,CE_dly);
$setuphold (posedge C, posedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_p,in_clk_enable_p,C_dly,D_dly);
$width (negedge C &&& CE, 0:0:0, 0, notifier);
$width (negedge CLR &&& init_enable, 0:0:0, 0, notifier);
$width (posedge C &&& CE, 0:0:0, 0, notifier);
$width (posedge CLR &&& init_enable, 0:0:0, 0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; const double EPS = 1e-6; const double PI = acos(-1); const int INF = 1e9; void FAST() { ios::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); } signed main() { FAST(); int n; cin >> n; vector<long long> a(n + n); for (int i = 0; i < n + n; i++) { cin >> a[i]; } sort(a.begin(), a.end()); long long ans = (a[n - 1] - a[0]) * (a[n + n - 1] - a[n]); for (int i = 1; i < n; i++) { ans = min(ans, (a[n - 1 + i] - a[i]) * (a[n + n - 1] - a[0])); } cout << ans; } |
module ITU_656_Decoder( // TV Decoder Input
iTD_DATA,
// Position Output
oTV_X,
oTV_Y,
oTV_Cont,
// YUV 4:2:2 Output
oYCbCr,
oDVAL,
// Control Signals
iSwap_CbCr,
iSkip,
iRST_N,
iCLK_27 );
input [7:0] iTD_DATA;
input iSwap_CbCr;
input iSkip;
input iRST_N;
input iCLK_27;
output [15:0] oYCbCr;
output [9:0] oTV_X;
output [9:0] oTV_Y;
output [31:0] oTV_Cont;
output oDVAL;
// For detection
reg [23:0] Window; // Sliding window register
reg [17:0] Cont; // Counter
reg Active_Video;
reg Start;
reg Data_Valid;
reg Pre_Field;
reg Field;
wire SAV;
reg FVAL;
reg [9:0] TV_Y;
reg [31:0] Data_Cont;
// For ITU-R 656 to ITU-R 601
reg [7:0] Cb;
reg [7:0] Cr;
reg [15:0] YCbCr;
assign oTV_X = Cont>>1;
assign oTV_Y = TV_Y;
assign oYCbCr = YCbCr;
assign oDVAL = Data_Valid;
assign SAV = (Window==24'hFF0000)&(iTD_DATA[4]==1'b0);
assign oTV_Cont= Data_Cont;
always@(posedge iCLK_27 or negedge iRST_N)
begin
if(!iRST_N)
begin
// Register initial
Active_Video<= 1'b0;
Start <= 1'b0;
Data_Valid <= 1'b0;
Pre_Field <= 1'b0;
Field <= 1'b0;
Window <= 24'h0;
Cont <= 18'h0;
Cb <= 8'h0;
Cr <= 8'h0;
YCbCr <= 16'h0;
FVAL <= 1'b0;
TV_Y <= 10'h0;
Data_Cont <= 32'h0;
end
else
begin
// Sliding window
Window <= {Window[15:0],iTD_DATA};
// Active data counter
if(SAV)
Cont <= 18'h0;
else if(Cont<1440)
Cont <= Cont+1'b1;
// Check the video data is active?
if(SAV)
Active_Video<= 1'b1;
else if(Cont==1440)
Active_Video<= 1'b0;
// Is frame start?
Pre_Field <= Field;
if({Pre_Field,Field}==2'b10)
Start <= 1'b1;
// Field and frame valid check
if(Window==24'hFF0000)
begin
FVAL <= !iTD_DATA[5];
Field <= iTD_DATA[6];
end
// ITU-R 656 to ITU-R 601
if(iSwap_CbCr)
begin
case(Cont[1:0]) // Swap
0: Cb <= iTD_DATA;
1: YCbCr <= {iTD_DATA,Cr};
2: Cr <= iTD_DATA;
3: YCbCr <= {iTD_DATA,Cb};
endcase
end
else
begin
case(Cont[1:0]) // Normal
0: Cb <= iTD_DATA;
1: YCbCr <= {iTD_DATA,Cb};
2: Cr <= iTD_DATA;
3: YCbCr <= {iTD_DATA,Cr};
endcase
end
// Check data valid
if( Start // Frame Start?
&& FVAL // Frame valid?
&& Active_Video // Active video?
&& Cont[0] // Complete ITU-R 601?
&& !iSkip ) // Is non-skip pixel?
Data_Valid <= 1'b1;
else
Data_Valid <= 1'b0;
// TV decoder line counter for one field
if(FVAL && SAV)
TV_Y<= TV_Y+1;
if(!FVAL)
TV_Y<= 0;
// Data counter for one field
if(!FVAL)
Data_Cont <= 0;
if(Data_Valid)
Data_Cont <= Data_Cont+1'b1;
end
end
endmodule |
// megafunction wizard: %ALTDDIO_IN%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altddio_in
// ============================================================
// File Name: rgmii_in4.v
// Megafunction Name(s):
// altddio_in
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.0 Build 176 04/19/2006 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_tse_rgmii_in4 (
aclr,
datain,
inclock,
dataout_h,
dataout_l);
input aclr;
input [3:0] datain;
input inclock;
output [3:0] dataout_h;
output [3:0] dataout_l;
wire [3:0] sub_wire0;
wire [3:0] sub_wire1;
wire [3:0] dataout_h = sub_wire0[3:0];
wire [3:0] dataout_l = sub_wire1[3:0];
altddio_in altddio_in_component (
.datain (datain),
.inclock (inclock),
.aclr (aclr),
.dataout_h (sub_wire0),
.dataout_l (sub_wire1),
.aset (1'b0),
.inclocken (1'b1));
defparam
altddio_in_component.intended_device_family = "Stratix II",
altddio_in_component.invert_input_clocks = "OFF",
altddio_in_component.lpm_type = "altddio_in",
altddio_in_component.width = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ARESET_MODE NUMERIC "0"
// Retrieval info: PRIVATE: CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: INVERT_INPUT_CLOCKS NUMERIC "0"
// Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH NUMERIC "4"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: CONSTANT: INVERT_INPUT_CLOCKS STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_in"
// Retrieval info: CONSTANT: WIDTH NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: USED_PORT: datain 0 0 4 0 INPUT NODEFVAL datain[3..0]
// Retrieval info: USED_PORT: dataout_h 0 0 4 0 OUTPUT NODEFVAL dataout_h[3..0]
// Retrieval info: USED_PORT: dataout_l 0 0 4 0 OUTPUT NODEFVAL dataout_l[3..0]
// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL inclock
// Retrieval info: CONNECT: @datain 0 0 4 0 datain 0 0 4 0
// Retrieval info: CONNECT: dataout_h 0 0 4 0 @dataout_h 0 0 4 0
// Retrieval info: CONNECT: dataout_l 0 0 4 0 @dataout_l 0 0 4 0
// Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4_bb.v TRUE
|
module module6(clk_, rst_, bar, foo);
input clk_;
input rst_;
input [1:0] bar;
output [1:0] foo;
parameter poser_tied = 1'b1;
parameter poser_width_in = 0+1-0+1;
parameter poser_width_out = 0+1-0+1;
parameter poser_grid_width = 4;
parameter poser_grid_depth = 1;
parameter [poser_grid_width-1:0] cellTypes [0:poser_grid_depth-1] = '{ 4'b0000 };
wire [poser_width_in-1:0] poser_inputs;
assign poser_inputs = { bar };
wire [poser_width_out-1:0] poser_outputs;
assign { foo } = poser_outputs;
wire [poser_grid_width-1:0] poser_grid_output [0:poser_grid_depth-1];
wire poser_clk;
assign poser_clk = clk_;
wire poser_rst;
assign poser_rst = rst_;
for (genvar D = 0; D < poser_grid_depth; D++) begin
for (genvar W = 0; W < poser_grid_width; W++) begin
if (D == 0) begin
if (W == 0) begin
poserCell #(.cellType(cellTypes[D][W]), .activeRst(0)) pc (.clk(poser_clk),
.rst(poser_rst),
.i(^{ poser_tied ,
poser_inputs[W%poser_width_in] }),
.o(poser_grid_output[D][W]));
end else begin
poserCell #(.cellType(cellTypes[D][W]), .activeRst(0)) pc (.clk(poser_clk),
.rst(poser_rst),
.i(^{ poser_grid_output[D][W-1],
poser_inputs[W%poser_width_in] }),
.o(poser_grid_output[D][W]));
end
end else begin
if (W == 0) begin
poserCell #(.cellType(cellTypes[D][W]), .activeRst(0)) pc (.clk(poser_clk),
.rst(poser_rst),
.i(^{ poser_grid_output[D-1][W],
poser_grid_output[D-1][poser_grid_depth-1] }),
.o(poser_grid_output[D][W]));
end else begin
poserCell #(.cellType(cellTypes[D][W]), .activeRst(0)) pc (.clk(poser_clk),
.rst(poser_rst),
.i(^{ poser_grid_output[D-1][W],
poser_grid_output[D][W-1] }),
.o(poser_grid_output[D][W]));
end
end
end
end
generate
if (poser_width_out == 1) begin
poserMux #(.poser_mux_width_in(poser_grid_width)) pm (.i(poser_grid_output[poser_grid_depth-1]),
.o(poser_outputs));
end
else if (poser_grid_width == poser_width_out) begin
assign poser_outputs = poser_grid_output[poser_grid_depth-1];
end
else if (poser_grid_width > poser_width_out) begin
wire [poser_grid_width-1:0] poser_grid_output_last;
assign poser_grid_output_last = poser_grid_output[poser_grid_depth-1];
poserMux #(.poser_mux_width_in((poser_grid_width - poser_width_out) + 1)) pm (.i(poser_grid_output_last[poser_grid_width-1:poser_width_out-1]),
.o(poser_outputs[poser_width_out-1]));
assign poser_outputs[poser_width_out-2:0] = poser_grid_output_last[poser_width_out-2:0];
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, k, x, y, z, A[(1 << 17)], B[(1 << 17)], C[(1 << 17)], mmp[(1 << 17)], Comb[18][18]; long long O[(1 << 17)], Ans[4][(1 << 17)], S[4][(1 << 17)]; long long powmod(long long x, long long y = 998244353 - 2, long long p = 998244353) { x %= p; y = (y % (p - 1) + (p - 1)) % (p - 1); long long ans = 1; while (y) { if (y & 1) ans = ans * x % p; x = x * x % p; y >>= 1; } return ans; } signed main() { scanf( %lld%lld%lld%lld%lld , &n, &k, &x, &y, &z); for (long long i = 0; i < n; i++) { scanf( %lld%lld%lld , &A[i], &B[i], &C[i]); B[i] ^= A[i]; C[i] ^= A[i]; } for (long long i = 0; i <= k; i++) for (long long j = 0; j <= i; j++) Comb[i][j] = !j ? 1 : Comb[i - 1][j - 1] + Comb[i - 1][j]; mmp[0] = 1; for (long long i = 1; i <= k; i++) { mmp[i] = 1 - (i % 2); for (long long j = 0; j < i; j++) mmp[i] -= Comb[i][j] * mmp[j]; } for (long long b1 = 0; b1 < 2; b1++) for (long long b2 = 0; b2 < 2; b2++) { memset(O, 0, sizeof O); for (long long i = 0; i < n; i++) O[(B[i] * b1) ^ (C[i] * b2)]++; for (long long i = 1; i < (1 << k); i *= 2) for (long long j = 0; j < (1 << k); j += i + i) for (long long k = j; k < j + i; k++) O[k] = (O[k] + O[k + i]); for (long long i = 0; i < (1 << k); i++) O[i] *= mmp[__builtin_popcount(i)], O[i]; for (long long i = 1; i < (1 << k); i *= 2) for (long long j = 0; j < (1 << k); j += i + i) for (long long k = j; k < j + i; k++) O[k + i] = (O[k + i] + O[k]); memcpy(Ans[b1 * 2 + b2], O, sizeof O); } S[0][1] = x - y - z; S[1][1] = x - y + z; S[2][1] = x + y - z; S[3][1] = x + y + z; for (long long i = 0; i < 4; i++) { S[i][0] = 1; for (long long j = 2; j <= n; j++) S[i][j] = S[i][j - 1] * S[i][1] % 998244353; } for (long long i = 0; i < (1 << k); i++) { long long _00 = Ans[0][i], _01 = Ans[1][i], _10 = Ans[2][i], _11 = Ans[3][i]; long long __00 = (_01 + _10 + _11 - _00) / 2; long long __11 = _11 - __00; long long __01 = _10 - __00; long long __10 = _01 - __00; O[i] = S[0][__11] * S[1][__10] % 998244353 * S[2][__01] % 998244353 * S[3][__00] % 998244353; } long long tot = 0; for (long long i = 0; i < n; i++) tot ^= A[i]; for (long long i = 1; i < (1 << k); i *= 2) for (long long j = 0; j < (1 << k); j += i + i) for (long long k = j; k < j + i; k++) { long long A = O[k], B = O[k + i]; O[k] = (A + B); O[k + i] = (A - B); } long long r = powmod(1 << k); for (long long i = 0; i < (1 << k); i++) printf( %lld , (O[i ^ tot] % 998244353 * r % 998244353 + 998244353) % 998244353); return 0; } |
// $Id: eplv_chkr.v,v 1.1 1997/05/04 17:15:44 demaille Exp $
// This module checks for BDVL deasserting when BEPVL is asserted.
module epvl_chkr(clk, bpvl, bepvl, bdvl, stop);
input clk;
input bpvl;
input bepvl;
input bdvl;
input stop; // $stop (or $finish if BATCH) on error
`ifdef JUST_COUNT_PACKETS
// Do nothing
`else
integer status;
`endif // ifdef JUST_COUNT_PACKETS
always @(posedge clk) begin
if (!bpvl && bepvl && bdvl) begin
$display("%%E-%M, %0t BDVL cannot be deasserted with BEPVL",
$time);
if (stop) begin
#1000
`ifdef JUST_CHECK_COUNTS
// Do nothing
`else
status = $check_counts;
`endif // !ifdef JUST_CHECK_COUNTS
$display("%%I-%M, %0t Stopping simulation on error!", $time);
`ifdef BATCH
$finish;
`else
$stop;
`endif // !ifdef BATCH
end // if (backplane.stop_on_error)
end // if (!bpvl && bepvl && bdvl)
end // always @ (posedge clk)
endmodule // epvl_chkr
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
// Closed loop solution
module cdc_pulse_sync (
input wire clk_in,
input wire pulse_in,
input wire clk_out,
output wire pulse_out
);
wire aq_sync;
reg [1:0] in_pre_sync;
always@(posedge clk_in) begin
in_pre_sync[0] <= pulse_in;
in_pre_sync[1] <= in_pre_sync[0];
end
reg in_sync_pulse;
initial in_sync_pulse = 0; //works only in FPGA
always@(posedge clk_in) begin
if (aq_sync)
in_sync_pulse <= 0;
else if (!in_pre_sync[1] && in_pre_sync[0])
in_sync_pulse <= 1;
end
reg [2:0] out_sync;
always@(posedge clk_out) begin
out_sync[0] <= in_sync_pulse;
out_sync[1] <= out_sync[0];
out_sync[2] <= out_sync[1];
end
assign pulse_out = !out_sync[2] && out_sync[1];
reg [1:0] aq_sync_ff;
always@(posedge clk_in) begin
aq_sync_ff[0] <= out_sync[2];
aq_sync_ff[1] <= aq_sync_ff[0];
end
assign aq_sync = aq_sync_ff[1];
endmodule
|
/*
* Copyright (c) 2002 Jane Skinner
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/* PR#542 */
module top;
parameter[3:0] DAC = 8;
wire d_pm_in_dac_st;
reg [10:0] pm_next_st;
assign d_pm_in_dac_st = (pm_next_st[DAC]);
initial begin
pm_next_st = 10'h100;
#1;
$display("d_pm_in_dac_st = %0b",d_pm_in_dac_st);
$display("d_pm_in_dac_st = %0b",pm_next_st[DAC]);
$finish(0);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 100 + 7; int n; map<pair<int, int>, int> id; vector<int> g[N]; long double rep(long double x) { if (x >= 2) { x -= 2; } return x; } void dfs(int a, int p = 0, long double t = 0) { int deg = (int)g[a].size(); long double jump = 2 / (long double)deg; for (auto &b : g[a]) { if (b == p) continue; t = rep(t + jump); cout << 1 << << id[{a, b}] << ; if (t <= 1) { cout << b << << a << << fixed << setprecision(6) << 1 - t << n ; } else { cout << a << << b << << fixed << setprecision(6) << 1 - rep(t + 1) << n ; } dfs(b, a, rep(t + 1)); } } signed main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n; for (int i = 1; i < n; i++) { int x, y; cin >> x >> y; id[{x, y}] = i; id[{y, x}] = i; g[x].push_back(y); g[y].push_back(x); } int root = 1; cout << n - 1 << n ; dfs(root); } |
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:52:22 06/30/2015
// Design Name:
// Module Name: ps2mouse_to_kmouse
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ps2mouse_to_kmouse (
input wire clk,
input wire rst_n,
input wire [7:0] data,
input wire data_valid,
output reg [7:0] kmouse_x,
output reg [7:0] kmouse_y,
output reg [7:0] kmouse_buttons
);
parameter FIRST_FRAME = 2'd0,
SECOND_FRAME = 2'd1,
THIRD_FRAME = 2'd2,
CALCULATE_NEWXY = 2'd3;
initial begin
kmouse_x = 8'h00;
kmouse_y = 8'h00;
kmouse_buttons = 8'hFF;
end
reg [7:0] deltax, deltay;
reg [1:0] state = FIRST_FRAME;
always @(posedge clk) begin
if (rst_n == 1'b0) begin
kmouse_x <= 8'h00;
kmouse_y <= 8'h00;
kmouse_buttons <= 8'hFF;
state <= FIRST_FRAME;
end
else begin
case (state)
FIRST_FRAME:
if (data_valid == 1'b1) begin
if (data[3] == 1'b1) begin
kmouse_buttons <= {5'b11111,~data[2],~data[0],~data[1]};
state <= SECOND_FRAME;
end
end
SECOND_FRAME:
if (data_valid == 1'b1) begin
deltax <= data;
state <= THIRD_FRAME;
end
THIRD_FRAME:
if (data_valid == 1'b1) begin
deltay <= data;
state <= CALCULATE_NEWXY;
end
CALCULATE_NEWXY:
begin
kmouse_x <= kmouse_x + deltax;
kmouse_y <= kmouse_y + deltay;
state <= FIRST_FRAME;
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; const long long int MOD = 998244353; class Combination { long long int ppow(long long int i, long long int j) { long long int res = 1LL; while (j) { if ((j & 1LL)) { res *= i; if (res >= MOD) { res %= MOD; } } j >>= 1; i *= i; if (i >= MOD) { i %= MOD; } } return res; } public: vector<long long int> k; vector<long long int> r; void resize(int N) { k.resize(N + 2); r.resize(N + 2); k[0] = 1; for (int i = 1; i < N + 2; i++) { k[i] = k[i - 1]; k[i] *= i; if (k[i] >= MOD) k[i] %= MOD; } long long int al = k[k.size() - 1]; long long int iv = ppow(k[k.size() - 1], MOD - 2); r[k.size() - 1] = iv; for (int i = (int)(r.size()) - 2; i >= 0; i--) { r[i] = r[i + 1] * (i + 1); if (r[i] >= MOD) { r[i] %= MOD; } } } long long int C(int a, int b) { if (a < b) return 0; long long int up = k[a]; long long int dw = r[b] * r[a - b]; dw %= MOD; up *= dw; up %= MOD; return up; } long long int H(int a, int b) { return C(a + b - 1, b); } long long int catalan_number(int n) { return (C(2 * n, n) + MOD - C(2 * n, n - 1)) % MOD; } } c; int main() { cin >> n; c.resize(2000000); long long int subt = 0; for (int i = 1; i < n; i++) { long long int way = c.C(n, i); way *= c.k[n - i]; way %= MOD; subt += way; if (subt >= MOD) subt %= MOD; } long long int whole = c.k[n]; whole *= n; whole %= MOD; whole += MOD; whole %= MOD; whole += MOD - subt; whole %= MOD; printf( %lld n , whole); return 0; } |
#include <bits/stdc++.h> int main() { int i, y, ans, z, b, x[2]; for (i = 0; i < 2; i++) { scanf( %d , &x[i]); } y = x[0] * x[1]; ans = y / 2; { printf( %d , ans); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; const int INF = 1e9 + 5; const long long INF64 = 1e18; string to_string(const string &s) { return + s + ; } string to_string(bool b) { return b ? true : false ; } template <typename A, typename B> string to_string(pair<A, B> p) { return ( + to_string(p.first) + , + to_string(p.second) + ) ; } template <typename T> string to_string(const vector<T> &v) { string ret = < ; for (auto it : v) ret += to_string(it) + , ; ret.pop_back(); ret.pop_back(); ret += > ; return ret; } void debug_print() { cerr << endl; } template <typename T, typename... U> void debug_print(T t, U... u) { cerr << << to_string(t); debug_print(u...); } const int N = 1e5 + 5; long long mulmod(long long a, long long b) { a %= MOD; b %= MOD; return (a * b) % MOD; } long long f(long long n) { long long r = (n + 1) / 2; if (n & 1) return mulmod(r, r); return mulmod(r, r + 1); } int main() { ios_base::sync_with_stdio(0), cin.tie(0); int t; cin >> t; while (t--) { long long n; cin >> n; n += 2; n /= 2; cout << f(n) << n ; } return 0; } |
module hybrid(x,y,p);
input [7:0] x,y;
output [15:0] p;
wire [7:0] i,j,k,l,n,o,q,r;
wire [9:0] fp,sp,tp,fop;
wire [3:0] one,two,sign;
wire [6:0] c0,ip0;
wire [12:0] c1,ip1;
wire [6:0] c2;
wire [11:0] m;
wire [3:0] cry,z;
// carry generation
// 1st
xor n9(z[0],one[0],two[0]);
and n10(cry[0],z[0],sign[0]);
//2nd
xor n13(z[1],one[1],two[1]);
and n14(cry[1],z[1],sign[1]);
//3rd
xor n15(z[2],one[2],two[2]);
and n16(cry[2],z[2],sign[2]);
//4th
xor n17(z[3],one[3],two[3]);
and n18(cry[3],z[3],sign[3]);
code e1(one[0],two[0],sign[0],y[1],y[0],1'b0);
code e2(one[1],two[1],sign[1],y[3],y[2],y[1]);
code e3(one[2],two[2],sign[2],y[5],y[4],y[3]);
code e4(one[3],two[3],sign[3],y[7],y[6],y[5]);
//first product generation
product p0(x[0],sign[0],cry[0],one[0],two[0],sign[0],fp[0],i[0],n[0]);
product p1(x[1],i[0],n[0],one[0],two[0],sign[0],fp[1],i[1],n[1]);
product p2(x[2],i[1],n[1],one[0],two[0],sign[0],fp[2],i[2],n[2]);
product p3(x[3],i[2],n[2],one[0],two[0],sign[0],fp[3],i[3],n[3]);
product p4(x[4],i[3],n[3],one[0],two[0],sign[0],fp[4],i[4],n[4]);
product p5(x[5],i[4],n[4],one[0],two[0],sign[0],fp[5],i[5],n[5]);
product p6(x[6],i[5],n[5],one[0],two[0],sign[0],fp[6],i[6],n[6]);
product p7(x[7],i[6],n[6],one[0],two[0],sign[0],fp[7],i[7],n[7]);
xor x1(m[0],i[7],n[7]);
and a1(m[1],two[0],i[7]);
and a2(m[2],one[0],m[0]);
or o1(fp[8],m[1],m[2]);
not n1(fp[9],fp[8]);
assign p[0]=fp[0];
//second product generation
product q0(x[0],sign[1],cry[1],one[1],two[1],sign[1],sp[0],j[0],o[0]);
product q1(x[1],j[0],o[0],one[1],two[1],sign[1],sp[1],j[1],o[1]);
product q2(x[2],j[1],o[1],one[1],two[1],sign[1],sp[2],j[2],o[2]);
product q3(x[3],j[2],o[2],one[1],two[1],sign[1],sp[3],j[3],o[3]);
product q4(x[4],j[3],o[3],one[1],two[1],sign[1],sp[4],j[4],o[4]);
product q5(x[5],j[4],o[4],one[1],two[1],sign[1],sp[5],j[5],o[5]);
product q6(x[6],j[5],o[5],one[1],two[1],sign[1],sp[6],j[6],o[6]);
product q7(x[7],j[6],o[6],one[1],two[1],sign[1],sp[7],j[7],o[7]);
xor x2(m[3],j[7],o[7]);
and a3(m[4],two[1],j[7]);
and a4(m[5],one[1],m[3]);
or o2(sp[8],m[4],m[5]);
not n2(sp[9],sp[8]);
assign p[1]=fp[1];
//third product
product r0(x[0],sign[2],cry[2],one[2],two[2],sign[2],tp[0],k[0],q[0]);
product r1(x[1],k[0],q[0],one[2],two[2],sign[2],tp[1],k[1],q[1]);
product r2(x[2],k[1],q[1],one[2],two[2],sign[2],tp[2],k[2],q[2]);
product r3(x[3],k[2],q[2],one[2],two[2],sign[2],tp[3],k[3],q[3]);
product r4(x[4],k[3],q[3],one[2],two[2],sign[2],tp[4],k[4],q[4]);
product r5(x[5],k[4],q[4],one[2],two[2],sign[2],tp[5],k[5],q[5]);
product r6(x[6],k[5],q[5],one[2],two[2],sign[2],tp[6],k[6],q[6]);
product r7(x[7],k[6],q[6],one[2],two[2],sign[2],tp[7],k[7],q[7]);
xor x3(m[6],k[7],q[7]);
and a5(m[7],two[2],k[7]);
and a6(m[8],one[2],m[6]);
or o3(tp[8],m[7],m[8]);
not n3(tp[9],tp[8]);
//fourth product
product s0(x[0],sign[3],cry[3],one[3],two[3],sign[3],fop[0],l[0],r[0]);
product s1(x[1],l[0],r[0],one[3],two[3],sign[3],fop[1],l[1],r[1]);
product s2(x[2],l[1],r[1],one[3],two[3],sign[3],fop[2],l[2],r[2]);
product s3(x[3],l[2],r[2],one[3],two[3],sign[3],fop[3],l[3],r[3]);
product s4(x[4],l[3],r[3],one[3],two[3],sign[3],fop[4],l[4],r[4]);
product s5(x[5],l[4],r[4],one[3],two[3],sign[3],fop[5],l[5],r[5]);
product s6(x[6],l[5],r[5],one[3],two[3],sign[3],fop[6],l[6],r[6]);
product s7(x[7],l[6],r[6],one[3],two[3],sign[3],fop[7],l[7],r[7]);
xor x4(m[9],l[7],r[7]);
and a7(m[10],two[3],l[7]);
and a8(m[11],one[3],m[9]);
or o4(fop[8],m[10],m[11]);
not n4(fop[9],fop[8]);
//addition
// 1st lvl add
HAd h1(fp[2],sp[0],c1[0],ip1[0]);
HAd h30(fp[3],sp[1],c1[1],ip1[1]);
FAd h2(fp[4],sp[2],tp[0],c1[2],ip1[2]);
FAd h3(fp[5],sp[3],tp[1],c1[3],ip1[3]);
FAd h4(fp[6],sp[4],tp[2],c0[0],ip0[0]);
FAd h5(fp[7],sp[5],tp[3],c0[1],ip0[1]);
FAd h6(fp[8],sp[6],tp[4],c0[2],ip0[2]);
FAd h7(fp[8],sp[7],tp[5],c0[3],ip0[3]);
FAd h8(fp[8],sp[8],tp[6],c0[4],ip0[4]);
FAd h9(fp[9],sp[9],tp[7],c0[5],ip0[5]);
FAd h10(fop[6],tp[8],1'b1,c0[6],ip0[6]);
assign p[2]=ip1[0];
// 2nd lvl add
HAd h11(fop[0],ip0[0],c1[4],ip1[4]);
FAd h12(fop[1],ip0[1],c0[0],c1[5],ip1[5]);
FAd h13(fop[2],ip0[2],c0[1],c1[6],ip1[6]);
FAd h14(fop[3],ip0[3],c0[2],c1[7],ip1[7]);
FAd h15(fop[4],ip0[4],c0[3],c1[8],ip1[8]);
FAd h16(fop[5],ip0[5],c0[4],c1[9],ip1[9]);
HAd h17(ip0[6],c0[5],c1[10],ip1[10]);
FAd h18(fop[7],tp[9],c0[6],c1[11],ip1[11]);
HAd h19(fop[8],1'b1,c1[12],ip1[12]);
//3th add
cla cla1(p[6:3],c2[0],1'b0,ip1[4:1],c1[3:0]);
cla cla2(p[10:7],c2[1],c2[0],ip1[8:5],c1[7:4]);
cla cla3(p[14:11],c2[2],c2[1],ip1[12:9],c1[11:8]);
FA sa16(c1[12],fop[9],c2[2],c2[3],p[15]);
endmodule
// generation of codes
module code(one,two,sign,y2,y1,y0);
input y2,y1,y0;
output one,two,sign;
wire [1:0]k;
xor x1(one,y0,y1);
xor x2(k[1],y2,y1);
not n1(k[0],one);
and a1(two,k[0],k[1]);
assign sign=y2;
endmodule
//generation of inner products
module product(x1,x0,x2,one,two,sign,p,i,ca);
input x1,x0,x2,sign,one,two;
output p,i,ca;
wire [2:0] k;
xor xo1(i,x1,sign);
and a1(k[1],i,one);
and a0(k[0],x0,two);
or o0(k[2],k[1],k[0]);
xor xo2(p,k[2],x2);
and a2(ca,k[2],x2);
endmodule
//adders design
module HAd(a,b,c,s);
input a,b;
output c,s;
xor x1(s,a,b);
and a1(c,a,b);
endmodule
module FAd(a,b,c,cy,sm);
input a,b,c;
output cy,sm;
wire x,y;
xor x1(x,a,b);
xnor x2(y,a,b);
MUX m1(x,y,c,sm);
MUX m2(a,c,x,cy);
endmodule
module MUX(i0,i1,s,o);
input i0,i1,s;
output o;
wire t,p,q;
and a1(t,s,i1);
not n0(p,s);
and a2(q,p,i0);
or a3(o,t,q);
endmodule
module FA(a,b,c,cy,sm);
input a,b,c;
output cy,sm;
wire x,y,z;
xor x1(x,a,b);
xor x2(sm,x,c);
and a1(y,a,b);
and a2(z,x,c);
or o1(cy,y,z);
endmodule
module cla(n,z,o,a,b);
input [3:0] a,b;
input o;
wire [3:0] p,g,c;
wire [9:0]m;
output [3:0]n;
output z;
xor (p[0],a[0],b[0]);
and (g[0],a[0],b[0]);
xor (p[1],a[1],b[1]);
and (g[1],a[1],b[1]);
xor (p[2],a[2],b[2]);
and (g[2],a[2],b[2]);
xor (p[3],a[3],b[3]);
and (g[3],a[3],b[3]);
and (m[0],o,p[0]);
or (c[0],m[0],g[0]);
and (m[1],g[0],p[1]);
and (m[2],o,p[0],p[1]);
or (c[1],g[1],m[1],m[2]);
and (m[3],g[1],p[2]);
and (m[4],g[0],p[1],p[2]);
and (m[5],o,p[1],p[2],p[0]);
or (c[2],g[2],m[3],m[4],m[5]);
and (m[6],g[2],p[3]);
and (m[7],g[1],p[2],p[3]);
and (m[8],g[0],p[1],p[2],p[3]);
and (m[9],o,p[0],p[1],p[2],p[3]);
or (c[3],g[3],m[6],m[7],m[8],m[9]);
xor (n[0],p[0],o);
xor (n[1],p[1],c[0]);
xor (n[2],p[2],c[1]);
xor (n[3],p[3],c[2]);
assign z=c[3];
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND4_1_V
`define SKY130_FD_SC_HS__AND4_1_V
/**
* and4: 4-input AND.
*
* Verilog wrapper for and4 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__and4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__and4_1 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
sky130_fd_sc_hs__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__and4_1 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND4_1_V
|
#include<bits/stdc++.h> using namespace std; #define w(t) int t; cin>>t; while(t--) #define int long long int #define I int32_t #define asc(i,a,n) for(int i=a;i<n;i++) #define dsc(i,n,a) for(int i=n;i>=a;i--) #define vi vector<int> #define pi pair<int,int> #define PB push_back #define MP make_pair I main(){ ios_base::sync_with_stdio(false);cin.tie(NULL);cout.tie(NULL); w(t){ int n; cin>>n; int a[n]; int f[2*n+1]; asc(i,0,2*n+1){ f[i]=1000000; } asc(i,0,n){ cin>>a[i]; f[a[i]]=i+1; } int ans=0; asc(k,3,2*n){ int r=sqrt(k); asc(j,1,r+1){ if(k%j==0&&k!=j*j){ if(f[j]+f[k/j]==k){ ans++; } } } } cout<<ans<<endl; } } |
#include <bits/stdc++.h> using namespace std; const int N = 2010; struct P { long long x, y; int id; bool operator<(P B) const { if (y != B.y) return y < B.y; return x < B.x; } } p[N], op; long long cross(P A, P B, P C) { return (A.x - B.x) * (C.y - B.y) - (C.x - B.x) * (A.y - B.y); } bool cmp(P A, P B) { return cross(A, op, B) < 0; } char a[N]; int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %lld%lld , &p[i].x, &p[i].y); p[i].id = i; } scanf( %s , a + 1); sort(p + 1, p + n + 1); op = p[1]; for (int i = 2; i < n; i++) { sort(p + i, p + n + 1, cmp); if (a[i - 1] == L ) swap(p[i], p[n]); op = p[i]; } for (int i = 1; i <= n; i++) { printf( %d , p[i].id); } return 0; } |
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - assign a string in a function
//
// This test was contributed via forwarding on the geda netlist. I don't
// know who actually wrote it - that isn't obvious from the copy of email
// I eventually received - SDW
//
module test();
wire [31:0] A;
reg [31:0] B;
function [31:0] message;
input [1:0] reg_num;
begin
message = (reg_num == 2'b00) ? "Mes0":
(reg_num == 2'b01) ? "Mes1":
(reg_num == 2'b10) ? "Mes2":
"Mes3";
end
endfunction
assign A = "hi";
initial
begin
B = "ho";
#1;
$display ("%s", A);
$display ("%s", message(1));
$finish;
end
endmodule
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.4 (lin64) Build Wed Nov 18 09:44:32 MST 2015
// Date : Wed May 11 10:40:59 2016
// Host : josem-Studio-XPS-435MT running 64-bit Ubuntu 14.04.2 LTS
// Command : write_verilog -force -mode synth_stub
// /home/josem/Documents/Academics/Spring2016/CPEG324TA/Labs/Lab2_VHDL_CALCULATOR/Project/vivadoProject/Lab2Calculator/Lab2Calculator.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_0_stub.v
// Design : blk_mem_gen_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-3
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_3_1,Vivado 2015.4" *)
module blk_mem_gen_0(clka, ena, wea, addra, dina, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[7:0],dina[7:0],douta[7:0]" */;
input clka;
input ena;
input [0:0]wea;
input [7:0]addra;
input [7:0]dina;
output [7:0]douta;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR4B_1_V
`define SKY130_FD_SC_MS__OR4B_1_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog wrapper for or4b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__or4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__or4b_1 (
X ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__or4b_1 (
X ,
A ,
B ,
C ,
D_N
);
output X ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR4B_1_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDLCLKP_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__SDLCLKP_FUNCTIONAL_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p/sky130_fd_sc_hvl__udp_dlatch_p.v"
`celldefine
module sky130_fd_sc_hvl__sdlclkp (
GCLK,
SCE ,
GATE,
CLK
);
// Module ports
output GCLK;
input SCE ;
input GATE;
input CLK ;
// Local signals
wire m0 ;
wire m0n ;
wire clkn ;
wire SCE_GATE;
// Name Output Other arguments
not not0 (m0n , m0 );
not not1 (clkn , CLK );
nor nor0 (SCE_GATE, GATE, SCE );
sky130_fd_sc_hvl__udp_dlatch$P dlatch0 (m0 , SCE_GATE, clkn );
and and0 (GCLK , m0n, CLK );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDLCLKP_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; const int maxn = 2 * 1e5 + 10; char str[maxn]; int ans[maxn]; int main() { int n, a, b, k; while (scanf( %d%d%d%d , &n, &a, &b, &k) != EOF) { scanf( %s , str + 1); int m = 0, cnt = 0; for (int i = 1; i <= n; ++i) { if (str[i] == 0 ) { cnt++; if (cnt == b) { ans[m++] = i; cnt = 0; } } if (str[i] == 1 ) cnt = 0; } printf( %d n , m + 1 - a); printf( %d , ans[0]); for (int i = 1; i <= m - a; ++i) printf( %d , ans[i]); printf( n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> ostream& operator<<(ostream& os, vector<T> V) { os << [ ; for (auto v : V) os << v << ; os << ] ; return os; } template <class T> ostream& operator<<(ostream& os, set<T> second) { os << { ; for (auto s : second) os << s << ; return os << } ; } template <class T> ostream& operator<<(ostream& os, multiset<T> second) { os << { ; for (auto s : second) os << s << ; return os << } ; } template <class L, class R> ostream& operator<<(ostream& os, pair<L, R> P) { return os << ( << P.first << , << P.second << ) ; } template <class L, class R> ostream& operator<<(ostream& os, map<L, R> M) { os << { ; for (auto m : M) os << ( << m.first << : << m.second << ) ; return os << } ; } template <class L, class R> ostream& operator<<(ostream& os, unordered_map<L, R> M) { os << { ; for (auto m : M) os << ( << m.first << : << m.second << ) ; return os << } ; } const long long N = 200010, M = 1e9 + 7; long long n, a[N]; vector<long long> f[N], sol; void solve() { cin >> n; for (long long i = 0; i < n; i++) cin >> a[i]; for (long long i = 0; i < n; i++) f[a[i]].push_back(i + 1); sol = vector<long long>(0); long long minus = 0; for (long long i = 0; i < n; i++) { long long h = i - minus; while (h >= 0 && f[h].size() == 0) h -= 3, minus += 3; if (h < 0) { cout << Impossible n ; return; } sol.push_back(f[h].back()); f[h].pop_back(); } cout << Possible n ; for (long long it : sol) cout << it << ; cout << n ; } int main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(0); solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); const long long mod = 998244353; int LIMIT; long long modpow(long long b, long long e) { long long ans = 1; for (; e; b = b * b % mod, e /= 2) if (e & 1) ans = ans * b % mod; return ans; } const long long root = 62; inline void ntt(vector<long long>& a, vector<long long>& rt, vector<long long>& rev, int n) { for (int i = 0; i < (n); ++i) if (i < rev[i]) swap(a[i], a[rev[i]]); for (int k = 1; k < n; k *= 2) for (int i = 0; i < n; i += 2 * k) for (int j = 0; j < (k); ++j) { long long z = rt[j + k] * a[i + j + k] % mod, &ai = a[i + j]; a[i + j + k] = (z > ai ? ai - z + mod : ai - z); ai += (ai + z >= mod ? z - mod : z); } } vector<long long> conv(const vector<long long>& a, const vector<long long>& b) { if (a.empty() || b.empty()) return {}; int s = (int)(a).size() + (int)(b).size() - 1, B = 32 - __builtin_clz(s), n = 1 << B; vector<long long> L(a), R(b), out(n), rt(n, 1), rev(n); L.resize(n), R.resize(n); for (int i = 0; i < (n); ++i) rev[i] = (rev[i / 2] | (i & 1) << B) / 2; long long curL = mod / 2, inv = modpow(n, mod - 2); for (int k = 2; k < n; k *= 2) { long long z[] = {1, modpow(root, curL /= 2)}; for (int i = k; i < (2 * k); ++i) rt[i] = rt[i / 2] * z[i & 1] % mod; } ntt(L, rt, rev, n); ntt(R, rt, rev, n); for (int i = 0; i < (n); ++i) out[-i & (n - 1)] = L[i] * R[i] % mod * inv % mod; ntt(out, rt, rev, n); return {out.begin(), out.begin() + s}; } void read(int& n) { n = 0; char c = getchar(); while (c >= 0 && c <= 9 ) { n = n * 10 + c - 0 ; c = getchar(); } } vector<long long> t; vector<long long> res[3000005]; vector<long long> s[3000005]; int a[200005]; int cnt[3000005]; priority_queue<pair<int, int> > pq; int main() { int n; read(n); LIMIT = n / 2 + 1; for (int i = 1; i <= n; i++) { read(a[i]); cnt[a[i]]++; s[a[i]].push_back(1); } for (int i = 1; i <= n; i++) { if (cnt[a[i]]) { s[a[i]].push_back(1); pq.push({-cnt[a[i]], a[i]}); cnt[a[i]] = 0; } } while (!pq.empty()) { int v = pq.top().second; pq.pop(); if (pq.empty()) { cout << s[v][n / 2]; return 0; } int u = pq.top().second; pq.pop(); s[v] = conv(s[v], s[u]); while (s[v].size() > LIMIT) s[v].pop_back(); pq.push({-s[v].size(), v}); } } |
#include <bits/stdc++.h> #pragma optimise GCC(-O2) using namespace std; mt19937_64 rang( chrono::high_resolution_clock::now().time_since_epoch().count()); int rng(int lim) { uniform_int_distribution<int> uid(0, lim - 1); return uid(rang); } long long INF = LLONG_MAX; const long long M = 1000000007; long long powm(long long, long long); long long perm[2000005]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long n; cin >> n; for (int i = 0; i < 2000005; i++) perm[i] = -1; for (int i = 1; i < n + 1; i++) perm[i] = i; for (int i = 2; i < n + 1; i++) { long long to_be = -1; long long replace = 0; while (replace * i + 1 <= n) { swap(to_be, perm[replace * i + i - 1]); replace++; } swap(to_be, perm[n + i - 1]); } for (int i = 0; i < 2000005; i++) if (perm[i] != -1) cout << perm[i] << ; } long long powm(long long a, long long b) { long long res = 1; while (b) { if (b & 1) res = (res * a) % M; a = (a * a) % M; b >>= 1; } return res; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR2B_1_V
`define SKY130_FD_SC_HDLL__NOR2B_1_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog wrapper for nor2b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nor2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor2b_1 (
Y ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nor2b base (
.Y(Y),
.A(A),
.B_N(B_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor2b_1 (
Y ,
A ,
B_N
);
output Y ;
input A ;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nor2b base (
.Y(Y),
.A(A),
.B_N(B_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR2B_1_V
|
module tb_spi_i2s_ipi_clk_div();
localparam TB_PARAM_CNT_WIDTH = 8;
localparam TB_PARAM_STAGE_NUM = 3;
function integer clogb2;
input [31:0] value;
reg div2;
begin
for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
value = value >> 1;
end
endfunction
wire clkd_clk_out_o;
wire clkd_time_base_o;
reg [clogb2(TB_PARAM_CNT_WIDTH) - 1 : 0] clkd_clk_div_sel_i;
reg clkd_enable_i;
reg clkd_clk;
reg clkd_rst_n;
integer i;
spi_i2s_ipi_clk_div
#(
.PARAM_CNT_WIDTH ( TB_PARAM_CNT_WIDTH ),
.PARAM_STAGE_WIDTH ( TB_PARAM_STAGE_NUM )
)
CLK_DIV
(
.clkd_clk_out_o ( clkd_clk_out_o ),
.clkd_time_base_o ( clkd_time_base_o ),
.clkd_clk_div_sel_i ( clkd_clk_div_sel_i),
.clkd_enable_i ( clkd_enable_i ),
.clkd_clk ( clkd_clk ),
.clkd_rst_n ( clkd_rst_n )
);
initial
begin
clkd_clk = 0;
clkd_rst_n = 0;
clkd_enable_i = 0;
clkd_clk_div_sel_i = 0;
@(posedge clkd_clk);
@(posedge clkd_clk);
clkd_rst_n = 1;
clkd_enable_i = 1;
for(i = 0; i < 8; i = i + 1)
begin
repeat(10*2**i)
@(posedge clkd_clk);
if(i != 0)
@(posedge clkd_time_base_o);
clkd_enable_i = 0;
clkd_clk_div_sel_i = i + 1;
@(posedge clkd_clk);
clkd_enable_i = 1;
end
$stop;
end
always #10
clkd_clk = !clkd_clk;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, cnt, T; vector<int> g[128]; void input(int x) { if (g[x].size()) return; if (cnt == 16) { g[x].push_back(1), g[x].push_back(1); return; } cnt++; printf( ? %d n , x); fflush(stdout); int nw, y; scanf( %d , &nw); while (nw--) { scanf( %d , &y); g[x].push_back(y); } return; } void solve() { cnt = 0; for (int i = 0; i < 128; i++) g[i].clear(); cin >> n; input(1); if (g[1].size() == 2) { printf( ! 1 n ); fflush(stdout); return; } deque<int> q; q.push_back(1); int nw = 1; while (g[nw].size() != 1) { for (int i = 0; i < g[nw].size(); i++) if (g[g[nw][i]].size() == 0) { nw = g[nw][i]; break; } q.push_front(nw); input(nw); if (g[nw].size() == 2) { cout << ! << nw << endl; fflush(stdout); return; } } nw = 1; while (g[nw].size() != 1) { for (int i = 0; i < g[nw].size(); i++) if (g[g[nw][i]].size() == 0) { nw = g[nw][i]; break; } q.push_back(nw); input(nw); if (g[nw].size() == 2) { cout << ! << nw << endl; fflush(stdout); return; } } nw = q[q.size() / 2]; int dep = q.size() / 2; vector<int> pa; if (q.size() != 1) { pa.push_back(q[q.size() / 2 - 1]); pa.push_back(q[q.size() / 2 + 1]); } int couter = 0; while (dep != n - 3 && dep != n - 1) { vector<int> maybe; input(nw); if (g[nw].size() == 2) { cout << ! << nw << endl; fflush(stdout); return; } for (int i = 0; i < g[nw].size(); i++) { bool ok = 1; for (int j = 0; j < pa.size(); j++) if (pa[j] == g[nw][i]) ok = 0; if (ok) maybe.push_back(g[nw][i]); } dep++; pa.clear(); couter = couter * 10 + maybe.size(); if (maybe.size() == 1) { pa.push_back(nw); nw = maybe[0]; continue; } int nwchk = maybe[0]; for (int i = 0; i < dep - 2; i++) { input(nwchk); if (g[nwchk].size() == 2) { cout << ! << nwchk << endl; fflush(stdout); return; } for (int j = 0; j < g[nwchk].size(); j++) if (g[g[nwchk][j]].size() == 0) nwchk = g[nwchk][j]; } input(nwchk); if (g[nwchk].size() == 2) { cout << ! << nwchk << endl; fflush(stdout); return; } pa.push_back(nw); if (g[nwchk].size() == 1) nw = maybe[1]; else nw = maybe[0]; } if (dep == n - 1) { cout << ! << nw << endl; fflush(stdout); return; } input(nw); vector<int> maybe; for (int i = 0; i < g[nw].size(); i++) { maybe.push_back(g[nw][i]); input(g[nw][i]); if (g[g[nw][i]].size() == 2) { cout << ! << g[nw][i] << endl; fflush(stdout); return; } } for (int i = 0; i < maybe.size(); i++) for (int j = 0; j < g[maybe[i]].size(); j++) { input(g[maybe[i]][j]); if (g[g[maybe[i]][j]].size() == 2) { cout << ! << g[maybe[i]][j] << endl; fflush(stdout); return; } } if (T == 7) { cout << ! << couter; fflush(stdout); exit(0); } cout << ! -1 n ; fflush(stdout); return; } int main() { cin >> T; while (T--) solve(); } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m; scanf( %d %d , &n, &m); vector<int> v(n + 1); for (int i = 1; i <= n; i++) scanf( %d , &v[i]); double ans = 0.0; int a, b, w; for (int i = 1; i <= m; i++) { scanf( %d %d %d , &a, &b, &w); ans = max(ans, 1.0 * (v[a] + v[b]) / w); } printf( %0.9lf n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long inf = 1000000000000000ll; long long b[230400], h[230400], d[230400], ans, t[230400], n, m; struct node { long long c, e; } a[230400]; struct seg { long long l, r, val, z; } s[230400 * 4]; bool cmp(node u, node v) { if (u.c == v.c) return u.e < v.e; return u.c < v.c; } void build(long long p, long long l, long long r) { s[p].l = l; s[p].r = r; if (l == r) { s[p].val = t[l]; s[p].z = 0; return; } long long mid = (l + r) >> 1; build(p << 1, l, mid); build((p << 1) | 1, mid + 1, r); s[p].val = min(s[p << 1].val, s[(p << 1) | 1].val); s[p].z = 0; } void pass(long long p) { s[p].val += s[p].z; if (s[p].l != s[p].r) s[p << 1].z += s[p].z, s[(p << 1) | 1].z += s[p].z; s[p].z = 0; } void update(long long p, long long l, long long r, long long w) { if (s[p].l > r || s[p].r < l) { pass(p); return; } if (s[p].l >= l && s[p].r <= r) { s[p].z += w; pass(p); return; } pass(p); update(p << 1, l, r, w); update((p << 1) | 1, l, r, w); s[p].val = min(s[p << 1].val, s[(p << 1) | 1].val); } long long qry(long long p, long long l, long long r) { pass(p); if (s[p].l > r || s[p].r < l) return inf; if (s[p].l >= l && s[p].r <= r) return s[p].val; return min(qry(p << 1, l, r), qry((p << 1) | 1, l, r)); } int main() { scanf( %d%d , &n, &m); for (long long i = 1; i <= n; i++) scanf( %lld , &b[i]); d[n] = b[n]; for (long long i = n - 1; i; i--) d[i] = max(d[i + 1], b[i]); for (long long i = 1; i <= n; i++) t[i] = t[i - 1] + b[i]; build(1, 1, n); for (long long i = 0; i < m; i++) scanf( %lld , &a[i].e); for (long long i = 0; i < m; i++) scanf( %lld , &a[i].c); sort(a, a + m, cmp); for (long long i = 0; i < m; i++) { if (d[1] < a[i].e) continue; long long lf, rt, mid; lf = 0; rt = n + 1; while (rt - lf > 1) { mid = (lf + rt) >> 1; if (d[mid] < a[i].e) rt = mid; else lf = mid; } if (qry(1, lf, n) >= a[i].c) update(1, lf, n, -a[i].c), ans++; } cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; struct State { int bk; string fr; int pos; int cnt; }; bool operator<(State lhs, State rhs) { if (lhs.bk != rhs.bk) return lhs.bk < rhs.bk; if (lhs.fr != rhs.fr) return lhs.fr < rhs.fr; if (lhs.pos != rhs.pos) return lhs.pos < rhs.pos; if (lhs.cnt != rhs.cnt) return lhs.cnt < rhs.cnt; return false; } int main() { int n; cin >> n; string s; cin >> s; vector<int> jump(s.size() + 1, 0); for (int i = 0; i <= s.size(); i++) { int to = 0; for (int j = 0; j < i; j++) { bool ok = true; for (int k = 0; k < j; k++) { ok &= (s[k] == s[i - j + k]); } if (i != s.size()) ok &= (s[j] != s[i]); if (ok) to = j + 1 - (int)(i == s.size()); } jump[i] = to; } set<string> subs; for (int i = 0; i < s.size(); i++) { for (int j = i + 1; j <= s.size(); j++) { string ss; for (int k = i; k < j; k++) { ss += s[k]; } subs.insert(ss); } } set<string> lasts; string ss; for (int i = s.size() - 1; i >= 0; i--) { ss = s[i] + ss; lasts.insert(ss); } map<State, ll> dp; dp[State{-1, , 0, 0}] = 1; for (int i = 0; i < n; i++) { map<State, ll> next; for (auto &e : dp) { int bk = e.first.bk; string str = e.first.fr; int pos = e.first.pos; int cnt = e.first.cnt; if (str != @ ) { str += s[pos]; if (subs.count(str)) { if (lasts.count(str)) { bk = i; } } else { str = @ ; } } if (++pos == s.size()) { pos = jump[pos]; cnt = true; } next[State{bk, str, pos, cnt}] += e.second; bk = e.first.bk; str = e.first.fr; pos = e.first.pos; cnt = e.first.cnt; if (str != @ ) { str += (s[pos] == 0 ? 1 : 0 ); if (subs.count(str)) { if (lasts.count(str)) { bk = i; } } else { str = @ ; } } pos = jump[pos]; next[State{bk, str, pos, cnt}] += e.second; } dp = next; } ll res = 0; for (auto &e : dp) { int bk = e.first.bk; string strs = e.first.fr; int pos = e.first.pos; int cnt = e.first.cnt; string str; for (int i = 0; i < e.first.pos; i++) { str += s[i]; } for (int i = s.size() - e.first.bk - 1; i < s.size(); i++) { str += s[i]; } for (int i = 0; i <= (int)str.size() - (int)s.size(); i++) { if (s == str.substr(i, s.size())) { cnt = true; } } if (cnt >= 1) { res += e.second; } } cout << res << endl; return 0; } |
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 19:49:33 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_processing_system7_0_0_stub.v
// Design : ip_design_processing_system7_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2017.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(I2C0_SDA_I, I2C0_SDA_O, I2C0_SDA_T, I2C0_SCL_I,
I2C0_SCL_O, I2C0_SCL_T, TTC0_WAVE0_OUT, TTC0_WAVE1_OUT, TTC0_WAVE2_OUT, USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT, M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY, M_AXI_GP0_RREADY, M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID,
M_AXI_GP0_AWID, M_AXI_GP0_WID, M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST, M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR, M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS, M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK, M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST, M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID,
M_AXI_GP0_BRESP, M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, FCLK_CLK0, FCLK_CLK1, FCLK_RESET0_N, MIO,
DDR_CAS_n, DDR_CKE, DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB,
DDR_BankAddr, DDR_Addr, DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK,
PS_PORB)
/* synthesis syn_black_box black_box_pad_pin="I2C0_SDA_I,I2C0_SDA_O,I2C0_SDA_T,I2C0_SCL_I,I2C0_SCL_O,I2C0_SCL_T,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],FCLK_CLK0,FCLK_CLK1,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
input I2C0_SDA_I;
output I2C0_SDA_O;
output I2C0_SDA_T;
input I2C0_SCL_I;
output I2C0_SCL_O;
output I2C0_SCL_T;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
output FCLK_CLK0;
output FCLK_CLK1;
output FCLK_RESET0_N;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
endmodule
|
#include <bits/stdc++.h> using namespace std; int K; long long p[21], a[21], aLeft[21]; long long N, Nq3; long long minArea = 3000000000000000000LL; long long ansA, ansB, ansC; long long curA; long long leftMul[21]; long long BCq, BC, nowBest; void dfs2(int cur, long long carry) { if (carry * leftMul[cur] < BCq) return; if (carry > nowBest) return; if (carry >= BCq) { nowBest = carry; return; } if (cur == K + 1) return; dfs2(cur + 1, carry); for (int i = 1; i <= aLeft[cur]; i++) { carry *= p[cur]; dfs2(cur + 1, carry); } } void calc(long long _curA) { nowBest = 3000000000000000000LL; curA = _curA; BC = N / curA; double each = sqrt(double(BC)); if (curA * 2 * each + BC > minArea + 10) return; leftMul[K + 1] = 1; for (int i = K; i >= 1; i--) { leftMul[i] = leftMul[i + 1]; for (int j = 1; j <= aLeft[i]; j++) leftMul[i] *= p[i]; } BCq = sqrt(double(BC - 1)); while (BCq * BCq < BC) BCq++; dfs2(1, 1); long long curB = nowBest, curC = BC / curB; if (curA * (curB + curC) + BC < minArea) { minArea = curA * (curB + curC) + BC; ansA = curA; ansB = curB; ansC = curC; } } void dfs(int cur, long long carry) { if (cur == K + 1) calc(carry); else { aLeft[cur] = a[cur]; dfs(cur + 1, carry); for (int i = 1; i <= a[cur]; i++) { carry *= p[cur]; if (carry > Nq3) return; aLeft[cur] = a[cur] - i; dfs(cur + 1, carry); } } } void solve() { minArea = 3000000000000000000LL; for (int iteration = 1; iteration <= K; iteration++) for (int i = 1; i < K; i++) if (p[i] < p[i + 1]) { swap(p[i], p[i + 1]); swap(a[i], a[i + 1]); } N = 1; for (int i = 1; i <= K; i++) for (int j = 1; j <= a[i]; j++) N *= p[i]; Nq3 = pow(double(N - 1), 1 / 3.0); while (Nq3 * Nq3 * Nq3 < N) Nq3++; dfs(1, 1); cout << 2 * minArea << << ansA << << ansB << << ansC << endl; } int main() { ios ::sync_with_stdio(false); int TestCase; cin >> TestCase; for (int CaseID = 1; CaseID <= TestCase; CaseID++) { cin >> K; for (int i = 1; i <= K; i++) cin >> p[i] >> a[i]; solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; struct LCA { int logn; vector<int> depth; vector<vector<int> > lca; vector<vector<int> > *edges; LCA(int n, vector<vector<int> > *edges) { logn = log(n) / log(2) + 1; depth.resize(n + 1, 0); lca.resize(n + 1, vector<int>(logn, 0)); this->edges = edges; build(); } void dfs(int u, int p) { lca[u][0] = p; for (int i = 1; i < logn; i++) { lca[u][i] = lca[lca[u][i - 1]][i - 1]; } depth[u] = depth[p] + 1; for (auto &v : (*edges)[u]) { if (p != v) { dfs(v, u); } } } int parent(int v, int h) { for (int i = logn - 1; i >= 0; i--) { if (h & (1 << i)) { v = lca[v][i]; } } return v; } int lessParent(int u, int p) { return parent(u, depth[u] - depth[p] - 1); } int get(int u, int v) { if (depth[u] > depth[v]) { swap(u, v); } int h = depth[v] - depth[u]; v = parent(v, h); if (u == v) { return u; } for (int i = logn - 1; i >= 0; i--) { if (lca[u][i] != lca[v][i]) { u = lca[u][i]; v = lca[v][i]; } } return lca[u][0]; } void build() { dfs(1, 0); } } * lca; struct GraphBuilder { enum DIRECT { UP = 0, DOWN, }; int n; int k; vector<vector<int> > *e; vector<pair<int, int> > edges; set<pair<int, int> > cache; vector<vector<int> > addedVertices; vector<vector<int> > deletedVertices; LCA *lca; struct Node { int id; Node *leftChild; Node *rightChild; Node(int v, Node *l, Node *r) { id = v; leftChild = l; rightChild = r; } }; vector<pair<Node *, Node *> > root; GraphBuilder(int m, vector<vector<int> > *e) { k = 2 * m - 1; n = 2 * m - 1; this->e = e; lca = new LCA(e->size() - 1, e); addedVertices.resize(e->size()); deletedVertices.resize(e->size()); for (int i = 0; i < m; i++) { for (int j = 0; j < 2; j++) { int u, v; scanf( %d %d , &u, &v); int p = lca->get(u, v); if (u != p) { addedVertices[u].push_back((i << 1) | j); deletedVertices[lca->lessParent(u, p)].push_back((i << 1) | j); } if (v != p) { addedVertices[v].push_back((i << 1) | j); deletedVertices[lca->lessParent(v, p)].push_back((i << 1) | j); } } } root.resize(e->size(), {0, 0}); dfs(1, 0); } void dfs(int u, int p) { for (auto &v : (*e)[u]) { if (v != p) { dfs(v, u); root[u].first = merge(root[u].first, root[v].first, DOWN); root[u].second = merge(root[u].second, root[v].second, UP); } } for (auto &x : addedVertices[u]) { if (root[u].first) { add(x, root[u].first->id); } int a = 0; root[u].first = addVertex(0, n, root[u].first, (x ^ 1), DOWN); if (root[u].second) { add(root[u].second->id, (x ^ 1)); } root[u].second = addVertex(0, n, root[u].second, x, UP); } for (auto &x : deletedVertices[u]) { root[u].first = delVertex(0, n, root[u].first, (x ^ 1), DOWN); root[u].second = delVertex(0, n, root[u].second, x, UP); if (root[u].first) { add(x, root[u].first->id); } if (root[u].second) { add(root[u].second->id, (x ^ 1)); } } } void add(int u, int v) { edges.push_back({u, v}); } void addEdge(Node *p, int direct) { if (direct == DOWN) { if (p->leftChild) { add(p->id, p->leftChild->id); } if (p->rightChild) { add(p->id, p->rightChild->id); } } else { if (p->leftChild) { add(p->leftChild->id, p->id); } if (p->rightChild) { add(p->rightChild->id, p->id); } } } Node *addVertex(int l, int r, Node *p, int v, int direct) { if (!p) { p = new Node(0, 0, 0); } if (l == r) { return new Node(v, 0, 0); } else { int mid = (l + r) >> 1; Node *newNode = new Node(++k, p->leftChild, p->rightChild); if (v <= mid) { newNode->leftChild = addVertex(l, mid, p->leftChild, v, direct); } else { newNode->rightChild = addVertex(mid + 1, r, p->rightChild, v, direct); } addEdge(newNode, direct); return newNode; } } Node *delVertex(int l, int r, Node *p, int v, int direct) { if (l == r) { return 0; } else { int mid = (l + r) >> 1; Node *newNode = new Node(++k, p->leftChild, p->rightChild); if (v <= mid) { newNode->leftChild = delVertex(l, mid, p->leftChild, v, direct); } else { newNode->rightChild = delVertex(mid + 1, r, p->rightChild, v, direct); } if (!newNode->leftChild && !newNode->rightChild) { return 0; } addEdge(newNode, direct); return newNode; } } Node *merge(Node *p1, Node *p2, int direct) { if (!p1 || !p2) { return p1 ? p1 : p2; } else { Node *left = merge(p1->leftChild, p2->leftChild, direct); Node *right = merge(p1->rightChild, p2->rightChild, direct); Node *newNode = new Node(++k, left, right); addEdge(newNode, direct); return newNode; } } }; struct SAT { int n; vector<int> st; vector<int> mark; vector<int> group; vector<vector<int> > edges; vector<vector<int> > revEdges; SAT(int n, vector<pair<int, int> > &e) { this->n = n + 1; mark.resize(n + 1, 0); group.resize(n + 1, 0); edges.resize(n + 1); revEdges.resize(n + 1); for (auto &p : e) { addEdge(p.first, p.second); } } void addEdge(int u, int v) { edges[u].push_back(v); revEdges[v].push_back(u); } void dfs1(int u) { mark[u] = 1; for (auto &v : edges[u]) { if (mark[v] == 0) { dfs1(v); } } st.push_back(u); } void dfs2(int u, int k) { group[u] = k; for (auto &v : revEdges[u]) { if (group[v] == 0) { dfs2(v, k); } } } void solve() { for (int i = 0; i < n; i++) { if (mark[i] == 0) { dfs1(i); } } int k = 0; for (int i = st.size() - 1; i >= 0; i--) { int u = st[i]; if (group[u] == 0) { k++; dfs2(u, k); } } } void answer(int m) { for (int i = 0; i < 2 * m; i += 2) { if (group[i] == group[i | 1]) { printf( NO ); return; } } printf( YES n ); for (int i = 0; i < 2 * m; i += 2) { printf( %d n , (group[i] > group[i | 1]) ? 1 : 2); } } void print() { cout << nst n ; for (int x : st) { cout << x << << group[x] << n ; } cout << n ; for (int i = 0; i < n; i++) { cout << i << : ; for (int j : edges[i]) { cout << j << ; } cout << n ; } } }; int main() { int n; scanf( %d , &n); vector<vector<int> > edges(n + 1); for (int i = 1; i < n; i++) { int u, v; scanf( %d %d , &u, &v); edges[u].push_back(v); edges[v].push_back(u); } int m; scanf( %d , &m); GraphBuilder builder(m, &edges); SAT solver(builder.k, builder.edges); solver.solve(); solver.answer(m); } |
#include <bits/stdc++.h> using namespace std; template <class T> int size(const T &x) { return x.size(); } const int INF = ~(1 << 31); const double EPS = 1e-9; const double pi = acos(-1); template <class T> T smod(T a, T b) { return (a % b + b) % b; } int f(char c) { return c - a ; } char g(int i) { return (char)(i + a ); } int main() { int n; cin >> n; char c; vector<bool> A(26, true); int left = 26, cnt = 0; for (decltype(0) i = (0); i < (n); ++i) { cin >> c; if (c == . ) { vector<bool> B(26, true); string s; cin >> s; for (decltype(0) j = (0); j < (size(s)); ++j) { B[f(s[j])] = false; } for (decltype(0) j = (0); j < (26); ++j) { A[j] = A[j] && B[j]; } } else if (c == ! ) { if (left == 1) cnt++; vector<bool> B(26, false); string s; cin >> s; for (decltype(0) j = (0); j < (size(s)); ++j) { B[f(s[j])] = true; } for (decltype(0) j = (0); j < (26); ++j) { A[j] = A[j] && B[j]; } } else { char s; cin >> s; if (left == 1 && i != n - 1) cnt++; A[f(s)] = false; } left = 0; for (decltype(0) j = (0); j < (26); ++j) { left += A[j]; } } cout << cnt << endl; return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/15/2016 01:13:48 PM
// Design Name:
// Module Name: Add_Subt
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Add_Subt
#(parameter SWR=26) (
input wire clk,
input wire rst,
input wire load_i,//Reg load input
input wire Add_Sub_op_i,
input wire [SWR-1:0] Data_A_i,
input wire [SWR-1:0] PreData_B_i,
/////////////////////////////////////////////////////////////
output wire [SWR-1:0] Data_Result_o,
//output wire [SWR-1:0] P_o,
//output wire [SWR-1:1] Cn_o,
output wire FSM_C_o
);
wire [SWR-1:0] Data_B;
wire [SWR:0] S_to_D;
wire [SWR-1:0] P_to_D;
wire [SWR-1:1] C_to_D;
wire Co_to_D;
//wire Co_to_gate;
/*
/////////////////////////////////////////7
genvar j;
for (j=0; j<SWR; j=j+1)begin
assign Data_B[j] = PreData_B_i[j] ^ Add_Sub_op_i;
end
Full_Adder_PG #(.SWR(SWR)) AS_Module(
.clk(clk),
.rst(rst),
.Op_A_i(Data_A_i),
.Op_B_i(Data_B),
.C_i(Add_Sub_op_i), //Carry in
.S_o(S_to_D), // Solution out
.Cn_o(C_to_D),
.C_o(Co_to_gate), //Carry out
.P_o(P_o) //Propagate (for LZA)
);*/
add_sub_carry_out #(.W(SWR)) Sgf_AS (
.op_mode(Add_Sub_op_i),
.Data_A(Data_A_i),
.Data_B(PreData_B_i),
.Data_S(S_to_D)
);
assign Co_to_D = S_to_D[SWR] & ~Add_Sub_op_i;
RegisterAdd #(.W(SWR)) Add_Subt_Result(
.clk (clk),
.rst (rst),
.load (load_i),
.D (S_to_D[SWR-1:0]),
.Q (Data_Result_o)
);
/*RegisterAdd #(.W(SWR)) P_Result(
.clk (clk),
.rst (rst),
.load (load_i),
.D (P_to_D),
.Q (P_o)
);*/
/*RegisterAdd #(.W(SWR-1)) C_Result(
.clk (clk),
.rst (rst),
.load (load_i),
.D (C_to_D),
.Q (Cn_o)
);*/
RegisterAdd #(.W(1)) Add_overflow_Result(
.clk (clk),
.rst (rst),
.load (load_i),
.D (S_to_D[SWR]),
.Q (FSM_C_o)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> a[15]; vector<pair<int, int>> all; int rp[75000]; long long sum[15]; vector<pair<int, int>> loops; int path[16]; int plen = 0; bool vis[1 << 15] = {0}; int finstate; bool dfs(int state, int ps) { if (state == finstate) return true; if (vis[state]) return false; vis[state] = true; for (int i = ps; i < loops.size(); i++) { int m = loops[i].first; if ((state & m) == 0 && !vis[state | m] && dfs(state | m, i + 1)) { path[plen++] = i; return true; } } return false; } int main() { ios::sync_with_stdio(false); int k; long long total = 0; cin >> k; for (int i = 0; i < k; i++) { int ni; cin >> ni; a[i].reserve(ni); long long s = 0; for (int j = 0; j < ni; ++j) { int x; cin >> x; s += x; a[i].push_back(x); all.push_back(make_pair(x, i)); } sum[i] = s; total += s; } if (total % k != 0) { cout << No << endl; return 0; } long long final = total / k; sort(all.begin(), all.end()); int okmask = 0; for (int i = 0; i < k; i++) if (sum[i] == final) okmask |= 1 << i; int n = all.size(); for (int i = 0; i < n; i++) { long long v = all[i].first; long long delta = final - sum[all[i].second]; long long rep = v + delta; rp[i] = -1; if (abs(rep) <= 1000000000 && delta != 0) { auto pos = lower_bound(all.begin(), all.end(), make_pair<int, int>((int)rep, 0)); if (pos != all.end() && pos->first == rep && pos->second != all[i].second) rp[i] = pos - all.begin(); } } for (int i = 0; i < n; ++i) { if (rp[i] != -1) { int mask = (1 << all[i].second); int p = rp[i]; while (p >= 0 && (mask & (1 << all[p].second)) == 0) { mask |= (1 << all[p].second); p = rp[p]; } if (p == i) { loops.push_back(make_pair(mask, i)); } } } sort(loops.begin(), loops.end()); loops.erase(unique(loops.begin(), loops.end()), loops.end()); finstate = (1 << k) - 1; if (dfs(okmask, 0)) { int moveTo[15]; int val[15]; for (int i = 0; i < k; i++) { moveTo[i] = i; val[i] = a[i][0]; } if (a[0][0] == -174529428) { cout << okmask = << okmask << endl; for (int i = 0; i < plen; i++) { cout << mask = << loops[path[i]].first << endl; } } for (int i = 0; i < plen; i++) { int p0 = loops[path[i]].second; int from = p0; int p = rp[from]; while (p != p0) { int grp = all[p].second; moveTo[grp] = all[from].second; val[grp] = all[p].first; from = p; p = rp[from]; } int sg = all[p].second; moveTo[sg] = all[from].second; val[sg] = all[p].first; } cout << Yes << endl; for (int i = 0; i < k; i++) { cout << val[i] << << (moveTo[i] + 1) << endl; } } else { cout << No << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; inline int Find(string x) { if (x == rock ) return 1; if (x == scissors ) return 2; if (x == paper ) return 3; } int main() { string a, b, c; int sa, sb, sc; cin >> a >> b >> c; sa = Find(a), sb = Find(b), sc = Find(c); if (sa == 1 && sb == 2 && sc == 2) printf( F ); else if (sa == 2 && sb == 3 && sc == 3) printf( F ); else if (sa == 3 && sb == 1 && sc == 1) printf( F ); else if (sa == 2 && sb == 1 && sc == 2) printf( M ); else if (sa == 3 && sb == 2 && sc == 3) printf( M ); else if (sa == 1 && sb == 3 && sc == 1) printf( M ); else if (sa == 2 && sb == 2 && sc == 1) printf( S ); else if (sa == 3 && sb == 3 && sc == 2) printf( S ); else if (sa == 1 && sb == 1 && sc == 3) printf( S ); else printf( ? ); return 0; } |
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module rw_manager_ddr3 (
// Avalon Interface
avl_clk,
avl_reset_n,
avl_address,
avl_write,
avl_writedata,
avl_read,
avl_readdata,
avl_waitrequest,
// AFI Interface
afi_clk,
afi_reset_n,
afi_address,
afi_bank,
afi_cs_n,
afi_cke,
afi_odt,
afi_ras_n,
afi_cas_n,
afi_we_n,
afi_dqs_en,
afi_mem_reset_n,
afi_wdata,
afi_wdata_valid,
afi_dm,
afi_rdata_en,
afi_rdata_en_full,
afi_rdata,
afi_rdata_valid,
csr_clk,
csr_ena,
csr_dout_phy,
csr_dout
);
parameter AVL_DATA_WIDTH = 32;
parameter AVL_ADDR_WIDTH = 16;
parameter MEM_ADDRESS_WIDTH = 19;
parameter MEM_CONTROL_WIDTH = 4;
parameter MEM_DQ_WIDTH = 36;
parameter MEM_DM_WIDTH = 4;
parameter MEM_NUMBER_OF_RANKS = 1;
parameter MEM_CLK_EN_WIDTH = 1;
parameter MEM_BANK_WIDTH = 2;
parameter MEM_ODT_WIDTH = 2;
parameter MEM_CHIP_SELECT_WIDTH = 1;
parameter MEM_READ_DQS_WIDTH = 4;
parameter MEM_WRITE_DQS_WIDTH = 4;
parameter AFI_RATIO = 2;
parameter RATE = "Half";
parameter HCX_COMPAT_MODE = 0;
parameter DEVICE_FAMILY = "STRATIXIV";
parameter AC_ROM_INIT_FILE_NAME = "AC_ROM.hex";
parameter INST_ROM_INIT_FILE_NAME = "inst_ROM.hex";
input avl_clk;
input avl_reset_n;
input [AVL_ADDR_WIDTH-1:0] avl_address;
input avl_write;
input [AVL_DATA_WIDTH-1:0] avl_writedata;
input avl_read;
output [AVL_DATA_WIDTH-1:0] avl_readdata;
output avl_waitrequest;
input afi_clk;
input afi_reset_n;
output [MEM_ADDRESS_WIDTH * AFI_RATIO - 1:0] afi_address;
output [MEM_BANK_WIDTH * AFI_RATIO - 1:0] afi_bank;
output [MEM_CHIP_SELECT_WIDTH * AFI_RATIO - 1:0] afi_cs_n;
output [MEM_CLK_EN_WIDTH * AFI_RATIO - 1:0] afi_cke;
output [MEM_ODT_WIDTH * AFI_RATIO - 1:0] afi_odt;
output [MEM_CONTROL_WIDTH * AFI_RATIO - 1:0] afi_ras_n;
output [MEM_CONTROL_WIDTH * AFI_RATIO - 1:0] afi_cas_n;
output [MEM_CONTROL_WIDTH * AFI_RATIO - 1:0] afi_we_n;
output [MEM_WRITE_DQS_WIDTH * AFI_RATIO - 1:0] afi_dqs_en;
output [MEM_CONTROL_WIDTH * AFI_RATIO - 1:0] afi_mem_reset_n;
output [MEM_DQ_WIDTH * 2 * AFI_RATIO - 1:0] afi_wdata;
output [MEM_WRITE_DQS_WIDTH * AFI_RATIO - 1:0] afi_wdata_valid;
output [MEM_DM_WIDTH * 2 * AFI_RATIO - 1:0] afi_dm;
output afi_rdata_en;
output afi_rdata_en_full;
input [MEM_DQ_WIDTH * 2 * AFI_RATIO - 1:0] afi_rdata;
input afi_rdata_valid;
input csr_clk;
input csr_ena;
input csr_dout_phy;
output csr_dout;
parameter AC_BUS_WIDTH = 30;
wire [AC_BUS_WIDTH - 1:0] ac_bus;
rw_manager_generic rw_mgr_inst (
.avl_clk(avl_clk),
.avl_reset_n(avl_reset_n),
.avl_address(avl_address),
.avl_write(avl_write),
.avl_writedata(avl_writedata),
.avl_read(avl_read),
.avl_readdata(avl_readdata),
.avl_waitrequest(avl_waitrequest),
.afi_clk(afi_clk),
.afi_reset_n(afi_reset_n),
.ac_masked_bus (afi_cs_n),
.ac_bus (ac_bus),
.afi_wdata(afi_wdata),
.afi_dm(afi_dm),
.afi_odt(afi_odt),
.afi_rdata(afi_rdata),
.afi_rdata_valid(afi_rdata_valid),
.csr_clk(csr_clk),
.csr_ena(csr_ena),
.csr_dout_phy(csr_dout_phy),
.csr_dout(csr_dout)
);
defparam rw_mgr_inst.AVL_DATA_WIDTH = AVL_DATA_WIDTH;
defparam rw_mgr_inst.AVL_ADDRESS_WIDTH = AVL_ADDR_WIDTH;
defparam rw_mgr_inst.MEM_DQ_WIDTH = MEM_DQ_WIDTH;
defparam rw_mgr_inst.MEM_DM_WIDTH = MEM_DM_WIDTH;
defparam rw_mgr_inst.MEM_ODT_WIDTH = MEM_ODT_WIDTH;
defparam rw_mgr_inst.AC_BUS_WIDTH = AC_BUS_WIDTH;
defparam rw_mgr_inst.AC_MASKED_BUS_WIDTH = MEM_CHIP_SELECT_WIDTH * AFI_RATIO;
defparam rw_mgr_inst.MASK_WIDTH = MEM_CHIP_SELECT_WIDTH;
defparam rw_mgr_inst.AFI_RATIO = AFI_RATIO;
defparam rw_mgr_inst.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
defparam rw_mgr_inst.MEM_WRITE_DQS_WIDTH = MEM_WRITE_DQS_WIDTH;
defparam rw_mgr_inst.RATE = RATE;
defparam rw_mgr_inst.HCX_COMPAT_MODE = HCX_COMPAT_MODE;
defparam rw_mgr_inst.DEVICE_FAMILY = DEVICE_FAMILY;
defparam rw_mgr_inst.DEBUG_READ_DI_WIDTH = 32;
defparam rw_mgr_inst.DEBUG_WRITE_TO_READ_RATIO_2_EXPONENT = 0;
defparam rw_mgr_inst.AC_ROM_INIT_FILE_NAME = AC_ROM_INIT_FILE_NAME;
defparam rw_mgr_inst.INST_ROM_INIT_FILE_NAME = INST_ROM_INIT_FILE_NAME;
defparam rw_mgr_inst.AC_ODT_BIT =
(AFI_RATIO == 4) ? 27 : // Quarter-rate
(AFI_RATIO == 2) ? 25 : // Half-rate
24; // Full-rate
generate
begin
if (AFI_RATIO == 4) begin
assign afi_address = {AFI_RATIO{ {(MEM_ADDRESS_WIDTH-13){1'b0}}, ac_bus[12:0] }};
assign afi_bank = {AFI_RATIO{ac_bus[15:13]}};
assign afi_mem_reset_n = {(MEM_CONTROL_WIDTH * AFI_RATIO){ac_bus[16]}};
assign afi_ras_n = {(MEM_CONTROL_WIDTH * AFI_RATIO){ac_bus[17]}};
assign afi_cas_n = {(MEM_CONTROL_WIDTH * AFI_RATIO){ac_bus[18]}};
assign afi_we_n = {(MEM_CONTROL_WIDTH * AFI_RATIO){ac_bus[19]}};
assign afi_dqs_en = {{(MEM_WRITE_DQS_WIDTH * AFI_RATIO / 4){ac_bus[23]}},
{(MEM_WRITE_DQS_WIDTH * AFI_RATIO / 4){ac_bus[22]}},
{(MEM_WRITE_DQS_WIDTH * AFI_RATIO / 4){ac_bus[21]}},
{(MEM_WRITE_DQS_WIDTH * AFI_RATIO / 4){ac_bus[20]}}};
assign afi_rdata_en_full = ac_bus[24];
assign afi_rdata_en = ac_bus[25];
assign afi_wdata_valid = {MEM_WRITE_DQS_WIDTH * AFI_RATIO{ac_bus[26]}};
assign afi_cke = {(MEM_CLK_EN_WIDTH * AFI_RATIO){ac_bus[28]}};
end else if (AFI_RATIO == 2) begin
assign afi_address = {AFI_RATIO{ {(MEM_ADDRESS_WIDTH-13){1'b0}}, ac_bus[12:0] }};
assign afi_bank = {AFI_RATIO{ac_bus[15:13]}};
assign afi_mem_reset_n = {(MEM_CONTROL_WIDTH * AFI_RATIO){ac_bus[16]}};
assign afi_ras_n = {(MEM_CONTROL_WIDTH * AFI_RATIO){ac_bus[17]}};
assign afi_cas_n = {(MEM_CONTROL_WIDTH * AFI_RATIO){ac_bus[18]}};
assign afi_we_n = {(MEM_CONTROL_WIDTH * AFI_RATIO){ac_bus[19]}};
assign afi_dqs_en = {{(MEM_WRITE_DQS_WIDTH * AFI_RATIO / 2){ac_bus[21]}}, {(MEM_WRITE_DQS_WIDTH * AFI_RATIO / 2){ac_bus[20]}}};
assign afi_rdata_en_full = ac_bus[22];
assign afi_rdata_en = ac_bus[23];
assign afi_wdata_valid = {MEM_WRITE_DQS_WIDTH * AFI_RATIO{ac_bus[24]}};
assign afi_cke = {(MEM_CLK_EN_WIDTH * AFI_RATIO){ac_bus[26]}};
end else begin
assign afi_address = {AFI_RATIO{ {(MEM_ADDRESS_WIDTH-13){1'b0}}, ac_bus[12:0] }};
assign afi_bank = {AFI_RATIO{ac_bus[15:13]}};
assign afi_mem_reset_n = {(MEM_CONTROL_WIDTH * AFI_RATIO){ac_bus[16]}};
assign afi_ras_n = {(MEM_CONTROL_WIDTH * AFI_RATIO){ac_bus[17]}};
assign afi_cas_n = {(MEM_CONTROL_WIDTH * AFI_RATIO){ac_bus[18]}};
assign afi_we_n = {(MEM_CONTROL_WIDTH * AFI_RATIO){ac_bus[19]}};
assign afi_dqs_en = {MEM_WRITE_DQS_WIDTH * AFI_RATIO{ac_bus[20]}};
assign afi_rdata_en_full = ac_bus[21];
assign afi_rdata_en = ac_bus[22];
assign afi_wdata_valid = {MEM_WRITE_DQS_WIDTH * AFI_RATIO{ac_bus[23]}};
assign afi_cke = {(MEM_CLK_EN_WIDTH * AFI_RATIO){ac_bus[25]}};
end
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> A(n), B(n); vector<int> Ai(n - 1), Bi(n - 1); int t = 0; for (int i = 0; i < n; ++i) { cin >> A[i]; if (A[i] != 0) { Ai[t] = A[i]; t++; } } t = 0; for (int i = 0; i < n; ++i) { cin >> B[i]; if (B[i] != 0) { Bi[t] = B[i]; t++; } } int i0 = 0; for (int i = 0; i < n - 1; ++i) { if (Bi[i] == Ai[0]) { i0 = i; break; } } for (int i = 0; i < n - 1; ++i) { if (Bi[(i + i0) % (n - 1)] != Ai[i]) { cout << NO << endl; return 0; } } cout << YES << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { char a; cin >> a; string str1, str2; cin >> str1 >> str2; int b1, b2; switch (str1[0]) { case T : b1 = 10; break; case J : b1 = 11; break; case Q : b1 = 12; break; case K : b1 = 13; break; case A : b1 = 14; break; default: b1 = str1[0] - 0 ; } switch (str2[0]) { case T : b2 = 10; break; case J : b2 = 11; break; case Q : b2 = 12; break; case K : b2 = 13; break; case A : b2 = 14; break; default: b2 = str2[0] - 0 ; } if (str1[1] == a) if (str2[1] != str1[1]) { cout << YES ; } else { if (b1 > b2) { cout << YES ; } else cout << NO ; } else { if (str2[1] == str1[1]) { if (b1 > b2) { cout << YES ; } else cout << NO ; } else { cout << NO ; }; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 3e5 + 5; const int maxm = 305; long long a[maxn]; long long c[11][maxn]; long long num[maxn]; long long n, m, v, k; int main() { cin >> n >> m >> k; for (int i = 0; i < n; i++) { cin >> a[i]; } sort(a, a + n); long long ans = 0; ans += (a[n - 1] * k + a[n - 2]) * (m / (k + 1)); long long mod = m % (k + 1); ans += (a[n - 1]) * mod; cout << ans << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFRTP_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__DFRTP_PP_BLACKBOX_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dfrtp (
Q ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFRTP_PP_BLACKBOX_V
|
// --------------------------------------------------
//
// Fake implementation specific memory
//
// Sample implementation specific memory with test ports
// and 2-clock delay on output after read-enable asserted.
//
// --------------------------------------------------
module mem_16nm_ram4x64
(
input wire clk,
input wire mem_wr_en,
input wire [1:0] mem_wr_addr,
input wire [63:0] mem_wr_data,
input wire mem_rd_en,
input wire [1:0] mem_rd_addr,
output wire [63:0] mem_rd_data,
input wire bist_clk,
input wire bist_en,
input wire [1:0] bist_addr,
input wire [63:0] bist_wr_data,
output wire [63:0] bist_rd_data
);
// The memory declaration
reg [63:0] memory [3:0];
reg [63:0] mem_rd_data_i;
always @ (posedge clk) begin
if( mem_wr_en ) begin
memory[mem_wr_addr] <= #0 mem_wr_data;
end
if( mem_rd_en ) begin
mem_rd_data_i <= #0 memory[mem_rd_addr];
end
end
always @ (posedge clk) begin
mem_rd_data <= #0 mem_rd_data_i;
end
// Bist fake logic
always @ (posedge bist_clk ) begin
bist_rd_data <= #0 bist_wr_data;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, m; cin >> n >> m; string a, b; cin >> a >> b; if (a.size() - 1 > b.size()) { cout << NO n ; return 0; } if (a == b) { cout << YES n ; return 0; } int l = 0, r = m - 1; while (a[l] == b[l] && l < min(n, m)) l++; while (a.back() == b.back() && min(a.size(), b.size()) > l) a.pop_back(), b.pop_back(); if (a.size() - l == 1 && a.back() == * ) { cout << YES ; } else { cout << NO n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAX = 1e5 + 10; int T, N; int a[MAX]; int main() { scanf( %d , &T); while (T--) { scanf( %d , &N); for (int i = 1; i <= N; i++) scanf( %d , &a[i]); sort(a + 1, a + 1 + N); int l = (N + 1) / 2, r = (N + 1) / 2; printf( %d , a[l]); for (int i = 1; i < N; i++) { if (i & 1) printf( %d , a[++r]); else printf( %d , a[--l]); } printf( n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; long long int ans[100000]; int main() { long long int n, m, mx, mn, i, j, k, diff, flag = 0, flag1 = 0, flag2 = 0; cin >> n >> m >> mn >> mx; long long int arr[m + 5]; for (i = 0; i < m; i++) { cin >> arr[i]; if (arr[i] == mn) flag1 = 1; if (arr[i] == mx) flag2 = 1; if (arr[i] < mn || arr[i] > mx) flag = 1; } diff = n - m; if (flag == 1) cout << Incorrect << endl; else if (flag1 == 1 && flag2 == 1) cout << Correct << endl; else if (flag1 == 1 && diff >= 1 || flag2 == 1 && diff >= 1) cout << Correct << endl; else if (flag1 == 0 && flag2 == 0 && diff >= 2) cout << Correct << endl; else cout << Incorrect << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxLog = 10; const int maxN = 1 << maxLog; const int INF = 0x3c3c3c3c; int f[333]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n; cin >> n; string s; cin >> s; vector<int> a(n); f[ > ] = 1; f[ < ] = -1; for (auto &x : a) { cin >> x; } int v = 0; for (int i = 0; i < n * 2 + 2; i++) { int j = f[s[v]] * a[v]; v += j; if (!(0 <= v && v < n)) { cout << FINITE << endl; return 0; } } cout << INFINITE << endl; return 0; } |
///////////////////////////////////////////////////////////////////////////////
// vim:set shiftwidth=3 softtabstop=3 expandtab:
// $Id: udp_reg_master.v 1965 2007-07-18 01:24:21Z grg $
//
// Module: udp_reg_master.v
// Project: NetFPGA
// Description: User data path register master
//
// Note: Set TIMEOUT_RESULT to specify the return value on timeout.
// This can be used to identify broken rings.
//
// Result: ack_in -> data_in
// timeout -> TIMEOUT_RESULT
// loop complete && !ack_in -> deadbeef
//
///////////////////////////////////////////////////////////////////////////////
module udp_reg_master
#(
parameter TABLE_NUM = 1
)
(
input reg_req_in ,
input reg_rd_wr_L_in ,
input [31:0] reg_addr_in ,
input [31:0] reg_data_in ,
output reg [31:0] reg_rd_data ,
output reg reg_ack ,
input clk ,
input reset ,
output [31:0] data_output_port_lookup_o ,
/*output [31:0] data_output_port_lookup_1_o ,
output [31:0] data_output_port_lookup_2_o ,*/
output [31:0] data_meter_o ,
output [31:0] data_output_queues_o ,
output [31:0] data_config_o ,
output [31:0] addr_output_port_lookup_o ,
/*output [31:0] addr_output_port_lookup_1_o ,
output [31:0] addr_output_port_lookup_2_o ,*/
output [31:0] addr_meter_o ,
output [31:0] addr_output_queues_o ,
output [31:0] addr_config_o ,
output req_output_port_lookup_o ,
/*output req_output_port_lookup_1_o ,
output req_output_port_lookup_2_o ,*/
output req_meter_o ,
output req_output_queues_o ,
output req_config_o ,
output rw_output_port_lookup_o ,
/*output rw_output_port_lookup_1_o ,
output rw_output_port_lookup_2_o ,*/
output rw_meter_o ,
output rw_output_queues_o ,
output rw_config_o ,
input ack_output_port_lookup_i ,
/*input ack_output_port_lookup_1_i ,
input ack_output_port_lookup_2_i ,*/
input ack_meter_i ,
input ack_output_queues_i ,
input ack_config_i ,
input [31:0] data_output_port_lookup_i ,
/*input [31:0] data_output_port_lookup_1_i ,
input [31:0] data_output_port_lookup_2_i ,*/
input [31:0] data_meter_i ,
input [31:0] data_output_queues_i ,
input [31:0] data_config_i
);
assign data_output_port_lookup_o = reg_data_in ;
/*assign data_output_port_lookup_1_o = reg_data_in ;
assign data_output_port_lookup_2_o = reg_data_in ;*/
assign data_meter_o = reg_data_in ;
assign data_output_queues_o = reg_data_in ;
assign data_config_o = reg_data_in ;
assign addr_output_port_lookup_o = reg_addr_in ;
/*assign addr_output_port_lookup_1_o = reg_addr_in ;
assign addr_output_port_lookup_2_o = reg_addr_in ;*/
assign addr_meter_o = reg_addr_in;
assign addr_output_queues_o = reg_addr_in;
assign addr_config_o = reg_addr_in ;
assign req_output_port_lookup_o = (reg_addr_in[`MODULE_ID_POS+`MODULE_ID_WIDTH-1:`MODULE_ID_POS]==`OUTPUT_PORT_LOOKUP_TAG && reg_addr_in[`TABLE_ID_POS+`TABLE_ID_WIDTH-1:`TABLE_ID_POS]<=TABLE_NUM) ? reg_req_in : 0;
/*assign req_output_port_lookup_1_o = (reg_addr_in[`MODULE_ID_POS+`MODULE_ID_WIDTH-1:`MODULE_ID_POS]==`OUTPUT_PORT_LOOKUP_TAG && reg_addr_in[`TABLE_ID_POS+`TABLE_ID_WIDTH-1:`TABLE_ID_POS]==1) ? reg_req_in : 0;
assign req_output_port_lookup_2_o = (reg_addr_in[`MODULE_ID_POS+`MODULE_ID_WIDTH-1:`MODULE_ID_POS]==`OUTPUT_PORT_LOOKUP_TAG && reg_addr_in[`TABLE_ID_POS+`TABLE_ID_WIDTH-1:`TABLE_ID_POS]==2) ? reg_req_in : 0; */
assign req_meter_o = (reg_addr_in[`MODULE_ID_POS+`MODULE_ID_WIDTH-1:`MODULE_ID_POS]==`METER_TAG) ? reg_req_in : 0;
assign req_output_queues_o = (reg_addr_in[`MODULE_ID_POS+`MODULE_ID_WIDTH-1:`MODULE_ID_POS]==`QOS_TAG) ? reg_req_in : 0;
assign req_config_o = (reg_addr_in[`MODULE_ID_POS+`MODULE_ID_WIDTH-1:`MODULE_ID_POS]==`CONFIG) ? reg_req_in : 0;
assign rw_output_port_lookup_o = reg_rd_wr_L_in;
/*assign rw_output_port_lookup_1_o = reg_rd_wr_L_in;
assign rw_output_port_lookup_2_o = reg_rd_wr_L_in; */
assign rw_meter_o = reg_rd_wr_L_in;
assign rw_output_queues_o = reg_rd_wr_L_in;
assign rw_config_o = reg_rd_wr_L_in;
reg [2:0]ack_state;
always@(posedge clk)
if(reset)
ack_state<=0;
else case(ack_state)
0:if(req_output_port_lookup_o | req_meter_o | req_output_queues_o | req_config_o) ack_state<=1;//| req_output_port_lookup_1_o | req_output_port_lookup_2_o
else if(reg_req_in) ack_state<=3;
1:if(ack_output_port_lookup_i | ack_meter_i | ack_output_queues_i | ack_config_i) ack_state<=2;
2:ack_state<=0;
3:ack_state<=0;
default:ack_state<=0;
endcase
always@(posedge clk)
if(reset)
reg_ack <= 0;
else if(ack_state==2 | ack_state==3)
reg_ack<=1;
else reg_ack<=0;
always@(posedge clk)
if(reset)
reg_rd_data<=0;
else if(ack_state==1)
begin
if(ack_output_port_lookup_i) reg_rd_data <= data_output_port_lookup_i;
/*else if(ack_output_port_lookup_1_i) reg_rd_data <= data_output_port_lookup_1_i;
else if(ack_output_port_lookup_2_i) reg_rd_data <= data_output_port_lookup_2_i;*/
else if(ack_meter_i) reg_rd_data <= data_meter_i;
else if(ack_output_queues_i) reg_rd_data <= data_output_queues_i;
else if(ack_config_i) reg_rd_data <= data_config_i;
end
else if(ack_state==3) reg_rd_data<=32'hdeadbeef;
endmodule // unused_reg |
#include <bits/stdc++.h> using namespace std; int n; double r, v; double a, b; bool check(double l) { double arfa = l / r; double A = r * (1 - cos(arfa)); double B = r * sin(arfa); return l + sqrt(A * A + B * B) >= b - a; } int main() { cin >> n >> r >> v; while (n--) { scanf( %lf%lf , &a, &b); double l = 0, r = b - a, ans; for (int i = 1; i <= 100; i++) { double mid = (l + r) / 2.0; if (check(mid)) ans = mid, r = mid; else l = mid; } printf( %.10f n , ans / v); } return 0; } |
module ghrd_10as066n2_pb_lwh2f #(
parameter DATA_WIDTH = 32,
parameter SYMBOL_WIDTH = 8,
parameter HDL_ADDR_WIDTH = 12,
parameter BURSTCOUNT_WIDTH = 1,
parameter PIPELINE_COMMAND = 1,
parameter PIPELINE_RESPONSE = 1
) (
input wire clk, // clk.clk
input wire m0_waitrequest, // m0.waitrequest
input wire [DATA_WIDTH-1:0] m0_readdata, // .readdata
input wire m0_readdatavalid, // .readdatavalid
output wire [BURSTCOUNT_WIDTH-1:0] m0_burstcount, // .burstcount
output wire [DATA_WIDTH-1:0] m0_writedata, // .writedata
output wire [HDL_ADDR_WIDTH-1:0] m0_address, // .address
output wire m0_write, // .write
output wire m0_read, // .read
output wire [3:0] m0_byteenable, // .byteenable
output wire m0_debugaccess, // .debugaccess
input wire reset, // reset.reset
output wire s0_waitrequest, // s0.waitrequest
output wire [DATA_WIDTH-1:0] s0_readdata, // .readdata
output wire s0_readdatavalid, // .readdatavalid
input wire [BURSTCOUNT_WIDTH-1:0] s0_burstcount, // .burstcount
input wire [DATA_WIDTH-1:0] s0_writedata, // .writedata
input wire [HDL_ADDR_WIDTH-1:0] s0_address, // .address
input wire s0_write, // .write
input wire s0_read, // .read
input wire [3:0] s0_byteenable, // .byteenable
input wire s0_debugaccess // .debugaccess
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long total = 0; struct c { int can; int tru; }; int main() { double a, b, c; scanf( %lf%lf%lf , &a, &b, &c); printf( %.100f n , a * (b) / (b + c)); } |
#include <bits/stdc++.h> using namespace std; char s[100005]; struct node { int x, op; } a[100005]; bool cmp(node q, node w) { return q.x < w.x; } int cnt; bool vis[100005]; int main() { int now, len, i; scanf( %d , &now); scanf( %s , s + 1); len = strlen(s + 1); s[0] = + ; for (i = 1; i <= len; i++) { if (s[i] == a ) { cnt++; vis[i] = 1; if (i > 2 && s[i - 1] == + && s[i - 2] == + && !vis[i - 1] && !vis[i - 2]) { a[cnt].op = 1; vis[i - 1] = 1; vis[i - 2] = 1; if (s[i - 3] == + ) a[cnt].x = 1; else if (s[i - 3] == - ) a[cnt].x = -1; else if (s[i - 3] == * ) { a[cnt].x = 0; int j, flg = 1; for (j = i - 4; j >= 1; j--) if (s[j] < 0 || s[j] > 9 ) { if (s[j] == - ) flg = -1; break; } for (j++; j <= i - 4; j++) a[cnt].x = 10 * a[cnt].x + s[j] - 48; a[cnt].x *= flg; } } else if (s[i + 1] == + && s[i + 2] == + && !vis[i + 1] && !vis[i + 2]) { a[cnt].op = 0; vis[i + 1] = 1; vis[i + 2] = 1; if (s[i - 1] == + ) a[cnt].x = 1; else if (s[i - 1] == - ) a[cnt].x = -1; else if (s[i - 1] == * ) { a[cnt].x = 0; int j, flg = 1; for (j = i - 2; j >= 1; j--) if (s[j] < 0 || s[j] > 9 ) { if (s[j] == - ) flg = -1; break; } for (j++; j <= i - 2; j++) a[cnt].x = 10 * a[cnt].x + s[j] - 48; a[cnt].x *= flg; } } } } sort(a + 1, a + cnt + 1, cmp); long long ans = 0; for (i = 1; i <= cnt; i++) { if (a[i].op == 1) { now++; ans = 1ll * ans + 1ll * now * a[i].x; } else { ans = 1ll * ans + 1ll * now * a[i].x; now++; } } printf( %I64d , ans); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2111OI_4_V
`define SKY130_FD_SC_LP__A2111OI_4_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog wrapper for a2111oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a2111oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2111oi_4 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a2111oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2111oi_4 (
Y ,
A1,
A2,
B1,
C1,
D1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a2111oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2111OI_4_V
|
// file: Clk_Wizard.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// VGA_clock___108.025______0.000______50.0______144.053____157.495
// Main_clock____99.432______0.000______50.0______146.499____157.495
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
module Clk_Wizard_clk_wiz
(// Clock in ports
// Clock out ports
output VGA_clock,
output Main_clock,
// Status and control signals
input resetn,
output locked,
input Clock_Board
);
// Input buffering
//------------------------------------
wire Clock_Board_Clk_Wizard;
wire clk_in2_Clk_Wizard;
IBUF clkin1_ibufg
(.O (Clock_Board_Clk_Wizard),
.I (Clock_Board));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire VGA_clock_Clk_Wizard;
wire Main_clock_Clk_Wizard;
wire clk_out3_Clk_Wizard;
wire clk_out4_Clk_Wizard;
wire clk_out5_Clk_Wizard;
wire clk_out6_Clk_Wizard;
wire clk_out7_Clk_Wizard;
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_Clk_Wizard;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
wire reset_high;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (2),
.CLKFBOUT_MULT_F (21.875),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (10.125),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (11),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (10.0))
mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_Clk_Wizard),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (VGA_clock_Clk_Wizard),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (Main_clock_Clk_Wizard),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_Clk_Wizard),
.CLKIN1 (Clock_Board_Clk_Wizard),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_int),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (reset_high));
assign reset_high = ~resetn;
assign locked = locked_int;
// Clock Monitor clock assigning
//--------------------------------------
// Output buffering
//-----------------------------------
BUFG clkout1_buf
(.O (VGA_clock),
.I (VGA_clock_Clk_Wizard));
BUFG clkout2_buf
(.O (Main_clock),
.I (Main_clock_Clk_Wizard));
endmodule
|
// This top level module chooses between the original Altera-ST JTAG Interface
// component in ACDS version 8.1 and before, and the new one with the PLI
// Simulation mode turned on, which adds a wrapper over the original component.
`timescale 1 ns / 1 ns
module altera_avalon_st_jtag_interface (
clk,
reset_n,
source_ready,
source_data,
source_valid,
sink_data,
sink_valid,
sink_ready,
resetrequest,
debug_reset,
mgmt_valid,
mgmt_channel,
mgmt_data
);
input clk;
input reset_n;
output [7:0] source_data;
input source_ready;
output source_valid;
input [7:0] sink_data;
input sink_valid;
output sink_ready;
output resetrequest;
output debug_reset;
output mgmt_valid;
output mgmt_data;
parameter PURPOSE = 0; // for discovery of services behind this JTAG Phy - 0
// for JTAG Phy, 1 for Packets to Master
parameter UPSTREAM_FIFO_SIZE = 0;
parameter DOWNSTREAM_FIFO_SIZE = 0;
parameter MGMT_CHANNEL_WIDTH = -1;
parameter USE_PLI = 0; // set to 1 enable PLI Simulation Mode
parameter PLI_PORT = 50000; // PLI Simulation Port
output [(MGMT_CHANNEL_WIDTH>0?MGMT_CHANNEL_WIDTH:1)-1:0] mgmt_channel;
wire clk;
wire resetrequest;
wire [7:0] source_data;
wire source_ready;
wire source_valid;
wire [7:0] sink_data;
wire sink_valid;
wire sink_ready;
generate
if (USE_PLI == 0)
begin : normal
altera_jtag_dc_streaming #(
.PURPOSE(PURPOSE),
.UPSTREAM_FIFO_SIZE(UPSTREAM_FIFO_SIZE),
.DOWNSTREAM_FIFO_SIZE(DOWNSTREAM_FIFO_SIZE),
.MGMT_CHANNEL_WIDTH(MGMT_CHANNEL_WIDTH)
) jtag_dc_streaming (
.clk(clk),
.reset_n(reset_n),
.source_data(source_data),
.source_valid(source_valid),
.sink_data(sink_data),
.sink_valid(sink_valid),
.sink_ready(sink_ready),
.resetrequest(resetrequest),
.debug_reset(debug_reset),
.mgmt_valid(mgmt_valid),
.mgmt_channel(mgmt_channel),
.mgmt_data(mgmt_data)
);
end
else
begin : pli_mode
altera_pli_streaming #(.PURPOSE(PURPOSE), .PLI_PORT(PLI_PORT)) pli_streaming (
.clk(clk),
.reset_n(reset_n),
.source_data(source_data),
.source_valid(source_valid),
.source_ready(source_ready),
.sink_data(sink_data),
.sink_valid(sink_valid),
.sink_ready(sink_ready),
.resetrequest(resetrequest)
);
end
endgenerate
endmodule
|
module ball_logic( input pxl_clk,
input reset_n,
input vsync,
input h_collision,
input v_collision,
input start,
output reg [9:0] ball_x,
output reg [9:0] ball_y );
`include "defines.v"
parameter down_right = 3'b000;
parameter down_left = 3'b001;
parameter up_right = 3'b010;
parameter up_left = 3'b011;
parameter stop = 3'b100;
reg drawn;
reg [2:0] ball_state;
reg [2:0] next_ball_state;
always @ (posedge pxl_clk or negedge reset_n)
begin : ball_logic
if (!reset_n)
begin
drawn <= 1;
//lose <= 0;
ball_y <= 240;
ball_x <= 260;
end
else if (!vsync && !drawn)
begin
drawn <= 1;
case(ball_state)
stop:
begin
ball_x <= ball_x;
ball_y <= ball_y;
end
down_right:
begin
ball_x <= ball_x + 2'd1;
ball_y <= ball_y + 2'd2;
end
down_left:
begin
ball_x <= ball_x - 2'd1;
ball_y <= ball_y + 2'd2;
end
up_right:
begin
ball_x <= ball_x + 2'd1;
ball_y <= ball_y - 2'd2;
end
up_left:
begin
ball_x <= ball_x - 2'd1;
ball_y <= ball_y - 2'd2;
end
default:
begin
ball_x <= ball_x + 2'd1;
ball_y <= ball_y + 2'd2;
end
endcase
end
else if (vsync && drawn)
begin
drawn <= 0;
end
end
always @ (posedge pxl_clk or negedge reset_n)
begin : register_generation
if (!reset_n) ball_state <= stop;
else ball_state <= next_ball_state;
end
always @ (ball_state or ball_x or ball_y or h_collision or v_collision or start)
begin
case (ball_state)
stop:
begin
if (start == 1) next_ball_state <= down_right;
else next_ball_state <= stop;
end
down_right:
begin
if (ball_y >= `bottom_edge) next_ball_state <= up_right;
else if (ball_x >= `right_edge) next_ball_state <= down_left;
else if (v_collision) next_ball_state <= up_right;
else if (h_collision) next_ball_state <= down_left;
else next_ball_state <= down_right;
end
down_left:
begin
if (ball_y >= `bottom_edge) next_ball_state <= up_left;
else if (ball_x <= `left_edge) next_ball_state <= down_right;
else if (v_collision) next_ball_state <= up_left;
else if (h_collision) next_ball_state <= down_right;
else next_ball_state <= down_left;
end
up_right:
begin
if (ball_y <= `top_edge) next_ball_state <= down_right;
else if (ball_x >= `right_edge) next_ball_state <= up_left;
else if (v_collision) next_ball_state <= down_right;
else if (h_collision) next_ball_state <= up_left;
else next_ball_state <= up_right;
end
up_left:
begin
if (ball_y <= `top_edge) next_ball_state <= down_left;
else if (ball_x <= `left_edge) next_ball_state <= up_right;
else if (v_collision) next_ball_state <= down_left;
else if (h_collision) next_ball_state <= up_right;
else next_ball_state <= up_left;
end
endcase
end
endmodule
|
//Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2015.1 (lin64) Build Mon Apr 27 19:07:21 MDT 2015
//Date : Fri Jun 5 14:04:18 2015
//Host : ubuntu running 64-bit Ubuntu 14.04.2 LTS
//Command : generate_target design_1_wrapper.bd
//Design : design_1_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module design_1_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
design_1 design_1_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb));
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; const long long SIZE = 100000; const int INF = 0x3f3f3f3f; const long long ll_INF = 0x3f3f3f3f3f3f3f3f; const long double PI = acos(-1); const long long MAXN = numeric_limits<long long>::max(); const long long MAX = 2000000; void disp(vector<long long> v) { for (auto u : v) cout << u << ; cout << n ; } void solve() { long long l, r, x = 0, y = 1, temp, ans = 0; cin >> l >> r; y = 1; while (y <= r) { temp = y; if (temp >= l && temp <= r) ans++; while (temp <= r) { temp *= 2; if (temp >= l && temp <= r) ans++; } y *= 3; } cout << ans; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); solve(); return 0; } |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ps
module ad_gt_common_1 (
// reset and clocks
rst,
ref_clk,
qpll_clk,
qpll_ref_clk,
qpll_locked,
// drp interface
drp_clk,
drp_en,
drp_addr,
drp_wr,
drp_wdata,
drp_rdata,
drp_ready);
// parameters
parameter QPLL_REFCLK_DIV = 2;
parameter QPLL_CFG = 27'h06801C1;
parameter QPLL_FBDIV_RATIO = 1'b1;
parameter QPLL_FBDIV = 10'b0000110000;
// reset and clocks
input rst;
input ref_clk;
output qpll_clk;
output qpll_ref_clk;
output qpll_locked;
// drp interface
input drp_clk;
input drp_en;
input [11:0] drp_addr;
input drp_wr;
input [15:0] drp_wdata;
output [15:0] drp_rdata;
output drp_ready;
// instantiations
GTXE2_COMMON #(
.SIM_RESET_SPEEDUP ("TRUE"),
.SIM_QPLLREFCLK_SEL (3'b001),
.SIM_VERSION ("3.0"),
.BIAS_CFG (64'h0000040000001000),
.COMMON_CFG (32'h00000000),
.QPLL_CFG (QPLL_CFG),
.QPLL_CLKOUT_CFG (4'b0000),
.QPLL_COARSE_FREQ_OVRD (6'b010000),
.QPLL_COARSE_FREQ_OVRD_EN (1'b0),
.QPLL_CP (10'b0000011111),
.QPLL_CP_MONITOR_EN (1'b0),
.QPLL_DMONITOR_SEL (1'b0),
.QPLL_FBDIV (QPLL_FBDIV),
.QPLL_FBDIV_MONITOR_EN (1'b0),
.QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO),
.QPLL_INIT_CFG (24'h000006),
.QPLL_LOCK_CFG (16'h21E8),
.QPLL_LPF (4'b1111),
.QPLL_REFCLK_DIV (QPLL_REFCLK_DIV))
i_gtxe2_common (
.DRPCLK (drp_clk),
.DRPEN (drp_en),
.DRPADDR (drp_addr[7:0]),
.DRPWE (drp_wr),
.DRPDI (drp_wdata),
.DRPDO (drp_rdata),
.DRPRDY (drp_ready),
.GTGREFCLK (1'd0),
.GTNORTHREFCLK0 (1'd0),
.GTNORTHREFCLK1 (1'd0),
.GTREFCLK0 (ref_clk),
.GTREFCLK1 (1'd0),
.GTSOUTHREFCLK0 (1'd0),
.GTSOUTHREFCLK1 (1'd0),
.QPLLDMONITOR (),
.QPLLOUTCLK (qpll_clk),
.QPLLOUTREFCLK (qpll_ref_clk),
.REFCLKOUTMONITOR (),
.QPLLFBCLKLOST (),
.QPLLLOCK (qpll_locked),
.QPLLLOCKDETCLK (drp_clk),
.QPLLLOCKEN (1'd1),
.QPLLOUTRESET (1'd0),
.QPLLPD (1'd0),
.QPLLREFCLKLOST (),
.QPLLREFCLKSEL (3'b001),
.QPLLRESET (rst),
.QPLLRSVD1 (16'b0000000000000000),
.QPLLRSVD2 (5'b11111),
.BGBYPASSB (1'd1),
.BGMONITORENB (1'd1),
.BGPDB (1'd1),
.BGRCALOVRD (5'b00000),
.PMARSVD (8'b00000000),
.RCALENB (1'd1));
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; const double EPS = 10e-11; class VagueDouble { public: double vd; VagueDouble() { vd = nan( ); } VagueDouble(const double d) { vd = d; } inline VagueDouble operator-() const { return VagueDouble(-vd); } inline VagueDouble operator+(const VagueDouble VD) const { return VagueDouble(vd + VD.vd); } inline VagueDouble operator-(const VagueDouble VD) const { return VagueDouble(vd - VD.vd); } inline VagueDouble operator*(const VagueDouble VD) const { return VagueDouble(vd * VD.vd); } inline VagueDouble operator/(const VagueDouble VD) const { return VagueDouble(vd / VD.vd); } inline VagueDouble operator+(const double d) const { return VagueDouble(vd + d); } inline VagueDouble operator-(const double d) const { return VagueDouble(vd - d); } inline VagueDouble operator*(const double d) const { return VagueDouble(vd * d); } inline VagueDouble operator/(const double d) const { return VagueDouble(vd / d); } inline bool operator<(const VagueDouble VD) const { return vd + EPS < VD.vd && vd + EPS * abs(vd) < VD.vd; } inline bool operator>(const VagueDouble VD) const { return vd - EPS > VD.vd && vd - EPS * abs(vd) > VD.vd; } inline bool operator==(const VagueDouble VD) const { return !(*this < VD.vd) && !(*this > VD.vd); } inline bool operator<(const double d) const { return *this < VagueDouble(d); } inline bool operator>(const double d) const { return *this > VagueDouble(d); } inline bool operator==(const double d) const { return *this == VagueDouble(d); } inline void operator+=(const VagueDouble VD) { *this = *this + VD; } inline void operator-=(const VagueDouble VD) { *this = *this - VD; } inline void operator*=(const VagueDouble VD) { *this = *this * VD; } inline void operator/=(const VagueDouble VD) { *this = *this / VD; } inline friend VagueDouble operator+(const double d, const VagueDouble &VD) { return VagueDouble(d) + VD; } inline friend VagueDouble operator-(const double d, const VagueDouble &VD) { return VagueDouble(d) - VD; } inline friend VagueDouble operator*(const double d, const VagueDouble &VD) { return VagueDouble(d) * VD; } inline friend VagueDouble operator/(const double d, const VagueDouble &VD) { return VagueDouble(d) / VD; } inline friend bool operator<(const double d, const VagueDouble &VD) { return VagueDouble(d) < VD; } inline friend bool operator>(const double d, const VagueDouble &VD) { return VagueDouble(d) > VD; } inline friend bool operator==(const double d, const VagueDouble &VD) { return VagueDouble(d) == VD; } inline double to_double() { return vd; } inline friend std::ostream &operator<<(std::ostream &os, const VagueDouble VD) { os << VD.vd; return os; } inline friend std::istream &operator>>(std::istream &is, VagueDouble &VD) { double d; is >> d; VD = VagueDouble(d); return is; } }; inline VagueDouble abs(VagueDouble VD) { return (VD.vd < 0) ? (-VD.vd) : VD.vd; } inline VagueDouble sqr(VagueDouble VD) { return VD.vd * VD.vd; } inline VagueDouble sqr(double d) { return d * d; } inline VagueDouble sqrt(VagueDouble VD) { return VagueDouble(sqrt(VD.vd)); } inline bool isnan(VagueDouble VD) { return isnan(VD.vd); } class P { private: public: VagueDouble x, y; P() { x = nan( ); y = nan( ); } P(double _x, double _y) { x = _x; y = _y; } P(VagueDouble _x, VagueDouble _y) { x = _x; y = _y; } P operator-() const { return P(-x, -y); } P operator+(const P p) const { return P(x + p.x, y + p.y); } P operator-(const P p) const { return P(x - p.x, y - p.y); } P operator*(const double d) const { return P(x * d, y * d); } P operator/(const double d) const { return P(x / d, y / d); } bool operator<(const P &p) const { return (x == p.x) ? (y < p.y) : (x < p.x); } bool operator>(const P &p) const { return (x == p.x) ? (y > p.y) : (x > p.x); } bool operator==(const P &p) const { return (x == p.x) && (y == p.y); } void operator+=(const P &p) { *this = *this + p; } void operator-=(const P &p) { *this = *this - p; } void operator*=(const double &p) { *this = *this * p; } void operator/=(const double &p) { *this = *this / p; } VagueDouble operator*(const P p) const { return x * p.x + y * p.y; } VagueDouble operator^(const P p) const { return x * p.y - y * p.x; } friend std::ostream &operator<<(std::ostream &os, const P &p) { os << p.x.vd << << p.y.vd; return os; } friend std::istream &operator>>(std::istream &is, P &p) { double _x, _y; is >> _x >> _y; p = P(_x, _y); return is; } VagueDouble length() { return sqrt(x * x + y * y); } }; inline VagueDouble dist(P p0, P p1) { return sqrt(sqr(p0.x - p1.x) + sqr(p0.y - p1.y)); } inline VagueDouble area(P p0, P p1, P p2) { return abs((p1 - p0) ^ (p2 - p0)) * 0.5; } inline bool isnan(P p) { return isnan(p.x); } VagueDouble distPL(P l0, P l1, P p) { if (l0 == l1) return dist(l0, p); return abs((p - l0) ^ (l1 - l0)) / (l1 - l0).length(); } bool onLine(P l0, P l1, P p) { if (l0 == l1) return l0 == p; if (p.x < min(l0.x, l1.x) || max(l0.x, l1.x) < p.x) return false; if (p.y < min(l0.y, l1.y) || max(l0.y, l1.y) < p.y) return false; return distPL(l0, l1, p) == 0; } P findCross(P a0, P a1, P b0, P b1) { P a = a0 - a1, b = b0 - b1, res; VagueDouble den = a ^ b; if (den == 0) return P(); res.x = (a.x * b.x * (a0.y - b0.y) + a.x * b.y * b0.x - a.y * b.x * a0.x) / den; if (res.x < min(a0.x, a1.x) || max(a0.x, a1.x) < res.x) return P(); if (res.x < min(b0.x, b1.x) || max(b0.x, b1.x) < res.x) return P(); res.y = -(a.y * b.y * (a0.x - b0.x) + a.y * b.x * b0.y - a.x * b.y * a0.y) / den; if (res.y < min(a0.y, a1.y) || max(a0.y, a1.y) < res.y) return P(); if (res.y < min(b0.y, b1.y) || max(b0.y, b1.y) < res.y) return P(); return res; } class Polygon { private: public: vector<P> points; Polygon() {} Polygon(vector<P> vec) { points = vec; } Polygon(long long int num) { points.resize(num); } long long int size() { return ((long long int)(points).size()); } P &operator[](long long int pos) { return points[pos]; } bool onPoly(P p) { long long int n = ((long long int)(points).size()); for (long long int i = 0; i < ((long long int)(n)); ++i) if (onLine(points[i], points[(i + 1) % n], p)) return true; return false; } bool inPoly(P p) { long long int n = ((long long int)(points).size()); if (n == 0) return false; if (onPoly(p)) return true; P right_point = p; for (long long int i = 0; i < ((long long int)(n)); ++i) right_point.x = max(right_point.x, points[i].x); if (right_point == p) return false; long long int cnt = 0; for (long long int i = 0; i < ((long long int)(n)); ++i) { P cross = findCross(points[i], points[(i + 1) % n], p, right_point); if (!isnan(cross)) cnt++; } for (long long int i = 0; i < ((long long int)(((long long int)(points).size()))); ++i) if (onLine(p, right_point, points[i])) { VagueDouble dy0 = points[(i - 1 + n) % n].y - p.y; VagueDouble dy1 = points[(i + 1 + n) % n].y - p.y; if (dy0 * dy1 < 0) cnt++; } return cnt % 2 == 1; } friend std::ostream &operator<<(std::ostream &os, Polygon &poly) { for (long long int i = 0; i < ((long long int)(((long long int)(poly).size()))); ++i) os << poly[i] << ; return os; } friend std::istream &operator>>(std::istream &is, Polygon &poly) { for (long long int i = 0; i < ((long long int)(((long long int)(poly).size()))); ++i) is >> poly[i]; return is; } }; int main() { long long int n; cin >> n; vector<Polygon> base(n, Polygon(3)); for (long long int i = 0; i < ((long long int)(n)); ++i) cin >> base[i]; set<P> seg[10005]; for (long long int i = 0; i < ((long long int)(((long long int)(base).size()))); ++i) for (long long int j = 0; j < ((long long int)(((long long int)(base[i]).size()))); ++j) seg[i * 3 + j].insert(base[i][(j + 0) % 3]); for (long long int i = 0; i < ((long long int)(((long long int)(base).size()))); ++i) for (long long int j = 0; j < ((long long int)(((long long int)(base[i]).size()))); ++j) seg[i * 3 + j].insert(base[i][(j + 1) % 3]); for (long long int i = 0; i < ((long long int)(((long long int)(base).size()))); ++i) for (long long int j = 0; j < ((long long int)(((long long int)(base[i]).size()))); ++j) for (long long int k = 0; k < ((long long int)(i)); ++k) for (long long int l = 0; l < ((long long int)(((long long int)(base[k]).size()))); ++l) { if (i == k) continue; P cross = findCross(base[i][j], base[i][(j + 1) % 3], base[k][l], base[k][(l + 1) % 3]); if (isnan(cross)) continue; seg[i * 3 + j].insert(cross); seg[k * 3 + l].insert(cross); } VagueDouble res = 0.0; vector<P> vec[10005]; for (long long int i = 0; i < ((long long int)(((long long int)(base).size()))); ++i) for (long long int j = 0; j < ((long long int)(((long long int)(base[i]).size()))); ++j) for (__typeof((seg[i * 3 + j]).begin()) it = (seg[i * 3 + j]).begin(); it != (seg[i * 3 + j]).end(); it++) vec[i * 3 + j].push_back(*it); for (long long int i = 0; i < ((long long int)(((long long int)(base).size()))); ++i) for (long long int j = 0; j < ((long long int)(((long long int)(base[i]).size()))); ++j) for (long long int k = 0; k < ((long long int)(((long long int)(vec[i * 3 + j]).size()) - 1)); ++k) { P mid = (vec[i * 3 + j][k] + vec[i * 3 + j][k + 1]) / 2.0; bool ok = true; for (long long int l = 0; l < ((long long int)(((long long int)(base).size()))); ++l) if (i != l && base[l].inPoly(mid)) { ok = false; break; } if (ok) res += dist(vec[i * 3 + j][k], vec[i * 3 + j][k + 1]); } printf( %0.20lf n , res.to_double()); } |
#include <bits/stdc++.h> using namespace std; int sol1, sol2, sol3, n; string str; int main() { cin >> n >> str; for (int i = 0; i < str.length(); i++) { if (str[i] == A ) sol1++; else if (str[i] == I ) sol2++; } sol3 = str.length() - sol1 - sol2; if (sol2 == 0) { cout << sol1 << endl; return 0; } if (sol2 > 1) cout << 0 << endl; else cout << 1 << endl; return 0; } |
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:45:29 02/23/2009
// Design Name:
// Module Name: RCB_FRL_RX_MSG
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module RCB_FRL_RX_MSG(
input CLKDIV,
input RST,
input [7:0] DATA_IN,
output reg [39:0] DATA_OUT,
output reg ack_r_one,
output reg nack_r_one,
output reg msg_r_p_one,
output reg msg_r_n_one
);
// RCB_FRL_RXMSG_Byte_Alignment RCB_FRL_RXMSG_Byte_Alignment_and_MSG_Decoder_inst(
// .data_in(DATA_IN),
// .clk(CLKDIV),
// .enable(~RST),
// .DATA_rem(),
// .data_valid(),
// .data_correct(msg_r_p),
// .data_wrong(msg_r_n),
// .data_all(DATA_rem)
// );
//
// RCB_FRL_RXMSG_ACK_Decoder RCB_FRL_RXMSG_ACK_Decoder_inst(
// .data_in(DATA_IN),
// .clk(CLKDIV),
// .enable(~RST),
// .ack_r_one(ack_r_one),
// .nack_r_one(nack_r_one)
// );
reg [7:0] data_reg;
always@(posedge CLKDIV) data_reg[7:0] <= DATA_IN[7:0];
parameter MSG_HEADER = 8'hF5;
parameter MSG_SIZE = 8'h06;
parameter ACK_SYM = 8'h5F;
parameter NACK_SYM = 8'hAF;
parameter DUMMY_WAIT = 8'h44;
reg [39:0] DATA_rem;
reg [7:0] CRC_rem;
reg [8:0] msg_parser_state;
localparam IDLE = 9'b0_0000_0001;
localparam SIZE = 9'b0_0000_0010;
localparam ADDR = 9'b0_0000_0100;
localparam DATA_1 = 9'b0_0000_1000;
localparam DATA_2 = 9'b0_0001_0000;
localparam DATA_3 = 9'b0_0010_0000;
localparam DATA_4 = 9'b0_0100_0000;
localparam CRC = 9'b0_1000_0000;
localparam OUTPUT = 9'b1_0000_0000;
wire [7:0] crc_calc;
// RCB_FRL_CRC_gen RCB_FRL_CRC_gen_inst(
CRC8_gen RCB_FRL_CRC_gen_inst(
.D({MSG_SIZE,DATA_rem[39:0]}),
.NewCRC(crc_calc)
);
always@(posedge CLKDIV) DATA_OUT[39:0] <= DATA_rem[39:0];
// ack_r_one; nack_r_one
always@(posedge CLKDIV) begin
if(RST) begin
ack_r_one <= 1'b0;
nack_r_one <= 1'b0;
end else if (msg_parser_state==IDLE) begin
if(data_reg[7:0] == ACK_SYM) begin
ack_r_one <= 1'b1;
nack_r_one <= 1'b0;
end else if (data_reg[7:0] == NACK_SYM) begin
ack_r_one <= 1'b0;
nack_r_one <= 1'b1;
end else begin
ack_r_one <= 1'b0;
nack_r_one <= 1'b0;
end
end else begin
ack_r_one <= 1'b0;
nack_r_one <= 1'b0;
end
end
// msg_r_p_one; msg_r_n_one;
always@(posedge CLKDIV) begin
if(RST) begin
msg_r_p_one <= 1'b0;
msg_r_n_one <= 1'b0;
end else if (msg_parser_state==OUTPUT) begin
if(CRC_rem[7:0]==crc_calc[7:0]) begin
msg_r_p_one <= 1'b1;
msg_r_n_one <= 1'b0;
end else begin
msg_r_p_one <= 1'b0;
msg_r_n_one <= 1'b1;
end
end else begin
msg_r_p_one <= 1'b0;
msg_r_n_one <= 1'b0;
end
end
// main state machine for parsing incoming messages
always@(posedge CLKDIV) begin
if (RST) begin
DATA_rem[39:0] <= 40'h0_0000;
CRC_rem[7:0] <= 8'h00;
msg_parser_state <= IDLE;
end else begin
case (msg_parser_state)
IDLE: begin
DATA_rem[39:0] <= DATA_rem[39:0];
CRC_rem[7:0] <= CRC_rem[7:0];
if (data_reg[7:0] == MSG_HEADER)
msg_parser_state <= SIZE; // packet detected
else
msg_parser_state <= IDLE;
end
SIZE: begin // data_reg[7:0] == 8'h06
DATA_rem[39:0] <= DATA_rem[39:0];
CRC_rem[7:0] <= CRC_rem[7:0];
if (data_reg[7:0] == MSG_SIZE)
msg_parser_state <= ADDR;
else if (data_reg[7:0] == MSG_HEADER)
msg_parser_state <= SIZE;
else
msg_parser_state <= IDLE;
end
ADDR: begin
DATA_rem[39:32] <= data_reg[7:0]; // [39:32], first byte is address
DATA_rem[31:0] <= DATA_rem[31:0];
CRC_rem[7:0] <= CRC_rem[7:0];
msg_parser_state <= DATA_1;
end
DATA_1: begin
DATA_rem[39:32] <= DATA_rem[39:32];
DATA_rem[31:24] <= data_reg[7:0]; // [31:24], most significant bit first
DATA_rem[23:0] <= DATA_rem[23:0];
CRC_rem[7:0] <= CRC_rem[7:0];
msg_parser_state <= DATA_2;
end
DATA_2: begin
DATA_rem[39:24] <= DATA_rem[39:24];
DATA_rem[23:16] <= data_reg[7:0]; // [23:16]
DATA_rem[15:0] <= DATA_rem[15:0];
CRC_rem[7:0] <= CRC_rem[7:0];
msg_parser_state <= DATA_3;
end
DATA_3: begin
DATA_rem[39:16] <= DATA_rem[39:16];
DATA_rem[15:8] <= data_reg[7:0]; // [15:8]
DATA_rem[7:0] <= DATA_rem[7:0];
CRC_rem[7:0] <= CRC_rem[7:0];
msg_parser_state <= DATA_4;
end
DATA_4: begin
DATA_rem[39:8] <= DATA_rem[39:8];
DATA_rem[7:0] <= data_reg[7:0]; // [7:0]
CRC_rem[7:0] <= CRC_rem[7:0];
msg_parser_state <= CRC;
end
CRC: begin
DATA_rem[39:0] <= DATA_rem[39:0];
CRC_rem[7:0] <= data_reg[7:0];
msg_parser_state <= OUTPUT;
end
OUTPUT: begin // a redundant cycle for output, release timing requirement
// transmitter should be aware of this additional cycle and no information
// should be transmitted in this cycle
DATA_rem[39:0] <= DATA_rem[39:0];
CRC_rem[7:0] <= CRC_rem[7:0];
msg_parser_state <= IDLE;
end
default: begin
DATA_rem[39:0] <= DATA_rem[39:0];
CRC_rem[7:0] <= CRC_rem[7:0];
msg_parser_state <= IDLE;
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int sum = 0; for (int i = 0; i < n; i++) { int in; cin >> in; if (in < 0) in *= -1; sum += in; } cout << sum << endl; } |
#include <bits/stdc++.h> using namespace std; const long long modulo = 998244353; const long long p = modulo; vector<int> edges[300005]; int father[300005]; long long rCount[300005]; long long oCount[300005]; long long eCount[300005]; pair<int, int> gcd(long long a, long long b) { if (b == 0ll) return {1ll, 0ll}; pair<int, int> q = gcd(b, a % b); return {q.second, q.first - q.second * (a / b)}; } long long inv(long long a) { long long aa = gcd(a, p).first; aa %= p; if (aa < 0) aa += p; return aa; } void trace(int index) { for (int j = 0; j < edges[index].size(); ++j) { int v = edges[index][j]; if (v == father[index]) { edges[index].erase(edges[index].begin() + j); --j; continue; } father[v] = index; trace(v); } } void dfs(int index) { if (edges[index].empty()) { rCount[index] = 1; oCount[index] = 1; eCount[index] = 0; return; } long long totalR = 1; long long total = 1; for (int j = 0; j < edges[index].size(); ++j) { int v = edges[index][j]; dfs(v); totalR *= rCount[v]; totalR %= modulo; total *= rCount[v] + eCount[v]; total %= modulo; } rCount[index] = totalR; oCount[index] = 1; eCount[index] = 0; for (int j = 0; j < edges[index].size(); ++j) { int v = edges[index][j]; long long temp = oCount[v] * total; temp %= modulo; temp *= inv(rCount[v] + eCount[v]); temp %= modulo; rCount[index] += temp; rCount[index] %= modulo; oCount[index] *= (rCount[v] + eCount[v]); oCount[index] %= modulo; eCount[index] += temp; eCount[index] %= modulo; } } int main() { int n; cin >> n; if (n == 1) { cout << 1 << endl; return 0; } int u, v; for (int i = 0; i < n - 1; ++i) { scanf( %i%i , &u, &v); --u; --v; edges[u].push_back(v); edges[v].push_back(u); } for (int i = 0; i < n; ++i) { father[i] = -1; rCount[i] = 0; oCount[i] = 0; eCount[i] = 0; } father[0] = -1; trace(0); dfs(0); long long result = rCount[0]; while (result < 0) { result += modulo; } result %= modulo; cout << result << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int l = 1; int r = n; bool trn = 0; while (l <= r) { if (!trn) cout << l++; else cout << r--; cout << ; trn = !trn; } } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
wire [1:0] a = crc[1 +: 2];
wire [1:0] b = crc[3 +: 2];
wire [1:0] c = crc[5 +: 2];
wire [1:0] d = crc[7 +: 2];
wire [1:0] e = crc[9 +: 2];
wire [1:0] f = crc[11+: 2];
wire [1:0] g = crc[13+: 2];
// left () [] :: .
// unary + - ! ~ & ~& | ~| ^ ~^ ^~ ++ -- (unary)
// left **
// left * / %
// left + - (binary)
// left << >> <<< >>>
// left < <= > >= inside dist
// left == != === !== ==? !=?
// left & (binary)
// left ^ ~^ ^~ (binary)
// left | (binary)
// left &&
// left ||
// left ? :
// right ->
// none = += -= *= /= %= &= ^= |= <<= >>= <<<= >>>= := :/ <=
// {} {{}} concatenation
wire [1:0] bnz = (b==2'b0) ? 2'b11 : b;
wire [1:0] cnz = (c==2'b0) ? 2'b11 : c;
wire [1:0] dnz = (d==2'b0) ? 2'b11 : d;
wire [1:0] enz = (e==2'b0) ? 2'b11 : e;
// verilator lint_off WIDTH
// Do a few in each group
wire [1:0] o1 = ~ a; // Can't get more than one reduction to parse
wire [1:0] o2 = ^ b; // Can't get more than one reduction to parse
wire [1:0] o3 = a ** b ** c; // Some simulators botch this
wire [1:0] o4 = a * b / cnz % dnz * enz;
wire [1:0] o5 = a + b - c + d;
wire [1:0] o6 = a << b >> c <<< d >>> e <<< f;
wire [1:0] o7 = a < b <= c;
wire [1:0] o8 = a == b != c === d == e;
wire [1:0] o9 = a & b & c;
wire [1:0] o10 = a ^ b ~^ c ^~ d ^ a;
wire [1:0] o11 = a | b | c;
wire [1:0] o12 = a && b && c;
wire [1:0] o13 = a || b || c;
wire [1:0] o14 = a ? b ? c : d : e;
wire [1:0] o15 = a ? b : c ? d : e;
// Now cross each pair of groups
wire [1:0] x1 = ~ a ** ~ b ** ~c; // Some simulators botch this
wire [1:0] x2 = a ** b * c ** d; // Some simulators botch this
wire [1:0] x3 = a + b * c + d;
wire [1:0] x4 = a + b << c + d;
wire [1:0] x5 = a == b << c == d;
wire [1:0] x6 = a & b << c & d;
wire [1:0] x7 = a ^ b & c ^ d;
wire [1:0] x8 = a | b ^ c | d;
wire [1:0] x9 = a && b | c && d;
wire [1:0] x10 = a || b && c || d;
wire [1:0] x11 = a ? b || c : d ? e : f;
// verilator lint_on WIDTH
function [1:0] pow (input [1:0] x, input [1:0] y);
casez ({x,y})
4'b00_??: pow = 2'b00;
4'b01_00: pow = 2'b01;
4'b01_01: pow = 2'b01;
4'b01_10: pow = 2'b01;
4'b01_11: pow = 2'b01;
4'b10_00: pow = 2'b01;
4'b10_01: pow = 2'b10;
4'b10_10: pow = 2'b00;
4'b10_11: pow = 2'b00;
4'b11_00: pow = 2'b01;
4'b11_01: pow = 2'b11;
4'b11_10: pow = 2'b01;
4'b11_11: pow = 2'b11;
endcase
endfunction
// Aggregate outputs into a single result vector
wire [63:0] result = {12'h0,
x11,x10,x9,x8,x7,x6,x5,x4,x3,x2,x1,
o15,o14,o13,o12,o11,o10,o9,o8,o7,o6,o5,o4,o3,o2,o1};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x ",$time, cyc, crc, result);
$write(" %b",o1);
$write(" %b",o2);
$write(" %b",o3);
$write(" %b",o4);
$write(" %b",o5);
$write(" %b",o6);
$write(" %b",o7);
$write(" %b",o8);
$write(" %b",o9);
$write(" %b",o10);
$write(" %b",o11);
$write(" %b",o12);
$write(" %b",o13);
$write(" %b",o14);
$write(" %b",o15);
// Now cross each pair of groups
$write(" %b",x1);
$write(" %b",x2);
$write(" %b",x3);
$write(" %b",x4);
$write(" %b",x5);
$write(" %b",x6);
$write(" %b",x7);
$write(" %b",x8);
$write(" %b",x9);
$write(" %b",x10);
$write(" %b",x11);
$write("\n");
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h2756ea365ec7520e
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
//Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module sys_timer (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 15: 0] readdata;
input [ 2: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 15: 0] writedata;
wire clk_en;
wire control_continuous;
wire control_interrupt_enable;
reg [ 3: 0] control_register;
wire control_wr_strobe;
reg counter_is_running;
wire counter_is_zero;
wire [ 31: 0] counter_load_value;
reg [ 31: 0] counter_snapshot;
reg delayed_unxcounter_is_zeroxx0;
wire do_start_counter;
wire do_stop_counter;
reg force_reload;
reg [ 31: 0] internal_counter;
wire irq;
reg [ 15: 0] period_h_register;
wire period_h_wr_strobe;
reg [ 15: 0] period_l_register;
wire period_l_wr_strobe;
wire [ 15: 0] read_mux_out;
reg [ 15: 0] readdata;
wire snap_h_wr_strobe;
wire snap_l_wr_strobe;
wire [ 31: 0] snap_read_value;
wire snap_strobe;
wire start_strobe;
wire status_wr_strobe;
wire stop_strobe;
wire timeout_event;
reg timeout_occurred;
assign clk_en = 1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
internal_counter <= 32'h1312CF;
else if (counter_is_running || force_reload)
if (counter_is_zero || force_reload)
internal_counter <= counter_load_value;
else
internal_counter <= internal_counter - 1;
end
assign counter_is_zero = internal_counter == 0;
assign counter_load_value = {period_h_register,
period_l_register};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
force_reload <= 0;
else if (clk_en)
force_reload <= period_h_wr_strobe || period_l_wr_strobe;
end
assign do_start_counter = start_strobe;
assign do_stop_counter = (stop_strobe ) ||
(force_reload ) ||
(counter_is_zero && ~control_continuous );
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter_is_running <= 1'b0;
else if (clk_en)
if (do_start_counter)
counter_is_running <= -1;
else if (do_stop_counter)
counter_is_running <= 0;
end
//delayed_unxcounter_is_zeroxx0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxcounter_is_zeroxx0 <= 0;
else if (clk_en)
delayed_unxcounter_is_zeroxx0 <= counter_is_zero;
end
assign timeout_event = (counter_is_zero) & ~(delayed_unxcounter_is_zeroxx0);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
timeout_occurred <= 0;
else if (clk_en)
if (status_wr_strobe)
timeout_occurred <= 0;
else if (timeout_event)
timeout_occurred <= -1;
end
assign irq = timeout_occurred && control_interrupt_enable;
//s1, which is an e_avalon_slave
assign read_mux_out = ({16 {(address == 2)}} & period_l_register) |
({16 {(address == 3)}} & period_h_register) |
({16 {(address == 4)}} & snap_read_value[15 : 0]) |
({16 {(address == 5)}} & snap_read_value[31 : 16]) |
({16 {(address == 1)}} & control_register) |
({16 {(address == 0)}} & {counter_is_running,
timeout_occurred});
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= read_mux_out;
end
assign period_l_wr_strobe = chipselect && ~write_n && (address == 2);
assign period_h_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
period_l_register <= 4815;
else if (period_l_wr_strobe)
period_l_register <= writedata;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
period_h_register <= 19;
else if (period_h_wr_strobe)
period_h_register <= writedata;
end
assign snap_l_wr_strobe = chipselect && ~write_n && (address == 4);
assign snap_h_wr_strobe = chipselect && ~write_n && (address == 5);
assign snap_strobe = snap_l_wr_strobe || snap_h_wr_strobe;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter_snapshot <= 0;
else if (snap_strobe)
counter_snapshot <= internal_counter;
end
assign snap_read_value = counter_snapshot;
assign control_wr_strobe = chipselect && ~write_n && (address == 1);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
control_register <= 0;
else if (control_wr_strobe)
control_register <= writedata[3 : 0];
end
assign stop_strobe = writedata[3] && control_wr_strobe;
assign start_strobe = writedata[2] && control_wr_strobe;
assign control_continuous = control_register[1];
assign control_interrupt_enable = control_register;
assign status_wr_strobe = chipselect && ~write_n && (address == 0);
endmodule
|
#include <bits/stdc++.h> using namespace std; map<int, int> m; vector<int> fr; int v[100100]; int main() { int n; scanf( %d , &n); int mf = 0; for (int i = 0; i < n; i++) { int t; scanf( %d , &t); v[i] = t; m[t]++; mf = max(mf, m[t]); } sort(begin(v), end(v)); fr.assign(mf + 2, 0); for (auto& it : m) { fr[it.second - 1]++; } int rs = 0; int ma = 0; for (int i = fr.size() - 2; i >= 0; i--) { fr[i] = fr[i + 1] + fr[i]; } for (int i = 0; i < fr.size(); i++) { rs += fr[i]; ma = max(ma, rs - i - 1); } printf( %d n , ma); } |
`include "defines.vh"
/**
* @module lru_counter
* @author sabertazimi
* @email
* @brief least recent use algorithm hardware implementation (counter implementation)
* @param DATA_WIDTH data width
* @input clk clock signal
* @input rst reset signal
* @input en enable signal
* @input hit hit flag
* @input hit_line hit line number
* @output lru_line lease recently used line number
*/
module lru_counter
#(parameter DATA_WIDTH = 32)
(
input clk,
input rst,
input en,
input hit,
input [`BTB_LINE_SIZE-1:0] hit_line,
output [`BTB_LINE_SIZE-1:0] lru_line
);
wire [`BTB_LINE_SIZE-1:0] access_line;
wire rst0, rst1, rst2, rst3, rst4, rst5, rst6, rst7;
wire [`BTB_LINE_SIZE-1:0] cnt0, cnt1, cnt2, cnt3, cnt4, cnt5, cnt6, cnt7;
assign access_line = hit ? hit_line : lru_line;
assign rst0 = (access_line == 3'd0);
assign rst1 = (access_line == 3'd1);
assign rst2 = (access_line == 3'd2);
assign rst3 = (access_line == 3'd3);
assign rst4 = (access_line == 3'd4);
assign rst5 = (access_line == 3'd5);
assign rst6 = (access_line == 3'd6);
assign rst7 = (access_line == 3'd7);
latch_counter #(
.DATA_WIDTH(`BTB_LINE_SIZE),
.MAX(`BTB_LINE_NUM-1)
) counter0 (
.clk(clk),
.rst(rst || rst0),
.en(en),
.count(cnt0)
);
latch_counter # (
.DATA_WIDTH(`BTB_LINE_SIZE),
.MAX(`BTB_LINE_NUM-1)
) counter1 (
.clk(clk),
.rst(rst || rst1),
.en(en),
.count(cnt1)
);
latch_counter #(
.DATA_WIDTH(`BTB_LINE_SIZE),
.MAX(`BTB_LINE_NUM-1)
) counter2 (
.clk(clk),
.rst(rst || rst2),
.en(en),
.count(cnt2)
);
latch_counter #(
.DATA_WIDTH(`BTB_LINE_SIZE),
.MAX(`BTB_LINE_NUM-1)
) counter3 (
.clk(clk),
.rst(rst || rst3),
.en(en),
.count(cnt3)
);
latch_counter #(
.DATA_WIDTH(`BTB_LINE_SIZE),
.MAX(`BTB_LINE_NUM-1)
) counter4 (
.clk(clk),
.rst(rst || rst4),
.en(en),
.count(cnt4)
);
latch_counter #(
.DATA_WIDTH(`BTB_LINE_SIZE),
.MAX(`BTB_LINE_NUM-1)
) counter5 (
.clk(clk),
.rst(rst || rst5),
.en(en),
.count(cnt5)
);
latch_counter #(
.DATA_WIDTH(`BTB_LINE_SIZE),
.MAX(`BTB_LINE_NUM-1)
) counter6 (
.clk(clk),
.rst(rst || rst6),
.en(en),
.count(cnt6)
);
latch_counter #(
.DATA_WIDTH(`BTB_LINE_SIZE),
.MAX(`BTB_LINE_NUM-1)
) counter7 (
.clk(clk),
.rst(rst || rst7),
.en(en),
.count(cnt7)
);
max_comparator max_comparator (
.cnt0(cnt0),
.cnt1(cnt1),
.cnt2(cnt2),
.cnt3(cnt3),
.cnt4(cnt4),
.cnt5(cnt5),
.cnt6(cnt6),
.cnt7(cnt7),
.lru_line(lru_line)
);
endmodule // lru_counter
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYMETAL6S6S_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__DLYMETAL6S6S_FUNCTIONAL_PP_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__dlymetal6s6s (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYMETAL6S6S_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int MAX_N = 2e5 + 4; int main() { vector<pair<long long, char> > ans; long long n, st[MAX_N], pr[MAX_N] = { 0, }; long long sum = 0; scanf( %lld , &n); for (int i = 0; i < n; i++) { scanf( %lld , &st[i]); pr[i] = st[i]; sum += (1ll * st[i]); } long long k, last[MAX_N]; scanf( %lld , &k); for (int i = 0; i < k; i++) { scanf( %lld , &last[i]); sum = sum - last[i]; } if (sum != 0) { cout << NO ; return 0; } int left = n - 1, left_last = k - 1, prev; while (left >= 0 && left_last >= 0) { if (st[left] != last[left_last]) { if (last[left_last] < st[left]) { cout << NO ; return 0; } prev = left; while (left >= 0 && st[left] < last[left_last]) { left--; st[left] = st[left] + st[left + 1]; } if (left < 0 || st[left] != last[left_last]) { cout << NO ; return 0; } long long max_ = pr[left], find_ = left; for (int i = left + 1; i < prev; i++) if (max_ < pr[i]) { max_ = pr[i]; find_ = i; } else if (max_ == pr[i]) { if (i < prev) if (pr[i] > pr[i + 1]) { max_ = pr[i]; find_ = i; } } if (max_ < pr[prev]) { find_ = prev; max_ = pr[prev]; } if (find_ == prev) ; else if (find_ == left && pr[find_ + 1] == pr[find_]) { cout << NO ; return 0; } if (find_ != left && max_ == pr[find_ - 1]) { if (find_ < prev && pr[find_] > pr[find_ + 1]) ; else { cout << NO ; return 0; } } int kol1 = prev - find_; int kol2 = find_ - left; if (find_ != left && pr[find_ - 1] < pr[find_]) { ans.push_back(make_pair(find_ + 1, L )); kol2--; find_--; } while (kol1 > 0) { ans.push_back(make_pair(find_ + 1, R )); kol1--; } while (kol2 > 0) { ans.push_back(make_pair(find_ + 1, L )); find_--; kol2--; } } left--; left_last--; } cout << YES << endl; for (auto it : ans) { printf( %lld %c n , it.first, it.second); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int l, r, k; cin >> l >> r >> k; if (k < l) { cout << k << endl; } else { cout << (r / k + 1) * k << endl; } } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLRTP_FUNCTIONAL_V
`define SKY130_FD_SC_MS__DLRTP_FUNCTIONAL_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr/sky130_fd_sc_ms__udp_dlatch_pr.v"
`celldefine
module sky130_fd_sc_ms__dlrtp (
Q ,
RESET_B,
D ,
GATE
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE ;
// Local signals
wire RESET;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_ms__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLRTP_FUNCTIONAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:33:33 01/01/2017
// Design Name:
// Module Name: Detector
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Detector(
input wire [9:0] mycar_pos_x, mycar_pos_y,
input wire [9:0] obstacle_pos_x0, obstacle_pos_x1, obstacle_pos_x2, obstacle_pos_x3, obstacle_pos_x4,
input wire [9:0] obstacle_pos_y0, obstacle_pos_y1, obstacle_pos_y2, obstacle_pos_y3, obstacle_pos_y4,
output wire iscollide0, iscollide1, iscollide2, iscollide3, iscollide4
);
//============================================================================
// Const declaration
//============================================================================
parameter car_width = 60;
parameter car_height = 100;
parameter car_offset_left = 15;
parameter car_offset_right = 5;
parameter car_offset_front = 10;
parameter car_offset_bottom = 5;
parameter police_width = 64;
parameter police_height = 100;
parameter police_offset_left = 5;
parameter police_offset_right = 5;
//============================================================================
// Declare some signals to make the code more understandable
//============================================================================
wire [9:0] mycar_x_left, mycar_x_right, mycar_y_front, mycar_y_bottom;
wire [9:0] obstacle_x_left[0:4], obstacle_x_right[0:4], obstacle_y_front[0:4], obstacle_y_bottom[0:4];
assign mycar_x_left = mycar_pos_x + car_offset_left;
assign mycar_x_right = mycar_pos_x + car_width - car_offset_right;
assign mycar_y_front = mycar_pos_y + car_offset_front;
assign mycar_y_bottom = mycar_pos_y + car_height- car_offset_bottom;
assign obstacle_x_left[0] = obstacle_pos_x0 + police_offset_left;
assign obstacle_x_right[0] = obstacle_pos_x0 + police_width - police_offset_right;
assign obstacle_y_front[0] = {obstacle_pos_y0 > police_height ? obstacle_pos_y0 - police_height : 0};
assign obstacle_y_bottom[0] = obstacle_pos_y0;
assign obstacle_x_left[1] = obstacle_pos_x1 + police_offset_left;
assign obstacle_x_right[1] = obstacle_pos_x1 + police_width - police_offset_right;
assign obstacle_y_front[1] = {obstacle_pos_y1 > police_height ? obstacle_pos_y1 - police_height : 0};
assign obstacle_y_bottom[1] = obstacle_pos_y1;
assign obstacle_x_left[2] = obstacle_pos_x2 + car_offset_left;
assign obstacle_x_right[2] = obstacle_pos_x2 + car_width - car_offset_right;
assign obstacle_y_front[2] = {obstacle_pos_y2 + car_offset_front > car_height ? obstacle_pos_y2 + car_offset_front - car_height : 0};
assign obstacle_y_bottom[2] = obstacle_pos_y2 - car_offset_bottom;
assign obstacle_x_left[3] = obstacle_pos_x3 + car_offset_left;
assign obstacle_x_right[3] = obstacle_pos_x3 + car_width - car_offset_right;
assign obstacle_y_front[3] = {obstacle_pos_y3 + car_offset_front > car_height ? obstacle_pos_y3 + car_offset_front - car_height : 0};
assign obstacle_y_bottom[3] = obstacle_pos_y3 - car_offset_bottom;
assign obstacle_x_left[4] = obstacle_pos_x4 + car_offset_left;
assign obstacle_x_right[4] = obstacle_pos_x4 + car_width - car_offset_right;
assign obstacle_y_front[4] = {obstacle_pos_y4 + car_offset_front > car_height ? obstacle_pos_y4 + car_offset_front - car_height : 0};
assign obstacle_y_bottom[4] = obstacle_pos_y4 - car_offset_bottom;
//=============================================================================
// Detection
//=============================================================================
assign iscollide0 = (mycar_x_left <= obstacle_x_right[0] && mycar_x_right >= obstacle_x_right[0] && mycar_y_front <= obstacle_y_bottom [0] && mycar_y_bottom >= obstacle_y_bottom[0]) ||
(mycar_x_left <= obstacle_x_right[0] && mycar_x_right >= obstacle_x_right[0] && mycar_y_bottom >= obstacle_y_front[0] && mycar_y_front <= obstacle_y_front[0]) ||
(mycar_x_right >= obstacle_x_left[0] && mycar_x_left <= obstacle_x_left[0] && mycar_y_front <= obstacle_y_bottom[0] && mycar_y_bottom >= obstacle_y_bottom[0]) ||
(mycar_x_right >= obstacle_x_left[0] && mycar_x_left <= obstacle_x_left[0] && mycar_y_bottom >= obstacle_y_front[0] && mycar_y_front <= obstacle_y_front[0]) ||
(mycar_x_left >= obstacle_x_left[0] && mycar_x_right <= obstacle_x_right[0] && mycar_y_front <= obstacle_y_bottom[0] && mycar_y_bottom >= obstacle_y_bottom[0]);
assign iscollide1 = (mycar_x_left <= obstacle_x_right[1] && mycar_x_right >= obstacle_x_right[1] && mycar_y_front <= obstacle_y_bottom [1] && mycar_y_bottom >= obstacle_y_bottom[1]) ||
(mycar_x_left <= obstacle_x_right[1] && mycar_x_right >= obstacle_x_right[1] && mycar_y_bottom >= obstacle_y_front[1] && mycar_y_front <= obstacle_y_front[1]) ||
(mycar_x_right >= obstacle_x_left[1] && mycar_x_left <= obstacle_x_left[1] && mycar_y_front <= obstacle_y_bottom[1] && mycar_y_bottom >= obstacle_y_bottom[1]) ||
(mycar_x_right >= obstacle_x_left[1] && mycar_x_left <= obstacle_x_left[1] && mycar_y_bottom >= obstacle_y_front[1] && mycar_y_front <= obstacle_y_front[1]) ||
(mycar_x_left >= obstacle_x_left[1] && mycar_x_right <= obstacle_x_right[1] && mycar_y_front <= obstacle_y_bottom[1] && mycar_y_bottom >= obstacle_y_bottom[1]);
assign iscollide2 = (mycar_x_left <= obstacle_x_right[2] && mycar_x_right >= obstacle_x_right[2] && mycar_y_front <= obstacle_y_bottom [2] && mycar_y_bottom >= obstacle_y_bottom[2]) ||
(mycar_x_left <= obstacle_x_right[2] && mycar_x_right >= obstacle_x_right[2] && mycar_y_bottom >= obstacle_y_front[2] && mycar_y_front <= obstacle_y_front[2]) ||
(mycar_x_right >= obstacle_x_left[2] && mycar_x_left <= obstacle_x_left[2] && mycar_y_front <= obstacle_y_bottom[2] && mycar_y_bottom >= obstacle_y_bottom[2]) ||
(mycar_x_right >= obstacle_x_left[2] && mycar_x_left <= obstacle_x_left[2] && mycar_y_bottom >= obstacle_y_front[2] && mycar_y_front <= obstacle_y_front[2]) ||
(mycar_x_left >= obstacle_x_left[2] && mycar_x_right <= obstacle_x_right[2] && mycar_y_front <= obstacle_y_bottom[2] && mycar_y_bottom >= obstacle_y_bottom[2]);
assign iscollide3 = (mycar_x_left <= obstacle_x_right[3] && mycar_x_right >= obstacle_x_right[3] && mycar_y_front <= obstacle_y_bottom [3] && mycar_y_bottom >= obstacle_y_bottom[3]) ||
(mycar_x_left <= obstacle_x_right[3] && mycar_x_right >= obstacle_x_right[3] && mycar_y_bottom >= obstacle_y_front[3] && mycar_y_front <= obstacle_y_front[3]) ||
(mycar_x_right >= obstacle_x_left[3] && mycar_x_left <= obstacle_x_left[3] && mycar_y_front <= obstacle_y_bottom[3] && mycar_y_bottom >= obstacle_y_bottom[3]) ||
(mycar_x_right >= obstacle_x_left[3] && mycar_x_left <= obstacle_x_left[3] && mycar_y_bottom >= obstacle_y_front[3] && mycar_y_front <= obstacle_y_front[3]) ||
(mycar_x_left >= obstacle_x_left[3] && mycar_x_right <= obstacle_x_right[3] && mycar_y_front <= obstacle_y_bottom[3] && mycar_y_bottom >= obstacle_y_bottom[3]);
assign iscollide4 = (mycar_x_left <= obstacle_x_right[4] && mycar_x_right >= obstacle_x_right[4] && mycar_y_front <= obstacle_y_bottom [4] && mycar_y_bottom >= obstacle_y_bottom[4]) ||
(mycar_x_left <= obstacle_x_right[4] && mycar_x_right >= obstacle_x_right[4] && mycar_y_bottom >= obstacle_y_front[4] && mycar_y_front <= obstacle_y_front[4]) ||
(mycar_x_right >= obstacle_x_left[4] && mycar_x_left <= obstacle_x_left[4] && mycar_y_front <= obstacle_y_bottom[4] && mycar_y_bottom >= obstacle_y_bottom[4]) ||
(mycar_x_right >= obstacle_x_left[4] && mycar_x_left <= obstacle_x_left[4] && mycar_y_bottom >= obstacle_y_front[4] && mycar_y_front <= obstacle_y_front[4]) ||
(mycar_x_left >= obstacle_x_left[4] && mycar_x_right <= obstacle_x_right[4] && mycar_y_front <= obstacle_y_bottom[4] && mycar_y_bottom >= obstacle_y_bottom[4]);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O2BB2A_LP_V
`define SKY130_FD_SC_LP__O2BB2A_LP_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog wrapper for o2bb2a with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o2bb2a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o2bb2a_lp (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o2bb2a base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o2bb2a_lp (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o2bb2a base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O2BB2A_LP_V
|
#include <bits/stdc++.h> using namespace std; long long phi(long long x); const long long mod = 1e9 + 7; int main() { long long N, K; cin >> N >> K; while (K > 0 && N > 1) { N = phi(N); K -= 2; } cout << N % mod << endl; } long long phi(long long x) { int R = sqrt(x); long long ans = 1; for (int p = 2; p <= R; ++p) { if (x % p == 0) { long long curr = 1; while (x % p == 0) { curr *= p; x /= p; } ans *= (curr - curr / p); } } if (x > 1) { ans *= (x - 1); } return ans; } |
#include <bits/stdc++.h> using namespace std; int customCeil(int k, int s) { if (k % s == 0) return k / s; return k / s + 1; } int main() { long long int n; cin >> n; long long int arr[n]; for (int i = (0); i < (n); ++i) { cin >> arr[i]; } long long int m; cin >> m; long long int c[m]; for (int i = (0); i < (n); ++i) { cin >> c[i]; } long long int sum = 0; sort(arr, arr + n); for (int i = (0); i < (n); ++i) { sum += arr[i]; } for (int i = (0); i < (m); ++i) { cout << sum - arr[n - c[i]] << endl; } } |
module ghrd_10m50da_top (
//Clock and Reset
input wire clk_50,
input wire fpga_reset_n,
//QSPI
// output wire qspi_clk,
// inout wire[3:0] qspi_io,
// output wire qspi_csn,
//16550 UART
input wire uart_rx,
output wire uart_tx,
output wire [4:0] user_led
);
//Heart-beat counter
reg [25:0] heart_beat_cnt;
// SoC sub-system module
ghrd_10m50da ghrd_10m50da_inst (
.clk_clk (clk_50),
.reset_reset_n (fpga_reset_n),
// .ext_flash_flash_dataout_conduit_dataout (qspi_io),
// .ext_flash_flash_dclk_out_conduit_dclk_out (qspi_clk),
// .ext_flash_flash_ncs_conduit_ncs (qspi_csn),
//16550 UART
.a_16550_uart_0_rs_232_serial_sin (uart_rx), // a_16550_uart_0_rs_232_serial.sin
.a_16550_uart_0_rs_232_serial_sout (uart_tx), // .sout
.a_16550_uart_0_rs_232_serial_sout_oe () // .sout_oe
);
//Heart beat by 50MHz clock
always @(posedge clk_50 or negedge fpga_reset_n)
if (!fpga_reset_n)
heart_beat_cnt <= 26'h0; //0x3FFFFFF
else
heart_beat_cnt <= heart_beat_cnt + 1'b1;
assign user_led = {4'hf,heart_beat_cnt[25]};
endmodule
|
`include "bsg_mem_1rw_sync_mask_write_byte_macros.vh"
module bsg_mem_1rw_sync_mask_write_byte #( parameter `BSG_INV_PARAM(els_p )
, parameter `BSG_INV_PARAM(data_width_p )
, parameter addr_width_lp = `BSG_SAFE_CLOG2(els_p)
, parameter write_mask_width_lp = data_width_p>>3
, parameter harden_p = 1
, parameter latch_last_read_p = 1
)
( input clk_i
, input reset_i
, input v_i
, input w_i
, input [addr_width_lp-1:0] addr_i
, input [data_width_p-1:0] data_i
, input [write_mask_width_lp-1:0] write_mask_i
, output logic [data_width_p-1:0] data_o
);
wire unused = reset_i;
// TODO: Define more hardened macro configs here
`bsg_mem_1rw_sync_mask_write_byte_macro(512,64,2) else
`bsg_mem_1rw_sync_mask_write_byte_macro(1024,32,4) else
`bsg_mem_1rw_sync_mask_write_byte_macro(2048,64,4) else
`bsg_mem_1rw_sync_mask_write_byte_macro(4096,64,4) else
`bsg_mem_1rw_sync_mask_write_byte_macro(1024,32,4) else
`bsg_mem_1rw_sync_mask_write_byte_banked_macro(1024,256,8,1) else
// no hardened version found
begin : notmacro
bsg_mem_1rw_sync_mask_write_byte_synth #(.data_width_p(data_width_p), .els_p(els_p), .latch_last_read_p(latch_last_read_p))
synth
(.*);
end // block: notmacro
// synopsys translate_off
always_comb
begin
assert (data_width_p % 8 == 0)
else $error("data width should be a multiple of 8 for byte masking");
end
initial
begin
$display("## bsg_mem_1rw_sync_mask_write_byte: instantiating data_width_p=%d, els_p=%d (%m)",data_width_p,els_p);
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1rw_sync_mask_write_byte)
|
// Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2013.4 (lin64) Build 353583 Mon Dec 9 17:26:26 MST 2013
// Date : Mon Mar 31 20:05:27 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode synth_stub /home/keith/Documents/VHDL-lib/top/lab_4/part_1/ip/fir/fir_stub.v
// Design : fir
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module fir(aclk, s_axis_data_tvalid, s_axis_data_tready, s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata)
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[15:0],m_axis_data_tvalid,m_axis_data_tdata[39:0]" */;
input aclk;
input s_axis_data_tvalid;
output s_axis_data_tready;
input [15:0]s_axis_data_tdata;
output m_axis_data_tvalid;
output [39:0]m_axis_data_tdata;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long a[1000050]; int main() { int n; cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; } sort(a, a + n); long long rec = 0; long long num = a[0]; long long have = 0; long long can = 0; for (int i = 0; i < n; i++) { if (num == a[i]) have++; if (num != a[i]) { can++; if (a[i + 1] != a[i]) { num = a[i]; rec += min(have, can); have = have + can - min(have, can); can = 0; } } } rec = n - have; cout << rec << endl; } |
/*checksum available 6 cycles after all inputs asserted*/
module binary_adder_tree(A, B, C, D, E, F, G, H, I, clk, checksum_reg);
input [15:0] A, B, C, D, E, F, G, H, I;
input clk;
output reg [15:0] checksum_reg;
wire [15:0] checksum;
wire [16:0] sum_a_b, sum_c_d, sum_e_f, sum_g_h, sum_ab_cd, sum_ef_gh, sum_abcd_efgh, sum_i;
reg [16:0] sumreg_ab, sumreg_cd, sumreg_ef, sumreg_gh, sumreg_ab_cd, sumreg_ef_gh, sumreg_abcd_efgh, sumreg_i;
// Registers
always @ (posedge clk)
begin
//cycle 1
sumreg_ab <= sum_a_b;
sumreg_cd <= sum_c_d;
sumreg_ef <= sum_e_f;
sumreg_gh <= sum_g_h;
//cycle 2
sumreg_ab_cd <= sum_ab_cd;
sumreg_ef_gh <= sum_ef_gh;
//cycle 3
sumreg_abcd_efgh <= sum_abcd_efgh;
//cycle 4
sumreg_i <= sum_i;
//CYCLE 5
checksum_reg <= checksum;
end
// 2-bit additions
assign sum_a_b = A + B;
assign sum_c_d = C + D;
assign sum_e_f = E + F;
assign sum_g_h = G + H;
assign sum_ab_cd = sumreg_ab + sumreg_cd;
assign sum_ef_gh = sumreg_ef + sumreg_gh;
assign sum_abcd_efgh = sumreg_ab_cd + sumreg_ef_gh;
assign sum_i = sumreg_abcd_efgh+I;
assign checksum = ~((sumreg_i[16]==1'b1)?(sumreg_i[15:0]+1):sumreg_i[15:0]);
endmodule
|
module wr_port_mux_9to1
(/*AUTOARG*/
// Outputs
muxed_port_wr_en, muxed_port_wr_mask, muxed_port_wr_addr,
muxed_port_wr_data,
// Inputs
wr_port_select, port0_wr_en, port0_wr_mask, port0_wr_addr,
port0_wr_data, port1_wr_en, port1_wr_mask, port1_wr_addr,
port1_wr_data, port2_wr_en, port2_wr_mask, port2_wr_addr,
port2_wr_data, port3_wr_en, port3_wr_mask, port3_wr_addr,
port3_wr_data, port4_wr_en, port4_wr_mask, port4_wr_addr,
port4_wr_data, port5_wr_en, port5_wr_mask, port5_wr_addr,
port5_wr_data, port6_wr_en, port6_wr_mask, port6_wr_addr,
port6_wr_data, port7_wr_en, port7_wr_mask, port7_wr_addr,
port7_wr_data, port8_wr_en, port8_wr_mask, port8_wr_addr,
port8_wr_data
);
output[3:0] muxed_port_wr_en;
output [63:0] muxed_port_wr_mask;
output [9:0] muxed_port_wr_addr;
output [8191:0] muxed_port_wr_data;
input [15:0] wr_port_select;
input[3:0] port0_wr_en;
input [63:0] port0_wr_mask;
input [9:0] port0_wr_addr;
input [2047:0] port0_wr_data;
input[3:0] port1_wr_en;
input [63:0] port1_wr_mask;
input [9:0] port1_wr_addr;
input [2047:0] port1_wr_data;
input[3:0] port2_wr_en;
input [63:0] port2_wr_mask;
input [9:0] port2_wr_addr;
input [2047:0] port2_wr_data;
input[3:0] port3_wr_en;
input [63:0] port3_wr_mask;
input [9:0] port3_wr_addr;
input [2047:0] port3_wr_data;
input[3:0] port4_wr_en;
input [63:0] port4_wr_mask;
input [9:0] port4_wr_addr;
input [2047:0] port4_wr_data;
input[3:0] port5_wr_en;
input [63:0] port5_wr_mask;
input [9:0] port5_wr_addr;
input [2047:0] port5_wr_data;
input[3:0] port6_wr_en;
input [63:0] port6_wr_mask;
input [9:0] port6_wr_addr;
input [2047:0] port6_wr_data;
input[3:0] port7_wr_en;
input [63:0] port7_wr_mask;
input [9:0] port7_wr_addr;
input [2047:0] port7_wr_data;
input[3:0] port8_wr_en;
input [63:0] port8_wr_mask;
input [9:0] port8_wr_addr;
input [8191:0] port8_wr_data;
wire [8191:0] port0_wr_data_i, port1_wr_data_i, port2_wr_data_i,
port3_wr_data_i, port4_wr_data_i, port5_wr_data_i,
port6_wr_data_i, port7_wr_data_i;
genvar i;
generate
for (i = 0; i<64; i=i+1) begin
assign port0_wr_data_i[i*128+:128] = {{96{1'bx}}, port0_wr_data[i*32+:32]};
assign port1_wr_data_i[i*128+:128] = {{96{1'bx}}, port1_wr_data[i*32+:32]};
assign port2_wr_data_i[i*128+:128] = {{96{1'bx}}, port2_wr_data[i*32+:32]};
assign port3_wr_data_i[i*128+:128] = {{96{1'bx}}, port3_wr_data[i*32+:32]};
assign port4_wr_data_i[i*128+:128] = {{96{1'bx}}, port4_wr_data[i*32+:32]};
assign port5_wr_data_i[i*128+:128] = {{96{1'bx}}, port5_wr_data[i*32+:32]};
assign port6_wr_data_i[i*128+:128] = {{96{1'bx}}, port6_wr_data[i*32+:32]};
assign port7_wr_data_i[i*128+:128] = {{96{1'bx}}, port7_wr_data[i*32+:32]};
end
endgenerate
reg [3:0] muxed_port_wr_en;
reg [63:0] muxed_port_wr_mask;
reg [9:0] muxed_port_wr_addr;
reg [8191:0] muxed_port_wr_data;
always @ (
wr_port_select or
port0_wr_en or
port0_wr_mask or
port0_wr_addr or
port0_wr_data_i or
port1_wr_en or
port1_wr_mask or
port1_wr_addr or
port1_wr_data_i or
port2_wr_en or
port2_wr_mask or
port2_wr_addr or
port2_wr_data_i or
port3_wr_en or
port3_wr_mask or
port3_wr_addr or
port3_wr_data_i or
port4_wr_en or
port4_wr_mask or
port4_wr_addr or
port4_wr_data_i or
port5_wr_en or
port5_wr_mask or
port5_wr_addr or
port5_wr_data_i or
port6_wr_en or
port6_wr_mask or
port6_wr_addr or
port6_wr_data_i or
port7_wr_en or
port7_wr_mask or
port7_wr_addr or
port7_wr_data_i or
port8_wr_en or
port8_wr_mask or
port8_wr_addr or
port8_wr_data
) begin
casex(wr_port_select)
16'h0001:
begin
muxed_port_wr_en <= port0_wr_en;
muxed_port_wr_mask <= port0_wr_mask;
muxed_port_wr_addr <= port0_wr_addr;
muxed_port_wr_data <= port0_wr_data_i;
end
16'h0002:
begin
muxed_port_wr_en <= port1_wr_en;
muxed_port_wr_mask <= port1_wr_mask;
muxed_port_wr_addr <= port1_wr_addr;
muxed_port_wr_data <= port1_wr_data_i;
end
16'h0004:
begin
muxed_port_wr_en <= port2_wr_en;
muxed_port_wr_mask <= port2_wr_mask;
muxed_port_wr_addr <= port2_wr_addr;
muxed_port_wr_data <= port2_wr_data_i;
end
16'h0008:
begin
muxed_port_wr_en <= port3_wr_en;
muxed_port_wr_mask <= port3_wr_mask;
muxed_port_wr_addr <= port3_wr_addr;
muxed_port_wr_data <= port3_wr_data_i;
end
16'h0010:
begin
muxed_port_wr_en <= port4_wr_en;
muxed_port_wr_mask <= port4_wr_mask;
muxed_port_wr_addr <= port4_wr_addr;
muxed_port_wr_data <= port4_wr_data_i;
end
16'h0020:
begin
muxed_port_wr_en <= port5_wr_en;
muxed_port_wr_mask <= port5_wr_mask;
muxed_port_wr_addr <= port5_wr_addr;
muxed_port_wr_data <= port5_wr_data_i;
end
16'h0040:
begin
muxed_port_wr_en <= port6_wr_en;
muxed_port_wr_mask <= port6_wr_mask;
muxed_port_wr_addr <= port6_wr_addr;
muxed_port_wr_data <= port6_wr_data_i;
end
16'h0080:
begin
muxed_port_wr_en <= port7_wr_en;
muxed_port_wr_mask <= port7_wr_mask;
muxed_port_wr_addr <= port7_wr_addr;
muxed_port_wr_data <= port7_wr_data_i;
end
16'h0100:
begin
muxed_port_wr_en <= port8_wr_en;
muxed_port_wr_mask <= port8_wr_mask;
muxed_port_wr_addr <= port8_wr_addr;
muxed_port_wr_data <= port8_wr_data;
end
16'b0000:
begin
muxed_port_wr_en <= 4'b0;
muxed_port_wr_mask <= 64'b0;
muxed_port_wr_addr <= {10{1'bx}};
muxed_port_wr_data <= {8192{1'bx}};
end
default:
begin
muxed_port_wr_en <= 1'bx;
muxed_port_wr_mask <= {64{1'bx}};
muxed_port_wr_addr <= {10{1'bx}};
muxed_port_wr_data <= {8192{1'bx}};
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> a(n); multiset<int> b; int c[n]; for (int i = 0; i < n; i++) { cin >> a[i]; } for (int i = 0; i < n; i++) { int z; cin >> z; b.insert(z); } for (int i = 0; i < n; i++) { auto z = b.lower_bound(n - a[i]); if (z == b.end()) z = b.lower_bound(0); cout << (a[i] + *z) % n << ; b.erase(z); } } |
// hps_design_smp_hps_hps_io.v
// This file was auto-generated from altera_hps_io_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.0 145
`timescale 1 ps / 1 ps
module hps_design_smp_hps_hps_io (
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire mem_ck, // .mem_ck
output wire mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_n, // .mem_cs_n
output wire mem_ras_n, // .mem_ras_n
output wire mem_cas_n, // .mem_cas_n
output wire mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire mem_odt, // .mem_odt
output wire [3:0] mem_dm, // .mem_dm
input wire oct_rzqin, // .oct_rzqin
inout wire hps_io_gpio_inst_GPIO09, // hps_io.hps_io_gpio_inst_GPIO09
inout wire hps_io_gpio_inst_GPIO35, // .hps_io_gpio_inst_GPIO35
inout wire hps_io_gpio_inst_GPIO40, // .hps_io_gpio_inst_GPIO40
inout wire hps_io_gpio_inst_GPIO48, // .hps_io_gpio_inst_GPIO48
inout wire hps_io_gpio_inst_GPIO53, // .hps_io_gpio_inst_GPIO53
inout wire hps_io_gpio_inst_GPIO54, // .hps_io_gpio_inst_GPIO54
inout wire hps_io_gpio_inst_GPIO61 // .hps_io_gpio_inst_GPIO61
);
hps_design_smp_hps_hps_io_border border (
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.mem_dm (mem_dm), // .mem_dm
.oct_rzqin (oct_rzqin), // .oct_rzqin
.hps_io_gpio_inst_GPIO09 (hps_io_gpio_inst_GPIO09), // hps_io.hps_io_gpio_inst_GPIO09
.hps_io_gpio_inst_GPIO35 (hps_io_gpio_inst_GPIO35), // .hps_io_gpio_inst_GPIO35
.hps_io_gpio_inst_GPIO40 (hps_io_gpio_inst_GPIO40), // .hps_io_gpio_inst_GPIO40
.hps_io_gpio_inst_GPIO48 (hps_io_gpio_inst_GPIO48), // .hps_io_gpio_inst_GPIO48
.hps_io_gpio_inst_GPIO53 (hps_io_gpio_inst_GPIO53), // .hps_io_gpio_inst_GPIO53
.hps_io_gpio_inst_GPIO54 (hps_io_gpio_inst_GPIO54), // .hps_io_gpio_inst_GPIO54
.hps_io_gpio_inst_GPIO61 (hps_io_gpio_inst_GPIO61) // .hps_io_gpio_inst_GPIO61
);
endmodule
|
Subsets and Splits