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#include <bits/stdc++.h> using namespace std; const int N = (int)1e6 + 5; long long add[N << 2], sum[N << 2], color[N << 1]; int n, m; void down(int rt, int len) { if (add[rt]) { add[(rt << 1)] += add[rt]; add[(rt << 1 | 1)] += add[rt]; sum[(rt << 1)] += add[rt] * (len - (len >> 1)); sum[(rt << 1 | 1)] += add[rt] * (len >> 1); add[rt] = 0; color[(rt << 1)] = color[(rt << 1 | 1)] = color[rt]; color[rt] = 0; } } void build(int rt, int l, int r) { if (l == r) { color[rt] = l; return; } int mid = (l + r) >> 1; build((rt << 1), l, mid); build((rt << 1 | 1), mid + 1, r); color[rt] = (color[(rt << 1)] == color[(rt << 1 | 1)]) ? color[(rt << 1)] : 0; sum[rt] = sum[(rt << 1)] + sum[(rt << 1 | 1)]; } void modify(int rt, int l, int r, int L, int R, int x) { if (L <= l && r <= R && color[rt]) { add[rt] += abs(color[rt] - x); sum[rt] += (r - l + 1) * abs(color[rt] - x); color[rt] = x; return; } down(rt, r - l + 1); int mid = (l + r) >> 1; if (L <= mid) modify((rt << 1), l, mid, L, R, x); if (mid < R) modify((rt << 1 | 1), mid + 1, r, L, R, x); color[rt] = (color[(rt << 1)] == color[(rt << 1 | 1)]) ? color[(rt << 1)] : 0; sum[rt] = sum[(rt << 1)] + sum[(rt << 1 | 1)]; } long long query(int rt, int l, int r, int L, int R) { if (L <= l && r <= R) { return sum[rt]; } down(rt, r - l + 1); long long t = 0ll; int mid = (l + r) >> 1; if (L <= mid) t += query((rt << 1), l, mid, L, R); if (mid < R) t += query((rt << 1 | 1), mid + 1, r, L, R); return t; } int main() { scanf( %d%d , &n, &m); build(1, 1, n); while (m--) { int op, l, r, x; scanf( %d , &op); if (op == 1) { scanf( %d%d%d , &l, &r, &x); modify(1, 1, n, l, r, x); } else { scanf( %d%d , &l, &r); printf( %I64d n , query(1, 1, n, l, r)); } } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:31:46 04/05/2017
// Design Name:
// Module Name: DSP48E_1
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module DSPCalcModule(
input signed [20:0] charge_in,
input signed [16:0] signal_in,
input delay_en,
input clk,
input store_strb,
input fb_en,
output reg signed [14:0] pout,
input bunch_strb,
output reg DSPoflow,
// input signed [12:0] banana_corr,
output reg fb_cond,
output reg dac_clk
// input fb_en
);
(* equivalent_register_removal = "no"*) reg [7:0] j;
reg signed [37:0] DSPtemp;
//reg signed [14:0] DSPtemp2;
reg signed [14:0] delayed;
//initial DSPout=0;
reg signed [37:0] DSPout;
//reg DSPoflow=1'b0;
reg signed [20:0] chargeA = 21'd0;
always @ (posedge clk) begin
chargeA <= charge_in;
DSPtemp <= chargeA*signal_in;
//DSPtemp2=DSPtemp[24:12]; // Doesnt help timing!!!
DSPout <= DSPtemp+{delayed, 12'b0}; // Remove 4096 factor added for LUT // delayed 25 bits,
pout<=DSPout[26:12];
DSPoflow<=(~&DSPout[37:26] && ~&(~DSPout[37:26]));
end
//reg signed [10:0] banana_fract;
// ***** Clk Counter after strobe *****
// No. of samples after bunch strb
always @ (posedge clk) begin
if (~store_strb) begin
j<=8;
end
else if (bunch_strb) begin j<=0;
//banana_fract<=banana_corr[12:2]; /// Bring in as 13 bit and pad with zeros to 25 bits
end
else if (~bunch_strb) begin
j<=j+1;
end
//else j<=10;
end
//reg [47:0] banana_corr_48=0;
// If more than two bunches multiplex to add banana correction
//k1_b2_offset
reg [14:0] delayed_a;
always @ (posedge clk) begin
delayed<=delayed_a; // add banana here
if (~store_strb) begin
delayed_a<=0;
end
else if (delay_en==1) begin
if (j==6) delayed_a<=pout;
end
end
//reg fb_cond2;
always @ (posedge clk) begin
if (fb_en) begin
if (j==2||j==3) fb_cond<=1;
else fb_cond<=0;
end
else fb_cond<=0;
end
(* equivalent_register_removal = "no"*) reg delay_store_strb;
reg clr_dac;
reg delay_clr_dac;
always @ (posedge clk) begin
if (fb_en) begin
if (j==6||j==7||clr_dac==1||delay_clr_dac==1) dac_clk<=1;
else dac_clk<=0;
end
else dac_clk<=0;
end
always @(posedge clk) begin
delay_store_strb<=store_strb;
delay_clr_dac<=clr_dac;
if ((delay_store_strb==1)&(store_strb==0)) clr_dac<=1;
else clr_dac<=0;
end
endmodule
|
//altiobuf_out CBX_AUTO_BLACKBOX="ALL" CBX_SINGLE_OUTPUT_FILE="ON" DEVICE_FAMILY="Stratix IV" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=1 OPEN_DRAIN_OUTPUT="FALSE" PSEUDO_DIFFERENTIAL_MODE="TRUE" USE_DIFFERENTIAL_MODE="TRUE" USE_OE="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN1="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN2="FALSE" USE_TERMINATION_CONTROL="FALSE" datain dataout dataout_b
//VERSION_BEGIN 11.0SP1 cbx_altiobuf_out 2011:07:03:21:10:33:SJ cbx_mgl 2011:07:03:21:11:41:SJ cbx_stratixiii 2011:07:03:21:10:33:SJ cbx_stratixv 2011:07:03:21:10:33:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2011 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//synthesis_resources = stratixiv_io_obuf 2 stratixiv_pseudo_diff_out 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module altera_mem_if_ddr3_phy_0001_clock_pair_generator
(
datain,
dataout,
dataout_b) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
output [0:0] dataout;
output [0:0] dataout_b;
wire [0:0] wire_obuf_ba_o;
wire [0:0] wire_obufa_o;
wire [0:0] wire_pseudo_diffa_o;
wire [0:0] wire_pseudo_diffa_obar;
wire [0:0] oe_b;
wire [0:0] oe_w;
stratixiv_io_obuf obuf_ba_0
(
.i(wire_pseudo_diffa_obar),
.o(wire_obuf_ba_o[0:0]),
.obar(),
.oe(oe_b)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({14{1'b0}}),
.seriesterminationcontrol({14{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obuf_ba_0.bus_hold = "false",
obuf_ba_0.open_drain_output = "false",
obuf_ba_0.lpm_type = "stratixiv_io_obuf";
stratixiv_io_obuf obufa_0
(
.i(wire_pseudo_diffa_o),
.o(wire_obufa_o[0:0]),
.obar(),
.oe(oe_w)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({14{1'b0}}),
.seriesterminationcontrol({14{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_0.bus_hold = "false",
obufa_0.open_drain_output = "false",
obufa_0.shift_series_termination_control = "false",
obufa_0.lpm_type = "stratixiv_io_obuf";
stratixiv_pseudo_diff_out pseudo_diffa_0
(
.i(datain),
.o(wire_pseudo_diffa_o[0:0]),
.obar(wire_pseudo_diffa_obar[0:0]));
assign
dataout = wire_obufa_o,
dataout_b = wire_obuf_ba_o,
oe_b = 1'b1,
oe_w = 1'b1;
endmodule //altera_mem_if_ddr3_phy_0001_clock_pair_generator
//VALID FILE
|
#include <bits/stdc++.h> long long int a[100005], c[100005], s[100005]; using namespace std; int main() { int n; cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; c[a[i]]++; } s[0] = 0; s[1] = c[1]; for (int i = 2; i <= 100000; i++) { s[i] = max(s[i - 1], (s[i - 2] + c[i] * i)); } cout << s[100000]; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long M = 998244353; const long long inf = 4e18; const long long N = 3e5; long long fac[N + 1]; long long power(long long x, long long y) { if (y < 0) return power(x, M - 2) * power(x, y + 1) % M; y %= (M - 1); long long res = 1; while (y > 0) { if (y & 1) res = res * x % M; y = y >> 1; x = x * x % M; } return res; } void factorial() { fac[0] = 1; for (long long i = 1; i <= N; i++) fac[i] = fac[i - 1] * i % M; } long long nCr(long long n, long long r) { if (r > n || r < 0) return 0; if (r == 0) return 1; return (fac[n] * power(fac[r], M - 2) % M * power(fac[n - r], M - 2) % M) % M; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); factorial(); long long n, k; cin >> n >> k; vector<pair<long long, long long> > v; vector<long long> right; for (long long i = 0; i < n; i++) { long long l, r; cin >> l >> r; v.emplace_back(l, r); right.emplace_back(r); } sort(v.begin(), v.end()); sort(right.begin(), right.end()); long long o = 0; for (long long i = 0; i < n; i++) { long long j = upper_bound(v.begin(), v.end(), make_pair(right[i], inf)) - v.begin(); o = (o + nCr(j - i - 1, k - 1)) % M; } cout << o << n ; } |
#include <bits/stdc++.h> using namespace std; template <typename T, typename U> inline void smin(T &a, U b) { if (a > b) a = b; } template <typename T, typename U> inline void smax(T &a, U b) { if (a < b) a = b; } int power(int a, int b, int m, int ans = 1) { for (; b; b >>= 1, a = 1LL * a * a % m) if (b & 1) ans = 1LL * ans * a % m; return ans; } int cnt[10]; int ans[5], id[5]; int main() { int n, s; scanf( %d%d , &n, &s); int a; for (int i = 0; i < n; i++) { scanf( %d , &a); cnt[a]++; } int A, B, C, mx = 0x3f3f3f3f; for (int i = s / n; i >= 0; i--) { id[0] = i; A = cnt[3] * id[0]; for (int j = (s - A) / (cnt[4] + cnt[5]); j >= i; j--) { id[1] = j; B = cnt[4] * id[1]; C = s - A - B; id[2] = C / cnt[5]; if (C % cnt[5]) continue; int tmp = abs(A - B) + abs(B - C); if (tmp >= mx && B <= C) break; if (tmp < mx) { ans[0] = id[0]; ans[1] = id[1]; ans[2] = id[2]; mx = tmp; } } } if (mx == 0x3f3f3f3f) puts( -1 ); else printf( %d %d %d n , ans[0], ans[1], ans[2]); return 0; } |
#include <bits/stdc++.h> using namespace std; string s[101][2]; int n, m; int main() { cin >> n; m = 0; for (int i = 1; i <= n; i++) { bool mark = true; m++; cin >> s[m][0] >> s[m][1]; for (int j = 1; j < m; j++) if ((s[m][0] == s[j][0]) && (s[m][1] == s[j][1])) { mark = false; break; } if (!mark) { m--; } } cout << m << endl; return 0; } |
// $Id: c_damq_tracker.v 5188 2012-08-30 00:31:31Z dub $
/*
Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// buffer state tracker for dynamically allocated multi-queue
//==============================================================================
module c_damq_tracker
(clk, reset, active, push_valid, push_sel_qu, pop_valid, pop_sel_qu,
almost_empty_qu, empty_qu, almost_full_qu, full_qu, two_free_qu, errors_qu);
`include "c_functions.v"
`include "c_constants.v"
//---------------------------------------------------------------------------
// parameters
//---------------------------------------------------------------------------
// number of queues
parameter num_queues = 4;
// buffer entries per queue
parameter num_slots = 32;
// generate the almost_empty output early in the clock cycle
parameter fast_almost_empty = 0;
// generate the two_free output early in the clock cycle
parameter fast_two_free = 0;
// allow bypassing through empty FIFO (i.e., empty & push & pop)
parameter enable_bypass = 0;
// reserve one entry for each queue
parameter enable_reservations = 0;
parameter reset_type = `RESET_TYPE_ASYNC;
//---------------------------------------------------------------------------
// derived parameters
//---------------------------------------------------------------------------
// number of shared credits
localparam num_shared_slots
= enable_reservations ? (num_slots - num_queues) : num_slots;
// max. number of slots per queue
localparam num_queue_slots
= enable_reservations ? (1 + num_shared_slots) : num_slots;
//---------------------------------------------------------------------------
// interface
//---------------------------------------------------------------------------
input clk;
input reset;
// clock enable signal
input active;
// insert data
input push_valid;
// queue to insert into
input [0:num_queues-1] push_sel_qu;
// remove data
input pop_valid;
// queue to remove from
input [0:num_queues-1] pop_sel_qu;
// queue state flags
output [0:num_queues-1] almost_empty_qu;
wire [0:num_queues-1] almost_empty_qu;
output [0:num_queues-1] empty_qu;
wire [0:num_queues-1] empty_qu;
output [0:num_queues-1] almost_full_qu;
wire [0:num_queues-1] almost_full_qu;
output [0:num_queues-1] full_qu;
wire [0:num_queues-1] full_qu;
output [0:num_queues-1] two_free_qu;
wire [0:num_queues-1] two_free_qu;
// internal error conditions detected
output [0:num_queues*2-1] errors_qu;
wire [0:num_queues*2-1] errors_qu;
//---------------------------------------------------------------------------
// implementation
//---------------------------------------------------------------------------
wire push_shared;
wire pop_shared;
generate
if(enable_reservations)
begin
wire push_empty;
c_select_1ofn
#(.num_ports(num_queues),
.width(1))
push_empty_sel
(.select(push_sel_qu),
.data_in(empty_qu),
.data_out(push_empty));
wire pop_almost_empty;
c_select_1ofn
#(.num_ports(num_queues),
.width(1))
pop_almost_empty_sel
(.select(pop_sel_qu),
.data_in(almost_empty_qu),
.data_out(pop_almost_empty));
wire same_queue;
assign same_queue = |(push_sel_qu & pop_sel_qu);
assign push_shared = push_valid & ~push_empty &
(~pop_valid | (pop_almost_empty & ~same_queue));
if(enable_bypass)
assign pop_shared = pop_valid & ~pop_almost_empty &
(~push_valid | (push_empty & ~same_queue));
else
assign pop_shared = pop_valid & ~pop_almost_empty &
(~push_valid | push_empty);
end
else
begin
assign push_shared = push_valid & ~pop_valid;
assign pop_shared = pop_valid & ~push_valid;
end
endgenerate
wire shared_almost_full;
wire shared_full;
wire shared_two_free;
wire [0:1] shared_errors;
c_fifo_tracker
#(.depth(num_shared_slots),
.fast_two_free(fast_two_free),
.enable_bypass(0),
.reset_type(reset_type))
sft
(.clk(clk),
.reset(reset),
.active(active),
.push(push_shared),
.pop(pop_shared),
.almost_empty(),
.empty(),
.almost_full(shared_almost_full),
.full(shared_full),
.two_free(shared_two_free),
.errors(shared_errors));
genvar queue;
generate
for(queue = 0; queue < num_queues; queue = queue + 1)
begin:queues
wire push_sel;
assign push_sel = push_sel_qu[queue];
wire push;
assign push = push_valid & push_sel;
wire pop_sel;
assign pop_sel = pop_sel_qu[queue];
wire pop;
assign pop = pop_valid & pop_sel;
wire almost_empty;
wire empty;
wire [0:1] private_errors;
c_fifo_tracker
#(.depth(num_queue_slots),
.fast_almost_empty(fast_almost_empty),
.enable_bypass(enable_bypass),
.reset_type(reset_type))
ft
(.clk(clk),
.reset(reset),
.active(active),
.push(push),
.pop(pop),
.almost_empty(almost_empty),
.empty(empty),
.almost_full(),
.full(),
.two_free(),
.errors(private_errors));
wire [0:1] errors;
assign errors[0] = private_errors[0] | (pop & shared_errors[0]);
assign errors[1] = private_errors[1] | (push & shared_errors[1]);
wire almost_full;
wire full;
wire two_free;
if(enable_reservations)
begin
assign almost_full = empty ? shared_full : shared_almost_full;
assign full = ~empty & shared_full;
assign two_free = empty ? shared_almost_full : shared_two_free;
end
else
begin
assign almost_full = shared_almost_full;
assign full = shared_full;
assign two_free = shared_two_free;
end
assign almost_empty_qu[queue] = almost_empty;
assign empty_qu[queue] = empty;
assign almost_full_qu[queue] = almost_full;
assign full_qu[queue] = full;
assign two_free_qu[queue] = two_free;
assign errors_qu[queue*2:queue*2+1] = errors;
end
endgenerate
endmodule
|
#include<bits/stdc++.h> using namespace std; # define ll long long # define read read1<ll>() # define Type template<typename T> Type T read1(){ T t=0; char k; bool vis=0; do (k=getchar())== - &&(vis=1);while( 0 >k||k> 9 ); while( 0 <=k&&k<= 9 )t=(t<<3)+(t<<1)+(k^ 0 ),k=getchar(); return vis?-t:t; } # define fre(k) freopen(k .in , r ,stdin);freopen(k .out , w ,stdout) struct A{ int l,r,v; A(int _l=1,int _r=0,int _v=0){l=_l;r=_r;v=_v;} A operator &(const A &b){return A(max(l,b.l),min(r,b.r),v&b.v);} }sl[100005][20],sr[100005][20]; int s,k[100005],la[100005][2]; pair<int,int>a[100005],b[100005]; void pr(int n,bool p){ if(n==1)return; pr(la[n][p],p^1); for(int i=la[n][p];i<n;++i) putchar(p^ 1 ),putchar( ); } int main(){ s=read;read; for(int i=1;i<=s;++i){ k[i]=read; a[i].first=read; a[i].second=read; b[i].first=read; b[i].second=read; sr[i][0]=A(a[i].first,a[i].second,b[i].first<=k[i]&&k[i]<=b[i].second); sl[i][0]=A(b[i].first,b[i].second,a[i].first<=k[i]&&k[i]<=a[i].second); }for(int i=s;i;--i) for(int j=0;i+(1<<j+1)-1<=s;++j){ sl[i][j+1]=sl[i][j]&sl[i+(1<<j)][j]; sr[i][j+1]=sr[i][j]&sr[i+(1<<j)][j]; } int xl=1,xr=1; for(int i=1;i<=s;++i){ int tv=xr; if(xl>=i&&a[i].first<=k[i]&&k[i]<=a[i].second&&b[i].first<=k[i-1]&&k[i-1]<=b[i].second){ int j=i; for(int x=17;x--;) if(sl[j][x].v&&sl[j][x].l<=k[i-1]&&k[i-1]<=sl[j][x].r) j+=1<<x; while(xr<j)la[++xr][1]=i; } if(tv>=i&&b[i].first<=k[i]&&k[i]<=b[i].second&&a[i].first<=k[i-1]&&k[i-1]<=a[i].second){ int j=i; for(int x=17;x--;) if(sr[j][x].v&&sr[j][x].l<=k[i-1]&&k[i-1]<=sr[j][x].r) j+=1<<x; while(xl<j)la[++xl][0]=i; } } if(xl<=s&&xr<=s)return puts( No ),0; puts( Yes ); if(xl>s)pr(s+1,0); else pr(s+1,1); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int a; cin >> a; int i = 1; while (true) { int cnt = i / 2 + 1; if (cnt == a) { break; } ++i; } cout << i << << 2 << endl; cout << 1 2 n ; return 0; } |
#include<bits/stdc++.h> #define pb push_back #define all(v) v.begin(),v.end() #define allr(v) v.rbegin(),v.rend() #define SORT(v) sort(all(v)) #define int long long #define ff first #define ss second #define mod 1000000007 using namespace std; void oj() { ios::sync_with_stdio(0);cin.tie(0);cout.tie(0); #ifndef ONLINE_JUDGE freopen( input.txt , r , stdin); freopen( output.txt , w , stdout); #endif } void solve() { int n, k; cin>>n>>k; vector<int>h(n); vector<pair<int,int>>val; for(int i = 0; i<n; i++) cin>>h[i]; int mini = h[0]; int maxi = h[0] + k; for(int i = 1; i<n - 1; i++){ if(h[i] + 2*k - 1 <= mini || h[i] >= maxi) { cout<< NO <<endl; return; } maxi = min(maxi + k - 1LL, h[i] + 2 * k - 1LL); mini = max(mini - k + 1LL, h[i] ); } if(h[n-1] + k <= mini || h[n-1] >= maxi) { cout<< NO <<endl; return; } cout<< YES <<endl; } signed main() { oj(); int t; cin>>t; while(t--) solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 7, M = 2e5 + 7; int n, m, k, t; vector<int> b; struct Node { int in, out; long long h; Node() {} Node(int i, int o, long long _h) : in(i), out(o), h(_h) {} } a[N]; bool operator<(const Node &a, const Node &b) { if (a.out == b.out) return a.in < b.in; return a.out < b.out; } long long fen[M]; void add(int i, long long v) { for (; i <= (int)b.size(); i += i & -i) fen[i] = max(fen[i], v); } long long get(int i) { long long res = 0; for (; i > 0; i -= i & -i) res = max(res, fen[i]); return res; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d%d%lld , &a[i].in, &a[i].out, &a[i].h); b.push_back(a[i].in), b.push_back(a[i].out); } sort(a + 1, a + n + 1); sort(b.begin(), b.end()), b.resize((int)(unique(b.begin(), b.end()) - b.begin())); for (int i = n; i > 0; i--) { k = (lower_bound(b.begin(), b.end(), a[i].out) - b.begin()) + 1; t = (lower_bound(b.begin(), b.end(), a[i].in) - b.begin()) + 1; add(t, get(k - 1) + a[i].h); } printf( %lld , get((int)b.size())); return 0; } |
#include <bits/stdc++.h> using namespace std; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t; cin >> t; while (t--) { long long a, b, c, d; cin >> a >> b >> c >> d; if (a > (b * c)) { cout << (-1) << endl; continue; } long long k = (a / (d * b)); cout << (a * (k + 1)) - (d * b * k * (k + 1) / 2) << endl; } return 0; } |
#include <bits/stdc++.h> const int inf = INT_MAX; const int MAX = 1e5 + 8; const long long MOD = 1e9 + 7; const int TOT_PRIMES = 1e6 + 9; const int MAX_A = 71; const int LN = 20; using namespace std; bool prime[MAX]; void precompute() { memset(prime, false, sizeof(prime)); for (int i = 2; i < MAX; i++) { if (!prime[i]) { for (int j = 2 * i; j < MAX; j += i) prime[j] = true; } } } int a[60][60], b[60][60]; int main() { int n; vector<long long> dif; cin >> n; long long ans = 0; for (int i = 0; i < n; i++) { long long x, y; cin >> x >> y; dif.push_back(x - y); ans = ans + (n * y - x); } sort(dif.begin(), dif.end()); for (int i = n - 1; i >= 0; i--) { ans = ans + (dif[n - i - 1] * (i + 1)); } cout << ans; } |
#include <bits/stdc++.h> using namespace std; int sg[100005], sgp[100005]; int main() { int n; cin >> n; if (n <= 2) { cout << -1 ; return 0; } sg[0] = sg[1] = sg[2] = 0; for (int i = 3; i <= n; ++i) { int cnt[105] = {0}; for (int d = 2; d <= i; ++d) { int fr, ls; if (d % 2 == 0) { fr = i / d - d / 2 + 1, ls = i / d + d / 2; if (ls >= i || fr <= 0) break; if ((fr + ls) * d / 2 != i) continue; } if (d % 2 == 1) { fr = i / d - (d - 1) / 2, ls = i / d + (d - 1) / 2; if (ls >= i || fr <= 0) break; if (i % d != 0) continue; } cnt[sgp[fr - 1] ^ sgp[ls]] = 1; if (i == n && (sgp[fr - 1] ^ sgp[ls]) == 0) { cout << d; return 0; } } for (int j = 0; j < 100000; ++j) if (cnt[j] == 0) { sg[i] = j; sgp[i] = sgp[i - 1] ^ sg[i]; break; } } cout << -1 ; } |
/* Memory mapped modules */
// Generate 25.00MHz
reg [1:0] clkdiv; // divider
always @(posedge sys_clk_in)
begin
case (clkdiv)
2'b11: clkdiv <= 2'b10;
2'b10: clkdiv <= 2'b00;
2'b00: clkdiv <= 2'b01;
2'b01: clkdiv <= 2'b11;
endcase
end
assign clk = clkdiv[1];
// Bi-directional SRAM data pins
wire [15:0] sram_in;
wire [15:0] sram_out;
wire data_we;
wire sram_vga_busy;
wire [2:0] rgb;
// AMBER: #ffff33
assign red=rgb[1]?4'he:4'b0;
assign green=rgb[0]?4'he:4'b0;
assign blue=rgb[2]?4'h3:4'b0;
SB_IO
#(
.PIN_TYPE(6'b 1010_01)
)
sram_data_pins [15:0]
(
.PACKAGE_PIN(DAT),
.OUTPUT_ENABLE(data_we_cpu),
.D_OUT_0(sram_out),
.D_IN_0(sram_in)
);
assign RAMCS_b = 1'b0;
assign RAMOE_b = !data_we;
assign RAMWE_b = (data_we);
assign RAMUB_b = 1'b0;
assign RAMLB_b = 1'b0;
wire [17:0] sram_adr_vga;
wire [17:0] sram_adr_cpu;
assign ADR = grant_vga?sram_adr_vga:grant_cpu?sram_adr_cpu:0;
wire data_we_cpu;
assign data_we = grant_vga?1:(!data_we_cpu);
wire data_rq_cpu;
wire data_rq_vga;
wire grant_cpu;
wire grant_vga;
arbiter arb1 (.clk(clk),
.rst(!rst),
.req0(data_rq_cpu),
.req1(data_rq_vga),
.req2(0), .req3(0),
.gnt0(grant_cpu),
.gnt1(grant_vga),
.gnt2(gnt2_),
.gnt3(gnt3_));
wire vgaenable;
vga640x480ice vga1 (.clk(clk),
.clk25mhz(clk),
.rst(vgaenable),
.sram_adr_vga(sram_adr_vga),
.sram_in(sram_in),
.data_rq_vga(data_rq_vga),
.grant_vga(grant_vga),
.hsync(hsync),
.vsync(vsync),
.rgb(rgb));
reg [9:0] reset_counter = 0;
reg hard_reset = 0;
always @(posedge clk) if (!hard_reset) begin
reset_counter <= reset_counter + 1;
if (reset_counter[9]) hard_reset <= 1;
end
assign rst = hard_reset;
wire [3:0] LED;
wire [3:0] LEDr;
outpin led0 (.clk(clk), .we(1'b1), .pin(LED1), .wd(LED[0]), .rd(LEDr[0]));
outpin led1 (.clk(clk), .we(1'b1), .pin(LED2), .wd(LED[1]), .rd(LEDr[1]));
outpin led2 (.clk(clk), .we(1'b1), .pin(LED3), .wd(LED[2]), .rd(LEDr[2]));
outpin led3 (.clk(clk), .we(1'b1), .pin(LED4), .wd(LED[3]), .rd(LEDr[3]));
ledwriter ledwr1 (.clk(clk),
.rst(rst),
.LED(LED),
.addr_b(ram_addr_in_b),
.data_b_in(ram_data_out_b),
.data_b_we(ram_we_out));
wire [31:0] data_bus_in_uart;
wire data_bus_strobe_uart;
`ifdef ENABLE_UART
uartmm uart1(.clk(clk),
.rst(rst),
.TX(TX),
.RX(RX),
.data_b(data_bus_in_uart),
.addr_b(ram_addr_in_b),
.strobe_b(data_bus_strobe_uart),
.data_b_in(ram_data_out_b),
.data_b_we(ram_we_out)
);
`else // !`ifdef ENABLE_UART
assign data_bus_strobe_uart = 0;
`endif // !`ifdef ENABLE_UART
|
#include <bits/stdc++.h> using namespace std; long long sub(long long a, long long b) { return (a - b + 1000000007) % 1000000007; } long long add(long long a, long long b) { return (a + b) % 1000000007; } long long mul(long long a, long long b) { return (a * b) % 1000000007; } vector<long long> adj[100005]; bool vis[100005]; long long siz, edges; void dfs(long long i) { vis[i] = 1; for (long long j = 0; j < adj[i].size(); j++) { edges++; if (!vis[adj[i][j]]) dfs(adj[i][j]); } } long long mpow(long long base, long long exp) { base %= 1000000007; long long result = 1; while (exp > 0) { if (exp & 1) result = ((long long)result * base) % 1000000007; base = ((long long)base * base) % 1000000007; exp >>= 1; } return result; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; long long n, sum = 0, t = 1, m, ans; while (t--) { string s1, s = ; cin >> s1; for (long long i = 0; i < s1.length(); i++) if (s1[i] == a || s1[i] == b ) s += s1[i]; n = s.length(); vector<long long> dp(n + 1, 1); dp[0] = 1; ans = 1; for (long long i = 1; i < n + 1; i++) { if (s[i - 1] == a ) dp[i] = dp[i - 1] + 1; else { dp[i] = 1; ans = (ans * (dp[i - 1])) % 1000000007; } } ans = (ans * dp[n]) % 1000000007; cout << ans - 1 << n ; } cerr << nTime elapsed: << 1.0 * clock() / CLOCKS_PER_SEC << s. n ; ; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; const ll INF = 4e18; const int N = 5e5 + 1; vector<int> vec; vector<pair<int, ll> > g[N]; int n, op, t, l, r, q, s, pos[N][2]; void construct(int node = 1, int b = 1, int e = n) { pos[node][op] = ++t; if (b == e) { if (op == 0) g[pos[node][0]].push_back({b, 0}); else g[b].push_back({pos[node][1], 0}); return; } int m = (b + e) >> 1; construct(node << 1, b, m); construct(node << 1 | 1, m + 1, e); if (op == 0) { g[pos[node][0]].push_back({pos[node << 1][0], 0}); g[pos[node][0]].push_back({pos[node << 1 | 1][0], 0}); } else { g[pos[node << 1][1]].push_back({pos[node][1], 0}); g[pos[node << 1 | 1][1]].push_back({pos[node][1], 0}); } } void query(int node = 1, int b = 1, int e = n) { if (b > e || b > r || e < l) return; if (l <= b && e <= r) { vec.push_back(pos[node][op]); return; } int m = (b + e) >> 1; query(node << 1, b, m); query(node << 1 | 1, m + 1, e); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> q >> s; t = n; op = 0; construct(); op = 1; construct(); while (q--) { cin >> op; if (op == 1) { int v, u, w; cin >> v >> u >> w; g[v].push_back({u, w}); } else { op -= 2; int v, w; cin >> v >> l >> r >> w; query(); if (op == 0) { for (int x : vec) { g[v].push_back({x, w}); } } else { for (int x : vec) { g[x].push_back({v, w}); } } vec.clear(); } } priority_queue<pair<ll, int> > pq; pq.push({0, s}); vector<ll> dis(N, INF); dis[s] = 0; for (int i = 1; i <= n; i += 1) { pq.push({-dis[i], i}); } while (!pq.empty()) { int u = pq.top().second; pq.pop(); for (auto x : g[u]) { int v = x.first; int cost = x.second; if (dis[v] > dis[u] + cost) { dis[v] = dis[u] + cost; pq.push({-dis[v], v}); } } } for (int i = 1; i <= n; i += 1) { if (dis[i] >= INF) dis[i] = -1; cout << dis[i] << ; } cout << n ; return 0; } |
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact :
//-------------------------------------------------------------------
// Filename : db_qp_ram.v
// Author : Yibo FAN
// Created : 2012-04-01
// Description : Single Port Ram Model
// Data :[5:0] qp_top [11:6]:qp_top_modified [19:12]:qp_top_flag[7:0]
// $Id$
//-------------------------------------------------------------------
`include "enc_defines.v"
module db_qp_ram(
clk ,
cen_i ,
oen_i ,
wen_i ,
addr_i ,
data_i ,
data_o
);
// ********************************************
//
// Parameter DECLARATION
//
// ********************************************
parameter Word_Width = 20 ;
parameter Addr_Width = `PIC_X_WIDTH;
// ********************************************
//
// Input/Output DECLARATION
//
// ********************************************
input clk; // clock input
input cen_i; // chip enable, low active
input oen_i; // data output enable, low active
input wen_i; // write enable, low active
input [Addr_Width-1:0] addr_i; // address input
input [Word_Width-1:0] data_i; // data input
output [Word_Width-1:0] data_o; // data output
// ********************************************
//
// Register DECLARATION
//
// ********************************************
reg [Word_Width-1:0] mem_array[(1<<Addr_Width)-1:0];
// ********************************************
//
// Wire DECLARATION
//
// ********************************************
reg [Word_Width-1:0] data_r;
// ********************************************
//
// Logic DECLARATION
//
// ********************************************
// mem write
always @(posedge clk) begin
if(!cen_i && !wen_i)
mem_array[addr_i] <= data_i;
end
// mem read
always @(posedge clk) begin
if (!cen_i && wen_i)
data_r <= mem_array[addr_i];
else
data_r <= 'bx;
end
assign data_o = oen_i ? 'bz : data_r;
endmodule |
#include <bits/stdc++.h> using namespace std; const int N = 100010; int main() { int n, k; scanf( %d %d , &n, &k); int def = 0; int a[N], d[N] = {}; for (int i = 0; i <= n; i++) { int a[N]; char c[10]; if (scanf( %d , &a[i])) d[i] = 1, def++; else scanf( %s , c); } if (k == 0) { if (d[0]) printf( %s n , a[0] == 0 ? Yes : No ); else printf( %s n , def % 2 == 0 ? No : Yes ); } else { if (def != n + 1) { printf( %s n , n % 2 ? Yes : No ); } else { if (k == 1) { int resp = 0; for (int i = n; i >= 0; i--) resp += a[i]; printf( %s n , resp == 0 ? Yes : No ); } else { long long r = 0; for (int i = 0; i <= n; i++) { r = r / k + a[i]; if (r % k) break; } printf( %s n , r == 0 ? Yes : No ); } } } return 0; } |
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for ip_eth_rx_64
*/
module test_ip_eth_rx_64;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg s_eth_hdr_valid = 0;
reg [47:0] s_eth_dest_mac = 0;
reg [47:0] s_eth_src_mac = 0;
reg [15:0] s_eth_type = 0;
reg [63:0] s_eth_payload_axis_tdata = 0;
reg [7:0] s_eth_payload_axis_tkeep = 0;
reg s_eth_payload_axis_tvalid = 0;
reg s_eth_payload_axis_tlast = 0;
reg s_eth_payload_axis_tuser = 0;
reg m_ip_hdr_ready = 0;
reg m_ip_payload_axis_tready = 0;
// Outputs
wire s_eth_hdr_ready;
wire s_eth_payload_axis_tready;
wire m_ip_hdr_valid;
wire [47:0] m_eth_dest_mac;
wire [47:0] m_eth_src_mac;
wire [15:0] m_eth_type;
wire [3:0] m_ip_version;
wire [3:0] m_ip_ihl;
wire [5:0] m_ip_dscp;
wire [1:0] m_ip_ecn;
wire [15:0] m_ip_length;
wire [15:0] m_ip_identification;
wire [2:0] m_ip_flags;
wire [12:0] m_ip_fragment_offset;
wire [7:0] m_ip_ttl;
wire [7:0] m_ip_protocol;
wire [15:0] m_ip_header_checksum;
wire [31:0] m_ip_source_ip;
wire [31:0] m_ip_dest_ip;
wire [63:0] m_ip_payload_axis_tdata;
wire [7:0] m_ip_payload_axis_tkeep;
wire m_ip_payload_axis_tvalid;
wire m_ip_payload_axis_tlast;
wire m_ip_payload_axis_tuser;
wire busy;
wire error_header_early_termination;
wire error_payload_early_termination;
wire error_invalid_header;
wire error_invalid_checksum;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_eth_hdr_valid,
s_eth_dest_mac,
s_eth_src_mac,
s_eth_type,
s_eth_payload_axis_tdata,
s_eth_payload_axis_tkeep,
s_eth_payload_axis_tvalid,
s_eth_payload_axis_tlast,
s_eth_payload_axis_tuser,
m_ip_hdr_ready,
m_ip_payload_axis_tready
);
$to_myhdl(
s_eth_hdr_ready,
s_eth_payload_axis_tready,
m_ip_hdr_valid,
m_eth_dest_mac,
m_eth_src_mac,
m_eth_type,
m_ip_version,
m_ip_ihl,
m_ip_dscp,
m_ip_ecn,
m_ip_length,
m_ip_identification,
m_ip_flags,
m_ip_fragment_offset,
m_ip_ttl,
m_ip_protocol,
m_ip_header_checksum,
m_ip_source_ip,
m_ip_dest_ip,
m_ip_payload_axis_tdata,
m_ip_payload_axis_tkeep,
m_ip_payload_axis_tvalid,
m_ip_payload_axis_tlast,
m_ip_payload_axis_tuser,
busy,
error_header_early_termination,
error_payload_early_termination,
error_invalid_header,
error_invalid_checksum
);
// dump file
$dumpfile("test_ip_eth_rx_64.lxt");
$dumpvars(0, test_ip_eth_rx_64);
end
ip_eth_rx_64
UUT (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(s_eth_hdr_valid),
.s_eth_hdr_ready(s_eth_hdr_ready),
.s_eth_dest_mac(s_eth_dest_mac),
.s_eth_src_mac(s_eth_src_mac),
.s_eth_type(s_eth_type),
.s_eth_payload_axis_tdata(s_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(s_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(s_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(s_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(s_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(s_eth_payload_axis_tuser),
// IP frame output
.m_ip_hdr_valid(m_ip_hdr_valid),
.m_ip_hdr_ready(m_ip_hdr_ready),
.m_eth_dest_mac(m_eth_dest_mac),
.m_eth_src_mac(m_eth_src_mac),
.m_eth_type(m_eth_type),
.m_ip_version(m_ip_version),
.m_ip_ihl(m_ip_ihl),
.m_ip_dscp(m_ip_dscp),
.m_ip_ecn(m_ip_ecn),
.m_ip_length(m_ip_length),
.m_ip_identification(m_ip_identification),
.m_ip_flags(m_ip_flags),
.m_ip_fragment_offset(m_ip_fragment_offset),
.m_ip_ttl(m_ip_ttl),
.m_ip_protocol(m_ip_protocol),
.m_ip_header_checksum(m_ip_header_checksum),
.m_ip_source_ip(m_ip_source_ip),
.m_ip_dest_ip(m_ip_dest_ip),
.m_ip_payload_axis_tdata(m_ip_payload_axis_tdata),
.m_ip_payload_axis_tkeep(m_ip_payload_axis_tkeep),
.m_ip_payload_axis_tvalid(m_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(m_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(m_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(m_ip_payload_axis_tuser),
// Status signals
.busy(busy),
.error_header_early_termination(error_header_early_termination),
.error_payload_early_termination(error_payload_early_termination),
.error_invalid_header(error_invalid_header),
.error_invalid_checksum(error_invalid_checksum)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND3_2_V
`define SKY130_FD_SC_HD__AND3_2_V
/**
* and3: 3-input AND.
*
* Verilog wrapper for and3 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__and3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and3_2 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and3_2 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND3_2_V
|
#include <bits/stdc++.h> using namespace std; int n, p, t[100100], tree[100100]; queue<int> q; set<int> waiting; long long curT, ans[100100]; int get(int x) { for (int i = x; i; i -= i & -i) if (tree[i]) return 1; return 0; } void add(int x, int v) { for (int i = x; i <= 100000; i += i & -i) tree[i] += v; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); vector<pair<int, int>> a; cin >> n >> p; for (int i = 0; i < n; i++) { cin >> t[i]; a.push_back({t[i], i}); } sort(a.begin(), a.end()); int i = 0; while (1) if (!q.empty()) { int x = q.front(); q.pop(); curT += p; ans[x] = curT; while (i < n && a[i].first < curT) { int y = a[i++].second; if (get(y)) waiting.insert(y); else { q.push(y); add(y + 1, 1); } } add(x + 1, -1); while (i < n && a[i].first == curT) waiting.insert(a[i++].second); if (waiting.empty()) continue; int y = *waiting.begin(); if (get(y)) { auto it = waiting.lower_bound(x); if (it == waiting.end()) continue; y = *it; if (get(y)) continue; } q.push(y); add(y + 1, 1); waiting.erase(y); } else { if (i == n) break; int x = a[i++].second; q.push(x); curT = t[x]; add(x + 1, 1); } for (int i = 0; i < n; i++) cout << ans[i] << n [i == n - 1]; } |
#include <bits/stdc++.h> using namespace std; int n, a[100010], cewa, now; int main() { cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; } sort(a, a + n); now = 0; for (int i = 0; i < n; i++) { if (now > a[i]) { cewa++; now -= a[i]; } now += a[i]; } cout << n - cewa << n ; } |
#include <bits/stdc++.h> using namespace std; struct Node { int loc; int s; int v; Node(int ll, int ss, int vv) : loc(ll), s(ss), v(vv) {} bool operator<(const Node& other) const { return v > other.v; } }; vector<pair<int, int> > adj[32]; int main() { priority_queue<Node> que; int N, K, T; scanf( %d%d%d , &N, &K, &T); while (K--) { int h, w, r; scanf( %d%d%d , &h, &w, &r); h--; w--; adj[h].push_back(pair<int, int>(w, r)); } que.push(Node(0, 0, 0)); int now = 0; while (now + 1 < T) { Node p = que.top(); que.pop(); now++; for (int h = p.loc; h < N; h++) { for (int i = 0; i < adj[h].size(); i++) { pair<int, int> w = adj[h][i]; if (!(p.s & (1 << w.first))) que.push(Node(h + 1, p.s | (1 << w.first), p.v + w.second)); } } } printf( %d n , que.top().v); return 0; } |
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: STARTUP.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module STARTUP (
address,
clock,
q);
input [8:0] address;
input clock;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({32{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
`ifdef NO_PLI
altsyncram_component.init_file = "./startup/startup.rif"
`else
altsyncram_component.init_file = "./startup/startup.hex"
`endif
,
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 512,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 9,
altsyncram_component.width_a = 32,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./startup/startup.hex"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "512"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "9"
// Retrieval info: PRIVATE: WidthData NUMERIC "32"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./startup/startup.hex"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 9 0 INPUT NODEFVAL "address[8..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: CONNECT: @address_a 0 0 9 0 address 0 0 9 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL STARTUP.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL STARTUP.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL STARTUP.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL STARTUP.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL STARTUP_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL STARTUP_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "soc_system_onchip_memory2_0.hex";
output [ 63: 0] readdata;
input [ 12: 0] address;
input [ 7: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [ 63: 0] writedata;
wire clocken0;
wire [ 63: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 8192,
the_altsyncram.numwords_a = 8192,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 64,
the_altsyncram.width_byteena_a = 8,
the_altsyncram.widthad_a = 13;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 101; int n, a[N][30]; long long nd[N][N], num[N]; int main() { ios_base::sync_with_stdio(false); cin >> n; for (int i = 1; i <= n; ++i) for (int j = 1; j <= n; ++j) cin >> nd[i][j]; memset(a, 0, sizeof(a)); for (int i = 1; i <= n; ++i) for (int j = i + 1; j <= n; ++j) { int run = 29; while (run >= 0) { if (nd[i][j] & (1 << (29 - run))) a[i][run] = a[j][run] = 1; --run; } } for (int i = 1; i <= n; ++i) for (int k = 0; k <= 29; ++k) num[i] += (1 << k) * (a[i][29 - k]); for (int i = 1; i <= n; ++i) cout << num[i] << ; cout << n ; } |
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_port_channel_gate_32.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Captures transaction open/close events as well as data
// and passes it to the RD_CLK domain through the async_fifo. CHNL_TX_DATA_REN can
// only be high after CHNL_TX goes high and after the CHNL_TX_ACK pulse. When
// CHNL_TX drops, the channel closes (until the next transaction -- signaled by
// CHNL_TX going up again).
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`define S_TXPORTGATE32_IDLE 2'b00
`define S_TXPORTGATE32_OPENING 2'b01
`define S_TXPORTGATE32_OPEN 2'b10
`define S_TXPORTGATE32_CLOSED 2'b11
`timescale 1ns/1ns
module tx_port_channel_gate_32
#(parameter C_DATA_WIDTH = 9'd32,
// Local parameters
parameter C_FIFO_DEPTH = 8,
parameter C_FIFO_DATA_WIDTH = C_DATA_WIDTH + 1)
(input RST,
input RD_CLK, // FIFO read clock
output [C_FIFO_DATA_WIDTH-1:0] RD_DATA, // FIFO read data
output RD_EMPTY, // FIFO is empty
input RD_EN, // FIFO read enable
input CHNL_CLK, // Channel write clock
input CHNL_TX, // Channel write receive signal
output CHNL_TX_ACK, // Channel write acknowledgement signal
input CHNL_TX_LAST, // Channel last write
input [31:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [30:0] CHNL_TX_OFF, // Channel write offset
input [C_DATA_WIDTH-1:0] CHNL_TX_DATA, // Channel write data
input CHNL_TX_DATA_VALID, // Channel write data valid
output CHNL_TX_DATA_REN); // Channel write data has been recieved
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [1:0] rState=`S_TXPORTGATE32_IDLE, _rState=`S_TXPORTGATE32_IDLE;
reg rFifoWen=0, _rFifoWen=0;
reg [C_FIFO_DATA_WIDTH-1:0] rFifoData=0, _rFifoData=0;
wire wFifoFull;
reg rChnlTx=0, _rChnlTx=0;
reg rChnlLast=0, _rChnlLast=0;
reg [31:0] rChnlLen=0, _rChnlLen=0;
reg [30:0] rChnlOff=0, _rChnlOff=0;
reg rAck=0, _rAck=0;
reg rPause=0, _rPause=0;
reg rClosed=0, _rClosed=0;
reg rOpen=0, _rOpen=0;
assign CHNL_TX_ACK = rAck;
assign CHNL_TX_DATA_REN = (rOpen & !wFifoFull); // S_TXPORTGATE32_OPEN
// Buffer the input signals that come from outside the tx_port.
always @ (posedge CHNL_CLK) begin
rChnlTx <= #1 (RST ? 1'd0 : _rChnlTx);
rChnlLast <= #1 _rChnlLast;
rChnlLen <= #1 _rChnlLen;
rChnlOff <= #1 _rChnlOff;
end
always @ (*) begin
_rChnlTx = CHNL_TX;
_rChnlLast = CHNL_TX_LAST;
_rChnlLen = CHNL_TX_LEN;
_rChnlOff = CHNL_TX_OFF;
end
// FIFO for temporarily storing data from the channel.
(* RAM_STYLE="DISTRIBUTED" *)
async_fifo
#(.C_WIDTH(C_FIFO_DATA_WIDTH),
.C_DEPTH(C_FIFO_DEPTH))
fifo
(.WR_CLK(CHNL_CLK),
.WR_RST(RST),
.WR_EN(rFifoWen),
.WR_DATA(rFifoData),
.WR_FULL(wFifoFull),
.RD_CLK(RD_CLK),
.RD_RST(RST),
.RD_EN(RD_EN),
.RD_DATA(RD_DATA),
.RD_EMPTY(RD_EMPTY));
// Pass the transaction open event, transaction data, and the transaction
// close event through to the RD_CLK domain via the async_fifo.
always @ (posedge CHNL_CLK) begin
rState <= #1 (RST ? `S_TXPORTGATE32_IDLE : _rState);
rFifoWen <= #1 (RST ? 1'd0 : _rFifoWen);
rFifoData <= #1 _rFifoData;
rAck <= #1 (RST ? 1'd0 : _rAck);
rPause <= #1 (RST ? 1'd0 : _rPause);
rClosed <= #1 (RST ? 1'd0 : _rClosed);
rOpen <= #1 (RST ? 1'd0 : _rOpen);
end
always @ (*) begin
_rState = rState;
_rFifoWen = rFifoWen;
_rFifoData = rFifoData;
_rPause = rPause;
_rAck = rAck;
_rClosed = rClosed;
_rOpen = rOpen;
case (rState)
`S_TXPORTGATE32_IDLE: begin // Write the len
_rPause = 0;
_rClosed = 0;
_rOpen = 0;
if (!wFifoFull) begin
_rFifoWen = rChnlTx;
_rFifoData = {1'd1, rChnlLen};
if (rChnlTx)
_rState = `S_TXPORTGATE32_OPENING;
end
end
`S_TXPORTGATE32_OPENING: begin // Write the off, last
// rClosed catches a transfer that opens and subsequently closes
// without writing data
_rClosed = (rClosed | !rChnlTx);
if (!wFifoFull) begin
_rAck = rChnlTx;
_rFifoData = {1'd1, rChnlOff, rChnlLast};
if (rClosed | !rChnlTx)
_rState = `S_TXPORTGATE32_CLOSED;
else begin
_rState = `S_TXPORTGATE32_OPEN;
_rOpen = CHNL_TX & rChnlTx;
end
end
end
`S_TXPORTGATE32_OPEN: begin // Copy channel data into the FIFO
_rAck = 0;
if (!wFifoFull) begin
// CHNL_TX_DATA_VALID & CHNL_TX_DATA should really be buffered
// but the VALID+REN model seem to make this difficult.
_rFifoWen = CHNL_TX_DATA_VALID;
_rFifoData = {1'd0, CHNL_TX_DATA};
end
if (!rChnlTx)
_rState = `S_TXPORTGATE32_CLOSED;
_rOpen = CHNL_TX & rChnlTx;
end
`S_TXPORTGATE32_CLOSED: begin // Write the end marker (twice)
_rAck = 0;
if (!wFifoFull) begin
_rPause = 1;
_rFifoWen = 1;
_rFifoData = {1'd1, {C_DATA_WIDTH{1'd0}}};
if (rPause)
_rState = `S_TXPORTGATE32_IDLE;
end
end
endcase
end
endmodule
|
#include <iostream> #define MAX 200010 using namespace std; long long int t, n, A[MAX], DP[MAX][105], res, a; int main() { cin >> t; for (int i = 0; i <= MAX - 3; i++) { DP[i][0] = 1; if (i <= 100) DP[i][i] = 1; } for (int i = 1; i <= MAX - 3; i++) { for (int j = 1; j <= min(i, 100); j++) { DP[i][j] = DP[i - 1][j] + DP[i - 1][j - 1]; } } while (t--) { cin >> n; res = 0; for (int i = 1; i <= n; i++) A[i] = 0; for (int i = 1; i <= n; i++) { cin >> a; A[a]++; } for (int i = 1; i <= n; i++) { res += A[i] * DP[A[i - 1] + A[i - 2]][2]; res += DP[A[i]][2] * DP[A[i - 1] + A[i - 2]][1]; res += DP[A[i]][3]; } cout << res << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long qpow(int a, int n, int modulus) { int ret = 1; while (n) { if (n & 1) ret = ret * a % modulus; a = a * a % modulus; n >>= 1; } return ret; } int main() { int n; scanf( %d , &n); if (n < 3) puts( -1 ); else if (n == 3) puts( 210 ); else { int m = 210 - qpow(10, n - 1, 210); putchar( 1 ); if (m >= 0 && m < 10) { for (int i = 1; i < n - 1; i++) putchar( 0 ); printf( %d n , m); } else if (m >= 10 && m < 100) { for (int i = 1; i < n - 2; i++) putchar( 0 ); printf( %d n , m); } else { for (int i = 1; i < n - 3; i++) putchar( 0 ); printf( %d n , m); } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long n; cin >> n; if (n == 1) { cout << 1; return 0; } for (long long i = 2; i * i <= n; i++) { if (n % i == 0) { while (n % i == 0) { n /= i; } if (n == 1) { cout << i; } else { cout << 1; } getchar(); getchar(); return 0; } } cout << n; getchar(); getchar(); } |
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2004 Xilinx, Inc.
// All Rights Reserved
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 1.01
// \ \ Filename: uart_clock.v
// / / Date Last Modified: 08/04/2004
// /___/ /\ Date Created: 10/xx/2002
// \ \ / \
// \___\/\___\
//
//Device: Xilinx
//Purpose:
// KCPSM3 reference design - Real Time Clock with UART communications
// The design demonstrates the following:-
// Connection of KCPSM3 to Program ROM
// Connection of UART macros supplied with PicoBlaze with
// Baud rate generation
// Definition of input and output ports with
// Minimum decoding
// Pipelining where appropriate
// Interrupt circuit with
// Simple fixed period timer
// Automatic clearing using interrupt acknowledge from KCPSM3
//
// The design is set up for a 50MHz system clock and UART communications
// rate of 38400 baud.
//
// Please read design documentation to modify to your own requirements.
//
//Reference:
// None
//Revision History:
// Rev 1.00 - kc - Start of design entry in VHDL, 10/xx/2002.
// Rev 1.01 - sus - Converted to verilog, 08/04/2004.
////////////////////////////////////////////////////////////////////////////////
// Contact: e-mail
//////////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
// LIMITED WARRANTY AND DISCLAIMER. These designs are
// provided to you "as is". Xilinx and its licensors make and you
// receive no warranties or conditions, express, implied,
// statutory or otherwise, and Xilinx specifically disclaims any
// implied warranties of merchantability, non-infringement, or
// fitness for a particular purpose. Xilinx does not warrant that
// the functions contained in these designs will meet your
// requirements, or that the operation of these designs will be
// uninterrupted or error free, or that defects in the Designs
// will be corrected. Furthermore, Xilinx does not warrant or
// make any representations regarding use or the results of the
// use of the designs in terms of correctness, accuracy,
// reliability, or otherwise.
//
// LIMITATION OF LIABILITY. In no event will Xilinx or its
// licensors be liable for any loss of data, lost profits, cost
// or procurement of substitute goods or services, or for any
// special, incidental, consequential, or indirect damages
// arising from the use or operation of the designs or
// accompanying documentation, however caused and on any theory
// of liability. This limitation will apply even if Xilinx
// has been advised of the possibility of such damage. This
// limitation shall apply not-withstanding the failure of the
// essential purpose of any limited remedies herein.
//////////////////////////////////////////////////////////////////////////////////
module uart_clock
( tx,
rx,
alarm,
clk);
output tx;
input rx;
output alarm;
input clk;
wire tx;
wire rx;
reg alarm;
wire clk;
//
//----------------------------------------------------------------------------------
//
// declaration of KCPSM3
//
//
// declaration of program ROM
//
//
// declaration of UART transmitter with integral 16 byte FIFO buffer
//
//
// declaration of UART Receiver with integral 16 byte FIFO buffer
//
//
//----------------------------------------------------------------------------------
//
// Signals used to connect KCPSM3 to program ROM and I/O logic
//
wire [9:0] address;
wire [17:0] instruction;
wire [7:0] port_id;
wire [7:0] out_port;
reg [7:0] in_port;
wire write_strobe;
wire read_strobe;
reg interrupt;
wire interrupt_ack;
// Signals for connection of peripherals
wire [7:0] uart_status_port;
// Signals to form an timer generating an interrupt every microsecond
reg [6:0] timer_count;
reg timer_pulse;
// Signals for UART connections
reg [9:0] baud_count;
reg en_16_x_baud;
wire write_to_uart;
wire tx_full;
wire tx_half_full;
reg read_from_uart;
wire [7:0] rx_data;
wire rx_data_present;
wire rx_full;
wire rx_half_full;
//----------------------------------------------------------------------------------------------------------------------------------------------------------------------
//
// Start of circuit description
//
//
//--------------------------------------------------------------------------------------------------------------------------------
// KCPSM3 and the program memory
//--------------------------------------------------------------------------------------------------------------------------------
//
kcpsm3 processor
( .address(address),
.instruction(instruction),
.port_id(port_id),
.write_strobe(write_strobe),
.out_port(out_port),
.read_strobe(read_strobe),
.in_port(in_port),
.interrupt(interrupt),
.interrupt_ack(interrupt_ack),
.reset(1'b0),
.clk(clk));
uclock program_rom
( .address(address),
.instruction(instruction),
.clk(clk));
//
//--------------------------------------------------------------------------------------------------------------------------------
// Interrupt
//--------------------------------------------------------------------------------------------------------------------------------
//
//
// Interrupt is a generated once every 50 clock cycles to provide a 1us reference.
// Interrupt is automatically cleared by interrupt acknowledgment from KCPSM3.
//
//
always @(posedge clk) begin
if (timer_count==49)
begin
timer_count <= 1'b0;
timer_pulse <= 1'b1;
end
else
begin
timer_count <= timer_count + 1;
timer_pulse <= 1'b0;
end
if (interrupt_ack == 1'b1)
begin
interrupt <= 1'b0;
end
else if (timer_pulse == 1'b1)
begin
interrupt <= 1'b1;
end
else
begin
interrupt <= interrupt;
end
end
//--------------------------------------------------------------------------------------------------------------------------------
// KCPSM3 input ports
//--------------------------------------------------------------------------------------------------------------------------------
//
//
// UART FIFO status signals to form a bus
//
assign uart_status_port = {3'b 000,rx_data_present,rx_full,rx_half_full,tx_full,tx_half_full};
//
// The inputs connect via a pipelined multiplexer
//
always @(posedge clk) begin
case(port_id[0] )
// read UART status at address 00 hex
1'b 0 :
begin
in_port <= uart_status_port;
end
// read UART receive data at address 01 hex
1'b 1 :
begin
in_port <= rx_data;
end
// Don't care used for all other addresses to ensure minimum logic implementation
default :
begin
in_port <= 8'b XXXXXXXX;
end
endcase
// Form read strobe for UART receiver FIFO buffer.
// The fact that the read strobe will occur after the actual data is read by
// the KCPSM3 is acceptable because it is really means 'I have read you'!
read_from_uart <= read_strobe & port_id[0] ;
end
//--------------------------------------------------------------------------------------------------------------------------------
// KCPSM3 output ports
//--------------------------------------------------------------------------------------------------------------------------------
//
// adding the output registers to the clock processor
always @(posedge clk) begin
if(write_strobe == 1'b 1) begin
// Alarm register at address 00 hex with data bit0 providing control
if(port_id[0] == 1'b 0) begin
alarm <= out_port[0] ;
end
end
end
//
// write to UART transmitter FIFO buffer at address 01 hex.
// This is a combinatorial decode because the FIFO is the 'port register'.
//
assign write_to_uart = write_strobe & port_id[0] ;
//
//--------------------------------------------------------------------------------------------------------------------------------
// UART
//--------------------------------------------------------------------------------------------------------------------------------
//
// Connect the 8-bit, 1 stop-bit, no parity transmit and receive macros.
// Each contains an embedded 16-byte FIFO buffer.
//
uart_tx transmit
( .data_in(out_port),
.write_buffer(write_to_uart),
.reset_buffer(1'b0),
.en_16_x_baud(en_16_x_baud),
.serial_out(tx),
.buffer_full(tx_full),
.buffer_half_full(tx_half_full),
.clk(clk));
uart_rx receive
( .serial_in(rx),
.data_out(rx_data),
.read_buffer(read_from_uart),
.reset_buffer(1'b0),
.en_16_x_baud(en_16_x_baud),
.buffer_data_present(rx_data_present),
.buffer_full(rx_full),
.buffer_half_full(rx_half_full),
.clk(clk));
// Set baud rate to 96 for the UART communications
// Requires en_16_x_baud to be 153600Hz which is a single cycle pulse every 325 cycles at 50MHz
//
// NOTE : If the highest value for baud_count exceeds 127 you will need to adjust
// the width in the reg declaration for baud_count.
//
//--------------------------------------------------------------------------------------------------------------------------------
always @(posedge clk) begin
if (baud_count == 324)
begin
baud_count <= 1'b0;
en_16_x_baud <= 1'b1;
end
else
begin
baud_count <= baud_count + 1;
en_16_x_baud <= 1'b0;
end
end
endmodule
//----------------------------------------------------------------------------------------------------------------------------------
//
// END OF FILE uart_clock.v
//
//----------------------------------------------------------------------------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; const int p[] = {1, 2, 2, 1}; const int q[] = {1, 1, 2, 2}; const int N = 500005; int n, m; int a[N], b[N]; long long ans; void check(int& a, int b) { if (!a) a = b; else if (a != b) ans = 0; } int F(int a, int b) { return (b & 1) ? a : 3 - a; } int main() { scanf( %d%d n , &n, &m); ans = 1; char ch; int k; for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { scanf( %c , &ch); if (ch == . ) continue; k = ch - 1 ; check(a[j], F(p[k], i)); check(b[i], F(q[k], j)); } scanf( n ); } for (int i = 1; i <= n; ++i) for (int j = 1; j <= m; ++j) (ans *= ((i == 1 && !a[j]) + 1) * ((j == 1 && !b[i]) + 1)) %= 1000003; printf( %I64d n , ans); return 0; } |
module mandelbrot_iter(in_real, in_imag, c_real, c_imag, out_real, out_imag, size_square, iters_in, iters_out);
parameter width = 20;
input signed [width - 1:0] in_real;
input signed [width - 1:0] in_imag;
input signed [width - 1:0] c_real;
input signed [width - 1:0] c_imag;
input unsigned [7:0] iters_in;
output signed [width - 1:0] out_real;
output signed [width - 1:0] out_imag;
output signed [width - 1:0] size_square;
output unsigned [7:0] iters_out;
wire signed [width - 1:0] real_square;
wire signed [width - 1:0] imag_square;
wire signed [width - 1:0] mixed;
fixed_multiplication m1(in_real, in_real, real_square);
fixed_multiplication m2(in_imag, in_imag, imag_square);
fixed_multiplication m3(in_real, in_imag, mixed);
assign out_real = real_square - imag_square + c_real;
assign out_imag = (mixed * 2) + c_imag;
assign size_square = real_square + imag_square;
assign iters_out = size_square >= 32'h1000 ? iters_in : iters_in + 1;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int dp[100005]; vector<int> t; vector<pair<int, int> > p; int r, n; cin >> r >> n; t.push_back(0); p.push_back(make_pair(1, 1)); for (int i = 0; i < n; i++) { dp[i] = 0; int x, y; cin >> x; t.push_back(x); cin >> x >> y; p.push_back(make_pair(x, y)); } int maxi = 0, ans = 0; dp[n] = 0; for (int i = n; i >= 0; i--) { for (int j = i - 1; j >= max(0, i - 2000); j--) { int dif = abs(p[i].first - p[j].first) + abs(p[i].second - p[j].second); if (dif <= abs(t[i] - t[j])) { dp[j] = max(dp[j], dp[i] + 1); } } } cout << dp[0] << endl; return 0; } |
module dyn_pll_ctrl # (parameter SPEED_MHZ = 25, parameter SPEED_LIMIT = 100, parameter SPEED_MIN = 25, parameter OSC_MHZ = 100)
(clk,
clk_valid,
speed_in,
start,
progclk,
progdata,
progen,
reset,
locked,
status);
input clk; // NB Assumed to be 12.5MHz uart_clk
input clk_valid; // Drive from LOCKED output of first dcm (ie uart_clk valid)
input [7:0] speed_in;
input start;
output reg progclk = 0;
output reg progdata = 0;
output reg progen = 0;
output reg reset = 0;
input locked;
input [2:1] status;
// NB spec says to use (dval-1) and (mval-1), but I don't think we need to be that accurate
// and this saves an adder. Feel free to amend it.
reg [23:0] watchdog = 0;
reg [7:0] state = 0;
reg [7:0] dval = OSC_MHZ; // Osc clock speed (hence mval scales in MHz)
reg [7:0] mval = SPEED_MHZ;
reg start_d1 = 0;
always @ (posedge clk)
begin
progclk <= ~progclk;
start_d1 <= start;
reset <= 1'b0;
// Watchdog is just using locked, perhaps also need | ~status[2]
if (locked)
watchdog <= 0;
else
watchdog <= watchdog + 1'b1;
if (watchdog[23]) // Approx 670mS at 12.5MHz - NB spec is 5ms to lock at >50MHz CLKIN (50ms at <50MHz CLKIN)
begin // but allow longer just in case
watchdog <= 0;
reset <= 1'b1; // One cycle at 12.5MHz should suffice (requirment is 3 CLKIN at 100MHz)
end
if (~clk_valid) // Try not to run while clk is unstable
begin
progen <= 0;
progdata <= 0;
state <= 0;
end
else
begin
// The documentation is unclear as to whether the DCM loads data on positive or negative edge. The timing
// diagram unhelpfully shows data changing on the positive edge, which could mean either its sampled on
// negative, or it was clocked on positive! However the following (WRONGLY) says NEGATIVE ...
// http://forums.xilinx.com/t5/Spartan-Family-FPGAs/Spartan6-DCM-CLKGEN-does-PROGCLK-have-a-maximum-period-minimum/td-p/175642
// BUT this can lock up the DCM, positive clock seems more reliable (but it can still lock up for low values of M, eg 2).
// Added SPEED_MIN to prevent this (and positive clock is correct, after looking at other implementations eg ztex/theseven)
if ((start || start_d1) && state==0 && speed_in >= SPEED_MIN && speed_in <= SPEED_LIMIT && progclk==1) // positive clock
// if ((start || start_d1) && state==0 && speed_in >= SPEED_MIN && speed_in <= SPEED_LIMIT && progclk==0) // negative clock
begin
progen <= 0;
progdata <= 0;
mval <= speed_in;
dval <= OSC_MHZ;
state <= 1;
end
if (state != 0)
state <= state + 1'd1;
case (state) // Even values to sync with progclk
// Send D
2: begin
progen <= 1;
progdata <= 1;
end
4: begin
progdata <= 0;
end
6,8,10,12,14,16,18,20: begin
progdata <= dval[0];
dval[6:0] <= dval[7:1];
end
22: begin
progen <= 0;
progdata <= 0;
end
// Send M
32: begin
progen <= 1;
progdata <= 1;
end
36,38,40,42,44,46,48,50: begin
progdata <= mval[0];
mval[6:0] <= mval[7:1];
end
52: begin
progen <= 0;
progdata <= 0;
end
// Send GO - NB 1 clock cycle
62: begin
progen <= 1;
end
64: begin
progen <= 0;
end
// We should wait on progdone/locked, but just go straight back to idle
254: begin
state <= 0;
end
endcase
end
end
endmodule
|
module axis_control_if
#(
parameter C_s_axis_TDATA_WIDTH = 32,
parameter C_m_axis_TDATA_WIDTH = 32,
parameter C_m_axis_START_COUNT = 32,
parameter C_S_AXIS_RXS_TDATA_WIDTH = 32,
parameter C_M_AXIS_TXC_TDATA_WIDTH = 32,
parameter C_m_axis_txc_START_COUNT = 32,
parameter ENABLE_LEN = 1
)
(
// Ports of Axi Master Bus Interface m_axis
input m_axis_txd_tvalid,
input m_axis_txd_tlast,
input m_axis_txd_tready,
input [11:0] tx_pkt_byte_cnt,
input tx_pkt_byte_cnt_vld,
input s_axis_rxs_aclk,
input s_axis_rxs_aresetn,
output s_axis_rxs_tready,
input [C_S_AXIS_RXS_TDATA_WIDTH-1 : 0] s_axis_rxs_tdata,
input [(C_S_AXIS_RXS_TDATA_WIDTH/8)-1 : 0] s_axis_rxs_tkeep,
input s_axis_rxs_tlast,
input s_axis_rxs_tvalid,
input m_axis_txc_aclk,
input m_axis_txc_aresetn,
output reg m_axis_txc_tvalid,
output reg [C_M_AXIS_TXC_TDATA_WIDTH-1 : 0] m_axis_txc_tdata,
output reg [(C_M_AXIS_TXC_TDATA_WIDTH/8)-1 : 0] m_axis_txc_tkeep,
output reg m_axis_txc_tlast,
input m_axis_txc_tready
);
reg [2:0] tx_ctrl_state;
localparam WAIT_FOR_REQ = 1,
SEND_CTRL_PKTS = 2,
WAIT_FOR_NXT = 4;
reg [7:0] send_ctrl_words;
localparam WORD0 = 1,
WORD1 = 2,
WORD2 = 4,
WORD3 = 8,
WORD4 = 16,
WORD5 = 32;
assign s_axis_rxs_tready = 1'b1;
reg len_fifo_rd_en;
wire [11:0] len_fifo_dout;
generate
if(ENABLE_LEN)begin
small_fifo
#( .WIDTH(12),
.MAX_DEPTH_BITS(5))
pkt_len_fifo
(
.clk(m_axis_txc_aclk),
.reset(!m_axis_txc_aresetn),
.din(tx_pkt_byte_cnt),
.wr_en(tx_pkt_byte_cnt_vld),
.rd_en(len_fifo_rd_en),
.dout(len_fifo_dout),
.full( ),
.prog_full(),
.nearly_full(),
.empty( )
);
end
else begin
assign len_fifo_dout = 12'hFFF;
end
endgenerate
always@(posedge m_axis_txc_aclk)
if(!m_axis_txc_aresetn)
len_fifo_rd_en <= 1'b0;
else if(tx_pkt_byte_cnt_vld)
len_fifo_rd_en <= 1'b1;
else len_fifo_rd_en<=0;
always @(posedge m_axis_txc_aclk)
if(!m_axis_txc_aresetn)begin
tx_ctrl_state <= WAIT_FOR_REQ;
send_ctrl_words <= WORD0;
m_axis_txc_tvalid <= 1'b0;
m_axis_txc_tdata <= 32'hFF_FF_FF_FF;
m_axis_txc_tkeep <= 4'hF;
m_axis_txc_tlast <= 1'b0;
end
else begin
m_axis_txc_tvalid <= 1'b0;
m_axis_txc_tdata <= {24'h50000,len_fifo_dout};
m_axis_txc_tkeep <= 4'hF;
m_axis_txc_tlast <= 1'b0;
case (tx_ctrl_state)
WAIT_FOR_REQ: begin
if(m_axis_txd_tvalid) begin
m_axis_txc_tvalid <= 1'b1;
tx_ctrl_state <= SEND_CTRL_PKTS;
end
end
SEND_CTRL_PKTS: begin
m_axis_txc_tvalid <= 1'b1;
if(m_axis_txc_tready) begin
case (send_ctrl_words)
WORD0: send_ctrl_words <= WORD1;
WORD1: send_ctrl_words <= WORD2;
WORD2: send_ctrl_words <= WORD3;
WORD3: send_ctrl_words <= WORD4;
WORD4: begin
send_ctrl_words <= WORD0;
m_axis_txc_tlast <= 1'b1;
tx_ctrl_state <= WAIT_FOR_NXT;
end
endcase
end
end
WAIT_FOR_NXT: begin
if(m_axis_txd_tready && m_axis_txd_tlast)tx_ctrl_state <= WAIT_FOR_REQ;
end
default:
tx_ctrl_state<=WAIT_FOR_REQ;
endcase
end
endmodule |
#include <bits/stdc++.h> using namespace std; int place_to_score[] = {25, 18, 15, 12, 10, 8, 6, 4, 2, 1}; int t, n; map<string, int> ids; int next_id = 1; char names[50][64]; char tmp[64]; int score[50]; int places[50][50]; int main() { scanf( %d , &t); for (int i = 0; i < t; i++) { scanf( %d , &n); int place = 0; for (int j = 0; j < n; j++) { scanf( %s , tmp); int id = ids[tmp]; if (!id) { ids[tmp] = id = next_id++; strcpy(names[id - 1], tmp); } id--; if (place < 10) score[id] += place_to_score[place]; places[id][place]++; place++; } } vector<int> best; int points = -1; for (int i = 0; i < next_id - 1; i++) { if (score[i] > points) { best.clear(); points = score[i]; } if (score[i] == points) best.push_back(i); } for (int place = 0; best.size() > 1 && place < next_id - 1; place++) { vector<int> new_best; points = -1; for (int i = 0; i < best.size(); i++) { if (places[best[i]][place] > points) { new_best.clear(); points = places[best[i]][place]; } if (places[best[i]][place] == points) new_best.push_back(best[i]); } best = new_best; } printf( %s n , names[best[0]]); best.clear(); points = -1; for (int i = 0; i < next_id - 1; i++) { if (places[i][0] > points) { best.clear(); points = places[i][0]; } if (places[i][0] == points) best.push_back(i); } if (best.size() > 1) { vector<int> new_best; points = -1; for (int i = 0; i < best.size(); i++) { if (score[best[i]] > points) { new_best.clear(); points = score[best[i]]; } if (score[best[i]] == points) new_best.push_back(best[i]); } best = new_best; } for (int place = 1; best.size() > 1 && place < next_id - 1; place++) { vector<int> new_best; points = -1; for (int i = 0; i < best.size(); i++) { if (places[best[i]][place] > points) { new_best.clear(); points = places[best[i]][place]; } if (places[best[i]][place] == points) new_best.push_back(best[i]); } best = new_best; } printf( %s n , names[best[0]]); } |
module test(input wire load, in,
output reg out1, out2);
(* ivl_combinational *)
always @* begin
out1 = 0;
if (load) begin
out1 = in;
out2 = in;
end else begin
out2 = ~in;
end
end
endmodule // test
module test_bench;
reg load;
reg val;
wire out1, out2;
test DUT(.load(load), .in(val), .out1(out1), .out2(out2));
(* ivl_synthesis_off *)
initial begin
val = 0;
load = 1;
#1 ;
if (out1 !== 0 || out2 !== 0) begin
$display("FAILED -- load=%b, val=%b, out1=%b, out2=%b", load, val, out1, out2);
$finish;
end
val = 1;
#1 ;
if (out1 !== 1 || out2 !== 1) begin
$display("FAILED -- load=%b, val=%b, out1=%b, out2=%b", load, val, out1, out2);
$finish;
end
load = 0;
#1 ;
if (out1 !== 0 || out2 !== 0) begin
$display("FAILED -- load=%b, val=%b, out1=%b, out2=%b", load, val, out1, out2);
$finish;
end
val = 0;
#1 ;
if (out1 !== 0 || out2 !== 1) begin
$display("FAILED -- load=%b, val=%b, out1=%b, out2=%b", load, val, out1, out2);
$finish;
end
$display("PASSED");
end // initial begin
endmodule // test_bench
|
#include <bits/stdc++.h> using namespace std; inline long long read() { long long x = 0, f = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { x = (x << 3) + (x << 1) + (c ^ 48); c = getchar(); } return f == 1 ? x : -x; } inline void print(long long x) { if (x < 0) putchar( - ), x = ~x + 1; if (x >= 10) print(x / 10); putchar((x % 10) | 48); } long long n; struct node { long long x, y; } a[2510], v[5010]; long long xiangxian(node x) { if (x.x >= 0) { if (x.y >= 0) return 1; else return 4; } else { if (x.y >= 0) return 2; else return 3; } } long long cross(node x, node y) { return x.x * y.y - y.x * x.y; } bool cmp(node x, node y) { long long x1 = xiangxian(x); long long x2 = xiangxian(y); if (x1 != x2) return x1 < x2; else return cross(x, y) > 0; } long long ans; long long C(long long x, long long y) { if (x < 0) return 0; long long res = 1; for (long long i = 1; i <= y; ++i) res *= (x - i + 1); for (long long i = 1; i <= y; ++i) res /= i; return res; } signed main() { n = read(); for (long long i = 1; i <= n; ++i) a[i].x = read(), a[i].y = read(); for (long long i = 1; i <= n; ++i) { long long cnt = 0; for (long long j = 1; j <= n; ++j) { if (j == i) continue; v[++cnt].x = a[j].x - a[i].x; v[cnt].y = a[j].y - a[i].y; } sort(v + 1, v + cnt + 1, cmp); for (long long j = 1; j <= cnt; ++j) v[j + cnt] = v[j]; long long lst = 1; for (long long j = cnt + 1; j <= 2 * cnt; ++j) { while (lst + cnt < j || cross(v[j], v[lst + 1]) >= 0) { ++lst; if (lst + 1 == j) break; } ans += C(j - lst - 1, 3); } } print(5 * C(n, 5) - ans); } |
#include <bits/stdc++.h> using namespace std; const long long MOD = 998244353; const int MAXN = 1000100; long long mpow(long long b, int e) { if (e == 0) return 1; long long v = mpow(b, e / 2); v = (v * v) % MOD; if (e & 1) v = (v * b) % MOD; return v; } long long inv(long long b) { return mpow(b % MOD, MOD - 2); } int N; vector<int> v[MAXN]; int ct[MAXN]; int main() { ios_base::sync_with_stdio(0); cin >> N; for (int i = 0; i < N; i++) { int K; cin >> K; for (int j = 0; j < K; j++) { int x; cin >> x; v[i].push_back(x); ct[x]++; } } long long res = 0; for (int i = 0; i < N; i++) { for (int cv : v[i]) { long long prob = (inv(v[i].size() * (long long)N)) % MOD; prob = (prob * ct[cv]) % MOD; prob = (prob * inv(N)) % MOD; res = (res + prob) % MOD; } } cout << res << n ; } |
// -----------------------------------------------------------------------------
// -- --
// -- (C) 2016-2022 Revanth Kamaraj (krevanth) --
// -- --
// -- --------------------------------------------------------------------------
// -- --
// -- This program is free software; you can redistribute it and/or --
// -- modify it under the terms of the GNU General Public License --
// -- as published by the Free Software Foundation; either version 2 --
// -- of the License, or (at your option) any later version. --
// -- --
// -- This program is distributed in the hope that it will be useful, --
// -- but WITHOUT ANY WARRANTY; without even the implied warranty of --
// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
// -- GNU General Public License for more details. --
// -- --
// -- You should have received a copy of the GNU General Public License --
// -- along with this program; if not, write to the Free Software --
// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA --
// -- 02110-1301, USA. --
// -- --
// -----------------------------------------------------------------------------
// -- --
// -- Implements a 16-bit instruction decoder. The 16-bit instruction set is --
// -- not logically organized so as to save on encoding and thus the code --
// -- seem a bit complex. --
// -- --
// -----------------------------------------------------------------------------
`default_nettype none
module zap_thumb_decoder_main (
// Clock and reset.
input wire i_clk,
input wire i_reset,
// Code stall.
input wire i_clear_from_writeback,
input wire i_data_stall,
input wire i_clear_from_alu,
input wire i_stall_from_shifter,
input wire i_stall_from_issue,
input wire i_stall_from_decode,
input wire i_clear_from_decode,
// Predictor status.
input wire [1:0] i_taken,
// Input from I-cache.
// Instruction and valid qualifier.
input wire [31:0] i_instruction,
input wire i_instruction_valid,
// Interrupts. Active high level sensitive signals.
input wire i_irq,
input wire i_fiq,
// Aborts.
input wire i_iabort,
output reg o_iabort,
// Ensure compressed mode is active (T bit).
input wire i_cpsr_ff_t,
// Program counter.
input wire [31:0] i_pc_ff,
input wire [31:0] i_pc_plus_8_ff,
//
// Outputs to the ARM decoder.
//
// Instruction, valid, undefined by this decoder and force 32-bit
// align signals (requires memory to keep lower 2 bits as 00).
output reg [34:0] o_instruction,
output reg o_instruction_valid,
output reg o_und,
output reg o_force32_align,
// PCs.
output reg [31:0] o_pc_ff,
output reg [31:0] o_pc_plus_8_ff,
// Interrupt status output.
output reg o_irq,
output reg o_fiq,
// Taken
output reg [1:0] o_taken_ff
);
`include "zap_defines.vh"
`include "zap_localparams.vh"
`include "zap_functions.vh"
wire [34:0] instruction_nxt;
wire instruction_valid_nxt;
wire und_nxt;
wire force32_nxt;
wire irq_nxt;
wire fiq_nxt;
reg [1:0] taken_nxt;
zap_thumb_decoder u_zap_thumb_decoder (
.i_instruction(i_instruction),
.i_instruction_valid(i_instruction_valid),
.i_irq(i_irq),
.i_fiq(i_fiq),
.i_offset(o_instruction[11:0]),
.i_cpsr_ff_t(i_cpsr_ff_t),
.o_instruction(instruction_nxt),
.o_instruction_valid(instruction_valid_nxt),
.o_und(und_nxt),
.o_force32_align(force32_nxt),
.o_irq(irq_nxt),
.o_fiq(fiq_nxt)
);
always @ (posedge i_clk)
begin
if ( i_reset )
begin
reset;
o_instruction_valid <= 1'd0;
o_irq <= 0;
o_fiq <= 0;
o_und <= 0;
o_iabort <= 0;
end
else if ( i_clear_from_writeback )
begin
o_instruction_valid <= 1'd0;
o_irq <= 0;
o_fiq <= 0;
o_und <= 0;
o_iabort <= 0;
end
else if ( i_data_stall )
begin
end
else if ( i_clear_from_alu )
begin
o_instruction_valid <= 1'd0;
o_irq <= 0;
o_fiq <= 0;
o_und <= 0;
o_iabort <= 0;
end
else if ( i_stall_from_shifter ) begin end
else if ( i_stall_from_issue ) begin end
else if ( i_stall_from_decode ) begin end
else if ( i_clear_from_decode )
begin
o_instruction_valid <= 1'd0;
o_irq <= 0;
o_fiq <= 0;
o_und <= 0;
o_iabort <= 0;
end
else // BUG FIX.
begin
o_iabort <= i_iabort;
o_instruction_valid <= instruction_valid_nxt;
o_instruction <= instruction_nxt;
o_und <= und_nxt;
o_force32_align <= force32_nxt;
o_pc_ff <= i_pc_ff;
o_pc_plus_8_ff <= i_pc_plus_8_ff;
o_irq <= irq_nxt;
o_fiq <= fiq_nxt;
o_taken_ff <= i_taken;
end
end
task reset;
begin
o_iabort <= 0;
o_instruction_valid <= 0;
o_instruction <= 0;
o_und <= 0;
o_force32_align <= 0;
o_pc_ff <= 0;
o_pc_plus_8_ff <= 0;
o_irq <= 0;
o_fiq <= 0;
o_taken_ff <= 0;
end
endtask
// Helpful for debug.
zap_decompile u_zap_decompile (
.i_instruction ({1'd0, o_instruction}),
.i_dav (o_instruction_valid),
.o_decompile ()
);
endmodule // zap_thumb_decoder_main
`default_nettype wire
// ----------------------------------------------------------------------------
// EOF
// ----------------------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; long long bigmod(long long b, long long p, long long m) { if (p == 0) return 1; if (p % 2 == 0) { long long temp = bigmod(b, p / 2, m); return (temp * temp) % m; } return (bigmod(b, p - 1, m) * (b % m)) % m; } int main() { string s; cin >> s; int n = s.length(); long long cnt = 0; long long ans = 0; long long mod = 1e9 + 7; for (int i = 0; i < n; i++) { if (s[i] == a ) { cnt++; } else { if (cnt > 0) ans += (bigmod(2, cnt, mod) - 1); ans %= mod; } } cout << ans << endl; } |
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// --------------------------------------------------------------------------------
//| Avalon ST Bytes to Packet
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module altera_avalon_st_bytes_to_packets
//if ENCODING ==0, CHANNEL_WIDTH must be 8
//else CHANNEL_WIDTH can be from 0 to 127
#( parameter CHANNEL_WIDTH = 8,
parameter ENCODING = 0 )
(
// Interface: clk
input clk,
input reset_n,
// Interface: ST out with packets
input out_ready,
output reg out_valid,
output reg [7: 0] out_data,
output reg [CHANNEL_WIDTH-1: 0] out_channel,
output reg out_startofpacket,
output reg out_endofpacket,
// Interface: ST in
output reg in_ready,
input in_valid,
input [7: 0] in_data
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg received_esc, received_channel, received_varchannel;
wire escape_char, sop_char, eop_char, channel_char, varchannelesc_char;
// data out mux.
// we need it twice (data & channel out), so use a wire here
wire [7:0] data_out;
// ---------------------------------------------------------------------
//| Thingofamagick
// ---------------------------------------------------------------------
assign sop_char = (in_data == 8'h7a);
assign eop_char = (in_data == 8'h7b);
assign channel_char = (in_data == 8'h7c);
assign escape_char = (in_data == 8'h7d);
assign data_out = received_esc ? (in_data ^ 8'h20) : in_data;
generate
if (CHANNEL_WIDTH == 0) begin
// Synchorous block -- reset and registers
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
received_esc <= 0;
out_startofpacket <= 0;
out_endofpacket <= 0;
end else begin
// we take data when in_valid and in_ready
if (in_valid & in_ready) begin
if (received_esc) begin
//if we got esc char, after next byte is consumed, quit esc mode
if (out_ready) received_esc <= 0;
end else begin
if (escape_char) received_esc <= 1;
if (sop_char) out_startofpacket <= 1;
if (eop_char) out_endofpacket <= 1;
end
if (out_ready & out_valid) begin
out_startofpacket <= 0;
out_endofpacket <= 0;
end
end
end
end
// Combinational block for in_ready and out_valid
always @* begin
//we choose not to pipeline here. We can process special characters when
//in_ready, but in a chain of microcores, backpressure path is usually
//time critical, so we keep it simple here.
in_ready = out_ready;
//out_valid when in_valid, except when we are processing the special
//characters. However, if we are in escape received mode, then we are
//valid
out_valid = 0;
if ((out_ready | ~out_valid) && in_valid) begin
out_valid = 1;
if (sop_char | eop_char | escape_char | channel_char) out_valid = 0;
end
out_data = data_out;
end
end else begin
assign varchannelesc_char = in_data[7];
// Synchorous block -- reset and registers
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
received_esc <= 0;
received_channel <= 0;
received_varchannel <= 0;
out_startofpacket <= 0;
out_endofpacket <= 0;
end else begin
// we take data when in_valid and in_ready
if (in_valid & in_ready) begin
if (received_esc) begin
//if we got esc char, after next byte is consumed, quit esc mode
if (out_ready | received_channel | received_varchannel) received_esc <= 0;
end else begin
if (escape_char) received_esc <= 1;
if (sop_char) out_startofpacket <= 1;
if (eop_char) out_endofpacket <= 1;
if (channel_char & ENCODING ) received_varchannel <= 1;
if (channel_char & ~ENCODING) received_channel <= 1;
end
if (received_channel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char ))) begin
received_channel <= 0;
end
if (received_varchannel & ~varchannelesc_char & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char))) begin
received_varchannel <= 0;
end
if (out_ready & out_valid) begin
out_startofpacket <= 0;
out_endofpacket <= 0;
end
end
end
end
// Combinational block for in_ready and out_valid
always @* begin
in_ready = out_ready;
out_valid = 0;
if ((out_ready | ~out_valid) && in_valid) begin
out_valid = 1;
if (received_esc) begin
if (received_channel | received_varchannel) out_valid = 0;
end else begin
if (sop_char | eop_char | escape_char | channel_char | received_channel | received_varchannel) out_valid = 0;
end
end
out_data = data_out;
end
end
endgenerate
// Channel block
generate
if (CHANNEL_WIDTH == 0) begin
always @(posedge clk) begin
out_channel <= 'h0;
end
end else if (CHANNEL_WIDTH < 8) begin
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
out_channel <= 'h0;
end else begin
if (in_ready & in_valid) begin
if ((channel_char & ENCODING) & (~received_esc & ~sop_char & ~eop_char & ~escape_char )) begin
out_channel <= 'h0;
end else if (received_varchannel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char & ~received_channel))) begin
// Shifting out only the required bits
out_channel[CHANNEL_WIDTH-1:0] <= data_out[CHANNEL_WIDTH-1:0];
end
end
end
end
end else begin
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
out_channel <= 'h0;
end else begin
if (in_ready & in_valid) begin
if (received_channel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char))) begin
out_channel <= data_out;
end else if ((channel_char & ENCODING) & (~received_esc & ~sop_char & ~eop_char & ~escape_char )) begin
// Variable Channel Encoding always setting to 0 before begin to shift the channel in
out_channel <= 'h0;
end else if (received_varchannel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char & ~received_channel))) begin
// Shifting out the lower 7 bits
out_channel <= out_channel <<7;
out_channel[6:0] <= data_out[6:0];
end
end
end
end
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); int n, m, q; cin >> n >> m >> q; vector<vector<pair<int, int>>> pos(n, vector<pair<int, int>>(m)); for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { pos[i][j] = {i, j}; } } vector<vector<int>> val(n, vector<int>(m, 0)); for (int i = 0; i < q; ++i) { int t; cin >> t; if (t == 1) { int r; cin >> r; --r; auto tmp = pos[r][0]; for (int i = 1; i < m; ++i) { pos[r][i - 1] = pos[r][i]; } pos[r][m - 1] = tmp; } else if (t == 2) { int c; cin >> c; --c; auto tmp = pos[0][c]; for (int i = 1; i < n; ++i) { pos[i - 1][c] = pos[i][c]; } pos[n - 1][c] = tmp; } else { int r, c, x; cin >> r >> c >> x; --r, --c; auto p = pos[r][c]; val[p.first][p.second] = x; } } for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { cout << val[i][j] << ; } cout << endl; } } |
#include <bits/stdc++.h> using namespace std; inline int read() { int x = 0, f = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { x = (x << 1) + (x << 3) + c - 0 ; c = getchar(); } return x * f; } const int maxn = 305; int n, a[maxn][maxn]; int dp[maxn << 1][maxn][maxn]; int main() { n = read(); for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) a[i][j] = read(); memset(dp, 0x8f, sizeof(dp)); dp[0][1][1] = a[1][1]; for (int i = 1; i <= 2 * n - 2; i++) for (int j = max(1, i + 2 - n); j <= min(i + 1, n); j++) for (int k = max(1, i + 2 - n); k <= min(i + 1, n); k++) { dp[i][j][k] = max(max(dp[i - 1][j - 1][k - 1], dp[i - 1][j - 1][k]), max(dp[i - 1][j][k - 1], dp[i - 1][j][k])); dp[i][j][k] += a[j][i - j + 2]; if (j != k) dp[i][j][k] += a[k][i - k + 2]; } printf( %d n , dp[2 * n - 2][n][n]); return 0; } |
/*
-- ============================================================================
-- FILE NAME : rom.v
-- DESCRIPTION : Read Only Memory
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito VKì¬
-- ============================================================================
*/
/********** ¤Êwb_t@C **********/
`include "nettype.h"
`include "stddef.h"
`include "global_config.h"
/********** ÂÊwb_t@C **********/
`include "rom.h"
/********** W
[ **********/
module rom (
/********** NbN & Zbg **********/
input wire clk, // NbN
input wire reset, // ñ¯úZbg
/********** oXC^tF[X **********/
input wire cs_, // `bvZNg
input wire as_, // AhXXg[u
input wire [`RomAddrBus] addr, // AhX
output wire [`WordDataBus] rd_data, // ÇÝoµf[^
output reg rdy_ // fB
);
/********** Xilinx FPGA Block RAM : VO|[gROM **********/
x_s3e_sprom x_s3e_sprom (
.clka (clk), // NbN
.addra (addr), // AhX
.douta (rd_data) // ÇÝoµf[^
);
/********** fB̶¬ **********/
always @(posedge clk or `RESET_EDGE reset) begin
if (reset == `RESET_ENABLE) begin
/* ñ¯úZbg */
rdy_ <= #1 `DISABLE_;
end else begin
/* fB̶¬ */
if ((cs_ == `ENABLE_) && (as_ == `ENABLE_)) begin
rdy_ <= #1 `ENABLE_;
end else begin
rdy_ <= #1 `DISABLE_;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1000000007; const int Nmax = 100005; int count_one(vector<int> s) { int ct = 0; int i = 0; while (i < s.size()) { if (s[i] == 1) ++ct; ++i; } return ct; } int count_zero(string s, int index) { int i = 0; int ct = 0; while (s[i] != 1 && i < s.length()) { ++ct; ++i; } } int gcd(int a, int b) { if (a == 0) { return b; } return gcd(b % a, a); } bool isPrime(int n) { for (int i = 2; i <= sqrt(n); i++) if (n % i == 0) return 0; return 1; } void binaryRepresentation(int x) { for (int i = 31; i >= 0; i--) { if (x & (1 << i)) cout << 1 ; else cout << 0 ; } } void DFS(vector<vector<int> > &adj, int u, vector<bool> &visit, vector<int> &dist, vector<int> &freq) { visit[u] = true; for (int i = 0; i < adj[u].size(); i++) { int x = adj[u][i]; if (!visit[x]) { dist[x] = dist[u] + 1; freq[u]++; DFS(adj, adj[u][i], visit, dist, freq); } } } bool check(string a, string b) { vector<int> first(26, 0); vector<int> second(26, 0); for (int i = 0; i < a.length(); i++) { first[a[i] - a ]++; second[b[i] - a ]++; } if (first != second) return false; else return true; } long long combination(long long n, long long r) { if (r == n || r == 0) { return 1; } return combination(n - 1, r - 1) + combination(n - 1, r); } bool cmp(const pair<int, int> &a, const pair<int, int> &b) { if (a.second == b.second) return a.first < b.first; return a.second > b.second; } int main() { ios_base::sync_with_stdio(false); long long n, k; cin >> n >> k; vector<int> ar(n); map<long long, long long> right; map<long long, long long> left; for (long long i = 0; i < n; i++) { cin >> ar[i]; } long long ans = 0; for (long long i = n - 1; i >= 0; i--) { ans += right[ar[i] * k]; right[ar[i]] += left[ar[i] * k]; left[ar[i]]++; } cout << ans << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; string one, o, two; vector<int> a(2, 0); cin >> n; cin >> one; a[0] += 1; while (n-- > 1) { cin >> o; if (o == one) a[0] += 1; else { a[1] += 1; two = o; } } if (a[0] > a[1]) cout << one; else cout << two; return 0; } |
`include "bsg_defines.v"
module test_case #(parameter width_p, parameter banks_p) (input clk_i, input go_i, output finish_o);
reg [width_p-1:0] lo;
reg [width_p:0] in_r;
wire [$clog2((2**width_p+banks_p-1)/banks_p)-1:0] index_lo;
wire [`BSG_SAFE_CLOG2(banks_p)-1:0] bank_lo;
// bsg_nonsynth_clock_gen #(.cycle_time_p(5)) clkgen (.o(clk));
bsg_hash_bank #(.banks_p(banks_p), .width_p(width_p))
hashme (/* .clk,*/
.i( in_r[width_p-1:0] ),
// .i({in_r[1:0],in_r[5:2]}),
.bank_o(bank_lo),
.index_o(index_lo)
);
bsg_hash_bank_reverse #(.banks_p(banks_p), .width_p(width_p))
unhashme (/* .clk,*/
.o( lo ),
// .i({in_r[1:0],in_r[5:2]}),
.bank_i(bank_lo),
.index_i(index_lo)
);
initial in_r = 0;
reg finish_r;
initial finish_r = 0;
always @(posedge clk_i)
begin
if (!finish_r & go_i)
begin
in_r <= in_r + 1;
finish_r <= in_r[width_p];
end
end
assign finish_o = finish_r;
always @(negedge clk_i)
begin
// $display ("%b -> %b %b -> %b", in_r, bucket_lo, index_lo,lo);
if (lo != in_r[width_p-1:0])
$display("(%3d,%3d) MISMATCH: %b -> %b %b -> %b",width_p,banks_p,in_r[width_p-1:0],bank_lo, index_lo, lo);
else
if (!finish_r & go_i)
$display("(%3d,%3d) match: %b -> %b %b -> %b",width_p,banks_p,in_r[width_p-1:0],bank_lo, index_lo, lo);
end
endmodule // test_case
module tb(input clk_i);
localparam tests_p = 10;
wire [tests_p-1:0] finish_lo;
test_case #(6,1) tc61 (.clk_i,.finish_o(finish_lo[0]),.go_i(1));
test_case #(6,2) tc62 (.clk_i,.finish_o(finish_lo[1]),.go_i(finish_lo[0]));
test_case #(6,3) tc63 (.clk_i,.finish_o(finish_lo[2]),.go_i(finish_lo[1]));
test_case #(6,4) tc64 (.clk_i,.finish_o(finish_lo[3]),.go_i(finish_lo[2]));
test_case #(6,6) tc66 (.clk_i,.finish_o(finish_lo[4]),.go_i(finish_lo[3]));
test_case #(6,7) tc67 (.clk_i,.finish_o(finish_lo[5]),.go_i(finish_lo[4]));
test_case #(8,7) tc87 (.clk_i,.finish_o(finish_lo[6]),.go_i(finish_lo[5]));
test_case #(6,8) tc68 (.clk_i,.finish_o(finish_lo[7]),.go_i(finish_lo[6]));
test_case #(6,12) tc612 (.clk_i,.finish_o(finish_lo[8]),.go_i(finish_lo[7]));
test_case #(8,15) tc815 (.clk_i,.finish_o(finish_lo[9]),.go_i(finish_lo[8]));
always @(*)
if (&finish_lo)
$finish();
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:36:03 05/26/2014
// Design Name: mccomp
// Module Name: E://muti_cpu/test.v
// Project Name: muti_cpu
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: mccomp
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test;
// Inputs
reg clock;
reg resetn;
reg mem_clk;
// Outputs
wire [2:0] q;
wire [31:0] a;
wire [31:0] b;
wire [31:0] alu;
wire [31:0] adr;
wire [31:0] tom;
wire [31:0] fromm;
wire [31:0] pc;
wire [31:0] ir;
// Instantiate the Unit Under Test (UUT)
mccomp uut (
.clock(clock),
.resetn(resetn),
.q(q),
.a(a),
.b(b),
.alu(alu),
.adr(adr),
.tom(tom),
.fromm(fromm),
.pc(pc),
.ir(ir),
.mem_clk(mem_clk)
);
initial begin
// Initialize Inputs
clock = 0;
resetn = 0;
mem_clk = 0;
// Wait 100 ns for global reset to finish
#11; resetn = 1;
// Add stimulus here
end
initial forever begin
#1; mem_clk=~mem_clk;
#1; mem_clk=~mem_clk;clock=~clock;
end
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( -O2 ) using namespace std; void err(istream_iterator<string> it) { cerr << endl; } template <typename T, typename... Args> void err(istream_iterator<string> it, T a, Args... args) { cerr << *it << = << a << t ; err(++it, args...); } template <typename T1, typename T2> ostream& operator<<(ostream& c, pair<T1, T2>& v) { c << ( << v.first << , << v.second << ) ; return c; } template <template <class...> class TT, class... T> ostream& operator<<(ostream& out, TT<T...>& c) { out << { ; for (auto& x : c) out << x << ; out << } ; return out; } const int LIM = 1.5e3 + 5, MOD = 998244353; const long double EPS = 1e-9; int read() { int xx = 0, ff = 1; char ch = getchar(); while (ch > 9 || ch < 0 ) { if (ch == - ) ff = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { xx = (xx << 3) + (xx << 1) + ch - 0 ; ch = getchar(); } return xx * ff; } mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); int n; int link[LIM], sz[LIM], edges[LIM]; long long poly[LIM][LIM]; int find(int x) { if (x == link[x]) return x; return link[x] = find(link[x]); } void polymul(int a, int b) { long long temp[LIM] = {0}; for (int i = 0; i < n + 1; ++i) { for (int j = 0; j + i <= n; j++) { temp[i + j] += (poly[a][i] * poly[b][j]) % MOD; } } for (int i = 0; i < LIM; ++i) { poly[a][i] = temp[i] % MOD; } return; } void unite(int a, int b) { a = find(a); b = find(b); if (sz[a] < sz[b]) swap(a, b); if (a == b) { edges[a]++; if (edges[a] == sz[a] * (sz[a] - 1) / 2) { poly[a][1]++; } return; } link[b] = a; sz[a] += sz[b]; polymul(a, b); edges[a]++; edges[a] += edges[b]; if (edges[a] == sz[a] * (sz[a] - 1) / 2) { poly[a][1]++; } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n; for (int i = 0; i < n; ++i) { poly[i][1] = 1; link[i] = i; sz[i] = 1; } vector<tuple<int, int, int>> v; for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { int x; cin >> x; if (i < j) { v.push_back({x, i, j}); } } } sort(v.begin(), v.end()); for (auto& r : v) { int cost, first, second; tie(cost, first, second) = r; unite(first, second); } int a = find(0); for (int i = 1; i < n + 1; ++i) { cout << poly[a][i] % MOD << ; } cout << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; inline long long mult(long long a, long long b, long long mod) { if (b == 0) return 0; if (b % 2 == 1) return (mult(a, b - 1, mod) + a) % mod; return (mult(a, b / 2, mod) * 2) % mod; } inline long long BinPow(long long a, long long b, long long mod) { if (b == 0) return 1; if (b == 1) return a; if (b % 2 == 1) return (mult(BinPow(a, b - 1, mod), a, mod)) % mod; long long res = BinPow(a, b / 2, mod); return mult(res, res, mod); } int n, m, k, w, kol, kol1, w1, sum1; char a[150][140][130]; int sum; int main() { cin >> n >> m >> k; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) for (int t = 1; t <= k; t++) cin >> a[i][j][t]; for (int l = 1; l <= n; l++) for (int j = 1; j <= m; j++) for (int t = 1; t <= k; t++) { if (a[l][j][t] == 1 ) { if (a[l - 1][j][t] == 1 ) if (a[l + 1][j][t] == 1 ) w = 1; if (a[l][j - 1][t] == 1 ) if (a[l][j + 1][t] == 1 ) w = 1; if (a[l][j][t - 1] == 1 ) if (a[l][j][t + 1] == 1 ) w = 1; if (a[l - 1][j][t] == 1 ) { if (a[l - 1][j + 1][t] == 0 ) if (a[l][j + 1][t] == 1 ) w1 = 1; if (a[l - 1][j][t + 1] == 0 ) if (a[l][j][t + 1] == 1 ) w1 = 1; } if (a[l][j - 1][t] == 1 ) { if (a[l][j - 1][t + 1] == 0 ) if (a[l][j][t + 1] == 1 ) w1 = 1; if (a[l + 1][j - 1][t] == 0 ) if (a[l + 1][j][t] == 1 ) w1 = 1; } if (a[l][j][t - 1] == 1 ) { if (a[l][j + 1][t - 1] == 0 ) if (a[l][j + 1][t] == 1 ) w1 = 1; if (a[l + 1][j][t - 1] == 0 ) if (a[l + 1][j][t] == 1 ) w1 = 1; } if (w || w1) sum++; w1 = w = 0; } } cout << sum; return 0; } |
#include <bits/stdc++.h> using namespace std; int n; string s[6], S; bool F; int main() { cin >> S; for (int i = 1; i <= 5; ++i) cin >> s[i]; for (int i = 1; i <= 5; ++i) if (s[i][0] == S[0] || s[i][1] == S[1]) F = 1; puts(F ? YES : NO ); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND2B_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__AND2B_PP_BLACKBOX_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__and2b (
X ,
A_N ,
B ,
VPWR,
VGND
);
output X ;
input A_N ;
input B ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND2B_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; complex<double> a[524288], b[524288], r[524288], o[524289]; void fft(complex<double> *x, int n, int base) { int size = 0, mask = (n >> 1) - 1; for (int i = base - 1; i >= 0; --i, size = (size << 1) | 1, mask >>= 1) { for (int j = 0; j < n; ++j) { int front = j >> i, back = j & mask; int a = (front & size) << 1, b = a | 1; r[j] = x[(a << i) | back] + o[(front << i) * (524288 / n)] * x[(b << i) | back]; } for (int j = 0; j < n; ++j) x[j] = r[j]; } } void ifft(complex<double> *x, int n, int base) { fft(x, n, base); reverse(x + 1, x + n); for (int i = 0; i < n; ++i) x[i] /= n; } void pin(vector<int> *v) { cout << v->size() << : ; for (int i : *v) cout << i << ; cout << endl; } vector<int> *mg(vector<int> *pa, vector<int> *pb) { int nn = pa->size() + pb->size() + 2, base = 0; while ((1 << base) < nn) ++base; nn = (1 << base); for (int i = 0; i < pa->size(); ++i) a[i] = complex<double>((*pa)[i], 0); for (int i = pa->size(); i <= nn; ++i) a[i] = complex<double>(0, 0); for (int i = 0; i < pb->size(); ++i) b[i] = complex<double>((*pb)[i], 0); for (int i = pb->size(); i <= nn; ++i) b[i] = complex<double>(0, 0); fft(a, nn, base); fft(b, nn, base); for (int i = 0; i < nn; ++i) a[i] *= b[i]; ifft(a, nn, base); vector<int> *rt = new vector<int>(); for (int i = 0; i < nn; ++i) rt->push_back(((long long)(real(a[i]) + 0.5)) % 1009); while (rt->size() && rt->back() == 0) rt->pop_back(); delete pa; delete pb; return rt; } int cnt[524288]; const double PI = acos(-1); int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); for (int i = 0; i <= 524288; ++i) o[i] = exp(2. * i * PI / 524288 * complex<double>(0, 1)); int n, m, k; cin >> n >> m >> k; while (n--) { int t; cin >> t; ++cnt[t]; } auto cmp = [&](const vector<int> *a, const vector<int> *b) { return a->size() > b->size(); }; priority_queue<vector<int> *, vector<vector<int> *>, decltype(cmp)> pq(cmp); for (int i = 1; i <= m; ++i) { if (cnt[i] == 0) continue; vector<int> *v = new vector<int>(); for (int j = 0; j <= cnt[i]; ++j) v->push_back(1); pq.push(v); } while (pq.size() > 1u) { vector<int> *p1, *p2; p1 = pq.top(); pq.pop(); p2 = pq.top(); pq.pop(); pq.push(mg(p1, p2)); } vector<int> *ans = pq.top(); cout << (ans->size() > k ? (*ans)[k] : 0) << endl; } |
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream frame length adjuster with FIFO
*/
module axis_frame_length_adjust_fifo #
(
// Width of AXI stream interfaces in bits
parameter DATA_WIDTH = 8,
// Propagate tkeep signal
// If disabled, tkeep assumed to be 1'b1
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
parameter KEEP_WIDTH = (DATA_WIDTH/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
parameter ID_WIDTH = 8,
// Propagate tdest signal
parameter DEST_ENABLE = 0,
// tdest signal width
parameter DEST_WIDTH = 8,
// Propagate tuser signal
parameter USER_ENABLE = 1,
// tuser signal width
parameter USER_WIDTH = 1,
// Depth of data FIFO in words
parameter FRAME_FIFO_DEPTH = 4096,
// Depth of header FIFO
parameter HEADER_FIFO_DEPTH = 8
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire [ID_WIDTH-1:0] s_axis_tid,
input wire [DEST_WIDTH-1:0] s_axis_tdest,
input wire [USER_WIDTH-1:0] s_axis_tuser,
/*
* AXI output
*/
output wire m_axis_hdr_valid,
input wire m_axis_hdr_ready,
output wire m_axis_hdr_pad,
output wire m_axis_hdr_truncate,
output wire [15:0] m_axis_hdr_length,
output wire [15:0] m_axis_hdr_original_length,
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_axis_tkeep,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire [ID_WIDTH-1:0] m_axis_tid,
output wire [DEST_WIDTH-1:0] m_axis_tdest,
output wire [USER_WIDTH-1:0] m_axis_tuser,
/*
* Configuration
*/
input wire [15:0] length_min,
input wire [15:0] length_max
);
wire [DATA_WIDTH-1:0] fifo_axis_tdata;
wire [KEEP_WIDTH-1:0] fifo_axis_tkeep;
wire fifo_axis_tvalid;
wire fifo_axis_tready;
wire fifo_axis_tlast;
wire [ID_WIDTH-1:0] fifo_axis_tid;
wire [DEST_WIDTH-1:0] fifo_axis_tdest;
wire [USER_WIDTH-1:0] fifo_axis_tuser;
wire status_valid;
wire status_ready;
wire status_frame_pad;
wire status_frame_truncate;
wire [15:0] status_frame_length;
wire [15:0] status_frame_original_length;
axis_frame_length_adjust #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
)
axis_frame_length_adjust_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(fifo_axis_tdata),
.m_axis_tkeep(fifo_axis_tkeep),
.m_axis_tvalid(fifo_axis_tvalid),
.m_axis_tready(fifo_axis_tready),
.m_axis_tlast(fifo_axis_tlast),
.m_axis_tid(fifo_axis_tid),
.m_axis_tdest(fifo_axis_tdest),
.m_axis_tuser(fifo_axis_tuser),
// Status
.status_valid(status_valid),
.status_ready(status_ready),
.status_frame_pad(status_frame_pad),
.status_frame_truncate(status_frame_truncate),
.status_frame_length(status_frame_length),
.status_frame_original_length(status_frame_original_length),
// Configuration
.length_min(length_min),
.length_max(length_max)
);
axis_fifo #(
.DEPTH(FRAME_FIFO_DEPTH),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(1),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.FRAME_FIFO(0)
)
frame_fifo_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(fifo_axis_tdata),
.s_axis_tkeep(fifo_axis_tkeep),
.s_axis_tvalid(fifo_axis_tvalid),
.s_axis_tready(fifo_axis_tready),
.s_axis_tlast(fifo_axis_tlast),
.s_axis_tid(fifo_axis_tid),
.s_axis_tdest(fifo_axis_tdest),
.s_axis_tuser(fifo_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
axis_fifo #(
.DEPTH(HEADER_FIFO_DEPTH),
.DATA_WIDTH(1+1+16+16),
.KEEP_ENABLE(0),
.LAST_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(0),
.FRAME_FIFO(0)
)
header_fifo_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata({status_frame_pad, status_frame_truncate, status_frame_length, status_frame_original_length}),
.s_axis_tkeep(0),
.s_axis_tvalid(status_valid),
.s_axis_tready(status_ready),
.s_axis_tlast(0),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(0),
// AXI output
.m_axis_tdata({m_axis_hdr_pad, m_axis_hdr_truncate, m_axis_hdr_length, m_axis_hdr_original_length}),
.m_axis_tkeep(),
.m_axis_tvalid(m_axis_hdr_valid),
.m_axis_tready(m_axis_hdr_ready),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m; int a[12][2001]; int dp[2][4096]; int sos[4096]; bool use[2001]; pair<int, int> b[2001]; void solve() { cin >> n >> m; for (int j = 1; j <= m; j++) b[j].first = 0; for (int i = 0; i < n; i++) { for (int j = 1; j <= m; j++) { cin >> a[i][j]; b[j].first = max(b[j].first, a[i][j]); b[j].second = j; } } sort(b + 1, b + m + 1); for (int j = m; j >= max(1, m - n + 1); j--) use[b[j].second] = true; for (int l = 0; l < (1 << n); l++) dp[0][l] = 0; int c = 0, p = 1; for (int j = 1; j <= m; j++) { if (!use[j]) continue; c ^= 1; p ^= 1; for (int l = 0; l < (1 << n); l++) dp[c][l] = 0; for (int k = 0; k < n; k++) { int tmp = a[0][j]; for (int l = 0; l < n - 1; l++) a[l][j] = a[l + 1][j]; a[n - 1][j] = tmp; for (int l = 0; l < (1 << n); l++) sos[l] = dp[p][l]; for (int i = 0; i < n; i++) { for (int l = 0; l < (1 << n); l++) { if (l & (1 << i)) sos[l] = max(sos[l], sos[l ^ (1 << i)] + a[i][j]); } } for (int l = 0; l < (1 << n); l++) dp[c][l] = max(dp[c][l], sos[l]); } } for (int j = m; j >= max(1, m - n + 1); j--) use[b[j].second] = false; cout << dp[c][(1 << n) - 1] << n ; } int main() { ios::sync_with_stdio(false); int t; cin >> t; while (t--) solve(); } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5; int t, n; long long x[maxn + 10], y[maxn + 10], z[maxn + 10]; long long l[4], r[4], tl[4], tr[4]; long long a[4]; void update(int p, long long a, long long b) { l[p] = max(l[p], a - b); r[p] = min(r[p], a + b); } bool calc() { long long sum = 0; for (int i = 0; i <= 3; ++i) { tl[i] = l[i] & 1 ? (l[i] + 1) / 2 : l[i] / 2; tr[i] = r[i] & 1 ? (r[i] - 1) / 2 : r[i] / 2; if (tl[i] > tr[i]) return 0; if (i) { a[i] = tl[i]; sum += tl[i]; } } for (int i = 1; i <= 3; ++i) { long long v = min(max(tl[0] - sum, 0ll), tr[i] - tl[i]); a[i] += v; sum += v; } return sum >= tl[0] && sum <= tr[0]; } bool chk(long long v) { memset(l, -0x3f, sizeof l); memset(r, 0x3f, sizeof r); for (int i = 1; i <= n; ++i) { update(0, x[i] + y[i] + z[i], v); update(1, x[i] + y[i] - z[i], v); update(2, x[i] - y[i] + z[i], v); update(3, -x[i] + y[i] + z[i], v); } if (calc()) { for (int i = 1; i <= 3; ++i) a[i] *= 2; return 1; } l[0] -= 3; r[0] -= 3; for (int i = 1; i <= 3; ++i) { --l[i]; --r[i]; } if (calc()) { for (int i = 1; i <= 3; ++i) a[i] = a[i] * 2 + 1; return 1; } return 0; } int main() { scanf( %d , &t); while (t--) { scanf( %d , &n); for (int i = 1; i <= n; ++i) scanf( %lld%lld%lld , &x[i], &y[i], &z[i]); long long l = 0, r = 3e18; while (l != r) { long long mid = (l + r) >> 1; if (chk(mid)) r = mid; else l = mid + 1; } chk(l); printf( %lld %lld %lld n , (a[1] + a[2]) / 2, (a[1] + a[3]) / 2, (a[2] + a[3]) / 2); } } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18.07.2017 10:30:15
// Design Name:
// Module Name: FPS_Testbench
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FPS_10;
integer i_count;
integer o_count;
//inputs
reg CLK;
reg RST;
reg enable;
//outputs
wire In_ack1, In_ack2, In_ack3;
wire In_rdy1, In_rdy2, In_rdy3;
wire Out_send1, Out_send2, Out_send3;
wire all_rdy, all_ack;
ProgNetwork uut
(
//-- XDF Network Input(s)
.In1_data (8'h0),
.In1_send (In_rdy1 & enable),
.In1_ack (In_ack1),
.In1_rdy (In_rdy1),
.In1_count (),
.In2_data (8'h0),
.In2_send (In_rdy2 & enable),
.In2_ack (In_ack2),
.In2_rdy (In_rdy2),
.In2_count (),
.In3_data (8'h0),
.In3_send (In_rdy3 & enable),
.In3_ack (In_ack3),
.In3_rdy (In_rdy3),
.In3_count (),
//-- XDF Network Output(s)
.Out1_data (),
.Out1_send (Out_send1),
.Out1_ack (Out_send1),
.Out1_rdy (enable),
.Out1_count (),
.Out2_data (),
.Out2_send (Out_send2),
.Out2_ack (Out_send2),
.Out2_rdy (enable),
.Out2_count (),
.Out3_data (),
.Out3_send (Out_send3),
.Out3_ack (Out_send3),
.Out3_rdy (enable),
.Out3_count (),
//-- Clock(s) and Reset
.CLK (CLK),
.RESET (RST)
);
initial begin
CLK = 0;
RST = 1;
enable = 0;
i_count = 0;
o_count = 0;
#500;
@(posedge CLK);
RST = 0;
#500;
@(posedge CLK);
enable=1;
end
assign all_rdy = In_rdy1 & In_rdy2 & In_rdy3;
assign all_ack = In_ack1 & In_ack2 & In_ack3;
always CLK = #1 ~CLK;
always@(posedge CLK)
begin
if(i_count == 10*10)
begin
$display("input frame at %d",$time);
i_count <= 0;
end
else
begin
if(all_rdy & all_ack & enable)
i_count <= i_count + 1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> arr(78498); vector<vector<int>> in(505, vector<int>(505)); vector<vector<int>> out(505, vector<int>(505)); void SieveOfEratosthenes(int n) { vector<bool> prime(n + 1, true); for (int p = 2; p * p <= n; p++) { if (prime[p] == true) { for (int i = p * p; i <= n; i += p) prime[i] = false; } } int i = 0; for (int p = 2; p <= n; p++) if (prime[p]) arr[i++] = p; } int f(int val) { int l = 0, u = arr.size() - 1, res = -1; while (l <= u) { int mid = (l + u) / 2; if (val == arr[mid]) return -2; else if (val < arr[mid]) { res = mid; u = mid - 1; } else l = mid + 1; } return res; } int main() { SieveOfEratosthenes(1000000); sort(arr.begin(), arr.end()); int n, m; cin >> n >> m; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) cin >> in[i][j]; } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { int res = f(in[i][j]); if (res == -2) out[i][j] = 0; else if (res == -1) cout << error << endl; else { out[i][j] = arr[res] - in[i][j]; } } } long long mini = pow(10, 18); for (int i = 0; i < n; i++) { long long tot = 0; for (int j = 0; j < m; j++) tot += (long long)out[i][j]; mini = min(mini, tot); } for (int j = 0; j < m; j++) { long long tot = 0; for (int i = 0; i < n; i++) tot += (long long)out[i][j]; mini = min(mini, tot); } cout << mini << endl; } |
`define bsg_nor3_macro(bits) \
if (harden_p && (width_p==bits)) \
begin: macro \
bsg_rp_tsmc_40_NR3D1BWP_b``bits nor3_gate (.i0(a_i),.i1(b_i),.i2(c_i),.o); \
end
module bsg_nor3 #(parameter `BSG_INV_PARAM(width_p)
, parameter harden_p=0
)
(input [width_p-1:0] a_i
, input [width_p-1:0] b_i
, input [width_p-1:0] c_i
, output [width_p-1:0] o
);
`bsg_nor3_macro(34) else
`bsg_nor3_macro(33) else
`bsg_nor3_macro(32) else
`bsg_nor3_macro(31) else
`bsg_nor3_macro(30) else
`bsg_nor3_macro(29) else
`bsg_nor3_macro(28) else
`bsg_nor3_macro(27) else
`bsg_nor3_macro(26) else
`bsg_nor3_macro(25) else
`bsg_nor3_macro(24) else
`bsg_nor3_macro(23) else
`bsg_nor3_macro(22) else
`bsg_nor3_macro(21) else
`bsg_nor3_macro(20) else
`bsg_nor3_macro(19) else
`bsg_nor3_macro(18) else
`bsg_nor3_macro(17) else
`bsg_nor3_macro(16) else
`bsg_nor3_macro(15) else
`bsg_nor3_macro(14) else
`bsg_nor3_macro(13) else
`bsg_nor3_macro(12) else
`bsg_nor3_macro(11) else
`bsg_nor3_macro(10) else
`bsg_nor3_macro(9) else
`bsg_nor3_macro(8) else
`bsg_nor3_macro(7) else
`bsg_nor3_macro(6) else
`bsg_nor3_macro(5) else
`bsg_nor3_macro(4) else
`bsg_nor3_macro(3) else
`bsg_nor3_macro(2) else
`bsg_nor3_macro(1) else
begin :notmacro
initial assert(harden_p==0) else $error("## %m wanted to harden but no macro");
assign o = ~(a_i | b_i | c_i);
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_nor3)
|
#include <bits/stdc++.h> using namespace std; const int mason[] = {2, 3, 5, 7, 13, 17, 19, 31, 61, 89, 107, 127, 521, 607, 1279, 2203, 2281, 3217, 4253, 4423, 9689, 9941, 11213, 19937, 21701, 23209, 44497, 86243, 110503, 132049, 216091, 756839, 859433, 1257787, 1398269, 2976221, 3021377, 6972593, 13466917, 20996011}, Mod = 1000000007; int main() { int n; scanf( %d , &n); int idx = mason[n - 1] - 1; long long ret = 1LL, val = 2LL; while (idx) { if (idx & 1) ret = ret * val % Mod; val = val * val % Mod; idx >>= 1; } printf( %lld n , ret - 1); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EINVP_FUNCTIONAL_V
`define SKY130_FD_SC_HS__EINVP_FUNCTIONAL_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__einvp (
VPWR,
VGND,
Z ,
A ,
TE
);
// Module ports
input VPWR;
input VGND;
output Z ;
input A ;
input TE ;
// Local signals
wire u_vpwr_vgnd0_out_A ;
wire u_vpwr_vgnd1_out_TE;
// Name Output Other arguments
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_A , A, VPWR, VGND );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd1 (u_vpwr_vgnd1_out_TE, TE, VPWR, VGND );
notif1 notif10 (Z , u_vpwr_vgnd0_out_A, u_vpwr_vgnd1_out_TE);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__EINVP_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 2; int num[N], n, res[N], a[N]; void ReadData() { cin >> n; for (int i = 0; i < n; ++i) cin >> num[i]; } void Update(int x, int y) { if (x > y) return; ++a[x]; --a[y + 1]; } void Solve() { for (int i = 0; i < n; ++i) { int k = 1; for (; k * k <= (i - 1); ++k) if (num[i] < num[(i - 1) / k]) ++res[k]; for (int j = 0; j <= (i - 1) / k; ++j) if (num[i] < num[j]) { if (0 == j) Update(i, n - 1); else Update(max(k, (i - 1) / (j + 1) + 1), (i - 1) / j); } } for (int i = 1; i < n; ++i) { a[i] += a[i - 1]; res[i] += a[i]; } } void Output() { for (int i = 1; i < n; ++i) cout << res[i] << endl; } int main() { ReadData(); Solve(); Output(); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; vector<set<int> > g(n + 1); map<int, int> co; for (int i = 0; i < m; i++) { int n1, n2; cin >> n1 >> n2; g[n1].insert(n2); g[n2].insert(n1); co[n1]++; co[n2]++; } int minn = 1000000000; for (int i = 1; i <= n; i++) { set<int>::iterator iter; for (iter = g[i].begin(); iter != g[i].end(); iter++) { set<int>::iterator iter2; for (iter2 = g[*iter].begin(); iter2 != g[*iter].end(); iter2++) { if (*iter2 == i) continue; if (g[*iter2].count(i)) { minn = min(minn, co[*iter] + co[*iter2] + co[i] - 6); } } } } if (minn == 1000000000) cout << -1 << endl; else cout << minn << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; while (cin >> n) { string s; cin >> s; string res = ; for (int i = 0; i < n; i++) { if (s[i] <= 1 ) continue; else { if (s[i] == 4 ) res += 3 , res += 2 , res += 2 ; else { if (s[i] == 6 ) res += 5 , res += 3 ; else { if (s[i] == 8 ) res += 7 , res += 2 , res += 2 , res += 2 ; else { if (s[i] == 9 ) res += 3 , res += 3 , res += 2 , res += 7 ; else res += s[i]; } } } } } sort(res.begin(), res.end()); reverse(res.begin(), res.end()); cout << res << endl; } } |
#include <bits/stdc++.h> using namespace std; void solve(); int arr[200005]; int count1[200005]; int count2[200005]; int main() { int n; cin >> n; for (int i = 0; i < n; i++) { cin >> arr[i]; } long long sum1 = 0; long long sum2 = 0; int cnt1 = 0; int cnt2 = 0; int j = 0; for (int i = n - 1; i >= 0; i--) { if (arr[i] == 0) { cnt1++; } count1[i] = cnt1; } for (int i = 0; i < n; i++) { if (arr[i] == 1) { cnt2++; } count2[i] = cnt2; } for (int i = 0; i < n; i++) { if (arr[i] == 1) sum2 += count1[i]; } for (int i = 0; i < n; i++) { if (arr[i] == 0) sum1 += count2[i]; } if (sum1 >= sum2) cout << sum2 << endl; else cout << sum1 << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SLEEP_PARGATE_PLV_TB_V
`define SKY130_FD_SC_LP__SLEEP_PARGATE_PLV_TB_V
/**
* sleep_pargate_plv: ????.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sleep_pargate_plv.v"
module top();
// Inputs are registered
reg SLEEP;
reg VPWR;
reg VPB;
reg VNB;
// Outputs are wires
wire VIRTPWR;
initial
begin
// Initial state is x for all inputs.
SLEEP = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 SLEEP = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 SLEEP = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 SLEEP = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 SLEEP = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 SLEEP = 1'bx;
end
sky130_fd_sc_lp__sleep_pargate_plv dut (.SLEEP(SLEEP), .VPWR(VPWR), .VPB(VPB), .VNB(VNB), .VIRTPWR(VIRTPWR));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SLEEP_PARGATE_PLV_TB_V
|
#pragma GCC optimize( O3 ) #pragma GCC optimize( unroll-loops ) #include<iostream> #include<string> #include<cstdio> #include<vector> #include<cmath> #include<algorithm> #include<functional> #include<iomanip> #include<queue> #include<ciso646> #include<random> #include<map> #include<set> #include<bitset> #include<stack> #include<unordered_map> #include<unordered_set> #include<utility> #include<cassert> #include<complex> #include<numeric> #include<array> using namespace std; //#define int long long typedef long long ll; typedef unsigned long long ul; typedef unsigned int ui; constexpr ll mod = 10007; const ll INF = mod * mod; typedef pair<int, int>P; #define stop char nyaa;cin>>nyaa; #define rep(i,n) for(int i=0;i<n;i++) #define per(i,n) for(int i=n-1;i>=0;i--) #define Rep(i,sta,n) for(int i=sta;i<n;i++) #define rep1(i,n) for(int i=1;i<=n;i++) #define per1(i,n) for(int i=n;i>=1;i--) #define Rep1(i,sta,n) for(int i=sta;i<=n;i++) #define all(v) (v).begin(),(v).end() typedef pair<ll, ll> LP; typedef long double ld; typedef pair<ld, ld> LDP; const ld eps = 1e-12; const ld pi = acosl(-1.0); ll mod_pow(ll x, ll n, ll m = mod) { if (n < 0) { ll res = mod_pow(x, -n, m); return mod_pow(res, m - 2, m); } if (abs(x) >= m)x %= m; if (x < 0)x += m; ll res = 1; while (n) { if (n & 1)res = res * x % m; x = x * x % m; n >>= 1; } return res; } struct modint { ll n; modint() :n(0) { ; } modint(ll m) :n(m) { if (n >= mod)n %= mod; else if (n < 0)n = (n % mod + mod) % mod; } operator int() { return n; } }; bool operator==(modint a, modint b) { return a.n == b.n; } modint operator+=(modint& a, modint b) { a.n += b.n; if (a.n >= mod)a.n -= mod; return a; } modint operator-=(modint& a, modint b) { a.n -= b.n; if (a.n < 0)a.n += mod; return a; } modint operator*=(modint& a, modint b) { a.n = ((ll)a.n * b.n) % mod; return a; } modint operator+(modint a, modint b) { return a += b; } modint operator-(modint a, modint b) { return a -= b; } modint operator*(modint a, modint b) { return a *= b; } modint operator^(modint a, ll n) { if (n == 0)return modint(1); modint res = (a * a) ^ (n / 2); if (n % 2)res = res * a; return res; } ll inv(ll a, ll p) { return (a == 1 ? 1 : (1 - p * inv(p % a, a)) / a + p); } modint operator/(modint a, modint b) { return a * modint(inv(b, mod)); } modint operator/=(modint& a, modint b) { a = a / b; return a; } const int max_n = 1 << 1; modint fact[max_n], factinv[max_n]; void init_f() { fact[0] = modint(1); for (int i = 0; i < max_n - 1; i++) { fact[i + 1] = fact[i] * modint(i + 1); } factinv[max_n - 1] = modint(1) / fact[max_n - 1]; for (int i = max_n - 2; i >= 0; i--) { factinv[i] = factinv[i + 1] * modint(i + 1); } } modint comb(int a, int b) { if (a < 0 || b < 0 || a < b)return 0; return fact[a] * factinv[b] * factinv[a - b]; } modint combP(int a, int b) { if (a < 0 || b < 0 || a < b)return 0; return fact[a] * factinv[a - b]; } void solve() { int n, m, x; cin >> n >> m >> x; vector<int> h(n); rep(i, n)cin >> h[i]; vector<int> sum(m); priority_queue<P, vector<P>, greater<P>> q; rep(i, m)q.push({ 0,i }); vector<int> ans(n); rep(i, n) { P p = q.top(); q.pop(); int id = p.second; ans[i] = id; sum[id] += h[i]; q.push({ sum[id],id }); } cout << YES n ; rep(i, n) { if (i > 0)cout << ; cout << ans[i] + 1; } cout << n ; } signed main() { ios::sync_with_stdio(false); cin.tie(0); //cout << fixed << setprecision(10); //init_f(); //init(); //expr(); int t; cin >> t; rep(i, t) solve(); return 0; } |
module test01(clk,
led_gnd1, led_gnd2, //LED grounds
led6, led7, led8, led9, led10, led12, led13, led15, led16, led17, led18, led19, led20, led21,
led_second_tick
);
input wire clk;
output wire led_gnd1, led_gnd2;
output wire led6, led7, led8, led9, led10, led12, led13, led15, led16, led17, led18, led19, led20, led21, led_second_tick;
//clk - general clock 32768
reg [14:0] clk_div; initial clk_div <= 15'd0; //?? may be not implement
always @(posedge clk) clk_div <= clk_div + 1'b1;
wire divided_clk = clk_div[3];
reg divided_clk_prev;
always @(posedge clk) divided_clk_prev <= divided_clk;
wire divided_clk_posedge = ((divided_clk_prev==1'b0)&&(divided_clk==1'b1));
assign led_gnd1 = clk_div[0];
assign led_gnd2 = ~clk_div[0];
wire [3:0] m;
wire [3:0] mm;
wire [3:0] h;
wire [3:0] hh;
wire m_en = divided_clk_posedge;
wire mm_en;
wire h_en;
wire hh_en;
wire m_cy;
wire mm_cy;
wire h_cy;
wire hh_cy;
cntr #(.max(9)) cnt_m( .en(divided_clk_posedge), .clk(clk), .out(m), .cy(m_cy) );
cntr #(.max(5)) cnt_mm( .en(m_cy), .clk(clk), .out(mm), .cy(mm_cy) );
cntr #(.max(9)) cnt_h( .en(mm_cy), .clk(clk), .out(h), .cy(h_cy), .res((hh==2)&&(h==4)) );
cntr #(.max(2)) cnt_hh( .en(h_cy), .clk(clk), .out(hh), .cy(hh_cy), .res((hh==2)&&(h==4)) );
wire [6:0] s_m;
wire [6:0] s_mm;
wire [6:0] s_h;
wire [6:0] s_hh;
bcd2seg sseg_m( .sin(m), .sout(s_m));
bcd2seg sseg_mm(.sin(mm), .sout(s_mm));
bcd2seg sseg_h( .sin(h), .sout(s_h));
bcd2seg sseg_hh(.sin(hh), .sout(s_hh));
wire a1,b1,c1,d1,e1,f1,g1;
wire a2,b2,c2,d2,e2,f2,g2;
wire a3,b3,c3,d3,e3,f3,g3;
wire a4,b4,c4,d4,e4,f4,g4;
assign {g4, f4, e4, d4, c4, b4, a4} = s_m;
assign {g3, f3, e3, d3, c3, b3, a3} = s_mm;
assign {g2, f2, e2, d2, c2, b2, a2} = s_h;
assign {g1, f1, e1, d1, c1, b1, a1} = s_hh;
//hide hour zero
wire h_show = !(hh==0);
assign led6 = (led_gnd1) ? (b1&&h_show):(b1&&h_show); // b1
assign led7 = (led_gnd1) ? (a1&&h_show):(g1&&h_show); // a1/g1
assign led8 = (led_gnd1) ? (d1&&h_show):(e1&&h_show); // d1/e1
assign led9 = (led_gnd1) ? e2:(c1&&h_show); // e2/c1
assign led10 = (led_gnd1) ? g2:b2; // g2/b2
assign led12 = (led_gnd1) ? d2:c2; // d2/c2
assign led13 = (led_gnd1) ? f2:a2; // f2/a2
assign led15 = (led_gnd1) ? a3:f3; // a3/f3
assign led16 = (led_gnd1) ? b3:g3; // b3/g3
assign led17 = (led_gnd1) ? c3:d3; // c3/d3
assign led18 = (led_gnd1) ? e4:e3; // e3/e4 !!
assign led19 = (led_gnd1) ? g4:b4; // g4/b4
assign led20 = (led_gnd1) ? d4:c4; // d4/c4
assign led21 = (led_gnd1) ? f4:a4; // f4/a4
//one second tick indicator
assign led_second_tick = led_gnd1 && clk_div[14];
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, f, d; int main() { cin >> n; if (n % 3 != 2) d = n / 3; else d = n / 3 + 1; f = d / 12; d %= 12; cout << f << << d; return 0; } |
// megafunction wizard: %LPM_MUX%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_MUX
// ============================================================
// File Name: datamux.v
// Megafunction Name(s):
// LPM_MUX
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 263 08/02/2012 SP 2.16 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module datamux (
aclr,
clock,
data0x,
data1x,
data2x,
data3x,
sel,
result);
input aclr;
input clock;
input [7:0] data0x;
input [7:0] data1x;
input [7:0] data2x;
input [7:0] data3x;
input [1:0] sel;
output [7:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
// Retrieval info: CONSTANT: LPM_SIZE NUMERIC "4"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "2"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data0x 0 0 8 0 INPUT NODEFVAL "data0x[7..0]"
// Retrieval info: USED_PORT: data1x 0 0 8 0 INPUT NODEFVAL "data1x[7..0]"
// Retrieval info: USED_PORT: data2x 0 0 8 0 INPUT NODEFVAL "data2x[7..0]"
// Retrieval info: USED_PORT: data3x 0 0 8 0 INPUT NODEFVAL "data3x[7..0]"
// Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL "result[7..0]"
// Retrieval info: USED_PORT: sel 0 0 2 0 INPUT NODEFVAL "sel[1..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 8 0 data0x 0 0 8 0
// Retrieval info: CONNECT: @data 0 0 8 8 data1x 0 0 8 0
// Retrieval info: CONNECT: @data 0 0 8 16 data2x 0 0 8 0
// Retrieval info: CONNECT: @data 0 0 8 24 data3x 0 0 8 0
// Retrieval info: CONNECT: @sel 0 0 2 0 sel 0 0 2 0
// Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL datamux.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL datamux.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL datamux.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL datamux.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL datamux_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL datamux_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
// file: testclk.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1___128.008______0.000______50.0______116.476_____95.328
// CLK_OUT2___128.008______0.000______50.0______116.476_____95.328
// CLK_OUT3___128.008______0.000______50.0______116.476_____95.328
// CLK_OUT4___256.017______0.000______50.0______102.099_____95.328
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_____________256____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "testclk,clk_wiz_v3_6,{component_name=testclk,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_ONCHIP,primtype_sel=MMCM_ADV,num_out_clk=4,clkin1_period=3.906,clkin2_period=3.906,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=true}" *)
module testclk
(// Clock in ports
input CLK_IN1,
input CLKFB_IN,
// Clock out ports
output CLK_OUT1,
output CLK_OUT2,
output CLK_OUT3,
output CLK_OUT4,
output CLKFB_OUT
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));
// Clocking primitive
//------------------------------------
// Instantiation of the MMCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_unused;
wire clkfbout;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1b_unused;
wire clkout2b_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCM_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.CLOCK_HOLD ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (2),
.CLKFBOUT_MULT_F (8.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (8.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (8),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKOUT2_DIVIDE (8),
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT2_USE_FINE_PS ("FALSE"),
.CLKOUT3_DIVIDE (4),
.CLKOUT3_PHASE (0.000),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKOUT3_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (3.906),
.REF_JITTER1 (0.010))
mmcm_adv_inst
// Output clocks
(.CLKFBOUT (clkfbout),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clkout0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (CLKFB_IN),
.CLKIN1 (clkin1),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_unused),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (1'b0));
// Output buffering
//-----------------------------------
assign CLKFB_OUT = clkfbout;
assign CLK_OUT1 = clkout0;
assign CLK_OUT2 = clkout1;
assign CLK_OUT3 = clkout2;
assign CLK_OUT4 = clkout3;
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Company: Xilinx
// Engineer: Karl Kurbjun
// Date: 12/7/2009
// Design Name: MMCM DRP
// Module Name: user_clock_gen.v
// Version: 2.0
// Target Devices: Virtex 6 Family
// Tool versions: L.50 (lin)
// Description: This is a basic demonstration of the MMCM_DRP
// connectivity to the MMCM_ADV.
//
// Revision Updated to support upto 4 frequencies. K. Vipin
//
// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
// APPLICATION OR STANDARD, XILINX IS MAKING NO
// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE.
//
// (c) Copyright 2009-1010 Xilinx, Inc.
// All rights reserved.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
module user_clock_gen
(
input DRP_CLK,
// SSTEP is the input to start a reconfiguration. It should only be
// pulsed for one clock cycle.
input SSTEP,
// STATE determines which state the MMCM_ADV will be reconfigured to. A
// value of 0 correlates to state 1, and a value of 1 correlates to state
// 2.
input [1:0] STATE,
// RST will reset the entire reference design including the MMCM_ADV
input RST,
// CLKIN is the input clock that feeds the MMCM_ADV CLKIN as well as the
// clock for the MMCM_DRP module
input CLKIN,
// SRDY pulses for one clock cycle after the MMCM_ADV is locked and the
// MMCM_DRP module is ready to start another re-configuration
output SRDY,
// These are the clock outputs from the MMCM_ADV.
output CLK0OUT
);
// These signals are used as direct connections between the MMCM_ADV and the
// MMCM_DRP.
wire [15:0] di;
wire [6:0] daddr;
wire [15:0] dout;
wire den;
wire dwe;
wire dclk;
wire rst_mmcm;
wire drdy;
wire locked;
// These signals are used for the BUFG's necessary for the design.
wire clkin_bufgout;
wire clkfb_bufgout;
wire clkfb_bufgin;
wire clk0_bufgin;
wire clk0_bufgout;
BUFG BUFG_FB (
.O(clkfb_bufgout),
.I(clkfb_bufgin)
);
BUFG BUFG_CLK0 (
.O(CLK0OUT),
.I(clk0_bufgin)
);
// MMCM_ADV that reconfiguration will take place on
MMCM_ADV #(
.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.CLOCK_HOLD ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (2),
.CLKFBOUT_MULT_F (8.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (4.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (5),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKOUT2_DIVIDE (7),
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT2_USE_FINE_PS ("FALSE"),
.CLKOUT3_DIVIDE (10),
.CLKOUT3_PHASE (0.000),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKOUT3_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (4.000),
.REF_JITTER1 (0.010)
) mmcm_inst (
.CLKFBOUT(clkfb_bufgin),
.CLKFBOUTB(),
.CLKFBSTOPPED(),
.CLKINSTOPPED(),
// Clock outputs
.CLKOUT0(clk0_bufgin),
.CLKOUT0B(),
.CLKOUT1(),
.CLKOUT1B(),
// DRP Ports
.DO(dout), // (16-bits)
.DRDY(drdy),
.DADDR(daddr), // 5 bits
.DCLK(dclk),
.DEN(den),
.DI(di), // 16 bits
.DWE(dwe),
.LOCKED(locked),
.CLKFBIN(clkfb_bufgout),
// Clock inputs
.CLKIN1(CLKIN),
.CLKIN2(),
.CLKINSEL(1'b1),
// Fine phase shifting
.PSDONE(),
.PSCLK(1'b0),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(rst_mmcm)
);
// MMCM_DRP instance that will perform the reconfiguration operations
mmcm_drp #(
//***********************************************************************
// State 1 Parameters - These are for the first reconfiguration state.
//***********************************************************************
// Set the multiply to 5 with 0 deg phase offset, low bandwidth, input
// divide of 1
.S1_CLKFBOUT_MULT(8),
.S1_CLKFBOUT_PHASE(0),
.S1_BANDWIDTH("LOW"),
.S1_DIVCLK_DIVIDE(2),
// Set clock out 0 to a divide of 5, 0deg phase offset, 50/50 duty cycle
.S1_CLKOUT0_DIVIDE(4),
.S1_CLKOUT0_PHASE(00000),
.S1_CLKOUT0_DUTY(50000),
//***********************************************************************
// State 2 Parameters - These are for the second reconfiguration state.
//***********************************************************************
.S2_CLKFBOUT_MULT(8),
.S2_CLKFBOUT_PHASE(0),
.S2_BANDWIDTH("LOW"),
.S2_DIVCLK_DIVIDE(2),
.S2_CLKOUT0_DIVIDE(5),
.S2_CLKOUT0_PHASE(0),
.S2_CLKOUT0_DUTY(50000),
//***********************************************************************
// State 3 Parameters - These are for the second reconfiguration state.
//***********************************************************************
.S3_CLKFBOUT_MULT(8),
.S3_CLKFBOUT_PHASE(0),
.S3_BANDWIDTH("LOW"),
.S3_DIVCLK_DIVIDE(2),
.S3_CLKOUT0_DIVIDE(7),
.S3_CLKOUT0_PHASE(0),
.S3_CLKOUT0_DUTY(50000),
//***********************************************************************
// State 4 Parameters - These are for the second reconfiguration state.
//***********************************************************************
.S4_CLKFBOUT_MULT(8),
.S4_CLKFBOUT_PHASE(0),
.S4_BANDWIDTH("LOW"),
.S4_DIVCLK_DIVIDE(2),
.S4_CLKOUT0_DIVIDE(10),
.S4_CLKOUT0_PHASE(0),
.S4_CLKOUT0_DUTY(50000)
) mmcm_drp_inst (
// Top port connections
.SADDR(STATE),
.SEN(SSTEP),
.RST(RST),
.SRDY(SRDY),
// Input from IBUFG
.SCLK(DRP_CLK),
// Direct connections to the MMCM_ADV
.DO(dout),
.DRDY(drdy),
.LOCKED(locked),
.DWE(dwe),
.DEN(den),
.DADDR(daddr),
.DI(di),
.DCLK(dclk),
.RST_MMCM(rst_mmcm)
);
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Store Buffer ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Implements store buffer. ////
//// ////
//// To Do: ////
//// - byte combining ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/08/18 19:53:08 lampret
// Added store buffer.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_sb(
// RISC clock, reset
clk, rst,
// Internal RISC bus (DC<->SB)
dcsb_dat_i, dcsb_adr_i, dcsb_cyc_i, dcsb_stb_i, dcsb_we_i, dcsb_sel_i, dcsb_cab_i,
dcsb_dat_o, dcsb_ack_o, dcsb_err_o,
// BIU bus
sbbiu_dat_o, sbbiu_adr_o, sbbiu_cyc_o, sbbiu_stb_o, sbbiu_we_o, sbbiu_sel_o, sbbiu_cab_o,
sbbiu_dat_i, sbbiu_ack_i, sbbiu_err_i
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
//
// RISC clock, reset
//
input clk; // RISC clock
input rst; // RISC reset
//
// Internal RISC bus (DC<->SB)
//
input [dw-1:0] dcsb_dat_i; // input data bus
input [aw-1:0] dcsb_adr_i; // address bus
input dcsb_cyc_i; // WB cycle
input dcsb_stb_i; // WB strobe
input dcsb_we_i; // WB write enable
input dcsb_cab_i; // CAB input
input [3:0] dcsb_sel_i; // byte selects
output [dw-1:0] dcsb_dat_o; // output data bus
output dcsb_ack_o; // ack output
output dcsb_err_o; // err output
//
// BIU bus
//
output [dw-1:0] sbbiu_dat_o; // output data bus
output [aw-1:0] sbbiu_adr_o; // address bus
output sbbiu_cyc_o; // WB cycle
output sbbiu_stb_o; // WB strobe
output sbbiu_we_o; // WB write enable
output sbbiu_cab_o; // CAB input
output [3:0] sbbiu_sel_o; // byte selects
input [dw-1:0] sbbiu_dat_i; // input data bus
input sbbiu_ack_i; // ack output
input sbbiu_err_i; // err output
`ifdef OR1200_SB_IMPLEMENTED
//
// Internal wires and regs
//
wire [4+dw+aw-1:0] fifo_dat_i; // FIFO data in
wire [4+dw+aw-1:0] fifo_dat_o; // FIFO data out
wire fifo_wr;
wire fifo_rd;
wire fifo_full;
wire fifo_empty;
wire sel_sb;
reg outstanding_store;
reg fifo_wr_ack;
//
// FIFO data in/out
//
assign fifo_dat_i = {dcsb_sel_i, dcsb_dat_i, dcsb_adr_i};
assign {sbbiu_sel_o, sbbiu_dat_o, sbbiu_adr_o} = sel_sb ? fifo_dat_o : {dcsb_sel_i, dcsb_dat_i, dcsb_adr_i};
//
// Control
//
assign fifo_wr = dcsb_cyc_i & dcsb_stb_i & dcsb_we_i & ~fifo_full & ~fifo_wr_ack;
assign fifo_rd = ~outstanding_store;
assign dcsb_dat_o = sbbiu_dat_i;
assign dcsb_ack_o = sel_sb ? fifo_wr_ack : sbbiu_ack_i;
assign dcsb_err_o = sel_sb ? 1'b0 : sbbiu_err_i; // SB never returns error
assign sbbiu_cyc_o = sel_sb ? outstanding_store : dcsb_cyc_i;
assign sbbiu_stb_o = sel_sb ? outstanding_store : dcsb_stb_i;
assign sbbiu_we_o = sel_sb ? 1'b1 : dcsb_we_i;
assign sbbiu_cab_o = sel_sb ? 1'b0 : dcsb_cab_i;
assign sel_sb = ~fifo_empty | (fifo_empty & outstanding_store); // | fifo_wr;
//
// Store buffer FIFO instantiation
//
or1200_sb_fifo or1200_sb_fifo (
.clk_i(clk),
.rst_i(rst),
.dat_i(fifo_dat_i),
.wr_i(fifo_wr),
.rd_i(fifo_rd),
.dat_o(fifo_dat_o),
.full_o(fifo_full),
.empty_o(fifo_empty)
);
//
// fifo_rd
//
always @(posedge clk or posedge rst)
if (rst)
outstanding_store <= #1 1'b0;
else if (sbbiu_ack_i)
outstanding_store <= #1 1'b0;
else if (sel_sb | fifo_wr)
outstanding_store <= #1 1'b1;
//
// fifo_wr_ack
//
always @(posedge clk or posedge rst)
if (rst)
fifo_wr_ack <= #1 1'b0;
else if (fifo_wr)
fifo_wr_ack <= #1 1'b1;
else
fifo_wr_ack <= #1 1'b0;
`else // !OR1200_SB_IMPLEMENTED
assign sbbiu_dat_o = dcsb_dat_i;
assign sbbiu_adr_o = dcsb_adr_i;
assign sbbiu_cyc_o = dcsb_cyc_i;
assign sbbiu_stb_o = dcsb_stb_i;
assign sbbiu_we_o = dcsb_we_i;
assign sbbiu_cab_o = dcsb_cab_i;
assign sbbiu_sel_o = dcsb_sel_i;
assign dcsb_dat_o = sbbiu_dat_i;
assign dcsb_ack_o = sbbiu_ack_i;
assign dcsb_err_o = sbbiu_err_i;
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); int N, P, M, T; cin >> N >> P >> M >> T; deque<int> dq(N, 1); for (int x = 0; x < T; x++) { int typ, pos; cin >> typ >> pos; if (typ) { dq.push_back(1); if (pos <= P) P++; cout << dq.size() << << P << n ; } else { int seg1 = pos; if (P <= seg1) { int Ind = dq.size() - seg1; while (Ind > 0) { dq.pop_back(); Ind--; } cout << dq.size() << << P << n ; } else { P -= seg1; while (seg1 > 0) { dq.pop_front(); seg1--; } cout << dq.size() << << P << n ; } } } return 0; } |
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ps
module ad_pps_receiver (
input clk,
input rst,
input gps_pps,
input up_clk,
input up_rstn,
output reg [31:0] up_pps_rcounter,
output reg up_pps_status,
input up_irq_mask,
output reg up_irq);
// *************************************************************************
// 1PPS reception and reporting counter implementation
// Note: this module should run on the core clock
// *************************************************************************
reg [ 2:0] gps_pps_m = 3'b0;
reg [ 2:0] up_pps_m = 3'b0;
reg up_pps_status_m = 1'b0;
reg pps_toggle = 1'b0;
reg [31:0] free_rcounter = 32'b0;
reg [31:0] pps_rcounter = 32'b0;
reg pps_status = 1'b0;
wire pps_posedge_s;
wire up_pps_posedge_s;
// gps_pps is asynchronous from the clk
always @(posedge clk) begin
if (rst == 1'b1) begin
gps_pps_m <= 3'b0;
end else begin
gps_pps_m <= {gps_pps_m[1:0], gps_pps};
end
end
assign pps_posedge_s = ~gps_pps_m[2] & gps_pps_m[1];
always @(posedge clk) begin
if (rst == 1'b1) begin
free_rcounter <= 32'b0;
pps_rcounter <= 32'b0;
pps_status <= 1'b1;
end else if (pps_posedge_s == 1'b1) begin
free_rcounter <= 32'b0;
pps_rcounter <= free_rcounter;
pps_status <= 1'b0;
end else begin
free_rcounter <= free_rcounter + 32'b1;
if (free_rcounter[28] == 1'b1) begin
pps_status <= 1'b1;
end
end
end
// up_tdd_pps_rcounter CDC
always @(posedge clk) begin
if (rst == 1'b1) begin
pps_toggle <= 1'b0;
end else if (pps_posedge_s == 1'b1) begin
pps_toggle <= ~pps_toggle;
end
end
always @(posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_pps_m <= 3'b0;
up_pps_rcounter <= 1'b0;
up_pps_status_m <= 1'b1;
up_pps_status <= 1'b1;
end else begin
up_pps_m <= {up_pps_m[1:0], pps_toggle};
up_pps_status_m <= pps_status;
up_pps_status <= up_pps_status_m;
if ((up_pps_m[2] ^ up_pps_m[1]) == 1'b1) begin
up_pps_rcounter <= pps_rcounter;
end
end
end
assign up_pps_posedge_s = ~up_pps_m[2] & up_pps_m[1];
// IRQ generation
always @(posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_irq <= 1'b0;
end else begin
up_irq <= up_pps_posedge_s & ~up_irq_mask;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const double EPS = 1e-9; inline int cmp(double x, double y = 0, double tol = EPS) { return ((x <= y + tol) ? (x + tol < y) ? -1 : 0 : 1); } struct point { long long x, y; point(long long x = 0, long long y = 0) : x(x), y(y) {} point operator+(point q) { return point(x + q.x, y + q.y); } point operator-(point q) { return point(x - q.x, y - q.y); } int cmp(point q) const { if (int t = ::cmp(x, q.x)) return t; return ::cmp(y, q.y); } bool operator==(point q) const { return cmp(q) == 0; }; bool operator!=(point q) const { return cmp(q) != 0; }; bool operator<(point q) const { return cmp(q) < 0; }; }; ostream &operator<<(ostream &os, const point &p) { os << ( << p.x << , << p.y << ) ; } long long dot(point a, point b) { return a.x * b.x + a.y * b.y; } long long cross(point a, point b) { return a.x * b.y - a.y * b.x; } long long abs2(point a) { return dot(a, a); } bool collinear(point a, point b, point c) { return cmp(cross((b - a), (c - a))) == 0; } int ccw(point a, point b, point p) { return cmp(cross((b - a), (p - a))); } point pivot; bool radial_lt(point a, point b) { int R = ccw(pivot, a, b); if (R == 0) return dot(pivot - a, pivot - a) < dot(pivot - b, pivot - b); else return (R == 1); } vector<point> convexhull(vector<point> T) { sort(T.begin(), T.end()); T.resize(unique(T.begin(), T.end()) - T.begin()); int tam = 0, n = T.size(); vector<point> U; int idx = min_element(T.begin(), T.end()) - T.begin(); pivot = T[idx]; swap(T[0], T[idx]); sort(++T.begin(), T.end(), radial_lt); for (int i = 0; i < T.size(); i++) { while (tam > 1 && ccw(U[tam - 2], U[tam - 1], T[i]) <= 0) U.pop_back(), tam--; U.push_back(T[i]); tam++; } return U; } void show(pair<pair<long long, long long>, pair<long long, long long> > s) { cout << s.first.first << << s.first.second << << s.second.first << << s.second.second << endl; } int least_rot( vector<pair<pair<long long, long long>, pair<long long, long long> > > second) { int n = second.size(); for (int i = (0); i < (n); i++) second.push_back(second[i]); vector<int> f(second.size(), -1); int k = 0; for (int j = 1; j < second.size(); j++) { pair<pair<long long, long long>, pair<long long, long long> > sj = second[j]; int i = f[j - k - 1]; while (i != -1 && sj != second[k + i + 1]) { if (sj < second[k + i + 1]) k = j - i - 1; i = f[i]; } if (sj != second[k + i + 1]) { if (sj < second[k]) k = j; f[j - k] = -1; } else f[j - k] = i + 1; } return k; } int main() { int n, m; scanf( %d %d , &n, &m); vector<point> A(n), B(m); point p; for (int i = (0); i < (n); i++) { scanf( %lld %lld , &p.x, &p.y); A[i] = p; } for (int i = (0); i < (m); i++) { scanf( %lld %lld , &p.x, &p.y); B[i] = p; } A = convexhull(A); B = convexhull(B); n = A.size(); m = B.size(); if (n != m) { cout << NO n ; return 0; } vector<pair<pair<long long, long long>, pair<long long, long long> > > AA, BB; point esq, dir; int ee, dd; for (int i = (0); i < (n); i++) { ee = i - 1; if (ee < 0) ee += n; dd = i + 1; if (dd >= n) dd %= n; esq = A[ee] - A[i], dir = A[dd] - A[i]; AA.push_back(make_pair(make_pair(cross(esq, dir), dot(esq, dir)), make_pair(abs2(esq), abs2(dir)))); } for (int i = (0); i < (n); i++) { ee = i - 1; if (ee < 0) ee += n; dd = i + 1; if (dd >= n) dd %= n; esq = B[ee] - B[i], dir = B[dd] - B[i]; BB.push_back(make_pair(make_pair(cross(esq, dir), dot(esq, dir)), make_pair(abs2(esq), abs2(dir)))); } int u = least_rot(AA); int v = least_rot(BB); bool ok = true; for (int i = (0); i < (n); i++) { if (AA[u] != BB[v]) { ok = false; break; } u = (u + 1) % n; v = (v + 1) % n; } if (ok) cout << YES n ; else cout << NO n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MAJ3_SYMBOL_V
`define SKY130_FD_SC_MS__MAJ3_SYMBOL_V
/**
* maj3: 3-input majority vote.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__maj3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__MAJ3_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int n, m; struct edge { int from; int to; int next; } E[500005 << 1]; int head[100005]; int deg[100005]; int tmp[500005]; int used[500005 << 1]; int size = 1; void add_edge(int u, int v) { size++; E[size].from = u; E[size].to = v; E[size].next = head[u]; head[u] = size; } stack<int> s, ans; void euler() { s.push(1); while (!s.empty()) { int x = s.top(); int i = head[x]; while (i != 0 && used[i] == 1) i = E[i].next; if (i != 0) { s.push(E[i].to); used[i] = used[i ^ 1] = 1; head[x] = E[i].next; } else { s.pop(); ans.push(x); } } } int main() { int u, v; scanf( %d %d , &n, &m); for (int i = 1; i <= m; i++) { scanf( %d %d , &u, &v); add_edge(u, v); add_edge(v, u); deg[u]++; deg[v]++; } int pre = 0; int cnt = 0; for (int i = 1; i <= n; i++) { if (deg[i] % 2 == 1) { if (pre != 0) { add_edge(pre, i); add_edge(i, pre); pre = 0; } else pre = i; } } if (((size - 1) / 2) % 2 == 1) { add_edge(1, 1); size++; } euler(); printf( %d n , (size - 1) / 2); int ptr = 0; while (!ans.empty()) { tmp[++ptr] = ans.top(); ans.pop(); } for (int i = 1; i <= ptr - 1; i++) { if (i & 1) printf( %d %d n , tmp[i], tmp[i + 1]); else printf( %d %d n , tmp[i + 1], tmp[i]); } } |
/* Concrete parameterizations of argmin for testing.
*
* Copyright (c) 2016, Stephen Longfield, stephenlongfield.com
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`include "argmin_10.v"
module argmin_test(
input clk,
input rst,
input wire [10*32-1:0] inp,
output wire [31:0] outp,
output wire [3:0] outp_addr
);
argmin_10#(.WIDTH(32)) am(clk, rst, inp, outp, outp_addr);
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
// IP Revision: 5
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module select2 (
clka,
wea,
addra,
dina,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [0 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [11 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [11 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [11 : 0] douta;
blk_mem_gen_v8_3_5 #(
.C_FAMILY("artix7"),
.C_XDEVICEFAMILY("artix7"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(0),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(1),
.C_INIT_FILE_NAME("select2.mif"),
.C_INIT_FILE("select2.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(0),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(12),
.C_READ_WIDTH_A(12),
.C_WRITE_DEPTH_A(2109),
.C_READ_DEPTH_A(2109),
.C_ADDRA_WIDTH(12),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(12),
.C_READ_WIDTH_B(12),
.C_WRITE_DEPTH_B(2109),
.C_READ_DEPTH_B(2109),
.C_ADDRB_WIDTH(12),
.C_HAS_MEM_OUTPUT_REGS_A(1),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_EN_SAFETY_CKT(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("1"),
.C_COUNT_18K_BRAM("1"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 3.822999 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(1'D0),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(12'B0),
.dinb(12'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.rsta_busy(),
.rstb_busy(),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(12'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
//Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_performance_counter_0 (
// inputs:
address,
begintransfer,
clk,
reset_n,
write,
writedata,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 2: 0] address;
input begintransfer;
input clk;
input reset_n;
input write;
input [ 31: 0] writedata;
wire clk_en;
reg [ 63: 0] event_counter_0;
reg [ 63: 0] event_counter_1;
wire global_enable;
wire global_reset;
wire go_strobe_0;
wire go_strobe_1;
wire [ 31: 0] read_mux_out;
reg [ 31: 0] readdata;
wire stop_strobe_0;
wire stop_strobe_1;
reg [ 63: 0] time_counter_0;
reg [ 63: 0] time_counter_1;
reg time_counter_enable_0;
reg time_counter_enable_1;
wire write_strobe;
//control_slave, which is an e_avalon_slave
assign clk_en = -1;
assign write_strobe = write & begintransfer;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
time_counter_0 <= 0;
else if ((time_counter_enable_0 & global_enable) | global_reset)
if (global_reset)
time_counter_0 <= 0;
else
time_counter_0 <= time_counter_0 + 1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
event_counter_0 <= 0;
else if ((go_strobe_0 & global_enable) | global_reset)
if (global_reset)
event_counter_0 <= 0;
else
event_counter_0 <= event_counter_0 + 1;
end
assign stop_strobe_0 = (address == 0) && write_strobe;
assign go_strobe_0 = (address == 1) && write_strobe;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
time_counter_enable_0 <= 0;
else if (clk_en)
if (stop_strobe_0 | global_reset)
time_counter_enable_0 <= 0;
else if (go_strobe_0)
time_counter_enable_0 <= -1;
end
assign global_enable = time_counter_enable_0 | go_strobe_0;
assign global_reset = stop_strobe_0 && writedata[0];
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
time_counter_1 <= 0;
else if ((time_counter_enable_1 & global_enable) | global_reset)
if (global_reset)
time_counter_1 <= 0;
else
time_counter_1 <= time_counter_1 + 1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
event_counter_1 <= 0;
else if ((go_strobe_1 & global_enable) | global_reset)
if (global_reset)
event_counter_1 <= 0;
else
event_counter_1 <= event_counter_1 + 1;
end
assign stop_strobe_1 = (address == 4) && write_strobe;
assign go_strobe_1 = (address == 5) && write_strobe;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
time_counter_enable_1 <= 0;
else if (clk_en)
if (stop_strobe_1 | global_reset)
time_counter_enable_1 <= 0;
else if (go_strobe_1)
time_counter_enable_1 <= -1;
end
assign read_mux_out = ({32 {(address == 0)}} & time_counter_0[31 : 0]) |
({32 {(address == 1)}} & time_counter_0[63 : 32]) |
({32 {(address == 2)}} & event_counter_0) |
({32 {(address == 4)}} & time_counter_1[31 : 0]) |
({32 {(address == 5)}} & time_counter_1[63 : 32]) |
({32 {(address == 6)}} & event_counter_1);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= read_mux_out;
end
endmodule
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module i2c_core #(
parameter ABUSWIDTH = 16,
parameter MEM_BYTES = 1,
parameter IGNORE_ACK = 0
) (
input wire BUS_CLK,
input wire BUS_RST,
input wire [ABUSWIDTH-1:0] BUS_ADD,
input wire [7:0] BUS_DATA_IN,
input wire BUS_RD,
input wire BUS_WR,
output reg [7:0] BUS_DATA_OUT,
input wire I2C_CLK,
inout wire I2C_SDA,
inout wire I2C_SCL
);
localparam VERSION = 1;
reg [7:0] status_regs [7:0];
wire RST;
wire SOFT_RST;
assign SOFT_RST = (BUS_ADD==0 && BUS_WR);
assign RST = BUS_RST || SOFT_RST;
wire START;
assign SOFT_RST = (BUS_ADD==0 && BUS_WR);
assign START = (BUS_ADD==1 && BUS_WR);
always @(posedge BUS_CLK) begin
if(RST) begin
status_regs[0] <= 0; //rst/version
status_regs[1] <= 0; //status
status_regs[2] <= 0; //addr
status_regs[3] <= MEM_BYTES[7:0]; //size
status_regs[4] <= MEM_BYTES[15:8]; //size
status_regs[5] <= 0; //size2
status_regs[6] <= 0;
status_regs[7] <= 0;
end
else if(BUS_WR && BUS_ADD < 8)
status_regs[BUS_ADD[2:0]] <= BUS_DATA_IN;
end
wire [7:0] I2C_ADD;
assign I2C_ADD = status_regs[2];
reg SDA_READBACK;
wire [15:0] CONF_SIZE;
assign CONF_SIZE = {status_regs[4], status_regs[3]};
wire [7:0] BUS_STATUS_OUT;
assign BUS_STATUS_OUT = status_regs[BUS_ADD[3:0]];
reg CONF_DONE;
reg CONF_NO_ACK;
reg [7:0] BUS_DATA_OUT_REG;
always @(posedge BUS_CLK) begin
if(BUS_RD) begin
if(BUS_ADD == 0)
BUS_DATA_OUT_REG <= VERSION;
else if(BUS_ADD == 1)
BUS_DATA_OUT_REG <= {6'b0, CONF_NO_ACK, CONF_DONE};
else if(BUS_ADD == 6)
BUS_DATA_OUT_REG <= MEM_BYTES[7:0];
else if(BUS_ADD == 7)
BUS_DATA_OUT_REG <= MEM_BYTES[15:8];
else if(BUS_ADD < 8)
BUS_DATA_OUT_REG <= BUS_STATUS_OUT;
end
end
reg [ABUSWIDTH-1:0] PREV_BUS_ADD;
always @(posedge BUS_CLK) begin
if(BUS_RD) begin
PREV_BUS_ADD <= BUS_ADD;
end
end
reg [7:0] OUT_MEM;
always @(*) begin
if(PREV_BUS_ADD < 8)
BUS_DATA_OUT = BUS_DATA_OUT_REG;
else if(PREV_BUS_ADD < 8 + MEM_BYTES )
BUS_DATA_OUT = OUT_MEM;
else
BUS_DATA_OUT = 8'hxx;
end
wire BUS_MEM_EN;
wire [ABUSWIDTH-1:0] BUS_MEM_ADD;
assign BUS_MEM_EN = (BUS_WR | BUS_RD) & BUS_ADD >= 8;
assign BUS_MEM_ADD = BUS_ADD-8;
(* RAM_STYLE="{BLOCK_POWER2}" *)
reg [7:0] mem [MEM_BYTES-1:0];
always @(posedge BUS_CLK)
if (BUS_MEM_EN) begin
if (BUS_WR)
mem[BUS_MEM_ADD] <= BUS_DATA_IN;
OUT_MEM <= mem[BUS_MEM_ADD];
end
wire EN_MEM_I2C;
wire WE_MEM_I2C;
reg [2:0] bit_count;
reg [15:0] byte_count;
wire [15:0] MEM_I2_WR;
reg [1:0] div_cnt;
reg [7:0] DATA_BYTE;
reg [7:0] DATA_BYTE_READBCK;
assign MEM_I2_WR = WE_MEM_I2C ? byte_count-1: byte_count;
always @(posedge I2C_CLK)
if (EN_MEM_I2C) begin
if (WE_MEM_I2C)
mem[MEM_I2_WR] <= DATA_BYTE_READBCK;
DATA_BYTE <= mem[MEM_I2_WR];
end
wire RST_SYNC;
wire RST_SOFT_SYNC;
cdc_pulse_sync rst_pulse_sync (.clk_in(BUS_CLK), .pulse_in(RST), .clk_out(I2C_CLK), .pulse_out(RST_SOFT_SYNC));
assign RST_SYNC = RST_SOFT_SYNC || BUS_RST;
wire START_SYNC;
cdc_pulse_sync start_pulse_sync (.clk_in(BUS_CLK), .pulse_in(START), .clk_out(I2C_CLK), .pulse_out(START_SYNC));
reg START_FSM;
localparam STATE_IDLE = 0, STATE_START = 1, STATE_ADDR = 2, STATE_RW = 3, STATE_AACK = 4, STATE_DATA_W = 5, STATE_DATA_R = 6, STATE_DACK_W = 7, STATE_DACK_R = 8, STATE_DACK_LAST = 9, STATE_STOP = 10;
always @(posedge I2C_CLK) begin
if (RST_SYNC)
START_FSM <= 0;
else if(START_SYNC)
START_FSM <= 1;
else if(div_cnt == 3 && START_FSM)
START_FSM <= 0;
end
reg [3:0] state, next_state;
always @(posedge I2C_CLK) begin
if (RST_SYNC)
state <= STATE_IDLE;
else if(div_cnt==3)
state <= next_state;
end
wire CONF_MODE;
assign CONF_MODE = I2C_ADD[0];
always @(*) begin
next_state = state; //default
case(state)
STATE_IDLE:
if(START_FSM)
next_state = STATE_START;
STATE_START:
next_state = STATE_ADDR;
STATE_ADDR:
if(bit_count==7)
next_state = STATE_AACK;
STATE_AACK:
if(SDA_READBACK==0) begin
if(CONF_MODE)
next_state = STATE_DATA_R;
else
next_state = STATE_DATA_W;
end
else
next_state = STATE_IDLE;
STATE_DATA_R:
if(bit_count==7)
next_state = STATE_DACK_R;
STATE_DATA_W:
if(bit_count==7)
next_state = STATE_DACK_W;
STATE_DACK_W:
begin
if(byte_count == CONF_SIZE) begin
if(SDA_READBACK==0)
next_state = STATE_STOP;
else
next_state = STATE_IDLE;
end
else
next_state = STATE_DATA_W;
end
STATE_DACK_R:
if(byte_count == CONF_SIZE)
next_state = STATE_STOP;
else
next_state = STATE_DATA_R;
STATE_STOP:
next_state = STATE_IDLE;
endcase
end
always @(posedge I2C_CLK) begin
if (state == STATE_AACK | state == STATE_START | state == STATE_DACK_W | state == STATE_DACK_R)
bit_count <= 0;
else if(div_cnt==3)
bit_count <= bit_count + 1;
end
always @(posedge I2C_CLK) begin
if (state == STATE_IDLE)
byte_count <= 0;
else if((next_state == STATE_DACK_W | next_state == STATE_DACK_R) & div_cnt==3)
byte_count <= byte_count + 1;
end
always @(posedge I2C_CLK) begin
if (RST_SYNC)
div_cnt <= 0;
else
div_cnt <= div_cnt + 1;
end
assign WE_MEM_I2C = (state == STATE_DACK_R & div_cnt==2);
assign EN_MEM_I2C = WE_MEM_I2C | ((state == STATE_DACK_W | state == STATE_AACK) & div_cnt==2);
reg SDA_D0;
reg SCL_D0;
always @(*) begin
SDA_D0 = 1;
SCL_D0 = 1;
case(state)
STATE_START:
begin
SDA_D0 = 0;
SCL_D0 = 0;
end
STATE_ADDR:
begin
SCL_D0 = 0;
SDA_D0 = I2C_ADD[7-bit_count];
end
STATE_AACK:
SCL_D0 = 0;
STATE_DATA_R:
SCL_D0 = 0;
STATE_DATA_W:
begin
SCL_D0 = 0;
SDA_D0 = DATA_BYTE[7-bit_count];
end
STATE_DACK_W:
SCL_D0 = 0;
STATE_DACK_R:
begin
SCL_D0 = 0;
if(byte_count != CONF_SIZE)
SDA_D0 = 0;
end
STATE_STOP:
begin
SDA_D0 = 0;
end
endcase
end
wire SLAVE_ACK;
wire NO_ACK;
assign NO_ACK = ((state == STATE_AACK & SDA_READBACK) | (state == STATE_DACK_W & SDA_READBACK)) & div_cnt == 3;
reg SDA;
always @(posedge I2C_CLK)
if(div_cnt == 0)
SDA <= SDA_D0;
assign I2C_SDA = SDA ? 1'bz : 1'b0;
reg SCL;
always @(posedge I2C_CLK)
if(div_cnt == 3)
SCL <= SCL_D0;
else if(div_cnt == 1)
SCL <= 1;
assign I2C_SCL = SCL ? 1'bz : 1'b0;
always @(posedge I2C_CLK)
if(div_cnt == 1)
SDA_READBACK <= IGNORE_ACK ? 0 : I2C_SDA;
always @(posedge I2C_CLK)
if(div_cnt == 3)
DATA_BYTE_READBCK[7-bit_count] <= I2C_SDA;
wire DONE;
assign DONE = (state == STATE_STOP);
wire DONE_SYNC;
cdc_pulse_sync done_pulse_sync (.clk_in(I2C_CLK), .pulse_in(DONE), .clk_out(BUS_CLK), .pulse_out(DONE_SYNC));
always @(posedge BUS_CLK)
if(RST)
CONF_DONE <= 1;
else if(START)
CONF_DONE <= 0;
else if(DONE_SYNC)
CONF_DONE <= 1;
wire NO_ACK_SYNC;
cdc_pulse_sync ack_pulse_sync (.clk_in(I2C_CLK), .pulse_in(NO_ACK), .clk_out(BUS_CLK), .pulse_out(NO_ACK_SYNC));
always @(posedge BUS_CLK)
if(RST)
CONF_NO_ACK <= 0;
else if(START)
CONF_NO_ACK <= 0;
else if(NO_ACK_SYNC)
CONF_NO_ACK <= 1;
endmodule
|
#include <bits/stdc++.h> using namespace std; bool ACS(string s) { int n1 = s.length(); for (int i = 1; i < n1; i++) if (s[i] != s[0]) return false; return true; } int main() { long long int t; cin >> t; while (t--) { string s; cin >> s; if (s.length() == 1) cout << 0 << endl; else if (s[0] == s[1] && ACS(s)) cout << 1 << endl; else { int ss1 = 0; map<char, int> m1; for (int i = 0; i < s.length(); i++) m1[s[i]]++; for (int i = 0; i < m1.size(); i++) { if (m1[i] > 2) ss1 = ss1 + 2; else ss1 = ss1 + m1[i]; } if (ss1 % 2) cout << (ss1 - 1) / 2 << endl; else cout << ss1 / 2 << endl; } } return 0; } |
/****************************************************************************
* Copyright (c) 2009 by Focus Robotics. All rights reserved.
*
* This program is an unpublished work fully protected by the United States
* copyright laws and is considered a trade secret belonging to the copyright
* holder. No part of this design may be reproduced stored in a retrieval
* system, or transmitted, in any form or by any means, electronic,
* mechanical, photocopying, recording, or otherwise, without prior written
* permission of Focus Robotics, Inc.
*
* Proprietary and Confidential
*
* Created By : Andrew Worcester
* Creation_Date: Tue Mar 10 2009
*
* Brief Description:
*
* Functionality:
*
* Issues:
*
* Limitations:
*
* Testing:
*
* Synthesis:
*
******************************************************************************/
module fric_switch_nosym_8port
(
clk,
rst,
fric_in0,
fric_out0,
fric_in1,
fric_out1,
fric_in2,
fric_out2,
fric_in3,
fric_out3,
fric_in4,
fric_out4,
fric_in5,
fric_out5,
fric_in6,
fric_out6,
fric_in7,
fric_out7
);
// In/Out declarations
input clk;
input rst;
input [7:0] fric_in0;
output [7:0] fric_out0;
input [7:0] fric_in1;
output [7:0] fric_out1;
input [7:0] fric_in2;
output [7:0] fric_out2;
input [7:0] fric_in3;
output [7:0] fric_out3;
input [7:0] fric_in4;
output [7:0] fric_out4;
input [7:0] fric_in5;
output [7:0] fric_out5;
input [7:0] fric_in6;
output [7:0] fric_out6;
input [7:0] fric_in7;
output [7:0] fric_out7;
// Parameters
parameter [3:0] mp_idle = 4'h0,
mp_req_adr = 4'h1,
mp_wdat0 = 4'h2,
mp_wdat1 = 4'h3,
mp_wack = 4'h4,
mp_rep_adr = 4'h5,
mp_rdat0 = 4'h6,
mp_rdat1 = 4'h7,
mp_done = 4'hf;
// Regs and Wires
reg [3:0] mp_state, next_mp_state;
reg [7:0] fric_out0;
reg [7:0] fric_inr0;
reg [7:0] pdat;
reg [3:0] psel, type, psel_reg;
reg capt_psel;
reg chng_port_out;
reg chng_port_in;
reg [7:0] prep;
reg [7:0] fric_out1;
reg [7:0] fric_out2;
reg [7:0] fric_out3;
reg [7:0] fric_out4;
reg [7:0] fric_out5;
reg [7:0] fric_out6;
reg [7:0] fric_out7;
reg [7:0] fric_inr1;
reg [7:0] fric_inr2;
reg [7:0] fric_inr3;
reg [7:0] fric_inr4;
reg [7:0] fric_inr5;
reg [7:0] fric_inr6;
reg [7:0] fric_inr7;
// RTL or Instances
/****************************************************************************
* Subblock: Master Port (port0)
*
* This is the only port which will be receiving requests from it's client.
* Other ports will forward those requests to their clients and get and ack
* back from them.
*
* The FSM basically works like this: monitor fric_in0 upper 4 bits until
* they are non-zero. Select the output port from the lower 4 bits of that
* word. Overwrite the lower 4 bits of that word with 0's and send that to
* the output port. Send the next three words to that same output port and
* wait for the ack. So input port had to be selected the same as the output
* port. Forward the ack to fric_out0, overwriting the lower 4 bits of the
* first word with the selected port. Start again.
*
* Inputs: fric_in0, preply
*
* Outputs: psel, pdat
*
* Todo/Fixme:
*
*/
always @ (/*AS*/fric_inr0 or mp_state or prep or type)
begin
// FSM default outputs
next_mp_state = mp_state;
capt_psel = 0;
chng_port_out = 0;
chng_port_in = 0;
case(mp_state)
mp_idle: // wait for transaction to start then capture and send type and port
if(|fric_inr0[7:4]!=0) begin
capt_psel = 1'b1;
chng_port_out = 1'b1;
next_mp_state = mp_req_adr;
end
mp_req_adr: // send addr, go to wait ack if read, go to dat if write
if(type==4'b0010)
next_mp_state = mp_wdat0;
else if(type==4'b0011)
next_mp_state = mp_wack;
else
$display("Illegal type captured in fric switch nosym\n");
mp_wdat0:
next_mp_state = mp_wdat1;
mp_wdat1:
next_mp_state = mp_wack;
mp_wack:
// wait for ack to start and then send type, port
// change port value back from this port to slave port
// FIXME: should probably re-capture type instead of relying on
// the ack to be correct based on the request.
// FIXME: with quick turnaround, is it possible for the ack to
// start before we get to this state?!?! probably not...
if(|prep[7:0]!=0) begin
chng_port_in = 1'b1;
next_mp_state = mp_rep_adr;
end
mp_rep_adr:
// send reply addr, got to idle if this is a write ack or continue
// for a read ack
if(type==4'b0010) // write ack only 2 cycles
next_mp_state = mp_idle;
else
next_mp_state = mp_rdat0;
mp_rdat0:
next_mp_state = mp_rdat1;
mp_rdat1:
next_mp_state = mp_idle;
default: next_mp_state = mp_idle;
endcase // case(mp_state)
end // always @ (...
always @ (posedge clk)
begin
if(rst==1'b1)
begin
mp_state <= mp_idle;
fric_inr0 <= 0;
psel_reg <= 0;
type <= 0;
fric_out0 <= 0;
end
else
begin
mp_state <= next_mp_state;
fric_inr0 <= fric_in0;
if(capt_psel==1'b1) begin
psel_reg <= fric_inr0[3:0];
type <= fric_inr0[7:4];
end
if(chng_port_in==1'b1)
fric_out0 <= {prep[7:4], psel};
else
fric_out0 <= prep;
end
end // always @ (posedge clk)
always @ (/*AS*/capt_psel or chng_port_out or fric_inr0 or psel_reg)
begin
if(chng_port_out==1'b1)
pdat <= {fric_inr0[7:4], 4'h0};
else
pdat <= fric_inr0;
if(capt_psel==1'b1)
psel = fric_inr0[3:0];
else
psel = psel_reg;
end
/****************************************************************************
* Subblock: Slave Ports (ports 1-7)
*
* Note that the various slave fric_out ports aren't driven to zero
* explicitly so each transaction must go to zeroes before another one starts
*
* Inputs:
* psel, pdat: from master port
* fric_in1 - fric_in7
*
* Outputs: prep: from reply port back to master
* fric_out1 - fric_out7
*
* Todo/Fixme:
*
*/
always @ (posedge clk)
begin
if(rst==1'b1)
begin
prep <= 0;
fric_inr1 <= 0;
fric_inr2 <= 0;
fric_inr3 <= 0;
fric_inr4 <= 0;
fric_inr5 <= 0;
fric_inr6 <= 0;
fric_inr7 <= 0;
fric_out1 <= 0;
fric_out2 <= 0;
fric_out3 <= 0;
fric_out4 <= 0;
fric_out5 <= 0;
fric_out6 <= 0;
fric_out7 <= 0;
end
else
begin
fric_inr1 <= fric_in1;
fric_inr2 <= fric_in2;
fric_inr3 <= fric_in3;
fric_inr4 <= fric_in4;
fric_inr5 <= fric_in5;
fric_inr6 <= fric_in6;
fric_inr7 <= fric_in7;
case(psel)
3'b000: ;
3'b001: fric_out1 <= pdat;
3'b010: fric_out2 <= pdat;
3'b011: fric_out3 <= pdat;
3'b100: fric_out4 <= pdat;
3'b101: fric_out5 <= pdat;
3'b110: fric_out6 <= pdat;
3'b111: fric_out7 <= pdat;
endcase // case(psel)
end // else: !if(rst==1'b1)
end // always @ (posedge clk)
always @ (/*AS*/fric_inr1 or fric_inr2 or fric_inr3 or fric_inr4 or fric_inr5
or fric_inr6 or fric_inr7 or psel)
begin
case(psel)
3'b000: prep = 0;
3'b001: prep = fric_inr1;
3'b010: prep = fric_inr2;
3'b011: prep = fric_inr3;
3'b100: prep = fric_inr4;
3'b101: prep = fric_inr5;
3'b110: prep = fric_inr6;
3'b111: prep = fric_inr7;
endcase // case(psel)
end // always @ (...
/****************************************************************************
* Subblock
*
* Inputs:
*
* Outputs:
*
* Todo/Fixme:
*
*/
endmodule // fric_switch_8port
|
//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 3.7
// \ \ Application : MIG
// / / Filename : ecc_gen.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : Virtex-6
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ps/1ps
// Generate the ecc code. Note that the synthesizer should
// generate this as a static logic. Code in this block should
// never run during simulation phase, or directly impact timing.
//
// The code generated is a single correct, double detect code.
// It is the classic Hamming code. Instead, the code is
// optimized for minimal/balanced tree depth and size. See
// Hsiao IBM Technial Journal 1970.
//
// The code is returned as a single bit vector, h_rows. This was
// the only way to "subroutinize" this with the restrictions of
// disallowed include files and that matrices cannot be passed
// in ports.
//
// Factorial and the combos functions are defined. Combos
// simply computes the number of combinations from the set
// size and elements at a time.
//
// The function next_combo computes the next combination in
// lexicographical order given the "current" combination. Its
// output is undefined if given the last combination in the
// lexicographical order.
//
// next_combo is insensitive to the number of elements in the
// combinations.
//
// An H transpose matrix is generated because that's the easiest
// way to do it. The H transpose matrix is generated by taking
// the one at a time combinations, then the 3 at a time, then
// the 5 at a time. The number combinations used is equal to
// the width of the code (CODE_WIDTH). The boundaries between
// the 1, 3 and 5 groups are hardcoded in the for loop.
//
// At the same time the h_rows vector is generated from the
// H transpose matrix.
module ecc_gen
#(
parameter CODE_WIDTH = 72,
parameter ECC_WIDTH = 8,
parameter DATA_WIDTH = 64
)
(
/*AUTOARG*/
// Outputs
h_rows
);
function integer factorial (input integer i);
integer index;
if (i == 1) factorial = 1;
else begin
factorial = 1;
for (index=2; index<=i; index=index+1)
factorial = factorial * index;
end
endfunction // factorial
function integer combos (input integer n, k);
combos = factorial(n)/(factorial(k)*factorial(n-k));
endfunction // combinations
// function next_combo
// Given a combination, return the next combo in lexicographical
// order. Scans from right to left. Assumes the first combination
// is k ones all of the way to the left.
//
// Upon entry, initialize seen0, trig1, and ones. "seen0" means
// that a zero has been observed while scanning from right to left.
// "trig1" means that a one have been observed _after_ seen0 is set.
// "ones" counts the number of ones observed while scanning the input.
//
// If trig1 is one, just copy the input bit to the output and increment
// to the next bit. Otherwise set the the output bit to zero, if the
// input is a one, increment ones. If the input bit is a one and seen0
// is true, dump out the accumulated ones. Set seen0 to the complement
// of the input bit. Note that seen0 is not used subsequent to trig1
// getting set.
function [ECC_WIDTH-1:0] next_combo (input [ECC_WIDTH-1:0] i);
integer index;
integer dump_index;
reg seen0;
reg trig1;
// integer ones;
reg [ECC_WIDTH-1:0] ones;
begin
seen0 = 1'b0;
trig1 = 1'b0;
ones = 0;
for (index=0; index<ECC_WIDTH; index=index+1)
begin
// The "== 1'bx" is so this will converge at time zero.
// XST assumes false, which should be OK.
if ((&i == 1'bx) || trig1) next_combo[index] = i[index];
else begin
next_combo[index] = 1'b0;
ones = ones + i[index];
if (i[index] && seen0) begin
trig1 = 1'b1;
for (dump_index=index-1; dump_index>=0;dump_index=dump_index-1)
if (dump_index>=index-ones) next_combo[dump_index] = 1'b1;
end
seen0 = ~i[index];
end // else: !if(trig1)
end
end // function
endfunction // next_combo
wire [ECC_WIDTH-1:0] ht_matrix [CODE_WIDTH-1:0];
output wire [CODE_WIDTH*ECC_WIDTH-1:0] h_rows;
localparam COMBOS_3 = combos(ECC_WIDTH, 3);
localparam COMBOS_5 = combos(ECC_WIDTH, 5);
genvar n;
genvar s;
generate
for (n=0; n<CODE_WIDTH; n=n+1) begin : ht
if (n == 0)
assign ht_matrix[n] = {{3{1'b1}}, {ECC_WIDTH-3{1'b0}}};
else if (n == COMBOS_3 && n < DATA_WIDTH)
assign ht_matrix[n] = {{5{1'b1}}, {ECC_WIDTH-5{1'b0}}};
else if ((n == COMBOS_3+COMBOS_5) && n < DATA_WIDTH)
assign ht_matrix[n] = {{7{1'b1}}, {ECC_WIDTH-7{1'b0}}};
else if (n == DATA_WIDTH)
assign ht_matrix[n] = {{1{1'b1}}, {ECC_WIDTH-1{1'b0}}};
else assign ht_matrix[n] = next_combo(ht_matrix[n-1]);
for (s=0; s<ECC_WIDTH; s=s+1) begin : h_row
assign h_rows[s*CODE_WIDTH+n] = ht_matrix[n][s];
end
end
endgenerate
endmodule // ecc_gen
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always 3.1.1A always reg_lvalue = constant ;
// D: Note that initial has to be before always to execute!
module main ;
reg [3:0] value1 ;
always begin
#0; #0; #0;
end
always value1 = 4'h5 ;
initial
if(value1 != 4'h5)
$display("FAILED - 3.1.1A always reg_lvalue = constant\n");
else
begin
$display("PASSED\n");
$finish;
end
endmodule
|
module prometheus_fx3_partial(
input rst_n,
input clk_100,
input partial_mode_selected,
input i_gpif_in_ch0_rdy_d,
input i_gpif_out_ch0_rdy_d,
output o_gpif_we_n_partial_,
output o_gpif_pkt_end_n_partial_,
output [31:0] data_out_partial
);
reg [2:0]current_partial_state;
reg [2:0]next_partial_state;
//parameters for PARTIAL mode state machine
parameter [2:0] partial_idle = 3'd0;
parameter [2:0] partial_wait_flagb = 3'd1;
parameter [2:0] partial_write = 3'd2;
parameter [2:0] partial_write_wr_delay = 3'd3;
parameter [2:0] partial_wait = 3'd4;
reg [3:0] strob_cnt;
reg strob;
reg [3:0] short_pkt_cnt;
reg [31:0]data_gen_partial;
reg o_gpif_pkt_end_n_prtl_;
assign o_gpif_we_n_partial_ = ((current_partial_state == partial_write) && (i_gpif_out_ch0_rdy_d == 1'b1)) ? 1'b0 : 1'b1;
//counters for short pkt
always @(posedge clk_100, negedge rst_n)begin
if(!rst_n)begin
short_pkt_cnt <= 4'd0;
end else if(current_partial_state == partial_idle)begin
short_pkt_cnt <= 4'd0;
end else if((current_partial_state == partial_write))begin
short_pkt_cnt <= short_pkt_cnt + 1'b1;
end
end
//counter to generate the strob for PARTIAL
always @(posedge clk_100, negedge rst_n)begin
if(!rst_n)begin
strob_cnt <= 4'd0;
end else if(current_partial_state == partial_idle)begin
strob_cnt <= 4'd0;
end else if(current_partial_state == partial_wait)begin
strob_cnt <= strob_cnt + 1'b1;
end
end
//Strob logic
always@(posedge clk_100, negedge rst_n)begin
if(!rst_n)begin
strob <= 1'b0;
end else if((current_partial_state == partial_wait) && (strob_cnt == 4'b0111)) begin
strob <= !strob;
end
end
always@(*)begin
if((partial_mode_selected) & (strob == 1'b1) & (short_pkt_cnt == 4'b1111))begin
o_gpif_pkt_end_n_prtl_ = 1'b0;
end else begin
o_gpif_pkt_end_n_prtl_ = 1'b1;
end
end
assign o_gpif_pkt_end_n_partial_ = o_gpif_pkt_end_n_prtl_;
//PARTIAL mode state machine
always @(posedge clk_100, negedge rst_n)begin
if(!rst_n)begin
current_partial_state <= partial_idle;
end else begin
current_partial_state <= next_partial_state;
end
end
//PARTIAL mode state machine combo
always @(*)begin
next_partial_state = current_partial_state;
case(current_partial_state)
partial_idle:begin
if((partial_mode_selected) & (i_gpif_in_ch0_rdy_d == 1'b1))begin
next_partial_state = partial_wait_flagb;
end else begin
next_partial_state = partial_idle;
end
end
partial_wait_flagb :begin
if (i_gpif_out_ch0_rdy_d == 1'b1)begin
next_partial_state = partial_write;
end else begin
next_partial_state = partial_wait_flagb;
end
end
partial_write:begin
if((i_gpif_out_ch0_rdy_d == 1'b0) | ((strob == 1'b1) & (short_pkt_cnt == 4'b1111)))begin
next_partial_state = partial_write_wr_delay;
end else begin
next_partial_state = partial_write;
end
end
partial_write_wr_delay:begin
next_partial_state = partial_wait;
end
partial_wait:begin
if(strob_cnt == 4'b0111)begin
next_partial_state = partial_idle;
end else begin
next_partial_state = partial_wait;
end
end
endcase
end
//data generator counter for Partial mode
always @(posedge clk_100, negedge rst_n)begin
if(!rst_n)begin
data_gen_partial <= 32'd0;
end else if((o_gpif_we_n_partial_ == 1'b0) & (partial_mode_selected)) begin
data_gen_partial <= data_gen_partial + 1;
end else if (!partial_mode_selected) begin
data_gen_partial <= 32'd0;
end
end
assign data_out_partial = data_gen_partial;
endmodule
|
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1); const int INF = 2e9; const long long MOD = 1e9 + 7; const int MAXN = 1e5 + 2; const int MN = 1e6 + 3; int d1, d2; int p1, p2; bool usual = 1; int ans[MN]; int main() { int n, q; scanf( %d %d , &n, &q); p1 = 0, p2 = 1; int tipo, x; int pareja; for (int(i) = (0); (i) < (q); ++(i)) { scanf( %d , &tipo); if (tipo == 1) { scanf( %d , &x); p1 += x, p2 += x; } else { if (p1 % 2 == 0) p1++; else p1--; if (p2 % 2 == 0) p2++; else p2--; } p1 %= n; if (p1 < 0) p1 += n; p2 %= n; if (p2 < 0) p2 += n; } int tt; for (int i = 0; i < n; i += 2) { tt = (p1 + i) % n; if (tt < 0) tt += n; ans[tt] = i; } for (int i = 1; i < n; i += 2) { tt = (p2 + i - 1) % n; if (tt < 0) tt += n; ans[tt] = i; } for (int(i) = (0); (i) < (n); ++(i)) printf( %d , ans[i] + 1); return 0; } |
#include <bits/stdc++.h> using namespace std; char Start; int n, m; char S[400005], T[400005]; int fa[400005], tr[400005][26], len[400005], rt[400005], pos[400005], tot, last; vector<int> G[400005]; void ins(int c, bool debug = 0) { if (tr[last][c]) { int p = last, q = tr[last][c]; if (len[q] != len[p] + 1) { int v = ++tot; memcpy(tr[v], tr[q], sizeof tr[q]); fa[v] = fa[q], len[v] = len[p] + 1; for (; ~p && tr[p][c] == q; p = fa[p]) tr[p][c] = v; fa[q] = v; } } else { int u = ++tot, p = last, q; len[u] = len[p] + 1; for (; ~p && !tr[p][c]; p = fa[p]) tr[p][c] = u; if (p == -1) fa[u] = 0; else if (len[q = tr[p][c]] == len[p] + 1) fa[u] = q; else { int v = ++tot; memcpy(tr[v], tr[q], sizeof tr[q]); fa[v] = fa[q], len[v] = len[p] + 1; for (; ~p && tr[p][c] == q; p = fa[p]) tr[p][c] = v; fa[q] = fa[u] = v; } } } int lc[400005 * 30], rc[400005 * 30], mx[400005 * 30], mxp[400005 * 30]; void upd(int u) { if (mx[lc[u]] >= mx[rc[u]]) mx[u] = mx[lc[u]], mxp[u] = mxp[lc[u]]; else mx[u] = mx[rc[u]], mxp[u] = mxp[rc[u]]; } void ins(int &u, int l, int r, int p) { if (!u) u = ++tot, mxp[u] = l; if (l == r) return (void)(mx[u]++); int m = l + r >> 1; p <= m ? ins(lc[u], l, m, p) : ins(rc[u], m + 1, r, p); upd(u); } void merge(int &u, int l, int r) { if (!l || !r) return (void)(u = l + r); u = ++tot; if (lc[l] || rc[l]) { merge(lc[u], lc[l], lc[r]), merge(rc[u], rc[l], rc[r]); upd(u); } else { mx[u] = mx[l] + mx[r], mxp[u] = mxp[l]; } } pair<int, int> qry(int u, int l, int r, int ql, int qr) { if (ql > r || l > qr || !u || ql > qr) return make_pair(0, 0x3f3f3f3f); if (ql <= l && r <= qr) return make_pair(mx[u], mxp[u]); int m = l + r >> 1; pair<int, int> r1 = qry(lc[u], l, m, ql, qr), r2 = qry(rc[u], m + 1, r, ql, qr); if (r1.first >= r2.first) return r1; else return r2; } int f[400005], g[400005], ps[400005]; void dfs(int u) { for (int v : G[u]) { dfs(v), merge(rt[u], rt[u], rt[v]); if (!ps[u]) ps[u] = ps[v]; } } int ans; void dfs2(int u) { ans = max(ans, f[u]); for (int v : G[u]) { if (!u || qry(rt[g[u]], 1, n, ps[v] - len[v] + len[g[u]], ps[v] - 1).first) f[v] = f[u] + 1, g[v] = v; else f[v] = f[u], g[v] = g[u]; dfs2(v); } } char End; int main() { scanf( %d , &n); scanf( %s , S + 1); fa[0] = -1; for (int i = (1), LIM = (n); i <= LIM; i++) ins(S[i] - a ), last = tr[last][S[i] - a ], ps[last] = i; for (int i = (1), LIM = (tot); i <= LIM; i++) { G[fa[i]].push_back(i); if (ps[i]) ins(rt[i], 1, n, ps[i]); } dfs(0); dfs2(0); printf( %d n , ans); } |
#include <bits/stdc++.h> using namespace std; void read_file(bool outToFile = true) {} int n, m; int A[1000 + 9][1000 + 9]; long long K, sum; int mrk = 0, to; int vis[1000 + 9][1000 + 9] = {0}; int di[] = {1, 0, -1, 0}; int dj[] = {0, 1, 0, -1}; set<int> usedAs[1000 + 9][1000 + 9]; bool valid(int i, int j) { return 0 <= i && i < n && 0 <= j && j < m; } bool flood(int i, int j) { if (!valid(i, j) || vis[i][j] == mrk || A[i][j] < to) return false; sum -= to; vis[i][j] = mrk; usedAs[i][j].insert(to); if (sum == 0) return true; for (int d = 0; d < 4; d++) if (flood(i + di[d], j + dj[d])) return true; return false; } int main() { read_file(); while (scanf( %d %d n , &n, &m) != EOF) { scanf( %lld , &K); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) scanf( %d , &A[i][j]), usedAs[i][j].clear(); bool done = false; memset(vis, 0, sizeof vis); for (int i = 0; i < n && !done; i++) { for (int j = 0; j < m && !done; j++) { if (K % A[i][j] == 0 && K / A[i][j] <= n * m) { if (usedAs[i][j].count(A[i][j])) continue; mrk++; to = A[i][j]; sum = K; if (flood(i, j)) done = true; } } } if (!done) { printf( NO n ); continue; } printf( YES n ); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) A[i][j] = vis[i][j] == mrk ? to : 0; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) printf( %d%c , A[i][j], n [j == m - 1]); } } |
/* HW4, Problem 24a */
module jerk_ct(output reg [7:0] count, input clk, reset);
reg [3:0] state; // 0 to 13 needed.
always @(posedge clk) begin
if (reset == 1) begin
state = 13;
end
case(state)
0: begin count <= 8'b00000010; state <= 1; end
1: begin count <= 8'b00000001; state <= 2; end
2: begin count <= 8'b00000100; state <= 3; end
3: begin count <= 8'b00000001; state <= 4; end
4: begin count <= 8'b00001000; state <= 5; end
5: begin count <= 8'b00000001; state <= 6; end
6: begin count <= 8'b00010000; state <= 7; end
7: begin count <= 8'b00000001; state <= 8; end
8: begin count <= 8'b00100000; state <= 9; end
9: begin count <= 8'b00000001; state <= 10;end
10:begin count <= 8'b01000000; state <= 11;end
11:begin count <= 8'b00000001; state <= 12;end
12:begin count <= 8'b10000000; state <= 13;end
13,14,15:
begin count <= 8'b00000001; state <= 0; end
endcase
end
endmodule
module p24_tb();
reg clk, reset;
wire [7:0] count;
jerk_ct device(count, clk, reset);
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial begin
reset = 0;
reset = 1;
#10 reset = 0;
$dumpfile("p24a.vcd");
$dumpvars(0, device);
fork
#201 reset = 1;
#205 reset = 0;
#300 reset = 1;
#320 reset = 0;
#500 $finish;
join
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFBBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__SDFBBP_BEHAVIORAL_PP_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`include "../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_ls__udp_dff_nsr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__sdfbbp (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire SET ;
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire CLK_delayed ;
wire SET_B_delayed ;
wire RESET_B_delayed;
wire mux_out ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
wire cond_D ;
wire cond_SCD ;
wire cond_SCE ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_ls__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK_delayed, mux_out, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
assign cond_D = ( ( SCE_delayed === 1'b0 ) && condb );
assign cond_SCD = ( ( SCE_delayed === 1'b1 ) && condb );
assign cond_SCE = ( ( D_delayed !== SCD_delayed ) && condb );
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFBBP_BEHAVIORAL_PP_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// UART TX Module
// Paul Mumby 2012
// Originally derived from code examples at:
// http://www.fpga4fun.com
//////////////////////////////////////////////////////////////////////////////////
module uart_tx(
clk, //Communications Clock
tx, //Tx IO Pin
tx_byte, //Byte to Transmit
start, //Start Transmitting Byte
busy //Tx Busy Flag
);
//Parameters:
//================================================
parameter CLOCK = 25000000; //Overridden by parent UART core
parameter BAUD = 9600; //Overridden by parent UART core
//IO Definitions:
//================================================
input clk;
wire baudtick;
output reg tx;
input [7:0] tx_byte;
input start;
output busy;
//Register/Wire Definitions:
//================================================
reg [3:0] state = 0;
reg [7:0] byte_buf;
reg muxflag;
wire ready;
//BUFG Instatiation:
//================================================
//Module Instantiation:
//================================================
uart_baudgenerator #(
.CLOCK(CLOCK),
.BAUD(BAUD),
.ROUNDBITS(5)
) BAUDGEN (
.clk(clk),
.baudtick(baudtick)
);
//Assignments:
//================================================
assign ready = (state==0);
assign busy = ~ready;
//Toplevel Logic:
//================================================
//Buffer Logic:
always @(posedge clk)
if(ready & start)
byte_buf <= tx_byte;
//Tx State Machine
always @(posedge clk)
case(state)
4'b0000: if(start) state <= 4'b0001;
4'b0001: if(baudtick) state <= 4'b0100;
4'b0100: if(baudtick) state <= 4'b1000; // start
4'b1000: if(baudtick) state <= 4'b1001; // bit 0
4'b1001: if(baudtick) state <= 4'b1010; // bit 1
4'b1010: if(baudtick) state <= 4'b1011; // bit 2
4'b1011: if(baudtick) state <= 4'b1100; // bit 3
4'b1100: if(baudtick) state <= 4'b1101; // bit 4
4'b1101: if(baudtick) state <= 4'b1110; // bit 5
4'b1110: if(baudtick) state <= 4'b1111; // bit 6
4'b1111: if(baudtick) state <= 4'b0010; // bit 7
4'b0010: if(baudtick) state <= 4'b0011; // stop1
4'b0011: if(baudtick) state <= 4'b0000; // stop2
default: if(baudtick) state <= 4'b0000;
endcase
//Mux Logic
always @(*)
case(state[2:0])
3'd0: muxflag <= byte_buf[0];
3'd1: muxflag <= byte_buf[1];
3'd2: muxflag <= byte_buf[2];
3'd3: muxflag <= byte_buf[3];
3'd4: muxflag <= byte_buf[4];
3'd5: muxflag <= byte_buf[5];
3'd6: muxflag <= byte_buf[6];
3'd7: muxflag <= byte_buf[7];
endcase
//TX IO Drive Logic
always @(posedge clk)
tx <= (state<4) | (state[3] & muxflag);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int mod = 1000000007; void dispvec(set<long long int> arr) { set<long long int>::iterator itr = arr.begin(); while (itr != arr.end()) { cout << *itr << ; itr++; } cout << endl; } struct CustomCompare { bool operator()(const pair<long long int, long long int> &i, const pair<long long int, long long int> &j) { if (i.first == j.first) return i.first < j.first; return i.second < j.second; } }; void solve() { int n; cin >> n; vector<long long int> arr(n); for (int i = 0; i < n; i++) cin >> arr[i]; long long int sum = arr[0] + 1; int curr = arr[0]; for (int i = 1; i < n; i++) { if (arr[i] < arr[i - 1]) { sum += arr[i - 1] - arr[i]; } else if (arr[i] > arr[i - 1]) { sum += arr[i] - arr[i - 1]; } sum += 2; } cout << sum << endl; } int main() { int t = 1; int i = 1; while (i <= t) { solve(); i++; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long int i, t, n; cin >> t; while (t--) { cin >> n; long long arr[n]; for (i = 0; i < n; i++) { cin >> arr[i]; } reverse(arr, arr + n); for (i = 0; i < n - 1; i++) { cout << arr[i] << ; } cout << arr[n - 1] << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long a[200001], b[200001]; int main() { int t; int i, j; cin >> t; while (t--) { long long n, m; cin >> n >> m; for (i = 0; i < n; i++) cin >> a[i] >> b[i]; long long A = 0, B = 0, Ap = 0, Bp = 0; long long tot = 0, sum = 0; for (i = 0; i < n; i++) { A += a[i] - (m - min(m, b[i])); Ap += m - min(m, b[i]); B += b[i] - (m - min(m, a[i])); Bp += m - min(m, a[i]); sum += m; tot += a[i] + b[i] - m; } if (A + A < tot) { cout << tot - (A + A) << endl; for (i = 0; i < n; i++) { cout << m - min(m, b[i]) << << min(m, b[i]) << endl; } } else if (B + B < tot) { cout << tot - (B + B) << endl; for (i = 0; i < n; i++) { cout << min(m, a[i]) << << m - min(m, a[i]) << endl; } } else { long long togo = A - tot / 2; cout << (tot & 1) << endl; for (i = 0; i < n; i++) { long long x = min(togo, min(m, b[i])); x = min(x, a[i] - (m - min(m, b[i]))); togo -= x; cout << m - min(m, b[i]) + x << << min(m, b[i]) - x << endl; } } } } |
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