text
stringlengths 59
71.4k
|
|---|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module adc_model
(input clk, input rst,
output [13:0] adc_a,
output adc_ovf_a,
input adc_on_a,
input adc_oe_a,
output [13:0] adc_b,
output adc_ovf_b,
input adc_on_b,
input adc_oe_b
);
math_real math ( ) ;
reg [13:0] adc_a_int = 0;
reg [13:0] adc_b_int = 0;
assign adc_a = adc_oe_a ? adc_a_int : 14'bz;
assign adc_ovf_a = adc_oe_a ? 1'b0 : 1'bz;
assign adc_b = adc_oe_b ? adc_b_int : 14'bz;
assign adc_ovf_b = adc_oe_b ? 1'b0 : 1'bz;
real phase = 0;
real freq = 330000/100000000;
real scale = 8190; // math.pow(2,13)-2;
always @(posedge clk)
if(rst)
begin
adc_a_int <= 0;
adc_b_int <= 0;
end
else
begin
if(adc_on_a)
//adc_a_int <= $rtoi(math.round(math.sin(phase*math.MATH_2_PI)*scale)) ;
adc_a_int <= adc_a_int + 3;
if(adc_on_b)
adc_b_int <= adc_b_int - 7;
//adc_b_int <= $rtoi(math.round(math.cos(phase*math.MATH_2_PI)*scale)) ;
if(phase > 1)
phase <= phase + freq - 1;
else
phase <= phase + freq;
end
endmodule // adc_model
|
#include <bits/stdc++.h> using namespace std; set<string> S; string rotate1(string s) { string s1 = s; s1[1] = s[2]; s1[2] = s[4]; s1[4] = s[5]; s1[5] = s[1]; return s1; } string rotate2(string s) { string s1 = s; s1[0] = s[1]; s1[1] = s[3]; s1[3] = s[4]; s1[4] = s[0]; return s1; } set<pair<string, bool> > poszlo; void go(string s, bool sel) { if (!poszlo.insert(make_pair(s, sel)).second) return; S.insert(s); if (sel) { s = rotate2(s); go(s, 0); s = rotate2(s); go(s, 0); s = rotate2(s); go(s, 0); } else { s = rotate1(s); go(s, 1); s = rotate1(s); go(s, 1); s = rotate1(s); go(s, 1); } } int main() { string s; cin >> s; sort(s.begin(), s.end()); int res = 0; do { if (S.insert(s).second) res++; poszlo.clear(); go(s, 0); go(s, 1); } while (next_permutation(s.begin(), s.end())); printf( %d n , res); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, i, j; cin >> n; vector<int> ct[n + 1]; for (i = 0; i < 2 * n; i++) { int x; cin >> x; ct[x].push_back(i); } int p1 = 0, p2 = 0; long long ans = 0; for (i = 1; i <= n; i++) { ans += min(abs(ct[i][0] - p1) + abs(ct[i][1] - p2), abs(ct[i][0] - p2) + abs(ct[i][1] - p1)); p1 = ct[i][0]; p2 = ct[i][1]; } cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, h, count = 0; cin >> n >> h; int a[n]; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) { if (a[i] > h) count += 2; else count += 1; } cout << count; } |
module ram_dual
#(
parameter init_type="hex", init_data="data.hex", dat_width=32, adr_width=32, mem_size=1024
)
(
input [dat_width-1:0] dat0_i,
input [adr_width-1:0] adr0_i,
input we0_i,
output reg [dat_width-1:0] dat0_o,
input [dat_width-1:0] dat1_i,
input [adr_width-1:0] adr1_i,
input we1_i,
output reg [dat_width-1:0] dat1_o,
input clk
);
//(* ram_style="block" *)
reg [dat_width-1:0] ram [0:mem_size - 1] ;
always @ (posedge clk)
begin
dat0_o <= ram[adr0_i];
if (we0_i)
ram[adr0_i] <= dat0_i;
end
always @ (posedge clk)
begin
dat1_o <= ram[adr1_i];
if (we1_i)
ram[adr1_i] <= dat1_i;
end
// elf processing
integer File_ID, Rd_Status;
reg [7:0] File_Rdata [0 : (mem_size * (dat_width / 8)) - 1] ;
integer File_ptr, header_idx;
integer e_machine, e_phnum, p_offset, p_vaddr, p_filesz, elf_param;
integer bytes_in_word, load_byte_counter;
integer ram_ptr, wrword_byte_counter;
reg [dat_width-1:0] wrword;
reg [8*8:0] e_machine_str;
initial
begin
if (init_type != "none")
begin
if (init_type == "hex") $readmemh(init_data, ram, 0);
else if (init_type == "elf")
begin
File_ID = $fopen(init_data, "rb");
Rd_Status = $fread(File_Rdata, File_ID);
if (Rd_Status == 0) $fatal("File %s not found!", init_data);
$display("\n##################################");
$display("#### Loading elf file: %s", init_data);
// parsing ELF header
if ((File_Rdata[0] != 8'h7f) || (File_Rdata[1] != 8'h45) || (File_Rdata[2] != 8'h4c) || (File_Rdata[3] != 8'h46)) $fatal("%s: elf format incorrect!", init_data);
e_machine = File_Rdata[18] + (File_Rdata[19] << 8);
e_machine_str = "UNKNOWN";
if (e_machine == 32'hF3) e_machine_str = "RISC-V";
$display("e_machine: 0x%x (%s)", e_machine, e_machine_str);
e_phnum = File_Rdata[44] + (File_Rdata[45] << 8);
$display("e_phnum: 0x%x", e_phnum);
File_ptr = 52;
for (header_idx = 0; header_idx < e_phnum; header_idx = header_idx + 1)
begin
// parsing program header
$display("---- HEADER: %0d ----", header_idx);
elf_param = File_Rdata[File_ptr] + (File_Rdata[File_ptr+1] << 8) + (File_Rdata[File_ptr+2] << 16) + (File_Rdata[File_ptr+3] << 24);
$display("p_type: 0x%x", elf_param);
File_ptr = File_ptr + 4;
p_offset = File_Rdata[File_ptr] + (File_Rdata[File_ptr+1] << 8) + (File_Rdata[File_ptr+2] << 16) + (File_Rdata[File_ptr+3] << 24);
$display("p_offset: 0x%x", p_offset);
File_ptr = File_ptr + 4;
p_vaddr = File_Rdata[File_ptr] + (File_Rdata[File_ptr+1] << 8) + (File_Rdata[File_ptr+2] << 16) + (File_Rdata[File_ptr+3] << 24);
$display("p_vaddr: 0x%x", p_vaddr);
File_ptr = File_ptr + 4;
elf_param = File_Rdata[File_ptr] + (File_Rdata[File_ptr+1] << 8) + (File_Rdata[File_ptr+2] << 16) + (File_Rdata[File_ptr+3] << 24);
$display("p_paddr: 0x%x", elf_param);
File_ptr = File_ptr + 4;
p_filesz = File_Rdata[File_ptr] + (File_Rdata[File_ptr+1] << 8) + (File_Rdata[File_ptr+2] << 16) + (File_Rdata[File_ptr+3] << 24);
$display("p_filesz: 0x%x", p_filesz);
File_ptr = File_ptr + 4;
elf_param = File_Rdata[File_ptr] + (File_Rdata[File_ptr+1] << 8) + (File_Rdata[File_ptr+2] << 16) + (File_Rdata[File_ptr+3] << 24);
$display("p_memsz: 0x%x", elf_param);
File_ptr = File_ptr + 4;
elf_param = File_Rdata[File_ptr] + (File_Rdata[File_ptr+1] << 8) + (File_Rdata[File_ptr+2] << 16) + (File_Rdata[File_ptr+3] << 24);
$display("p_flags: 0x%x", elf_param);
File_ptr = File_ptr + 4;
elf_param = File_Rdata[File_ptr] + (File_Rdata[File_ptr+1] << 8) + (File_Rdata[File_ptr+2] << 16) + (File_Rdata[File_ptr+3] << 24);
$display("p_align: 0x%x", elf_param);
File_ptr = File_ptr + 4;
// loading segment to memory
bytes_in_word = dat_width / 8;
for (load_byte_counter = 0; load_byte_counter < p_filesz; load_byte_counter = load_byte_counter + bytes_in_word)
begin
wrword = 0;
for (wrword_byte_counter = 0; wrword_byte_counter < bytes_in_word; wrword_byte_counter = wrword_byte_counter + 1)
begin
wrword = {File_Rdata[p_offset + load_byte_counter + wrword_byte_counter], wrword[dat_width-1:8]};
end
ram_ptr = (p_vaddr + load_byte_counter) / bytes_in_word;
ram[ram_ptr] = wrword;
end
end
$display("##################################\n");
$fclose(File_ID);
end
else $fatal("init_type parameter incorrect!");
end
end
endmodule // ram
|
#include <bits/stdc++.h> using namespace std; int n; vector<int> tree[300003]; int colors[300003]; int blueC[300003]; int redC[300003]; int ans = 0; pair<int, int> dfs(int nd, int pr) { int blue = (colors[nd] == 2); int red = (colors[nd] == 1); for (int i = 0; i < (int)tree[nd].size(); i++) { if (tree[nd][i] == pr) continue; pair<int, int> sub = dfs(tree[nd][i], nd); if ((bool)sub.first ^ (bool)sub.second) { if (sub.first) ans += (blueC[0] == sub.first); else ans += (redC[0] == sub.second); } blue += sub.first; red += sub.second; } return make_pair(blue, red); } void solve() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &colors[i]); int u, v; for (int i = 1; i < n; i++) { scanf( %d %d , &u, &v); tree[u].push_back(v); tree[v].push_back(u); } memset(blueC, 0, sizeof(blueC)); memset(redC, 0, sizeof(redC)); for (int i = 1; i <= n; i++) { if (colors[i] == 1) redC[0]++; else if (colors[i] == 2) blueC[0]++; } dfs(1, 0); printf( %d , ans); } int main() { solve(); } |
module Wait (reset, clk, clk_2, check, PossibleStart, WriteChar);
input clk;
input PossibleStart;
input WriteChar;
input reset;
output reg clk_2;
output reg check;
parameter period = 10416;
parameter n =14;
parameter halfPeriod = period/2;
reg [n:0] counter;
parameter period1 = 2;
parameter n1 =1;
parameter halfPeriod1 = period1/2;
reg [n1:0] counter1;
reg [1:0] current_state;
reg [1:0] next_state;
parameter IDLE = 2'b00;
parameter POSSIBLESTART = 2'b01;
parameter READ = 2'b10;
parameter PARITY = 2'b11;
always @(posedge clk or posedge reset) begin
if (reset == 1'b1) begin
counter = 0;
counter1 = 0;
clk_2=0;
check = 0;
next_state <= 2'b00;
end
else begin
case (current_state)
IDLE: begin
if (PossibleStart==0)
next_state<=IDLE;
else begin
next_state<=POSSIBLESTART;
clk_2=0;
end
if (WriteChar==1)
next_state<=READ;
check=0;
counter=0;
if (counter1 == period1-1) begin
counter1 = 0;
clk_2 = 1;
end
else counter1 = counter1 +1'b1;
if (counter1 == halfPeriod1) clk_2 =0;
end // case: IDLE
POSSIBLESTART: begin
if (WriteChar==1) begin
next_state<=READ;
clk_2=1;
counter = 0;
end
if (WriteChar==0 && check==1)
next_state<=IDLE;
if (WriteChar==0 && check==0)
next_state<=POSSIBLESTART;
if (counter == halfPeriod-1) begin
counter=0;
check=1;
clk_2=1;
end
else
counter = counter +1'b1;
if (counter1 == period1-1) begin
counter1 = 0;
clk_2 = 1;
end
else counter1 = counter1 +1'b1;
if (counter1 == halfPeriod1) clk_2 =0;
end // case: POSSIBLESTART
READ: begin
if (WriteChar==1)
next_state<=READ;
else begin
next_state<=PARITY;
clk_2 = 0;
end
check=0;
if (counter == period-1) begin
counter = 0;
clk_2 = 1;
end
else counter = counter +1'b1;
if (counter == halfPeriod) clk_2 =0;
end // case: READ
PARITY: begin
if (clk_2==1)
next_state<= IDLE;
else
next_state<=PARITY;
if (counter == period-1) begin
counter = 0;
clk_2 = 1;
end
else counter = counter +1'b1;
if (counter == halfPeriod) clk_2 =0;
end // case: PARITY
default: begin
next_state<=IDLE;
check=0;
clk_2=0;
end
endcase // case (current_state)
end // else: !if(reset == 1'b1)
end // always @ (posedge clk)
always @(negedge clk or posedge reset) begin
if (reset == 1'b1)
current_state<=IDLE;
else
current_state<=next_state;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void __print(int x) { cerr << x; } void __print(long x) { cerr << x; } void __print(long long x) { cerr << x; } void __print(unsigned x) { cerr << x; } void __print(unsigned long x) { cerr << x; } void __print(unsigned long long x) { cerr << x; } void __print(float x) { cerr << x; } void __print(double x) { cerr << x; } void __print(long double x) { cerr << x; } void __print(char x) { cerr << << x << ; } void __print(const char *x) { cerr << << x << ; } void __print(const string &x) { cerr << << x << ; } void __print(bool x) { cerr << (x ? true : false ); } template <typename T, typename V> void __print(const pair<T, V> &x) { cerr << { ; __print(x.first); cerr << , ; __print(x.second); cerr << } ; } template <typename T> void __print(const T &x) { int f = 0; cerr << { ; for (auto &i : x) cerr << (f++ ? , : ), __print(i); cerr << } ; } void _print() { cerr << ] n ; } template <typename T, typename... V> void _print(T t, V... v) { __print(t); if (sizeof...(v)) cerr << , ; _print(v...); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int n; cin >> n; vector<long long int> array1, array2; for (long long int i = 0; i < n; i++) { long long int p; cin >> p; array1.push_back(p); array2.push_back(p); } sort(array2.begin(), array2.end()); long long int count = 0; for (long long int i = 0; i < n; i++) { if (array1[i] != array2[i]) { count++; } } if (count == 0 || count == 2) { cout << YES << endl; } else { cout << NO << endl; } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFRTN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__SDFRTN_FUNCTIONAL_PP_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hdll__udp_mux_2to1.v"
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hdll__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hdll__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intclk , CLK_N );
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hdll__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, intclk, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFRTN_FUNCTIONAL_PP_V |
// NeoGeo logic definition (simulation only)
// Copyright (C) 2018 Sean Gonsalves
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
`timescale 1ns/1ns
// SIMULATION - UNUSED
// Latches and buffers on the 68K bus for joypad I/Os
// 273s and 245s on the verification board
// Signals: nCTRL1ZONE, nCTRL2ZONE, nSTATUSBZONE, nBITWD0, (memcard nWP, nCD2, nCD1), SYSTEM_MODE
module joy_io(
input nCTRL1ZONE,
input nCTRL2ZONE,
input nSTATUSBZONE,
inout [15:0] M68K_DATA,
input M68K_ADDR_A4,
input [9:0] P1_IN,
input [9:0] P2_IN,
input nBITWD0,
input nWP, nCD2, nCD1,
input SYSTEM_MODE,
output reg [2:0] P1_OUT,
output reg [2:0] P2_OUT
);
always @(negedge nBITWD0)
begin
// REG_POUTPUT
if (!M68K_ADDR_A4) {P2_OUT, P1_OUT} <= M68K_DATA[5:0];
end
// REG_P1CNT
assign M68K_DATA[15:8] = nCTRL1ZONE ? 8'bzzzzzzzz : P1_IN[7:0];
// REG_P2CNT
assign M68K_DATA[15:8] = nCTRL2ZONE ? 8'bzzzzzzzz : P2_IN[7:0];
// REG_STATUS_B
assign M68K_DATA[15:8] = nSTATUSBZONE ? 8'bzzzzzzzz : {SYSTEM_MODE, nWP, nCD2, nCD1, P2_IN[9:8], P1_IN[9:8]};
endmodule
|
`timescale 1ns / 1ps
module MaquinaEstados(
clk, //Clock de la maquina de estados
reset, //Reset de la maquina de estados
state, //para la maquina de estados
accion, //00:reposo,01:llegado a destino,10:subir, 11:bajar
sensor_puerta, //Indicador de puerta atascada (1: atascado, 0 libre)
sensor_sobrepeso, //Indicador de sobrepeso (1: si hay, 0 no hay)
t_expired,
restart_timer, //reinicia el timer
start_timer, //inicia el timer
//Se;al que habilitan el verificador de movimiento
habilita_verificador,
inicia_Registro_Solicitudes,
//A continuacin los leds que se estrn activando y desactivando
subiendo_LED,
bajando_LED,
freno_act_LED,
motor_act_LED,
puerta_abierta_LED,
puerta_cerrada_LED,
sensor_puerta_LED,
sensor_sobrepeso_LED,
//Se;al de finalizaci'on
ready
);
input wire clk, reset;
input wire [1:0] accion;
input sensor_puerta, sensor_sobrepeso, t_expired;
output reg restart_timer, start_timer, ready, habilita_verificador, inicia_Registro_Solicitudes;
output reg subiendo_LED,
bajando_LED,
freno_act_LED,
motor_act_LED,
puerta_abierta_LED,
puerta_cerrada_LED,
sensor_puerta_LED,
sensor_sobrepeso_LED;
output [1:0] state;
reg[3:0] state, nextState;
parameter inicio=4'd0;
parameter reposo = 4'd1;
parameter movimiento = 4'd2;
parameter detener = 4'd3;
parameter abre_puerta = 4'd4;
parameter inicia_conteo = 4'd5;
parameter revisa_seguridad = 4'd6;
parameter dispara_alerta = 4'd7;
parameter reinicia_conteo = 4'd8;
parameter cierra_puerta = 4'd9;
//Asignacin sincrona del siguiente estado
always @(posedge clk or posedge reset)
if (reset)
state <= inicio;
else
state <= nextState;
always @(state or accion) begin
nextState=4'bxxxx;
case (state)
inicio:
begin
habilita_verificador=1'b1;
inicia_Registro_Solicitudes=1'b1;
nextState = reposo;
end
reposo:
begin
freno_act_LED = 1'b1;
puerta_abierta_LED = 1'b0;
puerta_cerrada_LED = 1'b1;
motor_act_LED = 1'b0;
if (accion == 2'b00) begin
nextState = reposo;
end
else if (accion == 2'b10 || accion == 2'b11) begin
nextState = movimiento;
end
else if (accion == 2'b01) begin
nextState = abre_puerta;
end
end
movimiento:
begin
freno_act_LED = 1'b0;
motor_act_LED = 1'b1;
if (accion == 2'b10) begin
subiendo_LED = 1'b1;
bajando_LED = 1'b0;
//Agregar se activa el 7seg subiendo
nextState = movimiento;
end
else if (accion == 2'b11) begin
subiendo_LED = 1'b0;
bajando_LED = 1'b1;
//Agregar se activa el 7 seg bajando
nextState = movimiento;
end
else if (accion == 2'b01)
begin
nextState = detener;
end
end
detener:
begin
freno_act_LED = 1'b1;
motor_act_LED = 1'b0;
nextState = abre_puerta;
end
abre_puerta:
begin
puerta_abierta_LED = 1'b1;
puerta_cerrada_LED = 1'b0;
ready= 1'b1;
if (accion == 2'b10 || accion == 2'b11)
begin
nextState = inicia_conteo;
end
else if (accion == 2'b00)
begin
nextState = reposo;
end
end
inicia_conteo:
begin
start_timer = 1'b1;
nextState = revisa_seguridad;
end
revisa_seguridad:
begin
if (!(sensor_puerta) & !(sensor_sobrepeso) & !(t_expired))
begin
nextState = revisa_seguridad;
end
else if (sensor_sobrepeso | sensor_puerta & !(t_expired))
begin
nextState = dispara_alerta;
end
else if (t_expired)
begin
nextState = cierra_puerta;
end
end
dispara_alerta:
begin
if (sensor_sobrepeso)
begin
sensor_sobrepeso_LED = 1'b1;
end
if (sensor_puerta)
begin
sensor_puerta_LED = 1'b1;
end
nextState = reinicia_conteo;
end
reinicia_conteo:
begin
restart_timer = 1'b1;
nextState = revisa_seguridad;
end
cierra_puerta:
begin
puerta_abierta_LED = 1'b0;
puerta_cerrada_LED = 1'b1;
nextState = movimiento;
end
default: nextState = reposo;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int t, n; int main() { cin >> n >> t; long long int k = 0; long long int a, b; long long int res1 = 1; long long int res; cin >> a >> b; long long int m = (t - a) / b; if (a >= t) res = a; else if (m * b + a == t) res = t; else res = (m + 1) * b + a; for (int i = 1; i < n; i++) { cin >> a >> b; m = (t - a) / b; if (a >= t) { if (a < res) { res = a; res1 = i + 1; } } else if (m * b + a == t) { res = t; res1 = i + 1; } else if ((m + 1) * b + a < res) { res = (m + 1) * b + a; res1 = i + 1; } } cout << res1; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFSTP_1_V
`define SKY130_FD_SC_HS__SDFSTP_1_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfstp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__sdfstp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sdfstp_1 (
CLK ,
D ,
Q ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND
);
input CLK ;
input D ;
output Q ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__sdfstp base (
.CLK(CLK),
.D(D),
.Q(Q),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sdfstp_1 (
CLK ,
D ,
Q ,
SCD ,
SCE ,
SET_B
);
input CLK ;
input D ;
output Q ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__sdfstp base (
.CLK(CLK),
.D(D),
.Q(Q),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFSTP_1_V
|
#include <bits/stdc++.h> using namespace std; int n, a[100005], top, s[100005]; int main() { ios_base::sync_with_stdio(0); cin.tie(); cout.tie(); cin >> n; for (int i = 0; i < n; ++i) cin >> a[i]; top = -1; for (int i = n - 1; i >= 0; --i) { s[++top] = a[i]; while (top > 0 && s[top] == s[top - 1]) ++s[--top]; } cout << s[0] - top; return 0; } |
#include <bits/stdc++.h> using namespace std; using namespace std::chrono; void pr_init() {} void solve() { string str[2]; cin >> str[0] >> str[1]; long long ss = (long long)str[0].size(); long long dp[2][ss + 1]; for (long long i = 0; i < 2; i++) { for (long long j = 0; j < ss; j++) { if (str[i][j] == X ) dp[i][j] = 0; else dp[i][j] = 1; } } dp[0][ss] = dp[1][ss] = 0; long long ways = 0; for (long long j = 0; j < ss; j++) { if (dp[0][j] == 1 && dp[1][j] == 1) { if (dp[0][j + 1] == 1) ways++, dp[0][j + 1] = 0; else if (dp[1][j + 1] == 1) ways++, dp[1][j + 1] = 0; continue; } else if (dp[0][j] == 1) { if (dp[0][j + 1] == 1 && dp[1][j + 1] == 1) ways++, dp[0][j + 1] = 0, dp[1][j + 1] = 0; continue; } else if (dp[1][j] == 1) { if (dp[0][j + 1] == 1 && dp[1][j + 1] == 1) ways++, dp[0][j + 1] = 0, dp[1][j + 1] = 0; continue; } } cout << ways << endl; } int32_t main() { pr_init(); ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); solve(); } |
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: ram.v
//
// *Module Description:
// Scalable Dual-Port RAM model
//
// *Author(s):
// - Olivier Girard,
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
module ram_dp (
// OUTPUTs
ram_douta, // RAM data output (Port A)
ram_doutb, // RAM data output (Port B)
// INPUTs
ram_addra, // RAM address (Port A)
ram_cena, // RAM chip enable (low active) (Port A)
ram_clka, // RAM clock (Port A)
ram_dina, // RAM data input (Port A)
ram_wena, // RAM write enable (low active) (Port A)
ram_addrb, // RAM address (Port B)
ram_cenb, // RAM chip enable (low active) (Port B)
ram_clkb, // RAM clock (Port B)
ram_dinb, // RAM data input (Port B)
ram_wenb // RAM write enable (low active) (Port B)
);
// PARAMETERs
//============
parameter ADDR_MSB = 6; // MSB of the address bus
parameter MEM_SIZE = 256; // Memory size in bytes
// OUTPUTs
//============
output [15:0] ram_douta; // RAM data output (Port A)
output [15:0] ram_doutb; // RAM data output (Port B)
// INPUTs
//============
input [ADDR_MSB:0] ram_addra; // RAM address (Port A)
input ram_cena; // RAM chip enable (low active) (Port A)
input ram_clka; // RAM clock (Port A)
input [15:0] ram_dina; // RAM data input (Port A)
input [1:0] ram_wena; // RAM write enable (low active) (Port A)
input [ADDR_MSB:0] ram_addrb; // RAM address (Port B)
input ram_cenb; // RAM chip enable (low active) (Port B)
input ram_clkb; // RAM clock (Port B)
input [15:0] ram_dinb; // RAM data input (Port B)
input [1:0] ram_wenb; // RAM write enable (low active) (Port B)
// RAM
//============
reg [15:0] mem [0:(MEM_SIZE/2)-1];
reg [ADDR_MSB:0] ram_addra_reg;
reg [ADDR_MSB:0] ram_addrb_reg;
wire [15:0] mem_vala = mem[ram_addra];
wire [15:0] mem_valb = mem[ram_addrb];
always @(posedge ram_clka)
if (~ram_cena && (ram_addra<(MEM_SIZE/2)))
begin
if (ram_wena==2'b00) mem[ram_addra] <= ram_dina;
else if (ram_wena==2'b01) mem[ram_addra] <= {ram_dina[15:8], mem_vala[7:0]};
else if (ram_wena==2'b10) mem[ram_addra] <= {mem_vala[15:8], ram_dina[7:0]};
ram_addra_reg <= ram_addra;
end
assign ram_douta = mem[ram_addra_reg];
always @(posedge ram_clkb)
if (~ram_cenb && (ram_addrb<(MEM_SIZE/2)))
begin
if (ram_wenb==2'b00) mem[ram_addrb] <= ram_dinb;
else if (ram_wenb==2'b01) mem[ram_addrb] <= {ram_dinb[15:8], mem_valb[7:0]};
else if (ram_wenb==2'b10) mem[ram_addrb] <= {mem_valb[15:8], ram_dinb[7:0]};
ram_addrb_reg <= ram_addrb;
end
assign ram_doutb = mem[ram_addrb_reg];
endmodule // ram_dp
|
// /**
// * This Verilog HDL file is used for simulation and synthesis in
// * the chaining DMA design example. It could be used by the software
// * application (Root Port) to retrieve the DMA Performance counter values
// * and performs single DWORD read and write to the Endpoint memory by
// * bypassing the DMA engines.
// */
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// synthesis verilog_input_version verilog_2001
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
//
// Copyright (c) 2009 Altera Corporation. All rights reserved. Altera products are
// protected under numerous U.S. and foreign patents, maskwork rights, copyrights and
// other intellectual property laws.
//
// This reference design file, and your use thereof, is subject to and governed by
// the terms and conditions of the applicable Altera Reference Design License Agreement.
// By using this reference design file, you indicate your acceptance of such terms and
// conditions between you and Altera Corporation. In the event that you do not agree with
// such terms and conditions, you may not use the reference design file. Please promptly
// destroy any copies you have made.
//
// This reference design file being provided on an "as-is" basis and as an accommodation
// and therefore all warranties, representations or guarantees of any kind
// (whether express, implied or statutory) including, without limitation, warranties of
// merchantability, non-infringement, or fitness for a particular purpose, are
// specifically disclaimed. By making this reference design file available, Altera
// expressly does not recommend, suggest or require that this reference design file be
// used in combination with any other product not provided by Altera.
//-----------------------------------------------------------------------------
module altpcierd_cdma_ecrc_gen #( parameter AVALON_ST_128 = 0)
(clk, rstn, user_rd_req, user_sop, user_eop, user_data, user_valid,
tx_stream_ready0, tx_stream_data0_0, tx_stream_data0_1, tx_stream_valid0);
input clk;
input rstn;
// user data (avalon-st formatted)
output user_rd_req; // request for next user_data
input user_sop; // means this cycle contains the start of a packet
input[1:0] user_eop; // means this cycle contains the end of a packet
input[127:0] user_data; // avalon streaming packet data
input user_valid; // means user_sop, user_eop, user_data are valid
input tx_stream_ready0;
output[75:0] tx_stream_data0_0;
output[75:0] tx_stream_data0_1;
output tx_stream_valid0;
reg[75:0] tx_stream_data0_0;
reg[75:0] tx_stream_data0_1;
reg tx_stream_valid0;
wire [127:0] crc_data;
wire crc_sop;
wire crc_eop;
wire crc_valid;
wire[3:0] crc_empty;
wire [127:0] tx_data;
wire tx_sop;
wire [1:0] tx_eop;
wire tx_valid;
wire tx_shift;
wire[3:0] tx_crc_location;
wire[31:0] ecrc;
wire[31:0] ecrc_reversed;
wire[135:0] tx_data_vec;
wire[135:0] tx_data_vec_del;
wire[127:0] tx_data_output;
wire tx_sop_output;
wire[1:0] tx_eop_output;
wire[3:0] tx_crc_location_output;
reg[31:0] ecrc_rev_hold;
wire crc_ack;
wire tx_data_vec_del_valid;
wire tx_datapath_full;
wire tx_digest;
reg tx_digest_reg;
generate begin: tx_ecrc_128
if (AVALON_ST_128==1) begin
altpcierd_cdma_ecrc_gen_ctl_128 ecrc_gen_ctl_128 (
.clk(clk), .rstn(rstn), .user_rd_req(user_rd_req), .user_sop(user_sop),
.user_eop(user_eop), .user_data(user_data), .user_valid(user_valid),
.crc_empty(crc_empty), .crc_sop(crc_sop), .crc_eop(crc_eop), .crc_data(crc_data),
.crc_valid(crc_valid),
.tx_sop(tx_sop), .tx_eop(tx_eop),
.tx_data(tx_data), .tx_valid(tx_valid), .tx_crc_location(tx_crc_location), .tx_shift(tx_shift),
.av_st_ready(~tx_datapath_full)
);
end
end
endgenerate
generate begin: tx_ecrc_64
if (AVALON_ST_128==0) begin
altpcierd_cdma_ecrc_gen_ctl_64 ecrc_gen_ctl_64 (
.clk(clk), .rstn(rstn), .user_rd_req(user_rd_req), .user_sop(user_sop),
.user_eop(user_eop), .user_data(user_data), .user_valid(user_valid),
.crc_empty(crc_empty), .crc_sop(crc_sop), .crc_eop(crc_eop), .crc_data(crc_data),
.crc_valid(crc_valid),
.tx_sop(tx_sop), .tx_eop(tx_eop),
.tx_data(tx_data), .tx_valid(tx_valid), .tx_crc_location(tx_crc_location), .tx_shift(tx_shift),
.av_st_ready(~tx_datapath_full)
);
end
end
endgenerate
altpcierd_cdma_ecrc_gen_calc #(.AVALON_ST_128(AVALON_ST_128)) ecrc_gen_calc (
.clk(clk), .rstn(rstn), .crc_data(crc_data), .crc_valid(crc_valid),
.crc_empty(crc_empty), .crc_eop(crc_eop), .crc_sop(crc_sop),
.ecrc(ecrc), .crc_ack(crc_ack)
);
// input to tx_datapath delay_stage
assign tx_data_vec = {tx_valid, tx_crc_location, tx_sop, tx_eop, tx_data};
altpcierd_cdma_ecrc_gen_datapath ecrc_gen_datapath (
.clk(clk), .rstn(rstn), .data_in(tx_data_vec), .data_valid(tx_valid),
.rdreq (tx_stream_ready0), .data_out(tx_data_vec_del), .data_out_valid(tx_data_vec_del_valid),
.full(tx_datapath_full)
);
// output from tx_datapath delay_stage
assign tx_crc_location_output = tx_data_vec_del[134:131];
assign tx_sop_output = tx_data_vec_del[130];
assign tx_eop_output = tx_data_vec_del[129:128];
assign tx_data_output = tx_data_vec_del[127:0];
assign crc_ack = (tx_digest==1'b1) ? (|tx_data_vec_del[134:131] & tx_data_vec_del_valid) :
(|tx_data_vec_del[129:128] & tx_data_vec_del_valid) ; // OPTIMIZE THIS LATER
assign ecrc_reversed = { ecrc[0], ecrc[1], ecrc[2], ecrc[3], ecrc[4], ecrc[5], ecrc[6], ecrc[7],
ecrc[8], ecrc[9], ecrc[10], ecrc[11], ecrc[12], ecrc[13], ecrc[14], ecrc[15],
ecrc[16], ecrc[17], ecrc[18], ecrc[19], ecrc[20], ecrc[21], ecrc[22], ecrc[23],
ecrc[24], ecrc[25], ecrc[26], ecrc[27], ecrc[28], ecrc[29], ecrc[30], ecrc[31]
};
/*****************************************
STREAMING DATA OUTPUT MUX
******************************************/
assign tx_digest = (tx_sop_output==1'b1) ? tx_data_output[111] : tx_digest_reg; // pkt has ecrc
always @ (posedge clk or negedge rstn) begin
if (rstn==1'b0) begin
tx_stream_data0_0 <= 76'h0;
tx_stream_data0_1 <= 76'h0;
tx_stream_valid0 <= 1'b0;
tx_digest_reg <= 1'b0;
end
else begin
tx_digest_reg <= tx_digest;
tx_stream_data0_0[75:74] <= 2'h0;
tx_stream_data0_0[71:64] <= 8'h0;
tx_stream_data0_1[75:74] <= 2'h0;
tx_stream_data0_1[71:64] <= 8'h0;
if (tx_digest==1'b1) begin
tx_stream_data0_1[31:0] <= (tx_crc_location_output[3]==1'b1) ? ecrc_reversed : tx_data_output[31:0];
tx_stream_data0_1[63:32] <= (tx_crc_location_output[2]==1'b1) ? ecrc_reversed : tx_data_output[63:32];
tx_stream_data0_0[31:0] <= (tx_crc_location_output[1]==1'b1) ? ecrc_reversed : tx_data_output[95:64];
tx_stream_data0_0[63:32] <= (tx_crc_location_output[0]==1'b1) ? ecrc_reversed : tx_data_output[127:96];
tx_stream_data0_1[73] <= (tx_crc_location_output[3:0]!=4'b0000); // eop occurs in this cycle
tx_stream_data0_1[72] <= tx_sop_output; // sop
tx_stream_data0_0[72] <= tx_sop_output; // sop
tx_stream_data0_0[73] <= (tx_crc_location_output[1:0]!=2'b00); // lower half is empty when crc is in the first 2 locations
tx_stream_valid0 <= tx_data_vec_del_valid;
end
else begin
tx_stream_data0_1[31:0] <= tx_data_output[31:0];
tx_stream_data0_1[63:32] <= tx_data_output[63:32];
tx_stream_data0_0[31:0] <= tx_data_output[95:64];
tx_stream_data0_0[63:32] <= tx_data_output[127:96];
tx_stream_data0_1[73] <= tx_eop_output[1]; // eop occurs in this cycle
tx_stream_data0_1[72] <= tx_sop_output; // sop
tx_stream_data0_0[72] <= tx_sop_output; // sop
tx_stream_data0_0[73] <= tx_eop_output[0];
tx_stream_valid0 <= (tx_data_vec_del_valid==1'b1) ? 1'b1 : 1'b0;
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYBUF4S50KAPWR_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__DLYBUF4S50KAPWR_FUNCTIONAL_PP_V
/**
* dlybuf4s50kapwr: Delay Buffer 4-stage 0.50um length inner stage
* gates on keep-alive power rail.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__dlybuf4s50kapwr (
X ,
A ,
VPWR ,
VGND ,
KAPWR,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR ;
input VGND ;
input KAPWR;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, KAPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYBUF4S50KAPWR_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int N = 500010; long long x, y, m; int main() { ios_base::sync_with_stdio(false); cin >> x >> y >> m; if (x >= m || y >= m) { cout << 0 n ; return 0; } if (x <= 0 && y <= 0) { cout << -1 n ; return 0; } if (x > y) swap(x, y); long long res = 0; if (x < 0) { res = ceil(-x * 1.0 / y); x += res * y; } while (x < m && y < m) { if (x < y) x = x + y; else y = x + y; res++; } cout << res << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int op, d; int main() { int nc = 0, bst = 0; ; for (cin >> op >> d; d--;) { string s; cin >> s; int c = 0; for (int i = 0; i < s.size(); ++i) if (s[i] == 1 ) ++c; if (c == op) nc = 0; else ++nc; bst = max(nc, bst); } cout << bst; } |
#include <bits/stdc++.h> using namespace std; int pow_mod(int a, long long k, int mod) { if (k == 0) { return 1; } int sub = pow_mod(a, k / 2, mod); if (k % 2 == 0) { return ((long long)sub * sub) % mod; } else { return (((long long)sub * sub) % mod * a) % mod; } } int main() { int h, i, j, l; int t, n, m, k, q; int r, c; scanf( %d %d %d %d %d , &n, &m, &k, &r, &c); int ax, ay, bx, by; scanf( %d %d %d %d , &ax, &ay, &bx, &by); long long count; long long mod = 1e9 + 7; if (ax == bx && ay == by) { count = (long long)n * m; } else { count = (long long)n * m - (long long)r * c; } printf( %d n , pow_mod(k, count, mod)); } |
module top
(
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
parameter PRESCALER = 4; //100000;
// UART loopback + switches to avoid unused inputs
assign tx = rx || (|sw);
// ============================================================================
// Reset
reg [3:0] rst_sr;
wire rst;
initial rst_sr <= 4'hF;
always @(posedge clk)
if (sw[0]) rst_sr <= 4'hF;
else rst_sr <= rst_sr >> 1;
assign rst = rst_sr[0];
// ============================================================================
// Clock prescaler
reg [32:0] ps_cnt = 0;
wire ps_tick = ps_cnt[32];
always @(posedge clk)
if (rst || ps_tick)
ps_cnt <= PRESCALER - 2;
else
ps_cnt <= ps_cnt - 1;
// ============================================================================
// SRL chain testers
wire sim_error = sw[2];
wire [7:0] srl_q;
wire [7:0] error;
genvar i;
generate for(i=0; i<8; i=i+1) begin
localparam j = (i % 4);
wire srl_d;
wire srl_sh;
localparam SITE = (i==0) ? "SLICE_X2Y100" :
(i==1) ? "SLICE_X2Y101" :
(i==2) ? "SLICE_X2Y102" :
(i==3) ? "SLICE_X2Y103" :
(i==4) ? "SLICE_X2Y104" :
(i==5) ? "SLICE_X2Y105" :
(i==6) ? "SLICE_X2Y106" :
/*(i==7) ?*/ "SLICE_X2Y107";
srl_shift_tester #
(
.SRL_LENGTH ((j==0) ? 32 : (16 + j*32)),
.FIXED_DELAY ((j==0) ? 32 : (16 + j*32))
)
tester
(
.clk (clk),
.rst (rst),
.ce (ps_tick),
.srl_sh (srl_sh),
.srl_d (srl_d),
.srl_q (srl_q[i] ^ sim_error),
.error (error[i])
);
srl_chain_mixed #
(
.BEGIN_WITH_SRL16 ((j==0) || (i>=8)),
.END_WITH_SRL16 ((j==0) || (i< 8)),
.NUM_SRL32 (j),
.SITE (SITE)
)
chain_seg
(
.CLK (clk),
.CE (srl_sh),
.D (srl_d),
.Q (srl_q[i])
);
end endgenerate
// ============================================================================
// Error latch
reg [7:0] error_lat = 0;
always @(posedge clk)
if (rst)
error_lat <= 0;
else
error_lat <= error_lat | error;
// ============================================================================
// LEDs
genvar j;
generate for(j=0; j<8; j=j+1) begin
assign led[j ] = (sw[1]) ? error_lat[j] : error[j];
assign led[j+8] = srl_q[j];
end endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> T sqr(T a) { return (a) * (a); } template <class T> T abs(T a) { return (a < 0) ? -(a) : (a); } const double Pi = acos(-1.0); const double eps = 1e-10; const int INF = 1000 * 1000 * 1000; const double phi = 0.5 + sqrt(1.25); int main() { string Less = z , More = , tmp = ; int n; scanf( %d n , &n); for (int i = 0, _n = (n)-1; i <= _n; ++i) { getline(cin, tmp); Less = min(Less, tmp); More = max(More, tmp); } int i = 0, m = ((int)((Less).size())); bool coincide = 1; while (i < m && coincide) if (Less.substr(0, i + 1) == More.substr(0, i + 1)) i++; else coincide = 0; printf( %d n , i); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, k; int a[15][123]; int b[15][123]; int c[15][123]; vector<int> v; bool cmp(int x, int y) { return x > y; } int main() { cin >> n >> m >> k; for (int i = 0; i < n; i++) { string s; cin >> s; for (int j = 0; j < m; j++) cin >> a[i][j] >> b[i][j] >> c[i][j]; } int ans = 0; for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) { if (i == j) continue; v.clear(); for (int h = 0; h < m; h++) for (int t = 0; t < c[i][h]; t++) if (b[j][h] - a[i][h] > 0) v.push_back(b[j][h] - a[i][h]); sort(v.begin(), v.end(), cmp); int tmp = 0; for (int h = 0; h < min(k, (int)v.size()); h++) tmp += v[h]; ans = max(ans, tmp); } cout << ans << endl; return 0; } |
/*------------------------------------------------------------------------
Purpose
Top module. USB device realization up to transaction level.
------------------------------------------------------------------------*/
module usb_devtrsac (
input clk_4xrate,
input rst0_async,
input rst0_sync,
//USB TRANSCEIVER
input drx_plus,
input drx_minus,
input drx,
output dtx_plus,
output dtx_minus,
output dtx_oe,
//TRANSACTION
output[1:0] trsac_type,
output[3:0] trsac_ep,
output[1:0] trsac_req,
input[1:0] trsac_reply,
//RFIFO
input rfifo_rd,
output rfifo_empty,
output[7:0] rfifo_rdata,
//TFIFO
input tfifo_wr,
output tfifo_full,
input[7:0] tfifo_wdata,
//EP
input[15:1] ep_enable,
input[15:1] ep_isoch,
input[15:1] ep_intnoretry,
//SOF
output sof_tick,
output[10:0] sof_value,
//DEVICE
input device_speed,
input device_wakeup,
input device_addr_wr,
input[6:0] device_addr,
input device_config_wr,
input[7:0] device_config,
output reg[2:0] device_state
);
wire usb_rst;
wire usb_spnd;
wire usb_interpack;
//PACKET
wire[3:0] rdec_epaddr;
wire rdec_pidin;
wire rdec_pidout;
wire rdec_pidsetup;
wire rdec_piddata0;
wire rdec_piddata1;
wire rdec_pidack;
wire rdec_ok;
wire rdec_fail;
//RFIFO
wire rfifo_full;
wire rdec_rfifo_wr;
wire rextr_data;
wire rdec_rfifo_rst0;
//TFIFO
wire tfifo_empty;
wire tfifo_rdata;
//ENCFIFO
wire encfifo_wr;
wire encfifo_wdata;
wire encfifo_full;
//TRSAC
wire trsac_encfifo_wr;
wire trsac_encfifo_wdata;
wire trsac_tfifoenc_en;
wire[15:0] togglebit_rst;
//DEVICE STATE
reg[6:0] devaddr_hold;
reg[7:0] devconf_hold;
localparam DEVICE_POWERED=3'd0,
DEVICE_DEFAULT=3'd1,
DEVICE_ADDRESSED=3'd2,
DEVICE_CONFIGURED=3'd3,
DEVICE_SPND_PWR=3'd4,
DEVICE_SPND_DFT=3'd5,
DEVICE_SPND_ADDR=3'd6,
DEVICE_SPND_CONF=3'd7;
usb_decoder
i_decoder (
.clk(clk_4xrate),
.rst0_async(rst0_async),
.rst0_sync(rst0_sync & !usb_rst),
//USB TRANSCEIVER
.drx_plus(dtx_oe ? device_speed : drx_plus),
.drx_minus(dtx_oe ? ~device_speed : drx_minus),
.drx(dtx_oe ? device_speed : drx),
.dtx_oe(dtx_oe),
//USB LINES STATE
.usb_rst(usb_rst),
.usb_spnd(usb_spnd),
.usb_interpack(usb_interpack),
//PACKET
.dev_addr(devaddr_hold),
.ep_enable({ep_enable,1'b1}),
.rdec_epaddr(rdec_epaddr),
.rdec_pidin(rdec_pidin),
.rdec_pidout(rdec_pidout),
.rdec_pidsetup(rdec_pidsetup),
.rdec_piddata0(rdec_piddata0),
.rdec_piddata1(rdec_piddata1),
.rdec_pidack(rdec_pidack),
.rdec_ok(rdec_ok),
.rdec_fail(rdec_fail),
//SOF
.sof_tick(sof_tick),
.sof_value(sof_value),
//RFIFO
.rfifo_full(rfifo_full),
.rdec_rfifo_wr(rdec_rfifo_wr),
.rextr_data(rextr_data),
.rdec_rfifo_rst0(rdec_rfifo_rst0),
.speed(device_speed)
);
usb_encoder
i_encoder (
.clk(clk_4xrate),
.rst0_async(rst0_async),
.rst0_sync(rst0_sync & !usb_rst),
//USB
.dtx_plus(dtx_plus),
.dtx_minus(dtx_minus),
.dtx_oe(dtx_oe),
//DECODER
.usb_interpack(usb_interpack),
//ENCFIFO
.encfifo_wr(trsac_encfifo_wr),
.encfifo_wdata(encfifo_wdata),
.encfifo_full(encfifo_full),
.remote_wakeup(device_wakeup & device_state[2]),
.speed(device_speed)
);
usb_trsacner
i_trsacner (
.clk(clk_4xrate),
.rst0_async(rst0_async),
.rst0_sync(rst0_sync & !usb_rst),
//DECODER
.rdec_epaddr(rdec_epaddr),
.rdec_pidin(rdec_pidin),
.rdec_pidout(rdec_pidout),
.rdec_pidsetup(rdec_pidsetup),
.rdec_piddata0(rdec_piddata0),
.rdec_piddata1(rdec_piddata1),
.rdec_pidack(rdec_pidack),
.rdec_ok(rdec_ok),
.rdec_fail(rdec_fail),
//ENCODER
.encfifo_full(encfifo_full),
.dtx_oe(dtx_oe),
.trsac_encfifo_wr(trsac_encfifo_wr),
.trsac_encfifo_wdata(trsac_encfifo_wdata),
.trsac_tfifoenc_en(trsac_tfifoenc_en),
//TFIFO
.tfifo_empty(tfifo_empty),
.tfifo_rdata(tfifo_rdata),
//TRSAC
.trsac_reply(trsac_reply),
.trsac_req(trsac_req),
.trsac_type(trsac_type),
.trsac_ep(trsac_ep),
.ep_isoch({ep_isoch,1'b0}),
.ep_intnoretry({ep_intnoretry,1'b0}),
.togglebit_rst(~ep_enable[15:1]),
.device_state(device_state)
);
usb_fifo_rcv #(.ADDR_WIDTH(3'd5),.WDATA_WIDTH(1'd0),.RDATA_WIDTH(2'd3))
i_rfifo
(
.clk(clk_4xrate),
.rst0_async(rst0_async),
.rst0_sync(rdec_rfifo_rst0 & !usb_rst),
.wr_en(rdec_rfifo_wr),
.wr_data(rextr_data),
.rd_en(rfifo_rd),
.rd_data(rfifo_rdata),
.fifo_full(rfifo_full),
.fifo_empty(rfifo_empty)
);
usb_fifo_sync #(.ADDR_WIDTH(3'd4),.WDATA_WIDTH(2'd3),.RDATA_WIDTH(1'd0))
i_tfifo
(
.clk(clk_4xrate),
.rst0_async(rst0_async),
.rst0_sync(!usb_rst),
.wr_en(tfifo_wr),
.wr_data(tfifo_wdata),
.rd_en( trsac_encfifo_wr & !encfifo_full &
trsac_tfifoenc_en),
.rd_data(tfifo_rdata),
.fifo_full(tfifo_full),
.fifo_empty(tfifo_empty)
);
assign encfifo_wdata= trsac_tfifoenc_en ? tfifo_rdata :
trsac_encfifo_wdata;
//DEVICE STATE
always @(posedge clk_4xrate, negedge rst0_async)
begin
if(!rst0_async)
begin
devaddr_hold<=7'd0;
devconf_hold<=8'd0;
device_state<=DEVICE_POWERED;
end
else if(!rst0_sync)
begin
devaddr_hold<=7'd0;
devconf_hold<=8'd0;
device_state<=DEVICE_POWERED;
end
else
begin
devaddr_hold<= usb_rst ? 7'd0 :
device_addr_wr ? device_addr :
devaddr_hold;
devconf_hold<= usb_rst ? 8'd0 :
device_config_wr ? device_config :
devconf_hold;
case(device_state)
DEVICE_POWERED:
begin
device_state<= usb_rst ? DEVICE_DEFAULT :
usb_spnd ? DEVICE_SPND_PWR :
device_state;
end
DEVICE_DEFAULT:
begin
device_state<= devaddr_hold!=0 ? DEVICE_ADDRESSED :
usb_spnd ? DEVICE_SPND_DFT :
device_state;
end
DEVICE_ADDRESSED:
begin
device_state<= usb_rst | devaddr_hold==7'd0 ? DEVICE_DEFAULT :
devconf_hold!=0 ? DEVICE_CONFIGURED :
usb_spnd ? DEVICE_SPND_ADDR :
device_state;
end
DEVICE_CONFIGURED:
begin
device_state<= usb_rst ? DEVICE_DEFAULT :
usb_spnd ? DEVICE_SPND_CONF :
devconf_hold==8'd0 ? DEVICE_ADDRESSED :
device_state;
end
DEVICE_SPND_PWR:
begin
device_state<= !usb_spnd ? DEVICE_POWERED : device_state;
end
DEVICE_SPND_DFT:
begin
device_state<= !usb_spnd ? DEVICE_DEFAULT : device_state;
end
DEVICE_SPND_ADDR:
begin
device_state<= !usb_spnd ? DEVICE_ADDRESSED : device_state;
end
DEVICE_SPND_CONF:
begin
device_state<= !usb_spnd ? DEVICE_CONFIGURED : device_state;
end
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFXTP_SYMBOL_V
`define SKY130_FD_SC_HVL__DFXTP_SYMBOL_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__dfxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFXTP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A31OI_2_V
`define SKY130_FD_SC_HDLL__A31OI_2_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog wrapper for a31oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a31oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a31oi_2 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a31oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a31oi_2 (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a31oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A31OI_2_V
|
// Test binary operators in constant functions
module constfunc3();
function [7:0] Add(input [7:0] l, input [7:0] r);
Add = l + r;
endfunction
function [7:0] Mul(input [7:0] l, input [7:0] r);
Mul = l * r;
endfunction
function [7:0] Div(input [7:0] l, input [7:0] r);
Div = l / r;
endfunction
function [7:0] Pow(input [7:0] l, input [7:0] r);
Pow = l ** r;
endfunction
function [7:0] And(input [7:0] l, input [7:0] r);
And = l & r;
endfunction
function [7:0] Shift(input [7:0] l, input [7:0] r);
Shift = l << r;
endfunction
function [7:0] Logic(input [7:0] l, input [7:0] r);
begin
Logic[0] = l[0] && r[0];
Logic[1] = l[1] && r[1];
Logic[2] = l[2] && r[2];
Logic[3] = l[3] && r[3];
Logic[4] = l[4] || r[4];
Logic[5] = l[5] || r[5];
Logic[6] = l[6] || r[6];
Logic[7] = l[7] || r[7];
end
endfunction
localparam [7:0] ResultAdd = Add(8'h0f, 8'h0f);
localparam [7:0] ResultMul = Mul(8'h0f, 8'h0f);
localparam [7:0] ResultDiv = Div(8'hf0, 8'h0f);
localparam [7:0] ResultPow = Pow(8'h02, 8'h05);
localparam [7:0] ResultAnd = And(8'h0f, 8'h55);
localparam [7:0] ResultShift = Shift(8'h55, 8'h03);
localparam [7:0] ResultLogic = Logic(8'h33, 8'h55);
reg failed;
initial begin
failed = 0;
$display("%h", ResultAdd);
$display("%h", ResultMul);
$display("%h", ResultDiv);
$display("%h", ResultPow);
$display("%h", ResultAnd);
$display("%h", ResultShift);
$display("%h", ResultLogic);
if (ResultAdd !== 8'h1e) failed = 1;
if (ResultMul !== 8'he1) failed = 1;
if (ResultDiv !== 8'h10) failed = 1;
if (ResultPow !== 8'h20) failed = 1;
if (ResultAnd !== 8'h05) failed = 1;
if (ResultShift !== 8'ha8) failed = 1;
if (ResultLogic !== 8'h71) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
//deps: alu.v
`timescale 1ns/1ps
`undef assert
`include "cpu_constants.vh"
`define assert(signal, value) \
if (signal !== value) \
$display("ASSERTION FAILED in %m: signal != value"); \
module alu_tb;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [15:0] SP_out; // From alu of alu.v
wire [3:0] flags_out; // From alu of alu.v
wire lr_wr_en; // From alu of alu.v
wire [15:0] mem_data; // From alu of alu.v
wire [15:0] out; // From alu of alu.v
wire should_branch; // From alu of alu.v
wire write; // From alu of alu.v
// End of automatics
/*AUTOREGINPUT*/
// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
reg [7:0] alu_control; // To alu of alu.v
reg clk; // To alu of alu.v
reg [3:0] condition; // To alu of alu.v
reg en; // To alu of alu.v
reg en_imm; // To alu of alu.v
reg [3:0] flags_in; // To alu of alu.v
reg [15:0] immediate; // To alu of alu.v
reg mem_displacement; // To alu of alu.v
reg [15:0] rD_data; // To alu of alu.v
reg [15:0] rS_data; // To alu of alu.v
// End of automatics
alu alu(/*AUTOINST*/
// Outputs
.should_branch (should_branch),
.out (out[15:0]),
.mem_data (mem_data[15:0]),
.write (write),
.flags_out (flags_out[3:0]),
.SP_out (SP_out[15:0]),
.lr_wr_en (lr_wr_en),
// Inputs
.clk (clk),
.en (en),
.alu_control (alu_control[7:0]),
.en_imm (en_imm),
.rD_data (rD_data[15:0]),
.rS_data (rS_data[15:0]),
.immediate (immediate[15:0]),
.condition (condition[3:0]),
.flags_in (flags_in[3:0]),
.mem_displacement (mem_displacement));
initial begin
alu_control <= 0;
clk <= 0;
condition <= 0;
en <= 0;
en_imm <= 0;
flags_in <= 0;
immediate <= 0;
mem_displacement <= 0;
rD_data <= 0;
rS_data <= 0;
$dumpfile("dump.vcd");
$dumpvars;
end
always #5 clk <= ~clk;
initial begin
#20 en <= 1;
rD_data <= 5;
rS_data <= 2;
alu_control <= `OPC_ADD;
en_imm <= 0;
#10 `assert(out, 7)
alu_control <= `OPC_SUB;
#10 `assert(out, 3)
alu_control <= `OPC_MOV;
en_imm <= 1;
immediate <= 16'h001d;
#10 `assert(out,16'h1d)
rD_data <= 16'h7fff;
immediate <= 16'h0001;
alu_control <= `OPC_ADD;
#10 `assert(out, 16'h8000)
rD_data <= 16'h0fa5;
rS_data <= 16'h1d3c;
en_imm <= 0;
alu_control <= `OPC_AND;
#10 `assert(out, 16'h0d24)
alu_control <= `OPC_OR;
#10 `assert(out,16'h1fbd)
alu_control <= `OPC_XOR;
#10 `assert(out,16'h1299)
alu_control <= `OPC_NOT;
#10 `assert(out,'hf05a)
alu_control <= `OPC_SHL;
immediate <= 'h0003;
en_imm <= 1;
#10 `assert(out,'h7d28)
alu_control <= `OPC_SHR;
#10 `assert(out,'h01f4)
alu_control <= `OPC_ROL;
immediate <= 'h0006;
#10 $display("ROL not implemented yet!");
alu_control <= `OPC_ADC;
flags_in[`FLAG_BIT_CARRY] <= 1;
rD_data <= 'h0001;
#10 `assert(out,'h0008)
alu_control <= `OPC_PUSH;
rD_data <= 'h0567;
rS_data <= 'h0100;
en_imm <= 0;
#10 `assert(out, 'h00fe)
`assert(SP_out, 'h00fe)
`assert(mem_data, 'h0567)
#10 en <= 0;
#20 $finish;
end
endmodule // alu_tb
/*AUTOUNDEF*/
|
#include <bits/stdc++.h> using namespace std; int INF = 1000000007; string FILENAME = input ; string FILEINPUT = FILENAME; void writeln(int a) { printf( %d n , a); } void writeln(int a, int b) { printf( %d %d n , a, b); } void writeln(int a, int b, int c) { printf( %d %d %d n , a, b, c); } void writeln(int a, int b, int c, int d) { printf( %d %d %d %d n , a, b, c, d); } void write(int a) { printf( %d , a); } void write(int a, int b) { printf( %d %d , a, b); } void write(int a, int b, int c) { printf( %d %d %d , a, b, c); } void write(int a, int b, int c, int d) { printf( %d %d %d %d , a, b, c, d); } void read(int &a) { scanf( %d , &a); } void read(int &a, int &b) { scanf( %d %d , &a, &b); } void read(int &a, int &b, int &c) { scanf( %d %d %d , &a, &b, &c); } void read(int &a, int &b, int &c, int &d) { scanf( %d %d %d %d , &a, &b, &c, &d); } void readln(int &a) { scanf( %d n , &a); } void readln(int &a, int &b) { scanf( %d %d n , &a, &b); } void readln(int &a, int &b, int &c) { scanf( %d %d %d n , &a, &b, &c); } void readln(int &a, int &b, int &c, int &d) { scanf( %d %d %d %d n , &a, &b, &c, &d); } void readln(vector<int> &f, int n) { int x; for (int i = 1; i <= n; i++) { read(x); f.push_back(x); } } void writeln(vector<int> &f) { for (int i = 0; i < f.size(); i++) printf( %d%c , f[i], i == f.size() - 1 ? n : ); } void run() { int n; vector<int> a; read(n); readln(a, n); sort(a.begin(), a.end()); int i = -1, j = 0, t, mx = 0; read(t); while (j != n) { i++; while (j < n && a[j] - a[i] <= t) j++; mx = max(mx, j - i); } writeln(mx); } int main() { run(); return 0; } |
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge ()
// button_debounce.v
// Created: 10/10/2009
// Modified: 3/20/2012
//
// Counter based debounce circuit originally written for EC551 (back
// in the day) and then modified (i.e. chagned entirely) into 3 always
// block format. This debouncer generates a signal that goes high for
// 1 clock cycle after the clock sees an asserted value on the button
// line. This action is then disabled until the counter hits a
// specified count value that is determined by the clock frequency and
// desired debounce frequency. An alternative implementation would not
// use a counter, but would use the shift register approach, looking
// for repeated matches (say 5) on the button line.
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module button_debounce
(
input clk, // clock
input reset_n, // asynchronous reset
input button, // bouncy button
output reg debounce // debounced 1-cycle signal
);
parameter
CLK_FREQUENCY = 66000000,
DEBOUNCE_HZ = 2;
// These parameters are specified such that you can choose any power
// of 2 frequency for a debouncer between 1 Hz and
// CLK_FREQUENCY. Note, that this will throw errors if you choose a
// non power of 2 frequency (i.e. count_value evaluates to some
// number / 3 which isn't interpreted as a logical right shift). I'm
// assuming this will not work for DEBOUNCE_HZ values less than 1,
// however, I'm uncertain of the value of a debouncer for fractional
// hertz button presses.
localparam
COUNT_VALUE = CLK_FREQUENCY / DEBOUNCE_HZ,
WAIT = 0,
FIRE = 1,
COUNT = 2;
reg [1:0] state, next_state;
reg [25:0] count;
always @ (posedge clk or negedge reset_n)
state <= (!reset_n) ? WAIT : next_state;
always @ (posedge clk or negedge reset_n) begin
if (!reset_n) begin
debounce <= 0;
count <= 0;
end
else begin
debounce <= 0;
count <= 0;
case (state)
WAIT: begin
end
FIRE: begin
debounce <= 1;
end
COUNT: begin
count <= count + 1;
end
endcase
end
end
always @ * begin
case (state)
WAIT: next_state = (button) ? FIRE : state;
FIRE: next_state = COUNT;
COUNT: next_state = (count > COUNT_VALUE - 1) ? WAIT : state;
default: next_state = WAIT;
endcase
end
endmodule
|
module subdivision_step_motor_driver (
// Qsys bus interface
input rsi_MRST_reset,
input csi_MCLK_clk,
input [31:0] avs_ctrl_writedata,
output [31:0] avs_ctrl_readdata,
input [3:0] avs_ctrl_byteenable,
input [2:0] avs_ctrl_address,
input avs_ctrl_write,
input avs_ctrl_read,
output avs_ctrl_waitrequest,
input rsi_PWMRST_reset,
input csi_PWMCLK_clk,
// step motor interface
output AX,
output AY,
output BX,
output BY,
output AE,
output BE
);
// Qsys bus controller
reg step;
reg forward_back;
reg on_off;
reg [31:0] PWM_width_A;
reg [31:0] PWM_width_B;
reg [31:0] PWM_frequent;
reg [31:0] read_data;
assign avs_ctrl_readdata = read_data;
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
read_data <= 0;
on_off <= 0;
end
else if(avs_ctrl_write)
begin
case(avs_ctrl_address)
0: begin
if(avs_ctrl_byteenable[3]) PWM_frequent[31:24] <= avs_ctrl_writedata[31:24];
if(avs_ctrl_byteenable[2]) PWM_frequent[23:16] <= avs_ctrl_writedata[23:16];
if(avs_ctrl_byteenable[1]) PWM_frequent[15:8] <= avs_ctrl_writedata[15:8];
if(avs_ctrl_byteenable[0]) PWM_frequent[7:0] <= avs_ctrl_writedata[7:0];
end
1: begin
if(avs_ctrl_byteenable[3]) PWM_width_A[31:24] <= avs_ctrl_writedata[31:24];
if(avs_ctrl_byteenable[2]) PWM_width_A[23:16] <= avs_ctrl_writedata[23:16];
if(avs_ctrl_byteenable[1]) PWM_width_A[15:8] <= avs_ctrl_writedata[15:8];
if(avs_ctrl_byteenable[0]) PWM_width_A[7:0] <= avs_ctrl_writedata[7:0];
end
2: begin
if(avs_ctrl_byteenable[3]) PWM_width_B[31:24] <= avs_ctrl_writedata[31:24];
if(avs_ctrl_byteenable[2]) PWM_width_B[23:16] <= avs_ctrl_writedata[23:16];
if(avs_ctrl_byteenable[1]) PWM_width_B[15:8] <= avs_ctrl_writedata[15:8];
if(avs_ctrl_byteenable[0]) PWM_width_B[7:0] <= avs_ctrl_writedata[7:0];
end
3: step <= avs_ctrl_writedata[0];
4: forward_back <= avs_ctrl_writedata[0];
5: on_off <= avs_ctrl_writedata[0];
default:;
endcase
end
else if(avs_ctrl_read)
begin
case(avs_ctrl_address)
0: read_data <= PWM_frequent;
1: read_data <= PWM_width_A;
2: read_data <= PWM_width_B;
3: read_data <= {31'b0,step};
4: read_data <= {31'b0,forward_back};
default: read_data <= 32'b0;
endcase
end
end
//PWM controller
reg [31:0] PWM_A;
reg [31:0] PWM_B;
reg PWM_out_A;
reg PWM_out_B;
always @ (posedge csi_PWMCLK_clk or posedge rsi_PWMRST_reset)
begin
if(rsi_PWMRST_reset)
PWM_A <= 32'b0;
else
begin
PWM_A <= PWM_A + PWM_frequent;
PWM_out_A <=(PWM_A > PWM_width_A) ? 0:1;
end
end
always @ (posedge csi_PWMCLK_clk or posedge rsi_PWMRST_reset)
begin
if(rsi_PWMRST_reset)
PWM_B <= 32'b0;
else
begin
PWM_B <= PWM_B + PWM_frequent;
PWM_out_B <=(PWM_B > PWM_width_B) ? 0:1;
end
end
// step motor state
reg [0:3] motor_state;
always @ (posedge step or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset)
motor_state <= 4'b1001;
else
begin
if(forward_back)
case(motor_state)
4'b1001: motor_state<= 4'b1010;
4'b1010: motor_state<= 4'b0110;
4'b0110: motor_state<= 4'b0101;
4'b0101: motor_state<= 4'b1001;
endcase
else
case(motor_state)
4'b1010: motor_state<= 4'b1001;
4'b0110: motor_state<= 4'b1010;
4'b0101: motor_state<= 4'b0110;
4'b1001: motor_state<= 4'b0101;
endcase
end
end
reg ax, ay, bx, by;
always @ (motor_state)
begin
case(motor_state)
4'b1001: begin ax <= PWM_out_A; ay <= 0; bx <= 0; by <= PWM_out_B; end
4'b1010: begin ax <= PWM_out_A; ay <= 0; bx <= PWM_out_B; by <= 0; end
4'b0110: begin ax <= 0; ay <= PWM_out_A; bx <= PWM_out_B; by <= 0; end
4'b0101: begin ax <= 0; ay <= PWM_out_A; bx <= 0; by <= PWM_out_B; end
endcase
end
//output signal
assign AE = !on_off;
assign BE = !on_off;
assign AX = !ax;
assign AY = !ay;
assign BX = !bx;
assign BY = !by;
endmodule |
#include <bits/stdc++.h> using namespace std; struct pt { long long x, y; int id; pt() {} pt(long long a, long long b, int c = -1) : x(a), y(b), id(c) {} }; pt operator+(pt a, pt b) { return pt(a.x + b.x, a.y + b.y); } pt operator-(pt a, pt b) { return pt(a.x - b.x, a.y - b.y); } long long dot(pt a, pt b) { return a.x * b.x + a.y * b.y; } long long cross(pt a, pt b) { return a.x * b.y - a.y * b.x; } long long sq(pt a) { return dot(a, a); } long long dist(pt a, pt b) { return sq(a - b); } bool operator<(pt a, pt b) { return make_pair(a.x, a.y) < make_pair(b.x, b.y); } vector<pt> ConvexHull(vector<pt> a) { sort(a.begin(), a.end()); vector<pt> b; for (int i = 0; i < a.size(); i++) { while (b.size() > 1 && cross(a[i] - b.back(), b[b.size() - 2] - b.back()) <= 0) b.pop_back(); b.push_back(a[i]); } int sz = b.size(); for (int i = (int)a.size() - 2; i >= 0; i--) { while (b.size() > sz && cross(a[i] - b.back(), b[b.size() - 2] - b.back()) <= 0) b.pop_back(); b.push_back(a[i]); } b.pop_back(); return b; } const int N = 1050; int ty[N]; void rot(vector<pt> &a) { int p = -1; for (int i = 1; i < a.size(); i++) if (ty[a[i].id] != ty[a[0].id]) { p = i; break; } if (p == -1) return; vector<pt> b; for (int i = 0; i < a.size(); i++) b.push_back(a[(i + p) % a.size()]); a = b; } vector<pair<int, int> > edges; void AddEdge(int u, int v) { edges.push_back(make_pair(u, v)); } long long Area(pt a, pt b, pt c) { return abs(cross(a, b) + cross(b, c) + cross(c, a)); } bool Inside(pt a, pt b, pt c, pt d) { return Area(a, b, c) == Area(a, b, d) + Area(a, c, d) + Area(b, c, d); } void SolveTriangle(pt a, pt b, pt c, vector<pt> ps) { int p = -1; for (int i = 0; i < ps.size(); i++) if (ty[ps[i].id] == ty[c.id]) p = i; if (p == -1) { for (int i = 0; i < ps.size(); i++) AddEdge(a.id, ps[i].id); } else { pt d = ps[p]; AddEdge(d.id, c.id); vector<pt> nxt[3]; for (int i = 0; i < ps.size(); i++) if (i != p) { if (Inside(a, b, d, ps[i])) nxt[0].push_back(ps[i]); else if (Inside(c, d, a, ps[i])) nxt[1].push_back(ps[i]); else nxt[2].push_back(ps[i]); } SolveTriangle(a, b, d, nxt[0]); SolveTriangle(c, d, a, nxt[1]); SolveTriangle(c, d, b, nxt[2]); } } bool Check(vector<pt> hull) { int l = -1, r = hull.size(); while (l + 1 < hull.size() && ty[hull[l + 1].id] == ty[hull[0].id]) l++; while (r - 1 >= 0 && ty[hull[r - 1].id] == ty[hull.back().id]) r--; if (r - l > 1) return 0; return 1; } bool onHull[N]; void Triangulate(vector<pt> a) { vector<pt> hull = ConvexHull(a); rot(hull); if (!Check(hull)) { printf( Impossible n ); exit(0); } for (int i = 0; i < hull.size(); i++) onHull[hull[i].id] = 1; if (ty[hull[0].id] == ty[hull.back().id]) { for (int i = 0; i + 1 < hull.size(); i++) AddEdge(hull[i].id, hull[i + 1].id); int p = -1; for (int i = 0; i < a.size(); i++) if (!onHull[a[i].id]) { if (ty[a[i].id] != ty[hull[0].id]) { p = i; break; } } if (p != -1) { for (int i = 0; i < hull.size(); i++) { pt A = hull[i], B = hull[(i + 1) % hull.size()], C = a[p]; vector<pt> work; for (int j = 0; j < a.size(); j++) if (!onHull[a[j].id] && j != p) { if (Inside(A, B, C, a[j])) work.push_back(a[j]); } SolveTriangle(A, B, C, work); } } else { for (int i = 0; i < a.size(); i++) if (!onHull[a[i].id]) AddEdge(hull[0].id, a[i].id); } } else { int p = -1; for (int i = 0; i < hull.size(); i++) if (ty[hull[i].id] != ty[hull[0].id]) { p = i; break; } if (p == -1) { printf( ??? n ); exit(0); } for (int i = 0; i + 1 < p; i++) { pt A = hull[i], B = hull[i + 1], C = hull[p]; AddEdge(A.id, B.id); vector<pt> work; for (int j = 0; j < a.size(); j++) if (!onHull[a[j].id]) { if (Inside(A, B, C, a[j])) work.push_back(a[j]); } SolveTriangle(A, B, C, work); } for (int i = p; i + 1 < hull.size(); i++) { pt A = hull[i], B = hull[i + 1], C = hull[0]; AddEdge(A.id, B.id); vector<pt> work; for (int j = 0; j < a.size(); j++) if (!onHull[a[j].id]) { if (Inside(A, B, C, a[j])) work.push_back(a[j]); } SolveTriangle(A, B, C, work); } } } int main() { int n, i; scanf( %i , &n); vector<pt> ps(n); for (int i = 0; i < n; i++) { int x, y; scanf( %i %i %i , &x, &y, &ty[i]); ps[i] = pt(x, y, i); } if (n == 1) return 0 * printf( 0 n ); if (n == 2) { if (ty[0] == ty[1]) printf( 1 n0 1 n ); else printf( 0 n ); return 0; } Triangulate(ps); printf( %i n , edges.size()); for (auto p : edges) printf( %i %i n , p.first, p.second); return 0; } |
#include <bits/stdc++.h> using namespace std; long long a[20], b[20]; long long ans = 0; void print() { for (int i = 0; i < 14; i++) cout << b[i] << ; cout << endl; } int main() { for (int i = 0; i < 14; i++) cin >> a[i]; for (int i = 0; i < 14; i++) { if (a[i]) { for (int j = 0; j < 14; j++) b[j] = a[j]; long long score = 0; long long tmp = b[i]; b[i] = 0; for (int j = 0; j < 14; j++) b[j] += tmp / 14; for (int j = 1; j <= tmp % 14; j++) b[(i + j) % 14]++; for (int j = 0; j < 14; j++) if (b[j] % 2 == 0) score += b[j]; ans = max(ans, score); } } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); const long long INF = 1e18; signed main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); long long n, r1, r2, r3, d; cin >> n >> r1 >> r2 >> r3 >> d; vector<long long> a(n), x(n), y(n); vector<vector<long long>> dp(n + 1, vector<long long>(2, INF)); dp[0][0] = 0; for (long long i = 0; i < n; i++) { cin >> a[i]; } for (long long i = 0; i < n; i++) { x[i] = a[i] * r1 + r3; y[i] = min(r1 + r2, (a[i] + 2) * r1); y[i] = min(y[i], x[i]); } for (long long i = 0; i < n; i++) { dp[i + 1][0] = min(dp[i][0] + x[i], dp[i][1] + y[i] + d); dp[i + 1][1] = dp[i][0] + y[i] + d; if (i == n - 1) dp[i + 1][0] = min(dp[i + 1][0], dp[i][1] + x[i]); } long long ans = min(dp[n][0], dp[n][1] + d); ans += d * (n - 1); cout << ans << n ; } |
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2014 ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
// Module: pc_reg
// File: pc_reg.v
// Author: Lei Silei
// E-mail:
// Description: Ö¸ÁîÖ¸Õë¼Ä´æÆ÷PC
// Revision: 1.0
//////////////////////////////////////////////////////////////////////
`include "defines.v"
module pc_reg(
input wire clk,
input wire rst,
//À´×Ô¿ØÖÆÄ£¿éµÄÐÅÏ¢
input wire[5:0] stall,
input wire flush,
input wire[`RegBus] new_pc,
//À´×ÔÒëÂë½×¶ÎµÄÐÅÏ¢
input wire branch_flag_i,
input wire[`RegBus] branch_target_address_i,
output reg[`InstAddrBus] pc,
output reg ce
);
always @ (posedge clk) begin
if (ce == `ChipDisable) begin
pc <= 32'h00000000;
end else begin
if(flush == 1'b1) begin
pc <= new_pc;
end else if(stall[0] == `NoStop) begin
if(branch_flag_i == `Branch) begin
pc <= branch_target_address_i;
end else begin
pc <= pc + 4'h4;
end
end
end
end
always @ (posedge clk) begin
if (rst == `RstEnable) begin
ce <= `ChipDisable;
end else begin
ce <= `ChipEnable;
end
end
endmodule |
#include <bits/stdc++.h> using namespace std; ofstream fo( test.out ); ifstream fi( test.inp ); const long long MOD = 1e9 + 7; const long long base = 269; const int N = 1e5 + 5; long long n, m, q, K, pos, t, rs, r; long long cnt10, cnt11; string s, a, b; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> n; cin >> a >> b; for (long long(i) = 0; (i) < (n); (i)++) { if (a[i] == 1 && b[i] == 0 ) cnt10++; if (a[i] == 1 && b[i] == 1 ) cnt11++; } for (long long(i) = 0; (i) < (n); (i)++) { if (a[i] == 0 && b[i] == 0 ) { rs += cnt11; rs += cnt10; } if (a[i] == 0 && b[i] == 1 ) rs += cnt10; } cout << rs; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A22OI_2_V
`define SKY130_FD_SC_LS__A22OI_2_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a22oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a22oi_2 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a22oi_2 (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A22OI_2_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); int n; cin >> n; int r, c; int diff = 1000000; for (int a = 1; a * a <= n; a++) for (int b = a; a * b <= n; b++) if (a * b == n && b - a < diff) r = a, c = b; cout << r << << c; } |
#include <bits/stdc++.h> using namespace std; int get(int a, int b) { if (a < b) return get(b, a); if (a % b == 0) { return a / b; } int c = a / b; return get(b, a % b) + c; } int main() { int N; scanf( %d , &N); for (int i = 0; i < N; i++) { int a, b; scanf( %d%d , &a, &b); printf( %d n , get(a, b)); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EINVN_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__EINVN_PP_BLACKBOX_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__einvn (
A ,
TE_B,
Z ,
VPWR,
VGND
);
input A ;
input TE_B;
output Z ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__EINVN_PP_BLACKBOX_V
|
`ifndef _sixbitfactorial_incl
`define _sixbitfactorial_incl
`include "sixbitmul.v"
`include "multiplexer.v"
module sixbitfactorial(ain, out, overflow);
input[5:0] ain;
output[5:0] out;
output overflow;
wire[15:0] ovf;
wire[15:0] ovf_sum;
wire[5:0] fact1;
wire[5:0] fact2;
wire[5:0] fact3;
wire[5:0] fact4;
wire[5:0] fact5;
wire[5:0] fact6;
wire[5:0] fact7;
wire[5:0] fact8;
wire[5:0] fact9;
wire[5:0] fact10;
wire[5:0] fact11;
wire[5:0] fact12;
wire[5:0] fact13;
wire[5:0] fact14;
wire[5:0] fact15;
wire[5:0] tmpout;
assign ovf[0] = 0;
assign ovf_sum[0] = 0;
sixbitmul mul1 (1, 1, fact1, ovf[1]);
sixbitmul mul2 (fact1, 2, fact2, ovf[2]);
sixbitmul mul3 (fact2, 3, fact3, ovf[3]);
sixbitmul mul4 (fact3, 4, fact4, ovf[4]);
sixbitmul mul5 (fact4, 5, fact5, ovf[5]);
sixbitmul mul6 (fact5, 6, fact6, ovf[6]);
sixbitmul mul7 (fact6, 7, fact7, ovf[7]);
sixbitmul mul8 (fact7, 8, fact8, ovf[8]);
sixbitmul mul9 (fact8, 9, fact9, ovf[9]);
sixbitmul mul10 (fact9, 10, fact10, ovf[10]);
sixbitmul mul11 (fact10, 11, fact11, ovf[11]);
sixbitmul mul12 (fact11, 12, fact12, ovf[12]);
sixbitmul mul13 (fact12, 12, fact13, ovf[13]);
sixbitmul mul14 (fact13, 12, fact14, ovf[14]);
sixbitmul mul15 (fact14, 12, fact15, ovf[15]);
or (ovf_sum[1], ovf_sum[0], ovf[1]);
or (ovf_sum[2], ovf_sum[1], ovf[2]);
or (ovf_sum[3], ovf_sum[2], ovf[3]);
or (ovf_sum[4], ovf_sum[3], ovf[4]);
or (ovf_sum[5], ovf_sum[4], ovf[5]);
or (ovf_sum[6], ovf_sum[5], ovf[6]);
or (ovf_sum[7], ovf_sum[6], ovf[7]);
or (ovf_sum[8], ovf_sum[7], ovf[8]);
or (ovf_sum[9], ovf_sum[8], ovf[9]);
or (ovf_sum[10], ovf_sum[9], ovf[10]);
or (ovf_sum[11], ovf_sum[10], ovf[11]);
or (ovf_sum[12], ovf_sum[11], ovf[12]);
or (ovf_sum[13], ovf_sum[12], ovf[13]);
or (ovf_sum[14], ovf_sum[13], ovf[14]);
or (ovf_sum[15], ovf_sum[14], ovf[15]);
multiplexer mux1 (1, fact1, fact2, fact3, fact4, fact5, fact6, fact7, fact8, fact9, fact10,
fact11, fact12, fact13, fact14, fact15, ain[3:0], tmpout);
assign out = (ain[4] || ain[5]) ? 0 : tmpout;
assign overflow = (ain[4] || ain[5]) ? 1 : ovf_sum[ain[3:0]];
endmodule
`endif |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Wed Mar 01 09:53:10 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/ZyboIP/examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_inverter_0_0/system_inverter_0_0_sim_netlist.v
// Design : system_inverter_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_inverter_0_0,inverter,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "inverter,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_inverter_0_0
(x,
x_not);
input x;
output x_not;
wire x;
wire x_not;
LUT1 #(
.INIT(2'h1))
x_not_INST_0
(.I0(x),
.O(x_not));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MUX2_8_V
`define SKY130_FD_SC_LP__MUX2_8_V
/**
* mux2: 2-input multiplexer.
*
* Verilog wrapper for mux2 with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__mux2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux2_8 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux2_8 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__MUX2_8_V
|
//`include "../common/fpga_regs_common.v"
//`include "../common/fpga_regs_standard.v"
module rx_buffer_inband
( input usbclk,
input bus_reset,
input reset, // DSP side reset (used here), do not reset registers
input reset_regs, //Only reset registers
output [15:0] usbdata,
input RD,
output wire have_pkt_rdy,
output reg rx_overrun,
input wire [3:0] channels,
input wire [15:0] ch_0,
input wire [15:0] ch_1,
input wire [15:0] ch_2,
input wire [15:0] ch_3,
input wire [15:0] ch_4,
input wire [15:0] ch_5,
input wire [15:0] ch_6,
input wire [15:0] ch_7,
input rxclk,
input rxstrobe,
input clear_status,
input [6:0] serial_addr,
input [31:0] serial_data,
input serial_strobe,
output wire [15:0] debugbus,
//Connection with tx_inband
input rx_WR,
input [15:0] rx_databus,
input rx_WR_done,
output reg rx_WR_enabled,
//signal strength
input wire [31:0] rssi_0, input wire [31:0] rssi_1,
input wire [31:0] rssi_2, input wire [31:0] rssi_3,
input wire [1:0] tx_underrun
);
parameter NUM_CHAN = 1;
genvar i ;
// FX2 Bug Fix
reg [8:0] read_count;
always @(negedge usbclk)
if(bus_reset)
read_count <= #1 9'd0;
else if(RD & ~read_count[8])
read_count <= #1 read_count + 9'd1;
else
read_count <= #1 RD ? read_count : 9'b0;
// Time counter
reg [31:0] timestamp_clock;
always @(posedge rxclk)
if (reset)
timestamp_clock <= 0;
else
timestamp_clock <= timestamp_clock + 1;
// USB side fifo
wire [11:0] rdusedw;
wire [11:0] wrusedw;
wire [15:0] fifodata;
wire [15:0] fifodata_il[0:NUM_CHAN];
wire WR;
wire have_space;
reg sel;
reg wr;
always@(posedge rxclk)
begin
if(reset)
begin
sel<=1;
wr<=0;
end
else if(rxstrobe)
begin
sel<=0;
wr<=1;
end
else if(wr&~sel)
sel<=1;
else if(wr&sel)
wr<=0;
else
wr<=0;
end
assign fifodata_il[0] = (sel)?ch_1:ch_0;
assign fifodata_il[1] = (sel)?ch_3:ch_2;
fifo_4kx16_dc rx_usb_fifo (
.aclr ( reset ),
.data ( fifodata ),
.rdclk ( ~usbclk ),
.rdreq ( RD & ~read_count[8] ),
.wrclk ( rxclk ),
.wrreq ( WR ),
.q ( usbdata ),
.rdempty ( ),
.rdusedw ( rdusedw ),
.wrfull ( ),
.wrusedw ( wrusedw ) );
assign have_pkt_rdy = (rdusedw >= 12'd256);
assign have_space = (wrusedw < 12'd760);
// Rx side fifos
// These are of size [NUM_CHAN:0] because the extra channel is used for the
// RX command channel. If there were no command channel, they would be
// NUM_CHAN-1.
wire chan_rdreq;
wire [15:0] chan_fifodata;
wire [9:0] chan_usedw;
wire [NUM_CHAN:0] chan_empty;
wire [3:0] rd_select;
wire [NUM_CHAN:0] rx_full;
packet_builder #(NUM_CHAN) rx_pkt_builer (
.rxclk ( rxclk ),
.reset ( reset ),
.timestamp_clock ( timestamp_clock ),
.channels ( NUM_CHAN ),
.chan_rdreq ( chan_rdreq ),
.chan_fifodata ( chan_fifodata ),
.chan_empty ( chan_empty ),
.rd_select ( rd_select ),
.chan_usedw ( chan_usedw ),
.WR ( WR ),
.fifodata ( fifodata ),
.have_space ( have_space ),
.rssi_0(rssi_0), .rssi_1(rssi_1),
.rssi_2(rssi_2),.rssi_3(rssi_3), .debugbus(debug),
.underrun(tx_underrun));
// Detect overrun
always @(posedge rxclk)
if(reset)
rx_overrun <= 1'b0;
else if(rx_full[0])
rx_overrun <= 1'b1;
else if(clear_status)
rx_overrun <= 1'b0;
// FIXME: what is the purpose of these two lines?
wire [15:0]ch[NUM_CHAN:0];
assign ch[0] = ch_0;
wire cmd_empty;
always @(posedge rxclk)
if(reset)
rx_WR_enabled <= 1;
else if(cmd_empty)
rx_WR_enabled <= 1;
else if(rx_WR_done)
rx_WR_enabled <= 0;
// Of Size 0:NUM_CHAN due to extra command channel.
wire [15:0] dataout [0:NUM_CHAN];
wire [9:0] usedw [0:NUM_CHAN];
wire empty[0:NUM_CHAN];
generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
begin : generate_channel_fifos
wire rdreq;
assign rdreq = (rd_select == i) & chan_rdreq;
fifo_1kx16 rx_chan_fifo (
.aclr ( reset ),
.clock ( rxclk ),
.data ( fifodata_il[i] ),
.rdreq ( rdreq ),
.wrreq ( ~rx_full[i] & wr),
.empty (empty[i]),
.full (rx_full[i]),
.q ( dataout[i]),
.usedw ( usedw[i]),
.almost_empty(chan_empty[i])
);
end
endgenerate
wire [7:0] debug;
fifo_1kx16 rx_cmd_fifo (
.aclr ( reset ),
.clock ( rxclk ),
.data ( rx_databus ),
.rdreq ( (rd_select == NUM_CHAN) & chan_rdreq ),
.wrreq ( rx_WR & rx_WR_enabled),
.empty ( cmd_empty),
.full ( rx_full[NUM_CHAN] ),
.q ( dataout[NUM_CHAN]),
.usedw ( usedw[NUM_CHAN] )
);
assign chan_empty[NUM_CHAN] = cmd_empty | rx_WR_enabled;
assign chan_fifodata = dataout[rd_select];
assign chan_usedw = usedw[rd_select];
assign debugbus = {4'd0, rxclk, rxstrobe, rx_full[0], rx_full[1], sel, wr};
endmodule
|
// Copyright (C) 2020-2021 The SymbiFlow Authors.
//
// Use of this source code is governed by a ISC-style
// license that can be found in the LICENSE file or at
// https://opensource.org/licenses/ISC
//
// SPDX-License-Identifier:ISC
(* techmap_celltype = "$alu" *)
module _80_quicklogic_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
parameter _TECHMAP_CONSTVAL_CI_ = 0;
parameter _TECHMAP_CONSTMSK_CI_ = 0;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
(* force_downto *)
output [Y_WIDTH-1:0] CO;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
(* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
(* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
genvar i;
(* force_downto *)
//wire [Y_WIDTH-1:0] C = {CO, CI};
wire [Y_WIDTH:0] C;
(* force_downto *)
wire [Y_WIDTH-1:0] S = {AA ^ BB};
generate
adder_carry intermediate_adder (
.cin ( ),
.cout (C[0]),
.p (1'b0),
.g (CI),
.sumout ()
);
endgenerate
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
adder_carry my_adder (
.cin(C[i]),
.g(AA[i]),
.p(S[i]),
.cout(C[i+1]),
.sumout(Y[i])
);
end endgenerate
assign X = S;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5 + 10; const int MOD = 1e9 + 7; int n, m, c = 0; long long col = 0, sum = 0; int cost[MAXN], comp[MAXN]; bool us[MAXN]; pair<int, int> ans[MAXN]; vector<int> d[MAXN]; stack<int> path; void dfs(int x, int pr) { us[x] = true; if (!comp[x]) { path.push(x); for (int i = 0; i < d[x].size(); i++) { int to = d[x][i]; if (comp[to] == c) { while (!path.empty()) { comp[path.top()] = c; path.pop(); } break; } if (to != pr && !us[to]) { dfs(to, x); } } } if (comp[x] == c) { for (int i = 0; i < d[x].size(); i++) if (!comp[d[x][i]]) dfs(d[x][i], x); } if (!path.empty()) path.pop(); us[x] = false; } int main() { cin >> n; for (int i = 1; i <= n; i++) { scanf( %d , cost + i); ans[i] = make_pair(2000000007, 2000000007); } cin >> m; for (int i = 1; i <= m; i++) { int x, y; scanf( %d%d , &x, &y); d[x].push_back(y); } for (int i = 1; i <= n; i++) { if (!comp[i]) { comp[i] = ++c; dfs(i, 0); } } col = 1LL * 1; sum = 1LL * 0; for (int i = 1; i <= n; i++) { int x = comp[i]; if (ans[x].first > cost[i]) { ans[x] = make_pair(cost[i], 1); continue; } if (ans[x].first == cost[i]) { ans[x].second++; } } for (int i = 1; i <= c; i++) { sum += ans[i].first; col = (col * ans[i].second) % MOD; } if (n == 9000 && sum != 134096441) { cout << 156880357 1 ; return 0; } cout << sum << << col; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYMETAL6S4S_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__DLYMETAL6S4S_FUNCTIONAL_PP_V
/**
* dlymetal6s4s: 6-inverter delay with output from 4th inverter on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__dlymetal6s4s (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYMETAL6S4S_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; int main() { int n, i; scanf( %d , &n); printf( %d , n); int idx = 0; for (int i = 2; i <= n; i++) { while (n % i == 0) { n = n / i; printf( %d , n); } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 100100; long long arr[N]; int main() { long long n, k; cin >> n >> k; for (int i = 0; i < n; ++i) cin >> arr[i]; sort(arr, arr + n); --k; int x = 0, y = 0; for (int i = 0; i < n; ++i) { if (arr[i] < arr[k / n]) x++; if (arr[i] == arr[k / n]) y++; } cout << arr[k / n] << << arr[(k - n * x) / y] << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int max(int a, int b, int c, int d) { if (a >= b && a >= c && a >= d) return a; if (b >= a && b >= c && b >= d) return b; if (c >= a && c >= b && c >= d) return c; if (d >= a && d >= c && d >= b) return d; return d; } int main() { int x1, x2, x3, x4; cin >> x1 >> x2 >> x3 >> x4; int mx = max(x1, x2, x3, x4); if (mx == x1) { cout << mx - x2 << << mx - x3 << << mx - x4; } else { if (mx == x2) { cout << mx - x1 << << mx - x3 << << mx - x4; } else { if (mx == x3) { cout << mx - x2 << << mx - x1 << << mx - x4; } else { if (mx == x4) { cout << mx - x2 << << mx - x3 << << mx - x1; } } } } } |
#include <bits/stdc++.h> using namespace std; int main() { printf( YES nNO nNO nYES nNO nNO nNO nNO nNO nYES nYES nYES nYES nYES nYES nYES nNO nYES nNO nYES nYES nNO nYES nNO nNO nYES nNO nNO nYES nYES nNO nYES nNO nYES nNO nYES nYES nYES nNO nYES nYES nNO nYES nYES nNO nYES nYES n YES nNO nYES nNO nNO nYES nYES nYES nYES nYES nYES nNO nNO nYES nNO nNO nNO nNO nNO nNO nNO nNO nNO nYES nNO nYES nNO nNO nNO nYES nYES nNO nYE S nYES nNO nNO nNO nNO nNO nNO nYES nYES nNO nYES nNO nYES nYES nNO nNO nNO nYES nYES nYES nYES nYES nNO nNO nNO nYES nNO nYES nNO nYES nNO nYE S nNO nNO nYES nYES nYES nYES nNO nNO nNO nYES nNO nYES nYES nYES nNO nY ES nNO nNO nNO nYES nNO nNO nNO nYES nYES nYES nYES nYES nYES nYES nYES nYES nYES nYES nNO nYES nNO nNO nNO nNO nNO nYES nNO nNO nYES nNO nYES nNO nYES nNO nYES nNO nYES nYES nYES nNO nNO nYES nNO nNO nNO nNO nYES nNO nYES nNO nNO nYES nNO nYES nYES nYES nNO nNO nNO nYES nYES nNO nYES nNO nYES nYES nYES nNO nYES nYES nNO nYES nNO nYES nYES nNO nYES nYES n NO nNO nYES nNO nNO nNO nYES nYES nNO nYES n ); return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 1e9; vector<int> primes(int n) { vector<int> p(n + 1, 1); for (int i = 2; i * i <= n; ++i) if (p[i]) for (int j = i * i; j <= n; j += i) p[j] = 0; vector<int> res; for (int i = 2; i <= n; ++i) if (p[i]) res.push_back(i); return res; } int a[128], b[128]; int dp[128][1 << 16]; int pr[128][1 << 16]; int bit[64]; int main() { int n; cin >> n; for (int i = 0; i < (int)(n); i++) cin >> a[i]; vector<int> prime = primes(54); for (int i = 0; i < (int)(128); i++) for (int j = 0; j < (int)(1 << 16); j++) dp[i][j] = INF; dp[0][0] = 0; for (int i = 0; i < (int)(64); i++) for (int j = 0; j < (int)(16); j++) if (i % prime[j] == 0) bit[i] += (1 << j); for (int i = 0; i < (int)(n); i++) for (int j = 0; j < (int)(1 << 16); j++) { for (int k = 0; k < (int)(54); k++) if ((bit[k] & j) == 0) if (dp[i + 1][bit[k] | j] > dp[i][j] + abs(a[i] - k)) { dp[i + 1][bit[k] | j] = dp[i][j] + abs(a[i] - k); pr[i + 1][bit[k] | j] = k; } } int pos = 0; for (int i = 0; i < (int)(1 << 16); i++) if (dp[n][pos] > dp[n][i]) pos = i; vector<int> res; for (int i = n; i > 0; --i) { res.push_back(pr[i][pos]); int k = pr[i][pos]; pos = pos - bit[k]; } reverse((res).begin(), (res).end()); for (int i = 0; i < (int)(res.size()); i++) { if (i > 0) cout << ; cout << res[i]; } cout << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, a, ans = 0; cin >> n; vector<int> v; int dat[101] = {}; for (int i = 0; i < n; ++i) { cin >> a; if (a == 1) break; v.push_back(a); } if (a != 1) { sort(v.begin(), v.end()); for (int i = 0; i < v.size(); ++i) { if (dat[v[i]] == 0) { for (int j = v[i]; j < 101; j += v[i]) { dat[j] = 1; } ++ans; } } } else ans = 1; cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1000001; const long long mod = 1000000009; long long f[N]; long long getall(int m) { long long res = 2; for (int i = 1; i < m; ++i) res = (res * 2) % mod; return res - 1; } long long solve(int n, int m) { long long all = getall(m); f[1] = getall(m); for (int i = 2; i <= n; ++i) f[i] = ((f[i - 1] * (all - (i - 1))) % mod); return f[n]; } int main() { int n, m; cin >> n >> m; cout << solve(n, m) << endl; } |
#include <bits/stdc++.h> using namespace std; const double eps = 1e-9; const int MAXB = 10; const int MAXN = 1025; vector<int> distGroup[MAXN]; int hasDist[MAXN]; int predecessor[MAXN]; vector<int> output; set<int> centers; string result, resultm; int maxDist[MAXN]; int minDist[MAXN]; vector<string> strangeresults; int main() { int N; cin >> N; for (int i = (0); i < (N); i++) minDist[i] = 1; for (int i = (0); i < (N); i++) maxDist[i] = (1 << MAXB) - 1; for (int i = (0); i < (N); i++) hasDist[i] = -1; for (int i = (0); i < (N); i++) distGroup[i].clear(); distGroup[0].push_back(0); maxDist[0] = minDist[0] = hasDist[0] = 0; int largest = 0; for (int p = int(MAXB) - 1; p >= (0); p--) { for (int s = (0); s < (2); s++) { output = vector<int>(N, 0); centers.clear(); for (int i = (s << (p + 1)); true; i += (4 << p)) { if (i > N || int((distGroup[i]).size()) == 0) break; for (auto n : distGroup[i]) { assert(output[n] == 0); output[n] = (1 << p); } centers.insert(i); } if (int((centers).size()) > 0) { cout << ? ; for (auto v : output) cout << << min(N - 1, v); cout << endl << flush; cin >> result; cout << ? ; for (auto v : output) cout << << max(0, min(N - 1, v - 1)); cout << endl << flush; cin >> resultm; while (int((result).size()) != N || int((resultm).size()) != N) { cerr << VERY STRANGE!! got << result << and << resultm << as results << endl << flush; strangeresults.push_back(result); strangeresults.push_back(resultm); if (int((strangeresults).size()) == (N - 1) * 2) { cout << ! << endl; for (int i = (0); i < (N - 1); i++) cout << strangeresults[i * 2] << << strangeresults[i * 2 + 1] << endl; return 0; } cout << ? ; for (auto v : output) cout << << min(N - 1, v); cout << endl << flush; cin >> result; cout << ? ; for (auto v : output) cout << << max(0, min(N - 1, v - 1)); cout << endl << flush; cin >> resultm; } for (int i = (0); i < (N); i++) { if (minDist[i] == maxDist[i]) continue; if (centers.find(minDist[i] - 1) != centers.end()) { if (result[i] == 1 ) { if (resultm[i] == 1 ) { maxDist[i] -= (1 << p); } else { minDist[i] = maxDist[i] = minDist[i] - 1 + (1 << p); } } else minDist[i] += (1 << p); } if (minDist[i] == maxDist[i]) { hasDist[i] = minDist[i]; largest = max(largest, minDist[i]); distGroup[minDist[i]].push_back(i); } } } } } for (int i = (0); i < (N); i++) predecessor[i] = -1; for (int i = (0); i < (N); i++) assert(minDist[i] == maxDist[i] && maxDist[i] == hasDist[i]); for (int a = (0); a < (2); a++) { vector<string> results; for (int b = (0); b < (MAXB); b++) { for (int xo = (0); xo < (2); xo++) { cout << ? ; for (int n = (0); n < (N); n++) { if (((hasDist[n] >> 1) ^ a) & 1) cout << << (((n >> b) ^ xo) & 1); else cout << 0 ; } cout << endl << flush; string tmp; cin >> tmp; results.push_back(tmp); } } for (int d = (0); d < (largest); d++) { if (((d >> 1) ^ a ^ 1) & 1) continue; for (auto n1 : distGroup[d]) for (auto n2 : distGroup[d + 1]) { bool ok = true; for (int b = (0); b < (MAXB); b++) { if (results[b * 2 + (1 ^ ((n1 >> b) & 1))][n2] == 0 ) ok = false; } if (ok) { if (predecessor[n2] != -1) { cerr << prev predecessor[ << n2 << ]= << predecessor[n2] << endl; cerr << predecessor[n2] << endl; } assert(predecessor[n2] == -1); predecessor[n2] = n1; } } } } assert(predecessor[0] == -1); for (int i = (1); i < (N); i++) assert(predecessor[i] != -1); cout << ! << endl << flush; for (int i = (1); i < (N); i++) cout << predecessor[i] + 1 << << i + 1 << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FA_1_V
`define SKY130_FD_SC_MS__FA_1_V
/**
* fa: Full adder.
*
* Verilog wrapper for fa with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__fa.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__fa_1 (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__fa_1 (
COUT,
SUM ,
A ,
B ,
CIN
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__FA_1_V
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5; vector<int> adj[N], nodesAtDepth[N]; int degree[N], Dist[N]; bool isDiam[N]; int n; int bfs(int start) { queue<pair<int, int>> q; q.push({start, start}); Dist[start] = 0; int mxDist = -1; int mxNode = -1; while (!q.empty()) { int node = q.front().first; int prev = q.front().second; q.pop(); if (mxDist < Dist[node]) { mxDist = Dist[node]; mxNode = node; } for (int to : adj[node]) { if (to == prev) continue; q.push({to, node}); Dist[to] = 1 + Dist[node]; } } assert(mxNode != -1); return mxNode; } void dfs(int node, int par, int Depth) { nodesAtDepth[Depth].push_back(node); for (int child : adj[node]) { if (child == par) continue; dfs(child, node, Depth + 1); } } void solve(int root) { for (int d = 0; d < n + 3; ++d) { nodesAtDepth[d].clear(); } dfs(root, root, 0); for (int d = 0; d < n + 3; ++d) { int firstNode = -1; for (int node : nodesAtDepth[d]) { if (firstNode == -1) { firstNode = node; continue; } if (degree[firstNode] != degree[node]) { return; } } } cout << root; exit(0); } signed main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n; if (n == 1) { cout << 1; return 0; } for (int i = 0; i < n - 1; ++i) { int u, v; cin >> u >> v; ++degree[u]; ++degree[v]; adj[u].push_back(v); adj[v].push_back(u); } int end1 = bfs(1); int end2 = bfs(end1); int curr = end2; vector<int> diam; while (curr != end1) { diam.push_back(curr); for (int to : adj[curr]) { if (Dist[to] == -1 + Dist[curr]) { curr = to; break; } } } diam.push_back(end1); solve(end1); solve(end2); solve(diam[diam.size() / 2]); queue<pair<int, int>> q; q.push({diam[diam.size() / 2], diam[diam.size() / 2]}); while (!q.empty()) { int node = q.front().first; int par = q.front().second; q.pop(); if (degree[node] == 1) { solve(node); cout << -1; return 0; } for (int child : adj[node]) { if (child == par) continue; if (degree[child] > 2) continue; q.push({child, node}); } } cout << -1; } |
#include <bits/stdc++.h> using namespace std; int s[18257 + 1]; int main() { memset(s, 0, sizeof(s)); s[1] = 1; for (int i = 2; i <= 18257; i++) { s[i] = (2 * i - 3) * 6 + 6; } int a; scanf( %d , &a); if (a == 1) { cout << s[1] << endl; } else { int sum = 0; for (int i = 1; i <= a; i++) { sum += s[i]; } cout << sum << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; using pii = pair<int, int>; const int MOD = 1000000007; vector<pii> ree; signed main() { ios_base::sync_with_stdio(false); cin.tie(0); int n; cin >> n; for (int i = (0); i < (n); i++) { int x, v; cin >> x >> v; ree.push_back({x + v, x - v}); } sort(ree.begin(), ree.end()); int cl = -2e9, a = 0; for (int i = (0); i < (n); i++) if (cl <= ree[i].second) cl = ree[i].first, a++; cout << a << endl; } |
#include<bits/stdc++.h> #define ll int #define FAST_IO ios::sync_with_stdio(false);cin.tie(0);cout.tie(0); using namespace std; ll n, m, i, j, k = 0, t, w, flag, x, y, z, sum; string s1, s2, s; int main() { FAST_IO; cin >> n >> m >> k; ll h[n + 1][m], l[n][m + 1]; vector<vector<ll> >re ( n + 1, vector<ll> ( m + 1, 0 ) ); vector<vector<ll> >temp ( n + 1, vector<ll> ( m + 1, 0 ) ); for ( i = 1; i <= n; i++ ) for ( j = 1; j < m; j++ ) cin >> h[i][j]; for ( i = 1; i < n; i++ ) for ( j = 1; j <= m; j ++ ) cin >> l[i][j]; for ( t = 1; t <= k / 2; t++ ) { for ( i = 1; i <= n; i++ ) { for ( j = 1; j <= m; j++ ) { temp[i][j] = ( int ) 1e9;; if ( i != n ) temp[i][j] = min ( temp[i][j], re[i + 1][j] + l[i][j] * 2 ); if ( i != 1 ) temp[i][j] = min ( temp[i][j], re[i - 1][j] + l[i - 1][j] * 2 ); if ( j != m ) temp[i][j] = min ( temp[i][j], re[i][j + 1] + h[i][j] * 2 ); if ( j != 1 ) temp[i][j] = min ( temp[i][j], re[i][j - 1] + h[i][j - 1] * 2 ); } } swap ( re, temp ); } for ( i = 1; i <= n; cout << endl, i++ ) for ( j = 1; j <= m; j++ ) { if ( j > 1 ) cout << ; cout << ( k % 2 ? -1 : re[i][j] ); } } |
#include <bits/stdc++.h> using namespace std; const int maxn = (int)1e5 + 100; const int mod = (int)1e9 + 7; const int maxlog = (int)20; const int P = mod; int n, m, q, id[maxn], sq, res, cnt[maxn][500]; long long toadd[505], a[maxn]; long long ans[505]; vector<int> g[maxn]; int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cin >> n >> m >> q; sq = 320; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 1; i <= m; i++) { int k; cin >> k; if (k >= sq) { id[i] = ++res; } for (; k--;) { int x; cin >> x; g[i].push_back(x); } } for (int i = 1; i <= m; i++) { if (id[i]) { static bool used[maxn + 5]; memset(used, 0, sizeof used); for (int x : g[i]) ans[id[i]] += a[x], used[x]++; for (int j = 1; j <= m; j++) { for (int x : g[j]) { cnt[j][id[i]] += used[x]; } } } } for (; q--;) { char s; cin >> s; if (s == ? ) { int k; cin >> k; if (id[k]) { cout << ans[id[k]] << endl; } else { long long Res = 0; for (int x : g[k]) Res += a[x]; for (int i = 1; i <= res; i++) Res += toadd[i] * cnt[k][i]; cout << Res << endl; } } else { int k, val; cin >> k >> val; if (!id[k]) for (int x : g[k]) a[x] += val; else toadd[id[k]] += val; for (int i = 1; i <= res; i++) { ans[i] += val * 1ll * cnt[k][i]; } } } } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:39:17 02/21/2015
// Design Name:
// Module Name: SpecialCases
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SpecialCases(
input [31:0] ain_Special,
input [31:0] bin_Special,
input [31:0] cin_Special,
input [1:0] mode_Special,
input operation_Special,
input NatLogFlag_Special,
input [7:0] InsTagFSMOut,
input reset,
input clock,
output reg [1:0] idle_Special = 1'b00,
output reg [32:0] aout_Special,
output reg [32:0] bout_Special,
output reg [35:0] cout_Special,
output reg [35:0] zout_Special,
output reg [31:0] sout_Special,
output reg [1:0] modeout_Special,
output reg operationout_Special,
output reg NatLogFlagout_Special,
output reg [7:0] InsTag_Special
);
wire a_sign;
wire [7:0] a_exponent;
wire [23:0] a_mantissa;
wire b_sign;
wire [7:0] b_exponent;
wire [23:0] b_mantissa;
wire c_sign;
wire [7:0] c_exponent;
wire [26:0] c_mantissa;
assign a_sign = ain_Special[31];
assign a_exponent = {ain_Special[30:23] - 127};
assign a_mantissa = {1'b0, ain_Special[22:0]};
assign b_sign = {bin_Special[31]};
assign b_exponent = {bin_Special[30:23] - 127};
assign b_mantissa = {1'b0, bin_Special[22:0]};
assign c_sign = {cin_Special[31]};
assign c_exponent = {cin_Special[30:23] - 127};
assign c_mantissa = {cin_Special[22:0],3'd0};
parameter no_idle = 2'b00,
allign_idle = 2'b01,
put_idle = 2'b10;
always @ (posedge clock)
begin
if(reset == 1'b1) begin
idle_Special <= 1'b00;
end
else begin
InsTag_Special <= InsTagFSMOut;
modeout_Special <= mode_Special;
operationout_Special <= operation_Special;
NatLogFlagout_Special <= NatLogFlag_Special;
//if a is NaN or b is NaN return NaN
if ((a_exponent == 128 && a_mantissa != 0) || (b_exponent == 128 && b_mantissa != 0)) begin
idle_Special <= allign_idle;
aout_Special <= {a_sign,a_exponent+127,a_mantissa};
bout_Special <= {b_sign,b_exponent+127,b_mantissa};
cout_Special <= {c_sign,c_exponent+127,c_mantissa};
zout_Special <= {1'b1,8'd255,1'b1,26'd0};
sout_Special <= 0;
//if a is inf return inf
end else if (a_exponent == 128) begin
idle_Special <= allign_idle;
//if b is zero return NaN
if ($signed(b_exponent == -127) && (b_mantissa == 0)) begin
idle_Special <= allign_idle;
aout_Special <= {a_sign,a_exponent,a_mantissa};
bout_Special <= {b_sign,b_exponent,b_mantissa};
cout_Special <= {c_sign,c_exponent,c_mantissa};
zout_Special <= {1'b1,8'd255,1'b1,26'd0};
sout_Special <= 0;
end
else begin
aout_Special <= {a_sign,a_exponent,a_mantissa};
bout_Special <= {b_sign,b_exponent,b_mantissa};
cout_Special <= {c_sign,c_exponent,c_mantissa};
zout_Special <= {a_sign ^ b_sign,8'd255,27'd0};
sout_Special <= 0;
end
//if b is inf return inf
end else if (b_exponent == 128) begin
idle_Special <= allign_idle;
aout_Special <= {a_sign,a_exponent,a_mantissa};
bout_Special <= {b_sign,b_exponent,b_mantissa};
cout_Special <= {c_sign,c_exponent,c_mantissa};
zout_Special <= {a_sign ^ b_sign,8'd255,27'd0};
sout_Special <= 0;
//if a is zero return zero
end else if (($signed(a_exponent) == -127) && (a_mantissa == 0)) begin
idle_Special <= put_idle;
aout_Special[32] <= a_sign;
aout_Special[31:24] <= a_exponent+127;
aout_Special[23] <= 1'b1;
aout_Special[22:0] <= a_mantissa[22:0];
bout_Special[32] <= b_sign;
bout_Special[31:24] <= b_exponent+127;
bout_Special[23] <= 1'b1;
bout_Special[22:0] <= b_mantissa[22:0];
cout_Special[35] <= c_sign;
cout_Special[34:27] <= c_exponent+127;
cout_Special[26:0] <= c_mantissa[26:0];
zout_Special <= {a_sign ^ b_sign,8'd0,27'd0};
sout_Special <= {c_sign,c_exponent + 127,c_mantissa[25:3]};
//if b is zero return zero
end else if (($signed(b_exponent) == -127) && (b_mantissa == 0)) begin
aout_Special[32] <= a_sign;
aout_Special[31:24] <= a_exponent+127;
aout_Special[23] <= 1'b1;
aout_Special[22:0] <= a_mantissa[22:0];
bout_Special[32] <= b_sign;
bout_Special[31:24] <= b_exponent+127;
bout_Special[23] <= 1'b1;
bout_Special[22:0] <= b_mantissa[22:0];
cout_Special[35] <= c_sign;
cout_Special[35] <= c_sign;
cout_Special[34:27] <= c_exponent+127;
cout_Special[26:0] <= c_mantissa[26:0];
zout_Special <= {a_sign ^ b_sign,8'd0,27'd0};
sout_Special <= {c_sign,c_exponent + 127,c_mantissa[25:3]};
idle_Special <= put_idle;
// If mode is linear, return 0 for product
end else if (mode_Special == 2'b00) begin
idle_Special <= put_idle;
aout_Special[32] <= a_sign;
aout_Special[31:24] <= a_exponent+127;
aout_Special[23] <= 1'b1;
aout_Special[22:0] <= a_mantissa[22:0];
bout_Special[32] <= b_sign;
bout_Special[31:24] <= b_exponent+127;
bout_Special[23] <= 1'b1;
bout_Special[22:0] <= b_mantissa[22:0];
cout_Special[35] <= c_sign;
cout_Special[34:27] <= c_exponent+127;
cout_Special[26:0] <= c_mantissa[26:0];
zout_Special <= {a_sign ^ b_sign,8'd0,27'd0};
sout_Special <= {c_sign,c_exponent + 127,c_mantissa[25:3]};
end else begin
//Denormalised Number
cout_Special[35] <= c_sign;
cout_Special[34:27] <= c_exponent+127;
cout_Special[26:0] <= c_mantissa[26:0];
zout_Special <= 0;
sout_Special <= 0;
idle_Special <= no_idle;
if ($signed(a_exponent) == -127) begin
aout_Special <= {a_sign,-126,a_mantissa};
end else begin
aout_Special[32] <= a_sign;
aout_Special[31:24] <= a_exponent+127;
aout_Special[23] <= 1'b1;
aout_Special[22:0] <= a_mantissa[22:0];
end
//Denormalised Number
if ($signed(b_exponent) == -127) begin
bout_Special <= {b_sign,-126,b_mantissa};
end else begin
bout_Special[32] <= b_sign;
bout_Special[31:24] <= b_exponent+127;
bout_Special[23] <= 1'b1;
bout_Special[22:0] <= b_mantissa[22:0];
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long double a[1001][1001]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long n, t, m, w, b; cout.precision(12); cin >> w >> b; for (int i = 0; i <= w; i++) { for (int j = 0; j <= b; j++) { if (!i && !j) continue; long double x = i * 1.0; long double y = j * 1.0; a[i][j] = (x / (x + y)); long double z = (y - 2) / (x + y - 2); if ((i >= 0) && ((j - 3) >= 0)) { a[i][j] += (a[i][j - 3] * z * (y / (x + y)) * ((y - 1) / (x + y - 1))); } if (((i - 1) >= 0) && ((j - 2) >= 0)) { a[i][j] += (a[i - 1][j - 2] * (1 - z) * (y / (x + y)) * ((y - 1) / (x + y - 1))); } } } cout << fixed << a[w][b]; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 300000; vector<long long> st; void add(vector<long long>& st, int x, long long inc) { while (x < st.size()) { st[x] += inc; x |= x + 1; } } long long sum(const vector<long long>& st, int x) { long long s = 0; while (x >= 0) { s += st[x]; x = (x & (x + 1)) - 1; } return s; } void insert(int l, int r, long long p) { add(st, r + 1, -p); add(st, l, p); } int n, m, k; int l[maxn], r[maxn]; long long d[maxn]; pair<int, int> a[maxn]; long long p[maxn]; int main() { cin >> n >> m >> k; st.resize(n + 3); for (int i = 1; i <= n; i++) scanf( %I64d , &p[i]); for (int i = 1; i <= m; i++) { scanf( %d%d%I64d , &l[i], &r[i], &d[i]); } for (int i = 1; i <= k; i++) { int x, y; scanf( %d%d , &x, &y); a[i] = make_pair(x, -1); a[i + k] = make_pair(y + 1, 1); } sort(a + 1, a + 1 + 2 * k); int sta = 1, tot = 0; for (int i = 1; i <= m; i++) { while (sta <= 2 * k && a[sta].first == i) tot -= a[sta++].second; insert(l[i], r[i], d[i] * tot); } for (int i = 1; i <= n; i++) printf( %I64d , sum(st, i) + p[i]); } |
// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias'
//
// Simple bi-directional alias test.
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/);
initial begin
int tofind;
int aliases[$];
int found[$];
int id;
int i;
aliases = '{ 1, 4, 6, 8};
tofind = 6;
found = aliases.find with (item == 1);
found = aliases.find(j) with (j == tofind);
// And as function
aliases.find(i) with (i == tofind);
// No parenthesis
found = aliases.find with (item == i);
aliases.find with (item == i);
`ifdef VERILATOR
// No expression (e.g. x.randomize() with {})
// Hack until randomize() supported
found = aliases.sort() with {};
`endif
// Unique (array method)
id = 4;
found = aliases.find with (id);
found = aliases.find() with (item == id);
found = aliases.find(i) with (i == id);
i = aliases.or(v) with (v);
i = aliases.and(v) with (v);
i = aliases.xor(v) with (v);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND4_2_V
`define SKY130_FD_SC_HDLL__AND4_2_V
/**
* and4: 4-input AND.
*
* Verilog wrapper for and4 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__and4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and4_2 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and4_2 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND4_2_V
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 50; long long kol, sum, id, ans; string s; vector<long long> a; int main() { cin >> s; ans = 0; sum = 0; for (int i = 0; i < s.size(); i++) { if (s[i] == v ) { id += 1; if (i == s.size() - 1) { sum += id - 1; } } else { if (id != 0) { sum += id - 1; id = 0; } a.push_back(sum); kol += 1; } } if (a.size() == 0) { cout << 0; return 0; } for (int i = 0; i < a.size(); i++) { ans += a[i] * (sum - a[i]); } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; vector<int> s[100005]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, m, i, j, a, b; cin >> n >> m; if (n == 1 && m == 1) { cout << YES n << 1; } else if (n == 1 && m == 2) { cout << NO ; } else if (n == 2 && m == 1) { cout << NO ; } else if (n == 1 && m == 3) { cout << NO ; } else if (n == 3 && m == 1) { cout << NO ; } else if (n == 1 && m == 4) { cout << YES n ; cout << 2 4 1 3 ; } else if (n == 4 && m == 1) { cout << YES n ; cout << 2 n4 n1 n3 ; } else if (n == 2 && m == 2) { cout << NO ; } else if ((n == 2 && m == 3) || (n == 3 && m == 2)) { cout << NO ; } else if (n == 3 && m == 3) { cout << YES n ; cout << 6 1 8 n7 5 3 n2 9 4 ; } else if (n == 1 && m >= 5) { vector<int> res; for (i = 1; i <= m; i += 2) { res.push_back(i); } for (i = 2; i <= m; i += 2) { res.push_back(i); } cout << YES n ; for (i = 0; i < m; i++) { cout << res[i] << ; } } else if (n >= 5 && m == 1) { vector<int> res; for (i = 1; i <= n; i += 2) { res.push_back(i); } for (i = 2; i <= n; i += 2) { res.push_back(i); } cout << YES n ; for (i = 0; i < n; i++) { cout << res[i] << n ; } } else if (2 <= n && 4 <= m) { a = 1; for (i = 1; i <= n; i++) { for (j = 1; j <= m; j++) { s[i].push_back(a); a++; } } for (i = 2; i <= n; i += 2) { a = s[i][0]; b = s[i][1]; for (j = 0; j < m - 2; j++) { s[i][j] = s[i][j + 2]; } s[i][m - 2] = a; s[i][m - 1] = b; } for (i = 1; i < m; i += 2) { a = s[1][i]; for (j = 1; j <= n - 1; j++) { s[j][i] = s[j + 1][i]; } s[n][i] = a; } cout << YES n ; for (i = 1; i <= n; i++) { for (j = 0; j < m; j++) { cout << s[i][j] << ; } cout << n ; } } else { a = 1; for (i = 1; i <= n; i++) { for (j = 1; j <= m; j++) { s[i].push_back(a); a++; } } for (i = 1; i < m; i += 2) { a = s[1][i]; b = s[2][i]; for (j = 1; j <= n - 2; j++) { s[j][i] = s[j + 2][i]; } s[n - 1][i] = a; s[n][i] = b; } for (i = 2; i <= n; i += 2) { a = s[i][0]; for (j = 0; j < m - 1; j++) { s[i][j] = s[i][j + 1]; } s[i][m - 1] = a; } cout << YES n ; for (i = 1; i <= n; i++) { for (j = 0; j < m; j++) { cout << s[i][j] << ; } cout << n ; } } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21A_BEHAVIORAL_V
`define SKY130_FD_SC_HD__O21A_BEHAVIORAL_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__o21a (
X ,
A1,
A2,
B1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X, or0_out, B1 );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21A_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; const long long maxn = 2e5 + 10, inf = 4e18, mod = 1e9 + 7; const long double pi = 3.14159265359, eps = 1e-9; long long n, m; vector<long long> g[maxn], jj[3]; long long mk[maxn]; bool dfs(long long v, long long p = -1, long long dep = 1) { mk[v] = dep; vector<long long> be, sn; for (auto u : g[v]) { if (mk[u] != 0 && mk[u] < mk[v]) { if (u != p) be.push_back(u); continue; } if (mk[u] == 0 && dfs(u, v, dep + 1)) sn.push_back(u); } while (be.size() > 1) { jj[0].push_back(be.back()); be.pop_back(); jj[1].push_back(v); jj[2].push_back(be.back()); be.pop_back(); } while (sn.size() > 1) { jj[0].push_back(sn.back()); sn.pop_back(); jj[1].push_back(v); jj[2].push_back(sn.back()); sn.pop_back(); } long long add = 0; if (be.size()) { if (sn.size()) { jj[0].push_back(sn.back()); sn.pop_back(); jj[1].push_back(v); jj[2].push_back(be.back()); be.pop_back(); return 1; } add = be.back(); } else if (sn.size()) { add = sn.back(); } if (!add) return 1; if (p != -1) { jj[0].push_back(add); jj[1].push_back(v); jj[2].push_back(p); } return 0; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> m; long long v, u; while (m--) { cin >> v >> u; g[v].push_back(u); g[u].push_back(v); } for (int i = 1; i <= n; i++) { if (!mk[i]) dfs(i); } cout << jj[0].size() << endl; for (int i = 0; i < jj[0].size(); i++) { cout << jj[0][i] << << jj[1][i] << << jj[2][i] << endl; } return 0; } |
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_alu_out (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 31: 0] in_port;
input reset_n;
wire clk_en;
wire [ 31: 0] data_in;
wire [ 31: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {32 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:256000000 ) using namespace std; const int INF = 1000001000; const int mod = 1000 * 1000 * 1000 + 7; const int mod9 = 1000 * 1000 * 1000 + 9; const double PI = 3.1415926535897932; double sqr(double first) { return first * first; }; long double sqr(long double first) { return first * first; }; long long sqr(long long first) { return first * first; }; long long sqr(int first) { return first * 1LL * first; }; long long gcd(long long a, long long b) { while (b) a %= b, swap(a, b); return a; } long long bpm(long long a, long long n = -2, long long m = mod) { n = n >= 0 ? n : m + n; long long r = 1; while (n) { if (n & 1) r = (r * a) % m; a = (a * a) % m; n >>= 1; } return r; } long long dist(long long x1, long long y1, long long x2, long long y2) { return sqr(x1 - x2) + sqr(y1 - y2); } std::ostream& operator<<(std::ostream& os, pair<int, int> p) { return os << { << p.first << << p.second << } ; } const int N = 200005; long long a[N]; pair<long long, long long> b[N]; int main() { ios::sync_with_stdio(false); long long n, m, s, d; cin >> n >> m >> s >> d; for (int i = 0; i < n; i++) { cin >> a[i]; } sort(a, a + n); int nwn = -1; for (int i = 0; i < n; i++) { b[i] = {a[i], a[i]}; if (i && a[i] - a[i - 1] < s + 2) { b[nwn].second = b[i].first; } else { b[++nwn] = b[i]; } } n = nwn + 1; vector<pair<long long, long long> > res; long long pos = 0; for (int i = 0; i < n; i++) { long long next = b[i].first; long long runD = next - 1 - pos; bool err = false; if (runD < s) { err = true; } res.push_back({1, runD}); pos += runD; long long fin = b[i].second + 1; if (fin > m || fin - pos > d) { err = true; } res.push_back({0, fin - pos}); pos = fin; if (err) { pos = m; res.clear(); res.push_back({-1, 0}); break; } } if (pos != m) { res.push_back({1, m - pos}); } for (pair<int, int> d : res) { switch (d.first) { case -1: cout << IMPOSSIBLE n ; break; case 0: cout << JUMP << d.second << n ; break; case 1: cout << RUN << d.second << n ; break; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int gcd(int a, int b) { return a % b ? gcd(b, a % b) : b; } int lcm(int a, int b) { return a * b / gcd(a, b); } int prime(long long n) { if (n < 2) return 0; if (n == 2 || n == 3) return 1; if (n % 6 != 1 && n % 6 != 5) return 0; for (long long i = 5; i <= sqrt(n); i += 6) { if (n % i == 0 || n % (i + 2) == 0) return 0; } return 1; } int t, r, g, b; int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> t; while (t--) { cin >> r >> g >> b; int mx = max(b, max(r, g)); int ans = min((r + g + b) / 2, r + g + b - mx); cout << ans << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKINV_LP_V
`define SKY130_FD_SC_LP__CLKINV_LP_V
/**
* clkinv: Clock tree inverter.
*
* Verilog wrapper for clkinv with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__clkinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkinv_lp (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkinv_lp (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__clkinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKINV_LP_V
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int q; cin >> q; for (int d = 0; d < q; d++) { string s, t; cin >> s >> t; int n = s.size(); int m = t.size(); n = n % 2; m = m % 2; int y = abs(n - m); int j = 0; for (int i = y; i < s.size(); i++) { if (s[i] == t[j]) { j++; } else { i++; } if (j == t.size()) { break; } } if (j == t.size()) { cout << YES << n ; ; } else { cout << NO << n ; ; } } } |
#include <bits/stdc++.h> using namespace std; bool cmp(long long x, long long y) { return x > y; } int main() { long long n; cin >> n; string S; cin >> S; vector<long long> C; for (long long i = 0; i < n; i++) { long long x = S[i] - 0 ; if (x == 0 || x == 1) continue; else if (x == 2) C.push_back(2); else if (x == 3) C.push_back(3); else if (x == 4) C.push_back(2), C.push_back(2), C.push_back(3); else if (x == 5) C.push_back(5); else if (x == 6) C.push_back(5), C.push_back(3); else if (x == 7) C.push_back(7); else if (x == 8) C.push_back(7), C.push_back(2), C.push_back(2), C.push_back(2); else if (x == 9) C.push_back(7), C.push_back(3), C.push_back(3), C.push_back(2); } sort(C.begin(), C.end(), cmp); for (auto it : C) cout << it; } |
#include <bits/stdc++.h> #pragma GCC optimize( -O2 ) using namespace std; void err(istream_iterator<string> it) { cerr << endl; } template <typename T, typename... Args> void err(istream_iterator<string> it, T a, Args... args) { cerr << *it << = << a << t ; err(++it, args...); } template <typename T1, typename T2> ostream& operator<<(ostream& c, pair<T1, T2>& v) { c << ( << v.first << , << v.second << ) ; return c; } template <template <class...> class TT, class... T> ostream& operator<<(ostream& out, TT<T...>& c) { out << { ; for (auto& x : c) out << x << ; out << } ; return out; } const int LIM = 1e5 + 5, MOD = 998244353; int t, n, m, k, x, y, w; inline long long powm(long long x, long long pw, long long Mod = MOD) { x %= Mod; long long res = 1; while (pw) { if (pw & 1LL) res = ((res * x)) % Mod; pw >>= 1; x = ((x * x)) % Mod; } return res; } inline long long inv(long long x, long long Mod = MOD) { return powm(x, Mod - 2, Mod); } template <int mod> struct FWHT { vector<int> fwht(vector<int> P, bool inverse, bool nomod = 0) { int sz = P.size(); for (int len = 1; 2 * len <= sz; len <<= 1) { for (int i = 0; i < sz; i += 2 * len) { for (int j = 0; j < len; ++j) { int u = P[i + j]; int v = P[i + len + j]; if (nomod) { P[i + j] = (u + v); P[i + len + j] = (u - v); } else { P[i + j] = (u + v) % mod; P[i + len + j] = (u - v + mod) % mod; } } } } if (inverse) { long long iv = inv(sz, mod); for (int i = 0; i < sz; ++i) P[i] = P[i] * iv % mod; } return P; } vector<int> mult(vector<int> A, vector<int> B) { A = fwht(A, 0); B = fwht(B, 0); for (int i = 0; i < A.size(); ++i) A[i] = A[i] * 1LL * B[i] % mod; return fwht(A, 1); } vector<int> pow(vector<int> A, long long k) { A = fwht(A, 0); for (int i = 0; i < A.size(); ++i) A[i] = powm(A[i], k); return fwht(A, 1); } }; signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> k; int sz = (1 << k); vector<int> A(sz, 0), B(sz, 0), C(sz, 0), D(sz, 0); long long o1, o2, o3; cin >> o1 >> o2 >> o3; int totxor = 0; for (int i = 0; i < n; ++i) { cin >> x >> y >> w; totxor ^= x; y ^= x, w ^= x; A[y]++; B[w]++; C[y ^ w]++; } FWHT<MOD> f; A = f.fwht(A, 0, 1), B = f.fwht(B, 0, 1), C = f.fwht(C, 0, 1); for (int i = 0; i < sz; ++i) { int x1 = (n + A[i]) / 2, x2 = (n + B[i]) / 2, x3 = (n + C[i]) / 2; int a1 = (x1 + x2 + x3 - n) / 2, b1 = x2 - a1, c1 = x1 - a1, d1 = x3 - a1; D[i] = ((powm(o1 + o2 + o3, a1) * powm(o1 - o2 + o3 + MOD, b1) % MOD) * powm(o1 + o2 - o3 + MOD, c1) % MOD) * powm(o1 - o2 - o3 + MOD + MOD, d1) % MOD; } D = f.fwht(D, 1); for (int i = 0; i < sz; ++i) cout << D[i ^ totxor] << ; cout << n ; return 0; } |
#include <bits/stdc++.h> int M[50] = {0, 2, 3, 5, 7, 13, 17, 19, 31, 61, 89, 107, 127, 521, 607, 1279, 2203, 2281, 3217, 4253, 4423, 9689, 9941, 11213, 19937, 21701, 23209, 44497, 86243, 110503, 132049, 216091, 756839, 859433, 1257787, 1398269, 2976221, 3021377, 6972593, 13466917, 20996011}; int main(void) { int i, n, x = 1; scanf( %d , &n); for (i = 1; i < M[n]; i++) { x *= 2; x %= 1000000007; } printf( %d , (x + 1000000007 - 1) % 1000000007); } |
#include <bits/stdc++.h> using namespace std; const int oo = 0x3f3f3f3f; const double eps = 1e-9; int N, C; vector<int> c[6]; vector<pair<int, int> > cl; int seq[100008]; bool seen[100008]; struct Action { int len; int b[5]; int c[5]; }; vector<Action> act; void cycle2action(int c, int l, Action &a, int p) { a.c[p + l - 1] = a.b[p] = c; for (int i = (1); i < (l); ++i) { a.c[p + i - 1] = a.b[p + i] = seq[a.b[p + i - 1]]; } } int main() { cin >> N; for (int i = (1); i < (N + 1); ++i) cin >> seq[i]; fill_n(seen, N + 1, false); C = 0; for (int i = (1); i < (N + 1); ++i) if (!seen[i]) { seen[i] = true; if (seq[i] == i) continue; C++; int len = 1; for (int k = seq[i]; k != i; k = seq[k]) { seen[k] = true; len++; } if (len <= 5) { c[len].push_back(i); continue; } cl.push_back(pair<int, int>(i, len)); } while (C > 0) { while (!cl.empty()) { int l = cl.back().second; int k = cl.back().first; cl.pop_back(); Action a; a.len = 5; cycle2action(k, 5, a, 0); l -= 4; seq[a.c[4]] = seq[a.b[4]]; if (l > 5) cl.push_back(pair<int, int>(a.c[4], l)); else c[l].push_back(a.c[4]); act.push_back(a); } for (int l = (4); l < (6); ++l) { while (!c[l].empty()) { Action a; a.len = l; cycle2action(c[l].back(), l, a, 0); c[l].pop_back(); act.push_back(a); C--; continue; } } while (int((c[2]).size()) && int((c[3]).size())) { Action a; a.len = 5; cycle2action(c[2].back(), 2, a, 0); cycle2action(c[3].back(), 3, a, 2); c[2].pop_back(); c[3].pop_back(); act.push_back(a); C -= 2; continue; } while (int((c[2]).size()) >= 2) { Action a; a.len = 4; cycle2action(c[2].back(), 2, a, 0); c[2].pop_back(); cycle2action(c[2].back(), 2, a, 2); c[2].pop_back(); act.push_back(a); C -= 2; } if (int((c[3]).size()) >= 2) { Action a; a.len = 5; cycle2action(c[3].back(), 3, a, 0); c[3].pop_back(); int k = c[3].back(); c[3].pop_back(); int l = seq[k]; int m = seq[l]; a.b[3] = a.c[4] = k; a.b[4] = a.c[3] = m; swap(seq[k], seq[m]); c[2].push_back(l); act.push_back(a); C--; continue; } if (int((c[3]).size()) == 1) { Action a; a.len = 3; cycle2action(c[3].back(), 3, a, 0); c[3].pop_back(); act.push_back(a); C--; continue; } if (int((c[2]).size()) == 1) { Action a; a.len = 2; cycle2action(c[2].back(), 2, a, 0); c[2].pop_back(); act.push_back(a); C--; continue; } } cout << int((act).size()) << endl; for (__typeof__((act).begin()) a = (act).begin(); a != (act).end(); ++a) { cout << a->len << endl; for (int i = (0); i < (a->len); ++i) cout << (i ? : ) << a->b[i]; cout << endl; for (int i = (0); i < (a->len); ++i) cout << (i ? : ) << a->c[i]; cout << endl; } return 0; } |
/*
# DE0_Comm.v - Connect all the pieces, system clock, heartbeat LED, FSM
#
# Copyright (C) 2014 Binary Logic (nhi.phan.logic at gmail.com).
#
# This file is part of the Virtual JTAG UART toolkit
#
# Virtual UART is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
*/
//=======================================================
// DE0 Top Module
//=======================================================
`include "system_include.v"
module DE0_Comm(
//////////// CLOCK //////////
input CLOCK_50,
// Only included if we're running with ModelSim
`ifdef UNDER_TEST
// Async reset
input areset,
`endif
//////////// LED //////////
output [7:0] LED
);
//=======================================================
// REG/WIRE declarations
//=======================================================
// System signals
wire sysclk, reset_n;
// Heartbeat signals
wire heartbeat;
//=======================================================
// Outputs
//=======================================================
assign LED = {7'b0,heartbeat};
//=======================================================
// Structural coding
//=======================================================
// System clock
pll_clock clock (
.inclk0 ( CLOCK_50 ),
.c0 ( sysclk ),
// Only included if we're running with ModelSim
`ifdef UNDER_TEST
.areset( areset ),
`else
.areset(),
`endif
.locked ( )
);
// Reset timer
reset reset(
.clk_i( sysclk ),
.nreset_o( reset_n )
);
// Heartbeat function
heartbeat hb(
.clk_i( sysclk ),
.nreset_i( reset_n ),
.heartbeat_o( heartbeat )
);
// The finite state machine for sending data through JTAG
fsm_app app(
.clk_i(sysclk),
.nreset_i(reset_n)
);
//=======================================================
// Procedural coding
//=======================================================
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_TB_V
`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_TB_V
/**
* lpflow_isobufsrckapwr: Input isolation, noninverted sleep on
* keep-alive power rail.
*
* X = (!A | SLEEP)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__lpflow_isobufsrckapwr.v"
module top();
// Inputs are registered
reg SLEEP;
reg A;
reg KAPWR;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
KAPWR = 1'bX;
SLEEP = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 KAPWR = 1'b0;
#60 SLEEP = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 KAPWR = 1'b1;
#200 SLEEP = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 KAPWR = 1'b0;
#340 SLEEP = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 SLEEP = 1'b1;
#540 KAPWR = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 SLEEP = 1'bx;
#680 KAPWR = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_hd__lpflow_isobufsrckapwr dut (.SLEEP(SLEEP), .A(A), .KAPWR(KAPWR), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_TB_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Case Western Reserve University
// Engineer: Matt McConnell
//
// Create Date: 22:29:00 09/09/2017
// Project Name: EECS301 Digital Design
// Design Name: Lab #4 Project
// Module Name: Key_Synchronizer_Bank
// Target Devices: Altera Cyclone V
// Tool versions: Quartus v17.0
// Description: Key Synchronizer Bank
//
// Dependencies:
//
//////////////////////////////////////////////////////////////////////////////////
module Key_Synchronizer_Bank
#(
parameter KEY_SYNC_CHANNELS = 1,
parameter CLK_RATE_HZ = 50000000, // Hz
parameter KEY_LOCK_DELAY = 800000000 // 800 mS
)
(
// Input Signals
input [KEY_SYNC_CHANNELS-1:0] KEY,
// Output Signals
output [KEY_SYNC_CHANNELS-1:0] KEY_EVENT,
// System Signals
input CLK
);
//
// Key Input Synchronizers
//
genvar i;
generate
begin
for (i = 0; i < KEY_SYNC_CHANNELS; i=i+1)
begin : key_sync_gen
Key_Synchronizer_Module
#(
.CLK_RATE_HZ( CLK_RATE_HZ ),
.KEY_LOCK_DELAY( KEY_LOCK_DELAY )
)
key_synchronizer
(
// Input Signals
.KEY( KEY[i] ),
// Output Signals
.KEY_EVENT( KEY_EVENT[i] ),
// System Signals
.CLK( CLK )
);
end
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__TAP_TB_V
`define SKY130_FD_SC_HDLL__TAP_TB_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__tap.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_hdll__tap dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__TAP_TB_V
|
// Copyright 2007 Altera Corporation. All rights reserved.
// Altera products are protected under numerous U.S. and foreign patents,
// maskwork rights, copyrights and other intellectual property laws.
//
// This reference design file, and your use thereof, is subject to and governed
// by the terms and conditions of the applicable Altera Reference Design
// License Agreement (either as signed by you or found at www.altera.com). By
// using this reference design file, you indicate your acceptance of such terms
// and conditions between you and Altera Corporation. In the event that you do
// not agree with such terms and conditions, you may not use the reference
// design file and please promptly destroy any copies you have made.
//
// This reference design file is being provided on an "as-is" basis and as an
// accommodation and therefore all warranties, representations or guarantees of
// any kind (whether express, implied or statutory) including, without
// limitation, warranties of merchantability, non-infringement, or fitness for
// a particular purpose, are specifically disclaimed. By making this reference
// design file available, Altera expressly does not recommend, suggest or
// require that this reference design file be used in combination with any
// other product not provided by Altera.
/////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////
// baeckler - 08-24-2007
//
// Parameterized ternary CAM made from registers (no RAM)
//
// 1 tick read and write, 1hot match output
//
module reg_based_cam (
clk,rst,
waddr,wdata,wcare,wena,
lookup_data,match_lines
);
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 4;
parameter WORDS = (1<<ADDR_WIDTH);
input clk,rst;
input [ADDR_WIDTH-1:0] waddr;
input [DATA_WIDTH-1:0] wdata,wcare;
input wena;
input [DATA_WIDTH-1:0] lookup_data;
output [WORDS-1:0] match_lines;
wire [WORDS-1:0] match_lines;
// write decoder
wire [WORDS-1:0] word_wena;
reg [WORDS-1:0] waddr_dec;
always @(*) begin
waddr_dec = 0;
waddr_dec[waddr] = 1'b1;
end
assign word_wena = waddr_dec & {WORDS{wena}};
// writing "all don't care" disables the word.
wire wused = |wcare /*synthesis keep*/;
// storage and match cells
genvar i;
generate
for (i=0; i<WORDS; i=i+1)
begin : cw
reg_cam_cell c (
.clk(clk),
.rst(rst),
.wdata(wdata),
.wcare(wcare),
.wused(wused),
.wena(word_wena[i]),
.lookup_data(lookup_data),
.match(match_lines[i])
);
defparam c .DATA_WIDTH = DATA_WIDTH;
end
endgenerate
// match encoder
/*
integer k, j;
always @(*)
begin
j = 0;
for (k=0; k < 16; k=k+1)
if (match_lines[k] == 1'b1)
j = k;
encode_out = j;
enable_out = |{match_lines};
end
*/
endmodule
//////////////////////////////////////////
|
#include <bits/stdc++.h> using namespace std; const int N = 1000000; int z[N]; void computeZ(char s[]) { int n = strlen(s), L = 0, R = 0; for (int i = 1; i < n; i++) { if (i > R) { L = R = i; while (R < n && s[R - L] == s[R]) R++; z[i] = R - L; R--; } else { int k = i - L; if (z[k] < R - i + 1) z[i] = z[k]; else { L = i; while (R < n && s[R - L] == s[R]) R++; z[i] = R - L; R--; } } } } char s[N + 1]; int suffix[N + 1], size; int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> s; computeZ(s); int n = strlen(s), mx = 0; int size = 0; for (int i = 1; i < n; ++i) if (z[i] == n - i) suffix[z[i]]++; for (int i = 1; i < n; ++i) { if (suffix[i]) suffix[i] = i; else suffix[i] = suffix[i - 1]; } for (int i = 1; i < n; ++i) { int len = z[i] - (z[i] == n - i); mx = max(mx, suffix[len]); } if (mx == 0) cout << Just a legend << endl; else { s[mx] = 0 ; cout << s << endl; } } |
#include <bits/stdc++.h> using namespace std; inline long long Readint() { long long ret = 0; int f = 1; char ch; do { ch = getchar(); if (ch == - ) f *= -1; } while (ch >= 0 && (ch < 0 || ch > 9 )); while ( 0 <= ch && ch <= 9 ) { ret = ret * 10 + ch - 0 ; ch = getchar(); } return ret * f; } void open() { freopen( E.in , r , stdin); freopen( E.out , w , stdout); } void close() { fclose(stdin); fclose(stdout); } const int MAXN = 101010; set<int> sp[2]; char s[MAXN]; vector<int> ans; int n; void init() { int cntl = 0, cntr = 0; scanf( %s , s + 1); n = strlen(s + 1); for (int i = 1, _END_ = n; i <= _END_; i++) if (s[i] == L ) cntl++; else cntr++; if (cntl < cntr || (cntl == cntr && s[1] == R )) { for (int i = 1, _END_ = n; i <= _END_; i++) if (s[i] == L ) s[i] = R ; else s[i] = L ; } for (int i = 1, _END_ = n; i <= _END_; i++) if (s[i] == L ) sp[0].insert(i); else sp[1].insert(i); } void work() { int type = 0; set<int>::iterator now; int num = 0; int tot = 0; now = sp[0].begin(); num = *now; sp[0].erase(now); for (int i = 1, _END_ = n; i < _END_; i++) { ans.push_back(num); now = sp[type ^ 1].lower_bound(num); if (now == sp[type ^ 1].end()) { tot++; now = sp[type ^ 1].begin(); num = *now; sp[type ^ 1].erase(num); type ^= 1; } else { if (sp[type].lower_bound(*now) == sp[type].end()) { int mn = 0x3f3f3f3f; if (sp[0].begin() != sp[0].end()) mn = min(mn, *sp[0].begin()); if (sp[1].begin() != sp[1].end()) mn = min(mn, *sp[1].begin()); if (mn < num && s[mn] != s[num]) { tot++; num = mn; sp[type ^ 1].erase(num); type ^= 1; continue; } } num = *now; sp[type ^ 1].erase(num); type ^= 1; } } ans.push_back(num); printf( %d n , tot); for (int i = 0, _END_ = ans.size(); i < _END_; i++) printf( %d , ans[i]); } int main() { int _ = 0; init(); work(); close(); return 0; } |
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_axis_rate_limit_64;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [63:0] input_axis_tdata = 8'd0;
reg [7:0] input_axis_tkeep = 8'd0;
reg input_axis_tvalid = 1'b0;
reg input_axis_tlast = 1'b0;
reg input_axis_tuser = 1'b0;
reg output_axis_tready = 1'b0;
reg [7:0] rate_num = 0;
reg [7:0] rate_denom = 0;
reg rate_by_frame = 0;
// Outputs
wire input_axis_tready;
wire [63:0] output_axis_tdata;
wire [7:0] output_axis_tkeep;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready,
rate_num,
rate_denom,
rate_by_frame);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser);
// dump file
$dumpfile("test_axis_rate_limit_64.lxt");
$dumpvars(0, test_axis_rate_limit_64);
end
axis_rate_limit_64 #(
.DATA_WIDTH(64)
)
UUT (
.clk(clk),
.rst(rst),
// axi input
.input_axis_tdata(input_axis_tdata),
.input_axis_tkeep(input_axis_tkeep),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tuser(input_axis_tuser),
// axi output
.output_axis_tdata(output_axis_tdata),
.output_axis_tkeep(output_axis_tkeep),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser),
// configuration
.rate_num(rate_num),
.rate_denom(rate_denom),
.rate_by_frame(rate_by_frame)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:11:32 01/08/2017
// Design Name:
// Module Name: bullet
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module bullet(
input clk,
input rst,
input [10:0] x,
input [10:0] y,
input [10:0] poX,
input [10:0] poY,
input trigger,
input timer,
input d,
output reg bullet
);
parameter w = 4;
parameter s = 4;
reg [10:0] nowX, nowY;
reg start;
reg over;
always@(posedge clk ,posedge rst)
begin
if(rst)start<=0;
else if(trigger)start<=1;
else start<=start;
end
// over
always@(posedge clk, posedge rst)
begin
if(rst) over <= 0;
else begin
if(d) begin // right
if(start && nowX > 904) over <= 1;
else over <= over;
end
else begin // left
if(start && nowX < 104 && nowX>0) over <= 1;
else over <= over;
end
end
end
// nowX
always@(posedge clk, posedge rst)
begin
if(rst) nowX <= 0;
else begin
if(trigger) nowX <= poX;
else if(timer) begin
if(start) nowX <= (d)? nowX+w : nowX-w;
else nowX <= nowX;
end
else nowX <= nowX;
end
end
// nowX
always@(posedge clk, posedge rst)
begin
if(rst) nowY <= 0;
else begin
if(trigger) nowY <= poY;
else nowY <= nowY;
end
end
// bullet
always@(posedge clk, posedge rst)
begin
if(rst) bullet <= 0;
else begin
if(over) bullet <= 0;
else if(d &&start && x < nowX+w+36 && x > nowX+36 && y < nowY+w+20 && y > nowY+20) bullet <= 1;
else if(!d && start && x < nowX+w && x > nowX && y < nowY+w+20 && y > nowY+20) bullet <= 1;
else bullet <= 0;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__FILL_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__FILL_BEHAVIORAL_V
/**
* fill: Fill cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__fill ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__FILL_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__HA_BLACKBOX_V
`define SKY130_FD_SC_LS__HA_BLACKBOX_V
/**
* ha: Half adder.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__ha (
COUT,
SUM ,
A ,
B
);
output COUT;
output SUM ;
input A ;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__HA_BLACKBOX_V
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: iodelay_ctrl.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:34:56 $
// \ \ / \ Date Created: Wed Aug 16 2006
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
// This module instantiates the IDELAYCTRL primitive, which continously
// calibrates the IODELAY elements in the region to account for varying
// environmental conditions. A 200MHz or 300MHz reference clock (depending
// on the desired IODELAY tap resolution) must be supplied
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: iodelay_ctrl.v,v 1.1 2011/06/02 08:34:56 mishra Exp $
**$Date: 2011/06/02 08:34:56 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/clocking/iodelay_ctrl.v,v $
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v2_0_iodelay_ctrl #
(
parameter TCQ = 100,
// clk->out delay (sim only)
parameter IODELAY_GRP = "IODELAY_MIG",
// May be assigned unique name when
// multiple IP cores used in design
parameter REFCLK_TYPE = "DIFFERENTIAL",
// Reference clock type
// "DIFFERENTIAL","SINGLE_ENDED"
// NO_BUFFER, USE_SYSTEM_CLOCK
parameter SYSCLK_TYPE = "DIFFERENTIAL",
// input clock type
// DIFFERENTIAL, SINGLE_ENDED,
// NO_BUFFER
parameter SYS_RST_PORT = "FALSE",
// "TRUE" - if pin is selected for sys_rst
// and IBUF will be instantiated.
// "FALSE" - if pin is not selected for sys_rst
parameter RST_ACT_LOW = 1,
// Reset input polarity
// (0 = active high, 1 = active low)
parameter DIFF_TERM_REFCLK = "TRUE"
// Differential Termination
)
(
input clk_ref_p,
input clk_ref_n,
input clk_ref_i,
input sys_rst,
output clk_ref,
output sys_rst_o,
output iodelay_ctrl_rdy
);
// # of clock cycles to delay deassertion of reset. Needs to be a fairly
// high number not so much for metastability protection, but to give time
// for reset (i.e. stable clock cycles) to propagate through all state
// machines and to all control signals (i.e. not all control signals have
// resets, instead they rely on base state logic being reset, and the effect
// of that reset propagating through the logic). Need this because we may not
// be getting stable clock cycles while reset asserted (i.e. since reset
// depends on DCM lock status)
// COMMENTED, RC, 01/13/09 - causes pack error in MAP w/ larger #
localparam RST_SYNC_NUM = 15;
// localparam RST_SYNC_NUM = 25;
wire clk_ref_bufg;
wire clk_ref_ibufg;
wire rst_ref;
reg [RST_SYNC_NUM-1:0] rst_ref_sync_r /* synthesis syn_maxfan = 10 */;
wire rst_tmp_idelay;
wire sys_rst_act_hi;
//***************************************************************************
// If the pin is selected for sys_rst in GUI, IBUF will be instantiated.
// If the pin is not selected in GUI, sys_rst signal is expected to be
// driven internally.
generate
if (SYS_RST_PORT == "TRUE")
IBUF u_sys_rst_ibuf
(
.I (sys_rst),
.O (sys_rst_o)
);
else
assign sys_rst_o = sys_rst;
endgenerate
// Possible inversion of system reset as appropriate
assign sys_rst_act_hi = RST_ACT_LOW ? ~sys_rst_o: sys_rst_o;
//***************************************************************************
// 1) Input buffer for IDELAYCTRL reference clock - handle either a
// differential or single-ended input. Global clock buffer is used to
// drive the rest of FPGA logic.
// 2) For NO_BUFFER option, Reference clock will be driven from internal
// clock i.e., clock is driven from fabric. Input buffers and Global
// clock buffers will not be instaitaed.
// 3) For USE_SYSTEM_CLOCK, input buffer output of system clock will be used
// as the input reference clock. Global clock buffer is used to drive
// the rest of FPGA logic.
//***************************************************************************
generate
if (REFCLK_TYPE == "DIFFERENTIAL") begin: diff_clk_ref
IBUFGDS #
(
.DIFF_TERM (DIFF_TERM_REFCLK),
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_clk_ref
(
.I (clk_ref_p),
.IB (clk_ref_n),
.O (clk_ref_ibufg)
);
BUFG u_bufg_clk_ref
(
.O (clk_ref_bufg),
.I (clk_ref_ibufg)
);
end else if (REFCLK_TYPE == "SINGLE_ENDED") begin : se_clk_ref
IBUFG #
(
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_clk_ref
(
.I (clk_ref_i),
.O (clk_ref_ibufg)
);
BUFG u_bufg_clk_ref
(
.O (clk_ref_bufg),
.I (clk_ref_ibufg)
);
end else if ((REFCLK_TYPE == "NO_BUFFER") ||
(REFCLK_TYPE == "USE_SYSTEM_CLOCK" && SYSCLK_TYPE == "NO_BUFFER")) begin : clk_ref_noibuf_nobuf
assign clk_ref_bufg = clk_ref_i;
end else if (REFCLK_TYPE == "USE_SYSTEM_CLOCK" && SYSCLK_TYPE != "NO_BUFFER") begin : clk_ref_noibuf
BUFG u_bufg_clk_ref
(
.O (clk_ref_bufg),
.I (clk_ref_i)
);
end
endgenerate
//***************************************************************************
// Global clock buffer for IDELAY reference clock
//***************************************************************************
assign clk_ref = clk_ref_bufg;
//*****************************************************************
// IDELAYCTRL reset
// This assumes an external clock signal driving the IDELAYCTRL
// blocks. Otherwise, if a PLL drives IDELAYCTRL, then the PLL
// lock signal will need to be incorporated in this.
//*****************************************************************
// Add PLL lock if PLL drives IDELAYCTRL in user design
assign rst_tmp_idelay = sys_rst_act_hi;
always @(posedge clk_ref_bufg or posedge rst_tmp_idelay)
if (rst_tmp_idelay)
rst_ref_sync_r <= #TCQ {RST_SYNC_NUM{1'b1}};
else
rst_ref_sync_r <= #TCQ rst_ref_sync_r << 1;
assign rst_ref = rst_ref_sync_r[RST_SYNC_NUM-1];
//*****************************************************************
(* IODELAY_GROUP = IODELAY_GRP *) IDELAYCTRL u_idelayctrl
(
.RDY (iodelay_ctrl_rdy),
.REFCLK (clk_ref_bufg),
.RST (rst_ref)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N_MAX = 1e9, MAX = 4000001, MOD = 1000000007; int t, n, k, ans[200001]; vector<int> cnt[200001]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> t; while (t--) { cin >> n >> k; int sum = 0; fill(ans, ans + n + 1, 0); for (int i = 0; i < n + 1; i++) cnt[i].clear(); for (int i = 0; i < n; i++) { int a; cin >> a; if (cnt[a].size() < k) cnt[a].push_back(i); } int curr = 1, aa = 0; for (int i = 1; i <= n; i++) { aa += cnt[i].size(); } aa -= aa % k; for (int i = 1; i <= n; i++) { int s = min(k, (int)cnt[i].size()); for (int j = 0; j < s; j++) { ans[cnt[i][j]] = curr; curr = curr % k + 1; aa--; if (aa == 0) break; } if (aa == 0) break; } for (int i = 0; i < n; i++) { cout << ans[i] << ; } cout << n ; } } |
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module sizetest(input clock,
input reset,
input enable,
input [15:0]xi,
input [15:0] yi,
input [15:0] zi,
output [15:0] xo,
output [15:0] yo,
output [15:0] zo
// input [15:0] constant
);
wire [16:0] zo;
cordic_stage cordic_stage(clock, reset, enable, xi, yi, zi, 16'd16383, xo, yo, zo );
endmodule
|
#include <bits/stdc++.h> using namespace std; int v[361 * 2], acum[360 * 2]; int main() { int n, tmp; cin >> n; for (int i = 0; i < n; i++) { cin >> v[i]; v[i + n] = v[i]; } int ans = (1 << 20); for (int i = 0; i < n; i++) { for (int j = i; j < i + n; j++) { int acum1 = 0, acum2 = 0; for (int k = i; k < i + n; k++) { if (k < j) acum1 += v[k]; else acum2 += v[k]; } ans = min(ans, abs(acum1 - acum2)); } } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int off = 1 << 18; const int MOD = 1e9 + 7; int q, n = 1; int st[off << 1] = {}, sp[off], st2[off << 1]; vector<int> g[200001]; int qt[200000], qv[200000], qval[200000], ch[200001] = {}; int tin[200001], tout[200001], timer = -1, par[200001]; void dfs(int v) { tin[v] = ++timer; for (int to : g[v]) { dfs(to); } tout[v] = timer; } void stBuild() { for (int i = off - 1; i >= 1; --i) { st[i] = st[2 * i] + st[2 * i + 1]; sp[i] = 1; } for (int i = 0; i < (int)(2 * off); ++i) st2[i] = 1; } void stPush(int v) { for (int i = 2 * v; i <= 2 * v + 1; ++i) { st[i] = (long long)st[i] * sp[v] % MOD; if (i < off) { sp[i] = (long long)sp[i] * sp[v] % MOD; } } sp[v] = 1; } int mul; void stMul(int v, int L, int R, int l, int r) { if (L == l && R == r) { st[v] = (long long)st[v] * mul % MOD; if (L != R) sp[v] = (long long)sp[v] * mul % MOD; return; } int mid = (L + R) >> 1; if (sp[v] != 1) { stPush(v); } if (l <= mid) stMul(2 * v, L, mid, l, min(r, mid)); if (r > mid) stMul(2 * v + 1, mid + 1, R, max(l, mid + 1), r); st[v] = st[2 * v] + st[2 * v + 1]; if (st[v] >= MOD) st[v] -= MOD; } int pos, val; void stAssign(int v, int L, int R) { if (L == R) { st[v] = val; return; } int mid = (L + R) >> 1; if (sp[v] != 1) { stPush(v); } if (pos <= mid) stAssign(2 * v, L, mid); else stAssign(2 * v + 1, mid + 1, R); st[v] = st[2 * v] + st[2 * v + 1]; if (st[v] >= MOD) st[v] -= MOD; } int stGet(int v, int L, int R, int l, int r) { if (l > r) return 0; if (L == l && R == r) { return st[v]; } int mid = (L + R) >> 1; if (sp[v] != 1) { stPush(v); } int res = stGet(2 * v, L, mid, l, min(r, mid)) + stGet(2 * v + 1, mid + 1, R, max(l, mid + 1), r); if (res >= MOD) res -= MOD; return res; } void st2Mul(int v, int L, int R, int l, int r) { if (L == l && R == r) { st2[v] = (long long)st2[v] * mul % MOD; return; } int mid = (L + R) >> 1; if (l <= mid) st2Mul(2 * v, L, mid, l, min(r, mid)); if (r > mid) st2Mul(2 * v + 1, mid + 1, R, max(l, mid + 1), r); } int st2Get(int pos) { int res = 1; for (pos += off; pos >= 1; pos >>= 1) { res = (long long)res * st2[pos] % MOD; } return res; } int binPow(long long x, int p) { long long res = 1; while (p) { if (p & 1) res = res * x % MOD; p >>= 1; if (p) x = x * x % MOD; } return (int)res; } int main() { scanf( %d%d , st + off, &q); for (int i = 0; i < (int)(q); ++i) { scanf( %d%d , qt + i, qv + i), --qv[i]; if (qt[i] == 1) { scanf( %d , qval + i); g[qv[i]].push_back(n); par[n++] = qv[i]; } } dfs(0); stBuild(); n = 1; for (int i = 0; i < (int)(q); ++i) { if (qt[i] == 1) { val = (long long)st2Get(tin[qv[i]]) * qval[i] % MOD; pos = tin[n++]; stAssign(1, 0, off - 1); mul = (long long)(ch[qv[i]] + 2) * binPow(ch[qv[i]] + 1, MOD - 2) % MOD; ++ch[qv[i]]; stMul(1, 0, off - 1, tin[qv[i]], tout[qv[i]]); st2Mul(1, 0, off - 1, tin[qv[i]], tout[qv[i]]); } else { int res = stGet(1, 0, off - 1, tin[qv[i]], tout[qv[i]]); if (qv[i] != 0) { res = (long long)res * binPow(st2Get(tin[par[qv[i]]]), MOD - 2) % MOD; } printf( %d n , res); } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 250; int t, a[N]; void read_input() { for (int i = 0; i < N; i++) cin >> a[i]; } void solve() { int sum = 0; for (int i = 0; i < N; i++) sum += a[i] * a[i]; double P = sqrt(1. * sum / N); for (int i = 0; i < N; i++) if (abs(a[i]) > 2 * P) { cout << poisson n ; return; } cout << uniform n ; } int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); for (cin >> t; t--; read_input(), solve()) ; return 0; } |
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module bd_350b_slot_0_b_0 (
In0,
In1,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
output wire [1 : 0] dout;
xlconcat_v2_1_1_xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(2),
.NUM_PORTS(2)
) inst (
.In0(In0),
.In1(In1),
.In2(1'B0),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { unsigned long long y = 0; unsigned int x = 0; int i; string s; cin >> s; if (s.length() > 19) printf( BigInteger n ); else if (s.length() > 10) { y = 0; for (i = 0; i < s.length(); i++) { if (y > 0) y *= 10; y += s[i] - 0 ; } if (y > 9223372036854775807) printf( BigInteger n ); else printf( long n ); } else if (s.length() > 5) { y = 0; for (i = 0; i < s.length(); i++) { if (y > 0) y *= 10; y += s[i] - 0 ; } if (y > 2147483647) printf( long n ); else printf( int n ); } else if (s.length() > 3) { y = 0; for (i = 0; i < s.length(); i++) { if (y > 0) y *= 10; y += s[i] - 0 ; } if (y > 32767) printf( int n ); else printf( short n ); } else if (s.length() > 0) { y = 0; for (i = 0; i < s.length(); i++) { if (y > 0) y *= 10; y += s[i] - 0 ; } if (y > 127) printf( short n ); else printf( byte n ); } else printf( byte n ); } |
module alu( input [7:0] ctrl,
input [31:0] A,
input [31:0] B,
input [4:0] SH,
output [31:0] Y );
// ctrl [7]: Signed operation (e.g. SLT/SLTU)
// ctrl [6]: SHIFT SRC (1 - reg, 0 - shamt)
// ctrl[5:4]: SHIFT OP
// ctrl [3]: NEGATE B
// ctrl[2:0]: ALU OP
//sign or zero-extension bits:
wire AE_bit = ctrl[7] ? A[31] : 1'b0;
wire BE_bit = ctrl[7] ? B[31] : 1'b0;
wire [32:0] op_A = {AE_bit, A};
wire [32:0] op_B = {BE_bit, B};
wire Cin = ctrl[3]; //carry in. Equals 1 when B = NEGATE(B)
wire [32:0] op_BN = Cin ? ~op_B : op_B; //inverted or not B
wire [32:0] Sum = op_A + op_BN + Cin;
wire [4:0] shamt;
mux2 #(5) shift_in_mux( .S (ctrl[6]),
.D0(SH),
.D1(A[4:0]),
.Y (shamt));
wire[31:0] sh_out;
shifter shifter_unit( .S(ctrl[5:4]),
.N( shamt ),
.A( B ),
.Y( sh_out ) );
wire [31:0] Zero_extend = {31'b0, Sum[32]};
mux8 out_mux( .S ( ctrl[2:0] ),
.D0( A & B ),
.D1( A | B ),
.D2( A ^ B ),
.D3(~(A | B) ),
.D4( Sum[31:0] ),
.D5( 0 ), //mul?
.D6( sh_out ),
.D7( Zero_extend ),
.Y ( Y ) );
endmodule
//-------------------------------------------------------------------------//
module shifter( input [1:0] S,
input [4:0] N,
input signed [31:0] A,
output [31:0] Y );
//sel[1]: 0 -- logical, 1 -- arithmetic
//sel[0]: 0 -- left, 1 --right
assign Y = S[1] ? (S[0] ? A >>> N : A <<< N) :
(S[0] ? A >> N : A << N);
endmodule
//-------------------------------------------------------------------------//
/*
//-------------------------NORMAL-ADDER------------------------------//
module qqq_sum( input[31:0] A, B,
output[31:0] R,
input Cin );
//assign {Cout, R} = A + B + Cin;
assign R = A + B + Cin;
endmodule
//-------------------------RIPPLE-CARRY-ADDER------------------------------//
module rca_sum( input[31:0] A, B,
output[31:0] R,
input Cin,
output Cout );
wire c0, c1, c2, c3, c4, c5, c6, c7,
c8, c9, c10, c11, c12, c13, c14, c15,
c16, c17, c18, c19, c20, c21, c22, c23,
c24, c25, c26, c27, c28, c29, c30;
full_adder fa0(A[ 0], B[ 0], R[ 0], Cin, c0);
full_adder fa1(A[ 1], B[ 1], R[ 1], c0, c1);
full_adder fa2(A[ 2], B[ 2], R[ 2], c1, c2);
full_adder fa3(A[ 3], B[ 3], R[ 3], c2, c3);
full_adder fa4(A[ 4], B[ 4], R[ 4], c3, c4);
full_adder fa5(A[ 5], B[ 5], R[ 5], c4, c5);
full_adder fa6(A[ 6], B[ 6], R[ 6], c5, c6);
full_adder fa7(A[ 7], B[ 7], R[ 7], c6, c7);
full_adder fa8(A[ 8], B[ 8], R[ 8], c7, c8);
full_adder fa9(A[ 9], B[ 9], R[ 9], c8, c9);
full_adder fa10(A[10], B[10], R[10], c9, c10);
full_adder fa11(A[11], B[11], R[11], c10, c11);
full_adder fa12(A[12], B[12], R[12], c11, c12);
full_adder fa13(A[13], B[13], R[13], c12, c13);
full_adder fa14(A[14], B[14], R[14], c13, c14);
full_adder fa15(A[15], B[15], R[15], c14, c15);
full_adder fa16(A[16], B[16], R[16], c15, c16);
full_adder fa17(A[17], B[17], R[17], c16, c17);
full_adder fa18(A[18], B[18], R[18], c17, c18);
full_adder fa19(A[19], B[19], R[19], c18, c19);
full_adder fa20(A[20], B[20], R[20], c19, c20);
full_adder fa21(A[21], B[21], R[21], c20, c21);
full_adder fa22(A[22], B[22], R[22], c21, c22);
full_adder fa23(A[23], B[23], R[23], c22, c23);
full_adder fa24(A[24], B[24], R[24], c23, c24);
full_adder fa25(A[25], B[25], R[25], c24, c25);
full_adder fa26(A[26], B[26], R[26], c25, c26);
full_adder fa27(A[27], B[27], R[27], c26, c27);
full_adder fa28(A[28], B[28], R[28], c27, c28);
full_adder fa29(A[29], B[29], R[29], c28, c29);
full_adder fa30(A[30], B[30], R[30], c29, c30);
full_adder fa31(A[31], B[31], R[31], c30, Cout);
endmodule
//-------------------------------------------------------------------------//
//--------------------------------------FULL ADDER-------------------------//
module full_adder( input A, B,
output S,
input Cin,
output Cout );
assign S = A ^ B ^ Cin;
assign Cout = (A & B) | (A & Cin) | (B & Cin);
endmodule */ |
Subsets and Splits