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#include <bits/stdc++.h> using namespace std; template <typename T> inline void chkmin(T &x, T y) { if (y < x) x = y; } template <typename T> inline void chkmax(T &x, T y) { if (y > x) x = y; } template <typename T> inline T add(T x, T y) { return (x + y) % 1000000007; } template <typename T> inline T mul(T x, T y) { return 1LL * x * y % 1000000007; } template <typename T> inline T qp(T x, T n) { T ans = 1; do { if (n & 1) ans = mul(ans, x); x = mul(x, x); } while (n >>= 1); return ans; } const int SZ = 1 << 13; char buff[SZ], *pos = buff + SZ - 1; inline long long read() { long long x = 0; int f = 1, c = (++pos == buff + SZ ? fread(pos = buff, 1, SZ, stdin), *pos : *pos); for (; !isdigit(c); c = (++pos == buff + SZ ? fread(pos = buff, 1, SZ, stdin), *pos : *pos)) if (c == - ) f = -f; for (; isdigit(c); c = (++pos == buff + SZ ? fread(pos = buff, 1, SZ, stdin), *pos : *pos)) x = (x << 3) + (x << 1) + (c ^ 48); return x * f; } int n, m; int k; int a[105][105]; int dis[205][205]; int prvv[205][205]; int dp[205][1 << 7]; pair<pair<int, int>, pair<pair<int, int>, pair<int, int> > > prv[205][1 << 7]; int xx[15], yy[15]; char anss[105][105]; void print_path(int sx, int sy, int ex, int ey) { while (ex != sx || ey != sy) { anss[ex][ey] = X ; int xxx = prvv[sx * m + sy][ex * m + ey]; ex = xxx / m, ey = xxx % m; } anss[ex][ey] = X ; } void printans(int xy, int msk) { int x = xy / m, y = xy % m; if (__builtin_popcount(msk) == 1) { int lst = __builtin_ctz(msk); print_path(x, y, xx[lst], yy[lst]); return; } print_path(prv[xy][msk].second.first.first, prv[xy][msk].second.first.second, prv[xy][msk].second.second.first, prv[xy][msk].second.second.second); printans( prv[xy][msk].second.first.first * m + prv[xy][msk].second.first.second, prv[xy][msk].first.first); printans( prv[xy][msk].second.second.first * m + prv[xy][msk].second.second.second, prv[xy][msk].first.second); } const int dx[] = {0, 0, -1, 1}; const int dy[] = {-1, 1, 0, 0}; int main() { n = read(), m = read(), k = read(); for (int i = 0; i < (int)(n); ++i) for (int j = 0; j < (int)(m); ++j) a[i][j] = read(); for (int i = 0; i < (int)(k); ++i) xx[i] = read() - 1, yy[i] = read() - 1; memset(dis, 0x3f, sizeof dis); for (int sx = 0; sx < (int)(n); ++sx) for (int sy = 0; sy < (int)(m); ++sy) { priority_queue<pair<int, pair<int, int> >, vector<pair<int, pair<int, int> > >, greater<pair<int, pair<int, int> > > > pq; pq.push(make_pair(a[sx][sy], make_pair(sx, sy))); dis[sx * m + sy][sx * m + sy] = a[sx][sy]; while (!pq.empty()) { pair<int, pair<int, int> > p = pq.top(); pq.pop(); int x = p.second.first, y = p.second.second; for (int i = 0; i < (int)(4); ++i) { int nx = x + dx[i], ny = y + dy[i]; if (nx < 0 || ny < 0 || nx >= n || ny >= m) continue; if (dis[sx * m + sy][nx * m + ny] > dis[sx * m + sy][x * m + y] + a[nx][ny]) { dis[sx * m + sy][nx * m + ny] = dis[sx * m + sy][x * m + y] + a[nx][ny]; prvv[sx * m + sy][nx * m + ny] = x * m + y; pq.push( make_pair(dis[sx * m + sy][nx * m + ny], make_pair(nx, ny))); } } } } memset(dp, 0x3f, sizeof dp); for (int ij = 0; ij < (int)(n * m); ++ij) for (int l = 0; l < (int)(k); ++l) dp[ij][1 << l] = dis[ij][xx[l] * m + yy[l]]; for (int msk = 0; msk < (int)(1 << k); ++msk) if (__builtin_popcount(msk) > 1) { for (int i = 0; i < (int)(n * m); ++i) { for (int msk1 = (msk - 1) & msk; msk1; msk1 = (msk1 - 1) & msk) { int msk2 = msk ^ msk1; for (int j = 0; j < (int)(n * m); ++j) { if (dp[i][msk] > dp[i][msk1] + dp[j][msk2] + dis[i][j] - a[i / m][i % m] - a[j / m][j % m]) { dp[i][msk] = dp[i][msk1] + dp[j][msk2] + dis[i][j] - a[i / m][i % m] - a[j / m][j % m]; prv[i][msk] = make_pair( make_pair(msk1, msk2), make_pair(make_pair(i / m, i % m), make_pair(j / m, j % m))); } if (dp[i][msk] > dp[j][msk1] + dp[i][msk2] + dis[i][j] - a[i / m][i % m] - a[j / m][j % m]) { dp[i][msk] = dp[j][msk1] + dp[i][msk2] + dis[i][j] - a[i / m][i % m] - a[j / m][j % m]; prv[i][msk] = make_pair( make_pair(msk1, msk2), make_pair(make_pair(j / m, j % m), make_pair(i / m, i % m))); } } } } } int ans = 1e9; int ansxy; for (int i = 0; i < (int)(n * m); ++i) if (dp[i][(1 << k) - 1] < ans) ans = dp[i][(1 << k) - 1], ansxy = i; for (int i = 0; i < (int)(n); ++i) for (int j = 0; j < (int)(m); ++j) anss[i][j] = . ; printf( %d n , ans); printans(ansxy, (1 << k) - 1); for (int i = 0; i < (int)(n); ++i) for (int j = 0; j < (int)(m); ++j) { printf( %c , anss[i][j]); if (j + 1 == m) puts( ); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAPVGND_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__TAPVGND_PP_BLACKBOX_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection
* 1 row down.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__tapvgnd (
VPWR,
VGND
);
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAPVGND_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e3 + 7; int n; int a[maxn], b[maxn]; long long solve() { long long res = 0; for (int i = 0; i < int(n); i++) { long long sa = 0, sb = 0; for (int j = i; j < int(n); j++) { sa |= a[j]; sb |= b[j]; res = max(res, sa + sb); } } return res; } int main() { scanf( %d , &n); for (int i = 0; i < int(n); i++) scanf( %d , &a[i]); for (int i = 0; i < int(n); i++) scanf( %d , &b[i]); printf( %lld n , solve()); return 0; } |
module BoothPPG_32R4(a ,b, sign,
i, pp0, pp1, pp2, pp3,
pp4, pp5, pp6, pp7,
pp8, pp9, pp10, pp11,
pp12, pp13, pp14, pp15,
pp16);
input wire[31:0] a;
input wire[31:0] b;
input wire sign;
output wire[15:0] i;
output wire[33:0] pp0;
output wire[33:0] pp1;
output wire[33:0] pp2;
output wire[33:0] pp3;
output wire[33:0] pp4;
output wire[33:0] pp5;
output wire[33:0] pp6;
output wire[33:0] pp7;
output wire[33:0] pp8;
output wire[33:0] pp9;
output wire[33:0] pp10;
output wire[33:0] pp11;
output wire[33:0] pp12;
output wire[33:0] pp13;
output wire[33:0] pp14;
output wire[33:0] pp15;
output wire[31:0] pp16;
assign i[15:0] = {b[31], b[29], b[27], b[25], b[23], b[21], b[19], b[17], b[15], b[13], b[11], b[9], b[7], b[5], b[3], b[1]};
BoothPPG_32R4_NORM ppg0( .mulcand(a), .r4input({b[1:0],1'b0}), .sign(sign), .pp(pp0));
BoothPPG_32R4_NORM ppg1( .mulcand(a), .r4input(b[3:1]), .sign(sign), .pp(pp1));
BoothPPG_32R4_NORM ppg2( .mulcand(a), .r4input(b[5:3]), .sign(sign), .pp(pp2));
BoothPPG_32R4_NORM ppg3( .mulcand(a), .r4input(b[7:5]), .sign(sign), .pp(pp3));
BoothPPG_32R4_NORM ppg4( .mulcand(a), .r4input(b[9:7]), .sign(sign), .pp(pp4));
BoothPPG_32R4_NORM ppg5( .mulcand(a), .r4input(b[11:9]), .sign(sign), .pp(pp5));
BoothPPG_32R4_NORM ppg6( .mulcand(a), .r4input(b[13:11]), .sign(sign), .pp(pp6));
BoothPPG_32R4_NORM ppg7( .mulcand(a), .r4input(b[15:13]), .sign(sign), .pp(pp7));
BoothPPG_32R4_NORM ppg8( .mulcand(a), .r4input(b[17:15]), .sign(sign), .pp(pp8));
BoothPPG_32R4_NORM ppg9( .mulcand(a), .r4input(b[19:17]), .sign(sign), .pp(pp9));
BoothPPG_32R4_NORM ppg10(.mulcand(a), .r4input(b[21:19]), .sign(sign), .pp(pp10));
BoothPPG_32R4_NORM ppg11(.mulcand(a), .r4input(b[23:21]), .sign(sign), .pp(pp11));
BoothPPG_32R4_NORM ppg12(.mulcand(a), .r4input(b[25:23]), .sign(sign), .pp(pp12));
BoothPPG_32R4_NORM ppg13(.mulcand(a), .r4input(b[27:25]), .sign(sign), .pp(pp13));
BoothPPG_32R4_NORM ppg14(.mulcand(a), .r4input(b[29:27]), .sign(sign), .pp(pp14));
BoothPPG_32R4_NORM ppg15(.mulcand(a), .r4input(b[31:29]), .sign(sign), .pp(pp15));
BoothPPG_32R4_MSB ppg16(.mulcand(a), .msb(b[31]), .sign(sign), .pp(pp16));
endmodule
|
// modelling dma_sequencer.v together with dma_access.v
`define NO_CPU
module tb;
parameter DEVNUM = 4;
integer i,j,k;
tri1 iorq_n,mreq_n,rd_n,wr_n;
reg clk,rst_n;
tri0 busrq_n,busak_n;
trireg [15:0] zaddr;
tri [7:0] zdata;
wire dma_req,dma_rnw;
wire dma_ack,dma_end;
wire dma_busynready;
wire [20:0] dma_addr;
wire [7:0] dma_wd;
wire [7:0] dma_rd;
wire [DEVNUM-1:0] req;
wire [DEVNUM-1:0] rnw;
wire [DEVNUM-1:0] done;
wire [DEVNUM-1:0] ack;
reg [20:0] addr[0:DEVNUM-1];
reg [7:0] wd[0:DEVNUM-1];
wire [7:0] rd;
wire mem_dma_bus;
wire [15:0] mem_dma_addr;
wire [7:0] mem_dma_wd;
wire [7:0] mem_dma_rd;
wire mem_dma_rnw;
wire mem_dma_oe;
wire mem_dma_we;
`ifndef NO_CPU
T80a z80( .RESET_n(rst_n),
.CLK_n(clk),
.WAIT_n(1'b1),
.INT_n(1'b1),
.NMI_n(1'b1),
.MREQ_n(mreq_n),
.IORQ_n(iorq_n),
.RD_n(rd_n),
.WR_n(wr_n),
.BUSRQ_n(busrq_n),
.BUSAK_n(busak_n),
.A(zaddr),
.D(zdata) );
`endif
rom myrom( .addr(zaddr),
.data(zdata),
.ce_n( (zaddr<16'h8000)?(mreq_n|rd_n):1'b1 ) );
assign zaddr = mem_dma_bus ? mem_dma_addr[15:0] : 16'hZZZZ;
assign zdata = (mem_dma_bus&(!mem_dma_rnw)) ? mem_dma_wd : 8'hZZ;
assign mem_dma_rd = zdata;
ram myram( .addr(zaddr),
.data(zdata),
.ce_n( (zaddr>=16'h8000)?1'b0:1'b1 ),
.oe_n( mem_dma_bus ? mem_dma_oe : (mreq_n|rd_n) ),
.we_n( mem_dma_bus ? mem_dma_we : (mreq_n|wr_n) ) );
dma_sequencer myseq( .clk(clk),
.rst_n(rst_n),
.rd (rd),
.addr0(addr[0]),
.wd0 (wd[0]),
.req0 (req[0]),
.rnw0 (rnw[0]),
.ack0 (ack[0]),
.end0 (done[0]),
.addr1(addr[1]),
.wd1 (wd[1]),
.req1 (req[1]),
.rnw1 (rnw[1]),
.ack1 (ack[1]),
.end1 (done[1]),
.addr2(addr[2]),
.wd2 (wd[2]),
.req2 (req[2]),
.rnw2 (rnw[2]),
.ack2 (ack[2]),
.end2 (done[2]),
.addr3(addr[3]),
.wd3 (wd[3]),
.req3 (req[3]),
.rnw3 (rnw[3]),
.ack3 (ack[3]),
.end3 (done[3]),
.dma_req(dma_req),
.dma_rnw(dma_rnw),
.dma_ack(dma_ack),
.dma_end(dma_end),
.dma_addr(dma_addr),
.dma_wd(dma_wd),
.dma_rd(dma_rd) );
dma_access mydma( .dma_req(dma_req),
.dma_rnw(dma_rnw),
.dma_ack(dma_ack),
.dma_end(dma_end),
.dma_addr(dma_addr),
.dma_wd(dma_wd),
.dma_rd(dma_rd),
.dma_busynready(dma_busynready),
.mem_dma_rd(zdata),
.mem_dma_wd(mem_dma_wd),
.mem_dma_bus(mem_dma_bus),
.mem_dma_addr(mem_dma_addr),
.mem_dma_rnw(mem_dma_rnw),
.mem_dma_oe(mem_dma_oe),
.mem_dma_we(mem_dma_we),
.clk(clk),
.rst_n(rst_n),
.busrq_n(busrq_n),
.busak_n(busak_n) );
reg start [0:DEVNUM-1];
reg rnw_in [0:DEVNUM-1];
wire inprogress [0:DEVNUM-1];
generate
genvar gv;
for(gv=0;gv<DEVNUM;gv=gv+1)
begin : dmaers
dmaer g( .clk(clk), .rst_n(rst_n),
.start(start[gv]),
.rnw_in(rnw_in[gv]),
.inprogress(inprogress[gv]),
.req(req[gv]),
.rnw(rnw[gv]),
.ack(ack[gv]),
.done(done[gv]) );
end
endgenerate
initial
begin
clk = 1'b0;
forever #40 clk <= ~clk;
end
initial
begin
rst_n <= 1'b0;
for(i=0;i<DEVNUM;i=i+1)
begin
start[i] = 1'b0;
rnw_in[i] = 1'b1;
addr[i] = 21'h8001;
wd[i] = 1+i+(i<<2)+(i<<6);
end
@(posedge clk);
@(posedge clk);
@(posedge clk);
rst_n <= 1'b1;
@(posedge clk);
/* start[1] <= 1'b1;
@(posedge ack[1]);
start[1] <= 1'b0;
@(negedge inprogress[1]);
*/
repeat (5) @(posedge clk);
rnw_in[1] = 1'b0;
rnw_in[1] = 1'b1;
rnw_in[1] = 1'b1;
rnw_in[1] = 1'b1;
start[0] = 1'b1;
start[1] = 1'b1;
start[2] = 1'b1;
start[3] = 1'b1;
fork
begin
repeat (3) @(posedge ack[0]);
start[0] <= 1'b0;
end
begin
repeat (3) @(posedge ack[1]);
start[1] <= 1'b0;
repeat(9) @(posedge clk);
start[1] <= 1'b1;
repeat(2) @(posedge ack[1]);
start[1] <= 1'b0;
end
begin
repeat(13) @(posedge ack[2]);
start[2] <= 1'b0;
end
begin
repeat(17) @(posedge ack[3]);
start[3] <= 1'b0;
end
join
// $stop;
end
endmodule
module dmaer(
input wire clk,
input wire rst_n,
input wire start,
input wire rnw_in,
output reg inprogress,
output reg req,
output reg rnw,
input wire ack,
input wire done
);
initial
begin
inprogress = 1'b0;
req = 1'b0;
rnw = 1'b1;
end
always @(negedge rst_n)
begin
disable main_loop;
req = 1'b0;
rnw = 1'b1;
inprogress = 1'b0;
end
always
begin : main_loop
wait(rst_n);
wait(start);
begin : dma_loop
forever
begin
inprogress <= 1'b1;
rnw <= rnw_in;
req <= 1'b1;
@(negedge ack);
if( !start ) disable dma_loop;
end
end
req <= 1'b0;
wait(done);/*@(posedge done);*/
inprogress <= 1'b0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5; int n, a[N], lm[N], rm[N], q[N]; vector<int> tree[35]; long long ans; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); for (int j = 0; (1 << j) <= a[i]; j++) if (a[i] & (1 << j)) tree[j].push_back(i); } int tail = 0; for (int i = 1; i <= n; i++) { while (tail && a[q[tail - 1]] < a[i]) tail--; lm[i] = tail ? q[tail - 1] + 1 : 1; q[tail++] = i; } tail = 0; for (int i = n; i; i--) { while (tail && a[q[tail - 1]] <= a[i]) tail--; rm[i] = tail ? q[tail - 1] - 1 : n; q[tail++] = i; } for (int i = 1; i <= n; i++) { if (lm[i] == rm[i]) continue; int tl = lm[i] - 1, tr = rm[i] + 1; for (int j = 0; (1 << j) <= a[i]; j++) if (!((1 << j) & a[i])) { if (tree[j].size() == 0) continue; auto it = lower_bound(tree[j].begin(), tree[j].end(), i); if (it != tree[j].begin()) { it--; tl = max(tl, *it); } it = upper_bound(tree[j].begin(), tree[j].end(), i); if (it != tree[j].end()) tr = min(tr, *it); } ans += 1ll * (i - lm[i] + 1) * (rm[i] - i + 1ll) - 1ll * (i - tl) * (tr - i); } cout << ans << endl; } |
#include <bits/stdc++.h> int main() { long long u, v, a, b; scanf( %lld%lld , &u, &v); if (v == 0) printf( 0 n ); else if (u > v) printf( -1 n ); else if (u == v) { printf( 1 n ); printf( %lld n , u); } else if ((v - u) % 2 == 0) { a = u, b = (v - u) / 2; if ((a ^ b) == (a + b)) { printf( 2 n ); printf( %lld %lld n , a + b, b); } else { printf( 3 n ); printf( %lld %lld %lld n , a, b, b); } } else printf( -1 n ); return 0; } |
#include <bits/stdc++.h> using namespace std; const int inf = ~0U >> 1; const long long linf = (long long)1e18; const double eps = 1e-6; template <class T> string tostr(T a) { ostringstream out; out << a; return out.str(); } struct debugger { template <typename T> debugger &operator,(const T &x) { cerr << x << endl; return *this; } } dbg; namespace fastIO { bool IOerror = 0; inline char nc() { static char buf[100000], *p1 = buf + 100000, *pend = buf + 100000; if (p1 == pend) { p1 = buf; pend = buf + fread(buf, 1, 100000, stdin); if (pend == p1) { IOerror = 1; return -1; } } return *p1++; } inline bool blank(char ch) { return ch == || ch == n || ch == r || ch == t ; } inline void read(int &x) { bool sign = 0; char ch = nc(); x = 0; for (; blank(ch); ch = nc()) ; if (IOerror) return; if (ch == - ) sign = 1, ch = nc(); for (; ch >= 0 && ch <= 9 ; ch = nc()) x = x * 10 + ch - 0 ; if (sign) x = -x; } inline void read(long long &x) { bool sign = 0; char ch = nc(); x = 0; for (; blank(ch); ch = nc()) ; if (IOerror) return; if (ch == - ) sign = 1, ch = nc(); for (; ch >= 0 && ch <= 9 ; ch = nc()) x = x * 10 + ch - 0 ; if (sign) x = -x; } inline void read(bool &x) { bool sign = 0; char ch = nc(); x = 0; for (; blank(ch); ch = nc()) ; if (IOerror) return; if (ch == - ) sign = 1, ch = nc(); for (; ch >= 0 && ch <= 9 ; ch = nc()) x = x * 10 + ch - 0 ; if (sign) x = -x; } inline void read(double &x) { bool sign = 0; char ch = nc(); x = 0; for (; blank(ch); ch = nc()) ; if (IOerror) return; if (ch == - ) sign = 1, ch = nc(); for (; ch >= 0 && ch <= 9 ; ch = nc()) x = x * 10 + ch - 0 ; if (ch == . ) { double tmp = 1; ch = nc(); for (; ch >= 0 && ch <= 9 ; ch = nc()) tmp /= 10.0, x += tmp * (ch - 0 ); } if (sign) x = -x; } inline void read(char *s) { char ch = nc(); for (; blank(ch); ch = nc()) ; if (IOerror) return; for (; !blank(ch) && !IOerror; ch = nc()) *s++ = ch; *s = 0; } inline void read(char &c) { for (c = nc(); blank(c); c = nc()) ; if (IOerror) { c = -1; return; } } inline void read1(int &x) { char ch; int bo = 0; x = 0; for (ch = getchar(); ch < 0 || ch > 9 ; ch = getchar()) if (ch == - ) bo = 1; for (; ch >= 0 && ch <= 9 ; x = x * 10 + ch - 0 , ch = getchar()) ; if (bo) x = -x; } inline void read1(long long &x) { char ch; int bo = 0; x = 0; for (ch = getchar(); ch < 0 || ch > 9 ; ch = getchar()) if (ch == - ) bo = 1; for (; ch >= 0 && ch <= 9 ; x = x * 10 + ch - 0 , ch = getchar()) ; if (bo) x = -x; } inline void read1(double &x) { char ch; int bo = 0; x = 0; for (ch = getchar(); ch < 0 || ch > 9 ; ch = getchar()) if (ch == - ) bo = 1; for (; ch >= 0 && ch <= 9 ; x = x * 10 + ch - 0 , ch = getchar()) ; if (ch == . ) { double tmp = 1; for (ch = getchar(); ch >= 0 && ch <= 9 ; tmp /= 10.0, x += tmp * (ch - 0 ), ch = getchar()) ; } if (bo) x = -x; } inline void read1(char *s) { char ch = getchar(); for (; blank(ch); ch = getchar()) ; for (; !blank(ch); ch = getchar()) *s++ = ch; *s = 0; } inline void read1(char &c) { for (c = getchar(); blank(c); c = getchar()) ; } inline void read2(int &x) { scanf( %d , &x); } inline void read2(long long &x) { scanf( %lld , &x); } inline void read2(double &x) { scanf( %lf , &x); } inline void read2(char *s) { scanf( %s , s); } inline void read2(char &c) { scanf( %c , &c); } inline void readln2(char *s) { gets(s); } struct Ostream_fwrite { char *buf, *p1, *pend; Ostream_fwrite() { buf = new char[100000]; p1 = buf; pend = buf + 100000; } void out(char ch) { if (p1 == pend) { fwrite(buf, 1, 100000, stdout); p1 = buf; } *p1++ = ch; } void print(int x) { static char s[15], *s1; s1 = s; if (!x) *s1++ = 0 ; if (x < 0) out( - ), x = -x; while (x) *s1++ = x % 10 + 0 , x /= 10; while (s1-- != s) out(*s1); } void println(int x) { static char s[15], *s1; s1 = s; if (!x) *s1++ = 0 ; if (x < 0) out( - ), x = -x; while (x) *s1++ = x % 10 + 0 , x /= 10; while (s1-- != s) out(*s1); out( n ); } void print(long long x) { static char s[25], *s1; s1 = s; if (!x) *s1++ = 0 ; if (x < 0) out( - ), x = -x; while (x) *s1++ = x % 10 + 0 , x /= 10; while (s1-- != s) out(*s1); } void println(long long x) { static char s[25], *s1; s1 = s; if (!x) *s1++ = 0 ; if (x < 0) out( - ), x = -x; while (x) *s1++ = x % 10 + 0 , x /= 10; while (s1-- != s) out(*s1); out( n ); } void print(double x, int y) { static long long mul[] = {1, 10, 100, 1000, 10000, 100000, 1000000, 10000000, 100000000, 1000000000, 10000000000LL, 100000000000LL, 1000000000000LL, 10000000000000LL, 100000000000000LL, 1000000000000000LL, 10000000000000000LL, 100000000000000000LL}; if (x < -1e-7) out( - ), x = -x; x *= mul[y]; long long x1 = (long long)floor(x); if (x - floor(x) >= 0.5) ++x1; long long x2 = x1 / mul[y]; print(x2); if (y > 0) { out( . ); print(x1 - x2 * mul[y]); } } void println(double x, int y) { print(x, y); out( n ); } void print(char *s) { while (*s) out(*s++); } void println(char *s) { while (*s) out(*s++); out( n ); } void flush() { if (p1 != buf) { fwrite(buf, 1, p1 - buf, stdout); p1 = buf; } } ~Ostream_fwrite() { flush(); } } Ostream; inline void print(int x) { Ostream.print(x); } inline void println(int x) { Ostream.println(x); } inline void print(char x) { Ostream.out(x); } inline void println(char x) { Ostream.out(x); Ostream.out( n ); } inline void print(long long x) { Ostream.print(x); } inline void println(long long x) { Ostream.println(x); } inline void print(double x, int y) { Ostream.print(x, y); } inline void println(double x, int y) { Ostream.println(x, y); } inline void print(char *s) { Ostream.print(s); } inline void println(char *s) { Ostream.println(s); } inline void println() { Ostream.out( n ); } inline void flush() { Ostream.flush(); } char Out[100000], *o = Out; inline void print1(int x) { static char buf[15]; char *p1 = buf; if (!x) *p1++ = 0 ; if (x < 0) *o++ = - , x = -x; while (x) *p1++ = x % 10 + 0 , x /= 10; while (p1-- != buf) *o++ = *p1; } inline void println1(int x) { print1(x); *o++ = n ; } inline void print1(long long x) { static char buf[25]; char *p1 = buf; if (!x) *p1++ = 0 ; if (x < 0) *o++ = - , x = -x; while (x) *p1++ = x % 10 + 0 , x /= 10; while (p1-- != buf) *o++ = *p1; } inline void println1(long long x) { print1(x); *o++ = n ; } inline void print1(char c) { *o++ = c; } inline void println1(char c) { *o++ = c; *o++ = n ; } inline void print1(char *s) { while (*s) *o++ = *s++; } inline void println1(char *s) { print(s); *o++ = n ; } inline void println1() { *o++ = n ; } inline void flush1() { if (o != Out && *(o - 1) == n ) *--o = 0; puts(Out); } struct puts_write { ~puts_write() { flush1(); } }; inline void print2(int x) { printf( %d , x); } inline void println2(int x) { printf( %d n , x); } inline void print2(char x) { printf( %c , x); } inline void println2(char x) { printf( %c n , x); } inline void print2(long long x) { printf( %lld , x); } inline void println2(long long x) { print2(x); printf( n ); } inline void println2() { printf( n ); } }; // namespace fastIO using namespace fastIO; string name = , in = .in , out = .out ; bool a[2005][2005], visit[2005][2005]; int cx[700005], cy[700005], c1, n, cnt, cntC, cntS; double dist[700005], Ox, Oy; void dfs(int x, int y) { if (visit[x][y]) return; visit[x][y] = 1; ++cnt; bool bo = 0; Ox += x; Oy += y; for (int dx = -1; dx <= 1; ++dx) for (int dy = -1; dy <= 1; ++dy) { int x1 = x + dx, y1 = y + dy; if (!a[x1][y1]) ++bo; else dfs(x1, y1); } if (bo) ++c1, cx[c1] = x, cy[c1] = y; } void genMap() { static bool tmp[2005][2005]; memcpy(tmp, a, sizeof(a)); memset(a, 0, sizeof(a)); for (int i = 4; i + 3 <= n; ++i) for (int j = 4; j + 3 <= n; ++j) { int cnt = 0; for (int dx = -3; dx <= 3; ++dx) for (int dy = -3; dy <= 3; ++dy) cnt += tmp[i + dx][j + dy]; if (cnt >= 24) a[i][j] = 1; else a[i][j] = 0; } } int main() { read(n); memset(visit, 1, sizeof(visit)); for (int i = 1; i <= n; ++i) for (int j = 1; j <= n; ++j) read(a[i][j]), visit[i][j] = 0; genMap(); for (int i = 1; i <= n; ++i) for (int j = 1; j <= n; ++j) if (!visit[i][j] && a[i][j]) { c1 = 0; cnt = 0; Ox = 0; Oy = 0; dfs(i, j); if (cnt < 130) continue; double max_d = 0; int c1_pre = c1; Ox /= cnt; Oy /= cnt; for (int k = 1; k <= c1; ++k) dist[k] = sqrt((Ox - cx[k]) * (Ox - cx[k]) + (Oy - cy[k]) * (Oy - cy[k])); for (int k = 1; k <= c1; ++k) max_d = max(max_d, dist[k]); for (int k = 1; k <= c1; ++k) dist[k] /= max_d; double ave = accumulate(dist + 1, dist + c1 + 1, 0.0) / c1, sum = 0; for (int k = 1; k <= c1; ++k) sum += (dist[k] - ave) * (dist[k] - ave); sum /= c1; sum = sqrt(sum); double div = sum / ave; if (div > 0.045 && div < 0.055) { printf( div=%.5lf cnt=%d n , div, cnt); while (1) ; } if (div < 0.060) ++cntC; else ++cntS; } end:; printf( %d %d n , cntC, cntS); return 0; } |
//////////////////////////////////////////////////////////////////////
//// ////
//// dbg_comm_vpi.v ////
//// ////
//// ////
//// This file is part of the SoC/OpenRISC Development Interface ////
//// http://www.opencores.org/cores/DebugInterface/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor () ////
//// Gyorgy Jeney () ////
//// Nathan Yawn () ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2008 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: dbg_comm_vpi.v,v $
// Revision 1.2 2009-05-17 20:55:57 Nathan
// Changed email address to opencores.org
//
// Revision 1.1 2008/07/26 17:33:20 Nathan
// Added debug comm module for use with VPI / network communication.
//
// Revision 1.1 2002/03/28 19:59:54 lampret
// Added bench directory
//
// Revision 1.1.1.1 2001/11/04 18:51:07 lampret
// First import.
//
// Revision 1.3 2001/09/24 14:06:13 mohor
// Changes connected to the OpenRISC access (SPR read, SPR write).
//
// Revision 1.2 2001/09/20 10:10:30 mohor
// Working version. Few bugs fixed, comments added.
//
// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
// Initial official release.
//
//
//
//
//
`define JP_PORT "4567"
`define TIMEOUT_COUNT 6'd20 // 1/2 of a TCK clock will be this many SYS_CLK ticks. Must be less than 6 bits.
module dbg_comm_vpi (
SYS_CLK,
SYS_RSTN,
P_TMS,
P_TCK,
P_TRST,
P_TDI,
P_TDO
);
//parameter Tp = 20;
output SYS_CLK;
output SYS_RSTN;
output P_TMS;
output P_TCK;
output P_TRST;
output P_TDI;
input P_TDO;
reg SYS_CLK;
reg SYS_RSTN;
reg [4:0] memory; // [0:0];
wire P_TCK;
wire P_TRST;
wire P_TDI;
wire P_TMS;
wire P_TDO;
reg [3:0] in_word_r;
reg [5:0] clk_count;
// Provide the wishbone / CPU / system clock
initial
begin
SYS_CLK = 1'b0;
clk_count[5:0] <= `TIMEOUT_COUNT + 1; // Start with the timeout clock stopped
forever #5 SYS_CLK = ~SYS_CLK;
end
// Provide the system reset
initial
begin
SYS_RSTN = 1'b1;
#200 SYS_RSTN = 1'b0;
#5000 SYS_RSTN = 1'b1;
end
// Handle commands from the upper level
initial
begin
in_word_r = 5'b0;
memory = 5'b0;
$jp_init(`JP_PORT);
#5500; // Wait until reset is complete
while(1)
begin
#1;
$jp_in(memory); // This will not change memory[][] if no command has been sent from jp
if(memory[4]) // was memory[0][4]
begin
in_word_r = memory[3:0];
memory = memory & 4'b1111;
clk_count = 6'b000000; // Reset the timeout clock in case jp wants to wait for a timeout / half TCK period
end
end
end
// Send the output bit to the upper layer
always @ (P_TDO)
begin
$jp_out(P_TDO);
end
assign P_TCK = in_word_r[0];
assign P_TRST = in_word_r[1];
assign P_TDI = in_word_r[2];
assign P_TMS = in_word_r[3];
// Send timeouts / wait periods to the upper layer
always @ (posedge SYS_CLK)
begin
if(clk_count < `TIMEOUT_COUNT) clk_count[5:0] = clk_count[5:0] + 1;
else if(clk_count == `TIMEOUT_COUNT) begin
$jp_wait_time();
clk_count[5:0] = clk_count[5:0] + 1;
end
// else it's already timed out, don't do anything
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 100; void ask(int r1, int c1, int r2, int c2) { cout << ? << r1 << << c1 << << r2 << << c2 << n ; cout.flush(); } bool ans() { string ans; cin >> ans; return ans == YES ; } int main() { ios::sync_with_stdio(0); cin.tie(0); int n; cin >> n; int steps = 0; int rx = 1, ry = 1; string pre = ; while (steps < n - 1) { ask(rx + 1, ry, n, n); bool sol = ans(); if (sol) { pre += D ; rx++; } else { pre += R ; ry++; } steps++; } string suf = ; steps = 0; rx = n, ry = n; while (steps < n - 1) { ask(1, 1, rx, ry - 1); bool sol = ans(); if (sol) { suf += R ; ry--; } else { suf += D ; rx--; } steps++; } reverse(suf.begin(), suf.end()); cout << ! << (pre + suf) << n ; cout.flush(); } |
#include <bits/stdc++.h> using namespace std; long double PI = acos(-1); long double DEL = 1e-10; int M = 1e9 + 7; const int N = 3e5 + 10; #define ftt cin>>tc;for(int cas=1;cas<=tc;++cas) #define all(a) a.begin(),a.end() #define vpii vector<pair<int,int> > #define vvi vector<vector<int> > #define va(x) vector<array<int,(x)> > #define pii pair<int,int> #define vi vector<int> #define sq(a) ((a)*(a)) #define double long double #define dbg cout<< nhi n ; #define int long long #define nl cout<< n #define sp << << #define S second #define F first template<class T> using minpq = priority_queue<T,vector<T>,greater<T> >; struct DSU { vi par,size; DSU (int n) { par.resize(n+1); size.resize(n+1); for(int i=0;i<=n;i++) { par[i] = i; size[i] = 1; } } int find(int x) { return par[x] = (x == par[x]? par[x]:find(par[x])); } void join(int x,int y) { int parx = find(x),pary = find(y); if(parx == pary) { return; } if(size[parx] > size[pary]) { size[parx] += size[pary]; par[pary] = parx; } else { size[pary] += size[parx]; par[parx] = pary; } } }; int fpow(int x, int n) { int res = 1; x %= M; while(n) { if(n&1)res = res * x % M; x = x * x % M; n>>=1; } return res; } int gcd(int a,int b) { if(b == 0)return a; return gcd(b,a % b); } int lcm(int a,int b) { return a*(b/gcd(a,b)); } int popcount(int x) { return bitset<65>(x).count(); } vector<int> fac(N),inv(N); void create_fac(int n) { fac[0] = inv[0] = 1; for(int i=1;i<=n;i++) { fac[i] = fac[i-1]*i % M; inv[i] = fpow(fac[i],M-2); } } int ncr(int n,int r) { if(r > n)return 0; return fac[n] * (inv[r] * inv[n-r] % M) % M; return fac[n] * (fpow(fac[r],M-2) * fpow(fac[n-r],M-2) % M ) % M; } void sieve (int n) { vector<int> pf(N); pf[0] = pf[1] = 1; for (int i = 2; i <= n; i++) { if (!pf[i]) { pf[i] = i; for (int j = i * i; j <= n; j += i){ pf[j] = i; } } } } //**************************************** CHECK CONSTRAINTS *************************************** int cnt, sum, mid, mx, mn, ans, a[N], b[N]; int n, m, d, i, j, k, l, p, q, r, t, w, x, y, z, tc; string s; vvi dp(402,vi(402)); int32_t main() { ios_base::sync_with_stdio(0);cin.tie(0);cout.tie(0); #ifndef ONLINE_JUDGE freopen( /Users/jenish/XCode/cp/input.txt , r ,stdin); #endif cin >> n >> M; // dp[i][j] => done till i and had j gaps. for(int i = 1;i <= n;i++){ dp[i][0] = fpow(2,i-1); } create_fac(n+2); for(int i = 2;i <= n;i++){ for(int gaps = 1;gaps <= i - 2;gaps++){ //lgp = last gap position for(int lgp = 2;lgp < i;lgp++){ //cout << i sp gaps sp lgp;nl; //cout << dp[lgp - 1][gaps - 1] sp fpow(2,i - lgp - 1) sp ncr(i - gaps,i - lgp);nl; dp[i][gaps] += (dp[lgp - 1][gaps - 1] * fpow(2,i - lgp - 1) % M) * ncr(i - gaps,i - lgp) % M; dp[i][gaps] %= M; } } } for(int gaps = 0;gaps < n - 1;gaps++){ //cout<<gaps sp dp[n][gaps];nl; ans += dp[n][gaps]; ans %= M; } cout << ans; } |
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// ============================================================================
// LUT mapping
`ifndef _NO_LUTS
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
(* force_downto *)
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
if (LUT == 2'b01) begin
INV _TECHMAP_REPLACE_ (.O(Y), .I(A[0]));
end else begin
LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[0]));
end
end else
if (WIDTH == 2) begin
LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[0]), .I1(A[1]));
end else
if (WIDTH == 3) begin
LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2]));
end else
if (WIDTH == 4) begin
LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2]),
.I3(A[3]));
end else
if (WIDTH == 5 && WIDTH <= `LUT_WIDTH) begin
LUT5 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2]),
.I3(A[3]), .I4(A[4]));
end else
if (WIDTH == 6 && WIDTH <= `LUT_WIDTH) begin
LUT6 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2]),
.I3(A[3]), .I4(A[4]), .I5(A[5]));
end else
if (WIDTH == 5 && WIDTH > `LUT_WIDTH) begin
wire f0, f1;
\$lut #(.LUT(LUT[15: 0]), .WIDTH(4)) lut0 (.A(A[3:0]), .Y(f0));
\$lut #(.LUT(LUT[31:16]), .WIDTH(4)) lut1 (.A(A[3:0]), .Y(f1));
MUXF5 mux5(.I0(f0), .I1(f1), .S(A[4]), .O(Y));
end else
if (WIDTH == 6 && WIDTH > `LUT_WIDTH) begin
wire f0, f1;
\$lut #(.LUT(LUT[31: 0]), .WIDTH(5)) lut0 (.A(A[4:0]), .Y(f0));
\$lut #(.LUT(LUT[63:32]), .WIDTH(5)) lut1 (.A(A[4:0]), .Y(f1));
MUXF6 mux6(.I0(f0), .I1(f1), .S(A[5]), .O(Y));
end else
if (WIDTH == 7) begin
wire f0, f1;
\$lut #(.LUT(LUT[ 63: 0]), .WIDTH(6)) lut0 (.A(A[5:0]), .Y(f0));
\$lut #(.LUT(LUT[127:64]), .WIDTH(6)) lut1 (.A(A[5:0]), .Y(f1));
MUXF7 mux7(.I0(f0), .I1(f1), .S(A[6]), .O(Y));
end else
if (WIDTH == 8) begin
wire f0, f1;
\$lut #(.LUT(LUT[127: 0]), .WIDTH(7)) lut0 (.A(A[6:0]), .Y(f0));
\$lut #(.LUT(LUT[255:128]), .WIDTH(7)) lut1 (.A(A[6:0]), .Y(f1));
MUXF8 mux8(.I0(f0), .I1(f1), .S(A[7]), .O(Y));
end else
if (WIDTH == 9) begin
wire f0, f1;
\$lut #(.LUT(LUT[255: 0]), .WIDTH(8)) lut0 (.A(A[7:0]), .Y(f0));
\$lut #(.LUT(LUT[511:256]), .WIDTH(8)) lut1 (.A(A[7:0]), .Y(f1));
MUXF9 mux9(.I0(f0), .I1(f1), .S(A[8]), .O(Y));
end else begin
wire _TECHMAP_FAIL_ = 1;
end
endgenerate
endmodule
`endif
|
/*
* .--------------. .----------------. .------------.
* | .------------. | .--------------. | .----------. |
* | | ____ ____ | | | ____ ____ | | | ______ | |
* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
* | | | | | | | | | | | |
* |_| | '------------' | '--------------' | '----------' |
* '--------------' '----------------' '------------'
*
* openHMC - An Open Source Hybrid Memory Cube Controller
* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
* www.ziti.uni-heidelberg.de
* B6, 26
* 68159 Mannheim
* Germany
*
* Contact:
* http://ra.ziti.uni-heidelberg.de/openhmc
*
* This source file is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This source file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this source file. If not, see <http://www.gnu.org/licenses/>.
*
*
* Module name: openhmc_sync_fifo
*
*/
`default_nettype none
module openhmc_sync_fifo #(
`ifdef CAG_ASSERTIONS
parameter DISABLE_EMPTY_ASSERT = 0,
parameter DISABLE_SHIFT_OUT_ASSERT = 0,
parameter DISABLE_XCHECK_ASSERT = 0,
`endif
parameter DATASIZE = 8,
parameter ADDRSIZE = 8
) (
//----------------------------------
//----SYSTEM INTERFACE
//----------------------------------
input wire clk,
input wire res_n,
//----------------------------------
//----Signals
//----------------------------------
input wire [DATASIZE-1:0] d_in,
input wire shift_in,
input wire shift_out,
input wire next_stage_full, // Set to 1 if not chained
output wire [DATASIZE-1:0] d_out,
output wire empty
);
//=====================================================================================================
//-----------------------------------------------------------------------------------------------------
//---------WIRING AND SIGNAL STUFF---------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------
//=====================================================================================================
wire si, so; // internal gated shift signals
reg full_r1, full_r2;
wire full_1, full_2, full_3;
reg full_m2, full_m1;
reg [DATASIZE-1:0] d_out_r1, d_out_r2;
wire [DATASIZE-1:0] d_out_m2, d_out_2, d_out_3;
wire mux_rm_2;
reg [ADDRSIZE -1:0] ra_m, wa_m; //addr after register similar to signal internal to sram
reg [ADDRSIZE -1:0] ra, wa; // address calculated for the next read
wire wen, ren;
wire m_empty;
assign full_1 = full_r1 || full_m1 || (full_m2 && full_r2);
assign full_2 = full_r2 || full_m2;
//=====================================================================================================
//-----------------------------------------------------------------------------------------------------
//---------LOGIC STARTS HERE---------------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------
//=====================================================================================================
always @ (posedge clk or negedge res_n) begin
if (!res_n) begin
d_out_r1 <= {DATASIZE {1'b0}};
d_out_r2 <= {DATASIZE {1'b0}};
full_r1 <= 1'b0;
full_r2 <= 1'b0;
end else begin
// Register stage 1 (conditions shouldn't overlap)
if ((full_2 && !full_1 && si && !so) || // fill stage
(full_1 && m_empty && si && so)) begin // shift through
d_out_r1 <= d_in;
full_r1 <= 1'b1;
end
if (full_r1 && so && (!si || !m_empty)) begin // shift out
full_r1 <= 1'b0;
end
// Register stage 2 (conditions shouldn't overlap)
if (full_3 && ((!full_2 && si && !so) || // fill stage
(full_2 && !full_1 && si && so))) begin // shift through
d_out_r2 <= d_in;
full_r2 <= 1'b1;
end
if (full_r1 && so) begin // shift through
d_out_r2 <= d_out_r1;
full_r2 <= 1'b1;
end
if (full_m2 && ((!full_r2 && !so) || // Rescue
(full_r2 && so))) begin
d_out_r2 <= d_out_m2;
full_r2 <= 1'b1;
end
if (full_r2 &&
((!full_r1 && !full_m2 && so && !si) || // shift out
(full_m1 && si && so))) begin // shift through with RAM
full_r2 <= 1'b0;
end
end
end
// assign outputs and inputs to module interface
assign d_out = d_out_3;
assign empty = !full_3; // if the last stage is empty, the fifo is empty
assign si = shift_in;
assign so = shift_out;
wire [ADDRSIZE:0] fifo_ram_count = wa_m - ra_m;
assign mux_rm_2 = full_r2; // mux control of SRAM data bypass if only one value in stage r2
assign d_out_2 = mux_rm_2 ? d_out_r2 : d_out_m2; // additional data mux for SRAM bypass
// write port control of SRAM
assign wen = si && !so && full_1 // enter new value into SRAM, because regs are filled
|| si && !m_empty; // if a value is in the SRAM, then we have to shift through or shift in
// read port control of SRAM
assign ren = so && !m_empty;
assign m_empty = (wa_m == ra_m);
always @ (posedge clk or negedge res_n) begin
if (!res_n) begin
full_m1 <= 1'b0;
full_m2 <= 1'b0;
end else begin
full_m1 <= ren; // no control of m1
full_m2 <= full_m1
|| full_m2 && !so && full_r2; // no rescue possible
end
end
// pointer management
always @(*) begin
wa = wa_m + 1'b1; // wa_m is the address stored in mem addr register
ra = ra_m + 1'b1;
end
always @ (posedge clk or negedge res_n) begin
if (!res_n) begin
wa_m <= {ADDRSIZE {1'b0}};
ra_m <= {ADDRSIZE {1'b0}};
end else begin
if (wen) begin
wa_m <= wa; // next mem write addr to mem addr register
end
if (ren) begin
ra_m <= ra;
end
end
end
//=====================================================================================================
//-----------------------------------------------------------------------------------------------------
//---------INSTANTIATIONS HERE-------------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------
//=====================================================================================================
openhmc_sync_fifo_reg_stage #(.DWIDTH(DATASIZE))
sync_fifo_reg_stage_3_I (
.clk(clk),
.res_n(res_n),
.d_in(d_in),
.d_in_p(d_out_2),
.p_full(full_2),
.n_full(1'b1),
.si(si),
.so(so),
.full(full_3),
.d_out(d_out_3)
);
openhmc_ram #(
.DATASIZE(DATASIZE), // Memory data word width
.ADDRSIZE(ADDRSIZE), // Number of memory address bits
.PIPELINED(1)
)
ram(
.clk(clk),
.wen(wen),
.wdata(d_in),
.waddr(wa),
.ren(ren),
.raddr(ra),
.rdata(d_out_m2)
);
`ifdef CAG_ASSERTIONS
if (DISABLE_SHIFT_OUT_ASSERT == 0)
shift_out_and_empty: assert property (@(posedge clk) disable iff(!res_n) (shift_out |-> !empty));
if (DISABLE_XCHECK_ASSERT == 0)
dout_known: assert property (@(posedge clk) disable iff(!res_n) (!empty |-> !$isunknown(d_out)));
final
begin
if (DISABLE_EMPTY_ASSERT == 0)
begin
empty_not_set_assert: assert (empty);
end
end
`endif // CAG_ASSERTIONS
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 505; int n, m; int v[MAXN]; int head[MAXN]; double e[MAXN * MAXN]; int a, b, c; int main() { while (scanf( %d%d , &n, &m) != EOF) { for (int i = 1; i <= n; i++) scanf( %d , &v[i]); for (int i = 1; i <= m; i++) { scanf( %d%d%d , &a, &b, &c); e[i] = 1.0 * (v[a] + v[b]) / c; } double ans = 0.0; for (int i = 1; i <= m; i++) ans = max(ans, e[i]); printf( %.12lf n , ans); } return 0; } |
//
// Generated by Bluespec Compiler (build 0fccbb13)
//
//
// Ports:
// Name I/O size props
// m_near_mem_io_addr_base O 64 const
// m_near_mem_io_addr_size O 64 const
// m_near_mem_io_addr_lim O 64 const
// m_plic_addr_base O 64 const
// m_plic_addr_size O 64 const
// m_plic_addr_lim O 64 const
// m_uart0_addr_base O 64 const
// m_uart0_addr_size O 64 const
// m_uart0_addr_lim O 64 const
// m_boot_rom_addr_base O 64 const
// m_boot_rom_addr_size O 64 const
// m_boot_rom_addr_lim O 64 const
// m_mem0_controller_addr_base O 64 const
// m_mem0_controller_addr_size O 64 const
// m_mem0_controller_addr_lim O 64 const
// m_tcm_addr_base O 64 const
// m_tcm_addr_size O 64 const
// m_tcm_addr_lim O 64 const
// m_is_mem_addr O 1
// m_is_IO_addr O 1
// m_is_near_mem_IO_addr O 1
// m_pc_reset_value O 64 const
// m_mtvec_reset_value O 64 const
// m_nmivec_reset_value O 64 const
// CLK I 1 unused
// RST_N I 1 unused
// m_is_mem_addr_addr I 64
// m_is_IO_addr_addr I 64
// m_is_near_mem_IO_addr_addr I 64
//
// Combinational paths from inputs to outputs:
// m_is_mem_addr_addr -> m_is_mem_addr
// m_is_IO_addr_addr -> m_is_IO_addr
// m_is_near_mem_IO_addr_addr -> m_is_near_mem_IO_addr
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkSoC_Map(CLK,
RST_N,
m_near_mem_io_addr_base,
m_near_mem_io_addr_size,
m_near_mem_io_addr_lim,
m_plic_addr_base,
m_plic_addr_size,
m_plic_addr_lim,
m_uart0_addr_base,
m_uart0_addr_size,
m_uart0_addr_lim,
m_boot_rom_addr_base,
m_boot_rom_addr_size,
m_boot_rom_addr_lim,
m_mem0_controller_addr_base,
m_mem0_controller_addr_size,
m_mem0_controller_addr_lim,
m_tcm_addr_base,
m_tcm_addr_size,
m_tcm_addr_lim,
m_is_mem_addr_addr,
m_is_mem_addr,
m_is_IO_addr_addr,
m_is_IO_addr,
m_is_near_mem_IO_addr_addr,
m_is_near_mem_IO_addr,
m_pc_reset_value,
m_mtvec_reset_value,
m_nmivec_reset_value);
input CLK;
input RST_N;
// value method m_near_mem_io_addr_base
output [63 : 0] m_near_mem_io_addr_base;
// value method m_near_mem_io_addr_size
output [63 : 0] m_near_mem_io_addr_size;
// value method m_near_mem_io_addr_lim
output [63 : 0] m_near_mem_io_addr_lim;
// value method m_plic_addr_base
output [63 : 0] m_plic_addr_base;
// value method m_plic_addr_size
output [63 : 0] m_plic_addr_size;
// value method m_plic_addr_lim
output [63 : 0] m_plic_addr_lim;
// value method m_uart0_addr_base
output [63 : 0] m_uart0_addr_base;
// value method m_uart0_addr_size
output [63 : 0] m_uart0_addr_size;
// value method m_uart0_addr_lim
output [63 : 0] m_uart0_addr_lim;
// value method m_boot_rom_addr_base
output [63 : 0] m_boot_rom_addr_base;
// value method m_boot_rom_addr_size
output [63 : 0] m_boot_rom_addr_size;
// value method m_boot_rom_addr_lim
output [63 : 0] m_boot_rom_addr_lim;
// value method m_mem0_controller_addr_base
output [63 : 0] m_mem0_controller_addr_base;
// value method m_mem0_controller_addr_size
output [63 : 0] m_mem0_controller_addr_size;
// value method m_mem0_controller_addr_lim
output [63 : 0] m_mem0_controller_addr_lim;
// value method m_tcm_addr_base
output [63 : 0] m_tcm_addr_base;
// value method m_tcm_addr_size
output [63 : 0] m_tcm_addr_size;
// value method m_tcm_addr_lim
output [63 : 0] m_tcm_addr_lim;
// value method m_is_mem_addr
input [63 : 0] m_is_mem_addr_addr;
output m_is_mem_addr;
// value method m_is_IO_addr
input [63 : 0] m_is_IO_addr_addr;
output m_is_IO_addr;
// value method m_is_near_mem_IO_addr
input [63 : 0] m_is_near_mem_IO_addr_addr;
output m_is_near_mem_IO_addr;
// value method m_pc_reset_value
output [63 : 0] m_pc_reset_value;
// value method m_mtvec_reset_value
output [63 : 0] m_mtvec_reset_value;
// value method m_nmivec_reset_value
output [63 : 0] m_nmivec_reset_value;
// signals for module outputs
wire [63 : 0] m_boot_rom_addr_base,
m_boot_rom_addr_lim,
m_boot_rom_addr_size,
m_mem0_controller_addr_base,
m_mem0_controller_addr_lim,
m_mem0_controller_addr_size,
m_mtvec_reset_value,
m_near_mem_io_addr_base,
m_near_mem_io_addr_lim,
m_near_mem_io_addr_size,
m_nmivec_reset_value,
m_pc_reset_value,
m_plic_addr_base,
m_plic_addr_lim,
m_plic_addr_size,
m_tcm_addr_base,
m_tcm_addr_lim,
m_tcm_addr_size,
m_uart0_addr_base,
m_uart0_addr_lim,
m_uart0_addr_size;
wire m_is_IO_addr, m_is_mem_addr, m_is_near_mem_IO_addr;
// value method m_near_mem_io_addr_base
assign m_near_mem_io_addr_base = 64'h0000000002000000 ;
// value method m_near_mem_io_addr_size
assign m_near_mem_io_addr_size = 64'h000000000000C000 ;
// value method m_near_mem_io_addr_lim
assign m_near_mem_io_addr_lim = 64'd33603584 ;
// value method m_plic_addr_base
assign m_plic_addr_base = 64'h000000000C000000 ;
// value method m_plic_addr_size
assign m_plic_addr_size = 64'h0000000000400000 ;
// value method m_plic_addr_lim
assign m_plic_addr_lim = 64'd205520896 ;
// value method m_uart0_addr_base
assign m_uart0_addr_base = 64'h00000000C0000000 ;
// value method m_uart0_addr_size
assign m_uart0_addr_size = 64'h0000000000000080 ;
// value method m_uart0_addr_lim
assign m_uart0_addr_lim = 64'h00000000C0000080 ;
// value method m_boot_rom_addr_base
assign m_boot_rom_addr_base = 64'h0000000000001000 ;
// value method m_boot_rom_addr_size
assign m_boot_rom_addr_size = 64'h0000000000001000 ;
// value method m_boot_rom_addr_lim
assign m_boot_rom_addr_lim = 64'd8192 ;
// value method m_mem0_controller_addr_base
assign m_mem0_controller_addr_base = 64'h0000000080000000 ;
// value method m_mem0_controller_addr_size
assign m_mem0_controller_addr_size = 64'h0000000010000000 ;
// value method m_mem0_controller_addr_lim
assign m_mem0_controller_addr_lim = 64'h0000000090000000 ;
// value method m_tcm_addr_base
assign m_tcm_addr_base = 64'h0 ;
// value method m_tcm_addr_size
assign m_tcm_addr_size = 64'd0 ;
// value method m_tcm_addr_lim
assign m_tcm_addr_lim = 64'd0 ;
// value method m_is_mem_addr
assign m_is_mem_addr =
m_is_mem_addr_addr >= 64'h0000000000001000 &&
m_is_mem_addr_addr < 64'd8192 ||
m_is_mem_addr_addr >= 64'h0000000080000000 &&
m_is_mem_addr_addr < 64'h0000000090000000 ;
// value method m_is_IO_addr
assign m_is_IO_addr =
m_is_IO_addr_addr >= 64'h0000000002000000 &&
m_is_IO_addr_addr < 64'd33603584 ||
m_is_IO_addr_addr >= 64'h000000000C000000 &&
m_is_IO_addr_addr < 64'd205520896 ||
m_is_IO_addr_addr >= 64'h00000000C0000000 &&
m_is_IO_addr_addr < 64'h00000000C0000080 ;
// value method m_is_near_mem_IO_addr
assign m_is_near_mem_IO_addr =
m_is_near_mem_IO_addr_addr >= 64'h0000000002000000 &&
m_is_near_mem_IO_addr_addr < 64'd33603584 ;
// value method m_pc_reset_value
assign m_pc_reset_value = 64'h0000000000001000 ;
// value method m_mtvec_reset_value
assign m_mtvec_reset_value = 64'h0000000000001000 ;
// value method m_nmivec_reset_value
assign m_nmivec_reset_value = 64'hAAAAAAAAAAAAAAAA ;
endmodule // mkSoC_Map
|
#include <bits/stdc++.h> using namespace std; int main() { long long n; cin >> n; long long a, b; for (a = 0; a <= n / 1234567; a++) { for (b = 0; b * 123456 <= n - a * 1234567; b++) if ((n - (a * 1234567 + b * 123456)) % 1234 == 0) { cout << YES ; return 0; } } cout << NO ; } |
#include <bits/stdc++.h> #pragma GCC optimize(2) using namespace std; const long long mod = 998244353; const long long maxn = 3e5 + 10; long long p[2] = {1000000007, 998244353}; long long seed[2] = {500000004, 500000004}; int main() { int x, a[6]; scanf( %d , &x); for (int i = 0; i < 6; i++) if (x & (1 << i)) a[i] = 1; else a[i] = 0; swap(a[0], a[4]); swap(a[2], a[3]); int y = 0; for (int i = 0; i < 6; i++) if (a[i]) y += 1 << i; printf( %d n , y); return 0; } |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ADC channel-
`timescale 1ns/100ps
module axi_ad9652_channel (
// adc interface
adc_clk,
adc_rst,
adc_data,
adc_or,
// channel interface
adc_dcfilter_data_out,
adc_dcfilter_data_in,
adc_iqcor_data,
adc_enable,
up_adc_pn_err,
up_adc_pn_oos,
up_adc_or,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
parameter IQSEL = 0;
parameter CHID = 0;
parameter DP_DISABLE = 0;
// adc interface
input adc_clk;
input adc_rst;
input [15:0] adc_data;
input adc_or;
// channel interface
output [15:0] adc_dcfilter_data_out;
input [15:0] adc_dcfilter_data_in;
output [15:0] adc_iqcor_data;
output adc_enable;
output up_adc_pn_err;
output up_adc_pn_oos;
output up_adc_or;
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal signals
wire [15:0] adc_dcfilter_data_i_s;
wire [15:0] adc_dcfilter_data_q_s;
wire adc_iqcor_enb_s;
wire adc_dcfilt_enb_s;
wire [15:0] adc_dcfilt_offset_s;
wire [15:0] adc_dcfilt_coeff_s;
wire [15:0] adc_iqcor_coeff_1_s;
wire [15:0] adc_iqcor_coeff_2_s;
wire [ 3:0] adc_pnseq_sel_s;
wire adc_pn_err_s;
wire adc_pn_oos_s;
// iq correction inputs
assign adc_dcfilter_data_i_s = (IQSEL == 1) ? adc_dcfilter_data_in : adc_dcfilter_data_out;
assign adc_dcfilter_data_q_s = (IQSEL == 1) ? adc_dcfilter_data_out : adc_dcfilter_data_in;
axi_ad9652_pnmon i_pnmon (
.adc_clk (adc_clk),
.adc_data (adc_data),
.adc_pn_oos (adc_pn_oos_s),
.adc_pn_err (adc_pn_err_s),
.adc_pnseq_sel (adc_pnseq_sel_s));
generate
if (DP_DISABLE == 1) begin
assign adc_dcfilter_data_out = adc_data;
end else begin
ad_dcfilter i_ad_dcfilter (
.clk (adc_clk),
.valid (1'b1),
.data (adc_data),
.valid_out (),
.data_out (adc_dcfilter_data_out),
.dcfilt_enb (adc_dcfilt_enb_s),
.dcfilt_coeff (adc_dcfilt_coeff_s),
.dcfilt_offset (adc_dcfilt_offset_s));
end
endgenerate
generate
if (DP_DISABLE == 1) begin
assign adc_iqcor_data = (IQSEL == 1) ? adc_dcfilter_data_q_s : adc_dcfilter_data_i_s;
end else begin
ad_iqcor #(.IQSEL(IQSEL)) i_ad_iqcor (
.clk (adc_clk),
.valid (1'b1),
.data_i (adc_dcfilter_data_i_s),
.data_q (adc_dcfilter_data_q_s),
.valid_out (),
.data_out (adc_iqcor_data),
.iqcor_enable (adc_iqcor_enb_s),
.iqcor_coeff_1 (adc_iqcor_coeff_1_s),
.iqcor_coeff_2 (adc_iqcor_coeff_2_s));
end
endgenerate
up_adc_channel #(.PCORE_ADC_CHID(CHID)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),
.adc_iqcor_enb (adc_iqcor_enb_s),
.adc_dcfilt_enb (adc_dcfilt_enb_s),
.adc_dfmt_se (),
.adc_dfmt_type (),
.adc_dfmt_enable (),
.adc_dcfilt_offset (adc_dcfilt_offset_s),
.adc_dcfilt_coeff (adc_dcfilt_coeff_s),
.adc_iqcor_coeff_1 (adc_iqcor_coeff_1_s),
.adc_iqcor_coeff_2 (adc_iqcor_coeff_2_s),
.adc_pnseq_sel (adc_pnseq_sel_s),
.adc_data_sel (),
.adc_pn_err (adc_pn_err_s),
.adc_pn_oos (adc_pn_oos_s),
.adc_or (adc_or),
.up_adc_pn_err (up_adc_pn_err),
.up_adc_pn_oos (up_adc_pn_oos),
.up_adc_or (up_adc_or),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_decimation_m (),
.up_usr_decimation_n (),
.adc_usr_datatype_be (1'b0),
.adc_usr_datatype_signed (1'b1),
.adc_usr_datatype_shift (8'd0),
.adc_usr_datatype_total_bits (8'd16),
.adc_usr_datatype_bits (8'd16),
.adc_usr_decimation_m (16'd1),
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; queue<long long> q1; long long a[20005]; long long l, r; int main(void) { int i = 0; int j; cin >> l >> r; q1.push(0); while (1) { a[i] = q1.front() * 10 + 4; i++; if (a[i - 1] >= r) break; q1.push(a[i - 1]); a[i] = q1.front() * 10 + 7; i++; if (a[i - 1] >= r) break; q1.push(a[i - 1]); q1.pop(); } long long sum = 0; for (j = 0; j < i; j++) { if (l <= a[j] && r > a[j]) { sum += a[j] * (a[j] + 1 - l); l = a[j] + 1; } else if (l <= a[j] && r <= a[j]) { sum += a[j] * (r + 1 - l); break; } } cout << sum << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; vector<long long> factors(long long n) { vector<long long> first; long long tem = 1; for (long long x = 2; x * x <= n; x++) { while (n % x == 0) { first.push_back(x); n /= x; } } if (n > 1) first.push_back(n); return first; } long long stringToint(string str) { int num = stoi(str); return num; } int hamming(int a, int b) { return __builtin_popcount(a ^ b); } bool cmp(int a, int b) { return a > b; } void reset() { for (int i = 0; i < 200000 + 100; i++) { } } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); int n, d; while (cin >> n >> d) { int m; cin >> m; for (int i = 0, x, y; i < m; i++) { cin >> x >> y; if (abs(x - y) >= 0 && abs(x - y) <= d && x + y <= n + n - d && x + y >= d && (x + y != 0 || x - y != 0)) cout << YES n ; else cout << NO n ; } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int mn = 101000; vector<int> e[mn]; int c[mn], s[mn], sc[mn], sv[mn]; int R[mn], vis[mn]; int n, m, i, j, k, nc, tt; long long ans; bool cmpc(int i, int j) { return c[i] > c[j]; } bool cmps(int i, int j) { return s[i] < s[j]; } void add(int i, int d, int l) { s[0] = l; int j = lower_bound(sv + 1, sv + 1 + n, 0, cmps) - sv; if (j == n + 1) return; j = sv[j]; if (s[j] != l || c[j] > d) return; e[j].push_back(i); } inline bool dfs(int r) { int p, i; vis[r] = nc; for (p = 0; p < e[r].size(); ++p) { i = e[r][p]; if (R[i] == 0 || (vis[R[i]] != nc && dfs(R[i]))) { R[i] = r; return 1; } } return 0; } int main() { ios_base::sync_with_stdio(0); cin >> n; for (i = 1; i <= n; ++i) cin >> c[i] >> s[i]; for (i = 1; i <= n; ++i) sc[i] = sv[i] = i; sort(sc + 1, sc + 1 + n, cmpc); sort(sv + 1, sv + 1 + n, cmps); cin >> m; for (i = 1; i <= m; ++i) { cin >> j >> k; add(i, j, k); add(i, j, k + 1); } for (i = 1; i <= n; ++i) { ++nc; if (dfs(sc[i])) ++tt, ans += c[sc[i]]; } cout << ans << endl; cout << tt << endl; for (i = 1; i <= m; ++i) if (R[i]) cout << i << << R[i] << endl; return 0; } |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module cf_jesd_mon (
// gtx interface
rx_rst,
rx_clk,
rx_data,
rx_charisk,
rx_disperr,
rx_notintable,
// jesd interface
rx_sysref,
rx_sync,
// jesd controls
rx_sysref_enb,
rx_sync_enb,
rx_fsm,
// monitor signals
mon_trigger,
mon_data);
// gtx interface
input rx_rst;
input rx_clk;
input [31:0] rx_data;
input [ 3:0] rx_charisk;
input [ 3:0] rx_disperr;
input [ 3:0] rx_notintable;
// jesd interface
input rx_sysref;
input rx_sync;
// jesd controls
output rx_sysref_enb;
output rx_sync_enb;
output [ 3:0] rx_fsm;
// monitor signals
output [ 3:0] mon_trigger;
output [55:0] mon_data;
// the receive state machine parameters
parameter RX_FSM_IDLE = 'h0;
parameter RX_FSM_CGS = 'h1;
parameter RX_FSM_SYSREF = 'h2;
parameter RX_FSM_SYNC = 'h3;
parameter RX_FSM_DATA = 'h4;
reg rx_sysref_enb = 'd0;
reg rx_sync_enb = 'd0;
reg [ 3:0] rx_fsm = 'd0;
reg rx_valid_k = 'd0;
reg [ 4:0] rx_cgs_count = 'd0;
wire rx_ilas_f_s;
wire rx_ilas_q_s;
wire rx_ilas_a_s;
wire rx_ilas_r_s;
wire rx_cgs_k_s;
wire [ 3:0] rx_valid_k_s;
// monitor interface
assign mon_data[55:55] = rx_ilas_f_s;
assign mon_data[54:54] = rx_ilas_q_s;
assign mon_data[53:53] = rx_ilas_a_s;
assign mon_data[52:52] = rx_ilas_r_s;
assign mon_data[51:51] = rx_cgs_k_s;
assign mon_data[50:50] = rx_valid_k;
assign mon_data[49:49] = rx_sysref_enb;
assign mon_data[48:48] = rx_sync_enb;
assign mon_data[47:44] = rx_fsm;
assign mon_data[43:40] = rx_charisk;
assign mon_data[39:36] = rx_disperr;
assign mon_data[35:32] = rx_notintable;
assign mon_data[31: 0] = rx_data;
assign mon_trigger = {rx_valid_k, rx_fsm[2:0]};
// this state machine is just to monitor whether the jesd lanes are going through all
// the intial synchronization phase and asserts sync and/or system ref accordingly.
// after reset, it waits for cgs signals, followed by all the ilas frames then moves
// to the data phase.
always @(posedge rx_clk) begin
if (rx_rst == 1'b1) begin
rx_sysref_enb <= 'd0;
rx_sync_enb <= 'd0;
rx_fsm <= 'd0;
end else begin
case (rx_fsm)
RX_FSM_DATA: begin // stay in data phase until sync is asserted (restart)
rx_sysref_enb <= 'd0;
rx_sync_enb <= 'd1;
if (rx_sync == 1'b0) begin
rx_fsm <= RX_FSM_IDLE;
end else begin
rx_fsm <= RX_FSM_DATA;
end
end
RX_FSM_SYNC: begin // if sync is deasserted, move to ilas/data phase
rx_sysref_enb <= 'd0;
rx_sync_enb <= 'd1;
if (rx_sync == 1'b1) begin
rx_fsm <= RX_FSM_DATA;
end else begin
rx_fsm <= RX_FSM_SYNC;
end
end
RX_FSM_SYSREF: begin // assert sysref after cgs state
rx_sysref_enb <= 'd1;
rx_sync_enb <= 'd0;
if (rx_sysref == 1'b1) begin
rx_fsm <= RX_FSM_SYNC;
end else begin
rx_fsm <= RX_FSM_SYSREF;
end
end
RX_FSM_CGS: begin // leave cgs state after 256 (randomly picked) comma characters
rx_sysref_enb <= 'd0;
rx_sync_enb <= 'd0;
if (rx_cgs_count[4] == 1'b0) begin
rx_fsm <= RX_FSM_SYSREF;
end else begin
rx_fsm <= RX_FSM_CGS;
end
end
RX_FSM_IDLE: begin // reset gtx/jesd, and check for cgs
rx_sysref_enb <= 'd0;
rx_sync_enb <= 'd0;
rx_fsm <= RX_FSM_CGS;
end
default: begin
rx_sysref_enb <= 'd0;
rx_sync_enb <= 'd0;
rx_fsm <= RX_FSM_IDLE;
end
endcase
end
end
// decode the jesd cgs and ilas signals, this is a very straight forward monitoring.
// we are just checking whether the ilas signals are present or not.
// the detailed functionality already exists inside the jesd core.
always @(posedge rx_clk) begin
if (rx_rst == 1'b1) begin
rx_valid_k <= 'd0;
rx_cgs_count <= 5'h10;
end else begin
rx_valid_k <= (rx_valid_k_s == 4'd0) ? 1'b0 : 1'b1;
if (rx_cgs_k_s == 1'b0) begin
rx_cgs_count <= 5'h10;
end else if (rx_cgs_count[4] == 1'b1) begin
rx_cgs_count <= rx_cgs_count + 1'b1;
end
end
end
// the following logic decodes ilas frames and are just looking for specific code
// words, these are defined by jesd specifications.
assign rx_ilas_f_s =
(((rx_data[31:24] == 8'hfc) && (rx_valid_k_s[ 3] == 1'b1)) ||
((rx_data[23:16] == 8'hfc) && (rx_valid_k_s[ 2] == 1'b1)) ||
((rx_data[15: 8] == 8'hfc) && (rx_valid_k_s[ 1] == 1'b1)) ||
((rx_data[ 7: 0] == 8'hfc) && (rx_valid_k_s[ 0] == 1'b1))) ? 1'b1 : 1'b0;
assign rx_ilas_q_s =
(((rx_data[31:24] == 8'h9c) && (rx_valid_k_s[ 3] == 1'b1)) ||
((rx_data[23:16] == 8'h9c) && (rx_valid_k_s[ 2] == 1'b1)) ||
((rx_data[15: 8] == 8'h9c) && (rx_valid_k_s[ 1] == 1'b1)) ||
((rx_data[ 7: 0] == 8'h9c) && (rx_valid_k_s[ 0] == 1'b1))) ? 1'b1 : 1'b0;
assign rx_ilas_a_s =
(((rx_data[31:24] == 8'h7c) && (rx_valid_k_s[ 3] == 1'b1)) ||
((rx_data[23:16] == 8'h7c) && (rx_valid_k_s[ 2] == 1'b1)) ||
((rx_data[15: 8] == 8'h7c) && (rx_valid_k_s[ 1] == 1'b1)) ||
((rx_data[ 7: 0] == 8'h7c) && (rx_valid_k_s[ 0] == 1'b1))) ? 1'b1 : 1'b0;
assign rx_ilas_r_s =
(((rx_data[31:24] == 8'h1c) && (rx_valid_k_s[ 3] == 1'b1)) ||
((rx_data[23:16] == 8'h1c) && (rx_valid_k_s[ 2] == 1'b1)) ||
((rx_data[15: 8] == 8'h1c) && (rx_valid_k_s[ 1] == 1'b1)) ||
((rx_data[ 7: 0] == 8'h1c) && (rx_valid_k_s[ 0] == 1'b1))) ? 1'b1 : 1'b0;
assign rx_cgs_k_s =
(((rx_data[31:24] == 8'hbc) && (rx_valid_k_s[ 3] == 1'b1)) &&
((rx_data[23:16] == 8'hbc) && (rx_valid_k_s[ 2] == 1'b1)) &&
((rx_data[15: 8] == 8'hbc) && (rx_valid_k_s[ 1] == 1'b1)) &&
((rx_data[ 7: 0] == 8'hbc) && (rx_valid_k_s[ 0] == 1'b1))) ? 1'b1 : 1'b0;
// validate all characters
assign rx_valid_k_s = rx_charisk & (~rx_disperr) & (~rx_notintable);
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; long long a[100005]; long long b[100005]; long long x; long long n, m; long long c[100005]; long long d[100005]; void solve() { cin >> n >> m; for (long long i = 0; i < n; i++) { cin >> a[i]; if (i) a[i] += a[i - 1]; c[i + 1] = 1e9; } for (long long i = 0; i < m; i++) { cin >> b[i]; if (i) b[i] += b[i - 1]; d[i + 1] = 1e10; } cin >> x; long long fans = 0; for (long long i = 0; i < n; i++) { for (long long j = i; j < n; j++) { long long l = j - i + 1; if (i) c[l] = min(c[l], a[j] - a[i - 1]); else c[l] = min(c[l], a[j]); } } for (long long i = 0; i < m; i++) { for (long long j = i; j < m; j++) { long long l = j - i + 1; if (i) d[l] = min(d[l], b[j] - b[i - 1]); else d[l] = min(d[l], b[j]); } } for (long long i = 1; i <= n; i++) { for (long long j = 1; j <= m; j++) { if (c[i] * d[j] <= x) { fans = max(fans, i * j); } } } cout << fans; } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long T; T = 1; while (T--) { solve(); } return 0; } |
/*
* @Author: tmh
* @Date: 2017-07-25 20:02:24
* @File Name: PC.v
*/
`include "define.v"
module PC (
input clk , // Clock
input rst_n , // Asynchronous reset active low
input [ 8:0] IR , // Instruction in
input [ `EX_STATE_BITS-1:0] executeState, // Execute State
input [ `FE_STATE_BITS-1:0] fetchState , // Fetch State
input [`ALU_STATUS_WIDTH-1:0] aluStatusIn , // ALU State in
input [ `DATA_WIDTH-1:0] gprIn , // gpr In
input [ `PC_WIDTH-1:0] stackIn , // Stack in
input [ 2:0] writeCommand, // GPR write command
input [ 4:0] gprFSRIn , // gprFSRIn
output [ `PC_WIDTH-1:0] PC , // PC Register out
output goto ,
output skip
);
reg[`PC_WIDTH-1:0] rPC;
reg rgoto;
reg rskip;
assign PC = rPC;
assign goto = rgoto;
assign skip = rskip;
always @(posedge clk) begin
if (!rst_n) begin
rPC <= `PC_WIDTH'b0;
rskip <= 1'b0;
rgoto <= 1'b0;
end
else begin
case (fetchState)
`FE_Q1: begin
if (!rgoto) begin
rPC <= rPC + 1'b1;
end
end
`FE_Q2, `FE_Q3: begin
end
`FE_Q4: begin
end
endcase
case (executeState)
`EX_Q1: begin
if (rskip | rgoto) begin
rskip <= 1'b0;
rgoto <= 1'b0;
end
end
`EX_Q2: begin
end
`EX_Q3: begin
end
`EX_Q4_CLRF: begin
end
`EX_Q4_CLRW: begin
end
`EX_Q4_FSZ: begin
if (aluStatusIn[2]) begin
rskip <= 1'b1;
end
end
`EX_Q4_MOVF: begin
end
`EX_Q4_MOVWF: begin
end
`EX_Q4_BXF: begin
end
`EX_Q4_BTFSX: begin
case (IR[8])
1'b1: begin
if(gprIn[IR[7:5]]) begin
rskip <= 1'b1;
end
end
1'b0: begin
if(!gprIn[IR[7:5]]) begin
rskip <= 1'b1;
end
end
endcase
end
`EX_Q4_CALL: begin
rPC <= {1'b0, IR[7:0]};
rskip <= 1'b1;
rgoto <= 1'b1;
end
`EX_Q4_CLRWDT: begin
end
`EX_Q4_GOTO: begin
rPC <= IR[8:0];
rskip <= 1;
rgoto <= 1;
end
`EX_Q4_MOVLW: begin
end
`EX_Q4_OPTION: begin
end
`EX_Q4_RETLW: begin
rPC <= stackIn;
rskip <= 1'b1;
rgoto <= 1'b1;
end
`EX_Q4_SLEEP: begin
end
`EX_Q4_TRIS: begin
end
`EX_Q4_ELSE: begin
end
`EX_Q4_ALUXLW: begin
end
`EX_Q4_NOP: begin
end
default: ;
endcase
if (writeCommand[1] && (gprFSRIn[4:0] == `ADDR_PCL)) begin
rPC <= {1'b0, IR[7:0]};
rskip <= 1'b1;
end
end
end
endmodule |
#include <bits/stdc++.h> const int N = 1e5 + 5; const int K = 655; const int mod = 998244353; int T; int n, a[N]; int q[K], v[K], w[K], top = 0; int q2[K], v2[K], w2[K], top2 = 0; int MOD(int x) { return x >= mod ? x - mod : x; } int u(int x, int y) { return (x + y - 1) / y; } int main() { scanf( %d , &T); while (T--) { scanf( %d , &n); for (int i = 1; i <= n; ++i) scanf( %d , &a[i]); q[top = 1] = a[n], v[1] = 0, w[1] = 1; int ans = 0; for (int i = n - 1; i >= 1; --i) { top2 = 0; for (int l = 1, r, j = 0; l <= a[i]; l = r + 1) { r = a[i] / (a[i] / l); q2[++top2] = a[i] / l; v2[top2] = 0; w2[top2] = (l == 1); if (i == 1) { int tmp = 1; } while (j < top && u(a[i], q[j + 1]) >= l && u(a[i], q[j + 1]) <= r) { ++j; v2[top2] = MOD(v2[top2] + MOD(v[j] + (long long)(u(a[i], q[j]) - 1) * w[j] % mod)); w2[top2] = w2[top2] + w[j]; } } for (int j = 1; j <= top2; ++j) { q[j] = q2[j]; v[j] = v2[j]; w[j] = w2[j]; } top = top2; for (int j = 1; j <= top; ++j) ans = MOD(ans + v[j]); } printf( %d n , ans); } return 0; } |
#include <bits/stdc++.h> using namespace std; void solve() {} const long long maxn = 1050; long long n, a, b; long long ans[maxn][maxn]; void no() { cout << NO << n ; exit(0); } signed main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n >> a >> b; if (min(a, b) > 1) no(); if ((n == 2 or n == 3) and a == 1 and b == 1) no(); long long c = 1, d = 0; if (b != 1) { swap(a, b); swap(c, d); } for (long long i = 1; i <= n; i++) { ans[i][i] = 0; for (long long j = 1; j <= n; j++) { if (i != j) { ans[i][j] = ans[j][i] = d; } } } for (long long i = a; i + 1 <= n; i++) { ans[i][i + 1] = ans[i + 1][i] = c; } cout << YES << n ; for (long long i = 1; i <= n; i++) { for (long long j = 1; j <= n; j++) { cout << ans[i][j]; } cout << n ; } } |
#include <bits/stdc++.h> using namespace std; const int maxn = 100005; const int maxd = 205; struct Node { int l, d; } leg[maxn]; bool operator<(const Node &a, const Node &b) { return a.l > b.l; } int n, tot[maxd], td = 0, md = 0; int Solve(int st, int ed) { int cnt = ed - st; int res = td; for (int i = md; i >= 0 && cnt > 0; i--) { res -= min(cnt, tot[i]) * i; cnt -= min(cnt, tot[i]); } return res; } int main() { cin >> n; for (int i = 0; i < n; i++) cin >> leg[i].l; for (int i = 0; i < n; i++) cin >> leg[i].d; for (int i = 0; i < n; i++) md = max(md, leg[i].d); sort(leg, leg + n); for (int i = 0; i < n; i++) { tot[leg[i].d]++; td += leg[i].d; } int p = 0; int res = INT_MAX, tot_d = 0; while (p < n) { int p1 = p + 1; while (p1 < n && leg[p1].l == leg[p].l) p1++; p1--; for (int i = p; i <= p1; i++) { tot[leg[i].d]--; td -= leg[i].d; } int tmp = tot_d + Solve(p, p1); res = min(tmp, res); for (int i = p; i <= p1; i++) tot_d += leg[i].d; p = p1 + 1; } cout << res << endl; return 0; } |
// -----------------------------------------------------------------------------
// -- --
// -- (C) 2016-2022 Revanth Kamaraj (krevanth) --
// -- --
// -- --------------------------------------------------------------------------
// -- --
// -- This program is free software; you can redistribute it and/or --
// -- modify it under the terms of the GNU General Public License --
// -- as published by the Free Software Foundation; either version 2 --
// -- of the License, or (at your option) any later version. --
// -- --
// -- This program is distributed in the hope that it will be useful, --
// -- but WITHOUT ANY WARRANTY; without even the implied warranty of --
// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
// -- GNU General Public License for more details. --
// -- --
// -- You should have received a copy of the GNU General Public License --
// -- along with this program; if not, write to the Free Software --
// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA --
// -- 02110-1301, USA. --
// -- --
// -----------------------------------------------------------------------------
// -- --
// -- Examines TLB entries to authorize access. Purely combo logic. --
// -- --
// -----------------------------------------------------------------------------
`default_nettype none
module zap_tlb_check ( // ZAP TLB Processing Logic.
i_mmu_en, // MMU enable.
// Dynamics
i_va, // Virtual address.
i_rd, // WB rd.
i_wr, // WB wr.
// Static almost.
i_cpsr,
i_sr,
i_dac_reg,
// Data from TLB dist RAMs.
i_sptlb_rdata, i_sptlb_rdav,
i_lptlb_rdata, i_lptlb_rdav,
i_setlb_rdata, i_setlb_rdav,
i_fptlb_rdata, i_fptlb_rdav,
// Outputs to other units.
o_walk, // Need to page walk.
o_fsr, // FSR.
o_far, // FAR. 0 means no fault. This is a 4-bit number.
o_cacheable, // Cacheable based on PTE.
o_phy_addr // Physical address.
);
// Pass this from top.
parameter LPAGE_TLB_ENTRIES = 8;
parameter SPAGE_TLB_ENTRIES = 8;
parameter SECTION_TLB_ENTRIES = 8;
parameter FPAGE_TLB_ENTRIES = 8;
`include "zap_localparams.vh"
`include "zap_defines.vh"
`include "zap_functions.vh"
input wire i_mmu_en; // MMU enable.
input wire [31:0] i_va; // Virtual address.
input wire i_rd; // Read request.
input wire i_wr; // Write request.
input wire [31:0] i_cpsr; // CPSR.
input wire [1:0] i_sr; // Status Register.
input wire [31:0] i_dac_reg; // Domain Access Control Register.
input wire [`SPAGE_TLB_WDT -1:0] i_sptlb_rdata; // Small page TLB.
input wire i_sptlb_rdav; // TLB entry valid.
input wire [`LPAGE_TLB_WDT -1:0] i_lptlb_rdata; // Large page TLB read data.
input wire i_lptlb_rdav; // Large page TLB valid.
input wire [`SECTION_TLB_WDT-1:0] i_setlb_rdata; // Small page TLB read data.
input wire i_setlb_rdav; // Small page TLB valid.
input wire [`FPAGE_TLB_WDT-1:0] i_fptlb_rdata; // Fine page TLB read data.
input wire i_fptlb_rdav; // Fine page TLB valid.
output reg o_walk; // Signal page walk.
output reg [7:0] o_fsr; // FSR. 0 means all OK.
output reg [31:0] o_far; // Fault Address Register.
output reg o_cacheable; // Cacheble stats of the PTE.
output reg [31:0] o_phy_addr; // Physical address.
// ----------------------------------------------------------------------------
always @*
begin
// Default values. Taken for MMU disabled esp.
o_fsr = 0; // No fault.
o_far = i_va; // Fault address.
o_phy_addr = i_va; // VA = PA
o_walk = 0; // Walk disabled.
o_cacheable = 0; // Uncacheable.
if ( i_mmu_en && (i_rd|i_wr) ) // MMU enabled.
begin
if ( (i_sptlb_rdata[`SPAGE_TLB__TAG] == i_va[`VA__SPAGE_TAG]) && i_sptlb_rdav )
begin
// Entry found in small page TLB.
o_fsr = get_fsr
(
1'd0, 1'd1, 1'd0, 1'd0, // Small page.
i_va[`VA__SPAGE_AP_SEL],
i_cpsr[4:0] == USR,
i_rd,
i_wr,
i_sr,
i_dac_reg,
i_sptlb_rdata
) ;
o_phy_addr = {i_sptlb_rdata[`SPAGE_TLB__BASE],
i_va[11:0]};
o_cacheable = i_sptlb_rdata[`SECTION_TLB__CB] >> 1;
end
else if ( (i_lptlb_rdata[`LPAGE_TLB__TAG] == i_va[`VA__LPAGE_TAG]) && i_lptlb_rdav )
begin
// Entry found in large page TLB.
o_fsr = get_fsr
(
1'd0, 1'd0, 1'd1, 1'd0, // Large page.
i_va[`VA__LPAGE_AP_SEL],
i_cpsr[4:0] == USR,
i_rd,
i_wr,
i_sr,
i_dac_reg,
i_lptlb_rdata
) ;
o_phy_addr = {i_lptlb_rdata[`LPAGE_TLB__BASE],
i_va[15:0]};
o_cacheable = i_lptlb_rdata[`LPAGE_TLB__CB] >> 1;
end
else if ( (i_setlb_rdata[`SECTION_TLB__TAG] == i_va[`VA__SECTION_TAG]) && i_setlb_rdav )
begin
// Entry found in section TLB.
o_fsr = get_fsr
(
1'd1, 1'd0, 1'd0, 1'd0, // Section.
2'd0, // DONT CARE. Sections do not further divisions in AP SEL.
i_cpsr[4:0] == USR,
i_rd,
i_wr,
i_sr,
i_dac_reg,
i_setlb_rdata
) ;
o_phy_addr = {i_setlb_rdata[`SECTION_TLB__BASE],
i_va[19:0]};
o_cacheable = i_setlb_rdata[`SECTION_TLB__CB] >> 1;
end
else if( (i_fptlb_rdata[`FPAGE_TLB__TAG] == i_va[`VA__FPAGE_TAG]) && i_fptlb_rdav )
begin
// Entry found in fine page TLB.
o_fsr = get_fsr
(
1'd0, 1'd0, 1'd0, 1'd1,
2'd0,
i_cpsr[4:0] == USR,
i_rd,
i_wr,
i_sr,
i_dac_reg,
i_fptlb_rdata
);
end
else
begin
// Trigger TLB walk.
o_walk = 1'd1;
end
end // Else MMU disabled.
end
// ----------------------------------------------------------------------------
function [7:0] get_fsr ( // Return 0 means OK to access else is a valid FSR.
input section, spage, lpage, fpage, // Select one.
input [1:0] ap_sel, // AP sel bits. dont care for sections or fine pages.
input user, rd, wr, // Access properties.
input [1:0] sr, // S and R bits.
input [31:0] dac_reg, // DAC register.
input [63:0] tlb // TLB entry.
);
reg [3:0] apsr; // Concat of AP and SR.
reg [1:0] dac; // DAC bits.
begin
// Get AP and DAC.
if ( section ) // section.
begin
apsr = (tlb [ `SECTION_TLB__AP ]);
dac = (dac_reg >> (tlb [ `SECTION_TLB__DAC_SEL ] << 1));
end
else if ( spage ) // small page.
begin
apsr = (tlb [ `SPAGE_TLB__AP ]) >> (ap_sel << 1);
dac = (dac_reg >> (tlb [ `SPAGE_TLB__DAC_SEL ] << 1));
end
else if ( fpage ) // fine page
begin
apsr = (tlb [ `FPAGE_TLB__AP ]);
dac = (dac_reg >> (tlb [ `FPAGE_TLB__DAC_SEL ] << 1));
end
else // large page.
begin
apsr = (tlb [ `LPAGE_TLB__AP ]) >> (ap_sel << 1);
dac = (dac_reg >> (tlb [ `LPAGE_TLB__DAC_SEL ] << 1));
end
// Concat AP and SR bits.
apsr[3:2] = apsr[1:0];
apsr[1:0] = sr[1:0];
case(dac)
DAC_MANAGER: get_fsr = 0; // No fault.
DAC_CLIENT : get_fsr = is_apsr_ok ( user, rd, wr, apsr ) ? 0 :
(
section ? {tlb[`SECTION_TLB__DAC_SEL], FSR_SECTION_PERMISSION_FAULT}:
spage ? {tlb[`SPAGE_TLB__DAC_SEL] , FSR_PAGE_PERMISSION_FAULT }:
fpage ? {tlb[`FPAGE_TLB__DAC_SEL] , FSR_PAGE_PERMISSION_FAULT }:
{tlb[`LPAGE_TLB__DAC_SEL] , FSR_PAGE_PERMISSION_FAULT }
);
default : get_fsr =
section ? {tlb[`SECTION_TLB__DAC_SEL], FSR_SECTION_DOMAIN_FAULT} :
spage ? {tlb[`SPAGE_TLB__DAC_SEL], FSR_PAGE_DOMAIN_FAULT } :
fpage ? {tlb[`FPAGE_TLB__DAC_SEL], FSR_PAGE_DOMAIN_FAULT } :
{tlb[`LPAGE_TLB__DAC_SEL], FSR_PAGE_DOMAIN_FAULT } ;
endcase
end
endfunction
// ----------------------------------------------------------------------------
//
// Function to check APSR bits.
//
// Returns 0 for failure, 1 for okay.
// Checks AP and SR bits.
//
localparam APSR_BAD = 1'd0;
localparam APSR_OK = 1'd1;
function is_apsr_ok ( input user, input rd, input wr, input [3:0] apsr);
reg x;
begin
x = APSR_BAD; // Assume fail.
casez (apsr)
APSR_NA_NA: x = APSR_BAD; // No access.
APSR_RO_RO: x = !wr; // Reads allowed for all.
APSR_RO_NA: x = !user && rd; // Only kernel reads.
APSR_RW_NA: x = !user; // Only kernel access.
APSR_RW_RO: x = !user | (user && rd); // User RO, Kernel RW.
APSR_RW_RW: x = APSR_OK; // Grant all the time.
default : x = APSR_BAD; // Deny all the time.
endcase
// Assign to function. Return.
is_apsr_ok = x;
end
endfunction
endmodule // zap_tlb_check.v
`default_nettype wire
// ----------------------------------------------------------------------------
// EOF
// ----------------------------------------------------------------------------
|
#include <bits/stdc++.h> const int MOD = 1000000007; const int Inv2 = 500000004; inline int mul(int x, int y) { return (long long)x * (long long)y % MOD; } inline int add(int x, int y) { int r = x + y; if (r >= MOD) r -= MOD; return r; } inline int qpow(int a, int p) { int x = a, ans = 1; while (p) { if (p & 1) ans = mul(ans, x); x = mul(x, x); p >>= 1; } return ans; } using namespace std; template <typename T> inline void read(T &x) { char ch; while ((ch = getchar()), (ch < 0 || ch > 9 )) ; x = ch - 0 ; while ((ch = getchar()), (ch >= 0 && ch <= 9 )) x = x * 10 + (ch - 0 ); } inline int readbin(int *str) { char ch; int len = 1; while ((ch = getchar()), (ch < 0 || ch > 1 )) ; *(str++) = ch - 0 ; while ((ch = getchar()), (ch >= 0 && ch <= 1 )) *(str++) = ch - 0 , len++; return len; } void fwt(int A[], int n) { int i, h, k, A0, A1; for (h = 2; h <= n; h <<= 1) { for (i = 0; i < n; i += h) { for (k = i; k < i + (h / 2); k++) { A0 = A[k]; A1 = A[k + (h / 2)]; A[k] = (A0 + A1) % MOD; A[k + (h / 2)] = (A0 - A1) % MOD; } } } } void ifwt(int A[], int n) { int i, h, k, A0, A1; for (h = 2; h <= n; h <<= 1) { for (i = 0; i < n; i += h) { for (k = i; k < i + (h / 2); k++) { A0 = A[k]; A1 = A[k + (h / 2)]; A[k] = mul(Inv2, A0 + A1); A[k + (h / 2)] = mul(Inv2, A0 - A1); } } } } const int MAXN = 5 + (1 << 20); int A[MAXN], P[MAXN]; int N, NB; int main() { int i; read(NB); N = readbin(A); fwt(A, N); for (i = 0; i < N; i++) P[i] = mul(A[i], A[i]); ifwt(P, N); int Ans = 0; for (i = 0; i < N; i++) Ans = add(Ans, mul(P[i], 1 << (NB - __builtin_popcount(i)))); Ans = mul(Ans, 3); printf( %d , Ans); } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); int n, r; cin >> n >> r; double alpha = 90.0 - 180.0 / n; double val = cos(alpha * 3.14159265 / 180.0); double ans = val * (double)r / (1 - val); cout << fixed << setprecision(6) << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T> inline void read(T& t) { T f = 1; char ch = getchar(); t = 0; while (ch < 0 || ch > 9 ) { if (ch == - ) f = -f; ch = getchar(); } while (ch >= 0 && ch <= 9 ) t = t * 10 + ch - 0 , ch = getchar(); t *= f; } template <typename T, typename... Args> inline void read(T& t, Args&... args) { read(t); read(args...); } int t, T, n, m; int n1 = 1e9, n2 = -1e9; int l[100005], r[100005]; char ans[100005]; inline bool pd(int i, int x) { return l[i] <= x && x <= r[i]; } vector<int> edge[100005]; bool dfs(int now) { for (int i = 0; i < edge[now].size(); i++) if (ans[edge[now][i]] == 0) { ans[edge[now][i]] = 3 - ans[now]; if (dfs(edge[now][i]) == 0) return 0; } else if (ans[edge[now][i]] == ans[now]) return 0; return 1; } int main() { read(t, T, n, m); for (int i = 1; i <= n; i++) read(l[i], r[i]), n1 = min(n1, r[i]), n2 = max(n2, l[i]); if (n1 + n2 < t) n2 = t - n1; if (n1 + n2 > T) n1 = T - n2; if (n1 < 0 || n2 < 0) return printf( IMPOSSIBLE n ), 0; for (int i = 1; i <= n; i++) { if (pd(i, n1) == 0 && pd(i, n2) == 0) return printf( IMPOSSIBLE n ), 0; if (pd(i, n1) == 1 && pd(i, n2) == 0) ans[i] = 1; if (pd(i, n1) == 0 && pd(i, n2) == 1) ans[i] = 2; } for (int i = 1, x, y; i <= m; i++) { read(x, y); edge[x].push_back(y); edge[y].push_back(x); } for (int i = 1; i <= n; i++) if (ans[i]) if (dfs(i) == 0) return printf( IMPOSSIBLE n ), 0; for (int i = 1; i <= n; i++) if (ans[i] == 0) { ans[i] = 1; if (dfs(i) == 0) return printf( IMPOSSIBLE n ), 0; } printf( POSSIBLE n%d %d n , n1, n2); for (int i = 1; i <= n; i++) ans[i] += 0 ; printf( %s n , ans + 1); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 5; string s[N]; int n, k, fa[N], len[N], ch[N][26], root = 1, last = 1, tot = 1, times[N]; void insert(int x) { int now = ++tot, pre = last; last = now, len[now] = len[pre] + 1; for (; pre && !ch[pre][x]; pre = fa[pre]) ch[pre][x] = now; if (!pre) fa[now] = root; else { int q = ch[pre][x]; if (len[q] == len[pre] + 1) fa[now] = q; else { int nows = ++tot; len[nows] = len[pre] + 1; memcpy(ch[nows], ch[q], sizeof(ch[q])); fa[nows] = fa[q], fa[q] = fa[now] = nows; for (; pre && ch[pre][x] == q; pre = fa[pre]) ch[pre][x] = nows; } } } long long vis[N], sum[N]; void getcnt() { for (int i = 1; i <= n; i++) { int now = root; for (int j = 0; j < s[i].length(); j++) { now = ch[now][s[i][j] - a ]; int t = now; while (t && vis[t] != i) vis[t] = i, times[t]++, t = fa[t]; } } } void dfs(int x) { if (x == root || vis[x]) return; vis[x] = 1; dfs(fa[x]); sum[x] += sum[fa[x]]; } int main() { ios::sync_with_stdio(0); cin >> n >> k; for (int i = 1; i <= n; i++) cin >> s[i]; for (int i = 1; i <= n; i++) { last = 1; for (int j = 0; j < s[i].length(); j++) insert(s[i][j] - a ); } getcnt(); for (int i = 1; i <= tot; i++) sum[i] = (times[i] >= k) * (len[i] - len[fa[i]]); memset(vis, 0, sizeof(vis)); for (int i = 1; i <= tot; i++) dfs(i); for (int i = 1; i <= n; i++) { long long ans = 0, now = root; for (int j = 0; j < s[i].length(); j++) now = ch[now][s[i][j] - a ], ans += sum[now]; printf( %lld , ans); } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A211O_BLACKBOX_V
`define SKY130_FD_SC_LP__A211O_BLACKBOX_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a211o (
X ,
A1,
A2,
B1,
C1
);
output X ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A211O_BLACKBOX_V
|
module ADC_CTRL (
iRST,
iCLK,
iCLK_n,
iGO,
iCH,
oLED,
oDIN,
oCS_n,
oSCLK,
iDOUT
);
input iRST;
input iCLK;
input iCLK_n;
input iGO;
input [2:0] iCH;
output [7:0] oLED;
output oDIN;
output oCS_n;
output oSCLK;
input iDOUT;
reg data;
reg go_en;
wire [2:0] ch_sel;
reg sclk;
reg [3:0] cont;
reg [3:0] m_cont;
reg [11:0] adc_data;
reg [7:0] led;
assign oCS_n = ~go_en;
assign oSCLK = (go_en)? iCLK:1;
assign oDIN = data;
assign ch_sel = iCH;
assign oLED = led;
always@(posedge iGO or negedge iRST)
begin
if(!iRST)
go_en <= 0;
else
begin
if(iGO)
go_en <= 1;
end
end
always@(posedge iCLK or negedge go_en)
begin
if(!go_en)
cont <= 0;
else
begin
if(iCLK)
cont <= cont + 1;
end
end
always@(posedge iCLK_n)
begin
if(iCLK_n)
m_cont <= cont;
end
always@(posedge iCLK_n or negedge go_en)
begin
if(!go_en)
data <= 0;
else
begin
if(iCLK_n)
begin
if (cont == 2)
data <= iCH[2];
else if (cont == 3)
data <= iCH[1];
else if (cont == 4)
data <= iCH[0];
else
data <= 0;
end
end
end
always@(posedge iCLK or negedge go_en)
begin
if(!go_en)
begin
adc_data <= 0;
led <= 8'h00;
end
else
begin
if(iCLK)
begin
if (m_cont == 4)
adc_data[11] <= iDOUT;
else if (m_cont == 5)
adc_data[10] <= iDOUT;
else if (m_cont == 6)
adc_data[9] <= iDOUT;
else if (m_cont == 7)
adc_data[8] <= iDOUT;
else if (m_cont == 8)
adc_data[7] <= iDOUT;
else if (m_cont == 9)
adc_data[6] <= iDOUT;
else if (m_cont == 10)
adc_data[5] <= iDOUT;
else if (m_cont == 11)
adc_data[4] <= iDOUT;
else if (m_cont == 12)
adc_data[3] <= iDOUT;
else if (m_cont == 13)
adc_data[2] <= iDOUT;
else if (m_cont == 14)
adc_data[1] <= iDOUT;
else if (m_cont == 15)
adc_data[0] <= iDOUT;
else if (m_cont == 1)
led <= adc_data[11:4];
end
end
end
endmodule |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e3 + 5; int n, m, k; struct node { int x, y, step; }; char s[maxn][maxn]; bool vis[maxn][maxn][4]; int go[4][2] = {0, 1, 1, 0, 0, -1, -1, 0}; int bfs(int x, int y, int tx, int ty) { for (int i = 0; i < 4; ++i) vis[x][y][i] = 1; queue<node> q; node tmp, tem; tem.x = x, tem.y = y, tem.step = 0; q.push(tem); int xx, yy; while (!q.empty()) { tmp = q.front(); q.pop(); if (tmp.x == tx && tmp.y == ty) return tmp.step; for (int i = 0; i < 4; i++) { tem = tmp; tem.step++; for (int j = 1; j <= k; j++) { xx = tem.x + go[i][0]; yy = tem.y + go[i][1]; if (xx < 0 || xx > n) break; if (yy < 0 || yy > m) break; if (s[xx][yy] != . ) break; if (vis[xx][yy][i]) break; tem.x = xx; tem.y = yy; vis[xx][yy][i] = 1; q.push(tem); } } } return -1; } int main() { scanf( %d%d%d , &n, &m, &k); for (int i = 1; i <= n; i++) scanf( %s , s[i] + 1); int x, xx, y, yy; scanf( %d%d%d%d , &x, &y, &xx, &yy); printf( %d n , bfs(x, y, xx, yy)); return 0; } |
/*
* Copyright (c) 2001 Eric Brombaugh <>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// test_simple.v - testbench for simple.mcl behavioral output
// 01-22-01 E. Brombaugh
/*
* The ``simple'' module was generated by the synopsis module compiler
* and is typical of the modules it generates. The testbench was hand
* coded. This file was merged into a single file using the Verilog
* preprocessor.
*/
`timescale 1ns / 10 ps
module simple( y, a, b, c );
input [3:0] a;
input [3:0] b;
input [7:0] c;
output [8:0] y;
wire dpa_zero, dpa_one;
wire [8:0] y_1_;
assign dpa_zero= 1024'h0;
assign dpa_one= 1024'h1;
/* simple.mcl:4 module simple (y, a, b, c); */
/* simple.mcl:6 input signed [3:0] a, b; */
/* simple.mcl:7 input signed [7:0] c; */
/* simple.mcl:9 y = a*b+c; */
assign y_1_= ((a[2:0]-(a[3]<<3))*(b[2:0]-(b[3]<<3))+(c[6:0]-(c[7]<<7)));
/* simple.mcl:5 output signed [8:0] y; */
assign y = y_1_[8:0];
/* simple.mcl:4 module simple (y, a, b, c); */
/* simple.mcl:9 y = a*b+c; */
/*User Defined Aliases */
endmodule
module test_simple;
reg [15:0] count;
reg clk;
reg [3:0] a, b;
reg [7:0] c;
wire [8:0] y;
simple u1(y, a, b, c);
initial
begin
count = 0;
clk = 0;
a = 0;
b = 0;
c = 0;
end
always
#10 clk = ~clk;
always @(posedge clk)
begin
a = count[3:0];
b = count[7:4];
c = count[15:8];
#10
$display("%h %h %h %h", a, b, c, y);
count = count + 1;
if(count == 0)
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; string l; cin >> l; sort(l.begin(), l.end()); int a = 0, ans = 0; char p = l[0]; for (;;) { if (l[0] == p) { a++; l.erase(l.begin()); } else { ans = max(ans, a); if (l.size() > 0) { p = l[0]; a = 0; } else break; } } if (ans > k) cout << NO ; else cout << YES ; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long M = 998244353; long long modpow(long long base, long long exp, long long modulus = M) { base %= modulus; long long result = 1; while (exp > 0) { if (exp & 1) result = (result * base) % modulus; base = (base * base) % modulus; exp >>= 1; } return result; } long long modinv(long long a, long long mod = M) { return modpow(a, mod - 2); } string s; int n; long long f[1000010], invf[1000010]; long long C(long long a, long long b) { if (b > a || b < 0 || a < 0) return 0; return (((f[a] * invf[b]) % M) * invf[a - b]) % M; } int main() { ios::sync_with_stdio(false); cin >> s; n = s.length(); f[0] = invf[0] = 1; for (int i = 1; i <= n; ++i) { f[i] = (f[i - 1] * i) % M; invf[i] = modinv(f[i]); } int lb = 0, rb = 0, lq = 0, rq = 0; for (int i = 0; i < n; ++i) { if (s[i] == ) ) ++rb; else if (s[i] == ? ) ++rq; } long long ans = 0; for (int i = 0; i < n; ++i) { if (s[i] == ) ) --rb; if (s[i] == ( ) ++lb; if (s[i] == ? ) --rq, ++lq; ans += (1ll * lb * C(lq + rq, rq - lb + rb) + 1ll * lq * C(lq + rq - 1, rq - lb + rb - 1)) % M; ans %= M; } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; vector<int64_t> v[3001]; int64_t calc(int64_t taken, int64_t n, int64_t m) { int64_t req = taken - v[0].size(); int64_t t = v[0].size(); int64_t ans = 0; vector<int64_t> rem; for (int64_t i = 1; i < m; i++) { if (v[i].size() == 0) continue; for (int64_t j = 0; j < v[i].size(); j++) { if (j + taken <= v[i].size()) { ans += v[i][j]; req--; } else rem.push_back(v[i][j]); } } if (req > 0) { sort(rem.begin(), rem.end()); int64_t i = 0; while (req > 0 and i < rem.size()) { ans += rem[i]; i++; req--; } } return ans; } void solve() { int64_t n, m, i, ans; cin >> n >> m; for (int64_t i = 0; i < n; i++) { int64_t p, c; cin >> p >> c; p--; v[p].push_back(c); } for (int64_t i = 0; i < m; i++) { sort(v[i].begin(), v[i].end()); } ans = LLONG_MAX; for (int64_t i = 1; i <= n; i++) { int64_t curr_cost = calc(i, n, m); ans = min(ans, curr_cost); } cout << ans << n ; } signed main() { std::ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); solve(); cerr << Execution : << (1.0 * clock()) / CLOCKS_PER_SEC << s n ; return 0; } |
`timescale 1s/1s
module test(outp, outm, outl, in);
output outp, outm, outl;
input in;
// Check a primitive.
assign #1 outp = ~in;
// Check a multiplexer.
assign #1 outm = in ? in : 1'b0;
// Check a LPM.
assign #1 outl = in === 1'b1;
endmodule
// This is not exactly the same as the original code, but it is effectively
// the same and should test the same things that were failing.
`timescale 1ns/100ps
module top;
reg in, passed;
wire outp, outm, outl;
test dut(outp, outm, outl, in);
initial begin
passed = 1'b1;
#;
if (outp !== 1'bx) begin
$display("Failed initial prim. check, expected 1'bx, got %b.", outp);
passed = 1'b0;
end
if (outm !== 1'bx) begin
$display("Failed initial mux. check, expected 1'bx, got %b.", outm);
passed = 1'b0;
end
if (outl !== 1'b0) begin
$display("Failed initial LPM check, expected 1'b0, got %b.", outl);
passed = 1'b0;
end
in = 0;
#;
if (outp !== 1'b1) begin
$display("Failed in=0 prim. check, expected 1'b1, got %b.", outp);
passed = 1'b0;
end
if (outm !== 1'b0) begin
$display("Failed in=0 mux. check, expected 1'b0, got %b.", outm);
passed = 1'b0;
end
if (outl !== 1'b0) begin
$display("Failed in=0 LPM check, expected 1'b0, got %b.", outl);
passed = 1'b0;
end
in = 1;
#;
if (outp !== 1'b0) begin
$display("Failed in=1 prim. check, expected 1'b0, got %b.", outp);
passed = 1'b0;
end
if (outm !== 1'b1) begin
$display("Failed in=1 mux. check, expected 1'b1, got %b.", outm);
passed = 1'b0;
end
if (outl !== 1'b1) begin
$display("Failed in=1 LPM check, expected 1'b1, got %b.", outl);
passed = 1'b0;
end
if (passed) $display("PASSED");
end
endmodule
|
`timescale 1ns / 1ps
/////////////////////////////////////////////////////////////////
// Module Name: lab1_tb
/////////////////////////////////////////////////////////////////
module lab1_tb(
);
reg [7:0] switches;
wire [7:0] leds;
reg [7:0] e_led;
integer i;
lab1 dut(.led(leds),.swt(switches));
function [7:0] expected_led;
input [7:0] swt;
begin
expected_led[0] = ~swt[0];
expected_led[1] = swt[1] & ~swt[2];
expected_led[3] = swt[2] & swt[3];
expected_led[2] = expected_led[1] | expected_led[3];
expected_led[7:4] = swt[7:4];
end
endfunction
initial
begin
for (i=0; i < 255; i=i+2)
begin
#50 switches=i;
#10 e_led = expected_led(switches);
if(leds == e_led)
$display("LED output matched at", $time);
else
$display("LED output mis-matched at ",$time,": expected: %b, actual: %b", e_led, leds);
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[514]; long long int dp[514][514]; long long int mod = 1000000007ll; long long int mdp(int s, int e) { if (s == e) return 1; if (dp[s][e] != -1) return dp[s][e]; long long int& ans = dp[s][e]; if (s + 1 == e) return ans = 1; ans = mdp(s + 1, e); for (int i = s + 1; i < e; i++) { if (a[s] < a[i]) { ans += mdp(s + 1, i) * mdp(i, e) % mod; } } return ans = ans % mod; } int sol() { memset(dp, -1, sizeof(dp)); int n; if (scanf( %d , &n) == EOF) return 0; for (int i = 0; i < n; i++) { scanf( %d , a + i); } printf( %I64d n , n == 1 ? 1 : mdp(1, n)); return 1; } int main() { while (sol()) ; return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> bool umin(T& a, T b) { if (a > b) { a = b; return 1; } return 0; } template <class T> bool umax(T& a, T b) { if (a < b) { a = b; return 1; } return 0; } long long a, b, c, type, ric[300007], par[300007], cost[300007], d[300007], n, m, lvl[300007], P[300007][20 * 2]; vector<pair<long long, long long> > E[300007]; pair<pair<long long, long long>, long long> way[300007]; long long atabul(long long x) { if (ric[x] == x) return x; return ric[x] = atabul(ric[x]); } void dfs(long long x, long long y, long long z) { lvl[x] = lvl[y] + 1; P[x][0] = y; cost[x] = z; if (z == 1) { ric[x] = y; atabul(x); } for (int i = 0; i < int(E[x].size()); i++) if (E[x][i].first != y) dfs(E[x][i].first, x, E[x][i].second); } void build_table() { for (int j = 1; j <= 20; j++) for (int i = 1; i <= n; i++) if (P[i][j - 1] > 0) P[i][j] = P[P[i][j - 1]][j - 1]; } void form_LCA() { for (int i = 0; i <= n; i++) for (int j = 0; j <= 20; j++) P[i][j] = -1; dfs(1, 0, 0); build_table(); } long long LCA(long long x, long long y) { if (lvl[x] < lvl[y]) swap(x, y); for (int i = 20; i >= 0; i--) if (lvl[x] - (1 << i) >= lvl[y]) x = P[x][i]; if (x == y) return x; for (int i = 20; i >= 0; i--) if (P[x][i] > 0 && P[x][i] != P[y][i]) x = P[x][i], y = P[y][i]; return P[x][0]; } int main() { scanf( %lld%lld , &n, &m); ric[n] = n; for (int i = 1; i < n; i++) { scanf( %lld%lld%lld , &a, &b, &c); E[a].push_back(make_pair(b, c)); E[b].push_back(make_pair(a, c)); ric[i] = i; way[i] = {{a, b}, c}; } form_LCA(); while (m--) { scanf( %lld , &type); if (type == 1) { scanf( %lld%lld%lld , &a, &b, &c); long long tr = LCA(a, b); while (atabul(a) != atabul(tr) && c > 0) { if (cost[a] == 1) { a = atabul(a); continue; } c /= cost[a]; a = P[a][0]; } while (atabul(b) != atabul(tr) && c > 0) { if (cost[b] == 1) { b = atabul(b); continue; } c /= cost[b]; b = P[b][0]; } printf( %lld n , c); } else { scanf( %lld%lld , &a, &b); long long qm = way[a].first.first, gr = way[a].first.second; if (lvl[qm] < lvl[gr]) swap(qm, gr); cost[qm] = b; if (b == 1) { ric[qm] = gr; atabul(qm); } } } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long N = 20; long long n, m, dp[N][1 << N], B, res, cb[1 << N]; bool used[N][1 << N], w[N][N]; long long cbit(long long x) { long long c = 0; while (x) { c += x & 1; x /= 2; } return c; } signed main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> n >> m; for (long long i = 0; i < m; ++i) { long long a, b; cin >> a >> b; a--; b--; w[a][b] = 1; w[b][a] = 1; } B = 1 << n; for (long long i = 0; i < B; ++i) cb[i] = cbit(i); queue<pair<long long, long long>> q; for (long long i = 0; i < n; ++i) { for (long long j = 0; j < n; ++j) { for (long long ma = 0; ma < B; ++ma) { dp[j][ma] = 0; used[j][ma] = 0; } } q.push({i, 1 << i}); dp[i][1 << i] = 1; while (!q.empty()) { long long v = q.front().first, mask = q.front().second, nmask; q.pop(); for (long long u = i; u < n; ++u) { nmask = mask | (1 << u); if (nmask == mask || !w[u][v]) continue; dp[u][nmask] += dp[v][mask]; if (!used[u][nmask]) { used[u][nmask] = 1; q.push({u, nmask}); } } } long long av = 0; for (long long j = 0; j < n; ++j) { for (long long mask = 0; mask < B; ++mask) { if (cb[mask] >= 3 && w[i][j] && dp[j][mask]) { av += dp[j][mask]; } } } res += av / 2; } cout << res << n ; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAPMET1_BLACKBOX_V
`define SKY130_FD_SC_MS__TAPMET1_BLACKBOX_V
/**
* tapmet1: Tap cell with isolated power and ground connections.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__tapmet1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAPMET1_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O221AI_4_V
`define SKY130_FD_SC_HD__O221AI_4_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog wrapper for o221ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o221ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o221ai_4 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o221ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o221ai_4 (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o221ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O221AI_4_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, normg, bekg, uykg, beksur, uyksur; int i, j, x, y, t = 0, A[1000][2], fark; cin >> n >> normg >> bekg >> uykg >> beksur >> uyksur; for (i = 1; i <= n; i++) cin >> A[i][0] >> A[i][1]; for (i = 1; i <= n; i++) { t += abs(A[i][1] - A[i][0]) * normg; if (i != n) { fark = abs(A[i + 1][0] - A[i][1]); if (fark >= beksur) { t += beksur * normg; fark -= beksur; } else t += fark * normg, fark = 0; if (fark >= uyksur) { t += uyksur * bekg; fark -= uyksur; } else t += fark * bekg, fark = 0; if (fark > 0) t += fark * uykg; } } cout << t; return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Fri Jan 13 17:31:20 2017
// Host : KLight-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/shadow_pixel_1/shadow_pixel_stub.v
// Design : shadow_pixel
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
module shadow_pixel(clka, wea, addra, dina, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,wea[0:0],addra[10:0],dina[11:0],douta[11:0]" */;
input clka;
input [0:0]wea;
input [10:0]addra;
input [11:0]dina;
output [11:0]douta;
endmodule
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.4 (lin64) Build Wed Nov 18 09:44:32 MST 2015
// Date : Sun Aug 28 01:02:31 2016
// Host : fpgaserv running 64-bit Ubuntu 14.04.4 LTS
// Command : write_verilog -force -mode synth_stub
// /home/kobayashi/PCIe_test/branches/IEICE/data_compression/4-way_2-tree/src/ip_pcie/PCIeGen2x8If128_stub.v
// Design : PCIeGen2x8If128
// Purpose : Stub declaration of top-level module interface
// Device : xc7vx485tffg1761-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "PCIeGen2x8If128_pcie2_top,Vivado 2015.4" *)
module PCIeGen2x8If128(pci_exp_txp, pci_exp_txn, pci_exp_rxp, pci_exp_rxn, user_clk_out, user_reset_out, user_lnk_up, user_app_rdy, tx_buf_av, tx_cfg_req, tx_err_drop, s_axis_tx_tready, s_axis_tx_tdata, s_axis_tx_tkeep, s_axis_tx_tlast, s_axis_tx_tvalid, s_axis_tx_tuser, tx_cfg_gnt, m_axis_rx_tdata, m_axis_rx_tkeep, m_axis_rx_tlast, m_axis_rx_tvalid, m_axis_rx_tready, m_axis_rx_tuser, rx_np_ok, rx_np_req, fc_cpld, fc_cplh, fc_npd, fc_nph, fc_pd, fc_ph, fc_sel, cfg_status, cfg_command, cfg_dstatus, cfg_dcommand, cfg_lstatus, cfg_lcommand, cfg_dcommand2, cfg_pcie_link_state, cfg_pmcsr_pme_en, cfg_pmcsr_powerstate, cfg_pmcsr_pme_status, cfg_received_func_lvl_rst, cfg_trn_pending, cfg_pm_halt_aspm_l0s, cfg_pm_halt_aspm_l1, cfg_pm_force_state_en, cfg_pm_force_state, cfg_dsn, cfg_interrupt, cfg_interrupt_rdy, cfg_interrupt_assert, cfg_interrupt_di, cfg_interrupt_do, cfg_interrupt_mmenable, cfg_interrupt_msienable, cfg_interrupt_msixenable, cfg_interrupt_msixfm, cfg_interrupt_stat, cfg_pciecap_interrupt_msgnum, cfg_to_turnoff, cfg_turnoff_ok, cfg_bus_number, cfg_device_number, cfg_function_number, cfg_pm_wake, cfg_pm_send_pme_to, cfg_ds_bus_number, cfg_ds_device_number, cfg_ds_function_number, cfg_bridge_serr_en, cfg_slot_control_electromech_il_ctl_pulse, cfg_root_control_syserr_corr_err_en, cfg_root_control_syserr_non_fatal_err_en, cfg_root_control_syserr_fatal_err_en, cfg_root_control_pme_int_en, cfg_aer_rooterr_corr_err_reporting_en, cfg_aer_rooterr_non_fatal_err_reporting_en, cfg_aer_rooterr_fatal_err_reporting_en, cfg_aer_rooterr_corr_err_received, cfg_aer_rooterr_non_fatal_err_received, cfg_aer_rooterr_fatal_err_received, cfg_vc_tcvc_map, sys_clk, sys_rst_n)
/* synthesis syn_black_box black_box_pad_pin="pci_exp_txp[7:0],pci_exp_txn[7:0],pci_exp_rxp[7:0],pci_exp_rxn[7:0],user_clk_out,user_reset_out,user_lnk_up,user_app_rdy,tx_buf_av[5:0],tx_cfg_req,tx_err_drop,s_axis_tx_tready,s_axis_tx_tdata[127:0],s_axis_tx_tkeep[15:0],s_axis_tx_tlast,s_axis_tx_tvalid,s_axis_tx_tuser[3:0],tx_cfg_gnt,m_axis_rx_tdata[127:0],m_axis_rx_tkeep[15:0],m_axis_rx_tlast,m_axis_rx_tvalid,m_axis_rx_tready,m_axis_rx_tuser[21:0],rx_np_ok,rx_np_req,fc_cpld[11:0],fc_cplh[7:0],fc_npd[11:0],fc_nph[7:0],fc_pd[11:0],fc_ph[7:0],fc_sel[2:0],cfg_status[15:0],cfg_command[15:0],cfg_dstatus[15:0],cfg_dcommand[15:0],cfg_lstatus[15:0],cfg_lcommand[15:0],cfg_dcommand2[15:0],cfg_pcie_link_state[2:0],cfg_pmcsr_pme_en,cfg_pmcsr_powerstate[1:0],cfg_pmcsr_pme_status,cfg_received_func_lvl_rst,cfg_trn_pending,cfg_pm_halt_aspm_l0s,cfg_pm_halt_aspm_l1,cfg_pm_force_state_en,cfg_pm_force_state[1:0],cfg_dsn[63:0],cfg_interrupt,cfg_interrupt_rdy,cfg_interrupt_assert,cfg_interrupt_di[7:0],cfg_interrupt_do[7:0],cfg_interrupt_mmenable[2:0],cfg_interrupt_msienable,cfg_interrupt_msixenable,cfg_interrupt_msixfm,cfg_interrupt_stat,cfg_pciecap_interrupt_msgnum[4:0],cfg_to_turnoff,cfg_turnoff_ok,cfg_bus_number[7:0],cfg_device_number[4:0],cfg_function_number[2:0],cfg_pm_wake,cfg_pm_send_pme_to,cfg_ds_bus_number[7:0],cfg_ds_device_number[4:0],cfg_ds_function_number[2:0],cfg_bridge_serr_en,cfg_slot_control_electromech_il_ctl_pulse,cfg_root_control_syserr_corr_err_en,cfg_root_control_syserr_non_fatal_err_en,cfg_root_control_syserr_fatal_err_en,cfg_root_control_pme_int_en,cfg_aer_rooterr_corr_err_reporting_en,cfg_aer_rooterr_non_fatal_err_reporting_en,cfg_aer_rooterr_fatal_err_reporting_en,cfg_aer_rooterr_corr_err_received,cfg_aer_rooterr_non_fatal_err_received,cfg_aer_rooterr_fatal_err_received,cfg_vc_tcvc_map[6:0],sys_clk,sys_rst_n" */;
output [7:0]pci_exp_txp;
output [7:0]pci_exp_txn;
input [7:0]pci_exp_rxp;
input [7:0]pci_exp_rxn;
output user_clk_out;
output user_reset_out;
output user_lnk_up;
output user_app_rdy;
output [5:0]tx_buf_av;
output tx_cfg_req;
output tx_err_drop;
output s_axis_tx_tready;
input [127:0]s_axis_tx_tdata;
input [15:0]s_axis_tx_tkeep;
input s_axis_tx_tlast;
input s_axis_tx_tvalid;
input [3:0]s_axis_tx_tuser;
input tx_cfg_gnt;
output [127:0]m_axis_rx_tdata;
output [15:0]m_axis_rx_tkeep;
output m_axis_rx_tlast;
output m_axis_rx_tvalid;
input m_axis_rx_tready;
output [21:0]m_axis_rx_tuser;
input rx_np_ok;
input rx_np_req;
output [11:0]fc_cpld;
output [7:0]fc_cplh;
output [11:0]fc_npd;
output [7:0]fc_nph;
output [11:0]fc_pd;
output [7:0]fc_ph;
input [2:0]fc_sel;
output [15:0]cfg_status;
output [15:0]cfg_command;
output [15:0]cfg_dstatus;
output [15:0]cfg_dcommand;
output [15:0]cfg_lstatus;
output [15:0]cfg_lcommand;
output [15:0]cfg_dcommand2;
output [2:0]cfg_pcie_link_state;
output cfg_pmcsr_pme_en;
output [1:0]cfg_pmcsr_powerstate;
output cfg_pmcsr_pme_status;
output cfg_received_func_lvl_rst;
input cfg_trn_pending;
input cfg_pm_halt_aspm_l0s;
input cfg_pm_halt_aspm_l1;
input cfg_pm_force_state_en;
input [1:0]cfg_pm_force_state;
input [63:0]cfg_dsn;
input cfg_interrupt;
output cfg_interrupt_rdy;
input cfg_interrupt_assert;
input [7:0]cfg_interrupt_di;
output [7:0]cfg_interrupt_do;
output [2:0]cfg_interrupt_mmenable;
output cfg_interrupt_msienable;
output cfg_interrupt_msixenable;
output cfg_interrupt_msixfm;
input cfg_interrupt_stat;
input [4:0]cfg_pciecap_interrupt_msgnum;
output cfg_to_turnoff;
input cfg_turnoff_ok;
output [7:0]cfg_bus_number;
output [4:0]cfg_device_number;
output [2:0]cfg_function_number;
input cfg_pm_wake;
input cfg_pm_send_pme_to;
input [7:0]cfg_ds_bus_number;
input [4:0]cfg_ds_device_number;
input [2:0]cfg_ds_function_number;
output cfg_bridge_serr_en;
output cfg_slot_control_electromech_il_ctl_pulse;
output cfg_root_control_syserr_corr_err_en;
output cfg_root_control_syserr_non_fatal_err_en;
output cfg_root_control_syserr_fatal_err_en;
output cfg_root_control_pme_int_en;
output cfg_aer_rooterr_corr_err_reporting_en;
output cfg_aer_rooterr_non_fatal_err_reporting_en;
output cfg_aer_rooterr_fatal_err_reporting_en;
output cfg_aer_rooterr_corr_err_received;
output cfg_aer_rooterr_non_fatal_err_received;
output cfg_aer_rooterr_fatal_err_received;
output [6:0]cfg_vc_tcvc_map;
input sys_clk;
input sys_rst_n;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR3B_TB_V
`define SKY130_FD_SC_LS__OR3B_TB_V
/**
* or3b: 3-input OR, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__or3b.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C_N = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C_N = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C_N = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C_N = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C_N = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_ls__or3b dut (.A(A), .B(B), .C_N(C_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR3B_TB_V
|
module opc5lscpu( input[15:0] din, input clk, input reset_b, input int_b, input clken, output vpa, output vda, output[15:0] dout, output[15:0] address, output rnw);
parameter MOV=4'h0,AND=4'h1,OR=4'h2,XOR=4'h3,ADD=4'h4,ADC=4'h5,STO=4'h6,LD=4'h7,ROR=4'h8,NOT=4'h9,SUB=4'hA,SBC=4'hB,CMP=4'hC,CMPC=4'hD,BSWP=4'hE,PSR=4'hF;
parameter FETCH0=3'h0,FETCH1=3'h1,EA_ED=3'h2,RDMEM=3'h3,EXEC=3'h4,WRMEM=3'h5,INT=3'h6 ;
parameter EI=3,S=2,C=1,Z=0,P0=15,P1=14,P2=13,IRLEN=12,IRLD=16,IRSTO=17,IRGETPSR=18,IRPUTPSR=19,IRRTI=20,IRCMP=21,INT_VECTOR=16'h0002;
reg [15:0] OR_q,PC_q,PCI_q,result;
reg [21:0] IR_q; (* RAM_STYLE="DISTRIBUTED" *)
reg [15:0] sprf_q[15:0];
reg [2:0] FSM_q;
reg [3:0] sprf_radr_q,swiid,PSRI_q;
reg [7:0] PSR_q ;
reg zero,carry,sign,enable_int,reset_s0_b,reset_s1_b;
wire predicate = IR_q[P2] ^ (IR_q[P1]?(IR_q[P0]?PSR_q[S]:PSR_q[Z]):(IR_q[P0]?PSR_q[C]:1));
wire predicate_din = din[P2] ^ (din[P1]?(din[P0]?PSR_q[S]:PSR_q[Z]):(din[P0]?PSR_q[C]:1));
wire [15:0] sprf_dout = (sprf_radr_q==4'hF)?PC_q:(sprf_q[sprf_radr_q] & {16{(sprf_radr_q!=4'h0)}});
assign {rnw,dout,address} = {!(FSM_q==WRMEM),sprf_dout,(FSM_q==WRMEM || FSM_q == RDMEM)?OR_q:PC_q };
assign {vpa,vda} = {((FSM_q==FETCH0)||(FSM_q==FETCH1)||(FSM_q==EXEC)),((FSM_q==RDMEM)||(FSM_q==WRMEM)) };
always @(*)
begin
if (FSM_q==EA_ED)
{carry,result} = sprf_dout + OR_q; // carry is dont care in this state
else
case (IR_q[11:8]) // no real need for STO entry but include it so all instructions are covered,no need for default
LD,MOV,PSR,STO :{carry,result} = {PSR_q[C],(IR_q[IRGETPSR])?{8'b0,PSR_q}:OR_q} ;
AND,OR :{carry,result} = {PSR_q[C],(IR_q[8])?(sprf_dout & OR_q):(sprf_dout | OR_q)};
ADD,ADC :{carry,result} = sprf_dout + OR_q + (IR_q[8] & PSR_q[C]);
SUB,SBC,CMP,CMPC :{carry,result} = sprf_dout + (OR_q ^ 16'hFFFF) + ((IR_q[8])?PSR_q[C]:1);
XOR,BSWP :{carry,result} = {PSR_q[C],(!IR_q[11])?(sprf_dout ^ OR_q):{OR_q[7:0],OR_q[15:8] }};
NOT,ROR :{result,carry} = (IR_q[8])?{~OR_q,PSR_q[C]}:{PSR_q[C],OR_q} ;
endcase // case (IR_q)
{swiid,enable_int,sign,carry,zero} = (IR_q[IRPUTPSR])?OR_q[7:0]:(IR_q[3:0]!=4'hF)?{PSR_q[7:3],result[15],carry,!(|result)}:PSR_q;
end
always @(posedge clk)
if (clken) begin
{reset_s0_b,reset_s1_b} <= {reset_b,reset_s0_b};
if (!reset_s1_b)
{PC_q,PCI_q,PSRI_q,PSR_q,FSM_q} <= 0;
else begin
case (FSM_q)
FETCH0 :FSM_q <= (din[IRLEN])?FETCH1:(!predicate_din)?FETCH0:EA_ED;
FETCH1 :FSM_q <= (!predicate)?FETCH0:((sprf_radr_q!=0) || IR_q[IRLD] || IR_q[IRSTO])?EA_ED:EXEC;
EA_ED :FSM_q <= (!predicate)?FETCH0:(IR_q[IRLD])?RDMEM:(IR_q[IRSTO])?WRMEM:EXEC;
RDMEM :FSM_q <= EXEC;
EXEC :FSM_q <= ((!int_b & PSR_q[EI])||(IR_q[IRPUTPSR] && (|swiid)))?INT:(IR_q[3:0]==4'hF)?FETCH0:(din[IRLEN])?FETCH1:EA_ED;
WRMEM :FSM_q <= (!int_b & PSR_q[EI])?INT:FETCH0;
default:FSM_q <= FETCH0;
endcase // case (FSM_q)
case(FSM_q)
FETCH0,EXEC:{sprf_radr_q,OR_q } <= {din[7:4],16'b0};
FETCH1 :{sprf_radr_q,OR_q } <= {(((sprf_radr_q!=0) || IR_q[IRLD] || IR_q[IRSTO])?IR_q[7:4]:IR_q[3:0]),din};
EA_ED :{sprf_radr_q,OR_q } <= {IR_q[3:0],result}; // use ALU to compute effective address/data
default :{sprf_radr_q,OR_q } <= {IR_q[3:0],din};
endcase // case (FSM_q)
if (FSM_q == INT)
{PC_q,PCI_q,PSRI_q,PSR_q[EI]} <= {INT_VECTOR,PC_q,PSR_q[3:0],1'b0} ; // Always clear EI on taking interrupt
else if (FSM_q == FETCH0 || FSM_q == FETCH1)
PC_q <= PC_q + 1;
else if (FSM_q == EXEC) begin
PC_q <= (IR_q[IRRTI])?PCI_q:(IR_q[3:0]==4'hF)?result:((!int_b && PSR_q[EI]) || (IR_q[IRPUTPSR] && (|swiid)))?PC_q:PC_q + 1;
PSR_q <= (IR_q[IRRTI])?{4'b0,PSRI_q}:{swiid,enable_int,sign,carry,zero}; // Clear SWI bits on return
sprf_q[(IR_q[IRCMP])?4'b0:IR_q[3:0]] <= result ;
end
if (FSM_q == FETCH0 || FSM_q == EXEC)
IR_q <= {((din[11:8]==CMP)||(din[11:8]==CMPC)),{3{(din[11:8]==PSR)}}&{(din[3:0]==4'hF),(din[3:0]==4'h0),(din[7:4]==4'b0)},(din[11:8]==STO),(din[11:8]==LD),din};
end
end
endmodule
|
/*
* Copyright 2010, Aleksander Osman, . All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are
* permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
module serial_txd(
input CLK_I,
input RST_I,
//slave
input [7:0] DAT_I,
output reg ACK_O,
input CYC_I,
input STB_I,
input WE_I,
//serial output
input uart_rxd,
input uart_rts,
output reg uart_txd,
output uart_cts
);
assign uart_cts = uart_rts;
reg [12:0] counter;
always @(posedge CLK_I) begin
if(RST_I == 1'b1) begin
ACK_O <= 1'b0;
uart_txd <= 1'b1;
counter <= 13'd0;
end
else if(CYC_I == 1'b1 && STB_I == 1'b1 && WE_I == 1'b1 && ACK_O == 1'b0) begin
if(counter < 13'd8191) counter <= counter + 13'd1;
if(counter < 434*1) uart_txd <= 1'b0;
else if(counter < 434*2) uart_txd <= DAT_I[0];
else if(counter < 434*3) uart_txd <= DAT_I[1];
else if(counter < 434*4) uart_txd <= DAT_I[2];
else if(counter < 434*5) uart_txd <= DAT_I[3];
else if(counter < 434*6) uart_txd <= DAT_I[4];
else if(counter < 434*7) uart_txd <= DAT_I[5];
else if(counter < 434*8) uart_txd <= DAT_I[6];
else if(counter < 434*9) uart_txd <= DAT_I[7];
else if(counter < 434*10) uart_txd <= 1'b1;
else begin
uart_txd <= 1'b1;
ACK_O <= 1'b1;
end
end
else begin
ACK_O <= 1'b0;
uart_txd <= 1'b1;
counter <= 13'd0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5 + 10, Mod = 1e9 + 7; long long fact[2 * MAXN], dp[MAXN], ps[MAXN], inv[MAXN * 2]; pair<long long, long long> a[MAXN]; long long power(long long x, long long y) { if (!y) return 1; long long ans = power(x, y / 2); ans *= ans; ans %= Mod; if (y % 2) ans *= x; ans %= Mod; return ans; } long long c(int n, int r) { long long ans = fact[n]; ans *= inv[r]; ans %= Mod; ans *= inv[n - r]; ans %= Mod; return ans; } int main() { fact[0] = 1; inv[0] = 1; for (int i = 1; i < 2 * MAXN; i++) { fact[i] = (fact[i - 1] * i) % Mod; inv[i] = power(fact[i], Mod - 2); } int w, h, n; cin >> w >> h >> n; for (int i = 1; i <= n; i++) cin >> a[i].first >> a[i].second; n++; a[n].first = w; a[n].second = h; sort(a + 1, a + 1 + n); for (int i = 1; i <= n; i++) { dp[i] = c(a[i].first + a[i].second - 2, a[i].first - 1); dp[i] %= Mod; for (int j = 1; j < i; j++) if (a[j].first <= a[i].first and a[j].second <= a[i].second) { dp[i] -= dp[j] * c(a[i].first - a[j].first + a[i].second - a[j].second, a[i].first - a[j].first); dp[i] %= Mod; dp[i] += Mod; dp[i] %= Mod; } } cout << dp[n] << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FAHCON_SYMBOL_V
`define SKY130_FD_SC_LP__FAHCON_SYMBOL_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__fahcon (
//# {{data|Data Signals}}
input A ,
input B ,
input CI ,
output COUT_N,
output SUM
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__FAHCON_SYMBOL_V
|
// Benchmark "adder32" written by ABC on Wed Jan 7 18:50:17 2015
module adder32 (
a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15,
b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b10, b11, b12, b13, b14, b15,
s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15,
cout );
input a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15,
b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b10, b11, b12, b13, b14, b15;
output s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, cout;
wire n50, n51, n53, n54, n55, n56, n57, n58, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, n93, n94, n95, n96, n97, n98, n99, n100, n101, n102, n104, n105, n106, n107, n108, n109, n110, n111, n112, n113, n115, n116, n117, n118, n119, n120, n121, n122, n123, n124, n126, n127, n128, n129, n130, n131, n132, n133, n134, n135, n137, n138, n139, n140, n141, n142, n143, n144, n145, n146, n148, n149, n150, n151, n152, n153, n154, n155, n156, n157, n159, n160, n161, n162, n163, n164, n165, n166, n167, n168, n170, n171, n172, n173, n174, n175, n176, n177, n178, n179, n181, n182, n183, n184, n185, n186, n187, n188, n189, n190, n192, n193, n194, n195, n196, n197, n198, n199, n200, n201, n203, n204, n205, n206, n207, n208, n209, n210, n211, n212, n214, n215, n216, n217;
assign n50 = ~a0 & b0;
assign n51 = a0 & ~b0;
assign s0 = n50 | n51;
assign n53 = a0 & b0;
assign n54 = ~a1 & b1;
assign n55 = a1 & ~b1;
assign n56 = ~n54 & ~n55;
assign n57 = n53 & n56;
assign n58 = ~n53 & ~n56;
assign s1 = n57 | n58;
assign n60 = a1 & b1;
assign n61 = a1 & n53;
assign n62 = ~n60 & ~n61;
assign n63 = b1 & n53;
assign n64 = n62 & ~n63;
assign n65 = ~a2 & b2;
assign n66 = a2 & ~b2;
assign n67 = ~n65 & ~n66;
assign n68 = ~n64 & n67;
assign n69 = n64 & ~n67;
assign s2 = n68 | n69;
assign n71 = a2 & b2;
assign n72 = a2 & ~n64;
assign n73 = ~n71 & ~n72;
assign n74 = b2 & ~n64;
assign n75 = n73 & ~n74;
assign n76 = ~a3 & b3;
assign n77 = a3 & ~b3;
assign n78 = ~n76 & ~n77;
assign n79 = ~n75 & n78;
assign n80 = n75 & ~n78;
assign s3 = n79 | n80;
assign n82 = a3 & b3;
assign n83 = a3 & ~n75;
assign n84 = ~n82 & ~n83;
assign n85 = b3 & ~n75;
assign n86 = n84 & ~n85;
assign n87 = ~a4 & b4;
assign n88 = a4 & ~b4;
assign n89 = ~n87 & ~n88;
assign n90 = ~n86 & n89;
assign n91 = n86 & ~n89;
assign s4 = n90 | n91;
assign n93 = a4 & b4;
assign n94 = a4 & ~n86;
assign n95 = ~n93 & ~n94;
assign n96 = b4 & ~n86;
assign n97 = n95 & ~n96;
assign n98 = ~a5 & b5;
assign n99 = a5 & ~b5;
assign n100 = ~n98 & ~n99;
assign n101 = ~n97 & n100;
assign n102 = n97 & ~n100;
assign s5 = n101 | n102;
assign n104 = a5 & b5;
assign n105 = a5 & ~n97;
assign n106 = ~n104 & ~n105;
assign n107 = b5 & ~n97;
assign n108 = n106 & ~n107;
assign n109 = ~a6 & b6;
assign n110 = a6 & ~b6;
assign n111 = ~n109 & ~n110;
assign n112 = ~n108 & n111;
assign n113 = n108 & ~n111;
assign s6 = n112 | n113;
assign n115 = a6 & b6;
assign n116 = a6 & ~n108;
assign n117 = ~n115 & ~n116;
assign n118 = b6 & ~n108;
assign n119 = n117 & ~n118;
assign n120 = ~a7 & b7;
assign n121 = a7 & ~b7;
assign n122 = ~n120 & ~n121;
assign n123 = ~n119 & n122;
assign n124 = n119 & ~n122;
assign s7 = n123 | n124;
assign n126 = a7 & b7;
assign n127 = a7 & ~n119;
assign n128 = ~n126 & ~n127;
assign n129 = b7 & ~n119;
assign n130 = n128 & ~n129;
assign n131 = ~a8 & b8;
assign n132 = a8 & ~b8;
assign n133 = ~n131 & ~n132;
assign n134 = ~n130 & n133;
assign n135 = n130 & ~n133;
assign s8 = n134 | n135;
assign n137 = a8 & b8;
assign n138 = a8 & ~n130;
assign n139 = ~n137 & ~n138;
assign n140 = b8 & ~n130;
assign n141 = n139 & ~n140;
assign n142 = ~a9 & b9;
assign n143 = a9 & ~b9;
assign n144 = ~n142 & ~n143;
assign n145 = ~n141 & n144;
assign n146 = n141 & ~n144;
assign s9 = n145 | n146;
assign n148 = a9 & b9;
assign n149 = a9 & ~n141;
assign n150 = ~n148 & ~n149;
assign n151 = b9 & ~n141;
assign n152 = n150 & ~n151;
assign n153 = ~a10 & b10;
assign n154 = a10 & ~b10;
assign n155 = ~n153 & ~n154;
assign n156 = ~n152 & n155;
assign n157 = n152 & ~n155;
assign s10 = n156 | n157;
assign n159 = a10 & b10;
assign n160 = a10 & ~n152;
assign n161 = ~n159 & ~n160;
assign n162 = b10 & ~n152;
assign n163 = n161 & ~n162;
assign n164 = ~a11 & b11;
assign n165 = a11 & ~b11;
assign n166 = ~n164 & ~n165;
assign n167 = ~n163 & n166;
assign n168 = n163 & ~n166;
assign s11 = n167 | n168;
assign n170 = a11 & b11;
assign n171 = a11 & ~n163;
assign n172 = ~n170 & ~n171;
assign n173 = b11 & ~n163;
assign n174 = n172 & ~n173;
assign n175 = ~a12 & b12;
assign n176 = a12 & ~b12;
assign n177 = ~n175 & ~n176;
assign n178 = ~n174 & n177;
assign n179 = n174 & ~n177;
assign s12 = n178 | n179;
assign n181 = a12 & b12;
assign n182 = a12 & ~n174;
assign n183 = ~n181 & ~n182;
assign n184 = b12 & ~n174;
assign n185 = n183 & ~n184;
assign n186 = ~a13 & b13;
assign n187 = a13 & ~b13;
assign n188 = ~n186 & ~n187;
assign n189 = ~n185 & n188;
assign n190 = n185 & ~n188;
assign s13 = n189 | n190;
assign n192 = a13 & b13;
assign n193 = a13 & ~n185;
assign n194 = ~n192 & ~n193;
assign n195 = b13 & ~n185;
assign n196 = n194 & ~n195;
assign n197 = ~a14 & b14;
assign n198 = a14 & ~b14;
assign n199 = ~n197 & ~n198;
assign n200 = ~n196 & n199;
assign n201 = n196 & ~n199;
assign s14 = n200 | n201;
assign n203 = a14 & b14;
assign n204 = a14 & ~n196;
assign n205 = ~n203 & ~n204;
assign n206 = b14 & ~n196;
assign n207 = n205 & ~n206;
assign n208 = ~a15 & b15;
assign n209 = a15 & ~b15;
assign n210 = ~n208 & ~n209;
assign n211 = ~n207 & n210;
assign n212 = n207 & ~n210;
assign s15 = n211 | n212;
assign n214 = a15 & b15;
assign n215 = a15 & ~n207;
assign n216 = ~n214 & ~n215;
assign n217 = b15 & ~n207;
assign cout = ~n216 | n217;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long K[5], T[5]; int main() { queue<pair<long long, long long> > Q[5][2]; string ln; int n; getline(cin, ln); istringstream(ln) >> K[1] >> K[2] >> K[3]; getline(cin, ln); istringstream(ln) >> T[1] >> T[2] >> T[3]; getline(cin, ln); istringstream(ln) >> n; getline(cin, ln); istringstream in(ln); long long t0; for (int i = 0; i < n; i++) { in >> t0; Q[1][0].push(pair<long long, long long>(t0, t0)); } long long t = 0; for (int i = 1; i <= 3; i++) { while (Q[i][0].size()) { t = Q[i][0].front().first; t = max(t, Q[i][0].front().first); t0 = Q[i][0].front().second; Q[i][0].pop(); if (Q[i][1].size() < K[i]) { Q[i][1].push(pair<long long, long long>(t + T[i], t0)); } else { t = max(Q[i][1].front().first, t); Q[i + 1][0].push(Q[i][1].front()); Q[i][1].pop(); Q[i][1].push(pair<long long, long long>(t + T[i], t0)); } } while (Q[i][1].size()) { Q[i + 1][0].push(Q[i][1].front()); Q[i][1].pop(); } } long long res = 0; while (Q[4][0].size()) { res = max(res, Q[4][0].front().first - Q[4][0].front().second); Q[4][0].pop(); } cout << res << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A2111OI_PP_SYMBOL_V
`define SKY130_FD_SC_HS__A2111OI_PP_SYMBOL_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a2111oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input C1 ,
input D1 ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A2111OI_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; long long data[n + 1]; long long mx = LLONG_MIN; for (int i = 1; i <= n; i++) { cin >> data[i]; mx = max(mx, data[i]); } vector<int> graph[n + 1]; for (int i = 0; i < n - 1; i++) { int s, t; cin >> s >> t; graph[s].push_back(t); graph[t].push_back(s); } int mxi = 0; long long mxcnt = 0; for (int i = 1; i <= n; i++) { if (data[i] == mx) { mxi = i; mxcnt++; } } long long res = mx; if (mxcnt == 1) { int level[n + 1]; fill_n(level, n + 1, -1); deque<int> queue; queue.push_back(mxi); level[mxi] = 0; while (!queue.empty()) { int cur = queue.front(); res = max(res, data[cur] + level[cur]); queue.pop_front(); for (int next : graph[cur]) { if (level[next] < 0) { level[next] = min(2, level[cur] + 1); queue.push_back(next); } } } } else { bool level1 = false; for (int i = 1; !level1 && i <= n; i++) { long long cnt = data[i] == mx ? 1 : 0; for (int next : graph[i]) { if (data[next] == mx) cnt++; } level1 |= cnt == mxcnt; } res = level1 ? mx + 1 : mx + 2; } cout << res << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, x[101] = {0}, i, a, m = 0; cin >> n; for (i = 0; i < n; i++) { cin >> a; x[a]++; } for (i = 0; i <= 100; i++) { if (x[i] > m) m = x[i]; } cout << m; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INV_LP_V
`define SKY130_FD_SC_LP__INV_LP_V
/**
* inv: Inverter.
*
* Verilog wrapper for inv with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__inv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__inv_lp (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__inv_lp (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__inv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__INV_LP_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Wed May 31 20:12:37 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/examples/dma_example/dma_example.srcs/sources_1/bd/system/ip/system_auto_pc_1/system_auto_pc_1_stub.v
// Design : system_auto_pc_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_protocol_converter_v2_1_11_axi_protocol_converter,Vivado 2016.4" *)
module system_auto_pc_1(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awregion, s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb,
s_axi_wlast, s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready,
s_axi_arid, s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock,
s_axi_arcache, s_axi_arprot, s_axi_arregion, s_axi_arqos, s_axi_arvalid, s_axi_arready,
s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awid,
m_axi_awaddr, m_axi_awlen, m_axi_awsize, m_axi_awburst, m_axi_awlock, m_axi_awcache,
m_axi_awprot, m_axi_awqos, m_axi_awvalid, m_axi_awready, m_axi_wid, m_axi_wdata, m_axi_wstrb,
m_axi_wlast, m_axi_wvalid, m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_bvalid, m_axi_bready,
m_axi_arid, m_axi_araddr, m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlock,
m_axi_arcache, m_axi_arprot, m_axi_arqos, m_axi_arvalid, m_axi_arready, m_axi_rid,
m_axi_rdata, m_axi_rresp, m_axi_rlast, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[1:0],s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awregion[3:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[63:0],s_axi_wstrb[7:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[1:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[1:0],s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arregion[3:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[1:0],s_axi_rdata[63:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awid[1:0],m_axi_awaddr[31:0],m_axi_awlen[3:0],m_axi_awsize[2:0],m_axi_awburst[1:0],m_axi_awlock[1:0],m_axi_awcache[3:0],m_axi_awprot[2:0],m_axi_awqos[3:0],m_axi_awvalid,m_axi_awready,m_axi_wid[1:0],m_axi_wdata[63:0],m_axi_wstrb[7:0],m_axi_wlast,m_axi_wvalid,m_axi_wready,m_axi_bid[1:0],m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_arid[1:0],m_axi_araddr[31:0],m_axi_arlen[3:0],m_axi_arsize[2:0],m_axi_arburst[1:0],m_axi_arlock[1:0],m_axi_arcache[3:0],m_axi_arprot[2:0],m_axi_arqos[3:0],m_axi_arvalid,m_axi_arready,m_axi_rid[1:0],m_axi_rdata[63:0],m_axi_rresp[1:0],m_axi_rlast,m_axi_rvalid,m_axi_rready" */;
input aclk;
input aresetn;
input [1:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awregion;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [63:0]s_axi_wdata;
input [7:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [1:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [1:0]s_axi_rid;
output [63:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [1:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [3:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [1:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awqos;
output m_axi_awvalid;
input m_axi_awready;
output [1:0]m_axi_wid;
output [63:0]m_axi_wdata;
output [7:0]m_axi_wstrb;
output m_axi_wlast;
output m_axi_wvalid;
input m_axi_wready;
input [1:0]m_axi_bid;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [1:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [3:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [1:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arqos;
output m_axi_arvalid;
input m_axi_arready;
input [1:0]m_axi_rid;
input [63:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, k; cin >> n >> k; vector<bool> pref(1 << n); for (int i = 0; i < k; i++) { int x; cin >> x; pref[x - 1] = true; } const int oo = -1; vector<vector<vector<int>>> dp( 4, vector<vector<int>>(n + 1, vector<int>(1 << n, oo))); for (int i = 0; i < (1 << n); i += 2) { if (pref[i] && pref[i + 1]) dp[3][1][i] = 1; else if (pref[i] || pref[i + 1]) dp[1][1][i] = dp[2][1][i] = 1; else dp[0][1][i] = 0; } for (int i = 2; i <= n; i++) for (int j = 0; j < (1 << n); j += (1 << i)) for (int p = 0; p < 4; p++) for (int q = 0; q < 4; q++) if (dp[p][i - 1][j] != -1 && dp[q][i - 1][j + (1 << (i - 1))] != -1) { int t = dp[p][i - 1][j] + dp[q][i - 1][j + (1 << (i - 1))]; int upper = ((p & 2) > 0) + ((q & 2) > 0); int lower = ((p & 1) + (q & 1)); if (upper == 2) { t += (lower > 0) + 2; dp[3][i][j] = max(dp[3][i][j], t); if (lower < 2) dp[2][i][j] = max(dp[2][i][j], t); } else if (upper == 1) { t += (lower > 0) + 1; if (lower == 0) { dp[2][i][j] = max(dp[2][i][j], t); dp[1][i][j] = max(dp[1][i][j], t + 1); dp[0][i][j] = max(dp[0][i][j], t + 1); } if (lower == 1) { dp[3][i][j] = max(dp[3][i][j], t + 1); dp[2][i][j] = max(dp[2][i][j], t + 1); dp[1][i][j] = max(dp[1][i][j], t + 1); dp[0][i][j] = max(dp[0][i][j], t + 1); } if (lower == 2) { dp[3][i][j] = max(dp[3][i][j], t + 1); dp[2][i][j] = max(dp[2][i][j], t + 1); dp[1][i][j] = max(dp[1][i][j], t + 1); } } else if (upper == 0) { t += (lower > 0); if (lower == 0) dp[0][i][j] = max(dp[0][i][j], t); if (lower == 1) { dp[1][i][j] = max(dp[1][i][j], t + 1); dp[0][i][j] = max(dp[0][i][j], t + 1); } if (lower == 2) { dp[1][i][j] = max(dp[1][i][j], t + 1); dp[0][i][j] = max(dp[0][i][j], t + 1); } } } int ans = 0; for (int p = 0; p < 4; p++) ans = max(dp[p][n][0] + (p > 0), ans); cout << ans << n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__BUFINV_SYMBOL_V
`define SKY130_FD_SC_MS__BUFINV_SYMBOL_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__bufinv (
//# {{data|Data Signals}}
input A,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__BUFINV_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int big = 1e9; int dp[83][83][83][83], d[100][100]; int s[100][100][100], s1[100][100][100]; int n, kt, m, u, v, c; int main() { cin >> n >> kt >> m; for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) d[i][j] = -1; for (int i = 1; i <= m; i++) { cin >> u >> v >> c; if (d[u][v] == -1) d[u][v] = c; else d[u][v] = min(d[u][v], c); } for (int k = 1; k <= kt; k++) for (int i = 0; i <= n + 1; i++) for (int j = 0; j < i; j++) for (int l = i + 1; l <= n + 1; l++) dp[k][i][j][l] = -1; for (int k = 1; k <= kt; k++) for (int i = 0; i <= n + 1; i++) for (int j = 0; j <= n + 1; j++) { s[k][i][j] = big; s1[k][i][j] = big; } for (int k = 1; k <= kt; k++) { for (int i = 1; i <= n; i++) for (int j = 0; j < i; j++) for (int l = i + 1; l <= n + 1; l++) { if (j != 0 || k == 1) if (d[j][i] > -1 && s[k - 1][j][l] != big) dp[k][i][j][l] = s[k - 1][j][l] + d[j][i]; if (l != n + 1 || k == 1) if (d[l][i] > -1 && s1[k - 1][l][j] != big) { if (dp[k][i][j][l] == -1) dp[k][i][j][l] = s1[k - 1][l][j] + d[l][i]; else dp[k][i][j][l] = min(dp[k][i][j][l], s1[k - 1][l][j] + d[l][i]); } } for (int i = 1; i <= n; i++) for (int j = 0; j < i; j++) for (int l = i + 1; l <= n + 1; l++) if (dp[k][i][j][l] != -1) s[k][i][l] = min(s[k][i][l], dp[k][i][j][l]); for (int i = 1; i <= n; i++) for (int j = 0; j < i; j++) for (int l = i + 1; l <= n + 1; l++) if (dp[k][i][j][l] != -1) s1[k][i][j] = min(s1[k][i][j], dp[k][i][j][l]); } int mini = 1e9; for (int i = 1; i <= n; i++) for (int j = 0; j < i; j++) for (int l = i + 1; l <= n + 1; l++) if (dp[kt][i][j][l] != -1) mini = min(mini, dp[kt][i][j][l]); if (mini == 1e9) printf( -1 n ); else printf( %d n , mini); return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; inline int read(); const int M = 200016, MOD = 1000000007; int sz; int ch[M][26], len[M], link[M], pre[M]; void extend(const char *s) { for (int i = 0, lst = 0; s[i]; ++i) { int c = s[i] - a , cur = ++sz; len[cur] = len[lst] + 1; int p = lst; while (!ch[p][c]) ch[p][c] = cur, p = link[p]; if (ch[p][c] != cur) { int q = ch[p][c]; if (len[p] + 1 == len[q]) link[cur] = q; else { int clone = ++sz; memcpy(ch[clone], ch[q], sizeof(ch[q])); link[clone] = link[q]; len[clone] = len[p] + 1; while (ch[p][c] == q) ch[p][c] = clone, p = link[p]; link[q] = link[cur] = clone; } } lst = cur; pre[cur] = i + 1; } } pair<int, int> qrys[M * 2 * 26]; int qcnt; int qans[M * 2 * 26]; vector<int> sons[M]; vector<int> qry[M]; set<int> st[M]; int tar[M]; void merge(int a, int b) { if (st[tar[a]].size() < st[tar[b]].size()) swap(a, b); for (auto x : st[tar[b]]) st[tar[a]].insert(x); st[tar[b]].clear(); tar[b] = tar[a]; } void solve(int u) { for (auto v : sons[u]) solve(v), merge(u, v); for (auto qid : qry[u]) { int l = qrys[qid].first, r = qrys[qid].second; auto it = st[tar[u]].lower_bound(l); if (it != st[tar[u]].end() && *it <= r) qans[qid] = 1; } } char tex[M], pat[M * 2]; int lef[M], rig[M], pid[M], pln[M], pcnt; int solved[M]; void foreach_query(int ftq, int id, int now, int tag) { if (pat[id] && ch[now][pat[id] - a ]) foreach_query(ftq, id + 1, ch[now][pat[id] - a ], tag); for (int c = pat[id] ? pat[id] + 1 : a ; c <= z ; ++c) { int tmp = ch[now][c - a ]; if (tmp && rig[ftq] - lef[ftq] >= id - pid[ftq]) { ++qcnt; if (tag == 0) { qrys[qcnt] = {lef[ftq] + id - pid[ftq], rig[ftq]}; qry[tmp].push_back(qcnt); } else if (qans[qcnt] == 1 && !solved[ftq]) { solved[ftq] = 1; for (int xj = pid[ftq]; xj < id; ++xj) putchar(pat[xj]); putchar(c); printf( n ); } } } } int main(void) { scanf( %s , tex); extend(tex); for (int i = 1; i <= sz; ++i) sons[link[i]].push_back(i); for (int i = 0; i <= sz; ++i) { tar[i] = i; if (pre[i]) st[i].insert(pre[i]); } int q = read(); for (int i = 1; i <= q; ++i) { lef[i] = read(), rig[i] = read(), pid[i] = pcnt; scanf( %s , pat + pid[i]); pln[i] = strlen(pat + pid[i]); pcnt += pln[i] + 1; foreach_query(i, pid[i], 0, 0); } solve(0); qcnt = 0; for (int i = 1; i <= q; ++i) { foreach_query(i, pid[i], 0, 1); if (!solved[i]) printf( -1 n ); } return 0; } inline int read() { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } |
#include<bits/stdc++.h> using namespace std; const int Maxn=2021; const int Mod=998244353; int C[Maxn<<1|5][Maxn<<1|5]; int w[Maxn+5][Maxn+5]; int sum[Maxn+5][Maxn+5]; int ans; void init(){ C[0][0]=1; for(int i=1;i<=(Maxn<<1);i++){ C[i][0]=C[i][i]=1; for(int j=1;j<i;j++){ C[i][j]=(C[i-1][j]+C[i-1][j-1])%Mod; } } } void solve(int n,int m,int k){ for(int i=1;i<=n;i++){ for(int j=1;j<=m;j++){ int t_1=C[i-1+m-j][m-j],t_2=C[i+j-1][j-1]; w[i][j]=1ll*t_1*t_2%Mod; sum[i][j]=(sum[i][j-1]+w[i][j])%Mod; } } for(int i=1;i<n;i++){ for(int j=1;j<m;j++){ ans=(ans+1ll*w[i][j]*sum[n-i][m-j])%Mod; if(k==1){ ans=(ans-1ll*w[i][j]*w[n-i][m-j]%Mod+Mod)%Mod; } } } } int main(){ init(); int n,m; scanf( %d%d ,&n,&m); solve(n,m,1); solve(m,n,0); ans=(ans<<1)%Mod; printf( %d n ,ans); return 0; } |
#include <bits/stdc++.h> int main() { int n, i, z = 0, o = 0; char str[120]; scanf( %d , &n); getchar(); gets(str); for (i = 0; i < n; i++) { if (str[i] == 0 ) { z++; } else { o++; } } if (o > 0) { printf( 1 ); } for (i = 0; i < z; i++) { printf( 0 ); } printf( n ); return 0; } |
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// This module is a simple clock crosser for control signals. It will take
// the asynchronous control signal and synchronize it to the clk domain
// attached to the clk input. It does so by passing the control signal
// through a pair of registers and then sensing the level transition from
// either hi-to-lo or lo-to-hi. *ATTENTION* This module makes the assumption
// that the control signal will always transition every time is asserted.
// i.e.:
// ____ ___________________
// -> ___| |___ and ___| |_____
//
// on the control signal will be seen as only one assertion of the control
// signal. In short, if your control could be asserted back-to-back, then
// don't use this module. You'll be losing data.
`timescale 1 ns / 1 ns
module altera_jtag_control_signal_crosser (
clk,
reset_n,
async_control_signal,
sense_pos_edge,
sync_control_signal
);
input clk;
input reset_n;
input async_control_signal;
input sense_pos_edge;
output sync_control_signal;
parameter SYNC_DEPTH = 3; // number of synchronizer stages for clock crossing
reg sync_control_signal;
wire synchronized_raw_signal;
reg edge_detector_register;
altera_std_synchronizer #(.depth(SYNC_DEPTH)) synchronizer (
.clk(clk),
.reset_n(reset_n),
.din(async_control_signal),
.dout(synchronized_raw_signal)
);
always @ (posedge clk or negedge reset_n)
if (~reset_n)
edge_detector_register <= 1'b0;
else
edge_detector_register <= synchronized_raw_signal;
always @* begin
if (sense_pos_edge)
sync_control_signal <= ~edge_detector_register & synchronized_raw_signal;
else
sync_control_signal <= edge_detector_register & ~synchronized_raw_signal;
end
endmodule
// This module crosses the clock domain for a given source
module altera_jtag_src_crosser (
sink_clk,
sink_reset_n,
sink_valid,
sink_data,
src_clk,
src_reset_n,
src_valid,
src_data
);
parameter WIDTH = 8;
parameter SYNC_DEPTH = 3; // number of synchronizer stages for clock crossing
input sink_clk;
input sink_reset_n;
input sink_valid;
input [WIDTH-1:0] sink_data;
input src_clk;
input src_reset_n;
output src_valid;
output [WIDTH-1:0] src_data;
reg sink_valid_buffer;
reg [WIDTH-1:0] sink_data_buffer;
reg src_valid;
reg [WIDTH-1:0] src_data /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101 ; {-from \"*\"} CUT=ON " */;
wire synchronized_valid;
altera_jtag_control_signal_crosser #(
.SYNC_DEPTH(SYNC_DEPTH)
) crosser (
.clk(src_clk),
.reset_n(src_reset_n),
.async_control_signal(sink_valid_buffer),
.sense_pos_edge(1'b1),
.sync_control_signal(synchronized_valid)
);
always @ (posedge sink_clk or negedge sink_reset_n) begin
if (~sink_reset_n) begin
sink_valid_buffer <= 1'b0;
sink_data_buffer <= 'b0;
end else begin
sink_valid_buffer <= sink_valid;
if (sink_valid) begin
sink_data_buffer <= sink_data;
end
end //end if
end //always sink_clk
always @ (posedge src_clk or negedge src_reset_n) begin
if (~src_reset_n) begin
src_valid <= 1'b0;
src_data <= {WIDTH{1'b0}};
end else begin
src_valid <= synchronized_valid;
src_data <= synchronized_valid ? sink_data_buffer : src_data;
end
end
endmodule
module altera_jtag_dc_streaming #(
parameter PURPOSE = 0, // for discovery of services behind this JTAG Phy - 0
// for JTAG Phy, 1 for Packets to Master
parameter UPSTREAM_FIFO_SIZE = 0,
parameter DOWNSTREAM_FIFO_SIZE = 0,
parameter MGMT_CHANNEL_WIDTH = -1
) (
// Signals in the JTAG clock domain
input wire tck,
input wire tdi,
output wire tdo,
input wire [2:0] ir_in,
input wire virtual_state_cdr,
input wire virtual_state_sdr,
input wire virtual_state_udr,
input wire clk,
input wire reset_n,
output wire [7:0] source_data,
output wire source_valid,
input wire [7:0] sink_data,
input wire sink_valid,
output wire sink_ready,
output wire resetrequest,
output wire debug_reset,
output wire mgmt_valid,
output wire [(MGMT_CHANNEL_WIDTH>0?MGMT_CHANNEL_WIDTH:1)-1:0] mgmt_channel,
output wire mgmt_data
);
// the tck to sysclk sync depth is fixed at 8
// 8 is the worst case scenario from our metastability analysis, and since
// using TCK serially is so slow we should have plenty of clock cycles.
localparam TCK_TO_SYSCLK_SYNC_DEPTH = 8;
// The clk to tck path is fixed at 3 deep for Synchronizer depth.
// Since the tck clock is so slow, no parameter is exposed.
localparam SYSCLK_TO_TCK_SYNC_DEPTH = 3;
wire jtag_clock_reset_n; // system reset is synchronized with tck
wire [7:0] jtag_source_data;
wire jtag_source_valid;
wire [7:0] jtag_sink_data;
wire jtag_sink_valid;
wire jtag_sink_ready;
/* Reset Synchronizer module.
*
* The SLD Node does not provide a reset for the TCK clock domain.
* Due to the handshaking nature of the Avalon-ST Clock Crosser,
* internal states need to be reset to 0 in order to guarantee proper
* functionality throughout resets.
*
* This reset block will asynchronously assert reset, and synchronously
* deassert reset for the tck clock domain.
*/
altera_std_synchronizer #(
.depth(SYSCLK_TO_TCK_SYNC_DEPTH)
) synchronizer (
.clk(tck),
.reset_n(reset_n),
.din(1'b1),
.dout(jtag_clock_reset_n)
);
altera_jtag_streaming #(
.PURPOSE(PURPOSE),
.UPSTREAM_FIFO_SIZE(UPSTREAM_FIFO_SIZE),
.DOWNSTREAM_FIFO_SIZE(DOWNSTREAM_FIFO_SIZE),
.MGMT_CHANNEL_WIDTH(MGMT_CHANNEL_WIDTH)
) jtag_streaming (
.tck (tck),
.tdi (tdi),
.tdo (tdo),
.ir_in (ir_in),
.virtual_state_cdr(virtual_state_cdr),
.virtual_state_sdr(virtual_state_sdr),
.virtual_state_udr(virtual_state_udr),
.reset_n(jtag_clock_reset_n),
.source_data(jtag_source_data),
.source_valid(jtag_source_valid),
.sink_data(jtag_sink_data),
.sink_valid(jtag_sink_valid),
.sink_ready(jtag_sink_ready),
.clock_to_sample(clk),
.reset_to_sample(reset_n),
.resetrequest(resetrequest),
.debug_reset(debug_reset),
.mgmt_valid(mgmt_valid),
.mgmt_channel(mgmt_channel),
.mgmt_data(mgmt_data)
);
// synchronization in both clock domain crossings takes place in the "clk" system clock domain!
altera_avalon_st_clock_crosser #(
.SYMBOLS_PER_BEAT(1),
.BITS_PER_SYMBOL(8),
.FORWARD_SYNC_DEPTH(SYSCLK_TO_TCK_SYNC_DEPTH),
.BACKWARD_SYNC_DEPTH(TCK_TO_SYSCLK_SYNC_DEPTH)
) sink_crosser (
.in_clk(clk),
.in_reset(~reset_n),
.in_data(sink_data),
.in_ready(sink_ready),
.in_valid(sink_valid),
.out_clk(tck),
.out_reset(~jtag_clock_reset_n),
.out_data(jtag_sink_data),
.out_ready(jtag_sink_ready),
.out_valid(jtag_sink_valid)
);
altera_jtag_src_crosser #(
.SYNC_DEPTH(TCK_TO_SYSCLK_SYNC_DEPTH)
) source_crosser (
.sink_clk(tck),
.sink_reset_n(jtag_clock_reset_n),
.sink_valid(jtag_source_valid),
.sink_data(jtag_source_data),
.src_clk(clk),
.src_reset_n(reset_n),
.src_valid(source_valid),
.src_data(source_data)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c; cin >> a >> b >> c; map<int, vector<int> > vec; for (int i = 0; i < a; i++) { int g; cin >> g; vec[g % c].push_back(g); } for (int i = 0; i < c; i++) { if (vec[i].size() >= b) { cout << Yes << endl; for (int j = 0; j < b; j++) { cout << vec[i][j]; if (j != b - 1) { cout << ; } else { cout << endl; } } return 0; } } cout << No << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { int a[200], n, i, s = 0; scanf( %d , &n); for (i = 0; i < 2 * n - 1; i++) { scanf( %d , &a[i]); if (a[i] < 0) s -= a[i]; else s += a[i]; } if (n % 2 == 0) { sort(a, a + 2 * n - 1); for (i = 0; i < 2 * n - 1; i++) { if (a[i] > 0) break; } if (i % 2 == 1) { if (a[i - 1] + a[i] < -a[i - 1] - a[i] || a[i] < 0) s -= fabs(2 * a[i]); else s += 2 * a[i - 1]; } } cout << s << endl; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: xilinx
// Engineer: Yun Rock Qu
//
// Create Date: 12/19/2017 10:33:58 AM
// Design Name: color_swap
// Module Name: color_swap
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module color_swap(
hsync_in,
hsync_out,
pixel_in,
pixel_out,
vde_in,
vde_out,
vsync_in,
vsync_out
);
parameter input_format = "rgb";
parameter output_format = "rbg";
input hsync_in;
output hsync_out;
input vsync_in;
output vsync_out;
input [23:0]pixel_in;
output [23:0]pixel_out;
input vde_in;
output vde_out;
wire [23:0]pixel_rgb;
assign hsync_out = hsync_in;
assign vsync_out = vsync_in;
assign vde_out = vde_in;
if (input_format == "rgb")
assign pixel_rgb[23:0] = {pixel_in[23:16],pixel_in[15:8],pixel_in[7:0]};
else if (input_format == "rbg")
assign pixel_rgb[23:0] = {pixel_in[23:16],pixel_in[7:0],pixel_in[15:8]};
if (output_format == "rgb")
assign pixel_out[23:0] = {pixel_rgb[23:16],pixel_rgb[15:8],pixel_rgb[7:0]};
else if (output_format == "rbg")
assign pixel_out[23:0] = {pixel_rgb[23:16],pixel_rgb[7:0],pixel_rgb[15:8]};
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, k; int d[188]; int par[188]; vector<int> g[188]; int dp[188][188]; int pos[188]; int ans[188]; void build(int x, int pre) { par[x] = pre; for (int i = (0); i < (g[x].size()); ++i) { int to = g[x][i]; if (to == pre) { g[x].erase(g[x].begin() + i, g[x].begin() + i + 1); i--; continue; } build(to, x); } } void dfs(int x) { for (int i = (0); i < (g[x].size()); ++i) { int to = g[x][i]; dfs(to); } for (int y = (0); y < (n); ++y) { int z = y; while (z != x && z != -1) z = par[z]; if (z == -1) continue; z = y; int cur = 0, lst = -1, dis = 0; while (1) { cur += (dis ? d[dis] : k); dis++; for (int i = (0); i < (g[z].size()); ++i) { int to = g[z][i]; if (to == lst) continue; cur += dp[to][dis]; } if (z == x) break; lst = z; z = par[z]; } if (cur < dp[x][0]) { dp[x][0] = cur; pos[x] = y; } } for (int dis = (1); dis < (n); ++dis) { dp[x][dis] = dp[x][0]; int cur = d[dis]; for (int i = (0); i < (g[x].size()); ++i) { int to = g[x][i]; cur += dp[to][dis + 1]; } if (cur < dp[x][dis]) { dp[x][dis] = cur; } } } void getans(int x, int dis, int lst) { if (dp[x][dis] != dp[x][0]) { ans[x] = lst; for (int i = (0); i < (g[x].size()); ++i) { int to = g[x][i]; getans(to, dis + 1, lst); } return; } int y = pos[x]; int z = y; dis = 0; lst = -1; while (1) { ans[z] = y; dis++; for (int i = (0); i < (g[z].size()); ++i) { int to = g[z][i]; if (to == lst) continue; getans(to, dis, y); } if (z == x) break; lst = z; z = par[z]; } } int main() { memset(dp, 0x3f, sizeof(dp)); cin >> n >> k; for (int i = (1); i < (n); ++i) cin >> d[i]; for (int i = (1); i < (n); ++i) { int a, b; cin >> a >> b; a--; b--; g[a].push_back(b); g[b].push_back(a); } build(0, -1); dfs(0); cout << dp[0][0] << endl; getans(0, 0, -1); for (int i = (0); i < (n); ++i) { cout << ans[i] + 1 << (i == n - 1 ? n : ); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O2BB2A_PP_SYMBOL_V
`define SKY130_FD_SC_HS__O2BB2A_PP_SYMBOL_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o2bb2a (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O2BB2A_PP_SYMBOL_V
|
/*
* Internal RAM for VGA
* Copyright (C) 2010 Zeus Gomez Marmolejo <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vdu_ram_2k_char (
input clk,
input rst,
input we,
input [10:0] addr,
output [ 7:0] rdata,
input [ 7:0] wdata
);
// Registers and nets
reg [ 7:0] mem[0:2047];
reg [10:0] addr_reg;
always @(posedge clk)
begin
if (we) mem[addr] <= wdata;
addr_reg <= addr;
end
// Combinatorial logic
assign rdata = mem[addr_reg];
initial $readmemh("buff_rom.dat", mem);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; scanf( %d , &t); while (t--) { int n; scanf( %d , &n); int a[n], b[n]; for (int i = 0; i < n; i++) scanf( %d%d , &a[i], &b[i]); if (a[0] < b[0]) printf( NO n ); else { int f = 1; for (int i = 1; i < n; i++) { if (a[i] < a[i - 1] || b[i] < b[i - 1]) { f = 0; break; } if (a[i] - a[i - 1] < b[i] - b[i - 1]) { f = 0; break; } } if (f) printf( YES n ); else printf( NO n ); } } return 0; } |
#include <bits/stdc++.h> using namespace std; int n; int query(int x1, int y1, int x2, int y2) { if (x1 > x2 || y1 > y2) return 0; printf( ? %d %d %d %d n , x1, y1, x2, y2); fflush(stdout); int ans; scanf( %d , &ans); return ans; } int get_right(int x1, int y1, int x2, int y2) { int left = x1 - 1, right = x2; while (right - left > 1) { int mid = (left + right) / 2; if (query(x1, y1, mid, y2) == 1) right = mid; else left = mid; } return right; } int get_left(int x1, int y1, int x2, int y2) { int left = x1, right = x2 + 1; while (right - left > 1) { int mid = (left + right) / 2; if (query(mid, y1, x2, y2) == 1) left = mid; else right = mid; } return left; } int get_up(int x1, int y1, int x2, int y2) { int left = y1 - 1, right = y2; while (right - left > 1) { int mid = (left + right) / 2; if (query(x1, y1, x2, mid) == 1) right = mid; else left = mid; } return right; } int get_down(int x1, int y1, int x2, int y2) { int left = y1, right = y2 + 1; while (right - left > 1) { int mid = (left + right) / 2; if (query(x1, mid, x2, y2) == 1) left = mid; else right = mid; } return left; } bool solve_x() { int left = 0, right = n; while (right - left > 1) { int mid = (left + right) / 2; if (query(1, 1, mid, n) > 0) right = mid; else left = mid; } if (query(right + 1, 1, n, n) != 1) return false; int L1 = get_left(1, 1, right, n); int R1 = get_right(1, 1, right, n); int D1 = get_down(1, 1, right, n); int U1 = get_up(1, 1, right, n); int L2 = get_left(right + 1, 1, n, n); int R2 = get_right(right + 1, 1, n, n); int D2 = get_down(right + 1, 1, n, n); int U2 = get_up(right + 1, 1, n, n); printf( ! %d %d %d %d %d %d %d %d n , L1, D1, R1, U1, L2, D2, R2, U2); fflush(stdout); return true; } bool solve_y() { int left = 0, right = n; while (right - left > 1) { int mid = (left + right) / 2; if (query(1, 1, n, mid) > 0) right = mid; else left = mid; } if (query(1, right + 1, n, n) != 1) return false; int L1 = get_left(1, 1, n, right); int R1 = get_right(1, 1, n, right); int D1 = get_down(1, 1, n, right); int U1 = get_up(1, 1, n, right); int L2 = get_left(1, right + 1, n, n); int R2 = get_right(1, right + 1, n, n); int D2 = get_down(1, right + 1, n, n); int U2 = get_up(1, right + 1, n, n); printf( ! %d %d %d %d %d %d %d %d n , L1, D1, R1, U1, L2, D2, R2, U2); fflush(stdout); return true; } void solve() { scanf( %d , &n); if (!solve_x()) if (!solve_y()) throw; } int main() { solve(); 0; } |
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ecc_dec_fix.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_0_ecc_dec_fix
#(
parameter TCQ = 100,
parameter PAYLOAD_WIDTH = 64,
parameter CODE_WIDTH = 72,
parameter DATA_WIDTH = 64,
parameter DQ_WIDTH = 72,
parameter ECC_WIDTH = 8,
parameter nCK_PER_CLK = 4
)
(
/*AUTOARG*/
// Outputs
rd_data, ecc_single, ecc_multiple,
// Inputs
clk, rst, h_rows, phy_rddata, correct_en, ecc_status_valid
);
input clk;
input rst;
// Compute syndromes.
input [CODE_WIDTH*ECC_WIDTH-1:0] h_rows;
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rddata;
wire [2*nCK_PER_CLK*ECC_WIDTH-1:0] syndrome_ns;
genvar k;
genvar m;
generate
for (k=0; k<2*nCK_PER_CLK; k=k+1) begin : ecc_word
for (m=0; m<ECC_WIDTH; m=m+1) begin : ecc_bit
assign syndrome_ns[k*ECC_WIDTH+m] =
^(phy_rddata[k*DQ_WIDTH+:CODE_WIDTH] & h_rows[m*CODE_WIDTH+:CODE_WIDTH]);
end
end
endgenerate
reg [2*nCK_PER_CLK*ECC_WIDTH-1:0] syndrome_r;
always @(posedge clk) syndrome_r <= #TCQ syndrome_ns;
// Extract payload bits from raw DRAM bits and register.
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] ecc_rddata_ns;
genvar i;
generate
for (i=0; i<2*nCK_PER_CLK; i=i+1) begin : extract_payload
assign ecc_rddata_ns[i*PAYLOAD_WIDTH+:PAYLOAD_WIDTH] =
phy_rddata[i*DQ_WIDTH+:PAYLOAD_WIDTH];
end
endgenerate
reg [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] ecc_rddata_r;
always @(posedge clk) ecc_rddata_r <= #TCQ ecc_rddata_ns;
// Regenerate h_matrix from h_rows leaving out the identity part
// since we're not going to correct the ECC bits themselves.
genvar n;
genvar p;
wire [ECC_WIDTH-1:0] h_matrix [DATA_WIDTH-1:0];
generate
for (n=0; n<DATA_WIDTH; n=n+1) begin : h_col
for (p=0; p<ECC_WIDTH; p=p+1) begin : h_bit
assign h_matrix [n][p] = h_rows [p*CODE_WIDTH+n];
end
end
endgenerate
// Compute flip bits.
wire [2*nCK_PER_CLK*DATA_WIDTH-1:0] flip_bits;
genvar q;
genvar r;
generate
for (q=0; q<2*nCK_PER_CLK; q=q+1) begin : flip_word
for (r=0; r<DATA_WIDTH; r=r+1) begin : flip_bit
assign flip_bits[q*DATA_WIDTH+r] =
h_matrix[r] == syndrome_r[q*ECC_WIDTH+:ECC_WIDTH];
end
end
endgenerate
// Correct data.
output reg [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data;
input correct_en;
integer s;
always @(/*AS*/correct_en or ecc_rddata_r or flip_bits)
for (s=0; s<2*nCK_PER_CLK; s=s+1)
if (correct_en)
rd_data[s*PAYLOAD_WIDTH+:DATA_WIDTH] =
ecc_rddata_r[s*PAYLOAD_WIDTH+:DATA_WIDTH] ^
flip_bits[s*DATA_WIDTH+:DATA_WIDTH];
else rd_data[s*PAYLOAD_WIDTH+:DATA_WIDTH] =
ecc_rddata_r[s*PAYLOAD_WIDTH+:DATA_WIDTH];
// Copy raw payload bits if ECC_TEST is ON.
localparam RAW_BIT_WIDTH = PAYLOAD_WIDTH - DATA_WIDTH;
genvar t;
generate
if (RAW_BIT_WIDTH > 0)
for (t=0; t<2*nCK_PER_CLK; t=t+1) begin : copy_raw_bits
always @(/*AS*/ecc_rddata_r)
rd_data[(t+1)*PAYLOAD_WIDTH-1-:RAW_BIT_WIDTH] =
ecc_rddata_r[(t+1)*PAYLOAD_WIDTH-1-:RAW_BIT_WIDTH];
end
endgenerate
// Generate status information.
input ecc_status_valid;
output wire [2*nCK_PER_CLK-1:0] ecc_single;
output wire [2*nCK_PER_CLK-1:0] ecc_multiple;
genvar v;
generate
for (v=0; v<2*nCK_PER_CLK; v=v+1) begin : compute_status
wire zero = ~|syndrome_r[v*ECC_WIDTH+:ECC_WIDTH];
wire odd = ^syndrome_r[v*ECC_WIDTH+:ECC_WIDTH];
assign ecc_single[v] = ecc_status_valid && ~zero && odd;
assign ecc_multiple[v] = ecc_status_valid && ~zero && ~odd;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int k, a, b; cin >> k >> a >> b; if (a / k + b / k && a % k <= (b / k) * (k - 1) && b % k <= (a / k) * (k - 1)) cout << a / k + b / k << n ; else cout << -1 n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, dp[300005], k = 0, b[300005]; vector<int> ke[300005]; void dfs(int u, int par) { if (ke[u].size() == 1 && u != 1) { dp[u] = 1; k++; return; } if (b[u]) dp[u] = 1e9; else dp[u] = 0; for (int v : ke[u]) if (v != par) { dfs(v, u); if (b[u]) dp[u] = min(dp[u], dp[v]); else dp[u] += dp[v]; } } int main() { ios::sync_with_stdio(0); cin.tie(); cout.tie(); cin >> n; for (int i = 1; i <= n; i++) cin >> b[i]; int u; for (int i = 2; i <= n; i++) { cin >> u; ke[u].push_back(i); ke[i].push_back(u); } dfs(1, 0); cout << k - dp[1] + 1; return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:57:24 11/17/2016
// Design Name:
// Module Name: DLAU
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module DALU(
// Input signals
clk,
rst,
in_valid,
instruction,
// Output signals
out_valid,
out
);
//---------------------------------------------------------------------
// INPUT AND OUTPUT DECLARATION
//---------------------------------------------------------------------
input clk;
input rst;
input in_valid;
input [18:0] instruction;
output reg out_valid;
output reg signed [15:0] out;
//---------------------------------------------------------------------
// PARAMETER DECLARATION
//---------------------------------------------------------------------
parameter IDLE=0, INPUT=1, OUTPUT=2, OP=3;
//---------------------------------------------------------------------
// WIRE AND REG DECLARATION
//---------------------------------------------------------------------
reg [1:0] cState, nState;
wire [2:0] L;
wire signed [5:0] s, t;
wire signed [3:0] l;
wire signed [9:0] i;
//---------------------------------------------------------------------
// Combinational Circuits
//---------------------------------------------------------------------
assign L = instruction[18:16];
assign s = instruction[15:10];
assign t = instruction[9:4];
assign l = instruction[3:0];
assign i = instruction[9:0];
//---------------------------------------------------------------------
// Finite-State Mechine
//---------------------------------------------------------------------
// cState
always@(posedge clk, posedge rst)
begin
if(rst) cState <= IDLE;
else cState <= nState;
end
// nState
always@(*)
begin
case(cState)
IDLE: if(in_valid) nState = INPUT;
INPUT: if(!in_valid) nState = OUTPUT;
OUTPUT: nState = IDLE;
default: nState = IDLE;
endcase
end
//---------------------------------------------------------------------
// Design Description
//---------------------------------------------------------------------
// out_valid
always@(posedge clk, posedge rst)
begin
if(rst) out_valid <= 0;
else begin
case(cState)
IDLE: out_valid <= 0;
INPUT: out_valid <= 0;
OUTPUT: out_valid <= 1;
default: out_valid <= out_valid;
endcase
end
end
// out
always@(posedge clk, posedge rst)
begin
if(rst) out <= 0;
else begin
case(cState)
IDLE: begin
if(nState == INPUT) begin
case(L)
0: begin
case(l)
0: out <= s & t;
1: out <= s | t;
2: out <= s ^ t;
3: out <= s + t;
4: out <= s - t;
default: out <= out;
endcase
end
1: out <= s * t * l;
2: out <= (s+t+l) * (s+t+l);
3: out <= s + i;
4: out <= s - i;
default: out <= out;
endcase
end
end
INPUT: out <= out;
OUTPUT: out <= out;
default: out <= out;
endcase
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's DC TAG RAMs ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Instatiation of data cache tag rams. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_dc_tag.v,v $
// Revision 1.5 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.4 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.2.4.1 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.2 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "rtl/verilog/or1200/timescale.v"
// synopsys translate_on
`include "rtl/verilog/or1200/or1200_defines.v"
module or1200_dc_tag(
// Clock and reset
clk, rst,
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Internal i/f
addr, en, we, datain, tag_v, tag
);
parameter dw = `OR1200_DCTAG_W;
parameter aw = `OR1200_DCTAG;
//
// I/O
//
input clk;
input rst;
input [aw-1:0] addr;
input en;
input we;
input [dw-1:0] datain;
output tag_v;
output [dw-2:0] tag;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
`ifdef OR1200_NO_DC
//
// Data cache not implemented
//
assign tag = {dw-1{1'b0}};
assign tag_v = 1'b0;
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`else
//
// Instantiation of TAG RAM block
//
`ifdef OR1200_DC_1W_4KB
or1200_spram_256x21 dc_tag0(
`endif
`ifdef OR1200_DC_1W_8KB
or1200_spram_512x20 dc_tag0(
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.clk(clk),
.rst(rst),
.ce(en),
.we(we),
.oe(1'b1),
.addr(addr),
.di(datain),
.doq({tag, tag_v})
);
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 100005; int a[N], c[N]; int ans[N]; struct qq { int x, y, id; } s[N]; int n, Q; bool cmp(qq x, qq y) { return x.y < y.y; } int q[N]; int st, ed, now; double Y(int x) { return a[x] * x - c[x]; } double X(int x) { return -a[x]; } double get_k(int x, int y) { return (double)(Y(x) - Y(y)) / (double)(X(x) - X(y)); } int calc(int xx, int x, int y) { return c[y] - c[xx] + a[xx] * (x - y + xx); } void solve() { st = 1; ed = 0; now = 1; for (int u = 1; u <= n; u++) { while (st <= ed && a[q[ed]] >= a[u]) ed--; while (st < ed && get_k(q[ed - 1], q[ed]) < get_k(q[ed], u)) ed--; q[++ed] = u; while (now <= Q && s[now].y == u) { int l = st, r = ed, lalal; while (l <= r) { int mid = (l + r) >> 1; if (mid == ed || calc(q[mid], s[now].x, s[now].y) < calc(q[mid + 1], s[now].x, s[now].y)) { lalal = mid; r = mid - 1; } else l = mid + 1; } ans[s[now].id] = calc(q[lalal], s[now].x, s[now].y); now++; } } } int read() { char ch = getchar(); int x = 0; while (ch < 0 || ch > 9 ) ch = getchar(); while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x; } int main() { n = read(); for (int u = 1; u <= n; u++) { a[u] = read(); c[u] = c[u - 1] + a[u]; } Q = read(); for (int u = 1; u <= Q; u++) { s[u].x = read(); s[u].y = read(); s[u].id = u; } sort(s + 1, s + 1 + Q, cmp); solve(); for (int u = 1; u <= Q; u++) printf( %d n , ans[u]); return 0; } |
#include <bits/stdc++.h> using namespace std; int st(int x, int pos) { return x = x | (1 << pos); } int Reset(int x, int pos) { return x = x & ~(1 << pos); } int main() { long long x1, y1, x2, y2; cin >> x1 >> y1 >> x2 >> y2; if (x1 == x2) { cout << 4 + 2 * (abs(y1 - y2) + 1) << endl; } else if (y1 == y2) { cout << 4 + 2 * (abs(x1 - x2) + 1) << endl; } else cout << (abs(x1 - x2) + 1 + abs(y1 - y2) + 1) * 2 << endl; } |
#include <bits/stdc++.h> using namespace std; struct ppp { int x, y, id; } a[120000], b[120000]; int i, j, k, l, n, m, p, t; bool cmp(const ppp& a, const ppp& b) { return a.y < b.y || a.y == b.y && a.x > b.x; } bool cmp2(const ppp& a, const ppp& b) { return a.x > b.x || a.x == b.x && a.y > b.y; } int main() { scanf( %d%d%d , &n, &p, &m); for (i = 1; i <= n; ++i) scanf( %d%d , &a[i].x, &a[i].y), a[i].id = i; sort(a + 1, a + n + 1, cmp); p -= m; for (i = p + 1; i <= n; ++i) b[i].x = a[i].x, b[i].y = i; sort(b + p + 1, b + n + 1, cmp2); t = n; for (i = p + 1; i <= p + m; ++i) { t = min(t, b[i].y); printf( %d , a[b[i].y].id); } for (i = 1; i <= p; ++i) printf( %d , a[t - i].id); } |
module edma (/*AUTOARG*/
// Outputs
mi_dout, edma_access, edma_packet,
// Inputs
reset, clk, mi_en, mi_we, mi_addr, mi_din, edma_wait
);
/******************************/
/*Compile Time Parameters */
/******************************/
parameter RFAW = 6;
parameter AW = 32;
parameter DW = 32;
parameter PW = 104;
/******************************/
/*HARDWARE RESET (EXTERNAL) */
/******************************/
input reset;
input clk;
/*****************************/
/*REGISTER INTERFACE */
/*****************************/
input mi_en;
input mi_we;
input [RFAW+1:0] mi_addr;
input [63:0] mi_din;
output [31:0] mi_dout;
/*****************************/
/*DMA TRANSACTION */
/*****************************/
output edma_access;
output [PW-1:0] edma_packet;
input edma_wait;
assign edma_access=1'b0;
assign edma_packet='d0;
assign mi_dout='d0;
/*
//registers
reg [AW-1:0] edma_srcaddr_reg;
reg [AW-1:0] edma_dstaddr_reg;
reg [AW-1:0] edma_count_reg;
reg [AW-1:0] edma_stride_reg;
reg [8:0] edma_cfg_reg;
reg [1:0] edma_status_reg;
reg [31:0] mi_dout;
//wires
wire edma_write;
wire edma_read;
wire edma_cfg_write ;
wire edma_srcaddr_write;
wire edma_dstaddr_write;
wire edma_stride_write;
wire edma_count_write;
wire edma_message;
wire edma_expired;
wire edma_last_tran;
wire edma_error;
wire edma_enable;
//read/write decode
assign edma_write = mi_en & mi_we;
assign edma_read = mi_en & ~mi_we;
//DMA configuration
assign edma_cfg_write = edma_write & (mi_addr[RFAW+1:2]==`EDMACFG);
assign edma_srcaddr_write = edma_write & (mi_addr[RFAW+1:2]==`EDMASRCADDR);
assign edma_dstaddr_write = edma_write & (mi_addr[RFAW+1:2]==`EDMADSTADDR);
assign edma_count_write = edma_write & (mi_addr[RFAW+1:2]==`EDMACOUNT);
assign edma_stride_write = edma_write & (mi_addr[RFAW+1:2]==`EDMASTRIDE);
//###########################
//# DMACFG
//###########################
always @ (posedge clk or posedge reset)
if(reset)
edma_cfg_reg[8:0] <= 'd0;
else if (edma_cfg_write)
edma_cfg_reg[8:0] <= mi_din[8:0];
assign edma_enable = edma_cfg_reg[0]; //should be zero
assign edma_message = edma_cfg_reg[8];
assign edma_access = edma_enable & ~edma_expired;
assign edma_write = edma_cfg_reg[1]; //only 1 for test pattern
assign edma_datamode[1:0] = edma_cfg_reg[3:2];
assign edma_ctrlmode[3:0] = (edma_message & edma_last_tran) ? 4'b1100 : edma_cfg_reg[7:4];
//###########################
//# DMASTATUS
//###########################
//Misalignment
assign edma_error = ((edma_srcaddr_reg[0] | edma_dstaddr_reg[0]) & (edma_datamode[1:0]!=2'b00)) | //16/32/64
((edma_srcaddr_reg[1] | edma_dstaddr_reg[1]) & (edma_datamode[1])) | //32/64
((edma_srcaddr_reg[2] | edma_dstaddr_reg[2]) & (edma_datamode[1:0]==2'b11)); //64
always @ (posedge clk or posedge reset)
if(reset)
edma_status_reg[1:0] <= 'd0;
else if (edma_cfg_write)
edma_status_reg[1:0] <= mi_din[1:0];
else if (edma_enable)
begin
edma_status_reg[0] <= edma_enable & ~edma_expired;//dma busy
edma_status_reg[1] <= edma_status_reg[1] | (edma_enable & edma_error);
end
//###########################
//# EDMASRCADDR
//###########################
always @ (posedge clk or posedge reset)
if(reset)
edma_srcaddr_reg[AW-1:0] <= 'd0;
else if (edma_srcaddr_write)
edma_srcaddr_reg[AW-1:0] <= mi_din[AW-1:0];
else if (edma_enable & ~edma_wait)
edma_srcaddr_reg[AW-1:0] <= edma_srcaddr_reg[AW-1:0] + (1<<edma_datamode[1:0]);
assign edma_srcaddr[31:0] = edma_srcaddr_reg[31:0];
//###########################
//# EDMADSTADR
//###########################
always @ (posedge clk or posedge reset)
if(reset)
edma_dstaddr_reg[AW-1:0] <= 'd0;
else if (edma_dstaddr_write)
edma_dstaddr_reg[AW-1:0] <= mi_din[AW-1:0];
else if (edma_enable & ~edma_wait)
edma_dstaddr_reg[AW-1:0] <= edma_dstaddr_reg[AW-1:0] + (1<<edma_datamode[1:0]);
assign edma_dstaddr[31:0] = edma_dstaddr_reg[31:0];
//###########################
//# EDMACOUNT
//###########################
always @ (posedge clk or posedge reset)
if(reset)
edma_count_reg[AW-1:0] <= 'd0;
else if (edma_count_write)
edma_count_reg[AW-1:0] <= mi_din[AW-1:0];
else if (edma_enable & ~edma_wait)
edma_count_reg[AW-1:0] <= edma_count_reg[AW-1:0] - 1'b1;
assign edma_last_tran = (edma_count_reg[AW-1:0]==32'b1);
assign edma_expired = (edma_count_reg[AW-1:0]==32'b0);
//###########################
//# EDMASTRIDE
//###########################
//NOTE: not supported yet, need to think about feature...
always @ (posedge clk or posedge reset)
if(reset)
edma_stride_reg[AW-1:0] <= 'd0;
else if (edma_stride_write)
edma_stride_reg[AW-1:0] <= mi_din[AW-1:0];
//###########################
//# DUMMY DATA
//###########################
assign edma_data[31:0] = TEST_PATTERN;
//###########################
//# PACKET CREATION
//###########################
emesh2packet e2p (
// Outputs
.packet_out (edma_packet[PW-1:0]),
// Inputs
.access_in (edma_access),
.write_in (edma_write),
.datamode_in (edma_datamode[1:0]),
.ctrlmode_in (edma_ctrlmode[3:0]),
.dstaddr_in (edma_dstaddr[AW-1:0]),
.data_in (edma_data[DW-1:0]),
.srcaddr_in (edma_srcaddr_in[AW-1:0]));
//###############################
//# DATA READBACK MUX
//###############################
//Pipelineing readback
always @ (posedge clk)
if(edma_read)
case(mi_addr[RFAW+1:2])
`EDMACFG: mi_dout[31:0] <= {23'b0, edma_cfg_reg[8:0]};
`EDMASTATUS: mi_dout[31:0] <= {30'b0, edma_status_reg[1:0]};
`EDMASRCADDR:mi_dout[31:0] <= {edma_srcaddr_reg[31:0]};
`EDMADSTADDR:mi_dout[31:0] <= {edma_dstaddr_reg[31:0]};
`EDMACOUNT: mi_dout[31:0] <= {edma_count_reg[31:0]};
default: mi_dout[31:0] <= 32'd0;
endcase // case (mi_addr[RFAW+1:2])
else
begin
default: mi_dout[31:0] <= 32'd0;
end
*/
endmodule // edma
// Local Variables:
// verilog-library-directories:("." "../../common/hdl")
// End:
/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Andreas Olofsson <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
|
#include <bits/stdc++.h> using namespace std; long long int n, m, k, w; vector<vector<vector<char>>> mp; struct dsu { vector<long long int> p, sz; dsu(long long int n) { p.resize(n); sz.resize(n, 1); for (long long int i = 0; i < n; i++) p[i] = i; } long long int getRoot(long long int v) { if (p[v] == v) return v; else return p[v] = getRoot(p[v]); } void unite(long long int a, long long int b) { a = getRoot(a); b = getRoot(b); if (a != b) { if (sz[a] < sz[b]) swap(a, b); p[b] = a; sz[a] += sz[b]; } } bool inOne(long long int a, long long int b) { a = getRoot(a); b = getRoot(b); return a == b; } }; long long int getR(long long int a, long long int b) { long long int ans = 0; for (long long int i = 0; i < n; i++) { for (long long int j = 0; j < m; j++) { ans += (mp[a][i][j] != mp[b][i][j]); } } return ans; } struct edge { long long int a, b, w; edge(long long int a = 0, long long int b = 0, long long int w = 0) { this->a = a; this->b = b; this->w = w; } }; bool cmp(const edge& a, const edge& b) { return a.w < b.w; } vector<vector<long long int>> g; vector<pair<long long int, long long int>> path; void dfs(long long int v = 0, long long int p = -1) { if (p > -1) path.push_back({v, p}); for (auto to : g[v]) { if (to == p) continue; dfs(to, v); } } signed main() { cin >> n >> m >> k >> w; mp.resize(k + 1, vector<vector<char>>(n, vector<char>(m))); g.resize(k + 1); for (long long int i = 1; i <= k; i++) { for (long long int j = 0; j < n; j++) { for (long long int w = 0; w < m; w++) cin >> mp[i][j][w]; } } vector<edge> ed; for (long long int i = 1; i <= k; i++) ed.push_back(edge(0, i, n * m)); for (long long int i = 1; i <= k; i++) { for (long long int j = i + 1; j <= k; j++) ed.push_back(edge(i, j, getR(i, j) * w)); } sort(ed.begin(), ed.end(), cmp); dsu s(k + 1); long long int ans = 0; for (auto e : ed) { long long int a = e.a, b = e.b, w = e.w; if (s.inOne(a, b)) continue; ans += w; s.unite(a, b); g[a].push_back(b); g[b].push_back(a); } dfs(); cout << ans << n ; for (auto i : path) cout << i.first << << i.second << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { unsigned long long n, ans = 0, a[30], cur, deg = 20, countOfPair = 1; cin >> n; memset(a, 0, sizeof(unsigned long long) * 30); for (int i = 0; i < n; ++i) { cin >> cur; ++a[cur + 10]; } for (int i = 0; i < 10; ++i) { ans += a[i] * a[deg + i]; deg -= 2; } if (a[10] != 0 && a[10] != 1) { if (a[10] == 2) ans += 1; else { for (unsigned int i = 3; i <= a[10]; ++i) { countOfPair = countOfPair + i - 1; } ans += countOfPair; } } cout << ans; cin >> n; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; int a[n]; int c[101] = {0}; for (int i = 0; i < n; i++) cin >> a[i]; long long int sum = a[0]; int b[n]; b[0] = 0; c[a[0]]++; for (int i = 1; i < n; i++) { sum = sum + a[i]; long long int ex = sum - m; if (ex <= 0) { b[i] = 0; c[a[i]]++; continue; } int cnt = 0; for (int k = 100; k >= 1; k--) { if (ex <= c[k] * k) { cnt += (ex + k - 1) / k; ex = 0; break; } cnt = cnt + c[k]; ex = ex - c[k] * k; } b[i] = cnt; c[a[i]]++; } for (int i = 0; i < n; i++) cout << b[i] << ; cout << endl; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:45:05 04/18/2015
// Design Name: rgb2ycbcr
// Module Name: /home/vka/Programming/VHDL/workspace/sysrek/skin_color_segm/tb_rgb2ycbcr.v
// Project Name: vision
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: rgb2ycbcr
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_rgb2ycbcr;
// Inputs
reg clk = 0;
reg ce = 1'b1;
reg [7:0] R;
reg [7:0] G;
reg [7:0] B;
reg in_hsync = 0;
reg in_vsync = 0;
reg in_de = 0;
// Outputs
wire [7:0] Y;
wire [7:0] Cb;
wire [7:0] Cr;
wire out_hsync;
wire out_vsync;
wire out_de;
// Instantiate the Unit Under Test (UUT)
rgb2ycbcr uut (
.clk(clk),
.ce(ce),
.R(R),
.G(G),
.B(B),
.in_hsync(in_hsync),
.in_vsync(in_vsync),
.in_de(in_de),
.Y(Y),
.Cb(Cb),
.Cr(Cr),
.out_hsync(out_hsync),
.out_vsync(out_vsync),
.out_de(out_de)
);
initial begin
// Initialize Inputs
clk = 0;
ce = 1;
R = 8'b11110011;
G = 8'b00001100;
B = 8'b00101101;
in_hsync = 0;
in_vsync = 0;
in_de = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
// oczekiwane wyjscie
// Y = 01010100;
// Cb= 01101001;
// Cr= 11110000;
end
always #1 clk = ~clk;
endmodule
|
#include <bits/stdc++.h> using namespace std; char chess[8][8]; int main() { for (int i = 0; i < 8; i++) scanf( %s , chess[i]); for (int i = 0; i < 8; i++) { for (int j = 0; j < 7; j++) { if (chess[i][j] == chess[i][j + 1]) { printf( NO n ); return 0; } } } printf( YES n ); return 0; } |
`timescale 1ns / 1ps
/*
* Simple Brainfuck CPU in Verilog.
* Copyright (C) 2011 Sergey Gridasov <>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module ClockManager(
(* buffer_type = "ibufg" *) input CLK_IN,
input RESET_IN,
output CLK_MAIN,
output reg RESET
);
parameter DELAY = 4;
reg [DELAY - 1:0] CNT_SLOW;
reg CLK_SLOW;
always @ (posedge CLK_IN)
if(RESET_IN)
CNT_SLOW <= 0;
else
CNT_SLOW <= CNT_SLOW + 1;
always @ (posedge CLK_IN)
if(RESET_IN)
begin
RESET <= 1'b1;
CLK_SLOW <= 1'b0;
end
else if(CNT_SLOW == (1 << DELAY) - 1)
begin
RESET <= 1'b0;
CLK_SLOW <= ~CLK_SLOW;
end
assign CLK_MAIN = CLK_IN;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:21:14 08/24/2011
// Design Name:
// Module Name: q15_mult
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module qmult #(
//Parameterized values
parameter Q = 15,
parameter N = 32
)
(
input [N-1:0] i_multiplicand,
input [N-1:0] i_multiplier,
output [N-1:0] o_result,
output reg ovr
);
// The underlying assumption, here, is that both fixed-point values are of the same length (N,Q)
// Because of this, the results will be of length N+N = 2N bits....
// This also simplifies the hand-back of results, as the binimal point
// will always be in the same location...
reg [2*N-1:0] r_result; // Multiplication by 2 values of N bits requires a
// register that is N+N = 2N deep...
reg [N-1:0] r_RetVal;
//--------------------------------------------------------------------------------
assign o_result = r_RetVal; // Only handing back the same number of bits as we received...
// with fixed point in same location...
//---------------------------------------------------------------------------------
always @(i_multiplicand, i_multiplier) begin // Do the multiply any time the inputs change
r_result <= i_multiplicand[N-2:0] * i_multiplier[N-2:0]; // Removing the sign bits from the multiply - that
// would introduce *big* errors
ovr <= 1'b0; // reset overflow flag to zero
end
// This always block will throw a warning, as it uses a & b, but only acts on changes in result...
always @(r_result) begin // Any time the result changes, we need to recompute the sign bit,
r_RetVal[N-1] <= i_multiplicand[N-1] ^ i_multiplier[N-1]; // which is the XOR of the input sign bits... (you do the truth table...)
r_RetVal[N-2:0] <= r_result[N-2+Q:Q]; // And we also need to push the proper N bits of result up to
// the calling entity...
if (r_result[2*N-2:N-1+Q] > 0) // And finally, we need to check for an overflow
ovr <= 1'b1;
end
endmodule
|
// ******************************************************************************* //
// ** General Information ** //
// ******************************************************************************* //
// ** Module : iReg.v ** //
// ** Project : ISAAC NEWTON ** //
// ** Author : Kayla Nguyen ** //
// ** First Release Date : August 5, 2008 ** //
// ** Description : Internal Register for Newton core ** //
// ******************************************************************************* //
// ** Revision History ** //
// ******************************************************************************* //
// ** ** //
// ** File : iReg.v ** //
// ** Revision : 1 ** //
// ** Author : kaylangu ** //
// ** Date : August 5, 2008 ** //
// ** FileName : ** //
// ** Notes : Initial Release for ISAAC demo ** //
// ** ** //
// ** File : iReg.v ** //
// ** Revision : 2 ** //
// ** Author : kaylangu ** //
// ** Date : August 19, 2008 ** //
// ** FileName : ** //
// ** Notes : 1. Register 0 functional modification ** //
// ** 2. Bit ReOrdering function change to for loop ** //
// ** 3. Register 1 and Register 2 counter modify to use ** //
// ** Write Enable bits ** //
// ** ** //
// ** File : iReg.v ** //
// ** Revision : 3 ** //
// ** Author : kaylangu ** //
// ** Date : October 23, 2008 ** //
// ** FileName : ** //
// ** Notes : Change interrupt signal to be only one clock long ** //
// ** ** //
// ******************************************************************************* //
`timescale 1 ns / 100 ps
module iReg
(/*AUTOARG*/
// Outputs
ESCR, WPTR, ICNT, FREQ, OCNT, FCNT,
// Inputs
clk, arst, idata, iaddr, iwe, FIR_WE, WFIFO_WE
);
//**************************************************************************//
//* Declarations *//
//**************************************************************************//
// DATA TYPE - PARAMETERS
parameter r0setclr = 15; // Register 0 set/clr bit
parameter initWM = 8'h60;
// parameter ModuleVersion = 2;
// DATA TYPE - INPUTS AND OUTPUTS
input clk; // 100MHz Clock from BUS
input arst; // Asynchronous Reset (positive logic)
input [15:0] idata;
input [13:0] iaddr;
input iwe;
input FIR_WE;
input WFIFO_WE;
output [15:0] ESCR;
output [15:0] WPTR;
output [15:0] ICNT;
output [15:0] FREQ;
output [15:0] OCNT;
output [15:0] FCNT;
// DATA TYPE - INTERNAL REG
reg OVFL_MSK; // Overflow Mask
reg WMI_MSK; // WMI Mask
reg OVFL; // Overflow for CPTR
reg WMI; // Watermark Interrupt
reg [15:0] ICNT; // Counts the numbers of inputs
reg [7:0] OCNT_WM; // Output counter watermark
reg [7:0] OCNT_int; // Counts the numbers of outputs
reg FIR_WE_dly1;
reg [10:0] CPTR;
reg [15:0] FCNT;
reg SYNC;
// reg iReg_intr_d1;
// reg iReg_intr_1d;
reg [6:0] FREQ_int;
reg NEWFREQ;
reg START;
// DATA TYPE - INTERNAL WIRES
wire setclr;
wire reg0w;
wire reg1w;
wire reg2w;
wire reg3w;
wire reg4w;
//**************************************************************************//
//* REG 1 *//
//**************************************************************************//
assign setclr = reg0w & idata[r0setclr];
assign reg0w = (iaddr[2:0] == 3'h1) & iwe;
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
OVFL_MSK <= 1'b0;
else if (reg0w & idata[10])
OVFL_MSK <= idata[r0setclr];
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
WMI_MSK <= 1'b0;
else if (reg0w & idata[9])
WMI_MSK <= idata[r0setclr];
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
OVFL <= 1'b0;
else if (CPTR[10] == 1'b1) // BRAM pointer overflows
OVFL <= 1'b1;
else if (reg0w & idata[2])
OVFL <= idata[r0setclr];
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
START <= 1'b0;
else if (reg0w & idata[3])
START <= idata[r0setclr];
else if (WMI | (FCNT[11:0] == 12'b1111_1111_1110))
START <= 1'b0;
else
START <= START;
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
FIR_WE_dly1 <= 1'b0;
else
FIR_WE_dly1 <= FIR_WE;
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
WMI <= 1'b0;
else if (FIR_WE_dly1 & (OCNT_int[7:0] == OCNT_WM[7:0])) // Output counter overflows
WMI <= 1'b1;
else if (reg0w & idata[1])
WMI <= idata[r0setclr];
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
SYNC <= 1'b0;
else if (reg0w & idata[0])
SYNC <= idata[r0setclr];
// Read out
assign ESCR[15:0] = {setclr, 4'd0, OVFL_MSK, WMI_MSK, 5'd0, START,
OVFL, WMI, SYNC};
//**************************************************************************//
//* REG 2 *//
//**************************************************************************//
/*always @ (posedge clk or posedge arst)
if (arst != 1'b0)
SPTR[9:0] <= 10'd0;
else if (Bus2IP_WrCE[1])
SPTR[9:0] <= idata[25:16];*/
assign reg1w = (iaddr[2:0] == 3'h2) & iwe;
always @ (posedge clk or posedge SYNC)
if (SYNC != 1'b0)
CPTR[10:0] <= 11'd0;
else if (OVFL == 1'b1)
CPTR[10] <= 1'b0;
// else if (SYNC)
// CPTR[10:0] <= 11'd0;
else
CPTR[10:0] <= CPTR[10:0] + FIR_WE; //Pointer to BRAM address
// Readout
assign WPTR[15:0] = {6'd0, CPTR[9:0]};
//**************************************************************************//
//* REG 3 *//
//**************************************************************************//
assign reg2w = (iaddr[2:0] == 3'h3) & iwe;
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
ICNT[15:0] <= 16'd0;
else if (reg2w)
ICNT[15:0] <= idata[15:0];
else
ICNT[15:0] <= ICNT[15:0] + WFIFO_WE;
//**************************************************************************//
//* REG 4 *//
//**************************************************************************//
assign reg3w = (iaddr[2:0] == 3'h4) & iwe;
assign setclrf = reg3w & idata[7];
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
FREQ_int[6:0] <= 7'h41; //Resets to frequency 65MHz
else if (setclrf)
FREQ_int[6:0] <= idata[6:0];
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
NEWFREQ <= 1'b0;
else if (reg3w )
NEWFREQ <= idata[14];
assign FREQ[15:0] = {1'b0, NEWFREQ, 6'd0, setclrf, FREQ_int[6:0]};
//**************************************************************************//
//* REG 5 *//
//**************************************************************************//
assign reg4w = (iaddr[2:0] == 3'h5) & iwe;
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
OCNT_WM[7:0] <= initWM;
else if (reg4w)
OCNT_WM[7:0] <= idata[15:8];
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
OCNT_int[7:0] <= 8'd0;
else if (reg4w)
OCNT_int[7:0] <= idata[7:0];
else
OCNT_int[7:0] <= OCNT_int[7:0] + FIR_WE;
// Read out
assign OCNT[15:0] = {OCNT_WM[7:0], OCNT_int[7:0]};
//**************************************************************************//
//* REG 6 *//
//**************************************************************************//
assign reg5w = (iaddr[2:0] == 3'h6) & iwe;
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
FCNT[15:0] <= 16'd0;
else if (reg5w)
FCNT[15:0] <= idata[15:0];
else if (START)
FCNT[15:0] <= FCNT[15:0] + 1;
//**************************************************************************//
//* Read Out *//
//**************************************************************************//
//always @ (/*AS*/Bus2IP_RdCE or ESCR or ICNT or OCNT or WPTR)
/*begin
IP2Bus_Data_int[31:0] = 32'b0;
case (1'b1)
Bus2IP_RdCE[0] : IP2Bus_Data_int[31:0] = ESCR[31:0];
Bus2IP_RdCE[1] : IP2Bus_Data_int[31:0] = WPTR[31:0];
Bus2IP_RdCE[2] : IP2Bus_Data_int[31:0] = ICNT[31:0];
Bus2IP_RdCE[3] : IP2Bus_Data_int[31:0] = OCNT[31:0];
endcase // case (1'b1)
end*/
// assign iReg2IP_RdAck = |Bus2IP_RdCE[0:3];
// assign IP2Bus_WrAck = |Bus2IP_WrCE[0:3];
endmodule // iReg
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n; cin >> n; long long int a[n][2]; for (int i = 0; i < n; i++) cin >> a[i][0] >> a[i][1]; long long int l[n][2], r[n][2]; long long int mi = a[0][0]; long long int mx = a[0][1]; l[0][0] = mi; l[0][1] = mx; if (n == 1) { cout << a[0][1] - a[0][0]; return 0; } for (int i = 1; i < n; i++) { if (l[i - 1][0] == -1) { l[i][0] = -1; l[i][1] = -1; continue; } long long int x, y; x = max(a[i][0], l[i - 1][0]); y = min(a[i][1], l[i - 1][1]); if (y - x < 0) { l[i][0] = -1; l[i][1] = -1; } else { l[i][0] = x; l[i][1] = y; } } mx = a[n - 1][1]; mi = a[n - 1][0]; r[n - 1][0] = mi; r[n - 1][1] = mx; for (int i = n - 2; i >= 0; i--) { if (r[i + 1][0] == -1) { r[i][0] = -1; r[i][1] = -1; continue; } long long int x, y; x = max(a[i][0], r[i + 1][0]); y = min(a[i][1], r[i + 1][1]); if (y - x < 0) { r[i][0] = -1; r[i][1] = -1; } else { r[i][0] = x; r[i][1] = y; } } long long int ans = 0; if (l[n - 2][0] != -1) ans = l[n - 2][1] - l[n - 2][0]; if (r[1][0] != -1) ans = max(ans, r[1][1] - r[1][0]); for (int i = 1; i < n - 1; i++) { long long int x, y; if (l[i - 1][0] == -1 || r[i + 1][0] == -1) continue; x = max(l[i - 1][0], r[i + 1][0]); y = min(l[i - 1][1], r[i + 1][1]); ans = max(ans, max((long long int)0, y - x)); } cout << ans; } |
// Copyright 2021 The CFU-Playground Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
module Cfu (
input cmd_valid,
output cmd_ready,
input [9:0] cmd_payload_function_id,
input [31:0] cmd_payload_inputs_0,
input [31:0] cmd_payload_inputs_1,
output rsp_valid,
input rsp_ready,
output [31:0] rsp_payload_outputs_0,
input reset,
input clk,
output [13:0] port0_addr,
output [13:0] port1_addr,
output [13:0] port2_addr,
output [13:0] port3_addr,
input [31:0] port0_din,
input [31:0] port1_din,
input [31:0] port2_din,
input [31:0] port3_din,
);
reg cmd_valid_delay;
always @(posedge clk) if (rsp_ready) cmd_valid_delay <= cmd_valid;
// one clcok latency on the memory access
assign rsp_valid = cmd_valid_delay;
assign cmd_ready = rsp_ready;
// spam address to all banks
assign port0_addr = cmd_payload_inputs_1;
assign port1_addr = cmd_payload_inputs_1;
assign port2_addr = cmd_payload_inputs_1;
assign port3_addr = cmd_payload_inputs_1;
// pick result
reg [1:0] bank_sel;
always @(posedge clk) if (rsp_ready) bank_sel <= cmd_payload_inputs_0;
assign rsp_payload_outputs_0 = bank_sel[1] ? (bank_sel[0] ? port3_din : port2_din)
: (bank_sel[0] ? port1_din : port0_din);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long powmod(long long n, long long q) { long long ans = 1; n %= 1000000007; while (q > 0) { if (q & 1) ans = (ans * n) % 1000000007; n = (n * n) % 1000000007; q >>= 1; } return ans % 1000000007; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int tc = 1; while (tc--) { int n, ans = 0; cin >> n; for (int i = 1; i <= n; i++) { for (int j = i + 1; j <= n; j++) { int k = i ^ j; if (k < i + j) { if (i < k + j) { if (j < i + k) { if (k >= 1 && k <= n) ans++; } } } } } cout << ans / 3 << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 5e5 + 9; vector<pair<int, int> > barr[N]; int n, q, arr[N], a, b; long long t[N], ans[N]; int main() { cin >> n; for (int i = 1; i <= n; i++) cin >> arr[i]; scanf( %d , &q); int kok = sqrt(n); for (int i = 1; i <= q; i++) { scanf( %d %d , &a, &b); if (b > kok) { for (int j = a; j <= n; j += b) ans[i] += arr[j]; } else barr[b].push_back(make_pair(a, i)); } for (int i = 1; i <= kok; i++) { if (barr[i].size()) { for (int j = n; j >= 1; j--) t[j] = arr[j] + t[(i + j) * (i + j <= n)]; for (int j = 0; j < barr[i].size(); j++) ans[barr[i][j].second] = t[barr[i][j].first]; } } for (int i = 1; i <= q; i++) printf( %lld n , ans[i]); return 0; } |
#include <bits/stdc++.h> using namespace std; const int inf = 1 << 30; const long long linf = 1LL << 60; const int maxn = 100 + 5; int A[maxn]; bool used[maxn]; vector<int> Q; vector<vector<int> > B; vector<int> C; int n, k, m, q; long double anal() { long double res = 0; for (int i = 0; i < m; ++i) { res += (long double)A[B.back()[i] - 1]; used[B.back()[i] - 1] = 1; } res /= (long double)m; return res; } int main() { long double _min = inf; long double _max = -1; cin >> n >> k; for (int i = 0; i < n; ++i) cin >> A[i]; m = n / k; Q.reserve(m); cin >> q; for (int i = 0; i < q; ++i) { Q.clear(); for (int j = 0; j < m; ++j) { int x; cin >> x; Q.push_back(x); } sort((Q).begin(), (Q).end()); bool _new = 1; for (int j = 0; j < B.size(); ++j) { if (B[j][0] == Q[0]) { _new = 0; break; } } if (_new) { B.push_back(Q); long double _res = anal(); if (_min > _res) _min = _res; if (_max < _res) _max = _res; } } if ((int)(B).size() < k) { C.reserve(n); for (int i = 0; i < n; ++i) { if (!used[i]) C.push_back(A[i]); } sort((C).begin(), (C).end()); long double res = 0; for (int i = 0; i < m; ++i) { res += (long double)C[i]; } res /= (long double)m; if (_min > res) _min = res; if (_max < res) _max = res; res = 0; for (int i = (int)(C).size() - 1; i >= (int)(C).size() - m; --i) { res += (long double)C[i]; } res /= (long double)m; if (_min > res) _min = res; if (_max < res) _max = res; } cout.setf(ios::fixed); cout.precision(8); cout << _min << << _max << n ; return 0; } |
//-----------------------------------------------------
// Design Name : hw1_B_testbench_A_testcase
// File Name : hw1_B_testbench_A_testcase.v
// Function : This program will test hw1_B.v
// Coder : hydai
//-----------------------------------------------------
`timescale 1 ns/1 ns
`include "hw1_B.v"
module hw1_B_testbench_A_testcase ;
reg [15:0] data;
reg [15:0] control;
reg clk, rst_n;
wire [15:0] R0, R1, R2, R3;
hw1_B testA(data,
control,
clk,
rst_n,
R0,
R1,
R2,
R3);
initial begin
#0 rst_n = 1'b0; clk = 1'b0; control = 16'b111_111_111_0000;
$display ("====================================================================");
$display ("Simulate hw1_B");
$display ("Time %t status", $time);
$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
rst_n, data, control, R0, R1, R2, R3);
#20 rst_n = 1'b1;
$display ("====================================================================");
$display ("Time %t status", $time);
$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
rst_n, data, control, R0, R1, R2, R3);
// R1 <- Data(0x1234)
#20 data = 16'h1234; control = 16'b111_011_111_111_0010;
$display ("====================================================================");
$display ("Time %t status", $time);
$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
rst_n, data, control, R0, R1, R2, R3);
// R2 <- Data(0x8888)
#20 data = 16'h8888; control = 16'b111_111_011_111_0100;
$display ("====================================================================");
$display ("Time %t status", $time);
$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
rst_n, data, control, R0, R1, R2, R3);
// R1 <- R2; R2 <- R1
#20 control = 16'b111_001_001_111_0110;
$display ("====================================================================");
$display ("Time %t status", $time);
$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
rst_n, data, control, R0, R1, R2, R3);
// R3 <- R1; R0 <- R1
#20 control = 16'b000_111_111_001_1001;
$display ("====================================================================");
$display ("Time %t status", $time);
$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
rst_n, data, control, R0, R1, R2, R3);
#20
$display ("====================================================================");
$display ("Time %t status", $time);
$display ("rst_n = %b\tdata = %h\tcontrol = %b\nR0 = %h\tR1 = %h\tR2 = %h\tR3 = %h",
rst_n, data, control, R0, R1, R2, R3);
$display ("====================================================================");
#40 $finish;
end
always begin
#10 clk = ~clk;
end
initial begin
$fsdbDumpfile("hw1_B_testbench_A_testcase.fsdb");
$fsdbDumpvars;
end
endmodule // End of Module hw1_B_testbench_A_testcase
|
#include <bits/stdc++.h> using namespace std; inline int Get() { int res = 0, q = 1; char ch = getchar(); while ((ch < 0 || ch > 9 ) && ch != - ) ch = getchar(); if (ch == - ) q = -1, ch = getchar(); while (ch >= 0 && ch <= 9 ) res = res * 10 + ch - 0 , ch = getchar(); return res * q; } const double eps = 1e-12, pi = M_PI; const int oo = (int)2e9, mod = (int)1e9 + 7; const long long INF = (long long)1e17; int T; long long a, n, p, h; long long Calc(long long a, long long n, long long p) { long long rd = a * n / p; if (!rd) return ((a) > (p - a * n) ? (a) : (p - a * n)); long long dt = a * n % p, st = p - p % a - a; if (dt < st) --rd; return Calc(min(a - p % a, p % a), rd, a); } int main() { for (scanf( %d n , &T); T--;) { scanf( %I64d %I64d %I64d %I64d n , &a, &n, &p, &h), a %= p; if (a * n < p) printf( %s n , a <= h ? YES : NO ); else printf( %s n , Calc(a, n, p) <= h ? YES : NO ); } return 0; } |
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