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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND4B_FUNCTIONAL_V
`define SKY130_FD_SC_HD__AND4B_FUNCTIONAL_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__and4b (
X ,
A_N,
B ,
C ,
D
);
// Module ports
output X ;
input A_N;
input B ;
input C ;
input D ;
// Local signals
wire not0_out ;
wire and0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X, not0_out, B, C, D);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND4B_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__FILL_TB_V
`define SKY130_FD_SC_HVL__FILL_TB_V
/**
* fill: Fill cell.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__fill.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_hvl__fill dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__FILL_TB_V
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 5e5; vector<int> G[MAXN]; int happiness[MAXN], f[MAXN], tmpAns = 0, ans = 0; void dfs(int u, int par) { int oldTmpAns = -1, oldF = -1, oldFPos = -1; if (~par && f[tmpAns] < happiness[u]) oldTmpAns = tmpAns, f[++tmpAns] = happiness[u]; else { int pos = lower_bound(f, f + tmpAns, happiness[u]) - f; oldF = f[pos], oldFPos = pos; f[pos] = happiness[u]; } ans = max(ans, tmpAns); for (int i = 0; i < G[u].size(); i++) { int v = G[u][i]; if (v == par) continue; dfs(v, u); } if (oldTmpAns != -1) tmpAns = oldTmpAns; if (oldF != -1) f[oldFPos] = oldF; } int main() { int n; cin >> n; for (int i = 0; i < n; i++) cin >> happiness[i]; for (int i = 0; i < n - 1; i++) { int x, y; cin >> x >> y; --x, --y; G[x].push_back(y); G[y].push_back(x); } for (int i = 0; i < n; i++) { f[0] = happiness[i]; tmpAns = 0; dfs(i, -1); } cout << ans + 1 << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long maxn = 1e6 + 10, mod = 1e9 + 7, inf = 2e9, lg = 22, maskm = (1 << lg) - 1, maxm = (1 << lg) + 7; long long a[maxn], dp[maxm]; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n; cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; dp[a[i]] = a[i]; } for (int i = 1; i < maxm; i++) { for (int j = i; j && dp[i] == 0; j -= (j & -j)) { dp[i] = dp[i ^ (j & -j)]; } } for (int i = 0; i < n; i++) { long long tmp = maskm ^ a[i]; if (dp[tmp] == 0) cout << -1 << ; else cout << dp[tmp] << ; } } |
#include <bits/stdc++.h> using namespace std; const int mod = 998244353; inline int add(int x, int y) { x += y; return x >= mod ? x - mod : x; } inline int sub(int x, int y) { x -= y; return x < 0 ? x + mod : x; } inline int mul(int x, int y) { return 1ll * x * y % mod; } int quick_pow(int x, int y) { int res = 1; while (y) { if (y & 1) res = mul(res, x); x = mul(x, x), y >>= 1; } return res; } inline int getinv(int x) { return quick_pow(x, mod - 2); } const int maxk = 17; const int maxn = 1 << 16 | 5; int fac[maxk], ifac[maxk], inv[maxk]; void init(int N) { fac[0] = 1; for (int i = 1; i <= N; i++) fac[i] = mul(fac[i - 1], i); ifac[N] = getinv(fac[N]); for (int i = N; i >= 1; i--) ifac[i - 1] = mul(ifac[i], i); inv[0] = inv[1] = 1; for (int i = 2; i <= N; i++) inv[i] = mul(inv[mod % i], mod - mod / i); } int n, K, c; map<vector<int>, int> Map; void getln(int *A) { static int B[maxk]; B[0] = 0; for (int i = 1; i <= K; i++) { int tmp = 0; for (int j = 1; j < i; j++) tmp = add(tmp, mul(j, mul(B[j], A[i - j]))); B[i] = sub(A[i], mul(tmp, inv[i])); } for (int i = 0; i <= K; i++) A[i] = B[i]; } void getexp(int *A) { static int B[maxk]; B[0] = 1; for (int i = 1; i <= K; i++) { int tmp = 0; for (int j = 0; j < i; j++) tmp = add(tmp, mul(mul(A[i - j], i - j), B[j])); B[i] = mul(tmp, inv[i]); } for (int i = 0; i <= K; i++) A[i] = B[i]; } int popcnt[maxn], A[maxn]; vector<int> num[205]; int cnt[205], sum[maxn << 1], tot; int st[205], top; int Ln[maxn][maxk]; int main() { scanf( %d%d%d , &n, &K, &c), init(K); int all = 0; for (int i = 1, x; i <= n; i++) { scanf( %d , &x), all ^= x; vector<int> A; for (int j = 1; j <= K; j++) A.push_back(x ^ (x - j)); Map[A]++; } for (auto u : Map) num[++tot] = u.first, cnt[tot] = u.second; int S = (1 << K) - 1; for (int i = 0; i <= S; i++) { static int f[maxk]; f[0] = 1; for (int j = 0; j < K; j++) f[j + 1] = ((i >> j) & 1) ? mod - ifac[j + 1] : ifac[j + 1]; getln(f); for (int j = 0; j <= K; j++) Ln[i][j] = f[j]; } S = (1 << c) - 1; for (int i = 1; i <= S; i++) popcnt[i] = popcnt[i >> 1] + (i & 1); for (int i = 0; i <= S; i++) { for (int j = 1; j <= tot; j++) { int sta = 0; for (int k = 0; k < K; k++) if (popcnt[i & num[j][k]] & 1) sta |= (1 << k); if (!sum[sta]) st[++top] = sta; sum[sta] += cnt[j]; } static int f[maxk], g[maxk], h[maxk]; for (int j = 0; j <= K; j++) f[j] = h[j] = 0; f[0] = 1; for (int j = 1; j <= top; j++) { int sta = st[j]; for (int k = 0; k <= K; k++) g[k] = mul(Ln[sta][k], sum[sta]); getexp(g); for (int k = 0; k <= K; k++) for (int l = 0; k + l <= K; l++) h[k + l] = add(h[k + l], mul(f[k], g[l])); for (int k = 0; k <= K; k++) f[k] = h[k], h[k] = 0; sum[sta] = 0; } top = 0; A[i] = mul(f[K], fac[K]); } int N = 1 << c; for (int l = 2; l <= N; l <<= 1) { int m = (l >> 1); for (int j = 0; j < N; j += l) for (int i = j; i < j + m; i++) { int u = A[i], v = A[i + m]; A[i] = add(u, v); A[i + m] = sub(u, v); } } int tmp = getinv(mul(N, quick_pow(n, K))); for (int i = 0; i < N; i++) printf( %d , mul(A[i ^ all], tmp)); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, t; int data[105][3]; bitset<50> mark; set<pair<long long, long long> > ss; struct Node { pair<long long, long long> g; void reset() { g.first = g.second = 0; } void set(int x) { if (x < 50) g.first |= 1ll << x; else g.second |= 1ll << (x - 50); } void reset(int x) { if (x < 50) g.first &= (-1ll) ^ (1ll << x); else g.second |= (-1ll) ^ (1ll << (x - 50)); } bool test(int x) { if (x < 50) return (g.first & (1ll << x)); else return (g.second & (1ll << (x - 50))); } int key; friend bool operator<(const Node &a, const Node &b) { return a.key > b.key; } } tmp; priority_queue<Node> que; int main() { scanf( %d%d%d , &n, &m, &t); for (int i = 0; i < m; i++) scanf( %d%d%d , &data[i][0], &data[i][1], &data[i][2]); tmp.reset(); tmp.key = 0; que.push(tmp); int ans, tt = 0; while (t--) { if (que.empty()) { ans = -1; break; } tmp = que.top(); que.pop(); ans = tmp.key; mark.reset(); for (int i = 0; i < m; i++) if (tmp.test(i)) { mark.set(data[i][0]), mark.set(data[i][1] + n); } for (int i = 0; i < m; i++) if (!mark.test(data[i][0]) && !mark.test(data[i][1] + n)) { tmp.set(i); tmp.key += data[i][2]; if (ss.find(tmp.g) == ss.end()) { ss.insert(tmp.g); que.push(tmp); } tmp.key -= data[i][2]; tmp.reset(i); } } printf( %d n , ans); return 0; } |
module hdu(
d_raddr1, d_raddr2, d_addrselector, d_jr_or_exec, d_immonly, e_isLoad, e_wreg,
//nop_alu_stall, nop_lw_stall, nop_sw_stall, // this doesn't seem to be required for this
pc_stall, ifid_stall
);
// d_addrselector is lhb_llb_regcon, it gives addr fof [11:8] in raddr2 when 1 OR [7:4] in raddr2 when 0
// jal or exec is jal || exec
// ! (jal || exec) will indicate sw instruction
// d_immonly is 1 for instructions which only use immediates or offsets and don't need to be stalled
input [3:0] d_raddr1;
input [3:0] d_raddr2;
input d_addrselector;
input d_jr_or_exec;
input d_immonly;
input e_isLoad;
input e_wreg;
output pc_stall;
output ifid_stall;
reg pc_stall_temp;
reg ifid_stall_temp;
reg [1:0] stallCount;
always @ (*)
begin
stallCount = (e_isLoad===1'b1 && d_immonly!==1'b1 && (
(d_addrselector===1'b1 && d_jr_or_exec!==1'b1 && (d_raddr1===e_wreg || d_raddr2===e_wreg)) ||//Check if instr in d is sw and whether it needs a stall
(d_addrselector===1'b1 && d_jr_or_exec===1'b1 && (d_raddr2===e_wreg)) || // JR or exec
(d_addrselector!==1'b1 && (d_raddr1===e_wreg || d_raddr2===e_wreg))
)) ? 2'b111 : stallCount;
if(stallCount>3'b00) begin
pc_stall_temp = 1'b1;
ifid_stall_temp = 1'b1;
stallCount = stallCount-1'b1;
end
else begin
pc_stall_temp = 1'b0;
ifid_stall_temp = 1'b0;
end
end
assign pc_stall = pc_stall_temp;
assign ifid_stall = ifid_stall_temp;
/// NOP also has to sent through the whole pipeline 3 times
endmodule |
//==================================================================================================
// Filename : memory.v
// Created On : 2014-09-28 20:35:52
// Last Modified : 2015-05-31 21:18:35
// Revision :
// Author : Angel Terrones
// Company : Universidad Simón Bolívar
// Email :
//
// Description : Dual-port memory
//==================================================================================================
`include "musb_defines.v"
module memory#(
parameter addr_size = 8 // Default: 256 words/1 KB
)(
input clk,
input rst,
//port A
input [addr_size-1:0] a_addr, // Address
input [31:0] a_din, // Data input
input [3:0] a_wr, // Write/Read
input a_enable, // Valid operation
output reg [31:0] a_dout, // Data output
output reg a_ready, // Data output ready (valid)
// port B
input [addr_size-1:0] b_addr, // Address
input [31:0] b_din, // Data input
input [3:0] b_wr, // Write/Read
input b_enable, // Valid operation
output reg [31:0] b_dout, // Data output
output reg b_ready // Data output ready (valid)
);
//--------------------------------------------------------------------------
// Signal Declaration: reg
//--------------------------------------------------------------------------
reg [31:0] a_data_out;
reg [31:0] b_data_out;
//--------------------------------------------------------------------------
// Set the ready signal
//--------------------------------------------------------------------------
always @(posedge clk) begin
a_ready <= (rst) ? 1'b0 : a_enable;
b_ready <= (rst) ? 1'b0 : b_enable;
end
//--------------------------------------------------------------------------
// assigment
//--------------------------------------------------------------------------
always @(*) begin
a_dout <= (a_ready) ? a_data_out : 32'bz;
b_dout <= (b_ready) ? b_data_out : 32'bz;
end
//--------------------------------------------------------------------------
// inicializar memoria
//--------------------------------------------------------------------------
reg [31:0] mem [0:(2**addr_size)-1];
initial begin
$readmemh("mem.hex", mem);
end
//--------------------------------------------------------------------------
// Port A
//--------------------------------------------------------------------------
always @(posedge clk) begin
a_data_out <= mem[a_addr];
if(a_wr) begin
a_data_out <= a_din;
mem[a_addr][7:0] <= (a_wr[0] & a_enable) ? a_din[7:0] : mem[a_addr][7:0];
mem[a_addr][15:8] <= (a_wr[1] & a_enable) ? a_din[15:8] : mem[a_addr][15:8];
mem[a_addr][23:16] <= (a_wr[2] & a_enable) ? a_din[23:16] : mem[a_addr][23:16];
mem[a_addr][31:24] <= (a_wr[3] & a_enable) ? a_din[31:24] : mem[a_addr][31:24];
end
end
//--------------------------------------------------------------------------
// Port B
//--------------------------------------------------------------------------
always @(posedge clk) begin
b_data_out <= mem[b_addr];
if(b_wr) begin
b_data_out <= b_din;
mem[b_addr][7:0] <= (b_wr[0] & b_enable) ? b_din[7:0] : mem[b_addr][7:0];
mem[b_addr][15:8] <= (b_wr[1] & b_enable) ? b_din[15:8] : mem[b_addr][15:8];
mem[b_addr][23:16] <= (b_wr[2] & b_enable) ? b_din[23:16] : mem[b_addr][23:16];
mem[b_addr][31:24] <= (b_wr[3] & b_enable) ? b_din[31:24] : mem[b_addr][31:24];
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// d_KES_PE_DC_2MAXodr.v for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Jinwoo Jeong <>
// Ilyong Jung <>
// Yong Ho Song <>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Jinwoo Jeong <>
// Ilyong Jung <>
//
// Project Name: Cosmos OpenSSD
// Design Name: BCH Page Decoder
// Module Name: d_KES_PE_DC_2MAXodr
// File Name: d_KES_PE_DC_2MAXodr.v
//
// Version: v1.1.1-256B_T14
//
// Description:
// - Processing Element: Discrepancy Computation module, 2 max orders
// - for binary version of inversion-less Berlekamp-Massey algorithm (iBM.b)
// - for data area
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.1.1
// - minor modification for releasing
//
// * v1.1.0
// - change state machine: divide states
// - insert additional registers
// - improve frequency characteristic
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`include "d_KES_parameters.vh"
`timescale 1ns / 1ps
module d_KES_PE_DC_2MAXodr // discrepancy computation module: 2 max orders
(
input wire i_clk,
input wire i_RESET_KES,
input wire i_stop_dec,
input wire i_EXECUTE_PE_DC,
input wire [`D_KES_GF_ORDER-1:0] i_S_in,
input wire [`D_KES_GF_ORDER-1:0] i_v_2i_X,
//output wire [`D_KES_GF_ORDER-1:0] o_S_out,
output wire [`D_KES_GF_ORDER-1:0] o_coef_2ip1
);
parameter [11:0] D_KES_VALUE_ZERO = 12'b0000_0000_0000;
parameter [11:0] D_KES_VALUE_ONE = 12'b0000_0000_0001;
// FSM parameters
parameter PE_DC_RST = 2'b01; // reset
parameter PE_DC_INP = 2'b10; // input capture
// variable declaration
reg [1:0] r_cur_state;
reg [1:0] r_nxt_state;
reg [`D_KES_GF_ORDER-1:0] r_S_in_b;
reg [`D_KES_GF_ORDER-1:0] r_v_2i_X_b;
wire [`D_KES_GF_ORDER-1:0] w_coef_term;
// update current state to next state
always @ (posedge i_clk)
begin
if ((i_RESET_KES) || (i_stop_dec)) begin
r_cur_state <= PE_DC_RST;
end else begin
r_cur_state <= r_nxt_state;
end
end
// decide next state
always @ ( * )
begin
case (r_cur_state)
PE_DC_RST: begin
r_nxt_state <= (i_EXECUTE_PE_DC)? (PE_DC_INP):(PE_DC_RST);
end
PE_DC_INP: begin
r_nxt_state <= PE_DC_RST;
end
default: begin
r_nxt_state <= PE_DC_RST;
end
endcase
end
// state behaviour
always @ (posedge i_clk)
begin
if ((i_RESET_KES) || (i_stop_dec)) begin // initializing
r_S_in_b <= 0;
r_v_2i_X_b <= 0;
end
else begin
case (r_nxt_state)
PE_DC_RST: begin // hold original data
r_S_in_b <= r_S_in_b;
r_v_2i_X_b <= r_v_2i_X_b;
end
PE_DC_INP: begin // input capture only
r_S_in_b <= i_S_in;
r_v_2i_X_b <= i_v_2i_X;
end
default: begin
r_S_in_b <= r_S_in_b;
r_v_2i_X_b <= r_v_2i_X_b;
end
endcase
end
end
d_parallel_FFM_gate_GF12 d_S_in_FFM_v_2i_X (
.i_poly_form_A (r_S_in_b[`D_KES_GF_ORDER-1:0]),
.i_poly_form_B (r_v_2i_X_b[`D_KES_GF_ORDER-1:0]),
.o_poly_form_result(w_coef_term[`D_KES_GF_ORDER-1:0]));
//assign o_S_out[`D_KES_GF_ORDER-1:0] = r_S_in_b[`D_KES_GF_ORDER-1:0];
assign o_coef_2ip1 = w_coef_term;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 105; const int mod = 1e9 + 7; inline void MOD(int &x) { if (x >= mod) x -= mod; } int n, m, k; int dp[2][N][N][N], C[N][N], r; int ans; int main() { for (int i = 0; i <= 100; i++) { C[i][0] = 1; for (int j = 1; j <= i; j++) C[i][j] = min(C[i - 1][j - 1] + C[i - 1][j], 101); } scanf( %d%d%d , &n, &m, &k); r = 0; for (int j = 2; j <= n + 1; j++) dp[r][j][j - 1][1] = 1; for (int i = 1; i <= m; i++) { for (int j = 1 + i; j <= n + 1; j++) for (int q = 1; q <= k; q++) ans = ((long long)dp[r][j][0][q] * (m - i + 1) + ans) % (long long)mod, dp[r][j][0][q] = 0; if (i == m) break; for (int j = 1 + i; j <= n + 1; j++) for (int p = 1; p < j; p++) for (int q = 1; q <= k; q++) if (dp[r][j][p][q]) { for (int t = p; j + t <= n + 1 && q * C[t - 1][p - 1] <= k; t++) MOD(dp[r ^ 1][j + t][t - p][q * C[t - 1][p - 1]] += dp[r][j][p][q]); dp[r][j][p][q] = 0; } r ^= 1; } printf( %d n , ans); return 0; } |
/*
*
* Copyright 2015, Stephen A. Rodgers. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*
*/
`default_nettype none
/*
* Arbitrary width synchronous up/down counter
*/
module counter (rstn, clk, up, down, count);
// Default parameter. This can be overrriden
parameter WIDTH = 8;
input rstn;
input clk;
input up;
input down;
output [WIDTH-1:0] count;
reg[WIDTH-1:0] count_int = 0;
assign count = count_int;
always @ (posedge clk or negedge rstn) begin
if(rstn == 0) begin
count_int <= 0;
end else begin
if(up == 1) begin
count_int <= count_int + 1'b1;
end else if(down == 1) begin
count_int <= count_int - 1'b1;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__BUF_BLACKBOX_V
`define SKY130_FD_SC_MS__BUF_BLACKBOX_V
/**
* buf: Buffer.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__buf (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__BUF_BLACKBOX_V
|
//
// timing.v -- timing generator
//
module timing(clk, pixclk,
txtrow, txtcol,
chrrow, chrcol,
blank, hsync, vsync, blink);
input clk;
output pixclk;
output [4:0] txtrow;
output [6:0] txtcol;
output [3:0] chrrow;
output [2:0] chrcol;
output blank;
output hsync;
output vsync;
output reg blink;
reg pclk;
reg [9:0] hcnt;
reg hblank, hsynch;
reg [9:0] vcnt;
reg vblank, vsynch;
reg [5:0] bcnt;
always @(posedge clk) begin
pclk <= ~pclk;
end
assign pixclk = pclk;
always @(posedge clk) begin
if (pclk == 1) begin
if (hcnt == 10'd799) begin
hcnt <= 10'd0;
hblank <= 1;
end else begin
hcnt <= hcnt + 1;
end
if (hcnt == 10'd639) begin
hblank <= 0;
end
if (hcnt == 10'd655) begin
hsynch <= 0;
end
if (hcnt == 10'd751) begin
hsynch <= 1;
end
end
end
always @(posedge clk) begin
if (pclk == 1 && hcnt == 10'd799) begin
if (vcnt == 10'd524) begin
vcnt <= 10'd0;
vblank <= 1;
end else begin
vcnt <= vcnt + 1;
end
if (vcnt == 10'd479) begin
vblank <= 0;
end
if (vcnt == 10'd489) begin
vsynch <= 0;
end
if (vcnt == 10'd491) begin
vsynch <= 1;
end
end
end
always @(posedge clk) begin
if (pclk == 1 && hcnt == 10'd799 && vcnt == 10'd524) begin
if (bcnt == 6'd59) begin
bcnt <= 6'd0;
blink <= 1;
end else begin
bcnt <= bcnt + 1;
end
if (bcnt == 6'd29) begin
blink <= 0;
end
end
end
assign blank = hblank & vblank;
assign hsync = hsynch;
assign vsync = vsynch;
assign txtrow[4:0] = vcnt[8:4];
assign txtcol[6:0] = hcnt[9:3];
assign chrrow[3:0] = vcnt[3:0];
assign chrcol[2:0] = hcnt[2:0];
endmodule
|
/*
* Copyright 2018-2022 F4PGA Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
// UART transmitter.
module UART_TX(
input rst, clk, baud_edge, data_ready,
input [7:0] data,
output reg tx, data_accepted
);
localparam START = (1 << 0), DATA = (1 << 1), END = (1 << 2);
reg [7:0] data_reg;
reg [2:0] data_counter;
reg [3:0] state;
initial begin
tx <= 1;
data_accepted <= 0;
end
always @(posedge clk) begin
if(rst) begin
state <= END;
tx <= 1;
data_accepted <= 0;
end else if(baud_edge) begin
case(state)
START: begin
tx <= 0;
data_counter <= 0;
state <= DATA;
end
DATA: begin
tx <= data_reg[data_counter];
if(data_counter != 7) begin
data_counter <= data_counter + 1;
end else begin
state <= END;
data_counter <= 0;
end
end
END: begin
tx <= 1;
if(data_ready) begin
data_accepted <= 1;
data_reg <= data;
state <= START;
end
end
default: begin
tx <= 1;
state <= END;
end
endcase
end else begin
data_accepted <= 0;
end
end
endmodule
|
module var21_multi (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, S, T, U, valid);
input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, S, T, U;
output valid;
wire [8:0] min_value = 9'd120;
wire [8:0] max_weight = 9'd60;
wire [8:0] max_volume = 9'd60;
wire [8:0] total_value =
A * 9'd4
+ B * 9'd8
+ C * 9'd0
+ D * 9'd20
+ E * 9'd10
+ F * 9'd12
+ G * 9'd18
+ H * 9'd14
+ I * 9'd6
+ J * 9'd15
+ K * 9'd30
+ L * 9'd8
+ M * 9'd16
+ N * 9'd18
+ O * 9'd18
+ P * 9'd14
+ Q * 9'd7
+ R * 9'd7
+ S * 9'd29
+ T * 9'd23
+ U * 9'd24;
wire [8:0] total_weight =
A * 9'd28
+ B * 9'd8
+ C * 9'd27
+ D * 9'd18
+ E * 9'd27
+ F * 9'd28
+ G * 9'd6
+ H * 9'd1
+ I * 9'd20
+ J * 9'd0
+ K * 9'd5
+ L * 9'd13
+ M * 9'd8
+ N * 9'd14
+ O * 9'd22
+ P * 9'd12
+ Q * 9'd23
+ R * 9'd26
+ S * 9'd1
+ T * 9'd22
+ U * 9'd26;
wire [8:0] total_volume =
A * 9'd27
+ B * 9'd27
+ C * 9'd4
+ D * 9'd4
+ E * 9'd0
+ F * 9'd24
+ G * 9'd4
+ H * 9'd20
+ I * 9'd12
+ J * 9'd15
+ K * 9'd5
+ L * 9'd2
+ M * 9'd9
+ N * 9'd28
+ O * 9'd19
+ P * 9'd18
+ Q * 9'd30
+ R * 9'd12
+ S * 9'd28
+ T * 9'd13
+ U * 9'd18;
assign valid = ((total_value >= min_value) && (total_weight <= max_weight) && (total_volume <= max_volume));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_DLATCH_LP_SYMBOL_V
`define SKY130_FD_SC_HD__UDP_DLATCH_LP_SYMBOL_V
/**
* udp_dlatch$lP: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__udp_dlatch$lP (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_DLATCH_LP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); int n, m; cin >> n >> m; vector<vector<long long> > PRE(32, vector<long long>(n + 2, 0)), ZEROS(32, vector<long long>(n + 2, 0)); vector<long long> L(m), R(m), Q(m); for (int i = 0; i < m; ++i) { cin >> L[i] >> R[i] >> Q[i]; for (int j = 0; j < 32; ++j) { int ind = 1 << j; if (ind & Q[i]) { PRE[j][L[i]]++; PRE[j][R[i] + 1]--; } } } for (int i = 0; i < 32; ++i) { for (int j = 1; j < n + 2; ++j) { PRE[i][j] += PRE[i][j - 1]; if (PRE[i][j] == 0) ZEROS[i][j]++; ZEROS[i][j] += ZEROS[i][j - 1]; } } for (int i = 0; i < m; ++i) { int l = L[i], r = R[i], q = Q[i]; for (int j = 0; j < 32; ++j) { int ind = 1 << j; if (!(ind & q) && ZEROS[j][r] - ZEROS[j][l - 1] == 0) { cout << NO n ; return 0; } } } cout << YES n ; for (int i = 1; i <= n; ++i) { if (i != 1) cout << ; int aux = 0; for (int j = 0; j < 32; ++j) { int ind = 1 << j; if (PRE[j][i]) { aux |= ind; } } cout << aux; } cout << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int a[3]; int x[3]; int last = 0; cin >> a[0] >> a[1] >> a[2]; cin >> x[0] >> x[1] >> x[2]; for (int i = 0; i < 3; ++i) { int t = a[i] - x[i]; if (t > 0) t /= 2; last += t; } if (last < 0) cout << No n ; else cout << Yes n ; return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build Mon Oct 10 19:07:27 MDT 2016
// Date : Mon Sep 18 12:31:45 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub
// C:/Projects/srio_test/srio_test/srio_test.srcs/sources_1/ip/srio_gen2_0/srio_gen2_0_stub.v
// Design : srio_gen2_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "srio_gen2_v4_0_5,Vivado 2015.1.0" *)
module srio_gen2_0(sys_clkp, sys_clkn, sys_rst, log_clk_out,
phy_clk_out, gt_clk_out, gt_pcs_clk_out, drpclk_out, refclk_out, clk_lock_out, cfg_rst_out,
log_rst_out, buf_rst_out, phy_rst_out, gt_pcs_rst_out, gt0_qpll_clk_out,
gt0_qpll_out_refclk_out, srio_rxn0, srio_rxp0, srio_txn0, srio_txp0, s_axis_iotx_tvalid,
s_axis_iotx_tready, s_axis_iotx_tlast, s_axis_iotx_tdata, s_axis_iotx_tkeep,
s_axis_iotx_tuser, m_axis_iorx_tvalid, m_axis_iorx_tready, m_axis_iorx_tlast,
m_axis_iorx_tdata, m_axis_iorx_tkeep, m_axis_iorx_tuser, s_axi_maintr_rst,
s_axi_maintr_awvalid, s_axi_maintr_awready, s_axi_maintr_awaddr, s_axi_maintr_wvalid,
s_axi_maintr_wready, s_axi_maintr_wdata, s_axi_maintr_bvalid, s_axi_maintr_bready,
s_axi_maintr_bresp, s_axi_maintr_arvalid, s_axi_maintr_arready, s_axi_maintr_araddr,
s_axi_maintr_rvalid, s_axi_maintr_rready, s_axi_maintr_rdata, s_axi_maintr_rresp,
sim_train_en, force_reinit, phy_mce, phy_link_reset, phy_rcvd_mce, phy_rcvd_link_reset,
phy_debug, gtrx_disperr_or, gtrx_notintable_or, port_error, port_timeout, srio_host,
port_decode_error, deviceid, idle2_selected, phy_lcl_master_enable_out,
buf_lcl_response_only_out, buf_lcl_tx_flow_control_out, buf_lcl_phy_buf_stat_out,
phy_lcl_phy_next_fm_out, phy_lcl_phy_last_ack_out, phy_lcl_phy_rewind_out,
phy_lcl_phy_rcvd_buf_stat_out, phy_lcl_maint_only_out, port_initialized,
link_initialized, idle_selected, mode_1x)
/* synthesis syn_black_box black_box_pad_pin="sys_clkp,sys_clkn,sys_rst,log_clk_out,phy_clk_out,gt_clk_out,gt_pcs_clk_out,drpclk_out,refclk_out,clk_lock_out,cfg_rst_out,log_rst_out,buf_rst_out,phy_rst_out,gt_pcs_rst_out,gt0_qpll_clk_out,gt0_qpll_out_refclk_out,srio_rxn0,srio_rxp0,srio_txn0,srio_txp0,s_axis_iotx_tvalid,s_axis_iotx_tready,s_axis_iotx_tlast,s_axis_iotx_tdata[63:0],s_axis_iotx_tkeep[7:0],s_axis_iotx_tuser[31:0],m_axis_iorx_tvalid,m_axis_iorx_tready,m_axis_iorx_tlast,m_axis_iorx_tdata[63:0],m_axis_iorx_tkeep[7:0],m_axis_iorx_tuser[31:0],s_axi_maintr_rst,s_axi_maintr_awvalid,s_axi_maintr_awready,s_axi_maintr_awaddr[31:0],s_axi_maintr_wvalid,s_axi_maintr_wready,s_axi_maintr_wdata[31:0],s_axi_maintr_bvalid,s_axi_maintr_bready,s_axi_maintr_bresp[1:0],s_axi_maintr_arvalid,s_axi_maintr_arready,s_axi_maintr_araddr[31:0],s_axi_maintr_rvalid,s_axi_maintr_rready,s_axi_maintr_rdata[31:0],s_axi_maintr_rresp[1:0],sim_train_en,force_reinit,phy_mce,phy_link_reset,phy_rcvd_mce,phy_rcvd_link_reset,phy_debug[223:0],gtrx_disperr_or,gtrx_notintable_or,port_error,port_timeout[23:0],srio_host,port_decode_error,deviceid[15:0],idle2_selected,phy_lcl_master_enable_out,buf_lcl_response_only_out,buf_lcl_tx_flow_control_out,buf_lcl_phy_buf_stat_out[5:0],phy_lcl_phy_next_fm_out[5:0],phy_lcl_phy_last_ack_out[5:0],phy_lcl_phy_rewind_out,phy_lcl_phy_rcvd_buf_stat_out[5:0],phy_lcl_maint_only_out,port_initialized,link_initialized,idle_selected,mode_1x" */;
input sys_clkp;
input sys_clkn;
input sys_rst;
output log_clk_out;
output phy_clk_out;
output gt_clk_out;
output gt_pcs_clk_out;
output drpclk_out;
output refclk_out;
output clk_lock_out;
output cfg_rst_out;
output log_rst_out;
output buf_rst_out;
output phy_rst_out;
output gt_pcs_rst_out;
output gt0_qpll_clk_out;
output gt0_qpll_out_refclk_out;
input srio_rxn0;
input srio_rxp0;
output srio_txn0;
output srio_txp0;
input s_axis_iotx_tvalid;
output s_axis_iotx_tready;
input s_axis_iotx_tlast;
input [63:0]s_axis_iotx_tdata;
input [7:0]s_axis_iotx_tkeep;
input [31:0]s_axis_iotx_tuser;
output m_axis_iorx_tvalid;
input m_axis_iorx_tready;
output m_axis_iorx_tlast;
output [63:0]m_axis_iorx_tdata;
output [7:0]m_axis_iorx_tkeep;
output [31:0]m_axis_iorx_tuser;
input s_axi_maintr_rst;
input s_axi_maintr_awvalid;
output s_axi_maintr_awready;
input [31:0]s_axi_maintr_awaddr;
input s_axi_maintr_wvalid;
output s_axi_maintr_wready;
input [31:0]s_axi_maintr_wdata;
output s_axi_maintr_bvalid;
input s_axi_maintr_bready;
output [1:0]s_axi_maintr_bresp;
input s_axi_maintr_arvalid;
output s_axi_maintr_arready;
input [31:0]s_axi_maintr_araddr;
output s_axi_maintr_rvalid;
input s_axi_maintr_rready;
output [31:0]s_axi_maintr_rdata;
output [1:0]s_axi_maintr_rresp;
input sim_train_en;
input force_reinit;
input phy_mce;
input phy_link_reset;
output phy_rcvd_mce;
output phy_rcvd_link_reset;
output [223:0]phy_debug;
output gtrx_disperr_or;
output gtrx_notintable_or;
output port_error;
output [23:0]port_timeout;
output srio_host;
output port_decode_error;
output [15:0]deviceid;
output idle2_selected;
output phy_lcl_master_enable_out;
output buf_lcl_response_only_out;
output buf_lcl_tx_flow_control_out;
output [5:0]buf_lcl_phy_buf_stat_out;
output [5:0]phy_lcl_phy_next_fm_out;
output [5:0]phy_lcl_phy_last_ack_out;
output phy_lcl_phy_rewind_out;
output [5:0]phy_lcl_phy_rcvd_buf_stat_out;
output phy_lcl_maint_only_out;
output port_initialized;
output link_initialized;
output idle_selected;
output mode_1x;
endmodule
|
//--------------------------------------------------------------------------------
// Project : SWITCH
// File : eth_rcr_unpack.v
// Version : 0.2
// Author : Shreejith S
//
// Description: Ethernet Rx Module Unpacker
//
//--------------------------------------------------------------------------------
module eth_rcr_unpack #(parameter unpack_dst_addr = 48'hAABBCCDDEEFF)(
//from ethernet client fifo
input i_axi_rx_clk,
input i_axi_rx_rst_n,
input i_rx_axis_fifo_tvalid,
input [7:0] i_rx_axis_fifo_tdata,
input i_rx_axis_fifo_tlast,
output o_rx_axis_fifo_tready,
//to the user
output o_axi_rx_clk,
output o_axi_rx_rst_n,
output reg [7:0] o_axi_rx_tdata,
output reg o_axi_rx_data_tvalid,
input i_axi_rx_data_tready,
output reg o_axi_rx_data_tlast,
input loop_back
);
assign o_axi_rx_clk = i_axi_rx_clk;
assign o_axi_rx_rst_n = i_axi_rx_rst_n;
assign o_rx_axis_fifo_tready = i_axi_rx_data_tready;
reg [3:0] pkt_len_cntr;
reg [7:0] dest_addr [5:0];
reg [47:0] destination_addr;
reg state;
reg no_filter;
parameter idle = 1'b0,
stream_pkt = 1'b1;
always @(posedge i_axi_rx_clk)
begin
if(~i_axi_rx_rst_n)
begin
o_axi_rx_data_tvalid <= 1'b0;
state <= idle;
pkt_len_cntr <= 4'd0;
o_axi_rx_tdata <= 8'd0;
no_filter <= 1'b0;
dest_addr[0] <= 8'd0;
dest_addr[1] <= 8'd0;
dest_addr[2] <= 8'd0;
dest_addr[3] <= 8'd0;
dest_addr[4] <= 8'd0;
dest_addr[5] <= 8'd0;
end
else
begin
case(state)
idle:begin
o_axi_rx_data_tvalid <= 1'b0;
o_axi_rx_data_tlast <= 1'b0;
if(i_rx_axis_fifo_tvalid & i_axi_rx_data_tready) //valid data transaction
begin
pkt_len_cntr <= pkt_len_cntr+1'b1; //count the size of the pkt.
if(pkt_len_cntr == 'd13) //ethernet header is 14 bytes
begin
if (((~loop_back) && (destination_addr == unpack_dst_addr)) || loop_back)
no_filter <= 1'b1;
else
no_filter <= 1'b0;
pkt_len_cntr <= 0;
state <= stream_pkt;
end
if(pkt_len_cntr < 'd6)
dest_addr[pkt_len_cntr] <= i_rx_axis_fifo_tdata; //store the destination address for filtering
end
end
stream_pkt:begin
o_axi_rx_data_tvalid <= i_rx_axis_fifo_tvalid & no_filter;
o_axi_rx_tdata <= i_rx_axis_fifo_tdata;
o_axi_rx_data_tlast <= i_rx_axis_fifo_tlast & no_filter;
if(i_rx_axis_fifo_tlast)
begin
state <= idle;
end
end
endcase
end
end
always @(posedge i_axi_rx_clk)
begin
destination_addr <= {dest_addr[0],dest_addr[1],dest_addr[2],dest_addr[3],dest_addr[4],dest_addr[5]};
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.20131013
// \ \ Application: netgen
// / / Filename: gsu_umult.v
// /___/ /\ Timestamp: Thu Jun 07 01:13:23 2018
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog D:/prj/sd2snes/verilog/sd2snes_gsu/ipcore_dir/tmp/_cg/gsu_umult.ngc D:/prj/sd2snes/verilog/sd2snes_gsu/ipcore_dir/tmp/_cg/gsu_umult.v
// Device : 3s400pq208-4
// Input file : D:/prj/sd2snes/verilog/sd2snes_gsu/ipcore_dir/tmp/_cg/gsu_umult.ngc
// Output file : D:/prj/sd2snes/verilog/sd2snes_gsu/ipcore_dir/tmp/_cg/gsu_umult.v
// # of Modules : 1
// Design Name : gsu_umult
// Xilinx : E:\Xilinx\14.7\ISE_DS\ISE\
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module gsu_umult (
p, a, b
)/* synthesis syn_black_box syn_noprune=1 */;
output [15 : 0] p;
input [7 : 0] a;
input [7 : 0] b;
// synthesis translate_off
wire \blk00000001/sig00000011 ;
wire \NLW_blk00000001/blk00000003_P<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<16>_UNCONNECTED ;
MULT18X18 \blk00000001/blk00000003 (
.A({\blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 ,
\blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , a[7], a[6],
a[5], a[4], a[3], a[2], a[1], a[0]}),
.B({\blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 ,
\blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , b[7], b[6],
b[5], b[4], b[3], b[2], b[1], b[0]}),
.P({\NLW_blk00000001/blk00000003_P<35>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<34>_UNCONNECTED ,
\NLW_blk00000001/blk00000003_P<33>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<32>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<31>_UNCONNECTED ,
\NLW_blk00000001/blk00000003_P<30>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<29>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000003_P<27>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<26>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<25>_UNCONNECTED ,
\NLW_blk00000001/blk00000003_P<24>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<23>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000003_P<21>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<20>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<19>_UNCONNECTED ,
\NLW_blk00000001/blk00000003_P<18>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<17>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<16>_UNCONNECTED ,
p[15], p[14], p[13], p[12], p[11], p[10], p[9], p[8], p[7], p[6], p[5], p[4], p[3], p[2], p[1], p[0]})
);
GND \blk00000001/blk00000002 (
.G(\blk00000001/sig00000011 )
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
#include <bits/stdc++.h> using namespace std; const int MAXW = 1000000; const int INF = 0x3f3f3f3f; const int MOD = 1000000007; const char test[] = test n ; int in(); int tr[100010]; int ls[100010]; int n, m, k; int hav[100010]; int lowbit(int x) { return (-x) & x; } void updata(int in, int val) { while (in <= n) { if (val > tr[in]) { tr[in] = val; } in += lowbit(in); } } int ask(int to) { int mx = 0; while (to) { mx = max(mx, tr[to]); to -= lowbit(to); } return mx; } int main() { cin >> n >> m; hav[1]++; hav[m + 1]--; for (int i = 0; i < n; ++i) { int u, v; cin >> u >> v; hav[u]++; hav[v + 1]--; } for (int i = 1; i <= m; ++i) { hav[i] += hav[i - 1]; int val = ask(hav[i]) + 1; updata(hav[i], val); ls[i] = val; } memset(tr, 0, sizeof tr); int ans = 0; for (int i = m; i > 0; --i) { int val = ask(hav[i]) + 1; updata(hav[i], val); ans = max(ans, ls[i] + val - 1); } cout << ans; return 0; } int in() { int input; scanf( %d , &input); return input; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__BUFBUF_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__BUFBUF_BEHAVIORAL_V
/**
* bufbuf: Double buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__bufbuf (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__BUFBUF_BEHAVIORAL_V |
#include <bits/stdc++.h> std::priority_queue<std::pair<long long, int> > que; long long dis[2005]; int w[2005][2005]; int main() { int n, mn = 1e9; scanf( %d , &n); for (int i = 0; i < n - 1; i++) { for (int j = 1; j < n - i; j++) { int x; scanf( %d , &x); w[i][i + j] = w[i + j][i] = x; mn = std::min(mn, x); } } for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (i != j) w[i][j] -= mn; } } for (int i = 0; i < n; i++) { dis[i] = 1e18; for (int j = 0; j < n; j++) { if (i != j) dis[i] = std::min(dis[i], (long long)w[i][j] << 1); } que.push(std::make_pair(-dis[i], i)); } while (!que.empty()) { long long d = -que.top().first; int u = que.top().second; que.pop(); if (dis[u] != d) continue; for (int v = 0; v < n; v++) { if (u != v && d + w[u][v] < dis[v]) { dis[v] = d + w[u][v]; que.push(std::make_pair(-dis[v], v)); } } } for (int i = 0; i < n; i++) printf( %lld n , (long long)(n - 1) * mn + dis[i]); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 6e5; const long long mo = 1e9 + 7; const long long inf = 1e9; const long long Inf = 1e18; int lz[N], a[N], ls[N], rs[N], mi[N], mx[N]; bool ok[N]; char s[N]; void f(int x, int l, int r, int y, int z, int L, int R) { if (l == L && r == R && (!z || (L == R))) { if (z) ok[x] ^= 1; lz[x] += y; mi[x] += y; mx[x] += y; ls[x] -= y; rs[x] -= y; return; } int m = (L + R) / 2; if (lz[x]) { lz[x * 2] += lz[x]; mi[x * 2] += lz[x]; mx[x * 2] += lz[x]; ls[x * 2] -= lz[x]; rs[x * 2] -= lz[x]; lz[x * 2 + 1] += lz[x]; mi[x * 2 + 1] += lz[x]; mx[x * 2 + 1] += lz[x]; ls[x * 2 + 1] -= lz[x]; rs[x * 2 + 1] -= lz[x]; lz[x] = 0; } if (r <= m) f(x * 2, l, r, y, z, L, m); else if (l > m) f(x * 2 + 1, l, r, y, z, m + 1, R); else { f(x * 2, l, m, y, z, L, m); f(x * 2 + 1, m + 1, r, y, 0, m + 1, R); } ok[x] = ok[x * 2] | ok[x * 2 + 1]; mi[x] = min(mi[x * 2], mi[x * 2 + 1]); if (!ok[x * 2]) { mx[x] = mx[x * 2 + 1]; ls[x] = ls[x * 2 + 1]; a[x] = a[x * 2 + 1]; rs[x] = max(mx[x * 2 + 1] - mi[x * 2] * 2, rs[x * 2 + 1]); } else if (!ok[x * 2 + 1]) { mx[x] = mx[x * 2]; rs[x] = rs[x * 2]; a[x] = a[x * 2]; ls[x] = max(mx[x * 2] - mi[x * 2 + 1] * 2, ls[x * 2]); } else { mx[x] = max(mx[x * 2], mx[x * 2 + 1]); ls[x] = max(mx[x * 2] - mi[x * 2 + 1] * 2, max(ls[x * 2], ls[x * 2 + 1])); rs[x] = max(mx[x * 2 + 1] - mi[x * 2] * 2, max(rs[x * 2], rs[x * 2 + 1])); a[x] = max(max(ls[x * 2] + mx[x * 2 + 1], mx[x * 2] + rs[x * 2 + 1]), max(a[x * 2], a[x * 2 + 1])); } } int main() { int n, m; scanf( %d%d , &n, &m); scanf( %s , s + 1); f(1, 0, 0, 0, 1, 0, n * 2 - 2); for (int i = (1); i <= (n * 2 - 2); ++i) { if (s[i] == ( ) f(1, i, n * 2 - 2, 1, 1, 0, n * 2 - 2); else f(1, i, n * 2 - 2, -1, 0, 0, n * 2 - 2); } printf( %d n , a[1]); for (int i = (1); i <= (m); ++i) { int l, r; scanf( %d%d , &l, &r); if (l > r) swap(l, r); if (s[l] != s[r]) { if (s[l] == ( ) f(1, l, r - 1, -2, 1, 0, n * 2 - 2); else f(1, l, r - 1, 2, 1, 0, n * 2 - 2); f(1, r, r, 0, 1, 0, n * 2 - 2); swap(s[l], s[r]); } printf( %d n , a[1]); } } |
//Logarithm function evaluation
module log(u0, e, clk);
input [47:0]u0;
input clk;
output [30:0]e;
reg [30:0]e;
reg [7:0]exp_e;
reg [47:0]x_e;
reg [113:0]y_e1, y_e_2, y_e_3, y_e;
reg [65:0]y_e2;
reg [15:0]ln2;
reg [18:0]e_e;
reg [33:0]e_e_, y_e_;
reg [34:0]e0;
reg [16:0]c_e_1;
reg [16:0]c_e_2, c_e_3;
reg [48:0]x_e_;
integer i;
always@(posedge clk)
begin
i = 47; //Leading zero calculation for u0
while(i>=0)
begin
if(u0[i] == 1'b1)
begin
exp_e = 48 - i; //exp_e has the LZD value
i = 0;
end
i = i-1;
end
x_e = x_e&(48'h000000000000);
x_e = u0 << exp_e; //Left shift of u0 based on exp_e
y_e = 0;
//Logarithm function Approximation
c_e_1 = 17'b00011011000001110;
c_e_2 = 17'b10101000111110001;
c_e_3 = 17'b10001101010001101;
x_e_[47:0] = x_e[47:0];
x_e_[48] = 1;
y_e1 = c_e_1*x_e_*x_e_ ;
y_e2 = c_e_2*x_e_ ;
y_e_3[113] = 0;
y_e_2[113:48] = y_e2[65:0];
y_e_2[47:0] = 0;
y_e_3[112:96] = c_e_3[16:0];
y_e_3[95:0] = 0;
y_e = -y_e1 + y_e_2 - y_e_3; // Evalulating the polynomial
ln2 = 16'b1011000101110010;
e_e = exp_e*ln2;
y_e_[33:31] = 0;
y_e_[30:0] = y_e[111:81];
e_e_[33:15] = e_e[18:0];
e_e_[14:0] = 0;
e0 = e_e_ + y_e_;
e[27:0] = e0[34:7];
e[30:28] = 0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; for (int i = 0; i < t; i++) { int n, count = 1; cin >> n; while (n > 0) { if (count % 3 != 0 && count % 10 != 3) { count++; n--; } else { count++; } } int ans = count - 1; cout << ans << endl; } } |
/* Decode Unit Testbench*/
`timescale 1ns / 100ps
`include "../decode_32.v"
module decode_test();
localparam MEM_SIZE = 32;
/* Clocks */
reg clk;
always
#10 clk = ~ clk; //100MHz
/* Input signals to drive */
reg reset;
reg stall;
reg [31:0] insn;
reg [31:0] insn_address;
//integer insn_address;
reg [7:0] sysreg_data_input;
/* Output signals to observe*/
wire [4:0] reg_select;
wire [4:0] rsa;
wire [4:0] rsb;
wire [4:0] rd;
wire [20:0] imm;
wire [3:0] aluop;
wire jlnk;
wire pc_change_relative;
wire pc_change_absolute;
wire mem_read;
wire mem_write;
wire nri_flag;
wire [1:0] branch_funct;
wire stall_output;
wire memsync;
wire syscall;
wire permission_inc;
wire permission_dec;
wire [7:0] sysreg_addr;
wire [7:0] sysreg_data;
wire [31:0] insn_pc_output;
wire [30:0] cp_insn;
/* Memory Test Registers */
reg [31:0] insn_mem [0:MEM_SIZE-1]; //1024 addresses, 2^10
decode_32 decode_ut( //Decode unit under test
.insn_in(insn), //Instruction Input
.reset_in(reset), //Reset line input (active low)
.clk_in(clk), //Clock input
.insn_pc_in(insn_address), //Current instruction PC Address
.stall_in(stall), //CCCP Leader... nah just a stall signal
.reg_select_out(reg_select), //What register bank the instruction wants to access
.rsa_out(rsa), //RSa address
.rsb_out(rsb), //RSb address
.rd_out(rd), //Rd address
.imm_out(imm), //Immediate value (if used)
.aluop_out(aluop), //What operation to tell the ALU to do
.jlnk_out(jlnk), //Saving the PC to $R4/RA?
.pc_change_rel_out(pc_change_relative), //PC Relative address change
.pc_change_abs_out(pc_change_absolute), //PC Absolute address change
.mem_read_out(mem_read), //Memory read access
.mem_write_out(mem_write), //Memory write access
.nri_flg_out(nri_flag), //Not a real instruction, flag
.branch_funct_out(branch_funct), //Branch code, determines if branch should be taken or not along with output
.stall_out(stall_output), //Send stall signal out
.memsync_out(memsync), //Sync memory signal
.syscall_out(syscall), //Instruction is system call
.pem_inc_req_out(permission_inc), //Permission increase request
.pem_dec_req_out(permission_dec), //Permission decrease request
.sysreg_addr_out(sysreg_addr), //System/Special purpose register address to access
.sysreg_data_out(sysreg_data), //Data to write to System/Special purpose register
.sysreg_data_in(sysreg_data_input), //Data read from System/Special purpose register
.insn_pc_out(insn_pc_output), //Output PC value (for debugging)
/*Co-Processor Connections*/
.cp_insn_out(cp_insn) //Output instruction to Co-Processor to decode
);
integer i;
integer count;
/* Initial Conditions */
initial begin
$dumpfile("decode.vcd");
$dumpvars(0,decode_test);
$readmemh("test_insn.txt", insn_mem); //Fill memory
for( i = 0; i < MEM_SIZE; i = i + 1) begin
$display("Data read from insn_mem: %h | address: %h", insn_mem[i], i);
#10;
end
#100 //wait a bit before doing anything
clk <= 1'b0;
reset <= 1'b0; //put into reset to start
#10 //let the reset propagate
stall <= 1'b0;
// insn <= 32'b0;
insn_address <= 0;
sysreg_data_input <= 8'b0;
#10
reset <= 1'b1; //and they're off!
count <= 0;
/* Testing */
//always @(posedge clk) begin
#5
for( insn_address = 0; insn_address <= MEM_SIZE; insn_address = insn_address + 1) begin
#20;
insn <= insn_mem[insn_address]; //get instruction from memory address
$display("Current Address: %h | Instruction: %h", insn_address, insn);
end
//end
$finish;
end
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE rev.B2 compliant I2C Master byte-controller ////
//// ////
//// ////
//// Author: Richard Herveille ////
//// ////
//// www.asics.ws ////
//// ////
//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: i2c_master_byte_ctrl.v,v 1.7 2004/02/18 11:40:46 rherveille Exp $
//
// $Date: 2004/02/18 11:40:46 $
// $Revision: 1.7 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: i2c_master_byte_ctrl.v,v $
// Revision 1.7 2004/02/18 11:40:46 rherveille
// Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command.
//
// Revision 1.6 2003/08/09 07:01:33 rherveille
// Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
// Fixed a potential bug in the byte controller's host-acknowledge generation.
//
// Revision 1.5 2002/12/26 15:02:32 rherveille
// Core is now a Multimaster I2C controller
//
// Revision 1.4 2002/11/30 22:24:40 rherveille
// Cleaned up code
//
// Revision 1.3 2001/11/05 11:59:25 rherveille
// Fixed wb_ack_o generation bug.
// Fixed bug in the byte_controller statemachine.
// Added headers.
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "i2c_master_defines.v"
module i2c_master_byte_ctrl (
clk, rst, nReset, ena, clk_cnt, start, stop, read, write, ack_in, din,
cmd_ack, ack_out, dout, i2c_busy, i2c_al, scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen );
//
// inputs & outputs
//
input clk; // master clock
input rst; // synchronous active high reset
input nReset; // asynchronous active low reset
input ena; // core enable signal
input [15:0] clk_cnt; // 4x SCL
// control inputs
input start;
input stop;
input read;
input write;
input ack_in;
input [7:0] din;
// status outputs
output cmd_ack;
reg cmd_ack;
output ack_out;
reg ack_out;
output i2c_busy;
output i2c_al;
output [7:0] dout;
// I2C signals
input scl_i;
output scl_o;
output scl_oen;
input sda_i;
output sda_o;
output sda_oen;
//
// Variable declarations
//
// statemachine
parameter [4:0] ST_IDLE = 5'b0_0000;
parameter [4:0] ST_START = 5'b0_0001;
parameter [4:0] ST_READ = 5'b0_0010;
parameter [4:0] ST_WRITE = 5'b0_0100;
parameter [4:0] ST_ACK = 5'b0_1000;
parameter [4:0] ST_STOP = 5'b1_0000;
// signals for bit_controller
reg [3:0] core_cmd;
reg core_txd;
wire core_ack, core_rxd;
// signals for shift register
reg [7:0] sr; //8bit shift register
reg shift, ld;
// signals for state machine
wire go;
reg [2:0] dcnt;
wire cnt_done;
//
// Module body
//
// hookup bit_controller
i2c_master_bit_ctrl bit_controller (
.clk ( clk ),
.rst ( rst ),
.nReset ( nReset ),
.ena ( ena ),
.clk_cnt ( clk_cnt ),
.cmd ( core_cmd ),
.cmd_ack ( core_ack ),
.busy ( i2c_busy ),
.al ( i2c_al ),
.din ( core_txd ),
.dout ( core_rxd ),
.scl_i ( scl_i ),
.scl_o ( scl_o ),
.scl_oen ( scl_oen ),
.sda_i ( sda_i ),
.sda_o ( sda_o ),
.sda_oen ( sda_oen )
);
// generate go-signal
assign go = (read | write | stop) & ~cmd_ack;
// assign dout output to shift-register
assign dout = sr;
// generate shift register
always @(posedge clk or negedge nReset)
if (!nReset)
sr <= #1 8'h0;
else if (rst)
sr <= #1 8'h0;
else if (ld)
sr <= #1 din;
else if (shift)
sr <= #1 {sr[6:0], core_rxd};
// generate counter
always @(posedge clk or negedge nReset)
if (!nReset)
dcnt <= #1 3'h0;
else if (rst)
dcnt <= #1 3'h0;
else if (ld)
dcnt <= #1 3'h7;
else if (shift)
dcnt <= #1 dcnt - 3'h1;
assign cnt_done = ~(|dcnt);
//
// state machine
//
reg [4:0] c_state; // synopsis enum_state
always @(posedge clk or negedge nReset)
if (!nReset)
begin
core_cmd <= #1 `I2C_CMD_NOP;
core_txd <= #1 1'b0;
shift <= #1 1'b0;
ld <= #1 1'b0;
cmd_ack <= #1 1'b0;
c_state <= #1 ST_IDLE;
ack_out <= #1 1'b0;
end
else if (rst | i2c_al)
begin
core_cmd <= #1 `I2C_CMD_NOP;
core_txd <= #1 1'b0;
shift <= #1 1'b0;
ld <= #1 1'b0;
cmd_ack <= #1 1'b0;
c_state <= #1 ST_IDLE;
ack_out <= #1 1'b0;
end
else
begin
// initially reset all signals
core_txd <= #1 sr[7];
shift <= #1 1'b0;
ld <= #1 1'b0;
cmd_ack <= #1 1'b0;
case (c_state) // synopsys full_case parallel_case
ST_IDLE:
if (go)
begin
if (start)
begin
c_state <= #1 ST_START;
core_cmd <= #1 `I2C_CMD_START;
end
else if (read)
begin
c_state <= #1 ST_READ;
core_cmd <= #1 `I2C_CMD_READ;
end
else if (write)
begin
c_state <= #1 ST_WRITE;
core_cmd <= #1 `I2C_CMD_WRITE;
end
else // stop
begin
c_state <= #1 ST_STOP;
core_cmd <= #1 `I2C_CMD_STOP;
end
ld <= #1 1'b1;
end
ST_START:
if (core_ack)
begin
if (read)
begin
c_state <= #1 ST_READ;
core_cmd <= #1 `I2C_CMD_READ;
end
else
begin
c_state <= #1 ST_WRITE;
core_cmd <= #1 `I2C_CMD_WRITE;
end
ld <= #1 1'b1;
end
ST_WRITE:
if (core_ack)
if (cnt_done)
begin
c_state <= #1 ST_ACK;
core_cmd <= #1 `I2C_CMD_READ;
end
else
begin
c_state <= #1 ST_WRITE; // stay in same state
core_cmd <= #1 `I2C_CMD_WRITE; // write next bit
shift <= #1 1'b1;
end
ST_READ:
if (core_ack)
begin
if (cnt_done)
begin
c_state <= #1 ST_ACK;
core_cmd <= #1 `I2C_CMD_WRITE;
end
else
begin
c_state <= #1 ST_READ; // stay in same state
core_cmd <= #1 `I2C_CMD_READ; // read next bit
end
shift <= #1 1'b1;
core_txd <= #1 ack_in;
end
ST_ACK:
if (core_ack)
begin
if (stop)
begin
c_state <= #1 ST_STOP;
core_cmd <= #1 `I2C_CMD_STOP;
end
else
begin
c_state <= #1 ST_IDLE;
core_cmd <= #1 `I2C_CMD_NOP;
// generate command acknowledge signal
cmd_ack <= #1 1'b1;
end
// assign ack_out output to bit_controller_rxd (contains last received bit)
ack_out <= #1 core_rxd;
core_txd <= #1 1'b1;
end
else
core_txd <= #1 ack_in;
ST_STOP:
if (core_ack)
begin
c_state <= #1 ST_IDLE;
core_cmd <= #1 `I2C_CMD_NOP;
// generate command acknowledge signal
cmd_ack <= #1 1'b1;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, k, ans = -1, dist[2020]; vector<int> adj[2020], vet; int main() { scanf( %d%d , &n, &k); for (int(i) = (0); (i) < (k); (i)++) { int v; scanf( %d , &v); vet.push_back(v - n); } sort((vet).begin(), (vet).end()); vet.resize(unique((vet).begin(), (vet).end()) - vet.begin()); for (int(i) = (0); (i) < (2020); (i)++) for (int(j) = (0); (j) < (((int)(vet).size())); (j)++) if (i + vet[j] >= 0 && i + vet[j] < 2020) adj[i].push_back(i + vet[j]); queue<int> fila; fila.push(1010); while (!fila.empty()) { int v = fila.front(); fila.pop(); if (v == 1010 && dist[v]) { ans = dist[v]; break; } for (int(i) = (0); (i) < (((int)(adj[v]).size())); (i)++) if (!dist[adj[v][i]]) dist[adj[v][i]] = dist[v] + 1, fila.push(adj[v][i]); } printf( %d n , ans); } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR4BB_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__OR4BB_FUNCTIONAL_PP_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__or4bb (
VPWR,
VGND,
X ,
A ,
B ,
C_N ,
D_N
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
input B ;
input C_N ;
input D_N ;
// Local signals
wire DN nand0_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , D_N, C_N );
or or0 (or0_out_X , B, A, nand0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR4BB_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; int a[100005]; int cmp(int x, int y) { int x1 = 10 - x % 10; int y1 = 10 - y % 10; return x1 < y1; } int main() { int i, n, m; cin >> n >> m; for (i = 1; i <= n; i++) { scanf( %d , &a[i]); } sort(a + 1, a + 1 + n, cmp); for (i = 1; i <= n; i++) { if (a[i] == 100) continue; int x = 10 - a[i] % 10; if (m < x) { a[i] += m; m = 0; break; } a[i] += x; m -= x; } int s = 0; for (i = 1; i <= n; i++) { s += a[i] / 10; } if (m > 0) { for (i = 1; i <= n; i++) { if (m + a[i] >= 100) { s += (100 - a[i]) / 10; m -= (100 - a[i]); } else { s += m / 10; m = 0; break; } } } cout << s << endl; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFBBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__DFBBP_FUNCTIONAL_PP_V
/**
* dfbbp: Delay flop, inverted set, inverted reset,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_hd__udp_dff_nsr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dfbbp (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET;
wire SET ;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, D, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFBBP_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 2; int a[maxn << 1]; long long vis[maxn]; int main(void) { std::ios::sync_with_stdio(false), cin.tie(NULL), cout.tie(NULL); int n, m; while (cin >> n >> m) { int k = 0; int t; vector<int> a(n + m + 1); vector<long long> vis(m); for (int i = 1; i <= n + m; i++) cin >> a[i]; for (int i = 1; i <= n + m; i++) cin >> t, t ? vis[k++] = a[i] : 1; vis[k] = (int)1e18; for (int i = 1, j = 0; i <= n + m; j++) { int cnt = 0; while (a[i] < vis[j]) cnt++, i++; i++; while (a[i] - vis[j] <= vis[j + 1] - a[i] && i <= n + m) cnt++, i++; cout << cnt << ; } cout << endl; } } |
module CPU
(
clk_i,
rst_i,
start_i,
mem_data_i,
mem_ack_i,
mem_data_o,
mem_addr_o,
mem_enable_o,
mem_write_o
);
//input
input clk_i;
input rst_i;
input start_i;
//
// to Data Memory interface
//
input [256-1:0] mem_data_i;
input mem_ack_i;
output [256-1:0] mem_data_o;
output [32-1:0] mem_addr_o;
output mem_enable_o;
output mem_write_o;
wire [31:0] inst_addr, inst;
wire flush;
wire cache_stall;
assign flush = Control.Jump_o | (Control.Branch_o & Eq.branch_o);
Control Control(
.Inst_i(IF_ID.instruction_out[31:26]),
.Branch_o(),
.Jump_o(),
.Control_o()
);
Eq Eq(
.data1_i(Registers.RSdata_o),
.data2_i(Registers.RTdata_o),
.branch_o()
);
FW FW(
.EX_MEM_RegWrite(EX_MEM.WB_out[0]),
.MEM_WB_RegWrite(MEM_WB.RegWrite),
.EX_MEM_RegisterRd(EX_MEM.instruction_mux_out),
.MEM_WB_RegisterRd(MEM_WB.instruction_mux_out),
.ID_EX_RegisterRs(ID_EX.Inst_25_to_21_out),
.ID_Ex_RegisterRt(ID_EX.Inst_20_to_16_out),
.ForwardA(),
.ForwardB()
);
HD HD(
.ID_EX_MemRead(ID_EX.M_out[0]),
.IF_ID_RegisterRs(IF_ID.instruction_out[25:21]),
.IF_ID_RegisterRt(IF_ID.instruction_out[20:16]),
.ID_EX_RegisterRt(ID_EX.Inst_20_to_16_out),
.PC_Write(),
.IF_ID_Write(),
.data_o()
);
Instruction_Memory IM
(
.addr_i(PC.pc_o),
.instr_o()
);
mux1 mux1(
.data1_i(ADD.data_o), //branch_addr
.data2_i(add_pc.data_o), //Add_pc + 4
.Isbranch_i(Control.Branch_o & Eq.branch_o), //control && Eq
.data_o()
);
mux2 mux2(
.data1_i(mux1.data_o), //mux1.data_o
// DEBUG
.data2_i({mux1.data_o[31:28], IF_ID.instruction_out[25:0], 2'b00}), //jump_addr
.Isjump_i(Control.Jump_o),
.data_o()
);
mux3 mux3(
.data1_i(ID_EX.Inst_20_to_16_out),//RT
.data2_i(ID_EX.Inst_15_to_11_out),//RD
.IsRegDst_i(ID_EX.RegDst_out),
.data_o()
);
mux4 mux4(
.data1_i(mux7.data_o),//mux7 result
.data2_i(ID_EX.sign_extended_out),//signed extend
.IsALUSrc_i(ID_EX.ALUSrc_out),
.data_o()
);
mux5 mux5(
.data1_i(MEM_WB.ReadData_out),//read data from memory
.data2_i(MEM_WB.ALU_out),//ALU result
.IsMemtoReg_i(MEM_WB.MemtoReg),
.data_o()
);
mux6 mux6(
.data1_i(ID_EX.RDdata1_out),// ID/EX's read data1
.data2_i(mux5.data_o),// from REG's result
.data3_i(EX_MEM.ALU_out),// from EX's result
.IsForward_i(FW.ForwardA),
.data_o()
);
mux7 mux7(
.data1_i(ID_EX.RDdata2_out),// ID/EX's read data2
.data2_i(mux5.data_o),// from REG's result
.data3_i(EX_MEM.ALU_out),// from EX's result
.IsForward_i(FW.ForwardB),
.data_o()
);
mux8 mux8(
.data_i(Control.Control_o),
.IsHazzard_i(HD.data_o),
.data_o()
);
PC PC(
.clk_i(clk_i),
.rst_i(rst_i),
.start_i(start_i),
.pc_i(mux2.data_o),
.IsHazzard_i(HD.PC_Write),
.hold_i(cache_stall),
.pc_o()
);
Registers Registers
(
.clk_i(clk_i),
.RSaddr_i(IF_ID.instruction_out[25:21]),
.RTaddr_i(IF_ID.instruction_out[20:16]),
.RDaddr_i(MEM_WB.instruction_mux_out),
.RDdata_i(mux5.data_o),
.RegWrite_i(MEM_WB.RegWrite),
.RSdata_o(),
.RTdata_o()
);
Signed_Extend Signed_Extend(
.data_i(IF_ID.instruction_out[15:0]),
.data_o()
);
Adder ADD(
.data1_in(Signed_Extend.data_o << 2),
.data2_in(IF_ID.pc_plus4_out),
.data_o()
);
Adder add_pc(
.data1_in(PC.pc_o),
.data2_in(32'b100),
.data_o()
);
/*Data_memory Data_memory(
.clk_i(clk_i),
.addr_i(EX_MEM.ALU_out),
.data_i(EX_MEM.RDdata2_out),
.IsMemWrite(EX_MEM.MemWrite),
.IsMemRead(EX_MEM.MemRead),
.data_o()
);*/
IF_ID IF_ID(
.clk(clk_i),
.reset(),
.hazard_in(HD.IF_ID_Write),
.flush(Control.Jump_o | (Control.Branch_o & Eq.branch_o)),
.pc_plus4_in(add_pc.data_o),
.instruction_in(IM.instr_o),
.instruction_out(),
.pc_plus4_out(),
.hold_i(cache_stall)
);
ID_EX ID_EX(
.clk(clk_i),
.reset(),
.WB_in(mux8.data_o[1:0]),
.M_in(mux8.data_o[3:2]),
.EX_in(mux8.data_o[7:4]),
.RDdata1_in(Registers.RSdata_o),
.RDdata2_in(Registers.RTdata_o),
.sign_extended_in(Signed_Extend.data_o),
.Inst_25_to_21_in(IF_ID.instruction_out[25:21]),
.Inst_20_to_16_in(IF_ID.instruction_out[20:16]),
.Inst_15_to_11_in(IF_ID.instruction_out[15:11]),
.Inst_5_to_0_in(),
.pc_plus4_in(IF_ID.pc_plus4_out),
.WB_out(),
.M_out(),
.ALUSrc_out(),
.ALUOp_out(),
.RegDst_out(),
.RDdata1_out(),
.RDdata2_out(),
.sign_extended_out(),
.Inst_25_to_21_out(),
.Inst_20_to_16_out(),
.Inst_15_to_11_out(),
.Inst_5_to_0_out(),
.hold_i(cache_stall)
);
EX_MEM EX_MEM(
.clk(clk_i),
.reset(),
.WB_in(ID_EX.WB_out),
.M_in(ID_EX.M_out),
.ALU_in(ALU.data_o),
.instruction_mux_in(mux3.data_o),
.RDdata2_in(mux7.data_o),
.MemWrite(),
.MemRead(),
.WB_out(),
.ALU_out(),
.instruction_mux_out(),
.RDdata2_out(),
.hold_i(cache_stall)
);
MEM_WB MEM_WB(
.clk(clk_i),
.reset(),
.WB_in(EX_MEM.WB_out),
.ReadData_in(dcache.p1_data_o),
.ALU_in(EX_MEM.ALU_out),
.instruction_mux_in(EX_MEM.instruction_mux_out),
.RegWrite(),
.MemtoReg(),
.ReadData_out(),
.ALU_out(),
.instruction_mux_out(),
.hold_i(cache_stall)
);
ALU ALU(
.data1_i (mux6.data_o),
.data2_i (mux4.data_o),
.ALUCtrl_i (ALU_Control.ALUCtrl_o),
.data_o ()
);
ALU_Control ALU_Control(
.funct_i (ID_EX.sign_extended_out[5:0]),
.ALUOp_i (ID_EX.ALUOp_out),
.ALUCtrl_o ()
);
//data cache
dcache_top dcache
(
// System clock, reset and stall
.clk_i(clk_i),
.rst_i(rst_i),
// to Data Memory interface
.mem_data_i(mem_data_i),
.mem_ack_i(mem_ack_i),
.mem_data_o(mem_data_o),
.mem_addr_o(mem_addr_o),
.mem_enable_o(mem_enable_o),
.mem_write_o(mem_write_o),
// to CPU interface
.p1_data_i(EX_MEM.RDdata2_out),
.p1_addr_i(EX_MEM.ALU_out),
.p1_MemRead_i(EX_MEM.MemRead),
.p1_MemWrite_i(EX_MEM.MemWrite),
.p1_data_o(),
.p1_stall_o(cache_stall)
);
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: adc_data_fifo.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1.dp1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module adc_data_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input aclr;
input [11:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [11:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire [11:0] sub_wire1;
wire sub_wire2;
wire wrfull = sub_wire0;
wire [11:0] q = sub_wire1[11:0];
wire rdempty = sub_wire2;
dcfifo dcfifo_component (
.rdclk (rdclk),
.wrclk (wrclk),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.wrfull (sub_wire0),
.q (sub_wire1),
.rdempty (sub_wire2),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrusedw ());
defparam
dcfifo_component.intended_device_family = "Cyclone V",
dcfifo_component.lpm_numwords = 2048,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 12,
dcfifo_component.lpm_widthu = 11,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "2048"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "12"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "12"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "12"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 12 0 INPUT NODEFVAL "data[11..0]"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 12 0 data 0 0 12 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q 0 0 12 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL adc_data_fifo_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O21BAI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__O21BAI_BEHAVIORAL_PP_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__o21bai (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire b ;
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (b , B1_N );
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , b, or0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O21BAI_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; mt19937 mt_rand(time(0)); const int N = 3e5 + 5; int q, n, s[N], maks[N], dp[N]; map<int, int> mapa[N]; int main() { scanf( %d , &q); while (q--) { scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d , &s[i]); for (int i = 0; i < n; i++) { maks[i] = -1; mapa[i].clear(); dp[i] = 0; } mapa[0][s[0]] = 0; for (int i = 1; i < n; i++) { if (mapa[i - 1].count(s[i])) { int pos = mapa[i - 1][s[i]]; maks[i] = pos; swap(mapa[i], mapa[pos - 1]); if (pos > 0) mapa[i][s[pos - 1]] = pos - 1; } mapa[i][s[i]] = i; } long long ans = 0; for (int i = 1; i < n; i++) { if (maks[i] == -1) dp[i] = 0; else if (maks[i] == 0) dp[i] = 1; else dp[i] = 1 + dp[maks[i] - 1]; ans += dp[i]; } printf( %lld n , ans); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 102; int w, h, n, qs, qt; int area[maxn], areath; pair<int, int> q[1000006]; int dx[4] = {-1, 0, 1, 0}; int dy[4] = {0, -1, 0, 1}; bool vis[maxn][maxn]; bool cut[maxn][maxn][4]; int bfs(int stx, int sty) { qs = 0; qt = 1; q[0] = make_pair(stx, sty); while (qs < qt) { int nowx = q[qs].first; int nowy = q[qs++].second; for (int k = 0; k < 4; k++) if (!cut[nowx][nowy][k]) { int x = nowx + dx[k], y = nowy + dy[k]; if (x < 0 || x >= w || y < 0 || y >= h || vis[x][y]) continue; vis[x][y] = true; q[qt++] = make_pair(x, y); } } return qt; } int main() { cin >> w >> h >> n; for (int i = 1; i <= n; i++) { int xa, ya, xb, yb; cin >> xa >> ya >> xb >> yb; if (xa == xb) for (int j = ya; j < yb; j++) cut[xa][j][0] = cut[xa - 1][j][2] = true; else for (int j = xa; j < xb; j++) cut[j][ya][1] = cut[j][ya - 1][3] = true; } for (int i = 0; i < w; i++) for (int j = 0; j < h; j++) if (!vis[i][j]) { vis[i][j] = true; area[++areath] = bfs(i, j); } sort(area + 1, area + areath + 1); for (int i = 1; i < areath; i++) cout << area[i] << ; cout << area[areath] << endl; return 0; } |
//Legal Notice: (C)2020 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
//Register map:
//addr register type
//0 read data r
//1 write data w
//2 status r/w
//3 control r/w
//6 end-of-packet-value r/w
//INPUT_CLOCK: 116000000
//ISMASTER: 0
//DATABITS: 8
//TARGETCLOCK: 128000
//NUMSLAVES: 1
//CPOL: 0
//CPHA: 0
//LSBFIRST: 0
//EXTRADELAY: 0
//TARGETSSDELAY: 0
module wasca_spi_stm32 (
// inputs:
MOSI,
SCLK,
SS_n,
clk,
data_from_cpu,
mem_addr,
read_n,
reset_n,
spi_select,
write_n,
// outputs:
MISO,
data_to_cpu,
dataavailable,
endofpacket,
irq,
readyfordata
)
;
output MISO;
output [ 15: 0] data_to_cpu;
output dataavailable;
output endofpacket;
output irq;
output readyfordata;
input MOSI;
input SCLK;
input SS_n;
input clk;
input [ 15: 0] data_from_cpu;
input [ 2: 0] mem_addr;
input read_n;
input reset_n;
input spi_select;
input write_n;
wire E;
reg EOP;
wire MISO;
reg MOSI_reg;
reg ROE;
reg RRDY;
wire TMT;
reg TOE;
reg TRDY;
wire control_wr_strobe;
reg d1_tx_holding_emptied;
reg data_rd_strobe;
reg [ 15: 0] data_to_cpu;
reg data_wr_strobe;
wire dataavailable;
wire ds1_SCLK;
wire ds1_SS_n;
reg ds2_SCLK;
reg ds2_SS_n;
reg ds3_SS_n;
wire ds_MOSI;
wire endofpacket;
reg [ 15: 0] endofpacketvalue_reg;
wire endofpacketvalue_wr_strobe;
wire forced_shift;
reg iEOP_reg;
reg iE_reg;
reg iROE_reg;
reg iRRDY_reg;
reg iTMT_reg;
reg iTOE_reg;
reg iTRDY_reg;
wire irq;
reg irq_reg;
wire p1_data_rd_strobe;
wire [ 15: 0] p1_data_to_cpu;
wire p1_data_wr_strobe;
wire p1_rd_strobe;
wire p1_wr_strobe;
reg rd_strobe;
wire readyfordata;
wire resetShiftSample;
reg [ 7: 0] rx_holding_reg;
wire sample_clock;
reg shiftStateZero;
wire shift_clock;
reg [ 7: 0] shift_reg;
wire [ 10: 0] spi_control;
wire [ 10: 0] spi_status;
reg [ 3: 0] state;
wire status_wr_strobe;
reg transactionEnded;
reg tx_holding_emptied;
reg [ 7: 0] tx_holding_reg;
reg wr_strobe;
//spi_control_port, which is an e_avalon_slave
assign p1_rd_strobe = ~rd_strobe & spi_select & ~read_n;
// Read is a two-cycle event.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
rd_strobe <= 0;
else
rd_strobe <= p1_rd_strobe;
end
assign p1_data_rd_strobe = p1_rd_strobe & (mem_addr == 0);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_rd_strobe <= 0;
else
data_rd_strobe <= p1_data_rd_strobe;
end
assign p1_wr_strobe = ~wr_strobe & spi_select & ~write_n;
// Write is a two-cycle event.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
wr_strobe <= 0;
else
wr_strobe <= p1_wr_strobe;
end
assign p1_data_wr_strobe = p1_wr_strobe & (mem_addr == 1);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_wr_strobe <= 0;
else
data_wr_strobe <= p1_data_wr_strobe;
end
assign control_wr_strobe = wr_strobe & (mem_addr == 3);
assign status_wr_strobe = wr_strobe & (mem_addr == 2);
assign endofpacketvalue_wr_strobe = wr_strobe & (mem_addr == 6);
assign TMT = SS_n & TRDY;
assign E = ROE | TOE;
assign spi_status = {EOP, E, RRDY, TRDY, TMT, TOE, ROE, 3'b0};
// Streaming data ready for pickup.
assign dataavailable = RRDY;
// Ready to accept streaming data.
assign readyfordata = TRDY;
// Endofpacket condition detected.
assign endofpacket = EOP;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
iEOP_reg <= 0;
iE_reg <= 0;
iRRDY_reg <= 0;
iTRDY_reg <= 0;
iTMT_reg <= 0;
iTOE_reg <= 0;
iROE_reg <= 0;
end
else if (control_wr_strobe)
begin
iEOP_reg <= data_from_cpu[9];
iE_reg <= data_from_cpu[8];
iRRDY_reg <= data_from_cpu[7];
iTRDY_reg <= data_from_cpu[6];
iTMT_reg <= data_from_cpu[5];
iTOE_reg <= data_from_cpu[4];
iROE_reg <= data_from_cpu[3];
end
end
assign spi_control = {iEOP_reg, iE_reg, iRRDY_reg, iTRDY_reg, 1'b0, iTOE_reg, iROE_reg, 3'b0};
// IRQ output.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_reg <= 0;
else
irq_reg <= (EOP & iEOP_reg) | ((TOE | ROE) & iE_reg) | (RRDY & iRRDY_reg) | (TRDY & iTRDY_reg) | (TOE & iTOE_reg) | (ROE & iROE_reg);
end
assign irq = irq_reg;
// End-of-packet value register.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
endofpacketvalue_reg <= 0;
else if (endofpacketvalue_wr_strobe)
endofpacketvalue_reg <= data_from_cpu;
end
assign p1_data_to_cpu = ((mem_addr == 2))? spi_status :
((mem_addr == 3))? spi_control :
((mem_addr == 6))? endofpacketvalue_reg :
rx_holding_reg;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_to_cpu <= 0;
else
// Data to cpu.
data_to_cpu <= p1_data_to_cpu;
end
assign forced_shift = ds2_SS_n & ~ds3_SS_n;
assign ds1_SS_n = SS_n;
// System clock domain events.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
ds2_SS_n <= 1;
ds3_SS_n <= 1;
transactionEnded <= 0;
EOP <= 0;
RRDY <= 0;
TRDY <= 1;
TOE <= 0;
ROE <= 0;
tx_holding_reg <= 0;
rx_holding_reg <= 0;
d1_tx_holding_emptied <= 0;
end
else
begin
ds2_SS_n <= ds1_SS_n;
ds3_SS_n <= ds2_SS_n;
transactionEnded <= forced_shift;
d1_tx_holding_emptied <= tx_holding_emptied;
if (tx_holding_emptied & ~d1_tx_holding_emptied)
TRDY <= 1;
// EOP must be updated by the last (2nd) cycle of access.
if ((p1_data_rd_strobe && (rx_holding_reg == endofpacketvalue_reg)) || (p1_data_wr_strobe && (data_from_cpu[7 : 0] == endofpacketvalue_reg)))
EOP <= 1;
if (forced_shift)
begin
if (RRDY)
ROE <= 1;
else
rx_holding_reg <= shift_reg;
RRDY <= 1;
end
// On data read, clear the RRDY bit.
if (data_rd_strobe)
RRDY <= 0;
// On status write, clear all status bits (ignore the data).
if (status_wr_strobe)
begin
EOP <= 0;
RRDY <= 0;
ROE <= 0;
TOE <= 0;
end
// On data write, load the transmit holding register and prepare to execute.
//Safety feature: if tx_holding_reg is already occupied, ignore this write, and generate
//the write-overrun error.
if (data_wr_strobe)
begin
if (TRDY)
tx_holding_reg <= data_from_cpu;
if (~TRDY)
TOE <= 1;
TRDY <= 0;
end
end
end
assign resetShiftSample = ~reset_n | transactionEnded;
assign MISO = ~SS_n & shift_reg[7];
assign ds1_SCLK = SCLK;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
ds2_SCLK <= 0;
else
ds2_SCLK <= ds1_SCLK;
end
assign shift_clock = ((~ds1_SS_n & ~ds1_SCLK)) & ~((~ds2_SS_n & ~ds2_SCLK));
assign sample_clock = (~(~ds1_SS_n & ~ds1_SCLK)) & ~(~(~ds2_SS_n & ~ds2_SCLK));
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
state <= 0;
else
state <= resetShiftSample ? 0 : (sample_clock & (state != 8)) ? (state + 1) : state;
end
assign ds_MOSI = MOSI;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
MOSI_reg <= 0;
else
MOSI_reg <= resetShiftSample ? 0 : sample_clock ? ds_MOSI : MOSI_reg;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
shift_reg <= 0;
else
shift_reg <= resetShiftSample ? 0 : shift_clock ? (shiftStateZero ? tx_holding_reg : {shift_reg[6 : 0], MOSI_reg}) : shift_reg;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
shiftStateZero <= 1;
else
shiftStateZero <= resetShiftSample ? 1 : shift_clock? 0 : shiftStateZero;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
tx_holding_emptied <= 0;
else
tx_holding_emptied <= resetShiftSample ? 0 : shift_clock ? (shiftStateZero ? 1 : 0) : tx_holding_emptied;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, p, ans(0); cin >> n; map<string, int> mp; string s; while (n--) { cin >> s; mp[s]++; } for (auto x : mp) { if (x.first == Tetrahedron ) p = 4; else if (x.first == Cube ) p = 6; else if (x.first == Octahedron ) p = 8; else if (x.first == Dodecahedron ) p = 12; else p = 20; ans += p * x.second; } cout << ans; } |
#include <bits/stdc++.h> using namespace std; #define mod 1000000007 #define int long long #define double long double #define pb push_back #define mp make_pair #define endl n #define all(x) x.begin(),x.end() #define fill(a,b) memset(a,b,sizeof(a)) #define sz(x) (int)x.size() #define ff first #define ss second #define lb lower_bound #define ub upper_bound #define bs binary_search #define rep(i, begin, end) for (__typeof(end) i = (begin) - ((begin) > (end)); i != (end) - ((begin) > (end)); i += 1 - 2 * ((begin) > (end))) #define deb(x) cout<<#x<< <<x<<endl; #define T int t; cin>>t; while(t--) #define fst ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int firstMissingPositive(int arr[], int n) { for (int i = 0; i < n; i++) { while (arr[i] >= 1 && arr[i] <= n && arr[i] != arr[arr[i] - 1]) { swap(arr[i], arr[arr[i] - 1]); } } for (int i = 0; i < n; i++) { if (arr[i] != i + 1) { return i + 1; } } return n + 1; } signed main() { fst; #ifndef ONLINE_JUDGE freopen( input3.txt , r , stdin); freopen( output3.txt , w , stdout); #endif T{ int n,p,q, m,h, k, sum = 0, cnt=0, x, y, z, flag = 0, pos, diff,r=0,l=0,u=0,d=0,cnt1=0,cnt0=0,cnt2=0,ans,mi=INT_MAX,mx=INT_MIN; cin>>n; int a[n]; vector<int> v,v1,v2; set<int> st; map<int,int> mp; rep(i,0,n) { cin>>x; if(find(all(st),x) != st.end()) v.pb(x); st.insert(x); } for(auto i:st) cout<<i<< ; sort(all(v)); for(auto i:v) cout<<i<< ; cout<<endl; v.clear(); st.clear(); } } |
#include <bits/stdc++.h> using namespace std; void init_code() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); } int main() { init_code(); long long t; cin >> t; while (t--) { long long x1, y1, z1; long long x2, y2, z2; cin >> x1 >> y1 >> z1 >> x2 >> y2 >> z2; long long ans = 0; if (z1 >= y2) { z1 = z1 - y2; ans = ans + 2 * (y2); y2 = 0; long long f = z1 + x1; if (f <= z2) { z2 = z2 - f; ans = ans - 2 * z2; } } else { ans = ans + 2 * (z1); y2 = y2 - z1; z1 = 0; long long f = z1 + x1; if (f <= z2) { z2 = z2 - f; ans = ans - 2 * z2; } } cout << ans << n ; } } |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:1000000000 ) using namespace std; inline void solve(); int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); solve(); } string abc = abcdefghijklmnopqrstuvwxyz ; string ABC = ABCDEFGHIJKLMNOPQRSTUVWXYZ ; string digits = 0123456789 ; void solve() { vector<long long> ind[30]; string s; cin >> s; long long n = s.length(); for (long long i = 0; i < n; i++) ind[s[i] - a ].push_back(i); double ans = 0; s = s + s; long long p[30] = {0}; for (long long i = 0; i < 26; i++) { for (long long len = 1; len < n; len++) { long long c[30] = {0}; for (long long l = 0; l < ind[i].size(); l++) { c[s[ind[i][l] + len] - a ]++; } long long cnt = 0; for (long long j = 0; j < 30; j++) if (c[j] == 1) cnt++; p[i] = max(p[i], cnt); } ans += p[i] * 1. / n; } cout << setprecision(15) << fixed << ans; } |
#include <bits/stdc++.h> using namespace std; set<pair<pair<long long int, long long int>, long long int> > ev; vector<long long int> cnt, len; multiset<pair<long long int, long long int> > flug; void expand( set<pair<pair<long long int, long long int>, long long int> >::iterator it, long long int a) { pair<pair<long long int, long long int>, long long int> p = *it; p.first.first += a; cnt[p.second]++, len[p.second] += a; auto nt = ev.insert(p).first; ev.erase(it, nt); auto ft = flug.upper_bound(make_pair(p.first.first, 1e18)); if (ft == flug.begin()) return; ft--; if (ft->first >= -p.first.second) { long long int add = ft->second; flug.erase(ft); expand(nt, add); } } int main() { int n, m; scanf( %d%d , &n, &m); vector<pair<pair<long long int, long long int>, long long int> > g(n), f(m); cnt = len = vector<long long int>(n, 0); for (int((i)) = (0); ((i)) < ((n)); ((i))++) { int x, sz; scanf( %d%d , &x, &sz); g[i] = make_pair(make_pair((x), (sz)), (i)); len[i] = sz; } for (int((i)) = (0); ((i)) < ((m)); ((i))++) { int x, sz; scanf( %d%d , &x, &sz); f[i] = make_pair(make_pair((x), (sz)), (i)); } sort((g).begin(), (g).end()); reverse((g).begin(), (g).end()); for (int((i)) = (0); ((i)) < ((n)); ((i))++) { auto it = ev.insert(make_pair(make_pair((g[i].first.first + g[i].first.second), (-g[i].first.first)), (g[i].second))) .first; ev.erase(ev.begin(), it); } for (int((i)) = (0); ((i)) < ((m)); ((i))++) { pair<pair<long long int, long long int>, long long int> fp = make_pair(make_pair((f[i].first.first), (-1e18)), (0)); auto it = ev.lower_bound(fp); if (it != ev.end() && -it->first.second <= f[i].first.first) expand(it, f[i].first.second); else flug.insert({f[i].first.first, f[i].first.second}); } for (int((i)) = (0); ((i)) < ((n)); ((i))++) printf( %I64d %I64d n , cnt[i], len[i]); } |
#include <bits/stdc++.h> using namespace std; template <class T> bool umin(T& a, T b) { if (a > b) { a = b; return 1; } return 0; } template <class T> bool umax(T& a, T b) { if (a < b) { a = b; return 1; } return 0; } int arr[100009], val[100009], n, k; int ok(int x) { long long res = 0; for (int i = 1; i <= n; i++) res += (arr[i] + x - 1) / x; return (res <= k); } long long f(int x, int y) { int a = x % y, aa = x / y + 1; int b = y - a, bb = x / y; return aa * 1LL * aa * a + bb * 1LL * bb * b; } set<pair<long long, int> > s; int main() { scanf( %d%d , &n, &k); for (int i = 1; i <= n; i++) { scanf( %d , &arr[i]); val[i] = 1; if (arr[i] > 1) s.insert(make_pair(f(arr[i], val[i] + 1) - f(arr[i], val[i]), i)); } for (int j = 0; j < k - n; j++) { pair<long long, int> nd = *s.begin(); s.erase(nd); int i = nd.second; val[i]++; if (val[i] < arr[i]) s.insert(make_pair(f(arr[i], val[i] + 1) - f(arr[i], val[i]), i)); } long long res = 0; for (int i = 1; i <= n; i++) res += f(arr[i], val[i]); printf( %lld n , res); return 0; } |
// ====================================================================
// Radio-86RK FPGA REPLICA
//
// Copyright (C) 2011 Dmitry Tselikov
//
// This core is distributed under modified BSD license.
// For complete licensing information see LICENSE.TXT.
// --------------------------------------------------------------------
//
// An open implementation of Radio-86RK video output
//
// Author: Dmitry Tselikov http://bashkiria-2m.narod.ru/
// Modified by: Andy Karpov <> for WXEDA board
//
// Design File: rk_video.v
//
module rk_video(
input clk,
output hr,
output vr,
output hr_wg75,
output vr_wg75,
output cce,
output [4:0] r,
output [5:0] g,
output [4:0] b,
input[3:0] line,
input[6:0] ichar,
input vsp,
input lten,
input rvv
);
// rk related
reg[1:0] state;
reg[10:0] h_cnt;
reg[10:0] v_cnt;
reg[10:0] v_cnt2;
reg[1:0] v_cnt_line;
reg[2:0] d_cnt;
reg[5:0] data;
wire[7:0] fdata;
// framebuffer 408x300 (384x250 + gaps)
reg[17:0] address_in;
reg[17:0] address_out;
reg data_in;
wire data_out;
rambuffer framebuf(
.address_a(address_in),
.address_b(address_out),
.clock(clk),
.data_a(data_in),
.data_b(),
.wren_a(1'b1),
.wren_b(1'b0),
.q_a(),
.q_b(data_out)
);
assign hr_wg75 = h_cnt >= 10'd468 && h_cnt < 10'd516 ? 1'b0 : 1'b1; // wg75 hsync
assign vr_wg75 = v_cnt >= 10'd600 && v_cnt < 10'd620 ? 1'b0 : 1'b1; // wg75 vsync
assign cce = d_cnt==3'b000 && state == 2'b01; // wg75 chip enable signal
font from(.address({ichar[6:0],line[2:0]}), .clock(clk), .q(fdata));
always @(posedge clk)
begin
// 3x divider to get 16MHz clock from 48MHz
casex (state)
2'b00: state <= 2'b01;
2'b01: state <= 2'b10;
2'b1x: state <= 2'b00;
endcase
if (state == 2'b00)
begin
if (d_cnt==3'b101)
data <= lten ? 6'h3F : vsp ? 6'b0 : fdata[5:0]^{6{rvv}};
else
data <= {data[4:0],1'b0};
// write visible data to framebuffer
if (h_cnt >= 60 && h_cnt < 468 && v_cnt2 >= 0 && v_cnt2 < 300 && v_cnt_line == 2'b00)
begin
address_in <= h_cnt - 60 + (10'd408*(v_cnt2 - 0));
data_in <= data[5];
//data_in <= 1'b1; // test white screen
end
if (h_cnt+1'b1 == 10'd516) // 516 - end of line
begin
h_cnt <= 0;
d_cnt <= 0;
if (v_cnt+1'b1 == 10'd620 ) // 310 - end of frame
begin
v_cnt <= 0;
v_cnt2 <= 0;
end
else begin
v_cnt <= v_cnt+1'b1;
casex (v_cnt_line)
2'b00: v_cnt_line <= 2'b01;
2'b01: v_cnt_line <= 2'b00;
2'b1x: v_cnt_line <= 2'b00;
endcase
if (v_cnt_line == 2'b00)
v_cnt2 <= v_cnt2+1'b1;
end
end
else
begin
h_cnt <= h_cnt+1'b1;
if (d_cnt+1'b1 == 3'b110) // end of char
d_cnt <= 0;
else
d_cnt <= d_cnt+1'b1;
end
end
end
// vga sync generator
wire[10:0] CounterX;
wire[10:0] CounterY;
wire inDisplay;
hvsync_generator vgasync(
.clk(clk),
.vga_h_sync(hr),
.vga_v_sync(vr),
.inDisplayArea(inDisplay),
.CounterX(CounterX),
.CounterY(CounterY)
);
// vga signal generator
reg[1:0] pixel_state;
reg[1:0] line_state;
reg[10:0] pixel_cnt;
reg[10:0] line_cnt;
assign r = data_out && inDisplay ? 5'b10000 : 5'b0;
assign g = data_out && inDisplay ? 6'b100000 : 6'b0;
assign b = data_out && inDisplay ? 5'b10000 : 5'b0;
always @(posedge clk)
begin
if (CounterX >= 0 && CounterX < 816 && CounterY >= 0 && CounterY < 600) // doubledot visible area
begin
casex (pixel_state)
2'b00: pixel_state <= 2'b01;
2'b01: pixel_state <= 2'b00;
endcase
address_out <= pixel_cnt + (line_cnt*408);
if (pixel_state == 2'b01)
pixel_cnt <= pixel_cnt + 1;
if (CounterX+1 == 816)
begin
pixel_cnt <= 0;
casex (line_state)
2'b00: line_state <= 2'b01;
2'b01: line_state <= 2'b00;
endcase
if (line_state == 2'b01)
line_cnt <= line_cnt + 1;
end
if (CounterY+1 == 600)
begin
line_cnt <= 0;
pixel_cnt <= 0;
line_state <= 0;
end
end
end
endmodule
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
module altera_up_edge_detection_hysteresis (
// Inputs
clk,
reset,
data_in,
data_en,
// Bidirectionals
// Outputs
data_out
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter WIDTH = 640; // Image width in pixels
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [ 7: 0] data_in;
input data_en;
// Bidirectionals
// Outputs
output [ 7: 0] data_out;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [ 8: 0] shift_reg_out[ 1: 0];
wire data_above_high_threshold;
wire [ 8: 0] data_to_shift_register_1;
wire above_threshold;
wire overflow;
// Internal Registers
reg [ 8: 0] data_line_2[ 1: 0];
reg [ 2: 0] thresholds[ 2: 0];
reg [ 7: 0] result;
// State Machine Registers
// Integers
integer i;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
begin
data_line_2[0] <= 8'h00;
data_line_2[1] <= 8'h00;
for (i = 2; i >= 0; i = i-1)
thresholds[i] <= 3'h0;
end
else if (data_en == 1'b1)
begin
// Increase edge visibility by 32 and saturate at 255
data_line_2[1] <= data_line_2[0] | {9{data_line_2[0][8]}};
data_line_2[0] <= {1'b0, shift_reg_out[0][7:0]} + 32;
thresholds[0] <= {thresholds[0][1:0], data_above_high_threshold};
thresholds[1] <= {thresholds[1][1:0], shift_reg_out[0][8]};
thresholds[2] <= {thresholds[2][1:0], shift_reg_out[1][8]};
result <= (above_threshold) ? data_line_2[1][7:0] : 8'h00;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// External Assignments
assign data_out = result;
// Internal Assignments
assign data_above_high_threshold = (data_in >= 8'h0A) ? 1'b1 : 1'b0;
assign data_to_shift_register_1 = {data_above_high_threshold,data_in};
assign above_threshold =
((|(thresholds[0])) | (|(thresholds[1])) | (|(thresholds[2])));
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_edge_detection_data_shift_register shift_register_1 (
// Inputs
.clock (clk),
.clken (data_en),
.shiftin (data_to_shift_register_1),
// Bidirectionals
// Outputs
.shiftout (shift_reg_out[0]),
.taps ()
);
defparam
shift_register_1.DW = 9,
shift_register_1.SIZE = WIDTH;
altera_up_edge_detection_data_shift_register shift_register_2 (
// Inputs
.clock (clk),
.clken (data_en),
.shiftin (shift_reg_out[0]),
// Bidirectionals
// Outputs
.shiftout (shift_reg_out[1]),
.taps ()
);
defparam
shift_register_2.DW = 9,
shift_register_2.SIZE = WIDTH;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MD = 1000000007; long long A[100000 + 1], dp[100000 + 1]; long long exp(long long a, long long b) { long long r = 1; while (b > 0) { if (b & 1) r = r * a; b /= 2; a = a * a; } return r; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long t, n, i, s, j, p, m, x, y, k, q; string s1; map<long long, long long> mp; for (i = 0; i <= 32; i++) mp.insert({exp(2, i), i}); cin >> n >> m; for (long long i = 1; i <= n; i++) { cin >> x; A[mp[x]]++; } while (m--) { cin >> x; p = 0; for (i = 32; i >= 0; --i) { k = min(x / exp(2, i), A[i]); p += k; x -= k * exp(2, i); } if (x != 0) cout << -1 n ; else cout << p << n ; } } |
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module Computer_System_SysID (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? : 0;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int H, W, K; cin >> H >> W >> K; vector<string> photo(H); for (int h = 0; h < int(H); ++h) cin >> photo[h]; vector<vector<char> > star(H, vector<char>(W, 0)); for (int r = 1; r < int(H - 1); ++r) for (int c = 1; c < int(W - 1); ++c) { if (photo[r][c] == 1 && photo[r - 1][c] == 1 && photo[r][c - 1] == 1 && photo[r + 1][c] == 1 && photo[r][c + 1] == 1 ) { star[r][c] = 1; } } long long res = 0; for (int c1 = 0; c1 < int(W); ++c1) { vector<int> row_stars(H, 0); for (int c2 = c1 + 3; c2 <= int(W); ++c2) { for (int r = 0; r < int(H); ++r) row_stars[r] += star[r][c2 - 2]; int r1 = 0, stars = 0; for (int r2 = r1 + 3; r2 <= int(H); ++r2) { stars += row_stars[r2 - 2]; while (stars - row_stars[r1 + 1] >= K) { stars -= row_stars[r1 + 1]; ++r1; } if (stars >= K) res += r1 + 1; } } } cout << res << endl; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUXB8TO1_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__MUXB8TO1_BEHAVIORAL_V
/**
* muxb8to1: Buffered 8-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__muxb8to1 (
Z,
D,
S
);
// Module ports
output Z;
input [7:0] D;
input [7:0] S;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
bufif1 bufif10 (Z , !D[0], S[0] );
bufif1 bufif11 (Z , !D[1], S[1] );
bufif1 bufif12 (Z , !D[2], S[2] );
bufif1 bufif13 (Z , !D[3], S[3] );
bufif1 bufif14 (Z , !D[4], S[4] );
bufif1 bufif15 (Z , !D[5], S[5] );
bufif1 bufif16 (Z , !D[6], S[6] );
bufif1 bufif17 (Z , !D[7], S[7] );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUXB8TO1_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; const long long maxn = 205; long long dp[maxn][maxn][maxn]; long long n; string s, t; long long recur(long long pos, long long changes, long long sum) { if (pos == n) return 0; if (dp[pos][changes][sum] != -1) return dp[pos][changes][sum]; long long res = recur(pos + 1, changes, sum); if (s[pos] == t[0]) res = max(res, recur(pos + 1, changes, sum + 1)); if (s[pos] == t[1]) res = max(res, recur(pos + 1, changes, sum) + sum); if (s[pos] == t[0] && s[pos] == t[1]) res = max(res, recur(pos + 1, changes, sum + 1) + sum); if (changes > 0) { res = max(res, recur(pos + 1, changes - 1, sum + 1)); res = max(res, recur(pos + 1, changes - 1, sum) + sum); if (t[0] == t[1]) res = max(res, recur(pos + 1, changes - 1, sum + 1) + sum); } dp[pos][changes][sum] = res; return res; } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); for (long long i = 0; i < maxn; i++) for (long long j = 0; j < maxn; j++) for (long long k = 0; k < maxn; k++) dp[i][j][k] = -1; long long k; cin >> n >> k >> s >> t; long long res = recur(0, k, 0); cout << res << n ; } |
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
// IP Revision: 6
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module XEVIOUS_BROM (
clka,
addra,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [14 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [7 : 0] douta;
blk_mem_gen_v8_2 #(
.C_FAMILY("zynq"),
.C_XDEVICEFAMILY("zynq"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(3),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(1),
.C_INIT_FILE_NAME("XEVIOUS_BROM.mif"),
.C_INIT_FILE("XEVIOUS_BROM.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(0),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_READ_WIDTH_A(8),
.C_WRITE_DEPTH_A(32768),
.C_READ_DEPTH_A(32768),
.C_ADDRA_WIDTH(15),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(8),
.C_READ_WIDTH_B(8),
.C_WRITE_DEPTH_B(32768),
.C_READ_DEPTH_B(32768),
.C_ADDRB_WIDTH(15),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("8"),
.C_COUNT_18K_BRAM("0"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 2.326399 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(1'D0),
.regcea(1'D0),
.wea(1'B0),
.addra(addra),
.dina(8'B0),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(15'B0),
.dinb(8'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(8'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
// D6LUT, C6LUT, B6LUT, A6LUT == W6LUT
// A fracturable 6 input LUT. Can either be;
// - 2 * 5 input, 1 output LUT
// - 1 * 6 input, 1 output LUT
module {N}LUT(A1, A2, A3, A4, A5, A6, O6, O5);
input wire A1;
input wire A2;
input wire A3;
input wire A4;
input wire A5;
input wire A6;
output wire O6;
output wire O5;
parameter [63:0] INIT = 0;
// LUT5 (upper)
wire [15: 0] upper_s4 = A5 ? INIT[63:48] : INIT[47:32];
wire [ 7: 0] upper_s3 = A4 ? upper_s4[15: 8] : upper_s4[ 7: 0];
wire [ 3: 0] upper_s2 = A3 ? upper_s3[ 7: 4] : upper_s3[ 3: 0];
wire [ 1: 0] upper_s1 = A2 ? upper_s2[ 3: 2] : upper_s2[ 1: 0];
wire upper_O = A1 ? upper_s1[ 1] : upper_s1[ 0];
// LUT5 (lower)
wire [15: 0] lower_s4 = A5 ? INIT[31:16] : INIT[15: 0];
wire [ 7: 0] lower_s3 = A4 ? lower_s4[15: 8] : lower_s4[ 7: 0];
wire [ 3: 0] lower_s2 = A3 ? lower_s3[ 7: 4] : lower_s3[ 3: 0];
wire [ 1: 0] lower_s1 = A2 ? lower_s2[ 3: 2] : lower_s2[ 1: 0];
wire lower_O = A1 ? lower_s1[ 1] : lower_s1[ 0];
assign O5 = lower_O;
// MUXF6
assign O6 = A6 ? upper_O : lower_O;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, k, m; int times[45]; int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n >> k >> m; for (int i = 0; i < k; i++) cin >> times[i]; int s = 0; for (int i = 0; i < k; i++) s += times[i]; sort(begin(times), begin(times) + k); int currBest = 0; for (int numSolves = 0; numSolves < n + 1; numSolves++) { if (s * numSolves > m) break; int score = 0; score += numSolves * (k + 1); int timeLeft = m - s * numSolves; int numUnsolved = n - numSolves; int i = 0; while (timeLeft >= times[i] && i < k) { score += min(timeLeft / times[i], numUnsolved); timeLeft -= times[i] * min(timeLeft / times[i], numUnsolved); i++; } currBest = max(score, currBest); } cout << currBest << n ; } |
#include <bits/stdc++.h> #pragma GCC omptimize( unroll-loops ) #pragma optimize( SEX_ON_THE_BEACH ) #pragma GCC optimize( no-stack-protector ) #pragma comment(linker, /STACK:1000000000 ) using namespace std; using ll = long long int; using ull = unsigned long long int; using dd = long double; using ldd = long double; using si = short int; using pii = pair<int, int>; using pll = pair<ll, ll>; ll get_seed(string s) { ll ans = 0; for (int i = 0; i < s.size(); ++i) ans += s[i]; return ans; } int popcount(int x) { return __builtin_popcount(x); } ll popcountll(ll x) { return __builtin_popcount(x); } int way[10][10]; void build(int x, int y) { for (int i = 0; i < 10; ++i) for (int j = 0; j < 10; ++j) way[i][j] = 1e5; for (int i = 0; i < 10; ++i) way[i][(i + x) % 10] = way[i][(i + y) % 10] = 1; for (int k = 0; k < 10; ++k) for (int i = 0; i < 10; ++i) for (int j = 0; j < 10; ++j) way[i][j] = min(way[i][j], way[i][k] + way[k][j]); for (int i = 0; i < 10; ++i) for (int j = 0; j < 10; ++j) if (way[i][j] >= (int)(1e5)) way[i][j] = -1; } int get_ans(int x, int y, string& s) { build(x, y); ll ans = 0; int curr = 0; for (int i = 1; i < s.size(); ++i) { if (way[curr][s[i] - 0 ] == -1) return -1; ans += way[curr][s[i] - 0 ] - 1; curr = s[i] - 0 ; } return ans; } void solve(int ii) { string s; cin >> s; for (int x = 0; x < 10; ++x) { for (int y = 0; y < 10; ++y) cout << get_ans(x, y, s) << ; cout << n ; } } int main() { ios_base::sync_with_stdio(0); cout.tie(0); cin.tie(0); int t; t = 1; for (int i = 0; i < t; ++i) solve(i); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { long long n; cin >> n; vector<int> list; int maxx, ma; for (int i = 0; i < n; i++) { int u; cin >> u; list.push_back(u); } int u1, u2, u3; int flag; for (int i = 1; i < n - 1; i++) { flag = 0; for (int j = 0; j < i; j++) { if (list[i] > list[j]) { flag = 1; u1 = j; break; } } for (int j = i + 1; j < n; j++) { if (list[i] > list[j]) { if (flag == 1) { flag = 2; u2 = j; break; } else { break; } } } if (flag == 2) { u3 = i; break; } } if (flag == 2) { cout << YES << endl; cout << u1 + 1 << << u3 + 1 << << u2 + 1 << endl; } else { cout << NO << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 3010; int a[MAXN], b[MAXN], c[MAXN]; int d[MAXN][2]; int main() { int n; while (~scanf( %d , &n)) { for (int i = 1; i <= n; ++i) scanf( %d , &a[i]); for (int i = 1; i <= n; ++i) scanf( %d , &b[i]); for (int i = 1; i <= n; ++i) scanf( %d , &c[i]); d[1][0] = b[1]; d[1][1] = a[1]; for (int i = 2; i <= n; ++i) { d[i][0] = max(d[i - 1][0] + b[i], d[i - 1][1] + c[i]); d[i][1] = max(d[i - 1][0] + a[i], d[i - 1][1] + b[i]); } printf( %d n , d[n][1]); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 1e9 + 9; const int MAXN = 3e5 + 1; int l[MAXN], r[MAXN]; signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) { int n; cin >> n; vector<int> v(n); for (int i = (int)(0); i < (int)(n); ++i) { l[i] = INF; r[i] = -INF; } for (int i = (int)(0); i < (int)(n); ++i) { cin >> v[i]; --v[i]; l[v[i]] = min(l[v[i]], i); r[v[i]] = max(r[v[i]], i); } sort(v.begin(), v.end()); v.erase(unique(v.begin(), v.end()), v.end()); vector<int> dp(n, 0); int ans = n; for (int i = 0; i < v.size(); ++i) { if (!i || l[v[i]] <= r[v[i - 1]]) dp[i] = 1; else dp[i] = dp[i - 1] + 1; ans = min(ans, (int)(v.size() - dp[i])); } cout << ans << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { unsigned long long int ops = 0; long long int x, y, m; cin >> x >> y >> m; if (x >= m || y >= m) { cout << 0 << endl; return 0; } if (x <= 0 && y <= 0) { cout << -1 << endl; return 0; } long long int mi = min(x, y), ma = max(x, y); long long int dif = ma - mi; ops = dif / ma; if (dif % ma != 0) ops++; mi += ops * ma; swap(mi, ma); while (mi < m && ma < m) { mi += ma; swap(mi, ma); ops++; } cout << ops << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MOD = (int)1e9 + 7; const double EPS = 1e-9; const int INF = INT_MAX; const long long INFLL = (long long)1e18; const double PI = acos(-1.0); template <class T> T gcd(T a, T b) { return b ? gcd(b, a % b) : a; } template <class T> T lcm(T a, T b) { return a / gcd(a, b) * b; } const int N = (int)1e5 + 5; const int P = 1 << 18; int n, m; int a[N]; pair<int, int> g[N]; int use[N]; int main() { ios::sync_with_stdio(false); cout.setf(ios::fixed | ios::showpoint); cout.precision(8); cin >> n >> m; if (n == 1) return !printf( NO n ); for (int i = 0; i < m; i++) { int x, y; cin >> x >> y; a[x]++; a[y]++; g[i] = make_pair(x, y); } int flag = 0; for (int i = 1; i <= n; i++) { if (a[i] < n - 1) { flag = 1; for (int j = 0; j < m; j++) { if (g[j].first == i) { use[g[j].second] = 1; } if (g[j].second == i) { use[g[j].first] = 1; } } int cur; for (int j = 1; j <= n; j++) { if (!use[j] && j != i) { cur = j; break; } } cout << YES n ; int st = 3; for (int j = 1; j <= n; j++) { if (j == i) { cout << 1 ; continue; } if (j == cur) { cout << 2 ; continue; } cout << st << ; st++; } cout << n ; st = 3; for (int j = 1; j <= n; j++) { if (j == i || j == cur) { cout << 1 ; continue; } cout << st << ; st++; } return 0; } } if (!flag) return !printf( NO n ); return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T1, class T2, class T3> bool _IN(T1 x, T2 y, T3 z) { return x <= y && x >= z || x <= z && x >= y; } unsigned long long gcd(unsigned long long a, unsigned long long b) { if (!b) return a; while (b ^= a ^= b ^= a %= b) ; return a; } extern const long long mod; long long ksm(long long a, long long b) { long long res = 1; a %= mod; for (; b; b >>= 1) { if (b & 1) res = res * a % mod; a = a * a % mod; } return res; } char DATaJNTFnlmAoya[2]; double PDlaQLoCkCjCKyr; bool S(char* a) { return scanf( %s , a) == 1; } bool S(int& a) { return scanf( %d , &a) == 1; } bool S(bool& a) { return scanf( %d , &a) == 1; } bool S(unsigned& a) { return scanf( %u , &a) == 1; } bool S(float& a) { return scanf( %f , &a) == 1; } bool S(double& a) { return scanf( %lf , &a) == 1; } bool S(long long& a) { return scanf( %I64d , &a) == 1; } bool S(unsigned long long& a) { return scanf( %I64u , &a) == 1; } bool S(long double& a) { if (scanf( %lf , &PDlaQLoCkCjCKyr) == -1) return 0; a = PDlaQLoCkCjCKyr; return 1; } bool S(char& a) { if (scanf( %1s , DATaJNTFnlmAoya) == -1) return 0; a = *DATaJNTFnlmAoya; return 1; } bool SL(char* a) { a[0] = 0; while (gets(a) && !a[0]) ; return a[0]; } void _P(const int& x) { printf( %d , x); } void _P(const bool& x) { printf( %d , x); } void _P(const unsigned& x) { printf( %u , x); } void _P(const char& x) { printf( %c , x); } void _P(const char* x) { printf( %s , x); } void _P(const string& x) { printf( %s , x.c_str()); } void _P(const long long& x) { printf( %I64d , x); } void _P(const unsigned long long& x) { printf( %I64u , x); } void _P(const float& x) { printf( %.2f , x); } void _P(const double& x) { printf( %.2f , x); } void _P(const long double& x) { printf( %.2f , (double)x); } template <class T1, class T2> bool S(T1& a, T2& b) { return S(a) + S(b) == 2; } template <class T1, class T2, class T3> bool S(T1& a, T2& b, T3& c) { return S(a) + S(b) + S(c) == 3; } template <class T1, class T2, class T3, class T4> bool S(T1& a, T2& b, T3& c, T4& d) { return S(a) + S(b) + S(c) + S(d) == 4; } template <class T1, class T2, class T3, class T4, class T5> bool S(T1& a, T2& b, T3& c, T4& d, T5& e) { return S(a) + S(b) + S(c) + S(d) + S(e) == 5; } template <class T1> void P(const T1& a) { _P(a); putchar( ); } template <class T1, class T2> void P(const T1& a, const T2& b) { _P(a); putchar( ); _P(b); putchar( ); } template <class T1> void PN(const T1& a) { _P(a); puts( ); } template <class T1, class T2> void PN(const T1& a, const T2& b) { _P(a); putchar( ); _P(b); puts( ); } template <class T1, class T2, class T3> void PN(const T1& a, const T2& b, const T3& c) { _P(a); putchar( ); _P(b); putchar( ); _P(c); puts( ); } template <class T1, class T2, class T3, class T4> void PN(const T1& a, const T2& b, const T3& c, const T4& d) { _P(a); putchar( ); _P(b); putchar( ); _P(c); putchar( ); _P(d); puts( ); } template <class T1, class T2, class T3, class T4, class T5> void PN(const T1& a, const T2& b, const T3& c, const T4& d, const T5& e) { _P(a); putchar( ); _P(b); putchar( ); _P(c); putchar( ); _P(d); putchar( ); _P(e); puts( ); } template <class T> void PA(T* a, int n) { for (long long i = 0, pJNwFPtlXiwFoIv = (n - 1); i < pJNwFPtlXiwFoIv; i++) _P(a[i]), putchar( ); PN(a[n - 1]); } template <class T> void PA(const T& x) { for (__typeof((x).begin()) it = (x).begin(), CluhxSchFuDeugk = (x).end(); it != CluhxSchFuDeugk; it++) { _P(*it); if (it == --x.end()) puts( ); else putchar( ); } } int kase; const double pi = 4 * atan(1); const double ep = 1e-9; const int INF = 0x3f3f3f3f; const long long INFL = 0x3f3f3f3f3f3f3f3fll; const long long mod = 1000000007; template <long long mod, long long lim, int MAX_D> struct Hash_set { struct node { string x; node* next; node(node* a = 0, const string& b = ) : next(a), x(b) {} void add(const string& a) { erase(a); next = new node(next, a); } bool find(const string& a) { node* cur = next; while (cur) { if (cur->x == a) return 1; cur = cur->next; } return 0; } void clear() { while (next) { node* tmp = next->next; delete next; next = tmp; } } void erase(const string& a) { node *cur = next, *p = this; while (cur) { if (cur->x == a) { node* tmp = cur; p->next = cur->next; delete cur; cur = p->next; } if (!cur) break; p = cur; cur = cur->next; } } }; long long* d; node* ha; Hash_set() { ha = new node[mod]; d = new long long[MAX_D]; d[0] = 1; for (int i = 1; i < MAX_D; i++) d[i] = d[i - 1] * lim % mod; } ~Hash_set() { for (int i = 0; i < mod; i++) ha[i].clear(); delete[] ha; delete[] d; } long long hash(const string& x) { long long res = 0; for (int i = 0; i < x.size(); i++) res = (res + x[i] * d[i]) % mod; return res; } bool find(const string& x, int h = -1) { if (h == -1) h = hash(x); return ha[h].find(x); } void insert(const string& x, int h = -1) { if (h == -1) h = hash(x); ha[h].add(x); } void erase(const string& x, int h = -1) { if (h == -1) h = hash(x); ha[h].erase(x); } void clear() { for (int i = 0; i < mod; i++) ha[i].clear(); } int convert(long long h, int where, char from, char to) { return ((h + ((long long)to - from) * d[where]) % mod + mod) % mod; } }; char bf[600005]; Hash_set<600011, 311, 600000> x; bool OK() { S(bf); string cur = bf; long long ha = x.hash(cur); for (long long i = 0, pJNwFPtlXiwFoIv = (cur.size()); i < pJNwFPtlXiwFoIv; i++) { char c = cur[i]; for (long long j = ( a ), alVDbhLBoMEGSwA = ( c ); j <= alVDbhLBoMEGSwA; j++) { if (j == c) continue; cur[i] = j; long long ch = x.convert(ha, i, c, j); if (x.find(cur, ch)) return 1; } cur[i] = c; } return 0; } int main() { ; int n, m; S(n, m); while (n--) { S(bf); x.insert(bf); } while (m--) { puts(OK() ? YES : NO ); } } |
#include <bits/stdc++.h> using namespace std; vector<long long> a; struct SegTree { struct Node { long long left, right, mid, size; }; Node combine(const Node& A, const Node& B, long long m) { Node C; if (A.left < A.size) { C.left = A.left; } else { if ((a[m - 1] > 0) <= (a[m] > 0)) { C.left = A.size + B.left; } else { C.left = A.size; } } if (B.right < B.size) { C.right = B.right; } else { if ((a[m - 1] > 0) <= (a[m] > 0)) { C.right = B.size + A.right; } else { C.right = B.size; } } C.mid = max(A.mid, B.mid); if ((a[m - 1] > 0) <= (a[m] > 0)) { C.mid = max(C.mid, A.right + B.left); } C.size = A.size + B.size; return C; } long long size; vector<Node> t; void init(long long n) { size = n; t.resize(4 * size); } void build(long long x, long long lx, long long rx) { if (lx + 1 == rx) { if (a[lx] == 0) { t[x] = {0, 0, 0, 1}; } else { t[x] = {1, 1, 1, 1}; } } else { long long m = (lx + rx) / 2; build(2 * x + 1, lx, m); build(2 * x + 2, m, rx); t[x] = combine(t[2 * x + 1], t[2 * x + 2], m); } } void build(long long n) { init(n); build(0, 0, size); } void set(long long v, long long x, long long lx, long long rx) { if (lx + 1 == rx) { if (a[lx] == 0) { t[x] = {0, 0, 0, 1}; } else { t[x] = {1, 1, 1, 1}; } } else { long long m = (lx + rx) / 2; if (v < m) { set(v, 2 * x + 1, lx, m); } else { set(v, 2 * x + 2, m, rx); } t[x] = combine(t[2 * x + 1], t[2 * x + 2], m); } } void set(long long v) { set(v, 0, 0, size); } }; void solve() { long long Q; Q = 1; while (Q--) { long long n; cin >> n; vector<long long> b(n); for (long long i = 0; i < n; ++i) cin >> b[i]; ; a.resize(n - 1); for (long long i = 0; i < n - 1; ++i) { a[i] = b[i] - b[i + 1]; } SegTree tree; if (a.size() != 0) { tree.build(a.size()); } long long m; cin >> m; while (m--) { long long l, r, d; cin >> l >> r >> d; --l, --r; if (a.size() == 0) { cout << 1 << ; continue; } if (l > 0) { a[l - 1] -= d; tree.set(l - 1); } if (r < a.size()) { a[r] += d; tree.set(r); } cout << tree.t[0].mid + 1 << ; } } } signed main(signed argc, char** argv) { ios_base::sync_with_stdio(false); cin.tie(nullptr); if (argc > 1 && (string)argv[1] == local ) { freopen( input.txt , r , stdin); freopen( output.txt , w , stdout); solve(); while (cin.peek() != EOF) { if (isspace(cin.peek())) cin.get(); else { cout << n ; solve(); } } } else { solve(); } } |
module IDELAYE2 (/*AUTOARG*/
// Outputs
CNTVALUEOUT, DATAOUT,
// Inputs
C, CE, CINVCTRL, CNTVALUEIN, DATAIN, IDATAIN, INC, LD, LDPIPEEN,
REGRST
);
parameter CINVCTRL_SEL = "FALSE"; // Enable dynamic clock inversion
parameter DELAY_SRC = "IDATAIN"; // Delay input
parameter HIGH_PERFORMANCE_MODE = "FALSE"; // Reduced jitter
parameter IDELAY_TYPE = "FIXED"; // Type of delay line
parameter integer IDELAY_VALUE = 0; // Input delay tap setting
parameter [0:0] IS_C_INVERTED = 1'b0; //
parameter [0:0] IS_DATAIN_INVERTED = 1'b0; //
parameter [0:0] IS_IDATAIN_INVERTED = 1'b0; //
parameter PIPE_SEL = "FALSE"; // Select pipelined mode
parameter real REFCLK_FREQUENCY = 200.0; // Ref clock frequency
parameter SIGNAL_PATTERN = "DATA"; // Input signal type
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
parameter integer SIM_DELAY_D = 0;
localparam DELAY_D = (IDELAY_TYPE == "VARIABLE") ? SIM_DELAY_D : 0;
`endif // ifdef XIL_TIMING
`ifndef XIL_TIMING
integer DELAY_D=0;
`endif // ifndef XIL_TIMING
output [4:0] CNTVALUEOUT; // count value for monitoring tap value
output DATAOUT; // delayed data
input C; // clock input for variable mode
input CE; // enable increment/decrement function
input CINVCTRL; // dynamically inverts clock polarity
input [4:0] CNTVALUEIN; // counter value for tap delay
input DATAIN; // data input from FGPA logic
input IDATAIN; // data input from IBUF
input INC; // increment tap delay
input LD; // loads the delay primitive
input LDPIPEEN; // enables the pipeline register delay
input REGRST; // reset for pipeline register
assign DATAOUT = IDATAIN;
initial
begin
$display("Delay %d %m",IDELAY_VALUE);
end
endmodule // IDELAYE2
|
//======================================================================
//
// cmac_core.v
// -----------
// CMAC based on AES. Support for 128 and 256 bit keys. Generates
// 128 bit MAC. The core is compatible with NIST SP 800-38 B and
// as used in RFC 4493.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2018, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module cmac_core(
input wire clk,
input wire reset_n,
input wire [255 : 0] key,
input wire keylen,
input wire [7 : 0] final_size,
input wire init,
input wire next,
input wire finalize,
input wire [127 : 0] block,
output wire [127 : 0] result,
output wire ready,
output wire valid
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam BMUX_ZERO = 0;
localparam BMUX_MESSAGE = 1;
localparam BMUX_TWEAK = 2;
localparam CTRL_IDLE = 0;
localparam CTRL_INIT_CORE = 1;
localparam CTRL_GEN_SUBKEYS = 2;
localparam CTRL_NEXT_BLOCK = 3;
localparam CTRL_FINAL_BLOCK = 4;
localparam R128 = {120'h0, 8'b10000111};
localparam AES_BLOCK_SIZE = 128;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [127 : 0] result_reg;
reg [127 : 0] result_new;
reg result_we;
reg reset_result_reg;
reg update_result_reg;
reg valid_reg;
reg valid_new;
reg valid_we;
reg ready_reg;
reg ready_new;
reg ready_we;
reg [127 : 0] k1_reg;
reg [127 : 0] k1_new;
reg [127 : 0] k2_reg;
reg [127 : 0] k2_new;
reg k1_k2_we;
reg [3 : 0] cmac_ctrl_reg;
reg [3 : 0] cmac_ctrl_new;
reg cmac_ctrl_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg aes_init;
reg aes_next;
wire aes_encdec;
wire aes_ready;
reg [127 : 0] aes_block;
wire [127 : 0] aes_result;
wire aes_valid; // Just to not have a dangling port.
reg [1 : 0] bmux_ctrl;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign aes_encdec = 1'h1;
assign result = result_reg;
assign ready = ready_reg;
assign valid = valid_reg;
//----------------------------------------------------------------
// AES core instantiation.
//----------------------------------------------------------------
aes_core aes_inst(
.clk(clk),
.reset_n(reset_n),
.encdec(aes_encdec),
.init(aes_init),
.next(aes_next),
.ready(aes_ready),
.key(key),
.keylen(keylen),
.block(aes_block),
.result(aes_result),
.result_valid(aes_valid)
);
//----------------------------------------------------------------
// reg_update
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin : reg_update
if (!reset_n)
begin
k1_reg <= 128'h0;
k2_reg <= 128'h0;
result_reg <= 128'h0;
valid_reg <= 1'h0;
ready_reg <= 1'h1;
cmac_ctrl_reg <= CTRL_IDLE;
end
else
begin
if (result_we)
result_reg <= result_new;
if (ready_we)
ready_reg <= ready_new;
if (valid_we)
valid_reg <= valid_new;
if (k1_k2_we)
begin
k1_reg <= k1_new;
k2_reg <= k2_new;
end
if (cmac_ctrl_we)
cmac_ctrl_reg <= cmac_ctrl_new;
end
end // reg_update
//----------------------------------------------------------------
// cmac_datapath
//
// The cmac datapath. Basically a mux for the input data block
// to the AES core and some gates for the logic.
//----------------------------------------------------------------
always @*
begin : cmac_datapath
reg [127 : 0] mask;
reg [127 : 0] masked_block;
reg [127 : 0] padded_block;
reg [127 : 0] tweaked_block;
result_new = 128'h0;
result_we = 0;
// Handle result reg updates and clear
if (reset_result_reg)
result_we = 1'h1;
if (update_result_reg)
begin
result_new = aes_result;
result_we = 1'h1;
end
// Generation of subkey k1 and k2.
k1_new = {aes_result[126 : 0], 1'b0};
if (aes_result[127])
k1_new = k1_new ^ R128;
k2_new = {k1_new[126 : 0], 1'b0};
if (k1_new[127])
k2_new = k2_new ^ R128;
// Padding of final block. We create a mask that preserves
// the data in the block and zeroises all other bits.
// We add a one to bit at the first non-data position.
mask = 128'b0;
if (final_size[0])
mask = {1'b1, mask[127 : 1]};
if (final_size[1])
mask = {2'h3, mask[127 : 2]};
if (final_size[2])
mask = {4'hf, mask[127 : 4]};
if (final_size[3])
mask = {8'hff, mask[127 : 8]};
if (final_size[4])
mask = {16'hffff, mask[127 : 16]};
if (final_size[5])
mask = {32'hffffffff, mask[127 : 32]};
if (final_size[6])
mask = {64'hffffffff_ffffffff, mask[127 : 64]};
masked_block = block & mask;
padded_block = masked_block;
padded_block[(127 - final_size[6 : 0])] = 1'b1;
// Tweak of final block. Based on if the final block is full or not.
if (final_size == AES_BLOCK_SIZE)
tweaked_block = k1_reg ^ block;
else
tweaked_block = k2_reg ^ padded_block;
// Input mux for the AES core.
case (bmux_ctrl)
BMUX_ZERO:
aes_block = 128'h0;
BMUX_MESSAGE:
aes_block = result_reg ^ block;
BMUX_TWEAK:
aes_block = result_reg ^ tweaked_block;
default:
aes_block = 128'h0;
endcase // case (bmux_ctrl)
end
//----------------------------------------------------------------
// cmac_ctrl
//
// The FSM controlling the cmac functionality.
//----------------------------------------------------------------
always @*
begin : cmac_ctrl
aes_init = 1'h0;
aes_next = 1'h0;
bmux_ctrl = BMUX_ZERO;
reset_result_reg = 1'h0;
update_result_reg = 1'h0;
k1_k2_we = 1'h0;
ready_new = 1'h0;
ready_we = 1'h0;
valid_new = 1'h0;
valid_we = 1'h0;
cmac_ctrl_new = CTRL_IDLE;
cmac_ctrl_we = 1'h0;
case (cmac_ctrl_reg)
CTRL_IDLE:
begin
if (init)
begin
ready_new = 1'h0;
ready_we = 1'h1;
valid_new = 1'h0;
valid_we = 1'h1;
aes_init = 1'h1;
reset_result_reg = 1'h1;
cmac_ctrl_new = CTRL_INIT_CORE;
cmac_ctrl_we = 1'h1;
end
if (next)
begin
ready_new = 1'h0;
ready_we = 1'h1;
aes_next = 1'h1;
bmux_ctrl = BMUX_MESSAGE;
cmac_ctrl_new = CTRL_NEXT_BLOCK;
cmac_ctrl_we = 1'h1;
end
if (finalize)
begin
ready_new = 1'h0;
ready_we = 1'h1;
aes_next = 1'h1;
bmux_ctrl = BMUX_TWEAK;
cmac_ctrl_new = CTRL_FINAL_BLOCK;
cmac_ctrl_we = 1'h1;
end
end
CTRL_INIT_CORE:
begin
if (aes_ready)
begin
aes_next = 1'h1;
bmux_ctrl = BMUX_ZERO;
cmac_ctrl_new = CTRL_GEN_SUBKEYS;
cmac_ctrl_we = 1'h1;
end
end
CTRL_GEN_SUBKEYS:
begin
if (aes_ready)
begin
ready_new = 1'h1;
ready_we = 1'h1;
k1_k2_we = 1'h1;
cmac_ctrl_new = CTRL_IDLE;
cmac_ctrl_we = 1'h1;
end
end
CTRL_NEXT_BLOCK:
begin
bmux_ctrl = BMUX_MESSAGE;
if (aes_ready)
begin
update_result_reg = 1'h1;
ready_new = 1'h1;
ready_we = 1'h1;
cmac_ctrl_new = CTRL_IDLE;
cmac_ctrl_we = 1'h1;
end
end
CTRL_FINAL_BLOCK:
begin
bmux_ctrl = BMUX_TWEAK;
if (aes_ready)
begin
update_result_reg = 1'h1;
valid_new = 1'h1;
valid_we = 1'h1;
ready_new = 1'h1;
ready_we = 1'h1;
cmac_ctrl_new = CTRL_IDLE;
cmac_ctrl_we = 1'h1;
end
end
default:
begin
end
endcase // case (cmac_ctrl_reg)
end
endmodule // cmac_core
//======================================================================
// EOF cmac_core.v
//======================================================================
|
#include <bits/stdc++.h> using namespace std; int arr[4], sum; string s; int main() { cin >> arr[0] >> arr[1] >> arr[2] >> arr[3] >> s; for (int i = 0; i < s.size(); i++) { sum += arr[s[i] - 49]; } cout << sum; } |
#include <bits/stdc++.h> using namespace std; int main() { long long n, m, h; cin >> n >> m >> h; long long r[n], c[m], a[n][m]; for (long long i = 0; i < m; i++) { cin >> c[i]; } for (int i = 0; i < n; i++) { cin >> r[i]; } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> a[i][j]; } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (r[i] == c[j] && a[i][j] == 1) { a[i][j] = r[i]; } } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (a[i][j] == 1) { a[i][j] = min(r[i], c[j]); } } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cout << a[i][j] << ; } cout << endl; } return 0; } |
// megafunction wizard: %ROM: 2-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: cm_rom_shared.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.1 Build 197 01/19/2011 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module cm_rom_shared (
address_a,
address_b,
clock,
q_a,
q_b);
input [8:0] address_a;
input [8:0] address_b;
input clock;
output [3:0] q_a;
output [3:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "1"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: ECC NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "2048"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./sources_ngnp_multicore/src/output_CM_final.mif"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "4"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "4"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "4"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "4"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: INIT_FILE STRING "./sources_ngnp_multicore/src/output_CM_final.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "512"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "9"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "4"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "4"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: USED_PORT: address_a 0 0 9 0 INPUT NODEFVAL "address_a[8..0]"
// Retrieval info: USED_PORT: address_b 0 0 9 0 INPUT NODEFVAL "address_b[8..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q_a 0 0 4 0 OUTPUT NODEFVAL "q_a[3..0]"
// Retrieval info: USED_PORT: q_b 0 0 4 0 OUTPUT NODEFVAL "q_b[3..0]"
// Retrieval info: CONNECT: @address_a 0 0 9 0 address_a 0 0 9 0
// Retrieval info: CONNECT: @address_b 0 0 9 0 address_b 0 0 9 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 4 0 GND 0 0 4 0
// Retrieval info: CONNECT: @data_b 0 0 4 0 GND 0 0 4 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 GND 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 GND 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 4 0 @q_a 0 0 4 0
// Retrieval info: CONNECT: q_b 0 0 4 0 @q_b 0 0 4 0
// Retrieval info: GEN_FILE: TYPE_NORMAL cm_rom_shared.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL cm_rom_shared.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cm_rom_shared.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cm_rom_shared.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cm_rom_shared_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL cm_rom_shared_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; inline long long rd() { long long x = 0; bool f = 0; char c = getchar(); while (!isdigit(c)) { if (c == - ) f = 1; c = getchar(); } while (isdigit(c)) { x = (x << 1) + (x << 3) + (c ^ 48); c = getchar(); } return f ? -x : x; } long long n, m, l[1000010 << 1], f[1000010 << 1], hd[1000010]; int main() { n = rd(); m = rd(); for (register long long i = 1; i <= n; ++i) l[i] = l[n + i] = rd(); for (register long long i = 1; i <= (n << 1); ++i) l[i] += l[i - 1]; while (m--) { long long ptr = 0, len = rd(); for (register long long i = n + 1; i <= (n << 1); ++i) { while (l[i] - l[ptr] > len) ++ptr; f[i] = f[ptr] + 1; hd[i - n] = (i == ptr ? i : (ptr <= n ? ptr : hd[ptr - n])); if (i - hd[i - n] >= n) { printf( %I64d n , f[i]); break; } } } return 0; } |
/*
Copyright (c) 2020 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* LED shift register driver
*/
module led_sreg_driver #(
// number of LEDs
parameter COUNT = 8,
// invert output
parameter INVERT = 0,
// clock prescale
parameter PRESCALE = 31
)
(
input wire clk,
input wire rst,
input wire [COUNT-1:0] led,
output wire sreg_d,
output wire sreg_ld,
output wire sreg_clk
);
localparam CL_COUNT = $clog2(COUNT+1);
localparam CL_PRESCALE = $clog2(PRESCALE+1);
reg [CL_COUNT-1:0] count_reg = 0;
reg [CL_PRESCALE-1:0] prescale_count_reg = 0;
reg enable_reg = 1'b0;
reg update_reg = 1'b1;
reg cycle_reg = 1'b0;
reg [COUNT-1:0] led_sync_reg_1 = 0;
reg [COUNT-1:0] led_sync_reg_2 = 0;
reg [COUNT-1:0] led_reg = 0;
reg sreg_d_reg = 1'b0;
reg sreg_ld_reg = 1'b0;
reg sreg_clk_reg = 1'b0;
assign sreg_d = INVERT ? !sreg_d_reg : sreg_d_reg;
assign sreg_ld = sreg_ld_reg;
assign sreg_clk = sreg_clk_reg;
always @(posedge clk) begin
led_sync_reg_1 <= led;
led_sync_reg_2 <= led_sync_reg_1;
enable_reg <= 1'b0;
if (prescale_count_reg) begin
prescale_count_reg <= prescale_count_reg - 1;
end else begin
enable_reg <= 1'b1;
prescale_count_reg <= PRESCALE;
end
if (enable_reg) begin
if (cycle_reg) begin
cycle_reg <= 1'b0;
sreg_clk_reg <= 1'b1;
end else if (count_reg) begin
sreg_clk_reg <= 1'b0;
sreg_ld_reg <= 1'b0;
if (count_reg < COUNT) begin
count_reg <= count_reg + 1;
cycle_reg <= 1'b1;
sreg_d_reg <= led_reg[count_reg];
end else begin
count_reg <= 0;
cycle_reg <= 1'b0;
sreg_d_reg <= 1'b0;
sreg_ld_reg <= 1'b1;
end
end else begin
sreg_clk_reg <= 1'b0;
sreg_ld_reg <= 1'b0;
if (update_reg) begin
update_reg <= 1'b0;
count_reg <= 1;
cycle_reg <= 1'b1;
sreg_d_reg <= led_reg[0];
end
end
end
if (led_sync_reg_2 != led_reg) begin
led_reg <= led_sync_reg_2;
update_reg <= 1'b1;
end
if (rst) begin
count_reg <= 0;
prescale_count_reg <= 0;
enable_reg <= 1'b0;
update_reg <= 1'b1;
cycle_reg <= 1'b0;
led_reg <= 0;
sreg_d_reg <= 1'b0;
sreg_ld_reg <= 1'b0;
sreg_clk_reg <= 1'b0;
end
end
endmodule
`resetall
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: fpu_rptr_min_global.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// global (bufrpt_grp4 used to buffer rst_l, scan signals) and mintiming buffers in this file
// fpu_bufrpt_grp4: 4 bit wide to fix max trans time for scan, reset
module fpu_bufrpt_grp4 (
in,
out
);
input [3:0] in;
output [3:0] out;
assign out[3:0] = in[3:0];
endmodule
// fpu_rptr_fp_cpx_grp16: 16 bit wide vertical MSB top mintiming buffer for fp_cpx*
module fpu_rptr_fp_cpx_grp16 (
in,
out
);
input [15:0] in;
output [15:0] out;
assign out[15:0] = in[15:0];
endmodule
// fpu_rptr_pcx_fpio_grp16: 16 bit wide mintming vertical buffer, MSB top, for pcx_fpio*
// use minbuf_5x -> buf_5x -> buf_30x
module fpu_rptr_pcx_fpio_grp16 (
in,
out
);
input [15:0] in;
output [15:0] out;
assign out[15:0] = in[15:0];
endmodule
// fpu_rptr_inq: 156 bits wide mintiming buffer for inq_sram din (matched to inq_sram bit order)
module fpu_rptr_inq (
in,
out
);
input [155:0] in;
output [155:0] out;
assign out[155:0] = in[155:0];
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build Mon Oct 10 19:07:27 MDT 2016
// Date : Tue Sep 19 16:52:31 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_0_stub.v
// Design : ila_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ila,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5,
probe6)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[3:0],probe6[3:0]" */;
input clk;
input [63:0]probe0;
input [63:0]probe1;
input [0:0]probe2;
input [0:0]probe3;
input [0:0]probe4;
input [3:0]probe5;
input [3:0]probe6;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, sum = 0; cin >> n; sum = n; for (int i = 2; i <= n; i++) { while (n % i == 0) { sum += n / i; n /= i; } } cout << sum << endl; return 0; } |
//
// `aclass.v'
// Asynchronous class tech. cell description
//
// 2013 Shin'ya Ueoka
`define gate_delay 0.090
// VCC and GND
module VCC (Z);
output Z;
supply1 vdd;
assign Z= vdd;
endmodule
module GND (Z);
output Z;
supply0 gnd;
assign Z = gnd;
endmodule
// Combinational Gates
module AN2(Z,A,B);
input A,B;
output Z;
and #(`gate_delay, `gate_delay) (Z,A,B);
endmodule
module AN3(Z,A,B,C);
input A,B,C;
output Z;
and #(`gate_delay, `gate_delay) (Z,A,B,C);
endmodule
module AN4(Z,A,B,C,D);
input A,B,C,D;
output Z;
and #(`gate_delay, `gate_delay) (Z,A,B,C,D);
endmodule
module OR2(Z,A,B);
input A,B;
output Z;
or #(`gate_delay, `gate_delay) (Z,A,B);
endmodule
module OR3(Z,A,B,C);
input A,B,C;
output Z;
or #(`gate_delay, `gate_delay) (Z,A,B,C);
endmodule
module OR4(Z,A,B,C,D);
input A,B,C,D;
output Z;
or #(`gate_delay, `gate_delay) (Z,A,B,C,D);
endmodule
module IV(Z,A);
input A;
output Z;
not #(`gate_delay, `gate_delay) (Z,A);
endmodule
module ND2(Z,A,B);
input A,B;
output Z;
nand #(`gate_delay, `gate_delay) (Z,A,B);
endmodule
module ND3(Z,A,B,C);
input A,B,C;
output Z;
nand #(`gate_delay, `gate_delay) (Z,A,B,C);
endmodule
module ND4(Z,A,B,C,D);
input A,B,C,D;
output Z;
nand #(`gate_delay, `gate_delay) (Z,A,B,C,D);
endmodule
module NR2(Z,A,B);
input A,B;
output Z;
nor #(`gate_delay, `gate_delay) (Z,A,B);
endmodule
module NR3(Z,A,B,C);
input A,B,C;
output Z;
nor #(`gate_delay, `gate_delay) (Z,A,B,C);
endmodule
module NR4(Z,A,B,C,D);
input A,B,C,D;
output Z;
nor #(`gate_delay, `gate_delay) (Z,A,B,C,D);
endmodule
module EN(Z,A,B);
input A,B;
output Z;
xnor #(`gate_delay, `gate_delay) (Z,A,B);
endmodule
module EN3(Z,A,B,C);
input A,B,C;
output Z;
xnor #(`gate_delay, `gate_delay) (Z,A,B,C);
endmodule
module EO(Z,A,B);
input A,B;
output Z;
xor #(`gate_delay, `gate_delay) (Z,A,B);
endmodule
module EO3(Z,A,B,C);
input A,B,C;
output Z;
xor #(`gate_delay, `gate_delay) (Z,A,B,C);
endmodule
module IBUF1(Z,A);
output Z;
input A;
buf #(`gate_delay, `gate_delay) (Z,A);
endmodule
// Sequencial Gates
module LD1(D, G, Q, QN);
output Q, QN;
input D, G;
p_latch #(`gate_delay, `gate_delay) latch (Q,G,D);
not (QN,Q);
endmodule
primitive p_latch(q,g,d);
output q;
reg q;
input g,d;
table
// g d : present q : next q
1 0 : ? : 0;
1 1 : ? : 1;
0 ? : ? : -;
x 0 : 0 : 0;
x 1 : 1 : 1;
endtable
endprimitive
module C2 (Z, A, B);
output Z;
input A, B;
p_c2 #(`gate_delay, `gate_delay) (Z, A, B);
endmodule
primitive p_c2 (out, in0, in1);
output out;
input in0, in1;
reg out;
table
//in0 in1 : out' : out
0 0 : ? : 0 ;
0 ? : 0 : 0 ;
? 0 : 0 : 0 ;
? 1 : 1 : 1 ;
1 ? : 1 : 1 ;
1 1 : ? : 1 ;
x x : x : x ;
endtable
endprimitive
module C3 (Z, A, B, C);
output Z;
input A, B, C;
p_c3 #(`gate_delay, `gate_delay) (Z, A, B, C);
endmodule
primitive p_c3 (out, in0, in1, in2);
output out;
input in0, in1, in2;
reg out;
table
//in0 in1 in2 : out' : out
0 0 0 : ? : 0 ;
0 ? ? : 0 : 0 ;
? 0 ? : 0 : 0 ;
? ? 0 : 0 : 0 ;
1 ? ? : 1 : 1 ;
? 1 ? : 1 : 1 ;
? ? 1 : 1 : 1 ;
1 1 1 : ? : 1 ;
x x x : x : x ;
endtable
endprimitive
module C2R (Z, A, B, reset);
output Z;
input A, B;
input reset;
p_c2r #(`gate_delay, `gate_delay) U0 (Z, A, B, reset);
endmodule
primitive p_c2r(Q, A, B, reset);
output Q;
input A, B, reset;
reg Q;
table
//A B reset : Q' : Q
0 0 0 : ? : 0 ;
0 ? 0 : 0 : 0 ;
? 0 0 : 0 : 0 ;
? 1 0 : 1 : 1 ;
1 ? 0 : 1 : 1 ;
1 1 0 : ? : 1 ;
? ? 1 : ? : 0 ;
x x x : x : x ;
endtable
endprimitive
module p_ao22 (q, i0, i1, i2, i3);
output q;
input i0;
input i1;
input i2;
input i3;
wire [1:0] int_0n;
OR2 I0 (q, int_0n[0], int_0n[1]);
AN2 I1 (int_0n[1], i2, i3);
AN2 I2 (int_0n[0], i0, i1);
endmodule
module p_aoi22 (q, i0, i1, i2, i3);
output q;
input i0;
input i1;
input i2;
input i3;
wire [1:0] int_0n;
NR2 I0 (q, int_0n[0], int_0n[1]);
AN2 I1 (int_0n[1], i2, i3);
AN2 I2 (int_0n[0], i0, i1);
endmodule
module ACU0D1 (Z, A, B);
output Z;
input A, B;
wire int_0n;
OR2 I0 (Z, A, int_0n);
AN2 I1 (int_0n, B, Z);
endmodule
module NC2 (Q, A, B);
output Q;
input A, B;
wire nq_0n;
p_aoi222 I0 (Q, A, B, A, nq_0n, B, nq_0n);
IV I1 (nq_0n, Q);
endmodule
module p_aoi222(q, a, b, c, d, e, f);
output q;
input a, b, c, d, e, f;
wire [1:0] internal_0n;
wire [2:0] int_0n;
AN2 I0 (q, internal_0n[0], internal_0n[1]);
IV I1 (internal_0n[1], int_0n[2]);
NR2 I2 (internal_0n[0], int_0n[0], int_0n[1]);
AN2 I3 (int_0n[2], e, f);
AN2 I4 (int_0n[1], c, d);
AN2 I5 (int_0n[0], a, b);
endmodule
module NC2P (Z, A, B);
output Z;
input A, B;
wire nq_0n;
p_aoi22 I0 (Z, A, B, A, nq_0n);
IV I1 (nq_0n, Z);
endmodule
module SRFF (S, R, Q, NQ);
input S, R;
output Q, NQ;
NR2 I0 (NQ, Q, S);
NR2 O1 (Q, NQ, R);
endmodule
module AC2(Z, A, B);
input A, B;
output Z;
p_ao22 I0 (Z, A, B, A, Z);
endmodule
module AC3U12 (Z, A, B, C);
output Z;
input A, B, C;
wire [1:0] internal_0n;
wire [1:0] int_0n;
OR2 I0 (Z, int_0n[0], int_0n[1]);
AN2 I1 (int_0n[1], A, Z);
NR2 I2 (int_0n[0], internal_0n[0], internal_0n[1]);
IV I3 (internal_0n[1], C);
ND2 I4 (internal_0n[0], A, B);
endmodule
|
`include "bsg_mem_3r1w_sync_macros.vh"
module bsg_mem_3r1w_sync #( parameter `BSG_INV_PARAM(width_p )
, parameter `BSG_INV_PARAM(els_p )
, parameter read_write_same_addr_p = 0
, parameter addr_width_lp = `BSG_SAFE_CLOG2(els_p)
, parameter harden_p = 1
)
( input clk_i
, input reset_i
, input w_v_i
, input [addr_width_lp-1:0] w_addr_i
, input [width_p-1:0] w_data_i
, input r0_v_i
, input [addr_width_lp-1:0] r0_addr_i
, output logic [width_p-1:0] r0_data_o
, input r1_v_i
, input [addr_width_lp-1:0] r1_addr_i
, output logic [width_p-1:0] r1_data_o
, input r2_v_i
, input [addr_width_lp-1:0] r2_addr_i
, output logic [width_p-1:0] r2_data_o
);
wire unused = reset_i;
// TODO: Define more hardened macro configs here
`bsg_mem_3r1w_sync_macro(32,64,1) else
//`bsg_mem_3r1w_sync_macro(32,32,2) else
// no hardened version found
begin: notmacro
bsg_mem_3r1w_sync_synth #(.width_p(width_p), .els_p(els_p), .read_write_same_addr_p(read_write_same_addr_p))
synth
(.*);
end // block: notmacro
//synopsys translate_off
always_ff @(negedge clk_i)
if (w_v_i)
begin
assert (w_addr_i < els_p)
else $error("Invalid address %x to %m of size %x\n", w_addr_i, els_p);
assert (~(r0_addr_i == w_addr_i && r0_v_i && !read_write_same_addr_p))
else $error("%m: port 0 Attempt to read and write same address");
assert (~(r1_addr_i == w_addr_i && r1_v_i && !read_write_same_addr_p))
else $error("%m: port 1 Attempt to read and write same address");
assert (~(r2_addr_i == w_addr_i && r2_v_i && !read_write_same_addr_p))
else $error("%m: port 2 Attempt to read and write same address");
end
initial
begin
$display("## %L: instantiating width_p=%d, els_p=%d, read_write_same_addr_p=%d, harden_p=%d (%m)",width_p,els_p,read_write_same_addr_p,harden_p);
end
//synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_3r1w_sync)
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: sfifo_14x16.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sfifo_14x16 (
aclr,
clock,
data,
rdreq,
wrreq,
almost_full,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [13:0] data;
input rdreq;
input wrreq;
output almost_full;
output empty;
output full;
output [13:0] q;
output [3:0] usedw;
wire [3:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [13:0] sub_wire3;
wire sub_wire4;
wire [3:0] usedw = sub_wire0[3:0];
wire empty = sub_wire1;
wire full = sub_wire2;
wire [13:0] q = sub_wire3[13:0];
wire almost_full = sub_wire4;
scfifo scfifo_component (
.clock (clock),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.usedw (sub_wire0),
.empty (sub_wire1),
.full (sub_wire2),
.q (sub_wire3),
.almost_full (sub_wire4),
.almost_empty (),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.almost_full_value = 12,
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_numwords = 16,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 14,
scfifo_component.lpm_widthu = 4,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "12"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "16"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "14"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "14"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "12"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "14"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL "almost_full"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 14 0 INPUT NODEFVAL "data[13..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 14 0 OUTPUT NODEFVAL "q[13..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: usedw 0 0 4 0 OUTPUT NODEFVAL "usedw[3..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 14 0 data 0 0 14 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 14 0 @q 0 0 14 0
// Retrieval info: CONNECT: usedw 0 0 4 0 @usedw 0 0 4 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_14x16.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_14x16.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_14x16.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_14x16.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_14x16_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_14x16_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR4_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__NOR4_FUNCTIONAL_PP_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__nor4 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , A, B, C, D );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR4_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; double n, l, v1, v2, k; bool c(double x) { int num; if ((int)n % (int)k == 0) num = n / k; else num = n / k + 1; if (num * x + (num - 1) * x * (v2 - v1) / (v2 + v1) <= x + (l - x * v2) / v1) return 1; return 0; } int main() { scanf( %lf%lf%lf%lf%lf , &n, &l, &v1, &v2, &k); double lb = 0, rb = 1000000001; for (int i = 0; i < 100; i++) { double m = (lb + rb) / 2; if (c(m)) lb = m; else rb = m; } printf( %lf , rb + (l - rb * v2) / v1); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long N = 1000006, MOD = 1e9 + 7, INF = 1e16; long long a[N], b, n, m, k, g[105][105], q, x, ans, Ans, pre[N], l, r; string s; pair<int, int> p[N]; int main() { ios_base::sync_with_stdio(false), cin.tie(0); cin >> n >> m; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) cin >> g[i][j]; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) if (g[i][j] < 1) x = 1; while (!x) { Ans++; q += min(n, m); for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { g[i][j]--; if (g[i][j] < 1) x = 1; } } ans = 0; x = 0; for (int i = 1; i <= n; i++) if (!g[i][1]) x = 1; while (!x) { ans++, r++; for (int i = 1; i <= n; i++) { g[i][1]--; if (!g[i][1]) x = 1; } } x = 0; for (int i = 1; i <= m; i++) if (!g[1][i]) x = 1; while (!x) { ans++, l++; for (int i = 1; i <= m; i++) { g[1][i]--; if (!g[1][i]) x = 1; } } for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) if (g[i][j] != g[1][j] + g[i][1]) { cout << -1; return 0; } for (int i = 1; i <= n; i++) ans += g[i][1]; for (int i = 2; i <= m; i++) ans += g[1][i]; cout << ans + q << endl; for (int i = 1; i <= l; i++) cout << row << << 1 << endl; for (int i = 1; i <= r; i++) cout << col << << 1 << endl; for (int i = 1; i <= n; i++) for (int u = 1; u <= g[i][1]; u++) cout << row << << i << endl; for (int i = 1; i <= m; i++) for (int u = 1; u <= g[1][i]; u++) cout << col << << i << endl; if (n < m) s = row ; else s = col ; for (int i = 0; i < min(n, m) * Ans; i++) cout << s << << i % min(n, m) + 1 << endl; } |
#include <bits/stdc++.h> using namespace std; vector<pair<int, int> > v[100005]; bool visit[100005]; int n; vector<int> ans; bool dfs(int i, int last) { visit[i] = true; bool flag = false; for (int j = 0; j < v[i].size(); j++) { if (!visit[v[i][j].first]) { if (v[i][j].second == 2) flag = flag | dfs(v[i][j].first, v[i][j].first); else flag = flag | dfs(v[i][j].first, 0); } } if (flag == false && last != 0) { flag = true; ans.push_back(i); } return flag; } void Readinput() { int i, x, y, t; scanf( %d , &n); for (i = 0; i < n - 1; i++) { scanf( %d , &x); scanf( %d , &y); scanf( %d , &t); v[x].push_back(pair<int, int>(y, t)); v[y].push_back(pair<int, int>(x, t)); } } void solve() { int i, j; dfs(1, 0); cout << ans.size() << endl; for (i = 0; i < ans.size(); i++) cout << ans[i] << ; cout << endl; } int main() { memset(visit, false, sizeof(visit)); Readinput(); solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m; int p[2 * 100001], rnk[2 * 100001]; int cnt[2 * 100001]; long long pref[2 * 100001 + 5]; long long ans[2 * 100001 + 5]; vector<pair<int, int> > q; struct Edge { int a, b; int w; Edge(int a, int b, int w) : a(a), b(b), w(w) {} }; vector<Edge> e; bool comp(const Edge &one, const Edge &two) { return one.w < two.w; } void init() { pref[0] = 0; for (int i = 1; i <= 2 * 100001; ++i) pref[i] = pref[i - 1] + (i - 1); } void dsu_init() { for (int i = 0; i < 2 * 100001; ++i) { p[i] = i; rnk[i] = 0; cnt[i] = 1; } } int dsu_find(int v) { if (p[v] == v) return v; return p[v] = dsu_find(p[v]); } int dsu_meld(int a, int b, int &prev) { a = dsu_find(a), b = dsu_find(b); if (a == b) return 0; if (rnk[a] < rnk[b]) swap(a, b); p[b] = a; cnt[a] += cnt[b]; prev = cnt[b]; if (rnk[a] == rnk[b]) ++rnk[a]; return cnt[a]; } int main() { cin.sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); init(); dsu_init(); cin >> n >> m; int a, b, w; for (int i = 0; i < n - 1; ++i) { cin >> a >> b >> w; --a, --b; e.emplace_back(a, b, w); } sort(e.begin(), e.end(), comp); for (int i = 0; i < m; ++i) { cin >> a; q.push_back({a, i}); } sort(q.begin(), q.end()); long long sum = 0; int bnd = 0; int prev, now; for (int i = 0; i < q.size(); ++i) { for (int j = bnd; j < e.size(); ++j) { if (e[j].w > q[i].first) break; now = dsu_meld(e[j].a, e[j].b, prev); sum -= pref[prev]; sum += (pref[now] - pref[now - prev]); ++bnd; } ans[q[i].second] = sum; } for (int i = 0; i < m; ++i) cout << ans[i] << ; return 0; } |
module main;
int unsigned foo, bar = 10;
int signed foos, bars = 10;
int unsigned wire_sum;
int wire_sums;
assign wire_sum = foo + bar;
assign wire_sums = foos + bars;
function int unsigned sum(input int unsigned a, b);
sum = a + b;
endfunction
function int unsigned sums(input int signed a, b);
sums = a + b;
endfunction
initial begin
foo = 9;
$display("%0d * %0d = %0d", foo, bar, foo * bar);
$display("sum(%0d,%0d) = %0d", foo, bar, sum(foo,bar));
if (foo !== 9 || bar !== 10) begin
$display("FAILED");
$finish;
end
if (foo*bar !== 90) begin
$display("FAILED");
$finish;
end
if (sum(foo,bar) !== 19) begin
$display("FAILED");
$finish;
end
foos = -7;
$display("%0d * %0d = %0d", foos, bars, foos * bars);
$display("sums(%0d,%0d) = %0d", foos, bars, sums(foos,bars));
if (foos !== -7 || bars !== 10) begin
$display("FAILED");
$finish;
end
if (foos*bars !== -70) begin
$display("FAILED");
$finish;
end
if (sums(foos,bars) !== 3) begin
$display("FAILED");
$finish;
end
#0; // allow CAs to propagate
$display("wire_sum = %0d", wire_sum);
$display("wire_sums = %0d", wire_sums);
if (wire_sum !== 19) begin
$display("FAILED");
$finish;
end
if (wire_sums !== 3) begin
$display("FAILED");
$finish;
end
$display("PASSED");
end
endmodule // main
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:200000000 ) using namespace std; long long step(long long a, long long n) { if (n == 0) return 1; else if (n % 2 == 0) return step(a * a, n / 2); else return a * step(a, n - 1); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n, k; cin >> n >> k; vector<int> A, d; A.resize(n + 1); d.resize(n + 1); for (int i = 1; i <= n; i++) cin >> A[i]; vector<int> tmp(n + 1, 10e6); for (int i = n; i >= 1; i--) { d[i] = tmp[A[i]]; tmp[A[i]] = i; } set<pair<int, int>> cur; set<int> used; int ans = 0, last = 0; for (int i = 0; i <= n; i++) tmp[i] = 0; for (int i = 1; i <= n && used.size() < k; i++) { if (used.find(A[i]) == used.end()) { ans++; used.insert(A[i]); cur.insert(make_pair(-d[i], A[i])); tmp[A[i]] = -d[i]; } else { cur.erase(cur.find(make_pair(tmp[A[i]], A[i]))); cur.insert(make_pair(-d[i], A[i])); tmp[A[i]] = -d[i]; } last = i; } for (int i = last + 1; i <= n; i++) { if (used.find(A[i]) != used.end()) { cur.erase(cur.find(make_pair(tmp[A[i]], A[i]))); cur.insert(make_pair(-d[i], A[i])); tmp[A[i]] = -d[i]; } else { pair<int, int> t = *cur.begin(); cur.erase(cur.begin()); used.erase(t.second); used.insert(A[i]); cur.insert(make_pair(-d[i], A[i])); tmp[A[i]] = -d[i]; ans++; } } cout << ans; return 0; } |
#include <bits/stdc++.h> int main() { int p, q, l, r; scanf( %d %d %d %d , &p, &q, &l, &r); std::vector<std::pair<int, int> > fixed; std::vector<std::pair<int, int> > changing; for (int k = 0; k < p; k++) { int a, b; scanf( %d %d , &a, &b); fixed.push_back(std::pair<int, int>(a, b)); } for (int k = 0; k < q; k++) { int a, b; scanf( %d %d , &a, &b); changing.push_back(std::pair<int, int>(a, b)); } bool done; int output(0); for (int k = l; k <= r; k++) { done = 0; for (int x = 0; x < fixed.size(); x++) { if (done) { continue; } for (int y = 0; y < changing.size(); y++) { if ((fixed[x].second < k + changing[y].first) || (k + changing[y].second < fixed[x].first)) { continue; } else { done = 1; ++output; break; } } } } printf( %d n , output); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 7; int sg[N]; int main() { int T, n, k; scanf( %d , &T); while (T--) { scanf( %d %d , &n, &k); bool flag = true; if (k % 3 == 0) { int t = (k / 3 - 1) * 3 + 4; int s = n % t; if (s == t - 4) flag = false; else if (s < t - 4 && s % 3 == 0) flag = false; } else { if (n % 3 == 0) flag = false; } if (flag) printf( Alice n ); else printf( Bob n ); } return 0; } |
`timescale 1ns/1ps
module testadd();
reg clk;
reg reset;
reg [7:0] snoopa;
reg [7:0] snoopd;
reg snoopp;
discus dcs(.clk(clk),
.reset(reset),
.snoop_clk(clk),
.snoopa(snoopa),
.snoopd(snoopd),
.snoopq(),
.snoopm(1'b0),
.snoopp(snoopp));
wire[7:0] prgram[0:12] = {
8'h68,
8'h0c, 8'h34,
8'h03, 8'h4a,
8'h90,
8'h0c, 8'h38,
8'h42,
8'h4a,
8'h4a,
8'h42,
8'ha8 };
initial begin : testit
integer i;
clk = 0;
snoopp = 1;
reset = 1;
#105;
for (i = 0; i <= 255; i = i + 1) begin
if (prgram[i] != 0) begin
snoopa = i;
snoopd = prgram[i];
clk = 0;
#5;
clk = 1;
#5;
clk = 0;
end
end
snoopp = 0;
reset = 0;
for (i = 0; i <= 20; i = i + 1) begin
clk = 0;
#5;
clk = 1;
#5;
clk = 0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 111111; vector<int> g[N]; bool s[N], f[N], used[N], foo[N], bar[N]; int q[N], qb, qe; int main() { int n; cin >> n; for (int i = 1; i < n; i++) { int u, v; cin >> u >> v; g[u].push_back(v); g[v].push_back(u); } for (int i = 1; i <= n; i++) cin >> s[i]; for (int i = 1; i <= n; i++) cin >> f[i]; vector<int> x; q[qe++] = 1; used[1] = true; if (s[1] != f[1]) { x.push_back(1); foo[1] = 1; } while (qb < qe) { int u = q[qb++]; for (int i = 0; i < g[u].size(); i++) { int v = g[u][i]; if (used[v]) continue; q[qe++] = v; used[v] = true; if ((s[v] ^ bar[u]) != f[v]) { x.push_back(v); foo[v] = bar[u] ^ 1; bar[v] = foo[u]; } else { foo[v] = bar[u]; bar[v] = foo[u]; } } } cout << x.size() << endl; for (int i = 0; i < x.size(); i++) cout << x[i] << endl; } |
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tmu2_vdiv(
input sys_clk,
input sys_rst,
output busy,
input pipe_stb_i,
output reg pipe_ack_o,
input signed [17:0] ax,
input signed [17:0] ay,
input signed [17:0] bx,
input signed [17:0] by,
input diff_cx_positive,
input [16:0] diff_cx,
input diff_cy_positive,
input [16:0] diff_cy,
input diff_dx_positive,
input [16:0] diff_dx,
input diff_dy_positive,
input [16:0] diff_dy,
input signed [11:0] drx,
input signed [11:0] dry,
input [10:0] dst_squareh,
output reg pipe_stb_o,
input pipe_ack_i,
output reg signed [17:0] ax_f,
output reg signed [17:0] ay_f,
output reg signed [17:0] bx_f,
output reg signed [17:0] by_f,
output reg diff_cx_positive_f,
output [16:0] diff_cx_q,
output [16:0] diff_cx_r,
output reg diff_cy_positive_f,
output [16:0] diff_cy_q,
output [16:0] diff_cy_r,
output reg diff_dx_positive_f,
output [16:0] diff_dx_q,
output [16:0] diff_dx_r,
output reg diff_dy_positive_f,
output [16:0] diff_dy_q,
output [16:0] diff_dy_r,
output reg signed [11:0] drx_f,
output reg signed [11:0] dry_f
);
/* Divider bank */
reg start;
wire ready;
tmu2_divider17 d_cx(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.start(start),
.dividend(diff_cx),
.divisor({6'd0, dst_squareh}),
.ready(ready),
.quotient(diff_cx_q),
.remainder(diff_cx_r)
);
tmu2_divider17 d_cy(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.start(start),
.dividend(diff_cy),
.divisor({6'd0, dst_squareh}),
.ready(),
.quotient(diff_cy_q),
.remainder(diff_cy_r)
);
tmu2_divider17 d_dx(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.start(start),
.dividend(diff_dx),
.divisor({6'd0, dst_squareh}),
.ready(),
.quotient(diff_dx_q),
.remainder(diff_dx_r)
);
tmu2_divider17 d_dy(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.start(start),
.dividend(diff_dy),
.divisor({6'd0, dst_squareh}),
.ready(),
.quotient(diff_dy_q),
.remainder(diff_dy_r)
);
/* Forward */
always @(posedge sys_clk) begin
if(start) begin
ax_f <= ax;
ay_f <= ay;
bx_f <= bx;
by_f <= by;
diff_cx_positive_f <= diff_cx_positive;
diff_cy_positive_f <= diff_cy_positive;
diff_dx_positive_f <= diff_dx_positive;
diff_dy_positive_f <= diff_dy_positive;
drx_f <= drx;
dry_f <= dry;
end
end
/* Glue logic */
reg state;
reg next_state;
parameter IDLE = 1'b0;
parameter WAIT = 1'b1;
always @(posedge sys_clk) begin
if(sys_rst)
state = IDLE;
else
state = next_state;
end
assign busy = state;
always @(*) begin
next_state = state;
start = 1'b0;
pipe_stb_o = 1'b0;
pipe_ack_o = 1'b0;
case(state)
IDLE: begin
pipe_ack_o = 1'b1;
if(pipe_stb_i) begin
start = 1'b1;
next_state = WAIT;
end
end
WAIT: begin
if(ready) begin
pipe_stb_o = 1'b1;
if(pipe_ack_i)
next_state = IDLE;
end
end
endcase
end
endmodule
|
//*******************************************************************************************
// Description: Netlist for FLPv3L's Layer Controller Register File
// Generated by genRF (Version 1.01) 08/25/2017 00:09:00
//
// [NOTE] This is a subset of the entire Register File. See Log file or MBus Register File
// Verilog module definition for the complete list of the Register File
//*******************************************************************************************
//*******************************************************************************************
// MEMORY MAP
//*******************************************************************************************
// MBUS ADDR || Register Name || Reset Value || Type || Comments
//*******************************************************************************************
// 8'h07 || REGISTER 0x07 ( 7) || || ||
//-------------------------------------------------------------------------------------------
// 8'h07 [12: 0] || SRAM_START_ADDR || 13'h0000 || LC ||
//*******************************************************************************************
// 8'h08 || REGISTER 0x08 ( 8) || || ||
//-------------------------------------------------------------------------------------------
// 8'h08 [17: 0] || FLSH_START_ADDR || 18'h00000 || LC ||
//*******************************************************************************************
// 8'h09 || REGISTER 0x09 ( 9) || || ||
//-------------------------------------------------------------------------------------------
// 8'h09 [18: 6] || LENGTH || 13'h0000 || LC ||
// 8'h09 [ 5] || IRQ_EN || 1'h0 || LC ||
// 8'h09 [ 4: 1] || CMD || 4'h0 || LC ||
// 8'h09 [ 0] || GO || 1'h0 || LC ||
//*******************************************************************************************
// 8'h13 || REGISTER 0x13 ( 19) || || ||
//-------------------------------------------------------------------------------------------
// 8'h13 [19: 1] || PP_STR_LIMIT || 19'h00000 || LC || Limit the number of words streamed. 0 means no-limit.
// 8'h13 [ 0] || PP_STR_EN || 1'h0 || LC || Ping-Pong Straming Enable
//*******************************************************************************************
// 8'h16 || REGISTER 0x16 ( 22) || || ||
//-------------------------------------------------------------------------------------------
// 8'h16 [18: 0] || PP_LENGTH_STREAMED || 19'h00000 || LC || Number of words received during Ping-Pong Streaming
//*******************************************************************************************
// 8'h17 || REGISTER 0x17 ( 23) || || ||
//-------------------------------------------------------------------------------------------
// 8'h17 [ 23] || PP_FLAG_END_OF_FLASH || 1'h0 || LC ||
// 8'h17 [ 22] || PP_FLAG_STR_LIMIT || 1'h0 || LC ||
// 8'h17 [ 21] || PP_FLAG_COPY_LIMIT || 1'h0 || LC ||
// 8'h17 [18: 0] || PP_LENGTH_COPIED || 19'h00000 || LC || Number of words copied to Flash during Ping-Pong Streaming
//*******************************************************************************************
module flpv3l_layer_ctrl_rf (
//Input
input RESETn,
input [ 71:0] ADDR_IN,
input [ 23:0] DATA_IN,
//Output
//Register 0x07 ( 7)
output reg [12:0] SRAM_START_ADDR,
//Register 0x08 ( 8)
output reg [17:0] FLSH_START_ADDR,
//Register 0x09 ( 9)
output reg [12:0] LENGTH,
output reg IRQ_EN,
output reg [ 3:0] CMD,
output reg GO,
//Register 0x13 ( 19)
output reg [18:0] PP_STR_LIMIT,
output reg PP_STR_EN,
//Register 0x16 ( 22)
output reg [18:0] PP_LENGTH_STREAMED,
//Register 0x17 ( 23)
output reg PP_FLAG_END_OF_FLASH,
output reg PP_FLAG_STR_LIMIT,
output reg PP_FLAG_COPY_LIMIT,
output reg [18:0] PP_LENGTH_COPIED
);
//****************************************************
// REGISTER 0x07 ( 7)
//****************************************************
//SRAM_START_ADDR (13'h0000)
always @ (posedge ADDR_IN[7] or negedge RESETn) begin
if (~RESETn) SRAM_START_ADDR <= `SD 13'h0000;
else SRAM_START_ADDR <= `SD DATA_IN[12:0];
end
//****************************************************
// REGISTER 0x08 ( 8)
//****************************************************
//FLSH_START_ADDR (18'h00000)
always @ (posedge ADDR_IN[8] or negedge RESETn) begin
if (~RESETn) FLSH_START_ADDR <= `SD 18'h00000;
else FLSH_START_ADDR <= `SD DATA_IN[17:0];
end
//****************************************************
// REGISTER 0x09 ( 9)
//****************************************************
//LENGTH (13'h0000)
always @ (posedge ADDR_IN[9] or negedge RESETn) begin
if (~RESETn) LENGTH <= `SD 13'h0000;
else LENGTH <= `SD DATA_IN[18:6];
end
//IRQ_EN (1'h0)
always @ (posedge ADDR_IN[9] or negedge RESETn) begin
if (~RESETn) IRQ_EN <= `SD 1'h0;
else IRQ_EN <= `SD DATA_IN[5:5];
end
//CMD (4'h0)
always @ (posedge ADDR_IN[9] or negedge RESETn) begin
if (~RESETn) CMD <= `SD 4'h0;
else CMD <= `SD DATA_IN[4:1];
end
//GO (1'h0)
always @ (posedge ADDR_IN[9] or negedge RESETn) begin
if (~RESETn) GO <= `SD 1'h0;
else GO <= `SD DATA_IN[0:0];
end
//****************************************************
// REGISTER 0x13 ( 19)
//****************************************************
//PP_STR_LIMIT (19'h00000)
always @ (posedge ADDR_IN[19] or negedge RESETn) begin
if (~RESETn) PP_STR_LIMIT <= `SD 19'h00000;
else PP_STR_LIMIT <= `SD DATA_IN[19:1];
end
//PP_STR_EN (1'h0)
always @ (posedge ADDR_IN[19] or negedge RESETn) begin
if (~RESETn) PP_STR_EN <= `SD 1'h0;
else PP_STR_EN <= `SD DATA_IN[0:0];
end
//****************************************************
// REGISTER 0x16 ( 22)
//****************************************************
//PP_LENGTH_STREAMED (19'h00000)
always @ (posedge ADDR_IN[22] or negedge RESETn) begin
if (~RESETn) PP_LENGTH_STREAMED <= `SD 19'h00000;
else PP_LENGTH_STREAMED <= `SD DATA_IN[18:0];
end
//****************************************************
// REGISTER 0x17 ( 23)
//****************************************************
//PP_FLAG_END_OF_FLASH (1'h0)
always @ (posedge ADDR_IN[23] or negedge RESETn) begin
if (~RESETn) PP_FLAG_END_OF_FLASH <= `SD 1'h0;
else PP_FLAG_END_OF_FLASH <= `SD DATA_IN[23:23];
end
//PP_FLAG_STR_LIMIT (1'h0)
always @ (posedge ADDR_IN[23] or negedge RESETn) begin
if (~RESETn) PP_FLAG_STR_LIMIT <= `SD 1'h0;
else PP_FLAG_STR_LIMIT <= `SD DATA_IN[22:22];
end
//PP_FLAG_COPY_LIMIT (1'h0)
always @ (posedge ADDR_IN[23] or negedge RESETn) begin
if (~RESETn) PP_FLAG_COPY_LIMIT <= `SD 1'h0;
else PP_FLAG_COPY_LIMIT <= `SD DATA_IN[21:21];
end
//PP_LENGTH_COPIED (19'h00000)
always @ (posedge ADDR_IN[23] or negedge RESETn) begin
if (~RESETn) PP_LENGTH_COPIED <= `SD 19'h00000;
else PP_LENGTH_COPIED <= `SD DATA_IN[18:0];
end
endmodule // flpv3l_layer_ctrl_rf
|
#include <bits/stdc++.h> using namespace std; int main() { int n, s; cin >> n >> s; int *sa = new int[s + 1]; for (int i = 0; i < s + 1; i++) { sa[i] = 0; } for (int i = 0; i < n; i++) { int tm, tp; cin >> tm >> tp; if (sa[tm] < tp) { sa[tm] = tp; } } int t = 0; for (int i = s; i > 0; i--) { if (t < sa[i]) t = sa[i]; t++; } cout << t << endl; getchar(); getchar(); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long int n, k; cin >> n >> k; n /= k; if (n % 2) cout << YES << endl; else cout << NO << endl; return 0; } |
module foo
(/*AUTOARG*/
// Outputs
aa
);
/*AUTOOUTPUTEVERY*/
// Beginning of automatic outputs (every signal)
output [Y:X] aa; // From inst of autoinst_signed_fubar2.v, ..., Couldn't Merge
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [Y:X] aa; // From inst of autoinst_signed_fubar2.v, ..., Couldn't Merge
// End of automatics
// Check that if aa is connected differently in a input, it doesn't make conflicts.
autoinst_signed_fubar2 inst
(
// Outputs
.an_output2 (hi.ear.ial),
.another_output2 (aa[FOO:0]),
// Inputs
.an_input2 (an_input2[1:0])
/*AUTOINST*/);
autoinst_signed_fubar2 instx
(
// Outputs
.an_output2 (hi.ear.ial),
// Inputs
.an_input2 (an_input2[1:0]),
.another_output2 (aa[Y:X]),
/*AUTOINST*/);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A211O_SYMBOL_V
`define SKY130_FD_SC_HD__A211O_SYMBOL_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a211o (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A211O_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; long long x, y, m, cnt = 0; int main() { scanf( %lld%lld%lld , &x, &y, &m); if (x >= m || y >= m) { printf( 0 ); return 0; } if (x <= 0 && y <= 0) { printf( -1 ); return 0; } while (x < m && y < m) { if (x > y) swap(x, y); if (x + y <= 0) { cnt += abs(x) / y; x = x + (abs(x) - abs(x) % y); } else { x += y; cnt++; ; } } printf( %lld , cnt); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, k, a, rev[132001 * 2], g[2][132001 * 2], ntt[132001], v1[132001], v2[132001], fr[132001], ifr[132001], as[132001], fg = 255, inv[132001], vl[132001]; int pw(int a, int p) { int as = 1; while (p) { if (p & 1) as = 1ll * as * a % 998244353; a = 1ll * a * a % 998244353; p >>= 1; } return as; } void init(int d) { fr[0] = 1; for (int i = 1; i <= 1 << d; i++) fr[i] = 1ll * fr[i - 1] * i % 998244353; ifr[1 << d] = pw(fr[1 << d], 998244353 - 2); for (int i = (1 << d); i >= 1; i--) ifr[i - 1] = 1ll * ifr[i] * i % 998244353, inv[i] = 1ll * fr[i - 1] * ifr[i] % 998244353; for (int i = 2; i <= 1 << d; i <<= 1) for (int j = 0; j < i; j++) rev[i + j] = (rev[i + (j >> 1)] >> 1) + (j & 1 ? i >> 1 : 0); for (int t = 0; t < 2; t++) for (int i = 2; i <= 1 << d; i <<= 1) { int tp = pw(3, 998244353 - 1 + (998244353 - 1) * (t * 2 - 1) / i); for (int j = 0, vl = 1; j < (i >> 1); j++, vl = 1ll * vl * tp % 998244353) g[t][i + j] = vl; } } void dft(int s, int *a, int t) { for (int i = 0; i < s; i++) ntt[rev[s + i]] = a[i]; for (int l = 2; l <= s; l <<= 1) for (int i = 0; i < s; i += l) for (int j = i, st = l; j < i + (l >> 1); j++, st++) { int v1 = ntt[j], v2 = 1ll * ntt[j + (l >> 1)] * g[t][st] % 998244353; ntt[j] = (v1 + v2) % 998244353; ntt[j + (l >> 1)] = (v1 - v2 + 998244353) % 998244353; } int tp = t ? 1 : pw(s, 998244353 - 2); for (int i = 0; i < s; i++) a[i] = 1ll * ntt[i] * tp % 998244353; } vector<int> add(vector<int> a, vector<int> b) { vector<int> c; int s1 = a.size(), s2 = b.size(); for (int i = 0; i < s1 || i < s2; i++) c.push_back(((i < s1 ? a[i] : 0) + (i < s2 ? b[i] : 0)) % 998244353); return c; } vector<int> mul(vector<int> a, vector<int> b, int n = 1e7) { vector<int> c; int s1 = a.size(), s2 = b.size(); for (int i = 0; i < s1 + s2 - 1; i++) c.push_back(0); if (s1 + s2 <= fg) { for (int i = 0; i < s1; i++) for (int j = 0; j < s2; j++) c[i + j] = (c[i + j] + 1ll * a[i] * b[j]) % 998244353; while (c.size() > n) c.pop_back(); return c; } int l = 1; while (l <= s1 + s2) l <<= 1; for (int i = 0; i < l; i++) v1[i] = v2[i] = 0; for (int i = 0; i < s1; i++) v1[i] = a[i]; for (int i = 0; i < s2; i++) v2[i] = b[i]; dft(l, v1, 1); dft(l, v2, 1); for (int i = 0; i < l; i++) v1[i] = 1ll * v1[i] * v2[i] % 998244353; dft(l, v1, 0); for (int i = 0; i < s1 + s2 - 1; i++) c[i] = v1[i]; while (c.size() > n) c.pop_back(); return c; } vector<int> polyinv(vector<int> a, int n) { while (a.size() < n) a.push_back(0); vector<int> b; for (int i = 0; i < n; i++) b.push_back(0); int tp = min(n, fg), st = pw(a[0], 998244353 - 2); for (int i = 0; i < tp; i++) { int vl = i ? 0 : 1; for (int j = 0; j < i; j++) vl = (vl - 1ll * b[j] * a[i - j] % 998244353 + 998244353) % 998244353; b[i] = 1ll * vl * st % 998244353; } if (n <= fg) return b; int x = 0; while ((n >> x) >= fg * 2 - 1) x++; while (1) { int l1 = ((n - 1) >> x) + 1, l2 = (l1 >> 1) + 1, l = 1; while (l <= l1 * 2 + 4) l <<= 1; for (int i = 0; i < l; i++) v1[i] = v2[i] = 0; for (int i = 0; i < l1; i++) v1[i] = a[i]; for (int i = 0; i < l2; i++) v2[i] = b[i]; dft(l, v1, 1); dft(l, v2, 1); for (int i = 0; i < l; i++) v1[i] = 1ll * v2[i] * (2 - 1ll * v1[i] * v2[i] % 998244353 + 998244353) % 998244353; dft(l, v1, 0); for (int i = 0; i < l1; i++) b[i] = v1[i]; if (!x) return b; x--; } } vector<int> polyln(vector<int> a, int n) { vector<int> v1, v2 = polyinv(a, n), as; for (int i = 1; i < a.size() && i <= n; i++) v1.push_back(1ll * a[i] * i % 998244353); v1 = mul(v1, v2); as.push_back(0); for (int i = 0; i < n; i++) as.push_back(1ll * v1[i] * inv[i + 1] % 998244353); return as; } int main() { init(17); scanf( %d%d , &n, &k); int m = k / 2; vl[0] = 1; for (int i = 1; i <= n; i++) if (i & 1) vl[i] = 1ll * vl[i - 1] * inv[i] % 998244353 * (m - i / 2) % 998244353; else vl[i] = 1ll * vl[i - 1] * inv[i] % 998244353 * (m + i / 2) % 998244353; vector<int> s1, s2; for (int i = 0; i <= n; i++) s1.push_back(i & 1 ? 0 : vl[i]); for (int i = 0; i <= n; i++) s2.push_back(i & 1 ? vl[i] : 0); s2[0] = 998244353 - 1; vector<int> t1 = mul(s2, polyinv(s1, n + 1), n + 1); for (int i = 0; i <= n; i++) if ((i + 3) % 4 > 1) t1[i] = (998244353 - t1[i]) % 998244353; if (k & 1) t1[1] = (t1[1] + 1) % 998244353; for (int i = 1; i <= n; i++) t1[i] = (i & 1) * (998244353 - t1[i]) % 998244353; vector<int> f1 = polyln(t1, n + 1); int as = 1ll * n * (998244353 - f1[n]) % 998244353; if (~n & 1) { for (int i = 2; i <= n; i++) if (i % 4 == 2) s1[i] = (998244353 - s1[i]) % 998244353; s1 = polyln(s1, n + 1); as = (as + 1ll * n * (998244353 - s1[n]) % 998244353) % 998244353; } printf( %d n , as); } |
// file header here
//
`timescale 1ns/100ps
// Switch between FSDB or VCD format of output waveform
`define FSDB
// Option to dump the entire memory content
`define DEBUG_MEM
// Option to trace read/write access to the data memory from the top level
`define DEBUG_DATAMEM_RW
// Option to trace memory read/write
// Turned off by default because it would be annoying
//`define DEBUG_MEM_RW
// Option to capture the instruction register at the positive-edge clock
// instead of the change of the instruction register
// Trade-off:
// a. With this option disabled:
// 1. Identical instructions will not be prompted if they are
// consecutive in order.
// (Becasue I use 'always @(ir)'.)
// b. With this option enabled:
// 1. Unknown instruction in the beginning will be captured.
// 2. The program counter will be displayed one cycle ahead from its
// corresponding instruction.
// (Becasue I use 'always @(posedge clk)' which causes a delay.)
// I consider the trade-off a feature instead of a bug, because you might
// need to adapt the deassembler and revise it whatever necessary in your
// design.
//
//`define CYC_BASED_DEASSEMBLY
|
#include <bits/stdc++.h> using namespace std; int a[200002]; pair<int, int> b[200002]; int main() { int n, k, max = 0; for (int i = 0; i < 200001; i++) { a[i] = 2147483647; } scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d %d , &b[i].first, &b[i].second); } sort(b, b + n); for (int i = 0; i < n; i++) { int d = b[i].first - b[i].second; int* c = upper_bound(a, a + max, d); int index = c - a; if (index + 1 > max) { max = index + 1; } a[index] = min(a[index], b[i].first + b[i].second); } printf( %d n , max); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1005, mod = 1e9 + 7; int yh[N][N], a[N]; long long kpow(long long a, long long b) { long long ans = 1; while (b) { if (b & 1) ans = ans * a % mod; a = a * a % mod; b >>= 1; } return ans; } int main() { for (int i = (0); i < (N); ++i) yh[i][0] = 1; for (int i = (1); i < (N); ++i) for (int j = (1); j < (N); ++j) { yh[i][j] = yh[i - 1][j - 1] + yh[i - 1][j]; if (yh[i][j] >= mod) yh[i][j] -= mod; } int n, m; cin >> n >> m; a[0] = 0; a[m + 1] = n + 1; for (int i = (1); i < (m + 1); ++i) cin >> a[i]; sort(a + 1, a + m + 1); long long ans = 1, k = n - m; for (int i = (1); i < (m + 2); ++i) { int c = a[i] - a[i - 1] - 1; ans = ans * yh[k][c] % mod; if (i != 1 && i != m + 1 && c) ans = ans * kpow(2, c - 1) % mod; k -= c; } cout << ans << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = long long int; void fast() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); } int main() { fast(); int t, b, p, f, h, c; cin >> t; while (t--) { cin >> b >> p >> f; cin >> h >> c; int bun = b / 2; if (bun >= p + f) { cout << p * h + f * c << endl; } else { if (c > h) { if (bun >= f) { cout << f * c + (bun - f) * h << endl; } else { cout << bun * c << endl; } } else { if (bun >= p) { cout << p * h + (bun - p) * c << endl; } else { cout << bun * h << endl; } } } } return 0; } |
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