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//#############################################################################
//# Purpose: Clock divider with 2 outputs #
// Secondary clock must be multiple of first clock #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_clockdiv
(
//inputs
input clk, // main clock
input nreset, // async active low reset (from oh_rsync)
input clkchange, // indicates a parameter change
input clken, // clock enable
input [7:0] clkdiv, // [7:0]=period (0==bypass, 1=div/2, 2=div/3, etc)
input [15:0] clkphase0, // [7:0]=rising,[15:8]=falling
input [15:0] clkphase1, // [7:0]=rising,[15:8]=falling
//outputs
output clkout0, // primary output clock
output clkrise0, // rising edge match
output clkfall0, // falling edge match
output clkout1, // secondary output clock
output clkrise1, // rising edge match
output clkfall1, // falling edge match
output clkstable // clock is guaranteed to be stable
);
//regs
reg [7:0] counter;
reg clkout0_reg;
reg clkout1_reg;
reg clkout1_shift;
reg [2:0] period;
wire period_match;
wire [3:0] clk1_sel;
wire [3:0] clk1_sel_sh;
wire [1:0] clk0_sel;
wire [1:0] clk0_sel_sh;
//###########################################
//# CHANGE DETECT (count 8 periods)
//###########################################
always @ (posedge clk or negedge nreset)
if(!nreset)
period[2:0] <= 'b0;
else if (clkchange)
period[2:0] <='b0;
else if(period_match & ~clkstable)
period[2:0] <= period[2:0] +1'b1;
assign clkstable = (period[2:0]==3'b111);
//###########################################
//# CYCLE COUNTER
//###########################################
always @ (posedge clk or negedge nreset)
if (!nreset)
counter[7:0] <= 'b0;
else if(clken)
if(period_match)
counter[7:0] <= 'b0;
else
counter[7:0] <= counter[7:0] + 1'b1;
assign period_match = (counter[7:0]==clkdiv[7:0]);
//###########################################
//# RISING/FALLING EDGE SELECTORS
//###########################################
assign clkrise0 = (counter[7:0]==clkphase0[7:0]);
assign clkfall0 = (counter[7:0]==clkphase0[15:8]);
assign clkrise1 = (counter[7:0]==clkphase1[7:0]);
assign clkfall1 = (counter[7:0]==clkphase1[15:8]);
//###########################################
//# CLKOUT0
//###########################################
always @ (posedge clk or negedge nreset)
if(!nreset)
clkout0_reg <= 1'b0;
else if(clkrise0)
clkout0_reg <= 1'b1;
else if(clkfall0)
clkout0_reg <= 1'b0;
// clock mux
assign clk0_sel[1] = (clkdiv[7:0]==8'd0); // not implemented
assign clk0_sel[0] = ~(clkdiv[7:0]==8'd0);
// clock select needs to be stable high
oh_lat0 #(.DW(2))
latch_clk0 (.out (clk0_sel_sh[1:0]),
.clk (clk),
.in (clk0_sel[1:0]));
oh_clockmux #(.N(2))
mux_clk0 (.clkout(clkout0),
.en(clk0_sel[1:0]),
.clkin({clk, clkout0_reg}));
//###########################################
//# CLKOUT1
//###########################################
always @ (posedge clk or negedge nreset)
if(!nreset)
clkout1_reg <= 1'b0;
else if(clkrise1)
clkout1_reg <= 1'b1;
else if(clkfall1)
clkout1_reg <= 1'b0;
// creating divide by 2 shifted clock with negedge
always @ (negedge clk)
clkout1_shift <= clkout1_reg;
// clock mux
assign clk1_sel[3] = 1'b0; // not implemented
assign clk1_sel[2] = (clkdiv[7:0]==8'd0); // div1 (bypass)
assign clk1_sel[1] = (clkdiv[7:0]==8'd1); // div2 clock
assign clk1_sel[0] = |clkdiv[7:1]; // all others
// clock select needs to be stable high
oh_lat0 #(.DW(4))
latch_clk1 (.out (clk1_sel_sh[3:0]),
.clk (clk),
.in (clk1_sel[3:0]));
oh_clockmux #(.N(4))
mux_clk1 (.clkout(clkout1),
.en(clk1_sel[3:0]),
.clkin({1'b0, clk, clkout1_shift, clkout1_reg}));
endmodule // oh_clockdiv
|
#include <bits/stdc++.h> using namespace std; struct disjoint_set { vector<int> p; disjoint_set(int n) : p(n, -1) {} bool share(int a, int b) { return root(a) == root(b); } int sz(int u) { return -p[root(u)]; } int root(int u) { return p[u] < 0 ? u : p[u] = root(p[u]); } bool merge(int u, int v) { u = root(u), v = root(v); if (u == v) return false; p[u] += p[v], p[v] = u; return true; } }; int main() { cin.tie(0)->sync_with_stdio(0); int n; string s; cin >> n >> s; vector<array<int, 2>> dp(n + 1); vector<int> reach(n); for (auto i = n - 1; i >= 0; --i) { if (s[i] != 1 ) { dp[i][0] = dp[i + 1][0] + 1; } if (s[i] != 0 ) { dp[i][1] = dp[i + 1][1] + 1; } reach[i] = max(dp[i][0], dp[i][1]); } disjoint_set dsu(n + 1); for (auto l = 1; l <= n; ++l) { int res = 0; for (auto i = 0; i < n;) { if (reach[i] < l) { dsu.merge(i + 1, i); i = dsu.root(i); } else { res += reach[i] / l; i += reach[i] / l * l; } } cout << res << ; } cout << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long md = 1e9 + 7; const long long o5 = 716327852; const int N = 2e5 + 34; long long f[N], o[N]; long long ans, n, w, h; long long dp[N]; pair<long long, long long> a[N]; long long c(long long h, long long w) { return (((f[h + w] * o[h]) % md) * o[w]) % md; } int main() { o[0] = f[0] = 1; o[100000] = o5; for (long long i = 1; i < N; i++) f[i] = (f[i - 1] * i) % md; for (long long i = 99999; i > 0; i--) o[i] = (o[i + 1] * (i + 1)) % md; cin >> h >> w >> n; ans = c(h - 1, w - 1); for (int i = 0; i < n; i++) { cin >> a[i].first >> a[i].second; a[i].first--; a[i].second--; } sort(a, a + n); for (int i = 0; i < n; i++) { dp[i] = c(a[i].second, a[i].first); for (int j = 0; j < i; j++) if (a[j].first <= a[i].first && a[j].second <= a[i].second) dp[i] = (dp[i] - dp[j] * c(a[i].first - a[j].first, a[i].second - a[j].second) + md * md) % md; ans = (ans + md * md - dp[i] * c(w - a[i].second - 1, h - a[i].first - 1)) % md; } cout << ans; } |
#include <bits/stdc++.h> using namespace std; typedef long double real; string Pair[26][26]; int cost[26][26][501], dp[26][26][501]; pair<int, int> parent[26][26][501]; int n, m; char flag[501][501]; pair<int, pair<int, int> > buffer[26 * 26]; bool used[26][26]; int main() { ios_base::sync_with_stdio(false); string s; for (char c1 = a ; c1 < z + 1; ++c1) { for (char c2 = a ; c2 < z + 1; ++c2) { s = ; s += c1; s += c2; Pair[c1 - a ][c2 - a ] = s; } } cin >> n >> m; cin.get(); for (int i = 0; i < n; ++i) { cin.read(flag[i], m + 1); flag[i][m] = 0 ; } for (int i = 0; i < n; ++i) { for (int c1 = 0; c1 < 26; ++c1) { for (int c2 = 0; c2 < 26; ++c2) { cost[c1][c2][i] = m; } } for (int j = 0; j < m; ++j) { int c0 = flag[i][j] - a ; for (int c = 0; c < 26; ++c) { if (j % 2 == 0) { --cost[c0][c][i]; } else { --cost[c][c0][i]; } } } } for (int c1 = 0; c1 < 26; ++c1) { for (int c2 = 0; c2 < 26; ++c2) { dp[c1][c2][0] = cost[c1][c2][0]; } } for (int i = 1; i < n; ++i) { int ptr = 0; int cnt = 0; for (int c1 = 0; c1 < 26; ++c1) { for (int c2 = 0; c2 < 26; ++c2) { if (c1 == c2) { continue; } ++cnt; buffer[ptr++] = make_pair((dp[c1][c2][i - 1]), (make_pair((c1), (c2)))); used[c1][c2] = false; } } sort(buffer, buffer + cnt); ptr = 0; while (cnt) { for (int c1 = 0; c1 < 26; ++c1) { for (int c2 = 0; c2 < 26; ++c2) { pair<int, int> p = buffer[ptr].second; if (c1 == c2 || used[c1][c2] || p.first == c1 || p.second == c2) { continue; } dp[c1][c2][i] = dp[p.first][p.second][i - 1] + cost[c1][c2][i]; parent[c1][c2][i] = p; used[c1][c2] = true; --cnt; } } ++ptr; } } pair<int, int> p(0, 1); for (int c1 = 0; c1 < 26; ++c1) { for (int c2 = 0; c2 < 26; ++c2) { if (c1 == c2) { continue; } if (dp[c1][c2][n - 1] < dp[p.first][p.second][n - 1]) { p = make_pair((c1), (c2)); } } } cout << dp[p.first][p.second][n - 1] << n ; vector<pair<int, int> > ans; ans.reserve(n); int row = n - 1; while (row != -1) { ans.push_back(p); p = parent[p.first][p.second][row]; --row; } reverse((ans).begin(), (ans).end()); for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { flag[i][j] = Pair[ans[i].first][ans[i].second][j % 2]; } cout << flag[i] << n ; } } |
#include <bits/stdc++.h> using namespace std; const long long maxn = 1e4 + 9; long long a[maxn]; long long n; void solve() { cin >> n; long long sum = 0; for (long long i = 0; i < n; i++) { cin >> a[i]; sum += a[i]; } if (sum % n != 0) { cout << -1 n ; return; } sum /= n; long long j = -1; for (long long i = n - 1; i >= 1; i--) { if (a[i] >= i + 1) { j = i; break; } } vector<pair<pair<long long, long long>, long long> > ans; if (j != -1) { ans.emplace_back(make_pair(j, 0), 1); a[j] -= j + 1; a[0] += j + 1; for (long long e = j; e >= 1; e--) { if (a[e] % (e + 1) != 0) { long long x = (e + 1) - a[e] % (e + 1); ans.emplace_back(make_pair(0, e), x); a[0] -= x; a[e] += x; } ans.emplace_back(make_pair(e, 0), a[e] / (e + 1)); a[0] += a[e]; a[e] = 0; } } else { j = 0; } vector<pair<long long, long long> > kek; for (long long e = j + 1; e < n; e++) { kek.emplace_back((e + 1) - a[e], e); } sort(kek.begin(), kek.end()); for (auto x : kek) { if (a[0] >= x.first) { ans.emplace_back(make_pair(0, x.second), x.first); ans.emplace_back(make_pair(x.second, 0), 1); a[0] += a[x.second]; a[x.second] = 0; } else { cout << -1 n ; return; } } for (long long i = 1; i < n; i++) { ans.emplace_back(make_pair(0, i), sum); } if ((long long)ans.size() > 3 * n) { cout << -1 n ; return; } cout << ans.size() << n ; for (auto x : ans) cout << x.first.first + 1 << << x.first.second + 1 << << x.second << n ; } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t; cin >> t; while (t--) solve(); } |
#include <bits/stdc++.h> using namespace std; map<long long, int> mp; long long n, k, i, v[500005], val[500005], x, sum[500005], fr[500005], frec[500005], fr3[500005], nr, sum2[500005], bucket, val1, m, st, dr, s, stcur, drcur, sol[500005], fr2[500005], val2, b[500005]; struct wow { long long st, dr, poz; } a[500005]; long long cautbin(long long x) { long long st = 0, dr = n, mij, sol = 0; while (st <= dr) { mij = (st + dr) / 2; if (sum2[mij] <= x) { if (sum2[mij] == x) { sol = mij; } st = mij + 1; } else { dr = mij - 1; } } return sol; } bool compare(wow a, wow b) { if (a.st / bucket != b.st / bucket) { return a.st < b.st; } return a.dr < b.dr; } int main() { cin >> n >> k; for (i = 1; i <= n; i++) { cin >> x; if (x == 1) { val[i] = 1; } else { val[i] = -1; } } for (i = 1; i <= n; i++) { cin >> x; v[i] = x * val[i]; } for (i = 1; i <= n; i++) { sum[i] = sum[i - 1] + v[i]; } for (i = 0; i <= n; i++) { mp[sum[i] - k] = mp[sum[i]] = mp[sum[i] + k] = 0; } nr = 0; for (auto &a : mp) { a.second = ++nr; } for (i = 0; i <= n; i++) { fr[i] = mp[sum[i] - k]; fr2[i] = mp[sum[i]]; fr3[i] = mp[sum[i] + k]; } cin >> m; for (i = 1; i <= m; i++) { cin >> a[i].st >> a[i].dr; a[i].st--; a[i].poz = i; } bucket = 300; sort(a + 1, a + m + 1, compare); st = 0; dr = -1; s = 0; for (i = 1; i <= m; i++) { stcur = a[i].st; drcur = a[i].dr; while (st > stcur) { st--; s = s + frec[fr3[st]]; frec[fr2[st]]++; } while (dr < drcur) { dr++; s = s + frec[fr[dr]]; frec[fr2[dr]]++; } while (st < stcur) { frec[fr2[st]]--; s = s - frec[fr3[st]]; st++; } while (dr > drcur) { frec[fr2[dr]]--; s = s - frec[fr[dr]]; dr--; } sol[a[i].poz] = s; } for (i = 1; i <= m; i++) { cout << sol[i] << n ; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_PP_SYMBOL_V
`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_PP_SYMBOL_V
/**
* lpflow_isobufsrc: Input isolation, noninverted sleep.
*
* X = (!A | SLEEP)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_isobufsrc (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input SLEEP,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_PP_SYMBOL_V
|
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.92
// \ \ Application: MIG
// / / Filename: phy_rdctrl_sync.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 07:18:04 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
//Purpose:
// Synchronization of read control signal from MC/PHY rdlvl logic (clk) to
// read capture logic (clk_rsync) clock domain. Also adds additional delay
// to account for read latency
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: phy_rdctrl_sync.v,v 1.1 2011/06/02 07:18:04 mishra Exp $
**$Date: 2011/06/02 07:18:04 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_v3_9/data/dlib/virtex6/ddr3_sdram/verilog/rtl/phy/phy_rdctrl_sync.v,v $
******************************************************************************/
`timescale 1ps/1ps
module phy_rdctrl_sync #
(
parameter TCQ = 100
)
(
input clk,
input rst_rsync, // Use only CLK_RSYNC[0] reset
// Control for control sync logic
input mc_data_sel,
input [4:0] rd_active_dly,
// DFI signals from MC/PHY rdlvl logic
input dfi_rddata_en,
input phy_rddata_en,
// Control for read logic, initialization logic
output reg dfi_rddata_valid,
output reg dfi_rddata_valid_phy,
output reg rdpath_rdy // asserted when read path
// ready for use
);
// # of clock cycles after RST_RSYNC has deasserted before init/cal logic
// is taken out of reset. This is only needed for simulation when the "no
// init/no cal" option is selected. In this case, PHY_INIT will assert
// DFI_INIT_COMPLETE signal almost instantaneously once it is taken out
// of reset - however, there are certain pipe stages that must "flush
// out" (related to circular buffer synchronization) for a few cycles after
// RST_RSYNC is deasserted - in particular, the one related to generating
// DFI_RDDATA_VALID must not drive an unknown value on the bus after
// DFI_INIT_COMPLETE is asserted.
// NOTE: # of cycles of delay required depends on the circular buffer
// depth for RD_ACTIVE - it should >= (0.5*depth + 1)
localparam RDPATH_RDY_DLY = 10;
wire rddata_en;
wire rddata_en_rsync;
wire rddata_en_srl_out;
reg [RDPATH_RDY_DLY-1:0] rdpath_rdy_dly_r;
//***************************************************************************
// Delay RDDATA_EN by an amount determined during read-leveling
// calibration to reflect the round trip delay from command issuance until
// when read data is returned
//***************************************************************************
assign rddata_en = (mc_data_sel) ? dfi_rddata_en : phy_rddata_en;
// May need to flop output of SRL for better timing
SRLC32E u_rddata_en_srl
(
.Q (rddata_en_srl_out),
.Q31 (),
.A (rd_active_dly),
.CE (1'b1),
.CLK (clk),
.D (rddata_en)
);
// Flop once more for better timing
always @(posedge clk) begin
// Only assert valid on DFI bus after initialization complete
dfi_rddata_valid <= #TCQ rddata_en_srl_out & mc_data_sel;
// Assert valid for PHY during initialization
dfi_rddata_valid_phy <= #TCQ rddata_en_srl_out;
end
//***************************************************************************
// Generate a signal that tells initialization logic that read path is
// ready for use (i.e. for read leveling). Use RST_RSYNC, and delay it by
// RDPATH_RDY_DLY clock cycles, then synchronize to CLK domain.
// NOTE: This logic only required for simulation; for final h/w, there will
// always be a long delay between RST_RSYNC deassertion and
// DFI_INIT_COMPLETE assertion (for DRAM init, and leveling)
//***************************************************************************
// First delay by X number of clock cycles to guarantee that RDPATH_RDY
// isn't asserted too soon after RST_RSYNC is deasserted (to allow various
// synchronization pipe stages to "flush"). NOTE: Only RST_RSYNC[0] (or
// any of the up to 4 RST_RSYNC's) is used - any of them is sufficient
// close enough in timing to use
always @(posedge clk or posedge rst_rsync) begin
if (rst_rsync)
rdpath_rdy_dly_r <= #TCQ {{RDPATH_RDY_DLY}{1'b0}};
else
rdpath_rdy_dly_r[RDPATH_RDY_DLY-1:1]
<= #TCQ {rdpath_rdy_dly_r[RDPATH_RDY_DLY-2:0], 1'b1};
end
// Flop once more to prevent ISE tools from analyzing asynchronous path
// through this flop to receiving logic
always @(posedge clk)
rdpath_rdy <= rdpath_rdy_dly_r[RDPATH_RDY_DLY-1];
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O32A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__O32A_BEHAVIORAL_PP_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__o32a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X , or0_out, or1_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O32A_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; long long n, a[310]; long long fac[310], rev[310]; bool mmp[310][310]; long long mod = (long long)1e9 + 7; long long qmod(long long a, long long p) { long long ret = 1; while (p) { if (p & 1) ret = (ret * a) % mod; a = (a * a) % mod; p /= 2; } return ret; } void Init() { fac[0] = 1; for (int i = 1; i < 310; ++i) fac[i] = fac[i - 1] * i; rev[0] = 1; for (int i = 1; i < 310; ++i) rev[i] = qmod(fac[i], mod - 2); } long long C(int n, int m) { return fac[n] * rev[m] % mod * rev[n - m] % mod; } bool isSqure(long long q) { long long sq = (long long)sqrt(q); return sq * sq == q; } void input() { istream& in = cin; in >> n; for (int i = 1; i <= n; ++i) in >> a[i]; } bool vis[310]; int dfs(int p) { if (vis[p]) return 0; vis[p] = 1; int ret = 1; for (int i = 1; i <= n; ++i) { if (mmp[p][i]) { ret += dfs(i); } } return ret; } int num[310]; long long dp[310][310][310]; bool END[310]; void add(long long& a, long long b) { a %= mod; b %= mod; a = (a + b) % mod; } int main() { input(); Init(); for (int i = 1; i <= n; ++i) for (int j = i + 1; j <= n; ++j) { if (isSqure(a[i] * a[j])) { mmp[i][j] = mmp[j][i] = 1; } } vector<int> block; for (int i = 1; i <= n; ++i) { int ret = dfs(i); if (ret) block.push_back(ret); } sort(block.begin(), block.end()); reverse(block.begin(), block.end()); int sum = 0; for (int p : block) { for (int i = 1; i <= p; ++i) num[sum + i] = i; sum += p; END[sum] = 1; } dp[0][0][0] = 1; for (int i = 1; i <= n; ++i) for (int j = 0; j <= n + 1; ++j) for (int k = 0; k <= n + 1; ++k) { long long& ref = dp[i - 1][j][k]; if (dp[i - 1][j][k] == 0) continue; int allslot = i; int prewa = j - k; int nowwa = k; int nookwaslot = (num[i] - 1) * 2 - 2 * nowwa; int okslot = allslot - j - nookwaslot; if (!END[i]) { if (j > 0) add(dp[i][j - 1][k], dp[i - 1][j][k] * prewa); add(dp[i][j + 1][k + 1], dp[i - 1][j][k] * nowwa); add(dp[i][j][k], dp[i - 1][j][k] * okslot); add(dp[i][j + 1][k + 1], dp[i - 1][j][k] * nookwaslot); } else { if (j > 0) add(dp[i][j - 1][0], dp[i - 1][j][k] * prewa); add(dp[i][j + 1][0], dp[i - 1][j][k] * nowwa); add(dp[i][j][0], dp[i - 1][j][k] * okslot); add(dp[i][j + 1][0], dp[i - 1][j][k] * nookwaslot); } } cout << dp[n][0][0] << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n, m; cin >> n >> m; vector<vector<int> > A(n, vector<int>(m)), B(n, vector<int>(m)); for (int x = 0; x < n; x++) for (int y = 0; y < m; y++) cin >> A[x][y]; for (int x = 0; x < n; x++) for (int y = 0; y < m; y++) cin >> B[x][y]; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) if (A[i][j] < B[i][j]) swap(A[i][j], B[i][j]); } bool legal = true; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (i + 1 < n && A[i][j] >= A[i + 1][j]) legal = false; if (j + 1 < m && A[i][j] >= A[i][j + 1]) legal = false; } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (i + 1 < n && B[i][j] >= B[i + 1][j]) legal = false; if (j + 1 < m && B[i][j] >= B[i][j + 1]) legal = false; } } if (legal) cout << Possible n ; else cout << Impossible n ; } |
// cic_dec_2.v: CIC Decimator - single
// 2016-07-17 E. Brombaugh
module cic_dec_2 #(
parameter NUM_STAGES = 4, // Stages of int / comb
STG_GSZ = 8, // Bit growth per stage
ISZ = 10, // Input word size
OSZ = (ISZ + (NUM_STAGES * STG_GSZ)) // Output word size
)
(
input clk, // System clock
input reset, // System POR
input ena_out, // Decimated output rate (2 clks wide)
input signed [ISZ-1:0] x, // Input data
output signed [OSZ-1:0] y, // Output data
output valid // Output Valid
);
// sign-extend input
wire signed [OSZ-1:0] x_sx = {{OSZ-ISZ{x[ISZ-1]}},x};
// Integrators
reg signed [OSZ-1:0] integrator[0:NUM_STAGES-1];
always @(posedge clk)
begin
if(reset == 1'b1)
begin
integrator[0] <= {OSZ{1'b0}};
end
else
begin
integrator[0] <= integrator[0] + x_sx;
end
end
generate
genvar i;
for(i=1;i<NUM_STAGES;i=i+1)
begin
always @(posedge clk)
begin
if(reset == 1'b1)
begin
integrator[i] <= {OSZ{1'b0}};
end
else
begin
integrator[i] <= integrator[i] + integrator[i-1];
end
end
end
endgenerate
// Combs
reg [NUM_STAGES:0] comb_ena;
reg signed [OSZ-1:0] comb_diff[0:NUM_STAGES];
reg signed [OSZ-1:0] comb_dly[0:NUM_STAGES];
always @(posedge clk)
begin
if(reset == 1'b1)
begin
comb_ena <= {NUM_STAGES+2{1'b0}};
comb_diff[0] <= {OSZ{1'b0}};
comb_dly[0] <= {OSZ{1'b0}};
end
else
begin
if(ena_out == 1'b1)
begin
comb_diff[0] <= integrator[NUM_STAGES-1];
comb_dly[0] <= comb_diff[0];
end
comb_ena <= {comb_ena[NUM_STAGES:0],ena_out};
end
end
generate
genvar j;
for(j=1;j<=NUM_STAGES;j=j+1)
begin
always @(posedge clk)
begin
if(reset == 1'b1)
begin
comb_diff[j] <= {OSZ{1'b0}};
comb_dly[j] <= {OSZ{1'b0}};
end
else if(comb_ena[j-1] == 1'b1)
begin
comb_diff[j] <= comb_diff[j-1] - comb_dly[j-1];
comb_dly[j] <= comb_diff[j];
end
end
end
endgenerate
// assign output
assign y = comb_diff[NUM_STAGES];
assign valid = comb_ena[NUM_STAGES];
endmodule
|
#include <bits/stdc++.h> using namespace std; int tt(char p) { int s; if (p == > ) s = 8; else if (p == < ) s = 9; else if (p == + ) s = 10; else if (p == - ) s = 11; else if (p == . ) s = 12; else if (p == , ) s = 13; else if (p == [ ) s = 14; else s = 15; return s; } int main() { string x; int t = 0; int q = x.length() - 1; cin >> x; for (int i = 0; i < x.length(); ++i) { t = (t * 16 + tt(x[i])) % 1000003; } cout << t; return 0; } |
`timescale 1ns / 1ps
// sonic_sensor.v ver 1.0
// Description by Kazushi Yamashina
// Utsunomiya University
//
// _ _ _ _
//clk _| |__| |__ ........... __| |__| |_
// ___
//req __| |____________________________
// ____ ___
//busy ______| ........... |_______
// ____
//finish ____________________________| |_
// ______________
//out_data ____________ ....... __result______
//
// req : If you wanna get sensor value, assert req.
// busy : Module is processing while "busy" asserts.
// sig : assign to ultra sonic distance sensor.
// out_data : If "busy" negates, value is publisehd.
module sonic_sensor(
input clk,
input rst,
input req,
output [0:0] busy,
inout sig,
output finish,
output [31:0] out_data
);
parameter STATE_INIT = 0,
STATE_IDLE = 1,
STATE_OUT_SIG = 2,
STATE_OUT_END = 3,
STATE_WAIT750 = 4,
STATE_IN_SIG_WAIT = 5,
STATE_IN_SIG = 6,
STATE_IN_SIG_END = 7,
STATE_WAIT200 = 8,
STATE_PROCESS_END = 9;
reg [3:0] state;
reg [31:0] echo;
reg [32:0] counter;
reg [31:0] result;
wire count_5u;
wire count_750u;
wire count_200u;
wire echo_fl;
reg busy_reg;
reg finish_reg;
//for debug
// assign count_5u = counter == 5;
// assign count_750u = counter == 75;
// assign count_200u = counter == 20;
// assign echo_fl = (counter > 100)? 1 : 0;
assign count_5u = counter == 499;
assign count_750u = counter == 74998;
assign count_200u = counter == 19999;
assign echo_fl = (echo == )? 1 : 0; // 18.5ms @ 100MHz
assign sig = (state == STATE_OUT_SIG)? 1 : 1'bZ;
assign busy = busy_reg;
assign finish = finish_reg;
always @(posedge clk)
begin
if(rst) begin
busy_reg <= 0;
finish_reg <= 0;
end
else
case(state)
STATE_INIT: begin
busy_reg <= 0;
finish_reg <= 0;
end
STATE_IDLE: begin
if(req)
busy_reg <= 1;
else begin
busy_reg <= 0;
finish_reg <= 0;
end
end
STATE_PROCESS_END: begin
busy_reg <= 0;
finish_reg <= 1;
end
endcase
end
//state unit
always @(posedge clk)
begin
if(rst)
state <= 0;
else case(state)
STATE_INIT: state <= STATE_IDLE;
STATE_IDLE: if(req) state <= STATE_OUT_SIG;
STATE_OUT_SIG:if(count_5u) state <= STATE_OUT_END;
STATE_OUT_END: state <= STATE_WAIT750;
STATE_WAIT750:if(count_750u) state <= STATE_IN_SIG_WAIT;
STATE_IN_SIG_WAIT: state <= STATE_IN_SIG;
STATE_IN_SIG:begin
if(echo_fl || sig == 0) state <= STATE_IN_SIG_END;
end
STATE_IN_SIG_END: state <= STATE_WAIT200;
STATE_WAIT200:if(count_200u) state <= STATE_PROCESS_END;
STATE_PROCESS_END: state <= STATE_IDLE;
default: state <= STATE_INIT;
endcase
end
//counter
always @(posedge clk)
begin
if(rst)
counter <= 0;
else
case(state)
STATE_OUT_SIG: counter <= counter + 1;
STATE_WAIT750: counter <= counter + 1;
STATE_IN_SIG : counter <= counter + 1;
STATE_WAIT200: counter <= counter + 1;
default: counter <= 0;
endcase
end
//output
always @(posedge clk)
begin
if(rst)
echo <= 0;
else if(state == STATE_IN_SIG)begin
echo <= echo + 1;
end
else if (state == STATE_PROCESS_END)
echo <= 0;
end
always @(posedge clk)begin
if(rst)
result <= 0;
else if(state == STATE_PROCESS_END)
result <= echo;
end
assign out_data = result[31:0];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O32A_2_V
`define SKY130_FD_SC_HS__O32A_2_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog wrapper for o32a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o32a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o32a_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o32a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o32a_2 (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o32a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O32A_2_V
|
#include <bits/stdc++.h> using namespace std; const long long maxn = 500000 + 5; long long a[maxn], tmp[maxn]; multiset<long long> save; vector<pair<long long, long long> > b; int main() { long long total = 0; long long n; scanf( %lld , &n); for (long long i = 0; i < n; i++) scanf( %lld , a + i), total += a[i]; sort(a, a + n, greater<long long>()); for (long long i = 0, cnt = 1; i < n; i++, cnt++) if (i == n - 1 || a[i] != a[i + 1]) b.push_back(make_pair(a[i], cnt)), cnt = 0; for (long long i = 0, sizesum = 0; i < (long long)b.size(); i++) { long long num = b[i].first, nowsize = b[i].second; long long save_size = min(sizesum, sizesum + nowsize >> 1); long long cnt = max(0LL, save_size - nowsize); for (long long j = save_size - 1; j >= cnt; j--) if (j < (long long)save.size()) tmp[j] = *save.begin(), save.erase(save.begin()); else tmp[j] = 0; for (long long j = cnt, k = sizesum - cnt; j < k && j < save_size; j++) if (tmp[j] < num) tmp[j] = num; else if (--k < save_size) tmp[k] = max(0LL, 2LL * num - tmp[j]); save.insert(tmp + cnt, tmp + save_size); sizesum += nowsize; } for (auto it = save.begin(); it != save.end(); it++) total -= (*it); printf( %lld n , total); } |
#include<set> #include<map> #include<stack> #include<cmath> #include<queue> #include<cstdio> #include<vector> #include<climits> #include<cstdlib> #include<cstring> #include<iostream> #include<algorithm> #define LL long long using namespace std; LL read(){ bool f=0;LL x=0;char c=getchar(); while(c< 0 || 9 <c){if(c== - )f=1;c=getchar();} while( 0 <=c&&c<= 9 ) x=(x<<3)+(x<<1)+(c^48),c=getchar(); return !f?x:-x; } typedef pair<long double,long double> pii; #define mp make_pair #define fi first #define se second #define lch (u<<1) #define rch (u<<1|1) const long double eps=1e-10; const int MAXN=200000; const int INF=0x3f3f3f3f; LL a[MAXN+5]; vector<pair<int,LL> > Tu[5*MAXN+5]; bool K(pii p,pii a,pii b){if(p.fi==a.fi) return 1;return (p.se-a.se)/(p.fi-a.fi)>=(p.se-b.se)/(p.fi-b.fi);} void Build(int u,int L,int R){ if(L==R){ Tu[u].push_back(mp(L,a[L])); return ; } int Mid=(L+R)>>1; Build(lch,L,Mid),Build(rch,Mid+1,R); Tu[u]=Tu[lch]; int lst=Tu[u].size()-1; for(int i=0;i<Tu[rch].size();i++){ while(lst&&K(Tu[u][lst-1],Tu[u][lst],Tu[rch][i])) Tu[u].pop_back(),lst--; Tu[u].push_back(Tu[rch][i]),lst++; } return ; } pair<long double,int> P[MAXN+5]; int Query(int u,int L,int R,int qL,int qR,int pos){ if(qL<=L&&R<=qR){ int siz=Tu[u].size(); int le=0,ri=siz; while(le+1<ri){ int mid=(le+ri)>>1; if(K(mp(pos,a[pos]),Tu[u][mid-1],Tu[u][mid])) le=mid; else ri=mid; } return Tu[u][le].first; } int Mid=(L+R)>>1,ret=-1; if(qL<=Mid) ret=Query(lch,L,Mid,qL,qR,pos); if(Mid+1<=qR){ int tmp=Query(rch,Mid+1,R,qL,qR,pos); if(ret==-1||K(mp(pos,a[pos]),mp(ret,a[ret]),mp(tmp,a[tmp]))) ret=tmp; } return ret; } int n,m; void Get(int L,int R,int ad){ if(L>=R) return ; int p=Query(1,0,n,L,R,L); P[p]=mp(1.0*(a[p]-a[L])/(p-L)-eps,R-L-1+ad); //printf( %f %d %d %d n ,(double)P[p].first,p,L,R-L-1+ad); Get(L,p-1,1),Get(p,R,ad); return ; } int ans[MAXN+5]; long double k[MAXN+5]; int main(){ n=read(),m=read(); for(int i=1;i<=n;i++) a[i]=a[i-1]+read(); Build(1,0,n); Get(0,n,0); sort(P+1,P+n+1); for(int i=n;i>=1;i--) ans[i]=max(P[i].second,ans[i+1]); for(int i=1;i<=m;i++){ k[i]=read(); int t=upper_bound(P+1,P+n+1,mp(k[i],0))-P; printf( %d ,ans[t]),putchar(i==m? n : ); } return 0; } |
#include <bits/stdc++.h> using namespace std; bool exceed(long long x, long long y, long long m) { return x >= m / y + 1; } struct SegTree { int size; vector<pair<long long, long long> > seg; SegTree() {} SegTree(int size) { this->size = size; seg.resize(1 << (size + 1)); } pair<long long, long long> Ident() { return pair<long long, long long>(-1e18, -1e18); } pair<long long, long long> ope(pair<long long, long long> a, pair<long long, long long> b) { return max(a, b); } void init() { for (int i = 0; i < (1 << (size + 1)); i++) seg[i] = Ident(); } void update(int i, pair<long long, long long> val) { i += (1 << size); seg[i] = val; while (i > 1) { i /= 2; seg[i] = ope(seg[i * 2], seg[i * 2 + 1]); } } pair<long long, long long> query(int a, int b, int k, int l, int r) { if (b < l || r < a) return Ident(); if (a <= l && r <= b) return seg[k]; pair<long long, long long> lval = query(a, b, k * 2, l, (l + r) / 2); pair<long long, long long> rval = query(a, b, k * 2 + 1, (l + r) / 2 + 1, r); return ope(lval, rval); } pair<long long, long long> query(int a, int b) { if (a > b) return Ident(); return query(a, b, 1, 0, (1 << size) - 1); } }; long long n; long long a[500005], b[500005]; SegTree seg(19); bool used[500005]; long long ans[500005]; vector<long long> topo; void dfs(int v) { used[v] = true; seg.update(v, pair<long long, long long>(-1e18, -1e18)); if (a[v] <= n && !used[a[v]]) dfs(a[v]); while (1) { pair<long long, long long> res = seg.query(1, b[v] - 1); if (res.first <= v) break; dfs(res.second); } topo.push_back(v); } int main(void) { ios::sync_with_stdio(0); cin.tie(0); cin >> n; for (long long(i) = (1); (i) <= (n); (i)++) { cin >> a[i]; if (a[i] == -1) a[i] = n + 1; } for (long long(i) = (1); (i) <= (n); (i)++) b[a[i]] = i; for (long long(i) = (1); (i) <= (n); (i)++) if (b[i] == 0) b[i] = n + 1; seg.init(); for (long long(i) = (1); (i) <= (n); (i)++) seg.update(i, pair<long long, long long>(a[i], i)); for (long long(i) = (1); (i) <= (n); (i)++) if (!used[i]) dfs(i); reverse((topo).begin(), (topo).end()); for (long long(i) = 0; (i) < (long long)(topo).size(); (i)++) ans[topo[i]] = i + 1; for (long long(i) = (1); (i) <= (n); (i)++) cout << ans[i] << ; cout << endl; return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:19:08 12/01/2010
// Design Name:
// Module Name: sd_dma
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sd_dma(
input [3:0] SD_DAT,
inout SD_CLK,
input CLK,
input SD_DMA_EN,
output SD_DMA_STATUS,
output SD_DMA_SRAM_WE,
output SD_DMA_NEXTADDR,
output [7:0] SD_DMA_SRAM_DATA,
input SD_DMA_PARTIAL,
input [10:0] SD_DMA_PARTIAL_START,
input [10:0] SD_DMA_PARTIAL_END,
input SD_DMA_START_MID_BLOCK,
input SD_DMA_END_MID_BLOCK,
output [10:0] DBG_cyclecnt,
output [2:0] DBG_clkcnt
);
reg [10:0] SD_DMA_STARTr;
reg [10:0] SD_DMA_ENDr;
reg SD_DMA_PARTIALr;
always @(posedge CLK) SD_DMA_PARTIALr <= SD_DMA_PARTIAL;
reg SD_DMA_DONEr;
reg[1:0] SD_DMA_DONEr2;
initial begin
SD_DMA_DONEr2 = 2'b00;
SD_DMA_DONEr = 1'b0;
end
always @(posedge CLK) SD_DMA_DONEr2 <= {SD_DMA_DONEr2[0], SD_DMA_DONEr};
wire SD_DMA_DONE_rising = (SD_DMA_DONEr2[1:0] == 2'b01);
reg [1:0] SD_DMA_ENr;
initial SD_DMA_ENr = 2'b00;
always @(posedge CLK) SD_DMA_ENr <= {SD_DMA_ENr[0], SD_DMA_EN};
wire SD_DMA_EN_rising = (SD_DMA_ENr [1:0] == 2'b01);
reg SD_DMA_STATUSr;
assign SD_DMA_STATUS = SD_DMA_STATUSr;
reg SD_DMA_CLKMASKr = 1'b1;
// we need 1042 cycles (startbit + 1024 nibbles + 16 crc + stopbit)
reg [10:0] cyclecnt;
initial cyclecnt = 11'd0;
reg SD_DMA_SRAM_WEr;
initial SD_DMA_SRAM_WEr = 1'b1;
assign SD_DMA_SRAM_WE = (cyclecnt < 1025 && SD_DMA_STATUSr) ? SD_DMA_SRAM_WEr : 1'b1;
reg SD_DMA_NEXTADDRr;
assign SD_DMA_NEXTADDR = (cyclecnt < 1025 && SD_DMA_STATUSr) ? SD_DMA_NEXTADDRr : 1'b0;
reg[7:0] SD_DMA_SRAM_DATAr;
assign SD_DMA_SRAM_DATA = SD_DMA_SRAM_DATAr;
// we have 4 internal cycles per SD clock, 8 per RAM byte write
reg [2:0] clkcnt;
initial clkcnt = 3'b000;
reg [1:0] SD_CLKr;
initial SD_CLKr = 3'b111;
always @(posedge CLK)
if(SD_DMA_EN_rising) SD_CLKr <= 3'b111;
else SD_CLKr <= {SD_CLKr[0], clkcnt[1]};
assign SD_CLK = SD_DMA_CLKMASKr ? 1'bZ : SD_CLKr[1];
always @(posedge CLK) begin
if(SD_DMA_EN_rising) begin
SD_DMA_STATUSr <= 1'b1;
SD_DMA_STARTr <= (SD_DMA_PARTIALr ? SD_DMA_PARTIAL_START : 11'h0);
SD_DMA_ENDr <= (SD_DMA_PARTIALr ? SD_DMA_PARTIAL_END : 11'd1024);
end
else if (SD_DMA_DONE_rising) SD_DMA_STATUSr <= 1'b0;
end
always @(posedge CLK) begin
if(SD_DMA_EN_rising) begin
SD_DMA_CLKMASKr <= 1'b0;
end
else if (SD_DMA_DONEr) begin
SD_DMA_CLKMASKr <= 1'b1;
end
end
always @(posedge CLK) begin
if(cyclecnt == 1042
|| ((SD_DMA_END_MID_BLOCK & SD_DMA_PARTIALr) && cyclecnt == SD_DMA_PARTIAL_END))
SD_DMA_DONEr <= 1;
else SD_DMA_DONEr <= 0;
end
always @(posedge CLK) begin
if(SD_DMA_EN_rising || !SD_DMA_STATUSr) begin
clkcnt <= 0;
end else begin
if(SD_DMA_STATUSr) begin
clkcnt <= clkcnt + 1;
end
end
end
always @(posedge CLK) begin
if(SD_DMA_EN_rising)
cyclecnt <= (SD_DMA_PARTIALr && SD_DMA_START_MID_BLOCK) ? SD_DMA_PARTIAL_START : 0;
else if(!SD_DMA_STATUSr) cyclecnt <= 0;
else if(clkcnt[1:0] == 2'b10) cyclecnt <= cyclecnt + 1;
end
// we have 8 clk cycles to complete one RAM write
// (4 clk cycles per SD_CLK; 2 SD_CLK cycles per byte)
always @(posedge CLK) begin
if(SD_DMA_STATUSr) begin
case(clkcnt[2:0])
3'h0: begin
SD_DMA_SRAM_DATAr[7:4] <= SD_DAT;
if(cyclecnt>SD_DMA_STARTr && cyclecnt <= SD_DMA_ENDr) SD_DMA_NEXTADDRr <= 1'b1;
end
3'h1: begin
SD_DMA_NEXTADDRr <= 1'b0;
end
3'h2: if(cyclecnt>=SD_DMA_STARTr && cyclecnt < SD_DMA_ENDr) SD_DMA_SRAM_WEr <= 1'b0;
// 3'h3:
3'h4:
SD_DMA_SRAM_DATAr[3:0] <= SD_DAT;
// 3'h5:
// 3'h6:
3'h7:
SD_DMA_SRAM_WEr <= 1'b1;
endcase
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2HV_HL_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__LSBUFHV2HV_HL_BEHAVIORAL_PP_V
/**
* lsbufhv2hv_hl: Level shifting buffer, High Voltage to High Voltage,
* Higher Voltage to Lower Voltage.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__lsbufhv2hv_hl (
X ,
A ,
VPWR ,
VGND ,
LOWHVPWR,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR ;
input VGND ;
input LOWHVPWR;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A;
wire buf0_out_X ;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A, A, VPWR, VGND );
buf buf0 (buf0_out_X , pwrgood_pp0_out_A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (X , buf0_out_X, LOWHVPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2HV_HL_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int M = 100000 + 10; int d[M]; long long int pred[M]; long long int a[M]; long long int dp[110][M]; long long int pres[M]; long long int dq[M]; long long int yk(int i, int k) { long long int val = dp[i][k] + pres[k]; return val; } int main() { int n, m, p; cin >> n >> m >> p; for (int i = 2; i <= n; i++) { cin >> d[i]; pred[i] = pred[i - 1] + d[i]; } for (int i = 1; i <= m; i++) { int h, t; cin >> h >> t; int val = t - pred[h]; a[i] = val; } sort(a + 1, a + m + 1); for (int i = 1; i <= m; i++) { pres[i] = pres[i - 1] + a[i]; } for (int i = 1; i <= m; i++) { dp[1][i] = (i - 0) * a[i] - (pres[i] - pres[0]); } for (int i = 2; i <= p; i++) { int s = 0; int t = 0; for (int j = 1; j <= m; j++) { while ((t - s) >= 2 && (yk(i - 1, dq[t - 1]) - yk(i - 1, dq[t - 2])) * (j - dq[t - 1]) > (yk(i - 1, j) - yk(i - 1, dq[t - 1])) * (dq[t - 1] - dq[t - 2])) { t--; } dq[t] = j; t++; while ((t - s) >= 2 && dp[i - 1][dq[s]] - dq[s] * a[j] + pres[dq[s]] > dp[i - 1][dq[s + 1]] - dq[s + 1] * a[j] + pres[dq[s + 1]]) { s++; } dp[i][j] = dp[i - 1][dq[s]] + (j - dq[s]) * a[j] - (pres[j] - pres[dq[s]]); } } cout << dp[p][m] << endl; return 0; } |
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: fm_ram_1024w.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.0.0 Build 200 06/17/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fm_ram_1024w (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [23:0] data;
input [9:0] rdaddress;
input [9:0] wraddress;
input wren;
output [23:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [23:0] sub_wire0;
wire [23:0] q = sub_wire0[23:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({24{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.numwords_b = 1024,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 10,
altsyncram_component.widthad_b = 10,
altsyncram_component.width_a = 24,
altsyncram_component.width_b = 24,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "24576"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "24"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "24"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "24"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "24"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "24"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "24"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 24 0 INPUT NODEFVAL "data[23..0]"
// Retrieval info: USED_PORT: q 0 0 24 0 OUTPUT NODEFVAL "q[23..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 10 0 INPUT NODEFVAL "rdaddress[9..0]"
// Retrieval info: USED_PORT: wraddress 0 0 10 0 INPUT NODEFVAL "wraddress[9..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 10 0 wraddress 0 0 10 0
// Retrieval info: CONNECT: @address_b 0 0 10 0 rdaddress 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 24 0 data 0 0 24 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 24 0 @q_b 0 0 24 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fm_ram_1024w.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fm_ram_1024w.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fm_ram_1024w.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fm_ram_1024w.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fm_ram_1024w_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fm_ram_1024w_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; struct Edge { int v, next; } edge[100010]; int head[10]; int pos; void insert(int x, int y) { edge[pos].v = y; edge[pos].next = head[x]; head[x] = pos++; } int du[10]; int pp[100010]; int qq; int fa[10]; int find(int x) { if (fa[x] != x) fa[x] = find(fa[x]); return fa[x]; } void uunion(int x, int y) { int fx = find(x); int fy = find(y); fa[fx] = fy; } bool vis[100010]; void dfs(int now) { for (int i = head[now]; i != -1; i = edge[i].next) { if (vis[i / 2]) continue; vis[i / 2] = true; dfs(edge[i].v); pp[qq++] = i ^ 1; } } int main() { int n; scanf( %d , &n); memset(head, -1, sizeof(head)); pos = 0; for (int i = 0; i <= 6; i++) fa[i] = i; for (int i = 0; i < n; i++) { int x, y; scanf( %d %d , &x, &y); insert(x, y); insert(y, x); du[x]++; du[y]++; uunion(x, y); } bool flag = true; for (int i = 0; i <= 6; i++) for (int j = 0; j <= 6; j++) if (du[i] > 0 && du[j] > 0 && find(i) != find(j)) flag = false; if (!flag) { printf( No solution n ); return 0; } qq = 0; for (int i = 0; i <= 6; i++) if (du[i] & 1) pp[qq++] = i; if (qq > 2) { printf( No solution n ); return 0; } for (int i = 0; i <= 6; i++) if (du[i] != 0) pp[qq++] = i; int begin = pp[0]; qq = 0; memset(vis, false, sizeof(vis)); dfs(begin); for (int i = 0; i < qq; i++) { printf( %d , pp[i] / 2 + 1); if (pp[i] & 1) printf( - ); else printf( + ); printf( n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> void read(vector<T>& a) { for (auto& e : a) { cin >> e; } } template <class T> void print(vector<T>& a) { for (auto& e : a) { cout << e << ; } cout << n ; } void solve() { long long n, h; cin >> n >> h; vector<long long> a(n); read(a); if (n == 1) { cout << h << n ; return; } vector<long long> b; for (long long i = 1; i < n; ++i) { b.push_back(a[i] - a[i - 1]); } long long l = 0, r = 1e18; while (l + 1 != r) { long long m = (l + r) / 2; long long res = m; for (long long i = 0; i < n - 1; ++i) { res += min(m, b[i]); } if (res >= h) { r = m; } else { l = m; } } cout << r << n ; } signed main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t; cin >> t; while (t--) solve(); } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 2e5 + 5; const int oo = 0x3f3f3f3f; const int LIM = 2e5; int N, a[MAXN], num[MAXN], top, f[MAXN], ans[MAXN]; vector<int> S[MAXN]; int gcd(int a, int b) { return !b ? a : gcd(b, a % b); } namespace Graph { struct edge { int y, next; } e[MAXN << 1]; int LINK[MAXN], len = 0; inline void ins(int x, int y) { e[++len].next = LINK[x]; LINK[x] = len; e[len].y = y; } inline void Ins(int x, int y) { ins(x, y); ins(y, x); } void DFS(int node, int fa) { top = 0; S[node].push_back(f[fa]); f[node] = gcd(f[fa], a[node]); ans[node] = max(ans[node], f[node]); for (int i = 0; i <= (int)S[fa].size() - 1; i++) num[++top] = gcd(S[fa][i], a[node]); num[++top] = f[fa]; sort(num + 1, num + top + 1); top = unique(num + 1, num + top + 1) - (num + 1); ans[node] = max(ans[node], num[top]); for (int i = 1; i <= top; i++) S[node].push_back(num[i]); for (int i = LINK[node]; i; i = e[i].next) if (e[i].y != fa) DFS(e[i].y, node); } } // namespace Graph using namespace Graph; namespace solution { void Prepare() { scanf( %d , &N); for (int i = 1; i <= N; i++) scanf( %d , &a[i]); for (int i = 2; i <= N; i++) { int x, y; scanf( %d%d , &x, &y); Ins(x, y); } } void Solve() { DFS(1, 0); for (int i = 1; i <= N; i++) printf( %d , ans[i]); puts( ); } } // namespace solution int main() { using namespace solution; Prepare(); Solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; long long int n, a, k; char s[2000007], res[2000007]; bool vis[2000007]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n; long long int maxn = -1; for (long long int i = 0; i < n; ++i) { cin >> s >> k; long long int len = strlen(s); long long int cur = INT_MIN; for (long long int j = 0; j < k; ++j) { cin >> a; a--; maxn = max(maxn, a + len); for (long long int jj = max(cur, a); jj <= a + len - 1; ++jj) { if (!vis[jj]) { vis[jj] = 1; res[jj] = s[jj - a]; } } cur = max(cur, a + len - 1); } } for (long long int i = 0; i < maxn; ++i) if (!res[i]) cout << a ; else cout << res[i]; return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:52:53 06/12/2014
// Design Name:
// Module Name: seg7decimal
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module seg7decimal(
input [15:0] x,
input clk,
input clr,
output reg [6:0] a_to_g,
output reg [3:0] an,
output wire dp
);
wire [1:0] s;
reg [3:0] digit;
wire [3:0] aen;
reg [19:0] clkdiv;
assign dp = 1;
assign s = clkdiv[19:18];
assign aen = 4'b1111; // all turned off initially
// quad 4to1 MUX.
always @(posedge clk)// or posedge clr)
case(s)
0:digit = x[3:0]; // s is 00 -->0 ; digit gets assigned 4 bit value assigned to x[3:0]
1:digit = x[7:4]; // s is 01 -->1 ; digit gets assigned 4 bit value assigned to x[7:4]
2:digit = x[11:8]; // s is 10 -->2 ; digit gets assigned 4 bit value assigned to x[11:8
3:digit = x[15:12]; // s is 11 -->3 ; digit gets assigned 4 bit value assigned to x[15:12]
default:digit = x[3:0];
endcase
//decoder or truth-table for 7a_to_g display values
always @(*)
case(digit)
//////////<---MSB-LSB<---
//////////////gfedcba//////////////////////////////////////////// a
0:a_to_g = 7'b1000000;////0000 __
1:a_to_g = 7'b1111001;////0001 f/ /b
2:a_to_g = 7'b0100100;////0010 g
// __
3:a_to_g = 7'b0110000;////0011 e / /c
4:a_to_g = 7'b0011001;////0100 __
5:a_to_g = 7'b0010010;////0101 d
6:a_to_g = 7'b0000010;////0110
7:a_to_g = 7'b1111000;////0111
8:a_to_g = 7'b0000000;////1000
9:a_to_g = 7'b0010000;////1001
'hA:a_to_g = 7'b0111111; // dash-(g)
'hB:a_to_g = 7'b1111111; // all turned off
'hC:a_to_g = 7'b1110111;
default: a_to_g = 7'b0000000; // U
endcase
always @(*)begin
an=4'b1111;
if(aen[s] == 1)
an[s] = 0;
end
//clkdiv
always @(posedge clk or posedge clr) begin
if ( clr == 1)
clkdiv <= 0;
else
clkdiv <= clkdiv+1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const int N = 5e5 + 2; const int M = 1e5 + 2; const int inf = 2e9 + 2; const long long linf = 4e18 + 2; long long add(long long a, long long b) { a += b; return a >= mod ? a - mod : a; } long long sub(long long a, long long b) { a += mod - b; return a >= mod ? a - mod : a; } long long mul(long long a, long long b) { return (long long)a * b % mod; } long long a[N], bit[2][N]; long long id[N]; bool cmp(long long c, long long d) { return a[c] < a[d]; } void upd(int x, int val, int s) { for (; x < N; x += x & (-x)) bit[s][x] += val; } long long get(int x, int s) { long long ans = 0; for (; x > 0; x -= x & (-x)) ans += bit[s][x]; return ans; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n; cin >> n; for (int i = 1; i <= n; i++) cin >> a[i], id[i] = i; sort(id + 1, id + 1 + n, cmp); long long ans = 0; for (int j = 1; j <= n; j++) { int i = id[j]; ans = add(ans, mul(a[i], mul(i, n - i + 1))); long long l = get(i, 0); long long r = get(n, 1) - get(i, 1); ans = add(ans, mul(a[i], mul(l, n - i + 1))); ans = add(ans, mul(a[i], mul(r, i))); upd(i, i, 0); upd(i, n - i + 1, 1); } cout << ans << n ; return 0; } |
/* Simple external interrupt controller for MIPSfpga+ system
* managed using AHB-Lite bus
* Copyright(c) 2017 Stanislav Zhelnio
* https://github.com/zhelnio/ahb_lite_eic
*/
`include "mfp_eic_core.vh"
module mfp_ahb_lite_eic
(
//ABB-Lite side
input HCLK,
input HRESETn,
input [ 31 : 0 ] HADDR,
input [ 2 : 0 ] HBURST,
input HMASTLOCK, // ignored
input [ 3 : 0 ] HPROT, // ignored
input HSEL,
input [ 2 : 0 ] HSIZE,
input [ 1 : 0 ] HTRANS,
input [ 31 : 0 ] HWDATA,
input HWRITE,
output reg [ 31 : 0 ] HRDATA,
output HREADY,
output HRESP,
input SI_Endian, // ignored
//Interrupt side
input [ `EIC_CHANNELS-1 : 0 ] signal,
//CPU side
output [ 17 : 1 ] EIC_Offset,
output [ 3 : 0 ] EIC_ShadowSet,
output [ 7 : 0 ] EIC_Interrupt,
output [ 5 : 0 ] EIC_Vector,
output EIC_Present,
input EIC_IAck,
input [ 7 : 0 ] EIC_IPL,
input [ 5 : 0 ] EIC_IVN,
input [ 17 : 1 ] EIC_ION
);
assign HRESP = 1'b0;
assign HREADY = 1'b1;
wire [ `EIC_ADDR_WIDTH - 1 : 0 ] read_addr;
wire [ 31 : 0 ] read_data;
reg [ `EIC_ADDR_WIDTH - 1 : 0 ] write_addr;
wire [ 31 : 0 ] write_data;
reg write_enable;
wire [ `EIC_ADDR_WIDTH - 1 : 0 ] ADDR = HADDR [ `EIC_ADDR_WIDTH + 2 : 2 ];
parameter HTRANS_IDLE = 2'b0;
wire NeedRead = HTRANS != HTRANS_IDLE && HSEL;
wire NeedWrite = NeedRead & HWRITE;
assign write_data = HWDATA;
assign read_addr = ADDR;
always @ (posedge HCLK)
if(~HRESETn)
write_enable <= 1'b0;
else begin
if(NeedRead)
HRDATA <= read_data;
if(NeedWrite)
write_addr <= ADDR;
write_enable <= NeedWrite;
end
mfp_eic_core eic_core
(
.CLK ( HCLK ),
.RESETn ( HRESETn ),
.signal ( signal ),
.read_addr ( read_addr ),
.read_data ( read_data ),
.write_addr ( write_addr ),
.write_data ( write_data ),
.write_enable ( write_enable ),
.EIC_Offset ( EIC_Offset ),
.EIC_ShadowSet ( EIC_ShadowSet ),
.EIC_Interrupt ( EIC_Interrupt ),
.EIC_Vector ( EIC_Vector ),
.EIC_Present ( EIC_Present ),
.EIC_IAck ( EIC_IAck ),
.EIC_IPL ( EIC_IPL ),
.EIC_IVN ( EIC_IVN ),
.EIC_ION ( EIC_ION )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string x; cin >> x; int y; if (x.size() == 1) { y = x[0] - 0 ; if (!(y % 4)) cout << 4; else cout << 0; return 0; } y = x[x.size() - 1] - 0 + ((x[x.size() - 2] - 0 ) * 10); if (!(y % 4)) cout << 4; else cout << 0; return 0; } |
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 1999-2008 Easics NV.
// This source file may be used and distributed without restriction
// provided that this copyright statement is not removed from the file
// and that any derivative work contains the original copyright notice
// and the associated disclaimer.
//
// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
//
// Purpose : synthesizable CRC function
// * polynomial: x^16 + x^15 + x^2 + 1
// * data width: 72
//
// Info :
// http://www.easics.com
////////////////////////////////////////////////////////////////////////////////
module CRC16_D72(
nextCRC16_D1024,
Data,
crc
);
output reg [15:0] nextCRC16_D1024;
input wire [71:0] Data;
input wire [15:0] crc;
reg [71:0] d;
reg [15:0] c;
reg [15:0] newcrc;
begin
d = Data;
c = crc;
newcrc[0] = d[71] ^ d[69] ^ d[68] ^ d[67] ^ d[66] ^ d[65] ^ d[64] ^ d[63] ^ d[62] ^ d[61] ^ d[60] ^ d[55] ^ d[54] ^ d[53] ^ d[52] ^ d[51] ^ d[50] ^ d[49] ^ d[48] ^ d[47] ^ d[46] ^ d[45] ^ d[43] ^ d[41] ^ d[40] ^ d[39] ^ d[38] ^ d[37] ^ d[36] ^ d[35] ^ d[34] ^ d[33] ^ d[32] ^ d[31] ^ d[30] ^ d[27] ^ d[26] ^ d[25] ^ d[24] ^ d[23] ^ d[22] ^ d[21] ^ d[20] ^ d[19] ^ d[18] ^ d[17] ^ d[16] ^ d[15] ^ d[13] ^ d[12] ^ d[11] ^ d[10] ^ d[9] ^ d[8] ^ d[7] ^ d[6] ^ d[5] ^ d[4] ^ d[3] ^ d[2] ^ d[1] ^ d[0] ^ c[4] ^ c[5] ^ c[6] ^ c[7] ^ c[8] ^ c[9] ^ c[10] ^ c[11] ^ c[12] ^ c[13] ^ c[15];
newcrc[1] = d[70] ^ d[69] ^ d[68] ^ d[67] ^ d[66] ^ d[65] ^ d[64] ^ d[63] ^ d[62] ^ d[61] ^ d[56] ^ d[55] ^ d[54] ^ d[53] ^ d[52] ^ d[51] ^ d[50] ^ d[49] ^ d[48] ^ d[47] ^ d[46] ^ d[44] ^ d[42] ^ d[41] ^ d[40] ^ d[39] ^ d[38] ^ d[37] ^ d[36] ^ d[35] ^ d[34] ^ d[33] ^ d[32] ^ d[31] ^ d[28] ^ d[27] ^ d[26] ^ d[25] ^ d[24] ^ d[23] ^ d[22] ^ d[21] ^ d[20] ^ d[19] ^ d[18] ^ d[17] ^ d[16] ^ d[14] ^ d[13] ^ d[12] ^ d[11] ^ d[10] ^ d[9] ^ d[8] ^ d[7] ^ d[6] ^ d[5] ^ d[4] ^ d[3] ^ d[2] ^ d[1] ^ c[0] ^ c[5] ^ c[6] ^ c[7] ^ c[8] ^ c[9] ^ c[10] ^ c[11] ^ c[12] ^ c[13] ^ c[14];
newcrc[2] = d[70] ^ d[61] ^ d[60] ^ d[57] ^ d[56] ^ d[46] ^ d[42] ^ d[31] ^ d[30] ^ d[29] ^ d[28] ^ d[16] ^ d[14] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[4] ^ c[5] ^ c[14];
newcrc[3] = d[71] ^ d[62] ^ d[61] ^ d[58] ^ d[57] ^ d[47] ^ d[43] ^ d[32] ^ d[31] ^ d[30] ^ d[29] ^ d[17] ^ d[15] ^ d[2] ^ d[1] ^ c[1] ^ c[2] ^ c[5] ^ c[6] ^ c[15];
newcrc[4] = d[63] ^ d[62] ^ d[59] ^ d[58] ^ d[48] ^ d[44] ^ d[33] ^ d[32] ^ d[31] ^ d[30] ^ d[18] ^ d[16] ^ d[3] ^ d[2] ^ c[2] ^ c[3] ^ c[6] ^ c[7];
newcrc[5] = d[64] ^ d[63] ^ d[60] ^ d[59] ^ d[49] ^ d[45] ^ d[34] ^ d[33] ^ d[32] ^ d[31] ^ d[19] ^ d[17] ^ d[4] ^ d[3] ^ c[3] ^ c[4] ^ c[7] ^ c[8];
newcrc[6] = d[65] ^ d[64] ^ d[61] ^ d[60] ^ d[50] ^ d[46] ^ d[35] ^ d[34] ^ d[33] ^ d[32] ^ d[20] ^ d[18] ^ d[5] ^ d[4] ^ c[4] ^ c[5] ^ c[8] ^ c[9];
newcrc[7] = d[66] ^ d[65] ^ d[62] ^ d[61] ^ d[51] ^ d[47] ^ d[36] ^ d[35] ^ d[34] ^ d[33] ^ d[21] ^ d[19] ^ d[6] ^ d[5] ^ c[5] ^ c[6] ^ c[9] ^ c[10];
newcrc[8] = d[67] ^ d[66] ^ d[63] ^ d[62] ^ d[52] ^ d[48] ^ d[37] ^ d[36] ^ d[35] ^ d[34] ^ d[22] ^ d[20] ^ d[7] ^ d[6] ^ c[6] ^ c[7] ^ c[10] ^ c[11];
newcrc[9] = d[68] ^ d[67] ^ d[64] ^ d[63] ^ d[53] ^ d[49] ^ d[38] ^ d[37] ^ d[36] ^ d[35] ^ d[23] ^ d[21] ^ d[8] ^ d[7] ^ c[7] ^ c[8] ^ c[11] ^ c[12];
newcrc[10] = d[69] ^ d[68] ^ d[65] ^ d[64] ^ d[54] ^ d[50] ^ d[39] ^ d[38] ^ d[37] ^ d[36] ^ d[24] ^ d[22] ^ d[9] ^ d[8] ^ c[8] ^ c[9] ^ c[12] ^ c[13];
newcrc[11] = d[70] ^ d[69] ^ d[66] ^ d[65] ^ d[55] ^ d[51] ^ d[40] ^ d[39] ^ d[38] ^ d[37] ^ d[25] ^ d[23] ^ d[10] ^ d[9] ^ c[9] ^ c[10] ^ c[13] ^ c[14];
newcrc[12] = d[71] ^ d[70] ^ d[67] ^ d[66] ^ d[56] ^ d[52] ^ d[41] ^ d[40] ^ d[39] ^ d[38] ^ d[26] ^ d[24] ^ d[11] ^ d[10] ^ c[0] ^ c[10] ^ c[11] ^ c[14] ^ c[15];
newcrc[13] = d[71] ^ d[68] ^ d[67] ^ d[57] ^ d[53] ^ d[42] ^ d[41] ^ d[40] ^ d[39] ^ d[27] ^ d[25] ^ d[12] ^ d[11] ^ c[1] ^ c[11] ^ c[12] ^ c[15];
newcrc[14] = d[69] ^ d[68] ^ d[58] ^ d[54] ^ d[43] ^ d[42] ^ d[41] ^ d[40] ^ d[28] ^ d[26] ^ d[13] ^ d[12] ^ c[2] ^ c[12] ^ c[13];
newcrc[15] = d[71] ^ d[70] ^ d[68] ^ d[67] ^ d[66] ^ d[65] ^ d[64] ^ d[63] ^ d[62] ^ d[61] ^ d[60] ^ d[59] ^ d[54] ^ d[53] ^ d[52] ^ d[51] ^ d[50] ^ d[49] ^ d[48] ^ d[47] ^ d[46] ^ d[45] ^ d[44] ^ d[42] ^ d[40] ^ d[39] ^ d[38] ^ d[37] ^ d[36] ^ d[35] ^ d[34] ^ d[33] ^ d[32] ^ d[31] ^ d[30] ^ d[29] ^ d[26] ^ d[25] ^ d[24] ^ d[23] ^ d[22] ^ d[21] ^ d[20] ^ d[19] ^ d[18] ^ d[17] ^ d[16] ^ d[15] ^ d[14] ^ d[12] ^ d[11] ^ d[10] ^ d[9] ^ d[8] ^ d[7] ^ d[6] ^ d[5] ^ d[4] ^ d[3] ^ d[2] ^ d[1] ^ d[0] ^ c[3] ^ c[4] ^ c[5] ^ c[6] ^ c[7] ^ c[8] ^ c[9] ^ c[10] ^ c[11] ^ c[12] ^ c[14] ^ c[15];
nextCRC16_D72 = newcrc;
end
endfunction
endmodule
|
module IMPOR(
output reg [2:0] out,
output reg out_valid,
output reg ready,
input [2:0] in,
input [2:0] mode,
input in_valid,
input clk,
input rst_n
);
reg sta;
reg [2:0] sta10, sta11, sta12, sta13, sta14, sta15, sta16, sta17, sta18;
wire [2:0] sta20, sta21, sta22, sta23, sta24, sta25, sta26, sta27, sta28;
reg [20:0] cnt1, cnt2;
reg rst;
assign sta20 = sta10;
assign sta21 = sta11;
assign sta22 = sta12;
assign sta23 = sta13;
assign sta24 = sta14;
assign sta25 = sta15;
assign sta26 = sta16;
assign sta27 = sta17;
assign sta28 = sta18;
// rst, ready
always@(posedge clk or negedge rst_n) begin
if(rst_n == 0) begin
rst <= 0;
ready <= 1;
end else if(rst == 1) begin
rst <= 0;
ready <= 1;
end else if(cnt2 == 10) rst <= 1;
else;
end // end of always
// cnt1, cnt2
always@(posedge clk or negedge rst_n) begin
if(rst_n == 0) begin cnt1 <= 0; cnt2 <= 0; end
else if(rst == 1) begin cnt1 <= 0; cnt2 <= 0; end
else if(in_valid == 1) cnt1 <= cnt1+1;
else if(sta == 1 && in_valid == 0) cnt2 <= cnt2+1;
else;
end // end of always
// sta
always@(posedge clk or negedge rst_n) begin
if(rst_n == 0) begin
sta <= 0;
sta10 <= 0; sta11 <= 0; sta12 <= 0; sta13 <= 0; sta14 <= 0; sta15 <= 0; sta16 <= 0; sta17 <= 0; sta18 <= 0;
end else if(rst == 1) begin
sta <= 0;
sta10 <= 0; sta11 <= 0; sta12 <= 0; sta13 <= 0; sta14 <= 0; sta15 <= 0; sta16 <= 0; sta17 <= 0; sta18 <= 0;
end else if(in_valid == 1) begin
sta <= 1;
case(cnt1)
0: sta10 <= in;
1: sta11 <= in;
2: sta12 <= in;
3: sta13 <= in;
4: sta14 <= in;
5: sta15 <= in;
6: sta16 <= in;
7: sta17 <= in;
8: sta18 <= in;
default: begin
case(mode)
1: begin
sta10 <= sta22;
sta11 <= sta21;
sta12 <= sta20;
sta13 <= sta25;
sta14 <= sta24;
sta15 <= sta23;
sta16 <= sta28;
sta17 <= sta27;
sta18 <= sta26;
end
2: begin
sta10 <= sta26;
sta11 <= sta27;
sta12 <= sta28;
sta13 <= sta23;
sta14 <= sta24;
sta15 <= sta25;
sta16 <= sta20;
sta17 <= sta21;
sta18 <= sta22;
end
3: begin
sta10 <= sta22;
sta11 <= sta25;
sta12 <= sta28;
sta13 <= sta21;
sta14 <= sta24;
sta15 <= sta27;
sta16 <= sta20;
sta17 <= sta23;
sta18 <= sta26;
end
4: begin
sta10 <= sta26;
sta11 <= sta23;
sta12 <= sta20;
sta13 <= sta27;
sta14 <= sta24;
sta15 <= sta21;
sta16 <= sta28;
sta17 <= sta25;
sta18 <= sta22;
end
5: begin
if(sta20 == 7) sta10 <= sta20;
else sta10 <= sta20+1;
sta11 <= sta21;
sta12 <= sta22;
if(sta23 == 7) sta13 <= sta23;
else sta13 <= sta23+1;
sta14 <= sta24;
sta15 <= sta25;
if(sta26 == 7) sta16 <= sta26;
else sta16 <= sta26+1;
sta17 <= sta27;
sta18 <= sta28;
end
6: begin
sta10 <= sta20;
if(sta21 == 7) sta11 <= sta21;
else sta11 <= sta21+1;
sta12 <= sta22;
sta13 <= sta23;
if(sta24 == 7) sta14 <= sta24;
else sta14 <= sta24+1;
sta15 <= sta25;
sta16 <= sta26;
if(sta27 == 7) sta17 <= sta27;
else sta17 <= sta27+1;
sta18 <= sta28;
end
7: begin
sta10 <= sta20;
sta11 <= sta21;
if(sta22 == 7) sta12 <= sta22;
else sta12 <= sta22+1;
sta13 <= sta23;
sta14 <= sta24;
if(sta25 == 7) sta15 <= sta25;
else sta15 <= sta25+1;
sta16 <= sta26;
sta17 <= sta27;
if(sta28 == 7) sta18 <= sta28;
else sta18 <= sta28+1;
end
default: begin
sta10 <= sta20;
sta11 <= sta21;
sta12 <= sta22;
sta13 <= sta23;
sta14 <= sta24;
sta15 <= sta25;
sta16 <= sta26;
sta17 <= sta27;
sta18 <= sta28;
end
endcase
end
endcase
end else;
end // end of always
// out, out_valid
always@(posedge clk or negedge rst_n) begin
if(rst_n == 0) begin out <= 0; out_valid <= 0; end
else if(rst == 1) begin out <= 0; out_valid <= 0; end
else if(sta == 1 && in_valid == 0) begin
case(cnt2)
1: begin
out_valid <= 1;
out <= sta10;
end
2: begin
out_valid <= 1;
out <= sta11;
end
3: begin
out_valid <= 1;
out <= sta12;
end
4: begin
out_valid <= 1;
out <= sta13;
end
5: begin
out_valid <= 1;
out <= sta14;
end
6: begin
out_valid <= 1;
out <= sta15;
end
7: begin
out_valid <= 1;
out <= sta16;
end
8: begin
out_valid <= 1;
out <= sta17;
end
9: begin
out_valid <= 1;
out <= sta18;
end
default: begin
out_valid <= 0;
end
endcase
end else;
end // end of always
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O21BAI_2_V
`define SKY130_FD_SC_HS__O21BAI_2_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog wrapper for o21bai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o21bai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o21bai_2 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
sky130_fd_sc_hs__o21bai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o21bai_2 (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o21bai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O21BAI_2_V
|
#include <bits/stdc++.h> using namespace std; int main(void) { cin.sync_with_stdio(false); long long k[3]; int t[3]; int n, i, j; for (i = 0; i < 3; i++) cin >> k[i]; for (i = 0; i < 3; i++) cin >> t[i]; cin >> n; vector<long long> a(n); vector<long long> b(n); for (i = 0; i < n; i++) { cin >> a[i]; b[i] = a[i]; } for (j = 0; j < 3; j++) if (k[j] > n) k[j] = n; for (j = 0; j < 3; j++) { priority_queue<long long, vector<long long>, greater<long long> > Q; for (i = 0; i < k[j]; i++) { Q.push(0); } for (i = 0; i < n; i++) { long long p = Q.top(); Q.pop(); if (p < b[i]) p = b[i]; b[i] = p + t[j]; Q.push(b[i]); } } long long ans = 0; for (i = 0; i < n; i++) { if (b[i] - a[i] > ans) ans = b[i] - a[i]; } cout << ans << endl; return 0; } |
module projetoPessoal_TB;
integer a;
wire [1:0] ledVerde, ledVermelho;
wire [6:0] display;
reg clock;
inicial i( a[3], a[2], a[1], a[0], ledVerde, ledVermelho, display, clock );
//Alterando clock
always begin
clock <= 0;
#25;
clock <= 1;
#25;
end
initial begin
$display("\tPorta Giratorias\n");
$display(" Estado | Entrada | LG | LR");
$display("----------------------------");
//Estado A
a = 0; #50 // a = 0000
$display( " A | %x%x%x%x | %x%x | %x%x", a[3], a[2], a[1], a[0], ledVerde[1], ledVerde[0], ledVermelho[1], ledVermelho[0] );
//Estado B
a = 12; #100 // a = 1100
$display( " B | %x%x%x%x | %x%x | %x%x", a[3], a[2], a[1], a[0], ledVerde[1], ledVerde[0], ledVermelho[1], ledVermelho[0] );
//Estado C
a = 13; #100 // a = 1101
$display( " C | %x%x%x%x | %x%x | %x%x", a[3], a[2], a[1], a[0], ledVerde[1], ledVerde[0], ledVermelho[1], ledVermelho[0] );
//Estado D
a = 6; #100 // a = 0110
$display( " D | %x%x%x%x | %x%x | %x%x", a[3], a[2], a[1], a[0], ledVerde[1], ledVerde[0], ledVermelho[1], ledVermelho[0] );
//Estado E
a = 10; #100 // a = 1010
$display( " E | %x%x%x%x | %x%x | %x%x", a[3], a[2], a[1], a[0], ledVerde[1], ledVerde[0], ledVermelho[1], ledVermelho[0] );
//Estado A
a = 8; #100 // a = 1000
$display( " A | %x%x%x%x | %x%x | %x%x", a[3], a[2], a[1], a[0], ledVerde[1], ledVerde[0], ledVermelho[1], ledVermelho[0] );
end
endmodule
|
#include <bits/stdc++.h> using namespace std; char s1[100100], s2[100100]; long long ini; long long mod(long long a) { return ((a % 1000000007LL) + 1000000007LL) % 1000000007LL; } long long func(char* s, int t, bool som) { long long r = 0; long long ul = 0; long long soma = 0, ls = ini; long long qt = 0LL; bool tem = false; long long sum, lst, val, bas, qtd; sum = lst = ini; val = 0; bas = 3LL; qtd = 1LL; for (int i = t - 1, j = 0; i >= 0; i--, j++) { ul = (ul * 10 + s[j] - 0 ) % 1000000007LL; long long bas2 = (bas * bas) % 1000000007LL; if (s[i] == 7 ) { if (qt > 0) r = (r + ((qt - 1) * bas2) % 1000000007LL + (bas * (2 * soma - ls - ini)) % 1000000007LL + (lst * (ini + bas)) % 1000000007LL) % 1000000007LL; r = (r + val) % 1000000007LL; soma = (soma + sum + qt * bas) % 1000000007LL; qt = (qt + qtd) % 1000000007LL; if (tem) ls = (ls + bas) % 1000000007LL; tem = true; } else if (!tem) ls = (ls + bas) % 1000000007LL; val = (2 * val + (lst * (bas + ini)) % 1000000007LL + (bas2 * (qtd - 1)) % 1000000007LL + (bas * (2 * sum - lst - ini)) % 1000000007LL) % 1000000007LL; sum = (2 * sum + qtd * bas) % 1000000007LL; lst = (lst + bas) % 1000000007LL; bas = (bas * 10) % 1000000007LL; qtd = (qtd * 2) % 1000000007LL; } if (tem) return (r + ul * ls) % 1000000007LL; return r; } int main() { int tam; scanf( %s %s , s1, s2); tam = strlen(s1); ini = 0; for (int i = 0; i < tam; i++) ini = (ini * 10 + 4LL) % 1000000007LL; cout << mod(func(s2, tam, true) - func(s1, tam, false)) << endl; return 0; } |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:5000000000 ) const long long mod = 1000000007; long long Inf = (long long)2e9; long long LINF = (long long)1e18 + 1e17; using namespace std; int main() { ios::sync_with_stdio(false); int n; cin >> n; vector<long long> a(n); vector<bool> can(n, true); map<long long, set<int>> pos; for (int(i) = 0; (i) < n; (i)++) { cin >> a[i]; pos[a[i]].insert(i); } int k = n; while (pos.size()) { if (pos.begin()->second.size() < 2) { pos.erase(pos.begin()); continue; } int i1 = *pos.begin()->second.begin(); pos.begin()->second.erase(i1); int i2 = *pos.begin()->second.begin(); pos.begin()->second.erase(i2); long long x = pos.begin()->first; k--; can[i1] = false; pos[2 * x].insert(i2); a[i2] = 2 * x; } cout << k << endl; for (int(i) = 0; (i) < n; (i)++) if (can[i]) cout << a[i] << ; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__HA_BEHAVIORAL_V
`define SKY130_FD_SC_LS__HA_BEHAVIORAL_V
/**
* ha: Half adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__ha (
COUT,
SUM ,
A ,
B
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out_COUT;
wire xor0_out_SUM ;
// Name Output Other arguments
and and0 (and0_out_COUT, A, B );
buf buf0 (COUT , and0_out_COUT );
xor xor0 (xor0_out_SUM , B, A );
buf buf1 (SUM , xor0_out_SUM );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__HA_BEHAVIORAL_V |
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author:
* Description:
*
* Changes:
*/
module my_function (
input clk,
input rst
//output reg [7:0] o_reg_example
//input [7:0] i_reg_example
);
//local parameters
localparam PARAM1 = 32'h00000000;
//registes/wires
//submodules
//asynchronous logic
//synchronous logic
endmodule
|
#include <bits/stdc++.h> using namespace std; void getre() { int x = 0; printf( %d n , 1 / x); } void gettle() { int res = 1; while (1) res <<= 1; printf( %d n , res); } template <typename T, typename S> inline bool upmin(T &a, const S &b) { return a > b ? a = b, 1 : 0; } template <typename T, typename S> inline bool upmax(T &a, const S &b) { return a < b ? a = b, 1 : 0; } template <typename N, typename PN> inline N flo(N a, PN b) { return a >= 0 ? a / b : -((-a - 1) / b) - 1; } template <typename N, typename PN> inline N cei(N a, PN b) { return a > 0 ? (a - 1) / b + 1 : -(-a / b); } template <typename N> N gcd(N a, N b) { return b ? gcd(b, a % b) : a; } template <typename N> inline int sgn(N a) { return a > 0 ? 1 : (a < 0 ? -1 : 0); } inline void gn(long long &x) { int sg = 1; char c; while (((c = getchar()) < 0 || c > 9 ) && c != - ) ; c == - ? (sg = -1, x = 0) : (x = c - 0 ); while ((c = getchar()) >= 0 && c <= 9 ) x = x * 10 + c - 0 ; x *= sg; } inline void gn(int &x) { long long t; gn(t); x = t; } inline void gn(unsigned long long &x) { long long t; gn(t); x = t; } inline void gn(double &x) { double t; scanf( %lf , &t); x = t; } inline void gn(long double &x) { double t; scanf( %lf , &t); x = t; } inline void gs(char *s) { scanf( %s , s); } inline void gc(char &c) { while ((c = getchar()) > 126 || c < 33) ; } inline void pc(char c) { putchar(c); } inline long long sqr(long long a) { return a * a; } inline double sqrf(double a) { return a * a; } const int inf = 0x3f3f3f3f; const double pi = 3.14159265358979323846264338327950288L; const double eps = 1e-6; int n; long long x[111111], y[111111], z[111111]; int out = 0; bool check(long long d, int par) { long long lz, rz; lz = -7e18, rz = 7e18; long long l10, r10, l20, r20; long long l1, r1, l2, r2; l1 = l2 = -7e18; r1 = r2 = 7e18; for (int i = (1), _ed = (n + 1); i < _ed; i++) { upmax(l1, x[i] + y[i] + z[i] - d); upmin(r1, x[i] + y[i] + z[i] + d); upmax(l2, x[i] + y[i] - z[i] - d); upmin(r2, x[i] + y[i] - z[i] + d); } if ((l1 & 1) != par) l1++; if ((l2 & 1) != par) l2++; if ((r1 & 1) != par) r1--; if ((r2 & 1) != par) r2--; if (l1 > r1 || l2 > r2) return 0; upmin(rz, (r1 - l2) / 2ll); upmax(lz, (l1 - r2) / 2ll); l10 = l1; r10 = r1; l20 = l2; r20 = r2; l1 = l2 = -7e18; r1 = r2 = 7e18; for (int i = (1), _ed = (n + 1); i < _ed; i++) { upmax(l1, x[i] - y[i] + z[i] - d); upmin(r1, x[i] - y[i] + z[i] + d); upmax(l2, x[i] - y[i] - z[i] - d); upmin(r2, x[i] - y[i] - z[i] + d); } if ((l1 & 1) != par) l1++; if ((l2 & 1) != par) l2++; if ((r1 & 1) != par) r1--; if ((r2 & 1) != par) r2--; if (l1 > r1 || l2 > r2) return 0; upmin(rz, (r1 - l2) / 2ll); upmax(lz, (l1 - r2) / 2ll); if (lz > rz) return 0; long long z = lz; long long lplu = max(l10 - z, l20 + z); long long rplu = min(r10 - z, r20 + z); long long lmin = max(l1 - z, l2 + z); long long rmin = min(r1 - z, r2 + z); long long x = (lplu + lmin) / 2, y = (lplu - lmin) / 2; if (out) { out = 0; printf( %I64d %I64d %I64d n , x, y, z); } return 1; } int main() { int te; gn(te); while (te--) { gn(n); for (int i = (1), _ed = (n + 1); i < _ed; i++) { gn(x[i]); gn(y[i]); gn(z[i]); } long long l = 0, r = 3.1e18; while (l <= r) { long long mid = l + r >> 1; if (check(mid, 0) || check(mid, 1)) r = mid - 1; else l = mid + 1; } out = 1; check(l, 0); check(l, 1); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR4B_BLACKBOX_V
`define SKY130_FD_SC_HD__OR4B_BLACKBOX_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__or4b (
X ,
A ,
B ,
C ,
D_N
);
output X ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR4B_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; long long int a[200][3]; int main() { ios ::sync_with_stdio(false); cin.tie(0); ; long long int i, k, l, n, j; cin >> n; for (i = 0; i <= n - 1; i++) cin >> a[i][0] >> a[i][1]; cin >> j; for (i = 0; i <= n - 1; i++) if (j >= a[i][0] && j <= a[i][1]) { cout << n - i << endl; return 0; } return 0; } |
#include <bits/stdc++.h> using namespace std; struct Point { long long x, y; int id; Point() {} Point(long long a, long long b, int c) : x(a), y(b), id(c) {} Point operator-(Point b) { return Point(x - b.x, y - b.y, 0); } bool operator<(const Point &b) const { return (x != b.x) ? x < b.x : y < b.y; } }; long long cross(Point x, Point y) { return x.x * y.y - x.y * y.x; } bool in[2005]; int gethull(Point *p, int n, int s, bool v) { static Point st[2005], hull[2005]; int top = 0, cnt = 0; for (int i = 1; i <= n; i++) { while (top > 1 && cross(p[i] - st[top], st[top] - st[top - 1]) >= 0) top--; st[++top] = p[i]; } for (int i = 1; i < top; i++) hull[++cnt] = st[i]; top = 0; for (int i = 1; i <= n; i++) { while (top > 1 && cross(p[i] - st[top], st[top] - st[top - 1]) <= 0) top--; st[++top] = p[i]; } for (int i = top; i > 1; i--) hull[++cnt] = st[i]; for (int i = 1; i <= cnt; i++) if (hull[i].id == s) { in[hull[i].id] = 1; return (v) ? hull[(i - 1 + cnt - 1) % cnt + 1].id : hull[i % cnt + 1].id; } } Point p[2005], q[2005]; char str[2005]; int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) { int x, y; scanf( %d%d , &x, &y); p[i] = Point(x, y, i); } scanf( %s , str + 1); str[n - 1] = L ; sort(p + 1, p + n + 1); int cur = p[1].id; for (int i = 1; i < n; i++) { int cnt = 0; for (int j = 1; j <= n; j++) if (!in[p[j].id]) q[++cnt] = p[j]; printf( %d , cur); cur = gethull(q, cnt, cur, (str[i] == R )); } printf( %d n , cur); return 0; } |
// Copyright (c) 2014, Segiusz 'q3k' Bazanski <>
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
module qm_fetch(
/// datapath
// input PC to assume
input wire [31:0] di_PC,
// output instruction register
output reg [31:0] do_IR,
// output to next PC
output reg [31:0] do_NextPC,
// icache connectivity
output wire [31:0] icache_address,
input wire icache_hit,
input wire icache_should_stall,
input wire [31:0] icache_data
);
assign icache_address = di_PC;
always @(*) begin
if (icache_should_stall && !icache_hit) begin
do_NextPC = di_PC;
do_IR = 0;
end else begin
do_NextPC = di_PC + 4;
do_IR = icache_data;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct node { long long int word, prefix; node *child[2]; node() { word = prefix = 0; child[0] = child[1] = NULL; } }; void insert(node *root, long long int x, long long int bit) { root->prefix += 1; if (bit < 0) { root->word += 1; return; } bool b = (x & (1 << bit)); if (root->child[b] == NULL) { root->child[b] = new node(); } insert(root->child[b], x, bit - 1); } node *deleteit(node *root, long long int x, long long int bit) { if (root == NULL) { return NULL; } root->prefix -= 1; if (bit < 0) { root->word -= 1; if (root->word == 0 && root->prefix == 0) { delete root; return NULL; } return root; } bool b = (x & (1 << bit)); root->child[b] = deleteit(root->child[b], x, bit - 1); if (root->word == 0 && root->prefix == 0) { delete root; return NULL; } return root; } long long int query(node *root, long long int x, long long int k, long long int bit, long long int ans) { if (bit < 0 || root == NULL) { return ans; } bool a = (x & (1 << bit)), a_complement = (!a); bool b = (k & (1 << bit)), b_complement = (!b); if (b == true) { if (root->child[a] != NULL) { ans += root->child[a]->prefix; } return query(root->child[a_complement], x, k, bit - 1, ans); } else { return query(root->child[a], x, k, bit - 1, ans); } return ans; } int main() { ios::sync_with_stdio(0); cin.tie(0); node *root = new node; long long int q, x, y, t; cin >> q; for (long long int i = 0; i < q; i++) { cin >> t >> x; if (t == 1) { insert(root, x, 31); } else if (t == 2) { root = deleteit(root, x, 31); if (root == NULL) { root = new node; } } else { cin >> y; cout << query(root, x, y, 31, 0) << n ; } } return 0; } |
#include <bits/stdc++.h> using namespace std; struct Time { long long deno, num; inline long long gcd(long long a, long long b) { return !b ? a : gcd(b, a % b); } inline void simplify() { long long g = gcd(abs(deno), abs(num)); deno /= g; num /= g; if (deno < 0) { deno *= -1; num *= -1; } } Time() {} Time(long long n, long long d) : num(n), deno(d) { simplify(); } inline bool operator<(const Time &t) const { return num * t.deno < t.num * deno; } inline bool operator!=(const Time &t) const { return num * t.deno != t.num * deno; } }; pair<Time, Time> s[100010]; pair<Time, int> ds[100010]; int d[100010]; struct BIT { int f[100010]; BIT() { fill(f, f + 100010, 0); } inline int lowbit(int x) { return (x & -x); } inline void add(int p, int v) { for (++p; p < 100010; p += lowbit(p)) f[p] += v; } inline int sum(int p) { int ret = 0; for (++p; p; p -= lowbit(p)) ret += f[p]; return ret; } inline int sum(int l, int r) { return sum(r) - sum(l - 1); } } bit; int n, w; long long v, x; int main() { cin >> n >> w; for (int i = 0; i < n; i++) { cin >> x >> v; s[i] = make_pair(Time(-x, v - w), Time(-x, v + w)); } for (int i = 0; i < n; i++) s[i].second.num *= -1; sort(s, s + n); for (int i = 0; i < n; i++) s[i].second.num *= -1; for (int i = 0; i < n; i++) ds[i] = make_pair(s[i].second, i); sort(ds, ds + n); for (int i = 0, rk = -1; i < n; i++) { if (!i || ds[i].first != ds[i - 1].first) rk++; d[ds[i].second] = rk; } long long ans = 0; for (int i = 0; i < n; i++) { ans += bit.sum(d[i], 100010 - 1); bit.add(d[i], 1); } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const long double pi = acos(-1.0), eps = 1e-10; long double det(long double a11, long double a12, long double a21, long double a22) { return a11 * a22 - a12 * a21; } struct pt { long double x, y; pt(long double x, long double y) : x(x), y(y) {} }; struct line { long double a, b, c; line(long double x1, long double y1, long double x2, long double y2) { a = y1 - y2; b = x2 - x1; c = a * x1 + b * y1; } line(long double a, long double b, long double c) : a(a), b(b), c(c) {} void transpose(pt p) { c += a * p.x + b * p.y; } }; struct circle { long double x, y, r; circle(long double x, long double y, long double r) : x(x), y(y), r(r) {} }; long double dist(long double x1, long double y1, long double x2, long double y2) { long double dx = x1 - x2, dy = y1 - y2; return sqrt(dx * dx + dy * dy); } vector<pt> lineCircleIntersection(line l, pt center, long double r) { line t(l); t.transpose(pt(-center.x, -center.y)); long double a = t.a, b = t.b, c = -t.c; long double x0 = -a * c / (a * a + b * b), y0 = -b * c / (a * a + b * b); vector<pt> res; if (c * c > r * r * (a * a + b * b) + eps) { } else if (fabs(c * c - r * r * (a * a + b * b)) < eps) { res.push_back(pt(x0 + center.x, y0 + center.y)); } else { long double d = r * r - c * c / (a * a + b * b); long double mult = sqrt(d / (a * a + b * b)); long double ax, ay, bx, by; ax = x0 + b * mult; bx = x0 - b * mult; ay = y0 - a * mult; by = y0 + a * mult; res.push_back(pt(ax + center.x, ay + center.y)); res.push_back(pt(bx + center.x, by + center.y)); } return res; } vector<pt> circleCircleIntersection(circle c1, circle c2) { long double x = c1.x - c2.x, y = c1.y - c2.y; vector<pt> res = lineCircleIntersection( line(2 * x, 2 * y, x * x + y * y + c2.r * c2.r - c1.r * c1.r), pt(0, 0), c2.r); for (int i = 0; i < (int)res.size(); i++) { res[i].x += c2.x; res[i].y += c2.y; } return res; } bool inside(pt p, circle c) { return dist(p.x, p.y, c.x, c.y) <= c.r + eps; } bool intersects(circle c1, circle c2, circle c3) { c1.r += eps; c2.r += eps; c3.r += eps; vector<pt> p[3]; p[0] = circleCircleIntersection(c1, c2); p[1] = circleCircleIntersection(c2, c3); p[2] = circleCircleIntersection(c3, c1); p[0].push_back(pt(c1.x, c1.y)); p[1].push_back(pt(c2.x, c2.y)); p[2].push_back(pt(c3.x, c3.y)); for (int i = 0; i < 3; i++) { for (size_t j = 0; j < p[i].size(); j++) { if (inside(p[i][j], c1) && inside(p[i][j], c2) && inside(p[i][j], c3)) { return true; } } } return false; } long double t1, t2, cx, cy, hx, hy, sx, sy; void solve() { long double d1 = dist(hx, hy, sx, sy), d2 = dist(sx, sy, cx, cy), d3 = dist(cx, cy, hx, hy); long double l1 = d1 + d2 + t1, l2 = d3 + t2; cout << fixed << setprecision(10); if (l2 >= d1 + d2) { cout << min(l1, l2) << endl; } else { long double L = 0, R = min(l1, l2); while (fabs(L - R) > eps) { long double r1 = (L + R) / 2, r2 = max(0. * l1, l1 - d1 - r1), r3 = max(0. * l2, l2 - r1); if (intersects(circle(cx, cy, r1), circle(sx, sy, r2), circle(hx, hy, r3))) { L = r1; } else { R = r1; } } cout << L + eps << endl; } } int main() { while (cin >> t1 >> t2 >> cx >> cy >> hx >> hy >> sx >> sy) { solve(); } } |
#include <bits/stdc++.h> int Abs(int x) { return x < 0 ? -x : x; } int main() { int i, N, ans = 0, sum = 0, c = 0, d = 0; double p; scanf( %d , &N); for (i = 0; i < 2 * N; i++) { scanf( %lf , &p); int t = ((int)(p * 1000 + 0.1)) % 1000; if (!t) c++; sum += t; } ans = 1000 * N - sum; int q = Abs(ans); for (i = 1; i <= c; i++) { if (q > Abs(ans - i * 1000)) q = Abs(ans - i * 1000); } printf( %d.%03d n , q / 1000, q % 1000); return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013 by Sean Moore.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [7:0] tripline = crc[7:0];
/*AUTOWIRE*/
wire valid;
wire [3-1:0] value;
PriorityChoice #(.OCODEWIDTH(3))
pe (.out(valid), .outN(value[2:0]), .tripline(tripline));
// Aggregate outputs into a single result vector
wire [63:0] result = {60'h0, valid, value};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hc5fc632f816568fb
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module PriorityChoice (out, outN, tripline);
parameter OCODEWIDTH = 1;
localparam CODEWIDTH=OCODEWIDTH-1;
localparam SCODEWIDTH= (CODEWIDTH<1) ? 1 : CODEWIDTH;
output reg out;
output reg [OCODEWIDTH-1:0] outN;
input wire [(1<<OCODEWIDTH)-1:0] tripline;
wire left;
wire [SCODEWIDTH-1:0] leftN;
wire right;
wire [SCODEWIDTH-1:0] rightN;
generate
if(OCODEWIDTH==1) begin
assign left = tripline[1];
assign right = tripline[0];
always @(*) begin
out = left || right ;
if(right) begin outN = {1'b0}; end
else begin outN = {1'b1}; end
end
end else begin
PriorityChoice #(.OCODEWIDTH(OCODEWIDTH-1))
leftMap
(
.out(left),
.outN(leftN),
.tripline(tripline[(2<<CODEWIDTH)-1:(1<<CODEWIDTH)])
);
PriorityChoice #(.OCODEWIDTH(OCODEWIDTH-1))
rightMap
(
.out(right),
.outN(rightN),
.tripline(tripline[(1<<CODEWIDTH)-1:0])
);
always @(*) begin
if(right) begin
out = right;
outN = {1'b0, rightN[OCODEWIDTH-2:0]};
end else begin
out = left;
outN = {1'b1, leftN[OCODEWIDTH-2:0]};
end
end
end
endgenerate
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module pfpu #(
parameter csr_addr = 4'h0
) (
input sys_clk,
input sys_rst,
/* Control interface */
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output [31:0] csr_do,
output irq,
/* Wishbone DMA master (write only, sel=1111) */
output [31:0] wbm_dat_o,
output [31:0] wbm_adr_o,
output wbm_cyc_o,
output wbm_stb_o,
input wbm_ack_i
);
wire alu_rst;
wire [31:0] a;
wire [31:0] b;
wire ifb;
wire [3:0] opcode;
wire [31:0] r;
wire r_valid;
wire dma_en;
wire err_collision;
pfpu_alu alu(
.sys_clk(sys_clk),
.alu_rst(alu_rst), /* < from sequencer */
.a(a), /* < from register file */
.b(b), /* < from register file */
.ifb(ifb), /* < from register file */
.opcode(opcode), /* < from program memory */
.r(r), /* < to register file */
.r_valid(r_valid), /* < to register file */
.dma_en(dma_en), /* < to DMA engine and sequencer */
.err_collision(err_collision) /* < to control interface */
);
wire c_en;
wire [6:0] a_addr;
wire [6:0] b_addr;
wire [6:0] w_addr;
wire [6:0] cr_addr;
wire [31:0] cr_dr;
wire [31:0] cr_dw;
wire cr_w_en;
wire [31:0] r0;
wire [31:0] r1;
wire err_stray;
pfpu_regf regf(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.ifb(ifb), /* < to ALU */
.a(a), /* < to ALU */
.b(b), /* < to ALU */
.r(r), /* < to ALU */
.w_en(r_valid), /* < from ALU */
.a_addr(a_addr), /* < from program memory */
.b_addr(b_addr), /* < from program memory */
.w_addr(w_addr), /* < from program memory */
.c_en(c_en), /* < from sequencer */
.c_addr(cr_addr), /* < from control interface */
.c_do(cr_dr), /* < to control interface */
.c_di(cr_dw), /* < from control interface */
.c_w_en(cr_w_en), /* < from control interface */
.r0(r0), /* < from counters */
.r1(r1), /* < from counters */
.err_stray(err_stray) /* < to control interface */
);
wire [28:0] dma_base;
wire dma_busy;
wire dma_ack;
pfpu_dma dma(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.dma_en(dma_en), /* < from ALU */
.dma_base(dma_base), /* < from control interface */
.x(r0[6:0]), /* < from counters */
.y(r1[6:0]), /* < from counters */
.dma_d1(a), /* < from register file */
.dma_d2(b), /* < from register file */
.busy(dma_busy), /* < to sequencer */
.ack(dma_ack), /* < to sequencer */
.wbm_dat_o(wbm_dat_o),
.wbm_adr_o(wbm_adr_o),
.wbm_cyc_o(wbm_cyc_o),
.wbm_stb_o(wbm_stb_o),
.wbm_ack_i(wbm_ack_i)
);
wire vfirst;
wire vnext;
wire [6:0] hmesh_last;
wire [6:0] vmesh_last;
wire vlast;
pfpu_counters counters(
.sys_clk(sys_clk),
.first(vfirst), /* < from sequencer */
.next(vnext), /* < from sequencer */
.hmesh_last(hmesh_last), /* < from control interface */
.vmesh_last(vmesh_last), /* < from control interface */
.r0(r0), /* < to register file */
.r1(r1), /* < to register file */
.last(vlast) /* < to sequencer */
);
wire pcount_rst;
wire [1:0] cp_page;
wire [8:0] cp_offset;
wire [31:0] cp_dr;
wire [31:0] cp_dw;
wire cp_w_en;
wire [10:0] pc;
pfpu_prog prog(
.sys_clk(sys_clk),
.count_rst(pcount_rst), /* < from sequencer */
.a_addr(a_addr), /* < to ALU */
.b_addr(b_addr), /* < to ALU */
.opcode(opcode), /* < to ALU */
.w_addr(w_addr), /* < to ALU */
.c_en(c_en), /* < from sequencer */
.c_page(cp_page), /* < from control interface */
.c_offset(cp_offset), /* < from control interface */
.c_do(cp_dr), /* < to control interface */
.c_di(cp_dw), /* < from control interface */
.c_w_en(cp_w_en), /* < from control interface */
.pc(pc) /* < to control interface */
);
wire start;
wire busy;
pfpu_seq seq(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.alu_rst(alu_rst), /* < to ALU */
.dma_en(dma_en), /* < from ALU */
.dma_busy(dma_busy), /* < from DMA engine */
.dma_ack(dma_ack), /* < from DMA engine */
.vfirst(vfirst), /* < to counters */
.vnext(vnext), /* < to counters and control interface */
.vlast(vlast), /* < from counters */
.pcount_rst(pcount_rst), /* < to program memory */
.c_en(c_en), /* < to register file and program memory */
.start(start), /* < from control interface */
.busy(busy) /* < to control interface */
);
pfpu_ctlif #(
.csr_addr(csr_addr)
) ctlif (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.csr_a(csr_a),
.csr_we(csr_we),
.csr_di(csr_di),
.csr_do(csr_do),
.irq(irq),
.start(start), /* < to sequencer */
.busy(busy), /* < from sequencer */
.dma_base(dma_base), /* < to DMA engine */
.hmesh_last(hmesh_last), /* < to counters */
.vmesh_last(vmesh_last), /* < to counters */
.cr_addr(cr_addr), /* < to register file */
.cr_di(cr_dr), /* < from register file */
.cr_do(cr_dw), /* < to register file */
.cr_w_en(cr_w_en), /* < to register file */
.cp_page(cp_page), /* < to program memory */
.cp_offset(cp_offset), /* < to program memory */
.cp_di(cp_dr), /* < from program memory */
.cp_do(cp_dw), /* < to program memory */
.cp_w_en(cp_w_en), /* < to program memory */
.vnext(vnext), /* < from sequencer */
.err_collision(err_collision), /* < from ALU */
.err_stray(err_stray), /* < from register file */
.pc(pc), /* < from program memory */
.wbm_adr_o(wbm_adr_o), /* < from DMA engine */
.wbm_ack_i(wbm_ack_i) /* < from DMA engine */
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k, p, x, y; int a[1010], b[1010]; int i, j; while (scanf( %d%d%d%d%d , &n, &k, &p, &x, &y) != EOF) { int sum = 0; for (i = 0; i < k; i++) { scanf( %d , &a[i]); sum += a[i]; } if (sum > x) { puts( -1 ); continue; } for (i = k; i < n; i++) { a[i] = 1; sum += 1; } int t = k; while (t < n && sum + y - 1 <= x) { a[t++] = y; sum += y - 1; } for (i = 0; i < n; i++) b[i] = a[i]; sort(b, b + n); int m = b[n / 2]; if (sum <= x && m >= y) { for (i = k; i < n - 1; i++) printf( %d , a[i]); printf( %d n , a[n - 1]); } else printf( -1 n ); } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFRTN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__SDFRTN_FUNCTIONAL_PP_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_lp__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intclk , CLK_N );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_lp__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, intclk, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFRTN_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; int vet[1010], dp[2][1010]; const int mod = 998244353; long long soma(long long x, long long y) { x += y; if (x >= mod) x -= mod; return x; } int main() { int n; cin >> n; for (int i = 0; i < n; i++) { cin >> vet[i]; } for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { dp[1][j] = dp[0][j]; } if (vet[i] < n and vet[i] > 0) { dp[1][vet[i]] = soma(soma(dp[0][0], 1), dp[1][vet[i]]); } for (int k = 0; k < n; k++) { dp[1][k] = soma(dp[1][k], dp[0][k + 1]); } swap(dp[0], dp[1]); } cout << dp[0][0] << endl; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFXTP_FUNCTIONAL_V
`define SKY130_FD_SC_LP__SDFXTP_FUNCTIONAL_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`include "../../models/udp_dff_p/sky130_fd_sc_lp__udp_dff_p.v"
`celldefine
module sky130_fd_sc_lp__sdfxtp (
Q ,
CLK,
D ,
SCD,
SCE
);
// Module ports
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_lp__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFXTP_FUNCTIONAL_V |
(* begin hide *)
Require Import Coq.Strings.String.
Require Import Coq.Strings.Ascii.
(* end hide *)
(** Binary numbers are so ubiquitous in Computer Science that
programming languages often have special notations for them. The
most popular one is arguably hexadecimal notation. It is close to
binary representation, since each digit corresponds exactly to
four bits, but it is much more compact. Unfortunately, Coq has no
built-in support for hexadecimal notation. While the language does
allow the user to extend its syntax, this mechanism is not
powerful enough to implement this feature. Coq's own built-in
decimal notation, for instance, is a special case coded directly
in OCaml. In this post, I will show a way to circumvent this
problem by using Coq itself to parse base 16 numbers.
** Reading numbers
The first thing we will need is a Coq function to interpret
hexadecimal notation. As we've seen #<a
href="/posts/2013-03-31-reading-and-writing-numbers-in-coq.html">previously</a>#,
writing such a function is straightforward. The code that follows
is pretty much the same as in our past example, but reworked for
base 16. *)
Open Scope char_scope.
Definition hexDigitToNat (c : ascii) : option nat :=
match c with
| "0" => Some 0
| "1" => Some 1
| "2" => Some 2
| "3" => Some 3
| "4" => Some 4
| "5" => Some 5
| "6" => Some 6
| "7" => Some 7
| "8" => Some 8
| "9" => Some 9
| "a" | "A" => Some 10
| "b" | "B" => Some 11
| "c" | "C" => Some 12
| "d" | "D" => Some 13
| "e" | "E" => Some 14
| "f" | "F" => Some 15
| _ => None
end.
Open Scope string_scope.
Fixpoint readHexNatAux (s : string) (acc : nat) : option nat :=
match s with
| "" => Some acc
| String c s' =>
match hexDigitToNat c with
| Some n => readHexNatAux s' (16 * acc + n)
| None => None
end
end.
Definition readHexNat (s : string) : option nat :=
readHexNatAux s 0.
(** Our function behaves just as expected. *)
Example readHexNat1 : readHexNat "ff" = Some 255.
Proof. reflexivity. Qed.
(** ** Convenient notation
Now that we have a Coq function that reads hexadecimal numbers, we
can use it as our notation. There is a small problem,
though. Since [readHexNat] returns an [option nat], we can't just
use it where a natural number is expected, because the types do
not match. In regular functional programming languages such as
Haskell or OCaml, one could just raise a runtime error when such a
parse error is found. This is not possible in Coq, since all
functions must be total. Instead of doing that, we return a
default number when an error is found. *)
Module FirstTry.
Definition x (s : string) : nat :=
match readHexNat s with
| Some n => n
| None => 0
end.
(** This function allows us to write numbers with nice syntax. *)
Example e1 : x"ff" = 255.
Proof. reflexivity. Qed.
Example e2 : x"a0f" = 2575.
Proof. reflexivity. Qed.
(** Though slightly awkward, this notation is not too different from
the usual [0x] notation present in C and many other languages.
In spite of being simple, this approach has a significant drawback
when compared to languages that understand base 16 numbers
naturally. In those languages, a misspelled number will most
likely result in a parse error, which will probably be caught soon
and fixed. Here, on the other hand, we chose to ignore such
errors. Suppose, for instance, that we mistakingly type 10 with a
capital "O" instead of "0" in our code. Our number would now be
understood as 0. *)
Example e3 : x"1O" = 0.
Proof. reflexivity. Qed.
(** Such errors may not be noticed immediately, and will probably
manifest themselves as problems in other parts of the program,
making it hard to track the real cause. It may seem at this point
that we would either have to accept this limitation and live with
it, or need to patch the Coq source code and implement the new
notation by hand. Luckily, a sane solution exists. *)
End FirstTry.
(** ** Putting the type system to work
There are two key insights that we need here. First, types in Coq
can be manipulated pretty much like any other value in the
language. In particular, this means that functions can take types
as arguments and return other types. This is not too strange: the
familiar [list] type constructor, for instance, is just a function
that takes a type as input and returns the type of lists of that
type. *)
Check list.
(* list
: Type -> Type *)
(** As a more interesting example, one can write a function that takes
some piece of _data_ as input and returns a Coq type. *)
Definition natOrString (b : bool) : Type :=
if b then nat else string.
(** This idea might seem odd when seen for the first time, but it
enables very powerful techniques when combined with a second key
feature. Coq is a _dependently typed_ language, which means that
the return type of a function can depend on values passed to it as
arguments. *)
Definition alwaysZero (b : bool) : natOrString b :=
match b with
| true => 0
| false => "0"
end.
Definition z1 : nat := alwaysZero true.
Definition z2 : string := alwaysZero false.
(** The Coq type checker accepts the first definition because it knows
that [alwaysZero] returns a [nat] when its argument is [true], and
similarly for the second one.
Using this idea, we define a function that extracts the value of
an [option] when it has the form [Some a], but returns an element
of some other arbitrary type otherwise: *)
Definition forceOption A Err (o : option A) (err : Err) : match o with
| Some _ => A
| None => Err
end :=
match o with
| Some a => a
| None => err
end.
(** The type signature of this function looks weird, but nothing
fundamentally complicated is hapenning here. To see how this
function could help us solve our problem, suppose that the Coq
type checker is able to detect statically that the [o] argument
passed to [forceOption] is [Some a]. In this case, the result type
of the computation will be exactly [A], and we will be able to use
it like any other value of [A]: *)
Definition f1 : nat := forceOption nat bool (Some 42) false.
(** If, on the other hand, a [None] is passed to the function, the
return type will be [Err], which is used to signal the occurrence
of an error. Thus, if [Err] and [A] are not the same, type
checking will fail and a type error will be issued. *)
(* Definition f2 : nat := forceOption nat bool None false. *)
(* Toplevel input, characters 43-74:
Error: The term "forceOption nat bool None false" has type
"bool" while it is expected to have type "nat". *)
(** With [forceOption] in hand, it is easy to solve our problem. We
begin by defining a singleton type that represents type errors. *)
Inductive parseError := ParseError.
(** Now, we are ready for our second attempt. *)
Module SecondTry.
Definition x (s : string) :=
forceOption nat parseError (readHexNat s) ParseError.
(** Our new notation behaves as expected on the previous examples. The
type annotations below ([: nat]) are not mandatory; they are just
there to illustrate that the types match. *)
Example e1 : (x"ff" : nat) = 255.
Proof. reflexivity. Qed.
Example e2 : (x"a0f" : nat) = 2575.
Proof. reflexivity. Qed.
(** A parse error will result in a [None], which will be translated to
a [parseError] by [forceOption], and therefore will cause a type
error when used as a [nat]. *)
Example e3 : (x"1O" : parseError) = ParseError.
Proof. reflexivity. Qed.
End SecondTry.
(** ** Summary
We've seen that the expressivity of Coq's type system makes it
possible to encode tricks that would be unnatural or just
impossible in other languages.
As discussed above, in OCaml or Haskell one could trigger an error
when the program encounters an unexpected situation, such as
getting a [None] after parsing a number. While better than just
returning a nonsensical result, like we did in our first attempt,
this solution still only reveals the error at runtime. Using Coq's
dependent types, we were able to detect such errors as type errors
at compile time, without resorting to any external features. *)
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_timer_0 (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 15: 0] readdata;
input [ 2: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 15: 0] writedata;
wire clk_en;
wire control_continuous;
wire control_interrupt_enable;
reg [ 3: 0] control_register;
wire control_wr_strobe;
reg counter_is_running;
wire counter_is_zero;
wire [ 31: 0] counter_load_value;
reg [ 31: 0] counter_snapshot;
reg delayed_unxcounter_is_zeroxx0;
wire do_start_counter;
wire do_stop_counter;
reg force_reload;
reg [ 31: 0] internal_counter;
wire irq;
reg [ 15: 0] period_h_register;
wire period_h_wr_strobe;
reg [ 15: 0] period_l_register;
wire period_l_wr_strobe;
wire [ 15: 0] read_mux_out;
reg [ 15: 0] readdata;
wire snap_h_wr_strobe;
wire snap_l_wr_strobe;
wire [ 31: 0] snap_read_value;
wire snap_strobe;
wire start_strobe;
wire status_wr_strobe;
wire stop_strobe;
wire timeout_event;
reg timeout_occurred;
assign clk_en = 1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
internal_counter <= 32'hC34F;
else if (counter_is_running || force_reload)
if (counter_is_zero || force_reload)
internal_counter <= counter_load_value;
else
internal_counter <= internal_counter - 1;
end
assign counter_is_zero = internal_counter == 0;
assign counter_load_value = {period_h_register,
period_l_register};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
force_reload <= 0;
else if (clk_en)
force_reload <= period_h_wr_strobe || period_l_wr_strobe;
end
assign do_start_counter = start_strobe;
assign do_stop_counter = (stop_strobe ) ||
(force_reload ) ||
(counter_is_zero && ~control_continuous );
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter_is_running <= 1'b0;
else if (clk_en)
if (do_start_counter)
counter_is_running <= -1;
else if (do_stop_counter)
counter_is_running <= 0;
end
//delayed_unxcounter_is_zeroxx0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxcounter_is_zeroxx0 <= 0;
else if (clk_en)
delayed_unxcounter_is_zeroxx0 <= counter_is_zero;
end
assign timeout_event = (counter_is_zero) & ~(delayed_unxcounter_is_zeroxx0);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
timeout_occurred <= 0;
else if (clk_en)
if (status_wr_strobe)
timeout_occurred <= 0;
else if (timeout_event)
timeout_occurred <= -1;
end
assign irq = timeout_occurred && control_interrupt_enable;
//s1, which is an e_avalon_slave
assign read_mux_out = ({16 {(address == 2)}} & period_l_register) |
({16 {(address == 3)}} & period_h_register) |
({16 {(address == 4)}} & snap_read_value[15 : 0]) |
({16 {(address == 5)}} & snap_read_value[31 : 16]) |
({16 {(address == 1)}} & control_register) |
({16 {(address == 0)}} & {counter_is_running,
timeout_occurred});
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= read_mux_out;
end
assign period_l_wr_strobe = chipselect && ~write_n && (address == 2);
assign period_h_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
period_l_register <= 49999;
else if (period_l_wr_strobe)
period_l_register <= writedata;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
period_h_register <= 0;
else if (period_h_wr_strobe)
period_h_register <= writedata;
end
assign snap_l_wr_strobe = chipselect && ~write_n && (address == 4);
assign snap_h_wr_strobe = chipselect && ~write_n && (address == 5);
assign snap_strobe = snap_l_wr_strobe || snap_h_wr_strobe;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter_snapshot <= 0;
else if (snap_strobe)
counter_snapshot <= internal_counter;
end
assign snap_read_value = counter_snapshot;
assign control_wr_strobe = chipselect && ~write_n && (address == 1);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
control_register <= 0;
else if (control_wr_strobe)
control_register <= writedata[3 : 0];
end
assign stop_strobe = writedata[3] && control_wr_strobe;
assign start_strobe = writedata[2] && control_wr_strobe;
assign control_continuous = control_register[1];
assign control_interrupt_enable = control_register;
assign status_wr_strobe = chipselect && ~write_n && (address == 0);
endmodule
|
// -*- Mode: Verilog -*-
// Filename : spi_testbench.v
// Description : Testbench for testing SPI module
// Author : Philip Tracton
// Created On : Fri Jul 8 21:08:52 2016
// Last Modified By: Philip Tracton
// Last Modified On: Fri Jul 8 21:08:52 2016
// Update Count : 0
// Status : Unknown, Use with caution!
`include "timescale.v"
`include "simulation_includes.vh"
module spi_testbench (/*AUTOARG*/ ) ;
//
// Creates a clock, reset, a timeout in case the sim never stops,
// and pass/fail managers
//
`include "test_management.v"
wire sck;
wire miso;
wire mosi;
wire ncs;
wire wb_clk = clk;
wire wb_rst = reset;
fpga dut(
// Outputs
.sck_o(sck_o),
.ncs_o(ncs_o),
.mosi_o(mosi_o),
// Inputs
.clk_i(clk),
.rst_i(reset),
.miso_i(miso_i),
.int1(int1),
.int2(int2)
) ;
//
// Tasks used to interface with ADXL362
//
spi_tasks spi_tasks();
adxl362 adxl362(
.SCLK(sck_o),
.MOSI(mosi_o),
.nCS(ncs_o),
.MISO(miso_i),
.INT1(int1),
.INT2(int2)
);
//
// Tasks used to help test cases
//
test_tasks test_tasks();
//
// The actual test cases that are being tested
//
test_case test_case();
endmodule // spi_testbench
|
`include "config.inc"
module gamma(
input clock,
input [4:0] gamma_config,
input [7:0] in,
output reg [7:0] out
);
always @(posedge clock) begin
case (gamma_config)
`GAMMA_0_714290: begin
case (in)
`include "config/gamma_0_714290.v"
endcase
end
`GAMMA_0_769231: begin
case (in)
`include "config/gamma_0_769231.v"
endcase
end
`GAMMA_0_833330: begin
case (in)
`include "config/gamma_0_833330.v"
endcase
end
`GAMMA_0_909090: begin
case (in)
`include "config/gamma_0_909090.v"
endcase
end
`GAMMA_1_1: begin
case (in)
`include "config/gamma_1_1.v"
endcase
end
`GAMMA_1_2: begin
case (in)
`include "config/gamma_1_2.v"
endcase
end
`GAMMA_1_3: begin
case (in)
`include "config/gamma_1_3.v"
endcase
end
`GAMMA_1_4: begin
case (in)
`include "config/gamma_1_4.v"
endcase
end
default: out <= in;
endcase
end
endmodule |
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; int main() { ios::sync_with_stdio(false); int t; cin >> t; while (t--) { string s, t; cin >> s >> t; vector<int> each[26]; int n, m; n = s.length(); m = t.length(); for (int i = 0; i < n; ++i) { each[s[i] - a ].push_back(i); } int las = INF, res = 0; for (int i = 0; i < m; ++i) { if (upper_bound(each[t[i] - a ].begin(), each[t[i] - a ].end(), las) != each[t[i] - a ].end()) { las = *upper_bound(each[t[i] - a ].begin(), each[t[i] - a ].end(), las); } else { if (each[t[i] - a ].empty()) { res = -1; break; } else { res++; las = each[t[i] - a ][0]; } } } cout << res << endl; } return 0; } |
/*###########################################################################
# Function: Single port memory wrapper
# To run without hardware platform dependancy use:
# `define TARGET_CLEAN"
############################################################################
*/
module memory_sp(/*AUTOARG*/
// Outputs
dout,
// Inputs
clk, en, wen, addr, din
);
parameter AW = 14;
parameter DW = 32;
parameter WED = DW/8; //one write enable per byte
parameter MD = 1<<AW;//memory depth
//write-port
input clk; //clock
input en; //memory access
input [WED-1:0] wen; //write enable vector
input [AW-1:0] addr;//address
input [DW-1:0] din; //data input
output [DW-1:0] dout;//data output
`ifdef TARGET_CLEAN
reg [DW-1:0] ram [MD-1:0];
reg [DW-1:0] rd_data;
reg [DW-1:0] dout;
//read port
always @ (posedge clk)
if(en)
dout[DW-1:0] <= ram[addr[AW-1:0]];
//write port
generate
genvar i;
for (i = 0; i < WED; i = i+1) begin: gen_ram
always @(posedge clk)
begin
if (wen[i] & en)
ram[addr[AW-1:0]][(i+1)*8-1:i*8] <= din[(i+1)*8-1:i*8];
end
end
endgenerate
`elsif TARGET_XILINX
//instantiate XILINX BRAM (based on parameter size)
`elsif TARGET_ALTERA
//instantiate ALTERA BRAM (based on paremeter size)
`endif
endmodule // memory_dp
/*
Copyright (C) 2014 Adapteva, Inc.
Contributed by Andreas Olofsson <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
|
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2014, University of British Columbia (UBC); All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// lvt_bin.v: Binary-coded LVT (Live-Value-Table) //
// //
// Author: Ameer M.S. Abdelhadi (, ) //
// Switched SRAM-based Multi-ported RAM; University of British Columbia, 2014 //
////////////////////////////////////////////////////////////////////////////////////
`include "utils.vh"
module lvt_bin
#( parameter MEMD = 16, // memory depth
parameter nRP = 2 , // number of reading ports
parameter nWP = 2 , // number of writing ports
parameter WAWB = 1 , // allow Write-After-Write (need to bypass feedback ram)
parameter RAWB = 1 , // new data for Read-after-Write (need to bypass output ram)
parameter RDWB = 0 , // new data for Read-During-Write
parameter ZERO = 0 , // binary / Initial RAM with zeros (has priority over FILE)
parameter FILE = "" // initialization file, optional
)( input clk , // clock
input [ nWP-1:0] WEnb , // write enable for each writing port
input [`log2(MEMD)*nWP-1:0] WAddr, // write addresses - packed from nWP write ports
input [`log2(MEMD)*nRP-1:0] RAddr, // read addresses - packed from nRP read ports
output reg [`log2(nWP )*nRP-1:0] RBank); // read data - packed from nRP read ports
localparam ADRW = `log2(MEMD); // address width
localparam LVTW = `log2(nWP ); // required memory width
// Generate Bank ID's to write into LVT
wire [LVTW-1:0] WData2D [nWP-1:0];
genvar gi;
generate
for (gi=0;gi<nWP;gi=gi+1) begin: GenerateID
assign WData2D[gi]=gi;
end
endgenerate
// Register write addresses, data and enables
reg [ADRW*nWP-1:0] WAddr_r; // registered write addresses - packed from nWP write ports
reg [ nWP-1:0] WEnb_r ; // registered write enable for each writing port
always @(posedge clk) begin
WAddr_r <= WAddr;
WEnb_r <= WEnb ;
end
// unpacked/pack addresses/data
reg [ADRW -1:0] WAddr2D [nWP-1:0] ; // write addresses / 2D
reg [ADRW -1:0] WAddr2D_r [nWP-1:0] ; // registered write addresses / 2D
wire [LVTW* nRP -1:0] RDataOut2D [nWP-1:0] ; // read data out / 2D
reg [LVTW -1:0] RDataOut3D [nWP-1:0][nRP-1:0]; // read data out / 3D
reg [ADRW*(nWP-1)-1:0] RAddrFB2D [nWP-1:0] ; // read address fb / 2D
reg [ADRW -1:0] RAddrFB3D [nWP-1:0][nWP-2:0]; // read address fb / 3D
wire [LVTW*(nWP-1)-1:0] RDataFB2D [nWP-1:0] ; // read data fb / 2D
reg [LVTW -1:0] RDataFB3D [nWP-1:0][nWP-2:0]; // read data fb / 3D
reg [LVTW -1:0] WDataFB2D [nWP-1:0] ; // write data / 2D
reg [LVTW -1:0] RBank2D [nRP-1:0] ; // read data / 2D
`ARRINIT;
always @* begin
// packing/unpacking arrays into 1D/2D/3D structures; see utils.vh for definitions
`ARR1D2D(nWP, ADRW,WAddr ,WAddr2D );
`ARR1D2D(nWP, ADRW,WAddr_r ,WAddr2D_r );
`ARR2D1D(nRP, LVTW,RBank2D ,RBank );
`ARR2D3D(nWP,nRP ,LVTW,RDataOut2D,RDataOut3D);
`ARR3D2D(nWP,nWP-1,ADRW,RAddrFB3D ,RAddrFB2D );
`ARR2D3D(nWP,nWP-1,LVTW,RDataFB2D ,RDataFB3D );
end
// generate and instantiate mulriread BRAMs
genvar wpi;
generate
for (wpi=0 ; wpi<nWP ; wpi=wpi+1) begin: RPORTwpi
// feedback multiread ram instantiation
mrram #( .MEMD (MEMD ), // memory depth
.DATW (LVTW ), // data width
.nRP (nWP-1 ), // number of reading ports
.BYPS (WAWB||RDWB||RAWB), // bypass? 0:none; 1:single-stage; 2:two-stages
.ZERO (ZERO ), // binary / Initial RAM with zeros (has priority over FILE)
.FILE (FILE )) // initialization file, optional
mrram_fbk ( .clk (clk ), // clock - in
.WEnb (WEnb_r[wpi] ), // write enable (1 port) - in
.WAddr (WAddr2D_r[wpi] ), // write address (1 port) - in : [`log2(MEMD) -1:0]
.WData (WDataFB2D[wpi] ), // write data (1 port) - in : [LVTW -1:0]
.RAddr (RAddrFB2D[wpi] ), // read addresses - packed from nRP read ports - in : [`log2(MEMD)*nRP-1:0]
.RData (RDataFB2D[wpi] )); // read data - packed from nRP read ports - out: [LVTW *nRP-1:0]
// output multiread ram instantiation
mrram #( .MEMD (MEMD ), // memory depth
.DATW (LVTW ), // data width
.nRP (nRP ), // number of reading ports
.BYPS (RDWB ? 2 : RAWB), // bypass? 0:none; 1:single-stage; 2:two-stages
.ZERO (ZERO ), // binary / Initial RAM with zeros (has priority over FILE)
.FILE (FILE )) // initialization file, optional
mrram_out ( .clk (clk ), // clock - in
.WEnb (WEnb_r[wpi] ), // write enable (1 port) - in
.WAddr (WAddr2D_r[wpi] ), // write address (1 port) - in : [`log2(MEMD) -1:0]
.WData (WDataFB2D[wpi] ), // write data (1 port) - in : [LVTW -1:0]
.RAddr (RAddr ), // read addresses - packed from nRP read ports - in : [`log2(MEMD)*nRP-1:0]
.RData (RDataOut2D[wpi])); // read data - packed from nRP read ports - out: [LVTW *nRP-1:0]
end
endgenerate
// combinatorial logic for output and feedback functions
integer i,j,k;
always @* begin
// generate output read functions
for(i=0;i<nRP;i=i+1) begin
RBank2D[i] = RDataOut3D[0][i];
for(j=1;j<nWP;j=j+1) RBank2D[i] = RBank2D[i] ^ RDataOut3D[j][i];
end
// generate feedback functions
for(i=0;i<nWP;i=i+1) WDataFB2D[i] = WData2D[i];
for(i=0;i<nWP;i=i+1) begin
k = 0;
for(j=0;j<nWP-1;j=j+1) begin
k=k+(j==i);
RAddrFB3D[i][j] = WAddr2D[k];
WDataFB2D[k] = WDataFB2D[k] ^ RDataFB3D[i][j];
k=k+1;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int oo = 0x3f3f3f3f; const double eps = 1e-9; vector<int> p, vg; set<pair<int, int> > done; bool cando(int i, int j) { return done.find(make_pair(min(i, j), max(i, j))) == done.end(); } int moves = 0; void doswap(int i, int j) { ++moves; assert(i != j); assert(min(i, j) >= 0 && max(i, j) < int((vg).size())); assert(cando(i, j)); printf( %d %d n , min(i, j) + 1, max(i, j) + 1); swap(p[i], p[j]); swap(vg[i], vg[j]); done.insert(make_pair(min(i, j), max(i, j))); } void brute_force(vector<int> pp) { int N = int((pp).size()); vector<pair<int, int> > op; vector<int> aim = pp; sort((aim).begin(), (aim).end()); for (int i = (0); i < (N); i++) for (int j = (0); j < (i); j++) if (cando(i, j)) op.push_back(make_pair(i, j)); sort((op).begin(), (op).end()); do { vector<int> tmp = pp; for (auto it : op) { swap(tmp[it.first], tmp[it.second]); } if (tmp == aim) { for (auto it : op) doswap(it.first, it.second); return; } } while (next_permutation((op).begin(), (op).end())); cerr << EPIC FAIL n ; } int main() { ios::sync_with_stdio(false); int N; cin >> N; if (N == 1) { cout << YES n ; return 0; } if ((N * (N - 1)) % 4 != 0) { cout << NO n ; return 0; } printf( YES n ); p = vector<int>(N); for (int i = (0); i < (N); i++) p[i] = i; vg = p; while (true) { vector<int> ids; for (int i = (0); i < (N); i++) if (p[i] != -1) ids.push_back(i); int S = int((ids).size()); if (S <= 1) break; assert(ids[S - 1] == S - 1); if (S <= 5) { vector<int> tmp(S); for (int i = (0); i < (S); i++) tmp[i] = p[i]; brute_force(tmp); break; } vector<int> x(S - 1); for (int i = (0); i < (S - 1); i++) x[i] = i; random_shuffle((x).begin(), (x).end()); if (p[S - 1] == S - 1) { bool ok = false; while (!ok) { int z1 = max((rand() % (S - 1)), rand() % (S - 1)); int z2 = max((rand() % (S - 1)), rand() % (S - 1)); if (z1 == z2) continue; if (!cando(z1, S - 1) || !cando(z2, S - 1)) continue; if (!cando(z1, z2)) continue; ok = true; doswap(z2, S - 1); doswap(z2, z1); for (auto i : x) { if (i != z1 && i != z2 && cando(i, S - 1)) { doswap(i, S - 1); } } doswap(z1, S - 1); } } else { int id_largest = -1; for (int i = (0); i < (S); i++) if (p[i] == S - 1) id_largest = i; assert(id_largest != -1); if (cando(id_largest, S - 1)) { for (auto i : x) { if (i != id_largest && cando(i, S - 1)) { doswap(i, S - 1); } } doswap(id_largest, S - 1); } else { int z = S - 2; while (!cando(z, S - 1) || !cando(id_largest, z)) --z; assert(z >= 0); assert(z != id_largest); doswap(id_largest, z); for (auto i : x) { if (i != z && cando(i, S - 1)) { doswap(i, S - 1); } } doswap(z, S - 1); } } assert(p[S - 1] == S - 1); p[S - 1] = -1; } assert(moves == (N * (N - 1)) / 2); for (int i = (0); i < (N); i++) assert(vg[i] == i); return 0; } |
#include <bits/stdc++.h> using namespace std; vector<long long> a; vector<long long> dp(2001); int main() { ios_base::sync_with_stdio(false); cin.tie(NULL), cout.tie(NULL); int t = 1; long long n, k, x, temp; 2000000001LL; while (t--) { cin >> n >> k; for (int i = 0; i < n; i++) { cin >> x, a.push_back(x); } long long left = 0, right = 2000000000LL; long long required = 2000000001LL; while (left < right) { x = (left + right) / 2LL; required = 2000000001LL; for (int i = 0; i < n; i++) { dp[i] = i; for (int j = 0; j < i; j++) { temp = (abs(a[i] - a[j]) + i - j - 1) / (i - j); if (temp <= x) dp[i] = min(dp[i], dp[j] + i - j - 1); } required = min(required, dp[i] + n - i - 1); } if (required > k) left = x + 1; else right = x; } cout << left << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long nx2(long long n) { long long p = 1; if (n && !(n & (n - 1))) return n; while (p < n) p <<= 1; return p; } namespace Debug { void dout() { cerr << n ; } template <typename Head, typename... Tail> void dout(Head H, Tail... T) { cerr << << H; dout(T...); } template <typename T> void douta(const T *a, int n) { cerr << n[ ; for (int i = 0; i < n; i++) { cerr << << a[i]; } cerr << ] n ; } template <typename T> void doutaa(T **b, int r, int c) { for (int i = 0; i < r; i++) { cerr << [ ; for (int j = 0; j < c; j++) { cerr << << b[i][j]; } cerr << ] n ; } } template <typename T> void dout(const vector<T> v) { cerr << n[ ; for (T i : v) { cerr << << i; } cerr << ] n ; } template <typename T> void dout(const vector<vector<T>> v) { cerr << n ; for (vector<T> u : v) { cerr << [ ; for (T i : u) { cerr << << i; } cerr << ] n ; } } template <typename F, typename S> void dout(const vector<pair<F, S>> u) { cerr << n ; for (pair<F, S> v : u) { cerr << [ << v.first << << v.second << ] n ; } } } // namespace Debug using namespace Debug; signed main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n, m, k; cin >> n >> m >> k; vector<vector<vector<long long>>> adj(n); vector<long long> si(k); for (long long i = 0; i < m + k; i++) { if (i < m) { long long u, v, x; cin >> u >> v >> x, --u, --v; adj[u].push_back({v, x, i}); adj[v].push_back({u, x, i}); } else { long long s, y; cin >> s >> y, --s; si[i - m] = s; adj[0].push_back({s, y, i}); adj[s].push_back({0, y, i}); } } vector<long long> vis(n), vis1(n), dist(n, INT_MAX); priority_queue<pair<long long, long long>, vector<pair<long long, long long>>, greater<pair<long long, long long>>> pq; dist[0] = 0; pq.push({dist[0], 0}); vis[0] = 0; while (!pq.empty()) { long long u = pq.top().second; pq.pop(); if (vis1[u]) { continue; } vis1[u] = 1; for (auto vwi : adj[u]) { long long v = vwi[0], w = vwi[1], i = vwi[2]; if (v == 0) { continue; } if (dist[v] > dist[u] + w) { vis[v] = i; dist[v] = dist[u] + w; pq.push({dist[v], v}); } else if (dist[v] == dist[u] + w && vis[v] >= m && i < m) { vis[v] = i; pq.push({dist[v], v}); } } } long long res = 0; for (long long i = 0; i < k; i++) { res += (vis[si[i]] != i + m); } cout << res << n ; } |
//Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2014.2 (win64) Build 928826 Thu Jun 5 18:21:07 MDT 2014
//Date : Mon Jan 26 13:25:28 2015
//Host : Dtysky running 64-bit major release (build 9200)
//Command : generate_target MIPS_CPU.bd
//Design : MIPS_CPU
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CORE_GENERATION_INFO = "MIPS_CPU,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLanguage=VERILOG,numBlks=8,numReposBlks=8,numNonXlnxBlks=7,numHierBlks=0,maxHierDepth=0}" *)
module MIPS_CPU
(inclk,
key,
led);
input inclk;
input [15:0]key;
output [15:0]led;
wire [31:0]ALU32_0_r;
wire ALU32_0_z;
wire [3:0]CONTROL_UNIT_0_aluc;
wire CONTROL_UNIT_0_aluimm;
wire CONTROL_UNIT_0_jal;
wire CONTROL_UNIT_0_m2reg;
wire [1:0]CONTROL_UNIT_0_pcsource;
wire CONTROL_UNIT_0_regrt;
wire CONTROL_UNIT_0_sext;
wire CONTROL_UNIT_0_shfit;
wire CONTROL_UNIT_0_wmem;
wire CONTROL_UNIT_0_wreg;
wire [31:0]DATAPATH_0_alu_a;
wire [31:0]DATAPATH_0_alu_aluc;
wire [31:0]DATAPATH_0_alu_b;
wire [5:0]DATAPATH_0_con_func;
wire [5:0]DATAPATH_0_con_op;
wire DATAPATH_0_con_z;
wire [31:0]DATAPATH_0_data_a;
wire [31:0]DATAPATH_0_data_di;
wire DATAPATH_0_data_we;
wire [31:0]DATAPATH_0_inst_a;
wire [31:0]DATAPATH_0_reg_d;
wire [4:0]DATAPATH_0_reg_rna;
wire [4:0]DATAPATH_0_reg_rnb;
wire DATAPATH_0_reg_we;
wire [4:0]DATAPATH_0_reg_wn;
wire [31:0]DATA_MEM_0_data_out;
wire GND_1;
wire KEY2INST_0_clrn;
wire [31:0]KEY2INST_0_inst_do;
wire [31:0]REGFILE_0_qa;
wire [31:0]REGFILE_0_qb;
wire [15:0]SHOW_ON_LED_0_led;
wire [15:0]button_1;
wire clk_wiz_0_clk_out1;
wire inclk_1;
assign button_1 = key[15:0];
assign inclk_1 = inclk;
assign led[15:0] = SHOW_ON_LED_0_led;
MIPS_CPU_ALU32_0_0 ALU32_0
(.a(DATAPATH_0_alu_a),
.aluc(DATAPATH_0_alu_aluc),
.b(DATAPATH_0_alu_b),
.r(ALU32_0_r),
.z(ALU32_0_z));
MIPS_CPU_CONTROL_UNIT_0_0 CONTROL_UNIT_0
(.aluc(CONTROL_UNIT_0_aluc),
.aluimm(CONTROL_UNIT_0_aluimm),
.func(DATAPATH_0_con_func),
.jal(CONTROL_UNIT_0_jal),
.m2reg(CONTROL_UNIT_0_m2reg),
.op(DATAPATH_0_con_op),
.pcsource(CONTROL_UNIT_0_pcsource),
.regrt(CONTROL_UNIT_0_regrt),
.sext(CONTROL_UNIT_0_sext),
.shfit(CONTROL_UNIT_0_shfit),
.wmem(CONTROL_UNIT_0_wmem),
.wreg(CONTROL_UNIT_0_wreg),
.z(DATAPATH_0_con_z));
MIPS_CPU_DATAPATH_0_0 DATAPATH_0
(.alu_a(DATAPATH_0_alu_a),
.alu_aluc(DATAPATH_0_alu_aluc),
.alu_b(DATAPATH_0_alu_b),
.alu_r(ALU32_0_r),
.alu_z(ALU32_0_z),
.clk(clk_wiz_0_clk_out1),
.clrn(KEY2INST_0_clrn),
.con_aluc(CONTROL_UNIT_0_aluc),
.con_aluimm(CONTROL_UNIT_0_aluimm),
.con_func(DATAPATH_0_con_func),
.con_jal(CONTROL_UNIT_0_jal),
.con_m2reg(CONTROL_UNIT_0_m2reg),
.con_op(DATAPATH_0_con_op),
.con_pcsource(CONTROL_UNIT_0_pcsource),
.con_regrt(CONTROL_UNIT_0_regrt),
.con_sext(CONTROL_UNIT_0_sext),
.con_shfit(CONTROL_UNIT_0_shfit),
.con_wmem(CONTROL_UNIT_0_wmem),
.con_wreg(CONTROL_UNIT_0_wreg),
.con_z(DATAPATH_0_con_z),
.data_a(DATAPATH_0_data_a),
.data_di(DATAPATH_0_data_di),
.data_do(DATA_MEM_0_data_out),
.data_we(DATAPATH_0_data_we),
.inst_a(DATAPATH_0_inst_a),
.inst_do(KEY2INST_0_inst_do),
.reg_d(DATAPATH_0_reg_d),
.reg_qa(REGFILE_0_qa),
.reg_qb(REGFILE_0_qb),
.reg_rna(DATAPATH_0_reg_rna),
.reg_rnb(DATAPATH_0_reg_rnb),
.reg_we(DATAPATH_0_reg_we),
.reg_wn(DATAPATH_0_reg_wn));
MIPS_CPU_DATA_MEM_0_0 DATA_MEM_0
(.addr(DATAPATH_0_data_a),
.clk(clk_wiz_0_clk_out1),
.data_in(DATAPATH_0_data_di),
.data_out(DATA_MEM_0_data_out),
.we(DATAPATH_0_data_we));
GND GND
(.G(GND_1));
MIPS_CPU_KEY2INST_0_0 KEY2INST_0
(.button(button_1),
.clk(clk_wiz_0_clk_out1),
.clrn(KEY2INST_0_clrn),
.inst_a(DATAPATH_0_inst_a),
.inst_do(KEY2INST_0_inst_do));
MIPS_CPU_REGFILE_0_0 REGFILE_0
(.clk(clk_wiz_0_clk_out1),
.clrn(KEY2INST_0_clrn),
.d(DATAPATH_0_reg_d),
.qa(REGFILE_0_qa),
.qb(REGFILE_0_qb),
.rna(DATAPATH_0_reg_rna),
.rnb(DATAPATH_0_reg_rnb),
.we(DATAPATH_0_reg_we),
.wn(DATAPATH_0_reg_wn));
MIPS_CPU_SHOW_ON_LED_0_0 SHOW_ON_LED_0
(.alu_r(ALU32_0_r),
.button(button_1),
.clk(clk_wiz_0_clk_out1),
.inst_op(DATAPATH_0_con_op),
.led(SHOW_ON_LED_0_led));
MIPS_CPU_clk_wiz_0_0 clk_wiz_0
(.clk_in1(inclk_1),
.clk_out1(clk_wiz_0_clk_out1),
.reset(GND_1));
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, s; cin >> n >> s; int a[n + 1], b[n + 1], i; a[0] = -1; b[0] = -1; for (i = 1; i <= n; i++) { cin >> a[i]; } for (i = 1; i <= n; i++) { cin >> b[i]; } if (a[1] == 0) { cout << NO ; return 0; } else { if (a[s] == 1) { cout << YES ; return 0; } else { if (b[s] == 0) { cout << NO ; return 0; } else { for (i = s; i <= n; i++) { if (a[i] == 1 && b[i] == 1) { cout << YES ; return 0; } } } } } cout << NO ; } |
#include <bits/stdc++.h> using namespace std; #pragma comment(linker, /STACK:16777216 ) const double EPS = 1e-7; double iabs(const double a) { return (a < -EPS) ? -a : a; } double imin(const double a, const double b) { return (a - b > EPS) ? b : a; } double imax(const double a, const double b) { return (a - b > EPS) ? a : b; } template <class I> I iabs(const I a) { return (a < 0) ? -a : a; } template <class I> I imin(const I a, const I b) { return (a < b) ? a : b; } template <class I> I imax(const I a, const I b) { return (a < b) ? b : a; } template <class I> inline I mod_pow(const I& x, const long long p, const I& m) { if (p == 0) return 1; I mult = (p & 1) ? x : 1; I t = mod_pow(x, p / 2, m) % m; return (((mult * t) % m) * t) % m; } template <class T> inline T ipow(const T& x, const long long p) { if (p == 0) return 1; T mult = (p & 1) ? x : 1; T h = ipow(x, p / 2); return h * h * mult; } unsigned long long gcd(unsigned long long a, unsigned long long b) { if (a == 0) return b; return gcd(b % a, a); } template <int SIZE> class DSU { public: int parent[SIZE]; int rank[SIZE]; int count; void clear() { for (int i = 0; i < SIZE; i++) { this->parent[i] = -1; this->rank[i] = 0; } this->count = 0; } DSU() { this->clear(); } void make(int x) { this->parent[x] = x; this->rank[x] = 1; this->count++; } bool in_a_set(int x) { return this->parent[x] != -1; } int find(int x) { if (x == this->parent[x]) return x; return this->parent[x] = find(this->parent[x]); } void combine(int x, int y) { x = this->find(x); y = this->find(y); if (x != y) { if (this->rank[x] > this->rank[y]) this->parent[x] = y; else this->parent[y] = x; } } }; class BigInt { public: const static unsigned int N = 1000; const static unsigned int base = 10; unsigned int len; short sign; unsigned int digits[N]; BigInt(const BigInt& bi) { this->len = bi.len; this->sign = bi.sign; for (unsigned int i = 0; i < this->len; ++i) (*this)[i] = bi[i]; } BigInt(long long n) { this->len = 0; this->sign = (n >= 0) ? 1 : -1; this->digits[0] = 0; while (n) { this->digits[this->len] = n % this->base; n /= this->base; this->len++; } if (this->len == 0) this->len = 1; } BigInt(string s) { this->sign = (s[0] == - ) ? 1 : -1; this->digits[0] = 0; if (s[0] == - ) s = s.substr(1, s.length() - 1); this->len = s.length(); for (unsigned int i = 0; i < this->len; i++) (*this)[i] = s[this->len - i - 1] - 0 ; } string toString() const { stringstream ss; for (int i = this->len - 1; i >= 0; --i) ss << (*this)[i]; return ss.str(); } unsigned int& operator[](const unsigned int i) { return digits[i]; } unsigned int operator[](const unsigned int i) const { if (i < this->len) return this->digits[i]; return 0; } bool iszero() const { if (this->len <= 1 && this->digits[0] == 0) return true; return false; } BigInt& operator=(const BigInt& rval) { if (this != &rval) { this->len = rval.len; this->sign = rval.sign; for (unsigned int i = 0; i < this->len; ++i) (*this)[i] = rval[i]; } return *this; } BigInt operator+(const BigInt& rhs) const { BigInt s(0); unsigned long long r = 0, d, i; for (i = 0; i < max(this->len, rhs.len); i++) { d = (*this)[i] + rhs[i] + r; r = d / this->base; s[i] = d % this->base; } s.len = max(this->len, rhs.len); if (r) s[s.len++] = r; return s; } BigInt operator+(unsigned long long rhs) const { BigInt s(*this); unsigned long long r = 0, d, i = 0; while (rhs != 0 || r != 0) { d = s[i] + (rhs % s.base) + r; rhs /= s.base; r = d / s.base; s[i] = d % s.base; i++; } if (i > s.len) s.len = i; return s; } BigInt operator*(unsigned long long rhs) const { if (rhs == 0) return BigInt(0); BigInt s(*this); unsigned long long r = 0, d, i; for (i = 0; i < s.len; ++i) { d = s[i] * rhs + r; r = d / this->base; s[i] = d % this->base; } while (r) s[s.len++] = r % this->base, r /= this->base; return s; } BigInt operator*(const BigInt& rhs) const { BigInt s(0); if (rhs.iszero()) return s; unsigned long long r, d, i, j, k; for (i = 0; i < this->N; i++) s[i] = 0; for (i = 0; i < this->len; i++) { r = 0; for (j = 0, k = i; j < rhs.len; j++, k++) { d = (*this)[i] * rhs[j] + r + s[k]; r = d / this->base; s[k] = d % this->base; } while (r) s[k++] = r % this->base, r /= this->base; if (k > s.len) s.len = k; } while (s.len > 1 && s[s.len - 1] == 0) s.len--; return s; } unsigned int operator%(unsigned int rhs) { BigInt t(*this); unsigned long long pow = 1; unsigned long long mod = 0; for (unsigned int i = 0; i < this->len && pow != 0; i++) { mod = (((*this)[i] % rhs) * pow + mod) % rhs; pow = (pow * this->base) % rhs; } return mod; } }; vector<long long> genprimes(const int n) { vector<long long> res; res.push_back(2); long long m, t, j; for (int i = 3; i <= n; i++) { j = 0; m = res.size(); t = (long long)sqrt(i * 1.0) + 1; while (j < m && res[j] < t && i % res[j] != 0) j++; if (j == m || res[j] >= t) res.push_back(i); } return res; } const unsigned long long N = 1000; const long long INF = 100000000; long long n, m, i, j, k, t, d; int main(int argc, char* argv[]) { cin >> n; if (n < 3) cout << -1 n ; else { for (i = n; i > 0; i--) cout << i << ; cout << endl; } return 0; } |
`include "bsg_mem_1rw_sync_macros.vh"
module bsg_mem_1rw_sync #( parameter `BSG_INV_PARAM(width_p )
, parameter `BSG_INV_PARAM(els_p )
, parameter addr_width_lp = `BSG_SAFE_CLOG2(els_p)
// whether to substitute a 1r1w
, parameter substitute_1r1w_p = 1
, parameter harden_p = 1
, parameter latch_last_read_p = 1
)
( input clk_i
, input reset_i
, input [width_p-1:0] data_i
, input [addr_width_lp-1:0] addr_i
, input v_i
, input w_i
, output logic [width_p-1:0] data_o
);
wire unused = reset_i;
// TODO: Define more hardened macro configs here
`bsg_mem_1rw_sync_macro(512,64,4) else
`bsg_mem_1rw_sync_macro(256,96,2) else
`bsg_mem_1rw_sync_macro(1024,46,4) else
`bsg_mem_1rw_sync_macro(16,32,2) else
`bsg_mem_1rw_sync_macro(64,49,4) else
// no hardened version found
begin : z
// we substitute a 1r1w macro
// fixme: theoretically there may be
// a more efficient way to generate a 1rw synthesized ram
if (substitute_1r1w_p)
begin: s1r1w
logic [width_p-1:0] data_lo;
bsg_mem_1r1w #( .width_p(width_p)
, .els_p(els_p)
, .read_write_same_addr_p(0)
)
mem
(.w_clk_i (clk_i)
,.w_reset_i(reset_i)
,.w_v_i (v_i & w_i)
,.w_addr_i (addr_i)
,.w_data_i (data_i)
,.r_addr_i (addr_i)
,.r_v_i (v_i & ~w_i)
,.r_data_o (data_lo)
);
// register output data to convert sync to async
always_ff @(posedge clk_i) begin
data_o <= data_lo;
end
end // block: s1r1w
else
begin: notmacro
bsg_mem_1rw_sync_synth # (.width_p(width_p), .els_p(els_p), .latch_last_read_p(latch_last_read_p))
synth
(.*);
end // block: notmacro
end // block: z
// synopsys translate_off
initial
begin
$display("## %L: instantiating width_p=%d, els_p=%d, substitute_1r1w_p=%d (%m)",width_p,els_p,substitute_1r1w_p);
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1rw_sync)
|
module tb_elink
reg [1:0] elink_txrr_packet;
wire elink_txo_lclk_p;
wire elink_chip_resetb;
reg elink_rxrr_wait;
wire elink_txrd_wait;
wire elink_rxwr_access;
wire elink_cclk_p;
reg elink_rxrd_wait;
wire elink_cclk_n;
wire elink_rxrr_access;
reg elink_txwr_clk;
wire [3:0] elink_rowid;
reg elink_txwr_access;
wire [3:0] elink_colid;
wire elink_txo_lclk_n;
reg elink_rxwr_clk;
wire [1:0] elink_rxrr_packet;
reg elink_rxi_frame_n;
reg [7:0] elink_rxi_data_n;
reg elink_clkin;
reg elink_txrr_access;
reg elink_hard_reset;
reg elink_txi_rd_wait_p;
reg elink_rxrd_clk;
wire elink_txo_frame_n;
reg [1:0] elink_txrd_packet;
reg elink_txi_rd_wait_n;
reg elink_txi_wr_wait_p;
reg elink_txrd_clk;
reg [7:0] elink_rxi_data_p;
reg elink_rxi_frame_p;
wire [7:0] elink_txo_data_n;
reg elink_txrd_access;
wire elink_rxo_rd_wait_p;
reg elink_rxrr_clk;
wire [1:0] elink_rxwr_packet;
wire elink_rxo_rd_wait_n;
wire elink_mailbox_not_empty;
reg elink_txi_wr_wait_n;
wire elink_mailbox_full;
wire elink_txwr_wait;
wire [7:0] elink_txo_data_p;
wire elink_txo_frame_p;
reg elink_rxwr_wait;
wire [1:0] elink_rxrd_packet;
reg elink_rxi_lclk_p;
wire elink_rxo_wr_wait_p;
wire elink_txrr_wait;
reg [2:0] elink_clkbypass;
wire elink_rxrd_access;
reg [1:0] elink_txwr_packet;
wire elink_rxo_wr_wait_n;
reg elink_txrr_clk;
reg elink_rxi_lclk_n;
initial begin
$from_myhdl(
elink_txrr_packet,
elink_rxrr_wait,
elink_rxrd_wait,
elink_txwr_clk,
elink_txwr_access,
elink_rxwr_clk,
elink_rxi_frame_n,
elink_rxi_data_n,
elink_clkin,
elink_txrr_access,
elink_hard_reset,
elink_txi_rd_wait_p,
elink_rxrd_clk,
elink_txrd_packet,
elink_txi_rd_wait_n,
elink_txi_wr_wait_p,
elink_txrd_clk,
elink_rxi_data_p,
elink_rxi_frame_p,
elink_txrd_access,
elink_rxrr_clk,
elink_txi_wr_wait_n,
elink_rxwr_wait,
elink_rxi_lclk_p,
elink_clkbypass,
elink_txwr_packet,
elink_txrr_clk,
elink_rxi_lclk_n
);
$to_myhdl(
elink_txo_lclk_p,
elink_chip_resetb,
elink_txrd_wait,
elink_rxwr_access,
elink_cclk_p,
elink_cclk_n,
elink_rxrr_access,
elink_rowid,
elink_colid,
elink_txo_lclk_n,
elink_rxrr_packet,
elink_txo_frame_n,
elink_txo_data_n,
elink_rxo_rd_wait_p,
elink_rxwr_packet,
elink_rxo_rd_wait_n,
elink_mailbox_not_empty,
elink_mailbox_full,
elink_txwr_wait,
elink_txo_data_p,
elink_txo_frame_p,
elink_rxrd_packet,
elink_rxo_wr_wait_p,
elink_txrr_wait,
elink_rxrd_access,
elink_rxo_wr_wait_n
);
end
elink
dut(
elink_clkin,
elink_hard_reset,
elink_clkbypass,
elink_chip_resetb,
elink_rowid,
elink_colid,
elink_mailbox_full,
elink_mailbox_not_empty,
elink_cclk_p,
elink_cclk_n,
elink_rxrr_wait,
elink_txrd_wait,
elink_txrr_packet,
elink_rxwr_access,
elink_rxrd_wait,
elink_rxrr_access,
elink_txwr_clk,
elink_txwr_access,
elink_txrd_access,
elink_rxwr_clk,
elink_txrd_clk,
elink_rxrr_packet,
elink_txrr_access,
elink_rxrd_clk,
elink_txrd_packet,
elink_rxrr_clk,
elink_rxwr_packet,
elink_txwr_wait,
elink_rxwr_wait,
elink_rxrd_packet,
elink_txrr_wait,
elink_rxrd_access,
elink_txwr_packet,
elink_txrr_clk,
elink_txo_lclk_p,
elink_txo_lclk_n,
elink_txo_data_n,
elink_txo_frame_n,
elink_txi_wr_wait_p,
elink_txi_wr_wait_n,
elink_txi_rd_wait_p,
elink_txi_rd_wait_n,
elink_rxo_rd_wait_p,
elink_rxo_rd_wait_n,
elink_txo_data_p,
elink_txo_frame_p,
elink_rxo_wr_wait_p,
elink_rxo_wr_wait_n,
elink_rxi_frame_n,
elink_rxi_data_n,
elink_rxi_data_p,
elink_rxi_lclk_p,
elink_rxi_frame_p,
elink_rxi_lclk_n
);
endmodule
|
#include <bits/stdc++.h> using namespace std; mt19937 rnd(time(0)); const long long inf = 0x3f3f3f3f3f3f3f3fLL; const long long N = 1e5 + 10; const long long MOD = 1e9 + 7; long long n, m, s; vector<vector<long long>> g(N); bool vis[N][2]; long long par[N][2], mark[N]; void dfs(long long u, long long f) { vis[u][f] = 1; for (auto i : g[u]) { if (!vis[i][f ^ 1]) { par[i][f ^ 1] = u; dfs(i, f ^ 1); } } } bool cyc(long long u) { mark[u] = 1; for (auto i : g[u]) { if (mark[i] == 1) return true; if (mark[i] == 0 && cyc(i)) return true; } mark[u] = 2; return false; } int32_t main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n >> m; long long sz, x; for (long long i = 1; i <= n; i++) { cin >> sz; for (long long j = 0; j < sz; j++) { cin >> x; g[i].push_back(x); } } cin >> s; dfs(s, 0); for (long long i = 1; i <= n; i++) { if ((long long)g[i].size() == 0 && vis[i][1]) { vector<long long> res; long long node = i, f = 1; res.push_back(node); while (node != s || f != 0) { node = par[node][f]; f ^= 1; res.push_back(node); } reverse(res.begin(), res.end()); cout << Win << n ; for (auto i : res) cout << i << ; cout << n ; return 0; } } if (cyc(s)) cout << Draw << n ; else cout << Lose << n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__XNOR2_1_V
`define SKY130_FD_SC_HD__XNOR2_1_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog wrapper for xnor2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__xnor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__xnor2_1 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__xnor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__xnor2_1 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__xnor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__XNOR2_1_V
|
/*
* SBN machine with hardwired FSM control
* (c) Volker Strumpen
*
* modified to halt execution
* if result address is C all fff's
* i.e. ff for fwidth=8
* by Martin Polak
*/
module sbn (clk, state, PC, a, b);
parameter fwidth = 8; // field width of sbn operand
parameter dwidth = 32;
input clk;
output [2:0] state;
output [fwidth-1:0] PC;
output [dwidth-1:0] a, b;
parameter iwidth = 4 * fwidth;
reg [iwidth-1:0] imem[0:((1<<fwidth)-1)];
reg [dwidth-1:0] dmem[0:((1<<fwidth)-1)];
reg [dwidth-1:0] X, Y;
reg [fwidth-1:0] PC;
reg [iwidth-1:0] IR;
wire [iwidth-1:0] insn;
wire [dwidth-1:0] data, asubb;
wire [fwidth-1:0] addr, PCp1, A, B, C, D;
wire altb, stp;
reg [1:0] da;
reg [2:0] state, nextstate;
parameter S0 = 3'b000;
parameter S1 = 3'b001;
parameter S2 = 3'b010;
parameter S3 = 3'b011;
parameter S4 = 3'b100;
parameter S5 = 3'b101;
parameter S6 = 3'b111;
// datapath
assign insn = imem[PC];
assign data = dmem[addr];
assign a = X; // for monitoring
assign b = Y; // for monitoring
assign asubb = X - Y;
assign altb = asubb[dwidth-1];
assign PCp1 = PC + 1;
assign A = IR[(4*fwidth-1):(3*fwidth)];
assign B = IR[(3*fwidth-1):(2*fwidth)];
assign C = IR[(2*fwidth-1):fwidth];
assign D = IR[fwidth-1:0];
assign stp = (C == ~{fwidth{1'b0}}) ? 1 : 0;
assign addr = (da == 2'b00) ? A : ((da == 2'b01) ? B : C);
always @ (posedge clk)
case (state) // action at end of state cycle
S0: begin
IR <= insn;
da <= 2'b00;
end
S1: begin
X <= data;
da <= 2'b01;
end
S2: begin
Y <= data;
da <= 2'b10;
end
S3: begin
dmem[addr] <= asubb;
$display("mw:DMEM,%h,%h", addr, asubb);
end
S4: PC <= D;
S5: PC <= PCp1;
S6: begin
// $display("program caused halt with value %d\n",asubb);
$finish;
end
endcase
// state register
always @ (posedge clk)
state <= nextstate;
// next state logic
always @ (state or altb or stp)
case (state)
S0: nextstate = S1;
S1: nextstate = S2;
S2: if (stp ) nextstate = S6;
else nextstate = S3;
S3: if (altb) nextstate = S4;
else nextstate = S5;
default: nextstate = S0;
endcase
initial begin
$readmemh(%PROG%, imem);
$readmemh(%DATA%, dmem);
PC = 0;
state = 0;
$monitor("%d:%b:%h,%h,%h,%h,%h,%h,%h,%h,%h,%h,%h",
$time, clk, PC, X, Y, A, B, C, D, insn, addr, asubb, PCp1);
end // initial begin
endmodule
module top;
parameter fwidth = 8; // field width of sbn operand
parameter dwidth = 32;
parameter maximum = 200;
parameter maxmone = maximum - 1;
parameter step = 10;
reg clk;
wire [2:0] state;
wire [fwidth-1:0] pc;
wire [dwidth-1:0] a, b;
sbn #(fwidth,dwidth) mach1 (clk, state, pc, a, b);
initial begin
$display("=== start ===");
clk = 0;
#maxmone $display("=== end ===");
#1 $finish;
end
always
#step clk = ~clk;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxN = 23; const int mod = 1000 * 1000 * 1000 + 7; int dp[2][1 << maxN]; int a[maxN]; int res[maxN][maxN]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n; cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; dp[0][1] = 1; dp[0][0] = mod; memset(res, -1, sizeof res); for (int i = 0; i < n; i++) for (int j = 0; j < i; j++) for (int k = 0; k < i; k++) if (a[j] + a[k] == a[i]) res[i][j] = k; for (int i = 1; i < n; i++) { int u = i & 1; for (int mask = 0; mask < (1 << (i + 1)); mask++) dp[u][mask] = mod; for (int mask = 0; mask < (1 << i); mask++) { for (int j = 0; j < i; j++) { if (res[i][j] == -1) continue; if (mask >> j & 1) if (mask >> res[i][j] & 1) { int tmp = mask ^ (1 << i); dp[u][tmp] = min(dp[u][tmp], max(__builtin_popcount(tmp), dp[!u][mask])); for (int k = 0; k < i; k++) { if (mask >> k & 1) { dp[u][tmp ^ (1 << k)] = min(dp[u][tmp ^ (1 << k)], dp[!u][mask]); } } break; } } } } int ans = mod; for (int mask = 0; mask < (1 << n); mask++) ans = min(ans, dp[(n - 1) & 1][mask]); if (ans == mod) cout << -1 << endl; else cout << ans << endl; return 0; } |
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Control_DQ_Currents.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Control_DQ_Currents
// Source Path: velocityControlHdl/Control_DQ_Currents
// Hierarchy Level: 4
//
// Simulink subsystem description for velocityControlHdl/Control_DQ_Currents:
//
// Linear Current Controllers
//
// PID Blocks used for Control Design of Current Loop controllers.
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Control_DQ_Currents
(
CLK_IN,
reset,
enb_1_2000_0,
Reset_1,
q_current_command,
d_current_measured,
q_current_measured,
param_current_p_gain,
param_current_i_gain,
d_voltage,
q_voltage
);
input CLK_IN;
input reset;
input enb_1_2000_0;
input Reset_1;
input signed [17:0] q_current_command; // sfix18_En15
input signed [17:0] d_current_measured; // sfix18_En15
input signed [17:0] q_current_measured; // sfix18_En15
input signed [17:0] param_current_p_gain; // sfix18_En10
input signed [17:0] param_current_i_gain; // sfix18_En2
output signed [17:0] d_voltage; // sfix18_En12
output signed [17:0] q_voltage; // sfix18_En12
wire signed [17:0] d_current_command_1; // sfix18_En15
wire signed [18:0] D_Error_sub_cast; // sfix19_En15
wire signed [18:0] D_Error_sub_cast_1; // sfix19_En15
wire signed [18:0] D_Error_sub_temp; // sfix19_En15
wire signed [17:0] d_current_error; // sfix18_En14
wire signed [17:0] direct_voltage; // sfix18_En12
wire signed [18:0] Q_Error_sub_cast; // sfix19_En15
wire signed [18:0] Q_Error_sub_cast_1; // sfix19_En15
wire signed [18:0] Q_Error_sub_temp; // sfix19_En15
wire signed [17:0] q_current_error; // sfix18_En14
wire signed [17:0] quadrature_voltage; // sfix18_En12
// The controller regulates direct and quadrature currents.
//
// Current Controllers
// <S1>/d_current_command
assign d_current_command_1 = 18'sb000000000000000000;
// <S1>/D_Error
assign D_Error_sub_cast = d_current_command_1;
assign D_Error_sub_cast_1 = d_current_measured;
assign D_Error_sub_temp = D_Error_sub_cast - D_Error_sub_cast_1;
assign d_current_error = D_Error_sub_temp[18:1];
// <S1>/Control_Current
velocityControlHdl_Control_Current u_Control_Current (.CLK_IN(CLK_IN),
.reset(reset),
.enb_1_2000_0(enb_1_2000_0),
.Reest(Reset_1),
.Err(d_current_error), // sfix18_En14
.param_current_p_gain(param_current_p_gain), // sfix18_En10
.param_current_i_gain(param_current_i_gain), // sfix18_En2
.Out(direct_voltage) // sfix18_En12
);
assign d_voltage = direct_voltage;
// <S1>/Q_Error
assign Q_Error_sub_cast = q_current_command;
assign Q_Error_sub_cast_1 = q_current_measured;
assign Q_Error_sub_temp = Q_Error_sub_cast - Q_Error_sub_cast_1;
assign q_current_error = Q_Error_sub_temp[18:1];
// <S1>/Control_Current1
velocityControlHdl_Control_Current1 u_Control_Current1 (.CLK_IN(CLK_IN),
.reset(reset),
.enb_1_2000_0(enb_1_2000_0),
.Reest(Reset_1),
.Err(q_current_error), // sfix18_En14
.param_current_p_gain(param_current_p_gain), // sfix18_En10
.param_current_i_gain(param_current_i_gain), // sfix18_En2
.Out(quadrature_voltage) // sfix18_En12
);
assign q_voltage = quadrature_voltage;
endmodule // velocityControlHdl_Control_DQ_Currents
|
// megafunction wizard: %ALTDDIO_IN%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altddio_in
// ============================================================
// File Name: rgmii_in1.v
// Megafunction Name(s):
// altddio_in
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.0 Build 176 04/19/2006 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_tse_rgmii_in1 (
aclr,
datain,
inclock,
dataout_h,
dataout_l);
input aclr;
input datain;
input inclock;
output dataout_h;
output dataout_l;
wire [0:0] sub_wire0;
wire [0:0] sub_wire2;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire dataout_h = sub_wire1;
wire [0:0] sub_wire3 = sub_wire2[0:0];
wire dataout_l = sub_wire3;
wire sub_wire4 = datain;
wire sub_wire5 = sub_wire4;
altddio_in altddio_in_component (
.datain (sub_wire5),
.inclock (inclock),
.aclr (aclr),
.dataout_h (sub_wire0),
.dataout_l (sub_wire2),
.aset (1'b0),
.inclocken (1'b1));
defparam
altddio_in_component.intended_device_family = "Stratix II",
altddio_in_component.invert_input_clocks = "OFF",
altddio_in_component.lpm_type = "altddio_in",
altddio_in_component.width = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ARESET_MODE NUMERIC "0"
// Retrieval info: PRIVATE: CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: INVERT_INPUT_CLOCKS NUMERIC "0"
// Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: CONSTANT: INVERT_INPUT_CLOCKS STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_in"
// Retrieval info: CONSTANT: WIDTH NUMERIC "1"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: USED_PORT: datain 0 0 0 0 INPUT NODEFVAL datain
// Retrieval info: USED_PORT: dataout_h 0 0 0 0 OUTPUT NODEFVAL dataout_h
// Retrieval info: USED_PORT: dataout_l 0 0 0 0 OUTPUT NODEFVAL dataout_l
// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL inclock
// Retrieval info: CONNECT: @datain 0 0 1 0 datain 0 0 0 0
// Retrieval info: CONNECT: dataout_h 0 0 0 0 @dataout_h 0 0 1 0
// Retrieval info: CONNECT: dataout_l 0 0 0 0 @dataout_l 0 0 1 0
// Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1_bb.v TRUE
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_ic_local_mem_router_reorder #(
parameter integer DATA_W = 256, // > 0
parameter integer BURSTCOUNT_W = 1, // == 1
parameter integer ADDRESS_W = 32, // > 0
parameter integer BYTEENA_W = DATA_W / 8, // > 0
parameter integer NUM_BANKS = 8, // > 0
parameter integer BANK_MAX_PENDING_READS = 6, // > 0
parameter integer BANK_MAX_PENDING_WRITES = 1 // > 0
)
(
input logic clock,
input logic resetn,
// Bank select (one-hot)
input logic [NUM_BANKS-1:0] bank_select,
// Master
input logic m_arb_request,
input logic m_arb_read,
input logic m_arb_write,
input logic [DATA_W-1:0] m_arb_writedata,
input logic [BURSTCOUNT_W-1:0] m_arb_burstcount,
input logic [ADDRESS_W-1:0] m_arb_address,
input logic [BYTEENA_W-1:0] m_arb_byteenable,
output logic m_arb_stall,
output logic m_wrp_ack,
output logic m_rrp_datavalid,
output logic [DATA_W-1:0] m_rrp_data,
// To each bank
output logic b_arb_request [NUM_BANKS],
output logic b_arb_read [NUM_BANKS],
output logic b_arb_write [NUM_BANKS],
output logic [DATA_W-1:0] b_arb_writedata [NUM_BANKS],
output logic [BURSTCOUNT_W-1:0] b_arb_burstcount [NUM_BANKS],
output logic [ADDRESS_W-$clog2(NUM_BANKS)-1:0] b_arb_address [NUM_BANKS],
output logic [BYTEENA_W-1:0] b_arb_byteenable [NUM_BANKS],
input logic b_arb_stall [NUM_BANKS],
input logic b_wrp_ack [NUM_BANKS],
input logic b_rrp_datavalid [NUM_BANKS],
input logic [DATA_W-1:0] b_rrp_data [NUM_BANKS]
);
// +3 : bank data FIFO latency
// +1 : do not stall when pipeline is full
localparam READ_DATA_FIFO_DEPTH = BANK_MAX_PENDING_READS + 3 + 1;
// READ_BANK_SELECT_FIFO_DEPTH = max( NUM_BANKS, READ_DATA_FIFO_DEPTH );
localparam READ_BANK_SELECT_FIFO_DEPTH = NUM_BANKS > READ_DATA_FIFO_DEPTH ? NUM_BANKS : READ_DATA_FIFO_DEPTH;
// +1 : do not stall when pipeline is full
localparam WRITE_ACK_FIFO_DEPTH = BANK_MAX_PENDING_WRITES * NUM_BANKS + 1;
genvar i;
// Request.
generate
begin:req
integer req_b;
logic stall;
always_comb
begin
stall = 1'b0;
for( req_b = 0; req_b < NUM_BANKS; req_b = req_b + 1 )
begin:bank
b_arb_request[req_b] = m_arb_request & bank_select[req_b] & ~(rrp.stall | wrp.stall);
b_arb_read[req_b] = m_arb_read & bank_select[req_b] & ~(rrp.stall | wrp.stall);
b_arb_write[req_b] = m_arb_write & bank_select[req_b] & ~(rrp.stall | wrp.stall);
b_arb_writedata[req_b] = m_arb_writedata;
b_arb_burstcount[req_b] = m_arb_burstcount;
b_arb_address[req_b] = m_arb_address[ADDRESS_W-$clog2(NUM_BANKS)-1:0];
b_arb_byteenable[req_b] = m_arb_byteenable;
stall |= b_arb_stall[req_b] & bank_select[req_b];
end
end
end
endgenerate
// Read return path. Need to handle the two problems:
// 1) Data is returned in a different bank order than the order in which
// the banks were issued.
// 2) Multiple data words arrive in the same cycle (from different banks).
generate
begin:rrp
integer rrp_b;
logic stall;
logic [NUM_BANKS-1:0] bs_in, bs_out, bank_df_valid, bank_df_no_free;
logic bs_read, bs_write, bs_full, bs_empty, bs_valid;
logic [DATA_W-1:0] bank_df_out [NUM_BANKS];
// Bank select FIFO. Tracks which bank the next valid read data
// should come from. Data is assumed to be one-hot encoded.
acl_ll_fifo #(
.DEPTH(READ_BANK_SELECT_FIFO_DEPTH),
.WIDTH(NUM_BANKS)
)
bs_fifo (
.clk( clock ),
.reset( ~resetn ),
.data_in( bs_in ),
.write( bs_write ),
.data_out( bs_out ),
.read( bs_read ),
.empty( bs_empty ),
.full( bs_full )
);
// Per-bank logic.
for( i = 0; i < NUM_BANKS; i = i + 1 )
begin:bank
// Data FIFO.
logic [DATA_W-1:0] df_in, df_out;
logic df_read, df_write, df_full, df_empty;
scfifo #(
.lpm_width( DATA_W ),
.lpm_widthu( $clog2(READ_DATA_FIFO_DEPTH + 1) ),
.lpm_numwords( READ_DATA_FIFO_DEPTH ),
.add_ram_output_register( "ON" ),
.lpm_showahead( "ON" ),
.intended_device_family( "stratixiv" )
)
data_fifo (
.aclr( ~resetn ),
.clock( clock ),
.empty( df_empty ),
.full( df_full ),
.data( df_in ),
.q( df_out ),
.wrreq( df_write ),
.rdreq( df_read ),
.sclr(),
.usedw(),
.almost_full(),
.almost_empty()
);
// Number of free entries in the data FIFO minus one.
// This means that the data FIFO will be full if df_free == -1.
// This allows for a single-bit to indicate no more free entries.
//
// The range of values that need to be stored in this counter is
// [-1, READ_DATA_FIFO_DEPTH - 1]. Initial value is
// READ_DATA_FIFO_DEPTH - 1.
logic [$clog2(READ_DATA_FIFO_DEPTH):0] df_free;
logic incr_df_free, decr_df_free;
// Data FIFO assignments.
assign df_in = b_rrp_data[i];
assign df_write = b_rrp_datavalid[i];
assign df_read = bs_valid & bs_out[i] & bank_df_valid[i];
assign bank_df_valid[i] = ~df_empty;
assign bank_df_out[i] = df_out;
// Logic to track number of free entries in the data FIFO.
always @( posedge clock or negedge resetn )
if( !resetn )
df_free <= READ_DATA_FIFO_DEPTH - 1;
else
df_free <= df_free + incr_df_free - decr_df_free;
assign incr_df_free = df_read;
assign decr_df_free = m_arb_read & bs_in[i] & ~(req.stall | bs_full | bank_df_no_free[i]);
// If MSB is high, then df_free == -1 and that means all data FIFO
// entries are in use.
assign bank_df_no_free[i] = df_free[$bits(df_free) - 1];
end
// Bank select FIFO assignments.
assign bs_in = bank_select;
assign bs_write = m_arb_read & ~(req.stall | stall);
assign bs_read = bs_valid & |(bs_out & bank_df_valid);
assign bs_valid = ~bs_empty;
// Stall the current read request if the bank select FIFO is full or
// if the bank data FIFO has no free entries.
assign stall = m_arb_read & (bs_full | |(bs_in & bank_df_no_free));
// RRP output signals.
logic [DATA_W-1:0] rrp_data;
always_comb
begin
rrp_data = '0;
for( rrp_b = 0; rrp_b < NUM_BANKS; rrp_b = rrp_b + 1 )
rrp_data |= bs_out[rrp_b] ? bank_df_out[rrp_b] : '0;
end
always @( posedge clock or negedge resetn )
if( !resetn )
m_rrp_datavalid <= 1'b0;
else
m_rrp_datavalid <= bs_read;
always @( posedge clock )
m_rrp_data <= rrp_data;
end
endgenerate
// Write return path. Need to handle one problem:
// 1) Multiple write acks arrive in the same cycle (from different banks).
generate
begin:wrp
integer wrp_b;
logic stall;
// "FIFO" of acks to send out. This is just a counter that counts
// the number of wrp acks still left to send out, minus one (so a value
// of -1 indicates no wrp acks left to send out). This allows for
// a single bit to mean zero.
//
// The range of values stored by this counter is
// [-1, WRITE_ACK_FIFO_DEPTH - 1]. Initial value is -1.
logic [$clog2(WRITE_ACK_FIFO_DEPTH):0] ack_counter;
logic decr_ack_counter;
logic [$clog2(NUM_BANKS + 1)-1:0] ack_counter_incr;
logic has_acks;
// Counter to track the number of free entries in the ack "FIFO",
// minus one (so a value of -1 indicates no more free entries). This
// allows for a single bit to mean no more free entries.
//
// The range of values stored by this counter is
// [-1. WRITE_ACK_FIFO_DEPTH - 1]. Initial value is
// WRITE_ACK_FIFO_DEPTH - 1.
logic [$clog2(WRITE_ACK_FIFO_DEPTH):0] ack_free;
logic incr_ack_free, decr_ack_free;
logic ack_no_free;
// Logic for ack counter.
always @( posedge clock or negedge resetn )
if( !resetn )
ack_counter <= {$bits(ack_counter){1'b1}}; // -1
else
ack_counter <= ack_counter + ack_counter_incr - decr_ack_counter;
assign decr_ack_counter = has_acks;
assign has_acks = ~ack_counter[$bits(ack_counter) - 1];
always_comb
begin
// In any given cycle, each bank can assert its wrp ack signal
// and so the ack counter can increase by
ack_counter_incr = '0;
for( wrp_b = 0; wrp_b < NUM_BANKS; wrp_b = wrp_b + 1 )
ack_counter_incr += b_wrp_ack[wrp_b];
end
// Logic for free entries counter.
always @( posedge clock or negedge resetn )
if( !resetn )
ack_free <= WRITE_ACK_FIFO_DEPTH - 1;
else
ack_free <= ack_free + incr_ack_free - decr_ack_free;
assign incr_ack_free = decr_ack_counter;
assign decr_ack_free = m_arb_write & ~(req.stall | ack_no_free);
assign ack_no_free = ack_free[$bits(ack_free) - 1];
// Stall if the current request is a write and the write ack fifo has
// no more free entries.
assign stall = m_arb_write & ack_no_free;
// Wrp ack signal.
assign m_wrp_ack = has_acks;
end
endgenerate
// Stall signal.
assign m_arb_stall = req.stall | rrp.stall | wrp.stall;
endmodule
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-8; const double pi = acos(-1); const long long inf = 0x3f3f3f3f3f3f3f3f; const int INF = 0x3f3f3f3f; const int MAX = 2e5 + 10; const long long mod = 1e9 + 7; long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } char c[3] = { R , G , B }; int main() { int t; cin >> t; while (t--) { int dif[3] = {0}; int n, k; cin >> n >> k; string s; cin >> s; for (int i = (0); i < (3); ++i) { for (int j = (0); j < (k); ++j) { if (s[j] != c[(j + i) % 3]) dif[i]++; } } int ans = 0; ans = min(dif[0], min(dif[1], dif[2])); for (int i = 1; i + k - 1 < n; i++) { int a0 = dif[0], a1 = dif[1], a2 = dif[2]; dif[0] = a2 - (s[i - 1] == B ? 0 : 1) + (s[i + k - 1] == c[(k - 1) % 3] ? 0 : 1); dif[1] = a0 - (s[i - 1] == R ? 0 : 1) + ((s[i + k - 1] == c[k % 3]) ? 0 : 1); dif[2] = a1 - (s[i - 1] == G ? 0 : 1) + ((s[i + k - 1] == c[(k + 1) % 3]) ? 0 : 1); ans = min(ans, min(dif[0], min(dif[1], dif[2]))); } cout << ans << n ; } } |
#include <bits/stdc++.h> using namespace std; bool debug = true; long long n, m, a, b; int main(int argc, char* argv[]) { cin >> n >> m >> a >> b; long long r = n % m; cout << min(r * b, (m - r) * a); while (clock() <= 300) { } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXI = numeric_limits<int>::max() / 2; const int MINI = numeric_limits<int>::min() / 2; const long long MAXL = numeric_limits<long long>::max() / 2; const long long MINL = numeric_limits<long long>::min() / 2; int cnt[2][2]; long long pro(long long s, int &s1, int &s2) { while (s % 2 == 0) { ++s1; s /= 2; } while (s % 3 == 0) { ++s2; s /= 3; } return s; } int solve(int &s1, int &s2, int t, long long &a, long long &b) { int ans = 0; while (s1 > t) { --s1; ++s2; ++ans; if (a % 3 == 0) a = a * 2 / 3; else b = b * 2 / 3; } return ans; } int solve(int &s1, int &s2, long long &a, long long &b) { int ans = 0; while (s1 > s2) { --s1; ++ans; if (a % 2 == 0) a /= 2; else b /= 2; } return ans; } int main(int argc, char *argv[]) { long long a, b, c, d, s, t; cin >> a >> b >> c >> d; s = a * b; t = c * d; if (pro(s, cnt[0][0], cnt[0][1]) != pro(t, cnt[1][0], cnt[1][1])) cout << -1 << endl; else { int ans = cnt[0][1] > cnt[1][1] ? solve(cnt[0][1], cnt[0][0], cnt[1][1], a, b) : solve(cnt[1][1], cnt[1][0], cnt[0][1], c, d); ans += cnt[0][0] > cnt[1][0] ? solve(cnt[0][0], cnt[1][0], a, b) : solve(cnt[1][0], cnt[0][0], c, d); cout << ans << endl; cout << a << << b << endl; cout << c << << d << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR3_TB_V
`define SKY130_FD_SC_LS__NOR3_TB_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nor3.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_ls__nor3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR3_TB_V
|
#include <bits/stdc++.h> using namespace std; const long long maxn = 1e6 + 10; long long a[maxn], b[maxn], ans[maxn]; int32_t main() { long long n; cin >> n; for (long long i = 0; i < n; i++) { cin >> a[i]; b[i] = a[i]; } sort(b, b + n); if (b[0] == b[n - 1]) { if (b[0] == 0) { cout << YES << n ; for (long long i = 0; i < n; i++) cout << 1 ; } else cout << NO ; exit(0); } long long pos = -1, mx = b[n - 1]; for (long long i = 0; i < n; i++) { if (a[i] == mx && a[(i - 1 + n) % n] != mx) pos = i; } ans[pos] = a[pos]; bool bad = 1; for (long long i = (pos - 1 + n) % n; i != pos; i = (i - 1 + n) % n) { if (a[i] == 0 && bad) ans[i] = ans[(i + 1) % n] * 2LL, bad = 0; else ans[i] = ans[(i + 1) % n] + a[i]; } cout << YES << n ; for (long long i = 0; i < n; i++) cout << ans[i] << ; } |
#include <bits/stdc++.h> using namespace std; namespace io { const int SIZE = (1 << 21) + 1; char ibuf[SIZE], *iS, *iT, obuf[SIZE], *oS = obuf, *oT = oS + SIZE - 1, c, qu[55]; int f, qr; inline void flush() { fwrite(obuf, 1, oS - obuf, stdout); oS = obuf; } inline void putc(char x) { *oS++ = x; if (oS == oT) flush(); } template <class I> inline void read(I &x) { for (f = 1, c = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, SIZE, stdin), (iS == iT ? EOF : *iS++)) : *iS++); c < 0 || c > 9 ; c = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, SIZE, stdin), (iS == iT ? EOF : *iS++)) : *iS++)) if (c == - ) f = -1; for (x = 0; c <= 9 && c >= 0 ; c = (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, SIZE, stdin), (iS == iT ? EOF : *iS++)) : *iS++)) x = x * 10 + (c & 15); x *= f; } template <class I> inline void print(I &x) { if (!x) putc( 0 ); if (x < 0) putc( - ), x = -x; while (x) qu[++qr] = x % 10 + 0 , x /= 10; while (qr) putc(qu[qr--]); } struct Flusher_ { ~Flusher_() { flush(); } } io_flusher_; } // namespace io using io ::print; using io ::putc; using io ::read; struct node { int nxt; long long cnt; } s[100005]; int a[15][100005]; int main() { int i, j, k; int n, m; read(n), read(m); for (i = 1; i <= m; i++) for (j = 1; j <= n; j++) read(a[i][j]); for (i = 1; i < n; i++) { s[a[1][i]].nxt = a[1][i + 1]; s[a[1][i]].cnt = 1; } for (int i = (int)2; i <= (int)m; i++) for (int j = (int)1; j <= (int)n - 1; j++) if (s[a[i][j]].nxt == a[i][j + 1]) s[a[i][j]].cnt++; long long sum = 1, ans = 0; for (int i = (int)1; i <= (int)n - 1; i++) { if (s[a[1][i]].cnt != m) ans += sum * (sum + 1) / 2, sum = 1; else sum++; } if (sum > 0) ans += sum * (sum + 1) / 2; cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long N = 100005; bool dp[501][501]; long long a[501], b[501]; signed main() { std::ios::sync_with_stdio(false); cin.tie(NULL); long long n, k; cin >> n >> k; for (long long i = 1; i < n + 1; i++) { cin >> a[i] >> b[i]; } dp[0][0] = true; long long tot = 0; for (long long i = 1; i < n + 1; i++) { tot += (a[i] + b[i]); for (long long j = 0; j < min(k, a[i] + 1); j++) { long long x = (a[i] - j) % k; if (x + b[i] < k) continue; for (long long l = 0; l < k; l++) { if (!dp[i - 1][l]) continue; long long rem = (l + j) % k; dp[i][rem] = true; } } long long j = a[i] % k; for (long long l = 0; l < k; l++) { if (!dp[i - 1][l]) continue; long long rem = (l + j) % k; dp[i][rem] = true; } } for (long long i = 0; i < k; i++) { if (dp[n][i]) { long long ans = (tot - i) / k; cout << ans; return 0; } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 50005; const int MAXD = 55; const int MOD = 1e9 + 7; template <typename T> inline void read(T &AKNOI) { T x = 0, flag = 1; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) flag = -1; ch = getchar(); } while (isdigit(ch)) { x = x * 10 + ch - 0 ; ch = getchar(); } AKNOI = flag * x; } namespace ModCalculator { inline void Inc(int &x, int y) { x += y; if (x >= MOD) x -= MOD; } inline void Dec(int &x, int y) { x -= y; if (x < 0) x += MOD; } inline int Add(int x, int y) { Inc(x, y); return x; } inline int Sub(int x, int y) { Dec(x, y); return x; } inline int Mul(int x, int y) { return 1LL * x * y % MOD; } } // namespace ModCalculator using namespace ModCalculator; char s[MAXN], sx[MAXD], sy[MAXD]; int n, d, dg[MAXD]; int tot, ch[MAXN][10], fail[MAXN], ed[MAXN], q[MAXN]; int dp[MAXD][MAXN]; void Insert(int l, int r) { int p = 0; for (int i = l; i <= r; ++i) { int x = s[i] - 0 ; if (!ch[p][x]) ch[p][x] = ++tot; p = ch[p][x]; } ed[p] = 1; } void GetFail() { int head = 1, tail = 0; for (int i = 0; i < 10; ++i) { if (ch[0][i]) { q[++tail] = ch[0][i]; } } while (head <= tail) { int u = q[head++]; for (int i = 0; i < 10; ++i) { if (ch[u][i]) { fail[ch[u][i]] = ch[fail[u]][i]; q[++tail] = ch[u][i]; } else { ch[u][i] = ch[fail[u]][i]; } } } } int DP(int i, int j, bool full) { if (i > d) return 1; if (!full && dp[i][j] != -1) return dp[i][j]; int ret = 0, r = (full ? dg[i] : 9); for (int k = 0; k <= r; ++k) { if (ed[ch[j][k]]) continue; Inc(ret, DP(i + 1, ch[j][k], full && (k == r))); } if (!full) dp[i][j] = ret; return ret; } int Calc(char *ss) { int ret = 0; for (int i = 1; i <= d; ++i) { ret = Add(Mul(ret, 10), (dg[i] = ss[i] - 0 )); } return Sub(ret, DP(1, 0, 1)); } void init() { scanf( %s , s + 1); n = strlen(s + 1); scanf( %s , sx + 1); scanf( %s , sy + 1); d = strlen(sx + 1); int d2 = d / 2; for (int i = 1; i + d2 - 1 <= n; ++i) { Insert(i, i + d2 - 1); } GetFail(); } void solve() { int p = d; for (; sx[p] == 0 ; sx[p--] = 9 ) ; sx[p] -= 1; memset(dp, -1, sizeof(dp)); printf( %d n , Sub(Calc(sy), Calc(sx))); } int main() { init(); solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; vector<pair<long long int, pair<long long int, long long int> > > P; int level[1007]; double ans = 0; bool contains(pair<long long int, pair<long long int, long long int> > A, pair<long long int, pair<long long int, long long int> > B) { return (A.second.first - B.second.first) * (A.second.first - B.second.first) + (A.second.second - B.second.second) * (A.second.second - B.second.second) < (A.first) * (A.first); } int main() { long long int i, j, k, l, m, n, x, y, z, a, b, r; scanf( %lld , &n); for (i = 0; i < n; i++) { scanf( %lld , &x); scanf( %lld , &y); scanf( %lld , &r); P.push_back(make_pair(r, make_pair(x, y))); } sort(P.begin(), P.end()); for (i = n - 1; i >= 0; i--) { for (j = n - 1; j > i; j--) { if (contains(P[j], P[i])) { level[i] = max(level[i], level[j] + 1); } } if (level[i] == 0) level[i] = 1; } for (i = 0; i < n; i++) { if (level[i] <= 2) ans += (P[i].first * P[i].first); else { if (level[i] % 2 == 1) ans -= (P[i].first * P[i].first); else ans += (P[i].first * P[i].first); } } printf( %.10lf n , ans * 3.14159265358979); return 0; } |
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2012, Ameer M. Abdelhadi; . All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// pll.v: Altera's PLL instantiation //
// //
// Ameer M.S. Abdelhadi (; ), June 2012 //
////////////////////////////////////////////////////////////////////////////////////
// Ameer Abdelhadi, June 2012
module pll #(
parameter MUL0 = 27 , // integer: clock 0 divisor
parameter DIV0 = 5 , // integer: clock 0 multiplier
parameter PHS0 = "0" , // string : clock 0 phase shift / ps
parameter MUL1 = 27 , // integer: clock 1 divisor
parameter DIV1 = 5 , // integer: clock 1 multiplier
parameter PHS1 = "0" , // string : clock 1 phase shift / ps
parameter MUL2 = 27 , // integer: clock 2 divisor
parameter DIV2 = 5 , // integer: clock 2 multiplier
parameter PHS2 = "0" , // string : clock 2 phase shift / ps
parameter MUL3 = 27 , // integer: clock 3 divisor
parameter DIV3 = 5 , // integer: clock 3 multiplier
parameter PHS3 = "0" , // string : clock 3 phase shift / ps
parameter MUL4 = 27 , // integer: clock 4 divisor
parameter DIV4 = 5 , // integer: clock 4 multiplier
parameter PHS4 = "0" )( // string : clock 4 phase shift / ps
input rst , // asynchronous reset
input clki , // input clock
output [4:0] clko , // output clocks
// phase shift
input [2:0] phasecntsel, // Counter Select. 000:all 001:M 010:C0 011:C1 100:C2 101:C3 110:C4. registered in the rising edge of SCANCLK.
input phasestep , // Logic high enables dynamic phase shifting.
input phaseupdown, // Selects dynamic phase shift direction; 1:UP, 0:DOWN. Registered in the rising edge of SCANCLK.
input scanclk , // Free running clock used in combination with PHASESTEP to enable or disable dynamic phase shifting.
output phasedone ); // Indicates that the phase adjustment is complete and PLL is ready to act on a possible second adjustment pulse. De-asserts on the rising edge of SCANCLK.
altpll #(
.bandwidth_type ("AUTO" ),
.clk0_divide_by (DIV0 ),
.clk0_duty_cycle (50 ),
.clk0_multiply_by (MUL0 ),
.clk0_phase_shift (PHS0 ),
.clk1_divide_by (DIV1 ),
.clk1_duty_cycle (50 ),
.clk1_multiply_by (MUL1 ),
.clk1_phase_shift (PHS1 ),
.clk2_divide_by (DIV2 ),
.clk2_duty_cycle (50 ),
.clk2_multiply_by (MUL2 ),
.clk2_phase_shift (PHS2 ),
.clk3_divide_by (DIV3 ),
.clk3_duty_cycle (50 ),
.clk3_multiply_by (MUL3 ),
.clk3_phase_shift (PHS3 ),
.clk4_divide_by (DIV4 ),
.clk4_duty_cycle (50 ),
.clk4_multiply_by (MUL4 ),
.clk4_phase_shift (PHS4 ),
.compensate_clock ("CLK0" ),
.inclk0_input_frequency (20000 ),
.intended_device_family ("Cyclone IV E" ),
.lpm_hint ("CBX_MODULE_PREFIX=pll"),
.lpm_type ("altpll" ),
.operation_mode ("NORMAL" ),
.pll_type ("AUTO" ),
.port_activeclock ("PORT_UNUSED" ),
.port_areset ("PORT_USED" ),
.port_clkbad0 ("PORT_UNUSED" ),
.port_clkbad1 ("PORT_UNUSED" ),
.port_clkloss ("PORT_UNUSED" ),
.port_clkswitch ("PORT_UNUSED" ),
.port_configupdate ("PORT_UNUSED" ),
.port_fbin ("PORT_UNUSED" ),
.port_inclk0 ("PORT_USED" ),
.port_inclk1 ("PORT_UNUSED" ),
.port_locked ("PORT_UNUSED" ),
.port_pfdena ("PORT_UNUSED" ),
.port_phasecounterselect ("PORT_USED" ),
.port_phasedone ("PORT_USED" ),
.port_phasestep ("PORT_USED" ),
.port_phaseupdown ("PORT_USED" ),
.port_pllena ("PORT_UNUSED" ),
.port_scanaclr ("PORT_UNUSED" ),
.port_scanclk ("PORT_USED" ),
.port_scanclkena ("PORT_UNUSED" ),
.port_scandata ("PORT_UNUSED" ),
.port_scandataout ("PORT_UNUSED" ),
.port_scandone ("PORT_UNUSED" ),
.port_scanread ("PORT_UNUSED" ),
.port_scanwrite ("PORT_UNUSED" ),
.port_clk0 ("PORT_USED" ),
.port_clk1 ("PORT_USED" ),
.port_clk2 ("PORT_USED" ),
.port_clk3 ("PORT_USED" ),
.port_clk4 ("PORT_USED" ),
.port_clk5 ("PORT_UNUSED" ),
.port_clkena0 ("PORT_UNUSED" ),
.port_clkena1 ("PORT_UNUSED" ),
.port_clkena2 ("PORT_UNUSED" ),
.port_clkena3 ("PORT_UNUSED" ),
.port_clkena4 ("PORT_UNUSED" ),
.port_clkena5 ("PORT_UNUSED" ),
.port_extclk0 ("PORT_UNUSED" ),
.port_extclk1 ("PORT_UNUSED" ),
.port_extclk2 ("PORT_UNUSED" ),
.port_extclk3 ("PORT_UNUSED" ),
.vco_frequency_control ("MANUAL_PHASE" ),
.vco_phase_shift_step (200 ),
.width_clock (5 ),
.width_phasecounterselect(3 )
)
altpll_component (
.areset (rst ),
.inclk ({1'h0,clki}),
.clk (clko ),
.activeclock ( ),
.clkbad ( ),
.clkena ({6{1'b1}} ),
.clkloss ( ),
.clkswitch (1'b0 ),
.configupdate (1'b0 ),
.enable0 ( ),
.enable1 ( ),
.extclk ( ),
.extclkena ({4{1'b1}} ),
.fbin (1'b1 ),
.fbmimicbidir ( ),
.fbout ( ),
.fref ( ),
.icdrclk ( ),
.locked ( ),
.pfdena (1'b1 ),
.phasecounterselect(phasecntsel),
.phasedone (phasedone ),
.phasestep (phasestep ),
.phaseupdown (phaseupdown),
.pllena (1'b1 ),
.scanaclr (1'b0 ),
.scanclk (scanclk ),
.scanclkena (1'b1 ),
.scandata (1'b0 ),
.scandataout ( ),
.scandone ( ),
.scanread (1'b0 ),
.scanwrite (1'b0 ),
.sclkout0 ( ),
.sclkout1 ( ),
.vcooverrange ( ),
.vcounderrange ( )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int t; long long l[200002], c[200002]; long long minx, maxx, miny, maxy; string s; bool check(long long l[], int n) { int Min = 0, Max = 0; int last = 0, first = 0; for (int i = 1; i <= n; i++) { if (l[i] < Min) { first = i; Min = l[i]; } if (l[i] >= Max) { last = i; Max = l[i]; } } if (last < first) return 1; Min = 0, Max = 0; first = last = 0; for (int i = 1; i <= n; i++) { if (l[i] > Max) { first = i; Max = l[i]; } if (l[i] <= Min) { Min = l[i]; last = i; } } if (last < first) return 1; return 0; } int main() { cin >> t; while (t--) { cin >> s; minx = maxx = miny = maxy = 0; long long x = 0, y = 0; for (int i = 0; i < s.size(); i++) { if (s[i] == D ) c[i + 1] = c[i] + 1; if (s[i] == A ) c[i + 1] = c[i] - 1; if (s[i] == W ) l[i + 1] = l[i] + 1; if (s[i] == S ) l[i + 1] = l[i] - 1; if (s[i] == W || s[i] == S ) c[i + 1] = c[i]; if (s[i] == D || s[i] == A ) l[i + 1] = l[i]; minx = min(minx, l[i + 1]); miny = min(miny, c[i + 1]); maxx = max(maxx, l[i + 1]); maxy = max(maxy, c[i + 1]); } long long ans = (maxx - minx + 1) * (maxy - miny + 1); if (check(l, s.size()) && maxx - minx + 1 > 2) ans = min(ans, (maxx - minx) * (maxy - miny + 1)); if (check(c, s.size()) && maxy - miny + 1 > 2) ans = min(ans, (maxx - minx + 1) * (maxy - miny)); cout << ans << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long f(long long n) { if (n < 10) return n; long long last_digit = n % 10; long long ret = n / 10 + 9; long long tmp = n; while (tmp >= 10) tmp = tmp / 10; if (tmp > last_digit) ret--; return ret; } int main() { long long i, j, k, n, m, d, a, b; while (cin >> a >> b) { cout << f(b) - f(a - 1) << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; mt19937 rnd; const int N = 1e5 + 10; long long a[N], pref[N]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n, d, m; cin >> n >> d >> m; for (int i = 1; i <= n; i++) { cin >> a[i]; } sort(a + 1, a + n + 1); for (int i = 1; i <= n; i++) { pref[i] = pref[i - 1] + a[i]; } int cnt = 0; for (int i = 1; i <= n; i++) { if (a[i] <= m) { cnt++; } } long long ans = 0; for (int k = 0; k <= n - cnt; k++) { if (1ll * k * d + k + cnt < n) { continue; } if (1ll * (k - 1) * d + k > n) { continue; } int x = min(cnt, n - (k - 1) * d - k); ans = max(ans, pref[cnt] - pref[cnt - x] + pref[n] - pref[n - k]); } cout << ans << n ; return 0; } |
// $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2011 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / 3-State Diffential Signaling I/O Buffer
// /___/ /\ Filename : IOBUFDS_INTERMDISABLE.v
// \ \ / \
// \___\/\___\
//
// Revision:
// 04/20/11 - Initial version.
// 06/15/11 - CR 613347 -- made ouput logic_1 when IBUFDISABLE is active
// 08/31/11 - CR 623170 -- Tristate powergating support
// 09/20/11 - CR 624774, 625725 -- Removed attributes IBUF_DELAY_VALUE, IFD_DELAY_VALUE and CAPACITANCE
// 09/20/11 - CR 625564 -- Fixed Tristate powergating polarity
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 07/13/12 - 669215 - add parameter DQS_BIAS
// 08/29/12 - 675511 - add DQS_BIAS functionality
// 09/11/12 - 677753 - remove X glitch on O
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IOBUFDS_INTERMDISABLE (O, IO, IOB, I, IBUFDISABLE, INTERMDISABLE, T);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
parameter DIFF_TERM = "FALSE";
parameter DQS_BIAS = "FALSE";
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
parameter SIM_DEVICE = "7SERIES";
parameter SLEW = "SLOW";
parameter USE_IBUFDISABLE = "TRUE";
localparam MODULE_NAME = "IOBUFDS_INTERMDISABLE";
output O;
inout IO;
inout IOB;
input I;
input IBUFDISABLE;
input INTERMDISABLE;
input T;
wire i_in, io_in, iob_in, ibufdisable_in, intermdisable_in, t_in;
reg o_out, io_out, iob_out;
reg O_int;
wire out_val;
reg DQS_BIAS_BINARY = 1'b0;
reg USE_IBUFDISABLE_BINARY = 1'b0;
wire t_or_gts;
wire not_t_or_ibufdisable;
// wire disable_out;
tri0 GTS = glbl.GTS;
assign O = (USE_IBUFDISABLE_BINARY == 1'b0) ? o_out :
((not_t_or_ibufdisable === 1'b1) ? out_val : ((not_t_or_ibufdisable === 1'b0) ? o_out : 1'bx));
assign intermdisable_in = INTERMDISABLE;
assign i_in = I;
assign ibufdisable_in = IBUFDISABLE;
assign t_in = T;
assign io_in = IO;
assign iob_in = IOB;
assign t_or_gts = GTS || t_in;
assign IO = t_or_gts ? 1'bz : i_in;
assign IOB = t_or_gts ? 1'bz : ~i_in;
// assign disable_out = intermdisable_in && ibufdisable_in;
assign not_t_or_ibufdisable = ~t_in || ibufdisable_in;
initial begin
case (DQS_BIAS)
"TRUE" : DQS_BIAS_BINARY <= #1 1'b1;
"FALSE" : DQS_BIAS_BINARY <= #1 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute DQS_BIAS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DQS_BIAS);
$finish;
end
endcase
case (DIFF_TERM)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute DIFF_TERM on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DIFF_TERM);
$finish;
end
endcase // case(DIFF_TERM)
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, IBUF_LOW_PWR);
$finish;
end
endcase
if((IOSTANDARD == "LVDS_25") || (IOSTANDARD == "LVDSEXT_25")) begin
$display("DRC Warning : The IOSTANDARD attribute on IOBUFDS_DCIEN instance %m is set to %s. LVDS_25 is a fixed impedance structure optimized to 100ohm differential. If the intended usage is a bus architecture, please use BLVDS. This is only intended to be used in point to point transmissions that do not have turn around timing requirements", IOSTANDARD);
end
case (USE_IBUFDISABLE)
"TRUE" : USE_IBUFDISABLE_BINARY <= #1 1'b1;
"FALSE" : USE_IBUFDISABLE_BINARY <= #1 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute USE_IBUFDISABLE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, USE_IBUFDISABLE);
$finish;
end
endcase
if ((SIM_DEVICE != "7SERIES") &&
(SIM_DEVICE != "ULTRASCALE")) begin
$display("Attribute Syntax Error : The attribute SIM_DEVICE on %s instance %m is set to %s. Legal values for this attribute are 7SERIES or ULTRASCALE.",MODULE_NAME,SIM_DEVICE);
$finish;
end
end
generate
case (SIM_DEVICE)
"7SERIES" : begin
assign out_val = 1'b1;
end
"ULTRASCALE" : begin
assign out_val = 1'b0;
end
endcase
endgenerate
always @(io_in or iob_in or DQS_BIAS_BINARY) begin
if (io_in == 1'b1 && iob_in == 1'b0)
o_out <= 1'b1;
else if (io_in == 1'b0 && iob_in == 1'b1)
o_out <= 1'b0;
else if ((io_in === 1'bz || io_in == 1'b0) && (iob_in === 1'bz || iob_in == 1'b1))
if (DQS_BIAS_BINARY == 1'b1)
o_out <= 1'b0;
else
o_out <= 1'bx;
else if (io_in === 1'bx || iob_in === 1'bx)
o_out <= 1'bx;
end
`ifdef XIL_TIMING
specify
(I => IO) = (0:0:0, 0:0:0);
(I => IOB) = (0:0:0, 0:0:0);
(IO => O) = (0:0:0, 0:0:0);
(IO => IOB) = (0:0:0, 0:0:0);
(IOB => O) = (0:0:0, 0:0:0);
(IOB => IO) = (0:0:0, 0:0:0);
(IBUFDISABLE => O) = (0:0:0, 0:0:0);
(IBUFDISABLE => IO) = (0:0:0, 0:0:0);
(IBUFDISABLE => IOB) = (0:0:0, 0:0:0);
(INTERMDISABLE => O) = (0:0:0, 0:0:0);
(INTERMDISABLE => IO) = (0:0:0, 0:0:0);
(INTERMDISABLE => IOB) = (0:0:0, 0:0:0);
(I => O) = (0:0:0, 0:0:0);
(T => O) = (0:0:0, 0:0:0);
(T => IO) = (0:0:0, 0:0:0);
(T => IOB) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifdef XIL_TIMING
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; int a[200005], n, m, k, ans; queue<int> que; inline int gi() { register int x = 0, q = 1; register char ch = getchar(); while ((ch < 0 || ch > 9 ) && ch != - ) ch = getchar(); if (ch == - ) q = -1, ch = getchar(); while (ch >= 0 && ch <= 9 ) x = x * 10 + ch - 48, ch = getchar(); return q * x; } int main() { n = gi(), m = gi(), k = gi(); for (register int i = 1; i <= n; ++i) a[i] = gi(); sort(a + 1, a + n + 1); for (register int i = 1, pos = 1, tot = 0; i <= 2000000; ++i) { while (pos <= n && a[pos] <= i) { if (tot + 1 < k) que.push(a[pos]), ++tot, ++ans; ++pos; } while (!que.empty() && que.front() + m - 1 <= i) que.pop(), --tot; } cout << n - ans; return 0; } |
`default_nettype none
`timescale 1ns / 1ps
module joypad_controller(
input wire clock,
input wire reset,
input wire int_ack,
output reg int_req,
input wire [15:0] A,
input wire [7:0] Di,
output wire [7:0] Do,
input wire rd_n,
input wire wr_n,
input wire cs,
output reg [1:0] button_sel,
input wire [3:0] button_data
);
////////////////////////////////////////////////
// Joypad Registers
//
// JOYP - Joypad (FF00)
// Bit 5: 0 <= select button keys (R/W)
// Bit 4: 0 <= select direction keys (R/W)
// Bit 3: 0 <= Down or Start
// Bit 2: 0 <= Up or Select
// Bit 1: 0 <= Left or B
// Bit 0: 0 <= Right or A
////////////////////////////////////////////////
always @(posedge clock) begin
if (reset)
int_req <= 0;
else begin
if (!wr_n) begin
if (A == 16'hFF00)
button_sel <= Di[5:4];
end
end
end
assign Do = (cs) ? { 2'b11, button_sel[1:0], button_data[3:0] } : 8'hFF;
endmodule
|
#include <bits/stdc++.h> using namespace std; int k, n; long long ans, maxim, suma; map<string, int> f; deque<pair<string, int>> box[200001], b1, b2, b; vector<pair<int, int>> trouble; string s; int val; bool comp(pair<string, int> x, pair<string, int> y) { return x.second > y.second; } int main() { cin >> k >> n; int nr = 0; for (int i = 1; i <= k; i++) { cin >> s >> val; string s1 = s; reverse(s1.begin(), s1.end()); s1 = min(s1, s); if (f[s1] == 0) { nr++; f[s1] = nr; } box[f[s1]].push_back({s, val}); } for (int i = 1; i <= nr; i++) { b = box[i]; b1.clear(); b2.clear(); b1.push_back(b[0]); for (int j = 1; j < b.size(); j++) { if (b[j].first == b1[0].first) b1.push_back(b[j]); else b2.push_back(b[j]); } sort(b1.begin(), b1.end(), comp); sort(b2.begin(), b2.end(), comp); if (!b2.empty()) { while (b1.size() != b2.size()) { if (b1.size() > b2.size()) b1.pop_back(); else b2.pop_back(); } for (int j = 0; j < b1.size(); j++) if (b1[j].second + b2[j].second > 0) ans += b1[j].second + b2[j].second; } else { s = b1.front().first; string s1 = s; reverse(s1.begin(), s1.end()); if (s == s1) { while (b1.size() >= 2) { if (b1[0].second < 0 || b1[1].second < 0) break; ans += b1[0].second + b1[1].second; b1.pop_front(); b1.pop_front(); } if (b1.size() == 1 && b1[0].second > 0) trouble.push_back({b1[0].second, -1e8}); if (b1.size() >= 2 && b1[0].second > 0) trouble.push_back({b1[0].second, b1[1].second}); } } } for (auto i : trouble) { suma += max(i.first + i.second, 0); if (suma > maxim) maxim = suma; } for (auto i : trouble) { long long sum1 = suma - max(i.first + i.second, 0) + i.first; if (sum1 > maxim) maxim = sum1; } cout << ans + maxim; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD1_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__CLKDLYINV3SD1_PP_BLACKBOX_V
/**
* clkdlyinv3sd1: Clock Delay Inverter 3-stage 0.15um length inner
* stage gate.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__clkdlyinv3sd1 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV3SD1_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int INF = 1 << 30; const int N = 5e4 + 10; int y[N]; int main() { int n; scanf( %d , &n); for (int i = 0; i < n; ++i) { scanf( %d , y + i); } int low = 1, high = 1e9; while (low != high) { int mid = (low + high) / 2; unordered_set<int> A; bool found = false; for (int i = 0; i < n; ++i) { int cur = y[i]; while (cur > mid) cur >>= 1; while (cur > 1 && A.find(cur) != A.end()) cur >>= 1; if (A.find(cur) == A.end()) { A.insert(cur); } else { found = true; break; } } if (found) { low = mid + 1; } else { high = mid; } } unordered_set<int> A; for (int i = 0; i < n; ++i) { int cur = y[i]; while (cur > high) cur >>= 1; while (cur > 1 && A.find(cur) != A.end()) cur >>= 1; if (A.find(cur) == A.end()) { A.insert(cur); printf( %d%c , cur, n [i == n - 1]); } } return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2019 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
`define checkg(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%g' exp='%g'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
integer i;
always @ (posedge clk) begin
cyc <= cyc + 1;
begin
// Type
typedef bit [3:0] nibble_t;
string a [nibble_t];
string b [nibble_t];
nibble_t k;
string v;
a[4'd3] = "fooed";
a[4'd2] = "bared";
i = a.num(); `checkh(i, 2);
i = a.size; `checkh(i, 2); // Also checks no parens
v = a[4'd3]; `checks(v, "fooed");
v = a[4'd2]; `checks(v, "bared");
i = a.exists(4'd0); `checkh(i, 0);
i = a.exists(4'd2); `checkh(i, 1);
i = a.first(k); `checkh(i, 1); `checks(k, 4'd2);
i = a.next(k); `checkh(i, 1); `checks(k, 4'd3);
i = a.next(k); `checkh(i, 0);
i = a.last(k); `checkh(i, 1); `checks(k, 4'd3);
i = a.prev(k); `checkh(i, 1); `checks(k, 4'd2);
i = a.prev(k); `checkh(i, 0);
v = $sformatf("%p", a); `checks(v, "'{'h2:\"bared\", 'h3:\"fooed\"} ");
a.first(k); `checks(k, 4'd2);
a.next(k); `checks(k, 4'd3);
a.next(k);
a.last(k); `checks(k, 4'd3);
a.prev(k); `checks(k, 4'd2);
a.delete(4'd2);
i = a.size(); `checkh(i, 1);
b = a; // Copy assignment
i = b.size(); `checkh(i, 1);
end
begin
// Strings
string a [string];
string k;
string v;
a["foo"] = "fooed";
a["bar"] = "bared";
i = a.num(); `checkh(i, 2);
i = a.size(); `checkh(i, 2);
v = a["foo"]; `checks(v, "fooed");
v = a["bar"]; `checks(v, "bared");
i = a.exists("baz"); `checkh(i, 0);
i = a.exists("bar"); `checkh(i, 1);
i = a.first(k); `checkh(i, 1); `checks(k, "bar");
i = a.next(k); `checkh(i, 1); `checks(k, "foo");
i = a.next(k); `checkh(i, 0);
i = a.last(k); `checkh(i, 1); `checks(k, "foo");
i = a.prev(k); `checkh(i, 1); `checks(k, "bar");
i = a.prev(k); `checkh(i, 0);
v = $sformatf("%p", a["foo"]); `checks(v, "\"fooed\"");
v = $sformatf("%p", a); `checks(v, "'{\"bar\":\"bared\", \"foo\":\"fooed\"} ");
a.delete("bar");
i = a.size(); `checkh(i, 1);
a.delete();
i = a.size(); `checkh(i, 0);
i = a.first(k); `checkh(i, 0);
i = a.last(k); `checkh(i, 0);
// Patterns & default
a = '{ "f": "fooed", "b": "bared", default: "defaulted" };
i = a.size(); `checkh(i, 2); // Default doesn't count
v = a["f"]; `checks(v, "fooed");
v = a["b"]; `checks(v, "bared");
v = a["NEXISTS"]; `checks(v, "defaulted");
a = '{};
i = a.size(); `checkh(i, 0);
end
begin
// Wide-wides - need special array container classes, ick.
logic [91:2] a [ logic [65:1] ];
a[~65'hfe] = ~ 90'hfee;
`checkh(a[~65'hfe], ~ 90'hfee);
end
begin
int a [string];
int sum;
sum = 0;
a["one"] = 1;
a["two"] = 2;
foreach (a[i]) sum += a[i];
`checkh(sum, 1 + 2);
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
module test();
// function with no lifetime, return-type, or port-list
function f0;
blah0;
endfunction // f0
// empty port-list
function f1();
blah1;
endfunction // f1
// non-empty portlist
function f2(stuff2);
blah2;
endfunction // f2
// test that ": function_identifier" remains unscathed
function f3;
endfunction : f3
// return type
function void f4;
blah4;
endfunction // f4
// return type with empty port-list.
function void f5();
int i;
begin
blah4;
end
endfunction // f5
// return type, non-empty portlist
// also check that a stale auto-comment gets removed
function void f6(stuff,
that,
spans,
lines);
blah5;
endfunction // f6
// test lifetime keywords 'automatic' and 'static'
function automatic f7();
endfunction // f7
// test a crazy-long function declaration
function static union packed signed {bit[1:0] a, bit[2:0] b} [5:0] f8(input ports, input ports, output ports);
endfunction // f8
// port-list that doesn't start on the same line as the function declaration
function automatic void f9
(int a,
int b);
endfunction // f9
// mismatched keyword
function f10;
endtask // unmatched end(function|task|module|primitive|interface|package|class|clocking)
// make sure previous screw-up doesn't affect future functions
function f11;
endfunction // f11
endmodule // test
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps / 1ps
`include "gpio/gpio_core.v"
`include "gpio/gpio.v"
`include "tlu/tlu_controller_core.v"
`include "tlu/tlu_controller_fsm.v"
`include "tlu/tlu_controller.v"
`include "bram_fifo/bram_fifo_core.v"
`include "bram_fifo/bram_fifo.v"
`include "utils/bus_to_ip.v"
`include "utils/cdc_syncfifo.v"
`include "utils/flag_domain_crossing.v"
`include "utils/generic_fifo.v"
`include "utils/3_stage_synchronizer.v"
`include "utils/cdc_pulse_sync.v"
module tlu_model (
input wire SYS_CLK, SYS_RST, TLU_CLOCK, TLU_BUSY, ENABLE,
output wire TLU_TRIGGER, TLU_RESET
);
reg [14:0] TRIG_ID;
reg TRIG;
wire VETO;
integer seed;
initial
seed = 0;
always @(posedge SYS_CLK) begin
if(SYS_RST)
TRIG <= 0;
else if($random(seed) % 100 == 10 && !VETO && ENABLE)
TRIG <= 1;
else
TRIG <= 0;
end
always @(posedge SYS_CLK) begin
if(SYS_RST)
TRIG_ID <= 0;
else if(TRIG)
TRIG_ID <= TRIG_ID + 1;
end
localparam WAIT_STATE = 0, TRIG_STATE = 1, READ_ID_STATE = 2;
reg [1:0] state, state_next;
always @(posedge SYS_CLK)
if(SYS_RST)
state <= WAIT_STATE;
else
state <= state_next;
always @(*) begin
state_next = state;
case(state)
WAIT_STATE:
if(TRIG)
state_next = TRIG_STATE;
TRIG_STATE:
if(TLU_BUSY)
state_next = READ_ID_STATE;
READ_ID_STATE:
if(!TLU_BUSY)
state_next = WAIT_STATE;
default : state_next = WAIT_STATE;
endcase
end
assign VETO = (state != WAIT_STATE) || (state == WAIT_STATE && TLU_CLOCK == 1'b1);
reg [15:0] TRIG_ID_SR;
initial TRIG_ID_SR = 0;
always @(posedge TLU_CLOCK or posedge TRIG)
if(TRIG)
TRIG_ID_SR <= {TRIG_ID, 1'b0};
else
TRIG_ID_SR <= {1'b0, TRIG_ID_SR[15:1]};
assign TLU_TRIGGER = (state == TRIG_STATE) | (TRIG_ID_SR[0] & TLU_BUSY);
assign TLU_RESET = 0;
endmodule
module tb (
input wire BUS_CLK,
input wire BUS_RST,
input wire [31:0] BUS_ADD,
inout wire [31:0] BUS_DATA,
input wire BUS_RD,
input wire BUS_WR,
output wire BUS_BYTE_ACCESS
);
localparam GPIO_BASEADDR = 16'h0000;
localparam GPIO_HIGHADDR = 16'h000f;
localparam TLU_BASEADDR = 16'h8200;
localparam TLU_HIGHADDR = 16'h8300-1;
localparam FIFO_BASEADDR = 32'h8100;
localparam FIFO_HIGHADDR = 32'h8200-1;
localparam FIFO_BASEADDR_DATA = 32'h8000_0000;
localparam FIFO_HIGHADDR_DATA = 32'h9000_0000;
localparam ABUSWIDTH = 32;
assign BUS_BYTE_ACCESS = BUS_ADD < 32'h8000_0000 ? 1'b1 : 1'b0;
wire TLU_TRIGGER, TLU_RESET, TLU_BUSY, TLU_CLOCK;
wire TRIGGER_ENABLE, TRIGGER, TRIGGER_VETO;
wire [4:0] NOT_CONNECTED;
wire [7:0] GPIO_IO;
wire SHORT_TRIGGER;
reg TRIGGER_FF;
assign NOT_CONNECTED = GPIO_IO[7:3];
assign TRIGGER_ENABLE = GPIO_IO[0];
assign TRIGGER = GPIO_IO[1];
assign TRIGGER_VETO = GPIO_IO[2];
always @(posedge BUS_CLK) begin
TRIGGER_FF <= TRIGGER;
end
assign SHORT_TRIGGER = TRIGGER & ~TRIGGER_FF;
gpio #(
.BASEADDR(GPIO_BASEADDR),
.HIGHADDR(GPIO_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH),
.IO_WIDTH(8),
.IO_DIRECTION(8'hff)
) i_gpio (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.IO(GPIO_IO)
);
wire TLU_FIFO_READ;
wire TLU_FIFO_EMPTY;
wire [31:0] TLU_FIFO_DATA;
wire FIFO_FULL;
wire ACKNOWLEDGE;
//assign TRIGGER_ENABLE = 1'b1;
tlu_model itlu_model (
.SYS_CLK(BUS_CLK),
.SYS_RST(BUS_RST),
.ENABLE(TRIGGER_ENABLE),
.TLU_CLOCK(TLU_CLOCK),
.TLU_BUSY(TLU_BUSY),
.TLU_TRIGGER(TLU_TRIGGER),
.TLU_RESET(TLU_RESET)
);
tlu_controller #(
.BASEADDR(TLU_BASEADDR),
.HIGHADDR(TLU_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH),
.DIVISOR(16),
.TLU_TRIGGER_MAX_CLOCK_CYCLES(16)
) i_tlu_controller (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.TRIGGER_CLK(BUS_CLK),
.FIFO_READ(TLU_FIFO_READ),
.FIFO_EMPTY(TLU_FIFO_EMPTY),
.FIFO_DATA(TLU_FIFO_DATA),
.FIFO_PREEMPT_REQ(),
.TRIGGER_ENABLED(),
.TRIGGER_SELECTED(),
.TLU_ENABLED(),
.TRIGGER({5'b0, SHORT_TRIGGER, TRIGGER, TLU_TRIGGER}),
.TRIGGER_VETO({6'b0, TRIGGER_VETO, 1'b1}),
.TLU_TRIGGER(TLU_TRIGGER),
.TLU_RESET(TLU_RESET),
.TLU_BUSY(TLU_BUSY),
.TLU_CLOCK(TLU_CLOCK),
.EXT_TRIGGER_ENABLE(1'b0),
.TRIGGER_ACKNOWLEDGE(1'b0),
.TRIGGER_ACCEPTED_FLAG(),
.TIMESTAMP()
);
wire FIFO_READ, FIFO_EMPTY;
wire [31:0] FIFO_DATA;
assign FIFO_DATA = TLU_FIFO_DATA;
assign FIFO_EMPTY = TLU_FIFO_EMPTY;
assign TLU_FIFO_READ = FIFO_READ;
bram_fifo #(
.BASEADDR(FIFO_BASEADDR),
.HIGHADDR(FIFO_HIGHADDR),
.BASEADDR_DATA(FIFO_BASEADDR_DATA),
.HIGHADDR_DATA(FIFO_HIGHADDR_DATA),
.ABUSWIDTH(ABUSWIDTH)
) i_out_fifo (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.FIFO_READ_NEXT_OUT(FIFO_READ),
.FIFO_EMPTY_IN(FIFO_EMPTY),
.FIFO_DATA(FIFO_DATA),
.FIFO_NOT_EMPTY(),
.FIFO_FULL(FIFO_FULL),
.FIFO_NEAR_FULL(),
.FIFO_READ_ERROR()
);
initial begin
$dumpfile("tlu.vcd");
$dumpvars(0);
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVERNOVLP2_BEHAVIORAL_V
`define SKY130_FD_SC_LP__BUSDRIVERNOVLP2_BEHAVIORAL_V
/**
* busdrivernovlp2: Bus driver, enable gates pulldown only (pmos
* devices).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__busdrivernovlp2 (
Z ,
A ,
TE_B
);
// Module ports
output Z ;
input A ;
input TE_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
bufif0 bufif00 (Z , A, TE_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVERNOVLP2_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; const long long mod = 1000000007; int n; int m; int a, b; long long fast_mod_pow(long long a, long long b) { long long res = 1; a %= mod; while (b) { if (b & 1) { res = (res * a) % mod; } a = (a * a) % mod; b >>= 1; } return res; } const int MAXN = 1000005; long long fac[MAXN]; long long invfact[MAXN]; int main() { cin >> n >> m >> a >> b; long long ans = 0; fac[0] = 1; fac[1] = 1; for (int i = 2; i < MAXN; i++) { fac[i] = fac[i - 1] * i; fac[i] %= mod; } invfact[MAXN - 1] = fast_mod_pow(fac[MAXN - 1], mod - 2); for (int i = MAXN - 2; i >= 0; i--) { invfact[i] = (invfact[i + 1] * (i + 1)) % mod; } for (int i = 1; i <= m; i++) { if (i > n - 1) break; long long temp = 1; temp *= fac[m - 1]; temp %= mod; temp *= invfact[m - i]; temp %= mod; temp *= invfact[i - 1]; temp %= mod; temp *= fac[n - 2]; temp %= mod; temp *= invfact[n - i - 1]; temp %= mod; if ((n - i - 1) == 0) { ans += temp; ans %= mod; continue; } temp *= fast_mod_pow((long long)m, (long long)(n - i - 1)); temp %= mod; temp *= (i + 1); temp %= mod; temp *= fast_mod_pow((long long)n, (long long)(n - i - 2)); temp %= mod; ans += temp; ans %= mod; } cout << ans << endl; return 0; } |
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