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#include <bits/stdc++.h> using namespace std; signed main() { ios_base::sync_with_stdio(false); cin.tie(0); int n; cin >> n; set<int> ms; for (int i = 0; i < n; ++i) { int x; cin >> x; if (x) ms.insert(x); } cout << ms.size() << n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DIODE_SYMBOL_V
`define SKY130_FD_SC_HS__DIODE_SYMBOL_V
/**
* diode: Antenna tie-down diode.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__diode (
//# {{power|Power}}
input DIODE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DIODE_SYMBOL_V
|
/*
* Copyright (c) 2000 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* The assignment to the input of a task port should pad with
* zeros. It seems that certain Verilog bugs can cause this test to
* fail.
*/
module test;
task writeInto;
input [31:0] x;
begin
$display("x=%h", x);
if (x[31:10] !== 22'd0) begin
$display("FAILED -- x is %b", x);
$finish;
end
end
endtask
reg [7:0] y;
reg [31:0] y1;
initial begin
y1 = 512;
y = 4;
writeInto(y1);
writeInto(y);
$display("PASSED");
end
endmodule
|
// Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2013.4 (lin64) Build 353583 Mon Dec 9 17:26:26 MST 2013
// Date : Sat Mar 15 17:45:54 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode synth_stub
// /home/keith/Documents/VHDL-lib/top/lab_2/part_1/build/lab2_part1.srcs/sources_1/ip/clk_video/clk_video_stub.v
// Design : clk_video
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module clk_video(clk_100MHz, clk_193MHz, locked)
/* synthesis syn_black_box black_box_pad_pin="clk_100MHz,clk_193MHz,locked" */;
input clk_100MHz;
output clk_193MHz;
output locked;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/12/2016 06:26:54 PM
// Design Name:
// Module Name: shift_mux_array
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module shift_mux_array
#(parameter SWR=26, parameter LEVEL=5)
(
input wire [SWR-1:0] Data_i,
input wire select_i,
input wire bit_shift_i,
output wire [SWR-1:0] Data_o
);
genvar j;
localparam integer lvl = 2**(LEVEL);
localparam integer x = (SWR - 1);
generate for (j=0; j<=SWR-1 ; j=j+1) begin : MUX_ODDNORM
localparam integer sh=(2**LEVEL)+j; //value for second mux input. It changes in exponentation by 2 for each level
case ((lvl+j)>(x))
1'b1: begin :BSHITMUX
//assign mux_out = (sel) ? din_1 : din_0;
assign Data_o[j] = (select_i) ? bit_shift_i : Data_i[j];
end
1'b0: begin : FSHITMUX
assign Data_o[j] = (select_i) ? Data_i[lvl+j] : Data_i[j];
end
endcase
end
endgenerate
endmodule
|
//`timescale 1 ms /1 us
`include "mux81b.v"
module chap4p32b_tb (S);
// module declaration
output [0:3] S;
reg [0:3] S;
//S[0]=A, S[1]=B, S[2]=C, S[3]=D
wire [0:7] I;
wire Y;
integer fp;
// program body
assign I[0]=~S[3];
assign I[1]=~S[3];
assign I[2]=S[3];
assign I[3]=S[3];
assign I[4]=1'b0;
assign I[5]=S[3];
assign I[6]=1'b0;
assign I[7]=~S[3];
mux81b I1 (I,S[0:2],Y);
initial
begin
fp=$fopen("./chap4p32b_tb.out");
$fmonitor(fp,"time=%0d",$time,,"I=%b S=%b Y=%b",I,S,Y);
#2000
$fclose(fp);
$finish;
end
initial
begin
S=4'b0000;
#100
S=4'b0001;
#100
S=4'b0010;
#100
S=4'b0011;
#100
S=4'b0100;
#100
S=4'b0101;
#100
S=4'b0110;
#100
S=4'b0111;
#100
S=4'b1000;
#100
S=4'b1001;
#100
S=4'b1010;
#100
S=4'b1011;
#100
S=4'b1100;
#100
S=4'b1101;
#100
S=4'b1110;
#100
S=4'b1111;
end
initial #4000 $finish;
endmodule
|
/*
Shift Module Accepts the 11:4 bits of the instruction and Bit 25 (I)
Bit 4 >
1 >> Reg shift
0 >> constent amount
bits 6:5 >
LSL 00 Logical shift left
LSR 01 Logical shift right
ASR 10 Arithmetic shift right
ROR 11 Rotate right
bits 11:7 >
Shamt5 or Rs ( lower 8 bits of the register )
bit 25 >> enable the shift or not ..
the RD2 from the Reg file and perform the shift operation
*/
module shift(Inst,Enable,RD2_input,ALUSrc2_output);
input [7:0] Inst;
input Enable;
input [31:0] RD2_input;
output [31:0] ALUSrc2_output;
wire [4:0] shamt5;
assign shamt5[4:0]=(Inst[0]==0)? Inst[7:3] :5'b00000;
wire [1:0] sh;
assign sh[1:0]=Inst[2:1];
/*
LSL 00 Logical shift left
LSR 01 Logical shift right
ASR 10 Arithmetic shift right
ROR 11 Rotate right
*/
wire [31:0] internal_output;
assign internal_output= (sh[1]==1) ? ( (sh[0]==1)? ( (RD2_input>>shamt5)|(RD2_input<<32-shamt5) ):( (RD2_input>>shamt5)|({32{1'b1}}<<32-shamt5) ) ) : ( (sh[0]==1)? (RD2_input>>shamt5):(RD2_input<<shamt5) );
assign ALUSrc2_output = (Enable==1)? internal_output : RD2_input;
endmodule |
#include <bits/stdc++.h> using namespace std; #define INF 200000000000000000LL typedef long long int ll; typedef pair<ll,ll> ii; typedef pair<ii,ll> iii; typedef vector<ll> vi; typedef vector<ii> vii; #define getbit(n,i) (((n)&(1LL<<(i)))!=0) #define setbit0(n,i) ((n)&(~(1LL<<(i)))) #define setbit1(n,i) ((n)|(1LL<<(i))) #define lastone(n) ((n)&(-(n))) #define read freopen( debug//in.txt , r ,stdin) #define write freopen( debug//out.txt , w ,stdout) #define DBG(a) cerr<<#a<< ->->->-> <<a<< n #define fi first #define se second #define PI (acos(-1)) #define fastread ios::sync_with_stdio(false);cin.tie(NULL) mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); #define mod (1000000007) #define asz 500005 template<class T,class V> ostream& operator<<(ostream &s,pair<T,V> a) { s<<a.fi<< <<a.se; return s; } const int N = 1e3+5; int main() { fastread; #ifdef FILE_IO read; write; #endif int T=1; cin>>T; for(int qq=1; qq<=T; qq++) { int n; string s; cin>>n>>s; vi l(n+2),r(n+2); r[n] = 1; r[n-1] = 1 + (s.back() == R ); l[0] = 1; l[1] = 1 + (s[0] == L ); for(int i=2;i<=n;i++){ if(s[i-1] == L ){ if(s[i-2] == R )l[i] = 2+l[i-2]; else l[i] = 2; } else l[i] = 1; if(s[n-i] == R ){ if(s[n-i+1] == L )r[n-i] = 2+r[n-i+2]; else r[n-i] = 2; } else r[n-i] = 1; } for(int i=0;i<=n;i++)cout<<l[i]+r[i]-1<< ; cout<<endl; } } |
#include <bits/stdc++.h> using namespace std; long long n, m, q; long long gcd(long long a, long long b) { if (a < b) swap(a, b); if (b == 0) return a; return gcd(b, a % b); } int main() { cin >> n >> m >> q; long long v = gcd(n, m); long long innersize = n / v; long long outersize = m / v; for (int i = 0; i < q; i++) { long long s1, x1, s2, x2; cin >> s1 >> x1 >> s2 >> x2; x1--; x2--; if (s1 == 1) { x1 /= innersize; } else { x1 /= outersize; } if (s2 == 1) { x2 /= innersize; } else { x2 /= outersize; } if (x1 == x2) { cout << YES n ; } else { cout << NO n ; } } } |
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate continuous <= in assignment.
//
module main;
reg globvar;
reg [3:0] var1;
reg error;
wire var2 = (4'h02 >= var1);
initial
begin
error = 0;
var1 = 4'h0 ;
#1 ;
if(var2 !== 1'b1)
begin
$display("FAILED continuous >= logical op (1)");
error = 1;
end
#1 ;
var1 = 4'h2;
#1 ;
if(var2 !== 1'b1)
begin
$display("FAILED continuos <= logical op (2)");
error = 1;
end
#1 ;
var1 = 4'h4;
#1 ;
if(var2 !== 1'b0)
begin
$display("FAILED continuos <= logical op (3)");
error = 1;
end
if(error == 0)
$display("PASSED");
end
endmodule // main
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_arb_hp0_1.v
*
* Date : 2012-11
*
* Description : Module that arbitrates between RD/WR requests from 2 ports.
* Used for modelling the Top_Interconnect switch.
*****************************************************************************/
module processing_system7_bfm_v2_0_arb_hp0_1(
sw_clk,
rstn,
w_qos_hp0,
r_qos_hp0,
w_qos_hp1,
r_qos_hp1,
wr_ack_ddr_hp0,
wr_data_hp0,
wr_addr_hp0,
wr_bytes_hp0,
wr_dv_ddr_hp0,
rd_req_ddr_hp0,
rd_addr_hp0,
rd_bytes_hp0,
rd_data_ddr_hp0,
rd_dv_ddr_hp0,
wr_ack_ddr_hp1,
wr_data_hp1,
wr_addr_hp1,
wr_bytes_hp1,
wr_dv_ddr_hp1,
rd_req_ddr_hp1,
rd_addr_hp1,
rd_bytes_hp1,
rd_data_ddr_hp1,
rd_dv_ddr_hp1,
ddr_wr_ack,
ddr_wr_dv,
ddr_rd_req,
ddr_rd_dv,
ddr_rd_qos,
ddr_wr_qos,
ddr_wr_addr,
ddr_wr_data,
ddr_wr_bytes,
ddr_rd_addr,
ddr_rd_data,
ddr_rd_bytes
);
`include "processing_system7_bfm_v2_0_local_params.v"
input sw_clk;
input rstn;
input [axi_qos_width-1:0] w_qos_hp0;
input [axi_qos_width-1:0] r_qos_hp0;
input [axi_qos_width-1:0] w_qos_hp1;
input [axi_qos_width-1:0] r_qos_hp1;
input [axi_qos_width-1:0] ddr_rd_qos;
input [axi_qos_width-1:0] ddr_wr_qos;
output wr_ack_ddr_hp0;
input [max_burst_bits-1:0] wr_data_hp0;
input [addr_width-1:0] wr_addr_hp0;
input [max_burst_bytes_width:0] wr_bytes_hp0;
output wr_dv_ddr_hp0;
input rd_req_ddr_hp0;
input [addr_width-1:0] rd_addr_hp0;
input [max_burst_bytes_width:0] rd_bytes_hp0;
output [max_burst_bits-1:0] rd_data_ddr_hp0;
output rd_dv_ddr_hp0;
output wr_ack_ddr_hp1;
input [max_burst_bits-1:0] wr_data_hp1;
input [addr_width-1:0] wr_addr_hp1;
input [max_burst_bytes_width:0] wr_bytes_hp1;
output wr_dv_ddr_hp1;
input rd_req_ddr_hp1;
input [addr_width-1:0] rd_addr_hp1;
input [max_burst_bytes_width:0] rd_bytes_hp1;
output [max_burst_bits-1:0] rd_data_ddr_hp1;
output rd_dv_ddr_hp1;
input ddr_wr_ack;
output ddr_wr_dv;
output [addr_width-1:0]ddr_wr_addr;
output [max_burst_bits-1:0]ddr_wr_data;
output [max_burst_bytes_width:0]ddr_wr_bytes;
input ddr_rd_dv;
input [max_burst_bits-1:0] ddr_rd_data;
output ddr_rd_req;
output [addr_width-1:0] ddr_rd_addr;
output [max_burst_bytes_width:0] ddr_rd_bytes;
processing_system7_bfm_v2_0_arb_wr ddr_hp_wr(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(w_qos_hp0),
.qos2(w_qos_hp1),
.prt_dv1(wr_dv_ddr_hp0),
.prt_dv2(wr_dv_ddr_hp1),
.prt_data1(wr_data_hp0),
.prt_data2(wr_data_hp1),
.prt_addr1(wr_addr_hp0),
.prt_addr2(wr_addr_hp1),
.prt_bytes1(wr_bytes_hp0),
.prt_bytes2(wr_bytes_hp1),
.prt_ack1(wr_ack_ddr_hp0),
.prt_ack2(wr_ack_ddr_hp1),
.prt_req(ddr_wr_dv),
.prt_qos(ddr_wr_qos),
.prt_data(ddr_wr_data),
.prt_addr(ddr_wr_addr),
.prt_bytes(ddr_wr_bytes),
.prt_ack(ddr_wr_ack)
);
processing_system7_bfm_v2_0_arb_rd ddr_hp_rd(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(r_qos_hp0),
.qos2(r_qos_hp1),
.prt_req1(rd_req_ddr_hp0),
.prt_req2(rd_req_ddr_hp1),
.prt_data1(rd_data_ddr_hp0),
.prt_data2(rd_data_ddr_hp1),
.prt_addr1(rd_addr_hp0),
.prt_addr2(rd_addr_hp1),
.prt_bytes1(rd_bytes_hp0),
.prt_bytes2(rd_bytes_hp1),
.prt_dv1(rd_dv_ddr_hp0),
.prt_dv2(rd_dv_ddr_hp1),
.prt_qos(ddr_rd_qos),
.prt_req(ddr_rd_req),
.prt_data(ddr_rd_data),
.prt_addr(ddr_rd_addr),
.prt_bytes(ddr_rd_bytes),
.prt_dv(ddr_rd_dv)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFXTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__SDFXTP_FUNCTIONAL_PP_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ms__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__sdfxtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_ms__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFXTP_FUNCTIONAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLXBN_FUNCTIONAL_V
`define SKY130_FD_SC_LP__DLXBN_FUNCTIONAL_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p/sky130_fd_sc_lp__udp_dlatch_p.v"
`celldefine
module sky130_fd_sc_lp__dlxbn (
Q ,
Q_N ,
D ,
GATE_N
);
// Module ports
output Q ;
output Q_N ;
input D ;
input GATE_N;
// Local signals
wire GATE ;
wire buf_Q ;
wire GATE_N_delayed;
wire D_delayed ;
// Delay Name Output Other arguments
sky130_fd_sc_lp__udp_dlatch$P `UNIT_DELAY dlatch0 (buf_Q , D, GATE );
not not0 (GATE , GATE_N );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLXBN_FUNCTIONAL_V |
//
///////////////////////////////////////////////////////////////////////////////////////////
// Copyright © 2011-2012, Xilinx, Inc.
// This file contains confidential and proprietary information of Xilinx, Inc. and is
// protected under U.S. and international copyright and other intellectual property laws.
///////////////////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
// This disclaimer is not a license and does not grant any rights to the materials
// distributed herewith. Except as otherwise provided in a valid license issued to
// you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
// MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
// DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
// INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
// OR FITNESS FOR ANY PARTICULAR PURPOSE; and [2] Xilinx shall not be liable
// (whether in contract or tort, including negligence, or under any other theory
// of liability) for any loss or damage of any kind or nature related to, arising
// under or in connection with these materials, including for any direct, or any
// indirect, special, incidental, or consequential loss or damage (including loss
// of data, profits, goodwill, or any type of loss or damage suffered as a result
// of any action brought by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-safe, or for use in any
// application requiring fail-safe performance, such as life-support or safety
// devices or systems, Class III medical devices, nuclear facilities, applications
// related to the deployment of airbags, or any other applications that could lead
// to death, personal injury, or severe property or environmental damage
// (individually and collectively, "Critical Applications"). Customer assumes the
// sole risk and liability of any use of Xilinx products in Critical Applications,
// subject only to applicable laws and regulations governing limitations on product
// liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
///////////////////////////////////////////////////////////////////////////////////////////
//
//
// KCPSM6 reference design using 'uart_tx6' and 'uart_rx6'macros.
//
// Ken Chapman - Xilinx Ltd.
//
// 30th April 2012 - Conversion from original VHDL version (30th April 2012).
// 30th July 2014 - Corrections to comment only.
//
// This reference design provides a simple UART communication example.
// Please see 'UART6_User_Guide_and_Reference_Designs_30Sept14.pdf' for more detailed
// descriptions.
//
// The code in this example is set to implement a 115200 baud rate when using a 50MHz
// clock. Whilst the design is presented as a working example for the XC6VLX240T-1FF1156
// device on the ML605 Evaluation Board (www.xilinx.com) it is a simple reference design
// that is easily adapted or incorporated into a design for use with any hardware platform.
//
//
//////////////////////////////////////////////////////////////////////////////////////////-
//
//
module uart6_ml605 ( input uart_rx,
input clk200_p,
input clk200_n,
output uart_tx );
//
///////////////////////////////////////////////////////////////////////////////////////////
// Signals
///////////////////////////////////////////////////////////////////////////////////////////
//
// Signals used to create 50MHz clock from 200MHz differential clock
//
wire clk200;
wire clk;
// Signals used to connect KCPSM6
wire [11:0] address;
wire [17:0] instruction;
wire bram_enable;
reg [7:0] in_port;
wire [7:0] out_port;
wire [7:0] port_id;
wire write_strobe;
wire k_write_strobe;
wire read_strobe;
wire interrupt;
wire interrupt_ack;
wire kcpsm6_sleep;
wire kcpsm6_reset;
wire rdl;
// Signals used to connect UART_TX6
wire [7:0] uart_tx_data_in;
wire write_to_uart_tx;
wire uart_tx_data_present;
wire uart_tx_half_full;
wire uart_tx_full;
reg uart_tx_reset;
// Signals used to connect UART_RX6
wire [7:0] uart_rx_data_out;
reg read_from_uart_rx;
wire uart_rx_data_present;
wire uart_rx_half_full;
wire uart_rx_full;
reg uart_rx_reset;
// Signals used to define baud rate
reg [4:0] baud_count;
reg en_16_x_baud;
//
//
///////////////////////////////////////////////////////////////////////////////////////////
//
// Start of circuit description
//
///////////////////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////////////////
// Create 50MHz clock from 200MHz differential clock
/////////////////////////////////////////////////////////////////////////////////////////
IBUFGDS diff_clk_buffer(
.I(clk200_p),
.IB(clk200_n),
.O(clk200));
// BUFR used to divide by 4 and create a regional clock
BUFR #(
.BUFR_DIVIDE("4"),
.SIM_DEVICE("VIRTEX6"))
clock_divide (
.I(clk200),
.O(clk),
.CE(1'b1),
.CLR(1'b0));
/////////////////////////////////////////////////////////////////////////////////////////
// Instantiate KCPSM6 and connect to program ROM
/////////////////////////////////////////////////////////////////////////////////////////
//
// The generics can be defined as required. In this case the 'hwbuild' value is used to
// define a version using the ASCII code for the desired letter.
//
kcpsm6 #(
.interrupt_vector (12'h7F0),
.scratch_pad_memory_size(64),
.hwbuild (8'h42)) // 42 hex is ASCII Character "B"
processor (
.address (address),
.instruction (instruction),
.bram_enable (bram_enable),
.port_id (port_id),
.write_strobe (write_strobe),
.k_write_strobe (k_write_strobe),
.out_port (out_port),
.read_strobe (read_strobe),
.in_port (in_port),
.interrupt (interrupt),
.interrupt_ack (interrupt_ack),
.reset (kcpsm6_reset),
.sleep (kcpsm6_sleep),
.clk (clk));
// Reset connected to JTAG Loader enabled Program Memory
assign kcpsm6_reset = rdl;
// Unused signals tied off until required.
assign kcpsm6_sleep = 1'b0;
assign interrupt = interrupt_ack;
// Development Program Memory
// JTAG Loader enabled for rapid code development.
uart_control #(
.C_FAMILY ("V6"),
.C_RAM_SIZE_KWORDS (2),
.C_JTAG_LOADER_ENABLE (1))
program_rom (
.rdl (rdl),
.enable (bram_enable),
.address (address),
.instruction (instruction),
.clk (clk));
/////////////////////////////////////////////////////////////////////////////////////////
// UART Transmitter with integral 16 byte FIFO buffer
/////////////////////////////////////////////////////////////////////////////////////////
//
// Write to buffer in UART Transmitter at port address 01 hex
//
uart_tx6 tx(
.data_in(uart_tx_data_in),
.en_16_x_baud(en_16_x_baud),
.serial_out(uart_tx),
.buffer_write(write_to_uart_tx),
.buffer_data_present(uart_tx_data_present),
.buffer_half_full(uart_tx_half_full ),
.buffer_full(uart_tx_full),
.buffer_reset(uart_tx_reset),
.clk(clk));
/////////////////////////////////////////////////////////////////////////////////////////
// UART Receiver with integral 16 byte FIFO buffer
/////////////////////////////////////////////////////////////////////////////////////////
//
// Read from buffer in UART Receiver at port address 01 hex.
//
// When KCPMS6 reads data from the receiver a pulse must be generated so that the
// FIFO buffer presents the next character to be read and updates the buffer flags.
//
uart_rx6 rx(
.serial_in(uart_rx),
.en_16_x_baud(en_16_x_baud ),
.data_out(uart_rx_data_out ),
.buffer_read(read_from_uart_rx ),
.buffer_data_present(uart_rx_data_present ),
.buffer_half_full(uart_rx_half_full ),
.buffer_full(uart_rx_full ),
.buffer_reset(uart_rx_reset ),
.clk(clk ));
//
/////////////////////////////////////////////////////////////////////////////////////////
// RS232 (UART) baud rate
/////////////////////////////////////////////////////////////////////////////////////////
//
// To set serial communication baud rate to 115,200 then en_16_x_baud must pulse
// High at 1,843,200Hz which is every 27.13 cycles at 50MHz. In this implementation
// a pulse is generated every 27 cycles resulting is a baud rate of 115,741 baud which
// is only 0.5% high and well within limits.
//
always @ (posedge clk )
begin
if (baud_count == 5'b11010) begin // counts 27 states including zero
baud_count <= 5'b00000;
en_16_x_baud <= 1'b1; // single cycle enable pulse
end
else begin
baud_count <= baud_count + 5'b00001;
en_16_x_baud <= 1'b0;
end
end
//
/////////////////////////////////////////////////////////////////////////////////////////
// General Purpose Input Ports.
/////////////////////////////////////////////////////////////////////////////////////////
//
// Two input ports are used with the UART macros. The first is used to monitor the flags
// on both the transmitter and receiver. The second is used to read the data from the
// receiver and generate the 'buffer_read' pulse.
//
always @ (posedge clk)
begin
case (port_id[0])
// Read UART status at port address 00 hex
1'b0 : in_port <= { 2'b00,
uart_rx_full,
uart_rx_half_full,
uart_rx_data_present,
uart_tx_full,
uart_tx_half_full,
uart_tx_data_present };
// Read UART_RX6 data at port address 01 hex
// (see 'buffer_read' pulse generation below)
1'b1 : in_port <= uart_rx_data_out;
default : in_port <= 8'bXXXXXXXX ;
endcase;
// Generate 'buffer_read' pulse following read from port address 01
if ((read_strobe == 1'b1) && (port_id[0] == 1'b1)) begin
read_from_uart_rx <= 1'b1;
end
else begin
read_from_uart_rx <= 1'b0;
end
end
//
/////////////////////////////////////////////////////////////////////////////////////////
// General Purpose Output Ports
/////////////////////////////////////////////////////////////////////////////////////////
//
// In this simple example there is only one output port and that it involves writing
// directly to the FIFO buffer within 'uart_tx6'. As such the only requirements are to
// connect the 'out_port' to the transmitter macro and generate the write pulse.
//
assign uart_tx_data_in = out_port;
assign write_to_uart_tx = write_strobe & port_id[0];
//
/////////////////////////////////////////////////////////////////////////////////////////
// Constant-Optimised Output Ports
/////////////////////////////////////////////////////////////////////////////////////////
//
// One constant-optimised output port is used to facilitate resetting of the UART macros.
//
always @ (posedge clk)
begin
if (k_write_strobe == 1'b1) begin
if (port_id[0] == 1'b1) begin
uart_tx_reset <= out_port[0];
uart_rx_reset <= out_port[1];
end
end
end
/////////////////////////////////////////////////////////////////////////////////////////
endmodule
//
///////////////////////////////////////////////////////////////////////////////////////////
// END OF FILE uart6_ml605.v
///////////////////////////////////////////////////////////////////////////////////////////
//
|
#include <bits/stdc++.h> using namespace std; int execute() { int n; cin >> n; string s; s.assign(n / 2 - 1, 1 ); if (n % 2) { cout << 7; } else { cout << 1; } cout << s << endl; return 0; } int TE = true; bool mTest = true; int main() { ios_base::sync_with_stdio(false); if (mTest) cin >> TE; while (TE--) { execute(); } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long N = 4, M = 1e5 + 10, Mo = 1e9 + 7; long long n, m, nxt[M], p, lena, lenb, lens; string aa, bb, s; struct Matrix { long long n, a[N][N]; Matrix(long long _n = 4) { n = _n, memset(a, 0, sizeof(a)); } void operator~() { for (long long i = 0; i < 4; i++) a[i][i] = 1; } Matrix operator+(const Matrix &b) const { Matrix ret(4); for (long long i = 0; i < 4; i++) for (long long j = 0; j < 4; j++) ret.a[i][j] = (a[i][j] + b.a[i][j]) % Mo; return ret; } Matrix operator-(const Matrix &b) const { Matrix ret(4); for (long long i = 0; i < 4; i++) for (long long j = 0; j < 4; j++) ret.a[i][j] = (a[i][j] - b.a[i][j] + Mo) % Mo; return ret; } Matrix operator*(const Matrix &b) const { Matrix ret(4); for (long long i = 0; i < 4; i++) for (long long j = 0; j < 4; j++) for (long long k = 0; k < 4; k++) ret.a[i][k] = (ret.a[i][k] + 1LL * a[i][j] * b.a[j][k] % Mo + Mo) % Mo; return ret; } Matrix operator^(const long long &b) const { Matrix ret, x, m1, m2; for (long long i = 0; i < 4; i++) for (long long j = 0; j < 4; j++) if (i == j) ret.a[i][j] = 1; else ret.a[i][j] = 0; for (long long i = 0; i < 4; i++) for (long long j = 0; j < 4; j++) m1.a[i][j] = m2.a[i][j] = 0; m1.a[0][0] = m1.a[0][1] = m1.a[1][0] = m1.a[2][2] = m1.a[2][3] = m1.a[3][2] = m2.a[0][0] = m2.a[0][1] = m2.a[1][0] = m2.a[2][0] = m2.a[3][2] = 1; x = m2 * m1; for (long long B = b >> 1; B; B >>= 1, x = x * x) { if (B & 1) ret = ret * x; } if (b & 1) ret = m1 * ret; return ret; } } a, b, c, m1, m2; inline long long read() { long long x = 0, k = 1; char c = getchar(); for (; c < 48 || c > 57; c = getchar()) k ^= (c == - ); for (; c >= 48 && c <= 57; c = getchar()) x = x * 10 + (c ^ 48); return k ? x : -x; } long long kmp1(long long l, long long r) { long long ans = 0; for (long long i = 0, p = 0; i < r; i++) { for (; (~p) && s[p] != aa[i]; p = nxt[p]) ; p = p + 1; if (p == lens && i >= l && i <= r - 1) ans = ans + 1, p = nxt[p]; else if (p == lens) p = nxt[p]; } return ans; } long long kmp2(long long l, long long r) { long long ans = 0; for (long long i = 0, p = 0; i < r; i++) { for (; (~p) && s[p] != bb[i]; p = nxt[p]) ; p = p + 1; if (p == lens && i >= l && i <= r - 1) ans = ans + 1, p = nxt[p]; else if (p == lens) p = nxt[p]; } return ans; } long long KMP(const string &b, long long l, long long r) { long long ans = 0; long long lenb = b.length(); for (long long i = 0, p = 0; i < lenb; i++) { for (; (~p) && s[p] != b[i]; p = nxt[p]) ; p = p + 1; if (p == lens && i >= l && i <= r - 1) ans = ans + 1, p = nxt[p]; else if (p == lens) p = nxt[p]; } return ans; } signed main() { m1.a[0][0] = m1.a[0][1] = m1.a[1][0] = m1.a[2][2] = m1.a[2][3] = m1.a[3][2] = m2.a[0][0] = m2.a[0][1] = m2.a[1][0] = m2.a[2][0] = m2.a[3][2] = 1; std::ios::sync_with_stdio(false); std::cin >> n; long long T; std::cin >> T; for (long long x; T--;) { std::cin >> s; aa = a , bb = b ; lena = aa.length(), lenb = bb.length(), lens = s.length(), nxt[0] = -1, p = 0; ; for (long long i = 0; i < lens; i++) { for (p = nxt[i]; (~p) && s[p] != s[i]; p = nxt[p]) ; nxt[i + 1] = ++p; } if (n == 1) { printf( %lld n , kmp1(0, lena)); } else if (n == 2) { printf( %lld n , kmp2(0, lenb)); } else { for (x = 1; lena < lens && x <= n; ++x) { aa = bb + aa; std::swap(aa, bb); lena = aa.length(); } lenb = bb.length(); if (x > n) printf( 0 n ); else if (x == n) printf( %lld n , kmp1(0, lena)); else { lena = aa.length(), lenb = bb.length(), lens = s.length(); long long tt = n - x - 1; c = c ^ tt; printf( %lld n , (c.a[0][0] % Mo * kmp2(0, lenb) % Mo + c.a[1][0] % Mo * KMP(bb + aa, lenb, lena + lenb) % Mo + c.a[2][0] % Mo * KMP(aa + bb, lena, lena + lens - 1) % Mo + c.a[3][0] % Mo * KMP(bb + bb, lenb, lenb + lens - 1) % Mo) % Mo); } } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUXB16TO1_2_V
`define SKY130_FD_SC_HDLL__MUXB16TO1_2_V
/**
* muxb16to1: Buffered 16-input multiplexer.
*
* Verilog wrapper for muxb16to1 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__muxb16to1.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__muxb16to1_2 (
Z ,
D ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input [15:0] D ;
input [15:0] S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__muxb16to1 base (
.Z(Z),
.D(D),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__muxb16to1_2 (
Z,
D,
S
);
output Z;
input [15:0] D;
input [15:0] S;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__muxb16to1 base (
.Z(Z),
.D(D),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUXB16TO1_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EINVN_2_V
`define SKY130_FD_SC_LP__EINVN_2_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog wrapper for einvn with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__einvn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__einvn_2 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__einvn_2 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__EINVN_2_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2017/07/21 15:17:42
// Design Name:
// Module Name: segDisplayDriver
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
//Driver for 4-digits 7-segments display.
module segDisplayDriver(clk,data,out_dig,out_seg);
input clk;
input [15:0] data;
output [3:0] out_dig;
output [7:0] out_seg;
//·ÖƵ
reg [31:0] clk_cnt;
reg clk_500Hz;
always @ (posedge clk)
if(clk_cnt == 32'd200_000) begin
clk_cnt <= 1'b0;
clk_500Hz <= ~clk_500Hz;
end
else
clk_cnt <= clk_cnt + 1'b1;
//Digit Control
reg [3:0] dig_ctrl = 4'b1110;
always @(posedge clk_500Hz)
dig_ctrl <= { dig_ctrl[2:0], dig_ctrl[3] };
//Segment Control
reg [4:0] seg_ctrl;
always @ (dig_ctrl)
case(dig_ctrl)
4'b1110: seg_ctrl={1'b0,data[3:0]};
4'b1101: seg_ctrl={1'b0,data[7:4]};
4'b1011: seg_ctrl={1'b0,data[11:8]};
4'b0111: seg_ctrl={1'b0,data[15:12]};
default: seg_ctrl=5'h1f;
endcase
//----------------------------------------------------------
//½âÂëÄ£¿é
reg [7:0] seg_reg;
//seg_reg = {dp,g,f,e,d,c,b,a}
always @( seg_ctrl )
case( seg_ctrl )
5'h00: seg_reg = 8'b1100_0000;//0
5'h01: seg_reg = 8'b1111_1001;//1
5'h02: seg_reg = 8'b1010_0100;//2
5'h03: seg_reg = 8'b1011_0000;//3
5'h04: seg_reg = 8'b1001_1001;//4
5'h05: seg_reg = 8'b1001_0010;//5
5'h06: seg_reg = 8'b1000_0010;//6
5'h07: seg_reg = 8'b1111_1000;//7
5'h08: seg_reg = 8'b1000_0000;//8
5'h09: seg_reg = 8'b1001_0000;//9
5'h0a: seg_reg = 8'b1000_1000;//a
5'h0b: seg_reg = 8'b1000_0011;//b
5'h0c: seg_reg = 8'b1100_0110;//c
5'h0d: seg_reg = 8'b1010_0001;//d
5'h0e: seg_reg = 8'b1000_0110;//e
5'h0f: seg_reg = 8'b1000_1110;//f
5'h10: seg_reg = 8'b1111_1111;//None
5'h11: seg_reg = 8'b1100_0111;//L
5'h12: seg_reg = 8'b1010_1111;//r
5'h13: seg_reg = 8'b1010_0001;//d
5'h14: seg_reg = 8'b1010_0011;//o
5'h15: seg_reg = 8'b1010_1011;//n
5'h16: seg_reg = 8'b1000_0110;//e
// 5'hf:seg_reg=8'b1111_1111;//²»ÏÔʾ
default:seg_reg = 8'b1111_1111;//None
endcase
//----------------------------------------------------------
assign out_dig = dig_ctrl;
assign out_seg = seg_reg;
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Tue Mar 28 02:26:33 2017
// Host : DESKTOP-B1QME94 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dds_compiler_0_stub.v
// Design : dds_compiler_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "dds_compiler_v6_0_13,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, s_axis_phase_tvalid,
s_axis_phase_tdata, m_axis_data_tvalid, m_axis_data_tdata)
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_phase_tvalid,s_axis_phase_tdata[23:0],m_axis_data_tvalid,m_axis_data_tdata[15:0]" */;
input aclk;
input s_axis_phase_tvalid;
input [23:0]s_axis_phase_tdata;
output m_axis_data_tvalid;
output [15:0]m_axis_data_tdata;
endmodule
|
#include <bits/stdc++.h> using namespace std; char ch, B[1 << 20], *S = B, *T = B; long long aa, bb; long long rd() { while (ch = (S == T && (T = (S = B) + fread(B, 1, 1 << 20, stdin), S == T) ? 0 : *S++), !(ch >= 0 && ch <= 9 ) && ch != - ) ; ch == - ? aa = bb = 0 : (aa = ch - 0 , bb = 1); while (ch = (S == T && (T = (S = B) + fread(B, 1, 1 << 20, stdin), S == T) ? 0 : *S++), (ch >= 0 && ch <= 9 )) aa = aa * 10 + ch - 0 ; return bb ? aa : -aa; } const long long MAXN = 1e5 + 10; long long n, k, ans, b[MAXN], tr[MAXN]; struct Node { long long pos, l, r, q, len; } a[MAXN]; bool cmp1(Node a, Node b) { return a.len > b.len; } bool cmp2(Node a, Node b) { return a.q < b.q; } inline void add(long long x, long long c) { while (x <= n) { tr[x] += c; x += (x & (-x)); } } long long sum(long long x) { long long ret = 0; while (x) { ret += tr[x]; x -= (x & (-x)); } return ret; } long long query(long long l, long long r) { return sum(r) - sum(l - 1); } inline void cdq(long long l, long long r) { if (l == r) return; long long mid = (l + r) >> 1; cdq(l, mid); cdq(mid + 1, r); long long L = l, R = l - 1; for (register long long i = mid + 1; i <= r; ++i) { while (L <= mid && a[i].q - a[L].q > k) { add(a[L].pos, -1); ++L; } while (R < mid && a[R + 1].q - a[i].q <= k) { ++R; add(a[R].pos, 1); } ans += query(a[i].l, a[i].r); } for (register long long i = L; i <= R; ++i) add(a[i].pos, -1); sort(a + l, a + r + 1, cmp2); } inline void work() { n = rd(); k = rd(); for (register long long i = 1; i <= n; ++i) { a[i].pos = rd(); a[i].len = rd(); a[i].q = rd(); b[i] = a[i].pos; } sort(b + 1, b + n + 1); long long cnt = unique(b + 1, b + n + 1) - b - 1; for (register long long i = 1; i <= n; ++i) { a[i].l = lower_bound(b + 1, b + cnt + 1, a[i].pos - a[i].len) - b; a[i].r = upper_bound(b + 1, b + cnt + 1, a[i].pos + a[i].len) - b - 1; a[i].pos = lower_bound(b + 1, b + cnt + 1, a[i].pos) - b; } sort(a + 1, a + n + 1, cmp1); cdq(1, n); printf( %lld n , ans); } signed main() { work(); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVER2_PP_SYMBOL_V
`define SKY130_FD_SC_LP__BUSDRIVER2_PP_SYMBOL_V
/**
* busdriver2: Bus driver (pmos devices).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__busdriver2 (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE_B,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVER2_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; vector<vector<int> > g; bitset<(int)1e6> us; bool isCyclic(int v, int p = -1) { us.set(v); for (int i = 0; i < g[v].size(); i++) { if (us.test(g[v][i]) && g[v][i] != p) return 0; if (us.test(g[v][i])) continue; bool cures = isCyclic(g[v][i], v); if (!cures) return 0; } return 1; } int main() { int n, m; cin >> n >> m; g.resize(n + 1); for (int i = 0; i < m; i++) { int v, to; cin >> v >> to; g[to].push_back(v); g[v].push_back(to); } int sum = 0; for (int i = 1; i <= n; i++) { if (us.test(i)) continue; sum += isCyclic(i); } cout << sum << endl; } |
//`timescale 1 ns / 100 ps
module dv_embox();
parameter DW = 32;
//Stimulus to drive
reg clk;
reg reset;
reg mi_access;
reg [19:0] mi_addr;
reg [31:0] mi_data_in;
reg mi_write;
reg [1:0] test_state;
reg go;
//Reset
initial
begin
$display($time, " << Starting the Simulation >>");
#0
clk = 1'b0; // at time 0
reset = 1'b1; // reset is active
mi_write = 1'b0;
mi_access = 1'b0;
mi_addr[19:0] = 20'hf0368;
mi_data_in[31:0] = 32'h0;
test_state[1:0] = 2'b00;
go = 1'b0;
#100
reset = 1'b0; // at time 100 release reset
#100
go = 1'b1;
#10000
$finish;
end
//Clock
always
#10 clk = ~clk;
//Pattern generator
//1.) Write in 8 transactions (split into low and high)
//2.) Read back 8 transactions (split into low and high)
always @ (negedge clk)
if(go)
begin
case(test_state[1:0])
2'b00://write
if(~done)
begin
mi_access <= 1'b1;
mi_write <= 1'b1;
mi_addr[19:0] <= mi_addr[19:0] ^ 20'hc;
mi_data_in[31:0] <= mi_data_in[31:0]+1'b1;
end
else
begin
test_state <= 2'b01;
mi_addr[19:0] <= 20'hf0368;
mi_data_in[31:0] <= 32'h0;
end
2'b01://read
if(~done)
begin
mi_write <= 1'b0;
mi_access <= 1'b1;
mi_addr[19:0] <= mi_addr[19:0] ^ 20'hc;
mi_data_in[31:0] <= mi_data_in[31:0]+1'b1;
end
else
begin
test_state <= 2'b10;
mi_write <= 1'b0;
mi_access <= 1'b0;
end
endcase // case (test_state[1:0])
end
wire done = (mi_data_in[19:0]==20'h8);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire embox_empty; // From embox of embox.v
wire embox_full; // From embox of embox.v
wire [DW-1:0] mi_data_out; // From embox of embox.v
// End of automatics
//DUT
embox embox(
/*AUTOINST*/
// Outputs
.mi_data_out (mi_data_out[DW-1:0]),
.embox_full (embox_full),
.embox_empty (embox_empty),
// Inputs
.reset (reset),
.clk (clk),
.mi_access (mi_access),
.mi_write (mi_write),
.mi_addr (mi_addr[19:0]),
.mi_data_in (mi_data_in[DW-1:0]));
//Waveform dump
initial
begin
$dumpfile("test.vcd");
$dumpvars(0, dv_embox);
end
endmodule // dv_embox
// Local Variables:
// verilog-library-directories:("." "../hdl" "../../memory/hdl ")
// End:
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2018 by Alex Solomatnikov.
// SPDX-License-Identifier: CC0-1.0
interface hex2ram_if
(
input bit trigger
);
string instance_path = $sformatf("%m");
string testfile = "";
bit has_testfile = |($value$plusargs("testfile=%s", testfile));
bit armed = 1'b1;
bit armed_trigger;
initial begin
$display("successfully bound hex2ram_if to %s", instance_path);
armed = has_testfile && 1'b1;
end
assign armed_trigger = armed && trigger;
always @(posedge armed_trigger) begin
$display("%m(%0t): saw deassertion of reset", $time);
end
endinterface : hex2ram_if
module t
(
clk
);
input clk /*verilator clocker*/;
bit reset;
wire success;
SimpleTestHarness testHarness
(
.clk(clk),
.reset(reset),
.io_success(success)
);
integer cyc = 0;
always @ (posedge clk) begin
cyc = cyc + 1;
if (cyc<10) begin
reset <= '0;
end
else if (cyc<20) begin
reset <= '1;
end
else if (cyc<30) begin
reset <= '0;
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
bind testharness_ext hex2ram_if i_hex2ram (.trigger(!t.reset));
module testharness_ext
(
input W0_clk,
input [24:0] W0_addr,
input W0_en,
input [127:0] W0_data,
input [0:0] W0_mask,
input R0_clk,
input [24:0] R0_addr,
input R0_en,
output [127:0] R0_data
);
reg [24:0] reg_R0_addr;
wire [127:0] R0_rdata_mask;
reg [127:0] ram [33554431:0];
wire [127:0] W0_wdata_mask;
always @(posedge R0_clk)
if (R0_en) reg_R0_addr <= R0_addr;
always @(posedge W0_clk)
if (W0_en) begin
if (W0_mask[0]) ram[W0_addr] <= W0_data ^ W0_wdata_mask;
end
assign R0_data = ram[reg_R0_addr] ^ R0_rdata_mask;;
assign R0_rdata_mask = 0;
assign W0_wdata_mask = 0;
endmodule
module SimpleTestHarness
(
input clk,
input reset,
output io_success);
wire [24:0] testharness_ext_R0_addr;
wire testharness_ext_R0_en;
wire testharness_ext_R0_clk;
wire [127:0] testharness_ext_R0_data;
wire [24:0] testharness_ext_W0_addr;
wire testharness_ext_W0_en;
wire testharness_ext_W0_clk;
wire [127:0] testharness_ext_W0_data;
wire [0:0] testharness_ext_W0_mask;
testharness_ext testharness_ext
(
.R0_addr(testharness_ext_R0_addr),
.R0_en(testharness_ext_R0_en),
.R0_clk(testharness_ext_R0_clk),
.R0_data(testharness_ext_R0_data),
.W0_addr(testharness_ext_W0_addr),
.W0_en(testharness_ext_W0_en),
.W0_clk(testharness_ext_W0_clk),
.W0_data(testharness_ext_W0_data),
.W0_mask(testharness_ext_W0_mask)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[10], flag[200]; int main() { int sum = 0; for (int i = 1; i <= 5; i++) { cin >> a[i]; sum += a[i]; flag[a[i]]++; } int ans = sum; for (int i = 1; i <= 5; i++) { if (flag[a[i]] > 1 && flag[a[i]] < 4) ans = min(ans, sum - flag[a[i]] * a[i]); else if (flag[a[i]] > 3) { ans = min(ans, sum - 3 * a[i]); } } cout << ans << n ; return 0; } |
#include <iostream> #include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--){ //int n; cin >> n; string s; cin >> s; string res = ; for (int i=0;i<s.size();i++){ if (i%2==0){ if (s[i]== a ){ res += b ; } else { res += a ; } } else { if (s[i]== z ){ res += y ; } else { res += z ; } } } cout << res << endl; } } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ff_jbi_sc0_1.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module ff_jbi_sc0_1(/*AUTOARG*/
// Outputs
jbi_sctag_req_d1, scbuf_jbi_data_d1, jbi_scbuf_ecc_d1,
jbi_sctag_req_vld_d1, scbuf_jbi_ctag_vld_d1, scbuf_jbi_ue_err_d1,
sctag_jbi_iq_dequeue_d1, sctag_jbi_wib_dequeue_d1,
sctag_jbi_por_req_d1, so,
// Inputs
jbi_sctag_req, scbuf_jbi_data, jbi_scbuf_ecc, jbi_sctag_req_vld,
scbuf_jbi_ctag_vld, scbuf_jbi_ue_err, sctag_jbi_iq_dequeue,
sctag_jbi_wib_dequeue, sctag_jbi_por_req, rclk, si, se
);
output [31:0] jbi_sctag_req_d1;
output [31:0] scbuf_jbi_data_d1;
output [6:0] jbi_scbuf_ecc_d1;
output jbi_sctag_req_vld_d1;
output scbuf_jbi_ctag_vld_d1;
output scbuf_jbi_ue_err_d1;
output sctag_jbi_iq_dequeue_d1;
output sctag_jbi_wib_dequeue_d1;
output sctag_jbi_por_req_d1;
input [31:0] jbi_sctag_req;
input [31:0] scbuf_jbi_data;
input [6:0] jbi_scbuf_ecc;
input jbi_sctag_req_vld;
input scbuf_jbi_ctag_vld;
input scbuf_jbi_ue_err;
input sctag_jbi_iq_dequeue;
input sctag_jbi_wib_dequeue;
input sctag_jbi_por_req;
input rclk;
input si, se;
output so;
wire int_scanout;
// connect scanout of the last flop to int_scanout.
// The output of the lockup latch is
// the scanout of this dbb (so)
bw_u1_scanlg_2x so_lockup(.so(so), .sd(int_scanout), .ck(rclk), .se(se));
dff_s #(32) ff_flop_row0 (.q(jbi_sctag_req_d1[31:0]),
.din(jbi_sctag_req[31:0]),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(32) ff_flop_row1 (.q(scbuf_jbi_data_d1[31:0]),
.din(scbuf_jbi_data[31:0]),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(13) ff_flop_row2 (.q({ jbi_scbuf_ecc_d1[6:0],
jbi_sctag_req_vld_d1,
scbuf_jbi_ctag_vld_d1,
scbuf_jbi_ue_err_d1,
sctag_jbi_iq_dequeue_d1,
sctag_jbi_wib_dequeue_d1,
sctag_jbi_por_req_d1}),
.din({ jbi_scbuf_ecc[6:0],
jbi_sctag_req_vld,
scbuf_jbi_ctag_vld,
scbuf_jbi_ue_err,
sctag_jbi_iq_dequeue,
sctag_jbi_wib_dequeue,
sctag_jbi_por_req}),
.clk(rclk), .se(1'b0), .si(), .so() );
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYGATE4SD2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__DLYGATE4SD2_FUNCTIONAL_PP_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__dlygate4sd2 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYGATE4SD2_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int N, M, Dx, Dy; cin >> N >> M >> Dx >> Dy; vector<pair<int, int>> way(N); way[0].first = way[0].second = 0; for (int i = 1; i < N; ++i) { way[i].first = (way[i - 1].first + Dx) % N; way[i].second = (way[i - 1].second + Dy) % N; } sort(way.begin(), way.end()); vector<pair<int, int>> trees(M); for (auto& p : trees) { cin >> p.first >> p.second; } sort(trees.begin(), trees.end()); map<int, int> lower, upper; for (const auto& tree : trees) { int x = tree.first; int y = tree.second; if (y == way[x].second) { lower[0]++; upper[0]++; } else if (y < way[x].second) { upper[way[x].second - y]++; lower[y + N - way[x].second]++; } else { lower[y - way[x].second]++; upper[N - y + way[x].second]++; } } auto it1 = max_element(lower.begin(), lower.end(), [](const pair<int, int>& lhs, const pair<int, int>& rhs) { return lhs.second < rhs.second; }); auto it2 = max_element(upper.begin(), upper.end(), [](const pair<int, int>& lhs, const pair<int, int>& rhs) { return lhs.second < rhs.second; }); if (it2->second >= it1->second) { cout << 0 << << (2 * N - it2->first) % N << n ; } else { cout << 0 << << it1->first % N << n ; } return 0; } |
#include <iostream> #include <vector> #include <set> #include <unordered_set> #include <map> #include <unordered_map> #include <algorithm> #include <numeric> #include <queue> #include <iomanip> #include <numeric> #include <cmath> using namespace std; int main() { int t; cin >> t; for (int tt = 0; tt < t; tt++) { int n, m; cin >> n >> m; vector<int> va(n, 0), vb(n, 0); unordered_map<int, vector<int>> tofix; unordered_map<int, int> fixed; for (int i = 0; i < n; i++) { cin >> va[i]; } for (int i = 0; i < n; i++) { cin >> vb[i]; if (va[i] == vb[i]) { fixed[va[i]] = i; } else { tofix[vb[i]].push_back(i); } } vector<int> res(m, 0); vector<pair<int, int>> redundant; for (int i = 0; i < m; i++) { int x; cin >> x; if (tofix.count(x) > 0 and tofix[x].size() > 0) { res[i] = tofix[x].back(); fixed[x] = tofix[x].back(); tofix[x].pop_back(); if (tofix[x].size() == 0) { tofix.erase(x); } if (redundant.size() > 0) { for (auto p : redundant) { res[p.first] = fixed[x]; } redundant.clear(); } } else { if (fixed.count(x) > 0) { if (redundant.size() > 0) { for (auto p : redundant) { res[p.first] = fixed[x]; } redundant.clear(); res[i] = fixed[x]; } else { res[i] = fixed[x]; } } else { redundant.emplace_back(i, x); } } } if (redundant.empty() and tofix.size() == 0) { cout << YES << endl; for (auto r : res) { cout << r + 1 << ; } cout << endl; } else { cout << NO << endl; } } } |
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; const int maxn = 200000 + 10; int n, m, k, nv; vector<pair<int, pair<int, int> > > edge; vector<pair<int, int> > e[maxn]; int f[maxn]; bool vis[maxn]; long long dis[maxn]; vector<long long> q; void print(int a[], int n, int st = 0) { for (int i = 0; i < n; i++) { if (i != 0) printf( ); printf( %d , a[i + st]); } printf( n ); } void init() { scanf( %d%d%d , &n, &m, &k); for (int i = 0; i < m; i++) { int u, v, w; scanf( %d%d%d , &u, &v, &w); edge.push_back(make_pair(w, make_pair(min(u, v), max(u, v)))); } } void doit() { sort(edge.begin(), edge.end()); memset(f, -1, sizeof(f)); nv = 0; for (int i = 0; i < min(k, m); i++) { int u = edge[i].second.first, v = edge[i].second.second, w = edge[i].first; if (f[u] == -1) f[u] = nv++; u = f[u]; if (f[v] == -1) f[v] = nv++; v = f[v]; e[u].push_back(make_pair(v, w)); e[v].push_back(make_pair(u, w)); } for (int st = 0; st < nv; st++) { for (int i = 0; i < nv; i++) vis[i] = false; vis[st] = true; for (int i = 0; i < nv; i++) dis[i] = -1; dis[st] = 0; int cur = st; while (1) { for (int i = 0; i < e[cur].size(); i++) { int v = e[cur][i].first, w = e[cur][i].second; if (!vis[v] && (dis[v] == -1 || dis[v] > dis[cur] + w)) { dis[v] = dis[cur] + w; } } long long mn = -1; for (int i = 0; i < nv; i++) { if (!vis[i] && (dis[i] != -1 && (mn == -1 || dis[i] < mn))) { mn = dis[i]; cur = i; } } if (vis[cur]) break; vis[cur] = true; } for (int i = st + 1; i < nv; i++) { if (vis[i]) q.push_back(dis[i]); } } sort(q.begin(), q.end()); printf( %lld n , q[k - 1]); } int main() { init(); doit(); return 0; } |
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// Reduced Normalization module
//
// This module performs realignment of data such that the most significant bit is 1 for any number with exponent >= 1,
// and zero otherwise. This version of the module is specifically designed for the multiplier with no support for denormalized
// numbers. As such it is far smaller.
//
module acl_fp_custom_reduced_normalize_mult_double(
clock, resetn,
mantissa, exponent, sign,
// Used in HIGH_CAPACITY = 1 mode
stall_in, valid_in, stall_out, valid_out,
// Used in HIGH_CAPACITY = 0 mode
enable,
mantissa_out, exponent_out, sign_out);
parameter HIGH_CAPACITY = 1;
parameter FINITE_MATH_ONLY = 1;
parameter REMOVE_STICKY = 1;
input clock, resetn;
input stall_in, valid_in;
output stall_out, valid_out;
input enable;
// Data in
input [56:0] mantissa;
input [11:0] exponent; // Exponent with MSB set to 1 is an exception.
input sign;
// Data output
output [55:0] mantissa_out; // When mantissa_out[54] = 1 and exponent_out[11] == 1 then the number is NaN.
output [11:0] exponent_out; // Exponent with MSB set to 1 is an exception.
output sign_out;
// Stall/valid and enable signals on per-stage basis.
reg c1_valid;
wire c1_stall;
wire c1_enable;
// Cycle 1 - There is not much to do for a multiplier that does not support denormalized numbers.
// At the most, shift right by 1.
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [55:0] c1_mantissa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [11:0] c1_exponent;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c1_sign;
assign c1_enable = (HIGH_CAPACITY == 1) ? (~c1_valid | ~c1_stall) : enable;
assign stall_out = c1_valid & c1_stall;
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c1_mantissa <= 56'dx;
c1_exponent <= 12'dx;
c1_sign <= 1'bx;
c1_valid <= 1'b0;
end
else if (c1_enable)
begin
c1_valid <= valid_in;
c1_sign <= sign;
// Handle mantissa
if (mantissa[56])
begin
if ((exponent == 12'h7fe) && (FINITE_MATH_ONLY == 0))
begin
c1_mantissa <= 56'h40000000000000;
end
else
begin
if (REMOVE_STICKY == 1)
begin
c1_mantissa <= mantissa[56:1];
end
else
begin
c1_mantissa <= {mantissa[56:2], |mantissa[1:0]};
end
end
end
else
begin
c1_mantissa <= mantissa[55:0];
end
// handle exponent
if (FINITE_MATH_ONLY == 0)
begin
if (mantissa[56])
begin
if (exponent == 12'h7fe)
begin
c1_exponent <= 12'hfff;
end
else
begin
c1_exponent <= exponent + 1'b1;
end
end
else
begin
if (~mantissa[55] & ~exponent[11])
c1_exponent <= 12'd0;
else
c1_exponent <= exponent;
end
end
else
begin
c1_exponent <= (exponent & {12{mantissa[56] | mantissa[55]}}) + {1'b0, mantissa[56]};
end
end
end
assign mantissa_out = c1_mantissa;
assign exponent_out = c1_exponent;
assign sign_out = c1_sign;
assign valid_out = c1_valid;
assign c1_stall = stall_in;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; int values[400][400]; int mem[400][400][2]; void read() { cin >> n; for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { cin >> values[i][j]; mem[i][j][0] = 0; mem[i][j][1] = 0; } } } void add(int x1, int x2, int c, int v) { if (x1 > x2) return; int lo = max(0, c - n + 1), hi = min(n - 1, c); if (x1 < lo || x2 > hi) return; int y1 = c - x1, y2 = c - x2; v += values[x1][y1] + values[x2][y2]; if (x1 == x2) v -= values[x1][y1]; if (v > mem[x1][x2][c & 1]) mem[x1][x2][c & 1] = v; } void solve() { mem[0][0][0] = values[0][0]; for (int c = 0; c <= 2 * n - 3; ++c) { for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { mem[i][j][(c + 1) & 1] = -1000 * 400 * 2; } } int lo = max(0, c - n + 1), hi = min(n - 1, c); for (int x1 = lo; x1 <= hi; ++x1) { for (int x2 = x1; x2 <= hi; ++x2) { add(x1, x2, c + 1, mem[x1][x2][c & 1]); add(x1 + 1, x2, c + 1, mem[x1][x2][c & 1]); add(x1, x2 + 1, c + 1, mem[x1][x2][c & 1]); add(x1 + 1, x2 + 1, c + 1, mem[x1][x2][c & 1]); } } } } int main() { read(); solve(); cout << mem[n - 1][n - 1][0] << endl; return 0; } |
// (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:hls:pointer_basic:1.0
// IP Revision:
(* X_CORE_INFO = "pointer_basic,Vivado 2018.2" *)
(* CHECK_LICENSE_TYPE = "design_1_pointer_basic_0_1,pointer_basic,{}" *)
(* CORE_GENERATION_INFO = "design_1_pointer_basic_0_1,pointer_basic,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=hls,x_ipName=pointer_basic,x_ipVersion=1.0,x_ipCoreRevision=,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_S_AXI_POINTER_BASIC_IO_ADDR_WIDTH=5,C_S_AXI_POINTER_BASIC_IO_DATA_WIDTH=32}" *)
(* IP_DEFINITION_SOURCE = "HLS" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_pointer_basic_0_1 (
s_axi_pointer_basic_io_AWADDR,
s_axi_pointer_basic_io_AWVALID,
s_axi_pointer_basic_io_AWREADY,
s_axi_pointer_basic_io_WDATA,
s_axi_pointer_basic_io_WSTRB,
s_axi_pointer_basic_io_WVALID,
s_axi_pointer_basic_io_WREADY,
s_axi_pointer_basic_io_BRESP,
s_axi_pointer_basic_io_BVALID,
s_axi_pointer_basic_io_BREADY,
s_axi_pointer_basic_io_ARADDR,
s_axi_pointer_basic_io_ARVALID,
s_axi_pointer_basic_io_ARREADY,
s_axi_pointer_basic_io_RDATA,
s_axi_pointer_basic_io_RRESP,
s_axi_pointer_basic_io_RVALID,
s_axi_pointer_basic_io_RREADY,
ap_clk,
ap_rst_n,
interrupt
);
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io AWADDR" *)
input wire [4 : 0] s_axi_pointer_basic_io_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io AWVALID" *)
input wire s_axi_pointer_basic_io_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io AWREADY" *)
output wire s_axi_pointer_basic_io_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io WDATA" *)
input wire [31 : 0] s_axi_pointer_basic_io_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io WSTRB" *)
input wire [3 : 0] s_axi_pointer_basic_io_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io WVALID" *)
input wire s_axi_pointer_basic_io_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io WREADY" *)
output wire s_axi_pointer_basic_io_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io BRESP" *)
output wire [1 : 0] s_axi_pointer_basic_io_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io BVALID" *)
output wire s_axi_pointer_basic_io_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io BREADY" *)
input wire s_axi_pointer_basic_io_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io ARADDR" *)
input wire [4 : 0] s_axi_pointer_basic_io_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io ARVALID" *)
input wire s_axi_pointer_basic_io_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io ARREADY" *)
output wire s_axi_pointer_basic_io_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io RDATA" *)
output wire [31 : 0] s_axi_pointer_basic_io_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io RRESP" *)
output wire [1 : 0] s_axi_pointer_basic_io_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io RVALID" *)
output wire s_axi_pointer_basic_io_RVALID;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_pointer_basic_io, ADDR_WIDTH 5, DATA_WIDTH 32, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 50\
000000, ID_WIDTH 0, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_2_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_pointer_basic_io RREADY" *)
input wire s_axi_pointer_basic_io_RREADY;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ap_clk, ASSOCIATED_BUSIF s_axi_pointer_basic_io, ASSOCIATED_RESET ap_rst_n, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 50000000, PHASE 0.000, CLK\
_DOMAIN design_1_processing_system7_0_2_FCLK_CLK0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ap_clk CLK" *)
input wire ap_clk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ap_rst_n, POLARITY ACTIVE_LOW, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {RST {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 ap_rst_n RST" *)
input wire ap_rst_n;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME interrupt, SENSITIVITY LEVEL_HIGH, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {INTERRUPT {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, PortWidth 1" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT" *)
output wire interrupt;
pointer_basic #(
.C_S_AXI_POINTER_BASIC_IO_ADDR_WIDTH(5),
.C_S_AXI_POINTER_BASIC_IO_DATA_WIDTH(32)
) inst (
.s_axi_pointer_basic_io_AWADDR(s_axi_pointer_basic_io_AWADDR),
.s_axi_pointer_basic_io_AWVALID(s_axi_pointer_basic_io_AWVALID),
.s_axi_pointer_basic_io_AWREADY(s_axi_pointer_basic_io_AWREADY),
.s_axi_pointer_basic_io_WDATA(s_axi_pointer_basic_io_WDATA),
.s_axi_pointer_basic_io_WSTRB(s_axi_pointer_basic_io_WSTRB),
.s_axi_pointer_basic_io_WVALID(s_axi_pointer_basic_io_WVALID),
.s_axi_pointer_basic_io_WREADY(s_axi_pointer_basic_io_WREADY),
.s_axi_pointer_basic_io_BRESP(s_axi_pointer_basic_io_BRESP),
.s_axi_pointer_basic_io_BVALID(s_axi_pointer_basic_io_BVALID),
.s_axi_pointer_basic_io_BREADY(s_axi_pointer_basic_io_BREADY),
.s_axi_pointer_basic_io_ARADDR(s_axi_pointer_basic_io_ARADDR),
.s_axi_pointer_basic_io_ARVALID(s_axi_pointer_basic_io_ARVALID),
.s_axi_pointer_basic_io_ARREADY(s_axi_pointer_basic_io_ARREADY),
.s_axi_pointer_basic_io_RDATA(s_axi_pointer_basic_io_RDATA),
.s_axi_pointer_basic_io_RRESP(s_axi_pointer_basic_io_RRESP),
.s_axi_pointer_basic_io_RVALID(s_axi_pointer_basic_io_RVALID),
.s_axi_pointer_basic_io_RREADY(s_axi_pointer_basic_io_RREADY),
.ap_clk(ap_clk),
.ap_rst_n(ap_rst_n),
.interrupt(interrupt)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 3e5 + 10; int n, q, a, b, blo, arr[N]; struct node { int a, b, id; } qq[N]; long long ans[N], dp[N]; bool cmp(node a, node b) { if (a.b != b.b) return a.b > b.b; return a.a < b.a; } int main() { scanf( %d , &n); blo = sqrt(n); for (int i = 1; i <= n; i++) scanf( %d , &arr[i]); scanf( %d , &q); for (int i = 1; i <= q; i++) { scanf( %d%d , &qq[i].a, &qq[i].b); qq[i].id = i; } sort(qq + 1, qq + q + 1, cmp); int n_b = -1; for (int i = 1; i <= q; i++) { node nn = qq[i]; if (nn.b >= blo) { for (int i = nn.a; i <= n; i += nn.b) ans[nn.id] += arr[i]; } else { if (nn.b != n_b || dp[nn.a] == 0) { for (int j = n; j >= 1; j--) { if (j + nn.b > n) dp[j] = arr[j]; else dp[j] = dp[j + nn.b] + arr[j]; } n_b = nn.b; } ans[nn.id] = dp[nn.a]; } } for (int i = 1; i <= q; i++) { printf( %I64d n , ans[i]); } return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T> void dbg(T a) {} template <typename T, typename... Arg> void dbg(T a, Arg... arg) {} const int maxn = (1e6) + 7; const int inf = (1e9) + 7; const long long LLinf = (1e18) + 7; const long double eps = 1e-9; const long long mod = 1e9 + 7; int ile(vector<int> V) { int res = 0; while (((int)(V).size()) && V.back() == 0) { V.pop_back(); res++; } if (((int)(V).size()) == 0) return 10000; return res; } int rob(vector<int> V, int a, int b) { int cnt = 0; for (int i = 0; i < ((int)(V).size()); i++) if (V[i] == a) { for (int j = i - 1; j >= 0; j--) { swap(V[j], V[j + 1]); cnt++; } break; } for (int i = 1; i < ((int)(V).size()); i++) if (V[i] == b) { for (int j = i - 1; j > 0; j--) { swap(V[j], V[j + 1]); cnt++; } break; } if (V[0] == a && V[1] == b) return cnt + ile(V); else return 1000; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n; cin >> n; vector<int> V; while (n > 0) { V.push_back(n % 10); n /= 10LL; } int res = 1000; res = min(res, rob(V, 0, 0)); res = min(res, rob(V, 5, 2)); res = min(res, rob(V, 0, 5)); res = min(res, rob(V, 5, 7)); if (res < 100) cout << res; else cout << -1 ; return 0; } |
#include <bits/stdc++.h> using namespace std; void fact(int n) { const int N = 1e5; vector<int> arr(N, 0); int q = 2; arr[0] = 1; int len = 1; int x = 0; int carry = 0; while (q <= n) { x = 0; carry = 0; while (x < len) { arr[x] = arr[x] * q + carry; carry = arr[x] / 10; arr[x] = arr[x] % 10; x++; } while (carry) { arr[len] = carry % 10; carry = carry / 10; len++; } q++; } len--; for (int i = len; i >= 0; i--) { cout << arr[i]; } return; } long long int binary_exp(long long int x, long long int n) { if (n == 0) { return 1; } else if (n == 1) { return x % 1000000007; } else { long long int temp = binary_exp(x, n / 2); temp = (temp * temp) % 1000000007; if (n % 2 == 0) { return temp; } else { return ((x % 1000000007) * temp) % 1000000007; } } } int main() { int k, r; cin >> k >> r; int i = 1; while (i * k % 10 != r and i * k % 10 != 0) { i++; } cout << i; return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/05/24 22:02:40
// Design Name:
// Module Name: Register_with_synch_reset_load_behavior_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Register_with_synch_reset_load_behavior_tb(
);
reg [3:0] D;
reg Clk, reset, load;
wire [3:0] Q;
Register_with_synch_reset_load_behavior DUT (.D(D), .Clk(Clk), .reset(reset), .load(load), .Q(Q));
initial begin
#300 $finish;
end
initial begin
D = 4'b0000; Clk = 0; reset = 0; load = 0;
#10 Clk = 1;
#10 Clk = 0; D = 4'b0101;
#10 Clk = 1;
#10 Clk = 0;
#10 Clk = 1;
#10 Clk = 0; load = 1;
#10 Clk = 1;
#10 Clk = 0; D = 4'b1001; load = 0;
#10 Clk = 1;
#10 Clk = 0; // 100ns
#10 Clk = 1;
#10 Clk = 0; load = 1;
#10 Clk = 1;
#10 Clk = 0; load = 0;
#10 Clk = 1;
#5 reset = 1;
#5 Clk = 0;
#10 Clk = 1;
#10 Clk = 0;
#10 Clk = 1;
#5 load = 1;
#5 Clk = 0; // 200ns
#10 Clk = 1;
#5 load = 0;
#5 Clk = 0;
#10 Clk = 1;
#10 Clk = 0; reset = 0;
#10 Clk = 1;
#10 Clk = 0;
#10 Clk = 1;
#10 Clk = 0; load = 1;
#10 Clk = 1;
#10 Clk = 0; load = 0;// 300ns
end
endmodule
|
#include <bits/stdc++.h> using namespace std; string s, t; int l[200005], r[200005], last[200005]; int main() { cin >> s >> t; memset(last, -1, sizeof(last)); int j = 0, slen = s.size(), tlen = t.size(); for (int i = 0; i < slen; i++) { l[i] = last[s[i] - a ]; if (j < tlen && s[i] == t[j]) { l[i] = j; j++; } last[s[i] - a ] = l[i]; } memset(last, -1, sizeof(last)); j = tlen - 1; for (int i = slen - 1; i >= 0; i--) { r[i] = last[s[i] - a ]; if (j >= 0 && s[i] == t[j]) { r[i] = j; j--; } last[s[i] - a ] = r[i]; } bool ok = true; for (int i = 0; i < slen; i++) { if (l[i] == -1 || r[i] == -1 || l[i] < r[i]) { ok = false; break; } } if (ok) cout << yes << endl; else cout << no << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int last[444444], pr[444444], p[444444], pred[444444]; string s[444444], t; int ans, n, len; void go(int v, int K) { int j = last[v]; while (j > 0) { int k = K, sz = s[j].length(); for (int q = 0; q < sz; q++) { while (k > 0 && s[j][q] != t[k]) k = pr[k]; if (s[j][q] == t[k]) k++; if (k == len) ans++; } go(j, k); j = pred[j]; } } int main() { cin >> n; for (int i = 1; i <= n; i++) last[i] = 0; for (int i = 2; i <= n; i++) { cin >> p[i] >> s[i]; pred[i] = last[p[i]]; last[p[i]] = i; } cin >> t; len = t.length(); t = t + ; pr[1] = 0; int k = 0; for (int i = 2; i <= len; i++) { while (k > 0 && t[i - 1] != t[k]) k = pr[k]; if (t[i - 1] == t[k]) k++; pr[i] = k; } ans = 0; go(1, 0); printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int T, x; char str[100005], ans[100005]; char usd[100005]; int main() { scanf( %d , &T); while (T--) { scanf( %s , str + 1); scanf( %d , &x); int n = strlen(str + 1); for (int i = 1; i <= n; ++i) { if (str[i] == 0 ) { if (i + x <= n) ans[i + x] = 0 ; if (i - x >= 1) ans[i - x] = 0 ; } } for (int i = 1; i <= n; ++i) if (!ans[i]) ans[i] = 1 ; for (int i = 1; i <= n; ++i) { if (i - x >= 1 && ans[i - x] == 1 ) usd[i] = 1 ; else if (i + x <= n && ans[i + x] == 1 ) usd[i] = 1 ; else usd[i] = 0 ; } bool flag = true; for (int i = 1; i <= n; ++i) if (usd[i] != str[i]) { flag = false; break; } if (!flag) printf( -1 n ); else printf( %s n , ans + 1); for (int i = 1; i <= n; ++i) ans[i] = 0; } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long inf = 1e10; void solve() { long long n, m, k; cin >> n >> m >> k; long long moves = (n + m - 2) + (n * m) - 1; for (long long i = 0; i < m + n; i++) { cin >> k; } cout << moves << n ; for (long long i = 0; i < n - 1; i++) { cout << U ; } for (long long i = 0; i < m - 1; i++) { cout << L ; } string r(m - 1, R ); string l(m - 1, L ); for (long long i = 0; i < n; i++) { if (i % 2) { cout << l; } else cout << r; if (i != n - 1) cout << D ; } cout << n ; } int32_t main() { std::ios::sync_with_stdio(false); std::cin.tie(nullptr); long long t = 1; while (t--) solve(); return 0; } |
// phase_detector_filter.v
module phase_detector_filter
(
input clk,
input reset,
input update,
input [3:0]phase_in, // 2*pi phase, half steps
output [3:0]phase_out // 4*pi phase, full steps
);
localparam N = 10; // must be >= 5
// --- phase adder register
wire [(N-1):0]ph_cnt;
// 4*pi phase
assign phase_out = ph_cnt[(N-1):(N-4)];
// phase difference
wire [3:0]diff = ph_cnt[(N-2):(N-5)] - phase_in;
wire cnt_ena = update && (diff != 4'd0);
wire up = diff[3];
// --- phase counter: cnt_ena, up -> ph_cnt ------------------------------
wire [(N-2):0]ph_cnt_L; // lower (N-1) bits
reg ph_cnt_H; // upper most bit
wire carry;
assign ph_cnt = {ph_cnt_H, ph_cnt_L};
// special handling of upper most bit
always @(posedge clk or posedge reset)
begin
if (reset) ph_cnt_H <= 1'd1;
else if (cnt_ena && carry) ph_cnt_H <= up;
end
// counter for lower bits
lpm_counter phase_counter
(
.aclr (reset),
.clk_en (cnt_ena),
.clock (clk),
.updown (up),
.cout (carry),
.q (ph_cnt_L),
.aload (1'b0),
.aset (1'b0),
.cin (1'b1),
.cnt_en (1'b1),
.data ({(N-1){1'b0}}),
.eq (),
.sclr (1'b0),
.sload (1'b0),
.sset (1'b0)
);
defparam
phase_counter.lpm_direction = "UNUSED",
phase_counter.lpm_port_updown = "PORT_USED",
phase_counter.lpm_type = "LPM_COUNTER",
phase_counter.lpm_width = N-1;
endmodule
|
// $Id: aeMB_regf.v,v 1.3 2007/11/10 16:39:38 sybreon Exp $
//
// AEMB REGISTER FILE
//
// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <>
//
// This file is part of AEMB.
//
// AEMB is free software: you can redistribute it and/or modify it
// under the terms of the GNU Lesser General Public License as
// published by the Free Software Foundation, either version 3 of the
// License, or (at your option) any later version.
//
// AEMB is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
// Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
//
// $Log: aeMB_regf.v,v $
// Revision 1.3 2007/11/10 16:39:38 sybreon
// Upgraded license to LGPLv3.
// Significant performance optimisations.
//
// Revision 1.2 2007/11/09 20:51:52 sybreon
// Added GET/PUT support through a FSL bus.
//
// Revision 1.1 2007/11/02 03:25:41 sybreon
// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
// Fixed various minor data hazard bugs.
// Code compatible with -O0/1/2/3/s generated code.
//
module aeMB_regf (/*AUTOARG*/
// Outputs
rREGA, rREGB, rDWBDI, dwb_dat_o, fsl_dat_o,
// Inputs
rOPC, rRA, rRB, rRW, rRD, rMXDST, rPCLNK, rRESULT, rDWBSEL, rBRA,
rDLY, dwb_dat_i, fsl_dat_i, gclk, grst, gena
);
// INTERNAL
output [31:0] rREGA, rREGB;
output [31:0] rDWBDI;
input [5:0] rOPC;
input [4:0] rRA, rRB, rRW, rRD;
input [1:0] rMXDST;
input [31:2] rPCLNK;
input [31:0] rRESULT;
input [3:0] rDWBSEL;
input rBRA, rDLY;
// DATA WISHBONE
output [31:0] dwb_dat_o;
input [31:0] dwb_dat_i;
// FSL WISHBONE
output [31:0] fsl_dat_o;
input [31:0] fsl_dat_i;
// SYSTEM
input gclk, grst, gena;
// --- LOAD SIZER ----------------------------------------------
// Moves the data bytes around depending on the size of the
// operation.
wire [31:0] wDWBDI = dwb_dat_i; // FIXME: Endian
wire [31:0] wFSLDI = fsl_dat_i; // FIXME: Endian
reg [31:0] rDWBDI;
reg [1:0] rSIZ;
always @(/*AUTOSENSE*/rDWBSEL or wDWBDI or wFSLDI) begin
/* 51.2
case (rSIZ)
// FSL
2'o3: rDWBDI <= wFSLDI;
// 32'bit
2'o2: rDWBDI <= wDWBDI;
// 16'bit
2'o1: case (rRESULT[1])
1'b0: rDWBDI <= {16'd0, wDWBDI[31:16]};
1'b1: rDWBDI <= {16'd0, wDWBDI[15:0]};
endcase // case (rRESULT[1])
// 8'bit
2'o0: case (rRESULT[1:0])
2'o0: rDWBDI <= {24'd0, wDWBDI[31:24]};
2'o1: rDWBDI <= {24'd0, wDWBDI[23:16]};
2'o2: rDWBDI <= {24'd0, wDWBDI[15:8]};
2'o3: rDWBDI <= {24'd0, wDWBDI[7:0]};
endcase // case (rRESULT[1:0])
endcase // case (rSIZ)
*/
/* 50.6
case ({rSIZ, rRESULT[1:0]})
// FSL
4'hC, 4'hD, 4'hE, 4'hF: rDWBDI <= wFSLDI;
// 32'bit
4'h8: rDWBDI <= wDWBDI;
// 16'bit
4'h4: rDWBDI <= {16'd0, wDWBDI[31:16]};
4'h6: rDWBDI <= {16'd0, wDWBDI[15:0]};
// 8'bit
4'h0: rDWBDI <= {24'd0, wDWBDI[31:24]};
4'h1: rDWBDI <= {24'd0, wDWBDI[23:16]};
4'h2: rDWBDI <= {24'd0, wDWBDI[15:8]};
4'h3: rDWBDI <= {24'd0, wDWBDI[7:0]};
default: rDWBDI <= 32'hX;
endcase // case (rSIZ)
*/
// 52.0
case (rDWBSEL)
// 8'bit
4'h8: rDWBDI <= {24'd0, wDWBDI[31:24]};
4'h4: rDWBDI <= {24'd0, wDWBDI[23:16]};
4'h2: rDWBDI <= {24'd0, wDWBDI[15:8]};
4'h1: rDWBDI <= {24'd0, wDWBDI[7:0]};
// 16'bit
4'hC: rDWBDI <= {16'd0, wDWBDI[31:16]};
4'h3: rDWBDI <= {16'd0, wDWBDI[15:0]};
// 32'bit
4'hF: rDWBDI <= wDWBDI;
// FSL
4'h0: rDWBDI <= wFSLDI;
// Undefined
default: rDWBDI <= 32'hX;
endcase
end
always @(posedge gclk)
if (grst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rSIZ <= 2'h0;
// End of automatics
end else if (gena) begin
rSIZ <= rOPC[1:0];
end
// --- GENERAL PURPOSE REGISTERS (R0-R31) -----------------------
// LUT RAM implementation is smaller and faster. R0 gets written
// during reset with 0x00 and doesn't change after.
//synthesis attribute ram_style of mARAM is distributed
reg [31:0] mARAM[0:31];
//synthesis attribute ram_style of mBRAM is distributed
reg [31:0] mBRAM[0:31];
//synthesis attribute ram_style of mDRAM is distributed
reg [31:0] mDRAM[0:31];
wire [31:0] rREGW = mDRAM[rRW];
wire [31:0] rREGD = mDRAM[rRD];
assign rREGA = mARAM[rRA];
assign rREGB = mBRAM[rRB];
wire fRDWE = |rRW;
reg [31:0] xWDAT;
always @(/*AUTOSENSE*/rDWBDI or rMXDST or rPCLNK or rREGW
or rRESULT)
case (rMXDST)
2'o2: xWDAT <= rDWBDI;
2'o1: xWDAT <= {rPCLNK, 2'o0};
2'o0: xWDAT <= rRESULT;
2'o3: xWDAT <= rREGW; // No change
endcase // case (rMXDST)
always @(posedge gclk)
if (grst | fRDWE) begin
mARAM[rRW] <= xWDAT;
mBRAM[rRW] <= xWDAT;
mDRAM[rRW] <= xWDAT;
end
// --- STORE SIZER ---------------------------------------------
// Replicates the data bytes across depending on the size of the
// operation.
reg [31:0] rDWBDO, xDWBDO;
wire [31:0] xFSL;
wire fFFWD_M = (rRA == rRW) & (rMXDST == 2'o2) & fRDWE;
wire fFFWD_R = (rRA == rRW) & (rMXDST == 2'o0) & fRDWE;
assign fsl_dat_o = rDWBDO;
assign xFSL = (fFFWD_M) ? rDWBDI :
(fFFWD_R) ? rRESULT :
rREGA;
wire [31:0] xDST;
wire fDFWD_M = (rRW == rRD) & (rMXDST == 2'o2) & fRDWE;
wire fDFWD_R = (rRW == rRD) & (rMXDST == 2'o0) & fRDWE;
assign dwb_dat_o = rDWBDO;
assign xDST = (fDFWD_M) ? rDWBDI :
(fDFWD_R) ? rRESULT :
rREGD;
always @(/*AUTOSENSE*/rOPC or xDST or xFSL)
case (rOPC[1:0])
// 8'bit
2'h0: xDWBDO <= {(4){xDST[7:0]}};
// 16'bit
2'h1: xDWBDO <= {(2){xDST[15:0]}};
// 32'bit
2'h2: xDWBDO <= xDST;
// FSL
2'h3: xDWBDO <= xFSL;
//default: xDWBDO <= 32'hX;
endcase // case (rOPC[1:0])
always @(posedge gclk)
if (grst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rDWBDO <= 32'h0;
// End of automatics
end else if (gena) begin
rDWBDO <= #1 xDWBDO;
end
// --- SIMULATION ONLY ------------------------------------------
// Randomise memory to simulate real-world memory
// synopsys translate_off
integer i;
initial begin
for (i=0; i<32; i=i+1) begin
mARAM[i] <= $random;
mBRAM[i] <= $random;
mDRAM[i] <= $random;
end
end
// synopsys translate_on
endmodule // aeMB_regf
|
#include <bits/stdc++.h> #pragma GCC optimize(2) #pragma GCC optimize(3, Ofast , inline ) using namespace std; const long long mod = 1e9 + 7; const long long M = 1e8 + 5; const long long N = 6e5 + 5; char s[N]; bool check() { map<char, long long> mp; long long len = strlen(s + 1); long long l = 1; while (s[l] == a ) l++; if (l == 1) return 0; long long pos = l; while (s[l] == b ) l++; if (l == pos) return 0; while (s[l] == c ) l++; if (l != len + 1) return 0; for (register long long i = 1; i <= len; i++) mp[s[i]]++; if (mp[ c ] == mp[ a ] || mp[ c ] == mp[ b ]) return 1; return 0; } inline void solve() { scanf( %s , s + 1); puts(check() ? YES : NO ); } signed main() { long long T = 1; for (long long index = 1; index <= T; index++) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long maxn = 3e5 + 7, mod = 998244353, inf = 1e18, MAXN = 1e6 + 7; const double eps = 1e-9; mt19937 rnd(time(0)); long long n; long long cnt[maxn]; struct state { long long a, b, d; state(long long a, long long b, long long d) : a(a), b(b), d(d) {} state() : a(0), b(0), d(0) {} }; vector<state> have; bool cmp(state p1, state p2) { return p1.d > p2.d; } vector<long long> gr[maxn]; vector<long long> step[maxn]; void solve() { cin >> n; for (long long i = 1; i <= n; ++i) { long long d; cin >> d; long long a = 2 * i; long long b = a - 1; have.emplace_back(b, a, d); } sort(have.begin(), have.end(), cmp); vector<long long> even; for (auto v : have) { even.push_back(v.a); } for (long long i = 1; i < n; ++i) { gr[even[i - 1]].push_back(even[i]); } long long size = n; for (long long i = 0; i < n; ++i) { --size; long long d = have[i].d; long long b = have[i].b; if (size < d) { gr[even.back()].push_back(b); even.push_back(b); ++size; } else { gr[even[i + d - 1]].push_back(b); } } for (long long i = 1; i <= 2 * n; ++i) { for (auto v : gr[i]) { cout << i << << v << n ; } } } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.precision(20); cout << fixed; long long t = 1; for (long long i = 0; i < t; ++i) { solve(); } return 0; } |
//
// Generated by Bluespec Compiler (build 0fccbb13)
//
//
// Ports:
// Name I/O size props
// result_valid O 1
// result_value O 64 reg
// CLK I 1 clock
// RST_N I 1 reset
// put_args_x_is_signed I 1
// put_args_x I 32
// put_args_y_is_signed I 1
// put_args_y I 32
// EN_put_args I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkIntMul_32(CLK,
RST_N,
put_args_x_is_signed,
put_args_x,
put_args_y_is_signed,
put_args_y,
EN_put_args,
result_valid,
result_value);
input CLK;
input RST_N;
// action method put_args
input put_args_x_is_signed;
input [31 : 0] put_args_x;
input put_args_y_is_signed;
input [31 : 0] put_args_y;
input EN_put_args;
// value method result_valid
output result_valid;
// value method result_value
output [63 : 0] result_value;
// signals for module outputs
wire [63 : 0] result_value;
wire result_valid;
// register m_rg_isNeg
reg m_rg_isNeg;
wire m_rg_isNeg$D_IN, m_rg_isNeg$EN;
// register m_rg_signed
reg m_rg_signed;
wire m_rg_signed$D_IN, m_rg_signed$EN;
// register m_rg_state
reg [1 : 0] m_rg_state;
wire [1 : 0] m_rg_state$D_IN;
wire m_rg_state$EN;
// register m_rg_x
reg [63 : 0] m_rg_x;
wire [63 : 0] m_rg_x$D_IN;
wire m_rg_x$EN;
// register m_rg_xy
reg [63 : 0] m_rg_xy;
wire [63 : 0] m_rg_xy$D_IN;
wire m_rg_xy$EN;
// register m_rg_y
reg [31 : 0] m_rg_y;
wire [31 : 0] m_rg_y$D_IN;
wire m_rg_y$EN;
// rule scheduling signals
wire CAN_FIRE_RL_m_compute,
CAN_FIRE_put_args,
WILL_FIRE_RL_m_compute,
WILL_FIRE_put_args;
// inputs to muxes for submodule ports
wire [63 : 0] MUX_m_rg_x$write_1__VAL_1,
MUX_m_rg_x$write_1__VAL_2,
MUX_m_rg_xy$write_1__VAL_2;
wire [31 : 0] MUX_m_rg_y$write_1__VAL_1, MUX_m_rg_y$write_1__VAL_2;
// remaining internal signals
wire [63 : 0] x__h239, x__h341, xy___1__h265;
wire [31 : 0] _theResult___fst__h509,
_theResult___fst__h512,
_theResult___fst__h563,
_theResult___fst__h566,
_theResult___snd_fst__h558;
wire IF_put_args_x_is_signed_THEN_put_args_x_BIT_31_ETC___d34;
// action method put_args
assign CAN_FIRE_put_args = 1'd1 ;
assign WILL_FIRE_put_args = EN_put_args ;
// value method result_valid
assign result_valid = m_rg_state == 2'd2 ;
// value method result_value
assign result_value = m_rg_xy ;
// rule RL_m_compute
assign CAN_FIRE_RL_m_compute = m_rg_state == 2'd1 ;
assign WILL_FIRE_RL_m_compute = CAN_FIRE_RL_m_compute ;
// inputs to muxes for submodule ports
assign MUX_m_rg_x$write_1__VAL_1 = { 32'd0, _theResult___fst__h509 } ;
assign MUX_m_rg_x$write_1__VAL_2 = { m_rg_x[62:0], 1'd0 } ;
assign MUX_m_rg_xy$write_1__VAL_2 = (m_rg_y == 32'd0) ? x__h239 : x__h341 ;
assign MUX_m_rg_y$write_1__VAL_1 =
(put_args_x_is_signed && put_args_y_is_signed) ?
_theResult___fst__h566 :
_theResult___snd_fst__h558 ;
assign MUX_m_rg_y$write_1__VAL_2 = { 1'd0, m_rg_y[31:1] } ;
// register m_rg_isNeg
assign m_rg_isNeg$D_IN =
(put_args_x_is_signed && put_args_y_is_signed) ?
put_args_x[31] != put_args_y[31] :
IF_put_args_x_is_signed_THEN_put_args_x_BIT_31_ETC___d34 ;
assign m_rg_isNeg$EN = EN_put_args ;
// register m_rg_signed
assign m_rg_signed$D_IN = 1'b0 ;
assign m_rg_signed$EN = 1'b0 ;
// register m_rg_state
assign m_rg_state$D_IN = EN_put_args ? 2'd1 : 2'd2 ;
assign m_rg_state$EN =
WILL_FIRE_RL_m_compute && m_rg_y == 32'd0 || EN_put_args ;
// register m_rg_x
assign m_rg_x$D_IN =
EN_put_args ?
MUX_m_rg_x$write_1__VAL_1 :
MUX_m_rg_x$write_1__VAL_2 ;
assign m_rg_x$EN =
WILL_FIRE_RL_m_compute && m_rg_y != 32'd0 || EN_put_args ;
// register m_rg_xy
assign m_rg_xy$D_IN = EN_put_args ? 64'd0 : MUX_m_rg_xy$write_1__VAL_2 ;
assign m_rg_xy$EN =
WILL_FIRE_RL_m_compute && (m_rg_y == 32'd0 || m_rg_y[0]) ||
EN_put_args ;
// register m_rg_y
assign m_rg_y$D_IN =
EN_put_args ?
MUX_m_rg_y$write_1__VAL_1 :
MUX_m_rg_y$write_1__VAL_2 ;
assign m_rg_y$EN =
WILL_FIRE_RL_m_compute && m_rg_y != 32'd0 || EN_put_args ;
// remaining internal signals
assign IF_put_args_x_is_signed_THEN_put_args_x_BIT_31_ETC___d34 =
put_args_x_is_signed ?
put_args_x[31] :
put_args_y_is_signed && put_args_y[31] ;
assign _theResult___fst__h509 =
put_args_x_is_signed ? _theResult___fst__h512 : put_args_x ;
assign _theResult___fst__h512 = put_args_x[31] ? -put_args_x : put_args_x ;
assign _theResult___fst__h563 =
put_args_y_is_signed ? _theResult___fst__h566 : put_args_y ;
assign _theResult___fst__h566 = put_args_y[31] ? -put_args_y : put_args_y ;
assign _theResult___snd_fst__h558 =
put_args_x_is_signed ? put_args_y : _theResult___fst__h563 ;
assign x__h239 = m_rg_isNeg ? xy___1__h265 : m_rg_xy ;
assign x__h341 = m_rg_xy + m_rg_x ;
assign xy___1__h265 = -m_rg_xy ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
m_rg_state <= `BSV_ASSIGNMENT_DELAY 2'd0;
end
else
begin
if (m_rg_state$EN)
m_rg_state <= `BSV_ASSIGNMENT_DELAY m_rg_state$D_IN;
end
if (m_rg_isNeg$EN) m_rg_isNeg <= `BSV_ASSIGNMENT_DELAY m_rg_isNeg$D_IN;
if (m_rg_signed$EN) m_rg_signed <= `BSV_ASSIGNMENT_DELAY m_rg_signed$D_IN;
if (m_rg_x$EN) m_rg_x <= `BSV_ASSIGNMENT_DELAY m_rg_x$D_IN;
if (m_rg_xy$EN) m_rg_xy <= `BSV_ASSIGNMENT_DELAY m_rg_xy$D_IN;
if (m_rg_y$EN) m_rg_y <= `BSV_ASSIGNMENT_DELAY m_rg_y$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
m_rg_isNeg = 1'h0;
m_rg_signed = 1'h0;
m_rg_state = 2'h2;
m_rg_x = 64'hAAAAAAAAAAAAAAAA;
m_rg_xy = 64'hAAAAAAAAAAAAAAAA;
m_rg_y = 32'hAAAAAAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkIntMul_32
|
#include <bits/stdc++.h> using namespace std; int a[1003][1003]; int r[1003]; int c[1003]; char ch[5]; int main() { int n, m, k; scanf( %d %d %d , &n, &m, &k); for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { scanf( %d , &a[i][j]); } } for (int i = 1; i <= n; i++) { r[i] = i; } for (int i = 1; i <= m; i++) { c[i] = i; } for (int i = 1; i <= k; i++) { scanf( %s , ch); int x, y; scanf( %d %d , &x, &y); if (ch[0] == r ) { swap(r[x], r[y]); } else if (ch[0] == c ) { swap(c[x], c[y]); } else { printf( %d n , a[r[x]][c[y]]); } } return 0; } |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_t_e
//
// Generated
// by: wig
// on: Mon Jun 26 16:51:35 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../open.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_t_e.v,v 1.4 2006/07/04 09:54:11 wig Exp $
// $Date: 2006/07/04 09:54:11 $
// $Log: inst_t_e.v,v $
// Revision 1.4 2006/07/04 09:54:11 wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of inst_t_e
//
// No user `defines in this module
module inst_t_e
//
// Generated Module inst_t
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire [2:0] non_open;
wire non_open_bit;
wire [3:0] wire_open;
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_a
inst_a_e inst_a (
.open_bit(),
.open_bus(),
.open_bus_9(),
.open_in_bit_11(),
.open_in_bus_10(),
.open_part12({ non_open_bit, 3'bz, non_open }), // __W_PORT // from 5 to 3 // __W_PORT // __I_BIT_TO_BUSPORT // __I_COMBINE_SPLICES
.open_part13({ 1'bz, non_open_bit, 1'bz, 1'bz, non_open }), // __W_PORT // __I_BIT_TO_BUSPORT (x4) // __I_COMBINE_SPLICES
.openport14(), // check width and type
.wire_open({ 2'bz, wire_open }), // __W_PORT (x2) // __I_COMBINE_SPLICES
.wire_open_in(wire_open)
);
// End of Generated Instance Port Map for inst_a
// Generated Instance Port Map for inst_b
inst_b_e inst_b (
.mix_key_open(), // replace name
.non_open(non_open),
.non_open_bit(non_open_bit),
.open_bit_2(),
.open_bit_3(),
.open_bit_4()
);
// End of Generated Instance Port Map for inst_b
endmodule
//
// End of Generated Module rtl of inst_t_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; const int maxn = 300100, mod = 998244353; inline void Add(int &a, int b) { a = a + b >= mod ? a + b - mod : a + b; } int head[maxn], nxt[maxn << 1], ver[maxn << 1], tot; inline void addedge(int a, int b) { nxt[++tot] = head[a]; ver[tot] = b; head[a] = tot; nxt[++tot] = head[b]; ver[tot] = a; head[b] = tot; } int n, f[maxn][2], g[maxn][2], h[maxn]; inline void treedp(int x, int fat) { f[x][0] = f[x][1] = g[x][0] = g[x][1] = h[x] = 1; for (int i = head[x]; i; i = nxt[i]) { int y = ver[i]; if (y == fat) continue; treedp(y, x); f[x][0] = (0ll + f[y][0] + f[y][1] + g[y][0] + g[y][1] + h[y]) % mod * f[x][0] % mod; f[x][1] = (0ll + f[y][0] + g[y][0] + g[y][1] + h[y]) % mod * f[x][1] % mod; h[x] = (0ll + g[y][0] + g[y][1] + h[y]) % mod * h[x] % mod; } g[x][0] = (f[x][0] + mod - h[x]) % mod; g[x][1] = (f[x][1] + mod - h[x]) % mod; } int main() { scanf( %d , &n); for (int i = 1, a, b; i < n; i++) scanf( %d%d , &a, &b), addedge(a, b); treedp(1, 0); int ans = (0ll + g[1][0] + g[1][1] + h[1] - 1 + mod) % mod; cout << ans << endl; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2005 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
parameter [31:0] TWENTY4 = 24;
parameter [31:0] PA = TWENTY4/8;
parameter [1:0] VALUE = 2'b10;
parameter [5:0] REPL = {PA{VALUE}};
parameter [7:0] CONC = {REPL,VALUE};
parameter DBITS = 32;
parameter INIT_BYTE = 8'h1F;
parameter DWORDS_LOG2 = 7;
parameter DWORDS = (1<<DWORDS_LOG2);
parameter DBYTES=DBITS/8;
// verilator lint_off LITENDIAN
reg [DBITS-1:0] mem [0:DWORDS-1];
// verilator lint_on LITENDIAN
integer i;
integer cyc=1;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==1) begin
if (REPL != {2'b10,2'b10,2'b10}) $stop;
if (CONC != {2'b10,2'b10,2'b10,2'b10}) $stop;
end
if (cyc==2) begin
for (i = 0; i < DWORDS; i = i + 1)
mem[i] = {DBYTES{INIT_BYTE}};
end
if (cyc==3) begin
for (i = 0; i < DWORDS; i = i + 1)
if (mem[i] != {DBYTES{INIT_BYTE}}) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100005; int a[maxn], m, n, ans, dp[maxn]; inline bool check(int x) { memset(dp, 0, sizeof(dp)); for (int sta = 0; sta <= 1 && sta < n; sta++) { dp[sta] = sta ? max(a[0] + x, a[1]) : a[0]; for (int i = sta + 1; i < n; i++) { dp[i] = dp[i - 1]; if (dp[i - 1] >= a[i] - 1) dp[i] = max(dp[i], a[i] + x); if (dp[i - 1] >= a[i] - x - 1) dp[i] = max(dp[i], a[i]); if (dp[i - 2] >= a[i] - x - 1 && i >= 2) dp[i] = max(dp[i], a[i - 1] + x); } if (dp[n - 1] >= min(m - 1, m + a[sta] - x - 1)) return 1; } return 0; } int main() { scanf( %d%d , &m, &n); for (int i = 0; i < n; i++) scanf( %d , a + i); sort(a, a + n); pair<int, int> pos(a[0] + m - a[n - 1], 0); for (int i = 1; i < n; i++) { pos = max(pos, make_pair(a[i] - a[i - 1], i)); } rotate(a, a + pos.second, a + n); for (int i = n - 1; i >= 0; i--) { a[i] -= a[0]; if (a[i] < 0) { a[i] += m; } } int l = 0, r = a[0] - a[n - 1] + m - 1, ans = r; while (l <= r) { int mid = (l + r) >> 1; if (check(mid)) { ans = mid, r = mid - 1; } else l = mid + 1; } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 50 + 7; int ned[N][N]; string s[N]; void paint(const vector<pair<int, int> > &v) { set<pair<int, int> > s; queue<pair<int, int> > que; map<pair<int, int>, int> cnt; for (auto e : v) { que.push(e); s.insert(e); } const int dx[] = {2, 2, 1, 1, -1, -1, -2, -2}; const int dy[] = {1, -1, 2, -2, 2, -2, 1, -1}; int tot = 0; while (!que.empty()) { auto p = que.front(); que.pop(); tot++; for (int i = (0); i < (8); i++) { int x = p.first + dx[i]; int y = p.second + dy[i]; if (s.find(make_pair(x, y)) != s.end()) continue; if (++cnt[make_pair(x, y)] == 4) { s.insert({x, y}); que.push({x, y}); } } } cout << sz(s) << = << (((int)(s).size())) << n ; int des = ((int)(v).size()) * ((int)(v).size()) / 10; cout << des << = << (des) << n ; } int main() { std::ios::sync_with_stdio(false); std::cin.tie(0); int n; cin >> n; vector<pair<int, int> > v; for (int i = (0); i < (n); i++) { if (i & 1) v.push_back({3, i}); v.push_back({0, i}); if (((int)(v).size()) > n) break; } v.resize(n); for (auto e : v) cout << e.first << << e.second << n ; return 0; } |
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
// IP Revision: 5
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module bg_tex (
clka,
wea,
addra,
dina,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [0 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [13 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [11 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [11 : 0] douta;
blk_mem_gen_v8_3_5 #(
.C_FAMILY("artix7"),
.C_XDEVICEFAMILY("artix7"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(0),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(1),
.C_INIT_FILE_NAME("bg_tex.mif"),
.C_INIT_FILE("bg_tex.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(0),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(12),
.C_READ_WIDTH_A(12),
.C_WRITE_DEPTH_A(11130),
.C_READ_DEPTH_A(11130),
.C_ADDRA_WIDTH(14),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(12),
.C_READ_WIDTH_B(12),
.C_WRITE_DEPTH_B(11130),
.C_READ_DEPTH_B(11130),
.C_ADDRB_WIDTH(14),
.C_HAS_MEM_OUTPUT_REGS_A(1),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_EN_SAFETY_CKT(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("4"),
.C_COUNT_18K_BRAM("1"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 6.22775 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(1'D0),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(14'B0),
.dinb(12'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.rsta_busy(),
.rstb_busy(),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(12'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, k; int a[2000000]; int dem; int maxa; int dp[10000001]; void mmax(int &a, int b) { a = max(a, b); } bool ok(int len) { for (int i = 0; i <= maxa; i++) dp[i] = 0; dp[len] = 1; for (int i = len + 1; i <= maxa; i++) { mmax(dp[i], dp[i - 1]); mmax(dp[i], dp[i >> 1] + dp[(i + 1) >> 1]); } long long sum = 0; for (int i = 1; i <= n; i++) sum += dp[a[i]]; return sum >= k; } int main() { ios::sync_with_stdio(false); cin.tie(NULL); cin >> n >> k; for (int i = 1; i <= n; i++) cin >> a[i], maxa = max(maxa, a[i]); int d = 1, c = 10000000, g, fin = -1; while (d <= c) { g = (d + c) / 2; if (ok(g)) { fin = g; d = g + 1; } else c = g - 1; } cout << fin; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1505; int n, a[maxn], sum[maxn], ans, val, ID; int d[maxn * maxn], cnt; vector<int> v[maxn * maxn]; vector<int> vv[maxn]; unordered_map<int, int> mp, L[maxn]; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]), sum[i] = sum[i - 1] + a[i]; for (int i = 1; i <= n; i++) { for (int j = i - 1; ~j; j--) { int t = sum[i] - sum[j]; d[++cnt] = t; if (!L[i][t]) L[i][t] = j + 1, vv[i].push_back(t); } } sort(d + 1, d + 1 + cnt); cnt = unique(d + 1, d + 1 + cnt) - d - 1; for (int i = 1; i <= cnt; i++) mp[d[i]] = i; for (int i = 1; i <= n; i++) { for (int j = 0; j < vv[i].size(); j++) { int t = vv[i][j], id = mp[t]; if (v[id].empty() || v[id].back() < L[i][t]) { v[id].push_back(i); } if (ans < v[id].size()) { ans = v[id].size(); val = t; ID = id; } } } printf( %d n , ans); for (int i : v[ID]) { printf( %d %d n , L[i][val], i); } return 0; } |
/*
* Copyright (c) 2002 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
*/
`timescale 1ns / 1ns
module main;
initial begin
#3 $display("$time = %t (unformatted)", $time);
$timeformat(-6, 6, "ns", 12);
$display("$time = %t (-6,6)", $time);
$timeformat(-6, 1, "ns", 12);
$display("$time = %t (-6,1)", $time);
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; const int maxn = 333333; int ans[maxn]; int fa[maxn]; int nx[maxn]; int visit[maxn]; int n, m; inline int query(int a) { return a == fa[a] ? a : fa[a] = query(fa[a]); } inline void conbine(int a, int b) { a = query(a), b = query(b); if (a != b) fa[a] = b; } inline void paint(int l, int r, int x) { int i = l; while (i <= r) { int a = query(i); int j = nx[a]; if (j > r) return; if (ans[j] == 0) ans[j] = x; int b = query(j + 1); int _nx = nx[b]; conbine(a, b); nx[query(a)] = _nx; i = _nx; } } int main() { int n, m; while (scanf( %d%d , &n, &m) != EOF) { for (int i = 0; i <= n + 1; ++i) fa[i] = nx[i] = i, ans[i] = 0; for (int i = 0; i < m; ++i) { int l, r, x; scanf( %d%d%d , &l, &r, &x); paint(l, x - 1, x); paint(x + 1, r, x); } for (int i = 1; i <= n; ++i) { int tmp = ans[i]; printf( %d , tmp); if (i == n) printf( n ); else printf( ); } } return 0; } |
/*
* Copyright (c) 2000 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.will need a Picture Elements Binary Software
* License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This program demonstrates the mixing of reg and memories in l-value
* contatenations.
*/
module main;
reg [3:0] mem [2:0];
reg a, b;
initial begin
mem[0] = 0;
mem[1] = 0;
mem[2] = 0;
{b, mem[1], a} = 6'b0_0000_1;
if (a !== 1'b1) begin
$display("FAILED -- a = %b", a);
$finish;
end
if (mem[1] !== 4'b0000) begin
$display("FAILED -- mem[1] = %b", mem[1]);
$finish;
end
if (b !== 1'b0) begin
$display("FAILED -- b = %b", b);
$finish;
end
{b, mem[1], a} = 6'b0_1111_0;
if (a !== 1'b0) begin
$display("FAILED -- a = %b", a);
$finish;
end
if (mem[0] !== 4'b0000) begin
$display("FAILED -- mem[0] - %b", mem[0]);
$finish;
end
if (mem[1] !== 4'b1111) begin
$display("FAILED -- mem[1] = %b", mem[1]);
$finish;
end
if (b !== 1'b0) begin
$display("FAILED -- b = %b", b);
$finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
module mem (clk, wen, addr, in, out);
parameter data_width = 32;
parameter addr_width = 8;
input clk;
input wen;
input [addr_width-1:0] addr;
input [data_width-1:0] in;
output [data_width-1:0] out;
reg [data_width-1:0] m [0:(2**addr_width)-1];
always @ (posedge clk)
if (wen) m[addr] <= in;
always @ (addr)
assign out = m[addr];
endmodule // mem
module mux2to1 (clk, sel, d1, d0, out);
parameter width = 32;
input clk;
input sel;
input [width-1:0] d1;
input [width-1:0] d0;
output [width-1:0] out;
always @ (posedge clk)
case (sel)
1: out <= d1;
0: out <= d0;
default: $display("Something is awfully wrong in the mux2to1");
endcase // case (sel)
endmodule // mux2to1
module mux4to1 (clk, sel, d3, d2, d1, d0, out);
parameter width = 32;
input clk;
input [1:0] sel;
input [width-1:0] d3;
input [width-1:0] d2;
input [width-1:0] d1;
input [width-1:0] d0;
output [width-1:0] out;
always @ (posedge clk)
case (sel)
3: out <= d3;
2: out <= d2;
1: out <= d1;
0: out <= d0;
default: $display("Something is awfully wrong in the mux4to1");
endcase // case (sel)
endmodule // mux4to1
module control (clk);
parameter data_width = 32;
parameter addr_width = 8;
wire imem_en; assign imem_en = 0;
wire [addr_width-1:0] imem_addr;
wire [data_width-1:0] imem_din;
wire [data_width-1:0] imem_dout;
mem imem (clk, imem_en, imem_addr, imem_din, imem_dout);
wire dmem_en;
wire [addr_width-1:0] dmem_addr;
wire [data_width-1:0] dmem_din;
wire [data_width-1:0] dmem_dout;
mem imem (clk, dmem_en, dmem_addr, dmem_din, dmem_dout);
reg [addr_width-1:0] pc;
// mux2to1 pc_mux (clk, SELECT, d, pc + 1, pc);
endmodule // control
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A211OI_1_V
`define SKY130_FD_SC_LP__A211OI_1_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog wrapper for a211oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a211oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a211oi_1 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a211oi_1 (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A211OI_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND2_BLACKBOX_V
`define SKY130_FD_SC_HS__AND2_BLACKBOX_V
/**
* and2: 2-input AND.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__and2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND2_BLACKBOX_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:47:32 11/06/2013
// Design Name:
// Module Name: i2s_out
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
// Recibe un clock de 50Mhz
//
//////////////////////////////////////////////////////////////////////////////////
module i2s_out(
input clock,
input reset,
input[15:0] left_data,
input[15:0] right_data,
output mclk,
output lrck,
output reg sdin);
reg [3:0] data_pos;
initial
begin
data_pos <= 4'b0;
sdin <= 1'b0;
end
/** mclk es igual al clock . 50Mhz */
assign mclk = clock;
/** mclk/lrck = 64 entonces lrck se hace de 781250Hz */
lrck_divider lrck_gen(
.clock(clock),
.reset(reset),
.clock_out(lrck)
);
/** sclk/lrck = 32 y mclk/sclk = 2. Entonces sclk = 25Mhz*/
wire sclk;
sclk_divider sclk_gen(
.clock(clock),
.reset(reset),
.clock_out(sclk)
);
/**
* flanco positivo de lrck = canal derecho
* flanco negativo de lrck = canal izquierdo
* los datos se mandan con sclk
**/
always @ (negedge sclk or posedge reset)
begin
if(reset)
begin
data_pos <= 4'b0;
sdin <= 1'b0;
end
else
begin
if(lrck) //Canal derecho
begin
if(data_pos == 4'd0)
begin
sdin <= 1'b0;
end
else
begin
sdin <= right_data[data_pos];
end
end
else //Canal izquierdo
begin
if(data_pos == 4'd0)
begin
sdin <= 1'b0;
end
else
begin
sdin <= left_data[data_pos];
end
end
/** Siempre hay que cambiar la posicion */
data_pos <= data_pos - 1;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLXTN_BEHAVIORAL_V
`define SKY130_FD_SC_LS__DLXTN_BEHAVIORAL_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dlxtn (
Q ,
D ,
GATE_N
);
// Module ports
output Q ;
input D ;
input GATE_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire GATE ;
wire buf_Q ;
wire GATE_N_delayed;
wire D_delayed ;
reg notifier ;
wire awake ;
// Name Output Other arguments
not not0 (GATE , GATE_N_delayed );
sky130_fd_sc_ls__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE, notifier, VPWR, VGND);
buf buf0 (Q , buf_Q );
assign awake = ( VPWR === 1'b1 );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLXTN_BEHAVIORAL_V |
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: io_mux.v
//
// *Module Description:
// I/O mux for port function selection.
//
// *Author(s):
// - Olivier Girard,
//
//----------------------------------------------------------------------------
// $Rev: 23 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
//----------------------------------------------------------------------------
module io_mux (
// Function A (typically GPIO)
a_din,
a_dout,
a_dout_en,
// Function B (Timer A, ...)
b_din,
b_dout,
b_dout_en,
// IO Cell
io_din,
io_dout,
io_dout_en,
// Function selection (0=A, 1=B)
sel
);
// PARAMETERs
//============
parameter WIDTH = 8;
// Function A (typically GPIO)
//===============================
output [WIDTH-1:0] a_din;
input [WIDTH-1:0] a_dout;
input [WIDTH-1:0] a_dout_en;
// Function B (Timer A, ...)
//===============================
output [WIDTH-1:0] b_din;
input [WIDTH-1:0] b_dout;
input [WIDTH-1:0] b_dout_en;
// IO Cell
//===============================
input [WIDTH-1:0] io_din;
output [WIDTH-1:0] io_dout;
output [WIDTH-1:0] io_dout_en;
// Function selection (0=A, 1=B)
//===============================
input [WIDTH-1:0] sel;
//=============================================================================
// 1) I/O FUNCTION SELECTION MUX
//=============================================================================
function [WIDTH-1:0] mux (
input [WIDTH-1:0] A,
input [WIDTH-1:0] B,
input [WIDTH-1:0] SEL
);
integer i;
begin
mux = {WIDTH{1'b0}};
for (i = 0; i < WIDTH; i = i + 1)
mux[i] = sel[i] ? B[i] : A[i];
end
endfunction
assign a_din = mux( io_din, {WIDTH{1'b0}}, sel);
assign b_din = mux({WIDTH{1'b0}}, io_din, sel);
assign io_dout = mux( a_dout, b_dout, sel);
assign io_dout_en = mux( a_dout_en, b_dout_en, sel);
endmodule // io_mux
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 10; struct node { int a, b, id; bool operator<(const node& tem) const { return a > tem.a; } } vec[maxn]; bool used[maxn]; int n; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &vec[i].a); for (int i = 1; i <= n; i++) scanf( %d , &vec[i].b); for (int i = 1; i <= n; i++) vec[i].id = i; sort(vec + 1, vec + 1 + n); priority_queue<pair<int, int> > q; int pcou = 1, cnt = 0; for (int i = 1; i <= n / 2 + 1; i++) { while (pcou <= n && pcou <= 2 * i - 1) { q.push(pair<int, int>(vec[pcou].b, vec[pcou].id)); ++pcou; } if (!q.empty()) { ++cnt; int id = q.top().second; q.pop(); used[id] = 1; } } printf( %d n , cnt); for (int i = 1; i <= n; i++) if (used[i]) printf( %d , i); return 0; } |
#include <bits/stdc++.h> using namespace std; const int MX = 102, md = 1000000007; int n, k, i, j, e, c[MX][MX], f[MX][MX * MX]; long long m, p[MX], q[MX]; bool ifq; long long pw(long long a, long long b) { if (b == 0) return 1LL; if (b & 1) return (a * pw(a, b - 1)) % md; long long x = pw(a, b / 2); return (x * x) % md; } int main() { cin >> n >> m >> k; for (i = 0; i <= n; i++) { c[i][0] = 1; for (j = 1; j <= i; j++) c[i][j] = (c[i - 1][j - 1] + c[i - 1][j]) % md; } for (i = 0; i <= n; i++) { p[i] = pw(c[n][i], m / n); q[i] = (p[i] * c[n][i]) % md; } f[0][0] = 1; for (i = 0; i < n; i++) { ifq = (i < (m % n)); for (j = 0; j <= k; j++) if (f[i][j]) for (e = 0; e <= n && j + e <= k; e++) f[i + 1][j + e] = (f[i + 1][j + e] + f[i][j] * (ifq ? q[e] : p[e])) % md; } cout << f[n][k] << n ; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O221AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__O221AI_FUNCTIONAL_PP_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__o221ai (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , B2, B1 );
or or1 (or1_out , A2, A1 );
nand nand0 (nand0_out_Y , or1_out, or0_out, C1 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O221AI_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; const long long oo = (long long)1e4; long long n, k; vector<pair<int, int> > l, r; int length(int x) { return x < 10 ? 1 : length(x / 10) + 1; } pair<int, int> checkWavy(int x) { if (x < 10) return make_pair(1, 0); int digits[8] = {x % 10, x / 10 % 10}, len = 2, sign = digits[1] > digits[0]; if (digits[1] == digits[0]) return make_pair(0, 0); x /= 100; while (x) { digits[len] = x % 10; x /= 10; if (digits[len] == digits[len - 1]) return make_pair(0, 0); int newSign = digits[len] > digits[len - 1]; if (newSign == sign) return make_pair(0, 0); sign = newSign; len++; } if (len < 6) return make_pair(1, 0); if (len == 7) return make_pair(1, 1); return make_pair(1, sign); } int main() { ios::sync_with_stdio(0); cin >> n >> k; for (int i = 1; i < int(1e7); i++) { pair<int, int> u = checkWavy(i); if (!u.first) continue; if (i % n == 0) if (!--k) { cout << i << endl; return 0; } l.push_back(make_pair(i, i % n)); if (u.second) r.push_back(make_pair(i % n, i)); } sort(l.begin(), l.end()); sort(r.begin(), r.end()); for (int i = 0; i < int(l.size()); i++) { if ((n - 1LL * l[i].second * int(1e7) % n) % n > int(1e7)) continue; int mod = (n - 1LL * l[i].second * int(1e7) % n) % n; int x = l[i].first, lastDigit = x % 10; int from = lower_bound(r.begin(), r.end(), make_pair(mod, 0)) - r.begin(); int to = lower_bound(r.begin(), r.end(), make_pair(mod + 1, 0)) - r.begin(); if (from == to) continue; for (int digit = 0; digit < 10 && from < to; digit++) { int bound = lower_bound(r.begin() + from, r.begin() + to, make_pair(mod, (digit + 1) * int(1e6))) - r.begin(); if (digit < lastDigit) { if (x < 10 || x / 10 % 10 < lastDigit) { int low = (digit * 10 + digit + 1) * int(1e5); int idLow = lower_bound(r.begin() + from, r.begin() + bound, make_pair(mod, low)) - r.begin(); if (bound - idLow >= k) { cout << x; for (int q = length(r[from + k - 1].second); q < 7; q++) cout << 0; cout << r[idLow + k - 1].second << endl; return 0; } else k -= bound - idLow; } } if (digit > lastDigit) { if (x < 10 || x / 10 % 10 > lastDigit) { int high = (digit * 10 + digit) * int(1e5); int idHigh = lower_bound(r.begin() + from, r.begin() + bound, make_pair(mod, high)) - r.begin(); if (idHigh - from >= k) { cout << x; for (int q = length(r[from + k - 1].second); q < 7; q++) cout << 0; cout << r[from + k - 1].second << endl; return 0; } else k -= idHigh - from; } } from = bound; } } cout << -1 << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m, h; string s; cin >> n >> s; m = (s[3] - 0 ) * 10 + s[4] - 0 ; if (m > 59) { s[3] = 0 ; } if (n == 24) { h = (s[0] - 0 ) * 10 + s[1] - 0 ; if (h > 23) { if (s[0] - 0 > 2) s[0] = 0 ; else if (s[1] - 0 > 3) s[1] = 0 ; } } else { h = (s[0] - 0 ) * 10 + s[1] - 0 ; if (h == 0) s[1] = 1 ; if (h > 12) { if (s[0] - 0 > 1) s[0] = 0 ; else if (s[1] - 0 > 2) s[1] = 2 ; if (s[0] == 0 && s[1] == 0 ) s[0] = 1 ; } } cout << s << endl; return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08:33:08 11/02/2013
// Design Name:
// Module Name: sounds_module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sounds_module(input lrck, input reset, input[2:0] sound_code,
output reg[15:0] left_data, output reg[15:0] right_data);
/** Variable para recorrer el arreglo de la data de cada sonido */
reg [2:0] position;
/** Matriz que contiene los datos de un sonido */
parameter [15:0] sample_sound_left [2:0];
parameter [15:0] sample_sound_right [2:0];
initial
begin
/** Position empieza en cero */
position <= 1;
/** Se debe guardar los datos de los sonidos */
sample_sound_left[0] <= 16'd1;
sample_sound_right[0] <= 16'd2;
sample_sound_left[1] <= 16'd3;
sample_sound_right[1] <= 16'd4;
sample_sound_left[2] <= 16'd5;
sample_sound_right[2] <= 16'd6;
end
always @ (negedge lrck)
begin
case(sound_code)
3'b000:
begin
left_data <= sample_sound_left[position];
right_data <= sample_sound_right[position];
end
default:
begin
left_data <= sample_sound_left[position];
right_data <= sample_sound_right[position];
end
endcase
position <= position + 1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; int main() { int n; cin >> n; vector<int> a(n); for (int i = 0; i < n; i++) { cin >> a[i]; } map<vector<int>, int> S; for (int bit = 0; bit < (1 << 15); bit++) { vector<int> b(n); for (int i = 0; i < n; i++) { int c = a[i] ^ bit; for (int j = 0; j < 15; j++) { if (c & (1 << j)) b[i]++; } } vector<int> vec(n - 1); for (int i = 1; i < n; i++) { vec[i - 1] = b[i] - b[0]; } S[vec] = bit; } for (int bit = 0; bit < (1 << 15); bit++) { vector<int> b(n); for (int i = 0; i < n; i++) { int c = a[i] ^ (bit << 15); for (int j = 15; j < 30; j++) { if (c & (1 << j)) b[i]++; } } vector<int> vec(n - 1); for (int i = 1; i < n; i++) { vec[i - 1] = b[0] - b[i]; } if (S.find(vec) != S.end()) { cout << (bit << 15) + S[vec] << endl; return 0; } } cout << -1 << endl; } |
`timescale 1ns / 1ps
`define DEBUG
// Output Left-Justified 24bit 192kHz 2ch (Stereo) Audio Stream
module dac_drv(
input wire clk,
input wire rst,
output wire bck_o,
output wire data_o,
output wire lrck_o,
input wire [1:0] ack_i,
input wire [23:0] data_i,
output wire [1:0] pop_o);
// 256fs * 192kHz = 49.152Mhz
reg [7:0] clk_counter;
always @(posedge clk)
if(rst)
clk_counter <= 0;
else
clk_counter <= clk_counter + 1;
// generate bck = 4x clk = 64fs * 192kHz = 12.28Mhz
wire bck_int_o = clk_counter[1];
reg bck_ff;
always @(posedge clk)
bck_ff <= bck_int_o;
assign bck_o = bck_ff;
// generate lrck = 256x clk = 192kHz
wire lrck_int_o = ~clk_counter[7];
reg lrck_ff;
always @(posedge clk)
lrck_ff <= lrck_int_o;
assign lrck_o = lrck_ff;
// generate data
reg [23:0] data_i_ff [1:0];
always @(posedge clk) begin
if(rst) begin
data_i_ff[0] <= 0;
data_i_ff[1] <= 0;
end else if(ack_i[0])
data_i_ff[0] <= data_i;
else if (ack_i[1])
data_i_ff[1] <= data_i;
end
assign pop_o[1] = (clk_counter == 8'b00000000);
assign pop_o[0] = (clk_counter == 8'b10000000);
reg [31:0] data_o_ff;
wire data_int_o = data_o_ff[31];
reg data_o_buf_ff;
always @(posedge clk)
data_o_buf_ff <= data_int_o;
assign data_o = data_o_buf_ff;
wire chsel = clk_counter[7];
always @(posedge clk) begin
if(clk_counter[6:0] == 7'h7f) begin
`ifdef DEBUG
$display("dac_drv: lr %d send %h", lrck_o, data_i_ff[chsel]);
`endif
data_o_ff <= {data_i_ff[chsel], 8'b0};
end else if(clk_counter[1:0] == 2'b11) begin
data_o_ff <= {data_o_ff[30:0], 1'b0};
end
end
endmodule
|
`timescale 1ns / 1ps
/*
-- Module Name: Input Queue
-- Description: Estructura FIFO. El modulo permite el intercambio de
medio de almacenamiento. Por ejemplo, el uso del diseño
registerFile_distRAM.v implementa un banco de registros
que utiliza de manera exclusiva bloques de memoria
distribuida en FPGAs de Xilinx.
Las banderas de full/empty estan deshabilitadas ya que
la informacion almacenada es auto regulada por el
mecanismo de creditos.
-- Dependencies: -- system.vh
-- fifo_control.v
-- registerFile_distRAM.v (** intercambiable)
-- Parameters: -- CHANNEL_WIDTH: Ancho de palabra de los canales
de comunicacion entre routers.
-- BUFFER_DEPTH: Numero de direcciones en la
estructura de memoria.
-- ADDR_WIDTH: Numero de bits requerido para
representar el espacio de
direcciones del elemento de
memoria del FIFO.
-- Original Author: Héctor Cabrera
-- Current Author:
-- Notas:
-- History:
-- Creacion 07 de Junio 2015
*/
`include "system.vh"
module fifo
(
input wire clk,
input wire reset,
// -- inputs ------------------------------------------------- >>>>>
input wire write_strobe_din,
input wire read_strobe_din,
input wire [`CHANNEL_WIDTH-1:0] write_data_din,
// -- outputs ------------------------------------------------ >>>>>
output wire full_dout,
output wire empty_dout,
output wire [`CHANNEL_WIDTH-1:0] read_data_dout
);
// --- Definiciones Locales -------------------------------------- >>>>>
localparam ADDR_WIDTH = clog2(`BUFFER_DEPTH);
/*
-- Instancia :: Unidad de Control de FIFO
-- Descripcion: Implementacion de estructura de control para FIFO.
Incluye punteros para el camculo de la direccion a
escribir y a leer.
*/
// -- Unidad de Control -------------------------------------- >>>>>
wire [ADDR_WIDTH-1:0] write_addr;
wire [ADDR_WIDTH-1:0] read_addr;
wire write_enable;
fifo_control_unit fifo_control_unit
(
.clk (clk),
.reset (reset),
// -- inputs ----------------------------------------- >>>>>
.write_strobe_din (write_strobe_din),
.read_strobe_din (read_strobe_din),
// -- outputs ---------------------------------------- >>>>>
.full_dout (full_dout),
.empty_dout (empty_dout),
.write_addr_dout (write_addr),
.read_addr_dout (read_addr)
);
assign write_enable = write_strobe_din & ~full_dout;
/*
-- Instancia :: Banco de registros
-- Descripcion: Elemento de almacenamiento del FIFO. Puede intercambiar
la implementacion del banco de memoria (Memoria
Distribuida / Bloque de Memoria).
*/
// -- Banco de Registros ------------------------------------- >>>>>
register_file register_file
(
.clk(clk),
// -- inputs ------------------------------------- >>>>>
.write_strobe_din (write_enable),
.write_address_din (write_addr),
.write_data_din (write_data_din),
.read_address_din (read_addr),
// -- outputs ------------------------------------ >>>>>
.read_data_dout (read_data_dout)
);
// -- Codigo no sintetizable ------------------------------------ >>>>>
// -- Funciones ---------------------------------------------- >>>>>
// Funcion de calculo: log2(x) ---------------------- >>>>>
function integer clog2;
input integer depth;
for (clog2=0; depth>0; clog2=clog2+1)
depth = depth >> 1;
endfunction
endmodule
/* -- Plantilla de instancia ------------------------------------- >>>>>
wire [`CHANNEL_WIDTH-1:0] read_data;
wire full;
wire empty;
fifo buffer_de_paquetes
(
.clk (clk),
.reset (reset),
// -- inputs --------------------------------------------- >>>>>
.write_strobe_din (write_strobe),
.read_strobe_din (read_strobe),
.write_data_din (write_data),
// -- outputs -------------------------------------------- >>>>>
.full_dout (full),
.empty_dout (empty),
.read_data_dout (read_data)
);
*/
|
#include <bits/stdc++.h> using namespace std; vector<int> mark[4]; string sins[4]; int cost[5]; int sta[1010]; int dp[1010][0xffff + 1]; int main() { int n; cin >> n; for (int i = 0; i < 4; i++) cin >> cost[i]; for (int i = 0; i < 4; i++) cin >> sins[i]; for (int j = 0; j < n; j++) { sta[j] = 0; for (int i = 0; i < 4; i++) { sta[j] |= (sins[i][j] == * ) ? (1 << i) : 0; } } int S = 0; for (int i = 0; i < 4; i++) { S |= sta[i] << (i * 4); sta[n + i] = 0; } for (int i = 0; i < 4; i++) { for (int j = 3; j >= i; j--) { int t = 0xffff; for (int k = 0; k <= i; k++) { for (int y = j; y >= j - i; y--) t ^= 1 << (4 * k + y); } mark[i].push_back(t); } } memset(dp, 0x7f, sizeof(dp)); dp[0][S] = 0; for (int i = 0; i < n; i++) { for (int j = 0xffff; j >= 0; j--) { if (dp[i][j] == 0x7f7f7f7f) continue; if ((j & 0xf) == 0) { int S = (((j & 0xffff) >> 4) | (0xf000 & (sta[i + 4] << 12))); dp[i + 1][S] = min(dp[i + 1][S], dp[i][j]); } for (int k = 0; k < 4 && k + i < n; k++) { vector<int>::iterator y; for (y = mark[k].begin(); y != mark[k].end(); y++) { dp[i][j & (*y)] = min(dp[i][j & (*y)], dp[i][j] + cost[k]); } } } } cout << dp[n][0] << endl; } |
#include <bits/stdc++.h> using namespace std; string a, b, p1 = Widget , p2 = VBox , p3 = HBox , ans[105]; map<string, int> q; vector<int> d[105]; int id[105]; long long l[105], r[105], h1[105], h2[105]; void dfs(int x) { if (l[x] != -1) return; l[x] = 0; for (int i = 0; i < (int)d[x].size(); ++i) { int v = d[x][i]; dfs(v); if (id[x] == 2) { l[x] += l[v]; r[x] = max(r[x], r[v]); } else { r[x] += r[v]; l[x] = max(l[x], l[v]); } } if (d[x].size()) { if (id[x] == 2) { l[x] = l[x] + (d[x].size() - 1) * h2[x]; r[x] += 2 * h1[x]; l[x] += 2 * h1[x]; } else { r[x] = r[x] + (d[x].size() - 1) * h2[x]; l[x] += 2 * h1[x]; r[x] += 2 * h1[x]; } } } int main() { memset(l, -1, sizeof(l)); int n, tot = 0; scanf( %d , &n); for (int i = 1; i <= n; ++i) { cin >> a; if (a == p1) { cin >> a; b = ; for (int j = 0, k; j < (int)a.size(); ++j) { if (a[j] == ( ) { q[b] = ++tot; ans[tot] = b; l[tot] = 0; for (k = j + 1;; ++k) { if (a[k] == , ) break; l[tot] = l[tot] * 10 + a[k] - 0 ; } for (++k;; ++k) { if (a[k] == ) ) break; r[tot] = r[tot] * 10 + a[k] - 0 ; } break; } b += a[j]; } } else if (a == p2) { cin >> a; q[a] = ++tot; ans[tot] = a; id[tot] = 1; } else if (a == p3) { cin >> a; q[a] = ++tot; ans[tot] = a; id[tot] = 2; } else { string c = ; for (int j = 0; j < (int)a.size(); ++j) { if (a[j] == . ) { if (a[j + 1] == p ) { b = ; for (int k = j + 6; k < (int)a.size() - 1; ++k) b += a[k]; d[q[c]].push_back(q[b]); } else { long long tp = 0; for (int k = j + 1; k < (int)a.size(); ++k) if (a[k] >= 0 && a[k] <= 9 ) tp = tp * 10 + a[k] - 0 ; if (a[j + 5] == b ) h1[q[c]] = tp; else h2[q[c]] = tp; } break; } c += a[j]; } } } sort(ans + 1, ans + tot + 1); for (int i = 1; i <= tot; ++i) { dfs(q[ans[i]]); cout << ans[i] << ; printf( %I64d %I64d n , l[q[ans[i]]], r[q[ans[i]]]); } } |
#include <bits/stdc++.h> using namespace std; int n; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n; char ch; int Sum = 0, Count = 0; n /= 2; for (int i = 1; i <= n; i++) { cin >> ch; if (ch == 4 || ch == 7 ) { Count++; } Sum += ch - 0 ; } for (int i = 1; i <= n; i++) { cin >> ch; if (ch == 4 || ch == 7 ) { Count++; } Sum -= ch - 0 ; } cout << (Sum == 0 && Count == n * 2 ? YES : NO ); return 0; } |
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
// Designer : Bob Hu
//
// Description:
// The Reset Sync module to implement reset control
//
// ====================================================================
`include "e203_defines.v"
module e203_subsys_hclkgen_rstsync (
input clk, // clock
input rst_n_a, // async reset
input test_mode, // test mode
output rst_n
);
localparam RST_SYNC_LEVEL = `E203_ASYNC_FF_LEVELS;
reg [RST_SYNC_LEVEL-1:0] rst_sync_r;
always @(posedge clk or negedge rst_n_a)
begin:rst_sync_PROC
if(rst_n_a == 1'b0)
begin
rst_sync_r[RST_SYNC_LEVEL-1:0] <= {RST_SYNC_LEVEL{1'b0}};
end
else
begin
rst_sync_r[RST_SYNC_LEVEL-1:0] <= {rst_sync_r[RST_SYNC_LEVEL-2:0],1'b1};
end
end
assign rst_n = test_mode ? rst_n_a : rst_sync_r[`E203_ASYNC_FF_LEVELS-1];
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5 + 256; const char nxt = n ; inline void in(string Q) { Q += .in ; freopen(Q.c_str(), r , stdin); } inline void out(string Q) { Q += .out ; freopen(Q.c_str(), w , stdout); } inline void open_file(string Q) { in(Q); out(Q); } int n, a[111][111]; int main() { if (0) open_file( ); scanf( %d , &n); while (n--) { int x, y, X, Y; scanf( %d , &x); scanf( %d , &y); scanf( %d , &X); scanf( %d , &Y); for (int i = x; i <= X; ++i) { for (int j = y; j <= Y; ++j) { a[i][j]++; } } } int ans = 0; for (int i = 1; i <= 100; ++i) { for (int j = 1; j <= 100; ++j) { ans += a[i][j]; } } cout << ans; return 0; } |
module so2par(
input clk,
input ym_so,
input ym_sh1,
input ym_sh2,
input ym_p1,
output reg [15:0] left,
output reg [15:0] right,
output reg [15:0] left_exp,
output reg [15:0] right_exp,
output update_left,
output update_right
);
reg [12:0] sreg;
reg last_ym_sh1,last_ym_sh2;
reg [15:0] dr,dl;
reg [15:0] left0_pm, right0_pm;
reg [ 2:0] sr,sl;
reg [15:0] out_r,out_l;
reg update_l, update_r;
always @(posedge ym_p1) begin : sh_edges
last_ym_sh1 <= ym_sh1;
last_ym_sh2 <= ym_sh2;
end
always @(posedge ym_p1) begin : shift_register
// shift register
sreg <= {ym_so,sreg[12:1]};
if(last_ym_sh1 & ~ym_sh1)
begin
update_r <= 1'b1;
out_r <= dr;
sr <= sreg[12:10];
dr <= {~sreg[9],sreg[8:0],6'b000000};
right0_pm<= { 3'd0, sreg };
end else begin
update_r <= 1'b0;
if(sr<7) begin
sr <= sr + 1;
dr[14:0] <= dr[15:1];
end
end
if(last_ym_sh2 & ~ym_sh2)
begin
update_l <= 1'b1;
out_l <= dl;
sl <= sreg[12:10];
dl <= {~sreg[9],sreg[8:0],6'b000000};
left0_pm <= { 3'd0, sreg };
end else begin
update_l <= 1'b0;
if(sl<7) begin
sl <= sl + 1;
dl[14:0] <= dl[15:1];
end
end
end
reg [1:0] aux_upr, aux_upl;
assign update_right = aux_upr[1];
assign update_left = aux_upl[1];
always @(posedge clk) begin : update_sync
aux_upr[0] <= update_r;
aux_upr[1] <= aux_upr[0];
aux_upl[0] <= update_l;
aux_upl[1] <= aux_upl[0];
end
reg [15:0] aux_l, aux_r, left1, right1;
always @(posedge clk) begin : output_sync
if( update_l | update_r ) begin
aux_r <= out_r;
right <= aux_r;
aux_l <= out_l;
left <= aux_l;
// salidas en formato exponencial
left1 <= left0_pm;
left_exp <= left1;
right1 <= right0_pm;
right_exp<= right1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n; cin >> n; long long int ar[100000], br[10000]; memset(br, 0, sizeof(br)); for (long long int i = 1; i <= n; i++) { cin >> ar[i]; br[ar[i]]++; } sort(ar + 1, ar + n + 1); if (n == 1) { cout << YES << endl; } else if (ar[1] == ar[n]) { cout << NO << endl; } else { int f = 0; sort(br + 1, br + 10000, greater<long long int>()); for (long int i = 1; i <= n; i++) { if (br[i] > (n + 1) / 2) { f = 1; } } if (f == 0) { cout << YES << endl; } else cout << NO << endl; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSRECEIVER_M_V
`define SKY130_FD_SC_LP__BUSRECEIVER_M_V
/**
* busreceiver: Bus signal receiver.
*
* Verilog wrapper for busreceiver with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__busreceiver.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__busreceiver_m (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__busreceiver base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__busreceiver_m (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__busreceiver base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSRECEIVER_M_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 200000 + 10; struct Tree { int tl, tr; int mx; } tree[maxn << 2]; set<int> st[maxn]; int ve[maxn], n, m; void build(int id, int l, int r) { tree[id].tl = l; tree[id].tr = r; tree[id].mx = -1; if (l == r) return; int mid = (l + r) >> 1; build(id << 1, l, mid); build(id << 1 | 1, mid + 1, r); } void update(int id, int pos, int val, int y) { int l = tree[id].tl, r = tree[id].tr; if (l == r) { if (st[pos].size()) tree[id].mx = *(--st[pos].end()); else tree[id].mx = -1; return; } int mid = (l + r) >> 1; if (pos <= mid) update(id << 1, pos, val, y); else update(id << 1 | 1, pos, val, y); tree[id].mx = max(tree[id << 1].mx, tree[id << 1 | 1].mx); } int query(int id, int ql, int qr, int y) { int l = tree[id].tl, r = tree[id].tr; if (tree[id].mx <= y || ql > qr) { return -1; } int mid = (l + r) >> 1; if (l == r) return l; if (qr <= mid) return query(id << 1, ql, qr, y); else if (ql > mid) return query(id << 1 | 1, ql, qr, y); else { int tmp = query(id << 1, ql, mid, y); if (tmp != -1) return tmp; return query(id << 1 | 1, mid + 1, qr, y); } } struct Point { int x, y; char op[5]; void init() { scanf( %s%d%d , op, &x, &y); } } q[maxn]; int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) { q[i].init(); ve[i] = q[i].x; } sort(ve + 1, ve + 1 + n); int m = unique(ve + 1, ve + 1 + n) - (ve + 1); build(1, 1, m); for (int i = 1; i <= n; i++) { int pos = lower_bound(ve + 1, ve + 1 + m, q[i].x) - ve; if (q[i].op[0] == a ) { st[pos].insert(q[i].y); update(1, pos, 1, q[i].y); } else if (q[i].op[0] == r ) { st[pos].erase(q[i].y); update(1, pos, 1, q[i].y); } else { int ans = query(1, pos + 1, m, q[i].y); if (ans == -1) printf( -1 n ); else printf( %d %d n , ve[ans], *st[ans].upper_bound(q[i].y)); } } return 0; } |
#include <bits/stdc++.h> using namespace std; long long len(long long x, long long y) { return x * x + y * y; } long long scal(long long x1, long long y1, long long x2, long long y2) { if (x1 * y2 == x2 * y1) return -1; return x1 * x2 + y1 * y2; } bool in(long long x1, long long y1, long long x2, long long y2, long long x, long long y) { long long vx = x1 - x; long long vy = y1 - y; long long wx = x2 - x; long long wy = y2 - y; if (vx * wy == vy * wx && vx * wx + vy * wy < 0) return true; return false; } bool sootn(long long x1, long long y1, long long x2, long long y2, long long x, long long y) { long long vx = x - x1; long long vy = y - y1; long long wx = x - x2; long long wy = y - y2; long long l1 = len(vx, vy); long long l2 = len(wx, wy); if (l1 >= l2) return (16 * l2 >= l1); else return (16 * l1 >= l2); } int Solution() { int t; scanf( %d , &t); for (int i = 0; i < t; ++i) { long long x[6], y[6]; for (int j = 0; j < 6; ++j) scanf( %I64d%I64d , &x[j], &y[j]); int ind = -1; for (int j = 0; j < 6; ++j) for (int k = j + 1; k < 6; ++k) if (x[j] == x[k] && y[j] == y[k]) { ind = j; break; } if (ind == -1) { printf( NO n ); continue; } int ind1 = -1, ind2; for (int j = 0; j < 6; ++j) if (x[j] == x[ind] && y[j] == y[ind]) if (ind1 == -1) ind1 = j; else ind2 = j; if (ind1 & 1) ind1--; else ind1++; if (ind2 & 1) ind2--; else ind2++; long long an = scal(x[ind1] - x[ind], y[ind1] - y[ind], x[ind2] - x[ind], y[ind2] - y[ind]); if (an < 0) { printf( NO n ); continue; } int num3 = 3 - ind1 / 2 - ind2 / 2; if (in(x[ind], y[ind], x[ind1], y[ind1], x[num3 * 2], y[num3 * 2]) && in(x[ind], y[ind], x[ind2], y[ind2], x[num3 * 2 + 1], y[num3 * 2 + 1])) { bool soot = sootn(x[ind], y[ind], x[ind1], y[ind1], x[num3 * 2], y[num3 * 2]); if (!soot) { printf( NO n ); continue; } soot = sootn(x[ind], y[ind], x[ind2], y[ind2], x[num3 * 2 + 1], y[num3 * 2 + 1]); if (!soot) { printf( NO n ); continue; } } else if (in(x[ind], y[ind], x[ind1], y[ind1], x[num3 * 2 + 1], y[num3 * 2 + 1]) && in(x[ind], y[ind], x[ind2], y[ind2], x[num3 * 2], y[num3 * 2])) { bool soot = sootn(x[ind], y[ind], x[ind1], y[ind1], x[num3 * 2 + 1], y[num3 * 2 + 1]); if (!soot) { printf( NO n ); continue; } soot = sootn(x[ind], y[ind], x[ind2], y[ind2], x[num3 * 2], y[num3 * 2]); if (!soot) { printf( NO n ); continue; } } else { printf( NO n ); continue; } printf( YES n ); } return 0; } int main() { Solution(); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, q, p, p1, maxi, a[1000000], idx; stack<int> t, t1, id; int main() { scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d , &a[i]); maxi = -1; id.push(0); t.push(200000); t1.push(-1); for (int i = 1; i < n; i++) { p = 0; q = 5; while (q == 5) { idx = id.top(); p1 = t.top(); p = t1.top() + 1; if (a[idx] > a[i] && p <= p1) { q = 6; t1.top() = p; if (p > maxi) maxi = p; id.push(i); t.push(p); t1.push(-1); } else if (p1 == 200000) { q = 7; id.push(i); t.push(200000); t1.push(-1); } else { id.pop(); t.pop(); t1.pop(); } } } printf( %d , maxi + 1); return 0; } |
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module increases the frame size of video streams. *
* *
******************************************************************************/
module altera_up_video_clipper_add (
// Inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
// Bi-Directional
// Outputs
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 15; // Image's Data Width
parameter EW = 0; // Image's Empty Width
parameter IMAGE_WIDTH = 640; // Final image width in pixels
parameter IMAGE_HEIGHT = 480; // Final image height in lines
parameter WW = 9; // Final image width address width
parameter HW = 8; // Final image height address width
parameter ADD_PIXELS_AT_START = 0;
parameter ADD_PIXELS_AT_END = 0;
parameter ADD_LINES_AT_START = 0;
parameter ADD_LINES_AT_END = 0;
parameter ADD_DATA = 16'h0; // Data for added pixels
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [EW: 0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
// Bidirectional
// Outputs
output stream_in_ready;
output reg [DW: 0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg [EW: 0] stream_out_empty;
output reg stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire increment_counters;
wire new_startofpacket;
wire new_endofpacket;
wire pass_inner_frame;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output registers
always @(posedge clk)
begin
if (reset)
begin
stream_out_data <= 'h0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_empty <= 'h0;
stream_out_valid <= 1'b0;
end
else if (stream_out_ready | ~stream_out_valid)
begin
if (pass_inner_frame)
stream_out_data <= stream_in_data;
else
stream_out_data <= ADD_DATA;
stream_out_startofpacket <= new_startofpacket;
stream_out_endofpacket <= new_endofpacket;
stream_out_empty <= 'h0;
if (pass_inner_frame)
stream_out_valid <= stream_in_valid;
else
stream_out_valid <= 1'b1;
end
end
// Internal registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output assignments
assign stream_in_ready = pass_inner_frame & (~stream_out_valid | stream_out_ready);
// Internal assignments
assign increment_counters = (~stream_out_valid | stream_out_ready) &
(~pass_inner_frame | stream_in_valid);
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_video_clipper_counters Clipper_Add_Counters (
// Inputs
.clk (clk),
.reset (reset),
.increment_counters (increment_counters),
// Bidirectional
// Outputs
.start_of_outer_frame (new_startofpacket),
.end_of_outer_frame (new_endofpacket),
.start_of_inner_frame (),
.end_of_inner_frame (),
.inner_frame_valid (pass_inner_frame)
);
defparam
Clipper_Add_Counters.IMAGE_WIDTH = IMAGE_WIDTH,
Clipper_Add_Counters.IMAGE_HEIGHT = IMAGE_HEIGHT,
Clipper_Add_Counters.WW = WW,
Clipper_Add_Counters.HW = HW,
Clipper_Add_Counters.LEFT_OFFSET = ADD_PIXELS_AT_START,
Clipper_Add_Counters.RIGHT_OFFSET = ADD_PIXELS_AT_END,
Clipper_Add_Counters.TOP_OFFSET = ADD_LINES_AT_START,
Clipper_Add_Counters.BOTTOM_OFFSET = ADD_LINES_AT_END;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 200 * 1000 + 5; vector<pair<int, int> > adj[N]; int w[N]; int d[N]; bool mark[N]; set<pair<int, int> > s; vector<int> ans; int main() { int n, m; cin >> n >> m; for (int i = 1; i <= n; i++) { cin >> w[i]; } for (int i = 1; i <= m; i++) { int u, v; cin >> u >> v; adj[u].push_back({v, i}); adj[v].push_back({u, i}); } for (int i = 1; i <= n; i++) { d[i] = (int)adj[i].size() - w[i]; s.insert({d[i], i}); } while (s.size()) { int v = (*s.begin()).second; s.erase(s.begin()); mark[v] = true; if (d[v] > 0) { cout << DEAD ; return 0; } for (auto p : adj[v]) { int u = p.first; if (!mark[u]) { s.erase({d[u], u}); d[u]--; s.insert({d[u], u}); ans.push_back(p.second); } } } cout << ALIVE n ; reverse(ans.begin(), ans.end()); for (auto x : ans) { cout << x << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxN = 1e5 + 7; int n, m; vector<tuple<int, int, int>> res; vector<pair<int, int>> g[maxN]; bool blocked[maxN]; bool solve(int v, int pr = -1) { vector<int> unpaired; vector<int> adj; for (auto& to : g[v]) { if (!blocked[to.second]) { adj.push_back(to.first); } blocked[to.second] = true; } for (auto& to : adj) { if (solve(to, v)) { unpaired.push_back(to); } } while (unpaired.size() >= 2) { int first = unpaired.back(); unpaired.pop_back(); int second = unpaired.back(); unpaired.pop_back(); res.push_back(make_tuple(first, v, second)); } if (unpaired.size() > 0) { int vertex = unpaired.back(); unpaired.pop_back(); res.push_back(make_tuple(pr, v, vertex)); return false; } return true; } int main() { scanf( %d %d , &n, &m); if (m % 2 == 1) { printf( No solution n ); return 0; } for (int i = 0; i < m; ++i) { int a, b; scanf( %d %d , &a, &b); g[a].push_back({b, i}); g[b].push_back({a, i}); } solve(1); for (auto& x : res) { printf( %d %d %d n , get<0>(x), get<1>(x), get<2>(x)); } return 0; } |
#include <bits/stdc++.h> class Counter { public: Counter(std::vector<size_t> perm1, std::vector<size_t> perm2) : size_(perm1.size()) { std::vector<size_t> inv2(size_, 0); for (size_t i = 0; i < size_; ++i) { inv2[perm2[i]] = i; } auto& points = perm1; for (size_t x = 0; x < size_; ++x) { points[x] = inv2[perm1[x]]; } size_t nextPowOfTwo = 1; while (nextPowOfTwo < size_) nextPowOfTwo <<= 1; segTree_.resize(2 * nextPowOfTwo - 1); build(points, 0, 0, size_ - 1); } int count(size_t minX, size_t maxX, size_t minY, size_t maxY) { return countAux(0, 0, size_ - 1, minX, maxX, minY, maxY); } private: void build(const std::vector<size_t>& points, int vertex, int from, int to) { if (from == to) { segTree_[vertex].push_back(points[from]); } else { int middle = from + (to + 1 - from) / 2; build(points, 2 * vertex + 1, from, middle - 1); build(points, 2 * vertex + 2, middle, to); const auto& left = segTree_[2 * vertex + 1]; const auto& right = segTree_[2 * vertex + 2]; segTree_[vertex].reserve(left.size() + right.size()); std::merge(left.begin(), left.end(), right.begin(), right.end(), std::back_inserter(segTree_[vertex])); } } int countAux(int vertex, int from, int to, int minX, int maxX, int minY, int maxY) { if (maxX < minX) { return 0; } if (from == minX && to == maxX) { const auto& range = segTree_[vertex]; auto it1 = std::lower_bound(range.begin(), range.end(), minY); auto it2 = std::lower_bound(range.begin(), range.end(), maxY + 1); return it2 - it1; } int middle = from + (to + 1 - from) / 2; int countLeft = countAux(2 * vertex + 1, from, middle - 1, minX, std::min(maxX, middle - 1), minY, maxY); int countRight = countAux(2 * vertex + 2, middle, to, std::max(minX, middle), maxX, minY, maxY); return countLeft + countRight; } private: size_t size_; std::vector<std::vector<int>> segTree_; }; int main() { size_t size; ::scanf( %lu , &size); auto readPerm = [](size_t size) { std::vector<size_t> perm; perm.reserve(size); for (size_t i = 0; i < size; ++i) { size_t elem; ::scanf( %lu , &elem); --elem; perm.push_back(elem); } return perm; }; auto perm1 = readPerm(size); auto perm2 = readPerm(size); Counter counter(std::move(perm1), std::move(perm2)); size_t nQueries; ::scanf( %lu , &nQueries); size_t x = 0; auto f = [&](size_t z) { return (z + x - 1) % size; }; for (size_t i = 0; i < nQueries; ++i) { size_t a, b, c, d; ::scanf( %lu %lu %lu %lu , &a, &b, &c, &d); size_t count = counter.count(std::min(f(a), f(b)), std::max(f(a), f(b)), std::min(f(c), f(d)), std::max(f(c), f(d))); std::cout << count << n ; x = count + 1; } } |
module InstructionMemory(input clock,
input clear,
input[31:0] address,
output [31:0] instr);
reg[31:0] content[255:0];
integer i;
always @(posedge clear, negedge clock)
if (clear) begin
// Reset content
for (i = 0; i < 256; i = i + 1)
content[i] = 0;
// Initial values
/*
content[0] = 32'h00221820; // add $3, $1, $2 <- label 'main'
content[1] = 32'h00221822; // sub $3, $1, $2
content[2] = 32'h00221824; // and $3, $1, $2
content[3] = 32'h00221825; // or $3, $1, $2
content[4] = 32'h0022182a; // slt $3, $1, $2
content[5] = 32'h0041182a; // slt $3, $2, $1
content[6] = 32'h1140fff9; // beq $10, $0, main
content[7] = 32'h8d430000; // lw $3, 0($10)
content[8] = 32'h8d430004; // lw $3, 4($10)
content[9] = 32'had430008; // sw $3, 8($10)
content[10] = 32'h1000fff5; // beq $0, $0, main
*/
// MULT TESTING
content[0] = 32'h00220018; // mult $1, $2
content[1] = 32'h0041001A; // div $2, $1
content[2] = 32'h00001810; // mfhi $3
content[3] = 32'h00002012; // mflo $5
end
// Read instruction
assign instr = address >= 32'h400000 && address < 32'h4004000 ?
content[(address - 32'h400000) >> 2] : 0;
// Display current instruction
always @(instr)
$display("Fetch at PC %08x: instruction %08x", address, instr);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int m, n; cin >> m >> n; cout << (n * m) / 2 << n ; } |
#include <bits/stdc++.h> using namespace std; int mod = 1e9 + 7; int mat[2 * 100001][26]; int n, k; int count3 = 0; void find_most(int x, int y) { int total = 0, mx = 0; for (int i = 0; i < 26; i++) { total += mat[x][i] + mat[y][i]; mx = max(mx, mat[x][i] + mat[y][i]); } count3 += total - mx; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int t; cin >> t; while (t--) { cin >> n >> k; string s; cin >> s; for (int i = 0; i < k; i++) { for (int j = 0; j < 26; j++) mat[i][j] = 0; } for (int i = 0; i < n; i++) { mat[i % k][s[i] - a ]++; } for (int i = 0; i < k; i++) { find_most(i, k - i - 1); } cout << (count3) / 2; count3 = 0; cout << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 201110; int lab[N], val[N]; vector<int> gr[N]; map<string, int> mp; int n, m, q; int root(int u) { if (lab[u] < 0) return u; else return lab[u] = root(lab[u]); } void join(int type, int u, int v) { if (lab[u] < lab[v]) { lab[u] += lab[v]; lab[v] = u; for (int i = 0; i < gr[v].size(); i++) { gr[u].push_back(gr[v][i]); val[gr[v][i]] *= type; } gr[v].clear(); } else { lab[v] += lab[u]; lab[u] = v; for (int i = 0; i < gr[u].size(); i++) { gr[v].push_back(gr[u][i]); val[gr[u][i]] *= type; } gr[u].clear(); } } string read() { char ch; string ans = ; while (ch = getchar()) { if ( a <= ch && ch <= z ) break; } ans = ans + ch; while (ch = getchar()) { if (ch < a || ch > z ) break; ans = ans + ch; } return ans; } int main() { scanf( %d%d%d , &n, &m, &q); int k = 0; string st; int type, u, v; for (int i = 1; i <= n; i++) { val[i] = 1; gr[i].push_back(i); st = read(); mp[st] = i; } memset(lab, 255, sizeof(lab)); for (int i = 1; i <= m; i++) { scanf( %d , &type); st = read(); u = mp[st]; st = read(); v = mp[st]; if (root(u) != root(v)) { if ((val[u] == val[v] && type == 1) || (val[u] != val[v] && type == 2)) join(1, root(u), root(v)); else join(-1, root(u), root(v)); puts( YES ); } else { if ((val[u] != val[v] && type == 1) || (val[u] == val[v] && type == 2)) puts( NO ); else puts( YES ); } } for (int i = 1; i <= q; i++) { st = read(); u = mp[st]; st = read(); v = mp[st]; if (root(u) != root(v)) printf( 3 n ); else { if (val[u] == val[v]) printf( 1 n ); else printf( 2 n ); } } } |
#include <bits/stdc++.h> using namespace std; int main() { long n; cin >> n; array<long, 2> a[n], b[n]; long i; for (i = 0; i < n; i++) { cin >> a[i][0] >> a[i][1]; } for (i = 0; i < n; i++) { if (a[i][0] != a[i][1]) { cout << rated ; return 0; } } for (i = 0; i < n - 1; i++) { if (a[i][0] < a[i + 1][0]) { cout << unrated ; return 0; } } cout << maybe ; return 0; } |
// Code ok to distribute
module autoasciienum_auto();
reg [2:0] /* auto enum sm_psm */ sm_psm;
reg [2:0] /* auto enum sm_ps2 */ sm_ps2;
localparam [2:0] // auto enum sm_psm
PSM_IDL = 0,
PSM_RST = 6,
PSM_ZOT = 7;
localparam [2:0] // auto enum sm_ps2
PS2_IDL = 0,
PS2_FOO = 1;
/*AUTOASCIIENUM("sm_psm", "_sm_psm__ascii", "_")*/
// Beginning of automatic ASCII enum decoding
reg [47:0] _sm_psm__ascii; // Decode of sm_psm
always @(sm_psm) begin
case ({sm_psm})
PSM_IDL: _sm_psm__ascii = "psmidl";
PSM_RST: _sm_psm__ascii = "psmrst";
PSM_ZOT: _sm_psm__ascii = "psmzot";
default: _sm_psm__ascii = "%Error";
endcase
end
// End of automatics
/*AUTOASCIIENUM("sm_ps2", "_sm_ps2__ascii", "_")*/
// Beginning of automatic ASCII enum decoding
reg [47:0] _sm_ps2__ascii; // Decode of sm_ps2
always @(sm_ps2) begin
case ({sm_ps2})
PS2_IDL: _sm_ps2__ascii = "ps2idl";
PS2_FOO: _sm_ps2__ascii = "ps2foo";
default: _sm_ps2__ascii = "%Error";
endcase
end
// End of automatics
endmodule : autoasciienum_auto
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module converts video in stream between color spaces on the DE *
* boards. *
* *
******************************************************************************/
module Computer_System_Video_In_Subsystem_Video_In_CSC (
// Inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
// Bidirectional
// Outputs
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter IW = 23;
parameter OW = 23;
parameter EIW = 1;
parameter EOW = 1;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [IW: 0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [EIW:0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
// Bidirectional
// Outputs
output stream_in_ready;
output reg [OW: 0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg [EOW:0] stream_out_empty;
output reg stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire transfer_data;
wire [OW: 0] converted_data;
wire converted_startofpacket;
wire converted_endofpacket;
wire [EOW:0] converted_empty;
wire converted_valid;
// Internal Registers
reg [IW: 0] data;
reg startofpacket;
reg endofpacket;
reg [EIW:0] empty;
reg valid;
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
begin
stream_out_data <= 'h0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_empty <= 2'h0;
stream_out_valid <= 1'b0;
end
else if (transfer_data)
begin
stream_out_data <= converted_data;
stream_out_startofpacket <= converted_startofpacket;
stream_out_endofpacket <= converted_endofpacket;
stream_out_empty <= converted_empty;
stream_out_valid <= converted_valid;
end
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
begin
data <= 'h0;
startofpacket <= 1'b0;
endofpacket <= 1'b0;
empty <= 'h0;
valid <= 1'b0;
end
else if (stream_in_ready)
begin
data <= stream_in_data;
startofpacket <= stream_in_startofpacket;
endofpacket <= stream_in_endofpacket;
empty <= stream_in_empty;
valid <= stream_in_valid;
end
else if (transfer_data)
begin
data <= 'b0;
startofpacket <= 1'b0;
endofpacket <= 1'b0;
empty <= 'h0;
valid <= 1'b0;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_in_ready = stream_in_valid & (~valid | transfer_data);
// Internal Assignments
assign transfer_data = ~stream_out_valid |
(stream_out_ready & stream_out_valid);
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_YCrCb_to_RGB_converter YCrCb_to_RGB (
// Inputs
.clk (clk),
.clk_en (transfer_data),
.reset (reset),
.Y (data[ 7: 0]),
.Cr (data[23:16]),
.Cb (data[15: 8]),
.stream_in_startofpacket (startofpacket),
.stream_in_endofpacket (endofpacket),
.stream_in_empty (empty),
.stream_in_valid (valid),
// Bidirectionals
// Outputs
.R (converted_data[23:16]),
.G (converted_data[15: 8]),
.B (converted_data[ 7: 0]),
.stream_out_startofpacket (converted_startofpacket),
.stream_out_endofpacket (converted_endofpacket),
.stream_out_empty (converted_empty),
.stream_out_valid (converted_valid)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; void solutionA(); int main() { ios_base::sync_with_stdio(false); solutionA(); return EXIT_SUCCESS; } long long n, a, b, u[1024]; double d[1024]; struct point { double x, y; point(double x = 0, double y = 0) : x(x), y(y) {} } s, f; struct segment { point p1, p2; } t[1024]; point operator+(const point& p1, const point& p2) { return point(p1.x + p2.x, p1.y + p2.y); } point operator-(const point& p1, const point& p2) { return point(p1.x - p2.x, p1.y - p2.y); } istream& operator>>(istream& in, point& p) { in >> p.x >> p.y; return in; } ostream& operator<<(ostream& out, point& p) { out << ( << p.x << , << p.y << ) ; return out; } double dot(const point& p1, const point& p2) { return p1.x * p2.x + p1.y * p2.y; } double cross(const point& p1, const point& p2) { return p1.x * p2.y - p1.y * p2.x; } double dist(const point& p1, const point& p2) { double dx = p1.x - p2.x, dy = p1.y - p2.y; return sqrt(dx * dx + dy * dy); } double dist(const point& p, const segment& s) { double res = min(dist(p, s.p1), dist(p, s.p2)); double cos1 = dot(p - s.p1, s.p2 - s.p1); double cos2 = dot(p - s.p2, s.p1 - s.p2); if (fabs(cos1) > 1e-9 && cos1 < 0) return res; if (fabs(cos2) > 1e-9 && cos2 < 0) return res; double h = abs(cross(p - s.p1, s.p2 - s.p1)) / dist(s.p1, s.p2); res = min(res, h); return res; } double dist(const segment& s1, const segment& s2) { double res = min(dist(s1.p1, s2), dist(s1.p2, s2)); res = min(res, min(dist(s2.p1, s1), dist(s2.p2, s1))); return res; } void solve() { memset(u, 0, sizeof(long long) * 1024); for (long long i = 0; i < 1024; ++i) d[i] = 1e12; d[0] = 0; for (;;) { long long v = -1; for (long long i = 0; i < n + 2; ++i) { if (u[i]) continue; if (fabs(d[i] - 1e12) < 1e-9) continue; if (v == -1 || d[v] > d[i]) v = i; } if (v == -1 || v == 1) break; u[v] = 1; if (v == 0) { double l = dist(s, f); if (fabs(l - a) < 1e-9 || l < a) { d[1] = l; } for (long long i = 0; i < n; ++i) { l = dist(s, t[i]); if (fabs(l - a) > 1e-9 && l > a) continue; if (fabs(a - d[i + 2]) > 1e-9 && a < d[i + 2]) { d[i + 2] = a; } } } else { double l = dist(f, t[v - 2]); if (fabs(l - a) < 1e-9 || l < a) { double l2 = d[v] + b + l; if (fabs(l2 - d[1]) > 1e-9 && l2 < d[1]) { d[1] = l2; } } for (long long i = 0; i < n; ++i) { if (i + 2 == v) continue; l = dist(t[v - 2], t[i]); if (fabs(l - a) > 1e-9 && l > a) continue; double l2 = d[v] + a + b; if (fabs(l2 - d[i + 2]) > 1e-9 && l2 < d[i + 2]) { d[i + 2] = l2; } } } } if (fabs(d[1] - 1e12) < 1e-9) cout << -1 << endl; else cout << fixed << d[1] << endl; } void solutionA() { cout.precision(6); for (; cin >> a >> b;) { cin >> s >> f >> n; for (long long i = 0; i < n; ++i) cin >> t[i].p1 >> t[i].p2; solve(); cerr << endl; } } |
#include <bits/stdc++.h> using namespace std; template <typename T1, typename T2> string print_iterable(T1 begin_iter, T2 end_iter, int counter) { bool done_something = false; stringstream res; res << [ ; for (; begin_iter != end_iter and counter; ++begin_iter) { done_something = true; counter--; res << *begin_iter << , ; } string str = res.str(); if (done_something) { str.pop_back(); str.pop_back(); } str += ] ; return str; } vector<int> SortIndex(int size, std::function<bool(int, int)> compare) { vector<int> ord(size); for (int i = 0; i < size; i++) ord[i] = i; sort(ord.begin(), ord.end(), compare); return ord; } template <typename T> bool MinPlace(T& a, const T& b) { if (a > b) { a = b; return true; } return false; } template <typename T> bool MaxPlace(T& a, const T& b) { if (a < b) { a = b; return true; } return false; } template <typename S, typename T> ostream& operator<<(ostream& out, const pair<S, T>& p) { out << { << p.first << , << p.second << } ; return out; } template <typename T> ostream& operator<<(ostream& out, const vector<T>& v) { out << [ ; for (int i = 0; i < (int)v.size(); i++) { out << v[i]; if (i != (int)v.size() - 1) out << , ; } out << ] ; return out; } template <class TH> void _dbg(const char* name, TH val) { clog << name << : << val << endl; } template <class TH, class... TA> void _dbg(const char* names, TH curr_val, TA... vals) { while (*names != , ) clog << *names++; clog << : << curr_val << , ; _dbg(names + 1, vals...); } const int MAXN = 301000; int N; int d[MAXN]; string S; int x; int d2[MAXN]; int compute(int a, int b) { for (int i = 0; i < a; i++) d2[i] = d[i]; for (int i = b; i < N; i++) d2[i] = d[i]; int diff = 0; if (S[a] == S[b]) diff = 0; else if (S[a] == ) ) diff = 2; else diff = -2; for (int i = a; i < b; i++) d2[i] = d[i] + diff; int mm = 1e9; int cnt = 0; for (int i = 0; i < N; i++) { if (d2[i] == mm) cnt++; if (d2[i] < mm) mm = d2[i], cnt = 1; } return cnt; } pair<int, pair<int, int>> solve1() { int a = N; int b = -1; for (int i = 0; i < N; i++) { if (S[i] == ) ) a = i; if (d[i] == x) break; } for (int i = N - 1; i >= 0; i--) { if (d[i] == x) break; if (S[i] == ( ) b = i; } if (a > b) return {compute(0, 0), {0, 0}}; return {compute(a, b), {a, b}}; } pair<int, pair<int, int>> solve2() { int a = N; int b = -1; for (int i = 0; i < N; i++) { if (S[i] == ) ) a = i; if (d[i] == x or d[i] == x + 1) break; } for (int i = N - 1; i >= 0; i--) { if (d[i] == x or d[i] == x + 1) break; if (S[i] == ( ) b = i; } if (a > b) return {compute(0, 0), {0, 0}}; return {compute(a, b), {a, b}}; } pair<int, pair<int, int>> solve0() { int nomove = compute(0, 0); int res = nomove; pair<int, int> best = {0, 0}; for (int i = 0; i < N; i++) { if (d[i] == x or d[i] == x + 1) continue; int a = N; int b = -1; for (int j = i; j < N; j++) { if (S[j] == ( ) { a = j; break; } if (d[j] == x or d[j] == x + 1) break; } int last_i = i + 1; for (int j = i; j < N; j++) { last_i = j; if (d[j] == x or d[j] == x + 1) break; } for (int j = last_i; j >= a; j--) { if (S[j] == ) ) { b = j; break; } } i = last_i; if (a > b) continue; int ris = nomove; for (int j = a; j < b; j++) if (d[j] == x + 2) ris++; if (ris > res) { res = ris; best = {a, b}; } } return {res, best}; } pair<int, pair<int, int>> solvem1() { int res = 0; pair<int, int> best = {0, 0}; for (int i = 0; i < N; i++) { if (d[i] == x) continue; int a = N; int b = -1; for (int j = i; j < N; j++) { if (S[j] == ( ) { a = j; break; } if (d[j] == x) break; } int last_i = i + 1; for (int j = i; j < N; j++) { last_i = j; if (d[j] == x) break; } for (int j = last_i; j >= a; j--) { if (S[j] == ) ) { b = j; break; } } i = last_i; if (a > b) continue; int ris = 0; for (int j = a; j < b; j++) if (d[j] == x + 1) ris++; if (ris > res) { res = ris; best = {a, b}; } } return {res, best}; } pair<int, pair<int, int>> solve_slow() { pair<int, int> best; int res = 0; for (int a = 0; a < N; a++) { for (int b = a; b < N; b++) { if (res < compute(a, b)) { res = compute(a, b); best = {a, b}; } } } return {res, best}; } int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> N; cin >> S; for (int i = 0; i < N; i++) { if (i > 0) d[i] = d[i - 1]; if (S[i] == ( ) d[i]++; else d[i]--; } if (d[N - 1] != 0) { cout << 0 << n ; cout << 1 << << 1 << n ; return 0; } for (int i = 0; i < N; i++) x = min(x, d[i]); vector<pair<int, pair<int, int>>> res(4); res[0] = solve1(); res[1] = solve2(); res[2] = solve0(); res[3] = solvem1(); sort(res.begin(), res.end()); cout << res.back().first << n ; cout << res.back().second.first + 1 << << res.back().second.second + 1 << n ; } |
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* SoC Interface
*/
module soc_interface_wb_8
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [7:0] input_axis_tdata,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
/*
* AXI output
*/
output wire [7:0] output_axis_tdata,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
/*
* Wishbone interface
*/
output wire [35:0] wb_adr_o, // ADR_O() address
input wire [7:0] wb_dat_i, // DAT_I() data in
output wire [7:0] wb_dat_o, // DAT_O() data out
output wire wb_we_o, // WE_O write enable output
output wire wb_stb_o, // STB_O strobe output
input wire wb_ack_i, // ACK_I acknowledge input
input wire wb_err_i, // ERR_I error input
output wire wb_cyc_o, // CYC_O cycle output
/*
* Status
*/
output wire busy
);
// state register
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_READ_ADDR = 3'd1,
STATE_READ = 3'd2,
STATE_WRITE = 3'd3,
STATE_WAIT_LAST = 3'd4;
reg [2:0] state_reg = STATE_IDLE, state_next;
reg start_read_reg = 0, start_read_next;
reg inc_addr_reg = 0, inc_addr_next;
reg [7:0] cmd_reg = 0, cmd_next;
reg [35:0] addr_reg = 0, addr_next;
reg [7:0] data_reg = 0, data_next;
reg data_valid_reg = 0, data_valid_next;
reg [1:0] byte_cnt_reg = 0, byte_cnt_next;
reg rd_data_valid_reg = 0, rd_data_valid_next;
reg [7:0] rd_data_reg = 0, rd_data_next;
reg [7:0] wr_data_reg = 0, wr_data_next;
reg input_axis_tready_reg = 0, input_axis_tready_next;
reg [7:0] output_axis_tdata_reg = 0, output_axis_tdata_next;
reg output_axis_tvalid_reg = 0, output_axis_tvalid_next;
reg output_axis_tlast_reg = 0, output_axis_tlast_next;
reg wb_we_reg = 0, wb_we_next;
reg wb_stb_reg = 0, wb_stb_next;
reg wb_cyc_reg = 0, wb_cyc_next;
reg busy_reg = 0;
assign input_axis_tready = input_axis_tready_reg;
assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tvalid = output_axis_tvalid_reg;
assign output_axis_tlast = output_axis_tlast_reg;
assign wb_adr_o = addr_reg;
assign wb_dat_o = wr_data_reg;
assign wb_we_o = wb_we_reg;
assign wb_stb_o = wb_stb_reg;
assign wb_cyc_o = wb_cyc_reg;
assign busy = busy_reg;
always @* begin
state_next = 0;
start_read_next = start_read_reg;
inc_addr_next = 0;
cmd_next = cmd_reg;
addr_next = addr_reg;
if (inc_addr_reg) begin
addr_next[31:0] = addr_reg[31:0] + 1;
end
data_next = data_reg;
data_valid_next = data_valid_reg;
byte_cnt_next = byte_cnt_reg;
rd_data_valid_next = rd_data_valid_reg;
rd_data_next = rd_data_reg;
wr_data_next = wr_data_reg;
input_axis_tready_next = 0;
output_axis_tdata_next = output_axis_tdata_reg;
output_axis_tvalid_next = output_axis_tvalid_reg & ~output_axis_tready;
output_axis_tlast_next = output_axis_tlast_reg;
wb_we_next = wb_we_reg;
wb_stb_next = wb_stb_reg;
wb_cyc_next = wb_cyc_reg;
case (state_reg)
STATE_IDLE: begin
input_axis_tready_next = ~wb_cyc_reg;
data_valid_next = 0;
byte_cnt_next = 0;
if (input_axis_tready & input_axis_tvalid) begin
// get command
cmd_next = input_axis_tdata;
if (input_axis_tlast) begin
// early end of frame
state_next = STATE_IDLE;
end else if (cmd_next[7:4] == 4'hA || cmd_next[7:4] == 4'hB) begin
// read or write command
addr_next[35:32] = cmd_next[3:0];
state_next = STATE_READ_ADDR;
end else begin
state_next = STATE_WAIT_LAST;
end
end else begin
state_next = STATE_IDLE;
end
end
STATE_READ_ADDR: begin
input_axis_tready_next = 1;
data_next = 0;
data_valid_next = 0;
rd_data_valid_next = 0;
wb_we_next = 0;
start_read_next = 1;
if (input_axis_tready & input_axis_tvalid) begin
// read address byte (MSB first)
byte_cnt_next = byte_cnt_reg + 1;
case (byte_cnt_reg)
2'd0: addr_next[31:24] = input_axis_tdata;
2'd1: addr_next[23:16] = input_axis_tdata;
2'd2: addr_next[15: 8] = input_axis_tdata;
2'd3: addr_next[ 7: 0] = input_axis_tdata;
endcase
if (input_axis_tlast) begin
// early end of frame
state_next = STATE_IDLE;
end else if (byte_cnt_reg == 3) begin
// last address byte, process command
if (cmd_reg[7:4] == 4'hA) begin
// read command
wb_cyc_next = 1;
wb_stb_next = 1;
state_next = STATE_READ;
end else if (cmd_reg[7:4] == 4'hB) begin
// write command
state_next = STATE_WRITE;
end else begin
state_next = STATE_WAIT_LAST;
end
end else begin
state_next = STATE_READ_ADDR;
end
end else begin
state_next = STATE_READ_ADDR;
end
end
STATE_READ: begin
input_axis_tready_next = 1;
if (start_read_reg & data_valid_reg) begin
// send start flag
output_axis_tdata_next = 1;
output_axis_tvalid_next = 1;
output_axis_tlast_next = 0;
start_read_next = 0;
end else if (output_axis_tready & data_valid_reg) begin
// send read data
output_axis_tvalid_next = 1;
output_axis_tdata_next = data_reg;
data_valid_next = 0;
end
state_next = STATE_READ;
if (input_axis_tvalid & input_axis_tlast) begin
// send zero with last set on frame end
output_axis_tdata_next = 0;
output_axis_tvalid_next = 1;
output_axis_tlast_next = 1;
state_next = STATE_IDLE;
end
if (!data_valid_next & rd_data_valid_reg) begin
// read data word into register
data_next = rd_data_reg;
data_valid_next = 1;
rd_data_valid_next = 0;
// initiate a new read
wb_cyc_next = 1;
wb_stb_next = 1;
wb_we_next = 0;
end
end
STATE_WRITE: begin
input_axis_tready_next = ~wb_cyc_reg;
if (input_axis_tready & input_axis_tvalid) begin
// got data byte
wr_data_next = input_axis_tdata;
wb_cyc_next = 1;
wb_stb_next = 1;
wb_we_next = 1;
input_axis_tready_next = 0;
if (input_axis_tlast) begin
state_next = STATE_IDLE;
end else begin
state_next = STATE_WRITE;
end
end else begin
state_next = STATE_WRITE;
end
end
STATE_WAIT_LAST: begin
input_axis_tready_next = 1;
if (input_axis_tready & input_axis_tvalid & input_axis_tlast) begin
state_next = STATE_IDLE;
end else begin
state_next = STATE_WAIT_LAST;
end
end
endcase
if (wb_cyc_reg & wb_stb_reg) begin
// WB cycle
if (wb_ack_i | wb_err_i) begin
// end of cycle
wb_cyc_next = 0;
wb_stb_next = 0;
wb_we_next = 0;
inc_addr_next = 1;
if (wb_we_reg) begin
// write
end else begin
// read
rd_data_next = wb_dat_i;
rd_data_valid_next = 1;
end
end
end
end
always @(posedge clk or posedge rst) begin
if (rst) begin
state_reg <= STATE_IDLE;
start_read_reg <= 0;
inc_addr_reg <= 0;
cmd_reg <= 0;
addr_reg <= 0;
data_reg <= 0;
data_valid_reg <= 0;
byte_cnt_reg <= 0;
rd_data_valid_reg <= 0;
rd_data_reg <= 0;
wr_data_reg <= 0;
input_axis_tready_reg <= 0;
output_axis_tdata_reg <= 0;
output_axis_tvalid_reg <= 0;
output_axis_tlast_reg <= 0;
wb_we_reg <= 0;
wb_stb_reg <= 0;
wb_cyc_reg <= 0;
busy_reg <= 0;
end else begin
state_reg <= state_next;
start_read_reg <= start_read_next;
inc_addr_reg <= inc_addr_next;
cmd_reg <= cmd_next;
addr_reg <= addr_next;
data_reg <= data_next;
data_valid_reg <= data_valid_next;
byte_cnt_reg <= byte_cnt_next;
rd_data_valid_reg <= rd_data_valid_next;
rd_data_reg <= rd_data_next;
wr_data_reg <= wr_data_next;
input_axis_tready_reg <= input_axis_tready_next;
output_axis_tdata_reg <= output_axis_tdata_next;
output_axis_tvalid_reg <= output_axis_tvalid_next;
output_axis_tlast_reg <= output_axis_tlast_next;
wb_we_reg <= wb_we_next;
wb_stb_reg <= wb_stb_next;
wb_cyc_reg <= wb_cyc_next;
busy_reg <= state_next != STATE_IDLE;
end
end
endmodule
|
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