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#include<bits/stdc++.h> using namespace std; #ifndef ONLINE_JUDGE #include Mohit.h #endif typedef long long ll; typedef long double ld; #define endl n #define rep(i,n) for(ll i = 0; i < (n); ++i) #define repA(i, a, n) for(ll i = a; i <= (n); ++i) #define repD(i, a, n) for(ll i = a; i >= (n); --i) #define trav(a, x) for(auto& a : x) #define all(x) x.begin(), x.end() #define ff first #define ss second #define pb push_back typedef vector<ll> vll; typedef vector<pair<ll,ll>> vpl; const ld PI = 4*atan((ld)1); const ll INF = 1e18; const ll mod = 1e9+7; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); ll tt=1; cin >> tt; repA(qq,1,tt){ ll n; cin >> n; vll a(n); rep(i,n){ cin >> a[i]; } ll ans = INF; ll s1=a[0],s2=0,c1=1,c2=0; ll m1=a[0],m2=INF; repA(i,1,n-1){ if(i&1){ m2 = min(m2,a[i]); s2 += a[i]; ll t1 = (s2-m2)+(n-(c2))*m2; ll t2 = (s1-m1)+(n-(c1-1))*m1; ans = min(ans,t1+t2); c2++; }else{ m1 = min(m1,a[i]); s1 += a[i]; ll t1 = (s1-m1)+(n-(c1))*m1; ll t2 = (s2-m2)+(n-(c2-1))*m2; ans = min(ans,t1+t2); c1++; } } cout << ans << endl; } } |
//----------------------------------------------------------------------------
//-- Memoria RAM genérica
//------------------------------------------
//-- (C) BQ. October 2015. Written by Juan Gonzalez (Obijuan)
//-- GPL license
//----------------------------------------------------------------------------
//-- Memoria con los siguientes parametros:
//-- * AW: Numero de bits de las direcciones
//-- * DW: Numero de bits de los datos
//-- * ROMFILE: Fichero a usar para cargar la memoria
//--
//-- Con este componente podemos hacer memorias ram de cualquier tamano
//----------------------------------------------------------------------------
module genram #( //-- Parametros
parameter AW = 9, //-- Bits de las direcciones (Adress width)
parameter DW = 12) //-- Bits de los datos (Data witdh)
( //-- Puertos
input clk, //-- Señal de reloj global
input cs, //-- Chip select
input wire [AW-1: 0] addr, //-- Direcciones
input wire rw, //-- Modo lectura (1) o escritura (0)
input wire [DW-1: 0] data_in, //-- Dato de entrada
output reg [DW-1: 0] data_out); //-- Dato a escribir
//-- Parametro: Nombre del fichero con el contenido de la RAM
parameter ROMFILE = "";
//-- Calcular el numero de posiciones totales de memoria
localparam NPOS = 2 ** AW;
//-- Memoria
reg [DW-1: 0] ram [0: NPOS-1];
//-- Lectura de la memoria
//-- Solo si el chip select esta activado!
always @(posedge clk) begin
if (cs & rw == 1)
data_out <= ram[addr];
end
//-- Escritura en la memoria
//-- Solo si el chip select esta activado
always @(posedge clk) begin
if (cs & rw == 0)
ram[addr] <= data_in;
end
//-- Cargar en la memoria el fichero ROMFILE
//-- Los valores deben estan dados en hexadecimal
initial begin
if (ROMFILE) $readmemh(ROMFILE, ram);
end
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) #pragma GCC target( avx,avx2,fma ) #pragma GCC optimize( unroll-loops ) using namespace std; template <typename T> bool mycomp(T x, T y) { return (x == y); } bool paircomp(const pair<long long int, long long int> &x, const pair<long long int, long long int> &y) { return x.second < y.second; } void solve() { long long int n, m; cin >> n >> m; string s[n]; for (long long int i = 0; i < n; i++) cin >> s[i]; long long int labx, laby; for (long long int i = 0; i < n; i++) { for (long long int j = 0; j < m; j++) { if (s[i][j] == L ) labx = i, laby = j; } } bool vis[n][m]; memset(vis, false, sizeof(vis)); queue<pair<long long int, long long int> > qe; qe.push({labx, laby}); vis[labx][laby] = true; while (!qe.empty()) { long long int x = qe.front().first, y = qe.front().second; qe.pop(); if (s[x][y] != L ) { long long int no = 0; if (x && s[x - 1][y] == . ) no++; if (x < n - 1 && s[x + 1][y] == . ) no++; if (y && s[x][y - 1] == . ) no++; if (y < m - 1 && s[x][y + 1] == . ) no++; if (no <= 1) s[x][y] = + , vis[x][y] = true; else continue; } if (x && !vis[x - 1][y] && s[x - 1][y] != # ) qe.push({x - 1, y}); if (x < n - 1 && !vis[x + 1][y] && s[x + 1][y] != # ) qe.push({x + 1, y}); if (y && !vis[x][y - 1] && s[x][y - 1] != # ) qe.push({x, y - 1}); if (y < m - 1 && !vis[x][y + 1] && s[x][y + 1] != # ) qe.push({x, y + 1}); } for (long long int i = 0; i < n; i++) { cout << s[i] << n ; } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long int t = 1; cin >> t; while (t--) { solve(); } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A221OI_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__A221OI_PP_BLACKBOX_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a221oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A221OI_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const unsigned long long maxn = 200005; unsigned long long n, m, vis[maxn]; unsigned long long sum, A, B, C, he[maxn]; struct node { unsigned long long x, y; bool operator<(const node &a) const { return x == a.x ? x < a.x : y < a.y; } } chongtu[maxn]; vector<unsigned long long> to[maxn], from[maxn]; vector<unsigned long long> toq[maxn], fromq[maxn]; map<pair<unsigned long long, unsigned long long>, unsigned long long> mp; inline unsigned long long read() { unsigned long long x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = (x << 1) + (x << 3) + (ch ^ 48); ch = getchar(); } return x * f; } inline void write(unsigned long long a) { if (a < 0) { putchar( - ); putchar( 1 ); } else { if (a >= 10) write(a / 10); putchar(a % 10 + 0 ); } } signed main() { n = read(), m = read(); A = read(), B = read(), C = read(); for (unsigned long long i = 0; i <= n - 3; ++i) { unsigned long long len = (n - 1) - (i + 1) + 1; sum += 1ull * len * (len - 1) / 2 * A * i; } for (unsigned long long j = 1; j <= n - 2; ++j) { unsigned long long len1 = (j - 1) - 0 + 1, len2 = (n - 1) - (j + 1) + 1; sum += 1ull * len1 * len2 * B * j; } for (unsigned long long k = 2; k <= n - 1; ++k) { unsigned long long len = (k - 1) - 0 + 1; sum += 1ull * len * (len - 1) / 2 * C * k; } for (unsigned long long i = 1; i < n; ++i) he[i] = he[i - 1] + i; for (unsigned long long i = 1; i <= m; ++i) { unsigned long long x = read(), y = read(); if (x > y) swap(x, y); chongtu[i].x = x, chongtu[i].y = y; } sort(chongtu + 1, chongtu + m + 1); for (unsigned long long i = 1; i <= m; ++i) { unsigned long long x = chongtu[i].x, y = chongtu[i].y; mp[make_pair(x, y)]++; to[x].push_back(y); toq[x].push_back(1); from[y].push_back(x); fromq[y].push_back(1); if (x >= 1) sum -= 1ull * ((x - 1) - 0 + 1) * (B * x + C * y) + 1ull * A * (he[x - 1] - he[0]); if (y - x >= 2) sum -= 1ull * ((y - 1) - (x + 1) + 1) * (A * x + C * y) + 1ull * B * (he[y - 1] - he[x]); if (y <= n - 2) sum -= 1ull * ((n - 1) - (y + 1) + 1) * (A * x + B * y) + 1ull * C * (he[n - 1] - he[y]); } for (unsigned long long i = 0; i < n; ++i) { sort(to[i].begin(), to[i].end()); sort(from[i].begin(), from[i].end()); } for (unsigned long long fu = 0; fu < n; ++fu) { unsigned long long size11 = to[fu].size(); for (unsigned long long k = 0; k < size11; ++k) { unsigned long long zi = to[fu][k]; toq[fu][k] = zi; if (k) toq[fu][k] += toq[fu][k - 1]; } } for (unsigned long long zi = 0; zi < n; ++zi) { unsigned long long size11 = from[zi].size(); for (unsigned long long k = 0; k < size11; ++k) { unsigned long long fu = from[zi][k]; fromq[zi][k] = fu; if (k) fromq[zi][k] += fromq[zi][k - 1]; } } for (unsigned long long fu = 0; fu < n; ++fu) { unsigned long long size = to[fu].size(); sum += 1ull * (size - 1) * (size) / 2 * A * fu; for (unsigned long long j = 0; j < size; ++j) { unsigned long long zi1 = to[fu][j]; sum += 1ull * B * ((size - 1) - (j + 1) + 1) * zi1; sum += 1ull * C * (toq[fu][size - 1] - toq[fu][j]); } } for (unsigned long long zi = 0; zi < n; ++zi) { unsigned long long size = from[zi].size(); sum += 1ull * (size - 1) * (size) / 2 * C * zi; for (unsigned long long j = 0; j < size; ++j) { unsigned long long fu1 = from[zi][j]; sum += 1ull * A * ((size - 1) - (j + 1) + 1) * fu1; sum += 1ull * B * (fromq[zi][size - 1] - fromq[zi][j]); } } for (unsigned long long zi = 0; zi < n; ++zi) { unsigned long long size1 = to[zi].size(), size2 = from[zi].size(); sum += 1ull * B * (size1) * (size2)*zi; for (unsigned long long j = 0; j < size1; ++j) { unsigned long long sun = to[zi][j]; sum += 1ull * C * sun * size2; if (size2) sum += 1ull * A * fromq[zi][size2 - 1]; for (unsigned long long k = 0; k < size2; ++k) { unsigned long long fu = from[zi][k]; } } } for (unsigned long long fu = 0; fu < n; ++fu) { unsigned long long size = to[fu].size(); for (unsigned long long j = 0; j < size; ++j) vis[to[fu][j]] = 1; for (unsigned long long j = 0; j < size; ++j) { unsigned long long zi = to[fu][j]; unsigned long long sizez = to[zi].size(); for (unsigned long long k = 0; k < sizez; ++k) { unsigned long long sun = to[zi][k]; if (vis[sun]) sum -= (1ull * A * fu + 1ull * B * zi + 1ull * C * sun); } } for (unsigned long long j = 0; j < size; ++j) vis[to[fu][j]] = 0; } cout << sum; return 0; } |
#include <bits/stdc++.h> using namespace std; double pi = 3.1415926536; int main() { int n; cin >> n; int r[n]; for (int i = 0; i < n; i++) cin >> r[i]; double area = 0; sort(r, r + n); for (int i = n - 1; i >= 0; i -= 2) { if (i > 0) area += (r[i] * r[i] - r[i - 1] * r[i - 1]); else area += r[0] * r[0]; } area *= pi; printf( %0.10lf , area); return 0; } |
// megafunction wizard: %In-System Sources and Probes%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsource_probe
// ============================================================
// File Name: hps_reset.v
// Megafunction Name(s):
// altsource_probe
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Internal Build 108 07/09/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module hps_reset (
probe,
source_clk,
source);
input probe;
input source_clk;
output [2:0] source;
wire [2:0] sub_wire0;
wire [2:0] source = sub_wire0[2:0];
altsource_probe altsource_probe_component (
.probe (probe),
.source_clk (source_clk),
.source (sub_wire0)
// synopsys translate_off
,
.clrn (),
.ena (),
.ir_in (),
.ir_out (),
.jtag_state_cdr (),
.jtag_state_cir (),
.jtag_state_e1dr (),
.jtag_state_sdr (),
.jtag_state_tlr (),
.jtag_state_udr (),
.jtag_state_uir (),
.raw_tck (),
.source_ena (),
.tdi (),
.tdo (),
.usr1 ()
// synopsys translate_on
);
defparam
altsource_probe_component.enable_metastability = "YES",
altsource_probe_component.instance_id = "RST",
altsource_probe_component.probe_width = 0,
altsource_probe_component.sld_auto_instance_index = "YES",
altsource_probe_component.sld_instance_index = 0,
altsource_probe_component.source_initial_value = " 0",
altsource_probe_component.source_width = 3;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ENABLE_METASTABILITY STRING "YES"
// Retrieval info: CONSTANT: INSTANCE_ID STRING "RST"
// Retrieval info: CONSTANT: PROBE_WIDTH NUMERIC "0"
// Retrieval info: CONSTANT: SLD_AUTO_INSTANCE_INDEX STRING "YES"
// Retrieval info: CONSTANT: SLD_INSTANCE_INDEX NUMERIC "0"
// Retrieval info: CONSTANT: SOURCE_INITIAL_VALUE STRING " 0"
// Retrieval info: CONSTANT: SOURCE_WIDTH NUMERIC "3"
// Retrieval info: USED_PORT: probe 0 0 0 0 INPUT NODEFVAL "probe"
// Retrieval info: USED_PORT: source 0 0 3 0 OUTPUT NODEFVAL "source[2..0]"
// Retrieval info: USED_PORT: source_clk 0 0 0 0 INPUT NODEFVAL "source_clk"
// Retrieval info: CONNECT: @probe 0 0 0 0 probe 0 0 0 0
// Retrieval info: CONNECT: @source_clk 0 0 0 0 source_clk 0 0 0 0
// Retrieval info: CONNECT: source 0 0 3 0 @source 0 0 3 0
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; const int N = 1e2 + 5; const int MOD = 1e9 + 7; long long cnt[N], x; int n, tmp; vector<vector<long long> > matMul(vector<vector<long long> > &A, vector<vector<long long> > &B) { vector<vector<long long> > C(N, vector<long long>(N, 0)); for (int i = 0; i < N; i++) { for (int j = 0; j < N; j++) { for (int k = 0; k < N; k++) { C[i][j] = (C[i][j] + (A[i][k] * B[k][j]) % MOD) % MOD; } } } return C; } vector<vector<long long> > matPow(vector<vector<long long> > &A, int b) { if (b == 1) return A; vector<vector<long long> > ans = matPow(A, b >> 1); ans = matMul(ans, ans); if (b & 1) ans = matMul(ans, A); return ans; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> x; for (int i = 0; i < n; i++) { cin >> tmp; cnt[tmp]++; } if (x == 0) { cout << 1 n ; return 0; } vector<vector<long long> > res(N, vector<long long>(N, 0)); for (int i = 1; i <= 100; i++) { res[0][i - 1] = cnt[i]; if (i < 100) res[i][i - 1] = 1; } res[0][100] = 1; res[100][100] = 1; res = matPow(res, x); long long ans = (res[0][0] + res[0][100]) % MOD; cout << ans << n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND4BB_BLACKBOX_V
`define SKY130_FD_SC_HS__NAND4BB_BLACKBOX_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nand4bb (
Y ,
A_N,
B_N,
C ,
D
);
output Y ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND4BB_BLACKBOX_V
|
// bsg_barrier
//
// Light-weight configurable wire/logic efficient barrier.
//
// This barrier works with any nearest-neighbor connected topology (e.g., chain, torus, mesh, ruche)
// with bidirectional links.
//
// This allows all of the node hardware to be identical, but configured according into a number
// of subgraphs each capable of doing an independent barrier.
//
// Each node will have a local node input (Pi) and output (Po), and then a bunch of
// connections to neighbor links. In the normal state, Pi and Po match. To enter the barrier,
// a node will flip the Pi bit (i.e. via XOR). Each node has a bitmask of incoming links that
// must all match the new barrier value before the output link outputs the barrier value.
// The barrier value propagates through the network until you get to the root node. The root node
// completes the barrier, usually pulling in links from every direction, going into a special flop
// which is the barrier root. Then the barrier root is broadcast across the reverse links specified
// by the incoming link list, eventually setting all of the Po links. As soon as a node receives the
// broadcast, it flips its "sense bit" which says whether a 1 or 0 is the new barrier target value.
//
// In a RISC-V based system, the approach would be
//
// <setup>:
//
// mtcsr BARCFG, 8'b <this node's output id selector> 24'b <this node's input bitmask>
//
// <execution>:
//
// memory fence # if needed, stall until all memory operations done
// barsend # flip Pi bit (bit 1) of BAR csr (note: Po bit is mapped to bit 2 of the register)
// barreceive # stall in decode until Pi==Po
//
// Here is an example barrier for a Ruche factor 3 topology (you would configure the letters on the left of
// the -> as the input mask and the letter on the right as the output direction). Note R is the "Root".
//
// 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15.
// P->E P->E P->E PW->E PW->E PW->E PW->e PWwE->S PWEe->S PW->w PE->W PE->W PE->W P->W P->W P->W 0
// P->E P->E P->E PW->E PW->E PW->E PW->e NPWwE->S NPWEe->S PW->w PE->W PE->W PE->W P->W P->W P->W 1
// P->E P->E P->E PW->E PW->E PW->E PW->e NPWwE->S NPWEe->S PW->w PE->W PE->W PE->W P->W P->W P->W 2
// P->E P->E P->E PW->E PW->E PW->E PW->e NPWwE->e NPWEwe->S PW->w PE->W PE->W PE->W P->W P->W P->W 3
//
// P->E P->E P->E PW->E PW->E PW->E PW->e SPWeE->e NSPWEwe->R PW->w PE->W PE->W PE->W P->W P->W P->W 4
// P->E P->E P->E PW->E PW->E PW->E PW->e SPWwE->N SPWEe->N PW->w PE->W PE->W PE->W P->W P->W P->W 5
// P->E P->E P->E PW->E PW->E PW->E PW->e SPWwE->N SPWEe->N PW->w PE->W PE->W PE->W P->W P->W P->W 6
// P->E P->E P->E PW->E PW->E PW->E PW->e PWwE->N PWEe->N PW->w PE->W PE->W PE->W P->W P->W P->W 7
//
//
// Context switching. The barrier is context switchable. To context switch the barrier, you interrupt all of the relevant tiles
// and wait long enough for any successful barrier to fully propagate. At this point, using BAR CSR, you can determine if you are either barrier-completed
// (Pi = Po) for all tiles or barrier in progress (Pi != Po for some subset of nodes.) For barrier in progress, we can record all of the nodes
// that have barrier in progress, and then reset the corresponding Pi bit to clear the in progress barrier.
//
module bsg_barrier
#(`BSG_INV_PARAM(dirs_p),lg_dirs_lp=`BSG_SAFE_CLOG2(dirs_p+1))
(
input clk_i
,input reset_i
// to remote nodes
,input [dirs_p-1:0] data_i // late
,output [dirs_p-1:0] data_o // early-ish
//
// control of the barrier:
//
// which inputs we will gather from
// and which outputs we send the gather output to
// and for the broadcast phase, the opposite.
//
// usually comes from a CSR (or bsg_tag)
//
,input [dirs_p-1:0] src_r_i
,input [lg_dirs_lp-1:0] dest_r_i
);
wire [dirs_p:0] data_r;
wire activate_n;
wire data_broadcast_in = data_r[dest_r_i];
wire sense_n, sense_r;
wire gather_and = & (~src_r_i | data_r[dirs_p-1:0]); // true if all selected bits are set to 1
wire gather_or = | (src_r_i & data_r[dirs_p-1:0]); // false if all selected bits are set to 0
// the barrier should go forward, based on the sense bit, if we are either all 0 or all 1.
wire gather_out = sense_r ? gather_or : gather_and;
//
// flip sense bit if we are receiving the incoming broadcast
// we are relying on the P bit still being high at the leaves
// sense_r broadcast_in sense_n
// 0 0 0
// 0 1 1
// 1 1 1
// 1 0 0
// if we see a transition on data_broadcast_in, then we have completed the barrier
assign sense_n = data_broadcast_in;
bsg_dff_reset #(.width_p(dirs_p+2)) dff
(.clk_i(clk_i)
,.reset_i(reset_i)
,.data_i({activate_n, data_i[dirs_p-1:0], sense_n})
,.data_o({data_r[dirs_p], data_r[dirs_p-1:0], sense_r})
);
// this is simply a matter of propagating the value in question
wire [dirs_p-1:0] data_broadcast_out = { dirs_p { data_broadcast_in } } & src_r_i;
// here we propagate the gather_out value, either to network outputs, or to the local activate reg (at the root of the broadcast)
wire [dirs_p:0] dest_decode = 1 << (dest_r_i);
wire [dirs_p:0] data_gather_out = dest_decode & { (dirs_p+1) { gather_out } };
assign data_o = data_broadcast_out | data_gather_out[dirs_p-1:0];
assign activate_n = data_gather_out[dirs_p];
localparam debug_p = 0;
if (debug_p)
always @(negedge clk_i)
$display("%d: %m %b %b %b %b %b %b", $time, gather_and, gather_or, gather_out, sense_n, data_i, data_o);
endmodule
`BSG_ABSTRACT_MODULE(bsg_barrier);
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__MUX4_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__MUX4_PP_BLACKBOX_V
/**
* mux4: 4-input multiplexer.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__mux4 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__MUX4_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; #pragma comment(linker, /STACK:1024000000,1024000000 ) const double pi = acos(-1.0), eps = 1e-8; const int maxm = 1100000, inf = 0x3f3f3f3f; bool f[maxm]; vector<int> v[maxm]; int top, st[maxm]; int a[maxm]; void dfs(int x, int pre) { f[x] = true; int i; a[x] ^= 1; st[top++] = x; for (i = 0; i < v[x].size(); i++) { if (f[v[x][i]] == false) { dfs(v[x][i], x); st[top++] = x; a[x] ^= 1; } } if (a[x] != 0 && pre != -1) { st[top++] = pre; a[pre] ^= 1; st[top++] = x; a[x] ^= 1; } } int main() { int n, m, i, x, y, begin; while (scanf( %d%d , &n, &m) == 2) { for (i = 1; i <= n; i++) v[i].clear(); while (m--) { scanf( %d%d , &x, &y); v[x].push_back(y); v[y].push_back(x); } for (i = 1; i <= n; i++) { scanf( %d , &a[i]); f[i] = false; } top = 0; for (i = 1; i <= n; i++) { if (a[i] == 1) { dfs(i, -1); begin = i; break; } } if (i == n + 1) { printf( 0 n ); continue; } for (i = begin + 1; i <= n; i++) { if (a[i] != 0) { printf( -1 n ); break; } } if (i <= n) continue; if (a[begin] == 1) begin = 1; else begin = 0; printf( %d n , top - begin); for (i = begin; i < top; i++) { printf( %d , st[i]); if (i == top - 1) printf( n ); else printf( ); } } return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [7:0] crc;
reg [223:0] sum;
wire [255:0] mglehy = {32{~crc}};
wire [215:0] drricx = {27{crc}};
wire [15:0] apqrli = {2{~crc}};
wire [2:0] szlfpf = crc[2:0];
wire [15:0] dzosui = {2{crc}};
wire [31:0] zndrba = {16{crc[1:0]}};
wire [223:0] bxiouf;
vliw vliw (
// Outputs
.bxiouf (bxiouf),
// Inputs
.mglehy (mglehy[255:0]),
.drricx (drricx[215:0]),
.apqrli (apqrli[15:0]),
.szlfpf (szlfpf[2:0]),
.dzosui (dzosui[15:0]),
.zndrba (zndrba[31:0]));
always @ (posedge clk) begin
cyc <= cyc + 1;
crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
if (cyc==0) begin
// Setup
crc <= 8'hed;
sum <= 224'h0;
end
else if (cyc<90) begin
//$write("[%0t] cyc==%0d BXI=%x\n",$time, cyc, bxiouf);
sum <= {sum[222:0],sum[223]} ^ bxiouf;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%b %x\n",$time, cyc, crc, sum);
if (crc !== 8'b01110000) $stop;
if (sum !== 224'h1fdff998855c3c38d467e28124847831f9ad6d4a09f2801098f032a8) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module vliw (
input[255:0] mglehy,
input[215:0] drricx,
input[15:0] apqrli,
input[2:0] szlfpf,
input[15:0] dzosui,
input[31:0] zndrba,
output [223:0] bxiouf
);
wire [463:0] zhknfc = ({29{~apqrli}} & {mglehy, drricx[215:8]})
| ({29{apqrli}} & {mglehy[247:0], drricx});
wire [335:0] umntwz = ({21{~dzosui}} & zhknfc[463:128])
| ({21{dzosui}} & zhknfc[335:0]);
wire [335:0] viuvoc = umntwz << {szlfpf, 4'b0000};
wire [223:0] rzyeut = viuvoc[335:112];
wire [223:0] bxiouf = {rzyeut[7:0],
rzyeut[15:8],
rzyeut[23:16],
rzyeut[31:24],
rzyeut[39:32],
rzyeut[47:40],
rzyeut[55:48],
rzyeut[63:56],
rzyeut[71:64],
rzyeut[79:72],
rzyeut[87:80],
rzyeut[95:88],
rzyeut[103:96],
rzyeut[111:104],
rzyeut[119:112],
rzyeut[127:120],
rzyeut[135:128],
rzyeut[143:136],
rzyeut[151:144],
rzyeut[159:152],
rzyeut[167:160],
rzyeut[175:168],
rzyeut[183:176],
rzyeut[191:184],
rzyeut[199:192],
rzyeut[207:200],
rzyeut[215:208],
rzyeut[223:216]};
endmodule
|
#include <iostream> using namespace std; typedef long long ll; int main() { int t; cin >> t; while (t--) { ll n, m, x; cin >> n >> m >> x; x--; ll j = x / n, i = x % n; cout << i * m + j + 1 << n ; } cin.ignore(2); return 0; } |
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_360_64.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.0.2 Build 153 07/15/2015 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_360_64 (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
q);
input aclr;
input clock;
input [359:0] data;
input rdreq;
input wrreq;
output empty;
output [359:0] q;
wire sub_wire0;
wire [359:0] sub_wire1;
wire empty = sub_wire0;
wire [359:0] q = sub_wire1[359:0];
scfifo scfifo_component (
.aclr (aclr),
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.empty (sub_wire0),
.q (sub_wire1),
.almost_empty (),
.almost_full (),
.full (),
.sclr (),
.usedw ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_numwords = 64,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 360,
scfifo_component.lpm_widthu = 6,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "64"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "0"
// Retrieval info: PRIVATE: Width NUMERIC "360"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "360"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "64"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "360"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "6"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 360 0 INPUT NODEFVAL "data[359..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: q 0 0 360 0 OUTPUT NODEFVAL "q[359..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 360 0 data 0 0 360 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: q 0 0 360 0 @q 0 0 360 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_360_64.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_360_64.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_360_64.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_360_64.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_360_64_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_360_64_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; long long DP[100005][25], arr[100005], freq[100005], l = 1, r, ans; void alter_range(long long l1, long long r1) { while (l1 < l) { l--; ans += freq[arr[l]]++; } while (r < r1) { r++; ans += freq[arr[r]]++; } while (l < l1) { ans -= --freq[arr[l]]; l++; } while (r1 < r) { ans -= --freq[arr[r]]; r--; } } void make_layer(long long layer, long long l1, long long r1, long long a, long long b) { if (l1 > r1) return; long long i, j, mid = (l1 + r1) >> 1, &curr = DP[mid][layer], best = mid, better; for (i = a; i <= min(b, mid); i++) { alter_range(i, mid); better = DP[i - 1][layer - 1] + ans; if (curr > better) { curr = better; best = i; } } make_layer(layer, l1, mid - 1, a, best); make_layer(layer, mid + 1, r1, best, b); } int main() { long long i, j, n, k; scanf( %lld %lld , &n, &k); for (i = 1; i <= n; i++) scanf( %lld , &arr[i]); for (i = 0; i <= n; i++) for (j = 0; j <= k; j++) DP[i][j] = 1e18; DP[0][0] = 0; for (i = 1; i <= k; i++) make_layer(i, 1, n, 1, n); printf( %lld n , DP[n][k]); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long N = 3E5 + 7, mod = 998244353; long long n, a[N], inv[N], ans; signed main() { scanf( %lld , &n); for (long long i = 1; i <= n << 1; i++) scanf( %lld , &a[i]); sort(a + 1, a + 2 * n + 1); for (long long i = 1; i <= n; i++) ans = (ans - a[i] + mod) % mod; for (long long i = n + 1; i <= n << 1; i++) ans = (ans + a[i]) % mod; for (long long i = n << 1; i >= n + 1; i--) ans = ans * i % mod; inv[1] = 1; for (long long i = 2; i <= n; i++) { inv[i] = 1ll * inv[mod % i] * (mod - mod / i) % mod; ans = 1ll * ans * inv[i] % mod; } printf( %lld n , ans); return 0; } |
//-----------------------------------------------------
// Design Name : hw1_A
// File Name : hw1_A.v
// Function : This program designs a single mux-based bus.
// Coder : hydai
//-----------------------------------------------------
module hw1_A (
input [15:0] data,
input [6:0] control,
input clk,
input rst_n,
output reg [15:0] R0,
output reg [15:0] R1,
output reg [15:0] R2,
output reg [15:0] R3
);
reg [15:0] tmpData;
reg [15:0] T0, T1, T2, T3;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
R0 <= 0;
R1 <= 0;
R2 <= 0;
R3 <= 0;
end else begin
R0 <= (control[0])?(tmpData):R0;
R1 <= (control[1])?(tmpData):R1;
R2 <= (control[2])?(tmpData):R2;
R3 <= (control[3])?(tmpData):R3;
end // end of if-else block
end // end of always
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
tmpData <= 0;
end // end of if (!rst_n)
case (control[6:4])
3'b000: tmpData <= R0;
3'b001: tmpData <= R1;
3'b010: tmpData <= R2;
3'b011: tmpData <= R3;
3'b111: tmpData <= data;
default: tmpData <= 0;
endcase // end of case (control)
end // end of always
endmodule // endmodule of hw1_A
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 2; int ar[N], ar1[N]; signed main() { ios::sync_with_stdio(0); cin.tie(0); int n, i, j, k, l, r; long long sum; cin >> n >> sum; if (sum < 1ll * n * (n + 1) / 2) { cout << -1; return 0; } for (i = 1; i <= n; i++) { ar[i] = i; ar1[i] = i; } l = 1; r = n; sum -= 1ll * n * (n + 1) / 2; while (sum && l < r) { if (sum > r - l) { sum -= (r - l); swap(ar1[l], ar1[r]); l++; r--; } else { swap(ar1[r], ar1[r - sum]); break; } } sum = 0; for (i = 1; i <= n; i++) { sum += max(ar[i], ar1[i]); } cout << sum << n ; for (i = 1; i <= n; i++) { cout << ar[i] << ; } cout << n ; for (i = 1; i <= n; i++) { cout << ar1[i] << ; } } |
#include <bits/stdc++.h> using namespace std; int n, a[100009], x[100009], h[100009], id[100009], seg[400009]; void upd(int pos, int l, int r, int pp, int v) { if (l == r) { seg[pos] = v; return; } int m = (l + r) / 2; if (m >= pp) upd(2 * pos + 1, l, m, pp, v); else upd(2 * pos + 2, m + 1, r, pp, v); seg[pos] = max(seg[2 * pos + 1], seg[2 * pos + 2]); } int qu(int pos, int l, int r, int b, int e) { if (b <= l && r <= e) return seg[pos]; int m = (l + r) / 2; int r1 = 0, r2 = 0; if (m >= b) r1 = qu(2 * pos + 1, l, m, b, e); if (m < e) r2 = qu(2 * pos + 2, m + 1, r, b, e); return max(r1, r2); } int ans[100009]; void bs(int i, int l, int r) { int m; int o = x[i] + h[i] - 1; while (r - l > 1) { m = (l + r) / 2; if (o < x[m]) r = m; else l = m; } if (l == i) ans[id[i]] = i; else ans[id[i]] = qu(0, 0, n - 1, i + 1, l); upd(0, 0, n - 1, i, ans[id[i]]); ans[id[i]] -= i; ans[id[i]]++; } pair<int, pair<int, int> > p[100009]; int main() { cin >> n; for (int i = 0; i < n; i++) { cin >> x[i] >> h[i]; p[i] = {x[i], {h[i], i}}; } sort(p, p + n); for (int i = 0; i < n; i++) { x[i] = p[i].first; h[i] = p[i].second.first; id[i] = p[i].second.second; } ans[id[n - 1]] = 1; upd(0, 0, n - 1, n - 1, n - 1); for (int i = n - 2; i >= 0; i--) { bs(i, i, n); } for (int i = 0; i < n; i++) cout << ans[i] << ; } |
#include <bits/stdc++.h> std::string a, b; std::string cal(std::string a) { if (a.length() % 2) return a; std::string s1 = cal(a.substr(0, a.length() / 2)); std::string s2 = cal(a.substr(a.length() / 2, a.length())); if (s1 < s2) return s1 + s2; return s2 + s1; } int main() { std::cin >> a >> b; a = cal(a); b = cal(b); if (a == b) puts( YES ); else puts( NO ); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 5010; struct SA { bool _t[N * 2]; int _s[N * 2], _sa[N * 2], _c[N * 2], x[N], _p[N], _q[N * 2], hei[N], r[N]; int operator[](int i) { return _sa[i]; } void build(int *s, int n, int m) { memcpy(_s, s, sizeof(int) * n); sais(_s, _sa, _p, _q, _t, _c, n, m); mkhei(n); } void mkhei(int n) { for (int i = 0; i < int(n); i++) r[_sa[i]] = i; hei[0] = 0; for (int i = 0; i < int(n); i++) if (r[i]) { int ans = i > 0 ? max(hei[r[i - 1]] - 1, 0) : 0; while (_s[i + ans] == _s[_sa[r[i] - 1] + ans]) ans++; hei[r[i]] = ans; } } void sais(int *s, int *sa, int *p, int *q, bool *t, int *c, int n, int z) { bool uniq = t[n - 1] = true, neq; int nn = 0, nmxz = -1, *nsa = sa + n, *ns = s + n, lst = -1; memset((c), 0, z * sizeof(*(c))); for (int i = 0; i < int(n); i++) uniq &= ++c[s[i]] < 2; for (int i = 0; i < int(z - 1); i++) c[i + 1] += c[i]; if (uniq) { for (int i = 0; i < int(n); i++) sa[--c[s[i]]] = i; return; } for (int i = n - 2; i >= 0; i--) t[i] = (s[i] == s[i + 1] ? t[i + 1] : s[i] < s[i + 1]); memset((sa), 0, n * sizeof(*(sa))); memcpy(x, c, sizeof(int) * z); for (int i = (1); i <= int(n - 1); i++) if (t[i] && !t[i - 1]) sa[--x[s[i]]] = p[q[i] = nn++] = i; memcpy(x + 1, c, sizeof(int) * (z - 1)); for (int i = 0; i < int(n); i++) if (sa[i] && !t[sa[i] - 1]) sa[x[s[sa[i] - 1]]++] = sa[i] - 1; memcpy(x, c, sizeof(int) * z); for (int i = n - 1; i >= 0; i--) if (sa[i] && t[sa[i] - 1]) sa[--x[s[sa[i] - 1]]] = sa[i] - 1; ; for (int i = 0; i < int(n); i++) if (sa[i] && t[sa[i]] && !t[sa[i] - 1]) { neq = lst < 0 || memcmp(s + sa[i], s + lst, (p[q[sa[i]] + 1] - sa[i]) * sizeof(int)); ns[q[lst = sa[i]]] = nmxz += neq; } sais(ns, nsa, p + nn, q + n, t + n, c + z, nn, nmxz + 1); memset((sa), 0, n * sizeof(*(sa))); memcpy(x, c, sizeof(int) * z); for (int i = nn - 1; i >= 0; i--) sa[--x[s[p[nsa[i]]]]] = p[nsa[i]]; memcpy(x + 1, c, sizeof(int) * (z - 1)); for (int i = 0; i < int(n); i++) if (sa[i] && !t[sa[i] - 1]) sa[x[s[sa[i] - 1]]++] = sa[i] - 1; memcpy(x, c, sizeof(int) * z); for (int i = n - 1; i >= 0; i--) if (sa[i] && t[sa[i] - 1]) sa[--x[s[sa[i] - 1]]] = sa[i] - 1; ; } } sa; int H[N], SA[N]; void suffix_array(int *ip, int len) { ip[len++] = 0; sa.build(ip, len, 128); for (int i = 0; i < len; i++) { H[i] = sa.hei[i + 1]; SA[i] = sa._sa[i + 1]; } } int n, k, v[N]; char c[N]; void init() { scanf( %s , c); scanf( %d , &k); n = strlen(c); for (int i = 0; i < n; i++) v[i] = c[i] - a + 1; v[n] = 0; suffix_array(v, n); } bool gt[N][N], pp[N][N]; bool go(int l, int r) { if (l > r) return true; if (gt[l][r]) return pp[l][r]; gt[l][r] = true; if (c[l] != c[r]) return false; return pp[l][r] = go(l + 2, r - 2); } void solve() { for (int i = 0; i < n; i++) for (int j = i; j < n; j++) go(i, j); for (int i = 0; i < n; i++) for (int j = H[i]; SA[i] + j < n; j++) { if (!pp[SA[i]][SA[i] + j]) continue; int tlen = j + 1; for (int ii = i; ii < n; ii++) { if (ii > i) tlen = min(tlen, H[ii]); if (tlen < j + 1) break; k--; if (k == 0) { for (int u = SA[i]; u <= SA[i] + j; u++) putchar(c[u]); puts( ); exit(0); } } } } int main() { init(); solve(); } |
module step_ex_ld(clk, rst_, ena_, rdy_,
mem_re_, abus, dbus,
r1_dout, r0_din, r0_we_);
input clk;
input rst_;
input ena_;
output rdy_;
output mem_re_;
output[7:0] abus;
input[7:0] dbus;
input[7:0] r1_dout;
output[7:0] r0_din;
output r0_we_;
reg rdy_en;
assign rdy_ = rdy_en ? 1'b0 : 1'bZ;
reg mem_re_en;
assign mem_re_ = mem_re_en ? 1'b0 : 1'bZ;
assign abus = mem_re_en ? r1_dout : 8'bZ;
assign r0_din = mem_re_en ? dbus : 8'bZ;
reg r0_we_en;
assign r0_we_ = r0_we_en ? 1'b0 : 1'bZ;
reg[1:0] state;
always @(negedge rst_ or posedge clk)
if(!rst_) begin
rdy_en <= 0;
mem_re_en <= 0;
r0_we_en <= 0;
state <= 0;
end else begin
/*
State 0: ena_=0 state=00
rdy_en=0 mem_re_en=1 r0_we_en=0 state=01
State 1: ena_=1 state=01
rdy_en=0 mem_re_en=1 r0_we_en=1 state=10
State 2: ena_=1 state=10
rdy_en=1 mem_re_en=0 r0_we_en=0 state=00
State 3: ena_=1 state=00
rdy_en=0 mem_re_en=0 r0_we_en=0 state=00
*/
rdy_en <= state[1];
mem_re_en <= state[0] | ~ena_;
r0_we_en <= state[0];
state <= {state[0], ~ena_};
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND2B_BLACKBOX_V
`define SKY130_FD_SC_HDLL__NAND2B_BLACKBOX_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__nand2b (
Y ,
A_N,
B
);
output Y ;
input A_N;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND2B_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; ofstream fo( test.out ); ifstream fi( test.inp ); int n, m, k, dem; int x[200005], y[200005]; int main() { long long a; cin >> a; for (long long i = 2; i * i <= a; i++) { while (a % (i * i) == 0) a /= i; } cout << a; } |
// File: mm_vgasys.v
// Generated by MyHDL 0.9dev
// Date: Sun Mar 8 19:46:55 2015
`timescale 1ns/1ns
module mm_vgasys (
clock,
reset,
vselect,
hsync,
vsync,
red,
green,
blue,
pxlen,
active
);
input clock;
input reset;
input vselect;
output hsync;
reg hsync;
output vsync;
reg vsync;
output [9:0] red;
wire [9:0] red;
output [9:0] green;
wire [9:0] green;
output [9:0] blue;
wire [9:0] blue;
output pxlen;
reg pxlen;
output active;
reg active;
reg [2:0] gvga_vga_state;
reg [19:0] gvga_vcd;
reg [9:0] gvga_hpxl;
reg [8:0] gvga_vpxl;
reg [29:0] gvga_vmem_red;
reg [10:0] gvga_hcd;
reg [29:0] gvga_vmem_blue;
reg [29:0] gvga_vmem_green;
reg [29:0] gbar_pval;
reg [31:0] gbar_ssel;
always @(posedge clock) begin: MM_VGASYS_GVGA_RTL_SYNC
reg signed [3-1:0] xcnt;
reg [11-1:0] hcnt;
reg [20-1:0] vcnt;
if (reset == 0) begin
gvga_vpxl <= 0;
gvga_vcd <= 0;
vsync <= 0;
gvga_hpxl <= 0;
hsync <= 0;
pxlen <= 0;
gvga_hcd <= 0;
hcnt = 0;
vcnt = 0;
xcnt = 0;
end
else begin
hcnt = (hcnt + 1);
vcnt = (vcnt + 1);
if ((vcnt == 833333)) begin
vcnt = 0;
hcnt = 0;
end
else if ((vcnt > 768000)) begin
hcnt = (1600 - 1);
end
else if ((hcnt >= 1600)) begin
hcnt = 0;
end
xcnt = (xcnt + 1);
if ((hcnt == 1)) begin
xcnt = 1;
end
else if ((xcnt == 2)) begin
xcnt = 0;
end
if (((xcnt == 0) && (hcnt <= 1250))) begin
pxlen <= 1'b1;
end
else begin
pxlen <= 1'b0;
end
if (((hcnt >= (1250 + 50)) && (hcnt < ((1250 + 50) + 200)))) begin
hsync <= 1'b0;
end
else begin
hsync <= 1'b1;
end
if (((vcnt >= (768000 + 17000)) && (vcnt < ((768000 + 17000) + 3200)))) begin
vsync <= 1'b0;
end
else begin
vsync <= 1'b1;
end
if ((($signed({1'b0, gvga_hpxl}) < (640 - 1)) && (xcnt == 0) && (hcnt <= 1250))) begin
gvga_hpxl <= (gvga_hpxl + 1);
end
else if ((hcnt > (1250 + 50))) begin
gvga_hpxl <= 0;
end
if ((($signed({1'b0, hcnt}) >= (1600 - 1)) && (vcnt < 768000))) begin
gvga_vpxl <= (gvga_vpxl + 1);
end
else if ((vcnt > (768000 + 17000))) begin
gvga_vpxl <= 0;
end
gvga_hcd <= hcnt;
gvga_vcd <= vcnt;
end
end
always @(gvga_vcd, hsync, gvga_hcd, vsync) begin: MM_VGASYS_GVGA_RTL_STATE
if ((!hsync)) begin
gvga_vga_state = 3'b011;
end
else if ((!vsync)) begin
gvga_vga_state = 3'b110;
end
else if ((gvga_hcd < 1250)) begin
gvga_vga_state = 3'b001;
end
else if (((gvga_vcd >= 768000) && (gvga_vcd < (768000 + 17000)))) begin
gvga_vga_state = 3'b101;
end
else if (((gvga_vcd >= (768000 + 17000)) && (gvga_vcd < ((768000 + 17000) + 3200)))) begin
// pass
end
else if (((gvga_vcd >= ((768000 + 17000) + 3200)) && (gvga_vcd < 833333))) begin
gvga_vga_state = 3'b111;
end
else if (((gvga_hcd >= 1250) && (gvga_hcd < (1250 + 50)))) begin
gvga_vga_state = 3'b010;
end
else if (((gvga_hcd >= (1250 + 50)) && (gvga_hcd < ((1250 + 50) + 200)))) begin
// pass
end
else if (((gvga_hcd >= ((1250 + 50) + 200)) && (gvga_hcd < (((1250 + 50) + 200) + 100)))) begin
gvga_vga_state = 3'b100;
end
if ((gvga_hcd < 1250)) begin
active = 1'b1;
end
else begin
active = 1'b0;
end
end
assign red = gvga_vmem_red;
assign green = gvga_vmem_green;
assign blue = gvga_vmem_blue;
always @(gvga_hpxl) begin: MM_VGASYS_GBAR_RTL_PVAL
integer ii;
integer sel;
sel = 0;
for (ii=0; ii<8; ii=ii+1) begin
if (($signed({1'b0, gvga_hpxl}) > (ii * 80))) begin
sel = ii;
end
end
gbar_ssel = sel;
case (sel)
0: gbar_pval = ;
1: gbar_pval = ;
2: gbar_pval = ;
3: gbar_pval = ;
4: gbar_pval = ;
5: gbar_pval = ;
6: gbar_pval = 1023;
default: gbar_pval = 0;
endcase
end
always @(posedge clock) begin: MM_VGASYS_GBAR_RTL_RGB
if (reset == 0) begin
gvga_vmem_blue <= 0;
gvga_vmem_green <= 0;
gvga_vmem_red <= 0;
end
else begin
gvga_vmem_red <= ((gbar_pval >>> 20) & 1023);
gvga_vmem_green <= ((gbar_pval >>> 10) & 1023);
gvga_vmem_blue <= (gbar_pval & 1023);
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> poz[100]; int main() { string s; cin >> s; for (int i(0); i <= 26; i++) poz[i].push_back(-1); for (int i(0); i < s.size(); i++) poz[s[i] - a ].push_back(i); for (int i(0); i <= 26; i++) poz[i].push_back(s.size()); int kmin = s.size(); for (int i(0); i < 26; i++) { int dmax = 0; for (int j(0); j < poz[i].size() - 1; j++) dmax = max(dmax, poz[i][j + 1] - poz[i][j]); kmin = min(kmin, dmax); } cout << kmin; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAPMET1_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__TAPMET1_PP_BLACKBOX_V
/**
* tapmet1: Tap cell with isolated power and ground connections.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__tapmet1 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAPMET1_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; vector<int> a; int main() { string s; cin >> s; int i, l = 0, can = 0, can_too = 0; for (i = 0; i < s.length(); i++) { if (s[i] == @ && can == 0) { can = 1; a.push_back(i); } else if (s[i] == . && can && !can_too) { a.push_back(i); } else if (s[i] == / && can) { can_too = 1; a.push_back(i); } } for (i = 0; i < a.size(); i++) { int ta, tb; if (i == 0) { ta = -1; tb = a[i]; } else { ta = a[i - 1]; tb = a[i]; } if (abs(ta - tb) == 1) { cout << NO << endl; return 0; } for (int j = ta + 1, l = 0; j < tb; j++) { l++; if ((s[j] < a || s[j] > z ) && (s[j] < A || s[j] > Z ) && (s[j] < 0 || s[j] > 9 ) && s[j] != _ ) { cout << NO << endl; return 0; } else if (l > 16) { cout << NO << endl; return 0; } } if (i == a.size() - 1) { ta = a[i]; tb = s.length(); if (abs(ta - tb) == 0) { cout << NO << endl; return 0; } for (int j = ta + 1, l = 0; j < tb; j++) { l++; if ((s[j] < a || s[j] > z ) && (s[j] < A || s[j] > Z ) && (s[j] < 0 || s[j] > 9 ) && s[j] != _ ) { cout << NO << endl; return 0; } else if (l > 16) { cout << NO << endl; return 0; } } } } int px = 0, py = 0; for (i = 0; i < a.size(); i++) { if (s[a[i]] == @ ) { px = a[i]; break; } } for (i = 0; i < a.size(); i++) { if (s[a[i]] == / ) { py = a[i]; break; } } if (abs(py - px - 1) > 32 && px && py) { cout << NO << endl; return 0; } if (a.size() == 0) { cout << NO << endl; return 0; } if (a.size() == 1 && a[0] == s.length() - 1) { cout << NO << endl; return 0; } for (i = 0; i < a.size(); i++) { if (a[i] + 1 == s.length()) { cout << NO << endl; return 0; } } cout << YES << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; map<int, long long> ans, re, now; int n, h[200005], tot, mp[200005], siz[200005], mz[200005], rem[200005], cnt; bool vis[200005]; struct DX { int v, p; } dx[400005]; int gcd(int a, int b) { return b ? gcd(b, a % b) : a; } void add(int u, int v) { dx[tot].p = h[u]; dx[tot].v = v; h[u] = tot++; } void dfs_G(int u, int fx) { siz[u] = 1; rem[++cnt] = u; mz[u] = 0; for (int i = h[u]; ~i; i = dx[i].p) { int v = dx[i].v; if (v == fx || vis[v]) continue; dfs_G(v, u); siz[u] += siz[v]; mz[u] = max(mz[u], siz[v]); } } int fd_G(int u) { cnt = 0; dfs_G(u, u); for (int i = 1; i <= cnt; i++) if (mz[rem[i]] <= siz[u] / 2 && siz[u] - siz[rem[i]] <= siz[u] / 2) return rem[i]; } void dfs(int u, int fx, int gc) { re[gc = gcd(gc, mp[u])]++; for (int i = h[u]; ~i; i = dx[i].p) { int v = dx[i].v; if (v == fx || vis[v]) continue; dfs(v, u, gc); } } void sol(int u) { u = fd_G(u); vis[u] = 1; now[mp[u]] = 1; ans[mp[u]] += 1; for (int i = h[u]; ~i; i = dx[i].p) { int v = dx[i].v; if (vis[v]) continue; dfs(v, 0, mp[u]); for (map<int, long long>::iterator it = now.begin(); it != now.end(); it++) for (map<int, long long>::iterator ti = re.begin(); ti != re.end(); ti++) ans[gcd(it->first, ti->first)] += it->second * ti->second; for (map<int, long long>::iterator ti = re.begin(); ti != re.end(); ti++) now[ti->first] += ti->second; re.clear(); } now.clear(); for (int i = h[u]; ~i; i = dx[i].p) { int v = dx[i].v; if (vis[v]) continue; sol(v); } } int main() { memset(h, -1, sizeof(h)); scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &mp[i]); int a, b; for (int i = 1; i < n; i++) { scanf( %d%d , &a, &b); add(a, b); add(b, a); } sol(1); for (map<int, long long>::iterator it = ans.begin(); it != ans.end(); it++) printf( %d %lld n , it->first, it->second); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; long long tab[200001], min1, odl = -1, wynik, first; cin >> n; cin >> tab[0]; min1 = 0; first = 0; for (int i = 1; i < n; i++) { cin >> tab[i]; if (tab[i] == tab[min1]) { if (odl < i - min1) odl = i - min1; min1 = i; } if (tab[i] < tab[min1]) { min1 = i; first = i; odl = -1; } } if (odl == -1) cout << n * (tab[first] + 1) - 1; else { odl--; int space = n - (min1 - first + 1); if (odl > space) cout << n * tab[first] + odl; else cout << n * tab[first] + space; } } |
// Regression test for bug reported by Niels Moeller on 21-Mar-2015 via
// iverilog-devel mailing list. Extended to cover similar problems. This
// is just testing compiler error recovery.
module test();
integer array[3:0];
integer i1;
always @* begin
for (i1 = 0; i1 < 4; i1 = i1 + 1) begin
array[i1] = undeclared;
end
end
integer i2;
always @* begin
for (i2 = 0; i2 < 4; i2 = i2 + 1) begin
undeclared = array[i2];
end
end
integer i3;
always @* begin
for (i3 = undeclared; i3 < 4; i3 = i3 + 1) begin
array[i3] = i3;
end
end
integer i4;
always @* begin
for (i4 = 0; i4 < undeclared; i4 = i4 + 1) begin
array[i4] = i4;
end
end
integer i5;
always @* begin
for (i5 = 0; i5 < 4; i5 = i5 + undeclared) begin
array[i5] = i5;
end
end
integer i6;
always @* begin
i6 = 0;
while (i6 < undeclared) begin
array[i6] = i6;
i6 = i6 + 1;
end
end
integer i7;
always @* begin
i7 = 0;
while (i7 < 4) begin
array[i7] = undeclared;
i7 = i7 + 1;
end
end
integer i8;
always @* begin
i8 = 0;
repeat (undeclared) begin
array[i8] = i8;
i8 = i8 + 1;
end
end
integer i9;
always @* begin
i9 = 0;
repeat (4) begin
array[i9] = undeclared;
i9 = i9 + 1;
end
end
endmodule
|
`define BLACK_COLOR 8'b00000000
`define WHITE_COLOR 8'b11111111
`define WIDTH 640
`define HEIGHT 480
module Gpu(clk, reset, data_bus, address_bus, w, r, hs, vs, color);
input clk /* verilator clocker*/;
input reset;
input w, r;
inout [15:0] data_bus;
input [7:0] address_bus;
output reg hs, vs;
output reg [7:0] color;
reg [10:0] row;
reg [10:0] line;
reg [7:0] bar;
(* ram_style="block" *)
reg [15:0] sprites[11:0] /* verilator public_flat */;
(* ram_style="block" *)
reg [7:0] tiles[8:0] /* verilator public_flat */;
reg [15:0] data_bus_out;
assign data_bus = r ? data_bus_out : 16'bz;
initial begin
row = 0;
line = 0;
end
task draw_line;
begin
if (row < 16) begin
color <= `BLACK_COLOR;
hs <= 1'b0;
end else if(row < 16 + 96) begin
color <= `BLACK_COLOR;
hs <= 1'b1;
end else if(row < 16 + 96 + 48) begin
color <= `BLACK_COLOR;
hs <= 1'b0;
end else
color <= bar[row % 8];
end endtask
//always @(posedge clk) begin
// bar[row % 8];
//end
always @(posedge clk, posedge reset) begin
if (reset) begin
row <= 0;
line <= 0;
end else begin
row <= row + 1;
if (row == 800) begin
line <= line + 1;
row <= 0;
end
if (line < 10) begin
color <= `BLACK_COLOR;
vs <= 1'b0;
end else if (line < 10 + 2) begin
color <= `BLACK_COLOR;
vs <= 1'b1;
end else if (line < 10 + 2 + 33) begin
color <= `BLACK_COLOR;
vs <= 1'b0;
end else if (line < 10 + 2 + 33 + `HEIGHT) begin
draw_line();
end else begin
line <= 0;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int nsz = 3e5; int n; long long k, mod, a[nsz + 5], b[nsz + 5], ans; map<long long, int> mp; long long inline qpow(long long a, int p) { long long res = 1; for (; p; p >>= 1) { if (p & 1) { res *= a; res %= mod; } a *= a; a %= mod; } return res % mod; } long long inline modify(long long a) { a %= mod; return a < 0 ? a + mod : a; } int main() { ios_base::sync_with_stdio(0); cin >> n >> mod >> k; for (int i = 1; i <= n; ++i) { cin >> a[i]; ++mp[modify(qpow(a[i], 4) - k * a[i] % mod)]; } for (__typeof(mp.begin()) it = mp.begin(); it != mp.end(); ++it) { ans += it->second * (it->second - 1) / 2; } cout << ans << endl; } |
/*
* Zet processor core
* Copyright (C) 2010 Zeus Gomez Marmolejo <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
`include "defines.v"
module zet_core (
input clk,
input rst,
// interrupts
input intr,
output inta,
input nmi,
output nmia,
// interface to wishbone
output [19:0] cpu_adr_o,
input [15:0] iid_dat_i,
input [15:0] cpu_dat_i,
output [15:0] cpu_dat_o,
output cpu_byte_o,
input cpu_block,
output cpu_mem_op,
output cpu_m_io,
output cpu_we_o,
output [19:0] pc // for debugging purposes
);
// Net declarations
wire [`IR_SIZE-1:0] ir;
wire [15:0] off;
wire [15:0] imm;
wire wr_ip0;
wire [15:0] cs;
wire [15:0] ip;
wire of;
wire zf;
wire ifl;
wire iflm;
wire tfl;
wire tflm;
wire iflss;
wire wr_ss;
wire cx_zero;
wire div_exc;
wire [19:0] addr_exec;
wire byte_fetch;
wire byte_exec;
// wire decode - microcode
wire [`MICRO_ADDR_WIDTH-1:0] seq_addr;
wire [3:0] src;
wire [3:0] dst;
wire [3:0] base;
wire [3:0] index;
wire [1:0] seg;
wire end_seq;
wire [2:0] fdec;
wire div;
// wires fetch - decode
wire [7:0] opcode;
wire [7:0] modrm;
wire rep;
wire exec_st;
wire ld_base;
wire [2:0] sop_l;
wire need_modrm;
wire need_off;
wire need_imm;
wire off_size;
wire imm_size;
wire ext_int;
// wires fetch - microcode
wire [15:0] off_l;
wire [15:0] imm_l;
wire [15:0] imm_d;
wire [`IR_SIZE-1:0] rom_ir;
wire [5:0] ftype;
// wires fetch - exec
wire [15:0] imm_f;
// wires and regs for hlt
wire block_or_hlt;
wire hlt_op;
wire hlt_in;
wire hlt_out;
reg hlt_op_old;
reg hlt;
// regs for nmi
reg nmir;
reg nmi_old;
reg nmia_old;
// Module instantiations
zet_fetch fetch (
.clk (clk),
.rst (rst),
// to decode
.opcode (opcode),
.modrm (modrm),
.rep (rep),
.exec_st (exec_st),
.ld_base (ld_base),
.sop_l (sop_l),
// from decode
.need_modrm (need_modrm),
.need_off (need_off),
.need_imm (need_imm),
.off_size (off_size),
.imm_size (imm_size),
.ext_int (ext_int),
.end_seq (end_seq),
// to microcode
.off_l (off_l),
.imm_l (imm_l),
// from microcode
.ftype (ftype),
// to exec
.imm_f (imm_f),
.wr_ip0 (wr_ip0),
// from exec
.cs (cs),
.ip (ip),
.of (of),
.zf (zf),
.iflm (iflm),
.tflm (tflm),
.iflss (iflss),
.cx_zero (cx_zero),
.div_exc (div_exc),
// to wb
.data (cpu_dat_i),
.pc (pc),
.bytefetch (byte_fetch),
.block (block_or_hlt),
.intr (intr),
.nmir (nmir)
);
zet_decode decode (
.clk (clk),
.rst (rst),
.opcode (opcode),
.modrm (modrm),
.rep (rep),
.block (block_or_hlt),
.exec_st (exec_st),
.div_exc (div_exc),
.ld_base (ld_base),
.div (div),
.tfl (tfl),
.tflm (tflm),
.need_modrm (need_modrm),
.need_off (need_off),
.need_imm (need_imm),
.off_size (off_size),
.imm_size (imm_size),
.sop_l (sop_l),
.intr (intr),
.ifl (ifl),
.iflm (iflm),
.inta (inta),
.ext_int (ext_int),
.nmir (nmir),
.nmia (nmia),
.wr_ss (wr_ss),
.iflss (iflss),
.seq_addr (seq_addr),
.src (src),
.dst (dst),
.base (base),
.index (index),
.seg (seg),
.f (fdec),
.end_seq (end_seq)
);
zet_micro_data micro_data (
// from decode
.n_micro (seq_addr),
.off_i (off_l),
.imm_i (imm_l),
.src (src),
.dst (dst),
.base (base),
.index (index),
.seg (seg),
.fdec (fdec),
.div (div),
.end_seq (end_seq),
// to exec
.ir (rom_ir),
.off_o (off),
.imm_o (imm_d)
);
zet_exec exec (
.clk (clk),
.rst (rst),
// from fetch
.ir (ir),
.off (off),
.imm (imm),
.wrip0 (wr_ip0),
// to fetch
.cs (cs),
.ip (ip),
.of (of),
.zf (zf),
.ifl (ifl),
.tfl (tfl),
.cx_zero (cx_zero),
.div_exc (div_exc),
.wr_ss (wr_ss),
// from wb
.memout (iid_dat_i),
.wr_data (cpu_dat_o),
.addr (addr_exec),
.we (cpu_we_o),
.m_io (cpu_m_io),
.byteop (byte_exec),
.block (block_or_hlt)
);
// Assignments
assign cpu_adr_o = exec_st ? addr_exec : pc;
assign cpu_byte_o = exec_st ? byte_exec : byte_fetch;
assign cpu_mem_op = ir[`MEM_OP];
assign ir = exec_st ? rom_ir : `ADD_IP;
assign imm = exec_st ? imm_d : imm_f;
assign ftype = rom_ir[28:23];
assign hlt_op = ((opcode == `OP_HLT) && exec_st);
assign hlt_in = (hlt_op && !hlt_op_old && !hlt_out);
assign hlt_out = (intr & ifl) | nmir;
assign block_or_hlt = cpu_block | hlt | hlt_in;
// Behaviour
always @(posedge clk)
if (rst)
hlt_op_old <= 1'b0;
else
if (hlt_op)
hlt_op_old <= 1'b1;
else
hlt_op_old <= 1'b0;
always @(posedge clk)
if (rst)
hlt <= 1'b0;
else
if (hlt_in)
hlt <= 1'b1;
else if (hlt_out)
hlt <= 1'b0;
always @(posedge clk)
if (rst)
begin
nmir <= 1'b0;
nmi_old <= 1'b0;
nmia_old <= 1'b0;
end
else
begin
nmi_old <= nmi;
nmia_old <= nmia;
if (nmi & ~nmi_old)
nmir <= 1'b1;
else if (nmia_old)
nmir <= 1'b0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c, d; scanf( %i %i %i %i , &a, &b, &c, &d); int sum1 = max(3 * a / 10, a - a / 250 * c); int sum2 = max(3 * b / 10, b - b / 250 * d); if (sum1 > sum2) { printf( Misha n ); } else if (sum1 == sum2) { printf( Tie n ); } else { printf( Vasya n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; const int MAX_N = 1e5 + 50; int w[MAX_N]; void solve() { int n, m; cin >> n >> m; long long ret = ((long long)w[n] + (long long)w[m] - 1LL) * 2LL; cout << ret % MOD << n ; } void precal() { w[0] = 0; w[1] = 1; w[2] = 2; for (int i = (3); i < (MAX_N); ++i) { w[i] = w[i - 1] + w[i - 2]; w[i] %= MOD; } } signed main(void) { ios_base::sync_with_stdio(false); cin.tie(0); precal(); solve(); return 0; } |
Require Import Fiat.Common
Fiat.Computation
Fiat.ADT.ADTSig
Fiat.ADT.Core
Fiat.ADTRefinement.Core Fiat.ADTRefinement.SetoidMorphisms
Fiat.ADTRefinement.GeneralRefinements.
(* A generic refinement and honing tactic for switching the
representation of an ADT. *)
Section HoneRepresentation.
Variable oldRep : Type. (* The old representation type. *)
Variable newRep : Type. (* The new representation type. *)
(* The abstraction relation between old and new representations. *)
Variable AbsR : oldRep -> newRep -> Prop.
Local Infix "≃" := (AbsR) (at level 70).
(* When switching representations, we can always build a default
implementation (computation?) for the methods of an ADT by
using the old methods. *)
Fixpoint absMethod'
(dom : list Type)
(cod : option Type)
: (oldRep -> methodType' oldRep dom cod)
-> newRep -> (methodType' newRep dom cod) :=
match dom return
(oldRep -> methodType' oldRep dom cod)
-> newRep -> (methodType' newRep dom cod)
with
| nil =>
match cod return
(oldRep -> methodType' oldRep [] cod)
-> newRep -> (methodType' newRep [] cod)
with
| Some cod' =>
fun oldMethod nr =>
{nr' | forall or,
or ≃ nr ->
exists or',
(oldMethod or) ↝ or' /\
fst or' ≃ fst nr' /\ snd or' = snd nr'}%comp
| None =>
fun oldMethod nr =>
{nr' | forall or,
or ≃ nr ->
exists or',
(oldMethod or) ↝ or' /\ or' ≃ nr'}%comp
end
| cons d dom' =>
fun oldMethod nr t =>
absMethod' dom' cod (fun or => oldMethod or t) nr
end.
Definition absMethod
(dom : list Type)
(cod : option Type)
(oldMethod : methodType oldRep dom cod)
: methodType newRep dom cod :=
absMethod' dom cod oldMethod.
Lemma refine_absMethod
(dom : list Type)
(cod : option Type)
(oldMethod : methodType oldRep dom cod)
: @refineMethod oldRep newRep AbsR _ _
oldMethod
(absMethod oldMethod).
Proof.
induction dom.
- simpl in *; unfold refineMethod, refineMethod',
absMethod, absMethod', refine; intros;
destruct cod; intros; computes_to_inv.
+ destruct (H0 _ H) as [or' [Comp_or [AbsR_or'' eq_or''] ] ].
repeat computes_to_econstructor; eauto.
destruct v; simpl in *; subst; econstructor.
+ destruct (H0 _ H) as [or' [Comp_or AbsR_or'' ] ].
repeat computes_to_econstructor; eauto.
- intro; simpl; intros.
eapply (IHdom (fun or => oldMethod or d)); eauto.
Qed.
Hint Resolve refine_absMethod.
(* A similar approach works for constructors. *)
Fixpoint absConstructor
{dom : list Type}
: constructorType oldRep dom ->
constructorType newRep dom :=
match dom return
constructorType oldRep dom ->
constructorType newRep dom
with
| nil =>
fun oldConstr =>
{nr | exists or', oldConstr ↝ or' /\
or' ≃ nr }%comp
| cons d dom' =>
fun oldConstr t =>
@absConstructor dom' (oldConstr t)
end.
Lemma refine_absConstructor
(dom : list Type)
(oldConstr : constructorType oldRep dom)
: @refineConstructor oldRep newRep AbsR _ oldConstr
(absConstructor oldConstr).
Proof.
induction dom; simpl in *.
- unfold refineConstructor, absConstructor, refine; intros.
computes_to_inv; eauto.
- intros; eapply IHdom.
Qed.
Hint Resolve refine_absConstructor.
(* We can refine an ADT using the default mutator and observer
implementations provided by [absMutatorMethod] and [absObserverMethod]. *)
Lemma refineADT_Build_ADT_Rep_default
Sig
oldConstrs oldMeths :
refineADT
(@Build_ADT Sig oldRep oldConstrs oldMeths)
(@Build_ADT Sig newRep
(fun idx => absConstructor (oldConstrs idx))
(fun idx => absMethod (oldMeths idx))).
Proof.
eapply refineADT_Build_ADT_Rep; eauto.
Qed.
End HoneRepresentation.
(* Always unfold absMutatorMethods and absObserverMethods.
Global Arguments absMethod oldRep newRep AbsR Dom Cod oldMethod / nr n.
Global Arguments absConstructor oldRep newRep AbsR Dom oldConstr / n . *)
(* Honing tactic for refining the ADT representation which provides
default observer and mutator implementations. *)
Tactic Notation "hone" "representation" "using" constr(AbsR') :=
eapply SharpenStep;
[eapply refineADT_Build_ADT_Rep_default with (AbsR := AbsR') | ].
|
#include <bits/stdc++.h> using namespace std; int const N = 3e5 + 5; int const NN = 20; int const MAX = 1e9 + 1; int n, a[N]; struct ITMAX { pair<int, int> tree[4 * N]; pair<int, int> get_interval(pair<int, int> p, pair<int, int> q) { return make_pair(min(p.first, q.first), max(p.second, q.second)); } void build(int node, int l, int r, pair<int, int> val[]) { if (l == r) { tree[node] = val[l]; return; } int mid = (l + r) / 2; build(node * 2, l, mid, val); build(node * 2 + 1, mid + 1, r, val); tree[node] = get_interval(tree[node * 2], tree[node * 2 + 1]); } pair<int, int> get_max(int node, int l, int r, int d, int c) { if (l > c || r < d) { return make_pair(MAX, -MAX); } if (d <= l && r <= c) { return tree[node]; } int mid = (l + r) / 2; return get_interval(get_max(node * 2, l, mid, d, c), get_max(node * 2 + 1, mid + 1, r, d, c)); } }; ITMAX tree[NN]; pair<int, int> dp[NN][N]; void solve_nxt() { for (int i = 1; i <= n; i++) { dp[0][i] = make_pair(max(i - a[i], 1), min(i + a[i], n)); } tree[0].build(1, 1, n, dp[0]); for (int j = 1; j < NN; j++) { for (int i = 1; i <= n; i++) { dp[j][i] = tree[j - 1].get_max(1, 1, n, dp[j - 1][i].first, dp[j - 1][i].second); } tree[j].build(1, 1, n, dp[j]); } } int main() { ios_base::sync_with_stdio(0); cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; a[i + n] = a[i]; a[i + n + n] = a[i]; } if (n == 1) { cout << 0 << endl; return 0; } n *= 3; solve_nxt(); int sq = n / 3; for (int i = sq + 1; i <= sq + sq; i++) { int l = i; int r = i; int ans = 0; for (int j = NN - 1; j >= 0; j--) { pair<int, int> interval = tree[j].get_max(1, 1, n, l, r); int newL = interval.first; int newR = interval.second; if (newR - newL + 1 < sq) { l = newL; r = newR; ans += (1 << j); } } cout << ans + 1 << ; } cout << endl; } |
#include <bits/stdc++.h> using namespace std; int arr[92]; int main() { int n; cin >> n; for (int i = 0; i < n; i++) cin >> arr[i]; if (n == 1) { if (arr[0] == 15) cout << DOWN ; else if (arr[0] == 0) cout << UP ; else cout << -1; } else { if (arr[n - 1] > arr[n - 2]) { if (arr[n - 1] == 15) cout << DOWN ; else cout << UP ; } else if (arr[n - 1] < arr[n - 2]) { if (arr[n - 1] == 0) cout << UP ; else cout << DOWN ; } else cout << -1; } } |
#include <bits/stdc++.h> using namespace std; int n, k; int a[222], sum[222]; struct node { int a, id; } b[222]; bool cmp(node s, node d) { return s.a < d.a; } int main() { cin >> n >> k; for (int i = 0; i < n; i++) cin >> a[i], b[i].a = a[i], b[i].id = i; ; sum[0] = a[0]; for (int i = 1; i < n; i++) sum[i] = sum[i - 1] + a[i]; sort(b, b + n, cmp); int ans = -22222; for (int l = 0; l < n; l++) for (int r = l; r < n; r++) { int p = min(k, r - l + 1); int res = sum[r]; if (l) res -= sum[l - 1]; int i = 0, j = n - 1; while (p--) { while (i < n && b[i].id < l || b[i].id > r) i++; while (j >= 0 && b[j].id >= l && b[j].id <= r) j--; if (i == n || j == -1) break; if (b[i].a > b[j].a) break; res += (b[j].a - b[i].a); i++; j--; } ans = max(ans, res); } cout << ans << endl; } |
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Store Buffer ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Implements store buffer. ////
//// ////
//// To Do: ////
//// - byte combining ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_sb.v,v $
// Revision 1.1 2006-12-21 16:46:58 vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.2 2002/08/22 02:18:55 lampret
// Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.
//
// Revision 1.1 2002/08/18 19:53:08 lampret
// Added store buffer.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_sb(
// RISC clock, reset
clk, rst,
// Internal RISC bus (DC<->SB)
dcsb_dat_i, dcsb_adr_i, dcsb_cyc_i, dcsb_stb_i, dcsb_we_i, dcsb_sel_i, dcsb_cab_i,
dcsb_dat_o, dcsb_ack_o, dcsb_err_o,
// BIU bus
sbbiu_dat_o, sbbiu_adr_o, sbbiu_cyc_o, sbbiu_stb_o, sbbiu_we_o, sbbiu_sel_o, sbbiu_cab_o,
sbbiu_dat_i, sbbiu_ack_i, sbbiu_err_i
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
//
// RISC clock, reset
//
input clk; // RISC clock
input rst; // RISC reset
//
// Internal RISC bus (DC<->SB)
//
input [dw-1:0] dcsb_dat_i; // input data bus
input [aw-1:0] dcsb_adr_i; // address bus
input dcsb_cyc_i; // WB cycle
input dcsb_stb_i; // WB strobe
input dcsb_we_i; // WB write enable
input dcsb_cab_i; // CAB input
input [3:0] dcsb_sel_i; // byte selects
output [dw-1:0] dcsb_dat_o; // output data bus
output dcsb_ack_o; // ack output
output dcsb_err_o; // err output
//
// BIU bus
//
output [dw-1:0] sbbiu_dat_o; // output data bus
output [aw-1:0] sbbiu_adr_o; // address bus
output sbbiu_cyc_o; // WB cycle
output sbbiu_stb_o; // WB strobe
output sbbiu_we_o; // WB write enable
output sbbiu_cab_o; // CAB input
output [3:0] sbbiu_sel_o; // byte selects
input [dw-1:0] sbbiu_dat_i; // input data bus
input sbbiu_ack_i; // ack output
input sbbiu_err_i; // err output
`ifdef OR1200_SB_IMPLEMENTED
//
// Internal wires and regs
//
wire [4+dw+aw-1:0] fifo_dat_i; // FIFO data in
wire [4+dw+aw-1:0] fifo_dat_o; // FIFO data out
wire fifo_wr;
wire fifo_rd;
wire fifo_full;
wire fifo_empty;
wire sel_sb;
reg outstanding_store;
reg fifo_wr_ack;
//
// FIFO data in/out
//
assign fifo_dat_i = {dcsb_sel_i, dcsb_dat_i, dcsb_adr_i};
assign {sbbiu_sel_o, sbbiu_dat_o, sbbiu_adr_o} = sel_sb ? fifo_dat_o : {dcsb_sel_i, dcsb_dat_i, dcsb_adr_i};
//
// Control
//
assign fifo_wr = dcsb_cyc_i & dcsb_stb_i & dcsb_we_i & ~fifo_full & ~fifo_wr_ack;
assign fifo_rd = ~outstanding_store;
assign dcsb_dat_o = sbbiu_dat_i;
assign dcsb_ack_o = sel_sb ? fifo_wr_ack : sbbiu_ack_i;
assign dcsb_err_o = sel_sb ? 1'b0 : sbbiu_err_i; // SB never returns error
assign sbbiu_cyc_o = sel_sb ? outstanding_store : dcsb_cyc_i;
assign sbbiu_stb_o = sel_sb ? outstanding_store : dcsb_stb_i;
assign sbbiu_we_o = sel_sb ? 1'b1 : dcsb_we_i;
assign sbbiu_cab_o = sel_sb ? 1'b0 : dcsb_cab_i;
assign sel_sb = ~fifo_empty | (fifo_empty & outstanding_store); // | fifo_wr;
//
// Store buffer FIFO instantiation
//
or1200_sb_fifo or1200_sb_fifo (
.clk_i(clk),
.rst_i(rst),
.dat_i(fifo_dat_i),
.wr_i(fifo_wr),
.rd_i(fifo_rd),
.dat_o(fifo_dat_o),
.full_o(fifo_full),
.empty_o(fifo_empty)
);
//
// fifo_rd
//
always @(posedge clk or posedge rst)
if (rst)
outstanding_store <= #1 1'b0;
else if (sbbiu_ack_i)
outstanding_store <= #1 1'b0;
else if (sel_sb | fifo_wr)
outstanding_store <= #1 1'b1;
//
// fifo_wr_ack
//
always @(posedge clk or posedge rst)
if (rst)
fifo_wr_ack <= #1 1'b0;
else if (fifo_wr)
fifo_wr_ack <= #1 1'b1;
else
fifo_wr_ack <= #1 1'b0;
`else // !OR1200_SB_IMPLEMENTED
assign sbbiu_dat_o = dcsb_dat_i;
assign sbbiu_adr_o = dcsb_adr_i;
assign sbbiu_cyc_o = dcsb_cyc_i;
assign sbbiu_stb_o = dcsb_stb_i;
assign sbbiu_we_o = dcsb_we_i;
assign sbbiu_cab_o = dcsb_cab_i;
assign sbbiu_sel_o = dcsb_sel_i;
assign dcsb_dat_o = sbbiu_dat_i;
assign dcsb_ack_o = sbbiu_ack_i;
assign dcsb_err_o = sbbiu_err_i;
`endif
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title :
// File :
// Author : Jim MacLeod
// Created : 01-Dec-2011
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module flt_fx1616_mult
(
input clk,
input rstn,
input [31:0] fx,
input [31:0] bfl,
output reg [31:0] fl
);
reg sfx; // Sign of fixed
reg [31:0] afx; // Absolute fixed
reg [5:0] nom_shft_1; // Normalize shift.
reg [55:0] mfl_1; // Multiply Result.
reg [55:0] nmfl_1; // Mantisa of the Float
reg sfx_1;
reg sbfl_1;
reg [7:0] efl_1; // Exponent of the Float
reg [7:0] ebfl_1; // Exponent of the Float
reg sfl_1; // Sign of float
reg result0;
reg result0_1;
always @* // Take the absolute value of AFX.
begin
if(fx[31]) begin
sfx = 1;
afx = ~fx + 1;
end else begin
sfx = 0;
afx = fx;
end
if((fx==0) || (bfl[30:0]==0))result0 = 1;
else result0 = 0;
end
// Calculate the Mantissa.
always @(posedge clk, negedge rstn) begin
if(!rstn) begin
mfl_1 <= 56'h0;
sfx_1 <= 1'b0;
sbfl_1 <= 1'b0;
ebfl_1 <= 8'h0;
result0_1 <= 1'b0;
end else begin
mfl_1 <= afx * {1'b1,bfl[22:0]};
sfx_1 <= sfx;
sbfl_1 <= bfl[31];
ebfl_1 <= bfl[30:23];
result0_1 <= result0;
end
end
always @* begin
casex(mfl_1[55:23]) /* synopsys parallel_case */
33'b1xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx: nom_shft_1=6'd0;
33'b01xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx: nom_shft_1=6'd1;
33'b001xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx: nom_shft_1=6'd2;
33'b0001xxxxxxxxxxxxxxxxxxxxxxxxxxxxx: nom_shft_1=6'd3;
33'b00001xxxxxxxxxxxxxxxxxxxxxxxxxxxx: nom_shft_1=6'd4;
33'b000001xxxxxxxxxxxxxxxxxxxxxxxxxxx: nom_shft_1=6'd5;
33'b0000001xxxxxxxxxxxxxxxxxxxxxxxxxx: nom_shft_1=6'd6;
33'b00000001xxxxxxxxxxxxxxxxxxxxxxxxx: nom_shft_1=6'd7;
33'b000000001xxxxxxxxxxxxxxxxxxxxxxxx: nom_shft_1=6'd8;
33'b0000000001xxxxxxxxxxxxxxxxxxxxxxx: nom_shft_1=6'd9;
33'b00000000001xxxxxxxxxxxxxxxxxxxxxx: nom_shft_1=6'd10;
33'b000000000001xxxxxxxxxxxxxxxxxxxxx: nom_shft_1=6'd11;
33'b0000000000001xxxxxxxxxxxxxxxxxxxx: nom_shft_1=6'd12;
33'b00000000000001xxxxxxxxxxxxxxxxxxx: nom_shft_1=6'd13;
33'b000000000000001xxxxxxxxxxxxxxxxxx: nom_shft_1=6'd14;
33'b0000000000000001xxxxxxxxxxxxxxxxx: nom_shft_1=6'd15;
33'b00000000000000001xxxxxxxxxxxxxxxx: nom_shft_1=6'd16;
33'b000000000000000001xxxxxxxxxxxxxxx: nom_shft_1=6'd17;
33'b0000000000000000001xxxxxxxxxxxxxx: nom_shft_1=6'd18;
33'b00000000000000000001xxxxxxxxxxxxx: nom_shft_1=6'd19;
33'b000000000000000000001xxxxxxxxxxxx: nom_shft_1=6'd20;
33'b0000000000000000000001xxxxxxxxxxx: nom_shft_1=6'd21;
33'b00000000000000000000001xxxxxxxxxx: nom_shft_1=6'd22;
33'b000000000000000000000001xxxxxxxxx: nom_shft_1=6'd23;
33'b0000000000000000000000001xxxxxxxx: nom_shft_1=6'd24;
33'b00000000000000000000000001xxxxxxx: nom_shft_1=6'd25;
33'b000000000000000000000000001xxxxxx: nom_shft_1=6'd26;
33'b0000000000000000000000000001xxxxx: nom_shft_1=6'd27;
33'b00000000000000000000000000001xxxx: nom_shft_1=6'd28;
33'b000000000000000000000000000001xxx: nom_shft_1=6'd29;
33'b0000000000000000000000000000001xx: nom_shft_1=6'd30;
33'b00000000000000000000000000000001x: nom_shft_1=6'd31;
33'b000000000000000000000000000000001: nom_shft_1=6'd32;
default: nom_shft_1=0;
endcase
end
// Calculate the sign bit.
always @* sfl_1 = sfx_1 ^ sbfl_1;
// Calculate the Exponant.
// always @* efl_1 = ebfl_1 + (8'h10 - nom_shft_1);
always @* efl_1 = ebfl_1 + (8'h10 - nom_shft_1);
always @* nmfl_1 = mfl_1 << nom_shft_1;
always @(posedge clk, negedge rstn) //(SFL or EFL or MFL or FX or BFL)
begin
if(!rstn) fl <= 32'h0;
else if(result0_1) fl <= 32'h0;
else fl <= {sfl_1,efl_1,nmfl_1[54:32]};
end
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using db = double; using vi = vector<int>; const int l = 20; const int maxn = 300006; int e[maxn][l]; int tote; map<int, int> S; int a[maxn]; int yy[maxn]; int rr[maxn]; int h[maxn][1000 / l]; int n, q; int app[maxn]; int sum[maxn]; int Get(int a, int b) { return e[h[a][b / l]][b % l]; } int main() { scanf( %d%d , &n, &q); for (int i = 1; i <= n; ++i) { scanf( %d , &a[i]); S[a[i]] = 0; } int tot = 0; for (auto &p : S) { rr[tot] = p.first; p.second = tot; tot++; } for (int i = 1; i <= n; ++i) a[i] = S[a[i]]; int m = (int)sqrt(n * 5) + 3; for (int i = 1; i <= n; ++i) app[a[i]]++; vi big; for (int i = 0; i < tot; ++i) if (app[i] > m / 5 - 3) { big.push_back(i); yy[i] = big.size() - 1; } else yy[i] = -1; int maxs = big.size() / l; memset(h, 0, sizeof(h)); memset(e, 0, sizeof(e)); tote = 0; for (int i = 1; i <= n; ++i) { for (int j = 0; j <= maxs; ++j) h[i][j] = h[i - 1][j]; if (yy[a[i]] != -1) { int no = yy[a[i]]; tote++; for (int j = 0; j < l; ++j) e[tote][j] = e[h[i - 1][no / l]][j]; e[tote][no % l]++; h[i][no / l] = tote; } } for (int i = 1; i <= q; ++i) { int l, r, k; scanf( %d%d%d , &l, &r, &k); int ans = -1; for (auto x : big) if (Get(r, yy[x]) - Get(l - 1, yy[x]) > (r - l + 1) / k) if (ans == -1 || x < ans) ans = x; if (r - l + 1 <= m) { vi tr; for (int i = l; i <= r; ++i) { tr.push_back(a[i]); sum[a[i]]++; } for (auto x : tr) if (sum[x] > (r - l + 1) / k) if (ans == -1 || x < ans) ans = x; for (auto x : tr) sum[x] = 0; } printf( %d n , (ans == -1) ? -1 : rr[ans]); } } |
// This file is part of multiexp-a5gx.
//
// multiexp-a5gx is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see http://www.gnu.org/licenses/.
module pll_top ( input ref_clk
, input rst
, output out_clk
, output locked
, input pcie_ready
, output pcie_ready_sync
, input xwopen
, output xwopen_sync
);
wire pll_core_locked;
reg [5:0] lock_reg, lock_next;
assign locked = (lock_reg == '1);
reg [1:0] p_reg, x_reg;
assign pcie_ready_sync = p_reg[1];
assign xwopen_sync = x_reg[1];
// make absolutely sure that the pll_locked signal is stable before taking the ckt out of reset
always_comb begin
lock_next = lock_reg;
if (pll_core_locked) begin
// when pll_core_locked, count upwards w/saturation
if (~locked) begin
lock_next = lock_reg + 1'b1;
end
end else begin
// otherwise, restart count
lock_next = '0;
end
end
always_ff @(posedge out_clk or posedge rst) begin
if (rst) begin
lock_reg <= '0;
p_reg <= '0;
x_reg <= '0;
end else begin
lock_reg <= lock_next;
p_reg <= {p_reg[0],pcie_ready};
x_reg <= {x_reg[0],xwopen};
end
end
pll_core ipll ( .refclk (ref_clk)
, .rst (rst)
, .outclk_0 (out_clk)
, .locked (pll_core_locked)
);
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: sfifo_48x256.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sfifo_48x256 (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
full,
q);
input aclr;
input clock;
input [47:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [47:0] q;
wire sub_wire0;
wire sub_wire1;
wire [47:0] sub_wire2;
wire empty = sub_wire0;
wire full = sub_wire1;
wire [47:0] q = sub_wire2[47:0];
scfifo scfifo_component (
.aclr (aclr),
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.empty (sub_wire0),
.full (sub_wire1),
.q (sub_wire2),
.almost_empty (),
.almost_full (),
.sclr (),
.usedw ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 48,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "0"
// Retrieval info: PRIVATE: Width NUMERIC "48"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "48"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "48"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 48 0 INPUT NODEFVAL "data[47..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 48 0 OUTPUT NODEFVAL "q[47..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 48 0 data 0 0 48 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 48 0 @q 0 0 48 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_48x256.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_48x256.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_48x256.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_48x256.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_48x256_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_48x256_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> namespace modular { const int MOD = 1000000007; inline int add(int x, int y) { return (x += y) >= MOD ? x -= MOD : x; } inline void inc(int &x, int y) { (x += y) >= MOD ? x -= MOD : 0; } inline int mul(int x, int y) { return 1LL * x * y % MOD; } inline int qpow(int x, int y) { int ans = 1; for (; y; y >>= 1, x = mul(x, x)) if (y & 1) ans = mul(ans, x); return ans; } }; // namespace modular namespace Base { template <typename Tp> inline Tp input() { Tp x = 0, y = 1; char c = getchar(); while ((c < 0 || 9 < c) && c != EOF) { if (c == - ) y = -1; c = getchar(); } if (c == EOF) return 0; while ( 0 <= c && c <= 9 ) x = x * 10 + c - 0 , c = getchar(); return x *= y; } template <typename Tp> inline void read(Tp &x) { x = input<Tp>(); } template <typename Tp> inline void chmax(Tp &x, Tp y) { x < y ? x = y : 0; } template <typename Tp> inline void chmin(Tp &x, Tp y) { x > y ? x = y : 0; } }; // namespace Base using namespace Base; int N, M; struct edge { int u, v, w, t; bool operator<(const edge &rhs) const { return w < rhs.w; } } e[400007]; struct UFS { int fa[400007], sz[400007]; int top, cnt; std::pair<int, int> st[400007]; inline void init() { for (int i = 1; i <= N; ++i) fa[i] = i, sz[i] = 1; top = 0; cnt = N; } inline int find(int x) { while (fa[x] != x) x = fa[x]; return x; } inline void merge(int u, int v) { u = find(u), v = find(v); if (u == v) return; if (sz[u] < sz[v]) std::swap(u, v); st[++top] = std::pair<int, int>(u, v); if ((sz[u] & 1) && (sz[v] & 1)) cnt -= 2; fa[v] = u, sz[u] += sz[v]; } inline void pop(int t) { while (top > t) { int u = st[top].first, v = st[top].second; top--; sz[u] -= sz[v]; fa[v] = v; if ((sz[u] & 1) && (sz[v] & 1)) cnt += 2; } } } ufs; int ans[400007]; struct segTree { int pos; std::vector<int> t[400007 << 2]; segTree() : pos(1) {} void modi(int x, int l, int r, int ql, int qr, int id) { if (ql <= l && r <= qr) return t[x].push_back(id), void(); int mid = l + r >> 1; if (ql <= mid) modi(x << 1, l, mid, ql, qr, id); if (mid < qr) modi(x << 1 | 1, mid + 1, r, ql, qr, id); } void solve(int x, int l, int r) { int tmp = ufs.top; for (int id : t[x]) ufs.merge(e[id].u, e[id].v); if (l == r) { for (; pos <= M && ufs.cnt; ++pos) if (e[pos].t <= l) { ufs.merge(e[pos].u, e[pos].v); if (e[pos].t <= l - 1) modi(1, 1, M, e[pos].t, l - 1, pos); } ans[l] = ufs.cnt ? -1 : e[pos - 1].w; } else { int mid = l + r >> 1; solve(x << 1 | 1, mid + 1, r); solve(x << 1, l, mid); } ufs.pop(tmp); } } tr; int main() { read(N), read(M); for (int i = 1; i <= M; ++i) read(e[i].u), read(e[i].v), read(e[i].w), e[i].t = i; std::sort(e + 1, e + M + 1); ufs.init(); tr.solve(1, 1, M); for (int i = 1; i <= M; ++i) printf( %d n , ans[i]); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int t = 1; while (t--) { int n, k, inits[26]; char str[101]; bool poss = false, started[26] = {false}; scanf( %d%s , &k, str); n = strlen(str); if (n < k) { puts( NO ); break; } int cnt = 0; for (int i = 0, j = 0; i < n; i++) { if (!started[str[i] - a ]) { started[str[i] - a ] = 1; cnt++; inits[j] = i; j++; } if (cnt == k) { poss = true; break; } } if (!poss) puts( NO ); else { puts( YES ); int i = 0; for (int j = 0; j < n; j++) { if (j == inits[i + 1] - 1) { printf( %c n , str[j]); i++; } else printf( %c , str[j]); } } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5; int n, m, p; long long ans = -1e18; struct nd { int val, c; friend bool operator<(nd a, nd b) { return a.val < b.val; } } a[N], b[N]; struct mon { int x, y, z; friend bool operator<(mon a, mon b) { return a.x < b.x; } } c[N]; struct BIT { int tot; int ls[N << 1], rs[N << 1]; long long mx[N << 1], tag[N << 1]; void up(int x) { mx[x] = max(mx[ls[x]], mx[rs[x]]); } void down(int x) { if (!tag[x]) return; if (ls[x]) { mx[ls[x]] += tag[x]; tag[ls[x]] += tag[x]; } if (rs[x]) { mx[rs[x]] += tag[x]; tag[rs[x]] += tag[x]; } tag[x] = 0; } int build(int l, int r) { int x = ++tot; if (l == r) { mx[x] = -b[l].c; return x; } int mid = l + r >> 1; ls[x] = build(l, mid); rs[x] = build(mid + 1, r); up(x); return x; } void add(int x, int l, int r, int L, int R, long long d) { if (L <= l && r <= R) { mx[x] += d; tag[x] += d; return; } down(x); int mid = l + r >> 1; if (L <= mid) add(ls[x], l, mid, L, R, d); if (R > mid) add(rs[x], mid + 1, r, L, R, d); up(x); } void init() { mx[0] = -1e18; int root = build(1, m); } } T; int main() { scanf( %d%d%d , &n, &m, &p); for (int i = 1; i <= n; ++i) scanf( %d%d , &a[i].val, &a[i].c); for (int i = 1; i <= m; ++i) scanf( %d%d , &b[i].val, &b[i].c); for (int i = 1; i <= p; ++i) scanf( %d%d%d , &c[i].x, &c[i].y, &c[i].z); sort(a + 1, a + n + 1); sort(b + 1, b + m + 1); sort(c + 1, c + p + 1); T.init(); for (int i = 1, R = 0; i <= n; ++i) { while (R < p && c[R + 1].x < a[i].val) { ++R; int l = 1, r = m; while (l != r) { int mid = l + r >> 1; if (b[mid].val > c[R].y) r = mid; else l = mid + 1; } if (b[l].val > c[R].y) { T.add(1, 1, m, l, m, c[R].z); } } ans = max(ans, -a[i].c + T.mx[1]); } printf( %lld n , ans); } |
module tester;
reg rrst ;
reg [63:0] rdata ;
reg [31:0] rparameter_Block ;
reg [63:0] rparameter_Block2 ;
reg [7:0] rbmRequestType ;
reg [7:0] rbRequest ;
reg [15:0] rwValue ;
reg [15:0] rwIndex ;
reg [15:0] rwLength ;
reg renable ;
wire wbusy ;
wire [31:0] wdata_out;
wire [63:0] wdata_out2;
wire [15:0] wdata_out3;
reg rclk = 0;
always #1 rclk = !rclk;
always @(rclk)
begin
rdata [63:56] = rbmRequestType [7:0];
rdata [55:47]= rbRequest [7:0];
rdata [46:33] = rwValue [15:0];
rdata [32:16] = rwIndex [15:0];
rdata [15:0] = rwLength ;
end
initial begin
$dumpfile("tester.vcd");
$dumpvars(0,tester);
rrst = 1;
#5
rrst =0 ;
rdata = 0;
rparameter_Block = 1;
rparameter_Block2 = 12;
rbmRequestType [7:0] = 8'b00100001;
rbRequest = 8'h03 ;
rwValue = 0;
rwIndex = 0;
rwLength = 2;
renable = 1 ;
#5
rrst =0 ;
rdata = 0;
rparameter_Block = 1;
rparameter_Block2 = 0;
rbmRequestType [7:0] = 8'b10100001;
rbRequest = 8'h83 ;
rwValue = 0;
rwIndex = 0;
rwLength = 2;
renable = 1 ;
# 513 $finish;
end
control control_intance (
.busy (wbusy),
.clk (rclk),
.rst (rrst),
.data (rdata),
.data_out32 (wdata_out),
.data_out64 (wdata_out2),
.data_out16 (wdata_out3),
.parameter_Block32 (rparameter_Block),
.parameter_Block64 (rparameter_Block2),
.enable (renable)
);
endmodule |
#include <bits/stdc++.h> using namespace std; const int N = 5001; long long n, m, a[N + 1], b[N + 1], type[N], l[N], r[N], x[N]; int main() { ios_base::sync_with_stdio(false); cin >> n >> m; for (int i = 1; i <= n; i++) a[i] = 1e9; for (int j = 1; j <= m; j++) { cin >> type[j] >> l[j] >> r[j] >> x[j]; if (type[j] == 1) for (int i = l[j]; i <= r[j]; i++) b[i] += x[j]; else { bool ok = false; for (int i = l[j]; i <= r[j]; i++) { if (a[i] >= x[j] - b[i]) ok = true; a[i] = min(a[i], x[j] - b[i]); } if (!ok) { cout << NO ; return 0; } } } for (int i = 1; i <= n; i++) b[i] = a[i]; bool ok = true; for (int i = 1; i <= m; i++) { if (type[i] == 1) for (int j = l[i]; j <= r[i]; j++) a[j] += x[i]; else { long long mx = a[l[i]]; for (int j = l[i] + 1; j <= r[i]; j++) mx = max(mx, a[j]); if (mx != x[i]) { ok = false; break; } } } if (!ok) cout << NO ; else { cout << YES << endl; for (int i = 1; i <= n; i++) cout << b[i] << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 200015; const int MOD = 1000000007; int a[MAXN]; bool F(int len, int num) { bool flag; int pres; for (int i = 0; i <= num - 1; i++) { flag = true; pres = i; for (int j = 0; j <= len - 1; j++) { if (a[pres] == 0) flag = false; pres += num; } if (flag == true) return flag; } return false; } int main() { int n; scanf( %d , &n); for (int i = 0; i <= n - 1; i++) scanf( %d , &a[i]); bool ok = false; for (int i = 1; i <= sqrt(n); i++) { if (n % i == 0) { if (i >= 3) ok = ok | F(i, n / i); if (i != sqrt(n) && n / i >= 3) ok = ok | F(n / i, i); } } if (ok) cout << YES n ; else cout << NO n ; return 0; } |
// bsg_mesosync_link devides the chip's clock to a slower clock for IO
// based on the configuration it receives.
//
// bsg_mesosync_output module has three phases to be calibrated. After reset,
// it would send out a known pattern so the other side (master) can bit-allign
// its input. Next it would send all possible transitions of data using two
// counters to make sure the output channel is reliable.
//
// To find out the proper values for bit configuration, it sends outputs of
// the logic analzer received from the bsg_mesosync_input module.
//
// On the pins side there is no handshake protocol and on the other side,
// to rest of bsg_mesosync_link, it has ready-only protocol, which declares
// when it has sent a data.
//
// It also provides the loopback mode, received from config_tag, since the
// loopback module must be placed very close to it.
//
//`ifndef DEFINITIONS_V
//`include "definitions.v"
//`endif
`include "bsg_defines.v"
module bsg_mesosync_output
#( parameter `BSG_INV_PARAM(width_p )
, parameter `BSG_INV_PARAM(cfg_tag_base_id_p )
)
( input clk
, input reset
, input config_s config_i
// Sinals with their acknowledge
, input [width_p-1:0] data_i
, output logic ready_o
, output logic [width_p-1:0] pins_o
// Logic analyzer signals for mesosync_input module
, input LA_data_i
, input LA_valid_i
, output ready_to_LA_o
// loopback mode signal for loopback module
, output logic loopback_en_o
, output logic channel_reset_o
);
//------------------------------------------------
//------------ CONFIG TAG NODEs ------------------
//------------------------------------------------
// Configuratons
logic [1:0] cfg_reset, cfg_reset_r;
logic input_enable; // not used
mode_cfg_s mode_cfg;
logic [maxDivisionWidth_p-1:0] output_clk_divider;
logic [`BSG_SAFE_CLOG2(width_p)-1:0] la_output_bit_selector;
logic [`BSG_SAFE_CLOG2(width_p)-1:0] v_output_bit_selector;
// Calcuating data width of each configuration node
// For $clog2, width_lp is a number
localparam width_lp = width_p + 0;
// reset (2 bits), clock divider for output digital clock,
// logic analyzer data and valid line selector
localparam output_node_data_width_p = 2 + maxDivisionWidth_p
+ 2*(`BSG_SAFE_CLOG2(width_lp));
// mode_cfg, input_enable and loopback_en
localparam common_node_data_width_p = $bits(mode_cfg) + 1 + 1;
// relay nodes
config_s relay_out;
relay_node input_relay_1(.config_i(config_i),
.config_o(relay_out));
// Config nodes
config_node#(.id_p(cfg_tag_base_id_p)
,.data_bits_p(common_node_data_width_p)
,.default_p('d0)
) common_node
(.clk(clk)
,.reset(reset)
,.config_i(relay_out)
,.data_o({mode_cfg,input_enable,loopback_en_o})
);
config_node#(.id_p(cfg_tag_base_id_p+2)
,.data_bits_p(output_node_data_width_p)
,.default_p('d0)
) output_node
(.clk(clk)
,.reset(reset)
,.config_i(relay_out)
,.data_o({cfg_reset,output_clk_divider,la_output_bit_selector,
v_output_bit_selector})
);
//------------------------------------------------
//--------------- RESET LOGIC --------------------
//------------------------------------------------
always_ff @(posedge clk)
cfg_reset_r <= cfg_reset;
// reset is kept high until it is reset by the cfg node
// by changing reset value from 2'b01 to 2'b10, then
// it would remain low (unless another value is recieved)
always_ff @(posedge clk)
if ((cfg_reset == 2'b10) &
((cfg_reset_r == 2'b01)|(channel_reset_o == 1'b0)))
channel_reset_o <= 1'b0;
else
channel_reset_o <= 1'b1;
//------------------------------------------------
//--------- RELAY FIFO FOR LA DATA ---------------
//------------------------------------------------
// Using a bsg_relay_fifo to abosrb any latency on the line
logic LA_valid, ready_to_LA, LA_data;
bsg_relay_fifo #(.width_p(1)) LA_relay
(.clk_i(clk)
,.reset_i(channel_reset_o)
,.ready_o(ready_to_LA_o)
,.data_i(LA_data_i)
,.v_i(LA_valid_i)
,.v_o(LA_valid)
,.data_o(LA_data)
,.ready_i(ready_to_LA)
);
//------------------------------------------------
//------------- CLOCK DIVIDERS --------------------
//------------------------------------------------
logic [maxDivisionWidth_p-1:0] input_counter_r, output_counter_r;
// clk is divided by the configured outpt_clk_divider_i plus one. So 0
// means no clk division and 15 means clk division by factor of 16.
bsg_counter_dynamic_limit #(.width_p(maxDivisionWidth_p)) output_counter
( .clk_i(clk)
, .reset_i(channel_reset_o)
, .limit_i(output_clk_divider)
, .counter_o(output_counter_r)
);
//------------------------------------------------
//------------- OUTPUT MODULE --------------------
//------------------------------------------------
localparam counter_bits_lp = (width_p+1)*2+1;
// internal signal for channel output
logic [width_p-1:0] output_data;
// internal output_ready signals based on the output mode
logic output_ready, ready_to_sync1, ready_to_sync2;
// counter for sync2 output mode
logic [counter_bits_lp-1:0] out_ctr_r, out_ctr_n;
// shift register for sending out the pattern in sync1 output mode
logic [7:0] out_rot_r, out_rot_n;
// Counter and shift register
always_ff @(posedge clk)
begin
if (channel_reset_o)
begin
out_ctr_r <= counter_bits_lp ' (0);
out_rot_r <= 8'b1010_0101; // bit alignment sequence
end
else
begin
if (ready_to_sync1)
out_rot_r <= out_rot_n;
if (ready_to_sync2)
out_ctr_r <= out_ctr_n;
end
end
wire [counter_bits_lp-1:0] out_ctr_r_p1 = out_ctr_r + 1'b1;
// fill pattern with at least as many 10's to fill out_cntr_width_p bits
// having defaults be 10101 reduces electromigration on pads
localparam inactive_pattern_p = {((width_p+1)>>1) {2'b01}};
// Demux that merges 1 bit outputs of Logic Analyzer and its valid signal
logic [width_p-1:0] output_demux;
assign output_demux = (LA_valid << v_output_bit_selector)
|(LA_data << la_output_bit_selector);
// determning output based on output mode configuration
always_comb
begin
out_ctr_n = out_ctr_r;
out_rot_n = out_rot_r;
output_data = 0;
unique case (mode_cfg.output_mode)
STOP:
begin
end
PAT:
begin
output_data = {inactive_pattern_p[0+:width_p] };
end
SYNC1:
begin
out_rot_n = { out_rot_r[6:0], out_rot_r[7] };
output_data = { (width_p) { out_rot_r[7] } };
end
SYNC2:
begin
out_ctr_n = out_ctr_r_p1;
// we do fast bits then slow bits
output_data = out_ctr_r[0]
? out_ctr_r[(1+(width_p))+:(width_p)]
: out_ctr_r[1+:(width_p)];
end
LA:
begin
output_data = output_demux;
end
NORM:
begin
// Sending inactive pattern as data for non valid data
output_data[0] = data_i[0]; // valid
output_data[1] = data_i[1]; // token
output_data[width_p-1:2] = data_i[0] ? data_i [width_p-1:2]
: inactive_pattern_p[0+:width_p-2];
end
default:
begin
end
endcase
end
// each time outputcounter is about to over flow on clock edge, data
// would be sent out on the clock edge as well
always_ff @ (posedge clk)
if (channel_reset_o) begin
pins_o <= 0;
end else if (output_counter_r == output_clk_divider) begin
pins_o <= output_data;
end else begin
// pins_o keeps its value
pins_o <= pins_o;
end
assign output_ready = (output_counter_r == output_clk_divider) & ~channel_reset_o;
// ready signals based on the output mode
// There is no need for awknowledge of ready in STOP and PATTERN modes
assign ready_o = output_ready & (mode_cfg.output_mode == NORM);
assign ready_to_LA = output_ready & (mode_cfg.output_mode == LA);
assign ready_to_sync1 = output_ready & (mode_cfg.output_mode == SYNC1);
assign ready_to_sync2 = output_ready & (mode_cfg.output_mode == SYNC2);
endmodule
`BSG_ABSTRACT_MODULE(bsg_mesosync_output)
|
#include <bits/stdc++.h> using namespace std; const int N = 2e4 + 5; char s[N]; int dp[10][N]; int ans[N]; int len; int dfs(int num, int idx) { if (~dp[num][idx]) return dp[num][idx]; if (idx == len) return 1; else if (idx > len) return 0; int &ret = dp[num][idx]; ret = dfs(num ^ 1, idx + num); bool flag = false; for (int i = idx; i < idx + num; ++i) { if (s[i] != s[i + num]) { flag = true; break; } } if (flag) { ret = max(ret, dfs(num, idx + num)); } return ret; } const int B = 333; int cal(char a, char b, char c) { return a * B * B + b * B + c; } int cal(char a, char b) { return a * B * B + b * B; } void prt(int x) { printf( %c , x / (B * B)); printf( %c , x % (B * B) / B); if (x % B) { printf( %c , x % B); } puts( ); } int main() { while (~scanf( %s , s)) { memset(dp, -1, sizeof(dp)); int cnt = 0; len = strlen(s); for (int i = len - 2; i >= 5; --i) { if (dfs(2, i) == 1) { ans[cnt++] = (cal(s[i], s[i + 1])); } if (dfs(3, i) == 1) { ans[cnt++] = (cal(s[i], s[i + 1], s[i + 2])); } } sort(ans, ans + cnt); cnt = unique(ans, ans + cnt) - ans; printf( %d n , cnt); for (int i = 0; i < cnt; ++i) { prt(ans[i]); } } return 0; } |
#include <bits/stdc++.h> using namespace std; using uint = unsigned int; using ll = long long; using ld = long double; using ull = unsigned long long; using pii = pair<int, int>; using pll = pair<ll, ll>; template <typename T1, typename T2> ostream &operator<<(ostream &out, const pair<T1, T2> &item) { out << ( << item.first << , << item.second << ) ; return out; } template <typename T> ostream &operator<<(ostream &out, const vector<T> &v) { for (const auto &item : v) out << item << ; return out; } int x[2][2], y[2][2]; void mul(int a[2][2], int b[2][2], int c[2][2], int mod) { for (int i = 0; i < 2; ++i) for (int j = 0; j < 2; ++j) c[i][j] = (1LL * a[i][0] * b[0][j] + 1LL * a[i][1] * b[1][j]) % mod; } void pw(ll exp, int mod) { int aux[2][2]; y[0][0] = y[1][1] = 1 % mod; y[0][1] = y[1][0] = 0; for (; exp; exp >>= 1) { if (exp & 1) { mul(x, y, aux, mod); memcpy(y, aux, sizeof aux); } mul(x, x, aux, mod); memcpy(x, aux, sizeof aux); } } int fib(ll n, int mod) { if (n <= 2) return 1 % mod; x[0][0] = 0; x[0][1] = x[1][0] = x[1][1] = 1 % mod; pw(n - 1, mod); return (y[0][0] + y[1][0]) % mod; } ll l, r, k; ll collect(ll n) { if (n == 0) return 0; ll kk, res = 0; for (ll x = 1; x * x <= n; ++x) { if (r / x - (l - 1) / x >= k) res = max(res, x); kk = n / x; } for (; kk; --kk) { ll x = n / kk; if (r / x - (l - 1) / x >= k) res = max(res, x); } return res; } int main() { ios_base::sync_with_stdio(false); ll mod; cin >> mod >> l >> r >> k; ll ans = collect(l - 1); ans = max(ans, collect(r)); cout << fib(ans, mod) << n ; return 0; } |
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
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// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
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// (individually and collectively, "Critical
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// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
// IP Revision: 5
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module shadow_pixel (
clka,
wea,
addra,
dina,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [0 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [10 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [11 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [11 : 0] douta;
blk_mem_gen_v8_3_5 #(
.C_FAMILY("artix7"),
.C_XDEVICEFAMILY("artix7"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(0),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(1),
.C_INIT_FILE_NAME("shadow_pixel.mif"),
.C_INIT_FILE("shadow_pixel.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(0),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(12),
.C_READ_WIDTH_A(12),
.C_WRITE_DEPTH_A(1080),
.C_READ_DEPTH_A(1080),
.C_ADDRA_WIDTH(11),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(12),
.C_READ_WIDTH_B(12),
.C_WRITE_DEPTH_B(1080),
.C_READ_DEPTH_B(1080),
.C_ADDRB_WIDTH(11),
.C_HAS_MEM_OUTPUT_REGS_A(1),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_EN_SAFETY_CKT(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("1"),
.C_COUNT_18K_BRAM("0"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 2.5913 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(1'D0),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(11'B0),
.dinb(12'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.rsta_busy(),
.rstb_busy(),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(12'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__BUFBUF_16_V
`define SKY130_FD_SC_HS__BUFBUF_16_V
/**
* bufbuf: Double buffer.
*
* Verilog wrapper for bufbuf with size of 16 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__bufbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__bufbuf_16 (
X ,
A ,
VPWR,
VGND
);
output X ;
input A ;
input VPWR;
input VGND;
sky130_fd_sc_hs__bufbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__bufbuf_16 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__bufbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__BUFBUF_16_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUFINV_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__BUFINV_PP_BLACKBOX_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__bufinv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUFINV_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFXBP_PP_SYMBOL_V
`define SKY130_FD_SC_HVL__SDFXBP_PP_SYMBOL_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__sdfxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFXBP_PP_SYMBOL_V
|
//****************************************************************************************************
//*---------------Copyright (c) 2016 C-L-G.FPGA1988.lichangbeiju. All rights reserved-----------------
//
// -- It to be define --
// -- ... --
// -- ... --
// -- ... --
//****************************************************************************************************
//File Information
//****************************************************************************************************
//File Name : uart.v
//Project Name : azpr_soc
//Description : the digital top of the chip.
//Github Address : github.com/C-L-G/azpr_soc/trunk/ic/digital/rtl//uart/uart.v
//License : Apache-2.0
//****************************************************************************************************
//Version Information
//****************************************************************************************************
//Create Date : 2016-11-22 17:00
//First Author : lichangbeiju
//Last Modify : 2016-11-23 14:20
//Last Author : lichangbeiju
//Version Number : 12 commits
//****************************************************************************************************
//Change History(latest change first)
//yyyy.mm.dd - Author - Your log of change
//****************************************************************************************************
//2016.12.08 - lichangbeiju - Change the include.
//2016.11.23 - lichangbeiju - Change the coding style.
//2016.11.22 - lichangbeiju - Add io port.
//****************************************************************************************************
//File Include : system header file
`include "../sys_include.h"
`include "uart.h"
module uart (
input wire clk,
input wire reset,
input wire cs_n,
input wire as_n,
input wire rw,
input wire [`UartAddrBus] addr,
input wire [`WordDataBus] wr_data,
output wire [`WordDataBus] rd_data,
output wire rdy_n,
output wire irq_rx,
output wire irq_tx,
input wire rx,
output wire tx
);
wire rx_busy;
wire rx_end;
wire [`ByteDataBus] rx_data;
wire tx_busy;
wire tx_end;
wire tx_start;
wire [`ByteDataBus] tx_data;
uart_ctrl uart_ctrl (
.clk (clk),
.reset (reset),
.cs_n (cs_n),
.as_n (as_n),
.rw (rw),
.addr (addr),
.wr_data (wr_data),
.rd_data (rd_data),
.rdy_n (rdy_n),
.irq_rx (irq_rx),
.irq_tx (irq_tx),
.rx_busy (rx_busy),
.rx_end (rx_end),
.rx_data (rx_data),
.tx_busy (tx_busy),
.tx_end (tx_end),
.tx_start (tx_start),
.tx_data (tx_data)
);
uart_tx uart_tx (
.clk (clk),
.reset (reset),
.tx_start (tx_start),
.tx_data (tx_data),
.tx_busy (tx_busy),
.tx_end (tx_end),
.tx (tx)
);
uart_rx uart_rx (
.clk (clk),
.reset (reset),
.rx_busy (rx_busy),
.rx_end (rx_end),
.rx_data (rx_data),
.rx (rx)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__HA_4_V
`define SKY130_FD_SC_HD__HA_4_V
/**
* ha: Half adder.
*
* Verilog wrapper for ha with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__ha.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__ha_4 (
COUT,
SUM ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__ha base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__ha_4 (
COUT,
SUM ,
A ,
B
);
output COUT;
output SUM ;
input A ;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__ha base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__HA_4_V
|
`timescale 1 ns / 1 ps
//////////////////////////////////////////////////////////////////////////////////
// Company: AGH UST
// Engineer: Wojciech Gredel, Hubert Górowski
//
// Create Date:
// Design Name:
// Module Name: Change2Negedge
// Project Name: DOS_Mario
// Target Devices: Basys3
// Tool versions: Vivado 2016.1
// Description:
// A module which is used to put input data out on negedge of clock
//
// Dependencies:
//
// Revision:
// Revision 0.01 - Module created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Change2Negedge
(
input wire hsync_in,
input wire vsync_in,
input wire blnk_in,
input wire [23:0] rgb_in,
input wire clk,
input wire rst,
output reg hsync_out,
output reg vsync_out,
output reg blnk_out,
output reg [23:0] rgb_out
);
always @(negedge clk or posedge rst) begin
if(rst) begin
hsync_out <= #1 0;
vsync_out <= #1 0;
blnk_out <= #1 0;
rgb_out <= #1 0;
end
else begin
hsync_out <= #1 hsync_in;
vsync_out <= #1 vsync_in;
blnk_out <= #1 blnk_in;
rgb_out <= #1 rgb_in;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int a = 0; cin >> a; int z = 0, e = 0; char b; for (int i = 0; i < a; i++) { cin >> b; if (b == D ) z++; if (b == A ) e++; } if (e == z) cout << Friendship ; else if (e < z) cout << Danik ; else if (e > z) cout << Anton ; } |
#include <bits/stdc++.h> using namespace std; vector<int> pf(const string& s) { int n = s.size(); vector<int> pi(n); for (int i = 1; i < n; i++) { int j = pi[i - 1]; while (j > 0 && s[i] != s[j]) j = pi[j - 1]; if (s[i] == s[j]) j++; pi[i] = j; } return pi; } int main() { ios_base::sync_with_stdio(false); string s; string t; cin >> s >> t; auto a = pf(t); int val = t.length() - a.back(); int cyc = val; int c1 = 0, c0 = 0; for (int i = 0; i < s.length(); i++) { if (s[i] == 1 ) c1++; else c0++; } int p = 0; while (true) { if (t[p] == 0 ) { if (c0) { cout << 0; c0--; } else break; } else { if (c1) { cout << 1; c1--; } else break; } p++; p %= cyc; } while (c1) { cout << 1; c1--; } while (c0) { cout << 0; c0--; } return 0; } |
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
module reset_extender
#(parameter C_RST_COUNT = 10)
(input CLK,
input RST_BUS,
input RST_LOGIC,
output RST_OUT,
output PENDING_RST);
`include "functions.vh"
localparam C_CLOG2_RST_COUNT = clog2s(C_RST_COUNT);
localparam C_CEIL2_RST_COUNT = 1 << C_CLOG2_RST_COUNT;
localparam C_RST_SHIFTREG_DEPTH = 4;
wire [C_CLOG2_RST_COUNT:0] wRstCount;
wire [C_RST_SHIFTREG_DEPTH:0] wRstShiftReg;
assign PENDING_RST = wRstShiftReg != 0;
assign RST_OUT = wRstShiftReg[C_RST_SHIFTREG_DEPTH];
counter
#(// Parameters
.C_MAX_VALUE (C_CEIL2_RST_COUNT),
.C_SAT_VALUE (C_CEIL2_RST_COUNT),
.C_RST_VALUE (C_CEIL2_RST_COUNT - C_RST_COUNT)
/*AUTOINSTPARAM*/)
rst_counter
(// Outputs
.VALUE (wRstCount),
// Inputs
.ENABLE (1'b1),
.RST_IN (RST_BUS | RST_LOGIC),
/*AUTOINST*/
// Inputs
.CLK (CLK));
shiftreg
#(// Parameters
.C_DEPTH (C_RST_SHIFTREG_DEPTH),
.C_WIDTH (1),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
rst_shiftreg
(// Outputs
.RD_DATA (wRstShiftReg),
// Inputs
.RST_IN (0),
.WR_DATA (~wRstCount[C_CLOG2_RST_COUNT]),
/*AUTOINST*/
// Inputs
.CLK (CLK));
endmodule
|
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author:
* Description:
*
* Changes:
*/
module sdio_function_template (
input clk,
input rst
//output reg [7:0] o_reg_example
//input [7:0] i_reg_example
);
//local parameters
localparam PARAM1 = 32'h00000000;
//registes/wires
//submodules
//asynchronous logic
//synchronous logic
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 100; char s[maxn], t[maxn]; int s_big[30], s_small[30], t_big[30], t_small[30]; int main() { while (scanf( %s%s , s + 1, t + 1) != EOF) { memset(s_big, 0, sizeof(s_big)); memset(s_small, 0, sizeof(s_small)); memset(t_big, 0, sizeof(t_big)); memset(t_small, 0, sizeof(t_small)); int len1 = strlen(s + 1); int len2 = strlen(t + 1); for (int i = 1; i <= len1; i++) { if (s[i] > Z ) { s_small[s[i] - a ]++; } else { s_big[s[i] - A ]++; } } for (int i = 1; i <= len2; i++) { if (t[i] > Z ) { t_small[t[i] - a ]++; } else { t_big[t[i] - A ]++; } } int ans1 = 0, ans2 = 0; for (int i = 0; i < 26; i++) { ans1 += min(s_small[i], t_small[i]); ans1 += min(s_big[i], t_big[i]); if (s_small[i] < t_small[i]) { t_small[i] -= s_small[i]; s_small[i] = 0; } else { s_small[i] -= t_small[i]; t_small[i] = 0; } if (s_big[i] < t_big[i]) { t_big[i] -= s_big[i]; s_big[i] = 0; } else { s_big[i] -= t_big[i]; t_big[i] = 0; } } for (int i = 0; i < 26; i++) { ans2 += min(s_small[i], t_big[i]); ans2 += min(s_big[i], t_small[i]); } printf( %d %d n , ans1, ans2); } return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build Mon Oct 10 19:07:27 MDT 2016
// Date : Mon Sep 18 13:00:14 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub
// c:/Projects/srio_test/srio_test/srio_test.srcs/sources_1/ip/fifo_generator_0/fifo_generator_0_stub.v
// Design : fifo_generator_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v13_1_2,Vivado 2016.3" *)
module fifo_generator_0(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full,
empty, rd_data_count, wr_data_count, prog_full, prog_empty)
/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[63:0],wr_en,rd_en,dout[63:0],full,empty,rd_data_count[8:0],wr_data_count[9:0],prog_full,prog_empty" */;
input rst;
input wr_clk;
input rd_clk;
input [63:0]din;
input wr_en;
input rd_en;
output [63:0]dout;
output full;
output empty;
output [8:0]rd_data_count;
output [9:0]wr_data_count;
output prog_full;
output prog_empty;
endmodule
|
module I2C(
// clock and reset
input clk,
input reset,
// inputs
input [6:0] chip_addr,
input [7:0] reg_addr,
input [7:0] value,
input enable,
input is_read,
// I2C pins
inout sda,
inout scl,
// outputs
output reg [7:0] data,
output reg done,
output i2c_ack_error,
input [31:0] divider
);
reg i2c_ena;
reg [6:0] i2c_addr;
reg i2c_rw;
reg [7:0] i2c_data_wr;
reg i2c_busy;
reg [7:0] i2c_data_rd;
i2c_master i2c_master(
.clk (clk),
.reset_n (1'b1),
.ena (i2c_ena),
.addr (i2c_addr),
.rw (i2c_rw),
.data_wr (i2c_data_wr),
.busy (i2c_busy),
.data_rd (i2c_data_rd),
.ack_error (i2c_ack_error),
.sda (sda),
.scl (scl),
.divider (divider)
);
(* syn_encoding = "safe" *)
reg [1:0] state;
reg [5:0] busy_cnt;
reg busy_prev;
reg [6:0] chip_addr_reg;
reg [7:0] reg_addr_reg;
reg [7:0] value_reg;
localparam s_idle = 0,
s_send = 1;
initial begin
state <= s_idle;
busy_cnt = 0;
done <= 1'b1;
end
always @ (posedge clk) begin
if (~reset) begin
state <= s_idle;
busy_cnt = 0;
done <= 1'b1;
end
else begin
case(state)
s_idle: begin
if (enable) begin
chip_addr_reg <= chip_addr;
reg_addr_reg <= reg_addr;
value_reg <= value;
done <= 1'b0;
state <= s_send;
end
end
s_send: begin
busy_prev <= i2c_busy;
if (~busy_prev && i2c_busy) begin
busy_cnt = busy_cnt + 1'b1;
end
case (busy_cnt)
0: begin
i2c_ena <= 1'b1;
i2c_addr <= chip_addr_reg;
i2c_rw <= 1'b0;
i2c_data_wr <= reg_addr_reg;
end
1: begin
if (is_read) begin
i2c_rw <= 1'b1;
end else begin
i2c_data_wr <= value_reg;
end
end
2: begin
i2c_ena <= 1'b0;
if (~i2c_busy) begin
data <= i2c_data_rd;
busy_cnt = 0;
done <= 1'b1;
state <= s_idle;
end
end
endcase
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; using u128 = __uint128_t; signed main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t = 1; while (t--) { long long n; cin >> n; vector<long long> ans(n, 0); cout << ? << 1 << << n << endl; long long tot; cin >> tot; for (long long i = 2; i < n; i++) { cout << ? << i << << n << endl; long long q; cin >> q; ans[i - 2] = tot - q; tot = q; } cout << ? << n - 2 << << n - 1 << endl; long long q; cin >> q; ans[n - 2] = q - ans[n - 3]; ans[n - 1] = tot - ans[n - 2]; cout << ! ; for (long long i : ans) cout << i << ; exit(0); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 6; int n, m, a[N]; int main() { int x[3], y[3]; cin >> x[0] >> y[0] >> x[1] >> y[1] >> x[2] >> y[2]; int len[3] = {(x[1] - x[0]) * (x[1] - x[0]) + (y[1] - y[0]) * (y[1] - y[0]), (x[2] - x[0]) * (x[2] - x[0]) + (y[2] - y[0]) * (y[2] - y[0]), (x[1] - x[2]) * (x[1] - x[2]) + (y[1] - y[2]) * (y[1] - y[2])}; int ff = 0; int z[] = {len[0], len[1], len[2]}; sort(z, z + 3); if (z[0] + z[1] == z[2]) puts( RIGHT ); else { for (int i = 0; i < 3 && !ff; i++) { for (int j = 0; j < 4 && !ff; j++) { if (j == 0) { x[i] += 1; len[0] = (x[1] - x[0]) * (x[1] - x[0]) + (y[1] - y[0]) * (y[1] - y[0]); len[1] = (x[2] - x[0]) * (x[2] - x[0]) + (y[2] - y[0]) * (y[2] - y[0]); len[2] = (x[1] - x[2]) * (x[1] - x[2]) + (y[1] - y[2]) * (y[1] - y[2]); sort(len, len + 3); if (!len[0]) { x[i] -= 1; continue; } if (x[0] == x[1] && x[1] == x[2] || y[1] == y[0] && y[1] == y[2]) { x[i] -= 1; continue; } if (len[0] + len[1] == len[2]) { puts( ALMOST ); ff = 1; } x[i] -= 1; } else if (j == 1) { x[i] -= 1; len[0] = (x[1] - x[0]) * (x[1] - x[0]) + (y[1] - y[0]) * (y[1] - y[0]); len[1] = (x[2] - x[0]) * (x[2] - x[0]) + (y[2] - y[0]) * (y[2] - y[0]); len[2] = (x[1] - x[2]) * (x[1] - x[2]) + (y[1] - y[2]) * (y[1] - y[2]); sort(len, len + 3); if (!len[0]) { x[i] += 1; continue; } if (x[0] == x[1] && x[1] == x[2] || y[1] == y[0] && y[1] == y[2]) { x[i] += 1; continue; } if (len[0] + len[1] == len[2]) { puts( ALMOST ); ff = 1; } x[i] += 1; } else if (j == 2) { y[i] -= 1; len[0] = (x[1] - x[0]) * (x[1] - x[0]) + (y[1] - y[0]) * (y[1] - y[0]); len[1] = (x[2] - x[0]) * (x[2] - x[0]) + (y[2] - y[0]) * (y[2] - y[0]); len[2] = (x[1] - x[2]) * (x[1] - x[2]) + (y[1] - y[2]) * (y[1] - y[2]); sort(len, len + 3); if (!len[0]) { y[i] += 1; continue; } if (x[0] == x[1] && x[1] == x[2] || y[1] == y[0] && y[1] == y[2]) { y[i] += 1; continue; } if (len[0] + len[1] == len[2]) { puts( ALMOST ); ff = 1; } y[i] += 1; } else if (j == 3) { y[i] += 1; len[0] = (x[1] - x[0]) * (x[1] - x[0]) + (y[1] - y[0]) * (y[1] - y[0]); len[1] = (x[2] - x[0]) * (x[2] - x[0]) + (y[2] - y[0]) * (y[2] - y[0]); len[2] = (x[1] - x[2]) * (x[1] - x[2]) + (y[1] - y[2]) * (y[1] - y[2]); sort(len, len + 3); if (!len[0]) { y[i] -= 1; continue; } if (x[0] == x[1] && x[1] == x[2] || y[1] == y[0] && y[1] == y[2]) { y[i] -= 1; continue; } if (len[0] + len[1] == len[2]) { puts( ALMOST ); ff = 1; } y[i] -= 1; } } } if (!ff) puts( NEITHER ); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long t; cin >> t; while (t--) { long long n; cin >> n; long long arr[n + 5], mx = 0, mn = INT_MIN; for (int i = 0; i < n; i++) cin >> arr[i]; if (arr[n - 1] > 0) arr[n] = -1; else arr[n] = 1; bool p = false, o = false; long long sum = 0; for (int i = 0; i <= n; i++) { if (arr[i] > 0) { if (o) { sum += mn; mn = INT_MIN; } p = true; o = false; mx = max(mx, arr[i]); } else { if (p) { sum += mx; mx = 0; } o = true; p = false; mn = max(mn, arr[i]); } } cout << sum << endl; } return 0; } |
`timescale 1ns / 1ps
`include "Defintions.v"
`define LOOP1 8'd8
`define LOOP2 8'd5
module ROM
(
input wire[15:0] iAddress,
output reg [27:0] oInstruction
);
always @ ( iAddress )
begin
case (iAddress)
0: oInstruction = { `NOP ,24'd4000 };
1: oInstruction = { `STO , `R7,16'b0001 };
2: oInstruction = { `STO ,`R3,16'h1 };
3: oInstruction = { `STO, `R4,16'd1 };
4: oInstruction = { `STO, `R5,16'd0 }; //j
//LOOP2:
5: oInstruction = { `LED ,8'b0,`R7,8'b0 };
6: oInstruction = { `STO ,`R1,16'h0 };
7: oInstruction = { `STO ,`R2,16'd1 };
//LOOP1:
8: oInstruction = { `ADD ,`R1,`R1,`R3 };
9: oInstruction = { `BLE ,`LOOP1,`R1,`R2 };
10: oInstruction = { `ADD ,`R5,`R5,`R3 };
11: oInstruction = { `BLE ,`LOOP2,`R5,`R4 };
12: oInstruction = { `NOP ,24'd4000 };
13: oInstruction = { `ADD ,`R7,`R7,`R3 };
14: oInstruction = { `JMP , 8'd2,16'b0 };
default:
oInstruction = { `LED , 24'b10101010 }; //NOP
endcase
end
endmodule
|
/**
* @module alu_flags
* @author sabertazimi
* @email
* @brief get flags after alu calculation
* @param DATA_WIDTH data width
* @input srcA A port data
* @input srcB B port data
* @input aluop operation code
* @output zero equal flag
* @output of signed overflow flag
* @output uof unsigned overflow flag
*/
module alu_flags
#(parameter DATA_WIDTH = 32)
(
input [DATA_WIDTH-1:0] srcA,
input [DATA_WIDTH-1:0] srcB,
input [3:0] aluop,
output zero,
output of,
output uof
);
wire [DATA_WIDTH-1:0] sum, diff;
wire carry1, carry2;
assign {carry1, sum} = srcA + srcB; // awesome tip
assign {carry2, diff} = srcA - srcB; // awesome tip
assign zero = (srcA == srcB);
assign of = (aluop == 4'd5) ? ((srcA[DATA_WIDTH-1] & srcB[DATA_WIDTH-1] & ~sum[DATA_WIDTH-1]) | (~srcA[DATA_WIDTH-1] & ~srcB[DATA_WIDTH-1] & sum[DATA_WIDTH-1]))
: (aluop == 4'd6) ? ((srcA[DATA_WIDTH-1] & ~srcB[DATA_WIDTH-1] & ~diff[DATA_WIDTH-1]) | (~srcA[DATA_WIDTH-1] & srcB[DATA_WIDTH-1] & diff[DATA_WIDTH-1]))
: 0;
assign uof = (aluop == 4'd5) ? (carry1)
: (aluop == 4'd6) ? (carry2)
: 0;
endmodule // alu_flags
|
//==================================
// dc_planar
// luyanheng
// creat:2014-9-16
// modify:2015-1-9
//==================================
module dc_planar(
rstn,
clk,
counterrun1,
counterrun2,
gx,
gy,
cnt,
blockcnt,
bestmode,
bestmode16,
bestmode32,
modebest,
modebest16,
modebest32,
bestmode_o,
bestmode16_o,
bestmode32_o
);
parameter MODE=21;
parameter DIGIT=0;
parameter DC8=288;
parameter DC16=1152;
parameter DC32=4608;
parameter Plan8=32;
parameter Plan16=32;
parameter Plan32=32;
input rstn;
input clk;
input counterrun1;
input counterrun2;
input signed [10:0] gx;
input signed [10:0] gy;
input [5:0] cnt;
input [6:0] blockcnt;
input [5:0] bestmode;
input [5:0] bestmode16;
input [5:0] bestmode32;
input [MODE-DIGIT:0] modebest;
input [MODE-DIGIT+2:0] modebest16;
input [MODE-DIGIT+4:0] modebest32;
output [5:0] bestmode_o;
output [5:0] bestmode16_o;
output [5:0] bestmode32_o;
reg [10:0] data_tmp;
reg [15:0] modedata;
reg [15:0] modedata8;
reg [17:0] modedata16;
reg [19:0] modedata32;
reg [5:0] bestmode_o;
reg [5:0] bestmode16_o;
reg [5:0] bestmode32_o;
//==================mode data calculation====================================
always@(posedge clk or negedge rstn)
if(!rstn)
data_tmp <= 'd0;
else if(counterrun1)
data_tmp <= (gx[10]?(-gx):gx) + (gy[10]?(-gy):gy);
always@(posedge clk or negedge rstn)
if(!rstn)
modedata <= 'd0;
else if(counterrun2)
modedata <= modedata+data_tmp;
else if(counterrun1)
modedata <= 'd0;
always@(posedge clk or negedge rstn)
if(!rstn)
modedata8 <= 'd0;
else if((blockcnt != 'd0) && (cnt == 'd7))
modedata8 <= modedata;
always@(posedge clk or negedge rstn)
if(!rstn)
modedata16 <= 'd0;
else if((blockcnt != 'd0) && (cnt == 'd8) && (blockcnt[1:0] == 2'b01))
modedata16 <= modedata8;
else if((blockcnt != 'd0) && (cnt == 'd8))
modedata16 <= modedata16+modedata8;
always@(posedge clk or negedge rstn)
if(!rstn)
modedata32 <= 'd0;
else if((blockcnt != 'd0) && (cnt == 'd9) && (blockcnt[3:0] == 4'b0100))
modedata32 <= modedata16;
else if((blockcnt != 'd0) && (cnt == 'd9) && (blockcnt[1:0] == 2'b00))
modedata32 <= modedata32+modedata16;
//================best mode decision============================
always@(posedge clk or negedge rstn)
if(!rstn)
bestmode_o <= 'd0;
else if((modedata8 < DC8) && (blockcnt != 'd0) && (cnt == 'd35))
bestmode_o <= 'd1;
else if((modebest > Plan8 * modedata8) && (blockcnt != 'd0) && (cnt == 'd35))
bestmode_o <= 'd0;
else if((blockcnt != 'd0) && (cnt == 'd35))
bestmode_o <= bestmode;
always@(posedge clk or negedge rstn)
if(!rstn)
bestmode16_o <= 'd0;
else if((modedata16 < DC16) && (blockcnt != 'd0) && (cnt == 'd38) && (blockcnt[1:0] == 2'b00))
bestmode16_o <= 'd1;
else if((modebest16 > Plan16 * modedata16) && (blockcnt != 'd0) && (cnt == 'd38) && (blockcnt[1:0] == 2'b00))
bestmode16_o <= 'd0;
else if((blockcnt != 'd0) && (cnt == 'd38) && (blockcnt[1:0] == 2'b00))
bestmode16_o <= bestmode16;
always@(posedge clk or negedge rstn)
if(!rstn)
bestmode32_o <= 'd0;
else if((modedata32 < DC32) && (blockcnt != 'd0) && (cnt == 'd39) && (blockcnt[3:0] == 4'b0000))
bestmode32_o <= 'd1;
else if((modebest32 > Plan32 * modedata32) && (blockcnt != 'd0) && (cnt == 'd39) && (blockcnt[3:0] == 4'b0000))
bestmode32_o <= 'd0;
else if((blockcnt != 'd0) && (cnt == 'd39) && (blockcnt[3:0] == 4'b0000))
bestmode32_o <= bestmode32;
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Verilog code that really should be replaced with a generate
* statement, but it does not work with some free simulators.
* So I put it in a module so as not to make other code unreadable,
* and keep compatibility with as many simulators as possible.
*/
module hpdmc_obuft4(
input [3:0] T,
input [3:0] I,
output [3:0] O
);
OBUFT obuft0(
.T(T[0]),
.I(I[0]),
.O(O[0])
);
OBUFT obuft1(
.T(T[1]),
.I(I[1]),
.O(O[1])
);
OBUFT obuft2(
.T(T[2]),
.I(I[2]),
.O(O[2])
);
OBUFT obuft3(
.T(T[3]),
.I(I[3]),
.O(O[3])
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); long long int n; cin >> n; long long int a[n]; long long int mx = 0; long long int sum = 0; for (long long int i = 0; i < n; i++) { cin >> a[i]; mx = max(mx, a[i]); sum += a[i]; } long long int aa = sum; long long int bb = n - 1; long long int ans = (aa + bb - 1) / (bb); cout << max(ans, mx) << n ; } |
`timescale 1ps / 1ps
module AXI_DDR2_test(
);
// HELPER
function integer clogb2;
input integer value;
integer i;
begin
clogb2 = 0;
for(i = 0; 2**i < value; i = i + 1)
clogb2 = i + 1;
end
endfunction
localparam tries = 4;
localparam sword = 32;
localparam impl = 0;
localparam syncing = 0;
// Autogen localparams
reg CLK = 1'b0;
reg RST;
// AXI4-lite master memory interfaces
reg axi_awvalid;
wire axi_awready;
reg [sword-1:0] axi_awaddr;
reg [3-1:0] axi_awprot;
reg axi_wvalid;
wire axi_wready;
reg [sword-1:0] axi_wdata;
reg [4-1:0] axi_wstrb;
wire axi_bvalid;
reg axi_bready;
reg axi_arvalid;
wire axi_arready;
reg [sword-1:0] axi_araddr;
reg [3-1:0] axi_arprot;
wire axi_rvalid;
reg axi_rready;
wire [sword-1:0] axi_rdata;
// DDR2 interface
wire [12:0] ddr2_addr;
wire [2:0] ddr2_ba;
wire ddr2_ras_n;
wire ddr2_cas_n;
wire ddr2_we_n;
wire [0:0] ddr2_ck_p;
wire [0:0] ddr2_ck_n;
wire [0:0] ddr2_cke;
wire [0:0] ddr2_cs_n;
wire [1:0] ddr2_dm;
wire [0:0] ddr2_odt;
wire [15:0] ddr2_dq;
wire [1:0] ddr2_dqs_p;
wire [1:0] ddr2_dqs_n;
//integer fd1, tmp1, ifstop;
integer PERIOD = 5000 ;
integer i, error;
AXI_DDR2 inst_AXI_DDR2(
.CLK(CLK),
.RST(RST),
.axi_awvalid(axi_awvalid),
.axi_awready(axi_awready),
.axi_awaddr(axi_awaddr),
.axi_awprot(axi_awprot),
.axi_wvalid(axi_wvalid),
.axi_wready(axi_wready),
.axi_wdata(axi_wdata),
.axi_wstrb(axi_wstrb),
.axi_bvalid(axi_bvalid),
.axi_bready(axi_bready),
.axi_arvalid(axi_arvalid),
.axi_arready(axi_arready),
.axi_araddr(axi_araddr),
.axi_arprot(axi_arprot),
.axi_rvalid(axi_rvalid),
.axi_rready(axi_rready),
.axi_rdata(axi_rdata),
.ddr2_cas_n (ddr2_cas_n),
.ddr2_ras_n (ddr2_ras_n),
.ddr2_we_n (ddr2_we_n),
.ddr2_addr (ddr2_addr[12:0]),
.ddr2_ba (ddr2_ba[2:0]),
.ddr2_ck_n (ddr2_ck_n[0:0]),
.ddr2_ck_p (ddr2_ck_p[0:0]),
.ddr2_cke (ddr2_cke[0:0]),
.ddr2_cs_n (ddr2_cs_n[0:0]),
.ddr2_dm (ddr2_dm[1:0]),
.ddr2_odt (ddr2_odt[0:0]),
.ddr2_dq (ddr2_dq[15:0]),
.ddr2_dqs_n (ddr2_dqs_n[1:0]),
.ddr2_dqs_p (ddr2_dqs_p[1:0])
);
ddr2 inst_ddr2
(
.ck(ddr2_ck_p),
.ck_n(ddr2_ck_n),
.cke(ddr2_cke),
.cs_n(ddr2_cs_n),
.ras_n(ddr2_ras_n),
.cas_n(ddr2_cas_n),
.we_n(ddr2_we_n),
.dm_rdqs(ddr2_dm),
.ba(ddr2_ba),
.addr(ddr2_addr),
.dq(ddr2_dq),
.dqs(ddr2_dqs_p),
.dqs_n(ddr2_dqs_n),
//.rdqs_n(open),
.odt(ddr2_odt)
);
always
begin #(PERIOD/2) CLK = ~CLK; end
task aexpect;
input [sword-1:0] av, e;
begin
if (av == e)
$display ("TIME=%t." , $time, " Actual value of trans=%b, expected is %b. MATCH!", av, e);
else
begin
$display ("TIME=%t." , $time, " Actual value of trans=%b, expected is %b. ERROR!", av, e);
error = error + 1;
end
end
endtask
reg [63:0] xorshift64_state = 64'd88172645463325252;
task xorshift64_next;
begin
// see page 4 of Marsaglia, George (July 2003). "Xorshift RNGs". Journal of Statistical Software 8 (14).
xorshift64_state = xorshift64_state ^ (xorshift64_state << 13);
xorshift64_state = xorshift64_state ^ (xorshift64_state >> 7);
xorshift64_state = xorshift64_state ^ (xorshift64_state << 17);
end
endtask
initial begin
//$sdf_annotate("AXI_SRAM.sdf",AXI_SRAM);
CLK = 1'b0;
RST = 1'b0;
error = 0;
axi_awvalid = 1'b0;
axi_wvalid = 1'b0;
axi_bready = 1'b1;
axi_arvalid = 1'b0;
axi_rready = 1'b1;
axi_awaddr = {sword{1'b0}};
axi_awprot = {3{1'b0}};
axi_wdata = {sword{1'b0}};
axi_wstrb = 4'b1111;
axi_araddr = {sword{1'b0}};
axi_arprot = {3{1'b0}};
#101000;
RST = 1'b1;
//#52500000;
// WRITTING AND READING TEST
// BASICALLY, WHAT I READ, IS WHAT I WRITE
for(i = 0; i < tries; i = i+1) begin
#(PERIOD*8);
// WRITTING TEST
axi_awvalid = 1'b1;
axi_awaddr = i<<2;//xorshift64_state[sword*2-1:sword];
//#PERIOD;
while(!axi_awready) begin
#PERIOD;
end
while(axi_awready) begin
#PERIOD;
end
axi_awvalid = 1'b0;
axi_wvalid = 1'b1;
axi_wdata = xorshift64_state[sword-1:0];
while(!axi_wready) begin
#PERIOD;
end
while(axi_wready) begin
#PERIOD;
end
axi_wvalid = 1'b0;
while(!axi_bvalid) begin
#PERIOD;
end
while(axi_bvalid) begin
#PERIOD;
end
//axi_bready = 1'b1;
#PERIOD;
axi_awvalid = 1'b0;
axi_wvalid = 1'b0;
//axi_bready = 1'b0;
// WRITTING TEST
axi_arvalid = 1'b1;
axi_araddr = i<<2;//xorshift64_state[sword*2-1:sword];
//#PERIOD;
while(!axi_arready) begin
#PERIOD;
end
while(axi_arready) begin
#PERIOD;
end
axi_arvalid = 1'b0;
while(!axi_rvalid) begin
#PERIOD;
end
while(axi_rvalid) begin
#PERIOD;
end
//axi_rready = 1'b1;
#PERIOD;
axi_arvalid = 1'b0;
//axi_rready = 1'b0;
aexpect(axi_rdata, xorshift64_state[sword-1:0]);
xorshift64_next;
end
$timeformat(-9,0,"ns",7);
#(PERIOD*8) if (error == 0)
$display("All match");
else
$display("Mismatches = %d", error);
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<tuple<int, int, int, int> > ask; int mat[105][105]; int main() { int n, m, q, op, r, c, x, i, j; scanf( %d%d%d , &n, &m, &q); for (i = 0; i < q; i++) { scanf( %d , &op); if (op == 1 || op == 2) { scanf( %d , &x); ask.emplace_back(op, x, 0, 0); } else { scanf( %d%d%d , &r, &c, &x); ask.emplace_back(op, r, c, x); } } for (i = ask.size() - 1; i >= 0; i--) { tie(op, r, c, x) = ask[i]; if (op == 1) for (j = m - 1; j >= 1; j--) swap(mat[r][j + 1], mat[r][j]); else if (op == 2) for (j = n - 1; j >= 1; j--) swap(mat[j + 1][r], mat[j][r]); else mat[r][c] = x; } for (i = 1; i <= n; i++) { for (j = 1; j <= m; j++) printf( %d , mat[i][j]); printf( n ); } } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); int n, d; cin >> n >> d; int a[n], sum = 0; for (int i = 0; i < n; i++) cin >> a[i], sum += a[i]; if (sum + 10 * (n - 1) <= d) cout << (d - sum) / 5; else cout << -1; } |
#include <bits/stdc++.h> using namespace std; long long read() { long long x = 0, f = 0; char ch = getchar(); while (!isdigit(ch)) f = ch == - , ch = getchar(); while (isdigit(ch)) x = (x << 1) + (x << 3) + (ch ^ 48), ch = getchar(); return f ? -x : x; } const int N = 1005; int n, k, b; long long a[N][N], c[N][N]; int x[N], y[N]; int main() { k = read(), b = 1 << k; for (int i = (0); i <= (b - 1); i++) for (int j = (0); j <= (b - 1); j++) a[i][j] = read(); n = read(); for (int i = (1); i <= (n); i++) x[i] = read(), y[i] = read(); for (int d = (0); d <= (k - 1); d++) { memset(c, 0, sizeof(c)); for (int i = (0); i <= (b - 1); i++) for (int j = (0); j <= (b - 1); j++) for (int t = (1); t <= (n); t++) c[(i + (x[t] << d)) & (b - 1)][(j + (y[t] << d)) & (b - 1)] ^= a[i][j]; swap(a, c); } int c = 0; for (int i = (0); i <= (b - 1); i++) for (int j = (0); j <= (b - 1); j++) if (a[i][j]) c++; cout << c << endl; return 0; } |
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_uart.v
//
// *Module Description:
// uart peripheral
//
// *Author(s):
// - Windel Bouwman
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
module omsp_uart (
// OUTPUTs
per_dout, // Peripheral data output
// INPUTs
mclk, // Main system clock
per_addr, // Peripheral address
per_din, // Peripheral data input
per_en, // Peripheral enable (high active)
per_we, // Peripheral write enable (high active)
puc_rst // Main system reset
);
// OUTPUTs
//=========
output [15:0] per_dout; // Peripheral data output
// INPUTs
//=========
input mclk; // Main system clock
input [13:0] per_addr; // Peripheral address
input [15:0] per_din; // Peripheral data input
input per_en; // Peripheral enable (high active)
input [1:0] per_we; // Peripheral write enable (high active)
input puc_rst; // Main system reset
//=============================================================================
// 1) PARAMETER DECLARATION
//=============================================================================
// Register base address (must be aligned to decoder bit width)
parameter [14:0] BASE_ADDR = 15'h0060;
// Decoder bit width (defines how many bits are considered for address decoding)
parameter DEC_WD = 3;
// Register addresses offset
parameter [DEC_WD-1:0] CNTRL1 = 'h0,
CNTRL2 = 'h1,
CNTRL3 = 'h2,
TXBUF = 'h7;
// Register one-hot decoder utilities
parameter DEC_SZ = (1 << DEC_WD);
parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1};
// Register one-hot decoder
parameter [DEC_SZ-1:0] CNTRL1_D = (BASE_REG << CNTRL1),
CNTRL2_D = (BASE_REG << CNTRL2),
CNTRL3_D = (BASE_REG << CNTRL3),
TXBUF_D = (BASE_REG << TXBUF );
//============================================================================
// 2) REGISTER DECODER
//============================================================================
// Local register selection
wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
// Register local address
wire [DEC_WD-1:0] reg_addr = {1'b0, per_addr[DEC_WD-2:0]};
// Register address decode
wire [DEC_SZ-1:0] reg_dec = (CNTRL1_D & {DEC_SZ{(reg_addr==(CNTRL1 >>1))}}) |
(CNTRL2_D & {DEC_SZ{(reg_addr==(CNTRL2 >>1))}}) |
(CNTRL3_D & {DEC_SZ{(reg_addr==(CNTRL3 >>1))}}) |
(TXBUF_D & {DEC_SZ{(reg_addr==(TXBUF >>1))}});
// Read/Write probes
wire reg_lo_write = per_we[0] & reg_sel;
wire reg_hi_write = per_we[1] & reg_sel;
wire reg_read = ~|per_we & reg_sel;
// Read/Write vectors
wire [DEC_SZ-1:0] reg_hi_wr = reg_dec & {DEC_SZ{reg_hi_write}};
wire [DEC_SZ-1:0] reg_lo_wr = reg_dec & {DEC_SZ{reg_lo_write}};
wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}};
//============================================================================
// 3) REGISTERS
//============================================================================
// CNTRL1 Register
//-----------------
reg [7:0] cntrl1;
wire cntrl1_wr = CNTRL1[0] ? reg_hi_wr[CNTRL1] : reg_lo_wr[CNTRL1];
wire [7:0] cntrl1_nxt = CNTRL1[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) cntrl1 <= 8'h00;
else if (cntrl1_wr) cntrl1 <= cntrl1_nxt;
// CNTRL2 Register
//-----------------
reg [7:0] cntrl2;
wire cntrl2_wr = CNTRL2[0] ? reg_hi_wr[CNTRL2] : reg_lo_wr[CNTRL2];
wire [7:0] cntrl2_nxt = CNTRL2[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) cntrl2 <= 8'h00;
else if (cntrl2_wr) cntrl2 <= cntrl2_nxt;
// CNTRL3 Register
//-----------------
reg [7:0] cntrl3;
wire cntrl3_wr = CNTRL3[0] ? reg_hi_wr[CNTRL3] : reg_lo_wr[CNTRL3];
wire [7:0] cntrl3_nxt = CNTRL3[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) cntrl3 <= 8'h00;
else if (cntrl3_wr) cntrl3 <= cntrl3_nxt;
// TXBUF Register
//-----------------
reg [7:0] cntrl4;
wire cntrl4_wr = TXBUF[0] ? reg_hi_wr[TXBUF] : reg_lo_wr[TXBUF];
wire [7:0] cntrl4_nxt = TXBUF[0] ? per_din[15:8] : per_din[7:0];
integer fileHandle;
initial begin
fileHandle = $fopen("output.txt", "w");
end
always @ (posedge mclk or posedge puc_rst)
if (puc_rst)
cntrl4 <= 8'h00;
else if (cntrl4_wr)
begin
cntrl4 <= cntrl4_nxt;
if (cntrl4_nxt == 4)
begin
$display("EOT: %b", cntrl4_nxt);
$fclose(fileHandle);
$finish;
end
else
begin
$display("Write serial: %b, %c", cntrl4_nxt, cntrl4_nxt);
$fwrite(fileHandle, "%c", cntrl4_nxt);
end
end
//============================================================================
// 4) DATA OUTPUT GENERATION
//============================================================================
// Data output mux
wire [15:0] cntrl1_rd = {8'h00, (cntrl1 & {8{reg_rd[CNTRL1]}})} << (8 & {4{CNTRL1[0]}});
wire [15:0] cntrl2_rd = {8'h00, (cntrl2 & {8{reg_rd[CNTRL2]}})} << (8 & {4{CNTRL2[0]}});
wire [15:0] cntrl3_rd = {8'h00, (cntrl3 & {8{reg_rd[CNTRL3]}})} << (8 & {4{CNTRL3[0]}});
wire [15:0] cntrl4_rd = {8'h00, (cntrl4 & {8{reg_rd[TXBUF]}})} << (8 & {4{TXBUF[0]}});
wire [15:0] per_dout = cntrl1_rd |
cntrl2_rd |
cntrl3_rd |
cntrl4_rd;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long bef[1000100], af[1000100]; long long calc(long long n) { return (n * (n + 1)) / 2; } int main() { int k; string s; cin >> k >> s; memset(bef, 0, sizeof bef); memset(af, 0, sizeof af); long long last(1000010), cur(1), i(0); vector<int> ones; long long incase(0); while (i < s.size()) { while (s[i] == 0 ) { ++i; ++cur; } incase += calc(cur - 1); if (i < s.size()) { bef[i] = cur; cur = 1; ones.push_back(i); } ++i; } if (!k) { cout << incase; return 0; } i = s.size() - 1; cur = 1; while (i >= 0) { while (s[i] == 0 ) { --i; ++cur; } if (i >= 0) { af[i] = cur; cur = 1; } --i; } long long ans(0); for (int j = 0; j + k - 1 < ones.size(); ++j) { ans += bef[ones[j]] * af[ones[j + k - 1]]; } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); cerr.tie(0); int n, tmp; vector<pair<int, int> > a; cin >> n; for (int i = 0; i < n; i++) cin >> tmp, a.push_back(make_pair(tmp, i + 1)); sort(a.begin(), a.end()); int c1 = 0, c2 = 0, s1 = 0, s2 = 0; vector<int> t1, t2; int l = 0, r = n - 1; while (l <= r) { if (s1 > s2) { if (c2 - c1 <= 0) { c2++; s2 += a[r].first; t2.push_back(a[r].second); r--; } else { c1++; s1 += a[l].first; t1.push_back(a[l].second); l++; } } else { if (c2 - c1 <= 0) { c2++; s2 += a[l].first; t2.push_back(a[l].second); l++; } else { c1++; s1 += a[r].first; t1.push_back(a[r].second); r--; } } } cout << c1 << endl; for (int i = 0; i < c1; i++) cout << t1[i] << ; cout << endl; cout << c2 << endl; for (int i = 0; i < c2; i++) cout << t2[i] << ; return 0; } |
#include <bits/stdc++.h> using namespace std; int const N = 70; int dx[] = {0, 0, 1, -1}; int dy[] = {1, -1, 0, 0}; char s[N][N]; int vis[N][N]; int n, m; int dfs(int x, int y) { if (s[x][y] != # || vis[x][y]) return 0; vis[x][y] = 1; for (int i = 0; i < (4); i++) dfs(x + dx[i], y + dy[i]); return 1; } int main() { scanf( %d%d , &n, &m); for (int i = 0; i < (n); i++) scanf( %s , s[i]); int cnt = 0; for (int i = 0; i < (n); i++) for (int j = 0; j < (m); j++) { if (s[i][j] == . ) continue; cnt++; s[i][j] = . ; int k = 0; memset(vis, 0, sizeof(vis)); for (int d = 0; d < (4); d++) k += dfs(i + dx[d], j + dy[d]); if (k > 1) { puts( 1 ); return 0; } s[i][j] = # ; } printf( %d n , cnt > 2 ? 2 : -1); } |
`timescale 1ns / 1ps
///////////////////////////////////////////////////////////////////////////////////////////
// Company: Digilent Inc.
// Engineer: Andrew Skreen
//
// Create Date: 08/16/2011
// Module Name: display_controller
// Project Name: PmodGYRO_Demo
// Target Devices: Nexys3
// Tool versions: ISE 14.1
// Description: This module formats all data received from the PmodGYRO and
// displays it on the seven segment display (SSD).
//
// Revision History:
// Revision 0.01 - File Created (Andrew Skreen)
// Revision 1.00 - Added Comments and Converted to Verilog (Josh Sackos)
///////////////////////////////////////////////////////////////////////////////////////////
// ==============================================================================
// Define Module
// ==============================================================================
module display_controller(
clk,
rst,
sel,
temp_data,
x_axis,
y_axis,
z_axis,
dp,
an,
seg,
display_sel,
data_out
);
// ==============================================================================
// Port Declarations
// ==============================================================================
input clk;
input rst;
input [1:0] sel;
input [7:0] temp_data;
input [15:0] x_axis;
input [15:0] y_axis;
input [15:0] z_axis;
input display_sel;
output dp;
output [3:0] an;
output [6:0] seg;
output [15:0] data_out;
// ==============================================================================
// Parameters, Registers, and Wires
// ==============================================================================
wire [1:0] control;
wire dclk;
wire [3:0] digit;
wire [15:0] data;
wire dispSel;
wire [3:0] anodes;
wire [3:0] D1;
wire [3:0] D2;
wire [3:0] D3;
wire [3:0] D4;
reg [1:0] nSel;
wire [3:0] an;
// ==============================================================================
// Implementation
// ==============================================================================
//---------------------------------------------------
// Formats data received from PmodGYRO
//---------------------------------------------------
data_controller C0(
.clk(clk),
.dclk(dclk),
.rst(rst),
.display_sel(dispSel),
.sel(sel),
.data(data),
.D1(D1),
.D2(D2),
.D3(D3),
.D4(D4),
.frmt(data_out)
);
//---------------------------------------------------
// Clock for display components
//---------------------------------------------------
display_clk C1(
.clk(clk),
.RST(rst),
.dclk(dclk)
);
//---------------------------------------------------
// Produces anode pattern to illuminate digit on SSD
//---------------------------------------------------
anode_decoder C2(
.anode(anodes),
.control(control)
);
//---------------------------------------------------
// Produces cathode pattern to dipslay digits on SSD
//---------------------------------------------------
seven_seg_decoder C3(
.num_in(digit),
.control(control),
.seg_out(seg),
.display_sel(dispSel)
);
//---------------------------------------------------
// Provides select/control signal
//---------------------------------------------------
two_bit_counter C4(
.dclk(dclk),
.rst(rst),
.control(control)
);
//---------------------------------------------------
// Digit data mux
//---------------------------------------------------
digit_select C5(
.d1(D1),
.d2(D2),
.d3(D3),
.d4(D4),
.control(control),
.digit(digit)
);
//---------------------------------------------------
// Anode for the decimal on SSD
//---------------------------------------------------
decimal_select C6(
.control(control),
.dp(dp)
);
//---------------------------------------------------
// Select temperature or axis data to display
//---------------------------------------------------
data_select C7(
.x_axis(x_axis),
.y_axis(y_axis),
.z_axis(z_axis),
.temp_data(temp_data),
.sel(sel),
.data(data)
);
// Both select bits asserted, temperature selected, display decimal value
assign dispSel = (display_sel == 1'b1 || sel == 2'b11) ? 1'b1 : 1'b0;
// Do not display anything if reset
assign an = (rst == 1'b1) ? 4'b1111 : anodes;
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's IC FSM ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Insn cache state machine ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_ic_fsm.v,v $
// Revision 1.1 2006-12-21 16:46:58 vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.10 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.9 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.8.4.1 2003/07/08 15:36:37 lampret
// Added embedded memory QMEM.
//
// Revision 1.8 2003/06/06 02:54:47 lampret
// When OR1200_NO_IMMU and OR1200_NO_IC are not both defined or undefined at the same time, results in a IC bug. Fixed.
//
// Revision 1.7 2002/03/29 15:16:55 lampret
// Some of the warnings fixed.
//
// Revision 1.6 2002/03/28 19:10:40 lampret
// Optimized cache controller FSM.
//
// Revision 1.1.1.1 2002/03/21 16:55:45 lampret
// First import of the "new" XESS XSV environment.
//
//
// Revision 1.5 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.4 2002/02/01 19:56:54 lampret
// Fixed combinational loops.
//
// Revision 1.3 2002/01/28 01:16:00 lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.2 2002/01/14 06:18:22 lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.9 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from ic.v and ic.v. Fixed CR+LF.
//
// Revision 1.8 2001/10/19 23:28:46 lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.7 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
`define OR1200_ICFSM_IDLE 2'd0
`define OR1200_ICFSM_CFETCH 2'd1
`define OR1200_ICFSM_LREFILL3 2'd2
`define OR1200_ICFSM_IFETCH 2'd3
//
// Data cache FSM for cache line of 16 bytes (4x singleword)
//
module or1200_ic_fsm(
// Clock and reset
clk, rst,
// Internal i/f to top level IC
ic_en, icqmem_cycstb_i, icqmem_ci_i,
tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,
icram_we, biu_read, first_hit_ack, first_miss_ack, first_miss_err,
burst, tag_we
);
//
// I/O
//
input clk;
input rst;
input ic_en;
input icqmem_cycstb_i;
input icqmem_ci_i;
input tagcomp_miss;
input biudata_valid;
input biudata_error;
input [31:0] start_addr;
output [31:0] saved_addr;
output [3:0] icram_we;
output biu_read;
output first_hit_ack;
output first_miss_ack;
output first_miss_err;
output burst;
output tag_we;
//
// Internal wires and regs
//
reg [31:0] saved_addr_r;
reg [1:0] state;
reg [2:0] cnt;
reg hitmiss_eval;
reg load;
reg cache_inhibit;
//
// Generate of ICRAM write enables
//
assign icram_we = {4{biu_read & biudata_valid & !cache_inhibit}};
assign tag_we = biu_read & biudata_valid & !cache_inhibit;
//
// BIU read and write
//
assign biu_read = (hitmiss_eval & tagcomp_miss) | (!hitmiss_eval & load);
//assign saved_addr = hitmiss_eval ? start_addr : saved_addr_r;
assign saved_addr = saved_addr_r;
//
// Assert for cache hit first word ready
// Assert for cache miss first word stored/loaded OK
// Assert for cache miss first word stored/loaded with an error
//
assign first_hit_ack = (state == `OR1200_ICFSM_CFETCH) & hitmiss_eval & !tagcomp_miss & !cache_inhibit & !icqmem_ci_i;
assign first_miss_ack = (state == `OR1200_ICFSM_CFETCH) & biudata_valid;
assign first_miss_err = (state == `OR1200_ICFSM_CFETCH) & biudata_error;
//
// Assert burst when doing reload of complete cache line
//
assign burst = (state == `OR1200_ICFSM_CFETCH) & tagcomp_miss & !cache_inhibit
| (state == `OR1200_ICFSM_LREFILL3);
//
// Main IC FSM
//
always @(posedge clk or posedge rst) begin
if (rst) begin
state <= #1 `OR1200_ICFSM_IDLE;
saved_addr_r <= #1 32'b0;
hitmiss_eval <= #1 1'b0;
load <= #1 1'b0;
cnt <= #1 3'b000;
cache_inhibit <= #1 1'b0;
end
else
case (state) // synopsys parallel_case
`OR1200_ICFSM_IDLE :
if (ic_en & icqmem_cycstb_i) begin // fetch
state <= #1 `OR1200_ICFSM_CFETCH;
saved_addr_r <= #1 start_addr;
hitmiss_eval <= #1 1'b1;
load <= #1 1'b1;
cache_inhibit <= #1 1'b0;
end
else begin // idle
hitmiss_eval <= #1 1'b0;
load <= #1 1'b0;
cache_inhibit <= #1 1'b0;
end
`OR1200_ICFSM_CFETCH: begin // fetch
if (icqmem_cycstb_i & icqmem_ci_i)
cache_inhibit <= #1 1'b1;
if (hitmiss_eval)
saved_addr_r[31:13] <= #1 start_addr[31:13];
if ((!ic_en) ||
(hitmiss_eval & !icqmem_cycstb_i) || // fetch aborted (usually caused by IMMU)
(biudata_error) || // fetch terminated with an error
(cache_inhibit & biudata_valid)) begin // fetch from cache-inhibited page
state <= #1 `OR1200_ICFSM_IDLE;
hitmiss_eval <= #1 1'b0;
load <= #1 1'b0;
cache_inhibit <= #1 1'b0;
end
else if (tagcomp_miss & biudata_valid) begin // fetch missed, finish current external fetch and refill
state <= #1 `OR1200_ICFSM_LREFILL3;
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
hitmiss_eval <= #1 1'b0;
cnt <= #1 `OR1200_ICLS-2;
cache_inhibit <= #1 1'b0;
end
else if (!tagcomp_miss & !icqmem_ci_i) begin // fetch hit, finish immediately
saved_addr_r <= #1 start_addr;
cache_inhibit <= #1 1'b0;
end
else if (!icqmem_cycstb_i) begin // fetch aborted (usually caused by exception)
state <= #1 `OR1200_ICFSM_IDLE;
hitmiss_eval <= #1 1'b0;
load <= #1 1'b0;
cache_inhibit <= #1 1'b0;
end
else // fetch in-progress
hitmiss_eval <= #1 1'b0;
end
`OR1200_ICFSM_LREFILL3 : begin
if (biudata_valid && (|cnt)) begin // refill ack, more fetchs to come
cnt <= #1 cnt - 3'd1;
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
end
else if (biudata_valid) begin // last fetch of line refill
state <= #1 `OR1200_ICFSM_IDLE;
saved_addr_r <= #1 start_addr;
hitmiss_eval <= #1 1'b0;
load <= #1 1'b0;
end
end
default:
state <= #1 `OR1200_ICFSM_IDLE;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; bool isprime(long long int n) { if (n <= 1) return false; if (n <= 3) return true; if (n % 2 == 0 || n % 3 == 0) return false; for (int i = 5; i * i <= n; i = i + 6) if (n % i == 0 || n % (i + 2) == 0) return false; return true; } vector<long long int> prime; void sieve(long long int n) { bool bakh[n + 1]; memset(bakh, true, sizeof(bakh)); for (long long int p = 2; p * p <= n; p++) { if (bakh[p] == true) { for (long long int i = p * p; i <= n; i += p) bakh[i] = false; } } for (long long int p = 2; p <= n; p++) if (bakh[p]) prime.push_back(p); } long long int eulertotient(long long int z) { long long int fac = z; for (long long int i = 0; prime[i] * prime[i] <= z; i++) { if (z % prime[i] == 0) { fac -= (fac / prime[i]); while (z % prime[i] == 0) z /= prime[i]; } } if (z > 1) fac -= (fac / z); return fac; } long long int power(long long int x, long long int y, long long int p) { long long int res = 1; x = x % p; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res; } long long int gcd(long long int a, long long int b) { if (a == 0) return b; return gcd(b % a, a); } long long int lcm(long long int a, long long int b) { long long int g = gcd(a, b); long long int ans = (a * b) / g; return ans; } long long int modInverse(long long int a, long long int m) { long long int hvf = gcd(a, m); if (hvf == 1) return power(a, m - 2, m); return -1; } void multiply(long long int F[2][2], long long int M[2][2]) { long long int x = F[0][0] * M[0][0] + F[0][1] * M[1][0]; long long int y = F[0][0] * M[0][1] + F[0][1] * M[1][1]; long long int z = F[1][0] * M[0][0] + F[1][1] * M[1][0]; long long int w = F[1][0] * M[0][1] + F[1][1] * M[1][1]; F[0][0] = x; F[0][1] = y; F[1][0] = z; F[1][1] = w; } void powermat(long long int F[2][2], long long int n) { if (n == 0 || n == 1) return; long long int M[2][2] = {{1, 1}, {1, 0}}; powermat(F, n / 2); multiply(F, F); if (n % 2 != 0) multiply(F, M); } long long int fib(long long int n) { long long int F[2][2] = {{1, 1}, {1, 0}}; if (n == 0) return 0; powermat(F, n - 1); return F[0][0]; } long long int col[200005]; bool mark[200005]; vector<long long int> adj[200005]; void dfs(long long int v, long long int p1, long long int p2) { mark[v] = true; col[v] = p2; long long int c = 1; for (long long int i = 0; i < adj[v].size(); i++) { if (!mark[adj[v][i]]) { if (c == p1 || c == p2) c++; if (c == p1 || c == p2) c++; dfs(adj[v][i], p2, c), c++; } } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; long long int n, a, b; cin >> n; for (long long int i = 0; i < n - 1; i++) { cin >> a >> b; adj[a].push_back(b); adj[b].push_back(a); } long long int m = 1; for (long long int i = 1; i <= n; i++) m = max(m, (long long int)adj[i].size() + 1); dfs(1, 1, 1); cout << m << endl; ; for (long long int i = 1; i <= n; i++) cout << col[i] << ; cout << endl; ; } |
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f, oo = inf; inline long long read() { register long long x = 0, f = 1; register char c = getchar(); for (; !isdigit(c); c = getchar()) if (c == - ) f = -1; for (; isdigit(c); c = getchar()) x = (x << 1) + (x << 3) + (c ^ 48); return x * f; } void write(long long x) { if (x < 0) x = -x, putchar( - ); if (x >= 10) write(x / 10); putchar(x % 10 + 0 ); } void writeln(long long x) { write(x); puts( ); } const long long maxn = 200005; long long n, a[maxn], k; bool check(long long m) { long double sum = 0, s; long long p, q; for (register long long i = (0); i < (n); ++i) { if (a[i] == 0) continue; q = n - 1 - i + m - 1; p = m - 1; p = min(p, q - p); s = a[i]; while (p) { s = s * q / p; p--, q--; if (s >= k) return true; } sum += s; if (sum >= k) return true; } return false; } long long solve(long long l, long long r) { long long mid, ans; while (l <= r) { mid = (l + r) >> 1; if (check(mid)) { ans = mid; r = mid - 1; } else l = mid + 1; } return ans; } signed main() { n = read(), k = read(); for (register long long i = (0); i < (n); ++i) { a[i] = read(); if (a[i] >= k) { puts( 0 ); return 0; } } writeln(solve(1, k)); return 0; } |
/*
Copyright (c) 2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for lfsr
*/
module test_lfsr_prbs9;
// Parameters
parameter LFSR_WIDTH = 9;
parameter LFSR_POLY = 9'h021;
parameter LFSR_CONFIG = "FIBONACCI";
parameter LFSR_FEED_FORWARD = 0;
parameter REVERSE = 0;
parameter DATA_WIDTH = 8;
parameter STYLE = "AUTO";
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] data_in = 0;
reg [LFSR_WIDTH-1:0] state_in = 0;
// Outputs
wire [DATA_WIDTH-1:0] data_out;
wire [LFSR_WIDTH-1:0] state_out;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
data_in,
state_in
);
$to_myhdl(
data_out,
state_out
);
// dump file
$dumpfile("test_lfsr_prbs9.lxt");
$dumpvars(0, test_lfsr_prbs9);
end
lfsr #(
.LFSR_WIDTH(LFSR_WIDTH),
.LFSR_POLY(LFSR_POLY),
.LFSR_CONFIG(LFSR_CONFIG),
.LFSR_FEED_FORWARD(LFSR_FEED_FORWARD),
.REVERSE(REVERSE),
.DATA_WIDTH(DATA_WIDTH),
.STYLE(STYLE)
)
UUT (
.data_in(data_in),
.state_in(state_in),
.data_out(data_out),
.state_out(state_out)
);
endmodule
|
#include <bits/stdc++.h> int diru[] = {-1, -1, -1, 0, 0, 1, 1, 1}; int dirv[] = {-1, 0, 1, -1, 1, -1, 0, 1}; using namespace std; template <class T> T sq(T n) { return n * n; } template <class T> T gcd(T a, T b) { return (b != 0 ? gcd<T>(b, a % b) : a); } template <class T> T lcm(T a, T b) { return (a / gcd<T>(a, b) * b); } template <class T> bool inside(T a, T b, T c) { return a <= b && b <= c; } template <class T> void setmax(T &a, T b) { if (a < b) a = b; } template <class T> void setmin(T &a, T b) { if (b < a) a = b; } template <class T> T power(T N, T P) { return (P == 0) ? 1 : N * power(N, P - 1); } pair<int, int> in[110]; int main() { int n, T, t = 1, m, i, j, k; while (scanf( %d , &n) == 1) { scanf( %d , &k); double ans = 0; for (i = 0; i < n; i++) { scanf( %d , &in[i].first); scanf( %d , &in[i].second); } for (i = 1; i < n; i++) { ans += sqrt((double)(( ((in[i].first - in[i - 1].first) * (in[i].first - in[i - 1].first)) + ((in[i].second - in[i - 1].second) * (in[i].second - in[i - 1].second))))); } ans /= (double)50.0; printf( %.15lf n , ans * (double)k); } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, h, t, r, x, y, dis[210][210], h1[210], t1[210], h2[210], t2[210], bfs[210 * 210][2], L, R; void renew(int x, int y, int v) { if (x + y > r) return; if (dis[x][y] == -1) { dis[x][y] = v; bfs[++R][0] = x; bfs[R][1] = y; } } int dfs(int x, int y) { if (x + y > r) return 0; int i, p = 1; if (dis[x][y] == -1) { printf( Draw n ); exit(0); } if (dis[x][y]) return dis[x][y]; dis[x][y] = -1; for (i = 1; i <= n && i <= x; ++i) p = max(p, dfs(x - i + h1[i], y + t1[i]) + 1); for (i = 1; i <= m && i <= y; ++i) p = max(p, dfs(x + h2[i], y - i + t2[i]) + 1); dis[x][y] = p; return p; } int main() { int i; scanf( %d%d%d , &h, &t, &r); scanf( %d , &n); for (i = 1; i <= n; ++i) scanf( %d%d , &h1[i], &t1[i]); scanf( %d , &m); for (i = 1; i <= m; ++i) scanf( %d%d , &h2[i], &t2[i]); memset(dis, -1, sizeof(dis)); dis[h][t] = 0; bfs[L = R = 1][0] = h; bfs[1][1] = t; while (L <= R) { x = bfs[L][0]; y = bfs[L++][1]; for (i = 1; i <= n && i <= x; ++i) renew(x - i + h1[i], y + t1[i], dis[x][y] + 1); for (i = 1; i <= m && i <= y; ++i) renew(x + h2[i], y - i + t2[i], dis[x][y] + 1); } if (dis[0][0] != -1) return printf( Ivan n%d n , dis[0][0]), 0; memset(dis, 0, sizeof(dis)); printf( Zmey n%d n , dfs(h, t)); } |
#include <bits/stdc++.h> using namespace std; int max2[205][6005]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); fill_n(max2[0], 205 * 6005, -1); max2[0][0] = 0; int n, k; cin >> n >> k; for (int i = 0; i < n; i++) { long long int a; cin >> a; int p2 = 0, p5 = 0; while (a % 2 == 0) { a /= 2; p2++; } while (a % 5 == 0) { a /= 5; p5++; } for (int pos = k - 1; pos >= 0; pos--) { for (int s = p5; s < 6005; s++) { if (max2[pos][s - p5] != -1) { max2[pos + 1][s] = max(max2[pos + 1][s], max2[pos][s - p5] + p2); } } } } int best = 0; for (int i = 0; i < 6005; i++) { best = max(best, min(i, max2[k][i])); } cout << best << n ; return 0; } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: playback_driver.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module playback_driver();
parameter inputwidth=157;
parameter outputwidth=130;
parameter clockwidth=1;
reg [256*8-1:0] stimfile;
reg [256*8-1:0] iofile;
initial begin
stimfile = "not_provided";
if($test$plusargs("stim_file")) begin
$value$plusargs("stim_file=%s", stimfile);
end
end
reg [inputwidth-1:0] input_vector;
reg [inputwidth-1:0] input_vector_a;
reg [outputwidth-1:0] output_vector_ref;
reg clock_vector;
initial begin
clock_vector = 1'b0;
forever #418 clock_vector = ~clock_vector;
end
integer fid, code;
integer mismatch;
initial begin
fid = $fopen(stimfile, "r");
end
always @(posedge clock_vector) begin
#20;
input_vector = input_vector_a;
code = $fscanf(fid, "%b\n", input_vector_a);
if(code == 0 || code == -1) begin
if(mismatch == 0)
$display("Playback PASSED!");
else
$display("Playback FAILED with %1d mismatches!", mismatch);
$finish;
end
@(negedge clock_vector);
#1;
$fscanf(fid, "%b\n", output_vector_ref);
end
task displayMismatch;
input [7:0] port;
input exp;
input got;
begin
if(port < 124) begin
$display("spc_pcx_data_pa[%3d]: Expect:%b Got:%b",port, exp , got);
end else
if(port < 125) begin
$display("spc_pcx_atom_pq : Expect:%b Got:%b", exp , got);
end else begin
$display("spc_pcx_req_pq[%1d] : Expect:%b Got:%b", port-125,exp , got);
end
end
endtask
wire [outputwidth-1:0] output_vector;
reg [outputwidth-1:0] output_vector_mask;
wire [outputwidth-1:0] output_vector_masked;
wire [outputwidth-1:0] output_vector_ref_masked;
// WIRE Definitions for remove
wire spc_sscan_so;
wire spc_scanout0;
wire spc_scanout1;
wire tst_ctu_mbist_done;
wire tst_ctu_mbist_fail;
wire spc_efc_ifuse_data;
wire spc_efc_dfuse_data;
// WIRE Definitions for constraint
wire [3:0] const_cpuid = 4'b0000;
wire [7:0] const_maskid = 8'h20;
wire ctu_tck = 1'b0;
wire ctu_sscan_se = 1'b0;
wire ctu_sscan_snap = 1'b0;
wire [3:0] ctu_sscan_tid = 4'h1;
wire ctu_tst_mbist_enable = 1'b0;
wire efc_spc_fuse_clk1 = 1'b0;
wire efc_spc_fuse_clk2 = 1'b0;
wire efc_spc_ifuse_ashift = 1'b0;
wire efc_spc_ifuse_dshift = 1'b0;
wire efc_spc_ifuse_data = 1'b0;
wire efc_spc_dfuse_ashift = 1'b0;
wire efc_spc_dfuse_dshift = 1'b0;
wire efc_spc_dfuse_data = 1'b0;
wire ctu_tst_macrotest = 1'b0;
wire ctu_tst_scan_disable = 1'b0;
wire ctu_tst_short_chain = 1'b0;
wire global_shift_enable = 1'b0;
wire ctu_tst_scanmode = 1'b0;
wire spc_scanin0 = 1'b0;
wire spc_scanin1 = 1'b0;
// WIRE Definitions for clock
wire gclk;
// WIRE Definitions for input
wire [4:0] pcx_spc_grant_px;
wire cpx_spc_data_rdy_cx2;
wire [144:0] cpx_spc_data_cx2;
wire cluster_cken;
wire cmp_grst_l;
wire cmp_arst_l;
wire ctu_tst_pre_grst_l;
wire adbginit_l;
wire gdbginit_l;
// WIRE Definitions for output
wire [4:0] spc_pcx_req_pq;
wire spc_pcx_atom_pq;
wire [123:0] spc_pcx_data_pa;
// WIRE Definitions for inout
sparc sparc0 (
.spc_pcx_req_pq (spc_pcx_req_pq),
.spc_pcx_atom_pq (spc_pcx_atom_pq),
.spc_pcx_data_pa (spc_pcx_data_pa),
.spc_sscan_so (spc_sscan_so),
.spc_scanout0 (spc_scanout0),
.spc_scanout1 (spc_scanout1),
.tst_ctu_mbist_done (tst_ctu_mbist_done),
.tst_ctu_mbist_fail (tst_ctu_mbist_fail),
.spc_efc_ifuse_data (spc_efc_ifuse_data),
.spc_efc_dfuse_data (spc_efc_dfuse_data),
.pcx_spc_grant_px (pcx_spc_grant_px),
.cpx_spc_data_rdy_cx2 (cpx_spc_data_rdy_cx2),
.cpx_spc_data_cx2 (cpx_spc_data_cx2),
.const_cpuid (const_cpuid),
.const_maskid (const_maskid),
.ctu_tck (ctu_tck),
.ctu_sscan_se (ctu_sscan_se),
.ctu_sscan_snap (ctu_sscan_snap),
.ctu_sscan_tid (ctu_sscan_tid),
.ctu_tst_mbist_enable (ctu_tst_mbist_enable),
.efc_spc_fuse_clk1 (efc_spc_fuse_clk1),
.efc_spc_fuse_clk2 (efc_spc_fuse_clk2),
.efc_spc_ifuse_ashift (efc_spc_ifuse_ashift),
.efc_spc_ifuse_dshift (efc_spc_ifuse_dshift),
.efc_spc_ifuse_data (efc_spc_ifuse_data),
.efc_spc_dfuse_ashift (efc_spc_dfuse_ashift),
.efc_spc_dfuse_dshift (efc_spc_dfuse_dshift),
.efc_spc_dfuse_data (efc_spc_dfuse_data),
.ctu_tst_macrotest (ctu_tst_macrotest),
.ctu_tst_scan_disable (ctu_tst_scan_disable),
.ctu_tst_short_chain (ctu_tst_short_chain),
.global_shift_enable (global_shift_enable),
.ctu_tst_scanmode (ctu_tst_scanmode),
.spc_scanin0 (spc_scanin0),
.spc_scanin1 (spc_scanin1),
.cluster_cken (cluster_cken),
.gclk (gclk),
.cmp_grst_l (cmp_grst_l),
.cmp_arst_l (cmp_arst_l),
.ctu_tst_pre_grst_l (ctu_tst_pre_grst_l),
.adbginit_l (adbginit_l),
.gdbginit_l (gdbginit_l)
);
task generate_mask;
integer i;
begin
for(i=0;i<outputwidth;i=i+1)
output_vector_mask[i] = (output_vector_ref[i] === 1'b0) | (output_vector_ref[i] === 1'b1);
end
endtask
assign {pcx_spc_grant_px, cpx_spc_data_rdy_cx2, cpx_spc_data_cx2, cluster_cken, cmp_grst_l, cmp_arst_l, ctu_tst_pre_grst_l, adbginit_l, gdbginit_l} = input_vector;
assign {gclk} = clock_vector;
assign output_vector = {spc_pcx_req_pq, spc_pcx_atom_pq, spc_pcx_data_pa};
assign output_vector_ref_masked = output_vector_ref & output_vector_mask;
assign output_vector_masked = output_vector & output_vector_mask;
always @(output_vector_ref)
generate_mask;
integer i;
initial generate_mask;
initial mismatch = 0;
always @(negedge gclk) begin
if(output_vector_ref_masked !== output_vector_masked) begin
mismatch = mismatch + 1;
for(i=0;i<outputwidth;i=i+1)
if(output_vector_ref_masked[i] !== output_vector_masked[i])
displayMismatch(i, output_vector_ref_masked[i], output_vector_masked[i]);
$display("Number of cycles mismatched %d\n",mismatch);
end
end
endmodule
module cmp_top();
playback_driver iop();
`ifdef DUMP_ON
initial
if($test$plusargs("dump"))
$fsdbDumpvars(0, cmp_top.iop);
`endif
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A222OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__A222OI_BEHAVIORAL_PP_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__a222oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
C2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input C2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire nand2_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
nand nand2 (nand2_out , C2, C1 );
and and0 (and0_out_Y , nand0_out, nand1_out, nand2_out);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND );
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A222OI_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; int gl, gr, bl, br; bool check(int g, int b) { if (g - 1 <= b && b <= 2 * (g + 1)) return true; else return false; } int main() { scanf( %d %d %d %d , &gl, &gr, &bl, &br); if (check(gl, br) || check(gr, bl)) cout << YES << endl; else cout << NO << endl; return 0; } |
// Explore how procedural concatenations work in various contexts.
// Some of the checks are specific to the 1364-2005 standard.
//
// Cary R.
module main;
reg pass;
reg [31:0] a_c, b_c, c_c, d_c, a_r, b_r, c_r, d_r;
reg [127:0] y_c;
integer seed, fres;
// These will have the following value depending on the order.
// 1 = LSB->MSB, 2 = MSB->LSB, 3 = indeterminate.
integer sorder, uorder;
initial begin
pass = 1'b1;
/**********
* Try to find the order using $random.
**********/
// Start from a known place.
seed = 0;
y_c = {$random(seed), $random(seed), $random(seed), $random(seed)};
a_c = y_c[31:0];
b_c = y_c[63:32];
c_c = y_c[95:64];
d_c = y_c[127:96];
// Make the reference values in a known order.
seed = 0;
a_r = $random(seed);
b_r = $random(seed);
c_r = $random(seed);
d_r = $random(seed);
if (a_c === a_r && b_c === b_r && c_c === c_r && d_c == d_r) begin
$display("Concatenation of system functions is LSB -> MSB.");
sorder = 1;
end else if (a_c === d_r && b_c === c_r && c_c === b_r && d_c == a_r) begin
$display("Concatenation of system functions is MSB -> LSB.");
sorder = 2;
end else if ((a_c === a_r || a_c === b_r || a_c === c_r || a_c == d_r) &&
(b_c === a_r || b_c === b_r || b_c === c_r || b_c == d_r) &&
(c_c === a_r || c_c === b_r || c_c === c_r || c_c == d_r) &&
(d_c === a_r || d_c === b_r || d_c === c_r || d_c == d_r))
begin
$display("Concatenation of system functions is indeterminate.");
$display(" check:",, d_c,, c_c,, b_c,, a_c);
$display(" ref.:",, d_r,, c_r,, b_r,, a_r);
sorder = 3;
end else begin
$display("FAILED: system function concatenation order.");
$display(" check:",, d_c,, c_c,, b_c,, a_c);
$display(" ref.:",, d_r,, c_r,, b_r,, a_r);
pass = 1'b0;
end
/**********
* Try to find the order using ufunc().
**********/
// Start from a known place.
fres = 0;
y_c = {ufunc(0), ufunc(0), ufunc(0), ufunc(0)};
a_c = y_c[31:0];
b_c = y_c[63:32];
c_c = y_c[95:64];
d_c = y_c[127:96];
// Make the reference values in a known order.
fres = 0;
a_r = ufunc(0);
b_r = ufunc(0);
c_r = ufunc(0);
d_r = ufunc(0);
if (a_c === a_r && b_c === b_r && c_c === c_r && d_c == d_r) begin
$display("Concatenation of user functions is LSB -> MSB.");
uorder = 1;
end else if (a_c === d_r && b_c === c_r && c_c === b_r && d_c == a_r) begin
$display("Concatenation of user functions is MSB -> LSB.");
uorder = 2;
end else if ((a_c === a_r || a_c === b_r || a_c === c_r || a_c == d_r) &&
(b_c === a_r || b_c === b_r || b_c === c_r || b_c == d_r) &&
(c_c === a_r || c_c === b_r || c_c === c_r || c_c == d_r) &&
(d_c === a_r || d_c === b_r || d_c === c_r || d_c == d_r))
begin
$display("Concatenation of user functions is indeterminate.");
$display(" check:",, d_c,, c_c,, b_c,, a_c);
$display(" ref.:",, d_r,, c_r,, b_r,, a_r);
uorder = 3;
end else begin
$display("FAILED: user function concatenation order.");
$display(" check:",, d_c,, c_c,, b_c,, a_c);
$display(" ref.:",, d_r,, c_r,, b_r,, a_r);
pass = 1'b0;
end
if (sorder != uorder) begin
$display("WARNING: system functions and user functions have a ",
"different order.");
end
/**********
* Check to see if extra system functions are called and ignored.
* We do not care about the order for this test.
**********/
// Start from a known place.
seed = 0;
// You must run the extra $random(), but drop the result.
c_c = {$random(seed), $random(seed), $random(seed), $random(seed),
$random(seed), $random(seed)};
a_c = $random(seed);
// Make the reference values in a known order.
seed = 0;
a_r = $random(seed);
a_r = $random(seed);
a_r = $random(seed);
a_r = $random(seed);
a_r = $random(seed);
a_r = $random(seed);
a_r = $random(seed);
if (a_c !== a_r) begin
$display("FAILED: extra system functions in a concat. are not run.");
pass = 1'b0;
end
/**********
* Check to see if extra user functions are called and ignored.
* We do not care about the order for this test.
**********/
// Start from a known place.
fres = 0;
y_c = {ufunc(0), ufunc(0), ufunc(0), ufunc(0), ufunc(0), ufunc(0)};
if (fres != 6) begin
$display("FAILED: extra user functions in a concat. are not run.");
pass = 1'b0;
end
// Icarus handles this in a different way so check it as well.
// Start from a known place.
fres = 0;
y_c = check_64({ufunc(0), ufunc(0), ufunc(0)});
if (fres != 3) begin
$display("FAILED: extra ufunc in a concat. as an argument are not run.");
pass = 1'b0;
end
/**********
* Check to see if a system function replicated 0 times is done correctly.
**********/
// Start from a known place.
seed = 0;
// You must run the zero replication system call and then ignore it.
a_c = {{0{$random(seed)}}, $random(seed)};
a_c = $random(seed);
// Make a reference value.
seed = 0;
a_r = $random(seed);
a_r = $random(seed);
a_r = $random(seed);
if (a_c !== a_r) begin
$display("FAILED: zero repl. system functions in a concat. are not run.");
pass = 1'b0;
end
/**********
* Check to see if a user function replicated 0 times is done correctly.
**********/
// Start from a known place.
fres = 0;
// You must run the zero replication user call and then ignore it.
a_c = {{0{ufunc(0)}}, ufunc(0)};
if (fres != 2) begin
$display("FAILED: zero repl. user functions in a concat. are not run.");
pass = 1'b0;
end
/**********
* Check a simple replication of $random().
**********/
// Start from a known place.
seed = 0;
// This must run $random() only once.
y_c = {4{$random(seed)}};
a_c = y_c[31:0];
b_c = y_c[63:32];
c_c = y_c[95:64];
d_c = y_c[127:96];
// Start from a known place.
seed = 0;
a_r = $random(seed);
b_r = a_r;
c_r = a_r;
d_r = a_r;
if (a_c !== a_r || b_c !== b_r || c_c !== c_r || d_c !== d_r) begin
$display("FAILED $random() replication, each replication is different.");
pass = 1'b0;
end
/**********
* Check a replication of ufunc().
**********/
// Start from a known place.
fres = 0;
// This must run ufunc() only once.
y_c = {4{ufunc(0)}};
a_c = y_c[31:0];
b_c = y_c[63:32];
c_c = y_c[95:64];
d_c = y_c[127:96];
// Start from a known place.
fres = 0;
a_r = ufunc(0);
b_r = a_r;
c_r = a_r;
d_r = a_r;
if (a_c !== a_r || b_c !== b_r || c_c !== c_r || d_c !== d_r) begin
$display("FAILED ufunc() replication, each replication is different.");
pass = 1'b0;
end
/*
* A concatenation as an argument needs to pad or select as needed.
* We only check ufunc since it should be the same as $random and
* it has been tested above.
*/
/**********
* Check that a concat is zero extended.
**********/
// Start from a known place.
fres = 0;
y_c = check_64({ufunc(1)});
a_c = y_c[31:0];
b_c = y_c[63:32];
c_c = y_c[95:64];
d_c = y_c[127:96];
// Start from a known place.
fres = 0;
a_r = ufunc(1);
b_r = 32'h0;
c_r = 32'h0;
d_r = 32'h0;
if (a_c !== a_r || b_c !== b_r || c_c !== c_r || d_c !== d_r) begin
$display("FAILED padded user function concatenation.");
$displayh(" check:",, d_c,, c_c,, b_c,, a_c);
$displayh(" ref.:",, d_r,, c_r,, b_r,, a_r);
pass = 1'b0;
end
/**********
* Check that a $signed concat is sign extended.
**********/
// Start from a known place.
fres = 0;
y_c = check_64($signed({ufunc(1)}));
a_c = y_c[31:0];
b_c = y_c[63:32];
c_c = y_c[95:64];
d_c = y_c[127:96];
// Start from a known place.
fres = 0;
a_r = ufunc(1);
b_r = 32'hffffffff;
c_r = 32'h0;
d_r = 32'h0;
if (a_c !== a_r || b_c !== b_r || c_c !== c_r || d_c !== d_r) begin
$display("FAILED sign padded user function concatenation.");
$displayh(" check:",, d_c,, c_c,, b_c,, a_c);
$displayh(" ref.:",, d_r,, c_r,, b_r,, a_r);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
function [63:0] check_64;
input [63:0] in;
check_64 = in;
endfunction
// This user function has a side effect (fres) so the result is call
// order dependent.
function integer ufunc;
input in;
begin
if (in) fres = fres - 1;
else fres = fres + 1;
ufunc = fres;
end
endfunction
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; for (int i = 0; i < t; ++i) { int n; cin >> n; string s; cin >> s; int sum(0), pos(-1), pos1(-1), ot(-1), num(0); for (int i = 0; i < s.length(); ++i) sum += (s[i] - 0 ); for (int i = 0; i < s.length(); ++i) { if ((s[i] - 0 ) % 2) { pos = i; num = s[i] - 0 ; } } for (int i = 0; i < s.length(); ++i) { if ((s[i] - 0 ) % 2 == 0) pos1 = i; else if ((s[i] - 0 ) % 2 && i != pos) ot = s[i] - 0 ; } if (n == 1 || pos == -1) cout << -1 << n ; else if (pos1 == -1) { if (n % 2 == 0) cout << s << n ; else { s.erase(s.begin() + 0); cout << s << n ; } } else if (ot != -1) cout << ot * 10 + num << n ; else if (ot == -1) cout << -1 << n ; } } |
#include <bits/stdc++.h> using namespace std; int main() { int n, a1, a2, b1, b2, k = 1, f = 0, ans = 0; scanf( %d , &n); while (k <= 4) { scanf( %d%d%d%d , &a1, &a2, &b1, &b2); if (n >= a1 + b1 || n >= a1 + b2) ans = a1; else if (n >= a2 + b1 || n >= a2 + b2) ans = a2; if (ans > 0) { f = 1; printf( %d %d %d , k, ans, n - ans); break; } k++; } if (f == 0) printf( -1 ); return 0; } |
#include <bits/stdc++.h> using namespace std; const double PI = 2.0 * acos(0.0); const double EPS = 1e-6; int dp[100005]; static int topp; void LIS(int x) { if (topp == 0) dp[topp++] = x; else if (x > dp[topp - 1]) dp[topp++] = x; else { int left = 0, right = topp; while (left < right) { int mid = (left + right) >> 1; if (dp[mid] > x) right = mid; else left = mid + 1; } while (left < topp - 1 && dp[left] == dp[left + 1]) left++; dp[left] = x; } } int main() { int n; scanf( %d , &n); ::topp = 0; for (int i = 0; i < n; i++) { int a; scanf( %d , &a); LIS(a); } printf( %d n , topp); return 0; } |
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