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#include <bits/stdc++.h> using namespace std; const int N = 100010; int n; double f1[N], f2[N], f3[N], a[N], ans; int main() { ios::sync_with_stdio(false); cin >> n; for (int i = 1; i <= n; ++i) { cin >> a[i]; f1[i] = a[i] * (f1[i - 1] + 1); f2[i] = a[i] * (f2[i - 1] + 1 + 2 * f1[i - 1]); f3[i] = a[i] * (f3[i - 1] + 3 * f2[i - 1] + 3 * f1[i - 1] + 1); } for (int i = 1; i <= n + 1; ++i) ans += (1 - a[i]) * f2[i - 1]; printf( %.10lf n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, m; int gcd(long long a, long long b) { if (!b) return a; return gcd(b, a % b); } int main() { ios_base::sync_with_stdio(false); cin.tie(0), cout.tie(0); long long a, b = 0, c = 0, t, lj = 0, k = 0, r = 0, l = 0, sum = 0, rr, mn = LLONG_MAX, mx = LLONG_MIN, w, y = 0, x = 0, d, neg = 0, pos = 0, ans = 0; string s5 = , s2 = , s3 = , s1 = , s = ; map<char, long long> mp; cin >> a >> b >> x >> y; c = gcd(x, y); while (c != 1) { x /= c; y /= c; c = gcd(x, y); } cout << min(b / y, a / x); } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int qtn; cin >> qtn; vector<long long int> resp(qtn + 1); resp[qtn] = 1000000000000000010; for (int i = 0; i < qtn >> 1; i++) { long long int n; cin >> n; resp[qtn - i - 1] = min(resp[qtn - i], n); resp[i] = n - resp[qtn - i - 1]; if (i) { if (resp[i] < resp[i - 1]) { resp[i] = resp[i - 1]; resp[qtn - i - 1] = n - resp[i]; } } } for (int i = 0; i < qtn; i++) { cout << resp[i] << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 2505; int n, a[N][N]; struct node { int x, y, v; node() {} node(int _x, int _y, int _v) : x(_x), y(_y), v(_v) {} bool operator<(const node k) const { return v < k.v; } }; vector<node> p; bitset<N> r[N], c[N], t; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) scanf( %d , &a[i][j]); for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { if (a[i][j] != a[j][i]) { puts( NOT MAGIC ); return 0; } if (i == j && a[i][j]) { puts( NOT MAGIC ); return 0; } p.push_back(node(i, j, a[i][j])); } } sort(p.begin(), p.end()); for (int i = 0, j; i < p.size(); i = j) { j = i; while (j < p.size() && p[j].v == p[i].v) j++; for (int k = i; k < j; k++) { int x = p[k].x, y = p[k].y; t = r[x] & c[y]; if (t.count()) { puts( NOT MAGIC ); return 0; } } for (int k = i; k < j; k++) { int x = p[k].x, y = p[k].y; r[x][y] = c[y][x] = 1; } } puts( MAGIC ); return 0; } |
#include <bits/stdc++.h> using namespace std; vector<int> adj[3003]; int cost[3003], par[3003]; bool vis[3003]; map<pair<int, int>, bool> mark; void path(int x, int y) { if (x == y) return; cost[x] = 0; path(par[x], y); } void dfs(int u) { vis[u] = true; for (int v : adj[u]) { if (vis[v]) { if (par[u] != v) { cost[v] = 0; if (!mark[{u, v}]) { path(u, v); mark[{u, v}] = mark[{v, u}] = true; } } } else par[v] = u, dfs(v); } } void bfs(int src) { queue<int> q; q.push(src); while (q.size()) { int u = q.front(); q.pop(); for (int v : adj[u]) { if (cost[v] == -1) { cost[v] = cost[u] + 1; q.push(v); } } } } int main() { int n, x, y; cin >> n; for (int i = 0; i < n; i++) { cin >> x >> y; adj[x].push_back(y); adj[y].push_back(x); } memset(cost, -1, sizeof cost); par[1] = 1; dfs(1); memset(vis, false, sizeof vis); for (int i = 1; i <= n; i++) { if (cost[i] == 0) bfs(i); } for (int i = 1; i <= n; i++) cout << cost[i] << ; } |
module testbench_CSA();
parameter bits = 4;
reg [bits-1:0] a;
reg [bits-1:0] b;
reg [bits-1:0] cin;
wire [bits-1:0] sum;
wire [bits-1:0] cout;
integer i;
integer j;
integer k;
integer errorFlag = 0;
reg [bits-1:0] expectSum;
reg [bits-1:0] expectCout;
initial begin
for(i = 0;i < (1<<bits-1); i = i+1) begin
a = i;
for(i = 0;i < (1<<bits-1); i = i+1) begin
b = j;
for(i = 0;i < (1<<bits-1); i = i+1) begin
cin = k;
#1;
expectSum = (i^j^k);
expectCout = (i&j)|(i&k)|(j&k);
if( ( sum !== expectSum ) || ( cout !== expectCout ) ) begin
$display("%x + %x + %x, expect: sum = %x, cout = %x; actual sum = %x, cout = %x", i, j, k, expectSum, expectCout, sum, cout);
errorFlag = 1;
end
end
end
end
if (errorFlag === 0) begin
$display("Test passed.");
end
else begin
$display("Test failed.");
end
end
CSA #bits csa(.a(a), .b(b), .cin(cin), .sum(sum), .cout(cout));
endmodule
|
#include <bits/stdc++.h> template <class t> inline void read(t &s) { s = 0; register int f = 1; register char c = getchar(); while (!isdigit(c)) { if (c == - ) f = -1; c = getchar(); } while (isdigit(c)) s = (s << 3) + (s << 1) + (c ^ 48), c = getchar(); s *= f; return; } template <class t, class... A> inline void read(t &x, A &...a) { read(x); read(a...); } template <class t> inline void write(t x) { if (x < 0) putchar( - ), x = -x; int buf[21], top = 0; while (x) buf[++top] = x % 10, x /= 10; if (!top) buf[++top] = 0; while (top) putchar(buf[top--] ^ 0 ); return; } inline void setIn(std::string s) { freopen(s.c_str(), r , stdin); return; } inline void setOut(std::string s) { freopen(s.c_str(), w , stdout); return; } inline void setIO(std::string s = ) { setIn(s + .in ); setOut(s + .out ); return; } template <class t> inline bool ckmin(t &x, t y) { if (x > y) { x = y; return 1; } return 0; } template <class t> inline bool ckmax(t &x, t y) { if (x < y) { x = y; return 1; } return 0; } inline int lowbit(int x) { return x & (-x); } long double f[105], g[105]; int to[105]; inline int id(int x, int y) { if (x & 1) return (10 - x) * 10 + 11 - y; return (10 - x) * 10 + y; } signed main(void) { register int x; for (int i = 1; i <= 10; ++i) for (int j = 1; j <= 10; ++j) { read(x); if (x) to[id(i, j)] = id(i - x, j); } for (int i = 0; i <= 100; ++i) g[i] = 1e18; f[100] = 0; for (int i = 94; i <= 99; ++i) f[i] = 6; for (int i = 93; i; --i) { for (int j = 1; j <= 6; ++j) f[i] += std::min(f[i + j], g[i + j]) + 1; f[i] /= 6.0; if (to[i]) ckmin(g[i], f[to[i]]); } std::printf( %.99Lf n , std::min(f[1], g[1])); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O311A_BLACKBOX_V
`define SKY130_FD_SC_LS__O311A_BLACKBOX_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o311a (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O311A_BLACKBOX_V
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:00:17 07/29/2011
// Design Name:
// Module Name: Sora_FRL_STATUS_IN
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////
/////
///// Decode four patterns for specific states
///// Idle 00000000
///// Reset 01010101
///// FIFO full 00001111
///// Training_done 00110011
/////
/////////////////////////////////////////////////////////////////////////////////
module Sora_FRL_STATUS_decoder(
input clk,
// input rst, // no need for a reset signal since these's no internal state
// input from STATUS line
input status_in,
// four output states
output reg RST_state,
output reg TRAININGDONE_state,
output reg IDLE_state,
output reg FIFOFULL_state,
// error state
output reg error_state
);
reg ambiguity; // indicates ambiguous status
reg [3:0] error_cnt;
reg [7:0] shift_reg;
parameter IDLE = 4'b0001;
parameter RST = 4'b0010;
parameter FIFOFULL = 4'b0100;
parameter TRAININGDONE = 4'b1000;
reg [3:0] INT_SAT;
// always@(posedge clk)begin
// if(rst)
// shift_reg <= 8'h00;
// else
// shift_reg <= {shift_reg[6:0], status_in};
// end
initial shift_reg <= 8'h00;
always@(posedge clk) shift_reg <= {shift_reg[6:0], status_in};
// decoder
initial begin
ambiguity <= 1'b0;
INT_SAT <= IDLE;
end
always@(posedge clk) begin
ambiguity <= 1'b0;
if ( shift_reg == 8'h55 | shift_reg == 8'hAA) begin
INT_SAT <= RST;
end else if ( shift_reg == 8'hF0 | shift_reg == 8'h87 | shift_reg == 8'hC3 | shift_reg == 8'hE1 | shift_reg == 8'h78 | shift_reg == 8'h3C | shift_reg == 8'h1E | shift_reg == 8'h0F ) begin
INT_SAT <= FIFOFULL;
end else if ( shift_reg == 8'h33 | shift_reg == 8'h66 | shift_reg == 8'hCC | shift_reg == 8'h99 ) begin
INT_SAT <= TRAININGDONE;
end else if ( shift_reg == 8'h00) begin
INT_SAT <= IDLE;
end else begin// by default, the previous INT_SAT remains, this normally happen when the status is changing
INT_SAT <= INT_SAT;
ambiguity <= 1'b1;
end
end
// detect error state
initial
error_cnt <= 4'b0000;
always@(posedge clk) begin
// if (rst) begin
// error_cnt <= 4'b0000;
// end else if(ambiguity) begin
if (ambiguity) begin
if (error_cnt != 4'b1000)
error_cnt <= error_cnt + 4'b0001;
else
error_cnt <= error_cnt;
end else begin
error_cnt <= 4'b0000;
end
end
always@(posedge clk) begin
error_state <= (error_cnt == 4'b1000) ? 1'b1 : 1'b0;
end
// determine the output signals
initial begin
RST_state <= 1'b0;
TRAININGDONE_state <= 1'b0;
FIFOFULL_state <= 1'b0;
IDLE_state <= 1'b1;
end
always@(posedge clk) begin
// if (rst) begin
// RST_state <= 1'b0;
// TRAININGDONE_state <= 1'b0;
// FIFOFULL_state <= 1'b0;
// IDLE_state <= 1'b1;
// end else if (INT_SAT == RST) begin
if (INT_SAT == RST) begin
RST_state <= 1'b1;
TRAININGDONE_state <= 1'b0;
FIFOFULL_state <= 1'b0;
IDLE_state <= 1'b0;
end else if ( INT_SAT == FIFOFULL ) begin
RST_state <= 1'b0;
TRAININGDONE_state <= 1'b1;
FIFOFULL_state <= 1'b1;
IDLE_state <= 1'b0;
end else if ( INT_SAT == TRAININGDONE ) begin
RST_state <= 1'b0;
TRAININGDONE_state <= 1'b1;
FIFOFULL_state <= 1'b0;
IDLE_state <= 1'b0;
end else if ( INT_SAT == IDLE ) begin
RST_state <= 1'b0;
TRAININGDONE_state <= 1'b0;
FIFOFULL_state <= 1'b0;
IDLE_state <= 1'b1;
end else begin // should not go into this branch
RST_state <= 1'b0;
TRAININGDONE_state <= 1'b0;
FIFOFULL_state <= 1'b0;
IDLE_state <= 1'b1;
end
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Thu Oct 26 22:45:02 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/RATCPU/Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_Counter10bit_0_0/RAT_Counter10bit_0_0_sim_netlist.v
// Design : RAT_Counter10bit_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "RAT_Counter10bit_0_0,Counter10bit,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "Counter10bit,Vivado 2016.4" *)
(* NotValidForBitStream *)
module RAT_Counter10bit_0_0
(Din,
LOAD,
INC,
RESET,
CLK,
COUNT);
input [0:9]Din;
input LOAD;
input INC;
(* x_interface_info = "xilinx.com:signal:reset:1.0 RESET RST" *) input RESET;
(* x_interface_info = "xilinx.com:signal:clock:1.0 CLK CLK" *) input CLK;
output [0:9]COUNT;
wire CLK;
wire [0:9]COUNT;
wire [0:9]Din;
wire INC;
wire LOAD;
wire RESET;
RAT_Counter10bit_0_0_Counter10bit U0
(.CLK(CLK),
.COUNT(COUNT),
.Din(Din),
.INC(INC),
.LOAD(LOAD),
.RESET(RESET));
endmodule
(* ORIG_REF_NAME = "Counter10bit" *)
module RAT_Counter10bit_0_0_Counter10bit
(COUNT,
CLK,
RESET,
LOAD,
INC,
Din);
output [0:9]COUNT;
input CLK;
input RESET;
input LOAD;
input INC;
input [0:9]Din;
wire CLK;
wire [0:9]COUNT;
wire [0:9]Din;
wire INC;
wire LOAD;
wire RESET;
wire [9:0]p_0_in;
wire \s_COUNT[0]_i_1_n_0 ;
wire \s_COUNT[0]_i_3_n_0 ;
wire \s_COUNT[1]_i_2_n_0 ;
wire \s_COUNT[4]_i_2_n_0 ;
wire \s_COUNT[5]_i_2_n_0 ;
LUT2 #(
.INIT(4'hE))
\s_COUNT[0]_i_1
(.I0(LOAD),
.I1(INC),
.O(\s_COUNT[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'h8BBBB888))
\s_COUNT[0]_i_2
(.I0(Din[0]),
.I1(LOAD),
.I2(\s_COUNT[0]_i_3_n_0 ),
.I3(COUNT[1]),
.I4(COUNT[0]),
.O(p_0_in[9]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'h80))
\s_COUNT[0]_i_3
(.I0(COUNT[2]),
.I1(\s_COUNT[1]_i_2_n_0 ),
.I2(COUNT[3]),
.O(\s_COUNT[0]_i_3_n_0 ));
LUT6 #(
.INIT(64'h8BBBBBBBB8888888))
\s_COUNT[1]_i_1
(.I0(Din[1]),
.I1(LOAD),
.I2(COUNT[3]),
.I3(\s_COUNT[1]_i_2_n_0 ),
.I4(COUNT[2]),
.I5(COUNT[1]),
.O(p_0_in[8]));
LUT6 #(
.INIT(64'h8000000000000000))
\s_COUNT[1]_i_2
(.I0(COUNT[4]),
.I1(COUNT[6]),
.I2(COUNT[8]),
.I3(COUNT[9]),
.I4(COUNT[7]),
.I5(COUNT[5]),
.O(\s_COUNT[1]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h8BBBB888))
\s_COUNT[2]_i_1
(.I0(Din[2]),
.I1(LOAD),
.I2(\s_COUNT[1]_i_2_n_0 ),
.I3(COUNT[3]),
.I4(COUNT[2]),
.O(p_0_in[7]));
LUT4 #(
.INIT(16'h8BB8))
\s_COUNT[3]_i_1
(.I0(Din[3]),
.I1(LOAD),
.I2(\s_COUNT[1]_i_2_n_0 ),
.I3(COUNT[3]),
.O(p_0_in[6]));
LUT4 #(
.INIT(16'h8BB8))
\s_COUNT[4]_i_1
(.I0(Din[4]),
.I1(LOAD),
.I2(\s_COUNT[4]_i_2_n_0 ),
.I3(COUNT[4]),
.O(p_0_in[5]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h80000000))
\s_COUNT[4]_i_2
(.I0(COUNT[5]),
.I1(COUNT[7]),
.I2(COUNT[9]),
.I3(COUNT[8]),
.I4(COUNT[6]),
.O(\s_COUNT[4]_i_2_n_0 ));
LUT4 #(
.INIT(16'h8BB8))
\s_COUNT[5]_i_1
(.I0(Din[5]),
.I1(LOAD),
.I2(\s_COUNT[5]_i_2_n_0 ),
.I3(COUNT[5]),
.O(p_0_in[4]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h8000))
\s_COUNT[5]_i_2
(.I0(COUNT[6]),
.I1(COUNT[8]),
.I2(COUNT[9]),
.I3(COUNT[7]),
.O(\s_COUNT[5]_i_2_n_0 ));
LUT6 #(
.INIT(64'h8BBBBBBBB8888888))
\s_COUNT[6]_i_1
(.I0(Din[6]),
.I1(LOAD),
.I2(COUNT[8]),
.I3(COUNT[9]),
.I4(COUNT[7]),
.I5(COUNT[6]),
.O(p_0_in[3]));
LUT5 #(
.INIT(32'h8BBBB888))
\s_COUNT[7]_i_1
(.I0(Din[7]),
.I1(LOAD),
.I2(COUNT[9]),
.I3(COUNT[8]),
.I4(COUNT[7]),
.O(p_0_in[2]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h8BB8))
\s_COUNT[8]_i_1
(.I0(Din[8]),
.I1(LOAD),
.I2(COUNT[9]),
.I3(COUNT[8]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'h8B))
\s_COUNT[9]_i_1
(.I0(Din[9]),
.I1(LOAD),
.I2(COUNT[9]),
.O(p_0_in[0]));
FDCE \s_COUNT_reg[0]
(.C(CLK),
.CE(\s_COUNT[0]_i_1_n_0 ),
.CLR(RESET),
.D(p_0_in[9]),
.Q(COUNT[0]));
FDCE \s_COUNT_reg[1]
(.C(CLK),
.CE(\s_COUNT[0]_i_1_n_0 ),
.CLR(RESET),
.D(p_0_in[8]),
.Q(COUNT[1]));
FDCE \s_COUNT_reg[2]
(.C(CLK),
.CE(\s_COUNT[0]_i_1_n_0 ),
.CLR(RESET),
.D(p_0_in[7]),
.Q(COUNT[2]));
FDCE \s_COUNT_reg[3]
(.C(CLK),
.CE(\s_COUNT[0]_i_1_n_0 ),
.CLR(RESET),
.D(p_0_in[6]),
.Q(COUNT[3]));
FDCE \s_COUNT_reg[4]
(.C(CLK),
.CE(\s_COUNT[0]_i_1_n_0 ),
.CLR(RESET),
.D(p_0_in[5]),
.Q(COUNT[4]));
FDCE \s_COUNT_reg[5]
(.C(CLK),
.CE(\s_COUNT[0]_i_1_n_0 ),
.CLR(RESET),
.D(p_0_in[4]),
.Q(COUNT[5]));
FDCE \s_COUNT_reg[6]
(.C(CLK),
.CE(\s_COUNT[0]_i_1_n_0 ),
.CLR(RESET),
.D(p_0_in[3]),
.Q(COUNT[6]));
FDCE \s_COUNT_reg[7]
(.C(CLK),
.CE(\s_COUNT[0]_i_1_n_0 ),
.CLR(RESET),
.D(p_0_in[2]),
.Q(COUNT[7]));
FDCE \s_COUNT_reg[8]
(.C(CLK),
.CE(\s_COUNT[0]_i_1_n_0 ),
.CLR(RESET),
.D(p_0_in[1]),
.Q(COUNT[8]));
FDCE \s_COUNT_reg[9]
(.C(CLK),
.CE(\s_COUNT[0]_i_1_n_0 ),
.CLR(RESET),
.D(p_0_in[0]),
.Q(COUNT[9]));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; const long long N = 1e5 + 10; long long n, d, b, a[N], f[N]; int main() { long long i, j, k, t = 0, ans; scanf( %I64d%I64d%I64d , &n, &d, &b); for (i = 1; i <= n; i++) scanf( %I64d , &a[i]), f[i] = f[i - 1] + a[i]; for (i = 1; i <= n / 2; i++) if (f[min(i * d + i, n)] >= (t + 1) * b) t++; ans = t; t = 0; for (i = 1; i <= n / 2; i++) swap(a[i], a[n - i + 1]); f[0] = 0; for (i = 1; i <= n; i++) f[i] = f[i - 1] + a[i]; for (i = 1; i <= n / 2; i++) if (f[min(i * d + i, n)] >= (t + 1) * b) t++; printf( %I64d , n / 2 - min(ans, t)); } |
#include <bits/stdc++.h> using namespace std; int n, k; long long l; long long mo = 998244353; long long A[4005][4005][2]; long long B[4005]; long long a, b; long long f(long long x, long long y) { long long mid = 1; while (y) { if (y & 1) { mid = mid * x % mo; } x = x * x % mo; y >>= 1; } return mid; } int main() { cin >> n >> k >> l; A[0][0][0] = 1; for (int i = 0; i <= 2 * n; i++) { for (int j = 0; j <= i; j++) { A[i + 1][j + 1][0] = (A[i + 1][j + 1][0] + A[i][j][0]) % mo; A[i + 1][j + 1][1] = (A[i + 1][j + 1][1] + A[i][j][1]) % mo; if (j) { A[i + 1][j - 1][0] = (A[i + 1][j - 1][0] + A[i][j][0] * j) % mo; A[i + 1][j - 1][1] = (A[i + 1][j - 1][1] + A[i][j][1] * j) % mo; } if (j >= k) { A[i + 1][j][1] = (A[i + 1][j][1] + A[i][j][0]) % mo; } } } B[0] = 1; for (int i = 1; i <= n * 2 + 1; i++) { B[i] = B[i - 1] * i % mo; } a = A[2 * n + 1][0][1] * B[n] % mo * f(2, n) % mo; b = f(B[2 * n + 1], mo - 2) * l % mo; cout << a * b % mo << endl; } |
#include <bits/stdc++.h> using namespace std; const double eps = 1e-2; struct cplx { double x, y; cplx(double x1 = 0, double x2 = 0) { x = x1, y = x2; } } g[2000001], f[2000001]; cplx operator+(cplx a, cplx b) { return cplx(a.x + b.x, a.y + b.y); } cplx operator-(cplx a, cplx b) { return cplx(a.x - b.x, a.y - b.y); } cplx operator*(cplx a, cplx b) { return cplx(a.x * b.x - a.y * b.y, a.x * b.y + a.y * b.x); } void swap(cplx &a, cplx &b) { swap(a.x, b.x), swap(a.y, b.y); } int a[2000001], b[2000001]; int r[2000001]; const double Pi = acos(-1); void fft(cplx f[], int op, int n) { for (int i = 0; i < n; i++) if (i < r[i]) swap(f[i], f[r[i]]); for (int w = 2; w <= n; w <<= 1) { int len = w / 2; cplx tmp(cos(Pi / len), op * sin(Pi / len)); for (int k = 0; k < n; k += w) { cplx buf(1, 0); for (int l = k; l < k + len; l++) { cplx tt = f[len + l] * buf; f[len + l] = f[l] - tt; f[l] = f[l] + tt; buf = buf * tmp; } } } if (op == -1) { for (int i = 0; i < n; i++) f[i].x /= n, f[i].y /= n; } } char p[2000001]; char q[2000001]; int res[2000001]; int l1, l2, k, n, m; void solve(char c) { for (int i = 0; i <= n; i++) f[i].x = f[i].y = g[i].x = g[i].y = 0; int far = -1; for (int i = 0; i < l1; i++) { if (p[i] == c) far = i + k; if (i <= far) f[i].x = 1; } far = l1; for (int i = l1 - 1; i >= 0; i--) { if (p[i] == c) far = i - k; if (i >= far) f[i].x = 1; } for (int i = 0; i < l2; i++) if (q[i] == c) g[i].x = 1; fft(f, 1, n); fft(g, 1, n); for (int i = 0; i < n; i++) f[i] = f[i] * g[i]; fft(f, -1, n); for (int i = 0; i < n; i++) res[i] += (int)(f[i].x + eps); } signed main() { int ans = 0; scanf( %d%d%d , &l1, &l2, &k); cin >> p; cin >> q; reverse(p, p + l1); n = l1, m = l2; for (m += n, n = 1; n <= m; n <<= 1) ; for (int i = 0; i < n; i++) r[i] = (r[i >> 1] >> 1) | ((i & 1) ? n >> 1 : 0); solve( A ); solve( T ); solve( G ); solve( C ); for (int i = 0; i <= l1 - l2; i++) if (res[l1 - i - 1] >= l2) ans++; printf( %d , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; long long M = 1e9 + 7; long long powmodM(long long a, long long b, long long c = M) { long long res = 1; while (b) { if (b & 1) res = (res * a) % M; a = (a * a) % M; b /= 2; } return res; } long long power(long long a, long long b) { long long res = 1; while (b) { if (b & 1) res = (res * a); a = (a * a); b /= 2; } return res; } long long gcd(long long a, long long b) { while (a && b) a > b ? a %= b : b %= a; return a + b; } long long lcm(long long a, long long b) { return (max(a, b) / gcd(a, b)) * min(a, b); } vector<long long int> sieve(long long int n) { vector<long long int> ans, prime(2 * 1e6); prime[0] = false; prime[1] = false; for (long long int p = 2; p * p <= n; p++) if (prime[p]) for (long long int i = p * p; i <= n; i += p) prime[i] = 0; for (long long p = (2); p <= (n); ++p) if (prime[p]) ans.push_back(p); return ans; } long long modInverse(long long n, long long p = M) { return powmodM(n, p - 2, p); } long long nCrModP(long long n, long long r, long long p = M) { if (r == 0) return 1; long long fac[n + 1]; fac[0] = 1; for (long long i = (1); i <= (n); ++i) fac[i] = fac[i - 1] * i % p; return (fac[n] * modInverse(fac[r], p) % p * modInverse(fac[n - r], p) % p) % p; } double pie = 3.14159265358979323846264338; const long long int INF = 0x3f3f3f3f; class l { public: char data; l *next; l *prev; l(char a) { data = a; prev = NULL; next = NULL; } }; map<long long int, long long int> fre; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int n, m; cin >> n >> m; vector<long long int> arr(n); for (long long i = (0); i <= (n - 1); ++i) cin >> arr[i]; if (m == arr[0]) { cout << -1; return 0; } long long int ma = 0; fre[arr[ma]] = 1; bool ok = 1; long long int uski = 0; for (long long i = (1); i <= (n - 1); ++i) { if (arr[i] == m) { uski++; vector<long long int> re; for (auto u : fre) { if (u.second < uski) re.push_back(u.first); } for (auto u : re) { fre.erase(u); } if (!fre.size()) { cout << -1; return 0; } } if (!uski) fre[arr[i]]++; else if (fre[arr[i]]) { fre[arr[i]]++; } } vector<long long int> re; for (auto u : fre) { if (u.second < uski) re.push_back(u.first); } for (auto u : re) { fre.erase(u); } if (!fre.size()) { cout << -1; return 0; } if (fre.size()) { cout << fre.begin()->first; } else { cout << -1; } } |
#include <bits/stdc++.h> using namespace std; int gcd(int a, int b) { return !b ? a : gcd(b, a % b); } class fraction { public: int a, b; fraction() { a = 0, b = 1; } fraction(int a, int b) { if (b < 0) { a *= -1; b *= -1; } if (a == 0) b = 1; int g = gcd(abs(a), abs(b)); a /= g; b /= g; this->a = a; this->b = b; } bool operator==(fraction oth) const { return a == oth.a and b == oth.b; } bool operator!=(fraction oth) const { return !(*this == oth); } bool operator<(fraction oth) const { if (a < 0 and oth.a >= 0) return true; if (oth.a < 0 and a >= 0) return false; return (long long)a * oth.b < (long long)b * oth.a; } bool operator>(fraction oth) const { return !(*this < oth) and (*this != oth); } bool operator<=(fraction oth) const { return !(*this > oth); } bool operator>=(fraction oth) const { return !(*this < oth); } }; int main() { int n; scanf( %d , &n); int x1, y1, x2, y2; scanf( %d %d %d %d , &x1, &y1, &x2, &y2); fraction x(0, 1); fraction y(1e9, 1); for (int i = 1; i <= n; i++) { int rx, ry, vx, vy; scanf( %d %d %d %d , &rx, &ry, &vx, &vy); if ((rx == x1 or rx == x2) and vx == 0) { puts( -1 ); return 0; } if ((ry == y1 or ry == y2) and vy == 0) { puts( -1 ); return 0; } fraction tox1(x1 - rx, vx); fraction toy1(y1 - ry, vy); fraction tox2(x2 - rx, vx); fraction toy2(y2 - ry, vy); if (tox2 < tox1) swap(tox1, tox2); if (toy2 < toy1) swap(toy1, toy2); x = max(x, tox1); x = max(x, toy1); y = min(y, tox2); y = min(y, toy2); } if (x >= y) { puts( -1 ); } else { double l = (double)x.a / x.b; printf( %.9lf n , l); } return 0; } |
#include <bits/stdc++.h> using namespace std; int t[24], n; bool ok(int n) { set<int> u; int e = 0; for (int(i) = (0); (i) < (n); (i)++) for (int(j) = (0); (j) < (i); (j)++) { e++; u.insert(abs(t[i] + t[j])); } return (e == u.size()); } int main() { scanf( %d , &n); for (int(i) = (0); (i) < (n); (i)++) { t[i] = i; while (!ok(i + 1)) t[i]++; } for (int(i) = (0); (i) < (n); (i)++) { for (int(j) = (0); (j) < (n); (j)++) printf( %d , i == j ? 0 : abs(t[i] + t[j])); puts( ); } return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int a, b, c, d; cin >> a >> b >> c >> d; long double t = (a * 1.0 / b) * (1.0 / (1 - (1 - a * 1.0 / b) * (1 - c * 1.0 / d))); cout << t << fixed << setprecision(6); } |
#include <bits/stdc++.h> using namespace std; int main() { long long n; while (cin >> n) { long long i = 5, cnt = 1, x, ans = 0, y, z = 5, m; if (n < 5 || n == 5) { if (n == 1) cout << Sheldon << endl; else if (n == 2) cout << Leonard << endl; else if (n == 3) cout << Penny << endl; else if (n == 4) cout << Rajesh << endl; else if (n == 5) cout << Howard << endl; continue; } while (i < n || i == n) { x = i; if (i == n) { x = 0; break; } else { z += z; i += z; } cnt = cnt * 2; } if (x == 0) cout << Howard << endl; else { y = n - x; if (y < 1) y *= -1; ans = y / cnt; ans++; if (y % cnt == 0) ans--; if (ans == 1) cout << Sheldon << endl; else if (ans == 2) cout << Leonard << endl; else if (ans == 3) cout << Penny << endl; else if (ans == 4) cout << Rajesh << endl; else if (ans == 5) cout << Howard << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; struct node { int a, b, c, ty; } a[100010]; struct Tnode { int x, f, tag, ls, rs; } t[3000000]; int n, m, k, K, ans, rt, tot; bool cmp(node x, node y) { return x.a < y.a; } int getfull(int l, int r) { int s = 0; l--; for (int j = 1; j <= k; j <<= 1) s |= (((r / j - l / j) - (j * 2 <= k ? (r / j / 2 - l / j / 2) : 0)) & 1) * j; return s; } void update(int n) { if (t[n].tag) t[n].x = t[n].f; else t[n].x = t[t[n].ls].x ^ t[t[n].rs].x; } void modify(int &n, int l, int r, int L, int R, int k) { if (!n) n = ++tot, t[n].f = getfull(l, r); if ((L <= l) && (r <= R)) t[n].tag += k; else { int mid = (l + r) >> 1; if (L <= mid) modify(t[n].ls, l, mid, L, R, k); if (mid < R) modify(t[n].rs, mid + 1, r, L, R, k); } update(n); } void work() { scanf( %d %d %d , &n, &m, &k); for (K = 1; K * 2 <= k; K <<= 1) ; for (int i = 1, A, B, C, D; i <= m; i++) { scanf( %d %d %d %d , &A, &B, &C, &D); a[i] = (node){A, B, D, 1}, a[i + m] = (node){C + 1, B, D, -1}; } sort(a + 1, a + 2 * m + 1, cmp); for (int i = 1; i <= 2 * m; i++) { if (a[i - 1].a != a[i].a) { int x = getfull(a[i - 1].a, a[i].a - 1), y = t[rt].x, sx = 0, sy = 0, s; for (int j = K; j; j >>= 1) { s = -sx * sy, sx += (x & j) > 0, sy += (y & j) > 0, s += sx * sy; if (s & 1) ans ^= j; } } modify(rt, 1, n, a[i].b, a[i].c, a[i].ty); } puts(ans ? Hamed : Malek ); } int main() { work(); return 0; } |
module cache(clk,rst_n,addr,wr_data,wdirty,we,re,rd_data,tag_out,hit,dirty);
input clk,rst_n;
input [13:0] addr; // address to be read or written, 2-LSB's are dropped
input [63:0] wr_data; // 64-bit cache line to write
input wdirty; // dirty bit to be written
input we; // write enable for cache line
input re; // read enable (for power purposes only)
output hit;
output dirty;
output [63:0] rd_data; // 64-bit cache line read out
output [7:0] tag_out; // 8-bit tag. This is needed during evictions
reg [73:0]mem[0:63]; // {valid,dirty,tag[7:0],wdata[63:0]}
reg [6:0] x;
reg [73:0] line;
reg we_del;
wire we_filt;
//////////////////////////
// Glitch filter on we //
////////////////////////
always @(we)
we_del <= we;
assign we_filt = we & we_del;
///////////////////////////////////////////////////////
// Model cache write, including reset of valid bits //
/////////////////////////////////////////////////////
always @(clk or we_filt or negedge rst_n)
if (!rst_n)
for (x=0; x<64; x = x + 1)
mem[x] = {2'b00,{72{1'bx}}}; // only valid & dirty bit are cleared, all others are x
else if (~clk && we_filt)
mem[addr[5:0]] = {1'b1,wdirty,addr[13:6],wr_data};
////////////////////////////////////////////////////////////
// Model cache read including 4:1 muxing of 16-bit words //
//////////////////////////////////////////////////////////
always @(clk or re or addr)
if (clk && re) // read is on clock high
line = mem[addr[5:0]];
/////////////////////////////////////////////////////////////
// If tag bits match and line is valid then we have a hit //
///////////////////////////////////////////////////////////
assign hit = ((line[71:64]==addr[13:6]) && (re | we)) ? line[73] : 1'b0;
assign dirty = line[73]&line[72]; // if line is valid and dirty bit set
assign rd_data = line[63:0];
assign tag_out = line[71:64]; // need the tag for evictions
endmodule |
#include <bits/stdc++.h> using namespace std; int main() { string s; int dif; cin >> s >> dif; set<char> st; for (int i = (0); i < s.length(); i++) st.insert(s[i]); if (s.length() < dif) { cout << impossible << endl; } else if (st.size() >= dif) cout << 0; else cout << dif - st.size() << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR3B_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__NOR3B_PP_BLACKBOX_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nor3b (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND
);
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR3B_PP_BLACKBOX_V
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the program counter
// Import the modules that will be tested for in this testbench
`include "prog_counter2.v"
// IMPORTANT: To run this, try: ncverilog -f prog_counter.f +gui
module tb_prog_counter2();
// ============================================================
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the prog_counter
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
// next_pc output signal
wire [0:31] n_pc;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// clk, rst
reg clock,reset;
// cur_pc
//reg [0:31] c_pc;
// ============================================================
// Counter for loop to enumerate all the values of r
integer count;
// ============================================================
// Defining constants: parameter [name_of_constant] = value;
//parameter size_of_input = 6'd32;
// ============================================================
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
/**
* Clock frequency is arbitrarily chosen;
* Period = 5ns <==> 200 MHz clock
*/
#5 clock = 0;
#5 clock = 1;
end
// ============================================================
/**
* Instantiate an instance of regfile() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "rg"
*/
program_counter2 pc (
// instance_name(signal name),
// Signal name can be the same as the instance name
// next_pc,cur_pc,rst,clk
n_pc,reset,clock);
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
//c_pc=$random;
reset=1'b1;
#19
//c_pc=200;
reset=1'b0;
// Write to 8 data locations
for(count=200; count<216; count=count+1)
begin
#10
//c_pc=count;
//c_pc=n_pc;
reset=1'b0;
end
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX_N = 100 + 10; int a[MAX_N]; int main() { int n, count = 0, f = 0, h = 0, b; cin >> n; for (int i = 0; i < n; i++) { cin >> b; if (b < 0) count++; if (count == 3) { f++; a[f] = i - h; h += a[f]; count = 1; } if (count < 3 && i == n - 1) { f++; a[f] = i + 1 - h; h += a[f]; } } cout << f << endl; for (int i = 1; i <= f; i++) cout << a[i] << ; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, k; map<int, int> m; string s; long long ans; bool flag; void solve() { cin >> n; cin >> k; vector<int> a(n); int maxi = 0; for (auto i = 0; i < n; i++) cin >> a[i]; ; for (auto i = 0; i < n; i++) { maxi = max(maxi, a[i]); m[a[i]]++; if (m[a[i]] >= k) { cout << 0; return; } } long long ans = INT_MAX; for (auto x = 1; x < 200000; x++) { queue<int> q; q.push(x); long long an = 0; int mul = 0; int K = 0; while (!q.empty() && K < k) { int N = q.size(); while (N-- && K < k) { int y = q.front(); q.pop(); int count = m[y]; if ((y * 2 - 1) < maxi) { q.push(y * 2); q.push(y * 2 + 1); } if (count > (k - K)) count = (k - K); an += count * mul; K += count; } mul++; } if (K == k) ans = min(an, ans); } cout << ans; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t = 1; while (t--) { solve(); } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:46:58 11/16/2015
// Design Name:
// Module Name: AluControl
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module AluControl(
input [1:0] aluOp,
input [5:0] instructionCodeLowBits,
input [5:0] instructionCodeHighBits,
output reg [3:0] aluOperation
);
/*
ALU Operation codes
0: SLL
1: SRL
2: SRA
3: ADD
4: SUB
5: AND
6: OR
7: XOR
8: NOR
9: SLT
AluOp: 00 Store and Load
AluOp: 01 Branch Equal y Not Equal
AluOp: 10 Operaciones Tipo R
AluOp: 11 Operaciones con Immediate
*/
always @(*)begin
case(aluOp)
0: aluOperation<=3;
1: aluOperation<=4;
2: begin
case(instructionCodeLowBits)
6'b000000: aluOperation<=0; //SLL
6'b000010: aluOperation<=1; //SRL
6'b000011: aluOperation<=2; //SRA
6'b000110: aluOperation<=1; //SRLV
6'b000111: aluOperation<=2; //SRAV
6'b000100: aluOperation<=0; //SLLV
6'b100000: aluOperation<=3; //ADD
6'b100010: aluOperation<=4; //SUB
6'b100100: aluOperation<=5; //AND
6'b100101: aluOperation<=6; //OR
6'b100110: aluOperation<=7; //XOR
6'b100111: aluOperation<=8; //NOR
6'b101010: aluOperation<=9; //SLT
default: aluOperation<='hF;
endcase
end
3: begin
case(instructionCodeHighBits)
6'b001000: aluOperation<=3; //ADDI
6'b001100: aluOperation<=5; //ANDI
6'b001101: aluOperation<=6; //ORI
6'b001110: aluOperation<=7; //XORI
6'b001010: aluOperation<=9; //SLTI
default: aluOperation<='hF;
endcase
end
default:aluOperation<='hF;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void solve() { string n; int s; cin >> n >> s; int sum = 0; vector<int> digit; for (int i = 0; i < (int)n.size(); i++) { digit.push_back(n[i] - 0 ); sum += digit[i]; } if (sum <= s) { cout << 0 << n ; return; } sum = 0; int pos = -1; for (int i = 0; i < (int)digit.size(); i++) { sum += digit[i]; if (sum >= s) { pos = i; s -= (sum - digit[i]); break; } } if (pos == 0) { digit.insert(digit.begin(), 1); pos++; } else { digit[pos - 1]++; } for (int i = pos; i < (int)digit.size(); i++) digit[i] = 0; long long num = 0; for (int i = 0; i < (int)digit.size(); i++) num = num * 10 + digit[i]; long long res = num - stoll(n); cout << res << n ; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) { solve(); } } |
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
//
//
module main ();
reg [7:0] array [7:0];
reg error ;
reg [3:0] count;
initial
begin
for(count = 0; count <= 7; count = count + 1)
begin
array[count] = 1 << count;
end
$writememb("work/writememb2.dat", array, 6, 1);
for(count = 0; count <= 7; count = count + 1)
begin
array[count] = 'bx;
end
error = 0;
$readmemb("work/writememb2.dat", array);
for(count = 0; count <= 5; count = count + 1)
begin
if(array[count] !== (1<<(6-count)))
begin
error = 1;
$display("FAILED - array[count] == %h, s/b %h",
array[count], 1 << count);
end
end
if(error == 0)
$display("PASSED\n");
$finish ;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 305, MOD = 1e4 + 7; char s[N]; int n, m, ndc, f[N][N][N]; int getf(int cnt, int l, int r) { if (cnt < 0) return 0; if (~f[cnt][l][r]) return f[cnt][l][r]; if (l == 1 && r == m) return f[cnt][l][r] = !cnt; int ret = 0; if (l > 1 && r < m && s[l - 1] == s[r + 1]) ret = (ret + getf(cnt, l - 1, r + 1)) % MOD; if (l > 1 && s[l - 1] != s[r]) ret = (ret + getf(cnt - 1, l - 1, r)) % MOD; if (r < m && s[l] != s[r + 1]) ret = (ret + getf(cnt - 1, l, r + 1)) % MOD; return f[cnt][l][r] = ret; } struct matrix { int sq[N][N]; matrix() { memset(sq, 0, sizeof(sq)); } matrix operator*(const matrix &a) const { matrix ret; for (int i = 1; i <= ndc; i++) for (int j = i; j <= ndc; j++) for (int k = i; k <= j; k++) ret.sq[i][j] = (ret.sq[i][j] + 1ll * sq[i][k] * a.sq[k][j]) % MOD; return ret; } } trs, one; inline matrix qpow(matrix x, int y) { matrix ret = one; while (y) { if (y & 1) ret = ret * x; x = x * x; y >>= 1; } return ret; } int idr[N], idg[N], cntc[N]; int main() { int i, j, k, ans = 0; scanf( %s%d , s + 1, &n); m = strlen(s + 1); idr[0] = ++ndc; for (i = 1; i < m; i++) { int rem = (m - i + 1) / 2; if ((m - i + 1) / 2 != (m - i) / 2 + 1) idg[(m - i) / 2 + 1] = ++ndc; idr[i] = ++ndc; } if (!idg[1]) idg[1] = ++ndc; idg[0] = ++ndc; for (i = 0; i < m; i++) { if (i) trs.sq[idr[i]][idr[i]] = 24; if (i < m - 1) trs.sq[idr[i]][idr[i + 1]] = 1; } for (i = (m + 1) / 2; i > 0; i--) { trs.sq[idg[i]][idg[i]] = 25; trs.sq[idg[i]][idg[i - 1]] = 1; } for (i = 1; i <= ndc; i++) one.sq[i][i] = 1; memset(f, -1, sizeof(f)); for (i = 0; i < m; i++) { for (j = 1; j <= m; j++) { cntc[i] = (cntc[i] + getf(i, j, j)) % MOD; if (j < m && s[j] == s[j + 1]) cntc[i] = (cntc[i] + getf(i, j, j + 1)) % MOD; } } for (i = 0; i < m; i++) trs.sq[idr[i]][idg[(m - i + 1) / 2]] = cntc[i]; trs.sq[ndc][ndc] = 26; ans = (qpow(trs, (n + m + 1) / 2 + 1)).sq[1][ndc]; if (!((n + m) & 1)) { printf( %d , ans); return 0; } memset(f, -1, sizeof(f)); memset(cntc, 0, sizeof(cntc)); for (i = 0; i < m; i++) for (j = 1; j < m; j++) if (s[j] == s[j + 1]) cntc[i] = (cntc[i] + getf(i, j, j + 1)) % MOD; for (i = 0; i < m; i++) trs.sq[idr[i]][idg[(m - i + 1) / 2]] = cntc[i]; trs.sq[ndc][ndc] = 0; ans = (ans - (qpow(trs, (n + m + 1) / 2 + 1)).sq[1][ndc] + MOD) % MOD; printf( %d , ans); return 0; } |
// wasca_nios2_gen2_0.v
// This file was auto-generated from altera_nios2_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 193
`timescale 1 ps / 1 ps
module wasca_nios2_gen2_0 (
input wire clk, // clk.clk
input wire reset_n, // reset.reset_n
output wire [27:0] d_address, // data_master.address
output wire [3:0] d_byteenable, // .byteenable
output wire d_read, // .read
input wire [31:0] d_readdata, // .readdata
input wire d_waitrequest, // .waitrequest
output wire d_write, // .write
output wire [31:0] d_writedata, // .writedata
output wire debug_mem_slave_debugaccess_to_roms, // .debugaccess
output wire [27:0] i_address, // instruction_master.address
output wire i_read, // .read
input wire [31:0] i_readdata, // .readdata
input wire i_waitrequest, // .waitrequest
input wire [31:0] irq, // irq.irq
output wire debug_reset_request, // debug_reset_request.reset
input wire [8:0] debug_mem_slave_address, // debug_mem_slave.address
input wire [3:0] debug_mem_slave_byteenable, // .byteenable
input wire debug_mem_slave_debugaccess, // .debugaccess
input wire debug_mem_slave_read, // .read
output wire [31:0] debug_mem_slave_readdata, // .readdata
output wire debug_mem_slave_waitrequest, // .waitrequest
input wire debug_mem_slave_write, // .write
input wire [31:0] debug_mem_slave_writedata, // .writedata
output wire dummy_ci_port // custom_instruction_master.readra
);
wasca_nios2_gen2_0_cpu cpu (
.clk (clk), // clk.clk
.reset_n (reset_n), // reset.reset_n
.d_address (d_address), // data_master.address
.d_byteenable (d_byteenable), // .byteenable
.d_read (d_read), // .read
.d_readdata (d_readdata), // .readdata
.d_waitrequest (d_waitrequest), // .waitrequest
.d_write (d_write), // .write
.d_writedata (d_writedata), // .writedata
.debug_mem_slave_debugaccess_to_roms (debug_mem_slave_debugaccess_to_roms), // .debugaccess
.i_address (i_address), // instruction_master.address
.i_read (i_read), // .read
.i_readdata (i_readdata), // .readdata
.i_waitrequest (i_waitrequest), // .waitrequest
.irq (irq), // irq.irq
.debug_reset_request (debug_reset_request), // debug_reset_request.reset
.debug_mem_slave_address (debug_mem_slave_address), // debug_mem_slave.address
.debug_mem_slave_byteenable (debug_mem_slave_byteenable), // .byteenable
.debug_mem_slave_debugaccess (debug_mem_slave_debugaccess), // .debugaccess
.debug_mem_slave_read (debug_mem_slave_read), // .read
.debug_mem_slave_readdata (debug_mem_slave_readdata), // .readdata
.debug_mem_slave_waitrequest (debug_mem_slave_waitrequest), // .waitrequest
.debug_mem_slave_write (debug_mem_slave_write), // .write
.debug_mem_slave_writedata (debug_mem_slave_writedata), // .writedata
.dummy_ci_port (dummy_ci_port), // custom_instruction_master.readra
.reset_req (1'b0) // (terminated)
);
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always reg_lvalue = @ (event_expression) boolean_expr
//
module main ;
reg [3:0] value1 ;
reg event_var ;
initial
begin
# 2 ;
value1 = 5'h 0 ;
# 3 ;
event_var = 1'b0 ;
# 2 ;
value1 = 5'h 0 ;
# 3 ;
event_var = 1'b1 ;
#5 ;
end
initial
begin // Should be xxxx at initial time
if(value1 !== 4'bxxxx)
$display("FAILED - always reg_lvalue = @ (event_expression) boolean_expr\n");
# 6 ;
if(value1 != 4'h1) // Time 5 should see a change of 0 to 1
$display("FAILED - always reg_lvalue = @ (event_expression) boolean_expr\n");
# 5 ;
if(value1 != 4'h1) // Time 5 should see a change of 0 to 1
$display("FAILED - always reg_lvalue = @ (event_expression) boolean_expr\n");
begin
$display("PASSED\n");
$finish ;
end
end
always value1 = @ (event_var) 1'b1 && 1'b1 ;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 6e5 + 5, mod = 998244353; vector<int> num; long long A[N]; int a[N]; long long sumup = 0, sumdown = 0; long long qpow(long long a, long long b) { long long c = 1; while (b) { if (b & 1) c = (a * c) % mod; b >>= 1; a = (a * a) % mod; } return c; } long long inv(long long x) { return qpow(x, mod - 2); } int main() { int n; cin >> n; n <<= 1; A[0] = 1; for (int i = 1; i <= n; i++) A[i] = (A[i - 1] * i) % mod; for (int i = 1; i <= n; i++) cin >> a[i]; long long ans = 0; sort(a + 1, a + n + 1); for (int i = 1; i <= n / 2; i++) ans -= a[i]; for (int i = n / 2 + 1; i <= n; i++) ans += a[i]; ans = (ans % mod * A[n] % mod * inv(A[n / 2]) % mod * inv(A[n / 2])) % mod; cout << ans << endl; } |
#include <bits/stdc++.h> namespace IO { const unsigned int Buffsize = 1 << 15, Output = 1 << 23; static char Ch_[Buffsize], *S_ = Ch_, *T_ = Ch_; static char Out[Output], *nowps = Out; inline void flush() { fwrite(Out, 1, nowps - Out, stdout); nowps = Out; } template <typename T> inline T Read() { T _ = 0; static char __; T ___ = 1; for (__ = ((S_ == T_) && (T_ = (S_ = Ch_) + fread(Ch_, 1, Buffsize, stdin), S_ == T_) ? 0 : *S_++); !isdigit(__); __ = ((S_ == T_) && (T_ = (S_ = Ch_) + fread(Ch_, 1, Buffsize, stdin), S_ == T_) ? 0 : *S_++)) if (__ == - ) ___ = -1; for (; isdigit(__); __ = ((S_ == T_) && (T_ = (S_ = Ch_) + fread(Ch_, 1, Buffsize, stdin), S_ == T_) ? 0 : *S_++)) _ = (_ << 3) + (_ << 1) + (__ ^ 48); return _ *= ___; } template <typename T> inline void write(T _, char __ = n ) { if (!_) *nowps++ = 0 ; if (_ < 0) *nowps++ = - , _ = -_; static unsigned int sta[111], tp; for (tp = 0; _; _ /= 10) sta[++tp] = _ % 10; for (; tp; *nowps++ = sta[tp--] ^ 48) ; (*nowps++) = __; } template <class T> inline bool chkmax(T &_, T __) { return _ < __ ? _ = __, 1 : 0; } template <class T> inline bool chkmin(T &_, T __) { return _ > __ ? _ = __, 1 : 0; } } // namespace IO using namespace std; using namespace IO; const int N = 2e5 + 10, Mod = 1e9 + 7; int n; int fa[N], sz[N], flag[N], ans; int find(int first) { return first == fa[first] ? first : fa[first] = find(fa[first]); } void merge(int first, int second) { int fx = find(first), fy = find(second); if (fx != fy) { fa[fx] = fy; sz[fy] += sz[fx]; flag[fy] |= flag[fx]; } else flag[fy] = 1; } int main() { n = Read<int>(); for (int i = 1; i <= 2 * n; ++i) fa[i] = i, sz[i] = 1, flag[i] = 0; for (register int i = (1), i_end_ = (n); i <= i_end_; ++i) { int u = Read<int>(), v = Read<int>(); if (u != v) merge(u, v); else flag[u] = 2; } ans = 1; for (register int i = (1), i_end_ = (2 * n); i <= i_end_; ++i) if (find(i) == i) { if (flag[i] == 0) ans = (1ll * ans * sz[i]) % Mod; else if (flag[i] == 1) ans = (ans * 2ll) % Mod; } printf( %d n , ans); return flush(), 0; } |
//
// Paul Gao 03/2019
//
// This is the sender part of bsg_link_ddr, a complete DDR communication
// endpoint over multiple source-synchronous channels.
//
// * This module MUST be mirrored with bsg_link_ddr_downstream, which is
// instantiated on the destination chip or FPGA. It is not a must to
// use upstream and downstream in pair on same chip or FPGA.
//
// The purpose of bsg_link_ddr_upstream is to receive data packets from ready-valid
// interface in core clock domain, serialize them to fit in IO channels (optional),
// then send out through physical IO pins.
// Token-credit based flow control ensures efficiency and correctness.
// ODDR PHY sends out packets with center-aligned DDR clock.
//
// Typical usage: ASIC <-> ASIC communication and ASIC <-> FPGA communication.
// Instantiate one bsg_link_ddr_upstream on sender side, one bsg_link_ddr_downstream on
// receiver side to establish communication.
//
// Refer to bsg_link_source_sync_upstream for more information on flow control
//
// Reset procedures:
// Step 1: Assert io_link_reset_i and core_link_reset_i.
// Step 2: async_token_reset_i must be posedge/negedge toggled (0->1->0)
// at least once. token_clk_i cannot toggle during this step.
// Step 3: io_clk_i posedge toggled at least four times after that.
// Step 4: Deassert io_link_reset_i.
// Step 5: Deassert core_link_reset_i.
//
`include "bsg_defines.v"
module bsg_link_ddr_upstream
#(// Core data width
// MUST be multiple of (2*channel_width_p*num_channels_p)
// When use_extra_data_bit_p=1, must be multiple of ((2*channel_width_p+1)*num_channels_p)
parameter `BSG_INV_PARAM(width_p )
// Number of IO pins per physical IO channels
,parameter channel_width_p = 8
// Number of physical IO channels
,parameter num_channels_p = 1
// Receive fifo depth
// MUST MATCH paired bsg_link_ddr_downstream setting
// Default value comes from child module
// Refer to bsg_link_source_sync_downstream for more detail on this parameter
,parameter lg_fifo_depth_p = 6
// Token credit decimation
// MUST MATCH paired bsg_link_ddr_downstream setting
// Default value comes from child module
// Refer to bsg_link_source_sync_downstream for more detail on this parameter
,parameter lg_credit_to_token_decimation_p = 3
// There are (channel_width_p+1) physical wires available (1 wire for valid bit)
// With DDR clock, we can handle 2*channel_width_p+2 bits each cycle
// By default the link has 2*channel_width_p data bits and 1 valid bit, 1 bit is unused
// Set use_extra_data_bit_p=1 to utilize this extra bit
// MUST MATCH paired bsg_link_ddr_downstream setting
,parameter use_extra_data_bit_p = 0
// When channel_width_p is large, it might be hard to properly align source synchronous
// clock to all data wires. One option is to cut the channel in half and align to
// different clocks. Ecoding method below helps represent valid bit for bottom half data
// without adding an extra wire.
// +-------------+---------------+---------------------+
// | v_top | bottom | Value |
// | 0_0???_???? | 0000_0000 | no data (""comma"") |
// | 1_XXXX_XXXX | YYYY_YYYY!=0 | XXXX_XXXX_YYYY_YYYY |
// | 0_1XXX_XXXX | X000_0001 | XXXX_XXXX_0000_0000 |
// +-------------+---------------+---------------------+
// Physical bonding suggestion: Regard v bit and top bits of the channel as a group
// Regard bottom bits of the channel as another group
// Set use_encode_p=1 to enable this encoding feature
// MUST MATCH paired bsg_link_ddr_downstream setting
,parameter use_encode_p = 0
,parameter bypass_twofer_fifo_p = 0
,parameter bypass_gearbox_p = 0
,localparam ddr_width_lp = channel_width_p*2 + use_extra_data_bit_p
,localparam piso_ratio_lp = width_p/(ddr_width_lp*num_channels_p)
,localparam phy_width_lp = channel_width_p+1
)
(// Core side
input core_clk_i
,input core_link_reset_i
,input [width_p-1:0] core_data_i
,input core_valid_i
,output core_ready_o
// Physical IO side
,input io_clk_i
,input io_link_reset_i
,input async_token_reset_i
,output logic [num_channels_p-1:0] io_clk_r_o
,output logic [num_channels_p-1:0][channel_width_p-1:0] io_data_r_o
,output logic [num_channels_p-1:0] io_valid_r_o
,input [num_channels_p-1:0] token_clk_i
);
logic core_piso_valid_lo, core_piso_yumi_li;
logic [num_channels_p-1:0][ddr_width_lp-1:0] core_piso_data_lo;
// Dequeue from PISO when all channels are ready
logic [num_channels_p-1:0] core_piso_ready_li;
if (piso_ratio_lp == 1 && bypass_gearbox_p != 0)
begin
assign core_piso_valid_lo = core_valid_i;
assign core_piso_data_lo = core_data_i;
assign core_ready_o = (& core_piso_ready_li);
end
else
begin: piso
assign core_piso_yumi_li = (& core_piso_ready_li) & core_piso_valid_lo;
bsg_parallel_in_serial_out
#(.width_p(ddr_width_lp*num_channels_p)
,.els_p (piso_ratio_lp)
) out_piso
(.clk_i (core_clk_i)
,.reset_i(core_link_reset_i)
,.valid_i(core_valid_i)
,.data_i (core_data_i)
,.ready_and_o(core_ready_o)
,.valid_o(core_piso_valid_lo)
,.data_o (core_piso_data_lo)
,.yumi_i (core_piso_yumi_li)
);
end
genvar i;
// multiple channels
for (i = 0; i < num_channels_p; i++)
begin: ch
// core side signals
logic core_ss_valid_li, core_ss_ready_lo, core_ss_data_nonzero;
logic [phy_width_lp-1:0] core_ss_data_top;
logic [1:0][channel_width_p/2-1:0] core_ss_data_bottom;
// io side signals
logic io_oddr_valid_li, io_oddr_ready_lo;
logic [1:0][phy_width_lp-1:0] io_oddr_data_raw, io_oddr_data_final;
// connect to piso
assign core_ss_valid_li = core_piso_valid_lo;
assign core_piso_ready_li[i] = core_ss_ready_lo;
assign core_ss_data_top = (phy_width_lp)'(core_piso_data_lo[i][ddr_width_lp-1:channel_width_p]);
if (use_encode_p == 0)
begin
assign core_ss_data_nonzero = 1'b0; // unused
assign core_ss_data_bottom = core_piso_data_lo[i][channel_width_p-1:0];
// valid sent out in first cycle
// When idle, balance hi / lo bits in each channel
assign io_oddr_data_final = (io_oddr_valid_li)?
{io_oddr_data_raw[1], 1'b1, io_oddr_data_raw[0][channel_width_p-1:0]}
: {2{1'b0, {(channel_width_p/2){2'b10}}}};
end
else
begin
// core side encode
assign core_ss_data_nonzero = ~(core_piso_data_lo[i][channel_width_p/2-1:0] == '0);
assign core_ss_data_bottom[1] = (core_ss_data_nonzero)?
{ core_piso_data_lo[i][channel_width_p-0-1:channel_width_p/2]}
: {1'b1, core_piso_data_lo[i][channel_width_p-1-1:channel_width_p/2]};
assign core_ss_data_bottom[0] = (core_ss_data_nonzero)?
{core_piso_data_lo[i][channel_width_p/2-1:0] }
: {core_piso_data_lo[i][channel_width_p-1], (channel_width_p/2-1)'(1'b1)};
// When idle, assign 1'b0 to certain wires to represent invalid state
// Assign 1'b1 to rest of the wires to balance hi / lo bits in each channel
assign io_oddr_data_final = (io_oddr_valid_li)?
io_oddr_data_raw
: {2{2'b00, (channel_width_p/2-1)'('1), (channel_width_p/2)'('0)}};
end
bsg_link_source_sync_upstream
#(.channel_width_p(2*phy_width_lp)
,.lg_fifo_depth_p(lg_fifo_depth_p)
,.lg_credit_to_token_decimation_p(lg_credit_to_token_decimation_p)
,.bypass_twofer_fifo_p(bypass_twofer_fifo_p)
) sso
(// control signals
.core_clk_i (core_clk_i)
,.core_link_reset_i (core_link_reset_i)
,.io_clk_i (io_clk_i)
,.io_link_reset_i (io_link_reset_i)
,.async_token_reset_i (async_token_reset_i)
// Input from chip core
,.core_data_i ({core_ss_data_top, core_ss_data_nonzero, core_ss_data_bottom})
,.core_valid_i (core_ss_valid_li)
,.core_ready_o (core_ss_ready_lo)
// source synchronous output channel; going to chip edge
,.io_data_o (io_oddr_data_raw)
,.io_valid_o (io_oddr_valid_li)
,.io_ready_i (io_oddr_ready_lo)
,.token_clk_i (token_clk_i[i])
);
// valid and data signals are sent together
bsg_link_oddr_phy
#(.width_p(phy_width_lp)
) oddr_phy
(.reset_i (io_link_reset_i)
,.clk_i (io_clk_i)
,.data_i (io_oddr_data_final)
,.ready_o (io_oddr_ready_lo)
,.data_r_o({io_valid_r_o[i], io_data_r_o[i]})
,.clk_r_o (io_clk_r_o[i])
);
end
// synopsys translate_off
initial
begin
assert (piso_ratio_lp > 0)
else
begin
$error("BaseJump STL ERROR %m: width_p should be larger than or equal to (ddr_width_lp*num_channels_p)");
$finish;
end
assert (piso_ratio_lp*(ddr_width_lp*num_channels_p) == width_p)
else
begin
$error("BaseJump STL ERROR %m: width_p should be multiple of (ddr_width_lp*num_channels_p)");
$finish;
end
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_link_ddr_upstream)
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const long long INFF = 1e18; const double pi = acos(-1.0); const double inf = 1e18; const double eps = 1e-9; const long long mod = 1e9 + 7; const int maxmat = 10; const unsigned long long BASE = 133333331; inline void RI(int &x) { char c; while ((c = getchar()) < 0 || c > 9 ) ; x = c - 0 ; while ((c = getchar()) >= 0 && c <= 9 ) x = (x << 3) + (x << 1) + c - 0 ; } const int dy[3] = {-1, 0, 1}; char maze[3][105]; bool vis[3][105][105]; int sx, sy; int N, k; struct Node { int x, y, t; }; bool valid(int x, int y, int t) { return (x >= 0 && x < 3 && y >= 0 && y < N && (maze[x][y + 2 * t] == . || maze[x][y + 2 * t] == 0)); } bool bfs(int x, int y) { queue<Node> q; q.push((Node){x, y, 0}); while (!q.empty()) { Node tmp = q.front(); q.pop(); if (tmp.y == N - 1) return true; if (maze[tmp.x][tmp.y + 1 + 2 * tmp.t] >= A && maze[tmp.x][tmp.y + 1 + 2 * tmp.t] <= Z ) continue; for (int k = 0; k < 3; k++) { int tmpx = tmp.x + dy[k]; int tmpy = tmp.y + 1; if (valid(tmpx, tmpy, tmp.t) && valid(tmpx, tmpy, tmp.t + 1) && !vis[tmpx][tmpy][tmp.t + 1]) { vis[tmpx][tmpy][tmp.t + 1] = true; q.push((Node){tmpx, tmpy, tmp.t + 1}); } } } return false; } int main(int argc, char const *argv[]) { int T; cin >> T; while (T--) { scanf( %d%d , &N, &k); memset(maze, 0, sizeof(maze)); memset(vis, false, sizeof(vis)); for (int i = 0; i < 3; i++) { char s[105]; scanf( %s , s); for (int j = 0; j < N; j++) { maze[i][j] = s[j]; if (maze[i][j] == s ) sx = i, sy = j; } } cout << (bfs(sx, sy) ? YES : NO ) << endl; } return 0; } |
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerPeripheralHdlAdi_tc.v
// Created: 2014-09-08 14:12:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerPeripheralHdlAdi_tc
// Source Path: controllerPeripheralHdlAdi_tc
// Hierarchy Level: 1
//
// Master clock enable input: clk_enable
//
// enb : identical to clk_enable
// enb_1_1_1 : identical to clk_enable
// enb_1_2000_0: 2000x slower than clk_enable with last phase
// enb_1_2000_1: 2000x slower than clk_enable with phase 1
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerPeripheralHdlAdi_tc
(
CLK_IN,
reset,
clk_enable,
enb,
enb_1_1_1,
enb_1_2000_0,
enb_1_2000_1
);
input CLK_IN;
input reset;
input clk_enable;
output enb;
output enb_1_1_1;
output enb_1_2000_0;
output enb_1_2000_1;
reg [10:0] count2000; // ufix11
wire phase_all;
reg phase_0;
wire phase_0_tmp;
reg phase_1;
wire phase_1_tmp;
always @ ( posedge CLK_IN)
begin: Counter2000
if (reset == 1'b1) begin
count2000 <= 11'b00000000001;
end
else begin
if (clk_enable == 1'b1) begin
if (count2000 == 11'b11111001111) begin
count2000 <= 11'b00000000000;
end
else begin
count2000 <= count2000 + 1;
end
end
end
end // Counter2000
assign phase_all = clk_enable? 1 : 0;
always @ ( posedge CLK_IN)
begin: temp_process1
if (reset == 1'b1) begin
phase_0 <= 1'b0;
end
else begin
if (clk_enable == 1'b1) begin
phase_0 <= phase_0_tmp;
end
end
end // temp_process1
assign phase_0_tmp = (count2000 == 11'b11111001111 && clk_enable == 1'b1)? 1 : 0;
always @ ( posedge CLK_IN)
begin: temp_process2
if (reset == 1'b1) begin
phase_1 <= 1'b1;
end
else begin
if (clk_enable == 1'b1) begin
phase_1 <= phase_1_tmp;
end
end
end // temp_process2
assign phase_1_tmp = (count2000 == 11'b00000000000 && clk_enable == 1'b1)? 1 : 0;
assign enb = phase_all & clk_enable;
assign enb_1_1_1 = phase_all & clk_enable;
assign enb_1_2000_0 = phase_0 & clk_enable;
assign enb_1_2000_1 = phase_1 & clk_enable;
endmodule // controllerPeripheralHdlAdi_tc
|
#include <bits/stdc++.h> using namespace std; const int INF = 1000000000; struct Point { int x, y; Point(int x_ = 0, int y_ = 0) : x(x_), y(y_) {} Point(std::istream &in) { in >> x >> y; x *= 2; y *= 2; } }; bool operator<(const Point &a, const Point &b) { return (a.x < b.x) || (a.x == b.x && a.y < b.y); } bool cmp_sum(const Point &a, const Point &b) { return (a.x + a.y < b.x + b.y); } bool cmp_diff(const Point &a, const Point &b) { return (a.x - a.y < b.x - b.y); } int n, k; vector<Point> gnome, metro; vector<int> sorted_x, sorted_y; vector<int> tree; int curk; void upd_val(int x, int val, const vector<int> &coords) { x = lower_bound(coords.begin(), coords.end(), x) - coords.begin(); x += curk; tree[x] = min(tree[x], val); x /= 2; while (x != 1) { tree[x] = min(tree[x * 2], tree[x * 2 + 1]); x /= 2; } } int get_min_val(int l, int r, const vector<int> &coords) { l = lower_bound(coords.begin(), coords.end(), l) - coords.begin(); r = lower_bound(coords.begin(), coords.end(), r) - coords.begin(); l += curk; r += curk; int res = INF; while (l < r) { res = min(res, min(tree[l], tree[r])); l = (l + 1) / 2; r = (r - 1) / 2; } if (l == r) { res = min(res, tree[l]); } return res; } void shrink(vector<int> &coord) { sort(coord.begin(), coord.end()); coord.resize(unique(coord.begin(), coord.end()) - coord.begin()); } template <typename T> std::vector<int> argsort(const std::vector<T> &vals, bool reverse = false) { vector<int> result(vals.size()); for (int i = 0; i < int(vals.size()); ++i) { result[i] = i; } sort(result.begin(), result.end(), [&](int a, int b) -> bool { return (vals[a] < vals[b]); }); if (reverse) { std::reverse(result.begin(), result.end()); } return result; } void get_min_dist(const std::vector<Point> &gnome, std::vector<Point> metro, std::vector<int> &result) { sorted_x.clear(); sorted_y.clear(); for (auto &x : gnome) { sorted_x.push_back(x.x); sorted_y.push_back(x.y); } for (auto &x : metro) { sorted_x.push_back(x.x); sorted_y.push_back(x.y); } shrink(sorted_x); shrink(sorted_y); int nn = gnome.size(); result.assign(nn, INF); auto indices = argsort(gnome); sort(metro.begin(), metro.end()); curk = 2; while (int(sorted_y.size()) > curk) curk *= 2; { tree.assign(2 * curk, INF); int l = 0, r = 0; while (l < nn) { int ind = indices[l]; while (r < k && metro[r].x <= gnome[ind].x) { upd_val(metro[r].y, -metro[r].x - metro[r].y, sorted_y); ++r; } result[ind] = min(result[ind], get_min_val(sorted_y.front(), gnome[ind].y, sorted_y) + gnome[ind].x + gnome[ind].y); ++l; } } { tree.assign(2 * curk, INF); int l = 0, r = 0; while (l < nn) { int ind = indices[l]; while (r < k && metro[r].x <= gnome[ind].x) { upd_val(metro[r].y, -metro[r].x + metro[r].y, sorted_y); ++r; } result[ind] = min(result[ind], get_min_val(gnome[ind].y, sorted_y.back(), sorted_y) + gnome[ind].x - gnome[ind].y); ++l; } } reverse(metro.begin(), metro.end()); reverse(indices.begin(), indices.end()); { tree.assign(2 * curk, INF); int l = 0, r = 0; while (l < nn) { int ind = indices[l]; while (r < k && metro[r].x >= gnome[ind].x) { upd_val(metro[r].y, metro[r].x - metro[r].y, sorted_y); ++r; } result[ind] = min(result[ind], get_min_val(sorted_y.front(), gnome[ind].y, sorted_y) - gnome[ind].x + gnome[ind].y); ++l; } } { tree.assign(2 * curk, INF); int l = 0, r = 0; while (l < nn) { int ind = indices[l]; while (r < k && metro[r].x >= gnome[ind].x) { upd_val(metro[r].y, metro[r].x + metro[r].y, sorted_y); ++r; } result[ind] = min(result[ind], get_min_val(gnome[ind].y, sorted_y.back(), sorted_y) - gnome[ind].x - gnome[ind].y); ++l; } } } int find_dist(pair<pair<int, int>, pair<int, int> > rect, const Point &pnt) { int sum = pnt.x + pnt.y; int diff = pnt.x - pnt.y; int sum_dist = max(0, -min(rect.first.second, sum) + max(rect.first.first, sum)); int diff_dist = max(0, -min(rect.second.second, diff) + max(rect.second.first, diff)); return max(sum_dist, diff_dist); } void get_all_min_dist(vector<pair<pair<int, int>, pair<int, int> > > rect, vector<Point> metro, vector<int> &dist) { dist.assign(n, INF); vector<Point> ok_points; for (int i = 0; i < n; ++i) { const auto &cr = rect[i]; int a, b, c, d; tie(a, b) = cr.first; tie(c, d) = cr.second; ok_points.emplace_back((a + c) / 2, (a - c) / 2); ok_points.emplace_back((a + d) / 2, (a - d) / 2); ok_points.emplace_back((b + c) / 2, (b - c) / 2); ok_points.emplace_back((b + d) / 2, (b - d) / 2); } vector<int> tmp; get_min_dist(ok_points, metro, tmp); for (int i = 0; i < n * 4; ++i) { dist[i / 4] = min(dist[i / 4], tmp[i]); } vector<int> sorted_sum; vector<int> sorted_diff; for (auto &pnt : rect) { sorted_sum.push_back(pnt.first.first); sorted_sum.push_back(pnt.first.second); sorted_diff.push_back(pnt.second.first); sorted_diff.push_back(pnt.second.second); } for (auto &pnt : metro) { sorted_sum.push_back(pnt.x + pnt.y); sorted_diff.push_back(pnt.x - pnt.y); } shrink(sorted_sum); shrink(sorted_diff); sort(metro.begin(), metro.end(), cmp_sum); curk = 2; while (curk < int(sorted_diff.size())) curk *= 2; vector<pair<pair<int, int>, pair<int, int> > > segment(n); for (int i = 0; i < n; ++i) { segment[i] = make_pair(make_pair(rect[i].first.first, i), rect[i].second); } sort(segment.begin(), segment.end()); { tree.assign(curk * 2, INF); int nn = segment.size(); int l = 0, r = 0; while (l < nn) { while (r < k && metro[r].x + metro[r].y <= segment[l].first.first) { upd_val(metro[r].x - metro[r].y, -metro[r].y - metro[r].x, sorted_diff); ++r; } int ind = segment[l].first.second; dist[ind] = min(dist[ind], get_min_val(segment[l].second.first, segment[l].second.second, sorted_diff) + segment[l].first.first); ++l; } } reverse(metro.begin(), metro.end()); for (int i = 0; i < n; ++i) { segment[i] = make_pair(make_pair(rect[i].first.second, i), rect[i].second); } sort(segment.rbegin(), segment.rend()); { tree.assign(curk * 2, INF); int nn = segment.size(); int l = 0, r = 0; while (l < nn) { while (r < k && metro[r].x + metro[r].y >= segment[l].first.first) { upd_val(metro[r].x - metro[r].y, metro[r].x + metro[r].y, sorted_diff); ++r; } int ind = segment[l].first.second; dist[ind] = min(dist[ind], get_min_val(segment[l].second.first, segment[l].second.second, sorted_diff) - segment[l].first.first); ++l; } } sort(metro.begin(), metro.end(), cmp_diff); for (int i = 0; i < n; ++i) { segment[i] = make_pair(make_pair(rect[i].second.first, i), rect[i].first); } sort(segment.begin(), segment.end()); curk = 2; while (curk < int(sorted_sum.size())) curk *= 2; { tree.assign(curk * 2, INF); int nn = segment.size(); int l = 0, r = 0; while (l < nn) { while (r < k && metro[r].x - metro[r].y <= segment[l].first.first) { upd_val(metro[r].x + metro[r].y, metro[r].y - metro[r].x, sorted_sum); ++r; } int ind = segment[l].first.second; dist[ind] = min(dist[ind], get_min_val(segment[l].second.first, segment[l].second.second, sorted_sum) + segment[l].first.first); ++l; } } reverse(metro.begin(), metro.end()); for (int i = 0; i < n; ++i) { segment[i] = make_pair(make_pair(rect[i].second.second, i), rect[i].first); } sort(segment.rbegin(), segment.rend()); { tree.assign(curk * 2, INF); int nn = segment.size(); int l = 0, r = 0; while (l < nn) { while (r < k && metro[r].x - metro[r].y >= segment[l].first.first) { upd_val(metro[r].x + metro[r].y, metro[r].x - metro[r].y, sorted_sum); ++r; } int ind = segment[l].first.second; dist[ind] = min(dist[ind], get_min_val(segment[l].second.first, segment[l].second.second, sorted_sum) - segment[l].first.first); ++l; } } } int main() { ios_base::sync_with_stdio(false); cin >> n >> k; for (int i = 0; i < n; ++i) { gnome.emplace_back(std::cin); } for (int i = 0; i < k; ++i) { metro.emplace_back(std::cin); } int min_x = INF, max_x = -INF; int min_y = INF, max_y = -INF; for (const auto &pnt : gnome) { min_x = min(min_x, pnt.x + pnt.y); max_x = max(max_x, pnt.x + pnt.y); min_y = min(min_y, pnt.x - pnt.y); max_y = max(max_y, pnt.x - pnt.y); } int result = (max(max_x - min_x, max_y - min_y) + 1) / 2; if (n > 1 && k) { vector<int> dist; get_min_dist(gnome, metro, dist); auto indices = argsort(dist, true); vector<pair<pair<int, int>, pair<int, int> > > all_rect; vector<int> add_dist; min_x = INF, max_x = -INF; min_y = INF, max_y = -INF; for (int i = 0; i < n; ++i) { const auto &pnt = gnome[indices[i]]; min_x = min(min_x, pnt.x + pnt.y); max_x = max(max_x, pnt.x + pnt.y); min_y = min(min_y, pnt.x - pnt.y); max_y = max(max_y, pnt.x - pnt.y); int dist = (max(max_x - min_x, max_y - min_y) + 1) / 2; add_dist.push_back(dist); all_rect.emplace_back(make_pair(max_x - dist, min_x + dist), make_pair(max_y - dist, min_y + dist)); } result = min(result, dist[indices[0]]); vector<int> new_dist; get_all_min_dist(all_rect, metro, new_dist); for (int i = 0; i < n - 1; ++i) { int t1 = add_dist[i]; int t2 = new_dist[i]; int t3 = dist[indices[i + 1]]; int x = (max(0, min(2 * t2, t3 + t2 - t1)) + 1) / 2; result = min(result, max(t1 + x, t3 + t2 - x)); } } result = (result + 1) / 2; cout << result << n ; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFBBP_BEHAVIORAL_V
`define SKY130_FD_SC_LS__SDFBBP_BEHAVIORAL_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`include "../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_ls__udp_dff_nsr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__sdfbbp (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire RESET ;
wire SET ;
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire CLK_delayed ;
wire SET_B_delayed ;
wire RESET_B_delayed;
wire mux_out ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
wire cond_D ;
wire cond_SCD ;
wire cond_SCE ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_ls__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK_delayed, mux_out, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
assign cond_D = ( ( SCE_delayed === 1'b0 ) && condb );
assign cond_SCD = ( ( SCE_delayed === 1'b1 ) && condb );
assign cond_SCE = ( ( D_delayed !== SCD_delayed ) && condb );
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFBBP_BEHAVIORAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR3_BEHAVIORAL_V
`define SKY130_FD_SC_MS__OR3_BEHAVIORAL_V
/**
* or3: 3-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__or3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A, C );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR3_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; const int MOD = 998244353; const int N_MAX = 50; int pwr(int a, int b) { if (b == 0) return 1; if (b & 1) return 1LL * pwr(a, (b ^ 1)) * a % MOD; int aux = pwr(a, (b >> 1)); return 1LL * aux * aux % MOD; } int n; int invf[N_MAX + 2]; struct Task { int l, r; }; Task tasks[N_MAX + 2]; int points[N_MAX * 2 + 2]; struct Segment { int l, r; }; Segment segments[N_MAX * 4 + 2]; int cntSeg; int combrep[N_MAX * 4 + 2][N_MAX + 2]; int lmax[N_MAX + 2][N_MAX + 2]; int rmin[N_MAX + 2][N_MAX + 2]; int invplg[N_MAX + 2][N_MAX + 2]; int dp[N_MAX + 2][N_MAX * 4 + 2][N_MAX + 2]; int sdp[N_MAX + 2][N_MAX * 4 + 2]; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n; for (int i = n; i >= 1; i--) { cin >> tasks[i].l >> tasks[i].r; points[i * 2 - 1] = tasks[i].l; points[i * 2] = tasks[i].r; } sort(points + 1, points + n * 2 + 1); segments[++cntSeg] = Segment{points[1], points[1]}; for (int i = 2; i <= n * 2; i++) if (points[i] > points[i - 1]) { if (points[i - 1] + 1 <= points[i] - 1) segments[++cntSeg] = Segment{points[i - 1] + 1, points[i] - 1}; segments[++cntSeg] = Segment{points[i], points[i]}; } invf[0] = 1; for (int i = 1; i <= n; i++) invf[i] = 1LL * invf[i - 1] * pwr(i, MOD - 2) % MOD; for (int i = 1; i <= cntSeg; i++) for (int j = 1; j <= n; j++) { combrep[i][j] = 1; int lg = segments[i].r - segments[i].l + 1; for (int k = lg; k <= lg + j - 1; k++) combrep[i][j] = 1LL * combrep[i][j] * k % MOD; combrep[i][j] = 1LL * combrep[i][j] * invf[j] % MOD; } for (int i = 1; i <= n; i++) { lmax[i][i - 1] = INT_MIN; rmin[i][i - 1] = INT_MAX; invplg[i][i - 1] = 1; for (int j = i; j <= n; j++) { lmax[i][j] = max(lmax[i][j - 1], tasks[j].l); rmin[i][j] = min(rmin[i][j - 1], tasks[j].r); invplg[i][j] = 1LL * invplg[i][j - 1] * pwr(tasks[j].r - tasks[j].l + 1, MOD - 2) % MOD; } } dp[0][0][0] = 1; sdp[0][0] = 1; for (int i = 1; i <= n; i++) for (int j = 1; j <= cntSeg; j++) for (int k = 1; k <= i; k++) { if (lmax[i - k + 1][i] > segments[j].l || segments[j].r > rmin[i - k + 1][i]) break; for (int j1 = 0; j1 < j; j1++) { dp[i][j][k] += sdp[i - k][j1]; if (dp[i][j][k] >= MOD) dp[i][j][k] -= MOD; } dp[i][j][k] = 1LL * dp[i][j][k] * combrep[j][k] % MOD; dp[i][j][k] = 1LL * dp[i][j][k] * invplg[i - k + 1][i] % MOD; sdp[i][j] += dp[i][j][k]; if (sdp[i][j] >= MOD) sdp[i][j] -= MOD; } int ans = 0; for (int j = 1; j <= cntSeg; j++) { ans += sdp[n][j]; if (ans >= MOD) ans -= MOD; } cout << ans << n ; return 0; } |
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/* Program memory has 2048 25-bit words */
module pfpu_prog(
input sys_clk,
input count_rst,
output [6:0] a_addr,
output [6:0] b_addr,
output [3:0] opcode,
output [6:0] w_addr,
/* Control interface */
input c_en,
input [1:0] c_page,
input [8:0] c_offset,
output [31:0] c_do,
input [31:0] c_di,
input c_w_en,
output [10:0] pc
);
/* Infer single port RAM */
wire [10:0] mem_a;
wire [24:0] mem_di;
reg [24:0] mem_do;
wire mem_we;
reg [24:0] mem[0:2047];
always @(posedge sys_clk) begin
if(mem_we)
mem[mem_a] <= mem_di;
mem_do <= mem[mem_a];
end
/* Control logic */
reg [10:0] counter;
always @(posedge sys_clk) begin
if(count_rst)
counter <= 10'd0;
else
counter <= counter + 10'd1;
end
assign mem_a = c_en ? {c_page, c_offset} : counter;
assign c_do = {7'd0, mem_do};
assign mem_di = c_di[24:0];
assign mem_we = c_en & c_w_en;
assign a_addr = mem_do[24:18]; // 7
assign b_addr = mem_do[17:11]; // 7
assign opcode = mem_do[10:7]; // 4
assign w_addr = mem_do[6:0]; // 7
assign pc = counter;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m; char block[][3][4] = {{ ### , .#. , .#. }, { #.. , ### , #.. }, { .#. , .#. , ### }, { ..# , ### , ..# }}; int cell[10][10], anscell[10][10]; int bcnt, ans; bool isPlacable(int i, int j, int k) { for (int p = 0; p < 3; ++p) for (int q = 0; q < 3; ++q) { if (cell[i + p][j + q] != -1 && block[k][p][q] == # ) return false; } return true; } void setBlock(int i, int j, int k) { for (int p = 0; p < 3; ++p) for (int q = 0; q < 3; ++q) { if (block[k][p][q] == # ) cell[i + p][j + q] = bcnt; } ++bcnt; } void removeBlock(int i, int j, int k) { for (int p = 0; p < 3; ++p) for (int q = 0; q < 3; ++q) { if (block[k][p][q] == # ) cell[i + p][j + q] = -1; } --bcnt; } void go(int i, int j) { if (j >= m - 2) { go(i + 1, 0); return; } if (i == n - 2) { if (ans < bcnt) { ans = bcnt; memcpy(anscell, cell, sizeof(cell)); } return; } if (bcnt + (n * m - (i * m + j)) / 6 <= ans) { return; } for (int k = 0; k < 4; ++k) { if (isPlacable(i, j, k)) { setBlock(i, j, k); go(i, j + (k == 3 ? 3 : 2)); removeBlock(i, j, k); } } go(i, j + 1); } int main() { memset(cell, -1, sizeof(cell)); memset(anscell, -1, sizeof(anscell)); scanf( %d %d , &n, &m); if (n >= 3 && m >= 3) go(0, 0); printf( %d n , ans); for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { putchar(anscell[i][j] == -1 ? . : ( A + anscell[i][j])); } putchar( n ); } return 0; } |
#include <bits/stdc++.h> long long int const MOD = 1000000007; long long int const N = 1000005; long long int const LN = 20; long long int const inf = 8e18; using namespace std; long long int n, m, a[N]; vector<pair<long long int, long long int> > v[N]; struct data { long long int d, second, prev, idx; data(long long int d, long long int second, long long int prev, long long int idx) { this->d = d; this->second = second; this->prev = prev; this->idx = idx; } bool operator<(data other) const { if (d != other.d) return d < other.d; if (second != other.second) return second < other.second; if (prev != other.prev) return prev < other.prev; if (idx != other.idx) return idx < other.idx; return 0; } }; int main() { ios::sync_with_stdio(false); cin.tie(NULL); long long int n, m, k; cin >> n >> m >> k; for (long long int i = 1; i <= m; i++) { long long int a, b, c; cin >> a >> b >> c; v[a].push_back({c, b}); v[b].push_back({c, a}); } for (long long int i = 1; i <= n; i++) sort(v[i].begin(), v[i].end()); set<pair<long long int, long long int> > st; set<data> q; for (long long int i = 1; i <= n; i++) { st.insert({i, i}); q.insert(data(v[i][0].first, i, i, 0)); } k = 2 * k; while (!q.empty()) { data cur = *q.begin(); q.erase(cur); long long int nxt = v[cur.prev][cur.idx].second; if (st.find({cur.second, nxt}) == st.end()) { st.insert({cur.second, nxt}); k--; if (k == 0) { cout << cur.d << n ; return 0; } q.insert(data(cur.d + v[nxt][0].first, cur.second, nxt, 0)); } if (cur.idx + 1 < v[cur.prev].size()) q.insert(data( cur.d - v[cur.prev][cur.idx].first + v[cur.prev][cur.idx + 1].first, cur.second, cur.prev, cur.idx + 1)); } return 0; } |
#include <bits/stdc++.h> using namespace std; long long int prime[1000010] = {0}; vector<long long int> pr; void sieve() { prime[0] = 1; prime[1] = 1; for (long long int i = 2; i <= sqrt(1000010); i++) { if (prime[i] == 0) { for (long long int j = i * i; j < 1000010; j += i) { prime[j] = 1; } } } for (long long int i = 2; i < 1000010; i++) { if (!prime[i]) pr.push_back(i); } return; } double pi = 3.141592653589; long long int a[200100]; long long int pre[200100] = {0}; signed main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long int n, w; cin >> n >> w; for (long long int i = 1; i <= n; i += 1) { cin >> a[i]; pre[i] = pre[i - 1] + a[i]; } long long int mi = 0, ma = 0; for (long long int i = 1; i <= n; i += 1) { mi = min(mi, pre[i]); ma = max(ma, pre[i]); } long long int ans = (w - ma) + (mi + 1); if (ans > w + 1 || ans < 0) cout << 0 << endl; else cout << ans << endl; } |
#include <bits/stdc++.h> long long mpow(long long a, long long n, long long mod) { long long ret = 1; long long b = a; while (n) { if (n & 1) ret = (ret * b) % mod; b = (b * b) % mod; n >>= 1; } return (long long)ret; } using namespace std; int a[100000 + 5]; map<int, int> ind; long long cnt[1500]; long long dp[1400][1400]; long long fact[100000 + 5]; long long inv[100000 + 5]; void computefact() { fact[0] = 1; inv[0] = 1; long long i, j; for (j = 1; j < 100000 + 5; j++) { fact[j] = (fact[j - 1] * j) % 1000000007; inv[j] = mpow(fact[j], 1000000007 - 2, 1000000007); } } long long ncr(long long n, long long r) { long long den = (inv[r] * inv[n - r]) % 1000000007; long long num = (fact[n] * den) % 1000000007; return num; } bool chk(int x) { while (x != 0) { int p = x % 10; if (!(p == 4 || p == 7)) { return 0; } x /= 10; } return 1; } int main() { int i, j; vector<int> luck; long long n, len; cin >> n >> len; long long unl = 0; int c = 1; computefact(); for (j = 0; j < n; j++) { cin >> a[j]; if (chk(a[j])) { if (!ind[a[j]]) { luck.push_back(a[j]); ind[a[j]] = c; cnt[c]++; c++; } else { cnt[ind[a[j]]]++; } } else unl++; } dp[0][0] = 1; int sz = luck.size(); for (i = 1; i <= sz; i++) { for (j = 0; j <= sz; j++) { dp[i][j] = (dp[i - 1][j] + (dp[i - 1][j - 1] * cnt[i]) % 1000000007) % 1000000007; } } long long ans = 0; for (long long k = 0; k <= min(len, unl); k++) { long long q = len - k; if (q > sz) continue; ans = (ans + (ncr(unl, k) * dp[sz][q]) % 1000000007) % 1000000007; } cout << ans; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND2B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__NAND2B_BEHAVIORAL_PP_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__nand2b (
Y ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out , B );
or or0 (or0_out_Y , not0_out, A_N );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND2B_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISO0P_PP_SYMBOL_V
`define SKY130_FD_SC_LP__INPUTISO0P_PP_SYMBOL_V
/**
* inputiso0p: Input isolator with non-inverted enable.
*
* X = (A & !SLEEP_B)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__inputiso0p (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input SLEEP,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISO0P_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int arr[105]; int n; cin >> n; for (int x = 0; x < n; x++) { cin >> arr[x]; } sort(arr, arr + n); for (int x = 0; x < n; x++) { cout << arr[x] << ; } } |
`include "hglobal.v"
`default_nettype none
`define NS_MAX_DATA_VAL MAX_DATA_VAL[DSZ-1:0]
module hprb_sink
#(parameter
MY_LOCAL_ADDR=0,
PRB_SRC_ADDR=0,
ASZ=`NS_ADDRESS_SIZE,
DSZ=`NS_DATA_SIZE,
RSZ=`NS_REDUN_SIZE
)(
`NS_DECLARE_GLB_CHNL(gch),
`NS_DECLARE_IN_CHNL(rcv0),
`NS_DECLARE_ERR_CHNL(err0)
);
parameter RCV_REQ_CKS = `NS_REQ_CKS;
`NS_DEBOUNCER_REQ(gch_clk, gch_reset, rcv0)
reg [0:0] rg_rdy = `NS_OFF;
// SNK_0 regs
reg [0:0] has_inp0 = `NS_OFF;
reg [0:0] inp0_has_redun = `NS_OFF;
reg [0:0] inp0_done_cks = `NS_OFF;
`NS_DECLARE_REG_MSG(inp0)
wire [RSZ-1:0] inp0_calc_redun;
reg [RSZ-1:0] inp0_redun = 0;
calc_redun #(.ASZ(ASZ), .DSZ(DSZ), .RSZ(RSZ))
md_calc_red0 (inp0_src, inp0_dst, inp0_dat, inp0_calc_redun);
parameter MAX_DATA_VAL = $rtoi($pow(2, DSZ) - 1);
reg [0:0] inp0_ack = `NS_OFF;
reg [DSZ-1:0] inp0_back_dat = `NS_MAX_DATA_VAL;
reg [0:0] inp0_err = `NS_OFF;
`NS_DECLARE_ERR_REG(inp0_err) // inp0_err_error
//SNK_0
always @(posedge gch_clk)
begin
if(gch_reset) begin
rg_rdy <= `NS_OFF;
end
if(! gch_reset && ! rg_rdy) begin
rg_rdy <= ! rg_rdy;
has_inp0 <= `NS_OFF;
inp0_has_redun <= `NS_OFF;
inp0_done_cks <= `NS_OFF;
`NS_REG_MSG_INIT(inp0)
inp0_redun <= 0;
inp0_ack <= `NS_OFF;
inp0_back_dat <= `NS_MAX_DATA_VAL;
`NS_INIT_ERR_REG(inp0_err)
end
if(! gch_reset && rg_rdy) begin
if(rcv0_ckd_req && (! inp0_ack)) begin
if(! has_inp0) begin
has_inp0 <= `NS_ON;
`NS_MOV_REG_MSG(inp0, rcv0)
end
else
if(! inp0_has_redun) begin
inp0_has_redun <= `NS_ON;
inp0_redun <= inp0_calc_redun;
end
else
if(! inp0_done_cks) begin
inp0_done_cks <= `NS_ON;
if(! inp0_err_error) begin
if(inp0_dst != MY_LOCAL_ADDR) begin
inp0_err_error <= `NS_ON;
`NS_MOV_REG_MSG(inp0_err, inp0)
end
else
if(inp0_src != PRB_SRC_ADDR) begin
inp0_err_error <= `NS_ON;
`NS_MOV_REG_MSG(inp0_err, inp0)
end
else
if(inp0_red != inp0_redun) begin
inp0_err_error <= `NS_ON;
`NS_MOV_REG_MSG(inp0_err, inp0)
end
//else
if((inp0_back_dat <= (`NS_MAX_DATA_VAL - 1)) && ((inp0_back_dat + 1) != inp0_dat)) begin
inp0_err_error <= `NS_ON;
`NS_MOV_REG_MSG(inp0_err, inp0)
end
else
begin
inp0_back_dat <= inp0_dat;
end
end
end
if(inp0_done_cks) begin
has_inp0 <= `NS_OFF;
inp0_has_redun <= `NS_OFF;
inp0_done_cks <= `NS_OFF;
inp0_ack <= `NS_ON;
end
end
else
if((! rcv0_ckd_req) && inp0_ack) begin
inp0_ack <= `NS_OFF;
end
end
end
assign gch_ready = rg_rdy && rcv0_rdy;
//SNK_0
assign rcv0_ack_out = inp0_ack;
`NS_ASSIGN_ERR_CHNL(err0, inp0_err, MY_LOCAL_ADDR)
endmodule
|
Require Export Arith.
Require Export ArithRing.
Require Export Omega.
Ltac CaseEq f := generalize (refl_equal f);
pattern f at -1 in |- *; case f.
Fixpoint div4 (n:nat) : nat * nat :=
match n with
| S (S (S (S p))) => let (q, r) := div4 p in (S q, r)
| a => (0, a)
end.
Fixpoint bsqrt (n b:nat) {struct b} : nat * nat :=
match b with
| O => (0, 0)
| S b' =>
match div4 n with
| (O, O) => (0, 0)
| (O, S p) => (1, p)
| (q, r0) =>
let (s', r') := bsqrt q b' in
match le_gt_dec (4 * s' + 1) (4 * r' + r0) with
| left _ => (2 * s' + 1, 4 * r' + r0 - (4 * s' + 1))
| right _ => (2 * s', 4 * r' + r0)
end
end
end.
(* We start by proving a few basic properties of division by 4.
As suggested in section 8.3.1, we can use a specific induction
principle to work on div4. This is also the solution to exercise
\ref{quadruple_induction}. *)
Theorem div4_ind :
forall P:nat -> Prop,
P 0 ->
P 1 ->
P 2 ->
P 3 -> (forall n:nat, P n -> P (S (S (S (S n))))) -> forall n:nat, P n.
Proof.
intros P P0 P1 P2 P3 Prec n.
cut (P n /\ P (S n) /\ P (S (S n)) /\ P (S (S (S n)))).
intuition.
elim n; intuition.
Qed.
(* Proving the main characteristics of div4 is easy using
div4_ind. We avoid using Simpl so that multiplications
do not get unfolded into additions. *)
Lemma div4_exact : forall n:nat, let (q, r) := div4 n in n = 4 * q + r.
Proof.
intros n; elim n using div4_ind; try (simpl in |- *; auto; fail).
intros p; cbv beta iota zeta delta [div4] in |- *; fold div4 in |- *.
case (div4 p).
intros q r Hrec; rewrite Hrec; ring.
Qed.
(* Since 4 is a constant, we can use div4_exact to
obtain a linear equality in the sense of Presburger arithmetic
and the Omega decision procedure can cope with the formula.*)
Theorem div4_lt : forall n:nat, let (q, r) := div4 n in 0 < q -> q < n.
Proof.
intros n; generalize (div4_exact n); case (div4 n).
intros q r Heq; omega.
Qed.
Theorem div4_lt_rem : forall n:nat, let (q, r) := div4 n in r < 4.
Proof.
intros n; elim n using div4_ind; try (simpl in |- *; auto with arith).
intros p; case (div4 p); auto.
Qed.
Ltac remove_minus :=
match goal with
| |- context [(?X1 - ?X2 + ?X3)] =>
rewrite <- (plus_comm X3); remove_minus
| |- context [(?X1 + (?X2 - ?X3) + ?X4)] =>
rewrite (plus_assoc_reverse X1 (X2 - X3)); remove_minus
| |- context [(?X1 + (?X2 + (?X3 - ?X4)))] =>
rewrite (plus_assoc X1 X2 (X3 - X4))
| |- (_ = ?X1 + (?X2 - ?X3)) =>
apply (fun n m p:nat => plus_reg_l m p n) with X3;
try rewrite (plus_permute X3 X1 (X2 - X3));
rewrite le_plus_minus_r
end.
(* The proof of this goal is a simple matter of computation, but
NatRing can't cope with it because of the irregular behavior of
minus. The tactic remove_minus defined above takes care of that by
adding the subtracted term on both side of the equality, and then
simplifying with le_plus_minus. This simplification only works
because the theorem has the right hypothesis. *)
Theorem bsqrt_exact_lemma_le :
forall n q r s' r':nat,
n = 4 * q + r ->
q = s' * s' + r' ->
4 * s' + 1 <= 4 * r' + r ->
n = (2 * s' + 1) * (2 * s' + 1) + (4 * r' + r - (4 * s' + 1)).
Proof.
intros; remove_minus.
subst; ring.
assumption.
Qed.
Lemma bsqrt_exact_lemma_gt :
forall n q r s' r':nat,
n = 4 * q + r ->
q = s' * s' + r' ->
4 * s' + 1 > 4 * r' + r -> n = 2 * s' * (2 * s') + (4 * r' + r).
Proof.
intros; subst; ring.
Qed.
Theorem bsqrt_exact :
forall b n:nat, n <= b -> let (s, r) := bsqrt n b in n = s * s + r.
Proof.
(* Induction on the bound, as should always be the case
for bounded recursive functions. *)
intros b; elim b.
(* When the bound is zero, if n is lower than the bound, it
is also 0, it is only a matter of computation to check the
equality. *)
intros n Hle; rewrite <- (le_n_O_eq _ Hle); simpl in |- *; auto.
(*We limit simplification to the bsqrt function. *)
intros b' Hrec n Hle; cbv beta iota zeta delta [bsqrt] in |- *;
fold bsqrt in |- *.
(* We use the lemmas on div4. To avoid CaseEq, we rely on
Generalize before doing a Case analysis. *)
generalize (div4_lt n) (div4_exact n).
case (div4 n).
intros q r.
case q.
case r; intros; subst; ring.
intros q' Hlt Heq; generalize (Hrec (S q')).
case (bsqrt (S q') b').
intros s' r' Hrec'.
(* Because le_gt_dec is a well-specified function,
there is no need to generalize hypotheses to perform
the case analysis on this function call. *)
case (le_gt_dec (4 * s' + 1) (4 * r' + r)).
apply bsqrt_exact_lemma_le with (S q'); auto; omega.
apply bsqrt_exact_lemma_gt with (S q'); auto; omega.
Qed.
Theorem bsqrt_rem :
forall b n:nat, n <= b ->
let (s, r) := bsqrt n b in n < (s + 1) * (s + 1).
Proof.
intros b; elim b.
intros n Hle; rewrite <- (le_n_O_eq _ Hle);
simpl in |- *; auto with arith.
(*We limit simplification to the bsqrt function. *)
intros b' Hrec n Hle; generalize (bsqrt_exact (S b') n Hle);
cbv beta iota zeta delta [bsqrt] in |- *; fold bsqrt in |- *.
(* We use the lemmas on div4. To avoid CaseEq, we rely on
Generalize before doing a Case analysis. *)
generalize (div4_lt n) (div4_exact n) (div4_lt_rem n).
case (div4 n).
intros q r.
case q.
case r; intros; subst; simpl in |- *; auto with arith.
intros q' Hlt Heq Hlt_rem; generalize (Hrec (S q')).
case (bsqrt (S q') b').
intros s' r' Hrec'.
(* Because le_gt_dec is a well-specified function,
there is no need to generalize hypothesese to perform
the case analysis on this function call. *)
case (le_gt_dec (4 * s' + 1) (4 * r' + r)).
intros Hle' Heq'; rewrite Heq.
apply lt_le_trans with (4 * S q' + 4).
auto with arith.
replace ((2 * s' + 1 + 1) * (2 * s' + 1 + 1)) with
(4 * ((s' + 1) * (s' + 1))).
abstract omega.
ring.
intros Hgt Heq'; rewrite Heq'.
match goal with
| |- (?X1 < ?X2) => ring_simplify X1; ring_simplify X2
end.
abstract omega.
Qed.
Definition sqrt_nat :
forall n:nat,
{s : nat & {r : nat | n = s * s + r /\ n < (s + 1) * (s + 1)}}.
intros n;
generalize (bsqrt_exact n n (le_n n)) (bsqrt_rem n n (le_n n));
case (bsqrt n n).
intros s r H1 H2; exists s; exists r; auto.
Defined.
Eval compute in (bsqrt 37 37).
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11.06.2017 19:11:16
// Design Name:
// Module Name: clock_divider
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module clock_divider(
input clk,
input rst,
output reg clk_div
);
localparam constantNumber = 8_000;
reg [63:0] count;
always @ (posedge(clk) or posedge(rst))
begin
if (rst == 1'b1)
count <= 32'd0;
else if (count == (constantNumber - 32'd1))
count <= 32'd0;
else
count <= count + 32'b1;
end
always @ (posedge(clk) or posedge(rst))
begin
if (rst == 1'b1)
clk_div <= 1'b0;
else if (count == (constantNumber - 1))
clk_div <= ~clk_div;
else
clk_div <= clk_div;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; int main() { scanf( %d , &n); if (n <= 2) { puts( No ); return 0; } puts( Yes ); if (n & 1) { printf( 2 1 %d n , n); printf( %d , n - 2); for (int i = 2; i < n; i++) printf( %d , i); puts( ); } else { printf( %d n , n / 2); for (int i = 1; i <= n; i++) if (i & 1) printf( %d , i); puts( ); printf( %d n , n / 2); for (int i = 1; i <= n; i++) if (!(i & 1)) printf( %d , i); puts( ); } } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 1000100; int N; long long arr[MAXN]; long long csum; long long nv[MAXN]; long long dp[MAXN][2]; long long gogo(long long x) { nv[0] = 0; for (int i = 0; i < N; i++) { nv[i + 1] = (nv[i] + arr[i]) % x; } for (int i = 0; i <= N; i++) { dp[i][0] = dp[i][1] = 3e18; } dp[0][0] = nv[1]; dp[0][1] = (x - nv[1]); for (int i = 1; i < N; i++) { if ((x - nv[i]) + nv[i + 1] <= arr[i]) dp[i][0] = min(dp[i][0], dp[i - 1][1] + nv[i + 1]); if (nv[i + 1] - nv[i] <= arr[i]) dp[i][0] = min(dp[i][0], dp[i - 1][0] + nv[i + 1]); if ((x - nv[i]) + (nv[i + 1] - x) <= arr[i]) dp[i][1] = min(dp[i][1], dp[i - 1][1] + (x - nv[i + 1])); dp[i][1] = min(dp[i][1], dp[i - 1][0] + (x - nv[i + 1])); } return min(dp[N - 1][1], dp[N - 1][0]); } int main() { ios_base::sync_with_stdio(0); csum = 0; cin >> N; for (int i = 0; i < N; i++) { cin >> arr[i]; csum += arr[i]; } vector<long long> v; for (long long i = 2; i < MAXN; i++) { if (csum % i == 0) { v.push_back(i); while (csum % i == 0) csum /= i; } } if (csum > 1) v.push_back(csum); long long ans = 3e18; for (long long f : v) ans = min(ans, gogo(f)); if (ans > 2e18) cout << -1 n ; else cout << ans << n ; } |
// DESCRIPTION: Verilator: Verilog Test module
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2009 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
// End of automatics
Test #(16,2) test (/*AUTOINST*/
// Outputs
.out (out[31:0]),
// Inputs
.clk (clk),
.in (in[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hf9b3a5000165ed38
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, in
);
input clk;
input [31:0] in;
output [31:0] out;
parameter N = 0;
parameter PASSDOWN = 1;
add #(PASSDOWN) add (.in (in[(2*N)-1:(0*N)]),
.out (out));
endmodule
module add (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
parameter PASSDOWN = 9999;
input [31:0] in;
output [31:0] out;
wire out = in + PASSDOWN;
endmodule
|
#include <bits/stdc++.h> using namespace std; void read() { freopen( in.txt , r , stdin); freopen( out.txt , w , stdout); } bool voi(char c) { return (c == a || c == e || c == i || c == y || c == o || c == u ); } long long log_pow(long long b, long long p) { if (p == 0) return 1; if (p == 1) return b; if (p % 2) return b * log_pow(b, p - 1); long long r = log_pow(b, p / 2); return r * r; } int d5l_i() { int x; scanf( %d , &x); return x; } long long d5l_l() { long long x; scanf( %lld , &x); return x; } char d5l_c() { char x; scanf( %c , &x); return x; } long long fact(int n) { long long fc = 1; for (int i = 2; i <= n; i++) fc *= i; return fc; } int len(long long n) { int c = 0; while (n) { n /= 2; c++; } return c; } bool why(int a, int b, int c) { return ((long long)a + b > c && (long long)c + b > a && (long long)c + a > b); } int a[100005]; long long ans; int main() { int n = d5l_i(), m = d5l_i(); for (int i = 0; i < n; i++) a[i] = d5l_i(); sort(a, a + n); vector<int> v; bool flag = false, ops = false; for (int i = 1; i < a[0]; i++) { if (ans + i > m) { ops = true; break; } ans += i; v.push_back(i); } if (!ops) for (int i = 0; i < n - 1; i++) { for (int j = a[i] + 1; j < a[i + 1]; j++) { if (ans + j > m) { flag = true; break; } ans += j; v.push_back(j); } if (flag) break; } if (!flag && !ops) for (int i = a[n - 1] + 1; i <= 1e9; i++) { if (ans + i > m) break; ans += i; v.push_back(i); } printf( %d n , v.size()); for (int i = 0; i < v.size(); i++) printf( %d , v[i]); } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAPVGND2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__TAPVGND2_BEHAVIORAL_PP_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection 2
* rows down.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__tapvgnd2 (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAPVGND2_BEHAVIORAL_PP_V |
/* This file is part of JT12.
JT12 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 21-03-2019
*/
module jt12_dout(
// input rst_n,
input clk, // CPU clock
input flag_A,
input flag_B,
input busy,
input [5:0] adpcma_flags,
input adpcmb_flag,
input [7:0] psg_dout,
input [1:0] addr,
output reg [7:0] dout
);
parameter use_ssg=0, use_adpcm=0;
always @(posedge clk) begin
casez( addr )
2'b00: dout <= {busy, 5'd0, flag_B, flag_A }; // YM2203
2'b01: dout <= (use_ssg ==1) ? psg_dout : {busy, 5'd0, flag_B, flag_A };
2'b1?: dout <= (use_adpcm==1) ?
{ adpcmb_flag, 1'b0, adpcma_flags } :
{ busy, 5'd0, flag_B, flag_A };
endcase
end
endmodule // jt12_dout |
#include <bits/stdc++.h> using namespace std; bool vis[10010][51]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int m, n; cin >> m >> n; for (int i = 0; i < m; i++) { int k; cin >> k; for (int j = 0; j < k; j++) { int temp; cin >> temp; vis[temp][i] = true; } } for (int i = 0; i < m; i++) { for (int j = i + 1; j < m; j++) { int flag = 0; for (int k = 1; k < n + 1; k++) { if (vis[k][i] && vis[k][j]) { flag = 1; break; } } if (flag == 0) { cout << impossible << endl; return 0; } } } cout << possible << endl; } |
#include <bits/stdc++.h> using namespace std; int n, m, ya, yb, a[100003], b[100003], l[100003], dp[2][100003], ans; int main() { cin >> n >> m >> ya >> yb; ans = n; for (int i = 0; i < n; i++) scanf( %d , a + i); for (int i = 1; i <= m; i++) scanf( %d , b + i); b[0] = -998244353; m++; b[m] = 998244353; m++; for (int i = 0; i < m; i++) l[i] = 998244353; for (int i = 0; i < n; i++) { int j = lower_bound(b, b + m, a[i]) - b; int d = min(a[i] - b[j - 1], b[j] - a[i]); if (b[j] - a[i] > d || (a[i] - b[j - 1] == d && (l[j - 1] == 998244353 || l[j - 1] == d))) j--; if (l[j] == 998244353 || l[j] == d) ans--; l[j] = min(l[j], d); } cout << ans; } |
#include <bits/stdc++.h> using namespace std; int n, k; int a[5005]; int q, x; bool bfind(int p) { int lf = 0; int rt = n - 1; int mid; while (lf <= rt) { mid = (lf + rt) / 2; if (a[mid] < p) { lf = mid + 1; } else if (a[mid] > p) { rt = mid - 1; } else return true; } return false; } int main() { while (scanf( %d %d , &n, &k) != EOF) { for (int i = 0; i < n; i++) { scanf( %d , &a[i]); } scanf( %d , &q); while (q--) { int mn = k + 1; scanf( %d , &x); for (int i = n - 1; i >= 0; i--) { for (int j = 0; j <= k; j++) { if (a[i] * j == x) { mn = min(mn, j); break; } if (a[i] * j > x) break; for (int m = 1; m <= k - j; m++) { if ((x - a[i] * j) % m != 0) continue; int tmp = (x - a[i] * j) / m; if (bfind(tmp)) mn = min(mn, j + m); } } } if (mn > k) printf( -1 n ); else printf( %d n , mn); } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 10e5; int minc, maxk = 0; long long int a[maxn], c[maxn]; int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); cout << setprecision(30); int n, s; cin >> n >> s; for (int i = 0; i < n; i++) cin >> a[i]; int l = 0, r = n + 1; while (r - l > 1) { long long int mid = (l + r) / 2, tc = 0; for (int i = 0; i < n; i++) c[i] = mid * (i + 1) + a[i]; sort(c, c + n); for (int i = 0; i < mid; i++) tc += c[i]; if (tc > s) { r = mid; } if (tc <= s) { minc = tc; maxk = mid; l = mid; } } cout << maxk << << minc; return 0; } |
// AJ, Beck, and Ray
// addition testbench
// 5/4/15
`include "adder_subtractor.v"
`include "flag.v"
`include "Implementation/mux2_1.sv"
`include "adder16b.v"
`include "adder4b.v"
`include "fullAdder1b.v"
`include "lookAhead4b.v"
`include "addition.v"
module additiontest();
// localize variables
wire [31:0] busADD;
wire [31:0] busA, busB;
wire zADD, oADD, cADD, nADD;
// declare an instance of the module
addition addition (busADD, busA, busB, zADD, oADD, cADD, nADD);
// Running the GUI part of simulation
additiontester tester (busADD, busA, busB, zADD, oADD, cADD, nADD);
// file for gtkwave
initial
begin
$dumpfile("additiontest.vcd");
$dumpvars(1, addition);
end
endmodule
module additiontester (busADD, busA, busB, zADD, oADD, cADD, nADD);
input [31:0] busADD;
output reg [31:0] busA, busB;
input zADD, oADD, cADD, nADD;
parameter d = 20;
initial // Response
begin
$display("busADD \t busA \t busB \t\t zADD \t oADD \t cADD \t nADD \t ");
#d;
end
reg [31:0] i;
initial // Stimulus
begin
$monitor("%b \t %b \t %b \t %b \t %b \t %b \t %b", busADD, busA, busB, zADD, oADD, cADD, nADD, $time);
// positive + positive
busA = 32'h01010101; busB = 32'h01010101;
#d;
busA = 32'h7FFFFFFF; busB = 32'h7FFFFFFF; // should overflow
#d;
// positive + negative
busA = 32'h01010101; busB = 32'hFFFFFFFF; // 01010101 + -1
#d;
busA = 32'h00000001; busB = 32'hF0000000;
#d;
// negative + positive
busA = 32'hFFFFFFFF; busB = 32'h01010101;
#d;
busA = 32'hF0000000; busB = 32'h00000001;
#d;
// negative + negative
busA = 32'hFFFFFFFF; busB = 32'hFFFFFFFF; // -1 + -1
#d;
busA = 32'h90000000; busB = 32'h80000000; // should overflow
#d;
#(3*d);
$stop;
$finish;
end
endmodule |
/**
* decoder_complex.v - Microcoded Accumulator CPU
* Copyright (C) 2015 Orlando Arias, David Mascenik
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
`include "aludefs.v"
module decoder_complex(
input wire [ 7 : 0] opcode, /* opcode */
input wire [`FWIDTH - 1 : 0] flags, /* ALU flags */
output reg [`MC_OFFSET_WIDTH - 1 : 0] op_decoder_out /* microcode offset */
);
always @(*) begin
case(opcode)
/* add from immediate memory address into accumulator */
8'h00: op_decoder_out = `MC_OFFSET_WIDTH'h0a;
/* store from accumulator into immediate address */
8'h01: op_decoder_out = `MC_OFFSET_WIDTH'h08;
/* load from immediate address into accumulator */
8'h02: op_decoder_out = `MC_OFFSET_WIDTH'h04;
/* absolute branch to immediate address */
8'h03: op_decoder_out = `MC_OFFSET_WIDTH'h0e;
/* jump if negative */
8'h04: op_decoder_out =
flags[`NEGATIVE_FLAG] ?
`MC_OFFSET_WIDTH'h0e
: `MC_OFFSET_WIDTH'h0f;
/* subtract from immediate memory address into accumulator */
8'h05: op_decoder_out = `MC_OFFSET_WIDTH'h16;
/* exclusive OR from immediate memory address into accumulator */
8'h06: op_decoder_out = `MC_OFFSET_WIDTH'h1a;
/* NOR from immediate memory address into accumulator */
8'h07: op_decoder_out = `MC_OFFSET_WIDTH'h1e;
/* NAND from immediate memory address into accumulator */
8'h08: op_decoder_out = `MC_OFFSET_WIDTH'h22;
/* jump if positive */
8'h09: op_decoder_out =
flags[`NEGATIVE_FLAG] ?
`MC_OFFSET_WIDTH'h0f
: `MC_OFFSET_WIDTH'h0e;
/* jump if zero */
8'h0a: op_decoder_out =
flags[`ZERO_FLAG] ?
`MC_OFFSET_WIDTH'h0e
: `MC_OFFSET_WIDTH'h0f;
/* add immediate into accumulator */
8'h0b: op_decoder_out = `MC_OFFSET_WIDTH'h26;
/* accumulator arithmetic shift left */
8'h0d: op_decoder_out = `MC_OFFSET_WIDTH'h29;
/* accumulator arithmetic shift right */
8'h0e: op_decoder_out = `MC_OFFSET_WIDTH'h28;
/* jump if carry set */
8'h70: op_decoder_out =
flags[`CARRY_FLAG] ?
`MC_OFFSET_WIDTH'h0e
: `MC_OFFSET_WIDTH'h0f;
/* jump if overflow set */
8'h71: op_decoder_out =
flags[`OVERFLOW_FLAG] ?
`MC_OFFSET_WIDTH'h0e
: `MC_OFFSET_WIDTH'h0f;
/* increment accumulator */
8'h72: op_decoder_out = `MC_OFFSET_WIDTH'h10;
/* compare with immediate constant */
8'h73: op_decoder_out = `MC_OFFSET_WIDTH'h11;
/* compare with value at immediate address */
8'h74: op_decoder_out = `MC_OFFSET_WIDTH'h12;
/* invert accumulator */
8'h75: op_decoder_out = `MC_OFFSET_WIDTH'h27;
/* clear accumulator register */
8'h7e: op_decoder_out = `MC_OFFSET_WIDTH'h02;
/* load immediate into accumulator register */
8'h7f: op_decoder_out = `MC_OFFSET_WIDTH'h03;
default:op_decoder_out = {`MC_OFFSET_WIDTH{1'b1}};
endcase
end
endmodule
`include "aluundefs.v"
/* vim: set ts=4 tw=79 syntax=verilog */
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, h, k; cin >> n >> m >> h >> k; cout << ((n > m) ? First : Second ) << endl; return 0; } |
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2011 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file cx4_datram.v when simulating
// the core, cx4_datram. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module cx4_datram(
clka,
wea,
addra,
dina,
douta,
clkb,
web,
addrb,
dinb,
doutb
);
input clka;
input [0 : 0] wea;
input [11 : 0] addra;
input [7 : 0] dina;
output [7 : 0] douta;
input clkb;
input [0 : 0] web;
input [11 : 0] addrb;
input [7 : 0] dinb;
output [7 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V6_2 #(
.C_ADDRA_WIDTH(12),
.C_ADDRB_WIDTH(12),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("77"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(3072),
.C_READ_DEPTH_B(3072),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(1),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(3072),
.C_WRITE_DEPTH_B(3072),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.CLKB(clkb),
.WEB(web),
.ADDRB(addrb),
.DINB(dinb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.RSTB(),
.ENB(),
.REGCEB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> const double pi = 3.1415926535; using namespace std; int main() { double n, r; cin >> n >> r; r = sin(pi / n) * r / (1 - sin(pi / n)); cout << fixed << setprecision(7) << r; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long MOD = 1000000007; template <typename T> inline T Bigmod(T base, T power, T MOD) { T ret = 1; while (power) { if (power & 1) ret = (ret * base) % MOD; base = (base * base) % MOD; power >>= 1; } return ret; } bool sortinrev(const pair<int, int> &a, const pair<int, int> &b) { return (a.first > b.first); } int main() { ios::sync_with_stdio(false); int n, m; while (cin >> n >> m) { int a[n]; int b[m]; int max_a = 0, min_a = 110, min_b = 110; for (int i = 0; i < n; i++) { cin >> a[i]; max_a = max(max_a, a[i]); min_a = min(min_a, a[i]); } for (int i = 0; i < m; i++) { cin >> b[i]; min_b = min(min_b, b[i]); } if (max(2 * min_a, max_a) < min_b) cout << max(2 * min_a, max_a) << endl; else cout << -1 n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long M = 2100000; const long long N = 210000; struct node { long long inx; long long a, b; long long m; long long lt, rt; }; vector<node> odd_nodes[M]; vector<node> even_nodes[M]; bool cmp(node a, node b) { if (a.lt == b.lt) return a.rt > b.rt; else return a.lt < b.lt; } long long lt_ans[N], rt_ans[N]; set<long long> op; int main() { ios::sync_with_stdio(false); long long tt; cin >> tt; while (tt--) { op.clear(); long long m, n; cin >> n; long long a, b; for (long long i = 0; i < n; i++) { cin >> a >> b >> m; long long mn = max(0ll, a - m); long long tb = b - (m - (a - mn)); long long mx = max(0ll, b - m); long long ta = a - (m - (b - mx)); long long v = a + b - m; op.insert(v); odd_nodes[v].push_back({i, a, b, m, mn - tb, ta - mx}); } long long ans = 0; for (auto &u : op) { auto &p = odd_nodes[u]; if (p.empty()) continue; sort(p.begin(), p.end(), cmp); long long st = 0, ed = 1e9; for (long long i = 0; i < p.size(); i++) { if (p[i].lt > ed) { for (long long j = st; j < i; j++) { long long t = (p[j].a - p[j].b + p[j].m - ed) / 2; lt_ans[p[j].inx] = t; rt_ans[p[j].inx] = p[j].m - t; } ans++; ed = p[i].rt; st = i; } else { ed = min(ed, p[i].rt); } } ans++; for (long long j = st; j < p.size(); j++) { long long t = (p[j].a - p[j].b + p[j].m - ed) / 2; lt_ans[p[j].inx] = t; rt_ans[p[j].inx] = p[j].m - t; } p.clear(); } cout << ans << endl; for (long long i = 0; i < n; i++) cout << lt_ans[i] << << rt_ans[i] << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int DIM = 1005; bitset<DIM> oki; int val[DIM], nxt[DIM]; int main(void) { ios ::sync_with_stdio(false); cin.tie(); cout.tie(); int n, m, ans = 0; cin >> n >> m; for (int i = 1; i <= n; ++i) cin >> val[i], nxt[i] = -1; for (int i = 1; i <= m; ++i) { int x; cin >> x; for (int j = 1; j <= n; ++j) if (nxt[x] < nxt[j]) ans += val[j]; nxt[x] = i; } cout << ans << endl; return 0; } |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2010 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 11.1i (L.12)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Static Dual Port Synchronous RAM 32-Deep by 1-Wide
// /___/ /\ Filename : RAMD32.v
// \ \ / \ Timestamp : Thu Mar 25 16:44:03 PST 2004
// \___\/\___\
//
// Revision:
// 07/02/10 - Initial version.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 04/16/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps/1 ps
`celldefine
module RAMD32 #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter [31:0] INIT = 32'h00000000,
parameter [0:0] IS_CLK_INVERTED = 1'b0
)(
output O,
input CLK,
input I,
input RADR0,
input RADR1,
input RADR2,
input RADR3,
input RADR4,
input WADR0,
input WADR1,
input WADR2,
input WADR3,
input WADR4,
input WE
);
reg [31:0] mem;
wire [4:0] WADR_dly, WADR_in;
wire [4:0] radr;
wire I_dly, CLK_dly, WE_dly;
wire I_in, CLK_in, WE_in;
localparam MODULE_NAME = "RAMD32";
initial begin
mem[31:0] = INIT;
`ifndef XIL_TIMING
$display("ERROR: SIMPRIM primitive %s instance %m is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the SIMPRIM library.", MODULE_NAME);
$finish;
`endif
end
assign radr[4:0] = {RADR4, RADR3, RADR2, RADR1, RADR0};
always @(posedge CLK_in)
if (WE_in == 1'b1)
mem[WADR_in] <= #100 I_in;
assign O = mem[radr];
`ifdef XIL_TIMING
reg notifier;
always @(notifier)
mem[WADR_in] <= 1'bx;
`endif
`ifndef XIL_TIMING
assign I_dly = I;
assign CLK_dly = CLK;
assign WADR_dly = {WADR4, WADR3, WADR2, WADR1, WADR0};
assign WE_dly = WE;
`endif
assign CLK_in = IS_CLK_INVERTED ^ CLK_dly;
assign WE_in = WE_dly;
assign I_in = I_dly;
assign WADR_in = WADR_dly;
specify
(CLK => O) = (0:0:0, 0:0:0);
(RADR0 => O) = (0:0:0, 0:0:0);
(RADR1 => O) = (0:0:0, 0:0:0);
(RADR2 => O) = (0:0:0, 0:0:0);
(RADR3 => O) = (0:0:0, 0:0:0);
(RADR4 => O) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING
$period (negedge CLK &&& WE, 0:0:0, notifier);
$period (posedge CLK &&& WE, 0:0:0, notifier);
$setuphold (negedge CLK, negedge I &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,I_dly);
$setuphold (negedge CLK, negedge WADR0 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[0]);
$setuphold (negedge CLK, negedge WADR1 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[1]);
$setuphold (negedge CLK, negedge WADR2 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[2]);
$setuphold (negedge CLK, negedge WADR3 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[3]);
$setuphold (negedge CLK, negedge WADR4 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[4]);
$setuphold (negedge CLK, negedge WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WE_dly);
$setuphold (negedge CLK, posedge I &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,I_dly);
$setuphold (negedge CLK, posedge WADR0 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[0]);
$setuphold (negedge CLK, posedge WADR1 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[1]);
$setuphold (negedge CLK, posedge WADR2 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[2]);
$setuphold (negedge CLK, posedge WADR3 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[3]);
$setuphold (negedge CLK, posedge WADR4 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[4]);
$setuphold (negedge CLK, posedge WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WE_dly);
$setuphold (posedge CLK, negedge I &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,I_dly);
$setuphold (posedge CLK, negedge WADR0 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[0]);
$setuphold (posedge CLK, negedge WADR1 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[1]);
$setuphold (posedge CLK, negedge WADR2 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[2]);
$setuphold (posedge CLK, negedge WADR3 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[3]);
$setuphold (posedge CLK, negedge WADR4 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[4]);
$setuphold (posedge CLK, negedge WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WE_dly);
$setuphold (posedge CLK, posedge I &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,I_dly);
$setuphold (posedge CLK, posedge WADR0 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[0]);
$setuphold (posedge CLK, posedge WADR1 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[1]);
$setuphold (posedge CLK, posedge WADR2 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[2]);
$setuphold (posedge CLK, posedge WADR3 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[3]);
$setuphold (posedge CLK, posedge WADR4 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[4]);
$setuphold (posedge CLK, posedge WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WE_dly);
$width (negedge CLK, 0:0:0, 0, notifier);
$width (posedge CLK, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
#include <bits/stdc++.h> const int maxn = 5e5 + 5; const int logn = 21; const int lim = 2e1; const int maxq = 5e5 + 5; struct w { int l, r, id; friend bool operator<(w now, w oth) { return now.r < oth.r; } } qu[maxq]; int b[logn], p[logn]; void insert(int gave, int id) { for (int i = lim; i >= 0; i--) { if (!(gave >> i & 1)) continue; if (!b[i]) { b[i] = gave; p[i] = id; return; } if (p[i] < id) { std::swap(p[i], id); std::swap(b[i], gave); } gave ^= b[i]; } return; } int tian(int lef) { int r = 0; for (int i = lim; i >= 0; i--) if (p[i] >= lef) r = std::max(r, r ^ b[i]); return r; } int o[maxq]; int n, q; int v[maxn]; signed main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , v + i); scanf( %d , &q); for (int i = 1; i <= q; i++) { scanf( %d%d , &qu[i].l, &qu[i].r); qu[i].id = i; } std::sort(qu + 1, qu + q + 1); int nr = 0; for (int i = 1; i <= q; i++) { while (nr < qu[i].r) { nr++; insert(v[nr], nr); } o[qu[i].id] = tian(qu[i].l); } for (int i = 1; i <= q; i++) printf( %d n , o[i]); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long int inf = 1e18; const int N = 1e5 + 5; void solve() { int n; cin >> n; set<int> st; for (int i = 0; i < n; i++) { int x; cin >> x; if (x % 2 == 0) st.insert(x); } int ans = 0; while (!st.empty()) { int x = *st.rbegin(); st.erase(x); if (x % 2 == 0) st.insert(x / 2), ans++; } cout << ans << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout << fixed << showpoint; cout << setprecision(9); int test = 1; cin >> test; while (test--) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false), cin.tie(NULL); long long n; cin >> n; vector<long long> a(n); for (int i = 0; i < n; i++) { cin >> a[i]; } if (n == 1) { cout << YES ; return 0; } vector<long long> v; long long cnt0 = 1; for (int i = 1; i < n; i++) { if (a[i] != a[i - 1]) { v.push_back(cnt0); cnt0 = 1; } else cnt0++; if (i == n - 1) { v.push_back(cnt0); } } long long cnt = 1; for (int i = 0; i < v.size(); i++) { if (v[i] == v[i + 1]) cnt++; } if (cnt == v.size()) cout << YES ; else cout << NO ; } |
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ninja2.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module ninja2 (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./sprites/ninja2.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./sprites/ninja2.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja2.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja2.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja2.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja2.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja2_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja2_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e18; const int maxn = 200; long long x, y, l, r; void solve() { set<long long> a, b, S; a.insert(1); b.insert(1); long long base = x; while (base <= INF) { a.insert(base); if (INF / base < x || x == 1) break; base *= x; } base = y; while (base <= INF) { b.insert(base); if (INF / base < y || y == 1) break; base *= y; } for (auto i : a) for (auto j : b) if (i + j <= r && i + j >= l) S.insert(i + j); S.insert(r + 1); long long pre = l - 1; long long ans = 0; for (auto z : S) { ans = max(ans, z - pre - 1); pre = z; } cout << ans << endl; } int main() { ios::sync_with_stdio(false); while (cin >> x >> y >> l >> r) solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 60; map<double, int> p; bitset<N * N> g[N * N + 5]; int n, m; double ya[N + 5], yb[N + 5]; int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) scanf( %lf , &ya[i]); for (int i = 1; i <= m; i++) scanf( %lf , &yb[i]); int tot = 0; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { double now = (ya[i] + yb[j]) / 2; if (p.find(now) == p.end()) tot++, p[now] = tot; g[p[now]].set(i, 1); g[p[now]].set(j + n, 1); } } int ans = -1; for (int i = 1; i <= tot; i++) { for (int j = i; j <= tot; j++) { bitset<N * N> s; s = g[i] | g[j]; ans = max(ans, (int)s.count()); } } printf( %d n , ans); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFSTP_BLACKBOX_V
`define SKY130_FD_SC_HS__SDFSTP_BLACKBOX_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__sdfstp (
CLK ,
D ,
Q ,
SCD ,
SCE ,
SET_B
);
input CLK ;
input D ;
output Q ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFSTP_BLACKBOX_V
|
module top #(parameter CLOCK_FREQ = 33_000_000, parameter BAUD_RATE = 921600)
(
input [3:0] lpc_ad,
input lpc_clock,
input lpc_frame,
input lpc_reset,
input ext_clock,
input fscts,
input fsdo,
output fsdi,
output fsclk,
output lpc_clock_led,
output lpc_frame_led,
output lpc_reset_led,
output valid_lpc_output_led,
output overflow_led);
/* power on reset */
wire reset;
/* buffering */
wire [3:0] lpc_ad;
/* lpc */
wire [3:0] dec_cyctype_dir;
wire [31:0] dec_addr;
wire [7:0] dec_data;
wire dec_sync_timeout;
/* bufferdomain*/
wire [47:0] lpc_data;
wire [47:0] write_data;
wire lpc_data_enable;
/* ring buffer */
wire read_clock_enable;
wire write_clock_enable;
wire empty;
wire overflow;
/* mem2serial */
wire [47:0] read_data;
/* uart tx */
wire uart_ready;
wire [7:0] uart_data;
wire uart_clock_enable;
wire uart_clock;
wire trigger_port;
wire no_lpc_reset;
wire main_clock;
wire pll_locked;
pll PLL(.clock_in(ext_clock),
.clock_out(main_clock),
.locked(pll_locked));
power_on_reset POR(
.pll_locked(pll_locked),
.clock(main_clock),
.reset(reset));
lpc LPC(
.lpc_ad(lpc_ad),
.lpc_clock(lpc_clock),
.lpc_frame(lpc_frame),
.lpc_reset(no_lpc_reset),
.reset(reset),
.out_cyctype_dir(dec_cyctype_dir),
.out_addr(dec_addr),
.out_data(dec_data),
.out_sync_timeout(dec_sync_timeout),
.out_clock_enable(lpc_data_enable));
bufferdomain #(.AW(48))
BUFFERDOMAIN(
.input_data(lpc_data),
.input_enable(lpc_data_enable),
.reset(reset),
.clock(main_clock),
.output_data(write_data),
.output_enable(write_clock_enable));
assign lpc_data[47:16] = dec_addr;
assign lpc_data[15:8] = dec_data;
assign lpc_data[7:5] = 0;
assign lpc_data[4] = dec_sync_timeout;
assign lpc_data[3:0] = dec_cyctype_dir;
ringbuffer #(.AW(10), .DW(48))
RINGBUFFER (
.reset(reset),
.clock(main_clock),
.write_clock_enable(write_clock_enable),
.read_clock_enable(read_clock_enable),
.read_data(read_data),
.write_data(write_data),
.empty(empty),
.overflow(overflow));
mem2serial MEM_SERIAL(
.reset(reset),
.clock(main_clock),
.read_empty(empty),
.read_clock_enable(read_clock_enable),
.read_data(read_data),
.uart_clock_enable(uart_clock_enable),
.uart_ready(uart_ready),
.uart_data(uart_data));
wire [1:0] state;
ftdi SERIAL (
.read_data(uart_data),
.read_clock_enable(uart_clock_enable),
.reset(reset),
.ready(uart_ready),
.fsdi(fsdi),
.fscts(fscts),
.state(state),
.clock(main_clock));
assign fsclk = main_clock;
trigger_led TRIGGERLPC(
.reset(reset),
.clock(main_clock),
.led(valid_lpc_output_led),
.trigger(trigger_port));
//assign trigger_port = dec_addr == 32'h80 && dec_data == 8'h34 && dec_cyctype_dir == 4'b0010;
//assign trigger_port = dec_addr == 32'h3f9 && dec_cyctype_dir == 4'b0100;
assign trigger_port = dec_cyctype_dir == 4'b0100;
assign lpc_clock_led = 0;
assign lpc_frame_led = 0;
assign lpc_reset_led = 1;
assign no_lpc_reset = 1;
assign overflow_led = overflow;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 300005; int n; long long x1, x2; struct sss { long long val; int num; } a[maxn]; bool cmp(const sss &a, const sss &b) { return a.val > b.val; } void scanff() { scanf( %d%I64d%I64d , &n, &x1, &x2); for (int i = 1; i <= n; i++) { scanf( %I64d , &a[i].val); a[i].num = i; } sort(a + 1, a + n + 1, cmp); } void work() { int now1, now2; bool flag = false; if (x1 < x2) { swap(x1, x2); flag = true; } for (now1 = 1; now1 <= n; now1++) { if (a[now1].val * now1 >= x1) break; } if (now1 > n) { printf( No n ); return; } for (now2 = now1 + 1; now2 <= n; now2++) { if (a[now2].val * (now2 - now1) >= x2) break; } if (now2 > n) { int head = 1, tail = now1; for (;;) { if (tail + 1 <= n) { if (a[tail + 1].val * (tail - head + 1) >= x1) { tail++; head++; if (a[head - 1].val * (head - 1) >= x2) { printf( Yes n ); if (!flag) { printf( %d %d n , tail - head + 1, head - 1); for (int i = head; i <= tail; i++) { printf( %d , a[i].num); } printf( n ); for (int i = 1; i <= head - 1; i++) { printf( %d , a[i].num); } return; } else { printf( %d %d n , head - 1, tail - head + 1); for (int i = 1; i <= head - 1; i++) { printf( %d , a[i].num); } printf( n ); for (int i = head; i <= tail; i++) { printf( %d , a[i].num); } return; } } } else { tail++; } } else break; } printf( No n ); return; } printf( Yes n ); if (!flag) { printf( %d %d n , now1, now2 - now1); for (int i = 1; i <= now1; i++) { printf( %d , a[i].num); } printf( n ); for (int i = now1 + 1; i <= now2; i++) { printf( %d , a[i].num); } } else { printf( %d %d n , now2 - now1, now1); for (int i = now1 + 1; i <= now2; i++) { printf( %d , a[i].num); } printf( n ); for (int i = 1; i <= now1; i++) { printf( %d , a[i].num); } } } int main() { scanff(); work(); return 0; } |
//---------------------------------------------------------------------------
// Testbench
//---------------------------------------------------------------------------
//
//***************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
// from Xilinx, and may be used, copied and/or disclosed only
// pursuant to the terms of a valid license agreement with Xilinx.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
// does not warrant that functions included in the Materials will
// meet the requirements of Licensee, or that the operation of the
// Materials will be uninterrupted or error-free, or that defects
// in the Materials will be corrected. Furthermore, Xilinx does
// not warrant or make any representations regarding use, or the
// results of the use, of the Materials in terms of correctness,
// accuracy, reliability or otherwise.
//
// Xilinx products are not designed or intended to be fail-safe,
// or for use in any application requiring fail-safe performance,
// such as life-support or safety devices or systems, Class III
// medical devices, nuclear facilities, applications related to
// the deployment of airbags, or any other applications that could
// lead to death, personal injury or severe property or
// environmental damage (individually and collectively, "critical
// applications"). Customer assumes the sole risk and liability
// of any use of Xilinx products in critical applications,
// subject only to applicable laws and regulations governing
// limitations on product liability.
//
// Copyright 2009 Xilinx, Inc.
// All rights reserved.
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//***************************************************************************
//
`timescale 1ns / 1ps
module tb;
reg tb_ACLK;
reg tb_ARESETn;
wire temp_clk;
wire temp_rstn;
reg [31:0] read_data;
wire [7:0] leds;
reg resp;
initial
begin
tb_ACLK = 1'b0;
end
//------------------------------------------------------------------------
// Simple Clock Generator
//------------------------------------------------------------------------
always #10 tb_ACLK = !tb_ACLK;
initial
begin
$display ("running the tb");
tb_ARESETn = 1'b0;
repeat(2)@(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);
repeat(5) @(posedge tb_ACLK);
//Reset the PL
tb.zynq_sys.base_zynq_design_i.processing_system7_0.inst.fpga_soft_reset(32'h1);
tb.zynq_sys.base_zynq_design_i.processing_system7_0.inst.fpga_soft_reset(32'h0);
//This drives the LEDs on the GPIO output
tb.zynq_sys.base_zynq_design_i.processing_system7_0.inst.write_data(32'h41200000,4, 32'hFFFFFFFF, resp);
$display ("LEDs are toggled, observe the waveform");
//Write into the BRAM through GP0 and read back
tb.zynq_sys.base_zynq_design_i.processing_system7_0.inst.write_data(32'h40000000,4, 32'hDEADBEEF, resp);
tb.zynq_sys.base_zynq_design_i.processing_system7_0.inst.read_data(32'h40000000,4,read_data,resp);
$display ("%t, running the testbench, data read from BRAM was 32'h%x",$time, read_data);
if(read_data == 32'hDEADBEEF) begin
$display ("Zynq BFM Test PASSED");
end
else begin
$display ("Zynq BFM Test FAILED");
end
$display ("Simulation completed");
$stop;
end
assign temp_clk = tb_ACLK;
assign temp_rstn = tb_ARESETn;
base_zynq_design_wrapper zynq_sys
(.DDR_addr(),
.DDR_ba(),
.DDR_cas_n(),
.DDR_ck_n(),
.DDR_ck_p(),
.DDR_cke(),
.DDR_cs_n(),
.DDR_dm(),
.DDR_dq(),
.DDR_dqs_n(),
.DDR_dqs_p(),
.DDR_odt(),
.DDR_ras_n(),
.DDR_reset_n(),
.DDR_we_n(),
.FIXED_IO_ddr_vrn(),
.FIXED_IO_ddr_vrp(),
.FIXED_IO_mio(),
.FIXED_IO_ps_clk(temp_clk),
.FIXED_IO_ps_porb(temp_rstn ),
.FIXED_IO_ps_srstb(temp_rstn),
.leds_8bits_tri_o(leds));
endmodule
|
#include <bits/stdc++.h> using namespace std; map<int, int> mp; int main() { ios::sync_with_stdio(false); cin.tie(0); int n; cin >> n; for (int i = 1; i <= n; i++) { int num; cin >> num; mp[num]++; } if (mp.size() != 2) { cout << NO ; exit(0); } if (mp.begin()->second != mp.rbegin()->second) { cout << NO ; exit(0); } cout << YES n ; cout << mp.begin()->first << << mp.rbegin()->first; return 0; } |
#include <bits/stdc++.h> using namespace std; struct Graph { struct Edge { int u, v; int cost; Edge(int _u, int _v, int _cost) : u(_u), v(_v), cost(_cost) {} }; int n, m; bool is_digraph; vector<vector<int>> g; vector<Edge> e; Graph(int _n) : n(_n), m(0) { assert(n >= 1); g.resize(n); set_di(false); } Graph(int _n, int _m, bool _di = false) : n(_n) { assert(n >= 1); g.resize(n); e.reserve(_m); m = 0; set_di(_di); input(_m); } void set_di(bool _di) { pos = vector<int>(n, 0); deg = vector<int>(n, 0); is_digraph = _di; } vector<int> deg; inline void add(int u, int v, int cost = 1) { assert(0 <= u && u < n); assert(0 <= v && v < n); if (is_digraph) { g[u].emplace_back(m); } else { deg[u]++; deg[v]++; g[u].emplace_back(m); g[v].emplace_back(m); } e.emplace_back(u, v, cost); m++; } void input(int _m) { int u, v; for (int i = 0; i < _m; i++) { cin >> u >> v; u--; v--; add(u, v); } } vector<int> pos; void dfs(int u) { for (; pos[u] < g[u].size(); pos[u]++) { int i = g[u][pos[u]]; int v = e[i].u ^ e[i].v ^ u; dfs(v); } } int k; void dele() { int need_del = m - (n + m + 1) / 2; if (need_del > 0) { int cnt = 0; random_shuffle(e.begin(), e.end()); vector<int> d = deg; for (auto& x : e) { if (cnt < need_del && d[x.u] - 1 >= (deg[x.u] + 1) / 2 && d[x.v] - 1 >= (deg[x.v] + 1) / 2) { d[x.u]--; d[x.v]--; x.cost = 0; cnt++; } } assert(cnt == need_del); k = (n + m + 1) / 2; } else { k = m; } } void pri() { cout << k << n ; for (auto& x : e) { if (x.cost) cout << x.u + 1 << << x.v + 1 << n ; } } }; void solve() { int n, m; cin >> n >> m; Graph g(n, m); g.dele(); g.pri(); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); solve(); cout << endl; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFRTP_BLACKBOX_V
`define SKY130_FD_SC_HVL__DFRTP_BLACKBOX_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__dfrtp (
Q ,
CLK ,
D ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFRTP_BLACKBOX_V
|
///////////////////////////////////////////////////////////////////////////////
//
// Module: dest_ip_filter.v
// Project: NF2.1
// Description: matches the ip destination to on in a list and indicates hits
//
///////////////////////////////////////////////////////////////////////////////
module dest_ip_filter
#(parameter DATA_WIDTH = 64,
parameter LUT_DEPTH = `ROUTER_OP_LUT_DST_IP_FILTER_TABLE_DEPTH,
parameter LUT_DEPTH_BITS = log2(LUT_DEPTH)
)
(// --- Interface to the previous stage
input [DATA_WIDTH-1:0] in_data,
// --- Interface to process block
output dest_ip_hit,
output dest_ip_filter_vld,
input rd_dest_ip_filter_result,
// --- Interface to preprocess block
input word_IP_SRC_DST,
input word_IP_DST_LO,
// --- Interface to registers
// --- Read port
input [LUT_DEPTH_BITS-1:0] dest_ip_filter_rd_addr, // address in table to read
input dest_ip_filter_rd_req, // request a read
output [31:0] dest_ip_filter_rd_ip, // ip to match in the CAM
output dest_ip_filter_rd_ack, // pulses high
// --- Write port
input [LUT_DEPTH_BITS-1:0] dest_ip_filter_wr_addr,
input dest_ip_filter_wr_req,
input [31:0] dest_ip_filter_wr_ip, // data to match in the CAM
output dest_ip_filter_wr_ack,
// --- Misc
input reset,
input clk
);
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
//---------------------- Wires and regs----------------------------
wire cam_busy;
wire cam_match;
wire [LUT_DEPTH-1:0] cam_match_addr;
wire [31:0] cam_cmp_din, cam_cmp_data_mask;
wire [31:0] cam_din, cam_data_mask;
wire cam_we;
wire [LUT_DEPTH_BITS-1:0] cam_wr_addr;
reg dst_ip_vld;
reg [31:0] dst_ip;
//------------------------- Modules-------------------------------
// 1 cycle read latency, 2 cycles write latency
// priority encoded for the smallest address.
/*
bram_cam_unencoded_32x32 dest_ip_cam
(
// Outputs
.busy (cam_busy),
.match (cam_match),
.match_addr (cam_match_addr),
// Inputs
.clk (clk),
.cmp_din (cam_cmp_din),
.din (cam_din),
.we (cam_we),
.wr_addr (cam_wr_addr));
*/
//wire cam_busy_signal_reg;
cam dest_ip_cam
(
.reset(reset),
.wr_clk(clk),
.wr_en(cam_we),
.wr_key(cam_din),
.wr_index(cam_wr_addr),
.wr_erase_n(1'b1),
.rd_clk(clk),
.rd_en(dst_ip_vld),
.rd_key(cam_cmp_din),
.one_hot_addr(cam_match_addr),
.match_addr(),
.match(cam_match),
.multi_match(),
.index_reg(),
.cam_full(),
.multi_index()
);
// assign cam_busy = cam_busy_signal_reg;
//assign cam_busy = 1'b0;
localparam
IDLE_STATE_CAM = 2'b00,
FIRST_STATE_CAM = 2'b01,
SECOND_STATE_CAM = 2'b10;
reg [1:0] state_cam,state_cam_nxt;
reg cam_busy_signal_reg,cam_busy_signal_reg_next;
always @(posedge clk) begin
if (reset) begin
state_cam <= IDLE_STATE_CAM;
cam_busy_signal_reg <= 1'b0;
end
else begin
state_cam <= state_cam_nxt;
cam_busy_signal_reg <= cam_busy_signal_reg_next;
end // else
end
always @(*) begin
cam_busy_signal_reg_next = cam_busy_signal_reg;
state_cam_nxt = state_cam;
case (state_cam)
IDLE_STATE_CAM: begin
if (cam_we) begin
cam_busy_signal_reg_next = 1'b1;
state_cam_nxt = FIRST_STATE_CAM;
end
else
cam_busy_signal_reg_next = 1'b0;
end
FIRST_STATE_CAM: begin
cam_busy_signal_reg_next = 1'b1;
state_cam_nxt = SECOND_STATE_CAM;
end
SECOND_STATE_CAM: begin
cam_busy_signal_reg_next = 1'b0;
state_cam_nxt = IDLE_STATE_CAM;
end
endcase // case(state)
end
assign cam_busy = cam_busy_signal_reg;
unencoded_cam_lut_sm
#(.CMP_WIDTH(32), // IPv4 addr width
.DATA_WIDTH(1), // no data
.LUT_DEPTH(LUT_DEPTH),
.DEFAULT_DATA(0)
) cam_lut_sm
(// --- Interface for lookups
.lookup_req (dst_ip_vld),
.lookup_cmp_data (dst_ip),
.lookup_cmp_dmask (32'h0),
.lookup_ack (lookup_ack),
.lookup_hit (lookup_hit),
.lookup_data (),
// --- Interface to registers
// --- Read port
.rd_addr (dest_ip_filter_rd_addr), // address in table to read
.rd_req (dest_ip_filter_rd_req), // request a read
.rd_data (), // data found for the entry
.rd_cmp_data (dest_ip_filter_rd_ip), // matching data for the entry
.rd_cmp_dmask (), // don't cares entry
.rd_ack (dest_ip_filter_rd_ack), // pulses high
// --- Write port
.wr_addr (dest_ip_filter_wr_addr),
.wr_req (dest_ip_filter_wr_req),
.wr_data (1'b0), // data found for the entry
.wr_cmp_data (dest_ip_filter_wr_ip), // matching data for the entry
.wr_cmp_dmask (32'h0), // don't cares for the entry
.wr_ack (dest_ip_filter_wr_ack),
// --- CAM interface
.cam_busy (cam_busy),
.cam_match (cam_match),
.cam_match_addr (cam_match_addr),
.cam_cmp_din (cam_cmp_din),
.cam_din (cam_din),
.cam_we (cam_we),
.cam_wr_addr (cam_wr_addr),
.cam_cmp_data_mask (cam_cmp_data_mask),
.cam_data_mask (cam_data_mask),
// --- Misc
.reset (reset),
.clk (clk));
fallthrough_small_fifo #(.WIDTH(1), .MAX_DEPTH_BITS(2))
dest_ip_filter_fifo
(.din (lookup_hit), // Data in
.wr_en (lookup_ack), // Write enable
.rd_en (rd_dest_ip_filter_result), // Read the next word
.dout (dest_ip_hit),
.full (),
.nearly_full (),
.prog_full (),
.empty (empty),
.reset (reset),
.clk (clk)
);
//------------------------- Logic --------------------------------
assign dest_ip_filter_vld = !empty;
/*****************************************************************
* find the dst IP address and do the lookup
*****************************************************************/
always @(posedge clk) begin
if(reset) begin
dst_ip <= 0;
dst_ip_vld <= 0;
end
else begin
if(word_IP_SRC_DST) begin
dst_ip[31:16] <= in_data[15:0];
dst_ip_vld <= 0;
end
if(word_IP_DST_LO) begin
dst_ip[15:0] <= in_data[DATA_WIDTH-1:DATA_WIDTH-16];
dst_ip_vld <= 1;
end
else begin
dst_ip_vld <= 0;
end
end // else: !if(reset)
end // always @ (posedge clk)
endmodule // dest_ip_filter
|
#include <bits/stdc++.h> using namespace std; int n, m, i, a[1005], b[1005], Id[1005]; int ans, ans1, ans2; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); b[i] = a[i]; Id[b[i]] = i; } sort(a + 1, a + n + 1); i = 1; while (i <= n) { if (a[i] != b[i]) { m = Id[a[i]]; for (int j = i + 1; j <= m; j++) if (b[j] != b[j - 1] - 1) { printf( 0 0 n ); return 0; } ans++; ans1 = i; ans2 = m; i = m; } i++; } if (ans != 1) printf( 0 0 n ); else printf( %d %d n , ans1, ans2); return 0; } |
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module bd_350b_slot_0_aw_0 (
In0,
In1,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
output wire [1 : 0] dout;
xlconcat_v2_1_1_xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(2),
.NUM_PORTS(2)
) inst (
.In0(In0),
.In1(In1),
.In2(1'B0),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> inline void chkmax(T &x, T y) { if (x < y) x = y; } template <class T> inline void chkmin(T &x, T y) { if (x > y) x = y; } int t, n, m, k, cnt[26]; bool vis[200020]; char s[200020]; int solve() { int ans = 1000000007; for (int i = 0; i < n; i++) vis[i] = 0; vis[0] = 1; for (int i = 0; i < 26; i++) { for (int j = n - 1; j >= 0; j--) { if (vis[j]) { if (j + cnt[i] >= n) { if (j + cnt[i] + m <= k) return 0; chkmin(ans, (n - j) * (j + cnt[i] + m - k)); } else vis[j + cnt[i]] = 1; } } } for (int i = 0; i < m; i++) vis[i] = 0; vis[0] = 1; for (int i = 0; i < 26; i++) { for (int j = m - 1; j >= 0; j--) { if (vis[j]) { if (j + cnt[i] >= m) { if (j + cnt[i] + n <= k) return 0; chkmin(ans, (m - j) * (j + cnt[i] + n - k)); } else vis[j + cnt[i]] = 1; } } } return ans; } int main() { scanf( %d , &t); while (t--) { scanf( %d %d %d , &n, &m, &k); scanf( %s , s); memset(cnt, 0, sizeof cnt); for (int i = 0; i < k; i++) cnt[s[i] - A ]++; sort(cnt, cnt + 26, greater<int>()); printf( %d n , solve()); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10; const int M = 1e4 + 10; const int MOD = 1e9 + 7; const int inf = 1e9; const double pi = acos(-1.0); const double eps = 1e-6; int dx[] = {0, -1, 0, 1}; int dy[] = {1, 0, -1, 0}; int n, m; int a[101]; int sum[102]; int l, r; int res; int main() { cin >> n >> m; sum[0] = 0; for (int i = 0; i < n; i++) { cin >> a[i]; sum[i + 1] += sum[i] + a[i]; } for (int i = 0; i < m; i++) { cin >> l >> r; int v = sum[r] - sum[l - 1]; if (v > 0) res += v; } cout << res; return 0; } |
#include <bits/stdc++.h> using namespace std; struct IO { char buf[(1 << 20)], *p1, *p2; char pbuf[(1 << 20)], *pp; IO() : p1(buf), p2(buf), pp(pbuf) {} inline char gc() { return getchar(); if (p1 == p2) p2 = (p1 = buf) + fread(buf, 1, (1 << 20), stdin); return p1 == p2 ? : *p1++; } inline bool blank(char ch) { return ch == || ch == n || ch == r || ch == t ; } template <class T> inline void read(T &x) { register double tmp = 1; register bool sign = 0; x = 0; register char ch = gc(); for (; !(ch >= 0 && ch <= 9 ); ch = gc()) if (ch == - ) sign = 1; for (; (ch >= 0 && ch <= 9 ); ch = gc()) x = x * 10 + (ch - 0 ); if (ch == . ) for (ch = gc(); (ch >= 0 && ch <= 9 ); ch = gc()) tmp /= 10.0, x += tmp * (ch - 0 ); if (sign) x = -x; } inline void read(char *s) { register char ch = gc(); for (; blank(ch); ch = gc()) ; for (; !blank(ch); ch = gc()) *s++ = ch; *s = 0; } inline void read(char &c) { for (c = gc(); blank(c); c = gc()) ; } template <class t> inline void write(t x) { if (x < 0) putchar( - ), write(-x); else { if (x > 9) write(x / 10); putchar( 0 + x % 10); } } } io; const int mod = 1e9 + 7; const int mo = 998244353; const int N = 5e5 + 5; int n, m, a[N], b[N], c[N], stak[N], gs, ans; inline int get(int l, int r) { int top = 0; for (int i = (l); i <= (r); i++) { if (a[i] < a[l] || a[i] > a[r]) continue; if (!top || a[i] >= stak[top]) stak[++top] = a[i]; else { int p = upper_bound(stak + 1, stak + top + 1, a[i]) - stak; stak[p] = a[i]; } } return top; } int main() { io.read(n), io.read(m); for (int i = (1); i <= (n); i++) io.read(a[i]), a[i] = a[i] - i + 1; for (int i = (1); i <= (n); i++) b[i] = a[i]; a[++n] = 2e9, b[n] = 2e9; sort(b + 1, b + n + 1); gs = unique(b + 1, b + n + 1) - b - 1; for (int i = (1); i <= (n); i++) a[i] = lower_bound(b + 1, b + gs + 1, a[i]) - b; for (int i = (1); i <= (m); i++) io.read(b[i]); for (int i = (2); i <= (m); i++) if (a[b[i - 1]] > a[b[i]]) ans = -1; if (ans == -1) return puts( -1 ), 0; b[0] = 0, b[m + 1] = n; ans = 0; for (int i = (0); i <= (m); i++) ans += b[i + 1] - b[i] + 1 - get(b[i], b[i + 1]); io.write(ans), puts( ); return 0; } |
// --------------------------------------------------------------------
// Copyright (c) 20057 by Terasic Technologies Inc.
// --------------------------------------------------------------------
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// --------------------------------------------------------------------
//
// Terasic Technologies Inc
// 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
// HsinChu County, Taiwan
// 302
//
// web: http://www.terasic.com/
// email:
//
// --------------------------------------------------------------------
//
// Major Functions: RAW2RGB
//
// --------------------------------------------------------------------
//
// Revision History :
// --------------------------------------------------------------------
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.0 :| Johnny Fan :| 07/08/01 :| Initial Revision
// --------------------------------------------------------------------
module RAW2RGB( oRed,
oGreen,
oBlue,
oDVAL,
iX_Cont,
iY_Cont,
iDATA,
iDVAL,
iCLK,
iRST
);
input [10:0] iX_Cont;
input [10:0] iY_Cont;
input [11:0] iDATA;
input iDVAL;
input iCLK;
input iRST;
output [11:0] oRed;
output [11:0] oGreen;
output [11:0] oBlue;
output oDVAL;
wire [11:0] mDATA_0;
wire [11:0] mDATA_1;
reg [11:0] mDATAd_0;
reg [11:0] mDATAd_1;
reg [11:0] mCCD_R;
reg [12:0] mCCD_G;
reg [11:0] mCCD_B;
reg mDVAL;
assign oRed = mCCD_R[11:0];
assign oGreen = mCCD_G[12:1];
assign oBlue = mCCD_B[11:0];
assign oDVAL = mDVAL;
Line_Buffer1 u0 ( .clken(iDVAL),
.clock(iCLK),
.shiftin(iDATA),
.taps0x(mDATA_1),
.taps1x(mDATA_0) );
always@(posedge iCLK or negedge iRST)
begin
if(!iRST)
begin
mCCD_R <= 0;
mCCD_G <= 0;
mCCD_B <= 0;
mDATAd_0<= 0;
mDATAd_1<= 0;
mDVAL <= 0;
end
else
begin
mDATAd_0 <= mDATA_0;
mDATAd_1 <= mDATA_1;
mDVAL <= {iY_Cont[0]|iX_Cont[0]} ? 1'b0 : iDVAL;
if({iY_Cont[0],iX_Cont[0]}==2'b10)
begin
mCCD_R <= mDATA_0;
mCCD_G <= mDATAd_0+mDATA_1;
mCCD_B <= mDATAd_1;
end
else if({iY_Cont[0],iX_Cont[0]}==2'b11)
begin
mCCD_R <= mDATAd_0;
mCCD_G <= mDATA_0+mDATAd_1;
mCCD_B <= mDATA_1;
end
else if({iY_Cont[0],iX_Cont[0]}==2'b00)
begin
mCCD_R <= mDATA_1;
mCCD_G <= mDATA_0+mDATAd_1;
mCCD_B <= mDATAd_0;
end
else if({iY_Cont[0],iX_Cont[0]}==2'b01)
begin
mCCD_R <= mDATAd_1;
mCCD_G <= mDATAd_0+mDATA_1;
mCCD_B <= mDATA_0;
end
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:03:23 03/21/2014
// Design Name:
// Module Name: LC3_MIO
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module LC3_MIO(
input clk,
input reset,
input [15:0] DATABUS,
input MIO_EN,
input R_W,
input LD_MAR,
input LD_MDR,
input GateMDR,
output [15:0] MDRbus_out,
output KB_INT,
output R,
input LD_char,
input [7:0] I_char,
output [15:0] DDR,
output WR_DDR
);
/*internal wires*/
wire [1:0] INMUX;
wire LD_KBSR;
wire MEM_EN;
wire LD_DSR;
wire LD_DDR;
wire RD_KBDR;
wire [15:0] MEMout;
wire [15:0] KBSR;
wire [15:0] KBDR;
wire [15:0] DSR;
/*MAR*/
reg [15:0] MAR;
wire [15:0] MARin;
assign MARin=DATABUS;
/*Sequential Logic*/
always@(posedge clk) if (LD_MAR)
MAR<=MARin;
/*MDR*/
reg [15:0] MDR;
wire [15:0] MDRin;
reg [15:0] MIOout;
assign MDRin=DATABUS;
always@(posedge clk) if (LD_MDR) begin
if(MIO_EN)
MDR<=MIOout;
else
MDR<=MDRin;
end
/*ADDR CTL LOGIC*/
LC3_MIO_ADDRCTL inst_addrctl(
.clk (clk),
.ADDR (MAR),
.MIO_EN (MIO_EN),
.R_W (R_W),
.INMUX (INMUX),
.MEM_EN (MEM_EN),
.LD_KBSR (LD_KBSR),
.LD_DSR (LD_DSR),
.LD_DDR (LD_DDR),
.RD_KBDR (RD_KBDR),
.R (R)
);
/*MEMORY*/
LC3_MEMORY inst_memory(
.clk (clk),
.ADDR (MAR),
.DATAin (MDR),
.R_W (R_W),
.MEM_EN (MEM_EN),
.MEMout (MEMout)
);
/*INPUT KEYBOARD REG*/
LC3_keyboard_reg inst_keyboard_reg(
.clk (clk),
.reset (reset),
.LD_KBSR (LD_KBSR),
.RD_KBDR (RD_KBDR),
.DATA (MDR),
.I_char (I_char),
.LD_char (LD_char),
.KBDR (KBDR),
.KBSR (KBSR),
.KB_INT (KB_INT)
);
/*OUTPUT SCREEN REG*/
LC3_screen_reg insr_screen_reg(
.clk (clk),
.LD_DDR (LD_DDR),
.LD_DSR (LD_DSR),
.DATA (MDR),
.DSR (DSR),
.DDR (DDR),
.WR_DDR (WR_DDR)
);
/*INMUX LOGIC*/
always@(*) begin
case (INMUX)
2'b00: MIOout=KBSR;
2'b01: MIOout=KBDR;
2'b10: MIOout=DSR;
2'b11: MIOout=MEMout;
endcase
end
/*GATE CONTROL*/
assign MDRbus_out=(GateMDR?MDR:16'bz);
endmodule
|
#include <bits/stdc++.h> const int N = 100000 + 10; int n; std::vector<int> adj[N]; bool flag[N]; void dfs(int a, int fa = -1) { if (adj[a].size() > 2) return; flag[a] = true; for (int i = 0; i < adj[a].size(); ++i) { int b = adj[a][i]; if (b != fa) dfs(b, a); } } int main() { scanf( %d , &n); for (int i = n - 1; i--;) { int a, b; scanf( %d%d , &a, &b); adj[a].push_back(b); adj[b].push_back(a); } for (int i = 1; i <= n; ++i) if (adj[i].size() == 1) dfs(i); static int cnt[N]; for (int i = 1; i <= n; ++i) for (int j = 0; j < adj[i].size(); ++j) cnt[i] += flag[adj[i][j]]; for (int i = 1; i <= n; ++i) { if (flag[i]) continue; int cur = 0; for (int j = 0; j < adj[i].size(); ++j) { int t = adj[i][j]; if (!flag[t] && adj[t].size() - std::min(cnt[t], 2) > 1) ++cur; } if (cur > 2) return puts( No ), 0; } puts( Yes ); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long MAX = 1e9; vector<long long> lucky_nums; void generate_lucky(long long n) { if (n > MAX) return; long long n1 = 10 * n + 4; lucky_nums.push_back(n1); generate_lucky(n1); long long n2 = 10 * n + 7; lucky_nums.push_back(n2); generate_lucky(n2); } void solve() { generate_lucky(0); sort(lucky_nums.begin(), lucky_nums.end()); long long l, r; cin >> l >> r; int i = lower_bound(lucky_nums.begin(), lucky_nums.end(), l) - lucky_nums.begin(); long long prev = l, ans = 0; while (lucky_nums[i] < r) { ans += (lucky_nums[i] - prev + 1) * lucky_nums[i]; prev = lucky_nums[i] + 1; i++; } ans += (r - prev + 1) * lucky_nums[i]; cout << ans << endl; } int main() { solve(); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:25:20 11/19/2015
// Design Name:
// Module Name: MEM_WB
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MEM_WB(
input clock,
input reset,
input debugEnable,
input debugReset,
input [4:0] writeRegister,
input [31:0] aluOut,
input [31:0] memoryOut,
input regWrite,
input memToReg,
input eop,
output reg [4:0] writeRegisterOut,
output reg [31:0] aluOutOut,
output reg [31:0] memoryOutOut,
output reg regWriteOut,
output reg memToRegOut,
output reg eopOut
);
always @(negedge clock,posedge reset)begin
if(reset)begin
writeRegisterOut<=0;
aluOutOut<=0;
memoryOutOut<=0;
regWriteOut<=0;
memToRegOut<=0;
eopOut<=0;
end
else if (debugReset)begin
writeRegisterOut<=0;
aluOutOut<=0;
memoryOutOut<=0;
regWriteOut<=0;
memToRegOut<=0;
eopOut<=0;
end
else if(debugEnable) begin
writeRegisterOut<=writeRegister;
aluOutOut<=aluOut;
memoryOutOut<=memoryOut;
regWriteOut<=regWrite;
memToRegOut<=memToReg;
eopOut<=eop;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAPMET1_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__TAPMET1_BEHAVIORAL_PP_V
/**
* tapmet1: Tap cell with isolated power and ground connections.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hs__tapmet1 (
VGND,
VPWR
);
// Module ports
input VGND;
input VPWR;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAPMET1_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; int const N = 100; int const M = 900; typedef double (*F)[N]; int a[N]; double _f[N][N], _g[N][N]; F f = _f, g = _g; inline int c2(int n) { return n * (n + 1) >> 1; } int main() { int n, k; scanf( %d%d , &n, &k); for (int i = 0; i < n; ++i) scanf( %d , a + i); int n2 = c2(n); for (k = min(k, M); k--;) { for (int i = 0; i < n; ++i) for (int j = i + 1; j < n; ++j) { g[i][j] = (c2(i) + c2(n - 1 - j) + c2(j - i - 1)) * f[i][j]; for (int x = i; x < i + j; ++x) { int a = max(0, x - j + 1), b = min(i, x - i); g[i][j] += (b - a + 1) * f[x - i][j]; } for (int x = i + j + 1; x < n + j; ++x) { int a = max(i + 1, x - n + 1), b = min(j, x - j); g[i][j] += (b - a + 1) * f[i][x - j]; } for (int x = j; x < n + i; ++x) { int a = max(0, x - n + 1), b = min(i, x - j); g[i][j] += (b - a + 1) * (1 - f[x - j][x - i]); } g[i][j] /= n2; } swap(f, g); } double e = 0; for (int i = 0; i < n; ++i) for (int j = i + 1; j < n; ++j) { e += a[i] > a[j] ? 1 - f[i][j] : f[i][j]; } printf( %.16f n , e); return 0; } |
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
*
*(C)2012 Korotkyi Ievgen
* National Technical University of Ukraine "Kiev Polytechnic Institute"
* -------------------------------------------------------------------------------
*
* Tree Matrix Arbiter
*
* - 'multistage' parameter - see description in matrix_arbiter.v
*
* The tree arbiter splits the request vector into groups, performing arbitration
* simultaneously within groups and between groups. Note this has implications
* for fairness.
*
* Only builds one level of a tree
*
*/
module LAG_tree_arbiter (request, grant, success, clk, rst_n);
parameter multistage=0;
parameter max_groupsize=4;
parameter numgroups = 5;
parameter integer links[numgroups][2] = '{'{2,2}, '{2,2}, '{2,2}, '{2,2}, '{2,2} };
parameter priority_support = 0;
input [numgroups*max_groupsize-1:0] request;
output [numgroups*max_groupsize-1:0] grant;
input success;
input clk, rst_n;
logic [numgroups*max_groupsize-1:0] intra_group_grant;
logic [numgroups-1:0] group_grant, any_group_request;
logic [numgroups-1:0] current_group_success, last_group_success;
logic [numgroups-1:0] group_success;
genvar i;
generate
for (i=0; i<numgroups; i=i+1) begin:arbiters
if (multistage==0) begin
//
// group_arbs need to be multistage=1, as group may not get granted
//
matrix_arb #(.size(links[i][IN]),
.multistage(1)) arb
(.request(request[i*max_groupsize+links[i][IN]-1:i*max_groupsize]),
.grant(intra_group_grant[i*max_groupsize+links[i][IN]-1:i*max_groupsize]),
.success(group_success[i]),
.clk, .rst_n);
end else begin
matrix_arb #(.size(links[i][IN]),
.multistage(multistage)) arb
(.request(request[i*max_groupsize+links[i][IN]-1:i*max_groupsize]),
.grant(intra_group_grant[i*max_groupsize+links[i][IN]-1:i*max_groupsize]),
.success(group_success[i] & success),
// .success('1),
.clk, .rst_n);
end
assign any_group_request[i] = |request[i*max_groupsize+links[i][IN]-1:i*max_groupsize];
assign grant[(i+1)*max_groupsize-1:i*max_groupsize]=
intra_group_grant[(i+1)*max_groupsize-1:i*max_groupsize] & {max_groupsize{group_grant[i]}};
//.success(any_group_request[i] & group_grant[i] & success),
//assign current_group_success[i]=|grant[(i+1)*groupsize-1:i*groupsize];
assign current_group_success[i]= group_grant[i];
end
if (multistage==2) begin
always@(posedge clk) begin
if (!rst_n) begin
last_group_success<='0;
end else begin
last_group_success<=current_group_success;
end
end
assign group_success=last_group_success;
end else begin
assign group_success=current_group_success;
end
endgenerate
matrix_arb #(.size(numgroups),
.multistage(multistage)
) group_arb
(.request(any_group_request),
.grant(group_grant),
.success(success),
.clk, .rst_n);
endmodule // tree_arbiter
|
#include <bits/stdc++.h> using namespace std; long long int mod = 1e9 + 7; long long int mxm = 1e18; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int t; cin >> t; while (t--) { long long int n; cin >> n; long long int a[n], i; set<long long int> x; for (i = 0; i < n; i++) { cin >> a[i]; x.insert(i + 1); } sort(a, a + n); for (i = 0; i < n; i++) { if (x.count(a[i])) { x.erase(a[i]); a[i] = 0; } } long long int ans = 0; sort(a, a + n); for (i = 0; i < n; i++) { if (a[i] > 0) { if (2 * (*x.begin()) < a[i]) { x.erase(x.begin()); ans++; } else { ans = -1; break; } } } cout << (ans) << endl; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A2111OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__A2111OI_FUNCTIONAL_PP_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a2111oi (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
// Local signals
wire C1 and0_out ;
wire nor0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , B1, C1, D1, and0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A2111OI_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; string s(200, a ); cout << s << endl; for (int i = 0; i < n; i++) { int u; cin >> u; s[u] = s[u] == a ? b : a ; cout << s << endl; } } } |
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