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#include <bits/stdc++.h> using namespace std; char s[1005]; char t[1000005]; int main() { scanf( %s , s); scanf( %s , t); int len1 = strlen(s); int len2 = strlen(t); int le = 0x3f3f3f3f; int ri = 0x3f3f3f3f; for (int i = 0, j = 0; j < len2; j++) { if (s[i] == t[j]) i++; if (i == len1) { le = j; break; } } for (int i = len1 - 1, j = len2 - 1; j >= 0; j--) { if (s[i] == t[j]) i--; if (i == -1) { ri = j; break; } } if ((le - ri) == (len1 - 1)) cout << 0 << endl; else { int ans = ri - le; cout << ans << endl; } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
module sky130_fd_io__top_xres4v2 ( TIE_WEAK_HI_H, XRES_H_N, TIE_HI_ESD, TIE_LO_ESD,
AMUXBUS_A, AMUXBUS_B, PAD, PAD_A_ESD_H, ENABLE_H, EN_VDDIO_SIG_H, INP_SEL_H, FILT_IN_H,
DISABLE_PULLUP_H, PULLUP_H, ENABLE_VDDIO
,VCCD, VCCHIB, VDDA, VDDIO,VDDIO_Q, VSSA, VSSD, VSSIO, VSSIO_Q, VSWITCH
);
output XRES_H_N;
inout AMUXBUS_A;
inout AMUXBUS_B;
inout PAD;
input DISABLE_PULLUP_H;
input ENABLE_H;
input EN_VDDIO_SIG_H;
input INP_SEL_H;
input FILT_IN_H;
inout PULLUP_H;
input ENABLE_VDDIO;
input VCCD;
input VCCHIB;
input VDDA;
input VDDIO;
input VDDIO_Q;
input VSSA;
input VSSD;
input VSSIO;
input VSSIO_Q;
input VSWITCH;
wire mode_vcchib;
wire pwr_good_xres_tmp = (VDDIO===1) && (VDDIO_Q===1) && ((mode_vcchib && ENABLE_VDDIO)===1 ? VCCHIB===1 : 1'b1) && (VSSIO===0) && (VSSD===0);
wire pwr_good_xres_h_n = (VDDIO_Q===1) && (VSSD===0);
wire pwr_good_pullup = (VDDIO===1) && (VSSD===0);
inout PAD_A_ESD_H;
output TIE_HI_ESD;
output TIE_LO_ESD;
inout TIE_WEAK_HI_H;
wire tmp1;
pullup (pull1) p1 (tmp1); tranif1 x_pull_1 (TIE_WEAK_HI_H, tmp1, pwr_good_pullup===0 ? 1'bx : 1);
tran p2 (PAD, PAD_A_ESD_H);
buf p4 (TIE_HI_ESD, VDDIO);
buf p5 (TIE_LO_ESD, VSSIO);
wire tmp;
pullup (pull1) p3 (tmp); tranif0 x_pull (PULLUP_H, tmp, pwr_good_pullup===0 || ^DISABLE_PULLUP_H===1'bx ? 1'bx : DISABLE_PULLUP_H);
parameter MAX_WARNING_COUNT = 100;
`ifdef SKY130_FD_IO_TOP_XRES4V2_DISABLE_DELAY
parameter MIN_DELAY = 0;
parameter MAX_DELAY = 0;
`else
parameter MIN_DELAY = 50;
parameter MAX_DELAY = 600;
`endif
integer min_delay, max_delay;
initial begin
min_delay = MIN_DELAY;
max_delay = MAX_DELAY;
end
`ifdef SKY130_FD_IO_TOP_XRES4V2_DISABLE_ENABLE_VDDIO_CHANGE_X
parameter DISABLE_ENABLE_VDDIO_CHANGE_X = 1;
`else
parameter DISABLE_ENABLE_VDDIO_CHANGE_X = 0;
`endif
integer disable_enable_vddio_change_x = DISABLE_ENABLE_VDDIO_CHANGE_X;
reg notifier_enable_h;
specify
`ifdef SKY130_FD_IO_TOP_XRES4V2_DISABLE_DELAY
specparam DELAY = 0;
`else
specparam DELAY = 50;
`endif
if (INP_SEL_H==0 & ENABLE_H==0 & ENABLE_VDDIO==0 & EN_VDDIO_SIG_H==1) (PAD => XRES_H_N) = (0:0:0 , 0:0:0);
if (INP_SEL_H==0 & ENABLE_H==1 & ENABLE_VDDIO==1 & EN_VDDIO_SIG_H==1) (PAD => XRES_H_N) = (0:0:0 , 0:0:0);
if (INP_SEL_H==0 & ENABLE_H==1 & ENABLE_VDDIO==1 & EN_VDDIO_SIG_H==0) (PAD => XRES_H_N) = (0:0:0 , 0:0:0);
if (INP_SEL_H==0 & ENABLE_H==0 & ENABLE_VDDIO==0 & EN_VDDIO_SIG_H==0) (PAD => XRES_H_N) = (0:0:0 , 0:0:0);
if (INP_SEL_H==1) (FILT_IN_H => XRES_H_N) = (0:0:0 , 0:0:0);
specparam tsetup = 0;
specparam thold = 5;
$setuphold (posedge ENABLE_VDDIO, posedge ENABLE_H, tsetup, thold, notifier_enable_h);
$setuphold (negedge ENABLE_H, negedge ENABLE_VDDIO, tsetup, thold, notifier_enable_h);
endspecify
reg corrupt_enable;
always @(notifier_enable_h)
begin
corrupt_enable <= 1'bx;
end
initial
begin
corrupt_enable = 1'b0;
end
always @(PAD or ENABLE_H or EN_VDDIO_SIG_H or ENABLE_VDDIO or INP_SEL_H or FILT_IN_H or pwr_good_xres_tmp or DISABLE_PULLUP_H or PULLUP_H or TIE_WEAK_HI_H)
begin
corrupt_enable <= 1'b0;
end
assign mode_vcchib = ENABLE_H && !EN_VDDIO_SIG_H;
wire xres_tmp = (pwr_good_xres_tmp===0 || ^PAD===1'bx || (mode_vcchib===1'bx ) ||(mode_vcchib!==1'b0 && ^ENABLE_VDDIO===1'bx) || (corrupt_enable===1'bx) ||
(mode_vcchib===1'b1 && ENABLE_VDDIO===0 && (disable_enable_vddio_change_x===0)))
? 1'bx : PAD;
wire x_on_xres_h_n = (pwr_good_xres_h_n===0
|| ^INP_SEL_H===1'bx
|| INP_SEL_H===1 && ^FILT_IN_H===1'bx
|| INP_SEL_H===0 && xres_tmp===1'bx);
assign #1 XRES_H_N = x_on_xres_h_n===1 ? 1'bx : (INP_SEL_H===1 ? FILT_IN_H : xres_tmp);
realtime t_pad_current_transition,t_pad_prev_transition;
realtime t_filt_in_h_current_transition,t_filt_in_h_prev_transition;
realtime pad_pulse_width, filt_in_h_pulse_width;
always @(PAD)
begin
if (^PAD !== 1'bx)
begin
t_pad_prev_transition = t_pad_current_transition;
t_pad_current_transition = $realtime;
pad_pulse_width = t_pad_current_transition - t_pad_prev_transition;
end
else
begin
t_pad_prev_transition = 0;
t_pad_current_transition = 0;
pad_pulse_width = 0;
end
end
always @(FILT_IN_H)
begin
if (^FILT_IN_H !== 1'bx)
begin
t_filt_in_h_prev_transition = t_filt_in_h_current_transition;
t_filt_in_h_current_transition = $realtime;
filt_in_h_pulse_width = t_filt_in_h_current_transition - t_filt_in_h_prev_transition;
end
else
begin
t_filt_in_h_prev_transition = 0;
t_filt_in_h_current_transition = 0;
filt_in_h_pulse_width = 0;
end
end
reg dis_err_msgs;
integer msg_count_pad, msg_count_filt_in_h;
event event_errflag_pad_pulse_width, event_errflag_filt_in_h_pulse_width;
initial
begin
dis_err_msgs = 1'b1;
msg_count_pad = 0; msg_count_filt_in_h = 0;
`ifdef SKY130_FD_IO_TOP_XRES4V2_DIS_ERR_MSGS
`else
#1;
dis_err_msgs = 1'b0;
`endif
end
always @(pad_pulse_width)
begin
if (!dis_err_msgs)
begin
if (INP_SEL_H===0 && (pad_pulse_width > min_delay) && (pad_pulse_width < max_delay))
begin
msg_count_pad = msg_count_pad + 1;
->event_errflag_pad_pulse_width;
if (msg_count_pad <= MAX_WARNING_COUNT)
begin
$display(" ===WARNING=== sky130_fd_io__top_xres4v2 : Width of Input pulse for PAD input (= %3.2f ns) is found to be in \the range: %3d ns - %3d ns. In this range, the delay and pulse suppression of the input pulse are PVT dependent. : \%m",pad_pulse_width,min_delay,max_delay,$stime);
end
else
if (msg_count_pad == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_xres4v2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
always @(filt_in_h_pulse_width)
begin
if (!dis_err_msgs)
begin
if (INP_SEL_H===1 && (filt_in_h_pulse_width > min_delay) && (filt_in_h_pulse_width < max_delay))
begin
msg_count_filt_in_h = msg_count_filt_in_h + 1;
->event_errflag_filt_in_h_pulse_width;
if (msg_count_filt_in_h <= MAX_WARNING_COUNT)
begin
$display(" ===WARNING=== sky130_fd_io__top_xres4v2 : Width of Input pulse for FILT_IN_H input (= %3.2f ns) is found to be in \the range: %3d ns - %3d ns. In this range, the delay and pulse suppression of the input pulse are PVT dependent. : \%m",filt_in_h_pulse_width,min_delay,max_delay,$stime);
end
else
if (msg_count_filt_in_h == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_xres4v2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX = 5005; int n; string strs[MAX]; string strp[MAX]; int anspos = 0; int strlens[MAX]; int vis[MAX]; int change[MAX][2]; string ansa, ansb; bool cal(int pos) { int len = strs[pos].size(); strlens[pos] = len; int l = -1, r = len; while (l < len && strs[pos][++l] == strp[pos][l]) ; while (r > 0 && strs[pos][--r] == strp[pos][r]) ; if (l > r) return 1; string cnt = strs[pos].substr(l, r - l + 1); string cnt2 = strp[pos].substr(l, r - l + 1); if (ansa.size() == 0 && ansb.size() == 0) { anspos = pos; ansa = cnt; ansb = cnt2; } if (cnt != ansa || cnt2 != ansb) { return 0; } vis[pos] = 1; change[pos][0] = l, change[pos][1] = r; return 1; } bool myfinds(string &ps) { int nowcntlen = ps.size(); for (int i = 0; i < n; i++) { auto pos = strs[i].find(ps); if (pos != string::npos) { string rester = strs[i].substr(0, pos) + ansb + strs[i].substr(pos + ansb.size()); if (rester != strp[i]) { return 1; } } } return 0; } int addl, addr; string pre; bool check(int len) { addl = 0, addr = 0; while (change[anspos][0] > 0) { int flag = 1; for (int i = 0; i < n; i++) { if (i == anspos) continue; if (!vis[i]) continue; if (change[i][0] > 0 && strs[anspos][change[anspos][0] - 1] == strs[i][change[i][0] - 1]) { change[i][0]--; } else { flag = 0; break; } } if (flag) { change[anspos][0]--; addl++; } else { break; } } while (change[anspos][1] < len - 1) { int flag = 1; for (int i = 0; i < n; i++) { if (i == anspos) continue; if (!vis[i]) continue; if (change[i][1] < strlens[i] - 1 && strs[anspos][change[anspos][1] + 1] == strs[i][change[i][1] + 1]) { change[i][1]++; } else { flag = 0; break; } } if (flag) { change[anspos][1]++; addr++; } else { break; } } } int main() { std::ios::sync_with_stdio(false); cin >> n; ansa.clear(), ansb.clear(); for (int i = 0; i < n; i++) { cin >> strs[i]; } for (int i = 0; i < n; i++) { cin >> strp[i]; } for (int i = 0; i < n; i++) { if (!cal(i)) { cout << NO n ; return 0; } } int nowl = change[anspos][0], nowr = change[anspos][1]; check(strs[anspos].size()); if (addl) { ansa = strs[anspos].substr(nowl - addl, addl) + ansa; ansb = strs[anspos].substr(nowl - addl, addl) + ansb; } if (addr) { ansa += strs[anspos].substr(nowr + 1, addr); ansb += strs[anspos].substr(nowr + 1, addr); } if (myfinds(ansa)) { cout << NO n ; } else { cout << YES n ; cout << ansa << n << ansb << endl; } return 0; } |
// File : ../RTL/slaveController/slaveDirectcontrol.v
// Generated : 11/10/06 05:37:25
// From : ../RTL/slaveController/slaveDirectcontrol.asf
// By : FSM2VHDL ver. 5.0.0.9
//////////////////////////////////////////////////////////////////////
//// ////
//// slaveDirectControl
//// ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/ ////
//// ////
//// Module Description: ////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
//
`include "timescale.v"
`include "usbSerialInterfaceEngine_h.v"
module slaveDirectControl (SCTxPortCntl, SCTxPortData, SCTxPortGnt, SCTxPortRdy, SCTxPortReq, SCTxPortWEn, clk, directControlEn, directControlLineState, rst);
input SCTxPortGnt;
input SCTxPortRdy;
input clk;
input directControlEn;
input [1:0] directControlLineState;
input rst;
output [7:0] SCTxPortCntl;
output [7:0] SCTxPortData;
output SCTxPortReq;
output SCTxPortWEn;
reg [7:0] SCTxPortCntl, next_SCTxPortCntl;
reg [7:0] SCTxPortData, next_SCTxPortData;
wire SCTxPortGnt;
wire SCTxPortRdy;
reg SCTxPortReq, next_SCTxPortReq;
reg SCTxPortWEn, next_SCTxPortWEn;
wire clk;
wire directControlEn;
wire [1:0] directControlLineState;
wire rst;
// BINARY ENCODED state machine: slvDrctCntl
// State codes definitions:
`define START_SDC 3'b000
`define CHK_DRCT_CNTL 3'b001
`define DRCT_CNTL_WAIT_GNT 3'b010
`define DRCT_CNTL_CHK_LOOP 3'b011
`define DRCT_CNTL_WAIT_RDY 3'b100
`define IDLE_FIN 3'b101
`define IDLE_WAIT_GNT 3'b110
`define IDLE_WAIT_RDY 3'b111
reg [2:0] CurrState_slvDrctCntl;
reg [2:0] NextState_slvDrctCntl;
// Diagram actions (continuous assignments allowed only: assign ...)
// diagram ACTION
//--------------------------------------------------------------------
// Machine: slvDrctCntl
//--------------------------------------------------------------------
//----------------------------------
// Next State Logic (combinatorial)
//----------------------------------
always @ (directControlLineState or directControlEn or SCTxPortGnt or SCTxPortRdy or SCTxPortReq or SCTxPortWEn or SCTxPortData or SCTxPortCntl or CurrState_slvDrctCntl)
begin : slvDrctCntl_NextState
NextState_slvDrctCntl <= CurrState_slvDrctCntl;
// Set default values for outputs and signals
next_SCTxPortReq <= SCTxPortReq;
next_SCTxPortWEn <= SCTxPortWEn;
next_SCTxPortData <= SCTxPortData;
next_SCTxPortCntl <= SCTxPortCntl;
case (CurrState_slvDrctCntl)
`START_SDC:
NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
`CHK_DRCT_CNTL:
if (directControlEn == 1'b1)
begin
NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_GNT;
next_SCTxPortReq <= 1'b1;
end
else
begin
NextState_slvDrctCntl <= `IDLE_WAIT_GNT;
next_SCTxPortReq <= 1'b1;
end
`DRCT_CNTL_WAIT_GNT:
if (SCTxPortGnt == 1'b1)
NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY;
`DRCT_CNTL_CHK_LOOP:
begin
next_SCTxPortWEn <= 1'b0;
if (directControlEn == 1'b0)
begin
NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
next_SCTxPortReq <= 1'b0;
end
else
NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY;
end
`DRCT_CNTL_WAIT_RDY:
if (SCTxPortRdy == 1'b1)
begin
NextState_slvDrctCntl <= `DRCT_CNTL_CHK_LOOP;
next_SCTxPortWEn <= 1'b1;
next_SCTxPortData <= {6'b000000, directControlLineState};
next_SCTxPortCntl <= `TX_DIRECT_CONTROL;
end
`IDLE_FIN:
begin
next_SCTxPortWEn <= 1'b0;
next_SCTxPortReq <= 1'b0;
NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
end
`IDLE_WAIT_GNT:
if (SCTxPortGnt == 1'b1)
NextState_slvDrctCntl <= `IDLE_WAIT_RDY;
`IDLE_WAIT_RDY:
if (SCTxPortRdy == 1'b1)
begin
NextState_slvDrctCntl <= `IDLE_FIN;
next_SCTxPortWEn <= 1'b1;
next_SCTxPortData <= 8'h00;
next_SCTxPortCntl <= `TX_IDLE;
end
endcase
end
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : slvDrctCntl_CurrentState
if (rst)
CurrState_slvDrctCntl <= `START_SDC;
else
CurrState_slvDrctCntl <= NextState_slvDrctCntl;
end
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : slvDrctCntl_RegOutput
if (rst)
begin
SCTxPortCntl <= 8'h00;
SCTxPortData <= 8'h00;
SCTxPortWEn <= 1'b0;
SCTxPortReq <= 1'b0;
end
else
begin
SCTxPortCntl <= next_SCTxPortCntl;
SCTxPortData <= next_SCTxPortData;
SCTxPortWEn <= next_SCTxPortWEn;
SCTxPortReq <= next_SCTxPortReq;
end
end
endmodule |
#include <bits/stdc++.h> using namespace std; template <class T> bool ckmin(T& a, const T& b) { return b < a ? a = b, 1 : 0; } template <class T> bool ckmax(T& a, const T& b) { return a < b ? a = b, 1 : 0; } const long long MOD = (long long)(1e9) + 7; long long getVal(pair<pair<int, int>, long long> p) { return (p.second * (p.first.second - p.first.first + 1)) % MOD; } void pr(stack<pair<pair<int, int>, long long>> st) { cout << st.top().first.first << << st.top().first.second << << st.top().second << n ; st.pop(); if (!st.empty()) pr(st); } int main() { ios::sync_with_stdio(0); cin.tie(0); string second; cin >> second; vector<int> v; int cur = 0; for (int i = 0; i < (int)second.size(); i++) { if (second[i] == 1 ) { v.push_back(cur); cur = 0; } else { cur++; } } if ((int)v.size() == 0) { return cout << (int)second.size() << n , 0; ; } long long factor = ((long long)(v[0] + 1) * (cur + 1)) % MOD; v.erase(v.begin()); stack<pair<pair<int, int>, long long>> st; long long cursum = 0; for (int i = 0; i < (int)v.size(); i++) { long long ori = cursum; while (!st.empty()) { if (v[i] >= st.top().first.first) { cursum -= getVal(st.top()); cursum %= MOD; cursum += MOD; cursum %= MOD; if (v[i] < st.top().first.second) { st.top().first.first = v[i] + 1; cursum += getVal(st.top()); cursum %= MOD; break; } else { st.pop(); } } else { break; } } st.push(make_pair(make_pair(0, v[i]), (ori + 1) % MOD)); cursum += getVal(st.top()); cursum %= MOD; } cursum++; cursum %= MOD; long long res = (factor * cursum) % MOD; return cout << res << n , 0; ; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t; cin >> t; bool flag; while (t--) { int n; cin >> n; long long int a[n]; for (int i = 0; i < n; i++) cin >> a[i]; flag = true; sort(a, a + n); long long int k = a[0] * a[n - 1], tmp; for (int i = 0; i < n; i++) { tmp = a[i] * a[n - 1 - i]; if (tmp != k) flag = false; } int ptr = 0; if (flag) { for (int i = 2; i <= sqrt(k); i++) { if (k % i == 0) { if (a[ptr] == i) ptr++; else { flag = false; break; } } } } if (flag) cout << k << endl; else cout << -1 << endl; } } |
#include <bits/stdc++.h> int main() { int a[5], maxx = -1, k; for (int i = 0; i < 4; i++) { scanf( %d , &a[i]); if (maxx < a[i]) { maxx = a[i]; k = i; } } for (int i = 0; i < 4; i++) { if (k == i) continue; printf( %d , maxx - a[i]); } printf( n ); } |
#include <bits/stdc++.h> using namespace std; long long gcd(long long u, long long v) { if (u < v) swap(u, v); while (v != 0) { int r = u % v; u = v; v = r; } return u; } pair<int, int> row[200000], col[200000]; int main(void) { int n, m, k; cin >> n >> m >> k; for (int i = 0; i < 200000; ++i) { row[i] = make_pair(0, -1); col[i] = make_pair(0, -1); } int t = 0; for (int i = 0; i < k; ++i) { t++; int q; cin >> q; if (q == 1) { int r, a; cin >> r >> a; r--; row[r] = make_pair(a, t); } else if (q == 2) { int c, a; cin >> c >> a; c--; col[c] = make_pair(a, t); } } for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { if (row[i].second > col[j].second) cout << row[i].first; else cout << col[j].first; if (j != m - 1) cout << ; } cout << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_IO__TOP_SIO_SYMBOL_V
`define SKY130_FD_IO__TOP_SIO_SYMBOL_V
/**
* top_sio: Special I/O PAD that provides additionally a
* regulated output buffer and a differential input buffer.
* SIO cells are ONLY available IN pairs (see top_sio_macro).
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_io__top_sio (
//# {{data|Data Signals}}
input SLOW ,
output IN ,
input INP_DIS ,
output IN_H ,
input OUT ,
inout PAD ,
inout PAD_A_ESD_0_H,
inout PAD_A_ESD_1_H,
inout PAD_A_NOESD_H,
//# {{control|Control Signals}}
input [2:0] DM ,
input ENABLE_H ,
input HLD_H_N ,
input HLD_OVR ,
input IBUF_SEL ,
input OE_N ,
//# {{power|Power}}
input VREG_EN ,
input VTRIP_SEL ,
input REFLEAK_BIAS ,
input VINREF ,
input VOUTREF ,
output TIE_LO_ESD
);
// Voltage supply signals
supply0 VSSIO ;
supply0 VSSIO_Q;
supply0 VSSD ;
supply1 VCCD ;
supply1 VDDIO ;
supply1 VCCHIB ;
supply1 VDDIO_Q;
endmodule
`default_nettype wire
`endif // SKY130_FD_IO__TOP_SIO_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR3B_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__NOR3B_PP_BLACKBOX_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nor3b (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR3B_PP_BLACKBOX_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2014 by Wilson Snyder.
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=\"%s\" exp=\"%s\"\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [4*8:1] vstr;
const string s = "a"; // Check static assignment
string s2;
string s3;
reg eq;
// Operators == != < <= > >= {a,b} {a{b}} a[b]
// a.len, a.putc, a.getc, a.toupper, a.tolower, a.compare, a.icompare, a.substr
// a.atoi, a.atohex, a.atooct, a.atobin, a.atoreal,
// a.itoa, a.hextoa, a.octoa, a.bintoa, a.realtoa
initial begin
$sformat(vstr, "s=%s", s);
`checks(vstr, "s=a");
`checks(s, "a");
`checks({s,s,s}, "aaa");
`checks({4{s}}, "aaaa");
// Constification
`checkh(s == "a", 1'b1);
`checkh(s == "b", 1'b0);
`checkh(s != "a", 1'b0);
`checkh(s != "b", 1'b1);
`checkh(s > " ", 1'b1);
`checkh(s > "a", 1'b0);
`checkh(s >= "a", 1'b1);
`checkh(s >= "b", 1'b0);
`checkh(s < "a", 1'b0);
`checkh(s < "b", 1'b1);
`checkh(s <= " ", 1'b0);
`checkh(s <= "a", 1'b1);
end
// Test loop
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
s2 = "c0";
end
else if (cyc==1) begin
$sformat(vstr, "s2%s", s2);
`checks(vstr, "s2c0");
end
else if (cyc==2) begin
s3 = s2;
$sformat(vstr, "s2%s", s3);
`checks(vstr, "s2c0");
end
else if (cyc==3) begin
s2 = "a";
s3 = "b";
end
else if (cyc==4) begin
`checks({s2,s3}, "ab");
`checks({3{s3}}, "bbb");
`checkh(s == "a", 1'b1);
`checkh(s == "b", 1'b0);
`checkh(s != "a", 1'b0);
`checkh(s != "b", 1'b1);
`checkh(s > " ", 1'b1);
`checkh(s > "a", 1'b0);
`checkh(s >= "a", 1'b1);
`checkh(s >= "b", 1'b0);
`checkh(s < "a", 1'b0);
`checkh(s < "b", 1'b1);
`checkh(s <= " ", 1'b0);
`checkh(s <= "a", 1'b1);
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; char a[10005]; char b[1000005]; vector<int> poj[10005]; int alen, blen; long long total; int pos; vector<int>::iterator it; int main() { scanf( %s , a); scanf( %s , b); alen = strlen(a), blen = strlen(b); pos = 0; total = 1; for (int i = 0; i <= alen - 1; i++) { poj[a[i] - a ].push_back(i); } for (int i = 0; i <= 25; i++) { sort(poj[i].begin(), poj[i].end()); } for (int i = 0; i <= blen - 1; i++) { if (poj[b[i] - a ].empty()) { printf( -1 n ); return 0; } it = lower_bound(poj[b[i] - a ].begin(), poj[b[i] - a ].end(), pos); if (it == poj[b[i] - a ].end()) { it = poj[b[i] - a ].begin(); total++; } pos = (*it) + 1; } printf( %d n , total); return 0; } |
#include <bits/stdc++.h> using namespace std; const double PI = 4 * atan(1); int T, N; long long X[100013], Y[100013], Z[100013]; long long xmi, xma, ymi, yma, zmi, zma, smi, sma; long long ansx, ansy, ansz; inline bool is(long long x, int p) { return (((x % 2) + 2) % 2) == p; } bool go(long long d) { xmi = -8.1e18, xma = 8.1e18, ymi = -8.1e18, yma = 8.1e18, zmi = -8.1e18, zma = 8.1e18, smi = -8.1e18, sma = 8.1e18; for (int i = 0; i < N; i++) { xmi = max(xmi, Y[i] + Z[i] - X[i] - d); xma = min(xma, Y[i] + Z[i] - X[i] + d); ymi = max(ymi, -Y[i] + Z[i] + X[i] - d); yma = min(yma, -Y[i] + Z[i] + X[i] + d); zmi = max(zmi, Y[i] - Z[i] + X[i] - d); zma = min(zma, Y[i] - Z[i] + X[i] + d); smi = max(smi, Y[i] + Z[i] + X[i] - d); sma = min(sma, Y[i] + Z[i] + X[i] + d); } if (smi > sma || xmi > xma || ymi > yma || zmi > zma) return false; for (int p = 0; p < 2; p++) { if (smi == sma && is(smi, !p) || xmi == xma && is(xmi, !p) || ymi == yma && is(ymi, !p) || zmi == zma && is(zmi, !p)) continue; long long qmi = 0; qmi += (is(xmi, p) ? xmi : xmi + 1); qmi += (is(ymi, p) ? ymi : ymi + 1); qmi += (is(zmi, p) ? zmi : zmi + 1); long long qma = 0; qma += (is(xma, p) ? xma : xma - 1); qma += (is(yma, p) ? yma : yma - 1); qma += (is(zma, p) ? zma : zma - 1); if (qmi <= qma && qmi <= sma && qma >= smi) { if (qmi >= smi) { ansx = (is(xmi, p) ? xmi : xmi + 1); ansy = (is(ymi, p) ? ymi : ymi + 1); ansz = (is(zmi, p) ? zmi : zmi + 1); } else if (qma <= sma) { ansx = (is(xma, p) ? xma : xma - 1); ansy = (is(yma, p) ? yma : yma - 1); ansz = (is(zma, p) ? zma : zma - 1); } else { xmi += is(xmi, !p); xma -= is(xma, !p); ymi += is(ymi, !p); yma -= is(yma, !p); zmi += is(zmi, !p); zma -= is(zma, !p); smi += is(smi, !p); sma -= is(sma, !p); if (xma + ymi + zmi < smi) { if (xma + yma + zmi < smi) { ansx = xma; ansy = yma; ansz = smi - ansx - ansy; } else { ansx = xma; ansz = zmi; ansy = smi - ansx - ansz; } } else { ansy = ymi; ansz = zmi; ansx = smi - ymi - zmi; } } return true; } } return false; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> T; while (T--) { cin >> N; for (int i = 0; i < N; i++) { cin >> X[i] >> Y[i] >> Z[i]; } long long lo = 0; long long hi = 3.1e18; while (lo != hi) { long long mid = (lo + hi) / 2; if (go(mid)) { hi = mid; } else { lo = mid + 1; } } go(lo); cout << (ansy + ansz) / 2 << << (ansx + ansz) / 2 << << (ansx + ansy) / 2 << n ; } cout.flush(); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFRBP_SYMBOL_V
`define SKY130_FD_SC_HD__DFRBP_SYMBOL_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dfrbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFRBP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O211AI_4_V
`define SKY130_FD_SC_HD__O211AI_4_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog wrapper for o211ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o211ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o211ai_4 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o211ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o211ai_4 (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o211ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O211AI_4_V
|
#include<bits/stdc++.h> #define rb(a,b,c) for(int a=b;a<=c;++a) #define rl(a,b,c) for(int a=b;a>=c;--a) #define LL long long #define IT iterator #define PB push_back #define II(a,b) make_pair(a,b) #define FIR first #define SEC second #define FREO freopen( check.out , w ,stdout) #define rep(a,b) for(int a=0;a<b;++a) #define SRAND mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()) #define random(a) rng()%a #define ALL(a) a.begin(),a.end() #define POB pop_back #define ff fflush(stdout) #define fastio ios::sync_with_stdio(false) #define check_min(a,b) a=min(a,b) #define check_max(a,b) a=max(a,b) using namespace std; //inline int read(){ // int x=0; // char ch=getchar(); // while(ch< 0 ||ch> 9 ){ // ch=getchar(); // } // while(ch>= 0 &&ch<= 9 ){ // x=(x<<1)+(x<<3)+(ch^48); // ch=getchar(); // } // return x; //} const int INF=0x3f3f3f3f; typedef pair<int,int> mp; /*} */ const int MAXN=505; int t,n,a[MAXN<<1][MAXN]; bool era[MAXN<<1],cho[MAXN<<1]; int cnt[MAXN][MAXN]; int fa[MAXN<<1]; int root(int x){ return fa[x]=(x==fa[x]? x:root(fa[x])); } vector<int> g[MAXN<<1]; bool col[MAXN<<1]; bool vis[MAXN<<1]; void dfs(int now){ vis[now]=1; for(auto it:g[now]){ if(!vis[it]){ col[it]=col[now]^1; dfs(it); } } } void solve(){ scanf( %d ,&n); rb(i,1,n*2) rb(j,1,n) scanf( %d ,&a[i][j]); memset(era,0,sizeof(era)); memset(vis,0,sizeof(vis)); memset(cho,0,sizeof(cho)); memset(cnt,0,sizeof(cnt)); memset(col,0,sizeof(col)); rb(i,1,n*2) rb(j,1,n) cnt[j][a[i][j]]++; rb(T,1,n){ mp Tmp=II(-1,-1); rb(j,1,n){ rb(k,1,n) if(cnt[j][k]==1){ Tmp=II(j,k); break; } if(Tmp.FIR!=-1) break; } if(Tmp.FIR==-1) break; int x; rb(j,1,2*n){ if(!era[j]&&a[j][Tmp.FIR]==Tmp.SEC){ x=j; break; } } cho[x]=1; rb(j,1,2*n) if(!era[j]&&j!=x){ rb(k,1,n) if(j!=x&&a[j][k]==a[x][k]) era[j]=1; if(era[j]){ rb(k,1,n) cnt[k][a[j][k]]--; } } rb(k,1,n) cnt[k][a[x][k]]--; } rb(i,1,n*2) g[i].clear(),fa[i]=i; rb(i,1,n*2) era[i]|=cho[i]; rb(i,1,n*2) if(!era[i]) rb(j,i+1,n*2) if(!era[j]) { bool E=0; rb(k,1,n) if(a[i][k]==a[j][k]){ E=1; break; } if(E){ g[i].PB(j); g[j].PB(i); fa[root(i)]=root(j); } } rb(i,1,n*2) if(!era[i]&&!vis[i]) dfs(i); int ans=1; vector<int> res; rb(i,1,n*2){ if(!era[i]&&col[i]==0){ res.PB(i); } } rb(i,1,n*2) if(!era[i]&&root(i)==i) ans=(ans+ans)%998244353; rb(i,1,2*n) if(cho[i]) res.PB(i); printf( %d n ,ans); for(auto it:res){ printf( %d ,it); } puts( ); } int main(){ scanf( %d ,&t); while(t--) solve(); return 0; } |
module SortX8 # (
parameter DSIZE = 18,
parameter OFFSET = 8
)(
input [DSIZE-1:0] a0,
input [DSIZE-1:0] a1,
input [DSIZE-1:0] a2,
input [DSIZE-1:0] a3,
input [DSIZE-1:0] a4,
input [DSIZE-1:0] a5,
input [DSIZE-1:0] a6,
input [DSIZE-1:0] a7,
output wire [DSIZE-1:0] sort0,
output wire [DSIZE-1:0] sort1,
output wire [DSIZE-1:0] sort2,
output wire [DSIZE-1:0] sort3,
output wire [DSIZE-1:0] sort4,
output wire [DSIZE-1:0] sort5,
output wire [DSIZE-1:0] sort6,
output wire [DSIZE-1:0] sort7
);
wire [DSIZE-1:0] sortx4_0_0;
wire [DSIZE-1:0] sortx4_0_1;
wire [DSIZE-1:0] sortx4_0_2;
wire [DSIZE-1:0] sortx4_0_3;
wire [DSIZE-1:0] sortx4_1_0;
wire [DSIZE-1:0] sortx4_1_1;
wire [DSIZE-1:0] sortx4_1_2;
wire [DSIZE-1:0] sortx4_1_3;
wire [DSIZE-1:0] sort0_0;
wire [DSIZE-1:0] sort0_1;
wire [DSIZE-1:0] sort1_0;
wire [DSIZE-1:0] sort1_1;
wire [DSIZE-1:0] sort2_0;
wire [DSIZE-1:0] sort2_1;
wire [DSIZE-1:0] sort3_0;
wire [DSIZE-1:0] sort3_1;
// divide sort
SortX4 # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sortx4_inst0 (
.a0 (a0),
.a1 (a1),
.a2 (a2),
.a3 (a3),
.sort0 (sortx4_0_0),
.sort1 (sortx4_0_1),
.sort2 (sortx4_0_2),
.sort3 (sortx4_0_3)
);
SortX4 # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sortx4_inst1 (
.a0 (a4),
.a1 (a5),
.a2 (a6),
.a3 (a7),
.sort0 (sortx4_1_0),
.sort1 (sortx4_1_1),
.sort2 (sortx4_1_2),
.sort3 (sortx4_1_3)
);
// merge
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst0 (
.a(sortx4_0_0),
.b(sortx4_1_3),
.sort0(sort0_0),
.sort1(sort0_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst1 (
.a(sortx4_0_1),
.b(sortx4_1_2),
.sort0(sort1_0),
.sort1(sort1_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst2 (
.a(sortx4_0_2),
.b(sortx4_1_1),
.sort0(sort2_0),
.sort1(sort2_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst3 (
.a(sortx4_0_3),
.b(sortx4_1_0),
.sort0(sort3_0),
.sort1(sort3_1)
);
// bitonic
BitonicSortX4 # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) bitonicsortx4_inst0 (
.a0 (sort0_0),
.a1 (sort1_0),
.a2 (sort2_0),
.a3 (sort3_0),
.sort0 (sort0),
.sort1 (sort1),
.sort2 (sort2),
.sort3 (sort3)
);
BitonicSortX4 # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) bitonicsortx4_inst1 (
.a0 (sort3_1),
.a1 (sort2_1),
.a2 (sort1_1),
.a3 (sort0_1),
.sort0 (sort4),
.sort1 (sort5),
.sort2 (sort6),
.sort3 (sort7)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); int main() { int n; cin >> n; cout << n / 2 - 2; return 0; } |
// Top module connecting all the other modules
//`include "verilog/mips_instr_defines.v"
module top
(
input wire clk,
input wire reset
);
wire[31:0] instr_top;
wire wr_en_imem_top;
wire[31:0] curr_pc_top;
wire[31:0] next_pc_top;
wire[31:0] next_seq_pc_top;
wire[31:0] next_beq_pc_top;
wire next_seq_pc_carry_top;
wire next_beq_pc_carry_top;
wire[31:0] next_brn_eq_pc_top;
wire[31:0] next_jmp_pc_top;
wire[31:0] wr_instr_imem_top;
wire[4:0] rt_top;
wire[4:0] rs_top;
wire[4:0] rd_top;
wire[4:0] rs_dec_top;
wire[4:0] rd_dec_top;
wire[5:0] op_top;
wire[5:0] funct_top;
wire[4:0] shamt_top;
wire[25:0] target_top;
wire[31:0] sign_imm_top;
wire is_r_type_top;
wire is_i_type_top;
wire is_j_type_top;
wire use_link_reg_top;
wire reg_src_top;
wire reg_dst_top;
wire jump_top;
wire branch_top;
wire mem_read_top;
wire mem_to_reg_top;
wire[5:0] alu_op_top;
wire mem_wr_top;
wire[2:0] alu_src_top;
wire reg_wr_top;
wire sign_ext_top;
wire[31:0] r_data_p1_top;
wire[31:0] r_data_p2_top;
wire[31:0] r_data_p2_rf_top;
wire[31:0] res_alu_top;
wire z_top;
wire n_top;
wire v_pc_top;
wire v_branch_top;
wire[31:0] read_data_dmem_ram_top;
wire[31:0] wr_data_rf_top;
pc_reg PC (
.clk (clk),
.reset (reset),
.next_pc_pc_reg_i (next_pc_top),
.next_pc_pc_reg_o (curr_pc_top)
);
adder ADD1 (
.op1 (curr_pc_top),
.op2 (32'h4),
.cin (1'b0),
.sum (next_seq_pc_top),
.carry (next_seq_pc_carry_top),
.v_flag (v_pc_top)
);
adder ADD2 (
.op1 (next_seq_pc_top),
.op2 (sign_imm_top << 2),
.cin (1'b0),
.sum (next_beq_pc_top),
.carry (next_beq_pc_carry_top),
.v_flag (v_branch_top)
);
assign next_brn_eq_pc_top = (branch_top & ((op_top == `BEQ)) & z_top) |
(branch_top & ((op_top == `BVAR) & ((rt_top == `BGEZ)|
(rt_top == `BGEZAL))) & (~n_top | z_top)) |
(branch_top & ((op_top == `BLEZ)) & (n_top | z_top)) |
(branch_top & ((op_top == `BGTZ)) & ~(n_top | z_top)) |
(branch_top & ((op_top == `BVAR) & ((rt_top == `BLTZ) |
(rt_top == `BLTZAL))) & (n_top & ~z_top))|
(branch_top & ((op_top == `BNE)) & ~z_top) ? next_beq_pc_top : next_seq_pc_top;
assign next_jmp_pc_top = {next_seq_pc_top[31:28], instr_top[25:0] << 2};
assign next_pc_top = jump_top ? next_jmp_pc_top : next_brn_eq_pc_top;
instr_mem I_MEM1 (
.clk (clk),
.addr_imem_ram_i (curr_pc_top),
.wr_instr_imem_ram_i (wr_instr_imem_top),
.wr_en_imem_ram_i (wr_en_imem_top),
.read_instr_imem_ram_o (instr_top)
);
decode D1 (
.instr_dec_i (instr_top),
.sign_ext_i (sign_ext_top),
.rt_dec_o (rt_top),
.rs_dec_o (rs_dec_top),
.rd_dec_o (rd_dec_top),
.op_dec_o (op_top),
.funct_dec_o (funct_top),
.shamt_dec_o (shamt_top),
.target_dec_o (target_top),
.sign_imm_dec_o (sign_imm_top),
.is_r_type_dec_o (is_r_type_top),
.is_i_type_dec_o (is_i_type_top),
.is_j_type_dec_o (is_j_type_top),
.use_link_reg_dec_o (use_link_reg_top)
);
assign rd_top = (use_link_reg_top) ? 5'h1F :
(reg_dst_top ? rd_dec_top : rt_top);
assign rs_top = reg_src_top ? rt_top : rs_dec_top;
regfile R1 (
.clk (clk),
.reset (reset),
.w_en_rf_i (reg_wr_top | use_link_reg_top),
.w_data_rf_i (wr_data_rf_top),
.w_reg_rf_i (rd_top),
.r_reg_p1_rf_i (rs_top),
.r_reg_p2_rf_i (rt_top),
.r_data_p1_rf_o (r_data_p1_top),
.r_data_p2_rf_o (r_data_p2_rf_top)
);
assign r_data_p2_top = alu_src_top[2] ? 32'h0 :
alu_src_top[1] ? {{27{1'b0}}, shamt_top} :
alu_src_top[0] ? sign_imm_top : r_data_p2_rf_top;
alu A1 (
.opr_a_alu_i (r_data_p1_top),
.opr_b_alu_i (r_data_p2_top),
.op_alu_i (alu_op_top),
.res_alu_o (res_alu_top),
.z_alu_o (z_top),
.n_alu_o (n_top)
);
data_mem D_MEM1 (
.clk (clk),
.addr_dmem_ram_i (res_alu_top),
.wr_data_dmem_ram_i (r_data_p2_rf_top),
.wr_strb_dmem_ram_i (4'hF),
.wr_en_dmem_ram_i (mem_wr_top),
.read_data_dmem_ram_o (read_data_dmem_ram_top)
);
assign wr_data_rf_top = (use_link_reg_top) ? (next_seq_pc_top) :
(|rd_top) ? (mem_to_reg_top ? read_data_dmem_ram_top :
res_alu_top) :
32'h0;
control C1 (
.instr_op_ctl_i (op_top),
.instr_funct_ctl_i (funct_top),
.reg_src_ctl_o (reg_src_top),
.reg_dst_ctl_o (reg_dst_top),
.jump_ctl_o (jump_top),
.branch_ctl_o (branch_top),
.mem_read_ctl_o (mem_read_top),
.mem_to_reg_ctl_o (mem_to_reg_top),
.alu_op_ctl_o (alu_op_top),
.mem_wr_ctl_o (mem_wr_top),
.alu_src_ctl_o (alu_src_top),
.reg_wr_ctl_o (reg_wr_top),
.sign_ext_ctl_o (sign_ext_top)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INPUTISO1N_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__INPUTISO1N_BEHAVIORAL_V
/**
* inputiso1n: Input isolation, inverted sleep.
*
* X = (A & SLEEP_B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__inputiso1n (
X ,
A ,
SLEEP_B
);
// Module ports
output X ;
input A ;
input SLEEP_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire SLEEP;
// Name Output Other arguments
not not0 (SLEEP , SLEEP_B );
or or0 (X , A, SLEEP );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INPUTISO1N_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; long long n, i, j, a, b, c, t, cnt; int main() { cin >> a >> b >> c; n = 0; t = 0; cnt = 0; while ((a > 0) || (b > 0) || (c > 0)) { switch (t) { case 0: { if (a > 0) a -= 2; break; } case 1: { if (b > 0) b -= 2; break; } case 2: { if (c > 0) c -= 2; break; } } cnt++; n++; t++; t %= 3; } n--; n += 30; cout << n << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c, d; scanf( %d%d%d%d , &a, &b, &c, &d); if (a < max(c, d) || b < max(c, d)) { printf( -1 n ); } else if (c == 0 && d == 0) { for (int i = 0; i < a; i++) printf( 4 ); for (int i = 0; i < b; i++) printf( 7 ); printf( n ); } else if (c == d) { if (a == b && a == c) { printf( -1 n ); } else if (a == c) { for (int i = 0; i < c; i++) printf( 74 ); for (int i = 0; i < b - c; i++) printf( 7 ); printf( n ); } else if (b == c) { for (int i = 0; i < a - c; i++) printf( 4 ); for (int i = 0; i < c; i++) printf( 74 ); printf( n ); } else { for (int i = 0; i < a - c - 1; i++) printf( 4 ); for (int i = 0; i < c; i++) printf( 47 ); for (int i = 0; i < b - c; i++) printf( 7 ); printf( 4 ); printf( n ); } } else if (c - d == 1) { for (int i = 0; i < a - c; i++) printf( 4 ); for (int i = 0; i < c; i++) printf( 47 ); for (int i = 0; i < b - c; i++) printf( 7 ); printf( n ); } else if (d - c == 1) { printf( 74 ); for (int i = 0; i < a - d; i++) printf( 4 ); for (int i = 0; i < d - 2; i++) printf( 74 ); for (int i = 0; i < b - d; i++) printf( 7 ); printf( 74 ); printf( n ); } else printf( -1 n ); return 0; } |
// Top level which connects all the top-level functional blocks.
// Copyright 2010 University of Washington
// License: http://creativecommons.org/licenses/by/3.0/
// 2008 Dan Yeager
// The controller chooses if and what packet is sent.
// RX converts RFID protocol into a serial data stream
// and provides TRCAL, the tx clock divider calibration
// and the lsb of the counter as a random number stream.
// CMDPARSE and PACKETPARSE decode the serial bit stream
// and help the controller make decisions.
// TX converts a serial bit stream to RFID protocol.
// It is wrapped in a SEQUENCER which provides the proper
// clock to TX and sequences the preamble, DATA and crc in time.
// The controller connects one of 4 DATA sources to the sequencer.
// Options are RNG (random number), EPC (ID), READ (response to READ packet)
// and WRITE (response to WRITE packet).
module top(reset, clk, demodin, modout, // regular IO
adc_sample_ctl, adc_sample_clk, adc_sample_datain, // adc connections
msp_sample_ctl, msp_sample_clk, msp_sample_datain, // msp430 connections
uid_byte_in, uid_addr_out, uid_clk_out,
writedataout, writedataclk,
use_uid, use_q, comm_enable,
debug_clk, debug_out);
// Regular IO
// Oscillator input, master reset, demodulator input
input reset, clk, demodin;
// Modulator output
output modout;
// Functionality control
input use_uid, use_q, comm_enable;
// EPC ID source
input [7:0] uid_byte_in;
output [3:0] uid_addr_out;
output uid_clk_out;
// ADC connections
input adc_sample_datain;
output adc_sample_clk, adc_sample_ctl;
// MSP430 connections
input msp_sample_datain;
output msp_sample_clk, msp_sample_ctl;
output writedataout, writedataclk;
// Debugging IO
input debug_clk;
output debug_out;
// CONTROLLER module connections
wire rx_en, tx_en, docrc;
wire [15:0] currentrn; // current rn
wire [15:0] currenthandle; // current handle
// RX module connections
wire rx_reset, rxtop_reset, bitclk, bitout;
wire rx_overflow;
// PACKET PARSE module connections
wire handlematch;
wire [1:0] readwritebank;
wire [7:0] readwriteptr;
wire [7:0] readwords;
wire writedataout, writedataclk;
wire [3:0] rx_q;
wire [2:0] rx_updn;
// CMDPARSE module connections
wire packet_complete, cmd_complete;
wire [8:0] rx_cmd;
// TX module connections
wire tx_reset, txsetupdone, tx_done;
// TX settings module wires
wire dr_in, dr_out;
wire trext_in, trext_out;
wire [1:0] m_in, m_out;
wire [9:0] trcal_in, trcal_out;
// Signal to tx settings module to store TR modulation settings.
parameter QUERY = 9'b000000100;
wire query_complete;
assign query_complete = packet_complete && (rx_cmd==QUERY);
// RNG connections
wire rngbitin, rngbitinclk;
// Signal to RNG to clock in new bits for query, queryadj, reqrn
assign rngbitinclk = bitclk & (rx_cmd[2] | rx_cmd[3] | (rx_cmd[6] & handlematch));
// TX module connections
wire txbitclk, txbitsrc, txdatadone;
// RX and TX module reset signals
assign tx_reset = reset | !tx_en;
assign rx_reset = reset | !rx_en;
assign rxtop_reset = reset | !rx_en;
// mux control for transmit data source
wire [1:0] bitsrcselect;
parameter BITSRC_RNG = 0;
parameter BITSRC_EPC = 1;
parameter BITSRC_READ = 2;
parameter BITSRC_UID = 3;
// mux the bit source for the tx module
wire [3:0] bitsrc;
wire rngbitsrc, epcbitsrc, readbitsrc, uidbitsrc;
assign bitsrc[0] = rngbitsrc;
assign bitsrc[1] = epcbitsrc;
assign bitsrc[2] = readbitsrc;
assign bitsrc[3] = uidbitsrc;
assign txbitsrc = bitsrc[bitsrcselect];
// mux control for data source done flag
wire [3:0] datadone;
wire rngdatadone, epcdatadone, readdatadone, uiddatadone;
assign datadone[0] = rngdatadone;
assign datadone[1] = epcdatadone;
assign datadone[2] = readdatadone;
assign datadone[3] = uiddatadone;
assign txdatadone = datadone[bitsrcselect];
// mux control for tx data clock
wire rngbitclk, epcbitclk, readbitclk, uidbitclk;
assign rngbitclk = (bitsrcselect == BITSRC_RNG ) ? txbitclk : 1'b0;
assign epcbitclk = (bitsrcselect == BITSRC_EPC ) ? txbitclk : 1'b0;
assign readbitclk = (bitsrcselect == BITSRC_READ) ? txbitclk : 1'b0;
assign uidbitclk = (bitsrcselect == BITSRC_UID ) ? txbitclk : 1'b0;
// MUX connection from READ to MSP or ADC
wire readfrommsp;
wire readfromadc = !readfrommsp;
wire read_sample_ctl, read_sample_clk, read_sample_datain;
// ADC connections
assign adc_sample_ctl = read_sample_ctl & readfromadc;
assign adc_sample_clk = read_sample_clk & readfromadc;
// MSP430 connections
assign msp_sample_ctl = read_sample_ctl & readfrommsp;
assign msp_sample_clk = read_sample_clk & readfrommsp;
assign read_sample_datain = readfromadc ? adc_sample_datain : msp_sample_datain;
// Serial debug interface for viewing registers:
reg [3:0] debug_address;
reg debug_out;
always @ (posedge debug_clk or posedge reset) begin
if(reset) begin
debug_address <= 4'd0;
end else begin
debug_address <= debug_address + 4'd1;
end
end
always @ (debug_address) begin
case(debug_address)
0: debug_out = packet_complete;
1: debug_out = cmd_complete;
2: debug_out = handlematch;
3: debug_out = docrc;
4: debug_out = rx_en;
5: debug_out = tx_en;
6: debug_out = bitout;
7: debug_out = bitclk;
8: debug_out = rngbitin;
9: debug_out = rx_overflow;
10: debug_out = tx_done;
11: debug_out = txsetupdone;
12: debug_out = 1'b0;
13: debug_out = 1'b1;
14: debug_out = 1'b0;
15: debug_out = 1'b1;
default: debug_out = 1'b0;
endcase
end
// MODULES! :)
controller U_CTL (reset, clk, rx_overflow, rx_cmd, currentrn, currenthandle,
packet_complete, txsetupdone, tx_done,
rx_en, tx_en, docrc, handlematch,
bitsrcselect, readfrommsp, readwriteptr, rx_q, rx_updn,
use_uid, use_q, comm_enable);
txsettings U_SET (reset, trcal_in, m_in, dr_in, trext_in, query_complete,
trcal_out, m_out, dr_out, trext_out);
rx U_RX (rx_reset, clk, demodin, bitout, bitclk, rx_overflow, trcal_in, rngbitin);
cmdparser U_CMD (rxtop_reset, bitout, bitclk, rx_cmd, packet_complete, cmd_complete,
m_in, trext_in, dr_in);
packetparse U_PRSE (rx_reset, bitout, bitclk, rx_cmd, rx_q, rx_updn,
currenthandle, currentrn, handlematch,
readwritebank, readwriteptr, readwords,
writedataout, writedataclk );
rng U_RNG (tx_reset, reset, rngbitin, rngbitinclk, rngbitclk, rngbitsrc, rngdatadone, currentrn);
epc U_EPC (tx_reset, epcbitclk, epcbitsrc, epcdatadone);
read U_READ (tx_reset, readbitclk, readbitsrc, readdatadone,
read_sample_ctl, read_sample_clk, read_sample_datain,
currenthandle);
uid U_UID (tx_reset, uidbitclk, uidbitsrc, uiddatadone,
uid_byte_in, uid_addr_out, uid_clk_out);
sequencer U_SEQ (tx_reset, rx_overflow, clk, m_out, dr_out, docrc, trext_out,
trcal_out, txbitsrc, txdatadone, txbitclk, modout, txsetupdone, tx_done);
endmodule
|
#include <bits/stdc++.h> using namespace std; map<string, int> Map; string s[181], sn; int n, i; int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> sn; cin >> n; s[1] = January ; s[2] = February ; s[3] = March ; s[4] = April ; s[5] = May ; s[6] = June ; s[7] = July ; s[8] = August ; s[9] = September ; s[10] = October ; s[11] = November ; s[12] = December ; for (i = 13; i <= 24; i++) s[i] = s[i - 12]; for (i = 1; i <= 12; i++) Map[s[i]] = i; cout << s[Map[sn] + n % 12] << n ; return 0; } |
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.1 (win64) Build Mon Apr 27 19:22:08 MDT 2015
// Date : Sat Mar 19 19:16:24 2016
// Host : DESKTOP-5FTSDRT running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Users/SKL/Desktop/ECE532/repo/decoder_ip_prj/decoder_ip_prj.srcs/sources_1/ip/dcfifo_32in_32out_8kb_cnt/dcfifo_32in_32out_8kb_cnt_stub.v
// Design : dcfifo_32in_32out_8kb_cnt
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v12_0,Vivado 2015.1" *)
module dcfifo_32in_32out_8kb_cnt(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full, empty, rd_data_count)
/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[31:0],wr_en,rd_en,dout[31:0],full,empty,rd_data_count[0:0]" */;
input rst;
input wr_clk;
input rd_clk;
input [31:0]din;
input wr_en;
input rd_en;
output [31:0]dout;
output full;
output empty;
output [0:0]rd_data_count;
endmodule
|
module ControlUnit (output reg IR_CU, RFLOAD, PCLOAD, SRLOAD, SRENABLED, ALUSTORE, MFA, WORD_BYTE,READ_WRITE,IRLOAD,MBRLOAD,MBRSTORE,MARLOAD,output reg[4:0] opcode, output reg[3:0] CU, input MFC, Reset,Clk, input [31:0] IR,input [3:0] SR);
reg [4:0] State, NextState;
task registerTask;
input [17:0] signals;
//6 7 8 12 14 16
fork
//#2 set the alu signals
#2 {CU,IR_CU, RFLOAD, PCLOAD, SRLOAD,opcode, SRENABLED, ALUSTORE, MARLOAD,MBRSTORE,MBRLOAD,IRLOAD,MFA,READ_WRITE, WORD_BYTE} = {signals[17],1'b0,signals[15],1'b0,signals[13],1'b0,signals[11:9],1'b0,1'b0,1'b0,signals[5:0]};
//#4 set the register signals
#4 {CU,IR_CU, RFLOAD, PCLOAD, SRLOAD,opcode, SRENABLED, ALUSTORE, MARLOAD,MBRSTORE,MBRLOAD,IRLOAD,MFA,READ_WRITE, WORD_BYTE} = signals;
//#6 let data be saved
#6 {CU,IR_CU, RFLOAD, PCLOAD, SRLOAD,opcode, SRENABLED, ALUSTORE, MARLOAD,MBRSTORE,MBRLOAD,IRLOAD,MFA,READ_WRITE, WORD_BYTE} = signals;
join
endtask
always @ (negedge Clk, posedge Reset)
if (Reset) begin
State <= 5'b00001; IR_CU= 0 ; RFLOAD= 0 ; PCLOAD= 0 ; SRLOAD= 0 ; SRENABLED= 0 ; MFA= 0 ; WORD_BYTE= 0 ;READ_WRITE= 0 ;IRLOAD= 0 ;MBRLOAD= 0 ;MBRSTORE= 0 ;MARLOAD = 0 ;CU=0;end
else
State <= NextState;
always @ (State, MFC)
case (State)
5'b00000 : NextState = 5'b00000;
5'b00001 : NextState = 5'b00010;
5'b00010 : NextState = 5'b00011;
5'b00011 : NextState = 5'b00100;
5'b00100 : NextState = 5'b00101;
5'b00101 : NextState = 5'b00110;
5'b00110 : NextState = 5'b00111;
5'b00111 : NextState = 5'b01000;
5'b01000 : NextState = 5'b01001;
5'b01001 : NextState = 5'b01010;
5'b01010 : NextState = 5'b01011;
5'b01011 : NextState = 5'b01100;
5'b01100 : NextState = 5'b01101;
5'b01101 : NextState = 5'b01110;
5'b01110 : NextState = 5'b01111;
5'b01111 : NextState = 5'b10000;
5'b10000 : NextState = 5'b10001;
5'b10001 : NextState = 5'b00001;
endcase
always @ (State, MFC)
case (State)
5'b00000 : begin opcode = 0; ALUSTORE = 1 ; end
5'b00001 : begin opcode = 1; ALUSTORE = 1 ; end // send pc to mar: ircu = 1 cu = 1111,MARLOAD = 1
5'b00010 : begin opcode = 2; ALUSTORE = 1 ; end // increment pc : loadpc = 1 ircu = 1 cu = 1111 op = 17
5'b00011 : begin opcode = 3; ALUSTORE = 1 ; end // wait for MFC: MFA = 1 LOADIR = 1 read_write = 1 word_byte = 1
5'b00100 : begin opcode = 4; ALUSTORE = 1 ; end // transfer data to IR
5'b00101 : begin opcode = 5; ALUSTORE = 1 ; end // Check status codes
5'b00110 : begin opcode = 6; ALUSTORE = 1 ; end // Decode instruction type and set out signals
5'b00111 : begin opcode = 7; ALUSTORE = 1 ; end
5'b01000 : begin opcode = 8; ALUSTORE = 1 ; end
5'b01001 : begin opcode = 9; ALUSTORE = 1 ; end
5'b01010 : begin opcode = 10; ALUSTORE = 1 ; end
5'b01011 : begin opcode = 11; ALUSTORE = 1 ; end
5'b01100 : begin opcode = 12; ALUSTORE = 1 ; end
5'b01101 : begin opcode = 13; ALUSTORE = 1 ; end
5'b01110 : begin opcode = 14; ALUSTORE = 1 ; end
5'b01111 : begin opcode = 15; ALUSTORE = 1 ; end
5'b10000 : begin opcode = 16; ALUSTORE = 1 ; end
5'b10001 : begin opcode = 17; ALUSTORE = 1 ; end
/*branch and load_store instruction*/
default : begin end
endcase
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__BUF_TB_V
`define SKY130_FD_SC_HVL__BUF_TB_V
/**
* buf: Buffer.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__buf.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hvl__buf dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__BUF_TB_V
|
#include <bits/stdc++.h> using namespace std; int main() { int num; int arr[110]; cin >> num; for (int i = 0; i < num; i++) { cin >> arr[i]; } for (int i = 1; i <= num; i++) { for (int j = 0; j < num; j++) { if (arr[j] == i) { cout << j + 1 << ; } } } cout << endl; return 0; } |
/* FIX_POINT_FLOAT */
module ADD_FIX_POINT_FLOAT ( A, B, out );
parameter width = 16;
input [width:1] A,B;
output [width:1] out;
assign out = A + B;
endmodule
//-------------------------------------------------
module SUB_FIX_POINT_FLOAT ( A, B, out ) ;
parameter width = 16;
input [width:1] A,B;
output [width:1] out;
assign out = A - B;
endmodule
//-------------------------------------------------
module MUL_FIX_POINT_FLOAT ( A, B, out ) ;
parameter width = 16;
input [width:1] A,B;
output [width:1] out ;
genvar i;
parameter half = width/2;
parameter half_mask = ((1<<(half+1))-1);
parameter top_mask = half_mask << (half);
wire [width:1] A2,B2;
wire [2*width:1] temp;
wire [1:1] flag;
assign flag = A[width] ^ B[width];
assign A2 = A[width] ? -A : A;
assign B2 = B[width] ? -B : B;
assign temp = (
0
+ ( (B2[ 1]) ? A2 << ( 1 - 1 ) : 0 )
+ ( (B2[ 2]) ? A2 << ( 2 - 1 ) : 0 )
+ ( (B2[ 3]) ? A2 << ( 3 - 1 ) : 0 )
+ ( (B2[ 4]) ? A2 << ( 4 - 1 ) : 0 )
+ ( (B2[ 5]) ? A2 << ( 5 - 1 ) : 0 )
+ ( (B2[ 6]) ? A2 << ( 6 - 1 ) : 0 )
+ ( (B2[ 7]) ? A2 << ( 7 - 1 ) : 0 )
+ ( (B2[ 8]) ? A2 << ( 8 - 1 ) : 0 )
+ ( (B2[ 9]) ? A2 << ( 9 - 1 ) : 0 )
+ ( (B2[10]) ? A2 << ( 10 - 1 ) : 0 )
+ ( (B2[11]) ? A2 << ( 11 - 1 ) : 0 )
+ ( (B2[12]) ? A2 << ( 12 - 1 ) : 0 )
+ ( (B2[13]) ? A2 << ( 13 - 1 ) : 0 )
+ ( (B2[14]) ? A2 << ( 14 - 1 ) : 0 )
+ ( (B2[15]) ? A2 << ( 15 - 1 ) : 0 )
+ ( (B2[16]) ? A2 << ( 16 - 1 ) : 0 )
);
assign out = flag[1] ? -temp[width+half+1:half+1] : temp[width+half+1:half+1];
endmodule
//-------------------------------------------------
module DIV_FIX_POINT_FLOAT ( A, B, out ) ;
//include bugs
parameter width = 16;
parameter half = width/2;
input [width:1] A,B;
output [width:1] out;
assign out = (
0
+ ( (B[ 1]) ? A >> ( 1 - 1 - half ) : 0 )
+ ( (B[ 2]) ? A >> ( 2 - 1 - half ) : 0 )
+ ( (B[ 3]) ? A >> ( 3 - 1 - half ) : 0 )
+ ( (B[ 4]) ? A >> ( 4 - 1 - half ) : 0 )
+ ( (B[ 5]) ? A >> ( 5 - 1 - half ) : 0 )
+ ( (B[ 6]) ? A >> ( 6 - 1 - half ) : 0 )
+ ( (B[ 7]) ? A >> ( 7 - 1 - half ) : 0 )
+ ( (B[ 8]) ? A >> ( 8 - 1 - half ) : 0 )
+ ( (B[ 9]) ? A >> ( 9 - 1 - half ) : 0 )
+ ( (B[10]) ? A >> ( 10 - 1 - half ) : 0 )
+ ( (B[11]) ? A >> ( 11 - 1 - half ) : 0 )
+ ( (B[12]) ? A >> ( 12 - 1 - half ) : 0 )
+ ( (B[13]) ? A >> ( 13 - 1 - half ) : 0 )
+ ( (B[14]) ? A >> ( 14 - 1 - half ) : 0 )
+ ( (B[15]) ? A >> ( 15 - 1 - half ) : 0 )
+ ( (B[16]) ? A >> ( 16 - 1 - half ) : 0 )
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLRBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__DLRBP_FUNCTIONAL_PP_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_hd__udp_dlatch_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dlrbp (
Q ,
Q_N ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLRBP_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; int main() { string val; cin >> val; int cngIn1 = -1; int lDigit = int(val[val.length() - 1] - 0 ); for (int i = val.length() - 2; i >= 0; i--) { int dig = int(val[i] - 0 ); if ((dig % 2 == 0) && (dig < lDigit)) { cngIn1 = i; } } string sNewVal1 = val; if (cngIn1 != -1) { sNewVal1[sNewVal1.length() - 1] = val[cngIn1]; sNewVal1[cngIn1] = val[sNewVal1.length() - 1]; } int cngIn2 = -1; for (int i = val.length() - 2; i >= 0; i--) { int dig = int(val[i] - 0 ); if ((dig % 2 == 0) && (dig > lDigit)) { cngIn2 = i; break; } } string sNewVal2 = val; if (cngIn2 != -1) { sNewVal2[sNewVal2.length() - 1] = val[cngIn2]; sNewVal2[cngIn2] = val[sNewVal2.length() - 1]; } if ((sNewVal1 == val) && (sNewVal2 == val)) { cout << -1; } else if (sNewVal1 == val) { cout << sNewVal2; } else if (sNewVal2 == val) { cout << sNewVal1; } else { cout << sNewVal1; } } |
#include <bits/stdc++.h> using namespace std; int main() { int NWarm, NChip; cin >> NWarm >> NChip; int temp = NWarm * (NWarm + 1) / 2; int ans = NChip % temp; int i; for (i = 1; i <= temp; i++) { ans = ans - i; if (ans < 0) break; } int ans1 = ans + i; cout << ans1 << endl; } |
/*
-- ============================================================================
-- FILE NAME : ex_stage.v
-- DESCRIPTION : EXXe[W
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito VKì¬
-- ============================================================================
*/
/********** ¤Êwb_t@C **********/
`include "nettype.h"
`include "global_config.h"
`include "stddef.h"
/********** ÂÊwb_t@C **********/
`include "isa.h"
`include "cpu.h"
/********** W
[ **********/
module ex_stage (
/********** NbN & Zbg **********/
input wire clk, // NbN
input wire reset, // ñ¯úZbg
/********** pCvC§äM **********/
input wire stall, // Xg[
input wire flush, // tbV
input wire int_detect, // èÝo
/********** tH[fBO **********/
output wire [`WordDataBus] fwd_data, // tH[fBOf[^
/********** ID/EXpCvCWX^ **********/
input wire [`WordAddrBus] id_pc, // vOJE^
input wire id_en, // pCvCf[^ÌLø
input wire [`AluOpBus] id_alu_op, // ALUIy[V
input wire [`WordDataBus] id_alu_in_0, // ALUüÍ 0
input wire [`WordDataBus] id_alu_in_1, // ALUüÍ 1
input wire id_br_flag, // ªòtO
input wire [`MemOpBus] id_mem_op, // Iy[V
input wire [`WordDataBus] id_mem_wr_data, // «Ýf[^
input wire [`CtrlOpBus] id_ctrl_op, // §äWX^Iy[V
input wire [`RegAddrBus] id_dst_addr, // ÄpWX^«ÝAhX
input wire id_gpr_we_, // ÄpWX^«ÝLø
input wire [`IsaExpBus] id_exp_code, // áOR[h
/********** EX/MEMpCvCWX^ **********/
output wire [`WordAddrBus] ex_pc, // vOJE^
output wire ex_en, // pCvCf[^ÌLø
output wire ex_br_flag, // ªòtO
output wire [`MemOpBus] ex_mem_op, // Iy[V
output wire [`WordDataBus] ex_mem_wr_data, // «Ýf[^
output wire [`CtrlOpBus] ex_ctrl_op, // §äWX^Iy[V
output wire [`RegAddrBus] ex_dst_addr, // ÄpWX^«ÝAhX
output wire ex_gpr_we_, // ÄpWX^«ÝLø
output wire [`IsaExpBus] ex_exp_code, // áOR[h
output wire [`WordDataBus] ex_out // Ê
);
/********** ALUÌoÍ **********/
wire [`WordDataBus] alu_out; // ZÊ
wire alu_of; // I[ot[
/********** ZÊÌtH[fBO **********/
assign fwd_data = alu_out;
/********** ALU **********/
alu alu (
.in_0 (id_alu_in_0), // üÍ 0
.in_1 (id_alu_in_1), // üÍ 1
.op (id_alu_op), // Iy[V
.out (alu_out), // oÍ
.of (alu_of) // I[ot[
);
/********** pCvCWX^ **********/
ex_reg ex_reg (
/********** NbN & Zbg **********/
.clk (clk), // NbN
.reset (reset), // ñ¯úZbg
/********** ALUÌoÍ **********/
.alu_out (alu_out), // ZÊ
.alu_of (alu_of), // I[ot[
/********** pCvC§äM **********/
.stall (stall), // Xg[
.flush (flush), // tbV
.int_detect (int_detect), // èÝo
/********** ID/EXpCvCWX^ **********/
.id_pc (id_pc), // vOJE^
.id_en (id_en), // pCvCf[^ÌLø
.id_br_flag (id_br_flag), // ªòtO
.id_mem_op (id_mem_op), // Iy[V
.id_mem_wr_data (id_mem_wr_data), // «Ýf[^
.id_ctrl_op (id_ctrl_op), // §äWX^Iy[V
.id_dst_addr (id_dst_addr), // ÄpWX^«ÝAhX
.id_gpr_we_ (id_gpr_we_), // ÄpWX^«ÝLø
.id_exp_code (id_exp_code), // áOR[h
/********** EX/MEMpCvCWX^ **********/
.ex_pc (ex_pc), // vOJE^
.ex_en (ex_en), // pCvCf[^ÌLø
.ex_br_flag (ex_br_flag), // ªòtO
.ex_mem_op (ex_mem_op), // Iy[V
.ex_mem_wr_data (ex_mem_wr_data), // «Ýf[^
.ex_ctrl_op (ex_ctrl_op), // §äWX^Iy[V
.ex_dst_addr (ex_dst_addr), // ÄpWX^«ÝAhX
.ex_gpr_we_ (ex_gpr_we_), // ÄpWX^«ÝLø
.ex_exp_code (ex_exp_code), // áOR[h
.ex_out (ex_out) // Ê
);
endmodule
|
`begin_keywords "1364-2005"
/*
* This tests the synthesis of a case statement that has an empty case.
*/
module main;
reg clk, bit, foo, clr;
// Synchronous device that toggles whenever enabled by a high bit.
always @(posedge clk or posedge clr)
if (clr) foo = 0;
else case (bit)
1'b0: ;
1'b1: foo <= ~foo;
endcase // case(bit)
(* ivl_synthesis_off *)
always begin
#5 clk = 1;
#5 clk = 0;
end
(* ivl_synthesis_off *)
initial begin
clk = 0;
bit = 0;
clr = 1;
# 6 $display("clk=%b, bit=%b, foo=%b", clk, bit, foo);
if (bit !== 0 || foo !== 0) begin
$display("FAILED");
$finish;
end
clr = 0;
#10 $display("clk=%b, bit=%b, foo=%b", clk, bit, foo);
if (bit !== 0 || foo !== 0) begin
$display("FAILED");
$finish;
end
bit <= 1;
#10 $display("clk=%b, bit=%b, foo=%b", clk, bit, foo);
if (bit !== 1 || foo !== 1) begin
$display("FAILED");
$finish;
end
#10 $display("clk=%b, bit=%b, foo=%b", clk, bit, foo);
if (bit !== 1 || foo !== 0) begin
$display("FAILED");
$finish;
end
$display("PASSED");
$finish;
end
endmodule // main
`end_keywords
|
module test;
// force leading zero on outer scope genblk numbers
localparam genblk1 = 0;
localparam genblk2 = 0;
localparam genblk3 = 0;
localparam genblk4 = 0;
localparam genblk5 = 0;
localparam genblk6 = 0;
localparam genblk7 = 0;
localparam genblk8 = 0;
localparam genblk9 = 0;
parameter TRUE = 1;
genvar i;
genvar j;
for (i = 0; i < 2; i = i + 1) begin
reg r1 = 1;
end
for (i = 0; i < 2; i = i + 1) begin
for (j = 0; j < 2; j = j + 1) begin
reg r2 = 1;
end
end
for (i = 0; i < 2; i = i + 1) begin
case (TRUE)
0: begin
reg r3a = 1;
end
1: begin
reg r3b = 1;
end
endcase
end
for (i = 0; i < 2; i = i + 1) begin
if (TRUE)
begin
reg r4a = 1;
end
else
begin
reg r4b = 1;
end
end
for (i = 0; i < 2; i = i + 1) begin
if (!TRUE)
begin
reg r5a = 1;
end
else
begin
if (TRUE)
begin
reg r5b = 1;
end
else
begin
reg r5c = 1;
end
end
end
for (i = 0; i < 2; i = i + 1) begin
if (!TRUE)
begin
reg r6a = 1;
end
else
begin
if (!TRUE)
begin
reg r6b = 1;
end
else
begin
reg r6c = 1;
end
end
end
case (TRUE)
0: begin
reg r7a = 1;
end
1: begin
reg r7b = 1;
end
endcase
case (TRUE)
0: begin
case (TRUE)
0: begin
reg r8a = 1;
end
1: begin
reg r8b = 1;
end
endcase
end
1: begin
case (TRUE)
0: begin
reg r8c = 1;
end
1: begin
reg r8d = 1;
end
endcase
end
endcase
case (TRUE)
0: begin
if (TRUE)
begin
reg r9a = 1;
end
else
begin
reg r9b = 1;
end
end
1: begin
if (TRUE)
begin
reg r9c = 1;
end
else
begin
reg r9d = 1;
end
end
endcase
case (TRUE)
0: begin
if (!TRUE)
begin
reg r10a = 1;
end
else
begin
if (TRUE)
begin
reg r10b = 1;
end
else
begin
reg r10c = 1;
end
end
end
1: begin
if (!TRUE)
begin
reg r10d = 1;
end
else
begin
if (TRUE)
begin
reg r10e = 1;
end
else
begin
reg r10f = 1;
end
end
end
endcase
case (TRUE)
0: begin
if (!TRUE)
begin
reg r11a = 1;
end
else
begin
if (!TRUE)
begin
reg r11b = 1;
end
else
begin
reg r11c = 1;
end
end
end
1: begin
if (!TRUE)
begin
reg r11d = 1;
end
else
begin
if (!TRUE)
begin
reg r11e = 1;
end
else
begin
reg r11f = 1;
end
end
end
endcase
case (TRUE)
0: begin
if (!TRUE)
begin
reg r12a = 1;
end
else if (TRUE)
begin
reg r12b = 1;
end
else
begin
reg r12c = 1;
end
end
1: begin
if (!TRUE)
begin
reg r12d = 1;
end
else if (TRUE)
begin
reg r12e = 1;
end
else
begin
reg r12f = 1;
end
end
endcase
case (TRUE)
0: begin
if (!TRUE)
begin
reg r13a = 1;
end
else if (!TRUE)
begin
reg r13b = 1;
end
else
begin
reg r13c = 1;
end
end
1: begin
if (!TRUE)
begin
reg r13d = 1;
end
else if (!TRUE)
begin
reg r13e = 1;
end
else
begin
reg r13f = 1;
end
end
endcase
if (TRUE)
begin
reg r14a = 1;
end
else
begin
reg r14b = 1;
end
if (!TRUE)
begin
reg r15a = 1;
end
else
begin
if (TRUE)
begin
reg r15b = 1;
end
else
begin
reg r15c = 1;
end
end
if (!TRUE)
begin
reg r16a = 1;
end
else
begin
if (!TRUE)
begin
reg r16b = 1;
end
else
begin
reg r16c = 1;
end
end
if (!TRUE)
begin
reg r17a = 1;
end
else if (TRUE)
begin
reg r17b = 1;
end
else
begin
reg r17c = 1;
end
if (!TRUE)
begin
reg r18a = 1;
end
else if (!TRUE)
begin
reg r18b = 1;
end
else
begin
reg r18c = 1;
end
if (TRUE)
begin
if (TRUE)
begin
reg r19a = 1;
end
else
begin
reg r19b = 1;
end
end
else
begin
reg r19c = 1;
end
if (TRUE)
begin
if (!TRUE)
begin
reg r20a = 1;
end
else
begin
reg r20b = 1;
end
end
else
begin
reg r20c = 1;
end
if (TRUE)
begin
case (TRUE)
0: begin
reg r21a = 1;
end
1: begin
reg r21b = 1;
end
endcase
end
else
begin
case (TRUE)
0: begin
reg r21c = 1;
end
1: begin
reg r21d = 1;
end
endcase
end
if (!TRUE)
begin
case (TRUE)
0: begin
reg r22a = 1;
end
1: begin
reg r22b = 1;
end
endcase
end
else if (TRUE)
begin
case (TRUE)
0: begin
reg r22c = 1;
end
1: begin
reg r22d = 1;
end
endcase
end
else
begin
case (TRUE)
0: begin
reg r22e = 1;
end
1: begin
reg r22f = 1;
end
endcase
end
if (!TRUE)
begin
case (TRUE)
0: begin
reg r23a = 1;
end
1: begin
reg r23b = 1;
end
endcase
end
else if (!TRUE)
begin
case (TRUE)
0: begin
reg r23c = 1;
end
1: begin
reg r23d = 1;
end
endcase
end
else
begin
case (TRUE)
0: begin
reg r23e = 1;
end
1: begin
reg r23f = 1;
end
endcase
end
initial begin
$list_regs;
end
endmodule
|
//==================================================================================================
// Filename : antares_idex_register.v
// Created On : Sat Sep 5 21:08:59 2015
// Last Modified : Sat Nov 07 12:09:34 2015
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Simón Bolívar
// Email :
//
// Description : Pipeline register: ID -> EX
//==================================================================================================
module antares_idex_register (
input clk, // Main clock
input rst, // Main reset
input [4:0] id_alu_operation, // ALU operation from ID stage
input [31:0] id_data_rs, // Data Rs (forwarded)
input [31:0] id_data_rt, // Data Rt (forwarded)
input id_gpr_we, // GPR write enable
input id_mem_to_gpr_select, // Select MEM/ALU to GPR
input id_mem_write, // write to memory
input [1:0] id_alu_port_a_select, // Select: GPR, shamt, 0x00000004
input [1:0] id_alu_port_b_select, // Select: GPR, Imm16, PCAdd4
input [1:0] id_gpr_wa_select, // Select: direccion: Rt, Rd, $31
input id_mem_byte, // byte access
input id_mem_halfword, // halfword access
input id_mem_data_sign_ext, // Zero/Sign extend
input [4:0] id_rs, // Rs
input [4:0] id_rt, // Rt
input [3:0] id_dp_hazard,
input id_imm_sign_ext, // extend the imm16
input [15:0] id_sign_imm16, // sign_ext(imm16)
input [31:0] id_cp0_data, //
input [31:0] id_exception_pc, // Current PC
input id_movn,
input id_movz,
input id_llsc,
input id_kernel_mode,
input id_is_bds,
input id_trap,
input id_trap_condition,
input id_ex_exception_source,
input id_mem_exception_source,
input id_flush, // clean
input id_stall, // Stall ID stage
input ex_stall, // Stall EX stage
output reg [4:0] ex_alu_operation, // Same signals, but on EX stage
output reg [31:0] ex_data_rs, //
output reg [31:0] ex_data_rt, //
output reg ex_gpr_we, //
output reg ex_mem_to_gpr_select, //
output reg ex_mem_write, //
output reg [1:0] ex_alu_port_a_select, //
output reg [1:0] ex_alu_port_b_select, //
output reg [1:0] ex_gpr_wa_select, //
output reg ex_mem_byte, //
output reg ex_mem_halfword, //
output reg ex_mem_data_sign_ext, //
output reg [4:0] ex_rs, //
output reg [4:0] ex_rt, //
output reg [3:0] ex_dp_hazard,
output reg [16:0] ex_sign_imm16, //
output reg [31:0] ex_cp0_data,
output reg [31:0] ex_exception_pc,
output reg ex_movn,
output reg ex_movz,
output reg ex_llsc,
output reg ex_kernel_mode,
output reg ex_is_bds,
output reg ex_trap,
output reg ex_trap_condition,
output reg ex_ex_exception_source,
output reg ex_mem_exception_source
);
// sign extend the imm16
wire [16:0] id_imm_extended = (id_imm_sign_ext) ? {id_sign_imm16[15], id_sign_imm16[15:0]} : {1'b0, id_sign_imm16};
//--------------------------------------------------------------------------
// Propagate signals
// Clear only critical signals: op, WE, MEM write and Next PC
//--------------------------------------------------------------------------
always @(posedge clk) begin
ex_alu_operation <= (rst) ? 5'b0 : ((ex_stall & ~id_flush) ? ex_alu_operation : ((id_stall | id_flush) ? 5'b0 : id_alu_operation));
ex_data_rs <= (rst) ? 32'b0 : ((ex_stall & ~id_flush) ? ex_data_rs : id_data_rs);
ex_data_rt <= (rst) ? 32'b0 : ((ex_stall & ~id_flush) ? ex_data_rt : id_data_rt);
ex_gpr_we <= (rst) ? 1'b0 : ((ex_stall & ~id_flush) ? ex_gpr_we : ((id_stall | id_flush) ? 1'b0 : id_gpr_we));
ex_mem_to_gpr_select <= (rst) ? 1'b0 : ((ex_stall & ~id_flush) ? ex_mem_to_gpr_select : ((id_stall | id_flush) ? 1'b0 : id_mem_to_gpr_select));
ex_mem_write <= (rst) ? 1'b0 : ((ex_stall & ~id_flush) ? ex_mem_write : ((id_stall | id_flush) ? 1'b0 : id_mem_write));
ex_alu_port_a_select <= (rst) ? 2'b0 : ((ex_stall & ~id_flush) ? ex_alu_port_a_select : id_alu_port_a_select);
ex_alu_port_b_select <= (rst) ? 2'b0 : ((ex_stall & ~id_flush) ? ex_alu_port_b_select : id_alu_port_b_select);
ex_gpr_wa_select <= (rst) ? 2'b0 : ((ex_stall & ~id_flush) ? ex_gpr_wa_select : id_gpr_wa_select);
ex_mem_byte <= (rst) ? 1'b0 : ((ex_stall & ~id_flush) ? ex_mem_byte : id_mem_byte);
ex_mem_halfword <= (rst) ? 1'b0 : ((ex_stall & ~id_flush) ? ex_mem_halfword : id_mem_halfword);
ex_mem_data_sign_ext <= (rst) ? 1'b0 : ((ex_stall & ~id_flush) ? ex_mem_data_sign_ext : id_mem_data_sign_ext);
ex_rs <= (rst) ? 5'b0 : ((ex_stall & ~id_flush) ? ex_rs : id_rs);
ex_rt <= (rst) ? 5'b0 : ((ex_stall & ~id_flush) ? ex_rt : id_rt);
ex_dp_hazard <= (rst) ? 4'b0 : ((ex_stall & ~id_flush) ? ex_dp_hazard : ((id_stall | id_flush) ? 4'b0 : id_dp_hazard));
ex_sign_imm16 <= (rst) ? 17'b0 : ((ex_stall & ~id_flush) ? ex_sign_imm16 : id_imm_extended);
ex_cp0_data <= (rst) ? 32'b0 : ((ex_stall & ~id_flush) ? ex_cp0_data : id_cp0_data);
ex_exception_pc <= (rst) ? 32'b0 : ((ex_stall & ~id_flush) ? ex_exception_pc : id_exception_pc);
ex_movn <= (rst) ? 1'b0 : ((ex_stall & ~id_flush) ? ex_movn : ((id_stall | id_flush) ? 1'b0 : id_movn));
ex_movz <= (rst) ? 1'b0 : ((ex_stall & ~id_flush) ? ex_movz : ((id_stall | id_flush) ? 1'b0 : id_movz));
ex_llsc <= (rst) ? 1'b0 : ((ex_stall & ~id_flush) ? ex_llsc : id_llsc);
ex_kernel_mode <= (rst) ? 1'b0 : ((ex_stall & ~id_flush) ? ex_kernel_mode : id_kernel_mode);
ex_is_bds <= (rst) ? 1'b0 : ((ex_stall & ~id_flush) ? ex_is_bds : id_is_bds);
ex_trap <= (rst) ? 1'b0 : ((ex_stall & ~id_flush) ? ex_trap : ((id_stall | id_flush) ? 1'b0 : id_trap));
ex_trap_condition <= (rst) ? 1'b0 : ((ex_stall & ~id_flush) ? ex_trap_condition : id_trap_condition);
ex_ex_exception_source <= (rst) ? 1'b0 : ((ex_stall & ~id_flush) ? ex_ex_exception_source : ((id_stall | id_flush) ? 1'b0 : id_ex_exception_source));
ex_mem_exception_source <= (rst) ? 1'b0 : ((ex_stall & ~id_flush) ? ex_mem_exception_source : ((id_stall | id_flush) ? 1'b0 : id_mem_exception_source));
end // always @ (posedge clk)
endmodule // antares_idex_register
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 06/17/2017 09:57:13 AM
// Design Name:
// Module Name: Snake
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
//ÉßÔ˶¯Çé¿ö¿ØÖÆÄ£¿é
module Snake
(
input clk,
input rst,
input[15:0] point,
input left_press,
input right_press,
input up_press,
input down_press,
output reg [1:0]snake,//ÓÃÓÚ±íʾµ±Ç°É¨ÃèɨÃèµÄ²¿¼þ ËÄÖÖ״̬ 00£ºÎÞ 01£ºÍ· 10£ºÉíÌå 11£ºÇ½
input [9:0]x_pos,
input [9:0]y_pos,//ɨÃè×ø±ê µ¥Î»£º"ÏñËصã"
output [5:0]head_x,
output [5:0]head_y,//Í·²¿¸ñ×ø±ê
input add_cube,//Ôö¼ÓÌ峤ÐźÅ
input [1:0]game_status,//ËÄÖÖÓÎϷ״̬
output reg [6:0]cube_num,
output reg hit_body, //ײµ½Éí×ÓÐźÅ
output reg hit_wall, //ײµ½Ç½ÐźÅ
input die_flash //ÉÁ¶¯ÐźÅ
);
localparam UP = 2'b00;
localparam DOWN = 2'b01;
localparam LEFT = 2'b10;
localparam RIGHT = 2'b11;
localparam NONE = 2'b00;
localparam HEAD = 2'b01;
localparam BODY = 2'b10;
localparam WALL = 2'b11;
localparam RESTART = 2'b00;
localparam PLAY = 2'b10;
reg[31:0]cnt;
reg[31:0] cnt_lv1 = 32'd12_500_000;
reg[31:0] cnt_lv2 = 32'd62_500_00;
wire[1:0]direct;
reg [1:0]direct_r; //¼Ä´æ·½Ïò
assign direct = direct_r;//¼Ä´æÏÂÒ»¸ö·½Ïò
reg[1:0]direct_next;
reg change_to_left;
reg change_to_right;
reg change_to_up;
reg change_to_down;
reg [5:0]cube_x[15:0];
reg [5:0]cube_y[15:0];//Ì峤×ø±ê µ¥Î»£º"¸ñ×Ó"
reg [15:0]is_exist; //ÓÃÓÚ¿ØÖÆÉí×ÓµÄÁÁÃ𣬼´¿ØÖÆÉí×Ó³¤¶È
reg addcube_state;
assign head_x = cube_x[0];
assign head_y = cube_y[0];
always @(posedge clk or negedge rst) begin
if(!rst)
direct_r <= RIGHT; //ĬÈÏÒ»³öÀ´ÏòÓÒÒƶ¯
else if(game_status == RESTART)
direct_r <= RIGHT;
else
direct_r <= direct_next;
end
always @(posedge clk or negedge rst) begin
//³ÔÏÂÆ»¹ûû£¿£¬³ÔÏÂÔòadd_cube==1£¬ÏÔʾÌ峤Ôö¼Óһ룬"is_exixt[cube_num]<=1",ÈõÚcube_numλ"³öÏÖ"
if(!rst) begin
is_exist <= 16'd7;
cube_num <= 3;
addcube_state <= 0;//³õʼÏÔʾ³¤¶ÈΪ3£¬is_exist=0000_0000_0111,±íʾǰÈýλ³öÏÖ
end
else if (game_status == RESTART) begin
is_exist <= 16'd7;
cube_num <= 3;
addcube_state <= 0;
end
else begin
case(addcube_state) //ÅжÏÉßÍ·ÓëÆ»¹û×ø±êÊÇ·ñÖغÏ
0:begin
if(add_cube) begin
cube_num <= cube_num + 1;
is_exist[cube_num] <= 1;
addcube_state <= 1;//"³ÔÏÂ"ÐźÅ
end
end
1:begin
if(!add_cube)
addcube_state <= 0;
end
endcase
end
end
reg[3:0]lox;
reg[3:0]loy;
always @(x_pos or y_pos ) begin
if(x_pos >= 0 && x_pos < 640 && y_pos >= 0 && y_pos < 480) begin
if(x_pos[9:4] == 0 | y_pos[9:4] == 0 | x_pos[9:4] == 39 | y_pos[9:4] == 29)
snake = WALL;//ɨÃèǽ
else if(x_pos[9:4] == cube_x[0] && y_pos[9:4] == cube_y[0] && is_exist[0] == 1)
snake = (die_flash == 1) ? HEAD : NONE;//ɨÃèÍ·
else if
((x_pos[9:4] == cube_x[1] && y_pos[9:4] == cube_y[1] && is_exist[1] == 1)|
(x_pos[9:4] == cube_x[2] && y_pos[9:4] == cube_y[2] && is_exist[2] == 1)|
(x_pos[9:4] == cube_x[3] && y_pos[9:4] == cube_y[3] && is_exist[3] == 1)|
(x_pos[9:4] == cube_x[4] && y_pos[9:4] == cube_y[4] && is_exist[4] == 1)|
(x_pos[9:4] == cube_x[5] && y_pos[9:4] == cube_y[5] && is_exist[5] == 1)|
(x_pos[9:4] == cube_x[6] && y_pos[9:4] == cube_y[6] && is_exist[6] == 1)|
(x_pos[9:4] == cube_x[7] && y_pos[9:4] == cube_y[7] && is_exist[7] == 1)|
(x_pos[9:4] == cube_x[8] && y_pos[9:4] == cube_y[8] && is_exist[8] == 1)|
(x_pos[9:4] == cube_x[9] && y_pos[9:4] == cube_y[9] && is_exist[9] == 1)|
(x_pos[9:4] == cube_x[10] && y_pos[9:4] == cube_y[10] && is_exist[10] == 1)|
(x_pos[9:4] == cube_x[11] && y_pos[9:4] == cube_y[11] && is_exist[11] == 1)|
(x_pos[9:4] == cube_x[12] && y_pos[9:4] == cube_y[12] && is_exist[12] == 1)|
(x_pos[9:4] == cube_x[13] && y_pos[9:4] == cube_y[13] && is_exist[13] == 1)|
(x_pos[9:4] == cube_x[14] && y_pos[9:4] == cube_y[14] && is_exist[14] == 1)|
(x_pos[9:4] == cube_x[15] && y_pos[9:4] == cube_y[15] && is_exist[15] == 1))
snake = (die_flash == 1) ? BODY : NONE;//ɨÃèÉíÌå
else snake = NONE;
end
end
endmodule
|
`timescale 1 ns / 100 ps
// ********************************************************************/
// Actel Corporation Proprietary and Confidential
// Copyright 2009 Actel Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
// Description: AMBA BFMs
// AHB Lite BFM
//
// Revision Information:
// Date Description
// 01Sep07 Initial Release
// 14Sep07 Updated for 1.2 functionality
// 25Sep07 Updated for 1.3 functionality
// 09Nov07 Updated for 1.4 functionality
// 08May08 2.0 for Soft IP Usage
//
// SVN Revision Information:
// SVN $Revision: 21608 $
// SVN $Date: 2013-12-02 16:03:36 -0800 (Mon, 02 Dec 2013) $
//
//
// Resolved SARs
// SAR Date Who Description
//
//
// Notes:
// 28Nov07 IPB Updated to increase throughput
//
// *********************************************************************/
module BFM_APB2APB ( PCLK_PM, PRESETN_PM, PADDR_PM, PWRITE_PM, PENABLE_PM, PWDATA_PM, PRDATA_PM, PREADY_PM, PSLVERR_PM,
PCLK_SC, PSEL_SC, PADDR_SC, PWRITE_SC, PENABLE_SC, PWDATA_SC, PRDATA_SC, PREADY_SC, PSLVERR_SC);
parameter[9:0] TPD = 1;
localparam TPDns = TPD * 1;
input PCLK_PM;
input PRESETN_PM;
input[31:0] PADDR_PM;
input PWRITE_PM;
input PENABLE_PM;
input[31:0] PWDATA_PM;
output[31:0] PRDATA_PM;
reg[31:0] PRDATA_PM;
output PREADY_PM;
reg PREADY_PM;
output PSLVERR_PM;
reg PSLVERR_PM;
input PCLK_SC;
output[15:0] PSEL_SC;
wire[15:0] #TPDns PSEL_SC;
output[31:0] PADDR_SC;
wire[31:0] #TPDns PADDR_SC;
output PWRITE_SC;
wire #TPDns PWRITE_SC;
output PENABLE_SC;
wire #TPDns PENABLE_SC;
output[31:0] PWDATA_SC;
wire[31:0] #TPDns PWDATA_SC;
input[31:0] PRDATA_SC;
input PREADY_SC;
input PSLVERR_SC;
parameter[0:0] IDLE = 0;
parameter[0:0] ACTIVE = 1;
reg[0:0] STATE_PM;
parameter[1:0] T0 = 0;
parameter[1:0] T1 = 1;
parameter[1:0] T2 = 2;
reg[1:0] STATE_SC;
reg[15:0] PSEL_P0;
reg[31:0] PADDR_P0;
reg PWRITE_P0;
reg PENABLE_P0;
reg[31:0] PWDATA_P0;
reg PSELEN;
reg[31:0] PRDATA_HD;
reg PSLVERR_HD;
reg PENABLE_PM_P0;
reg TRIGGER;
reg DONE;
always @(posedge PCLK_PM or negedge PRESETN_PM)
begin
if (PRESETN_PM == 1'b0)
begin
STATE_PM <= IDLE ;
TRIGGER <= 1'b0 ;
PREADY_PM <= 1'b0 ;
PSLVERR_PM <= 1'b0 ;
PRDATA_PM <= {32{1'b0}} ;
PENABLE_PM_P0 <= 1'b0 ;
end
else
begin
PREADY_PM <= 1'b0 ;
PENABLE_PM_P0 <= PENABLE_PM ;
case (STATE_PM)
IDLE :
begin
if (PENABLE_PM == 1'b1 & PENABLE_PM_P0 == 1'b0)
begin
TRIGGER <= 1'b1 ;
STATE_PM <= ACTIVE ;
end
end
ACTIVE :
begin
if (DONE == 1'b1)
begin
STATE_PM <= IDLE ;
TRIGGER <= 1'b0 ;
PREADY_PM <= 1'b1 ;
PSLVERR_PM <= PSLVERR_HD ;
PRDATA_PM <= PRDATA_HD ;
end
end
endcase
end
end
always @(posedge PCLK_SC or negedge TRIGGER)
begin
if (TRIGGER == 1'b0)
begin
STATE_SC <= T0 ;
DONE <= 1'b0 ;
PRDATA_HD <= {32{1'b0}} ;
PSLVERR_HD <= 1'b0 ;
PSELEN <= 1'b0 ;
PENABLE_P0 <= 1'b0 ;
PADDR_P0 <= {32{1'b0}} ;
PWDATA_P0 <= {32{1'b0}} ;
PWRITE_P0 <= 1'b0 ;
end
else
begin
case (STATE_SC)
T0 :
begin
STATE_SC <= T1 ;
PADDR_P0 <= PADDR_PM ;
PWDATA_P0 <= PWDATA_PM ;
PWRITE_P0 <= PWRITE_PM ;
PSELEN <= 1'b1 ;
PENABLE_P0 <= 1'b0 ;
DONE <= 1'b0 ;
end
T1 :
begin
STATE_SC <= T2 ;
PENABLE_P0 <= 1'b1 ;
end
T2 :
begin
if (PREADY_SC == 1'b1)
begin
DONE <= 1'b1 ;
PRDATA_HD <= PRDATA_SC ;
PSLVERR_HD <= PSLVERR_SC ;
PSELEN <= 1'b0 ;
PENABLE_P0 <= 1'b0 ;
PADDR_P0 <= {32{1'b0}} ;
PWDATA_P0 <= {32{1'b0}} ;
PWRITE_P0 <= 1'b0 ;
end
end
endcase
end
end
always @(PADDR_P0 or PSELEN)
begin
PSEL_P0 <= {16{1'b0}} ;
if (PSELEN == 1'b1)
begin
begin : xhdl_5
integer i;
for(i = 0; i <= 15; i = i + 1)
begin
PSEL_P0[i] <= (PADDR_P0[27:24] == i);
end
end
end
end
assign PSEL_SC = PSEL_P0 ;
assign PADDR_SC = PADDR_P0 ;
assign PWRITE_SC = PWRITE_P0 ;
assign PENABLE_SC = PENABLE_P0 ;
assign PWDATA_SC = PWDATA_P0 ;
endmodule
|
//control unit for write enable and ALU control
//defining the conditions inside the conditional instructions
`include "define.v"
module control(
opcode,
//cond,
//flag,
dmem_wen,
rf_wen,
alu_op,
alusrc,
regdest,
branch,
mem2reg,
lhb_llb_con1,
s5,
s6,
s7,
jal,
jr,
exec,
lw,
//jump_control
);
input[3:0] opcode;
//cond is needed for branch
//input [3:0] cond;
//flag will be of a previous instruction
//input[2:0] flag;
output reg dmem_wen;
output reg rf_wen;
output reg[2:0] alu_op;
output reg alusrc;
output reg regdest;
output reg branch;
output reg mem2reg;
output reg lhb_llb_con1;
output reg s5;
output reg s6;
output reg s7;
output reg jal;
output reg jr;
output reg exec;
output reg lw;
//output reg control_lhb_llb;
//output reg jump_control;
always @ (*)
begin
//dmem_wen is active on low
// rf_wen is active on high
if ( (opcode==`ADD) || (opcode==`SUB) || (opcode==`AND) || (opcode==`OR) )
begin
dmem_wen=1;
rf_wen=1;
alu_op=opcode[2:0];
alusrc=0;
regdest=1;
branch=0;
mem2reg=0;
lhb_llb_con1 = 0;
s5 = 0;
s6 = 1;
s7 = 0;//THIS SHOULD BE 0
jal = 0;
jr = 0;
exec = 0;
lw=0;
end
if ( (opcode==`SLL) || (opcode==`SRL) || (opcode==`SRA) || (opcode==`RL) )
begin
dmem_wen=1;
rf_wen=1;
alu_op=opcode[2:0];
alusrc=1;
regdest=1;
branch=0;
mem2reg=0;
lhb_llb_con1 = 0;
s5 = 0;
s6 = 1;
s7 = 0;
jal=0;
jr = 0;
exec = 0;
lw=0;
end
if (opcode==`LW)
begin
dmem_wen=1;
rf_wen=1;
alu_op=3'b000;
alusrc=1;
regdest=1;
branch=0;
mem2reg=1;
lhb_llb_con1 = 0;
s5 = 0;
s6 = 1;
s7 = 0;
jal=0;
jr = 0;
exec =0;
lw=1;
end
if (opcode==`SW)
begin
dmem_wen=0;
rf_wen=0;
alu_op=3'b000;
alusrc=1;
regdest=0;
branch=0;
//FIXED
lhb_llb_con1 = 1;
s5 = 0;
s6 = 1;
jal=0;
jr = 0;
exec = 0;
lw=0;
mem2reg=0;
end
if((opcode == `LHB))
begin
dmem_wen = 1;
alu_op = 3'b010;
rf_wen = 1;
regdest = 1;
branch = 0;
lhb_llb_con1 = 1;
mem2reg=0;
alusrc = 0;
s5 = 1;
s6 = 0;
s7 = 0;
jal=0;
jr = 0;
exec = 0;
lw=0;
end
if(opcode == `LLB)
begin
dmem_wen = 1;
rf_wen = 1;
regdest = 1;
mem2reg=0;
s7 = 1;
branch = 0;
jal=0;
jr = 0;
exec = 0;
lw=0;
end
if(opcode == `JAL)
begin
dmem_wen=1;
rf_wen=1;
alu_op=3'b000; // ALU will be NOP (decided by control_EXE)
//alusrc=1; // not using ALU
//regdest=1;
branch=0;
jal = 1;
mem2reg=0;
lhb_llb_con1 = 0;
s5 = 0;
s6 = 1;
s7 = 0;
jr = 0;
exec = 0;
lw=0;
end
if(opcode == `JR)
begin
dmem_wen = 1;
rf_wen = 0;
branch = 0;
lhb_llb_con1 = 1;
mem2reg=0;
jal = 0;
s5 = 0;
s6 = 1;
s7 = 0;
jr = 1;
exec = 0;
lw=0;
end
if(opcode == `EXEC)
begin
dmem_wen = 1;
rf_wen = 0;
branch = 0;
mem2reg=0;
lhb_llb_con1 = 1;
jal = 0;
s5 = 0;
s6 = 1;
s7 = 0;
jr = 0;
exec = 1;
lw=0;
end
/*if(opcode == `JAL)
begin
control_lhb_llb = 0;
lhb_llb_sec_control = 0;
rf_wen = 1;
dmem_wen = 1;
jr_rf = 0;
jr_adder = 0;
jal_control_mux = 1;
jal_write_reg = 1;
mem_branch = 0;
end*/
if((opcode == `BR))
begin
//control_lhb_llb = 0;
//lhb_llb_sec_control = 0;
//jal_control_mux = 0;
//jal_write_reg = 0;
//jr_rf=0;
//jr_adder=0;
s7 = 0;
dmem_wen=1;
rf_wen=0;
branch=1;
jal=0;
jr = 0;
mem2reg=0;
/*if(flag[2] == 1'b1 && cond==4'b000)
begin
//Branch EQUAL previous instruction condition
dmem_wen = 1;
rf_wen = 0;
branch = 1;
end
else if(flag[2] == 1'b0 && cond==4'b001)
begin
//Branch NOT EQUAL prev instruction condition
dmem_wen = 1;
rf_wen = 0;
branch = 1;
end
else if((flag[2] == 1'b0) && (flag[0] == 1'b0) && cond == 4'b010)
begin
//Branch GREATER THAN prev instruction condition
dmem_wen = 1;
rf_wen = 0;
branch = 1;
end
else if(flag[0] == 1'b1 && cond == 4'b011)
begin
//Branch LESS THAN prev instruction condition
dmem_wen = 1;
rf_wen = 0;
branch = 1;
end
else if((flag[2] == 1'b1) || ((flag[2] == 1'b0) && (flag[0] == 1'b0)) && cond == 4'b100)
begin
//Branch Greater Than or Equal To prev instruction condition
dmem_wen = 1;
rf_wen = 0;
branch = 1;
end
else if((flag[0] == 1'b1) || (flag[2] == 1'b0) && cond == 4'b101)
begin
//Branch Less Than or Equal To prev instruction condition
dmem_wen = 1;
rf_wen = 0;
branch = 1;
end
else if(flag[1] == 1'b1 && cond == 110)
begin
//Branch overflow prev instruction condition
dmem_wen = 1;
rf_wen = 0;
branch = 1;
end
else if(cond==4'b111)
begin
//Branch if true
dmem_wen = 1;
rf_wen = 0;
branch = 1;
end
else
begin
dmem_wen = 1;
rf_wen = 0;
branch = 0;
end */
end
end
endmodule |
#include <bits/stdc++.h> using namespace std; int main() { int c, d, n, m, k; cin >> c >> d >> n >> m >> k; int users = n * m - k; int ans = 1000000000; for (int i = 0; i <= m; i++) for (int j = 0; j <= 10000; j++) { if (i * n + j >= users) { if (c * i + j * d < ans) ans = c * i + j * d; } } cout << ans; } |
#include <bits/stdc++.h> using namespace std; const int MAX_N = 2e5 + 1; int main() { int N, Q; cin >> N >> Q; set<int> all; multiset<int> gaps; for (int i = 0; i < N; ++i) { int x; cin >> x; all.insert(x); } for (auto iter = all.begin(); iter != all.end(); ++iter) { auto nxt = next(iter); if (nxt != all.end()) { gaps.insert(*nxt - *iter); } } cout << ((all.size() > 2) ? ((*prev(all.end()) - *all.begin()) - *prev(gaps.end())) : 0) << endl; while (Q--) { int type; int x; cin >> type >> x; if (type) { auto iter = all.insert(x).first; if (all.size() > 1) { if (iter == all.begin()) { gaps.insert(*next(iter) - *iter); } else if (iter == prev(all.end())) { gaps.insert(*iter - *prev(iter)); } else { int gap_l = *next(iter) - *iter; int gap_r = *iter - *prev(iter); auto gap_old = gaps.find(*next(iter) - *prev(iter)); gaps.erase(gap_old); gaps.insert(gap_l); gaps.insert(gap_r); } } } else { auto cur = all.find(x); if (cur == all.begin() && all.size() > 1) { gaps.erase(gaps.find(*next(cur) - *cur)); } else if (cur == prev(all.end()) && all.size() > 1) { gaps.erase(gaps.find(*cur - *prev(cur))); } else if (all.size() > 2) { auto prv = prev(cur); auto nxt = next(cur); auto gap1_old = gaps.find(*cur - *prv); gaps.erase(gap1_old); auto gap2_old = gaps.find(*nxt - *cur); gaps.erase(gap2_old); gaps.insert(*nxt - *prv); } all.erase(x); } cout << ((all.size() > 2) ? ((*prev(all.end()) - *all.begin()) - *prev(gaps.end())) : 0) << endl; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O32AI_2_V
`define SKY130_FD_SC_HS__O32AI_2_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog wrapper for o32ai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o32ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o32ai_2 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o32ai_2 (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O32AI_2_V
|
#include <bits/stdc++.h> using namespace std; int const N = 202000; set<int> s; set<int>::iterator it; int edg[N]; vector<int> g[N]; int ans[N]; int cur = 1; int vis[N]; void dfs(int node) { vis[node] = 1; ans[cur]++; vector<int> send; for (it = s.begin(); it != s.end();) { if (!binary_search(g[node].begin(), g[node].end(), *it)) { send.push_back(*it); s.erase(it++); } else it++; } for (int el : send) dfs(el); } int main() { int n, e; scanf( %d%d , &n, &e); for (int i = 1; i <= n; ++i) s.insert(i); for (int i = 0; i < e; ++i) { int temp, temp1; scanf( %d%d , &temp, &temp1); edg[temp]++; edg[temp1]++; g[temp].push_back(temp1); g[temp1].push_back(temp); } vector<pair<int, int>> go; for (int i = 1; i <= n; i++) { go.push_back(make_pair(edg[i], i)); sort(g[i].begin(), g[i].end()); } sort(go.begin(), go.end()); for (auto el : go) { if (vis[el.second]) continue; s.erase(el.second); ans[0]++; dfs(el.second); cur++; } cout << ans[0] << n ; sort(ans + 1, ans + ans[0] + 1); for (int i = 1; i <= ans[0]; i++) { cout << ans[i] << ; } return 0; } |
module uart(
input clk,
input rst,
// uart lines
input hwrx,
output hwtx,
// bus interface
input addr, // 2 registers
input we,
input re,
input [31:0] wdata,
output reg [31:0] rdata,
// latch char on rising edge if dosend set
// input [7:0] txchar,
// input dosend,
// rx
output reg [7:0] rxchar,
output reg rxvalid
);
initial begin
end
// 24000000 / (115200) ==
`define BAUD_DIV 208
// tx
reg [7:0] txclkdiv;
reg [9:0] txshift;
reg [3:0] txcount;
assign hwtx = txshift[0];
reg txdone;
always @ (posedge clk)
begin
if (rst)
begin
txdone <= 1;
txcount <= 0;
txshift <= 1;
txclkdiv <= 0;
end else if (we && txdone) begin
// start the tx process
txshift[0] <= 0; // start bit
txshift[8:1] <= wdata[7:0];
txshift[9] <= 1; // stop bit
txcount <= 9;
// start bit
txclkdiv <= `BAUD_DIV;
txdone <= 0;
end else if (!txdone) begin
// keep shifting bits out
if (txclkdiv == 0) begin
txshift <= txshift >> 1;
txclkdiv <= `BAUD_DIV;
if (txcount == 0) begin
// terminating condition
txdone <= 1;
end else begin
txcount <= txcount - 1;
end
end else begin
txclkdiv <= txclkdiv - 1;
end
end
end
always @(posedge clk)
begin
if (re) begin
rdata <= txdone;
end else begin
rdata <= 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
end
end
// XXX rx is disabled for now
initial begin
rxvalid <= 0;
rxchar <= 0;
end
/*
// rx
reg [7:0] rxshift;
reg [3:0] rxclkdiv;
integer rxcount;
always @ (posedge clk)
begin
if (rst)
begin
rxchar <= 0;
rxvalid <= 0;
rxcount <= 0;
rxclkdiv <= 0;
end
else
begin
// rx state machine
if (rxcount == 0) begin
if (hwrx == 0) begin
// possible start bit
rxcount <= 1;
rxclkdiv <= 1;
rxshift <= 0;
end
end else begin
if (rxclkdiv == 8) begin
if (rxcount >= 1 && rxcount <= 9) begin // rxcount > 0
// data bits
rxshift[7:1] <= rxshift[6:0];
rxshift[0] <= hwrx;
rxcount <= rxcount + 1;
end else if (rxcount == 10) begin
// stop bit
if (hwrx == 1) begin
// it's valid
$display("what");
rxchar <= rxshift;
rxvalid <= 1;
end else begin
// reject it
rxcount <= 0;
rxvalid <= 0;
end
end
end
rxclkdiv <= rxclkdiv + 1;
end
end
end
*/
endmodule // uart
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } long long lcm(long long a, long long b) { return a / gcd(a, b) * b; } long long powmod(long long a, long long b, long long MOD) { if (a == 0ll) { return 0ll; } a %= MOD; long long ans = 1; while (b) { if (b & 1) { ans = ans * a % MOD; } a = a * a % MOD; b >>= 1; } return ans; } long long poww(long long a, long long b) { if (a == 0ll) { return 0ll; } long long ans = 1; while (b) { if (b & 1) { ans = ans * a; } a = a * a; b >>= 1; } return ans; } void Pv(const vector<int> &V) { int Len = int(V.size()); for (int i = 0; i < Len; ++i) { printf( %d , V[i]); if (i != Len - 1) { printf( ); } else { printf( n ); } } } void Pvl(const vector<long long> &V) { int Len = int(V.size()); for (int i = 0; i < Len; ++i) { printf( %lld , V[i]); if (i != Len - 1) { printf( ); } else { printf( n ); } } } inline long long readll() { long long tmp = 0, fh = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) fh = -1; c = getchar(); } while (c >= 0 && c <= 9 ) tmp = tmp * 10 + c - 48, c = getchar(); return tmp * fh; } inline int readint() { int tmp = 0, fh = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) fh = -1; c = getchar(); } while (c >= 0 && c <= 9 ) tmp = tmp * 10 + c - 48, c = getchar(); return tmp * fh; } void pvarr_int(int *arr, int n, int strat = 1) { if (strat == 0) { n--; } for (int i = strat; i <= n; i++) { printf( %d%c , arr[i], i == n ? n : ); } } void pvarr_LL(long long *arr, int n, int strat = 1) { if (strat == 0) { n--; } for (int i = strat; i <= n; i++) { printf( %lld%c , arr[i], i == n ? n : ); } } const int maxn = 1000010; const int inf = 0x3f3f3f3f; int n, m; long long a[maxn], b[maxn]; struct node { int f, t; long long val; node() {} node(int ff, int tt, long long vv) { f = ff; t = tt; val = vv; } bool operator<(const node &bb) const { return val > bb.val; } }; std::vector<node> v; int far[maxn]; void dsu_init(int n) { for (int i = 0; i <= n; i++) { far[i] = i; } } int findpar(int x) { if (x == far[x]) { return x; } else { return far[x] = findpar(far[x]); } } void mg(int x, int y) { x = findpar(x); y = findpar(y); if (x == y) return; far[x] = y; } long long maxst() { dsu_init(n + m); sort((v).begin(), (v).end()); long long res = 0ll; for (auto e : v) { int x = e.f; int y = e.t; x = findpar(x); y = findpar(y); if (x != y) { res += e.val; far[x] = y; } } return res; } int main() { m = readint(); n = readint(); for (int i = 1; i <= m; i++) { a[i] = readll(); } for (int i = 1; i <= n; i++) { b[i] = readll(); } long long ans = 0ll; for (int i = 1; i <= m; i++) { int k = readint(); while (k--) { int x = readint(); ans += a[i] + b[x]; v.push_back(node(i, m + x, a[i] + b[x])); v.push_back(node(m + x, i, a[i] + b[x])); } } printf( %lld n , ans - maxst()); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYMETAL6S4S_1_V
`define SKY130_FD_SC_MS__DLYMETAL6S4S_1_V
/**
* dlymetal6s4s: 6-inverter delay with output from 4th inverter on
* horizontal route.
*
* Verilog wrapper for dlymetal6s4s with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dlymetal6s4s.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dlymetal6s4s_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__dlymetal6s4s base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dlymetal6s4s_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__dlymetal6s4s base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYMETAL6S4S_1_V
|
//
// Copyright (c) 1999 Steve Williams ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate fork template 2
module main;
initial begin
other_main.passed;
end
endmodule // main
module other_main;
task passed;
$display("PASSED");
endtask // passed
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) { int n, m; cin >> n >> m; bool ch1 = false; if (m % 2 == 0) ch1 = true; bool ch2 = false; for (int i = 0; i < n; i++) { int a, b, c, d; cin >> a >> b >> c >> d; if (b == c) { ch2 = true; } } if (ch1 && ch2) { cout << YES n ; } else { cout << NO n ; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int hed[600010], nxt[600010], to[600010], cnt; inline void addedge(int u, int v) { nxt[++cnt] = hed[u]; hed[u] = cnt; to[cnt] = v; } int siz[300010], root[300010], ans[300010]; int mx[300010]; int id[6000010], son[6000010][2], tot; int n, q; int merge(int x, int y) { if (!x) return y; if (!y) return x; if (mx[id[y]] < mx[id[x]]) id[x] = id[y]; son[x][0] = merge(son[x][0], son[y][0]); son[x][1] = merge(son[x][1], son[y][1]); return x; } void update(int &x, int l, int r, int p, int v, int i) { if (!x) x = ++tot; if (v < mx[id[x]]) id[x] = i; if (l == r) return; int mid = (l + r) >> 1; if (p <= mid) update(son[x][0], l, mid, p, v, i); else update(son[x][1], mid + 1, r, p, v, i); } int query(int a, int b, int k, int l, int r) { if (a > b || l > r || !k) return 0; if (a == l && b == r) return id[k]; int mid = (l + r) >> 1; if (b <= mid) return query(a, b, son[k][0], l, mid); else if (a > mid) return query(a, b, son[k][1], mid + 1, r); else { int L = query(a, mid, son[k][0], l, mid), R = query(mid + 1, b, son[k][1], mid + 1, r); if (!L) return R; if (!R) return L; if (mx[L] < mx[R]) return L; else return R; } } void dfs(int x) { siz[x] = 1; for (int i = hed[x]; i; i = nxt[i]) { int y = to[i]; dfs(y); siz[x] += siz[y]; root[x] = merge(root[x], root[y]); mx[x] = max(mx[x], siz[y]); } update(root[x], 1, n, siz[x], mx[x], x); ans[x] = query((siz[x] + 1) / 2, siz[x], root[x], 1, n); } int main() { scanf( %d%d , &n, &q); mx[0] = 1e9; for (int i = 2; i <= n; i++) { int p; scanf( %d , &p); addedge(p, i); } dfs(1); while (q--) { int x; scanf( %d , &x); printf( %d n , ans[x]); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O41A_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__O41A_PP_BLACKBOX_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o41a (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O41A_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__INV_SYMBOL_V
`define SKY130_FD_SC_LS__INV_SYMBOL_V
/**
* inv: Inverter.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__inv (
//# {{data|Data Signals}}
input A,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__INV_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; vector<set<int> > A; set<int>::iterator it; int main() { int n, m, a; cin >> n; A.resize(n); int D[101]; for (int i = 1; i <= 100; ++i) D[i] = 0; for (int i = 0; i < n; ++i) { cin >> m; for (int j = 0; j < m; ++j) { cin >> a; ++D[a]; A[i].insert(a); } } for (int i = 0; i < n; ++i) { bool yes = 1; for (int j = 0; j < n; ++j) { if (i != j) { bool y = 0; for (it = A[j].begin(); it != A[j].end(); ++it) if (A[i].count(*it) == 0) y = 1; if (y == 0) yes = 0; } } if (yes) cout << YES << endl; else cout << NO << endl; } } |
#include <bits/stdc++.h> using namespace std; vector<vector<int>> g, rv; int ds[3030][3030]; vector<int> md[3030]; int rd[3030][3030]; vector<int> mr[3030]; int main() { int n, m; scanf( %d %d , &n, &m); g.assign(n, vector<int>()); rv.assign(n, vector<int>()); while (m--) { int a, b; scanf( %d %d , &a, &b); a--; b--; if (a == b) continue; g[a].push_back(b); rv[b].push_back(a); } memset(ds, -1, sizeof(ds)); memset(rd, -1, sizeof(rd)); for (int i = 0; i < n; i++) { ds[i][i] = rd[i][i] = 0; queue<int> q; priority_queue<pair<int, int>, vector<pair<int, int>>, greater<pair<int, int>>> pq; q.push(i); while (!q.empty()) { int u = q.front(); q.pop(); if (i != u) pq.push({ds[i][u], u}); while (pq.size() > 3) { pq.pop(); } for (int j = 0; j < g[u].size(); j++) { int v = g[u][j]; if (ds[i][v] >= 0) { continue; } ds[i][v] = ds[i][u] + 1; q.push(v); } } while (!pq.empty()) { int u = pq.top().second; pq.pop(); md[i].push_back(u); } q = queue<int>(); q.push(i); while (!q.empty()) { int u = q.front(); q.pop(); if (i != u) pq.push({rd[i][u], u}); while (pq.size() > 3) { pq.pop(); } for (int j = 0; j < rv[u].size(); j++) { int v = rv[u][j]; if (rd[i][v] >= 0) continue; rd[i][v] = rd[i][u] + 1; q.push(v); } } while (!pq.empty()) { int u = pq.top().second; pq.pop(); mr[i].push_back(u); } } int ma = 0; int mi[4]; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (i == j) continue; if (ds[i][j] < 0) continue; for (int k = 0; k < mr[i].size(); k++) { for (int l = 0; l < md[j].size(); l++) { int a = mr[i][k], b = md[j][l]; if (a == b || a == j) continue; if (b == i) continue; int dist = ds[a][i] + ds[i][j] + ds[j][b]; if (dist > ma) { ma = dist; mi[0] = a; mi[1] = i; mi[2] = j; mi[3] = b; } } } } } printf( %d %d %d %d n , mi[0] + 1, mi[1] + 1, mi[2] + 1, mi[3] + 1); } |
#include <bits/stdc++.h> using namespace std; set<int> s; int ans[300005]; int main() { int n, m, l, r, x; cin >> n >> m; for (int i = 1; i < n + 1; i++) { s.insert(i); ans[i] = 0; } for (int i = 0; i < m; i++) { cin >> l >> r >> x; set<int>::iterator lb = s.lower_bound(l), ub = s.upper_bound(r); for (set<int>::iterator it = lb; it != ub; it++) if (*it != x) ans[*it] = x; s.erase(lb, ub); s.insert(x); } for (int i = 1; i < n + 1; i++) cout << ans[i] << ; cout << n ; return 0; } |
/*
* fifo module implements simple fifo which could read
* and write entry in same cycle.
* NOTE: when issued rd command fifo shouldn't be empty,
* when issued wr command fifo shouldn't be full,
* when issued rd and wr commands fifo shouldn't be empty or full
* only when fifo is empty data_out isn't valid
* Author: Kimi - Aug 2010
*/
`ifndef _my_fifo
`define _my_fifo
`timescale 1ns / 1ns
module my_fifo #(parameter max_len = 16, len_wd = 4, entry_wd = 32)
(
input wire clk, rst, // standard input signals
input wire rd, wr, // raed and write signals
input wire [entry_wd-1:0] data_in, // input entry
output wire full, empty,// fifo status indicators
output wire [entry_wd-1:0] data_out, // output entry
output reg [len_wd-1:0] len // indicated current fifo length
);
reg [entry_wd-1:0] reg_ram [max_len-1:0]; // registers array that implements ram.
reg [len_wd:0] rd_ptr, // point to ram address of entry that will be retrieved in next read command
wr_ptr; // point to next free ram address that will be occupied during next write cmd.
assign full = (len == max_len);
assign empty = (len == 0);
assign data_out = reg_ram[rd_ptr];
// pointers and length managements FSM
always @ (posedge clk) begin
if(rst) begin
len <= #5 0;
rd_ptr <= #5 0;
wr_ptr <= #5 0;
end
else begin
if(rd && wr && rd_ptr != wr_ptr) begin // to prevent read and write to same address (read and write)
if(rd_ptr == max_len-1) begin
rd_ptr <= #5 {len_wd{1'b0}}; // 0
end
else begin
rd_ptr <= #5 rd_ptr + {{(len_wd-1){1'b0}},1'b1}; // 1
end
if(wr_ptr == max_len-1) begin
wr_ptr <= #5 {len_wd{1'b0}}; // 0
end
else begin
wr_ptr <= #5 wr_ptr + {{(len_wd-1){1'b0}},1'b1}; // 1
end
end
else if (rd && !empty) begin // read only
len <= #5 len - {{(len_wd-1){1'b0}},1'b1}; // len--
if(rd_ptr == max_len-1) begin
rd_ptr <= #5 {len_wd{1'b0}}; // 0
end
else begin
rd_ptr <= #5 rd_ptr + {{(len_wd-1){1'b0}},1'b1}; // rd_ptr++
end
end
else if (wr && !full) begin // write only
len <= #5 len + {{(len_wd-1){1'b0}},1'b1}; // len++
if(wr_ptr == max_len-1) begin
wr_ptr <= #5 {len_wd{1'b0}}; // 0
end
else begin
wr_ptr <= #5 wr_ptr + {{(len_wd-1){1'b0}},1'b1}; // wr_ptr++
end
end
end
end
// write data into fifo
always @ (posedge clk) begin
if(!rst && ((wr && !full) || (rd && wr && rd_ptr != wr_ptr))) begin
reg_ram[wr_ptr] <= #5 data_in;
end
end
endmodule
`endif |
// megafunction wizard: %In-System Sources and Probes%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsource_probe
// ============================================================
// File Name: hps_reset.v
// Megafunction Name(s):
// altsource_probe
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 16.0.2 Build 222 07/20/2016 SJ Standard Edition
// ************************************************************
//Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
module hps_reset (
probe,
source_clk,
source);
input probe;
input source_clk;
output [2:0] source;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ENABLE_METASTABILITY STRING "YES"
// Retrieval info: CONSTANT: INSTANCE_ID STRING "RST"
// Retrieval info: CONSTANT: PROBE_WIDTH NUMERIC "0"
// Retrieval info: CONSTANT: SLD_AUTO_INSTANCE_INDEX STRING "YES"
// Retrieval info: CONSTANT: SLD_INSTANCE_INDEX NUMERIC "0"
// Retrieval info: CONSTANT: SOURCE_INITIAL_VALUE STRING " 0"
// Retrieval info: CONSTANT: SOURCE_WIDTH NUMERIC "3"
// Retrieval info: USED_PORT: probe 0 0 0 0 INPUT NODEFVAL "probe"
// Retrieval info: USED_PORT: source 0 0 3 0 OUTPUT NODEFVAL "source[2..0]"
// Retrieval info: USED_PORT: source_clk 0 0 0 0 INPUT NODEFVAL "source_clk"
// Retrieval info: CONNECT: @probe 0 0 0 0 probe 0 0 0 0
// Retrieval info: CONNECT: @source_clk 0 0 0 0 source_clk 0 0 0 0
// Retrieval info: CONNECT: source 0 0 3 0 @source 0 0 3 0
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset_bb.v TRUE
|
#include <bits/stdc++.h> using namespace std; void O_o() { ios::sync_with_stdio(0); ios_base::sync_with_stdio(0); cin.tie(0), cout.tie(0); } int main() { O_o(); int x, y; bool flag; vector<int> vec; cin >> x; y = x; while (x != 0) { vec.push_back(x % 10); x = x / 10; } for (int i = 0; i < vec.size(); i++) { if (vec[i] == 4 || vec[i] == 7) flag = 1; else { flag = 0; break; } } if (flag) cout << YES ; else if (y % 7 == 0 || y % 4 == 0 || y == 799 || y == 94 || y == 141) cout << YES ; else cout << NO ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 5, maxh = 3; int mod[maxh] = {(int)1e9 + 7, (int)1e9 + 9, (int)998244353}; struct data { int v[maxh]; data(int a = 0, int b = 0, int c = 0) { v[0] = a; v[1] = b; v[2] = c; } int& operator[](int w) { return v[w]; } friend data operator+(data a, data b) { for (int i = 0; i < maxh; ++i) a[i] = (a[i] + b[i]) % mod[i]; return a; } friend data operator+(data a, int b) { for (int i = 0; i < maxh; ++i) a[i] = (a[i] + b) % mod[i]; return a; } friend data operator*(data a, data b) { for (int i = 0; i < maxh; ++i) a[i] = 1ll * a[i] * b[i] % mod[i]; return a; } friend data operator*(data a, int b) { for (int i = 0; i < maxh; ++i) a[i] = 1ll * a[i] * b % mod[i]; return a; } friend bool operator==(data a, data b) { for (int i = 0; i < maxh; ++i) if (a[i] != b[i]) return false; return true; } friend data operator-(data a, data b) { for (int i = 0; i < maxh; ++i) a[i] = ((a[i] - b[i]) % mod[i] + mod[i]) % mod[i]; return a; } void print() { cout << v[0] << << v[1] << << v[2] << n ; } }; data H[N], Pow[N]; int n; char s[N]; data geth(int L, int R) { return H[R] - H[L - 1] * Pow[R - L + 1]; } vector<int> Ans; int main() { scanf( %d%s , &n, s + 1); Pow[0] = data(1, 1, 1); for (int i = 1; i <= n; ++i) Pow[i] = Pow[i - 1] * 1331; for (int i = 1; i <= n; ++i) H[i] = (H[i - 1] * 1331) + (int)s[i]; for (int i = (n + 1) / 2, lst = 10000000, cur; i >= 1; --i) { int st = i, ed = n + 1 - st, mx = min(lst + 2, ed - st); mx -= (mx % 2 == 0); cur = -1; for (int t = mx; t >= 1; t -= 2) if (geth(st, st + t - 1) == geth(ed - t + 1, ed)) { cur = t; break; } Ans.push_back(cur); lst = cur; } reverse(Ans.begin(), Ans.end()); for (auto x : Ans) cout << x << ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A22O_1_V
`define SKY130_FD_SC_HVL__A22O_1_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__a22o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__a22o_1 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__a22o_1 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A22O_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21BO_LP_V
`define SKY130_FD_SC_LP__A21BO_LP_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog wrapper for a21bo with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a21bo.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a21bo_lp (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a21bo_lp (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21BO_LP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A22O_SYMBOL_V
`define SKY130_FD_SC_LS__A22O_SYMBOL_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a22o (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A22O_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR4B_SYMBOL_V
`define SKY130_FD_SC_HS__OR4B_SYMBOL_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__or4b (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D_N,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR4B_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; long long mod = 1e9 + 7; struct frac { long long first, second; frac(long long X = 0) : first((X % mod + mod) % mod), second(1) {} frac(long long X, long long Y) : first((X % mod + mod) % mod), second((Y % mod + mod) % mod) {} frac operator+(frac a) { return frac(first * a.second + second * a.first, second * a.second); } frac operator-(frac a) { return frac(first * a.second - second * a.first, second * a.second); } frac operator*(frac a) { return frac(first * a.first, second * a.second); } frac operator/(frac a) { return frac(first * a.second, second * a.first); } }; frac pd[1010][1010], pa, emplace_back; int va, vb, k; frac solve(int a, int ja) { if (a + ja >= k) return emplace_back * ((pa + frac(a + ja)) - (pa * frac(a + ja))) / ((pa - frac(1)) * (pa - frac(1))); if (pd[a][ja].first != -1) return pd[a][ja]; return pd[a][ja] = pa * solve(a + 1, ja) + emplace_back * solve(a, ja + a); } long long modpow(long long b, long long e) { long long ret = 1; while (e) { if (e & 1) ret = ret * b % mod; b = b * b % mod; e >>= 1; } return ret; } int main() { for (__typeof(1010) i = (0) - ((0) > (1010)); i != (1010) - ((0) > (1010)); i += 1 - 2 * ((0) > (1010))) for (__typeof(1010) j = (0) - ((0) > (1010)); j != (1010) - ((0) > (1010)); j += 1 - 2 * ((0) > (1010))) pd[i][j].first = -1; scanf( %d%d%d , &k, &va, &vb); pa = frac(va, va + vb); emplace_back = frac(vb, va + vb); frac p = solve(1, 0); frac ans = pa * p / (frac(1) - emplace_back); printf( %lld n , ans.first * modpow(ans.second, mod - 2) % mod); } |
module crc_unit
(
//OUTPUTS
output [31:0] crc_poly_out,
output [31:0] crc_out,
output [31:0] crc_init_out,
output [7:0] crc_idr_out,
output buffer_full,
output read_wait,
output reset_pending,
//INPUTS
input [31:0] bus_wr,
input [ 1:0] crc_poly_size,
input [ 1:0] bus_size,
input [ 1:0] rev_in_type,
input rev_out_type,
input crc_init_en,
input crc_idr_en,
input crc_poly_en,
input buffer_write_en,
input reset_chain,
input clk,
input rst_n
);
//Interconection signals
wire [ 1:0] size_in;
wire [ 1:0] byte_sel;
wire clear_crc_init;
wire set_crc_init;
wire bypass_byte0;
wire bypass_size;
wire crc_out_en;
wire byte_en;
wire buffer_en;
//The write in the buffer only occur if there is free space
assign buffer_en = buffer_write_en && !buffer_full;
//Instance of the Datapath
crc_datapath DATAPATH
(
.crc_out ( crc_out ),
.size_out ( size_in ),
.crc_idr_out ( crc_idr_out ),
.crc_poly_out ( crc_poly_out ),
.crc_init_out ( crc_init_out ),
.bus_wr ( bus_wr ),
.rev_in_type ( rev_in_type ),
.rev_out_type ( rev_out_type ),
.buffer_en ( buffer_en ),
.byte_en ( byte_en ),
.crc_init_en ( crc_init_en ),
.crc_out_en ( crc_out_en ),
.crc_idr_en ( crc_idr_en ),
.crc_poly_en ( crc_poly_en ),
.buffer_rst ( clear_crc_init ),
.bypass_byte0 ( bypass_byte0 ),
.bypass_size ( bypass_size ),
.byte_sel ( byte_sel ),
.size_in ( bus_size ),
.clear_crc_init_sel ( clear_crc_init ),
.set_crc_init_sel ( set_crc_init ),
.crc_poly_size ( crc_poly_size ),
.clk ( clk ),
.rst_n ( rst_n )
);
//Instance of the Control unit
crc_control_unit CONTROL_UNIT
(
.byte_en ( byte_en ),
.crc_out_en ( crc_out_en ),
.byte_sel ( byte_sel ),
.bypass_byte0 ( bypass_byte0 ),
.buffer_full ( buffer_full ),
.read_wait ( read_wait ),
.bypass_size ( bypass_size ),
.set_crc_init_sel ( set_crc_init ),
.clear_crc_init_sel ( clear_crc_init ),
.size_in ( size_in ),
.write ( buffer_write_en ),
.reset_chain ( reset_chain ),
.reset_pending ( reset_pending ),
.clk ( clk ),
.rst_n ( rst_n )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX = 3e5 + 9; int sz[MAX], ans[MAX], p[MAX], n, q; vector<int> g[MAX]; int dfs(int v) { sz[v] = 1; for (auto u : g[v]) sz[v] += dfs(u); return sz[v]; } void calc(int v) { int bes = -1; for (auto u : g[v]) { calc(u); if (sz[u] >= ceil(sz[v] / 2.0)) bes = u; } if (bes == -1) { ans[v] = v; return; } int t = ans[bes]; while (sz[t] < ceil(sz[v] / 2.0)) t = p[t]; ans[v] = t; } int main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); cin >> n >> q; for (int i = 1; i < n; i++) cin >> p[i], p[i]--, g[p[i]].push_back(i); dfs(0), calc(0); while (q--) { int x; cin >> x, x--; cout << ans[x] + 1 << n ; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FA_TB_V
`define SKY130_FD_SC_LS__FA_TB_V
/**
* fa: Full adder.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__fa.v"
module top();
// Inputs are registered
reg A;
reg B;
reg CIN;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire COUT;
wire SUM;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
CIN = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 CIN = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 CIN = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 CIN = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 CIN = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 CIN = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_ls__fa dut (.A(A), .B(B), .CIN(CIN), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .COUT(COUT), .SUM(SUM));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__FA_TB_V
|
#include <bits/stdc++.h> using namespace std; inline int read() { int n = 0, f = 1, ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { n = n * 10 + ch - 0 ; ch = getchar(); } return n * f; } char a[2000005], b[2000005]; int n; int c[2000005]; int get(int x) { int cur = 0, res = 0; for (int i = 1; i <= n; i++) { cur += x * c[i]; res = max(res, cur); if (cur < 0) cur = 0; } return res; } int main() { int s1 = 0, s2 = 0; n = read(); scanf( %s%s , a + 1, b + 1); for (int i = 1; i <= n; i++) { if (a[i] != b[i] && a[i] == 0 ) c[i] = -1, s1++; else if (a[i] != b[i] && a[i] == 1 ) c[i] = 1, s2++; } if (s1 != s2) { printf( -1 n ); return 0; } printf( %d n , max(get(1), get(-1))); return 0; } |
#include <bits/stdc++.h> using namespace std; struct Item { int x[3], y[3]; }; bool check(Item t); inline int Dist(int x1, int y1, int x2, int y2) { return (x1 - x2) * (x1 - x2) + (y1 - y2) * (y1 - y2); } int main() { Item it; for (int i = 0; i < 3; i++) cin >> it.x[i] >> it.y[i]; if (check(it)) cout << RIGHT n ; else { bool f = false; for (int i = 0; i < 3; i++) { Item tmp = it; tmp.x[i]--; if (check(tmp)) { f = true; break; } tmp.x[i] += 2; if (check(tmp)) { f = true; break; } } for (int i = 0; i < 3; i++) { Item tmp = it; tmp.y[i]--; if (check(tmp)) { f = true; break; } tmp.y[i] += 2; if (check(tmp)) { f = true; break; } } if (f == true) cout << ALMOST n ; else cout << NEITHER n ; } return 0; } bool check(Item t) { int d[3]; int xx[3], yy[3]; d[0] = Dist(t.x[0], t.y[0], t.x[1], t.y[1]); d[1] = Dist(t.x[0], t.y[0], t.x[2], t.y[2]); d[2] = Dist(t.x[1], t.y[1], t.x[2], t.y[3]); if (!d[0] || !d[1] || !d[2]) return false; if (d[0] + d[1] == d[2] || d[1] + d[2] == d[0] || d[0] + d[2] == d[1]) return false; xx[0] = t.x[0] - t.x[1]; yy[0] = t.y[0] - t.y[1]; xx[1] = t.x[0] - t.x[2]; yy[1] = t.y[0] - t.y[2]; xx[2] = t.x[1] - t.x[2]; yy[2] = t.y[1] - t.y[2]; if (xx[0] * xx[1] + yy[0] * yy[1] == 0 || xx[0] * xx[2] + yy[0] * yy[2] == 0 || xx[1] * xx[2] + yy[1] * yy[2] == 0) return true; else return false; } |
// N64 controller read command parser/receiver
//
// Inputs: clk_4M 4 MHz clock
// din Input data line
// enable Only samples when this is active
// Outputs: ctrl_state 32-bit register with controller state
// ctrl_clk Output clock, sample at negative edge
module n64_readcmd_rx(input wire clk_4M,
input wire din,
input wire enable,
output reg [31:0] ctrl_state,
output wire ctrl_clk);
// In sample window, we can read the value of the
// last 8 samples of the input signal.
// Sampling frequency is 4 MHz
wire [6:0] sampling_window;
shiftM #(.M(7), .INI(7'b1111111))
shift_sampling_reg (
.clk(clk_4M),
.enable(enable),
.serin(din),
.data(sampling_window)
);
// When we detect a falling edge at the oldest bit of
// the sampling window, we already have our desired
// bit at the newest position
wire [32:0] ctrl_state_dirty;
shiftM #(.M(33), .INI(33'b0))
shift_controller_state_reg (
.clk(~sampling_window[6]),
.enable(enable),
.serin(sampling_window[0]),
.data(ctrl_state_dirty)
);
// We need to update our 'ctrl_state' from 'ctrl_state_dirty'
// at the right time, that is, when we finish reading
// all of the 32 bits.
wire output_en;
counterM #(.M(32))
counter_signal_complete (
.clk(~sampling_window[6]),
.reset(ctrl_clk),
.empty(ctrl_clk)
);
initial ctrl_state = 32'b0;
always @(posedge ctrl_clk)
ctrl_state <= ctrl_state_dirty[32:1];
endmodule
|
`timescale 1ns / 1ps
/*
* File : FIFO_NoFull_Count.v
* Creator(s) : Grant Ayers ()
*
* Modification History:
* Rev Date Initials Description of Change
* 1.0 24-May-2010 GEA Initial design.
*
* Standards/Formatting:
* Verilog 2001, 4 soft tab, wide column.
*
* Description:
* A synchronous FIFO of variable data width and depth. 'enQ' is ignored when
* the FIFO is full and 'deQ' is ignored when the FIFO is empty. If 'enQ' and
* 'deQ' are asserted simultaneously, the FIFO is unchanged and the output data
* is the same as the input data.
*
* This FIFO is "First word fall-through" meaning data can be read without
* asserting 'deQ' by merely supplying an address. This data is only valid
* when not writing and not empty (i.e., valid when ~(empty | enQ)).
* When 'deQ' is asserted, the data is "removed" from the FIFO and one location
* is freed.
*
* Variation:
* - There is no output to indicate the FIFO is full.
* - Output 'count' indicates how many elements are in the FIFO, from 0 to 256
* (for 8-bit ADDR_WIDTH).
*/
module FIFO_NoFull_Count(clock, reset, enQ, deQ, data_in, data_out, empty, count);
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 8;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
input clock;
input reset;
input enQ;
input deQ;
input [(DATA_WIDTH-1):0] data_in;
output [(DATA_WIDTH-1):0] data_out;
output empty;
output reg [(ADDR_WIDTH):0] count; // How many elements are in the FIFO (0->256)
reg [(ADDR_WIDTH-1):0] enQ_ptr, deQ_ptr; // Addresses for reading from and writing to internal memory
wire [(ADDR_WIDTH-1):0] addr = (enQ) ? enQ_ptr : deQ_ptr;
assign empty = (count == 0);
wire full = (count == (1 << ADDR_WIDTH));
wire [(DATA_WIDTH-1):0] w_data_out;
assign data_out = (enQ & deQ) ? data_in : w_data_out;
wire w_enQ = enQ & ~(full | deQ); // Mask 'enQ' when the FIFO is full or reading
wire w_deQ = deQ & ~(empty | enQ); // Mask 'deQ' when the FIFO is empty or writing
always @(posedge clock) begin
if (reset) begin
enQ_ptr <= 0;
deQ_ptr <= 0;
count <= 0;
end
else begin
enQ_ptr <= (w_enQ) ? enQ_ptr + 1'b1 : enQ_ptr;
deQ_ptr <= (w_deQ) ? deQ_ptr + 1'b1 : deQ_ptr;
count <= (w_enQ ~^ w_deQ) ? count : ((w_enQ) ? count + 1'b1 : count - 1'b1);
end
end
RAM_SP_AR #(
.DATA_WIDTH (DATA_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH))
ram(
.clk (clock),
.addr (addr),
.we (w_enQ),
.din (data_in),
.dout (w_data_out)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; string s[1000]; scanf( %d , &n); for (int i = 0; i < n; i++) { cin >> s[i]; } char ch = s[0][0]; int flg = 0, cnc = 0, cnch = 0; char c = s[0][1]; if (c == ch) flg = 1; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (s[i][j] == c) { cnc++; } else if (s[i][j] == ch) { cnch++; } else flg = 1; } } if (cnch != 2 * n - 1) flg = 1; else if (n * n - cnch != cnc) flg = 1; for (int j = 0, i = 0; i < n / 2; i++) { if (s[i][i] == s[i][n - i - 1] && ch == s[i][i]) { } else flg = 1; } if (s[n / 2][n / 2] != ch) flg = 1; for (int j = 0, i = n - 1; i > n / 2; j++, i--) { if (s[i][j] == s[i][n - 1 - j] && ch == s[i][j]) { } else flg = 1; } if (flg) cout << NO << endl; else cout << YES << endl; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O311A_PP_SYMBOL_V
`define SKY130_FD_SC_LS__O311A_PP_SYMBOL_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o311a (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
input C1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O311A_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; inline int read() { int out = 0, fh = 1; char jp = getchar(); while ((jp > 9 || jp < 0 ) && jp != - ) jp = getchar(); if (jp == - ) fh = -1, jp = getchar(); while (jp >= 0 && jp <= 9 ) out = out * 10 + jp - 0 , jp = getchar(); return out * fh; } void print(int x) { if (x >= 10) print(x / 10); putchar( 0 + x % 10); } void write(int x, char c) { if (x < 0) putchar( - ), x = -x; print(x); putchar(c); } int phi(int x) { int res = x; for (int i = 2; i * i <= x; ++i) if (x % i == 0) { res /= i, res *= i - 1; while (x % i == 0) x /= i; } if (x > 1) res /= x, res *= x - 1; return res; } int mul(int a, int b, int Mod) { long long pr = 1LL * a * b; if (pr < Mod) return pr; return pr % Mod + Mod; } int fpow(int a, int b, int Mod) { int res = 1; while (b) { if (b & 1) res = mul(res, a, Mod); a = mul(a, a, Mod); b >>= 1; } return res; } int f(int x, int Mod) { if (x < Mod) return x; return x % Mod + Mod; } const int N = 1e5 + 10; int n, m, q, Mod[N], k = 0, a[N]; int query(int l, int r, int p) { if (l == r || p == k) return f(a[l], Mod[p]); int base = a[l], expo = query(l + 1, r, p + 1); return fpow(base, expo, Mod[p]); } signed main() { n = read(), m = read(); while (1) { Mod[++k] = m; if (m == 1) break; m = phi(m); } for (int i = 1; i <= n; ++i) a[i] = read(); q = read(); for (int i = 1; i <= q; ++i) { int l = read(), r = read(); int ans = query(l, r, 1) % Mod[1]; write(ans, n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; long long a[n]; for (long long i = 0; i <= n - 1; i++) cin >> a[i]; for (long long i = 0; i <= n - 1; i++) if ((a[i] % 2)) a[i] += 1; for (long long i = 0; i <= n - 1; i++) if (!(a[i] % 2)) a[i] -= 1; for (long long i = 0; i <= n - 1; i++) cout << a[i] << ; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND4B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__NAND4B_FUNCTIONAL_PP_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__nand4b (
Y ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y , D, C, B, not0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND4B_FUNCTIONAL_PP_V |
module xtime (
output [7:0] y,
input [7:0] x
);
wire [7:0] w;
assign w = x << 1;
//MUX MUX_1(.A(w), .B(w ^ 8'h1B), .S(x[7]), .O(y));
/*MUX
#(
.N(8)
)
MUX_1
(
.A(w),
.B(w ^ 8'h1B),
.S(x[7]),
.O(y)
);*/
assign y = x[7]? w ^ 8'h1B : w;
endmodule
module MixColumns(
x,
z);
input [127:0] x;
output [127:0] z;
/* function [7:0] xtime;
input [7:0] a;
begin
xtime = (a & 8'h80) ? ((a << 1) ^ 8'h1B) : (a << 1);
end
endfunction */
generate
genvar i;
for (i = 0; i < 4; i = i + 1) begin: gen_loop_enc
wire[7:0] a0, a1, a2, a3, temp;
wire[7:0] b0, b1, b2, b3;
wire[7:0] c0, c1, c2, c3;
assign a0 = x[8*(4*i+1)-1:8*(4*i+0)];
assign a1 = x[8*(4*i+2)-1:8*(4*i+1)];
assign a2 = x[8*(4*i+3)-1:8*(4*i+2)];
assign a3 = x[8*(4*i+4)-1:8*(4*i+3)];
assign temp = a0 ^ a1 ^ a2 ^ a3;
xtime xtime_0(c0, a0 ^ a1);
xtime xtime_1(c1, a1 ^ a2);
xtime xtime_2(c2, a2 ^ a3);
xtime xtime_3(c3, a3 ^ a0);
assign b0 = a0 ^ temp ^ c0;
assign b1 = a1 ^ temp ^ c1;
assign b2 = a2 ^ temp ^ c2;
assign b3 = a3 ^ temp ^ c3;
assign z[8*(4*i+1)-1:8*(4*i+0)] = b0;
assign z[8*(4*i+2)-1:8*(4*i+1)] = b1;
assign z[8*(4*i+3)-1:8*(4*i+2)] = b2;
assign z[8*(4*i+4)-1:8*(4*i+3)] = b3;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ull = unsigned long long; using ld = long double; const ll llinf = (1ll << 61) - 1; const double eps = 1e-6, ldeps = 1e-9; struct Dbg { static constexpr auto &os = cout; template <class C> static auto dud(C *x) -> decltype(os << *x, 0); template <class C> static char dud(...); template <class C> typename enable_if<sizeof dud<C>(0) != 1, Dbg &>::type operator<<( const C &x) { os << x; return *this; } template <class C> Dbg &dump(C b, C e) { *this << n[ ; int cur = 0; for (C i = b; i != e and cur < 26; i++, cur++) *this << , + 2 * (i == b) << *i; return *this << ] ; } template <class C> typename enable_if<sizeof dud<C>(0) == 1, Dbg &>::type operator<<( const C &x) { return dump(begin(x), end(x)); } template <class C, size_t X> typename enable_if<sizeof(C) != 1, Dbg &>::type operator<<(C (&x)[X]) { return dump(begin(x), end(x)); } template <class B, class C> Dbg &operator<<(const pair<B, C> &x) { return *this << { << x.first << , << x.second << } ; } template <class C, size_t Y> struct TP { void operator()(Dbg &os, const C &t) { TP<C, Y - 1>()(os, t); os << , << get<Y - 1>(t); } }; template <class C> struct TP<C, 1> { void operator()(Dbg &os, const C &t) { os << get<0>(t); } }; template <class... C> Dbg &operator<<(const tuple<C...> &t) { os << { , TP<decltype(t), sizeof...(C)>()(*this, t); return *this << } ; } Dbg &operator<<(ostream &(*x)(std::ostream &)) { os << x; return *this; } } dbg; void err(istringstream *iss) { delete iss; } template <class C, class... Args> void err(istringstream *iss, const C &val, const Args &...args) { string name; *iss >> name; if (name.back() == , ) name.pop_back(); dbg << name << = << val << ; , err(iss, args...); } int n, m, K, T, Q, cn; const int inf = 1000000007, mxnm = 1000005; vector<vector<int> > a; vector<pair<int, int> > pos[mxnm]; int maxrow[mxnm], maxcol[mxnm]; template <class C> C compress(vector<C> &v) { int sz = int(v.size()); vector<pair<C, int> > tmp(sz); for (int i = 0; i < sz; i++) { tmp[i] = {v[i], i}; } sort(begin(tmp), end(tmp)); int cur = 1; for (int i = 0; i < sz; i++) { cur += i and tmp[i].first != tmp[i - 1].first; v[tmp[i].second] = cur; } return cur; } int os[mxnm], lastrow[mxnm], lastcol[mxnm]; class DSU { vector<int> dsupar, siz; public: int cntDSU; void reset() { int sz = int(dsupar.size()); for (int i = 0; i < sz; i++) dsupar[i] = i, siz[i] = 1; } DSU(int N, int noOfSets = -1) { dsupar.resize(N + 5), siz.resize(N + 5); reset(); cntDSU = noOfSets == -1 ? N : noOfSets; } int find(int x) { return dsupar[x] == x ? x : dsupar[x] = find(dsupar[x]); } void union_(int u, int v) { if ((u = find(u)) == (v = find(v))) return; if (siz[u] < siz[v]) swap(u, v); dsupar[v] = u, siz[u] += siz[v], siz[v] = 0, os[u] = max(os[u], os[v]); cntDSU--; } } dsu(mxnm); signed main() { ios::sync_with_stdio(0); cin.tie(NULL); cout.precision(11); cin >> n >> m; a.resize(n + 5, vector<int>(m + 5)); vector<int> a2(n * m); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> a2[i * m + j]; } } int o = compress(a2); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { pos[a2[i * m + j]].push_back({i, j}); a[i][j] = a2[i * m + j]; } } memset(lastrow, -1, sizeof(lastrow)), memset(lastcol, -1, sizeof(lastcol)); for (int i = 1; i <= o; i++) { for (auto &j : pos[i]) { os[j.first * m + j.second] = max(maxrow[j.first], maxcol[j.second]) + 1; } for (auto &j : pos[i]) { if (lastrow[j.first] == -1) lastrow[j.first] = j.second; else dsu.union_(j.first * m + j.second, j.first * m + lastrow[j.first]); if (lastcol[j.second] == -1) lastcol[j.second] = j.first; else dsu.union_(j.first * m + j.second, lastcol[j.second] * m + j.second); } for (auto &j : pos[i]) { a[j.first][j.second] = os[dsu.find(j.first * m + j.second)]; lastrow[j.first] = lastcol[j.second] = -1; } for (auto &j : pos[i]) { maxrow[j.first] = max(maxrow[j.first], a[j.first][j.second]), maxcol[j.second] = max(maxcol[j.second], a[j.first][j.second]); } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cout << a[i][j] << n [j == m - 1]; } } } |
#include <bits/stdc++.h> using namespace std; const int N = 1005; long long ara[N]; int main() { long long n, m; cin >> n >> m; for (long long i = 0; i < m; ++i) { long long x; cin >> x; ++ara[x]; } vector<long long> v; for (long long i = 1; i <= 100; ++i) { if (ara[i] != 0) v.push_back(ara[i]); } long long mx = 0; for (long long i = 1; i <= 100; ++i) { long long s = 0; for (long long j = 0; j < v.size(); ++j) { s += v[j] / i; } if (s >= n) mx = max(mx, i); } cout << mx; } |
#include <bits/stdc++.h> using namespace std; long long isPalindrome(string str) { long long l = 0; long long h = str.length() - 1; while (h > l) { if (str[l++] != str[h--]) { return -1; } } return 1; } int32_t main() { string s; cin >> s; long long n = s.size(); string ans = YES ; for (long long i = 0; i < n; i++) { if (s[i] == A || s[i] == H || s[i] == I || s[i] == M || s[i] == O || s[i] == T || s[i] == U || s[i] == V || s[i] == W || s[i] == X || s[i] == Y ) { } else { ans = NO ; } } if (isPalindrome(s) == 1 && ans == YES ) { cout << ans << endl; ; } else { cout << NO << endl; ; } } |
#include <bits/stdc++.h> using namespace std; int n, a[100005]; long long b[100005], dpMax[100005], dpMin[100005], ans = (1ll << 63); void setup() { cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 1; i <= n - 1; i++) b[i] = abs(a[i] - a[i + 1]); n--; } void xuly() { for (int i = n; i >= 1; i--) { dpMax[i] = -min(dpMin[i + 1], 0ll) + b[i]; dpMin[i] = -max(dpMax[i + 1], 0ll) + b[i]; ans = max(ans, dpMax[i]); } cout << ans; } int main() { iostream::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); setup(); xuly(); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long int n, k, j = 0, oo = 1; cin >> n >> k; while (k != j) { oo *= 10; j++; } long long int prod = oo * n; while (oo != n) { if (oo > n) { oo %= n; if (oo == 0) oo = n; } else { n %= oo; if (n == 0) n = oo; } } cout << prod / oo; return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [31:0] in_a;
reg [31:0] in_b;
reg [31:0] e,f,g,h;
always @ (/*AS*/in_a) begin
e = in_a;
f = {e[15:0], e[31:16]};
g = {f[15:0], f[31:16]};
h = {g[15:0], g[31:16]};
end
// verilator lint_off UNOPTFLAT
reg [31:0] e2,f2,g2,h2;
always @ (/*AS*/f2) begin
h2 = {g2[15:0], g2[31:16]};
g2 = {f2[15:0], f2[31:16]};
end
always @ (/*AS*/in_a) begin
f2 = {e2[15:0], e2[31:16]};
e2 = in_a;
end
// verilator lint_on UNOPTFLAT
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
//$write("%d %x %x\n", cyc, h, h2);
if (h != h2) $stop;
if (cyc==1) begin
in_a <= 32'h89a14fab;
in_b <= 32'h7ab512fa;
end
if (cyc==2) begin
in_a <= 32'hf4c11a42;
in_b <= 32'h359967c6;
if (h != 32'h4fab89a1) $stop;
end
if (cyc==3) begin
if (h != 32'h1a42f4c1) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
//altiobuf_out CBX_AUTO_BLACKBOX="ALL" CBX_SINGLE_OUTPUT_FILE="ON" DEVICE_FAMILY="Cyclone V" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=1 OPEN_DRAIN_OUTPUT="FALSE" PSEUDO_DIFFERENTIAL_MODE="TRUE" USE_DIFFERENTIAL_MODE="TRUE" USE_OE="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN1="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN2="FALSE" USE_TERMINATION_CONTROL="FALSE" datain dataout dataout_b
//VERSION_BEGIN 16.1 cbx_altiobuf_out 2016:10:24:15:04:16:SJ cbx_mgl 2016:10:24:15:05:03:SJ cbx_stratixiii 2016:10:24:15:04:16:SJ cbx_stratixv 2016:10:24:15:04:16:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Intel and sold by Intel or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = cyclonev_io_obuf 2 cyclonev_pseudo_diff_out 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module hps_sdram_p0_clock_pair_generator
(
datain,
dataout,
dataout_b) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
output [0:0] dataout;
output [0:0] dataout_b;
wire [0:0] wire_obuf_ba_o;
wire [0:0] wire_obuf_ba_oe;
wire [0:0] wire_obufa_o;
wire [0:0] wire_obufa_oe;
wire [0:0] wire_pseudo_diffa_o;
wire [0:0] wire_pseudo_diffa_obar;
wire [0:0] wire_pseudo_diffa_oebout;
wire [0:0] wire_pseudo_diffa_oein;
wire [0:0] wire_pseudo_diffa_oeout;
wire [0:0] oe_w;
cyclonev_io_obuf obuf_ba_0
(
.i(wire_pseudo_diffa_obar),
.o(wire_obuf_ba_o[0:0]),
.obar(),
.oe(wire_obuf_ba_oe[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obuf_ba_0.bus_hold = "false",
obuf_ba_0.open_drain_output = "false",
obuf_ba_0.lpm_type = "cyclonev_io_obuf";
assign
wire_obuf_ba_oe = {(~ wire_pseudo_diffa_oebout[0])};
cyclonev_io_obuf obufa_0
(
.i(wire_pseudo_diffa_o),
.o(wire_obufa_o[0:0]),
.obar(),
.oe(wire_obufa_oe[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_0.bus_hold = "false",
obufa_0.open_drain_output = "false",
obufa_0.lpm_type = "cyclonev_io_obuf";
assign
wire_obufa_oe = {(~ wire_pseudo_diffa_oeout[0])};
cyclonev_pseudo_diff_out pseudo_diffa_0
(
.dtc(),
.dtcbar(),
.i(datain),
.o(wire_pseudo_diffa_o[0:0]),
.obar(wire_pseudo_diffa_obar[0:0]),
.oebout(wire_pseudo_diffa_oebout[0:0]),
.oein(wire_pseudo_diffa_oein[0:0]),
.oeout(wire_pseudo_diffa_oeout[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dtcin(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
assign
wire_pseudo_diffa_oein = {(~ oe_w[0])};
assign
dataout = wire_obufa_o,
dataout_b = wire_obuf_ba_o,
oe_w = 1'b1;
endmodule //hps_sdram_p0_clock_pair_generator
//VALID FILE
|
#include <bits/stdc++.h> using namespace std; long long int mod = 1000000007; int main() { ios_base ::sync_with_stdio(false); cin.tie(NULL); long long int n; cin >> n; if (n == 1) { cout << 2; return 0; } if (n == 2) { cout << 3; return 0; } long long int curr = 2, line = 3, to = 2; while (to < n) { line++; to += curr; if (to >= n) { cout << line; return 0; } line++; to += (curr); curr++; if (to >= n) { cout << line; return 0; } } } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long x, y, n, m, t, q, a, b, count = 0; cin >> n >> m; long long arr[n]; for (x = 0; x < n; x++) cin >> arr[x]; a = 0; for (x = 0; x < n; x++) { a = a + arr[x]; cout << a / m << ; a = a % m; } } |
#include <bits/stdc++.h> using namespace std; int main() { char s[110]; while (scanf( %s , s) != EOF) { int l = strlen(s); int ans = 0; for (int i = 0; i < l; i++) { if (s[i] == Q ) { for (int j = i + 1; j < l; j++) { if (s[j] == A ) { for (int k = j + 1; k < l; k++) { if (s[k] == Q ) { ans++; } } } } } } printf( %d n , ans); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); long long w, m; cin >> w >> m; vector<int> f; while (m) { f.push_back(m % w); m /= w; } f.push_back(0); f.push_back(0); reverse(f.begin(), f.end()); for (int i = f.size() - 1; i >= 0; i--) { if (i > 1) f[i - 1] += f[i] / w; f[i] %= w; if (f[i] == 0) continue; if (f[i] == 1) continue; if (f[i] == w - 1) { f[i - 1]++; continue; } cout << NO ; return 0; } cout << YES ; } |
#include <bits/stdc++.h> using namespace std; long long a[100000], i, n, m, k; set<int> s; int main() { cin >> n >> k; for (i = 0; i < n; i++) { cin >> a[i]; } sort(a, a + n); s.insert(a[0]); for (i = 1; i < n; i++) { m = s.size(); if (a[i] % k != 0) { s.insert(a[i]); } else { s.insert(a[i] / k); if (m != s.size()) { s.erase(a[i] / k); s.insert(a[i]); } } } cout << s.size(); } |
#include <bits/stdc++.h> using namespace std; const int T = 1e3 + 5; int g[T][T]; void add(int a, int b) { g[a][b] = g[b][a] = 1; } int last, K, a, b, i, j, N; int main() { cin >> K; add(0, 2); add(0, 3); for (i = 2; i <= 30; i++) { add(2 * i, 2 * i - 1); add(2 * i, 2 * i - 2); add(2 * i + 1, 2 * i - 1); add(2 * i + 1, 2 * i - 2); } N = 2 * 30 + 1; for (i = 30; i >= 0; i--) if (K & (1 << (i - 1))) { last = 2 * i; for (j = i; j < 30; j++) { N++; add(N, last); last = N; } add(last, 1); } cout << N + 1 << endl; for (i = 0; i <= N; i++) { for (j = 0; j <= N; j++) if (g[i][j]) printf( %c , Y ); else printf( %c , N ); printf( n ); } } |
#include <bits/stdc++.h> using namespace std; int dpr[107]; int dps[107]; int dpc[107]; int a[107]; int main() { int n; scanf( %d , &n); for (int i = 1; i < n + 1; i++) scanf( %d , a + i); dpr[1] = 1; dps[1] = (a[1] == 2 || a[1] == 3) ? 0 : -1; dpc[1] = (a[1] == 1 || a[1] == 3) ? 0 : -1; for (int i = 2; i < n + 1; i++) { dpr[i] = dpr[i - 1]; if (dps[i - 1] != -1) dpr[i] = min(dpr[i], dps[i - 1]); if (dpc[i - 1] != -1) dpr[i] = min(dpr[i], dpc[i - 1]); dpr[i] += 1; if (a[i] != 2 && a[i] != 3) dps[i] = -1; else { dps[i] = dpr[i - 1]; if (dpc[i - 1] != -1) dps[i] = min(dps[i], dpc[i - 1]); } if (a[i] != 1 && a[i] != 3) dpc[i] = -1; else { dpc[i] = dpr[i - 1]; if (dps[i - 1] != -1) dpc[i] = min(dpc[i], dps[i - 1]); } } int ans = 200; ans = min(ans, dpr[n]); if (dps[n] != -1) ans = min(ans, dps[n]); if (dpc[n] != -1) ans = min(ans, dpc[n]); printf( %d n , ans); } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__TAP_BEHAVIORAL_PP_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__tap (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAP_BEHAVIORAL_PP_V |
//-----------------------------------------------------------------------------
//-- Microbio. Mini procesador hola-mundo
//-----------------------------------------------------------------------------
//-- (C) BQ November 2015. Written by Juan Gonzalez
//-----------------------------------------------------------------------------
//----- DOCUMENTACION
//-- Formato instrucciones (8 bits)
//-- CO (2 bits) DAT (6 bits)
//--
//-- Memoria de 64 posiciones (direcciones de 6 bits)
//-- Anchura de los datos: 8 bits
//--
//-- Codigos de operacion
//-- 00 --> WAIT (consume ciclos sin hacer nada)
//-- 01 --> HALT (Parar. Enciende led verde)
//-- 10 --> LEDS (Establecer valor en los leds)
//-- 11 --> JP (Saltar a la direccion indicada)
//------------------------------------------------------------------------------
`default_nettype none
`include "divider.vh"
//-- Procesador microbio
module microbio (input wire clk, //-- Reloj del sistema
input wire rstn_ini, //-- Reset
output wire [3:0] leds, //-- leds
output wire stop); //-- Indicador de stop
//-- Parametro: Tiempo de espera para la instruccion WAIT
parameter WAIT_DELAY = `T_200ms;
//-- Parametro: fichero con el programa a cargar en la rom
parameter ROMFILE = "prog.list";
//-- Tamaño de la memoria ROM a instanciar
localparam AW = 6; //-- Anchura del bus de direcciones
localparam DW = 8; //-- Anchura del bus de datos
//-- Codigo de operacion de las instrucciones
localparam WAIT = 2'b00;
localparam HALT = 2'b01;
localparam LEDS = 2'b10;
localparam JP = 2'b11;
//-- Instanciar la memoria ROM
wire [DW-1: 0] data;
wire [AW-1: 0] addr;
genrom
#( .ROMFILE(ROMFILE),
.AW(AW),
.DW(DW))
ROM (
.clk(clk),
.addr(addr),
.data(data)
);
//-- Registrar la señal de reset
reg rstn = 0;
always @(posedge clk)
rstn <= rstn_ini;
//-- Declaracion de las microordenes
reg cp_inc = 0; //-- Incrementar contador de programa
reg cp_load = 0; //-- Cargar el contador de programa
reg ri_load = 0; //-- Cargar una instruccion en el registro de instruccion
reg halt = 0; //-- Instruccion halt ejecutada
reg leds_load = 0; //-- Mostrar un valor por los leds
//-- Contador de programa
reg [AW-1: 0] cp;
always @(posedge clk)
if (!rstn)
cp <= 0;
else if (cp_load)
cp <= DAT;
else if (cp_inc)
cp <= cp + 1;
assign addr = cp;
//-- Registro de instruccion
reg [DW-1: 0] ri;
//-- Descomponer la instruccion en los campos CO y DAT
wire [1:0] CO = ri[7:6]; //-- Codigo de operacion
wire [5:0] DAT = ri[5:0]; //-- Campo de datos
always @(posedge clk)
if (!rstn)
ri <= 0;
else if (ri_load)
ri <= data;
//-- Registro de stop
//-- Se pone a 1 cuando se ha ejecutado una instruccion de HALT
reg reg_stop;
always @(posedge clk)
if (!rstn)
reg_stop <= 0;
else if (halt)
reg_stop <= 1;
//-- Registro de leds
reg [3:0] leds_r;
always @(posedge clk)
if (!rstn)
leds_r <= 0;
else if (leds_load)
leds_r <= DAT[3:0];
assign leds = leds_r;
//-- Mostrar la señal de stop por el led verde
assign stop = reg_stop;
//-------- Debug
//-- Sacar codigo de operacion por leds
//assign leds = CO;
/*-- Hacer parpadear el led de stop
reg cont=0;
always @(posedge clk)
if (clk_tic)
cont <= cont + 1;
assign stop = cont;
*/
//----------- UNIDAD DE CONTROL
localparam INIT = 0;
localparam FETCH = 1;
localparam EXEC = 2;
//-- Estado del automata
reg [1:0] state;
reg [1:0] next_state;
//-- Transiciones de estados
wire clk_tic;
always @(posedge clk)
if (!rstn)
state <= INIT;
else
state <= next_state;
//-- Generacion de microordenes
//-- y siguientes estados
always @(*) begin
//-- Valores por defecto
next_state = state; //-- Por defecto permanecer en el mismo estado
cp_inc = 0;
cp_load = 0;
ri_load = 0;
halt = 0;
leds_load = 0;
case (state)
//-- Estado inicial y de reposo
INIT:
next_state = FETCH;
//-- Ciclo de captura: obtener la siguiente instruccion
//-- de la memoria
FETCH: begin
cp_inc = 1; //-- Incrementar CP (en el siguiente estado)
ri_load = 1; //-- Cargar la instruccion (en el siguiente estado)
next_state = EXEC;
end
//-- Ciclo de ejecucion
EXEC: begin
next_state = FETCH;
//-- Ejecutar la instruccion
case (CO)
//-- Instruccion HALT
HALT: begin
halt = 1; //-- Activar microorden de halt
next_state = EXEC; //-- Permanecer en este estado indefinidamente
end
//-- Instruccion WAIT
WAIT: begin
//-- Mientras no se active clk_tic, se sigue en el mismo
//-- estado de ejecucion
if (clk_tic) next_state = FETCH;
else next_state = EXEC;
end
//-- Instruccion LEDs
LEDS:
leds_load = 1; //-- Microorden de carga en el registro de leds
//-- Instruccion de Salto
JP: begin
cp_load = 1; //-- Microorden de carga del CP
next_state = INIT; //-- Realizar un ciclo de reposo para
//-- que se cargue CP antes del estado FETCH
end
endcase
end
endcase
end
//-- Divisor para marcar la duracion de cada estado del automata
dividerp1 #(WAIT_DELAY)
TIMER0 (
.clk(clk),
.clk_out(clk_tic)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); long long n_Cases = 1; for (long long case_i = 1; case_i <= n_Cases; case_i++) { long long up, down; cin >> up >> down; long long n = up + down + 1; for (long long i = 1; i <= up; i++) cout << i << ; cout << n << ; for (long long j = n - 1; j >= n - down; j--) cout << j << ; cout << n ; } return 0; } |
//////////////////////////////////////////////////////////////////////////////////
// AXI4CommandDivider for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Kibin Park <>
// Yong Ho Song <>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Kibin Park <>
//
// Project Name: Cosmos OpenSSD
// Design Name: AXI4 command divider
// Module Name: AXI4CommandDivider
// File Name: AXI4CommandDivider.v
//
// Version: v1.0.0
//
// Description: Divides a long burst into multiple smaller bursts
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module AXI4CommandDivider
#
(
parameter AddressWidth = 32 ,
parameter DataWidth = 32 ,
parameter InnerIFLengthWidth = 16 ,
parameter MaxDivider = 16
)
(
ACLK ,
ARESETN ,
SRCADDR ,
SRCLEN ,
SRCVALID ,
SRCREADY ,
SRCREADYCOND,
DIVADDR ,
DIVLEN ,
DIVVALID ,
DIVREADY ,
DIVFLUSH
);
input ACLK ;
input ARESETN ;
input [AddressWidth - 1:0] SRCADDR ;
input [InnerIFLengthWidth - 1:0] SRCLEN ;
input SRCVALID ;
output SRCREADY ;
input SRCREADYCOND;
output [AddressWidth - 1:0] DIVADDR ;
output [7:0] DIVLEN ;
output DIVVALID ;
input DIVREADY ;
output DIVFLUSH ;
reg [7:0] rDivLen ;
reg rDivValid ;
reg rDivFlush ;
localparam State_Idle = 2'b00 ;
localparam State_Dividing = 2'b01 ;
localparam State_Request = 2'b11 ;
reg [1:0] rCurState ;
reg [1:0] rNextState ;
reg [AddressWidth - 1:0] rAddress ;
reg [InnerIFLengthWidth:0] rLength ;
reg [$clog2(MaxDivider):0] rDivider ;
wire wDivisionNotNeeded ;
wire wDivisionNeeded ;
always @ (posedge ACLK)
if (!ARESETN)
rCurState <= State_Idle;
else
rCurState <= rNextState;
assign wDivisionNotNeeded = (rLength >= rDivider) ;
assign wDivisionNeeded = (rLength < rDivider) ;
always @ (*)
case (rCurState)
State_Idle:
if (SRCVALID && (SRCLEN != {(InnerIFLengthWidth){1'b0}}))
rNextState <= State_Dividing;
else
rNextState <= State_Idle;
State_Dividing:
rNextState <= (wDivisionNotNeeded)?State_Request:State_Dividing;
State_Request:
if (DIVREADY)
begin
if (rLength == 0)
rNextState <= State_Idle;
else
rNextState <= State_Dividing;
end
else
rNextState <= State_Request;
default:
rNextState <= State_Idle;
endcase
assign SRCREADY = (rCurState == State_Idle) && SRCREADYCOND;
assign DIVADDR = rAddress;
assign DIVLEN = rDivLen;
always @ (posedge ACLK)
if (!ARESETN)
rAddress <= 8'b0;
else
case (rCurState)
State_Idle:
if (SRCVALID)
rAddress <= SRCADDR;
State_Request:
if (DIVREADY)
rAddress <= rAddress + (rDivider << ($clog2(DataWidth/8 - 1)));
endcase
always @ (posedge ACLK)
if (!ARESETN)
rLength <= 8'b0;
else
case (rCurState)
State_Idle:
if (SRCVALID)
rLength <= SRCLEN;
State_Dividing:
if (wDivisionNotNeeded)
rLength <= rLength - rDivider;
endcase
always @ (posedge ACLK)
case (rCurState)
State_Idle:
rDivider <= MaxDivider;
State_Dividing:
if (wDivisionNeeded)
rDivider <= rDivider >> 1'b1;
endcase
always @ (posedge ACLK)
if (!ARESETN)
rDivLen <= 8'b0;
else
case (rCurState)
State_Dividing:
if (wDivisionNotNeeded)
rDivLen <= rDivider - 1'b1;
endcase
assign DIVVALID = rDivValid;
always @ (posedge ACLK)
if (!ARESETN)
rDivValid <= 1'b0;
else
if (!rDivValid && (rCurState == State_Dividing) && wDivisionNotNeeded)
rDivValid <= 1'b1;
else if (rDivValid && DIVREADY)
rDivValid <= 1'b0;
always @ (*)
case (rCurState)
State_Idle:
rDivFlush <= 1'b1;
State_Request:
if (!DIVREADY) // WCmdQ is Full
rDivFlush <= 1'b1;
else
rDivFlush <= 1'b0;
default:
rDivFlush <= 1'b0;
endcase
assign DIVFLUSH = rDivFlush;
endmodule
|
/**
* @note:
* 1. size of image must be integral multiple of C_M_AXI_DATA_WIDTH * C_M_AXI_BURST_LEN.
* 2. the sof [start of frame] must be 1'b1 for first image data.
*/
module FIFO2MM #
(
parameter integer C_DATACOUNT_BITS = 12,
// Burst Length. Supports 1, 2, 4, 8, 16, 32, 64, 128, 256 burst lengths
parameter integer C_M_AXI_BURST_LEN = 16,
// Width of Address Bus
parameter integer C_M_AXI_ADDR_WIDTH = 32,
// Width of Data Bus
parameter integer C_M_AXI_DATA_WIDTH = 32,
// Image width/height pixel number bits
parameter integer C_IMG_WBITS = 12,
parameter integer C_IMG_HBITS = 12,
parameter integer C_ADATA_PIXELS = 4
)
(
input wire soft_resetn,
output wire resetting,
input wire [C_IMG_WBITS-1:0] img_width,
input wire [C_IMG_HBITS-1:0] img_height,
//input wire sof,
input wire [C_M_AXI_DATA_WIDTH-1 : 0] din,
//input wire empty,
output wire rd_en,
input wire [C_DATACOUNT_BITS-1:0] rd_data_count,
output wire frame_pulse,
input wire [C_M_AXI_ADDR_WIDTH-1 : 0] base_addr,
input wire M_AXI_ACLK,
input wire M_AXI_ARESETN,
output wire [C_M_AXI_ADDR_WIDTH-1 : 0] M_AXI_AWADDR,
output wire [7 : 0] M_AXI_AWLEN,
output wire [2 : 0] M_AXI_AWSIZE,
output wire [1 : 0] M_AXI_AWBURST,
output wire M_AXI_AWLOCK,
output wire [3 : 0] M_AXI_AWCACHE,
output wire [2 : 0] M_AXI_AWPROT,
output wire [3 : 0] M_AXI_AWQOS,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
output wire [C_M_AXI_DATA_WIDTH-1 : 0] M_AXI_WDATA,
output wire [C_M_AXI_DATA_WIDTH/8-1 : 0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
input wire [1 : 0] M_AXI_BRESP,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
output wire write_resp_error
);
function integer clogb2 (input integer bit_depth);
begin
for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
bit_depth = bit_depth >> 1;
end
endfunction
// C_TRANSACTIONS_NUM is the width of the index counter for
// number of write or read transaction.
localparam integer C_TRANSACTIONS_NUM = clogb2(C_M_AXI_BURST_LEN-1);
//Burst size in bytes
localparam integer C_BURST_SIZE_BYTES = C_M_AXI_BURST_LEN * C_M_AXI_DATA_WIDTH/8;
// @note: do not cause bursts across 4K address boundaries.
reg [C_M_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
reg axi_awvalid;
reg axi_wlast;
reg axi_bready;
//write beat count in a burst
reg [C_TRANSACTIONS_NUM : 0] write_index;
reg start_burst_pulse;
reg burst_active;
wire burst_done;
wire wnext;
reg need_data;
reg r_dvalid;
reg [C_IMG_WBITS-1:0] r_img_col_idx;
reg [C_IMG_HBITS-1:0] r_img_row_idx;
wire final_data;
assign final_data = (r_img_col_idx == 0 && r_img_row_idx == 0);
assign wnext = M_AXI_WREADY & M_AXI_WVALID;
assign burst_done = M_AXI_BVALID && M_AXI_BREADY;
/// resetting
reg soft_resetn_d1;
always @ (posedge M_AXI_ACLK) begin
if (M_AXI_ARESETN == 1'b0) soft_resetn_d1 <= 1'b0;
else soft_resetn_d1 <= soft_resetn;
end
reg r_soft_resetting;
assign resetting = r_soft_resetting;
always @ (posedge M_AXI_ACLK) begin
if (M_AXI_ARESETN == 1'b0)
r_soft_resetting <= 1'b1;
else if (~(start_burst_pulse | burst_active))
r_soft_resetting <= 1'b0;
else if (burst_done)
r_soft_resetting <= 1'b0;
else if (~soft_resetn && soft_resetn_d1) /// soft_resetn_negedge
r_soft_resetting <= 1'b1;
else
r_soft_resetting <= r_soft_resetting;
end
// I/O Connections assignments
reg r_frame_pulse;
assign frame_pulse = r_frame_pulse;
always @ (posedge M_AXI_ACLK) begin
if (M_AXI_ARESETN == 0)
r_frame_pulse <= 1'b0;
else if (burst_done && final_data)
r_frame_pulse <= 1'b1;
else
r_frame_pulse <= 1'b0;
end
wire try_read_en;
assign try_read_en = need_data && (~r_dvalid | M_AXI_WREADY);
assign rd_en = try_read_en && ~resetting;
always @(posedge M_AXI_ACLK) begin
if (M_AXI_ARESETN == 0)
r_dvalid <= 1'b0;
else if (try_read_en)
r_dvalid <= 1'b1;
else if (M_AXI_WREADY)
r_dvalid <= 1'b0;
else
r_dvalid <= r_dvalid;
end
assign M_AXI_AWADDR = axi_awaddr;
assign M_AXI_AWLEN = C_M_AXI_BURST_LEN - 1;
assign M_AXI_AWSIZE = clogb2((C_M_AXI_DATA_WIDTH/8)-1);
//INCR burst type is usually used, except for keyhole bursts
assign M_AXI_AWBURST = 2'b01;
assign M_AXI_AWLOCK = 1'b0;
//write response must be sended by terminal device, i.e. memory or its' controller
assign M_AXI_AWCACHE = 4'b0010;
assign M_AXI_AWPROT = 3'h0;
assign M_AXI_AWQOS = 4'h0;
assign M_AXI_AWVALID = axi_awvalid;
//Write Data(W)
assign M_AXI_WDATA = din;
//All bursts are complete and aligned
assign M_AXI_WSTRB = {(C_M_AXI_DATA_WIDTH/8){1'b1}};
assign M_AXI_WLAST = axi_wlast;
assign M_AXI_WVALID = r_dvalid | r_soft_resetting;
//Write Response (B)
assign M_AXI_BREADY = axi_bready;
always @ (posedge M_AXI_ACLK) begin
if (M_AXI_ARESETN == 1'b0)
axi_bready <= 1'b0;
else if (M_AXI_BVALID)
axi_bready <= 1'b1;
else
axi_bready <= 1'b0;
end
//--------------------
//Write Address Channel
//--------------------
always @(posedge M_AXI_ACLK) begin
if (M_AXI_ARESETN == 0)
axi_awvalid <= 1'b0;
else if (~axi_awvalid && start_burst_pulse)
axi_awvalid <= 1'b1;
else if (M_AXI_AWREADY && axi_awvalid)
axi_awvalid <= 1'b0;
else
axi_awvalid <= axi_awvalid;
end
always @(posedge M_AXI_ACLK) begin
if (M_AXI_ARESETN == 0)
axi_awaddr <= 'b0;
else if (start_burst_pulse) begin
if (final_data)
axi_awaddr <= base_addr;
else
axi_awaddr <= axi_awaddr + C_BURST_SIZE_BYTES;
end
else
axi_awaddr <= axi_awaddr;
end
//--------------------
//Write Data Channel
//--------------------
always @(posedge M_AXI_ACLK) begin
if (M_AXI_ARESETN == 0)
need_data <= 1'b0;
else if (~need_data && M_AXI_AWREADY && M_AXI_AWVALID)
need_data <= 1'b1;
else if (wnext && (write_index == 1))
need_data <= 1'b0;
else
need_data <= need_data;
end
always @(posedge M_AXI_ACLK) begin
if (M_AXI_ARESETN == 0)
axi_wlast <= 1'b0;
else if (C_M_AXI_BURST_LEN == 1)
axi_wlast <= 1'b1;
else if (wnext)
axi_wlast <= (write_index == 1);
else
axi_wlast <= axi_wlast;
end
always @(posedge M_AXI_ACLK) begin
if (M_AXI_ARESETN == 1'b0)
write_index <= 0;
else if (start_burst_pulse == 1'b1)
write_index <= C_M_AXI_BURST_LEN-1;
else if (wnext && (write_index != 0))
write_index <= write_index - 1;
else
write_index <= write_index;
end
//----------------------------
//Write Response (B) Channel
//----------------------------
//Interface response error flags
assign write_resp_error = M_AXI_BVALID & M_AXI_BRESP[1];
always @(posedge M_AXI_ACLK) begin
if (M_AXI_ARESETN == 1'b0)
start_burst_pulse <= 1'b0;
else if (~start_burst_pulse && ~burst_active
&& soft_resetn
&& (rd_data_count >= C_M_AXI_BURST_LEN)
)
start_burst_pulse <= 1'b1;
else
start_burst_pulse <= 1'b0;
end
always @(posedge M_AXI_ACLK) begin
if (M_AXI_ARESETN == 1'b0)
burst_active <= 1'b0;
else if (start_burst_pulse)
burst_active <= 1'b1;
else if (burst_done)
burst_active <= 0;
else
burst_active <= burst_active;
end
always @(posedge M_AXI_ACLK) begin
if (M_AXI_ARESETN == 1'b0 || soft_resetn == 1'b0) begin
r_img_col_idx <= 0;
r_img_row_idx <= 0;
end
else if (start_burst_pulse && final_data) begin
r_img_col_idx <= img_width - C_ADATA_PIXELS;
r_img_row_idx <= img_height - 1;
end
else if (wnext) begin
if (r_img_col_idx != 0) begin
r_img_col_idx <= r_img_col_idx - C_ADATA_PIXELS;
r_img_row_idx <= r_img_row_idx;
end
else if (r_img_row_idx != 0) begin
r_img_col_idx <= img_width - C_ADATA_PIXELS;
r_img_row_idx <= r_img_row_idx - 1;
end
else begin /// @note: keep zero, reserve for start_burst_pulse
r_img_col_idx <= r_img_col_idx;
r_img_row_idx <= r_img_row_idx;
end
end
else begin
r_img_col_idx <= r_img_col_idx;
r_img_row_idx <= r_img_row_idx;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1000000007; const long long maxn = 1e5 + 10; vector<long long> a[maxn]; long long lo[maxn], hi[maxn]; const long long inf = 1e15; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout << fixed << setprecision(9); long long n; cin >> n; long long cnt = 0; map<long long, long long> mp; vector<long long> keep; for (long long i = 0; i < n; ++i) { long long len; cin >> len; bool ok = false; long long mn = inf; long long mx = -inf; for (long long j = 0; j < len; ++j) { long long cur; cin >> cur; a[i].push_back(cur); if (cur > mn) ok = true; mn = min(mn, cur); mx = max(mx, cur); } lo[i] = mn; hi[i] = mx; if (ok) { ++cnt; hi[i] = inf; } else { keep.push_back(mx); } } sort(keep.begin(), keep.end()); long long res = 0; for (long long i = 0; i < n; ++i) { if (hi[i] == inf) { res += n; } else { long long cur = cnt; auto it = upper_bound(keep.begin(), keep.end(), lo[i]); if (it != keep.end()) { long long ind = it - keep.begin(); long long is = (long long)keep.size() - ind; cur += is; } res += cur; } } cout << res << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main(int argc, char* argv[]) { ios_base::sync_with_stdio(false); cin.tie(NULL); long long i, t, n, com, midc; cin >> n; map<int, int> m; set<int> s; vector<int> x(n); vector<int> a(3); for (i = 0; i < n; i++) { cin >> x[i]; m[x[i]]++; s.insert(x[i]); } t = s.size(); if (t == 1) { cout << n << endl; for (i = 0; i < n; i++) cout << x[i] << ; cout << endl; } else if (t == 2) { i = 0; for (set<int>::const_iterator it = s.begin(); it != s.end(); it++) { a[i] = *it; i++; } if (abs(a[0] - a[1]) == 1) { cout << n << endl; for (i = 0; i < n; i++) cout << x[i] << ; cout << endl; } else { com = min(m[a[0]], m[a[1]]); cout << n - (2 * com) << endl; ; for (i = 0; i < (2 * com); i++) cout << a[0] + 1 << ; for (i = 0; i < m[a[0]] - com; i++) cout << a[0] << ; for (i = 0; i < m[a[1]] - com; i++) cout << a[1] << ; cout << endl; } } else { i = 0; for (set<int>::const_iterator it = s.begin(); it != s.end(); it++) { a[i] = *it; i++; } midc = m[a[1]] / 2; com = min(m[a[0]], m[a[2]]); if (midc > com) { cout << n - (midc * 2) << endl; for (i = 0; i < midc; i++) { cout << a[0] << ; cout << a[2] << ; } for (i = 0; i < m[a[0]]; i++) cout << a[0] << ; for (i = 0; i < m[a[2]]; i++) cout << a[2] << ; if (m[a[1]] % 2) cout << a[1]; cout << endl; } else { cout << n - (2 * com) << endl; for (i = 0; i < m[a[1]]; i++) cout << a[1] << ; for (i = 0; i < (2 * com); i++) cout << a[1] << ; for (i = 0; i < m[a[0]] - com; i++) cout << a[0] << ; for (i = 0; i < m[a[2]] - com; i++) cout << a[2] << ; cout << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 702, M = 4900005; int main() { int n, m, a[55], b, i, j, ans, cnt; while (scanf( %d , &n) == 1) { for (i = 1; i <= n; i++) scanf( %d , a + i); scanf( %d , &m); for (i = 1, ans = 0; i <= m; i++) { scanf( %d , &b); for (j = 1; j <= n; j++) if (b % a[j] == 0) { if (b / a[j] > ans) { ans = b / a[j]; cnt = 1; } else if (b / a[j] == ans) cnt++; } } printf( %d n , cnt); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 5; int n; double r, v, l; double tim(double p1, double p2) { double rem = p2 - p1; double k = int(rem / l); rem = rem - k * l; double le = 0, ri = 1e9, mid; for (int I = 1; I <= 200; I++) { mid = (le + ri) / 2.0; if (v * mid + 2 * sin(v * mid / (2 * r)) * r >= rem) { ri = mid; } else { le = mid; } } return mid + double(k * l) / v; } int main() { scanf( %d%lf%lf , &n, &r, &v); l = 3.141592653589 * r * 2; for (int i = 1; i <= n; i++) { int p1, p2; scanf( %d%d , &p1, &p2); printf( %.10f n , float(tim(double(p1), double(p2)))); } return 0; } |
#include <bits/stdc++.h> using namespace std; int INTlog2(unsigned long long number) { int logval = 0; while (number >>= 1) logval++; return logval; } int main() { unsigned long long n, k; cin >> n >> k; if (k == 1) cout << n << endl; else cout << (1LL << (INTlog2(n) + 1LL)) - 1 << endl; return 0; } |
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