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#include <bits/stdc++.h> using namespace std; const int maxn = 2000; const int INF = 1e9 + 7; int le, ri, tot, cpt[60][60], fir[maxn], sec[maxn]; struct MCMF { struct Edge { int from, to, cap, cost; Edge() {} Edge(int from, int to, int cap, int cost) : from(from), to(to), cap(cap), cost(cost) {} }; int n, m, s, t; vector<Edge> edges; vector<int> G[maxn]; int inq[maxn]; int d[maxn]; int p[maxn]; int a[maxn]; void init() { for (int i = 0; i <= n; ++i) G[i].clear(); edges.clear(); } void AddEdge(int from, int to, int cap, int cost) { edges.push_back(Edge(from, to, cap, cost)); edges.push_back(Edge(to, from, 0, -cost)); m = edges.size(); G[from].push_back(m - 2); G[to].push_back(m - 1); } bool BF(int& flow, int& cost) { for (int i = 1; i <= n; ++i) d[i] = INF, inq[i] = 0; d[s] = 0, inq[s] = 1, p[s] = 0, a[s] = INF; queue<int> Q; Q.push(s); while (!Q.empty()) { int u = Q.front(); Q.pop(); inq[u] = 0; for (int i = 0; i < G[u].size(); ++i) { Edge& e = edges[G[u][i]]; if (e.cap && d[e.to] > d[u] + e.cost) { d[e.to] = d[u] + e.cost; p[e.to] = G[u][i]; a[e.to] = min(a[u], e.cap); if (!inq[e.to]) { Q.push(e.to); inq[e.to] = 1; } } } } if (d[t] == INF) return false; flow += a[t]; cost += d[t] * a[t]; int u = t; while (u != s) { edges[p[u]].cap -= a[t]; edges[p[u] ^ 1].cap += a[t]; u = edges[p[u]].from; } return true; } int Mincost() { int flow = 0, cost = 0; while (BF(flow, cost)) ; for (int i = le + 1; i < t; ++i) { if (!edges[G[i][1]].cap) cpt[fir[i]][sec[i]] = 1, cpt[sec[i]][fir[i]] = 0; else cpt[fir[i]][sec[i]] = 0, cpt[sec[i]][fir[i]] = 1; } return cost; } } NF; inline int read() { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = (x << 1) + (x << 3) + (ch ^ 48); ch = getchar(); } return x; } inline void readin() { int temp, win[60] = {0}, du[60] = {0}, wwin, llos; le = read(), ri = read(); for (int i = 1; i <= le; ++i) for (int j = 1; j <= le; ++j) if (i != j) cpt[i][j] = 2; NF.s = 0; temp = le + 1; for (int i = 1; i <= ri; ++i) { wwin = read(); llos = read(); cpt[wwin][llos] = 1; cpt[llos][wwin] = 0; } for (int i = 1; i <= le; ++i) for (int j = 1; j <= le; ++j) if (cpt[i][j] == 2) { if (i > j) continue; fir[temp] = i; sec[temp] = j; NF.AddEdge(0, temp, 1, 0); NF.AddEdge(temp, i, 1, 0); NF.AddEdge(temp++, j, 1, 0); ++du[i]; ++du[j]; } else win[i] += cpt[i][j]; NF.n = NF.t = temp; for (int i = 1; i <= le; ++i) { tot += win[i] * win[i]; for (int j = 1; j <= du[i]; ++j) NF.AddEdge(i, NF.t, 1, 2 * (win[i] + j) - 1); } } int main() { NF.init(); readin(); int p = NF.Mincost(); for (int i = 1; i <= le; ++i, puts( )) for (int j = 1; j <= le; ++j) printf( %d , cpt[i][j]); return 0; } |
//-----------------------------------------------------------------------------
// The FPGA is responsible for interfacing between the A/D, the coil drivers,
// and the ARM. In the low-frequency modes it passes the data straight
// through, so that the ARM gets raw A/D samples over the SSP. In the high-
// frequency modes, the FPGA might perform some demodulation first, to
// reduce the amount of data that we must send to the ARM.
//
// I am not really an FPGA/ASIC designer, so I am sure that a lot of this
// could be improved.
//
// Jonathan Westhues, March 2006
// Added ISO14443-A support by Gerhard de Koning Gans, April 2008
//-----------------------------------------------------------------------------
`include "lo_read.v"
`include "lo_passthru.v"
`include "lo_edge_detect.v"
`include "hi_read_tx.v"
`include "hi_read_rx_xcorr.v"
`include "hi_simulate.v"
`include "hi_iso14443a.v"
`include "util.v"
module fpga(
spcki, miso, mosi, ncs,
pck0i, ck_1356meg, ck_1356megb,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk, adc_noe,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
cross_hi, cross_lo,
dbg
);
input spcki, mosi, ncs;
output miso;
input pck0i, ck_1356meg, ck_1356megb;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk, adc_noe;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
input cross_hi, cross_lo;
output dbg;
//assign pck0 = pck0i;
IBUFG #(.IOSTANDARD("DEFAULT") ) pck0b(
.O(pck0),
.I(pck0i)
);
//assign spck = spcki;
IBUFG #(.IOSTANDARD("DEFAULT") ) spckb(
.O(spck),
.I(spcki)
);
//-----------------------------------------------------------------------------
// The SPI receiver. This sets up the configuration word, which the rest of
// the logic looks at to determine how to connect the A/D and the coil
// drivers (i.e., which section gets it). Also assign some symbolic names
// to the configuration bits, for use below.
//-----------------------------------------------------------------------------
reg [15:0] shift_reg;
reg [7:0] divisor;
reg [7:0] conf_word;
// We switch modes between transmitting to the 13.56 MHz tag and receiving
// from it, which means that we must make sure that we can do so without
// glitching, or else we will glitch the transmitted carrier.
always @(posedge ncs)
begin
case(shift_reg[15:12])
4'b0001: conf_word <= shift_reg[7:0];
4'b0010: divisor <= shift_reg[7:0];
endcase
end
always @(posedge spck)
begin
if(~ncs)
begin
shift_reg[15:1] <= shift_reg[14:0];
shift_reg[0] <= mosi;
end
end
wire [2:0] major_mode;
assign major_mode = conf_word[7:5];
// For the low-frequency configuration:
wire lo_is_125khz;
assign lo_is_125khz = conf_word[3];
// For the high-frequency transmit configuration: modulation depth, either
// 100% (just quite driving antenna, steady LOW), or shallower (tri-state
// some fraction of the buffers)
wire hi_read_tx_shallow_modulation;
assign hi_read_tx_shallow_modulation = conf_word[0];
// For the high-frequency receive correlator: frequency against which to
// correlate.
wire hi_read_rx_xcorr_848;
assign hi_read_rx_xcorr_848 = conf_word[0];
// and whether to drive the coil (reader) or just short it (snooper)
wire hi_read_rx_xcorr_snoop;
assign hi_read_rx_xcorr_snoop = conf_word[1];
// Divide the expected subcarrier frequency for hi_read_rx_xcorr by 4
wire hi_read_rx_xcorr_quarter;
assign hi_read_rx_xcorr_quarter = conf_word[2];
// For the high-frequency simulated tag: what kind of modulation to use.
wire [2:0] hi_simulate_mod_type;
assign hi_simulate_mod_type = conf_word[2:0];
// For the high-frequency simulated tag: what kind of modulation to use.
wire lf_field;
assign lf_field = conf_word[0];
//-----------------------------------------------------------------------------
// And then we instantiate the modules corresponding to each of the FPGA's
// major modes, and use muxes to connect the outputs of the active mode to
// the output pins.
//-----------------------------------------------------------------------------
lo_read lr(
pck0, ck_1356meg, ck_1356megb,
lr_pwr_lo, lr_pwr_hi, lr_pwr_oe1, lr_pwr_oe2, lr_pwr_oe3, lr_pwr_oe4,
adc_d, lr_adc_clk,
lr_ssp_frame, lr_ssp_din, ssp_dout, lr_ssp_clk,
cross_hi, cross_lo,
lr_dbg,
lo_is_125khz, divisor
);
lo_passthru lp(
pck0, ck_1356meg, ck_1356megb,
lp_pwr_lo, lp_pwr_hi, lp_pwr_oe1, lp_pwr_oe2, lp_pwr_oe3, lp_pwr_oe4,
adc_d, lp_adc_clk,
lp_ssp_frame, lp_ssp_din, ssp_dout, lp_ssp_clk,
cross_hi, cross_lo,
lp_dbg, divisor
);
lo_edge_detect ls(
pck0, ck_1356meg, ck_1356megb,
ls_pwr_lo, ls_pwr_hi, ls_pwr_oe1, ls_pwr_oe2, ls_pwr_oe3, ls_pwr_oe4,
adc_d, ls_adc_clk,
ls_ssp_frame, ls_ssp_din, ssp_dout, ls_ssp_clk,
cross_hi, cross_lo,
ls_dbg, divisor,
lf_field
);
hi_read_tx ht(
pck0, ck_1356meg, ck_1356megb,
ht_pwr_lo, ht_pwr_hi, ht_pwr_oe1, ht_pwr_oe2, ht_pwr_oe3, ht_pwr_oe4,
adc_d, ht_adc_clk,
ht_ssp_frame, ht_ssp_din, ssp_dout, ht_ssp_clk,
cross_hi, cross_lo,
ht_dbg,
hi_read_tx_shallow_modulation
);
hi_read_rx_xcorr hrxc(
pck0, ck_1356meg, ck_1356megb,
hrxc_pwr_lo, hrxc_pwr_hi, hrxc_pwr_oe1, hrxc_pwr_oe2, hrxc_pwr_oe3, hrxc_pwr_oe4,
adc_d, hrxc_adc_clk,
hrxc_ssp_frame, hrxc_ssp_din, ssp_dout, hrxc_ssp_clk,
cross_hi, cross_lo,
hrxc_dbg,
hi_read_rx_xcorr_848, hi_read_rx_xcorr_snoop, hi_read_rx_xcorr_quarter
);
hi_simulate hs(
pck0, ck_1356meg, ck_1356megb,
hs_pwr_lo, hs_pwr_hi, hs_pwr_oe1, hs_pwr_oe2, hs_pwr_oe3, hs_pwr_oe4,
adc_d, hs_adc_clk,
hs_ssp_frame, hs_ssp_din, ssp_dout, hs_ssp_clk,
cross_hi, cross_lo,
hs_dbg,
hi_simulate_mod_type
);
hi_iso14443a hisn(
pck0, ck_1356meg, ck_1356megb,
hisn_pwr_lo, hisn_pwr_hi, hisn_pwr_oe1, hisn_pwr_oe2, hisn_pwr_oe3, hisn_pwr_oe4,
adc_d, hisn_adc_clk,
hisn_ssp_frame, hisn_ssp_din, ssp_dout, hisn_ssp_clk,
cross_hi, cross_lo,
hisn_dbg,
hi_simulate_mod_type
);
// Major modes:
// 000 -- LF reader (generic)
// 001 -- LF simulated tag (generic)
// 010 -- HF reader, transmitting to tag; modulation depth selectable
// 011 -- HF reader, receiving from tag, correlating as it goes; frequency selectable
// 100 -- HF simulated tag
// 101 -- HF ISO14443-A
// 110 -- LF passthrough
// 111 -- everything off
mux8 mux_ssp_clk (major_mode, ssp_clk, lr_ssp_clk, ls_ssp_clk, ht_ssp_clk, hrxc_ssp_clk, hs_ssp_clk, hisn_ssp_clk, lp_ssp_clk, 1'b0);
mux8 mux_ssp_din (major_mode, ssp_din, lr_ssp_din, ls_ssp_din, ht_ssp_din, hrxc_ssp_din, hs_ssp_din, hisn_ssp_din, lp_ssp_din, 1'b0);
mux8 mux_ssp_frame (major_mode, ssp_frame, lr_ssp_frame, ls_ssp_frame, ht_ssp_frame, hrxc_ssp_frame, hs_ssp_frame, hisn_ssp_frame, lp_ssp_frame, 1'b0);
mux8 mux_pwr_oe1 (major_mode, pwr_oe1, lr_pwr_oe1, ls_pwr_oe1, ht_pwr_oe1, hrxc_pwr_oe1, hs_pwr_oe1, hisn_pwr_oe1, lp_pwr_oe1, 1'b0);
mux8 mux_pwr_oe2 (major_mode, pwr_oe2, lr_pwr_oe2, ls_pwr_oe2, ht_pwr_oe2, hrxc_pwr_oe2, hs_pwr_oe2, hisn_pwr_oe2, lp_pwr_oe2, 1'b0);
mux8 mux_pwr_oe3 (major_mode, pwr_oe3, lr_pwr_oe3, ls_pwr_oe3, ht_pwr_oe3, hrxc_pwr_oe3, hs_pwr_oe3, hisn_pwr_oe3, lp_pwr_oe3, 1'b0);
mux8 mux_pwr_oe4 (major_mode, pwr_oe4, lr_pwr_oe4, ls_pwr_oe4, ht_pwr_oe4, hrxc_pwr_oe4, hs_pwr_oe4, hisn_pwr_oe4, lp_pwr_oe4, 1'b0);
mux8 mux_pwr_lo (major_mode, pwr_lo, lr_pwr_lo, ls_pwr_lo, ht_pwr_lo, hrxc_pwr_lo, hs_pwr_lo, hisn_pwr_lo, lp_pwr_lo, 1'b0);
mux8 mux_pwr_hi (major_mode, pwr_hi, lr_pwr_hi, ls_pwr_hi, ht_pwr_hi, hrxc_pwr_hi, hs_pwr_hi, hisn_pwr_hi, lp_pwr_hi, 1'b0);
mux8 mux_adc_clk (major_mode, adc_clk, lr_adc_clk, ls_adc_clk, ht_adc_clk, hrxc_adc_clk, hs_adc_clk, hisn_adc_clk, lp_adc_clk, 1'b0);
mux8 mux_dbg (major_mode, dbg, lr_dbg, ls_dbg, ht_dbg, hrxc_dbg, hs_dbg, hisn_dbg, lp_dbg, 1'b0);
// In all modes, let the ADC's outputs be enabled.
assign adc_noe = 1'b0;
endmodule
|
module uniphy_status
#(
parameter WIDTH=32,
parameter NUM_UNIPHYS=2
)
(
input clk,
input resetn,
// Slave port
input slave_read,
output [WIDTH-1:0] slave_readdata,
// hw.tcl won't let me index into a bit vector :(
input mem0_local_cal_success,
input mem0_local_cal_fail,
input mem0_local_init_done,
input mem1_local_cal_success,
input mem1_local_cal_fail,
input mem1_local_init_done,
input mem2_local_cal_success,
input mem2_local_cal_fail,
input mem2_local_init_done,
input mem3_local_cal_success,
input mem3_local_cal_fail,
input mem3_local_init_done,
input mem4_local_cal_success,
input mem4_local_cal_fail,
input mem4_local_init_done,
input mem5_local_cal_success,
input mem5_local_cal_fail,
input mem5_local_init_done,
input mem6_local_cal_success,
input mem6_local_cal_fail,
input mem6_local_init_done,
input mem7_local_cal_success,
input mem7_local_cal_fail,
input mem7_local_init_done,
output export_local_cal_success,
output export_local_cal_fail,
output export_local_init_done
);
reg [WIDTH-1:0] aggregate_uniphy_status;
wire local_cal_success;
wire local_cal_fail;
wire local_init_done;
wire [NUM_UNIPHYS-1:0] not_init_done;
wire [7:0] mask;
assign mask = (NUM_UNIPHYS < 1) ? 0 : ~(8'hff << NUM_UNIPHYS);
assign local_cal_success = &( ~mask | {mem7_local_cal_success,
mem6_local_cal_success,
mem5_local_cal_success,
mem4_local_cal_success,
mem3_local_cal_success,
mem2_local_cal_success,
mem1_local_cal_success,
mem0_local_cal_success});
assign local_cal_fail = mem0_local_cal_fail |
mem1_local_cal_fail |
mem2_local_cal_fail |
mem3_local_cal_fail |
mem4_local_cal_fail |
mem5_local_cal_fail |
mem6_local_cal_fail |
mem7_local_cal_fail;
assign local_init_done = &( ~mask |{mem7_local_init_done,
mem6_local_init_done,
mem5_local_init_done,
mem4_local_init_done,
mem3_local_init_done,
mem2_local_init_done,
mem1_local_init_done,
mem0_local_init_done});
assign not_init_done = mask & ~{ mem7_local_init_done,
mem6_local_init_done,
mem5_local_init_done,
mem4_local_init_done,
mem3_local_init_done,
mem2_local_init_done,
mem1_local_init_done,
mem0_local_init_done};
// Desire status==0 to imply success - may cause false positives, but the
// alternative is headaches for non-uniphy memories.
// Status MSB-LSB: not_init_done, 0, !calsuccess, calfail, !initdone
always@(posedge clk or negedge resetn)
if (!resetn)
aggregate_uniphy_status <= {WIDTH{1'b0}};
else
aggregate_uniphy_status <= { not_init_done, 1'b0,
{~local_cal_success,local_cal_fail,~local_init_done}
};
assign slave_readdata = aggregate_uniphy_status;
assign export_local_cal_success = local_cal_success;
assign export_local_cal_fail = local_cal_fail;
assign export_local_init_done = local_init_done;
endmodule
|
/**************************************************************************************************/
/* Many-core processor project Arch Lab. TOKYO TECH */
/**************************************************************************************************/
`default_nettype none
/**************************************************************************************************/
`include "define.v"
/**************************************************************************************************/
`define SS_SER_WAIT 'd0 // do not modify this. RS232C deserializer, State WAIT
`define SS_SER_RCV0 'd1 // do not modify this. RS232C deserializer, State Receive0
`define SS_SER_DONE 'd9 // do not modify this. RS232C deserializer, State DONE
/**************************************************************************************************/
/*
module UartTx(CLK, RST_X, DATA, WE, TXD, READY);
input wire CLK, RST_X, WE;
input wire [15:0] DATA;
output reg TXD, READY;
reg [18:0] cmd;
reg [11:0] waitnum;
reg [4:0] cnt;
always @(posedge CLK or negedge RST_X) begin
if(~RST_X) begin
TXD <= 1'b1;
READY <= 1'b1;
cmd <= 19'h7ffff;
waitnum <= 0;
cnt <= 0;
end else if( READY ) begin
TXD <= 1'b1;
waitnum <= 0;
if( WE )begin
READY <= 1'b0;
//cmd <= {DATA[15:8], 2'b01, DATA[7:0], 1'b0};
cmd <= {DATA[15:8], 2'b01, 8'b11111111, 1'b1};
cnt <= 20; // 10
end
end else if( waitnum >= `SERIAL_WCNT ) begin
TXD <= cmd[0];
READY <= (cnt == 1);
cmd <= {1'b1, cmd[18:1]};
waitnum <= 1;
cnt <= cnt - 1;
end else begin
waitnum <= waitnum + 1;
end
end
endmodule
*/
module UartTx(CLK, RST_X, DATA, WE, TXD, READY);
input wire CLK, RST_X, WE;
input wire [7:0] DATA;
output reg TXD, READY;
reg [8:0] cmd;
reg [11:0] waitnum;
reg [3:0] cnt;
always @(posedge CLK or negedge RST_X) begin
if(~RST_X) begin
TXD <= 1'b1;
READY <= 1'b1;
cmd <= 9'h1ff;
waitnum <= 0;
cnt <= 0;
end else if( READY ) begin
TXD <= 1'b1;
waitnum <= 0;
if( WE )begin
READY <= 1'b0;
cmd <= {DATA, 1'b0};
cnt <= 10;
end
end else if( waitnum >= `SERIAL_WCNT ) begin
TXD <= cmd[0];
READY <= (cnt == 1);
cmd <= {1'b1, cmd[8:1]};
waitnum <= 1;
cnt <= cnt - 1;
end else begin
waitnum <= waitnum + 1;
end
end
endmodule
/**************************************************************************************************/
module TX_FIFO(CLK, RST_X, D_IN, WE, RE, D_OUT, D_EN, RDY, ERR);
input wire CLK, RST_X, WE, RE;
input wire [7:0] D_IN;
output reg [7:0] D_OUT;
output reg D_EN, ERR;
output wire RDY;
reg [7:0] mem [0:2048-1]; // FIFO memory
reg [10:0] head, tail; // regs for FIFO
assign RDY = (D_EN==0 && head!=tail);
always @(posedge CLK) begin
if(~RST_X) begin
{D_EN, ERR, head, tail, D_OUT} <= 0;
end
else begin
if(WE) begin ///// enqueue
mem[tail] <= D_IN;
tail <= tail + 1;
if(head == (tail + 1)) ERR <= 1; // buffer may full!
end
if(RE) begin ///// dequeue
D_OUT <= mem[head];
D_EN <= 1;
head <= head + 1;
end else begin
D_EN <= 0;
end
end
end
endmodule
/**************************************************************************************************/
/*
module MultiUartTx(CLK, RST_X, TXD, ERR,
DT01, WE01, DT02, WE02, DT03, WE03, DT04, WE04);
input wire CLK, RST_X;
input wire [7:0] DT01, DT02, DT03, DT04;
input wire WE01, WE02, WE03, WE04;
output wire TXD, ERR;
wire RE01, RE02, RE03, RE04;
wire [7:0] data01, data02, data03, data04;
wire en01, en02, en03, en04;
wire RDY01, RDY02, RDY03, RDY04;
wire ERR01, ERR02, ERR03, ERR04;
wire [15:0] data;
wire en;
wire TxRdy;
assign ERR = ERR01 | ERR02 | ERR03 | ERR04;
assign RE01 = (RDY01 & TxRdy);
assign RE02 = (RDY02 & TxRdy) & (~RDY01 & ~en01);
assign RE03 = (RDY03 & TxRdy) & (~RDY01 & ~en01) & (~RDY02 & ~en02);
assign RE04 = (RDY04 & TxRdy) & (~RDY01 & ~en01) & (~RDY02 & ~en02) & (~RDY03 & ~en03);
assign data = (en01) ? {data01, 8'h30} :
(en02) ? {data02, 8'h31} :
(en03) ? {data03, 8'h32} : {data04, 8'h33};
assign en = en01 | en02 | en03 | en04;
TX_FIFO fifo_01(CLK, RST_X, DT01, WE01, RE01, data01, en01, RDY01, ERR01);
TX_FIFO fifo_02(CLK, RST_X, DT02, WE02, RE02, data02, en02, RDY02, ERR02);
TX_FIFO fifo_03(CLK, RST_X, DT03, WE03, RE03, data03, en03, RDY03, ERR03);
TX_FIFO fifo_04(CLK, RST_X, DT04, WE04, RE04, data04, en04, RDY04, ERR04);
UartTx send(CLK, RST_X, data, en, TXD, TxRdy);
endmodule
*/
module SingleUartTx(CLK, RST_X, TXD, ERR, DT01, WE01);
input wire CLK, RST_X;
input wire [7:0] DT01;
input wire WE01;
output wire TXD, ERR;
wire RE01;
wire [7:0] data01;
wire en01;
wire RDY01;
wire ERR01;
wire TxRdy;
assign ERR = ERR01;
assign RE01 = (RDY01 & TxRdy);
TX_FIFO fifo_01(CLK, RST_X, DT01, WE01, RE01, data01, en01, RDY01, ERR01);
UartTx send(CLK, RST_X, data01, en01, TXD, TxRdy);
endmodule
/**************************************************************************************************/
module UartRx(CLK, RST_X, RXD, DATA, EN);
input wire CLK, RST_X, RXD; // clock, reset, RS232C input
output reg [7:0] DATA; // 8bit output data
output reg EN; // 8bit output data enable
reg [3:0] stage;
reg [12:0] cnt; // counter to latch D0, D1, ..., D7
reg [11:0] cnt_start; // counter to detect the Start Bit
wire [12:0] waitcnt;
assign waitcnt = `SERIAL_WCNT;
always @(posedge CLK or negedge RST_X)
if (~RST_X) cnt_start <= 0;
else cnt_start <= (RXD) ? 0 : cnt_start + 1;
always @(posedge CLK or negedge RST_X)
if(~RST_X) begin
EN <= 0;
stage <= `SS_SER_WAIT;
cnt <= 1;
DATA <= 0;
end else if (stage == `SS_SER_WAIT) begin // detect the Start Bit
EN <= 0;
stage <= (cnt_start == (waitcnt >> 1)) ? `SS_SER_RCV0 : stage;
end else begin
if (cnt != waitcnt) begin
cnt <= cnt + 1;
EN <= 0;
end else begin // receive 1bit data
stage <= (stage == `SS_SER_DONE) ? `SS_SER_WAIT : stage + 1;
EN <= (stage == 8) ? 1 : 0;
DATA <= {RXD, DATA[7:1]};
cnt <= 1;
end
end
endmodule
/**************************************************************************************************/
/*
module PLOADER(CLK, RST_X, RXD, ADDR, DATA, WE, DONE1, DONE2);
input wire CLK, RST_X, RXD;
output reg [31:0] ADDR;
output reg [31:0] DATA;
output reg WE;
output reg DONE1; // application program load is done
output reg DONE2; // scheduling program load is done
reg [31:0] waddr; // memory write address
wire SER_EN;
wire [7:0] SER_DATA;
UartRx recv(CLK, RST_X, RXD, SER_DATA, SER_EN);
always @(posedge CLK or negedge RST_X) begin
if(~RST_X) begin
{ADDR, DATA, WE, waddr, DONE1, DONE2} <= 0;
end else begin
if(DONE2==0 && SER_EN) begin
//ADDR <= (waddr<32'h40000) ? waddr : {8'h04, 6'd0, waddr[17:0]};
ADDR <= waddr;
DATA <= {SER_DATA, DATA[31:8]};
WE <= (waddr[1:0]==3);
waddr <= waddr + 1;
if(waddr>=`APP_SIZE) DONE1 <= 1;
end else begin
WE <= 0;
if(waddr>=`APP_SIZE) DONE1 <= 1;
if(waddr>=`IMG_SIZE) DONE2 <= 1;
end
end
end
endmodule
*/
module PLOADER(CLK, RST_X, RXD, ADDR, DATA, WE_32, WE_128, DONE);
input wire CLK, RST_X, RXD;
output reg [31:0] ADDR;
output reg [127:0] DATA;
output reg WE_32;
output reg WE_128;
output reg DONE;
reg [31:0] waddr; // memory write address
wire SER_EN;
wire [7:0] SER_DATA;
UartRx recv(CLK, RST_X, RXD, SER_DATA, SER_EN);
always @(posedge CLK or negedge RST_X) begin
if(~RST_X) begin
{ADDR, DATA, WE_32, WE_128, waddr, DONE} <= 0;
end else begin
if(DONE==0 && SER_EN) begin
ADDR <= waddr;
DATA <= {SER_DATA, DATA[127:8]};
WE_32 <= (waddr[1:0]==3) ? 1'b1 : 1'b0;
WE_128 <= (waddr[3:0]==15) ? 1'b1 : 1'b0;
waddr <= waddr + 1;
if(waddr>=`APP_SIZE) DONE <= 1;
end else begin
WE_32 <= 0;
WE_128 <= 0;
if(waddr>=`APP_SIZE) DONE <= 1;
end
end
end
endmodule
/**************************************************************************************************/
`default_nettype wire
/**************************************************************************************************/
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1000000007; const long double pi = acos(-1); const long long maxn = 200001; template <class T> ostream &operator<<(ostream &out, vector<T> &A) { for (auto x : A) out << x << ; return out; } template <class T1, class T2> T1 powr(T1 a, T2 b) { T1 res = 1; for (long long i = 1; i < b + 1; i++) res = res * a; return res; } int32_t main() { long long Q; cin >> Q; while (Q--) { long long n, pos; cin >> n; vector<long long> A(n); for (long long i = 0; i < n; i++) { cin >> A[i]; if (A[i] == 1) pos = i; } bool okl = true, okr = true; for (long long j = 1; j < n; j++) { okl &= (A[(pos - j + n) % n] == j + 1); okr &= (A[(pos + j + n) % n] == j + 1); } puts(okl or okr ? YES : NO ); } } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e6 + 5; double a[maxn], st[maxn]; int len[maxn]; int main() { int n, x; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &x); a[i] = x; } int p = 0; for (int i = 1; i <= n; i++) { st[++p] = a[i]; len[p] = 1; while (p > 1 && st[p] < st[p - 1]) { st[p - 1] = (st[p - 1] * len[p - 1] + st[p] * len[p]) / (len[p - 1] + len[p]); len[p - 1] += len[p]; p--; } } for (int i = 1; i <= p; i++) { for (int j = 1; j <= len[i]; j++) { printf( %.10f n , st[i]); } } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long mod = 1000000007LL; const long long mod2 = 998244353LL; int n; int a[100005], b[100005]; int main() { cin >> n; for (int i = 1; i <= n; ++i) { scanf( %d , &a[i]); } for (int i = 1; i <= n; ++i) { scanf( %d , &b[i]); } sort(a + 1, a + n + 1); sort(b + 1, b + n + 1); long long det = 0; int i = n, j = n; bool cur = false; while (i >= 1 || j >= 1) { if (!cur) { if (i < 1) { j--; } else { if (j < 1) { det += a[i]; i--; } else { if (a[i] >= b[j]) { det += a[i]; i--; } else { j--; } } } } else { if (j < 1) { i--; } else { if (i < 1) { det -= b[j]; j--; } else { if (b[j] >= a[i]) { det -= b[j]; j--; } else { i--; } } } } cur = !cur; } cout << det << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long inf = 1e18; const long long N = 100001; long long mod = 1000000007; long long min(long long a, long long b) { if (a < b) return a; else return b; } long long max(long long a, long long b) { if (a > b) return a; else return b; } long long power(long long a, long long b) { long long res = 1; a %= mod; assert(b >= 0); for (; b; b >>= 1) { if (b & 1) res = res * a % mod; a = a * a % mod; } return res; } long long gcd(long long p, long long q) { if (p % q == 0) return q; else { return gcd(q, p % q); } } long long mul(long long a, long long b) { return ((a % mod) * (b % mod)) % mod; } long long sub(long long a, long long b) { return (((a - b) % mod) + mod) % mod; } vector<long long> kmp(string s) { long long n = s.size(); vector<long long> ans(n); long long len = 0; for (long long i = 1; i < n; i++) { while (len > 0 && s[len] != s[i]) len = ans[len - 1]; len += (s[i] == s[len]); ans[i] = len; } return ans; } void solve() { string s; cin >> s; vector<long long> ans = kmp(s); if (ans.back() == 0) { cout << Just a legend << n ; return; } for (long long i = 1; i < s.size() - 1; i++) { if (ans[i] == ans.back()) { cout << s.substr(0, ans[i]); cout << n ; return; } } if (ans[ans.back() - 1] == 0) cout << Just a legend ; else cout << s.substr(0, ans[ans.back() - 1]); } signed main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t = 1; for (long long i = 0; i < t; i++) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int MAXN = 2e5 + 7; long long a[MAXN]; int dis[233][233]; int val[233][233]; int main(int argc, char const *argv[]) { int n; scanf( %d , &n); for (int i = (1); i <= (n); ++i) { scanf( %lld , &a[i]); if (a[i] == 0) { i--; n--; } } if (n > 400) printf( 3 n ); else { for (int i = (1); i <= (n); ++i) { for (int j = (1); j <= (n); ++j) { dis[i][j] = 1 << 28; val[i][j] = 1 << 28; } } for (int i = (1); i <= (n); ++i) { for (int j = (1); j <= (n); ++j) { if (a[i] & a[j]) { dis[i][j] = 1; val[i][j] = 1; } } } int ans = 1 << 28; for (int k = 1; k <= n; ++k) { for (int i = 1; i < k; ++i) { for (int j = 1; j < i; ++j) { ans = min(ans, dis[i][j] + val[i][k] + val[k][j]); } } for (int i = 1; i <= n; ++i) { for (int j = 1; j <= n; ++j) { dis[i][j] = min(dis[i][j], dis[i][k] + dis[k][j]); } } } if (ans > 200) printf( -1 n ); else printf( %d n , ans); } return 0; } |
/*
* .--------------. .----------------. .------------.
* | .------------. | .--------------. | .----------. |
* | | ____ ____ | | | ____ ____ | | | ______ | |
* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
* | | | | | | | | | | | |
* |_| | '------------' | '--------------' | '----------' |
* '--------------' '----------------' '------------'
*
* openHMC - An Open Source Hybrid Memory Cube Controller
* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
* www.ziti.uni-heidelberg.de
* B6, 26
* 68159 Mannheim
* Germany
*
* Contact:
* http://ra.ziti.uni-heidelberg.de/openhmc
*
* This source file is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This source file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this source file. If not, see <http://www.gnu.org/licenses/>.
*
*
* Module name: openhmc_sync_fifo_reg_stage
*
*/
`default_nettype none
module openhmc_sync_fifo_reg_stage #(parameter DWIDTH = 8)(
input wire clk,
input wire res_n,
input wire [DWIDTH-1:0] d_in,
input wire [DWIDTH-1:0] d_in_p,
input wire p_full, // full signal from the previous stage
input wire n_full, // full signal from the next stage
input wire si,
input wire so,
output reg full, // full = '1' -> this stage has a valid entry
output reg [DWIDTH-1:0] d_out
);
//=====================================================================================================
//-----------------------------------------------------------------------------------------------------
//---------WIRING AND SIGNAL STUFF---------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------
//=====================================================================================================
wire en, muxi;
assign en = (si & so & full) // so and si, shift through
| (si & ~so & ~full && n_full) // shift in new value
| (~si & so & p_full); // shift through
assign muxi = (si & ~so) | (si & so & ~p_full & full);
//=====================================================================================================
//-----------------------------------------------------------------------------------------------------
//---------LOGIC STARTS HERE---------------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------
//=====================================================================================================
always @ (posedge clk or negedge res_n) begin
if (!res_n) begin
full <= 1'b0;
d_out <= {DWIDTH{1'b0}};
end else begin
if (en) begin
if (muxi) begin
d_out <= d_in; // enter new value when enabled
end else begin
d_out <= d_in_p; // shift through
end
end
full <= (full & si) // stay full while si to other stage
| (full & ~si & ~so) // hold full
| (~si & so & p_full) // keep full as long as prev stage is full
| (si & ~so & n_full); // fill this stage by si
end
end
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 7; const long long mod = 1e9 + 7; long long mpow(long long a, long long b) { long long res = 1; while (b) { if (b % 2 == 1) { res = res * a; } b = b / 2; a = a * a; } return res; } long long pow1(long long a, long long b) { long long res = 1; while (b) { if (b % 2 == 1) res = res * a % mod; b = b / 2; a = a * a % mod; } return res; } int main() { long long k; cin >> k; long long b = 1; b = mpow(2LL, k - 1) - 1 + mpow(2, k) - 1 - (mpow(2, k - 1)); long long ans = pow1(4, b); ans = ans * 6 % mod; cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int inf = (int)1e9; const double INF = 1e12, EPS = 1e-9; const int B = 2000; const int dy[] = {-1, 0, 1, 0}, dx[] = {0, -1, 0, 1}; int h, w, q; int qs[100000][4]; char in[100010][12], dir[256]; int dp[100010 * 12], vis[100010][12]; inline int to(int y, int x) { int &res = dp[y * 12 + x]; if (res != -1) return res; if (y == 0 || x == 0 || x == w + 1) return res = y * 12 + x; res = -2; int d = dir[in[y][x]]; return res = to(y + dy[d], x + dx[d]); } int main() { dir[ < ] = 1; dir[ ^ ] = 0; dir[ > ] = 3; scanf( %d%d%d , &h, &w, &q); for (int i = 0; i < (int)h; i++) scanf( %s , in[i + 1] + 1); for (int i = 0; i < (int)q; i++) { char c, d; int y, x; scanf( %c%d%d , &c, &y, &x); qs[i][0] = c == A ; qs[i][1] = y; qs[i][2] = x; if (c == C ) { scanf( %c , &d); qs[i][3] = d; } } memset(vis, -1, sizeof(vis)); for (int it = 0; it < (int)q; it++) { if (it % B == 0) { memset(dp, -1, sizeof(dp)); for (int i = it; i < it + B && i < q; i++) if (qs[i][0] == 0) { int y = qs[i][1], x = qs[i][2]; dp[y * 12 + x] = y * 12 + x; } } int y = qs[it][1], x = qs[it][2]; if (!qs[it][0]) { in[y][x] = (char)qs[it][3]; continue; } while (1) { if (x == 0 || x == w + 1 || y == 0) { printf( %d %d n , y, x); break; } if (vis[y][x] == it) { puts( -1 -1 ); break; } vis[y][x] = it; int ny = to(y, x), nx; if (ny < 0) { puts( -1 -1 ); break; } nx = ny % 12; ny /= 12; if (nx == 0 || nx == w + 1 || ny == 0) { printf( %d %d n , ny, nx); break; } int d = dir[in[ny][nx]]; y = ny + dy[d]; x = nx + dx[d]; } } return 0; } |
#include <bits/stdc++.h> using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); const int N = 88; const int M = 100100; int dp[N][M][2]; pair<int, int> a[N]; int n, m; int main() { scanf( %d%d , &n, &m); for (int i = 0; i < n; i++) scanf( %d%d , &a[i].first, &a[i].second); sort(a, a + n); for (int i = 0; i <= n; i++) for (int j = 0; j <= m; j++) for (int f = 0; f < 2; f++) dp[i][j][f] = M; dp[0][0][1] = 0; for (int i = 0; i < n; i++) { for (int x = 0; x <= m; x++) dp[i + 1][x][0] = min(dp[i + 1][x][0], min(dp[i][x][0], dp[i][x][1])); for (int x = 0; x <= m; x++) { int r = a[i].first - x - 1; r = max(r, x - a[i].first); r = max(r, a[i].second); int y = min(m, a[i].first + r); dp[i + 1][y][1] = min(dp[i + 1][y][1], min(dp[i][x][0], dp[i][x][1]) + r - a[i].second); } for (int x = 1; x <= m; x++) dp[i + 1][x][1] = min(dp[i + 1][x][1], dp[i + 1][x - 1][1] + 1); } printf( %d n , min(dp[n][m][0], dp[n][m][1])); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = (int)1e5 + 9; long long power(long long x, long long y) { if (y == 0) return 1; long long temp = power(x, y / 2); if (y % 2 == 1) return temp * temp * x; else return temp * temp; } bool check(string a, string b) { sort(a.begin(), a.end()); sort(b.begin(), b.end()); if (a == b) return true; return false; } string solve(string x) { int n = x.length(); if (n % 2) return x; string a = solve(x.substr(0, n / 2)); string b = solve(x.substr(n / 2, n)); return a < b ? (a + b) : (b + a); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); string a, b; cin >> a >> b; if (solve(a) == solve(b)) cout << YES ; else cout << NO ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int i, j, w, h; string temp; vector<string> img; cin >> w >> h; for (i = 0; i < h; i++) { cin >> temp; img.push_back(temp); } for (j = 0; j < w; j++) { for (i = 0; i < h; i++) cout << img[i][j] << img[i][j]; cout << endl; for (i = 0; i < h; i++) cout << img[i][j] << img[i][j]; cout << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 1e9 + 7; const int mod = 1e9 + 7; long long int powmod(long long int a, long long int b) { long long int res = 1; a %= mod; assert(b >= 0); for (; b; b >>= 1) { if (b & 1) res = res * a % mod; a = a * a % mod; } return res; } int nxt() { int x; scanf( %d , &x); return x; } class FenwickTree { public: vector<int> ft; FenwickTree(int n) { ft.assign(n + 1, 0); } int rsq(int b) { int sum = 0; for (; b; b -= (b & (-b))) sum += ft[b]; return sum; } int rsq(int a, int b) { return rsq(b) - (a == 1 ? 0 : rsq(a - 1)); } void adjust(int k, int v) { for (; k < (int)ft.size(); k += (k & (-k))) ft[k] += v; } }; void cnt(int l, int r) {} void add(int l) {} void rmv(int l) {} int main() { long long int n, k; cin >> n >> k; vector<int> a(n), b(n); for (int i = 0; i < n; i++) { a[i] = nxt(); b[i] = a[i]; } sort((b).begin(), (b).end()); for (int i = 0; i < n; i++) { a[i] = lower_bound((b).begin(), (b).end(), a[i]) - b.begin() + 1; } FenwickTree ft(n), ft2(n); long long int cnt = 0; for (int i = 0; i < n; i++) { cnt += (long long int)ft2.rsq(a[i] + 1, n); ft2.adjust(a[i], 1); } if (cnt <= k) { printf( %lld n , n * (n - 1) / 2); return 0; } int pr = 0; long long int tmp = cnt; cnt = 0; for (int i = 0; i < n; i++) { tmp += ft.rsq(a[i] + 1, n); tmp += ft2.rsq(a[i] - 1); ft.adjust(a[i], 1); while (tmp > k && pr <= n - 1) { tmp -= ft.rsq(a[pr] + 1, n); tmp -= ft2.rsq(a[pr] - 1); ft2.adjust(a[pr], -1); pr++; } cnt += max(0LL, n - pr); } printf( %lld n , cnt); return 0; } |
#include <bits/stdc++.h> int main() { long long a, sum, l, i, b; char ch[10]; while (scanf( %I64d , &a) != EOF) { getchar(); scanf( %s , ch); l = strlen(ch); b = 0; for (i = l - 1; i > 0; i--) b = (ch[i] - 0 + b) * 10; b = ch[0] - 0 + b; sum = a + b; printf( %I64d n , sum); } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SEDFXBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__SEDFXBP_BEHAVIORAL_PP_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ls__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__sedfxbp (
Q ,
Q_N ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire DE_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire mux_out ;
wire de_d ;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
// Name Output Other arguments
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD_delayed, SCE_delayed );
sky130_fd_sc_ls__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D_delayed, DE_delayed );
sky130_fd_sc_ls__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond1 = ( awake && ( SCE_delayed === 1'b0 ) && ( DE_delayed === 1'b1 ) );
assign cond2 = ( awake && ( SCE_delayed === 1'b1 ) );
assign cond3 = ( awake && ( DE_delayed === 1'b1 ) && ( D_delayed !== SCD_delayed ) );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SEDFXBP_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLXTP_BLACKBOX_V
`define SKY130_FD_SC_HS__DLXTP_BLACKBOX_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlxtp (
Q ,
D ,
GATE
);
output Q ;
input D ;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLXTP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int used[100]; vector<vector<int>> g; int cmp = 0; vector<int> parent, rank1; void make_set(int v) { parent[v] = v; rank1[v] = 0; } int find_set(int v) { if (v == parent[v]) return v; return parent[v] = find_set(parent[v]); } void union_sets(int a, int b) { a = find_set(a); b = find_set(b); if (a != b) { if (rank1[a] < rank1[b]) swap(a, b); parent[b] = a; if (rank1[a] == rank1[b]) ++rank1[a]; } } bool ok = 1; void dfs(int v, int p = -1) { used[v] = 1; for (auto to : g[v]) { if (!used[to]) union_sets(v, to), dfs(to, v); else { if (to != p) ok = 0; } } } signed main() { ios_base::sync_with_stdio(0), cin.tie(0); int n, m; cin >> n >> m; parent.resize(n); rank1.resize(n); for (int i = 0; i < n; ++i) make_set(i); g.resize(n); bool ok1 = 1, ok2 = 1, ok3 = 1; bool ok4 = 1; if (m > n) ok1 = 0; for (int i = 0; i < m; ++i) { int a, b; cin >> a >> b; a--, b--; g[a].push_back(b); g[b].push_back(a); if (g[a].size() > 2 || g[b].size() > 2) { ok2 = 0; } } dfs(0); for (int i = 0; i < n; ++i) { if (!used[i]) ok3 = 0; if (g[i].size() != 2) ok4 = 0; } if (ok4 && ok3) { cout << YES << endl << 0; return 0; } memset(used, 0, sizeof(used)); for (int i = 0; i < n; ++i) { if (!used[i]) dfs(i); } if (!(ok1 && ok2 && ok)) { cout << NO ; return 0; } vector<pair<int, int>> ans; vector<int> cur; vector<int> deg(n); for (int i = 0; i < n; ++i) { deg[i] = g[i].size(); if (deg[i] <= 1) cur.push_back(i); } for (int i = 0; i < n; ++i) { if (!used[i]) { dfs(i); cmp++; } } vector<int> nd; for (int i = 0; i < n; ++i) { for (int j = i + 1; j < n; ++j) { if (deg[i] >= 2 || deg[j] >= 2) continue; if (find_set(i) != find_set(j)) { ans.push_back({i, j}); deg[i]++; deg[j]++; union_sets(i, j); } } } for (int i = 0; i < n; ++i) { if (deg[i] <= 1) nd.push_back(i); } ans.push_back({nd[0], nd[nd.size() - 1]}); cout << YES n << ans.size() << n ; for (auto u : ans) cout << u.first + 1 << << u.second + 1 << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; long long int dp[2002][2002]; vector<long long int> col, row; long long int sol(long int p, long int q, int n, int m, int jk) { if (p == 0 || q == 0) { return 0; } vector<long long int>::iterator it; if (p <= 2 * n && q <= 2 * m) { if (jk == 0) { return (p * q - dp[p][q]); } return dp[p][q]; } else if (p <= 2 * n) { it = lower_bound(col.begin(), col.end(), q); if (*it != q) { it--; } long long int ab = *it; q = q % ab; ab /= 2; ab = ab * p; return ab + sol(p, q, n, m, 1 - jk); } else { it = lower_bound(row.begin(), row.end(), p); if (*it != p) { it--; } long long int ab = *it; p = p % ab; ab /= 2; ab = ab * q; return ab + sol(p, q, n, m, 1 - jk); } return 0; } int main() { int n, m, q; cin >> n >> m >> q; int arr[2 * n + 2][2 * m + 2]; for (int x = 1; x <= n; x++) { string s; cin >> s; for (int y = 1; y <= m; y++) { arr[x][y] = s[y - 1] - 0 ; } } for (int x = 1; x <= 2 * n; x++) { for (int y = 1; y <= 2 * m; y++) { if (x <= n && y <= m) { } else if (x > n && y > m) { arr[x][y] = arr[x - n][y - m]; } else if (x > n) { arr[x][y] = 1 - arr[x - n][y]; } else { arr[x][y] = 1 - arr[x][y - m]; } dp[x][y] = dp[x][y - 1] + dp[x - 1][y] - dp[x - 1][y - 1] + arr[x][y]; } } int sz = 0; col.push_back(m); while (col[sz] < INT_MAX) { col.push_back(col[sz++] * 2); } sz = 0; row.push_back(n); while (row[sz] < INT_MAX) { row.push_back(row[sz++] * 2); } while (q--) { int x1, x2, y1, y2; cin >> x1 >> y1 >> x2 >> y2; long long int a = sol(x2, y2, n, m, 1); long long int b = sol(x1 - 1, y2, n, m, 1); long long int c = sol(x2, y1 - 1, n, m, 1); long long int d = sol(x1 - 1, y1 - 1, n, m, 1); cout << a + d - b - c << endl; } } |
// RS-232 TX module
// (c) fpga4fun.com KNJN LLC - 2003, 2004, 2005, 2006
//`define DEBUG // in DEBUG mode, we output one bit per clock cycle (useful for faster simulations)
`include "includes.v"
module async_transmitter(clk, TxD_start, TxD_data, TxD, TxD_busy);
input clk, TxD_start;
input [7:0] TxD_data;
output TxD, TxD_busy;
parameter ClkFrequency = `UART_CLK; // 40MHz
parameter Baud = `UART_BAUD;
parameter RegisterInputData = 1; // in RegisterInputData mode, the input doesn't have to stay valid while the character is been transmitted
// Baud generator
parameter BaudGeneratorAccWidth = 16;
reg [BaudGeneratorAccWidth:0] BaudGeneratorAcc;
wire [BaudGeneratorAccWidth:0] BaudGeneratorInc = ((Baud<<(BaudGeneratorAccWidth-4))+(ClkFrequency>>5))/(ClkFrequency>>4);
wire BaudTick = BaudGeneratorAcc[BaudGeneratorAccWidth];
wire TxD_busy;
always @(posedge clk) if(TxD_busy) BaudGeneratorAcc <= BaudGeneratorAcc[BaudGeneratorAccWidth-1:0] + BaudGeneratorInc;
// Transmitter state machine
reg [3:0] state;
wire TxD_ready = (state==0);
assign TxD_busy = ~TxD_ready;
reg [7:0] TxD_dataReg;
always @(posedge clk) if(TxD_ready & TxD_start) TxD_dataReg <= TxD_data;
wire [7:0] TxD_dataD = RegisterInputData ? TxD_dataReg : TxD_data;
always @(posedge clk)
case(state)
4'b0000: if(TxD_start) state <= 4'b0001;
4'b0001: if(BaudTick) state <= 4'b0100;
4'b0100: if(BaudTick) state <= 4'b1000; // start
4'b1000: if(BaudTick) state <= 4'b1001; // bit 0
4'b1001: if(BaudTick) state <= 4'b1010; // bit 1
4'b1010: if(BaudTick) state <= 4'b1011; // bit 2
4'b1011: if(BaudTick) state <= 4'b1100; // bit 3
4'b1100: if(BaudTick) state <= 4'b1101; // bit 4
4'b1101: if(BaudTick) state <= 4'b1110; // bit 5
4'b1110: if(BaudTick) state <= 4'b1111; // bit 6
4'b1111: if(BaudTick) state <= 4'b0010; // bit 7
4'b0010: if(BaudTick) state <= 4'b0011; // stop1
4'b0011: if(BaudTick) state <= 4'b0000; // stop2
default: if(BaudTick) state <= 4'b0000;
endcase
// Output mux
reg muxbit;
always @( * )
case(state[2:0])
3'd0: muxbit <= TxD_dataD[0];
3'd1: muxbit <= TxD_dataD[1];
3'd2: muxbit <= TxD_dataD[2];
3'd3: muxbit <= TxD_dataD[3];
3'd4: muxbit <= TxD_dataD[4];
3'd5: muxbit <= TxD_dataD[5];
3'd6: muxbit <= TxD_dataD[6];
3'd7: muxbit <= TxD_dataD[7];
endcase
// Put together the start, data and stop bits
reg TxD;
always @(posedge clk) TxD <= (state<4) | (state[3] & muxbit); // register the output to make it glitch free
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFBBN_BEHAVIORAL_V
`define SKY130_FD_SC_HS__SDFBBN_BEHAVIORAL_V
/**
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
* clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dfb_setdom_notify_pg/sky130_fd_sc_hs__u_dfb_setdom_notify_pg.v"
`include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v"
`celldefine
module sky130_fd_sc_hs__sdfbbn (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
// Local signals
wire RESET ;
wire SET ;
wire CLK ;
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire CLK_N_delayed ;
wire SET_B_delayed ;
wire RESET_B_delayed;
wire mux_out ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
wire cond_D ;
wire cond_SCD ;
wire cond_SCE ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
not not2 (CLK , CLK_N_delayed );
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hs__u_dfb_setdom_notify_pg u_dfb_setdom_notify_pg0 (buf_Q , SET, RESET, CLK, mux_out, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
assign cond_D = ( ( SCE_delayed === 1'b0 ) && condb );
assign cond_SCD = ( ( SCE_delayed === 1'b1 ) && condb );
assign cond_SCE = ( ( D_delayed !== SCD_delayed ) && condb );
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFBBN_BEHAVIORAL_V |
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <>
* Copyright (C) 2018 gatecat <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
(* techmap_celltype = "$alu" *)
module _80_gw1n_alu(A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
(* force_downto *)
output [Y_WIDTH-1:0] CO;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
(* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
(* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] BB = B_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] C = {CO, CI};
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
ALU #(.ALU_MODE(2)) // ADDSUB I3 ? add : sub
alu(.I0(AA[i]),
.I1(BB[i]),
.I3(~BI),
.CIN(C[i]),
.COUT(CO[i]),
.SUM(Y[i])
);
end endgenerate
assign X = AA ^ BB;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MXX = 3e5 + 5; int n, m; int a[MXX], ans[MXX]; bool ok(int x) { int mx = m - 1; for (int i = n - 1; i >= 0; i--) { if (a[i] <= mx) { if (a[i] + x >= mx) { ans[i] = mx; } else { ans[i] = a[i] + x; } } else { if (a[i] + x >= mx + m) ans[i] = mx; else ans[i] = (a[i] + x) % m; } mx = ans[i]; } for (int i = 0; i < n - 1; i++) { if (ans[i] > ans[i + 1]) { return false; } } return true; } bool ok2() { for (int i = 0; i < n - 1; i++) { if (a[i] > a[i + 1]) { return false; } } return true; } int main() { cin >> n >> m; for (int i = 0; i < n; i++) { cin >> a[i]; } if (ok2()) { return cout << 0 << endl, 0; } int lo = 0, hi = m - 1, mid, ans = -1; while (lo <= hi) { mid = (lo + hi) / 2; if (ok(mid)) { ans = mid; hi = mid - 1; } else { lo = mid + 1; } } cout << ans << endl; return 0; } |
/*
* Copyright 2017 Google Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`define IVERILOG_SIM
`define TEST_PROG "prog_load_out.list"
`include "top.v"
module top_test_load_out;
localparam WIDTH = 8;
localparam UART_WIDTH = $clog2(WIDTH);
localparam OUTPUT_CNT = 7;
reg clk = 1;
reg uart_clk = 0;
reg receiving = 0;
reg display = 0;
reg [UART_WIDTH-1 : 0] serial_cnt = 0;
reg [WIDTH-1 : 0] serial_data;
wire uart_tx;
reg [WIDTH-1 : 0] expected_output = 0;
always #2 clk = !clk;
always #4 uart_clk = !uart_clk;
top t(
.clk(clk),
.uart_tx_line(uart_tx));
always @ (posedge uart_clk) begin
if (receiving) begin
if (serial_cnt == WIDTH - 1 ) begin
receiving <= 0;
display <= 1;
end
serial_data[serial_cnt] <= uart_tx;
serial_cnt <= serial_cnt + 1;
end else if (display) begin
if (expected_output >= OUTPUT_CNT) begin
$display("Load and output test passed!\n");
$finish;
end
if (serial_data != expected_output) begin
$display("Load and output test failed!\n");
$display("Serial output:%d doesn't match expected_output:%d\n",
serial_data, expected_output);
$finish;
end
expected_output <= expected_output + 1;
display <= 0;
end else begin
if (uart_tx == 0) begin
receiving <= 1;
end
end
end
endmodule
|
//Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2014.4 (lin64) Build Tue Nov 18 16:48:31 MST 2014
//Date : Wed Sep 30 15:12:45 2015
//Host : rcswrka27 running 64-bit Ubuntu 10.04.4 LTS
//Command : generate_target Test_AXI_Master_simple_v1_0_hw_1_wrapper.bd
//Design : Test_AXI_Master_simple_v1_0_hw_1_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module Test_AXI_Master_simple_v1_0_hw_1_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
mosi_o,
ppm_signal_in,
sck_o,
ss_o);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
output mosi_o;
input ppm_signal_in;
output sck_o;
output [0:0]ss_o;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
wire mosi_o;
wire ppm_signal_in;
wire sck_o;
wire [0:0]ss_o;
Test_AXI_Master_simple_v1_0_hw_1 Test_AXI_Master_simple_v1_0_hw_1_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
.mosi_o(mosi_o),
.ppm_signal_in(ppm_signal_in),
.sck_o(sck_o),
.ss_o(ss_o));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100005; const int maxm = 300005; int n, m, cnt1, cnt2, ans; int head[maxn], Head[maxn]; int dis1[maxn], vis1[maxn]; int use1[maxn], use2[maxn]; int num[maxn], ok[maxn]; struct nood { int nex, to, w; int fr; }; nood e[maxm], E[maxm]; inline void jia(int u, int v, int c) { e[++cnt1].nex = head[u]; e[cnt1].fr = u; head[u] = cnt1; e[cnt1].to = v; e[cnt1].w = c; } inline void Jia(int u, int v, int c) { E[++cnt2].nex = Head[u]; Head[u] = cnt2; E[cnt2].to = v; E[cnt2].w = c; } inline void dfs(int u) { use1[u] = 1; for (int i = head[u]; i; i = e[i].nex) { int v = e[i].to; if (use1[v]) continue; dfs(v); } } inline void Dfs(int u) { use2[u] = 1; for (int i = Head[u]; i; i = E[i].nex) { int v = E[i].to; if (use2[v]) continue; Dfs(v); } } inline void spfa(int s) { queue<int> q; memset(dis1, 127 / 3, sizeof(dis1)); memset(vis1, 0, sizeof(vis1)); q.push(s), dis1[s] = 0; num[s] = 1, vis1[s] = 1; while (!q.empty()) { int u = q.front(); q.pop(); vis1[u] = 0; for (int i = Head[u]; i; i = E[i].nex) { int v = E[i].to; if (dis1[v] > dis1[u] + E[i].w) { dis1[v] = dis1[u] + E[i].w; if (!vis1[v]) { vis1[v] = 1; q.push(v); num[v]++; } if (num[v] > n) { printf( No n ); exit(0); } } } } } inline int read() { int sum = 0; char ch = getchar(); while (!isdigit(ch)) ch = getchar(); while (isdigit(ch)) sum = sum * 10 + (ch ^ 48), ch = getchar(); return sum; } int main() { n = read(); m = read(); for (int i = 1; i <= m; i++) { int u = read(); int v = read(); jia(u, v, 0); Jia(v, u, 0); } dfs(1); Dfs(n); for (int i = 1; i <= n; i++) if (use1[i] && use2[i]) ok[i] = 1; if (!use1[n]) return printf( No n ), 0; memset(E, 0, sizeof(E)); memset(Head, 0, sizeof(Head)); cnt2 = 0; ok[1] = 1, ok[n] = 1; for (int i = 1; i <= m; i++) { int u = e[i].fr; int v = e[i].to; if (ok[u] && ok[v]) { Jia(u, v, -1); Jia(v, u, 2); } } spfa(1); printf( Yes n ); for (int i = 1; i <= m; i++) { int u = e[i].fr; int v = e[i].to; if (ok[u] && ok[v]) printf( %d n , abs(dis1[u] - dis1[v])); else printf( 1 n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; const signed long long Infinity = 1000000001; const long double Epsilon = 1e-9; template <typename T, typename U> ostream& operator<<(ostream& os, const pair<T, U>& p) { return os << ( << p.first << , << p.second << ) ; } template <typename T> ostream& operator<<(ostream& os, const vector<T>& V) { os << [ ; for (__typeof(V.begin()) i = V.begin(); i != V.end(); ++i) os << *i << (i - V.begin() + 1 == ((int)V.size()) ? : , ); os << ] n ; return os; } template <typename T> ostream& operator<<(ostream& os, const set<T>& S) { os << ( ; for (__typeof(S.begin()) i = S.begin(); i != S.end(); ++i) os << *i << (*i == *S.rbegin() ? : , ); os << ) n ; return os; } template <typename T, typename U> ostream& operator<<(ostream& os, const map<T, U>& M) { os << { ; for (__typeof(M.begin()) i = M.begin(); i != M.end(); ++i) os << *i << (i->first == M.rbegin()->first ? : , ); os << } n ; return os; } int N, K; void read_data() { scanf( %d %d , &N, &K); } void solve() { if (N == K) { printf( -1 n ); } else { for (int(i) = (1); (i) <= (N - K - 1); (i)++) printf( %d , i + 1); printf( 1 ); for (int(i) = (N - K + 1); (i) <= (N); (i)++) printf( %d , i); } } int main() { read_data(); solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 0; int n, k, x; string s; vector<int> v; int main() { int a, b, c, d, e, f; int cnt = 0; scanf( %d%d%d%d%d%d , &a, &b, &c, &d, &e, &f); if (a == d) cnt++; if (b == e) cnt++; if (c == f) cnt++; if (cnt >= 1) { printf( YES n ); } else { printf( NO n ); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O221A_BLACKBOX_V
`define SKY130_FD_SC_HS__O221A_BLACKBOX_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o221a (
X ,
A1,
A2,
B1,
B2,
C1
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O221A_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int n, men = 0, pluss = 0, nol = 0; long long a, ans = 0; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> n; for (int i = 1; i <= n; i++) { cin >> a; if (a < 0) { ans += (-1 - a); men++; } else if (a > 0) { ans += (a - 1); pluss++; } else { nol++; } } if (nol > 0) { cout << ans + nol << endl; } else { if (men % 2 == 0) { cout << ans << endl; } else { cout << ans + 2 << endl; } } } |
module VgaRenderer
(
input RENDERER_CLK ,
// --------- FROM VGA SYNC GENERATOR ---------
input wire [10:0] RENDERER_POS_X ,
input wire [9:0] RENDERER_POS_Y ,
input wire RENDERER_ENABLE,
input wire RENDERER_SEL_BUFF,
// -------------------------------------------
// --------------- TO MEMORY -----------------
input wire [ 7:0] RENDERER_DATA ,
output wire [18:0] RENDERER_ADDR ,
output wire RENDERER_WE ,
output wire RENDERER_OE ,
output wire RENDERER_CE ,
// -------------------------------------------
// ---------------- TO VGA -------------------
output wire [ 4:0] RENDERER_RED ,
output wire [ 4:0] RENDERER_GREEN ,
output wire [ 4:0] RENDERER_BLUE
// -------------------------------------------
);
localparam RENDERER_COLOR_FORMAT_332 = 2'b00;
localparam RENDERER_COLOR_FORMAT_555 = 2'b01;
localparam RENDERER_RESOLUTION_H = 10'd400;
localparam RENDERER_RESOLUTION_V = 10'd300;
localparam RENDERER_PIXEL_WITH = 10'd2;
assign RENDERER_ADDR = RENDERER_RESOLUTION_H * ( RENDERER_POS_Y / RENDERER_PIXEL_WITH )
+ ( RENDERER_POS_X / RENDERER_PIXEL_WITH ) + RENDERER_RESOLUTION_H * RENDERER_RESOLUTION_V * SelectBuffer;
reg SelectBuffer = 0;
always @( posedge RENDERER_CLK )
begin
if( RENDERER_POS_Y == 0 && RENDERER_POS_X == 0 )
SelectBuffer <= RENDERER_SEL_BUFF;
end
function [4:0] GetColorRed( input [2:0] colorFormat, input [7:0] value );
begin
GetColorRed = value[ 2:0 ] << 2;
end
endfunction
function [4:0] GetColorGreen( input [2:0] colorFormat, input [7:0] value );
begin
GetColorGreen = value[ 5:3 ] << 2;
end
endfunction
function [4:0] GetColorBlue( input [2:0] colorFormat, input [7:0] value );
begin
GetColorBlue = value[ 7:6 ] << 2;
end
endfunction
assign RENDERER_RED = ( RENDERER_ENABLE ) ? GetColorRed ( RENDERER_COLOR_FORMAT_332, RENDERER_DATA ) : 5'b00000;
assign RENDERER_GREEN = ( RENDERER_ENABLE ) ? GetColorGreen( RENDERER_COLOR_FORMAT_332, RENDERER_DATA ) : 5'b00000;
assign RENDERER_BLUE = ( RENDERER_ENABLE ) ? GetColorBlue ( RENDERER_COLOR_FORMAT_332, RENDERER_DATA ) : 5'b00000;
assign RENDERER_CE = 1'b0;
assign RENDERER_WE = 1'b1;
assign RENDERER_OE = 1'b0;
endmodule |
#include <bits/stdc++.h> using namespace std; inline int read(int f = 1, int x = 0, char ch = ) { while (!isdigit(ch = getchar())) if (ch == - ) f = -1; while (isdigit(ch)) x = x * 10 + ch - 0 , ch = getchar(); return f * x; } const int N = 1e2 + 5; int n, c[2], p[N], q[N], f[2][N][N][N]; int main() { n = read(); for (int i = 1; i <= n; ++i) p[i] = q[i] = read(), p[i] &= 1, c[p[i]] += q[i] != 0; c[0] = n / 2 - c[0], c[1] = n - n / 2 - c[1]; memset(f, 0x3f, sizeof(f)), f[0][0][0][0] = f[1][0][0][0] = 0; for (int i = 1; i <= n; ++i) for (int j = 0; j <= c[0]; ++j) for (int k = 0; k <= c[1]; ++k) if (q[i]) f[p[i]][i][j][k] = min(f[0][i - 1][j][k] + (0 ^ p[i]), f[1][i - 1][j][k] + (1 ^ p[i])); else { if (j) f[0][i][j][k] = min(f[0][i][j][k], f[0][i - 1][j - 1][k]), f[0][i][j][k] = min(f[0][i][j][k], f[1][i - 1][j - 1][k] + 1); if (k) f[1][i][j][k] = min(f[1][i][j][k], f[1][i - 1][j][k - 1]), f[1][i][j][k] = min(f[1][i][j][k], f[0][i - 1][j][k - 1] + 1); } printf( %d n , min(f[0][n][c[0]][c[1]], f[1][n][c[0]][c[1]])); return 0; } |
#include <bits/stdc++.h> using namespace std; long long arr[200005], lazy[4 * 200005], seg[4 * 200005]; void build(int node, int start, int end) { int mid = (start + end) / 2; if (start == end) { lazy[node] = 0; seg[node] = arr[start]; return; } build(2 * node, start, mid); build(2 * node + 1, mid + 1, end); seg[node] = min(seg[2 * node], seg[2 * node + 1]); } void update(int node, int start, int end, int left, int right, long long val) { int mid = (start + end) / 2; if ((start > right) || (end < left)) return; if ((left <= start) && (end <= right)) { lazy[node] += val; seg[node] += val; return; } else { update(2 * node, start, mid, left, right, val); update(2 * node + 1, mid + 1, end, left, right, val); seg[node] = min(seg[2 * node], seg[2 * node + 1]) + lazy[node]; } } long long query(int node, int start, int end, int left, int right) { int mid = (start + end) / 2; if ((start > right) || (end < left)) return LLONG_MAX; if ((left <= start) && (end <= right)) return seg[node]; else return lazy[node] + min(query(2 * node, start, mid, left, right), query(2 * node + 1, mid + 1, end, left, right)); } int main() { int n, m, lf, rg; long long v; char c; scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %lld , &arr[i]); build(1, 0, n - 1); scanf( %d , &m); for (int i = 0; i < m; i++) { scanf( %d%d , &lf, &rg); c = getchar(); if (c != n ) { scanf( %lld , &v); if (lf <= rg) update(1, 0, n - 1, lf, rg, v); else { update(1, 0, n - 1, lf, n - 1, v); update(1, 0, n - 1, 0, rg, v); } } else { if (lf <= rg) printf( %lld n , query(1, 0, n - 1, lf, rg)); else printf( %lld n , min(query(1, 0, n - 1, lf, n - 1), query(1, 0, n - 1, 0, rg))); } } return 0; } |
#include <bits/stdc++.h> using namespace std; int const MAXN = 5e5 + 10; int n, a[MAXN], ans; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int i = 1; i < n; i++) { if (a[i] != a[i + 1]) { int pt = i + 1, tam = 1; while (a[pt] != a[pt + 1] && pt != n) pt++, tam++; if (a[i] == a[pt]) for (int j = i; j <= pt; j++) a[j] = a[i]; else { tam--; for (int j = i; j <= i + tam / 2; j++) a[j] = a[i]; for (int j = i + tam / 2 + 1; j <= pt; j++) a[j] = a[pt]; } ans = max(ans, tam / 2); } } printf( %d n , ans); for (int i = 1; i <= n; i++) printf( %d , a[i]); printf( n ); } |
#include <bits/stdc++.h> using namespace std; const int M = 1000000007; int n, m, t; long long dp[61][31][31]; int arr[61]; long long solve(int ind, int x, int y) { if (x > 3 && y > 0 && x + y == t) return 1; if (ind == n + m + 1) return 0; long long &ret = dp[ind][x][y]; if (ret != -1) return ret; ret = solve(ind + 1, x, y); if (x < n && arr[ind] == 1) ret += solve(ind + 1, x + 1, y); if (y < m && arr[ind] == 2) ret += solve(ind + 1, x, y + 1); return ret; } int main() { scanf( %d%d%d , &n, &m, &t); int i = 0; for (; i < n; i++) arr[i] = 1; for (; i < n + m; i++) arr[i] = 2; memset(dp, -1, sizeof dp); printf( %lld n , solve(0, 0, 0)); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLXBP_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__DLXBP_PP_BLACKBOX_V
/**
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlxbp (
Q ,
Q_N ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLXBP_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int MAX = 2e5 + 3; string s, p; int F[MAX][2]; void solve() { cin >> s >> p; F[0][0] = F[0][1] = 0; for (int i = 1; i <= p.size(); ++i) { for (int j = 0; j < 2; ++j) { F[i][j] = F[i - 1][j]; } ++F[i][p[i - 1] - 0 ]; } long long int ans = 0; for (int i = 0; i < s.size(); ++i) { int c = s[i] - 0 ; for (int j = 0; j < 2; ++j) { ans += abs(c - j) * (F[p.size() - s.size() + i + 1][j] - F[i][j]); } } cout << ans << n ; } int main() { ios_base::sync_with_stdio(false); solve(); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21A_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__O21A_PP_BLACKBOX_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o21a (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21A_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; namespace math { template <typename T> T gcd(T a, T b) { if (a < 0) a = -a; if (b < 0) b = -b; while (b > 0) { T r = a % b; a = b; b = r; } return a; } } // namespace math template <typename C> int SZ(const C& c) { return (int)c.size(); } template <size_t n, class... Types> struct TupleHashHelper { static std::size_t calc(const std::tuple<Types...>& t) { using std::size_t; std::hash<typename std::tuple_element<n - 1, std::tuple<Types...>>::type> elemHash; return elemHash(std::get<n - 1>(t)) + 31013 * TupleHashHelper<n - 1, Types...>::calc(t); } }; template <class... Types> struct TupleHashHelper<0, Types...> { static std::size_t calc(const std::tuple<Types...>&) { return 0; } }; template <class... Types> struct TupleHash { std::size_t operator()(const std::tuple<Types...>& t) const { static const size_t n = std::tuple_size<std::tuple<Types...>>::value; return TupleHashHelper<n, Types...>::calc(t); } }; class Solution { public: void solve(std::istream& in, std::ostream& out) { int n; in >> n; vector<int> x(n), y(n); for (int i = 0; i < n; ++i) in >> x[i] >> y[i]; unordered_map<tuple<int, int, int>, set<int>, TupleHash<int, int, int>> lines; for (int i = 0; i < n; ++i) for (int j = i + 1; j < n; ++j) { using math::gcd; int a = y[j] - y[i], b = x[i] - x[j]; int c = -a * x[i] - b * y[i]; int d = gcd(gcd(a, b), c); if (a < 0) { a = -a; b = -b; c = -c; } else if (a == 0 && b < 0) { b = -b; c = -c; } auto t = make_tuple(a / d, b / d, c / d); lines[t].insert(i); lines[t].insert(j); } long long res = (long long)n * (n - 1) * (n - 2) / 6; for (const auto& p : lines) { long long s = SZ(p.second); res -= s * (s - 1) * (s - 2) / 6; } out << res << endl; } }; void solve(std::istream& in, std::ostream& out) { out << std::setprecision(12); Solution solution; solution.solve(in, out); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); istream& in = cin; ostream& out = cout; solve(in, out); return 0; } |
# include <bits/stdc++.h> using namespace std; int main(){ ios::sync_with_stdio(false); int t; cin>>t; while(t--){ int n,m; cin>>n>>m; int ans=0; int a[101]={0}; for(int i=0; i<n;i++){ int x; cin>>x; a[x]=1; } for(int i=0;i<m;i++){ int x; cin>>x; if(a[x]==1) ans++; } cout<<ans<< n ; } return 0; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:13:59 12/01/2015
// Design Name: spi_master
// Module Name: /home/jorge/Documentos/SPI_SD/spi_master_testbench.v
// Project Name: SPI_SD
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: spi_master
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module spi_master_testbench;
// Inputs
reg clk;
reg rst;
reg sssd_in;
reg start;
reg miso;
reg [7:0] data_in;
// Outputs
wire mosi;
wire sck;
wire ss;
wire sssd_out;
wire [7:0] data_out;
wire busy;
wire new_data;
//parameters
parameter PERIOD = 10;
parameter real DUTY_CYCLE = 0.5;
parameter OFFSET = 0;
// Instantiate the Unit Under Test (UUT)
spi_master uut (
.clk(clk),
.rst(rst),
.sssd_in(sssd_in),
.start(start),
.miso(miso),
.data_in(data_in),
.mosi(mosi),
.sck(sck),
.ss(ss),
.ss(sssd_out),
.data_out(data_out),
.busy(busy),
.new_data(new_data)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 1;
sssd_in = 1;
start = 0;
miso = 0;
data_in = 0;
#OFFSET
forever
begin
clk = 1'b1;
#(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b0;
#(PERIOD*DUTY_CYCLE);
end
end
initial begin
#OFFSET
forever
begin
miso = 1'b1;
#(3*PERIOD) miso = 1'b0;
#(3*PERIOD);
end
end
initial begin
// Wait 10 ns for global reset to finish
#10;
rst=0;
start=1;
sssd_in=0;
data_in=01011100;
#10
start=0;
@(*)begin
if (new_data)begin
#20
rst=1;
#10
rst=0;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int f[100010], g[100010]; int _Max(int x, int y) { return x > y ? x : y; } void upd(int x, int ans, int k) { if (f[x] < ans) f[x] = ans, g[x] = k; else if (f[x] == ans && k < g[x]) g[x] = k; } int main() { int n, L, p, t, i, j, l = 1, r = 0, x, y, s = 0, ans = 0; scanf( %d%d%d%d , &L, &n, &p, &t); for (i = 1; i <= n; i++) { scanf( %d%d , &x, &y); while (r < i - 1 && g[r + 1] + t <= y) r++; while (l < i && g[l] + t <= x) s = _Max(s, f[l++]); f[i] = -1; upd(i, s + (y - x) / p, x + (y - x) / p * p); for (j = l; j <= r; j++) upd(i, f[j] + (y - g[j] - t) / p, g[j] + t + (y - g[j] - t) / p * p); ans = _Max(ans, f[i]); } printf( %d n , ans); return 0; } |
`timescale 1us/100ns
module top;
reg pass = 1'b1;
real ra = 1.0, rb = 2.0;
wire real rpow;
/* Real Power. */
assign #1 rpow = ra ** rb;
initial begin
#0.9;
if (rpow == 1.0) begin
pass = 1'b0;
$display("Real: power value not delayed.");
end
#0.1;
#0;
if (rpow != 1.0) begin
pass = 1'b0;
$display("Real: power value not correct, expected 1.0 got %g.", rpow);
end
#1 ra = 2.0;
#2;
if (rpow != 4.0) begin
pass = 1'b0;
$display("Real: power value not correct, expected 4.0 got %g.", rpow);
end
#1 ra = 0.0;
#2;
if (rpow != 0.0) begin
pass = 1'b0;
$display("Real: power value not correct, expected 0.0 got %g.", rpow);
end
#1 ra = 10.0;
#2;
if (rpow != 100.0) begin
pass = 1'b0;
$display("Real: power value not correct, expected 100.0 got %g.", rpow);
end
#1 ra = 0.0; rb = -1.0;
#2;
$display("0.0 ** -1.0 = %g", rpow);
#1 ra = -1.0; rb = 2.5;
#2;
$display("-1.0 ** 2.5 = %g", rpow);
if (pass) $display("PASSED");
end
endmodule
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_delta (clock, reset, enable, test_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 1;
parameter min = 1;
parameter max = 1;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input [width-1:0] test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_DELTA";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/assert_delta_logic.v"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_SVA
`include "./sva05/assert_delta_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_delta_psl_logic.v"
`else
`endmodule // ovl_delta
`endif
|
#include <bits/stdc++.h> using namespace std; int main() { int x, y; cin >> x >> y; if (x > y) { int t = x; x = y; y = t; } cout << x << << (y - x) / 2 << endl; } |
#include <bits/stdc++.h> using namespace std; const long long BINF = 1e18 + 10; signed main() { ios_base::sync_with_stdio(false); long long T; cin >> T; while (T--) { long long n, a, b; cin >> n >> a >> b; vector<long long> c(n); for (auto &it : c) { char kek; cin >> kek; it = kek - 0 ; } vector<vector<long long>> dp(n + 1, vector<long long>(2, BINF)); dp[0][0] = b; for (long long i = 0; i < n; i++) { dp[i + 1][1] = min(dp[i][0] + 2 * (a + b), dp[i][1] + a + 2 * b); if (!c[i] && (i + 1 == n || !c[i + 1])) { dp[i + 1][0] = min(dp[i][0] + a + b, dp[i][1] + 2 * a + b); } } cout << dp[n][0] << n ; } } |
#include <bits/stdc++.h> using namespace std; queue<int> q[300005]; set<int> all; int main() { int n, quer; scanf( %d%d , &n, &quer); int t, x, v; int in = 1; for (int i = 1; i <= quer; i++) { scanf( %d%d , &t, &x); if (t == 1) { q[x].push(in); all.insert(in); in++; } else if (t == 2) { while (!q[x].empty()) { all.erase(q[x].front()); q[x].pop(); } } else { while (all.size() >= 1) { v = *all.begin(); if (v <= x) all.erase(v); else break; } } printf( %d n , all.size()); } } |
#include <bits/stdc++.h> using namespace std; void solve() { string s; cin >> s; int n = s.size(); if (s[0] == b && s[n - 1] == a ) { s[0] = a ; } else if (s[0] == a && s[n - 1] == b ) { s[n - 1] = a ; } cout << s << n ; } int main() { int t; cin >> t; while (t--) { solve(); } return 0; } |
// spw_light_mm_interconnect_0_avalon_st_adapter.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 17.1 593
`timescale 1 ps / 1 ps
module spw_light_mm_interconnect_0_avalon_st_adapter #(
parameter inBitsPerSymbol = 34,
parameter inUsePackets = 0,
parameter inDataWidth = 34,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 34,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [33:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [33:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
spw_light_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
`include "bsg_defines.v"
module bsg_reduce_segmented #(parameter `BSG_INV_PARAM(segments_p )
,parameter `BSG_INV_PARAM(segment_width_p )
, parameter xor_p = 0
, parameter and_p = 0
, parameter or_p = 0
, parameter nor_p = 0
)
(input [segments_p*segment_width_p-1:0] i
, output [segments_p-1:0] o
);
// synopsys translate_off
initial
assert( $countones({xor_p[0], and_p[0], or_p[0], nor_p[0]}) == 1)
else $error("%m: exactly one function may be selected\n");
// synopsys translate_on
genvar j;
for (j = 0; j < segments_p; j=j+1)
begin: rof2
if (xor_p)
assign o[j] = ^i[(j*segment_width_p)+:segment_width_p];
else if (and_p)
assign o[j] = &i[(j*segment_width_p)+:segment_width_p];
else if (or_p)
assign o[j] = |i[(j*segment_width_p)+:segment_width_p];
else if (nor_p)
assign o[j] = ~(|i[(j*segment_width_p)+:segment_width_p]);
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_reduce_segmented)
|
#include <bits/stdc++.h> using namespace std; long long h[1000010], dp[1000010][2]; int n; int main() { int i, j; while (scanf( %d , &n) != EOF) { for (i = 1; i <= n; i++) scanf( %lld , &h[i]), h[i]--; for (i = 1; i <= n; i++) { dp[i][0] = (dp[i - 1][0] + dp[i - 1][1] * min(h[i], h[i - 1]) + h[i]) % 1000000007; dp[i][1] = (min(h[i + 1], h[i]) + min(min(h[i], h[i - 1]), h[i + 1]) * dp[i - 1][1]) % 1000000007; } printf( %d n , dp[n][0]); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int arr[101]; int n; cin >> n; for (int i = 0; i < n; i++) { cin >> arr[i]; } sort(arr, arr + n); for (int i = 0; i < n; i++) { cout << arr[i] << ; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__UDP_DFF_PS_TB_V
`define SKY130_FD_SC_HVL__UDP_DFF_PS_TB_V
/**
* udp_dff$PS: Positive edge triggered D flip-flop with active high
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__udp_dff_ps.v"
module top();
// Inputs are registered
reg D;
reg SET;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SET = 1'bX;
#20 D = 1'b0;
#40 SET = 1'b0;
#60 D = 1'b1;
#80 SET = 1'b1;
#100 D = 1'b0;
#120 SET = 1'b0;
#140 SET = 1'b1;
#160 D = 1'b1;
#180 SET = 1'bx;
#200 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hvl__udp_dff$PS dut (.D(D), .SET(SET), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__UDP_DFF_PS_TB_V
|
#include <bits/stdc++.h> using namespace std; long long const M = 2e5 + 10, M2 = 1e7 + 10, mod = 1e9 + 7, inf = 1e9 + 10, sq = 450; long long a[M], cnt[M], t1, t2, t0, x1; pair<long long, long long> good, ans; bool check(long long ind, long long sum) { if (sum - ind > x1) return 0; long long res = t2 * ind + t1 * (sum - ind); if (res >= sum * t0) return 1; return 0; } int32_t main() { long long x2; cin >> t1 >> t2 >> x1 >> x2 >> t0; bool flag = 0; good = make_pair(-1, -1); if (t1 > t2) swap(t1, t2), swap(x1, x2), flag = 1; for (long long i = 1; i <= x1 + x2; i++) { long long lo = 0, hi = min(x2, i); if (!check(hi, i)) continue; while (hi > lo + 1) { long long mid = (lo + hi) / 2; if (check(mid, i)) hi = mid; else lo = mid + 1; } long long best = hi; if (check(lo, i)) best = lo; long long res = best * t2 + t1 * (i - best); if (good.first == -1 || (res * good.second <= good.first * i)) good = make_pair(res, i), ans = make_pair(best, i - best); } swap(ans.first, ans.second); if (flag) cout << ans.second << << ans.first; else cout << ans.first << << ans.second; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR4BB_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__OR4BB_FUNCTIONAL_PP_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__or4bb (
X ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , D_N, C_N );
or or0 (or0_out_X , B, A, nand0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR4BB_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int kN = 2e5 + 10; const long long kInf = 1e18 + 10; int n, q; long long a[kN], b[kN]; vector<int> g[kN]; int in[kN], out[kN], dfs_clock; pair<long long, long long> p1[kN], p2[kN]; void dfs(int u) { in[u] = ++dfs_clock; for (int v : g[u]) { a[v] += a[u], b[v] += b[u]; dfs(v); } out[u] = dfs_clock; } struct SegmentTree { pair<long long, long long> pos[kN << 2]; struct Node { long long a, b; long long wait, tg; }; Node seg[kN << 2]; void init(pair<long long, long long> *a) { for (int i = 1; i <= n; i++) pos[i] = a[i]; } void push_down(int o) { if (seg[o].tg == 0) return; seg[(o << 1)].tg += seg[o].tg, seg[(o << 1 | 1)].tg += seg[o].tg; seg[(o << 1)].wait -= seg[o].tg, seg[(o << 1 | 1)].wait -= seg[o].tg; seg[(o << 1)].a += seg[o].tg, seg[(o << 1 | 1)].a += seg[o].tg; seg[o].tg = 0; } void push_up(int o) { long long a1 = seg[(o << 1)].a, b1 = seg[(o << 1)].b; long long a2 = seg[(o << 1 | 1)].a, b2 = seg[(o << 1 | 1)].b; if (a1 * b1 > a2 * b2) seg[o].a = a1, seg[o].b = b1; else seg[o].a = a2, seg[o].b = b2; seg[o].wait = min(seg[(o << 1)].wait, seg[(o << 1 | 1)].wait); if (b1 != b2) { long long tmp = (a2 * b2 - a1 * b1) / (b1 - b2); if (tmp >= 0) seg[o].wait = min(seg[o].wait, tmp); } } void build(int l = 1, int r = n, int o = 1) { if (l == r) { seg[o] = {pos[l].first, pos[l].second, kInf, 0}; return; } int m = (l + r) >> 1; build(l, m, (o << 1)), build(m + 1, r, (o << 1 | 1)); push_up(o); } void update(int ql, int qr, int x, int l = 1, int r = n, int o = 1) { if (ql > r || qr < l) return; if (ql <= l && r <= qr && seg[o].wait >= x) { seg[o].tg += x, seg[o].wait -= x, seg[o].a += x; return; } push_down(o); int m = (l + r) >> 1; if (ql <= m) update(ql, qr, x, l, m, (o << 1)); if (qr > m) update(ql, qr, x, m + 1, r, (o << 1 | 1)); push_up(o); } long long query(int ql, int qr, int l = 1, int r = n, int o = 1) { if (ql > r || qr < l) return -kInf; if (ql <= l && r <= qr) return seg[o].a * seg[o].b; push_down(o); int m = (l + r) >> 1; return max(query(ql, qr, l, m, (o << 1)), query(ql, qr, m + 1, r, (o << 1 | 1))); } }; SegmentTree t1, t2; int main() { scanf( %d%d , &n, &q); for (int i = 2, x; i <= n; i++) { scanf( %d , &x); g[x].push_back(i); } for (int i = 1; i <= n; i++) scanf( %lld , a + i); for (int i = 1; i <= n; i++) scanf( %lld , b + i); dfs(1); for (int i = 1; i <= n; i++) { p1[in[i]] = {a[i], b[i]}, p2[in[i]] = {a[i], -b[i]}; } t1.init(p1), t2.init(p2); t1.build(), t2.build(); while (q--) { int op, v; scanf( %d%d , &op, &v); if (op == 1) { int x; scanf( %d , &x); t1.update(in[v], out[v], x); t2.update(in[v], out[v], x); } else { printf( %lld n , max(t1.query(in[v], out[v]), t2.query(in[v], out[v]))); } } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DECAP_BEHAVIORAL_V
`define SKY130_FD_SC_MS__DECAP_BEHAVIORAL_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__decap ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DECAP_BEHAVIORAL_V |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:45:52 11/03/2011
// Design Name: MGIA
// Module Name: /Users/kc5tja/tmp/kestrel/2/nexys2/uxa/mgia/T_uxa_mgia.v
// Project Name: mgia
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: MGIA
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module T_uxa_mgia;
// Inputs
reg CLK_I_50MHZ;
reg RST_I;
reg [15:0] DAT_O;
reg ack;
// Outputs
wire HSYNC_O;
wire VSYNC_O;
wire [2:0] RED_O;
wire [2:0] GRN_O;
wire [2:1] BLU_O;
// Instantiate the Unit Under Test (UUT)
MGIA uut (
.CLK_I_50MHZ(CLK_I_50MHZ),
.RST_I(RST_I),
.HSYNC_O(HSYNC_O),
.VSYNC_O(VSYNC_O),
.RED_O(RED_O),
.GRN_O(GRN_O),
.BLU_O(BLU_O),
.MGIA_DAT_I(DAT_O),
.MGIA_ACK_I(ack)
);
always begin
#10 CLK_I_50MHZ <= ~CLK_I_50MHZ;
DAT_O <= DAT_O ^ 16'h0505;
end
initial begin
// Initialize Inputs
CLK_I_50MHZ <= 0;
RST_I <= 1;
DAT_O <= 16'hF0A0;
ack <= 1'b1;
#100 RST_I <= 0;
end
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.4 (win64) Build Tue Nov 18 18:29:27 MST 2014
// Date : Tue Jun 30 15:23:38 2015
// Host : Vangelis-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/Vfor/Documents/GitHub/Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/Mem/Mem_stub.v
// Design : Mem
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tcsg324-3
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "dist_mem_gen_v8_0,Vivado 2014.4" *)
module Mem(a, d, dpra, clk, we, spo, dpo)
/* synthesis syn_black_box black_box_pad_pin="a[8:0],d[4:0],dpra[8:0],clk,we,spo[4:0],dpo[4:0]" */;
input [8:0]a;
input [4:0]d;
input [8:0]dpra;
input clk;
input we;
output [4:0]spo;
output [4:0]dpo;
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_ea_e
//
// Generated
// by: wig
// on: Mon Jun 26 08:25:04 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../generic.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_ea_e.v,v 1.3 2006/06/26 08:39:43 wig Exp $
// $Date: 2006/06/26 08:39:43 $
// $Log: inst_ea_e.v,v $
// Revision 1.3 2006/06/26 08:39:43 wig
// Update more testcases (up to generic)
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_ea_e
//
// No `defines in this module
module inst_ea_e
//
// Generated Module inst_ea
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of inst_ea_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
// Copyright (C) 2013 Simon Que
//
// This file is part of DuinoCube.
//
// DuinoCube is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// DuinoCube is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with DuinoCube. If not, see <http://www.gnu.org/licenses/>.
// Test bench for video display signal generator
// Note: this testbench simulates a realistic 50 MHz clock.
// Run it for 17 ms to get a full VGA refresh cycle.
`include "video_modes.vh"
module DisplayController_Test;
reg clk; // System clock
reg reset; // System reset
wire [`VIDEO_COUNT_WIDTH-1:0] h_pos; // Output scan position counters.
wire [`VIDEO_COUNT_WIDTH-1:0] v_pos;
wire hsync; // Horizontal sync
wire vsync; // Vertical sync
wire hblank; // Horizontal blanking indicator
wire vblank; // Vertical blanking indicator
DisplayController display_controller(.clk(clk),
.reset(reset),
.h_pos(h_pos),
.v_pos(v_pos));
DisplayTiming display_timing(.h_pos(h_pos), .v_pos(v_pos),
.h_sync(hsync), .v_sync(vsync),
.h_blank(hblank), .v_blank(vblank));
initial begin
clk = 0;
reset = 0;
// Test a reset.
#100 reset = 1;
#200 reset = 0;
end
// 50 MHz clock.
always
#10 clk = !clk;
endmodule
|
#include <bits/stdc++.h> const int N = (1 << 19) - 1; using namespace std; int n; double dp[N + 1], a[20][20]; int main() { scanf( %d , &n); for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) scanf( %lf , &a[i][j]); } dp[(1 << n) - 1] = 1; for (int s = ((1 << n) - 1); s > 0; s--) { int c = 0; for (int i = 0; i < n; i++) { if ((1 << i) & s) c++; } if (c < 2) continue; for (int i = 0; i < n; i++) if ((1 << i) & (s)) for (int j = 0; j < n; j++) { if (i == j) continue; if ((1 << j) & s) { dp[s ^ (1 << i)] += dp[s] * a[j][i] / c / (c - 1); dp[s ^ (1 << j)] += dp[s] * a[i][j] / c / (c - 1); } } } for (int i = 1; i < (1 << n); i <<= 1) { printf( %.10f , dp[i]); } } |
#include <bits/stdc++.h> const long long max9 = 10 + 1e9, max6 = 10 + 1e6, max12 = 10 + 1e12, max15 = 10 + 1e15; const long long min6 = -1 * max6, min9 = -1 * max9, min12 = -1 * max12, min15 = -1 * max15; const long long R = 7 + 1e9, NN = 10 + 1e5; using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long n; long long k; cin >> n >> k; long long mn = n * (n + 1); mn /= 2; long long nn = n / 2 - 1, mx = 2 * (nn + 1) * n - nn * (nn + 1); if (n % 2) mx += nn + 2; if (k < mn) { cout << -1; return 0; } if (k >= mx) { cout << mx << endl; for (int i = (0); i < (n); ++i) cout << i + 1 << ; cout << endl; for (int i = (0); i < (n); ++i) cout << n - i << ; return 0; } vector<int> a(n); long long l = 0, last = n; for (int i = (0); i < (n); ++i) a[i] = i + 1; long long ben = k - mn; for (int i = (0); i < (n / 2); ++i) { if (ben == 0) break; long long test = a[i] + ben; if (test > last) { a[i] = last; a[last - 1] = i + 1; ben -= last - i - 1; last--; } else { a[i] = test; a[test - 1] = i + 1; break; } } long long sum = 0; for (int i = (0); i < (n); ++i) sum += max(i + 1, a[i]); cout << sum << endl; for (int i = (0); i < (n); ++i) cout << i + 1 << ; cout << endl; for (int i = (0); i < (n); ++i) cout << a[i] << ; return 0; } |
#include <bits/stdc++.h> using namespace std; constexpr int mod = 998244353; int x[5], y[5]; int px[32], nx[32], py[32], ny[32]; int dp[32][20][20][20][20][2][2]; void add(int& x, const int& y) { x += y; if (x >= mod) x -= mod; } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); int n, m; cin >> n >> m; for (int i = 0; i < n; i += 1) cin >> x[i] >> y[i]; for (int mask = 0; mask < (1 << n); mask += 1) for (int i = 0; i < n; i += 1) if ((mask >> i) & 1) { (x[i] > 0 ? px : nx)[mask] += abs(x[i]); (y[i] > 0 ? py : ny)[mask] += abs(y[i]); } dp[0][0][0][0][0][0][0] = 1; for (int i = 0; i < (30); i += 1) for (int cpx = 0; cpx < (20); cpx += 1) for (int cnx = 0; cnx < (20); cnx += 1) for (int cpy = 0; cpy < (20); cpy += 1) for (int cny = 0; cny < (20); cny += 1) for (int bx = 0; bx < (2); bx += 1) for (int by = 0; by < (2); by += 1) for (int mask = 0; mask < (1 << n); mask += 1) if (dp[i][cpx][cnx][cpy][cny][bx][by]) { if (0) cout << i << << cpx << << cny << << cpy << << cny << << bx << << by << << dp[i][cpx][cnx][cpy][cny][bx][by] << endl; int npx = cpx + px[mask], nnx = cnx + nx[mask], npy = cpy + py[mask], nny = cny + ny[mask]; if ((npx ^ nnx) & 1) continue; if ((npy ^ nny) & 1) continue; int cx = npx & 1, mx = (m >> i) & 1; int cy = npy & 1, my = (m >> i) & 1; add(dp[i + 1][npx >> 1][nnx >> 1][npy >> 1][nny >> 1] [cx != mx ? (cx > mx) : bx] [cy != my ? (cy > my) : by], dp[i][cpx][cnx][cpy][cny][bx][by]); } cout << (dp[30][0][0][0][0][0][0] + mod - 1) % mod; return 0; } |
#include <bits/stdc++.h> using namespace std; int N, M; pair<pair<long long, long long>, int> range[200000 - 1]; pair<long long, int> bridge[200000]; priority_queue<pair<long long, int>, vector<pair<long long, int> >, greater<pair<long long, int> > > rends; int ans[200000 - 1]; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> N >> M; long long prevL, prevR; cin >> prevL >> prevR; for (int i = 0; i < N - 1; i++) { long long L, R; cin >> L >> R; range[i] = {{L - prevR, R - prevL}, i}; prevL = L; prevR = R; } for (int i = 0; i < M; i++) { cin >> bridge[i].first; bridge[i].second = i; } sort(range, range + N - 1); sort(bridge, bridge + M); int ind = 0; for (int i = 0; i < M; i++) { while (ind < N - 1 && bridge[i].first >= range[ind].first.first) { rends.push(make_pair(range[ind].first.second, range[ind].second)); ind++; } if (!rends.empty()) { pair<long long, int> e = rends.top(); rends.pop(); if (e.first >= bridge[i].first) { ans[e.second] = bridge[i].second + 1; } else { cout << No << endl; return 0; } } } if (ind < N - 1 || !rends.empty()) { cout << No << endl; return 0; } cout << Yes << n ; cout << ans[0]; for (int i = 1; i < N - 1; i++) { cout << << ans[i]; } cout << endl; return 0; } |
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: afifo.v
// /___/ /\ Date Last Modified: $Date: 2010/12/02 07:21:45 $
// \ \ / \ Date Created: Oct 21 2008
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: A generic synchronous fifo.
//Reference:
//Revision History: 1.2 11/8/2010 Removed unused signals.
//*****************************************************************************
`timescale 1ps/1ps
module afifo #
(
parameter TCQ = 100,
parameter DSIZE = 32,
parameter FIFO_DEPTH = 16,
parameter ASIZE = 4,
parameter SYNC = 1 // only has always '1' logic.
)
(
input wr_clk,
input rst,
input wr_en,
input [DSIZE-1:0] wr_data,
input rd_en,
input rd_clk,
output [DSIZE-1:0] rd_data,
output reg full,
output reg empty,
output reg almost_full
);
// memory array
reg [DSIZE-1:0] mem [0:FIFO_DEPTH-1];
//Read Capture Logic
// if Sync = 1, then no need to remove metastability logic because wrclk = rdclk
reg [ASIZE:0] rd_capture_ptr;
reg [ASIZE:0] pre_rd_capture_gray_ptr;
reg [ASIZE:0] rd_capture_gray_ptr;
reg [ASIZE:0] wr_capture_ptr;
reg [ASIZE:0] pre_wr_capture_gray_ptr;
reg [ASIZE:0] wr_capture_gray_ptr;
wire [ASIZE:0] buf_avail;
wire [ASIZE:0] buf_filled;
wire [ASIZE-1:0] wr_addr, rd_addr;
reg [ASIZE:0] wr_ptr, rd_ptr,rd_ptr_cp;
integer i,j,k;
// for design that use the same clock for both read and write
generate
if (SYNC == 1) begin: RDSYNC
always @ (rd_ptr)
rd_capture_ptr = rd_ptr;
end
endgenerate
//capture the wr_gray_pointers to rd_clk domains and convert the gray pointers to binary pointers
// before do comparison.
// if Sync = 1, then no need to remove metastability logic because wrclk = rdclk
generate
if (SYNC == 1) begin: WRSYNC
always @ (wr_ptr)
wr_capture_ptr = wr_ptr;
end
endgenerate
// dualport ram
// Memory (RAM) that holds the contents of the FIFO
assign wr_addr = wr_ptr[ASIZE-1:0];
assign rd_data = mem[rd_addr];
always @(posedge wr_clk)
begin
if (wr_en && !full)
mem[wr_addr] <= #TCQ wr_data;
end
// Read Side Logic
assign rd_addr = rd_ptr_cp[ASIZE-1:0];
assign rd_strobe = rd_en && !empty;
integer n;
// change the binary pointer to gray pointer
always @(posedge rd_clk)
begin
if (rst)
begin
rd_ptr <= #TCQ 'b0;
rd_ptr_cp <= #TCQ 'b0;
end
else begin
if (rd_strobe) begin
rd_ptr <= #TCQ rd_ptr + 1'b1;
rd_ptr_cp <= #TCQ rd_ptr_cp + 1'b1;
end
// change the binary pointer to gray pointer
end
end
//generate empty signal
assign buf_filled = wr_capture_ptr - rd_ptr;
always @ (posedge rd_clk )
begin
if (rst)
empty <= #TCQ 1'b1;
else if ((buf_filled == 0) || (buf_filled == 1 && rd_strobe))
empty <= #TCQ 1'b1;
else
empty <= #TCQ 1'b0;
end
// write side logic;
reg [ASIZE:0] wbin;
wire [ASIZE:0] wgraynext, wbinnext;
always @(posedge rd_clk)
begin
if (rst)
begin
wr_ptr <= #TCQ 'b0;
end
else begin
if (wr_en)
wr_ptr <= #TCQ wr_ptr + 1'b1;
// change the binary pointer to gray pointer
end
end
// change the write pointer to gray pointer
// calculate how many buf still available
assign buf_avail = (rd_capture_ptr + 5'd16) - wr_ptr;
always @ (posedge wr_clk )
begin
if (rst)
full <= #TCQ 1'b0;
else if ((buf_avail == 0) || (buf_avail == 1 && wr_en))
full <= #TCQ 1'b1;
else
full <= #TCQ 1'b0;
end
always @ (posedge wr_clk )
begin
if (rst)
almost_full <= #TCQ 1'b0;
else if ((buf_avail == FIFO_DEPTH - 2 ) || ((buf_avail == FIFO_DEPTH -3) && wr_en))
almost_full <= #TCQ 1'b1;
else
almost_full <= #TCQ 1'b0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long powmod(long long a, long long b, long long MOD) { long long res = 1; a %= MOD; for (; b; b >>= 1) { if (b & 1) res = res * a % MOD; a = a * a % MOD; } return res; } const int N = 1e5 + 5; double pos[N]; double getExpe(int l, int r, int p) { int ans = ((r / p) - ((l - 1) / p)); return double(ans) / (r - l + 1); } double calculate(int x, int n, int p) { int l = (x == 1 ? n : x - 1); int r = (x == n ? 1 : x + 1); return pos[x] * (2.0 - pos[l] / 2 - pos[r] / 2); } int main() { int l, r, n, p; double ans = 0.0; scanf( %d%d , &n, &p); for (int i = 1; i <= n; i++) { scanf( %d%d , &l, &r); pos[i] = getExpe(l, r, p); } for (int i = 1; i <= n; i++) { ans += calculate(i, n, p); } printf( %.9f n , ans * 1000.0 * 2); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:52:12 01/24/2016
// Design Name:
// Module Name: latch_IF_ID
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module latch_IF_ID
#(
parameter B=32 //32 bits instruccion, 7 bits pc_next (direccion)
)
(
input wire clk,
input wire reset,
input wire ena,
input wire disa,
input wire flush,
input wire [B-1:0]pc_incrementado_in,
input wire [B-1:0]instruction_in,
output reg [B-1:0]pc_incrementado_out,
output reg [B-1:0]instruction_out
);
reg [B-1:0] instr_reg;
reg [B-1:0] pc_next_reg;
always @(posedge clk)
begin
if (reset)
begin
pc_incrementado_out <= 0;
instruction_out <=0;
end
else
if(ena)
begin
if(disa)
begin
pc_next_reg <= pc_next_reg;
instr_reg <= instr_reg;
end
else if (flush)
begin
pc_incrementado_out <= pc_incrementado_out;
instruction_out <= 0;
end
else
begin
instruction_out <= instruction_in;
pc_incrementado_out <= pc_incrementado_in;
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2111OI_BEHAVIORAL_V
`define SKY130_FD_SC_LP__A2111OI_BEHAVIORAL_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__a2111oi (
Y ,
A1,
A2,
B1,
C1,
D1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, B1, C1, D1, and0_out);
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2111OI_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; const int MAXN = 1086; const int MAXT = 1586; const long long R = 1000000; struct query { long long ts, tl; long double ss, sl, p; query() {} query(long double _ss, long double _sl, long long _ts, long long _tl, long double _p) : ss(_ss), sl(_sl), ts(_ts), tl(_tl), p(_p) {} void init() { cin >> ss >> sl >> ts >> tl >> p; ss *= R, sl *= R; } } Q[MAXN]; pair<long double, long double> dp[MAXN][MAXT]; inline bool cmp(const query &a, const query &b) { return a.tl * (1 - b.p) * a.p < b.tl * (1 - a.p) * b.p; } void update(pair<long double, long double> &a, pair<long double, long double> b) { if (b.first > a.first || a.first == b.first && a.second > b.second) a = b; } int main() { int i, j; int m, n; scanf( %d%d , &n, &m); for (i = 0; i < n; ++i) Q[i].init(); sort(Q, Q + n, cmp); for (i = 0; i < n; ++i) for (j = 0; j <= m; ++j) dp[i][j].first = dp[i][j].second = -1; dp[0][0].first = dp[0][0].second = 0; for (i = 0; i < n; ++i) { long long ts = Q[i].ts, tl = Q[i].tl; long double ss = Q[i].ss, sl = Q[i].sl, p = Q[i].p; for (j = 0; j <= m; ++j) if (dp[i][j].first != -1) { long double cs = dp[i][j].first, cp = dp[i][j].second; update(dp[i + 1][j], dp[i][j]); if (j + ts <= m) update(dp[i + 1][j + ts], pair<long double, long double>(cs + ss, cp + ts)); if (j + ts + tl <= m) update(dp[i + 1][j + ts + tl], pair<long double, long double>( cs + ss + (1 - p) * sl, ts + (j + tl) * (1 - p) + p * cp)); } } pair<long double, long double> res(0, 0); for (i = 0; i <= m; ++i) update(res, dp[n][i]); cout << setprecision(20) << res.first / R << << res.second << endl; return 0; } |
/*
* Copyright (c) 2015, Arch Laboratory
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/* ----- Do not change ----- */
`define DRAM_CMD_WRITE 3'b000
`define DRAM_CMD_READ 3'b001
`define DDR2_DATA 15:0
`define DDR2_ADDR 12:0
`define DDR2_CMD 2:0
// `define APPADDR_WIDTH 29
`define APPADDR_WIDTH 27
`define APPDATA_WIDTH 128
`define APPMASK_WIDTH (`APPDATA_WIDTH / 8)
module DRAMCON(input wire CLK200M,
input wire RST_IN,
output wire CLK_OUT,
output wire RST_OUT,
// User logic interface ports
input wire [`APPADDR_WIDTH-1:0] D_ADDR,
input wire [`APPDATA_WIDTH-1:0] D_DIN,
input wire D_WE,
input wire D_RE,
output reg [`APPDATA_WIDTH-1:0] D_DOUT,
output reg D_DOUTEN,
output wire D_BUSY,
// Memory interface ports
inout wire [`DDR2_DATA] DDR2DQ,
inout wire [1:0] DDR2DQS_N,
inout wire [1:0] DDR2DQS_P,
output wire [`DDR2_ADDR] DDR2ADDR,
output wire [2:0] DDR2BA,
output wire DDR2RAS_N,
output wire DDR2CAS_N,
output wire DDR2WE_N,
output wire [0:0] DDR2CK_P,
output wire [0:0] DDR2CK_N,
output wire [0:0] DDR2CKE,
output wire [0:0] DDR2CS_N,
output wire [1:0] DDR2DM,
output wire [0:0] DDR2ODT);
// inputs of u_dram
reg [`APPADDR_WIDTH-1:0] app_addr;
reg [`DDR2_CMD] app_cmd;
reg app_en;
reg [`APPDATA_WIDTH-1:0] app_wdf_data;
reg app_wdf_end;
reg [`APPMASK_WIDTH-1:0] app_wdf_mask;
reg app_wdf_wren;
wire app_sr_req = 0; // no used
wire app_ref_req = 0; // no used
wire app_zq_req = 0; // no used
// outputs of u_dram
wire [`APPDATA_WIDTH-1:0] app_rd_data;
wire app_rd_data_end;
wire app_rd_data_valid;
wire app_rdy;
wire app_wdf_rdy;
wire app_sr_active; // no used
wire app_ref_ack; // no used
wire app_zq_ack; // no used
wire ui_clk;
wire ui_clk_sync_rst;
wire init_calib_complete;
mig
u_mig (
// Memory interface ports
.ddr2_dq (DDR2DQ),
.ddr2_dqs_n (DDR2DQS_N),
.ddr2_dqs_p (DDR2DQS_P),
.ddr2_addr (DDR2ADDR),
.ddr2_ba (DDR2BA),
.ddr2_ras_n (DDR2RAS_N),
.ddr2_cas_n (DDR2CAS_N),
.ddr2_we_n (DDR2WE_N),
.ddr2_ck_p (DDR2CK_P),
.ddr2_ck_n (DDR2CK_N),
.ddr2_cke (DDR2CKE),
.ddr2_cs_n (DDR2CS_N),
.ddr2_dm (DDR2DM),
.ddr2_odt (DDR2ODT),
// Clock input ports
.sys_clk_i (CLK200M),
// Application interface ports
.app_addr (app_addr),
.app_cmd (app_cmd),
.app_en (app_en),
.app_wdf_data (app_wdf_data),
.app_wdf_end (app_wdf_end),
.app_wdf_mask (app_wdf_mask),
.app_wdf_wren (app_wdf_wren),
.app_rd_data (app_rd_data),
.app_rd_data_end (app_rd_data_end),
.app_rd_data_valid (app_rd_data_valid),
.app_rdy (app_rdy),
.app_wdf_rdy (app_wdf_rdy),
.app_sr_req (app_sr_req),
.app_sr_active (app_sr_active),
.app_ref_req (app_ref_req),
.app_ref_ack (app_ref_ack),
.app_zq_req (app_zq_req),
.app_zq_ack (app_zq_ack),
.ui_clk (ui_clk),
.ui_clk_sync_rst (ui_clk_sync_rst),
.init_calib_complete (init_calib_complete),
.sys_rst (RST_IN)
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
assign D_BUSY = (mode != WAIT_REQ);
assign CLK_OUT = ui_clk;
assign RST_OUT = (ui_clk_sync_rst || ~init_calib_complete); // High Active
///// READ & WRITE PORT CONTROL (begin) //////////////////////////////////////
localparam INIT = 0; // INIT must be 0
localparam WAIT_REQ = 1;
localparam WRITE = 2;
localparam READ = 3;
reg [1:0] mode;
reg [1:0] state;
reg [3:0] cnt;
reg [`APPDATA_WIDTH-1:0] app_wdf_data_buf;
reg write_finish;
reg error_reg;
always @(posedge ui_clk) begin
if (ui_clk_sync_rst) begin
mode <= INIT;
state <= 0;
app_addr <= 0;
app_cmd <= 0;
app_en <= 0;
app_wdf_data <= 0;
app_wdf_wren <= 0;
app_wdf_mask <= 0;
app_wdf_end <= 0;
cnt <= 0;
D_DOUT <= 0;
D_DOUTEN <= 0;
write_finish <= 0;
error_reg <= 0;
end else begin
case (mode)
INIT: begin // initialize
if (init_calib_complete) mode <= WAIT_REQ;
end
WAIT_REQ: begin // wait request
app_addr <= D_ADDR;
app_en <= 0;
app_wdf_data_buf <= D_DIN;
app_wdf_mask <= {`APPMASK_WIDTH{1'b0}};
if (D_WE) mode <= WRITE;
else if (D_RE) mode <= READ;
end
WRITE: begin
case (state)
0: begin
app_cmd <= `DRAM_CMD_WRITE;
app_en <= 1;
state <= 1;
cnt <= 0;
end
1: begin
if (app_rdy) begin
app_en <= 0;
end
if (app_wdf_rdy) begin
cnt <= cnt + 1;
if (cnt == 1) begin
app_wdf_wren <= 0;
app_wdf_end <= 0;
write_finish <= 1;
end else if (cnt == 0) begin
app_wdf_data <= app_wdf_data_buf;
app_wdf_wren <= 1;
app_wdf_end <= 1;
end
end
if (!app_en && write_finish) begin
mode <= WAIT_REQ;
state <= 0;
cnt <= 0;
write_finish <= 0;
end
end
endcase
end
READ: begin
case (state)
0: begin
app_cmd <= `DRAM_CMD_READ;
app_en <= 1;
state <= 1;
cnt <= 0;
end
1: begin
if (app_rdy) app_en <= 0;
if (app_rd_data_valid) begin
if (app_rd_data_end) cnt <= 1;
D_DOUT <= app_rd_data;
end
if (!app_en && cnt) begin
state <= 2;
D_DOUTEN <= 1;
end
end
2: begin
D_DOUTEN <= 0;
mode <= WAIT_REQ;
state <= 0;
cnt <= 0;
end
endcase
end
endcase
end
end
///// READ & WRITE PORT CONTROL (end) //////////////////////////////////////
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; const int inf = (1 << 30) - 1; const long long linf = (1ll << 62) - 1; const int N = 1e6 + 100; int n, m; int u[N], v[N]; set<int> g[N]; bool used[N]; int ts[N], tsLen = 0; void topSort(int v) { if (used[v]) { return; } used[v] = true; for (int to : g[v]) { topSort(to); } ts[tsLen++] = v; } inline bool check(int m) { for (int i = 0; i < n; i++) { g[i].clear(); } for (int i = 0; i < m; i++) { g[u[i]].insert(v[i]); } fill_n(used, n, false); tsLen = 0; for (int i = 0; i < n; i++) { if (!used[i]) { topSort(i); } } reverse(ts, ts + tsLen); for (int i = 0; i < tsLen - 1; i++) { if (g[ts[i]].count(ts[i + 1]) == 0) { return false; } } return true; } int main() { cin >> n >> m; for (int i = 0; i < m; i++) { scanf( %d%d , &u[i], &v[i]); u[i]--, v[i]--; } int l = 0, r = m; while (r - l > 1) { int x = (l + r) / 2; if (check(x)) { r = x; } else { l = x; } } if (!check(r)) { puts( -1 ); } else { printf( %d n , r); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int max_n = 100111, inf = 1000111222; const int max_lev = 18; int n, m, q, parent[max_lev][max_n], best_h[max_n], used[max_n], h[max_n]; int real_p[max_lev][max_n]; int tin[max_n], tout[max_n], cur; vector<int> g[max_n]; void dfs(int v, int p) { tin[v] = ++cur; parent[0][v] = p; real_p[0][v] = p; for (int to : g[v]) { if (to == p) { continue; } if (tin[to]) { if (tin[to] < tin[parent[0][v]]) { parent[0][v] = to; } } else { dfs(to, v); if (tin[parent[0][to]] < tin[parent[0][v]]) { parent[0][v] = parent[0][to]; } } } tout[v] = cur; } void get_all_p(int parent[max_lev][max_n]) { for (int lev = 1; lev < max_lev; ++lev) { for (int i = 0; i < n; ++i) { parent[lev][i] = parent[lev - 1][parent[lev - 1][i]]; } } } bool is_ancestor(int v1, int v2) { return tin[v1] <= tin[v2] && tout[v1] >= tout[v2]; } int lca(int v1, int v2) { if (is_ancestor(v1, v2)) { return v1; } for (int i = max_lev - 1; i >= 0; --i) { if (!is_ancestor(real_p[i][v1], v2)) { v1 = real_p[i][v1]; } } return real_p[0][v1]; } int get_d(int v, int up) { if (v == up) { return 0; } int res = 1; for (int i = max_lev - 1; i >= 0; --i) { if (!is_ancestor(parent[i][v], up)) { res += 1 << i; v = parent[i][v]; } } return res; } int main() { scanf( %d%d%d , &n, &m, &q); while (m--) { int u, v; scanf( %d%d , &u, &v); --u; --v; g[u].push_back(v); g[v].push_back(u); } dfs(0, 0); get_all_p(parent); get_all_p(real_p); while (q--) { int u, v; scanf( %d%d , &u, &v); --u; --v; int lc = lca(u, v); int ans = get_d(u, lc) + get_d(v, lc); printf( %d n , ans); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 300010; pair<pair<int, int>, pair<int, int> > allNums[MAXN * 2]; set<pair<int, int> > startTimes; pair<int, int> v[MAXN]; int main() { int N; scanf( %d , &N); for (int i = 0; i < N; ++i) { scanf( %d%d , &v[i].first, &v[i].second); int L = v[i].second - v[i].first; allNums[2 * i] = make_pair(make_pair(v[i].first, 0), make_pair(L, i)); allNums[2 * i + 1] = make_pair(make_pair(v[i].second, 1), make_pair(L, i)); } sort(allNums, allNums + 2 * N); for (int i = 0; i < 2 * N; ++i) { if (allNums[i].first.second == 0) { startTimes.insert( make_pair(allNums[i].first.first, allNums[i].second.second)); continue; } int idx = allNums[i].second.second; int st = v[idx].first; set<pair<int, int> >::iterator it = startTimes.find(make_pair(st, idx)); set<pair<int, int> >::iterator snd = startTimes.begin(); if (it == snd) ++snd; if (snd != startTimes.end() && snd->first <= it->first) { printf( %d %d n , idx + 1, snd->second + 1); return 0; } startTimes.erase(it); } puts( -1 -1 ); return 0; } |
`timescale 1ns/10ps
module spw_light_pll_0(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(1),
.output_clock_frequency0("200.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("0 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long n; cin >> n; int v = 3 - n % 3, ans = 0; for (int i = v;; i += 3) { if (1LL * i * (i + 1) / 2 > (n + i) / 3) break; ++ans; } cout << ans; return 0; } |
`timescale 1ns / 1ps
///////////////// ** ctrl_reg_readback ** //////////////////////////////////////////
//
// This module contains the control registers for the font5 9 channel daq firmware
// Clocked at 40MHz
//
// It consists of 7-bit registers, 5-bit addresses
// Data, data strobe and address to be written are all to be provided 'asynchronously'
// and brought onto this clock domain (40 MHz, note signals also provided @40 MHz
module ctrl_reg_readback #(parameter CR_WIDTH=6, N_CTRL_REGS=64) (
input clk,
input rst,
input tx_en,
input tx_data_loaded,
output reg tx_data_ready,
output reg tx_complete,
output reg [CR_WIDTH-1:0] tx_cnt
);
// Readback logic. This works as the DAQ RAM readback. Each ctrl reg is
// stepped trhough in turn, with its data presented until transmitted by the uart
always @(posedge clk) begin
if (rst) begin
tx_cnt <= 0;
tx_data_ready <= 0;
tx_complete <= 0;
end else begin
//tx_data_loaded is asserted by the UART once it has loaded the current
//data word. Since the UART operates on the baud clock domain, synchronise
if (!tx_complete && tx_en) begin //Transmission of RAM contents enabled
if (tx_data_ready && tx_data_loaded) begin //Data word has been loaded to the uart. tx_data_loaded will stay high until the UART transmission has finished
tx_data_ready <= 0;
if (tx_cnt == N_CTRL_REGS-1) begin //We have transmitted the data from the last address
tx_complete <= 1;
tx_cnt <= tx_cnt;
end
else begin
tx_complete <= tx_complete;
tx_cnt <= tx_cnt + 1;
end
end
else begin
tx_complete <= tx_complete;
tx_cnt <= tx_cnt;
tx_data_ready <= (!tx_data_ready && !tx_data_loaded) ? 1 : tx_data_ready; //Load the data from RAM address currently specified by tx_cnt
end
end else if (tx_complete && !tx_en) begin //Transmission is complete. Wait for enable to go low, then reset tx logic
tx_cnt <= 0;
tx_data_ready <= 0;
tx_complete <= 0;
end else begin
tx_data_ready <= tx_data_ready;
tx_complete <= tx_complete;
tx_cnt <= tx_cnt;
end
end // if (~rst)
end //always
endmodule
|
#include <bits/stdc++.h> using namespace std; bool is_right(complex<long long> p1, complex<long long> p2, complex<long long> p3) { return (conj(p2 - p1) * (p3 - p1)).imag() < 0; } const int N = 1e5 + 5; vector<complex<long long> > U; complex<long long> a[N]; int n; void read_input() { cin >> n; for (int i = 0; i < n; i++) { int x, y; cin >> x >> y; a[i] = complex<long long>(x, y - 1LL * x * x); } } void solve() { sort(a, a + n, [](complex<long long> a, complex<long long> b) { return make_pair(a.real(), a.imag()) < make_pair(b.real(), b.imag()); }); for (int i = 0; i < n; U.push_back(a[i++])) while (U.size() > 1 && !is_right(U[U.size() - 2], U.back(), a[i])) U.pop_back(); cout << U.size() - (U.size() > 1 && U[0].real() == U[1].real()) - 1; } int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); read_input(), solve(); return 0; } |
module artemis_clkgen (
(* KEEP = "TRUE" *) input clk,
input rst,
output locked,
(* KEEP = "TRUE" *) output ddr3_clk
);
//Local Parameters
//Registers/Wires
wire clk_100mhz_buf;
wire clk_fbout;
wire clk_fbout_buf;
wire clk_100mhz_out;
//wire ddr3_clk_pre;
//wire ddr3_clk_int;
//Submodules
BUFG clkfb_buf (
.I (clk_fbout ),
.O (clk_fbout_buf )
);
/*
BUFG ddr3_clk_obuf (
.I (ddr3_clk_pre ),
.O (ddr3_clk_int )
);
ODDR2 #(
.DDR_ALIGNMENT ("NONE"), //Sets output alignment to NON
.INIT (1'b0), //Sets the inital state to 0
.SRTYPE ("SYNC") //Specified "SYNC" or "ASYNC" reset
) pad_buf (
.Q (ddr3_clk),
.C0 (ddr3_clk_int),
.C1 (~ddr3_clk_int),
.CE (1'b1),
.D0 (1'b1),
.D1 (1'b0),
.R (1'b0),
.S (1'b0)
);
*/
PLL_BASE #(
.BANDWIDTH ("OPTIMIZED" ),
.CLK_FEEDBACK ("CLKFBOUT" ),
.COMPENSATION ("SYSTEM_SYNCHRONOUS" ),
.DIVCLK_DIVIDE (1 ),
.CLKFBOUT_MULT (10 ),
.CLKFBOUT_PHASE (0.00 ),
.CLKOUT0_DIVIDE (3 ),
.CLKOUT0_PHASE (0.00 ),
.CLKOUT0_DUTY_CYCLE (0.50 ),
.CLKIN_PERIOD (10.0 ),
.REF_JITTER (0.010 )
) artemis_clkgen_pll(
.CLKFBOUT (clk_fbout ),
.CLKOUT0 (ddr3_clk ),
// .CLKOUT0 (ddr3_clk_pre ),
.CLKOUT1 ( ),
.CLKOUT2 ( ),
.CLKOUT3 ( ),
.CLKOUT4 ( ),
.CLKOUT5 ( ),
.LOCKED (locked ),
.RST (rst ),
.CLKFBIN (clk_fbout_buf ),
.CLKIN (clk )
);
//Assynchronous Logic
//Synchronous Logic
endmodule
|
#include<cstdio> #include<iostream> #include<algorithm> int main() { int n; char a[100000]; bool x = 1; while (~scanf( %d , &n)) { while (n--) { x = 1; scanf( %s , a); for (int i = 0; a[i] != 0 ; i++) { if (x) { if (a[i] != a ) a[i] = a ; else a[i] = b ; x = 0; } else { if (a[i] != z ) a[i] = z ; else a[i] = z - 1; x = 1; } } printf( %s n , a); } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[n]; for (int i = 0; i < n; i++) cin >> a[i]; int b[n]; b[0] = 0; for (int i = 1; i < n; i++) b[i] = abs(a[i] - a[i - 1]); long long int dp[n], dd[n]; dp[0] = 0; dd[0] = 0; for (int i = 1; i < n; i++) { if (i % 2 == 1) { dp[i] = dp[i - 1] + b[i]; dd[i] = max(dd[i - 1] - b[i], 0LL); } else { dp[i] = max(0LL, dp[i - 1] - b[i]); dd[i] = dd[i - 1] + b[i]; } } long long int ans = 0; for (int i = 0; i < n; i++) ans = max(ans, dp[i]); for (int i = 0; i < n; i++) ans = max(ans, dd[i]); cout << ans << endl; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYMETAL6S2S_SYMBOL_V
`define SKY130_FD_SC_MS__DLYMETAL6S2S_SYMBOL_V
/**
* dlymetal6s2s: 6-inverter delay with output from 2nd stage on
* horizontal route.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlymetal6s2s (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYMETAL6S2S_SYMBOL_V
|
`timescale 1ns/1ps
//-----------------------------------------------------------------------------
// Title : ALU
// Project : KPU
//-----------------------------------------------------------------------------
// File : alu.v
// Author : acorallo <>
// Created : 17.12.2016
//-----------------------------------------------------------------------------
// Description :
// Arithmetic logic implementation for KPU
//-----------------------------------------------------------------------------
// This file is part of KPU.
// KPU is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
// KPU is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY;
// without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with KPU. If not, see <http://www.gnu.org/licenses/>.
//
// Copyright (c) 2016 2017 by Andrea Corallo.
//------------------------------------------------------------------------------
// Modification history :
// 17.12.2016 : created
//-----------------------------------------------------------------------------
`ifndef _alu
`define _alu
`include "kpu_conf.v"
`include "uart_defines.v"
module alu(input wire [3:0] alu_op_i,
input wire [`N-1:0] a_i,
input wire [`N-1:0] b_i,
output reg [`N-1:0] out_o,
output reg [3:0] flags_o);
wire [`N-1:0] add_r;
wire [`N-1:0] sub_r;
wire oflow_add;
wire oflow_sub;
wire signed [`N-1:0] a_signed;
wire signed [`N-1:0] b_signed;
assign a_signed = a_i;
assign b_signed = b_i;
assign add_r = a_i + b_i;
assign sub_r = a_i - b_i;
assign oflow_add = (a_i[`N-1] == b_i[`N-1] && add_r[`N-1] != a_i[`N-1]) ?
1 : 0;
assign oflow_sub = (a_i[`N-1] == b_i[`N-1] && sub_r[`N-1] != a_i[`N-1]) ?
1 : 0;
always @(*) begin
if (alu_op_i != 4'hE) begin
flags_o[1] = a_i > b_i;
flags_o[2] = a_i == b_i;
flags_o[3] = out_o > 0;
end
else begin
flags_o[1] = a_signed > b_signed;
flags_o[2] = a_signed == b_signed;
flags_o[3] = out_o > 0;
end
case (alu_op_i)
4'h0: flags_o[0] = oflow_add; // add
4'h1: flags_o[0] = oflow_sub; // sub
default: flags_o[0] = 1'b0;
endcase
case (alu_op_i)
4'h0: out_o = add_r; // add
4'h1: out_o = sub_r; // sub
4'h2: out_o = a_i >> b_i; // shr
4'h3: out_o = a_i << b_i; // shl
4'h4: out_o = ~a_i; // not
4'h5: out_o = a_i & b_i; // and
4'h6: out_o = a_i | b_i; // or
4'h7: out_o = a_i ^ b_i; // xor
4'h8: out_o = a_i * b_i; // mult
4'h9: out_o = a_i / b_i; // div
4'hA: out_o = a_i % b_i; // mod
4'hF: out_o = a_i; // cmp
default: out_o = `N'h0; // latch prevention
endcase
end
endmodule // alu
`endif
|
#include <bits/stdc++.h> #pragma comment(linker, /stack:20000000 ) using namespace std; template <typename T1, typename T2, typename T3> struct triple { T1 a; T2 b; T3 c; triple(){}; triple(T1 _a, T2 _b, T3 _c) : a(_a), b(_b), c(_c) {} }; template <typename T1, typename T2, typename T3> bool operator<(const triple<T1, T2, T3> &t1, const triple<T1, T2, T3> &t2) { if (t1.a != t2.a) return t1.a < t2.a; else return t1.b < t2.b; } template <typename T1, typename T2> inline std::ostream &operator<<(std::ostream &os, const std::pair<T1, T2> &p) { return os << ( << p.first << , << p.second << ) ; } template <typename T> inline std::ostream &operator<<(std::ostream &os, const std::vector<T> &v) { bool first = true; os << [ ; for (unsigned int i = 0; i < v.size(); i++) { if (!first) os << , ; os << v[i]; first = false; } return os << ] ; } template <typename T> inline std::ostream &operator<<(std::ostream &os, const std::set<T> &v) { bool first = true; os << [ ; for (typename std::set<T>::const_iterator ii = v.begin(); ii != v.end(); ++ii) { if (!first) os << , ; os << *ii; first = false; } return os << ] ; } template <typename T1, typename T2> inline std::ostream &operator<<(std::ostream &os, const std::map<T1, T2> &v) { bool first = true; os << [ ; for (typename std::map<T1, T2>::const_iterator ii = v.begin(); ii != v.end(); ++ii) { if (!first) os << , ; os << *ii; first = false; } return os << ] ; } template <typename T, typename T2> void printarray(T a[], T2 sz, T2 beg = 0) { for (T2 i = beg; i < sz; i++) cout << a[i] << ; } inline long long binpow(long long x, long long n) { long long res = 1; while (n) { if (n & 1) res *= x; x *= x; n >>= 1; } return res; } inline long long powmod(long long x, long long n, long long _mod) { long long res = 1; while (n) { if (n & 1) res = (res * x) % _mod; x = (x * x) % _mod; n >>= 1; } return res; } inline long long mulmod(long long x, long long n, long long _mod) { long long res = 0; while (n) { if (n & 1) res = (res + x) % _mod; x = (x + x) % _mod; n >>= 1; } return res; } inline long long gcd(long long a, long long b) { long long t; while (b) { a = a % b; t = a; a = b; b = t; } return a; } inline int gcd(int a, int b) { int t; while (b) { a = a % b; t = a; a = b; b = t; } return a; } inline long long lcm(int a, int b) { return a / gcd(a, b) * (long long)b; } inline long long lcm(long long a, long long b) { return a / gcd(a, b) * b; } inline long long gcd(long long a, long long b, long long c) { return gcd(gcd(a, b), c); } inline int gcd(int a, int b, int c) { return gcd(gcd(a, b), c); } inline long long lcm(long long a, long long b, long long c) { return lcm(lcm(a, b), c); } inline long long lcm(int a, int b, int c) { return lcm(lcm(a, b), (long long)c); } inline long long max(long long a, long long b) { return (a > b) ? a : b; } inline int max(int a, int b) { return (a > b) ? a : b; } inline double max(double a, double b) { return (a > b) ? a : b; } inline long long max(long long a, long long b, long long c) { return max(a, max(b, c)); } inline int max(int a, int b, int c) { return max(a, max(b, c)); } inline double max(double a, double b, double c) { return max(a, max(b, c)); } inline long long min(long long a, long long b) { return (a < b) ? a : b; } inline int min(int a, int b) { return (a < b) ? a : b; } inline double min(double a, double b) { return (a < b) ? a : b; } inline long long min(long long a, long long b, long long c) { return min(a, min(b, c)); } inline int min(int a, int b, int c) { return min(a, min(b, c)); } inline double min(double a, double b, double c) { return min(a, min(b, c)); } inline void getar(int *a, int n) { for (int ii = 0; ii < n; ii++) { scanf( %d , a + ii); } } inline void getar(long long *a, int n) { for (int ii = 0; ii < n; ii++) { scanf( %I64 , a + ii); } } bool a[1621][1621]; bool used[1621][1621]; bool used2[1621][1621]; bool used3[1621][1621]; const int maxl = 15; const int maxs = 10; int w, h; int k = 0; int cur = 0; int basei, basej; triple<int, int, int> q[10000]; int qs = 0; void go2(int i, int j) { if (((abs(i - basei) + abs(j - basej)) >= maxl) || (!a[i][j]) || used2[i][j]) return; used2[i][j] = true; qs = 0; q[qs].a = i; q[qs].b = j; q[qs++].c = 0; int qc = 0; while (qc < qs) { int curi = q[qc].a; int curj = q[qc].b; int curl = q[qc++].c; if (curl == maxl) break; for (int t = -1; t <= 1; t++) for (int w = -1; w <= 1; w++) { if (!used2[curi + t][curj + w] && a[curi + t][curj + w]) { used2[curi + t][curj + w] = true; q[qs].a = curi + t; q[qs].b = curj + w; q[qs++].c = curl + 1; } } } } vector<pair<int, int>> v3; bool check(int i, int j) { int s = 0; qs = 0; q[qs].a = i; q[qs].b = j; q[qs++].c = 0; used3[i][j] = true; int qc = 0; v3.clear(); while (qc < qs) { int curi = q[qc].a; int curj = q[qc].b; int curl = q[qc++].c; if (max(abs(basei - curi), abs(basej - curj)) > 2) continue; if (a[curi][curj]) s++; for (int t = -1; t <= 1; t++) for (int w = -1; w <= 1; w++) { if (!used3[curi + t][curj + w]) { used3[curi + t][curj + w] = true; v3.push_back(make_pair(curi + t, curj + w)); q[qs].a = curi + t; q[qs].b = curj + w; q[qs++].c = curl + 1; } } } for (int i = 0; i < v3.size(); i++) { used3[v3[i].first][v3[i].second] = false; } return (s < maxs); } void go(int i, int j) { if ((!a[i][j]) || used[i][j]) return; used[i][j] = true; go(i - 1, j); go(i + 1, j); go(i, j - 1); go(i, j + 1); if (used2[i][j]) return; int t = 0; if (a[i - 1][j] == 0) t++; if (a[i][j - 1] == 0) t++; if (a[i + 1][j] == 0) t++; if (a[i][j + 1] == 0) t++; if (t >= 2) { basei = i; basej = j; if (check(i, j)) { cur++; go2(i, j); } } } vector<int> ans; int main() { scanf( %d , &w); scanf( %d , &h); int x; for (int i = 5; i < w + 5; i++) { for (int j = 5; j < h + 5; j++) { scanf( %d , &x); a[i][j] = x; used[i][j] = used2[i][j] = false; } } for (int i = 5; i < w + 5; i++) { for (int j = 5; j < h + 5; j++) { if ((!used[i][j]) && a[i][j]) { k++; cur = 0; go(i, j); ans.push_back(cur); } } } cout << k << endl; sort(ans.begin(), ans.end()); for (int i = 0; i < k; i++) { cout << ans[i] << ; } cout << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; signed main() { long long int n, k; cin >> n >> k; long long int arr1[n], arr2[n]; for (long long int i = 0; i < n; i++) cin >> arr1[i]; for (long long int i = 0; i < n; i++) cin >> arr2[i]; multiset<pair<long long int, pair<long long int, long long int> > > s; for (long long int i = 0; i < n; i++) { s.insert(make_pair(arr2[i] / arr1[i], make_pair(arr1[i], arr2[i]))); } multiset<pair<long long int, pair<long long int, long long int> > >::iterator it1; while (true) { pair<long long int, pair<long long int, long long int> > pp = *s.begin(); long long int num = pp.first, a = pp.second.first, b = pp.second.second; long long int req = a - (b % a); if (k >= req) { k -= req; s.erase(s.begin()); s.insert(make_pair(num + 1, make_pair(a, b + req))); } else { break; } } it1 = s.begin(); cout << it1->first; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A22OI_SYMBOL_V
`define SKY130_FD_SC_LS__A22OI_SYMBOL_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a22oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A22OI_SYMBOL_V
|
`timescale 1ns / 1ns
module fake_mii
(input mdc,
inout mdio);
reg [15:0] regs[0:31];
reg [15:0] save;
reg mdo;
reg mdo_en;
reg mdio_del;
reg di;
reg [1:0] op;
reg [4:0] phyad;
reg [4:0] regad;
integer count;
always @(mdio) #10 mdio_del <= mdio;
assign mdio = mdo_en ? mdo : 1'bz;
integer i, j;
initial begin
mdo = 0;
mdo_en = 0;
for (i=0; i<32; i=i+1) begin
j = i+1;
regs[i] = {j[7:0], i[7:0]};
end
#20
while (1) handle_op;
end
task handle_op;
begin
wait_for_clk; sample_mdio;
while (di !== 1) begin wait_for_clk; sample_mdio; end // wait for preamble
while (di !== 0) begin wait_for_clk; sample_mdio; end // gobble up preamble
wait_for_clk; sample_mdio; // eat 0
if (di !== 1) $display ($time, " ERROR! Bad MII start frame");
wait_for_clk; sample_mdio; // eat 1
op[1] = di; wait_for_clk; sample_mdio;
op[0] = di; wait_for_clk; sample_mdio;
phyad[4] = di; wait_for_clk; sample_mdio;
phyad[3] = di; wait_for_clk; sample_mdio;
phyad[2] = di; wait_for_clk; sample_mdio;
phyad[1] = di; wait_for_clk; sample_mdio;
phyad[0] = di; wait_for_clk; sample_mdio;
regad[4] = di; wait_for_clk; sample_mdio;
regad[3] = di; wait_for_clk; sample_mdio;
regad[2] = di; wait_for_clk; sample_mdio;
regad[1] = di; wait_for_clk; sample_mdio;
regad[0] = di; wait_for_clk; sample_mdio;
if (op == 2'b10) begin
$display ($time, " MII: reading register %x from phy %x (%x).", regad, phyad, regs[regad]);
if (di !== 1'bz) $display ($time, " ERROR! Bad MII turn around");
wait_for_nclk;
mdo_en = 1'b1;
mdo = 1'b0;
count = 15;
while (count >= 0) begin
wait_for_nclk;
mdo = regs[regad][count];
count = count - 1;
end
wait_for_nclk;
mdo = 0;
mdo_en = 0;
wait_for_clk;
$display ($time, " MII: done reading.");
end
else if (op == 2'b01) begin
$display ($time, " MII: writing register %x to phy %x.", regad, phyad);
if (di !== 1'b1) $display ($time, " ERROR! Bad MII turn around");
wait_for_clk; sample_mdio;
if (di !== 1'b0) $display ($time, " ERROR! Bad MII turn around");
count = 15;
while (count >= 0) begin
wait_for_clk;
save[count] = mdio;
count = count - 1;
end
regs[regad] = save;
wait_for_clk;
$display ($time, " MII: done writing %x to register %x.", regs[regad], regad);
end
else
$display ($time, " ERROR! Invalid MII op %b.", op);
end
endtask
task wait_for_clk;
@(posedge mdc) begin end
endtask
task wait_for_nclk;
@(negedge mdc) begin end
endtask
task sample_mdio;
begin
if (mdio != mdio_del)
$display($time, " ERROR! mdio not setup for 10 ns prior to rising edge of mdc.");
#10 if (mdio != mdio_del)
$display ($time, " ERROR! mdio not held for 10 ns after rising edge of mdc.");
di = mdio_del;
end
endtask
endmodule
// module test_fake_mii;
// initial begin
// $dumpfile("test_fake_mii.vcd");
// $dumpvars;
// end
// reg reset_n;
// initial begin
// reset_n = 0;
// #7 reset_n = 1;
// end
// wire mdc;
// fake_clk #(2) U_mdc(reset_n, mdc);
// reg mdo;
// reg mdo_en;
// wire mdio = mdo_en ? mdo : 1'bz;
// fake_mii U_fake_mii(mdc, mdio);
// reg [65:0] tosend;
// reg [65:0] tosend_en;
// initial begin
// tosend = 0;
// tosend_en = 0;
// #200;
// tosend = {{32{1'b1}}, 4'b0110, 5'h00, 5'h1c, 2'b00, 16'h0000, 1'b0};
// tosend_en = {{32{1'b1}}, 4'b1111, 5'h1f, 5'h1f, 2'b00, 16'h0000, 1'b0};
// #100000;
// $finish;
// end
// always @(negedge mdc) begin
// mdo = tosend[65];
// mdo_en = tosend_en[65];
// tosend = tosend << 1;
// tosend_en = tosend_en << 1;
// end
// endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__TAPVGND_TB_V
`define SKY130_FD_SC_LP__TAPVGND_TB_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection
* 1 row down.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__tapvgnd.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_lp__tapvgnd dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__TAPVGND_TB_V
|
#include <bits/stdc++.h> using namespace std; inline int read() { int d = 0; char c = getchar(); while (c < 0 || c > 9 ) c = getchar(); while (c >= 0 && c <= 9 ) { d = (d << 3) + (d << 1) + c - 0 ; c = getchar(); } return d; } const int N = 1e5 + 5; const long long INF = 1e14; int n, m, k; int from[N * 2], ver[N * 2], nxt[N * 2], edge[N * 2], head[N], cnt; int v[N * 2], h[N], nx[N * 2], cnt1; long long dis[N][2], ed[N * 2]; int po[N]; bool pl[N]; inline void add(int x, int y, int z) { from[++cnt] = x, ver[cnt] = y, edge[cnt] = z, nxt[cnt] = head[x], head[x] = cnt; } void spfa() { for (int i = 1; i <= n; i++) dis[i][0] = dis[i][1] = INF; queue<int> q; for (int i = 1; i <= k; i++) { q.push(po[i]); pl[po[i]] = true; dis[po[i]][0] = po[i]; dis[po[i]][1] = 0; } while (!q.empty()) { int x = q.front(); q.pop(); pl[x] = false; for (int i = head[x]; i; i = nxt[i]) { int y = ver[i]; if (dis[y][1] > dis[x][1] + edge[i]) { dis[y][1] = dis[x][1] + edge[i]; dis[y][0] = dis[x][0]; if (!pl[y]) { q.push(y); pl[y] = true; } } } } } long long prim() { long long ans = dis[1][1], nm = dis[1][0]; int tot = 1; priority_queue<pair<long long, int>, vector<pair<long long, int> >, greater<pair<long long, int> > > q; pl[nm] = true; for (int i = h[nm]; i; i = nx[i]) q.push(make_pair(ed[i], v[i])); while (tot < k) { while (pl[q.top().second]) q.pop(); int x = q.top().second; long long len = q.top().first; pl[x] = true; ans += len; tot++; for (int i = h[x]; i; i = nx[i]) q.push(make_pair(ed[i], v[i])); } return ans; } int main() { n = read(), m = read(); for (int i = 1; i <= m; i++) { int u = read(), v = read(), w = read(); add(u, v, w); add(v, u, w); } k = read(); for (int i = 1; i <= k; i++) po[i] = read(); spfa(); for (int i = 1; i <= cnt; i += 2) { int x = from[i], y = ver[i]; v[++cnt1] = dis[y][0], nx[cnt1] = h[dis[x][0]], h[dis[x][0]] = cnt1; ed[cnt1] = dis[x][1] + edge[i] + dis[y][1]; v[++cnt1] = dis[x][0], nx[cnt1] = h[dis[y][0]], h[dis[y][0]] = cnt1; ed[cnt1] = dis[y][1] + edge[i] + dis[x][1]; } cout << prim(); return 0; } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module image_filter_mul_8ns_6ns_13_3_MAC3S_0(clk, ce, a, b, p);
input clk;
input ce;
input[8 - 1 : 0] a; // synthesis attribute keep a "true"
input[6 - 1 : 0] b; // synthesis attribute keep b "true"
output[13 - 1 : 0] p;
reg [8 - 1 : 0] a_reg0;
reg [6 - 1 : 0] b_reg0;
wire [13 - 1 : 0] tmp_product;
reg [13 - 1 : 0] buff0;
assign p = buff0;
assign tmp_product = a_reg0 * b_reg0;
always @ (posedge clk) begin
if (ce) begin
a_reg0 <= a;
b_reg0 <= b;
buff0 <= tmp_product;
end
end
endmodule
`timescale 1 ns / 1 ps
module image_filter_mul_8ns_6ns_13_3(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
image_filter_mul_8ns_6ns_13_3_MAC3S_0 image_filter_mul_8ns_6ns_13_3_MAC3S_0_U(
.clk( clk ),
.ce( ce ),
.a( din0 ),
.b( din1 ),
.p( dout ));
endmodule
|
/*
* cpu_tv.v
* Testbench for cpu.v
*
* Copyright (C) 2013 James Cowgill
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
module cpu_tb;
// Inputs
reg clk;
reg [7:0] data_in;
reg data_available;
// Outputs
wire [7:0] data_out;
wire data_out_en;
wire data_read;
// This testbench just lets the CPU run, producing whatever output it wants
cpu #(.INIT_RAM(1)) uut (
.clk(clk),
.data_in(data_in),
.data_available(data_available),
.data_out(data_out),
.data_out_en(data_out_en),
.data_read(data_read)
);
initial
begin
clk = 0;
data_in = 0;
data_available = 0;
#101 data_available = 1;
end
// Generate some data
always @(posedge clk)
begin
if (data_read)
begin
data_in <= data_in + 1'b1;
end
end
// Print output
always @(posedge clk)
begin
if (data_out_en)
begin
$write("%c", data_out);
end
end
// Clock signal
always
begin
#10 clk = 0;
#10 clk = 1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, p, q, a; cin >> p >> q >> n; for (int i = 1; i <= n; i++) { cin >> a; if (q == 0 || a > p / q) return cout << NO , 0; p -= q * a; swap(p, q); } cout << ((q) ? NO : YES ); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFBBN_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__DFBBN_PP_BLACKBOX_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dfbbn (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFBBN_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2BB2O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__A2BB2O_FUNCTIONAL_PP_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__a2bb2o (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
or or0 (or0_out_X , nor0_out, and0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2BB2O_FUNCTIONAL_PP_V |
//SIMPLE TESTBENCH TO VERIFY THAT THINGS ARE ALIVE AND KICKING
`timescale 1 ns/1 ps
module tb_one_port_mem;
parameter addresses = 32;
parameter width = 8;
parameter muxFactor = 0;
//Auto-calculated, user dont touch
localparam addressWidth =$clog2(addresses);
wire [width-1:0] readData;
reg readEnable;
reg [addressWidth-1:0] address;
reg clk;
reg writeEnable;
reg [width-1:0] writeData;
initial
begin
readEnable=0;
address=0;
clk=0;
writeEnable=0;
writeData=0;
end
always
begin
#5 clk = ~clk;
end
integer i;
initial
begin
repeat(10)@(posedge clk);
for(i=0;i<addresses;i=i+1)
begin
readEnable =0;
address =i;
writeEnable =1;
writeData= i[width-1:0];
@(posedge clk);
end
readEnable=0;
address=0;
writeEnable=0;
writeData=0;
repeat(10)@(posedge clk);
for(i=0;i<addresses;i=i+1)
begin
readEnable=1;
address =i;
writeEnable =0;
writeData= 0;
@(posedge clk);
#1;
if(readData[width-1:0] != i[width-1:0])
begin
$display("ERROR");
$finish;
end
end // for (i=0;i<addresses;i=i+1)
$display("Tested %d addresses",addresses);
$display("PASS");
$finish;
end
onePortMem #(.addresses (addresses),
.width (width),
.muxFactor (muxFactor)
) mem (.readData(readData),
.readEnable(readEnable),
.address(address),
.clk(clk),
.writeEnable(writeEnable),
.writeData(writeData));
endmodule // tb
|
#include <bits/stdc++.h> using namespace std; int n, m; int a[205], b[205]; int main() { cin >> n >> m; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < m; i++) cin >> b[i]; for (int i = 0; i < 512; i++) { int cnt = 0; for (int j = 0; j < n; j++) { for (int k = 0; k < m; k++) { if (((a[j] & b[k]) | i) == i) { cnt++; break; } } } if (cnt == n) { cout << i << endl; break; } } } |
#include <bits/stdc++.h> using namespace std; long long dp[300005]; int main() { long long n, k; cin >> n >> k; for (int i = 1; i <= n; i++) for (int j = i + i; j <= n; j += i) dp[j]++; long long sum = 0, m = 0; for (int i = 1; i <= n; i++) { sum += dp[i]; if (sum >= k) { m = i; break; } } vector<pair<long long, long long> > vec; for (int i = m / 2 + 1; i <= m; i++) vec.emplace_back(dp[i], i); sort(vec.rbegin(), vec.rend()); set<int> st; for (int i = 1; i <= m; i++) st.insert(i); k = sum - k; for (int i = 0; i < vec.size() and k > 0; i++) { if (vec[i].first <= k) { k -= vec[i].first; st.erase(vec[i].second); } } if (k != 0) cout << No << endl; else { cout << Yes << endl; cout << st.size() << endl; for (int val : st) cout << val << ; cout << endl; } return 0; } |
#include <bits/stdc++.h> #pragma optimization_level 3 #pragma GCC optimize( Ofast,no-stack-protector,unroll-loops,fast-math,O3 ) #pragma GCC target( avx,avx2,fma ) using namespace std; mt19937 rnd(chrono::steady_clock::now().time_since_epoch().count()); int a, k, nc = 0, isz = 0; vector<unordered_set<int>> n, l; vector<int> cmp, vrt; void dfs(int v) { cmp[v] = nc; vrt.push_back(v); for (int i : l[v]) { if (cmp[i] == -1) dfs(i); else if (cmp[i] != nc) { assert(cmp[i] == 0); isz = 1; } } } int main() { cin.tie(0); cout.tie(0); cin.sync_with_stdio(0); cout.sync_with_stdio(0); ; cin >> a >> k; cmp = vector<int>(a, -1); l = vector<unordered_set<int>>(a, unordered_set<int>()); n = vector<unordered_set<int>>(a, unordered_set<int>()); for (int q = 0; q < k; q++) { int x, y; cin >> x >> y; x--, y--; n[x].insert(y); n[y].insert(x); } for (int q = 0; q < a; q++) { int sos = (a - 1) - n[q].size(); if (sos > a / 2) cmp[q] = 0; } for (int q = 0; q < a; q++) { if (cmp[q] != -1) continue; for (int w = 0; w < a; w++) { if (w == q || n[q].count(w)) continue; l[q].insert(w); } } for (int q = 0; q < a; q++) { if (cmp[q] != -1) continue; nc = q + 1; vrt.clear(); isz = 0; dfs(q); if (isz) { for (int i : vrt) cmp[i] = 0; } } map<int, int> mp; for (int i : cmp) mp[i]++; vector<int> u; for (pair<int, int> p : mp) u.push_back(p.second); sort(u.begin(), u.end()); cout << u.size() << n ; for (int i : u) cout << i << ; } |
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