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#include <bits/stdc++.h> using namespace std; inline int read() { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } namespace SAT2 { vector<int> v[200000 + 5], V[200000 + 5]; int n, b[200000 + 5], dn, q[200000 + 5], mark[200000 + 5], num, yes[200000 + 5]; void init(int sz) { for (int i = 1; i <= sz; ++i) v[i].clear(), V[i].clear(), mark[i] = b[i] = yes[i] = 0; dn = num = 0; n = sz; } void ins(int f, int t) { v[f].push_back(t); v[((t & 1) ? t + 1 : t - 1)].push_back(((f & 1) ? f + 1 : f - 1)); V[t].push_back(f); V[((f & 1) ? f + 1 : f - 1)].push_back(((t & 1) ? t + 1 : t - 1)); } void dfs(int x) { b[x] = 1; for (int i = 0; i < v[x].size(); ++i) if (!b[v[x][i]]) dfs(v[x][i]); q[++dn] = x; } void rdfs(int x) { mark[x] = num; for (int i = 0; i < V[x].size(); ++i) if (!mark[V[x][i]]) rdfs(V[x][i]); } bool Solve() { for (int i = 1; i <= n; ++i) if (!b[i]) dfs(i); for (int i = n; i; --i) if (!mark[q[i]]) ++num, rdfs(q[i]); for (int i = 1; i <= n; ++i) if (mark[i] == mark[((i & 1) ? i + 1 : i - 1)]) return false; for (int i = 1; i <= n; ++i) yes[mark[i] > mark[((i & 1) ? i + 1 : i - 1)] ? i : ((i & 1) ? i + 1 : i - 1)] = 1; return true; } } // namespace SAT2 int n, a, b, s[100000 + 5]; map<int, int> mp; int main() { n = read(); a = read(); b = read(); SAT2::init(2 * n); for (int i = 1; i <= n; ++i) mp[s[i] = read()] = i; for (int i = 1; i <= n; ++i) { int t1 = mp[a - s[i]], t2 = mp[b - s[i]]; if (t1) SAT2::ins(2 * i - 1, 2 * t1 - 1); else SAT2::ins(2 * i - 1, 2 * i); if (t2) SAT2::ins(2 * i, 2 * t2); else SAT2::ins(2 * i, 2 * i - 1); } if (!SAT2::Solve()) return 0 * puts( NO ); puts( YES ); for (int i = 1; i <= n; ++i) printf(SAT2::yes[2 * i - 1] ? 0 : 1 ); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, k, x, y; int main() { cin >> n >> k; int l = 1, r = n, mid; while (l <= r) { if (l == r) { x = l; break; } mid = l + r >> 1; cout << 1 << mid << << mid + 1 << endl; fflush(stdout); string s; cin >> s; if (s == TAK ) r = mid; else l = mid + 1; } l = 1, r = x - 1; while (l <= r) { if (l == r) { y = l; break; } mid = l + r >> 1; cout << 1 << mid << << mid + 1 << endl; fflush(stdout); string s; cin >> s; if (s == TAK ) r = mid; else l = mid + 1; } if (y > 0) { cout << 1 << y << << x << endl; fflush(stdout); string s; cin >> s; if (s == TAK ) { cout << 2 << x << << y << endl; fflush(stdout); return 0; } } l = x + 1, r = n; while (l <= r) { if (l == r) { y = l; break; } mid = l + r >> 1; cout << 1 << mid << << mid + 1 << endl; fflush(stdout); string s; cin >> s; if (s == TAK ) r = mid; else l = mid + 1; } cout << 2 << x << << y << endl; fflush(stdout); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND2B_SYMBOL_V
`define SKY130_FD_SC_HS__AND2B_SYMBOL_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__and2b (
//# {{data|Data Signals}}
input A_N,
input B ,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND2B_SYMBOL_V
|
`include "bsg_defines.v"
`ifndef DATA_WIDTH
`define DATA_WIDTH 8
`endif
`ifndef ADDR_WIDTH
`define ADDR_WIDTH 10
`endif
module testbench ();
localparam width_p = `DATA_WIDTH;
localparam data_width_p = width_p;
localparam mask_width_p = width_p>>3;
localparam els_p=(1<<`ADDR_WIDTH);
localparam addr_width_p=`ADDR_WIDTH;
// Clock generation
logic clk;
bsg_nonsynth_clock_gen
#(.cycle_time_p(1000))
clkgen
(.o(clk));
// Reset generation
logic reset;
bsg_nonsynth_reset_gen
#(.reset_cycles_lo_p(0)
,.reset_cycles_hi_p(20))
resetgen
(.clk_i(clk)
,.async_reset_o(reset));
// DMA memory
logic v_li;
logic w_li;
logic [addr_width_p-1:0] addr_li;
logic [width_p-1:0] data_li;
logic [mask_width_p-1:0] wmask_li;
logic [width_p-1:0] data_lo;
bsg_nonsynth_mem_1rw_sync_mask_write_byte_dma
#(.width_p(width_p)
,.els_p(els_p)
,.id_p(0)
,.init_mem_p(0))
DUT
(.clk_i(clk)
,.reset_i(reset)
,.v_i(v_li)
,.w_i(w_li)
,.addr_i(addr_li)
,.data_i(data_li)
,.w_mask_i(wmask_li)
,.data_o(data_lo)
);
// trace replay
typedef struct packed {
logic write_not_read;
logic [addr_width_p-1:0] addr;
logic [data_width_p-1:0] data;
logic [mask_width_p-1:0] mask;
} trace_s;
localparam ring_width_p = $bits(trace_s);
localparam rom_addr_width_p = 20; // no need to get cute - 1M is plenty
localparam rom_data_width_p=ring_width_p+4;
logic [rom_addr_width_p-1:0] rom_addr_lo;
logic [rom_data_width_p-1:0] rom_data_li;
trace_s trace_lo;
logic trace_v_lo;
logic trace_done_lo;
bsg_fsb_node_trace_replay
#(.ring_width_p(ring_width_p)
,.rom_addr_width_p(rom_addr_width_p))
tr
(.clk_i(clk)
,.reset_i(reset)
,.en_i(1'b1)
,.v_i(1'b0)
,.data_i('0)
,.ready_o()
,.v_o(trace_v_lo)
,.data_o(trace_lo)
,.yumi_i(1'b1)
,.rom_addr_o(rom_addr_lo)
,.rom_data_i(rom_data_li)
,.done_o(trace_done_lo)
,.error_o()
);
// ROM
bsg_nonsynth_test_rom
#(.data_width_p(rom_data_width_p)
,.addr_width_p(rom_addr_width_p)
,.filename_p(`BSG_STRINGIFY(`ROM_FILE)))
rom
(.addr_i(rom_addr_lo)
,.data_o(rom_data_li)
);
assign v_li = trace_v_lo;
assign w_li = trace_lo.write_not_read;
assign data_li = trace_lo.data;
assign addr_li = trace_lo.addr;
assign wmask_li = trace_lo.mask;
always_ff @(posedge clk) begin
if (trace_done_lo) $finish;
end
trace_s trace_r;
logic trace_v_r;
always_ff @(posedge clk) begin
trace_r <= trace_lo;
trace_v_r <= trace_v_lo;
end
// verify values
logic [data_width_p-1:0] verify [els_p-1:0];
always_ff @(posedge clk) begin
if (trace_v_lo) begin
if (trace_lo.write_not_read) begin
for (int i = 0; i < mask_width_p; i++) begin
if (trace_lo.mask[i])
verify[trace_lo.addr][i*8+:8] <= trace_lo.data[i*8+:8];
end
end
end
else if (reset) begin
for (int i = 0; i < els_p; i++) begin
verify[i] <= '0;
end
end
end
always_ff @(posedge clk) begin
assert(reset // reset
| ~(trace_v_r & ~trace_r.write_not_read) // didn't just read a value
| (verify[trace_r.addr] == data_lo)) else // assert equal o/w
$error("Mismatch: address=%08x, got %08x, expected %08x",
trace_r.addr, data_lo, verify[trace_r.addr]);
end
if (0) begin
always_ff @(posedge clk) begin
if (v_li & w_li) begin
$display("[DEBUG] Writing address = %08x, data = %08x, mask=%08x\n",
addr_li, data_li, wmask_li);
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e9 + 7; const int N = 5e2 + 10; int a[N][N]; int b[N][N]; int c[N][N]; int minv[N]; int main() { int n, m, k; scanf( %d%d%d , &n, &m, &k); memset((minv), (0x3f), sizeof(minv)); for (int i = 1; i <= n; i++) { scanf( %*s ); for (int j = 1; j <= m; j++) { cin >> a[i][j] >> b[i][j] >> c[i][j]; } } int ans = 0; for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { vector<int> v; for (int o = 1; o <= m; o++) { for (int t = 0; t < c[i][o]; t++) v.push_back(max(0, b[j][o] - a[i][o])); } sort(v.rbegin(), v.rend()); int sum = 0; for (int o = 0; o < k && o < v.size(); o++) sum += v[o]; ans = max(ans, sum); } } cout << ans << endl; return 0; } |
//----------------------------------------------------------------------------
//-- Ejemplo de uso de una memoria rom generica
//-- Se reproduce en los leds la secuencia definida en el fichero rom1.list
//------------------------------------------
//-- (C) BQ. October 2015. Written by Juan Gonzalez (Obijuan)
//-- GPL license
//----------------------------------------------------------------------------
`default_nettype none
`include "divider.vh"
module genromleds (input wire clk,
output wire [4:0] leds);
//- Tiempo de envio
parameter DELAY = `T_500ms;
//-- Fichero con la rom
parameter ROMFILE = "rom1.list";
//-- Numero de bits de la direccione
parameter AW = 5;
parameter DW = 5;
//-- Cable para direccionar la memoria
reg [AW-1: 0] addr;
reg rstn = 0;
wire clk_delay;
//-- Instanciar la memoria rom
genrom
#( .ROMFILE(ROMFILE),
.AW(AW),
.DW(DW))
ROM (
.clk(clk),
.addr(addr),
.data(leds)
);
//-- Contador
always @(negedge clk)
if (rstn == 0)
addr <= 0;
else if (clk_delay)
addr <= addr + 1;
//---------------------------
//-- Temporizador
//---------------------------
dividerp1 #(.M(DELAY))
DIV0 ( .clk(clk),
.clk_out(clk_delay)
);
//-- Inicializador
always @(negedge clk)
rstn <= 1;
endmodule
|
(* Copyright (c) 2008-2012, Adam Chlipala
*
* This work is licensed under a
* Creative Commons Attribution-Noncommercial-No Derivative Works 3.0
* Unported License.
* The license text is available at:
* http://creativecommons.org/licenses/by-nc-nd/3.0/
*)
Require Import Eqdep List Lists.List.
Require Omega.
Set Implicit Arguments.
(** A version of [injection] that does some standard simplifications afterward: clear the hypothesis in question, bring the new facts above the double line, and attempt substitution for known variables. *)
Ltac inject H := injection H; clear H; intros; try subst.
(** Try calling tactic function [f] on all hypotheses, keeping the first application that doesn't fail. *)
Ltac appHyps f :=
match goal with
| [ H : _ |- _ ] => f H
end.
(** Succeed iff [x] is in the list [ls], represented with left-associated nested tuples. *)
Ltac inList x ls :=
match ls with
| x => idtac
| (_, x) => idtac
| (?LS, _) => inList x LS
end.
(** Try calling tactic function [f] on every element of tupled list [ls], keeping the first call not to fail. *)
Ltac app f ls :=
match ls with
| (?LS, ?X) => f X || app f LS || fail 1
| _ => f ls
end.
(** Run [f] on every element of [ls], not just the first that doesn't fail. *)
Ltac all f ls :=
match ls with
| (?LS, ?X) => f X; all f LS
| (_, _) => fail 1
| _ => f ls
end.
(** Workhorse tactic to simplify hypotheses for a variety of proofs.
* Argument [invOne] is a tuple-list of predicates for which we always do inversion automatically. *)
Ltac simplHyp invOne :=
(** Helper function to do inversion on certain hypotheses, where [H] is the hypothesis and [F] its head symbol *)
let invert H F :=
(** We only proceed for those predicates in [invOne]. *)
inList F invOne;
(** This case covers an inversion that succeeds immediately, meaning no constructors of [F] applied. *)
(inversion H; fail)
(** Otherwise, we only proceed if inversion eliminates all but one constructor case. *)
|| (inversion H; [idtac]; clear H; try subst) in
match goal with
(** Eliminate all existential hypotheses. *)
| [ H : ex _ |- _ ] => destruct H
(** Find opportunities to take advantage of injectivity of data constructors, for several different arities. *)
| [ H : ?F ?X = ?F ?Y |- ?G ] =>
(** This first branch of the [||] fails the whole attempt iff the arguments of the constructor applications are already easy to prove equal. *)
(assert (X = Y); [ assumption | fail 1 ])
(** If we pass that filter, then we use injection on [H] and do some simplification as in [inject].
* The odd-looking check of the goal form is to avoid cases where [injection] gives a more complex result because of dependent typing, which we aren't equipped to handle here. *)
|| (injection H;
match goal with
| [ |- X = Y -> G ] =>
try clear H; intros; try subst
end)
| [ H : ?F ?X ?U = ?F ?Y ?V |- ?G ] =>
(assert (X = Y); [ assumption
| assert (U = V); [ assumption | fail 1 ] ])
|| (injection H;
match goal with
| [ |- U = V -> X = Y -> G ] =>
try clear H; intros; try subst
end)
(** Consider some different arities of a predicate [F] in a hypothesis that we might want to invert. *)
| [ H : ?F _ |- _ ] => invert H F
| [ H : ?F _ _ |- _ ] => invert H F
| [ H : ?F _ _ _ |- _ ] => invert H F
| [ H : ?F _ _ _ _ |- _ ] => invert H F
| [ H : ?F _ _ _ _ _ |- _ ] => invert H F
(** Use an (axiom-dependent!) inversion principle for dependent pairs, from the standard library. *)
| [ H : existT _ ?T _ = existT _ ?T _ |- _ ] => generalize (inj_pair2 _ _ _ _ _ H); clear H
(** If we're not ready to use that principle yet, try the standard inversion, which often enables the previous rule. *)
| [ H : existT _ _ _ = existT _ _ _ |- _ ] => inversion H; clear H
(** Similar logic to the cases for constructor injectivity above, but specialized to [Some], since the above cases won't deal with polymorphic constructors. *)
| [ H : Some _ = Some _ |- _ ] => injection H; clear H
end.
(** Find some hypothesis to rewrite with, ensuring that [auto] proves all of the extra subgoals added by [rewrite]. *)
Ltac rewriteHyp :=
match goal with
| [ H : _ |- _ ] => rewrite H by solve [ auto ]
end.
(** Combine [autorewrite] with automatic hypothesis rewrites. *)
Ltac rewriterP := repeat (rewriteHyp; autorewrite with core in *).
Ltac rewriter := autorewrite with core in *; rewriterP.
(** This one is just so darned useful, let's add it as a hint here. *)
Hint Rewrite <- app_assoc.
(** Devious marker predicate to use for encoding state within proof goals *)
Definition done (T : Type) (x : T) := True.
(** Try a new instantiation of a universally quantified fact, proved by [e].
* [trace] is an accumulator recording which instantiations we choose. *)
Ltac inster e trace :=
(** Does [e] have any quantifiers left? *)
match type of e with
| forall x : _, _ =>
(** Yes, so let's pick the first context variable of the right type. *)
match goal with
| [ H : _ |- _ ] =>
inster (e H) (trace, H)
| _ => fail 2
end
| _ =>
(** No more quantifiers, so now we check if the trace we computed was already used. *)
match trace with
| (_, _) =>
(** We only reach this case if the trace is nonempty, ensuring that [inster] fails if no progress can be made. *)
match goal with
| [ H : done (trace, _) |- _ ] =>
(** Uh oh, found a record of this trace in the context! Abort to backtrack to try another trace. *)
fail 1
| _ =>
(** What is the type of the proof [e] now? *)
let T := type of e in
match type of T with
| Prop =>
(** [e] should be thought of as a proof, so let's add it to the context, and also add a new marker hypothesis recording our choice of trace. *)
generalize e; intro;
assert (done (trace, tt)) by constructor
| _ =>
(** [e] is something beside a proof. Better make sure no element of our current trace was generated by a previous call to [inster], or we might get stuck in an infinite loop! (We store previous [inster] terms in second positions of tuples used as arguments to [done] in hypotheses. Proofs instantiated by [inster] merely use [tt] in such positions.) *)
all ltac:(fun X =>
match goal with
| [ H : done (_, X) |- _ ] => fail 1
| _ => idtac
end) trace;
(** Pick a new name for our new instantiation. *)
let i := fresh "i" in (pose (i := e);
assert (done (trace, i)) by constructor)
end
end
end
end.
(** After a round of application with the above, we will have a lot of junk [done] markers to clean up; hence this tactic. *)
Ltac un_done :=
repeat match goal with
| [ H : done _ |- _ ] => clear H
end.
Require Import JMeq.
(** A more parameterized version of the famous [crush]. Extra arguments are:
* - A tuple-list of lemmas we try [inster]-ing
* - A tuple-list of predicates we try inversion for *)
Ltac crush' lemmas invOne :=
(** A useful combination of standard automation *)
let sintuition := simpl in *; intuition; try subst;
repeat (simplHyp invOne; intuition; try subst); try congruence in
(** A fancier version of [rewriter] from above, which uses [crush'] to discharge side conditions *)
let rewriter := autorewrite with core in *;
repeat (match goal with
| [ H : ?P |- _ ] =>
match P with
| context[JMeq] => fail 1 (** JMeq is too fancy to deal with here. *)
| _ => rewrite H by crush' lemmas invOne
end
end; autorewrite with core in *) in
(** Now the main sequence of heuristics: *)
(sintuition; rewriter;
match lemmas with
| false => idtac (** No lemmas? Nothing to do here *)
| _ =>
(** Try a loop of instantiating lemmas... *)
repeat ((app ltac:(fun L => inster L L) lemmas
(** ...or instantiating hypotheses... *)
|| appHyps ltac:(fun L => inster L L));
(** ...and then simplifying hypotheses. *)
repeat (simplHyp invOne; intuition)); un_done
end;
sintuition; rewriter; sintuition;
(** End with a last attempt to prove an arithmetic fact with [omega], or prove any sort of fact in a context that is contradictory by reasoning that [omega] can do. *)
try omega; try (elimtype False; omega)).
(** [crush] instantiates [crush'] with the simplest possible parameters. *)
Ltac crush := crush' false fail.
(** * Wrap Program's [dependent destruction] in a slightly more pleasant form *)
Require Import Program.Equality.
(** Run [dependent destruction] on [E] and look for opportunities to simplify the result.
The weird introduction of [x] helps get around limitations of [dependent destruction], in terms of which sorts of arguments it will accept (e.g., variables bound to hypotheses within Ltac [match]es). *)
Ltac dep_destruct E :=
let x := fresh "x" in
remember E as x; simpl in x; dependent destruction x;
try match goal with
| [ H : _ = E |- _ ] => rewrite <- H in *; clear H
end.
(** Nuke all hypotheses that we can get away with, without invalidating the goal statement. *)
Ltac clear_all :=
repeat match goal with
| [ H : _ |- _ ] => clear H
end.
(** Instantiate a quantifier in a hypothesis [H] with value [v], or, if [v] doesn't have the right type, with a new unification variable.
* Also prove the lefthand sides of any implications that this exposes, simplifying [H] to leave out those implications. *)
Ltac guess v H :=
repeat match type of H with
| forall x : ?T, _ =>
match type of T with
| Prop =>
(let H' := fresh "H'" in
assert (H' : T); [
solve [ eauto 6 ]
| specialize (H H'); clear H' ])
|| fail 1
| _ =>
specialize (H v)
|| let x := fresh "x" in
evar (x : T);
let x' := eval unfold x in x in
clear x; specialize (H x')
end
end.
(** Version of [guess] that leaves the original [H] intact *)
Ltac guessKeep v H :=
let H' := fresh "H'" in
generalize H; intro H'; guess v H'.
|
#include <bits/stdc++.h> using namespace std; std::mt19937 rnd( (int)std::chrono::steady_clock::now().time_since_epoch().count()); long long gcd(long long a, long long b) { return b == 0 ? a : gcd(b, a % b); } const int MAXH = 100000; const int MAXW = 100000; const int MAXDIM = MAXH >= MAXW ? MAXH : MAXW; const int MAXQ = 100000; const int MAXS = 4 * MAXDIM; int h, w, nq; char initlft[MAXH + 1]; char initrgt[MAXH + 1]; char inittop[MAXW + 1]; char initbot[MAXW + 1]; char qside[MAXQ]; int ql[MAXQ], qr[MAXQ], qans[MAXQ + 1]; struct SegNode { int cost[2][2][2][2]; bool lazyfliptop, lazyflipbot; int cntblue[2], cntred[2]; }; struct SegTree { int n; int crosscost, lftcost[2], rgtcost[2]; char inittop[MAXDIM + 1]; char initbot[MAXDIM + 1]; SegNode sval[MAXS]; void sfliptop(int x) { swap(sval[x].cntblue[0], sval[x].cntred[0]); for (int lftcol = (0); lftcol < (2); ++lftcol) for (int rgtcol = (0); rgtcol < (2); ++rgtcol) for (int botflip = (0); botflip < (2); ++botflip) swap(sval[x].cost[lftcol][rgtcol][0][botflip], sval[x].cost[lftcol][rgtcol][1][botflip]); sval[x].lazyfliptop = !sval[x].lazyfliptop; } void sflipbot(int x) { swap(sval[x].cntblue[1], sval[x].cntred[1]); for (int lftcol = (0); lftcol < (2); ++lftcol) for (int rgtcol = (0); rgtcol < (2); ++rgtcol) for (int topflip = (0); topflip < (2); ++topflip) swap(sval[x].cost[lftcol][rgtcol][topflip][0], sval[x].cost[lftcol][rgtcol][topflip][1]); sval[x].lazyflipbot = !sval[x].lazyflipbot; } void spush(int x) { if (sval[x].lazyfliptop) sfliptop(2 * x + 1), sfliptop(2 * x + 2), sval[x].lazyfliptop = false; if (sval[x].lazyflipbot) sflipbot(2 * x + 1), sflipbot(2 * x + 2), sval[x].lazyflipbot = false; } void spull(int x) { const SegNode &a = sval[2 * x + 1]; const SegNode &b = sval[2 * x + 2]; for (int side = (0); side < (2); ++side) sval[x].cntblue[side] = a.cntblue[side] + b.cntblue[side]; for (int side = (0); side < (2); ++side) sval[x].cntred[side] = a.cntred[side] + b.cntred[side]; for (int lftcol = (0); lftcol < (2); ++lftcol) for (int rgtcol = (0); rgtcol < (2); ++rgtcol) for (int topflip = (0); topflip < (2); ++topflip) for (int botflip = (0); botflip < (2); ++botflip) { int cur = INT_MAX; for (int midcol1 = (0); midcol1 < (2); ++midcol1) for (int midcol2 = (0); midcol2 < (2); ++midcol2) { int acost = a.cost[lftcol][midcol1][topflip][botflip]; int bcost = b.cost[midcol2][rgtcol][topflip][botflip]; int ccost = midcol1 == midcol2 ? 0 : crosscost; if (acost == INT_MAX || bcost == INT_MAX) continue; cur = min(cur, acost + bcost + ccost); } sval[x].cost[lftcol][rgtcol][topflip][botflip] = cur; } } void sinit(int x, int l, int r) { sval[x].lazyfliptop = sval[x].lazyflipbot = false; if (l == r) { int sa = inittop[l] == B ? 0 : 1; int sb = initbot[l] == B ? 0 : 1; sval[x].cntblue[0] = sa == 0 ? 1 : 0, sval[x].cntred[0] = 1 - sval[x].cntblue[0]; sval[x].cntblue[1] = sb == 0 ? 1 : 0, sval[x].cntred[1] = 1 - sval[x].cntblue[1]; for (int lftcol = (0); lftcol < (2); ++lftcol) for (int rgtcol = (0); rgtcol < (2); ++rgtcol) for (int topflip = (0); topflip < (2); ++topflip) for (int botflip = (0); botflip < (2); ++botflip) { int cur; if (lftcol == rgtcol) { int a = sa; if (topflip) a = 1 - a; int b = sb; if (botflip) b = 1 - b; cur = (a == lftcol ? 0 : 1) + (b == lftcol ? 0 : 1); } else { cur = INT_MAX; } sval[x].cost[lftcol][rgtcol][topflip][botflip] = cur; } } else { int m = l + (r - l) / 2; sinit(2 * x + 1, l, m); sinit(2 * x + 2, m + 1, r); spull(x); } } void sflip(int x, int l, int r, int L, int R, bool istop) { if (L <= l && r <= R) { if (istop) sfliptop(x); else sflipbot(x); } else { int m = l + (r - l) / 2; spush(x); if (L <= m) sflip(2 * x + 1, l, m, L, R, istop); if (m + 1 <= R) sflip(2 * x + 2, m + 1, r, L, R, istop); spull(x); } } void init() { sinit(0, 0, n - 1); } void flip(int l, int r, bool istop) { sflip(0, 0, n - 1, l, r, istop); } int calc() { int ret = INT_MAX; for (int lftcol = (0); lftcol < (2); ++lftcol) for (int rgtcol = (0); rgtcol < (2); ++rgtcol) { int cur = sval[0].cost[lftcol][rgtcol][0][0]; if (cur == INT_MAX) continue; cur += lftcost[lftcol]; cur += rgtcost[rgtcol]; ret = min(ret, cur); } return ret; } }; SegTree stopbot, slftrgt; int calc() { stopbot.lftcost[0] = slftrgt.sval[0].cntred[0], stopbot.lftcost[1] = slftrgt.sval[0].cntblue[0]; stopbot.rgtcost[0] = slftrgt.sval[0].cntred[1], stopbot.rgtcost[1] = slftrgt.sval[0].cntblue[1]; slftrgt.lftcost[0] = stopbot.sval[0].cntred[0], slftrgt.lftcost[1] = stopbot.sval[0].cntblue[0]; slftrgt.rgtcost[0] = stopbot.sval[0].cntred[1], slftrgt.rgtcost[1] = stopbot.sval[0].cntblue[1]; return min(stopbot.calc(), slftrgt.calc()); } void solve() { stopbot.n = w, stopbot.crosscost = h; for (int i = (0); i <= (w); ++i) stopbot.inittop[i] = inittop[i], stopbot.initbot[i] = initbot[i]; stopbot.init(); slftrgt.n = h, slftrgt.crosscost = w; for (int i = (0); i <= (h); ++i) slftrgt.inittop[i] = initlft[i], slftrgt.initbot[i] = initrgt[i]; slftrgt.init(); qans[0] = calc(); for (int i = (0); i < (nq); ++i) { char side = qside[i]; int l = ql[i], r = qr[i]; if (side == U ) stopbot.flip(l, r, true); if (side == D ) stopbot.flip(l, r, false); if (side == L ) slftrgt.flip(l, r, true); if (side == R ) slftrgt.flip(l, r, false); qans[i + 1] = calc(); } } void run() { scanf( %d%d%d , &h, &w, &nq); scanf( %s , initlft); scanf( %s , initrgt); scanf( %s , inittop); scanf( %s , initbot); for (int i = (0); i < (nq); ++i) scanf( %c%d%d , &qside[i], &ql[i], &qr[i]), --ql[i], --qr[i]; solve(); for (int i = (0); i <= (nq); ++i) printf( %d n , qans[i]); } void stress() { h = MAXH, w = MAXW, nq = MAXQ; for (int i = (0); i < (h); ++i) initlft[i] = BR [rnd() % 2]; initlft[h] = 0 ; for (int i = (0); i < (h); ++i) initrgt[i] = BR [rnd() % 2]; initrgt[h] = 0 ; for (int i = (0); i < (w); ++i) inittop[i] = BR [rnd() % 2]; inittop[w] = 0 ; for (int i = (0); i < (w); ++i) initbot[i] = BR [rnd() % 2]; initbot[w] = 0 ; for (int i = (0); i < (nq); ++i) { qside[i] = UDLR [rnd() % 4]; int dim = qside[i] == U || qside[i] == D ? w : h; ql[i] = rnd() % dim, qr[i] = rnd() % dim; if (ql[i] > qr[i]) swap(ql[i], qr[i]); } solve(); printf( done n ); } int main() { run(); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O22A_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__O22A_BEHAVIORAL_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__o22a (
X ,
A1,
A2,
B1,
B2
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X, or0_out, or1_out);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O22A_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; long long int pow_mod(long long int a, long long int b) { long long int res = 1; while (b != 0) { if (b & 1) { res = (res * a) % 1000000007; } a = (a * a) % 1000000007; b /= 2; } return res; } long long int inv(long long int x) { return pow_mod(x, 1000000007 - 2); } void solve() { long long int n; cin >> n; long long int x = 2 * n - 1; long long int y = n; long long int res1 = 1; for (long long int i = 0; i < y; i++) res1 = (res1 * (x - i)) % 1000000007; long long int res2 = 1; for (long long int i = 1; i <= y; i++) res2 = (res2 * i) % 1000000007; long long int ans = (res1 * inv(res2)) % 1000000007; ans *= 2; ans %= 1000000007; ans -= n; ans += 1000000007; ans %= 1000000007; cout << ans << endl; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int t; t = 1; while (t--) solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { std::ios_base::sync_with_stdio(false); cin.tie(0); long long int n, i, j, x, in = 0; string s; vector<pair<string, long long int>> v; priority_queue<long long int, vector<long long int>, greater<long long int>> pq; cin >> n; long long int mn = 1000000000000000000LL, dummy = -1; for (i = 1; i <= n; i++) { cin >> s; if (s == insert ) { cin >> x; v.push_back(make_pair(s, x)); pq.push(x); } else if (s == getMin ) { cin >> x; if (pq.size() != 0) mn = pq.top(); else mn = -1; if (x != mn) { if (x > mn) { while (x > mn && pq.size() != 0) { mn = pq.top(); if (mn >= x) break; pq.pop(); v.push_back(make_pair( removeMin , -1)); } if (x == mn && pq.size() != 0) { v.push_back(make_pair(s, x)); } else if ((mn > x && pq.size() != 0) || pq.size() == 0) { v.push_back(make_pair( insert , x)); pq.push(x); v.push_back(make_pair(s, x)); } } else { v.push_back(make_pair( insert , x)); pq.push(x); v.push_back(make_pair(s, x)); } } else { v.push_back(make_pair(s, x)); } } else if (s == removeMin ) { if (pq.size() != 0) pq.pop(); else { v.push_back(make_pair( insert , 0)); } v.push_back(make_pair(s, -1)); } } cout << v.size() << endl; for (i = 0; i < v.size(); i++) { cout << v[i].first << ; if (v[i].first != removeMin ) cout << v[i].second << endl; else cout << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int nax = 3e5 + 5; int nxt[nax][20]; int reach[20]; int main() { int n, q; cin >> n >> q; vector<int> arr(n); for (int i = 0; i < n; i++) cin >> arr[i]; for (int bit = 0; bit < 19; bit++) reach[bit] = n; for (int i = n - 1; i >= 0; i--) { for (int bit = 0; bit < 19; bit++) { nxt[i][bit] = n; } for (int bit = 0; bit < 19; bit++) { if (arr[i] & (1 << bit)) { nxt[i][bit] = min(nxt[i][bit], reach[bit]); if (reach[bit] < n) { for (int j = 0; j < 19; j++) { nxt[i][j] = min(nxt[i][j], nxt[reach[bit]][j]); } } reach[bit] = i; } } } while (q--) { int x, y; cin >> x >> y; x--; y--; bool res = false; for (int bit = 0; bit < 19; bit++) { if (arr[y] & (1 << bit)) { if (nxt[x][bit] <= y) { res = true; break; } } } (res ? cout << Shi n : cout << Fou n ); } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2111O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__A2111O_BEHAVIORAL_PP_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__a2111o (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X , C1, B1, and0_out, D1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2111O_BEHAVIORAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A21OI_FUNCTIONAL_V
`define SKY130_FD_SC_MS__A21OI_FUNCTIONAL_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__a21oi (
Y ,
A1,
A2,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, B1, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A21OI_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; struct T { T *l, *r; int v; int c; T(int v) : v(v), c(1) { l = r = NULL; } T(T *a) { l = a->l; r = a->r; v = a->v; c = a->c; } T() {} }; T pool[(5000000) + 10000]; int stack_size; T *my_new(int v) { return &(pool[stack_size++] = T(v)); } T *my_new(T *a) { return &(pool[stack_size++] = T(a)); } int count(T *c) { if (!c) return 0; else return c->c; } T *update(T *c) { if (!c) return c; c->c = count(c->l) + count(c->r) + 1; return c; } T *merge(T *a, T *b, int flag = 1) { if (!a) return b; if (!b) return a; if (rand() % (count(a) + count(b)) < count(a)) { T *R = flag ? my_new(a) : a; R->r = merge(a->r, b, flag); return update(R); } else { T *R = flag ? my_new(b) : b; R->l = merge(a, b->l, flag); return update(R); } } pair<T *, T *> split(T *c, int k, int flag = 1) { if (!c) return make_pair(c, c); T *R = flag ? my_new(c) : c; if (k <= count(c->l)) { pair<T *, T *> s = split(c->l, k, flag); R->l = s.second; return make_pair(s.first, update(R)); } else { pair<T *, T *> s = split(c->r, k - count(c->l) - 1, flag); R->r = s.first; return make_pair(update(R), s.second); } } T *insert(T *c, int k, int value) { pair<T *, T *> div = split(c, k, 0); T *mono_tree = my_new(value); return merge(merge(div.first, mono_tree, 0), div.second, 0); } int tmp[100010]; int tmp2[100010]; int N, M, m; pair<T *, T *> generate_tree() { stack_size = 0; T *root1 = NULL; T *root2 = NULL; for (int i = 0; i < N; i++) root1 = insert(root1, i, tmp[i]); for (int i = 0; i < N; i++) root2 = insert(root2, i, tmp2[i]); return make_pair(root1, root2); } void write(int *arr, T *c) { if (m >= N) return; if (!c) return; write(arr, c->l); if (m < N) arr[m++] = c->v; write(arr, c->r); } int main() { scanf( %d%d , &N, &M); for (int i = 0; i < N; i++) { scanf( %d , &tmp[i]); } for (int i = 0; i < N; i++) { scanf( %d , &tmp2[i]); } T *A, *B; pair<T *, T *> hoge = generate_tree(); A = hoge.first; B = hoge.second; for (int i = 0; i < M; i++) { int a; int x, y, k; scanf( %d , &a); if (a == 1) { scanf( %d%d%d , &x, &y, &k); x--, y--; pair<T *, T *> sub = split(A, x); pair<T *, T *> sub2 = split(sub.second, k); pair<T *, T *> sub3 = split(B, y); pair<T *, T *> sub4 = split(sub3.second, k); T *f1 = merge(sub3.first, sub2.first); T *f2 = merge(f1, sub4.second); B = f2; if (stack_size > (5000000)) { m = 0; write(tmp, A); m = 0; write(tmp2, B); pair<T *, T *> hoge = generate_tree(); A = hoge.first; B = hoge.second; } } else { scanf( %d , &x); x--; pair<T *, T *> sub = split(B, x); pair<T *, T *> sub2 = split(sub.second, 1); printf( %d n , sub2.first->v); } } } |
#include <bits/stdc++.h> using namespace std; using LL = long long; using ULL = unsigned long long; using VI = vector<int>; using VL = vector<LL>; using PII = pair<int, int>; using PLL = pair<LL, LL>; void dout() { cerr << endl; } template <typename Head, typename... Tail> void dout(Head H, Tail... T) { cerr << H << ; dout(T...); } const int MAX = 1 << 10; int a[MAX][MAX]; set<int> s[MAX]; int main() { ios::sync_with_stdio(false); cin.tie(0); int n, m, k; cin >> n >> m >> k; for (int i = (0); i < (n); ++i) for (int j = (0); j < (m); ++j) { cin >> a[i][j]; if (a[i][j] != 2) s[j].insert(i); } while (k--) { int c; cin >> c; c--; int r = 0; while (true) { auto it = s[c].lower_bound(r); if (it == s[c].end()) break; int nr = *it; int& na = a[nr][c]; s[c].erase(it); if (na == 1) { c++; } else { assert(na == 3); c--; } na = 2; r = nr; } cout << c + 1 << ; } cout << n ; } |
/*---------------------------------------------------------------------------------------------------------------------
-- Author: Peter Hasza,
--
-- Create Date: 04/02/2017
-- Module Name: fifo
-- Project Name: AXI_SPI_IF
-- Description:
-- Generic fifo module
--
------------------------------ REVISION HISTORY -----------------------------------------------------------------------
--
-- 2017.apr.2 | hp3265 || Initial version
--
-----------------------------------------------------------------------------------------------------------------------*/
`include "utils.v"
module fifo(
input clk_i,
input rst_i,
input [g_width-1:0] data_i,
input push_i,
input pull_i,
output [g_width-1:0] data_o,
output full_o,
output empty_o
);
parameter g_width = 32;
parameter g_depth = 1;
`CLOGB2(clogb2);
localparam c_ptr_width = clogb2(g_depth);
/*=============================================================================================
-- Locals
--=============================================================================================*/
reg [g_width-1:0] mem[0:g_depth-1];
reg [c_ptr_width-1:0] wr_ptr, rd_ptr;
wire [c_ptr_width-1:0] wr_ptr_next, rd_ptr_next;
reg gb;
integer k;
initial
begin
for (k = 0; k < g_depth ; k = k + 1)
begin
mem[k] = 32'h0000_0000;
end
end
/*=============================================================================================
-- Pointer settting
--=============================================================================================*/
always @(posedge clk_i, negedge rst_i)
if(!rst_i) wr_ptr <= 0;
else if(push_i) wr_ptr <= wr_ptr_next;
always @(posedge clk_i, negedge rst_i)
if(!rst_i) rd_ptr <= 0;
else if(pull_i) rd_ptr <= rd_ptr_next;
`TRUNC(trunc_signal, c_ptr_width + 1, c_ptr_width);
assign wr_ptr_next = trunc_signal(wr_ptr + 1);
assign rd_ptr_next = trunc_signal(rd_ptr + 1);
// Fifo Output
assign data_o = mem[ rd_ptr ];
// Fifo Input
always @(posedge clk_i)
if(push_i) mem[ wr_ptr ] <= data_i;
// Status
assign empty_o = (wr_ptr == rd_ptr) & !gb;
assign full_o = (wr_ptr == rd_ptr) & gb;
// Guard Bit ...
always @(posedge clk_i, negedge rst_i)
if(!rst_i) gb <= 0;
else if((wr_ptr_next == rd_ptr) & push_i) gb <= 1;
else if(pull_i) gb <= 0;
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 13 12:44:42 2017
// Host : WK117 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_microblaze_0_xlconcat_0/system_microblaze_0_xlconcat_0_sim_netlist.v
// Design : system_microblaze_0_xlconcat_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35ticsg324-1L
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_microblaze_0_xlconcat_0,xlconcat,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "xlconcat,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_microblaze_0_xlconcat_0
(In0,
In1,
In2,
In3,
In4,
In5,
In6,
dout);
input [0:0]In0;
input [0:0]In1;
input [0:0]In2;
input [0:0]In3;
input [0:0]In4;
input [0:0]In5;
input [0:0]In6;
output [6:0]dout;
wire [0:0]In0;
wire [0:0]In1;
wire [0:0]In2;
wire [0:0]In3;
wire [0:0]In4;
wire [0:0]In5;
wire [0:0]In6;
assign dout[6] = In6;
assign dout[5] = In5;
assign dout[4] = In4;
assign dout[3] = In3;
assign dout[2] = In2;
assign dout[1] = In1;
assign dout[0] = In0;
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__TAPVGND_TB_V
`define SKY130_FD_SC_HD__TAPVGND_TB_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection
* 1 row down.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__tapvgnd.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_hd__tapvgnd dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__TAPVGND_TB_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
//// ////
//// Description ////
//// This block is a wrapper with common single-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// single-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Supported ASIC RAMs are: ////
//// - Artisan Single-Port Sync RAM ////
//// - Avant! Two-Port Sync RAM (*) ////
//// - Virage Single-Port Sync RAM ////
//// - Virtual Silicon Single-Port Sync RAM ////
//// ////
//// Supported FPGA RAMs are: ////
//// - Xilinx Virtex RAMB4_S16 ////
//// - Altera LPM ////
//// ////
//// To Do: ////
//// - xilinx rams need external tri-state logic ////
//// - fix avant! two-port ram ////
//// - add additional RAMs ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_spram_64x14(
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, doq
);
//
// Default address and data buses width
//
parameter aw = 6;
parameter dw = 14;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
input rst; // Reset
input ce; // Chip enable input
input we; // Write enable input
input oe; // Output enable input
input [aw-1:0] addr; // address bus inputs
input [dw-1:0] di; // input data bus
output [dw-1:0] doq; // output data bus
//
// Internal wires and registers
//
wire [1:0] unconnected;
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
`ifdef OR1200_ARTISAN_SSP
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_64x14 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_64x14_bist artisan_ssp(
`else
art_hssp_64x14 artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
.WEN(~we),
.A(addr),
.D(di),
.OEN(~oe),
.Q(doq)
);
`else
`ifdef OR1200_AVANT_ATP
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
.web(~we),
.reb(),
.oeb(~oe),
.rcsb(),
.wcsb(),
.ra(addr),
.wa(addr),
.di(di),
.doq(doq)
);
`else
`ifdef OR1200_VIRAGE_SSP
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
.clk(clk),
.adr(addr),
.d(di),
.we(we),
.oe(oe),
.me(ce),
.q(doq)
);
`else
`ifdef OR1200_VIRTUALSILICON_SSP
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_64x14 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_64x14_bist vs_ssp(
`else
vs_hdsp_64x14 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
.DI(di),
.WEN(~we),
.CEN(~ce),
.OEN(~oe),
.DOUT(doq)
);
`else
`ifdef OR1200_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
//
// Block 0
//
RAMB4_S16 ramb4_s16_0(
.CLK(clk),
.RST(rst),
.ADDR({2'b00, addr}),
.DI({unconnected, di[13:0]}),
.EN(ce),
.WE(we),
.DO({unconnected, doq[13:0]})
);
`else
`ifdef OR1200_ALTERA_LPM
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
wire wr;
assign wr = ce & we;
initial $display("Using Altera LPM.");
lpm_ram_dq lpm_ram_dq_component (
.address(addr),
.inclock(clk),
.outclock(clk),
.data(di),
.we(wr),
.q(doq)
);
defparam lpm_ram_dq_component.lpm_width = dw,
lpm_ram_dq_component.lpm_widthad = aw,
lpm_ram_dq_component.lpm_indata = "REGISTERED",
lpm_ram_dq_component.lpm_address_control = "REGISTERED",
lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
// examplar attribute lpm_ram_dq_component NOOPT TRUE
`else
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [aw-1:0] addr_reg; // RAM address register
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
//
// RAM address register
//
always @(posedge clk or posedge rst)
if (rst)
addr_reg <= #1 {aw{1'b0}};
else if (ce)
addr_reg <= #1 addr;
//
// RAM write
//
always @(posedge clk)
if (ce && we)
mem[addr] <= #1 di;
`endif // !OR1200_ALTERA_LPM
`endif // !OR1200_XILINX_RAMB4_S16
`endif // !OR1200_VIRTUALSILICON_SSP
`endif // !OR1200_VIRAGE_SSP
`endif // !OR1200_AVANT_ATP
`endif // !OR1200_ARTISAN_SSP
endmodule
|
/*
Copyright (c) 2014-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog-2001
`timescale 1 ns / 1 ps
/*
* Synchronizes switch and button inputs with a slow sampled shift register
*/
module debounce_switch #(
parameter WIDTH=1, // width of the input and output signals
parameter N=3, // length of shift register
parameter RATE=125000 // clock division factor
)(
input wire clk,
input wire rst,
input wire [WIDTH-1:0] in,
output wire [WIDTH-1:0] out
);
reg [23:0] cnt_reg = 24'd0;
reg [N-1:0] debounce_reg[WIDTH-1:0];
reg [WIDTH-1:0] state;
/*
* The synchronized output is the state register
*/
assign out = state;
integer k;
always @(posedge clk or posedge rst) begin
if (rst) begin
cnt_reg <= 0;
state <= 0;
for (k = 0; k < WIDTH; k = k + 1) begin
debounce_reg[k] <= 0;
end
end else begin
if (cnt_reg < RATE) begin
cnt_reg <= cnt_reg + 24'd1;
end else begin
cnt_reg <= 24'd0;
end
if (cnt_reg == 24'd0) begin
for (k = 0; k < WIDTH; k = k + 1) begin
debounce_reg[k] <= {debounce_reg[k][N-2:0], in[k]};
end
end
for (k = 0; k < WIDTH; k = k + 1) begin
if (|debounce_reg[k] == 0) begin
state[k] <= 0;
end else if (&debounce_reg[k] == 1) begin
state[k] <= 1;
end else begin
state[k] <= state[k];
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, i, cnt; string s; map<int, pair<int, int> > mapp; cin >> n; cin >> s; cnt = 0; int maxm = 0; for (i = 0; i < n; i++) { if (s[i] == 0 ) cnt--; else cnt++; if (mapp.find(cnt) == mapp.end()) { mapp[cnt].first = i; mapp[cnt].second = i; } else { mapp[cnt].second = i; int len = mapp[cnt].second - mapp[cnt].first; if (len > maxm) maxm = len; } } if (mapp.find(0) != mapp.end()) maxm = max(maxm, mapp[0].second + 1); cout << maxm << endl; } |
#include <bits/stdc++.h> using namespace std; int FuN(long long n) { string s; while (n != 0) { int ch = (n % 2); s += ch + 0 ; n /= 2; } int x = -1; for (int i = 0; i < s.size(); i++) { if (s[i] == 1 ) x = i + 1; } return x; } int main() { int t, n, i, j; t = 1; cin >> t; while (t--) { long long ans = 0, fg = 1, a[200005], cnt = 0, x; cin >> n; map<long long, long long> m; for (i = 1; i <= n; i++) { cin >> a[i]; x = FuN(a[i]); m[x]++; } for (auto it : m) { ans += (it.second * (it.second - 1)) / 2; } cout << ans << endl; } return 0; } |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// Transmit HDMI, video dma data in, hdmi separate syncs data out.
module axi_hdmi_tx_vdma (
// hdmi interface
hdmi_fs_toggle,
hdmi_raddr_g,
// vdma interface
vdma_clk,
vdma_rst,
vdma_fs,
vdma_fs_ret,
vdma_valid,
vdma_data,
vdma_ready,
vdma_wr,
vdma_waddr,
vdma_wdata,
vdma_fs_ret_toggle,
vdma_fs_waddr,
vdma_tpm_oos,
vdma_ovf,
vdma_unf);
// parameters
localparam BUF_THRESHOLD_LO = 9'd3;
localparam BUF_THRESHOLD_HI = 9'd509;
localparam RDY_THRESHOLD_LO = 9'd450;
localparam RDY_THRESHOLD_HI = 9'd500;
// hdmi interface
input hdmi_fs_toggle;
input [ 8:0] hdmi_raddr_g;
// vdma interface
input vdma_clk;
input vdma_rst;
output vdma_fs;
input vdma_fs_ret;
input vdma_valid;
input [63:0] vdma_data;
output vdma_ready;
output vdma_wr;
output [ 8:0] vdma_waddr;
output [47:0] vdma_wdata;
output vdma_fs_ret_toggle;
output [ 8:0] vdma_fs_waddr;
output vdma_tpm_oos;
output vdma_ovf;
output vdma_unf;
// internal registers
reg vdma_fs_toggle_m1 = 'd0;
reg vdma_fs_toggle_m2 = 'd0;
reg vdma_fs_toggle_m3 = 'd0;
reg vdma_fs = 'd0;
reg [ 8:0] vdma_fs_waddr = 'd0;
reg vdma_fs_ret_toggle = 'd0;
reg vdma_wr = 'd0;
reg [ 8:0] vdma_waddr = 'd0;
reg [47:0] vdma_wdata = 'd0;
reg [22:0] vdma_tpm_data = 'd0;
reg vdma_tpm_oos = 'd0;
reg [ 8:0] vdma_raddr_g_m1 = 'd0;
reg [ 8:0] vdma_raddr_g_m2 = 'd0;
reg [ 8:0] vdma_raddr = 'd0;
reg [ 8:0] vdma_addr_diff = 'd0;
reg vdma_ready = 'd0;
reg vdma_almost_full = 'd0;
reg vdma_almost_empty = 'd0;
reg vdma_ovf = 'd0;
reg vdma_unf = 'd0;
// internal wires
wire [47:0] vdma_tpm_data_s;
wire vdma_tpm_oos_s;
wire [ 9:0] vdma_addr_diff_s;
wire vdma_ovf_s;
wire vdma_unf_s;
// grey to binary conversion
function [8:0] g2b;
input [8:0] g;
reg [8:0] b;
begin
b[8] = g[8];
b[7] = b[8] ^ g[7];
b[6] = b[7] ^ g[6];
b[5] = b[6] ^ g[5];
b[4] = b[5] ^ g[4];
b[3] = b[4] ^ g[3];
b[2] = b[3] ^ g[2];
b[1] = b[2] ^ g[1];
b[0] = b[1] ^ g[0];
g2b = b;
end
endfunction
// get fs from hdmi side, return fs and sof write address back
always @(posedge vdma_clk) begin
if (vdma_rst == 1'b1) begin
vdma_fs_toggle_m1 <= 'd0;
vdma_fs_toggle_m2 <= 'd0;
vdma_fs_toggle_m3 <= 'd0;
end else begin
vdma_fs_toggle_m1 <= hdmi_fs_toggle;
vdma_fs_toggle_m2 <= vdma_fs_toggle_m1;
vdma_fs_toggle_m3 <= vdma_fs_toggle_m2;
end
vdma_fs <= vdma_fs_toggle_m2 ^ vdma_fs_toggle_m3;
if (vdma_fs_ret == 1'b1) begin
vdma_fs_waddr <= vdma_waddr;
vdma_fs_ret_toggle <= ~vdma_fs_ret_toggle;
end
end
// vdma write
always @(posedge vdma_clk) begin
vdma_wr <= vdma_valid & vdma_ready;
if (vdma_rst == 1'b1) begin
vdma_waddr <= 9'd0;
end else if (vdma_wr == 1'b1) begin
vdma_waddr <= vdma_waddr + 1'b1;
end
vdma_wdata <= {vdma_data[55:32], vdma_data[23:0]};
end
// test error conditions
assign vdma_tpm_data_s = {vdma_tpm_data, 1'b1, vdma_tpm_data, 1'b0};
assign vdma_tpm_oos_s = (vdma_wdata == vdma_tpm_data_s) ? 1'b0 : vdma_wr;
always @(posedge vdma_clk) begin
if ((vdma_rst == 1'b1) || (vdma_fs_ret == 1'b1)) begin
vdma_tpm_data <= 23'd0;
vdma_tpm_oos <= 1'd0;
end else if (vdma_wr == 1'b1) begin
vdma_tpm_data <= vdma_tpm_data + 1'b1;
vdma_tpm_oos <= vdma_tpm_oos_s;
end
end
// overflow or underflow status
assign vdma_addr_diff_s = {1'b1, vdma_waddr} - vdma_raddr;
assign vdma_ovf_s = (vdma_addr_diff < BUF_THRESHOLD_LO) ? vdma_almost_full : 1'b0;
assign vdma_unf_s = (vdma_addr_diff > BUF_THRESHOLD_HI) ? vdma_almost_empty : 1'b0;
always @(posedge vdma_clk) begin
if (vdma_rst == 1'b1) begin
vdma_raddr_g_m1 <= 9'd0;
vdma_raddr_g_m2 <= 9'd0;
end else begin
vdma_raddr_g_m1 <= hdmi_raddr_g;
vdma_raddr_g_m2 <= vdma_raddr_g_m1;
end
vdma_raddr <= g2b(vdma_raddr_g_m2);
vdma_addr_diff <= vdma_addr_diff_s[8:0];
if (vdma_addr_diff >= RDY_THRESHOLD_HI) begin
vdma_ready <= 1'b0;
end else if (vdma_addr_diff <= RDY_THRESHOLD_LO) begin
vdma_ready <= 1'b1;
end
if (vdma_addr_diff > BUF_THRESHOLD_HI) begin
vdma_almost_full <= 1'b1;
end else begin
vdma_almost_full <= 1'b0;
end
if (vdma_addr_diff < BUF_THRESHOLD_LO) begin
vdma_almost_empty <= 1'b1;
end else begin
vdma_almost_empty <= 1'b0;
end
vdma_ovf <= vdma_ovf_s;
vdma_unf <= vdma_unf_s;
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; const int neginf = 0xc0c0c0c0; const int mod = 1000000007; bool cmp(const double& a, const double& b, const double TOL = 1e-9) { return (a + TOL > b) ? (b + TOL > a) ? 0 : 1 : -1; } long long powmod(long long a, long long b) { long long res = 1; a %= mod; assert(b >= 0); for (; b; b >>= 1) { if (b & 1) res = (res * a) % mod; a = (a * a) % mod; } return res; } int n, A, B, C, T; int main() { cin >> n >> A >> B >> C >> T; vector<int> msg(n); for (int(i) = (0); (i) < (n); ++(i)) cin >> msg[i]; sort((msg).begin(), (msg).end()); int last = msg.back(); long long best = 0; for (int v : msg) { int gain; if (C > B) { gain = A + (T - v) * (C - B); } else gain = A; best += gain; } cout << best << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int T; cin >> T; for (int t = 0; t < T; t++) { int n; cin >> n; int a[n], b[n]; for (int i = 0; i < n; i++) { cin >> a[i]; } for (int i = 0; i < n; i++) { cin >> b[i]; } int difference = 0; bool used = false, possible = true; for (int i = 0; i < n; i++) { if (a[i] > b[i]) { possible = false; break; } else if (a[i] == b[i]) { continue; } else { if (used) { possible = false; break; } difference = b[i] - a[i]; while (i < n) { if (b[i] - a[i] == difference) { i++; continue; } if (b[i] == a[i]) { used = true; break; } if (b[i] - a[i] != difference) { possible = false; break; } } } } if (possible) cout << YES n ; else cout << NO n ; } } |
/* Made by brandon for brandon.
* I guarantee absolutely nothing and am not liable for any damages.
*/
//=======================================================
// This code is generated by Terasic System Builder
//=======================================================
module DE0_Nano(
//////////// CLOCK //////////
CLOCK_50,
//////////// LED //////////
LED,
//////////// KEY //////////
KEY,
//////////// SW //////////
SW,
//////////// SDRAM //////////
DRAM_ADDR,
DRAM_BA,
DRAM_CAS_N,
DRAM_CKE,
DRAM_CLK,
DRAM_CS_N,
DRAM_DQ,
DRAM_DQM,
DRAM_RAS_N,
DRAM_WE_N,
// //////////// EPCS //////////
// EPCS_ASDO,
// EPCS_DATA0,
// EPCS_DCLK,
// EPCS_NCSO,
//////////// Accelerometer and EEPROM //////////
G_SENSOR_CS_N,
G_SENSOR_INT,
I2C_SCLK,
I2C_SDAT,
//////////// ADC //////////
ADC_CS_N,
ADC_SADDR,
ADC_SCLK,
ADC_SDAT,
//////////// 2x13 GPIO Header //////////
GPIO_2,
GPIO_2_IN,
//////////// GPIO_0, GPIO_0 connect to GPIO Default //////////
GPIO_0,
GPIO_0_IN,
//////////// GPIO_1, GPIO_1 connect to GPIO Default //////////
GPIO_1,
GPIO_1_IN
);
//=======================================================
// PARAMETER declarations
//=======================================================
//=======================================================
// PORT declarations
//=======================================================
//////////// CLOCK //////////
input CLOCK_50;
//////////// LED //////////
output [7:0] LED;
//////////// KEY //////////
input [1:0] KEY;
//////////// SW //////////
input [3:0] SW;
//////////// SDRAM //////////
output [12:0] DRAM_ADDR;
output [1:0] DRAM_BA;
output DRAM_CAS_N;
output DRAM_CKE;
output DRAM_CLK;
output DRAM_CS_N;
inout [15:0] DRAM_DQ;
output [1:0] DRAM_DQM;
output DRAM_RAS_N;
output DRAM_WE_N;
////////////// EPCS //////////
//output EPCS_ASDO;
//input EPCS_DATA0;
//output EPCS_DCLK;
//output EPCS_NCSO;
//////////// Accelerometer and EEPROM //////////
output G_SENSOR_CS_N;
input G_SENSOR_INT;
output I2C_SCLK;
inout I2C_SDAT;
//////////// ADC //////////
output ADC_CS_N;
output ADC_SADDR;
output ADC_SCLK;
input ADC_SDAT;
//////////// 2x13 GPIO Header //////////
inout [12:0] GPIO_2;
input [2:0] GPIO_2_IN;
//////////// GPIO_0, GPIO_0 connect to GPIO Default //////////
inout [33:0] GPIO_0;
input [1:0] GPIO_0_IN;
//////////// GPIO_1, GPIO_1 connect to GPIO Default //////////
inout [33:0] GPIO_1;
input [1:0] GPIO_1_IN;
//=======================================================
// REG/WIRE declarations
//=======================================================
// Stuff about more "natural" wires. ;)
wire [3:0] seconds;
wire [3:0] tens_seconds;
wire minute_inc;
wire [3:0] minutes;
wire [3:0] tens_minutes;
wire hours_inc;
wire [3:0] hours;
wire [3:0] tens_hours;
wire days_inc;
wire AM;
wire PM;
wire seconds_tick;
wire [5:0] segment_sel;
wire [6:0] seven_segment;
// What the wires actually are...
// 7 segments!
assign GPIO_0[9] = seven_segment[6];
assign GPIO_0[11] = seven_segment[5];
assign GPIO_0[13] = seven_segment[4];
assign GPIO_0[15] = seven_segment[3];
assign GPIO_0[17] = seven_segment[2];
assign GPIO_0[19] = seven_segment[1];
assign GPIO_0[21] = seven_segment[0];
// segment select lines!
assign GPIO_0[8] = segment_sel[5];
assign GPIO_0[10] = segment_sel[4];
assign GPIO_0[12] = segment_sel[3];
assign GPIO_0[14] = segment_sel[2];
assign GPIO_0[16] = segment_sel[1];
assign GPIO_0[18] = segment_sel[0];
assign LED[0] = seconds_tick;
// Registers
reg [12:0] count_div;
//=======================================================
// Structural coding
//=======================================================
always @ (posedge CLOCK_50)
count_div <= count_div + 1;
divide_by_50M u1(CLOCK_50, seconds_tick);
count_seconds u2 (
,
seconds_tick,
seconds[3:0],
tens_seconds[3:0],
minute_inc
);
count_minutes u3 (
!KEY[0],
minute_inc,
minutes[3:0],
tens_minutes[3:0],
hours_inc
);
count_hours u5(
SW[0],
!KEY[1],
hours_inc,
hours[3:0],
tens_hours[3:0],
LED[7],
LED[6],
days_inc
);
clock_display u6(
count_div[12],
tens_hours[3:0],
hours[3:0],
tens_minutes[3:0],
minutes[3:0],
tens_seconds[3:0],
seconds[3:0],
segment_sel[5:0],
seven_segment[6:0]
);
endmodule
|
module test_RegWaitRW32(
//Avalon System control signal.
input rsi_MRST_reset, // reset_n from MCU GPIO
input csi_MCLK_clk,
//Avalon-MM Control.
input [31:0] avs_test_writedata,
output [31:0] avs_test_readdata,
input [5:0] avs_test_address,
input [3:0] avs_test_byteenable,
input avs_test_write,
input avs_test_read,
output avs_test_readdatavalid,
output avs_test_waitrequest
);
reg [31:0] out_data = 0;
reg [31:0] r_data = 0;
reg r_wait = 0;
reg [3:0] r_wait_cnt = 0;
reg r_valid = 0;
assign avs_test_readdata = out_data;
assign avs_test_waitrequest = r_wait;
assign avs_test_readdatavalid = r_valid;
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
out_data <= 0;
r_data <= 0;
r_wait <= 0;
r_wait_cnt <= 0;
r_valid <= 0;
end
else begin
if(r_wait_cnt == 15) r_valid <= 1; else r_valid <= 0;
if(((r_wait_cnt > 0)&&(r_wait_cnt < 15))||(avs_test_read)||(avs_test_write)) r_wait <= 1; else r_wait <= 0;
if(avs_test_read) begin
r_wait_cnt <= r_wait_cnt + 1;
out_data <= r_data + avs_test_address;
end
else if(avs_test_write) begin
r_wait_cnt <= r_wait_cnt + 1;
case(avs_test_address)
0: begin
if(avs_test_byteenable[3]) r_data[31:24] <= avs_test_writedata[31:24];
if(avs_test_byteenable[2]) r_data[23:16] <= avs_test_writedata[23:16];
if(avs_test_byteenable[1]) r_data[15:8] <= avs_test_writedata[15:8];
if(avs_test_byteenable[0]) r_data[7:0] <= avs_test_writedata[7:0];
end
1: begin
if(avs_test_byteenable[3]) r_data[31:24] <= ~avs_test_writedata[31:24];
if(avs_test_byteenable[2]) r_data[23:16] <= ~avs_test_writedata[23:16];
if(avs_test_byteenable[1]) r_data[15:8] <= ~avs_test_writedata[15:8];
if(avs_test_byteenable[0]) r_data[7:0] <= ~avs_test_writedata[7:0];
end
default: begin
r_data <= 0;
end
endcase
end
else begin
if(r_wait_cnt > 0) r_wait_cnt <= r_wait_cnt + 1; else r_wait_cnt <= 0;
end
end
end
endmodule
|
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.2 (win64) Build Thu Jun 14 20:03:12 MDT 2018
// Date : Tue Sep 17 19:45:28 2019
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub
// d:/github/Digital-Hardware-Modelling/xilinx-vivado/gcd_snickerdoodle/gcd_snickerdoodle.srcs/sources_1/bd/gcd_zynq_snick/ip/gcd_zynq_snick_auto_pc_0/gcd_zynq_snick_auto_pc_0_stub.v
// Design : gcd_zynq_snick_auto_pc_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg400-3
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_protocol_converter_v2_1_17_axi_protocol_converter,Vivado 2018.2" *)
module gcd_zynq_snick_auto_pc_0(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wid, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awprot, m_axi_awvalid,
m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid, m_axi_wready, m_axi_bresp,
m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot, m_axi_arvalid, m_axi_arready,
m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready" */;
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [3:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [3:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [31:0]m_axi_awaddr;
output [2:0]m_axi_awprot;
output m_axi_awvalid;
input m_axi_awready;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wvalid;
input m_axi_wready;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [31:0]m_axi_araddr;
output [2:0]m_axi_arprot;
output m_axi_arvalid;
input m_axi_arready;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sctag_pcx_rptr_2.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module sctag_pcx_rptr_2 (/*AUTOARG*/
// Outputs
sig_buf,
// Inputs
sig
);
// this repeater has 164 bits
output [163:0] sig_buf;
input [163:0] sig;
assign sig_buf = sig;
//output pcx_sctag_data_rdy_px1_buf;
//output [`PCX_WIDTH-1:0] pcx_sctag_data_px2_buf; // pcx to sctag packet
//output pcx_sctag_atm_px1_buf; // indicates that the current packet is atm with the next
//output sctag_pcx_stall_pq_buf;
//input pcx_sctag_data_rdy_px1;
//input [`PCX_WIDTH-1:0] pcx_sctag_data_px2; // pcx to sctag packet
//input pcx_sctag_atm_px1; // indicates that the current packet is atm with the next
//input sctag_pcx_stall_pq;
//assign pcx_sctag_data_rdy_px1_buf = pcx_sctag_data_rdy_px1;
//assign pcx_sctag_data_px2_buf = pcx_sctag_data_px2;
//assign pcx_sctag_atm_px1_buf = pcx_sctag_atm_px1;
//assign sctag_pcx_stall_pq_buf = sctag_pcx_stall_pq;
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> primes; int dp[101][1 << 18], n, a[111], man, ansd[111], loc[100]; vector<int> fact[100]; int rec(int i, int mask) { if (i == n) return 0; if (dp[i][mask] != 1000000000) return dp[i][mask]; int dif = abs(a[i] - 1); int ans = rec(i + 1, mask) + dif; for (int j = 2; j <= 60; j++) { int k; for (k = 0; k < fact[j].size(); k++) if (mask & (1 << fact[j][k])) break; if (k != (int)fact[j].size()) continue; int d = abs(a[i] - j); if (d <= dif) { int msk = mask; for (k = 0; k < fact[j].size(); k++) msk = msk | (1 << fact[j][k]); ans = min(ans, rec(i + 1, msk) + d); } } return dp[i][mask] = ans; } void reccons(int i, int mask, int m) { if (i == n) return; int dif = abs(a[i] - 1); if (rec(i + 1, mask) == m - dif) { ansd[i] = 1; reccons(i + 1, mask, m - dif); return; } for (int j = 2; j <= 60; j++) { int k; for (k = 0; k < fact[j].size(); k++) if (mask & (1 << fact[j][k])) break; if (k != (int)fact[j].size()) continue; int d = abs(a[i] - j); if (d > dif) continue; int msk = mask; for (k = 0; k < fact[j].size(); k++) msk = msk | (1 << fact[j][k]); if (rec(i + 1, msk) == m - d) { ansd[i] = j; reccons(i + 1, msk, m - d); return; } } } int main() { int i, j, t; for (i = 2; i <= 60; i++) { for (j = 2; j < i; j++) if (i % j == 0) break; if (j == i) primes.push_back(i); } for (i = 0; i < 17; i++) loc[primes[i]] = i; for (i = 2; i <= 60; i++) { for (j = 0; j < 17; j++) if (i % primes[j] == 0) fact[i].push_back(j); } scanf( %d , &n); for (i = 0; i < n; i++) scanf( %d , &a[i]); for (i = 0; i <= n; i++) for (j = 0; j < (1 << 17); j++) dp[i][j] = 1000000000; man = rec(0, 0); reccons(0, 0, man); for (i = 0; i < n; i++) printf( %d , ansd[i]); printf( n ); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long M = 998244353; long long power(long long a, long long b, long long m) { long long res = 1; a %= m; while (b) { if (b & 1LL) res = res * a % m; a = a * a % m; b >>= 1; } return res; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long n, m, k; cin >> n >> m >> k; m = power(m, M - 2, M); vector<vector<long long>> dp(k + 1, vector<long long>(k + 1, 0)); for (long long i = 0; i <= k; ++i) { for (long long j = 0; j <= k; ++j) { long long N = n - k + i, K = j; if (N <= 0 || K == 0) { dp[i][j] = 0; continue; } if (K == 1) { dp[i][j] = N * m % M; continue; } if (i > 0) dp[i][j] = (dp[i][j - 1] - dp[i - 1][j - 1] * (1 - m + M) % M + M) % M * N % M; } } cout << dp[k][k] << endl; return 0; } |
//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 3.7
// \ \ Application : MIG
// / / Filename : round_robin_arb.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : Virtex-6
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// A simple round robin arbiter implemented in a not so simple
// way. Two things make this special. First, it takes width as
// a parameter and secondly it's constructed in a way to work with
// restrictions synthesis programs.
//
// Consider each req/grant pair to be a
// "channel". The arbiter computes a grant response to a request
// on a channel by channel basis.
//
// The arbiter implementes a "round robin" algorithm. Ie, the granting
// process is totally fair and symmetric. Each requester is given
// equal priority. If all requests are asserted, the arbiter will
// work sequentially around the list of requesters, giving each a grant.
//
// Grant priority is based on the "last_master". The last_master
// vector stores the channel receiving the most recent grant. The
// next higher numbered channel (wrapping around to zero) has highest
// priority in subsequent cycles. Relative priority wraps around
// the request vector with the last_master channel having lowest priority.
//
// At the highest implementation level, a per channel inhibit signal is computed.
// This inhibit is bit-wise AND'ed with the incoming requests to
// generate the grant.
//
// There will be at most a single grant per state. The logic
// of the arbiter depends on this.
//
// Once a grant is given, it is stored as the last_master. The
// last_master vector is initialized at reset to the zero'th channel.
// Although the particular channel doesn't matter, it does matter
// that the last_master contains a valid grant pattern.
//
// The heavy lifting is in computing the per channel inhibit signals.
// This is accomplished in the generate statement.
//
// The first "for" loop in the generate statement steps through the channels.
//
// The second "for" loop steps through the last mast_master vector
// for each channel. For each last_master bit, an inh_group is generated.
// Following the end of the second "for" loop, the inh_group signals are OR'ed
// together to generate the overall inhibit bit for the channel.
//
// For a four bit wide arbiter, this is what's generated for channel zero:
//
// inh_group[1] = last_master[0] && |req[3:1]; // any other req inhibits
// inh_group[2] = last_master[1] && |req[3:2]; // req[3], or req[2] inhibit
// inh_group[3] = last_master[2] && |req[3:3]; // only req[3] inhibits
//
// For req[0], last_master[3] is ignored because channel zero is highest priority
// if last_master[3] is true.
//
`timescale 1ps/1ps
module round_robin_arb
#(
parameter TCQ = 100,
parameter WIDTH = 3
)
(
/*AUTOARG*/
// Outputs
grant_ns, grant_r,
// Inputs
clk, rst, req, disable_grant, current_master, upd_last_master
);
input clk;
input rst;
input [WIDTH-1:0] req;
wire [WIDTH-1:0] last_master_ns;
reg [WIDTH*2-1:0] dbl_last_master_ns;
always @(/*AS*/last_master_ns)
dbl_last_master_ns = {last_master_ns, last_master_ns};
reg [WIDTH*2-1:0] dbl_req;
always @(/*AS*/req) dbl_req = {req, req};
reg [WIDTH-1:0] inhibit = {WIDTH{1'b0}};
genvar i;
genvar j;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : channel
wire [WIDTH-1:1] inh_group;
for (j = 0; j < (WIDTH-1); j = j + 1) begin : last_master
assign inh_group[j+1] =
dbl_last_master_ns[i+j] && |dbl_req[i+WIDTH-1:i+j+1];
end
always @(/*AS*/inh_group) inhibit[i] = |inh_group;
end
endgenerate
input disable_grant;
output wire [WIDTH-1:0] grant_ns;
assign grant_ns = req & ~inhibit & {WIDTH{~disable_grant}};
output reg [WIDTH-1:0] grant_r;
always @(posedge clk) grant_r <= #TCQ grant_ns;
input [WIDTH-1:0] current_master;
input upd_last_master;
reg [WIDTH-1:0] last_master_r;
localparam ONE = 1 << (WIDTH - 1); //Changed form '1' to fix the CR #544024
//A '1' in the LSB of the last_master_r
//signal gives a low priority to req[0]
//after reset. To avoid this made MSB as
//'1' at reset.
assign last_master_ns = rst
? ONE[0+:WIDTH]
: upd_last_master
? current_master
: last_master_r;
always @(posedge clk) last_master_r <= #TCQ last_master_ns;
`ifdef MC_SVA
grant_is_one_hot_zero:
assert property (@(posedge clk) (rst || $onehot0(grant_ns)));
last_master_r_is_one_hot:
assert property (@(posedge clk) (rst || $onehot(last_master_r)));
`endif
endmodule
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/16.1/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
// $Revision: #1 $
// $Date: 2016/08/07 $
// $Author: swbranch $
// -----------------------------------------------
// Reset Synchronizer
// -----------------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_synchronizer
#(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
)
(
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register chain. We cannot reuse the
// standard synchronizer in this implementation
// because our timing constraints are different.
//
// Instead of cutting the timing path to the d-input
// on the first flop we need to cut the aclr input.
//
// We omit the "preserve" attribute on the final
// output register, so that the synthesis tool can
// duplicate it where needed.
// -----------------------------------------------
(*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
reg altera_reset_synchronizer_int_chain_out;
generate if (ASYNC_RESET) begin
// -----------------------------------------------
// Assert asynchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk or posedge reset_in) begin
if (reset_in) begin
altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
altera_reset_synchronizer_int_chain_out <= 1'b1;
end
else begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end else begin
// -----------------------------------------------
// Assert synchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk) begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast,no-stack-protector,unroll-loops ) #pragma GCC optimize( no-stack-protector,fast-math ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,tune=native ) using namespace std; template <class S, class T> inline S smax(S &l, T r) { return l = max(l, (S)r); } template <class S, class T> inline S smin(S &l, T r) { return l = min(l, (S)r); } const int N = 1e6 + 10; int nex[N][26], sz, cnt[N], lvl[N]; inline void In(string &s) { int now = 0; for (auto c : s) { c -= a ; if (!nex[now][c]) { nex[now][c] = ++sz; lvl[sz] = lvl[now] + 1; } now = nex[now][c]; } cnt[now]++; } vector<int> dp[N]; inline int f(int i) { return i * (i - 1) / 2; } inline void merge(int v, int u) { vector<int> tmp(dp[v].size() + dp[u].size() - 1); for (int i = 0; i < (int)dp[v].size(); i++) for (int j = 0; j < (int)dp[u].size(); j++) tmp[i + j] = max(tmp[i + j], dp[v][i] + dp[u][j] + i * j * lvl[v]); dp[v] = tmp; } void dfs(int v) { for (int i = 0; i <= cnt[v]; i++) dp[v].emplace_back(lvl[v] * f(i)); for (int i = 0; i < 26; i++) if (nex[v][i]) { dfs(nex[v][i]); merge(v, nex[v][i]); } } int32_t main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); int n, k; cin >> n >> k; for (int i = 0; i < n; ++i) { string s; cin >> s; In(s); } dfs(0); cout << dp[0][k] << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A32O_2_V
`define SKY130_FD_SC_MS__A32O_2_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog wrapper for a32o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a32o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a32o_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a32o_2 (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A32O_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV5SD3_BLACKBOX_V
`define SKY130_FD_SC_HS__CLKDLYINV5SD3_BLACKBOX_V
/**
* clkdlyinv5sd3: Clock Delay Inverter 5-stage 0.50um length inner
* stage gate.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__clkdlyinv5sd3 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV5SD3_BLACKBOX_V
|
/*
* This module is dual port ram with 2 I/O ports
* this ram can read / write data to ports 0 and 1 simulataniously
*
* Author: Kimi
*/
`ifndef _dp_ram_duo
`define _dp_ram_duo
`timescale 1ns /1ps
////////////////////////////////////////////
// start of behavioral RAM implemintation //
////////////////////////////////////////////
module dp_ram_duo #(parameter add_wd=4, data_wd=32,depth=16)
(
input wire clk, cs, rst, rd0, rd1, wr0, wr1,
input wire [add_wd-1:0] rd_add0, wr_add0,
input wire [add_wd-1:0] rd_add1, wr_add1,
input wire [data_wd-1:0] wr_data0, wr_data1,
output reg [data_wd-1:0] rd_data0, rd_data1
);
reg [data_wd-1:0] ram [0:depth-1];
always @(posedge clk) begin
///////////////////
// READ COMMANDS //
///////////////////
if (cs && rd0) begin // port 0
// rd_data0 <= #1 {data_wd{1'bx}};
rd_data0 <= #5 ram[rd_add0];
end
if (cs && rd1) begin // port 1
// rd_data1 <= #1 {data_wd{1'bx}};
rd_data1 <= #5 ram[rd_add1];
end
////////////////////
// WRITE COMMANDS //
////////////////////
if (cs && wr0) // port 0
ram[wr_add0] <= #1 wr_data0;
if (cs && wr1) // port 1
ram[wr_add1] <= #1 wr_data1;
end
endmodule
//////////////////////////////////////////
// end of behavioral RAM implemintation //
//////////////////////////////////////////
`endif |
#include<iostream> #include<vector> #include<queue> #include<cstring> #include<cmath> #include<map> #include<set> #include<cstdio> #include<algorithm> #define debug(a) cout<<#a<< = <<a<<endl; using namespace std; const int maxn=1e3+100; typedef long long LL; LL a[maxn]; int main(void) { cin.tie(0);std::ios::sync_with_stdio(false); LL n;cin>>n; if(n==1){ cout<<4<<endl; } else{ if(n&1) cout<<(1+ ( (3*n*(n+4)+2)+ ( (n+4)*n+2 ) )/8 )<<endl; else cout<<(1+ ( (3*n*(n+4)+2)- ( (n+4)*n+2 ) )/8 )<<endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int32_t main() { long long q; cin >> q; for (long long i = 0; i < q; i++) { long long a, b, c; cin >> a >> b >> c; long long ans = 0; long long num = min(min(a, b), c); ans += num; a -= num; b -= num; c -= num; if (a > b) { swap(a, b); } num = min(a, (a + b) / 3); ans += num; cout << ans << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long K, A, B, V; cin >> K >> A >> B >> V; long long nuts = A; long long divisors = B; long long capacity = V; long long maxSections = K; int boxes = 0; while (nuts > 0) { boxes++; int sections = min(divisors + 1, maxSections); nuts -= sections * capacity; divisors -= sections - 1; } cout << boxes; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { long long n, k; cin >> n; vector<long long> dp(n + 3, 0); vector<long long> v; long long sum = 0; for (int j = 0; j < n; j++) { cin >> k; if (j % 2 == 0) { sum = sum + k; } v.push_back(k); } dp[0] = 0; long long ans = 0; long long z = 0; if (n > 1) { dp[1] = max(z, v[1] - v[0]); ans = max(ans, dp[1]); } k = 2; for (int j = 1; j < n - 1; j++) { if (j % 2 == 0) { dp[k] = max(z, dp[k - 2] + (v[j + 1] - v[j])); } else { dp[k] = max(z, dp[k - 2] + (v[j] - v[j + 1])); } ans = max(ans, dp[k]); k++; } cout << sum + ans << endl; } } |
#include <bits/stdc++.h> using namespace std; int main() { long long int t, n; cin >> t; while (t--) { cin >> n; long long int c = 0; string s = ; cin >> s; string h = s; sort(h.begin(), h.end()); for (int j = 0; j < n; j++) if (h.at(j) != s.at(j)) c++; cout << c << endl; } return 0; } |
/*
* Copyright (c) 1998-2000 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* Test some subtleties of bitwise and and if condition expressions.
*/
module test;
reg [31:0] c;
initial begin
c = 13;
if (c & 4)
begin
$display("PASSED");
$finish;
end
$display("FAILED");
end
endmodule
|
module example;
reg [7:0] vec;
reg [3:0] ix;
wire vix = vec[ix];
initial begin
$display( " time ix vix vec" );
$display( " ---- ---- --- --------" );
$monitor( "%T %b %b %b", $time, ix, vix, vec );
vec = 8'b00000000;
ix = 0; // 0
#100 ix = 1; // 100
#100 ix = 2; // 200
#100 ix = 3; // 300
#100 ix = 4; // 400
#100 ix = 5; // 500
#100 ix = 6; // 600
#100 ix = 7; // 700
#100 ix = 8; // 800
#100 ix = 4'b001x; // 900
#100 ix = 4'b01x0; // 1000
#100 ix = 4'b0x01; // 1100
#100 ix = 0; // 1200
#100 vec[ix] = 1'b1; // 1300
#100 vec[ix] = 1'b0; // 1400
#100 ix = 3; // 1500
#100 vec[ix] = 1'b1; // 1600
#100 vec[ix] = 1'b0; // 1700
#100 ix = 6; // 1800
#100 vec[ix] = 1'b1; // 1900
#100 vec[ix] = 1'b0; // 2000
#100 ix = 8; // 2100
#100 vec[ix] = 1'b1; // 2200
#100 vec[ix] = 1'b0; // 2300
#100 ix = 4'b010x; // 2400
#100 vec[ix] = 1'b1; // 2500
#100 vec[ix] = 1'b0; // 2600
#100 ix = 4'b00x1; // 2700
#100 vec[ix] = 1'b1; // 2800
#100 vec[ix] = 1'b0; // 2900
#100 ix = 4'b0x10; // 3000
#100 vec[ix] = 1'b1; // 3100
#100 vec[ix] = 1'b0; // 3200
#100 ix = 4'bxxxx; // 3300
#100 vec[ix] = 1'b1; // 3400
#100 vec[ix] = 1'b0; // 3500
#100 $display( "Finish at time %T", $time );
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND3B_BLACKBOX_V
`define SKY130_FD_SC_MS__AND3B_BLACKBOX_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__and3b (
X ,
A_N,
B ,
C
);
output X ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND3B_BLACKBOX_V
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: Digilent:digilent:axi_dispctrl:1.0
// IP Revision: 9
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module block_design_axi_dispctrl_0_0 (
REF_CLK_I,
PXL_CLK_O,
PXL_CLK_5X_O,
LOCKED_O,
FSYNC_O,
HSYNC_O,
VSYNC_O,
DE_O,
RED_O,
GREEN_O,
BLUE_O,
DEBUG_O,
s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
s_axis_mm2s_aclk,
s_axis_mm2s_aresetn,
s_axis_mm2s_tready,
s_axis_mm2s_tdata,
s_axis_mm2s_tstrb,
s_axis_mm2s_tlast,
s_axis_mm2s_tvalid
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 REF_CLK_I CLK" *)
input wire REF_CLK_I;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 PXL_CLK_O CLK" *)
output wire PXL_CLK_O;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 PXL_CLK_5X_O CLK" *)
output wire PXL_CLK_5X_O;
output wire LOCKED_O;
output wire FSYNC_O;
output wire HSYNC_O;
output wire VSYNC_O;
output wire DE_O;
output wire [4 : 0] RED_O;
output wire [5 : 0] GREEN_O;
output wire [4 : 0] BLUE_O;
output wire [31 : 0] DEBUG_O;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S_AXI_CLK CLK" *)
input wire s_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S_AXI_RST RST" *)
input wire s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [5 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [5 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S_AXIS_MM2S_CLK CLK" *)
input wire s_axis_mm2s_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S_AXIS_MM2S_RST RST" *)
input wire s_axis_mm2s_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_MM2S TREADY" *)
output wire s_axis_mm2s_tready;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_MM2S TDATA" *)
input wire [31 : 0] s_axis_mm2s_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_MM2S TSTRB" *)
input wire [3 : 0] s_axis_mm2s_tstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_MM2S TLAST" *)
input wire s_axis_mm2s_tlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_MM2S TVALID" *)
input wire s_axis_mm2s_tvalid;
axi_dispctrl_v1_0 #(
.C_USE_BUFR_DIV5(0),
.C_RED_WIDTH(5),
.C_GREEN_WIDTH(6),
.C_BLUE_WIDTH(5),
.C_S_AXI_DATA_WIDTH(32),
.C_S_AXI_ADDR_WIDTH(6),
.C_S_AXIS_MM2S_TDATA_WIDTH(32)
) inst (
.REF_CLK_I(REF_CLK_I),
.PXL_CLK_O(PXL_CLK_O),
.PXL_CLK_5X_O(PXL_CLK_5X_O),
.LOCKED_O(LOCKED_O),
.FSYNC_O(FSYNC_O),
.HSYNC_O(HSYNC_O),
.VSYNC_O(VSYNC_O),
.DE_O(DE_O),
.RED_O(RED_O),
.GREEN_O(GREEN_O),
.BLUE_O(BLUE_O),
.DEBUG_O(DEBUG_O),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awprot(s_axi_awprot),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_araddr(s_axi_araddr),
.s_axi_arprot(s_axi_arprot),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.s_axis_mm2s_aclk(s_axis_mm2s_aclk),
.s_axis_mm2s_aresetn(s_axis_mm2s_aresetn),
.s_axis_mm2s_tready(s_axis_mm2s_tready),
.s_axis_mm2s_tdata(s_axis_mm2s_tdata),
.s_axis_mm2s_tstrb(s_axis_mm2s_tstrb),
.s_axis_mm2s_tlast(s_axis_mm2s_tlast),
.s_axis_mm2s_tvalid(s_axis_mm2s_tvalid)
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
// verilator lint_off GENCLK
reg printclk;
// verilator lint_on GENCLK
ps ps (printclk);
reg [7:0] a;
wire [7:0] z;
l1 u (~a,z);
always @ (posedge clk) begin
printclk <= 0;
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
printclk <= 1'b1;
end
if (cyc==2) begin
a <= 8'b1;
end
if (cyc==3) begin
if (z !== 8'hf8) $stop;
//if (u.u1.u1.u1.u0.PARAM !== 1) $stop;
//if (u.u1.u1.u1.u1.PARAM !== 2) $stop;
//if (u.u0.u0.u0.u0.z !== 8'hfe) $stop;
//if (u.u0.u0.u0.u1.z !== 8'hff) $stop;
//if (u.u1.u1.u1.u0.z !== 8'h00) $stop;
//if (u.u1.u1.u1.u1.z !== 8'h01) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module ps (input printclk);
// Check that %m stays correct across inlines
always @ (posedge printclk) $write("[%0t] %m: Clocked\n", $time);
endmodule
module l1 (input [7:0] a, output [7:0] z);
wire [7:0] z0; wire [7:0] z1;
assign z = z0+z1;
l2 u0 (a, z0); l2 u1 (a, z1);
endmodule
module l2 (input [7:0] a, output [7:0] z);
wire [7:0] z0; wire [7:0] z1;
assign z = z0+z1;
wire [7:0] a1 = a+8'd1;
l3 u0 (a, z0); l3 u1 (a1, z1);
endmodule
module l3 (input [7:0] a, output [7:0] z);
wire [7:0] z0; wire [7:0] z1;
assign z = z0+z1;
wire [7:0] a1 = a+8'd1;
l4 u0 (a, z0); l4 u1 (a1, z1);
endmodule
module l4 (input [7:0] a, output [7:0] z);
wire [7:0] z0; wire [7:0] z1;
assign z = z0+z1;
wire [7:0] a1 = a+8'd1;
l5 #(1) u0 (a, z0); l5 #(2) u1 (a1, z1);
endmodule
module l5 (input [7:0] a, output [7:0] z);
parameter PARAM = 5;
wire [7:0] z0; wire [7:0] z1;
assign z = a;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; string s; cin >> s; int cnt = 0; for (int i = 0; i < n; i++) { if (s[i] == + ) { cnt++; } else if (s[i] == - && cnt) { cnt--; } } cout << cnt << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { string str; cin >> str; for (int i = 1; i < str.size() - 1; i++) { if (str[i + 1] != . && str[i - 1] != . && str[i] != . ) { if (str[i + 1] != str[i - 1] && str[i - 1] != str[i] && str[i + 1] != str[i]) { cout << Yes << endl; return 0; } } } cout << No << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__XNOR2_PP_SYMBOL_V
`define SKY130_FD_SC_HS__XNOR2_PP_SYMBOL_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__xnor2 (
//# {{data|Data Signals}}
input A ,
input B ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__XNOR2_PP_SYMBOL_V
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*
* Chuck Benz, Hollis, NH Copyright (c)2002
*
* The information and description contained herein is the
* property of Chuck Benz.
*
* Permission is granted for any reuse of this information
* and description as long as this copyright notice is
* preserved. Modifications may be made as long as this
* notice is preserved.
* per Widmer and Franaszek
*/
`timescale 1ps/1ps
`default_nettype none
module decode_8b10b (datain, dispin, dataout, dispout, code_err, disp_err) ;
input wire [9:0] datain ;
input wire dispin ;
output wire [8:0] dataout ;
output wire dispout ;
output wire code_err ;
output wire disp_err ;
wire ai = datain[0] ;
wire bi = datain[1] ;
wire ci = datain[2] ;
wire di = datain[3] ;
wire ei = datain[4] ;
wire ii = datain[5] ;
wire fi = datain[6] ;
wire gi = datain[7] ;
wire hi = datain[8] ;
wire ji = datain[9] ;
wire aeqb = (ai & bi) | (!ai & !bi) ;
wire ceqd = (ci & di) | (!ci & !di) ;
wire p22 = (ai & bi & !ci & !di) |
(ci & di & !ai & !bi) |
( !aeqb & !ceqd) ;
wire p13 = ( !aeqb & !ci & !di) |
( !ceqd & !ai & !bi) ;
wire p31 = ( !aeqb & ci & di) |
( !ceqd & ai & bi) ;
wire p40 = ai & bi & ci & di ;
wire p04 = !ai & !bi & !ci & !di ;
wire disp6a = p31 | (p22 & dispin) ; // pos disp if p22 and was pos, or p31.
wire disp6a2 = p31 & dispin ; // disp is ++ after 4 bits
wire disp6a0 = p13 & ! dispin ; // -- disp after 4 bits
wire disp6b = (((ei & ii & ! disp6a0) | (disp6a & (ei | ii)) | disp6a2 |
(ei & ii & di)) & (ei | ii | di)) ;
// The 5B/6B decoding special cases where ABCDE != abcde
wire p22bceeqi = p22 & bi & ci & (ei == ii) ;
wire p22bncneeqi = p22 & !bi & !ci & (ei == ii) ;
wire p13in = p13 & !ii ;
wire p31i = p31 & ii ;
wire p13dei = p13 & di & ei & ii ;
wire p22aceeqi = p22 & ai & ci & (ei == ii) ;
wire p22ancneeqi = p22 & !ai & !ci & (ei == ii) ;
wire p13en = p13 & !ei ;
wire anbnenin = !ai & !bi & !ei & !ii ;
wire abei = ai & bi & ei & ii ;
wire cdei = ci & di & ei & ii ;
wire cndnenin = !ci & !di & !ei & !ii ;
// non-zero disparity cases:
wire p22enin = p22 & !ei & !ii ;
wire p22ei = p22 & ei & ii ;
//wire p13in = p12 & !ii ;
//wire p31i = p31 & ii ;
wire p31dnenin = p31 & !di & !ei & !ii ;
//wire p13dei = p13 & di & ei & ii ;
wire p31e = p31 & ei ;
wire compa = p22bncneeqi | p31i | p13dei | p22ancneeqi |
p13en | abei | cndnenin ;
wire compb = p22bceeqi | p31i | p13dei | p22aceeqi |
p13en | abei | cndnenin ;
wire compc = p22bceeqi | p31i | p13dei | p22ancneeqi |
p13en | anbnenin | cndnenin ;
wire compd = p22bncneeqi | p31i | p13dei | p22aceeqi |
p13en | abei | cndnenin ;
wire compe = p22bncneeqi | p13in | p13dei | p22ancneeqi |
p13en | anbnenin | cndnenin ;
wire ao = ai ^ compa ;
wire bo = bi ^ compb ;
wire co = ci ^ compc ;
wire do_ = di ^ compd ;
wire eo = ei ^ compe ;
wire feqg = (fi & gi) | (!fi & !gi) ;
wire heqj = (hi & ji) | (!hi & !ji) ;
wire fghj22 = (fi & gi & !hi & !ji) |
(!fi & !gi & hi & ji) |
( !feqg & !heqj) ;
wire fghjp13 = ( !feqg & !hi & !ji) |
( !heqj & !fi & !gi) ;
wire fghjp31 = ( (!feqg) & hi & ji) |
( !heqj & fi & gi) ;
assign dispout = (fghjp31 | (disp6b & fghj22) | (hi & ji)) & (hi | ji) ;
wire ko = ( (ci & di & ei & ii) | ( !ci & !di & !ei & !ii) |
(p13 & !ei & ii & gi & hi & ji) |
(p31 & ei & !ii & !gi & !hi & !ji)) ;
wire alt7 = (fi & !gi & !hi & // 1000 cases, where disp6b is 1
((dispin & ci & di & !ei & !ii) | ko |
(dispin & !ci & di & !ei & !ii))) |
(!fi & gi & hi & // 0111 cases, where disp6b is 0
(( !dispin & !ci & !di & ei & ii) | ko |
( !dispin & ci & !di & ei & ii))) ;
wire k28 = (ci & di & ei & ii) | ! (ci | di | ei | ii) ;
// k28 with positive disp into fghi - .1, .2, .5, and .6 special cases
wire k28p = ! (ci | di | ei | ii) ;
wire fo = (ji & !fi & (hi | !gi | k28p)) |
(fi & !ji & (!hi | gi | !k28p)) |
(k28p & gi & hi) |
(!k28p & !gi & !hi) ;
wire go = (ji & !fi & (hi | !gi | !k28p)) |
(fi & !ji & (!hi | gi |k28p)) |
(!k28p & gi & hi) |
(k28p & !gi & !hi) ;
wire ho = ((ji ^ hi) & ! ((!fi & gi & !hi & ji & !k28p) | (!fi & gi & hi & !ji & k28p) |
(fi & !gi & !hi & ji & !k28p) | (fi & !gi & hi & !ji & k28p))) |
(!fi & gi & hi & ji) | (fi & !gi & !hi & !ji) ;
wire disp6p = (p31 & (ei | ii)) | (p22 & ei & ii) ;
wire disp6n = (p13 & ! (ei & ii)) | (p22 & !ei & !ii) ;
wire disp4p = fghjp31 ;
wire disp4n = fghjp13 ;
assign code_err = p40 | p04 | (fi & gi & hi & ji) | (!fi & !gi & !hi & !ji) |
(p13 & !ei & !ii) | (p31 & ei & ii) |
(ei & ii & fi & gi & hi) | (!ei & !ii & !fi & !gi & !hi) |
(ei & !ii & gi & hi & ji) | (!ei & ii & !gi & !hi & !ji) |
(!p31 & ei & !ii & !gi & !hi & !ji) |
(!p13 & !ei & ii & gi & hi & ji) |
(((ei & ii & !gi & !hi & !ji) |
(!ei & !ii & gi & hi & ji)) &
! ((ci & di & ei) | (!ci & !di & !ei))) |
(disp6p & disp4p) | (disp6n & disp4n) |
(ai & bi & ci & !ei & !ii & ((!fi & !gi) | fghjp13)) |
(!ai & !bi & !ci & ei & ii & ((fi & gi) | fghjp31)) |
(fi & gi & !hi & !ji & disp6p) |
(!fi & !gi & hi & ji & disp6n) |
(ci & di & ei & ii & !fi & !gi & !hi) |
(!ci & !di & !ei & !ii & fi & gi & hi) ;
assign dataout = {ko, ho, go, fo, eo, do_, co, bo, ao} ;
// my disp err fires for any legal codes that violate disparity, may fire for illegal codes
assign disp_err = ((dispin & disp6p) | (disp6n & !dispin) |
(dispin & !disp6n & fi & gi) |
(dispin & ai & bi & ci) |
(dispin & !disp6n & disp4p) |
(!dispin & !disp6p & !fi & !gi) |
(!dispin & !ai & !bi & !ci) |
(!dispin & !disp6p & disp4n) |
(disp6p & disp4p) | (disp6n & disp4n)) ;
endmodule
|
#include <bits/stdc++.h> int vv[(1 << 16) + 1], ff[(1 << 16) + 1], gg[(1 << 16) + 1], bcnt[(1 << 16)]; void init() { int i; ff[0] = gg[0] = 1; for (i = 1; i <= (1 << 16); i++) { vv[i] = i == 1 ? 1 : (long long)vv[i - 998244353 % i] * (998244353 / i + 1) % 998244353; ff[i] = (long long)ff[i - 1] * i % 998244353; gg[i] = (long long)gg[i - 1] * vv[i] % 998244353; } for (i = 1; i < (1 << 16); i++) bcnt[i] = bcnt[i & i - 1] + 1; } void wht(int *aa, int h) { if (h > 0) { int n = 1 << h, m = n >> 1, i, j; wht(aa, h - 1), wht(aa + m, h - 1); for (i = 0; (j = i + m) < n; i++) { int a = aa[i], b = aa[j]; if ((aa[i] = a + b) >= 998244353) aa[i] -= 998244353; if ((aa[j] = a - b) < 0) aa[j] += 998244353; } } } int main() { static int cnt[16 + 1][1 << 4], dp[1 << 4][16 + 1][16 + 1][2][1 << 4], dq[16 + 1][2][1 << 4], dr[16 + 1][2][1 << 4], ans[16 + 1][(1 << 16)]; int n, k_, h_, d, h, a, k, l, p, k1, p1, b, t, c, base, fv; init(); scanf( %d%d%d , &n, &k_, &d); h_ = 0; while (1 << h_ < k_) h_++; fv = (long long)ff[k_] % 998244353; for (k = 0; k < k_; k++) fv = (long long)fv * vv[n] % 998244353; base = 0; while (n--) { scanf( %d , &a); base ^= a; h = h_; while (a >> h != a - k_ >> h) h++; cnt[h][a & (1 << h_) - 1]++; } for (a = 0; a < 1 << h_; a++) { dp[a][0][0][0][0] = 1; for (t = 1; t <= k_; t++) for (k = k_; k >= 0; k--) for (l = 0; l <= k; l++) for (p = 0; p < 2; p++) for (b = 0; b < 1 << h_; b++) { int x, y; if ((x = dp[a][k][l][p][b]) == 0) continue; y = 1; for (c = 1; k + c * t <= k_; c++) { int k_ = k + c * t, l_ = l + c, p_ = p ^ (a < t && c % 2 != 0), b_ = b ^ (c % 2 == 0 ? 0 : a ^ (a >= t ? a - t : a - t + (1 << h_))); y = (long long)y * gg[t] % 998244353; dp[a][k_][l_][p_][b_] = (dp[a][k_][l_][p_][b_] + (long long)x * y % 998244353 * gg[c]) % 998244353; } } for (k = 0; k <= k_; k++) for (l = 0; l <= k; l++) for (p = 0; p < 2; p++) wht(dp[a][k][l][p], h_); } for (h = h_; h <= d; h++) { if (h > h_) for (k = 0; k <= k_; k++) for (b = 0; b < 1 << h - 1; b++) ans[k][b | 1 << h - 1] = ans[k][b]; else for (b = 0; b < 1 << h_; b++) ans[0][b] = 1; for (k = 0; k <= k_; k++) for (p = 0; p < 2; p++) for (b = 0; b < 1 << h_; b++) dr[k][p][b] = k == 0 && p == 0; for (a = 0; a < 1 << h_; a++) { for (k = 0; k <= k_; k++) for (p = 0; p < 2; p++) for (b = 0; b < 1 << h_; b++) { int x = 0; for (l = 1; l <= k && l <= cnt[h][a]; l++) x = (x + (long long)dp[a][k][l][p][b] * gg[cnt[h][a] - l] % 998244353 * ff[cnt[h][a]]) % 998244353; dq[k][p][b] = x; } for (k = k_; k >= 0; k--) for (p = 0; p < 2; p++) for (k1 = 1; k + k1 <= k_; k1++) for (p1 = 0; p1 < 2; p1++) { int k_ = k + k1, p_ = p ^ p1; for (b = 0; b < 1 << h_; b++) dr[k_][p_][b] = (dr[k_][p_][b] + (long long)dr[k][p][b] * dq[k1][p1][b]) % 998244353; } } for (k = k_; k >= 0; k--) for (k1 = 1; k + k1 <= k_; k1++) for (p = 0; p < 2; p++) { int k_ = k + k1; for (b = 0; b < 1 << h; b++) ans[k_][b] = (ans[k_][b] + (long long)ans[k][b] * dr[k1][p][b & (1 << h_) - 1] % 998244353 * (bcnt[b >> h_] % 2 == 0 || p % 2 == 0 ? 1 : 998244353 - 1)) % 998244353; } } wht(ans[k_], d); for (b = 0; b < 1 << d; b++) ans[k_][b] = (long long)ans[k_][b] * vv[1 << d] % 998244353; for (b = 0; b < 1 << d; b++) printf( %lld , (long long)ans[k_][base ^ b] * fv % 998244353); printf( n ); return 0; } |
`timescale 1ns / 1ps
//-----------------------------------------------
// Company: agh
// Engineer: komorkiewicz
// Create Date: 23:14:48 04/19/2011
// Description: vga generator
//-----------------------------------------------
module hdmi_in
(
//hdmi outputs
output reg hdmi_clk,
output hdmi_de,
output hdmi_hs,
output hdmi_vs,
//image data
output [7:0]hdmi_r,
output [7:0]hdmi_g,
output [7:0]hdmi_b
);
//-----------------------------------------------
//for now supports VGA 640x480 60Hz only
//horizontal
parameter hr=64; //resolution
parameter hbp=8; //back porch
parameter hfp=8; //front porch
parameter hs=2; //sync len
//vertical
parameter vr=64; //resolution
parameter vbp=8; //back porch
parameter vfp=8; //front porch
parameter vs=4; //sync len
//-----------------------------------------------
reg line=1'b0;
reg vsync=1'b1;
reg hsync=1'b1;
reg enab=1'b0;
reg eenab=1'b0;
reg h_enable=1'b0;
reg v_enable=1'b0;
reg [10:0]hcounter=0;
reg [10:0]vcounter=64+1;//480+7
//-----------------------------------------------
reg [7:0]red;
reg [7:0]green;
reg [7:0]blue;
//reg hdmi_clk=1'b0;
//-----------------------------------------------
initial
begin
while(1)
begin
#1 hdmi_clk=1'b0;
#1 hdmi_clk=1'b1;
end
end
//-----------------------------------------------
integer rgbfile,i,v,clo,cle,wl,x;
//-----------------------------------------------
always @(posedge hdmi_clk)
begin
hcounter<=hcounter+1;
eenab<=enab;
if(hcounter==(hr+hbp)) begin
hsync<=1'b0;
end
if(hcounter==(hr+hbp+hs)) begin
hsync<=1'b1;
line<=1'b0;
end
if(hcounter<hr)
h_enable<=1'b1;
else
h_enable<=1'b0;
if(vcounter<vr)
v_enable<=1'b1;
else
v_enable<=1'b0;
if((v_enable==1'b1)&&(h_enable==1'b1))
enab<=1'b1;
else
enab<=1'b0;
if(hcounter==(hr+hbp+hs+hfp))
begin
hcounter<=0;
line<=1'b1;
end
end
//-----------------------------------------------
//TB only
always @(posedge hdmi_clk)
begin
if(enab)
begin
red=$fgetc(rgbfile);
green=$fgetc(rgbfile);
blue=$fgetc(rgbfile);
end
end
//TB end
//-----------------------------------------------
reg [7:0]vsc=0;
always @(posedge line)
begin
vcounter<=vcounter+1;
if(vcounter==(vr+vbp))
begin
vsync<=1'b0;
//TB only
vsc=vsc+1;
rgbfile = $fopen("matlab/reka_bin64.ppm","rb");
// read header file
for(i=0;i<13;i=i+1)
begin
v=$fgetc(rgbfile);
end
//TB end
end
if(vcounter==(vr+vbp+vs)) vsync<=1'b1;
if(vcounter==(vr+vbp+vs+vfp)) vcounter<=0;
end
//-----------------------------------------------
assign hdmi_r=red;
assign hdmi_g=green;
assign hdmi_b=blue;
assign hdmi_de=eenab;
assign hdmi_hs=hsync;
assign hdmi_vs=vsync;
//-----------------------------------------------
endmodule
//-----------------------------------------------
|
//
// Paul Gao 02/2021
//
// This is the sender part of bsg_link_sdr, an SDR communication endpoint
// over single source-synchronous channel.
//
// Typical usage: Communication between different hierarchical blocks in
// different clock domains on ASIC. In this way the clock trees can be
// fully independent in different hierarchical blocks.
//
//
// General reset procedures:
//
// Step 1: Assert io_link_reset and core_link_reset.
// Step 2: async_token_reset must be posedge/negedge toggled (0->1->0)
// at least once. token_clk_i cannot toggle during this step.
// Step 3: io_clk_i posedge toggled at least four times after that.
// Step 4: De-assert upstream_io_link_reset to generate io_clk_o.
// Step 5: De-assert downstream_io_link_reset.
// Step 6: De-assert downstream_core_link_reset.
//
// *************************************************************************
// async upstream downstream downstream
// token_reset io_link_reset io_link_reset core_link_reset
// Step 1 0 1 1 1
// Step 2 1 1 1 1
// Step 3 0 1 1 1
// Step 4 0 0 1 1
// Step 5 0 0 0 1
// Step 6 0 0 0 0
// *************************************************************************
//
module bsg_link_sdr_upstream
#(parameter `BSG_INV_PARAM(width_p )
// Receive fifo depth
// MUST MATCH paired bsg_link_sdr_downstream setting
,parameter lg_fifo_depth_p = 3
// Token credit decimation
// MUST MATCH paired bsg_link_sdr_downstream setting
,parameter lg_credit_to_token_decimation_p = 0
,parameter bypass_twofer_fifo_p = 0
,parameter strength_p = 0
)
(// Core side
input io_clk_i
,input io_link_reset_i
,input async_token_reset_i
,input io_v_i
,input [width_p-1:0] io_data_i
,output io_ready_and_o
// IO side
,output io_clk_o
,output io_v_o
,output [width_p-1:0] io_data_o
,input token_clk_i
);
logic osdr_v_li;
logic [width_p-1:0] osdr_data_li;
bsg_link_source_sync_upstream_sync
#(.width_p (width_p)
,.lg_fifo_depth_p (lg_fifo_depth_p)
,.lg_credit_to_token_decimation_p(lg_credit_to_token_decimation_p)
,.bypass_twofer_fifo_p (bypass_twofer_fifo_p)
) sso
(.io_clk_i (io_clk_i)
,.io_link_reset_i (io_link_reset_i)
,.async_token_reset_i(async_token_reset_i)
,.io_v_i (io_v_i)
,.io_data_i (io_data_i)
,.io_ready_and_o (io_ready_and_o)
,.io_v_o (osdr_v_li)
,.io_data_o (osdr_data_li)
,.token_clk_i (token_clk_i)
);
// valid and data signals are sent together
bsg_link_osdr_phy
#(.width_p(width_p+1)
,.strength_p(strength_p)
) osdr_phy
(.clk_i (io_clk_i)
,.reset_i(io_link_reset_i)
,.data_i ({osdr_v_li, osdr_data_li})
,.clk_o (io_clk_o)
,.data_o ({io_v_o, io_data_o})
);
endmodule
`BSG_ABSTRACT_MODULE(bsg_link_sdr_upstream)
|
#include <bits/stdc++.h> using namespace std; const int inf = 1e9 + 7; const int N = 230; const int M = 3500; int m, n; int a[N], b[N]; long long dp[M][N]; int main() { cin >> m >> n; memset(dp, 0, sizeof(dp)); for (int i = 0; i < m; ++i) { cin >> a[i] >> b[i]; dp[a[i]][i]++; if (a[i] != b[i]) { a[i + m] = b[i]; b[i + m] = a[i]; dp[a[i + m]][i + m]++; } } for (int i = 1; i <= n; ++i) { for (int j = 0; j < m * 2; ++j) { if (!dp[i][j]) continue; for (int k = 0; k < 2 * m; ++k) { if (j % m != k % m && a[k] == b[j]) dp[i + a[k]][k] = (dp[i + a[k]][k] + dp[i][j]) % inf; } } } long long ans = 0; for (int i = 0; i < 2 * m; ++i) ans = (ans + dp[n][i]) % inf; cout << ans << endl; return 0; } |
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tmu2_clamp(
input sys_clk,
input sys_rst,
output busy,
input pipe_stb_i,
output pipe_ack_o,
input signed [11:0] dx,
input signed [11:0] dy,
input signed [17:0] tx,
input signed [17:0] ty,
input [10:0] tex_hres,
input [10:0] tex_vres,
input [10:0] dst_hres,
input [10:0] dst_vres,
output reg pipe_stb_o,
input pipe_ack_i,
output reg [10:0] dx_c,
output reg [10:0] dy_c,
output reg [16:0] tx_c,
output reg [16:0] ty_c
);
always @(posedge sys_clk) begin
if(sys_rst)
pipe_stb_o <= 1'b0;
else begin
if(pipe_ack_i)
pipe_stb_o <= 1'b0;
if(pipe_stb_i & pipe_ack_o) begin
pipe_stb_o <= (~dx[11]) && (dx[10:0] < dst_hres)
&& (~dy[11]) && (dy[10:0] < dst_vres);
dx_c <= dx[10:0];
dy_c <= dy[10:0];
if(tx[17])
tx_c <= 17'd0;
else if(tx[16:0] > {tex_hres - 11'd1, 6'd0})
tx_c <= {tex_hres - 11'd1, 6'd0};
else
tx_c <= tx[16:0];
if(ty[17])
ty_c <= 17'd0;
else if(ty[16:0] > {tex_vres - 11'd1, 6'd0})
ty_c <= {tex_vres - 11'd1, 6'd0};
else
ty_c <= ty[16:0];
end
end
end
assign pipe_ack_o = ~pipe_stb_o | pipe_ack_i;
assign busy = pipe_stb_o;
endmodule
|
`default_nettype none
`include "irq.h"
/****
HOLD
0 START
1 MOVE_K2U
1 MOVE_UK
2 EMD
*/
module execute_exception_check_ldst(
input wire iCLOCK,
input wire inRESET,
input wire iRESET_SYNC,
//Event CTRL
input wire iEVENT_HOLD,
input wire iEVENT_START,
input wire iEVENT_IRQ_FRONT2BACK,
input wire iEVENT_IRQ_BACK2FRONT,
input wire iEVENT_END,
//Execute Module State
input wire iPREV_STATE_NORMAL,
input wire iPREV_STATE_LDST,
//Previous Instruxtion
input wire iPREV_VALID,
input wire iPREV_KERNEL_ACCESS,
input wire iPREV_PAGING_ENA,
input wire iPREV_LDST_RW,
//Load Store
input wire iLDST_VALID,
input wire [11:0] iLDST_MMU_FLAG,
//Output Exception
output wire oEXCEPT_VALID,
output wire [6:0] oEXCEPT_NUM
);
reg b_kernel_access;
reg b_paging_ena;
reg [31:0] b_pc;
reg b_ldst_rw;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_kernel_access <= 1'b0;
b_paging_ena <= 1'b0;
b_pc <= 32'h0;
b_ldst_rw <= 1'b0;
end
else if(iRESET_SYNC || iEVENT_HOLD)begin
b_kernel_access <= 1'b0;
b_paging_ena <= 1'b0;
b_ldst_rw <= 1'b0;
end
else begin
if(iPREV_VALID && iPREV_STATE_NORMAL)begin
b_kernel_access <= iPREV_KERNEL_ACCESS;
b_paging_ena <= iPREV_PAGING_ENA;
b_ldst_rw <= iPREV_LDST_RW;
end
end
end
/**************************************************************************************************
Load/Store Exception
**************************************************************************************************/
wire exception_ldst_valid;
wire [6:0] exception_ldst_num;
assign {exception_ldst_valid, exception_ldst_num} = func_ldst_exception_check(
b_paging_ena,
b_kernel_access,
b_ldst_rw,
iLDST_MMU_FLAG[5:0]
);
//MMU Flag Check
function [7:0] func_ldst_exception_check;
input func_paging;
input func_kernel; //1:kernel mode
input func_rw;
input [5:0] func_mmu_flags;
begin
if(func_paging)begin
//Privilege error check
if(func_kernel)begin //Kernell Mode
case(func_mmu_flags[5:4])
2'h1:
begin
if(func_rw)begin
func_ldst_exception_check = {1'b1, `INT_NUM_PRIVILEGE_ERRPR};
end
else begin
func_ldst_exception_check = 8'h0;
end
end
2'h0,
2'h2,
2'h3:
begin
func_ldst_exception_check = 8'h0;
end
endcase
end
else begin //User Mode
case(func_mmu_flags[5:4])
2'h0: func_ldst_exception_check = {1'b1, `INT_NUM_PRIVILEGE_ERRPR};
2'h1,
2'h2:
begin
if(func_rw)begin
func_ldst_exception_check = {1'b1, `INT_NUM_PRIVILEGE_ERRPR};
end
else begin
func_ldst_exception_check = 8'h0;
end
end
2'h3: func_ldst_exception_check = 8'h0;
endcase
end
end
else begin
func_ldst_exception_check = 8'h0;
end
end
endfunction
assign oEXCEPT_VALID = exception_ldst_valid && iPREV_STATE_LDST;
assign oEXCEPT_NUM = exception_ldst_num;
endmodule
`default_nettype wire
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Jafet Chaves Barrantes
//
// Create Date: 15:45:17 04/03/2016
// Design Name:
// Module Name: contador_AD_SS_T_2dig
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module contador_AD_SS_T_2dig
(
input wire clk,
input wire reset,
input wire [3:0] en_count,
input wire enUP,
input wire enDOWN,
output wire [7:0] data_SS_T
);
localparam N = 6; // Para definir el número de bits del contador (hasta 59->6 bits)
//Declaración de señales
reg [N-1:0] q_act, q_next;
wire [N-1:0] count_data;
reg [3:0] digit1, digit0;
//Descripción del comportamiento
always@(posedge clk, posedge reset)
begin
if(reset)
begin
q_act <= 6'b0;
end
else
begin
q_act <= q_next;
end
end
//Lógica de salida
always@*
begin
if (en_count == 8)
begin
if (enUP)
begin
if (q_act >= 6'd59) q_next = 6'd0;
else q_next = q_act + 6'd1;
end
else if (enDOWN)
begin
if (q_act == 6'd0) q_next = 6'd59;
else q_next = q_act - 6'd1;
end
else q_next = q_act;
end
else q_next = q_act;
end
assign count_data = q_act;
//Decodificación BCD (2 dígitos)
always@*
begin
case(count_data)
6'd0: begin digit1 = 4'b0000; digit0 = 4'b0000; end
6'd1: begin digit1 = 4'b0000; digit0 = 4'b0001; end
6'd2: begin digit1 = 4'b0000; digit0 = 4'b0010; end
6'd3: begin digit1 = 4'b0000; digit0 = 4'b0011; end
6'd4: begin digit1 = 4'b0000; digit0 = 4'b0100; end
6'd5: begin digit1 = 4'b0000; digit0 = 4'b0101; end
6'd6: begin digit1 = 4'b0000; digit0 = 4'b0110; end
6'd7: begin digit1 = 4'b0000; digit0 = 4'b0111; end
6'd8: begin digit1 = 4'b0000; digit0 = 4'b1000; end
6'd9: begin digit1 = 4'b0000; digit0 = 4'b1001; end
6'd10: begin digit1 = 4'b0001; digit0 = 4'b0000; end
6'd11: begin digit1 = 4'b0001; digit0 = 4'b0001; end
6'd12: begin digit1 = 4'b0001; digit0 = 4'b0010; end
6'd13: begin digit1 = 4'b0001; digit0 = 4'b0011; end
6'd14: begin digit1 = 4'b0001; digit0 = 4'b0100; end
6'd15: begin digit1 = 4'b0001; digit0 = 4'b0101; end
6'd16: begin digit1 = 4'b0001; digit0 = 4'b0110; end
6'd17: begin digit1 = 4'b0001; digit0 = 4'b0111; end
6'd18: begin digit1 = 4'b0001; digit0 = 4'b1000; end
6'd19: begin digit1 = 4'b0001; digit0 = 4'b1001; end
6'd20: begin digit1 = 4'b0010; digit0 = 4'b0000; end
6'd21: begin digit1 = 4'b0010; digit0 = 4'b0001; end
6'd22: begin digit1 = 4'b0010; digit0 = 4'b0010; end
6'd23: begin digit1 = 4'b0010; digit0 = 4'b0011; end
6'd24: begin digit1 = 4'b0010; digit0 = 4'b0100; end
6'd25: begin digit1 = 4'b0010; digit0 = 4'b0101; end
6'd26: begin digit1 = 4'b0010; digit0 = 4'b0110; end
6'd27: begin digit1 = 4'b0010; digit0 = 4'b0111; end
6'd28: begin digit1 = 4'b0010; digit0 = 4'b1000; end
6'd29: begin digit1 = 4'b0010; digit0 = 4'b1001; end
6'd30: begin digit1 = 4'b0011; digit0 = 4'b0000; end
6'd31: begin digit1 = 4'b0011; digit0 = 4'b0001; end
6'd32: begin digit1 = 4'b0011; digit0 = 4'b0010; end
6'd33: begin digit1 = 4'b0011; digit0 = 4'b0011; end
6'd34: begin digit1 = 4'b0011; digit0 = 4'b0100; end
6'd35: begin digit1 = 4'b0011; digit0 = 4'b0101; end
6'd36: begin digit1 = 4'b0011; digit0 = 4'b0110; end
6'd37: begin digit1 = 4'b0011; digit0 = 4'b0111; end
6'd38: begin digit1 = 4'b0011; digit0 = 4'b1000; end
6'd39: begin digit1 = 4'b0011; digit0 = 4'b1001; end
6'd40: begin digit1 = 4'b0100; digit0 = 4'b0000; end
6'd41: begin digit1 = 4'b0100; digit0 = 4'b0001; end
6'd42: begin digit1 = 4'b0100; digit0 = 4'b0010; end
6'd43: begin digit1 = 4'b0100; digit0 = 4'b0011; end
6'd44: begin digit1 = 4'b0100; digit0 = 4'b0100; end
6'd45: begin digit1 = 4'b0100; digit0 = 4'b0101; end
6'd46: begin digit1 = 4'b0100; digit0 = 4'b0110; end
6'd47: begin digit1 = 4'b0100; digit0 = 4'b0111; end
6'd48: begin digit1 = 4'b0100; digit0 = 4'b1000; end
6'd49: begin digit1 = 4'b0100; digit0 = 4'b1001; end
6'd50: begin digit1 = 4'b0101; digit0 = 4'b0000; end
6'd51: begin digit1 = 4'b0101; digit0 = 4'b0001; end
6'd52: begin digit1 = 4'b0101; digit0 = 4'b0010; end
6'd53: begin digit1 = 4'b0101; digit0 = 4'b0011; end
6'd54: begin digit1 = 4'b0101; digit0 = 4'b0100; end
6'd55: begin digit1 = 4'b0101; digit0 = 4'b0101; end
6'd56: begin digit1 = 4'b0101; digit0 = 4'b0110; end
6'd57: begin digit1 = 4'b0101; digit0 = 4'b0111; end
6'd58: begin digit1 = 4'b0101; digit0 = 4'b1000; end
6'd59: begin digit1 = 4'b0101; digit0 = 4'b1001; end
default: begin digit1 = 0; digit0 = 0; end
endcase
end
assign data_SS_T = {digit1,digit0};
endmodule
|
#include <bits/stdc++.h> using namespace std; char s[1010][3][50]; bool p[1010]; int main() { int n, i, j, c; cin >> n; for (i = 1; i <= n; i++) cin >> s[i][1] >> s[i][2]; memset(p, true, sizeof(p)); for (i = 1; i <= n; i++) { for (j = 1; j <= n; j++) { if (i != j) { if (strcmp(s[i][2], s[j][1]) == 0) { strcpy(s[i][2], s[j][2]); p[j] = false; } } } } for (i = 1, c = 0; i <= n; i++) if (p[i]) c++; cout << c << endl; for (i = 1; i <= n; i++) { if (p[i]) cout << s[i][1] << << s[i][2] << endl; } return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty.
// SPDX-License-Identifier: CC0-1.0
module some_module (
input [3:0] i_clks
);
logic [ 1 : 0 ] some_state;
logic [1:0] some_other_state;
always @(posedge i_clks[3]) begin
case (some_state)
2'b11:
if (some_other_state == 0)
some_state <= 2'b00;
default:
$display ("This is a display statement");
endcase
if (i_clks[3])
some_other_state <= 0;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
`define BROKEN
module t1(
input [3:0] i_clks,
input i_clk0,
input i_clk1
);
some_module
some_module
(
.i_clks (i_clks)
);
endmodule
module t2(
input [2:0] i_clks,
input i_clk0,
input i_clk1,
input i_clk2,
input i_data
);
logic [3:0] the_clks;
logic data_q;
assign the_clks[3] = i_clk1;
assign the_clks[2] = i_clk2;
assign the_clks[1] = i_clk1;
assign the_clks[0] = i_clk0;
always @(posedge i_clk0) begin
data_q <= i_data;
end
t1 t1
(
.i_clks (the_clks),
.i_clk0 (i_clk0),
.i_clk1 (i_clk1)
);
endmodule
module t(
/*AUTOARG*/
// Inputs
clk /*verilator clocker*/,
input clk0 /*verilator clocker*/,
input clk1 /*verilator clocker*/,
input clk2 /*verilator clocker*/,
input data_in
);
input clk;
logic [2:0] clks;
assign clks = {1'b0, clk1, clk0};
t2
t2
(
.i_clks (clks),
.i_clk0 (clk0),
.i_clk1 (clk),
.i_clk2 (clk2),
.i_data (data_in)
);
// initial begin
// $write("*-* All Finished *-*\n");
// $finish;
// end
endmodule
|
/**
* Module: example
*
* Description:
* A parametrized example that uses the arbiter and timers. The 'request'
* asks for ownership of shared resource. The 'grant' indicates that
* ownership has been given. The 'active' is high when an actor (any actor)
* has been granted ownership.
*
* Created:
* Sun Jun 2 16:23:21 EDT 2013
*
* Author:
* Berin Martini ()
*/
`ifndef _example_ `define _example_
`include "timer.v"
`include "arbiter.v"
module example
#(parameter
NUM_PORTS = 3,
TIMEOUT = 10)
(input clk,
input rst,
input [NUM_PORTS-1:0] request,
output [NUM_PORTS-1:0] grant,
output active
);
/**
* Local parameters
*/
`ifdef VERBOSE
initial $display("Bus example with timeout %d", TIMEOUT);
`endif
/**
* Internal signals
*/
wire [NUM_PORTS-1:0] timed_req;
wire [NUM_PORTS-1:0] timed_grant;
/**
* Implementation
*/
arbiter #(
.NUM_PORTS (NUM_PORTS))
arbiter_ (
.clk (clk),
.rst (rst),
.request (timed_req),
.grant (timed_grant),
.active (active)
);
genvar xx;
generate
for (xx = 0; xx < NUM_PORTS; xx = xx + 1) begin : TIMER_
timer #(
.TIMEOUT (TIMEOUT))
timer_ (
.clk (clk),
.rst (rst),
.up_req (request[xx]),
.up_grant (grant[xx]),
.up_ack (),
.down_req (timed_req[xx]),
.down_grant (timed_grant[xx]),
.down_ack ()
);
end
endgenerate
endmodule
`endif // `ifndef _example_
|
#include <bits/stdc++.h> using namespace std; int n; vector<vector<int>> a; bool inp(int i, int j) { (i < n && j == n) && inp(i + 1, 0); (i < n && j < n) && (cin >> a[i][j]); (i < n && j < n) && (inp(i, j + 1)); return 0; } bool floyd(int k, int i, int j) { (k < n && i < n && j == n) && floyd(k, i + 1, 0); (k < n && i == n) && floyd(k + 1, 0, 0); (k < n && i < n && j < n) && floyd(k, i, j + 1); (k < n && i < n && j < n) && (a[i][j] = min(a[i][j], a[i][k] + a[k][j])); return 0; } void go(int &ans, int i) { ans = max(ans, *max_element(begin(a[i]), end(a[i]))); } int main() { cin.tie(nullptr); ios_base::sync_with_stdio(0); cin >> n; a.assign(20, vector<int>(20)); inp(0, 0); floyd(0, 0, 0); int ans = 0; go(ans, 0); go(ans, 1); go(ans, 2); go(ans, 3); go(ans, 4); go(ans, 5); go(ans, 6); go(ans, 7); go(ans, 8); go(ans, 9); cout << ans << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int arr[4]; cin >> arr[0] >> arr[1] >> arr[2] >> arr[3]; sort(arr, arr + 4); if ((arr[0] + arr[3]) == (arr[1] + arr[2]) || (arr[0] + arr[1] + arr[2]) == arr[3]) { cout << YES << n ; } else { cout << NO << n ; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DECAP_4_V
`define SKY130_FD_SC_HS__DECAP_4_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog wrapper for decap with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__decap.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__decap_4 (
VPWR,
VGND
);
input VPWR;
input VGND;
sky130_fd_sc_hs__decap base (
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__decap_4 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__decap base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__DECAP_4_V
|
#include <bits/stdc++.h> using namespace std; const int MaxN = 100010; struct adjList { int id, nxt; } Lst[MaxN * 2]; int LCnt, Head[MaxN]; int N, w[MaxN], root; void addEdge(int a, int b) { Lst[LCnt].id = b; Lst[LCnt].nxt = Head[a]; Head[a] = LCnt++; } pair<long long, long long> dfs(int id, int pre) { vector<pair<long long, long long> > v; for (int x = Head[id]; x != -1; x = Lst[x].nxt) { if (Lst[x].id != pre) { v.push_back(dfs(Lst[x].id, id)); } } sort(v.begin(), v.end()); long long sum = 1, rem = 0; w[id]--; for (int i = (int)(v.size()) - 1; i >= 0; i--) { if (w[id] == 0) break; w[id]--; sum += v[i].first + 1; rem += v[i].second; } if (w[id]) { sum += 2 * min((long long)w[id], rem); w[id] -= min((long long)w[id], rem); } return make_pair(sum, w[id]); } int main() { while (cin >> N) { memset(Head, -1, sizeof(Head)); LCnt = 0; for (int i = 1; i <= N; i++) { scanf( %d , w + i); } for (int i = 1; i < N; i++) { int a, b; scanf( %d %d , &a, &b); addEdge(a, b); addEdge(b, a); } cin >> root; w[root]++; cout << dfs(root, -1).first - 1 << endl; ; } return 0; } |
#include <bits/stdc++.h> using namespace std; typedef pair<int, int> pii; typedef long long ll; typedef unsigned long long ull; template <typename T> bool umax(T& a, const T& b) { return b <= a ? false : (a = b, true); } template <typename T> bool umin(T& a, const T& b) { return b >= a ? false : (a = b, true); } template <typename T> void V2A(T a[], const vector<T>& b) { for (int i = 0; i < b.size(); i++) a[i] = b[i]; } template <typename T> void A2V(vector<T>& a, const T b[]) { for (int i = 0; i < a.size(); i++) a[i] = b[i]; } const double PI = acos(-1.0); const int INF = 1e9 + 7; const int maxn = 2e3 + 7; bool plot[maxn][maxn]; int r[maxn][maxn]; int n, m, k; int check(int row, int col) { if (col >= 0 && col < m) return true; return false; } int main() { cin >> n >> m >> k; for (int i = 0; i < k; i++) { int x, y; scanf( %d%d , &x, &y); x--; y--; if (!plot[x][y]) { printf( %d %d n , x + 1, y + 1); plot[x][y] = true; continue; } for (int d = 1; d <= 3; d++) { int Max = min(n, x + d + 1); for (int row = max(0, x - d); row < Max; row++) { int t = d - abs(x - row), col1 = y - t, col2 = y + t; if (check(row, col1)) umax(r[x][y], r[row][col1] - d); if (check(row, col2)) umax(r[x][y], r[row][col2] - d); } } for (int d = r[x][y] + 1;; d++) { int Max = min(n, x + d + 1); bool ok = false; for (int row = max(0, x - d); row < Max; row++) { int t = d - abs(x - row), col1 = y - t, col2 = y + t; if (check(row, col1) && !plot[row][col1]) { ok = true; printf( %d %d n , row + 1, col1 + 1); plot[row][col1] = true; break; } if (check(row, col2) && !plot[row][col2]) { ok = true; printf( %d %d n , row + 1, col2 + 1); plot[row][col2] = true; break; } } if (ok) { r[x][y] = d - 1; break; } } } return 0; } |
#include <bits/stdc++.h> long long t1[100], t2[100], n, k, m, i, j, mod[10], o, s; int main() { scanf( %I64d %I64d %I64d , &n, &k, &m); t1[0] = 1; for (i = 0; i < 10; i++) mod[i] = i % k; for (i = 1; i <= n; i++) { for (j = 0; j < 10; j++) { if (j == 0 && (i == n || i == 1)) continue; for (o = 0; o < k; o++) { t2[(o + mod[j]) % k] += t1[o]; } } if (i != 1) { for (j = 1; j < 10; j++) { t2[mod[j]]++; } } s += t2[0]; t2[0] = 0; t1[0] = 0; if (i != n) { if (i == n - 1) s *= 9; else s *= 10; s %= m; } for (j = 1; j < k; j++) { t1[j] = t2[j] % m; t2[j] = 0; } for (j = 0; j < 10; j++) mod[j] = (mod[j] * 10) % k; } s %= m; printf( %I64d n , s); return 0; } |
//*****************************************************************************
// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2.3
// \ \ Application : MIG
// / / Filename : dram.v
// /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
// \ \ / \ Date Created : Wed Feb 01 2012
// \___\/\___\
//
// Device : 7 Series
// Design Name : DDR3 SDRAM
// Purpose :
// Wrapper module for the user design top level file. This module can be
// instantiated in the system and interconnect as shown in example design
// (example_top module).
// Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module dram (
// Inouts
inout [63:0] ddr3_dq,
inout [7:0] ddr3_dqs_n,
inout [7:0] ddr3_dqs_p,
// Outputs
output [15:0] ddr3_addr,
output [2:0] ddr3_ba,
output ddr3_ras_n,
output ddr3_cas_n,
output ddr3_we_n,
output ddr3_reset_n,
output [0:0] ddr3_ck_p,
output [0:0] ddr3_ck_n,
output [0:0] ddr3_cke,
output [0:0] ddr3_cs_n,
output [7:0] ddr3_dm,
output [0:0] ddr3_odt,
// Inputs
// Differential system clocks
input sys_clk_p,
input sys_clk_n,
// user interface signals
input [29:0] app_addr,
input [2:0] app_cmd,
input app_en,
input [511:0] app_wdf_data,
input app_wdf_end,
input [63:0] app_wdf_mask,
input app_wdf_wren,
output [511:0] app_rd_data,
output app_rd_data_end,
output app_rd_data_valid,
output app_rdy,
output app_wdf_rdy,
input app_sr_req,
input app_ref_req,
input app_zq_req,
output app_sr_active,
output app_ref_ack,
output app_zq_ack,
output ui_clk,
output ui_clk_sync_rst,
output init_calib_complete,
input sys_rst
);
// Start of IP top instance
dram_mig u_dram_mig (
// Memory interface ports
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),
.ddr3_ck_n (ddr3_ck_n),
.ddr3_ck_p (ddr3_ck_p),
.ddr3_cke (ddr3_cke),
.ddr3_ras_n (ddr3_ras_n),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_we_n (ddr3_we_n),
.ddr3_dq (ddr3_dq),
.ddr3_dqs_n (ddr3_dqs_n),
.ddr3_dqs_p (ddr3_dqs_p),
.init_calib_complete (init_calib_complete),
.ddr3_cs_n (ddr3_cs_n),
.ddr3_dm (ddr3_dm),
.ddr3_odt (ddr3_odt),
// Application interface ports
.app_addr (app_addr),
.app_cmd (app_cmd),
.app_en (app_en),
.app_wdf_data (app_wdf_data),
.app_wdf_end (app_wdf_end),
.app_wdf_wren (app_wdf_wren),
.app_rd_data (app_rd_data),
.app_rd_data_end (app_rd_data_end),
.app_rd_data_valid (app_rd_data_valid),
.app_rdy (app_rdy),
.app_wdf_rdy (app_wdf_rdy),
.app_sr_req (app_sr_req),
.app_ref_req (app_ref_req),
.app_zq_req (app_zq_req),
.app_sr_active (app_sr_active),
.app_ref_ack (app_ref_ack),
.app_zq_ack (app_zq_ack),
.ui_clk (ui_clk),
.ui_clk_sync_rst (ui_clk_sync_rst),
.app_wdf_mask (app_wdf_mask),
// System Clock Ports
.sys_clk_p (sys_clk_p),
.sys_clk_n (sys_clk_n),
.sys_rst (sys_rst)
);
// End of IP top instance
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> void chmax(T& a, const T& b) { a = max(a, b); } template <class T> void chmin(T& a, const T& b) { a = min(a, b); } using ll = long long; using P = pair<int, int>; using VI = vector<int>; using VVI = vector<VI>; using VL = vector<ll>; using VVL = vector<VL>; int dp[6][410][410]; int d[410]; int main() { ios::sync_with_stdio(false); cin.tie(0); int tt; cin >> tt; while (tt--) { int n, m; cin >> n >> m; for (int k = 0; k < int(5); ++k) for (int i = 0; i < int(m + 1); ++i) for (int j = 0; j < int(m + 1); ++j) dp[k][i][j] = 100; int ans = 100; for (int _ = 0; _ < int(n); ++_) { for (int j = 0; j < int(m); ++j) { char c; cin >> c; d[j + 1] = c - 0 ; } for (int j = 0; j < int(m); ++j) d[j + 1] += d[j]; for (int k = int(5) - 1; k >= 0; --k) for (int r = 0; r < int(m + 1); ++r) for (int l = int(r - 4 + 1) - 1; l >= 0; --l) { if (k == 0 || k == 4) { int x = r - 1 - (l + 1) - (d[r - 1] - d[l + 1]); if (k == 4) { chmin(ans, x + dp[k][l][r]); dp[k][l][r] += d[r - 1] - d[l + 1] + 1 - (d[l + 1] - d[l]) + 1 - (d[r] - d[r - 1]); } else { dp[1][l][r] = x; } } else { int x = d[r - 1] - d[l + 1] + 1 - (d[l + 1] - d[l]) + 1 - (d[r] - d[r - 1]); if (k < 3) { dp[k + 1][l][r] = dp[k][l][r] + x; } else { chmin(dp[k + 1][l][r], dp[k][l][r] + x); } } } } cout << ans << n ; } } |
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const long long mod1 = 998244353; const double pie = 3.1415926535; long long power(long long x, long long y) { if (y == 0) return 1; else { if (y % 2 == 0) return power(x * x, y / 2); else return x * power(x * x, (y - 1) / 2); } } long long mod_power(long long x, long long y, long long m) { long long r = 1; x = x % m; if (x == 0) return 0; while (y > 0) { if (y & 1) r = (r * x) % m; y = y / 2; x = (x * x) % m; } return r; } unsigned long long gcd(unsigned long long x, unsigned long long y) { if (y == 0) return x; return gcd(y, x % y); } vector<long long> extended_Euclid(long long a, long long b) { vector<long long> v(3); if (b == 0) { v[0] = a; v[1] = 1; v[2] = 0; return v; } else { vector<long long> v1 = extended_Euclid(b, a % b); v[0] = v1[0]; v[1] = v1[2]; v[2] = v1[1] - (a / b) * v1[2]; return v; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int TESTS = 1; while (TESTS--) { int n, k; cin >> n >> k; vector<vector<int> > adj; long long t = 0; int flag = 0; for (int i = 0; i < k; i++) { int m; cin >> m; vector<int> v(m); for (int i = 0; i < m; i++) cin >> v[i]; if (v[0] == 1) { for (int i = 1; i < m; i++) { if (v[i] == (v[i - 1] + 1)) flag++; else break; } t += m - 1 - flag; } else t += m - 1; } long long ans = t + n - flag - 1; cout << ans << endl; } } |
#include <bits/stdc++.h> using namespace std; unsigned long long gcd(unsigned long long a, unsigned long long b) { return b == 0 ? a : gcd(b, a % b); } const int MAXTREE = 50; const int MOD = 998244353; const int INV6 = 166374059; const int MINCOORD = -1000000000; const int MAXCOORD = +1000000000; struct P { int x, y; P() {} P(int x, int y) : x(x), y(y) {} }; P operator-(const P &a, const P &b) { return P(a.x - b.x, a.y - b.y); } bool operator==(const P &a, const P &b) { return a.x == b.x && a.y == b.y; } struct Pol { vector<P> p; }; int ntree, tlast; P t[MAXTREE]; void rotate(P &p) { p = P(-p.y, +p.x); } void rotate(Pol &pol) { for (int i = (0); i < (((int)(pol.p).size())); ++i) rotate(pol.p[i]); } void flip(P &p) { swap(p.x, p.y); } void flip(Pol &pol) { for (int i = (0); i < (((int)(pol.p).size())); ++i) flip(pol.p[i]); reverse(pol.p.begin(), pol.p.end()); } P infleftup(const P &p) { int t = min(p.x - MINCOORD, MAXCOORD - p.y); return P(p.x - t, p.y + t); } P infleftdown(const P &p) { int t = min(p.x - MINCOORD, p.y - MINCOORD); return P(p.x - t, p.y - t); } P infrightup(const P &p) { int t = min(MAXCOORD - p.x, MAXCOORD - p.y); return P(p.x + t, p.y + t); } P infrightdown(const P &p) { int t = min(MAXCOORD - p.x, p.y - MINCOORD); return P(p.x + t, p.y - t); } int getdelta(const P &a, const P &b) { P ba = b - a; assert(ba.y == 0 || abs(ba.y) == abs(ba.x)); return ba.y / ba.x; } int getdir(const P &a, const P &b) { P ba = b - a; int mag = max(abs(ba.x), abs(ba.y)); assert(mag != 0 && ba.x % mag == 0 && ba.y % mag == 0); ba.x /= mag, ba.y /= mag; if (ba == P(1, 1)) return 0; if (ba == P(1, 0)) return 1; if (ba == P(1, -1)) return 2; if (ba == P(0, -1)) return 3; if (ba == P(-1, -1)) return 4; if (ba == P(-1, 0)) return 5; if (ba == P(-1, 1)) return 6; if (ba == P(0, 1)) return 7; assert(false); return -1; } int gety(int x, const vector<P> &path) { int idx = 0; while (idx + 1 < ((int)(path).size()) && path[idx + 1].x <= x) ++idx; assert(idx + 1 < ((int)(path).size())); int v = getdelta(path[idx], path[idx + 1]); return path[idx].y + (x - path[idx].x) * v; } vector<pair<P, P>> segmentsbeloworequal(P a, P b, const vector<P> &path) { bool swapab = false; if (a.x > b.x) swapab = true, swap(a, b); P ba = b - a; vector<pair<P, P>> ret; if (ba.x == 0) { int x = a.x, py = gety(x, path); assert(!swapab); if (a.y <= py) ret.push_back(make_pair(a, P(x, min(py, b.y)))); else if (b.y <= py) ret.push_back(make_pair(P(x, py), b)); } else { int x = a.x, y = a.y, u = getdelta(a, b), idx = 0; P oth = a; while (true) { while (idx + 1 < ((int)(path).size()) && path[idx + 1].x <= x) ++idx; assert(idx + 1 < ((int)(path).size())); int v = getdelta(path[idx], path[idx + 1]); int py = path[idx].y + (x - path[idx].x) * v; if (x == b.x) { if (y <= py) ret.push_back(make_pair(oth, b)); break; } int dx = min(b.x - x, path[idx + 1].x - x); if (y <= py) { if (u - v >= 1) { int t = (py - y) / (u - v); if (t < dx) ret.push_back(make_pair(oth, P(x + t, y + u * t))); } } else { if (v - u >= 1) { int t = (y - py - 1) / (v - u); if (t < dx) oth = P(x + t + 1, y + u * (t + 1)); } } x += dx, y += u * dx; } } if (swapab) { swapab = false, swap(a, b), reverse(ret.begin(), ret.end()); for (int i = (0); i < (((int)(ret).size())); ++i) swap(ret[i].first, ret[i].second); } return ret; } bool isbeloworequal(const P &a, const vector<P> &path) { return a.y <= gety(a.x, path); } bool isinside(const P &p, const Pol &pol) { if (((int)(pol.p).size()) == 1) return pol.p[0] == p; bool ret = false; for (int i = (0); i < (((int)(pol.p).size())); ++i) { P a = pol.p[i], b = pol.p[(i + 1) % ((int)(pol.p).size())], c = pol.p[(i + 2) % ((int)(pol.p).size())], d = pol.p[(i + 3) % ((int)(pol.p).size())]; int pdir = getdir(a, b), cdir = getdir(b, c), ndir = getdir(c, d); int sgn, delta; P l, r; bool includefirst, includelast; if (cdir < 4) { includefirst = pdir < 3 || pdir >= cdir + 4, includelast = cdir != 3 && ndir >= 4 && ndir <= cdir + 4; if (cdir == 3) { sgn = includefirst ? +1 : 0, delta = 0, l = r = b; ++l.y, ++r.y; } else { sgn = +1, delta = getdelta(b, c); l = b, r = c; ++l.y, ++r.y; if (!includefirst) ++l.x, l.y += delta; if (!includelast) --r.x, r.y -= delta; } } else { includefirst = pdir != 7 && pdir >= cdir - 4, includelast = cdir != 7 && ndir <= cdir - 4; if (cdir == 7) { sgn = includefirst ? -1 : 0, delta = 0, l = r = b; } else { sgn = -1, delta = getdelta(c, b), l = c, r = b; if (!includefirst) --r.x, r.y -= delta; if (!includelast) ++l.x, l.y += delta; } } if (sgn != 0 && l.x <= p.x && p.x <= r.x && p.y < l.y + (p.x - l.x) * delta) ret = !ret; } return ret; } void updatepol(Pol &pol, bool prvonpol, const P p, const vector<P> &path, const Pol &orig) { if (((int)(pol.p).size()) >= 1 && p == pol.p[((int)(pol.p).size()) - 1]) return; if (!prvonpol && ((int)(pol.p).size()) >= 1) { P a = pol.p[((int)(pol.p).size()) - 1], b = p; bool swapab = false; if (a.x > b.x) swapab = true, swap(a, b); int ay = gety(a.x, path), by = gety(b.x, path); if (ay != a.y) { assert(ay == a.y + 1); if (isinside(P(a.x, a.y + 1), orig)) ++a.y; else ++a.x, --ay; } if (by != b.y) { assert(by == b.y + 1); if (isinside(P(b.x, b.y + 1), orig)) ++b.y; else --b.x, --by; } vector<P> extra; if (!(a == pol.p[((int)(pol.p).size()) - 1])) extra.push_back(a); for (int i = (0); i < (((int)(path).size())); ++i) if (a.x < path[i].x && path[i].x < b.x) extra.push_back(path[i]); if (!(b == p) && !(b == a)) extra.push_back(b); if (swapab) reverse(extra.begin(), extra.end()); for (int i = (0); i < (((int)(extra).size())); ++i) pol.p.push_back(extra[i]); } if (((int)(pol.p).size()) == 0 || !(p == pol.p[((int)(pol.p).size()) - 1])) pol.p.push_back(p); } Pol cutabove(Pol pol, const vector<P> &path) { if (((int)(pol.p).size()) == 0) return pol; Pol ret; if (((int)(pol.p).size()) == 1) return isbeloworequal(pol.p[0], path) ? pol : ret; bool prvonpol = false; for (int i = (0); i < (((int)(pol.p).size())); ++i) { P a = pol.p[i], b = pol.p[(i + 1) % ((int)(pol.p).size())]; vector<pair<P, P>> segments = segmentsbeloworequal(a, b, path); if (((int)(segments).size()) == 0 || !(segments[0].first == a)) prvonpol = false; for (int k = (0); k < (((int)(segments).size())); ++k) { if (segments[k].first == b) { assert(segments[k].second == b); assert(k == ((int)(segments).size()) - 1); prvonpol = false; } else { updatepol(ret, prvonpol, segments[k].first, path, pol); if (segments[k].first == segments[k].second) { prvonpol = false; } else if (segments[k].second == b) { prvonpol = true; } else { updatepol(ret, true, segments[k].second, path, pol); prvonpol = false; } } } } if (((int)(ret.p).size()) >= 1) { if (!(ret.p[0] == pol.p[0])) prvonpol = false; updatepol(ret, prvonpol, ret.p[0], path, pol); if (((int)(ret.p).size()) >= 2 && ret.p[((int)(ret.p).size()) - 1] == ret.p[0]) ret.p.pop_back(); } return ret; } Pol cut(Pol pol, P a, P b, bool winequal) { int nrot = 0, nflip = 0; while (b.y <= a.y || b.x < a.x) rotate(pol), rotate(a), rotate(b), ++nrot; if (b.y - a.y < b.x - a.x) flip(pol), flip(a), flip(b), ++nflip; P d = b - a; int between = d.y - 1; int asteps = between / 2, bsteps = between / 2, turn = winequal ? 0 : 1; if (between % 2 == 1) if (turn == 0) ++asteps, turn = 1; else ++bsteps, turn = 0; vector<P> path; int y = a.y + asteps; if (d.x == d.y) { P m(a.x + asteps + (turn == 0 ? 1 : 0), y); path.push_back(infleftup(m)); path.push_back(infrightdown(m)); } else if (d.x == 0) { if (asteps < bsteps) { assert(turn == 0); ++asteps, turn = 1; } if (bsteps < asteps) { assert(turn == 1); ++bsteps, turn = 0; } assert(asteps == bsteps); P l(a.x - asteps, y), r(a.x + asteps, y); path.push_back(turn == 0 ? infleftup(l) : infleftdown(l)); path.push_back(l); if (l.x != r.x || l.y != r.y) path.push_back(r); path.push_back(turn == 0 ? infrightup(r) : infrightdown(r)); } else { P l(a.x + d.x - bsteps - (turn == 0 ? 0 : 1), y), r(a.x + asteps + (turn == 0 ? 1 : 0), y); path.push_back(infleftup(l)); path.push_back(l); path.push_back(r); path.push_back(infrightdown(r)); } pol = cutabove(pol, path); while (nflip % 2 != 0) flip(pol), flip(a), flip(b), ++nflip; while (nrot % 4 != 0) rotate(pol), rotate(a), rotate(b), ++nrot; return pol; } int sum(int a, int b) { return (long long)(a + b) * (b - a + 1) / 2 % MOD; } int sumsq(int a, int b) { return ((long long)2 * a * a + (long long)2 * b * b + (long long)2 * a * b + b - a) % MOD * (b - a + 1) % MOD * INV6 % MOD; } int calcsum(const P &l, const P &r, int delta) { int y = l.y % MOD; if (y < 0) y += MOD; int x = l.x % MOD; if (x < 0) x += MOD; if (delta == 0) { return (long long)sum(l.x, r.x) * y % MOD; } else if (delta == 1) { return ((long long)sum(l.x, r.x) * (y + MOD - x) + sumsq(l.x, r.x)) % MOD; } else if (delta == -1) { return ((long long)sum(l.x, r.x) * (y + x) + MOD - sumsq(l.x, r.x)) % MOD; } else { assert(false); } } int xcalc(Pol pol) { int ret = 0; if (((int)(pol.p).size()) >= 2) for (int i = (0); i < (((int)(pol.p).size())); ++i) { P a = pol.p[i], b = pol.p[(i + 1) % ((int)(pol.p).size())], c = pol.p[(i + 2) % ((int)(pol.p).size())], d = pol.p[(i + 3) % ((int)(pol.p).size())]; int pdir = getdir(a, b), cdir = getdir(b, c), ndir = getdir(c, d); int sgn, delta; P l, r; bool includefirst, includelast; if (cdir < 4) { includefirst = pdir < 3 || pdir >= cdir + 4, includelast = cdir != 3 && ndir >= 4 && ndir <= cdir + 4; if (cdir == 3) { sgn = includefirst ? +1 : 0, delta = 0, l = r = b; ++l.y, ++r.y; } else { sgn = +1, delta = getdelta(b, c); l = b, r = c; ++l.y, ++r.y; if (!includefirst) ++l.x, l.y += delta; if (!includelast) --r.x, r.y -= delta; } } else { includefirst = pdir != 7 && pdir >= cdir - 4, includelast = cdir != 7 && ndir <= cdir - 4; if (cdir == 7) { sgn = includefirst ? -1 : 0, delta = 0, l = r = b; } else { sgn = -1, delta = getdelta(c, b), l = c, r = b; if (!includefirst) --r.x, r.y -= delta; if (!includelast) ++l.x, l.y += delta; } } int cur = sgn != 0 && l.x <= r.x ? calcsum(l, r, delta) : 0; if (sgn == +1) ret = (ret + cur) % MOD; else ret = (ret + MOD - cur) % MOD; } if (((int)(pol.p).size()) == 1) ret = (ret + pol.p[0].x) % MOD; return ret; } Pol cutbelow(Pol pol, vector<P> path) { for (int rep = (0); rep < (2); ++rep) { rotate(pol); for (int i = (0); i < (((int)(path).size())); ++i) rotate(path[i]); } reverse(path.begin(), path.end()); pol = cutabove(pol, path); for (int rep = (0); rep < (2); ++rep) { rotate(pol); for (int i = (0); i < (((int)(path).size())); ++i) rotate(path[i]); } reverse(path.begin(), path.end()); return pol; } int calc(Pol pol) { int ret = 0; for (int rep = (0); rep < (4); ++rep) { vector<P> upath; upath.push_back(infleftdown(P(0, 0))); upath.push_back(infrightup(P(0, 0))); vector<P> lpath; lpath.push_back(P(MINCOORD, 0)); lpath.push_back(P(1, 0)); lpath.push_back(infrightdown(P(1, 0))); Pol cpol = cutbelow(cutabove(pol, upath), lpath); ret = (ret + xcalc(cpol)) % MOD; rotate(pol); } return ret; } int solve() { if (tlast == 0) return 0; int ret = 0; for (int i = (0); i < (ntree); ++i) { Pol pol; pol.p.push_back(P(t[i].x - tlast, t[i].y + tlast)); pol.p.push_back(P(t[i].x + tlast, t[i].y + tlast)); pol.p.push_back(P(t[i].x + tlast, t[i].y - tlast)); pol.p.push_back(P(t[i].x - tlast, t[i].y - tlast)); for (int j = (0); j < (ntree); ++j) if (j != i) { pol = cut(pol, t[i], t[j], i < j); } for (int k = (0); k < (((int)(pol.p).size())); ++k) pol.p[k] = pol.p[k] - t[i]; ret = (ret + calc(pol)) % MOD; } return ret; } void run() { scanf( %d%d , &ntree, &tlast); for (int i = (0); i < (ntree); ++i) scanf( %d%d , &t[i].x, &t[i].y); printf( %d n , solve()); } int solvestupid() { int lx = INT_MAX, hx = INT_MIN, ly = INT_MAX, hy = INT_MIN; for (int i = (0); i < (ntree); ++i) lx = min(lx, t[i].x - tlast), hx = max(hx, t[i].x + tlast), ly = min(ly, t[i].y - tlast), hy = max(hy, t[i].y + tlast); vector<vector<int>> d(hx - lx + 1, vector<int>(hy - ly + 1, INT_MAX)); for (int i = (0); i < (ntree); ++i) for (int x = (t[i].x - tlast); x <= (t[i].x + tlast); ++x) for (int y = (t[i].y - tlast); y <= (t[i].y + tlast); ++y) { int &v = d[x - lx][y - ly]; v = min(v, max(abs(x - t[i].x), abs(y - t[i].y))); } int ret = 0; for (int x = (lx); x <= (hx); ++x) for (int y = (ly); y <= (hy); ++y) { int v = d[x - lx][y - ly]; if (v != INT_MAX) ret += v; } return ret; } void stress() { mt19937 rnd(12344); int mxn = 100, mxt = 100, mncoord = 0, mxcoord = 100; for (int rep = (0); rep < (100000); ++rep) { ntree = rnd() % mxn + 1; tlast = rnd() % (mxt + 1); set<pair<int, int>> seen; for (int i = (0); i < (ntree); ++i) while (true) { t[i].x = rnd() % (mxcoord - mncoord + 1) + mncoord, t[i].y = rnd() % (mxcoord - mncoord + 1) + mncoord; if (seen.count(make_pair(t[i].x, t[i].y))) continue; seen.insert(make_pair(t[i].x, t[i].y)); break; } int have = solve(); int want = solvestupid(); if (have == want) { if (rep % 100 == 99) printf( . ); continue; } puts( ); printf( %d %d n , ntree, tlast); for (int i = (0); i < (ntree); ++i) printf( %d %d n , t[i].x, t[i].y); printf( err have=%d want=%d n , have, want); break; } } int main() { run(); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLXBP_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__DLXBP_PP_BLACKBOX_V
/**
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlxbp (
Q ,
Q_N ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLXBP_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR3_1_V
`define SKY130_FD_SC_HD__NOR3_1_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog wrapper for nor3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nor3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nor3_1 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nor3_1 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR3_1_V
|
#include <bits/stdc++.h> using namespace std; const int N = 150000; const int L = 19; vector<int> edges[N]; long long x[N], y[N]; int anc[N][L], tin[N], tout[N], s[N], moment; void dfs(int x, int last) { tin[x] = ++moment; anc[x][0] = last; for (int i = 1; i < L; i++) anc[x][i] = anc[anc[x][i - 1]][i - 1]; for (int i = 0; i < edges[x].size(); i++) if (edges[x][i] != last) dfs(edges[x][i], x); tout[x] = ++moment; } long long coef(int i, int j, int k) { long long a = y[i] - y[j], b = x[j] - x[i], c = x[i] * y[j] - x[j] * y[i]; return (a * x[k] + b * y[k] + c); } bool father(int x, int y) { return (tin[x] <= tin[y] && tout[y] <= tout[x]); } int lca(int a, int b) { if (father(a, b)) return a; if (father(b, a)) return b; for (int i = L - 1; i >= 0; i--) if (!father(anc[a][i], b)) a = anc[a][i]; return anc[a][0]; } int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %I64d %I64d , &x[i], &y[i]); int cnt = 1; s[cnt] = n; for (int i = n - 1; i >= 1; i--) { s[++cnt] = i; while (cnt > 2 && coef(s[cnt], s[cnt - 2], s[cnt - 1]) < 0) swap(s[cnt - 1], s[cnt]), cnt--; edges[s[cnt]].push_back(s[cnt - 1]); edges[s[cnt - 1]].push_back(s[cnt]); } moment = 0, dfs(n, n); int quests; scanf( %d , &quests); for (int i = 1; i <= quests; i++) { int x, y; scanf( %d %d , &x, &y); printf( %d , lca(x, y)); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLRBN_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__DLRBN_PP_BLACKBOX_V
/**
* dlrbn: Delay latch, inverted reset, inverted enable,
* complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlrbn (
Q ,
Q_N ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLRBN_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int arr[100005]; int lfl[100005]; int rfl[100005]; int main() { int n; cin >> n; int i, j; for (i = 1; i <= n; i++) { cin >> arr[i]; } for (i = 1; i <= n; i++) { lfl[i] = min(lfl[i - 1] + 1, arr[i]); } long long ans = INT_MIN; for (i = n; i >= 1; i--) { rfl[i] = min(rfl[i + 1] + 1, arr[i]); ans = (long long)max(ans, (long long)min(lfl[i], rfl[i])); } cout << ans << endl; return 0; } |
module avr_interface #(
parameter CLK_RATE = 50000000,
parameter SERIAL_BAUD_RATE = 500000
)(
input clk,
input rst,
// cclk, or configuration clock is used when the FPGA is begin configured.
// The AVR will hold cclk high when it has finished initializing.
// It is important not to drive the lines connecting to the AVR
// until cclk is high for a short period of time to avoid contention.
input cclk,
// AVR SPI Signals
output spi_miso,
input spi_mosi,
input spi_sck,
input spi_ss,
output [3:0] spi_channel,
// AVR Serial Signals
output tx,
input rx,
// ADC Interface Signals
input [3:0] channel,
output new_sample,
output [9:0] sample,
output [3:0] sample_channel,
// Serial TX User Interface
input [7:0] tx_data,
input new_tx_data,
output tx_busy,
input tx_block,
// Serial Rx User Interface
output [7:0] rx_data,
output new_rx_data
);
wire ready;
wire n_rdy = !ready;
wire spi_done;
wire [7:0] spi_dout;
wire tx_m;
wire spi_miso_m;
reg byte_ct_d, byte_ct_q;
reg [9:0] sample_d, sample_q;
reg new_sample_d, new_sample_q;
reg [3:0] sample_channel_d, sample_channel_q;
reg [3:0] block_d, block_q;
reg busy_d, busy_q;
// cclk_detector is used to detect when cclk is high signaling when
// the AVR is ready
cclk_detector #(.CLK_RATE(CLK_RATE)) cclk_detector (
.clk(clk),
.rst(rst),
.cclk(cclk),
.ready(ready)
);
spi_slave spi_slave (
.clk(clk),
.rst(n_rdy),
.ss(spi_ss),
.mosi(spi_mosi),
.miso(spi_miso_m),
.sck(spi_sck),
.done(spi_done),
.din(8'hff),
.dout(spi_dout)
);
// CLK_PER_BIT is the number of cycles each 'bit' lasts for
// rtoi converts a 'real' number to an 'integer'
localparam CLK_PER_BIT = 100; //$rtoi($ceil(CLK_RATE/SERIAL_BAUD_RATE));
serial_rx #(.CLK_PER_BIT(CLK_PER_BIT)) serial_rx (
.clk(clk),
.rst(n_rdy),
.rx(rx),
.data(rx_data),
.new_data(new_rx_data)
);
serial_tx #(.CLK_PER_BIT(CLK_PER_BIT)) serial_tx (
.clk(clk),
.rst(n_rdy),
.tx(tx_m),
.block(busy_q),
.busy(tx_busy),
.data(tx_data),
.new_data(new_tx_data)
);
// Output declarations
assign new_sample = new_sample_q;
assign sample = sample_q;
assign sample_channel = sample_channel_q;
// these signals connect to the AVR and should be Z when the AVR isn't ready
assign spi_channel = ready ? channel : 4'bZZZZ;
assign spi_miso = ready && !spi_ss ? spi_miso_m : 1'bZ;
assign tx = ready ? tx_m : 1'bZ;
always @(*) begin
byte_ct_d = byte_ct_q;
sample_d = sample_q;
new_sample_d = 1'b0;
sample_channel_d = sample_channel_q;
busy_d = busy_q;
block_d = {block_q[2:0], tx_block};
if (block_q[3] ^ block_q[2])
busy_d = 1'b0;
if (!tx_busy && new_tx_data)
busy_d = 1'b1;
if (spi_ss) begin // device is not selected
byte_ct_d = 1'b0;
end
if (spi_done) begin // sent/received data from SPI
if (byte_ct_q == 1'b0) begin
sample_d[7:0] = spi_dout; // first byte is the 8 LSB of the sample
byte_ct_d = 1'b1;
end else begin
sample_d[9:8] = spi_dout[1:0]; // second byte is the channel 2 MSB of the sample
sample_channel_d = spi_dout[7:4]; // and the channel that was sampled
byte_ct_d = 1'b1; // slave-select must be brought high before the next transfer
new_sample_d = 1'b1;
end
end
end
always @(posedge clk) begin
if (n_rdy) begin
byte_ct_q <= 1'b0;
sample_q <= 10'b0;
new_sample_q <= 1'b0;
end else begin
byte_ct_q <= byte_ct_d;
sample_q <= sample_d;
new_sample_q <= new_sample_d;
end
block_q <= block_d;
busy_q <= busy_d;
sample_channel_q <= sample_channel_d;
end
endmodule
|
#include <bits/stdc++.h> long long Max(const long long x, const long long y) { if (x > y) return x; return y; } const long long mo = 1e9 + 7, M = 1005; char s[M]; long long k, a[M], len, dp[M][M][2]; long long dfs(const long long pos, const long long dis, const bool pd, const bool lim) { if (!pos) return pd; if (!lim && ~dp[pos][dis][pd]) return dp[pos][dis][pd]; long long res = 0, up = lim ? a[pos] : 9; for (long long i = 0; i <= up; ++i) if (i != 4 && i != 7) res = (res + dfs(pos - 1, Max(dis - 1, 0), pd, lim && i == up)) % mo; else res = (res + dfs(pos - 1, k, dis || pd, lim && i == up)) % mo; if (!lim) dp[pos][dis][pd] = res; return res; } long long check() { long long last = 0x3f3f3f3f; for (long long i = len; i; --i) if (a[i] == 4 || a[i] == 7) { if (last - i <= k) return 1; last = i; } return 0; } signed main() { memset(dp, -1, sizeof dp); long long T; scanf( %lld%lld , &T, &k); while (T--) { scanf( %s , s); len = strlen(s); for (long long i = 0; i < len; ++i) a[len - i] = s[i] ^ 48; long long ans = (dfs(len, 0, 0, 1) - check() + mo) % mo; scanf( %s , s); len = strlen(s); for (long long i = 0; i < len; ++i) a[len - i] = s[i] ^ 48; ans = (dfs(len, 0, 0, 1) - ans + mo) % mo; printf( %lld n , ans); } return 0; } |
#include <bits/stdc++.h> using namespace std; void solve() {} const int maxn = (int)1e6 + 420; const int MOD = (int)1e9 + 7; int n; int dp[maxn][4][4]; void contr() { cout << 0 << n ; exit(0); } int madd(int a, int b) { long long sum = a + b; sum %= MOD; return sum; } signed main() { ios::sync_with_stdio(0); cin.tie(0); string s; cin >> s; n = (int)s.size(); s = . + s; dp[0][0][0] = 1; for (int i = 1; i <= n; i++) { for (int l = 0; l <= 3; l++) { for (int m = 0; m <= 3; m++) { for (int r = 0; r <= 3; r++) { if ((i == 1) and !(l == 0 and m == 0)) continue; if ((i == 2) and !(l == 0)) continue; bool ok = true; if (i >= 2) { if (m == 0 and (l == 3 or r == 3)) { ok = false; continue; } if (m == 1 and !(l == 3 ^ r == 3)) { ok = false; continue; } if (m == 2 and (l != 3 or r != 3)) { ok = false; continue; } } if (r == 0 and m == 3) { ok = false; continue; } if (r == 2 and m != 3) { ok = false; continue; } if (r == 1 and i == n and m != 3) { ok = false; continue; } if (r == 2 and i == n) { ok = false; continue; } vector<int> v = {r, m, l}; for (int j = 0; j < 3; j++) { if (s[i - j] == ? ) continue; if (i - j < 1) continue; if ((v[j] == 3)) { if (s[i - j] != * ) { ok = false; continue; } } else if (s[i - j] - 0 != v[j]) { ok = false; continue; } } if (ok) { dp[i][m][r] = madd(dp[i][m][r], dp[i - 1][l][m]); } } } } } int ans = 0; for (int i = 0; i <= 3; i++) { for (int j = 0; j <= 3; j++) { ans = madd(ans, dp[n][i][j]); } } cout << ans << n ; } |
`define bsg_nor3_macro(bits) \
if (harden_p && (width_p==bits)) \
begin: macro \
bsg_rp_tsmc_250_NOR3X1_b``bits nor3_gate (.i0(a_i),.i1(b_i),.i2(c_i),.o); \
end
module bsg_nor3 #(parameter `BSG_INV_PARAM(width_p)
, parameter harden_p=0
)
(input [width_p-1:0] a_i
, input [width_p-1:0] b_i
, input [width_p-1:0] c_i
, output [width_p-1:0] o
);
`bsg_nor3_macro(34) else
`bsg_nor3_macro(33) else
`bsg_nor3_macro(32) else
`bsg_nor3_macro(31) else
`bsg_nor3_macro(30) else
`bsg_nor3_macro(29) else
`bsg_nor3_macro(28) else
`bsg_nor3_macro(27) else
`bsg_nor3_macro(26) else
`bsg_nor3_macro(25) else
`bsg_nor3_macro(24) else
`bsg_nor3_macro(23) else
`bsg_nor3_macro(22) else
`bsg_nor3_macro(21) else
`bsg_nor3_macro(20) else
`bsg_nor3_macro(19) else
`bsg_nor3_macro(18) else
`bsg_nor3_macro(17) else
`bsg_nor3_macro(16) else
`bsg_nor3_macro(15) else
`bsg_nor3_macro(14) else
`bsg_nor3_macro(13) else
`bsg_nor3_macro(12) else
`bsg_nor3_macro(11) else
`bsg_nor3_macro(10) else
`bsg_nor3_macro(9) else
`bsg_nor3_macro(8) else
`bsg_nor3_macro(7) else
`bsg_nor3_macro(6) else
`bsg_nor3_macro(5) else
`bsg_nor3_macro(4) else
`bsg_nor3_macro(3) else
`bsg_nor3_macro(2) else
`bsg_nor3_macro(1) else
begin :notmacro
initial assert(harden_p==0) else $error("## %m wanted to harden but no macro");
assign o = ~(a_i | b_i | c_i);
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_nor3)
|
#include <bits/stdc++.h> struct Seg { int l; int r; int y; }; struct Event { int x; enum { BEG, END } type; Seg seg; static Event beginOf(Seg seg) { return Event{seg.l, BEG, seg}; } static Event endOf(Seg seg) { return Event{seg.r, END, seg}; } friend bool operator<(const Event& a, const Event& b) { return std::tie(a.x, a.type, a.seg.y) < std::tie(b.x, b.type, b.seg.y); } }; int main() { int sx, sy; std::cin >> sy >> sx; std::vector<Event> events; events.reserve(sy * sx); for (int y = 0; y < sy; y++) { int intervals; std::cin >> intervals; for (int i = 0; i < intervals; i++) { int l, r; std::cin >> l >> r; Seg seg{l - 1, r, y}; events.push_back(Event::beginOf(seg)); events.push_back(Event::endOf(seg)); } } std::sort(events.begin(), events.end()); std::vector<std::vector<int>> dp(sx + 1, std::vector<int>(sx + 1, 0)); for (int len = 1; len <= sx; len++) { for (int l = 0, r = len; r <= sx; l++, r++) { int currHeight = 0; auto currEv = events.begin(); for (int x = l; x < r; x++) { for (; currEv != events.end() && currEv->x <= x; ++currEv) { if (l <= currEv->seg.l && currEv->seg.r <= r) { if (currEv->type == Event::BEG) currHeight++; else currHeight--; } } dp[l][r] = std::max(dp[l][r], dp[l][x] + dp[x + 1][r] + currHeight * currHeight); } } } std::cout << dp[0][sx] << std::endl; } |
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2013, University of British Columbia (UBC); All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// mpram_gen.v: Generic multiported-RAM; Old data will be read in case of RAW. //
// //
// Author: Ameer M. Abdelhadi (, ) //
// SRAM-based Multi-ported RAMs; University of British Columbia (UBC), March 2013 //
////////////////////////////////////////////////////////////////////////////////////
`include "utils.vh"
module mpram_gen
#( parameter MEMD = 16, // memory depth
parameter DATAW = 32, // data width
parameter nRPORTS = 3 , // number of reading ports
parameter nWPORTS = 2 , // number of writing ports
parameter IZERO = 0 , // binary / Initial RAM with zeros (has priority over INITFILE)
parameter IFILE = "" // initialization hex file (don't pass extension), optional
)( input clk , // clock
input [nWPORTS-1:0 ] WEnb , // write enable for each writing port
input [`log2(MEMD)*nWPORTS-1:0] WAddr, // write addresses - packed from nWPORTS write ports
input [DATAW *nWPORTS-1:0] WData, // write data - packed from nRPORTS read ports
input [`log2(MEMD)*nRPORTS-1:0] RAddr, // read addresses - packed from nRPORTS read ports
output reg [DATAW *nRPORTS-1:0] RData // read data - packed from nRPORTS read ports
);
localparam ADDRW = `log2(MEMD); // address width
integer i;
// initialize RAM, with zeros if IZERO or file if IFLE.
reg [DATAW-1:0] mem [0:MEMD-1]; // memory array
initial
if (IZERO)
for (i=0; i<MEMD; i=i+1) mem[i] = {DATAW{1'b0}};
else
if (IFILE != "") $readmemh({IFILE,".hex"}, mem);
always @(posedge clk) begin
// write to nWPORTS ports; nonblocking statement to read old data
for (i=1; i<=nWPORTS; i=i+1)
if (WEnb[i-1]) mem[WAddr[i*ADDRW-1 -: ADDRW]] <= WData[i*DATAW-1 -: DATAW]; // Change into blocking statement (=) to read new data
// Read from nRPORTS ports; nonblocking statement to read old data
for (i=1; i<=nRPORTS; i=i+1)
RData[i*DATAW-1 -: DATAW] <= mem[RAddr[i*ADDRW-1 -: ADDRW]]; //Change into blocking statement (=) to read new data
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAP_1_V
`define SKY130_FD_SC_MS__TAP_1_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Verilog wrapper for tap with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__tap.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__tap_1 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__tap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__tap_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__tap base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAP_1_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:04:55 07/15/2014
// Design Name: cic_decim
// Module Name: U:/GitHubA2300_ltxdev/hdl/test/cic_decim_stimulus.v
// Project Name: Asr2300FpgaCore_2chrx
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: cic_decim
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module cic_decim_stimulus;
parameter DSPCLK_PERIOD = 1000.0/128.0; //128 MHz
// Inputs
reg sclr;
wire nd;
reg reset;
reg dspclk;
reg rate_we;
reg [11:0] din;
reg [12:0] rate;
// Outputs
wire rfd;
wire rdy;
wire [15:0] dout;
//create 32 MHz strobed
reg [1:0] strobe_nd;
always @(posedge dspclk)
begin
if(reset) strobe_nd <= 4'h0;
else strobe_nd <= strobe_nd + 4'h1;
end
assign nd = strobe_nd == 0;
// Instantiate the Unit Under Test (UUT)
cic_decim uut (
.sclr(sclr | reset),
.rfd(rfd),
.rdy(rdy),
.nd(nd),
.clk(dspclk),
.rate_we(rate_we),
.dout(dout),
.din(din),
.rate(rate)
);
initial begin
// Initialize Inputs
sclr = 0;
dspclk = 1;
rate_we = 0;
din = 12'h010;
rate = 12'h4;
// Wait 100 ns for global reset to finish
#100 reset = 1;
#(DSPCLK_PERIOD*4)reset = 0;
#(DSPCLK_PERIOD) rate_we = 1;
#(DSPCLK_PERIOD) rate_we = 0;
#(DSPCLK_PERIOD*120) sclr = 1;
#(DSPCLK_PERIOD) sclr = 0;
#(DSPCLK_PERIOD*64) rate_we = 1;
#(DSPCLK_PERIOD) rate_we = 0;
// Add stimulus here
#(DSPCLK_PERIOD*75) rate_we = 1;
#(DSPCLK_PERIOD) rate_we = 0;
end
//////////////////////////////////////////////////////////////////////
// Clocks
//////////////////////////////////////////////////////////////////////
always @(dspclk)
#(DSPCLK_PERIOD / 2.0) dspclk<= !dspclk;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EBUFN_BLACKBOX_V
`define SKY130_FD_SC_HS__EBUFN_BLACKBOX_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__ebufn (
A ,
TE_B,
Z
);
input A ;
input TE_B;
output Z ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__EBUFN_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int mxn = 257; string rec[mxn][3]; bool been[mxn][3]; inline int G(string s) { int t = 0; for (int i = 0; i < s.size(); ++i) t = t * 2 + s[i] - 0 ; return t; } priority_queue<pair<int, int> > pq; bool changed; string Min(string a, string b) { if (a.size() != b.size()) { if (a.size() < b.size()) return a; else return b; } return min(a, b); } inline void upd(string& a, string b) { if (a == b) return; if (Min(a, b) == b) { changed = 1; a = b; } } inline void prep() { int n = 256; for (int i = 0; i < n; ++i) for (int j = 0; j < 3; ++j) rec[i][j] = zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz ; rec[G( 00001111 )][0] = x ; rec[G( 00110011 )][0] = y ; rec[G( 01010101 )][0] = z ; for (changed = 1; changed;) { changed = 0; for (int i = 0; i < n; ++i) for (int j = 0; j < 2; ++j) upd(rec[i][j + 1], rec[i][j]); for (int i = 0; i < n; ++i) upd(rec[i ^ 255][0], ! + rec[i][0]); for (int i = 0; i < n; ++i) for (int j = 0; j < n; ++j) upd(rec[i & j][1], rec[i][1] + & + rec[j][0]), upd(rec[i | j][2], rec[i][2] + | + rec[j][1]); for (int i = 0; i < n; ++i) upd(rec[i][0], ( + rec[i][2] + ) ); } } int main() { ios_base::sync_with_stdio(false); cin.tie(0), cout.tie(0); int T = 1; cin >> T; prep(); for (; T--;) { string s; cin >> s; int t = G(s); cout << Min(Min(rec[t][0], rec[t][1]), rec[t][2]) << n ; } } |
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_Sys_sw (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input [ 3: 0] in_port;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 3: 0] d1_data_in;
reg [ 3: 0] d2_data_in;
wire [ 3: 0] data_in;
reg [ 3: 0] edge_capture;
wire edge_capture_wr_strobe;
wire [ 3: 0] edge_detect;
wire irq;
reg [ 3: 0] irq_mask;
wire [ 3: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({4 {(address == 0)}} & data_in) |
({4 {(address == 2)}} & irq_mask) |
({4 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2))
irq_mask <= writedata[3 : 0];
end
assign irq = |(edge_capture & irq_mask);
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[0] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[0] <= 0;
else if (edge_detect[0])
edge_capture[0] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[1] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[1] <= 0;
else if (edge_detect[1])
edge_capture[1] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[2] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[2] <= 0;
else if (edge_detect[2])
edge_capture[2] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[3] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[3] <= 0;
else if (edge_detect[3])
edge_capture[3] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_data_in <= 0;
d2_data_in <= 0;
end
else if (clk_en)
begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = d1_data_in ^ d2_data_in;
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> v[200010], circle; int fa[200010], dep[200010], a[200010], b[200010], n, rt, vs, vt, h1, h2; bool vis[200010], bo[200010]; inline int rd() { int x = 0; char ch = getchar(); for (; ch < 0 || ch > 9 ; ch = getchar()) ; for (; ch >= 0 && ch <= 9 ; ch = getchar()) x = x * 10 + ch - 0 ; return x; } inline void dfs(int x) { for (int i = 0, siz = v[x].size(); i < siz; i++) { int t = v[x][i]; if (t == fa[x]) continue; dep[t] = dep[x] + 1; fa[t] = x; dfs(t); } } inline bool gao() { int p = 0, q = 0; bool flag = true; for (int i = 1; i <= n; i++) if (a[i] != b[i] && dep[i] > dep[p]) p = i; if (!p) return true; for (int hh = p; a[hh] != b[hh]; hh = fa[hh]) bo[hh] = true, circle.push_back(hh); for (int i = 1; i <= n; i++) if (a[i] != b[i] && !bo[i] && dep[i] > dep[q]) q = i; if (q) { reverse(circle.begin(), circle.end()); flag = false; for (int hh = q; a[hh] != b[hh]; hh = fa[hh]) bo[hh] = true, circle.push_back(hh); } else q = fa[circle.back()]; for (int i = 1; i <= n; i++) if (a[i] != b[i] && !bo[i]) return false; int h1 = p, h2 = q; for (; h1 != h2; h1 = fa[h1]) if (dep[h1] < dep[h2]) swap(h1, h2); rt = h1; if (circle.size() != dep[p] + dep[q] - dep[rt] * 2) return false; vs = p; vt = q; if (flag) reverse(circle.begin(), circle.end()); return true; } int main() { n = rd(); for (int i = 1; i <= n; i++) if (!(a[i] = rd())) h1 = i; for (int i = 1; i <= n; i++) if (!(b[i] = rd())) h2 = i; for (int i = 1; i < n; i++) { int x = rd(), y = rd(); v[x].push_back(y); v[y].push_back(x); } dep[0] = -1; dfs(h2); for (int hh = h1; hh != h2; hh = fa[hh]) swap(a[hh], a[fa[hh]]); long long ans = dep[h1]; if (!gao()) { puts( -1 ); return 0; } if (!circle.size()) { printf( 0 %d n , ans); return 0; } for (int i = h1; i; i = fa[i]) vis[i] = true; if (vis[circle.back()] && !vis[circle[0]]) reverse(circle.begin(), circle.end()); int gap = 0, siz = circle.size(); for (int i = 0; i < siz; i++) if (b[circle[i]] == a[circle[0]]) gap = i; for (int i = 0; i < siz; i++) if (b[circle[(i + gap) % siz]] != a[circle[i]]) { puts( -1 ); return 0; } if (vis[circle[0]] || vis[circle.back()]) { int now = siz; for (int i = 0; i < siz; i++) if (!vis[circle[i]]) { now = i; break; } ans = ans - now + min((long long)gap * (siz + 1) + now, abs((long long)(siz - gap) * (siz + 1) - now)); } else ans = (ans + (long long)min(gap, siz - gap) * (siz + 1)); for (; !vis[rt]; rt = fa[rt]) ans += 2; if (vs > vt) swap(vs, vt); printf( %d %d %I64d n , vs, vt, ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; const int mod = 1000000007; const long long linf = 0x3f3f3f3f3f3f3f3f; char c[200100]; int qnt[200100][26]; int main() { int t; scanf( %d , &t); while (t--) { int n, k; scanf( %d%d , &n, &k); scanf( %s , c); int m = n / k; int res = 0; if (k % 2) { for (int i = 0; i <= k / 2; i++) { for (int j = 0; j < m; j++) { int a = i + j * k; int b = k - 1 - i + j * k; qnt[i][c[a] - a ]++; qnt[i][c[b] - a ]++; } } for (int i = 0; i < k / 2; i++) { int maior = 0; for (int j = 0; j < 26; j++) maior = max(maior, qnt[i][j]); res += 2 * m - maior; } int maior = 0; for (int j = 0; j < 26; j++) maior = max(maior, qnt[k / 2][j]); res += (2 * m - maior) / 2; } else { for (int i = 0; i < k / 2; i++) { for (int j = 0; j < m; j++) { int a = i + j * k; int b = k - 1 - i + j * k; qnt[i][c[a] - a ]++; qnt[i][c[b] - a ]++; } } for (int i = 0; i < k / 2; i++) { int maior = 0; for (int j = 0; j < 26; j++) maior = max(maior, qnt[i][j]); res += 2 * m - maior; } } printf( %d n , res); for (int i = 0; i <= n; i++) { for (int j = 0; j < 26; j++) qnt[i][j] = 0; } } return 0; } |
#include <bits/stdc++.h> using namespace std; vector<pair<long long, long long> > vp, pp; int h[105][105]; int a[105], b[104]; int main() { int n, m, k; cin >> n >> m >> k; for (int i = 0; i < m; i++) cin >> a[i]; for (int i = 0; i < n; i++) cin >> b[i]; int x; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> h[i][j]; } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (h[i][j] == 1) h[i][j] = min(a[j], b[i]); } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cout << h[i][j] << ; } cout << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int k; cin >> k; int a[k + 1]; for (int i = 0; i < k; i++) cin >> a[i]; long long int comb[1005][1005]; comb[0][0] = 1; for (int i = 1; i < 1005; i++) { comb[i][0] = 1; for (int j = 1; j <= i; j++) { comb[i][j] = (comb[i - 1][j] + comb[i - 1][j - 1]) % 1000000007; } } long long sum = 0, ans = 1; for (int i = 0; i < k; i++) { ans = (ans * comb[sum + a[i] - 1][a[i] - 1]) % 1000000007; sum += a[i]; } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 200005; vector<int> lk[maxn]; int fa[maxn], dep[maxn], a[maxn], b[maxn], n; void dfs(int now, int pre) { fa[now] = pre; dep[now] = dep[pre] + 1; for (auto p : lk[now]) if (p != pre) dfs(p, now); } vector<int> cir; int rt, lp, lq; bool find_circle() { cir.clear(); static bool vis[maxn]; int p = 0; for (int i = 1; i <= n; i++) if (a[i] != b[i] && dep[i] > dep[p]) p = i; if (!p) return 1; for (int u = p; vis[u] = 1, cir.push_back(u), a[fa[u]] != b[fa[u]]; u = fa[u]) ; int q = 0; for (int i = 1; i <= n; i++) if (a[i] != b[i] && !vis[i] && dep[i] > dep[q]) q = i; if (q) { reverse(cir.begin(), cir.end()); for (int u = q; vis[u] = 1, cir.push_back(u), a[fa[u]] != b[fa[u]]; u = fa[u]) ; } else q = fa[cir.back()]; for (int i = 1; i <= n; i++) if (a[i] != b[i] && !vis[i]) return 0; int u, v; for (u = p, v = q; u != v; u = fa[u]) if (dep[u] < dep[v]) swap(u, v); rt = u; if (cir.size() != dep[p] + dep[q] - 2 * dep[rt]) return 0; lp = p, lq = q; return 1; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int i = 1; i <= n; i++) scanf( %d , &b[i]); for (int i = 1, u, v; i < n; i++) { scanf( %d%d , &u, &v); lk[u].push_back(v), lk[v].push_back(u); } int pa = find(a + 1, a + n + 1, 0) - a, pb = find(b + 1, b + n + 1, 0) - b; dep[0] = -1; dfs(pb, 0); for (int u = pa; u != pb; u = fa[u]) swap(a[u], a[fa[u]]); long long ans = dep[pa]; if (!find_circle()) { printf( -1 n ); return 0; } if (!cir.size()) { printf( 0 %d n , ans); return 0; } int gap = 0, len = cir.size(); for (int i = 0; i < len; i++) if (b[cir[i]] == a[cir[0]]) gap = i; for (int i = 1; i < len; i++) if (b[cir[(i + gap) % len]] != a[cir[i]]) { printf( -1 n ); return 0; } static bool vis[maxn]; for (int i = pa; i; i = fa[i]) vis[i] = 1; if (vis[cir[0]] || vis[cir.back()]) { if (vis[cir.back()]) reverse(cir.begin(), cir.end()), gap = len - gap; int po = cir.size(); for (int i = 0; i < cir.size(); i++) if (!vis[cir[i]]) { po = i; break; } ans = ans - po + min(po + gap * 1ll * (len + 1), abs((len - gap) * 1ll * (len + 1) - po)); } else ans = (ans + min(gap, len - gap) * 1ll * (len + 1)); for (; !vis[rt]; rt = fa[rt]) ans += 2; if (lp > lq) swap(lq, lp); printf( %d %d %lld n , lp, lq, ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long MAX_N = 1e5 + 5; long long n, val; pair<pair<long long, long long>, pair<long long, long long> > edge[MAX_N]; long long par[MAX_N]; long long len[MAX_N]; vector<long long> h; vector<long long> ans; vector<pair<long long, long long> > G[MAX_N]; vector<long long> rot, ver; long long P[MAX_N]; long long down[MAX_N]; long long up[MAX_N]; bool mark[MAX_N]; long long root(long long v) { return (par[v] == v ? v : par[v] = root(par[v])); } void cheak(long long tmp, long long id) { if (val < tmp) { val = tmp; ans.clear(); } if (val == tmp) ans.push_back(id); } long long dfs1(long long v, long long p) { P[v] = p; down[v] = len[v]; mark[v] = true; for (pair<long long, long long> u : G[v]) if (!mark[u.first]) down[v] += dfs1(u.first, v); return down[v]; } void dfs2(long long v, long long uval) { up[v] = uval; for (pair<long long, long long> u : G[v]) if (u.first != P[v]) dfs2(u.first, uval + down[v] - down[u.first]); } void dfs3(long long v) { for (pair<long long, long long> u : G[v]) if (u.first != P[v]) { dfs3(u.first); cheak(up[u.first] * down[u.first], u.second); } } void calc() { for (long long id : h) { ver.push_back(root(edge[id].second.first)); ver.push_back(root(edge[id].second.second)); } sort(ver.begin(), ver.end()); ver.resize(unique(ver.begin(), ver.end()) - ver.begin()); for (long long id : h) { G[root(edge[id].second.first)].push_back( {root(edge[id].second.second), edge[id].first.second}); G[root(edge[id].second.second)].push_back( {root(edge[id].second.first), edge[id].first.second}); } for (long long v : ver) if (!mark[v]) { rot.push_back(v); dfs1(v, v); } for (long long v : rot) dfs2(v, 0); for (long long v : rot) dfs3(v); rot.clear(); for (long long v : ver) { G[v].clear(); mark[v] = false; } ver.clear(); } int main() { ios::sync_with_stdio(false), cin.tie(0); cin >> n; for (long long i = 0; i < n - 1; i++) { long long v, u, d; cin >> edge[i].second.first >> edge[i].second.second >> edge[i].first.first; edge[i].first.second = i + 1; edge[i].second.first--, edge[i].second.second--; } sort(edge, edge + n - 1); for (long long i = 0; i < n; i++) { par[i] = i; len[i] = 1; } h.push_back(0); for (long long i = 1; i < n - 1; i++) { if (edge[i].first.first != edge[i - 1].first.first) { calc(); for (long long id : h) { len[root(edge[id].second.second)] += len[root(edge[id].second.first)]; par[root(edge[id].second.first)] = root(edge[id].second.second); } h.clear(); } h.push_back(i); } calc(); cout << 2 * val << << ans.size() << n ; sort(ans.begin(), ans.end()); for (long long u : ans) cout << u << ; return 0; } |
#include <bits/stdc++.h> using namespace std; int flash_drives[100001]; int main() { int n, m; scanf( %d%d , &n, &m); for (int i = 0; i < n; i++) { scanf( %d , &flash_drives[i]); } sort(flash_drives, flash_drives + n, greater<int>()); int l = 0; int sum = 0; for (int i = 0; i < n; i++) { if (sum < m) { sum += flash_drives[i]; l++; } else break; } printf( %d n , l); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long MAXN = +100500; const long long INF = 4e18; long long a[MAXN]; int main() { long long n, k; cin >> n >> k; for (int i = 1; i <= n; i++) { cin >> a[i]; } if (k >= 3) { sort(a + 1, a + n + 1); cout << a[n]; return 0; } if (k == 1) { sort(a + 1, a + n + 1); cout << a[1]; return 0; } multiset<long long> b; multiset<long long> c; for (int i = 1; i <= n; i++) { c.insert(a[i]); } long long ans = -INF; long long pt = 1; while (pt < n) { b.insert(a[pt]); c.erase(c.equal_range(a[pt]).first); long long x = max(*c.begin(), *b.begin()); ans = max(ans, x); pt++; } cout << ans; } |
#include <bits/stdc++.h> using namespace std; int n; string s; vector<vector<int> > dp; vector<int> res; void recalc(char col) { dp = vector<vector<int> >(n + 1, vector<int>(n + 1, 0)); res = vector<int>(n, 0); for (int(i) = 0; (i) < (n + 1); ++(i)) dp[i][0] = 0; for (int(ncur) = (1); (ncur) < (n + 1); ++(ncur)) { for (int(mcur) = (0); (mcur) < (n + 1); ++(mcur)) { if (s[ncur - 1] == col) { dp[mcur][ncur] = dp[mcur][ncur - 1] + 1; continue; } if (mcur == 0) { dp[mcur][ncur] = 0; } else { dp[mcur][ncur] = dp[mcur - 1][ncur - 1] + 1; } } } for (int(i) = 0; (i) < (n); ++(i)) { for (int(j) = (1); (j) < (n + 1); ++(j)) { res[i] = max(res[i], dp[i + 1][j]); } } } void solve() { cin >> n; cin >> s; int q; cin >> q; vector<pair<pair<char, int>, int> > qrs(q); for (int(i) = 0; (i) < (q); ++(i)) { cin >> qrs[i].first.second >> qrs[i].first.first; qrs[i].second = i; } sort(qrs.begin(), qrs.end()); vector<pair<int, int> > ans(q); char lastcol = -1; for (int(i) = 0; (i) < (q); ++(i)) { char col = qrs[i].first.first; int m = qrs[i].first.second; if (col != lastcol) { lastcol = col; recalc(col); } ans[i].first = qrs[i].second; ans[i].second = res[m - 1]; } sort(ans.begin(), ans.end()); for (int(i) = 0; (i) < (q); ++(i)) cout << ans[i].second << endl; } int main() { ios_base::sync_with_stdio(false); solve(); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLRTP_4_V
`define SKY130_FD_SC_MS__DLRTP_4_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog wrapper for dlrtp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dlrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dlrtp_4 (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ms__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dlrtp_4 (
Q ,
RESET_B,
D ,
GATE
);
output Q ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLRTP_4_V
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#include <bits/stdc++.h> using namespace std; const double eps = 1e-8; const double pi = acos(-1.0); const long long INF = 0x3f3f3f3f3f3f3f3f; const int inf = 0x3f3f3f3f; const long long mod = 1e9 + 7; const int N = 1e5 + 10; struct zz { long long x, y; } a[N]; bool check(zz z1, zz z2, zz y1, zz y2) { if ((z1.y - z2.y) * (y1.x - y2.x) == (z1.x - z2.x) * (y1.y - y2.y)) return true; else return false; } long long dis(zz z1, zz z2) { return (z1.x - z2.x) * (z1.x - z2.x) + (z1.y - z2.y) * (z1.y - z2.y); } bool check(int n) { while (n % 2 == 0) { n /= 2; } if (n == 1) return true; else return false; } void solve() { int n; cin >> n; for (int i = 0; i < n; i++) { cin >> a[i].x >> a[i].y; } if (n & 1) { cout << NO << endl; return; } int flag = 1; for (int i = 0; i < n / 2; i++) { if (!check(a[i], a[i + 1], a[i + n / 2], a[(i + n / 2 + 1) % n])) { flag = 0; break; } } if (flag && n == 4) { cout << YES << endl; return; } long long r = dis(a[1], a[0]); for (int i = 0; i < n / 2; i++) { if (dis(a[i], a[(i + 1) % n]) != dis(a[i + n / 2], a[(i + n / 2 + 1) % n])) { flag = 0; break; } } if (flag) cout << Yes << endl; else cout << NO << endl; } int main() { ios::sync_with_stdio(false); int t = 1; while (t--) { solve(); } return 0; } |
/*
* This module demonstrates the ability to use a defparam to control
* the instantation of an instance array, and to also control
* parameter values within the instance array.
*/
module main;
localparam wid = 5;
reg [wid-1:0] clk;
if (wid > 0) begin : D
dut xx (.clk(clk));
end
// This defparam sets the desired with of the U instance vector.
defparam main.D.xx.wid = wid;
// These defparams set parameters within U instances.
defparam main.D.xx.sub[0].U.number = 0;
defparam main.D.xx.sub[1].U.number = 1;
defparam main.D.xx.sub[2].U.number = 2;
defparam main.D.xx.sub[3].U.number = 3;
defparam main.D.xx.sub[4].U.number = 4;
initial begin
clk = 0;
#1 clk = 1;
while (clk != 0)
#1 clk = clk << 1;
$finish(0);
end
endmodule // main
module dut #(parameter wid = 1) (input [wid-1:0] clk);
genvar i;
for (i = 0 ; i < wid ; i = i+1) begin : sub
target U (.clk(clk[i]));
end
endmodule //
module target(input wire clk);
parameter number = 999;
always @(posedge clk)
$display("%m: number=%0d", number);
endmodule // target
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