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#include <bits/stdc++.h> using namespace std; const int64_t N = 5e6 + 10; int64_t n, m; int64_t it[N]; bool hamband[N]; int64_t adj[N]; int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> m; if (m == (n - 1) * n >> 1) { cout << 0; return 0; } for (int64_t i = 0; i < m; i++) { int64_t x, y; cin >> x >> y; x--, y--; adj[x] += (1 << y); adj[y] += (1 << x); } hamband[0] = true; int64_t tow = 1; for (int64_t mask = 1; mask < (1 << n); mask++) { if (mask == tow) { hamband[mask] = true; tow <<= 1; continue; } for (int64_t now = mask; now;) { int64_t i = __builtin_ctz(now); if (hamband[mask ^ (1 << i)] && (adj[i] & mask)) { hamband[mask] = true; break; } now ^= (1 << i); } } int64_t ans = 0, Ans = 0; for (int64_t mask = 1; mask < (1 << n); mask++) { if (!hamband[mask]) { continue; } int64_t all = 0; for (int64_t now = mask; now; now ^= (1 << __builtin_ctz(now))) { all |= adj[__builtin_ctz(now)]; } if ((all & ((1 << n) - 1 - mask)) == ((1 << n) - 1 - mask)) { if (ans < n - __builtin_popcount(mask)) { ans = n - __builtin_popcount(mask); Ans = mask; } } } cout << n - ans << n ; for (int64_t i = 0; i < n; i++) { if (Ans & (1 << i)) { cout << i + 1 << ; } } }
|
#include <bits/stdc++.h> using namespace std; int n, m; const int N = 1005; char grid[N][N]; int visited[N][N]; bool row[N]; bool col[N]; int drow[] = {0, 0, -1, 1}; int dcol[] = {1, -1, 0, 0}; bool fullrow = false; bool fullcol = false; bool inside(int x, int y) { return (1 <= x && x <= n && 1 <= y && y <= m); } bool edge(int x, int y) { return (x == 1 || y == 1 || x == n || y == m); } void ngang() { for (int i = 1; i <= n; ++i) { int cnt = 0; for (int j = 1; j <= m; ++j) { if (grid[i][j] == # ) { if (grid[i][j - 1] != # ) ++cnt; } if (cnt > 1) { cout << -1; cerr << nngang ; exit(0); } } if (cnt == 0) { fullrow = true; } } } void doc() { for (int j = 1; j <= m; ++j) { int cnt = 0; for (int i = 1; i <= n; ++i) { if (grid[i][j] == # ) { if (grid[i - 1][j] != # ) ++cnt; } if (cnt > 1) { cout << -1; cerr << ndoc ; exit(0); } } if (cnt == 0) { fullcol = true; } } } void input() { cin >> n >> m; for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { cin >> grid[i][j]; } } } void dfs(int i, int j) { visited[i][j] = true; for (int d = 0; d <= 3; ++d) { int x = i + drow[d]; int y = j + dcol[d]; if (!inside(x, y)) continue; if (grid[x][y] == # ) { if (!visited[x][y]) dfs(x, y); } } } void solve() { ngang(); doc(); if (fullrow != fullcol) { cout << -1; return; } int ans = 0; for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { if (!visited[i][j] && grid[i][j] == # ) { dfs(i, j); ++ans; } } } cout << ans; } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); input(); solve(); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR3_2_V
`define SKY130_FD_SC_LP__OR3_2_V
/**
* or3: 3-input OR.
*
* Verilog wrapper for or3 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__or3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or3_2 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__or3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or3_2 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__or3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR3_2_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:01:49 01/04/2015
// Design Name:
// Module Name: neopixel_tx
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module neopixel_tx(
input wire clk,
input wire sys_rst,
//input wire mode,
//input wire tx_enable,
//input wire [24:0] dIn,
//input wire wr_en,
//output wire rgb_full_flg,
//output wire cmd_full_flg,
//output wire empty_flg,
output wire [4:0] ctrlLed,
output wire neo_tx_out
);
// connectors between FIFOs and TX_FSM
wire neoClk;
wire neo_msgTyp;
wire [23:0] neo_rgb;
wire neo_rdEn;
wire cmd_empty_flg;
wire rgb_empty_flg;
// connectors between microblaze and parts
wire empty_flg;
wire rst;
wire tx_enable;
wire mode;
wire mb_rst;
wire gpi_int;
wire wr_en;
wire cmd_dIn;
wire [23:0]rgb_dIn;
// microblaze for loading fifos
mojo_mb mojo_mb (
.Clk(clk),
.Reset(~sys_rst), // goes nowhere
.GPI1_Interrupt(gpi_int),
.GPI1({cmd_full_flg, rgb_full_flg}),
.GPO1({rst, wr_en, cmd_dIn, mode, tx_enable}),
.GPO2(rgb_dIn)
);
// 20MHz source
clk_wiz_v3_6 clk20MHz (
// Clock in ports
.clk(clk),
// Clock out ports
.clk_20MHz(neoClk)
);
// data FIFO (1024*3 bytes)
FIFO_WxD #(
24,
10)
neo_rgbFIFO (
.rst(rst),
.dataIn(rgb_dIn),
.wr_en(wr_en),
.rd_en(neo_rdEn),
.dataOut(neo_rgb),
.full_flg(rgb_full_flg),
.empty_flg(rgb_empty_flg)
);
// command bit FIFO (31 bits)
FIFO_WxD #(
1,
10)
neo_cmdFIFO (
.rst(rst),
.dataIn(cmd_dIn),
.wr_en(wr_en),
.rd_en(neo_rdEn),
.dataOut(neo_msgTyp),
.full_flg(cmd_full_flg),
.empty_flg(cmd_empty_flg)
);
// Neopixel Transmitter
neopixel_tx_fsm neo_tx(
.clk(neoClk),
.rst(rst),
.mode(mode),
.tx_enable(tx_enable),
.empty_flg(empty_flg),
.neo_dIn(neo_rgb),
.rgb_msgTyp(neo_msgTyp),
.rd_next(neo_rdEn),
.neo_tx_out(neo_tx_out)
);
// combine the two empty flags
assign empty_flg = cmd_empty_flg | rgb_empty_flg;
assign ctrlLed[0] = tx_enable;
assign ctrlLed[1] = mode;
assign ctrlLed[2] = cmd_dIn;
assign ctrlLed[3] = wr_en;
assign ctrlLed[4] = rst;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2007 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
supply0 [1:0] low;
supply1 [1:0] high;
reg [7:0] isizedwire;
reg ionewire;
wire oonewire;
wire [7:0] osizedreg; // From sub of t_inst_v2k_sub.v
t_inst sub
(
.osizedreg,
.oonewire,
// Inputs
.isizedwire (isizedwire[7:0]),
.*
//.ionewire (ionewire)
);
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
ionewire <= 1'b1;
isizedwire <= 8'd8;
end
if (cyc==2) begin
if (low != 2'b00) $stop;
if (high != 2'b11) $stop;
if (oonewire !== 1'b1) $stop;
if (isizedwire !== 8'd8) $stop;
end
if (cyc==3) begin
ionewire <= 1'b0;
isizedwire <= 8'd7;
end
if (cyc==4) begin
if (oonewire !== 1'b0) $stop;
if (isizedwire !== 8'd7) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module t_inst
(
output reg [7:0] osizedreg,
output wire oonewire /*verilator public*/,
input [7:0] isizedwire,
input wire ionewire
);
assign oonewire = ionewire;
always @* begin
osizedreg = isizedwire;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O211AI_1_V
`define SKY130_FD_SC_HDLL__O211AI_1_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog wrapper for o211ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o211ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o211ai_1 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__o211ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o211ai_1 (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__o211ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O211AI_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFXBP_TB_V
`define SKY130_FD_SC_HD__SDFXBP_TB_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__sdfxbp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SCD = 1'b0;
#60 SCE = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 D = 1'b1;
#180 SCD = 1'b1;
#200 SCE = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 D = 1'b0;
#320 SCD = 1'b0;
#340 SCE = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 SCE = 1'b1;
#540 SCD = 1'b1;
#560 D = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 SCE = 1'bx;
#680 SCD = 1'bx;
#700 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hd__sdfxbp dut (.D(D), .SCD(SCD), .SCE(SCE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFXBP_TB_V
|
#include <bits/stdc++.h> using namespace std; string proc(char *a) { int n = strlen(a); char s[100]; int i = 0, j = 0; while (i < n) { if (a[i] == u ) s[j++] = o , s[j++] = o ; else s[j++] = a[i]; i++; } s[j] = 0 ; strcpy(a, s); n = j; i = j = 0; while (i < n) { if (i < n - 1 && a[i] == a[i + 1] && a[i] == o ) s[j++] = u , i += 2; else s[j++] = a[i++]; } s[j] = 0 ; strcpy(a, s); n = j; i = j = 0; while (i < n) { int t = i; if (a[i] == k ) { while (a[i] == k && i < n) i++; if (a[i] == h ) s[j++] = h , i++; else { while (t < i) s[j++] = k , t++; s[j++] = a[i++]; } } else s[j++] = a[i++]; } s[j] = 0 ; return string(s); } int main() { int n; cin >> n; cin.ignore(); char a[1000][100]; vector<string> ret; for (int i = 0; i < n; i++) { cin.getline(a[i], 100); ret.push_back(proc(a[i])); } sort(ret.begin(), ret.end()); int ans = 0; int i = 0; while (i < n) { int t = i + 1; while (t < n && ret[i] == ret[t]) t++; ans++; i = t; } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 5e5 + 5; int n, f[N]; long long a[N], b[N], c[N]; int main() { cin >> n; for (int i = 1; i <= n; i++) { scanf( %I64d , a + i); a[n + 1] = 1; long long t = a[i]; while (t % 2 == 0) t /= 2, b[i]++; c[i] = t; } for (int i = 1; i <= n + 1; i++) { f[i] = i - 1; for (int j = 0; j <= i - 1; j++) { if (a[j] != 0 && a[i] % a[j] == 0 && i - j <= 50) { if (a[i] / a[j] == 1LL << (i - j)) { f[i] = min(f[i], f[j] + i - j - 1); } } if (a[i] % 2 == 0) { long long l = c[j], r = c[i]; int cl = b[j], cr = b[i]; if (l % r != 0) continue; if (cr > cl && cr - cl == i - j) { f[i] = min(f[j] + i - j - 1, f[i]); } if (cr - 1 + (cl > 0) <= i - j - 1) { f[i] = min(f[j] + i - j - 1, f[i]); } } if (a[i] % 2 == 1) if (a[j] % a[i] == 0) { f[i] = min(f[j] + i - j - 1, f[i]); continue; } } } cout << f[n + 1]; }
|
// File: BDCLed_TBV.v
// Generated by MyHDL 0.10
// Date: Mon Aug 20 12:45:05 2018
`timescale 1ns/10ps
module BDCLed_TBV (
);
// myHDL -> Verilog Testbench for `BDCLed`
reg clk = 0;
wire [1:0] sw;
reg [3:0] led = 0;
wire [7:0] BDCLed0_0_duty_led;
reg [7:0] BDCLed0_0_counter = 0;
assign sw = 2'd0;
assign BDCLed0_0_duty_led = 8'd8;
always @(led, sw, clk) begin: BDCLED_TBV_PRINT_DATA
$write("%h", sw);
$write(" ");
$write("%h", clk);
$write(" ");
$write("%h", led);
$write("\n");
end
always @(posedge clk) begin: BDCLED_TBV_BDCLED0_0_LOGIC
BDCLed0_0_counter <= (BDCLed0_0_counter + 1);
if ((BDCLed0_0_counter < BDCLed0_0_duty_led)) begin
led <= 15;
end
else begin
led <= 0;
end
end
initial begin: BDCLED_TBV_CLK_SIGNAL
while (1'b1) begin
clk <= (!clk);
# 1;
end
end
initial begin: BDCLED_TBV_STIMULES
integer i;
i = 0;
while (1'b1) begin
if ((i == 1000)) begin
$finish;
end
i = i + 1;
@(posedge clk);
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A41O_BEHAVIORAL_V
`define SKY130_FD_SC_HS__A41O_BEHAVIORAL_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a41o (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
// Local signals
wire A4 and0_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2, A3, A4 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A41O_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; vector<int> v, vv, vv2; int main() { long long t, n, a[1000], k, f = 0; cin >> n; string s; cin >> s; int cnt = 0; for (int i = 0; i < s.size() && cnt >= -1; i++) { if (s[i] == ( ) cnt++; else cnt--; } if (!cnt) cout << Yes << endl; else cout << No << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long modn = 1000000007; inline long long mod(long long x) { return x % modn; } int n; vector<int> v[30]; int qt[30]; int main() { int i, j; string s; cin >> s; n = s.size(); for (i = 0; i < n; i++) v[s[i] - a ].push_back(i); double ans = 0; for (i = 0; i < 26; i++) { if (v[i].empty()) continue; if (v[i].size() == 1) { ans += 1; continue; } if (v[i].size() == 2) { string t1 = s, t2 = s; rotate(t1.begin(), t1.begin() + v[i][0], t1.end()); rotate(t2.begin(), t2.begin() + v[i][1], t2.end()); if (t1 != t2) ans += 2; continue; } int mx = 0; for (j = 0; j < n; j++) { for (int k : v[i]) qt[s[(k + j) % n] - a ]++; int cur = 0; int k; for (k = 0; k < 26; k++) if (qt[k] == 1) cur++; mx = max(mx, cur); for (int k : v[i]) qt[s[(k + j) % n] - a ]--; } ans += mx; } printf( %.15f n , ans / n); }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n; cin >> n; long long cur = 1; long long ans = 0; long long now = n; while (cur <= now) { now -= cur; cur *= 2; ans++; } if (now != 0) ans++; cout << ans << endl; return 0; }
|
`timescale 1 ns / 1 ps
`include "pwm_v1_0_tb_include.vh"
// lite_response Type Defines
`define RESPONSE_OKAY 2'b00
`define RESPONSE_EXOKAY 2'b01
`define RESP_BUS_WIDTH 2
`define BURST_TYPE_INCR 2'b01
`define BURST_TYPE_WRAP 2'b10
// AMBA AXI4 Lite Range Constants
`define S00_AXI_MAX_BURST_LENGTH 1
`define S00_AXI_DATA_BUS_WIDTH 32
`define S00_AXI_ADDRESS_BUS_WIDTH 32
`define S00_AXI_MAX_DATA_SIZE (`S00_AXI_DATA_BUS_WIDTH*`S00_AXI_MAX_BURST_LENGTH)/8
module pwm_v1_0_tb;
reg tb_ACLK;
reg tb_ARESETn;
// Create an instance of the example tb
`BD_WRAPPER dut (.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn));
// Local Variables
// AMBA S00_AXI AXI4 Lite Local Reg
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_rd_data_lite;
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_test_data_lite [3:0];
reg [`RESP_BUS_WIDTH-1:0] S00_AXI_lite_response;
reg [`S00_AXI_ADDRESS_BUS_WIDTH-1:0] S00_AXI_mtestAddress;
reg [3-1:0] S00_AXI_mtestProtection_lite;
integer S00_AXI_mtestvectorlite; // Master side testvector
integer S00_AXI_mtestdatasizelite;
integer result_slave_lite;
// Simple Reset Generator and test
initial begin
tb_ARESETn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);
end
// Simple Clock Generator
initial tb_ACLK = 1'b0;
always #10 tb_ACLK = !tb_ACLK;
//------------------------------------------------------------------------
// TEST LEVEL API: CHECK_RESPONSE_OKAY
//------------------------------------------------------------------------
// Description:
// CHECK_RESPONSE_OKAY(lite_response)
// This task checks if the return lite_response is equal to OKAY
//------------------------------------------------------------------------
task automatic CHECK_RESPONSE_OKAY;
input [`RESP_BUS_WIDTH-1:0] response;
begin
if (response !== `RESPONSE_OKAY) begin
$display("TESTBENCH ERROR! lite_response is not OKAY",
"\n expected = 0x%h",`RESPONSE_OKAY,
"\n actual = 0x%h",response);
$stop;
end
end
endtask
//------------------------------------------------------------------------
// TEST LEVEL API: COMPARE_LITE_DATA
//------------------------------------------------------------------------
// Description:
// COMPARE_LITE_DATA(expected,actual)
// This task checks if the actual data is equal to the expected data.
// X is used as don't care but it is not permitted for the full vector
// to be don't care.
//------------------------------------------------------------------------
`define S_AXI_DATA_BUS_WIDTH 32
task automatic COMPARE_LITE_DATA;
input [`S_AXI_DATA_BUS_WIDTH-1:0]expected;
input [`S_AXI_DATA_BUS_WIDTH-1:0]actual;
begin
if (expected === 'hx || actual === 'hx) begin
$display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
result_slave_lite = 0;
$stop;
end
if (actual != expected) begin
$display("TESTBENCH ERROR! Data expected is not equal to actual.",
"\nexpected = 0x%h",expected,
"\nactual = 0x%h",actual);
result_slave_lite = 0;
$stop;
end
else
begin
$display("TESTBENCH Passed! Data expected is equal to actual.",
"\n expected = 0x%h",expected,
"\n actual = 0x%h",actual);
end
end
endtask
task automatic S00_AXI_TEST;
begin
$display("---------------------------------------------------------");
$display("EXAMPLE TEST : S00_AXI");
$display("Simple register write and read example");
$display("---------------------------------------------------------");
S00_AXI_mtestvectorlite = 0;
S00_AXI_mtestAddress = `S00_AXI_SLAVE_ADDRESS;
S00_AXI_mtestProtection_lite = 0;
S00_AXI_mtestdatasizelite = `S00_AXI_MAX_DATA_SIZE;
result_slave_lite = 1;
for (S00_AXI_mtestvectorlite = 0; S00_AXI_mtestvectorlite <= 3; S00_AXI_mtestvectorlite = S00_AXI_mtestvectorlite + 1)
begin
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],
S00_AXI_mtestdatasizelite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_rd_data_lite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_rd_data_lite,S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
COMPARE_LITE_DATA(S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_rd_data_lite);
$display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S00_AXI_mtestvectorlite,S00_AXI_mtestvectorlite);
S00_AXI_mtestAddress = S00_AXI_mtestAddress + 32'h00000004;
end
$display("---------------------------------------------------------");
$display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!");
if ( result_slave_lite ) begin
$display("PTGEN_TEST: PASSED!");
end else begin
$display("PTGEN_TEST: FAILED!");
end
$display("---------------------------------------------------------");
end
endtask
// Create the test vectors
initial begin
// When performing debug enable all levels of INFO messages.
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);
// Create test data vectors
S00_AXI_test_data_lite[0] = 32'h0101FFFF;
S00_AXI_test_data_lite[1] = 32'habcd0001;
S00_AXI_test_data_lite[2] = 32'hdead0011;
S00_AXI_test_data_lite[3] = 32'hbeef0011;
end
// Drive the BFM
initial begin
// Wait for end of reset
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
S00_AXI_TEST();
end
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlslice:1.0
// IP Revision: 0
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xlslice_11_0 (
Din,
Dout
);
input wire [15 : 0] Din;
output wire [0 : 0] Dout;
xlslice #(
.DIN_WIDTH(16),
.DIN_FROM(15),
.DIN_TO(15)
) inst (
.Din(Din),
.Dout(Dout)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; const int NAX = 2e5 + 5, MOD = 1000000007; struct Node { set<pair<int, int>> vals; Node() {} Node lazylazyMerge(const Node &rhs) {} Node seglazyMerge(const Node &rhs, const int &l, const int &r) {} Node segSegMerge(const Node &rhs) {} }; template <typename segNode> struct Segtree { vector<segNode> Seg, Lazy; vector<segNode> Base; vector<bool> isLazy; int n; Segtree(int _n = 2e5) { this->n = _n; Seg.resize(4 * _n + 10); Lazy.resize(4 * _n + 10); isLazy.resize(4 * _n + 10); } void merge(segNode &curr, segNode &l, segNode &r) { curr = l + r; } void propagate(int node, int L, int R) { if (isLazy[node]) { isLazy[node] = false; Seg[node] = Seg[node].seglazyMerge(Lazy[node], L, R); if (L != R) { Lazy[2 * node] = Lazy[2 * node].lazylazyMerge(Lazy[node]); Lazy[2 * node + 1] = Lazy[2 * node + 1].lazylazyMerge(Lazy[node]); isLazy[2 * node] = true; isLazy[2 * node + 1] = true; } Lazy[node] = segNode(); } } void build(int node, int start, int end) { if (start == end) { Seg[node] = Base[start]; return; } int mid = (start + end) / 2; build(2 * node, start, mid); build(2 * node + 1, mid + 1, end); Seg[node] = Seg[2 * node].segSegMerge(Seg[2 * node + 1]); } void build(vector<segNode> &Arr) { Base = Arr; n = Arr.size(); Seg.resize(4 * n + 10); Lazy.resize(4 * n + 10); isLazy.resize(4 * n + 10); build(1, 0, n - 1); } pair<int, int> Query(int node, int start, int end, int qstart, int qend) { propagate(node, start, end); if (qend < start || qstart > end || start > end) return pair<int, int>(MOD, MOD); if (qstart <= start && end <= qend) { if ((Seg[node].vals).empty()) return pair<int, int>(MOD, MOD); return *((Seg[node].vals).begin()); } int mid = (start + end) / 2; auto l = Query(2 * node, start, mid, qstart, qend); auto r = Query(2 * node + 1, mid + 1, end, qstart, qend); return min(l, r); } segNode qQuery(int node, int start, int end, int pos) { propagate(node, start, end); if (start == end) return Seg[node]; int mid = (start + end) / 2; if (pos <= mid) return qQuery(2 * node, start, mid, pos); return qQuery(2 * node + 1, mid + 1, end, pos); } void Update(int node, int start, int end, int qstart, int qend, segNode val) { propagate(node, start, end); if (qend < start || qstart > end || start > end) return; if (qstart <= start && end <= qend) { isLazy[node] = true; Lazy[node] = val; propagate(node, start, end); return; } int mid = (start + end) / 2; Update(2 * node, start, mid, qstart, qend, val); Update(2 * node + 1, mid + 1, end, qstart, qend, val); Seg[node] = Seg[2 * node].segSegMerge(Seg[2 * node + 1]); } void pUpdate(int node, int start, int end, int pos, pair<int, int> val) { Seg[node].vals.insert(val); if (start == end) { return; } int mid = (start + end) / 2; if (pos <= mid) pUpdate(2 * node, start, mid, pos, val); else pUpdate(2 * node + 1, mid + 1, end, pos, val); } void pdel(int node, int start, int end, int pos, pair<int, int> val) { Seg[node].vals.erase(val); if (start == end) { return; } int mid = (start + end) / 2; if (pos <= mid) pdel(2 * node, start, mid, pos, val); else pdel(2 * node + 1, mid + 1, end, pos, val); } segNode query(int pos) { return qQuery(1, 0, n - 1, pos); } pair<int, int> query(int left, int right) { return Query(1, 0, n - 1, left, right); } void update(int pos, pair<int, int> val) { pUpdate(1, 0, n - 1, pos, val); } void update(int start, int end, segNode val) { Update(1, 0, n - 1, start, end, val); } }; void solveCase() { int n; cin >> n; ; vector<pair<pair<int, int>, pair<int, pair<int, int>>>> a(n); vector<int> ranges; for (size_t i = 0; i < n; i++) { cin >> a[i].first.first >> a[i].first.second; cin >> a[i].second.first >> a[i].second.second.first; a[i].second.second.second = i; ranges.push_back(a[i].first.first); ranges.push_back(a[i].second.first); } sort(ranges.begin(), ranges.end()); ranges.erase(unique(ranges.begin(), ranges.end()), ranges.end()); for (size_t i = 0; i < n; i++) { a[i].first.first = lower_bound(ranges.begin(), ranges.end(), a[i].first.first) - ranges.begin(); a[i].second.first = lower_bound(ranges.begin(), ranges.end(), a[i].second.first) - ranges.begin(); } sort(a.begin(), a.end()); ; vector<int> prev(n, -1), dist(n, MOD); queue<int> Q; Segtree<Node> stree(n); for (size_t i = 0; i < n; i++) { if (a[i].first.first == 0 && a[i].first.second == 0) { Q.push(i); dist[i] = 0; } else stree.update(i, {a[i].first.second, i}); } while (Q.size()) { auto curr_idx = Q.front(); ; Q.pop(); int c = a[curr_idx].second.first; int d = a[curr_idx].second.second.first; int idx2 = lower_bound(a.begin(), a.end(), make_pair(make_pair(c + 1, 0), make_pair(0, make_pair(0, 0)))) - a.begin(); --idx2; ; while (true) { auto q = stree.query(0, idx2); ; if (q.first > d) break; int idx = q.second; Q.push(idx); dist[idx] = dist[curr_idx] + 1; prev[idx] = curr_idx; stree.pdel(1, 0, n - 1, idx, q); } }; for (size_t i = 0; i < n; i++) { if (a[i].second.second.second == (n - 1)) { if (dist[i] != MOD) { cout << dist[i] + 1 << n ; vector<int> path; int curr = i; while (curr >= 0) { path.push_back(curr); curr = prev[curr]; } for (int i = path.size() - 1; i >= 0; i--) { cout << a[path[i]].second.second.second + 1 << ; } cout << n ; return; } } } cout << -1 << n ; } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); int t = 1; ; for (int i = 1; i <= t; ++i) solveCase(); return 0; }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; const int MOD = 998244353; void add(int& a, int b) { a += b; if (a >= MOD) a -= MOD; } int mul(int a, int b) { return ll(a) * b % MOD; } int modinv(int a, int m = MOD) { return a == 1 ? a : m - modinv(m % a, a) * ll(m) / a; } const int MAXV = 4242; int p2[MAXV], invp2[MAXV]; int p2m1[MAXV], invp2m1[MAXV]; void precomp() { p2[0] = 1; for (int i = 1; i < MAXV; i++) { p2[i] = mul(2, p2[i - 1]); } for (int i = 0; i < MAXV; i++) { invp2[i] = modinv(p2[i]); } for (int i = 0; i < MAXV; i++) { p2m1[i] = p2[i] - 1; } for (int i = 1; i < MAXV; i++) { invp2m1[i] = modinv(p2m1[i]); } } const int MAXN = 3010; int N, C; int A[MAXN]; int main() { precomp(); scanf( %d %d , &N, &C); for (int i = 0; i < N; i++) { scanf( %d , &A[i]); A[i]--; } vector<vector<int>> dp(N + 1); dp[0] = {{1}}; if (C > 10) { for (int i = 0; i < N; i++) { vector<int> freq(C); int prod = 1; int cnt_bad = C - 1; for (int j = i; j >= 0; j--) { if (A[i] != A[j]) { if (!freq[A[j]]) { cnt_bad--; } else { prod = mul(prod, invp2m1[freq[A[j]]]); } freq[A[j]]++; prod = mul(prod, p2m1[freq[A[j]]]); } if (cnt_bad == 0) { if (dp[i + 1].size() < dp[j].size() + 1) { dp[i + 1].resize(dp[j].size() + 1); } for (int l = 0; l < int(dp[j].size()); l++) { add(dp[i + 1][l + 1], mul(prod, dp[j][l])); } } } } } else { vector<vector<int>> dp2(1 << C); dp2[0] = {{1}}; for (int i = 0; i < N; i++) { for (int m = (1 << C) - 1; m >= 0; m--) { if (dp2[m | (1 << A[i])].size() < dp2[m].size()) { dp2[m | (1 << A[i])].resize(dp2[m].size()); } for (int l = 0; l < int(dp2[m].size()); l++) { add(dp2[m | (1 << A[i])][l], dp2[m][l]); } } swap(dp[i + 1], dp2[(1 << C) - 1]); dp[i + 1].insert(dp[i + 1].begin(), 0); if (dp2[0].size() < dp[i + 1].size()) { dp2[0].resize(dp[i + 1].size()); } for (int l = 0; l < int(dp[i + 1].size()); l++) { add(dp2[0][l], dp[i + 1][l]); } } } vector<int> ans(N + 1); for (int i = 0; i <= N; i++) { for (int l = 0; l < int(dp[i].size()); l++) { add(ans[l], mul(p2[N - i], dp[i][l])); } } ans[0]--; for (int i = 0; i < N; i++) { add(ans[i], MOD - ans[i + 1]); } for (int i = 0; i <= N; i++) { printf( %d%c , ans[i], n [i == N]); } return 0; }
|
module junsignedArrayMultiplierTb;
wire [7:0] Y;
reg [3:0] A, B;
junsignedArrayMultiplier juam(Y, A, B);
initial
begin
$display("RSLT\tA x B = Y");
A = 2; B = 2; #10;
if ( Y == 4 )
$display("PASS\t%p x %p = %p",A,B,Y);
else
$display("FAIL\t%p x %p = %p",A,B,Y);
A = 3; B = 3; #10;
if ( Y == 9 )
$display("PASS\t%p x %p = %p",A,B,Y);
else
$display("FAIL\t%p x %p = %p",A,B,Y);
A = 3; B = 4; #10;
if ( Y == 12 )
$display("PASS\t%p x %p = %p",A,B,Y);
else
$display("FAIL\t%p x %p = %p",A,B,Y);
A = 3; B = 5; #10;
if ( Y == 15 )
$display("PASS\t%p x %p = %p",A,B,Y);
else
$display("FAIL\t%p x %p = %p",A,B,Y);
A = 0; B = 0; #10;
if ( Y == 0 )
$display("PASS\t%p x %p = %p",A,B,Y);
else
$display("FAIL\t%p x %p = %p",A,B,Y);
A = 1; B = 1; #10;
if ( Y == 1 )
$display("PASS\t%p x %p = %p",A,B,Y);
else
$display("FAIL\t%p x %p = %p",A,B,Y);
A = 15; B = 15; #10;
if ( Y == 225 )
$display("PASS\t%p x %p = %p",A,B,Y);
else
$display("FAIL\t%p x %p = %p",A,B,Y);
end
endmodule
|
//----------------------------------------------------------------------------
//-- Unidad de recepcion serie asincrona
//------------------------------------------
//-- (C) BQ. October 2015. Written by Juan Gonzalez (Obijuan)
//-- GPL license
//----------------------------------------------------------------------------
//-- Comprobado su funcionamiento a todas las velocidades estandares:
//-- 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200
//----------------------------------------------------------------------------
//-- Although this transmitter has been written from the scratch, it has been
//-- inspired by the one developed in the swapforth proyect by James Bowman
//--
//-- https://github.com/jamesbowman/swapforth
//--
//----------------------------------------------------------------------------
`default_nettype none
`include "baudgen.vh"
module uart_rx
#(
parameter BAUD = `B115200
)
(input wire clk, //-- Reloj del sistema
input wire rstn, //-- Reset
input wire rx, //-- Linea de recepcion serie
output reg rcv, //-- Indicar Dato disponible
output reg [7:0] data); //-- Dato recibo
//-- Reloj para la recepcion
wire clk_baud;
//-- Linea de recepcion registrada
//-- Para cumplir reglas de diseño sincrono
reg rx_r;
//-- Microordenes
reg bauden; //-- Activar señal de reloj de datos
reg clear; //-- Poner a cero contador de bits
reg load; //-- Cargar dato recibido
//-------------------------------------------------------------------
//-- RUTA DE DATOS
//-------------------------------------------------------------------
//-- Registrar la señal de recepcion de datos
//-- Para cumplir con las normas de diseño sincrono
always @(posedge clk)
rx_r <= rx;
//-- Divisor para la generacion del reloj de llegada de datos
baudgen_rx #(.BAUD(BAUD))
baudgen0 (
.clk(clk),
.clk_ena(bauden),
.clk_out(clk_baud)
);
//-- Contador de bits
reg [3:0] bitc;
always @(posedge clk)
if (clear)
bitc <= 4'd0;
else if (clear == 0 && clk_baud == 1)
bitc <= bitc + 1;
//-- Registro de desplazamiento para almacenar los bits recibidos
reg [9:0] raw_data;
always @(posedge clk)
if (clk_baud == 1) begin
raw_data = {rx_r, raw_data[9:1]};
end
//-- Registro de datos. Almacenar el dato recibido
always @(posedge clk)
if (rstn == 0)
data <= 0;
else if (load)
data <= raw_data[8:1];
//-------------------------------------
//-- CONTROLADOR
//-------------------------------------
localparam IDLE = 2'd0; //-- Estado de reposo
localparam RECV = 2'd1; //-- Recibiendo datos
localparam LOAD = 2'd2; //-- Almacenamiento del dato recibido
localparam DAV = 2'd3; //-- Señalizar dato disponible
reg [1:0] state;
//-- Transiciones entre estados
always @(posedge clk)
if (rstn == 0)
state <= IDLE;
else
case (state)
//-- Resposo
IDLE :
//-- Al llegar el bit de start se pasa al estado siguiente
if (rx_r == 0)
state <= RECV;
else
state <= IDLE;
//--- Recibiendo datos
RECV:
//-- Vamos por el ultimo bit: pasar al siguiente estado
if (bitc == 4'd10)
state <= LOAD;
else
state <= RECV;
//-- Almacenamiento del dato
LOAD:
state <= DAV;
//-- Señalizar dato disponible
DAV:
state <= IDLE;
default:
state <= IDLE;
endcase
//-- Salidas de microordenes
always @* begin
bauden <= (state == RECV) ? 1 : 0;
clear <= (state == IDLE) ? 1 : 0;
load <= (state == LOAD) ? 1 : 0;
rcv <= (state == DAV) ? 1 : 0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; bool isPowerOfTwo(int x) { return (x && !(x & (x - 1))); } bool is_prime(int n) { if (n == 1) return false; for (int i = 2; i <= sqrt(n); i++) { if (n % i == 0) { return false; } } return true; } void solve() { int n; cin >> n; long long int a, b; cin >> a >> b; set<long long int> st; st.insert(a); st.insert(b); for (int i = 2; i * i <= a; i++) { if (a % i == 0) { st.insert(i); st.insert(a / i); } } for (int i = 2; i * i <= b; i++) { if (b % i == 0) { st.insert(i); st.insert(b / i); } } map<pair<long long int, long long int>, long long int> ch; ch[{a, b}]++; for (int i = 1; i < n; i++) { cin >> a >> b; if (ch[{a, b}] >= 1) continue; ch[{a, b}]++; for (auto it = st.begin(); it != st.end();) { long long int k = *it; if (a % k == 0 || b % k == 0) { it++; } else { it = st.erase(it++); } } } if (st.empty()) cout << -1 ; else cout << (*st.begin()); } int main() { ios::sync_with_stdio(0); cin.tie(0); int t = 1; while (t--) { solve(); } return 0; }
|
module DFF
(output reg Q0,
output reg [1:0] Q1,
input wire D0,
input wire [1:0] D1,
input wire CLK,
input wire RST
/* */);
always @(posedge CLK or posedge RST)
if (RST) begin
Q0 <= 0;
Q1 <= 0;
end else begin
Q0 <= D0;
Q1 <= D1;
end
endmodule // dut
module main;
wire q0;
wire [1:0] q1;
reg d0, clk, rst;
reg [1:0] d1;
DFF dut (.Q0(q0), .Q1(q1), .D0(d0), .D1(d1), .CLK(clk), .RST(rst));
initial begin
clk <= 1;
d0 <= 0;
d1 <= 2;
#1 rst <= 1;
#1 if (q0 !== 1'b0 || q1 !== 1'b0) begin
$display("FAILED -- RST=%b, Q0=%b, Q1=%b", rst, q0, q1);
$finish;
end
#1 rst <= 0;
#1 if (q0 !== 1'b0 || q1 !== 1'b0) begin
$display("FAILED -- RST=%b, Q0=%b, Q1=%b", rst, q0, q1);
$finish;
end
#1 clk <= 0;
#1 clk <= 1;
#1 if (q0 !== d0 || q1 !== d1) begin
$display("FAILED -- Q0=%b Q1=%b, D0=%b D1=%b", q0, q1, d0, d1);
$finish;
end
$display("PASSED");
$finish;
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; const int inf = 1e9; const long long INF = 1e18; long long n, sum, ans; long long a[200010]; struct BIT { long long tree[600010]; BIT() { memset(tree, 0, sizeof(tree)); } void update(long long i, long long x) { while (i <= 600000) { tree[i] += x; i += i & -i; } } long long sum(long long i) { long long ret = 0; while (i) { ret += tree[i]; i -= i & -i; } return ret; } } t1, t2; int main() { ios::sync_with_stdio(false); cin.tie(0); ; cin >> n; for (long long i = 1; i <= n; i++) { cin >> a[i]; ans += (i - 1) * a[i] - t1.sum(a[i]); long long x = sum; for (long long j = a[i]; j <= 300000; j += a[i]) { t1.update(j, a[i]); x -= (j / a[i]) * a[i] * (t2.sum(j + a[i] - 1) - t2.sum(j - 1)); } ans += x; sum += a[i]; t2.update(a[i], 1); cout << ans << ; } }
|
#include <bits/stdc++.h> using namespace std; int N, T; char str[15], temp[15]; int main() { int i, j, k; scanf( %s%s , str, temp); i = strlen(str); sort(str, str + i); if (str[0] == 0 ) { do { if (str[0] != 0 ) break; } while (next_permutation(str, str + i)); } if (strcmp(str, temp) == 0) printf( OK n ); else printf( WRONG_ANSWER n ); scanf( ); }
|
#include <bits/stdc++.h> using namespace std; struct que { int l, r, y, val; bool operator<(const que &v) const { return y < v.y; } }; int n, k, x[100010], y[100010], cnt[100010 * 2], pre[100010 * 2]; long long ans[100010]; vector<que> q; vector<int> h; int main() { scanf( %d%d , &n, &k); for (int i = 1; i <= n; i++) scanf( %d%d , &x[i], &y[i]); for (int i = 1; i <= 2 * n; i++) pre[i] = -0x3f3f3f3f; h.push_back(-0x3f3f3f3f); for (int i = 1; i <= n; i++) { h.push_back(x[i]); h.push_back(x[i] + k); } sort(h.begin(), h.end()); h.resize(unique(h.begin(), h.end()) - h.begin()); for (int i = 1, l, r; i <= n; i++) { l = upper_bound(h.begin(), h.end(), x[i]) - h.begin(); r = lower_bound(h.begin(), h.end(), x[i] + k) - h.begin(); q.push_back({l, r, y[i], 1}); q.push_back({l, r, y[i] + k, -1}); } sort(q.begin(), q.end()); for (auto i : q) for (int j = i.l; j <= i.r; j++) { ans[cnt[j]] += 1ll * (h[j] - h[j - 1]) * (i.y - pre[j]); cnt[j] += i.val; pre[j] = i.y; } for (int i = 1; i <= n; i++) printf( %lld , ans[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; void fast(); int main() { fast(); int k, d; cin >> k >> d; string ans = ; if ((d > (pow(10, k) - 1)) || (d == 0 && k != 1)) { cout << No solution ; return 0; } for (int i = 0; i < k; i++) { if (d > 9) { ans += 9 ; d -= 9; } else { stringstream t; t << d; ans += t.str(); d = 0; } } cout << ans; return 0; } void fast() { ios_base::sync_with_stdio(0); cin.tie(NULL), cout.tie(NULL); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFRTP_TB_V
`define SKY130_FD_SC_MS__SDFRTP_TB_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__sdfrtp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg RESET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 SCD = 1'b0;
#80 SCE = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 D = 1'b1;
#200 RESET_B = 1'b1;
#220 SCD = 1'b1;
#240 SCE = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 D = 1'b0;
#360 RESET_B = 1'b0;
#380 SCD = 1'b0;
#400 SCE = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 SCE = 1'b1;
#600 SCD = 1'b1;
#620 RESET_B = 1'b1;
#640 D = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 SCE = 1'bx;
#760 SCD = 1'bx;
#780 RESET_B = 1'bx;
#800 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_ms__sdfrtp dut (.D(D), .SCD(SCD), .SCE(SCE), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFRTP_TB_V
|
#include <bits/stdc++.h> using namespace std; long long add(long long n) { long long mi = INT_MAX, ma = INT_MIN; while (n > 0) { mi = min(n % 10, mi); ma = max(n % 10, ma); n = n / 10; } return mi * ma; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; scanf( %d , &t); while (t--) { long long n, k; scanf( %lld%lld , &n, &k); k--; while (k--) { long long j = add(n); n = n + j; if (j == 0) { break; } } cout << n << endl; } }
|
#include <bits/stdc++.h> using namespace std; int main() { int a[7]; while (scanf( %d , &a[0]) != EOF) { int maxx = a[0]; int minn = a[0]; int ans = 0; for (int i = 1; i < 6; i++) { cin >> a[i]; } ans = (a[0] + a[1] + a[2]) * (a[0] + a[2] + a[1]) - a[0] * a[0] - a[2] * a[2] - a[4] * a[4]; cout << ans << endl; } return 0; }
|
// Copyright (c) 2014 Takashi Toyoshima <>.
// All rights reserved. Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
module SerialReceiver(
clk_x4,
rst_x,
i_rx,
o_data,
o_valid,
o_error);
input clk_x4;
input rst_x;
input i_rx;
output [7:0] o_data;
output o_valid;
output o_error;
reg [1:0] r_phase;
reg [3:0] r_state;
reg [7:0] r_data;
wire w_phase_latch;
wire w_phase_shift;
wire w_phase_next;
wire w_valid;
wire w_stop;
localparam S_IDLE = 4'b0000;
localparam S_START = 4'b0001;
localparam S_BIT0 = 4'b0011;
localparam S_BIT1 = 4'b0010;
localparam S_BIT2 = 4'b0110;
localparam S_BIT3 = 4'b0111;
localparam S_BIT4 = 4'b0101;
localparam S_BIT5 = 4'b0100;
localparam S_BIT6 = 4'b1100;
localparam S_BIT7 = 4'b1101;
localparam S_STOP = 4'b1111;
assign w_phase_latch = r_phase == 2'b01;
assign w_phase_next = r_phase == 2'b10;
assign w_phase_shift = r_phase == 2'b11;
assign w_valid = (r_state == S_STOP) && w_phase_latch;
assign w_stop = i_rx == 1'b1;
assign o_data = r_data;
assign o_valid = w_valid & w_stop;
assign o_error = w_valid & !w_stop;
always @ (posedge clk_x4) begin
if (w_phase_latch) begin
r_data <= { i_rx, r_data[7:1] };
end
end // always @ (posedge clk_x4)
always @ (posedge clk_x4 or negedge rst_x) begin
if (!rst_x) begin
r_phase <= 2'b00;
end else begin
if (r_state == S_IDLE) begin
r_phase <= 2'b00;
end else begin
r_phase <= r_phase + 2'b01;
end
end // else (!rst_x)
end // always @ (posedge clk_x4 or negedge rst_x)
always @ (posedge clk_x4 or negedge rst_x) begin
if (!rst_x) begin
r_state <= S_IDLE;
end else begin
case (r_state)
S_IDLE: begin
if (i_rx == 1'b0) begin
r_state <= S_START;
end
end // S_IDLE
S_START: begin
if (w_phase_shift) begin
r_state <= S_BIT0;
end
end // S_START
S_BIT0: begin
if (w_phase_shift) begin
r_state <= S_BIT1;
end
end // S_BIT0
S_BIT1: begin
if (w_phase_shift) begin
r_state <= S_BIT2;
end
end // S_BIT1
S_BIT2: begin
if (w_phase_shift) begin
r_state <= S_BIT3;
end
end // S_BIT2
S_BIT3: begin
if (w_phase_shift) begin
r_state <= S_BIT4;
end
end // S_BIT3
S_BIT4: begin
if (w_phase_shift) begin
r_state <= S_BIT5;
end
end // S_BIT4
S_BIT5: begin
if (w_phase_shift) begin
r_state <= S_BIT6;
end
end // S_BIT5
S_BIT6: begin
if (w_phase_shift) begin
r_state <= S_BIT7;
end
end // S_BIT6
S_BIT7: begin
if (w_phase_shift) begin
r_state <= S_STOP;
end
end // S_BIT7
S_STOP: begin
if (w_phase_next) begin
r_state <= S_IDLE;
end
end // S_STOP
endcase // case (r_state)
end // else (!rst_x)
end // always @ (posedge clk_x4 or negedge rst_x)
endmodule // SerialReceiver
|
#include <bits/stdc++.h> using namespace std; #define ll long long #define ld long double #define pii pair <ll, ll> #define mp make_pair // const int inf = 1e9 + 111; const int NMAX = 200111; const int inf = 1e9 + 7; const ld eps = 0.00000000001; const ll mod = 1e9 + 7; constexpr int64_t MOD = 998244353; int main() { cin.tie(0); cout.tie(0); cin.sync_with_stdio(0); cout.sync_with_stdio(0); cout << setprecision(20) << fixed; int t; cin >> t; for (int i = 0; i < t; ++i) { int n, k; cin >> n >> k; if (k < n) { if (n % k == 0) { cout << 1 << endl; } else { cout << 2 << endl; } } else { cout << (k + n - 1) / n << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m; string grid[101]; int nb, l = 200, r = -1, u = 200, d = -1; int main() { scanf( %d %d , &n, &m); for (int i = 0; i < n; i++) cin >> grid[i]; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) if (grid[i][j] == B ) { nb++; l = min(l, j); r = max(r, j); u = min(u, i); d = max(d, i); } } if (nb == 0) { cout << 1 << endl; return 0; } int h = d - u + 1, w = r - l + 1; if (w > h) { if (w > n) { cout << -1 << endl; return 0; } cout << w * w - nb << endl; } else { if (h > m) { cout << -1 << endl; return 0; } cout << h * h - nb << endl; } }
|
#include <bits/stdc++.h> using namespace std; deque<int> d[100005]; int v[100005]; int p[100005]; pair<int, int> q[100005]; int ans = 0; int prog = 0; int as[100005]; unordered_map<int, int> possible[100005]; bool cmp(int a, int b) { if (q[a].first / 300 != q[b].first / 300) return q[a].first / 300 < q[b].first / 300; return q[a].second < q[b].second; } void update(int val, int pos, int u, int c) { if (c == -1) { prog -= possible[val].size() <= 1; if (u == 1) { int cnt = d[val].front(); d[val].pop_front(); if (d[val].empty()) --ans; else { --possible[val][d[val].front() - cnt]; if (!possible[val][d[val].front() - cnt]) possible[val].erase(d[val].front() - cnt); } } else { int cnt = d[val].back(); d[val].pop_back(); if (d[val].empty()) --ans; else { --possible[val][cnt - d[val].back()]; if (!possible[val][cnt - d[val].back()]) possible[val].erase(cnt - d[val].back()); } } if (!d[val].empty()) prog += possible[val].size() <= 1; } else { if (d[val].empty()) ++ans; else prog -= possible[val].size() <= 1; if (u == 1) { if (d[val].empty()) { d[val].push_front(pos); } else { int cnt = d[val].front(); d[val].push_front(pos); ++possible[val][cnt - pos]; } } else { if (d[val].empty()) { d[val].push_back(pos); } else { int cnt = d[val].back(); d[val].push_back(pos); ++possible[val][pos - cnt]; } } if (possible[val].size() <= 1) ++prog; } } int main(void) { int n, m; ios_base ::sync_with_stdio(0); cin >> n; for (int i = 1; i <= n; ++i) cin >> v[i]; cin >> m; for (int i = 1; i <= m; ++i) cin >> q[i].first >> q[i].second, p[i] = i; sort(p + 1, p + 1 + m, cmp); for (int i = q[p[1]].first; i <= q[p[1]].second; ++i) update(v[i], i, 1, 1); as[p[1]] = ans + !prog; int l = q[p[1]].first, r = q[p[1]].second; for (int i = 2; i <= m; ++i) { while (l > q[p[i]].first) --l, update(v[l], l, -1, 1); while (r < q[p[i]].second) ++r, update(v[r], r, 1, 1); while (l < q[p[i]].first) update(v[l], l, -1, -1), ++l; while (r > q[p[i]].second) update(v[r], r, 1, -1), --r; as[p[i]] = ans + !prog; } for (int i = 1; i <= m; ++i) cout << as[i] << n ; return cout << n , 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYGATE4S50_TB_V
`define SKY130_FD_SC_LP__DLYGATE4S50_TB_V
/**
* dlygate4s50: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlygate4s50.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_lp__dlygate4s50 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYGATE4S50_TB_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, a, i, j, arr[300] = {0}, p = 0, k = 0, c, d; cin >> n >> a; for (i = 1; i < n + 1; i++) { cin >> arr[i]; } arr[0] = 1, arr[n + 1] = 1; j = min(a, n - a + 1); for (i = j; i < n + 1; i++) { c = a + k; d = a - k; if (d < 1) d = 0; if (c > n) c = n + 1; if (arr[d] == arr[c] and arr[c]) { if (c != d and c <= n and d > 0) p += 2; else p++; } k++; } cout << p << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long int inf = 2000000000; const long double eps = 0.0000001; const long double pi = acos(-1.0); const long long int MOD = 998244353; const long long int N = 1e5 + 5; signed main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long int n; cin >> n; long long int a[n]; for (long long int i = 0; i < n; ++i) { cin >> a[i]; } long long int ans = 1, mn = inf; for (long long int t = 1; t <= 100; t++) { long long int s = 0; for (long long int i = 0; i < n; ++i) { if (a[i] > t + 1) s += a[i] - t - 1; else if (a[i] < t - 1) s += t - a[i] - 1; } if (s < mn) { mn = s; ans = t; } } cout << ans << << mn; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKINVLP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__CLKINVLP_BEHAVIORAL_PP_V
/**
* clkinvlp: Lower power Clock tree inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__clkinvlp (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKINVLP_BEHAVIORAL_PP_V
|
/**
* $Id: red_pitaya_ams.v -01-21 11:40:39Z matej.oblak $
*
* @brief Red Pitaya analog mixed signal.
*
* @Author Matej Oblak
*
* (c) Red Pitaya http://www.redpitaya.com
*
* This part of code is written in Verilog hardware description language (HDL).
* Please visit http://en.wikipedia.org/wiki/Verilog
* for more details on the language used herein.
*/
/**
* GENERAL DESCRIPTION:
*
* Module using XADC and software interface for PWM DAC.
*
*
* /------\
* SUPPLY V. -----> | |
* TEMPERATURE ---> | XADC | ------
* EXTERNAL V. ---> | | |
* \------/ |
* |
* ˇ
* /------\
* PWD DAC <------------------ | REGS | <------> SW
* \------/
*
*
* Reading system and external voltages is done with XADC, running in sequencer
* mode. It measures supply voltages, temperature and voltages on external
* connector. Measured values are then exposed to SW.
*
* Beside that SW can sets registes which controls logic for PWM DAC (analog module).
*
*/
module red_pitaya_ams (
// ADC
input clk_i , // clock
input rstn_i , // reset - active low
// PWM DAC
output reg [ 24-1: 0] dac_a_o , // values used for
output reg [ 24-1: 0] dac_b_o , // conversion into PWM signal
output reg [ 24-1: 0] dac_c_o , //
output reg [ 24-1: 0] dac_d_o , //
input [ 14-1: 0] pwm0_i , // 14 bit inputs for compatibility and future upgrades;
// right now only 12 bits are used
input [ 14-1: 0] pwm1_i ,
// system bus
input [ 32-1: 0] sys_addr , // bus address
input [ 32-1: 0] sys_wdata , // bus write data
input [ 4-1: 0] sys_sel , // bus write byte select
input sys_wen , // bus write enable
input sys_ren , // bus read enable
output reg [ 32-1: 0] sys_rdata , // bus read data
output reg sys_err , // bus error indicator
output reg sys_ack // bus acknowledge signal
);
//---------------------------------------------------------------------------------
//
// System bus connection
always @(posedge clk_i)
if (rstn_i == 1'b0) begin
dac_a_o <= 24'h000000 ;
dac_b_o <= 24'h000000 ;
dac_c_o <= 24'h000000 ;
dac_d_o <= 24'h000000 ;
end else begin
dac_a_o <= cfg;
dac_b_o <= cfg_b;
if (sys_wen) begin
// if (sys_addr[19:0]==16'h20) dac_a_o <= sys_wdata[24-1: 0] ;
// if (sys_addr[19:0]==16'h24) dac_b_o <= sys_wdata[24-1: 0] ;
if (sys_addr[19:0]==16'h28) dac_c_o <= sys_wdata[24-1: 0] ;
if (sys_addr[19:0]==16'h2C) dac_d_o <= sys_wdata[24-1: 0] ;
end
end
wire sys_en;
assign sys_en = sys_wen | sys_ren;
always @(posedge clk_i)
if (rstn_i == 1'b0) begin
sys_err <= 1'b0 ;
sys_ack <= 1'b0 ;
end else begin
sys_err <= 1'b0 ;
casez (sys_addr[19:0])
20'h00020 : begin sys_ack <= sys_en; sys_rdata <= {{32-24{1'b0}}, dac_a_o} ; end
20'h00024 : begin sys_ack <= sys_en; sys_rdata <= {{32-24{1'b0}}, dac_b_o} ; end
20'h00028 : begin sys_ack <= sys_en; sys_rdata <= {{32-24{1'b0}}, dac_c_o} ; end
20'h0002C : begin sys_ack <= sys_en; sys_rdata <= {{32-24{1'b0}}, dac_d_o} ; end
default : begin sys_ack <= sys_en; sys_rdata <= 32'h0 ; end
endcase
end
// conversion of 14 bit input signal into config register:
// bits 4-11 are the duty cycle
// bits 0-3 configure the duty cycle modulation
// therefore fundamental switch frequency is
// 250 MHz/2**8 = 488.28125 kHz
// the duty cycle is modulated over a period of 16 PWM cycles
// -> lowest frequency is 30.51757812 kHz
// we need to convert bits 0-3 into a bit sequence that
// will prolong the duty cycle by 1 if the bit is set
// and 0 if it is not set. The 16 bits will be sequentially
// interrogated by the PWM
// we will encode bits 0-3 as follows:
// bit3 = 16'b0101010101010101
// bit2 = 16'b0010001000100010
// bit1 = 16'b0000100000001000
// bit0 = 16'b0000000010000000
// resp. bit: 323132303231323
// as you can see, each row except for the first can be filled
// with exactly one bit, therefore our method is exclusive
// and will always lead to a modulation duty cycle in the interval [0:1[
// on top of all this, we need to convert the incoming signal from signed to unsigned
// and from 14 bits to 12
// the former is easy: just bitshift by 2
// the latter is easy as well:
// maxnegative = 0b1000000 -> 0
// maxnegative + 1 = 0b10000001 -> 1
// ...
// -1 = 0b1111111111 -> 0b01111111111
// therefore: only need to invert the sign bit
// works as well for positive numbers:
// 0 -> 0b1000000000
// 1 -> 0b1000000001
//maxpositive = -> 11111111111
// its not clear at all if the timing will be right here since we work at 250 MHz in this module
// if something doesnt work, parts of the logic must be transferred down to 125 MHz
localparam CCW = 24; // configuration bitwidth for pwm module
reg [24-1:0] cfg;
wire bit3;
wire bit2;
wire bit1;
wire bit0;
assign {bit3,bit2,bit1,bit0} = pwm0_i[5:2];
always @(posedge clk_i)
if (rstn_i == 1'b0) begin
cfg <= {CCW{1'b0}};
end else begin
cfg <= {~pwm0_i[13],pwm0_i[13-1:6],1'b0,bit3,bit2,bit3,bit1,bit3,bit2,bit3,bit0,bit3,bit2,bit3,bit1,bit3,bit2,bit3};
end
reg [24-1:0] cfg_b;
wire bit3_b;
wire bit2_b;
wire bit1_b;
wire bit0_b;
assign {bit3_b,bit2_b,bit1_b,bit0_b} = pwm1_i[5:2];
always @(posedge clk_i)
if (rstn_i == 1'b0) begin
cfg_b <= {CCW{1'b0}};
end else begin
cfg_b <= {~pwm1_i[13],pwm1_i[13-1:6],1'b0,bit3_b,bit2_b,bit3_b,bit1_b,bit3_b,bit2_b,bit3_b,bit0_b,bit3_b,bit2_b,bit3_b,bit1_b,bit3_b,bit2_b,bit3_b};
end
endmodule
|
#include <bits/stdc++.h> using namespace std; using namespace std; long long int **sparse; void buildSparseTable(long long int arr[], long long int n, long long int **sparse) { for (long long int i = 0; i < n; i++) { sparse[i][0] = i; } for (long long int j = 1; pow(2, j) <= n; j++) { for (long long int i = 0; i + pow(2, j) - 1 < n; i++) { if (arr[sparse[i][j - 1]] >= arr[sparse[i + (long long int)pow(2, j - 1)][j - 1]]) { sparse[i][j] = sparse[i][j - 1]; } else { sparse[i][j] = sparse[i + (long long int)pow(2, j - 1)][j - 1]; } } } } long long int query(long long int l, long long int r, long long int **sparse, long long int arr[]) { long long int len = r - l + 1; long long int k = (log(len) / log(2.0)); long long int m; if (arr[sparse[l][k]] >= arr[sparse[l + len - (long long int)pow(2, k)][k]]) { return sparse[l][k]; } else return sparse[l + len - (long long int)pow(2, k)][k]; } int main() { long long int n; cin >> n; long long int arr[n]; sparse = new long long int *[n]; for (long long int i = 0; i < n; i++) { sparse[i] = new long long int[(long long int)floor(log(n) / log(2.0)) + 1]; } arr[n - 1] = n - 1; for (long long int i = 0; i < n - 1; i++) { cin >> arr[i]; arr[i]--; } buildSparseTable(arr, n, sparse); long long int dp[n]; dp[n - 1] = 0; long long int sum = 0; for (long long int i = n - 2; i >= 0; i--) { long long int m = query(i + 1, arr[i], sparse, arr); dp[i] = dp[m] - (arr[i] - m) + n - 1 - i; sum += dp[i]; } cout << sum << endl; }
|
#include <bits/stdc++.h> using namespace std; int n, a[3]; int dp[310][310]; string name[2] = { BitAryo , BitLGM }; int mem(int x, int y) { if (dp[x][y] != -1) return dp[x][y]; int mn = 1; for (int i = 1; i <= x; i++) mn = min(mn, mem(x - i, y)); for (int i = 1; i <= y; i++) mn = min(mn, mem(x, y - i)); for (int i = 1; i <= min(x, y); i++) mn = min(mn, mem(x - i, y - i)); return dp[x][y] = 1 - mn; } int main() { memset(dp, -1, sizeof dp); cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; if (n == 1) cout << name[(a[0] == 0 ? 0 : 1)] << endl; if (n == 2) cout << name[mem(a[0], a[1])] << endl; if (n == 3) cout << name[((a[0] ^ a[1] ^ a[2]) == 0 ? 0 : 1)] << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 5; int num[5005], cnt[5005] = {}, id[5005]; int dp[5005][5005]; bool used[5005]; int main() { ios::sync_with_stdio(0); cin.tie(0); int n, k; cin >> n >> k; for (int i = 1; i <= n; i++) cin >> num[i]; sort(num + 1, num + n + 1); for (int i = 1; i <= n; i++) { int r = i; while (r + 1 <= n && (num[r + 1] - num[i]) <= 5) r++; cnt[i] = r; } for (int i = n; i >= 1; i--) { for (int j = 1; j <= k; j++) { dp[i][j] = dp[i + 1][j]; dp[i][j] = max(dp[i][j], dp[cnt[i] + 1][j - 1] + cnt[i] - i + 1); } } int ans = 0; for (int i = 1; i <= n; i++) ans = max(ans, dp[1][i]); cout << ans << n ; }
|
#include <bits/stdc++.h> using namespace std; void vin(vector<long long int> &v, long long int t) { for (long long int i = 0; i < t; i++) cin >> v[i]; } void vout(vector<long long int> &v, long long int t) { for (long long int i = 0; i < t; i++) cout << v[i] << ; cout << endl; } void ingraph(vector<vector<long long int>> &graph, long long int m) { long long int x, y; for (long long int i = 0; i < m; i++) { cin >> x >> y; x--, y--; graph[x].push_back(y); graph[y].push_back(x); } } bool sortbysec(const pair<int, int> &a, const pair<int, int> &b) { return (a.second < b.second); } long long int gcd(long long int a, long long int b) { if (b == 0) return a; return gcd(b, a % b); } long long int lcm(long long int a, long long int b) { return a * b / gcd(a, b); } void solve() { long long int n, m, x, y; cin >> n >> m >> x >> y; long long int cost = 0; y = min(y, 2 * x); for (long long int i = 0; i < n; i++) { string s; cin >> s; for (long long int j = 0; j < m; j++) { if (s[j] == . ) { if (j != m - 1 && s[j + 1] == . ) cost += y, j++; else cost += x; } } } cout << cost << n ; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long int t; cin >> t; while (t--) solve(); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__PROBE_P_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__PROBE_P_FUNCTIONAL_PP_V
/**
* probe_p: Virtual voltage probe point.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__probe_p (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__PROBE_P_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, a, b, c, ans, boby, apu; cin >> n; while (n--) { cin >> a >> b >> c >> ans; boby = b - a; apu = c + ans; if (boby % apu == 0) { cout << boby / apu << endl; } else cout << -1 << endl; } return 0; }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module image_filter_Filter2D_k_buf_0_val_0_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk);
parameter DWIDTH = 8;
parameter AWIDTH = 11;
parameter MEM_SIZE = 1920;
input[AWIDTH-1:0] addr0;
input ce0;
output reg[DWIDTH-1:0] q0;
input[AWIDTH-1:0] addr1;
input ce1;
input[DWIDTH-1:0] d1;
input we1;
input clk;
(* ram_style = "block" *)reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
always @(posedge clk)
begin
if (ce0)
begin
q0 <= ram[addr0];
end
end
always @(posedge clk)
begin
if (ce1)
begin
if (we1)
begin
ram[addr1] <= d1;
end
end
end
endmodule
`timescale 1 ns / 1 ps
module image_filter_Filter2D_k_buf_0_val_0(
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd1920;
parameter AddressWidth = 32'd11;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
output[DataWidth - 1:0] q0;
input[AddressWidth - 1:0] address1;
input ce1;
input we1;
input[DataWidth - 1:0] d1;
image_filter_Filter2D_k_buf_0_val_0_ram image_filter_Filter2D_k_buf_0_val_0_ram_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.q0( q0 ),
.addr1( address1 ),
.ce1( ce1 ),
.d1( d1 ),
.we1( we1 ));
endmodule
|
module dut(/*AUTOARG*/
// Outputs
dut_active, clkout, wait_out, access_out, packet_out,
// Inputs
clk1, clk2, nreset, vdd, vss, access_in, packet_in, wait_in
);
parameter N = 1;
parameter PW = 104;
//clock, reset
input clk1;
input clk2;
input nreset;
input [N*N-1:0] vdd;
input vss;
output dut_active;
output clkout;
//Stimulus Driven Transaction
input [N-1:0] access_in;
input [N*PW-1:0] packet_in;
output [N-1:0] wait_out;
//DUT driven transactoin
output [N-1:0] access_out;
output [N*PW-1:0] packet_out;
input [N-1:0] wait_in;
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOWIRE*/
//tie offs for Dv
assign dut_active = 1'b1;
assign wait_out = 1'b0;
assign clk = clk1;
oh_clockdiv oh_clockdiv (.clkout (clkout),
.clkout90 (clkout90),
.clk (clk),
.nreset (nreset),
.en (1'b1),
.divcfg (packet_in[11:8])
);
endmodule // dv_elink
// Local Variables:
// verilog-library-directories:("." "../hdl" "../../emesh/dv" "../../emesh/hdl")
// End:
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:536870912 ) const int MOD = 1000000007; const int INF = 1000000001; const int MAXN = 17; const long double EPS = 1e-6; const int HASH_POW = 29; const long double PI = acos(-1.0); using namespace std; void my_return(int code) { exit(code); } int main() { cin.sync_with_stdio(0); cin.tie(0); mt19937 mt_rand(time(0)); int n, k; scanf( %d %d , &n, &k); if (k >= n / 2) printf( %I64d n , n * 1ll * (n - 1) / 2); else { long long ans = 0; int ptr = n - 1; for (int i = 0; i < k; ++i) { ans += 2 * ptr - 1; ptr -= 2; } printf( %I64d n , ans); } my_return(0); }
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module routing_buffer(clock, resetn,
i_datain, i_datain_valid, o_datain_stall,
o_dataout, i_dataout_stall, o_dataout_valid);
parameter DATA_WIDTH = 32;
parameter INSERT_REGISTER = 0;
input clock, resetn;
input [DATA_WIDTH-1:0] i_datain;
input i_datain_valid;
output reg o_datain_stall;
output reg [DATA_WIDTH-1:0] o_dataout;
input i_dataout_stall;
output reg o_dataout_valid;
generate
if (INSERT_REGISTER)
begin
always @ (negedge resetn or posedge clock)
begin
if (~resetn)
begin
o_datain_stall <= 1'b0;
o_dataout_valid <= 1'b0;
o_dataout <= 'x;
end
else
begin
o_datain_stall <= i_dataout_stall;
o_dataout_valid <= i_datain_valid;
o_dataout <= i_datain;
end
end
end
else
begin //non-registered version
always @ (*)
begin
o_datain_stall <= i_dataout_stall;
o_dataout_valid <= i_datain_valid;
o_dataout <= i_datain;
end
end
endgenerate
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2011 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
real r, r2;
integer cyc=0;
task check(integer line, real got, real ex);
if (got != ex) begin
if ((got > ex ? got - ex : ex - got) > 0.000001) begin
$display("%%Error: Line %0d: Bad result, got=%0.99g expect=%0.99g",line,got,ex);
$stop;
end
end
endtask
initial begin
// Check constant propagation
// Note $abs is not defined in SystemVerilog (as of 2012)
check(`__LINE__, $ceil(-1.2), -1);
check(`__LINE__, $ceil(1.2), 2);
check(`__LINE__, $exp(1.2), 3.3201169227365472380597566370852291584014892578125);
check(`__LINE__, $exp(0.0), 1);
check(`__LINE__, $exp(-1.2), 0.301194211912202136627314530414878390729427337646484375);
check(`__LINE__, $floor(-1.2), -2);
check(`__LINE__, $floor(1.2), 1);
check(`__LINE__, $ln(1.2), 0.1823215567939545922460098381634452380239963531494140625);
//check(`__LINE__, $ln(0), 0); // Bad value
//check(`__LINE__, $ln(-1.2), 0); // Bad value
check(`__LINE__, $log10(1.2), 0.07918124604762481755226843915806966833770275115966796875);
//check(`__LINE__, $log10(0), 0); // Bad value
//check(`__LINE__, $log10(-1.2), 0);
check(`__LINE__, $pow(2.3,1.2), 2.71689843249914897427288451581262052059173583984375);
check(`__LINE__, $pow(2.3,-1.2), 0.368066758785732861536388327294844202697277069091796875);
//check(`__LINE__, $pow(-2.3,1.2),0); // Bad value
check(`__LINE__, $sqrt(1.2), 1.095445115010332148841598609578795731067657470703125);
//check(`__LINE__, $sqrt(-1.2), 0); // Bad value
check(`__LINE__, ((1.5)**(1.25)), 1.660023);
check(`__LINE__, $acos (0.2), 1.369438406); // Arg1 is -1..1
check(`__LINE__, $acosh(1.2), 0.622362503);
check(`__LINE__, $asin (0.2), 0.201357920); // Arg1 is -1..1
check(`__LINE__, $asinh(1.2), 1.015973134);
check(`__LINE__, $atan (0.2), 0.197395559);
check(`__LINE__, $atan2(0.2,2.3), 0.086738338); // Arg1 is -1..1
check(`__LINE__, $atanh(0.2), 0.202732554); // Arg1 is -1..1
check(`__LINE__, $cos (1.2), 0.362357754);
check(`__LINE__, $cosh (1.2), 1.810655567);
check(`__LINE__, $hypot(1.2,2.3), 2.594224354);
check(`__LINE__, $sin (1.2), 0.932039085);
check(`__LINE__, $sinh (1.2), 1.509461355);
check(`__LINE__, $tan (1.2), 2.572151622);
check(`__LINE__, $tanh (1.2), 0.833654607);
end
real sum_ceil;
real sum_exp;
real sum_floor;
real sum_ln;
real sum_log10;
real sum_pow1;
real sum_pow2;
real sum_sqrt;
real sum_acos;
real sum_acosh;
real sum_asin;
real sum_asinh;
real sum_atan;
real sum_atan2;
real sum_atanh;
real sum_cos ;
real sum_cosh;
real sum_hypot;
real sum_sin;
real sum_sinh;
real sum_tan;
real sum_tanh;
// Test loop
always @ (posedge clk) begin
r = $itor(cyc)/10.0 - 5.0; // Crosses 0
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d r=%g s_ln=%0.12g\n",$time, cyc, r, sum_ln);
`endif
cyc <= cyc + 1;
if (cyc==0) begin
end
else if (cyc<90) begin
// Setup
sum_ceil += 1.0+$ceil(r);
sum_exp += 1.0+$exp(r);
sum_floor += 1.0+$floor(r);
if (r > 0.0) sum_ln += 1.0+$ln(r);
if (r > 0.0) sum_log10 += 1.0+$log10(r);
// Pow requires if arg1<0 then arg1 integral
sum_pow1 += 1.0+$pow(2.3,r);
if (r >= 0.0) sum_pow2 += 1.0+$pow(r,2.3);
if (r >= 0.0) sum_sqrt += 1.0+$sqrt(r);
if (r>=-1.0 && r<=1.0) sum_acos += 1.0+$acos (r);
if (r>=1.0) sum_acosh += 1.0+$acosh(r);
if (r>=-1.0 && r<=1.0) sum_asin += 1.0+$asin (r);
sum_asinh += 1.0+$asinh(r);
sum_atan += 1.0+$atan (r);
if (r>=-1.0 && r<=1.0) sum_atan2 += 1.0+$atan2(r,2.3);
if (r>=-1.0 && r<=1.0) sum_atanh += 1.0+$atanh(r);
sum_cos += 1.0+$cos (r);
sum_cosh += 1.0+$cosh (r);
sum_hypot += 1.0+$hypot(r,2.3);
sum_sin += 1.0+$sin (r);
sum_sinh += 1.0+$sinh (r);
sum_tan += 1.0+$tan (r);
sum_tanh += 1.0+$tanh (r);
end
else if (cyc==99) begin
check (`__LINE__, sum_ceil, 85);
check (`__LINE__, sum_exp, 608.06652950);
check (`__LINE__, sum_floor, 4);
check (`__LINE__, sum_ln, 55.830941633);
check (`__LINE__, sum_log10, 46.309585076);
check (`__LINE__, sum_pow1, 410.98798177);
check (`__LINE__, sum_pow2, 321.94765689);
check (`__LINE__, sum_sqrt, 92.269677253);
check (`__LINE__, sum_acos, 53.986722862);
check (`__LINE__, sum_acosh, 72.685208498);
check (`__LINE__, sum_asin, 21);
check (`__LINE__, sum_asinh, 67.034973416);
check (`__LINE__, sum_atan, 75.511045389);
check (`__LINE__, sum_atan2, 21);
check (`__LINE__, sum_atanh, 0);
check (`__LINE__, sum_cos, 72.042023124);
check (`__LINE__, sum_cosh, 1054.);
check (`__LINE__, sum_hypot, 388.92858406);
check (`__LINE__, sum_sin, 98.264184989);
check (`__LINE__, sum_sinh, -);
check (`__LINE__, sum_tan, 1.);
check (`__LINE__, sum_tanh, 79.003199681);
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
(** Responses from the server. *)
Require Import ListString.All.
Require Http.
Require Import Model.
(** Sum type of the responses. *)
Inductive t :=
(** Errors. *)
| NotFound | WrongArguments | Forbidden
(** Static content from the `static/` folder. *)
| Static (mime_type : LString.t) (content : LString.t)
(** Confirm that you are logged in or out. *)
| Login | Logout
(** The index page. *)
| Index (is_logged : bool) (posts : list Post.Header.t)
(** The page of a post. *)
| PostShow (is_logged : bool) (url : LString.t) (post : option Post.t)
(** Form to add a post. *)
| PostAdd
(** Confirm that a post is added. *)
| PostDoAdd (is_success : bool)
(** Form to edit a post. *)
| PostEdit (url : LString.t) (post : option Post.t)
(** Confirm that a post is edited. *)
| PostDoEdit (url : LString.t) (is_success : bool)
(** Confirm that a post is deleted. *)
| PostDoDelete (is_success : bool).
(** Raw responses after pretty-printing in `Render.v`. The return code is always
200 (OK). *)
Module Raw.
Record t := New {
mime_type : LString.t;
cookies : Http.Cookies.t;
content : LString.t }.
End Raw.
|
module RegisterFileTestBench3;
parameter sim_time = 750*2; // Num of Cycles * 2
reg [31:0] in,Pcin;
reg [19:0] RSLCT;
reg Clk, RESET, LOADPC, LOAD,IR_CU;
wire [31:0] Rn,Rm,Rs,PCout;
//RegisterFile(input [31:0] in,Pcin,input [19:0] RSLCT,input Clk, RESET, LOADPC, LOAD,IR_CU, output [31:0] Rn,Rm,Rs,PCout);
RegisterFile RF(in,Pcin,RSLCT,Clk, RESET, LOADPC, LOAD,IR_CU, Rn,Rm,Rs,PCout);
initial fork
//Clk 0
Clk = 0 ; RESET = 1 ; Pcin = 32'bz ; in = 32'bz ; LOADPC = 0 ; LOAD = 0 ;IR_CU = 1 ; RSLCT = 0 ;
//Clk 1 (Rising Edge)
#1 RESET = 0 ; #1 Pcin = 32'bz ; #1 in = 1 ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ; #1 RSLCT = 0 ;
//Clk 0 (Falling Edge)
#2 Pcin = 32'bz ; #2 in = 1 ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 1 ; #2 RSLCT = 1 ;
//Clk 1 (Rising Edge)
#3 Pcin = 32'bz ; #3 in = 1 ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 1 ; #3 RSLCT = 1 ;
//Clk 0 (Falling Edge)
#4 Pcin = 32'bz ; #4 in = 1 ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 1 ; #4 RSLCT = 1 ;
//Clk 1 (Rising Edge)
#5 Pcin = 32'bz ; #5 in = 1 ; #5 LOADPC = 0 ; #5 LOAD = 0 ; #5 IR_CU = 1 ; #5 RSLCT = 1 ;
//Clk 0 (Falling Edge)
#6 Pcin = 32'bz ; #6 in = 1 ; #6 LOADPC = 0 ; #6 LOAD = 1 ; #6 IR_CU = 1 ; #6 RSLCT = 2 ;
//Clk 1 (Rising Edge)
#7 Pcin = 32'bz ; #7 in = 1 ; #7 LOADPC = 0 ; #7 LOAD = 1 ; #7 IR_CU = 1 ; #7 RSLCT = 2 ;
//Clk 0 (Falling Edge)
#8 Pcin = 32'bz ; #8 in = 1 ; #8 LOADPC = 0 ; #8 LOAD = 1 ; #8 IR_CU = 1 ; #8 RSLCT = 2 ;
//Clk 1 (Rising Edge)
#9 Pcin = 32'bz ; #9 in = 1 ; #9 LOADPC = 0 ; #9 LOAD = 1 ; #9 IR_CU = 1 ; #9 RSLCT = 2 ;
//Clk 0 (Falling Edge)
#10 Pcin = 32'bz ; #10 in = 1 ; #10 LOADPC = 0 ; #10 LOAD = 0 ; #10 IR_CU = 1 ; #10 RSLCT = 0 ;
join
always
#1 Clk = ~Clk;
initial #sim_time $finish;
initial begin
$dumpfile("RegisterFileTestBench3.vcd");
$dumpvars(0,RegisterFileTestBench3);
$display(" Test Results" );
$monitor("time = %3d ,Pcin = %3d , in = %3d , LOADPC = %3d , LOAD = %3d , IR_CU = %3d , RSLCT = %3d , Rn = %3d ,Rm = %3d ,Rs = %3d ,PCout = %3d",$time,Pcin, in, LOADPC, LOAD, IR_CU, RSLCT,Rn,Rm,Rs,PCout);
end
endmodule
//iverilog Buffer32_32.v Decoder4x16.v Multiplexer2x1_32b.v Register.v RegisterFile.v RegisterFileTestBench.v
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Spartan-6 Integrated Block for PCI Express
// File : axi_basic_top.v
//----------------------------------------------------------------------------//
// File: axi_basic_top.v //
// //
// Description: //
// TRN/AXI4-S Bridge top level module. Instantiates RX and TX modules. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module axi_basic_top #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter STRB_WIDTH = C_DATA_WIDTH / 8 // TKEEP width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI TX
//-----------
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user
input s_axis_tx_tvalid, // TX data is valid
output s_axis_tx_tready, // TX ready for data
input [STRB_WIDTH-1:0] s_axis_tx_tkeep, // TX strobe byte enables
input s_axis_tx_tlast, // TX data is last
input [3:0] s_axis_tx_tuser, // TX user signals
// AXI RX
//-----------
output [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
output m_axis_rx_tvalid, // RX data is valid
input m_axis_rx_tready, // RX ready for data
output [STRB_WIDTH-1:0] m_axis_rx_tkeep, // RX strobe byte enables
output m_axis_rx_tlast, // RX data is last
output [21:0] m_axis_rx_tuser, // RX user signals
// User Misc.
//-----------
input user_turnoff_ok, // Turnoff OK from user
input user_tcfg_gnt, // Send cfg OK from user
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN TX
//-----------
output [C_DATA_WIDTH-1:0] trn_td, // TX data from block
output trn_tsof, // TX start of packet
output trn_teof, // TX end of packet
output trn_tsrc_rdy, // TX source ready
input trn_tdst_rdy, // TX destination ready
output trn_tsrc_dsc, // TX source discontinue
output [REM_WIDTH-1:0] trn_trem, // TX remainder
output trn_terrfwd, // TX error forward
output trn_tstr, // TX streaming enable
input [5:0] trn_tbuf_av, // TX buffers available
output trn_tecrc_gen, // TX ECRC generate
// TRN RX
//-----------
input [C_DATA_WIDTH-1:0] trn_rd, // RX data from block
input trn_rsof, // RX start of packet
input trn_reof, // RX end of packet
input trn_rsrc_rdy, // RX source ready
output trn_rdst_rdy, // RX destination ready
input trn_rsrc_dsc, // RX source discontinue
input [REM_WIDTH-1:0] trn_rrem, // RX remainder
input trn_rerrfwd, // RX error forward
input [6:0] trn_rbar_hit, // RX BAR hit
input trn_recrc_err, // RX ECRC error
// TRN Misc.
//-----------
input trn_tcfg_req, // TX config request
output trn_tcfg_gnt, // RX config grant
input trn_lnk_up, // PCIe link up
// 7 Series/Virtex6 PM
//-----------
input [2:0] cfg_pcie_link_state, // Encoded PCIe link state
// Virtex6 PM
//-----------
input cfg_pm_send_pme_to, // PM send PME turnoff msg
input [1:0] cfg_pmcsr_powerstate, // PMCSR power state
input [31:0] trn_rdllp_data, // RX DLLP data
input trn_rdllp_src_rdy, // RX DLLP source ready
// Virtex6/Spartan6 PM
//-----------
input cfg_to_turnoff, // Turnoff request
output cfg_turnoff_ok, // Turnoff grant
// System
//-----------
output [2:0] np_counter, // Non-posted counter
input user_clk, // user clock from block
input user_rst // user reset from block
);
//---------------------------------------------//
// RX Data Pipeline //
//---------------------------------------------//
axi_basic_rx #(
.C_DATA_WIDTH (C_DATA_WIDTH ),
.C_FAMILY (C_FAMILY ),
.TCQ (TCQ ),
.REM_WIDTH (REM_WIDTH ),
.STRB_WIDTH (STRB_WIDTH )
) rx_inst (
// Outgoing AXI TX
//-----------
.m_axis_rx_tdata (m_axis_rx_tdata ),
.m_axis_rx_tvalid (m_axis_rx_tvalid ),
.m_axis_rx_tready (m_axis_rx_tready ),
.m_axis_rx_tkeep (m_axis_rx_tkeep ),
.m_axis_rx_tlast (m_axis_rx_tlast ),
.m_axis_rx_tuser (m_axis_rx_tuser ),
// Incoming TRN RX
//-----------
.trn_rd (trn_rd ),
.trn_rsof (trn_rsof ),
.trn_reof (trn_reof ),
.trn_rsrc_rdy (trn_rsrc_rdy ),
.trn_rdst_rdy (trn_rdst_rdy ),
.trn_rsrc_dsc (trn_rsrc_dsc ),
.trn_rrem (trn_rrem ),
.trn_rerrfwd (trn_rerrfwd ),
.trn_rbar_hit (trn_rbar_hit ),
.trn_recrc_err (trn_recrc_err ),
// System
//-----------
.np_counter (np_counter ),
.user_clk (user_clk ),
.user_rst (user_rst )
);
//---------------------------------------------//
// TX Data Pipeline //
//---------------------------------------------//
axi_basic_tx #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.C_ROOT_PORT( C_ROOT_PORT ),
.C_PM_PRIORITY( C_PM_PRIORITY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.STRB_WIDTH( STRB_WIDTH )
) tx_inst (
// Incoming AXI RX
//-----------
.s_axis_tx_tdata( s_axis_tx_tdata ),
.s_axis_tx_tvalid( s_axis_tx_tvalid ),
.s_axis_tx_tready( s_axis_tx_tready ),
.s_axis_tx_tkeep( s_axis_tx_tkeep ),
.s_axis_tx_tlast( s_axis_tx_tlast ),
.s_axis_tx_tuser( s_axis_tx_tuser ),
// User Misc.
//-----------
.user_turnoff_ok( user_turnoff_ok ),
.user_tcfg_gnt( user_tcfg_gnt ),
// Outgoing TRN TX
//-----------
.trn_td( trn_td ),
.trn_tsof( trn_tsof ),
.trn_teof( trn_teof ),
.trn_tsrc_rdy( trn_tsrc_rdy ),
.trn_tdst_rdy( trn_tdst_rdy ),
.trn_tsrc_dsc( trn_tsrc_dsc ),
.trn_trem( trn_trem ),
.trn_terrfwd( trn_terrfwd ),
.trn_tstr( trn_tstr ),
.trn_tbuf_av( trn_tbuf_av ),
.trn_tecrc_gen( trn_tecrc_gen ),
// TRN Misc.
//-----------
.trn_tcfg_req( trn_tcfg_req ),
.trn_tcfg_gnt( trn_tcfg_gnt ),
.trn_lnk_up( trn_lnk_up ),
// 7 Series/Virtex6 PM
//-----------
.cfg_pcie_link_state( cfg_pcie_link_state ),
// Virtex6 PM
//-----------
.cfg_pm_send_pme_to( cfg_pm_send_pme_to ),
.cfg_pmcsr_powerstate( cfg_pmcsr_powerstate ),
.trn_rdllp_data( trn_rdllp_data ),
.trn_rdllp_src_rdy( trn_rdllp_src_rdy ),
// Spartan6 PM
//-----------
.cfg_to_turnoff( cfg_to_turnoff ),
.cfg_turnoff_ok( cfg_turnoff_ok ),
// System
//-----------
.user_clk( user_clk ),
.user_rst( user_rst )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int ted[1010]; int main() { memset(ted, 0, sizeof ted); int n; cin >> n; while (n--) { int x; cin >> x; ted[x]++; } int ans = 0; int mx = 0; for (int i = 1; i <= 1000; i++) if (ted[i]) { ans++; mx = max(mx, ted[i]); } cout << mx << << ans << endl; return 0; }
|
////////////////////////////////////////////////////////////////////////////////////
//
// pGB, yet another FPGA fully functional and super fun GB classic clone!
// Copyright (C) 2015-2016 Diego Valverde ()
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
//
////////////////////////////////////////////////////////////////////////////////////
// Sound module, channel 4. White noise generation module using LFSR.
////////////////////////////////////////////////////////////////////////////////////
module SoundCtrlChannel4 //parameters
(
input wire iClock, //CPU CLOCK, 4194304Hz
input wire iReset,
input wire iOsc64, //OSC1 clock 64Hz
input wire iOsc256, //OSC1 clock 256Hz
input wire [7:0] iNR41,
input wire [7:0] iNR42,
input wire [7:0] iNR43,
input wire [7:0] iNR44,
output reg [4:0] oOut,
output wire oOnFlag
);
reg [5:0] rLength;
reg [19:0] rLengthCounter;
reg rLengthComplete; // Channe disable.
wire rTone;
reg [3:0] rStep;
reg [18:0] rStepTime;
reg [18:0] rStepCounter;
reg [3:0] rInitialValue;
reg rEvelopeMode;
reg [2:0] rDivRatioFreq;
reg [3:0] rShiftClockFreq;
reg rPolCoutSteps;
reg rClkDiv;
reg [5:0] rDivRatioCounter;
reg rCountPre;
reg [14:0] rShiftCounter;
reg rTimedMode;
wire [4:0] up_value, down_value;
// register load
always @(posedge iClock) begin
if (iReset || iNR44[7]) begin // Register reload and counters restart.
rLength <= iNR41[5:0];
rLengthCounter <= 64-iNR41[5:0]; // Decrements to zero then load rLength.
rLengthComplete <= 0; // Disables channel when is asserted.
rStepTime <= iNR42[2:0];
rStepCounter <= iNR42[2:0]; // Decrements to zero then load rStepTime.
rEvelopeMode <= iNR42[3];
rInitialValue <= iNR42[7:4];
rStep <= iNR42[7:4];
rDivRatioFreq <= iNR43[2:0];
// rDivRatioCounter <= 6'd16;
if (iNR43[2:0]==0) begin
rDivRatioCounter[5:0] <= 6'd4;
end
else begin
rDivRatioCounter[5:0] <= {iNR43[2:0],3'b0};
end
// rDivRatioCounter <= (iNR43[2:0]==0) ? 6'd4 : (iNR43[2:0]<<3) ; // fcpu/8
rClkDiv <= 0;
rPolCoutSteps <= iNR43[3];
rShiftClockFreq <= iNR43[7:4];
rShiftCounter <= (iNR43[7:4] < 15) ? 1 << iNR43[7:4] : 1 << 14;
rCountPre <= 0;
rTimedMode <= iNR44[6];
end
end
// step gen: generates the output amplitud value.
always @(posedge iOsc64) begin
if (rStepTime != 0) begin // Check if channel is enabled.
if (rStepCounter ==1 ) begin
rStepCounter <= rStepTime; // Reset counter.
if(rEvelopeMode) begin // Envelope mode.
rStep <= ((rStep == 4'hF) ? rStep : rStep+1); //INCREASES ONLY IF STEP IF LOWER THAN TOP VALUE
end
else begin
rStep <= ((rStep == 4'h0) ? rStep : rStep-1); //DECREASES ONLY IF STEP IF LOWER THAN BOTTOM VALUE
end
end
else begin
rStepCounter <= rStepCounter-1;
end
end
end
// clock divider
always @(posedge iClock) begin
if (rDivRatioCounter === 0) begin
rClkDiv <= ~rClkDiv;
if (rDivRatioFreq==0) begin
rDivRatioCounter <= 6'd4;
end
else begin
rDivRatioCounter <= {rDivRatioFreq,3'b0};
end
// rDivRatioCounter <= 6'd16;
// rDivRatioCounter <= (rDivRatioFreq==0) ? 6'd4 : (rDivRatioFreq<<3) ; // fcpu/8
end
else begin
rDivRatioCounter <= rDivRatioCounter-1;
end
end
// counter pre-scaler
always @(posedge rClkDiv) begin
if (rShiftCounter == 0) begin
rCountPre <= ~rCountPre;
rShiftCounter <= (rShiftClockFreq < 15) ? 1 << rShiftClockFreq : 1 << 14;
end
else begin
rShiftCounter <= rShiftCounter-1;
end
end
// white noise gen
lfsr l0 (
.iClock(rCountPre),
.iReset(iReset),
.iStages(rPolCoutSteps),
.oOut(rTone)
);
// timmer: enable or disable channel output.
always @(posedge iOsc256) begin
if (rLengthCounter == 0) begin
rLengthCounter <= 64-rLength;
rLengthComplete <= rTimedMode; // Disable channel only if timmer is enabled.
end
else begin
rLengthCounter <= rLengthCounter-1;
end
end
//re-map mux
assign up_value = 5'd15 + rStep;
assign down_value = 5'd15 - rStep;
always @(posedge iClock) begin
if (rLengthComplete) begin
oOut[4:0] <= 5'd15;
end
else begin
if (rTone) begin
oOut[4:0] <= up_value[4:0];
end
else begin
oOut[4:0] <= down_value[4:0];
end
end
end
assign oOnFlag = rLengthComplete;
endmodule
// misc modules.
module lfsr //parameters
(
input wire iClock,
input wire iReset,
input wire iStages,
output oOut
);
//Stage conection wires.
wire wS0S1, wS1S2, wS2S3, wS3S4, wS4S5, wS5S6, wS6S7, wS7S8;
wire wS8S9, wS9S10, wS10S11, wS11S12, wS12S13, wS13S14, wS14S15, wS15S16;
FFD_POSEDGE_ASYNCRONOUS_RESET_INIT # ( 1 ) FF_CH4_0 (
.Clock(iClock),
.Reset(iReset),
.Enable(1),
.iInitial(1),
.D(oOut ^ wS6S7),
.Q(wS0S1)
);
FFD_POSEDGE_ASYNCRONOUS_RESET_INIT # ( 1 ) FF_CH4_1 (
.Clock(iClock),
.Reset(iReset),
.Enable(1),
.iInitial(1),
.D(wS0S1),
.Q(wS1S2)
);
FFD_POSEDGE_ASYNCRONOUS_RESET_INIT # ( 1 ) FF_CH4_2 (
.Clock(iClock),
.Reset(iReset),
.Enable(1),
.iInitial(1),
.D(wS1S2),
.Q(wS2S3)
);
FFD_POSEDGE_ASYNCRONOUS_RESET_INIT # ( 1 ) FF_CH4_3 (
.Clock(iClock),
.Reset(iReset),
.Enable(1),
.iInitial(1),
.D(wS2S3),
.Q(wS3S4)
);
FFD_POSEDGE_ASYNCRONOUS_RESET_INIT # ( 1 ) FF_CH4_4 (
.Clock(iClock),
.Reset(iReset),
.Enable(1),
.iInitial(1),
.D(wS3S4),
.Q(wS4S5)
);
FFD_POSEDGE_ASYNCRONOUS_RESET_INIT # ( 1 ) FF_CH4_5 (
.Clock(iClock),
.Reset(iReset),
.Enable(1),
.iInitial(1),
.D(wS4S5),
.Q(wS5S6)
);
FFD_POSEDGE_ASYNCRONOUS_RESET_INIT # ( 1 ) FF_CH4_6 (
.Clock(iClock),
.Reset(iReset),
.Enable(1),
.iInitial(1),
.D(wS5S6),
.Q(wS6S7)
);
FFD_POSEDGE_ASYNCRONOUS_RESET_INIT # ( 1 ) FF_CH4_7 (
.Clock(iClock),
.Reset(iReset),
.Enable(1),
.iInitial(1),
.D(wS6S7),
.Q(wS7S8)
);
FFD_POSEDGE_ASYNCRONOUS_RESET_INIT # ( 1 ) FF_CH4_8 (
.Clock(iClock),
.Reset(iReset),
.Enable(1),
.iInitial(1),
.D(wS7S8),
.Q(wS8S9)
);
FFD_POSEDGE_ASYNCRONOUS_RESET_INIT # ( 1 ) FF_CH4_9 (
.Clock(iClock),
.Reset(iReset),
.Enable(1),
.iInitial(1),
.D(wS8S9),
.Q(wS9S10)
);
FFD_POSEDGE_ASYNCRONOUS_RESET_INIT # ( 1 ) FF_CH4_10 (
.Clock(iClock),
.Reset(iReset),
.Enable(1),
.iInitial(1),
.D(wS9S10),
.Q(wS10S11)
);
FFD_POSEDGE_ASYNCRONOUS_RESET_INIT # ( 1 ) FF_CH4_11 (
.Clock(iClock),
.Reset(iReset),
.Enable(1),
.iInitial(1),
.D(wS10S11),
.Q(wS11S12)
);
FFD_POSEDGE_ASYNCRONOUS_RESET_INIT # ( 1 ) FF_CH4_12 (
.Clock(iClock),
.Reset(iReset),
.Enable(1),
.iInitial(1),
.D(wS11S12),
.Q(wS12S13)
);
FFD_POSEDGE_ASYNCRONOUS_RESET_INIT # ( 1 ) FF_CH4_13 (
.Clock(iClock),
.Reset(iReset),
.Enable(1),
.iInitial(1),
.D(wS12S13),
.Q(wS13S14)
);
FFD_POSEDGE_ASYNCRONOUS_RESET_INIT # ( 1 ) FF_CH4_14 (
.Clock(iClock),
.Reset(iReset),
.Enable(1),
.iInitial(1),
.D(wS13S14),
.Q(wS14S15)
);
FFD_POSEDGE_ASYNCRONOUS_RESET_INIT # ( 1 ) FF_CH4_15 (
.Clock(iClock),
.Reset(iReset),
.Enable(1),
.iInitial(1),
.D(wS14S15),
.Q(wS15S16)
);
assign oOut = (iStages) ? wS7S8 : wS15S16 ;
endmodule
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module is a rom for auto initializing the on board audio chip. *
* *
******************************************************************************/
module altera_up_av_config_auto_init_ob_audio (
// Inputs
rom_address,
// Bidirectionals
// Outputs
rom_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter AUD_LINE_IN_LC = 9'h01A;
parameter AUD_LINE_IN_RC = 9'h01A;
parameter AUD_LINE_OUT_LC = 9'h07B;
parameter AUD_LINE_OUT_RC = 9'h07B;
parameter AUD_ADC_PATH = 9'h0F8;
parameter AUD_DAC_PATH = 9'h006;
parameter AUD_POWER = 9'h000;
parameter AUD_DATA_FORMAT = 9'h001;
parameter AUD_SAMPLE_CTRL = 9'h002;
parameter AUD_SET_ACTIVE = 9'h001;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input [ 5: 0] rom_address;
// Bidirectionals
// Outputs
output [26: 0] rom_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// States
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
reg [23: 0] data;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign rom_data = {data[23:16], 1'b0,
data[15: 8], 1'b0,
data[ 7: 0], 1'b0};
// Internal Assignments
always @(*)
begin
case (rom_address)
// Audio Config Data
0 : data <= {8'h34, 7'h0, AUD_LINE_IN_LC};
1 : data <= {8'h34, 7'h1, AUD_LINE_IN_RC};
2 : data <= {8'h34, 7'h2, AUD_LINE_OUT_LC};
3 : data <= {8'h34, 7'h3, AUD_LINE_OUT_RC};
4 : data <= {8'h34, 7'h4, AUD_ADC_PATH};
5 : data <= {8'h34, 7'h5, AUD_DAC_PATH};
6 : data <= {8'h34, 7'h6, AUD_POWER};
7 : data <= {8'h34, 7'h7, AUD_DATA_FORMAT};
8 : data <= {8'h34, 7'h8, AUD_SAMPLE_CTRL};
9 : data <= {8'h34, 7'h9, AUD_SET_ACTIVE};
default : data <= {8'h00, 7'h0, 9'h000};
endcase
end
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/05/24 23:33:19
// Design Name:
// Module Name: lab1_4_2
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module bcdto7segment_dataflow(
input [3:0] x,
output [6:0] seg
);
assign #1 seg[6] = (x[2]&(~x[1])&(~x[0]))|((~x[3])&(~x[2])&(~x[1])&x[0]);
assign #1 seg[5] = (x[2]&(~x[1])&x[0])|(x[2]&x[1]&(~x[0]));
assign #1 seg[4] = (~x[3])&(~x[2])&x[1]&(~x[0]);
assign #1 seg[3] = (x[2]&(~x[1])&(~x[0]))|(x[2]&x[1]&x[0])|((~x[3])&(~x[2])&(~x[1])&x[0]);
assign #1 seg[2] = (x[2]&(~x[1]))|x[0];
assign #1 seg[1] = (x[1]&x[0])|((~x[3])&(~x[2])&x[0])|((~x[3])&(~x[2])&x[1]);
assign #1 seg[0] = ((~x[3])&(~x[2])&(~x[1]))|(x[2]&x[1]&x[0]);
endmodule
|
#include <bits/stdc++.h> int main() { int n; scanf( %d , &n); printf( %d , n); for (int i = 1; i < n; i++) { printf( %d , i); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 50; const int maxm = 1e6 + 50; const double eps = 1e-10; const int max_index = 62; const int inf = 0x3f3f3f3f; const int MOD = 1e9 + 7; inline int read() { char c = getchar(); while (!isdigit(c)) c = getchar(); int x = 0; while (isdigit(c)) { x = x * 10 + c - 0 ; c = getchar(); } return x; } const int offset = 2000; struct Point { int x, y; Point(int x = 0, int y = 0) : x(x), y(y) {} bool operator<(const Point &rhs) const { if (x == rhs.x) return y < rhs.y; return x < rhs.x; } } P[205]; std::vector<int> G[maxm]; int n, m; int dis[maxm], vis[maxm]; int get(int x, int y) { return x * m + y; } int ans = 0; void dfs(int u) { vis[u] = 1; int res = 0; for (int i = 0; i < G[u].size(); i++) { int v = G[u][i]; if (vis[v]) { puts( Poor Inna! ); exit(0); } if (!dis[v]) dfs(v); res = max(res, dis[v]); } dis[u] = res + 1; vis[u] = 0; } int dir[4][2] = {0, -1, -1, 0, 0, 1, 0, -1}; char mp[1005][1005]; bool judge(char x, char y) { bool ok = 0; ok |= (x == D && y == I ); ok |= (x == I && y == M ); ok |= (x == M && y == A ); ok |= (x == A && y == D ); return ok; } int main() { n = read(), m = read(); for (int i = 0; i < n; i++) scanf( %s , mp[i]); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { int u = get(i, j); for (int k = 0; k < 2; k++) { int dx = i + dir[k][0], dy = j + dir[k][1]; if (dx < 0 || dy < 0) continue; int v = get(dx, dy); if (judge(mp[dx][dy], mp[i][j])) { G[v].push_back(u); } else if (judge(mp[i][j], mp[dx][dy])) { G[u].push_back(v); } } } } for (int i = 0; i < m * n; i++) { int x = i / m, y = i % m; if (mp[x][y] != D ) continue; dfs(i); ans = max(ans, dis[i]); } if (ans < 4) puts( Poor Dima! ); else printf( %d n , ans / 4); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e6 + 10; int k, q; long long f[10], dp[maxn]; void update(long long v, long long w) { for (int i = 1000000; i >= w; i--) dp[i] = max(dp[i], dp[i - w] + v); return; } void solve(long long v, long long w) { int num = min((long long)k, 1000000 / w); for (int i = 0; (1 << i) <= num; i++) { int c = (1 << i); update(v * c, w * c); num -= c; } if (num) update(v * num, w * num); return; } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); cin >> k; k = 3 * (k - 1); for (int i = 0; i <= 5; i++) cin >> f[i]; for (int i = 0; i <= 1000000; i++) { int cur = 0, x = i; while (x) { int low = x % 10; if (low % 3 == 0) { dp[i] += f[cur] * (low / 3); } x /= 10; ++cur; } } int sz = 1; for (int i = 0; i <= 5; i++) { solve(f[i], sz * 3); sz *= 10; } cin >> q; while (q--) { int n; cin >> n; cout << dp[n] << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int fin[100005]; int main() { int n; while (cin >> n) { int l, r; int flag = 1; int temp; for (int i = 0; i < n; i++) { cin >> l >> r; if (i == 0) fin[0] = l > r ? l : r; else { temp = l > r ? l : r; if (temp <= fin[i - 1]) fin[i] = temp; else fin[i] = l < r ? l : r; if (fin[i] > fin[i - 1]) flag = 0; } } if (!flag) cout << NO << endl; if (flag) cout << YES << endl; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A31O_2_V
`define SKY130_FD_SC_MS__A31O_2_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog wrapper for a31o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a31o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a31o_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a31o_2 (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A31O_2_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A2111OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__A2111OI_BEHAVIORAL_PP_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__a2111oi (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , B1, C1, D1, and0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A2111OI_BEHAVIORAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFBBN_BLACKBOX_V
`define SKY130_FD_SC_LP__DFBBN_BLACKBOX_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dfbbn (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFBBN_BLACKBOX_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
sys_rst,
sys_clk_p,
sys_clk_n,
uart_sin,
uart_sout,
ddr3_1_n,
ddr3_1_p,
ddr3_reset_n,
ddr3_addr,
ddr3_ba,
ddr3_cas_n,
ddr3_ras_n,
ddr3_we_n,
ddr3_ck_n,
ddr3_ck_p,
ddr3_cke,
ddr3_cs_n,
ddr3_dm,
ddr3_dq,
ddr3_dqs_n,
ddr3_dqs_p,
ddr3_odt,
mdio_mdc,
mdio_mdio,
mii_rst_n,
mii_col,
mii_crs,
mii_rx_clk,
mii_rx_er,
mii_rx_dv,
mii_rxd,
mii_tx_clk,
mii_tx_en,
mii_txd,
linear_flash_addr,
linear_flash_adv_ldn,
linear_flash_ce_n,
linear_flash_dq_io,
linear_flash_oen,
linear_flash_wen,
fan_pwm,
gpio_lcd,
gpio_bd,
iic_rstn,
iic_scl,
iic_sda,
hdmi_out_clk,
hdmi_hsync,
hdmi_vsync,
hdmi_data_e,
hdmi_data,
spdif);
input sys_rst;
input sys_clk_p;
input sys_clk_n;
input uart_sin;
output uart_sout;
output [ 2:0] ddr3_1_n;
output [ 1:0] ddr3_1_p;
output ddr3_reset_n;
output [13:0] ddr3_addr;
output [ 2:0] ddr3_ba;
output ddr3_cas_n;
output ddr3_ras_n;
output ddr3_we_n;
output ddr3_ck_n;
output ddr3_ck_p;
output ddr3_cke;
output ddr3_cs_n;
output [ 7:0] ddr3_dm;
inout [63:0] ddr3_dq;
inout [ 7:0] ddr3_dqs_n;
inout [ 7:0] ddr3_dqs_p;
output ddr3_odt;
output mdio_mdc;
inout mdio_mdio;
output mii_rst_n;
input mii_col;
input mii_crs;
input mii_rx_clk;
input mii_rx_er;
input mii_rx_dv;
input [ 3:0] mii_rxd;
input mii_tx_clk;
output mii_tx_en;
output [ 3:0] mii_txd;
output [26:1] linear_flash_addr;
output linear_flash_adv_ldn;
output linear_flash_ce_n;
inout [15:0] linear_flash_dq_io;
output linear_flash_oen;
output linear_flash_wen;
output fan_pwm;
inout [ 6:0] gpio_lcd;
inout [16:0] gpio_bd;
output iic_rstn;
inout iic_scl;
inout iic_sda;
output hdmi_out_clk;
output hdmi_hsync;
output hdmi_vsync;
output hdmi_data_e;
output [15:0] hdmi_data;
output spdif;
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
// default logic
assign ddr3_1_p = 2'b11;
assign ddr3_1_n = 3'b000;
assign fan_pwm = 1'b1;
assign iic_rstn = 1'b1;
ad_iobuf #(.DATA_WIDTH(17)) i_iobuf_sw_led (
.dio_t (gpio_t[16:0]),
.dio_i (gpio_o[16:0]),
.dio_o (gpio_i[16:0]),
.dio_p (gpio_bd));
// instantiations
system_wrapper i_system_wrapper (
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),
.ddr3_ck_n (ddr3_ck_n),
.ddr3_ck_p (ddr3_ck_p),
.ddr3_cke (ddr3_cke),
.ddr3_cs_n (ddr3_cs_n),
.ddr3_dm (ddr3_dm),
.ddr3_dq (ddr3_dq),
.ddr3_dqs_n (ddr3_dqs_n),
.ddr3_dqs_p (ddr3_dqs_p),
.ddr3_odt (ddr3_odt),
.ddr3_ras_n (ddr3_ras_n),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_we_n (ddr3_we_n),
.gpio_lcd_tri_io (gpio_lcd),
.hdmi_16_data (hdmi_data),
.hdmi_16_data_e (hdmi_data_e),
.hdmi_16_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_16_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.gpio0_o (gpio_o[31:0]),
.gpio0_t (gpio_t[31:0]),
.gpio0_i (gpio_i[31:0]),
.gpio1_o (gpio_o[63:32]),
.gpio1_t (gpio_t[63:32]),
.gpio1_i (gpio_i[63:32]),
.mb_intr_02 (1'b0),
.mb_intr_03 (1'b0),
.mb_intr_06 (1'b0),
.mb_intr_12 (1'b0),
.mb_intr_13 (1'b0),
.mb_intr_14 (1'b0),
.mb_intr_15 (1'b0),
.mdio_mdc (mdio_mdc),
.mdio_mdio_io (mdio_mdio),
.mii_col (mii_col),
.mii_crs (mii_crs),
.mii_rst_n (mii_rst_n),
.mii_rx_clk (mii_rx_clk),
.mii_rx_dv (mii_rx_dv),
.mii_rx_er (mii_rx_er),
.mii_rxd (mii_rxd),
.mii_tx_clk (mii_tx_clk),
.mii_tx_en (mii_tx_en),
.mii_txd (mii_txd),
.linear_flash_addr (linear_flash_addr),
.linear_flash_adv_ldn (linear_flash_adv_ldn),
.linear_flash_ce_n (linear_flash_ce_n),
.linear_flash_dq_io (linear_flash_dq_io),
.linear_flash_oen (linear_flash_oen),
.linear_flash_wen (linear_flash_wen),
.spdif (spdif),
.sys_clk_n (sys_clk_n),
.sys_clk_p (sys_clk_p),
.sys_rst (sys_rst),
.uart_sin (uart_sin),
.uart_sout (uart_sout));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__PROBE_P_TB_V
`define SKY130_FD_SC_HVL__PROBE_P_TB_V
/**
* probe_p: Virtual voltage probe point.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__probe_p.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hvl__probe_p dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__PROBE_P_TB_V
|
module wasca (
abus_avalon_sdram_bridge_0_abus_address,
abus_avalon_sdram_bridge_0_abus_read,
abus_avalon_sdram_bridge_0_abus_waitrequest,
abus_avalon_sdram_bridge_0_abus_addressdata,
abus_avalon_sdram_bridge_0_abus_chipselect,
abus_avalon_sdram_bridge_0_abus_direction,
abus_avalon_sdram_bridge_0_abus_disable_out,
abus_avalon_sdram_bridge_0_abus_interrupt,
abus_avalon_sdram_bridge_0_abus_muxing,
abus_avalon_sdram_bridge_0_abus_writebyteenable_n,
abus_avalon_sdram_bridge_0_abus_reset,
abus_avalon_sdram_bridge_0_sdram_addr,
abus_avalon_sdram_bridge_0_sdram_ba,
abus_avalon_sdram_bridge_0_sdram_cas_n,
abus_avalon_sdram_bridge_0_sdram_cke,
abus_avalon_sdram_bridge_0_sdram_cs_n,
abus_avalon_sdram_bridge_0_sdram_dq,
abus_avalon_sdram_bridge_0_sdram_dqm,
abus_avalon_sdram_bridge_0_sdram_ras_n,
abus_avalon_sdram_bridge_0_sdram_we_n,
abus_avalon_sdram_bridge_0_sdram_clk,
altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_cmd,
altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat,
altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat3,
altera_up_sd_card_avalon_interface_0_conduit_end_o_SD_clock,
altpll_1_areset_conduit_export,
altpll_1_locked_conduit_export,
altpll_1_phasedone_conduit_export,
audio_out_BCLK,
audio_out_DACDAT,
audio_out_DACLRCK,
buffered_spi_mosi,
buffered_spi_clk,
buffered_spi_miso,
buffered_spi_cs,
clk_clk,
clock_116_mhz_clk,
reset_reset_n,
reset_controller_0_reset_in1_reset,
uart_0_external_connection_rxd,
uart_0_external_connection_txd);
input [9:0] abus_avalon_sdram_bridge_0_abus_address;
input abus_avalon_sdram_bridge_0_abus_read;
output abus_avalon_sdram_bridge_0_abus_waitrequest;
inout [15:0] abus_avalon_sdram_bridge_0_abus_addressdata;
input [2:0] abus_avalon_sdram_bridge_0_abus_chipselect;
output abus_avalon_sdram_bridge_0_abus_direction;
output abus_avalon_sdram_bridge_0_abus_disable_out;
output abus_avalon_sdram_bridge_0_abus_interrupt;
output [1:0] abus_avalon_sdram_bridge_0_abus_muxing;
input [1:0] abus_avalon_sdram_bridge_0_abus_writebyteenable_n;
input abus_avalon_sdram_bridge_0_abus_reset;
output [12:0] abus_avalon_sdram_bridge_0_sdram_addr;
output [1:0] abus_avalon_sdram_bridge_0_sdram_ba;
output abus_avalon_sdram_bridge_0_sdram_cas_n;
output abus_avalon_sdram_bridge_0_sdram_cke;
output abus_avalon_sdram_bridge_0_sdram_cs_n;
inout [15:0] abus_avalon_sdram_bridge_0_sdram_dq;
output [1:0] abus_avalon_sdram_bridge_0_sdram_dqm;
output abus_avalon_sdram_bridge_0_sdram_ras_n;
output abus_avalon_sdram_bridge_0_sdram_we_n;
output abus_avalon_sdram_bridge_0_sdram_clk;
inout altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_cmd;
inout altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat;
inout altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat3;
output altera_up_sd_card_avalon_interface_0_conduit_end_o_SD_clock;
input altpll_1_areset_conduit_export;
output altpll_1_locked_conduit_export;
output altpll_1_phasedone_conduit_export;
input audio_out_BCLK;
output audio_out_DACDAT;
input audio_out_DACLRCK;
output buffered_spi_mosi;
output buffered_spi_clk;
input buffered_spi_miso;
output buffered_spi_cs;
input clk_clk;
output clock_116_mhz_clk;
input reset_reset_n;
input reset_controller_0_reset_in1_reset;
input uart_0_external_connection_rxd;
output uart_0_external_connection_txd;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O211AI_PP_SYMBOL_V
`define SKY130_FD_SC_LS__O211AI_PP_SYMBOL_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o211ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input C1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O211AI_PP_SYMBOL_V
|
#include <bits/stdc++.h> constexpr int MAXN = 1e2 + 2; constexpr int MAXE = 1e4 + 4; using namespace std; int n; vector<double> choc, prefixSum, suffixSum, cpy; int main() { std::ios::sync_with_stdio(false); cin >> n; choc.resize(n), prefixSum.resize(n), suffixSum.resize(n); for (int i = 0; i < n; i++) { cin >> choc[i]; if (i == 0) prefixSum[0] = choc[0]; else prefixSum[i] = prefixSum[i - 1] + choc[i]; } for (int i = n - 1; i >= 0; i--) { if (i == n - 1) suffixSum[i] = choc[i]; else suffixSum[i] = suffixSum[i + 1] + choc[i]; } cpy = suffixSum; reverse(cpy.begin(), cpy.end()); double mid = prefixSum[n - 1] / 2; int midPos = upper_bound(prefixSum.begin(), prefixSum.end(), mid) - prefixSum.begin() - 1; int i = 0, j = n - 1; for (i = 0; i <= midPos; i++) { int tAlice = prefixSum[i]; j = upper_bound(cpy.begin(), cpy.end(), tAlice * 1.0) - cpy.begin() - 1; j = n - 1 - j; int tBob = suffixSum[j]; if (i + 1 == j) { if (tAlice - choc[i] > tBob) i--; else if (tAlice - choc[i] == tBob) break; break; } if (i + 2 == j) { if (tAlice == tBob) i++; else if (tAlice < tBob) i++; break; } if (i >= j) break; } cout << i + 1 << << n - i - 1 << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long int n; set<long long int> nos; long long powmod(long long x, long long y, long long m) { long long res = 1LL; while (y) { if (y & 1) res = (res * x) % m; x = (x * x) % m; y /= 2; } return res; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> n; long long int ans = 1; long long int buyt = 0; long long int selt = INT64_MAX; for (long long int i = 1; i <= n; i++) { string s; long long int val; cin >> s >> val; if (s == ADD ) nos.insert(val); else { nos.erase(val); if (buyt < val && selt > val) ans = (ans * 2) % 1000000007; else if (buyt == val || selt == val) ans = (ans * 1) % 1000000007; else ans = 0; auto it = nos.upper_bound(val); auto it1 = nos.lower_bound(val); if (it != nos.end()) selt = *it; else selt = INT64_MAX; if (it1 != nos.begin()) { it1--; buyt = *it1; } else { buyt = 0; } } } long long int m = 0; for (auto it = nos.begin(); it != nos.end(); it++) { long long int temp = *it; if (temp > buyt && temp < selt) m++; } ans = (ans * (m + 1)) % 1000000007; cout << ans << n ; }
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-12; int main() { int n; double r, v, T; scanf( %d%lf%lf , &n, &r, &v); T = 2 * acos(-1) * r / v; for (int i = 0; i < n; i++) { double s, f, tim, tot = 0; scanf( %lf%lf , &s, &f); tim = (f - s) / v; tot = T * floor(tim / T); tim -= tot; double lef = 0.0, rig = T; for (int j = 0; j < 100; j++) { double t = (lef + rig) / 2.0; double g = t + (2.0 * r / v) * sin(v * t / (2.0 * r)); if (g - tim >= -eps) rig = t; else lef = t; } tot += lef; printf( %.12lf n , tot); } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename A, typename B> string to_string(pair<A, B> p); template <typename A, typename B, typename C> string to_string(tuple<A, B, C> p); template <typename A, typename B, typename C, typename D> string to_string(tuple<A, B, C, D> p); string to_string(const string& s) { return + s + ; } string to_string(char ch) { string s; s += ch; return s; } string to_string(const char* s) { return to_string((string)s); } string to_string(bool b) { return (b ? true : false ); } string to_string(vector<bool> v) { bool first = true; string res = { ; for (int i = 0; i < static_cast<int>(v.size()); i++) { if (!first) { res += , ; } first = false; res += to_string(v[i]); } res += } ; return res; } template <size_t N> string to_string(bitset<N> v) { string res = ; for (size_t i = 0; i < N; i++) { res += static_cast<char>( 0 + v[i]); } return res; } template <typename A> string to_string(A v) { bool first = true; string res = { ; for (const auto& x : v) { if (!first) { res += , ; } first = false; res += to_string(x); } res += } ; return res; } template <typename A, typename B> string to_string(pair<A, B> p) { return ( + to_string(p.first) + , + to_string(p.second) + ) ; } template <typename A, typename B, typename C> string to_string(tuple<A, B, C> p) { return ( + to_string(get<0>(p)) + , + to_string(get<1>(p)) + , + to_string(get<2>(p)) + ) ; } template <typename A, typename B, typename C, typename D> string to_string(tuple<A, B, C, D> p) { return ( + to_string(get<0>(p)) + , + to_string(get<1>(p)) + , + to_string(get<2>(p)) + , + to_string(get<3>(p)) + ) ; } void debug_out() { cerr << endl; } template <typename Head, typename... Tail> void debug_out(Head H, Tail... T) { cerr << << to_string(H); debug_out(T...); } long long expmod(long long x, long long n, long long mod) { if (n == 0) return 1; else if (n % 2 == 0) { long long temp = expmod(x, n / 2, mod); return (temp * temp) % mod; } else { return (expmod(x, n - 1, mod) * x) % mod; } } long long modinv(long long x, long long mod) { return expmod(x, mod - 2, mod); } void solve() { int n; cin >> n; long long mod = 1e9 + 7; long long p = 0, q = 0; int even = 0; long long power = 2; for (int i = 0; i < n; i++) { long long x; cin >> x; even |= (x % 2 == 0); power = expmod(power, x, mod); } 42; power = power * modinv(2, mod) % mod; p = power + (even ? 1 : -1); p = (p + mod) % mod; p = p * modinv(3, mod) % mod; q = power; 42; cout << p << / << q << n ; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t = 1; for (int tc = 1; tc <= t; tc++) { solve(); } }
|
#include <bits/stdc++.h> using namespace std; int n, d, v[102], c, g[102], k, S; int main(void) { cin >> n >> d; for (int i = 1; i <= n; i++) cin >> v[i]; for (int i = 1; i < n; i++) { if (v[i] % 2) c++; else c--; if (c == 0) g[k++] = abs(v[i] - v[i + 1]); } sort(g, g + k); for (S = 0; S < k && d >= g[S]; S++) d -= g[S]; cout << S; }
|
#include <bits/stdc++.h> using namespace std; const int N = 200005; int n, t, k, ret; int a[N]; int sum[N]; int main() { scanf( %d%d%d , &n, &t, &k); int all = 0; sum[0] = 1; a[0] = 1; for (int i = 1; i <= t; i++) { scanf( %d , &a[i]); sum[i] = sum[i - 1] + a[i]; if (a[i] < a[i - 1]) ret += a[i - 1] - a[i]; } if (ret + a[t] > k || n - t < k) { printf( -1 n ); return 0; } printf( %d n , n); int fa = 1, now = 2; int need = n - t - k; for (int i = 1; i <= t; i++) { while (now <= sum[i]) { printf( %d %d n , fa, now); if (fa != sum[i - 1] && now != sum[i] && need > 0) { fa++; need--; } now++; } fa = sum[i - 1] + 1; } }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 100; const int inf = 0x3f3f3f3f; int n, m; long long ans; long long b[maxn], g[maxn]; bool cmp(int a, int b) { return a > b; } int main() { long long bmx = 0; int flag = 1, cnt = 0; scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) { scanf( %lld , &b[i]); ans += b[i] * m; bmx = max(bmx, b[i]); } sort(b + 1, b + 1 + n, cmp); for (int i = 1; i <= m; i++) { scanf( %lld , &g[i]); if (g[i] < bmx) flag = 0; if (g[i] > bmx) { cnt++; ans += g[i] - b[1 + cnt / m]; } } if (flag) { printf( %lld n , ans); } else { printf( -1 n ); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFBBN_TB_V
`define SKY130_FD_SC_LS__DFBBN_TB_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dfbbn.v"
module top();
// Inputs are registered
reg D;
reg SET_B;
reg RESET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
SET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 SET_B = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 D = 1'b1;
#180 RESET_B = 1'b1;
#200 SET_B = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 D = 1'b0;
#320 RESET_B = 1'b0;
#340 SET_B = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 SET_B = 1'b1;
#540 RESET_B = 1'b1;
#560 D = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 SET_B = 1'bx;
#680 RESET_B = 1'bx;
#700 D = 1'bx;
end
// Create a clock
reg CLK_N;
initial
begin
CLK_N = 1'b0;
end
always
begin
#5 CLK_N = ~CLK_N;
end
sky130_fd_sc_ls__dfbbn dut (.D(D), .SET_B(SET_B), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK_N(CLK_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFBBN_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPVGND2_FUNCTIONAL_V
`define SKY130_FD_SC_LS__TAPVGND2_FUNCTIONAL_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection 2
* rows down.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__tapvgnd2 ();
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPVGND2_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int n, t, z = 0; cin >> n >> t; if (n == 1 && t == 10) cout << -1 << endl; else if (t == 10) { for (int i = 0; i < n - 1; i++) { cout << 1; } cout << 0 << endl; } else { for (int i = 0; i < n; i++) { cout << t; } } return 0; }
|
`timescale 1ns/1ns
module mips(clk, rst, PrAddr, PrBe, PrRD, PrWD, HWInt);
input clk ;
// clock
input rst ;
// reset
output [31:0] PrWD;
output [31:2] PrAddr;
output [3:0] PrBe;
input [31:0] PrRD;
input [7:2] HWInt;
wire BJ_W,CMPSrc;
wire JType;
wire RegWrite,real_regwrite;
wire ShiftSrc,ALUSrc;
wire hilo,MULDIVstart,HILOWe,busy;
wire isDM,CP0_WE,IntReq;
wire isMFC0,isERET,isERET_e,isERET_m,isERET_w;
wire over,br;
wire stall;
wire [1:0] BEExtOp,real_beextop;
wire [1:0] EXOut;
wire [1:0] ExtOp;
wire [1:0] MULDIVOp;
wire [1:0] MemToReg;
wire [1:0] NPCOp;
wire [1:0] RegDst;
wire [1:0] memaddrE,memaddrW;
wire [1:0] real_npcop;
wire [2:0] CMPOp;
wire [2:0] EXTWbOp;
wire [3:0] ALUOp;
wire [3:0] BE;
wire [4:0] regdst;
wire [31:0] ALUOutM,ALUOutW;
wire [31:0] WriteDataM,WriteDataW;
wire [31:0] alusrc,aluout,memout,exout,cmpsrc;
wire [31:0] epc,cp0_out,cp0_pc;
wire [31:0] extwbout;
wire [31:0] hi,lo;
wire [31:0] imm,immE;
wire [31:0] instr,instrD,instrE,instrM,instrW;
wire [31:0] jtypeaddr;
wire [31:0] memstage_out;
wire [31:0] pc_im;
wire [31:0] pcplus,pcplusD,pcD,pcplusE,pcplusM,pcplusW,pctmp;
wire [31:0] shiftsrc;
wire [31:0] wd,rd1,rd2,rd1E,rd2E;
wire [31:0] npc_pc;
wire irq;
//hazard
hazard _hazard(instrD,instrE,instrM,MULDIVstart,busy,stall);
//forward_ctl
wire [2:0] ForwardRSD,ForwardRTD;
wire [2:0] ForwardRSE,ForwardRTE;
wire [1:0] ForwardRTM;
forward_ctl _forward_ctl(instrD,instrE,instrM,instrW,
ForwardRSD,ForwardRTD,
ForwardRSE,ForwardRTE,
ForwardRTM);
//muxs for forward
wire [31:0] FRSD,FRTD,FRSE,FRTE,FRTM;
assign FRSD=(ForwardRSD==3'b000)?rd1:
(ForwardRSD==3'b001)?ALUOutM:
(ForwardRSD==3'b010)?wd:
(ForwardRSD==3'b011)?pcplusM:
pcplusW;
assign FRTD=(ForwardRTD==3'b000)?(isMFC0?cp0_out:rd2):
(ForwardRTD==3'b001)?ALUOutM:
(ForwardRTD==3'b010)?wd:
(ForwardRTD==3'b011)?pcplusM:
pcplusW;
assign FRSE=(ForwardRSE==3'b000)?rd1E:
(ForwardRSE==3'b001)?ALUOutM:
(ForwardRSE==3'b010)?wd:
(ForwardRSE==3'b011)?pcplusM:
pcplusW;
assign FRTE=(ForwardRTE==3'b000)?rd2E:
(ForwardRTE==3'b001)?ALUOutM:
(ForwardRTE==3'b010)?wd:
(ForwardRTE==3'b011)?pcplusM:
pcplusW;
assign FRTM=(ForwardRTM==2'b00)?WriteDataM:
(ForwardRTM==2'b01)?wd:
pcplusW;
pc _pc(clk,rst,!(stall|isERET_e),npc_pc,pc_im,pcplus);
im_4k _im(pc_im[14:2],instr);
//---------------------------------
assign pctmp=(isERET_e)?npc_pc+4:pcplus;
if_id _if_id(clk,rst|IntReq|isERET_e,!stall,instr,pctmp,instrD,pcplusD);
assign regdst=(RegDst==2'b00)?instrW[20:16]:
(RegDst==2'b01)?instrW[15:11]:
31;
assign real_npcop=(IntReq)?2'b11:
(isERET)?2'b10:
(NPCOp!=2'b01)?NPCOp:
(br)?NPCOp:2'b00;
assign pcD=pcplusD-4;
assign jtypeaddr=(isERET)?epc:
(JType==0)?{pcD[31:28],instrD[25:0],2'b00}:
FRSD;
assign cmpsrc=(CMPSrc?32'h0000_0000:FRTD);
ctl_id _ctl_id(instrD,NPCOp,ExtOp,CMPOp,CMPSrc,JType,isMFC0,isERET);
gpr _gpr(clk,rst,real_regwrite,
instrD[25:21],
instrD[20:16],
regdst,wd,rd1,rd2);
cmp _cmp(FRSD,cmpsrc,CMPOp,br);
ext _ext(ExtOp,instrD[15:0],imm);
npc _npc(real_npcop,pcplus,pcplusD,instrD[15:0],jtypeaddr,npc_pc);
//----------------------------------
id_ex _id_ex(clk,rst|IntReq,stall,instrD,imm,rd1,rd2,pcplusD+4,instrE,immE,rd1E,rd2E,pcplusE);
assign alusrc=(ALUSrc==0)?FRTE:immE;
assign shiftsrc=(ShiftSrc)?{{27{1'b0}},instrE[10:6]}:FRSE;
assign exout=(EXOut==2'b01)?lo:
(EXOut==2'b10)?hi:
aluout;
ctl_ex _ctl_ex(instrE,ShiftSrc,ALUSrc,ALUOp,hilo,MULDIVOp,MULDIVstart,HILOWe,EXOut,isERET_e);
alu _alu(shiftsrc,alusrc,ALUOp,aluout,over);
muldiv _muldiv(FRSE,FRTE,hilo,MULDIVOp,MULDIVstart,HILOWe,busy,hi,lo,clk,rst);
//----------------------------------
ex_mem _ex_mem(clk,rst|IntReq,instrE,exout,FRTE,pcplusE,
instrM,ALUOutM,WriteDataM,pcplusM);
assign PrAddr=ALUOutM[31:2];
assign PrBe=BE;
assign PrWD=FRTM;
assign isDM=(ALUOutM<32'h0000_3000);
assign memaddrE=ALUOutM[1:0];
assign cp0_pc=BJ_W?pcplusW-8:pcplusM-8;
assign memstage_out=isDM?memout:PrRD;
assign real_beextop=(IntReq)?2'b11:BEExtOp;
assign IntReq=irq&(!stall)&(!isERET)&(!isERET_e)&(!isERET_m)&(!isERET_w);
ctl_mem _ctl_mem(instrM,BEExtOp,CP0_WE,isERET_m);
beext _beext(ALUOutM[1:0],BEExtOp,BE);
dm _dm(ALUOutM[12:2],FRTM,IntReq?4'b0000:BE,clk,memout);
cp0 _cp0(clk,rst,instrD[20:16],instrM[15:11],FRTM,cp0_pc,0,HWInt,IntReq?0:CP0_WE,irq,isERET_w,irq,epc,cp0_out);
//----------------------------------
mem_wb _mem_wb(clk,rst,instrM,memaddrE,memstage_out,ALUOutM,pcplusM,
instrW,memaddrW,WriteDataW,ALUOutW,pcplusW);
ctl_wb _ctl_wb(instrW,MemToReg,RegWrite,RegDst,EXTWbOp,BJ_W,isERET_w);
extwb _extwb(memaddrW,WriteDataW,EXTWbOp,extwbout);
assign wd=(MemToReg==2'b00)?ALUOutW:
(MemToReg==2'b01)?extwbout:
pcplusW;
assign real_regwrite=RegWrite&&(!IntReq);
endmodule // mips
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#include <bits/stdc++.h> struct { inline operator int() { int x; return scanf( %d , &x), x; } inline operator long long() { long long x; return scanf( %lld , &x), x; } template <class T> inline void operator()(T &x) { x = *this; } template <class T, class... A> inline void operator()(T &x, A &...a) { x = *this; this->operator()(a...); } } read; const int maxn = 300005; int l[maxn], r[maxn]; int main() { int T = read; while (T--) { int n = read; std::fill(l, l + n + 1, 0); std::fill(r, r + n + 1, 0); for (int i = 1; i <= n; i++) { int x = read; if (!l[x]) l[x] = i; r[x] = i; } int ans = 0, max = 0; for (int x = 1, y = 0, now = 0; x <= n; x++) if (l[x]) { if (r[y] < l[x]) ++now; else now = 1; ++ans; max = std::max(max, now); y = x; } ans -= max; printf( %d n , ans); } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DLATCH_P_PP_PG_N_BLACKBOX_V
`define SKY130_FD_SC_LP__UDP_DLATCH_P_PP_PG_N_BLACKBOX_V
/**
* udp_dlatch$P_pp$PG$N: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__udp_dlatch$P_pp$PG$N (
Q ,
D ,
GATE ,
NOTIFIER,
VPWR ,
VGND
);
output Q ;
input D ;
input GATE ;
input NOTIFIER;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DLATCH_P_PP_PG_N_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int N = 1000005; const int CS = 22; int cmax[N][CS], cmin[N][CS], ans[N]; int lt[CS]; int main() { int n, k; scanf( %d%d , &n, &k); for (int i = 1; i <= n; i++) { scanf( %d , &cmax[i][0]); cmax[i][0] *= 100; } for (int i = 1; i <= n; i++) scanf( %d , &cmin[i][0]); int cs = 1; for (int g = 1; g < n; g <<= 1, cs++) { int gg = g << 1; for (int i = 1; i <= n; i++) { if (i + gg - 1 > n) cmax[i][cs] = cmin[i][cs] = 0; else { cmax[i][cs] = max(cmax[i][cs - 1], cmax[i + g][cs - 1]); cmin[i][cs] = min(cmin[i][cs - 1], cmin[i + g][cs - 1]); } } } lt[0] = 1; for (int i = 1; i < cs; i++) lt[i] = lt[i - 1] << 1; for (int i = 1; i <= n; i++) { ans[i] = 0; int tmax = 0, tmin = 10000000; int mid = i; for (int j = cs - 1; j >= 0; j--) { if (cmax[mid][j] > 0) { int tmax2 = max(tmax, cmax[mid][j]); int tmin2 = min(tmin, cmin[mid][j]); ans[i] = max(ans[i], min(tmax2, tmin2)); if (tmax2 <= tmin2) { tmax = tmax2; tmin = tmin2; if (tmax == tmin) break; mid += lt[j]; if (mid > n) break; } } } } sort(ans + 1, ans + n + 1); double p = 1.0; double res = 0; for (int i = 1; i <= n - k + 1; i++) { if (p < 1e-20) break; double pp = k * 1.0 / (n - i + 1); res += p * pp * ans[i]; p *= (1 - pp); } printf( %.12f , res); return 0; }
|
/* This file is part of JT12.
JT12 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 14-2-2017
*/
module jt12_csr( // Circular Shift Register + input mux
input rst,
input clk,
input clk_en /* synthesis direct_enable */,
input [ 7:0] din,
input [43:0] shift_in,
output [43:0] shift_out,
input up_tl,
input up_dt1,
input up_ks_ar,
input up_amen_dr,
input up_sr,
input up_sl_rr,
input up_ssgeg,
input update_op_I,
input update_op_II,
input update_op_IV
);
localparam regop_width=44;
reg [regop_width-1:0] regop_in;
jt12_sh_rst #(.width(regop_width),.stages(12)) u_regch(
.clk ( clk ),
.clk_en ( clk_en ),
.rst ( rst ),
.din ( regop_in ),
.drop ( shift_out )
);
wire up_tl_op = up_tl & update_op_IV;
wire up_dt1_op = up_dt1 & update_op_I;
wire up_mul_op = up_dt1 & update_op_II;
wire up_ks_op = up_ks_ar & update_op_II;
wire up_ar_op = up_ks_ar & update_op_I;
wire up_amen_op = up_amen_dr& update_op_IV;
wire up_dr_op = up_amen_dr& update_op_I;
wire up_sr_op = up_sr & update_op_I;
wire up_sl_op = up_sl_rr & update_op_I;
wire up_rr_op = up_sl_rr & update_op_I;
wire up_ssg_op = up_ssgeg & update_op_I;
always @(*)
regop_in = {
up_tl_op ? din[6:0] : shift_in[43:37], // 7
up_dt1_op ? din[6:4] : shift_in[36:34], // 3
up_mul_op ? din[3:0] : shift_in[33:30], // 4
up_ks_op ? din[7:6] : shift_in[29:28], // 2
up_ar_op ? din[4:0] : shift_in[27:23], // 5
up_amen_op ? din[7] : shift_in[ 22], // 1
up_dr_op ? din[4:0] : shift_in[21:17], // 5
up_sr_op ? din[4:0] : shift_in[16:12], // 5
up_sl_op ? din[7:4] : shift_in[11: 8], // 4
up_rr_op ? din[3:0] : shift_in[ 7: 4], // 4
up_ssg_op ? din[3:0] : shift_in[ 3: 0] // 4
};
endmodule // jt12_reg
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_nios2_gen2_0_cpu_mult_cell (
// inputs:
E_src1,
E_src2,
M_en,
clk,
reset_n,
// outputs:
M_mul_cell_p1,
M_mul_cell_p2,
M_mul_cell_p3
)
;
output [ 31: 0] M_mul_cell_p1;
output [ 31: 0] M_mul_cell_p2;
output [ 31: 0] M_mul_cell_p3;
input [ 31: 0] E_src1;
input [ 31: 0] E_src2;
input M_en;
input clk;
input reset_n;
wire [ 31: 0] M_mul_cell_p1;
wire [ 31: 0] M_mul_cell_p2;
wire [ 31: 0] M_mul_cell_p3;
wire mul_clr;
wire [ 31: 0] mul_src1;
wire [ 31: 0] mul_src2;
assign mul_clr = ~reset_n;
assign mul_src1 = E_src1;
assign mul_src2 = E_src2;
altera_mult_add the_altmult_add_p1
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (mul_src1[15 : 0]),
.datab (mul_src2[15 : 0]),
.ena0 (M_en),
.result (M_mul_cell_p1)
);
defparam the_altmult_add_p1.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_p1.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_p1.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_p1.dedicated_multiplier_circuitry = "YES",
the_altmult_add_p1.input_register_a0 = "UNREGISTERED",
the_altmult_add_p1.input_register_b0 = "UNREGISTERED",
the_altmult_add_p1.input_source_a0 = "DATAA",
the_altmult_add_p1.input_source_b0 = "DATAB",
the_altmult_add_p1.lpm_type = "altera_mult_add",
the_altmult_add_p1.multiplier1_direction = "ADD",
the_altmult_add_p1.multiplier_aclr0 = "ACLR0",
the_altmult_add_p1.multiplier_register0 = "CLOCK0",
the_altmult_add_p1.number_of_multipliers = 1,
the_altmult_add_p1.output_register = "UNREGISTERED",
the_altmult_add_p1.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_p1.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_p1.representation_a = "UNSIGNED",
the_altmult_add_p1.representation_b = "UNSIGNED",
the_altmult_add_p1.selected_device_family = "MAX10",
the_altmult_add_p1.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_p1.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_p1.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_p1.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_p1.signed_register_a = "UNREGISTERED",
the_altmult_add_p1.signed_register_b = "UNREGISTERED",
the_altmult_add_p1.width_a = 16,
the_altmult_add_p1.width_b = 16,
the_altmult_add_p1.width_result = 32;
altera_mult_add the_altmult_add_p2
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (mul_src1[15 : 0]),
.datab (mul_src2[31 : 16]),
.ena0 (M_en),
.result (M_mul_cell_p2)
);
defparam the_altmult_add_p2.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_p2.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_p2.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_p2.dedicated_multiplier_circuitry = "YES",
the_altmult_add_p2.input_register_a0 = "UNREGISTERED",
the_altmult_add_p2.input_register_b0 = "UNREGISTERED",
the_altmult_add_p2.input_source_a0 = "DATAA",
the_altmult_add_p2.input_source_b0 = "DATAB",
the_altmult_add_p2.lpm_type = "altera_mult_add",
the_altmult_add_p2.multiplier1_direction = "ADD",
the_altmult_add_p2.multiplier_aclr0 = "ACLR0",
the_altmult_add_p2.multiplier_register0 = "CLOCK0",
the_altmult_add_p2.number_of_multipliers = 1,
the_altmult_add_p2.output_register = "UNREGISTERED",
the_altmult_add_p2.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_p2.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_p2.representation_a = "UNSIGNED",
the_altmult_add_p2.representation_b = "UNSIGNED",
the_altmult_add_p2.selected_device_family = "MAX10",
the_altmult_add_p2.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_p2.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_p2.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_p2.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_p2.signed_register_a = "UNREGISTERED",
the_altmult_add_p2.signed_register_b = "UNREGISTERED",
the_altmult_add_p2.width_a = 16,
the_altmult_add_p2.width_b = 16,
the_altmult_add_p2.width_result = 32;
altera_mult_add the_altmult_add_p3
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (mul_src1[31 : 16]),
.datab (mul_src2[15 : 0]),
.ena0 (M_en),
.result (M_mul_cell_p3)
);
defparam the_altmult_add_p3.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_p3.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_p3.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_p3.dedicated_multiplier_circuitry = "YES",
the_altmult_add_p3.input_register_a0 = "UNREGISTERED",
the_altmult_add_p3.input_register_b0 = "UNREGISTERED",
the_altmult_add_p3.input_source_a0 = "DATAA",
the_altmult_add_p3.input_source_b0 = "DATAB",
the_altmult_add_p3.lpm_type = "altera_mult_add",
the_altmult_add_p3.multiplier1_direction = "ADD",
the_altmult_add_p3.multiplier_aclr0 = "ACLR0",
the_altmult_add_p3.multiplier_register0 = "CLOCK0",
the_altmult_add_p3.number_of_multipliers = 1,
the_altmult_add_p3.output_register = "UNREGISTERED",
the_altmult_add_p3.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_p3.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_p3.representation_a = "UNSIGNED",
the_altmult_add_p3.representation_b = "UNSIGNED",
the_altmult_add_p3.selected_device_family = "MAX10",
the_altmult_add_p3.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_p3.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_p3.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_p3.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_p3.signed_register_a = "UNREGISTERED",
the_altmult_add_p3.signed_register_b = "UNREGISTERED",
the_altmult_add_p3.width_a = 16,
the_altmult_add_p3.width_b = 16,
the_altmult_add_p3.width_result = 32;
endmodule
|
#include <bits/stdc++.h> using namespace std; inline long long add(long long a, long long b, long long p = 1000000007) { long long c = a + b; if (c >= p) c -= p; return c; } inline long long sub(long long a, long long b, long long p = 1000000007) { long long c = a - b; if (c < 0) c += p; return c; } inline long long mul(long long a, long long b, long long p = 1000000007) { return ((a % p) * (b % p)) % p; } long long power(long long x, long long y, long long p = 1000000007) { long long res = 1; x = x % p; if (x == 0) return 0; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res; } vector<int> g[200005]; int t = 0; int tim[500005]; void dfs(int u, int v = -1) { tim[t++] = u; for (auto x : g[u]) { if (x == v) continue; dfs(x, u); } tim[t++] = u; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; int a; cin >> n; int p[n + 1]; for (int i = 2; i <= n; i++) { cin >> a; g[i].push_back(a); g[a].push_back(i); } dfs(1); map<int, int> mp; for (int i = 0; i <= 2 * n - 1; i++) { mp[tim[i]]++; if (tim[i] == n) break; } for (auto it = mp.begin(); it != mp.end(); it++) { if (it->second == 1) { cout << it->first << ; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; scanf( %d%d , &n, &m); vector<vector<pair<int, int> > > e(n, vector<pair<int, int> >()); for (int i = 1; i < n; ++i) { int u, v, d; scanf( %d%d%d , &u, &v, &d); e[--u].push_back(make_pair(--v, d)); } vector<pair<int, int> > info; vector<set<int> > adt(n, set<int>()), eve(n, set<int>()); for (int i = 0; i < m; ++i) { int s, t; scanf( %d%d , &s, &t); info.push_back(make_pair(--s, t)); adt[s].insert(i); } vector<pair<long long, long long> > seg, rseg; auto upd_seg = [&](int x, int y, long long adt, bool add = 1) { auto tmp = make_pair(info[x].second + adt, info[y].second + adt); if (add) { seg.push_back(tmp); } else { rseg.push_back(tmp); } }; vector<int> dsu(n, -1); function<int(int)> dsu_find = [&](int u) { return dsu[u] < 0 ? u : (dsu[u] = dsu_find(dsu[u])); }; auto dsu_check = [&](int x, int y) { return dsu_find(info[x].first) == dsu_find(info[y].first); }; function<void(int, long long)> dfs = [&](int u, long long dis) { for (auto &it : e[u]) { int &v = it.first; dfs(v, dis + it.second); if (eve[u].size() < eve[v].size()) eve[u].swap(eve[v]); set<int>::iterator vL = eve[v].begin(); while (vL != eve[v].end()) { set<int>::iterator uR = eve[u].lower_bound(*vL); if (uR != eve[u].begin()) { set<int>::iterator uL = uR; --uL; if (uR != eve[u].end() && !dsu_check(*uL, *uR)) upd_seg(*uL, *uR, dis, 0); upd_seg(*uL, *vL, dis); } if (uR == eve[u].end()) { eve[u].insert(vL, eve[v].end()); vL = eve[v].end(); } else { int upp = *uR; set<int>::iterator vR = vL; while (vR != eve[v].end() && *vR < upp) { eve[u].insert(*vR); vL = vR++; } upd_seg(*vL, upp, dis); if (vR != eve[v].end() && !dsu_check(*vL, *vR)) upd_seg(*vL, *vR, dis, 0); ++vL; } } set<int>().swap(eve[v]); } if (!eve[u].empty()) { int low = *eve[u].begin(); if (dsu_find(info[low].first) != e[u].back().first) seg.push_back(make_pair(0LL, info[low].second + dis)); } eve[u].insert(adt[u].begin(), adt[u].end()); set<int>().swap(adt[u]); for (auto &it : e[u]) dsu[it.first] = u; }; dfs(0, 0); sort(seg.begin(), seg.end()); sort(rseg.begin(), rseg.end()); auto it = seg.begin(), jt = it, kt = rseg.begin(); while (it != seg.end()) { if (kt != rseg.end() && *it == *kt) { ++kt; } else if (it == jt) { ++jt; } else { *(jt++) = *it; } ++it; } assert(kt == rseg.end()); seg.erase(jt, seg.end()); long long cur = 0, lim = -1; it = seg.begin(); priority_queue<long long, vector<long long>, greater<long long> > Q; while (it != seg.end() || !Q.empty()) { if (Q.empty() && (it->first) > cur) cur = it->first; while (it != seg.end() && (it->first) <= cur) Q.push((it++)->second); long long upp = Q.top(); Q.pop(); if (cur >= upp) { lim = upp; break; } ++cur; } int cnt = 0; if (lim == -1) { cnt += (int)seg.size(); } else { for (auto &it : seg) cnt += it.second < lim; } printf( %lld %d n , lim, cnt); return 0; }
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/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2015 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file Ram.v when simulating
// the core, Ram. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module Ram(
clka,
wea,
addra,
dina,
douta
);
input clka;
input [0 : 0] wea;
input [12 : 0] addra;
input [31 : 0] dina;
output [31 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(13),
.C_ADDRB_WIDTH(13),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("Ram.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(0),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(8192),
.C_READ_DEPTH_B(8192),
.C_READ_WIDTH_A(32),
.C_READ_WIDTH_B(32),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(8192),
.C_WRITE_DEPTH_B(8192),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:04:40 05/25/2015
// Design Name:
// Module Name: seven_segment_leds_x_8
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments: Note that the segments are a_to_g with a in position 0, b in position 1, etc.
// The reverse assignments are commented out to the right.
// To turn off decimal point set the corresponding bit low.
//
//////////////////////////////////////////////////////////////////////////////////
module seven_segment_leds_x_8(
input [31:0] bcd_in,
input [7:0] decimal_points,
input clk,
output reg [6:0] a_to_g,
output reg decimal_point,
output reg [7:0] anode
);
wire [2:0] counter;
reg [3:0] digit;
reg [20:0] clkdiv;
assign counter = clkdiv[20:18]; //count every 2.6 ms (with 100 MHz clock)
//4 to 1 MUX
always @(posedge clk)
case(counter)
0: {digit, decimal_point} = {bcd_in[3:0], ~decimal_points[0]};
1: {digit, decimal_point} = {bcd_in[7:4], ~decimal_points[1]};
2: {digit, decimal_point} = {bcd_in[11:8], ~decimal_points[2]};
3: {digit, decimal_point} = {bcd_in[15:12], ~decimal_points[3]};
4: {digit, decimal_point} = {bcd_in[19:16], ~decimal_points[4]};
5: {digit, decimal_point} = {bcd_in[23:20], ~decimal_points[5]};
6: {digit, decimal_point} = {bcd_in[27:24], ~decimal_points[6]};
7: {digit, decimal_point} = {bcd_in[31:28], ~decimal_points[7]};
endcase
//7-segment decoder
always @(posedge clk)
case(digit)
0: a_to_g = 8'b1000000; //8'b0000001;
1: a_to_g = 8'b1111001; //8'b1001111;
2: a_to_g = 8'b0100100; //8'b0010010;
3: a_to_g = 8'b0110000; //8'b0000110;
4: a_to_g = 8'b0011001; //8'b1001100;
5: a_to_g = 8'b0010010; //8'b0100100;
6: a_to_g = 8'b0000010; //8'b0100000;
7: a_to_g = 8'b1111000; //8'b0001111;
8: a_to_g = 8'b0000000; //8'b0000000;
9: a_to_g = 8'b0010000; //8'b0000100;
default: a_to_g = 8'b11111111; //default to blank
endcase
//digit selector
always @(posedge clk)
case(counter)
0: anode = 8'b11111110;
1: anode = 8'b11111101;
2: anode = 8'b11111011;
3: anode = 8'b11110111;
4: anode = 8'b11101111;
5: anode = 8'b11011111;
6: anode = 8'b10111111;
7: anode = 8'b01111111;
default: anode = 8'b11111111; //all blank
endcase
//clock divider
always @ (posedge clk)
begin
clkdiv <= clkdiv + 21'b1;
end
endmodule
|
#include <bits/stdc++.h> int main() { int i, j, k, p, r, n, c = 0; scanf( %d , &n); char s[1000000]; scanf( %s , s); for (i = 0; i < n - 2; i++) { if (s[i] == s[i + 1]) { c++; if (s[i] == G ) { if (s[i + 2] == R ) s[i + 1] = B ; else if (s[i + 2] == B ) s[i + 1] = R ; else if (s[i + 2] == G ) s[i + 1] = B ; } else if (s[i] == R ) { if (s[i + 2] == G ) s[i + 1] = B ; else if (s[i + 2] == B ) s[i + 1] = G ; else if (s[i + 2] == R ) s[i + 1] = B ; } else if (s[i] == B ) { if (s[i + 2] == R ) s[i + 1] = G ; else if (s[i + 2] == G ) s[i + 1] = R ; else if (s[i + 2] == B ) s[i + 1] = G ; } } } if (s[n - 1] == s[n - 2]) { c++; if (s[n - 2] == R ) s[n - 1] = G ; else if (s[n - 2] == G ) s[n - 1] = R ; else if (s[n - 2] == B ) s[n - 1] = G ; } printf( %d n , c); puts(s); }
|
#include <bits/stdc++.h> using ll = long long; const ll LINF = 1e13; using namespace std; namespace ProconLib { template <typename cost_t = long long, bool hasNegativeCost = false, cost_t INF = LINF> class Flow { public: struct Edge { int to; cost_t cap, rev; cost_t cost; }; using Edges = vector<Edge>; using Graph = vector<Edges>; private: int N; Graph g; vector<int> level; vector<int> iter; void bfs(int s); cost_t dfs(int v, int t, cost_t f); public: Flow(int N) : N(N), g(N){}; void addEdge(int from, int to, cost_t cap); void addEdge(int from, int to, cost_t cap, cost_t cost); cost_t maxFlow(int s, int t); cost_t minCostFlow(int s, int t, cost_t f); }; template <typename cost_t, bool hasNegativeCost, cost_t INF> void Flow<cost_t, hasNegativeCost, INF>::addEdge(int from, int to, cost_t cap) { g[from].push_back({to, cap, int(g[to].size()), 0}); g[to].push_back({from, cost_t(0), int(g[from].size()) - 1, 0}); } template <typename cost_t, bool hasNegativeCost, cost_t INF> void Flow<cost_t, hasNegativeCost, INF>::addEdge(int from, int to, cost_t cap, cost_t cost) { g[from].push_back({to, cap, int(g[to].size()), cost}); g[to].push_back({from, cost_t(0), int(g[from].size()) - 1, -cost}); } template <typename cost_t, bool hasNegativeCost, cost_t INF> cost_t Flow<cost_t, hasNegativeCost, INF>::maxFlow(int s, int t) { cost_t flow = 0; while (true) { bfs(s); if (level[t] < 0) return flow; iter.assign(N, 0); cost_t f; while ((f = dfs(s, t, INF)) > 0) { flow += f; } } } template <typename cost_t, bool hasNegativeCost, cost_t INF> void Flow<cost_t, hasNegativeCost, INF>::bfs(int s) { level.assign(N, -1); queue<int> que; level[s] = 0; que.push(s); while (!que.empty()) { int v = que.front(); que.pop(); for (int i = 0; i < g[v].size(); i++) { Edge& e = g[v][i]; if (e.cap > 0 && level[e.to] < 0) { level[e.to] = level[v] + 1; que.push(e.to); } } } } template <typename cost_t, bool hasNegativeCost, cost_t INF> cost_t Flow<cost_t, hasNegativeCost, INF>::dfs(int v, int t, cost_t f) { if (v == t) return f; for (int& i = iter[v]; i < g[v].size(); i++) { Edge& e = g[v][i]; if (e.cap > 0 && level[v] < level[e.to]) { cost_t d = dfs(e.to, t, min(f, e.cap)); if (d > 0) { e.cap -= d; g[e.to][e.rev].cap += d; return d; } } } return 0; } template <typename cost_t, bool hasNegativeCost, cost_t INF> cost_t Flow<cost_t, hasNegativeCost, INF>::minCostFlow(int s, int t, cost_t f) { using P = pair<cost_t, int>; cost_t res = 0; vector<cost_t> h(N, 0); vector<int> used(N), preve(N), prevv(N); vector<cost_t> dist(N); while (f > 0) { fill(dist.begin(), dist.end(), INF); dist[s] = 0; if (!hasNegativeCost) { fill(used.begin(), used.end(), 0); priority_queue<P, vector<P>, greater<P>> que; que.push(make_pair(cost_t(0), s)); while (!que.empty()) { P p = que.top(); que.pop(); int v = p.second; if (used[v]) continue; used[v] = true; for (int i = 0; i < g[v].size(); i++) { Edge& e = g[v][i]; if (e.cap > 0 && dist[e.to] > dist[v] + e.cost + h[v] - h[e.to]) { dist[e.to] = dist[v] + e.cost + h[v] - h[e.to]; prevv[e.to] = v; preve[e.to] = i; que.push(make_pair(dist[e.to], e.to)); } } } } else { bool update = true; while (update) { update = false; for (int v = 0; v < N; v++) { if (dist[v] == INF) continue; for (int i = 0; i < g[v].size(); i++) { Edge& e = g[v][i]; if (e.cap > 0 && dist[e.to] > dist[v] + e.cost) { dist[e.to] = dist[v] + e.cost; prevv[e.to] = v; preve[e.to] = i; update = true; } } } } } if (dist[t] == INF) { return -1; } if (!hasNegativeCost) { for (int v = 0; v < N; v++) h[v] += dist[v]; } cost_t d = f; for (int v = t; v != s; v = prevv[v]) { d = min(d, g[prevv[v]][preve[v]].cap); } f -= d; if (!hasNegativeCost) { res += d * h[t]; } else { res += d * dist[t]; } for (int v = t; v != s; v = prevv[v]) { Edge& e = g[prevv[v]][preve[v]]; e.cap -= d; g[v][e.rev].cap += d; } } return res; } } // namespace ProconLib struct Spaceship { int x, a, f, p; }; struct Base { int x, d, g; }; using namespace ProconLib; using vvi = vector<vector<int>>; void dfs(int v, vvi& g, vector<int>& used, vector<int>& vs) { used[v] = true; vs.push_back(v); for (auto to : g[v]) { if (used[to]) continue; dfs(to, g, used, vs); } } int main() { int n, m; cin >> n >> m; vector<vector<int>> dist(n, vector<int>(n, 1e9 + 5)); for (int i = 0; i < m; i++) { int u, v; cin >> u >> v; u--, v--; dist[u][v] = 1; dist[v][u] = 1; } for (int i = 0; i < n; i++) dist[i][i] = 0; int s, b, k; cin >> s >> b >> k; vector<Spaceship> ship(s); for (int i = 0; i < s; i++) { cin >> ship[i].x >> ship[i].a >> ship[i].f >> ship[i].p, ship[i].x--; } vector<Base> base(b); for (int i = 0; i < b; i++) { cin >> base[i].x >> base[i].d >> base[i].g; base[i].x--; } vvi sg(s); for (int i = 0; i < k; i++) { int s1, s2; cin >> s1 >> s2; s1--, s2--; sg[s1].push_back(s2); } for (int k = 0; k < n; k++) { for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { dist[i][j] = min(dist[i][j], dist[i][k] + dist[k][j]); } } } vector<ll> profit(s, -LINF); vector<vector<int>> bids(n); for (int i = 0; i < b; i++) { bids[base[i].x].push_back(i); } auto cmp = [&](int lhs, int rhs) { return base[lhs].d < base[rhs].d; }; for (int i = 0; i < n; i++) sort(bids[i].begin(), bids[i].end(), cmp); vector<vector<int>> accMax(n); for (int i = 0; i < n; i++) { accMax[i].resize(bids[i].size() + 1); for (int j = 0; j < bids[i].size(); j++) { accMax[i][j + 1] = max(accMax[i][j], base[bids[i][j]].g); } } for (int i = 0; i < s; i++) { int x = ship[i].x; for (int v = 0; v < n; v++) { if (dist[x][v] <= ship[i].f) { int lb = -1, ub = bids[v].size(); while (ub - lb > 1) { int mid = (lb + ub) / 2; if (base[bids[v][mid]].d <= ship[i].a) lb = mid; else ub = mid; } ll sc = accMax[v][ub] - ship[i].p; if (ub > 0) profit[i] = max(profit[i], sc); } } } auto doFlow = [&](const vvi& graph, const vector<ll>& mpPro) { int n = graph.size(); const int S = n; const int T = n + 1; Flow<ll> flow(n + 2); ll sum = 0; for (int i = 0; i < n; i++) { if (mpPro[i] > 0) { sum += mpPro[i]; flow.addEdge(S, i, mpPro[i]); flow.addEdge(i, T, 0); } else { flow.addEdge(S, i, 0); flow.addEdge(i, T, -mpPro[i]); } } for (int i = 0; i < n; i++) { for (auto to : graph[i]) { flow.addEdge(i, to, LINF); } } return sum - flow.maxFlow(S, T); }; vvi undirSG(s); for (int i = 0; i < s; i++) { for (auto to : sg[i]) { undirSG[i].push_back(to); undirSG[to].push_back(i); } } ll res = 0; vector<int> used(s); for (int i = 0; i < s; i++) { if (!used[i]) { vector<int> vs; dfs(i, undirSG, used, vs); if (vs.size() == 1) { if (profit[i] > 0) res += profit[i]; continue; } map<int, int> mp; int id = 0; for (auto v : vs) { mp[v] = id++; } vvi mapG(id); vector<ll> mpPro(id); for (auto v : vs) { mpPro[mp[v]] = profit[v]; for (auto to : sg[v]) { mapG[mp[v]].push_back(mp[to]); } } res += doFlow(mapG, mpPro); } } cout << res << endl; return 0; }
|
// file: Test_AXI_Master_simple_v1_0_hw_1_clk_wiz_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1_____7.373______0.000______50.0______624.752____391.211
// CLK_OUT2____23.997______0.000______50.0______511.434____391.211
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "Test_AXI_Master_simple_v1_0_hw_1_clk_wiz_0,clk_wiz_v5_1,{component_name=Test_AXI_Master_simple_v1_0_hw_1_clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module Test_AXI_Master_simple_v1_0_hw_1_clk_wiz_0
(
// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
output clk_out2
);
Test_AXI_Master_simple_v1_0_hw_1_clk_wiz_0_clk_wiz inst
(
// Clock in ports
.clk_in1(clk_in1),
// Clock out ports
.clk_out1(clk_out1),
.clk_out2(clk_out2)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int Maxn = 200020; int n, a[Maxn]; long long sum[Maxn]; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , a + i); for (int i = 0; i < n - 1; i++) { int cur; for (cur = 1; cur <= i;) { int val = i / cur; int ncur = i / val + 1; if (a[i + 2] < a[val + 1]) { sum[cur]++; sum[ncur]--; } cur = ncur; } if (a[i + 2] < a[1]) sum[cur]++, sum[n]--; } for (int i = 1; i < n; i++) sum[i] += sum[i - 1], printf( %I64d n , sum[i]); ; }
|
#include <bits/stdc++.h> using namespace std; void fio() {} void pti() { double timeuse = clock() * 1000.0 / CLOCKS_PER_SEC; cerr << Timeuse << timeuse << ms << endl; } void end() { exit(0); } namespace io { const int SIZ = 55; int que[SIZ], op, qr; char ch; template <class I> inline void gi(I& w) { ch = getchar(), op = 1, w = 0; while (!isdigit(ch)) { if (ch == - ) op = -1; ch = getchar(); } while (isdigit(ch)) { w = w * 10 + ch - 0 ; ch = getchar(); } w *= op; } template <typename T, typename... Args> inline void gi(T& t, Args&... args) { gi(t); gi(args...); } template <class I> inline void print(I w) { qr = 0; if (!w) putchar( 0 ); if (w < 0) putchar( - ), w = -w; while (w) que[++qr] = w % 10 + 0 , w /= 10; while (qr) putchar(que[qr--]); } } // namespace io using io::gi; using io::print; const int N = 5005; int n, m; int a[N]; int main() { fio(); gi(n, m); int t = 0; for (int i = 1; i <= n; ++i) { a[i] = i; t += (i - 1) >> 1; if (t >= m) { int res = (t - m) << 1; a[i] += res; for (int j = n, s = 1e9; j > i; --j, s -= a[i] + 1) a[j] = s; for (int j = 1; j <= n; ++j) print(a[j]), putchar( ); end(); } } print(-1); end(); }
|
//
// Maintains the replacement policy for an array of elements
// The scheme is synchronously updated when v_i goes high, and asynchronously
// outputs the selected way for replacement based on internal and emptiness
//
// Currently supported schemes
// LRU:
// - Both alloc and read operations update LRU in parallel
// - Allocation is performed logically before the read update
// - If the read and alloc refer to the same set, all is well,
// since the LRU update is idempotent.
`include "bsg_defines.v"
module bsg_cam_1r1w_replacement
#(parameter els_p = 2
// Which replacement scheme to use
, parameter scheme_p = "lru"
, parameter safe_els_lp = `BSG_MAX(els_p,1)
)
(input clk_i
, input reset_i
// Synchronous update (i.e. indicate that an entry was read)
, input [safe_els_lp-1:0] read_v_i
// May use combination of internal state and empty vector
// to determine replacement
// Synchronous update (i.e. indicate that an entry was allocated)
, input alloc_v_i
, input [safe_els_lp-1:0] alloc_empty_i
, output [safe_els_lp-1:0] alloc_v_o
);
if (els_p == 0)
begin : zero
assign alloc_v_o = 1'b0;
end
else if (els_p == 1)
begin : one
assign alloc_v_o = 1'b1;
end
// Standard tree-based pseudo-lru
else if (scheme_p == "lru")
begin : lru
localparam lg_els_lp = `BSG_SAFE_CLOG2(els_p);
wire read_v_li = |read_v_i;
wire lru_touch_li = read_v_li | alloc_v_i;
// LRU storage
logic [els_p-2:0] lru_n, lru_r;
bsg_dff_reset_en
#(.width_p(els_p-1))
lru_reg
(.clk_i(clk_i)
,.reset_i(reset_i)
,.en_i(lru_touch_li)
,.data_i(lru_n)
,.data_o(lru_r)
);
//
// Selection output logic
//
// Encode the one-hot way select based on LRU
logic [lg_els_lp-1:0] lru_way_lo;
bsg_lru_pseudo_tree_encode
#(.ways_p(els_p))
lru_encoder
(.lru_i(lru_r)
,.way_id_o(lru_way_lo)
);
// Find an empty way if one exists
logic [lg_els_lp-1:0] empty_way_lo;
logic empty_way_v_lo;
bsg_priority_encode
#(.width_p(els_p), .lo_to_hi_p(1))
empty_encoder
(.i(alloc_empty_i)
,.addr_o(empty_way_lo)
,.v_o(empty_way_v_lo)
);
// Select the empty way if one exists; else, use LRU
wire [lg_els_lp-1:0] way_lo = empty_way_v_lo ? empty_way_lo : lru_way_lo;
// Output the one-hot way selected
bsg_decode
#(.num_out_p(els_p))
way_decoder
(.i(way_lo)
,.o(alloc_v_o)
);
//
// LRU update logic
//
// Encode the one-hot way read inputs to this module
logic [lg_els_lp-1:0] read_way_li;
bsg_encode_one_hot
#(.width_p(els_p))
read_way_encoder
(.i(read_v_i)
,.addr_o(read_way_li)
,.v_o()
);
// Decides which way to update based on read MRU
logic [els_p-2:0] read_update_data_lo, read_update_mask_lo;
bsg_lru_pseudo_tree_decode
#(.ways_p(els_p))
read_decoder
(.way_id_i(read_way_li)
,.data_o(read_update_data_lo)
,.mask_o(read_update_mask_lo)
);
// Muxes in the update data to compute the next LRU state
// This doesn't get latched in unless there's an active use
logic [els_p-2:0] read_update_lo;
wire [els_p-2:0] read_sel_lo = read_update_mask_lo & {(els_p-1){read_v_li}};
bsg_mux_bitwise
#(.width_p(els_p-1))
read_update_mux
(.data0_i(lru_r)
,.data1_i(read_update_data_lo)
,.sel_i(read_sel_lo)
,.data_o(read_update_lo)
);
// Decides which way to update based on write MRU
logic [els_p-2:0] alloc_update_data_lo, alloc_update_mask_lo;
bsg_lru_pseudo_tree_decode
#(.ways_p(els_p))
alloc_decoder
(.way_id_i(way_lo)
,.data_o(alloc_update_data_lo)
,.mask_o(alloc_update_mask_lo)
);
logic [els_p-2:0] alloc_update_lo;
wire [els_p-2:0] alloc_sel_lo = alloc_update_mask_lo & {(els_p-1){alloc_v_i}};
bsg_mux_bitwise
#(.width_p(els_p-1))
alloc_update_mux
(.data0_i(read_update_lo)
,.data1_i(alloc_update_data_lo)
,.sel_i(alloc_sel_lo)
,.data_o(alloc_update_lo)
);
assign lru_n = alloc_update_lo;
end
initial
begin
assert (scheme_p == "lru") else $error("Only LRU scheme is currently supported");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1010 + 1; const double EPS = 1E-8; int n; double a[MAXN], low[MAXN], high[MAXN], mmin, mmax; int main() { scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %lf , &a[i]); if (i) { low[i] = 10 * a[i] / (i + 1); high[i] = 10 * (a[i] + 1) / (i + 1); mmin = max(mmin, low[i]); mmax = min(mmax, high[i]); } else { low[i] = 10 * a[i]; high[i] = 10 * (a[i] + 1); mmin = low[i]; mmax = high[i]; } } mmin = (n + 1) * mmin / 10; mmax = (n + 1) * mmax / 10; int res = (int)floor(mmin + EPS); if (res - EPS < mmin && mmax < res + 1 + EPS) { puts( unique ); printf( %d n , res); } else { puts( not unique ); } return 0; }
|
/*
Copyright (C) 2016
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//-------------------------------------------------------------------------
// https://github.com/balanx/laotzu
//
// Description : submodule of stream_asyn_fifo_controller
// read function
//
//-------------------------------------------------------------------------
// History :
// 10/15/2016
// initial draft
//
//-------------------------------------------------------------------------
module stream_asyn_fifo_read #(
parameter FWFTEN = 1, // 0 : disable
parameter ADDRWIDTH = 6,
parameter [ADDRWIDTH:0] FIFODEPTH = 44,
parameter [ADDRWIDTH:0] MINBIN2 = 0,
parameter [ADDRWIDTH:0] MAXBIN2 = 7
) (
input wire r_clk ,
input wire r_rst_n ,
input wire r_en ,
input wire [ADDRWIDTH:0] w2r_ptr ,
output reg [ADDRWIDTH-1:0] rbin ,
output reg [ADDRWIDTH:0] rptr ,
output inc ,
output reg r_valid ,
output reg [ADDRWIDTH:0] r_counter,
output reg r_error
);
//
wire zero = (r_counter == {(ADDRWIDTH+1){1'b0}} );
// FWFT (First Word Fall Through)
wire fwft = FWFTEN ? (!r_valid && !zero) : 1'b0;
//
assign inc = (r_en && !zero) || fwft;
//---------------------------------------------------------------
// "rbin2" is double the amount of "rbin"
//---------------------------------------------------------------
reg [ADDRWIDTH:0] rbin2;
wire [ADDRWIDTH:0] rbnext = (rbin2>=MINBIN2 && rbin2<MAXBIN2) ?
(rbin2 + 1'b1) : MINBIN2;
//
always @(posedge r_clk or negedge r_rst_n)
if (!r_rst_n)
rbin2 <= MINBIN2;
else if (inc)
rbin2 <= rbnext;
//---------------------------------------------------------------
// memory address
//---------------------------------------------------------------
always @(posedge r_clk or negedge r_rst_n)
if (!r_rst_n)
rbin <= {ADDRWIDTH{1'b0}};
else if (inc)
rbin <= rbnext[ADDRWIDTH] ? rbnext[ADDRWIDTH-1:0] :
(rbnext[ADDRWIDTH-1:0] - MINBIN2[ADDRWIDTH-1:0]);
//---------------------------------------------------------------
// GRAY pointer
//---------------------------------------------------------------
// binary-to-gray conversion
wire [ADDRWIDTH:0] rptr_gray = {1'b0,rbnext[ADDRWIDTH:1]} ^ rbnext;
always @(posedge r_clk or negedge r_rst_n)
if (!r_rst_n)
rptr <= (MINBIN2>>1) ^ MINBIN2;
else if (inc)
rptr <= rptr_gray;
//---------------------------------------------------------------
// from other-side
//---------------------------------------------------------------
wire [ADDRWIDTH:0] w2r_bin = w2r_ptr;
//---------------------------------------------------------------
// output signals
//---------------------------------------------------------------
wire [ADDRWIDTH:0] distance = ( (w2r_bin >= rbin2) ?
(w2r_bin - rbin2) :
(w2r_bin - rbin2 - (MINBIN2<<1) )
) - inc;
// "r_counter" is precise.
always @(posedge r_clk or negedge r_rst_n)
if (!r_rst_n)
r_counter <= {(ADDRWIDTH+1){1'b0}};
else
r_counter <= distance;
// "r_valid" is alignment with "dout" because of FWFT
always @(posedge r_clk or negedge r_rst_n)
if (!r_rst_n)
r_valid <= 1'b0;
else if (r_en || fwft)
r_valid <= !zero;
//
always @(posedge r_clk or negedge r_rst_n)
if (!r_rst_n)
r_error <= 1'b0;
else
r_error <= (r_counter > FIFODEPTH);
//
endmodule
|
#include <bits/stdc++.h> using namespace std; int arr[1001][1001]; int main() { int n, m, f1 = 0; cin >> n >> m; int cnt = m; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (i != j && arr[i][j] == 0) { arr[i][j] = 1; arr[j][i] = -1; cnt--; } if (cnt == 0) break; } if (cnt > 0) { f1 = 1; break; } cnt = m; } if (f1 == 1) cout << -1 << endl; else { cout << n * m << endl; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) if (arr[i][j] == 1) cout << i + 1 << << j + 1 << endl; } } return 0; }
|
/*
* I2S shift in function. Data interface is a FIFO. FIFO is assumed to be dual-clock.
* There will be no writes if not enabled.
* New values will be written to FIFO only when fifo_ready. If enabled, but not ready,
* the last data sample will be dropped.
*/
module i2s_shift_in (
input clk, // Master clock, should be synchronous with bclk/lrclk
input reset_n, // Asynchronous reset
output reg [31:0] fifo_right_data, // Fifo interface, right channel
output reg [31:0] fifo_left_data, // Fifo interface, left channel
input fifo_ready, // Fifo ready (not full)
output reg fifo_write, // Fifo write strobe, write only when l+r received
input enable, // Software enable
input bclk, // I2S bclk
input lrclk, // I2S lrclk (word clock)
input data_in // Data in from ADC
);
// bclk edge
reg bclk_delayed;
always @(posedge clk or negedge reset_n)
begin
if (~reset_n)
begin
bclk_delayed <= 0;
end
else
begin
bclk_delayed <= bclk;
end
end
wire bclk_rising_edge = bclk & ~bclk_delayed;
wire bclk_falling_edge = ~bclk & bclk_delayed;
// lrclk edges
reg lrclk_delayed;
always @(posedge clk or negedge reset_n)
begin
if (~reset_n)
begin
lrclk_delayed <= 0;
end
else
begin
lrclk_delayed <= lrclk;
end
end
wire lrclk_rising_edge = lrclk & ~lrclk_delayed;
wire lrclk_falling_edge = ~lrclk & lrclk_delayed;
// I2S is one bclk delayed, so detect falling egde of first (complete) bclk after each lrclk edge
reg [1:0] first_bclk_falling_after_lrclk_rising_r;
always @(posedge clk or negedge reset_n)
begin
if (~reset_n)
begin
first_bclk_falling_after_lrclk_rising_r <= 0;
end
else
begin
if (lrclk_rising_edge)
first_bclk_falling_after_lrclk_rising_r <= 2'b01;
else if (first_bclk_falling_after_lrclk_rising_r == 2'b01 && bclk_rising_edge)
first_bclk_falling_after_lrclk_rising_r <= 2'b10;
else if (first_bclk_falling_after_lrclk_rising_r == 2'b10 && bclk_falling_edge)
first_bclk_falling_after_lrclk_rising_r <= 2'b11;
else if (first_bclk_falling_after_lrclk_rising_r == 2'b11)
first_bclk_falling_after_lrclk_rising_r <= 2'b00;
end
end
wire first_bclk_falling_after_lrclk_rising = first_bclk_falling_after_lrclk_rising_r == 2'b11;
reg [1:0] first_bclk_falling_after_lrclk_falling_r;
always @(posedge clk or negedge reset_n)
begin
if (~reset_n)
begin
first_bclk_falling_after_lrclk_falling_r <= 0;
end
else
begin
if (lrclk_falling_edge)
first_bclk_falling_after_lrclk_falling_r <= 2'b01;
else if (first_bclk_falling_after_lrclk_falling_r == 2'b01 && bclk_rising_edge)
first_bclk_falling_after_lrclk_falling_r <= 2'b10;
else if (first_bclk_falling_after_lrclk_falling_r == 2'b10 && bclk_falling_edge)
first_bclk_falling_after_lrclk_falling_r <= 2'b11;
else if (first_bclk_falling_after_lrclk_falling_r == 2'b11)
first_bclk_falling_after_lrclk_falling_r <= 2'b00;
end
end
wire first_bclk_falling_after_lrclk_falling = first_bclk_falling_after_lrclk_falling_r == 2'b11;
// shift-register
reg [31:0] shift_register;
always @(posedge clk or negedge reset_n)
begin
if (~reset_n)
begin
shift_register <= 0;
end
else
begin
if (~enable)
shift_register <= 0;
else if (bclk_rising_edge)
shift_register <= {shift_register[30:0], data_in};
end
end
// Load output register
always @(posedge clk or negedge reset_n)
begin
if (~reset_n)
begin
fifo_right_data <= 0;
fifo_left_data <= 0;
end
else
begin
if (~enable)
begin
fifo_right_data <= 0;
fifo_left_data <= 0;
end
else if (first_bclk_falling_after_lrclk_rising)
fifo_left_data <= shift_register;
else if (first_bclk_falling_after_lrclk_falling)
fifo_right_data <= shift_register;
end
end
// fifo write strobe, one clock after right channel has been loaded to output register
always @(posedge clk or negedge reset_n)
begin
if (~reset_n)
begin
fifo_write <= 0;
end
else
begin
if (~enable | ~fifo_ready)
fifo_write <= 0;
else
fifo_write <= first_bclk_falling_after_lrclk_falling;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); long double P = 3.1415926536, a[110], n; cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; a[i] *= a[i]; a[i] *= P; } for (int i = 0; i < n; i++) for (int j = 0; j < n - 1; j++) if (a[j] > a[j + 1]) swap(a[j], a[j + 1]); long double ans = 0; for (int i = n - 1; i >= 0; i -= 2) if (i == 0) ans += a[i]; else ans += a[i] - a[i - 1]; cout << setprecision(12) << ans; return 0; }
|
/*
* Copyright 2017 Google Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`include "alu.v"
`include "pcounter.v"
`include "ram.v"
`include "uart-tx.v"
module cpu(
input clk,
output uart_tx_wire);
localparam INSTR_SIZE = 4;
localparam WIDTH = 8;
localparam ADDRESS_WIDTH = WIDTH - INSTR_SIZE;
localparam NOP = 4'b0000; //No operation.
localparam LDA = 4'b0001; //Load register A from memory.
localparam ADD = 4'b0010; //Add specified memory pointer to register A.
//Store the result in register A.
localparam SUB = 4'b0011; //Subtract specified memory from register A.
//Store the result in register A.
localparam STA = 4'b0100; //Store register A to memory.
localparam OUT = 4'b0101; //Send register A to UART port. The instruction
//will block until the transfer completes.
localparam JMP = 4'b0110; //Jump at some code location
localparam LDI = 4'b0111; //Load 4'bit immediate value in register A.
localparam JC = 4'b1000; //Jump if carry flag is set.
localparam SHLA= 4'b1001; //Logical shift left of register A.
localparam MULA= 4'b1010; //Unsigned multiplcation between two nibbles in register A.
//Result is stored again in register A.
localparam HLT = 4'b1111; //Halt CPU control clock;
//Control signals
localparam j = 0; //Program counter jump
localparam co = 1; //Program counter output enable
localparam ce = 2; //Program counter enable
localparam oi = 3; //Display/UART tx
localparam su = 4; //Subtract enable
localparam ao = 5; //Register A read enable
localparam io = 6; //Instruction register read enable
localparam ro = 7; //RAM out
localparam ri = 8; //RAM in
localparam mi = 9; //Address in
localparam she = 10; //Shift enable
localparam mul = 11; //Multiply enable
localparam SIG_COUNT = mul + 1;
localparam STAGE_T0 = 0;
localparam STAGE_T1 = 1;
localparam STAGE_T2 = 2;
localparam STAGE_T3 = 3;
localparam STAGE_T4 = 4;
localparam STAGE_COUNT = STAGE_T4 + 1;
localparam STAGE_WIDTH = $clog2(STAGE_COUNT);
localparam rst_size = 5;
localparam rst_max = (1 << 5) - 1;
reg [rst_size : 0] rst_cnt = 0;
reg rstn = 0;
reg [WIDTH-1 : 0] ir; //Instruction register.
reg [SIG_COUNT-1 : 0] ctrl_reg; //Holds control signal status.
reg [STAGE_WIDTH-1 : 0] stage_reg; //Keeps track of the current execution stage.
reg [WIDTH-1 : 0] reg_a; //A CPU register
reg [WIDTH-1 : 0] reg_b; //B CPU register
reg carry_status;
wire [WIDTH-1 : 0] alu_out; //ALU I/O
wire alu_carry; //
wire [ADDRESS_WIDTH-1 : 0] pc_in; //Program counter I/O
wire [ADDRESS_WIDTH-1 : 0] pc_out; //
wire [WIDTH-1 : 0] mem_in; //RAM I/O
wire [WIDTH-1 : 0] mem_out; //
wire [WIDTH-1 : 0] mem_addr; //
wire tx_idle; //UART TX idle signal
//CPU modules
pcounter #(.ADDRESS_WIDTH(ADDRESS_WIDTH)) pc(
.rst(!rstn),
.clk(clk),
.enable(ctrl_reg[ce]),
.jump(ctrl_reg[j]),
.out_enable(ctrl_reg[co]),
.bus_in(pc_in),
.bus_out(pc_out));
alu #(.WIDTH(WIDTH)) alu(
.a(reg_a),
.b(reg_b),
.mul_enable(ctrl_reg[mul]),
.sub_enable(ctrl_reg[su]),
.shift_enable(ctrl_reg[she]),
.shift_pos(ir[2 : 0]),
.result(alu_out),
.carry_out(alu_carry));
ram #(.WIDTH(WIDTH),.ADDRESS_WIDTH(ADDRESS_WIDTH)) memory(
.clk(clk),
.enable(ctrl_reg[ro]),
.write_enable(ctrl_reg[ri]),
.addr(mem_addr),
.data_in(mem_in),
.data_out(mem_out));
uarttx uart(
.rst(!rstn),
.clk(clk),
.tx_start(ctrl_reg[oi]),
.tx_byte(reg_a),
.tx(uart_tx_wire),
.tx_ready(tx_idle));
//Data transfer paths
assign pc_in = (ctrl_reg[j] && ctrl_reg[io]) ? ir[ADDRESS_WIDTH-1 : 0] : 0;
assign mem_addr = (ctrl_reg[mi] && ctrl_reg[io]) ? ir[ADDRESS_WIDTH-1 : 0] :
(ctrl_reg[mi] && ctrl_reg[co]) ? pc_out : 0;
assign mem_in = (ctrl_reg[ri] && ctrl_reg[ao]) ? reg_a : 0;
always @(posedge clk) begin
if (rst_cnt != rst_max) begin
rst_cnt <= rst_cnt + 1;
end else begin
rstn <= 1;
end
end
always @(posedge clk) begin
if (rstn) begin
case (stage_reg)
STAGE_T0: begin
ctrl_reg <= (1 << ro) | (1 << mi) | (1 << co);
stage_reg <= STAGE_T1;
end
STAGE_T1: begin
ctrl_reg <= 1 << ce;
ir <= mem_out;
stage_reg <= STAGE_T2;
end
STAGE_T2: begin
case (ir[WIDTH-1 : ADDRESS_WIDTH])
MULA: begin
ctrl_reg <= (1 << mul);
stage_reg <= STAGE_T3;
end
SHLA: begin
ctrl_reg <= (1 << she);
stage_reg <= STAGE_T3;
end
LDA: begin
ctrl_reg <= (1 << ro) | (1 << mi) | (1 << io);
stage_reg <= STAGE_T3;
end
STA: begin
ctrl_reg <= (1 << ri) | (1 << ao) | (1 << mi) | (1 << io);
stage_reg <= STAGE_T0;
end
ADD: begin
ctrl_reg <= (1 << ro) | (1 << mi) | (1 << io);
stage_reg <= STAGE_T3;
end
SUB: begin
ctrl_reg <= (1 << ro) | (1 << mi) | (1 << io);
stage_reg <= STAGE_T3;
end
OUT: begin
ctrl_reg <= 1 << oi;
stage_reg <= STAGE_T3;
end
JMP: begin
ctrl_reg <= (1 << j) | (1 << io);
stage_reg <= STAGE_T0;
end
JC: begin
if (carry_status) begin
ctrl_reg <= (1 << j) | (1 << io);
end else begin
ctrl_reg <= 0;
end
stage_reg <= STAGE_T0;
end
LDI: begin
ctrl_reg <= 0;
reg_a <= {4'b0, ir[3 : 0]};
stage_reg <= STAGE_T0;
end
NOP: begin
ctrl_reg <= 0;
stage_reg <= STAGE_T0;
end
HLT: begin
ctrl_reg <= 0;
stage_reg <= STAGE_COUNT;
end
default: begin
stage_reg <= STAGE_COUNT;
end
endcase
end
STAGE_T3: begin
case (ir[WIDTH-1 : ADDRESS_WIDTH])
MULA: begin
reg_a <= alu_out;
carry_status <= alu_carry;
stage_reg <= STAGE_T0;
end
SHLA: begin
reg_a <= alu_out;
carry_status <= alu_carry;
stage_reg <= STAGE_T0;
end
LDA: begin
reg_a <= mem_out;
stage_reg <= STAGE_T0;
end
ADD: begin
ctrl_reg <= 0;
reg_b <= mem_out;
stage_reg <= STAGE_T4;
end
SUB: begin
ctrl_reg <= 1 << su;
reg_b <= mem_out;
stage_reg <= STAGE_T4;
end
OUT: begin
ctrl_reg <= 0;
if (tx_idle) begin
stage_reg <= STAGE_T0;
end else begin
stage_reg <= STAGE_T3;
end
end
default: begin
stage_reg <= STAGE_COUNT;
end
endcase
end
STAGE_T4: begin
case (ir[WIDTH-1 : ADDRESS_WIDTH])
ADD: begin
reg_a <= alu_out;
carry_status <= alu_carry;
stage_reg <= STAGE_T0;
end
SUB: begin
reg_a <= alu_out;
stage_reg <= STAGE_T0;
end
default: begin
stage_reg <= STAGE_COUNT;
end
endcase
end
default: begin
stage_reg <= STAGE_COUNT;
end
endcase
end else begin
ir <= 0;
carry_status <= 0;
ctrl_reg <= 0;
reg_a <= 0;
reg_b <= 0;
stage_reg <= STAGE_T0;
end
end
endmodule
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#include <bits/stdc++.h> typedef long long int ll; typedef unsigned long long int ull; #define N 1010100 #define inf 1e9 #define loop(x, n, r) for(int i = x; i < n; i += r) #define pb push_back #define pp pair<int, int> using namespace std; int main(){ ios::sync_with_stdio(0); cin.tie(0); int T = 1; cin >> T; while(T--){ int n; cin >> n; string b; cin >> b; cout << 1 ; char prev = b[0] == 0 ? 1 : 2 ; loop(1, n, 1){ if(prev == 2 ){ if(b[i] == 1 ) cout << 0 ; else cout << 1 ; prev = 1 ; } else if(prev == 1 ){ if(b[i] == 1 ){ cout << 1 ; prev = 2 ; } else{ cout << 0 ; prev = 0 ; } } else{ if(b[i] == 1 ){ cout << 1 ; prev = 2 ; } else{ cout << 1 ; prev = 1 ; } } } cout << n ; } return 0; }
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