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// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\Select_AB.v
// Created: 2014-09-08 14:12:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: Select_AB
// Source Path: controllerPeripheralHdlAdi/Encoder_Peripheral_Hardware_Specification/Select AB
// Hierarchy Level: 2
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module Select_AB
(
in_select,
in1,
in2,
A,
B
);
input in_select;
input in1;
input in2;
output A;
output B;
wire Switch_out1;
wire Switch1_out1;
// <S8>/Switch
assign Switch_out1 = (in_select == 1'b0 ? in2 :
in1);
assign A = Switch_out1;
// <S8>/Switch1
assign Switch1_out1 = (in_select == 1'b0 ? in1 :
in2);
assign B = Switch1_out1;
endmodule // Select_AB
|
#include <bits/stdc++.h> const int maxn = 400010, maxq = 400010; int n, cnt[maxn], tmp[maxn], lg[maxn]; int min(int a, int b) { return a < b ? a : b; } int max(int a, int b) { return a > b ? a : b; } struct SA { char S[maxn]; int nxt[maxn], mn[maxn], sa[maxn], r[2][maxn], *rk, ht[20][maxn]; void make() { for (int i = 0; i < 128; i++) cnt[i] = 0, tmp[i] = 1 << 30; mn[n] = 1 << 30; for (int i = n; i--;) nxt[i] = tmp[S[i]], tmp[S[i]] = i, mn[i] = min(nxt[i], mn[i + 1]); for (int i = 0; i < n; i++) cnt[S[i]]++; for (int i = 1; i < 128; i++) cnt[i] += cnt[i - 1]; for (int i = n; i--;) sa[--cnt[S[i]]] = i; int tot = 0; rk = *r; for (int i = 0; i < n; i++) rk[sa[i]] = i && S[sa[i - 1]] == S[sa[i]] ? tot - 1 : tot++; for (int k = 1, *t = r[1]; tot < n; k *= 2) { for (int i = 0; i < k; i++) tmp[i] = i + n - k; for (int i = 0, j = k; i < n; i++) if (sa[i] >= k) tmp[j++] = sa[i] - k; for (int i = 0; i < tot; i++) cnt[i] = 0; for (int i = 0; i < n; i++) cnt[rk[i]]++; for (int i = 1; i < tot; i++) cnt[i] += cnt[i - 1]; for (int i = n; i--;) sa[--cnt[rk[tmp[i]]]] = tmp[i]; rk[n] = -1; for (int i = tot = 0; i < n; i++) t[sa[i]] = i && rk[sa[i - 1]] == rk[sa[i]] && rk[sa[i - 1] + k] == rk[sa[i] + k] ? tot - 1 : tot++; std::swap(rk, t); } for (int i = 0, h = 0; i < n; ht[0][rk[i++]] = h) for (h ? --h : 0; rk[i] + 1 < n && S[i + h] == S[sa[rk[i] + 1] + h]; h++) ; for (int k = 1; k <= lg[n]; k++) for (int i = 0; i + (1 << k) <= n; i++) ht[k][i] = min(ht[k - 1][i], ht[k - 1][i + (1 << k - 1)]); } int lcp(int i, int j) { if (i == n || j == n) return 0; int k; if ((i = rk[i]) > (j = rk[j])) return k = lg[i - j], min(ht[k][j], ht[k][i - (1 << k)]); return k = lg[j - i], min(ht[k][i], ht[k][j - (1 << k)]); } } S0, S1; int R[maxq], ans[maxq]; std::vector<int> pf[maxn], qs[maxn]; int ul[maxn], ur[maxn], dl[maxn], dr[maxn], ml[maxn], pl[maxn], pr[maxn], list[maxn]; int find(int* u, int i) { return u[i] == i ? i : u[i] = find(u, u[i]); } void upd(int* u, int* d, int l, int r, int x) { while ((l = find(u, l)) < r) d ? d[l] = x : 0, u[l] = find(u, l + 1); } int calc(int l, int r, int br) { int len = r - l; for (int i = pf[len].size(); i--;) { int p = len / pf[len][i]; if (S0.lcp(l, l + p) >= len - p) return 1; } if (dl[l] && l + dl[l] * 2 <= r) return 2; if (dr[r] && r - dr[r] * 2 >= l) return 2; if (r > br && ul[r] > r) return 2; for (int i = 1; l + i < r && l + i <= br; i++) if (S0.lcp(l, r - i) >= i) return 2; if (S0.nxt[l] < r || S1.nxt[n - r] < n - l || ml[l] <= r) return 3; if (S0.mn[l] < r) return 4; return -1; } int main() { scanf( %d%s , &n, S0.S); for (int i = n, j = 0; i--; j++) S1.S[j] = S0.S[i]; for (int i = 2; i <= n; i++) { lg[i] = lg[i / 2] + 1; if (!pf[i].size()) for (int j = i; j <= n; j += i) pf[j].push_back(i); } S0.make(); S1.make(); for (int i = 0; i <= n + 1; i++) ul[i] = ur[i] = i; for (int l = 1; l <= n / 2; l++) { int la = -1; for (int i = 0; i + l <= n; i += l) if (i > la) { int pl = i - S1.lcp(n - i - l, n - i), pr = i + S0.lcp(i, i + l); if (pr - pl >= l) { upd(ul, dl, pl, pr - l + 1, l); upd(ur, dr, pl + l * 2, pr + l + 1, l); } la = pr; } } ml[n] = 1 << 30; for (int i = n; i--;) { ml[i] = ml[i + 1]; if (dl[i]) ml[i] = min(ml[i], i + dl[i] * 2); } int q; scanf( %d , &q); for (int i = 0, l; i < q; i++) { scanf( %d%d , &l, R + i); qs[l - 1].push_back(i); } int b = 0; while (b * b < n * 4) b++; for (int bl = 0, br = b; bl < n; bl = br, br += b) { if (br > n) br = n; for (int i = 0; i <= br; i++) cnt[i] = 0; for (int i = br + 1; i <= n; i++) { ul[i] = i; pl[i] = br - S1.lcp(n - i, n - br); cnt[pl[i]]++; } for (int i = 0; i < br; i++) cnt[i + 1] += cnt[i]; int tot = cnt[br]; for (int i = n; i > br; i--) tmp[--cnt[pl[i]]] = i; for (int l = bl, i = 0; l < n && l < br; l++) { for (; i < tot && pl[tmp[i]] <= l; i++) upd(ul, 0, tmp[i], tmp[i] + S0.lcp(br, tmp[i]) + 1, 0); for (int id = qs[l].size(); id--;) { int x = qs[l][id]; ans[x] = calc(l, R[x], br); } } } for (int i = 0; i < q; i++) printf( %d n , ans[i]); } |
#include <bits/stdc++.h> using namespace std; long long i, j, n, c[223456], d[223456], a[456789], l, r, s, t, tt, k, x, y, z, m, b[1111111]; string p, q, du, qq; vector<long long> u[345678], uu, ui; multiset<long long> mm; int main() { cin >> n >> t; for (i = 0; i < n; i++) { cin >> a[i]; } m = t; cin >> k; for (i = 0; i < n; i++) { cin >> b[i]; mm.insert(b[i]); while (t < a[i]) { if (mm.empty()) { cout << -1; return 0; } s += *mm.begin(); mm.erase(mm.begin()); t += k; } } cout << s; return 0; } |
#include <bits/stdc++.h> const long long MX = 2 * 100 * 1000 + 1000, inf = 3e18, mod = 1000 * 1000 * 1000 + 7; using namespace std; vector<long long> ans[MX]; int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); string s; cin >> s; long long n = s.size(); long long one = 0, num = 0; for (long long i = 0; i < n; i++) { if (s[i] == 1 ) { if (one < num) { ans[one].push_back(i); one++; } else { return cout << -1 << endl, 0; } } else { if (one > 0) { one--; ans[one].push_back(i); } else { ans[num].push_back(i); num++; } } } if (one) { return cout << -1 << endl, 0; } cout << num << endl; for (long long i = 0; i < num; i++) { cout << ans[i].size() << ; for (long long j = 0; j < ans[i].size(); j++) { cout << ans[i][j] + 1 << ; } cout << endl; } } |
#include <bits/stdc++.h> using namespace std; int main() { int a[1001], i, n, sum = 0, max = 0; int b[1001] = {0}; cin >> n; for (i = 0; i < n; i++) cin >> a[i]; for (i = 0; i < n; i++) { b[a[i]]++; } for (i = 0; i < 1001; i++) { if (b[i] > max) max = b[i]; if (b[i]) sum++; } cout << max << ; cout << sum; return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:40:46 12/20/2010
// Design Name:
// Module Name: clk_test
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module clk_test(
input clk,
input sysclk,
input read,
input write,
input pawr,
input pard,
input refresh,
input cpuclk,
input romsel,
input cicclk,
output reg [31:0] snes_sysclk_freq,
output reg [31:0] snes_read_freq,
output reg [31:0] snes_write_freq,
output reg [31:0] snes_pawr_freq,
output reg [31:0] snes_pard_freq,
output reg [31:0] snes_refresh_freq,
output reg [31:0] snes_cpuclk_freq,
output reg [31:0] snes_romsel_freq,
output reg [31:0] snes_cicclk_freq
);
reg [31:0] sysclk_counter;
reg [31:0] sysclk_value;
reg [31:0] read_value;
reg [31:0] write_value;
reg [31:0] pard_value;
reg [31:0] pawr_value;
reg [31:0] refresh_value;
reg [31:0] cpuclk_value;
reg [31:0] romsel_value;
reg [31:0] cicclk_value;
initial snes_sysclk_freq = 32'hFFFFFFFF;
initial sysclk_counter = 0;
initial sysclk_value = 0;
initial read_value = 0;
initial write_value = 0;
initial pard_value = 0;
initial pawr_value = 0;
initial refresh_value = 0;
initial cpuclk_value = 0;
initial romsel_value = 0;
initial cicclk_value = 0;
reg [1:0] sysclk_sreg;
reg [1:0] read_sreg;
reg [1:0] write_sreg;
reg [1:0] pard_sreg;
reg [1:0] pawr_sreg;
reg [1:0] refresh_sreg;
reg [1:0] cpuclk_sreg;
reg [1:0] romsel_sreg;
reg [1:0] cicclk_sreg;
always @(posedge clk) romsel_sreg <= {romsel_sreg[0], romsel};
wire romsel_rising = (romsel_sreg == 2'b01);
always @(posedge clk) cpuclk_sreg <= {cpuclk_sreg[0], cpuclk};
wire cpuclk_rising = (cpuclk_sreg == 2'b01);
always @(posedge clk) sysclk_sreg <= {sysclk_sreg[0], sysclk};
wire sysclk_rising = (sysclk_sreg == 2'b01);
always @(posedge clk) read_sreg <= {read_sreg[0], read};
wire read_rising = (read_sreg == 2'b01);
always @(posedge clk) write_sreg <= {write_sreg[0], write};
wire write_rising = (write_sreg == 2'b01);
always @(posedge clk) pard_sreg <= {pard_sreg[0], pard};
wire pard_rising = (pard_sreg == 2'b01);
always @(posedge clk) pawr_sreg <= {pawr_sreg[0], pawr};
wire pawr_rising = (pawr_sreg == 2'b01);
always @(posedge clk) refresh_sreg <= {refresh_sreg[0], refresh};
wire refresh_rising = (refresh_sreg == 2'b01);
always @(posedge clk) cicclk_sreg <= {cicclk_sreg[0], cicclk};
wire cicclk_rising = (cicclk_sreg == 2'b01);
always @(posedge clk) begin
if(sysclk_counter < 96000000) begin
sysclk_counter <= sysclk_counter + 1;
if(sysclk_rising) sysclk_value <= sysclk_value + 1;
if(read_rising) read_value <= read_value + 1;
if(write_rising) write_value <= write_value + 1;
if(pard_rising) pard_value <= pard_value + 1;
if(pawr_rising) pawr_value <= pawr_value + 1;
if(refresh_rising) refresh_value <= refresh_value + 1;
if(cpuclk_rising) cpuclk_value <= cpuclk_value + 1;
if(romsel_rising) romsel_value <= romsel_value + 1;
if(cicclk_rising) cicclk_value <= cicclk_value + 1;
end else begin
snes_sysclk_freq <= sysclk_value;
snes_read_freq <= read_value;
snes_write_freq <= write_value;
snes_pard_freq <= pard_value;
snes_pawr_freq <= pawr_value;
snes_refresh_freq <= refresh_value;
snes_cpuclk_freq <= cpuclk_value;
snes_romsel_freq <= romsel_value;
snes_cicclk_freq <= cicclk_value;
sysclk_counter <= 0;
sysclk_value <= 0;
read_value <= 0;
write_value <= 0;
pard_value <= 0;
pawr_value <= 0;
refresh_value <= 0;
cpuclk_value <= 0;
romsel_value <= 0;
cicclk_value <= 0;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV3SD1_FUNCTIONAL_V
`define SKY130_FD_SC_MS__CLKDLYINV3SD1_FUNCTIONAL_V
/**
* clkdlyinv3sd1: Clock Delay Inverter 3-stage 0.15um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__clkdlyinv3sd1 (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV3SD1_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; long long bigmod(long long b, long long p, long long n) { if (p == 0) return 1; else if (p % 2 == 0) { long long half1 = bigmod(b, p / 2, n); return ((half1 * half1) % n); } else if (p % 2 == 1) { long long p1 = b % n; long long p2 = bigmod(b, p - 1, n); return ((p1 * p2) % n); } } long long pre11[1000010], pre21[1000010]; string s, s1; const int p = 31; const int m1 = 1e9 + 7; long long MMI[1000010]; void com() { MMI[0] = 1; MMI[1] = bigmod(31, m1 - 2, m1); for (long long i = 2; i <= s.size() + 3; i++) MMI[i] = (MMI[i - 1] * MMI[1]) % m1; } void compute_hash() { long long hash_value1 = 0, hash_value2 = 0; long long p_pow1 = 1, p_pow2 = 1; for (int i = 0; i < s.size(); i++) { hash_value1 = (hash_value1 + (s[i] - a + 1) * p_pow1) % m1; if (i < s1.size()) hash_value2 = (hash_value2 + (s1[i] - a + 1) * p_pow1) % m1; p_pow1 = (p_pow1 * p) % m1; pre11[i] = hash_value1; if (i < s1.size()) pre21[i] = hash_value2; } } void compute_hash2() { long long hash_value1 = 0, hash_value2 = 0; long long p_pow1 = 1, p_pow2 = 1; for (int i = 0; i < s1.size(); i++) { hash_value1 = (hash_value1 + (s1[i] - a + 1) * p_pow1) % m1; p_pow1 = (p_pow1 * p) % m1; pre21[i] = hash_value1; } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; cin >> s >> s1; com(); compute_hash(); vector<int> V; for (int i = 0; i < s.size(); i++) { long long p1, p2; long long t1, t2; if (i == 0) { p2 = pre11[s.size() - 1] - pre11[0]; if (p2 < 0) p2 += m1; p2 = ((p2 % m1) * MMI[i + 1]) % m1; if (p2 == pre21[s1.size() - 1]) V.push_back(i + 1); } else if (i == s.size() - 1) { if (pre21[i - 1] == pre11[i - 1]) V.push_back(i + 1); } else { p2 = pre11[s.size() - 1] - pre11[i]; if (p2 < 0) p2 += m1; p2 = ((p2 % m1) * MMI[i + 1]) % m1; t2 = pre21[s1.size() - 1] - pre21[i - 1]; if (t2 < 0) t2 += m1; t2 = ((t2 % m1) * MMI[i]) % m1; if (p2 == t2 && pre21[i - 1] == pre11[i - 1]) V.push_back(i + 1); } } cout << V.size() << endl; for (int i = 0; i < V.size(); i++) cout << V[i] << ; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR2B_TB_V
`define SKY130_FD_SC_MS__NOR2B_TB_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__nor2b.v"
module top();
// Inputs are registered
reg A;
reg B_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B_N = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B_N = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B_N = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B_N = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B_N = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_ms__nor2b dut (.A(A), .B_N(B_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR2B_TB_V
|
// This file has been automatically generated by goFB and should not be edited by hand
// Compiler written by Hammond Pearce and available at github.com/kiwih/goFB
// Verilog support is EXPERIMENTAL ONLY
// This file represents the Top of the IEC61499 network
module top
(
input wire clk,
//input events
input wire InjectorArmFinishMovement_eI,
input wire EmergencyStopChanged_eI,
input wire CanisterPressureChanged_eI,
input wire FillContentsAvailableChanged_eI,
input wire LasersChanged_eI,
input wire DoorOverride_eI,
input wire VacuumTimerElapsed_eI,
//output events
output wire DoorReleaseCanister_eO,
output wire ConveyorChanged_eO,
output wire InjectorPositionChanged_eO,
output wire InjectorControlsChanged_eO,
output wire FillContentsChanged_eO,
output wire StartVacuumTimer_eO,
output wire GoRejectArm_eO,
output wire CanisterCountChanged_eO,
output wire InjectDone_eO,
//input variables
input wire EmergencyStop_I,
input wire [7:0] CanisterPressure_I,
input wire [7:0] FillContentsAvailable_I,
input wire DoorSiteLaser_I,
input wire InjectSiteLaser_I,
input wire RejectSiteLaser_I,
input wire RejectBinLaser_I,
input wire AcceptBinLaser_I,
//output variables
output wire [7:0] ConveyorSpeed_O ,
output wire [7:0] InjectorPosition_O ,
output wire InjectorContentsValveOpen_O ,
output wire InjectorVacuumRun_O ,
output wire InjectorPressurePumpRun_O ,
output wire FillContents_O ,
output wire [7:0] CanisterCount_O ,
input reset
);
// I/O
FB_FlexPRET iec61499_network_top (
.clk(clk),
//input events
.InjectorArmFinishMovement_eI(InjectorArmFinishMovement_eI),
.EmergencyStopChanged_eI(EmergencyStopChanged_eI),
.CanisterPressureChanged_eI(CanisterPressureChanged_eI),
.FillContentsAvailableChanged_eI(FillContentsAvailableChanged_eI),
.LasersChanged_eI(LasersChanged_eI),
.DoorOverride_eI(DoorOverride_eI),
.VacuumTimerElapsed_eI(VacuumTimerElapsed_eI),
//output events
.DoorReleaseCanister_eO(DoorReleaseCanister_eO),
.ConveyorChanged_eO(ConveyorChanged_eO),
.InjectorPositionChanged_eO(InjectorPositionChanged_eO),
.InjectorControlsChanged_eO(InjectorControlsChanged_eO),
.FillContentsChanged_eO(FillContentsChanged_eO),
.StartVacuumTimer_eO(StartVacuumTimer_eO),
.GoRejectArm_eO(GoRejectArm_eO),
.CanisterCountChanged_eO(CanisterCountChanged_eO),
.InjectDone_eO(InjectDone_eO),
//input variables
.EmergencyStop_I(EmergencyStop_I),
.CanisterPressure_I(CanisterPressure_I),
.FillContentsAvailable_I(FillContentsAvailable_I),
.DoorSiteLaser_I(DoorSiteLaser_I),
.InjectSiteLaser_I(InjectSiteLaser_I),
.RejectSiteLaser_I(RejectSiteLaser_I),
.RejectBinLaser_I(RejectBinLaser_I),
.AcceptBinLaser_I(AcceptBinLaser_I),
//output variables
.ConveyorSpeed_O(ConveyorSpeed_O),
.InjectorPosition_O(InjectorPosition_O),
.InjectorContentsValveOpen_O(InjectorContentsValveOpen_O),
.InjectorVacuumRun_O(InjectorVacuumRun_O),
.InjectorPressurePumpRun_O(InjectorPressurePumpRun_O),
.FillContents_O(FillContents_O),
.CanisterCount_O(CanisterCount_O),
.reset(reset)
);
endmodule |
#include <bits/stdc++.h> using namespace std; int main() { int n, x; vector<pair<int, int>> v; cin >> n; for (int i = 1; i <= n && cin >> x; i++) v.push_back({x, i}); sort(v.begin(), v.end()); cout << v[n - 1].second << << v[n - 2].first; } |
/* This file is part of JT51.
JT51 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT51 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT51. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: March, 9th 2017
*/
`timescale 1ns / 1ps
/*
input sampling rate must be the same as clk frequency
interpolate input signal accordingly to get the
right sampling rate.
Refer to sigmadelta.ods to see how the internal width (int_w)
was determined.
*/
module jt51_dac2 #(parameter width=16)
(
input clk,
input rst,
input signed [width-1:0] din,
output reg dout
);
parameter int_w = width+5;
reg [int_w-1:0] y, error, error_1, error_2;
wire [width-1:0] undin = { ~din[width-1], din[width-2:0] };
always @(*) begin
y <= undin + { error_1, 1'b0} - error_2;
dout <= ~y[int_w-1];
error <= y - {dout, {width{1'b0}}};
end
always @(posedge clk)
if( rst ) begin
error_1 <= {int_w{1'b0}};
error_2 <= {int_w{1'b0}};
end else begin
error_1 <= error;
error_2 <= error_1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long int MOD = 1e9 + 7; long long int ne; long long int go(long long int idx, long long int pre) { if (idx == ne) return 0; long long int ans = 1e15; if (idx == 0) ans = min(ans, 1 + go(idx + 1, 0)); else { if (idx == 3) { if (pre != 1) ans = min(ans, go(idx + 1, 1)); if (pre != 2) ans = min(ans, go(idx + 1, 2)); } else if (idx == 1) { if (pre != 1) ans = min(ans, go(idx + 1, 1)); } else { if (pre != 2) ans = min(ans, go(idx + 1, 2)); } ans = min(ans, 1 + go(idx + 1, 0)); } } long double k, d, t; long double kk, dl, dd, tt, tc; long double kectotal, tnow, ans; long double prnow, kebnow; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> k >> d >> t; kk = ceil(k / d); dd = kk * d; dl = dd - k; tt = 1 / (2 * t); tt = dl * tt; tc = k / t; kectotal = tt + tc; tnow = floor(1.0 / kectotal); ans = (tnow * dd); prnow = tnow * kectotal; kebnow = 1.0 - prnow; if (kebnow <= 0.000000000) { } else if (kebnow <= tc) { ans += ((kebnow / tc) * k); kebnow -= kebnow; } else if (kebnow > tc) { ans += k; kebnow -= tc; } if (kebnow <= 0.000000000) { } else if (kebnow <= tt) { ans += ((kebnow / tt) * dl); kebnow -= kebnow; } cout << fixed << setprecision(11) << ans << endl; return 0; } |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_4_e
//
// Generated
// by: wig
// on: Mon Jun 26 08:25:04 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../generic.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_4_e.v,v 1.3 2006/06/26 08:39:43 wig Exp $
// $Date: 2006/06/26 08:39:43 $
// $Log: inst_4_e.v,v $
// Revision 1.3 2006/06/26 08:39:43 wig
// Update more testcases (up to generic)
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_4_e
//
// No `defines in this module
module inst_4_e
//
// Generated Module inst_4
//
(
);
// Module parameters:
parameter FOO = 10;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of inst_4_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module is a rom for auto initializing the TRDB LTM lcd screen. *
* *
******************************************************************************/
module altera_up_av_config_auto_init_ltm (
// Inputs
rom_address,
// Bidirectionals
// Outputs
rom_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input [ 4: 0] rom_address;
// Bidirectionals
// Outputs
output [23: 0] rom_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// States
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
reg [23: 0] data;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign rom_data = {data[13: 8], 2'h0,
data[ 7: 0]};
// Internal Assignments
always @(*)
begin
case (rom_address)
0 : data <= {6'h02, 8'h07};
1 : data <= {6'h03, 8'hDF};
2 : data <= {6'h04, 8'h17};
3 : data <= {6'h11, 8'h00};
4 : data <= {6'h12, 8'h5B};
5 : data <= {6'h13, 8'hFF};
6 : data <= {6'h14, 8'h00};
7 : data <= {6'h15, 8'h20};
8 : data <= {6'h16, 8'h40};
9 : data <= {6'h17, 8'h80};
10 : data <= {6'h18, 8'h00};
11 : data <= {6'h19, 8'h80};
12 : data <= {6'h1A, 8'h00};
13 : data <= {6'h1B, 8'h00};
14 : data <= {6'h1C, 8'h80};
15 : data <= {6'h1D, 8'hC0};
16 : data <= {6'h1E, 8'hE0};
17 : data <= {6'h1F, 8'hFF};
18 : data <= {6'h20, 8'hD2};
19 : data <= {6'h21, 8'hD2};
default : data <= 14'h0000;
endcase
end
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const long long LINF = 0x3f3f3f3f3f3f3f3fLL; const double EPS = 1e-8; const int MOD = 1000000007; const int dy[] = {1, 0, -1, 0}, dx[] = {0, -1, 0, 1}; int main() { cin.tie(0); ios::sync_with_stdio(false); int h, w; cin >> h >> w; vector<int> y{1}, x{1}; int ue = 1, shita = h; while (ue < shita) { for (int ue_x = 1, shita_x = w; ue_x <= w && shita_x >= 0; --shita_x) { y.emplace_back(shita); x.emplace_back(shita_x); ++ue_x; if (ue_x <= w) { y.emplace_back(ue); x.emplace_back(ue_x); } } ++ue; --shita; if (ue <= shita) { y.emplace_back(ue); x.emplace_back(1); } } if (ue == shita) { int hidari = 1, migi = w; while (hidari < migi) { y.emplace_back(ue); x.emplace_back(migi); ++hidari; if (hidari < migi) { y.emplace_back(ue); x.emplace_back(hidari); } --migi; } } set<pair<int, int> > st; for (int i = (1); i < (y.size()); ++i) st.emplace(y[i] - y[i - 1], x[i] - x[i - 1]); if (st.size() < h * w - 1) assert(false); for (int i = (0); i < (y.size()); ++i) cout << y[i] << << x[i] << n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR3B_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__OR3B_PP_BLACKBOX_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__or3b (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR3B_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int n, k; long long sum, s[1000005], ans = -(1LL << 62); struct el { long long val; int poz; bool operator<(const el &A) const { return val < A.val; } }; el a[1000005]; int main() { int i, poz; cin.sync_with_stdio(0); cin >> n; for (i = 1; i <= n; ++i) { cin >> a[i].val; a[i].poz = i; } cin >> k; sort(a + 1, a + n + 1); for (i = 1; i <= n; ++i) s[i] = s[i - 1] + a[i].val; for (i = 1, sum = 0; i <= k; ++i) sum += a[i].val * (2 * i - 1 - k); ans = sum; poz = 1; for (i = k + 1; i <= n; ++i) { sum = sum - a[i - k].val * (1 - k) + a[i].val * (k - 1) - 2 * (s[i - 1] - s[i - k]); if (sum < ans) { ans = sum; poz = i - k + 1; } } for (i = poz; i < poz + k; ++i) cout << a[i].poz << ; return 0; } |
/*
* Copyright (c) 2000 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This example catches the case of a unser defined function that is
* a parameter to a system task.
*/
module main;
function [15:0] sum;
input [15:0] a;
input [15:0] b;
sum = a + b;
endfunction // sum
initial begin
$display("%h = sum(%h, %h)", sum(3,5), 16'd3, 16'd5);
$display("PASSED");
end
endmodule // main
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SEDFXBP_1_V
`define SKY130_FD_SC_HD__SEDFXBP_1_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Verilog wrapper for sedfxbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__sedfxbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__sedfxbp_1 (
Q ,
Q_N ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__sedfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__sedfxbp_1 (
Q ,
Q_N,
CLK,
D ,
DE ,
SCD,
SCE
);
output Q ;
output Q_N;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__sedfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__SEDFXBP_1_V
|
module dis_controller (/*AUTOARG*/
// Outputs
dis_controller_start_alloc, dis_controller_alloc_ack,
dis_controller_wg_alloc_valid, dis_controller_wg_dealloc_valid,
dis_controller_wg_rejected_valid, dis_controller_cu_busy,
// Inputs
clk, rst, inflight_wg_buffer_alloc_valid,
inflight_wg_buffer_alloc_available, allocator_cu_valid,
allocator_cu_rejected, allocator_cu_id_out, grt_wg_alloc_done,
grt_wg_dealloc_done, grt_wg_alloc_wgid, grt_wg_dealloc_wgid,
grt_wg_alloc_cu_id, grt_wg_dealloc_cu_id,
gpu_interface_alloc_available, gpu_interface_dealloc_available,
gpu_interface_cu_id
) ;
parameter NUMBER_CU = 64;
parameter CU_ID_WIDTH = 6;
parameter RES_TABLE_ADDR_WIDTH = 1;
localparam NUMBER_RES_TABLE = 2**RES_TABLE_ADDR_WIDTH;
localparam CU_PER_RES_TABLE = NUMBER_CU/NUMBER_RES_TABLE;
input clk,rst;
input inflight_wg_buffer_alloc_valid, inflight_wg_buffer_alloc_available;
input allocator_cu_valid, allocator_cu_rejected;
input [CU_ID_WIDTH-1 :0] allocator_cu_id_out;
input grt_wg_alloc_done, grt_wg_dealloc_done;
input [CU_ID_WIDTH-1:0] grt_wg_alloc_wgid, grt_wg_dealloc_wgid;
input [CU_ID_WIDTH-1 :0] grt_wg_alloc_cu_id, grt_wg_dealloc_cu_id;
input gpu_interface_alloc_available,
gpu_interface_dealloc_available;
input [CU_ID_WIDTH-1:0] gpu_interface_cu_id;
// Outputs to handle incomming wg
output dis_controller_start_alloc;
// Outputs to handle wg going from allocator to resource table
output dis_controller_alloc_ack;
output dis_controller_wg_alloc_valid;
output dis_controller_wg_dealloc_valid;
output dis_controller_wg_rejected_valid;
// Output to allocator
output [NUMBER_CU-1:0] dis_controller_cu_busy;
reg [NUMBER_CU-1:0] cus_allocating;
reg [NUMBER_RES_TABLE-1:0] cu_groups_allocating;
reg [CU_ID_WIDTH-1 :0] alloc_waiting_cu_id;
reg alloc_waiting;
reg dis_controller_start_alloc_i;
reg dis_controller_alloc_ack_i;
reg dis_controller_wg_alloc_valid_i;
reg dis_controller_wg_dealloc_valid_i;
reg dis_controller_wg_rejected_valid_i;
localparam ALLOC_NUM_STATES = 4;
localparam ST_AL_IDLE = 0;
localparam ST_AL_ALLOC = 2;
localparam ST_AL_HANDLE_RESULT = 4;
localparam ST_AL_ACK_PROPAGATION = 8;
reg [ALLOC_NUM_STATES-1:0] alloc_st;
function [RES_TABLE_ADDR_WIDTH-1:0] get_res_tbl_addr;
input[CU_ID_WIDTH-1 :0] cu_id;
begin
get_res_tbl_addr = cu_id[CU_ID_WIDTH-1 -: RES_TABLE_ADDR_WIDTH];
end
endfunction // if
always @ ( posedge clk or posedge rst ) begin
if(rst) begin
alloc_st <= ST_AL_IDLE;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
alloc_waiting <= 1'h0;
alloc_waiting_cu_id <= {CU_ID_WIDTH{1'b0}};
cu_groups_allocating <= {NUMBER_RES_TABLE{1'b0}};
dis_controller_alloc_ack_i <= 1'h0;
dis_controller_start_alloc_i <= 1'h0;
dis_controller_wg_alloc_valid_i <= 1'h0;
dis_controller_wg_dealloc_valid_i <= 1'h0;
dis_controller_wg_rejected_valid_i <= 1'h0;
// End of automatics
end
else begin
dis_controller_start_alloc_i <= 1'b0;
dis_controller_alloc_ack_i <= 1'b0;
// State machine that babysits the allocator.
// Waits until allocator input can be handled by the grt to acknowledge a allocated wg
case(alloc_st)
ST_AL_IDLE: begin
if(inflight_wg_buffer_alloc_valid && !(&cu_groups_allocating) ) begin
dis_controller_start_alloc_i <= 1'b1;
alloc_st <= ST_AL_ALLOC;
end
end
ST_AL_ALLOC: begin
if(allocator_cu_valid) begin
alloc_waiting <= 1'b1;
alloc_waiting_cu_id <= allocator_cu_id_out;
alloc_st <= ST_AL_HANDLE_RESULT;
end // if (allocator_cu_valid)
end
ST_AL_HANDLE_RESULT: begin
// If we served the waiting wg,
// then move on
if(!alloc_waiting) begin
dis_controller_alloc_ack_i <= 1'b1;
alloc_st <= ST_AL_ACK_PROPAGATION;
end
end // case: ST_AL_HANDLE_RESULT
ST_AL_ACK_PROPAGATION: begin
alloc_st <= ST_AL_IDLE;
end
endcase // case (alloc_st)
// Handles the grt
// Deallocations are always handled first
dis_controller_wg_dealloc_valid_i <= 1'b0;
dis_controller_wg_alloc_valid_i <= 1'b0;
dis_controller_wg_rejected_valid_i <= 1'b0;
if(gpu_interface_dealloc_available &&
!cu_groups_allocating[get_res_tbl_addr(gpu_interface_cu_id)]) begin
dis_controller_wg_dealloc_valid_i <= 1'b1;
cu_groups_allocating[get_res_tbl_addr(gpu_interface_cu_id)] <= 1'b1;
end
else if(alloc_waiting &&
!cu_groups_allocating[get_res_tbl_addr(alloc_waiting_cu_id)]) begin
if(allocator_cu_rejected) begin
alloc_waiting <= 1'b0;
dis_controller_wg_rejected_valid_i <= 1'b1;
end
else if(gpu_interface_alloc_available &&
inflight_wg_buffer_alloc_available) begin
alloc_waiting <= 1'b0;
dis_controller_wg_alloc_valid_i <= 1'b1;
cu_groups_allocating[get_res_tbl_addr(alloc_waiting_cu_id)] <= 1'b1;
end
end // if (alloc_waiting &&...
// End of allocation/deallocation
if(grt_wg_alloc_done) begin
cu_groups_allocating[get_res_tbl_addr(grt_wg_alloc_cu_id)] <= 1'b0;
end
else if(grt_wg_dealloc_done) begin
cu_groups_allocating[get_res_tbl_addr(grt_wg_dealloc_cu_id)] <= 1'b0;
end
end // else: !if(rst)
end // always @ ( posedge clk or posedge rst )
always @ ( /*AUTOSENSE*/cu_groups_allocating) begin : EXPAND_CU_GROUPS
reg[CU_ID_WIDTH :0] i;
for (i=0; i < NUMBER_CU; i=i+1) begin
cus_allocating[i] = cu_groups_allocating[get_res_tbl_addr(i[CU_ID_WIDTH-1:0])];
end
end
assign dis_controller_start_alloc = dis_controller_start_alloc_i;
assign dis_controller_alloc_ack = dis_controller_alloc_ack_i;
assign dis_controller_wg_alloc_valid = dis_controller_wg_alloc_valid_i;
assign dis_controller_wg_dealloc_valid = dis_controller_wg_dealloc_valid_i;
assign dis_controller_wg_rejected_valid = dis_controller_wg_rejected_valid_i;
assign dis_controller_cu_busy = cus_allocating;
endmodule // dis_controller
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A2111O_1_V
`define SKY130_FD_SC_HS__A2111O_1_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog wrapper for a2111o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a2111o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a2111o_1 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a2111o_1 (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A2111O_1_V
|
#include <bits/stdc++.h> using namespace std; struct PR { int to; int ne; } Prise[200010]; bool compare(PR a, PR b) { return (a.to - a.ne) < (b.to - b.ne); } int main(int argc, char const *argv[]) { int n, k; cin >> n >> k; int i; for (i = 0; i < n; i++) { cin >> Prise[i].to; } for (i = 0; i < n; i++) { cin >> Prise[i].ne; } sort(Prise, Prise + n, compare); int count = 0; for (i = 0; i < k; i++) { count += Prise[i].to; } for (i = k; i < n; i++) { if (Prise[i].to < Prise[i].ne) { count += Prise[i].to; } else { count += Prise[i].ne; } } cout << count << endl; return 0; } |
#pragma GCC optimize( Ofast ) #include<bits/stdc++.h> #define int long long using namespace std; void fileio(const string &s) { freopen((s+ .in ).c_str(), r ,stdin); freopen((s+ .out ).c_str(), w ,stdout); } const int INF=4e18; inline int read() { int x=0; bool flag=1; char c=getchar(); while(c< 0 ||c> 9 ) { if(c== - ) flag=0; c=getchar(); } while(c>= 0 &&c<= 9 ) { x=(x<<1)+(x<<3)+c- 0 ; c=getchar(); } return (flag?x:~(x-1)); } int t,tx,ty,ax,ay,bx,by; void solve() { ax=read(); ay=read(); bx=read(); by=read(); int ans=abs(ax-bx)+abs(ay-by); tx=read(); ty=read(); if(tx==ax&&tx==bx) { if(ay<ty&&ty<by) ans+=2; if(ay>ty&&ty>by) ans+=2; } if(ty==ay&&ty==by) { if(ax<tx&&tx<bx) ans+=2; if(ax>tx&&tx>bx) ans+=2; } cout<<ans<<endl; } signed main() { t=read(); while(t--) solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 200005; int a[N]; int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); sort(a + 1, a + n + 1); int lim = n / 2 - 1, res = 1e9 + 7; for (int i = 0; i <= lim; i++) { res = min(res, a[n - (lim - i)] - a[i + 1]); } printf( %d n , res); return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 3e5 + 100; int a[maxn]; long long dp[maxn][2]; int get1(long long n) { int sum = 0; while (n != 0) { if ((n & 1) == 1) sum += 1; n >>= 1; } return sum; } int main() { int N; cin >> N; for (int i = 1; i <= N; i++) { long long x; cin >> x; a[i] = get1(x); } dp[0][0] = 0; dp[0][1] = 0; dp[1][0] = 0; dp[1][1] = 0; for (int i = 2; i <= N; i++) { if (a[i] & 1) { dp[i][0] = dp[i - 1][1] + (a[i - 1] & 1); dp[i][1] = dp[i - 1][0] + !(a[i - 1] & 1); } else { dp[i][0] = dp[i - 1][0] + !(a[i - 1] & 1); dp[i][1] = dp[i - 1][1] + (a[i - 1] & 1); } } long long ans = 0; for (int i = 2; i <= N; i++) { int L = max(1, i - 120); int sum = a[i]; int pmax = a[i]; int res = 0; for (int j = i - 1; j >= L; j--) { pmax = max(pmax, a[j]); sum += a[j]; if (sum & 1) continue; if (pmax > sum / 2) res += 1; } ans += dp[i][0] - res; } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; long long mo(long long a) { return a % (long long)(1e9 + 7); } long long po(long long x, long long y, long long p) { long long res = 1; x = x % p; while (y > 0) { if (y & 1) res = (res * x) % p; y >>= 1; x = (x * x) % p; } return res % p; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long t; cin >> t; while (t--) { long long n; cin >> n; vector<long long> a(n); for (long long i = 0; i < a.size(); i++) cin >> a[i]; ; vector<long long> sp; long long i = 0; while (i < n && a[i] == 0) i++; for (; i < n; i++) { while (i < n && a[i]) i++; long long cnt = 0; while (i < n && a[i] == 0) { cnt++; i++; } sp.push_back(cnt); } if (a[n - 1] == 0) sp.pop_back(); long long ans = 0; for (long long e : sp) ans += e; cout << ans << n ; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A22O_TB_V
`define SKY130_FD_SC_HS__A22O_TB_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a22o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 A1 = 1'b1;
#160 A2 = 1'b1;
#180 B1 = 1'b1;
#200 B2 = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 A1 = 1'b0;
#280 A2 = 1'b0;
#300 B1 = 1'b0;
#320 B2 = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 B2 = 1'b1;
#440 B1 = 1'b1;
#460 A2 = 1'b1;
#480 A1 = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 B2 = 1'bx;
#560 B1 = 1'bx;
#580 A2 = 1'bx;
#600 A1 = 1'bx;
end
sky130_fd_sc_hs__a22o dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A22O_TB_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:38:39 08/19/2014
// Design Name: satadd
// Module Name: C:/ece4743/projects/lab2_solution_part1/tb_satadd.v
// Project Name: lab2_solution_part1
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: satadd
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_satadd;
// Inputs
reg [11:0] a;
reg [11:0] b;
reg [1:0] mode;
// Outputs
wire [11:0] y;
reg[8*100:1] aline;
integer fd;
integer count,status;
integer i_a, i_b, i_mode, i_result;
integer errors;
// Instantiate the Unit Under Test (UUT)
satadd uut (
.a(a),
.b(b),
.mode(mode),
.y(y)
);
initial begin
// Initialize Inputs
a = 0;
b = 0;
mode = 0;
fd = $fopen("test_out.txt","w");
$fclose(fd);
fd = $fopen("satadd_vectors.txt","r");
count = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
errors = 0;
while ($fgets(aline,fd)) begin
status = $sscanf(aline,"%x %x %x %x",i_mode, i_a, i_b, i_result);
a = i_a;
b = i_b;
mode = i_mode;
#10 //delay
if (i_result == y) begin
$display("PASS, mode: %x, a: %x, b: %x, y: %x\n",mode,a,b,y);
end else begin
$display("FAIL, mode: %x, a: %x, b: %x, y (actual): %x, y (expected): %x\n",mode,a,b,y,i_result);
errors = errors + 1;
end
end //end while
if (errors == 0) $display("PASS: All vectors pased.\n");
else $display ("FAIL: %d vectors failed\n",errors);
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYGATE4SD2_BEHAVIORAL_V
`define SKY130_FD_SC_LS__DLYGATE4SD2_BEHAVIORAL_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__dlygate4sd2 (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYGATE4SD2_BEHAVIORAL_V |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC optimize( unroll-loops ) #pragma GCC target( sse2 ) using namespace std; template <typename Arg1> void __f(const char* name, Arg1&& arg1) { cout << name << : << arg1 << n ; } template <typename Arg1, typename... Args> void __f(const char* names, Arg1&& arg1, Args&&... args) { const char* comma = strchr(names + 1, , ); cout.write(names, comma - names) << : << arg1 << | ; __f(comma + 1, args...); } void solution() { int n; cin >> n; vector<long long> arr(n); map<long long, long long> cnt; map<long long, long long> freq; for (int i = 0; i < n; i++) cin >> arr[i]; long long ans = 1; for (int i = 1; i < n + 1; i++) { cnt[arr[i - 1]]++; freq[cnt[arr[i - 1]]]++; long long x = cnt[arr[i - 1]]; long long y = freq[cnt[arr[i - 1]]]; if (x * y == i && i < n) ans = i + 1; else if (x * y == i - 1) ans = i; } cout << ans << n ; } signed main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t = 1; for (int i = 1; i < t + 1; i++) { solution(); } } |
#include <bits/stdc++.h> using namespace std; int main() { string str[101]; int n; cin >> n; for (int i = 0; i < n; ++i) cin >> str[i]; int maxi = 1; for (int i = 0; i < n - 1; ++i) { int m = 1; for (int j = i + 1; j < n; ++j) { if (str[i] == str[j]) ++m; } maxi = max(m, maxi); } cout << maxi << endl; return 0; } |
module Execute(p0, p1, pcNext, imm, shamt, aluOp, branchOp, aluSrc0, aluSrc1, regWe, memWe, addz, b, jal, jr, ov_EX_MEM, zr_EX_MEM, ne_EX_MEM, ov_EX, zr_EX, ne_EX, aluResult, branchAddr, branch, regWriteEnable, memoryWriteEnable);
input[15:0] p0, p1, pcNext;
input[11:0] imm;
input [3:0] shamt;
input [2:0] aluOp, branchOp;
// Control signals
input aluSrc0, aluSrc1, regWe, memWe, addz, b, jal, jr;
// Flags
input ov_EX_MEM, zr_EX_MEM, ne_EX_MEM;
output ov_EX, zr_EX, ne_EX;
output [15:0] aluResult, branchAddr;
output branch, regWriteEnable, memoryWriteEnable;
wire [15:0] src0, src1, branchJumpResult;
SRC_MUX srcmux(.p0(p0),
.p1(p1),
.imm(imm[7:0]),
.aluSrc0(aluSrc0),
.aluSrc1(aluSrc1),
.src0(src0),
.src1(src1));
ALU alu(.src0(src0),
.src1(src1),
.ctrl(aluOp),
.shamt(shamt),
.result(aluResult),
.ov(ov_EX),
.zr(zr_EX),
.ne(ne_EX));
BranchJumpAdder branchjumpadder(.pcNext(pcNext),
.jal(jal),
.branchOffset(imm[8:0]),
.jumpOffset(imm),
.result(branchJumpResult));
// Branch Codes, straight off the quick reference
localparam neq = 3'b000;
localparam eq = 3'b001;
localparam gt = 3'b010;
localparam lt = 3'b011;
localparam gte = 3'b100;
localparam lte = 3'b101;
localparam ovfl = 3'b110;
localparam uncond = 3'b111;
assign branchAddr = jr ? p0: // Set to P0
branchJumpResult;
assign branch = jal | jr |
(b &
((branchOp == uncond) |
((branchOp == neq) & !zr_EX_MEM) |
((branchOp == eq) & zr_EX_MEM) |
((branchOp == gt) & !(zr_EX_MEM | ne_EX_MEM)) |
((branchOp == lt) & ne_EX_MEM) |
((branchOp == gte) & !ne_EX_MEM) |
((branchOp == lte) & (ne_EX_MEM | zr_EX_MEM)) |
((branchOp == ovfl) & ov_EX_MEM)));
assign regWriteEnable = (!branch || jal) && (regWe || (addz && zr_EX_MEM));
assign memoryWriteEnable = !branch & memWe;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX = 2e6 + 5; int ends_here[MAX]; int qs, qe; struct data { int child[26]; int score; bool leaf; int suf; int ends; }; data arr[MAX]; int que[MAX]; int cur; struct aho_corasick { int root; int size; void init() { root = (++cur); } void insert(string s, int ind) { int node = root; for (int i = 0; i < s.length(); i++) { int c = s[i] - a ; if (!arr[node].child[c]) { arr[node].child[c] = (++cur); } node = arr[node].child[c]; } ++size; arr[node].leaf = 1; arr[node].ends = ind; } int find(int node, int c) { while (node != root) { if (arr[node].child[c]) { return arr[node].child[c]; } node = arr[node].suf; } if (arr[root].child[c]) { return arr[root].child[c]; } else { return root; } } void prepare() { qs = 0; qe = 0; que[qe++] = root; arr[root].suf = root; while (qs < qe) { int node = que[qs++]; for (int i = 0; i < 26; i++) { if (arr[node].child[i]) { int nxt = arr[node].child[i]; if (node != root) { arr[nxt].suf = find(arr[node].suf, i); } else { arr[nxt].suf = root; } arr[nxt].score = arr[arr[nxt].suf].score + arr[nxt].leaf; que[qe++] = nxt; } } } } long long query(string s) { int node = root; long long ans = 0; for (int i = 0; i < s.length(); i++) { int c = s[i] - a ; node = find(node, c); ans += arr[node].score; } return ans; } void dfs(int s1, int s2) { arr[s1].leaf |= arr[s2].leaf; for (int i = 0; i < 26; i++) { if (!arr[s2].child[i]) { continue; } if (!arr[s1].child[i]) { arr[s1].child[i] = arr[s2].child[i]; continue; } dfs(arr[s1].child[i], arr[s2].child[i]); } } void merge(aho_corasick other) { dfs(root, other.root); size += other.size; } }; int n, k; set<int> pos; vector<int> hlp; void check(int ind) { int f = 0; for (int i = ind;; i += k) { if (ends_here[i + k - 1] == 0) { f = 1; break; } if (pos.find(ends_here[i + k - 1]) != pos.end()) { f = 1; break; } pos.insert(ends_here[i + k - 1]); hlp.push_back(ends_here[i + k - 1]); if (pos.size() == n) { break; } } if (f == 0) { printf( YES n ); for (auto x : hlp) { printf( %d , x); } exit(0); } else { pos.clear(); hlp.clear(); } } string str[100005]; int main() { aho_corasick a; a.init(); scanf( %d %d , &n, &k); string s; cin >> s; s = s + s; int m; scanf( %d , &m); for (int i = 1; i <= m; i++) { cin >> str[i]; a.insert(str[i], i); } a.prepare(); int st = a.root; for (int i = 0; i < s.length(); i++) { int c = s[i] - a ; st = a.find(st, c); if (arr[st].score > 0) { ends_here[i] = arr[st].ends; } } for (int i = 0; i < k; i++) { check(i); } printf( NO n ); return 0; } |
`include "config.inc"
module video2ram(
input clock,
input nreset,
input [7:0] R,
input [7:0] G,
input [7:0] B,
input [11:0] counterX,
input [11:0] counterY,
input line_doubler,
input is_pal,
output [23:0] wrdata,
output [`RAM_WIDTH-1:0] wraddr,
output wren,
output starttrigger,
input DCVideoConfig dcVideoConfig,
input [7:0] color_config_data
);
reg [9:0] H_CAPTURE_START;
reg [9:0] H_CAPTURE_END;
reg [9:0] V_CAPTURE_START;
reg [9:0] V_CAPTURE_END;
reg wren_reg;
reg [23:0] wrdata_reg;
reg [14:0] wraddr_reg;
reg [14:0] ram_addrY_reg;
reg trigger;
reg [11:0] counterX_prev;
reg line_doubler_reg = 0;
reg is_pal_reg = 0;
wire wren_cv;
wire [14:0] wraddr_cv;
wire [23:0] wrdata_cv;
wire starttrigger_cv;
colorconv cv(
.clock(clock),
.color_config(color_config_data[2:0]),
.in_wren(wren_reg),
.in_wraddr(wraddr_reg),
.in_red(wrdata_reg[23:16]),
.in_green(wrdata_reg[15:8]),
.in_blue(wrdata_reg[7:0]),
.in_starttrigger(trigger),
.wren(wren_cv),
.wraddr(wraddr_cv),
.wrdata(wrdata_cv),
.starttrigger(starttrigger_cv)
);
gammaconv gv(
.clock(clock),
.gamma_config(color_config_data[7:3]),
.in_wren(wren_cv),
.in_wraddr(wraddr_cv),
.in_red(wrdata_cv[23:16]),
.in_green(wrdata_cv[15:8]),
.in_blue(wrdata_cv[7:0]),
.in_starttrigger(starttrigger_cv),
.wren(wren),
.wraddr(wraddr),
.wrdata(wrdata),
.starttrigger(starttrigger)
);
always @(*) begin
if (line_doubler_reg) begin
H_CAPTURE_START = dcVideoConfig.i_horizontal_capture_start;
H_CAPTURE_END = dcVideoConfig.i_horizontal_capture_end;
V_CAPTURE_START = dcVideoConfig.i_vertical_capture_start;
V_CAPTURE_END = dcVideoConfig.i_vertical_capture_end;
end else begin
H_CAPTURE_START = dcVideoConfig.p_horizontal_capture_start;
H_CAPTURE_END = dcVideoConfig.p_horizontal_capture_end;
V_CAPTURE_START = dcVideoConfig.p_vertical_capture_start;
V_CAPTURE_END = dcVideoConfig.p_vertical_capture_end;
end
end
`define GetWriteAddr(x) (ram_addrY_reg + (x - H_CAPTURE_START))
`define IsFirstBuffer(y) ((y - V_CAPTURE_START) < dcVideoConfig.buffer_size)
`define IsTriggerPoint(y) (`IsFirstBuffer(y) && wraddr_reg == (line_doubler_reg ? dcVideoConfig.trigger_address_i : dcVideoConfig.trigger_address_p))
`define IsVerticalCaptureTime(y) ( \
line_doubler_reg \
? (is_pal_reg \
? (y < 288 || (y > 312 && y < V_CAPTURE_END)) \
: (y < 240 || (y > 262 && y < V_CAPTURE_END))) \
: (y >= V_CAPTURE_START && y < V_CAPTURE_END) \
)
`define IsCaptureTime(x,y) ( \
`IsVerticalCaptureTime(y) && x >= H_CAPTURE_START && x < H_CAPTURE_END \
)
initial begin
wren_reg <= 0;
wrdata_reg <= 24'd0;
wraddr_reg <= 0;
ram_addrY_reg <= 0;
trigger <= 0;
end
always @ (posedge clock or negedge nreset) begin
if (~nreset) begin
wren_reg <= 0;
wrdata_reg <= 24'd0;
wraddr_reg <= 0;
ram_addrY_reg <= 0;
trigger <= 0;
line_doubler_reg <= 0;
is_pal_reg <= 0;
end else begin
line_doubler_reg <= line_doubler;
is_pal_reg <= is_pal;
counterX_prev <= counterX;
if (counterX_prev == H_CAPTURE_END && counterX == H_CAPTURE_END) begin // calculate ram_addrY_reg once per line
if (`IsVerticalCaptureTime(counterY)
&& ram_addrY_reg < dcVideoConfig.ram_numwords - dcVideoConfig.buffer_line_length) begin
ram_addrY_reg <= ram_addrY_reg + dcVideoConfig.buffer_line_length;
end else begin
ram_addrY_reg <= 0;
end
end
if (`IsCaptureTime(counterX, counterY)) begin
wren_reg <= 1;
wraddr_reg <= `GetWriteAddr(counterX);
wrdata_reg <= { R, G, B };
if (`IsTriggerPoint(counterY)) begin
trigger <= 1'b1;
end else begin
trigger <= 1'b0;
end
end else begin
wren_reg <= 0;
trigger <= 1'b0;
end
end
end
// assign wren = wren_reg;
// assign wraddr = wraddr_reg;
// assign wrdata = wrdata_reg;
// assign starttrigger = trigger;
endmodule |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:02:11 05/12/2016
// Design Name:
// Module Name: fifo
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module fifo
#(
parameter B=8, // number of bits in a word
W=2 // number of address bits
)
(
input wire clk, reset,
input wire rd, wr,
input wire [B-1:0] w_data,
output wire empty, full,
output wire [B-1:0] r_data
);
//signal declaration
reg [B-1:0] array_reg [2**W-1:0]; // register array
reg [W-1:0] w_ptr_reg, w_ptr_next, w_ptr_succ;
reg [W-1:0] r_ptr_reg, r_ptr_next, r_ptr_succ;
reg full_reg, empty_reg, full_next, empty_next;
wire wr_en;
// body
// register file write operation
always @(posedge clk)
if (wr_en)
array_reg[w_ptr_reg] <= w_data;
// register file read operation
assign r_data = array_reg[r_ptr_reg];
// write enabled only when FIFO is not full
assign wr_en = wr & ~full_reg;
// fifo control logic
// register for read and write pointers
always @(posedge clk, posedge reset)
if (reset)
begin
w_ptr_reg <= 0;
r_ptr_reg <= 0;
full_reg <= 1'b0;
empty_reg <= 1'b1;
end
else
begin
w_ptr_reg <= w_ptr_next;
r_ptr_reg <= r_ptr_next;
full_reg <= full_next;
empty_reg <= empty_next;
end
// next-state logic for read and write pointers
always @*
begin
// successive pointer values
w_ptr_succ = w_ptr_reg + 1'b1;
r_ptr_succ = r_ptr_reg + 1'b1;
// default: keep old values
w_ptr_next = w_ptr_reg;
r_ptr_next = r_ptr_reg;
full_next = full_reg;
empty_next = empty_reg;
case ({wr, rd})
// 2'b00: no op
2'b01: // read
if (~empty_reg) // not empty
begin
r_ptr_next = r_ptr_succ;
full_next = 1'b0;
if (r_ptr_succ==w_ptr_reg)
empty_next = 1'b1;
end
2'b10: // write
if (~full_reg) // not full
begin
w_ptr_next = w_ptr_succ;
empty_next = 1'b0;
if (w_ptr_succ==r_ptr_reg)
full_next = 1'b1;
end
2'b11: // write and read
begin
w_ptr_next = w_ptr_succ;
r_ptr_next = r_ptr_succ;
end
endcase
end
// output
assign full = full_reg;
assign empty = empty_reg;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long L[100005]; long long P[100005][40]; long long T[100005]; vector<long long> graph[100005]; long long mx = 0, hh; void dfs(long long src, long long par) { if (src == -1) L[par] = 0; else L[par] = L[src] + 1; if (mx < L[par]) { hh = par; mx = max(mx, L[par]); } T[par] = src; long long len = graph[par].size(); for (long long i = 0; i < (long long)graph[par].size(); i++) { long long v = graph[par][i]; if (v != src) { dfs(par, v); } } } void dfs1(long long src, long long par) { if (src == -1) L[par] = 0; else L[par] = L[src] + 1; if (mx < L[par]) { hh = par; mx = max(mx, L[par]); } long long len = graph[par].size(); for (long long i = 0; i < (long long)graph[par].size(); i++) { long long v = graph[par][i]; if (v != src) { dfs1(par, v); } } } int main() { long long i, j, n, m, t, a, b, c, d, e, f, x, y; scanf( %lld , &t); for (long long cz = 0; cz < t; cz++) { scanf( %lld%lld%lld%lld%lld , &n, &a, &b, &c, &d); for (i = 0; i < n - 1; i++) { scanf( %lld%lld , &x, &y); graph[x].push_back(y); graph[y].push_back(x); } mx = 0; dfs(-1, a); long long cc, dd; cc = L[b]; for (i = 0; i <= n; i++) { L[i] = 0; } mx = 0; dfs1(-1, hh); if (c * 2 >= min(d, mx) || cc <= c) { printf( Alice n ); } else printf( Bob n ); for (i = 0; i <= n; i++) { graph[i].clear(); L[i] = 0; } } } |
#include <bits/stdc++.h> using namespace std; string s = What are you doing at the end of the world? Are you busy? Will you save us? ; string s1 = What are you doing while sending ; string s2 = ? Are you busy? Will you send ; string s3 = ? ; const int MAX_N = 1e5 + 10; const long long MAX_F = 1e18 + 10; long long F[MAX_N] = {(int)s.size()}; char f(int n, long long k) { if (F[n] <= k) return . ; if (n == 0) return s[k]; if (k < (int)s1.size()) return s1[k]; k -= (int)s1.size(); if (k < F[n - 1]) return f(n - 1, k); k -= F[n - 1]; if (k < (int)s2.size()) return s2[k]; k -= (int)s2.size(); if (k < F[n - 1]) return f(n - 1, k); k -= F[n - 1]; return s3[k]; } int main() { ios_base ::sync_with_stdio(false), cout.tie(0), cin.tie(0); int l = (int)s1.size() + (int)s2.size() + (int)s3.size(); for (int i = 1; i < MAX_N; i++) { if (2 * F[i - 1] + l > MAX_F) F[i] = MAX_F; else F[i] = 2 * F[i - 1] + l; } int q; cin >> q; while (q--) { int n; long long k; cin >> n >> k; cout << f(n, k - 1); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O211AI_BLACKBOX_V
`define SKY130_FD_SC_HDLL__O211AI_BLACKBOX_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o211ai (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O211AI_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int m, n, a[7][7] = {{0, 1, 2}, {1, 0, 2}, {1, 2, 0}, {2, 1, 0}, {2, 0, 1}, {0, 2, 1}, {0, 1, 2}}; int main() { cin >> n >> m; n %= 6; cout << a[n][m]; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long N = 105; struct Point { long long x, y; Point() { x = y = 0; } Point(long long _x, long long _y) { x = _x; y = _y; } void input() { cin >> x >> y; } Point operator+(const Point &a) const { return Point(x + a.x, y + a.y); } Point operator-(const Point &a) const { return Point(x - a.x, y - a.y); } Point Rotate(const Point &a) const { return Point(-a.y, a.x); } long long modul(void) const { return 1LL * x + 1LL * y; } bool operator<(const Point &a) const { return (x == a.x ? y < a.y : x < a.x); } bool operator==(const Point &a) const { return (x == a.x && y == a.y); } }; Point rotation(const Point &o, const Point &a, long long t) { Point res = a; while (t--) { res = o + o.Rotate(res - o); } return res; } long long dis(Point u, Point v) { long long dx = u.x - v.x; long long dy = u.y - v.y; return dx * dx + dy * dy; } bool isSquare(vector<Point> &u) { vector<Point> mi = u; sort(mi.begin(), mi.end()); map<long long, long long> xx, yy; for (long long i = 0; i < mi.size(); i++) { xx[mi[i].x]++; yy[mi[i].y]++; if (xx[mi[i].x] == 3 || yy[mi[i].y] == 3) return 0; } vector<long long> d; for (long long i = 0; i < 4; i++) { for (long long j = i + 1; j < 4; j++) d.push_back(dis(mi[i], mi[j])); } sort(d.begin(), d.end()); if (d[0] == d[3] && d[4] == d[5] && d[0] && d[3] + d[0] == d[4]) return 1; return 0; } bool isRectangle(vector<Point> &u) { vector<Point> mi = u; sort(mi.begin(), mi.end()); map<long long, long long> xx, yy; for (long long i = 0; i < mi.size(); i++) { xx[mi[i].x]++; yy[mi[i].y]++; if (xx[mi[i].x] == 3 || yy[mi[i].y] == 3) return 0; } vector<long long> d; for (long long i = 0; i < 4; i++) { for (long long j = i + 1; j < 4; j++) d.push_back(dis(mi[i], mi[j])); } sort(d.begin(), d.end()); if (d[0] == d[1] && d[2] == d[3] && d[4] == d[5] && d[0] && d[0] + d[2] == d[5]) return 1; return 0; } void run() { Point pos[9]; int col[9]; for (long long i = 1; i <= 8; i++) { pos[i].input(); } bool ok = 0; for (int i = 1; i <= 8; i++) { for (int j = i + 1; j <= 8; j++) { for (int k = j + 1; k <= 8; k++) { for (int t = k + 1; t <= 8; t++) { for (long long run = 1; run <= 8; run++) col[run] = (run == j || run == k || run == t || run == i); vector<Point> rec; vector<Point> square; for (long long run = 1; run <= 8; run++) if (col[run]) rec.push_back(pos[run]); else square.push_back(pos[run]); if (!isSquare(square)) continue; if (!isRectangle(rec)) continue; cout << YES << endl; for (long long run = 1; run <= 8; run++) if (!col[run]) cout << run << ; cout << endl; for (long long run = 1; run <= 8; run++) if (col[run]) cout << run << ; return; } } } } cout << NO ; } int main() { ios_base::sync_with_stdio(false); run(); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_P_PP_PKG_SN_TB_V
`define SKY130_FD_SC_HS__UDP_DFF_P_PP_PKG_SN_TB_V
/**
* udp_dff$P_pp$PKG$sN: Positive edge triggered D flip-flop
* (Q output UDP).
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__udp_dff_p_pp_pkg_sn.v"
module top();
// Inputs are registered
reg D;
reg SLEEP_B;
reg NOTIFIER;
reg KAPWR;
reg VGND;
reg VPWR;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
KAPWR = 1'bX;
NOTIFIER = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 KAPWR = 1'b0;
#60 NOTIFIER = 1'b0;
#80 SLEEP_B = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 KAPWR = 1'b1;
#180 NOTIFIER = 1'b1;
#200 SLEEP_B = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 KAPWR = 1'b0;
#300 NOTIFIER = 1'b0;
#320 SLEEP_B = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 SLEEP_B = 1'b1;
#440 NOTIFIER = 1'b1;
#460 KAPWR = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 SLEEP_B = 1'bx;
#560 NOTIFIER = 1'bx;
#580 KAPWR = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hs__udp_dff$P_pp$PKG$sN dut (.D(D), .SLEEP_B(SLEEP_B), .NOTIFIER(NOTIFIER), .KAPWR(KAPWR), .VGND(VGND), .VPWR(VPWR), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_P_PP_PKG_SN_TB_V
|
#include <bits/stdc++.h> using namespace std; pair<int, pair<int, int> > a[200020]; int f[200020]; int v[200020]; int n, m; int F(int x) { if (f[x] == x) { return x; } f[x] = F(f[x]); v[f[x]] |= v[x]; return f[x]; } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) { f[i] = i; v[i] = 0; } for (int i = 0; i < m; i++) { scanf( %d%d%d , &a[i].second.first, &a[i].second.second, &a[i].first); } sort(a, a + m); reverse(a, a + m); long long ans = 0; for (int i = 0; i < m; i++) { int x = a[i].second.first; int y = a[i].second.second; x = F(x); y = F(y); if (x == y && v[x] == 0) { v[x] = 1; ans += a[i].first; } else if (x != y && (v[x] == 0 || v[y] == 0)) { v[y] |= v[x]; f[x] = y; ans += a[i].first; } } cout << ans << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__MUX2I_TB_V
`define SKY130_FD_SC_LS__MUX2I_TB_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__mux2i.v"
module top();
// Inputs are registered
reg A0;
reg A1;
reg S;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A0 = 1'bX;
A1 = 1'bX;
S = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A0 = 1'b0;
#40 A1 = 1'b0;
#60 S = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A0 = 1'b1;
#180 A1 = 1'b1;
#200 S = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A0 = 1'b0;
#320 A1 = 1'b0;
#340 S = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 S = 1'b1;
#540 A1 = 1'b1;
#560 A0 = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 S = 1'bx;
#680 A1 = 1'bx;
#700 A0 = 1'bx;
end
sky130_fd_sc_ls__mux2i dut (.A0(A0), .A1(A1), .S(S), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__MUX2I_TB_V
|
#include <bits/stdc++.h> using namespace std; const int MX = 400000; long long l[500000], r[500000], k[500000], b[500000], a[500000], pref1[500000], pref2[500000], s = MX; long long f(long long b1, long long a1, long long b2, long long a2) { return (b1 - b2) / (a1 - a2); } void add(long long kx, long long bx) { if (s == MX) { l[s] = -2e18; r[s] = 2e18; b[s] = bx; k[s] = kx; s--; return; } if (f(bx, kx, b[s + 1], k[s + 1]) > r[s + 1]) { s++; add(kx, bx); return; } l[s] = -2e18; r[s] = f(bx, kx, b[s + 1], k[s + 1]); b[s] = bx; k[s] = kx; l[s + 1] = r[s] + 1; s--; return; } int main() { ios::sync_with_stdio(0); long long n; cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; pref1[0] = a[0]; pref2[0] = a[0]; for (int i = 1; i < n; i++) { pref1[i] = pref1[i - 1] + a[i]; pref2[i] = pref2[i - 1] + a[i] * (i + 1); } long long ans = 0; for (long long i = 0; i < n; i++) { ans = max(ans, pref2[i]); long long lt = s + 1, rt = MX; while (lt < rt) { long long mid = (lt + rt) / 2; if (lt == rt - 1) mid++; if (pref1[i] < l[mid]) rt = mid - 1; else lt = mid; } long long q = 0, t = 0; if (i > 0) { q = pref2[i - 1]; t = pref1[i - 1]; } if (lt <= MX) ans = max(ans, pref2[i] - b[lt] + pref1[i] * k[lt]); add(-i - 1, -(pref1[i] * (i + 1) - pref2[i])); } cout << ans << n ; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O221AI_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__O221AI_BEHAVIORAL_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__o221ai (
Y ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , B2, B1 );
or or1 (or1_out , A2, A1 );
nand nand0 (nand0_out_Y, or1_out, or0_out, C1);
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O221AI_BEHAVIORAL_V |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2014 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2014.4
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Transparent Data Latch with Asynchronous Preset and Gate Enable
// /___/ /\ Filename : LDPE.v
// \ \ / \
// \___\/\___\
//
// Revision:
// 08/25/10 - Initial version.
// 11/01/11 - Disable timing check when set reset active (CR633224)
// 12/08/11 - add MSGON and XON attribures (CR636891)
// 01/16/12 - 640813 - add MSGON and XON functionality
// 04/16/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module LDPE #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
parameter MSGON = "TRUE",
parameter XON = "TRUE",
`endif
parameter [0:0] INIT = 1'b1,
parameter [0:0] IS_G_INVERTED = 1'b0,
parameter [0:0] IS_PRE_INVERTED = 1'b0
)(
output Q,
input D,
input G,
input GE,
input PRE
);
wire [0:0] IS_G_INVERTED_BIN;
wire [0:0] IS_PRE_INVERTED_BIN;
reg Q_out = INIT;
wire D_in;
wire GE_in;
wire G_in;
wire PRE_in;
assign IS_G_INVERTED_BIN = IS_G_INVERTED;
assign IS_PRE_INVERTED_BIN = IS_PRE_INVERTED;
`ifdef XIL_TIMING
wire D_dly;
wire GE_dly;
wire G_dly;
wire PRE_dly;
assign D_in = D_dly;
assign G_in = G_dly ^ IS_G_INVERTED_BIN;
assign GE_in = (GE === 1'bz) || GE_dly; // rv 1
assign PRE_in = (PRE !== 1'bz) && (PRE_dly ^ IS_PRE_INVERTED_BIN); // rv 0
`else
assign D_in = D;
assign G_in = G ^ IS_G_INVERTED_BIN;
assign GE_in = (GE === 1'bz) || GE; // rv 1
assign PRE_in = (PRE !== 1'bz) && (PRE ^ IS_PRE_INVERTED_BIN); // rv 0
`endif
assign Q = Q_out;
reg notifier;
wire notifier1;
reg rst_int, set_int;
wire o_out;
`ifdef XIL_TIMING
wire ngsr, in_out;
wire nset;
wire in_clk_enable, in_clk_enable_n, in_clk_enable_p;
wire ce_clk_enable, ce_clk_enable_n, ce_clk_enable_p;
wire rst_clk_enable, rst_clk_enable1;
wire tl_enable, tl_enable_n, tl_enable_p;
wire clk_en_n, clk_en_p;
`endif
tri0 GSR = glbl.GSR;
`ifdef XIL_TIMING
not (nset, PRE_in);
not (ngsr, GSR);
xor (in_out, D_dly, Q);
and (in_clk_enable, ngsr, nset, GE_in);
and (ce_clk_enable, ngsr, nset, in_out);
and (rst_clk_enable, ngsr, GE_in);
and (tl_enable, ngsr, nset);
assign notifier1 = (XON == "FALSE") ? 1'bx : notifier;
assign in_clk_enable_n = (MSGON =="TRUE") && in_clk_enable && IS_G_INVERTED_BIN;
assign in_clk_enable_p = (MSGON =="TRUE") && in_clk_enable && ~IS_G_INVERTED_BIN;
assign ce_clk_enable_n = (MSGON =="TRUE") && ce_clk_enable && IS_G_INVERTED_BIN;
assign ce_clk_enable_p = (MSGON =="TRUE") && ce_clk_enable && ~IS_G_INVERTED_BIN;
assign rst_clk_enable1 = (MSGON =="FALSE") ? 1'b0 : rst_clk_enable;
assign tl_enable_n = (MSGON =="TRUE") && tl_enable && IS_G_INVERTED_BIN;
assign tl_enable_p = (MSGON =="TRUE") && tl_enable && ~IS_G_INVERTED_BIN;
assign clk_en_n = (MSGON =="TRUE") && IS_G_INVERTED_BIN;
assign clk_en_p = (MSGON =="TRUE") && ~IS_G_INVERTED_BIN;
`else
assign notifier1 = 1'bx;
`endif
always @(GSR or PRE_in) begin
if (GSR) begin
if (INIT) begin
rst_int = 1'b0;
set_int = 1'b1;
end
else begin
rst_int = 1'b1;
set_int = 1'b0;
end
end
else begin
rst_int = 1'b0;
set_int = PRE_in;
end
end
latchsre_ldpe (o_out, G_in, D_in, set_int, rst_int, GE_in, notifier1);
always @(o_out)
Q_out = o_out;
specify
(D => Q) = (100:100:100, 100:100:100);
(G => Q) = (100:100:100, 100:100:100);
(GE => Q) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING
(PRE => Q) = (0:0:0, 0:0:0);
(negedge PRE => (Q +: 1)) = (0:0:0, 0:0:0);
(posedge PRE => (Q +: 1)) = (0:0:0, 0:0:0);
$period (negedge G, 0:0:0, notifier);
$period (posedge G, 0:0:0, notifier);
$recrem (negedge GE, negedge G, 0:0:0, 0:0:0, notifier,tl_enable_n,tl_enable_n,GE_dly, G_dly);
$recrem (negedge GE, posedge G, 0:0:0, 0:0:0, notifier,tl_enable_p,tl_enable_p,GE_dly, G_dly);
$recrem (negedge PRE, negedge G, 0:0:0, 0:0:0, notifier,tl_enable_n,tl_enable_n,PRE_dly, G_dly);
$recrem (negedge PRE, posedge G, 0:0:0, 0:0:0, notifier,tl_enable_p,tl_enable_p,PRE_dly, G_dly);
$recrem (posedge PRE, negedge G, 0:0:0, 0:0:0, notifier,tl_enable_n,tl_enable_n,PRE_dly, G_dly);
$recrem (posedge PRE, posedge G, 0:0:0, 0:0:0, notifier,tl_enable_p,tl_enable_p,PRE_dly, G_dly);
$setuphold (negedge G, negedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_n,in_clk_enable_n,G_dly,D_dly);
$setuphold (negedge G, negedge GE, 0:0:0, 0:0:0, notifier,ce_clk_enable_n,ce_clk_enable_n,G_dly,GE_dly);
$setuphold (negedge G, posedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_n,in_clk_enable_n,G_dly,D_dly);
$setuphold (negedge G, posedge GE, 0:0:0, 0:0:0, notifier,ce_clk_enable_n,ce_clk_enable_n,G_dly,GE_dly);
$setuphold (posedge G, negedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_p,in_clk_enable_p,G_dly,D_dly);
$setuphold (posedge G, negedge GE, 0:0:0, 0:0:0, notifier,ce_clk_enable_p,ce_clk_enable_p,G_dly,GE_dly);
$setuphold (posedge G, posedge D, 0:0:0, 0:0:0, notifier,in_clk_enable_p,in_clk_enable_p,G_dly,D_dly);
$setuphold (posedge G, posedge GE, 0:0:0, 0:0:0, notifier,ce_clk_enable_p,ce_clk_enable_p,G_dly,GE_dly);
$width (negedge G, 0:0:0, 0, notifier);
$width (negedge PRE, 0:0:0, 0, notifier);
$width (posedge G, 0:0:0, 0, notifier);
$width (posedge GE, 0:0:0, 0, notifier);
$width (posedge PRE, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
primitive latchsre_ldpe (q, clk, d, set, rst, ge, notifier);
output q; reg q;
input clk, d, set, rst, ge, notifier;
table
// clk d set rst ge notifier q q+;
1 0 0 0 1 ? : ? : 0;
1 1 0 0 1 ? : ? : 1;
0 ? 0 0 ? ? : ? : -;
? ? 0 0 0 ? : ? : -;
? 0 0 ? ? ? : 0 : -;
? 1 ? 0 ? ? : 1 : -;
? ? 1 0 ? ? : ? : 1;
? ? ? 1 ? ? : ? : 0;
0 ? 0 x ? ? : 0 : 0;
? ? 0 x 0 ? : 0 : 0;
1 0 0 x 1 ? : ? : 0;
0 ? x 0 ? ? : 1 : 1;
? ? x 0 0 ? : 1 : 1;
1 1 x 0 1 ? : ? : 1;
? ? ? ? ? * : ? : x;
endtable
endprimitive
|
#include <bits/stdc++.h> const int MAXN = 1000 + 10; int n; std::set<int> g[MAXN]; std::vector<std::pair<int, int> > process(bool ty) { std::vector<std::pair<int, int> > ans; for (int i = 2; i < n; i++) { while (!g[1].count(i + 1)) { int k = *std::next(g[1].find(i)); assert(g[i].count(k)); g[i].erase(k); g[k].erase(i); for (auto v : g[i]) { if (v != 1 && g[k].count(v)) { assert(i < v && v < k); g[1].insert(v); g[v].insert(1); if (ty) { ans.emplace_back(v, 1); } else { ans.emplace_back(i, k); } break; } } } } return ans; } void read() { for (int i = 1; i <= n; i++) g[i].clear(); for (int i = 1; i <= n - 3; i++) { int a, b; scanf( %d%d , &a, &b); g[a].insert(b); g[b].insert(a); } for (int i = 1; i < n; i++) { g[i].insert(i + 1); g[i + 1].insert(i); } g[1].insert(n); g[n].insert(1); } int main() { scanf( %d , &n); read(); auto ans1 = process(0); read(); auto ans2 = process(1); std::reverse(ans2.begin(), ans2.end()); ans1.insert(ans1.end(), ans2.begin(), ans2.end()); printf( %lu n , ans1.size()); for (auto i : ans1) { printf( %d %d n , i.first, i.second); } } |
#include <bits/stdc++.h> using namespace std; int main() { int i = 0, n; bool ok(false); cin >> n; while (i * (i + 1) / 2 <= n && ok == false) { if (i * (i + 1) / 2 == n) { ok = true; } i++; } (ok == true) ? cout << YES : cout << NO ; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFBBN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__SDFBBN_FUNCTIONAL_PP_V
/**
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
* clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`include "../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_ls__udp_dff_nsr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__sdfbbn (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire SET ;
wire CLK ;
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
not not2 (CLK , CLK_N );
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_ls__udp_dff$NSR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, mux_out, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFBBN_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[n]; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) if (a[i] % 2 == 0) a[i]--; for (int i = 0; i < n; i++) cout << a[i] << ; return 0; } |
`include "sdio_defines.v"
module sdio_device_phy (
input rst,
input i_posedge_stb,
//Configuration
input i_ddr_en,
input i_spi_phy,
input i_sd1_phy,
input i_sd4_phy,
//Data Link Interface
output o_cmd_phy_idle,
output reg o_cmd_phy,
output reg o_cmd_stb,
output reg o_cmd_crc_good_stb,
output reg [5:0] o_cmd,
output reg [31:0] o_cmd_arg,
input i_rsps_stb,
input [39:0] i_rsps,
input [7:0] i_rsps_len,
input i_rsps_fail,
output reg o_rsps_idle,
//XXX: Need to hook this up
input i_interrupt,
input i_data_activate,
output o_data_finished,
input i_write_flag,
input [12:0] i_data_count,
output o_data_wr_stb,
output [7:0] o_data_wr_data,
input i_data_rd_stb,
input [7:0] i_data_rd_data,
output o_data_hst_rdy,
input i_data_com_rdy,
//FPGA Interface
input i_sdio_clk,
input i_sdio_clk_x2,
output reg o_sdio_cmd_dir,
input i_sdio_cmd_in,
output reg o_sdio_cmd_out,
output o_sdio_data_dir,
input [7:0] i_sdio_data_in,
output [7:0] o_sdio_data_out
);
//Local Parameters
localparam IDLE = 4'h0;
localparam READ_COMMAND = 4'h1;
localparam RESPONSE_DIR_BIT = 4'h2;
localparam WAIT_FOR_RESPONSE = 4'h3;
localparam RESPONSE = 4'h4;
localparam RESPONSE_FIRST_CRC= 4'h5;
localparam RESPONSE_CRC = 4'h6;
localparam RESPONSE_FINISHED = 4'h7;
//Local Registers/Wires
reg [3:0] state;
reg [3:0] phy_mode;
reg [7:0] bit_count;
reg txrx_dir;
reg [6:0] r_crc;
wire [6:0] crc;
wire [6:0] crc_good;
wire busy;
wire crc_bit;
reg crc_en;
reg crc_rst;
reg [39:0] lcl_rsps;
//Submodules
crc7 crc_gen (
.clk (i_sdio_clk ),
.rst (crc_rst ),
.bit (crc_bit ),
.crc (crc ),
.en (crc_en )
);
sdio_data_phy data_phy(
.clk (i_sdio_clk ),
.rst (rst ),
.i_interrupt (i_interrupt ),
.i_posedge_stb (i_posedge_stb ),
.i_ddr_en (i_ddr_en ),
.i_spi_phy (i_spi_phy ),
.i_sd1_phy (i_sd1_phy ),
.i_sd4_phy (i_sd4_phy ),
.i_activate (i_data_activate ),
.o_finished (o_data_finished ),
.i_write_flag (i_write_flag ),
.i_data_count (i_data_count ),
.o_data_wr_stb (o_data_wr_stb ),
.o_data_wr_data (o_data_wr_data ),
.i_data_rd_stb (i_data_rd_stb ),
.i_data_rd_data (i_data_rd_data ),
.o_data_hst_rdy (o_data_hst_rdy ),
.i_data_com_rdy (i_data_com_rdy ),
.o_sdio_data_dir (o_sdio_data_dir ),
.i_sdio_data_in (i_sdio_data_in ),
.o_sdio_data_out (o_sdio_data_out )
);
//Asynchronous Logic
assign busy = ((state != IDLE) || !i_sdio_cmd_in);
assign crc_bit = o_sdio_cmd_dir ? o_sdio_cmd_out: i_sdio_cmd_in;
assign o_cmd_phy_idle = !busy;
//Synchronous Logic
//XXX: this clock should probably be i_sdio_clk
always @ (posedge i_sdio_clk) begin
if (rst) begin
//Start out in SPI mode
bit_count <= 0;
txrx_dir <= 0;
state <= IDLE;
o_rsps_idle <= 0;
o_cmd_stb <= 0;
o_cmd <= 0;
o_cmd_arg <= 0;
r_crc <= 0;
o_sdio_cmd_out <= 1;
o_sdio_cmd_dir <= 0;
crc_en <= 0;
crc_rst <= 1;
lcl_rsps <= 0;
end
else begin
//strobes
o_cmd_stb <= 0;
o_cmd_crc_good_stb<= 0;
crc_rst <= 0;
//Incrementing bit count
if (busy) begin
bit_count <= bit_count + 1;
end
else begin
bit_count <= 0;
end
case (state)
IDLE: begin
o_rsps_idle <= 1;
o_sdio_cmd_out <= 1;
o_sdio_cmd_dir <= 0;
crc_en <= 0;
crc_rst <= 0;
//Detect beginning of transaction when the command line goes low
if (!i_sdio_cmd_in) begin
o_rsps_idle <= 0;
crc_en <= 1;
//New Command Detected
state <= READ_COMMAND;
end
else begin
crc_rst <= 1;
end
end
READ_COMMAND: begin
if (bit_count == `SDIO_C_BIT_ARG_END) begin
crc_en <= 0;
end
if (bit_count == `SDIO_C_BIT_TXRX_DIR)
txrx_dir <= i_sdio_cmd_in;
else if ((bit_count >= `SDIO_C_BIT_CMD_START) && (bit_count <= `SDIO_C_BIT_CMD_END))
o_cmd <= {o_cmd[4:0], i_sdio_cmd_in};
else if ((bit_count >= `SDIO_C_BIT_ARG_START) && (bit_count <= `SDIO_C_BIT_ARG_END))
o_cmd_arg <= {o_cmd_arg[30:0], i_sdio_cmd_in};
else if ((bit_count >= `SDIO_C_BIT_CRC_START) && (bit_count <= `SDIO_C_BIT_CRC_END))
r_crc <= {r_crc[5:0], i_sdio_cmd_in};
else begin //Last Bit
r_crc <= {r_crc[5:0], i_sdio_cmd_in};
/*
if (r_crc == crc)
o_cmd_crc_good_stb <= 1;
crc_rst <= 1;
o_cmd_stb <= 1;
bit_count <= 0;
o_sdio_cmd_dir <= 1;
o_sdio_cmd_out <= 1;
*/
state <= RESPONSE_DIR_BIT;
end
end
RESPONSE_DIR_BIT: begin
//Test
if (r_crc == crc) begin
o_cmd_crc_good_stb <= 1;
crc_rst <= 1;
end
//$display("CMD:Args %h:%h", o_cmd, o_cmd_arg);
o_cmd_stb <= 1;
o_sdio_cmd_out <= 1;
o_sdio_cmd_dir <= 1;
//End Test
state <= WAIT_FOR_RESPONSE;
end
WAIT_FOR_RESPONSE: begin
if (i_rsps_stb) begin
lcl_rsps <= i_rsps;
state <= RESPONSE;
bit_count <= 0;
o_sdio_cmd_out <= 0; //Direction From Device to Host
end
end
RESPONSE: begin
crc_en <= 1;
o_sdio_cmd_out <= lcl_rsps[39];
lcl_rsps <= {lcl_rsps[38:0], 1'b0};
if (bit_count >= i_rsps_len) begin
crc_en <= 0;
state <= RESPONSE_FIRST_CRC;
bit_count <= 0;
end
end
RESPONSE_FIRST_CRC: begin
o_sdio_cmd_out <= crc[6];
r_crc <= {crc[5:0], 1'b0};
state <= RESPONSE_CRC;
end
RESPONSE_CRC: begin
o_sdio_cmd_out <= r_crc[6];
r_crc <= {r_crc[5:0], 1'b0};
if (bit_count >= 8'h6) begin
state <= RESPONSE_FINISHED;
end
end
RESPONSE_FINISHED: begin
o_sdio_cmd_out <= 1'b1;
state <= IDLE;
end
default: begin
o_sdio_cmd_dir <= 0;
state <= IDLE;
end
endcase
if (i_rsps_fail) begin
//Do not respond when we detect a fail
state <= IDLE;
end
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////
/// ////
/// Wishbone arbiter, burst-compatible ////
/// ////
/// Simple round-robin arbiter for multiple Wishbone masters ////
/// ////
/// Olof Kindgren, ////
/// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2013 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module wb_arbiter
#(parameter dw = 32,
parameter aw = 32,
parameter num_masters = 2)
(
input wb_clk_i,
input wb_rst_i,
// Wishbone Master Interface
input [num_masters*aw-1:0] wbm_adr_i,
input [num_masters*dw-1:0] wbm_dat_i,
input [num_masters*4-1:0] wbm_sel_i,
input [num_masters-1:0] wbm_we_i,
input [num_masters-1:0] wbm_cyc_i,
input [num_masters-1:0] wbm_stb_i,
input [num_masters*3-1:0] wbm_cti_i,
input [num_masters*2-1:0] wbm_bte_i,
output [num_masters*dw-1:0] wbm_dat_o,
output [num_masters-1:0] wbm_ack_o,
output [num_masters-1:0] wbm_err_o,
output [num_masters-1:0] wbm_rty_o,
// Wishbone Slave interface
output [aw-1:0] wbs_adr_o,
output [dw-1:0] wbs_dat_o,
output [3:0] wbs_sel_o,
output wbs_we_o,
output wbs_cyc_o,
output wbs_stb_o,
output [2:0] wbs_cti_o,
output [1:0] wbs_bte_o,
input [dw-1:0] wbs_dat_i,
input wbs_ack_i,
input wbs_err_i,
input wbs_rty_i);
`include "verilog_utils.vh"
///////////////////////////////////////////////////////////////////////////////
// Parameters
///////////////////////////////////////////////////////////////////////////////
localparam master_sel_bits = num_masters > 1 ? `clog2(num_masters) : 1;
wire [num_masters-1:0] grant;
wire [master_sel_bits-1:0] master_sel;
wire active;
arbiter
#(.NUM_PORTS (num_masters))
arbiter0
(.clk (wb_clk_i),
.rst (wb_rst_i),
.request (wbm_cyc_i),
.grant (grant),
.select (master_sel),
.active (active));
//Mux active master
assign wbs_adr_o = wbm_adr_i[master_sel*aw+:aw];
assign wbs_dat_o = wbm_dat_i[master_sel*dw+:dw];
assign wbs_sel_o = wbm_sel_i[master_sel*4+:4];
assign wbs_we_o = wbm_we_i [master_sel];
assign wbs_cyc_o = wbm_cyc_i[master_sel] & active;
assign wbs_stb_o = wbm_stb_i[master_sel];
assign wbs_cti_o = wbm_cti_i[master_sel*3+:3];
assign wbs_bte_o = wbm_bte_i[master_sel*2+:2];
assign wbm_dat_o = {num_masters{wbs_dat_i}};
assign wbm_ack_o = ((wbs_ack_i & active) << master_sel);
assign wbm_err_o = ((wbs_err_i & active) << master_sel);
assign wbm_rty_o = ((wbs_rty_i & active) << master_sel);
endmodule // wb_arbiter
|
#include <bits/stdc++.h> using namespace std; int a, b, c, d, e; int ar[200100]; int ar1[200100]; int main() { vector<int> arr(200100); string s, s1; cin >> s; cin >> s1; a = min(s.length(), s1.length()); b = a; c = 1; while ((c <= a) && (s[s.length() - c] == s1[s1.length() - c])) ++c; cout << (a - c + 1) + max(s.length(), s1.length()) - c + 1; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Tue Apr 18 23:15:16 2017
// Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ bram_2048_0_stub.v
// Design : bram_2048_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clka, ena, wea, addra, dina, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[10:0],dina[19:0],douta[19:0]" */;
input clka;
input ena;
input [0:0]wea;
input [10:0]addra;
input [19:0]dina;
output [19:0]douta;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int oo = (int)1e9; const double PI = 2 * acos(0); const double eps = 1e-9; inline int comp(const double &a, const double &b) { if (fabs(a - b) < eps) return 0; return a > b ? 1 : -1; } int di[] = {1, -1, 0, 0, 1, -1, 1, -1}; int dj[] = {0, 0, 1, -1, 1, -1, -1, 1}; int diK[] = {-2, -2, -1, 1, 2, 2, 1, -1}; int djK[] = {-1, 1, 2, 2, 1, -1, -2, -2}; int I, J; inline bool val(const int &i, const int &j) { if (i < 0 || j < 0 || i >= I || j >= J) return false; return true; } int N; int n; int ret[109][109]; bool val() { for (int i = 0; i < (int)(I); i++) for (int j = 0; j < (int)(J); j++) for (int k = 0; k < (int)(4); k++) { int ni = i + di[k]; int nj = j + dj[k]; if (val(ni, nj) && abs(ret[i][j] - ret[ni][nj] == 1)) return 0; } return 1; } bool vis[10009]; bool dfs(int i, int j) { if (i == I) return 1; if (j == J) return dfs(i + 1, 0); for (int a = 1; a <= I * J; a++) if (!vis[a]) { if (i && abs(a - ret[i - 1][j]) == 1) continue; if (j && abs(a - ret[i][j - 1]) == 1) continue; vis[a] = 1; ret[i][j] = a; if (dfs(i, j + 1)) return 1; vis[a] = 0; } return 0; } int main() { cin >> I >> J; if (I * J <= 1000000) { if (dfs(0, 0)) { for (int i = 0; i < (int)(I); i++) { for (int j = 0; j < (int)(J); j++) { if (j) printf( ); printf( %d , ret[i][j]); } printf( n ); } } else cout << -1 << endl; return 0; } vector<pair<int, int> > v; for (int i = 0; i < (int)(I); i++) for (int j = 0; j < (int)(J); j++) v.push_back(make_pair(i, j)); int cc = 1; for (int i = 1; i < I * J; i += 2) ret[v[i].first][v[i].second] = cc++; for (int i = 0; i < I * J; i += 2) ret[v[i].first][v[i].second] = cc++; if (!val()) { cc = 1; for (int i = 0; i < I * J; i += 2) ret[v[i].first][v[i].second] = cc++; for (int i = 1; i < I * J; i += 2) ret[v[i].first][v[i].second] = cc++; if (!val()) { cout << -1 << endl; return 0; } } for (int i = 0; i < (int)(I); i++) { for (int j = 0; j < (int)(J); j++) { if (j) printf( ); printf( %d , ret[i][j]); } printf( n ); } return 0; } |
/*
* Copyright (c) 2000 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This program tests that a non-integer delay gets its extra
* precision accounted for if the timescale supports it. In this
* example, set the units to 1ms, but set the precision so that the
* numbers can be given accurate to .1ms. This should cause a delay
* of 2.4 and 2.6 to really be different.
*/
`timescale 1ms / 100us
module main;
reg err;
reg clk;
reg out1, out2;
realtime time1;
realtime time2;
real eps;
always @(posedge clk) #2.4 begin
$display($time,,$realtime, " set out1 == 1");
time1 = $realtime;
out1 = 1;
end
always @(posedge clk) #2.6 begin
$display($time,,$realtime, " set out2 == 1");
time2 = $realtime;
out2 = 1;
end
initial begin
clk = 0;
out1 = 0;
out2 = 0;
time1 = 0;
time2 = 0;
err = 0;
$timeformat(-3,1,"ms",5);
#1 if (out1 !== 0) begin
$display("Error -- out1 s/b 0 at time $time but is=%x", out1);
err =1 ;
end
clk = 1;
#3 if (out1 !== 1) begin
$display("Error -- out1 s/b 1 at time $time but is=%x", out1);
err =1 ;
end
eps = time1 - 3.4;
if (eps < 0.0)
eps = 0.0 - eps;
if (eps > 0.0001) begin
$display("Error -- time1 s/b 3.4 but is=%t", time1);
err =1 ;
end
#1 eps = time2 - 3.6;
if (eps < 0.0)
eps = 0.0 - eps;
if (eps > 0.0001) begin
$display("Error -- time2 s/b 3.6 but is=%t, ", time2);
err =1 ;
end
// Use a gold file to check this version.
end // initial begin
endmodule // main
|
#include <bits/stdc++.h> using namespace std; bool isused[26]; string s, t; vector<pair<int, int> > v; int abs(int num) { if (num < 0) return -num; else return num; } int main(void) { cin >> s >> t; int slen = s.size(); for (int i = 0; i < slen; i++) isused[(s[i] - a )] = true; int tlen = t.size(); for (int i = 0; i < tlen; i++) { if (isused[(t[i] - a )] == false) { cout << -1 << endl; return 0; } } for (int i = 0; i < tlen;) { pair<int, int> temp = make_pair(-1, -1); for (int j = 0; j < slen; j++) { if (t[i] == s[j]) { int k1 = 0; while (i + k1 + 1 < tlen && j + k1 + 1 < slen && t[i + k1 + 1] == s[j + k1 + 1]) k1++; int k2 = 0; while (i + k2 + 1 < tlen && j - k2 - 1 >= 0 && t[i + k2 + 1] == s[j - k2 - 1]) k2++; if (k1 >= k2) { if (temp.first == -1) temp = make_pair(j, j + k1); else if (abs(temp.second - temp.first) < k1) temp = make_pair(j, j + k1); } else { if (temp.first == -1) temp = make_pair(j, j - k2); else if (abs(temp.first - temp.second) < k2) temp = make_pair(j, j - k2); } } } if (temp.first <= temp.second) i += (temp.second - temp.first) + 1; else i += (temp.first - temp.second) + 1; v.push_back(make_pair(temp.first + 1, temp.second + 1)); } cout << v.size() << endl; for (int i = 0; i < v.size(); i++) cout << v[i].first << << v[i].second << endl; return 0; } |
`timescale 1ns/1ps
/***************************************************************************
Name:
Date: 7/11/2016
Founction: pwm capture deal
Note:
****************************************************************************/
module led_capture(
led_input,clk,rst_n,tx_start,tx_data
);
input led_input;
input clk;
input rst_n;
output tx_start;
output[7:0] tx_data;
reg ready;
reg[31:0] counter;
reg[31:0] pos_counter;
reg[31:0] nextpos_counter;
reg[31:0] periodcounter;
reg pos_counter_flag;
reg nextpos_counter_flag;
wire pos_btn;
/*******************************************************************************
*counter
*********************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n) begin
counter <= 'h0;
end
else begin
counter <= (counter < 32'hFFFFFFFF) ? (counter + 1'b1) : 'h0 ;
end
end
/*******************************************************************************
*Instance
*********************************************************************************/
pos_capture pos_capture_instance(
.led_input(led_input),
.clk(clk),
.rst_n(rst_n),
.pos_btn(pos_btn)
);
captuer_tx captuer_tx_instance(
.clk(clk),
.rst_n(rst_n),
.tx_start(tx_start),
.capture_ready(ready),
.periodcounter(periodcounter),
.tx_data(tx_data),
.counter(counter),
.led_input(led_input)
);
/*******************************************************************************
*Capture pos counter value
*********************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
pos_counter <= 'h0;
pos_counter_flag <= 'h0;
end
else if(pos_btn && (pos_counter_flag != 1'b1))begin
pos_counter <= counter;
pos_counter_flag <= 1'b1;
end
end
/*******************************************************************************
*Capture next pos counter value
*********************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
nextpos_counter <= 'h0;
nextpos_counter_flag <= 'h0;
end
else if(pos_btn && pos_counter_flag && (nextpos_counter_flag != 1'b1))begin
nextpos_counter <= counter;
nextpos_counter_flag <= 1'b1;
end
end
/*******************************************************************************
*Calculate the period
*********************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
periodcounter <= 'h0;
ready <= 'h0;
end
else if(pos_counter_flag && nextpos_counter_flag)begin
periodcounter <= nextpos_counter - pos_counter;
ready <= 'h1;
end
end
endmodule |
#include <bits/stdc++.h> namespace IO { char buf[1000000], *p1, *p2; inline char getc() { if (p1 == p2) p2 = (p1 = buf) + fread(buf, 1, 1000000, stdin); return p1 == p2 ? EOF : *(p1++); } template <typename tp> inline void r(tp &n) { n = 0; char c = getc(); while (!isdigit(c)) c = getc(); while (isdigit(c)) n = n * 10 + c - 48, c = getc(); } template <typename tp, typename... Args> inline void r(tp &n, Args &...args) { r(n); r(args...); } template <typename tp> inline void write(tp n) { if (n / 10) write(n / 10); putchar(n % 10 + 48); } template <typename tp> inline void w(tp n, char c = n ) { write(n); putchar(c); } }; // namespace IO using namespace IO; const int N = 1e6 + 2333; using namespace std; int m; int dep[N], f[N][25]; int LCA(int x, int y) { if (dep[x] < dep[y]) x ^= y ^= x ^= y; for (int i = 20; i >= 0; --i) if (dep[f[x][i]] >= dep[y]) x = f[x][i]; if (x == y) return x; for (int i = 20; i >= 0; --i) if (f[x][i] != f[y][i]) x = f[x][i], y = f[y][i]; return f[x][0]; } int dis(int a, int b) { return dep[a] + dep[b] - dep[LCA(a, b)] * 2; } int main() { r(m); int n = 4, u = 2, v = 3, nowdis = 2; for (int i = 2; i <= 4; ++i) f[i][0] = 1, dep[i] = 1; while (m--) { int x; r(x); dep[n + 1] = dep[x] + 1, f[n + 1][0] = x; dep[n + 2] = dep[x] + 1, f[n + 2][0] = x; for (int i = 0; f[n + 1][i]; ++i) f[n + 1][i + 1] = f[f[n + 1][i]][i]; for (int i = 0; f[n + 2][i]; ++i) f[n + 2][i + 1] = f[f[n + 2][i]][i]; n += 2; int a = dis(u, n), b = dis(v, n), c = nowdis; nowdis = max(max(a, b), c); if (nowdis == a) v = n; else if (nowdis == b) u = n; w(nowdis); } return 0; } |
#include <bits/stdc++.h> using namespace std; int n; vector<pair<pair<int, int>, int> > v; signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> n; for (int i = 1; i <= n; i++) { int x, y; cin >> x >> y; v.push_back(pair<pair<int, int>, int>(pair<int, int>(x / 2012, y), i)); } sort(v.begin(), v.end()); for (int i = 0; i < v.size(); i++) cout << v[i].second << ; } |
#include <bits/stdc++.h> using namespace std; const int N = 55; int res[N][N][N][N]; int tmp[N][N], dat[N][N]; string s[N]; int n, m, q, a, b, c, d; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> m >> q; for (int i = 1; i <= n; i++) { cin >> s[i]; for (int j = 1; j <= m; j++) dat[i][j] = (s[i][j - 1] == 1 ); } for (int i = 0; i <= n; i++) { for (int j = 0; j <= m; j++) { if (i == 0 || j == 0) continue; tmp[i][j] = tmp[i - 1][j] + tmp[i][j - 1] - tmp[i - 1][j - 1] + dat[i][j]; } } for (int xa = 1; xa <= n; xa++) for (int ya = 1; ya <= m; ya++) for (int xb = 1; xb <= n; xb++) for (int yb = 1; yb <= m; yb++) { int sum = tmp[xb][yb] - tmp[xa - 1][yb] - tmp[xb][ya - 1] + tmp[xa - 1][ya - 1]; res[xa][ya][xb][yb] = (sum == 0); } for (int xa = n; xa >= 2; xa--) for (int ya = 1; ya <= m; ya++) for (int xb = xa; xb <= n; xb++) for (int yb = ya; yb <= m; yb++) res[xa - 1][ya][xb][yb] += res[xa][ya][xb][yb]; for (int xa = 1; xa <= n; xa++) for (int ya = m; ya >= 2; ya--) for (int xb = xa; xb <= n; xb++) for (int yb = ya; yb <= m; yb++) res[xa][ya - 1][xb][yb] += res[xa][ya][xb][yb]; for (int xa = 1; xa <= n; xa++) for (int ya = 1; ya <= m; ya++) for (int xb = xa; xb <= n; xb++) for (int yb = ya; yb <= m; yb++) res[xa][ya][xb + 1][yb] += res[xa][ya][xb][yb]; for (int xa = 1; xa <= n; xa++) for (int ya = 1; ya <= m; ya++) for (int xb = xa; xb <= n; xb++) for (int yb = ya; yb <= m; yb++) res[xa][ya][xb][yb + 1] += res[xa][ya][xb][yb]; while (q--) { cin >> a >> b >> c >> d; cout << res[a][b][c][d] << n ; } return 0; } |
module fsm_full(
clock , // Clock
reset , // Active high reset
req_0 , // Active high request from agent 0
req_1 , // Active high request from agent 1
req_2 , // Active high request from agent 2
req_3 , // Active high request from agent 3
gnt_0 , // Active high grant to agent 0
gnt_1 , // Active high grant to agent 1
gnt_2 , // Active high grant to agent 2
gnt_3 // Active high grant to agent 3
);
// Port declaration here
input clock ; // Clock
input reset ; // Active high reset
input req_0 ; // Active high request from agent 0
input req_1 ; // Active high request from agent 1
input req_2 ; // Active high request from agent 2
input req_3 ; // Active high request from agent 3
output gnt_0 ; // Active high grant to agent 0
output gnt_1 ; // Active high grant to agent 1
output gnt_2 ; // Active high grant to agent 2
output gnt_3 ; // Active high grant to agent
// Internal Variables
reg gnt_0 ; // Active high grant to agent 0
reg gnt_1 ; // Active high grant to agent 1
reg gnt_2 ; // Active high grant to agent 2
reg gnt_3 ; // Active high grant to agent
parameter [2:0] IDLE = 3'b000;
parameter [2:0] GNT0 = 3'b001;
parameter [2:0] GNT1 = 3'b010;
parameter [2:0] GNT2 = 3'b011;
parameter [2:0] GNT3 = 3'b100;
reg [2:0] state, next_state;
always @ (state or req_0 or req_1 or req_2 or req_3)
begin
next_state = 0;
case(state)
IDLE : if (req_0 == 1'b1) begin
next_state = GNT0;
end else if (req_1 == 1'b1) begin
next_state= GNT1;
end else if (req_2 == 1'b1) begin
next_state= GNT2;
end else if (req_3 == 1'b1) begin
next_state= GNT3;
end else begin
next_state = IDLE;
end
GNT0 : if (req_0 == 1'b0) begin
next_state = IDLE;
end else begin
next_state = GNT0;
end
GNT1 : if (req_1 == 1'b0) begin
next_state = IDLE;
end else begin
next_state = GNT1;
end
GNT2 : if (req_2 == 1'b0) begin
next_state = IDLE;
end else begin
next_state = GNT2;
end
GNT3 : if (req_3 == 1'b0) begin
next_state = IDLE;
end else begin
next_state = GNT3;
end
default : next_state = IDLE;
endcase
end
always @ (posedge clock)
begin : OUTPUT_LOGIC
if (reset) begin
gnt_0 <= 1'b0;
gnt_1 <= 1'b0;
gnt_2 <= 1'b0;
gnt_3 <= 1'b0;
state <= IDLE;
end else begin
state <= next_state;
case(state)
IDLE : begin
gnt_0 <= 1'b0;
gnt_1 <= 1'b0;
gnt_2 <= 1'b0;
gnt_3 <= 1'b0;
end
GNT0 : begin
gnt_0 <= 1'b1;
end
GNT1 : begin
gnt_1 <= 1'b1;
end
GNT2 : begin
gnt_2 <= 1'b1;
end
GNT3 : begin
gnt_3 <= 1'b1;
end
default : begin
state <= IDLE;
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void solve() { long long i, j, k, l, n, m, a, b, u; cin >> n; vector<long long> v(n); map<long long, long long> mp; long long ans = 0LL; priority_queue<pair<long long, long long>> pq; for (i = 0; i < n; i++) { cin >> v[i]; mp[v[i]]++; } unordered_set<long long> st; for (auto it : mp) { pq.push({it.second, it.first}); } map<long long, long long> mp2; while (!pq.empty()) { auto p = pq.top(); pq.pop(); if (p.first == 0) continue; if (st.find(p.first) == st.end()) { st.insert(p.first); ans += p.first; } else { pq.push({p.first - 1, p.second}); } } cout << ans << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t; cin >> t; while (t--) solve(); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR4B_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__NOR4B_BEHAVIORAL_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__nor4b (
Y ,
A ,
B ,
C ,
D_N
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input D_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire nor0_out_Y;
// Name Output Other arguments
not not0 (not0_out , D_N );
nor nor0 (nor0_out_Y, A, B, C, not0_out);
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR4B_BEHAVIORAL_V |
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.4 (win64) Build Wed Nov 18 09:43:45 MST 2015
// Date : Wed Mar 02 15:28:43 2016
// Host : Dries007Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// d:/Xilinx/Projects/VGA/VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v
// Design : clk_wiz_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module clk_wiz_0(clk_in1, clk_out1, reset, locked)
/* synthesis syn_black_box black_box_pad_pin="clk_in1,clk_out1,reset,locked" */;
input clk_in1;
output clk_out1;
input reset;
output locked;
endmodule
|
//-------------------------------------------------------------------
//-- tristate1_tb.v
//-- Banco de pruebas para la puerta tri-estado
//-------------------------------------------------------------------
//-- BQ November 2015. Written by Juan Gonzalez (Obijuan)
//-------------------------------------------------------------------
//-- GPL license
//-------------------------------------------------------------------
//-------------------------------------------------------------------
//-- Este codigo simula bien, pero NO se sintetiza con Yosys + icestorm:
//-- Todavía el sopote para puertas tri-estado no es completo
//-- Mensaje de error:
/*
2.12.2. Executing Verilog-2005 frontend.
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/arith_map.v' to AST representation.
Generating RTLIL representation for module `\_80_ice40_alu'.
Successfully finished Verilog frontend.
Mapping error1.$ternary$error1.v:22$2 ($tribuf) with simplemap.
terminate called after throwing an instance of 'std::out_of_range'
what(): vector::_M_range_check: __n (which is 1) >= this->size() (which is 1)
Aborted (core dumped)
Makefile:173: recipe for target 'error1.bin' failed
make: *** [error1.bin] Error 134
*/
module error1_tb();
//-- Registro para generar la señal de reloj
reg clk = 0;
//-- Led a controlar
wire [1:0] leds;
//-- Instanciar el componente
error1
dut(
.clk(clk),
.leds(leds)
);
//-- Generador de reloj. Periodo 2 unidades
always #1 clk = ~clk;
//-- Proceso al inicio
initial begin
//-- Fichero donde almacenar los resultados
$dumpfile("error1_tb.vcd");
$dumpvars(0, error1_tb);
# 100 $display("FIN de la simulacion");
$finish;
end
endmodule
|
//
// Generated by Bluespec Compiler (build 0fccbb13)
//
//
// Ports:
// Name I/O size props
// RDY_server_reset_request_put O 1 reg
// RDY_server_reset_response_get O 1
// read_rs1 O 64
// read_rs1_port2 O 64
// read_rs2 O 64
// read_rs3 O 64
// CLK I 1 clock
// RST_N I 1 reset
// read_rs1_rs1 I 5
// read_rs1_port2_rs1 I 5
// read_rs2_rs2 I 5
// read_rs3_rs3 I 5
// write_rd_rd I 5
// write_rd_rd_val I 64 reg
// EN_server_reset_request_put I 1
// EN_server_reset_response_get I 1
// EN_write_rd I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkFPR_RegFile(CLK,
RST_N,
EN_server_reset_request_put,
RDY_server_reset_request_put,
EN_server_reset_response_get,
RDY_server_reset_response_get,
read_rs1_rs1,
read_rs1,
read_rs1_port2_rs1,
read_rs1_port2,
read_rs2_rs2,
read_rs2,
read_rs3_rs3,
read_rs3,
write_rd_rd,
write_rd_rd_val,
EN_write_rd);
input CLK;
input RST_N;
// action method server_reset_request_put
input EN_server_reset_request_put;
output RDY_server_reset_request_put;
// action method server_reset_response_get
input EN_server_reset_response_get;
output RDY_server_reset_response_get;
// value method read_rs1
input [4 : 0] read_rs1_rs1;
output [63 : 0] read_rs1;
// value method read_rs1_port2
input [4 : 0] read_rs1_port2_rs1;
output [63 : 0] read_rs1_port2;
// value method read_rs2
input [4 : 0] read_rs2_rs2;
output [63 : 0] read_rs2;
// value method read_rs3
input [4 : 0] read_rs3_rs3;
output [63 : 0] read_rs3;
// action method write_rd
input [4 : 0] write_rd_rd;
input [63 : 0] write_rd_rd_val;
input EN_write_rd;
// signals for module outputs
wire [63 : 0] read_rs1, read_rs1_port2, read_rs2, read_rs3;
wire RDY_server_reset_request_put, RDY_server_reset_response_get;
// register rg_state
reg [1 : 0] rg_state;
reg [1 : 0] rg_state$D_IN;
wire rg_state$EN;
// ports of submodule f_reset_rsps
wire f_reset_rsps$CLR,
f_reset_rsps$DEQ,
f_reset_rsps$EMPTY_N,
f_reset_rsps$ENQ,
f_reset_rsps$FULL_N;
// ports of submodule regfile
wire [63 : 0] regfile$D_IN,
regfile$D_OUT_1,
regfile$D_OUT_2,
regfile$D_OUT_3,
regfile$D_OUT_4;
wire [4 : 0] regfile$ADDR_1,
regfile$ADDR_2,
regfile$ADDR_3,
regfile$ADDR_4,
regfile$ADDR_5,
regfile$ADDR_IN;
wire regfile$WE;
// rule scheduling signals
wire CAN_FIRE_RL_rl_reset_loop,
CAN_FIRE_RL_rl_reset_start,
CAN_FIRE_server_reset_request_put,
CAN_FIRE_server_reset_response_get,
CAN_FIRE_write_rd,
WILL_FIRE_RL_rl_reset_loop,
WILL_FIRE_RL_rl_reset_start,
WILL_FIRE_server_reset_request_put,
WILL_FIRE_server_reset_response_get,
WILL_FIRE_write_rd;
// action method server_reset_request_put
assign RDY_server_reset_request_put = f_reset_rsps$FULL_N ;
assign CAN_FIRE_server_reset_request_put = f_reset_rsps$FULL_N ;
assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ;
// action method server_reset_response_get
assign RDY_server_reset_response_get =
rg_state == 2'd2 && f_reset_rsps$EMPTY_N ;
assign CAN_FIRE_server_reset_response_get =
rg_state == 2'd2 && f_reset_rsps$EMPTY_N ;
assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ;
// value method read_rs1
assign read_rs1 = regfile$D_OUT_4 ;
// value method read_rs1_port2
assign read_rs1_port2 = regfile$D_OUT_3 ;
// value method read_rs2
assign read_rs2 = regfile$D_OUT_2 ;
// value method read_rs3
assign read_rs3 = regfile$D_OUT_1 ;
// action method write_rd
assign CAN_FIRE_write_rd = 1'd1 ;
assign WILL_FIRE_write_rd = EN_write_rd ;
// submodule f_reset_rsps
FIFO20 #(.guarded(1'd1)) f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(f_reset_rsps$ENQ),
.DEQ(f_reset_rsps$DEQ),
.CLR(f_reset_rsps$CLR),
.FULL_N(f_reset_rsps$FULL_N),
.EMPTY_N(f_reset_rsps$EMPTY_N));
// submodule regfile
RegFile #(.addr_width(32'd5),
.data_width(32'd64),
.lo(5'h0),
.hi(5'd31)) regfile(.CLK(CLK),
.ADDR_1(regfile$ADDR_1),
.ADDR_2(regfile$ADDR_2),
.ADDR_3(regfile$ADDR_3),
.ADDR_4(regfile$ADDR_4),
.ADDR_5(regfile$ADDR_5),
.ADDR_IN(regfile$ADDR_IN),
.D_IN(regfile$D_IN),
.WE(regfile$WE),
.D_OUT_1(regfile$D_OUT_1),
.D_OUT_2(regfile$D_OUT_2),
.D_OUT_3(regfile$D_OUT_3),
.D_OUT_4(regfile$D_OUT_4),
.D_OUT_5());
// rule RL_rl_reset_start
assign CAN_FIRE_RL_rl_reset_start = rg_state == 2'd0 ;
assign WILL_FIRE_RL_rl_reset_start = CAN_FIRE_RL_rl_reset_start ;
// rule RL_rl_reset_loop
assign CAN_FIRE_RL_rl_reset_loop = rg_state == 2'd1 ;
assign WILL_FIRE_RL_rl_reset_loop = CAN_FIRE_RL_rl_reset_loop ;
// register rg_state
always@(EN_server_reset_request_put or
WILL_FIRE_RL_rl_reset_loop or WILL_FIRE_RL_rl_reset_start)
case (1'b1)
EN_server_reset_request_put: rg_state$D_IN = 2'd0;
WILL_FIRE_RL_rl_reset_loop: rg_state$D_IN = 2'd2;
WILL_FIRE_RL_rl_reset_start: rg_state$D_IN = 2'd1;
default: rg_state$D_IN = 2'b10 /* unspecified value */ ;
endcase
assign rg_state$EN =
EN_server_reset_request_put || WILL_FIRE_RL_rl_reset_start ||
WILL_FIRE_RL_rl_reset_loop ;
// submodule f_reset_rsps
assign f_reset_rsps$ENQ = EN_server_reset_request_put ;
assign f_reset_rsps$DEQ = EN_server_reset_response_get ;
assign f_reset_rsps$CLR = 1'b0 ;
// submodule regfile
assign regfile$ADDR_1 = read_rs3_rs3 ;
assign regfile$ADDR_2 = read_rs2_rs2 ;
assign regfile$ADDR_3 = read_rs1_port2_rs1 ;
assign regfile$ADDR_4 = read_rs1_rs1 ;
assign regfile$ADDR_5 = 5'h0 ;
assign regfile$ADDR_IN = write_rd_rd ;
assign regfile$D_IN = write_rd_rd_val ;
assign regfile$WE = EN_write_rd ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
rg_state <= `BSV_ASSIGNMENT_DELAY 2'd0;
end
else
begin
if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
rg_state = 2'h2;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkFPR_RegFile
|
#include <bits/stdc++.h> using namespace std; bool a[2001][2001], w[2001][2001]; int n, fi, fj, si, sj, dist, s, clr = 4; inline bool val(int x, int y) { return (x > 0 && y > 0 && x < n && y < n); } inline void clear(int x, int y) { s = 0; for (int i = 0; i < clr; i++) for (int j = 0; j < clr; j++) if (a[i + x][j + y]) s++; if (s <= clr) for (int i = 0; i < clr; i++) for (int j = 0; j < clr; j++) a[i + x][j + y] = 0; } void dfs(int x, int y) { w[x][y] = 1; s++; if (((x - fi) * (x - fi)) + ((y - fj) * (y - fj)) > dist) dist = ((x - fi) * (x - fi)) + ((y - fj) * (y - fj)); if (val(x - 1, y) && a[x - 1][y] && !w[x - 1][y]) dfs(x - 1, y); if (val(x + 1, y) && a[x + 1][y] && !w[x + 1][y]) dfs(x + 1, y); if (val(x, y - 1) && a[x][y - 1] && !w[x][y - 1]) dfs(x, y - 1); if (val(x, y + 1) && a[x][y + 1] && !w[x][y + 1]) dfs(x, y + 1); } int main() { ios_base::sync_with_stdio(0); int i, j, x, as = 0, ac = 0; cin >> n; for (i = 0; i < n; i++) for (j = 0; j < n; j++) cin >> a[i][j]; for (i = 0; i < n; i += clr) for (j = 0; j < n; j += clr) clear(i, j); for (i = 0; i < n; i++) for (j = 0; j < n; j++) if (!w[i][j] && a[i][j]) { dist = s = 0; fi = i, fj = j; dfs(i, j); if (dist < 200.0) { a[i][j] = 0; continue; } s *= 1.2; double d = sqrt(dist), sq = ((d / sqrt(2.0)) * (d / sqrt(2.0))), circ = ((d / 2.0) * (d / 2.0)) * M_PI; if (abs(s - sq) < abs(s - circ)) as++; else ac++; } cout << ac << << as; return 0; } |
#include <bits/stdc++.h> using namespace std; void sol_problem(const long *, long); int main() { long n, t, *matriz; cin >> n >> t; matriz = new long[n - 1]; for (int i = 0; i < n - 1; i++) cin >> matriz[i]; sol_problem(matriz, t); return 0; } void sol_problem(const long *matriz, long t) { long ind = 1 + matriz[0]; while (ind <= t) { if (ind == t) { cout << YES ; break; } ind += matriz[ind - 1]; } if (ind > t) cout << NO ; } |
module altera_edge_detector #(
parameter PULSE_EXT = 0, // 0, 1 = edge detection generate single cycle pulse, >1 = pulse extended for specified clock cycle
parameter EDGE_TYPE = 0, // 0 = falling edge, 1 or else = rising edge
parameter IGNORE_RST_WHILE_BUSY = 0 // 0 = module internal reset will be default whenever rst_n asserted, 1 = rst_n request will be ignored while generating pulse out
) (
input clk,
input rst_n,
input signal_in,
output pulse_out
);
localparam IDLE = 0, ARM = 1, CAPT = 2;
localparam SIGNAL_ASSERT = EDGE_TYPE ? 1'b1 : 1'b0;
localparam SIGNAL_DEASSERT = EDGE_TYPE ? 1'b0 : 1'b1;
reg [1:0] state, next_state;
reg pulse_detect;
wire busy_pulsing;
assign busy_pulsing = (IGNORE_RST_WHILE_BUSY)? pulse_out : 1'b0;
assign reset_qual_n = rst_n | busy_pulsing;
generate
if (PULSE_EXT > 1) begin: pulse_extend
integer i;
reg [PULSE_EXT-1:0] extend_pulse;
always @(posedge clk or negedge reset_qual_n) begin
if (!reset_qual_n)
extend_pulse <= {{PULSE_EXT}{1'b0}};
else begin
for (i = 1; i < PULSE_EXT; i = i+1) begin
extend_pulse[i] <= extend_pulse[i-1];
end
extend_pulse[0] <= pulse_detect;
end
end
assign pulse_out = |extend_pulse;
end
else begin: single_pulse
reg pulse_reg;
always @(posedge clk or negedge reset_qual_n) begin
if (!reset_qual_n)
pulse_reg <= 1'b0;
else
pulse_reg <= pulse_detect;
end
assign pulse_out = pulse_reg;
end
endgenerate
always @(posedge clk) begin
if (!rst_n)
state <= IDLE;
else
state <= next_state;
end
// edge detect
always @(*) begin
next_state = state;
pulse_detect = 1'b0;
case (state)
IDLE : begin
pulse_detect = 1'b0;
if (signal_in == SIGNAL_DEASSERT) next_state = ARM;
else next_state = IDLE;
end
ARM : begin
pulse_detect = 1'b0;
if (signal_in == SIGNAL_ASSERT) next_state = CAPT;
else next_state = ARM;
end
CAPT : begin
pulse_detect = 1'b1;
if (signal_in == SIGNAL_DEASSERT) next_state = ARM;
else next_state = IDLE;
end
default : begin
pulse_detect = 1'b0;
next_state = IDLE;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast , unroll-loops , no-stack-protector ) using namespace std; int32_t main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long test = 1; while (test--) { long long x, y; cin >> x >> y; long long n; cin >> n; long long hash[7]; hash[0] = 0; hash[1] = x; hash[2] = y; hash[3] = (y - x + 1000000007) % 1000000007; hash[4] = (-1 * x + 1000000007) % 1000000007; hash[5] = (-1 * y + 1000000007) % 1000000007; hash[6] = (x - y + 1000000007) % 1000000007; long long rem = (n) % 6; if (rem == 0) rem = 6; long long ans = hash[rem]; cout << (ans + 1000000007) % 1000000007; } cerr << endl << Time: << (clock() * 1000. / CLOCKS_PER_SEC) << ms << endl; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRDLSTP_FUNCTIONAL_V
`define SKY130_FD_SC_LP__SRDLSTP_FUNCTIONAL_V
/**
* srdlstp: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_psa_pp_pkg_s/sky130_fd_sc_lp__udp_dlatch_psa_pp_pkg_s.v"
`celldefine
module sky130_fd_sc_lp__srdlstp (
Q ,
SET_B ,
D ,
GATE ,
SLEEP_B
);
// Module ports
output Q ;
input SET_B ;
input D ;
input GATE ;
input SLEEP_B;
// Local signals
wire buf_Q;
wire kapwr;
wire vgnd ;
wire vpwr ;
// Delay Name Output Other arguments
sky130_fd_sc_lp__udp_dlatch$PSa_pp$PKG$s `UNIT_DELAY dlatch0 (buf_Q , D, GATE, SET_B, SLEEP_B, kapwr, vgnd, vpwr);
bufif1 bufif10 (Q , buf_Q, vpwr );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRDLSTP_FUNCTIONAL_V |
// ********************************************************************/
// Actel Corporation Proprietary and Confidential
// Copyright 2009 Actel Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
// Description: AMBA BFMs
// APB Master Wrapper
//
// Revision Information:
// Date Description
// 01Sep07 Initial Release
// 14Sep07 Updated for 1.2 functionality
// 25Sep07 Updated for 1.3 functionality
// 09Nov07 Updated for 1.4 functionality
//
//
// SVN Revision Information:
// SVN $Revision: 21608 $
// SVN $Date: 2013-12-02 16:03:36 -0800 (Mon, 02 Dec 2013) $
//
//
// Resolved SARs
// SAR Date Who Description
//
//
// Notes:
//
// *********************************************************************/
`timescale 1 ns / 100 ps
module BFM_APB (SYSCLK, SYSRSTN, PCLK, PRESETN, PADDR, PENABLE, PWRITE, PWDATA, PRDATA, PREADY, PSLVERR, PSEL, INTERRUPT, GP_OUT, GP_IN, EXT_WR, EXT_RD, EXT_ADDR, EXT_DATA, EXT_WAIT, CON_ADDR, CON_DATA, CON_RD, CON_WR, CON_BUSY, FINISHED, FAILED);
parameter OPMODE = 0;
parameter VECTFILE = "test.vec";
parameter MAX_INSTRUCTIONS = 16384;
parameter MAX_STACK = 1024;
parameter MAX_MEMTEST = 65536;
parameter TPD = 1;
parameter DEBUGLEVEL = -1;
parameter CON_SPULSE = 0;
parameter ARGVALUE0 = 0;
parameter ARGVALUE1 = 0;
parameter ARGVALUE2 = 0;
parameter ARGVALUE3 = 0;
parameter ARGVALUE4 = 0;
parameter ARGVALUE5 = 0;
parameter ARGVALUE6 = 0;
parameter ARGVALUE7 = 0;
parameter ARGVALUE8 = 0;
parameter ARGVALUE9 = 0;
parameter ARGVALUE10 = 0;
parameter ARGVALUE11 = 0;
parameter ARGVALUE12 = 0;
parameter ARGVALUE13 = 0;
parameter ARGVALUE14 = 0;
parameter ARGVALUE15 = 0;
parameter ARGVALUE16 = 0;
parameter ARGVALUE17 = 0;
parameter ARGVALUE18 = 0;
parameter ARGVALUE19 = 0;
parameter ARGVALUE20 = 0;
parameter ARGVALUE21 = 0;
parameter ARGVALUE22 = 0;
parameter ARGVALUE23 = 0;
parameter ARGVALUE24 = 0;
parameter ARGVALUE25 = 0;
parameter ARGVALUE26 = 0;
parameter ARGVALUE27 = 0;
parameter ARGVALUE28 = 0;
parameter ARGVALUE29 = 0;
parameter ARGVALUE30 = 0;
parameter ARGVALUE31 = 0;
parameter ARGVALUE32 = 0;
parameter ARGVALUE33 = 0;
parameter ARGVALUE34 = 0;
parameter ARGVALUE35 = 0;
parameter ARGVALUE36 = 0;
parameter ARGVALUE37 = 0;
parameter ARGVALUE38 = 0;
parameter ARGVALUE39 = 0;
parameter ARGVALUE40 = 0;
parameter ARGVALUE41 = 0;
parameter ARGVALUE42 = 0;
parameter ARGVALUE43 = 0;
parameter ARGVALUE44 = 0;
parameter ARGVALUE45 = 0;
parameter ARGVALUE46 = 0;
parameter ARGVALUE47 = 0;
parameter ARGVALUE48 = 0;
parameter ARGVALUE49 = 0;
parameter ARGVALUE50 = 0;
parameter ARGVALUE51 = 0;
parameter ARGVALUE52 = 0;
parameter ARGVALUE53 = 0;
parameter ARGVALUE54 = 0;
parameter ARGVALUE55 = 0;
parameter ARGVALUE56 = 0;
parameter ARGVALUE57 = 0;
parameter ARGVALUE58 = 0;
parameter ARGVALUE59 = 0;
parameter ARGVALUE60 = 0;
parameter ARGVALUE61 = 0;
parameter ARGVALUE62 = 0;
parameter ARGVALUE63 = 0;
parameter ARGVALUE64 = 0;
parameter ARGVALUE65 = 0;
parameter ARGVALUE66 = 0;
parameter ARGVALUE67 = 0;
parameter ARGVALUE68 = 0;
parameter ARGVALUE69 = 0;
parameter ARGVALUE70 = 0;
parameter ARGVALUE71 = 0;
parameter ARGVALUE72 = 0;
parameter ARGVALUE73 = 0;
parameter ARGVALUE74 = 0;
parameter ARGVALUE75 = 0;
parameter ARGVALUE76 = 0;
parameter ARGVALUE77 = 0;
parameter ARGVALUE78 = 0;
parameter ARGVALUE79 = 0;
parameter ARGVALUE80 = 0;
parameter ARGVALUE81 = 0;
parameter ARGVALUE82 = 0;
parameter ARGVALUE83 = 0;
parameter ARGVALUE84 = 0;
parameter ARGVALUE85 = 0;
parameter ARGVALUE86 = 0;
parameter ARGVALUE87 = 0;
parameter ARGVALUE88 = 0;
parameter ARGVALUE89 = 0;
parameter ARGVALUE90 = 0;
parameter ARGVALUE91 = 0;
parameter ARGVALUE92 = 0;
parameter ARGVALUE93 = 0;
parameter ARGVALUE94 = 0;
parameter ARGVALUE95 = 0;
parameter ARGVALUE96 = 0;
parameter ARGVALUE97 = 0;
parameter ARGVALUE98 = 0;
parameter ARGVALUE99 = 0;
input SYSCLK;
input SYSRSTN;
output PCLK;
wire PCLK;
output PRESETN;
wire PRESETN;
output[31:0] PADDR;
wire[31:0] PADDR;
output PENABLE;
wire PENABLE;
output PWRITE;
wire PWRITE;
output[31:0] PWDATA;
wire[31:0] PWDATA;
input[31:0] PRDATA;
input PREADY;
input PSLVERR;
output[15:0] PSEL;
wire[15:0] PSEL;
input[255:0] INTERRUPT;
output[31:0] GP_OUT;
wire[31:0] GP_OUT;
input[31:0] GP_IN;
output EXT_WR;
wire EXT_WR;
output EXT_RD;
wire EXT_RD;
output[31:0] EXT_ADDR;
wire[31:0] EXT_ADDR;
inout[31:0] EXT_DATA;
wire[31:0] EXT_DATA;
input EXT_WAIT;
input[15:0] CON_ADDR;
inout[31:0] CON_DATA;
wire[31:0] CON_DATA;
input CON_RD;
input CON_WR;
output CON_BUSY;
wire CON_BUSY;
output FINISHED;
wire FINISHED;
output FAILED;
wire FAILED;
wire iPCLk;
wire iHCLk;
wire iHRESETN;
wire[31:0] iHADDR;
wire[2:0] iHBURST;
wire iHMASTLOCK;
wire[3:0] iHPROT;
wire[2:0] iHSIZE;
wire[1:0] iHTRANS;
wire iHWRITE;
wire[31:0] iHRDATA;
wire[31:0] iHWDATA;
wire iHREADY;
wire iHREADYIN;
wire iHREADYOUT;
wire iHRESP;
wire[15:0] iHSEL;
wire[31:0] INSTR_IN = {32{1'b0}};
BFM_MAIN #( OPMODE, VECTFILE, MAX_INSTRUCTIONS, MAX_STACK, MAX_MEMTEST, TPD, DEBUGLEVEL, CON_SPULSE,
ARGVALUE0, ARGVALUE1, ARGVALUE2, ARGVALUE3, ARGVALUE4, ARGVALUE5, ARGVALUE6, ARGVALUE7, ARGVALUE8, ARGVALUE9,
ARGVALUE10, ARGVALUE11, ARGVALUE12, ARGVALUE13, ARGVALUE14, ARGVALUE15, ARGVALUE16, ARGVALUE17, ARGVALUE18, ARGVALUE19,
ARGVALUE20, ARGVALUE21, ARGVALUE22, ARGVALUE23, ARGVALUE24, ARGVALUE25, ARGVALUE26, ARGVALUE27, ARGVALUE28, ARGVALUE29,
ARGVALUE30, ARGVALUE31, ARGVALUE32, ARGVALUE33, ARGVALUE34, ARGVALUE35, ARGVALUE36, ARGVALUE37, ARGVALUE38, ARGVALUE39,
ARGVALUE40, ARGVALUE41, ARGVALUE42, ARGVALUE43, ARGVALUE44, ARGVALUE45, ARGVALUE46, ARGVALUE47, ARGVALUE48, ARGVALUE49,
ARGVALUE50, ARGVALUE51, ARGVALUE52, ARGVALUE53, ARGVALUE54, ARGVALUE55, ARGVALUE56, ARGVALUE57, ARGVALUE58, ARGVALUE59,
ARGVALUE60, ARGVALUE61, ARGVALUE62, ARGVALUE63, ARGVALUE64, ARGVALUE65, ARGVALUE66, ARGVALUE67, ARGVALUE68, ARGVALUE69,
ARGVALUE70, ARGVALUE71, ARGVALUE72, ARGVALUE73, ARGVALUE74, ARGVALUE75, ARGVALUE76, ARGVALUE77, ARGVALUE78, ARGVALUE79,
ARGVALUE80, ARGVALUE81, ARGVALUE82, ARGVALUE83, ARGVALUE84, ARGVALUE85, ARGVALUE86, ARGVALUE87, ARGVALUE88, ARGVALUE89,
ARGVALUE90, ARGVALUE91, ARGVALUE92, ARGVALUE93, ARGVALUE94, ARGVALUE95, ARGVALUE96, ARGVALUE97, ARGVALUE98, ARGVALUE99
) UBFM(
.SYSCLK(SYSCLK),
.SYSRSTN(SYSRSTN),
.HADDR(iHADDR),
.HCLK(iHCLk),
.PCLK(iPCLk),
.HRESETN(iHRESETN),
.HBURST(iHBURST),
.HMASTLOCK(iHMASTLOCK),
.HPROT(iHPROT),
.HSIZE(iHSIZE),
.HTRANS(iHTRANS),
.HWRITE(iHWRITE),
.HWDATA(iHWDATA),
.HRDATA(iHRDATA),
.HREADY(iHREADY),
.HRESP(iHRESP),
.HSEL(iHSEL),
.INTERRUPT(INTERRUPT),
.GP_OUT(GP_OUT),
.GP_IN(GP_IN),
.EXT_WR(EXT_WR),
.EXT_RD(EXT_RD),
.EXT_ADDR(EXT_ADDR),
.EXT_DATA(EXT_DATA),
.EXT_WAIT(EXT_WAIT),
.CON_ADDR(CON_ADDR),
.CON_DATA(CON_DATA),
.CON_RD(CON_RD),
.CON_WR(CON_WR),
.CON_BUSY(CON_BUSY),
.INSTR_OUT(),
.INSTR_IN(INSTR_IN),
.FINISHED(FINISHED),
.FAILED(FAILED)
);
assign PCLK = iPCLk ;
assign PRESETN = iHRESETN ;
BFM_AHB2APB #(TPD) UBRIDGE(
.HCLK(iHCLk),
.HRESETN(iHRESETN),
.HSEL(1'b1),
.HWRITE(iHWRITE),
.HADDR(iHADDR),
.HWDATA(iHWDATA),
.HRDATA(iHRDATA),
.HREADYIN(iHREADY),
.HREADYOUT(iHREADY),
.HTRANS(iHTRANS),
.HSIZE(iHSIZE),
.HBURST(iHBURST),
.HMASTLOCK(iHMASTLOCK),
.HPROT(iHPROT),
.HRESP(iHRESP),
.PSEL(PSEL),
.PADDR(PADDR),
.PWRITE(PWRITE),
.PENABLE(PENABLE),
.PWDATA(PWDATA),
.PRDATA(PRDATA),
.PREADY(PREADY),
.PSLVERR(PSLVERR)
);
endmodule
|
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01:22:53 06/15/2015
// Design Name:
// Module Name: scratch_register
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module scandoubler_ctrl (
input wire clk,
input wire [15:0] a,
input wire kbd_change_video_output,
input wire iorq_n,
input wire wr_n,
input wire [7:0] zxuno_addr,
input wire zxuno_regrd,
input wire zxuno_regwr,
input wire [7:0] din,
output reg [7:0] dout,
output wire oe_n,
output wire vga_enable,
output wire scanlines_enable,
output wire [2:0] freq_option,
output wire [1:0] turbo_enable,
output wire csync_option
);
parameter SCANDBLCTRL = 8'h0B;
parameter PRISMSPEEDCTRL = 16'h8e3b; // PRISM speed control: bits D0-D3. We use TURBO=1 if D0-D3>0
assign oe_n = ~(zxuno_addr == SCANDBLCTRL && zxuno_regrd == 1'b1);
assign vga_enable = scandblctrl[0];
assign scanlines_enable = scandblctrl[1];
assign freq_option = scandblctrl[4:2];
assign turbo_enable = scandblctrl[7:6];
assign csync_option = scandblctrl[5];
reg [7:0] scandblctrl = 8'h00; // initial value
reg [1:0] kbd_change_video_edge_detect = 2'b00;
always @(posedge clk) begin
kbd_change_video_edge_detect <= {kbd_change_video_edge_detect[0], kbd_change_video_output};
if (zxuno_addr == SCANDBLCTRL && zxuno_regwr == 1'b1)
scandblctrl <= din;
else if (iorq_n == 1'b0 && wr_n == 1'b0 && a == PRISMSPEEDCTRL)
scandblctrl <= {din[1:0], scandblctrl[5:0]};
else if (kbd_change_video_edge_detect == 2'b01) begin
scandblctrl <= {scandblctrl[7:5], ((scandblctrl[0] == 1'b0)? 3'b111 : 3'b000), scandblctrl[1], ~scandblctrl[0]};
end
dout <= scandblctrl;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m; int price[101], fruit[101]; int main() { cin >> n >> m; for (int i = 0; i < n; i++) cin >> price[i]; map<string, int> fruits; for (int i = 0; i < m; i++) { char x[101]; cin >> x; if (fruits.find(x) != fruits.end()) fruits.find(x)->second++; else fruits.insert(make_pair(x, 1)); } m = 0; for (auto i = fruits.begin(); i != fruits.end(); i++) fruit[m++] = i->second; sort(price, price + n); sort(fruit, fruit + m); int s = 0; for (int i = 0; i < m; i++) s += (price[i] * fruit[m - i - 1]); cout << s << ; s = 0; for (int i = 0; i < m; i++) s += (price[n - i - 1] * fruit[m - i - 1]); cout << s; return 0; } |
#include <bits/stdc++.h> using namespace std; int read() { int res = 0, f = 1; char c = getchar(); while (!isdigit(c) && c != - ) c = getchar(); if (c == - ) f = -1, c = getchar(); while (isdigit(c)) res = (res << 3) + (res << 1) + (c ^ 48), c = getchar(); return res * f; } const int maxn = 2e5 + 10; int n, k, val[26]; char s[maxn]; int main() { int T = read(); while (T--) { n = read(); k = read(); int ans = 0; scanf( %s , s + 1); for (int i = 1; i <= k / 2; i++) { memset(val, 0, sizeof(val)); for (int j = 0; j < n / k; j++) { val[s[i + j * k] - a ]++; val[s[k - i + 1 + j * k] - a ]++; } int tmp = 0; for (int j = 0; j < 26; j++) tmp = max(tmp, val[j]); ans += n / k * 2 - tmp; } if (k & 1) { memset(val, 0, sizeof(val)); for (int j = 0; j < n / k; j++) { val[s[k / 2 + 1 + j * k] - a ]++; } int tmp = 0; for (int j = 0; j < 26; j++) tmp = max(tmp, val[j]); ans += n / k - tmp; } printf( %d n , ans); } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, ds[3001], sz[3001], ot[3001], a, b, c, no, ans, sum; vector<pair<int, pair<int, int> > > v; int get(int x) { if (ds[x] == x) return x; else return ds[x] = get(ds[x]); } void merge(int x, int y) { sz[x] += sz[y]; ds[y] = x; ot[x] += ot[y]; if (sz[x] > sum - ot[x]) no = 1; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n; for (int i = 0; i < n - 1; ++i) { cin >> a >> b >> c; v.push_back(make_pair(c, make_pair(a, b))); } sort(v.begin(), v.end()); for (int i = 1; i <= n; ++i) { cin >> ot[i]; sz[i] = 1; ds[i] = i; sum += ot[i]; } for (int i = 1; i <= n; ++i) if (sz[i] > sum - ot[i]) no = 1; if (!no && n > 1) ans = v[0].first; for (int i = 0; i < v.size();) { int j = i; while (j < v.size() && v[i].first == v[j].first) { merge(get(v[j].second.first), get(v[j].second.second)); ++j; } i = j; if (!no && i < v.size()) ans = v[i].first; } cout << ans << n ; } |
#include <bits/stdc++.h> int main(void) { int n; std::cin >> n; std::vector<std::string> a(n); for (int i = 0; i < n; ++i) { std::cin >> a[i]; } std::set<std::string> used; for (int i = n - 1; i >= 0; --i) { if (used.find(a[i]) == used.end()) { used.insert(a[i]); std::cout << a[i] << std::endl; } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_PP_SYMBOL_V
`define SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_PP_SYMBOL_V
/**
* lpflow_decapkapwr: Decoupling capacitance filler on keep-alive
* rail.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_decapkapwr (
//# {{power|Power}}
input KAPWR,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_PP_SYMBOL_V
|
//======================================================================
//
// sha256_axi4.v
// -------------
// Top level wrapper for the SHA-256 hash function providing
// an AXI4 Slave interface.
//
//
// Author: Sanjay A Menon
// Copyright (c) 2020.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module sha256_axi4 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 8
)
(
// Users to add ports here
// User ports ends
output wire hash_complete,
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
// Instantiation of Axi Bus Interface S00_AXI
sha256_axi4_slave # (
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) sha256_axi4_slave_inst (
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
//.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready)
);
// Add user logic here
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam ADDR_NAME0 = 8'h00;
localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02;
localparam ADDR_CTRL = 8'h08;
localparam CTRL_INIT_BIT = 0;
localparam CTRL_NEXT_BIT = 1;
localparam CTRL_MODE_BIT = 2;
localparam ADDR_STATUS = 8'h09;
localparam STATUS_READY_BIT = 0;
localparam STATUS_VALID_BIT = 1;
localparam ADDR_BLOCK0 = 8'h10;
localparam ADDR_BLOCK15 = 8'h1f;
localparam ADDR_DIGEST0 = 8'h20;
localparam ADDR_DIGEST7 = 8'h27;
localparam CORE_NAME0 = 32'h73686132; // "sha2"
localparam CORE_NAME1 = 32'h2d323536; // "-256"
localparam CORE_VERSION = 32'h312e3830; // "1.80"
localparam MODE_SHA_224 = 1'h0;
localparam MODE_SHA_256 = 1'h1;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg init_reg;
reg init_new;
reg next_reg;
reg next_new;
reg mode_reg;
reg mode_new;
reg mode_we;
reg ready_reg;
reg [31 : 0] block_reg [0 : 15];
reg block_we;
reg [255 : 0] digest_reg;
reg digest_valid_reg;
reg hash_complete_reg;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
wire core_ready;
wire [511 : 0] core_block;
wire [255 : 0] core_digest;
wire core_digest_valid;
reg [31 : 0] tmp_read_data;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign core_block = {block_reg[00], block_reg[01], block_reg[02], block_reg[03],
block_reg[04], block_reg[05], block_reg[06], block_reg[07],
block_reg[08], block_reg[09], block_reg[10], block_reg[11],
block_reg[12], block_reg[13], block_reg[14], block_reg[15]};
assign s00_axi_rdata = tmp_read_data;
assign hash_complete = hash_complete_reg;
//----------------------------------------------------------------
// core instantiation.
//----------------------------------------------------------------
sha256_core core(
.clk(s00_axi_aclk),
.reset_n(s00_axi_aresetn),
.init(init_reg),
.next(next_reg),
.mode(mode_reg),
.block(core_block),
.ready(core_ready),
.digest(core_digest),
.digest_valid(core_digest_valid)
);
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge s00_axi_aclk or negedge s00_axi_aresetn)
begin : reg_update
integer i;
if (!s00_axi_aresetn)
begin
for (i = 0 ; i < 16 ; i = i + 1)
block_reg[i] <= 32'h0;
init_reg <= 1'h0;
next_reg <= 1'h0;
ready_reg <= 1'h0;
mode_reg <= MODE_SHA_256;
digest_reg <= 256'h0;
hash_complete_reg <= 1'h0;
digest_valid_reg <= 1'h0;
end
else
begin
ready_reg <= core_ready;
digest_valid_reg <= core_digest_valid;
init_reg <= init_new;
next_reg <= next_new;
if (mode_we)
mode_reg <= mode_new;
if (core_digest_valid)
begin
digest_reg <= core_digest;
hash_complete_reg <= 1'h1;
end
if (block_we)
begin
hash_complete_reg <= 1'h0;
block_reg[s00_axi_awaddr[3 : 0]] <= s00_axi_wdata;
end
end
end // reg_update
//----------------------------------------------------------------
// api_logic
//
// Implementation of the api logic. If s00_axi_awprot is enabled will either
// try to write to or read from the internal registers.
//----------------------------------------------------------------
always @*
begin : api_logic
init_new = 0;
next_new = 0;
mode_new = 0;
mode_we = 0;
block_we = 0;
tmp_read_data = 32'h0;
if (s00_axi_awprot)
begin
if (s00_axi_awvalid)
begin
if (s00_axi_awaddr == ADDR_CTRL)
begin
init_new = s00_axi_wdata[CTRL_INIT_BIT];
next_new = s00_axi_wdata[CTRL_NEXT_BIT];
mode_new = s00_axi_wdata[CTRL_MODE_BIT];
mode_we = 1;
end
if ((s00_axi_awaddr >= ADDR_BLOCK0) && (s00_axi_awaddr <= ADDR_BLOCK15))
begin
block_we = 1;
end
end // if (s00_axi_awvalid)
else
begin
if ((s00_axi_araddr >= ADDR_BLOCK0) && (s00_axi_araddr <= ADDR_BLOCK15))
tmp_read_data = block_reg[s00_axi_awaddr[3 : 0]];
if ((s00_axi_araddr >= ADDR_DIGEST0) && (s00_axi_araddr <= ADDR_DIGEST7))
begin
tmp_read_data = digest_reg[(7 - (s00_axi_araddr - ADDR_DIGEST0)) * 32 +: 32] ;
end
case (s00_axi_araddr)
// Read operations.
ADDR_NAME0:
tmp_read_data = CORE_NAME0;
ADDR_NAME1:
tmp_read_data = CORE_NAME1;
ADDR_VERSION:
tmp_read_data = CORE_VERSION;
ADDR_CTRL:
tmp_read_data = {29'h0, mode_reg, next_reg, init_reg};
ADDR_STATUS:
tmp_read_data = {30'h0, digest_valid_reg, ready_reg};
default:
begin
end
endcase // case (s00_axi_awaddr)
end
end
end // addr_decoder
endmodule // sha256_axi4
//======================================================================
// EOF sha256_axi4.v
//======================================================================
|
#include <bits/stdc++.h> using namespace std; bool has[200009]; int left[200009]; int main() { int Q; cin >> Q; for (int q = 0; q < Q; q++) { int N; cin >> N; vector<int> v; for (int i = 0; i < N; i++) { int a; cin >> a; v.push_back(a); } sort(v.begin(), v.end()); reverse(v.begin(), v.end()); int res = v[0]; vector<int> w; vector<int> t; for (int i = 1; i < v.size(); i++) if (v[i] != v[i - 1]) { if (v[0] % v[i] != 0) w.push_back(v[i]); else t.push_back(v[i]); } if (w.size() > 0) { res += w[0]; for (int i = 1; i < w.size(); i++) if (w[0] % w[i] != 0) { res += w[i]; break; } } if (t.size() >= 3 && t[0] + t[1] + t[2] > res) { if (t[0] % t[1] != 0 && t[1] % t[2] != 0 && t[0] % t[2] != 0) res = t[0] + t[1] + t[2]; } if (t.size() >= 4 && t[0] + t[1] + t[3] > res) { if (t[0] % t[1] != 0 && t[1] % t[3] != 0 && t[0] % t[3] != 0) res = t[0] + t[1] + t[3]; } cout << res << n ; } return 0; } |
// DESCRIPTION: Verilator: Verilog Test module for Issue#1631
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2019 by Julien Margetts.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
clk
);
input clk;
localparam N = 4;
wire [7:0] cval1[0:N-1];
wire [7:0] cval2[N-1:0];
wire [7:0] cval3[0:N-1];
wire [7:0] cval4[N-1:0];
wire [3:0] inc;
assign inc = 4'b0001;
// verilator lint_off LITENDIAN
COUNTER UCOUNTER1[N-1:0]
(
.clk (clk),
.inc (inc),
.o (cval1) // Twisted
);
COUNTER UCOUNTER2[N-1:0]
(
.clk (clk),
.inc (inc),
.o (cval2) // Matches
);
COUNTER UCOUNTER3[0:N-1]
(
.clk (clk),
.inc (inc),
.o (cval3) // Matches
);
COUNTER UCOUNTER4[0:N-1]
(
.clk (clk),
.inc (inc),
.o (cval4) // Twisted
);
always @(posedge clk) begin
if ((cval1[3] != cval2[0]) || (cval3[3] != cval4[0]))
$stop;
if ((cval1[0] + cval1[1] + cval1[2] + cval2[1] + cval2[2] + cval2[3] +
cval3[0] + cval3[1] + cval3[2] + cval4[1] + cval4[2] + cval4[3]) != 0)
$stop;
`ifdef TEST_VERBOSE
$display("%d %d %d %d", cval1[0], cval1[1], cval1[2], cval1[3]);
$display("%d %d %d %d", cval2[0], cval2[1], cval2[2], cval2[3]);
$display("%d %d %d %d", cval3[0], cval3[1], cval3[2], cval3[3]);
$display("%d %d %d %d", cval4[0], cval4[1], cval4[2], cval4[3]);
`endif
if (cval1[0] + cval1[3] > 3) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module COUNTER
(
input clk,
input inc,
output reg [7:0] o
);
initial o = 8'd0; // No reset input
always @(posedge clk) if (inc) o <= o + 1;
endmodule
|
// $Revision: #70 $$Date: 2002/10/19 $$Author: wsnyder $ -*- Verilog -*-
//====================================================================
module CmpEng (/*AUTOARG*/
// Inputs
clk, reset_l
);
input clk;
input reset_l;
// ****************************************************************
/*AUTOREG*/
/*AUTOWIRE*/
// ********* Prefetch FSM definitions ****************************
reg [3:0] m_cac_state_r;
reg [2:0] m_cac_sel_r, m_dat_sel_r, m_cac_rw_sel_r;
reg m_wid1_r;
reg [2:0] m_wid3_r;
reg [5:2] m_wid4_r_l;
logic [4:1] logic_four;
logic [PARAM-1:0] paramed;
`define M 2
`define L 1
parameter MS = 2;
parameter LS = 1;
reg [MS:LS] m_param_r;
reg [`M:`L] m_def2_r;
always @ (posedge clk) begin
if (~reset_l) begin
m_cac_state_r <= CAC_IDLE;
m_cac_sel_r <= CSEL_PF;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
logic_four <= 4'h0;
m_def2_r <= {(1+(`M)-(`L)){1'b0}};
m_param_r <= {(1+(MS)-(LS)){1'b0}};
m_wid1_r <= 1'h0;
m_wid3_r <= 3'h0;
m_wid4_r_l <= ~4'h0;
paramed <= {PARAM{1'b0}};
// End of automatics
end
else begin
m_wid1_r <= 0;
m_wid3_r <= 0;
m_wid4_r_l <= 0;
m_param_r <= 0;
m_def2_r <= 0;
logic_four <= 4;
paramed <= 1;
end
end
endmodule
// Local Variables:
// verilog-auto-read-includes:t
// verilog-auto-sense-defines-constant: t
// verilog-auto-reset-widths: t
// verilog-active-low-regexp: "_l$"
// End:
|
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V2.1
// Ultra-Embedded.com
// Copyright 2011 - 2014
//
// Email:
//
// License: LGPL
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2014 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Module - ALU
//-----------------------------------------------------------------
module altor32_alu
(
// ALU operation select
input [3:0] op_i /*verilator public*/,
// Operands
input [31:0] a_i /*verilator public*/,
input [31:0] b_i /*verilator public*/,
input c_i /*verilator public*/,
// Result
output [31:0] p_o /*verilator public*/,
// Carry
output reg c_o /*verilator public*/,
output reg c_update_o /*verilator public*/,
// Comparison
output reg equal_o /*verilator public*/,
output reg greater_than_signed_o /*verilator public*/,
output reg greater_than_o /*verilator public*/,
output reg less_than_signed_o /*verilator public*/,
output reg less_than_o /*verilator public*/,
output flag_update_o /*verilator public*/
);
//-----------------------------------------------------------------
// Includes
//-----------------------------------------------------------------
`include "altor32_defs.v"
`include "altor32_funcs.v"
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [31:0] result_r;
reg [31:16] shift_right_fill_r;
reg [31:0] shift_right_1_r;
reg [31:0] shift_right_2_r;
reg [31:0] shift_right_4_r;
reg [31:0] shift_right_8_r;
reg [31:0] shift_left_1_r;
reg [31:0] shift_left_2_r;
reg [31:0] shift_left_4_r;
reg [31:0] shift_left_8_r;
//-----------------------------------------------------------------
// ALU
//-----------------------------------------------------------------
always @ (op_i or a_i or b_i or c_i)
begin
case (op_i)
//----------------------------------------------
// Shift Left
//----------------------------------------------
`ALU_SHIFTL :
begin
if (b_i[0] == 1'b1)
shift_left_1_r = {a_i[30:0],1'b0};
else
shift_left_1_r = a_i;
if (b_i[1] == 1'b1)
shift_left_2_r = {shift_left_1_r[29:0],2'b00};
else
shift_left_2_r = shift_left_1_r;
if (b_i[2] == 1'b1)
shift_left_4_r = {shift_left_2_r[27:0],4'b0000};
else
shift_left_4_r = shift_left_2_r;
if (b_i[3] == 1'b1)
shift_left_8_r = {shift_left_4_r[23:0],8'b00000000};
else
shift_left_8_r = shift_left_4_r;
if (b_i[4] == 1'b1)
result_r = {shift_left_8_r[15:0],16'b0000000000000000};
else
result_r = shift_left_8_r;
c_o = 1'b0;
c_update_o = 1'b0;
end
//----------------------------------------------
// Shift Right
//----------------------------------------------
`ALU_SHIFTR, `ALU_SHIRTR_ARITH:
begin
// Arithmetic shift? Fill with 1's if MSB set
if (a_i[31] == 1'b1 && op_i == `ALU_SHIRTR_ARITH)
shift_right_fill_r = 16'b1111111111111111;
else
shift_right_fill_r = 16'b0000000000000000;
if (b_i[0] == 1'b1)
shift_right_1_r = {shift_right_fill_r[31], a_i[31:1]};
else
shift_right_1_r = a_i;
if (b_i[1] == 1'b1)
shift_right_2_r = {shift_right_fill_r[31:30], shift_right_1_r[31:2]};
else
shift_right_2_r = shift_right_1_r;
if (b_i[2] == 1'b1)
shift_right_4_r = {shift_right_fill_r[31:28], shift_right_2_r[31:4]};
else
shift_right_4_r = shift_right_2_r;
if (b_i[3] == 1'b1)
shift_right_8_r = {shift_right_fill_r[31:24], shift_right_4_r[31:8]};
else
shift_right_8_r = shift_right_4_r;
if (b_i[4] == 1'b1)
result_r = {shift_right_fill_r[31:16], shift_right_8_r[31:16]};
else
result_r = shift_right_8_r;
c_o = 1'b0;
c_update_o = 1'b0;
end
//----------------------------------------------
// Arithmetic
//----------------------------------------------
`ALU_ADD :
begin
{c_o, result_r} = (a_i + b_i);
c_update_o = 1'b1;
end
`ALU_ADDC :
begin
{c_o, result_r} = (a_i + b_i) + {31'h00000000, c_i};
c_update_o = 1'b1;
end
`ALU_SUB :
begin
result_r = (a_i - b_i);
c_o = 1'b0;
c_update_o = 1'b0;
end
//----------------------------------------------
// Logical
//----------------------------------------------
`ALU_AND :
begin
result_r = (a_i & b_i);
c_o = 1'b0;
c_update_o = 1'b0;
end
`ALU_OR :
begin
result_r = (a_i | b_i);
c_o = 1'b0;
c_update_o = 1'b0;
end
`ALU_XOR :
begin
result_r = (a_i ^ b_i);
c_o = 1'b0;
c_update_o = 1'b0;
end
default :
begin
result_r = a_i;
c_o = 1'b0;
c_update_o = 1'b0;
end
endcase
end
assign p_o = result_r;
//-----------------------------------------------------------------
// Comparisons
//-----------------------------------------------------------------
always @ *
begin
if (a_i == b_i)
equal_o = 1'b1;
else
equal_o = 1'b0;
if (a_i < b_i)
less_than_o = 1'b1;
else
less_than_o = 1'b0;
if (a_i > b_i)
greater_than_o = 1'b1;
else
greater_than_o = 1'b0;
less_than_signed_o = less_than_signed(a_i, b_i);
greater_than_signed_o = ~(less_than_signed_o | equal_o);
end
assign flag_update_o = (op_i == `ALU_COMPARE);
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> inline void amin(T &a, const T &b) { if (b < a) a = b; } template <class T> inline void amax(T &a, const T &b) { if (a < b) a = b; } struct Data { int sx, sy; int le, ri, to, bo; bool operator<(const Data &y) const { return sx < y.sx; } }; int N, Q; int main() { scanf( %d%d , &N, &Q); set<Data> S; S.insert((Data){1, 1, 1, N, 1, N}); Data seek; for (int $ = 0, $_len = (Q); $ < $_len; ++$) { int col, row; char buf[8], dir; scanf( %d%d%s , &col, &row, buf); dir = buf[0]; int ans = 0; seek.sx = col; set<Data>::iterator it = S.upper_bound(seek); if (it != S.begin()) { it--; if (it->sx <= col && col <= it->ri) { Data D = *it; S.erase(it); if (dir == U ) { ans = row - D.to + 1; if (D.sx < col) S.insert((Data){D.sx, row + 1, D.le, col - 1, D.to, D.bo}); if (col < D.ri) S.insert((Data){col + 1, D.sy, col + 1, D.ri, D.to, row - 1}); } else { ans = col - D.le + 1; if (D.sy < row) S.insert((Data){col + 1, D.sy, D.le, D.ri, D.to, row - 1}); if (row < D.bo) S.insert((Data){D.sx, row + 1, D.le, col - 1, row + 1, D.bo}); } } else { ans = 0; } } else { ans = 0; } printf( %d n , ans); } return 0; } |
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 2677 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w4,
w5,
w2048,
w2047,
w640,
w2687,
w10,
w2677;
assign w1 = i_data0;
assign w10 = w5 << 1;
assign w2047 = w2048 - w1;
assign w2048 = w1 << 11;
assign w2677 = w2687 - w10;
assign w2687 = w2047 + w640;
assign w4 = w1 << 2;
assign w5 = w1 + w4;
assign w640 = w5 << 7;
assign o_data0 = w2677;
//multiplier_block area estimate = 7171.71836743236;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND3B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__AND3B_BEHAVIORAL_PP_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__and3b (
VPWR,
VGND,
X ,
A_N ,
B ,
C
);
// Module ports
input VPWR;
input VGND;
output X ;
input A_N ;
input B ;
input C ;
// Local signals
wire not0_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X , C, not0_out, B );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND3B_BEHAVIORAL_PP_V |
/*
RC4 PRGA Testbench
Copyright Groundworks Technologies 2012-2013
Author: Alfredo Ortega
This library is free software: you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation, either
version 3 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
`define RC4
`ifndef TEST_CYCLES
`define TEST_CYCLES 2000
`endif
`include "rc4.inc"
module rc4_tb;
reg [7:0] password[0:`KEY_SIZE-1];
parameter tck = 10, program_cycles = `TEST_CYCLES;
reg clk, rst; // clock, reset
wire output_ready; // output ready (valid)
wire [7:0] K; // output
reg [7:0] password_input; //input
/* Clocking device */
always #(tck/2)
clk = ~clk;
/* Password loader and info display*/
integer clkcount;
always @ (posedge clk)
begin
clkcount<=clkcount+1;
if (clkcount < `KEY_SIZE)
begin
password_input<=password[clkcount];
$display ("--- clk %d --- key[%x] = %08X",clkcount,clkcount,password[clkcount]);
end
else $display ("--- clk %d --- K %08X --- valid: ",clkcount,K,output_ready);
end
/* rc4 module implementation */
rc4 rc4mod(
.clk(clk),
.rst(rst),
.password_input(password_input),
.output_ready(output_ready),
.K(K)
);
/* Simulation */
integer q;
initial begin
password[0] = 8'h01; // Testvectors http://tools.ietf.org/html/draft-josefsson-rc4-test-vectors-02#page-4
password[1] = 8'h02; //
password[2] = 8'h03; //
password[3] = 8'h04; //
password[4] = 8'h05; //
password[5] = 8'h06; //
password[6] = 8'h07; //
// Key length: 56 bits.
// key: 0x01020304050607
// DEC 0 HEX 0: 29 3f 02 d4 7f 37 c9 b6 33 f2 af 52 85 fe b4 6b
$display ("Start...");
clk = 0;
rst = 1;
clkcount =0;
password_input=password[clkcount];
#(1*tck)
rst = 0;
#(program_cycles*tck+100000)
$display ("Finish.");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); long long int n, x, ans = 0, i; cin >> n; for (i = 0; i < n; i++) { cin >> x; ans += (i + 1) * x; } ans -= (((n - 1) * (n)) / 2); cout << ans << n ; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10; int n; int L; int R; struct data { int u; int f; int dis; int dep; }; queue<data> q1, q2; struct ed { int v; int val; int siz; int ori; friend bool operator<(ed a, ed b) { return a.siz < b.siz; } }; vector<ed> v[N]; int ng[N]; int tim; int nsiz[N]; int w[N]; int nu[N]; int siz[N]; bool cut[N]; int ans1; int ans2; struct dq { int q[3 * N]; int hd; int tl; inline void clr() { hd = 1; tl = 0; } inline bool emp() { return hd <= tl; } inline void ins(int j) { while (hd <= tl && w[j] >= w[q[tl]]) tl--; q[++tl] = j; } inline void del(int k) { while (hd <= tl && q[hd] > k) hd++; } inline int qmx() { return q[hd]; } } q; inline void clear(queue<data>& q) { queue<data> emp; swap(q, emp); } inline int dfs1(int u, int f) { siz[u] = 1; for (vector<ed>::iterator it = v[u].begin(); it != v[u].end(); ++it) if (it->v != f && !cut[it->v]) siz[u] += dfs1(it->v, u); return siz[u]; } inline int find(int u, int f, const int& tot) { for (vector<ed>::iterator it = v[u].begin(); it != v[u].end(); ++it) if (it->v != f && !cut[it->v] && 2 * siz[it->v] >= tot) return find(it->v, u, tot); return u; } inline int dfs3(int u, int f) { int mx = 0; for (vector<ed>::iterator it = v[u].begin(); it != v[u].end(); ++it) if (it->v != f && !cut[it->v]) mx = max(mx, dfs3(it->v, u)); return mx + 1; } inline bool bfs(data st, int mxsiz) { q.clr(); clear(q1); clear(q2); int j = min(R, mxsiz); for (; j >= L; j--) q.ins(j); for (q1.push(st); !q1.empty();) { data nw = q1.front(); q2.push(nw); q1.pop(); if (nw.dep > R) continue; int dl = max(L - nw.dep, 0); int dr = min(R - nw.dep, mxsiz); for (; j >= dl; j--) q.ins(j); q.del(dr); if (q.emp()) { int p = q.qmx(); if (nw.dis + w[p] >= 0) { ans1 = nu[p]; ans2 = nw.u; return true; } } for (vector<ed>::iterator it = v[nw.u].begin(); it != v[nw.u].end(); ++it) if (it->v != nw.f && !cut[it->v]) q1.push((data){it->v, nw.u, nw.dis + it->val, nw.dep + 1}); } for (; !q2.empty(); q2.pop()) { data a = q2.front(); if (w[a.dep] < a.dis) w[a.dep] = a.dis, nu[a.dep] = a.u; } return false; } inline bool solve(int u) { ++tim; int g; if (ng[tim] == -1) { dfs1(u, 0); g = find(u, 0, siz[u]); cut[g] = true; ng[tim] = g; nsiz[tim] = siz[u]; if (siz[u] == 1) return false; for (int i = 1; i <= siz[u]; i++) w[i] = -0x3f3f3f3f, nu[i] = 0; for (vector<ed>::iterator it = v[g].begin(); it != v[g].end(); ++it) if (!cut[it->v]) it->siz = dfs3(it->v, g); sort(v[g].begin(), v[g].end()); w[0] = 0; nu[0] = g; } else { g = ng[tim]; cut[g] = true; if (nsiz[tim] == 1) return false; for (int i = 1; i <= nsiz[tim]; i++) w[i] = -0x3f3f3f3f, nu[i] = 0; w[0] = 0; nu[0] = g; } for (vector<ed>::iterator it = v[g].begin(); it != v[g].end(); ++it) if (!cut[it->v]) if (bfs((data){it->v, g, it->val, 1}, it->siz)) return true; for (vector<ed>::iterator it = v[g].begin(); it != v[g].end(); ++it) if (!cut[it->v]) if (solve(it->v)) return true; return false; } inline bool jud(int mid) { tim = 0; for (int i = 1; i <= n; i++) for (vector<ed>::iterator it = v[i].begin(); it != v[i].end(); ++it) it->val = (it->ori >= mid) ? 1 : -1; for (int i = 1; i <= n; i++) cut[i] = false; return solve(1); } int main() { scanf( %d%d%d , &n, &L, &R); int l = 0; int r = 0; for (int i = 1; i <= n; i++) ng[i] = -1; for (int i = 1, u, V, va; i < n; i++) { scanf( %d%d%d , &u, &V, &va); r = max(r, va); v[u].push_back((ed){V, 0, 0, va}); v[V].push_back((ed){u, 0, 0, va}); } while (l != r) { int mid = (l + r + 1) / 2; if (jud(mid)) l = mid; else r = mid - 1; } jud(l); printf( %d %d , ans1, ans2); return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 2147483647; const double PI = 3.141592653589793; int n, k, l, a[105], used[105], suma, i, j, q, b; double maxx, minn; vector<int> wek; int main() { scanf( %d %d , &n, &k); l = n / k; for (i = 0; i < n; i++) { scanf( %d , &a[i]); used[i] = 0; } maxx = -INF; minn = INF; scanf( %d , &q); for (j = 0; j < q; j++) { suma = 0; for (i = 0; i < l; i++) { scanf( %d , &b); b--; suma += a[b]; used[b] = 1; } maxx = max(maxx, suma * 1.0 / l); minn = min(minn, suma * 1.0 / l); } wek.resize(0); for (i = 0; i < n; i++) if (!used[i]) wek.push_back(a[i]); sort(wek.begin(), wek.end()); if (wek.size() == n - k * l) { printf( %.8lf %.8lf n , minn, maxx); return 0; } suma = 0; for (i = 0; i < l; i++) suma += wek[i]; maxx = max(maxx, suma * 1.0 / l); minn = min(minn, suma * 1.0 / l); suma = 0; for (i = wek.size() - 1; i >= (int)wek.size() - l; i--) suma += wek[i]; maxx = max(maxx, suma * 1.0 / l); minn = min(minn, suma * 1.0 / l); printf( %.8lf %.8lf n , minn, maxx); return 0; } |
#include <bits/stdc++.h> using namespace std; void __print(int x) { cout << x; } void __print(long x) { cout << x; } void __print(long long x) { cout << x; } void __print(unsigned x) { cout << x; } void __print(unsigned long x) { cout << x; } void __print(unsigned long long x) { cout << x; } void __print(float x) { cout << x; } void __print(double x) { cout << x; } void __print(long double x) { cout << x; } void __print(char x) { cout << << x << ; } void __print(const char *x) { cout << << x << ; } void __print(const string &x) { cout << << x << ; } void __print(bool x) { cout << (x ? true : false ); } void _print() { cout << ] n ; } template <typename T, typename... V> void _print(T t, V... v) { __print(t); if (sizeof...(v)) cout << , ; _print(v...); } const long long int dx4[4] = {+1, -1, 0, 0}; const long long int dy4[4] = {0, 0, +1, -1}; const long long int dx8[8] = {-1, -1, -1, 0, 0, 1, 1, 1}; const long long int dy8[8] = {-1, 0, 1, -1, 1, -1, 0, 1}; const long long int MOD = 1e9 + 7; const long long int INF = 1e10; const long long int N = 2e5 + 5; void solve() { long long int n; string s; cin >> n >> s; map<char, long long int> cnt; for (auto x : s) cnt[x]++; for (auto x : cnt) while (x.second) cout << x.first, x.second--; return; } int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long int t = 1; while (t--) solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxN = 1e4; long long F[maxN + 1]; void fact() { F[0] = F[1] = 1; for (int i = 2; i <= maxN; i++) F[i] = (1LL * F[i - 1] * i) % 998244353; } long long power(long long a, long long b) { long long res = 1; while (b) { if (b & 1) { res = (1LL * res * a) % 998244353, b--; } else { a = (1LL * a * a) % 998244353, b >>= 1; } } return res; } long long C(long long n, long long r) { if (r > n) return 0; long long res = F[n]; res = (1LL * res * power(F[r], 998244353 - 2)) % 998244353; res = (1LL * res * power(F[n - r], 998244353 - 2)) % 998244353; return res; } void solve() { long long n, k; cin >> n >> k; string second; cin >> second; if (!k) { cout << 1 n ; return; } long long ans = 1, l = 0, r = 0, cnt = 0; while (r < n) { if (second[r] == 1 ) { if (cnt == k) { (ans += (C(r - l, k) - 1 + 998244353) % 998244353) %= 998244353; while (l < n && second[l] != 1 ) l++; l++, cnt--; ans = (ans - C(r - l, k - 1) + 1 + 998244353) % 998244353; } cnt++; } r++; } if (cnt == k) (ans += (C(r - l, k) - 1 + 998244353) % 998244353) %= 998244353; cout << ans << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(0), cout.tie(0), fact(); solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long n, m, l = 0, p = 0, i, flag = 0, k, j, r = 0, q = 0, t, curr = 0, d, x; cin >> n >> x >> k; long long a[n]; for (long long i = 0; i < n; i++) { cin >> a[i]; } sort(a, a + n); for (long long i = 0; i < n; i++) { long long r1 = a[i] + (x * k); if (a[i] % x == 0) { r1--; } r1 -= r1 % x; long long r2 = r1 + x - 1; r1 = max(a[i], r1); auto it = upper_bound(a, a + n, r2); auto it1 = lower_bound(a, a + n, r1); p += it - it1; } cout << p; return 0; } |
module wb_ram
#(//Wishbone parameters
parameter dw = 32,
//Memory parameters
parameter depth = 256,
parameter aw = $clog2(depth),
parameter memfile = "")
(input wb_clk_i,
input wb_rst_i,
input [aw-1:0] wb_adr_i,
input [dw-1:0] wb_dat_i,
input [3:0] wb_sel_i,
input wb_we_i,
input [1:0] wb_bte_i,
input [2:0] wb_cti_i,
input wb_cyc_i,
input wb_stb_i,
output reg wb_ack_o,
output wb_err_o,
output [dw-1:0] wb_dat_o);
`include "wb_common.v"
reg [aw-1:0] adr_r;
wire [aw-1:0] next_adr;
wire valid = wb_cyc_i & wb_stb_i;
reg valid_r;
reg is_last_r;
always @(posedge wb_clk_i)
is_last_r <= wb_is_last(wb_cti_i);
wire new_cycle = (valid & !valid_r) | is_last_r;
assign next_adr = wb_next_adr(adr_r, wb_cti_i, wb_bte_i, dw);
wire [aw-1:0] adr = new_cycle ? wb_adr_i : next_adr;
always@(posedge wb_clk_i) begin
adr_r <= adr;
valid_r <= valid;
//Ack generation
wb_ack_o <= valid & (!((wb_cti_i == 3'b000) | (wb_cti_i == 3'b111)) | !wb_ack_o);
if(wb_rst_i) begin
adr_r <= {aw{1'b0}};
valid_r <= 1'b0;
wb_ack_o <= 1'b0;
end
end
wire ram_we = wb_we_i & valid & wb_ack_o;
//TODO:ck for burst address errors
assign wb_err_o = 1'b0;
`ifdef RTL
wb_ram_generic
#(.depth(depth/4),
.memfile (memfile))
ram0
(.clk (wb_clk_i),
.we ({4{ram_we}} & wb_sel_i),
.din (wb_dat_i),
.waddr(adr_r[aw-1:2]),
.raddr (adr[aw-1:2]),
.dout (wb_dat_o));
`else // !`ifdef RTL
`ifdef XILINX
wb_ram_xilinx ram0(
.clk (wb_clk_i),
.rst (wb_rst_i),
.we ({4{ram_we}} & wb_sel_i),
.din (wb_dat_i),
.waddr({2'b00, adr_r[aw-1:2]}),
.raddr ({2'b00, adr[aw-1:2]}),
.dout (wb_dat_o)
);
`else // !`ifdef XILINX
`ifdef ALTERA
wb_ram_32x8192 ram0(
.address(adr_r),
.byteena(),
.clock(wb_clk_i),
.data(wb_dat_i),
.wren({4{ram_we}} & wb_sel_i),
.q(wb_dat_o)
);
`endif
`endif // !`ifdef XILINX
`endif // !`ifdef RTL
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 10; int mod = 1e9 + 7; int a, b, c, d, n, m, x, y, z; vector<int> v; int arr[3]; int main() { cin >> a >> b >> c; for (int i = 0; i <= a; i++) { x = c - i; y = b - (a - i); if (x >= 0 && y >= 0 && x == y) { cout << a - i << << x << << i << endl; return 0; } } cout << Impossible << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e6; int n, k, a, b; vector<int> v; int ret(int lt, int rt) { int id2 = upper_bound(v.begin(), v.end(), rt) - v.begin(); int id1 = lower_bound(v.begin(), v.end(), lt) - v.begin(); return id2 - id1; } long long dfs(int lt, int rt) { int nm = ret(lt, rt); if (!nm) return a; long long on = b * 1LL; on *= nm; on *= (rt - lt + 1); if (lt == rt) return on; int md = (lt + rt) / 2; long long tw = dfs(lt, md) + dfs(md + 1, rt); return min(on, tw); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n >> k >> a >> b; for (int i = 1; i <= k; i++) { int x; cin >> x; v.push_back(x); } sort(v.begin(), v.end()); cout << dfs(1, 1 << n) << endl; return 0; } |
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream asynchronous frame FIFO (64 bit datapath)
*/
module axis_async_frame_fifo_64 #
(
parameter ADDR_WIDTH = 12,
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter DROP_WHEN_FULL = 0
)
(
/*
* AXI input
*/
input wire input_clk,
input wire input_rst,
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
input wire input_axis_tuser,
/*
* AXI output
*/
input wire output_clk,
input wire output_rst,
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast
);
reg [ADDR_WIDTH:0] wr_ptr = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next;
reg [ADDR_WIDTH:0] wr_ptr_cur = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_gray = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr = {ADDR_WIDTH+1{1'b0}}, rd_ptr_next;
reg [ADDR_WIDTH:0] rd_ptr_gray = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_gray_sync1 = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_gray_sync2 = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_gray_sync1 = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_gray_sync2 = {ADDR_WIDTH+1{1'b0}};
reg input_rst_sync1 = 1;
reg input_rst_sync2 = 1;
reg output_rst_sync1 = 1;
reg output_rst_sync2 = 1;
reg drop_frame = 1'b0;
reg [DATA_WIDTH+KEEP_WIDTH+2-1:0] data_out_reg = {1'b0, {KEEP_WIDTH{1'b0}}, {DATA_WIDTH{1'b0}}};
//(* RAM_STYLE="BLOCK" *)
reg [DATA_WIDTH+KEEP_WIDTH+2-1:0] mem[(2**ADDR_WIDTH)-1:0];
reg output_read = 1'b0;
reg output_axis_tvalid_reg = 1'b0;
wire [DATA_WIDTH+KEEP_WIDTH+2-1:0] data_in = {input_axis_tlast, input_axis_tkeep, input_axis_tdata};
// full when first TWO MSBs do NOT match, but rest matches
// (gray code equivalent of first MSB different but rest same)
wire full = ((wr_ptr_gray[ADDR_WIDTH] != rd_ptr_gray_sync2[ADDR_WIDTH]) &&
(wr_ptr_gray[ADDR_WIDTH-1] != rd_ptr_gray_sync2[ADDR_WIDTH-1]) &&
(wr_ptr_gray[ADDR_WIDTH-2:0] == rd_ptr_gray_sync2[ADDR_WIDTH-2:0]));
// empty when pointers match exactly
wire empty = rd_ptr_gray == wr_ptr_gray_sync2;
// overflow in single packet
wire full_cur = ((wr_ptr[ADDR_WIDTH] != wr_ptr_cur[ADDR_WIDTH]) &&
(wr_ptr[ADDR_WIDTH-1:0] == wr_ptr_cur[ADDR_WIDTH-1:0]));
wire write = input_axis_tvalid & (~full | DROP_WHEN_FULL);
wire read = (output_axis_tready | ~output_axis_tvalid_reg) & ~empty;
assign {output_axis_tlast, output_axis_tkeep, output_axis_tdata} = data_out_reg;
assign input_axis_tready = (~full | DROP_WHEN_FULL);
assign output_axis_tvalid = output_axis_tvalid_reg;
// reset synchronization
always @(posedge input_clk or posedge input_rst or posedge output_rst) begin
if (input_rst | output_rst) begin
input_rst_sync1 <= 1;
input_rst_sync2 <= 1;
end else begin
input_rst_sync1 <= 0;
input_rst_sync2 <= input_rst_sync1;
end
end
always @(posedge output_clk or posedge input_rst or posedge output_rst) begin
if (input_rst | output_rst) begin
output_rst_sync1 <= 1;
output_rst_sync2 <= 1;
end else begin
output_rst_sync1 <= 0;
output_rst_sync2 <= output_rst_sync1;
end
end
// write
always @(posedge input_clk or posedge input_rst_sync2) begin
if (input_rst_sync2) begin
wr_ptr <= 0;
wr_ptr_cur <= 0;
wr_ptr_gray <= 0;
drop_frame <= 0;
end else if (write) begin
if (full | full_cur | drop_frame) begin
// buffer full, hold current pointer, drop packet at end
drop_frame <= 1;
if (input_axis_tlast) begin
wr_ptr_cur <= wr_ptr;
drop_frame <= 0;
end
end else begin
mem[wr_ptr_cur[ADDR_WIDTH-1:0]] <= data_in;
wr_ptr_cur <= wr_ptr_cur + 1;
if (input_axis_tlast) begin
if (input_axis_tuser) begin
// bad packet, reset write pointer
wr_ptr_cur <= wr_ptr;
end else begin
// good packet, push new write pointer
wr_ptr_next = wr_ptr_cur + 1;
wr_ptr <= wr_ptr_next;
wr_ptr_gray <= wr_ptr_next ^ (wr_ptr_next >> 1);
end
end
end
end
end
// pointer synchronization
always @(posedge input_clk or posedge input_rst_sync2) begin
if (input_rst_sync2) begin
rd_ptr_gray_sync1 <= 0;
rd_ptr_gray_sync2 <= 0;
end else begin
rd_ptr_gray_sync1 <= rd_ptr_gray;
rd_ptr_gray_sync2 <= rd_ptr_gray_sync1;
end
end
// read
always @(posedge output_clk or posedge output_rst_sync2) begin
if (output_rst_sync2) begin
rd_ptr <= 0;
rd_ptr_gray <= 0;
end else if (read) begin
data_out_reg <= mem[rd_ptr[ADDR_WIDTH-1:0]];
rd_ptr_next = rd_ptr + 1;
rd_ptr <= rd_ptr_next;
rd_ptr_gray <= rd_ptr_next ^ (rd_ptr_next >> 1);
end
end
// pointer synchronization
always @(posedge output_clk or posedge output_rst_sync2) begin
if (output_rst_sync2) begin
wr_ptr_gray_sync1 <= 0;
wr_ptr_gray_sync2 <= 0;
end else begin
wr_ptr_gray_sync1 <= wr_ptr_gray;
wr_ptr_gray_sync2 <= wr_ptr_gray_sync1;
end
end
// source ready output
always @(posedge output_clk or posedge output_rst_sync2) begin
if (output_rst_sync2) begin
output_axis_tvalid_reg <= 1'b0;
end else if (output_axis_tready | ~output_axis_tvalid_reg) begin
output_axis_tvalid_reg <= ~empty;
end else begin
output_axis_tvalid_reg <= output_axis_tvalid_reg;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; bool f = 0; const double eps = 1e-8; int n; struct point { double x, y; } p[100010]; inline int rd() { int x = 0; bool f = 0; char c = getchar(); while (!isdigit(c)) { if (c == - ) f = 1; c = getchar(); } while (isdigit(c)) { x = (x << 1) + (x << 3) + (c ^ 48); c = getchar(); } return f ? -x : x; } inline bool valid(double x) { double l = -(double)1e18, r = (double)1e18, dlt; for (register int i = 1; i <= n; ++i) { if (p[i].y > x + x) return 0; dlt = sqrt(p[i].y * (2 * x - p[i].y)); l = max(l, p[i].x - dlt); r = min(r, p[i].x + dlt); } return (r - l + eps >= 0.0); } int main() { n = rd(); for (register int i = 1; i <= n; ++i) { p[i].x = (double)rd(); p[i].y = (double)rd(); if (p[i].y < 0.0) f = 1; } if (f == 1) for (register int i = 1; i <= n; ++i) { p[i].y = -p[i].y; if (p[i].y < 0.0) { puts( -1 ); return 0; } } int t = 0; register double l = 0.0, r = (double)1e18, mid; while (t <= 300) { mid = (l + r) / 2.0; ++t; valid(mid) ? r = mid : l = mid; } printf( %.10lf , l); return 0; } |
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