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#include <bits/stdc++.h> using namespace std; const long long N = 1e5 + 5; vector<long long> tim(N), pos(N), cur(N); int main() { long long T, n, act, start, des, dir, ans, startTime; cin>>T; for(long long t = 1; t <= T; ++t) { tim[0] = pos[0] = start = des = act = ans = startTime = 0; cin>>n; for(long long i = 1; i <= n; ++i) { cin>>tim[i]>>pos[i]; if(tim[i] >= act) { cur[i] = des; startTime = tim[i]; act = tim[i] + abs(des - pos[i]); start = des; des = pos[i]; } else { dir = (start <= des) ? 1 : -1; cur[i] = start + dir * (tim[i] - startTime); } } cur[n+1] = des; for(long long i = 1; i <= n; ++i) { if(min(cur[i],cur[i+1]) <= pos[i] && pos[i] <= max(cur[i],cur[i+1])) { ans += 1; } } cout<<ans<<endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; struct edge { int v, nxt; } e[2050]; int ecnt; int n, m; int totdep; int pw[2050]; map<int, int> head; map<int, bool> has_fa; map<int, int> sz; map<int, bool> vis; void adde(int u, int v) { e[++ecnt].v = v; e[ecnt].nxt = head[u]; head[u] = ecnt; } int getdep(int pos) { return pos == 0 ? 0 : getdep(pos / 2) + 1; } int getsz(int pos) { int curdep = getdep(pos); int tmp = curdep; int lc = pos, rc = pos; while (curdep < totdep) { curdep++; lc = lc << 1; rc = rc << 1 | 1; } if (n < lc) return pw[totdep - tmp - 1]; else if (n > rc) return pw[totdep - tmp]; else return pw[totdep - tmp - 1] + n - lc + 1; } int us[2050], vs[2050]; int seq[2050], scnt; long long ans; const int mod = 1000000007; void mark(int pos) { while (pos / 2) { if (has_fa[pos]) return; has_fa[pos] = 1; seq[++scnt] = pos; pos = pos / 2; } } void dfs_sz(int pos) { sz[pos] = getsz(pos); if (has_fa[pos << 1]) dfs_sz(pos << 1), sz[pos] -= getsz(pos << 1); if (has_fa[pos << 1 | 1]) dfs_sz(pos << 1 | 1), sz[pos] -= getsz(pos << 1 | 1); } int cur; void dfs_solv(int pos) { vis[pos] = 1; ans += 1ll * cur * sz[pos] % mod; ans %= mod; if (!vis[pos << 1] && has_fa[pos << 1]) dfs_solv(pos << 1); if (!vis[pos << 1 | 1] && has_fa[pos << 1 | 1]) dfs_solv(pos << 1 | 1); if (!vis[pos >> 1] && (pos >> 1)) dfs_solv(pos >> 1); for (int i = head[pos]; i; i = e[i].nxt) { int v = e[i].v; if (!vis[v]) dfs_solv(v); } vis[pos] = 0; } int main() { scanf( %d%d , &n, &m); if (m == 0) { printf( %lld n , n * 1ll * n % mod); return 0; } seq[++scnt] = 1; totdep = getdep(n); pw[0] = 1; for (int i = 1; i <= 1000; ++i) pw[i] = pw[i - 1] * 2 + 1; for (int i = 1; i <= m; ++i) { scanf( %d%d , &us[i], &vs[i]); mark(us[i]); mark(vs[i]); adde(us[i], vs[i]); adde(vs[i], us[i]); } dfs_sz(1); for (int i = 1; i <= scnt; ++i) { cur = sz[seq[i]]; dfs_solv(seq[i]); } printf( %lld n , ans); } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty.
// bug998
interface intf
#(parameter PARAM = 0)
();
logic val;
function integer func (); return 5; endfunction
endinterface
module t1(intf mod_intf);
initial begin
$display("%m %d", mod_intf.val);
end
endmodule
module t();
generate
begin : TestIf
intf #(.PARAM(1)) my_intf ();
assign my_intf.val = '0;
t1 t (.mod_intf(my_intf));
// initial $display("%0d", my_intf.func());
end
endgenerate
generate
begin
intf #(.PARAM(1)) my_intf ();
assign my_intf.val = '1;
t1 t (.mod_intf(my_intf));
// initial $display("%0d", my_intf.func());
end
endgenerate
localparam LP = 1;
logic val;
generate begin
if (LP) begin
intf #(.PARAM(2)) my_intf ();
assign my_intf.val = '1;
assign val = my_intf.val;
end else begin
intf #(.PARAM(3)) my_intf ();
assign my_intf.val = '1;
assign val = my_intf.val;
end
end endgenerate
initial begin
$display("%0d", val);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long dem[100001]; long long f[100002]; int main() { int n; long long x; cin >> n; for (int i = 0; i < n; i++) { cin >> x; dem[x]++; } f[1] = dem[1]; for (int i = 2; i < 100002; i++) f[i] = max(f[i - 2] + dem[i] * i, f[i - 1]); cout << f[100001]; } |
#include <bits/stdc++.h> using namespace std; const long long p = 1000000007LL; long long power(long long x, long long n) { long long ret = 1LL; while (n > 0LL) { if (n & 1LL) ret = ret * x % p; x = x * x % p; n >>= 1LL; } return ret; } long long n, m; long long dp; int main() { cin >> n >> m; dp = 1; for (long long i = 1LL; i <= n; i++) dp = (dp * (m * 2LL - 1LL) + power(m, i - 1LL)) % p; cout << dp << endl; } |
#include <bits/stdc++.h> using namespace std; long long res; const long long mod = 1073741824; long long d(int a, int b, int c) { vector<int> q(102, 0); for (int i = 2; i <= a; i++) if (a % i == 0) { while (a % i == 0) { a /= i; q[i]++; } } for (int i = 2; i <= b; i++) if (b % i == 0) { while (b % i == 0) { b /= i; q[i]++; } } for (int i = 2; i <= c; i++) if (c % i == 0) { while (c % i == 0) { c /= i; q[i]++; } } long long res = 1; for (int i = 0; i < 102; i++) res = (res * (q[i] + 1)) % mod; return res; } int main() { int a, b, c; cin >> a >> b >> c; for (int i = 1; i <= a; i++) for (int j = 1; j <= b; j++) for (int k = 1; k <= c; k++) res = (res % mod + d(i, j, k) % mod) % mod; cout << res; } |
#include <bits/stdc++.h> using namespace std; int n, k; struct Poi { int x, y, ff; bool operator<(const Poi &A) const { return x < A.x || (x == A.x && y < A.y); } } pp[(200100)]; int row[(200100)], cntr; int cnt[(200100)], pre[(200100)]; long long ans[(200100)]; inline void solve() { sort(pp + 1, pp + 1 + n * 2); for (int i = 1; i <= n * 2; ++i) { int y = lower_bound(row + 1, row + 1 + cntr, pp[i].y) - row; for (int j = y; row[j] < row[y] + k; ++j) { if (cnt[j] > 0) ans[cnt[j]] += (long long)(row[j + 1] - row[j]) * (pp[i].x - pre[j]); pre[j] = pp[i].x; cnt[j] += pp[i].ff; } } for (int i = 1; i <= n; ++i) cout << ans[i] << ; } inline void In() { scanf( %d %d , &n, &k); for (int i = 1; i <= n; ++i) { int i1 = i * 2 - 1, i2 = i * 2; scanf( %d %d , &pp[i1].x, &pp[i1].y); pp[i1].ff = 1; row[i1] = pp[i1].y; row[i2] = row[i1] + k; pp[i2].y = pp[i1].y; pp[i2].ff = -1; pp[i2].x = pp[i1].x + k; } sort(row + 1, row + 1 + n * 2); cntr = 1; for (int i = 2; i <= n * 2; ++i) if (row[i] != row[cntr]) row[++cntr] = row[i]; } int main() { In(); solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; int n, q, l; int A[N], sum[N]; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , A + i); sum[i] = sum[i - 1] + A[i]; } scanf( %d , &q); while (q--) { scanf( %d , &l); printf( %d n , lower_bound(sum, sum + n + 1, l) - sum); } return 0; } |
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2020 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file upd77c25_pgmrom.v when simulating
// the core, upd77c25_pgmrom. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module upd77c25_pgmrom(
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb
);
input clka;
input [0 : 0] wea;
input [10 : 0] addra;
input [23 : 0] dina;
input clkb;
input [10 : 0] addrb;
output [23 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(11),
.C_ADDRB_WIDTH(11),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(2048),
.C_READ_DEPTH_B(2048),
.C_READ_WIDTH_A(24),
.C_READ_WIDTH_B(24),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(2048),
.C_WRITE_DEPTH_B(2048),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(24),
.C_WRITE_WIDTH_B(24),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.DOUTA(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; long long holes[14]; int main() { long long zeroes = 0; for (long long i = 0; i < 14; i++) { cin >> holes[i]; if (holes[i] == 0) zeroes++; } zeroes++; long long mx = 0; for (long long i = 0; i < 14; i++) { long long cnt = 0; if (holes[i] != 0) { long long a = holes[i] / 14; long long b = holes[i] % 14; if (a % 2 == 0) { cnt = zeroes * a; while (b) { if (holes[(i + b) % 14] == 0) cnt -= a; else cnt += (a + holes[(i + b) % 14] + 1); b--; } } else { cnt = a * (14 - zeroes); for (long long j = 0; j < 14; j++) if (i != j) cnt += holes[j]; while (b) { if (holes[(i + b) % 14] == 0) cnt += a + 1; else cnt -= (a + holes[(i + b) % 14]); b--; } } } mx = max(cnt, mx); } cout << mx; } |
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 10994 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w8,
w7,
w8192,
w8185,
w896,
w7289,
w1792,
w5497,
w10994;
assign w1 = i_data0;
assign w10994 = w5497 << 1;
assign w1792 = w7 << 8;
assign w5497 = w7289 - w1792;
assign w7 = w8 - w1;
assign w7289 = w8185 - w896;
assign w8 = w1 << 3;
assign w8185 = w8192 - w7;
assign w8192 = w1 << 13;
assign w896 = w7 << 7;
assign o_data0 = w10994;
//multiplier_block area estimate = 6955.50221374706;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int t; int x, n, m; int main() { cin >> t; while (t--) { cin >> x >> n >> m; while (x > 20 && n) { x = x / 2 + 10; n--; } while (m) x -= 10, m--; if (x > 0) printf( NO n ); else printf( YES n ); } } |
#include <bits/stdc++.h> using namespace std; int n; char s[1000005]; int main() { int i, j, l, r, p = 0; scanf( %s , s); n = strlen(s); for (j = 0; j < n && s[j] != . ; j++) ; if (j == n) { s[n] = . ; n++; } for (i = 0; i < n && s[i] == 0 ; i++) ; if (i == j) { for (; i < n - 1 && s[i + 1] == 0 ; i++) swap(s[i], s[i + 1]), p--; if (i == n - 1) { printf( 0 n ); return 0; } swap(s[i], s[i + 1]), p--; for (r = n - 1; s[r] == 0 ; r--) ; if (s[r] == . ) r--; for (; i <= r; i++) printf( %c , s[i]); if (p != 0) printf( E%d n , p); } else { for (; j > i + 1; j--) swap(s[j], s[j - 1]), p++; for (r = n - 1; s[r] == 0 ; r--) ; if (s[r] == . ) r--; for (; i <= r; i++) printf( %c , s[i]); if (p != 0) printf( E%d n , p); } return 0; } |
#include <bits/stdc++.h> using namespace std; long long a[300005] = {0}; long long two[300005] = {0}; const long long mod = 1e9 + 7; int main() { two[0] = 1; for (int i = 1; i <= 300000; i++) { two[i] = (two[i - 1] * 2LL) % mod; } long long res = 0; int n; while (cin >> n) { a[0] = 0; for (int i = 1; i <= n; i++) { cin >> a[i]; } sort(a, a + n + 1); res = 0; for (int i = 1; i <= n; i++) { res += (a[i] * (two[i - 1] - two[n - i])); res %= mod; } cout << res << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O31A_LP_V
`define SKY130_FD_SC_LP__O31A_LP_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog wrapper for o31a with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o31a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o31a_lp (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o31a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o31a_lp (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o31a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O31A_LP_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 5; int n, a[maxn], b[maxn], t[maxn]; bool check(int num, int pos) { t[pos] = num; if (pos == n) return true; for (int i = 0; i <= 3; i++) { if ((num | i) == a[pos] && (num & i) == b[pos]) return check(i, pos + 1); } return false; } int main() { scanf( %d , &n); for (int i = 1; i < n; i++) { scanf( %d , &a[i]); } for (int i = 1; i < n; i++) { scanf( %d , &b[i]); } for (int i = 0; i <= 3; i++) { if (check(i, 1)) { printf( YES n ); for (int j = 1; j <= n; j++) { printf( %d , t[j]); } return 0; } } printf( NO ); } |
#include <bits/stdc++.h> #pragma GCC optimize( -O3 ) using namespace std; const long long N = 1e6 + 5; const long long MAX = 1e7 + 9; long long binarySearch(long long arr[], long long l, long long r, long long x) { if (r >= l) { long long mid = l + (r - l) / 2; if (arr[mid] == x) return mid; if (arr[mid] > x) return binarySearch(arr, l, mid - 1, x); return binarySearch(arr, mid + 1, r, x); } return -1; } void pairsort(long long a[], long long b[], long long n) { pair<long long, long long> pairt[n]; for (long long i = 0; i < n; i++) { pairt[i].first = a[i]; pairt[i].second = b[i]; } sort(pairt, pairt + n); for (long long i = 0; i < n; i++) { a[i] = pairt[i].first; b[i] = pairt[i].second; } } long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } long long isprime(long long n) { if (n < 2) return 0; if (n < 4) return 1; if (n % 2 == 0 or n % 3 == 0) return 0; for (long long i = 5; i * i <= n; i += 6) if (n % i == 0 or n % (i + 2) == 0) return 0; return 1; } long long C(long long n, long long r) { if (r > n - r) r = n - r; long long ans = 1; for (long long i = 1; i <= r; i++) { ans *= n - r + i; ans /= i; } return ans; } long long mod = 1e9 + 7; long long modexpo(long long x, long long p) { long long res = 1; x = x % mod; while (p) { if (p % 2) res = res * x; p >>= 1; x = x * x % mod; res %= mod; } return res; } long long countDistinct(long long arr[], long long n) { sort(arr, arr + n); long long res = 0; for (long long i = 0; i < n; i++) { while (i < n - 1 && arr[i] == arr[i + 1]) i++; res++; } return res; } long long int2Bin(string s) { reverse(s.begin(), s.end()); long long b = 1; long long x = 0; for (long long i = 0; i < s.length(); ++i) { if (s[i] == 1 ) x += b; b *= 2; ; } return x; } long long getSum(long long n) { long long sum; for (sum = 0; n > 0; sum += n % 10, n /= 10) ; return sum; } long long nex(long long i) { return (i / 10 + 1) * 10 - i; } bool up[N]; long long a[N], ind, leave[11]; int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t; cin >> t; while (t--) { long long n; cin >> n; pair<long long, long long> a[n]; long long i; for (i = 0; i < n; i++) { long long x; cin >> x; a[i].first = x; a[i].second = i; } sort(a, a + n); long long ans = 2 * n; for (i = 1; i < n; i++) { if (a[i].first == a[i - 1].first) ans = min(ans, a[i].second - a[i - 1].second + 1); } if (ans == 2 * n) cout << -1 n ; else cout << ans << n ; } } |
#include <bits/stdc++.h> using namespace std; long long t, n, m, u, v, q, k; const int N = 3e5 + 500; const int LN = 20; const int SN = 331; const long long mod = 1e9 + 7; const long long INF = 1LL << 57; long long arr[N], brr[N]; string str, ss; vector<int> adj[N]; vector<int> idx[N]; int d[N]; int actuald[N]; bool can[N]; bool vis[N]; void dfs(int v, int p) { if (d[v] == -1) d[v] = 0; vis[v] = true; for (int i = 0; i < adj[v].size(); ++i) { int u = adj[v][i]; if (u == p || vis[u]) continue; dfs(u, v); if (actuald[u] != d[u]) { can[idx[v][i]] = true; actuald[v]++; actuald[u]++; actuald[v] %= 2; actuald[u] %= 2; } } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> n >> m; int has = -1, sum = 0; for (int i = 1; i <= n; ++i) { cin >> d[i]; if (d[i] == -1) has = i; else sum += d[i]; } for (int i = 1; i <= m; ++i) { cin >> u >> v; adj[u].push_back(v); adj[v].push_back(u); idx[u].push_back(i); idx[v].push_back(i); } if (sum % 2 == 1 && has == -1) { cout << -1 << n ; return 0; } if (sum % 2 == 1) d[has] = 1; dfs(1, 0); sum = 0; for (int i = 1; i <= m; ++i) { sum += can[i]; } cout << sum << n ; for (int i = 1; i <= m; ++i) { if (can[i]) cout << i << ; } cout << n ; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A2BB2O_BLACKBOX_V
`define SKY130_FD_SC_HS__A2BB2O_BLACKBOX_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a2bb2o (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A2BB2O_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int maxN = 200011; long long n, i, j, cntx, cnty, x, y, z; long long vx[maxN]; map<long long, long long> Mx, My; map<pair<long long, long long>, long long> M; pair<long long, pair<long long, long long> > low; vector<vector<long long> > data; vector<long long> le, ri; vector<long long> vals; long long gcd(long long a, long long b) { if (a < b) swap(a, b); while (b > 0) { a %= b; swap(a, b); } return a; } bool check_rat() { int i, j; for (i = 1; i + 1 <= cntx; i++) { for (j = 1; j + 1 <= cnty; j++) { if (data[i][j] * data[i + 1][j + 1] != data[i + 1][j] * data[i][j + 1]) return false; } } return true; } void check(long long d) { long long i, j; le[low.second.first] = d; for (i = 1; i <= cnty; i++) { if (data[low.second.first][i] % d) return; ri[i] = data[low.second.first][i] / d; } for (i = 1; i <= cntx; i++) { if (data[i][1] % ri[1]) return; le[i] = data[i][1] / ri[1]; } long long aux = 0; for (i = 1; i <= cntx; i++) aux += le[i] * vx[i]; vals.push_back(aux); } int main() { low = make_pair(1LL << 60, make_pair(0, 0)); scanf( %lld , &n); for (i = 1; i <= n; i++) { scanf( %lld%lld%lld , &x, &y, &z); if (Mx[x] == 0) Mx[x] = ++cntx, vx[cntx] = x; if (My[y] == 0) My[y] = ++cnty; M[make_pair(Mx[x], My[y])] = z; low = min(low, make_pair(z, make_pair(Mx[x], My[y]))); } if (cntx * cnty != n) { printf( 0 ); return 0; } le.resize(cntx + 1); ri.resize(cnty + 1); data = vector<vector<long long> >(cntx + 1, vector<long long>(cnty + 1, 0)); for (i = 1; i <= cntx; i++) for (j = 1; j <= cnty; j++) data[i][j] = M[make_pair(i, j)]; if (!check_rat()) { printf( 0 ); return 0; } for (i = 1; i <= cnty; i++) low.first = gcd(low.first, data[low.second.first][i]); for (long long d = 1; d * d <= low.first; d++) { if (low.first % d) continue; check(d); if (d * d != low.first) check(low.first / d); } sort(vals.begin(), vals.end()); vals.resize(unique(vals.begin(), vals.end()) - vals.begin()); printf( %d , vals.size()); return 0; } |
`include "defines.v"
`timescale 1ns/1ps
module tb(
input `control_w port0_ci,
input `data_w port0_di,
output `control_w port0_co,
output `data_w port0_do,
input `control_w port1_ci,
input `data_w port1_di,
output `control_w port1_co,
output `data_w port1_do,
input `control_w port2_ci,
input `data_w port2_di,
output `control_w port2_co,
output `data_w port2_do,
input `control_w port3_ci,
input `data_w port3_di,
output `control_w port3_co,
output `data_w port3_do,
input `control_w port4_ci,
input `data_w port4_di,
output `control_w port4_co,
output `data_w port4_do
);
wire injrd, injack;
reg clk, rst;
reg `control_w flit0c;
reg `data_w flit0d;
reg `control_w flit1c;
reg `data_w flit1d;
reg `control_w flit2c;
reg `data_w flit2d;
reg `control_w flit3c;
reg `data_w flit3d;
brouter r(
.clk(clk),
.rst(rst),
.port0_ci(flit0c), .port0_co(port0_co),
.port1_ci(flit1c), .port1_co(port1_co),
.port2_ci(flit2c), .port2_co(port2_co),
.port3_ci(flit3c), .port3_co(port3_co),
.port4_ci(port4_ci), .port4_co(port4_co),
.port0_di(flit0d), .port0_do(port0_do),
.port1_di(flit1d), .port1_do(port1_do),
.port2_di(flit2d), .port2_do(port2_do),
.port3_di(flit3d), .port3_do(port3_do),
.port4_di(port4_di), .port4_do(port4_do),
.port4_ready(injrd)
);
initial begin
clk = 0;
rst = 0;
flit0c = 22'h200001;
flit0d = 128'h0123456789abcdef0123456789abcdef;
flit1c = 22'h200802;
flit1d = 128'h0123456789abcdef0123456789abcdef;
flit2c = 22'h200c03;
flit2d = 128'h0123456789abcdef0123456789abcdef;
flit3c = 22'h201804;
flit3d = 128'h0123456789abcdef0123456789abcdef;
#1;
clk = 1;
#1;
clk = 0;
flit0c = 22'h0;
flit0d = 128'h0;
$display("port0 %04x, port1 %04x, port2 %04x, port3 %04x, port4 %04x\n",
port0_co, port1_co, port2_co, port3_co, port4_co);
$display("port0 %16x, port1 %16x, port2 %16x, port3 %16x, port4 %16x\n",
port0_do, port1_do, port2_do, port3_do, port4_do);
#1;
clk = 1;
#1;
clk = 0;
$display("port0 %04x, port1 %04x, port2 %04x, port3 %04x, port4 %04x\n",
port0_co, port1_co, port2_co, port3_co, port4_co);
$display("port0 %16x, port1 %16x, port2 %16x, port3 %16x, port4 %16x\n",
port0_do, port1_do, port2_do, port3_do, port4_do);
#1;
clk = 1;
#1;
clk = 0;
$display("port0 %04x, port1 %04x, port2 %04x, port3 %04x, port4 %04x\n",
port0_co, port1_co, port2_co, port3_co, port4_co);
$display("port0 %16x, port1 %16x, port2 %16x, port3 %16x, port4 %16x\n",
port0_do, port1_do, port2_do, port3_do, port4_do);
end
endmodule
|
module GPU_core(
input clk,
// ~ wishbone. Somethink like wishbone
input wire [31:0] W_ADDR,
input wire [31:0] W_DAT_I,
input wire W_CLK,
input wire W_RST,
output reg [31:0] W_DAT_O,
output reg W_ACK,
// monitor connection
input [9:0] x,
input [8:0] y,
output R,
output G,
output B,
output reg [9:0] res_x,
output reg [8:0] res_y,
output reg flipHenable,
output reg flipVenable
);
reg [3:0] cbyte;
reg [15:0] cc_code;
reg ccolor;
wire [15:0] char_code;
// temporary
assign R = ccolor;
assign G = ccolor;
assign B = ccolor;
reg ss;
wire [7:0] sline;
initial
begin
res_x <= 799;
res_y <= 479;
flipVenable <= 1'b1;
flipHenable <= 1'b1;
ccolor <= 1'b0;
end
// clk, data_a, data_b, addr_a, addr_b, we_a, we_b, q_a, q_b (not used)
V_RAM vram(clk, 16'b0, cc_code, {y[8:4], x[9:3]}, 16'h0, 1'b0, 1'b0, char_code);
CHARSET charset(clk, {char_code[7:0], y[3:0]}, sline);
always @(posedge clk)
ccolor <= sline[3'b111 - x[2:0] + 3'b001] ? 1'b0 : 1'b1;
endmodule |
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2007 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file fifo_xlnx_16x40_2clk.v when simulating
// the core, fifo_xlnx_16x40_2clk. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module fifo_xlnx_16x40_2clk(
din,
rd_clk,
rd_en,
rst,
wr_clk,
wr_en,
dout,
empty,
full);
input [39 : 0] din;
input rd_clk;
input rd_en;
input rst;
input wr_clk;
input wr_en;
output [39 : 0] dout;
output empty;
output full;
// synthesis translate_off
FIFO_GENERATOR_V4_3 #(
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(4),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(40),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(40),
.C_ENABLE_RLOCS(0),
.C_FAMILY("spartan3"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(2),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x72"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(15),
.C_PROG_FULL_THRESH_NEGATE_VAL(14),
.C_PROG_FULL_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(4),
.C_RD_DEPTH(16),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(4),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(4),
.C_WR_DEPTH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(4),
.C_WR_RESPONSE_LATENCY(1))
inst (
.DIN(din),
.RD_CLK(rd_clk),
.RD_EN(rd_en),
.RST(rst),
.WR_CLK(wr_clk),
.WR_EN(wr_en),
.DOUT(dout),
.EMPTY(empty),
.FULL(full),
.CLK(),
.INT_CLK(),
.BACKUP(),
.BACKUP_MARKER(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.RD_RST(),
.SRST(),
.WR_RST(),
.ALMOST_EMPTY(),
.ALMOST_FULL(),
.DATA_COUNT(),
.OVERFLOW(),
.PROG_EMPTY(),
.PROG_FULL(),
.VALID(),
.RD_DATA_COUNT(),
.UNDERFLOW(),
.WR_ACK(),
.WR_DATA_COUNT(),
.SBITERR(),
.DBITERR());
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; inline long long gcd(long long a, long long b) { a = ((a) < 0 ? -(a) : (a)); b = ((b) < 0 ? -(b) : (b)); while (b) { a = a % b; swap(a, b); } return a; } const long long inf = 2147383647; const long long mod = 1000000007; const double pi = 2 * acos(0.0); const double eps = 1e-9; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); int main() { int t; cin >> t; int x, y, z, a, b, c, ans; for (int kas = 1; kas <= t; kas++) { scanf( %d , &x); scanf( %d , &y); scanf( %d , &z); a = min(x, y); b = max(x, y); c = b - a; if (z <= a) { ans = (x + y + z) / 3; ans = min(ans, a); } else ans = a; printf( %d n , ans); } return 0; } |
#include <bits/stdc++.h> using namespace std; signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; long long int n, t, x, y, a = 0, b = 0, suma = 0, sumb = 0; cin >> n; while (n--) { cin >> t >> x >> y; if (t == 1) { a++; suma += x; } else { b++; sumb += x; } } if (suma >= 5 * a) cout << LIVE ; else cout << DEAD ; cout << endl; if (sumb >= 5 * b) cout << LIVE ; else cout << DEAD ; } |
///////////////////////////////////////////////////////////
module counter_behavioural #(
parameter bits = 16
) (
input clock, reset, enable, load,
input [bits-1:0] init,
output reg [bits-1:0] q
);
always @(posedge clock, posedge reset)
if (reset)
q <= 0;
else if (enable)
if (load) q <= init;
else q <= q + 1;
endmodule
///////////////////////////////////////////////////////////
module register #(
parameter bits = 16
) (
input clock, reset, enable,
input [bits-1:0] d,
output reg [bits-1:0] q
);
always @(posedge clock, posedge reset)
if (reset)
q <= 0;
else if (enable)
q <= d;
endmodule
module mux2 #(
parameter bits = 16
) (
input sel,
input [bits-1:0] d0, d1,
output [bits-1:0] q
);
assign q = sel ? d1 : d0;
endmodule
module add #(
parameter bits = 16
) (
input [bits-1:0] a, b,
output [bits-1:0] q
);
assign q = a + b;
endmodule
module counter_structural #(
parameter bits = 16
) (
input clock, reset, enable, load,
input [bits-1:0] init,
output [bits-1:0] q
);
wire [bits-1:0] qp, qf;
add #(bits) theadd (q, 1, qp);
mux2 #(bits) themux (load, init, qp, qf);
register #(bits) thereg (clock, reset, enable, qf, q);
endmodule
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 30165 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w2048,
w2047,
w4,
w2043,
w32,
w2011,
w32176,
w30165;
assign w1 = i_data0;
assign w2011 = w2043 - w32;
assign w2043 = w2047 - w4;
assign w2047 = w2048 - w1;
assign w2048 = w1 << 11;
assign w30165 = w32176 - w2011;
assign w32 = w1 << 5;
assign w32176 = w2011 << 4;
assign w4 = w1 << 2;
assign o_data0 = w30165;
//multiplier_block area estimate = 7032.00941024118;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21A_4_V
`define SKY130_FD_SC_HDLL__O21A_4_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog wrapper for o21a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o21a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o21a_4 (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__o21a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o21a_4 (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__o21a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21A_4_V
|
#include <bits/stdc++.h> using namespace std; const int INF = 1e9 + 7, N = 3e5 + 7, M = 998244353; vector<int> G[N], add[N], del[N]; long long f[N], fi[N], inv[N]; int cans[41], dp[1 << 20][21]; int C(int n, int k) { return f[n] * fi[k] % M * fi[n - k] % M; } void ADD(int& a, int b) { a += b; if (a >= M) a -= M; } signed main() { std::ios::sync_with_stdio(0); std::cin.tie(0); ; f[0] = 1; for (int i = 1; i < N; i++) f[i] = f[i - 1] * i % M; inv[1] = 1; for (int i = 2; i < N; i++) inv[i] = M - M / i * inv[M % i] % M; fi[0] = 1; for (int i = 1; i < N; i++) fi[i] = fi[i - 1] * inv[i] % M; int n, m; cin >> n >> m; for (int i = 1; i <= n; i++) { int l, r; cin >> l >> r; add[l].push_back(i); del[r + 1].push_back(i); } for (int i = 0; i < m; i++) { int u, v; cin >> u >> v; G[u].push_back(i); G[v].push_back(i); } long long ans = 0, cnt = 0, cnt1 = 0; dp[0][0] = cans[0] = 1; for (int i = 1; i <= n; i++) { bool change = false; for (int j : add[i]) { if (G[j].size()) { int mask = 0; for (int k : G[j]) mask |= 1 << k; for (int k = 0; k < (1 << m); k++) for (int l = 1; l <= 20; l++) if ((k & mask) == mask) ADD(dp[k][l], dp[k ^ mask][l - 1]); change = true; cnt1++; } else cnt++; } for (int j : del[i]) { if (G[j].size()) { int mask = 0; for (int k : G[j]) mask |= 1 << k; for (int k = 0; k < (1 << m); k++) for (int l = 1; l <= 20; l++) if ((k & mask) == mask) ADD(dp[k][l], M - (dp[k ^ mask][l - 1] ? dp[k ^ mask][l - 1] : M)); change = true; cnt1--; } else cnt--; } if (change) { memset(cans, 0, sizeof cans); for (int mask = 0; mask < (1 << m); mask++) for (int j = 0; j <= 20; j++) ADD(cans[j], dp[mask][j]); } for (int j = 0; j <= cnt1; j++) { if (i - j < 0 || i - j > cnt) continue; ans = (ans + (long long)C(cnt, i - j) * cans[j]) % M; } } cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; template <class T> void read(T& num) { char CH; bool F = false; for (CH = getchar(); CH < 0 || CH > 9 ; F = CH == - , CH = getchar()) ; for (num = 0; CH >= 0 && CH <= 9 ; num = num * 10 + CH - 0 , CH = getchar()) ; F && (num = -num); } int stk[70], tp; template <class T> inline void print(T p) { if (!p) { puts( 0 ); return; } while (p) stk[++tp] = p % 10, p /= 10; while (tp) putchar(stk[tp--] + 0 ); putchar( n ); } const int mod = 1e9 + 7; const double PI = acos(-1.0); const int inf = 1e9; const int N = 1e6 + 20; const int maxn = 1e5 + 110; const double eps = 1e-12; int main() { int n, k; read(n); read(k); cout << (n - 1) * 6 * k + 5 * k << endl; for (int i = 1; i <= n; i++) { int t = (i - 1) * 6 + 1; printf( %d %d %d %d n , t * k, t * k + k, t * k + 2 * k, t * k + 4 * k); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 100000 + 10; int a[maxn], b[maxn]; int main() { int n; scanf( %d , &n); long long ans = 0; int cnt1 = 0, cnt2 = 0, cnt0 = 0; for (int i = 1; i <= n; i++) { scanf( %d , a + i); if (a[i] <= -1) { ans += -1 - a[i]; cnt1++; } else if (a[i] >= 1) { ans += a[i] - 1; cnt2++; } else { cnt0++; } } if (cnt1 % 2) { if (cnt0) { ans += cnt0; } else { ans += 2; } } else { ans += cnt0; } printf( %lld n , ans); getchar(); getchar(); return 0; } |
#include <bits/stdc++.h> using namespace std; int tree[10000][2]; int lights; void mark(int node, int l) { int p = node / 2; if (p == 0) return; tree[p][node % 2] = min(tree[p][node % 2], lights - l); mark(p, l); } int cont[10000]; int main() { cin.tie(0); ios_base::sync_with_stdio(0); memset(tree, -1, sizeof(tree)); int n, a, p; cin >> n; int lim = (1 << (n + 1)) - 1; for (int i = 2; i <= lim; ++i) { cin >> a; p = i / 2; tree[p][i % 2] = a; } lights = 0; queue<int> Q; Q.push(1); Q.push(0); while (!Q.empty()) { int u = Q.front(); Q.pop(); int l = Q.front(); Q.pop(); if (tree[u][0] == -1) { lights = max(lights, l); cont[u] = l; continue; } Q.push(2 * u); Q.push(tree[u][0] + l); Q.push(2 * u + 1); Q.push(tree[u][1] + l); tree[u][0] = tree[u][1] = 0x3fffffff; } for (int i = 1 << n; i <= lim; ++i) mark(i, cont[i]); int ans = 0; Q.push(1); Q.push(0); while (!Q.empty()) { int u = Q.front(); Q.pop(); int l = Q.front(); Q.pop(); if (tree[u][0] == -1) continue; ans += tree[u][0] + tree[u][1] - 2 * l; Q.push(2 * u); Q.push(tree[u][0]); Q.push(2 * u + 1); Q.push(tree[u][1]); } cout << ans; } |
#include <bits/stdc++.h> int n, h; char name[10]; long double p[70], cont[70]; int main() { scanf( %s%d%d , name, &n, &h); if (name[0] == B ) { printf( %d n , n); return 0; } long double ans = n; p[0] = cont[0] = 1.0; for (int i = 1; i <= h; i++) { p[i] = p[i - 1] / 2.0; cont[i] = cont[i - 1] * 2.0; } for (int i = 1; i <= h; i++) for (int j = 2; j <= n; j++) ans += p[i] * p[i] * pow(1.0 - p[i], j - 2) * (cont[i] - cont[i - 1] * ((j - 2) / (cont[i] - 1.0) + 1.0)) * (n - j + 1); printf( %.10f n , (double)ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int a, b, mn = 1000000009, mx; char c[59][59]; int ist, ien; bool w; int main() { cin >> a >> b; for (int i = 1; i <= a; i++) for (int j = 1; j <= b; j++) { cin >> c[i][j]; if (c[i][j] == * ) mn = min(j, mn), mx = max(j, mx), (w == 0 ? ist = i : ist = ist), ien = i, w = 1; } for (int i = ist; i <= ien; i++) { for (int j = mn; j <= mx; j++) cout << c[i][j]; cout << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A31O_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__A31O_PP_BLACKBOX_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a31o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A31O_PP_BLACKBOX_V
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate task with internal delay
module main;
reg var1,var2;
reg in1;
reg error;
task my_task ;
input in1;
output out1;
out1 = #10 in1;
endtask
initial
begin
var1 = 0;
error = 0;
fork
my_task(1'b1,var1);
begin
if(var1 != 1'b0)
begin
$display("FAILED - task3.14F Task with internal delay(1)");
error = 1;
end
#20;
if(var1 != 1'b1)
begin
$display("FAILED - task3.14F Task with internal delay(2)");
error = 1;
end
end
join
if(error == 0)
$display("PASSED");
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; void seive(bool a[], long long int n) { for (int i = 2; i * i <= n; i++) { if (a[i] == true) { for (int j = i * i; j <= n; j += i) a[j] = false; } } } int np(bool a[], long long int ppr, long long int n) { ppr++; while (ppr <= n) { if (a[ppr] == true) return ppr; ppr++; } return -1; } int main() { long long int n, i, n_1 = 0, n_2 = 0, sum = 0, s; int t; cin >> n; for (i = 0; i < n; i++) { cin >> t; if (t == 1) n_1++; else n_2++; sum += t; } bool a[sum + 1]; memset(a, true, sizeof(a)); seive(a, sum); s = 0; a[1] = false; long long int ppr = 0, pr; while (s <= sum && pr != -1) { pr = np(a, ppr, sum); if (pr - ppr >= 2 && pr != -1) { s = pr; int m = min(n_2, (pr - ppr) / 2); n_2 -= m; for (i = 0; i < m; i++) cout << 2 << ; m = min(n_1, 2 * ((pr - ppr) / 2 - m)); n_1 -= m; for (i = 0; i < m; i++) cout << 1 << ; ppr = pr; } else if (pr != -1) { n_1--; if (n_1 < 0) { for (i = 0; i < n_1; i++) cout << 1 << ; for (i = 0; i < n_2; i++) cout << 2 << ; pr = -1; } else { cout << 1 << ; } ppr = pr; } else { for (i = 0; i < n_1; i++) cout << 1 << ; for (i = 0; i < n_2; i++) cout << 2 << ; } if (n_1 <= 0 && n_2 <= 0) break; } return 0; } |
#include <bits/stdc++.h> using namespace std; int freq[3]; int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); int n; cin >> n; string s; cin >> s; for (int i = 0; i < n; i++) { freq[s[i] - 0 ]++; } for (int i = n - 1; i >= 0; i--) { if (freq[0] <= n / 3) { break; } if (s[i] == 0 ) { if (freq[2] < n / 3) { freq[2]++; s[i] = 2 ; freq[0]--; } else { freq[1]++; s[i] = 1 ; freq[0]--; } } } for (int i = 0; i < n; i++) { if (freq[1] <= n / 3) break; if (s[i] == 1 ) { if (freq[0] < n / 3) { freq[0]++; freq[1]--; s[i] = 0 ; } } } for (int i = n - 1; i >= 0; i--) { if (freq[1] <= n / 3) break; if (s[i] == 1 ) { if (freq[2] < n / 3) { freq[2]++; freq[1]--; s[i] = 2 ; } } } for (int i = 0; i < n; i++) { if (freq[2] <= n / 3) break; if (s[i] == 2 ) { if (freq[0] < n / 3) { freq[0]++; freq[2]--; s[i] = 0 ; } else { freq[1]++; freq[2]--; s[i] = 1 ; } } } cout << s; return 0; } |
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\PWM.v
// Created: 2014-09-08 14:12:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: PWM
// Source Path: controllerPeripheralHdlAdi/PWM
// Hierarchy Level: 1
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module PWM
(
CLK_IN,
reset,
enb,
c_0,
c_1,
c_2,
pwm_0,
pwm_1,
pwm_2
);
input CLK_IN;
input reset;
input enb;
input [15:0] c_0; // uint16
input [15:0] c_1; // uint16
input [15:0] c_2; // uint16
output pwm_0; // boolean
output pwm_1; // boolean
output pwm_2; // boolean
wire [15:0] Timer_Period_Clock_Cycles_out1; // uint16
wire [15:0] Chart_out1; // uint16
wire [15:0] c [0:2]; // uint16 [3]
wire [15:0] Add_out1 [0:2]; // uint16 [3]
wire [15:0] Add_out1_0; // uint16
wire Relational_Operator_relop1;
wire [15:0] Add_out1_1; // uint16
wire Relational_Operator_relop2;
wire [15:0] Add_out1_2; // uint16
wire Relational_Operator_relop3;
wire [0:2] Relational_Operator_out1; // boolean [3]
wire Relational_Operator_out1_0;
wire [0:2] Compare_To_Zero_out1; // boolean [3]
wire Compare_To_Zero_out1_0;
wire Relational_Operator_out1_0_1;
wire Relational_Operator_out1_1;
wire Compare_To_Zero_out1_1;
wire Relational_Operator_out1_1_1;
wire Relational_Operator_out1_2;
wire Compare_To_Zero_out1_2;
wire Relational_Operator_out1_2_1;
// <S2>/Timer Period Clock Cycles
assign Timer_Period_Clock_Cycles_out1 = 16'd1000;
// <S2>/Chart
Chart u_Chart (.CLK_IN(CLK_IN),
.reset(reset),
.enb(enb),
.CounterMax(Timer_Period_Clock_Cycles_out1), // uint16
.count(Chart_out1) // uint16
);
assign c[0] = c_0;
assign c[1] = c_1;
assign c[2] = c_2;
// <S2>/Add
assign Add_out1[0] = Timer_Period_Clock_Cycles_out1 - c[0];
assign Add_out1[1] = Timer_Period_Clock_Cycles_out1 - c[1];
assign Add_out1[2] = Timer_Period_Clock_Cycles_out1 - c[2];
assign Add_out1_0 = Add_out1[0];
assign Relational_Operator_relop1 = (Chart_out1 >= Add_out1_0 ? 1'b1 :
1'b0);
assign Add_out1_1 = Add_out1[1];
assign Relational_Operator_relop2 = (Chart_out1 >= Add_out1_1 ? 1'b1 :
1'b0);
assign Add_out1_2 = Add_out1[2];
// <S2>/Relational Operator
assign Relational_Operator_relop3 = (Chart_out1 >= Add_out1_2 ? 1'b1 :
1'b0);
assign Relational_Operator_out1[0] = Relational_Operator_relop1;
assign Relational_Operator_out1[1] = Relational_Operator_relop2;
assign Relational_Operator_out1[2] = Relational_Operator_relop3;
assign Relational_Operator_out1_0 = Relational_Operator_out1[0];
// <S2>/Compare To Zero
assign Compare_To_Zero_out1[0] = (c[0] != 16'b0000000000000000 ? 1'b1 :
1'b0);
assign Compare_To_Zero_out1[1] = (c[1] != 16'b0000000000000000 ? 1'b1 :
1'b0);
assign Compare_To_Zero_out1[2] = (c[2] != 16'b0000000000000000 ? 1'b1 :
1'b0);
assign Compare_To_Zero_out1_0 = Compare_To_Zero_out1[0];
assign Relational_Operator_out1_0_1 = Relational_Operator_out1_0 & Compare_To_Zero_out1_0;
assign pwm_0 = Relational_Operator_out1_0_1;
assign Relational_Operator_out1_1 = Relational_Operator_out1[1];
assign Compare_To_Zero_out1_1 = Compare_To_Zero_out1[1];
assign Relational_Operator_out1_1_1 = Relational_Operator_out1_1 & Compare_To_Zero_out1_1;
assign pwm_1 = Relational_Operator_out1_1_1;
assign Relational_Operator_out1_2 = Relational_Operator_out1[2];
assign Compare_To_Zero_out1_2 = Compare_To_Zero_out1[2];
// <S2>/Logical Operator
assign Relational_Operator_out1_2_1 = Relational_Operator_out1_2 & Compare_To_Zero_out1_2;
assign pwm_2 = Relational_Operator_out1_2_1;
endmodule // PWM
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__UDP_DFF_PS_PP_PG_N_TB_V
`define SKY130_FD_SC_LS__UDP_DFF_PS_PP_PG_N_TB_V
/**
* udp_dff$PS_pp$PG$N: Positive edge triggered D flip-flop with active
* high
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__udp_dff_ps_pp_pg_n.v"
module top();
// Inputs are registered
reg D;
reg SET;
reg NOTIFIER;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
NOTIFIER = 1'bX;
SET = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 NOTIFIER = 1'b0;
#60 SET = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 NOTIFIER = 1'b1;
#160 SET = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 NOTIFIER = 1'b0;
#260 SET = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 SET = 1'b1;
#380 NOTIFIER = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 SET = 1'bx;
#480 NOTIFIER = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_ls__udp_dff$PS_pp$PG$N dut (.D(D), .SET(SET), .NOTIFIER(NOTIFIER), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__UDP_DFF_PS_PP_PG_N_TB_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long i, j, k, n, t; cin >> n; vector<long long> adj[n + 1]; vector<long long> par(n + 1, 0); for (i = 2; i <= n; i++) { cin >> k; par[i] = k; adj[k].push_back(i); } vector<long long> level(n + 1, 0); level[1] = 0; queue<long long> q; q.push(1); vector<bool> vis; long long maxim = INT_MIN; while (!q.empty()) { long long u = q.front(); q.pop(); for (j = 0; j < adj[u].size(); j++) { level[adj[u][j]] = level[u] + 1; maxim = max(level[u] + 1, maxim); q.push(adj[u][j]); } } vector<long long> maxiy[maxim + 1]; for (j = 1; j <= n; j++) { k = level[j]; maxiy[k].push_back(j); } vector<long long> ans(maxim + 1, 1); k = 0; for (j = maxim; j >= 0; j--) { k += maxiy[j].size() % 2; } cout << k << endl; return 0; } |
//-----------------------------------------------------------------------------
//
// Jonathan Westhues, April 2006
//-----------------------------------------------------------------------------
module hi_read_rx_xcorr(
pck0, ck_1356meg, ck_1356megb,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
cross_hi, cross_lo,
dbg,
xcorr_is_848, snoop, xcorr_quarter_freq
);
input pck0, ck_1356meg, ck_1356megb;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
input cross_hi, cross_lo;
output dbg;
input xcorr_is_848, snoop, xcorr_quarter_freq;
// Carrier is steady on through this, unless we're snooping.
assign pwr_hi = ck_1356megb & (~snoop);
assign pwr_oe1 = 1'b0;
assign pwr_oe3 = 1'b0;
assign pwr_oe4 = 1'b0;
reg [2:0] fc_div;
always @(negedge ck_1356megb)
fc_div <= fc_div + 1;
(* clock_signal = "yes" *) reg adc_clk; // sample frequency, always 16 * fc
always @(ck_1356megb, xcorr_is_848, xcorr_quarter_freq, fc_div)
if (xcorr_is_848 & ~xcorr_quarter_freq) // fc = 847.5 kHz, standard ISO14443B
adc_clk <= ck_1356megb;
else if (~xcorr_is_848 & ~xcorr_quarter_freq) // fc = 423.75 kHz
adc_clk <= fc_div[0];
else if (xcorr_is_848 & xcorr_quarter_freq) // fc = 211.875 kHz
adc_clk <= fc_div[1];
else // fc = kHz
adc_clk <= fc_div[2];
// When we're a reader, we just need to do the BPSK demod; but when we're an
// eavesdropper, we also need to pick out the commands sent by the reader,
// using AM. Do this the same way that we do it for the simulated tag.
reg after_hysteresis, after_hysteresis_prev, after_hysteresis_prev_prev;
reg [11:0] has_been_low_for;
always @(negedge adc_clk)
begin
if(& adc_d[7:0]) after_hysteresis <= 1'b1;
else if(~(| adc_d[7:0])) after_hysteresis <= 1'b0;
if(after_hysteresis)
begin
has_been_low_for <= 7'b0;
end
else
begin
if(has_been_low_for == 12'd4095)
begin
has_been_low_for <= 12'd0;
after_hysteresis <= 1'b1;
end
else
has_been_low_for <= has_been_low_for + 1;
end
end
// Let us report a correlation every 4 subcarrier cycles, or 4*16=64 samples,
// so we need a 6-bit counter.
reg [5:0] corr_i_cnt;
// And a couple of registers in which to accumulate the correlations. Since
// load modulation saturates the ADC we have to use a large enough register
// 32 * 255 = 8160, which can be held in 13 bits. Add 1 bit for sign.
//
// The initial code assumed a phase shift of up to 25% and the accumulators were
// 11 bits (32 * 255 * 0,25 = 2040), we will pack all bits exceeding 11 bits into
// MSB. This prevents under/-overflows but preserves sensitivity on the lower end.
reg signed [13:0] corr_i_accum;
reg signed [13:0] corr_q_accum;
// we will report maximum 8 significant bits
reg signed [7:0] corr_i_out;
reg signed [7:0] corr_q_out;
// clock and frame signal for communication to ARM
reg ssp_clk;
reg ssp_frame;
always @(negedge adc_clk)
begin
corr_i_cnt <= corr_i_cnt + 1;
end
// ADC data appears on the rising edge, so sample it on the falling edge
always @(negedge adc_clk)
begin
// These are the correlators: we correlate against in-phase and quadrature
// versions of our reference signal, and keep the (signed) result to
// send out later over the SSP.
if(corr_i_cnt == 6'd0)
begin
// send 10 bits of tag signal, 4 MSBs are stuffed into 2 MSB
if(~corr_i_accum[13])
corr_i_out <= {corr_i_accum[13],
corr_i_accum[12] | corr_i_accum[11] | corr_i_accum[10],
corr_i_accum[12] | corr_i_accum[11] | corr_i_accum[9],
corr_i_accum[8:4]};
else
corr_i_out <= {corr_i_accum[13],
corr_i_accum[12] & corr_i_accum[11] & corr_i_accum[10],
corr_i_accum[12] & corr_i_accum[11] & corr_i_accum[9],
corr_i_accum[8:4]};
if(~corr_q_accum[13])
corr_q_out <= {corr_q_accum[13],
corr_q_accum[12] | corr_q_accum[11] | corr_q_accum[10],
corr_q_accum[12] | corr_q_accum[11] | corr_q_accum[9],
corr_q_accum[8:4]};
else
corr_q_out <= {corr_q_accum[13],
corr_q_accum[12] & corr_q_accum[11] & corr_q_accum[10],
corr_q_accum[12] & corr_q_accum[11] & corr_q_accum[9],
corr_q_accum[8:4]};
if(snoop)
begin
// replace LSB with 1 bit reader signal
corr_i_out[0] <= after_hysteresis_prev_prev;
corr_q_out[0] <= after_hysteresis_prev;
after_hysteresis_prev_prev <= after_hysteresis;
end
corr_i_accum <= adc_d;
corr_q_accum <= adc_d;
end
else
begin
if(corr_i_cnt[3])
corr_i_accum <= corr_i_accum - adc_d;
else
corr_i_accum <= corr_i_accum + adc_d;
if(corr_i_cnt[3] == corr_i_cnt[2]) // phase shifted by pi/2
corr_q_accum <= corr_q_accum + adc_d;
else
corr_q_accum <= corr_q_accum - adc_d;
end
// The logic in hi_simulate.v reports 4 samples per bit. We report two
// (I, Q) pairs per bit, so we should do 2 samples per pair.
if(corr_i_cnt == 6'd32)
after_hysteresis_prev <= after_hysteresis;
// Then the result from last time is serialized and send out to the ARM.
// We get one report each cycle, and each report is 16 bits, so the
// ssp_clk should be the adc_clk divided by 64/16 = 4.
if(corr_i_cnt[1:0] == 2'b10)
ssp_clk <= 1'b0;
if(corr_i_cnt[1:0] == 2'b00)
begin
ssp_clk <= 1'b1;
// Don't shift if we just loaded new data, obviously.
if(corr_i_cnt != 6'd0)
begin
corr_i_out[7:0] <= {corr_i_out[6:0], corr_q_out[7]};
corr_q_out[7:1] <= corr_q_out[6:0];
end
end
// set ssp_frame signal for corr_i_cnt = 0..3 and corr_i_cnt = 32..35
// (send two frames with 8 Bits each)
if(corr_i_cnt[5:2] == 4'b0000 || corr_i_cnt[5:2] == 4'b1000)
ssp_frame = 1'b1;
else
ssp_frame = 1'b0;
end
assign ssp_din = corr_i_out[7];
assign dbg = corr_i_cnt[3];
// Unused.
assign pwr_lo = 1'b0;
assign pwr_oe2 = 1'b0;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long NR = 5e5 + 100; const long long oo = 2e9 + 100; const long long MOD = 998244353; long long n; string s; long long a[NR]; long long dp[5]; signed main() { ios::sync_with_stdio(0); cin.tie(0); long long i; cin >> n; cin >> s; for (i = 0; i < n; ++i) { cin >> a[i]; } for (i = 0; i < s.size(); ++i) { if (s[i] == h ) { dp[0] += a[i]; } if (s[i] == a ) { dp[1] = min(dp[1] + a[i], dp[0]); } if (s[i] == r ) { dp[2] = min(a[i] + dp[2], dp[1]); } if (s[i] == d ) { dp[3] = min(a[i] + dp[3], dp[2]); } } cout << dp[3] << n ; return 0; } |
/*
* This module demonstrates the ability to use a defparam to control
* the instantation of an instance array, and to also control
* parameter values within the instance array.
*/
module main;
localparam wid = 5;
reg [wid-1:0] clk;
dut xx (.clk(clk));
// This defparam sets the desired with of the U instance vector.
defparam main.xx.wid = wid;
// These defparams set parameters within U instances.
defparam main.xx.sub[0].U.number = 0;
defparam main.xx.sub[1].U.number = 1;
defparam main.xx.sub[2].U.number = 2;
defparam main.xx.sub[3].U.number = 3;
defparam main.xx.sub[4].U.number = 4;
initial begin
clk = 0;
#1 clk = 1;
while (clk != 0)
#1 clk = clk << 1;
$finish(0);
end
endmodule // main
module dut #(parameter wid = 1) (input [wid-1:0] clk);
genvar i;
for (i = 0 ; i < wid ; i = i+1) begin : sub
target U (.clk(clk[i]));
end
endmodule //
module target(input wire clk);
parameter number = 999;
always @(posedge clk)
$display("%m: number=%0d", number);
endmodule // target
|
/** * Author: lukasdeimos */ #include<bits/stdc++.h> #define endl n #define ff first #define ss second using ll = long long; using namespace std; void solve() { int n,k; cin >> n >> k; cout << (n-k+k/2) << endl; for(int i = k+1; i <= n; i++) cout << i << ; for(int i = (k+1)/2; i < k; i++) cout << i << ; cout << endl; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); ll tt; tt = 1; cin >> tt; for(auto test_case = 1; test_case <= tt; test_case++) { // cout << Case << test_case << : ; solve(); } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR4BB_FUNCTIONAL_V
`define SKY130_FD_SC_MS__NOR4BB_FUNCTIONAL_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__nor4bb (
Y ,
A ,
B ,
C_N,
D_N
);
// Module ports
output Y ;
input A ;
input B ;
input C_N;
input D_N;
// Local signals
wire nor0_out ;
wire and0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y, nor0_out, C_N, D_N);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR4BB_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; pair<int, long long> da; inline long long p(long long x) { return x * x * x; } long long m; void dfs(long long now, int sum, long long maxnum) { if (!now) da = max(da, make_pair(sum, maxnum)); else { long long i = 1; for (; p(i + 1) <= now; ++i) ; dfs(now - p(i), sum + 1, maxnum + p(i)); if (now) dfs(p(i) - p(i - 1) - 1, sum + 1, maxnum + p(i - 1)); } } int main() { scanf( %lld , &m); dfs(m, 0, 0); printf( %d %lld , da.first, da.second); } |
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; template <class T> inline void amin(T &x, const T &y) { if (y < x) x = y; } template <class T> inline void amax(T &x, const T &y) { if (x < y) x = y; } template <class Iter> void rprintf(const char *fmt, Iter begin, Iter end) { for (bool sp = 0; begin != end; ++begin) { if (sp) putchar( ); else sp = true; printf(fmt, *begin); } putchar( n ); } int N; int dp[2011]; int prv[2011]; bool tar[1011]; bool cur[1011]; int calc(int a) { memset(dp, 0xc0, sizeof dp); dp[0] = 0; for (int i = 0, i_len = (N); i < i_len; ++i) { for (int j = 1; j < a; j++) { if (dp[i + j + 1] < dp[i] + j) { dp[i + j + 1] = dp[i] + j; prv[i + j + 1] = i; } } } return dp[N] - a + 1; } void query(vector<int> v) { printf( %d , (int)v.size()); for (int i = 0, i_len = (v.size()); i < i_len; ++i) printf( %d , v[i] + 1); printf( n ); fflush(stdout); for (__typeof((v).begin()) e = (v).begin(), e_end = (v).end(); e != e_end; ++e) cur[*e] = true; int x; scanf( %d , &x); x--; for (int i = 0, i_len = (v.size()); i < i_len; ++i) cur[(x + i) % N] = false; } void solve() { int ma = 0, a = 0; for (int b = 1; b < N; b++) { int tmp = calc(b); if (ma < tmp) { ma = tmp; a = b; } } if (ma == 0) { puts( 0 ); fflush(stdout); } else { calc(a); int x = N; memset(tar, 0, sizeof tar); memset(cur, 0, sizeof cur); while (x) { for (int k = prv[x]; k < x - 1; k++) tar[k] = true; x = prv[x]; } while (1) { vector<int> v; for (int i = 0, i_len = (N); i < i_len; ++i) if (tar[i] && !cur[i]) { v.push_back(i); } if ((int)v.size() <= a) { for (int i = 0, i_len = (N); i < i_len; ++i) if (tar[i] && cur[i]) { if ((int)v.size() == a) break; v.push_back(i); } query(v); break; } else { v.resize(a); query(v); } } puts( 0 ); fflush(stdout); } } void MAIN() { scanf( %d , &N); solve(); } int main() { int TC = 1; for (int tc = 0, tc_len = (TC); tc < tc_len; ++tc) MAIN(); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int n, k; cin >> n >> k; string s[n + 1]; set<string> ar; for (int x = 0; x < n; x++) { cin >> s[x]; ar.insert(s[x]); } char a[3] = { S , E , T }; long long int ans = 0; for (int x = 0; x < n; x++) { for (int y = x + 1; y < n; y++) { string d; for (int z = 0; z < k; z++) { if (s[x][z] == s[y][z]) { d += s[x][z]; } else { for (int i = 0; i < 3; i++) { if (a[i] != s[x][z] && a[i] != s[y][z]) { d += a[i]; break; } } } } if (d.length() != 0) if (ar.count(d)) ++ans; } } cout << ans / 3 << n ; } |
/*
* plle2_adv.v: Simulates the PLLE2_ADV pll of the xilinx 7 series. This is
* just a wrapper around the actual logic found in pll.v
* author: Till Mahlburg
* year: 2020
* organization: Universität Leipzig
* license: ISC
*
*/
`timescale 1 ns / 1 ps
/* A reference for the interface can be found in Xilinx UG953 page 503ff */
module PLLE2_ADV #(
/* not implemented */
parameter BANDWIDTH = "OPTIMIZED",
parameter CLKFBOUT_MULT = 5,
parameter CLKFBOUT_PHASE = 0.0,
/* are ignored, but need to be set */
parameter CLKIN1_PERIOD = 0.0,
parameter CLKIN2_PERIOD = 0.0,
parameter CLKOUT0_DIVIDE = 1,
parameter CLKOUT1_DIVIDE = 1,
parameter CLKOUT2_DIVIDE = 1,
parameter CLKOUT3_DIVIDE = 1,
parameter CLKOUT4_DIVIDE = 1,
parameter CLKOUT5_DIVIDE = 1,
parameter CLKOUT0_DUTY_CYCLE = 0.5,
parameter CLKOUT1_DUTY_CYCLE = 0.5,
parameter CLKOUT2_DUTY_CYCLE = 0.5,
parameter CLKOUT3_DUTY_CYCLE = 0.5,
parameter CLKOUT4_DUTY_CYCLE = 0.5,
parameter CLKOUT5_DUTY_CYCLE = 0.5,
parameter CLKOUT0_PHASE = 0.0,
parameter CLKOUT1_PHASE = 0.0,
parameter CLKOUT2_PHASE = 0.0,
parameter CLKOUT3_PHASE = 0.0,
parameter CLKOUT4_PHASE = 0.0,
parameter CLKOUT5_PHASE = 0.0,
parameter DIVCLK_DIVIDE = 1,
/* not implemented */
parameter REF_JITTER1 = 0.010,
parameter REF_JITTER2 = 0.010,
parameter STARTUP_WAIT = "FALSE",
parameter COMPENSATION = "ZHOLD",
/* Setting the FPGA model and speed grade allows a more realistic
* simulation. Default values are the most restrictive */
parameter FPGA_TYPE = "ARTIX",
parameter SPEED_GRADE = "-1")(
output CLKOUT0,
output CLKOUT1,
output CLKOUT2,
output CLKOUT3,
output CLKOUT4,
output CLKOUT5,
/* PLL feedback output. */
output CLKFBOUT,
output LOCKED,
input CLKIN1,
input CLKIN2,
/* Select input clk. 1 for CLKIN1, 0 for CLKIN2 */
input CLKINSEL,
/* PLL feedback input. Is ignored in this implementation, but should be connected to CLKFBOUT for internal feedback. */
input CLKFBIN,
/* Used to power down instatiated but unused PLLs */
input PWRDWN,
input RST,
/* Dynamic reconfiguration ports */
/* Address to write/read reconfiguration data to/from */
input [6:0] DADDR,
/* CLK to drive the reconfiguration */
input DCLK,
/* ENable the reconfiguration functionality */
input DEN,
/* Enable Write access on the given address */
input DWE,
/* What to write in the given ADDR */
input [15:0] DI,
/* Content of the given address */
output [15:0] DO,
/* Tells you, when the reconfiguration is done and ready for new inputs */
output DRDY);
pll #(
.BANDWIDTH(BANDWIDTH),
.CLKFBOUT_MULT_F(CLKFBOUT_MULT),
.CLKFBOUT_PHASE(CLKFBOUT_PHASE),
.CLKIN1_PERIOD(CLKIN1_PERIOD),
.CLKIN2_PERIOD(CLKIN2_PERIOD),
.CLKOUT0_DIVIDE_F(CLKOUT0_DIVIDE),
.CLKOUT1_DIVIDE(CLKOUT1_DIVIDE),
.CLKOUT2_DIVIDE(CLKOUT2_DIVIDE),
.CLKOUT3_DIVIDE(CLKOUT3_DIVIDE),
.CLKOUT4_DIVIDE(CLKOUT4_DIVIDE),
.CLKOUT5_DIVIDE(CLKOUT5_DIVIDE),
.CLKOUT0_DUTY_CYCLE(CLKOUT0_DUTY_CYCLE),
.CLKOUT1_DUTY_CYCLE(CLKOUT1_DUTY_CYCLE),
.CLKOUT2_DUTY_CYCLE(CLKOUT2_DUTY_CYCLE),
.CLKOUT3_DUTY_CYCLE(CLKOUT3_DUTY_CYCLE),
.CLKOUT4_DUTY_CYCLE(CLKOUT4_DUTY_CYCLE),
.CLKOUT5_DUTY_CYCLE(CLKOUT5_DUTY_CYCLE),
.CLKOUT0_PHASE(CLKOUT0_PHASE),
.CLKOUT1_PHASE(CLKOUT1_PHASE),
.CLKOUT2_PHASE(CLKOUT2_PHASE),
.CLKOUT3_PHASE(CLKOUT3_PHASE),
.CLKOUT4_PHASE(CLKOUT4_PHASE),
.CLKOUT5_PHASE(CLKOUT5_PHASE),
.DIVCLK_DIVIDE(DIVCLK_DIVIDE),
.REF_JITTER1(REF_JITTER1),
.REF_JITTER2(REF_JITTER2),
.STARTUP_WAIT(STARTUP_WAIT),
.COMPENSATION(COMPENSATION),
.MODULE_TYPE("PLLE2_ADV"),
.FPGA_TYPE(FPGA_TYPE),
.SPEED_GRADE(SPEED_GRADE))
plle2_adv (
.CLKOUT0(CLKOUT0),
.CLKOUT1(CLKOUT1),
.CLKOUT2(CLKOUT2),
.CLKOUT3(CLKOUT3),
.CLKOUT4(CLKOUT4),
.CLKOUT5(CLKOUT5),
.CLKFBOUT(CLKFBOUT),
.LOCKED(LOCKED),
.CLKIN1(CLKIN1),
.CLKIN2(CLKIN2),
.CLKINSEL(CLKINSEL),
.PWRDWN(PWRDWN),
.RST(RST),
.CLKFBIN(CLKFBIN),
.DADDR(DADDR),
.DCLK(DCLK),
.DEN(DEN),
.DWE(DWE),
.DI(DI),
.DO(DO),
.DRDY(DRDY)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__XOR3_PP_SYMBOL_V
`define SKY130_FD_SC_LS__XOR3_PP_SYMBOL_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__xor3 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__XOR3_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int N = 2e3 + 9; bool p[N][N]; priority_queue<pair<pair<int, int>, pair<int, int> > > q; int cu; int n, m, si, sj, ml, mr, a, b, ti, tj; char c; bool valid(int i, int j) { return i > 0 && i <= n && j > 0 && j <= m && p[i][j]; } void add(int x, int y, int i, int j) { p[i][j] = 0; ++cu; q.push({{x, y}, {i, j}}); } int main() { scanf( %d %d %d %d %d %d , &n, &m, &si, &sj, &mr, &ml); for (int i = 1; i <= n; ++i) for (int j = 1; j <= m; ++j) p[i][j] = ((cin >> c, c) == . ? true : false); add(0, 0, si, sj); auto cr = q.top(); while (!q.empty()) { cr = q.top(); a = -cr.first.first; b = -cr.first.second; ti = cr.second.first; tj = cr.second.second; q.pop(); if (valid(ti + 1, tj)) add(-a, -b, ti + 1, tj); if (valid(ti - 1, tj)) add(-a, -b, ti - 1, tj); if (valid(ti, tj + 1) && b + 1 <= ml) add(-a, -(b + 1), ti, tj + 1); if (valid(ti, tj - 1) && a + 1 <= mr) add(-(a + 1), -b, ti, tj - 1); } printf( %d n , cu); } |
#include <bits/stdc++.h> using namespace std; int main() { int n, d, m, i, a, b; cin >> n >> d >> m; for (i = 0; i < m; i++) { cin >> a >> b; if ((a - b + d) * (a - b - d) <= 0 && (a + b - d) * (a + b + d - 2 * n) <= 0) cout << YES << endl; else cout << NO << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A311O_2_V
`define SKY130_FD_SC_LS__A311O_2_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog wrapper for a311o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a311o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a311o_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a311o_2 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A311O_2_V
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin>>t; while(t--) { int x,y; cin>>x>>y; int count =0; while(x>0&&y>0) { x--; y--; count+=2; } if(x!=0||y!=0) count =count+2*max(x,y)-1; cout<<count<< n ; } } |
#include <bits/stdc++.h> using namespace std; int main() { long l; cin >> l; int div = 0; for (int i = 5; i < 1 + pow(l, 0.5); i++) { if (l % i == 0) { div = i; break; } } if (div == 0 || (l / div) < 5) { cout << -1 << endl; } else { char a[div][int(l / div)]; a[0][0] = a ; a[0][1] = e ; a[0][2] = i ; a[0][3] = o ; a[0][4] = u ; a[1][0] = e ; a[1][1] = i ; a[1][2] = o ; a[1][3] = u ; a[1][4] = a ; a[2][0] = i ; a[2][1] = o ; a[2][2] = u ; a[2][3] = a ; a[2][4] = e ; a[3][0] = o ; a[3][1] = u ; a[3][2] = a ; a[3][3] = e ; a[3][4] = i ; a[4][0] = u ; a[4][1] = a ; a[4][2] = e ; a[4][3] = i ; a[4][4] = o ; for (int i = 0; i < 5; i++) { for (int j = 5; j < (l / div); j++) { a[i][j] = a[i][j - 5]; } } for (int i = 5; i < div; i++) { for (int j = 0; j < (l / div); j++) { a[i][j] = a[i - 5][j]; } } for (int i = 0; i < div; i++) { for (int j = 0; j < (l / div); j++) { cout << a[i][j]; } } cout << endl; } } |
#include <bits/stdc++.h> using namespace std; long long x, y, n; long long arr[6]; int main() { ios_base::sync_with_stdio(0); cin >> x >> y >> n; int pos = (n - 1) % 6; arr[0] = (x + 1000000007) % 1000000007; arr[1] = (y + 1000000007) % 1000000007; arr[2] = (y - x + 1000000007 + 1000000007) % 1000000007; arr[3] = (-x + 1000000007) % 1000000007; arr[4] = (-y + 1000000007) % 1000000007; arr[5] = (x - y + 1000000007 + 1000000007) % 1000000007; cout << arr[pos] << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, k, T; long long doit(long long n, long long k) { if (n == 1) return k * (k + 1) / 2; long long tp = (n - 1) / k + 1, v1 = doit(tp, k), tp2 = (n - 1) % k + 1; long long f1 = (tp - 1) * (k * k + 1), f2 = v1 - f1; if (tp2 * k < f2) return (f1 * 2 + tp2 * 2 * k - k + 1) * k / 2; else if ((tp2 - 1) * k >= f2) return (f1 * 2 - k + 3 + tp2 * 2 * k) * k / 2; else return (f1 * 2 - k + 1 + tp2 * 2 * k) * k / 2 + tp2 * k - f2 + 1; } long long solve(long long n, long long k) { long long tp = (n - 1) / (k * k + 1) + 1, st = doit(tp, k); if (n == st) return tp * (k + 1); else return (n - tp + (n < st) - 1) / k + n - tp + (n < st); } int main() { scanf( %d , &T); while (T--) scanf( %lld%lld , &n, &k), printf( %lld n , solve(n, k)); } |
//---------------------------------------------------------------------------
//--clockGenerator.v---------------------------------------------------------
//--By Kyle Williams, 11/20/2012---------------------------------------------
//--PROJECT DESCRIPTION------------------------------------------------------
//----This module Acts as a crystal and influences prescion in timing--------
//This line is important in a Verilog simulation, because it sets up the time scale and
//operating precision for a module. It causes the unit delays to be in nanoseconds (ns) and
//the precision at which the simulator will round the events down to at 100 ps. This causes
//a #5 or #1 in a Verilog assignment to be a 5 ns or 1 ns delay respectively. The rounding
//of the events will be to .1ns or 100 pico seconds.
`timescale 1 ns / 100ps //time unit = 1ns; precision = 1/10 ns
module ClockGenerator(
output reg clock,
output reg reset
);
always begin
//10 MHz clock as defined in tb(50*1 ns*2) with 50% duty-cycle
#50 clock = ~clock;
//executes every 50 nanoseconds this causes a period of 100ns or frequency of
//if use 10 then will have a period of 20ns which is equivalent to 50 Mhz
//quick formula p = period 1/((p*2)*(10^(-9)))/1e6 = the frequency in Mhz
end
initial
begin
clock = 0;
reset = 1;
#20 reset = 0;//active high reset
end
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFXBP_SYMBOL_V
`define SKY130_FD_SC_HS__DFXBP_SYMBOL_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dfxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFXBP_SYMBOL_V
|
module lsu_transit_table(
in_wftag_resp,
in_wfid,
in_lddst_stsrc_addr,
in_exec_value,
in_gm_or_lds,
in_rd_en,
in_wr_en,
in_instr_pc,
out_exec_value,
out_gm_or_lds,
out_lddst_stsrc_addr,
out_reg_wr_en,
out_instr_pc,
clk,
rst
);
input [6:0] in_wftag_resp;
input [5:0] in_wfid;
input [11:0] in_lddst_stsrc_addr;
input [63:0] in_exec_value;
input in_gm_or_lds;
input [3:0] in_rd_en;
input [3:0] in_wr_en;
input [31:0] in_instr_pc;
output [63:0] out_exec_value;
output out_gm_or_lds;
output [11:0] out_lddst_stsrc_addr;
output [3:0] out_reg_wr_en;
output [31:0] out_instr_pc;
input clk;
input rst;
wire enable;
assign enable = |{in_rd_en,in_wr_en};
reg_40xX_1r_1w #(12) lddst_stsrc_addr(
.rd_addr(in_wftag_resp[6:1]),
.rd_data(out_lddst_stsrc_addr),
.wr_en(enable),
.wr_addr(in_wfid),
.wr_data(in_lddst_stsrc_addr),
.clk(clk),
.rst(rst)
);
reg_40xX_1r_1w #(64) exec_value(
.rd_addr(in_wftag_resp[6:1]),
.rd_data(out_exec_value),
.wr_en(enable),
.wr_addr(in_wfid),
.wr_data(in_exec_value),
.clk(clk),
.rst(rst)
);
reg_40xX_1r_1w #(1) gm_or_lds(
.rd_addr(in_wftag_resp[6:1]),
.rd_data(out_gm_or_lds),
.wr_en(enable),
.wr_addr(in_wfid),
.wr_data(in_gm_or_lds),
.clk(clk),
.rst(rst)
);
reg_40xX_1r_1w #(32) instr_pc(
.rd_addr(in_wftag_resp[6:1]),
.rd_data(out_instr_pc),
.wr_en(enable),
.wr_addr(in_wfid),
.wr_data(in_instr_pc),
.clk(clk),
.rst(rst)
);
reg_40xX_1r_1w #(4) register_wr_en(
.rd_addr(in_wftag_resp[6:1]),
//.rd_data(reg_wr_en),
.rd_data(out_reg_wr_en),
.wr_en(enable),
.wr_addr(in_wfid),
.wr_data(in_rd_en),
.clk(clk),
.rst(rst)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; struct Node { int v; int id; } node[110]; int t[110]; bool cmp(Node x, Node y) { return x.v > y.v; } int main() { int n, w; cin.sync_with_stdio(false); while (cin >> n >> w) { for (int i = 0; i < n; i++) { cin >> node[i].v; node[i].id = i; } bool flag = true; for (int i = 0; i < n; i++) { if (node[i].v & 1) t[i] = node[i].v / 2 + 1, w -= t[i]; else t[i] = node[i].v / 2, w -= t[i]; if (w < 0) { flag = false; printf( -1 n ); break; } } if (!flag) continue; sort(node, node + n, cmp); for (int i = 0; i < n; i++) { if (w > (node[i].v - t[node[i].id])) { int d = node[i].v - t[node[i].id]; t[node[i].id] = node[i].v; w = w - d; } else { t[node[i].id] += w; break; } } for (int i = 0; i < n - 1; i++) cout << t[i] << ; cout << t[n - 1] << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; using lint = long long; using ulint = unsigned long long; const int T = 10; lint dp[T], nxt[T]; void relax(lint &x, lint y) { x = max(x, y); } int main(void) { ios_base::sync_with_stdio(false); cin.tie(nullptr); fill(begin(dp), end(dp), -1); fill(begin(nxt), end(nxt), -1); int n; cin >> n; dp[0] = 0; while (n--) { int k; cin >> k; vector<lint> cards[4]; for (int i = 0; i < k; i++) { int c, d; cin >> c >> d; cards[c].push_back(d); } for (auto &vec : cards) { sort(vec.begin(), vec.end(), greater<lint>()); } for (int i = 0; i < T; i++) { if (dp[i] == -1) continue; bool flag1 = i + 1 >= T; bool flag2 = i + 2 >= T; bool flag3 = i + 3 >= T; relax(nxt[i], dp[i]); if (cards[1].size() >= 1) relax(nxt[(i + 1) % T], dp[i] + cards[1][0] * (flag1 + 1)); if (cards[2].size() >= 1) relax(nxt[(i + 1) % T], dp[i] + cards[2][0] * (flag1 + 1)); if (cards[3].size() >= 1) relax(nxt[(i + 1) % T], dp[i] + cards[3][0] * (flag1 + 1)); if (cards[1].size() >= 2) relax(nxt[(i + 2) % T], dp[i] + cards[1][0] * (flag2 + 1) + cards[1][1]); if (cards[1].size() >= 1 && cards[2].size() >= 1) relax(nxt[(i + 2) % T], dp[i] + cards[1][0] + cards[2][0] + max(cards[1][0], cards[2][0]) * flag2); if (cards[1].size() >= 3) relax(nxt[(i + 3) % T], dp[i] + cards[1][0] * (flag3 + 1) + cards[1][1] + cards[1][2]); } copy(begin(nxt), end(nxt), begin(dp)); } cout << *max_element(begin(dp), end(dp)) << endl; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 100010; int m, n, nword, R[MAXN], len[MAXN]; map<string, int> M; string s[MAXN]; vector<int> adj[MAXN], adj2[MAXN]; int super[MAXN], nsuper, number[MAXN], low[MAXN], cnt; int best[MAXN], rep[MAXN]; bool inStack[MAXN]; int st[MAXN], nst; int f[MAXN]; long long resR, resLen; void toLower(string& s) { for (int i = 0; i < s.size(); i++) { s[i] = tolower(s[i]); } } int countR(string s) { int ret = 0; for (int i = 0; i < s.size(); i++) { ret += s[i] == r ; } return ret; } void add(string& s) { toLower(s); if (M[s] == 0) M[s] = ++nword; int x = M[s]; len[x] = s.length(); R[x] = countR(s); } void input() { scanf( %d , &m); for (int i = 1; i <= m; i++) { cin >> s[i]; add(s[i]); } scanf( %d , &n); for (int i = 1; i <= n; i++) { string tmp; int u, v; cin >> tmp; add(tmp); u = M[tmp]; cin >> tmp; add(tmp); v = M[tmp]; adj[u].push_back(v); } } void tarjan(int u) { number[u] = ++cnt; low[u] = number[u]; inStack[u] = true; st[++nst] = u; for (int i = 0; i < adj[u].size(); i++) { int v = adj[u][i]; if (number[v] == 0) { tarjan(v); low[u] = min(low[u], low[v]); } else if (inStack[v]) low[u] = min(low[u], number[v]); } if (low[u] == number[u]) { nsuper++; best[nsuper] = u; super[u] = nsuper; inStack[u] = false; while (st[nst] != u) { int v = st[nst--]; super[v] = nsuper; inStack[v] = false; if (R[v] < R[best[nsuper]] || (R[v] == R[best[nsuper]] && len[v] < len[best[nsuper]])) best[nsuper] = v; } nst--; } } void dfs(int u) { f[u] = best[u]; for (int i = 0; i < adj2[u].size(); i++) { int v = adj2[u][i]; if (f[v] == 0) dfs(v); if (R[f[v]] < R[f[u]] || (R[f[v]] == R[f[u]] && len[f[v]] < len[f[u]])) f[u] = f[v]; } } void solve() { for (int i = 1; i <= nword; i++) { if (number[i] == 0) tarjan(i); } for (int i = 1; i <= nword; i++) { for (int j = 0; j < adj[i].size(); j++) { int v = adj[i][j]; if (super[i] != super[v]) adj2[super[i]].push_back(super[v]); } } for (int i = 1; i <= nword; i++) { if (f[i] == 0) dfs(i); } for (int i = 1; i <= m; i++) { int id = M[s[i]]; resR += R[f[super[id]]]; resLen += len[f[super[id]]]; } } void output() { printf( %I64d %I64d , resR, resLen); } int main() { input(); solve(); output(); } |
#include <bits/stdc++.h> using namespace std; int main() { long long n, k, s; while (cin >> n >> k >> s) { long long temp = (s / k); long long rem = s % k; temp++; if (((n - 1) * k < s || (k > s))) { cout << NO << endl; return 0; } cout << YES << endl; long long ans = 1; int flag = 0; for (int i = 1; i <= k; i++) { if (flag == 0 && rem == 0) { flag = 1; temp--; } else rem--; if (ans + temp <= n) { ans += temp; cout << ans << ; } else { ans -= temp; cout << ans << ; } } cout << endl; } } |
#include <bits/stdc++.h> using namespace std; int AbsDifference(int a, int b) { if (a >= b) return a - b; return b - a; } long long AbsDifference(long long a, long long b) { if (a >= b) return a - b; return b - a; } const int mod = 1000000007; const int mod2 = 1000000009; const int inf = 1 << 30; const long long infLL = 1ll << 62; const int impossible = -1; struct stoyan_point { int x, y; int id; }; struct stoyan_pointLL { long long x, y; int id; }; struct stoyan_segment { stoyan_point first, second; int lenght; bool type; int id; }; struct stoyan_segmentLL { stoyan_pointLL first, second; long long lenght; bool type; int id; }; string translate(int number, int lenght, int k) { string ans; while (number) { ans += char(( 1 ) + number & 1); number >>= 1; } reverse(ans.begin(), ans.end()); return ans; } vector<int> find_divisors(long long number) { vector<int> ans; int sq = sqrt(number), j; for (j = 1; j <= sq; j++) { if (number % j == 0) { ans.push_back(j); if (j * j != number) ans.push_back(number / j); } } sort(ans.begin(), ans.end()); return ans; } int cnt_divisors(long long number) { int ans = 0; int sq = sqrt(number), j; for (j = 1; j <= sq; j++) { if (number % j == 0) { ans++; if (j * j != number) ans++; } } return ans; } int n; string s; int x, y; int where_last = 0; int AnswerProblem; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; cin >> s; for (int i = 0; i < int(s.size()); i++) { if (s[i] == R ) x++; else y++; if (y > x) { if (where_last == -1) { AnswerProblem++; } where_last = 1; } if (y < x) { if (where_last == 1) { AnswerProblem++; } where_last = -1; } } cout << AnswerProblem << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND4BB_1_V
`define SKY130_FD_SC_LP__NAND4BB_1_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog wrapper for nand4bb with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand4bb_1 (
Y ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand4bb_1 (
Y ,
A_N,
B_N,
C ,
D
);
output Y ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND4BB_1_V
|
#include <bits/stdc++.h> struct vit { int price; char vit[4]; }; int main() { int i, n, min; scanf( %d , &n); struct vit t[n]; for (i = 0; i < n; i++) { scanf( %d %s , &t[i].price, t[i].vit); } int A = 300001, B = 300001, C = 300001, AB = 300001, AC = 300001, BC = 300001, ABC = 300001; for (i = 0; i < n; i++) { if (strcmp( A , t[i].vit) == 0) { if (A > t[i].price) A = t[i].price; } } for (i = 0; i < n; i++) { if (strcmp( B , t[i].vit) == 0) { if (B > t[i].price) B = t[i].price; } } for (i = 0; i < n; i++) { if (strcmp( C , t[i].vit) == 0) { if (C > t[i].price) C = t[i].price; } } for (i = 0; i < n; i++) { if ((strcmp( AB , t[i].vit) == 0) || (strcmp( BA , t[i].vit) == 0)) { if (AB > t[i].price) AB = t[i].price; } } for (i = 0; i < n; i++) { if ((strcmp( BC , t[i].vit) == 0) || (strcmp( CB , t[i].vit) == 0)) { if (BC > t[i].price) BC = t[i].price; } } for (i = 0; i < n; i++) { if ((strcmp( AC , t[i].vit) == 0) || (strcmp( CA , t[i].vit) == 0)) { if (AC > t[i].price) AC = t[i].price; } } for (i = 0; i < n; i++) { if ((strcmp( ABC , t[i].vit) == 0) || (strcmp( ACB , t[i].vit) == 0) || (strcmp( BAC , t[i].vit) == 0) || (strcmp( BCA , t[i].vit) == 0) || (strcmp( CAB , t[i].vit) == 0) || (strcmp( CBA , t[i].vit) == 0)) { if (ABC > t[i].price) ABC = t[i].price; } } min = ABC; if (A + B + C < min) min = A + B + C; if (AB + C < min) min = AB + C; if (BC + A < min) min = BC + A; if (AC + B < min) min = AC + B; if (AB + BC < min) min = AB + BC; if (AB + AC < min) min = AB + AC; if (BC + AC < min) min = BC + AC; if (min > 300000) { printf( -1 ); return 0; } printf( %d , min); return 0; } |
`define WIDTH_P 3
`define ELS_P 4
`define SEED_P 100
/**************************** TEST RATIONALE *******************************
1. STATE SPACE
All the elements are in memory are written once and the first $clog2(`ELS_P)
elements are re-written with w_v_i kept LOW to check if those elements are
overwritten.
2. PARAMETERIZATION
The synthesis of the design is not much influenced by data width WIDTH_P.
But the parameter ELS_P be varied to include different cases, powers of 2
and non power of 2 for example. SEED_P may be varied to generated different
streams of random numbers that are written to the test memory. So a minimum
set of tests might be WIDTH_P=1,4,5 and ELS_P=1,2,3,4,5,8.
***************************************************************************/
module test_bsg
#(
parameter cycle_time_p = 20,
parameter width_p = `WIDTH_P, // width of test input
parameter els_p = `ELS_P,
parameter addr_width_p = `BSG_SAFE_CLOG2(`ELS_P),
parameter seed_p = `SEED_P,
parameter reset_cycles_lo_p=1,
parameter reset_cycles_hi_p=5
);
// clock and reset generation
wire clk;
wire reset;
bsg_nonsynth_clock_gen #( .cycle_time_p(cycle_time_p)
) clock_gen
( .o(clk)
);
bsg_nonsynth_reset_gen #( .num_clocks_p (1)
, .reset_cycles_lo_p(reset_cycles_lo_p)
, .reset_cycles_hi_p(reset_cycles_hi_p)
) reset_gen
( .clk_i (clk)
, .async_reset_o(reset)
);
initial
begin
/*$monitor("\n@%0t ps: ", $time
, "test_input_wdata:%b || test_input_waddr:%b || test_input_wv:%b"
, test_input_wdata, test_input_waddr, test_input_wv
, " || test_input_raddr:%b || test_output_rdata:%b"
, test_input_raddr, test_output_rdata
);*/
$display("\n\n\n");
$display("===========================================================");
$display("testing bsg_mem_1r1w with ...");
$display("WIDTH_P: %d", width_p);
$display("ELS_P : %d\n", els_p);
end
logic [width_p-1:0] test_input_wdata, test_input_wdata_r;
logic [width_p-1:0] test_output_rdata;
logic [addr_width_p-1:0] test_input_waddr, test_input_raddr;
logic test_input_wv;
// stores some inputs
logic [addr_width_p-1:0] [width_p-1:0] test_inputs;
logic [addr_width_p:0] count;
logic finish_r;
bsg_cycle_counter #( .width_p (addr_width_p+1)
, .init_val_p(0)
) counter
( .clk_i (clk)
, .reset_i(reset)
, .ctr_r_o(count)
);
bsg_nonsynth_random_gen #( .width_p(width_p)
, .seed_p (seed_p)
) random_gen
( .clk_i (clk)
, .reset_i(reset)
, .yumi_i (1'b1)
, .data_o (test_input_wdata)
);
always_ff @(posedge clk)
begin
test_input_wdata_r <= test_input_wdata;
if(reset)
begin
test_input_waddr <= addr_width_p'(0);
test_input_raddr <= addr_width_p'(0);
test_input_wv <= 1'b1;
finish_r <= 1'b0;
end
else
begin
test_input_waddr <= (test_input_waddr + 1) % els_p;
test_input_raddr <= test_input_waddr;
if(count < (els_p - 1)) // entire mem. is written once
begin
if(count < addr_width_p)
// keeps track of initial addr_width_p values being written
test_inputs[test_input_waddr] <= test_input_wdata;
end
else
test_input_wv <= 1'b0; // w_v_i is tested in the next round
if(count == ((els_p - 1) + addr_width_p + 1))
finish_r <= 1'b1;
if(finish_r)
begin
$display("=========================================================\n");
$finish;
end
end
end
always_ff @(posedge clk)
begin
if(!reset)
if(count <= els_p)
// checks if data is not being written correctly
assert(test_output_rdata == test_input_wdata_r)
else $error("mismatch on reading the address: %x\n", test_input_raddr);
else
// checks if data is overwritten when w_v_i is asserted
if(addr_width_p > 1) // does not work with els_p=1 i.e., one mem. element
assert(test_output_rdata == test_inputs[test_input_raddr])
else $error("data may be overwritten when w_v_i is low at %x\n"
, test_input_raddr);
end
bsg_mem_1r1w #( .width_p (width_p)
, .els_p (els_p)
, .read_write_same_addr_p(1)
, .addr_width_p ()
) DUT
( .w_clk_i (clk)
, .w_reset_i(reset)
, .w_v_i (test_input_wv)
, .w_addr_i (test_input_waddr)
, .w_data_i (test_input_wdata)
, .r_v_i (1'b1)
, .r_addr_i (test_input_raddr)
, .r_data_o (test_output_rdata)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O2111A_FUNCTIONAL_V
`define SKY130_FD_SC_HD__O2111A_FUNCTIONAL_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__o2111a (
X ,
A1,
A2,
B1,
C1,
D1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X, B1, C1, or0_out, D1);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O2111A_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; long long n, m, k; long long cp1[102]; long long cp2[102]; long long dp[102][10002]; long long comb[102][102]; bool mark[102][10002]; long long Calculate_Pow(long long x, long long y) { long long val = 1; for (long long i = 1, t = x; i <= y; i <<= 1, t = (t * t) % 1000000007) if (y & i) val = (val * t) % 1000000007; return val; } void Calculate_Combination() { for (long long i = 0; i <= n; i++) comb[i][0] = 1; for (long long i = 1; i <= n; i++) for (long long j = 1; j <= i; j++) comb[i][j] = (comb[i - 1][j - 1] + comb[i - 1][j]) % 1000000007; } long long f(long long col, long long last) { if (last < 0) return 0; if (col == n && last) return 0; if (col == n) return 1; if (mark[col][last]) return dp[col][last]; mark[col][last] = true; if (col >= m % n) { for (long long i = 0; i <= n; i++) dp[col][last] = (dp[col][last] + cp1[i] * f(col + 1, last - i)) % 1000000007; } else { for (long long i = 0; i <= n; i++) dp[col][last] = (dp[col][last] + cp2[i] * f(col + 1, last - i)) % 1000000007; } return dp[col][last]; } int main() { scanf( %I64d%I64d%I64d , &n, &m, &k); Calculate_Combination(); for (long long i = 0; i <= n; i++) { cp1[i] = Calculate_Pow(comb[n][i], m / n); cp2[i] = Calculate_Pow(comb[n][i], m / n + 1); } printf( %I64d n , f(0, k)); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:09:18 10/03/2016
// Design Name:
// Module Name: sr_timer
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sr_timer #(TIME = 8)
(
input S,
input R,
input CLK,
output reg OUT = 0
);
reg [$clog2(TIME)-1:0] COUNTER = 0;
reg running = 0;
always @(posedge CLK) begin
if(R) begin
OUT <= 0;
COUNTER <= 0;
running <= 0;
end else if(S & !running) begin
OUT <= 1;
running <= 1;
end else if(running) begin
COUNTER <= COUNTER + 1;
if(COUNTER+1 == TIME) begin
running <= 0;
OUT <= 0;
COUNTER <= 0;
end
end
end
endmodule
module sr_timer_variable #(WIDTH = 8)
(
input S,
input R,
input CLK,
input [WIDTH-1:0] TIME,
output reg OUT = 0
);
reg [WIDTH-1:0] COUNTER = 0;
reg running = 0;
always @(posedge CLK) begin
if(R) begin
OUT <= 0;
COUNTER <= 0;
running <= 0;
end else if(S & !running) begin
OUT <= 1;
running <= 1;
end else if(running) begin
COUNTER <= COUNTER + 1;
if(COUNTER+1 == TIME) begin
running <= 0;
OUT <= 0;
COUNTER <= 0;
end
end
end
endmodule
|
`include "assert.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 4;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("i64.eq2.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
reg reset = 0;
wire [63:0] result;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("i64.eq2_tb.vcd");
$dumpvars(0, cpu_tb);
#24
`assert(result, 0);
`assert(result_empty, 0);
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, x[100005], h[100005]; cin >> n; for (int i = 0; i < n; ++i) cin >> x[i] >> h[i]; int count = 1; int newarr[100005]; newarr[1] = x[0] - h[0]; for (int i = 1; i < n - 1; ++i) { if ((x[i] - h[i] > x[i - 1]) && (x[i] - h[i] > newarr[count])) { count++; newarr[count] = x[i] - h[i]; } else if (x[i] + h[i] < x[i + 1]) { count++; newarr[count] = x[i] + h[i]; } else continue; } if (n == 1) puts( 1 ); else cout << count + 1 << endl; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CONB_BEHAVIORAL_V
`define SKY130_FD_SC_HD__CONB_BEHAVIORAL_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__conb (
HI,
LO
);
// Module ports
output HI;
output LO;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Name Output
pullup pullup0 (HI );
pulldown pulldown0 (LO );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__CONB_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_IO__TOP_GROUND_LVC_WPAD_PP_SYMBOL_V
`define SKY130_FD_IO__TOP_GROUND_LVC_WPAD_PP_SYMBOL_V
/**
* top_ground_lvc_wpad: Base ground I/O pad with low voltage clamp.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_io__top_ground_lvc_wpad (
//# {{data|Data Signals}}
inout G_PAD ,
//# {{control|Control Signals}}
inout AMUXBUS_A ,
inout AMUXBUS_B ,
//# {{power|Power}}
inout BDY2_B2B ,
inout G_CORE ,
inout VSWITCH ,
inout VCCD ,
inout VCCHIB ,
inout VDDA ,
inout VDDIO ,
inout VDDIO_Q ,
inout DRN_LVC1 ,
inout DRN_LVC2 ,
inout OGC_LVC ,
inout SRC_BDY_LVC1,
inout SRC_BDY_LVC2,
inout VSSA ,
inout VSSD ,
inout VSSIO ,
inout VSSIO_Q
);
endmodule
`default_nettype wire
`endif // SKY130_FD_IO__TOP_GROUND_LVC_WPAD_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; struct city { int x, y, p; double dis; } t[1010]; int cmp(city a, city b) { return a.dis < b.dis; } int main() { int s, n, i; while (scanf( %d%d , &n, &s) > 0) { for (i = 0; i < n; i++) { scanf( %d%d%d , &t[i].x, &t[i].y, &t[i].p); t[i].dis = sqrt(t[i].x * t[i].x + t[i].y * t[i].y); } sort(t, t + n, cmp); double ans; for (i = 0; i < n; i++) { s += t[i].p; if (s >= 1e6) { ans = t[i].dis; break; } } if (i == n) { printf( -1 n ); continue; } printf( %lf n , ans); } return 0; } |
#include <bits/stdc++.h> using namespace std; const double eps = 1e-10; const int inf = 0x3f3f3f3f; const long long INF = 1e18; const int maxn = 200000 + 10; const int maxm = 1000000000 + 7; const int mod = 1000000000 + 7; int gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } inline long long read() { char ch = getchar(); long long x = 0, f = 1; while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while ( 0 <= ch && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } int n, m; long long a[maxn]; long long num[maxn]; int main() { int T = read(); while (T--) { n = read(); for (int i = 1; i <= n; ++i) a[i] = read(), num[i] = 0; m = read(); for (int i = 1; i <= m; ++i) { long long x = read(), y = read(); num[y] = max(num[y], x); } for (int i = n - 1; i >= 1; --i) { num[i] = max(num[i], num[i + 1]); } bool ok = true; int ans = 1; int pos = 1; long long maxx = 0; for (int i = 1; i <= n; ++i) { maxx = max(maxx, a[i]); int len = i - pos + 1; if (num[len] < maxx) { ans++; pos = i; maxx = a[i]; } if (num[1] < a[i]) ok = false; } if (ok) printf( %d n , ans); else puts( -1 ); } } |
#include <bits/stdc++.h> using namespace std; struct scroll { int pow; int dmg; int loc; bool operator<(const scroll& a) const { if (dmg > a.dmg) return true; else if (dmg == a.dmg && pow < a.pow) return true; else return false; } }; struct used_scrollr { int num; int time; bool operator<(const used_scrollr& a) const { return time < a.time; } }; int main() { int N, max, reg; scanf( %d%d%d , &N, &max, ®); scroll ary[N]; bool used_scroll[N]; int used_time[N]; for (int i = 0; i < N; ++i) { int x, y; scanf( %d%d , &x, &y); ary[i] = (scroll){x, y, i + 1}; used_scroll[i] = false; } sort(ary, ary + N); int time = 0; int used_scrolls = 0; int current_hp = max; int drain = 0; while (true) { current_hp -= drain; if (current_hp + reg < max) current_hp += reg; else current_hp = max; if (current_hp <= 0) { time++; break; } bool used_a_scroll = false; for (int i = 0; i < N; ++i) { if (used_scroll[i] == false && (((current_hp * 100) / max) + ((current_hp * 100) % max == 0 ? 0 : 1) <= ary[i].pow)) { used_time[i] = time; drain += ary[i].dmg; used_scroll[i] = true; used_scrolls++; used_a_scroll = true; break; } } if ((reg - drain) >= 0 && used_a_scroll == false) break; time++; } if (current_hp <= 0) { printf( YES n ); printf( %d %d n , time - 1, used_scrolls); used_scrollr ary2[used_scrolls]; int cnt = 0; for (int i = 0; i < N; ++i) if (used_scroll[i]) ary2[cnt++] = (used_scrollr){ary[i].loc, used_time[i]}; sort(ary2, ary2 + used_scrolls); for (int i = 0; i < used_scrolls; ++i) printf( %d %d n , ary2[i].time, ary2[i].num); } else { printf( NO n ); } } |
#include <bits/stdc++.h> using namespace std; int n, m, mr; vector<string> v; string s, s2, tmp, res; vector<pair<int, int> > e; int main() { cin >> n >> m; for (int i = 0; i < n; i++) { cin >> s; v.push_back(s); } sort(v.begin(), v.end()); for (int i = 0; i < m; i++) { cin >> s >> s2; int a; for (a = 0; a < n; a++) if (v[a] == s) break; int b; for (b = 0; b < n; b++) if (v[b] == s2) break; e.push_back(make_pair(a, b)); } int mx = (int)pow(2.0, n); for (int x = mx - 1; x > 0; x--) { bool f = true; for (int i = 0; i < e.size(); i++) { int e1 = n - e[i].first - 1, e2 = n - e[i].second - 1; if ((x >> e1 & 1) && (x >> e2 & 1)) f = false; } if (f) { int amx = mx; int r = 0; for (int o = 0; o < n; o++) { if (x & (mx >> 1)) r++; mx /= 2; } mx = amx; tmp = ; for (int o = 0; o < n; o++) { if (x & (mx >> 1)) tmp += v[o] + n ; mx /= 2; } mx = amx; if (r > mr) res = tmp, mr = r; } } cout << mr << endl; cout << res; return 0; } |
/* This file is part of jt51.
jt51 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
jt51 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with jt51. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: March, 7th 2017
*/
`timescale 1ns / 1ps
module jt51_fir
#(parameter data_width=9, output_width=12, coeff_width=9,
addr_width=7, stages=81, acc_extra=1)
(
input clk,
input rst,
input sample,
input signed [data_width-1:0] left_in,
input signed [data_width-1:0] right_in,
input signed [coeff_width-1:0] coeff,
output reg [addr_width-1:0] cnt,
output reg signed [output_width-1:0] left_out,
output reg signed [output_width-1:0] right_out,
output reg sample_out
);
wire signed [data_width-1:0] mem_left, mem_right;
// pointers
reg [addr_width-1:0] addr_left, addr_right,
forward, rev, in_pointer;
reg update, last_sample;
reg [1:0] state;
parameter IDLE=2'b00, LEFT=2'b01, RIGHT=2'b10;
jt51_fir_ram #(.data_width(data_width),.addr_width(addr_width)) chain_left(
.clk ( clk ),
.data ( left_in ),
.addr ( addr_left ),
.we ( update ),
.q ( mem_left )
);
jt51_fir_ram #(.data_width(data_width),.addr_width(addr_width)) chain_right(
.clk ( clk ),
.data ( right_in ),
.addr ( addr_right),
.we ( update ),
.q ( mem_right)
);
always @(posedge clk)
if( rst )
{ update, last_sample } <= 2'b00;
else begin
last_sample <= sample;
update <= sample && !last_sample;
end
parameter mac_width=(data_width+1)+coeff_width;
parameter acc_width=output_width; // mac_width+3;
reg signed [acc_width-1:0] acc_left, acc_right;
//integer acc,mac;
wire [addr_width-1:0] next = cnt+1'b1;
reg signed [data_width:0] sum;
wire last_stage = cnt==(stages-1)/2;
reg signed [data_width-1:0] buffer_left, buffer_right;
always @(*) begin
if( state==LEFT) begin
if( last_stage )
sum = buffer_left;
else
sum = buffer_left + mem_left;
end
else begin
if( last_stage )
sum = buffer_right;
else
sum = buffer_right + mem_right;
end
end
wire signed [mac_width-1:0] mac = coeff*sum;
wire signed [acc_width-1:0] mac_trim = mac[mac_width-1:mac_width-acc_width];
//wire signed [acc_width-1:0] mac_trimx = (coeff*sum)>>>(mac_width-acc_width);
wire [addr_width-1:0]
in_pointer_next = in_pointer - 1'b1,
forward_next = forward+1'b1,
rev_next = rev-1'b1;
always @(*) begin
case( state )
default: begin
addr_left = update ? rev : in_pointer;
addr_right= in_pointer;
end
LEFT: begin
addr_left = forward_next;
addr_right= rev;
end
RIGHT: begin
if( cnt==(stages-1)/2 ) begin
addr_left = in_pointer_next;
addr_right= in_pointer_next;
end
else begin
addr_left = rev_next;
addr_right= forward;
end
end
endcase
end
always @(posedge clk)
if( rst ) begin
sample_out <= 1'b0;
state <= IDLE;
in_pointer <= 7'd0;
//addr_left <= in_pointer;
//addr_right<= in_pointer;
end else begin
case(state)
default: begin
if( update ) begin
state <= LEFT;
buffer_left <= left_in;
//addr_left <= rev;
end
cnt <= 6'd0;
acc_left <= {acc_width{1'b0}};
acc_right <= {acc_width{1'b0}};
rev <= in_pointer+stages-1'b1;
forward <= in_pointer;
sample_out <= 1'b0;
end
LEFT: begin
acc_left <= acc_left + mac_trim;
//addr_left <= forward_next;
buffer_right <= mem_right;
//addr_right <= rev;
forward<=forward_next;
state <= RIGHT;
end
RIGHT:
if( cnt==(stages-1)/2 ) begin
left_out <= acc_left;
right_out <= acc_right + mac_trim;
sample_out <= 1'b1;
in_pointer <= in_pointer_next;
//addr_left <= in_pointer_next;
//addr_right<= in_pointer_next;
state <= IDLE;
end else begin
acc_right <= acc_right + mac_trim;
//addr_right <= forward;
buffer_left <= mem_left;
//addr_left <= rev_next;
cnt<=next;
rev<=rev-1'b1;
state <= LEFT;
end
endcase
end
endmodule // jt51_fir8 |
#include <bits/stdc++.h> using namespace std; long long ll, tt, i, j, a[234567], b[211212], c[211456], d[213456]; long long x, m, n, r, s, t, k, l, y, z; vector<long long> p[12], q; pair<long long, long long> pp[345678]; int main() { cin >> n; for (i = 1; i <= n; i++) { cin >> x; if (x == 1) { a[i]++; } else { b[i]++; } a[i] += a[i - 1]; b[i] += b[i - 1]; } for (t = 1; t <= n; t++) { x = 0; y = 0; l = 0; r = 0; z = 0; do { x = lower_bound(a + z + 1, a + n + 1, a[z] + t) - a; y = lower_bound(b + z + 1, b + n + 1, b[z] + t) - b; if (x < y) { l++; z = x; } else { r++; z = y; } } while (x + y <= 2 * n); if (z == n && l != r) { if (x == n && l < r) continue; if (y == n && l > r) continue; pp[s].first = max(l, r); pp[s].second = t; s++; } } sort(pp, pp + s); cout << s << endl; for (i = 0; i < s; i++) cout << pp[i].first << << pp[i].second << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; vector<int> temp(100005); vector<int> v(100005); int fn(int l, int h, int x) { while (h - l > 1) { int mid = (h + l) / 2; if (temp[mid] >= x) { h = mid; } else { l = mid; } } if (temp[h] > x) return h; else return l; } int main() { ios_base::sync_with_stdio(false); int n; cin >> n; for (int i = 0; i < n; i++) { cin >> v[i]; } int len = 1; temp[0] = v[0]; for (int i = 1; i < n; i++) { if (temp[0] > v[i]) { temp[0] = v[i]; } else if (v[i] > temp[len - 1]) { temp[len] = v[i]; len++; } else { int index = fn(0, len - 1, v[i]); temp[index] = v[i]; } } cout << len; } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: dram_ctl_pad.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module dram_ctl_pad(/*AUTOARG*/
// Outputs
ctl_pad_clk_so, bso,
// Inouts
pad,
// Inputs
vrefcode, vdd_h, update_dr, testmode_l, shift_dr, rst_l,
mode_ctrl, hiz_n, data, ctl_pad_clk_si, ctl_pad_clk_se, clock_dr,
clk, cbu, cbd, bsi
);
//////////////////////////////////////////////////////////////////////////
// INPUTS
//////////////////////////////////////////////////////////////////////////
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input bsi; // To sstl_pad of dram_sstl_pad.v
input [8:1] cbd; // To sstl_pad of dram_sstl_pad.v
input [8:1] cbu; // To sstl_pad of dram_sstl_pad.v
input clk; // To ctl_edgelogic of dram_ctl_edgelogic.v
input clock_dr; // To sstl_pad of dram_sstl_pad.v
input ctl_pad_clk_se; // To ctl_edgelogic of dram_ctl_edgelogic.v
input ctl_pad_clk_si; // To ctl_edgelogic of dram_ctl_edgelogic.v
input data; // To ctl_edgelogic of dram_ctl_edgelogic.v
input hiz_n; // To sstl_pad of dram_sstl_pad.v
input mode_ctrl; // To sstl_pad of dram_sstl_pad.v
input rst_l; // To ctl_edgelogic of dram_ctl_edgelogic.v
input shift_dr; // To sstl_pad of dram_sstl_pad.v
input testmode_l; // To ctl_edgelogic of dram_ctl_edgelogic.v
input update_dr; // To sstl_pad of dram_sstl_pad.v
input vdd_h; // To sstl_pad of dram_sstl_pad.v
input [7:0] vrefcode; // To sstl_pad of dram_sstl_pad.v
// End of automatics
//////////////////////////////////////////////////////////////////////////
// INOUTPUTS
//////////////////////////////////////////////////////////////////////////
inout pad;
//////////////////////////////////////////////////////////////////////////
// OUTPUTS
//////////////////////////////////////////////////////////////////////////
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output bso; // From sstl_pad of dram_sstl_pad.v
output ctl_pad_clk_so; // From ctl_edgelogic of dram_ctl_edgelogic.v
// End of automatics
//////////////////////////////////////////////////////////////////////////
// CODE
//////////////////////////////////////////////////////////////////////////
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire to_pad; // From ctl_edgelogic of dram_ctl_edgelogic.v
// End of automatics
// INSTANTIATING PAD LOGIC
dram_ctl_edgelogic ctl_edgelogic(/*AUTOINST*/
// Outputs
.ctl_pad_clk_so(ctl_pad_clk_so),
.to_pad(to_pad),
// Inputs
.clk (clk),
.rst_l (rst_l),
.testmode_l(testmode_l),
.ctl_pad_clk_se(ctl_pad_clk_se),
.ctl_pad_clk_si(ctl_pad_clk_si),
.data (data));
// SSTL LOGIC
/*dram_sstl_pad AUTO_TEMPLATE(
.pad (pad),
.oe (1'b1),
.to_core (),
.odt_enable_mask (1'b1),
.data_in (to_pad));
*/
dram_sstl_pad sstl_pad(/*AUTOINST*/
// Outputs
.bso (bso),
.to_core (), // Templated
// Inouts
.pad (pad), // Templated
// Inputs
.bsi (bsi),
.cbd (cbd[8:1]),
.cbu (cbu[8:1]),
.clock_dr (clock_dr),
.data_in (to_pad), // Templated
.hiz_n (hiz_n),
.mode_ctrl (mode_ctrl),
.odt_enable_mask (1'b1), // Templated
.oe (1'b1), // Templated
.shift_dr (shift_dr),
.update_dr (update_dr),
.vdd_h (vdd_h),
.vrefcode (vrefcode[7:0]));
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "usb_system_onchip_memory2_0.hex";
output [ 31: 0] readdata;
input [ 12: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [ 31: 0] writedata;
wire clocken0;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 8192,
the_altsyncram.numwords_a = 8192,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 13;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, k, p, x, y; cin >> n >> k >> p >> x >> y; long long int sum = 0; long long int cov = 0; for (int i = 0; i < k; i++) { long long int kk; cin >> kk; if (kk < y) cov++; sum += kk; } int used = k; int remain; if (cov > (n / 2)) { cout << -1 ; return 0; } else { remain = (n / 2) - cov; if (remain > n - k) remain = n - k; sum += remain; used += remain; } int finalre = n - used; if (sum + finalre * y <= x) { for (int i = 0; i < remain; i++) cout << 1 << ; for (int i = 0; i < finalre; i++) cout << y << ; } else cout << -1 << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRSDFXTP_TB_V
`define SKY130_FD_SC_LP__SRSDFXTP_TB_V
/**
* srsdfxtp: Scan flop with sleep mode, non-inverted clock,
* single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__srsdfxtp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg SLEEP_B;
reg KAPWR;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
KAPWR = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 KAPWR = 1'b0;
#60 SCD = 1'b0;
#80 SCE = 1'b0;
#100 SLEEP_B = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 D = 1'b1;
#220 KAPWR = 1'b1;
#240 SCD = 1'b1;
#260 SCE = 1'b1;
#280 SLEEP_B = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 D = 1'b0;
#400 KAPWR = 1'b0;
#420 SCD = 1'b0;
#440 SCE = 1'b0;
#460 SLEEP_B = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 SLEEP_B = 1'b1;
#660 SCE = 1'b1;
#680 SCD = 1'b1;
#700 KAPWR = 1'b1;
#720 D = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 SLEEP_B = 1'bx;
#840 SCE = 1'bx;
#860 SCD = 1'bx;
#880 KAPWR = 1'bx;
#900 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_lp__srsdfxtp dut (.D(D), .SCD(SCD), .SCE(SCE), .SLEEP_B(SLEEP_B), .KAPWR(KAPWR), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRSDFXTP_TB_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2021 Yutetsu TAKATSUKASA.
// SPDX-License-Identifier: CC0-1.0
import "DPI-C" context function int import_func0();
import "DPI-C" context function int import_func1();
import "DPI-C" context function int import_func2();
import "DPI-C" context function int import_func3();
import "DPI-C" context function int import_func4();
module t(/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
wire [31:0] i = crc[31:0];
wire out;
Test test(
// Outputs
.out (out),
// Inputs
.clk (clk),
.i (i[31:0]));
wire [63:0] result = {63'b0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc == 0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= '0;
end
else if (cyc < 10) begin
sum <= '0;
end
else if (cyc == 99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (import_func1() != 1) $stop; // this must be the first call
if (import_func3() != 1) $stop; // this must be the first call
if (import_func4() < 95) $stop; // expected to return around 100
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h162c58b1635b8d6e
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test(/*AUTOARG*/
// Outputs
out,
// Inputs
clk, i
);
input clk;
input [31:0] i;
output wire out;
logic [2:0] tmp;
assign out = ^tmp;
always_ff @(posedge clk) begin
// Note that import_func?() always returns positive integer,
// so '|(import_func?())' is always 1'b1
tmp[0] <= |(import_func0()) || |(import_func1()); // import_fnc1 must not be called
tmp[1] <= !(|(import_func2())) && |(import_func3()); // import_fnc3 must not be called
tmp[2] <= ^(0 * import_func4()); // import_func1 has side effect, so must be executed anyway.
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDLCLKP_1_V
`define SKY130_FD_SC_HVL__SDLCLKP_1_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog wrapper for sdlclkp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__sdlclkp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__sdlclkp_1 (
GCLK,
SCE ,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__sdlclkp base (
.GCLK(GCLK),
.SCE(SCE),
.GATE(GATE),
.CLK(CLK),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__sdlclkp_1 (
GCLK,
SCE ,
GATE,
CLK
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__sdlclkp base (
.GCLK(GCLK),
.SCE(SCE),
.GATE(GATE),
.CLK(CLK)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDLCLKP_1_V
|
#include <bits/stdc++.h> using namespace std; vector<int> H; vector<int> L; int a[200001]; bool vis[200001]; int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); } bool T = 0; for (int i = 1; i <= n;) { bool faH = 0, faL = 0; int tailH = H.size() - 1, tailL = L.size() - 1; if (H.size() == 0) faH = 1; else if (H[tailH] < a[i]) faH = 1; if (L.size() == 0) faL = 1; else if (L[tailL] > a[i]) faL = 1; if (faH == 0 && faL == 0) { T = 1; break; } if (faH == 0 && faL == 1) { L.push_back(a[i]); vis[i] = 1; i++; } if (faH == 1 && faL == 0) { H.push_back(a[i]); vis[i] = 0; i++; } if (faH == 1 && faL == 1) { if (a[i] < a[i + 1]) { H.push_back(a[i]); vis[i] = 0; i++; } else if (a[i] > a[i + 1]) { L.push_back(a[i]); vis[i] = 1; i++; } else { H.push_back(a[i]); L.push_back(a[i + 1]); vis[i] = 0; vis[i + 1] = 1; i += 2; } } } if (T) puts( NO ); else { puts( YES ); for (int i = 1; i <= n; i++) { printf( %d , vis[i]); } } } |
#include <bits/stdc++.h> int** arr; std::vector<int> opers; void del3(int x, int y) { if (arr[x][y] && arr[x + 1][y] && arr[x][y + 1]) { opers.push_back(x + 1); opers.push_back(y + 1); opers.push_back(x + 2); opers.push_back(y + 1); opers.push_back(x + 1); opers.push_back(y + 2); arr[x][y] = 0; arr[x + 1][y] = 0; arr[x][y + 1] = 0; } else if (arr[x][y] && arr[x + 1][y] && arr[x + 1][y + 1]) { opers.push_back(x + 1); opers.push_back(y + 1); opers.push_back(x + 2); opers.push_back(y + 1); opers.push_back(x + 2); opers.push_back(y + 2); arr[x][y] = 0; arr[x + 1][y] = 0; arr[x + 1][y + 1] = 0; } else if (arr[x][y + 1] == 1 && arr[x + 1][y] && arr[x + 1][y + 1]) { opers.push_back(x + 1); opers.push_back(y + 2); opers.push_back(x + 2); opers.push_back(y + 1); opers.push_back(x + 2); opers.push_back(y + 2); arr[x][y + 1] = 0; arr[x + 1][y] = 0; arr[x + 1][y + 1] = 0; } else if (arr[x][y] == 1 && arr[x][y + 1] && arr[x + 1][y + 1]) { opers.push_back(x + 1); opers.push_back(y + 1); opers.push_back(x + 1); opers.push_back(y + 2); opers.push_back(x + 2); opers.push_back(y + 2); arr[x][y] = 0; arr[x][y + 1] = 0; arr[x + 1][y + 1] = 0; } } void del2(int x, int y) { bool fl = false; if (arr[x][y] == 0) { opers.push_back(x + 1); opers.push_back(y + 1); arr[x][y] = 1; } else { if (!fl) { opers.push_back(x + 1); opers.push_back(y + 1); arr[x][y] = 0; fl = true; } } if (arr[x + 1][y] == 0) { opers.push_back(x + 2); opers.push_back(y + 1); arr[x + 1][y] = 1; } else { if (!fl) { opers.push_back(x + 2); opers.push_back(y + 1); fl = true; arr[x + 1][y] = 0; } } if (arr[x][y + 1] == 0) { opers.push_back(x + 1); opers.push_back(y + 2); arr[x][y + 1] = 1; } else { if (!fl) { opers.push_back(x + 1); opers.push_back(y + 2); arr[x][y + 1] = 0; fl = true; } } if (arr[x + 1][y + 1] == 0) { opers.push_back(x + 2); opers.push_back(y + 2); arr[x + 1][y + 1] = 1; } else { if (!fl) { opers.push_back(x + 2); opers.push_back(y + 2); arr[x + 1][y + 1] = 0; fl = true; } } del3(x, y); } void del1(int x, int y) { int h = 0; if (arr[x][y] == 1) { opers.push_back(x + 1); opers.push_back(y + 1); arr[x][y] = 0; } else { if (h < 2) { opers.push_back(x + 1); opers.push_back(y + 1); arr[x][y] = 1; h++; } } if (arr[x + 1][y] == 1) { opers.push_back(x + 2); opers.push_back(y + 1); arr[x + 1][y] = 0; } else { if (h < 2) { opers.push_back(x + 2); opers.push_back(y + 1); arr[x + 1][y] = 1; h++; } } if (arr[x][y + 1] == 1) { opers.push_back(x + 1); opers.push_back(y + 2); arr[x][y + 1] = 0; } else { if (h < 2) { opers.push_back(x + 1); opers.push_back(y + 2); arr[x][y + 1] = 1; h++; } } if (arr[x + 1][y + 1] == 1) { opers.push_back(x + 2); opers.push_back(y + 2); arr[x + 1][y + 1] = 0; } else { if (h < 2) { opers.push_back(x + 2); opers.push_back(y + 2); arr[x + 1][y + 1] = 1; h++; } } del2(x, y); } void setup(int x, int y) { int iu = arr[x][y] + arr[x][y + 1] + arr[x + 1][y] + arr[x + 1][y + 1]; if (iu == 3) { del3(x, y); } else if (iu == 2) { del2(x, y); } else if (iu == 1) { del1(x, y); } else if (iu == 4) { del3(x, y); del1(x, y); } arr[x][y] = 0; arr[x][y + 1] = 0; arr[x + 1][y] = 0; arr[x + 1][y + 1] = 0; } int main() { int t; std::cin >> t; for (int i = 0; i < t; i++) { int n, m; std::cin >> n >> m; arr = new int*[n]; for (int i = 0; i < n; i++) arr[i] = new int[m]; for (int i = 0; i < n; i++) { std::string s; std::cin >> s; for (int j = 0; j < s.size(); j++) { arr[i][j] = s[j] - 0 ; } } for (int a = 0; a < n - 1; a++) { for (int b = 0; b < m - 1; b++) { setup(a, b); } } std::cout << opers.size() / 6 << n ; for (int i = 0; i < opers.size() / 6; i++) { for (int j = 0; j < 6; j++) { std::cout << opers[i * 6 + j] << ; } std::cout << n ; } opers.clear(); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { string p; cin >> p; int n; cin >> n; bool a = false, b = false; while (n--) { string s; cin >> s; if (s == p) { a = true; b = true; } if (s[0] == p[1]) a = true; if (s[1] == p[0]) b = true; } if (a && b) cout << YES ; else cout << NO ; return 0; } |
#include <bits/stdc++.h> using namespace std; int C[200005], A[200005], n, k, i, j, mx; int main() { scanf( %d%d%d , &n, &i, &k); for (i = 1; i <= n; i++) scanf( %d , &A[i]); for (i = j = 1; i <= n; i++) { while (j - i + 1 - C[A[i]] - (A[j] == A[i]) <= k && j <= n) { C[A[j]]++; j++; } if (j - i - C[A[i]]-- <= n) mx = max(mx, C[A[i]] + 1); } printf( %d , mx); return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1000010; const int s = 1000000; int n; int b[maxn]; int p[maxn]; int c[maxn]; vector<int> ans; int main() { scanf( %d , &n); int t; for (int i = 0; i < n; ++i) { scanf( %d , &t); b[t] = 1; p[i] = t; } int l = 1; for (int i = 0; i < n; ++i) { if (c[p[i]] == 0) { if (b[s - p[i] + 1] == 0) { ans.push_back(s - p[i] + 1); b[s - p[i] + 1] = 1; } else { while (b[l] || b[s - l + 1]) { l++; } ans.push_back(l); b[l] = 1; ans.push_back(s - l + 1); b[s - l + 1] = 1; c[s - p[i] + 1] = 1; } } } printf( %ld n , ans.size()); for (int i = 0; i < ans.size(); ++i) { if (i) printf( ); printf( %d , ans[i]); } printf( n ); return 0; } |
/*
* PicoSoC - A simple example SoC using PicoRV32
*
* Copyright (C) 2017 Clifford Wolf <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
`default_nettype wire
module simpleuart (
input clk,
input resetn,
output ser_tx,
input ser_rx,
input [3:0] reg_div_we,
input [31:0] reg_div_di,
output [31:0] reg_div_do,
input reg_dat_we,
input reg_dat_re,
input [31:0] reg_dat_di,
output [31:0] reg_dat_do,
output reg_dat_wait
);
reg [31:0] cfg_divider;
reg [3:0] recv_state;
reg [31:0] recv_divcnt;
reg [7:0] recv_pattern;
reg [7:0] recv_buf_data;
reg recv_buf_valid;
reg [9:0] send_pattern;
reg [3:0] send_bitcnt;
reg [31:0] send_divcnt;
reg send_dummy;
assign reg_div_do = cfg_divider;
assign reg_dat_wait = reg_dat_we && (send_bitcnt || send_dummy);
assign reg_dat_do = recv_buf_valid ? recv_buf_data : ~0;
always @(posedge clk) begin
if (!resetn) begin
cfg_divider <= 1;
end else begin
if (reg_div_we[0]) cfg_divider[ 7: 0] <= reg_div_di[ 7: 0];
if (reg_div_we[1]) cfg_divider[15: 8] <= reg_div_di[15: 8];
if (reg_div_we[2]) cfg_divider[23:16] <= reg_div_di[23:16];
if (reg_div_we[3]) cfg_divider[31:24] <= reg_div_di[31:24];
end
end
always @(posedge clk) begin
if (!resetn) begin
recv_state <= 0;
recv_divcnt <= 0;
recv_pattern <= 0;
recv_buf_data <= 0;
recv_buf_valid <= 0;
end else begin
recv_divcnt <= recv_divcnt + 1;
if (reg_dat_re)
recv_buf_valid <= 0;
case (recv_state)
0: begin
if (!ser_rx)
recv_state <= 1;
recv_divcnt <= 0;
end
1: begin
if (2*recv_divcnt > cfg_divider) begin
recv_state <= 2;
recv_divcnt <= 0;
end
end
10: begin
if (recv_divcnt > cfg_divider) begin
recv_buf_data <= recv_pattern;
recv_buf_valid <= 1;
recv_state <= 0;
end
end
default: begin
if (recv_divcnt > cfg_divider) begin
recv_pattern <= {ser_rx, recv_pattern[7:1]};
recv_state <= recv_state + 1;
recv_divcnt <= 0;
end
end
endcase
end
end
assign ser_tx = send_pattern[0];
always @(posedge clk) begin
if (reg_div_we)
send_dummy <= 1;
send_divcnt <= send_divcnt + 1;
if (!resetn) begin
send_pattern <= ~0;
send_bitcnt <= 0;
send_divcnt <= 0;
send_dummy <= 1;
end else begin
if (send_dummy && !send_bitcnt) begin
send_pattern <= ~0;
send_bitcnt <= 15;
send_divcnt <= 0;
send_dummy <= 0;
end else
if (reg_dat_we && !send_bitcnt) begin
send_pattern <= {1'b1, reg_dat_di[7:0], 1'b0};
send_bitcnt <= 10;
send_divcnt <= 0;
end else
if (send_divcnt > cfg_divider && send_bitcnt) begin
send_pattern <= {1'b1, send_pattern[9:1]};
send_bitcnt <= send_bitcnt - 1;
send_divcnt <= 0;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m; int a[1010][1010]; bool got[1010][1010]; bool ok(int x) { memset(got, 0, sizeof(got)); for (int j = 0; j < m; j++) { vector<int> vt; for (int i = 0; i < n; i++) if (a[i][j] >= x) vt.push_back(i); for (int o = 0; o < vt.size(); o++) for (int p = o + 1; p < vt.size(); p++) if (got[vt[o]][vt[p]]) return true; else got[vt[o]][vt[p]] = true; } return false; } int t[1000010]; int main() { int cnt = 0; scanf( %d%d , &n, &m); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { scanf( %d , &a[i][j]); t[cnt++] = a[i][j]; } sort(t, t + n * m); int l = 0, r = unique(t, t + n * m) - t - 1; while (l < r) { int m = (l + r + 1) >> 1; if (ok(t[m])) l = m; else r = m - 1; } printf( %d n , t[l]); return 0; } |
#include <bits/stdc++.h> using namespace std; const int max_n = 2e5 + 5; long long ans[max_n]; struct no { long long p, val; }; vector<no> v; bool operator<(const no &x, const no &y) { return x.p < y.p; } int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) { long long x, y; scanf( %lld%lld , &x, &y); v.push_back(no{x, 1}); v.push_back(no{y + 1, -1}); } sort(v.begin(), v.end()); long long add = v[0].val, now = v[0].p; for (int i = 1; i < v.size();) { for (int j = i; j < v.size(); j++) { if (v[j].p == now) { add = add + v[j].val; i++; } else { ans[add] += v[j].p - now; add += v[j].val; now = v[j].p; i = j + 1; break; } } } for (int i = 1; i <= n; i++) printf( %lld , ans[i]); return 0; } |
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_tfifo.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core transmitter FIFO ////
//// ////
//// To Do: ////
//// Nothing. ////
//// ////
//// Author(s): ////
//// - ////
//// - Jacob Gorban ////
//// - Igor Mohor () ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2002/07/22 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.16 2001/12/20 13:25:46 mohor
// rx push changed to be only one cycle wide.
//
// Revision 1.15 2001/12/18 09:01:07 mohor
// Bug that was entered in the last update fixed (rx state machine).
//
// Revision 1.14 2001/12/17 14:46:48 mohor
// overrun signal was moved to separate block because many sequential lsr
// reads were preventing data from being written to rx fifo.
// underrun signal was not used and was removed from the project.
//
// Revision 1.13 2001/11/26 21:38:54 gorban
// Lots of fixes:
// Break condition wasn't handled correctly at all.
// LSR bits could lose their values.
// LSR value after reset was wrong.
// Timing of THRE interrupt signal corrected.
// LSR bit 0 timing corrected.
//
// Revision 1.12 2001/11/08 14:54:23 mohor
// Comments in Slovene language deleted, few small fixes for better work of
// old tools. IRQs need to be fix.
//
// Revision 1.11 2001/11/07 17:51:52 gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.10 2001/10/20 09:58:40 gorban
// Small synopsis fixes
//
// Revision 1.9 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.8 2001/08/24 08:48:10 mohor
// FIFO was not cleared after the data was read bug fixed.
//
// Revision 1.7 2001/08/23 16:05:05 mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.3 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.3 2001/05/27 17:37:48 gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.2 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:12+02 jacob
// Initial revision
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "uart_defines.v"
module uart_tfifo (clk,
wb_rst_i, data_in, data_out,
// Control signals
push, // push strobe, active high
pop, // pop strobe, active high
// status signals
overrun,
count,
fifo_reset,
reset_status
);
// FIFO parameters
parameter fifo_width = `UART_FIFO_WIDTH;
parameter fifo_depth = `UART_FIFO_DEPTH;
parameter fifo_pointer_w = `UART_FIFO_POINTER_W;
parameter fifo_counter_w = `UART_FIFO_COUNTER_W;
input clk;
input wb_rst_i;
input push;
input pop;
input [fifo_width-1:0] data_in;
input fifo_reset;
input reset_status;
output [fifo_width-1:0] data_out;
output overrun;
output [fifo_counter_w-1:0] count;
wire [fifo_width-1:0] data_out;
// FIFO pointers
reg [fifo_pointer_w-1:0] top;
reg [fifo_pointer_w-1:0] bottom;
reg [fifo_counter_w-1:0] count;
reg overrun;
wire [fifo_pointer_w-1:0] top_plus_1 = top + 1'b1;
raminfr #(fifo_pointer_w,fifo_width,fifo_depth) tfifo
(.clk(clk),
.we(push),
.a(top),
.dpra(bottom),
.di(data_in),
.dpo(data_out)
);
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
begin
if (wb_rst_i)
begin
top <= #1 0;
bottom <= #1 1'b0;
count <= #1 0;
end
else
if (fifo_reset) begin
top <= #1 0;
bottom <= #1 1'b0;
count <= #1 0;
end
else
begin
case ({push, pop})
2'b10 : if (count<fifo_depth) // overrun condition
begin
top <= #1 top_plus_1;
count <= #1 count + 1'b1;
end
2'b01 : if(count>0)
begin
bottom <= #1 bottom + 1'b1;
count <= #1 count - 1'b1;
end
2'b11 : begin
bottom <= #1 bottom + 1'b1;
top <= #1 top_plus_1;
end
default: ;
endcase
end
end // always
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
begin
if (wb_rst_i)
overrun <= #1 1'b0;
else
if(fifo_reset | reset_status)
overrun <= #1 1'b0;
else
if(push & (count==fifo_depth))
overrun <= #1 1'b1;
end // always
endmodule
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#include <bits/stdc++.h> #pragma comment(linker, /stack:200000000 ) #pragma GCC optimize( Ofast ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,tune=native ) using namespace std; const long long int maxN = 5005; long long int n; vector<long long int> a, coords, keys; long long int cnt[maxN]; long long int getKey(long long int x) { if (x == 0) return 0; vector<long long int> ans; if (x < 0) ans.push_back(-1); x = abs(x); for (long long int i = 2; i * i <= x; i++) { if (x % i == 0) { long long int cnt = 0; while (x % i == 0) { cnt++; x /= i; } if (cnt % 2 == 1) ans.push_back(i); } } if (x > 1) ans.push_back(x); long long int res = 1; for (auto i : ans) res *= i; return res; } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; a.resize(n); keys.resize(n); for (long long int i = 0; i < n; i++) cin >> a[i]; for (long long int i = 0; i < n; i++) { long long int key = getKey(a[i]); keys[i] = key; coords.push_back(key); } sort(coords.begin(), coords.end()); coords.erase(unique(coords.begin(), coords.end()), coords.end()); for (long long int i = 0; i < n; i++) keys[i] = (lower_bound(coords.begin(), coords.end(), keys[i]) - coords.begin()); vector<long long int> ans(n + 1, 0); for (long long int i = 0; i < n; i++) { for (long long int j = 0; j < maxN; j++) cnt[j] = 0; long long int cntZ = 0, cntD = 0; for (long long int j = i; j < n; j++) { long long int key = keys[j]; if (coords[key] == 0) cntZ++; else { cnt[key]++; if (cnt[key] == 1) cntD++; } if (cntD > 0) ans[cntD]++; else ans[cntZ > 0]++; } } for (long long int i = 1; i <= n; i++) cout << ans[i] << ; return 0; } |
#include <bits/stdc++.h> using namespace std; int mobius[500005], prime_cnt[500005], prime[500005], present[500005], nums[500005], cnt[500005]; vector<int> divisors[500005]; void calc_divisors(int val) { int i; if (divisors[val].size() > 0) return; int foo = sqrt(val); for (i = 1; i <= foo; i++) { if ((val % i) == 0) { divisors[val].push_back(i); divisors[val].push_back(val / i); } } if ((foo * foo) == val) { int temp = divisors[val].size(); divisors[val][temp - 1] = 0; } return; } void calc_mobius() { mobius[0] = 0; long long int i, j, temp; prime[1] = 1; mobius[1] = 1; for (i = 2; i < 500005; i++) { if (prime[i] == 0) { for (j = 2 * i; j < 500005; j += i) { prime[j] = 1; prime_cnt[j]++; } temp = i * i; j = 1; while (temp < 500005) { mobius[temp] = 0; j++; temp = j * i * i; } mobius[i] = -1; } else { if (mobius[i] == 500005) { if ((prime_cnt[i] % 2) == 0) mobius[i] = 1; else mobius[i] = -1; } } } return; } int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); ; int i, j, t, n, m, k, l, r, temp, mini, maxi, flag; long long int result = 0LL; for (i = 0; i < 500005; i++) { mobius[i] = 500005; prime[i] = 0; prime_cnt[i] = 0; cnt[i] = 0; present[i] = 0; } calc_mobius(); divisors[1].push_back(1); divisors[2].push_back(1); divisors[2].push_back(2); divisors[3].push_back(1); divisors[3].push_back(3); cin >> n >> m; for (i = 1; i <= n; i++) { cin >> nums[i]; calc_divisors(nums[i]); } for (i = 0; i < m; i++) { cin >> k; temp = nums[k]; if (present[k] == 0) { present[k] = 1; for (j = 0; j < divisors[temp].size(); j++) { result = result + (long long int)mobius[divisors[temp][j]] * cnt[divisors[temp][j]]; cnt[divisors[temp][j]]++; } } else { present[k] = 0; for (j = 0; j < divisors[temp].size(); j++) { result = result - (long long int)mobius[divisors[temp][j]] * (cnt[divisors[temp][j]] - 1LL); cnt[divisors[temp][j]]--; } } cout << result << endl; } return 0; } |
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