text
stringlengths 59
71.4k
|
|---|
#include <bits/stdc++.h> using namespace std; inline long long read() { register char ch; while (!isdigit(ch = getchar())) ; register long long x = ch ^ 0 ; while (isdigit(ch = getchar())) x = (((x << 2) + x) << 1) + (ch ^ 0 ); return x; } vector<pair<long long, long long> > e[200005]; long long n, m, q, a[200005], b[200005], c[200005], sum[200005 << 2], lzy[200005 << 2]; void build(long long o, long long l, long long r, long long p[]) { lzy[o] = 0; if (l == r) { sum[o] = p[l]; return; } long long mid = l + r >> 1; build(o << 1, l, mid, p); build(o << 1 | 1, mid + 1, r, p); sum[o] = min(sum[o << 1], sum[o << 1 | 1]); } void pushdown(long long o) { sum[o << 1] += lzy[o]; sum[o << 1 | 1] += lzy[o]; lzy[o << 1] += lzy[o]; lzy[o << 1 | 1] += lzy[o]; lzy[o] = 0; } void updata(long long o, long long l, long long r, long long L, long long R, long long val) { if (L == l && r == R) { sum[o] += val; lzy[o] += val; return; } if (lzy[o]) pushdown(o); long long mid = l + r >> 1; if (L <= mid) updata(o << 1, l, mid, L, min(mid, R), val); if (R > mid) updata(o << 1 | 1, mid + 1, r, max(mid + 1, L), R, val); sum[o] = min(sum[o << 1], sum[o << 1 | 1]); } signed main() { n = read(); m = read(); q = read(); for (long long i = 1; i < n; ++i) { a[i] = read(); b[i + 1] = read(); } build(1, 1, n, b); for (long long i = 1; i <= m; ++i) { long long u, v, w; u = read(); v = read(); w = read(); e[u].push_back(make_pair(v, w)); } for (long long i = 1; i <= n; ++i) { for (long long j = 0; j < e[i].size(); ++j) { long long v = e[i][j].first, w = e[i][j].second; updata(1, 1, n, 1, v, w); } c[i] = sum[1] + a[i]; } build(1, 1, n, c); printf( %lld n , sum[1]); while (q--) { long long x, y; x = read(); y = read(); updata(1, 1, n, x, x, y - a[x]); a[x] = y; printf( %lld n , sum[1]); } return 0; } |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// MMCM with DRP and device specific
`timescale 1ns/100ps
module ad_mmcm_drp (
// clocks
clk,
mmcm_rst,
mmcm_clk_0,
mmcm_clk_1,
// drp interface
up_clk,
up_rstn,
up_drp_sel,
up_drp_wr,
up_drp_addr,
up_drp_wdata,
up_drp_rdata,
up_drp_ready,
up_drp_locked);
// parameters
parameter MMCM_DEVICE_TYPE = 0;
localparam MMCM_DEVICE_7SERIES = 0;
localparam MMCM_DEVICE_VIRTEX6 = 1;
parameter MMCM_CLKIN_PERIOD = 1.667;
parameter MMCM_VCO_DIV = 6;
parameter MMCM_VCO_MUL = 12.000;
parameter MMCM_CLK0_DIV = 2.000;
parameter MMCM_CLK1_DIV = 6;
// clocks
input clk;
input mmcm_rst;
output mmcm_clk_0;
output mmcm_clk_1;
// drp interface
input up_clk;
input up_rstn;
input up_drp_sel;
input up_drp_wr;
input [11:0] up_drp_addr;
input [15:0] up_drp_wdata;
output [15:0] up_drp_rdata;
output up_drp_ready;
output up_drp_locked;
// internal registers
reg [15:0] up_drp_rdata = 'd0;
reg up_drp_ready = 'd0;
reg up_drp_locked_m1 = 'd0;
reg up_drp_locked = 'd0;
// internal signals
wire bufg_fb_clk_s;
wire mmcm_fb_clk_s;
wire mmcm_clk_0_s;
wire mmcm_clk_1_s;
wire mmcm_locked_s;
wire [15:0] up_drp_rdata_s;
wire up_drp_ready_s;
// drp read and locked
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_drp_rdata <= 'd0;
up_drp_ready <= 'd0;
up_drp_locked_m1 <= 1'd0;
up_drp_locked <= 1'd0;
end else begin
up_drp_rdata <= up_drp_rdata_s;
up_drp_ready <= up_drp_ready_s;
up_drp_locked_m1 <= mmcm_locked_s;
up_drp_locked <= up_drp_locked_m1;
end
end
// instantiations
generate
if (MMCM_DEVICE_TYPE == MMCM_DEVICE_VIRTEX6) begin
MMCM_ADV #(
.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.CLOCK_HOLD ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (MMCM_VCO_DIV),
.CLKFBOUT_MULT_F (MMCM_VCO_MUL),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (MMCM_CLK0_DIV),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (MMCM_CLK1_DIV),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (MMCM_CLKIN_PERIOD),
.REF_JITTER1 (0.010))
i_mmcm (
.CLKIN1 (clk),
.CLKFBIN (bufg_fb_clk_s),
.CLKFBOUT (mmcm_fb_clk_s),
.CLKOUT0 (mmcm_clk_0_s),
.CLKOUT1 (mmcm_clk_1_s),
.LOCKED (mmcm_locked_s),
.DCLK (up_clk),
.DEN (up_drp_sel),
.DADDR (up_drp_addr[6:0]),
.DWE (up_drp_wr),
.DI (up_drp_wdata),
.DO (up_drp_rdata_s),
.DRDY (up_drp_ready_s),
.CLKFBOUTB (),
.CLKOUT0B (),
.CLKOUT1B (),
.CLKOUT2 (),
.CLKOUT2B (),
.CLKOUT3 (),
.CLKOUT3B (),
.CLKOUT4 (),
.CLKOUT5 (),
.CLKOUT6 (),
.CLKIN2 (1'b0),
.CLKINSEL (1'b1),
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
.CLKINSTOPPED (),
.CLKFBSTOPPED (),
.PWRDWN (1'b0),
.RST (mmcm_rst));
end
if (MMCM_DEVICE_TYPE == MMCM_DEVICE_7SERIES) begin
MMCME2_ADV #(
.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (MMCM_VCO_DIV),
.CLKFBOUT_MULT_F (MMCM_VCO_MUL),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (MMCM_CLK0_DIV),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (MMCM_CLK1_DIV),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (MMCM_CLKIN_PERIOD),
.REF_JITTER1 (0.010))
i_mmcm (
.CLKIN1 (clk),
.CLKFBIN (bufg_fb_clk_s),
.CLKFBOUT (mmcm_fb_clk_s),
.CLKOUT0 (mmcm_clk_0_s),
.CLKOUT1 (mmcm_clk_1_s),
.LOCKED (mmcm_locked_s),
.DCLK (up_clk),
.DEN (up_drp_sel),
.DADDR (up_drp_addr[6:0]),
.DWE (up_drp_wr),
.DI (up_drp_wdata),
.DO (up_drp_rdata_s),
.DRDY (up_drp_ready_s),
.CLKFBOUTB (),
.CLKOUT0B (),
.CLKOUT1B (),
.CLKOUT2 (),
.CLKOUT2B (),
.CLKOUT3 (),
.CLKOUT3B (),
.CLKOUT4 (),
.CLKOUT5 (),
.CLKOUT6 (),
.CLKIN2 (1'b0),
.CLKINSEL (1'b1),
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
.CLKINSTOPPED (),
.CLKFBSTOPPED (),
.PWRDWN (1'b0),
.RST (mmcm_rst));
end
endgenerate
BUFG i_fb_clk_bufg (.I (mmcm_fb_clk_s), .O (bufg_fb_clk_s));
BUFG i_clk_0_bufg (.I (mmcm_clk_0_s), .O (mmcm_clk_0));
BUFG i_clk_1_bufg (.I (mmcm_clk_1_s), .O (mmcm_clk_1));
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; int gcd(int a, int b) { if (a == 0) return b; return gcd(b % a, a); } int lcm(int a, int b) { return (a * b) / gcd(a, b); } int fact(int n) { if (n == 0 || n == 1) return 1; else return n * fact(n - 1); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t--) { int n, a = 0, b = 0, l1 = 0, l2 = 0, c = 0, k = 0; cin >> n; deque<int> q; for (int i = 0, x; i < n; i++) { cin >> x; q.push_back(x); } while (!q.empty()) { while (l1 <= l2 && !q.empty()) { a += q.front(); l1 += q.front(); q.pop_front(); k = 1; } c += k; k = l2 = 0; while (l2 <= l1 && !q.empty()) { b += q.back(); l2 += q.back(); q.pop_back(); k = 1; } c += k; k = l1 = 0; } cout << c << << a << << b << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(NULL); long long i, j, n, m; cin >> n; long long a[n - 1]; for (int i = 0; i < n - 1; i++) cin >> a[i]; long long dp[n][2][2]; memset(dp, 0, sizeof(dp)); for (int j = 0; j < 2; j++) for (int k = 0; k < 2; k++) dp[1][j][k] = a[0] - 1; if (a[0] % 2 == 0) dp[1][0][0]++, dp[1][1][1]++; else dp[1][1][0]++, dp[1][0][1]++; long long maxi = a[0]; for (int i = 2; i < n; i++) { long long t = a[i - 1]; if (t % 2 == 0) { dp[i][0][0] = dp[i - 1][0][0] + t; dp[i][1][1] = max(dp[i - 1][1][1], max(dp[i - 1][0][0], dp[i - 1][0][1])) + t; dp[i][0][1] = max(dp[i - 1][0][0], dp[i - 1][0][1]) + t - 1; dp[i][1][0] = max(dp[i - 1][0][0], dp[i - 1][1][0]) + t - 1; } else if (t == 1) { dp[i][0][0] = 0; dp[i][1][1] = 0; dp[i][0][1] = max(dp[i - 1][0][0], dp[i - 1][0][1]) + 1; dp[i][1][0] = max(dp[i - 1][0][0], dp[i - 1][1][0]) + 1; } else { dp[i][0][0] = dp[i - 1][0][0] + t - 1; dp[i][1][1] = max(dp[i - 1][1][1], max(dp[i - 1][0][0], dp[i - 1][0][1])) + t - 1; dp[i][0][1] = max(dp[i - 1][0][0], dp[i - 1][0][1]) + t; dp[i][1][0] = max(dp[i - 1][0][0], dp[i - 1][1][0]) + t; } for (int j = 0; j < 2; j++) for (int k = 0; k < 2; k++) maxi = max(maxi, dp[i][j][k]); } cout << maxi; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, x; long long amt = 0; cin >> n; vector<pair<int, int> > a; vector<int> p(n); vector<long long> count(6, 0); for (int i(0); i < (n); i++) { cin >> p[i]; } for (int i(0); i < (5); i++) { cin >> x; a.push_back(make_pair(x, i + 1)); } sort((a).begin(), (a).end()); for (int i(0); i < (n); i++) { amt += p[i]; for (int j(4); j >= (0); j--) { if (a[j].first <= amt) { count[a[j].second] += amt / a[j].first; amt -= a[j].first * (amt / a[j].first); } } } for (int i(1); i < (6); i++) { cout << count[i] << ; } cout << n << amt; return 0; } |
#include <bits/stdc++.h> long long minus(long long k) { return (1000000009LL - 1 + k) % 1000000009LL; } long long multiply(long long k) { return (k * 2) % 1000000009LL; } long long multiply(long long a, long long b) { return (a * b) % 1000000009LL; } int main() { int n, m; scanf( %d %d , &n, &m); long long p = 1; for (int i = 0; i < m; i++) p = multiply(p); if (m < 20 && p < n) { printf( 0 n ); return 0; } long long ans = 1; for (int i = 0; i < n; i++) { p = minus(p); ans = multiply(ans, p); } printf( %I64d n , ans); } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; int max = 0, min = 0; int a[m], b[m]; for (int i = 0; i < m; i++) { cin >> a[i]; b[i] = a[i]; } sort(a, a + m, greater<int>()); for (int i = 0; i < n; i++) { if (a[0] != 0) { max = max + a[0]; a[0] = a[0] - 1; sort(a, a + m, greater<int>()); } else { break; } } sort(b, b + m); int i = 0, k = 0; while (i != n) { if (b[k] != 0) { min = min + b[k]; b[k] = b[k] - 1; } else { k++; min = min + b[k]; b[k] = b[k] - 1; } i++; } cout << max << << min; return 0; } |
/*
* Author: Oswaldo Cadenas <>
*/
module test;
parameter S = 9;
parameter K = 3;
parameter L = 2**(S-K);
parameter N = 2**(S-1);
reg signed [S-1:0] a_reg;
bit signed [S-1:0] a_bit;
byte signed a_byte;
shortint signed a_short;
int signed a_int;
longint signed a_long;
byte signed amount;
byte unsigned pos;
int temp;
int i;
initial begin
// test for style "a += some" statement on type reg
for (i = 0; i < N; i = i+1) begin
a_reg = $random % L;
amount = $random % K;
#1;
temp = a_reg + amount;
a_reg += amount;
#1;
//$display ("a = %0d, amount = %0d, temp = %0d", a, amount, temp);
if (temp !== a_reg) begin
$display("FAILED");
$finish;
end
#1;
temp = a_reg - amount;
a_reg -= amount;
#1;
if (temp !== a_reg) begin
$display("FAILED");
$finish;
end
end
// test for style "a += some" statement on type bit
for (i = 0; i < N; i = i+1) begin
a_bit = $random % L;
amount = $random % K;
#1;
temp = a_bit + amount;
a_bit += amount;
#1;
if (temp !== a_bit) begin
$display("FAILED");
$finish;
end
#1;
temp = a_bit - amount;
a_bit -= amount;
#1;
if (temp !== a_bit) begin
$display("FAILED");
$finish;
end
end // for
// test for style "a += some" statement on type byte
for (i = 0; i < N; i = i+1) begin
a_byte = $random % L;
amount = $random % K;
#1;
temp = a_byte + amount;
a_byte += amount;
#1;
if (temp !== a_byte) begin
$display("FAILED");
$finish;
end
#1;
temp = a_byte - amount;
a_byte -= amount;
#1;
if (temp !== a_byte) begin
$display("FAILED");
$finish;
end
end // for
// test for style "a += some" statement on type shortint
for (i = 0; i < N; i = i+1) begin
a_short = 2*($random % L);
amount = 2*($random % K);
#1;
temp = a_short + amount;
a_short += amount;
#1;
if (temp !== a_short) begin
$display("FAILED");
$finish;
end
#1;
temp = a_short - amount;
a_short -= amount;
#1;
if (temp !== a_short) begin
$display("FAILED");
$finish;
end
#1;
temp = a_short * amount;
a_short *= amount;
#1;
if (temp !== a_short) begin
$display("FAILED");
$finish;
end
#1;
temp = a_short / amount;
a_short /= amount;
#1;
if (temp !== a_short) begin
$display("FAILED");
$finish;
end
#1;
temp = a_short % amount;
a_short %= amount;
#1;
if (temp !== a_short) begin
$display("FAILED");
$finish;
end
#1;
temp = a_short & amount;
a_short &= amount;
#1;
if (temp !== a_short) begin
$display("FAILED");
$finish;
end
#1;
temp = a_short | amount;
a_short |= amount;
#1;
if (temp !== a_short) begin
$display("FAILED");
$finish;
end
#1;
temp = a_short ^ amount;
a_short ^= amount;
#1;
if (temp !== a_short) begin
$display("FAILED");
$finish;
end
#1;
pos = 2*({$random} % K);
temp = a_short << pos;
a_short <<= pos;
#1;
if (temp !== a_short) begin
$display("FAILED");
$finish;
end
#1;
temp = a_short >> pos;
a_short >>= pos;
#1;
if (temp !== a_short) begin
$display("FAILED");
$finish;
end
#1;
temp = a_short <<< pos;
a_short <<<= pos;
#1;
if (temp !== a_short) begin
$display("FAILED");
$finish;
end
#1;
temp = a_short >>> pos;
a_short >>>= pos;
#1;
if (temp !== a_short) begin
$display("FAILED");
$finish;
end
end // for
// test for style "a += some" statement on type int
for (i = 0; i < N; i = i+1) begin
a_int = 4*($random % L);
amount = 4*($random % K);
#1;
temp = a_int + amount;
a_int += amount;
#1;
if (temp !== a_int) begin
$display("FAILED");
$finish;
end
#1;
temp = a_int - amount;
a_int -= amount;
#1;
if (temp !== a_int) begin
$display("FAILED");
$finish;
end
#1;
temp = a_int * amount;
a_int *= amount;
#1;
if (temp !== a_int) begin
$display("FAILED");
$finish;
end
#1;
temp = a_int / amount;
a_int /= amount;
#1;
if (temp !== a_int) begin
$display("FAILED");
$finish;
end
#1;
temp = a_int % amount;
a_int %= amount;
#1;
if (temp !== a_int) begin
$display("FAILED");
$finish;
end
#1;
temp = a_int & amount;
a_int &= amount;
#1;
if (temp !== a_int) begin
$display("FAILED");
$finish;
end
#1;
temp = a_int | amount;
a_int |= amount;
#1;
if (temp !== a_int) begin
$display("FAILED");
$finish;
end
#1;
temp = a_int ^ amount;
a_int ^= amount;
#1;
if (temp !== a_int) begin
$display("FAILED");
$finish;
end
#1;
pos = 4*({$random} % K);
temp = a_int << pos;
a_int <<= pos;
#1;
if (temp !== a_int) begin
$display("FAILED");
$finish;
end
#1;
temp = a_int >> pos;
a_int >>= pos;
#1;
if (temp !== a_int) begin
$display("FAILED");
$finish;
end
#1;
temp = a_int <<< pos;
a_int <<<= pos;
#1;
if (temp !== a_int) begin
$display("FAILED");
$finish;
end
#1;
temp = a_int >>> pos;
a_int >>= pos;
#1;
if (temp !== a_int) begin
$display("FAILED");
$finish;
end
end // for
// test for style "a += some" statement on type longint
for (i = 0; i < N; i = i+1) begin
a_long = 8*($random % L);
amount = 8*($random % K);
#1;
temp = a_long + amount;
a_long += amount;
#1;
if (temp !== a_long) begin
$display("FAILED");
$finish;
end
#1;
temp = a_long - amount;
a_long -= amount;
#1;
if (temp !== a_long) begin
$display("FAILED");
$finish;
end
#1;
temp = a_long * amount;
a_long *= amount;
#1;
if (temp !== a_long) begin
$display("FAILED");
$finish;
end
#1;
temp = a_long / amount;
a_long /= amount;
#1;
if (temp !== a_long) begin
$display("FAILED");
$finish;
end
#1;
temp = a_long % amount;
a_long %= amount;
#1;
if (temp !== a_long) begin
$display("FAILED");
$finish;
end
#1;
temp = a_long & amount;
a_long &= amount;
#1;
if (temp !== a_long) begin
$display("FAILED");
$finish;
end
#1;
temp = a_long | amount;
a_long |= amount;
#1;
if (temp !== a_long) begin
$display("FAILED");
$finish;
end
#1;
temp = a_long ^ amount;
a_long ^= amount;
#1;
if (temp !== a_long) begin
$display("FAILED");
$finish;
end
#1;
pos = 8*({$random} % K);
temp = a_long << pos;
a_long <<= pos;
#1;
if (temp !== a_long) begin
$display("FAILED");
$finish;
end
#1;
temp = a_long >> pos;
a_long >>= pos;
#1;
if (temp !== a_long) begin
$display("FAILED");
$finish;
end
#1;
temp = a_long <<< pos;
a_long <<<= pos;
#1;
if (temp !== a_long) begin
$display("FAILED");
$finish;
end
#1;
temp = a_long >>> pos;
a_long >>= pos;
#1;
if (temp !== a_long) begin
$display("FAILED");
$finish;
end
end // for
$display("PASSED");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; int h[5005]; int dp[5005][2505][2]; void test_case() { int n; scanf( %d , &n); for (int i = 1; i <= n; ++i) scanf( %d , &h[i]); memset(dp, INF, sizeof(dp)); dp[0][0][0] = 0; dp[1][0][0] = 0; dp[1][1][1] = 0; for (int i = 2; i <= n; ++i) { for (int j = 0, c = (i + 1) / 2; j <= c; ++j) dp[i][j][0] = min(dp[i - 1][j][0], dp[i - 1][j][1] + max(0, h[i] - (h[i - 1] - 1))); for (int j = 1, c = (i + 1) / 2; j <= c; ++j) dp[i][j][1] = min( dp[i - 2][j - 1][0] + max(0, h[i - 1] - (h[i] - 1)), dp[i - 2][j - 1][1] + max(0, max(h[i - 1] - (h[i] - 1), h[i - 1] - (h[i - 2] - 1)))); } for (int k = 1, c = (n + 1) / 2; k <= c; ++k) printf( %d%c , min(dp[n][k][0], dp[n][k][1]), n [k == c]); } int main() { int t = 1; for (int ti = 1; ti <= t; ++ti) { test_case(); } } |
#include <bits/stdc++.h> using namespace std; vector<pair<int, pair<int, int> > > horz, vert, tmp; set<int> y_com; map<int, int> y_map; void cleanup(vector<pair<int, pair<int, int> > >& v) { sort(v.begin(), v.end()); for (auto it = v.begin(); it != v.end();) { if (it != v.begin()) { auto prev = it; prev--; if (prev->first == it->first && prev->second.second >= it->second.first - 1) { prev->second.second = max(it->second.second, prev->second.second); it = v.erase(it); } else it++; } else it++; } } int BIT[211111]; void update(int pos, int val) { while (pos < 211111) { BIT[pos] += val; pos += (pos & (-pos)); } } int get(int pos) { int ans = 0; while (pos > 0) { ans += BIT[pos]; pos -= (pos & (-pos)); } return ans; } int main() { ios_base::sync_with_stdio(false); int n; cin >> n; long long ans = 0; for (int i = 0; i < n; i++) { int x[2], y[2]; cin >> x[0] >> y[0] >> x[1] >> y[1]; x[0] += 1000000001; x[1] += 1000000001; y[0] += 1000000001; y[1] += 1000000001; if (y[0] == y[1]) { horz.push_back( make_pair(y[0], make_pair(min(x[0], x[1]), max(x[0], x[1])))); } else { vert.push_back( make_pair(x[0], make_pair(min(y[0], y[1]), max(y[0], y[1])))); } } cleanup(horz); cleanup(vert); for (auto it : horz) { ans += it.second.second - it.second.first + 1; y_com.insert(it.first); } for (auto it : vert) { ans += it.second.second - it.second.first + 1; y_com.insert(it.second.first); y_com.insert(it.second.second); } int cnt = 1; for (auto it : y_com) y_map[it] = cnt++; for (auto it : horz) { tmp.push_back(make_pair(it.second.first, make_pair(it.first, 1))); tmp.push_back(make_pair(it.second.second + 1, make_pair(it.first, -1))); } sort(tmp.begin(), tmp.end()); int cur = 0; for (auto it : vert) { while (cur < tmp.size() && tmp[cur].first <= it.first) { update(y_map[tmp[cur].second.first], tmp[cur].second.second); cur++; } ans -= get(y_map[it.second.second]) - get(y_map[it.second.first] - 1); } cout << ans << endl; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O211AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__O211AI_BEHAVIORAL_PP_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o211ai (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
B1 ,
C1
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
// Local signals
wire C1 or0_out ;
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , C1, or0_out, B1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O211AI_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; inline int two(int n) { return 1 << n; } inline int test(int n, int b) { return (n >> b) & 1; } inline void set_bit(int& n, int b) { n |= two(b); } inline void unset_bit(int& n, int b) { n &= ~two(b); } inline int last_bit(int n) { return n & (-n); } int dist[403][403]; void print(int a[][403], int n) { for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) cout << a[i][j] << ; cout << n ; } } int floyd_warshall(int a[][403], int n) { for (int via = 1; via <= n; via++) { for (int from = 1; from <= n; from++) { for (int to = 1; to <= n; to++) { a[from][to] = min(a[from][to], a[from][via] + a[via][to]); } } } return a[1][n]; } int dist_dij[403]; bool visited[403]; int vertex_min_path_len(int n) { int min_dist = INT_MAX, min_vertex = 0; for (int i = 1; i <= n; i++) { if (!visited[i] && dist_dij[i] <= min_dist) min_dist = dist_dij[i], min_vertex = i; } return min_vertex; } int dijkstra(int src, int n) { memset(visited, 0, sizeof visited); for (int i = 1; i <= n; i++) dist_dij[i] = 403; dist_dij[src] = 0; int cnt = 1; while (cnt <= n) { int u = vertex_min_path_len(n); visited[u] = true; for (int v = 1; v <= n; v++) { if (!visited[v] && dist[u][v] != 403 && dist_dij[u] + dist[u][v] <= dist_dij[v]) dist_dij[v] = dist_dij[u] + dist[u][v]; } cnt++; } return dist_dij[n]; } int main() { ios::sync_with_stdio(false); int n, m; cin >> n >> m; for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) dist[i][j] = 403; for (int i = 0; i < m; i++) { int u, v; cin >> u >> v; dist[u][v] = dist[v][u] = 1; } if (dist[1][n] == 1) { for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { if (dist[i][j] == 403) dist[i][j] = 1; else dist[i][j] = 403; if (i == j) dist[i][j] = 403; } } } int ans = -2; ans = dijkstra(1, n); if (ans == 403) cout << -1 n ; else cout << ans << n ; return 0; } |
//////////////////////////////////////////////////////////////////////
//// ////
//// spi_top.v ////
//// ////
//// This file is part of the SPI IP core project ////
//// http://www.opencores.org/projects/spi/ ////
//// ////
//// Author(s): ////
//// - Simon Srot () ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
////
//// /* Modifications to spi_top.v */
//// /* Copyright (c) 2006 Rice University */
//// /* All Rights Reserved */
//// /* This code is covered by the Rice-WARP license */
//// /* See http://warp.rice.edu/license/ for details */
module spi_top
(
// OPB signals
opb_clk_i, opb_rst_i,
// SPI registers
reg_ctrl, reg_ss, reg_divider, reg_tx, ctrlwrite, busval, go,
// SPI signals
ss_pad_o, sclk_pad_o, mosi_pad_o
);
parameter Tp = 1;
// OPB signals
input opb_clk_i; // master clock input
input opb_rst_i; // synchronous active high reset
// SPI registers
input [13:0] reg_ctrl;
input [7:0] reg_ss;
input reg_divider;
input [17:0] reg_tx;
input ctrlwrite;
input busval;
output go;
// SPI signals
output [8-1:0] ss_pad_o; // slave select
output sclk_pad_o; // serial clock
output mosi_pad_o; // master out slave in
// Internal signals
wire [17:0] rx; // Rx register
wire rx_negedge; // miso is sampled on negative edge
wire tx_negedge; // mosi is driven on negative edge
wire [4:0] char_len; // char len
//wire go; // go
wire lsb; // lsb first on line
wire ie; // interrupt enable
wire ass; // automatic slave select
wire spi_divider_sel; // divider register select
wire spi_ctrl_sel; // ctrl register select
wire [3:0] spi_tx_sel; // tx_l register select
wire spi_ss_sel; // ss register select
wire tip; // transfer in progress
wire pos_edge; // recognize posedge of sclk
wire neg_edge; // recognize negedge of sclk
wire last_bit; // marks last character bit
reg ctrlbitgo;
assign rx_negedge = reg_ctrl[9];
assign tx_negedge = reg_ctrl[10];
assign go = ctrlbitgo;
assign char_len = reg_ctrl[6:0];
assign lsb = reg_ctrl[11];
assign ie = reg_ctrl[12];
assign ass = reg_ctrl[13];
always @(posedge opb_clk_i or posedge opb_rst_i)
begin
if (opb_rst_i)
ctrlbitgo <= #Tp 1'b0;
else if(ctrlwrite && !tip)
ctrlbitgo <= #Tp busval;
else if(tip && last_bit && pos_edge)
ctrlbitgo <= #Tp 1'b0;
end
assign ss_pad_o = ~((reg_ss & {8{tip & ass}}) | (reg_ss & {8{!ass}}));
spi_clgen clgen (.clk_in(opb_clk_i), .rst(opb_rst_i), .go(go), .enable(tip), .last_clk(last_bit),
.divider(reg_divider), .clk_out(sclk_pad_o), .pos_edge(pos_edge),
.neg_edge(neg_edge));
spi_shift shift (.clk(opb_clk_i), .rst(opb_rst_i), .len(char_len[5-1:0]),
.lsb(lsb), .go(go), .pos_edge(pos_edge), .neg_edge(neg_edge),
.rx_negedge(rx_negedge), .tx_negedge(tx_negedge),
.tip(tip), .last(last_bit),
.p_in(reg_tx), .p_out(rx),
.s_clk(sclk_pad_o), .s_out(mosi_pad_o));
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ull = unsigned long long; using ld = long double; using pii = pair<int, int>; using pll = pair<ll, ll>; using pci = pair<char, int>; using vi = vector<int>; using vll = vector<ll>; using vpii = vector<pii>; const ll infll = 1e18 + 3; const int maxn = 1e6 + 77; const int nmax = 1e6 + 77; const ll basell = 1e18 + 3; const int mod = 1e9 + 7; const ld eps = 1e-7; const int inf = 1009000999; const int nv = 100505; const int baseint = 1000200013; const ld PI = acos(-1.0); inline bool EQ(ld a, ld b) { return fabs(a - b) < 1e-9; } struct lis { int x, y, z; }; vector<lis> ans; int vis[2 * nv]; int used[2 * nv]; vi g[2 * nv]; int h[2 * nv]; void dfs(int v, int p) { vis[v] = 1; vector<int> q; for (int u : g[v]) { if (u == p) continue; if (!vis[u]) { h[u] = h[v] + 1; dfs(u, v); if (!used[u]) q.push_back(u); } else { if (h[u] > h[v]) q.push_back(u); } } for (int i = 0; i + 1 < ((int)(q).size()); i += 2) { ans.push_back({q[i], v, q[i + 1]}); } if (((int)(q).size()) % 2 == 1 && p != -1) { ans.push_back({q.back(), v, p}); used[v] = 1; } } int inline solve() { ios::sync_with_stdio(NULL), cin.tie(NULL), cout.tie(NULL); ; int n, m; cin >> n >> m; for (int i = 0; i < m; ++i) { int a, b; cin >> a >> b; g[a - 1].push_back(b - 1); g[b - 1].push_back(a - 1); } for (int i = 0; i < n; ++i) { if (!vis[i]) dfs(i, -1); } cout << ((int)(ans).size()) << n ; for (lis u : ans) cout << u.x + 1 << << u.y + 1 << << u.z + 1 << n ; return 0; } int32_t main() { solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; map<string, long long> m; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); vector<pair<long long, long long> > v = { make_pair(1989, 1998), make_pair(1999, 2098), make_pair(2099, 3098), make_pair(3099, 13098), make_pair(13099, 113098), make_pair(113099, 1113098), make_pair(1113099, 11113098), make_pair(11113099, 111113098), make_pair(111113099, 1111113098)}; for (int i = 1989; i <= 1998; i++) { string s = ; long long temp = i; s += (temp % 10 + 48); m[s] = i; } for (int i = 1999; i <= 2098; i++) { string s = ; long long temp = i; for (int j = 0; j < 2; j++) { s += (temp % 10 + 48); temp /= 10; } reverse(s.begin(), s.end()); m[s] = i; } for (int i = 2099; i <= 3098; i++) { string s = ; long long temp = i; for (int j = 0; j < 3; j++) { s += (temp % 10 + 48); temp /= 10; } reverse(s.begin(), s.end()); m[s] = i; } int n; cin >> n; for (int i = 1; i <= n; i++) { string s; cin >> s; string work = ; int sz = s.size(); for (int j = 4; j < sz; j++) { work += s[j]; } sz = work.size(); if (sz <= 3) { cout << m[work] << n ; } else { long long temp = v[sz - 1].first; string s1 = ; while (temp) { s1 += (temp % 10 + 48); temp /= 10; } reverse(s1.begin(), s1.end()); if (work < s1) { cout << 1 << work << n ; } else { cout << work << n ; } } } } |
#include <bits/stdc++.h> using namespace std; template <class T> inline void checkmin(T &a, T b) { if (b < a) a = b; } template <class T> inline void checkmax(T &a, T b) { if (b > a) a = b; } int cond = (long long)1; void _main() { int n, w, m; scanf( %d%d%d , &n, &w, &m); int guests = m; int usedbottles = 0; int botid = 1; int fuel = m; int used = 0; bool ok = 1; vector<vector<pair<int, int> > > sol; for (int i = (0); i < (m); ++i) { int needfuel = n; vector<pair<int, int> > result; while (needfuel > 0) { if (fuel > 0) { int use = min(fuel, needfuel); result.push_back(pair<int, int>(botid, use)); fuel -= use; needfuel -= use; ++used; if (used > 2) ok = 0; if (fuel == 0) { botid++; fuel = m; used = 0; } } else assert(0); } sol.push_back(result); } if (!ok) cout << NO << endl; cout.precision(6); if (ok) { cout << YES << endl; for (int i = (0); i < (m); ++i) { for (int j = (0); j < ((int)(sol[i]).size()); ++j) { if (j) cout << ; long double myfuel = (long double)sol[i][j].second * w / m; cout << fixed << sol[i][j].first << << myfuel; } cout << endl; } } } int main(int argc, char **argv) { string p = ../gcj/source/ + string( ) + argv[0][strlen(argv[0]) - 1]; for (int i = (0); i < (argc); ++i) if (strcmp(argv[i], 1n ) == 0) { freopen( 1.in , r , stdin); } for (int i = (0); i < (argc); ++i) if (strcmp(argv[i], 2n ) == 0) { freopen( 2.in , r , stdin); } for (int i = (0); i < (argc); ++i) if (strcmp(argv[i], 3n ) == 0) { freopen( 3.in , r , stdin); } for (int i = (0); i < (argc); ++i) if (strcmp(argv[i], 4n ) == 0) { freopen( 4.in , r , stdin); } for (int i = (0); i < (argc); ++i) if (strcmp(argv[i], 5n ) == 0) { freopen( 5.in , r , stdin); } for (int i = (0); i < (argc); ++i) if (strcmp(argv[i], s0 ) == 0) { freopen((p + -small-0.in ).c_str(), r , stdin); freopen((p + -small-0.out ).c_str(), w , stdout); } for (int i = (0); i < (argc); ++i) if (strcmp(argv[i], s1 ) == 0) { freopen((p + -small-1.in ).c_str(), r , stdin); freopen((p + -small-1.out ).c_str(), w , stdout); } for (int i = (0); i < (argc); ++i) if (strcmp(argv[i], s2 ) == 0) { freopen((p + -small-2.in ).c_str(), r , stdin); freopen((p + -small-2.out ).c_str(), w , stdout); } for (int i = (0); i < (argc); ++i) if (strcmp(argv[i], l0 ) == 0) { freopen((p + -large-0.in ).c_str(), r , stdin); freopen((p + -large-0.out ).c_str(), w , stdout); } for (int i = (0); i < (argc); ++i) if (strcmp(argv[i], q ) == 0) cond = 1 << 30; _main(); return 0; } |
module ExecuteForwarding(p0, p1, p0Addr, p1Addr, regAddr_EX_MEM, regWe_EX_MEM, aluResult_EX_MEM, jal_EX_MEM, pcNext_EX_MEM, memRe_EX_MEM, regAddr_MEM_WB, regWe_MEM_WB, aluResult_MEM_WB, jal_MEM_WB, pcNext_MEM_WB, memRe_MEM_WB, memData_MEM_WB, writeData_WB, writeAddr_WB, writeEnable_WB, forwardP0, forwardP1, forwardStall);
input [15:0] p0, p1, aluResult_EX_MEM, pcNext_EX_MEM, aluResult_MEM_WB, pcNext_MEM_WB, memData_MEM_WB, writeData_WB;
input [3:0] p0Addr, p1Addr, regAddr_EX_MEM, regAddr_MEM_WB, writeAddr_WB;
input regWe_EX_MEM, jal_EX_MEM, memRe_EX_MEM, regWe_MEM_WB, jal_MEM_WB, memRe_MEM_WB, writeEnable_WB;
output [15:0] forwardP0, forwardP1;
output forwardStall;
wire [15:0] memoryForwarding, writeBackForwarding;
assign memoryForwarding = jal_EX_MEM ? pcNext_EX_MEM : aluResult_EX_MEM;
assign writeBackForwarding = jal_MEM_WB ? pcNext_MEM_WB : (memRe_MEM_WB ? memData_MEM_WB : aluResult_MEM_WB);
assign forwardP0 = (p0Addr == 4'b0000) ? p0 :
(regWe_EX_MEM && (p0Addr == regAddr_EX_MEM) && !(regWe_MEM_WB && memRe_MEM_WB && (p0Addr == regAddr_MEM_WB))) ? memoryForwarding :
(regWe_MEM_WB && (p0Addr == regAddr_MEM_WB)) ? writeBackForwarding:
(writeEnable_WB && (p0Addr == writeAddr_WB)) ? writeData_WB :
p0;
assign forwardP1 = (p1Addr == 4'b0000) ? p1 :
(regWe_EX_MEM && (p1Addr == regAddr_EX_MEM) && !(regWe_MEM_WB && memRe_MEM_WB && (p1Addr == regAddr_MEM_WB))) ? memoryForwarding :
(regWe_MEM_WB && (p1Addr == regAddr_MEM_WB)) ? writeBackForwarding :
(writeEnable_WB && (p1Addr == writeAddr_WB)) ? writeData_WB :
p1;
assign forwardStall = (regWe_EX_MEM &&
(((p0Addr == regAddr_EX_MEM) && memRe_EX_MEM &&
!(regWe_MEM_WB && memRe_MEM_WB && (p0Addr == regAddr_MEM_WB))) ||
((p1Addr == regAddr_EX_MEM) && memRe_EX_MEM &&
!(regWe_MEM_WB && memRe_MEM_WB && (p1Addr == regAddr_MEM_WB)))));
endmodule
|
`timescale 1ns/10ps
`include "pipeconnect.h"
module bus_ctrl(input wire clk,
input wire rst,
// Master connections
input wire `REQ master1_req,
output wire `RES master1_res,
input wire `REQ master2_req,
output wire `RES master2_res,
input wire `REQ master3_req,
output wire `RES master3_res,
// Target connections
output wire `REQ target1_req,
input wire `RES target1_res,
output wire `REQ target2_req,
input wire `RES target2_res
);
parameter debug = 0;
wire master1_target1 = (master1_req`A & 'hFFF0_0000) == 'h4000_0000;
wire master2_target1 = (master2_req`A & 'hFFF0_0000) == 'h4000_0000;
wire master3_target1 = (master3_req`A & 'hFFF0_0000) == 'h4000_0000;
wire master1_target2 = (master1_req`A & 'hFFF0_0000) == 'hFF00_0000;
wire master2_target2 = (master2_req`A & 'hFFF0_0000) == 'hFF00_0000;
wire master3_target2 = (master3_req`A & 'hFFF0_0000) == 'hFF00_0000;
/*
* Dummy target the returns all memory as 0. XXX xbar3x2 is cheaper
* so we might drop this dummy target in future.
*/
wire `REQ target3_req;
wire `RES target3_res = 0;
xbar3x3 xbar3x3(clk,
master1_target1, master1_target2, master1_req, master1_res,
master2_target1, master2_target2, master2_req, master2_res,
master3_target1, master3_target2, master3_req, master3_res,
target1_req, target1_res,
target2_req, target2_res,
target3_req, target3_res);
pipechecker check1("bus_ctrl_i", clk, master1_req, master1_res);
pipechecker check2("master2", clk, master2_req, master2_res);
pipechecker check3("master3", clk, master3_req, master3_res);
pipechecker check4("bus_ctrl sram", clk, target1_req, target1_res);
pipechecker check5("bus_ctrl peri", clk, target2_req, target2_res);
pipechecker check6("target3", clk, target3_req, target3_res);
reg r1_ = 0, r2_ = 0, r3_ = 0;
always @(posedge clk) if (debug) begin
r1_ <= master1_req`R;
r2_ <= master2_req`R;
r3_ <= master3_req`R;
if (master1_req`R) $display("%5d BUS_CTRL1: vga [%x]", $time, master1_req`A);
if (master1_res`HOLD) $display("%5d BUS_CTRL1: Stall 1", $time);
if (r1_) $display("%5d BUS_CTRL1: vga -> %x", $time, master1_res`RD);
if (master1_req`W) $display("%5d BUS_CTRL1: store# %x->[%x] (bytena %x)",
$time, master1_req`WD, master1_req`A, master1_req`WBE);
if (master2_req`R) $display("%5d BUS_CTRL2: fetc [%x]", $time, master2_req`A);
if (master2_res`HOLD) $display("%5d BUS_CTRL2: Stall 2", $time);
if (r2_) $display("%5d BUS_CTRL2: fetc -> %x", $time, master2_res`RD);
if (master2_req`W) $display("%5d BUS_CTRL2: store? %x->[%x] (bytena %x)",
$time, master2_req`WD, master2_req`A, master2_req`WBE);
if (master3_req`R) $display("%5d BUS_CTRL3: load [%x]", $time, master3_req`A);
if (master3_res`HOLD) $display("%5d BUS_CTRL3: Stall 3", $time);
if (r3_) $display("%5d BUS_CTRL3: load -> %x", $time, master3_res`RD);
if (master3_req`W) $display("%5d BUS_CTRL3: store %x->[%x] (bytena %x)",
$time, master3_req`WD, master3_req`A, master3_req`WBE);
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A221OI_1_V
`define SKY130_FD_SC_MS__A221OI_1_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog wrapper for a221oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a221oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a221oi_1 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a221oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a221oi_1 (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a221oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A221OI_1_V
|
#include <bits/stdc++.h> using namespace std; void func() { string s; cin >> s; long long n = s.length(); long long i = 1, len = 0, pre[n]; pre[0] = 0; while (i < n) { if (s[i] == s[len]) { len++; pre[i++] = len; } else { if (len == 0) { pre[i++] = 0; } else { len = pre[len - 1]; } } } if (pre[n - 1] == 0) { cout << Just a legend << n ; return; } for (long long i = 0; i < n - 1; ++i) { if (pre[i] == pre[n - 1]) { cout << s.substr(0, pre[n - 1]) << n ; return; } } if (pre[pre[n - 1] - 1] == 0) { cout << Just a legend << n ; return; } cout << s.substr(0, pre[pre[n - 1] - 1]) << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t = 1; while (t--) { func(); } } |
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2.0
// \ \ Application : MIG
// / / Filename : mig_7series_v2_3_axi_fi_xor.v
// /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
// \ \ / \ Date Created : Tue Sept 21 2010
// \___\/\___\
//
//*****************************************************************************
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
module mig_7series_v2_3_fi_xor #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// External Memory Data Width
parameter integer DQ_WIDTH = 72,
parameter integer DQS_WIDTH = 9,
parameter integer nCK_PER_CLK = 4
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] wrdata_in ,
output wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] wrdata_out ,
input wire wrdata_en ,
input wire [DQS_WIDTH-1:0] fi_xor_we ,
input wire [DQ_WIDTH-1:0] fi_xor_wrdata
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam DQ_PER_DQS = DQ_WIDTH / DQS_WIDTH;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg [DQ_WIDTH-1:0] fi_xor_data = {DQ_WIDTH{1'b0}};
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
///////////////////////////////////////////////////////////////////////////////
// Register in the fi_xor_wrdata on a byte width basis
generate
begin
genvar i;
for (i = 0; i < DQS_WIDTH; i = i + 1) begin : assign_fi_xor_data
always @(posedge clk) begin
if (wrdata_en) begin
fi_xor_data[i*DQ_PER_DQS+:DQ_PER_DQS] <= {DQ_PER_DQS{1'b0}};
end
else if (fi_xor_we[i]) begin
fi_xor_data[i*DQ_PER_DQS+:DQ_PER_DQS] <= fi_xor_wrdata[i*DQ_PER_DQS+:DQ_PER_DQS];
end
else begin
fi_xor_data[i*DQ_PER_DQS+:DQ_PER_DQS] <= fi_xor_data[i*DQ_PER_DQS+:DQ_PER_DQS];
end
end
end
end
endgenerate
assign wrdata_out[0+:DQ_WIDTH] = wrdata_in[0+:DQ_WIDTH] ^ fi_xor_data[0+:DQ_WIDTH];
// Pass through upper bits
assign wrdata_out[DQ_WIDTH+:(2*nCK_PER_CLK-1)*DQ_WIDTH] = wrdata_in[DQ_WIDTH+:(2*nCK_PER_CLK-1)*DQ_WIDTH];
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> const double eps = 1e-9; const int inf = 2000000000; const double pi = acos(-1.0); const long long mod = 1000000007; using namespace std; char s[150]; int t; long long d[26 * 100 + 200][130]; int main() { scanf( %d n , &t); memset(d, 0, sizeof(d)); for (int num = 0; num <= 120; num++) for (int sum = 0; sum <= 26 * 100 + 100; sum++) { if (num == 0) { if (sum == 0) d[sum][num] = 1; else break; } else for (int last = 0; last < 26; last++) if (sum - last >= 0) d[sum][num] = (d[sum][num] + d[sum - last][num - 1]) % mod; } for (int it = 0; it < (int)t; it++) { gets(s); int n = (int)strlen(s); int sum = 0; for (int i = 0; i < (int)n; i++) sum += s[i] - a ; printf( %I64d n , (d[sum][n] == 0) ? 1000000006 : (d[sum][n] - 1)); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); long long int n, i, x; cin >> n; long long int a[2 * n]; for (i = 0; i < 2 * n; i++) { cin >> a[i]; } sort(a, a + 2 * n); x = (a[n - 1] - a[0]) * (a[2 * n - 1] - a[n]); for (i = 0; i < n; i++) { x = min(x, (a[i + n - 1] - a[i]) * (a[2 * n - 1] - a[0])); } cout << x; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
class ClsZ;
function new();
$display("ClsZ::new");
endfunction
endclass
class ClsA;
function new();
$display("ClsA::new");
endfunction
function void access;
$display("ClsA::access");
endfunction
endclass
class ClsB;
static ClsZ z = new;
function new();
$display("ClsB::new");
endfunction
function void access;
$display("ClsB::access");
endfunction
endclass
class ClsC;
// Elaboration will call these
static ClsA a = new;
static ClsB b = new;
function new();
$display("ClsC::new");
endfunction
function void access;
$display("ClsC::access");
a = new;
a.access;
endfunction
endclass
module t (/*AUTOARG*/);
function void makec;
ClsC c;
$display("c = new;");
c = new;
$display("c.access;");
c.access;
endfunction
initial begin
$display("makec;");
makec;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// Booth encoding
// TODO: radix-4
module multiplier(
input clk,
input [WIDTH - 1 : 0] a,
input [WIDTH - 1 : 0] b,
output [WIDTH * 2 - 1 : 0] c
);
parameter WIDTH = 2;
wire [WIDTH : 0] _a;
wire [WIDTH : 0] _b;
wire [2 * WIDTH - 1 : 0] _c;
assign _a = { {a[WIDTH - 1]}, {a[WIDTH - 1 : 0]} };
assign _b = { {b[WIDTH - 1]}, {b[WIDTH - 1 : 0]} };
assign c = _c;
_multiplier#(
.WIDTH(WIDTH + 1)
) mult(
.clk(clk),
.a(_a),
.b(_b),
.c(_c)
);
endmodule // multiplier
// Will fail on most negative number
// i.e { {1'b1} , {(WIDTH - 2)'b0} }
// So for e.g WIDTH=4 signed numbers, WIDTH=5 for M
module _multiplier(
input clk,
input [WIDTH - 1 : 0] a,
input [WIDTH - 1 : 0] b,
output [WIDTH * 2 - 1 : 0] c
);
parameter WIDTH = 2;
localparam M_WIDTH = WIDTH;
localparam P_WIDTH = 2 * M_WIDTH;
reg [P_WIDTH - 1 : 0] P [M_WIDTH : 0];
reg signed [M_WIDTH - 1 : 0] M [M_WIDTH : 0];
reg [M_WIDTH - 1 : 0] Q;
assign c = P[M_WIDTH];
always @(a, b)
begin
P[0] <= { {(P_WIDTH){1'b0}}, {a} };
M[0] <= b;
end
always @(posedge clk)
begin
if (P[0][0])
begin
P[1] <= sub_shift_right(P[0], M[0]);
end
else
begin
P[1] <= shift_right(P[0]);
end
Q[0] <= P[0][0];
M[1] <= M[0];
end // always @ (posedge clk)
genvar i;
generate
for (i = 1; i < M_WIDTH; i = i + 1)
begin
always @(posedge clk)
begin
Q[i] <= P[i][0];
M[i + 1] <= M[i];
case( { P[i][0], Q[i - 1] } )
2'b01:
P[i + 1] <= add_shift_right(P[i], M[i]);
2'b10:
P[i + 1] <= sub_shift_right(P[i], M[i]);
default:
P[i + 1] <= shift_right(P[i]);
endcase
end
end // for (i = 0; i < WIDTH; i = i + 1)
endgenerate
function [P_WIDTH - 1 : 0] shift_right(input [P_WIDTH - 1 : 0] x);
shift_right = { {x[P_WIDTH - 1]}, x[P_WIDTH - 1 : 1] };
endfunction // shift_right
function [P_WIDTH - 1 : 0] add_shift_right(input [P_WIDTH - 1 : 0] x, input signed [M_WIDTH - 1 : 0] y);
add_shift_right = shift_right({ {x[P_WIDTH - 1 : M_WIDTH] + y}, {x[M_WIDTH - 1 : 0]} });
endfunction // add_shift_right
function [2 * WIDTH - 1 : 0] sub_shift_right(input [P_WIDTH - 1 : 0] x, input signed [M_WIDTH - 1 : 0] y);
sub_shift_right = shift_right({ {x[P_WIDTH - 1 : M_WIDTH] - y}, {x[M_WIDTH - 1 : 0]} });;
endfunction // sub_shift_right
endmodule // _multiplier
|
#include <bits/stdc++.h> using namespace std; void solve() { long long n; cin >> n; vector<int> res; for (int i = n + 1;; i++) { if (res.size() == n) { break; } res.push_back(i); } for (auto x : res) { cout << x << ; } } int main() { long long t = 1; while (t--) { solve(); } return 0; } |
// ghrd_10as066n2_f2sdram2_m.v
// Generated using ACDS version 17.1 240
`timescale 1 ps / 1 ps
module ghrd_10as066n2_f2sdram2_m (
input wire clk_clk, // clk.clk
input wire clk_reset_reset, // clk_reset.reset
output wire [31:0] master_address, // master.address
input wire [31:0] master_readdata, // .readdata
output wire master_read, // .read
output wire master_write, // .write
output wire [31:0] master_writedata, // .writedata
input wire master_waitrequest, // .waitrequest
input wire master_readdatavalid, // .readdatavalid
output wire [3:0] master_byteenable, // .byteenable
output wire master_reset_reset // master_reset.reset
);
ghrd_10as066n2_f2sdram2_m_altera_jtag_avalon_master_171_wqhllki #(
.USE_PLI (0),
.PLI_PORT (50000),
.FIFO_DEPTHS (2)
) f2sdram2_m (
.clk_clk (clk_clk), // input, width = 1, clk.clk
.clk_reset_reset (clk_reset_reset), // input, width = 1, clk_reset.reset
.master_address (master_address), // output, width = 32, master.address
.master_readdata (master_readdata), // input, width = 32, .readdata
.master_read (master_read), // output, width = 1, .read
.master_write (master_write), // output, width = 1, .write
.master_writedata (master_writedata), // output, width = 32, .writedata
.master_waitrequest (master_waitrequest), // input, width = 1, .waitrequest
.master_readdatavalid (master_readdatavalid), // input, width = 1, .readdatavalid
.master_byteenable (master_byteenable), // output, width = 4, .byteenable
.master_reset_reset (master_reset_reset) // output, width = 1, master_reset.reset
);
endmodule
|
//--------------------------------------------------------------------------------
//
// iomodules.v
// Copyright (C) 2011 Ian Davis
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
//
//--------------------------------------------------------------------------------
//
// Details:
// http://www.dangerousprototypes.com/ols
// http://www.gadgetfactory.net/gf/project/butterflylogic
// http://www.mygizmos.org/ols
//
// Standalone instances of I/O pads. Makes it easier to control synth
// tool from removing duplicate registers... Usually that helps, but
// -not- with I/O's which have builtin flops.
//
//--------------------------------------------------------------------------------
//
(* equivalent_register_removal = "no" *)
module outbuf (pad, clk, outsig, oe);
inout pad;
input clk;
input outsig, oe;
reg sampled_outsig, next_sampled_outsig;
reg sampled_oe, next_sampled_oe;
assign pad = (sampled_oe) ? sampled_outsig : 1'bz;
always @ (posedge clk)
begin
sampled_outsig = next_sampled_outsig;
sampled_oe = next_sampled_oe;
end
always @*
begin
#1;
next_sampled_outsig = outsig;
next_sampled_oe = oe;
end
endmodule
(* equivalent_register_removal = "no" *)
module ddr_clkout (pad, clk);
input clk;
output pad;
ODDR2 ddrout (.Q(pad), .D0(1'b0), .D1(1'b1), .C0(!clk), .C1(clk));
endmodule
(* equivalent_register_removal = "no" *)
module ddr_inbuf (clk, pad, indata, indata180);
parameter WIDTH=32;
input clk;
input [WIDTH-1:0] pad;
output [WIDTH-1:0] indata;
output [WIDTH-1:0] indata180;
reg [WIDTH-1:0] indata, indata180, next_indata;
always @(posedge clk) indata = next_indata;
always @(negedge clk) indata180 = next_indata;
always @* begin #1; next_indata = pad; end
endmodule
|
// #####################################################################################
// # Copyright (C) 1991-2008 Altera Corporation
// # Any megafunction design, and related netlist (encrypted or decrypted),
// # support information, device programming or simulation file, and any other
// # associated documentation or information provided by Altera or a partner
// # under Altera's Megafunction Partnership Program may be used only
// # to program PLD devices (but not masked PLD devices) from Altera. Any
// # other use of such megafunction design, netlist, support information,
// # device programming or simulation file, or any other related documentation
// # or information is prohibited for any other purpose, including, but not
// # limited to modification, reverse engineering, de-compiling, or use with
// # any other silicon devices, unless such use is explicitly licensed under
// # a separate agreement with Altera or a megafunction partner. Title to the
// # intellectual property, including patents, copyrights, trademarks, trade
// # secrets, or maskworks, embodied in any such megafunction design, netlist,
// # support information, device programming or simulation file, or any other
// # related documentation or information provided by Altera or a megafunction
// # partner, remains with Altera, the megafunction partner, or their respective
// # licensors. No other licenses, including any licenses needed under any third
// # party's intellectual property, are provided herein.
// #####################################################################################
// #####################################################################################
// # Loopback module for SOPC system simulation with
// # Altera Triple Speed Ethernet (TSE) Megacore
// #
// # Generated at Tue Mar 5 15:23:15 2013 as a SOPC Builder component
// #
// #####################################################################################
// # This is a module used to provide external loopback on the TSE megacore by supplying
// # necessary clocks and default signal values on the network side interface
// # (GMII/MII/TBI/Serial)
// #
// # - by default this module generate clocks for operation in Gigabit mode that is
// # of 8 ns clock period
// # - no support for forcing collision detection and carrier sense in MII mode
// # the mii_col and mii_crs signal always pulled to zero
// # - you are recomment to set the the MAC operation mode using register access
// # rather than directly pulling the control signals
// #
// #####################################################################################
`timescale 1ns / 1ps
module tse_mac3_loopback (
ref_clk,
txp,
rxp
);
output ref_clk;
input txp;
output rxp;
reg clk_tmp;
initial
clk_tmp <= 1'b0;
always
#4 clk_tmp <= ~clk_tmp;
reg reconfig_clk_tmp;
initial
reconfig_clk_tmp <= 1'b0;
always
#20 reconfig_clk_tmp <= ~reconfig_clk_tmp;
assign ref_clk = clk_tmp;
assign rxp=txp;
endmodule
|
#include <bits/stdc++.h> using namespace std; map<string, int> m; string s, c, a; int n, i, p; int main() { for (cin >> n >> s; i < n - 1; i++) { c += s[i]; c += s[i + 1]; m[c]++; if (p < m[c]) p = m[c], a = c; c.clear(); } cout << a; } |
#include <bits/stdc++.h> using namespace std; int pow(int a, int b, int c) { int ret = 1; for (; b; b >>= 1, a = 1LL * a * a % c) if (b & 1) ret = 1LL * ret * a % c; return ret; } const int N = 2e3 + 10, M = 4.05e6 + 10; int h[N], g[N], p[M], n1[M], ee, low[N], dfn[N], dfntot, vis[N], n, m, st[N], top, id[N], tot, sz[N], ans, dp[N], ok[N]; pair<int, int> e[M]; void ae(int *A, int x, int y) { p[ee] = y; n1[ee] = A[x]; A[x] = ee++; } void tarjan(int u, int fa) { vis[u] = 1; low[u] = dfn[u] = ++dfntot; st[++top] = u; for (int i = h[u]; ~i; i = n1[i]) if (p[i] != fa) { if (!vis[p[i]]) tarjan(p[i], u), low[u] = min(low[u], low[p[i]]); else low[u] = min(low[u], dfn[p[i]]); if (low[p[i]] > dfn[u]) { ++tot; while (st[top] != p[i]) id[st[top--]] = tot, sz[tot]++; id[st[top--]] = tot; sz[tot]++; } } } void dfs(int u, int fa) { dp[u] = sz[u]; for (int i = g[u]; ~i; i = n1[i]) if (p[i] != fa) { dfs(p[i], u); dp[u] += dp[p[i]]; } } int main() { scanf( %d%d , &n, &m); memset(h, -1, sizeof(h)); memset(g, -1, sizeof(g)); int x, y; for (int i = 1; i <= m; i++) scanf( %d%d , &x, &y), ae(h, x, y), ae(h, y, x); for (int i = 1; i <= n; i++) if (!vis[i]) tarjan(i, 0); ++tot; while (top) id[st[top--]] = tot, sz[tot]++; for (int i = 1; i <= n; i++) for (int j = h[i]; ~j; j = n1[j]) if (id[i] != id[p[j]]) ae(g, id[i], id[p[j]]); for (int i = 1; i <= tot; i++) ans += sz[i] * (sz[i] - 1); int ret = 0; for (int i = 1; i <= tot; i++) { int tmp = 0; dfs(i, 0); for (int j = 1; j <= tot; j++) tmp += (dp[j] - sz[j]) * sz[j]; for (int j = 0; j <= n; j++) ok[j] = 0; ok[0] = 1; for (int k = g[i]; ~k; k = n1[k]) for (int j = n; j >= dp[p[k]]; j--) ok[j] |= ok[j - dp[p[k]]]; int mx = 0; for (int j = 0; j <= n; j++) if (ok[j]) mx = max(mx, j * (n - sz[i] - j)); ret = max(ret, tmp + mx); } printf( %d n , n + ans + ret); return 0; } |
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
// WARNING! THIS MODULE IS WORK IN PROGRESS! NOT TESTED!
/*
* Possible extra options:
* - delay block that allow SEQ_EXT_START in past (enabled by parameter - for speed needed applications a simple memory circular buffer)
* - SEQ_EXT_START selections as pulse or as gate/enable
* - multi window recording (sorted with but multiple times)
*/
module seq_rec_core
#(
parameter MEM_BYTES = 8*1024,
parameter ABUSWIDTH = 16,
parameter IN_BITS = 8 //4,8,16,32
)(
BUS_CLK,
BUS_RST,
BUS_ADD,
BUS_DATA_IN,
BUS_RD,
BUS_WR,
BUS_DATA_OUT,
SEQ_CLK,
SEQ_IN,
SEQ_EXT_START
);
localparam VERSION = 0;
input wire BUS_CLK;
input wire BUS_RST;
input wire [ABUSWIDTH-1:0] BUS_ADD;
input wire [7:0] BUS_DATA_IN;
input wire BUS_RD;
input wire BUS_WR;
output reg [7:0] BUS_DATA_OUT;
input wire SEQ_CLK;
input wire [IN_BITS-1:0] SEQ_IN;
input wire SEQ_EXT_START;
`include "../includes/log2func.v"
localparam ADDR_SIZEA = `CLOG2(MEM_BYTES);
localparam ADDR_SIZEB = (IN_BITS > 8) ? `CLOG2(MEM_BYTES/(IN_BITS/8)) : `CLOG2(MEM_BYTES*(8/IN_BITS));
reg [7:0] status_regs [15:0];
wire RST;
wire SOFT_RST;
assign RST = BUS_RST || SOFT_RST;
localparam DEF_BIT_OUT = MEM_BYTES;
always @(posedge BUS_CLK) begin
if(RST) begin
status_regs[0] <= 0;
status_regs[1] <= 0;
status_regs[2] <= 0;
status_regs[3] <= DEF_BIT_OUT[7:0]; //bits
status_regs[4] <= DEF_BIT_OUT[15:8]; //bits
end
else if(BUS_WR && BUS_ADD < 16)
status_regs[BUS_ADD[3:0]] <= BUS_DATA_IN;
end
reg [7:0] BUS_IN_MEM;
reg [7:0] BUS_OUT_MEM;
// 1 - finished
wire START;
assign SOFT_RST = (BUS_ADD==0 && BUS_WR);
assign START = (BUS_ADD==1 && BUS_WR);
wire [15:0] CONF_COUNT;
assign CONF_COUNT = {status_regs[4], status_regs[3]};
wire CONF_EN_SEQ_EXT_START;
assign CONF_EN_SEQ_EXT_START = status_regs[2][0];
reg CONF_DONE;
wire [7:0] BUS_STATUS_OUT;
assign BUS_STATUS_OUT = status_regs[BUS_ADD[3:0]];
reg [7:0] BUS_DATA_OUT_REG;
always @ (posedge BUS_CLK) begin
if(BUS_RD)
begin
if(BUS_ADD == 0)
BUS_DATA_OUT_REG <= VERSION;
else if(BUS_ADD == 1)
BUS_DATA_OUT_REG <= {7'b0,CONF_DONE};
else if(BUS_ADD == 2)
BUS_DATA_OUT_REG <= {7'b0,CONF_EN_SEQ_EXT_START};
else if(BUS_ADD == 3)
BUS_DATA_OUT_REG <= CONF_COUNT[15:8];
else if(BUS_ADD == 4)
BUS_DATA_OUT_REG <= CONF_COUNT[7:0];
else if(BUS_ADD < 16)
BUS_DATA_OUT_REG <= BUS_STATUS_OUT;
end
end
reg [ABUSWIDTH-1:0] PREV_BUS_ADD;
always @ (posedge BUS_CLK) begin
if(BUS_RD) begin
PREV_BUS_ADD <= BUS_ADD;
end
end
always @(*) begin
if(PREV_BUS_ADD < 16)
BUS_DATA_OUT = BUS_DATA_OUT_REG;
else if(PREV_BUS_ADD < 16 + MEM_BYTES )
BUS_DATA_OUT = BUS_IN_MEM;
else
BUS_DATA_OUT = 8'hxx;
end
reg [ABUSWIDTH-1:0] out_bit_cnt;
wire [ADDR_SIZEB-1:0] memout_addrb;
assign memout_addrb = out_bit_cnt-1;
wire [ADDR_SIZEA-1:0] memout_addra;
wire [ABUSWIDTH-1:0] BUS_ADD_MEM;
assign BUS_ADD_MEM = BUS_ADD-16;
localparam IN_BYTES = IN_BITS/8;
localparam IN_BYTES_WIDTH = `CLOG2(IN_BYTES);
generate
if (IN_BITS<=8) begin
assign memout_addra = BUS_ADD_MEM;
end else begin
assign memout_addra = {BUS_ADD_MEM[ADDR_SIZEA:IN_BYTES_WIDTH], {(IN_BYTES_WIDTH){1'b0}}} + (IN_BYTES-1) - BUS_ADD_MEM[IN_BYTES_WIDTH-1:0]; //Byte order
end
endgenerate
reg [IN_BITS-1:0] SEQ_IN_MEM;
wire WEA, WEB;
assign WEA = BUS_WR && BUS_ADD >=16 && BUS_ADD < 16+MEM_BYTES && !WEB;
generate
if (IN_BITS==8) begin
(* RAM_STYLE="{BLOCK}" *)
reg [7:0] mem [(2**ADDR_SIZEA)-1:0];
// synthesis translate_off
//to make simulator happy (no X propagation)
integer i;
initial
for(i = 0; i < (2**ADDR_SIZEA); i = i + 1)
mem[i] = 0;
// synthesis translate_on
always @(posedge BUS_CLK) begin
if (WEA)
mem[memout_addra] <= BUS_DATA_IN;
BUS_IN_MEM <= mem[memout_addra];
end
always @(posedge SEQ_CLK)
if(WEB)
mem[memout_addrb] <= SEQ_IN;
end else begin
wire [7:0] douta;
seq_rec_blk_mem memout(
.clka(BUS_CLK), .clkb(SEQ_CLK), .douta(douta), .doutb(),
.wea(WEA), .web(WEB), .addra(memout_addra), .addrb(memout_addrb),
.dina(BUS_DATA_IN), .dinb(SEQ_IN)
);
always@(*) begin
BUS_IN_MEM = douta;
end
end
endgenerate
assign WEB = out_bit_cnt != 0;
wire RST_SYNC;
wire RST_SOFT_SYNC;
cdc_pulse_sync rst_pulse_sync (.clk_in(BUS_CLK), .pulse_in(RST), .clk_out(SEQ_CLK), .pulse_out(RST_SOFT_SYNC));
assign RST_SYNC = RST_SOFT_SYNC || BUS_RST;
wire START_SYNC;
cdc_pulse_sync start_pulse_sync (.clk_in(BUS_CLK), .pulse_in(START), .clk_out(SEQ_CLK), .pulse_out(START_SYNC));
wire [ADDR_SIZEB:0] STOP_BIT;
assign STOP_BIT = CONF_COUNT;
wire START_SYNC_OR_TRIG;
assign START_SYNC_OR_TRIG = START_SYNC | (CONF_EN_SEQ_EXT_START & SEQ_EXT_START);
always @ (posedge SEQ_CLK)
if (RST_SYNC)
out_bit_cnt <= 0;
else if(START_SYNC_OR_TRIG)
out_bit_cnt <= 1;
else if(out_bit_cnt == STOP_BIT)
out_bit_cnt <= out_bit_cnt;
else if(out_bit_cnt != 0)
out_bit_cnt <= out_bit_cnt + 1;
reg DONE;
always @(posedge SEQ_CLK)
if(RST_SYNC | START_SYNC_OR_TRIG)
DONE <= 0;
else if(out_bit_cnt == STOP_BIT)
DONE <= 1;
wire DONE_SYNC;
cdc_pulse_sync done_pulse_sync (.clk_in(SEQ_CLK), .pulse_in(DONE), .clk_out(BUS_CLK), .pulse_out(DONE_SYNC));
always @(posedge BUS_CLK)
if(RST)
CONF_DONE <= 1;
else if(START)
CONF_DONE <= 0;
else if(DONE_SYNC)
CONF_DONE <= 1;
endmodule |
/**
* ------------------------------------------------------------
* Copyright (c) SILAB , Physics Institute of Bonn University
* ------------------------------------------------------------
*/
`timescale 1ps / 1ps
`include "firmware/src/fe65p2_mio.v"
module tb (
input wire FCLK_IN,
//full speed
inout wire [7:0] BUS_DATA,
input wire [15:0] ADD,
input wire RD_B,
input wire WR_B,
//high speed
inout wire [7:0] FD,
input wire FREAD,
input wire FSTROBE,
input wire FMODE,
output wire CLK_BX,
input wire [64*64-1:0] HIT,
input wire TRIGGER,
output wire [1:0] RESET
);
wire [19:0] SRAM_A;
wire [15:0] SRAM_IO;
wire SRAM_BHE_B;
wire SRAM_BLE_B;
wire SRAM_CE1_B;
wire SRAM_OE_B;
wire SRAM_WE_B;
//wire [1:0] RESET;
//wire CLK_BX;
wire TRIGGER_DUT;
wire CLK_CNFG;
wire EN_PIX_SR_CNFG;
wire LD_CNFG;
wire SI_CNFG;
wire SO_CNFG;
wire PIX_D_CONF;
wire CLK_DATA;
wire OUT_DATA;
wire HIT_OR;
wire INJ;
fe65p2_mio fpga (
.FCLK_IN(FCLK_IN),
.BUS_DATA(BUS_DATA),
.ADD(ADD),
.RD_B(RD_B),
.WR_B(WR_B),
.FDATA(FD),
.FREAD(FREAD),
.FSTROBE(FSTROBE),
.FMODE(FMODE),
.SRAM_A(SRAM_A),
.SRAM_IO(SRAM_IO),
.SRAM_BHE_B(SRAM_BHE_B),
.SRAM_BLE_B(SRAM_BLE_B),
.SRAM_CE1_B(SRAM_CE1_B),
.SRAM_OE_B(SRAM_OE_B),
.SRAM_WE_B(SRAM_WE_B),
.DUT_RESET(RESET) ,
.DUT_CLK_BX(CLK_BX),
.DUT_TRIGGER(TRIGGER_DUT),
.DUT_INJ(INJ),
.DUT_CLK_CNFG(CLK_CNFG),
.DUT_EN_PIX_SR_CNFG(EN_PIX_SR_CNFG),
.DUT_LD_CNFG(LD_CNFG),
.DUT_SI_CNFG(SI_CNFG),
.DUT_SO_CNFG(SO_CNFG),
.DUT_PIX_D_CONF(PIX_D_CONF),
.DUT_CLK_DATA(CLK_DATA),
.DUT_OUT_DATA(OUT_DATA),
.DUT_HIT_OR(HIT_OR)
);
wire [64*64-1:0] ANA_HIT;
wire TRIGGER_FE;
assign TRIGGER_FE = TRIGGER_DUT | TRIGGER;
wire PrmpVbp, vthin1, vthin2, vff, VctrCF0, VctrCF1, PrmpVbnFol, vbnLcc, compVbn, preCompVbn, RefVbn;
wire [31:0] test_out1L, test_out1R, test_out2L, test_out2R, test_out2bL, test_out2bR;
wire [63:0] outDiscInvR;
wire HIT_OR_N, OUT_DATA_N;
wire OUT_DATA_P;
fe65p2 dut(
ANA_HIT,
RESET ,
CLK_BX,
TRIGGER_FE,
HIT_OR,
HIT_OR_N,
CLK_CNFG,
EN_PIX_SR_CNFG,
LD_CNFG,
SI_CNFG,
SO_CNFG,
PIX_D_CONF,
CLK_DATA,
OUT_DATA_P,
OUT_DATA_N,
~INJ,
PrmpVbp, vthin1, vthin2, vff, VctrCF0, VctrCF1, PrmpVbnFol, vbnLcc, compVbn, preCompVbn, RefVbn,
test_out1L, test_out1R, test_out2L, test_out2R, test_out2bL, test_out2bR, outDiscInvR
);
assign #5500 OUT_DATA = OUT_DATA_P;
//SRAM Model
reg [15:0] sram [-1:0];
assign SRAM_IO = !SRAM_OE_B ? sram[SRAM_A] : 16'hzzzz;
always@(negedge SRAM_WE_B)
sram[SRAM_A] <= SRAM_IO;
assign ANA_HIT = HIT;
initial begin
$dumpfile("fe65p2.vcd");
$dumpvars(0);
//force dut.i_output_data.iser_div.cnt = 4'b0;
//#10 force CLK_DATA = 4'b0;
//#100000 force CLK_DATA = 4'b1;
//#10000 release CLK_DATA;
//#50000 release dut.i_output_data.iser_div.cnt;
end
endmodule
|
// Copyright 2007, Martin Whitaker.
// This code may be freely copied for any purpose.
module unnamed_generate_block();
localparam up = 1;
wire [2:0] count1;
wire [2:0] count2;
wire [2:0] count3;
generate
if (up)
count_up counter(count1);
else
count_down counter(count1);
endgenerate
generate
if (up)
begin:genblk1
count_up counter(count2);
end
else
begin:genblk1
count_down counter(count2);
end
endgenerate
count_down genblk01(count3);
initial begin:genblk001
reg [2:0] count;
#1 count = 4;
#1 count = 5;
#1 count = 6;
#1 count = 7;
end
always @(genblk0001.counter.count) begin
$display(genblk0001.counter.count);
end
//initial begin
// $dumpfile("dump.vcd");
// $dumpvars;
//end
endmodule
module count_up(output reg [2:0] count);
initial begin
#1 count = 0;
#1 count = 1;
#1 count = 2;
#1 count = 3;
end
endmodule
module count_down(output reg [2:0] count);
initial begin
#1 count = 3;
#1 count = 2;
#1 count = 1;
#1 count = 0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { size_t found; vector<string> str; string a, b, c, in, out; long long i, j, k, m, n, l, t; cin >> t; while (t--) { cin >> in; for (i = 0, j = 0, k = 0; i < in.size(); i++) { if (in[i] == : && i == 0) { i++; j = 1; } if (in[i] == : ) { b = in.substr(j, i - j); if (b == ) k++; str.push_back(b); j = i + 1; } } if (in[in.size() - 1] != : ) { b = in.substr(j, in.size() - j); str.push_back(b); } for (i = 0; i < str.size(); i++) { if (i > 0) cout << : ; if (str[i] == ) { for (j = 0; j < 8 - str.size() + k; j++) { if (j > 0) cout << : ; cout << 0000 ; } } else { if (str[i].size() < 4) { for (l = str[i].size(); l < 4; l++) cout << 0 ; } cout << str[i]; } } cout << endl; str.clear(); in.clear(); k = 0; } return 0; } |
#include <bits/stdc++.h> using namespace std; int N, H, M; int main() { scanf( %d%d:%d , &N, &H, &M); if (N == 24) { if (H / 10 >= 3) H %= 10; if (H / 10 == 2 && H % 10 >= 4) H %= 10; } else { if (H / 10 >= 2) { if (H % 10 == 0) H = H % 10 + 10; else H %= 10; } if (H / 10 == 1 && H % 10 >= 3) H = 10; if (H == 0) H = 1; } if (M / 10 >= 6) M %= 10; printf( %02d:%02d n , H, M); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKBUF_2_V
`define SKY130_FD_SC_HS__CLKBUF_2_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog wrapper for clkbuf with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__clkbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__clkbuf_2 (
X ,
A ,
VPWR,
VGND
);
output X ;
input A ;
input VPWR;
input VGND;
sky130_fd_sc_hs__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__clkbuf_2 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__clkbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKBUF_2_V
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_leds_pio_0 (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 7: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 7: 0] data_out;
wire [ 7: 0] out_port;
wire [ 7: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 255;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[7 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long A = 100000000000000LL, N = 300228; long long t[N * 4], i, j, n, m, a[N], p[N], o, b, l, r; void modi(long long v, long long l, long long r, long long p, long long g) { if (p < l || p > r) return; if (l == r) { t[v] = g; return; } long long mid = (l + r) / 2; if (p <= mid) modi(v * 2, l, mid, p, g); else modi(v * 2 + 1, mid + 1, r, p, g); t[v] = t[v * 2] + t[v * 2 + 1]; } long long get(long long v, long long l, long long r, long long _l, long long _r) { if (_l > _r) return 0; if (l == _l && r == _r) return t[v]; long long mid = (l + r) / 2; return get(v * 2, l, mid, _l, min(_r, mid)) + get(v * 2 + 1, mid + 1, r, max(mid + 1, _l), _r); } int main() { cin >> n; for (i = 1; i <= n; i++) scanf( %d , &a[i]), p[a[i]] = i; for (i = 1; i < n; i++) if (p[i] > p[i + 1]) modi(1, 1, n, i + 1, 1); cin >> m; while (m--) { scanf( %d%d%d , &b, &l, &r); if (b == 1) printf( %d n , get(1, 1, n, l + 1, r) + 1); else { swap(p[a[l]], p[a[r]]), swap(a[l], a[r]); if (p[a[l]] > p[a[l] + 1]) modi(1, 1, n, a[l] + 1, 1); else modi(1, 1, n, a[l] + 1, 0); if (p[a[r]] > p[a[r] + 1]) modi(1, 1, n, a[r] + 1, 1); else modi(1, 1, n, a[r] + 1, 0); if (p[a[l] - 1] > p[a[l]]) modi(1, 1, n, a[l], 1); else modi(1, 1, n, a[l], 0); if (p[a[r] - 1] > p[a[r]]) modi(1, 1, n, a[r], 1); else modi(1, 1, n, a[r], 0); } } } |
#include <bits/stdc++.h> using namespace std; const long double pi = 3.1415926535897932384626433832795l; template <typename T> inline auto sqr(T x) -> decltype(x * x) { return x * x; } template <typename T1, typename T2> inline bool umx(T1& a, T2 b) { if (a < b) { a = b; return 1; } return 0; } template <typename T1, typename T2> inline bool umn(T1& a, T2 b) { if (b < a) { a = b; return 1; } return 0; } const int K = 5; const int INF = 1e9; struct node { int t[K][K]; node() { for (int i = int(0); i < int(K); ++i) for (int j = int(0); j < int(K); ++j) t[i][j] = INF; for (int i = int(0); i < int(K); ++i) t[i][i] = 0; } }; const int N = 200100; node t[4 * N]; int sz; node botva(node a, node b) { node c; for (int i = int(0); i < int(K); ++i) for (int j = int(i); j < int(K); ++j) { c.t[i][j] = INF; for (int k = int(i); k < int(j + 1); ++k) umn(c.t[i][j], a.t[i][k] + b.t[k][j]); } return c; } node fnd(int i, int x, int y, int l, int r) { if (x > r || y < l) return node(); if (x >= l && y <= r) { return t[i]; } return botva(fnd(2 * i, x, (x + y) >> 1, l, r), fnd(2 * i + 1, ((x + y) >> 1) + 1, y, l, r)); } node fnd(int l, int r) { l += sz, r += sz; if (l == r) { return t[l]; } node left = t[l], right = t[r]; while (l / 2 != r / 2) { if (!(l & 1)) { left = botva(left, t[l + 1]); } if (r & 1) { right = botva(t[r - 1], right); } l >>= 1, r >>= 1; } return botva(left, right); } char c[N]; int main() { cout.setf(ios::showpoint | ios::fixed); cout.precision(20); int n, q; cin >> n >> q; string s; getline(cin, s); gets(c); s = c; string g = 2017 ; sz = 1; while (sz < n) sz <<= 1; for (int i = int(0); i < int(n); ++i) { node& v = t[i + sz]; for (int j = int(0); j < int(((int)(g).size())); ++j) { if (g[j] == s[i]) { v.t[j][j] = 1; v.t[j][j + 1] = 0; } } if (s[i] == 6 ) { v.t[3][3] = v.t[4][4] = 1; } } for (int i = int(sz) - 1; i >= int(1); --i) { t[i] = botva(t[2 * i], t[2 * i + 1]); } for (int i = int(0); i < int(q); ++i) { int l, r; scanf( %d%d , &l, &r); l--, r--; node res = fnd(1, 0, sz - 1, l, r); if (res.t[0][4] >= INF) { printf( -1 n ); } else { printf( %d n , res.t[0][4]); } } return 0; } |
/*
* chained_pll_tb.v: Test bench for chained plls.
* author: Till Mahlburg
* year: 2020
* organization: Universität Leipzig
* license: ISC
*
*/
`timescale 1 ns / 1 ps
`ifndef WAIT_INTERVAL
`define WAIT_INTERVAL 1000
`endif
`ifndef CLKIN1_PERIOD
`define CLKIN1_PERIOD 5
`endif
`ifndef CLKFBOUT_MULT
`define CLKFBOUT_MULT 5
`endif
`ifndef DIVCLK_DIVIDE
`define DIVCLK_DIVIDE 1
`endif
/* number of PLLs which are chained after one another */
`ifndef PLL_NUM
`define PLL_NUM 3
`endif
module chained_pll_tb ();
reg rst;
reg clk;
integer pass_count;
integer fail_count;
/* adjust according to the number of test cases */
localparam total = (`PLL_NUM + 7);
wire [(`PLL_NUM - 1):0] CLKOUT[5:0];
wire [(`PLL_NUM):0] CLKFBOUT;
wire [(`PLL_NUM - 1):0] LOCKED;
assign CLKFBOUT[0] = CLKFBOUT[`PLL_NUM];
wire [31:0] period_1000[0:5];
wire [31:0] period_1000_fb;
genvar i;
generate
for (i = 0; i < `PLL_NUM; i = i + 1) begin : pll
PLLE2_BASE #(
.CLKFBOUT_MULT(`CLKFBOUT_MULT),
.CLKFBOUT_PHASE(0.0),
.CLKIN1_PERIOD(`CLKIN1_PERIOD),
.DIVCLK_DIVIDE(`DIVCLK_DIVIDE)) pll (
.CLKOUT0(CLKOUT[0][i]),
.CLKOUT1(CLKOUT[1][i]),
.CLKOUT2(CLKOUT[2][i]),
.CLKOUT3(CLKOUT[3][i]),
.CLKOUT4(CLKOUT[4][i]),
.CLKOUT5(CLKOUT[5][i]),
.CLKFBOUT(CLKFBOUT[i+1]),
.CLKFBIN(CLKFBOUT[i]),
.LOCKED(LOCKED[i]),
.RST(rst),
.CLKIN1(clk),
.PWRDWN(1'b0));
end
for (i = 0; i <= 5; i = i + 1) begin : period_count
period_count period_count (
.RST(rst),
.clk(CLKOUT[i][`PLL_NUM - 1]),
.period_length_1000(period_1000[i]));
end
endgenerate
period_count period_count_fb (
.RST(rst),
.clk(CLKFBOUT[`PLL_NUM - 1]),
.period_length_1000(period_1000_fb));
integer k;
initial begin
$dumpfile("chained_pll_tb.vcd");
$dumpvars(0, chained_pll_tb);
rst = 0;
clk = 0;
pass_count = 0;
fail_count = 0;
#10;
rst = 1;
#10;
/* TEST CASES */
for (k = 0; k < `PLL_NUM; k = k + 1) begin
if ((CLKOUT[0][k] & CLKOUT[1][k] & CLKOUT[2][k] & CLKOUT[3][k] & CLKOUT[4][k] & CLKOUT[5][k] & CLKFBOUT[k+1] & LOCKED[k]) == 0) begin
$display("PASSED: RST on PLL %0d", k);
pass_count = pass_count + 1;
end else begin
$display("FAILED: RST on PLL %0d", k);
fail_count = fail_count + 1;
end
end
rst = 0;
#`WAIT_INTERVAL;
for (k = 0; k <= 5; k = k + 1) begin
if ((period_1000[k] / 1000.0) == (`CLKIN1_PERIOD * ((`DIVCLK_DIVIDE * 1.0) / `CLKFBOUT_MULT))) begin
$display("PASSED: CLKOUT%0d frequency", k);
pass_count = pass_count + 1;
end else begin
$display("FAILED: CLKOUT%0d frequency", k);
fail_count = fail_count + 1;
end
end
if ((period_1000_fb / 1000.0) == (`CLKIN1_PERIOD * ((`DIVCLK_DIVIDE * 1.0) / `CLKFBOUT_MULT))) begin
$display("PASSED: CLKFBOUT frequency");
pass_count = pass_count + 1;
end else begin
$display("FAILED: CLKFBOUT frequency");
fail_count = fail_count + 1;
end
if ((pass_count + fail_count) == total) begin
$display("PASSED: number of test cases");
pass_count = pass_count + 1;
end else begin
$display("FAILED: number of test cases");
fail_count = fail_count + 1;
end
$display("%0d/%0d PASSED", pass_count, (total + 1));
$finish;
end
always #(`CLKIN1_PERIOD / 2.0) clk <= ~clk;
endmodule
|
`include "senior_defines.vh"
module fwd_ctrl(
input wire[`FWD_CTRL_WIDTH-1:0] ctrl_i,
input wire condition_p4_i,
input wire condition_p5_i,
input wire condition_wb_i,
input wire [`RF_CTRL_WIDTH-1:0] rf_ctrl_i,
output reg [`FWDMUX_CTRL_WIDTH-1:0] fwdmux_ctrl_o
);
wire p5_mux_mac;
//p5 in mac wants to write to rf?
assign p5_mux_mac = (ctrl_i`FWD_WB_MUX_SEL_P5 == 4'b0001) ? 1'b1 : 1'b0;
//operand A
always@* begin
fwdmux_ctrl_o`FWDMUX_OPA = 0;
casex({rf_ctrl_i`RF_OPA, 1'b1, p5_mux_mac})
{1'b0, ctrl_i`FWD_RF_WRITE_CTRL_P4, 1'bx}: begin
if((ctrl_i`FWD_WB_MUX_SEL_P4 == 4'b0010) && condition_p4_i)
fwdmux_ctrl_o`FWDMUX_OPA = 1;
end
{1'b0, ctrl_i`FWD_RF_WRITE_CTRL_P5, 1'b1}: begin
if(condition_p5_i)
fwdmux_ctrl_o`FWDMUX_OPA = 4;
end
{1'b0, rf_ctrl_i`RF_WRITE_REG_SEL, rf_ctrl_i`RF_WRITE_REG_EN, 1'bx}: begin
if(condition_wb_i)
fwdmux_ctrl_o`FWDMUX_OPA = 2;
end
{1'b0, rf_ctrl_i`RF_WRITE_REG_SEL_DM, rf_ctrl_i`RF_WRITE_REG_EN_DM, 1'bx}:
fwdmux_ctrl_o`FWDMUX_OPA = 3;
endcase
end
//operand B
always@* begin
fwdmux_ctrl_o`FWDMUX_OPB = 0;
casex({rf_ctrl_i`RF_OPB, 1'b1, p5_mux_mac})
{1'b0, ctrl_i`FWD_RF_WRITE_CTRL_P4, 1'bx}: begin
if((ctrl_i`FWD_WB_MUX_SEL_P4 == 4'b0010) && condition_p4_i)
fwdmux_ctrl_o`FWDMUX_OPB = 1;
end
{1'b0, ctrl_i`FWD_RF_WRITE_CTRL_P5, 1'b1}: begin
if(condition_p5_i)
fwdmux_ctrl_o`FWDMUX_OPB = 4;
end
{1'b0, rf_ctrl_i`RF_WRITE_REG_SEL, rf_ctrl_i`RF_WRITE_REG_EN, 1'bx}: begin
if(condition_wb_i)
fwdmux_ctrl_o`FWDMUX_OPB = 2;
end
{1'b0, rf_ctrl_i`RF_WRITE_REG_SEL_DM, rf_ctrl_i`RF_WRITE_REG_EN_DM, 1'bx}:
fwdmux_ctrl_o`FWDMUX_OPB = 3;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mod = 998244353; map<int, int> mmp; long long qpow(long long a, long long b, long long m) { long long ans = 1, aa = a; while (b) { if (b & 1) ans = ans * aa % m; aa = aa * aa % m; b >>= 1; } return ans; } int a[200010]; int ccc[200010]; int main() { int n, i, x = 1; cin >> n; for (i = 1; i <= n; i++) { cin >> a[i]; mmp[a[i]] = i; } int pos = 1; ccc[0] = mmp[a[1]]; int num = 0; while (pos <= n) { while (pos <= n) { ccc[num] = max(mmp[a[pos]], ccc[num]); if (pos == ccc[num]) break; pos++; } if (pos == n) break; pos++; num++; } cout << qpow(2, num, mod) << endl; } |
//------------------------------------------------------------------------------
// YF32 -- A small SOC implementation based on mlite (32-bit RISC CPU)
// @Taiwan
//------------------------------------------------------------------------------
//
// YF32 - A SOC implementation based on verilog ported mlite (32-bit RISC CPU)
// Copyright (C) 2003-2004 Yung-Fu Chen ()
//
// This code is free software; you can redistribute it and/or modify it under
// the terms of the GNU Lesser General Public License as published by the Free
// Software Foundation; either version 2.1 of the License, or (at your option)
// any later version.
//
// This code is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
// for more details.
//
// Full details of the license can be found in
// http://www.gnu.org/copyleft/gpl.html
//
//------------------------------------------------------------------------------
// FETURE
// . verilog ported mlite included
// . wishbone bus support
// . simple_pic (programmable interrupt controller)
// . most MIPS-I(TM) opcode support
// . do not support excption
// . do not support "unaligned memory accesses"
// . only user mode support
// . 32K byte ROM
// . 2K byte SRAM
// . UART/Timer are not fully tested yet
// . no internal tri-state bus
// TO DO
// . integrate UART
// . integrate LCD/VGA Controller
// . integrete PS/2 interface
//
//------------------------------------------------------------------------------
// Note:
// MIPS(R) is a registered trademark and MIPS I(TM) is a trademark of
// MIPS Technologies, Inc. in the United States and other countries.
// MIPS Technologies, Inc. does not endorse and is not associated with
// this project. OpenCores and Steve Rhoads are not affiliated in any way
// with MIPS Technologies, Inc.
//------------------------------------------------------------------------------
//
// FILE: yf32_core.v (mlite CPU core with Wishbone I/F)
//
// Vertsion: 1.0
//
// Date: 2004/03/29
//
// Author: Yung-Fu Chen ()
//
// MODIFICATION HISTORY:
// Date By Version Change Description
//============================================================
// 2004/03/29 yfchen 1.0 1st version
//------------------------------------------------------------------------------
module yf32_core (CLK_I, RST_I, ADR_O, DAT_I, DAT_O, WE_O, SEL_O,
STB_O, ACK_I, CYC_O, INT_I);
input CLK_I;
input RST_I;
input [31:0] DAT_I;
input ACK_I;
input INT_I;
output [31:0] ADR_O;
output [31:0] DAT_O;
output WE_O;
output [ 3:0] SEL_O;
output STB_O;
output CYC_O;
wire STB_O = ~RST_I;
wire CYC_O = ~RST_I;
mlite_cpu u1_cpu(
.clk (CLK_I ),
.reset_in (RST_I ),
.intr_in (INT_I ),
.mem_address (ADR_O ),
.mem_data_w (DAT_O ),
.mem_data_r (DAT_I ),
.mem_byte_sel (SEL_O ),
.mem_write (WE_O ),
.mem_pause (~ACK_I )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> inline T sqr(T x) { return x * x; } const double EPS = 1e-6; const int INF = 0x3fffffff; const long long LINF = INF * 1ll * INF; const double PI = acos(-1.0); using namespace std; char g[505][505]; int cnt[505]; int dp[2][505][505]; int C[505][505]; int mod; void Add(int &ans, int v) { ans += v; if (ans >= mod) ans -= mod; } int main(void) { int n, m; scanf( %d %d %d , &n, &m, &mod); C[0][0] = 1; for (int i = 1; i <= n; i++) { C[i][0] = 1; for (int j = 1; j <= i; j++) C[i][j] = (C[i - 1][j - 1] + C[i - 1][j]) % mod; } for (int i = 0; i < (m); ++i) { scanf( %s , g[i]); for (int j = 0; j < (n); ++j) cnt[j] += g[i][j] - 0 ; } int cnt0 = 0, cnt1 = 0; for (int i = 0; i < (n); ++i) { if (cnt[i] > 2) { puts( 0 ); return 0; } if (cnt[i] == 1) cnt1++; else if (cnt[i] == 0) cnt0++; } int now = 0; dp[now][cnt0][cnt1] = 1; for (int i = m; i < n; i++) { memset(dp[now ^ 1], 0, sizeof(dp[now ^ 1])); for (int j = 0; j <= n; j++) { for (int k = 0; k + j <= n; k++) { if (dp[now][j][k] == 0) continue; if (j >= 2) Add(dp[now ^ 1][j - 2][k + 2], 1ll * C[j][2] * dp[now][j][k] % mod); if (k >= 2) Add(dp[now ^ 1][j][k - 2], 1ll * C[k][2] * dp[now][j][k] % mod); if (j && k) Add(dp[now ^ 1][j - 1][k], 1ll * C[k][1] * C[j][1] % mod * dp[now][j][k] % mod); } } now ^= 1; } printf( %d n , dp[now][0][0]); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O31AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__O31AI_BEHAVIORAL_PP_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__o31ai (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O31AI_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int DBG = 0, INF = int(1e9); string toString(long long k) { stringstream ss; ss << k; string res; ss >> res; return res; } int toInt(string s) { stringstream ss; ss << s; int res; ss >> res; return res; } int main() { ios_base::sync_with_stdio(0); cout.setf(ios::fixed); cout << setprecision(10); int n, a, d; cin >> n >> a >> d; vector<pair<int, int> > V(n); for (int _n = (n), i = 0; i < _n; ++i) cin >> V[i].first >> V[i].second; double prev = -1; for (int _n = (n), i = 0; i < _n; ++i) { double accTime = double(V[i].second) / double(a); double accDst = double(V[i].second) * accTime * 0.5; if (accDst >= d) { double t = sqrt((2. * double(d)) / double(a)); prev = max(t + double(V[i].first), prev); } else { double remDst = d - accDst; double remTime = remDst / double(V[i].second); prev = max(accTime + remTime + double(V[i].first), prev); } cout << prev << endl; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O2BB2A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__O2BB2A_FUNCTIONAL_PP_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__o2bb2a (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
and and0 (and0_out_X , nand0_out, or0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O2BB2A_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); long long int x1, y1; cin >> x1 >> y1; long long int x2, y2; cin >> x2 >> y2; int n; cin >> n; int ans = 0; for (int i = 0; n > i; i++) { long long int a, b, c; cin >> a >> b >> c; long long int res1 = a * x1 + b * y1 + c; long long int res2 = a * x2 + b * y2 + c; if ((res1 < 0 && res2 > 0) || (res1 > 0 && res2 < 0)) { ans++; } } cout << ans; } |
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate 3 way fork. Bug report 228.
module test;
reg a,b,c;
reg error;
initial
begin
error = 0;
fork
a = 1;
b = 0;
c = 1;
join
if(a !== 1)
begin
$display("FAILED - a not set to 1");
error = 1;
end
if(b !== 0)
begin
$display("FAILED - b not set to 0");
error = 1;
end
if(c !== 1)
begin
$display("FAILED - c not set to 1");
error = 1;
end
if(error == 0)
$display("PASSED");
end
endmodule
|
/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
/***************************************************************************
****************************************************************************
***
*** Program File: @(#)macros.v
***
****************************************************************************
****************************************************************************/
module Mflipflop_8 (out, din, clock, enable_l) ;
output [7:0] out ;
input [7:0] din ;
input clock ;
input enable_l ;
Mflipflop Mflipflop_7_0 (out[0], din[0], clock, enable_l);
Mflipflop Mflipflop_7_1 (out[1], din[1], clock, enable_l);
Mflipflop Mflipflop_7_2 (out[2], din[2], clock, enable_l);
Mflipflop Mflipflop_7_3 (out[3], din[3], clock, enable_l);
Mflipflop Mflipflop_7_4 (out[4], din[4], clock, enable_l);
Mflipflop Mflipflop_7_5 (out[5], din[5], clock, enable_l);
Mflipflop Mflipflop_7_6 (out[6], din[6], clock, enable_l);
Mflipflop Mflipflop_7_7 (out[7], din[7], clock, enable_l);
endmodule
|
#include <bits/stdc++.h> //#include <ext/pb_ds/assoc_container.hpp> //using namespace __gnu_pbds; using namespace std; typedef long long ll; typedef long double ld; //typedef tree<int,null_type,less<int >,rb_tree_tag,tree_order_statistics_node_update>indexed_set; template<class T1, class T2> ostream &operator <<(ostream &os, pair<T1,T2>&p); template <class T> ostream &operator <<(ostream &os, vector<T>&v); template <class T> ostream &operator <<(ostream &os, set<T>&v); template <class T1, class T2> ostream &operator <<(ostream &os, map<T1,T2>&v); #ifdef APURBA #define HERE cout<< here - <<__LINE__<< n ; #define debug(args...) { string _s = #args; replace(_s.begin(), _s.end(), , , ); stringstream _ss(_s); istream_iterator<string> _it(_ss); err(_it, args); } void err(istream_iterator<string> it) { cout<<endl; } template<typename T, typename... Args> void err(istream_iterator<string> it, T a, Args... args) { cout << *it << = << a << ; err(++it, args...); } #else #define HERE #define debug(args...) #endif const int N = 5e5 +5; const ll mod = 1e9 + 7; typedef pair<int,int> pii; struct info{ int zero , one; int lazy; info() { zero = 0; one = 0; lazy = 0; } }; struct segtree{ int n; vector<info>t; segtree(int n, string &s) { this->n = n; t.resize(n*4); build(1,0,n-1,s); } void Merge(info &node , info &l , info &r) { node.zero = l.zero + r.zero; node.one = l.one + r.one; } void build(int node, int l ,int r,string &s) { if(l==r) { if(s[l]== 0 ) { t[node].zero = 1; } else{ t[node].one = 1; } return; } int mid= (l+r)/2; build(node*2 , l, mid,s); build(node *2 +1 , mid+1, r,s); Merge(t[node], t[node*2] , t[node *2+1]); } void push_down(int node , int l, int r, int b, int mid , int e) { if(t[node].lazy==1) { t[l].zero = (mid-b+1); t[l].one = 0; t[l].lazy = 1; t[r].zero = (e-mid); t[r].one = 0; t[r].lazy = 1; t[node].lazy =0; } else if(t[node].lazy == 2) { t[l].one = (mid-b+1); t[l].zero = 0; t[l].lazy = 2; t[r].one = (e-mid); t[r].zero = 0; t[r].lazy = 2; t[node].lazy =0; } } void update(int node, int l ,int r , int i, int j, int add) { if(l>j || r<i) { return; } if(l>=i && r<=j) { if(add==0) { t[node].zero = (r-l+1); t[node].one = 0; t[node].lazy = 1; } else{ t[node].one = (r-l+1); t[node].zero = 0; t[node].lazy = 2; } return; } int mid = (l+r)/2; push_down(node, node*2, node*2+1 , l, mid, r); update(node *2 , l ,mid , i, j, add); update(node *2 +1 , mid+1 , r , i, j, add); Merge(t[node] , t[node *2] , t[node*2+1]); } void update(int l ,int r, int add) { update(1,0,n-1,l,r,add); } info query(int node, int l, int r, int i, int j) { if(l>j || r<i) { info tmp; return tmp; } if(l>=i && r<=j) { return t[node]; } int mid = (l+r)/2; push_down(node, node*2, node*2+1,l,mid,r); info x = query(node *2 , l ,mid , i, j); info y = query(node *2 +1 , mid+1 , r , i, j); info ret; Merge(ret , x, y); return ret; } pii query(int l, int r) { info ret = query(1,0,n-1,l,r); return make_pair(ret.zero , ret.one); } void show() { for(int i=0;i<n;i++) { pii tmp = query(i,i); cout<<tmp<< ; } cout<<endl; } }; void TEST_CASES(int cas) { int n,q; string s,t; cin>>n>>q>>s>>t; vector<pii>a(q); for(int i=0;i<q;i++) { int l,r; cin>>l>>r; l--; r--; a[i] = {l,r}; } segtree seg(n,t); //seg.show(); for(int i=q-1;i>=0;i--) { int l = a[i].first , r = a[i].second; int sz = (r-l+1); pii koto = seg.query(l,r); //debug(i,koto); if(koto.first*2<sz) { //HERE; seg.update(l,r,1); } else if(koto.second*2<sz) { seg.update(l,r,0); } else{ cout<< NO n ; return; } //seg.show(); } for(int i=0;i<n;i++) { int eta = s[i]- 0 ; pii bal = seg.query(i,i); if(eta==0 && bal.second==1) { cout<< NO n ; return; } else if(eta==1 && bal.first==1) { cout<< NO n ; return; } } cout<< YES n ; } /* */ int32_t main() { #ifndef APURBA ios_base::sync_with_stdio(false); cin.tie(nullptr); #endif //freopen( input.txt , r ,stdin); //freopen( out1.txt , w ,stdout); int t=1,cas=0; cin>>t; while(t--) { TEST_CASES(++cas); } return 0; } template<class T1, class T2> ostream &operator <<(ostream &os, pair<T1,T2>&p) { os<< { <<p.first<< , <<p.second<< } ; return os; } template <class T> ostream &operator <<(ostream &os, vector<T>&v) { os<< [ ; for(int i=0; i<v.size(); i++) { os<<v[i]<< ; } os<< ] ; return os; } template <class T> ostream &operator <<(ostream &os, set<T>&v) { os<< [ ; for(T i:v) { os<<i<< ; } os<< ] ; return os; } template <class T1, class T2> ostream &operator <<(ostream &os, map<T1,T2>&v) { for(auto i:v) { os<< Key : <<i.first<< , Value : <<i.second<<endl; } return os; } |
#include <bits/stdc++.h> using namespace std; template <class T> void pv(T a, T b) { for (T i = a; i != b; ++i) cout << *i << ; cout << endl; } template <class T> void chmin(T &t, const T &f) { if (t > f) t = f; } template <class T> void chmax(T &t, const T &f) { if (t < f) t = f; } int in() { int x; scanf( %d , &x); return x; } int N, M; int X[1000010], Y[1000010]; int bitN; int bit[2100010]; void bitAdd(int pos, int val) { for (int x = pos; x <= bitN; x += x & -x) bit[x] += val; } int bitLowerBound(int w) { if (w <= 0) return 0; int x = 0; for (int k = bitN; k > 0; k /= 2) { if (x + k <= bitN && bit[x + k] < w) { w -= bit[x + k]; x += k; } } return x + 1; } int perm[1000010]; int ids[2000010]; bool used[1000010]; bool solve() { for (bitN = 2; bitN < M + N + 5; bitN <<= 1) ; memset(bit, 0, sizeof(bit)); memset(perm, ~0, sizeof(perm)); memset(ids, ~0, sizeof(ids)); for (int j = 1; j <= N; ++j) { bitAdd(M + j, +1); ids[M + j] = j; } for (int i = 0; i < M; ++i) { const int pos = bitLowerBound(Y[i]); const int j = ids[pos]; if (!~perm[j]) { perm[j] = X[i]; } if (perm[j] != X[i]) { return false; } bitAdd(pos, -1); bitAdd(M - i, +1); ids[pos] = -1; ids[M - i] = j; } memset(used, 0, sizeof(used)); for (int j = 1; j <= N; ++j) if (~perm[j]) { if (used[perm[j]]) { return false; } used[perm[j]] = true; } int k = 1; for (int j = 1; j <= N; ++j) if (!~perm[j]) { for (; used[k]; ++k) ; perm[j] = k; used[k] = true; } return true; } int main() { for (; ~scanf( %d%d , &N, &M);) { for (int i = 0; i < M; ++i) { X[i] = in(); Y[i] = in(); } bool res = solve(); if (res) { for (int j = 1; j <= N; ++j) { if (j > 1) printf( ); printf( %d , perm[j]); } puts( ); } else { puts( -1 ); } } return 0; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:12:22 08/30/2014
// Design Name: lab4dpath
// Module Name: C:/ece4743/projects/lab4_part1_solution/tb_lab4dpath.v
// Project Name: lab4_part1_solution
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: lab4dpath
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_lab4dpath;
// Inputs
reg [9:0] x1;
reg [9:0] x2;
reg [9:0] x3;
// Outputs
wire [9:0] y;
reg clock;
reg[8*100:1] aline;
`define FSIZE 1024
`define LATENCY 2
integer infifo[(`FSIZE-1):0];
integer head,tail;
integer fd;
integer count,status;
integer i_a, i_b, i_c, i_result;
integer o_a, o_b, o_c, o_result;
integer errors;
integer clock_count;
// Instantiate the Unit Under Test (UUT)
lab4dpath uut (
.x1(x1),
.x2(x2),
.x3(x3),
.clk(clock),
.y(y)
);
initial begin
clock = 0;
#100 //reset delay
forever #25 clock = ~clock;
end
initial begin
// Initialize Inputs
x1 = 0;
x2 = 0;
x3 = 0;
head = 0;
tail = 0;
clock_count = 0;
fd = $fopen("multadd_vectors.txt","r");
count = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
// Add stimulus here
errors = 0;
while ($fgets(aline,fd)) begin
status = $sscanf(aline,"%x %x %x %x",i_a, i_b, i_c, i_result);
@(negedge clock);
x1 = i_a;
x2 = i_b;
x3 = i_c;
infifo[head]=i_a;inc_head;
infifo[head]=i_b;inc_head;
infifo[head]=i_c;inc_head;
infifo[head]=i_result;inc_head;
end //end while
end
task inc_head;
begin
head = head + 1;
if (head == `FSIZE) head = 0;
end
endtask
task inc_tail;
begin
tail = tail + 1;
if (tail == `FSIZE) tail = 0;
end
endtask
always @(negedge clock) begin
clock_count = clock_count + 1;
if (clock_count > `LATENCY+1) begin
o_a = infifo[tail];inc_tail;
o_b = infifo[tail];inc_tail;
o_c = infifo[tail];inc_tail;
o_result = infifo[tail];inc_tail;
if (o_result == y) begin
$display("%d PASS, x1: %x, x2: %x, x3: %x, y: %x\n",count,o_a,o_b,o_c,y);
end else begin
$display("%d FAIL, x1: %x, x2: %x, x3: %x, y (actual): %x, y (expected): %x\n",count,o_a,o_b,o_c,y,o_result);
errors = errors + 1;
end
end //end if
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1510; const int MOD = 1000000007; const int SZ = 100010; inline int add(int u, int v) { return (u += v) >= MOD ? u - MOD : u; } inline int sub(int u, int v) { return (u -= v) < 0 ? u + MOD : u; } inline int mul(int u, int v) { return (long long)u * v % MOD; } inline int power(int u, int v) { int res = 1; while (v) { if (v & 1) res = mul(res, u); u = mul(u, u); v >>= 1; } return res; } inline int inv(int u) { return power(u, MOD - 2); } int n, m, a, b, k, p; int dp[N][N]; int pref[N][N]; int sumG[N], g[N]; int fac[SZ], invFac[SZ]; int comb(int n, int k) { if (k > n || k < 0) return 0; return mul(fac[n], mul(invFac[k], invFac[n - k])); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n >> m; cin >> a >> b; cin >> k; p = mul(a, inv(b)); fac[0] = 1; for (int i = 1; i < SZ; i++) { fac[i] = mul(fac[i - 1], i); } invFac[SZ - 1] = inv(fac[SZ - 1]); for (int i = SZ - 2; i >= 0; i--) { invFac[i] = mul(invFac[i + 1], i + 1); } for (int i = 0; i <= m; i++) { g[i] = comb(k, i); if (g[i] != 0) { g[i] = mul(g[i], power(p, i)); g[i] = mul(g[i], power(sub(1, p), k - i)); } sumG[i] = g[i]; if (i > 0) sumG[i] = add(sumG[i], sumG[i - 1]); } memset(dp, 0, sizeof dp); memset(pref, 0, sizeof pref); dp[0][m] = 1; for (int i = 1; i <= n; i++) { for (int r = 1; r <= m; r++) { int p1 = mul(sumG[r - 1], sub(dp[i - 1][m], dp[i - 1][m - r])); int p2 = pref[i - 1][r - 1]; int foo = mul(sub(p1, p2), g[m - r]); dp[i][r] = add(dp[i][r - 1], foo); pref[i][r] = add(pref[i][r - 1], mul(g[r], dp[i][r])); } } cout << dp[n][m] << endl; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVER2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__BUSDRIVER2_FUNCTIONAL_PP_V
/**
* busdriver2: Bus driver (pmos devices).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__busdriver2 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_teb;
// Name Output Other arguments
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND );
bufif0 bufif00 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVER2_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> const int Maxn = 1000 * 1000 + 10; using namespace std; int main() { vector<int> A[10000]; int B[10000]; int n; cin >> n; n *= 2; int e[10000]; for (int i = 0; i < n; i++) { int a; cin >> a; A[a].push_back(i); B[i] = a; } bool k = true; int size1 = 0, size2 = 0; int s1 = 0, s2 = 0; for (int i = 10; i <= 99; i++) { if (A[i].size() > 1) { for (int j = 0; j < 2; j++) { if (j % 2 == 0) e[A[i][A[i].size() - 1]] = 1; else e[A[i][A[i].size() - 1]] = 2; A[i].pop_back(); } s1++; s2++; size1++; size2++; } else if (A[i].size() == 0) continue; else { if (k) { e[A[i][0]] = 1; size1++; s1++; } else { s2++; size2++; e[A[i][0]] = 2; } k = !k; A[i].pop_back(); } } cout << s1 * s2 << endl; for (int i = 0; i < n; i++) { while (!A[B[i]].empty()) { if (size1 < n / 2) { e[A[B[i]][A[B[i]].size() - 1]] = 1; size1++; A[B[i]].pop_back(); } else { e[A[B[i]][A[B[i]].size() - 1]] = 2; size2++; A[B[i]].pop_back(); } } } for (int i = 0; i < n; i++) { cout << e[i] << ; } cout << endl; return 0; } |
`default_nettype none
module memory_pipe_arbiter(
input wire iCLOCK,
input wire inRESET,
//Data(Core -> Memory)
input wire iDATA_REQ,
output wire oDATA_LOCK,
input wire [1:0] iDATA_ORDER,
input wire [3:0] iDATA_MASK,
input wire iDATA_RW,
input wire [13:0] iDATA_TID,
input wire [1:0] iDATA_MMUMOD,
input wire [31:0] iDATA_PDT,
input wire [31:0] iDATA_ADDR,
input wire [31:0] iDATA_DATA,
//Data(Memory -> Core)
output wire oDATA_REQ,
input wire iDATA_BUSY,
output wire oDATA_PAGEFAULT,
output wire [63:0] oDATA_DATA,
output wire [27:0] oDATA_MMU_FLAGS,
//Inst(Core -> Memory)
input wire iINST_REQ,
output wire oINST_LOCK,
input wire [1:0] iINST_MMUMOD,
input wire [31:0] iINST_PDT,
input wire [31:0] iINST_ADDR,
//Inst(Memory -> Core)
output wire oINST_REQ,
input wire iINST_BUSY,
output wire oINST_PAGEFAULT,
output wire oINST_QUEUE_FLUSH,
output wire [63:0] oINST_DATA,
output wire [27:0] oINST_MMU_FLAGS,
//Memory(OutPort)
output wire oMEMORY_REQ,
input wire iMEMORY_LOCK,
output wire oMEMORY_DATA_STORE_ACK, //1:Data Access && Store(MMUFlag read only. Not Memory access.)
output wire [1:0] oMEMORY_MMU_MODE,
output wire [31:0] oMEMORY_PDT,
output wire [1:0] oMEMORY_ORDER,
output wire [3:0] oMEMORY_MASK,
output wire oMEMORY_RW,
output wire [31:0] oMEMORY_ADDR,
output wire [31:0] oMEMORY_DATA,
//Memory(InPort)
input wire iMEMORY_VALID,
output wire oMEMORY_BUSY,
input wire iMEMORY_STORE_ACK,
input wire iMEMORY_PAGEFAULT,
input wire iMEMORY_QUEUE_FLUSH,
input wire [63:0] iMEMORY_DATA,
input wire [27:0] iMEMORY_MMU_FLAGS
);
/*********************************************************
Wire and Register
*********************************************************/
//Matching Bridge
wire matching_bridfe_wr_full;
wire matching_bridge_rd_valid;
wire matching_bridge_rd_type;
//Core -> Memory
wire mem2core_inst_lock;
wire mem2core_data_lock;
wire core2mem_inst_condition;
wire core2mem_data_condition;
wire core2mem_data_lock = 1'b0;
reg b_core2mem_req;
reg b_core2mem_data_store_ack;
reg [1:0] b_core2mem_order;
reg [3:0] b_core2mem_mask;
reg b_core2mem_rw;
reg [1:0] b_core2mem_mmumod;
reg [13:0] b_core2mem_pdt;
reg [31:0] b_core2mem_addr;
reg [31:0] b_core2mem_data;
//Memory -> Core
reg b_mem2core_inst_valid;
reg b_mem2core_inst_pagefault;
reg b_mem2core_inst_queue_flush;
reg [63:0] b_mem2core_inst_data;
reg [27:0] b_mem2core_inst_mmu_flags;
reg b_mem2core_data_valid;
reg b_mem2core_data_pagefault;
reg [63:0] b_mem2core_data_data;
reg [27:0] b_mem2core_data_mmu_flags;
//Condition
wire mem2core_common_lock = matching_bridfe_wr_full || iMEMORY_LOCK;
wire core2mem_data_write_ack_condition = iDATA_RW && core2mem_data_condition;
wire core2mem_normal_memory_access_condition = (!iDATA_RW && core2mem_data_condition) || core2mem_inst_condition;
/*********************************************************
Memory Matching Controal
*********************************************************/
mist1032sa_arbiter_matching_queue #(16, 4, 1) MEM_MATCHING_BRIDGE( //Queue deep : 16, Queue deep_n : 4, Flag_n : 1
.iCLOCK(iCLOCK),
.inRESET(inRESET),
//Flash
.iFLASH(iMEMORY_QUEUE_FLUSH),
//Write
.iWR_REQ(!mem2core_common_lock && core2mem_normal_memory_access_condition),
.iWR_FLAG(core2mem_data_condition), //0:Inst, 1:Data
.oWR_FULL(matching_bridfe_wr_full),
//Read
.iRD_REQ(iMEMORY_VALID && (matching_bridge_rd_type && !core2mem_data_lock || !matching_bridge_rd_type && !iINST_BUSY) && !iMEMORY_STORE_ACK),
.oRD_VALID(matching_bridge_rd_valid),
.oRD_FLAG(matching_bridge_rd_type), //0:Inst, 1:Data
.oRD_EMPTY()
);
/*********************************************************
Buffer & Assign(Core -> Memory)
*********************************************************/
//assign
assign mem2core_inst_lock = mem2core_common_lock || core2mem_data_condition;
assign mem2core_data_lock = mem2core_common_lock || core2mem_inst_condition;
assign core2mem_inst_condition = !iDATA_REQ && iINST_REQ;
assign core2mem_data_condition = iDATA_REQ;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_core2mem_req <= 1'b0;
b_core2mem_order <= 2'h0;
b_core2mem_mask <= 4'h0;
b_core2mem_rw <= 1'b0;
b_core2mem_data_store_ack <= 1'b0;
b_core2mem_mmumod <= 2'h0;
b_core2mem_pdt <= {32{1'b0}};
b_core2mem_addr <= {32{1'b0}};
b_core2mem_data <= {32{1'b0}};
end
else if(iMEMORY_QUEUE_FLUSH)begin
b_core2mem_req <= 1'b0;
b_core2mem_order <= 2'h0;
b_core2mem_mask <= 4'h0;
b_core2mem_rw <= 1'b0;
b_core2mem_data_store_ack <= 1'b0;
b_core2mem_mmumod <= 2'h0;
b_core2mem_pdt <= {32{1'b0}};
b_core2mem_addr <= {32{1'b0}};
b_core2mem_data <= {32{1'b0}};
end
else begin
if(!mem2core_common_lock)begin
//if(b_io_startaddr_valid )
if(core2mem_data_condition)begin
b_core2mem_req <= 1'b1;
b_core2mem_order <= iDATA_ORDER;
b_core2mem_mask <= iDATA_MASK;
b_core2mem_rw <= iDATA_RW;
b_core2mem_data_store_ack <= core2mem_data_write_ack_condition;
b_core2mem_mmumod <= iDATA_MMUMOD;
b_core2mem_pdt <= iDATA_PDT;
b_core2mem_addr <= iDATA_ADDR;
b_core2mem_data <= iDATA_DATA;
end
else if(core2mem_inst_condition)begin
b_core2mem_req <= 1'b1;
b_core2mem_order <= 2'h2;
b_core2mem_mask <= 4'hff;
b_core2mem_rw <= 1'b0;
b_core2mem_data_store_ack <= 1'b0;
b_core2mem_mmumod <= iINST_MMUMOD;
b_core2mem_pdt <= iINST_PDT;
b_core2mem_addr <= iINST_ADDR;
b_core2mem_data <= {32{1'b0}};
end
else begin
b_core2mem_req <= 1'b0;
end
end
end
end
/*********************************************************
Inst Data Selector & Buffer & assign (Memory -> Core)
*********************************************************/
//Inst
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_mem2core_inst_valid <= 1'b0;
b_mem2core_inst_pagefault <= 1'b0;
b_mem2core_inst_queue_flush <= 1'b0;
b_mem2core_inst_data <= {63{1'b0}};
b_mem2core_inst_mmu_flags <= 28'h0;
end
else begin
if(!iINST_BUSY)begin
b_mem2core_inst_valid <= !matching_bridge_rd_type && matching_bridge_rd_valid && !iMEMORY_STORE_ACK && iMEMORY_VALID;
b_mem2core_inst_pagefault <= iMEMORY_PAGEFAULT;
b_mem2core_inst_queue_flush <= iMEMORY_QUEUE_FLUSH;
b_mem2core_inst_data <= iMEMORY_DATA;
b_mem2core_inst_mmu_flags <= iMEMORY_MMU_FLAGS;
end
end
end
//Data
assign core2mem_data_lock = 1'b0;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_mem2core_data_valid <= 1'b0;
b_mem2core_data_pagefault <= 1'b0;
b_mem2core_data_data <= {63{1'b0}};
b_mem2core_data_mmu_flags <= 28'h0;
end
else begin
if(!core2mem_data_lock)begin
b_mem2core_data_valid <= ((matching_bridge_rd_type && matching_bridge_rd_valid) || iMEMORY_STORE_ACK) && iMEMORY_VALID;
b_mem2core_data_pagefault <= iMEMORY_PAGEFAULT;
b_mem2core_data_data <= iMEMORY_DATA;
b_mem2core_data_mmu_flags <= iMEMORY_MMU_FLAGS;
end
end
end
/*********************************************************
Assign
*********************************************************/
assign oDATA_LOCK = mem2core_data_lock;
assign oINST_LOCK = mem2core_inst_lock;
assign oMEMORY_REQ = b_core2mem_req;
assign oMEMORY_DATA_STORE_ACK = b_core2mem_data_store_ack;
assign oMEMORY_MMU_MODE = b_core2mem_mmumod;
assign oMEMORY_PDT = b_core2mem_pdt;
assign oMEMORY_ORDER = b_core2mem_order;
assign oMEMORY_MASK = b_core2mem_mask;
assign oMEMORY_RW = b_core2mem_rw;
assign oMEMORY_ADDR = b_core2mem_addr;
assign oMEMORY_DATA = b_core2mem_data;
assign oMEMORY_BUSY = iDATA_BUSY || iINST_BUSY;
assign oDATA_REQ = b_mem2core_data_valid && !core2mem_data_lock;
assign oDATA_PAGEFAULT = b_mem2core_data_pagefault;
assign oDATA_DATA = b_mem2core_data_data;
assign oDATA_MMU_FLAGS = b_mem2core_data_mmu_flags;
assign oINST_REQ = b_mem2core_inst_valid && !iINST_BUSY;
assign oINST_PAGEFAULT = b_mem2core_inst_pagefault;
assign oINST_QUEUE_FLUSH = b_mem2core_inst_queue_flush;
assign oINST_DATA = b_mem2core_inst_data;
assign oINST_MMU_FLAGS = b_mem2core_inst_mmu_flags;
endmodule
`default_nettype wire
|
/*
* Copyright (c) 2015-2017 The Ultiparc Project. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* Long integer multiplication
*/
`include "uparc_cpu_config.vh"
`include "uparc_cpu_common.vh"
`include "uparc_cpu_const.vh"
/* Multiplication */
module uparc_long_imul(
clk,
nrst,
multiplicand,
multiplier,
start,
signd,
ready,
product
);
input wire clk;
input wire nrst;
input wire [`UPARC_REG_WIDTH-1:0] multiplicand;
input wire [`UPARC_REG_WIDTH-1:0] multiplier;
input wire start;
input wire signd;
output wire ready;
output wire [2*`UPARC_REG_WIDTH-1:0] product;
/* Local registers */
reg [5:0] nbit;
reg [2*`UPARC_REG_WIDTH-1:0] prod;
reg [`UPARC_REG_WIDTH-1:0] abs_multiplicand;
assign ready = !nbit && !start;
assign product = (signd && (multiplicand[`UPARC_REG_WIDTH-1] ^ multiplier[`UPARC_REG_WIDTH-1])) ?
-prod : prod;
always @(posedge clk or negedge nrst)
begin
if(!nrst)
begin
nbit <= 6'b0;
prod <= {(2*`UPARC_REG_WIDTH){1'b0}};
abs_multiplicand <= {(`UPARC_REG_WIDTH){1'b0}};
end
else if(start)
begin
if(!multiplicand || !multiplier)
begin
nbit <= 6'b0;
prod <= {(2*`UPARC_REG_WIDTH){1'b0}};
end
else
begin
nbit <= 6'd`UPARC_REG_WIDTH;
prod <= { {(`UPARC_REG_WIDTH){1'b0}}, signd && multiplier[`UPARC_REG_WIDTH-1] ?
-multiplier : multiplier };
abs_multiplicand <= signd && multiplicand[`UPARC_REG_WIDTH-1] ?
-multiplicand : multiplicand;
end
end
else if(nbit)
begin
nbit <= nbit - 1'b1;
if(prod[0])
begin
prod[2*`UPARC_REG_WIDTH-1:`UPARC_REG_WIDTH-1] <=
prod[2*`UPARC_REG_WIDTH-1:`UPARC_REG_WIDTH] + abs_multiplicand;
prod[`UPARC_REG_WIDTH-2:0] <= prod[`UPARC_REG_WIDTH-1:1];
end
else
prod <= { 1'b0, prod[2*`UPARC_REG_WIDTH-1:1] };
end
end
endmodule /* uparc_long_imul */
|
/*
* mmcme2_base.v: Simulates the MMCME2_BASE pll of the Xilinx 7 series. This
* is just a wrapper around the actual logic found in pll.v
* author: Till Mahlburg
* year: 2020
* organization: Universität Leipzig
* license: ISC
*
*/
`timescale 1 ns / 1 ps
/* A reference for the interface can be found in Xilinx UG953 page 461ff */
module MMCME2_BASE #(
/* not implemented */
parameter BANDWIDTH = "OPTIMIZED",
parameter CLKFBOUT_MULT_F = 5.000,
parameter CLKFBOUT_PHASE = 0.000,
/* is ignored, but should be set */
parameter CLKIN1_PERIOD = 0.000,
parameter CLKOUT0_DIVIDE_F = 1.000,
parameter CLKOUT1_DIVIDE = 1,
parameter CLKOUT2_DIVIDE = 1,
parameter CLKOUT3_DIVIDE = 1,
parameter CLKOUT4_DIVIDE = 1,
parameter CLKOUT5_DIVIDE = 1,
parameter CLKOUT6_DIVIDE = 1,
parameter CLKOUT0_DUTY_CYCLE = 0.500,
parameter CLKOUT1_DUTY_CYCLE = 0.500,
parameter CLKOUT2_DUTY_CYCLE = 0.500,
parameter CLKOUT3_DUTY_CYCLE = 0.500,
parameter CLKOUT4_DUTY_CYCLE = 0.500,
parameter CLKOUT5_DUTY_CYCLE = 0.500,
parameter CLKOUT6_DUTY_CYCLE = 0.500,
parameter CLKOUT0_PHASE = 0.000,
parameter CLKOUT1_PHASE = 0.000,
parameter CLKOUT2_PHASE = 0.000,
parameter CLKOUT3_PHASE = 0.000,
parameter CLKOUT4_PHASE = 0.000,
parameter CLKOUT5_PHASE = 0.000,
parameter CLKOUT6_PHASE = 0.000,
parameter CLKOUT4_CASCADE = "FALSE",
parameter DIVCLK_DIVIDE = 1,
/* both not implemented */
parameter REF_JITTER1 = 0.010,
parameter STARTUP_WAIT = "FALSE",
/* Setting the FPGA model and speed grade allows a more realistic
* simulation. Default values are the most restrictive */
parameter FPGA_TYPE = "ARTIX",
parameter SPEED_GRADE = "-1")(
output CLKOUT0,
output CLKOUT0B,
output CLKOUT1,
output CLKOUT1B,
output CLKOUT2,
output CLKOUT2B,
output CLKOUT3,
output CLKOUT3B,
output CLKOUT4,
output CLKOUT5,
output CLKOUT6,
/* PLL feedback output. */
output CLKFBOUT,
output CLKFBOUTB,
output LOCKED,
input CLKIN1,
/* PLL feedback input. Is ignored in this implementation, but should be connected to CLKFBOUT for internal feedback. */
input CLKFBIN,
/* Used to power down instatiated but unused PLLs */
input PWRDWN,
input RST);
wire [15:0] DO;
wire DRDY;
pll #(
.BANDWIDTH(BANDWIDTH),
.CLKFBOUT_MULT_F(CLKFBOUT_MULT_F),
.CLKFBOUT_PHASE(CLKFBOUT_PHASE),
.CLKIN1_PERIOD(CLKIN1_PERIOD),
.CLKIN2_PERIOD(0.000),
.CLKOUT0_DIVIDE_F(CLKOUT0_DIVIDE_F),
.CLKOUT1_DIVIDE(CLKOUT1_DIVIDE),
.CLKOUT2_DIVIDE(CLKOUT2_DIVIDE),
.CLKOUT3_DIVIDE(CLKOUT3_DIVIDE),
.CLKOUT4_DIVIDE(CLKOUT4_DIVIDE),
.CLKOUT5_DIVIDE(CLKOUT5_DIVIDE),
.CLKOUT6_DIVIDE(CLKOUT6_DIVIDE),
.CLKOUT0_DUTY_CYCLE(CLKOUT0_DUTY_CYCLE),
.CLKOUT1_DUTY_CYCLE(CLKOUT1_DUTY_CYCLE),
.CLKOUT2_DUTY_CYCLE(CLKOUT2_DUTY_CYCLE),
.CLKOUT3_DUTY_CYCLE(CLKOUT3_DUTY_CYCLE),
.CLKOUT4_DUTY_CYCLE(CLKOUT4_DUTY_CYCLE),
.CLKOUT5_DUTY_CYCLE(CLKOUT5_DUTY_CYCLE),
.CLKOUT6_DUTY_CYCLE(CLKOUT6_DUTY_CYCLE),
.CLKOUT0_PHASE(CLKOUT0_PHASE),
.CLKOUT1_PHASE(CLKOUT1_PHASE),
.CLKOUT2_PHASE(CLKOUT2_PHASE),
.CLKOUT3_PHASE(CLKOUT3_PHASE),
.CLKOUT4_PHASE(CLKOUT4_PHASE),
.CLKOUT5_PHASE(CLKOUT5_PHASE),
.CLKOUT6_PHASE(CLKOUT6_PHASE),
.CLKOUT4_CASCADE(CLKOUT4_CASCADE),
.DIVCLK_DIVIDE(DIVCLK_DIVIDE),
.REF_JITTER1(REF_JITTER1),
.REF_JITTER2(0.010),
.STARTUP_WAIT(STARTUP_WAIT),
.COMPENSATION("ZHOLD"),
.MODULE_TYPE("MMCME2_BASE"),
.FPGA_TYPE(FPGA_TYPE),
.SPEED_GRADE(SPEED_GRADE))
mmcme2_base (
.CLKOUT0(CLKOUT0),
.CLKOUT0B(CLKOUT0B),
.CLKOUT1(CLKOUT1),
.CLKOUT1B(CLKOUT1B),
.CLKOUT2(CLKOUT2),
.CLKOUT2B(CLKOUT2B),
.CLKOUT3(CLKOUT3),
.CLKOUT3B(CLKOUT3B),
.CLKOUT4(CLKOUT4),
.CLKOUT5(CLKOUT5),
.CLKOUT6(CLKOUT6),
.CLKFBOUT(CLKFBOUT),
.CLKFBOUTB(CLKFBOUTB),
.LOCKED(LOCKED),
.CLKIN1(CLKIN1),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.PWRDWN(PWRDWN),
.RST(RST),
.CLKFBIN(CLKFBIN),
.DADDR(7'h00),
.DCLK(1'b0),
.DEN(1'b0),
.DWE(1'b0),
.DI(16'h0),
.DO(DO),
.DRDY(DRDY));
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using lli = long long int; using str = string; const ll MOD = 1e9 + 7; void solve() { ll a, b, c; cin >> a >> b >> c; cout << a + b + c - 1 << n ; return; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout << setprecision(15) << fixed; ll t = 1; cin >> t; while (t--) { solve(); } return 0; } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_img_5_cols_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_img_5_cols_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_img_5_cols_V_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_img_5_cols_V_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
`default_nettype none
`timescale 1ns / 1ps
`include "../src/message_formatter.v"
// ============================================================================
module tb;
// ============================================================================
reg CLK;
initial CLK <= 1'b0;
always #0.5 CLK <= !CLK;
reg [3:0] rst_sr;
initial rst_sr <= 4'hF;
always @(posedge CLK) rst_sr <= rst_sr >> 1;
wire RST;
assign RST = rst_sr[0];
// ============================================================================
initial begin
$dumpfile("waveforms.vcd");
$dumpvars;
end
integer cycle_cnt;
initial cycle_cnt <= 0;
always @(posedge CLK)
if (!RST) cycle_cnt <= cycle_cnt + 1;
always @(posedge CLK)
if (!RST && cycle_cnt >= 150)
$finish;
// ============================================================================
wire i_stb = (cycle_cnt == 10);
wire [32*2-1:0] i_dat = 64'h01234567_ABCD4321;
wire o_stb;
wire [7:0] o_dat;
message_formatter #
(
.WIDTH (32),
.COUNT (2),
.TX_INTERVAL (4)
)
dut
(
.CLK (CLK),
.RST (RST),
.I_STB (i_stb),
.I_DAT (i_dat),
.O_STB (o_stb),
.O_DAT (o_dat)
);
always @(posedge CLK)
if (o_stb)
$display("%c", o_dat);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, ans = 1; cin >> n; vector<vector<int>> graph(n + 1); vector<bool> visit(n + 1); vector<int> color(n + 1); for (int i = 1; i < n; i++) { int a, b; cin >> a >> b; graph[a].push_back(b); graph[b].push_back(a); } queue<pair<int, int>> q; color[1] = 1; visit[1] = 1; int curC = 2; for (auto i : graph[1]) { visit[i] = 1; color[i] = curC; ans = max(ans, color[i]); curC++; q.push({1, i}); } while (!q.empty()) { int kakek = q.front().first, bapak = q.front().second; q.pop(); curC = 1; for (auto i : graph[bapak]) { if (!visit[i]) { visit[i] = 1; while (curC == color[bapak] || curC == color[kakek]) curC++; color[i] = curC; ans = max(ans, color[i]); curC++; q.push({bapak, i}); } } } cout << ans << n ; for (int i = 1; i <= n; i++) cout << color[i] << ; cout << n ; } |
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_unchange (clock, reset, enable, start_event, test_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 1;
parameter num_cks = 1;
parameter action_on_new_start = `OVL_ACTION_ON_NEW_START_DEFAULT;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input start_event;
input [width-1:0] test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_UNCHANGE";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_SYNTHESIS
`else
// Sanity Checks
initial begin
if (~((action_on_new_start == `OVL_IGNORE_NEW_START) ||
(action_on_new_start == `OVL_RESET_ON_NEW_START) ||
(action_on_new_start == `OVL_ERROR_ON_NEW_START)))
begin
ovl_error_t(`OVL_FIRE_2STATE,"Illegal value set for parameter action_on_new_start");
end
//
if (num_cks <= 0) begin
ovl_error_t(`OVL_FIRE_2STATE,"Illegal value for parameter num_cks which must be set to value greater than 0");
end
end
`endif
`ifdef OVL_VERILOG
`include "./vlog95/assert_unchange_logic.v"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_SVA
`include "./sva05/assert_unchange_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_unchange_psl_logic.v"
`else
`endmodule // ovl_unchange
`endif
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; int nLund0 = 0; int nRund0 = 0; int n00 = 0; int nL = 0; int nR = 0; auto zaehle = [&](char c1, char c2) -> void { if ((c1 == > && c2 == - ) || (c2 == > && c1 == - )) nRund0++; if ((c1 == < && c2 == - ) || (c2 == < && c1 == - )) nLund0++; if (c1 == > && c2 == > ) nR++; if (c1 == < && c2 == < ) nL++; if (c1 == - && c2 == - ) n00++; }; cin >> n; char c1 = 0, c2 = 0; char c0; for (int i = 0; i < n; ++i) { if (i > 0) c1 = c2; cin >> c2; if (i == 0) { c0 = c2; continue; } zaehle(c1, c2); } zaehle(c2, c0); cout << nRund0 + nLund0 + n00 + nL * ((nLund0 + nL + n00) == n ? 1 : 0) + nR * ((nRund0 + nR + n00) == n ? 1 : 0) << endl; } } |
// IS61LV25616 Asynchronous SRAM, 256K x 16 = 4M; speed: 10ns.
// Note; 1) Please include "+define+ OEb" in running script if you want to check
// timing in the case of OE_ being set.
// 2) Please specify access time by defining tAC_10 or tAC_12.
`define OEb
`define tAC_10 //tAC_10 or tAC_12 defines different parameters
`timescale 1ns/1ns
module IS61LV25616 (A, IO, CE_, OE_, WE_, LB_, UB_);
parameter dqbits = 16;
parameter memdepth = 262143;
parameter addbits = 18;
parameter Toha = 2;
parameter Tsa = 2;
`ifdef tAC_10 //if "`define tAC_10 " at beginning,sentences below are compiled
parameter Taa = 10,
Thzce = 3,
Thzwe = 5;
`endif
`ifdef tAC_12 //if "`define tAC_12 " at beginning,sentences below are compiled
parameter Taa = 12,
Thzce = 5,
Thzwe = 6;
`endif
input CE_, OE_, WE_, LB_, UB_;
input [(addbits - 1) : 0] A;
inout [(dqbits - 1) : 0] IO;
wire [(dqbits - 1) : 0] dout;
reg [(dqbits/2 - 1) : 0] bank0 [0 : memdepth];
reg [(dqbits/2 - 1) : 0] bank1 [0 : memdepth];
//array to simulate SRAM
// wire [(dqbits - 1) : 0] memprobe = {bank1[A], bank0[A]};
wire r_en = WE_ & (~CE_) & (~OE_); //WE=1,CE=OE=0 Read
wire w_en = (~WE_) & (~CE_) & ((~LB_) | (~UB_)); //WE=CE=0,LB or UB="0",OE=x Write
assign #(r_en ? Taa : Thzce) IO = r_en ? dout : 16'bz;
initial
$timeformat (-9, 0.1, " ns", 10); //show current simulation time
assign dout [(dqbits/2 - 1) : 0] = LB_ ? 8'bz : bank0[A];
assign dout [(dqbits - 1) : (dqbits/2)] = UB_ ? 8'bz : bank1[A];
always @(A or w_en)
begin
#Tsa //address setup time
if (w_en)
#Thzwe
begin
bank0[A] = LB_ ? bank0[A] : IO [(dqbits/2 - 1) : 0];
bank1[A] = UB_ ? bank1[A] : IO [(dqbits - 1) : (dqbits/2)];
end
end
// Timing Check
`ifdef tAC_10
specify //sepcify delay
specparam
tSA = 0,
tAW = 8,
tSCE = 8,
tSD = 6,
tPWE2 = 10,
tPWE1 = 8,
tPBW = 8;
`else
`ifdef tAC_12
specify
specparam
tSA = 0,
tAW = 8,
tSCE = 8,
tSD = 6,
tPWE2 = 12,
tPWE1 = 8,
tPBW = 8;
`endif
`endif
$setup (A, negedge CE_, tSA);
$setup (A, posedge CE_, tAW);
$setup (IO, posedge CE_, tSD);
$setup (A, negedge WE_, tSA);
$setup (IO, posedge WE_, tSD);
$setup (A, negedge LB_, tSA);
$setup (A, negedge UB_, tSA);
$width (negedge CE_, tSCE);
$width (negedge LB_, tPBW);
$width (negedge UB_, tPBW);
`ifdef OEb
$width (negedge WE_, tPWE1);
`else
$width (negedge WE_, tPWE2);
`endif
endspecify
endmodule
|
#include <bits/stdc++.h> template <typename T> inline void read(T &x) { bool b = 0; char c; while (!isdigit(c = getchar()) && c != - ) ; if (c == - ) c = getchar(), b = 1; x = c - 48; while (isdigit(c = getchar())) x = (x << 3) + (x << 1) + c - 48; if (b) x = -x; } template <typename T> inline void write(T x) { if (x > 9) write(x / 10); putchar(x % 10 + 48); } using namespace std; const int N = 1e5 + 11; int n, pos1, pos0, a[N], ans[N], ke[N], num[2]; int Max0(int pos) { int res = 0; for (int i = 1; i <= pos; i++) { num[a[i]]++; if (a[i]) res++; else res = max(res, num[0]); } num[0] = num[1] = 0; return res; } int Max1(int pos) { int res = 0; for (int i = 1; i <= pos; i++) { num[ans[i]]++; if (ans[i]) res++; else res = max(res, num[0]); } num[0] = num[1] = 0; return res; } int main() { char c; while (isdigit(c = getchar())) a[++n] = c - 48; for (int i = 1; i <= n; i++) ans[i] = a[i]; ke[n + 1] = n; ke[n] = n; for (int i = n - 1; i > 0; i--) { if (a[i] == a[i + 1]) ke[i] = ke[i + 1]; else ke[i] = i; } for (int i = 1; i <= n; i++) if (a[i]) { pos1 = i; break; } while (pos1 <= n) { pos0 = ke[pos1] + 1; int num0 = ke[pos0] - pos0 + 1; int num1 = ke[pos1] - pos1 + 1; if (num0 < num1) { num1 -= num0; for (int i = 1; i <= num1; i++) { ans[pos1 + i - 1] = 0; if (Max0(pos1 + i - 1) != Max1(pos1 + i - 1) || Max0(n) != Max1(n)) ans[pos1 + i - 1] = 1; } } pos1 = ke[pos0] + 1; } for (int i = 1; i <= n; i++) cout << ans[i]; } |
#include <bits/stdc++.h> using namespace std; const double fs = 6e-2, Pi = acos(-1.0); struct point { double x, y; } p[4]; double a, b, c, r, S, C, P, C1, A1, B1, R1, Ans; double s(point a, point b) { return sqrt((a.x - b.x) * (a.x - b.x) + (a.y - b.y) * (a.y - b.y)); } double gcd(double a, double b) { return (fabs(b) > fs) ? gcd(b, fmod(a, b)) : a; } int main() { for (int i = 1; i <= 3; ++i) scanf( %lf%lf , &p[i].x, &p[i].y); a = s(p[1], p[2]), b = s(p[2], p[3]), c = s(p[1], p[3]), P = (a + b + c) / 2; S = sqrt(P * (P - a) * (P - b) * (P - c)), r = a * b * c / (4 * S); C1 = acos(1 - c * c / (2 * r * r)), A1 = acos(1 - a * a / (2 * r * r)), B1 = 2 * Pi - A1 - C1; R1 = gcd(A1, gcd(B1, C1)); return printf( %.6lf , (Pi * r * r * sin(R1)) / R1), 0; } |
/*
*--------------------------------------------------------------
* This module converts a counter value N into a reset value
* for an 8-bit LFSR. The count is initialized by "reset" high
* or "start" transition high. When the count is valid, it is
* latched into "dp" and the signal "done" is raised to indicate
* a valid new value of "dp".
*--------------------------------------------------------------
*/
module map9v3(clock, reset, start, N, dp, done, counter, sr);
input clock;
input start; // run at rising edge of start
input reset; // high is reset case ( run after reset)
input [8:0] N; // the number to divide by
output [8:0] dp; // these outputs drive an LFSR counter
output done;
output [7:0] counter;
output [7:0] sr;
reg [8:0] dp;
reg [7:0] sr;
reg [7:0] counter;
reg startbuf;
reg done;
reg [2:0] state;
parameter INIT = 3'b000;
parameter RUN = 3'b001;
parameter ALMOSTDONE = 3'b010;
parameter DONE = 3'b011;
parameter WAIT = 3'b100;
always @(posedge clock or posedge reset) begin
if (reset == 1) begin
dp <= 9'b0;
sr <= 8'b0;
counter <= 8'b0;
startbuf <= 0;
done <= 0;
state <= INIT;
end else begin
if (state == INIT) begin
counter <= 255 - N[8:1] + 3;
sr <= 8'b0;
done <= 0;
state <= RUN;
end else if (state == RUN) begin
sr[7] <= sr[6];
sr[6] <= sr[5];
sr[5] <= sr[4];
sr[4] <= sr[3];
sr[3] <= sr[2];
sr[2] <= sr[1];
sr[1] <= sr[0];
sr[0] <= ~(sr[7] ^ sr[5] ^ sr[4] ^ sr[3]);
counter <= counter - 1;
if (counter == 0) begin
state <= ALMOSTDONE;
end
end else if (state == ALMOSTDONE) begin
dp[0] <= N[0];
dp[8:1] <= sr[7:0];
state <= DONE;
end else if (state == DONE) begin
done <= 1;
state <= WAIT;
end else if (state == WAIT) begin
if (start == 1 && startbuf == 0) begin
state <= INIT;
end
end
startbuf <= start;
end
end
endmodule
|
//////////////////////////////////////////////////////////////////
// //
// Wishbone master interface for the Amber core //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// Turns memory access requests from the execute stage and //
// cache into wishbone bus cycles. For 4-word read requests //
// from the cache and swap accesses ( read followed by write //
// to the same address) from the execute stage, //
// a block transfer is done. All other requests result in //
// single word transfers. //
// //
// Write accesses can be done in a single clock cycle on //
// the wishbone bus, is the destination allows it. The //
// next transfer will begin immediately on the //
// next cycle on the bus. This looks like a block transfer //
// and does hold ownership of the wishbone bus, preventing //
// the other master ( the ethernet MAC) from gaining //
// ownership between those two cycles. But otherwise it would //
// be necessary to insert a wait cycle after every write, //
// slowing down the performance of the core by around 5 to //
// 10%. //
// //
// Author(s): //
// - Conor Santifort, //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
module a23_wishbone
(
input i_clk,
// Core Accesses to Wishbone bus
input i_select,
input [31:0] i_write_data,
input i_write_enable,
input [3:0] i_byte_enable, // valid for writes only
input i_data_access,
input i_exclusive, // high for read part of swap access
input [31:0] i_address,
output o_stall,
// Cache Accesses to Wishbone bus
input i_cache_req,
// Wishbone Bus
output reg [31:0] o_wb_adr = 'd0,
output reg [3:0] o_wb_sel = 'd0,
output reg o_wb_we = 'd0,
input [31:0] i_wb_dat,
output reg [31:0] o_wb_dat = 'd0,
output reg o_wb_cyc = 'd0,
output reg o_wb_stb = 'd0,
input i_wb_ack,
input i_wb_err
);
localparam [3:0] WB_IDLE = 3'd0,
WB_BURST1 = 3'd1,
WB_BURST2 = 3'd2,
WB_BURST3 = 3'd3,
WB_WAIT_ACK = 3'd4;
reg [2:0] wishbone_st = WB_IDLE;
wire core_read_request;
wire core_write_request;
wire cache_read_request;
wire cache_write_request;
wire start_access;
reg servicing_cache = 'd0;
wire [3:0] byte_enable;
reg exclusive_access = 'd0;
wire read_ack;
wire wait_write_ack;
wire wb_wait;
// Write buffer
reg [31:0] wbuf_addr_r = 'd0;
reg [3:0] wbuf_sel_r = 'd0;
reg wbuf_busy_r = 'd0;
assign read_ack = !o_wb_we && i_wb_ack;
assign o_stall = ( core_read_request && !read_ack ) ||
( core_read_request && servicing_cache ) ||
( core_write_request && servicing_cache ) ||
( core_write_request && wishbone_st == WB_WAIT_ACK) ||
( cache_write_request && wishbone_st == WB_WAIT_ACK) ||
wbuf_busy_r;
// Don't stall on writes
// Wishbone is doing burst read so make core wait to execute the write
// ( core_write_request && !i_wb_ack ) ;
assign core_read_request = i_select && !i_write_enable;
assign core_write_request = i_select && i_write_enable;
assign cache_read_request = i_cache_req && !i_write_enable;
assign cache_write_request = i_cache_req && i_write_enable;
assign wb_wait = o_wb_stb && !i_wb_ack;
assign start_access = (core_read_request || core_write_request || i_cache_req) && !wb_wait ;
// For writes the byte enable is always 4'hf
assign byte_enable = wbuf_busy_r ? wbuf_sel_r :
( core_write_request || cache_write_request ) ? i_byte_enable :
4'hf ;
// ======================================
// Write buffer
// ======================================
always @( posedge i_clk )
if ( wb_wait && !wbuf_busy_r && (core_write_request || cache_write_request) )
begin
wbuf_addr_r <= i_address;
wbuf_sel_r <= i_byte_enable;
wbuf_busy_r <= 1'd1;
end
else if (!o_wb_stb)
wbuf_busy_r <= 1'd0;
// ======================================
// Register Accesses
// ======================================
always @( posedge i_clk )
if ( start_access )
o_wb_dat <= i_write_data;
assign wait_write_ack = o_wb_stb && o_wb_we && !i_wb_ack;
always @( posedge i_clk )
case ( wishbone_st )
WB_IDLE :
begin
if ( start_access )
begin
o_wb_stb <= 1'd1;
o_wb_cyc <= 1'd1;
o_wb_sel <= byte_enable;
end
else if ( !wait_write_ack )
begin
o_wb_stb <= 1'd0;
// Hold cyc high after an exclusive access
// to hold ownership of the wishbone bus
o_wb_cyc <= exclusive_access;
end
// cache has priority over the core
servicing_cache <= cache_read_request && !wait_write_ack;
if ( wait_write_ack )
begin
// still waiting for last (write) access to complete
wishbone_st <= WB_WAIT_ACK;
end
// do a burst of 4 read to fill a cache line
else if ( cache_read_request )
begin
wishbone_st <= WB_BURST1;
exclusive_access <= 1'd0;
end
else if ( core_read_request )
begin
wishbone_st <= WB_WAIT_ACK;
exclusive_access <= i_exclusive;
end
// The core does not currently issue exclusive write requests
// but there's no reason why this might not be added some
// time in the future so allow for it here
else if ( core_write_request )
exclusive_access <= i_exclusive;
if ( start_access )
begin
if (wbuf_busy_r)
begin
o_wb_we <= 1'd1;
o_wb_adr[31:2] <= wbuf_addr_r[31:2];
end
else
begin
o_wb_we <= core_write_request || cache_write_request;
// only update these on new wb access to make debug easier
o_wb_adr[31:2] <= i_address[31:2];
end
o_wb_adr[1:0] <= byte_enable == 4'b0001 ? 2'd0 :
byte_enable == 4'b0010 ? 2'd1 :
byte_enable == 4'b0100 ? 2'd2 :
byte_enable == 4'b1000 ? 2'd3 :
byte_enable == 4'b0011 ? 2'd0 :
byte_enable == 4'b1100 ? 2'd2 :
2'd0 ;
end
end
// Read burst, wait for first ack
WB_BURST1:
if ( i_wb_ack )
begin
// burst of 4 that wraps
o_wb_adr[3:2] <= o_wb_adr[3:2] + 1'd1;
wishbone_st <= WB_BURST2;
end
// Read burst, wait for second ack
WB_BURST2:
if ( i_wb_ack )
begin
// burst of 4 that wraps
o_wb_adr[3:2] <= o_wb_adr[3:2] + 1'd1;
wishbone_st <= WB_BURST3;
end
// Read burst, wait for third ack
WB_BURST3:
if ( i_wb_ack )
begin
// burst of 4 that wraps
o_wb_adr[3:2] <= o_wb_adr[3:2] + 1'd1;
wishbone_st <= WB_WAIT_ACK;
end
// Wait for the wishbone ack to be asserted
WB_WAIT_ACK:
if ( i_wb_ack )
begin
wishbone_st <= WB_IDLE;
o_wb_stb <= 1'd0;
o_wb_cyc <= exclusive_access;
o_wb_we <= 1'd0;
servicing_cache <= 1'd0;
end
endcase
// ========================================================
// Debug Wishbone bus - not synthesizable
// ========================================================
//synopsys translate_off
wire [(14*8)-1:0] xAS_STATE;
assign xAS_STATE = wishbone_st == WB_IDLE ? "WB_IDLE" :
wishbone_st == WB_BURST1 ? "WB_BURST1" :
wishbone_st == WB_BURST2 ? "WB_BURST2" :
wishbone_st == WB_BURST3 ? "WB_BURST3" :
wishbone_st == WB_WAIT_ACK ? "WB_WAIT_ACK" :
"UNKNOWN" ;
//synopsys translate_on
endmodule
|
`timescale 1ns / 1ps
/*
module OpDecoder(clk, );
// we: Write Enable
input clk, we;
input [15:0]addr;
input [31:0]wdata;
output [31:0]data;
reg [3:0] state;
assign data = rom[addr];
always @ (posedge clk)
begin
if(we == 1) begin
rom[addr] = wdata;
end
end
initial
begin
$readmemh("rom.hex", rom);
end
endmodule
*/
`timescale 1ns / 1ps
// timescale [単位時間] / [丸め精度]
/*
module testbench();
reg clk;
// regは値を保持してくれる。
// wireは値を保持してくれない。
reg [15:0] counter;
reg [31:0] wdata;
reg we;
reg PCinc;
wire [31:0] data;
memory mem(clk, counter, data, wdata, we);
initial
begin
// 初期化ブロック。
// 出力する波形ファイルをここで指定する。
$dumpfile("memory.vcd");
$dumpvars(0, testbench);
PCinc = 0;
#1;
counter = 0;
#3;
PCinc = 1;
end
always // 常に実行される。
begin
// クロックを生成する。
// #1; は、1クロック待機する。
clk <= 1; #1;
clk <= 0; #1;
end
always @ (posedge clk)
begin
if(PCinc == 1) begin
counter = counter + 1;
end
if(counter === 1000) begin
$display ("Simulation end");
$finish;
end
end
endmodule
*/
|
#include <bits/stdc++.h> using namespace std; struct node { int x, h, id; } a[100005]; int n, i, j, f[100005], ans[100005]; bool cmp(node x, node y) { if (x.x != y.x) return x.x < y.x; else return x.h < y.h; } int main() { scanf( %d , &n); for (i = 1; i <= n; i++) { scanf( %d%d , &a[i].x, &a[i].h); a[i].id = i; } sort(a + 1, a + n + 1, cmp); for (i = n; i >= 1; i--) { f[i] = 1; for (j = i + 1; j <= n; j += f[j]) { if (a[i].x + a[i].h - 1 >= a[j].x) f[i] += f[j]; else break; } ans[a[i].id] = f[i]; } for (i = 1; i <= n; i++) printf( %d , ans[i]); printf( n ); return 0; } |
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2020 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file cx4_pgmrom.v when simulating
// the core, cx4_pgmrom. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module cx4_pgmrom(
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb
);
input clka;
input [0 : 0] wea;
input [9 : 0] addra;
input [7 : 0] dina;
input clkb;
input [8 : 0] addrb;
output [15 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V6_2 #(
.C_ADDRA_WIDTH(10),
.C_ADDRB_WIDTH(9),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(1024),
.C_READ_DEPTH_B(512),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(16),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(1024),
.C_WRITE_DEPTH_B(512),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(16),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.DOUTA(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
`timescale 1 ns / 1 ps
module phase_unwrapper #
(
parameter integer DIN_WIDTH = 16,
parameter integer DOUT_WIDTH = 32
)
(
input wire clk,
input wire acc_on,
input wire rst,
input wire signed [DIN_WIDTH-1:0] phase_in,
output wire signed [DIN_WIDTH+1-1:0] freq_out,
output reg signed [DOUT_WIDTH-1:0] phase_out
);
// Value of Pi in scaled radians representation
localparam PI = 2**(DIN_WIDTH-3);
localparam TWOPI = 2**(DIN_WIDTH-2);
initial phase_out = 0;
initial unwrapped_diff = 0;
initial phase_in0 = 0;
initial diff = 0;
reg signed [DIN_WIDTH-1:0] phase_in0;
reg signed [DIN_WIDTH+1-1:0] diff;
reg signed [DIN_WIDTH+1-1:0] unwrapped_diff;
// Compute phase difference
always @(posedge clk) begin
phase_in0 <= phase_in;
diff <= phase_in - phase_in0;
end
// Unwrap phase difference
always @(posedge clk) begin
if (diff > PI) begin
unwrapped_diff <= diff - TWOPI;
end else if (diff < -PI) begin
unwrapped_diff <= diff + TWOPI;
end else begin
unwrapped_diff <= diff;
end
end
// Accumulate phase
always @(posedge clk) begin
if (rst) begin
phase_out <= 0;
end else begin
if (acc_on) begin
phase_out <= phase_out + unwrapped_diff;
end else begin
phase_out <= phase_out;
end
end
end
assign freq_out = unwrapped_diff;
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2009 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file spartan3e_pmem.v when simulating
// the core, spartan3e_pmem. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module spartan3e_pmem(
clka,
ena,
wea,
addra,
dina,
douta);
input clka;
input ena;
input [0 : 0] wea;
input [11 : 0] addra;
input [7 : 0] dina;
output [7 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V3_3 #(
.C_ADDRA_WIDTH(12),
.C_ADDRB_WIDTH(12),
.C_ALGORITHM(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan3"),
.C_HAS_ENA(1),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(0),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(4096),
.C_READ_DEPTH_B(4096),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(4096),
.C_WRITE_DEPTH_B(4096),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan3e"))
inst (
.CLKA(clka),
.ENA(ena),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.RSTA(),
.REGCEA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of spartan3e_pmem is "black_box"
endmodule
|
#include <bits/stdc++.h> using namespace std; void init_code() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); } set<pair<int, int>> es; map<int, list<int>> m; void add(int a, int b) { m[a].push_back(b); m[b].push_back(a); } int v[1001]; void dfs(int node) { v[node] = 1; for (int i : m[node]) { if (v[i] == 0) { es.erase({node, i}); es.erase({i, node}); dfs(i); } } } int main() { init_code(); int n; cin >> n; for (int i = 0; i < n - 1; i++) { int a, b; cin >> a >> b; add(a, b); es.insert({a, b}); } vector<int> ans; for (int i = 1; i <= n; i++) { if (v[i] == 0) { ans.push_back(i); dfs(i); } } cout << es.size() << endl; vector<pair<int, int>> ans2, ans3; for (auto i : es) { ans2.push_back(i); } for (int i = 1; i < ans.size(); i++) { ans3.push_back({ans[i], ans[i - 1]}); } for (int i = 0; i < ans2.size(); i++) { cout << ans2[i].first << << ans2[i].second << << ans3[i].first << << ans3[i].second << endl; } } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:43:27 04/04/2016
// Design Name: Top
// Module Name: C:/Users/Ranolazine/Desktop/lab5_better_io/test_for_top.v
// Project Name: lab5
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_for_top;
// Inputs
reg CLOCK;
reg RESET;
reg [2:0] MODE;
reg FAST;
// Outputs
wire [7:0] LED;
// Instantiate the Unit Under Test (UUT)
Top uut (
.CLOCK(CLOCK),
.RESET(RESET),
.MODE(MODE),
.LED(LED),
.FAST(FAST)
);
always #10 CLOCK=~CLOCK;
initial begin
// Initialize Inputs
CLOCK = 0;
RESET = 1;
MODE = 0;
FAST = 0;
// Wait 100 ns for global reset to finish
#100;
RESET = 0;
// Add stimulus here
end
endmodule
|
#include <bits/stdc++.h> using namespace std; bool G[100005]; bool use[100005]; int top[100005]; int Top[100005]; char R[100005]; int num[100005]; int main() { int m, n, Len = 0, useLen = 0; char str[10]; memset(G, true, sizeof(G)); memset(use, false, sizeof(use)); scanf( %d%d , &n, &m); int number = 0, last = 0; for (int i = 0; i < m; i++) { scanf( %s %d , str, &num[i]); R[i] = str[0]; } for (int i = 0; i < m; i++) { int a; str[0] = R[i]; a = num[i]; if (str[0] == + ) { if (number != 0 || (Len != 0 && use[a] == false)) G[a] = false; last = a; number++; } if (str[0] == - ) { if (use[a] == false) { for (int i = Len - 1; i >= useLen; i--) { G[Top[i]] = false; } useLen = Len; if (number != 0 || (i != m - 1 && a != num[i + 1])) G[a] = false; } else { if (number > 1 || (number == 1 && i != m - 1 && num[i + 1] != a)) G[a] = false; number--; } } if (use[a] == false) { Top[Len++] = a; use[a] = true; } } int sum = 0; for (int i = 1; i <= n; i++) if (G[i]) { top[sum++] = i; } printf( %d n , sum); if (sum > 0) { for (int i = 0; i < sum - 1; i++) printf( %d , top[i]); printf( %d n , top[sum - 1]); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A31O_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__A31O_PP_BLACKBOX_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a31o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A31O_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O41AI_LP_V
`define SKY130_FD_SC_LP__O41AI_LP_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog wrapper for o41ai with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o41ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o41ai_lp (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o41ai_lp (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O41AI_LP_V
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5 + 10; int n, sz; vector<int> vec[MAXN]; int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n; cout << n - 1 << n ; for (int i = 0; i < n - 1; i++) { int a, b; cin >> a >> b; a--, b--; vec[a].push_back(sz); vec[b].push_back(sz++); cout << 2 << << a + 1 << << b + 1 << n ; } for (int i = 0; i < n; i++) for (int j = 1; j < vec[i].size(); j++) cout << vec[i][j - 1] + 1 << << vec[i][j] + 1 << n ; return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; const double PI = acos(-1.0); const long long MOD = 1000000007LL; template <class T> inline bool chmax(T &a, T b) { if (a < b) { a = b; return true; } return false; } template <class T> inline bool chmin(T &a, T b) { if (a > b) { a = b; return true; } return false; } int dp[500][500]; void solve() { string S, T; cin >> S >> T; int N = S.size(); int M = T.size(); for (int i = 0; i < (int)(M); ++i) { for (int j = 0; j < (int)(N + 1); ++j) for (int k = 0; k < (int)(M + 1); ++k) dp[j][k] = -1; for (int j = 0; j < (int)(N + 1); ++j) dp[j][0] = 0; for (int j = 0; j < (int)(N); ++j) { for (int k = 0; k < (int)(i + 1); ++k) { chmax(dp[j + 1][k], dp[j][k]); if (k < i && S[j] == T[k]) { chmax(dp[j + 1][k + 1], dp[j][k]); } if (dp[j][k] >= 0 && dp[j][k] < M - i && S[j] == T[i + dp[j][k]]) { chmax(dp[j + 1][k], dp[j][k] + 1); } } } if (dp[N][i] == M - i) { cout << YES << n ; return; } } cout << NO << n ; } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); int Q; cin >> Q; while (Q--) { solve(); } } |
#include <bits/stdc++.h> using namespace std; void solve() { long long int a, b, c, d, m, n, p, q, r, x, y, z, aa, bb, cc, dd; double pp, qq, rr, xx, yy, zz; char ch1, ch2, ch3, ch4, ch5; long long int i, j, k, l; long long int cnt = 0, cnt1 = 0, cnt2 = 0, cnt3 = 0, sum = 0, sum2 = 0, mx = LLONG_MIN, mn = LLONG_MAX; long long int flag = 0, flag2 = 0; vector<long long int> vec1, vec2, vec3; string s1, s2, s3; cin >> n; for (long long int i = (long long int)(0); i < (long long int)(n); ++i) { cin >> x; vec1.push_back(x); } for (long long int i = (long long int)(0); i < (long long int)(n); ++i) { cin >> x; vec2.push_back(x); } if (n == 1) { cout << 0 n ; return; } for (long long int i = (long long int)(n - 1); i >= (long long int)(0); --i) { sum += vec1[i]; vec1[i] = sum; } sum = 0; for (long long int i = (long long int)(0); i < (long long int)(n); ++i) { sum += vec2[i]; vec2[i] = sum; } for (long long int i = (long long int)(0); i < (long long int)(n - 2); ++i) { mx = max(vec2[i], vec1[i + 2]); mn = min(mn, mx); } mn = min(mn, vec1[1]); mn = min(mn, vec2[n - 2]); cout << mn << endl; } int main() { ios::sync_with_stdio(false); long long int t = 1; cin >> t; while (t--) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; int d[1008][1008]; int main() { int n, x1, x2, y1, y2; int di[] = {0, 0, 1, -1}; int dj[] = {1, -1, 0, 0}; cin >> n >> x1 >> y1 >> x2 >> y2; int i, j, k; d[n - y1][x1] = 1; queue<int> qi, qj, dist; qi.push(n - y1); qj.push(x1); dist.push(1); int ii, jj, D; while (!qi.empty()) { ii = qi.front(); jj = qj.front(); qi.pop(); qj.pop(); D = dist.front(); dist.pop(); int t1, t2; for (k = 0; k < 4; k++) { t1 = ii + di[k]; t2 = jj + dj[k]; if ((t1 == 0 || t1 == n || t2 == 0 || t2 == n) && d[t1][t2] == 0 && (t1 >= 0 && t1 <= n && t2 >= 0 && t2 <= n)) { d[t1][t2] = D + 1; qi.push(t1); qj.push(t2); dist.push(D + 1); } } } cout << d[n - y2][x2] - 1 << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> bool umin(T &x, T y) { return y < x ? x = y, 1 : 0; } template <class T> bool umax(T &x, T y) { return y > x ? x = y, 1 : 0; } const int N = 505; int n, m, g[N][N][2]; bitset<N> dp[100][2][N], ok, tmp; signed main() { cin >> n >> m; for (int i = 1, u, v, w; i <= m; ++i) { cin >> u >> v >> w; dp[0][w][u][v] = 1; } for (int i = 1; i <= 60; ++i) { for (int u = 1; u <= n; ++u) { for (int k = 1; k <= n; ++k) { if (dp[i - 1][0][u][k]) dp[i][0][u] |= dp[i - 1][1][k]; if (dp[i - 1][1][u][k]) dp[i][1][u] |= dp[i - 1][0][k]; } } } for (int i = 1; i <= n; ++i) if (dp[60][0][i].count()) { puts( -1 ); return 0; } long long ans = 0; ok[1] = 1; int cur = 0; for (int i = 59; i >= 0; --i) { tmp = 0; for (int u = 1; u <= n; ++u) if (ok[u]) tmp |= dp[i][cur][u]; if (tmp.count()) { for (int u = 1; u <= n; ++u) ok[u] = tmp[u]; ans |= (1ll << i); if (ans > 1e18) { ans = -1; break; } cur ^= 1; } } cout << ans << n ; return 0; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:08:01 02/19/2016
// Design Name: tp_final
// Module Name: /home/poche002/Desktop/ArqComp/Trabajo_final/arquitectura_tpf/tp_final_tb.v
// Project Name: arquitectura_tpf
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: tp_final
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tp_final_tb;
// Inputs
reg clk;
reg reset;
reg rx;
// Outputs
wire tx;
//Para test
//wire [1:0] op;
//wire ena_pip_test;
//wire [31:0] pc_PC_out_test;
//wire [31:0] instruction_IF_test;
//wire [31:0] write_data_WB_out_test;
//wire stallF_HZ_out_test;
//wire [2:0] state_reg_test;
//wire rx_empty_test;
//wire rx_done_tick_test;
//wire [7:0] rx_data_out_test;
//wire [7:0] write_data_test;
//wire [3:0] byteN_test;
//wire [7:0] reg_0;
//wire [7:0] reg_1;
//wire [7:0] reg_2;
//wire [7:0] reg_3;
//wire tick_test;
integer ciclo;
//wire [7:0] fifo_data;
//wire fifo_full;
//wire [1:0] state_test;
wire [7:0] led;
// Instantiate the Unit Under Test (UUT)
tp_final uut (
.clk(clk),
.reset(reset),
.rx(rx),
.tx(tx),
.led(led)
//.op(op),
//.ena_pip_test(ena_pip_test),
//.pc_incrementado_PC_out_test(pc_PC_out_test),
//.instruction_IF_test(instruction_IF_test),
//.write_data_WB_out_test(write_data_WB_out_test)
//.stallF_HZ_out_test(stallF_HZ_out_test)
//.state_reg_test(state_reg_test)
//.rx_empty_test(rx_empty_test),
//.btn_read_reg_test(btn_read_reg_test),
//.write_data_test(write_data_test),
//.byteN_test(byteN_test)
//.reg_0(reg_0),
//.reg_1(reg_1),
//.reg_2(reg_2),
//.reg_3(reg_3),
//.rx_done_tick_test(rx_done_tick_test),
//.rx_data_out_test(rx_data_out_test),
//.tick_test(tick_test),
//.fifo_data(fifo_data),
//.fifo_full(fifo_full),
//.state_test(state_test)
);
initial begin
// Initialize Inputs
clk = 0;
rx = 1;
reset = 0;
ciclo= 0;
// Wait 100 ns for global reset to finish
#1 reset = 1;
#1 reset = 0;
//1 byte 0000_0010
#64 rx=0;
#64 rx=0;
#64 rx=1;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=1;
#8000
//0000_0010
#64 rx=0;
#64 rx=0;
#64 rx=1;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=1;
#8000
//0000_0010
#64 rx=0;
#64 rx=0;
#64 rx=1;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=1;
#8000
//0000_0010
#64 rx=0;
#64 rx=1;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=1;
//0000_0011
/*
#64 rx=0;
#64 rx=1;
#64 rx=1;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=0;
#64 rx=1;
*/
//#10000 reset = 1'b1;
//#2 reset = 1'b0;
// Add stimulus here
end
always
begin
#1
clk=~clk;
#1
clk=~clk;
ciclo = ciclo + 1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int pow(long long int x, long long int y, long long int m) { long long int res = 1; x = x % m; while (y > 0) { if (y & 1) res = ((res % m) * (x % m)) % m; y = y >> 1; x = ((x % m) * (x % m)) % m; } return res % m; } template <typename Arg1> void ZZ(const char* name, Arg1&& arg1) { std::cerr << name << = << arg1 << endl; } template <typename Arg1, typename... Args> void ZZ(const char* names, Arg1&& arg1, Args&&... args) { const char* comma = strchr(names + 1, , ); std::cerr.write(names, comma - names) << = << arg1; ZZ(comma, args...); } const long long int INF = 0xFFFFFFFFFFFFFFFL; long long int clz(unsigned long long N) { return N ? 64LL - __builtin_clzll(N) : -INF; } clock_t time_p = clock(); void abhigyan10() { time_p = clock() - time_p; cerr << Time Taken : << (float)(time_p) / CLOCKS_PER_SEC << n ; } long long int seed; mt19937 rng(seed = chrono::steady_clock::now().time_since_epoch().count()); inline long long int rnd(long long int l = 0, long long int r = INF) { return uniform_int_distribution<long long int>(l, r)(rng); } const long long int mod = 1000000007; long long int modinv(long long int x) { return pow(x, mod - 2, mod); } vector<long long int> a; int bs(long long int x, long long int n) { long long int l = 0, h = n - 1, m, ans = 0; while (l <= h) { m = (l + h) / 2; if (a[m] <= x) { l = m + 1; ans = max(ans, m); } else { h = m - 1; } } return ans; } int main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int s = 0, t, n, p, i; cin >> n >> p; a.resize(n); for (i = 0; i < n; i++) cin >> a[i]; sort(a.begin(), a.end()); for (i = 0; i < n; i++) s = max(s, a[i] - i); t = a[n - 1]; for (i = 0; i < n;) { int d = t + i; int u = bs(d, n) + 1 - i; if (u < p) i++; else t--; if (t < s) break; } cout << max(0LL, t - s + 1) << n ; for (i = s; i <= t; i++) cout << i << ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND2B_PP_SYMBOL_V
`define SKY130_FD_SC_HS__AND2B_PP_SYMBOL_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__and2b (
//# {{data|Data Signals}}
input A_N ,
input B ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND2B_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FAHCIN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__FAHCIN_FUNCTIONAL_PP_V
/**
* fahcin: Full adder, inverted carry in.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__fahcin (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire ci ;
wire xor0_out_SUM ;
wire pwrgood_pp0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT ;
wire pwrgood_pp1_out_COUT;
// Name Output Other arguments
not not0 (ci , CIN );
xor xor0 (xor0_out_SUM , A, B, ci );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND);
buf buf0 (SUM , pwrgood_pp0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, ci );
and and2 (b_ci , B, ci );
or or0 (or0_out_COUT , a_b, a_ci, b_ci );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_COUT, or0_out_COUT, VPWR, VGND);
buf buf1 (COUT , pwrgood_pp1_out_COUT );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__FAHCIN_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 7; map<long long, int> cnt; bool vis[N]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; long long a[n]; memset(vis, 0, sizeof(vis)); for (int i = 0; i < n; i++) { long long x; cin >> x; while (1) { auto it = cnt.find(x); if (it == cnt.end()) { cnt[x] = i; break; } else { vis[cnt[x]] = true; cnt.erase(it); x *= 2LL; } } a[i] = x; } vector<long long> vec; for (int i = 0; i < n; i++) { if (vis[i]) continue; vec.push_back(a[i]); } cout << vec.size() << endl; for (long long x : vec) cout << x << ; cout << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 55, mod = 1LL * 1000 * 1000 * 1000 + 7; int dp[N][N][2], ans[N][N][2], n, cnt50, cnt100, W, c[N][N], seen[N][N]; bool vis[N][N][2], vis2[N][N][2]; int C(int r, int n) { if (r == 0 || r == n) return 1; if (r > n) return 0; if (seen[r][n]) return c[r][n]; seen[r][n] = true; return c[r][n] = (C(r - 1, n - 1) + C(r, n - 1)) % mod; } int dfs(int x, int y, int tp) { if (vis2[x][y][tp]) return ans[x][y][tp]; vis2[x][y][tp] = true; if (tp) { for (int i = 0; i <= cnt50 - x; i++) for (int j = 0; j <= cnt100 - y; j++) if (i * 50 + j * 100 <= W && (i || j) && dp[x][y][tp] == dp[x + i][y + j][!tp] + 1) (ans[x][y][tp] += 1LL * dfs(x + i, y + j, !tp) * C(i, cnt50 - x) % mod * C(j, cnt100 - y) % mod) %= mod; } else { for (int i = 0; i <= x; i++) for (int j = 0; j <= y; j++) if ((i || j) && i * 50 + j * 100 <= W && dp[x][y][tp] == dp[x - i][y - j][!tp] + 1) (ans[x][y][tp] += 1LL * dfs(x - i, y - j, !tp) * C(i, x) % mod * C(j, y) % mod) %= mod; } return ans[x][y][tp]; } struct Node { int x = 0, y = 0, tp = 0; Node(int a = 0, int b = 0, int c = 0) { x = a, y = b, tp = c; } }; int main() { ios::sync_with_stdio(false), cin.tie(0), cout.tie(0); for (int i = 0; i < N; i++) for (int j = 0; j < N; j++) for (int k = 0; k < 2; k++) dp[i][j][k] = 1 << 29; cin >> n >> W; for (int i = 0, a; i < n; i++) { cin >> a; cnt50 += (a == 50); cnt100 += (a == 100); } dp[0][0][0] = dp[0][0][1] = 0; vis[0][0][0] = vis[0][0][1] = true; ans[0][0][0] = ans[0][0][1] = 1; queue<Node> q; q.push(Node(0, 0, 0)), q.push(Node(0, 0, 1)); while (q.size()) { Node tmp = q.front(); q.pop(); int x = tmp.x, y = tmp.y, tp = tmp.tp; if (tp) { for (int i = 0; i <= cnt50 - x; i++) for (int j = 0; j <= cnt100 - y; j++) if (i * 50 + j * 100 <= W && (i || j) && !vis[x + i][y + j][!tp]) { q.push(Node(x + i, y + j, !tp)); dp[x + i][y + j][!tp] = dp[x][y][tp] + 1; vis[x + i][y + j][!tp] = true; } } else { for (int i = 0; i <= x; i++) for (int j = 0; j <= y; j++) if ((i || j) && i * 50 + 100 * j <= W && !vis[x - i][y - j][!tp]) { q.push(Node(x - i, y - j, !tp)); dp[x - i][y - j][!tp] = dp[x][y][tp] + 1; vis[x - i][y - j][!tp] = true; } } } dfs(cnt50, cnt100, 0); if (dp[cnt50][cnt100][0] >= (1 << 29)) dp[cnt50][cnt100][0] = -1; cout << dp[cnt50][cnt100][0] << n << ans[cnt50][cnt100][0] << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int mx = 1e6 + 50; bool tot[10000050]; vector<int> prime; void seive() { for (int i = 2; i * i <= mx; i++) { if (!tot[i]) { for (int j = (2 * i); j <= mx; j += i) { tot[j] = true; } } } for (int i = 2; i <= mx; i++) { if (!tot[i]) { prime.push_back(i); } } } vector<int> g[mx]; map<int, bool> mp; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n, m; seive(); cin >> n >> m; long long int sum = 0; for (int i = 1; i < n - 1; i++) { sum += 2; } int p = upper_bound(prime.begin(), prime.end(), sum) - prime.begin(); int x = prime[p] - sum; cout << 2 << << prime[p] << endl; cout << 1 << << n << << 2 << endl; for (int i = 2; i <= n - 1; i++) { cout << 1 << << i << << ((i == 2) ? x : 2) << endl; } m -= n - 1; long long int tot = (int)1e6 + 10; int j = 2; mp[1] = true; int t = 3; int f = 0; for (int i = 2; i < n; i++) { for (int j = i + 1; j <= n; j++) { if (f == m) { return 0; } f++; cout << i << << j << << (++tot) << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 110; int main() { cin.tie(0); cout.tie(0); ios::sync_with_stdio(false); int al, ar, bl, br; cin >> al >> ar >> bl >> br; if ((al * 2 + 3 > br && br >= al - 1) || (ar * 2 + 3 > bl && bl >= ar - 1)) cout << YES << endl; else cout << NO << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T1, class T2> bool chmin(T1 &a, T2 b) { return b < a && (a = b, true); } template <class T1, class T2> bool chmax(T1 &a, T2 b) { return a < b && (a = b, true); } int main() { int n; cin >> n; static long long dp[100][100][100][4]; dp[1][1][1][0] = 1; dp[1][1][1][1] = 1; dp[1][1][1][2] = 1; dp[1][1][1][3] = 1; for (int i = (1); i < (2 * n - 2); i++) for (int j = 0; j < (n + 1); j++) for (int k = 0; k < (100); k++) for (int l = 0; l < (4); l++) { for (int x = 0; x < (4); x++) { if (l == x) { dp[i + 1][j + 1][max(k, j + 1)][x] += dp[i][j][k][l]; } else { dp[i + 1][1][max(k, 1)][x] += dp[i][j][k][l]; } } } long long ans = 0; for (int j = 0; j < (n + 1); j++) for (int i = 0; i < (4); i++) ans += dp[2 * n - 2][j][n][i]; cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m; int dir[405][405], dic[405][405]; int main() { memset(dir, 63, sizeof(dir)); memset(dic, 63, sizeof(dic)); scanf( %d %d , &n, &m); for (int i = 1, x, y; i <= m; i++) { scanf( %d %d , &x, &y); dir[x][y] = dir[y][x] = 1; } for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) if (dir[i][j] == 1061109567) dic[i][j] = 1; for (int k = 1; k <= n; k++) { for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) dir[i][j] = min(dir[i][k] + dir[k][j], dir[i][j]); } } for (int k = 1; k <= n; k++) { for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { int res = dic[i][k] + dic[k][j]; if (res == dir[i][j]) continue; dic[i][j] = min(dic[i][j], res); } } } int ans = max(dic[1][n], dir[1][n]); if (ans == 1061109567) ans = -1; printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 1e9; long long n, m, b, ans; long long a[1005]; int l, r, mid; long long dp[1005][1005]; struct Node { long long w, id; } f[1005]; bool cmp(Node a, Node b) { if (a.w != b.w) return a.w < b.w; return a.id > b.id; } int main() { cin >> n >> m; for (int i = 1; i <= n; ++i) cin >> a[i]; for (int i = 1; i <= n + 1; ++i) for (int j = 0; j <= n + 1; ++j) dp[i][j] = 1e18; dp[n + 1][0] = 0; for (int i = n; i >= 1; --i) { for (int j = 0; j <= n; ++j) dp[i][j] = min(dp[i][j], max(0LL, dp[i + 1][j] - a[i])); for (int j = 1; j <= n; ++j) dp[i][j] = min(dp[i][j], dp[i + 1][j - 1]); } for (int i = 0; i <= n; ++i) { f[i].w = dp[1][i]; f[i].id = i; } sort(f, f + n + 1, cmp); for (int i = 1; i <= m; ++i) { cin >> b; l = 0; r = n; ans = -1; while (l <= r) { mid = (l + r) / 2; if (f[mid].w <= b) { ans = f[mid].id; l = mid + 1; } else r = mid - 1; } cout << ans << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A32OI_SYMBOL_V
`define SKY130_FD_SC_HD__A32OI_SYMBOL_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a32oi (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
input B2,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A32OI_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; long long row1[n], row2[n]; for (int i = 0; i < n; i++) cin >> row1[i]; for (int i = 0; i < n; i++) cin >> row2[i]; long long first, second, pref = 0, pres = 0; for (int i = 0; i < n; i++) { first = max(pref, pres + row1[i]); second = max(pres, pref + row2[i]); pref = first; pres = second; } cout << max(pref, pres); return 0; } |
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: check_fifo.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 350 03/24/2010 SP 2 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module check_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull);
input aclr;
input [0:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [0:0] q;
output rdempty;
output [6:0] rdusedw;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire sub_wire1;
wire [0:0] sub_wire2;
wire [6:0] sub_wire3;
wire rdempty = sub_wire0;
wire wrfull = sub_wire1;
wire [0:0] q = sub_wire2[0:0];
wire [6:0] rdusedw = sub_wire3[6:0];
dcfifo dcfifo_component (
.wrclk (wrclk),
.rdreq (rdreq),
.aclr (aclr),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.rdempty (sub_wire0),
.wrfull (sub_wire1),
.q (sub_wire2),
.rdusedw (sub_wire3)
// synopsys translate_off
,
.rdfull (),
.wrempty (),
.wrusedw ()
// synopsys translate_on
);
defparam
dcfifo_component.intended_device_family = "Arria II GX",
dcfifo_component.lpm_hint = "RAM_BLOCK_TYPE=MLAB",
dcfifo_component.lpm_numwords = 128,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 1,
dcfifo_component.lpm_widthu = 7,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "128"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "1"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "1"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=MLAB"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: USED_PORT: data 0 0 1 0 INPUT NODEFVAL data[0..0]
// Retrieval info: USED_PORT: q 0 0 1 0 OUTPUT NODEFVAL q[0..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: rdusedw 0 0 7 0 OUTPUT NODEFVAL rdusedw[6..0]
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 1 0
// Retrieval info: CONNECT: q 0 0 1 0 @q 0 0 1 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 7 0 @rdusedw 0 0 7 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL check_fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL check_fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL check_fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL check_fifo.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL check_fifo_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL check_fifo_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL check_fifo_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL check_fifo_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
Subsets and Splits