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// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
// Date : Wed Apr 30 22:30:36 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode funcsim
// /home/keith/Documents/VHDL-lib/top/lab_7/part_3/ip/clk_adc/clk_adc_funcsim.v
// Design : clk_adc
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* core_generation_info = "clk_adc,clk_wiz_v5_1,{component_name=clk_adc,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=4.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
(* NotValidForBitStream *)
module clk_adc
(clk_in1_p,
clk_in1_n,
clk_250Mhz,
locked);
input clk_in1_p;
input clk_in1_n;
output clk_250Mhz;
output locked;
wire clk_250Mhz;
(* DIFF_TERM=0 *) (* IBUF_LOW_PWR *) wire clk_in1_n;
(* DIFF_TERM=0 *) (* IBUF_LOW_PWR *) wire clk_in1_p;
wire locked;
clk_adcclk_adc_clk_wiz U0
(.clk_250Mhz(clk_250Mhz),
.clk_in1_n(clk_in1_n),
.clk_in1_p(clk_in1_p),
.locked(locked));
endmodule
(* ORIG_REF_NAME = "clk_adc_clk_wiz" *)
module clk_adcclk_adc_clk_wiz
(clk_in1_p,
clk_in1_n,
clk_250Mhz,
locked);
input clk_in1_p;
input clk_in1_n;
output clk_250Mhz;
output locked;
wire clk_250Mhz;
wire clk_250Mhz_clk_adc;
wire clk_in1_clk_adc;
(* DIFF_TERM=0 *) (* IBUF_LOW_PWR *) wire clk_in1_n;
(* DIFF_TERM=0 *) (* IBUF_LOW_PWR *) wire clk_in1_p;
wire clkfbout_buf_clk_adc;
wire clkfbout_clk_adc;
wire locked;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
(* box_type = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_clk_adc),
.O(clkfbout_buf_clk_adc));
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
(* box_type = "PRIMITIVE" *)
IBUFDS #(
.DQS_BIAS("FALSE"),
.IOSTANDARD("DEFAULT"))
clkin1_ibufgds
(.I(clk_in1_p),
.IB(clk_in1_n),
.O(clk_in1_clk_adc));
(* box_type = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_250Mhz_clk_adc),
.O(clk_250Mhz));
(* box_type = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(4.000000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(4.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(4.000000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(236.250000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(1),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.000000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_buf_clk_adc),
.CLKFBOUT(clkfbout_clk_adc),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(clk_in1_clk_adc),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(clk_250Mhz_clk_adc),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(locked),
.PSCLK(1'b0),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
`timescale 1 ns / 1 ns
//////////////////////////////////////////////////////////////////////////////////
// Company: Rehkopf
// Engineer: Rehkopf
//
// Create Date: 01:13:46 05/09/2009
// Design Name:
// Module Name: address
// Project Name:
// Target Devices:
// Tool versions:
// Description: Address logic w/ SaveRAM masking
//
// Dependencies:
//
// Revision:
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module address(
input CLK,
input [7:0] featurebits, // peripheral enable/disable
input [2:0] MAPPER, // MCU detected mapper
input [23:0] SNES_ADDR, // requested address from SNES
input [7:0] SNES_PA, // peripheral address from SNES
input SNES_ROMSEL, // SNES ROM access
output [23:0] ROM_ADDR, // Address to request from SRAM0
output ROM_HIT, // enable SRAM0
output IS_SAVERAM, // address/CS mapped as SRAM?
output IS_ROM, // address mapped as ROM?
output IS_WRITABLE, // address somehow mapped as writable area?
input [23:0] SAVERAM_MASK,
input [23:0] ROM_MASK,
output msu_enable,
output r213f_enable,
output snescmd_enable,
output nmicmd_enable,
output return_vector_enable,
output branch1_enable,
output branch2_enable,
output obc1_enable
);
parameter [2:0]
FEAT_MSU1 = 3,
FEAT_213F = 4
;
wire [23:0] SRAM_SNES_ADDR;
/* currently supported mappers:
Index Mapper
000 HiROM
001 LoROM
010 ExHiROM (48-64Mbit)
*/
/* HiROM: SRAM @ Bank 0x30-0x3f, 0xb0-0xbf
Offset 6000-7fff */
assign IS_ROM = ((!SNES_ADDR[22] & SNES_ADDR[15])
|(SNES_ADDR[22]));
assign IS_SAVERAM = SAVERAM_MASK[0]
&(((MAPPER == 3'b000
|| MAPPER == 3'b010)
? (!SNES_ADDR[22]
& SNES_ADDR[21]
& &SNES_ADDR[14:13]
& !SNES_ADDR[15]
)
/* LoROM: SRAM @ Bank 0x70-0x7d, 0xf0-0xff
* Offset 0000-7fff for ROM >= 32 MBit, otherwise 0000-ffff */
:(MAPPER == 3'b001)
? (&SNES_ADDR[22:20]
& (~SNES_ROMSEL)
& (~SNES_ADDR[15] | ~ROM_MASK[21])
)
: 1'b0));
assign IS_WRITABLE = IS_SAVERAM;
assign SRAM_SNES_ADDR = ((MAPPER == 3'b000)
?(IS_SAVERAM
? 24'hE00000 + ({SNES_ADDR[20:16], SNES_ADDR[12:0]}
& SAVERAM_MASK)
: ({1'b0, SNES_ADDR[22:0]} & ROM_MASK))
:(MAPPER == 3'b001)
?(IS_SAVERAM
? 24'hE00000 + ({SNES_ADDR[20:16], SNES_ADDR[14:0]}
& SAVERAM_MASK)
: ({2'b00, SNES_ADDR[22:16], SNES_ADDR[14:0]}
& ROM_MASK))
:(MAPPER == 3'b010)
?(IS_SAVERAM
? 24'hE00000 + ({SNES_ADDR[20:16], SNES_ADDR[12:0]}
& SAVERAM_MASK)
: ({1'b0, !SNES_ADDR[23], SNES_ADDR[21:0]}
& ROM_MASK))
: 24'b0);
assign ROM_ADDR = SRAM_SNES_ADDR;
assign ROM_SEL = 1'b0;
assign ROM_HIT = IS_ROM | IS_WRITABLE;
assign msu_enable = featurebits[FEAT_MSU1] & (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfff8) == 16'h2000));
assign r213f_enable = featurebits[FEAT_213F] & (SNES_PA == 8'h3f);
assign obc1_enable = (~SNES_ADDR[22]) & (SNES_ADDR[15:11] == 5'b01111);
assign snescmd_enable = ({SNES_ADDR[22], SNES_ADDR[15:9]} == 8'b0_0010101);
assign nmicmd_enable = (SNES_ADDR == 24'h002BF2);
assign return_vector_enable = (SNES_ADDR == 24'h002A5A);
assign branch1_enable = (SNES_ADDR == 24'h002A13);
assign branch2_enable = (SNES_ADDR == 24'h002A4D);
endmodule
|
module RetimeShiftRegister
#(
parameter WIDTH = 1,
parameter STAGES = 1)
(
input clock,
input reset,
input [WIDTH-1:0] in,
output reg [WIDTH-1:0] out
);
integer i;
reg [WIDTH-1:0] sr[STAGES]; // Create 'STAGES' number of register, each 'WIDTH' bits wide
/* synopsys dc_tcl_script_begin
set_ungroup [current_design] true
set_flatten true -effort high -phase true -design [current_design]
set_dont_retime [current_design] false
set_optimize_registers true -design [current_design]
*/
always @(posedge clock) begin
if (reset) begin
for(i=0; i<STAGES; i=i+1) begin
sr[i] <= {WIDTH{1'b0}};
end
end else begin
sr[0] <= in;
for(i=1; i<STAGES; i=i+1) begin
sr[i] <= sr[i-1];
end
end
end
always @(*) begin
out <= sr[STAGES-1];
end
endmodule
module RetimeShiftRegisterBool
#(
parameter WIDTH = 1,
parameter STAGES = 1)
(
input clock,
input reset,
input in,
output reg out
);
integer i;
reg sr[STAGES]; // Create 'STAGES' number of register, each 'WIDTH' bits wide
/* synopsys dc_tcl_script_begin
set_ungroup [current_design] true
set_flatten true -effort high -phase true -design [current_design]
set_dont_retime [current_design] false
set_optimize_registers true -design [current_design]
*/
always @(posedge clock) begin
if (reset) begin
for(i=0; i<STAGES; i=i+1) begin
sr[i] <= {WIDTH{1'b0}};
end
end else begin
sr[0] <= in;
for(i=1; i<STAGES; i=i+1) begin
sr[i] <= sr[i-1];
end
end
end
always @(*) begin
out <= sr[STAGES-1];
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
module sky130_fd_io__top_refgen (VINREF, VOUTREF, REFLEAK_BIAS,
HLD_H_N, IBUF_SEL, OD_H, VOHREF, VREF_SEL, VREG_EN, VTRIP_SEL);
wire error_vsel;
output VINREF;
output VOUTREF;
inout REFLEAK_BIAS;
wire vccd =1;
wire vcchib =1;
wire vdda =1;
wire vddio =1;
wire vddio_q=1;
wire vssd =0;
wire vssio =0;
wire vssio_q=0;
input HLD_H_N;
input IBUF_SEL;
input OD_H;
input VOHREF;
input VREF_SEL;
input VREG_EN;
input VTRIP_SEL;
reg [2:0] dm_final;
reg slow_final, vtrip_sel_final, inp_dis_final, hld_ovr_final;
reg [2:0] dm;
reg slow, inp_dis, hld_ovr;
reg [1:0] vsel;
wire pwr_good_hold_mode = 1;
wire pwr_good_active_mode = 1;
always @(*)
begin
if (^OD_H===1'bx || !pwr_good_hold_mode || (OD_H===0 && ^HLD_H_N===1'bx))
begin
dm_final = 3'bxxx;
slow_final = 1'bx;
vtrip_sel_final = 1'bx;
inp_dis_final = 1'bx;
hld_ovr_final = 1'bx;
end
else if (OD_H===1)
begin
dm_final = 3'b000;
slow_final = 1'b0;
vtrip_sel_final = 1'b0;
inp_dis_final = 1'b0;
hld_ovr_final = 1'b0;
end
else if (HLD_H_N===1)
begin
dm_final = (^dm[2:0] === 1'bx || !pwr_good_active_mode) ? 3'bxxx : dm;
slow_final = (^slow === 1'bx || !pwr_good_active_mode) ? 1'bx : slow;
vtrip_sel_final = (^VTRIP_SEL === 1'bx || !pwr_good_active_mode) ? 1'bx : VTRIP_SEL;
inp_dis_final = (^inp_dis === 1'bx || !pwr_good_active_mode) ? 1'bx : inp_dis;
hld_ovr_final = (^hld_ovr === 1'bx || !pwr_good_active_mode) ? 1'bx : hld_ovr;
end
end
reg dis_err_msgs;
initial
begin
dis_err_msgs = 1'b1;
`ifdef SKY130_FD_IO_TOP_REFGEN_DIS_ERR_MSGS
`else
#1;
dis_err_msgs = 1'b0;
`endif
end
assign error_vsel = (vsel[1]===1 && vsel[0]===1);
always @(*)
begin
if (!dis_err_msgs)
begin
if (error_vsel==1) $display(" ===ERROR=== sky130_fd_io__top_refgen : %m : Incorrect inputs on vsel[1:0] = 11",$stime);
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__INV_TB_V
`define SKY130_FD_SC_MS__INV_TB_V
/**
* inv: Inverter.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__inv.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_ms__inv dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__INV_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR2B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__NOR2B_BEHAVIORAL_PP_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nor2b (
VPWR,
VGND,
Y ,
A ,
B_N
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A ;
input B_N ;
// Local signals
wire Y not0_out ;
wire and0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A );
and and0 (and0_out_Y , not0_out, B_N );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR2B_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int N = 3e3 + 10; int n; int a[N], b[N]; long long dp[N][N]; long long solve(int idx = 0, int val = 0) { if (idx == n) return 0; if (val == n) return 1e18; long long &ret = dp[idx][val]; if (ret == -1) ret = min(solve(idx + 1, val) + abs(a[idx] - b[val]), solve(idx, val + 1)); return ret; } int main() { scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d , &a[i]); b[i] = a[i] -= i; } sort(b, b + n); memset(dp, -1, sizeof(dp)); printf( %lld n , solve()); return 0; } |
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module ram16_2port (input clock, input write,
input [3:0] wr_addr, input [15:0] wr_data,
input [3:0] rd_addr1, output reg [15:0] rd_data1,
input [3:0] rd_addr2, output reg [15:0] rd_data2);
reg [15:0] ram_array [0:31];
always @(posedge clock)
rd_data1 <= #1 ram_array[rd_addr1];
always @(posedge clock)
rd_data2 <= #1 ram_array[rd_addr2];
always @(posedge clock)
if(write)
ram_array[wr_addr] <= #1 wr_data;
endmodule // ram16_2port
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
//------------------------------------------------------------------------------
// SHARED CODE
//------------------------------------------------------------------------------
// No shared code for this OVL
//------------------------------------------------------------------------------
// ASSERTION
//------------------------------------------------------------------------------
`ifdef OVL_ASSERT_ON
// 2-STATE
// =======
wire fire_2state_1;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_2state_1) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression evaluates to a value outside the range specified by parameters min and max");
end
end
end
assign fire_2state_1 = ((test_expr < min) || (test_expr > max));
// X-CHECK
// =======
`ifdef OVL_XCHECK_OFF
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
`else
reg fire_xcheck_1;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_xcheck_1) begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
end
end
wire valid_test_expr = ((test_expr ^ test_expr) == 1'b0);
always @ (valid_test_expr) begin
if (valid_test_expr) begin
fire_xcheck_1 = 1'b0;
end
else begin
fire_xcheck_1 = 1'b1;
end
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`endif // OVL_ASSERT_ON
//------------------------------------------------------------------------------
// COVERAGE
//------------------------------------------------------------------------------
`ifdef OVL_COVER_ON
// Auxiliary logic
reg [width-1:0] prev_test_expr;
always @ (posedge clk) begin
// REVISIT: update only if SANITY on?
prev_test_expr <= test_expr; // deliberately not reset
end
wire fire_cover_1, fire_cover_2, fire_cover_3;
always @ (posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_cover_1) begin
ovl_cover_t("test_expr_change covered"); // sanity
end
if (fire_cover_2) begin
ovl_cover_t("test_expr_at_min covered"); // corner
end
if (fire_cover_3) begin
ovl_cover_t("test_expr_at_max covered"); // corner
end
end
end
assign fire_cover_1 = ((OVL_COVER_SANITY_ON > 0) && (test_expr != prev_test_expr));
assign fire_cover_2 = ((OVL_COVER_CORNER_ON > 0) && (test_expr == min));
assign fire_cover_3 = ((OVL_COVER_CORNER_ON > 0) && (test_expr == max));
`endif // OVL_COVER_ON
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [15:0] m_din;
// We expect all these blocks should split;
// blocks that don't split should go in t_alw_nosplit.v
reg [15:0] a_split_1, a_split_2;
always @ (/*AS*/m_din) begin
a_split_1 = m_din;
a_split_2 = m_din;
end
reg [15:0] d_split_1, d_split_2;
always @ (posedge clk) begin
d_split_1 <= m_din;
d_split_2 <= d_split_1;
d_split_1 <= ~m_din;
end
reg [15:0] h_split_1;
reg [15:0] h_split_2;
always @ (posedge clk) begin
// $write(" cyc = %x m_din = %x\n", cyc, m_din);
if (cyc > 2) begin
if (m_din == 16'h0) begin
h_split_1 <= 16'h0;
h_split_2 <= 16'h0;
end
else begin
h_split_1 <= m_din;
h_split_2 <= ~m_din;
end
end
else begin
h_split_1 <= 16'h0;
h_split_2 <= 16'h0;
end
end
reg [15:0] l_split_1, l_split_2;
always @ (posedge clk) begin
l_split_2 <= l_split_1;
l_split_1 <= l_split_2 | m_din;
end
// (The checker block is an exception, it won't split.)
always @ (posedge clk) begin
if (cyc!=0) begin
cyc<=cyc+1;
if (cyc==1) begin
m_din <= 16'hfeed;
end
if (cyc==3) begin
end
if (cyc==4) begin
m_din <= 16'he11e;
//$write(" A %x %x\n", a_split_1, a_split_2);
if (!(a_split_1==16'hfeed && a_split_2==16'hfeed)) $stop;
if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop;
if (!(h_split_1==16'hfeed && h_split_2==16'h0112)) $stop;
end
if (cyc==5) begin
m_din <= 16'he22e;
if (!(a_split_1==16'he11e && a_split_2==16'he11e)) $stop;
if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop;
if (!(h_split_1==16'hfeed && h_split_2==16'h0112)) $stop;
end
if (cyc==6) begin
m_din <= 16'he33e;
if (!(a_split_1==16'he22e && a_split_2==16'he22e)) $stop;
if (!(d_split_1==16'h1ee1 && d_split_2==16'h0112)) $stop;
if (!(h_split_1==16'he11e && h_split_2==16'h1ee1)) $stop;
end
if (cyc==7) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end // always @ (posedge clk)
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O221AI_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__O221AI_PP_SYMBOL_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o221ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
input C1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O221AI_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int dp[3000]; bool apare[1010]; int n, k, c; int main() { ios_base ::sync_with_stdio(0); cin >> n >> k; while (k--) { cin >> c; apare[c] = 1; } queue<int> q; vector<int> lungimi; for (int i(0); i < 1010; i++) { if (!apare[i]) continue; int x(n - i + 1500); dp[x] = 1; q.push(x); lungimi.push_back(x - 1500); } while (!q.empty()) { int x(q.front()), t(dp[x]); q.pop(); for (auto i : lungimi) { if (x + i >= 0 && x + i < 3000 && !dp[x + i]) { dp[x + i] = 1 + t; q.push(x + i); } } } cout << (dp[1500] ? dp[1500] : -1); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long max_N = 100003; const long long max_M = 200003; vector<pair<long long, long long> > briaunos[max_N]; bool nepavyko_uzdavinys = false; struct reiskinys { long long skaicius, a; long double a_reiksme; bool isreikstas; bool isvestas; long double a_reiksme_kai_reisinys_nulis; reiskinys() { isreikstas = false; isvestas = false; skaicius = 0; a = 0; } void tapk_pradiniu() { skaicius = 0; a = 1; isreikstas = true; } long double reiksme() { return (long double)a_reiksme * (long double)a + (long double)skaicius; } void kada_tampa_nuliu() { if ((a == 0) && (skaicius == 0)) a_reiksme_kai_reisinys_nulis = 0; else if (a == 0) a_reiksme_kai_reisinys_nulis = 1000000000; else a_reiksme_kai_reisinys_nulis = ((long double)0 - (long double)skaicius) / (long double)a; } bool operator<(const reiskinys &kitas) const { return a_reiksme_kai_reisinys_nulis < kitas.a_reiksme_kai_reisinys_nulis; } }; reiskinys virsuniu_reiksmes[max_N]; void isreisk(reiskinys &turimas, reiskinys &norimas, long long suma) { norimas.a = 0 - turimas.a; norimas.skaicius = suma - turimas.skaicius; norimas.isreikstas = true; } pair<bool, long double> rask_a_reiksme(reiskinys &pirmas, reiskinys &antras, long double suma) { long long skaicius = 0 - (suma - pirmas.skaicius - antras.skaicius); long long a = 0 - pirmas.a - antras.a; if ((a == 0) && (skaicius != 0)) { nepavyko_uzdavinys = true; return {false, 0}; } else if (a == 0) { return {false, 0}; } else { long double a_reiksme = (long double)skaicius / (long double)a; return {true, a_reiksme}; } } bool tenkina(reiskinys &pirmas, reiskinys &antras, long double suma) { if (pirmas.reiksme() + antras.reiksme() == suma) return true; return false; } void ieskok_minimalaus_a(vector<long long> komponente) { for (long long i = 0; i < komponente.size(); i++) { virsuniu_reiksmes[komponente[i]].kada_tampa_nuliu(); } sort(komponente.begin(), komponente.end(), [&](long long &i, long long &j) { return virsuniu_reiksmes[i] < virsuniu_reiksmes[j]; }); reiskinys neigiami; reiskinys teigiami; long double a_reiksme = virsuniu_reiksmes[komponente[0]].a_reiksme_kai_reisinys_nulis - 1; bool ar_teigiamas[komponente.size()]; for (long long i = 0; i < komponente.size(); i++) { virsuniu_reiksmes[komponente[i]].a_reiksme = a_reiksme; if (virsuniu_reiksmes[komponente[i]].reiksme() > (long double)0) { ar_teigiamas[i] = true; teigiami.a += virsuniu_reiksmes[komponente[i]].a; teigiami.skaicius += virsuniu_reiksmes[komponente[i]].skaicius; } else { ar_teigiamas[i] = false; neigiami.a -= virsuniu_reiksmes[komponente[i]].a; neigiami.skaicius -= virsuniu_reiksmes[komponente[i]].skaicius; } } neigiami.a_reiksme = a_reiksme; teigiami.a_reiksme = a_reiksme; long double minimalus_ats = teigiami.reiksme() + neigiami.reiksme(); long double minimali_a_reiksme = a_reiksme; for (long long i = 0; i < komponente.size(); i++) { long double a_reiksme = virsuniu_reiksmes[komponente[i]].a_reiksme_kai_reisinys_nulis; neigiami.a_reiksme = a_reiksme; teigiami.a_reiksme = a_reiksme; if (ar_teigiamas[i]) { teigiami.a -= virsuniu_reiksmes[komponente[i]].a; teigiami.skaicius -= virsuniu_reiksmes[komponente[i]].skaicius; neigiami.a -= virsuniu_reiksmes[komponente[i]].a; neigiami.skaicius -= virsuniu_reiksmes[komponente[i]].skaicius; } else { neigiami.a += virsuniu_reiksmes[komponente[i]].a; neigiami.skaicius += virsuniu_reiksmes[komponente[i]].skaicius; teigiami.a += virsuniu_reiksmes[komponente[i]].a; teigiami.skaicius += virsuniu_reiksmes[komponente[i]].skaicius; } if (teigiami.reiksme() + neigiami.reiksme() < minimalus_ats) { minimalus_ats = teigiami.reiksme() + neigiami.reiksme(); minimali_a_reiksme = a_reiksme; } } for (long long i = 0; i < komponente.size(); i++) virsuniu_reiksmes[komponente[i]].a_reiksme = minimali_a_reiksme; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long N, M; cin >> N >> M; for (long long i = 0; i < M; i++) { long long a, b, tipas; cin >> a >> b >> tipas; briaunos[a].push_back({b, tipas}); briaunos[b].push_back({a, tipas}); } bool surastas[N + 1]; for (long long i = 1; i <= N; i++) surastas[i] = false; for (long long i = 1; i <= N; i++) { if (surastas[i]) continue; queue<long long> eile; vector<long long> komponente; eile.push(i); komponente.push_back(i); surastas[i] = true; virsuniu_reiksmes[i].tapk_pradiniu(); while (!eile.empty()) { long long g = eile.front(); eile.pop(); for (long long j = 0; j < briaunos[g].size(); j++) { long long kitas = briaunos[g][j].first; if (surastas[kitas]) continue; if (g == kitas) continue; isreisk(virsuniu_reiksmes[g], virsuniu_reiksmes[kitas], briaunos[g][j].second); surastas[kitas] = true; eile.push(kitas); komponente.push_back(kitas); } } bool radau_a_reiksme = false; long double a_reiksme; for (long long j = 0; j < komponente.size(); j++) { long long dab = komponente[j]; for (long long x = 0; x < briaunos[dab].size(); x++) { long long kitas = briaunos[dab][x].first; pair<bool, long double> ats = rask_a_reiksme(virsuniu_reiksmes[dab], virsuniu_reiksmes[kitas], briaunos[dab][x].second); radau_a_reiksme = ats.first; a_reiksme = ats.second; if (radau_a_reiksme) { break; } } if (radau_a_reiksme) break; } if (radau_a_reiksme) { for (long long j = 0; j < komponente.size(); j++) { virsuniu_reiksmes[komponente[j]].a_reiksme = a_reiksme; } for (long long j = 0; j < komponente.size(); j++) { long long dab = komponente[j]; for (long long x = 0; x < briaunos[dab].size(); x++) { long long kitas = briaunos[dab][x].first; if (!tenkina(virsuniu_reiksmes[dab], virsuniu_reiksmes[kitas], briaunos[dab][x].second)) { nepavyko_uzdavinys = true; } } } } else { ieskok_minimalaus_a(komponente); } } if (nepavyko_uzdavinys) cout << NO ; else { cout << YES n ; for (long long i = 1; i <= N; i++) cout << fixed << setprecision(9) << virsuniu_reiksmes[i].reiksme() << ; } return 0; } |
module tb_comm_fpga_fx2_v2;
reg clk_in;
reg reset_in;
wire fx2FifoSel_out;
reg [7:0] fx2Data_in;
wire [7:0] fx2Data_out;
wire fx2Data_sel;
reg fx2Read_out;
reg fx2GotData_in;
reg fx2Write_out;
reg fx2GotRoom_in;
reg fx2PktEnd_out;
reg [6:0] chanAddr_out;
reg [7:0] h2fData_out;
reg h2fValid_out;
reg h2fReady_in;
reg [7:0] f2hData_in;
reg f2hValid_in;
reg f2hReady_out;
initial begin
$from_myhdl(
clk_in,
reset_in,
fx2Data_in,
fx2Read_out,
fx2GotData_in,
fx2Write_out,
fx2GotRoom_in,
fx2PktEnd_out,
chanAddr_out,
h2fData_out,
h2fValid_out,
h2fReady_in,
f2hData_in,
f2hValid_in,
f2hReady_out
);
$to_myhdl(
fx2FifoSel_out,
fx2Data_out,
fx2Data_sel
);
end
comm_fpga_fx2_v2 dut(
clk_in,
reset_in,
fx2FifoSel_out,
fx2Data_in,
fx2Data_out,
fx2Data_sel,
fx2Read_out,
fx2GotData_in,
fx2Write_out,
fx2GotRoom_in,
fx2PktEnd_out,
chanAddr_out,
h2fData_out,
h2fValid_out,
h2fReady_in,
f2hData_in,
f2hValid_in,
f2hReady_out
);
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module cpu_mult_cell (
// inputs:
M_mul_src1,
M_mul_src2,
clk,
reset_n,
// outputs:
M_mul_cell_result
)
;
output [ 31: 0] M_mul_cell_result;
input [ 31: 0] M_mul_src1;
input [ 31: 0] M_mul_src2;
input clk;
input reset_n;
wire [ 31: 0] M_mul_cell_result;
wire [ 31: 0] M_mul_cell_result_part_1;
wire [ 15: 0] M_mul_cell_result_part_2;
wire mul_clr;
assign mul_clr = ~reset_n;
altmult_add the_altmult_add_part_1
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (M_mul_src1[15 : 0]),
.datab (M_mul_src2[15 : 0]),
.ena0 (1'b1),
.result (M_mul_cell_result_part_1)
);
defparam the_altmult_add_part_1.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_part_1.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_part_1.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_part_1.dedicated_multiplier_circuitry = "YES",
the_altmult_add_part_1.input_register_a0 = "UNREGISTERED",
the_altmult_add_part_1.input_register_b0 = "UNREGISTERED",
the_altmult_add_part_1.input_source_a0 = "DATAA",
the_altmult_add_part_1.input_source_b0 = "DATAB",
the_altmult_add_part_1.intended_device_family = "CYCLONEII",
the_altmult_add_part_1.lpm_type = "altmult_add",
the_altmult_add_part_1.multiplier1_direction = "ADD",
the_altmult_add_part_1.multiplier_aclr0 = "ACLR0",
the_altmult_add_part_1.multiplier_register0 = "CLOCK0",
the_altmult_add_part_1.number_of_multipliers = 1,
the_altmult_add_part_1.output_register = "UNREGISTERED",
the_altmult_add_part_1.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_part_1.port_signa = "PORT_UNUSED",
the_altmult_add_part_1.port_signb = "PORT_UNUSED",
the_altmult_add_part_1.representation_a = "UNSIGNED",
the_altmult_add_part_1.representation_b = "UNSIGNED",
the_altmult_add_part_1.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_part_1.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_part_1.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_part_1.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_part_1.signed_register_a = "UNREGISTERED",
the_altmult_add_part_1.signed_register_b = "UNREGISTERED",
the_altmult_add_part_1.width_a = 16,
the_altmult_add_part_1.width_b = 16,
the_altmult_add_part_1.width_result = 32;
altmult_add the_altmult_add_part_2
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (M_mul_src1[31 : 16]),
.datab (M_mul_src2[15 : 0]),
.ena0 (1'b1),
.result (M_mul_cell_result_part_2)
);
defparam the_altmult_add_part_2.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_part_2.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_part_2.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_part_2.dedicated_multiplier_circuitry = "YES",
the_altmult_add_part_2.input_register_a0 = "UNREGISTERED",
the_altmult_add_part_2.input_register_b0 = "UNREGISTERED",
the_altmult_add_part_2.input_source_a0 = "DATAA",
the_altmult_add_part_2.input_source_b0 = "DATAB",
the_altmult_add_part_2.intended_device_family = "CYCLONEII",
the_altmult_add_part_2.lpm_type = "altmult_add",
the_altmult_add_part_2.multiplier1_direction = "ADD",
the_altmult_add_part_2.multiplier_aclr0 = "ACLR0",
the_altmult_add_part_2.multiplier_register0 = "CLOCK0",
the_altmult_add_part_2.number_of_multipliers = 1,
the_altmult_add_part_2.output_register = "UNREGISTERED",
the_altmult_add_part_2.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_part_2.port_signa = "PORT_UNUSED",
the_altmult_add_part_2.port_signb = "PORT_UNUSED",
the_altmult_add_part_2.representation_a = "UNSIGNED",
the_altmult_add_part_2.representation_b = "UNSIGNED",
the_altmult_add_part_2.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_part_2.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_part_2.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_part_2.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_part_2.signed_register_a = "UNREGISTERED",
the_altmult_add_part_2.signed_register_b = "UNREGISTERED",
the_altmult_add_part_2.width_a = 16,
the_altmult_add_part_2.width_b = 16,
the_altmult_add_part_2.width_result = 16;
assign M_mul_cell_result = {M_mul_cell_result_part_1[31 : 16] +
M_mul_cell_result_part_2,
M_mul_cell_result_part_1[15 : 0]};
endmodule
|
#include <bits/stdc++.h> int main() { double n2, a, b, c, n1; scanf( %lf %lf %lf , &a, &b, &c); n1 = ((-b + pow((b * b - 4 * a * c), 0.5)) / (a * 2)); n2 = ((-b - pow((b * b - 4 * a * c), 0.5)) / (a * 2)); if (n1 >= n2) printf( %lf %lf , n1, n2); else printf( %lf %lf , n2, n1); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; int n, k, par[N], siz[N]; bool inv[N]; multiset<int> S; struct dist { int val, id; }; dist tab[N]; bool cmp(dist x, dist y) { return x.val < y.val; } int Find(int x) { if (par[x] != x) par[x] = Find(par[x]); return par[x]; } void Union(int x, int y) { x = Find(x); y = Find(y); par[x] = y; S.erase(S.find(siz[x])); S.erase(S.find(siz[y])); siz[y] += siz[x]; S.insert(siz[y]); } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &tab[i].val); tab[i].id = i; } sort(tab + 1, tab + n + 1, cmp); int ans = 0, ile = 0; multiset<int>::iterator low, high; for (int i = 1; i <= n; i++) { int x = tab[i].id; inv[x] = 1; S.insert(1); siz[x] = 1; par[x] = x; if (inv[x - 1]) Union(x - 1, x); if (inv[x + 1]) Union(x + 1, x); low = S.begin(); high = S.end(); high--; if (*high == *low) { if (ile < S.size()) { ile = S.size(); ans = tab[i].val + 1; } } } printf( %d , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; #define ll long long #define mod 1000000007 #define ffor(i,a,b) for(int i=a;i<b;i++) #define bfor(i,a,b) for(int i=a-1;i>=b;i--) #define mp make_pair #define pb push_back #define ff first #define ss second #define mem(x,y) memset(x,y,sizeof(x)) #define all(x) x.begin(),x.end() #define SP(x) setprecision(x) #define sz(x) (int)x.size() #define fast ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL) #define PI 3.14159265358979323846 #define lb lower_bound #define ub upper_bound #define bs binary_search #define endl n #define int long long void solve() { int n; cin>>n; int c[n]; int a[n], b[n]; ffor(i,0,n) cin>>c[i]; ffor(i,0,n) cin>>a[i]; ffor(i,0,n) cin>>b[i]; int ans=0; int dp[n]; mem(dp,0); dp[1]=abs(a[1]-b[1])+c[1]-1+2; ffor(i,2,n) { if(a[i]==b[i]) dp[i]=c[i]-1+2; else { int x=abs(a[i]-b[i])+c[i]-1+2; int y=c[i]-1+2+dp[i-1]-abs(a[i]-b[i]); dp[i]=max(x,y); } } cout<< *max_element(dp,dp+n)<<endl; } signed main() { #ifndef ONLINE_JUDGE freopen( input.txt , r , stdin); freopen( output.txt , w , stdout); #endif int t; cin>>t; while(t--) { solve(); } return 0; } |
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo_mixed_widths
// ============================================================
// File Name: rxlengthfifo_128x13.v
// Megafunction Name(s):
// dcfifo_mixed_widths
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 173 11/01/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module rxlengthfifo_128x13 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input aclr;
input [14:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [14:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "512"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "15"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "1"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "15"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "15"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
// Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "9"
// Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "15"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 15 0 INPUT NODEFVAL "data[14..0]"
// Retrieval info: USED_PORT: q 0 0 15 0 OUTPUT NODEFVAL "q[14..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 15 0 data 0 0 15 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 15 0 @q 0 0 15 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL rxlengthfifo_128x13.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rxlengthfifo_128x13.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rxlengthfifo_128x13.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rxlengthfifo_128x13.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rxlengthfifo_128x13_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rxlengthfifo_128x13_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; long long n, res, dpa[4005][4005], s[4005], c[4005][4005]; long long combo(long long x, long long y) { if (c[x][y] != 0) return c[x][y]; if (y == 0 || x == y) return c[x][y] = 1; if (x == 0 || x < y) return 0; return c[x][y] = (combo(x - 1, y - 1) + combo(x - 1, y)) % 1000000007; } int main() { cin >> n; dpa[0][0] = s[0] = 1; for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { dpa[i][j] = dpa[i - 1][j - 1] + dpa[i - 1][j] * j; dpa[i][j] %= 1000000007; s[i] += dpa[i][j]; s[i] %= 1000000007; } } for (int i = 0; i < n; i++) { res += combo(n, n - i) * s[i]; res %= 1000000007; } cout << res; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 110; int T, mod = 1e9 + 7, n, k, deep[N], timer, sz; long long ans, fact[N], mem[N][N], vis[N][N]; vector<int> adj[N], v; map<int, int> mp[N]; void _clear() { ans = 0; for (int i = 1; i <= n; i++) adj[i].clear(); } long long po(long long x, long long os) { if (os == 0) return 1; long long z = po(x, os / 2); if (os & 1) return z * z % mod * x % mod; return z * z % mod; } long long modInv(long long x) { return po(x, mod - 2); } long long c(long long n, long long r) { return fact[n] * modInv(fact[r] * fact[n - r] % mod) % mod; } void dfs(int u, int v) { deep[u] = deep[v] + 1; mp[u][deep[u]]++; for (auto &x : adj[u]) if (x != v) { dfs(x, u); for (auto &p : mp[x]) mp[u][p.first] += p.second; } } long long dp(int i, int k) { if (k == 0) return 1; if (i == sz) return 0; long long &ret = mem[i][k]; if (vis[i][k] == timer) return ret; vis[i][k] = timer; return ret = (dp(i + 1, k) + dp(i + 1, k - 1) * v[i] % mod) % mod; } long long calc(int p) { deep[p] = 0; for (int i = 1; i <= n; i++) mp[i].clear(); dfs(p, p); long long ret = 0; for (int i = 2; i <= n; i++) { int num = 0; v.clear(); for (auto &x : adj[p]) if (mp[x].find(i) != mp[x].end()) { num++; v.push_back(mp[x][i]); } if (num < k) continue; timer++; sz = (int)(v.size()); ret = (ret + dp(0, k)) % mod; } return ret; } int main() { fact[0] = 1; for (int i = 1; i < N; i++) fact[i] = fact[i - 1] * i % mod; scanf( %d , &T); while (T--) { scanf( %d%d , &n, &k); _clear(); for (int i = 1; i <= n - 1; i++) { int a, b; scanf( %d%d , &a, &b); adj[a].push_back(b); adj[b].push_back(a); } if (k == 2) { printf( %lld n , c(n, 2)); continue; } for (int i = 1; i <= n; i++) ans = (ans + calc(i)) % mod; printf( %lld n , ans); } } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04.03.2016 14:20:17
// Design Name:
// Module Name: LUT_Z
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module LUT_Z#(parameter P = 32, parameter D = 5) (
input wire CLK,
input wire EN_ROM1,
input wire [D-1:0] ADRS,
output reg [P-1:0] O_D
);
always @(posedge CLK)
if (EN_ROM1)
case (ADRS)
5'b00000: O_D <= 32'b10111111100011001001111101010100;
5'b00001: O_D <= 32'b10111111000000101100010101111000;
5'b00010: O_D <= 32'b10111110100000001010110001001001;
5'b00011: O_D <= 32'b10111110000000000010101011000100;
5'b00100: O_D <= 32'b10111110000000000010101011000100;
5'b00101: O_D <= 32'b10111101100000000000101010101100;
5'b00110: O_D <= 32'b10111101000000000000001010101011;
5'b00111: O_D <= 32'b10111100100000000000000010101011;
5'b01000: O_D <= 32'b10111100000000000000000000101011;
5'b01001: O_D <= 32'b10111011010111100011010101000010;
5'b01010: O_D <= 32'b10111011000000000000000000000011;
5'b01011: O_D <= 32'b10111010100000000000000000000001;
5'b01100: O_D <= 32'b10111010000000000000000000000000;
5'b01101: O_D <= 32'b10111001100000000000000000000000;
5'b01110: O_D <= 32'b10111001100000000000000000000000;
5'b01111: O_D <= 32'b10111001000000000000000000000000;
5'b10000: O_D <= 32'b10111000100000000000000000000000;
5'b10001: O_D <= 32'b10111000000000000000000000000000;
5'b10010: O_D <= 32'b10110111100000000000000000000000;
5'b10011: O_D <= 32'b10110111000000000000000000000000;
5'b10100: O_D <= 32'b10110110100000000000000000000000;
5'b10101: O_D <= 32'b10110110000000000000000000000000;
5'b10110: O_D <= 32'b10110101100000000000000000000000;
5'b10111: O_D <= 32'b10110101000000000000000000000000;
5'b11000: O_D <= 32'b10110100100000000000000000000000;
5'b11001: O_D <= 32'b10110100000000000000000000000000;
5'b11010: O_D <= 32'b10110011100000000000000000000000;
5'b11011: O_D <= 32'b10110011000000000000000000000000;
5'b11100: O_D <= 32'b10110010100000000000000000000000;
5'b11101: O_D <= 32'b10110010000000000000000000000000;
5'b11110: O_D <= 32'b10110001100000000000000000000000;
5'b11111: O_D <= 32'b10110001000000000000000000000000;
default: O_D <= 32'b00000000000000000000000000000000;
endcase
else
O_D <= 32'b00000000000000000000000000000000;
endmodule |
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE Connection Matrix Priority Decoder ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/wb_conmax/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: wb_conmax_pri_dec.v,v 1.2 2002-10-03 05:40:07 rudi Exp $
//
// $Date: 2002-10-03 05:40:07 $
// $Revision: 1.2 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2001/10/19 11:01:42 rudi
// WISHBONE CONMAX IP Core
//
//
//
//
//
`include "wb_conmax_defines.v"
module wb_conmax_pri_dec(valid, pri_in, pri_out);
////////////////////////////////////////////////////////////////////
//
// Module Parameters
//
parameter [1:0] pri_sel = 2'd0;
////////////////////////////////////////////////////////////////////
//
// Module IOs
//
input valid;
input [1:0] pri_in;
output [3:0] pri_out;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
wire [3:0] pri_out;
reg [3:0] pri_out_d0;
reg [3:0] pri_out_d1;
////////////////////////////////////////////////////////////////////
//
// Priority Decoder
//
// 4 Priority Levels
always @(valid or pri_in)
if(!valid) pri_out_d1 = 4'b0001;
else
if(pri_in==2'h0) pri_out_d1 = 4'b0001;
else
if(pri_in==2'h1) pri_out_d1 = 4'b0010;
else
if(pri_in==2'h2) pri_out_d1 = 4'b0100;
else pri_out_d1 = 4'b1000;
// 2 Priority Levels
always @(valid or pri_in)
if(!valid) pri_out_d0 = 4'b0001;
else
if(pri_in==2'h0) pri_out_d0 = 4'b0001;
else pri_out_d0 = 4'b0010;
// Select Configured Priority
assign pri_out = (pri_sel==2'd0) ? 4'h0 : ( (pri_sel==1'd1) ? pri_out_d0 : pri_out_d1 );
endmodule
|
#include <bits/stdc++.h> using namespace std; void read(int& x) { bool fu = 0; char c; for (c = getchar(); c <= 32; c = getchar()) ; if (c == - ) fu = 1, c = getchar(); for (x = 0; c > 32; c = getchar()) x = x * 10 + c - 0 ; if (fu) x = -x; }; char getc() { char c; for (c = getchar(); c <= 32; c = getchar()) ; return c; } const int N = 100010; int n, i, j, k, l, p, x, a[N], s0, s1; int b[N]; int main() { read(n); for (i = 1; i <= n; i++) read(a[i]); for (i = 1; i <= n && a[i] == 0; i++) printf( 0 n ); for (; i <= n; i = j + 1) { for (j = i; j <= n && a[j] > 0; j++) ; j--; if (j + 1 > n) { for (k = i; k <= n; k++) printf( pushStack n ); break; } b[0] = 0; for (k = i; k <= j; k++) b[++b[0]] = a[k]; sort(b + 1, b + 1 + b[0]); if (b[0] == 0) printf( 0 n ); else if (b[0] == 1) printf( pushStack n1 popStack n ); else if (b[0] == 2) printf( pushStack npushQueue n2 popStack popQueue n ); else { p = b[b[0] - 2]; for (k = i; k <= j; k++) if (a[k] >= p) break; s0 = k; for (k = j; k >= i; k--) if (a[k] >= p) break; s1 = k; if (s1 <= s0) printf( - - n ); for (k = i; k <= j; k++) if (k == s1) printf( pushStack n ); else if (k == s0) printf( pushQueue n ); else if (a[k] >= p) printf( pushFront n ); else if (k < s1) printf( pushStack n ); else printf( pushQueue n ); printf( 3 popStack popQueue popFront n ); } j++; } scanf( n ); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFRTP_TB_V
`define SKY130_FD_SC_HD__SDFRTP_TB_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__sdfrtp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg RESET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 SCD = 1'b0;
#80 SCE = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 D = 1'b1;
#200 RESET_B = 1'b1;
#220 SCD = 1'b1;
#240 SCE = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 D = 1'b0;
#360 RESET_B = 1'b0;
#380 SCD = 1'b0;
#400 SCE = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 SCE = 1'b1;
#600 SCD = 1'b1;
#620 RESET_B = 1'b1;
#640 D = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 SCE = 1'bx;
#760 SCD = 1'bx;
#780 RESET_B = 1'bx;
#800 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hd__sdfrtp dut (.D(D), .SCD(SCD), .SCE(SCE), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFRTP_TB_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, i, j, k, p, t, a = 0, b = 0; cin >> n; vector<long long int> vec; for (i = 0; i < n; i++) { cin >> p; if (p % 2 == 0) a++; else b++; vec.push_back(p); } if (a == 0 || b == 0) { for (i = 0; i < n; i++) cout << vec[i] << ; } else { sort(vec.begin(), vec.end()); for (i = 0; i < n; i++) cout << vec[i] << ; } } |
//#############################################################################
//# Function: 7:1 one hot mux #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_mux7 #(parameter DW = 1 ) // width of mux
(
input sel6,
input sel5,
input sel4,
input sel3,
input sel2,
input sel1,
input sel0,
input [DW-1:0] in6,
input [DW-1:0] in5,
input [DW-1:0] in4,
input [DW-1:0] in3,
input [DW-1:0] in2,
input [DW-1:0] in1,
input [DW-1:0] in0,
output [DW-1:0] out //selected data output
);
assign out[DW-1:0] = ({(DW){sel0}} & in0[DW-1:0] |
{(DW){sel1}} & in1[DW-1:0] |
{(DW){sel2}} & in2[DW-1:0] |
{(DW){sel3}} & in3[DW-1:0] |
{(DW){sel4}} & in4[DW-1:0] |
{(DW){sel5}} & in5[DW-1:0] |
{(DW){sel6}} & in6[DW-1:0]);
endmodule // oh_mux7
|
module top;
reg passed = 1'b1;
wire out, cout0, cout1;
reg sel, in_1, in_0;
reg pout;
assign cout0 = sel ? 1'bz : in_0;
assign cout1 = sel ? in_1: 1'bz;
assign out = sel ? in_1: in_0;
task automatic check;
input bit, in_1, in_0;
input [63:0] comment;
begin
if (sel === 1'b1) begin
if (bit !== in_1) begin
$display("FAILED: %0s sel = 1'b1, expected %b, got %b",
comment, in_1, bit);
passed = 1'b0;
end
end else if (sel === 1'b0) begin
if (bit !== in_0) begin
$display("FAILED: %0s sel = 1'b0, expected %b, got %b",
comment, in_0, bit);
passed = 1'b0;
end
end else begin
// This is technically incorrect for 1'bz inputs. The standard
// states that we should produce 1'bx for that case (idiotic)!
if (in_0 === in_1 && in_0 !== bit) begin
$display("FAILED: %0s sel = 1'bx/z & ins = %b, expected 1'b%b, got %b",
comment, in_0, in_0, bit);
passed = 1'b0;
end else if (in_0 !== in_1 && bit !== 1'bx) begin
$display("FAILED: %0s sel = 1'bx/z & %b %b, expected 1'bx, got %b",
comment, in_1, in_0, bit);
passed = 1'b0;
end
end
end
endtask
// Check the 1 case as a constant Z
always @(cout0) begin
check(cout0, 1'bz, in_0, "CZ 1");
end
// Check the 0 case as a constant Z
always @(cout1) begin
check(cout1, in_1, 1'bz, "CZ 0");
end
// Check the continuous assign
always @(out) begin
check(out, in_1, in_0, "CA");
end
// Check procedural assign.
always @(sel, in_1, in_0) begin
check(sel ? in_1 : in_0, in_1, in_0, "PR");
end
initial begin
#1 sel = 1'b1;
#1 in_1 = 1'b0;
#1 in_1 = 1'b1;
#1 in_1 = 1'bz;
#1 in_1 = 1'bx;
#1 sel = 1'b0;
#1 in_0 = 1'b0;
#1 in_0 = 1'b1;
#1 in_0 = 1'bz;
#1 in_0 = 1'bx;
#1 sel = 1'bx;
#1 in_1 = 1'b0; //
#1 in_0 = 1'b0;
#1 in_0 = 1'b1;
#1 in_0 = 1'bz;
#1 in_0 = 1'bx;
#1 in_1 = 1'b1; //
#1 in_0 = 1'b0;
#1 in_0 = 1'b1;
#1 in_0 = 1'bz;
#1 in_0 = 1'bx;
#1 in_1 = 1'bz; //
#1 in_0 = 1'b0;
#1 in_0 = 1'b1;
#1 in_0 = 1'bz;
#1 in_0 = 1'bx;
#1 in_1 = 1'bx; //
#1 in_0 = 1'b0;
#1 in_0 = 1'b1;
#1 in_0 = 1'bz;
#1 in_0 = 1'bx;
#1 sel = 1'bz;
#1 in_1 = 1'b0; //
#1 in_0 = 1'b0;
#1 in_0 = 1'b1;
#1 in_0 = 1'bz;
#1 in_0 = 1'bx;
#1 in_1 = 1'b1; //
#1 in_0 = 1'b0;
#1 in_0 = 1'b1;
#1 in_0 = 1'bz;
#1 in_0 = 1'bx;
#1 in_1 = 1'bz; //
#1 in_0 = 1'b0;
#1 in_0 = 1'b1;
#1 in_0 = 1'bz;
#1 in_0 = 1'bx;
#1 in_1 = 1'bx; //
#1 in_0 = 1'b0;
#1 in_0 = 1'b1;
#1 in_0 = 1'bz;
#1 in_0 = 1'bx;
#1 if (passed) $display("PASSED");
end
endmodule
|
//*******************************************************************************************************************************************************/
// Module Name: control_matrix
// Module Type: Moore State Machine
// Author: Shreyas Vinod
// Purpose: Control Matrix for Neptune I v3.0
// Description: A Moore State Machine designed to be Neptune I's Control Matrix. The next state is determined by comparing the current OPcode to the
// State Clock Register, a four bit register that keeps track of the progress of the current instruction. The State Clock is incremented
// after every microinstruction. The Instruction Register is built-in to the Control Matrix.
//*******************************************************************************************************************************************************/
module control_matrix(clk, rst, dma_req, rf_mem_fault, stack_mem_fault, alu_o_flag, alu_z_flag, alu_n_flag, alu_cond_flag, mar_incr, alu_enable, we_in, ins_in, dma_appr, sys_halt, prc, intr_ack, rf_add1, rf_add2, alu_opcode, state);
// Parameter Definitions
parameter width = 'd16; // Data Width
parameter rf_add_width = 'd3; // Register File Depth
parameter ins_width = 'd16; // Instruction Width, heavily impacts the Instruction Decode and Execute Process
// Inputs
input wire clk /* System Clock */, rst /* System Reset. Resets States, State Clock and Halt conditions */, dma_req /* Direct Memory Access (DMA) Request */; // Management Interfaces
input wire rf_mem_fault /* Register File Memory Fault */, stack_mem_fault /* Stack Memory Fault */;
input wire alu_o_flag /* ALU Overflow Flag */, alu_z_flag /* ALU Zero Flag */, alu_n_flag /* ALU Sign Flag */, alu_cond_flag /* ALU Conditional Flag */;
input wire mar_incr /* Direct Memory Access (DMA) Increment Memory Address Register (MAR) Request */;
input wire [2:0] we_in /* Direct Memory Access (DMA) External Write Enable Request */;
input wire [width-1:0] ins_in /* Input Port for Instructions */;
// Outputs
output wire dma_appr /* DMA Approval Notification */, sys_halt /* System Halt Notification */, prc /* Process Notification */, intr_ack /* Interrupt Acknowledge Notification */;
output reg alu_enable /* Arithmetic Logic Unit (ALU) Enable */;
output reg [rf_add_width-1:0] rf_add1 /* Register File (RF) Port I Address */, rf_add2 /* Register File (RF) Port II Address */;
output reg [4:0] alu_opcode /* Arithmetic Logic Unit (ALU) OPcode */;
output reg [15:0] state /* 16-bit State Register */;
// Internal
wire sys_mem_fault /* System Fault Flag */;
reg dma_appr_buf /* DMA Approval Notification Buffer */, hlt /* Halt Register */, intr_ack_buf /* Interrupt Acknowledge Notification Buffer */;
reg [5:0] stclk /* State Clock */;
reg [ins_width-1:0] ins_reg /* Instruction Register */;
// Fault Logic
assign sys_fault = rf_mem_fault || stack_mem_fault; // System Fault on Memory Fault
// Notification Translation Logic
assign dma_appr = dma_appr_buf; // DMA Approval Notification
assign sys_halt = hlt; // System Halt Notification
assign prc = |stclk; // Translate Process Notification Signal from State Clock.
assign intr_ack = intr_ack_buf; // Interrupt Acknowledge Notification
// State Logic
always@(posedge clk) begin
if(dma_req && rst) begin // DMA Mode
dma_appr_buf <= 1'b1;
intr_ack_buf <= 1'b0;
hlt <= 1'b0;
alu_enable <= 1'b1;
stclk [5:0] <= 6'b0;
// Direct Memory Access (DMA) Block
if(mar_incr) state [15:0] <= 16'b0001000000000000; // Increment Memory Address Register (MAR)
else begin
case(we_in) // synthesis parallel_case
3'b000: state [15:0] <= 16'b0; // No Write DMA Mode
3'b001: state [15:0] <= 16'b0000100000000000; // Write to Register File (RF)
3'b010: state [15:0] <= 16'b0; // No Write DMA Mode
3'b011: state [15:0] <= 16'b0000001000000000; // Write to Random Access Memory (RAM)
3'b100: state [15:0] <= 16'b1000000000000000; // Write to Program Counter (PC)
3'b101: state [15:0] <= 16'b0010000000000000; // Write to Memory Address Register (MAR)
3'b110: state [15:0] <= 16'b0; // No Write DMA Mode
3'b111: state [15:0] <= 16'b0; // No Write DMA Mode
default: state [15:0] <= 16'b0; // No Write DMA Mode
endcase
end
end else if(rst || dma_req) begin // Reset
dma_appr_buf <= 1'b0;
intr_ack_buf <= 1'b0;
hlt <= 1'b0;
alu_enable <= 1'b0;
stclk [5:0] <= 6'b0;
rf_add1 [rf_add_width-1:0] <= {rf_add_width{1'b0}};
rf_add2 [rf_add_width-1:0] <= {rf_add_width{1'b0}};
alu_opcode [4:0] <= 5'b0;
state [15:0] <= 16'b0;
end else if(sys_fault) begin // Fault Encounter Interrupt
dma_appr_buf <= 1'b0;
intr_ack_buf <= 1'b1;
hlt <= 1'b1;
stclk [5:0] <= 6'b0;
state [15:0] <= 16'b0;
end else if(sys_halt) begin // Halt
dma_appr_buf <= 1'b0;
intr_ack_buf <= 1'b0;
hlt <= 1'b1;
stclk [5:0] <= 6'b0;
state [15:0] <= 16'b0;
end else begin // Process
dma_appr_buf <= 1'b0;
intr_ack_buf <= 1'b0;
// Instruction Fetch Phase
if(stclk [5:0] == 6'b0) begin // T0
stclk [5:0] <= stclk [5:0] + 1'b1;
state [15:0] <= 16'b0000000000010000; // Select MAR Write Source Multiplexer to PC
end else if(stclk [5:0] == 6'b000001) begin // T1
stclk [5:0] <= stclk [5:0] + 1'b1;
state [15:0] <= 16'b0010000000010000; // Write to MAR
end else if(stclk [5:0] == 6'b000010) begin // T2
stclk [5:0] <= stclk [5:0] + 1'b1;
state [15:0] <= 16'b0100000000010000; // RAM Read Time, Increment PC
end else if(stclk [5:0] == 6'b000011) begin // T3
stclk [5:0] <= stclk [5:0] + 1'b1;
ins_reg [ins_width-1:0] <= ins_in [ins_width-1:0]; // Updates Instruction Register with value in the RAM Read Bus
state [15:0] <= 16'b0000000001101111; // Fetch Instruction, Set Multiplexers to optimal modes
end else begin
// Instruction Execute Phase
casez(ins_reg [ins_width-1:ins_width-4]) // synthesis parallel_case
4'b10??: begin // Arithmetic
case(stclk) // synthesis parallel_case
6'b000100: begin // T4
stclk [5:0] <= stclk [5:0] + 1'b1;
rf_add1 [rf_add_width-1:0] <= ins_reg [8:6];
rf_add2 [rf_add_width-1:0] <= ins_reg [5:3];
alu_opcode [4:0] <= ins_reg [13:9];
end
6'b000101: begin // T5
alu_enable <= 1'b1;
stclk [5:0] <= stclk [5:0] + 1'b1;
end
6'b001010: begin // T10
alu_enable <= 1'b0;
stclk [5:0] <= stclk [5:0] + 1'b1;
end
6'b001011: begin // T11
rf_add2 [rf_add_width-1:0] <= ins_reg [2:0];
stclk [5:0] <= stclk [5:0] + 1'b1;
end
6'b001100: begin // T12
stclk [5:0] <= 6'b0;
state [15:0] <= 16'b0000010001101111; // Write to RFPII
end
default: begin
stclk [5:0] <= stclk [5:0] + 1'b1;
end
endcase
end
4'b0110: begin // No Operation
stclk [5:0] <= 6'b0;
state [15:0] <= 16'b0000000001101111;
end
4'b0111: begin // Halt
stclk [5:0] <= 6'b0;
hlt <= 1'b1;
state [15:0] <= 16'b0;
end
default: begin // No Operation
stclk [5:0] <= 6'b0;
state [15:0] <= 16'b0000000001101111;
end
endcase
end
end
end
endmodule |
module NIOSCar(
//////////// CLOCK //////////
CLOCK_50,
//////////// LED //////////
LED,
//////////// KEY //////////
KEY,
//////////// SW //////////
SW,
//////////// SDRAM //////////
DRAM_ADDR,
DRAM_BA,
DRAM_CAS_N,
DRAM_CKE,
DRAM_CLK,
DRAM_CS_N,
DRAM_DQ,
DRAM_DQM,
DRAM_RAS_N,
DRAM_WE_N,
//////////// ADC //////////
ADC_CS_N,
ADC_SADDR,
ADC_SCLK,
ADC_SDAT,
//////////// U0 //////////
U0_F,
U0_T,
//////////// U1 //////////
U1_F,
U1_T,
//////////// U2 //////////
U2_F,
U2_T,
//////////// U3 //////////
U3_F,
U3_T,
//////////// U4 //////////
U4_F,
U4_T,
//////////// U5 //////////
U5_F,
U5_T,
//////////// pwm0 //////////
PWM0Ch0,
PWM0Ch1,
//////////// pwm1 //////////
PWM1Ch0,
PWM1Ch1,
//////////// pwm2 //////////
PWM2Ch0,
PWM2Ch1,
//////////// pwm3 //////////
PWM3Ch0,
PWM3Ch1,
//////////// INPUT//////////
PIO1,
//////////// endcoder0 //////////
Encoder0,
//////////// endcoder1 //////////
Encoder1,
//////////// PIO //////////
GPIO_0,
//////////// uart //////////
// 115200, data bit:8, stop bit: 1, Parity: none
tx_out,
rx_in
);
//=======================================================
// PARAMETER declarations
//=======================================================
//=======================================================
// PORT declarations
//=======================================================
//////////// CLOCK //////////
input CLOCK_50;
//////////// LED //////////
output [7:0] LED;
//////////// KEY //////////
input [1:0] KEY;
//////////// PIO1 //////////
input [3:0] PIO1;
//////////// SW //////////
input [3:0] SW;
//////////// SDRAM //////////
output [12:0] DRAM_ADDR;
output [1:0] DRAM_BA;
output DRAM_CAS_N;
output DRAM_CKE;
output DRAM_CLK;
output DRAM_CS_N;
inout [15:0] DRAM_DQ;
output [1:0] DRAM_DQM;
output DRAM_RAS_N;
output DRAM_WE_N;
////////////// EPCS //////////
//output EPCS_ASDO;
//input EPCS_DATA0;
//output EPCS_DCLK;
//output EPCS_NCSO;
////////////// Accelerometer and EEPROM //////////
//output G_SENSOR_CS_N;
//input G_SENSOR_INT;
//output I2C_SCLK;
//inout I2C_SDAT;
//////////// ADC //////////
output ADC_CS_N;
output ADC_SADDR;
output ADC_SCLK;
input ADC_SDAT;
//////////// U0 //////////
input U0_F;
output U0_T;
//////////// U1 //////////
input U1_F;
output U1_T;
//////////// U2 //////////
input U2_F;
output U2_T;
//////////// U3 //////////
input U3_F;
output U3_T;
//////////// U4 //////////
input U4_F;
output U4_T;
//////////// U5 //////////
input U5_F;
output U5_T;
//////////// pwm0 //////////
output PWM0Ch0;
output PWM0Ch1;
//////////// pwm1 //////////
output PWM1Ch0;
output PWM1Ch1;
//////////// pwm2 //////////
output PWM2Ch0;
output PWM2Ch1;
//////////// pwm3 //////////
output PWM3Ch0;
output PWM3Ch1;
//////////// endcoder0 //////////
input [1:0] Encoder0;
//////////// endcoder1 //////////
input [1:0] Encoder1;
//////////// endcoder1 //////////
output [7:0] GPIO_0;
//////////// uart //////////
// 115200, data bit:8, stop bit: 1, Parity: none
output tx_out;
input rx_in;
////////////// 2x13 GPIO Header //////////
//inout [12:0] GPIO_2;
//input [2:0] GPIO_2_IN;
//
////////////// GPIO_0, GPIO_0 connect to GPIO Default //////////
//inout [33:0] GPIO_0;
//input [1:0] GPIO_0_IN;
//
////////////// GPIO_1, GPIO_1 connect to GPIO Default //////////
//inout [33:0] GPIO_1;
//input [1:0] GPIO_1_IN;
////=======================================================
//// REG/WIRE declarations
////=======================================================
//wire reset_n;
//wire select_i2c_clk;
//wire i2c_clk;
//wire spi_clk;
//=======================================================
// Structural coding
//=======================================================
assign reset_n = 1'b1;
NIOS_Sys u0(
.led_external_connection_export (LED), // led_external_connection.export
.sdram_wire_addr (DRAM_ADDR), // sdram_wire.addr
.sdram_wire_ba (DRAM_BA), // .ba
.sdram_wire_cas_n (DRAM_CAS_N), // .cas_n
.sdram_wire_cke (DRAM_CKE), // .cke
.sdram_wire_cs_n (DRAM_CS_N), // .cs_n
.sdram_wire_dq (DRAM_DQ), // .dq
.sdram_wire_dqm (DRAM_DQM), // .dqm
.sdram_wire_ras_n (DRAM_RAS_N), // .ras_n
.sdram_wire_we_n (DRAM_WE_N), // .we_n
.key_external_connection_export (KEY), // key_external_connection.export
.sw_external_connection_export (SW), // sw_external_connection.export
.reset_reset_n (reset_n), // reset.reset_n
.altpll_0_c1_clk (DRAM_CLK), // altpll_0_c1.clk
.clk_clk (CLOCK_50),
.ultrasound0_conduit_end_feedback_in (U0_F), // ultrasound0_conduit_end.feedback_in
.ultrasound0_conduit_end_trigger_out (U0_T), // .trigger_out
.ultrasound1_conduit_end_feedback_in (U1_F), // ultrasound1_conduit_end.feedback_in
.ultrasound1_conduit_end_trigger_out (U1_T), // .trigger_out
.adc_spi_read_conduit_end_OUT (ADC_SADDR), // adc_spi_read_conduit_end.OUT
.adc_spi_read_conduit_end_IN (ADC_SDAT), // .IN
.adc_spi_read_conduit_end_CS_n (ADC_CS_N), // .CS_n
.adc_spi_read_conduit_end_CLK (ADC_SCLK), // .CLK
.pwm0_conduit_end_pwm1 (PWM0Ch0), // pwm0_conduit_end.pwm1
.pwm0_conduit_end_pwm2 (PWM0Ch1), // .pwm2
.pwm1_conduit_end_pwm1 (PWM1Ch0), // pwm1_conduit_end.pwm1
.pwm1_conduit_end_pwm2 (PWM1Ch1), // .pwm2
.encoder0_conduit_end_export (Encoder0), // encoder0_conduit_end.export
.encoder1_conduit_end_export (Encoder1), // encoder1_conduit_end.export
.pio_0_external_connection_export (GPIO_0), // pio_0_external_connection.export
.uart_0_external_connection_rxd (rx_in), // uart_0_external_connection.rxd
.uart_0_external_connection_txd (tx_out), // .txd
.ultrasound2_conduit_end_feedback_in (U2_F), // ultrasound2_conduit_end.feedback_in
.ultrasound2_conduit_end_trigger_out (U2_T), // .trigger_out
.ultrasound3_conduit_end_feedback_in (U3_F), // ultrasound3_conduit_end.feedback_in
.ultrasound3_conduit_end_trigger_out (U3_T), // .trigger_out
.ultrasound5_conduit_end_feedback_in (U5_F), // ultrasound5_conduit_end.feedback_in
.ultrasound5_conduit_end_trigger_out (U5_T), // .trigger_out
.pwm2_conduit_end_pwm1 (PWM2Ch0), // pwm2_conduit_end.pwm1
.pwm2_conduit_end_pwm2 (PWM2Ch1), // .pwm2
.pwm3_conduit_end_pwm1 (PWM3Ch0), // pwm3_conduit_end.pwm1
.pwm3_conduit_end_pwm2 (PWM3Ch1), // .pwm2
.ultrasound4_conduit_end_feedback_in (U4_F), // ultrasound4_conduit_end.feedback_in
.ultrasound4_conduit_end_trigger_out (U4_T), //
.pio_1_external_connection_export(PIO1)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 51; vector<int> g[N]; int n, sz[N], dp[N][N][N][N], s, m, ans = 1e9, cost[N][N], temp[N]; void dfs(int u, int p) { for (auto i : g[u]) if (i != p) dfs(i, u), sz[u] += sz[i]; } int calc(int from, int to, int behind, int front) { if (!front) return 1e9; if (g[to].size() == 1) return behind ? calc(to, from, 0, behind) + cost[to][from] : cost[to][from]; int &ref = dp[to][from][behind][front], id = 0, x; if (ref != -1) return ref; for (auto i : g[to]) if (i != from) for (int j = 1; j <= front; j++) calc(to, i, behind + front - j, j); for (int i = 1; i <= front; i++) temp[i] = -1e9; for (auto x : g[to]) { if (x == from) continue; for (int i = front; i; i--) for (int j = 1; i - j >= 0; j++) temp[i] = max(temp[i], min(temp[i - j], calc(to, x, behind + front - j, j))); } return ref = temp[front] + cost[from][to]; } int main() { scanf( %d , &n); memset(dp, -1, sizeof dp); for (int i = 1, a, b, c; i < n; i++) { scanf( %d%d%d , &a, &b, &c); g[--a].push_back(--b); g[b].push_back(a); cost[a][b] = cost[b][a] = c; } temp[0] = 1e9; scanf( %d%d , &s, &m); for (int i = 0, a; i < m; i++) { scanf( %d , &a); sz[a - 1]++; } dfs(--s, -1); for (auto i : g[s]) ans = min(ans, calc(s, i, m - sz[i], sz[i])); printf( %d n , ans); } |
#include <bits/stdc++.h> using namespace std; const int N = 103, M = 998244353; const int mod = M - 1; struct matrix { int row, col; int a[N][N]; matrix() { memset(a, 0, sizeof a); } matrix(int r, int c) : row(r), col(c) { memset(a, 0, sizeof a); } matrix operator*(const matrix &p) { assert(col == p.row); matrix ret(row, p.col); long long mod2 = (long long)mod * mod; for (int i = 0; i < ret.row; ++i) { for (int j = 0; j < ret.col; ++j) { long long sum = 0; for (int k = 0; k < col; ++k) { sum += (1LL * a[i][k] * p.a[k][j]); if (sum >= mod2) sum -= mod2; } ret.a[i][j] = sum % mod; } } return ret; } matrix power(int p) { assert(row == col); matrix base = *this; matrix ret(row, col); for (int i = 0; i < row; ++i) ret.a[i][i] = 1; while (p > 0) { if (p & 1) ret = ret * base; base = base * base; p >>= 1; } return ret; } }; inline int gcd(int a, int b) { return a ? gcd(b % a, a) : b; } int powMod(int a, int b, int p) { int res = 1; while (b) { if (b & 1) res = (res * 1LL * a % p), --b; else a = (a * 1LL * a % p), b >>= 1; } return res; } int primitive_root(int p) { vector<int> fact; int phi = p - 1, n = phi; for (int i = 2; i * i <= n; ++i) { if (n % i == 0) { fact.push_back(i); while (n % i == 0) n /= i; } } if (n > 1) fact.push_back(n); for (int res = 2; res <= p; ++res) { bool ok = true; for (int factor : fact) { if (powMod(res, phi / factor, p) == 1) { ok = false; break; } } if (ok) return res; } return -1; } int discrete_log(int a, int b, int m) { long long n = (int)sqrt(m + .0) + 1; map<int, int> Hash; for (int i = n; i >= 1; i--) Hash[powMod(a, i * n, m)] = i; for (int i = 0; i <= n; i++) { int cur = (powMod(a, i, m) * b) % m; if (Hash.count(cur)) { int ans = Hash[cur] * n - i; if (ans < m) return ans; } } return -1; } vector<int> discrete_root(int n, int k, int a) { if (a == 0) return vector<int>(1, 0); int g = primitive_root(n); int sq = (int)sqrt(n + .0) + 1; vector<pair<int, int> > dec(sq); for (int i = 1; i <= sq; ++i) dec[i - 1] = make_pair(powMod(g, int(i * sq * 1LL * k % (n - 1)), n), i); sort(dec.begin(), dec.end()); int any_ans = -1; for (int i = 0; i < sq; ++i) { int my = int(powMod(g, int(i * 1LL * k % (n - 1)), n) * 1LL * a % n); vector<pair<int, int> >::iterator it = lower_bound(dec.begin(), dec.end(), make_pair(my, 0)); if (it != dec.end() && it->first == my) { any_ans = it->second * sq - i; break; } } if (any_ans == -1) return vector<int>(); int delta = (n - 1) / gcd(k, n - 1); vector<int> ans; for (int cur = any_ans % delta; cur < n - 1; cur += delta) { ans.push_back(powMod(g, cur, n)); break; } sort(ans.begin(), ans.end()); return ans; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n; cin >> n; matrix ank(n, n); for (int i = 0; i < n; i++) cin >> ank.a[0][i]; for (int j = 1; j < n; j++) ank.a[j][j - 1] = 1; int k, x; cin >> k >> x; ank = ank.power(k - n); int pw = ank.a[0][0]; auto res = discrete_root(M, pw, x); if (res.empty()) res.push_back(-1); cout << res.front() << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 5e3 + 5; const int mod = 998244353; inline long long fpm(long long a, long long p) { long long r = 1; while (p) { if (p & 1) r = r * a % mod; a = a * a % mod; p /= 2; } return r; } int k, n, m; int s[maxn][maxn]; inline void init() { s[0][0] = 1; for (int i = 1; i <= k; i++) { for (int j = 1; j <= i; j++) { s[i][j] = (s[i - 1][j - 1] + 1ll * j * s[i - 1][j] % mod) % mod; } } } int main() { cin >> n >> m >> k; init(); long long ans = 0, cur = 1; long long invm = fpm(m, mod - 2); for (int i = 0; i <= k; i++) { ans = (ans + 1ll * cur * s[k][i] % mod * fpm(invm, i) % mod) % mod; cur = 1ll * cur * (n - i) % mod; } cout << ans << endl; } |
`timescale 1ns/1ps
module SensorFSM #(
parameter DataWidth = 8
) (
input Reset_n_i,
input Clk_i,
// top level
input Enable_i,
output reg CpuIntr_o,
output [2*DataWidth-1:0] SensorValue_o,
// to/from Measure-FSM
output reg MeasureFSM_Start_o,
input MeasureFSM_Done_i,
input [DataWidth-1:0] MeasureFSM_Byte0_i,
input [DataWidth-1:0] MeasureFSM_Byte1_i,
// parameters
input [2*DataWidth-1:0] ParamThreshold_i,
input [4*DataWidth-1:0] ParamCounterPreset_i
);
// Sensor FSM
localparam stDisabled = 2'b00;
localparam stIdle = 2'b01;
localparam stXfer = 2'b10;
localparam stNotify = 2'b11;
reg [1:0] SensorFSM_State;
reg [1:0] SensorFSM_NextState;
wire SensorFSM_TimerOvfl;
reg SensorFSM_TimerPreset;
reg SensorFSM_TimerEnable;
wire SensorFSM_DiffTooLarge;
reg SensorFSM_StoreNewValue;
/////////////////////////////////////////////////////////////////////////////
// Word Arithmetic
// interconnecting signals
wire [2*DataWidth-1:0] SensorValue;
reg [2*DataWidth-1:0] Word0;
wire [2*DataWidth-1:0] AbsDiffResult;
/////////////////////////////////////////////////////////////////////////////
// FSM //////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
SensorFSM_State <= stDisabled;
end
else
begin
SensorFSM_State <= SensorFSM_NextState;
end
end
always @(SensorFSM_State, Enable_i, SensorFSM_TimerOvfl, MeasureFSM_Done_i, SensorFSM_DiffTooLarge)
begin // process SensorFSM_CombProc
SensorFSM_NextState = SensorFSM_State;
// control signal default values
SensorFSM_TimerPreset = 1'b1;
SensorFSM_TimerEnable = 1'b0;
MeasureFSM_Start_o = 1'b0;
SensorFSM_StoreNewValue = 1'b0;
CpuIntr_o = 1'b0;
// next state and output logic
case (SensorFSM_State)
stDisabled: begin
if (Enable_i == 1'b1)
begin
SensorFSM_NextState = stIdle;
SensorFSM_TimerPreset = 1'b0;
SensorFSM_TimerEnable = 1'b1; // start timer
end
end
stIdle: begin
SensorFSM_TimerPreset = 1'b0;
SensorFSM_TimerEnable = 1'b1; // timer running
if (Enable_i == 1'b0)
begin
SensorFSM_NextState = stDisabled;
end
else
if (SensorFSM_TimerOvfl == 1'b1)
begin
SensorFSM_NextState = stXfer;
MeasureFSM_Start_o = 1'b1;
end
end
stXfer: begin
if (MeasureFSM_Done_i == 1'b1)
begin
if (SensorFSM_DiffTooLarge == 1'b1)
begin
SensorFSM_NextState = stNotify;
SensorFSM_TimerPreset = 1'b0;
SensorFSM_TimerEnable = 1'b1; // timer running
SensorFSM_StoreNewValue = 1'b1; // store new value
end
else
begin
SensorFSM_NextState = stIdle;
end
end
end
stNotify: begin
SensorFSM_TimerPreset = 1'b1;
SensorFSM_TimerEnable = 1'b0; // preset timer
SensorFSM_NextState = stIdle;
CpuIntr_o = 1'b1; // notify CPU
end
default: begin
end
endcase
end
/////////////////////////////////////////////////////////////////////////////
// Word Arithmetic //////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
reg [4*DataWidth-1:0] SensorFSM_Timer;
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
SensorFSM_Timer <= 32'd0;
end
else
begin
if (SensorFSM_TimerPreset)
begin
SensorFSM_Timer <= ParamCounterPreset_i;
end
else if (SensorFSM_TimerEnable)
begin
SensorFSM_Timer <= SensorFSM_Timer - 1'b1;
end
end
end
assign SensorFSM_TimerOvfl = (SensorFSM_Timer == 0) ? 1'b1 : 1'b0;
assign SensorValue = {MeasureFSM_Byte1_i, MeasureFSM_Byte0_i};
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
Word0 <= 16'd0;
end
else
begin
if (SensorFSM_StoreNewValue)
begin
Word0 <= SensorValue;
end
end
end
wire [2*DataWidth : 0] DiffAB;
wire [2*DataWidth-1 : 0] DiffBA;
assign DiffAB = {1'b0, SensorValue} - {1'b0, Word0};
assign DiffBA = Word0 - SensorValue;
assign AbsDiffResult = DiffAB[2*DataWidth] ? DiffBA : DiffAB[2*DataWidth-1 : 0];
assign SensorFSM_DiffTooLarge = (AbsDiffResult > ParamThreshold_i) ? 1'b1 : 1'b0;
assign SensorValue_o = Word0;
endmodule // SensorFSM
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
module weight(CLK ,RST,ED,START, DReal,DImag, DOReal, DOImag,RDY );
parameter total_bits = 32;
input CLK;
input RST;
input ED;
input START;
output reg RDY;
input [total_bits-1:0] DReal;
input [total_bits-1:0] DImag;
output [total_bits-1:0] DOReal;
output [total_bits-1:0] DOImag;
reg [4:0] ADDR;
reg [1:0] state;
/////////////////////////////////////////////////////////////////////////////////// Data change according to use
reg signed [31:0] re[0:15];
reg signed [31:0] im[0:15];
initial begin
re[0] = 32'h00010000;re[1] = 32'h0000FB15;re[2] = 32'h0000EC83;re[3] = 32'h0000D4DB;
re[4] = 32'h0000B505;re[5] = 32'h00008E3A;re[6] = 32'h000061F8;re[7] = 32'h000031F1;
re[8] = 32'h00000000;re[9] = 32'hFFFFCE0F;re[10] = 32'hFFFF9E08;re[11] = 32'hFFFF71C6;
re[12] = 32'hFFFF4AFB;re[13] = 32'hFFFF2B25;re[14] = 32'hFFFF137D;re[15] = 32'hFFFF04EB;
im[0] = 32'h00000000;im[1] = 32'hFFFFCE0F;im[2] = 32'hFFFF9E08;im[3] = 32'hFFFF71C6;
im[4] = 32'hFFFF4AFB;im[5] = 32'hFFFF2B25;im[6] = 32'hFFFF137D;im[7] = 32'hFFFF04EB;
im[8] = 32'hFFFF0000;im[9] = 32'hFFFF04EB;im[10] = 32'hFFFF137D;im[11] = 32'hFFFF2B25;
im[12] = 32'hFFFF4AFB;im[13] = 32'hFFFF71C6;im[14] = 32'hFFFF9E08;im[15] = 32'hFFFFCE0F;
end
/////////////////////////////////////////////////////////////////////////////////////////
always @(posedge CLK)
begin
if(RST) begin
ADDR<=18;
state<=0;
RDY<=0;
end
else if(START) begin
if(state==0)
state<=1;
else if(state==1) begin
state<=2;
ADDR<=0;
end
else if(state==2)
state<=1;
RDY<=0;
end
else if(ED) begin
RDY<=0;
if(state==2)
if(ADDR!=18)
ADDR<=ADDR+1;
end
if(ADDR==1)
RDY<=1;
end
reg signed [total_bits-1 : 0] drd,did;
reg signed [total_bits-1 : 0] wrd,wid;
wire signed [2*total_bits-1 : 0] drri,drii,diri,diii;
reg signed [total_bits:0] drr,dri,dir,dii,dwr,dwi;
assign drri=drd*wrd;
assign diri=did*wrd;
assign drii=drd*wid;
assign diii=did*wid;
//wire OVF; //Change for different width
//assign sel = drri[63] ^ dwr[62] ^ dwr[61] ^ drri[63] ^ dwr[62] ^ dwr[61]
always @(posedge CLK) begin
if((state==2&&ED)&&(ADDR!=18)) begin
drd<=DReal;
did<=DImag;
wrd<=re[ADDR];
wid<=im[ADDR];
drr<=drri[47:15]; //Change according to use
dri<=drii[47:15];
dir<=diri[47:15];
dii<=diii[47:15];
dwr<=drr - dii;
dwi<=dri + dir;
end
end
assign DOReal = dwr[total_bits:1];
assign DOImag = dwi[total_bits:1];
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int x1, y1, x2, y2; cin >> x1 >> y1 >> x2 >> y2; int a = abs(x1 - x2); int b = abs(y1 - y2); int u = min(a, b); cout << u + abs(a - b); return 0; } |
///////////////////////////////////////////////////////////////////////////////
// Title : alt_mem_ddrx_mm_st_converter
//
// File : alt_mem_ddrx_mm_st_converter.v
//
// Abstract : take in Avalon MM interface and convert it to single cmd and
// multiple data Avalon ST
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module alt_mem_ddrx_mm_st_converter # (
parameter
AVL_SIZE_WIDTH = 3,
AVL_ADDR_WIDTH = 25,
AVL_DATA_WIDTH = 32,
LOCAL_ID_WIDTH = 8,
CFG_DWIDTH_RATIO = 4,
CFG_MM_ST_CONV_REG = 0
)
(
ctl_clk, // controller clock
ctl_reset_n, // controller reset_n, synchronous to ctl_clk
ctl_half_clk, // controller clock, half-rate
ctl_half_clk_reset_n, // controller reset_n, synchronous to ctl_half_clk
// Avalon data slave interface
avl_ready, // Avalon wait_n
avl_read_req, // Avalon read
avl_write_req, // Avalon write
avl_size, // Avalon burstcount
avl_burstbegin, // Avalon burstbegin
avl_addr, // Avalon address
avl_rdata_valid, // Avalon readdata_valid
avl_rdata, // Avalon readdata
avl_wdata, // Avalon writedata
avl_be, // Avalon byteenble
local_rdata_error, // Avalon readdata_error
local_multicast, // In-band multicast
local_autopch_req, // In-band auto-precharge request signal
local_priority, // In-band priority signal
// cmd channel
itf_cmd_ready,
itf_cmd_valid,
itf_cmd,
itf_cmd_address,
itf_cmd_burstlen,
itf_cmd_id,
itf_cmd_priority,
itf_cmd_autopercharge,
itf_cmd_multicast,
// write data channel
itf_wr_data_ready,
itf_wr_data_valid,
itf_wr_data,
itf_wr_data_byte_en,
itf_wr_data_begin,
itf_wr_data_last,
itf_wr_data_id,
// read data channel
itf_rd_data_ready,
itf_rd_data_valid,
itf_rd_data,
itf_rd_data_error,
itf_rd_data_begin,
itf_rd_data_last,
itf_rd_data_id
);
localparam AVL_BE_WIDTH = AVL_DATA_WIDTH / 8;
input ctl_clk;
input ctl_reset_n;
input ctl_half_clk;
input ctl_half_clk_reset_n;
output avl_ready;
input avl_read_req;
input avl_write_req;
input [AVL_SIZE_WIDTH-1:0] avl_size;
input avl_burstbegin;
input [AVL_ADDR_WIDTH-1:0] avl_addr;
output avl_rdata_valid;
output [3:0] local_rdata_error;
output [AVL_DATA_WIDTH-1:0] avl_rdata;
input [AVL_DATA_WIDTH-1:0] avl_wdata;
input [AVL_BE_WIDTH-1:0] avl_be;
input local_multicast;
input local_autopch_req;
input local_priority;
input itf_cmd_ready;
output itf_cmd_valid;
output itf_cmd;
output [AVL_ADDR_WIDTH-1:0] itf_cmd_address;
output [AVL_SIZE_WIDTH-1:0] itf_cmd_burstlen;
output [LOCAL_ID_WIDTH-1:0] itf_cmd_id;
output itf_cmd_priority;
output itf_cmd_autopercharge;
output itf_cmd_multicast;
input itf_wr_data_ready;
output itf_wr_data_valid;
output [AVL_DATA_WIDTH-1:0] itf_wr_data;
output [AVL_BE_WIDTH-1:0] itf_wr_data_byte_en;
output itf_wr_data_begin;
output itf_wr_data_last;
output [LOCAL_ID_WIDTH-1:0] itf_wr_data_id;
output itf_rd_data_ready;
input itf_rd_data_valid;
input [AVL_DATA_WIDTH-1:0] itf_rd_data;
input itf_rd_data_error;
input itf_rd_data_begin;
input itf_rd_data_last;
input [LOCAL_ID_WIDTH-1:0] itf_rd_data_id;
reg [AVL_SIZE_WIDTH-1:0] burst_count;
wire int_ready;
wire itf_cmd; // high is write
wire itf_wr_if_ready;
wire [LOCAL_ID_WIDTH-1:0] itf_cmd_id;
wire itf_wr_data_begin;
wire itf_wr_data_last;
wire [LOCAL_ID_WIDTH-1:0] itf_wr_data_id;
reg data_pass;
reg [AVL_SIZE_WIDTH-1:0] burst_counter;
reg avl_read_req_reg;
reg avl_write_req_reg;
reg [AVL_SIZE_WIDTH-1:0] avl_size_reg;
reg [AVL_ADDR_WIDTH-1:0] avl_addr_reg;
reg [AVL_DATA_WIDTH-1:0] avl_wdata_reg;
reg [AVL_DATA_WIDTH/8-1:0] avl_be_reg;
reg itf_rd_data_valid_reg;
reg [AVL_DATA_WIDTH-1:0] itf_rd_data_reg;
reg [3:0] itf_rd_data_error_reg;
reg local_multicast_reg;
reg local_autopch_req_reg;
reg local_priority_reg;
generate
if (CFG_MM_ST_CONV_REG == 1)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
avl_read_req_reg <= 1'b0;
avl_write_req_reg <= 1'b0;
avl_size_reg <= {AVL_SIZE_WIDTH{1'b0}};
avl_addr_reg <= {AVL_ADDR_WIDTH{1'b0}};
avl_wdata_reg <= {AVL_DATA_WIDTH{1'b0}};
avl_be_reg <= {AVL_BE_WIDTH{1'b0}};
itf_rd_data_valid_reg <= 1'b0;
itf_rd_data_reg <= {AVL_DATA_WIDTH{1'b0}};
itf_rd_data_error_reg <= 4'b0;
local_multicast_reg <= 1'b0;
local_autopch_req_reg <= 1'b0;
local_priority_reg <= 1'b0;
end else
begin
if (int_ready)
begin
avl_read_req_reg <= avl_read_req;
avl_write_req_reg <= avl_write_req;
avl_size_reg <= avl_size;
avl_addr_reg <= avl_addr;
avl_wdata_reg <= avl_wdata;
avl_be_reg <= avl_be;
local_multicast_reg <= local_multicast;
local_autopch_req_reg <= local_autopch_req;
local_priority_reg <= local_priority;
end
itf_rd_data_valid_reg <= itf_rd_data_valid;
itf_rd_data_reg <= itf_rd_data;
itf_rd_data_error_reg <= itf_rd_data_error;
end
end
end else
begin
always @ (*)
begin
avl_read_req_reg = avl_read_req;
avl_write_req_reg = avl_write_req;
avl_size_reg = avl_size;
avl_addr_reg = avl_addr;
avl_wdata_reg = avl_wdata;
avl_be_reg = avl_be;
itf_rd_data_valid_reg = itf_rd_data_valid;
itf_rd_data_reg = itf_rd_data;
itf_rd_data_error_reg = {4{itf_rd_data_error}};
local_multicast_reg = local_multicast;
local_autopch_req_reg = local_autopch_req;
local_priority_reg = local_priority;
end
end
endgenerate
// when cmd_ready = 1'b1, avl_ready = 1'b1;
// when avl_write_req = 1'b1,
// take this write req and then then drive avl_ready until receive # of beats = avl_size?
// we will look at cmd_ready, if cmd_ready = 1'b0, avl_ready = 1'b0
// when cmd_ready = 1'b1, avl_ready = 1'b1;
// when local_ready_req = 1'b1,
// take this read_req
// we will look at cmd_ready, if cmd_ready = 1'b0, avl_ready = 1'b0
assign itf_cmd_valid = avl_read_req_reg | itf_wr_if_ready;
assign itf_wr_if_ready = itf_wr_data_ready & avl_write_req_reg & ~data_pass;
assign avl_ready = int_ready;
assign itf_rd_data_ready = 1'b1;
assign itf_cmd_address = avl_addr_reg ;
assign itf_cmd_burstlen = avl_size_reg ;
assign itf_cmd_autopercharge = local_autopch_req_reg ;
assign itf_cmd_priority = local_priority_reg ;
assign itf_cmd_multicast = local_multicast_reg ;
assign itf_cmd = avl_write_req_reg;
assign itf_cmd_id = {LOCAL_ID_WIDTH{1'b0}};
assign itf_wr_data_begin = 1'b0;
assign itf_wr_data_last = 1'b0;
assign itf_wr_data_id = {LOCAL_ID_WIDTH{1'b0}};
// write data channel
assign itf_wr_data_valid = (data_pass) ? avl_write_req_reg : itf_cmd_ready & avl_write_req_reg;
assign itf_wr_data = avl_wdata_reg ;
assign itf_wr_data_byte_en = avl_be_reg ;
// read data channel
assign avl_rdata_valid = itf_rd_data_valid_reg;
assign avl_rdata = itf_rd_data_reg;
assign local_rdata_error = itf_rd_data_error_reg;
assign int_ready = (data_pass) ? itf_wr_data_ready : ((itf_cmd) ? (itf_wr_data_ready & itf_cmd_ready) : itf_cmd_ready);
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
burst_counter <= {AVL_SIZE_WIDTH{1'b0}};
else
begin
if (itf_wr_if_ready && avl_size_reg > 1 && itf_cmd_ready)
burst_counter <= avl_size_reg - 1'b1;
else if (avl_write_req_reg && itf_wr_data_ready)
burst_counter <= burst_counter - 1'b1;
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
data_pass <= 1'b0;
else
begin
if (itf_wr_if_ready && avl_size_reg > 1 && itf_cmd_ready)
data_pass <= 1'b1;
else if (burst_counter == 1 && avl_write_req_reg && itf_wr_data_ready)
data_pass <= 1'b0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, k, a[((int)1001 * 1000)], maxi, mini; vector<int> v; int jaghool; bitset<((int)1001 * 1000)> dp, mark; int main() { scanf( %d%d , &n, &k); int k2 = k; for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int i = 1; i <= n; i++) if (!mark[i]) { int x = a[i], p = 1; while (x != i) p++, mark[x] = 1, x = a[x]; v.push_back(p); maxi += min(k2, p / 2) * 2, k2 -= min(k2, p / 2); if (p % 2) jaghool++; } maxi += min(k2, jaghool); dp[0] = 1; sort(v.begin(), v.end()); v.push_back(-1); vector<int> v2; for (int i = 0, cnt = 1; i < v.size(); i++) { if (v[i] != v[i + 1]) { int x = v[i]; while (cnt) { dp |= (dp << v[i]); for (int j = 0; j < ((int)20); j++) { if ((1 << j) <= cnt && cnt < (1 << (j + 1))) { cnt -= (1 << j); break; } dp |= (dp << (v[i] << j)); } } cnt = 1; } else cnt++; } cout << k + 1 - dp[k] << << maxi << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int ans; int visited[1001]; int cc = 0; vector<int> arr[1001]; void dfs(int node) { visited[node]++; if (visited[node] == 2) { ans = node; return; } for (auto child : arr[node]) { if (visited[node] < 2) dfs(child); } } int main() { int n, v, a, b; cin >> n; for (int i = 1; i <= n; i++) { cin >> a; arr[i].push_back(a); } for (int i = 1; i <= n; i++) { memset(visited, 0, sizeof(visited)); dfs(i); cout << ans << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; map<string, int> mp; int n, m; int a[110], b[110]; int main() { while (~scanf( %d%d , &n, &m)) { mp.clear(); for (int i = 0; i < (n); ++i) scanf( %d , a + i); for (int i = 0; i < (m); ++i) { string s; cin >> s; mp[s]++; } int tot = 0; for (map<string, int>::iterator it = mp.begin(); it != mp.end(); ++it) b[tot++] = it->second; sort(a, a + n); sort(b, b + tot); int mint = 0, maxt = 0; for (int i = 0; i < (tot); ++i) mint += a[i] * b[tot - 1 - i], maxt += a[n - tot + i] * b[i]; printf( %d %d n , mint, maxt); } return 0; } |
/*******************************************************************************
* *
* Copyright (C) 2009 Altera Corporation *
* *
* Altera products are protected under numerous U.S. and foreign patents, *
* maskwork rights, copyrights and other intellectual property laws. *
* *
* This reference design file, and your use thereof, is subject to and *
* governed by the terms and conditions of the applicable Altera Reference *
* Design License Agreement (either as signed by you, agreed by you upon *
* download or as a "click-through" agreement upon installation andor found *
* at www.altera.com). By using this reference design file, you indicate your *
* acceptance of such terms and conditions between you and Altera Corporation. *
* In the event that you do not agree with such terms and conditions, you may *
* not use the reference design file and please promptly destroy any copies *
* you have made. *
* *
* This reference design file is being provided on an "as-is" basis and as an *
* accommodation and therefore all warranties, representations or guarantees *
* of any kind (whether express, implied or statutory) including, without *
* limitation, warranties of merchantability, non-infringement, or fitness for *
* a particular purpose, are specifically disclaimed. By making this refer- *
* ence design file available, Altera expressly does not recommend, suggest *
* or require that this reference design file be used in combination with any *
* other product not provided by Altera. *
* *
* Module Name: multi_bit_check File Name: multi_bit_check.v *
* *
* Module Function: This module checks to see if more than one bit is set in *
* an input bus. *
* *
* Modules Used: *
* *
* Parameters and Defines Used: *
* - N : Power for number of bits of input data *
* - WIDTH : Width of input data *
* *
* Created by: Jim Schwalbe Created on: 08/06/2009 *
* *
* REVISION HISTORY: *
* * Revision 1.0 08/06/2009 Jim Schwalbe *
* - Initial Revision *
* *
******************************************************************************/
module multi_bit_check (
data_in,
multi_bit
);
parameter WIDTH = 64;
parameter N = log2(WIDTH);
input [WIDTH-1:0] data_in;
output multi_bit;
reg [N-1:0] sum;
reg multi_bit;
integer j;
always @(*)
begin
multi_bit = 0;
sum = 0;
for (j=WIDTH-1; j >= 0; j = j-1)
sum = sum + data_in[j];
if (sum > 1)
multi_bit = 1;
end
function integer log2;
input [32:0] depth;
integer i;
begin
log2 = 1;
for (i=0; 2**i < depth; i=i+1)
log2 = i + 1;
end
endfunction // log2
endmodule // multi_bit_check
|
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1.0); const unsigned long long MAX = LONG_MAX; void fasterIO() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); } int sumDig(int a) { int sum = 0; while (a != 0) { sum += a % 10; a /= 10; } return sum; } int main() { int test; cin >> test; while (test--) { long long p, k; long long arr[150]; cin >> p >> k; for (unsigned long long i = 0; i < (p); i++) cin >> arr[i]; sort(arr, arr + p); if (abs((arr[0] + k) - arr[p - 1]) > k) cout << -1 << endl; else cout << arr[0] + k << endl; } return 0; } |
/*
Este modulo esta encargado de ejecutar las operaciones principales que cada instruccion debe realizar
ademas es el que envia los datos y la direccion a la memoria de datos para ser almacenados.
*/
module ALU(
input wire[15:0] wInstruction,
input wire[7:0] iA,
input wire [7:0] iB,
output reg oRamEnableWrite,
output wire[7:0] oData,
output reg oWriteA,
output reg oWriteB,
output reg wCa, wCb,
output reg [9:0] oRamAddress,
output reg oReadA,oReadB
);
reg [8:0]rEx;
assign oData=rEx;
always @ ( * )
begin
case(wInstruction[15:10])
`ADDA:
begin
rEx=iA+iB;
wCa<=rEx[8];
oRamEnableWrite<=1'b0;
oWriteA<=1'b1;
oWriteB<=1'b0;
wCb<=1'b0;
oReadA<=1'b0;
oReadB<=1'b0;
end
`ADDB:
begin
rEx=iB+iA;
wCb<=rEx[8];
oRamEnableWrite<=1'b0;
oWriteA<=1'b0;
oWriteB<=1'b1;
wCa<=1'b0;
oReadA<=1'b0;
oReadB<=1'b0;
end
`ADDCA:
begin
rEx=iA+iB;
wCa<=rEx[8];
oRamEnableWrite<=1'b0;
oWriteA<=1'b1;
oWriteB<=1'b0;
wCb<=1'b0;
oReadA<=1'b0;
oReadB<=1'b0;
end
`ADDCB:
begin
rEx=iA+iB;
wCb<=rEx[8];
oRamEnableWrite<=1'b0;
oWriteB<=1'b1;
oWriteA<=1'b0;
wCa<=1'b0;
oReadA<=1'b0;
oReadB<=1'b0;
end
`SUBA:
begin
rEx=iA-iB;
wCa<=rEx[8];
oRamEnableWrite<=1'b0;
oWriteA<=1'b1;
oWriteB<=1'b0;
wCb<=1'b0;
oReadA<=1'b0;
oReadB<=1'b0;
end
`SUBB:
begin
rEx=iB-iA;
wCb<=rEx[8];
oRamEnableWrite<=1'b0;
oWriteA<=1'b0;
oWriteB<=1'b1;
wCa<=1'b0;
oReadA<=1'b0;
oReadB<=1'b0;
end
`SUBCA:
begin
rEx=iA-iB;
wCa<=rEx[8];
oRamEnableWrite<=1'b0;
oWriteA<=1'b1;
oWriteB<=1'b0;
wCb<=1'b0;
oReadA<=1'b0;
oReadB<=1'b0;
end
`SUBCB:
begin
rEx=iB-iA;
wCb<=rEx[8];
oRamEnableWrite<=1'b0;
oWriteB<=1'b1;
oWriteA<=1'b0;
wCa<=1'b0;
oReadA<=1'b0;
oReadB<=1'b0;
end
`ANDA:
begin
rEx=iA&iB;
wCa<=wCa;
oRamEnableWrite<=1'b0;
oWriteA<=1'b1;
oWriteB<=1'b0;
wCb<=wCb;
oReadA<=1'b0;
oReadB<=1'b0;
end
`ANDB:
begin
rEx=iB&iA;
wCb<=wCb;
oRamEnableWrite<=1'b0;
oWriteA<=1'b0;
oWriteB<=1'b1;
wCa<=wCa;
oReadA<=1'b0;
oReadB<=1'b0;
end
`ANDCA:
begin
rEx=iA&iB;
wCa<=wCa;
oRamEnableWrite<=1'b0;
oWriteA<=1'b0;
oWriteB<=1'b0;
wCb<=wCb;
oReadA<=1'b0;
oReadB<=1'b0;
end
`ANDCB:
begin
rEx=iB&iA;
wCb<=wCb;
oRamEnableWrite<=1'b0;
oWriteB<=1'b1;
oWriteA<=1'b0;
oReadA<=1'b0;
oReadB<=1'b0;
wCa<=wCa;
end
`ORA:
begin
rEx=iA|iB;
wCa<=wCa;
oRamEnableWrite<=1'b0;
oWriteA<=1'b1;
oWriteB<=1'b0;
wCb<=wCb;
oReadA<=1'b0;
oReadB<=1'b0;
end
`ORB:
begin
rEx=iB|iA;
wCb<=wCb;
oRamEnableWrite<=1'b0;
oWriteA<=1'b0;
oWriteB<=1'b1;
wCa<=wCa;
oReadA<=1'b0;
oReadB<=1'b0;
end
`ORCA:
begin
rEx=iA|iB;
wCa<=wCa;
oRamEnableWrite<=1'b0;
oWriteA<=1'b0;
oWriteB<=1'b0;
wCb<=wCb;
oReadA<=1'b0;
oReadB<=1'b0;
end
`ORCB:
begin
rEx=iB|iA;
wCb<=wCb;
oRamEnableWrite<=1'b0;
oWriteB<=1'b1;
oWriteA<=1'b0;
wCa<=wCa;
oReadA<=1'b0;
oReadB<=1'b0;
end
`ASLA:
begin
rEx=iA<<1;
wCa<=rEx[8];
oRamEnableWrite<=1'b0;
oWriteA<=1'b1;
oWriteB<=1'b0;
wCb<=wCb;
oReadA<=1'b0;
oReadB<=1'b0;
end
`ASRA:
begin
rEx=iA>>1;
wCa<=rEx[8];
oRamEnableWrite<=1'b0;
oWriteA<=1'b1;
oWriteB<=1'b0;
wCb<=wCb;
oReadA<=1'b0;
oReadB<=1'b0;
end
`LDA:
begin
rEx=rEx;
wCa<=wCa;
oRamAddress=wInstruction[9:0];
oRamEnableWrite<=1'b0;
oReadA<=1'b1;
oReadB<=1'b0;
oWriteA<=1'b0;
oWriteB<=1'b0;
wCb<=wCb;
end
`LDB:
begin
rEx=rEx;
wCa<=wCa;
oRamAddress=wInstruction[9:0];
oRamEnableWrite<=1'b0;
oReadA<=1'b0;
oReadB<=1'b1;
oWriteA<=1'b0;
oWriteB<=1'b0;
wCb<=wCb;
end
`STA:
begin
rEx=iA;
wCa<=wCa;
oRamAddress=wInstruction[9:0];
oRamEnableWrite<=1'b1;
oReadA<=1'b0;
oReadB<=1'b0;
oWriteA<=1'b0;
oWriteB<=1'b0;
wCb<=wCb;
end
`STB:
begin
rEx=iB;
wCa<=wCa;
oRamAddress=wInstruction[9:0];
oRamEnableWrite<=1'b1;
oReadA<=1'b0;
oReadB<=1'b0;
oWriteA<=1'b0;
oWriteB<=1'b0;
wCb<=wCb;
end
`LDCA:
begin
rEx=iA[7:0];
wCa<=wCa;
oRamAddress=wInstruction[9:0];
oRamEnableWrite<=1'b0;
oWriteA<=1'b1;
oWriteB<=1'b0;
oReadA<=1'b0;
oReadB<=1'b0;
wCb<=wCb;
end
`LDCB:
begin
rEx=iB[7:0];
wCa<=wCa;
oRamAddress=wInstruction[9:0];
oRamEnableWrite<=1'b0;
oWriteA<=1'b0;
oWriteB<=1'b1;
oReadA<=1'b0;
oReadB<=1'b0;
wCb<=wCb;
end
default: //Todos los Branches van a caer en este caso es un NOP
begin
rEx=rEx;
wCa<=wCa;
oRamAddress=wInstruction[9:0];
oRamEnableWrite<=1'b0;
oWriteA<=1'b0;
oWriteB<=1'b0;
oReadA<=1'b0;
oReadB<=1'b0;
wCb<=wCb;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int get() { char ch; while (ch = getchar(), (ch < 0 || ch > 9 ) && ch != - ) ; if (ch == - ) { int s = 0; while (ch = getchar(), ch >= 0 && ch <= 9 ) s = s * 10 + ch - 0 ; return -s; } int s = ch - 0 ; while (ch = getchar(), ch >= 0 && ch <= 9 ) s = s * 10 + ch - 0 ; return s; } const int N = 100005; const int L = 262144; int n, a[N]; int d[20][N]; int ans[40]; int key[40]; void dfs(int x) { if (d[x - 1][0] == 1) { if (d[x - 1][1] != 0) return; if (key[0] < ans[0]) { ans[0] = key[0]; for (int i = 1; i <= key[0]; i++) ans[i] = key[i]; } return; } int mv = 1 << 19; for (int i = 1; i <= d[x - 1][0]; i++) { int v = abs(d[x - 1][i]); if ((v & -v) > 0) mv = min(mv, v & -v); } if (mv == (1 << 19)) return; key[++key[0]] = mv; d[x][0] = 0; for (int i = 1; i <= d[x - 1][0]; i++) { if ((d[x - 1][i] & mv) > 0) d[x][++d[x][0]] = d[x - 1][i] - mv; else d[x][++d[x][0]] = d[x - 1][i]; } sort(d[x] + 1, d[x] + 1 + d[x][0]); int k = 1; for (int i = 2; i <= d[x][0]; i++) if (d[x][i] != d[x][i - 1]) d[x][++k] = d[x][i]; d[x][0] = k; dfs(x + 1); key[key[0]] = -mv; d[x][0] = 0; for (int i = 1; i <= d[x - 1][0]; i++) { if ((d[x - 1][i] & mv) > 0) d[x][++d[x][0]] = d[x - 1][i] + mv; else d[x][++d[x][0]] = d[x - 1][i]; } sort(d[x] + 1, d[x] + 1 + d[x][0]); k = 1; for (int i = 2; i <= d[x][0]; i++) if (d[x][i] != d[x][i - 1]) d[x][++k] = d[x][i]; d[x][0] = k; dfs(x + 1); key[0]--; } int main() { n = get(); for (int i = 1; i <= n; i++) a[i] = get(); ans[0] = 100; a[++n] = 0; sort(a + 1, a + 1 + n); int n_ = 1; for (int i = 2; i <= n; i++) if (a[i] != a[i - 1]) a[++n_] = a[i]; n = n_; for (int i = 1; i <= n; i++) d[0][i] = a[i]; d[0][0] = n; dfs(1); printf( %d n , ans[0]); for (int i = 1; i <= ans[0]; i++) printf( %d , ans[i]); return 0; } |
module gpio_tx(
#(
parameter GPIO_DATA_WIDTH = 8
)
(
//gpio_wr_interface
output [GPIO_DATA_WIDTH-1:0] gpio_rd_data,
output gpio_rd_par,
input gpio_rd_err,
output gpio_rd_req,
input gpio_rd_ack,
//gpio_fifo_interface
input [GPIO_DATA_WIDTH-1:0] gpio_n2p_data,
input gpio_n2p_req,
output gpio_n2p_done,
//misc
input reset,
input clk
);
always@(posedge clk)
begin
gpio_rd_ack_reg <= gpio_rd_ack;
gpio_rd_err_reg <= gpio_rd_err;
end
localparam
GPIO_TX_IDLE = 2'h0,
GPIO_TX_CHECK = 2'h1,
GPIO_TX_CHECK_DONE = 2'h2,
GPIO_TX_DONE = 2'h3;
//state_machine
always@(posedge clk)
begin
gpio_tx_state <= gpio_tx_state_nxt;
end
//rx state
always@(*)
begin
if(reset)
gpio_tx_state_nxt = GPIO_TX_IDLE;
else
begin
case(gpio_tx_state)
GPIO_TX_IDLE:
begin
if(gpio_wr_req_reg)
gpio_tx_state_nxt = GPIO_TX_CHECK;
else
gpio_tx_state_nxt = GPIO_TX_IDLE;
end
GPIO_TX_CHECK:
gpio_tx_state_nxt = GPIO_TX_CHECK_DONE;
GPIO_TX_CHECK_DONE:
gpio_tx_state_nxt = GPIO_TX_DONE;
GPIO_TX_DONE:
if(!gpio_wr_req_reg)
gpio_tx_state_nxt = GPIO_TX_IDLE;
else
gpio_tx_state_nxt = GPIO_TX_DONE;
default:
gpio_tx_state_nxt <= gpio_tx_state;
end
end
//tx state
*/
always@(posedge clk)
begin //to fifo
if(gpio_tx_state == GPIO_TX_CHECK_DONE && !gpio_wr_err)
end
always@(posedge clk)
begin
if(gpio_tx_state == GPIO_TX_CHECK_DONE)
gpio_wr_ack = 1'b1;
else if(gpio_tx_state == GPIO_TX_IDLE)
gpio_wr_ack = 1'b0;
else
gpio_wr_ack = gpio_wr_ack;
end
always@(posedge clk)
begin //even parity bit
if(gpio_tx_state == GPIO_TX_CHECK)
begin
if((^ gpio_wr_data_reg) ^ gpio_wr_par_reg)
gpio_wr_err = 1'b1;
else
gpio_wr_err = 1'b0;
end
else
gpio_wr_err = gpio_wr_err;
end
endmodule
|
`define WINDOW_SIZE ((2**WINDOW_WIDTH))
`define LARGE_CLOG2(x) clog2(x)
`define MAXIMUM_ROLLING_SUM ((2**WIDTH)-1)
`define MAXIMUM_ROLLING_SQUARES_SUM (pow(2,(WIDTH*2))-1)
`include "math.v"
module variance #(
parameter WIDTH=14, // data input width
parameter WINDOW_WIDTH=7 // window size will be 2^WINDOW_WIDTH, so the default here is a size of 128
)
(
input wire [WIDTH-1:0] data_in,
output reg [WIDTH*2-1:0] data_out,
input wire reset,
input wire clk
);
reg [`LARGE_CLOG2(`MAXIMUM_ROLLING_SUM * `WINDOW_SIZE)-1:0] rolling_sum;
reg [`LARGE_CLOG2(`MAXIMUM_ROLLING_SQUARES_SUM * `WINDOW_SIZE)-1:0] rolling_squares_sum;
wire [WIDTH-1:0] fifo_dout;
wire fifo_data_valid;
fifo #(.WIDTH(WIDTH), .DEPTH(`WINDOW_SIZE)) fifo_inst (
.data_in(data_in),
.data_out(fifo_dout),
.data_valid(fifo_data_valid),
.reset(reset),
.clk(clk)
);
reg [`LARGE_CLOG2(`MAXIMUM_ROLLING_SUM*`MAXIMUM_ROLLING_SUM * (`WINDOW_SIZE+1))-1:0] mean_squared [2:0];
reg [`LARGE_CLOG2(`MAXIMUM_ROLLING_SQUARES_SUM * (`WINDOW_SIZE+1))-1:0] mean_of_squares [2:0];
reg [WIDTH-1:0] data_in_delay [2:0];
reg [WIDTH-1:0] fifo_dout_delay [2:0];
reg [`LARGE_CLOG2(pow(2,WIDTH*2))-1:0] data_in_squared [2:0];
reg [`LARGE_CLOG2(pow(2,WIDTH*2))-1:0] fifo_dout_squared [2:0];
always @(posedge clk) begin
if (reset == 1'b0) begin
rolling_sum <= 0;
rolling_squares_sum <= 0;
data_in_delay[0] <= 0; data_in_delay[1] <= 0; data_in_delay[2] <= 0;
data_in_squared[0] <= 0; data_in_squared[1] <= 0; data_in_squared[2] <= 0;
fifo_dout_delay[0] <= 0; fifo_dout_delay[1] <= 0; fifo_dout_delay[2] <= 0;
fifo_dout_squared[0] <= 0; fifo_dout_squared[1] <= 0; fifo_dout_squared[2] <= 0;
end else begin
data_in_delay[0] <= data_in;
data_in_delay[1] <= data_in_delay[0];
data_in_delay[2] <= data_in_delay[1]; // delay is required to keep data in sync with DSP output
data_in_squared[0] <= data_in*data_in;
data_in_squared[1] <= data_in_squared[0];
data_in_squared[2] <= data_in_squared[1]; // pipeline DSP output
if (fifo_data_valid) begin
fifo_dout_delay[0] <= fifo_dout;
fifo_dout_delay[1] <= fifo_dout_delay[0];
fifo_dout_delay[2] <= fifo_dout_delay[1]; // delay is required to keep data in sync with DSP output
fifo_dout_squared[0] <= fifo_dout*fifo_dout;
fifo_dout_squared[1] <= fifo_dout_squared[0];
fifo_dout_squared[2] <= fifo_dout_squared[1]; // pipeline DSP output
rolling_sum <= rolling_sum + data_in_delay[2] - fifo_dout_delay[2];
rolling_squares_sum <= rolling_squares_sum + data_in_squared[2] - fifo_dout_squared[2];
mean_squared[0] <= (rolling_sum >> WINDOW_WIDTH) * (rolling_sum >> WINDOW_WIDTH);
mean_squared[1] <= mean_squared[0];
mean_squared[2] <= mean_squared[1];
mean_of_squares[0] <= (rolling_squares_sum >> WINDOW_WIDTH);
mean_of_squares[1] <= mean_of_squares[0];
mean_of_squares[2] <= mean_of_squares[1];
data_out <= mean_of_squares[2] - mean_squared[2];
end else begin
// just load up the sums
rolling_sum <= rolling_sum + data_in_delay[2];
rolling_squares_sum <= rolling_squares_sum + data_in_squared[2];
end
end
end
initial begin
$dumpfile("dump.vcd");
$dumpvars(0, variance);
end
endmodule |
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_never_unknown_async (reset, enable, test_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 1;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input reset, enable;
input [width-1:0] test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_NEVER_UNKNOWN_ASYNC";
`include "std_ovl_reset.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/assert_never_unknown_async_logic.v"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_SVA
`include "./sva05/assert_never_unknown_async_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_never_unknown_async_psl_logic.v"
`else
`endmodule // ovl_never_unknown_async
`endif
|
`define bsg_mem_1rw_sync_mask_write_bit_macro(words,bits) \
if (els_p == words && width_p == bits) \
begin: macro \
hard_mem_1rw_bit_mask_d``words``_w``bits``_wrapper \
mem \
(.clk_i (clk_i) \
,.reset_i (reset_i) \
,.data_i (data_i) \
,.addr_i (addr_i) \
,.v_i (v_i) \
,.w_mask_i(w_mask_i) \
,.w_i (w_i) \
,.data_o (data_o) \
); \
end: macro
`define bsg_mem_1rw_sync_mask_write_bit_banked_macro(words,bits,wbank,dbank) \
if (els_p == words && width_p == bits) begin: macro \
bsg_mem_1rw_sync_mask_write_bit_banked #( \
.width_p(width_p) \
,.els_p(els_p) \
,.latch_last_read_p(latch_last_read_p) \
,.num_width_bank_p(wbank) \
,.num_depth_bank_p(dbank) \
) bmem ( \
.clk_i(clk_i) \
,.reset_i(reset_i) \
,.v_i(v_i) \
,.w_i(w_i) \
,.addr_i(addr_i) \
,.data_i(data_i) \
,.w_mask_i(w_mask_i) \
,.data_o(data_o) \
); \
end: macro
module bsg_mem_1rw_sync_mask_write_bit #( parameter `BSG_INV_PARAM(width_p )
, parameter `BSG_INV_PARAM(els_p )
, parameter addr_width_lp = `BSG_SAFE_CLOG2(els_p)
, parameter latch_last_read_p = 0
)
( input clk_i
, input reset_i
, input [width_p-1:0] data_i
, input [addr_width_lp-1:0] addr_i
, input v_i
, input [width_p-1:0] w_mask_i
, input w_i
, output logic [width_p-1:0] data_o
);
wire unused = reset_i;
// TODO: Define more hardened macro configs here
`bsg_mem_1rw_sync_mask_write_bit_macro(64,7) else
`bsg_mem_1rw_sync_mask_write_bit_macro(64,15) else
`bsg_mem_1rw_sync_mask_write_bit_macro(64,124) else
`bsg_mem_1rw_sync_mask_write_bit_macro(128,15) else
`bsg_mem_1rw_sync_mask_write_bit_macro(128,116) else
`bsg_mem_1rw_sync_mask_write_bit_macro(128,84) else
`bsg_mem_1rw_sync_mask_write_bit_macro(64,92) else
`bsg_mem_1rw_sync_mask_write_bit_macro(512,23) else
`bsg_mem_1rw_sync_mask_write_bit_banked_macro(64,248,2,1) else
`bsg_mem_1rw_sync_mask_write_bit_banked_macro(128,232,2,1) else
`bsg_mem_1rw_sync_mask_write_bit_banked_macro(128,168,2,1) else
`bsg_mem_1rw_sync_mask_write_bit_banked_macro(64,184,2,1) else
begin: notmacro
bsg_mem_1rw_sync_mask_write_bit_synth #(.width_p(width_p), .els_p(els_p), .latch_last_read_p(latch_last_read_p))
synth
(.*);
end // block: notmacro
// synopsys translate_off
always_ff @(posedge clk_i)
begin
if (v_i)
assert (addr_i < els_p)
else $error("Invalid address %x to %m of size %x\n", addr_i, els_p);
end
initial
begin
$display("## %L: instantiating width_p=%d, els_p=%d (%m)",width_p,els_p);
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1rw_sync_mask_write_bit)
|
#include <bits/stdc++.h> using namespace std; map<long long, int> cnt; int lp[100005]; long long p[100005][102]; void sieve() { for (int i = 2; i <= 100000; i++) { if (!lp[i]) { lp[i] = i; for (int j = i + i; j <= 100000; j += i) if (!lp[j]) lp[j] = i; } } } int main() { int n, k, a; long long ans = 0; sieve(); for (int i = 1; i <= 100000; i++) { p[i][0] = 1; for (int j = 1; j <= 100; j++) { p[i][j] = p[i][j - 1] * i; if (p[i][j] > 1e9) p[i][j] = 0; } } scanf( %d%d , &n, &k); for (int i = 0; i < n; i++) { scanf( %d , &a); long long cur = 1; long long mate = 1; while (a > 1) { int cnt = 0; int prime = lp[a]; while (a % prime == 0) { a /= prime; cnt++; } cnt %= k; cur *= p[prime][cnt]; mate *= p[prime][(k - cnt) % k]; if (mate > 1e9) mate = 0; } if (mate != 0 && cnt.count(mate)) ans += cnt[mate]; cnt[cur]++; } printf( %lld n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, root; vector<vector<int> > tree, par, sub; vector<vector<long long> > dp; void dfs(int u) { sub[root][u] = 1; for (int v : tree[u]) { if (v == par[root][u]) continue; par[root][v] = u; dfs(v); sub[root][u] += sub[root][v]; } } long long getDP(int u, int v) { if (u == v) return 0; if (dp[u][v] != -1) return dp[u][v]; long long res = sub[u][v] * sub[v][u] + max(getDP(par[v][u], v), getDP(u, par[u][v])); return dp[u][v] = res; } void input() { scanf( %d , &n); tree.assign(n, vector<int>()); for (int i = 0; i < n - 1; ++i) { int u, v; scanf( %d%d , &u, &v); --u, --v; tree[u].push_back(v); tree[v].push_back(u); } } void solve() { par.assign(n, vector<int>(n, -1)); sub.assign(n, vector<int>(n, -1)); for (int u = 0; u < n; ++u) { root = u; dfs(u); } dp.assign(n, vector<long long>(n, -1LL)); long long ans = 0; for (int u = 0; u < n; ++u) for (int v = 0; v < n; ++v) ans = max(ans, getDP(u, v)); cout << ans << endl; } int main() { input(); solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAX = 2e5 + 5; int n, k, a; int vis_time[MAX], vis_cnt[MAX], ans; struct data { int size, op; bool operator<(data b) const { if (size == b.size) return op > b.op; else return size < b.size; } }; priority_queue<data> line; int main() { scanf( %d%d , &n, &k); for (register int i = 1; i <= n; ++i) { scanf( %d , &a); line.push((data){a, 0}); } ans = 0x3f3f3f3f; while (!line.empty()) { data tmp = line.top(); line.pop(); int size = tmp.size, op = tmp.op; vis_time[size]++; vis_cnt[size] += op; if (vis_time[size] == k) { ans = min(ans, vis_cnt[size]); } if (!size) continue; else line.push((data){size / 2, op + 1}); } printf( %d n , ans); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKDLYBUF4S15_FUNCTIONAL_V
`define SKY130_FD_SC_LP__CLKDLYBUF4S15_FUNCTIONAL_V
/**
* clkdlybuf4s15: Clock Delay Buffer 4-stage 0.15um length inner stage
* gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__clkdlybuf4s15 (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKDLYBUF4S15_FUNCTIONAL_V |
module fifo_address_gray (
input m_axis_aclk,
input m_axis_aresetn,
input m_axis_ready,
output reg m_axis_valid,
output [C_ADDRESS_WIDTH-1:0] m_axis_raddr_next,
input s_axis_aclk,
input s_axis_aresetn,
output reg s_axis_ready,
input s_axis_valid,
output reg s_axis_empty,
output [C_ADDRESS_WIDTH-1:0] s_axis_waddr
);
parameter C_ADDRESS_WIDTH = 4;
reg [C_ADDRESS_WIDTH:0] _s_axis_waddr = 'h00;
reg [C_ADDRESS_WIDTH:0] _s_axis_waddr_next;
reg [C_ADDRESS_WIDTH:0] _m_axis_raddr = 'h00;
reg [C_ADDRESS_WIDTH:0] _m_axis_raddr_next;
reg [C_ADDRESS_WIDTH:0] s_axis_waddr_gray = 'h00;
wire [C_ADDRESS_WIDTH:0] s_axis_waddr_gray_next;
wire [C_ADDRESS_WIDTH:0] s_axis_raddr_gray;
reg [C_ADDRESS_WIDTH:0] m_axis_raddr_gray = 'h00;
wire [C_ADDRESS_WIDTH:0] m_axis_raddr_gray_next;
wire [C_ADDRESS_WIDTH:0] m_axis_waddr_gray;
assign s_axis_waddr = _s_axis_waddr[C_ADDRESS_WIDTH-1:0];
assign m_axis_raddr_next = _m_axis_raddr_next[C_ADDRESS_WIDTH-1:0];
always @*
begin
if (s_axis_ready && s_axis_valid)
_s_axis_waddr_next <= _s_axis_waddr + 1;
else
_s_axis_waddr_next <= _s_axis_waddr;
end
assign s_axis_waddr_gray_next = _s_axis_waddr_next ^ _s_axis_waddr_next[C_ADDRESS_WIDTH:1];
always @(posedge s_axis_aclk)
begin
if (s_axis_aresetn == 1'b0) begin
_s_axis_waddr <= 'h00;
s_axis_waddr_gray <= 'h00;
end else begin
_s_axis_waddr <= _s_axis_waddr_next;
s_axis_waddr_gray <= s_axis_waddr_gray_next;
end
end
always @*
begin
if (m_axis_ready && m_axis_valid)
_m_axis_raddr_next <= _m_axis_raddr + 1;
else
_m_axis_raddr_next <= _m_axis_raddr;
end
assign m_axis_raddr_gray_next = _m_axis_raddr_next ^ _m_axis_raddr_next[C_ADDRESS_WIDTH:1];
always @(posedge m_axis_aclk)
begin
if (m_axis_aresetn == 1'b0) begin
_m_axis_raddr <= 'h00;
m_axis_raddr_gray <= 'h00;
end else begin
_m_axis_raddr <= _m_axis_raddr_next;
m_axis_raddr_gray <= m_axis_raddr_gray_next;
end
end
sync_bits #(
.NUM_BITS(C_ADDRESS_WIDTH + 1)
) i_waddr_sync (
.out_clk(m_axis_aclk),
.out_resetn(m_axis_aresetn),
.in(s_axis_waddr_gray),
.out(m_axis_waddr_gray)
);
sync_bits #(
.NUM_BITS(C_ADDRESS_WIDTH + 1)
) i_raddr_sync (
.out_clk(s_axis_aclk),
.out_resetn(s_axis_aresetn),
.in(m_axis_raddr_gray),
.out(s_axis_raddr_gray)
);
always @(posedge s_axis_aclk)
begin
if (s_axis_aresetn == 1'b0) begin
s_axis_ready <= 1'b1;
s_axis_empty <= 1'b1;
end else begin
s_axis_ready <= (s_axis_raddr_gray[C_ADDRESS_WIDTH] == s_axis_waddr_gray_next[C_ADDRESS_WIDTH] ||
s_axis_raddr_gray[C_ADDRESS_WIDTH-1] == s_axis_waddr_gray_next[C_ADDRESS_WIDTH-1] ||
s_axis_raddr_gray[C_ADDRESS_WIDTH-2:0] != s_axis_waddr_gray_next[C_ADDRESS_WIDTH-2:0]);
s_axis_empty <= s_axis_raddr_gray == s_axis_waddr_gray_next;
end
end
always @(posedge m_axis_aclk)
begin
if (s_axis_aresetn == 1'b0)
m_axis_valid <= 1'b0;
else begin
m_axis_valid <= m_axis_waddr_gray != m_axis_raddr_gray_next;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFBBP_PP_SYMBOL_V
`define SKY130_FD_SC_LS__DFBBP_PP_SYMBOL_V
/**
* dfbbp: Delay flop, inverted set, inverted reset,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dfbbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
input SET_B ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFBBP_PP_SYMBOL_V
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ac
//
// Generated
// by: wig
// on: Tue Jun 27 05:12:12 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ac.v,v 1.6 2006/07/04 09:54:11 wig Exp $
// $Date: 2006/07/04 09:54:11 $
// $Log: ent_ac.v,v $
// Revision 1.6 2006/07/04 09:54:11 wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_ac
//
// No user `defines in this module
module ent_ac
//
// Generated Module inst_ac
//
(
port_ac_2 // Use internally test2, no port generated
);
// Generated Module Outputs:
output port_ac_2;
// Generated Wires:
wire port_ac_2;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of ent_ac
//
//
//!End of Module/s
// --------------------------------------------------------------
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.2
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module video_scaler_sdivhbi_div_u
#(parameter
in0_WIDTH = 32,
in1_WIDTH = 32,
out_WIDTH = 32
)
(
input clk,
input reset,
input ce,
input start,
input [in0_WIDTH-1:0] dividend,
input [in1_WIDTH-1:0] divisor,
input [1:0] sign_i,
output wire [1:0] sign_o,
output wire done,
output wire [out_WIDTH-1:0] quot,
output wire [out_WIDTH-1:0] remd
);
localparam cal_WIDTH = (in0_WIDTH > in1_WIDTH)? in0_WIDTH : in1_WIDTH;
//------------------------Local signal-------------------
reg [in0_WIDTH-1:0] dividend0;
reg [in1_WIDTH-1:0] divisor0;
reg [1:0] sign0;
reg [in0_WIDTH-1:0] dividend_tmp;
reg [in0_WIDTH-1:0] remd_tmp;
wire [in0_WIDTH-1:0] dividend_tmp_mux;
wire [in0_WIDTH-1:0] remd_tmp_mux;
wire [in0_WIDTH-1:0] comb_tmp;
wire [cal_WIDTH:0] cal_tmp;
//------------------------Body---------------------------
assign quot = dividend_tmp;
assign remd = remd_tmp;
assign sign_o = sign0;
// dividend0, divisor0
always @(posedge clk)
begin
if (start) begin
dividend0 <= dividend;
divisor0 <= divisor;
sign0 <= sign_i;
end
end
// One-Hot Register
// r_stage[0]=1:accept input; r_stage[in0_WIDTH]=1:done
reg [in0_WIDTH:0] r_stage;
assign done = r_stage[in0_WIDTH];
always @(posedge clk)
begin
if (reset == 1'b1)
r_stage[in0_WIDTH:0] <= {in0_WIDTH{1'b0}};
else if (ce)
r_stage[in0_WIDTH:0] <= {r_stage[in0_WIDTH-1:0], start};
end
// MUXs
assign dividend_tmp_mux = r_stage[0]? dividend0 : dividend_tmp;
assign remd_tmp_mux = r_stage[0]? {in0_WIDTH{1'b0}} : remd_tmp;
if (in0_WIDTH == 1) assign comb_tmp = dividend_tmp_mux[0];
else assign comb_tmp = {remd_tmp_mux[in0_WIDTH-2:0], dividend_tmp_mux[in0_WIDTH-1]};
assign cal_tmp = {1'b0, comb_tmp} - {1'b0, divisor0};
always @(posedge clk)
begin
if (ce) begin
if (in0_WIDTH == 1) dividend_tmp <= ~cal_tmp[cal_WIDTH];
else dividend_tmp <= {dividend_tmp_mux[in0_WIDTH-2:0], ~cal_tmp[cal_WIDTH]};
remd_tmp <= cal_tmp[cal_WIDTH]? comb_tmp : cal_tmp[in0_WIDTH-1:0];
end
end
endmodule
module video_scaler_sdivhbi_div
#(parameter
in0_WIDTH = 32,
in1_WIDTH = 32,
out_WIDTH = 32
)
(
input clk,
input reset,
input ce,
input start,
output reg done,
input [in0_WIDTH-1:0] dividend,
input [in1_WIDTH-1:0] divisor,
output reg [out_WIDTH-1:0] quot,
output reg [out_WIDTH-1:0] remd
);
//------------------------Local signal-------------------
reg start0 = 'b0;
wire done0;
reg [in0_WIDTH-1:0] dividend0;
reg [in1_WIDTH-1:0] divisor0;
wire [in0_WIDTH-1:0] dividend_u;
wire [in1_WIDTH-1:0] divisor_u;
wire [out_WIDTH-1:0] quot_u;
wire [out_WIDTH-1:0] remd_u;
wire [1:0] sign_i;
wire [1:0] sign_o;
//------------------------Instantiation------------------
video_scaler_sdivhbi_div_u #(
.in0_WIDTH ( in0_WIDTH ),
.in1_WIDTH ( in1_WIDTH ),
.out_WIDTH ( out_WIDTH )
) video_scaler_sdivhbi_div_u_0 (
.clk ( clk ),
.reset ( reset ),
.ce ( ce ),
.start ( start0 ),
.done ( done0 ),
.dividend ( dividend_u ),
.divisor ( divisor_u ),
.sign_i ( sign_i ),
.sign_o ( sign_o ),
.quot ( quot_u ),
.remd ( remd_u )
);
//------------------------Body---------------------------
assign sign_i = {dividend0[in0_WIDTH-1] ^ divisor0[in1_WIDTH-1], dividend0[in0_WIDTH-1]};
assign dividend_u = dividend0[in0_WIDTH-1]? ~dividend0[in0_WIDTH-1:0] + 1'b1 :
dividend0[in0_WIDTH-1:0];
assign divisor_u = divisor0[in1_WIDTH-1]? ~divisor0[in1_WIDTH-1:0] + 1'b1 :
divisor0[in1_WIDTH-1:0];
always @(posedge clk)
begin
if (ce) begin
dividend0 <= dividend;
divisor0 <= divisor;
start0 <= start;
end
end
always @(posedge clk)
begin
done <= done0;
end
always @(posedge clk)
begin
if (done0) begin
if (sign_o[1])
quot <= ~quot_u + 1'b1;
else
quot <= quot_u;
end
end
always @(posedge clk)
begin
if (done0) begin
if (sign_o[0])
remd <= ~remd_u + 1'b1;
else
remd <= remd_u;
end
end
endmodule
`timescale 1 ns / 1 ps
module video_scaler_sdivhbi(
clk,
reset,
ce,
start,
done,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input start;
output done;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
wire[dout_WIDTH - 1:0] sig_remd;
video_scaler_sdivhbi_div #(
.in0_WIDTH( din0_WIDTH ),
.in1_WIDTH( din1_WIDTH ),
.out_WIDTH( dout_WIDTH ))
video_scaler_sdivhbi_div_U(
.dividend( din0 ),
.divisor( din1 ),
.quot( dout ),
.remd( sig_remd ),
.clk( clk ),
.ce( ce ),
.reset( reset ),
.start( start ),
.done( done ));
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11.06.2017 19:09:17
// Design Name:
// Module Name: ALU
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ALU
#( parameter n =16
)(
input [15:0] operador_1,
input [15:0] operador_2,
input [2:0] control,
output wire [3:0] flags,
output reg [15:0] resultado
);
reg V,C,Z,N;
assign flags={V,C,Z,N};
always @(*) begin
case(control)
3'd1: resultado= operador_1 + operador_2;
3'd2: resultado= operador_1 - operador_2;
3'd3: resultado= operador_1 * operador_2;
3'd4: resultado= operador_1 & operador_2;
3'd5: resultado= operador_1 | operador_2;
default resultado = 16'b0;
endcase
end
always @(*) begin
case(control)
3'd1: begin
if(operador_1[0]==1'b0 & operador_2[0]==1'b0 & resultado[0]==1'b1) begin
V=1'b1;
end
else begin
V=1'b0;
end
if((operador_1[0]==1'b1 | operador_2[0]==1'b1) & resultado[0]==1'b0) begin
C=1'b1;
end
else begin
C=1'b0;
end
end
3'd2: begin
if (operador_1[0]==1'b1 & operador_2[0]==1'b1 & resultado[0]==1'b0) begin
V=1'b1;
end
else begin
V=1'b0;
end
if ((operador_1[0]==1'b0 | operador_2[0]==1'b0) & resultado[0]==1'b1) begin
C=1'b1;
end
else begin
C=1'b0;
end
end
default:{V,C}={1'b0,1'b0};
endcase
if (control==3'd2 & operador_1 < operador_2) begin
N=1'b1;
end
else begin
N=1'b0;
end
if (resultado==16'b0) begin
Z=1'b1;
end
else begin
Z=1'b0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long int mod = 1e9 + 7; int main() { long long int t, n, ans = 0, count0 = 0, count1 = 0, count2 = 0, num0 = 0, num1 = 0, num2 = 0; t = 1; while (t--) { cin >> n; vector<long long int> A(n, 0); for (int i = 0; i < n; i++) { cin >> A[i]; } sort(A.begin(), A.end()); for (int i = n - 1; i >= 0; i--) { if (A[i] > 0) { count1 += (A[i] - 1); num1++; } else if (A[i] == 0) { count0++; num0++; } else { count2 += (-1 - A[i]); num2++; } } ans += count1; if (num2 % 2 == 0) { ans += count2; ans += count0; } else { if (num0 > 0) { ans += count0; ans += count2; } else { ans += count0; ans += (count2 + 2); } } cout << ans << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long t; cin >> t; while (t--) { double l, r; cin >> l >> r; if (l > r / 2) { cout << YES << endl; } else { cout << NO << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 4e5 + 5; int n, q, l[N], r[N], level[N], p[N][20]; pair<int, int> res[N]; int import[N], numCity, numVirus, node[N], total_num; vector<int> adj[N], newAdj[N]; struct T { int city, speed; }; T virus[N]; int cnt = 0; void dfs(int x, int pa) { cnt++; l[x] = cnt; p[x][0] = pa; for (auto &u : adj[x]) { if (u == pa) continue; level[u] = level[x] + 1; dfs(u, x); } r[x] = cnt; } void init_lca() { for (int k = 1; k <= 18; k++) { for (int i = 1; i <= n; i++) p[i][k] = p[p[i][k - 1]][k - 1]; } } int lca(int x, int y) { if (x == 1 || y == 1) return 1; if (level[x] > level[y]) swap(x, y); int diff = level[y] - level[x]; for (int k = 18; k >= 0; k--) if (diff >> k & 1) y = p[y][k]; if (x == y) return x; for (int k = 18; k >= 0; k--) { if (p[x][k] != p[y][k]) { x = p[x][k]; y = p[y][k]; } } return p[x][0]; } bool isParent(int p, int u) { return (l[p] <= l[u] && l[u] <= r[p]); } bool lf(const int &x, const int &y) { return l[x] < l[y]; } int dist(int x, int y) { return level[x] + level[y] - 2 * level[lca(x, y)]; } void compress_tree() { total_num = numCity + numVirus; for (int i = 1; i <= numVirus; i++) node[i] = virus[i].city; for (int i = numVirus + 1; i <= total_num; i++) node[i] = import[i - numVirus]; sort(node + 1, node + total_num + 1, lf); total_num = unique(node + 1, node + total_num + 1) - node - 1; int now = total_num; for (int i = 1; i < now; i++) { total_num++; node[total_num] = lca(node[i], node[i + 1]); } sort(node + 1, node + total_num + 1, lf); total_num = unique(node + 1, node + total_num + 1) - node - 1; for (int i = 1; i <= total_num; i++) newAdj[node[i]].clear(); stack<int> st; st.push(node[1]); for (int i = 2; i <= total_num; i++) { while (!st.empty() && !isParent(st.top(), node[i])) st.pop(); if (!st.empty()) { int par = st.top(); newAdj[par].push_back(node[i]); newAdj[node[i]].push_back(par); } st.push(node[i]); } } int calc(int dist, int s) { return (dist - 1 + s) / s; } void solve() { for (int i = 1; i <= total_num; i++) res[node[i]] = make_pair(1e9, 0); priority_queue<pair<pair<int, int>, int>, vector<pair<pair<int, int>, int>>, greater<pair<pair<int, int>, int>>> pq; for (int i = 1; i <= numVirus; i++) { int id = virus[i].city; res[id] = make_pair(0, i); pq.push(make_pair(res[id], id)); } while (!pq.empty()) { auto now = pq.top(); pq.pop(); if (res[now.second] != now.first) continue; for (auto &u : newAdj[now.second]) { if (res[u] > make_pair(calc(dist(u, virus[now.first.second].city), virus[now.first.second].speed), now.first.second)) { res[u] = make_pair(calc(dist(u, virus[now.first.second].city), virus[now.first.second].speed), now.first.second); pq.push(make_pair(res[u], u)); } } } for (int i = 1; i <= numCity; i++) cout << res[import[i]].second << ; cout << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cin >> n; for (int i = 1; i < n; i++) { int u, v; cin >> u >> v; adj[u].push_back(v); adj[v].push_back(u); } dfs(1, 0); init_lca(); cin >> q; while (q--) { cin >> numVirus >> numCity; for (int i = 1; i <= numVirus; i++) cin >> virus[i].city >> virus[i].speed; for (int i = 1; i <= numCity; i++) cin >> import[i]; compress_tree(); solve(); } } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 100010; int n, br; int p[MAXN], niz[MAXN], num[MAXN], bio[MAXN]; inline void ne() { printf( NO n ); exit(0); } void dfs1(int x) { if (bio[x]) return; bio[x] = br; num[br]++; dfs1(niz[x]); } void dfs2(int x) { if (bio[x]) return; bio[x] = 1; if (bio[niz[x]]) return; printf( %d %d n , x, niz[x]); dfs2(niz[x]); } void dfs3(int x, int y) { if (bio[x]) return; bio[x] = 1; printf( %d %d n , x, y); dfs3(niz[x], niz[y]); } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &p[i]); for (int i = 1; i <= n; i++) niz[p[i]] = p[p[i]]; br = 1; for (int i = 1; i <= n; i++) if (!bio[i]) { dfs1(i); br++; } int poc = 0, val = MAXN, grupa = 0; for (int i = 1; i <= n; i++) if (num[bio[i]] < val) { val = num[bio[i]]; poc = i; grupa = bio[i]; } if (num[grupa] > 2) ne(); for (int i = 1; i < br; i++) if (num[i] % num[grupa] != 0) ne(); printf( YES n ); memset(bio, 0, sizeof(bio)); dfs2(poc); for (int i = 1; i <= n; i++) if (!bio[i]) dfs3(i, poc); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND4B_4_V
`define SKY130_FD_SC_MS__NAND4B_4_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog wrapper for nand4b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__nand4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nand4b_4 (
Y ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__nand4b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nand4b_4 (
Y ,
A_N,
B ,
C ,
D
);
output Y ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__nand4b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND4B_4_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, i, a, b, x, y, ans = 0; scanf( %d , &n); printf( YES n ); for (int i = 1; i <= n; i++) { scanf( %d %d %d %d , &a, &b, &x, &y); x = min(a, x); y = min(y, b); ans = abs(x) % 2; ans = ans * 2 + (abs(y) % 2); printf( %d n , ans + 1); } } |
#include <bits/stdc++.h> using namespace std; int main() { int x = 0, y = 0; cin >> x >> y; int z = abs(x) + abs(y); if ((x > 0) && (y > 0)) cout << 0 << << z << << z << << 0; else if ((x < 0) && (y > 0)) cout << -z << << 0 << << 0 << << z; else if ((x > 0) && (y < 0)) cout << 0 << << -z << << z << << 0; else cout << -z << << 0 << << 0 << << -z; return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize(3) using namespace std; using ll = long long; namespace io { const int SIZE = (1 << 21) + 1; char ibuf[SIZE], *iS, *iT, obuf[SIZE], *oS = obuf, *oT = oS + SIZE - 1; char getc() { return (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, SIZE, stdin), (iS == iT ? EOF : *iS++)) : *iS++); } void flush() { fwrite(obuf, 1, oS - obuf, stdout); oS = obuf; } void putc(char x) { *oS++ = x; if (oS == oT) flush(); } template <class T> void read(T &x) { char ch; int f = 1; x = 0; while (isspace(ch = getc())) ; if (ch == - ) ch = getc(), f = -1; do x = x * 10 + (ch - 0 ); while (isdigit(ch = getc())); x *= f; } template <class T, class... A> void read(T &x, A &...args) { read(x); read(args...); } template <class T> void write(T x) { static char stk[128]; int top = 0; if (x == 0) { putc( 0 ); return; } if (x < 0) putc( - ), x = -x; while (x) stk[top++] = x % 10, x /= 10; while (top) putc(stk[--top] + 0 ); } template <class T, class... A> void write(T x, A... args) { write(x); putc( ); write(args...); } void space() { putc( ); } void endl() { putc( n ); } struct _f { ~_f() { flush(); } } __f; } // namespace io using io::endl; using io::flush; using io::getc; using io::putc; using io::read; using io::space; using io::write; const int B = 17; const int N = 100005; const ll INF = 0x3f3f3f3f3f3f3f3f; int phi[N], p[N], pc = 0; bool np[N]; void sieve(int n) { phi[1] = 1; for (int i = 2; i <= n; ++i) { if (!np[i]) p[++pc] = i, phi[i] = i - 1; for (int j = 1; j <= pc && i * p[j] <= n; ++j) { np[i * p[j]] = true; if (i % p[j] == 0) { phi[i * p[j]] = phi[i] * p[j]; break; } phi[i * p[j]] = phi[i] * (p[j] - 1); } } } struct node { ll mn[B], tag; } t[N * 4]; void up(int x) { for (int i = 0; i < B; ++i) t[x].mn[i] = min(t[x << 1].mn[i], t[x << 1 | 1].mn[i]) + t[x].tag; } void tag(int x, int val) { for (int i = 0; i < B; ++i) t[x].mn[i] += val; t[x].tag += val; } void modify(int x, int l, int r, int ql, int qr, int v) { if (ql <= l && r <= qr) { tag(x, v); return; } int mid = (l + r) >> 1; if (ql <= mid) modify(x << 1, l, mid, ql, qr, v); if (qr > mid) modify(x << 1 | 1, mid + 1, r, ql, qr, v); up(x); } void assign(int x, int l, int r, int p, const ll *v, int tag = 0) { if (l == r) { for (int i = 0; i < B; ++i) t[x].mn[i] = v[i] - tag; return; } int mid = (l + r) >> 1; tag += t[x].tag; p <= mid ? assign(x << 1, l, mid, p, v, tag) : assign(x << 1 | 1, mid + 1, r, p, v, tag); up(x); } void build(int x, int l, int r) { memset(t[x].mn, 0x3f, sizeof(t[x].mn)); if (l == 0) t[x].mn[0] = 0; t[x].tag = 0; if (l == r) return; int mid = (l + r) >> 1; build(x << 1, l, mid); build(x << 1 | 1, mid + 1, r); } ll dp[N][B]; vector<int> di[N]; void prework(int n) { sieve(n); for (int i = 1; i <= n; ++i) for (int j = i; j <= n; j += i) di[j].push_back(i); build(1, 0, n); for (int i = 1; i <= n; ++i) { for (int d : di[i]) modify(1, 0, n, 0, d - 1, phi[i / d]); dp[i][0] = INF; for (int j = 0; j < B - 1; ++j) dp[i][j + 1] = t[1].mn[j]; assign(1, 0, n, i, dp[i]); } } int main() { int qc; read(qc); prework(100000); while (qc--) { int n, k; read(n, k); if (k >= B) write(n); else write(dp[n][k]); endl(); } return 0; } |
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module vfabric_lsu_pipelined_read(clock, resetn,
i_addressin, i_addressin_valid, o_addressin_stall,
i_controlin, i_controlin_valid, o_controlin_stall,
avm_waitrequest, avm_address, avm_read, avm_readdata,
avm_byteenable, avm_readdatavalid, avm_burstcount,
o_dataout, o_dataout_valid, i_dataout_stall);
parameter AWIDTH = 32;
parameter WIDTH_BYTES = 4;
parameter DATA_WIDTH = 32;
parameter FIFO_DEPTH = 64;
input clock, resetn;
input [AWIDTH-1:0] i_addressin;
input i_controlin;
input i_addressin_valid, i_controlin_valid;
output o_addressin_stall, o_controlin_stall;
input avm_waitrequest;
output [31:0] avm_address;
output avm_read;
input avm_readdatavalid;
input [255:0] avm_readdata;
output [31:0] avm_byteenable;
output [5:0] avm_burstcount;
output [31:0] o_dataout;
input i_dataout_stall;
output o_dataout_valid;
wire [AWIDTH-1:0] addressin;
wire controlin;
wire fifo_a_valid_out;
wire fifo_c_valid_out;
wire are_fifos_valid;
wire are_fifos_stalled;
wire is_lsu_stalled;
vfabric_buffered_fifo fifo_a ( .clock(clock), .resetn(resetn), .data_in(i_addressin), .data_out(addressin), .valid_in(i_addressin_valid),
.valid_out( fifo_a_valid_out ), .stall_in(are_fifos_stalled), .stall_out(o_addressin_stall) );
defparam fifo_a.DATA_WIDTH = AWIDTH;
defparam fifo_a.DEPTH = FIFO_DEPTH;
vfabric_buffered_fifo fifo_c ( .clock(clock), .resetn(resetn), .data_in(i_controlin), .data_out(controlin), .valid_in(i_controlin_valid),
.valid_out( fifo_c_valid_out ), .stall_in(are_fifos_stalled), .stall_out(o_controlin_stall) );
defparam fifo_c.DATA_WIDTH = 1;
defparam fifo_c.DEPTH = FIFO_DEPTH;
assign are_fifos_valid = fifo_a_valid_out & fifo_c_valid_out;
assign are_fifos_stalled = ~(fifo_a_valid_out & fifo_c_valid_out & ~is_lsu_stalled);
lsu_pipelined_read lsu0 (.clk(clock), .reset(~resetn),
.i_address(addressin),
.i_valid(are_fifos_valid), .o_stall(is_lsu_stalled),
.o_readdata(o_dataout),
.o_valid(o_dataout_valid),
.i_stall(i_dataout_stall),
.i_burstcount(), //unconnected because we're not using burst mode
.avm_read(avm_read),
.avm_readdata(avm_readdata),
.avm_readdatavalid(avm_readdatavalid),
.avm_byteenable(avm_byteenable),
.avm_waitrequest(avm_waitrequest),
.avm_address(avm_address),
.avm_burstcount(avm_burstcount));
defparam lsu0.AWIDTH = AWIDTH;
defparam lsu0.WIDTH_BYTES=WIDTH_BYTES;
defparam lsu0.USEINPUTFIFO = 0;
defparam lsu0.USEBURST = 0;
endmodule
module vfabric_lsu_pipelined_write(clock, resetn,
i_addressin, i_addressin_valid, o_addressin_stall,
i_datain, i_datain_valid, o_datain_stall,
i_controlin, i_controlin_valid, o_controlin_stall,
avm_waitrequest,
avm_address, avm_write,
avm_writeack, avm_writedata, avm_byteenable,
o_dataout_valid, i_dataout_stall);
parameter AWIDTH = 32;
parameter WIDTH_BYTES = 4;
parameter DATA_WIDTH = 32;
parameter FIFO_DEPTH = 64;
input clock, resetn;
input [AWIDTH-1:0] i_addressin;
input [DATA_WIDTH-1:0] i_datain;
input i_controlin;
input i_addressin_valid, i_datain_valid, i_controlin_valid;
output o_addressin_stall, o_datain_stall, o_controlin_stall;
input avm_waitrequest;
output [31:0] avm_address;
output avm_write;
input avm_writeack;
output [255:0] avm_writedata;
output [31:0] avm_byteenable;
input i_dataout_stall;
output o_dataout_valid;
wire [AWIDTH-1:0] addressin;
wire [DATA_WIDTH-1:0] datain;
wire controlin;
wire fifo_a_valid_out;
wire fifo_b_valid_out;
wire fifo_c_valid_out;
wire are_fifos_valid;
wire are_fifos_stalled;
wire is_lsu_stalled;
vfabric_buffered_fifo fifo_a ( .clock(clock), .resetn(resetn), .data_in(i_addressin), .data_out(addressin), .valid_in(i_addressin_valid),
.valid_out( fifo_a_valid_out ), .stall_in(are_fifos_stalled), .stall_out(o_addressin_stall) );
defparam fifo_a.DATA_WIDTH = AWIDTH;
defparam fifo_a.DEPTH = FIFO_DEPTH;
vfabric_buffered_fifo fifo_b ( .clock(clock), .resetn(resetn), .data_in(i_datain), .data_out(datain), .valid_in(i_datain_valid),
.valid_out( fifo_b_valid_out ), .stall_in(are_fifos_stalled), .stall_out(o_datain_stall) );
defparam fifo_b.DATA_WIDTH = DATA_WIDTH;
defparam fifo_b.DEPTH = FIFO_DEPTH;
vfabric_buffered_fifo fifo_c ( .clock(clock), .resetn(resetn), .data_in(i_controlin), .data_out(controlin), .valid_in(i_controlin_valid),
.valid_out( fifo_c_valid_out ), .stall_in(are_fifos_stalled), .stall_out(o_controlin_stall) );
defparam fifo_c.DATA_WIDTH = 1;
defparam fifo_c.DEPTH = FIFO_DEPTH;
assign are_fifos_valid = fifo_a_valid_out & fifo_b_valid_out & fifo_c_valid_out;
assign are_fifos_stalled = ~(fifo_a_valid_out & fifo_b_valid_out
& fifo_c_valid_out & ~is_lsu_stalled);
lsu_pipelined_write lsu0 (.clk(clock), .reset(~resetn),
.i_address(addressin),
.i_writedata(datain),
.i_valid(are_fifos_valid), .o_stall(is_lsu_stalled),
.o_valid(o_dataout_valid),
.i_stall(i_dataout_stall),
.avm_write(avm_write),
.avm_writeack(avm_writeack),
.avm_writedata(avm_writedata),
.avm_byteenable(avm_byteenable),
.avm_waitrequest(avm_waitrequest),
.avm_address(avm_address));
defparam lsu0.AWIDTH = AWIDTH;
defparam lsu0.WIDTH_BYTES=WIDTH_BYTES;
defparam lsu0.USEINPUTFIFO = 0;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX = 1e6 + 6; long long int arr[2000005], brr[2000005], crr[2000005]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long int n, k, ans; cin >> n >> k; vector<pair<int, int> > v; for (int i = 1; i <= n; i++) cin >> arr[i]; while (k--) { int mx = 0; for (int i = 1; i <= n; i++) if (!mx || arr[i] > arr[mx]) mx = i; int mn = 0; for (int i = 1; i <= n; i++) if (!mn || arr[i] < arr[mn]) mn = i; if (mx == mn) { ans = 0; break; } arr[mx]--; arr[mn]++; v.push_back({mx, mn}); } int mx = 0; for (int i = 1; i <= n; i++) if (!mx || arr[i] > arr[mx]) mx = i; int mn = 0; for (int i = 1; i <= n; i++) if (!mn || arr[i] < arr[mn]) mn = i; ans = arr[mx] - arr[mn]; cout << ans << << v.size() << endl; for (int i = 0; i < v.size(); i++) cout << v[i].first << << v[i].second << endl; } |
#include <bits/stdc++.h> using namespace std; int a[505]; pair<int, int> query(set<int> s) { cout << ? ; for (auto e : s) { cout << e << ; } cout << endl; pair<int, int> res; cin >> res.first >> res.second; a[res.first] = res.second; return res; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, k; cin >> n >> k; set<int> s; for (int i = 1; i <= k; i++) { s.insert(i); } int mn = 1e9 + 1; for (int i = k + 1; i <= n; i++) { pair<int, int> u = query(s); mn = min(mn, u.second); s.erase(u.first); s.insert(i); } pair<int, int> u = query(s); mn = min(mn, u.second); s.erase(u.first); int ans = 1; set<int> t; int sm = 1e9 + 1, bg = 0; for (int i = 1; i <= n; i++) { if (a[i] != 0) { t.insert(i); sm = min(sm, a[i]); bg = max(bg, a[i]); } if (t.size() == 2) break; } set<int> ss; for (auto e : s) ss.insert(e); for (auto e : t) ss.insert(e); for (auto e : s) { ss.erase(e); auto u = query(ss); if (u.second == bg) ans++; ss.insert(e); } cout << ! << ans << endl; return 0; } |
//*****************************************************************************
// (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ecc_dec_fix.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v1_8_ecc_dec_fix
#(
parameter TCQ = 100,
parameter PAYLOAD_WIDTH = 64,
parameter CODE_WIDTH = 72,
parameter DATA_WIDTH = 64,
parameter DQ_WIDTH = 72,
parameter ECC_WIDTH = 8,
parameter nCK_PER_CLK = 4
)
(
/*AUTOARG*/
// Outputs
rd_data, ecc_single, ecc_multiple,
// Inputs
clk, rst, h_rows, phy_rddata, correct_en, ecc_status_valid
);
input clk;
input rst;
// Compute syndromes.
input [CODE_WIDTH*ECC_WIDTH-1:0] h_rows;
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rddata;
wire [2*nCK_PER_CLK*ECC_WIDTH-1:0] syndrome_ns;
genvar k;
genvar m;
generate
for (k=0; k<2*nCK_PER_CLK; k=k+1) begin : ecc_word
for (m=0; m<ECC_WIDTH; m=m+1) begin : ecc_bit
assign syndrome_ns[k*ECC_WIDTH+m] =
^(phy_rddata[k*DQ_WIDTH+:CODE_WIDTH] & h_rows[m*CODE_WIDTH+:CODE_WIDTH]);
end
end
endgenerate
reg [2*nCK_PER_CLK*ECC_WIDTH-1:0] syndrome_r;
always @(posedge clk) syndrome_r <= #TCQ syndrome_ns;
// Extract payload bits from raw DRAM bits and register.
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] ecc_rddata_ns;
genvar i;
generate
for (i=0; i<2*nCK_PER_CLK; i=i+1) begin : extract_payload
assign ecc_rddata_ns[i*PAYLOAD_WIDTH+:PAYLOAD_WIDTH] =
phy_rddata[i*DQ_WIDTH+:PAYLOAD_WIDTH];
end
endgenerate
reg [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] ecc_rddata_r;
always @(posedge clk) ecc_rddata_r <= #TCQ ecc_rddata_ns;
// Regenerate h_matrix from h_rows leaving out the identity part
// since we're not going to correct the ECC bits themselves.
genvar n;
genvar p;
wire [ECC_WIDTH-1:0] h_matrix [DATA_WIDTH-1:0];
generate
for (n=0; n<DATA_WIDTH; n=n+1) begin : h_col
for (p=0; p<ECC_WIDTH; p=p+1) begin : h_bit
assign h_matrix [n][p] = h_rows [p*CODE_WIDTH+n];
end
end
endgenerate
// Compute flip bits.
wire [2*nCK_PER_CLK*DATA_WIDTH-1:0] flip_bits;
genvar q;
genvar r;
generate
for (q=0; q<2*nCK_PER_CLK; q=q+1) begin : flip_word
for (r=0; r<DATA_WIDTH; r=r+1) begin : flip_bit
assign flip_bits[q*DATA_WIDTH+r] =
h_matrix[r] == syndrome_r[q*ECC_WIDTH+:ECC_WIDTH];
end
end
endgenerate
// Correct data.
output reg [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data;
input correct_en;
integer s;
always @(/*AS*/correct_en or ecc_rddata_r or flip_bits)
for (s=0; s<2*nCK_PER_CLK; s=s+1)
if (correct_en)
rd_data[s*PAYLOAD_WIDTH+:DATA_WIDTH] =
ecc_rddata_r[s*PAYLOAD_WIDTH+:DATA_WIDTH] ^
flip_bits[s*DATA_WIDTH+:DATA_WIDTH];
else rd_data[s*PAYLOAD_WIDTH+:DATA_WIDTH] =
ecc_rddata_r[s*PAYLOAD_WIDTH+:DATA_WIDTH];
// Copy raw payload bits if ECC_TEST is ON.
localparam RAW_BIT_WIDTH = PAYLOAD_WIDTH - DATA_WIDTH;
genvar t;
generate
if (RAW_BIT_WIDTH > 0)
for (t=0; t<2*nCK_PER_CLK; t=t+1) begin : copy_raw_bits
always @(/*AS*/ecc_rddata_r)
rd_data[(t+1)*PAYLOAD_WIDTH-1-:RAW_BIT_WIDTH] =
ecc_rddata_r[(t+1)*PAYLOAD_WIDTH-1-:RAW_BIT_WIDTH];
end
endgenerate
// Generate status information.
input ecc_status_valid;
output wire [2*nCK_PER_CLK-1:0] ecc_single;
output wire [2*nCK_PER_CLK-1:0] ecc_multiple;
genvar v;
generate
for (v=0; v<2*nCK_PER_CLK; v=v+1) begin : compute_status
wire zero = ~|syndrome_r[v*ECC_WIDTH+:ECC_WIDTH];
wire odd = ^syndrome_r[v*ECC_WIDTH+:ECC_WIDTH];
assign ecc_single[v] = ecc_status_valid && ~zero && odd;
assign ecc_multiple[v] = ecc_status_valid && ~zero && ~odd;
end
endgenerate
endmodule
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module packet32_tb();
wire [35:0] data;
wire src_rdy, dst_rdy;
wire clear = 0;
reg clk = 0;
reg reset = 1;
always #10 clk <= ~clk;
initial #1000 reset <= 0;
initial $dumpfile("packet32_tb.vcd");
initial $dumpvars(0,packet32_tb);
wire [31:0] total, crc_err, seq_err, len_err;
packet_generator32 pkt_gen (.clk(clk), .reset(reset), .clear(clear),
.data_o(data), .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy));
packet_verifier32 pkt_ver (.clk(clk), .reset(reset), .clear(clear),
.data_i(data), .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy),
.total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err));
endmodule // packet32_tb
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
//
// This is a copy of t_param.v with the parentheses around the module parameters
// removed.
module t (/*AUTOARG*/
// Inputs
clk
);
parameter PAR = 3;
m1 #PAR m1();
m3 #PAR m3();
mnooverride #10 mno();
input clk;
integer cyc=1;
reg [4:0] bitsel;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==0) begin
bitsel = 0;
if (PAR[bitsel]!==1'b1) $stop;
bitsel = 1;
if (PAR[bitsel]!==1'b1) $stop;
bitsel = 2;
if (PAR[bitsel]!==1'b0) $stop;
end
if (cyc==1) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module m1;
localparam PAR1MINUS1 = PAR1DUP-2-1;
localparam PAR1DUP = PAR1+2; // Check we propagate parameters properly
parameter PAR1 = 0;
m2 #PAR1MINUS1 m2 ();
endmodule
module m2;
parameter PAR2 = 10;
initial begin
$display("%x",PAR2);
if (PAR2 !== 2) $stop;
end
endmodule
module m3;
localparam LOC = 13;
parameter PAR = 10;
initial begin
$display("%x %x",LOC,PAR);
if (LOC !== 13) $stop;
if (PAR !== 3) $stop;
end
endmodule
module mnooverride;
localparam LOC = 13;
parameter PAR = 10;
initial begin
$display("%x %x",LOC,PAR);
if (LOC !== 13) $stop;
if (PAR !== 10) $stop;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; char a; int s, kh; int main() { while (cin >> a) { if (a == ( ) s++; else if (s > 0) { kh += 2; s--; } } cout << kh; } |
#include <bits/stdc++.h> using namespace std; const int M = 50 * 1000 * 1000, LG = 40; int get(long long x, int y) { return (x >> y) & 1; } int main() { int n, p; cin >> n >> p; for (int i = 0; i < M; i++) { long long x = (long long)n - 1ll * p * i; if (x >= i && __builtin_popcount(x) <= i) { cout << i << endl; return 0; } } cout << -1 << endl; return 0; } |
//=================================================
//
// Hsiang-Yi Chung
// March 2016
//
// This Module is for estimating the
// magnitude of complex numbers.
//
// Formula for estimating magnitude:
// mag = max(|I|,|Q|) + 1/4*min(|I|,|Q|) - 1/16*max(|I|,|Q|)
//
//=================================================
//mag1 = magnitude(Y0 + Y1 * i)
//mag2 = magnitude(Y2 + Y3 * i)
module magnitude(Y0, Y1, Y2, Y3, mag1, mag2);
input [11:0] Y0, Y1, Y2, Y3;
output [11:0] mag1, mag2;
wire [11:0] max1, max2, min1, min2;
wire [11:0] Z0, Z1, Z2, Z3;
toPositive p1 (.in(Y0), .out(Z0));
toPositive p2 (.in(Y1), .out(Z1));
toPositive p3 (.in(Y2), .out(Z2));
toPositive p4 (.in(Y3), .out(Z3));
max m1 (.imagPart(Z1), .realPart(Z0), .maximun(max1));
max m2 (.imagPart(Z3), .realPart(Z2), .maximun(max2));
min m3 (.imagPart(Z1), .realPart(Z0), .minimum(min1));
min m4 (.imagPart(Z3), .realPart(Z2), .minimum(min2));
assign mag1 = max1 + (min1 >> 2) - (max1 >> 4);
assign mag2 = max2 + (min2 >> 2) - (max2 >> 4);
endmodule
module toPositive(
input [11:0] in,
output reg [11:0] out);
always @ * begin
if(in[11] == 1'b1)
out = ~in + 12'b1;
else
out = in;
end
endmodule
module max(
input [11:0] imagPart,
input [11:0] realPart,
output reg [11:0] maximun);
always @ * begin
if(imagPart > realPart)
maximun = imagPart;
else
maximun = realPart;
end
endmodule
module min(
input [11:0] imagPart,
input [11:0] realPart,
output reg [11:0] minimum);
always @ * begin
if(imagPart > realPart)
minimum = realPart;
else
minimum = imagPart;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct p { int x; int i; } a[200123]; int cmp(p a, p b) { if (a.x != b.x) return a.x < b.x; else return a.i < b.i; } int main() { int n; int i, j; scanf( %d , &n); for (i = 0; i < n; i++) { scanf( %d , &a[i].x); a[i].i = i; } sort(a, a + n, cmp); int mi = 0; long long y = 0; i = 1; while (i < n && a[i].x == a[0].x) { if (a[i].i - a[i - 1].i - 1 > mi) mi = a[i].i - a[i - 1].i - 1; i++; } if (a[0].i + n - a[i - 1].i - 1 > mi) mi = a[0].i + n - a[i - 1].i - 1; y = (long long)a[0].x * n + mi; printf( %lld n , y); return 0; } |
// file: dacclk_mmcm.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1___128.008______0.000______50.0______116.987_____95.328
// CLK_OUT2___128.008_____90.000______50.0______116.987_____95.328
// CLK_OUT3___128.008____180.000______50.0______116.987_____95.328
// CLK_OUT4___128.008____270.000______50.0______116.987_____95.328
// CLK_OUT5___256.017______0.000______50.0______102.681_____95.328
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________128.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "dacclk_mmcm,clk_wiz_v3_6,{component_name=dacclk_mmcm,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_ONCHIP,primtype_sel=MMCM_ADV,num_out_clk=5,clkin1_period=7.812,clkin2_period=10.000,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}" *)
module dacclk_mmcm
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
output CLK_OUT2,
output CLK_OUT3,
output CLK_OUT4,
output CLK_OUT5,
// Status and control signals
output LOCKED
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));
// Clocking primitive
//------------------------------------
// Instantiation of the MMCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire clkfbout;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1b_unused;
wire clkout2b_unused;
wire clkout3b_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCM_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.CLOCK_HOLD ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (8.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (8.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (8),
.CLKOUT1_PHASE (90.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKOUT2_DIVIDE (8),
.CLKOUT2_PHASE (180.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT2_USE_FINE_PS ("FALSE"),
.CLKOUT3_DIVIDE (8),
.CLKOUT3_PHASE (270.000),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKOUT3_USE_FINE_PS ("FALSE"),
.CLKOUT4_DIVIDE (4),
.CLKOUT4_PHASE (0.000),
.CLKOUT4_DUTY_CYCLE (0.500),
.CLKOUT4_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (7.812),
.REF_JITTER1 (0.010))
mmcm_adv_inst
// Output clocks
(.CLKFBOUT (clkfbout),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clkout0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout),
.CLKIN1 (clkin1),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (LOCKED),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (1'b0));
// Output buffering
//-----------------------------------
assign CLK_OUT1 = clkout0;
assign CLK_OUT2 = clkout1;
assign CLK_OUT3 = clkout2;
assign CLK_OUT4 = clkout3;
assign CLK_OUT5 = clkout4;
endmodule
|
#include <bits/stdc++.h> using namespace std; void upd(long long &x, long long y) { x += y; } struct node { int nxt; long long sta, v[10]; node() { nxt = 0; memset(v, 0, sizeof(v)); } }; struct state { vector<node> nodes; int head[100007]; state() { memset(head, -1, sizeof(head)); } size_t size() const { return nodes.size(); } void sum() { for (int i = 0; i < nodes.size(); i++) for (int j = 1; j <= 9; j++) upd(nodes[i].v[j], nodes[i].v[j - 1]); } void update(int at, long long key, long long v) { int tmp = key % 100007; for (int i = head[tmp]; i != -1; i = nodes[i].nxt) if (nodes[i].sta == key) { upd(nodes[i].v[at], v); return; } node now; now.nxt = head[tmp]; head[tmp] = nodes.size(); now.v[at] = v; now.sta = key; nodes.push_back(now); } long long find(int at, long long key) { int tmp = key % 100007; for (int i = head[tmp]; i != -1; i = nodes[i].nxt) if (nodes[i].sta == key) return nodes[i].v[at]; return 0; } } f[11][20]; long long c[2][20], bit[15]; bitset<200> vis[15], pre[200], tmp; struct big { int a[35], len; void read() { memset(a, 0, sizeof(a)); len = 0; char ch = getchar(); for (; ch < 0 || ch > 9 ; ch = getchar()) ; for (; ch >= 0 && ch <= 9 ; ch = getchar()) a[len++] = ch - 48; } long long mod() { long long ans = 0; for (int i = 0; i < len; i++) ans = (10ll * ans + a[i]) % 1000000000000000007ll; return ans; } void plus() { a[len - 1]++; for (int i = len - 1; i >= 1; i--) a[i - 1] += a[i] / 10, a[i] %= 10; if (a[0] > 9) { a[0] = 1; for (int i = 1; i <= len; i++) a[i] = 0; len++; } } } L, R; int sum[40], times = 0; void dfs(int dep, int cnt, int sum, long long msk) { int mx = sum + (18 - cnt) * 9; tmp = pre[mx >> 1]; if (sum >> 1) tmp ^= pre[(sum >> 1) - 1]; if ((vis[dep - 1] & tmp) == tmp) return; if (dep == 10) { for (int i = sum >> 1; i >= 0; i--) if (vis[dep - 1][i]) { int dif = sum - i - i; if (dif > 1) { ::sum[cnt]++; f[dif][0].update(0, msk, 1); } break; } return; } vis[dep] = vis[dep - 1]; dfs(dep + 1, cnt, sum, msk); for (; cnt < 18;) { vis[dep] |= vis[dep] << dep; dfs(dep + 1, ++cnt, sum += dep, msk += bit[dep]); } } long long solve(int dif, big lim) { long long ans = 0, msk = 0; int len = lim.len; state *F = f[dif]; for (int i = 0; i < len; i++) if (len - i > 18) { for (int j = 0; j < lim.a[i]; j++) ans += F[len - i - 1].find(9, msk); } else if (lim.a[i]) { ans += F[len - i].find(lim.a[i] - 1, msk); msk += bit[lim.a[i]]; } return ans; } long long solve2(big lim) { int len = lim.len; long long ans = 0; int part = 0; for (int i = 0; i < len; i++) { int odd = lim.a[i] >> 1, even = lim.a[i] - odd; ans += c[part][len - 1 - i] * odd + c[part ^ 1][len - 1 - i] * even; part ^= lim.a[i] & 1; } return ans; } inline long long read() { long long x = 0; char ch = getchar(); for (; ch < 0 || ch > 9 ; ch = getchar()) ; for (; ch >= 0 && ch <= 9 ; ch = getchar()) x = x * 10 - 48 + ch; return x; } int main() { pre[0][0] = 1; for (int i = 1; i <= 190; i++) pre[i] = pre[i - 1], pre[i][i] = 1; c[0][0] = 1; for (int i = 1; i <= 18; i++) c[0][i] = c[1][i] = 5ll * (c[0][i - 1] + c[1][i - 1]) % 1000000000000000007ll; bit[1] = 1; for (int i = 2; i < 10; i++) bit[i] = bit[i - 1] << 5; vis[0].set(0); dfs(1, 0, 0, 0); for (int i = 2; i < 10; i++) { f[i][0].sum(); for (int j = 0; j < 18; j++) { state &cur = f[i][j], &nxt = f[i][j + 1]; for (int id = 0, sz = cur.size(); id < sz; id++) { int cnt = j; long long way = cur.nodes[id].v[9]; long long msk = cur.nodes[id].sta, tmp = msk; for (int k = 1; k < 10; k++, tmp >>= 5) { int rem = tmp & 31; if (!rem) continue; cnt += rem; nxt.update(k, msk - bit[k], way); } if (cnt < 18) nxt.update(0, msk, way); } nxt.sum(); } } int Q = read(); while (Q--) { L.read(); R.read(); R.plus(); int k = read(); long long ans = R.mod() - L.mod(); if (!k) { ans -= solve2(R) - solve2(L); for (int i = 2; i < 10; i += 2) ans -= solve(i, R) - solve(i, L); } else for (int i = k + 1; i < 10; i++) ans -= solve(i, R) - solve(i, L); printf( %lld n , (ans % 1000000000000000007ll + 1000000000000000007ll) % 1000000000000000007ll); } return 0; } |
/// date:2016/3/3
/// engineer:ZhaiShaoMin
/// module name:upload_fsm_datapath
/// module function:combine fsm of upload and datapath of upload
module upload_fsm_datapath(//input
clk,
rst,
v_flits_in,
out_req_fifo_rdy_in,
en_inv_ids,
inv_ids_in,
flits_max_in,
head_flit,
addrhi,
addrlo,
// datahi1,
// datalo1,
// datahi2,
// datalo2,
// datahi3,
// datalo3,
// datahi4,
// datalo4,
//output
ctrl_out,
flit_out,
fsm_state,
v_flit_to_req_fifo
);
// input
input clk;
input rst;
input v_flits_in;
input out_req_fifo_rdy_in;
input en_inv_ids;
input [3:0] inv_ids_in;
input [3:0] flits_max_in;
input [15:0] head_flit;
input [15:0] addrhi;
input [15:0] addrlo;
/*input [15:0] datahi1;
//input [15:0] datalo1;
input [15:0] datahi2;
input [15:0] datalo2;
input [15:0] datahi3;
input [15:0] datalo3;
input [15:0] datahi4;
input [15:0] datalo4;
*/
//output
output [1:0] ctrl_out;
output [15:0] flit_out;
output [1:0] fsm_state;
output v_flit_to_req_fifo;
//nets of upload_datapath output
wire [3:0] inv_ids_reg_net;
wire [1:0] sel_cnt_invs_net;
wire [15:0] flit_out_net;
wire cnt_eq_max_net;
wire cnt_invs_eq_3_net;
wire cnt_eq_0_net;
//net of fsm_upload_flit output
wire dest_sel_net;
wire clr_max_net;
wire clr_inv_ids_net;
wire clr_sel_cnt_inv_net;
wire clr_sel_cnt_net;
wire inc_sel_cnt_net;
wire inc_sel_cnt_invs_net;
wire en_flit_max_in_net;
wire en_inv_ids_net;
FSM_upload_flit req_fsm_dut (// input
.clk(clk),
.rst(rst),
.en_for_reg(v_flits_in),
.out_req_fifo_rdy(out_req_fifo_rdy_in),
.cnt_invs_eq_3(cnt_invs_eq_3_net),
.cnt_eq_max(cnt_eq_max_net),
.head_flit(head_flit),
.inv_ids_reg(inv_ids_reg_net),
.sel_cnt_invs(sel_cnt_invs_net),
.sel_cnt_eq_0(cnt_eq_0_net),
// output
.en_inv_ids(en_inv_ids_net),
.en_flit_max_in(en_flit_max_in_net),
.inc_sel_cnt_invs(inc_sel_cnt_invs_net),
.inc_sel_cnt(inc_sel_cnt_net),
.ctrl(ctrl_out),
.clr_max(clr_max_net),
.clr_inv_ids(clr_inv_ids_net),
.clr_sel_cnt_inv(clr_sel_cnt_inv_net),
.clr_sel_cnt(clr_sel_cnt_net),
.dest_sel(dest_sel_net),
.fsm_state_out(fsm_state),
.en_flit_out(v_flit_to_req_fifo)
);
upload_datapath req_datapath_dut(// input
.clk(clk),
.rst(rst),
.clr_max(clr_max_net),
.clr_inv_ids(clr_inv_ids_net),
.clr_sel_cnt_inv(clr_sel_cnt_inv_net),
.clr_sel_cnt(clr_sel_cnt_net),
.inc_sel_cnt(inc_sel_cnt_net),
.inc_sel_cnt_inv(inc_sel_cnt_invs_net),
.en_flit_max_in(en_flit_max_in_net),
.en_for_reg(v_flits_in),
.en_inv_ids(en_inv_ids_net),
.inv_ids_in(inv_ids_in),
.dest_sel(dest_sel_net),
.flit_max_in(flits_max_in),
.head_flit(head_flit),
.addrhi(addrhi),
.addrlo(addrlo),
/* .datahi1(datahi1),
.datalo1(datalo1),
.datahi2(datahi2),
.datalo2(datalo2),
.datahi3(datahi3),
.datalo3(datalo3),
.datahi4(datahi4),
.datalo4(datalo4), */
//output
.flit_out(flit_out_net),
.cnt_eq_max(cnt_eq_max_net),
.cnt_invs_eq_3(cnt_invs_eq_3_net),
.cnt_eq_0(cnt_eq_0_net),
.inv_ids_reg_out(inv_ids_reg_net),
.sel_cnt_invs_out(sel_cnt_invs_net)
);
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O32A_M_V
`define SKY130_FD_SC_LP__O32A_M_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog wrapper for o32a with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o32a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o32a_m (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o32a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o32a_m (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o32a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O32A_M_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:05:40 09/06/2015
// Design Name:
// Module Name: Deco_Round_Mult
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Deco_Round_Mult(
input wire [1:0] round_mode,
input wire or_info, //23 less significant bits from the product of significands
input wire xor_info, //Brings information about the sign of the operation
output reg ctrl //control signal mux --- control of the rounded significand
);
wire round_ok;
always @*
case ({xor_info,or_info,round_mode})
// Round to infinity - (Round down)
//1'b0: Let pass the significand without rounding
//1'b1: Let pass the rounded significand
//Round towards - infinity
//0: positive number ; 01: Round towards - inifnity ; XX rounding bits
//Positive Number
//xor, or, round
4'b0101: ctrl <= 1'b0;
//Negative Number
4'b1101: ctrl <= 1'b1;
//Round towards + infinity
//Positive Number
4'b0110: ctrl <= 1'b1;
//Negative Number
4'b1110: ctrl <= 1'b0;
default: ctrl <= 1'b0; //Truncation
endcase
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 200005, INF = 1 << 31; struct A { int x, w; } a[MAXN]; int b[MAXN], c[MAXN], n, d[MAXN], f[MAXN]; bool cmp(const A &x, const A &y) { return x.x < y.x; } int main() { scanf( %d , &n); for (int i = 0; i < n; ++i) scanf( %d%d , &a[i].x, &a[i].w); sort(a, a + n, cmp); memset(f, 0, sizeof f); memset(d, 0x7f, sizeof d); for (int i = 0; i < n; ++i) { b[i] = a[i].x - a[i].w; c[i] = a[i].x + a[i].w; } int ans = 0; for (int i = 0; i < n; ++i) { int t = upper_bound(d + 1, d + ans + 1, b[i]) - d - 1; d[t + 1] = min(c[i], d[t + 1]); if (ans == t) ans = t + 1; } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int N, ans[(int)20 + 7][(int)20 + 7], a[500]; set<pair<int, int> > st; map<int, int> mp; int main() { ios::sync_with_stdio(false); cin >> N; for (int i = 0; i < N * N; i++) { cin >> a[i]; mp[a[i]]++; } int idx = -1; map<int, int>::iterator itt = mp.begin(); while (itt != mp.end()) { st.insert({itt->second, itt->first}); itt++; } memset(ans, -1, sizeof ans); for (int i = 0; i < N; i++) { for (int j = 0; j < N; j++) { if (ans[i][j] != -1) continue; if (!st.size()) return cout << NO , 0; if (N % 2 && i == N / 2 || j == N / 2) { continue; } set<pair<int, int> >::iterator it = st.lower_bound({4, -1}); ; int c = (*it).first, n = (*it).second; if (it == st.end()) return cout << NO , 0; st.erase(it); c -= 4; if (c < 0) return cout << NO , 0; ans[i][j] = n; ans[i][N - j - 1] = n; ans[N - i - 1][j] = n; ans[N - i - 1][N - j - 1] = n; if (c) st.insert({c, n}); } } for (int i = 0; i < N; i++) { for (int j = 0; j < N; j++) { if (ans[i][j] != -1) continue; if (N % 2 && i == N / 2 && j == N / 2) continue; if (N % 2 && i == N / 2) { set<pair<int, int> >::iterator it = st.lower_bound({2, -1}); if (it == st.end()) return cout << NO , 0; st.erase(it); int c = (*it).first, n = (*it).second; c -= 2; if (c < 0) return cout << NO , 0; ans[i][j] = n; ans[i][N - j - 1] = n; if (c) st.insert({c, n}); } else if (N % 2 && j == N / 2) { set<pair<int, int> >::iterator it = st.lower_bound({2, -1}); ; if (it == st.end()) return cout << NO , 0; st.erase(it); int c = (*it).first, n = (*it).second; c -= 2; if (c < 0) return cout << NO , 0; ans[i][j] = n; ans[N - i - 1][j] = n; if (c) st.insert({c, n}); } } } if (N % 2) { ans[N / 2][N / 2] = (*st.begin()).second; } cout << YES << endl; for (int i = 0; i < N; i++, cout << endl) for (int j = 0; j < N; j++) cout << ans[i][j] << ; return 0; } |
#include <bits/stdc++.h> using namespace std; vector<long long> erat; long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } long long nd(long long a) { map<long long, long long> m; while (a != 1) { ++m[erat[a]]; a /= erat[a]; } long long count = 1; for (auto e : m) count *= e.second + 1; return count; } int main() { vector<vector<vector<bool> > > count( 8, vector<vector<bool> >(8, vector<bool>(8, true))); count[1][7][6] = false; count[3][7][6] = false; count[5][3][6] = false; count[5][3][7] = false; count[5][7][6] = false; count[7][2][5] = false; count[7][3][4] = false; count[7][3][5] = false; count[7][3][6] = false; count[7][3][7] = false; count[7][6][5] = false; count[7][7][5] = false; count[7][7][6] = false; ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); erat = vector<long long>(1e5 + 1, 1); erat[0] = erat[1] = 1; for (long long i = 2; i <= 1e5; ++i) { if (erat[i] == 1) { erat[i] = i; for (long long j = i * i; j <= 1e5; j += i) { if (erat[j] == 1) erat[j] = i; } } } long long t; cin >> t; while (t--) { long long a, b, c; cin >> a >> b >> c; long long d = gcd(a, b); long long e = gcd(a, c); long long f = gcd(b, c); long long g = gcd(d, c); a = nd(a); b = nd(b); c = nd(c); d = nd(d); e = nd(e); f = nd(f); g = nd(g); d -= g, e -= g, f -= g; a -= d + e + g, b -= d + f + g, c -= e + f + g; vector<long long> v(8); v[1] = a, v[2] = b, v[3] = d, v[4] = c, v[5] = e, v[6] = f, v[7] = g; long long total = 0; for (int i = 0; i < 4; ++i) { for (int j = 0; j < 4; ++j) { for (int k = 0; k < 4; ++k) { int l = 2 * i + 1; int m = 2 + j; if (j >= 2) m += 2; int p = 4 + k; if (count[l][m][p]) { if (l == m) { if (m == p) total += v[l] * (v[m] + 1) * (v[p] + 2) / 6; else total += v[l] * (v[m] + 1) * v[p] / 2; } else if (l == p or m == p) total += v[l] * v[m] * (v[p] + 1) / 2; else total += v[l] * v[m] * v[p]; } } } } cout << total << endl; } } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t--) { int n; cin >> n; string s; cin >> s; int cnt = 0; reverse(s.begin(), s.end()); cnt += (s[0] - 0 ); for (int i = 1; i < n; i++) { if (s[i] != 0 ) cnt = cnt + 1 + (s[i] - 0 ); } cout << cnt << n ; } } |
#include <bits/stdc++.h> using namespace std; #define endl n #define ll long long #define fr(i,s,e) for(ll i=s;i<=e;i++) #define rfr(i,s,e) for(ll i=s;i>=e;i--) #define f(x,m) for(auto x : m) #define ff first #define ss second #define pb push_back #define pp pop_back #define pf push_front #define ppf pop_front #define m_p make_pair #define mod 1000000007 #define TIME cerr<< Time Taken: <<(float)clock()/CLOCKS_PER_SEC*1000<< ms <<endl const ll INF = (1LL << 60) - 1; int main() { #ifndef ONLINE_JUDGE freopen( ../input-output/input.txt , r , stdin); freopen( ../input-output/output.txt , w , stdout); #endif ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin>>t; while(t--){ ll r,b,d; cin>>r>>b>>d; int noPackets=min(r,b); r=max(r,b)-min(r,b); // cout<<r<< ; if(noPackets==0){ cout<< NO n ; continue; } ll maxdiff=r/noPackets; if(r%noPackets) maxdiff++; // cout<<maxdiff<<endl; if(maxdiff<=d) cout<< YES n ; else cout<< NO n ; } TIME; return 0; } |
`define CYCLE_TIME 50
`include "StateTable.v"
module Cache_TestBench;
integer i, outfile, outfile2, counter;
parameter flush_cycle = 300;
reg clk, rst, start;
reg flag;
reg [26:0] address;
reg [23:0] tag;
reg [4:0] index;
wire [256-1:0] mem_cpu_data;
wire mem_cpu_ack;
wire [256-1:0] cpu_mem_data;
wire [32-1:0] cpu_mem_addr;
wire cpu_mem_enable;
wire cpu_mem_write;
always #(`CYCLE_TIME/2)
clk = ~clk;
CPU CPU(
.clk (clk),
.rst (rst),
.start (start),
// Interface to external memory.
.ext_mem_addr (cpu_mem_addr),
.ext_mem_data_i (mem_cpu_data),
.ext_mem_cs (cpu_mem_enable),
.ext_mem_we (cpu_mem_write),
.ext_mem_data_o (cpu_mem_data),
.ext_mem_ack (mem_cpu_ack)
);
Data_Memory Data_Memory
(
.clk_i (clk),
.rst_i (rst),
.addr_i (cpu_mem_addr),
.data_i (cpu_mem_data),
.enable_i (cpu_mem_enable),
.write_i (cpu_mem_write),
.ack_o (mem_cpu_ack),
.data_o (mem_cpu_data)
);
/*
// External memory, 16KB.
DRAM #(.data_width(256), .mem_size(2048), .delay(10)) Data_Memory (
.clk (clk),
// Interface to the CPU.
.addr_i (cpu_mem_addr),
.data_i (cpu_mem_data),
.cs (cpu_mem_enable),
.we (cpu_mem_write),
.ack (mem_cpu_ack),
.data_o (mem_cpu_data)
);
*/
initial begin
counter = 1;
// initialize data memory (16KB)
for(i=0; i<512; i=i+1) begin
Data_Memory.memory[i] = 256'b0;
end
// initialize cache memory (1KB)
for(i=0; i<32; i=i+1) begin
CPU.L1Cache.dcache_tag_sram.memory[i] = 24'b0;
CPU.L1Cache.dcache_data_sram.memory[i] = 256'b0;
end
// Load instructions into instruction memory
$readmemb(".\\dat\\cache_instruction.txt", CPU.InstrMem.memory);
// Open output file
outfile = $fopen(".\\dat\\output.txt") | 1;
outfile2 = $fopen(".\\dat\\cache.txt") | 1;
// Set Input n into data memory at 0x00
Data_Memory.memory[0] = 256'h5; // n = 5 for example
/*
clk = 0;
rst = 1;
start = 0;
#(`CYCLE_TIME/8)
rst = 0;
#(`CYCLE_TIME/8)
start = 1;
#(`CYCLE_TIME/8)
rst = 1;
*/
clk = 0;
rst = 0;
start = 0;
#(`CYCLE_TIME/4)
rst = 1;
start = 1;
end
always @ (posedge clk) begin
// Store cache to memory.
if(counter > flush_cycle)
$stop;
else if(counter == flush_cycle) begin
$fdisplay(outfile, "Flush Cache! \n");
for(i=0; i<32; i=i+1) begin
tag = CPU.L1Cache.dcache_tag_sram.memory[i];
index = i;
address = {tag[21:0], index};
Data_Memory.memory[address] = CPU.L1Cache.dcache_data_sram.memory[i];
end
end
$fdisplay(outfile, "cycle = %d, Start = %b", counter, start);
$fdisplay(outfile, "PC = %d", CPU.PC.addr_o);
// Dump the registers.
$fdisplay(outfile, "RegFiles");
$fdisplay(outfile, "R0(r0) = %h, R8 (t0) = %h, R16(s0) = %h, R24(t8) = %h", CPU.RegFiles.register[0], CPU.RegFiles.register[8] , CPU.RegFiles.register[16], CPU.RegFiles.register[24]);
$fdisplay(outfile, "R1(at) = %h, R9 (t1) = %h, R17(s1) = %h, R25(t9) = %h", CPU.RegFiles.register[1], CPU.RegFiles.register[9] , CPU.RegFiles.register[17], CPU.RegFiles.register[25]);
$fdisplay(outfile, "R2(v0) = %h, R10(t2) = %h, R18(s2) = %h, R26(k0) = %h", CPU.RegFiles.register[2], CPU.RegFiles.register[10], CPU.RegFiles.register[18], CPU.RegFiles.register[26]);
$fdisplay(outfile, "R3(v1) = %h, R11(t3) = %h, R19(s3) = %h, R27(k1) = %h", CPU.RegFiles.register[3], CPU.RegFiles.register[11], CPU.RegFiles.register[19], CPU.RegFiles.register[27]);
$fdisplay(outfile, "R4(a0) = %h, R12(t4) = %h, R20(s4) = %h, R28(gp) = %h", CPU.RegFiles.register[4], CPU.RegFiles.register[12], CPU.RegFiles.register[20], CPU.RegFiles.register[28]);
$fdisplay(outfile, "R5(a1) = %h, R13(t5) = %h, R21(s5) = %h, R29(sp) = %h", CPU.RegFiles.register[5], CPU.RegFiles.register[13], CPU.RegFiles.register[21], CPU.RegFiles.register[29]);
$fdisplay(outfile, "R6(a2) = %h, R14(t6) = %h, R22(s6) = %h, R30(s8) = %h", CPU.RegFiles.register[6], CPU.RegFiles.register[14], CPU.RegFiles.register[22], CPU.RegFiles.register[30]);
$fdisplay(outfile, "R7(a3) = %h, R15(t7) = %h, R23(s7) = %h, R31(ra) = %h", CPU.RegFiles.register[7], CPU.RegFiles.register[15], CPU.RegFiles.register[23], CPU.RegFiles.register[31]);
// Dump the data memory.
$fdisplay(outfile, "Data Memory: 0x0000 = %h", Data_Memory.memory[0]);
$fdisplay(outfile, "Data Memory: 0x0020 = %h", Data_Memory.memory[1]);
$fdisplay(outfile, "Data Memory: 0x0040 = %h", Data_Memory.memory[2]);
$fdisplay(outfile, "Data Memory: 0x0060 = %h", Data_Memory.memory[3]);
$fdisplay(outfile, "Data Memory: 0x0080 = %h", Data_Memory.memory[4]);
$fdisplay(outfile, "Data Memory: 0x00A0 = %h", Data_Memory.memory[5]);
$fdisplay(outfile, "Data Memory: 0x00C0 = %h", Data_Memory.memory[6]);
$fdisplay(outfile, "Data Memory: 0x00E0 = %h", Data_Memory.memory[7]);
$fdisplay(outfile, "Data Memory: 0x0400 = %h", Data_Memory.memory[32]);
$fdisplay(outfile, "\n");
// Print the status of data cache.
// print Data Cache Status
if(CPU.L1Cache.p1_stall_o && CPU.L1Cache.state==0) begin
if(CPU.L1Cache.sram_dirty) begin
if(CPU.L1Cache.p1_MemWrite_i)
$fdisplay(outfile2, "Cycle: %d, Write Miss, Address: %h, Write Data: %h (Write Back!)", counter, CPU.L1Cache.p1_addr_i, CPU.L1Cache.p1_data_i);
else if(CPU.L1Cache.p1_MemRead_i)
$fdisplay(outfile2, "Cycle: %d, Read Miss , Address: %h, Read Data : %h (Write Back!)", counter, CPU.L1Cache.p1_addr_i, CPU.L1Cache.p1_data_o);
end
else begin
if(CPU.L1Cache.p1_MemWrite_i)
$fdisplay(outfile2, "Cycle: %d, Write Miss, Address: %h, Write Data: %h", counter, CPU.L1Cache.p1_addr_i, CPU.L1Cache.p1_data_i);
else if(CPU.L1Cache.p1_MemRead_i)
$fdisplay(outfile2, "Cycle: %d, Read Miss , Address: %h, Read Data : %h", counter, CPU.L1Cache.p1_addr_i, CPU.L1Cache.p1_data_o);
end
flag = 1'b1;
end
else if(!CPU.L1Cache.p1_stall_o) begin
if(!flag) begin
if(CPU.L1Cache.p1_MemWrite_i)
$fdisplay(outfile2, "Cycle: %d, Write Hit , Address: %h, Write Data: %h", counter, CPU.L1Cache.p1_addr_i, CPU.L1Cache.p1_data_i);
else if(CPU.L1Cache.p1_MemRead_i)
$fdisplay(outfile2, "Cycle: %d, Read Hit , Address: %h, Read Data : %h", counter, CPU.L1Cache.p1_addr_i, CPU.L1Cache.p1_data_o);
end
flag = 1'b0;
end
counter = counter+1;
end
endmodule
|
#include <bits/stdc++.h> int map[2001][2001] = {0}; int ans[2001] = {0}; int n, m, k; char ss[2001]; void show() { int i, j; for (i = 0; i < n; i++) { for (j = 0; j < m; j++) { printf( %d , map[i][j]); } printf( n ); } } int main() { int i, j, k; scanf( %d %d %d , &n, &m, &k); for (i = 0; i < n; i++) { scanf( %s , ss); for (j = 0; j < m; j++) { if (ss[j] == . ) { map[i][j] = 0; } else if (ss[j] == L ) { map[i][j] = 1; } else if (ss[j] == R ) { map[i][j] = 2; } else if (ss[j] == U ) { map[i][j] = 4; } else { map[i][j] = 8; } } } for (i = 0; i < n; i++) { for (j = 0; j < m; j++) { if (map[i][j] == 1) { if (i <= j) ans[j - i]++; } else if (map[i][j] == 2) { if (i < m - j) ans[i + j]++; } else if (map[i][j] == 4) { if (!(i & 1)) ans[j]++; } else if (map[i][j] == 8) { } } } printf( %d , ans[0]); for (i = 1; i < m; i++) { printf( %d , ans[i]); } printf( n ); return 0; } |
`timescale 1ns / 1ps
// -*- Mode: Verilog -*-
// Filename : alucontrol.v
// Description : Description of the ALU control logic for our simplified MIPS processor.
// Author : Pallav Gupta
// Created On : Wed Oct 22 21:43:19 2008
// Last Modified On: Time-stamp: <2008-10-22 21:07:01 pgupta>
// Update Count : 0
// Status : Unknown, Use with caution!
module alucontrol(input [1:0] aluop, // alu op code
input [5:0] funct, // function code
output reg [2:0] alucontrol // generated control signals for the ALU
);
// FUNCT field definitions
parameter ADD = 6'b100000;
parameter SUB = 6'b100010;
parameter AND = 6'b100100;
parameter OR = 6'b100101;
parameter SLT = 6'b101010;
// The Synopsys full_case directives are given on each statement to tell the
// synthezizer that all the cases we care about are handled. This avoids
// needing a default that takes extra logic gate or implying a latch.
always @(*)
case (aluop) // synopsys full_case
2'b00: alucontrol = 3'b010; // add (for lb/sb/addi)
2'b01: alucontrol = 3'b110; // sub (for beq)
2'b10: case (funct) // synopsys full_case
ADD: alucontrol = 3'b010; // add (for add)
SUB: alucontrol = 3'b110; // sub (for sub)
AND: alucontrol = 3'b000; // logical and (for and)
OR: alucontrol = 3'b001; // logical or (for or)
SLT: alucontrol = 3'b111; // set on less (for slt)
// no other functions are legal (don't care)
endcase // case (funct)
// aluop = 11 is never given (don't care)
endcase // case (aluop)
endmodule // alucontrol
|
// --------------------------------------------------------------------
// Copyright (c) 2007 by Terasic Technologies Inc.
// --------------------------------------------------------------------
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// --------------------------------------------------------------------
//
// Terasic Technologies Inc
// 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
// HsinChu County, Taiwan
// 302
//
// web: http://www.terasic.com/
// email:
//
// --------------------------------------------------------------------
//
// Major Functions: D5M CCD_Capture
//
// --------------------------------------------------------------------
//
// Revision History :
// --------------------------------------------------------------------
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.0 :| Johnny FAN :| 07/07/09 :| Initial Revision
// --------------------------------------------------------------------
module CCD_Capture( oDATA,
oDVAL,
oX_Cont,
oY_Cont,
oFrame_Cont,
iDATA,
iFVAL,
iLVAL,
iSTART,
iEND,
iCLK,
iRST
);
input [11:0] iDATA;
input iFVAL;
input iLVAL;
input iSTART;
input iEND;
input iCLK;
input iRST;
output [11:0] oDATA;
output [15:0] oX_Cont;
output [15:0] oY_Cont;
output [31:0] oFrame_Cont;
output oDVAL;
reg Pre_FVAL;
reg mCCD_FVAL;
reg mCCD_LVAL;
reg [11:0] mCCD_DATA;
reg [15:0] X_Cont;
reg [15:0] Y_Cont;
reg [31:0] Frame_Cont;
reg mSTART;
parameter COLUMN_WIDTH = 1280;
assign oX_Cont = X_Cont;
assign oY_Cont = Y_Cont;
assign oFrame_Cont = Frame_Cont;
assign oDATA = mCCD_DATA;
assign oDVAL = mCCD_FVAL&mCCD_LVAL;
always@(posedge iCLK or negedge iRST)
begin
if(!iRST)
mSTART <= 0;
else
begin
if(iSTART)
mSTART <= 1;
if(iEND)
mSTART <= 0;
end
end
always@(posedge iCLK or negedge iRST)
begin
if(!iRST)
begin
Pre_FVAL <= 0;
mCCD_FVAL <= 0;
mCCD_LVAL <= 0;
X_Cont <= 0;
Y_Cont <= 0;
end
else
begin
Pre_FVAL <= iFVAL;
if( ({Pre_FVAL,iFVAL}==2'b01) && mSTART )
mCCD_FVAL <= 1;
else if({Pre_FVAL,iFVAL}==2'b10)
mCCD_FVAL <= 0;
mCCD_LVAL <= iLVAL;
if(mCCD_FVAL)
begin
if(mCCD_LVAL)
begin
if(X_Cont<(COLUMN_WIDTH-1))
X_Cont <= X_Cont+1;
else
begin
X_Cont <= 0;
Y_Cont <= Y_Cont+1;
end
end
end
else
begin
X_Cont <= 0;
Y_Cont <= 0;
end
end
end
always@(posedge iCLK or negedge iRST)
begin
if(!iRST)
Frame_Cont <= 0;
else
begin
if( ({Pre_FVAL,iFVAL}==2'b01) && mSTART )
Frame_Cont <= Frame_Cont+1;
end
end
always@(posedge iCLK or negedge iRST)
begin
if(!iRST)
mCCD_DATA <= 0;
else if (iLVAL)
mCCD_DATA <= iDATA;
else
mCCD_DATA <= 0;
end
reg ifval_dealy;
wire ifval_fedge;
reg [15:0] y_cnt_d;
always@(posedge iCLK or negedge iRST)
begin
if(!iRST)
y_cnt_d <= 0;
else
y_cnt_d <= Y_Cont;
end
always@(posedge iCLK or negedge iRST)
begin
if(!iRST)
ifval_dealy <= 0;
else
ifval_dealy <= iFVAL;
end
assign ifval_fedge = ({ifval_dealy,iFVAL}==2'b10)?1:0;
endmodule |
#include <bits/stdc++.h> using namespace std; const int N = 2e5; vector<int> g[N]; int mn[N]; int mx[N]; int ans; void dfs(int u, int p) { bool leaf = true; mn[u] = 1e9; mx[u] = -1e9; for (int v : g[u]) if (v != p) { dfs(v, u); leaf = false; mn[u] = min(mn[u], mn[v] + 1); mx[u] = max(mx[u], mx[v] + 1); } if (leaf) { mn[u] = 0; mx[u] = 0; } } void dfs2(int u, int p) { const int m = g[u].size(); bool ok = true; vector<int> hh; for (int v : g[u]) { if (mx[v] != mn[v]) ok = false; hh.push_back(mx[v] + 1); } if (ok) { sort(hh.begin(), hh.end()); hh.erase(unique(hh.begin(), hh.end()), hh.end()); if (hh.size() <= 2) { int len = 0; for (int e : hh) len += e; while (len % 2 == 0) len /= 2; ans = min(ans, len); } } vector<int> maxl(m); vector<int> maxr(m); vector<int> minl(m); vector<int> minr(m); maxl[0] = -1e9; minl[0] = 1e9; maxr[m - 1] = -1e9; minr[m - 1] = 1e9; for (int i = 1; i < m; i++) { maxl[i] = max(maxl[i - 1], mx[g[u][i - 1]] + 1); minl[i] = min(minl[i - 1], mn[g[u][i - 1]] + 1); } for (int i = m - 2; i >= 0; i--) { maxr[i] = max(maxr[i + 1], mx[g[u][i + 1]] + 1); minr[i] = min(minr[i + 1], mn[g[u][i + 1]] + 1); } for (int i = 0; i < m; i++) { int v = g[u][i]; if (v == p) continue; mn[u] = min(minl[i], minr[i]); mx[u] = max(maxl[i], maxr[i]); dfs2(v, u); } } int main() { int n; cin >> n; for (int i = 0; i < n - 1; i++) { int u, v; scanf( %d %d , &u, &v); u--; v--; g[u].push_back(v); g[v].push_back(u); } if (n == 2) { cout << 1 << endl; return 0; } for (int i = 0; i < n; i++) { if (g[i].size() >= 2) { ans = 1e9; dfs(i, -1); dfs2(i, -1); if (ans >= 1e8) ans = -1; cout << ans << endl; return 0; } } } |
///////////////////////////////////////////////////////////////////////////////
//
// Project: Aurora Module Generator version 2.2
//
// Date: $Date: 2004/11/08 16:19:31 $
// Tag: $Name: i+H-38+78751 $
// File: $RCSfile: standard_cc_module.ejava,v $
// Rev: $Revision: 1.1.6.2 $
//
// Company: Xilinx
// Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone
//
// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
// APPLICATION OR STANDARD, XILINX IS MAKING NO
// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE.
//
// (c) Copyright 2004 Xilinx, Inc.
// All rights reserved.
//
///////////////////////////////////////////////////////////////////////////////
//
// STANDARD CC MODULE
//
// Author: Nigel Gulstone
// Xilinx - Embedded Networking System Engineering Group
//
// Description: This module drives the Aurora module's Clock Compensation
// interface. Clock Compensation sequences are generated according
// to the requirements in the Aurora Protocol specification.
//
// This module supports Aurora Modules with any number of
// 4-byte lanes and no User Flow Control.
//
//
`timescale 1 ns / 10 ps
module STANDARD_CC_MODULE
(
//Clock Compensation Control Interface
WARN_CC,
DO_CC,
//System Interface
DCM_NOT_LOCKED,
USER_CLK,
CHANNEL_UP
);
`define DLY #1
//***********************************Port Declarations*******************************
//Clock Compensation Control Interface
output WARN_CC;
output DO_CC;
//System Interface
input DCM_NOT_LOCKED;
input USER_CLK;
input CHANNEL_UP;
//**************************** External Register Declarations*************************
reg WARN_CC;
reg DO_CC;
//************************** Internal Register Declarations **************************
reg [0:7] prepare_count_r;
reg [0:5] cc_count_r;
reg reset_r;
reg [0:11] count_13d_srl_r;
reg count_13d_flop_r;
reg [0:14] count_16d_srl_r;
reg count_16d_flop_r;
reg [0:10] count_12d_srl_r;
reg count_12d_flop_r;
//*********************************Wire Declarations**********************************
wire start_cc_c;
wire inner_count_done_r;
wire middle_count_done_c;
wire cc_idle_count_done_c;
//*********************************Main Body of Code**********************************
//________________________Clock Correction State Machine__________________________
// The clock correction state machine is a counter with three sections. The first
// section counts out the idle period before a clock correction occurs. The second
// section counts out a period when NFC and UFC operations should not be attempted
// because they will not be completed. The last section counts out the cycles of
// the clock correction sequence.
// The inner count for the CC counter counts to 13. It is implemented using
// an SRL16 and a flop
// The SRL counts 12 bits of the count
always @(posedge USER_CLK)
count_13d_srl_r <= `DLY {count_13d_flop_r, count_13d_srl_r[0:10]};
// The inner count is done when a 1 reaches the end of the SRL
assign inner_count_done_r = count_13d_srl_r[11];
// The flop extends the shift register to 13 bits for counting. It is held at
// zero while channel up is low to clear the register, and is seeded with a
// single 1 when channel up transitions from 0 to 1
always @(posedge USER_CLK)
if(~CHANNEL_UP)
count_13d_flop_r <= `DLY 1'b0;
else if(CHANNEL_UP && reset_r)
count_13d_flop_r <= `DLY 1'b1;
else
count_13d_flop_r <= `DLY inner_count_done_r;
// The middle count for the CC counter counts to 16. Its count increments only
// when the inner count is done. It is implemented using an SRL16 and a flop
// The SRL counts 15 bits of the count. It is enabled only when the inner count
// is done
always @(posedge USER_CLK)
if(inner_count_done_r|| !CHANNEL_UP)
count_16d_srl_r <= `DLY {count_16d_flop_r, count_16d_srl_r[0:13]};
// The middle count is done when a 1 reaches the end of the SRL and the inner
// count finishes
assign middle_count_done_c = inner_count_done_r && count_16d_srl_r[14];
// The flop extends the shift register to 16 bits for counting. It is held at
// zero while channel up is low to clear the register, and is seeded with a
// single 1 when channel up transitions from 0 to 1
always @(posedge USER_CLK)
if(~CHANNEL_UP)
count_16d_flop_r <= `DLY 1'b0;
else if(CHANNEL_UP && reset_r)
count_16d_flop_r <= `DLY 1'b1;
else if(inner_count_done_r)
count_16d_flop_r <= `DLY middle_count_done_c;
// The outer count (aka the cc idle count) is done when it reaches 12. Its count
// increments only when the middle count is done. It is implemented with an SRL16
// and a flop
// The SRL counts 11 bits of the count. It is enabled only when the middle count is
// done
always @(posedge USER_CLK)
if(middle_count_done_c || !CHANNEL_UP)
count_12d_srl_r <= `DLY {count_12d_flop_r, count_12d_srl_r[0:9]};
// The cc idle count is done when a 1 reaches the end of the SRL and the middle count finishes
assign cc_idle_count_done_c = middle_count_done_c & count_12d_srl_r[10];
// The flop extends the shift register to 12 bits for counting. It is held at
// zero while channel up is low to clear the register, and is seeded with a single
// 1 when channel up transitions from 0 to 1
always @(posedge USER_CLK)
if(~CHANNEL_UP)
count_12d_flop_r <= `DLY 1'b0;
else if(CHANNEL_UP && reset_r)
count_12d_flop_r <= `DLY 1'b1;
else if(middle_count_done_c)
count_12d_flop_r <= `DLY cc_idle_count_done_c;
// For simulation, initialize prepare count to all zeros to simulate an SRL16
// after configuration. The circuit will also work is the init value includes
// ones.
initial
prepare_count_r = 8'b00000000;
// Because UFC and CC sequences are not allowed to preempt one another, there
// there is a warning signal to indicate an impending CC sequence. This signal
// is used to prevent UFC messages from starting.
// For 1 lane, we use a 4-cycle count.
always @(posedge USER_CLK)
prepare_count_r <= `DLY {4'd0,cc_idle_count_done_c,prepare_count_r[4:6]};
// The state machine stays in the prepare_cc state from when the cc idle
// count finishes, to when the prepare count has finished. While in this
// state, UFC operations cannot start, which prevents them from having to
// be pre-empted by CC sequences.
always @(posedge USER_CLK)
if(!CHANNEL_UP) WARN_CC <= `DLY 1'b0;
else if(cc_idle_count_done_c) WARN_CC <= `DLY 1'b1;
else if(prepare_count_r[7]) WARN_CC <= `DLY 1'b0;
// For simulation, init to zeros, to simulate an SRL after configuration. The circuit
// will also operate if the SRL is not initialized to all zeros
initial
cc_count_r = 6'b000000;
// Track the state of channel up on the previous cycle. We use this signal to determine
// when to seed the shift register counters with ones
always @(posedge USER_CLK)
reset_r <= `DLY !CHANNEL_UP;
//Do a CC after CHANNEL_UP is asserted or CC_warning is complete.
assign start_cc_c = prepare_count_r[7] || (CHANNEL_UP && reset_r);
// This SRL counter keeps track of the number of cycles spent in the CC
// sequence. It starts counting when the prepare_cc state ends, and
// finishes counting after 3 cycles have passed.
always @(posedge USER_CLK)
cc_count_r <= `DLY {3'b000,(!CHANNEL_UP|prepare_count_r[7]),cc_count_r[3:4]};
// The TX_LL module stays in the do_cc state for 3 cycles. It starts
// when the prepare_cc state ends.
always @(posedge USER_CLK)
if(!CHANNEL_UP) DO_CC <= `DLY 1'b0;
else if(start_cc_c) DO_CC <= `DLY 1'b1;
else if(cc_count_r[5]) DO_CC <= `DLY 1'b0;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long int N = 60 + 10, M = (1 << 16) + 10, MOD = 1e9 + 7, INF = 2e9 + 10; const long double PI = acos(-1); int n, a[N], in[N], fac[N], msk[N], all; long long int dp[M][N], ans = 1; vector<int> adj[N], S, T; bool mrk[N], ad[N][N]; long long int Power(long long int x, long long int y) { if (y == 0) { return 1ll; } return ((y % 2 ? x : 1) * Power((x * x) % MOD, y / 2)) % MOD; } void Dfs(int u) { mrk[u] = 1; if (in[u]) T.push_back(u); else S.push_back(u); for (int v : adj[u]) { if (!mrk[v]) { Dfs(v); } } return; } void Solve() { memset(dp, 0, sizeof(dp)); int t = T.size(), s = S.size(); if (t < 2) return; for (int i = 0; i < t; i++) { msk[i] = 0; for (int j = 0; j < s; j++) { if ((a[T[i]] % a[S[j]]) == 0) { msk[i] |= (1 << j); } } dp[msk[i]][1]++; } for (int k = 1; k < t; k++) { for (int mask = 1; mask < (1 << s); mask++) { int cnt = 0; for (int i = 0; i < t; i++) { if ((msk[i] | mask) == mask) { cnt++; } else if (0 < (msk[i] & mask)) { dp[mask | msk[i]][k + 1] += dp[mask][k]; dp[mask | msk[i]][k + 1] %= MOD; } } if (k < cnt) { dp[mask][k + 1] += (cnt - k) * dp[mask][k]; dp[mask][k + 1] %= MOD; } } } ans = (ans * dp[(1 << s) - 1][t]) % MOD; ans = (ans * Power(fac[t - 1], MOD - 2)) % MOD; all += (t - 1); return; } void Dfs_All() { for (int i = 0; i < n; i++) { if (!mrk[i]) { Dfs(i); Solve(); S.clear(); T.clear(); } } return; } int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); fac[0] = 1; for (int i = 1; i < N; i++) { fac[i] = (fac[i - 1] * i) % MOD; } cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; for (int j = 0; j < i; j++) { int u = i, v = j; if (a[v] < a[u]) swap(u, v); if ((a[v] % a[u]) == 0) { adj[u].push_back(v); adj[v].push_back(u); in[v]++; } } } Dfs_All(); ans = (ans * fac[all]) % MOD; cout << ans << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; inline int read() { int x = 0; bool t = false; char ch = getchar(); while ((ch < 0 || ch > 9 ) && ch != - ) ch = getchar(); if (ch == - ) t = true, ch = getchar(); while (ch <= 9 && ch >= 0 ) x = x * 10 + ch - 48, ch = getchar(); return t ? -x : x; } int s[1010000], a[1010000], b[1010000], n, k; char ch[1010000]; bool vis[1010000]; int eql[1010000]; void output() { for (int i = 1; i <= k; ++i) if (!eql[i]) for (int j = 1; j <= k; ++j) if (!vis[j]) { eql[i] = j; vis[j] = true; break; } for (int i = 1; i <= k; ++i) putchar(eql[i] + 96); puts( ); } void clear() { for (int i = 1; i <= k; ++i) eql[i] = 0, vis[i] = false; } int main() { int T = read(); while (T--) { k = read(); scanf( %s , ch + 1); n = strlen(ch + 1); for (int i = 1; i <= n; ++i) s[i] = ch[i] - 96; scanf( %s , ch + 1); for (int i = 1; i <= n; ++i) a[i] = ch[i] - 96 - (i == n); scanf( %s , ch + 1); for (int i = 1; i <= n; ++i) b[i] = ch[i] - 96; clear(); int p = -1; for (int i = 1; i <= n; ++i) { if (i > 1) { if (eql[s[i - 1]] && eql[s[i - 1]] != a[i - 1]) break; if (!eql[s[i - 1]] && vis[a[i - 1]]) break; eql[s[i - 1]] = a[i - 1]; vis[a[i - 1]] = true; } if (eql[s[i]]) if (eql[s[i]] > a[i]) p = i; if (!eql[s[i]]) for (int j = a[i] + 1; j <= k; ++j) if (!vis[j]) { p = i; break; } } if (p == -1) puts( NO ); else { clear(); for (int i = 1; i < p; ++i) eql[s[i]] = a[i], vis[a[i]] = true; if (!eql[s[p]]) for (int i = a[p] + 1; i <= k; ++i) if (!vis[i]) { eql[s[p]] = i, vis[i] = true; break; } for (int i = p + 1; i <= n; ++i) if (!eql[s[i]]) for (int j = 1; j <= k; ++j) if (!vis[j]) { eql[s[i]] = j; vis[j] = true; break; } for (int i = 1; i <= n; ++i) s[i] = eql[s[i]]; bool chk = true; for (int i = 1; i <= n; ++i) if (s[i] > b[i]) { puts( NO ); chk = false; break; } else if (s[i] < b[i]) { puts( YES ); output(); chk = false; break; } if (chk) puts( YES ), output(); } } } |
#include <bits/stdc++.h> using namespace std; double low = 0, high = 0, mid = 0; int binary_sear(const vector<int>& v, int x) { while (1) { mid = floor((low + high) / 2); if (low > high) break; if (v[mid] == x) { return mid; break; } else if (v[mid] < x) { low = mid + 1; } else { high = mid - 1; } } return -1; } int binary(vector<int> v, int x) { mid = floor((low + high) / 2); cout << low << << mid << << high << endl; if (low > high) return -1; if (v[mid] == x) return mid; else if (v[mid] < x) { low = mid + 1; return binary(v, x); } else { high = mid - 1; return binary(v, x); } } string decToBinary(int n) { string s = {}; int i = 0; while (n > 0) { s += (n % 2) + 48; n = n / 2; i++; } reverse(s.begin(), s.end()); return s; } int main() { long long int a, b = 0, c = 1, n, m, mx = 0, mn = 0; vector<int> v; bool flag = true, flag2 = true; cin >> n; while (n--) { cin >> m; for (int i = 0; i < m; i++) { cin >> a; if (i == 0) { b = a; c = a; continue; } b += a; c ^= a; } cout << 2 << endl; cout << c << << c + b << endl; b = 0; c = 1; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 4040, inF = 1e9; int n, a, b, c, dp[N]; int main() { cin >> n >> a >> b >> c; dp[0] = 0; for (int i = 1; i <= n; i++) { dp[i] = -inF; if (i >= a) dp[i] = max(dp[i], dp[i - a] + 1); if (i >= b) dp[i] = max(dp[i], dp[i - b] + 1); if (i >= c) dp[i] = max(dp[i], dp[i - c] + 1); } cout << dp[n]; return 0; } |
#include <bits/stdc++.h> using namespace std; int n; long long a[1010]; int main() { cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; } long long k; cin >> k; cin >> k; cin >> k; long long x = (long long)a[2] * a[1] / k; long double dx = x; long long ans = (long long)(sqrt(x) + 0.005); cout << ans << ; for (int i = 1; i < n; i++) { cout << a[i] / ans << ; } return 0; } |
#include <bits/stdc++.h> using i64 = long long; std::vector<std::vector<int>> read_tree1(int v) { std::vector<std::vector<int>> graph(v); while (v-- > 1) { int x, y; std::cin >> x >> y; graph[x - 1].push_back(y - 1); graph[y - 1].push_back(x - 1); } return graph; } template <class T> std::pair<T, T> ext_euclid(T a, T b) { if (b == 0) { return {a > 0 ? +1 : -1, 0}; } else { auto res = ext_euclid(b, a % b); return {res.second, res.first - a / b * res.second}; } } template <class T> T mod_inv(T num, T mod) { num = (num % mod + mod) % mod; T res = ext_euclid(num, mod).first; return res < 0 ? res + mod : res; } int main() { std::ios::sync_with_stdio(0), std::cin.tie(0), std::cout.tie(0); const i64 MOD = 998244353; int n; std::cin >> n; auto tree = read_tree1(n); std::function<std::tuple<i64, i64, i64>(int, int)> dfs = [&](int cur, int prv) -> std::tuple<i64, i64, i64> { std::vector<std::tuple<i64, i64, i64>> nxts; for (int nxt : tree[cur]) if (nxt != prv) { nxts.push_back(dfs(nxt, cur)); } i64 prod = 1; for (const auto& [f, g, h] : nxts) { prod = prod * (f + h) % MOD; } i64 F = 1, G = 1, H = 0; for (const auto& [f, g, h] : nxts) { F = F * f % MOD; G = G * (f + h) % MOD; H = (H + g * mod_inv(f + h, MOD)) % MOD; } H = H * prod % MOD; F = (F + H) % MOD; return {F, G, H}; }; std::cout << std::get<0>(dfs(0, -1)) << n ; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFSTP_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__SDFSTP_FUNCTIONAL_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hdll__udp_mux_2to1.v"
`include "../../models/udp_dff_ps/sky130_fd_sc_hdll__udp_dff_ps.v"
`celldefine
module sky130_fd_sc_hdll__sdfstp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hdll__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SET);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFSTP_FUNCTIONAL_V |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx_buf_p4_odd.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
`include "sys.h"
`include "iop.h"
module pcx_buf_p4_odd(/*AUTOARG*/
// Outputs
arbpc1_pcxdp_grant_pa, arbpc1_pcxdp_q0_hold_pa_l,
arbpc1_pcxdp_qsel0_pa, arbpc1_pcxdp_qsel1_pa_l,
arbpc1_pcxdp_shift_px, arbpc3_pcxdp_grant_pa,
arbpc3_pcxdp_q0_hold_pa_l, arbpc3_pcxdp_qsel0_pa,
arbpc3_pcxdp_qsel1_pa_l, arbpc3_pcxdp_shift_px,
arbpc4_pcxdp_grant_pa, arbpc4_pcxdp_q0_hold_pa_l,
arbpc4_pcxdp_qsel0_pa, arbpc4_pcxdp_qsel1_pa_l,
arbpc4_pcxdp_shift_px,
// Inputs
arbpc1_pcxdp_grant_bufp3_pa_l, arbpc1_pcxdp_q0_hold_bufp3_pa,
arbpc1_pcxdp_qsel0_bufp3_pa_l, arbpc1_pcxdp_qsel1_bufp3_pa,
arbpc1_pcxdp_shift_bufp3_px_l, arbpc3_pcxdp_grant_bufp3_pa_l,
arbpc3_pcxdp_q0_hold_bufp3_pa, arbpc3_pcxdp_qsel0_bufp3_pa_l,
arbpc3_pcxdp_qsel1_bufp3_pa, arbpc3_pcxdp_shift_bufp3_px_l,
arbpc4_pcxdp_grant_bufp3_pa_l, arbpc4_pcxdp_q0_hold_bufp3_pa,
arbpc4_pcxdp_qsel0_bufp3_pa_l, arbpc4_pcxdp_qsel1_bufp3_pa,
arbpc4_pcxdp_shift_bufp3_px_l
);
output arbpc1_pcxdp_grant_pa;
output arbpc1_pcxdp_q0_hold_pa_l;
output arbpc1_pcxdp_qsel0_pa;
output arbpc1_pcxdp_qsel1_pa_l;
output arbpc1_pcxdp_shift_px;
output arbpc3_pcxdp_grant_pa;
output arbpc3_pcxdp_q0_hold_pa_l;
output arbpc3_pcxdp_qsel0_pa;
output arbpc3_pcxdp_qsel1_pa_l;
output arbpc3_pcxdp_shift_px;
output arbpc4_pcxdp_grant_pa;
output arbpc4_pcxdp_q0_hold_pa_l;
output arbpc4_pcxdp_qsel0_pa;
output arbpc4_pcxdp_qsel1_pa_l;
output arbpc4_pcxdp_shift_px;
input arbpc1_pcxdp_grant_bufp3_pa_l;
input arbpc1_pcxdp_q0_hold_bufp3_pa;
input arbpc1_pcxdp_qsel0_bufp3_pa_l;
input arbpc1_pcxdp_qsel1_bufp3_pa;
input arbpc1_pcxdp_shift_bufp3_px_l;
input arbpc3_pcxdp_grant_bufp3_pa_l;
input arbpc3_pcxdp_q0_hold_bufp3_pa;
input arbpc3_pcxdp_qsel0_bufp3_pa_l;
input arbpc3_pcxdp_qsel1_bufp3_pa;
input arbpc3_pcxdp_shift_bufp3_px_l;
input arbpc4_pcxdp_grant_bufp3_pa_l;
input arbpc4_pcxdp_q0_hold_bufp3_pa;
input arbpc4_pcxdp_qsel0_bufp3_pa_l;
input arbpc4_pcxdp_qsel1_bufp3_pa;
input arbpc4_pcxdp_shift_bufp3_px_l;
assign arbpc1_pcxdp_grant_pa = ~arbpc1_pcxdp_grant_bufp3_pa_l;
assign arbpc1_pcxdp_q0_hold_pa_l = ~arbpc1_pcxdp_q0_hold_bufp3_pa;
assign arbpc1_pcxdp_qsel0_pa = ~arbpc1_pcxdp_qsel0_bufp3_pa_l;
assign arbpc1_pcxdp_qsel1_pa_l = ~arbpc1_pcxdp_qsel1_bufp3_pa;
assign arbpc1_pcxdp_shift_px = ~arbpc1_pcxdp_shift_bufp3_px_l;
assign arbpc3_pcxdp_grant_pa = ~arbpc3_pcxdp_grant_bufp3_pa_l;
assign arbpc3_pcxdp_q0_hold_pa_l = ~arbpc3_pcxdp_q0_hold_bufp3_pa;
assign arbpc3_pcxdp_qsel0_pa = ~arbpc3_pcxdp_qsel0_bufp3_pa_l;
assign arbpc3_pcxdp_qsel1_pa_l = ~arbpc3_pcxdp_qsel1_bufp3_pa;
assign arbpc3_pcxdp_shift_px = ~arbpc3_pcxdp_shift_bufp3_px_l;
assign arbpc4_pcxdp_grant_pa = ~arbpc4_pcxdp_grant_bufp3_pa_l;
assign arbpc4_pcxdp_q0_hold_pa_l = ~arbpc4_pcxdp_q0_hold_bufp3_pa;
assign arbpc4_pcxdp_qsel0_pa = ~arbpc4_pcxdp_qsel0_bufp3_pa_l;
assign arbpc4_pcxdp_qsel1_pa_l = ~arbpc4_pcxdp_qsel1_bufp3_pa;
assign arbpc4_pcxdp_shift_px = ~arbpc4_pcxdp_shift_bufp3_px_l;
endmodule // pcx_buf_p4
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 100005; int N, M; int pwr[MAXN], jump[MAXN], cnt[MAXN]; int len; void recalc(int pos) { int nxt = pos + pwr[pos]; if (nxt < N && (nxt / len) == (pos / len)) { jump[pos] = jump[nxt]; cnt[pos] = cnt[nxt] + 1; } else { jump[pos] = nxt; cnt[pos] = 1; } } int main(int argc, char *argv[]) { scanf( %d%d , &N, &M); for (int i = 0, _i = N; i < _i; ++i) { scanf( %d , pwr + i); } len = (int)sqrt((double)N); for (int i = N - 1; i >= 0; i--) { recalc(i); } for (int i = 0, _i = M; i < _i; ++i) { int type, a; scanf( %d%d , &type, &a); --a; if (type) { int cur = a, ret = 0; while (true) { ret += cnt[cur]; if (jump[cur] >= N) break; cur = jump[cur]; } while (cur + pwr[cur] < N) cur += pwr[cur]; printf( %d %d n , cur + 1, ret); } else { int b; scanf( %d , &b); pwr[a] = b; int ablock = a / len; for (int i = a; i >= 0 && (i / len) == ablock; i--) recalc(i); } } return 0; } |
Subsets and Splits