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/*
* LatticeMico32
* JTAG Registers
*
* Copyright (C) 2010 Michael Walle
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
module jtag_cores (
input [7:0] reg_d,
input [2:0] reg_addr_d,
output reg_update,
output [7:0] reg_q,
output [2:0] reg_addr_q,
output jtck,
output jrstn
);
wire tck;
wire tdi;
wire tdo;
wire shift;
wire update;
wire reset;
jtag_tap jtag_tap (
.tck(tck),
.tdi(tdi),
.tdo(tdo),
.shift(shift),
.update(update),
.reset(reset)
);
reg [10:0] jtag_shift;
reg [10:0] jtag_latched;
always @(posedge tck or posedge reset)
begin
if(reset)
jtag_shift <= 11'b0;
else begin
if(shift)
jtag_shift <= {tdi, jtag_shift[10:1]};
else
jtag_shift <= {reg_d, reg_addr_d};
end
end
assign tdo = jtag_shift[0];
always @(posedge reg_update or posedge reset)
begin
if(reset)
jtag_latched <= 11'b0;
else
jtag_latched <= jtag_shift;
end
assign reg_update = update;
assign reg_q = jtag_latched[10:3];
assign reg_addr_q = jtag_latched[2:0];
assign jtck = tck;
assign jrstn = ~reset;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; cout << ceil(n / 2.0) - 1; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:01:56 04/23/2017
// Design Name: decrypt
// Module Name: C:/Users/vkoro/Final_Project/project/des/DES/decrypt_tb.v
// Project Name: DES
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: decrypt
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module decrypt_tb;
// Inputs
reg [63:0] message;
reg [63:0] DESkey;
reg clk;
reg reset;
reg enable;
reg ack;
integer clk_cnt;
parameter CLK_PERIOD = 10;
// Outputs
wire [63:0] decrypted;
wire done;
// Instantiate the Unit Under Test (UUT)
decrypt_dumb uut (
.message(message),
.DESkey(DESkey),
.decrypted(decrypted),
.done(done),
.clk(clk),
.reset(reset),
.enable(enable),
.ack(ack)
);
initial
begin : CLK_GENERATOR
clk = 0;
forever
begin
#(CLK_PERIOD/2) clk = ~clk;
end
end
initial
begin : RESET_GENERATOR
reset = 1;
#(10 * CLK_PERIOD) reset = 0;
end
initial
begin : CLK_COUNTER
clk_cnt = 0;
forever
begin
#(CLK_PERIOD) clk_cnt = clk_cnt + 1;
end
end
initial begin
// Initialize Inputs
message = 0;
DESkey = 0;
enable = 0;
ack = 0;
// Wait 100 ns for global reset to finish
#10;
// Add stimulus here
message = 64'b1110000010100110111110111111100010010010011001011010011101100101;
DESkey = 64'h133457799BBCDFF1;
enable = 1;
wait(done);
ack = 1;
# 100;
DESkey = 64'h133457799BBCDFF0;
wait(done);
ack = 1;
# 100;
DESkey = 64'hab01986231bc8d01;
//ack = 1;
# 10;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:54:33 05/11/2014
// Design Name:
// Module Name: ID_stage
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ID_stage(/*AUTOARG*/
//Inputs
clk, rst, ID_stall, ID_flush, EX_stall, ID_reg_dst,
ID_data_a, ID_data_b, ID_data_c, ID_aluc,
ID_sign, ID_memread, ID_memwrite, ID_memaddr,
ID_load_op, ID_store_op, ID_memtoreg, ID_regwrite,
//Outputs
EX_data_a, EX_data_b, EX_data_c,
EX_aluc, EX_sign, EX_memread, EX_memwrite, EX_memaddr, EX_load_op,
EX_store_op, EX_memtoreg, EX_regwrite);
input clk;
input rst;
input ID_stall;
input ID_flush;
input EX_stall;
input [4:0] ID_reg_dst;
input [31:0] ID_data_a, ID_data_b, ID_data_c;
input [20:0] ID_aluc;
input ID_sign;
input ID_memread, ID_memwrite;
input [31:0] ID_memaddr;
input [8:0] ID_load_op;
input [5:0] ID_store_op;
input ID_memtoreg, ID_regwrite;
// Hazard
// Outputs
output reg [31:0] EX_data_a, EX_data_b, EX_data_c;
output reg [20:0] EX_aluc;
output reg EX_sign;
output reg EX_memread, EX_memwrite;
output reg [31:0] EX_memaddr;
output reg [8:0] EX_load_op;
output reg [5:0] EX_store_op;
output reg EX_memtoreg, EX_regwrite;
always @(posedge clk) begin
EX_data_a <= rst ? 32'b0 : (EX_stall ? EX_data_a : ID_data_a);
EX_data_b <= rst ? 32'b0 : (EX_stall ? EX_data_b : ID_data_b);
EX_data_c <= rst ? 32'b0 : (EX_stall ? EX_data_c : ID_data_c);
EX_aluc <= rst ? 21'b0 : (EX_stall ? EX_aluc : ((ID_stall | ID_flush) ? 21'b0 : ID_aluc));
EX_sign <= rst ? 0 : (EX_stall ? EX_sign : ID_sign);
EX_memread <= rst ? 0 : (EX_stall ? EX_memread : ((ID_stall | ID_flush) ? 0 : ID_memread));
EX_memwrite <= rst ? 0 : (EX_stall ? EX_memwrite: ((ID_stall | ID_flush) ? 0 : ID_memwrite));
EX_memaddr <= rst ? 0 : (EX_stall ? EX_memaddr : ((ID_stall | ID_flush) ? 0 : ID_memaddr));
EX_load_op <= rst ? 9'b0 : (EX_stall ? EX_load_op : ID_load_op);
EX_store_op <= rst ? 6'b0 : (EX_stall ? EX_store_op: ID_store_op);
//EX_regread <= rst ? 0 : (EX_stall ? EX_regread : ((ID_stall | ID_flush) ? 0 : ID_regread));
EX_regwrite <= rst ? 0 : (EX_stall ? EX_regwrite: ((ID_stall | ID_flush) ? 0 : ID_regwrite));
EX_memtoreg <= rst ? 0 : (EX_stall ? EX_memtoreg: ID_memtoreg);
end
endmodule
|
/* ltcminer_icarus.v copyright kramble 2013
* Based on https://github.com/teknohog/Open-Source-FPGA-Bitcoin-Miner/tree/master/projects/Xilinx_cluster_cgminer
* Hub code for a cluster of miners using async links
* by teknohog
*/
`include "../../source/sha-256-functions.v"
`include "../../source/sha256_transform.v"
`include "../../ICARUS-LX150/xilinx_pll.v"
`include "../../ICARUS-LX150/uart_receiver.v"
`include "../../ICARUS-LX150/uart_transmitter.v"
`include "../../ICARUS-LX150/serial.v"
`include "../../ICARUS-LX150/serial_hub.v"
`include "../../ICARUS-LX150/hub_core.v"
`include "../../ICARUS-LX150/pwm_fade.v"
module ltcminer_icarus (osc_clk, RxD, TxD, led, extminer_rxd, extminer_txd, dip, TMP_SCL, TMP_SDA, TMP_ALERT);
function integer clog2; // Courtesy of razorfishsl, replaces $clog2()
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction
// NB SPEED_MHZ resolution is 5MHz steps to keep pll divide ratio sensible. Change the divider in xilinx_pll.v if you
// want other steps (1MHz is not sensible as it requires divide 100 which is not in the allowed range 1..32 for DCM_SP)
// TODO dynamic speed adjustment (possibly use top byte of target to set multiplier, this keeps serial interface compatible)
`ifdef SPEED_MHZ
parameter SPEED_MHZ = `SPEED_MHZ;
`else
parameter SPEED_MHZ = 50;
`endif
`ifdef SERIAL_CLK
parameter comm_clk_frequency = `SERIAL_CLK;
`else
parameter comm_clk_frequency = 12_500_000; // 100MHz divide 8
`endif
`ifdef BAUD_RATE
parameter BAUD_RATE = `BAUD_RATE;
`else
parameter BAUD_RATE = 115_200;
`endif
// kramble - nonce distribution is crude using top 4 bits of nonce so max LOCAL_MINERS = 8
// teknohog's was more sophisticated, but requires modification of hashcore.v
// Miners on the same FPGA with this hub
`ifdef LOCAL_MINERS
parameter LOCAL_MINERS = `LOCAL_MINERS;
`else
parameter LOCAL_MINERS = 2; // One to four cores (configures ADDRBITS automatically)
`endif
`ifdef ADDRBITS
parameter ADDRBITS = `ADDRBITS;
`else
parameter ADDRBITS = 12 - clog2(LOCAL_MINERS); // May want to override for simulation
`endif
// kramble - nonce distribution only works for a single external port
`ifdef EXT_PORTS
parameter EXT_PORTS = `EXT_PORTS;
`else
parameter EXT_PORTS = 1;
`endif
localparam SLAVES = LOCAL_MINERS + EXT_PORTS;
// kramble - since using separare clocks for uart and hasher, need clock crossing logic
input osc_clk;
wire hash_clk, uart_clk;
`ifndef SIM
main_pll # (.SPEED_MHZ(SPEED_MHZ)) pll_blk (.CLKIN_IN(osc_clk), .CLKFX_OUT(hash_clk), .CLKDV_OUT(uart_clk));
`else
assign hash_clk = osc_clk;
assign uart_clk = osc_clk;
`endif
input TMP_SCL, TMP_SDA, TMP_ALERT; // Unused but set to PULLUP so as to avoid turning on the HOT LED
// TODO implement I2C protocol to talk to temperature sensor chip (TMP101?)
// and drive FAN speed control output.
input [3:0]dip;
wire reset, nonce_chip;
assign reset = dip[0]; // Not used
assign nonce_chip = dip[1]; // Distinguishes between the two Icarus FPGA's
// Work distribution is simply copying to all miners, so no logic
// needed there, simply copy the RxD.
input RxD;
output TxD;
// Results from the input buffers (in serial_hub.v) of each slave
wire [SLAVES*32-1:0] slave_nonces;
wire [SLAVES-1:0] new_nonces;
// Using the same transmission code as individual miners from serial.v
wire serial_send;
wire serial_busy;
wire [31:0] golden_nonce;
serial_transmit #(.comm_clk_frequency(comm_clk_frequency), .baud_rate(BAUD_RATE)) sertx (.clk(uart_clk), .TxD(TxD), .send(serial_send), .busy(serial_busy), .word(golden_nonce));
hub_core #(.SLAVES(SLAVES)) hc (.uart_clk(uart_clk), .new_nonces(new_nonces), .golden_nonce(golden_nonce), .serial_send(serial_send), .serial_busy(serial_busy), .slave_nonces(slave_nonces));
// Common workdata input for local miners
wire [255:0] data1, data2;
wire [127:0] data3;
wire [31:0] target;
// reg [31:0] targetreg = 32'hffffffff; // TEST - matches ANYTHING
reg [31:0] targetreg = 32'h000007ff; // Start at sane value (overwritten by serial_receive)
wire rx_done; // Signals hashcore to reset the nonce
// NB in my implementation, it loads the nonce from data3 which should be fine as
// this should be zero, but also supports testing using non-zero nonces.
// Synchronise across clock domains from uart_clk to hash_clk
// This probably looks amateurish (mea maxima culpa, novice verilogger at work), but should be OK
reg rx_done_toggle = 1'b0; // uart_clk domain
always @ (posedge uart_clk)
rx_done_toggle <= rx_done_toggle ^ rx_done;
reg rx_done_toggle_d1 = 1'b0; // hash_clk domain
reg rx_done_toggle_d2 = 1'b0;
reg rx_done_toggle_d3 = 1'b0;
wire loadnonce;
assign loadnonce = rx_done_toggle_d3 ^ rx_done_toggle_d2;
always @ (posedge hash_clk)
begin
rx_done_toggle_d1 <= rx_done_toggle;
rx_done_toggle_d2 <= rx_done_toggle_d1;
rx_done_toggle_d3 <= rx_done_toggle_d2;
if (loadnonce)
targetreg <= target;
end
// End of clock domain sync
serial_receive #(.comm_clk_frequency(comm_clk_frequency), .baud_rate(BAUD_RATE)) serrx (.clk(uart_clk), .RxD(RxD), .data1(data1),
.data2(data2), .data3(data3), .target(target), .rx_done(rx_done));
// Local miners now directly connected
generate
genvar i;
for (i = 0; i < LOCAL_MINERS; i = i + 1)
// begin: for_local_miners ... too verbose, so...
begin: miners
wire [31:0] nonce_out; // Not used
wire [2:0] nonce_core = i;
wire gn_match;
wire salsa_din, salsa_dout, salsa_busy, salsa_result, salsa_reset, salsa_start, salsa_shift;
// Currently one pbkdfengine per salsaengine - TODO share the pbkdfengine for several salsaengines
pbkdfengine P (.hash_clk(hash_clk), .data1(data1), .data2(data2), .data3(data3), .target(targetreg),
.nonce_msb({nonce_chip, nonce_core}), .nonce_out(nonce_out), .golden_nonce_out(slave_nonces[i*32+31:i*32]),
.golden_nonce_match(gn_match), .loadnonce(loadnonce),
.salsa_din(salsa_din), .salsa_dout(salsa_dout), .salsa_busy(salsa_busy), .salsa_result(salsa_result),
.salsa_reset(salsa_reset), .salsa_start(salsa_start), .salsa_shift(salsa_shift));
salsaengine #(.ADDRBITS(ADDRBITS)) S (.hash_clk(hash_clk), .reset(salsa_reset), .din(salsa_din), .dout(salsa_dout),
.shift(salsa_shift), .start(salsa_start), .busy(salsa_busy), .result(salsa_result) );
// Synchronise across clock domains from hash_clk to uart_clk for: assign new_nonces[i] = gn_match;
reg gn_match_toggle = 1'b0; // hash_clk domain
always @ (posedge hash_clk)
gn_match_toggle <= gn_match_toggle ^ gn_match;
reg gn_match_toggle_d1 = 1'b0; // uart_clk domain
reg gn_match_toggle_d2 = 1'b0;
reg gn_match_toggle_d3 = 1'b0;
assign new_nonces[i] = gn_match_toggle_d3 ^ gn_match_toggle_d2;
always @ (posedge uart_clk)
begin
gn_match_toggle_d1 <= gn_match_toggle;
gn_match_toggle_d2 <= gn_match_toggle_d1;
gn_match_toggle_d3 <= gn_match_toggle_d2;
end
// End of clock domain sync
end // for
endgenerate
// External miner ports, results appended to the same
// slave_nonces/new_nonces as local ones
output [EXT_PORTS-1:0] extminer_txd;
input [EXT_PORTS-1:0] extminer_rxd;
assign extminer_txd = {EXT_PORTS{RxD}};
generate
genvar j;
for (j = LOCAL_MINERS; j < SLAVES; j = j + 1)
// begin: for_ports ... too verbose, so ...
begin: ports
slave_receive #(.comm_clk_frequency(comm_clk_frequency), .baud_rate(BAUD_RATE)) slrx (.clk(uart_clk), .RxD(extminer_rxd[j-LOCAL_MINERS]), .nonce(slave_nonces[j*32+31:j*32]), .new_nonce(new_nonces[j]));
end
endgenerate
output [3:0] led;
assign led[1] = ~RxD;
assign led[2] = ~TxD;
assign led[3] = ~ (TMP_SCL | TMP_SDA | TMP_ALERT); // IDLE LED - held low (the TMP pins are PULLUP, this is a fudge to
// avoid warning about unused inputs)
// Light up only from locally found nonces, not ext_port results
pwm_fade pf (.clk(uart_clk), .trigger(|new_nonces[LOCAL_MINERS-1:0]), .drive(led[0]));
endmodule
|
//altiobuf_out CBX_AUTO_BLACKBOX="ALL" CBX_SINGLE_OUTPUT_FILE="ON" DEVICE_FAMILY="Cyclone V" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=1 OPEN_DRAIN_OUTPUT="FALSE" PSEUDO_DIFFERENTIAL_MODE="TRUE" USE_DIFFERENTIAL_MODE="TRUE" USE_OE="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN1="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN2="FALSE" USE_TERMINATION_CONTROL="FALSE" datain dataout dataout_b
//VERSION_BEGIN 15.1 cbx_altiobuf_out 2015:10:14:18:59:15:SJ cbx_mgl 2015:10:21:19:02:34:SJ cbx_stratixiii 2015:10:14:18:59:15:SJ cbx_stratixv 2015:10:14:18:59:15:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = cyclonev_io_obuf 2 cyclonev_pseudo_diff_out 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module nios_mem_if_ddr2_emif_0_p0_clock_pair_generator
(
datain,
dataout,
dataout_b) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
output [0:0] dataout;
output [0:0] dataout_b;
wire [0:0] wire_obuf_ba_o;
wire [0:0] wire_obuf_ba_oe;
wire [0:0] wire_obufa_o;
wire [0:0] wire_obufa_oe;
wire [0:0] wire_pseudo_diffa_o;
wire [0:0] wire_pseudo_diffa_obar;
wire [0:0] wire_pseudo_diffa_oebout;
wire [0:0] wire_pseudo_diffa_oein;
wire [0:0] wire_pseudo_diffa_oeout;
wire [0:0] oe_w;
cyclonev_io_obuf obuf_ba_0
(
.i(wire_pseudo_diffa_obar),
.o(wire_obuf_ba_o[0:0]),
.obar(),
.oe(wire_obuf_ba_oe[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obuf_ba_0.bus_hold = "false",
obuf_ba_0.open_drain_output = "false",
obuf_ba_0.lpm_type = "cyclonev_io_obuf";
assign
wire_obuf_ba_oe = {(~ wire_pseudo_diffa_oebout[0])};
cyclonev_io_obuf obufa_0
(
.i(wire_pseudo_diffa_o),
.o(wire_obufa_o[0:0]),
.obar(),
.oe(wire_obufa_oe[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_0.bus_hold = "false",
obufa_0.open_drain_output = "false",
obufa_0.lpm_type = "cyclonev_io_obuf";
assign
wire_obufa_oe = {(~ wire_pseudo_diffa_oeout[0])};
cyclonev_pseudo_diff_out pseudo_diffa_0
(
.dtc(),
.dtcbar(),
.i(datain),
.o(wire_pseudo_diffa_o[0:0]),
.obar(wire_pseudo_diffa_obar[0:0]),
.oebout(wire_pseudo_diffa_oebout[0:0]),
.oein(wire_pseudo_diffa_oein[0:0]),
.oeout(wire_pseudo_diffa_oeout[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dtcin(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
assign
wire_pseudo_diffa_oein = {(~ oe_w[0])};
assign
dataout = wire_obufa_o,
dataout_b = wire_obuf_ba_o,
oe_w = 1'b1;
endmodule //nios_mem_if_ddr2_emif_0_p0_clock_pair_generator
//VALID FILE
|
#include <bits/stdc++.h> using namespace std; int read_number(int i) { cout << ? << i << n ; fflush(stdout); int number; cin >> number; return number; } bool intersects(int l1, int l2, int r1, int r2) { if (l1 >= l2) swap(l1, l2); if (r1 >= r2) swap(r2, r1); return max(l1, r1) <= min(l2, r2); } bool contains(int l1, int l2, int r1, int r2) { if (l1 >= l2) swap(l1, l2); if (r1 >= r2) swap(r1, r2); return (l1 <= r1 && l2 >= r2) || (r1 <= l1 && l2 <= r2); } bool dif(int l1, int l2, int r1, int r2) { return (l2 - l1) * (r2 - r1) <= 0; } bool solution(int l1, int l2, int r1, int r2) { return (dif(l1, l2, r1, r2) && intersects(l1, l2, r1, r2)) || contains(l1, l2, r1, r2); } int main() { int n; cin >> n; if ((n / 2) % 2 == 1) { cout << ! -1 n ; return 0; } int l1 = read_number(1); int r1 = read_number(n / 2 + 1); int l2 = r1; int r2 = l1; int min_l1 = 1; int max_l1 = n / 2 + 1; int min_r1 = n / 2 + 1; int max_r2 = n + 1; if (l1 == r1) { cout << ! << l1 << n ; return 0; } while (true) { int med_l1 = (1 + min_l1 + max_l1) / 2; int med_r2 = (1 + min_r1 + max_r2) / 2; int temp_l1 = read_number(med_l1); int temp_r1 = read_number(med_r2); if (temp_l1 == temp_r1) { cout << ! << med_l1 << n ; return 0; } if (solution(l1, temp_l1, r1, temp_r1)) { l2 = temp_l1; r2 = temp_r1; max_l1 = med_l1; max_r2 = med_r2; } else { l1 = temp_l1; r1 = temp_r1; min_l1 = med_l1; min_r1 = med_r2; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int u, v; const int maxn = 5e3 + 10; vector<long long> G[maxn]; bool visited[maxn]; long long dp[maxn]; vector<long long> vc[maxn]; bool mark[maxn]; long long n; vector<long long> ans; void dfs(int x) { visited[x] = 1; for (int i = 0; i != G[x].size(); i++) { if (visited[G[x][i]] == 0) { dfs(G[x][i]); dp[x] += 1 + dp[G[x][i]]; } } } void main_dfs(int x) { visited[x] = 1; memset(mark, 0, sizeof(mark)); for (int i = 0; i < G[x].size(); i++) { if (visited[G[x][i]] == 0) { int g = vc[x].size(); for (int j = 0; j < g; j++) { if (vc[x][j] + dp[G[x][i]] + 1 != n - 1 && mark[vc[x][j] + dp[G[x][i]] + 1] == 0) { vc[x].push_back(vc[x][j] + dp[G[x][i]] + 1); mark[vc[x][j] + dp[G[x][i]] + 1] = 1; } } if (dp[G[x][i]] + 1 != n - 1 && mark[dp[G[x][i]] + 1] == 0) { vc[x].push_back(dp[G[x][i]] + 1); mark[dp[G[x][i]] + 1] = 1; } } else { int g = vc[x].size(); for (int j = 0; j < g; j++) { if (mark[vc[x][j] + n - 1 - dp[x]] == 0) if (vc[x][j] + n - 1 - dp[x] != 0 && vc[x][j] + n - 1 - dp[x] != n - 1) { vc[x].push_back(vc[x][j] + n - dp[x] - 1); mark[vc[x][j] + n - dp[x] - 1] = 1; } } if (mark[n - dp[x] - 1] == 0) if (n - dp[x] - 1 != 0 && n - dp[x] - 1 != n - 1) { vc[x].push_back(n - dp[x] - 1); mark[n - dp[x] - 1] = 1; } } } for (int i = 0; i != G[x].size(); i++) { if (visited[G[x][i]] == 0) main_dfs(G[x][i]); } } bool mk[maxn]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> n; for (int i = 0; i != n - 1; i++) { cin >> u >> v; G[u].push_back(v); G[v].push_back(u); } dfs(1); fill(visited, visited + maxn, 0); main_dfs(1); for (int i = 1; i != n + 1; i++) { for (int j = 0; j != vc[i].size(); j++) { if (find(ans.begin(), ans.end(), vc[i][j]) == ans.end()) { ans.push_back(vc[i][j]); if (n - 1 - vc[i][j] != vc[i][j]) ans.push_back(n - 1 - vc[i][j]); } } } sort(ans.begin(), ans.end()); cout << ans.size() << endl; for (int i = 0; i != ans.size(); i++) { cout << ans[i] << << n - 1 - ans[i] << endl; } } |
/*WARNING: INCOMPLETE MODEL, DON'T USE. I RECOMMEND AGAINST USING THIS
*BLOCK ALL TOGETHER. NOT OPEN SOURCE FRIENDLY /AO
*/
module ISERDESE2 (/*AUTOARG*/
// Outputs
O, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, SHIFTOUT1, SHIFTOUT2,
// Inputs
BITSLIP, CE1, CE2, CLK, CLKB, CLKDIV, CLKDIVP, D, DDLY,
DYNCLKDIVSEL, DYNCLKSEL, OCLK, OCLKB, OFB, RST, SHIFTIN1, SHIFTIN2
);
parameter DATA_RATE = 0; // "DDR" or "SDR"
parameter DATA_WIDTH = 0; // 4,2,3,5,6,7,8,10,14
parameter DYN_CLK_INV_EN = 0; // "FALSE", "TRUE"
parameter DYN_CLKDIV_INV_EN = 0; // "FALSE", "TRUE"
parameter INIT_Q1 = 0; // 1'b0 to 1'b1
parameter INIT_Q2 = 0; // 1'b0 to 1'b1
parameter INIT_Q3 = 0; // 1'b0 to 1'b1
parameter INIT_Q4 = 0; // 1'b0 to 1'b1
parameter INTERFACE_TYPE = 0; // "MEMORY","MEMORY_DDR3", "MEMORY_QDR",
// "NETWORKING", "OVERSAMPLE"
parameter IOBDELAY = 0; // "NONE", "BOTH", "IBUF", "IFD"
parameter NUM_CE = 0; // 2,1
parameter OFB_USED = 0; // "FALSE", "TRUE"
parameter SERDES_MODE = 0; // "MASTER" or "SLAVE"
parameter SRVAL_Q1 = 0; // 1'b0 or 1'b1
parameter SRVAL_Q2 = 0; // 1'b0 or 1'b1
parameter SRVAL_Q3 = 0; // 1'b0 or 1'b1
parameter SRVAL_Q4 = 0; // 1'b0 or 1'b1
input BITSLIP; // performs bitslip operation
input CE1; // clock enable
input CE2; // clock enable
input CLK; // high speed clock input
input CLKB; // high speed clock input (inverted)
input CLKDIV; // divided clock (for bitslip and CE module)
input CLKDIVP; // for MIG only
input D; // serial input data pin
input DDLY; // serial input data from IDELAYE2
input DYNCLKDIVSEL; // dynamically select CLKDIV inversion
input DYNCLKSEL; // dynamically select CLK and CLKB inversion.
input OCLK; // clock for strobe based memory interfaces
input OCLKB; // clock for strobe based memory interfaces
input OFB; // data feebdack from OSERDESE2?
input RST; // asynchronous reset
input SHIFTIN1; // slave of multie serdes
input SHIFTIN2; // slave of multie serdes
//outputs
output O; // pass through from D or DDLY
output Q1; // parallel data out (last bit)
output Q2;
output Q3;
output Q4;
output Q5;
output Q6;
output Q7;
output Q8; // first bit of D appears here
output SHIFTOUT1; // master of multi serdes
output SHIFTOUT2; // master of multi serdes
reg [3:0] even_samples;
reg [3:0] odd_samples;
reg Q1;
reg Q2;
reg Q3;
reg Q4;
reg Q5;
reg Q6;
reg Q7;
reg Q8;
always @ (posedge CLK)
odd_samples[3:0] <= {odd_samples[2:0],D};//#0.1
always @ (negedge CLK)
even_samples[3:0] <= {even_samples[2:0],D};//#0.1
always @ (posedge CLKDIV)
begin
Q1 <= odd_samples[0];
Q2 <= even_samples[0];
Q3 <= odd_samples[1];
Q4 <= even_samples[1];
Q5 <= odd_samples[2];
Q6 <= even_samples[2];
Q7 <= odd_samples[3];
Q8 <= even_samples[3];
end
//pass through
assign O=D;
//not implemented
assign SHIFTOUT1=1'b0;
assign SHIFTOUT2=1'b0;
endmodule // ISERDESE2
|
`timescale 1ns / 1ps
`define RESET 0
`define RESET_WAIT 1
`define INIT_INSTRUCTION 2
`define INIT_WAIT 3
`define DATA_WAIT 4
`define DATA_WRITE 5
`define DATA_WRITE_WAIT 6
module LCD_controler(
input wire clk,
input wire [3:0] iLCD_data,
input wire iLCD_reset,
input wire iLCD_writeEN,
output reg oLCD_response,
output reg [3:0] oLCD_Data,
output reg oLCD_Enabled,
output reg oLCD_RegisterSelect,
output wire oLCD_ReadWrite,
output wire oLCD_StrataFlashControl
);
assign oLCD_StrataFlashControl = 1;
assign oLCD_ReadWrite = 0;
reg [7:0] CurrentState;
reg [7:0] NextState;
reg [31:0] TimeCount;
reg TimeCountReset;
reg [7:0] init_ptr;
reg [3:0] instruction;
always @ (posedge clk)
begin
if(iLCD_reset)
CurrentState = `RESET;
else
begin
if(TimeCountReset)
TimeCount = 32'b0;
else
TimeCount = TimeCount + 1;
end
CurrentState = NextState;
end
always @ (*)
case(CurrentState)
`RESET:
begin
oLCD_response = 1'b0;
oLCD_Data = 4'h0;
oLCD_Enabled = 1'b0;
oLCD_RegisterSelect = 1'b0;
init_ptr = 3'b0;
TimeCountReset = 1'b1;
NextState = `RESET_WAIT;
end
`RESET_WAIT:
begin
oLCD_response = 1'b0;
oLCD_Data = 4'h0;
oLCD_Enabled = 1'b0;
oLCD_RegisterSelect = 1'b0;
init_ptr = init_ptr;
if(TimeCount > 32'd750000)
begin
TimeCountReset = 1'b1;
NextState = `INIT_INSTRUCTION;
end
else
begin
TimeCountReset = 1'b0;
NextState = `RESET_WAIT;
end
end
`INIT_INSTRUCTION:
begin
oLCD_response = 1'b0;
oLCD_RegisterSelect = 1'b0;
init_ptr = init_ptr;
if(TimeCount > 32'd12)
begin
oLCD_Data = 4'h0;
oLCD_Enabled = 1'b0;
TimeCountReset = 1'b1;
NextState = `INIT_WAIT;
end
else
begin
oLCD_Data = instruction;
oLCD_Enabled = 1'b1;
TimeCountReset = 1'b0;
NextState = `INIT_INSTRUCTION;
end
end
`INIT_WAIT:
if(TimeCount > 32'd250000)
// se acabaron las instrucciones
if(init_ptr == 8'd11)
begin
oLCD_response = 1'b1;
oLCD_Data = 4'h0;
oLCD_Enabled = 1'b0;
oLCD_RegisterSelect = 1'b0;
TimeCountReset = 1'b1;
NextState = `DATA_WAIT;
init_ptr = init_ptr;
end
else
begin
oLCD_response = 1'b0;
oLCD_Data = 4'h0;
oLCD_Enabled = 1'b0;
oLCD_RegisterSelect = 1'b0;
TimeCountReset = 1'b1;
NextState = `INIT_INSTRUCTION;
init_ptr = init_ptr + 1;
end
else
begin
oLCD_response = 1'b0;
oLCD_Data = 4'h0;
oLCD_Enabled = 1'b0;
oLCD_RegisterSelect = 1'b0;
TimeCountReset = 1'b0;
init_ptr = init_ptr;
NextState = `INIT_WAIT;
end
`DATA_WAIT:
begin
oLCD_response = 1'b1;
oLCD_Enabled = 1'b0;
oLCD_RegisterSelect = 1'b0;
TimeCountReset = 1'b1;
init_ptr = init_ptr;
if(iLCD_writeEN)
begin
NextState = `DATA_WRITE;
oLCD_Data = iLCD_data;
end
else
begin
oLCD_Data = 4'b0;
NextState = `DATA_WAIT;
end
end
`DATA_WRITE:
begin
oLCD_response = 1'b0;
oLCD_Enabled = 1'b1;
oLCD_RegisterSelect = 1'b1;
init_ptr = init_ptr;
if(TimeCount > 32'd50)
begin
oLCD_Data = 4'b0;
NextState = `DATA_WRITE_WAIT;
TimeCountReset = 1'b1;
end
else
begin
oLCD_Data = oLCD_Data;
NextState = `DATA_WRITE;
TimeCountReset = 1'b0;
end
end
`DATA_WRITE_WAIT:
begin
oLCD_Data = 4'b0;
oLCD_Enabled = 1'b0;
oLCD_RegisterSelect = 1'b0;
init_ptr = init_ptr;
if(TimeCount > 32'd2000)
begin
oLCD_response = 1'b1;
NextState = `DATA_WAIT;
TimeCountReset = 1'b1;
end
else
begin
oLCD_response = 1'b0;
NextState = `DATA_WRITE_WAIT;
TimeCountReset = 1'b0;
end
end
default:
begin
oLCD_response = 1'b0;
oLCD_Data = 4'h0;
oLCD_Enabled = 1'b0;
oLCD_RegisterSelect = 1'b0;
NextState = `RESET;
TimeCountReset = 1'b1;
init_ptr = 1'b0;
end
endcase
always @ (init_ptr)
case(init_ptr)
// init sequence
0: instruction = 4'h3;
1: instruction = 4'h3;
2: instruction = 4'h3;
3: instruction = 4'h2;
// Function_set 0x28
4: instruction = 4'h2;
5: instruction = 4'h8;
//Entry_mode 0x06
6: instruction = 4'h0;
7: instruction = 4'h6;
//Display On
8: instruction = 4'h0;
9: instruction = 4'hC;
//Clear Display
10: instruction = 4'h0;
11: instruction = 4'h1;
default: instruction = 4'h0;
endcase
endmodule |
#include <bits/stdc++.h> int n, m, k, flag, ans, cnt, p, q, w[1000005], f[1000005], g[1000005], s[1000005]; int main() { scanf( %d%d%d , &n, &m, &k); w[0] = 1; for (int i = 1; i <= n; i++) w[i] = w[i - 1] * 2 % 1000000007; for (int i = 1; i <= m; i++) { int x, y; scanf( %d%d , &x, &y); if (x > y) std::swap(x, y); if (x + 1 == y) f[x] = 1; else if (x + k + 1 == y) g[x] = 1, ++cnt; else flag = 1; } if (flag) { puts( 0 ); return 0; } if (cnt == 0) { for (int i = 1; i <= n; i++) { if (i + k + 1 > n) continue; int up = (i + k + k + 1 > n ? n - k - 1 : i + k); int can = up - i + 1; ans = (ans + w[can - 1]) % 1000000007; } ++ans; printf( %d n , ans); return 0; } for (int i = 1; i <= n; i++) if (g[i]) q = i; for (int i = n; i >= 1; i--) if (g[i]) p = i; if (p + k + 1 <= q) { puts( 0 ); return 0; } for (int i = 1; i <= n; i++) s[i] = s[i - 1] + g[i]; for (int i = 1; i <= n; i++) { if (g[i] || i + k + 1 > n) continue; if (i >= p + k + 1 || i + k + 1 <= q) continue; int cp = p, cq = q; if (i < p) p = i; if (i > q) q = i; int up = (p + k + k + 1 > n ? n - k - 1 : p + k); int can = up - i + 1 - (s[up] - s[i - 1]); ans = (ans + w[can - 1]) % 1000000007; q = cq, p = cp; } ++ans; printf( %d n , ans); } |
#include <bits/stdc++.h> using namespace std; using ll = long long; #pragma GCC optimize( O3 ) #pragma GCC optimize( unroll-loops ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,tune=native ) template <typename T> ostream& operator<<(ostream& os, const vector<T>& v) { for (ll i = 0; i < v.size(); ++i) os << v[i] << ; return os; } template <typename T> ostream& operator<<(ostream& os, const set<T>& v) { for (auto it : v) os << it << ; return os; } template <typename T, typename S> ostream& operator<<(ostream& os, const pair<T, S>& v) { os << v.first << << v.second; return os; } const ll mod = 1e9 + 7; const ll inf = 2e18; const ll ninf = -2e18; ll takemod(ll a) { return ((a % mod) + mod) % mod; } ll pow(ll a, ll b, ll m) { ll ans = 1; a %= m; while (b) { if (b & 1) ans = (ans * a) % m; b /= 2; a = (a * a) % m; } return ans; } ll modinv(ll a) { return takemod(pow(takemod(a), mod - 2, mod)); } void solve() { ll n; cin >> n; string s1, s2; cin >> s1 >> s2; ll arr[26][26]; memset(arr, 0, sizeof(arr)); for (ll i = 0; i < n; i++) { ll a = s1[i] - a ; ll b = s2[i] - a ; if (a == b) continue; if (a > b) { cout << -1 << n ; return; } arr[a][b]++; } ll ans = 0; for (ll i = 0; i <= 20; i++) { for (ll j = i + 1; j <= 20; j++) { if (!arr[i][j]) continue; for (ll k = j + 1; k <= 20; k++) { if (arr[i][k]) { arr[j][k] += arr[i][k]; arr[i][k] = 0; } } ans++; } } cout << ans << n ; } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); time_t t1, t2; t1 = clock(); ll t; cin >> t; while (t--) solve(); t2 = clock(); cerr << n << t2 - t1 << n ; return 0; } |
/****************************************************************
/*
/* Description:
/* change internal parallel data to output
/* serial data
/* Author:
/* Guozhu Xin
/* Date:
/* 2017/7/10
/* Email:
/*
******************************************************************/
module para2ser(
input clk,
input rst_n,
input trans_start, // indicate tansform begin, level signal
input [8:0] data, // signal:0-9 max coding length:9
input [3:0] data_len, // 9 - 1
output wire output_data, // MSB first
output wire output_start,
output wire output_done
);
reg [3:0] data_cnt;
reg [8:0] data_reg;
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
data_cnt <= 4'b0;
data_reg <= 9'b0;
end
else if(trans_start) begin
data_cnt <= (data_cnt == 4'b0) ? data_len-1 : data_cnt-1;
data_reg <= data;
end
end
reg trans_start_q1;
reg trans_start_q2;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
trans_start_q1 <= 1'b0;
trans_start_q2 <= 1'b0;
end
else begin
trans_start_q1 <= trans_start;
trans_start_q2 <= trans_start_q1;
end
end
assign output_start = trans_start & ~trans_start_q1;
assign output_done = ~trans_start_q1 & trans_start_q2;
assign output_data = (data_reg >> data_cnt) & 1'b1;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long a, b; cin >> b >> a; a--; b -= a; if (b >= 0 && b % 2 == 0 && a > 0) { cout << Yes << endl; } else if (b == 0 && a == 0) cout << Yes << endl; else cout << No << endl; return 0; } |
// -- (c) Copyright 2008 - 2014 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: This is a generic n-deep SRL instantiation
// Verilog-standard: Verilog 2001
// $Revision:
// $Date:
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_data_fifo_v2_1_ndeep_srl #
(
parameter C_FAMILY = "rtl", // FPGA Family
parameter C_A_WIDTH = 1 // Address Width (>= 1)
)
(
input wire CLK, // Clock
input wire [C_A_WIDTH-1:0] A, // Address
input wire CE, // Clock Enable
input wire D, // Input Data
output wire Q // Output Data
);
localparam integer P_SRLASIZE = 5;
localparam integer P_SRLDEPTH = 32;
localparam integer P_NUMSRLS = (C_A_WIDTH>P_SRLASIZE) ? (2**(C_A_WIDTH-P_SRLASIZE)) : 1;
localparam integer P_SHIFT_DEPTH = 2**C_A_WIDTH;
wire [P_NUMSRLS:0] d_i;
wire [P_NUMSRLS-1:0] q_i;
wire [(C_A_WIDTH>P_SRLASIZE) ? (C_A_WIDTH-1) : (P_SRLASIZE-1) : 0] a_i;
genvar i;
// Instantiate SRLs in carry chain format
assign d_i[0] = D;
assign a_i = A;
generate
if (C_FAMILY == "rtl") begin : gen_rtl_shifter
if (C_A_WIDTH <= P_SRLASIZE) begin : gen_inferred_srl
reg [P_SRLDEPTH-1:0] shift_reg = {P_SRLDEPTH{1'b0}};
always @(posedge CLK)
if (CE)
shift_reg <= {shift_reg[P_SRLDEPTH-2:0], D};
assign Q = shift_reg[a_i];
end else begin : gen_logic_shifter // Very wasteful
reg [P_SHIFT_DEPTH-1:0] shift_reg = {P_SHIFT_DEPTH{1'b0}};
always @(posedge CLK)
if (CE)
shift_reg <= {shift_reg[P_SHIFT_DEPTH-2:0], D};
assign Q = shift_reg[a_i];
end
end else begin : gen_primitive_shifter
for (i=0;i<P_NUMSRLS;i=i+1) begin : gen_srls
SRLC32E
srl_inst
(
.CLK (CLK),
.A (a_i[P_SRLASIZE-1:0]),
.CE (CE),
.D (d_i[i]),
.Q (q_i[i]),
.Q31 (d_i[i+1])
);
end
if (C_A_WIDTH>P_SRLASIZE) begin : gen_srl_mux
generic_baseblocks_v2_1_nto1_mux #
(
.C_RATIO (2**(C_A_WIDTH-P_SRLASIZE)),
.C_SEL_WIDTH (C_A_WIDTH-P_SRLASIZE),
.C_DATAOUT_WIDTH (1),
.C_ONEHOT (0)
)
srl_q_mux_inst
(
.SEL_ONEHOT ({2**(C_A_WIDTH-P_SRLASIZE){1'b0}}),
.SEL (a_i[C_A_WIDTH-1:P_SRLASIZE]),
.IN (q_i),
.OUT (Q)
);
end else begin : gen_no_srl_mux
assign Q = q_i[0];
end
end
endgenerate
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; inline void read(int &x) { int v = 0, f = 1; char c = getchar(); while (!isdigit(c) && c != - ) c = getchar(); if (c == - ) f = -1; else v = (c & 15); while (isdigit(c = getchar())) v = (v << 1) + (v << 3) + (c & 15); x = v * f; } inline void read(long long &x) { long long v = 0ll, f = 1ll; char c = getchar(); while (!isdigit(c) && c != - ) c = getchar(); if (c == - ) f = -1; else v = (c & 15); while (isdigit(c = getchar())) v = (v << 1) + (v << 3) + (c & 15); x = v * f; } inline void readc(char &x) { char c; while (((c = getchar()) == ) || c == n ) ; x = c; } int n, m, i, j, vis[100005], ve[100005], dep[100005]; long long a[100005], px[100005], py[100005], res[100005]; vector<int> e[100005]; void dfs1(int x) { vis[x] = 1; for (__typeof((e[x]).begin()) it = (e[x]).begin(); it != (e[x]).end(); it++) { if (!ve[*it]) { int y = px[*it] ^ py[*it] ^ x; if (!vis[y]) { ve[*it] = 1; dep[y] = dep[x] + 1; dfs1(y); res[*it] += a[y]; a[x] -= a[y]; a[y] = 0; } } } } int main() { read(n); read(m); for (((i)) = (1); ((i)) <= ((n)); ((i))++) read(a[i]); for (((i)) = (1); ((i)) <= ((m)); ((i))++) { int x, y; read(x); read(y); px[i] = x; py[i] = y; e[x].push_back(i); e[y].push_back(i); } dfs1(1); for (((i)) = (1); ((i)) <= ((m)); ((i))++) if (!ve[i]) { if (!((dep[px[i]] ^ dep[py[i]]) & 1)) { if (dep[px[i]] & 1) res[i] -= a[1] / 2; else res[i] = +a[1] / 2; a[px[i]] -= res[i]; a[py[i]] -= res[i]; break; } } memset(vis, 0, sizeof(vis)); memset(ve, 0, sizeof(ve)); dfs1(1); if (a[1]) { puts( NO ); return 0; } puts( YES ); for (((i)) = (1); ((i)) <= ((m)); ((i))++) { printf( %lld n , res[i]); } return 0; } |
#include <bits/stdc++.h> using namespace std; long long int power(long long int x, long long int y, long long int m) { if (y == 0) return 1; long long int p = power(x, y / 2, m) % m; p = (p * p) % m; return (y % 2 == 0) ? p : (x * p) % m; } long long int nCr(long long int n, long long int r, long long int m) { if (r > n) return 0; long long int a = 1, b = 1, i; for (i = 0; i < r; i++) { a = (a * n) % m; --n; } while (r) { b = (b * r) % m; --r; } return (a * power(b, m - 2, m)) % m; } vector<vector<int>> sufs, suft, ans; string s, t; int dp(int a, int b) { if (b == 0) return 0; if (ans[a][b] != -1) return ans[a][b]; ans[a][b] = 1e5; if (a > 0) ans[a][b] = min(ans[a][b], 1 + dp(a - 1, b)); if (s[a - 1] == t[b - 1] && a > 0) ans[a][b] = min(ans[a][b], dp(a - 1, b - 1)); int ch = t[b - 1] - a ; if (sufs[a][ch] - suft[b][ch] > 0) ans[a][b] = min(ans[a][b], dp(a, b - 1)); return ans[a][b]; } void solve() { int n; cin >> n; cin >> s >> t; sufs = suft = vector<vector<int>>(n + 1, vector<int>(26, 0)); for (int i = n - 1; i >= 0; --i) { sufs[i][s[i] - a ]++; suft[i][t[i] - a ]++; for (int j = 0; j < 26; ++j) { sufs[i][j] += sufs[i + 1][j]; suft[i][j] += suft[i + 1][j]; if (i == 0 && sufs[i][j] != suft[i][j]) { cout << -1 << n ; return; } } } ans = vector<vector<int>>(n + 1, vector<int>(n + 1, -1)); cout << dp(n, n); cout << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t--) solve(); return 0; } |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_edb_e
//
// Generated
// by: wig
// on: Mon Mar 22 13:27:29 2004
// cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_edb_e.v,v 1.1 2004/04/06 10:50:30 wig Exp $
// $Date: 2004/04/06 10:50:30 $
// $Log: inst_edb_e.v,v $
// Revision 1.1 2004/04/06 10:50:30 wig
// Adding result/mde_tests
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
//
// Generator: mix_0.pl Revision: 1.26 ,
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_edb_e
//
// No `defines in this module
module inst_edb_e
//
// Generated module inst_edb
//
(
acg_systime_init,
cgu_scani,
cgu_scano,
ifu_gpio0_wkup,
ifu_gpio1_wkup,
ifu_gpio2_wkup,
nreset,
nreset_s,
vclkl27
);
// Generated Module Inputs:
input [30:0] acg_systime_init;
input cgu_scani;
input ifu_gpio0_wkup;
input ifu_gpio1_wkup;
input ifu_gpio2_wkup;
input nreset;
input nreset_s;
input vclkl27;
// Generated Module Outputs:
output cgu_scano;
// Generated Wires:
wire [30:0] acg_systime_init;
wire cgu_scani;
wire cgu_scano;
wire ifu_gpio0_wkup;
wire ifu_gpio1_wkup;
wire ifu_gpio2_wkup;
wire nreset;
wire nreset_s;
wire vclkl27;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of inst_edb_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; void marmot0814() { int n; cin >> n; int p1 = 1, p2 = 2, p3 = 3; while (n--) { int v; cin >> v; if (v == p3) { cout << NO n ; return; } else if (v == p1) { swap(p2, p3); } else { swap(p1, p3); } } cout << YES n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); int t = 1, kase = 0; while (t--) { marmot0814(); } } |
#include <bits/stdc++.h> using namespace std; const int N = 100005; int a[N]; int main() { int n; long long sum = 0; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); sum += a[i] - 1; if (sum % 2 == 1) printf( 1 n ); else printf( 2 n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; void time() { ios_base ::sync_with_stdio(0); cin.tie(0); cout.tie(0); } int main() { time(); int a, s, d, f; cin >> a >> s >> d >> f; if (a == s || s > a) { cout << Second << endl; } else { cout << First << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_MUX_4TO2_SYMBOL_V
`define SKY130_FD_SC_LP__UDP_MUX_4TO2_SYMBOL_V
/**
* udp_mux_4to2: Four to one multiplexer with 2 select controls
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__udp_mux_4to2 (
//# {{data|Data Signals}}
input A0,
input A1,
input A2,
input A3,
output X ,
//# {{control|Control Signals}}
input S0,
input S1
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_MUX_4TO2_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYMETAL6S4S_PP_SYMBOL_V
`define SKY130_FD_SC_MS__DLYMETAL6S4S_PP_SYMBOL_V
/**
* dlymetal6s4s: 6-inverter delay with output from 4th inverter on
* horizontal route.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlymetal6s4s (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYMETAL6S4S_PP_SYMBOL_V
|
/**
HaarFilter
==========
Haar filter bank. Output is an array of signed values OUT_WIDTH bits wide,
arranged in little-endian fashion. Word 0 is the low-pass output, word 1 is the
corresponding high-pass output, word 2 is the high pass output from the previous
filter pair, and so on:
```
in --+--> HPF ---------------------------> word 3
|
\--> LPF --+--> HPF ----------------> word 2
|
\--> LPF --+--> HPF -----> word 1
|
\--> LPF -----> word 0
```
The filters are multirate, downsampling after each filter pair. To save on
resources, the filter calculation steps are interleaved. New samples are
available on the corresponding bit in `outStrobes`.
Usage Notes
-----------
- The enable strobe (`en`) *must* be 1 clock wide and occur no more than once
every 2 clock cycles!
- It is recommended to use an `INTERNAL_WIDTH` wider than `IN_WIDTH`. To
completely preserve bits, make `INTERNAL_WIDTH` `STAGES` bits wider than
`IN_WIDTH`.
*/
module HaarFilter #(
parameter STAGES = 4, ///< Number of stages
parameter INTERNAL_WIDTH = 18, ///< Internal bit width used for calculations
parameter IN_WIDTH = 16, ///< Width of input signal
parameter OUT_WIDTH = 16 ///< Width of output signals from filter bank
)
(
input clk, ///< System clock
input rst, ///< Reset, synchronous and active high
input en, ///< Enable (once per new sample)
input signed [IN_WIDTH-1:0] dataIn, ///< Input samples
output reg [STAGES:0] outStrobes, ///< Strobes for each output
output reg [OUT_WIDTH*(STAGES+1)-1:0] dataOut ///< Outputs from analysis filter
);
///////////////////////////////////////////////////////////////////////////
// Parameter Declarations
///////////////////////////////////////////////////////////////////////////
// Verify Parameters are correct
initial begin
if (STAGES < 2 || STAGES > 8) begin
$display("Attribute STAGES on HaarFilter instance %m is set to %d. Valid range is 2 to 8", STAGES);
#1 $finish;
end
if (INTERNAL_WIDTH < 2) begin
$display("Attribute INTERNAL_WIDTH on HaarFilter instance %m is set to %d. Must be at least 2.", INTERNAL_WIDTH);
#1 $finish;
end
if (IN_WIDTH < 2) begin
$display("Attribute IN_WIDTH on HaarFilter instance %m is set to %d. Must be at least 2.", IN_WIDTH);
#1 $finish;
end
if (OUT_WIDTH < 2) begin
$display("Attribute OUT_WIDTH on HaarFilter instance %m is set to %d. Must be at least 2.", OUT_WIDTH);
#1 $finish;
end
end
///////////////////////////////////////////////////////////////////////////
// Signal Declarations
///////////////////////////////////////////////////////////////////////////
reg signed [INTERNAL_WIDTH-1:0] lowPass [STAGES-1:0];
reg signed [INTERNAL_WIDTH-1:0] prevArray [STAGES-1:0];
reg signed [INTERNAL_WIDTH-1:0] highPass [STAGES-1:0];
reg [7:0] counter;
integer outArray;
integer i;
///////////////////////////////////////////////////////////////////////////
// Calculation Engine
///////////////////////////////////////////////////////////////////////////
wire signed [INTERNAL_WIDTH:0] calcOut;
wire signed [INTERNAL_WIDTH-1:0] in0;
wire signed [INTERNAL_WIDTH-1:0] in1;
reg signed [IN_WIDTH-1:0] dataInD1;
reg [3:0] index;
reg [3:0] index2;
reg enD1;
wire step0;
wire step1;
always @(counter) begin
if (counter[0] == 1'b0) index = 'd0;
else if (counter[1:0] == 2'b01) index = 'd1;
else if (counter[2:0] == 3'b011) index = 'd2;
else if (counter[3:0] == 4'b0111) index = 'd3;
else if (counter[4:0] == 5'b01111) index = 'd4;
else if (counter[5:0] == 6'b011111) index = 'd5;
else if (counter[6:0] == 7'b0111111) index = 'd6;
else if (counter[7:0] == 8'b01111111) index = 'd7;
else index = 'd8; // Used to avoid updating values
if (counter[0] == 1'b0) index2 = 'd8;
else if (counter[1:0] == 2'b01) index2 = 'd0;
else if (counter[2:0] == 3'b011) index2 = 'd1;
else if (counter[3:0] == 4'b0111) index2 = 'd2;
else if (counter[4:0] == 5'b01111) index2 = 'd3;
else if (counter[5:0] == 6'b011111) index2 = 'd4;
else if (counter[6:0] == 7'b0111111) index2 = 'd5;
else if (counter[7:0] == 8'b01111111) index2 = 'd6;
else index2 = 'd7; // Used to avoid updating values
end
if (IN_WIDTH > INTERNAL_WIDTH) begin
assign in0 = counter[0] ? prevArray[index2] : (dataInD1 >>> (IN_WIDTH-INTERNAL_WIDTH));
assign in1 = counter[0] ? lowPass[index2] : (dataIn >>> (IN_WIDTH-INTERNAL_WIDTH));
end
else begin
assign in0 = counter[0] ? prevArray[index2] : (dataInD1 <<< (INTERNAL_WIDTH-IN_WIDTH));
assign in1 = counter[0] ? lowPass[index2] : (dataIn <<< (INTERNAL_WIDTH-IN_WIDTH));
end
assign step0 = en && !enD1;
assign step1 = !en && enD1;
assign calcOut = (step1) ? (in1 - in0) : (in1 + in0);
always @(posedge clk) begin
if (rst) begin
counter <= 'd0;
enD1 <= 'd0;
outStrobes <= 'd0;
dataInD1 <= 'd0;
for (i=0; i<STAGES; i=i+1) begin
lowPass[i] <= 'd0;
highPass[i] <= 'd0;
prevArray[i] <= 'd0;
end
end
else begin
enD1 <= en;
if (step1) begin
counter <= counter + 2'd1;
end
if (step1) dataInD1 <= dataIn;
for (i=0; i<STAGES; i=i+1) begin
// High-pass outputs
if (index == i && step1) begin
highPass[i] <= calcOut[INTERNAL_WIDTH:1];
outStrobes[STAGES-i] <= 1'b1;
end
else begin
outStrobes[STAGES-i] <= 1'b0;
end
// Low-pass outputs
if (index == i && step0) begin
lowPass[i] <= calcOut[INTERNAL_WIDTH:1];
prevArray[i] <= lowPass[i];
end
end
// Final low-pass output strobe
if (index == STAGES-1 && step0) begin
outStrobes[0] <= 1'b1;
end
else begin
outStrobes[0] <= 1'b0;
end
end
end
///////////////////////////////////////////////////////////////////////////
// Output Mapping
///////////////////////////////////////////////////////////////////////////
// Map filter outputs onto output array
if (INTERNAL_WIDTH > OUT_WIDTH) begin
always @(*) begin
dataOut[0+:OUT_WIDTH] = lowPass[STAGES-1] >>> (INTERNAL_WIDTH-OUT_WIDTH);
for (outArray=0; outArray<STAGES; outArray = outArray+1) begin
dataOut[(OUT_WIDTH*(outArray+1))+:OUT_WIDTH] = highPass[STAGES-1-outArray] >>> (INTERNAL_WIDTH-OUT_WIDTH);
end
end
end
else begin
always @(*) begin
dataOut[0+:OUT_WIDTH] = lowPass[STAGES-1] <<< (OUT_WIDTH-INTERNAL_WIDTH);
for (outArray=0; outArray<STAGES; outArray = outArray+1) begin
dataOut[(OUT_WIDTH*(outArray+1))+:OUT_WIDTH] = highPass[STAGES-1-outArray] <<< (OUT_WIDTH-INTERNAL_WIDTH);
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; string solve(string s) { if (s.size() & 1) { return s; } string a = solve(s.substr(0, s.size() / 2)); string b = solve(s.substr(s.size() / 2)); if (a < b) { return a.append(b); } else { return b.append(a); } } int main() { string s, t; cin >> s >> t; cout << (solve(s) == solve(t) ? YES : NO ) << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const int N = 1e6 + 10; string s[101]; string x; long long dp[101]; long long n; int m; int fail[N]; struct matrix { long long v[4][4]; matrix() { for (int i = 0; i < 4; i++) for (int j = 0; j < 4; j++) v[i][j] = 0; } matrix(long long u[4][4]) { for (int i = 0; i < 4; i++) for (int j = 0; j < 4; j++) v[i][j] = u[i][j]; } matrix operator*(const matrix a) const { matrix ans; for (int i = 0; i < 4; i++) for (int j = 0; j < 4; j++) for (int k = 0; k < 4; k++) { ans.v[i][j] += (v[i][k] * a.v[k][j]); ans.v[i][j] = (ans.v[i][j] + mod) % mod; } return ans; } void setunit() { for (int i = 0; i < 4; i++) v[i][i] = 1; } }; long long mtx[4][4] = { {1, 2, -1, -1}, {1, 0, 0, 0}, {0, 1, 0, 0}, {0, 0, 1, 0}, }; matrix calc(long long i) { matrix tmp(mtx); matrix ans; ans.setunit(); while (i) { if (i & 1ll) ans = tmp * ans; tmp = tmp * tmp; i = i / 2ll; } return ans; } long long kmp(int p) { int m = x.length(), n = s[p].length(); if (m > n) return 0; for (int i = 1, j = fail[0] = -1; i < m; i++) { while (j >= 0 && x[j + 1] != x[i]) j = fail[j]; if (x[j + 1] == x[i]) j++; fail[i] = j; } int ans = 0; for (int i = 0, j = -1; i < n; i++) { while (j >= 0 && x[j + 1] != s[p][i]) j = fail[j]; if (x[j + 1] == s[p][i]) j++; if (j == m - 1) { ans++; j = fail[j]; } } return (long long)ans; } long long calc(int a, int b) { string p = s[a] + s[b]; int s1 = s[a].length(); int m = x.length(), n = p.length(); if (m > n) return 0; for (int i = 1, j = fail[0] = -1; i < m; i++) { while (j >= 0 && x[j + 1] != x[i]) j = fail[j]; if (x[j + 1] == x[i]) j++; fail[i] = j; } int ans = 0; for (int i = 0, j = -1; i < n; i++) { while (j >= 0 && x[j + 1] != p[i]) j = fail[j]; if (x[j + 1] == p[i]) j++; if (j == m - 1) { if ((i - m + 1 < s1) && (i + 1) > s1) ans++; j = fail[j]; } } return (long long)ans; } int main() { s[1] = a ; s[2] = b ; for (int i = 3; i <= 30; i++) s[i] = s[i - 1] + s[i - 2]; cin >> n >> m; while (m--) { cin >> x; if (n <= 25) { cout << kmp((int)n) << endl; continue; } int len = x.length(); int r = 1; while (s[r].length() < len) r++; long long add1 = calc(r, r), add2 = calc(r + 1, r); for (int i = 1; i <= r + 2; i++) dp[i] = kmp(i); dp[r + 3] = dp[r + 2] + dp[r + 1] + add1; dp[r + 4] = dp[r + 3] + dp[r + 2] + add2; dp[r + 5] = dp[r + 4] + dp[r + 3] + add1; dp[r + 6] = dp[r + 5] + dp[r + 4] + add2; if (n <= r + 6) { cout << dp[n] << endl; continue; } matrix mat = calc(n - r - 6); long long ans = 0; for (int i = 0; i < 4; i++) ans += mat.v[0][i] * dp[r + 6 - i]; ans = ans % mod; while (ans < 0) ans += mod; cout << ans << endl; } } |
#include <bits/stdc++.h> using namespace std; using LL = long long; constexpr int N = 1e5 + 5; int main() { ios::sync_with_stdio(false); cin.tie(nullptr); int n, m, x, y; cin >> n >> m >> x >> y; x--; y--; string s; cin >> s; vector<vector<int>> mat(n, vector<int>(m, -1)); for (int i = 0; i < s.size(); i++) { if (mat[x][y] == -1) mat[x][y] = i; if (s[i] == U ) x = max(x - 1, 0); if (s[i] == D ) x = min(x + 1, n - 1); if (s[i] == R ) y = min(y + 1, m - 1); if (s[i] == L ) y = max(y - 1, 0); } vector<int> ans(s.size() + 1); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (mat[i][j] == -1) { ans[s.size()]++; } else { ans[mat[i][j]]++; } } } for (int x : ans) cout << x << ; } |
#include <bits/stdc++.h> using namespace std; int n, m, k, a[100][100], ans, ma[100]; bool mark[10]; int seen[100000]; void BT(int n) { if (n > ::n) { int ans = 0; for (int i = 1; i <= ::n; i++) { if (a[i][ma[i]] == 0 && ma[i] != 0) return; ans += a[i][ma[i]]; } seen[ans]++; return; } for (int i = 0; i <= ::n; i++) { if (i == 0 || !mark[i]) { ma[n] = i; mark[i] = true; BT(n + 1); ma[n] = 0; mark[i] = false; } } return; } int main() { cin >> n >> m >> k; for (int i = 0; i < m; i++) { int A, b, c; cin >> A >> b >> c; a[A][b] = c; } int t = 0, i = 0; BT(1); seen[0] = 1; while (t < k) { if (seen[i]) t += seen[i]; i++; } cout << i - 1 << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int cmpfunc(const void* a, const void* b) { return (*(int*)a - *(int*)b); } int main() { int A, B, i; long long int sum = 0; int a[100001] = {0}; cin >> A; cin >> B; for (i = 0; i < A; i++) { cin >> a[i]; } qsort(a, A, sizeof(int), cmpfunc); for (i = 1; i < A; i++) { if ((a[i] - a[0]) % B == 0) sum = sum + (a[i] - a[0]) / B; else { sum = -1; break; } } cout << sum; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; vector<int> v[N]; vector<pair<int, int> > ans; int deg[N], maxT; void dfs(int x, int T, int u) { ans.push_back({x, T}); int beginT = T; for (auto it : v[x]) if (it != u) { if (T == maxT) { T = maxT - deg[x]; ans.push_back({x, T}); } dfs(it, T + 1, x); ans.push_back({x, ++T}); } if (T >= beginT) ans.push_back({x, beginT - 1}); } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; for (int i = 1; i < n; i++) { int x, y; cin >> x >> y; v[x].push_back(y); v[y].push_back(x); deg[x]++; deg[y]++; } for (int i = 1; i <= n; i++) maxT = max(maxT, deg[i]); dfs(1, 0, 0); ans.pop_back(); cout << ans.size() << n ; for (auto it : ans) cout << it.first << << it.second << n ; } |
// This file extends the original bug test case to explore all the
// forms of a signed right shift that are treated as special cases.
module test;
reg pass;
reg [8*40:1] str;
integer s;
initial begin
pass = 1'b1;
s = 1;
$sformat(str, "%0d", ((0 >> 1) + 1) * -1);
if (str[8*2:1] !== "-1" || str[8*40:8*2+1] !== 0) begin
$display("FAILED 1st test, expected \"-1\", got %s", str);
pass = 1'b0;
end
$sformat(str, "%0d", ((2 >> 1) + 1) * -1);
if (str[8*2:1] !== "-2" || str[8*40:8*2+1] !== 0) begin
$display("FAILED 2nd test, expected \"-2\", got %s", str);
pass = 1'b0;
end
$sformat(str, "%0d", ((2 >> s) + 1) * -1);
if (str[8*2:1] !== "-2" || str[8*40:8*2+1] !== 0) begin
$display("FAILED 3rd test, expected \"-2\", got %s", str);
pass = 1'b0;
end
$sformat(str, "%0d", ((s >> 1) + 1) * -1);
if (str[8*2:1] !== "-1" || str[8*40:8*2+1] !== 0) begin
$display("FAILED 4th test, expected \"-1\", got %s", str);
pass = 1'b0;
end
$sformat(str, "%0d", ((s >> 0) + 1) * -1);
if (str[8*2:1] !== "-2" || str[8*40:8*2+1] !== 0) begin
$display("FAILED 5th test, expected \"-2\", got %s", str);
pass = 1'b0;
end
$sformat(str, "%0d", ((s >> 64) + 1) * -1);
if (str[8*2:1] !== "-1" || str[8*40:8*2+1] !== 0) begin
$display("FAILED 6th test, expected \"-1\", got %s", str);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t;
sub #(.WIDTH(4)) sub4();
sub #(.WIDTH(8)) sub8();
logic [3:0] out4;
logic [7:0] out8;
initial begin
out4 = sub4.orer(4'b1000);
out8 = sub8.orer(8'b10000000);
if (out4 != 4'b1011) $stop;
if (out8 != 8'b10111111) $stop;
out4 = sub4.orer2(4'b1000);
out8 = sub8.orer2(8'b10000000);
if (out4 != 4'b1001) $stop;
if (out8 != 8'b10011111) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module sub;
parameter WIDTH = 1;
function [WIDTH-1:0] orer;
input [WIDTH-1:0] in;
// IEEE provices no way to override this parameter, basically it's a localparam
parameter MASK_W = WIDTH - 2;
localparam [MASK_W-1:0] MASK = '1;
// verilator lint_off WIDTH
return in | MASK;
// verilator lint_on WIDTH
endfunction
function [WIDTH-1:0] orer2;
input [WIDTH-1:0] in;
// Same param names as other function to check we disambiguate
// IEEE provices no way to override this parameter, basically it's a localparam
parameter MASK_W = WIDTH - 3;
localparam [MASK_W-1:0] MASK = '1;
// verilator lint_off WIDTH
return in | MASK;
// verilator lint_on WIDTH
endfunction
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); int n; cin >> n; vector<int> scores; for (int i = 0; i < n; i++) { int temp; cin >> temp; scores.push_back(temp); } int max = scores[0]; int min = scores[0]; int count = 0; for (int s : scores) { if (s > max) { max = s; count++; } if (s < min) { min = s; count++; } } cout << count << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; inline int in() { int x, y; y = scanf( %d , &x); return x; } const int MAXN = 2e6 + 10; int n, p[MAXN], sec[MAXN], pt[MAXN]; string s; int nxt[MAXN], prv[MAXN]; int d[MAXN][2]; bool ok(int mid, int sz) { memset(d, 0, sizeof(d)); d[0][0] = d[0][1] = 1; for (int i = 1; i <= n; i++) { if (s[i - 1] == . ) d[i][0] = d[i - 1][0]; else if (s[i - 1] == P ) d[i][0] = d[i - 1][1]; else { int xx = prv[i - 1]; if (~xx && xx + mid >= i - 1) { d[i][0] |= d[xx][0]; int temp = prv[xx]; if (~temp && temp + mid >= i - 1) { int t = max(0, xx - mid); int temp2 = 0; if (t && nxt[t - 1] < temp) temp2 = 1; d[i][0] |= d[t][temp2]; } } } int xx = nxt[i - 1]; if (xx < n) { int temp = max(0, xx - mid); temp = min(temp, i); int temp2 = 0; if (temp && nxt[temp - 1] < xx) temp2 = 1; d[i][1] |= d[temp][temp2]; } } return d[n][0]; } int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n >> s; int sz = 0, c = 0; for (int i = 0; i < n; i++) if (s[i] == P ) sec[sz++] = i; else if (s[i] == * ) c++; int mn = 1e9, mx = -1; for (int i = 0; i < n; i++) { p[i + 1] = p[i]; if (s[i] == * ) { p[i + 1]++; mn = min(mn, i); mx = max(mx, i); } } int last = n; for (int i = n - 1; ~i; i--) { nxt[i] = last; if (s[i] == P ) last = i; } last = -1; for (int i = 0; i < n; i++) { prv[i] = last; if (s[i] == P ) last = i; } memcpy(pt, p, sizeof(p)); if (sz == 1) { if (mn > sec[0]) cout << c << << mx - sec[0] << n ; else if (mx < sec[0]) cout << c << << sec[0] - mn << n ; else { if (p[sec[0]] > c - p[sec[0]]) cout << p[sec[0]] << << sec[0] - mn << n ; else if (p[sec[0]] < c - p[sec[0]]) cout << c - p[sec[0]] << << mx - sec[0] << n ; else cout << p[sec[0]] << << min(sec[0] - mn, mx - sec[0]) << n ; } } else { int lo = 0, hi = n - 1; while (hi - lo > 1) { int mid = hi + lo >> 1; if (ok(mid, sz)) hi = mid; else lo = mid; } cout << c << << hi << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long int b[101]; int main() { long long int n; cin >> n; long long int a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; b[a[i]]++; } long long int ans = 0; for (int i = 1; i < 101; i++) { if (b[i] >= ans) { ans = b[i]; } } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int d[105], n, sum1 = 0, sum2 = 0, begin, end; cin >> n; for (int i = 1; i <= n; i++) cin >> d[i]; cin >> begin >> end; if (begin > end) { int t; t = begin; begin = end; end = t; } for (int i = begin; i < end; i++) sum1 += d[i]; for (int i = end; i != begin; i++) { sum2 += d[i]; if (i >= n) i = 0; } sum1 = sum1 > sum2 ? sum2 : sum1; cout << sum1 << endl; return 0; } |
#include <bits/stdc++.h> int main() { int n; scanf( %d , &n); if (n % 5 == 0) printf( %d , n / 5); else printf( %d , (n / 5) + 1); return 0; } |
#include <bits/stdc++.h> using namespace std; int N, M, neg, nsus; int ar[100002]; int cnt[100002]; int sus[100002]; int main() { scanf( %d%d , &N, &M); for (int i = 1; i <= N; i++) { scanf( %d , &ar[i]); if (ar[i] > 0) cnt[ar[i]]++; else { cnt[-ar[i]]--; neg++; } } for (int i = 1; i <= N; i++) if (cnt[i] + neg == M) { sus[i] = 1; nsus++; } for (int i = 1; i <= N; i++) { if ((ar[i] < 0 && !sus[-ar[i]]) || (ar[i] > 0 && sus[ar[i]] && nsus == 1)) printf( Truth n ); else if ((ar[i] < 0 && sus[-ar[i]] && nsus == 1) || (ar[i] > 0 && !sus[ar[i]])) printf( Lie n ); else printf( Not defined n ); } } |
#include <bits/stdc++.h> #include<stdlib.h> using namespace std; #define pb push_back #define ll long long #define ff first #define ss second #define ppb pop_back #define mp make_pair #define vl vector<ll> #define vi vector<int> #define endl n #define all(x) x.begin(), x.end() #define deb(x) cout << #x << << x << endl; #define f(i, n) for(i=0; i<n; i++) #define F(i, k, n) for(i=k; i<n; i++) #define max(a,b) (a<b?b:a) #define min(a,b) (a>b?b:a) #define INF 1001001001 #define PI 3.1415926535897932384626 #define MOD 1000000007 void FAST() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); } // template<typename... T> // void read(T&... args) { // FAST(); // ((cin >> args), ...); // } // template<typename... T> // void write(T&&... args) { // FAST(); // ((cout << args << ), ...); // } // template<typename T> // T gcd(T a, T b) { // if (b == 0) // return a; // return gcd(b, a % b); // } // template <typename T> // void printContainer(T &v){ // for(auto i : v){ // cout<<i<< ; // } // cout <<endl; // } int main() { FAST(); //code ll t; cin>>t; ll p; f(p,t){ string s; cin>>s; ll i, a1=0, x1=0, x2=0, a2=0,b1=0,b2=0; f(i,s.size()){ if(s[i]== ( ){ a1++; x1++; } else if(s[i]== ) && x1>0){ a2++; x1--; } else if(s[i]== [ ){ b1++; x2++; } else if(s[i]== ] && x2>0){ b2++; x2--; } } cout<<min(a1,a2)+min(b1,b2)<<endl; } return 0; } |
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module gerneric_fifo (
clk, reset, write, read,
data_in,
full,
empty,
data_out,
size
);
parameter DATA_SIZE = 32;
parameter DEPTH = 8;
input wire clk, reset, write, read;
input wire [DATA_SIZE-1:0] data_in;
output wire full;
output reg empty;
output reg [DATA_SIZE-1:0] data_out;
`include "../includes/log2func.v"
reg [DATA_SIZE:0] mem [DEPTH-1:0];
parameter POINTER_SIZE = `CLOG2(DEPTH);
reg [POINTER_SIZE-1:0] rd_ponter, rd_tmp, wr_pointer;
output reg [POINTER_SIZE-1:0] size;
wire empty_loc;
always@(posedge clk) begin
if(reset)
rd_ponter <= 0;
else if(read && !empty) begin
if(rd_ponter == DEPTH-1)
rd_ponter <= 0;
else
rd_ponter <= rd_ponter + 1;
end
end
always@(*) begin
rd_tmp = rd_ponter;
if(read && !empty) begin
if(rd_ponter == DEPTH-1)
rd_tmp = 0;
else
rd_tmp = rd_ponter + 1;
end
end
always@(posedge clk) begin
if(reset)
wr_pointer <= 0;
else if(write && !full) begin
if(wr_pointer == DEPTH-1)
wr_pointer <= 0;
else
wr_pointer <= wr_pointer + 1;
end
end
always@(posedge clk)
if(read && !empty)
if(rd_ponter == DEPTH-1)
empty <= (wr_pointer == 0);
else
empty <= (wr_pointer == rd_ponter+1);
else
empty <= empty_loc;
assign empty_loc = (wr_pointer == rd_ponter);
assign full = ((wr_pointer==(DEPTH-1) && rd_ponter==0) || (wr_pointer!=(DEPTH-1) && wr_pointer+1 == rd_ponter));
always@(posedge clk)
if(write && !full)
mem[wr_pointer] <= data_in;
always@(posedge clk)
//if(read && !empty)
data_out <= mem[rd_tmp];
always @ (*) begin
if(wr_pointer >= rd_ponter)
size = wr_pointer - rd_ponter;
else
size = wr_pointer + (DEPTH-rd_ponter);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const double pi = acos(-1.0); const int mod = 1000000007; const int inf = 0x3f3f3f3f; const int maxn = 200005; void task() { int r1, c1, r2, c2; cin >> r1 >> c1 >> r2 >> c2; int Rook = 0, Bishop = 0, King = 0; if (r1 == r2 or c1 == c2) Rook = 1; else Rook = 2; if ((r1 + c1) == (r2 + c2) or (r2 - r1) == (c2 - c1)) Bishop = 1; else if ((r1 + c1) % 2 == (r2 + c2) % 2) Bishop = 2; else Bishop = 0; King = max(abs(r1 - r2), abs(c1 - c2)); cout << Rook << << Bishop << << King << n ; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int T = 1; while (T--) { task(); } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:16:03 03/03/2016
// Design Name:
// Module Name: data_memory
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module data_memory( clock_in,address,writeData,memWrite,memRead,readData);
input clock_in;
input [31:0] address;
input [31:0] writeData;
input memWrite;
input memRead;
output [31:0] readData;
reg [31:0] memFile[0:31];
reg [31:0] readData;
integer i;
initial
begin
memFile[0] = 32'h00000000;
memFile[1] = 32'h00000001;
memFile[2] = 32'h00000002;
memFile[3] = 32'h00000003;
memFile[4] = 32'h00000004;
memFile[5] = 32'h00000005;
memFile[6] = 32'h00000006;
memFile[7] = 32'h00000007;
memFile[8] = 32'h00000008;
memFile[9] = 32'h00000009;
memFile[10] = 32'h0000000a;
memFile[11] = 32'h0000000b;
memFile[12] = 32'h0000000c;
memFile[13] = 32'h0000000d;
memFile[14] = 32'h0000000e;
memFile[15] = 32'h0000000f;
memFile[16] = 32'h00000010;
memFile[17] = 32'h00000011;
memFile[18] = 32'h00000012;
memFile[19] = 32'h00000013;
memFile[20] = 32'h00000014;
memFile[21] = 32'h00000015;
memFile[22] = 32'h00000016;
memFile[23] = 32'h00000017;
memFile[24] = 32'h00000018;
memFile[25] = 32'h00000019;
memFile[26] = 32'h0000001a;
memFile[27] = 32'h0000001b;
memFile[28] = 32'h0000001c;
memFile[29] = 32'h0000001d;
memFile[30] = 32'h0000001e;
memFile[31] = 32'h0000001f;
end
always @ (memRead or address) //Ïò´æ´¢Æ÷ÖжÁÊý¾Ý
begin
readData = memFile[address];
end
always @ (negedge clock_in) //Ïò´æ´¢Æ÷ÖÐдÊý¾Ý
begin
if(memWrite)
memFile[address] = writeData;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; vector<int> a(n), b(n), c(n); for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) cin >> b[i]; int ans = INT_MAX; sort(a.begin(), a.end()); sort(b.begin(), b.end()); for (int i = 0; i < n; i++) { int x = (b[i] - a[0] + m) % m; for (int j = 0; j < n; j++) c[j] = (a[j] + x) % m; sort(c.begin(), c.end()); if (c == b) ans = min(ans, x); } cout << ans << endl; } |
//#############################################################################
//# Function: MIO Configuration Registers #
//# (See README.md for complete documentation) #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in this repository) #
//#############################################################################
`include "mio_regmap.vh"
module mio_regs #(parameter N = 8, // number of I/O pins
parameter AW = 32, // address width
parameter PW = 104, // packet width
parameter DEF_CFG = 0, // reset MIO_CONFIG value
parameter DEF_CLK = 0 // reset MIO_CLKDIV value
)
(
// clk,reset
input clk,
input nreset,
// register access interface
input access_in, // incoming access
input [PW-1:0] packet_in, // incoming packet
output wait_out,
output access_out, // outgoing read packet
output [PW-1:0] packet_out, // outgoing read packet
input wait_in,
// config outputs
output tx_en, // enable tx
output rx_en, // enable rx
output ddr_mode, // ddr mode for mio
output emode, // epiphany packet mode
output amode, // mio packet mode
output dmode, // mio packet mode
output [7:0] datasize, // mio datasize
output lsbfirst, // lsb shift first
output framepol, // framepolarity (0=actrive high)
output [4:0] ctrlmode, // emode ctrlmode
output [AW-1:0] dstaddr, // destination address for RX dmode
output clkchange, // indicates a clock change
output [7:0] clkdiv, // mio clk clock setting
output [15:0] clkphase0, // [7:0]=rising,[15:8]=falling
output [15:0] clkphase1, // [7:0]=rising,[15:8]=falling
// status inputs
input tx_full, //tx fifo is full (should not happen!)
input tx_prog_full, //tx fifo is nearing full
input tx_empty, //tx fifo is empty
input rx_full, //rx fifo is full (should not happen!)
input rx_prog_full, //rx fifo is nearing full
input rx_empty //rx fifo is empty
);
localparam DEF_RISE0 = 0; // 0 degrees
localparam DEF_FALL0 = ((DEF_CLK+8'd1)>>8'd1); // 180 degrees
localparam DEF_RISE1 = ((DEF_CLK+8'd1)>>8'd2); // 90 degrees
localparam DEF_FALL1 = ((DEF_CLK+8'd1)>>8'd2)+
((DEF_CLK+8'd1)>>8'd1); // 270 degrees
//##############
//# LOCAL WIRES
//##############
reg [20:0] config_reg;
reg [15:0] status_reg;
reg [31:0] clkdiv_reg;
reg [63:0] addr_reg;
reg [31:0] clkphase_reg;
wire [7:0] status_in;
wire reg_write;
wire config_write;
wire status_write;
wire clkdiv_write;
wire clkphase_write;
wire idelay_write;
wire odelay_write;
wire addr0_write;
wire addr1_write;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [4:0] ctrlmode_in; // From p2e of packet2emesh.v
wire [AW-1:0] data_in; // From p2e of packet2emesh.v
wire [1:0] datamode_in; // From p2e of packet2emesh.v
wire [AW-1:0] dstaddr_in; // From p2e of packet2emesh.v
wire [AW-1:0] srcaddr_in; // From p2e of packet2emesh.v
wire write_in; // From p2e of packet2emesh.v
// End of automatics
//#####################################
//# DECODE
//#####################################
packet2emesh #(.AW(AW),
.PW(PW))
p2e (/*AUTOINST*/
// Outputs
.write_in (write_in),
.datamode_in (datamode_in[1:0]),
.ctrlmode_in (ctrlmode_in[4:0]),
.dstaddr_in (dstaddr_in[AW-1:0]),
.srcaddr_in (srcaddr_in[AW-1:0]),
.data_in (data_in[AW-1:0]),
// Inputs
.packet_in (packet_in[PW-1:0]));
assign reg_write = write_in & access_in;
assign config_write = reg_write & (dstaddr_in[5:2]==`MIO_CONFIG);
assign status_write = reg_write & (dstaddr_in[5:2]==`MIO_STATUS);
assign clkdiv_write = reg_write & (dstaddr_in[5:2]==`MIO_CLKDIV);
assign clkphase_write = reg_write & (dstaddr_in[5:2]==`MIO_CLKPHASE);
assign idelay_write = reg_write & (dstaddr_in[5:2]==`MIO_IDELAY);
assign odelay_write = reg_write & (dstaddr_in[5:2]==`MIO_ODELAY);
assign addr0_write = reg_write & (dstaddr_in[5:2]==`MIO_ADDR0);
assign addr1_write = reg_write & (dstaddr_in[5:2]==`MIO_ADDR1);
assign clkchange = clkdiv_write | clkphase_write;
//################################
//# CONFIG
//################################
always @ (posedge clk or negedge nreset)
if(!nreset)
begin
config_reg[20:0] <= DEF_CFG;
end
else if(config_write)
config_reg[20:0] <= data_in[20:0];
assign tx_en = ~config_reg[0]; // tx disable
assign rx_en = ~config_reg[1]; // rx disable
assign emode = config_reg[3:2]==2'b00; // emesh packets
assign dmode = config_reg[3:2]==2'b01; // data mode (streaming)
assign amode = config_reg[3:2]==2'b10; // auto address mode
assign datasize[7:0] = config_reg[11:4]; // number of flits per packet
assign ddr_mode = config_reg[12]; // dual data rate mode
assign lsbfirst = config_reg[13]; // lsb-first transmit
assign framepol = config_reg[14]; // frame polarity
assign ctrlmode[4:0] = config_reg[20:16]; // ctrlmode
//###############################
//# STATUS
//################################
assign status_in[7:0] = {2'b0, //7:6
tx_full, //5
tx_prog_full,//4
tx_empty, //3
rx_full, //2
rx_prog_full,//1
rx_empty //0
};
always @ (posedge clk or negedge nreset)
if(!nreset)
status_reg[15:0] <= 'b0;
else if(status_write)
status_reg[15:0] <= data_in[7:0];
else
status_reg[15:0] <= {(status_reg[15:8] | status_in[7:0]), // sticky bits
status_in[7:0]}; // immediate bits
//###############################
//# CLKDIV
//################################
always @ (posedge clk or negedge nreset)
if(!nreset)
clkdiv_reg[7:0] <= DEF_CLK;
else if(clkdiv_write)
clkdiv_reg[7:0] <= data_in[7:0];
assign clkdiv[7:0] = clkdiv_reg[7:0];
//###############################
//# CLKPHASE
//################################
always @ (posedge clk or negedge nreset)
if(!nreset)
begin
clkphase_reg[7:0] <= DEF_RISE0;
clkphase_reg[15:8] <= DEF_FALL0;
clkphase_reg[23:16] <= DEF_RISE1;
clkphase_reg[31:24] <= DEF_FALL1;
end
else if(clkphase_write)
clkphase_reg[31:0] <= data_in[31:0];
assign clkphase0[15:0] = clkphase_reg[15:0];
assign clkphase1[15:0] = clkphase_reg[31:16];
//###############################
//# RX DESTINATION ADDR ("AMODE")
//################################
always @ (posedge clk)
if(addr0_write)
addr_reg[31:0] <= data_in[31:0];
else if(addr1_write)
addr_reg[63:32] <= data_in[31:0];
assign dstaddr[AW-1:0] = addr_reg[AW-1:0];
//###############################
//# READBACK
//################################
assign access_out ='b0;
assign wait_out ='b0;
assign packet_out ='b0;
endmodule
// Local Variables:
// verilog-library-directories:("." "../../emesh/hdl" "../../../oh/common/hdl")
// End:
|
#include <bits/stdc++.h> using namespace std; string s[1005]; long long a[1005]; long long ans; long long b[1005][5]; long long ma; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, m; cin >> n >> m; for (long long i = 1; i <= n; i++) { cin >> s[i]; } for (long long i = 0; i < m; i++) { cin >> a[i]; } for (long long i = 0; i < m; i++) { ma = 0; for (long long j = 1; j <= n; j++) { b[i][s[j][i] - A ]++; } for (long long j = 0; j < 5; j++) { ma = max(ma, b[i][j]); } ans += ma * a[i]; } cout << ans; } |
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: alt_rom.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.0.1 Build 150 06/03/2015 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
module alt_rom (
address,
clock,
q);
input [11:0] address;
input clock;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./bootrom.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "32"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./bootrom.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_rom.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_rom.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_rom.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_rom.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_rom_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_rom_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// ==================================================================
// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ------------------------------------------------------------------
// Copyright (c) 2013 by Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// ------------------------------------------------------------------
//
// Permission:
//
// Lattice SG Pte. Ltd. grants permission to use this code
// pursuant to the terms of the Lattice Reference Design License Agreement.
//
//
// Disclaimer:
//
// This VHDL or Verilog source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Lattice provides no warranty
// regarding the use or functionality of this code.
//
// --------------------------------------------------------------------
//
// Lattice SG Pte. Ltd.
// 101 Thomson Road, United Square #07-02
// Singapore 307591
//
//
// TEL: 1-800-Lattice (USA and Canada)
// +65-6631-2000 (Singapore)
// +1- (other locations)
//
// web: http://www.latticesemi.com/
// email:
//
// --------------------------------------------------------------------
//
`timescale 1 ns / 1 ps
`define DISABLE_CPU_IO_BUS 1
module sdram_controller (/*AUTOARG*/
// Outputs
o_data_valid, o_data_req, o_busy, o_init_done, o_ack,
o_sdram_addr, o_sdram_blkaddr, o_sdram_casn, o_sdram_cke,
o_sdram_csn, o_sdram_dqm, o_sdram_rasn, o_sdram_wen, o_sdram_clk,
o_write_done, o_read_done,
// Inouts
`ifdef DISABLE_CPU_IO_BUS
i_data,
o_data,
`else
io_data,
`endif
io_sdram_dq,
// Inputs
i_addr, i_adv, i_clk, i_rst, i_rwn,
i_selfrefresh_req, i_loadmod_req, i_burststop_req, i_disable_active, i_disable_precharge, i_precharge_req, i_power_down, i_disable_autorefresh
);
`include "sdram_defines.vh"
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [26:0] i_addr; // To U0 of sdram_control_fsm.v
input i_adv; // To U0 of sdram_control_fsm.v
input i_clk; // To U0 of sdram_control_fsm.v
input i_rst; // To U0 of sdram_control_fsm.v
input i_rwn; // To U0 of sdram_control_fsm.v
input i_selfrefresh_req; // To U0 of sdram_control_fsm.v
input i_loadmod_req; // To U0 of sdram_control_fsm.v
input i_burststop_req; // To U0 of sdram_control_fsm.v
input i_disable_active;
input i_disable_precharge;
input i_precharge_req;
input i_power_down;
input i_disable_autorefresh;
/*AUTOOUTPUT*/
// End of automatics
output o_data_valid; // From U0 of sdram_control_fsm.v
output o_data_req; // From U0 of sdram_control_fsm.v
output o_busy; // From U0 of sdram_control_fsm.v
output o_init_done; // From U0 of sdram_control_fsm.v
output o_ack; // From U0 of sdram_control_fsm.v
output [12:0] o_sdram_addr; // From U0 of sdram_control_fsm.v
output [1:0] o_sdram_blkaddr;// From U0 of sdram_control_fsm.v
output o_sdram_casn; // From U0 of sdram_control_fsm.v
output o_sdram_cke; // From U0 of sdram_control_fsm.v
output o_sdram_csn; // From U0 of sdram_control_fsm.v
output [3:0] o_sdram_dqm; // From U0 of sdram_control_fsm.v
output o_sdram_rasn; // From U0 of sdram_control_fsm.v
output o_sdram_wen; // From U0 of sdram_control_fsm.v
output o_sdram_clk; // From U0 of sdram_control_fsm.v
output o_write_done;
output o_read_done;
/*AUTOINOUT*/
`ifdef DISABLE_CPU_IO_BUS
input [31:0] i_data; // To/From U0 of sdram_control_fsm.v
output [31:0] o_data; // To/From U0 of sdram_control_fsm.v
`else
inout [31:0] io_data; // To/From U0 of sdram_control_fsm.v
`endif
inout [31:0] io_sdram_dq; // To/From U0 of sdram_control_fsm.v
wire delay_done150us_i; // To U0 of sdram_control_fsm.v
wire refresh_count_done_i; // From U2 of autorefresh_counter.v
wire autoref_ack_i, init_done_i, sdrctl_busyn_i;
reg latch_ref_req_i;
reg refresh_req_i;
reg autorefresh_enable_i;
wire cpu_den_i;
wire [CPU_DATA_WIDTH-1:0] cpu_datain_i; // To/From U0 of sdram_control_fsm.v
wire [CPU_DATA_WIDTH-1:0] cpu_dataout_i; // To/From U0 of sdram_control_fsm.v
`ifdef DISABLE_CPU_IO_BUS
assign #WIREDLY o_data = cpu_dataout_i;
assign #WIREDLY cpu_datain_i = i_data;
`else
assign #WIREDLY io_data = (cpu_den_i) ? cpu_dataout_i : {`CPU_DBUS_LEN{1'bz}};
assign #WIREDLY cpu_datain_i = io_data;
`endif
reg power_down_reg1_i;
reg power_down_reg2_i;
reg power_down_reg3_i;
always @(posedge i_clk or posedge i_rst) begin
if (i_rst) begin
power_down_reg1_i <= 1'b0; end
else begin
power_down_reg1_i <= i_power_down; end
end
assign o_sdram_clk = i_clk ? ~(power_down_reg1_i) : 1'b0;
assign o_init_done = init_done_i;
assign sys_clk_i = i_clk;
assign sys_rst_i = i_rst;
assign o_busy = sdrctl_busyn_i;
sdram_control_fsm U0 (/*AUTOINST*/
// Outputs
.o_ack (o_ack),
.o_autoref_ack (autoref_ack_i),
.o_busy (sdrctl_busyn_i),
.o_init_done (init_done_i),
.o_sdram_cke (o_sdram_cke),
.o_sdram_csn (o_sdram_csn),
.o_sdram_rasn (o_sdram_rasn),
.o_sdram_casn (o_sdram_casn),
.o_sdram_wen (o_sdram_wen),
.o_sdram_blkaddr (o_sdram_blkaddr[SDRAM_BLKADR_WIDTH-1:0]),
.o_sdram_addr (o_sdram_addr[SDRAM_ADDR_WIDTH-1:0]),
.o_data_valid (o_data_valid),
.o_data_req (o_data_req),
.o_sdram_dqm (o_sdram_dqm[SDRAM_DQM_WIDTH-1:0]),
.o_write_done (o_write_done),
.o_read_done (o_read_done),
// Inouts
.i_data (i_data[CPU_DATA_WIDTH-1:0]),
.o_data (cpu_dataout_i[CPU_DATA_WIDTH-1:0]),
.o_den (cpu_den_i),
.io_sdram_dq (io_sdram_dq[SDRAM_DATA_WIDTH-1:0]),
// Inputs
.i_clk (i_clk),
.i_rst (i_rst),
.i_rwn (i_rwn),
.i_adv (i_adv),
.i_delay_done_100us (delay_done150us_i),
.i_refresh_req (refresh_req_i),
.i_selfrefresh_req (i_selfrefresh_req),
.i_loadmod_req (i_loadmod_req),
.i_burststop_req (i_burststop_req),
.i_disable_active (i_disable_active),
.i_disable_precharge (i_disable_precharge),
.i_precharge_req (i_precharge_req),
.i_power_down (i_power_down),
.i_addr (i_addr[ROWADDR_MSB:COLADDR_LSB]));
delay_gen150us U1 (/*AUTOINST*/
// Outputs
.o_lfsr_256_done (delay_done150us_i),
// Inputs
.i_sys_clk (sys_clk_i),
.i_sys_rst (sys_rst_i));
autorefresh_counter U2(/*AUTOINST*/
// Outputs
.o_refresh_count_done(refresh_count_done_i),
// Inputs
.i_sys_clk (sys_clk_i),
.i_sys_rst (sys_rst_i),
.i_autorefresh_enable(autorefresh_enable_i));
//Latch auto refresh request and clear it after ack
always @(posedge i_clk or posedge i_rst)
if (i_rst)
latch_ref_req_i <= #WIREDLY 0;
else if (latch_ref_req_i && autoref_ack_i)
latch_ref_req_i <= #WIREDLY 0;
else
latch_ref_req_i <= #WIREDLY refresh_count_done_i;
//Issue refresh request when SDRAM Controller initialization done and is not busy
always @(posedge i_clk or posedge i_rst)
if (i_rst)
refresh_req_i <= #WIREDLY 0;
else if (i_disable_autorefresh)
refresh_req_i <= #WIREDLY 0;
else if (init_done_i && ~sdrctl_busyn_i)
refresh_req_i <= #WIREDLY latch_ref_req_i;
else
refresh_req_i <= #WIREDLY 0;
//Enable auto refresh counter after initialization and not under self refresh state
always @(posedge i_clk or posedge i_rst)
if (i_rst)
autorefresh_enable_i <= #WIREDLY 0;
else if (init_done_i && ~i_selfrefresh_req)
autorefresh_enable_i <= #WIREDLY 1;
else
autorefresh_enable_i <= #WIREDLY 0;
endmodule // sdram_controller
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR3B_PP_SYMBOL_V
`define SKY130_FD_SC_HS__NOR3B_PP_SYMBOL_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nor3b (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR3B_PP_SYMBOL_V
|
/*
reset...init...save.start_write.stop_write.restore.start_read(compare).stop_read.loop
error...
*/
module mem_tester(
clk,
rst_n,
led, // LED flashing or not
// SRAM signals
SRAM_DQ, // sram inout databus
SRAM_ADDR, // sram address bus
SRAM_UB_N,
SRAM_LB_N,
SRAM_WE_N, //
SRAM_CE_N, //
SRAM_OE_N //
);
parameter SRAM_DATA_SIZE = 8;
parameter SRAM_ADDR_SIZE = 19;
inout [SRAM_DATA_SIZE-1:0] SRAM_DQ;
wire [SRAM_DATA_SIZE-1:0] SRAM_DQ;
output [SRAM_ADDR_SIZE-1:0] SRAM_ADDR;
wire [SRAM_ADDR_SIZE-1:0] SRAM_ADDR;
output SRAM_UB_N,SRAM_LB_N,SRAM_WE_N,SRAM_CE_N,SRAM_OE_N;
wire SRAM_UB_N,SRAM_LB_N,SRAM_WE_N,SRAM_CE_N,SRAM_OE_N;
input clk;
input rst_n;
output led; reg led;
reg inc_pass_ctr; // increment passes counter (0000-9999 BCD)
reg inc_err_ctr; // increment errors counter (10 red binary LEDs)
reg check_in_progress; // when 1 - enables errors checking
reg [19:0] ledflash;
reg was_error;
initial ledflash='d0;
always @(posedge clk)
begin
if( inc_pass_ctr )
ledflash <= 20'd0;
else if( !ledflash[19] )
ledflash <= ledflash + 20'd1;
end
always @(posedge clk)
begin
led <= ledflash[19] ^ was_error;
end
always @(posedge clk, negedge rst_n)
begin
if( !rst_n )
was_error <= 1'b0;
else if( inc_err_ctr )
was_error <= 1'b1;
end
reg rnd_init,rnd_save,rnd_restore; // rnd_vec_gen control
wire [SRAM_DATA_SIZE-1:0] rnd_out; // rnd_vec_gen output
reg sram_start,sram_rnw;
wire sram_stop,sram_ready;
rnd_vec_gen my_rnd( .clk(clk), .init(rnd_init), .next(sram_ready), .save(rnd_save), .restore(rnd_restore), .out(rnd_out) );
defparam my_rnd.OUT_SIZE = SRAM_DATA_SIZE;
defparam my_rnd.LFSR_LENGTH = 41;
defparam my_rnd.LFSR_FEEDBACK = 3;
wire [SRAM_DATA_SIZE-1:0] sram_rdat;
sram_control my_sram( .clk(clk), .clk2(clk), .start(sram_start), .rnw(sram_rnw), .stop(sram_stop), .ready(sram_ready),
.rdat(sram_rdat), .wdat(rnd_out),
.SRAM_DQ(SRAM_DQ), .SRAM_ADDR(SRAM_ADDR),
.SRAM_CE_N(SRAM_CE_N), .SRAM_OE_N(SRAM_OE_N), .SRAM_WE_N(SRAM_WE_N) );
defparam my_sram.SRAM_DATA_SIZE = SRAM_DATA_SIZE;
defparam my_sram.SRAM_ADDR_SIZE = SRAM_ADDR_SIZE;
// FSM states and registers
reg [3:0] curr_state,next_state;
parameter RESET = 4'h0;
parameter INIT1 = 4'h1;
parameter INIT2 = 4'h2;
parameter BEGIN_WRITE1 = 4'h3;
parameter BEGIN_WRITE2 = 4'h4;
parameter BEGIN_WRITE3 = 4'h5;
parameter BEGIN_WRITE4 = 4'h6;
parameter WRITE = 4'h7;
parameter BEGIN_READ1 = 4'h8;
parameter BEGIN_READ2 = 4'h9;
parameter BEGIN_READ3 = 4'hA;
parameter BEGIN_READ4 = 4'hB;
parameter READ = 4'hC;
parameter END_READ = 4'hD;
parameter INC_PASSES1 = 4'hE;
parameter INC_PASSES2 = 4'hF;
// FSM dispatcher
always @*
begin
case( curr_state )
RESET:
next_state <= INIT1;
INIT1:
if( sram_stop )
next_state <= INIT2;
else
next_state <= INIT1;
INIT2:
next_state <= BEGIN_WRITE1;
BEGIN_WRITE1:
next_state <= BEGIN_WRITE2;
BEGIN_WRITE2:
next_state <= BEGIN_WRITE3;
BEGIN_WRITE3:
next_state <= BEGIN_WRITE4;
BEGIN_WRITE4:
next_state <= WRITE;
WRITE:
if( sram_stop )
next_state <= BEGIN_READ1;
else
next_state <= WRITE;
BEGIN_READ1:
next_state <= BEGIN_READ2;
BEGIN_READ2:
next_state <= BEGIN_READ3;
BEGIN_READ3:
next_state <= BEGIN_READ4;
BEGIN_READ4:
next_state <= READ;
READ:
if( sram_stop )
next_state <= END_READ;
else
next_state <= READ;
END_READ:
next_state <= INC_PASSES1;
INC_PASSES1:
next_state <= INC_PASSES2;
INC_PASSES2:
next_state <= BEGIN_WRITE1;
default:
next_state <= RESET;
endcase
end
// FSM sequencer
always @(posedge clk,negedge rst_n)
begin
if( !rst_n )
curr_state <= RESET;
else
curr_state <= next_state;
end
// FSM controller
always @(posedge clk)
begin
case( curr_state )
//////////////////////////////////////////////////
RESET:
begin
// various initializings begin
inc_pass_ctr <= 1'b0;
check_in_progress <= 1'b0;
rnd_init <= 1'b1; //begin RND init
rnd_save <= 1'b0;
rnd_restore <= 1'b0;
sram_start <= 1'b1;
sram_rnw <= 1'b1; // start condition for sram controller, in read mode
end
INIT1:
begin
sram_start <= 1'b0; // end sram start
end
INIT2:
begin
rnd_init <= 1'b0; // end rnd init
end
//////////////////////////////////////////////////
BEGIN_WRITE1:
begin
rnd_save <= 1'b1;
sram_rnw <= 1'b0;
end
BEGIN_WRITE2:
begin
rnd_save <= 1'b0;
sram_start <= 1'b1;
end
BEGIN_WRITE3:
begin
sram_start <= 1'b0;
end
/* BEGIN_WRITE4:
begin
rnd_save <= 1'b0;
sram_start <= 1'b1;
end
WRITE:
begin
sram_start <= 1'b0;
end
*/
//////////////////////////////////////////////////
BEGIN_READ1:
begin
rnd_restore <= 1'b1;
sram_rnw <= 1'b1;
end
BEGIN_READ2:
begin
rnd_restore <= 1'b0;
sram_start <= 1'b1;
end
BEGIN_READ3:
begin
sram_start <= 1'b0;
check_in_progress <= 1'b1;
end
/* BEGIN_READ4:
begin
rnd_restore <= 1'b0;
sram_start <= 1'b1;
end
READ:
begin
sram_start <= 1'b0;
check_in_progress <= 1'b1;
end
*/
END_READ:
begin
check_in_progress <= 1'b0;
end
INC_PASSES1:
begin
inc_pass_ctr <= 1'b1;
end
INC_PASSES2:
begin
inc_pass_ctr <= 1'b0;
end
endcase
end
// errors counter
always @(posedge clk)
inc_err_ctr <= check_in_progress & sram_ready & ((sram_rdat==rnd_out)?0:1);
endmodule
|
`timescale 1 ns / 100 ps
`include "sm_cpu.vh"
module sm_testbench;
// simulation options
parameter Tt = 20;
parameter Ncycle = 120;
reg clk;
reg rst_n;
reg [ 4:0] regAddr;
wire [31:0] regData;
// ***** DUT start ************************
//instruction memory
wire [31:0] imAddr;
wire [31:0] imData;
sm_rom reset_rom(imAddr, imData);
//cpu core
sm_cpu sm_cpu
(
.clk ( clk ),
.rst_n ( rst_n ),
.regAddr ( regAddr ),
.regData ( regData ),
.imAddr ( imAddr ),
.imData ( imData )
);
// ***** DUT end ************************
`ifdef ICARUS
//iverilog memory dump init workaround
initial $dumpvars;
genvar k;
for (k = 0; k < 32; k = k + 1) begin
initial $dumpvars(0, sm_cpu.rf.rf[k]);
end
`endif
// simulation init
initial begin
clk = 0;
forever clk = #(Tt/2) ~clk;
end
initial begin
rst_n = 0;
repeat (4) @(posedge clk);
rst_n = 1;
end
//register file reset
integer i;
initial begin
for (i = 0; i < 32; i = i + 1)
sm_cpu.rf.rf[i] = 0;
end
task disasmInstr
(
input [31:0] instr
);
reg [ 5:0] cmdOper;
reg [ 5:0] cmdFunk;
reg [ 4:0] cmdRs;
reg [ 4:0] cmdRt;
reg [ 4:0] cmdRd;
reg [ 4:0] cmdSa;
reg [15:0] cmdImm;
reg signed [15:0] cmdImmS;
begin
cmdOper = instr[31:26];
cmdFunk = instr[ 5:0 ];
cmdRs = instr[25:21];
cmdRt = instr[20:16];
cmdRd = instr[15:11];
cmdSa = instr[10:6 ];
cmdImm = instr[15:0 ];
cmdImmS = instr[15:0 ];
$write(" ");
casez( {cmdOper,cmdFunk} )
default : if (instr == 32'b0)
$write ("nop");
else
$write ("new/unknown");
{ `C_SPEC, `F_ADDU } : $write ("addu $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);
{ `C_SPEC, `F_OR } : $write ("or $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);
{ `C_SPEC, `F_SRL } : $write ("srl $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);
{ `C_SPEC, `F_SLTU } : $write ("sltu $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);
{ `C_SPEC, `F_SUBU } : $write ("subu $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);
{ `C_ADDIU, `F_ANY } : $write ("addiu $%1d, $%1d, %1d", cmdRt, cmdRs, cmdImm);
{ `C_LUI, `F_ANY } : $write ("lui $%1d, %1d", cmdRt, cmdImm);
{ `C_BEQ, `F_ANY } : $write ("beq $%1d, $%1d, %1d", cmdRs, cmdRt, cmdImmS + 1);
{ `C_BNE, `F_ANY } : $write ("bne $%1d, $%1d, %1d", cmdRs, cmdRt, cmdImmS + 1);
endcase
end
endtask
//simulation debug output
integer cycle; initial cycle = 0;
initial regAddr = 0; // get PC
always @ (posedge clk)
begin
$write ("%5d pc = %2d pcaddr = %h instr = %h v0 = %1d",
cycle, regData, (regData << 2), sm_cpu.instr, sm_cpu.rf.rf[2]);
disasmInstr(sm_cpu.instr);
$write("\n");
cycle = cycle + 1;
if (cycle > Ncycle)
begin
$display ("Timeout");
$stop;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLXTN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__DLXTN_BEHAVIORAL_PP_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_lp__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dlxtn (
Q ,
D ,
GATE_N,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire GATE ;
wire buf_Q ;
wire GATE_N_delayed;
wire D_delayed ;
reg notifier ;
// Name Output Other arguments
sky130_fd_sc_lp__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE, notifier, VPWR, VGND);
not not0 (GATE , GATE_N_delayed );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLXTN_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; long long power(long long a, long long b) { if (b == 0) return 1; else if (b % 2 == 0) return (power(a, b / 2) * power(a, b / 2)) % 998244353; else return (a * power(a, b / 2) * power(a, b / 2)) % 998244353; } int main() { long long n, num, ma, cnt = 0; map<long long, pair<long long, long long> > mp; vector<pair<long long, long long> > v; cin >> n; for (long long i = 1; i <= n; i++) { cin >> num; if (mp[num].first == 0) mp[num].first = i; mp[num].second = i; } for (auto it = mp.begin(); it != mp.end(); it++) v.push_back({it->second.first, it->second.second}); sort(v.begin(), v.end()); ma = v[0].second; for (long long i = 1; i < v.size(); i++) { if (v[i].first > ma) { cnt++; ma = v[i].second; } else ma = max(ma, v[i].second); } cout << power(2, cnt); } |
#include <bits/stdc++.h> using namespace std; int n, m; int a[200013]; int type[200013], len[200013]; int high[200013]; int res[200013]; multiset<int> has; int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int i = 1; i <= m; i++) scanf( %d%d , &type[i], &len[i]); for (int i = m; i > 0; i--) high[i] = max(high[i + 1], len[i]); for (int i = high[1] + 1; i <= n; i++) res[i] = a[i]; for (int i = 1; i <= high[1]; i++) has.insert(a[i]); int dir = 1; int last = high[1]; for (int i = 1; i <= m + 1; i++) { if (len[i] == high[i]) { while (last > len[i]) { if (dir == 1) { res[last--] = *has.rbegin(); has.erase(--has.end()); } else { res[last--] = *has.begin(); has.erase(has.begin()); } } dir = type[i]; } } for (int i = 1; i <= n; i++) printf( %d , res[i]); printf( n ); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 205; char g[N]; map<char, int> h; void work() { int i, j; int s1 = 0, s2 = 0; h[ q ] = 9; h[ r ] = 5; h[ b ] = 3; h[ n ] = 3; h[ p ] = 1; h[ k ] = 0; for (i = 0; i < 8; ++i) { scanf( %s , g); for (j = 0; j < 8; ++j) if (islower(g[j])) s1 += h[g[j]]; else if (isupper(g[j])) s2 += h[g[j] - A + a ]; } if (s1 > s2) puts( Black ); else if (s1 == s2) puts( Draw ); else puts( White ); } int main() { work(); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:17:07 04/14/2015
// Design Name:
// Module Name: finalcounter
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module finalcounter(
input clk,
input rst,
input [64:1] dectext,
input [1:0] updown,
output reg [6:0] OUT,
output reg [3:0] EN,
input select
);
wire HZ1;
wire HZ100;
wire [3:0] out0, out2;
wire [3:0] out1, out3;
wire [6:0] bcd0, bcd1, bcd2, bcd3;
wire [1:0] sel_MUX;
assign out0 = (updown == 2'b00)? dectext[4:1] : ((updown == 2'b01)? dectext[20:17]: ( ((updown == 2'b10)? dectext[36:33]: ( dectext[52:49]) )) );
assign out1 = (updown == 2'b00)? dectext[8:5] : ((updown == 2'b01)? dectext[24:21]: ( ((updown == 2'b01)? dectext[40:37]: (dectext[56:53]) )) );
assign out2 = (updown == 2'b00)? dectext[12:9] : ((updown == 2'b01)? dectext[28:25]: (((updown == 2'b01)? dectext[44:41]: (dectext[60:57]) )) );
assign out3 = (updown == 2'b00)? dectext[16:13] : ((updown == 2'b01)? dectext[32:29]: (((updown == 2'b01)? dectext[48:45]: (dectext[64:61]) )) );
clockdivide2 divider(.clk(clk),.rst(rst),.clkdivided1hz(HZ1), .clkdivided2hz(HZ100));
BCD7segment BCD0(out0, select,bcd0);
BCD7segment BCD1(out1,select,bcd1);
BCD7segment BCD2(out2,select, bcd2);
BCD7segment BCD3(out3,select, bcd3);
moduloNcounter cont(.clk(HZ100),.rst(rst), .Q(sel_MUX), .EN(1), .N(3));
always @ * //binary decoder
begin
case(sel_MUX)
0: EN = 4'b0111;
1: EN = 4'b1011;
2: EN = 4'b1101;
3: EN = 4'b1110;
endcase
end
always @ * //MUX
begin
case(sel_MUX)
0: OUT = bcd3;
1: OUT = bcd2;
2: OUT = bcd1;
3: OUT = bcd0;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int dy[] = {-1, 0, 1, 0}, dx[] = {0, 1, 0, -1}; const double EPS = 1e-8; const double PI = acos(-1.0); int popcount(int n) { return __builtin_popcount(n); } int popcount(long long n) { return __builtin_popcountll(n); } template <class T> int SIZE(T a) { return a.size(); } template <class T> string IntToString(T num) { string res; stringstream ss; ss << num; return ss.str(); } template <class T> T StringToInt(string str) { T res = 0; for (int i = 0; i < SIZE(str); i++) res = (res * 10 + str[i] - 0 ); return res; } template <class T> T gcd(T a, T b) { if (b == 0) return a; return gcd(b, a % b); } template <class T> T lcm(T a, T b) { return a / gcd(a, b) * b; } template <class T> void PrintSeq(T &a, int sz) { for (int i = 0; i < sz; i++) { cout << a[i]; if (sz == i + 1) cout << endl; else cout << ; } } bool EQ(double a, double b) { return abs(a - b) < EPS; } void fastStream() { cin.tie(0); std::ios_base::sync_with_stdio(0); } vector<string> split(string str, char del) { vector<string> res; for (int i = 0, s = 0; i < SIZE(str); i++) { if (str[i] == del) { if (i - s != 0) res.push_back(str.substr(s, i - s)); s = i + 1; } else if (i == SIZE(str) - 1) { res.push_back(str.substr(s)); } } return res; } int froms[1000001]; int tos[1000001]; vector<pair<int, int> > G[1000001]; bool used[1000001]; void dfs(int pprv, int prv, int now) { used[now] = true; for (int i = 0; i < (int)G[now].size(); i++) { int to = G[now][i].first; int en = G[now][i].second; if (!used[to]) { dfs(prv, en, to); } } if (prv != -1 && pprv != -1) cout << pprv << << prv << endl; } int main() { fastStream(); int N; cin >> N; for (int i = 0; i < N - 1; i++) { cin >> froms[i] >> tos[i]; G[froms[i]].push_back(make_pair(tos[i], i + 1)); G[tos[i]].push_back(make_pair(froms[i], i + 1)); } cout << N - 1 << endl; for (int i = 0; i < N - 1; i++) cout << 2 << << froms[i] << << tos[i] << endl; for (int i = 0; i < N; i++) { if (G[i + 1].size() == 1) { dfs(-1, -1, i + 1); break; } } return 0; } |
#include <bits/stdc++.h> using namespace std; struct gam { int o; long long k; int nez; long long bd; long long kd; gam() { o = 0; k = 0; nez = 0; bd = 0; kd = 0; } }; bool mycomp(gam i, gam j) { return (i.k < j.k); } int main() { long long n; long long r; long long tr; long long sum = 0; cin >> n; cin >> r; cin >> tr; gam* a = new gam[n + 1]; a[0].k = 0; for (int i = 1; i <= n; i++) { cin >> a[i].o; cin >> a[i].k; a[i].nez = r - a[i].o; sum = sum + a[i].o; } sort(a + 1, a + n + 1, mycomp); long long nug = tr * n - sum; if (nug > 0) { int cur; for (int i = 1; i <= n; i++) { a[i].bd = a[i - 1].bd + a[i].nez; a[i].kd = a[i - 1].kd + a[i].k * a[i].nez; if (a[i].bd >= nug) { cur = i; break; } } long long enug = nug - a[cur - 1].bd; long long rez = a[cur - 1].kd + enug * a[cur].k; cout << rez; } else cout << 0; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long inf = 1e9 + 7; const int maxn = 1e5 + 5; int n, m; int a[maxn]; int num[maxn]; int main() { cin >> n; long long sum1 = 0; for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); sum1 += a[i]; } num[n] = a[n]; long long sum2 = 0; for (int i = n - 1; i >= 1; i--) { num[i] = max(a[i], num[i + 1] - 1); } for (int i = 1; i < n; i++) { if (num[i] > num[i + 1]) { num[i + 1] = num[i]; } } for (int i = 1; i <= n; i++) { sum2 += num[i] + 1; } cout << sum2 - sum1 - n << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int te; cin >> te; while (te--) { int n, m, x, ji = 0, ou = 0; cin >> n >> m; for (int i = 0; i < n; ++i) { cin >> x; if (x & 1) ji++; else ou++; } if (ji == 0) { puts( No ); continue; } ji--; m--; int q = min(m / 2 * 2, ji / 2 * 2); m -= q; ou -= m; if (ou < 0) puts( No ); else puts( Yes ); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_DLATCH_P_PP_PG_N_SYMBOL_V
`define SKY130_FD_SC_HD__UDP_DLATCH_P_PP_PG_N_SYMBOL_V
/**
* udp_dlatch$P_pp$PG$N: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_DLATCH_P_PP_PG_N_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e6 + 10; int sum[maxn], op[maxn]; int main() { int n, l = 0, r = 0, ans = 0, minn = 100; string s; cin >> n >> s; for (int i = 0; i < n; i++) { if (s[i] == ( ) { op[i + 1] = 1; sum[i + 1] = sum[i] + 1; l++; } else { op[i + 1] = 0; sum[i + 1] = sum[i] - 1; r++; } } if (n & 1 == 1 || (abs(l - r) > 2) || (sum[n] == 0) || (*min_element(sum + 1, sum + 1 + n) < -2) || (*min_element(sum + 1, sum + 1 + n) < 0 && sum[n] != -2)) { printf( 0 n ); exit(0); } if (sum[n] == -2) { for (int i = 1; i <= n; i++) { if (op[i] == 0 && sum[i] < 0) { ans++; break; } else if (op[i] == 0 && sum[i] >= 0) ans++; } } if (sum[n] == 2) { for (int i = n; i >= 1; i--) { if (sum[i] >= 2) minn = i; else break; } minn = max(minn, 2); for (int i = minn; i <= n; i++) { if (op[i] == 1) ans++; } } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; int b; cin >> n >> b; int a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; } int mini[n]; mini[0] = a[0]; for (int i = 1; i < n; i++) { mini[i] = min(mini[i - 1], a[i]); } int maxi = b; for (int i = 1; i < n; i++) { maxi = max(maxi, b % mini[i] + (b / mini[i]) * a[i]); } cout << maxi; return 0; } |
#include <bits/stdc++.h> using namespace std; #pragma comment(linker, /STACK:1024000000,1024000000 ) long long ans; int son[100010][2], fa[100010], cnt[100010], val[100010]; int is[100010]; long long sumVal[100010], sumCnt[100010], sum[100010], all[100010], lazy[100010]; void up(int p) { sumCnt[p] = sumCnt[son[p][0]] + sumCnt[son[p][1]] + cnt[p]; sumVal[p] = sumVal[son[p][0]] + sumVal[son[p][1]] + val[p]; sum[p] = sum[son[p][0]] + sum[son[p][1]] + 1LL * cnt[p] * val[p]; } void func(int p, long long v) { if (!p) return; all[p] += v * cnt[p]; lazy[p] += v; } void down(int p) { if (lazy[p]) { func(son[p][0], lazy[p]); func(son[p][1], lazy[p]); lazy[p] = 0; } } void Rotate(int x) { int y = fa[x], z = fa[y]; int o = son[y][0] == x; down(y), down(x); son[y][!o] = son[x][o], fa[son[x][o]] = y; son[x][o] = y, fa[y] = x; fa[x] = z; if (is[y]) is[y] = 0, is[x] = 1; else son[z][son[z][1] == y] = x; up(y); } void Splay(int x) { int y, z; down(x); while (!is[x]) { y = fa[x], z = fa[y]; if (is[y]) Rotate(x); else if ((son[y][0] == x) ^ (son[z][0] == y)) Rotate(x), Rotate(x); else Rotate(y), Rotate(x); } up(x); } int Access(int x) { int y = 0; for (; x; x = fa[x]) { Splay(x); is[son[x][1]] = 1; if (son[x][1]) { cnt[x] += sumCnt[son[x][1]]; } son[x][1] = y; if (y) { cnt[x] -= sumCnt[y]; } is[y] = 0; y = x; up(x); } return y; } int vv[100010], nxt[100010], h[100010], e; void add(int u, int v) { vv[e] = v, nxt[e] = h[u], h[u] = e++; } void dfs(int u, int f) { fa[u] = f, is[u] = 1, cnt[u] = 1; son[u][0] = son[u][1] = 0; all[u] = 1; for (int i = h[u]; i + 1; i = nxt[i]) { int v = vv[i]; dfs(v, u); all[u] += 1LL * cnt[v] * cnt[u] * 2; cnt[u] += cnt[v]; } ans += all[u] * val[u]; up(u); } void change(int x, long long v) { Splay(x); ans += (v - val[x]) * all[x]; val[x] = v; up(x); } int getFa(int x) { Splay(x); if (!son[x][0]) return fa[x]; int y = son[x][0]; while (son[y][1]) y = son[y][1]; return y; } void gao(int u, int v) { Access(u); Splay(v); if (!fa[v]) swap(u, v); int f = getFa(v); if (f == u) return; Access(f), Splay(f); cnt[f] -= sumCnt[v], up(f); fa[v] = 0; ans -= 2 * sum[f] * sumCnt[v]; func(f, -2 * sumCnt[v]); Access(u), Splay(u); ans += 2 * sum[u] * sumCnt[v]; func(u, 2 * sumCnt[v]); cnt[u] += sumCnt[v], up(u); fa[v] = u; } int main() { int n; int u; scanf( %d , &n); memset(h, -1, sizeof(h)), e = 0; for (int i = 2; i <= n; ++i) { scanf( %d , &u); add(u, i); } for (int i = 1; i <= n; ++i) scanf( %d , val + i); dfs(1, 0); int m, v; scanf( %d , &m); char c[3]; double mu = 1.0 * n * n; printf( %.10lf n , ans / mu); while (m--) { scanf( %s%d%d , c, &u, &v); if (c[0] == P ) gao(v, u); else change(u, v); printf( %.10lf n , ans / mu); } } |
#include <bits/stdc++.h> using namespace std; int n; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n; int sl = 0; for (int i = 1; i <= n; ++i) { int x, y; cin >> x >> y; if (x > 0) ++sl; } if (sl == n || sl == 0 || sl == n - 1 || sl == 1) { cout << Yes ; return 0; } cout << No ; } |
#include <bits/stdc++.h> using namespace std; int main(void) { long long int n, x; cin >> n; vector<vector<long long int> > a(n); for (long long int i = 0; i < n; i++) { cin >> x; for (long long int j = 0; j < x; j++) { long long int tp; cin >> tp; a[i].push_back(tp); } } long long int a1 = 0, b = 0; vector<long long int> q; for (long long int i = 0; i < n; i++) { long long int f = a[i].size(); if (f % 2 != 0) { for (long long int j = 0; j < (f - 1) / 2; j++) { a1 += a[i][j]; } for (long long int j = (f - 1) / 2 + 1; j < f; j++) { b += a[i][j]; } q.push_back(a[i][(f - 1) / 2]); } else { for (long long int j = 0; j < f / 2; j++) { a1 += a[i][j]; } for (long long int j = f / 2; j < f; j++) { b += a[i][j]; } } } sort(q.begin(), q.end(), greater<long long int>()); for (long long int k = 0; k < q.size(); k++) { if (k % 2 == 0) a1 += q[k]; else b += q[k]; } cout << a1 << << b; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFSBP_1_V
`define SKY130_FD_SC_HD__DFSBP_1_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog wrapper for dfsbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dfsbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dfsbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dfsbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFSBP_1_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:04:06 03/25/2011
// Design Name:
// Module Name: debounce
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// Debounce Pushbutton: Filters out mechanical switch bounce for around 40Ms
module debounce(pb_debounced, pb, clk);
//push_button_debounced, push_button, clock
output pb_debounced; // signal of push button after debounced
input pb; // signal from push button of the FPGA board
input clk; // 100hz clock
reg [3:0] shift_reg; // use shift_reg to filter push button bounce
//when positive edge clock, shift the signal of pb to shift_reg[0]
always @(posedge clk) begin
shift_reg[3:1] <= shift_reg[2:0];
shift_reg[0] <= pb;
end
//if pb remain 0 at 4 positive edge clock, then pb_debounced = 0
assign pb_debounced = ((shift_reg == 4'b0000) ? 1'b0 : 1'b1);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRDLSTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__SRDLSTP_FUNCTIONAL_PP_V
/**
* srdlstp: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_psa_pp_pkg_s/sky130_fd_sc_lp__udp_dlatch_psa_pp_pkg_s.v"
`celldefine
module sky130_fd_sc_lp__srdlstp (
Q ,
SET_B ,
D ,
GATE ,
SLEEP_B,
KAPWR ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input SET_B ;
input D ;
input GATE ;
input SLEEP_B;
input KAPWR ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_lp__udp_dlatch$PSa_pp$PKG$s `UNIT_DELAY dlatch0 (buf_Q , D, GATE, SET_B, SLEEP_B, KAPWR, VGND, VPWR);
bufif1 bufif10 (Q , buf_Q, VPWR );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRDLSTP_FUNCTIONAL_PP_V |
/*
* Copyright (c) 2000 Peter monta ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// Reworked by SDW to be self checking
module main;
reg [7:0] x;
reg [7:0] y;
reg [2:0] i; // Was a wire..
reg error;
initial begin
#5;
x[i] <= #1 0;
y[i] = 0;
end
initial
begin
error = 0;
#1;
i = 1;
#7;
if(x[i] !== 1'b0)
begin
$display("FAILED - x[1] != 0");
error = 1;
end
if(y[i] !== 1'b0)
begin
$display("FAILED - y[1] != 0");
error = 1;
end
if(error === 0)
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e9 + 5; const long long N = 205; void solve(); int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; cout << fixed << setprecision(10); long long _ = 1; while (_--) solve(); return 0; } void solve() { string s; cin >> s; long long n = s.size(); long long ans = LLONG_MAX; for (long long loop = 0; loop < 26; loop++) { char ch = a + loop; long long cnt = 0, temp = 0; for (long long i = 0; i < n; i++) { cnt++; if (ch == s[i]) { temp = max(temp, cnt); cnt = 0; } } if (cnt) cnt++; temp = max(temp, cnt); ans = min(temp, ans); } cout << ans << n ; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21BAI_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__O21BAI_FUNCTIONAL_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__o21bai (
Y ,
A1 ,
A2 ,
B1_N
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Local signals
wire b ;
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
not not0 (b , B1_N );
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, b, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21BAI_FUNCTIONAL_V |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Sun Apr 09 08:38:15 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_zed_vga_0_0 -prefix
// system_zed_vga_0_0_ system_zed_vga_0_0_sim_netlist.v
// Design : system_zed_vga_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_zed_vga_0_0,zed_vga,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "zed_vga,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_zed_vga_0_0
(rgb565,
vga_r,
vga_g,
vga_b);
input [15:0]rgb565;
output [3:0]vga_r;
output [3:0]vga_g;
output [3:0]vga_b;
wire [15:0]rgb565;
assign vga_b[3:0] = rgb565[4:1];
assign vga_g[3:0] = rgb565[10:7];
assign vga_r[3:0] = rgb565[15:12];
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
`define ADDER_WIDTH 021
`define DUMMY_WIDTH 128
`define 2_LEVEL_ADDER
module adder_tree_top (
clk,
isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1,
sum,
);
input clk;
input [`ADDER_WIDTH+0-1:0] isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1;
output [`ADDER_WIDTH :0] sum;
reg [`ADDER_WIDTH :0] sum;
wire [`ADDER_WIDTH+3-1:0] sum0;
wire [`ADDER_WIDTH+2-1:0] sum0_0, sum0_1;
wire [`ADDER_WIDTH+1-1:0] sum0_0_0, sum0_0_1, sum0_1_0, sum0_1_1;
reg [`ADDER_WIDTH+0-1:0] sum0_0_0_0, sum0_0_0_1, sum0_0_1_0, sum0_0_1_1, sum0_1_0_0, sum0_1_0_1, sum0_1_1_0, sum0_1_1_1;
adder_tree_branch L1_0(sum0_0, sum0_1, sum0 );
defparam L1_0.EXTRA_BITS = 2;
adder_tree_branch L2_0(sum0_0_0, sum0_0_1, sum0_0 );
adder_tree_branch L2_1(sum0_1_0, sum0_1_1, sum0_1 );
defparam L2_0.EXTRA_BITS = 1;
defparam L2_1.EXTRA_BITS = 1;
adder_tree_branch L3_0(sum0_0_0_0, sum0_0_0_1, sum0_0_0);
adder_tree_branch L3_1(sum0_0_1_0, sum0_0_1_1, sum0_0_1);
adder_tree_branch L3_2(sum0_1_0_0, sum0_1_0_1, sum0_1_0);
adder_tree_branch L3_3(sum0_1_1_0, sum0_1_1_1, sum0_1_1);
defparam L3_0.EXTRA_BITS = 0;
defparam L3_1.EXTRA_BITS = 0;
defparam L3_2.EXTRA_BITS = 0;
defparam L3_3.EXTRA_BITS = 0;
always @(posedge clk) begin
sum0_0_0_0 <= isum0_0_0_0;
sum0_0_0_1 <= isum0_0_0_1;
sum0_0_1_0 <= isum0_0_1_0;
sum0_0_1_1 <= isum0_0_1_1;
sum0_1_0_0 <= isum0_1_0_0;
sum0_1_0_1 <= isum0_1_0_1;
sum0_1_1_0 <= isum0_1_1_0;
sum0_1_1_1 <= isum0_1_1_1;
`ifdef 3_LEVEL_ADDER
sum <= sum0;
`endif
`ifdef 2_LEVEL_ADDER
sum <= sum0_0;
`endif
end
endmodule
module adder_tree_branch(a,b,sum);
parameter EXTRA_BITS = 0;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] a;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] b;
output [`ADDER_WIDTH+EXTRA_BITS:0] sum;
assign sum = a + b;
endmodule |
#include <bits/stdc++.h> using namespace std; long long Seg[3][1 << 21 + 2], X, Cnt = 1; pair<long long, int> P[1000001]; int l_q, r_q, Len; long long RSQ(int l, int r, int root) { if (l > r_q || l_q > r || l > r) return 0; if (l >= l_q && r <= r_q) return Seg[Len][root]; int mid = (r + l) / 2; long long C1 = RSQ(l, mid, root * 2); long long C2 = RSQ(mid + 1, r, root * 2 + 1); return C1 + C2; } void Update(int l, int r, int root) { if (l > r_q || l_q > r || l > r) return; if (l >= l_q && r <= r_q) { Seg[Len][root] += X; return; } int mid = (r + l) / 2; Update(l, mid, root * 2); Update(mid + 1, r, root * 2 + 1); Seg[Len][root] = Seg[Len][root * 2] + Seg[Len][root * 2 + 1]; } int main() { int n; cin >> n; for (int i = 0; i < n; i++) cin >> P[i].first, P[i].second = i; sort(P, P + n); for (int i = 0; i < n; i++) { P[P[i].second].first = Cnt++; } reverse(P, P + n); for (int i = 0; i < n; i++) { for (int L = 0; L < 3; L++) { l_q = 1; r_q = P[i].first - 1; Len = L - 1; long long val; if (L == 0) val = 1; else val = RSQ(1, n, 1); l_q = r_q = P[i].first; Len = L; X = val; Update(1, n, 1); } } cout << Seg[2][1] << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 5e5 + 5; struct edg { int u, v, l, r; edg(int u = 0, int v = 0, int l = 0, int r = 0) : u(u), v(v), l(l), r(r) {} bool operator<(const edg &n1) const { return l > n1.l; } }; priority_queue<edg> q; vector<edg> adj[maxn][2]; int n, m; int dp[maxn][2]; inline void add(int u, int v, int l, int r) { int op = l % 2; if (dp[u][op] >= l) { if (v == n) { cout << l + 1 << endl; exit(0); } if (r + 1 > dp[v][op ^ 1]) { dp[v][op ^ 1] = r + 1; for (int i = 0; i < adj[v][op ^ 1].size(); i++) { edg t = adj[v][op ^ 1][i]; if (l + 1 <= t.r) q.push(edg(v, t.v, l + 1, t.r)); } adj[v][op ^ 1].clear(); } } else { adj[u][op].push_back(edg(u, v, l, r)); } } int main() { cin >> n >> m; memset(dp, 0xf3, sizeof(dp)); dp[1][0] = 0; for (int i = 1; i <= m; i++) { int u, v, l, r; scanf( %d%d%d%d , &u, &v, &l, &r); if ((r - l + 1) % 2 == 0) { q.push(edg(u, v, l, r - 1)); q.push(edg(v, u, l, r - 1)); if (l + 1 <= r - 2) { q.push(edg(u, v, l + 1, r - 2)); q.push(edg(v, u, l + 1, r - 2)); } } else { if (l <= r - 2) { q.push(edg(u, v, l, r - 2)); q.push(edg(v, u, l, r - 2)); } q.push(edg(u, v, l + 1, r - 1)); q.push(edg(v, u, l + 1, r - 1)); } } if (n == 1) { cout << 0 << endl; return 0; } while (!q.empty()) { edg t = q.top(); q.pop(); add(t.u, t.v, t.l, t.r); } cout << -1 << endl; return 0; } |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ps/1ps
module ad_mul (
// data_p = data_a * data_b;
clk,
data_a,
data_b,
data_p,
// delay interface
ddata_in,
ddata_out);
// delayed data bus width
parameter DELAY_DATA_WIDTH = 16;
// data_p = data_a * data_b;
input clk;
input [16:0] data_a;
input [16:0] data_b;
output [33:0] data_p;
// delay interface
input [(DELAY_DATA_WIDTH-1):0] ddata_in;
output [(DELAY_DATA_WIDTH-1):0] ddata_out;
// internal registers
reg [(DELAY_DATA_WIDTH-1):0] p1_ddata = 'd0;
reg [(DELAY_DATA_WIDTH-1):0] p2_ddata = 'd0;
reg [(DELAY_DATA_WIDTH-1):0] ddata_out = 'd0;
// a/b reg, m-reg, p-reg delay match
always @(posedge clk) begin
p1_ddata <= ddata_in;
p2_ddata <= p1_ddata;
ddata_out <= p2_ddata;
end
MULT_MACRO #(
.LATENCY (3),
.WIDTH_A (17),
.WIDTH_B (17))
i_mult_macro (
.CE (1'b1),
.RST (1'b0),
.CLK (clk),
.A (data_a),
.B (data_b),
.P (data_p));
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e9; const long long mod = 1e9 + 7; const long long N = 1e5 + 5; const long long Sz = 1e6 + 5; string to_string(const string& s) { return + s + ; } void DBG() { cerr << ] << endl; } template <class H, class... T> void DBG(H h, T... t) { cerr << to_string(h); if (sizeof...(t)) cerr << , ; DBG(t...); } void setIO() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); if (fopen( .inp , r )) { freopen( .inp , r , stdin); freopen( .out , w , stdout); } } long long n, a[200]; void test_case() { cin >> n; long long result = 0, pre = 0; for (long long i = (1); i <= (n); ++i) { cin >> a[i]; if (a[i] <= i + result) { ++pre; continue; } result += a[i] - pre - 1; pre = a[i]; } cout << result << n ; } signed main() { setIO(); long long TC = 1; cin >> TC; while (TC--) { test_case(); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main(void) { int n; cin >> n; set<int> a, b; vector<pair<int, int> > ans(n); for (int i = 0; i < n; ++i) { cin >> ans[i].first >> ans[i].second; --ans[i].first; --ans[i].second; if (ans[i].first == -1) a.insert(i); if (ans[i].second == -1) b.insert(i); } while (a.size() > 1) { int node = *a.begin(); a.erase(a.begin()); int last = node; while (ans[last].second != -1) last = ans[last].second; auto nxt = b.begin(); if (*nxt == last) ++nxt; ans[*nxt].second = node; ans[node].first = *nxt; b.erase(nxt); } for (int i = 0; i < n; ++i) cout << ans[i].first + 1 << << ans[i].second + 1 << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long int b1, b2, h1, h2, n, h, i, j, k, a, b; cin >> n >> h >> a >> b >> k; if (a > b) { swap(a, b); } while (k--) { long long int ans = 0; cin >> b1 >> h1 >> b2 >> h2; if (b1 == b2) { ans += abs(h1 - h2); } else if (h1 >= b && h2 >= b) { ans += (h1 - b); ans += abs(b1 - b2); ans += (h2 - b); } else if (h1 <= a && h2 <= a) { ans += (a - h1); ans += abs(b1 - b2); ans += (a - h2); } else { ans += abs(b1 - b2); ans += abs(h1 - h2); } cout << ans << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 2e3 + 15; const int mod = 998244353; char s[N]; int len; int depth[N]; vector<int> adj[N]; int dp[N][2]; int add(int x, int y) { return ((x + y) % mod + mod) % mod; } int mul(int x, int y) { return (long long)x * y % mod; } int mypow(int x, int c) { int ret = 1; while (c > 0) { if (c & 1) { ret = mul(ret, x); } c /= 2; x = mul(x, x); } return ret; } bool vis[N]; void dfs(int node, int par) { vis[node] = true; for (int ch : adj[node]) { if (ch != par && !vis[ch]) { depth[ch] = depth[node] + 1; dfs(ch, node); } } } int solveDp(int node, int bit) { int &ret = dp[node][bit]; if (ret != -1) { return ret; } ret = 0; bool isLeaf = true; int cc = 0; for (int ch : adj[node]) { if (depth[ch] > depth[node]) { isLeaf = false; } else { continue; } ++cc; int diff = abs(ch - node); if (diff >= len) { int ind = min(ch, node); if (s[ind] == ? ) { ret = add(ret, solveDp(ch, 0)); ret = add(ret, solveDp(ch, 1)); } else { int u = (s[ind] - 0 ) ^ bit; ret = solveDp(ch, u); } } else { ret = solveDp(ch, bit); } } if (isLeaf) { ret = 1; } return ret; } void solve() { scanf( %s , s + 1); len = strlen(s + 1); int ret = 0; for (int st = 2; st <= len; ++st) { for (int i = 1; i <= len * 2; ++i) adj[i].clear(); memset(dp, -1, sizeof(dp)); memset(depth, 0, sizeof(depth)); memset(vis, 0, sizeof(vis)); for (int i = 1; i <= len; ++i) { int j = len - i + 1; if (i != j) adj[i].push_back(j); } int g = len - st + 1; for (int j = st; j <= len; ++j) { int ind = j - st + 1; int nind = g - ind + 1 + (st - 1); if (j + len != nind + len) adj[j + len].push_back(nind + len); } for (int i = 1; i < st; ++i) { dp[i + len][1] = 0; } dp[1][0] = 0; dp[len][0] = 0; dp[st + len][0] = 0; dp[len * 2][0] = 0; for (int i = 1; i <= len; ++i) { adj[i].push_back(i + len); adj[i + len].push_back(i); } int tmp = 1; for (int i = 1; i <= len * 2; ++i) { assert(adj[i].size() <= 2); if (adj[i].size() == 1 && !vis[i]) { dfs(i, 0); } } for (int i = 1; i <= len * 2; ++i) { assert(vis[i]); if (depth[i] == 0) { assert(adj[i].size() == 1); tmp = mul(tmp, add(solveDp(i, 0), solveDp(i, 1))); } } ret = add(ret, tmp); } printf( %d n , ret); } int main() { solve(); return 0; } |
// -- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
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// -- Applications"). Customer assumes the sole risk and
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// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized OR with carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module mig_7series_v4_0_ddr_carry_latch_or #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire I,
output wire O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign O = CIN | I;
end else begin : USE_FPGA
OR2L or2l_inst1
(
.O(O),
.DI(CIN),
.SRI(I)
);
end
endgenerate
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Wed May 31 20:16:38 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/examples/dma_example/dma_example.srcs/sources_1/bd/system/ip/system_auto_us_1/system_auto_us_1_stub.v
// Design : system_auto_us_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_dwidth_converter_v2_1_11_top,Vivado 2016.4" *)
module system_auto_us_1(s_axi_aclk, s_axi_aresetn, s_axi_araddr,
s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache, s_axi_arprot,
s_axi_arregion, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_araddr, m_axi_arlen, m_axi_arsize,
m_axi_arburst, m_axi_arlock, m_axi_arcache, m_axi_arprot, m_axi_arregion, m_axi_arqos,
m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rlast, m_axi_rvalid,
m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arregion[3:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_araddr[31:0],m_axi_arlen[7:0],m_axi_arsize[2:0],m_axi_arburst[1:0],m_axi_arlock[0:0],m_axi_arcache[3:0],m_axi_arprot[2:0],m_axi_arregion[3:0],m_axi_arqos[3:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[63:0],m_axi_rresp[1:0],m_axi_rlast,m_axi_rvalid,m_axi_rready" */;
input s_axi_aclk;
input s_axi_aresetn;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arregion;
output [3:0]m_axi_arqos;
output m_axi_arvalid;
input m_axi_arready;
input [63:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
#include <bits/stdc++.h> using namespace std; int ntest = 0, test = 0; inline void init(); inline void run(); inline void stop() { ntest = test - 1; } int main() { init(); while (++test <= ntest) { run(); } return 0; } const int INF = (int)1E9 + 5; const double EPS = 1E-11; const long long MOD = (long long)1E9 + 7; const int dx[] = {-1, 0, 0, 1}; const int dy[] = {0, -1, 1, 0}; inline void init() { ntest = 1; } long long mu(long long a, long long n) { long long rs = 1; for (; n; n >>= 1) { if (n & 1) rs = (rs * a) % MOD; a = (a * a) % MOD; } return rs; } vector<int> a; inline void run() { int n, k; cin >> n >> k; a.resize(n); for (int i = 0; i < (n); i++) cin >> a[i]; if (k == 0) { for (int i = 0; i < (n); i++) cout << a[i] << ; return; } for (int i = 0; i < (n); i++) { long long total = a[i]; long long cur = 1; for (int j = (1); j <= (i); j++) { cur = (cur * (k + j - 1)) % MOD; cur = (cur * mu(j, MOD - 2)) % MOD; total = (total + (cur * a[i - j]) % MOD) % MOD; } cout << total << ; } } |
#include <bits/stdc++.h> using namespace std; vector<int> P; int m, n; void bs() { int lo = 1, hi = m, ans = 0; int cnt = 0; while (lo <= hi) { int mid = (lo + hi) / 2; cout << mid << endl; int t; cin >> t; if (P[cnt % n] == 0) { if (t == 0) { exit(0); } if (t == -1) { lo = mid + 1; } if (t == 1) { hi = mid - 1; } } if (P[cnt % n] == 1) { if (t == 0) { exit(0); } if (t == 1) { lo = mid + 1; } if (t == -1) { hi = mid - 1; } } cnt++; } } int main() { cin >> m >> n; P = vector<int>(n); for (int i = 0; i < n; i++) { cout << 1 << endl; int t; cin >> t; if (t == 0 || t == -2) exit(0); if (t == 1) P[i] = 1; else P[i] = 0; } bs(); return 0; } |
#include <bits/stdc++.h> using namespace std; vector<int> adj[100005], dir[100005], vec; int vis1[100005], vis2[100005], vis3[100005], fl = 0; void dfs1(int u) { vis1[u] = 1; vec.push_back(u); for (int i = (int)0; i <= (int)adj[u].size() - 1; i++) { if (!vis1[adj[u][i]]) dfs1(adj[u][i]); } } void dfs2(int u) { vis2[u] = 1; vis3[u] = 1; for (int i = (int)0; i <= (int)dir[u].size() - 1; i++) { if (!vis2[dir[u][i]]) dfs2(dir[u][i]); if (vis3[dir[u][i]]) fl = 1; } vis3[u] = 0; } int fun() { int ret = 0; for (int j = (int)0; j <= (int)vec.size() - 1; j++) { if (!vis2[vec[j]]) { fl = 0; dfs2(vec[j]); ret += fl; } } return (ret == 0); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, m; cin >> n >> m; for (int i = (int)1; i <= (int)m; i++) { int u, v; cin >> u >> v; adj[u].push_back(v); adj[v].push_back(u); dir[u].push_back(v); } int ans = 0; for (int i = (int)1; i <= (int)n; i++) { if (!vis1[i]) { vec.clear(); dfs1(i); ans += vec.size() - fun(); } } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { string s; int n; cin >> n >> s; vector<int> vec; for (int i = 0; i < s.length(); ++i) { if (s[i] == B ) { int res = 0; while (i < s.length() && s[i] == B ) { ++res; ++i; } vec.push_back(res); continue; } } cout << vec.size() << n ; for (int i = 0; i < (int)vec.size(); ++i) { cout << vec[i] << ; } cout << n ; } |
#include <bits/stdc++.h> using namespace std; const long long INF = 1e17; struct edge { int u, v; edge() {} edge(int _u, int _v) : u(_u), v(_v) {} }; struct node { vector<edge> edges; }; struct tree { vector<node> nodes; int root, n; tree(int _n, int _r = 0) : n(_n), root(_r) { nodes.resize(n); } void add_edge(int u, int v) { edge e1(u, v); edge e2(v, u); nodes[u].edges.push_back(e1); nodes[v].edges.push_back(e2); } vector<pair<int, int>> findDiametersAndCenters() { vector<pair<int, int>> ans; vector<bool> vis1(n, 0), vis2(n, 0); vector<int> parent(n, 0); for (int i = 0; i < n; i++) { if (vis1[i]) { continue; } int diameter, d1, d2; findDiameter(i, vis1, vis2, parent, diameter, d1, d2); int c = findCenter(d2, diameter, parent); ans.push_back({diameter, c}); } return move(ans); } pair<int, int> bfs(int u, vector<bool> &visited, vector<int> &parent) { queue<pair<int, int>> Q; visited[u] = true; int dist = 0; Q.push({u, 0}); while (!Q.empty()) { u = Q.front().first; dist = Q.front().second; Q.pop(); for (auto &e : nodes[u].edges) { if (visited[e.v]) { continue; } visited[e.v] = true; Q.push({e.v, dist + 1}); parent[e.v] = u; } } return {u, dist}; } void findDiameter(int u, vector<bool> &vis1, vector<bool> &vis2, vector<int> &parent, int &diameter, int &d1, int &d2) { d1 = bfs(u, vis1, parent).first; auto p = bfs(d1, vis2, parent); d2 = p.first; diameter = p.second; } int findCenter(int u, int diameter, vector<int> &parent) { diameter >>= 1; while (diameter--) { u = parent[u]; } return u; } }; int main() { ios::sync_with_stdio(0); cin.tie(0), cout.tie(0); int n, m; cin >> n >> m; tree t(n); for (int i = 0; i < m; i++) { int u, v; cin >> u >> v; u--; v--; t.add_edge(u, v); } vector<pair<int, int>> DnC = t.findDiametersAndCenters(); sort(DnC.rbegin(), DnC.rend()); int res = DnC[0].first; if (DnC.size() >= 2) { res = max(res, (DnC[0].first + 1) / 2 + (DnC[1].first + 1) / 2 + 1); } if (DnC.size() >= 3) { res = max(res, (DnC[1].first + 1) / 2 + (DnC[2].first + 1) / 2 + 2); } cout << res << n ; for (int i = 1; i < DnC.size(); i++) { cout << DnC[i].second + 1 << << DnC[0].second + 1 << n ; } } |
#include <bits/stdc++.h> using namespace std; const int N = 60 + 5; char a[N][N]; int l[N][N]; int r[N][N]; int main() { ios::sync_with_stdio(0); cin.tie(0); int t; cin >> t; while (t--) { int m, n; cin >> n >> m; for (int i = 1; i <= n; i++) cin >> (a[i] + 1); int f1 = 0, f2 = 0; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { if (a[i][j] == A ) f1 = 1; if (a[i][j] == P ) f2 = 1; } } if (!f2) { printf( 0 n ); continue; } if (!f1) { printf( MORTAL n ); continue; } int visl = 0, visb = 0, visj = 0; if (a[1][1] == A || a[1][m] == A || a[n][1] == A || a[n][m] == A ) visj = 1; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { if (i == 1 || j == 1 || i == n || j == m) { if (a[i][j] == A ) visb = 1; } if (a[i][j] == A ) l[i][j] = l[i][j - 1] + 1; } if (l[i][m] == m) visl = 1; } for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { if (a[i][j] == A ) r[i][j] = r[i - 1][j] + 1; if (r[n][j] == n) visl = 1; } } int visjl = 0; if (r[n][m] == n || l[n][m] == m || r[n][1] == n || l[1][m] == m) visjl = 1; if (visjl) printf( 1 n ); else if (visj) printf( 2 n ); else if (visl && visb) printf( 2 n ); else if (visb) printf( 3 n ); else printf( 4 n ); memset(l, 0, sizeof l); memset(r, 0, sizeof r); } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFRTN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__SDFRTN_BEHAVIORAL_PP_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ms__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_N_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (intclk , CLK_N_delayed );
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_ms__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, intclk, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFRTN_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; int num1 = 0; string s1, s2; int counter = 0; int ques = 0; int main() { cin >> s1 >> s2; int num2 = 0; for (int i = 0; i < s1.length(); i++) if (s1[i] == + ) num1++; else num1--; for (int i = 0; i < s2.length(); i++) if (s2[i] == + ) num2++; else if (s2[i] == - ) num2--; else ques++; float num = 0; int limit = (1 << ques); for (int i = 0; i < limit; i++) { int sum = num2; for (int j = 0; j < ques; j++) { if ((1 << j) & i) sum++; else sum--; } if (sum == num1) counter++; } if (ques != 0) { num = (float)counter / (1 << ques); } else if (num2 == num1) num = 1; printf( %0.12f n , num); } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLRBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__DLRBP_FUNCTIONAL_PP_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_lp__udp_dlatch_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dlrbp (
Q ,
Q_N ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_lp__udp_dlatch$PR_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLRBP_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR2_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__NOR2_PP_BLACKBOX_V
/**
* nor2: 2-input NOR.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__nor2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR2_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int solve(string s, int x, int y) { int t = 0; for (auto i : s) { if (i - 0 == x) { t++; swap(x, y); } } if (x != y && t % 2 == 1) --t; return t; } int main() { cin.tie(0); cout.tie(0); ios_base::sync_with_stdio(0); int t; cin >> t; while (t--) { string s; cin >> s; int ans = 0; for (int i = 0; i <= 9; i++) { for (int j = 0; j <= 9; j++) { ans = max(ans, solve(s, i, j)); } } cout << (int)(s.size()) - ans << endl; } return 0; } |
//Legal Notice: (C)2019 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_dut_pio_3 (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 7: 0] out_port;
output [ 31: 0] readdata;
input [ 2: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 7: 0] data_out;
wire [ 7: 0] out_port;
wire [ 7: 0] read_mux_out;
wire [ 31: 0] readdata;
wire wr_strobe;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_out;
assign wr_strobe = chipselect && ~write_n;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (clk_en)
if (wr_strobe)
data_out <= (address == 5)? data_out & ~writedata[7 : 0]: (address == 4)? data_out | writedata[7 : 0]: (address == 0)? writedata[7 : 0]: data_out;
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long n; cin >> n; vector<long long> a(n); long long i; for (i = 0; i < n; i++) cin >> a[i]; map<long long, long long> m; long long add = 0; for (i = 0; i < n; i++) { auto it = m.find(a[i]); if (it != m.end()) { pair<long long, long long> p = *it; long long val = p.second; m.erase(a[i]); m.insert(make_pair(a[i], val + 1)); } else { m.insert(make_pair(a[i], 1)); } auto itneg = m.find(a[i] - 1); auto itpos = m.find(a[i] + 1); if (itneg != m.end()) { pair<long long, long long> p = *itneg; add -= p.second; } if (itpos != m.end()) { pair<long long, long long> p = *itpos; add += p.second; } } long long ans = add; long long ch = 0; for (i = 0; i < n; i++) { ans += a[i] * (i * 2 - (n - 1)); while (ans >= 1000000000000000000) { ch++; ans -= 1000000000000000000; } while (ans < 0) { ch--; ans += 1000000000000000000; } } if (ch >= 0) { if (ch == 0) cout << ans << endl; else { cout << ch; vector<int> nums(18); for (i = 17; i >= 0; i--) { nums[i] = ans % 10; ans /= 10; } for (i = 0; i < 18; i++) { cout << nums[i]; } cout << endl; } } else { ch++; ans -= 1000000000000000000; if (ch == 0) { cout << ans << endl; } else { ans = abs(ans); cout << - ; if (ch < 0) cout << abs(ch); vector<int> nums(18); for (i = 17; i >= 0; i--) { nums[i] = ans % 10; ans /= 10; } for (i = 0; i < 18; i++) { cout << nums[i]; } cout << endl; } } } |
`timescale 1ns / 1ps
`define STATE_IDLE 0
`define STATE_TX 1
`define STATE_RX 2
module spi_cmd(
// controls
input clk,
input reset,
input trigger,
output reg busy,
input [8:0] data_in_count,
input data_out_count,
input [260 * 8 - 1 : 0] data_in, // max len is: 256B data + 1B cmd + 3B addr
output reg [7:0] data_out,
input quad_mode,
// SPI memory
inout [3:0] DQio,
output reg S
);
wire [2:0] n_bits_parallel = quad_mode ? 4 : 1;
reg [11:0] bit_cntr;
reg [3:0] DQ = 4'b1111;
reg oe;
reg [1:0] state;
assign DQio[0] = oe ? DQ[0] : 1'bZ;
assign DQio[1] = oe ? DQ[1] : 1'bZ;
assign DQio[2] = oe ? DQ[2] : 1'bZ;
assign DQio[3] = quad_mode ? (oe ? DQ[3] : 1'bZ) : 1'b1;
// has to be held 1 as 'hold'
// during single IO operation, but in quad mode behaves as other IOs
always @(posedge clk) begin
if (reset) begin
state <= `STATE_IDLE;
oe <= 0;
S <= 1;
busy <= 1;
end else begin
case (state)
`STATE_IDLE: begin
if (trigger && !busy) begin
state <= `STATE_TX;
busy <= 1;
bit_cntr <= data_in_count * 8 - 1;
end else begin
S <= 1;
busy <= 0;
end
end
`STATE_TX: begin
S <= 0;
oe <= 1;
if(quad_mode) begin
DQ[0] <= data_in[bit_cntr - 3];
DQ[1] <= data_in[bit_cntr - 2];
DQ[2] <= data_in[bit_cntr - 1];
DQ[3] <= data_in[bit_cntr];
end else
DQ[0] <= data_in[bit_cntr];
if (bit_cntr > n_bits_parallel - 1) begin
bit_cntr <= bit_cntr - n_bits_parallel;
end else begin
if (data_out_count > 0) begin
state <= `STATE_RX;
bit_cntr <= 7 + 1; // +1 because read happens on falling edge
end
else begin
state <= `STATE_IDLE;
end
end
end
`STATE_RX: begin
oe <= 0;
if (bit_cntr > n_bits_parallel - 1) begin
bit_cntr <= bit_cntr - n_bits_parallel;
end else begin
S <= 1;
state <= `STATE_IDLE;
end
end
default: begin
state <= `STATE_IDLE;
end
endcase
end
end
always @(negedge clk) begin
if (reset) begin
data_out <= 0;
end else begin
if (state == `STATE_RX) begin
if (quad_mode)
data_out <= {data_out[3:0], DQio[3], DQio[2], DQio[1], DQio[0]};
else
data_out <= {data_out[6:0], DQio[1]};
end
end
end
endmodule
|
#include <bits/stdc++.h> #pragma GCC diagnostic ignored -Wunused-result #pragma GCC diagnostic ignored -Wunused-function using namespace std; namespace { namespace shik { template <class T> void _R(T &x) { cin >> x; } void _R(int &x) { scanf( %d , &x); } void _R(int64_t &x) { scanf( % SCNd64, &x); } void _R(double &x) { scanf( %lf , &x); } void _R(char &x) { scanf( %c , &x); } void _R(char *x) { scanf( %s , x); } void R() {} template <class T, class... U> void R(T &head, U &...tail) { _R(head); R(tail...); } template <class T> void _W(const T &x) { cout << x; } void _W(const int &x) { printf( %d , x); } void _W(const int64_t &x) { printf( % PRId64, x); } void _W(const double &x) { printf( %.16f , x); } void _W(const char &x) { putchar(x); } void _W(const char *x) { printf( %s , x); } template <class T> void _W(const vector<T> &x) { for (auto i = x.begin(); i != x.end(); _W(*i++)) if (i != x.cbegin()) putchar( ); } void W() {} template <class T, class... U> void W(const T &head, const U &...tail) { _W(head); putchar(sizeof...(tail) ? : n ); W(tail...); } template <class T, class F = less<T>> void sort_uniq(vector<T> &v, F f = F()) { sort(begin(v), end(v), f); v.resize(unique(begin(v), end(v)) - begin(v)); } template <class T> inline T bit(T x, int i) { return (x >> i) & 1; } template <class T> inline bool chkmax(T &a, const T &b) { return b > a ? a = b, true : false; } template <class T> inline bool chkmin(T &a, const T &b) { return b < a ? a = b, true : false; } template <class T> using MaxHeap = priority_queue<T>; template <class T> using MinHeap = priority_queue<T, vector<T>, greater<T>>; const int N = 1e5 + 10; int n, k; vector<int> e[N]; void make_tree(int p) { for (int i : e[p]) { e[i].erase(find(begin(e[i]), end(e[i]), p)); make_tree(i); } } pair<int, int> go(int p) { int s = 0, r = 0, a1 = 0, a2 = 0; for (int i : e[p]) { auto t = go(i); s += t.first; int x = t.second; if (x >= a1) { a2 = a1; a1 = x; } else if (x >= a2) { a2 = x; } } if (a1 + a2 + 1 >= k) { s++; } else { r = a1 + 1; } return {s, r}; } int shik(int _k) { k = _k; return go(1).first; } int ans[N]; void solve(int l, int r, int al, int ar) { if (r - l <= 1) return; if (al == ar) { for (int i = (l); i <= int(r); i++) ans[i] = al; return; } int m = (l + r) / 2; int am = shik(m); ans[m] = am; solve(l, m, al, am); solve(m, r, am, ar); } void main() { R(n); for (int i = 0; i < int(n - 1); i++) { int a, b; R(a, b); e[a].push_back(b); e[b].push_back(a); } make_tree(1); ans[1] = n; solve(1, n + 1, n, 0); for (int i = (1); i <= int(n); i++) W(ans[i]); } } // namespace shik } // namespace int main() { shik::main(); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFRTN_BLACKBOX_V
`define SKY130_FD_SC_HD__DFRTN_BLACKBOX_V
/**
* dfrtn: Delay flop, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dfrtn (
Q ,
CLK_N ,
D ,
RESET_B
);
output Q ;
input CLK_N ;
input D ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFRTN_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; long long power(long long a, long long b) { long long res = 1ll; while (b > 0) { if (b % 2 != 0) res = (res * a) % 1000000007; a = (a * a) % 1000000007; b /= 2; } return res % 1000000007; } long long ncr(long long n, long long k) { if (k > n - k) k = n - k; long long pro = 1; for (long long i = 0; i < k; i++) { pro = (pro * (n - i)) % 1000000007; pro /= (i + 1); } return (pro) % 1000000007; } void swap(long long *a, long long *b) { long long temp = *a; *a = *b; *b = temp; } vector<long long> prime; void seive() { vector<bool> isprime(1000001, true); for (int i = 2; i * i <= 1000000; i++) { if (isprime[i]) { for (int j = i * i; j <= 1000000; j += i) { isprime[j] = false; } } } for (int i = 2; i <= 1000000; i++) { if (isprime[i]) prime.push_back(i); } } vector<long long> parent; long long find(long long p) { if (parent[p] == p) return parent[p]; return parent[p] = find(parent[p]); } void unun(long long a, long long b) { long long r1 = find(a); long long r2 = find(b); if (r1 != r2) parent[r2] = r1; } void solve() { long long n; cin >> n; set<long long> s; s.insert(0); s.insert(1); s.insert(n); for (int i = 1; i * i <= n; i++) { long long x = (n / i); long long y = (n / x); s.insert((n / x)); s.insert((n / y)); } cout << s.size() << n ; for (auto itr : s) cout << itr << ; cout << n ; } int main(void) { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t; t = 1; cin >> t; while (t--) { solve(); } return 0; } |
//-----------------------------------------------------------------------------
// Title : GT Common wrapper
// Project : 10GBASE-R
//-----------------------------------------------------------------------------
// File : ten_gig_eth_pcs_pma_ip_GT_Common_wrapper.v
//-----------------------------------------------------------------------------
// Description: This file contains the
// 10GBASE-R Transceiver GT Common block.
//-----------------------------------------------------------------------------
// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
module ten_gig_eth_pcs_pma_ip_GT_Common_wrapper # (
parameter WRAPPER_SIM_GTRESET_SPEEDUP = "false" ) //Does not affect hardware
(
input refclk,
input qplllockdetclk,
input qpllreset,
output qplllock,
output qpllrefclklost,
output qplloutclk,
output qplloutrefclk
);
//***************************** Parameter Declarations ************************
parameter QPLL_FBDIV_TOP = 66;
parameter QPLL_FBDIV_IN = (QPLL_FBDIV_TOP == 16) ? 10'b0000100000 :
(QPLL_FBDIV_TOP == 20) ? 10'b0000110000 :
(QPLL_FBDIV_TOP == 32) ? 10'b0001100000 :
(QPLL_FBDIV_TOP == 40) ? 10'b0010000000 :
(QPLL_FBDIV_TOP == 64) ? 10'b0011100000 :
(QPLL_FBDIV_TOP == 66) ? 10'b0101000000 :
(QPLL_FBDIV_TOP == 80) ? 10'b0100100000 :
(QPLL_FBDIV_TOP == 100) ? 10'b0101110000 : 10'b0000000000;
parameter QPLL_FBDIV_RATIO = (QPLL_FBDIV_TOP == 16) ? 1'b1 :
(QPLL_FBDIV_TOP == 20) ? 1'b1 :
(QPLL_FBDIV_TOP == 32) ? 1'b1 :
(QPLL_FBDIV_TOP == 40) ? 1'b1 :
(QPLL_FBDIV_TOP == 64) ? 1'b1 :
(QPLL_FBDIV_TOP == 66) ? 1'b0 :
(QPLL_FBDIV_TOP == 80) ? 1'b1 :
(QPLL_FBDIV_TOP == 100) ? 1'b1 : 1'b1;
//***************************** Wire Declarations *****************************
// ground and vcc signals
wire tied_to_ground_i;
wire [63:0] tied_to_ground_vec_i;
wire tied_to_vcc_i;
wire [63:0] tied_to_vcc_vec_i;
//********************************* Main Body of Code**************************
assign tied_to_ground_i = 1'b0;
assign tied_to_ground_vec_i = 64'h0000000000000000;
assign tied_to_vcc_i = 1'b1;
assign tied_to_vcc_vec_i = 64'hffffffffffffffff;
wire GT0_GTREFCLK0_COMMON_IN;
wire GT0_QPLLLOCKDETCLK_IN;
wire GT0_QPLLRESET_IN;
wire GT0_QPLLLOCK_OUT;
wire GT0_QPLLREFCLKLOST_OUT;
wire gt0_qplloutclk_i;
wire gt0_qplloutrefclk_i;
assign GT0_GTREFCLK0_COMMON_IN = refclk;
assign GT0_QPLLLOCKDETCLK_IN = qplllockdetclk;
assign GT0_QPLLRESET_IN = qpllreset;
assign qplllock = GT0_QPLLLOCK_OUT;
assign qpllrefclklost = GT0_QPLLREFCLKLOST_OUT;
assign qplloutclk = gt0_qplloutclk_i;
assign qplloutrefclk = gt0_qplloutrefclk_i;
//_________________________________________________________________________
//_________________________________________________________________________
//_________________________GTHE2_COMMON____________________________________
GTHE2_COMMON #
(
// Simulation attributes
.SIM_RESET_SPEEDUP (WRAPPER_SIM_GTRESET_SPEEDUP),
.SIM_QPLLREFCLK_SEL (3'b001),
.SIM_VERSION ("2.0"),
//----------------COMMON BLOCK Attributes---------------
.BIAS_CFG (64'h0000040000001000),
.COMMON_CFG (32'h00000000),
.QPLL_CFG (27'h0480181),
.QPLL_CLKOUT_CFG (4'b0000),
.QPLL_COARSE_FREQ_OVRD (6'b010000),
.QPLL_COARSE_FREQ_OVRD_EN (1'b0),
.QPLL_CP (10'b0000011111),
.QPLL_CP_MONITOR_EN (1'b0),
.QPLL_DMONITOR_SEL (1'b0),
.QPLL_FBDIV (QPLL_FBDIV_IN),
.QPLL_FBDIV_MONITOR_EN (1'b0),
.QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO),
.QPLL_INIT_CFG (24'h000006),
.QPLL_LOCK_CFG (16'h05E8),
.QPLL_LPF (4'b1111),
.QPLL_REFCLK_DIV (1),
.RSVD_ATTR0 (16'h0000),
.RSVD_ATTR1 (16'h0000),
.QPLL_RP_COMP (1'b0),
.QPLL_VTRL_RESET (2'b00),
.RCAL_CFG (2'b00)
)
gthe2_common_0_i
(
//----------- Common Block - Dynamic Reconfiguration Port (DRP) -----------
.DRPADDR (tied_to_ground_vec_i[7:0]),
.DRPCLK (tied_to_ground_i),
.DRPDI (tied_to_ground_vec_i[15:0]),
.DRPDO (),
.DRPEN (tied_to_ground_i),
.DRPRDY (),
.DRPWE (tied_to_ground_i),
//-------------------- Common Block - Ref Clock Ports ---------------------
.GTGREFCLK (tied_to_ground_i),
.GTNORTHREFCLK0 (tied_to_ground_i),
.GTNORTHREFCLK1 (tied_to_ground_i),
.GTREFCLK0 (GT0_GTREFCLK0_COMMON_IN),
.GTREFCLK1 (tied_to_ground_i),
.GTSOUTHREFCLK0 (tied_to_ground_i),
.GTSOUTHREFCLK1 (tied_to_ground_i),
//----------------------- Common Block - QPLL Ports ------------------------
.BGRCALOVRDENB (tied_to_vcc_i),
.PMARSVDOUT (),
.QPLLDMONITOR (),
.QPLLFBCLKLOST (),
.QPLLLOCK (GT0_QPLLLOCK_OUT),
.QPLLLOCKDETCLK (GT0_QPLLLOCKDETCLK_IN),
.QPLLLOCKEN (tied_to_vcc_i),
.QPLLOUTCLK (gt0_qplloutclk_i),
.QPLLOUTREFCLK (gt0_qplloutrefclk_i),
.QPLLOUTRESET (tied_to_ground_i),
.QPLLPD (tied_to_ground_i),
.QPLLREFCLKLOST (GT0_QPLLREFCLKLOST_OUT),
.QPLLREFCLKSEL (3'b001),
.QPLLRESET (GT0_QPLLRESET_IN),
.QPLLRSVD1 (16'b0000000000000000),
.QPLLRSVD2 (5'b11111),
.REFCLKOUTMONITOR (),
//--------------------------- Common Block Ports ---------------------------
.BGBYPASSB (tied_to_vcc_i),
.BGMONITORENB (tied_to_vcc_i),
.BGPDB (tied_to_vcc_i),
.BGRCALOVRD (5'b00000),
.PMARSVD (8'b00000000),
.RCALENB (tied_to_vcc_i)
);
endmodule |
Subsets and Splits