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#include <bits/stdc++.h> using namespace std; const int MAX = 35005; struct segtree { segtree *left, *right; int start, end, v, m; int lazy; segtree(int start, int end) : start(start), end(end), v(0), lazy(0) { if (start == end) { left = right = NULL; } else { m = (start + end) / 2; left = new segtree(start, m); right = new segtree(m + 1, end); } } void propagate() { if (lazy) { v += lazy; if (left != NULL) left->lazy += lazy; if (right != NULL) right->lazy += lazy; lazy = 0; } } void update(int a, int b, int val) { if (b < a) return; propagate(); if (a == start && b == end) { lazy += val; propagate(); } else { if (b <= m) left->update(a, b, val); else if (a > m) right->update(a, b, val); else left->update(a, m, val), right->update(m + 1, b, val); left->propagate(); right->propagate(); v = max(left->v, right->v); } } int query(int a, int b) { if (b < a) return 1; propagate(); if (a == start && b == end) return v; if (b <= m) return left->query(a, b); if (a > m) return right->query(a, b); return max(left->query(a, m), right->query(m + 1, b)); } }; int dp[MAX][51]; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n, k; cin >> n >> k; vector<int> v(n + 1); for (int i = 1; i <= n; i++) { cin >> v[i]; } set<int> diff; for (int i = 1; i <= n; i++) { diff.insert(v[i]); dp[i][1] = diff.size(); } for (int i = 2; i <= k; i++) { segtree cur(1, n); for (int j = 1; j <= n; j++) { cur.update(j, j, dp[j][i - 1]); } vector<int> last(n + 1, 1); for (int j = 1; j <= n; j++) { cur.update(last[v[j]], j - 1, 1); dp[j][i] = cur.query(1, j - 1); last[v[j]] = j; } } cout << dp[n][k] << n ; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV5SD3_1_V
`define SKY130_FD_SC_MS__CLKDLYINV5SD3_1_V
/**
* clkdlyinv5sd3: Clock Delay Inverter 5-stage 0.50um length inner
* stage gate.
*
* Verilog wrapper for clkdlyinv5sd3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__clkdlyinv5sd3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__clkdlyinv5sd3_1 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__clkdlyinv5sd3 base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__clkdlyinv5sd3_1 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__clkdlyinv5sd3 base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV5SD3_1_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, m, x, p, l, r, e, ans, set; l = r = e = ans = 0; cin >> n >> x; vector<long long int> a(n); set = 0; m = (n + 1) / 2; for (int i = 0; i < n; i++) { cin >> a[i]; if (a[i] < x) l++; if (a[i] > x) r++; if (a[i] == x) e++; } if (e == 0) ans++; else e--; set = 1; if (e >= abs(r - l)) { cout << ans << n ; return 0; } if (l < r) { l += e; e = 0; cout << ans + (r - 1) - l << endl; } else { r += e; e = 0; cout << ans + l - r << endl; } } |
/*
* 4-bit up - down counter
* Structural Description
*/
module D_flip_flop (output Q, input D, Clk);
reg Q;
initial Q = 1'b0;
always @ (posedge Clk) Q <= D;
endmodule
module T_flip_flop (output Q, input T, Clk);
wire DT;
assign DT = Q ^ T;
D_flip_flop DFF1 (Q, DT, Clk);
endmodule
module _1_bit_up_down_counter (output A, input I1, I2, Clk);
wire w1;
or (w1, I1, I2);
T_flip_flop TFF1 (A, w1, Clk);
endmodule
module _4_bit_up_down_counter_part (output A, and_out_1, and_out_2, input I1, I2, Clk);
wire A_not;
_1_bit_up_down_counter TTF1 (A, I1, I2, Clk);
not (A_not, A);
and (and_out_1, I2, A_not);
and (and_out_2, I1, A);
endmodule
module _4_bit_up_down_counter (output [3:0] A, input up, down, Clk);
wire up_not, w1;
wire [5:0] wr;
not (up_not, up);
and (w1, down, up_not);
_4_bit_up_down_counter_part TFF1 (A[0], wr[0], wr[1], up, w1, Clk),
TTF2 (A[1], wr[2], wr[3], wr[1], wr[0], Clk),
TTF3 (A[2], wr[4], wr[5], wr[3], wr[2], Clk);
_1_bit_up_down_counter TFF4 (A[3], wr[5], wr[4], Clk);
endmodule
|
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1.0); const int N = 200010; const bool QUERY_MAX = true; const double INF = 1e30; struct Line { long long a, b, val; double xLeft; bool is_query; Line() {} Line(long long _a, long long _b) { a = _a; b = _b; val = 0; xLeft = -INF; is_query = false; } long long value(long long x) { return a * x + b; } bool operator<(const Line l) const { if (l.is_query) { return QUERY_MAX ? (xLeft < l.val) : (l.val < xLeft); } return a < l.a; } bool areParallel(const Line l) const { return a == l.a; } double intersect(const Line l) const { if (!areParallel(l)) return (l.b - b) / (1.0 * (a - l.a)); return INF; } void printLine() const { printf( a = %lld t b = %lld n , a, b); } }; set<Line> hull; bool has_prev(set<Line>::iterator it) { return it != hull.begin(); } bool has_next(set<Line>::iterator it) { return (it != hull.end()) and (++it != hull.end()); } bool irrelevant(set<Line>::iterator it) { if (!has_prev(it) or !has_next(it)) { return false; } set<Line>::iterator prev = it, next = it; prev--; next++; return QUERY_MAX ? prev->intersect(*next) <= prev->intersect(*it) : next->intersect(*prev) <= next->intersect(*it); } set<Line>::iterator update_left_border(set<Line>::iterator it) { if ((QUERY_MAX and !has_prev(it)) or (!QUERY_MAX and !has_next(it))) return it; set<Line>::iterator it2 = it; double val = it->intersect(QUERY_MAX ? *--it2 : *++it2); Line l(*it); l.xLeft = val; hull.erase(it++); return hull.insert(it, l); } void addLine(long long a, long long b) { Line l(a, b); set<Line>::iterator it = hull.lower_bound(l); if (it != hull.end() and it->areParallel(l)) { if ((QUERY_MAX and it->b < b) or (!QUERY_MAX and it->b > b)) hull.erase(it++); else return; } it = hull.insert(it, l); if (irrelevant(it)) { hull.erase(it); return; } while (has_prev(it) and irrelevant(--it)) hull.erase(it++); while (has_next(it) and irrelevant(++it)) hull.erase(it--); it = update_left_border(it); if (has_prev(it)) { update_left_border(--it); } if (has_next(++it)) { update_left_border(++it); } } long long best(long long x) { Line q(0, 0); q.val = x; q.is_query = true; set<Line>::iterator it = hull.lower_bound(q); if (QUERY_MAX) --it; return it->a * x + it->b; } long long v[N], sum[N], resp; int main(void) { int n; scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %lld , v + i); sum[i + 1] = sum[i] + v[i]; resp += v[i] * (i + 1); } long long ans = resp; addLine(n, -sum[n]); for (int i = n - 1; i >= 1; i--) { long long x = v[i - 1]; long long value = best(x) + resp + sum[i] - v[i - 1] * i; addLine(i, -sum[i]); ans = max(ans, value); } hull.clear(); addLine(1, 0); for (int i = 2; i <= n; i++) { long long x = v[i - 1]; long long value = best(x) + resp + sum[i - 1] - v[i - 1] * i; addLine(i, -sum[i - 1]); ans = max(ans, value); } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { string s, ss; getline(cin, s); getline(cin, ss); int ara[500]; memset(ara, 0, sizeof ara); for (auto x : s) if (isalpha(x)) ara[x]++; bool ok = true; for (auto x : ss) { if (isalpha(x)) { if (!ara[x]) { ok = false; break; } else ara[x]--; } } if (ok) printf( YES n ); else printf( NO n ); return 0; } |
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_nios2_qsys_0_cpu_debug_slave_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
nios_system_nios2_qsys_0_cpu_debug_slave_tck the_nios_system_nios2_qsys_0_cpu_debug_slave_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
nios_system_nios2_qsys_0_cpu_debug_slave_sysclk the_nios_system_nios2_qsys_0_cpu_debug_slave_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic nios_system_nios2_qsys_0_cpu_debug_slave_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam nios_system_nios2_qsys_0_cpu_debug_slave_phy.sld_auto_instance_index = "YES",
// nios_system_nios2_qsys_0_cpu_debug_slave_phy.sld_instance_index = 0,
// nios_system_nios2_qsys_0_cpu_debug_slave_phy.sld_ir_width = 2,
// nios_system_nios2_qsys_0_cpu_debug_slave_phy.sld_mfg_id = 70,
// nios_system_nios2_qsys_0_cpu_debug_slave_phy.sld_sim_action = "",
// nios_system_nios2_qsys_0_cpu_debug_slave_phy.sld_sim_n_scan = 0,
// nios_system_nios2_qsys_0_cpu_debug_slave_phy.sld_sim_total_length = 0,
// nios_system_nios2_qsys_0_cpu_debug_slave_phy.sld_type_id = 34,
// nios_system_nios2_qsys_0_cpu_debug_slave_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(); cin.tie(); int t, n, a, b; cin >> t; while (t--) { int a, b; cin >> a >> b; int c = abs(a - b); int ans = 0; int tmp = c / 5; ans += tmp; c -= tmp * 5; tmp = c / 2; ans += tmp; c -= tmp * 2; tmp = c / 1; ans += tmp; c -= tmp * 1; cout << ans << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 2e9; const long long INFL = 2e18; const int N = 1e6, M = N; int n, m, G = 0; vector<int> adj[N + 5]; int gr[N + 5], p[N + 5]; vector<int> pth[N + 5]; vector<int> PTH_myEndlessLove; int Pos[N + 5]; void dfs(int u) { gr[u] = G; PTH_myEndlessLove.push_back(u); for (int i = (0), _b = (((int)(adj[u]).size())); i < _b; ++i) { int v = adj[u][i]; if (gr[v]) continue; dfs(v); } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> n >> m; for (int i = (1), _b = (n); i <= _b; ++i) cin >> p[i]; int u, v; while (m--) { cin >> u >> v; adj[p[u]].push_back(p[v]); adj[p[v]].push_back(p[u]); } for (int i = (1), _b = (n); i <= _b; ++i) if (!gr[p[i]]) { PTH_myEndlessLove.clear(); ++G; dfs(p[i]); sort(PTH_myEndlessLove.begin(), PTH_myEndlessLove.end()); reverse(PTH_myEndlessLove.begin(), PTH_myEndlessLove.end()); pth[G] = PTH_myEndlessLove; } for (int i = (1), _b = (n); i <= _b; ++i) { cout << pth[gr[p[i]]][Pos[gr[p[i]]]] << ; ++Pos[gr[p[i]]]; } cout << n ; return 0; } |
#include <bits/stdc++.h> inline int read() { int s = 0; char c; while ((c = getchar()) < 0 || c > 9 ) ; do { s = s * 10 + c - 0 ; } while ((c = getchar()) >= 0 && c <= 9 ); return s; } int n, l, r, ql, qr; long long ans; int main() { for (n = read(), l = r = read(); n--;) { ql = read(), qr = read(); if (ql <= l && r <= qr) continue; if (qr < l) ans += l - qr, r = l, l = qr; else if (r < ql) ans += ql - r, l = r, r = ql; else l = ql > l ? ql : l, r = qr < r ? qr : r; } printf( %I64d n , ans); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:30:27 03/03/2015
// Design Name:
// Module Name: vga
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module vga_driver(clk, color, hsync, vsync, red, green, blue, x, y);
// VGA signal explanation and timing values for specific modes:
// http://www-mtl.mit.edu/Courses/6.111/labkit/vga.shtml
// 640x480 @ 60Hz, 25MHz pixel clock
parameter H_ACTIVE = 640;
parameter H_FRONT = 16;
parameter H_PULSE = 96;
parameter H_BACK = 48;
parameter V_ACTIVE = 480;
parameter V_FRONT = 11;
parameter V_PULSE = 2;
parameter V_BACK = 31;
input clk;
input [7:0] color;
output hsync, vsync;
output [9:0] x, y;
output [2:0] red, green;
output [1:0] blue;
reg [9:0] h_count;
reg [9:0] v_count;
reg [6:0] bar_count;
reg [2:0] column_count;
always @(posedge clk)
begin
if (h_count < H_ACTIVE + H_FRONT + H_PULSE + H_BACK - 1)
begin
// Increment horizontal count for each tick of the pixel clock
h_count <= h_count + 1;
if (bar_count>91)
begin
bar_count <= 0;
column_count <= column_count+1;
end
else
begin
bar_count <= bar_count + 1;
end
end
else
begin
bar_count <= 0;
column_count <= 0;
// At the end of the line, reset horizontal count and increment vertical
h_count <= 0;
if (v_count < V_ACTIVE + V_FRONT + V_PULSE + V_BACK - 1)
v_count <= v_count + 1;
else
// At the end of the frame, reset vertical count
v_count <= 0;
end
end
// Generate horizontal and vertical sync pulses at the appropriate time
assign hsync = h_count > H_ACTIVE + H_FRONT && h_count < H_ACTIVE + H_FRONT + H_PULSE;
assign vsync = v_count > V_ACTIVE + V_FRONT && v_count < V_ACTIVE + V_FRONT + V_PULSE;
// Output x and y coordinates
assign x = h_count < H_ACTIVE ? h_count : 0;
assign y = v_count < V_ACTIVE ? v_count : 0;
// Generate separate RGB signals from different parts of color byte
// Output black during horizontal and vertical blanking intervals
assign red = h_count < H_ACTIVE && v_count < V_ACTIVE ? color[7:5] : 3'b0;
assign green = h_count < H_ACTIVE && v_count < V_ACTIVE ? color[4:2] : 3'b0;
assign blue = h_count < H_ACTIVE && v_count < V_ACTIVE ? color[1:0] : 2'b0;
assign colour_count = column_count;
endmodule
|
#include <bits/stdc++.h> int n, x, y, att, cnt; using namespace std; int main() { cin >> n >> x >> y; if (x > y) return cout << n, 0; for (int i = (1); i <= (n); i++) { cin >> att; if (att <= x) cnt++; } cout << (cnt + 1) / 2; } |
#include <bits/stdc++.h> using namespace std; long long int modular(long long int n, long long int pow, long long int N) { long long int res = 1; while (pow) { if (pow & 1) res = (res % N * n % N) % N; n = (n % N * n % N) % N; pow = pow / 2; } return res; } long long int d, x, y; void extendedEuclid(long long int A, long long int B) { if (B == 0) { d = A; x = 1; y = 0; } else { extendedEuclid(B, A % B); long long int temp = x; x = y; y = temp - (A / B) * y; } } long long int modInverse(long long int A, long long int N) { extendedEuclid(A, N); return (x % N + N) % N; } int main() { long long int n, i; cin >> n; vector<pair<long long int, long long int>> v; for (i = 0; i < n; i++) { long long int x, y; cin >> x >> y; v.push_back({x, y}); } long long int ans = min(v[n - 1].first, v[n - 1].second); long long int flag = 0; for (i = n - 2; i >= 0; i--) { if (v[i].second >= ans && v[i].first >= ans) ans = min(v[i].second, v[i].first); else if (v[i].second >= ans) ans = v[i].second; else if (v[i].first >= ans) ans = ans = v[i].first; else { flag = 1; break; } } if (flag == 1) cout << NO << endl; else cout << YES << endl; } |
#include <bits/stdc++.h> const int Maxn = 500000; int n; struct Answer { int l, r; } a[Maxn + 5]; int len; void work(int left, int right) { if (left == right) { return; } int mid = (left + right) >> 1; work(left, mid); work(mid + 1, right); for (int i = left; i <= mid; i++) { a[++len].l = i; a[len].r = mid + (i - left + 1); } } int main() { scanf( %d , &n); if (n <= 2) { puts( 0 ); return 0; } int lim = 1; while (lim <= n) { lim <<= 1; } lim >>= 1; work(1, lim); int m = n - lim; if (m > 0) { int sz = 1; while (sz < m) { sz <<= 1; } work(n - sz + 1, n); } printf( %d n , len); for (int i = 1; i <= len; i++) { printf( %d %d n , a[i].l, a[i].r); } return 0; } |
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* 10M/100M Ethernet MAC with MII interface
*/
module eth_mac_mii #
(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// Clock input style ("BUFG", "BUFR", "BUFIO", "BUFIO2")
// Use BUFR for Virtex-5, Virtex-6, 7-series
// Use BUFG for Ultrascale
// Use BUFIO2 for Spartan-6
parameter CLOCK_INPUT_STYLE = "BUFIO2",
parameter ENABLE_PADDING = 1,
parameter MIN_FRAME_LENGTH = 64
)
(
input wire rst,
output wire rx_clk,
output wire rx_rst,
output wire tx_clk,
output wire tx_rst,
/*
* AXI input
*/
input wire [7:0] tx_axis_tdata,
input wire tx_axis_tvalid,
output wire tx_axis_tready,
input wire tx_axis_tlast,
input wire tx_axis_tuser,
/*
* AXI output
*/
output wire [7:0] rx_axis_tdata,
output wire rx_axis_tvalid,
output wire rx_axis_tlast,
output wire rx_axis_tuser,
/*
* MII interface
*/
input wire mii_rx_clk,
input wire [3:0] mii_rxd,
input wire mii_rx_dv,
input wire mii_rx_er,
input wire mii_tx_clk,
output wire [3:0] mii_txd,
output wire mii_tx_en,
output wire mii_tx_er,
/*
* Status
*/
output wire tx_start_packet,
output wire tx_error_underflow,
output wire rx_start_packet,
output wire rx_error_bad_frame,
output wire rx_error_bad_fcs,
/*
* Configuration
*/
input wire [7:0] ifg_delay
);
wire [3:0] mac_mii_rxd;
wire mac_mii_rx_dv;
wire mac_mii_rx_er;
wire [3:0] mac_mii_txd;
wire mac_mii_tx_en;
wire mac_mii_tx_er;
mii_phy_if #(
.TARGET(TARGET),
.CLOCK_INPUT_STYLE(CLOCK_INPUT_STYLE)
)
mii_phy_if_inst (
.rst(rst),
.mac_mii_rx_clk(rx_clk),
.mac_mii_rx_rst(rx_rst),
.mac_mii_rxd(mac_mii_rxd),
.mac_mii_rx_dv(mac_mii_rx_dv),
.mac_mii_rx_er(mac_mii_rx_er),
.mac_mii_tx_clk(tx_clk),
.mac_mii_tx_rst(tx_rst),
.mac_mii_txd(mac_mii_txd),
.mac_mii_tx_en(mac_mii_tx_en),
.mac_mii_tx_er(mac_mii_tx_er),
.phy_mii_rx_clk(mii_rx_clk),
.phy_mii_rxd(mii_rxd),
.phy_mii_rx_dv(mii_rx_dv),
.phy_mii_rx_er(mii_rx_er),
.phy_mii_tx_clk(mii_tx_clk),
.phy_mii_txd(mii_txd),
.phy_mii_tx_en(mii_tx_en),
.phy_mii_tx_er(mii_tx_er)
);
eth_mac_1g #(
.ENABLE_PADDING(ENABLE_PADDING),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH)
)
eth_mac_1g_inst (
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.gmii_rxd(mac_mii_rxd),
.gmii_rx_dv(mac_mii_rx_dv),
.gmii_rx_er(mac_mii_rx_er),
.gmii_txd(mac_mii_txd),
.gmii_tx_en(mac_mii_tx_en),
.gmii_tx_er(mac_mii_tx_er),
.rx_clk_enable(1'b1),
.tx_clk_enable(1'b1),
.rx_mii_select(1'b1),
.tx_mii_select(1'b1),
.tx_start_packet(tx_start_packet),
.tx_error_underflow(tx_error_underflow),
.rx_start_packet(rx_start_packet),
.rx_error_bad_frame(rx_error_bad_frame),
.rx_error_bad_fcs(rx_error_bad_fcs),
.ifg_delay(ifg_delay)
);
endmodule
`resetall
|
module fifo_testbench ( );
/* Parameters */
parameter DATA_WIDTH = 1;
parameter FIFO_DEPTH = 8;
/* Variables */
reg [DATA_WIDTH - 1 : 0] wr_data = 0;
reg wr_clk = 0, wr_en = 1;
wire [DATA_WIDTH - 1 : 0] rd_data;
reg rd_clk = 0, rd_en = 1;
wire rd_valid;
wire full, empty;
reg reset = 0;
/* Behavioral */
// FIFO module instance
fifo #(
.DATA_WIDTH(DATA_WIDTH),
.FIFO_DEPTH(FIFO_DEPTH)
) fifo (
.wr_data(wr_data),
.wr_clk(wr_clk),
.wr_en(wr_en),
.rd_data(rd_data),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rd_valid(rd_valid),
.full(full),
.empty(empty),
.reset(reset)
);
// Write Clock Generation
always
#5 wr_clk = !wr_clk;
// Write Data Generation
always
#10 wr_data = !wr_data;
// Read Clock Generation
always
#3 rd_clk = !rd_clk & !full;
// Reset Generation
initial begin
#2 reset = 1;
#2 reset = 0;
end
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKINV_PP_SYMBOL_V
`define SKY130_FD_SC_HS__CLKINV_PP_SYMBOL_V
/**
* clkinv: Clock tree inverter.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__clkinv (
//# {{data|Data Signals}}
input A ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKINV_PP_SYMBOL_V
|
module station_management
#(
parameter STATE_IDLE = 4'd0,
parameter STATE_PREAMBLE = 4'd1,
parameter STATE_START_OF_FRAME = 4'd2,
parameter STATE_OPCODE = 4'd3,
parameter STATE_PHY_ADDRESS = 4'd4,
parameter STATE_REG_ADDRESS = 4'd5,
parameter STATE_TURNAROUND = 4'd6,
parameter STATE_DATA = 4'd7,
parameter STATE_OK = 4'd8,
parameter READ = 1'b0,
parameter WRITE = 1'b1
)(
input wire reset,
input wire clock,
output wire mdc,
input wire mdi,
output reg mdo,
input wire mode,
input wire begin_transaction,
input wire [4:0] phy_address,
input wire [4:0] reg_address,
input wire [15:0] data_in,
output reg [15:0] data_out
);
localparam start_of_frame = 2'b01;
localparam turnaround = 2'b10;
reg [3:0] state;
reg [3:0] next_state;
reg [1:0] opcode;
reg [15:0] data_read;
reg [4:0] preamble_counter;
reg start_of_frame_counter;
reg opcode_counter;
reg [2:0] phy_address_counter;
reg [2:0] reg_address_counter;
reg turnaround_counter;
reg [3:0] data_counter;
// MDC
assign mdc = clock;
// State Update
always @(posedge mdc)
if (reset)
state <= STATE_IDLE;
else
state <= next_state;
// State Machine
always @(*)
case(state)
STATE_IDLE:
if ( begin_transaction )
next_state <= STATE_PREAMBLE;
else
next_state <= STATE_IDLE;
STATE_PREAMBLE:
if (preamble_counter == 5'b0)
next_state <= STATE_START_OF_FRAME;
else
next_state <= STATE_PREAMBLE;
STATE_START_OF_FRAME:
if (start_of_frame_counter == 0)
next_state <= STATE_OPCODE;
else
next_state <= STATE_START_OF_FRAME;
STATE_OPCODE:
if (opcode_counter == 0)
next_state <= STATE_PHY_ADDRESS;
else
next_state <= STATE_OPCODE;
STATE_PHY_ADDRESS:
if (phy_address_counter == 0)
next_state <= STATE_REG_ADDRESS;
else
next_state <= STATE_PHY_ADDRESS;
STATE_REG_ADDRESS:
if (reg_address_counter == 0)
next_state <= STATE_TURNAROUND;
else
next_state <= STATE_REG_ADDRESS;
STATE_TURNAROUND:
if (turnaround_counter == 0)
next_state <= STATE_DATA;
else
next_state <= STATE_TURNAROUND;
STATE_DATA:
if (data_counter == 0)
next_state <= STATE_OK;
else
next_state <= STATE_DATA;
STATE_OK:
next_state <= STATE_IDLE;
default:
next_state <= STATE_IDLE;
endcase
// State Outputs
always @(*)
case(state)
STATE_IDLE:
mdo <= 0;
STATE_PREAMBLE:
mdo <= 1;
STATE_START_OF_FRAME:
mdo <= start_of_frame[start_of_frame_counter-:1];
STATE_OPCODE:
mdo <= opcode[opcode_counter-:1];
STATE_PHY_ADDRESS:
mdo <= phy_address[phy_address_counter-:1];
STATE_REG_ADDRESS:
mdo <= reg_address[reg_address_counter-:1];
STATE_TURNAROUND:
mdo <= (mode == READ) ? 1'bz : turnaround[turnaround_counter-:1];
STATE_DATA:
mdo <= (mode == READ) ? 1'bz : data_in[data_counter-:1];
default:
mdo <= 0;
endcase
always @(posedge mdc)
if (reset)
data_read <= 0;
else if (state == STATE_DATA && mode == READ)
begin
$display ("MDI: %b", mdi);
data_read[data_counter-:1] <= mdi;
end
else
data_read <= 0;
always @(*)
if (reset)
data_out <= 0;
else if (state == STATE_OK)
data_out <= data_read;
else
data_out <= data_out;
always @(*)
if (mode == READ)
opcode <= 2'b10;
else
opcode <= 2'b01;
// Counters
// Preamble
always @(posedge mdc)
if (reset)
preamble_counter <= 5'd31;
else if (state == STATE_PREAMBLE)
preamble_counter <= preamble_counter - 1;
else
preamble_counter <= 5'd31;
// Start of Frame
always @(posedge mdc)
if (reset)
start_of_frame_counter <= 1'b1;
else if (state == STATE_START_OF_FRAME)
start_of_frame_counter <= 1'b0;
else
start_of_frame_counter <= 1'b1;
// Opcode
always @(posedge mdc)
if (reset)
opcode_counter <= 1'b1;
else if (state == STATE_OPCODE)
opcode_counter <= 1'b0;
else
opcode_counter <= 1'b1;
// PHY Address
always @(posedge mdc)
if (reset)
phy_address_counter <= 3'd4;
else if (state == STATE_PHY_ADDRESS)
phy_address_counter <= phy_address_counter - 1;
else
phy_address_counter <= 3'd4;
// Register Address
always @(posedge mdc)
if (reset)
reg_address_counter <= 3'd4;
else if (state == STATE_REG_ADDRESS)
reg_address_counter <= reg_address_counter - 1;
else
reg_address_counter <= 3'd4;
// Turnaround
always @(posedge mdc)
if (reset)
turnaround_counter <= 1'b1;
else if (state == STATE_TURNAROUND)
turnaround_counter <= 1'b0;
else
turnaround_counter <= 1'b1;
// Data
always @(posedge mdc)
if (reset)
data_counter <= 4'd15;
else if (state == STATE_DATA)
data_counter <= data_counter - 1;
else
data_counter <= 4'd15;
endmodule
|
#include <bits/stdc++.h> int main(void) { char s[1001]; char t[1001]; scanf( %s %s , s, t); int idx = 0; while (s[idx] != 0 ) { if (t[idx] == 0 ) { puts( No ); return 0; } char cs = s[idx]; char ct = t[idx]; int cvowel = 0; int tvowel = 0; if (cs == a || cs == e || cs == i || cs == o || cs == u ) cvowel = 1; if (ct == a || ct == e || ct == i || ct == o || ct == u ) tvowel = 1; if (cvowel != tvowel) { puts( No ); return 0; } idx++; } if (t[idx] != 0 && s[idx] == 0 ) { puts( No ); return 0; } puts( Yes ); return 0; } |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// PN monitors
`timescale 1ns/100ps
module axi_ad6676_pnmon (
// adc interface
adc_clk,
adc_data,
// pn out of sync and error
adc_pn_oos,
adc_pn_err,
// processor interface
adc_pnseq_sel);
// adc interface
input adc_clk;
input [31:0] adc_data;
// pn out of sync and error
output adc_pn_oos;
output adc_pn_err;
// processor interface PN9 (0x0), PN23 (0x1)
input [ 3:0] adc_pnseq_sel;
// internal registers
reg [31:0] adc_pn_data_in = 'd0;
reg [31:0] adc_pn_data_pn = 'd0;
// internal signals
wire [31:0] adc_pn_data_pn_s;
// PN23 function
function [31:0] pn23;
input [31:0] din;
reg [31:0] dout;
begin
dout[31] = din[22] ^ din[17];
dout[30] = din[21] ^ din[16];
dout[29] = din[20] ^ din[15];
dout[28] = din[19] ^ din[14];
dout[27] = din[18] ^ din[13];
dout[26] = din[17] ^ din[12];
dout[25] = din[16] ^ din[11];
dout[24] = din[15] ^ din[10];
dout[23] = din[14] ^ din[ 9];
dout[22] = din[13] ^ din[ 8];
dout[21] = din[12] ^ din[ 7];
dout[20] = din[11] ^ din[ 6];
dout[19] = din[10] ^ din[ 5];
dout[18] = din[ 9] ^ din[ 4];
dout[17] = din[ 8] ^ din[ 3];
dout[16] = din[ 7] ^ din[ 2];
dout[15] = din[ 6] ^ din[ 1];
dout[14] = din[ 5] ^ din[ 0];
dout[13] = din[ 4] ^ din[22] ^ din[17];
dout[12] = din[ 3] ^ din[21] ^ din[16];
dout[11] = din[ 2] ^ din[20] ^ din[15];
dout[10] = din[ 1] ^ din[19] ^ din[14];
dout[ 9] = din[ 0] ^ din[18] ^ din[13];
dout[ 8] = din[22] ^ din[12];
dout[ 7] = din[21] ^ din[11];
dout[ 6] = din[20] ^ din[10];
dout[ 5] = din[19] ^ din[ 9];
dout[ 4] = din[18] ^ din[ 8];
dout[ 3] = din[17] ^ din[ 7];
dout[ 2] = din[16] ^ din[ 6];
dout[ 1] = din[15] ^ din[ 5];
dout[ 0] = din[14] ^ din[ 4];
pn23 = dout;
end
endfunction
// PN9 function
function [31:0] pn9;
input [31:0] din;
reg [31:0] dout;
begin
dout[31] = din[ 8] ^ din[ 4];
dout[30] = din[ 7] ^ din[ 3];
dout[29] = din[ 6] ^ din[ 2];
dout[28] = din[ 5] ^ din[ 1];
dout[27] = din[ 4] ^ din[ 0];
dout[26] = din[ 3] ^ din[ 8] ^ din[ 4];
dout[25] = din[ 2] ^ din[ 7] ^ din[ 3];
dout[24] = din[ 1] ^ din[ 6] ^ din[ 2];
dout[23] = din[ 0] ^ din[ 5] ^ din[ 1];
dout[22] = din[ 8] ^ din[ 0];
dout[21] = din[ 7] ^ din[ 8] ^ din[ 4];
dout[20] = din[ 6] ^ din[ 7] ^ din[ 3];
dout[19] = din[ 5] ^ din[ 6] ^ din[ 2];
dout[18] = din[ 4] ^ din[ 5] ^ din[ 1];
dout[17] = din[ 3] ^ din[ 4] ^ din[ 0];
dout[16] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
dout[15] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3];
dout[14] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[13] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[12] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0];
dout[11] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4];
dout[10] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3];
dout[ 9] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2];
dout[ 8] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1];
dout[ 7] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0];
dout[ 6] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4];
dout[ 5] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3];
dout[ 4] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[ 3] = din[ 7] ^ din[ 0] ^ din[ 5] ^ din[ 1];
dout[ 2] = din[ 6] ^ din[ 8] ^ din[ 0];
dout[ 1] = din[ 5] ^ din[ 7] ^ din[ 8] ^ din[ 4];
dout[ 0] = din[ 4] ^ din[ 6] ^ din[ 7] ^ din[ 3];
pn9 = dout;
end
endfunction
// pn sequence select
assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in : adc_pn_data_pn;
always @(posedge adc_clk) begin
adc_pn_data_in <= {adc_data[15:0], adc_data[31:16]};
if (adc_pnseq_sel == 4'd0) begin
adc_pn_data_pn <= pn9(adc_pn_data_pn_s);
end else begin
adc_pn_data_pn <= pn23(adc_pn_data_pn_s);
end
end
// pn oos & pn err
ad_pnmon #(.DATA_WIDTH(32)) i_pnmon (
.adc_clk (adc_clk),
.adc_valid_in (1'b1),
.adc_data_in (adc_pn_data_in),
.adc_data_pn (adc_pn_data_pn),
.adc_pn_oos (adc_pn_oos),
.adc_pn_err (adc_pn_err));
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; long long a, b, c, l; long long sum; int main() { cin >> a >> b >> c >> l; sum = ((l + 1) * (l + 2) * (l + 3)) / 6; for (long long i = 0; i <= l; i++) { long long temp1 = a - b - c + i; if (temp1 >= 0) { long long temp2 = l - i; long long x = min(temp1, temp2); sum -= (x + 1) * (x + 2) / 2; } } for (long long i = 0; i <= l; i++) { long long temp1 = b - a - c + i; if (temp1 >= 0) { long long temp2 = l - i; long long x = min(temp1, temp2); sum -= (x + 1) * (x + 2) / 2; } } for (long long i = 0; i <= l; i++) { long long temp1 = c - b - a + i; if (temp1 >= 0) { long long temp2 = l - i; long long x = min(temp1, temp2); sum -= (x + 1) * (x + 2) / 2; } } cout << sum << endl; } |
#include <bits/stdc++.h> using namespace std; template <class T> class Node { public: Node<T> *prev; Node<T> *next; T data; Node(T data); }; template <class T> Node<T>::Node(T data) { this->data = data; } template <class T> class Stack { public: Node<T> *top; int size; Stack(); bool empty(); void push(T a); void pop(); void clear(); }; template <class T> Stack<T>::Stack() { top = NULL; size = 0; } template <class T> bool Stack<T>::empty() { return (size == 0); } template <class T> void Stack<T>::push(T data) { Node<T> *t = new Node<T>(data); t->next = top; top = t; size++; return; } template <class T> void Stack<T>::pop() { top = top->next; size--; return; } template <class T> void Stack<T>::clear() { top = NULL; size = 0; } int main() { Stack<int> *st = new Stack<int>(); int n; cin >> n; int a; int answer = 0; int size = 0; int leftSum = 0, rightSum = 0; for (int i = 0; i < n; i++) { cin >> a; rightSum = rightSum + a; st->push(a); size++; } while (!st->empty()) { leftSum = leftSum + st->top->data; rightSum = rightSum - st->top->data; if (leftSum == rightSum && size != 1) answer++; st->pop(); size--; } cout << answer; return 0; } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ff_jbi_sc2_2.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module ff_jbi_sc2_2(/*AUTOARG*/
// Outputs
jbi_sctag_req_d1, scbuf_jbi_data_d1, jbi_scbuf_ecc_d1,
jbi_sctag_req_vld_d1, scbuf_jbi_ctag_vld_d1, scbuf_jbi_ue_err_d1,
sctag_jbi_iq_dequeue_d1, sctag_jbi_wib_dequeue_d1,
sctag_jbi_por_req_d1, so,
// Inputs
jbi_sctag_req, scbuf_jbi_data, jbi_scbuf_ecc, jbi_sctag_req_vld,
scbuf_jbi_ctag_vld, scbuf_jbi_ue_err, sctag_jbi_iq_dequeue,
sctag_jbi_wib_dequeue, sctag_jbi_por_req, rclk, si, se
);
output [31:0] jbi_sctag_req_d1;
output [31:0] scbuf_jbi_data_d1;
output [6:0] jbi_scbuf_ecc_d1;
output jbi_sctag_req_vld_d1;
output scbuf_jbi_ctag_vld_d1;
output scbuf_jbi_ue_err_d1;
output sctag_jbi_iq_dequeue_d1;
output sctag_jbi_wib_dequeue_d1;
output sctag_jbi_por_req_d1;
input [31:0] jbi_sctag_req;
input [31:0] scbuf_jbi_data;
input [6:0] jbi_scbuf_ecc;
input jbi_sctag_req_vld;
input scbuf_jbi_ctag_vld;
input scbuf_jbi_ue_err;
input sctag_jbi_iq_dequeue;
input sctag_jbi_wib_dequeue;
input sctag_jbi_por_req;
input rclk;
input si, se;
output so;
wire int_scanout;
// connect scanout of the last flop to int_scanout.
// The output of the lockup latch is
// the scanout of this dbb (so)
bw_u1_scanlg_2x so_lockup(.so(so), .sd(int_scanout), .ck(rclk), .se(se));
dff_s #(32) ff_flop_row0 (.q(jbi_sctag_req_d1[31:0]),
.din(jbi_sctag_req[31:0]),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(32) ff_flop_row1 (.q(scbuf_jbi_data_d1[31:0]),
.din(scbuf_jbi_data[31:0]),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(13) ff_flop_row2 (.q({ jbi_scbuf_ecc_d1[6:0],
jbi_sctag_req_vld_d1,
scbuf_jbi_ctag_vld_d1,
scbuf_jbi_ue_err_d1,
sctag_jbi_iq_dequeue_d1,
sctag_jbi_wib_dequeue_d1,
sctag_jbi_por_req_d1}),
.din({ jbi_scbuf_ecc[6:0],
jbi_sctag_req_vld,
scbuf_jbi_ctag_vld,
scbuf_jbi_ue_err,
sctag_jbi_iq_dequeue,
sctag_jbi_wib_dequeue,
sctag_jbi_por_req}),
.clk(rclk), .se(1'b0), .si(), .so() );
endmodule
|
module main(
// clocks
input fclk,
output clkz_out,
input clkz_in,
// z80
input iorq_n,
input mreq_n,
input rd_n,
input wr_n,
input m1_n,
input rfsh_n,
output int_n,
output nmi_n,
output wait_n,
output res,
inout [7:0] d,
input [15:0] a,
// zxbus and related
output csrom,
output romoe_n,
output romwe_n,
output rompg0_n,
output dos_n, // aka rompg1
output rompg2,
output rompg3,
output rompg4,
input iorqge1,
input iorqge2,
output iorq1_n,
output iorq2_n,
// DRAM
inout [15:0] rd,
output [9:0] ra,
output rwe_n,
output rucas_n,
output rlcas_n,
output rras0_n,
output rras1_n,
// video
output [1:0] vred,
output [1:0] vgrn,
output [1:0] vblu,
output vhsync,
output vvsync,
output vcsync,
// AY control and audio/tape
output ay_clk,
output ay_bdir,
output ay_bc1,
output beep,
// IDE
output [2:0] ide_a,
inout [15:0] ide_d,
output ide_dir,
input ide_rdy,
output ide_cs0_n,
output ide_cs1_n,
output ide_rs_n,
output ide_rd_n,
output ide_wr_n,
// VG93 and diskdrive
output vg_clk,
output vg_cs_n,
output vg_res_n,
output vg_hrdy,
output vg_rclk,
output vg_rawr,
output [1:0] vg_a, // disk drive selection
output vg_wrd,
output vg_side,
input step,
input vg_sl,
input vg_sr,
input vg_tr43,
input rdat_b_n,
input vg_wf_de,
input vg_drq,
input vg_irq,
input vg_wd,
// serial links (atmega-fpga, sdcard)
output sdcs_n,
output sddo,
output sdclk,
input sddi,
input spics_n,
input spick,
input spido,
output spidi,
output spiint_n
);
wire zclk; // z80 clock for short
reg [2:0] zclk_gen; // make 3.5 mhz clock
wire rst_n; // global reset
wire rrdy;
wire cbeg;
wire [15:0] rddata;
wire [4:0] rompg;
wire [7:0] zports_dout;
wire zports_dataout;
wire porthit;
wire [4:0] keys;
wire tape_in;
wire [15:0] ideout;
wire [15:0] idein;
wire [7:0] zmem_dout;
wire zmem_dataout;
wire [7:0] sd_dout_to_zports;
wire start_from_zports;
wire sd_inserted;
wire sd_readonly;
reg [3:0] ayclk_gen;
wire [7:0] received;
wire [7:0] tobesent;
wire intrq,drq;
wire vg_wrFF;
// Z80 clock control
assign zclk = clkz_in;
always @(posedge fclk)
zclk_gen <= zclk_gen + 3'd1;
assign clkz_out = zclk_gen[2];
// RESETTER
resetter myrst( .clk(fclk),
.rst_in_n(ide_rdy),
.rst_out_n(rst_n) );
defparam myrst.RST_CNT_SIZE = 6;
assign int_n=1'b1;
assign nmi_n=1'b1;
assign wait_n=1'b1;
assign res=1'b1;
assign d=8'hZZ;
assign csrom=1'b0;
assign romoe_n=1'b1;
assign romwe_n=1'b1;
assign iorq1_n=1'b1;
assign iorq2_n=1'b1;
assign rd=16'hZZZZ;
assign ay_bdir=1'b0;
assign ay_bc1=1'b0;
assign ide_d=16'hZZZZ;
assign ide_dir=1'b1;
assign ide_rs_n = 1'b0;
assign ide_cs1_n = 1'b1;
assign ide_rd_n = 1'b1;
assign ide_wr_n = 1'b1;
assign vg_cs_n=1'b1;
assign vg_res_n=1'b0;
assign sdcs_n=1'b1;
assign spiint_n=1'b1;
//AY control
always @(posedge fclk)
begin
ayclk_gen <= ayclk_gen + 4'd1;
end
assign ay_clk = ayclk_gen[3];
wire blinker;
assign ide_cs0_n = blinker;
mem_tester mytst( .clk(fclk), .rst_n(rst_n), .led(blinker), .rstart(ide_a[0]), .rready(ide_a[1]), .rstop(ide_a[2]),
.DRAM_DQ(rd), .DRAM_MA(ra), .DRAM_RAS0_N(rras0_n), .DRAM_RAS1_N(rras1_n),
.DRAM_LCAS_N(rlcas_n), .DRAM_UCAS_N(rucas_n), .DRAM_WE_N(rwe_n) );
endmodule
|
/*
* ALU.
*
* AI and BI are 8 bit inputs. Result in OUT.
* CI is Carry In.
* CO is Carry Out.
*
* op[3:0] is defined as follows:
*
* 0011 AI + BI
* 0111 AI - BI
* 1011 AI + AI
* 1100 AI | BI
* 1101 AI & BI
* 1110 AI ^ BI
* 1111 AI
*
*/
module ALU( clk, op, right, AI, BI, CI, CO, BCD, OUT, V, Z, N, HC, RDY );
input clk;
input right;
input [3:0] op; // operation
input [7:0] AI;
input [7:0] BI;
input CI;
input BCD; // BCD style carry
output [7:0] OUT;
output CO;
output V;
output Z;
output N;
output HC;
input RDY;
reg [7:0] OUT;
reg CO;
wire V;
wire Z;
reg N;
reg HC;
reg AI7;
reg BI7;
reg [8:0] temp_logic;
reg [7:0] temp_BI;
reg [4:0] temp_l;
reg [4:0] temp_h;
wire [8:0] temp = { temp_h, temp_l[3:0] };
wire adder_CI = (right | (op[3:2] == 2'b11)) ? 0 : CI;
// calculate the logic operations. The 'case' can be done in 1 LUT per
// bit. The 'right' shift is a simple mux that can be implemented by
// F5MUX.
always @* begin
case( op[1:0] )
2'b00: temp_logic = AI | BI;
2'b01: temp_logic = AI & BI;
2'b10: temp_logic = AI ^ BI;
2'b11: temp_logic = AI;
endcase
if( right )
temp_logic = { AI[0], CI, AI[7:1] };
end
// Add logic result to BI input. This only makes sense when logic = AI.
// This stage can be done in 1 LUT per bit, using carry chain logic.
always @* begin
case( op[3:2] )
2'b00: temp_BI = BI; // A+B
2'b01: temp_BI = ~BI; // A-B
2'b10: temp_BI = temp_logic; // A+A
2'b11: temp_BI = 0; // A+0
endcase
end
// HC9 is the half carry bit when doing BCD add
wire HC9 = BCD & (temp_l[3:1] >= 3'd5);
// CO9 is the carry-out bit when doing BCD add
wire CO9 = BCD & (temp_h[3:1] >= 3'd5);
// combined half carry bit
wire temp_HC = temp_l[4] | HC9;
// perform the addition as 2 separate nibble, so we get
// access to the half carry flag
always @* begin
temp_l = temp_logic[3:0] + temp_BI[3:0] + adder_CI;
temp_h = temp_logic[8:4] + temp_BI[7:4] + temp_HC;
end
// calculate the flags
always @(posedge clk)
if( RDY ) begin
AI7 <= AI[7];
BI7 <= temp_BI[7];
OUT <= temp[7:0];
CO <= temp[8] | CO9;
N <= temp[7];
HC <= temp_HC;
end
assign V = AI7 ^ BI7 ^ CO ^ N;
assign Z = ~|OUT;
endmodule
|
#include <bits/stdc++.h> using namespace std; struct Query { int l, r, x; Query(int l = 0, int r = 0, int x = 0) : l(l), r(r), x(x) {} }; struct node { int pref, suff, val; node(int pref = 0, int suff = 0, int val = 0) : pref(pref), suff(suff), val(val) {} }; int n, k; map<int, int> ha; int hacnt; int a[100005]; node st[4000000]; int lazy[4000000]; Query queries[100005]; int ori[1000005]; bool changed[1000000]; set<int> vals; int mn; int st1[5000000]; void build1(int p = 1, int l = 0, int r = n - 1) { if (l == r) { st1[p] = a[l]; return; } int mid = (l + r) >> 1; build1(p * 2, l, mid); build1(p * 2 + 1, mid + 1, r); st1[p] = min(st1[p * 2], st1[p * 2 + 1]); } int query1(int i, int j, int p = 1, int l = 0, int r = n - 1) { if (i > r || j < l) return 1e9 + 3; if (i <= l && j >= r) return st1[p]; int mid = (l + r) >> 1; int c1 = query1(i, j, p * 2, l, mid); int c2 = query1(i, j, p * 2 + 1, mid + 1, r); return min(c1, c2); } int get(int l, int r) { if (l > r) return 1000000008; if (r - l + 1 >= n) return mn; l %= n, r %= n; if (l > r) return min(query1(l, n - 1), query1(0, r)); return query1(l, r); } void merge(node& ret, node& x, node& y) { ret.pref = x.pref; ret.suff = y.suff; ret.val = min(x.val, x.suff); ret.val = min(ret.val, min(y.val, y.pref)); } void pushLazy(int p) { if (lazy[p]) { lazy[p * 2] = lazy[p * 2 + 1] = lazy[p]; st[p] = node(1000000008, 1000000008, lazy[p]); lazy[p] = 0; } } void build(int p = 1, int l = 1, int r = hacnt - 1) { if (l == r) { if (l != 1) st[p].pref = get(ori[l - 1] + 1, ori[l] - 1); else st[p].pref = 1000000008; if (r != hacnt - 1) st[p].suff = get(ori[r] + 1, ori[r + 1] - 1); else st[p].suff = 1000000008; st[p].val = get(ori[l], ori[l]); return; } int mid = (l + r) >> 1; build(p * 2, l, mid); build(p * 2 + 1, mid + 1, r); merge(st[p], st[p * 2], st[p * 2 + 1]); } void update(int i, int j, int x, int p = 1, int l = 1, int r = hacnt - 1) { pushLazy(p); if (i > r || j < l) return; if (i <= l && j >= r) { lazy[p] = x; pushLazy(p); return; } int mid = (l + r) >> 1; update(i, j, x, p * 2, l, mid); update(i, j, x, p * 2 + 1, mid + 1, r); merge(st[p], st[p * 2], st[p * 2 + 1]); } int query(int i, int j, int p = 1, int l = 1, int r = hacnt - 1) { pushLazy(p); if (i > r || j < l) return 1000000008; if (i <= l && j >= r) { int ret = 1000000008; if (i != l) ret = min(ret, st[p].pref); if (j != r) ret = min(ret, st[p].suff); ret = min(ret, st[p].val); return ret; } int mid = (l + r) >> 1; int c1 = query(i, j, p * 2, l, mid); int c2 = query(i, j, p * 2 + 1, mid + 1, r); return min(c1, c2); } int main() { scanf( %d%d , &n, &k); mn = 1e9 + 1; for (int i = 0; i < n; i++) scanf( %d , &a[i]), mn = min(mn, a[i]); build1(); int q; scanf( %d , &q); for (int i = 0; i < q; i++) { int type; scanf( %d , &type); if (type == 1) { int l, r, x; scanf( %d%d%d , &l, &r, &x); l--, r--; queries[i] = Query(l, r, x); ha[l]; ha[r]; } else { int l, r; scanf( %d%d , &l, &r); l--, r--; ha[l]; ha[r]; queries[i] = Query(l, r, -1); } } hacnt = 1; for (map<int, int>::iterator it = ha.begin(); it != ha.end(); it++) { it->second = hacnt; ori[hacnt] = it->first; vals.insert(hacnt); hacnt++; } build(); for (int i = 0; i < q; i++) { int l = queries[i].l, r = queries[i].r, x = queries[i].x; if (x < 0) { int ans = query(ha[l], ha[r]); printf( %d n , ans); } else { update(ha[l], ha[r], x); int from = ha[l]; int to = ha[r]; while (1) { set<int>::iterator it = vals.lower_bound(from); if (it == vals.end() || *it > to) break; changed[*it] = 1; vals.erase(it); } } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 500; const int M = 1e6 + 500; const int INF = 0x3f3f3f3f; const int MOD = 1e9 + 7; const int LOG = 20; const int OFF = (1 << 20); const double EPS = 1e-9; const double PI = 3.1415926535; set<int> st; int n, x, l, r; char s[10]; long long sol = 1; int main() { st.insert(-INF); st.insert(INF); sol = 1; l = -INF; r = INF; scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %s , s); scanf( %d , &x); if (s[1] == D ) { st.insert(x); } else { st.erase(x); if (l <= x && x <= r) { if (x != l && x != r) sol = (2LL * sol) % (long long)MOD; l = *(--st.upper_bound(x)); r = *st.upper_bound(x); } else { sol = 0; } } } int cnt = 0; for (int x : st) { if (l <= x && x <= r) cnt++; } sol = (sol * (cnt - 1)) % (long long)MOD; printf( %d n , (int)sol); return 0; } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_ddr_vref_logic_high.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_ddr_vref_logic_high(in,vrefcode,vdd18);
input vdd18;
input [7:1] in;
output [7:0] vrefcode;
assign vrefcode[7:0] = {in[7:1],1'b0};
endmodule
|
#include <bits/stdc++.h> using namespace std; signed main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long n; cin >> n; vector<pair<long long, long long> > v(n); for (long long i = 0; i < n; i++) { cin >> v[i].first >> v[i].second; } long long sum = 0; for (long long i = 0; i < n; i++) { for (long long j = i + 1; j < n; j++) { pair<long long, long long> p1 = v[i], p2 = v[j]; bool flag = true; if (p1.first > p2.first || p1.first == p2.first && i < j) { swap(p1, p2); flag = false; } vector<pair<long long, pair<long long, long long> > > p(4); if (flag) { p[0] = {p1.first, {-i, 1}}; p[1] = {p1.first + p1.second, {-i, 2}}; p[2] = {p2.first, {-j, 3}}; p[3] = {p2.first + p2.second, {-j, 4}}; } else { p[0] = {p1.first, {-j, 1}}; p[1] = {p1.first + p1.second, {-j, 2}}; p[2] = {p2.first, {-i, 3}}; p[3] = {p2.first + p2.second, {-i, 4}}; } sort(p.begin(), p.end()); vector<long long> g(4); for (long long h = 0; h < 4; h++) { g[h] = p[h].second.second; } if (g[0] == 1 && g[2] == 2 && g[1] == 3 && g[3] == 4 || g[0] == 2 && g[2] == 1 && g[3] == 3 && g[1] == 4) sum += 2; else if (g[0] == 1 && g[3] == 2 || g[1] == 2 && g[2] == 1 || g[1] == 1 && g[2] == 2 || g[1] == 1 && g[2] == 3 && g[3] == 2 && g[0] == 4 || g[0] == 1 && g[2] == 2 && g[3] == 3 && g[1] == 4) sum++; } } cout << sum; } |
#include <bits/stdc++.h> using namespace std; int n; int a[210000]; long long sum[210000]; long long calc_move(int from, int to) { return a[from] * 1ll * (to - from) - (sum[to] - sum[from]); } long long crossover(int from, int to) { long long headstart = calc_move(from, to); if (headstart < 0) return to; return to + 1 + headstart / (a[to] - a[from]); } long long solve() { long long ret = 0; deque<int> q; for (int(i) = 0; (i) < (int)(n); (i)++) sum[i] = (i == 0 ? 0 : sum[i - 1]) + a[i]; int largest_so_far = -100000000; for (int(i) = 0; (i) < (int)(n); (i)++) { if (a[i] > largest_so_far) { while (q.size() >= 2 && crossover(q[0], q[1]) >= crossover(q[0], i)) q.pop_back(); q.push_back(i); largest_so_far = a[i]; } while (q.size() >= 2 && crossover(q[0], q[1]) <= i) q.pop_front(); ret = max(ret, calc_move(q[0], i)); } return ret; } int main() { long long start_char = 0; scanf( %d , &n); for (int(i) = 0; (i) < (int)(n); (i)++) { scanf( %d , &a[i]); start_char += (i + 1) * 1ll * a[i]; } long long best_delta = solve(); reverse(a, a + n); for (int(i) = 0; (i) < (int)(n); (i)++) a[i] = -a[i]; best_delta = max(best_delta, solve()); printf( %lld n , start_char + best_delta); } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLRTN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__DLRTN_FUNCTIONAL_PP_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_lp__udp_dlatch_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dlrtn (
Q ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire intgate;
wire buf_Q ;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intgate, GATE_N );
sky130_fd_sc_lp__udp_dlatch$PR_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, intgate, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLRTN_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR3B_PP_SYMBOL_V
`define SKY130_FD_SC_LP__NOR3B_PP_SYMBOL_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nor3b (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR3B_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; long long a[100005]; set<int> b; set<int>::iterator it; int main() { long long n, i, s, x, y, z, d, st; scanf( %lld , &n); for (i = 0; i < n; i++) { scanf( %lld , &x); b.insert(x); } n = 0; for (it = b.begin(); it != b.end(); it++) a[n++] = *it; scanf( %lld%lld , &x, &y); s = 0; st = 0; while (y < x) { z = x - 1; for (i = n - 1; i >= st; i--) { d = x - x % a[i]; if (z > d && d >= y) z = d; } x = z; while (n > st && x - x % a[st] < y) st++; while (n > 0 && x - x % a[n - 1] < y) n--; s++; } printf( %lld n , s); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FILL_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__FILL_PP_BLACKBOX_V
/**
* fill: Fill cell.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__fill (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__FILL_PP_BLACKBOX_V
|
//======================================================================
//
// rosc_entropy_core.v
// -------------------
// Digitial ring oscillator based entropy generation core.
// This version implements 32 separate oscillators where each
// oscillator can be enabled or disabled.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module rosc_entropy_core(
input wire clk,
input wire reset_n,
input wire [31 : 0] opa,
input wire [31 : 0] opb,
input wire [31 : 0] rosc_en,
input wire [7 : 0] rosc_cycles,
output wire [31 : 0] raw_entropy,
output wire [31 : 0] rosc_outputs,
output wire [31 : 0] entropy_data,
output wire entropy_valid,
input wire entropy_ack,
output wire [7 : 0] debug,
input wire debug_update
);
//----------------------------------------------------------------
// Parameters.
//----------------------------------------------------------------
localparam ADDER_WIDTH = 2;
localparam DEBUG_DELAY = 32'h002c4b40;
localparam NUM_SHIFT_BITS = 8'h20;
localparam SAMPLE_CLK_CYCLES = 8'hff;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [31 : 0] ent_shift_reg;
reg [31 : 0] ent_shift_new;
reg ent_shift_we;
reg [31 : 0] entropy_reg;
reg entropy_we;
reg entropy_valid_reg;
reg entropy_valid_new;
reg entropy_valid_we;
reg bit_we_reg;
reg bit_we_new;
reg [7 : 0] bit_ctr_reg;
reg [7 : 0] bit_ctr_new;
reg bit_ctr_inc;
reg bit_ctr_we;
reg [7 : 0] sample_ctr_reg;
reg [7 : 0] sample_ctr_new;
reg [31 : 0] debug_delay_ctr_reg;
reg [31 : 0] debug_delay_ctr_new;
reg debug_delay_ctr_we;
reg [7 : 0] debug_reg;
reg debug_we;
reg debug_update_reg;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] rosc_we;
// Ugly in-line Xilinx attribute to preserve the registers.
(* equivalent_register_removal = "no" *)
wire [31 : 0] rosc_dout;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign rosc_outputs = rosc_dout;
assign raw_entropy = ent_shift_reg;
assign entropy_data = entropy_reg;
assign entropy_valid = entropy_valid_reg;
assign debug = debug_reg;
//----------------------------------------------------------------
// module instantiations.
//
// 32 oscillators each ADDER_WIDTH wide. We want them to run
// as fast as possible to maximize differences over time.
// We also only sample the oscillators SAMPLE_CLK_CYCLES number
// of cycles.
//----------------------------------------------------------------
genvar i;
generate
for(i = 0 ; i < 32 ; i = i + 1)
begin: oscillators
rosc #(.WIDTH(ADDER_WIDTH)) rosc_array(.clk(clk),
.we(rosc_we[i]),
.reset_n(reset_n),
.opa(opa[(ADDER_WIDTH - 1) : 0]),
.opb(opb[(ADDER_WIDTH - 1) : 0]),
.dout(rosc_dout[i])
);
end
endgenerate
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
ent_shift_reg <= 32'h00000000;
entropy_reg <= 32'h00000000;
entropy_valid_reg <= 0;
bit_ctr_reg <= 8'h00;
sample_ctr_reg <= 8'h00;
debug_delay_ctr_reg <= 32'h00000000;
debug_reg <= 8'h00;
debug_update_reg <= 0;
end
else
begin
sample_ctr_reg <= sample_ctr_new;
debug_update_reg <= debug_update;
if (ent_shift_we)
begin
ent_shift_reg <= ent_shift_new;
end
if (bit_ctr_we)
begin
bit_ctr_reg <= bit_ctr_new;
end
if (entropy_we)
begin
entropy_reg <= ent_shift_reg;
end
if (entropy_valid_we)
begin
entropy_valid_reg <= entropy_valid_new;
end
if (debug_delay_ctr_we)
begin
debug_delay_ctr_reg <= debug_delay_ctr_new;
end
if (debug_we)
begin
debug_reg <= ent_shift_reg[7 : 0];
end
end
end // reg_update
//----------------------------------------------------------------
// debug_out
//
// Logic that updates the debug port.
//----------------------------------------------------------------
always @*
begin : debug_out
debug_delay_ctr_new = 32'h00000000;
debug_delay_ctr_we = 0;
debug_we = 0;
if (debug_update_reg)
begin
debug_delay_ctr_new = debug_delay_ctr_reg + 1'b1;
debug_delay_ctr_we = 1;
end
if (debug_delay_ctr_reg == DEBUG_DELAY)
begin
debug_delay_ctr_new = 32'h00000000;
debug_delay_ctr_we = 1;
debug_we = 1;
end
end
//----------------------------------------------------------------
// entropy_out
//
// Logic that implements the random output control. If we have
// added more than NUM_SHIFT_BITS we raise the entropy_valid flag.
// When we detect and ACK, the valid flag is dropped.
//----------------------------------------------------------------
always @*
begin : entropy_out
bit_ctr_new = 8'h00;
bit_ctr_we = 0;
entropy_we = 0;
entropy_valid_new = 0;
entropy_valid_we = 0;
if (bit_ctr_inc)
begin
if (bit_ctr_reg < NUM_SHIFT_BITS)
begin
bit_ctr_new = bit_ctr_reg + 1'b1;
bit_ctr_we = 1;
end
else
begin
entropy_we = 1;
entropy_valid_new = 1;
entropy_valid_we = 1;
end
end
if (entropy_ack)
begin
bit_ctr_new = 8'h00;
bit_ctr_we = 1;
entropy_valid_new = 0;
entropy_valid_we = 1;
end
end
//----------------------------------------------------------------
// entropy_gen
//
// Logic that implements the actual entropy bit value generator
// by XOR mixing the oscillator outputs. These outputs are
// sampled once every SAMPLE_CLK_CYCLES.
//----------------------------------------------------------------
always @*
begin : entropy_gen
reg ent_bit;
bit_ctr_inc = 0;
rosc_we = 32'h00000000;
ent_shift_we = 0;
ent_bit = ^rosc_dout;
ent_shift_new = {ent_shift_reg[30 : 0], ent_bit};
sample_ctr_new = sample_ctr_reg + 1'b1;
if (sample_ctr_reg == SAMPLE_CLK_CYCLES)
begin
sample_ctr_new = 8'h00;
bit_ctr_inc = 1;
rosc_we = rosc_en;
ent_shift_we = 1;
end
end
endmodule // rosc_entropy_core
//======================================================================
// EOF rosc_entropy_core.v
//======================================================================
|
module Board(clkin, /*reset,*/ rgb, led, segments, buttons, enable_segments, hsync, vsync);
input clkin /*verilator clocker*/;
reg reset;
initial reset = 1;
output [5:0] rgb;
output hsync, vsync;
input [4:0] buttons;
wire halt;
wire [15:0] data_bus;
wire [15:0] address_bus;
wire [7:0] interrupts;
wire clk;
wire write, read;
//buttons
wire cs_buttons; assign cs_buttons = read && address_bus[15:12] == 4'hB;
Buttons module_buttons(data_bus, cs_buttons, interrupts[7], buttons);
//diodes
output [15:0] led;
wire cs_diodes; assign cs_diodes = address_bus[15:12] == 4'h9;
Diodes diodes(data_bus, led, cs_diodes, write);
//led counter
output [3:0] enable_segments;
output [7:0] segments;
wire cs_led_counter; assign cs_led_counter = address_bus[15:12] == 4'hA;
LedCounter led_counter(
.clk(clk),
.data_bus(data_bus),
.enable(cs_led_counter),
.write(write),
.segments(segments),
.enable_segments(enable_segments));
//clock
//Dcm dcm(
// .CLKIN_IN(clkin),
// .RST_IN(reset),
// .CLKFX_OUT(clk),
// .CLKIN_IBUFG_OUT());
//assign clk = clkin;
reg [3:0] clk_counter;
initial clk_counter = 0;
assign clk = clk_counter[3];
always @ (posedge clkin) begin
clk_counter = clk_counter + 1;
end
reg [3:0] counter;
initial counter = 0;
//initial led_counter = 0;
always @ (posedge clk) begin
counter = counter + 1;
if (&counter) begin
reset = 0;
//led_counter <= led_counter + 1;
end
end
//assign led = led_counter;
//gpu
wire cs_gpu; assign cs_gpu = address_bus[15:12] == 4'b1111;
Gpu gpu(
.clk(clk),
.reset(reset),
.data_bus(data_bus),
.address_bus(address_bus[7:0]),
.w(cs_gpu & write),
.r(cs_gpu & read),
.hs(hsync),
.vs(vsync),
.color(rgb));
//ram
wire cs_ram; assign cs_ram = !address_bus[15];
Ram ram(
.clk(clk),
.data_bus(data_bus),
.address_bus(address_bus[10:0]),
.enable(cs_ram),
.write(write),
.read(read));
//cpu
Cpu cpu(
.clk(clk),
.reset(reset),
.data_bus(data_bus),
.address_bus(address_bus),
.r(read),
.w(write),
.interrupts(interrupts),
.halt(halt));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
module sky130_fd_io__top_xres4v2 ( TIE_WEAK_HI_H, XRES_H_N, TIE_HI_ESD, TIE_LO_ESD,
AMUXBUS_A, AMUXBUS_B, PAD, PAD_A_ESD_H, ENABLE_H, EN_VDDIO_SIG_H, INP_SEL_H, FILT_IN_H,
DISABLE_PULLUP_H, PULLUP_H, ENABLE_VDDIO
);
wire mode_vcchib;
output XRES_H_N;
inout AMUXBUS_A;
inout AMUXBUS_B;
inout PAD;
input DISABLE_PULLUP_H;
input ENABLE_H;
input EN_VDDIO_SIG_H;
input INP_SEL_H;
input FILT_IN_H;
inout PULLUP_H;
input ENABLE_VDDIO;
supply1 vccd;
supply1 vcchib;
supply1 vdda;
supply1 vddio;
supply1 vddio_q;
supply0 vssa;
supply0 vssd;
supply0 vssio;
supply0 vssio_q;
supply1 vswitch;
wire pwr_good_xres_tmp = 1;
wire pwr_good_xres_h_n = 1;
wire pwr_good_pullup = 1;
inout PAD_A_ESD_H;
output TIE_HI_ESD;
output TIE_LO_ESD;
inout TIE_WEAK_HI_H;
wire tmp1;
pullup (pull1) p1 (tmp1); tranif1 x_pull_1 (TIE_WEAK_HI_H, tmp1, pwr_good_pullup===0 ? 1'bx : 1);
tran p2 (PAD, PAD_A_ESD_H);
buf p4 (TIE_HI_ESD, vddio);
buf p5 (TIE_LO_ESD, vssio);
wire tmp;
pullup (pull1) p3 (tmp); tranif0 x_pull (PULLUP_H, tmp, pwr_good_pullup===0 || ^DISABLE_PULLUP_H===1'bx ? 1'bx : DISABLE_PULLUP_H);
parameter MAX_WARNING_COUNT = 100;
`ifdef SKY130_FD_IO_TOP_XRES4V2_DISABLE_DELAY
parameter MIN_DELAY = 0;
parameter MAX_DELAY = 0;
`else
parameter MIN_DELAY = 50;
parameter MAX_DELAY = 600;
`endif
integer min_delay, max_delay;
initial begin
min_delay = MIN_DELAY;
max_delay = MAX_DELAY;
end
`ifdef SKY130_FD_IO_TOP_XRES4V2_DISABLE_ENABLE_VDDIO_CHANGE_X
parameter DISABLE_ENABLE_VDDIO_CHANGE_X = 1;
`else
parameter DISABLE_ENABLE_VDDIO_CHANGE_X = 0;
`endif
integer disable_enable_vddio_change_x = DISABLE_ENABLE_VDDIO_CHANGE_X;
reg notifier_enable_h;
specify
`ifdef SKY130_FD_IO_TOP_XRES4V2_DISABLE_DELAY
specparam DELAY = 0;
`else
specparam DELAY = 50;
`endif
if (INP_SEL_H==0 & ENABLE_H==0 & ENABLE_VDDIO==0 & EN_VDDIO_SIG_H==1) (PAD => XRES_H_N) = (0:0:0 , 0:0:0);
if (INP_SEL_H==0 & ENABLE_H==1 & ENABLE_VDDIO==1 & EN_VDDIO_SIG_H==1) (PAD => XRES_H_N) = (0:0:0 , 0:0:0);
if (INP_SEL_H==0 & ENABLE_H==1 & ENABLE_VDDIO==1 & EN_VDDIO_SIG_H==0) (PAD => XRES_H_N) = (0:0:0 , 0:0:0);
if (INP_SEL_H==0 & ENABLE_H==0 & ENABLE_VDDIO==0 & EN_VDDIO_SIG_H==0) (PAD => XRES_H_N) = (0:0:0 , 0:0:0);
if (INP_SEL_H==1) (FILT_IN_H => XRES_H_N) = (0:0:0 , 0:0:0);
specparam tsetup = 0;
specparam thold = 5;
endspecify
reg corrupt_enable;
always @(notifier_enable_h)
begin
corrupt_enable <= 1'bx;
end
initial
begin
corrupt_enable = 1'b0;
end
always @(PAD or ENABLE_H or EN_VDDIO_SIG_H or ENABLE_VDDIO or INP_SEL_H or FILT_IN_H or pwr_good_xres_tmp or DISABLE_PULLUP_H or PULLUP_H or TIE_WEAK_HI_H)
begin
corrupt_enable <= 1'b0;
end
assign mode_vcchib = ENABLE_H && !EN_VDDIO_SIG_H;
wire xres_tmp = (pwr_good_xres_tmp===0 || ^PAD===1'bx || (mode_vcchib===1'bx ) ||(mode_vcchib!==1'b0 && ^ENABLE_VDDIO===1'bx) || (corrupt_enable===1'bx) ||
(mode_vcchib===1'b1 && ENABLE_VDDIO===0 && (disable_enable_vddio_change_x===0)))
? 1'bx : PAD;
wire x_on_xres_h_n = (pwr_good_xres_h_n===0
|| ^INP_SEL_H===1'bx
|| INP_SEL_H===1 && ^FILT_IN_H===1'bx
|| INP_SEL_H===0 && xres_tmp===1'bx);
assign #1 XRES_H_N = x_on_xres_h_n===1 ? 1'bx : (INP_SEL_H===1 ? FILT_IN_H : xres_tmp);
realtime t_pad_current_transition,t_pad_prev_transition;
realtime t_filt_in_h_current_transition,t_filt_in_h_prev_transition;
realtime pad_pulse_width, filt_in_h_pulse_width;
always @(PAD)
begin
if (^PAD !== 1'bx)
begin
t_pad_prev_transition = t_pad_current_transition;
t_pad_current_transition = $realtime;
pad_pulse_width = t_pad_current_transition - t_pad_prev_transition;
end
else
begin
t_pad_prev_transition = 0;
t_pad_current_transition = 0;
pad_pulse_width = 0;
end
end
always @(FILT_IN_H)
begin
if (^FILT_IN_H !== 1'bx)
begin
t_filt_in_h_prev_transition = t_filt_in_h_current_transition;
t_filt_in_h_current_transition = $realtime;
filt_in_h_pulse_width = t_filt_in_h_current_transition - t_filt_in_h_prev_transition;
end
else
begin
t_filt_in_h_prev_transition = 0;
t_filt_in_h_current_transition = 0;
filt_in_h_pulse_width = 0;
end
end
reg dis_err_msgs;
integer msg_count_pad, msg_count_filt_in_h;
event event_errflag_pad_pulse_width, event_errflag_filt_in_h_pulse_width;
initial
begin
dis_err_msgs = 1'b1;
msg_count_pad = 0; msg_count_filt_in_h = 0;
`ifdef SKY130_FD_IO_TOP_XRES4V2_DIS_ERR_MSGS
`else
#1;
dis_err_msgs = 1'b0;
`endif
end
always @(pad_pulse_width)
begin
if (!dis_err_msgs)
begin
if (INP_SEL_H===0 && (pad_pulse_width > min_delay) && (pad_pulse_width < max_delay))
begin
msg_count_pad = msg_count_pad + 1;
->event_errflag_pad_pulse_width;
if (msg_count_pad <= MAX_WARNING_COUNT)
begin
$display(" ===WARNING=== sky130_fd_io__top_xres4v2 : Width of Input pulse for PAD input (= %3.2f ns) is found to be in \the range: %3d ns - %3d ns. In this range, the delay and pulse suppression of the input pulse are PVT dependent. : \%m",pad_pulse_width,min_delay,max_delay,$stime);
end
else
if (msg_count_pad == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_xres4v2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
always @(filt_in_h_pulse_width)
begin
if (!dis_err_msgs)
begin
if (INP_SEL_H===1 && (filt_in_h_pulse_width > min_delay) && (filt_in_h_pulse_width < max_delay))
begin
msg_count_filt_in_h = msg_count_filt_in_h + 1;
->event_errflag_filt_in_h_pulse_width;
if (msg_count_filt_in_h <= MAX_WARNING_COUNT)
begin
$display(" ===WARNING=== sky130_fd_io__top_xres4v2 : Width of Input pulse for FILT_IN_H input (= %3.2f ns) is found to be in \the range: %3d ns - %3d ns. In this range, the delay and pulse suppression of the input pulse are PVT dependent. : \%m",filt_in_h_pulse_width,min_delay,max_delay,$stime);
end
else
if (msg_count_filt_in_h == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_xres4v2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
endmodule
|
#include <bits/stdc++.h> const double pi = acos(-1.0); const double eps = 1e-9; using namespace std; int k, n1, n2, n3, t1, t2, t3; void solve() { cin >> k >> n1 >> n2 >> n3 >> t1 >> t2 >> t3; set<pair<long long, int>> st[3]; for (int i = 1; i <= 1000; i++) { if (i <= n1) { st[0].insert({0, i}); } if (i <= n2) { st[1].insert({0, i}); } if (i <= n3) { st[2].insert({0, i}); } } long long ans = 0; while (k--) { auto beg0 = *st[0].begin(); auto beg1 = *st[1].begin(); auto beg2 = *st[2].begin(); auto last0 = beg0, last1 = beg1, last2 = beg2; st[0].erase(beg0); st[1].erase(beg1); st[2].erase(beg2); beg0.first += t1; beg1.first = max(beg1.first + t2, beg0.first + t2); beg2.first = max(beg2.first + t3, beg1.first + t3); ans = max(ans, beg2.first); beg1.first = beg2.first - t3; beg0.first = beg1.first - t2; assert(last0.first <= beg0.first); assert(last1.first <= beg1.first); assert(last2.first <= beg2.first); st[0].insert(beg0); st[1].insert(beg1); st[2].insert(beg2); } cout << ans << endl; } int main() { ios::sync_with_stdio(NULL), cin.tie(0), cout.tie(0); cout.setf(ios::fixed), cout.precision(7); int step = 1; for (int i = 1; i <= step; i++) { solve(); } } |
#include <bits/stdc++.h> using namespace std; int n, s, T, ans; int ar[101]; bool ok[301]; int dp[301][301]; int res[301][301]; int tmp[301][301]; int ways[24][301][301]; vector<int> v; int main() { scanf( %d%d , &n, &T); for (int i = 1; i <= n; i++) { scanf( %d , &ar[i]); ok[ar[i]] = true; } for (int i = 1; i < 301; i++) if (ok[i]) v.push_back(i); s = v.size(); for (int h = 0; h < s; h++) { int head = v[h]; dp[head][head] = 1; for (int i = 1; i <= n; i++) { int mx = dp[head][ar[i]]; for (int j = 1; j <= ar[i]; j++) if (dp[head][j]) mx = max(mx, dp[head][j] + 1); dp[head][ar[i]] = mx; } } for (int i = 1; i < 301; i++) for (int j = 1; j < 301; j++) ways[0][i][j] = max(dp[i][j] - 1, 0); for (int kd = 1; (1 << kd) <= T; kd++) for (int i = 0; i < s; i++) for (int j = i; j < s; j++) for (int k = i; k <= j; k++) { int vi = v[i]; int vj = v[j]; int vk = v[k]; ways[kd][vi][vj] = max(ways[kd][vi][vj], ways[kd - 1][vi][vk] + ways[kd - 1][vk][vj]); } for (int kd = 0; (1 << kd) <= T; kd++) if (T & (1 << kd)) { memset(tmp, 0, sizeof(tmp)); for (int i = 0; i < s; i++) for (int j = i; j < s; j++) for (int k = i; k <= j; k++) { int vi = v[i]; int vj = v[j]; int vk = v[k]; tmp[vi][vj] = max(tmp[vi][vj], res[vi][vk] + ways[kd][vk][vj]); } for (int i = 0; i < s; i++) for (int j = 0; j < s; j++) res[v[i]][v[j]] = tmp[v[i]][v[j]]; } for (int i = 0; i < s; i++) for (int j = 0; j < s; j++) ans = max(ans, res[v[i]][v[j]]); printf( %d n , ans); return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Tue May 30 22:29:11 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_ov7670_vga_1_0/system_ov7670_vga_1_0_stub.v
// Design : system_ov7670_vga_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "ov7670_vga,Vivado 2016.4" *)
module system_ov7670_vga_1_0(clk_x2, active, data, rgb)
/* synthesis syn_black_box black_box_pad_pin="clk_x2,active,data[7:0],rgb[15:0]" */;
input clk_x2;
input active;
input [7:0]data;
output [15:0]rgb;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FAHCIN_BEHAVIORAL_V
`define SKY130_FD_SC_LP__FAHCIN_BEHAVIORAL_V
/**
* fahcin: Full adder, inverted carry in.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__fahcin (
COUT,
SUM ,
A ,
B ,
CIN
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire ci ;
wire xor0_out_SUM;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT;
// Name Output Other arguments
not not0 (ci , CIN );
xor xor0 (xor0_out_SUM, A, B, ci );
buf buf0 (SUM , xor0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, ci );
and and2 (b_ci , B, ci );
or or0 (or0_out_COUT, a_b, a_ci, b_ci);
buf buf1 (COUT , or0_out_COUT );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__FAHCIN_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; vector<int> g[26]; int visited[26]; int p[26], deg[26]; string ans; bool fail; void dfs(int u) { visited[u] = 2; ans += (char)(u + a ); for (int i = 0; i < (int)g[u].size(); i++) { int v = g[u][i]; if (visited[v] == 0) { p[v] = u; dfs(v); } else if (visited[v] == 2) { if (p[u] != v) { fail = true; } } } visited[u] = 1; } int main() { ios::sync_with_stdio(false); cin.tie(0); int tt; cin >> tt; while (tt--) { string s; cin >> s; int n = s.size(); ans = ; for (int i = 0; i < 26; i++) { g[i].clear(); visited[i] = 0; p[i] = -1; deg[i] = 0; } map<pair<int, int>, int> m; for (int i = 1; i < n; i++) { int v = (s[i] - a ); int u = (s[i - 1] - a ); int uu = min(u, v); int vv = max(u, v); if (m[make_pair(uu, vv)] == 0) { g[u].push_back(v); g[v].push_back(u); deg[u]++; deg[v]++; m[make_pair(uu, vv)]++; } } fail = false; for (int i = 0; i < 26; i++) { if (deg[i] > 2) { fail = true; } if (!visited[i] && deg[i] < 2) { dfs(i); } } if (fail || ans.size() < 26) { cout << NO << n ; } else { cout << YES << n ; cout << ans << n ; } } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A41O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__A41O_BEHAVIORAL_PP_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__a41o (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2, A3, A4 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A41O_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKBUF_4_V
`define SKY130_FD_SC_LP__CLKBUF_4_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog wrapper for clkbuf with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__clkbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkbuf_4 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkbuf_4 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__clkbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKBUF_4_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKINV_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__CLKINV_FUNCTIONAL_PP_V
/**
* clkinv: Clock tree inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__clkinv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKINV_FUNCTIONAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21A_FUNCTIONAL_V
`define SKY130_FD_SC_LP__O21A_FUNCTIONAL_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__o21a (
X ,
A1,
A2,
B1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X, or0_out, B1 );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21A_FUNCTIONAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02:03:00 09/16/2014
// Design Name:
// Module Name: segClkDevider
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module segClkDevider(
input clk,
input rst,
output reg clk_div
);
localparam constantNumber = 10000;
reg [31:0] count;
always @ (posedge(clk), posedge(rst))
begin
if (rst == 1'b1)
count <= 32'b0;
else if (count == constantNumber - 1)
count <= 32'b0;
else
count <= count + 1;
end
always @ (posedge(clk), posedge(rst))
begin
if (rst == 1'b1)
clk_div <= 1'b0;
else if (count == constantNumber - 1)
clk_div <= ~clk_div;
else
clk_div <= clk_div;
end
endmodule |
#include <bits/stdc++.h> void build_comp(int v, int comp_num, std::vector<int> &cur_comp, std::vector<int> &rev_comps, const std::vector<std::vector<int>> &g) { cur_comp.push_back(v); rev_comps[v] = comp_num; for (int to : g[v]) { if (rev_comps[to] == -1) { build_comp(to, comp_num, cur_comp, rev_comps, g); } } } void solve() { int n; std::cin >> n; std::vector<std::vector<std::pair<int, int>>> positions(n); const auto reader = [n, &positions](int num) { for (int i = 0; i < n; ++i) { int a; std::cin >> a; positions[a - 1].emplace_back(num, i); } }; const auto neg = [n](int val) { return (val + n) % (2 * n); }; reader(0); reader(1); for (int i = 0; i < n; ++i) { if (positions[i].size() != 2) { std::cout << -1 << n ; return; } } std::vector<std::vector<int>> g(2 * n); for (int i = 0; i < n; ++i) { auto pa = positions[i][0]; auto pb = positions[i][1]; if (pa.second == pb.second) { continue; } int a = pa.second; int b = pb.second; if (pa.first == pb.first) { a = neg(a); } g[a].push_back(b); g[b].push_back(a); g[neg(a)].push_back(neg(b)); g[neg(b)].push_back(neg(a)); } int comp_num = 0; std::vector<std::vector<int>> comps; std::vector<int> rev_comps(2 * n, -1); for (int i = 0; i < 2 * n; ++i) { if (rev_comps[i] == -1) { std::vector<int> cur_comp; build_comp(i, comp_num++, cur_comp, rev_comps, g); comps.emplace_back(std::move(cur_comp)); } } for (int i = 0; i < n; ++i) { if (rev_comps[i] == rev_comps[neg(i)]) { std::cout << -1 << n ; return; } } std::set<int> res; std::set<size_t> skipping_comps; for (size_t i = 0; i < comps.size(); ++i) { if (skipping_comps.find(i) != skipping_comps.end()) { continue; } const auto &line = comps[i]; int positive = 0; for (int v : line) { if (v < n) { ++positive; } } int negative = line.size() - positive; if (positive <= negative) { for (int v : line) { if (v < n) { res.insert(v); } } } if (positive == negative) { skipping_comps.insert(rev_comps[neg(line[0])]); } } std::cout << res.size() << n ; for (int v : res) { std::cout << v + 1 << ; } std::cout << n ; } int main() { int t; std::cin >> t; for (; t; --t) { solve(); } return 0; } |
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
`timescale 1ns / 1ps
module bd_350b_ila_lib_0 (
clk,
trig_out,
trig_out_ack,
trig_in,
trig_in_ack,
probe0,
probe1,
probe2,
probe3,
probe4,
probe5,
probe6,
probe7,
probe8,
probe9,
probe10,
probe11,
probe12,
probe13,
probe14,
probe15,
probe16,
probe17,
probe18,
probe19,
probe20,
probe21,
probe22,
probe23,
probe24,
probe25,
probe26,
probe27,
probe28,
probe29,
probe30,
probe31,
probe32,
probe33,
probe34,
probe35,
probe36,
probe37,
probe38,
probe39,
probe40,
probe41,
probe42,
probe43,
probe44,
probe45,
probe46,
probe47,
probe48,
probe49,
probe50
);
input clk;
output trig_out;
input trig_out_ack;
input trig_in;
output trig_in_ack;
input [1 : 0] probe0;
input [8 : 0] probe1;
input [1 : 0] probe2;
input [8 : 0] probe3;
input [1 : 0] probe4;
input [1 : 0] probe5;
input [1 : 0] probe6;
input [31 : 0] probe7;
input [1 : 0] probe8;
input [31 : 0] probe9;
input [3 : 0] probe10;
input [1 : 0] probe11;
input [1 : 0] probe12;
input [1 : 0] probe13;
input [1 : 0] probe14;
input [1 : 0] probe15;
input [7 : 0] probe16;
input [1 : 0] probe17;
input [15 : 0] probe18;
input [1 : 0] probe19;
input [3 : 0] probe20;
input [11 : 0] probe21;
input [7 : 0] probe22;
input [0 : 0] probe23;
input [2 : 0] probe24;
input [3 : 0] probe25;
input [2 : 0] probe26;
input [1 : 0] probe27;
input [15 : 0] probe28;
input [1 : 0] probe29;
input [3 : 0] probe30;
input [11 : 0] probe31;
input [7 : 0] probe32;
input [0 : 0] probe33;
input [2 : 0] probe34;
input [3 : 0] probe35;
input [2 : 0] probe36;
input [1 : 0] probe37;
input [11 : 0] probe38;
input [1 : 0] probe39;
input [1 : 0] probe40;
input [31 : 0] probe41;
input [11 : 0] probe42;
input [1 : 0] probe43;
input [31 : 0] probe44;
input [3 : 0] probe45;
input [1 : 0] probe46;
input [2 : 0] probe47;
input [1 : 0] probe48;
input [1 : 0] probe49;
input [2 : 0] probe50;
endmodule
|
#include <bits/stdc++.h> using namespace std; char s[200010]; int T, N; int Solve() { N = strlen(s + 1); int Ans = 0, Len = 1; while ((1 << (Len)) <= N) ++Len; for (register int i = 1; i <= N; ++i) { if (s[i] == 0 ) continue; int p = i, num = 0; while (p > 1 && s[p - 1] == 0 ) --p; for (register int j = i; j <= min(i + Len - 1, N); ++j) { num = (num << 1) + s[j] - 0 ; if (num > N) break; int L = j - i + 1, R = j - p + 1; if (L <= num && num <= R) ++Ans; } } return Ans; } int main() { scanf( %d , &T); while (T--) { scanf( %s , s + 1); printf( %d n , Solve()); } return 0; } |
/*
* Copyright (c) 2001 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* Catch problems with non-zero lsb values in l-value expressions.
*/
module main;
reg [7:1] a = 6'b111111;
reg [7:1] b = 6'b000010;
integer q;
reg [7:1] x;
reg PCLK = 1;
always @(posedge PCLK)
for (q=1; q<=7; q=q+1)
x[q] <= #1 a[q] & b[q];
always #5 PCLK = !PCLK;
initial begin
// $dumpfile("dump.vcd");
// $dumpvars(0, main);
#50 $display("done: x=%b", x);
if (x !== 6'b000010)
$display("FAILED -- x = %b", x);
else
$display("PASSED");
$finish;
end
endmodule // main
|
/*******************************************************************
Company: UNSW
Original Author: Lingkan Gong
Project Name: XDRS
Create Date: 19/09/2010
Design Name: pipeline_sync
*******************************************************************/
`timescale 1ns/1ns
module pipeline_sync
#(parameter
C_SYNCCNT = 32
)
(
input clk ,
input rstn ,
//-- to/from core----
input rdy ,
output start_sync ,
//-- to/from reconfiguration controller----
input rc_reqn,
output rc_ackn
);
localparam [1:0]
IDLE = 4'd0,
SYNC = 4'd1;
reg [7:0] state_c, state_n;
reg [31:0] synccnt;
wire is_end_sync;
//-------------------------------------------------------------------
// Main FSM
//-------------------------------------------------------------------
always @(posedge clk or negedge rstn) begin
if (~rstn)
state_c <= IDLE;
else
state_c <= state_n;
end
always @(*) begin
case (state_c)
IDLE: begin state_n = (~rc_reqn)? SYNC: IDLE; end
SYNC: begin state_n = (is_end_sync)? IDLE: SYNC; end
default: begin state_n = IDLE; end
endcase
end
assign start_sync = (state_c==SYNC);
//-------------------------------------------------------------------
// Pipeline_Sync Counter
//-------------------------------------------------------------------
always @(posedge clk or negedge rstn) begin
if (~rstn) begin
synccnt <= 32'h0;
end else begin
if (is_end_sync) begin
synccnt <= 32'h0;
end else if (state_c==SYNC) begin
if (rdy)
synccnt <= synccnt+1'b1;
end
end
end
assign is_end_sync = ((synccnt+1'b1 == C_SYNCCNT) & rdy);
assign rc_ackn = ~((synccnt+1'b1 == C_SYNCCNT) & rdy); // ~is_end_sync
endmodule
|
#include <bits/stdc++.h> using namespace std; void c_p_c() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); } long long me(long long x, long long y, long long p) { long long res = 1; x = x % p; if (x == 0) return 0; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res; } int main() { c_p_c(); long long t; cin >> t; while (t--) { long long n; cin >> n; long long a[n]; long long b[n]; for (long long i = 0; i < n; i++) cin >> a[i]; for (long long i = 0; i < n; i++) cin >> b[i]; long long c[n]; multiset<long long> s; long long l = 0; vector<long long> v; long long g = 0; long long temp = 0; long long g1 = 0; for (long long i = 0; i < n; i++) { c[i] = b[i] - a[i]; if (c[i] == 0 && g1 == 1) { break; } if (c[i] < 0) { cout << NO n ; l = 1; break; } if (c[i] != 0 && (temp == c[i] || g == 0)) { a[i] = a[i] + c[i]; temp = c[i]; g = 1; g1 = 1; } } if (l == 1) { continue; } long long flg = 0; for (long long i = 0; i < n; i++) { if (a[i] != b[i]) { flg = 1; break; } } if (flg == 1) { cout << NO n ; } else { cout << YES n ; } } return 0; } |
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_axis_fifo_64;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [63:0] input_axis_tdata = 0;
reg [7:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
reg output_axis_tready = 0;
// Outputs
wire input_axis_tready;
wire [63:0] output_axis_tdata;
wire [7:0] output_axis_tkeep;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser);
// dump file
$dumpfile("test_axis_fifo_64.lxt");
$dumpvars(0, test_axis_fifo_64);
end
axis_fifo_64 #(
.ADDR_WIDTH(2),
.DATA_WIDTH(64)
)
UUT (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata(input_axis_tdata),
.input_axis_tkeep(input_axis_tkeep),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tuser(input_axis_tuser),
// AXI output
.output_axis_tdata(output_axis_tdata),
.output_axis_tkeep(output_axis_tkeep),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser)
);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_ifu_par16.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: sparc_ifu_par16
// Description:
// Generates 34b parity. Odd number of ones => out = 1
*/
module sparc_ifu_par16 (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
input [15:0] in;
output out;
assign out = (^in[15:0]);
endmodule // sparc_ifu_par16
|
#include <bits/stdc++.h> using namespace std; int n, k; int a[100005]; int b[100005]; bool ok(long long x) { long long s = k; for (int i = 0; i < n; i++) { if (x * a[i] >= b[i]) { s -= (x * a[i] - b[i]); } if (s < 0) { return false; } } return true; } int main() { cin >> n >> k; for (int i = 0; i < n; i++) { cin >> a[i]; } for (int j = 0; j < n; j++) { cin >> b[j]; } if (n == 1) { cout << (b[0] + k) / a[0] << endl; } else { int sum = 0; long long l = 0, r = 0xffffffff; long long mid; while (l <= r) { mid = (l + r) >> 1; if (ok(mid)) { l = mid + 1; sum = mid; } else { r = mid - 1; } } cout << sum << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long ans = 0; int n, m, x, y; int main() { while (scanf( %d%d%d%d , &n, &x, &m, &y) == 4) { if (x > y) { n ^= m ^= n ^= m; x ^= y ^= x ^= y; } ans = n + 1; int l, r; for (int i = 1; i <= m; ++i) { l = y - i; r = y + i; if (l <= x - n || l >= x + n) ++ans; else { r = min(r - 1, n + x); if (l >= x) ans += ((r - l) << 1); else ans += ((r - x - (x - l)) << 1) + 1; } } cout << ans << endl; } return 0; } |
// test case taken from amber23 Verilog code
module a23_barrel_shift_fpga_rotate(i_in, direction, shift_amount, rot_prod);
input [31:0] i_in;
input direction;
input [4:0] shift_amount;
output [31:0] rot_prod;
// Generic rotate. Theoretical cost: 32x5 4-to-1 LUTs.
// Practically a bit higher due to high fanout of "direction".
generate
genvar i, j;
for (i = 0; i < 5; i = i + 1)
begin : netgen
wire [31:0] in;
reg [31:0] out;
for (j = 0; j < 32; j = j + 1)
begin : net
always @*
out[j] = in[j] & (~shift_amount[i] ^ direction) |
in[wrap(j, i)] & (shift_amount[i] ^ direction);
end
end
// Order is reverted with respect to volatile shift_amount[0]
assign netgen[4].in = i_in;
for (i = 1; i < 5; i = i + 1)
begin : router
assign netgen[i-1].in = netgen[i].out;
end
endgenerate
// Aliasing
assign rot_prod = netgen[0].out;
function [4:0] wrap;
input integer pos;
input integer level;
integer out;
begin
out = pos - (1 << level);
wrap = out[4:0];
end
endfunction
endmodule
|
//#############################################################################
//# Function: IO Buffer #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_iobuf #(parameter N = 1, // BUS WIDTH
parameter TYPE = "BEHAVIORAL" // BEHAVIORAL, HARD
)
(
//POWER
inout vdd, // core supply
inout vddio,// io supply
inout vss, // ground
//CONTROLS
input enpullup, //enable pullup
input enpulldown, //enable pulldown
input slewlimit, //slew limiter
input [3:0] drivestrength, //drive strength
//DATA
input [N-1:0] ie, //input enable
input [N-1:0] oe, //output enable
output [N-1:0] out,//output to core
input [N-1:0] in, //input from core
//BIDIRECTIONAL PAD
inout [N-1:0] pad
);
genvar i;
//TODO: Model power signals
for (i = 0; i < N; i = i + 1) begin : gen_buf
if(TYPE=="BEHAVIORAL") begin : gen_beh
assign pad[i] = oe[i] ? in[i] : 1'bZ;
assign out[i] = ie[i] ? pad[i] : 1'b0;
end
else begin : gen_custom
end
end
endmodule // oh_iobuf
|
#include <bits/stdc++.h> using namespace std; int32_t main() { int64_t t; cin >> t; vector<int64_t> ans; map<int64_t, int64_t> m; for (int64_t i = 0; i < t; i++) { m[0] = 0; m[1] = 0; m[2] = 0; int64_t n; cin >> n; for (int64_t j = 0; j < n; j++) { int64_t u; cin >> u; m[u % 3]++; } ans.push_back( max(m[0] + min(m[1], m[2]) + (m[1] - min(m[1], m[2])) / 3 + (m[2] - min(m[1], m[2])) / 3, m[0] + m[1] / 3 + m[2] / 3 + min(m[1] % 3, (int64_t)1) * min(m[2] % 3, (int64_t)1))); } for (int64_t a : ans) cout << a << endl; } |
#include <bits/stdc++.h> using namespace std; long long int t, n, m, k; string s; long long int dp[30][30004]; long long int frq[30]; int main() { ios::sync_with_stdio(0); cin.tie(0); long long int i, j, x; cin >> t; while (t--) { cin >> n >> m >> k; cin >> s; long long int ans = 1e10; long long int tot = s.size(); memset(frq, 0, sizeof frq); for (i = 0; i < s.size(); i++) { frq[s[i] - A + 1]++; } for (i = 1; i <= 26; i++) { for (j = 0; j <= 27; j++) { for (k = 0; k <= n; k++) { dp[j][k] = 0; if (k == 0) dp[j][k] = 1; } } for (j = 1; j <= 26; j++) { for (k = 1; k <= n; k++) { dp[j][k] = dp[j - 1][k]; if (i != j && k - frq[j] >= 0 && dp[j - 1][k - frq[j]] == 1) { dp[j][k] = 1; } } } long long int rem = tot - frq[i]; for (k = 0; k <= n; k++) { if (dp[26][k]) { long long int cn = n - k; long long int cm = m - rem + k; if (cm <= 0) { if (frq[i] >= cn) ans = min(ans, 0LL); } else { if (cn == 0) { if (frq[i] >= cm) ans = min(ans, 0LL); } else { if (frq[i] >= cn + cm) { ans = min(ans, cn * cm); } } } } } } cout << ans << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; string i2s(int x) { stringstream ss; ss << x; return ss.str(); } int s2i(string str) { istringstream ss(str); int nro; ss >> nro; return nro; } int n; int NRO5(int nro) { int cnt = 0; while (nro % 5 == 0) { cnt++; nro /= 5; } return cnt; } int main() { int A[500005]; map<int, vector<int> > mapa; map<int, vector<int> >::iterator it; for (int i = 1; i < 500005; i++) { A[i] = A[i - 1] + NRO5(i); mapa[A[i]].push_back(i); } scanf( %d n , &n); if (mapa[n].size() == 0) { putchar( 0 ); putchar( n ); } else { printf( %d n , (int)mapa[n].size()); for (int i = 0; i < mapa[n].size(); i++) { printf( %d%c , mapa[n][i], i == mapa[n].size() - 1 ? 10 : 32); } } return 0; } |
#include <bits/stdc++.h> using namespace std; #pragma comment(linker, /STACK:1024000000,1024000000 ) const int INF = 0x3f3f3f; const long long mod = 1e9 + 7; const int MAXN = 1055; const double eps = 1e-6; const double pi = acos(-1.0); using namespace std; int main() { long long n, t; cin >> n >> t; double x = 1.000000011; double ans = 1.0; for (long long i = t; i; i = i >> 1, x *= x) if (i & 1) ans *= x; printf( %.6f n , ans * n); return 0; } |
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module mult_16x16 (
input wire [15:0] A,
input wire [15:0] B,
output wire [31:0] Z
);
assign Z = A * B;
endmodule
module mult_20x18 (
input wire [19:0] A,
input wire [17:0] B,
output wire [37:0] Z
);
assign Z = A * B;
endmodule
module mult_8x8 (
input wire [ 7:0] A,
input wire [ 7:0] B,
output wire [15:0] Z
);
assign Z = A * B;
endmodule
module mult_10x9 (
input wire [ 9:0] A,
input wire [ 8:0] B,
output wire [18:0] Z
);
assign Z = A * B;
endmodule
module mult_8x8_s (
input wire signed [ 7:0] A,
input wire signed [ 7:0] B,
output wire signed [15:0] Z
);
assign Z = A * B;
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; void err(istream_iterator<string> it) {} template <typename T, typename... Args> void err(istream_iterator<string> it, T a, Args... args) { cerr << *it << = << a << endl; err(++it, args...); } long long powm(long long a, long long b, long long mod) { long long res = 1; while (b) { if (b & 1) res = (res * a) % mod; a = (a * a) % mod; b >>= 1; } return res; } const long long mod = 1e9 + 7; const long long N = 1000005; const long long inf = 1e9; void solve() { int n; cin >> n; deque<long long> dq; long long ans = 0; while (n--) { long long x; cin >> x; if (dq.size() == 0) { dq.push_back(x); continue; } if (dq.size() > 0) ans = max(ans, (dq.back() ^ x)); while (dq.size() > 0 and dq.back() < x) { ans = max(ans, (x ^ dq.back())); dq.pop_back(); } if (dq.size() > 0) ans = max(ans, (dq.back() ^ x)); dq.push_back(x); } long long curr = dq.back(); dq.pop_back(); while (!dq.empty()) { ans = max(ans, (curr ^ dq.back())); curr = dq.back(); dq.pop_back(); } cout << ans << endl; } signed main() { ios_base::sync_with_stdio(false); cin.tie(0), cout.tie(0); cout << fixed << setprecision(15); int tc = 1; while (tc--) { solve(); } return 0; } |
// $Id: c_pseudo_sram_mac.v 1833 2010-03-22 23:18:22Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// register file wrapper that implements SRAM-like timing
module c_pseudo_sram_mac
(clk, reset, write_enable, write_address, write_data, read_enable,
read_address, read_data);
`include "c_functions.v"
`include "c_constants.v"
// number of entries
parameter depth = 8;
// width of each entry
parameter width = 64;
// select implementation variant
parameter regfile_type = `REGFILE_TYPE_FF_2D;
parameter reset_type = `RESET_TYPE_ASYNC;
// width required to swelect an entry
localparam addr_width = clogb(depth);
input clk;
input reset;
// if high, write to entry selected by write_address
input write_enable;
// entry to be written to
input [0:addr_width-1] write_address;
// data to be written
input [0:width-1] write_data;
// if high, enable read for next cycle
input read_enable;
// entry to read out
input [0:addr_width-1] read_address;
// contents of entry selected by read_address
output [0:width-1] read_data;
wire [0:width-1] read_data;
// make read timing behave like SRAM (read address selects entry to be read
// out in next cycle)
wire [0:addr_width-1] read_address_s, read_address_q;
assign read_address_s = read_enable ? read_address : read_address_q;
c_dff
#(.width(addr_width),
.reset_type(reset_type))
read_addrq
(.clk(clk),
.reset(reset),
.d(read_address_s),
.q(read_address_q));
c_regfile
#(.depth(depth),
.width(width),
.regfile_type(regfile_type))
rf
(.clk(clk),
.write_enable(write_enable),
.write_address(write_address),
.write_data(write_data),
.read_address(read_address_q),
.read_data(read_data));
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; const int N = 1e5 + 5; ll f[N]; int n, ans, c; int main() { scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %lld , &f[i]); for (int i = 2; i < n; i++) { if (f[i] == f[i - 1] + f[i - 2]) { c++; ans = max(ans, c + 2); } else { c = 0; } } printf( %d n , (ans == 0 || ans == 1) ? (n == 1 ? 1 : 2) : ans); return 0; } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx2mb_link_ctr.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/***************************************************************************
* pcx2mb_link_cnt.v: A counter to keep track of outstanding transactions
* to one of the five destinations of the PCX request. This
* counter will be instantiated 5 times.
*
* The core has a link credit of 2 transactions. However, it will
* speculatively send a third transaction, assuming that a grant
* will be received in time. If this block is not ready to grant
* the first transaction, then the third one must be dropped,
* because the core will re-send it.
*
* NOTE: Pipeline stages from SPARC point of view are
* PQ Initial Request
* PA Data sent for request.
* PX Grant returned, Request sent to cache
* PX2 Data sent to cache
*
* $Id: pcx2mb_link_ctr.v,v 1.1 2007/06/30 00:23:40 tt147840 Exp $
***************************************************************************/
// Global header file includes
// Local header file includes
`include "ccx2mb.h"
module pcx2mb_link_ctr (
// Outputs
request_mask_pa,
// Inputs
rclk,
reset_l,
pcx_req_pa,
pcx_req_px,
pcx_atom_px,
pcx_grant_px
);
output request_mask_pa;
input rclk;
input reset_l;
input pcx_req_pa;
input pcx_req_px;
input pcx_atom_px;
input pcx_grant_px;
reg [1:0] link_count_pa;
wire request_mask_pa;
wire count_inc;
wire count_dec;
assign count_inc = pcx_req_pa || (pcx_req_px && pcx_atom_px);
assign count_dec = pcx_grant_px;
always @(posedge rclk) begin
if (!reset_l) begin
link_count_pa <= 2'b00;
end
else if (count_inc && count_dec) begin
link_count_pa <= link_count_pa;
end
else if (count_inc && !link_count_pa[1]) begin
link_count_pa <= link_count_pa + 2'b01;
end
else if (count_dec) begin
link_count_pa <= link_count_pa - 2'b01;
end
else begin
link_count_pa <= link_count_pa;
end
end
assign request_mask_pa = link_count_pa[1];
endmodule
|
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V2.0
// Ultra-Embedded.com
// Copyright 2011 - 2013
//
// Email:
//
// License: LGPL
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2013 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Module:
//-----------------------------------------------------------------
module uart
(
// Clock & Reset
clk_i,
rst_i,
// Status
tx_busy_o,
rx_ready_o,
break_o,
// Data
data_i,
wr_i,
data_o,
rd_i,
// UART pins
rxd_i,
txd_o
);
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter [31:0] UART_DIVISOR = 278;
//-----------------------------------------------------------------
// I/O
//-----------------------------------------------------------------
input clk_i /*verilator public*/;
input rst_i /*verilator public*/;
input [7:0] data_i /*verilator public*/;
output [7:0] data_o /*verilator public*/;
input wr_i /*verilator public*/;
input rd_i /*verilator public*/;
output tx_busy_o /*verilator public*/;
output rx_ready_o /*verilator public*/;
output break_o /*verilator public*/;
input rxd_i /*verilator public*/;
output txd_o /*verilator public*/;
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
parameter FULL_BIT = UART_DIVISOR;
parameter HALF_BIT = (FULL_BIT / 2);
// TX Signals
reg [7:0] tx_buf;
reg tx_buf_full;
reg tx_busy;
reg [3:0] tx_bits;
integer tx_count;
reg [7:0] tx_shift_reg;
reg txd_o;
// RX Signals
reg i_rxd;
reg [7:0] data_o;
reg [3:0] rx_bits;
integer rx_count;
reg [7:0] rx_shift_reg;
reg rx_ready_o;
reg break_o;
//-----------------------------------------------------------------
// Re-sync RXD
//-----------------------------------------------------------------
always @ (posedge rst_i or posedge clk_i )
begin
if (rst_i == 1'b1)
i_rxd <= 1'b1;
else
i_rxd <= rxd_i;
end
//-----------------------------------------------------------------
// RX Process
//-----------------------------------------------------------------
always @ (posedge clk_i or posedge rst_i )
begin
if (rst_i == 1'b1)
begin
rx_bits <= 0;
rx_count <= 0;
rx_ready_o <= 1'b0;
rx_shift_reg <= 8'h00;
data_o <= 8'h00;
break_o <= 1'b0;
end
else
begin
// If reading data, reset data ready state
if (rd_i == 1'b1)
rx_ready_o <= 1'b0;
// Rx bit timer
if (rx_count != 0)
rx_count <= (rx_count - 1);
else
begin
//-------------------------------
// Start bit detection
//-------------------------------
if (rx_bits == 0)
begin
break_o <= 1'b0;
// If RXD low, check again in half bit time
if (i_rxd == 1'b0)
begin
rx_count <= HALF_BIT;
rx_bits <= 1;
end
end
//-------------------------------
// Start bit (mid bit time point)
//-------------------------------
else if (rx_bits == 1)
begin
// RXD should still be low at mid point of bit period
if (i_rxd == 1'b0)
begin
rx_count <= FULL_BIT;
rx_bits <= rx_bits + 1'b1;
rx_shift_reg <= 8'h00;
end
// Start bit not still low, reset RX process
else
begin
rx_bits <= 0;
end
end
//-------------------------------
// Stop bit
//-------------------------------
else if (rx_bits == 10)
begin
// RXD should be still high
if (i_rxd == 1'b1)
begin
rx_count <= 0;
rx_bits <= 0;
data_o <= rx_shift_reg;
rx_ready_o <= 1'b1;
end
// Bad Stop bit - wait for a full bit period
// before allowing start bit detection again
else
begin
rx_count <= FULL_BIT;
rx_bits <= 0;
// Interpret this as a break
break_o <= 1'b1;
end
end
//-------------------------------
// Data bits
//-------------------------------
else
begin
// Receive data LSB first
rx_shift_reg[7] <= i_rxd;
rx_shift_reg[6:0]<= rx_shift_reg[7:1];
rx_count <= FULL_BIT;
rx_bits <= rx_bits + 1'b1;
end
end
end
end
//-----------------------------------------------------------------
// TX Process
//-----------------------------------------------------------------
always @ (posedge clk_i or posedge rst_i )
begin
if (rst_i == 1'b1)
begin
tx_count <= 0;
tx_bits <= 0;
tx_busy <= 1'b0;
txd_o <= 1'b1;
tx_shift_reg <= 8'h00;
tx_buf <= 8'h00;
tx_buf_full <= 1'b0;
end
else
begin
// Buffer data to transmit
if (wr_i == 1'b1)
begin
tx_buf <= data_i;
tx_buf_full <= 1'b1;
end
// Tx bit timer
if (tx_count != 0)
tx_count <= (tx_count - 1);
else
begin
//-------------------------------
// Start bit (TXD = L)
//-------------------------------
if (tx_bits == 0)
begin
tx_busy <= 1'b0;
// Data in buffer ready to transmit?
if (tx_buf_full == 1'b1)
begin
tx_shift_reg <= tx_buf;
tx_busy <= 1'b1;
txd_o <= 1'b0;
tx_buf_full <= 1'b0;
tx_bits <= 1;
tx_count <= FULL_BIT;
end
end
//-------------------------------
// Stop bit (TXD = H)
//-------------------------------
else if (tx_bits == 9)
begin
txd_o <= 1'b1;
tx_bits <= 0;
tx_count <= FULL_BIT;
end
//-------------------------------
// Data bits
//-------------------------------
else
begin
// Shift data out LSB first
txd_o <= tx_shift_reg[0];
tx_shift_reg[6:0]<= tx_shift_reg[7:1];
tx_bits <= tx_bits + 1'b1;
tx_count <= FULL_BIT;
end
end
end
end
//-----------------------------------------------------------------
// Combinatorial
//-----------------------------------------------------------------
assign tx_busy_o = (tx_busy | tx_buf_full | wr_i);
endmodule
|
#include <bits/stdc++.h> using namespace std; ifstream fin; ofstream fout; FILE *outt, *inn; const int N = 100009, M = 70; int k, b[M], d[M], k2, y, yy; unsigned long long m, c[M][M], l, r, cur; void find() { for (int i = 0; i <= 64; i++) { for (int j = 0; j <= 64; j++) { if (i == 0) { c[i][j] = 1; continue; } if (i > j) continue; c[i][j] = c[i - 1][j - 1] + c[i][j - 1]; } } } int cnt; bool is; void binary(unsigned long long x) { memset(b, 0, sizeof(b)); is = 0; cnt = 69; while (x > 0) { b[--cnt] = x % 2; x /= 2; } b[0] = cnt; for (int i = b[0] + 1; i <= 68; i++) { if (b[i]) { return; } } is = 1; } unsigned long long solve(unsigned long long x) { cur = 0; binary(2 * x); k2 = k - 1; for (int i = b[0] + 1; i <= 68; i++) { if (b[i] == 1) { y = 68 - i; cur += c[k2][y]; k2--; } if (k2 == 0) { for (int j = i + 1; j <= 68; j++) { if (b[j]) { cur++; break; } } break; } } k2 = 0; for (int i = b[0]; i <= 68; i++) { if (b[i]) k2++; } if (k2 == k) cur++; binary(x + 1); if (!is) { k2 = k - 1; for (int i = b[0] + 1; i <= 68; i++) { if (b[i] == 0) { cur += c[k2 - 1][68 - i]; } if (b[i] == 1) { k2--; } if (k2 == 0) { break; } } k2 = 0; for (int i = b[0]; i <= 68; i++) { if (b[i]) k2++; } if (k2 == k) cur++; } return cur; } int main() { memset(c, 0, sizeof(c)); find(); cin >> m >> k; r = (unsigned long long)1; while (solve(r) < m) { r *= 2; } l = r / 2 + 1; while (l < r) { unsigned long long mid = (l + r) / 2; unsigned long long res = solve(mid); if (res < m) { l = mid + 1; } else if (res > m) { r = mid - 1; } else { cout << mid; return 0; } } cout << l; return 0; } |
#include <bits/stdc++.h> using namespace std; #pragma comment(linker, /STACK:100000000 ) int mod = 1000000007; int mas[1010]; int pow2(int b) { if (b == -1) return 0; int res = 1; for (int i = 1; i <= b; i++) { res <<= 1; res %= mod; } return res; } int GCD(int a, int b) { if (b == 0) return a; else return GCD(b, a % b); } vector<int> v; vector<int> C; int main() { int n, m; scanf( %d %d , &n, &m); for (int i = 0; i < m; i++) scanf( %d , &mas[i]); sort(mas, mas + m); if (mas[0] != 1) v.push_back(mas[0] - 1); if ((n > 1 || m != 1) && mas[m - 1] != n) v.push_back(n - mas[m - 1]); for (int i = 1; i < m; i++) { int a = pow2(mas[i] - mas[i - 1] - 2); if (mas[i] - 1 != mas[i - 1]) v.push_back(mas[i] - mas[i - 1] - 1); a = max(a, 1); C.push_back(a); } sort(v.begin(), v.end()); int S = 0; vector<int> F; for (int i = 0, maxi = (int)(v).size(); i < maxi; i++) S += v[i]; for (int i = 2; i <= S; i++) F.push_back(i); vector<int> VVV; for (int i = 0, maxi = (int)(v).size(); i < maxi; i++) for (int j = 2; j <= v[i]; j++) VVV.push_back(j); for (int i = 0, maxi = (int)(VVV).size(); i < maxi; i++) { for (int j = 0, maxj = (int)(F).size(); j < maxj; j++) { if (VVV[i] == 1) break; int G = GCD(F[j], VVV[i]); VVV[i] /= G; F[j] /= G; } } long long ans = 1; for (int i = 0, maxi = (int)(F).size(); i < maxi; i++) ans *= (long long)F[i], ans %= (long long)mod; for (int i = 0, maxi = (int)(C).size(); i < maxi; i++) ans *= (long long)C[i], ans %= (long long)mod; cout << ans << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYGATE4SD2_TB_V
`define SKY130_FD_SC_HD__DLYGATE4SD2_TB_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dlygate4sd2.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hd__dlygate4sd2 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYGATE4SD2_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O32AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__O32AI_BEHAVIORAL_PP_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__o32ai (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A3, A1, A2 );
nor nor1 (nor1_out , B1, B2 );
or or0 (or0_out_Y , nor1_out, nor0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O32AI_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const int N = 2e5 + 4; int main() { string s; int n; scanf( %d , &n); cin >> s; int pre[n], suf[n], minm = 0, bal = 0; for (int i = 0; i < n; i++) { if (s[i] == ( ) { pre[i] = 1; suf[i] = -1; } else { pre[i] = -1; suf[i] = 1; } bal += pre[i]; minm = min(minm, bal); } if (bal == 0) { if (minm > -2) { printf( Yes ); return 0; } } printf( No ); } |
`timescale 1ns / 1ps
module ControlUnit(
input [5:0] op,
input zero,
output reg extend,
// PC
output reg [1:0] PCSrcSelector,
output reg PCWriteOp,
// ALU
output reg ALUSrcASelector,
output reg ALUSrcBSelector,
output reg [2:0] ALUOp,
// Instruction Memory
output reg IMReadWriteOp,
// Data Memory
output reg DMWriteOp,
output reg DMReadOp,
// Register File
output reg RFWriteRegSelector,
output reg RFWriteDataSelector,
output reg RFWriteOp
);
initial begin
extend = 0;
PCSrcSelector = 2'B00;
PCWriteOp = 0;
ALUSrcASelector = 0;
ALUSrcBSelector = 0;
ALUOp = 3'B000;
IMReadWriteOp = 1;
DMWriteOp = 0;
DMReadOp = 0;
RFWriteRegSelector = 0;
RFWriteDataSelector = 0;
RFWriteOp = 0;
end
always@(op or zero) begin
case (op)
// add rd, rs, rt
6'B000000: begin
// extend = 0;
PCSrcSelector = 2'B00;
PCWriteOp = 1;
ALUSrcASelector = 0;
ALUSrcBSelector = 0;
ALUOp = 3'B000;
IMReadWriteOp = 1;
DMWriteOp = 0;
DMReadOp = 0;
RFWriteRegSelector = 1;
RFWriteDataSelector = 0;
RFWriteOp = 1;
end
// addi rt, rs, imm
6'B000001: begin
extend = 1;
PCSrcSelector = 2'B00;
PCWriteOp = 1;
ALUSrcASelector = 0;
ALUSrcBSelector = 1;
ALUOp = 3'B000;
IMReadWriteOp = 1;
DMWriteOp = 0;
DMReadOp = 0;
RFWriteRegSelector = 0;
RFWriteDataSelector = 0;
RFWriteOp = 1;
end
// sub rd, rs, rt
6'B000010: begin
// extend = 0;
PCSrcSelector = 2'B00;
PCWriteOp = 1;
ALUSrcASelector = 0;
ALUSrcBSelector = 0;
ALUOp = 3'B001;
IMReadWriteOp = 1;
DMWriteOp = 0;
DMReadOp = 0;
RFWriteRegSelector = 1;
RFWriteDataSelector = 0;
RFWriteOp = 1;
end
// ori rt, rs, imm
6'B010000: begin
extend = 0;
PCSrcSelector = 2'B00;
PCWriteOp = 1;
ALUSrcASelector = 0;
ALUSrcBSelector = 1;
ALUOp = 3'B011;
IMReadWriteOp = 1;
DMWriteOp = 0;
DMReadOp = 0;
RFWriteRegSelector = 0;
RFWriteDataSelector = 0;
RFWriteOp = 1;
end
// and rd, rs, rt
6'B010001: begin
// extend = 0;
PCSrcSelector = 2'B00;
PCWriteOp = 1;
ALUSrcASelector = 0;
ALUSrcBSelector = 0;
ALUOp = 3'B100;
IMReadWriteOp = 1;
DMWriteOp = 0;
DMReadOp = 0;
RFWriteRegSelector = 1;
RFWriteDataSelector = 0;
RFWriteOp = 1;
end
// or rd, rs, rt
6'B010010: begin
// extend = 0;
PCSrcSelector = 2'B00;
PCWriteOp = 1;
ALUSrcASelector = 0;
ALUSrcBSelector = 0;
ALUOp = 3'B011;
IMReadWriteOp = 1;
DMWriteOp = 0;
DMReadOp = 0;
RFWriteRegSelector = 1;
RFWriteDataSelector = 0;
RFWriteOp = 1;
end
// sll rd, rt, sa
6'B011000: begin
// extend = 0;
PCSrcSelector = 2'B00;
PCWriteOp = 1;
ALUSrcASelector = 1;
ALUSrcBSelector = 0;
ALUOp = 3'B010;
IMReadWriteOp = 1;
DMWriteOp = 0;
DMReadOp = 0;
RFWriteRegSelector = 1;
RFWriteDataSelector = 0;
RFWriteOp = 1;
end
// slti rt, rs, imm
6'B011011: begin
extend = 1;
PCSrcSelector = 2'B00;
PCWriteOp = 1;
ALUSrcASelector = 0;
ALUSrcBSelector = 1;
ALUOp = 3'B110;
IMReadWriteOp = 1;
DMWriteOp = 0;
DMReadOp = 0;
RFWriteRegSelector = 0;
RFWriteDataSelector = 0;
RFWriteOp = 1;
end
// sw rt, imm(rs)
6'B100110: begin
extend = 1;
PCSrcSelector = 2'B00;
PCWriteOp = 1;
ALUSrcASelector = 0;
ALUSrcBSelector = 1;
ALUOp = 3'B000;
IMReadWriteOp = 1;
DMWriteOp = 1;
DMReadOp = 0;
RFWriteRegSelector = 1;
// RFWriteDataSelector = 0;
RFWriteOp = 0;
end
// lw rt, imm(rs)
6'B100111: begin
extend = 1;
PCSrcSelector = 2'B00;
PCWriteOp = 1;
ALUSrcASelector = 0;
ALUSrcBSelector = 1;
ALUOp = 3'B000;
IMReadWriteOp = 1;
DMWriteOp = 0;
DMReadOp = 1;
RFWriteRegSelector = 0;
RFWriteDataSelector = 1;
RFWriteOp = 1;
end
// beq rs, rt, imm
6'B110000: begin
extend = 1;
PCSrcSelector = (zero == 0 ? 2'B00 : 2'B01);
PCWriteOp = 1;
ALUSrcASelector = 0;
ALUSrcBSelector = 0;
ALUOp = 3'B001;
IMReadWriteOp = 1;
DMWriteOp = 0;
DMReadOp = 0;
RFWriteRegSelector = 1;
// RFWriteDataSelector = 0;
RFWriteOp = 0;
end
// bne rs, rt, imm
6'B110001: begin
extend = 1;
PCSrcSelector = (zero == 1 ? 2'B00 : 2'B01);
PCWriteOp = 1;
ALUSrcASelector = 0;
ALUSrcBSelector = 0;
ALUOp = 3'B001;
IMReadWriteOp = 1;
DMWriteOp = 0;
DMReadOp = 0;
RFWriteRegSelector = 1;
// RFWriteDataSelector = 0;
RFWriteOp = 0;
end
// j addr
6'B111000: begin
// extend = 0;
PCSrcSelector = 2'B10;
PCWriteOp = 1;
// ALUSrcASelector = 0;
// ALUSrcBSelector = 0;
// ALUOp = 3'B000;
IMReadWriteOp = 1;
DMWriteOp = 0;
DMReadOp = 0;
// RFWriteRegSelector = 1;
// RFWriteDataSelector = 0;
RFWriteOp = 0;
end
// halt
6'B111111: begin
// extend = 0;
// PCSrcSelector = 2'B00;
PCWriteOp = 0;
// ALUSrcASelector = 0;
// ALUSrcBSelector = 0;
// ALUOp = 3'B000;
IMReadWriteOp = 1;
DMWriteOp = 0;
DMReadOp = 0;
// RFWriteRegSelector = 1;
// RFWriteDataSelector = 0;
RFWriteOp = 0;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int Read() { int x = 0, f = 1; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) f = -1; ch = getchar(); } while (isdigit(ch)) { x = (x << 3) + (x << 1) + ch - 0 ; ch = getchar(); } return x * f; } int n, m, q, a[200005], b[200005], f[200005], g[200005], h[200005], minn[800005], rev[200005]; vector<int> pos[200005], pos2[200005]; void build(int o, int l, int r) { if (l == r) { minn[o] = (g[l] == -1) ? 1E9 : g[l]; return; } int mid = (l + r) >> 1; build(o << 1, l, mid); build(o << 1 | 1, mid + 1, r); minn[o] = min(minn[o << 1], minn[o << 1 | 1]); } int query(int o, int l, int r, int nl, int nr) { if (nl <= l && r <= nr) return minn[o]; int mid = (l + r) >> 1, ans = 1E9; if (nl <= mid) ans = min(ans, query(o << 1, l, mid, nl, nr)); if (mid < nr) ans = min(ans, query(o << 1 | 1, mid + 1, r, nl, nr)); return ans; } signed main() { n = Read(), m = Read(), q = Read(); for (int i = 1; i <= n; i++) a[i] = Read(), rev[a[i]] = i; for (int i = 1; i <= m; i++) b[i] = Read(), pos[b[i]].push_back(i); memset(f, -1, sizeof(f)); memset(g, -1, sizeof(g)); memset(h, -1, sizeof(h)); for (int i = n; i >= 1; i--) { if (i == n) { for (int j = 0; j < pos[a[i]].size(); j++) f[pos[a[i]][j]] = pos[a[i]][j]; continue; } for (int j = 0; j < pos[a[i]].size(); j++) { vector<int>::iterator it = lower_bound(pos[a[i + 1]].begin(), pos[a[i + 1]].end(), pos[a[i]][j]); if (it == pos[a[i + 1]].end()) continue; f[pos[a[i]][j]] = f[*it]; } } for (int i = 1; i <= n; i++) { if (i == 1) { for (int j = 0; j < pos[a[i]].size(); j++) h[pos[a[i]][j]] = pos[a[i]][j]; continue; } for (int j = 0; j < pos[a[i]].size(); j++) { vector<int>::iterator it = lower_bound(pos[a[i - 1]].begin(), pos[a[i - 1]].end(), pos[a[i]][j]); if (it == pos[a[i - 1]].begin()) continue; --it; h[pos[a[i]][j]] = h[*it]; } } for (int i = 1; i <= n; i++) { for (int j = 0; j < pos[a[i]].size(); j++) pos2[a[i]].push_back(h[pos[a[i]][j]]); } for (int i = 1; i <= m; i++) { int ff = rev[b[i]]; if (ff == 1) { g[i] = f[i]; continue; } if (f[i] == -1) continue; vector<int>::iterator it = lower_bound(pos2[a[ff - 1]].begin(), pos2[a[ff - 1]].end(), f[i]); if (it == pos2[a[ff - 1]].end()) continue; int Pos = it - pos2[a[ff - 1]].begin(); g[i] = pos[a[ff - 1]][Pos]; } build(1, 1, m); for (int i = 1; i <= q; i++) { int l = Read(), r = Read(); int mpos = query(1, 1, m, l, r); if (mpos <= r) putchar( 1 ); else putchar( 0 ); } return 0; } |
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1); const double EPS = 1e-9; long long dis(pair<long long, long long> a, pair<long long, long long> b) { return (a.first - b.first) * (a.first - b.first) + (a.second - b.second) * (a.second - b.second); } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long T, v; pair<long long, long long> C; cin >> C.first >> C.second >> v >> T; long long R = 1.00 * v * T; long long n; cin >> n; vector<pair<double, long long>> cut; pair<long long, long long> center; long long radi; for (long long i = 0; i < n; i++) { cin >> center.first >> center.second >> radi; double distance = dis(center, C); if (distance < radi * radi + EPS) { cout << 1.00000 ; return 0; } if (sqrt(distance) - EPS > 1.00 * radi + 1.00 * R) continue; double angletocenter = atan2(center.second - C.second, center.first - C.first); if (angletocenter < 0) angletocenter += 2 * PI; double tangent_length = sqrt(distance - 1.0 * radi * radi); double diverge_angle; if (tangent_length < R + EPS) { diverge_angle = asin(radi / sqrt(distance)); } else { diverge_angle = acos((distance + 1.00 * R * R - 1.0 * radi * radi) / (2 * sqrt(distance) * 1.00 * R)); } double left = angletocenter - diverge_angle; double right = angletocenter + diverge_angle; if (left < 0) { cut.push_back({left + 2 * PI, 1}); cut.push_back({2 * PI, -1}); cut.push_back({0.00, 1}); cut.push_back({right, -1}); } else if (right > 2 * PI) { cut.push_back({left, 1}); cut.push_back({2 * PI, -1}); cut.push_back({right - 2 * PI, -1}); cut.push_back({0.00, 1}); } else cut.push_back({left, 1}), cut.push_back({right, -1}); } double ans = 0.00; long long count = 0; double last = 0; sort(cut.begin(), cut.end()); for (auto& x : cut) { if (count > 0) ans += (x.first - last); last = x.first; count += (x.second); } cout << fixed << setprecision(6) << (ans / (2 * PI)); } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module AESL_automem_b (
clk,
rst,
ce0,
we0,
address0,
din0,
dout0,
ce1,
we1,
address1,
din1,
dout1,
ready,
done
);
//------------------------Parameter----------------------
localparam
TV_IN = "../tv/cdatafile/c.matrix_mult.autotvin_b.dat",
TV_OUT = "../tv/rtldatafile/rtl.matrix_mult.autotvout_b.dat";
//------------------------Local signal-------------------
parameter DATA_WIDTH = 32'd 8;
parameter ADDR_WIDTH = 32'd 5;
parameter DEPTH = 32'd 25;
parameter DLY = 0.1;
// Input and Output
input clk;
input rst;
input ce0, ce1;
input we0, we1;
input [ADDR_WIDTH - 1 : 0] address0, address1;
input [DATA_WIDTH - 1 : 0] din0, din1;
output reg [DATA_WIDTH - 1 : 0] dout0, dout1;
input ready;
input done;
// Inner signals
reg [DATA_WIDTH - 1 : 0] mem [0 : DEPTH - 1];
initial begin : initialize_mem
integer i;
for (i = 0; i < DEPTH; i = i + 1) begin
mem[i] = 0;
end
end
reg writed_flag;
event write_process_done;
//------------------------Task and function--------------
task read_token;
input integer fp;
output reg [127 :0] token;
integer ret;
begin
token = "";
ret = 0;
ret = $fscanf(fp,"%s",token);
end
endtask
//------------------------Read array-------------------
// Read data form file to array
initial begin : read_file_process
integer fp;
integer err;
integer ret;
reg [127 : 0] token;
reg [ 8*5 : 1] str;
reg [ DATA_WIDTH - 1 : 0 ] mem_tmp;
integer transaction_idx;
integer i;
transaction_idx = 0;
wait(rst === 0);
@(write_process_done);
fp = $fopen(TV_IN,"r");
if(fp == 0) begin // Failed to open file
$display("Failed to open file \"%s\"!", TV_IN);
$finish;
end
read_token(fp, token);
if (token != "[[[runtime]]]") begin // Illegal format
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
read_token(fp, token);
while (token != "[[[/runtime]]]") begin
if (token != "[[transaction]]") begin
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
read_token(fp, token); // skip transaction number
while(ready == 0) begin
@(write_process_done);
end
for(i = 0; i < DEPTH; i = i + 1) begin
read_token(fp, token);
ret = $sscanf(token, "0x%x", mem_tmp);
mem[i] = mem_tmp;
if (ret != 1) begin
$display("Failed to parse token!");
$finish;
end
end
@(write_process_done);
read_token(fp, token);
if(token != "[[/transaction]]") begin
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
read_token(fp, token);
transaction_idx = transaction_idx + 1;
end
$fclose(fp);
end
// Read data from array to RTL
always @ (posedge clk or rst) begin
if(rst === 1) begin
dout0 <= 0;
end
else begin
if((we0 == 0) && (ce0 == 1) && (ce1 == 1) && (we1 == 1) && (address0 == address1))
dout0 <= #DLY din1;
else if(ce0 == 1)
dout0 <= #DLY mem[address0];
else ;
end
end
always @ (posedge clk or rst) begin
if(rst === 1) begin
dout1 <= 0;
end
else begin
if((we0 == 1) && (ce0 == 1) && (ce1 == 1) && (we1 == 0) && (address0 == address1))
dout1 <= #DLY din0;
else if(ce1 == 1)
dout1 <= #DLY mem[address1];
else ;
end
end
//------------------------Write array-------------------
// Write data from RTL to array
always @ (posedge clk) begin
if((we0 == 1) && (ce0 == 1) && (ce1 == 1) && (we1 == 1) && (address0 == address1))
mem[address0] <= #DLY din1;
else if ((we0 == 1) && (ce0 == 1))
mem[address0] <= #DLY din0;
end
always @ (posedge clk) begin
if((ce1 == 1) && (we1 == 1))
mem[address1] <= #DLY din1;
end
// Write data from array to file
initial begin : write_file_proc
integer fp;
integer transaction_num;
reg [ 8*5 : 1] str;
integer i;
transaction_num = 0;
writed_flag = 1;
wait(rst === 0);
@(negedge clk);
while(1) begin
while(done == 0) begin
-> write_process_done;
@(negedge clk);
end
fp = $fopen(TV_OUT, "a");
if(fp == 0) begin // Failed to open file
$display("Failed to open file \"%s\"!", TV_OUT);
$finish;
end
$fdisplay(fp, "[[transaction]] %d", transaction_num);
for (i = 0; i < DEPTH; i = i + 1) begin
$fdisplay(fp,"0x%x",mem[i]);
end
$fdisplay(fp, "[[/transaction]]");
transaction_num = transaction_num + 1;
$fclose(fp);
writed_flag = 1;
-> write_process_done;
@(negedge clk);
end
end
//------------------------conflict check-------------------
always @ (posedge clk) begin
if ((we0 == 1) && (ce0 == 1) && (ce1 == 1) && (we1 == 1) && (address0 == address1))
$display($time,"WARNING:write conflict----port0 and port1 write to the same address:%h at the same clock. Port1 has the high priority.",address0);
end
always @ (posedge clk) begin
if ((we0 == 1) && (ce0 == 1) && (ce1 == 1) && (we1 == 0) && (address0 == address1))
$display($time,"NOTE:read & write conflict----port0 write and port1 read to the same address:%h at the same clock. Write first Mode.",address0);
end
always @ (posedge clk) begin
if ((we0 == 0) && (ce0 == 1) && (ce1 == 1) && (we1 == 1) && (address0 == address1))
$display($time,"NOTE:read & write conflict----port0 read and port1 write to the same address:%h at the same clock. Write first Mode.",address0);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> a, b, e; char s[5]; long long ans; int c; int main() { int n, f; scanf( %d , &n); while (n--) { scanf( %s %d , &s, &f); if (s[0] == 0 && s[1] == 1 ) a.push_back(f); else if (s[0] == 1 && s[1] == 0 ) b.push_back(f); else if (s[0] == 0 && s[1] == 0 ) e.push_back(f); else { c++; ans += f; } } int temp = c + 2 * min((int)a.size(), (int)b.size()); c += min((int)a.size(), (int)b.size()); if (!a.empty()) sort(a.rbegin(), a.rend()); if (!b.empty()) sort(b.rbegin(), b.rend()); for (int i = 0; i < min((int)a.size(), (int)b.size()); ++i) { ans += a[i]; ans += b[i]; } if (a.size() > b.size()) { for (int i = min(a.size(), b.size()); i < a.size(); ++i) e.push_back(a[i]); } else if (b.size() > a.size()) { for (int i = min(a.size(), b.size()); i < b.size(); ++i) e.push_back(b[i]); } if (!e.empty()) sort(e.rbegin(), e.rend()); for (int i = 0; i < e.size(); ++i) { if (((temp + 2) / 2) <= c) { ans += e[i]; temp++; } } printf( %lld , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 121; int a[N], b[N], last[N], kol, ans, v, u, i, n; inline void add(int v, int u) { a[++kol] = u; b[kol] = last[v]; last[v] = kol; } void dfs(int v, int p, int len) { if (len == 2) { ++ans; return; } int x = last[v]; while (x) { if (a[x] != p) dfs(a[x], v, len + 1); x = b[x]; } } int main() { cin >> n; for (i = 1; i < n; ++i) { cin >> v >> u; add(v, u); add(u, v); } for (i = 1; i <= n; ++i) dfs(i, 0, 0); cout << ans / 2 << endl; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND3_1_V
`define SKY130_FD_SC_LS__NAND3_1_V
/**
* nand3: 3-input NAND.
*
* Verilog wrapper for nand3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nand3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand3_1 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand3_1 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND3_1_V
|
#include <bits/stdc++.h> using namespace std; int k, i; int main() { cin >> k; for (i = 1; i <= k; i <<= 1) { } cout << 2 3 << endl; cout << i * 2 - 1 << << k << 0 << endl; cout << i << << i * 2 - 1 << << k << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKINVLP_BLACKBOX_V
`define SKY130_FD_SC_LP__CLKINVLP_BLACKBOX_V
/**
* clkinvlp: Lower power Clock tree inverter.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__clkinvlp (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKINVLP_BLACKBOX_V
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module ac97 #(
parameter csr_addr = 4'h0
) (
input sys_clk,
input sys_rst,
input ac97_clk,
input ac97_rst_n,
/* Codec interface */
input ac97_sin,
output ac97_sout,
output ac97_sync,
/* Control interface */
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output [31:0] csr_do,
/* Interrupts */
output crrequest_irq,
output crreply_irq,
output dmar_irq,
output dmaw_irq,
/* DMA */
output [31:0] wbm_adr_o,
output [2:0] wbm_cti_o,
output wbm_we_o,
output wbm_cyc_o,
output wbm_stb_o,
input wbm_ack_i,
input [31:0] wbm_dat_i,
output [31:0] wbm_dat_o
);
wire up_stb;
wire up_ack;
wire up_sync;
wire up_sdata;
wire down_ready;
wire down_stb;
wire down_sync;
wire down_sdata;
ac97_transceiver transceiver(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.ac97_clk(ac97_clk),
.ac97_rst_n(ac97_rst_n),
.ac97_sin(ac97_sin),
.ac97_sout(ac97_sout),
.ac97_sync(ac97_sync),
.up_stb(up_stb),
.up_ack(up_ack),
.up_sync(up_sync),
.up_data(up_sdata),
.down_ready(down_ready),
.down_stb(down_stb),
.down_sync(down_sync),
.down_data(down_sdata)
);
wire down_en;
wire down_next_frame;
wire down_addr_valid;
wire [19:0] down_addr;
wire down_data_valid;
wire [19:0] down_data;
wire down_pcmleft_valid;
wire [19:0] down_pcmleft;
wire down_pcmright_valid;
wire [19:0] down_pcmright;
ac97_framer framer(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
/* to transceiver */
.down_ready(down_ready),
.down_stb(down_stb),
.down_sync(down_sync),
.down_data(down_sdata),
/* frame data */
.en(down_en),
.next_frame(down_next_frame),
.addr_valid(down_addr_valid),
.addr(down_addr),
.data_valid(down_data_valid),
.data(down_data),
.pcmleft_valid(down_pcmleft_valid),
.pcmleft(down_pcmleft),
.pcmright_valid(down_pcmright_valid),
.pcmright(down_pcmright)
);
wire up_en;
wire up_next_frame;
wire up_frame_valid;
wire up_addr_valid;
wire [19:0] up_addr;
wire up_data_valid;
wire [19:0] up_data;
wire up_pcmleft_valid;
wire [19:0] up_pcmleft;
wire up_pcmright_valid;
wire [19:0] up_pcmright;
ac97_deframer deframer(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.up_stb(up_stb),
.up_ack(up_ack),
.up_sync(up_sync),
.up_data(up_sdata),
.en(up_en),
.next_frame(up_next_frame),
.frame_valid(up_frame_valid),
.addr_valid(up_addr_valid),
.addr(up_addr),
.data_valid(up_data_valid),
.data(up_data),
.pcmleft_valid(up_pcmleft_valid),
.pcmleft(up_pcmleft),
.pcmright_valid(up_pcmright_valid),
.pcmright(up_pcmright)
);
wire dmar_en;
wire [29:0] dmar_addr;
wire [15:0] dmar_remaining;
wire dmar_next;
wire dmaw_en;
wire [29:0] dmaw_addr;
wire [15:0] dmaw_remaining;
wire dmaw_next;
ac97_ctlif #(
.csr_addr(csr_addr)
) ctlif (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.csr_a(csr_a),
.csr_we(csr_we),
.csr_di(csr_di),
.csr_do(csr_do),
.crrequest_irq(crrequest_irq),
.crreply_irq(crreply_irq),
.dmar_irq(dmar_irq),
.dmaw_irq(dmaw_irq),
.down_en(down_en),
.down_next_frame(down_next_frame),
.down_addr_valid(down_addr_valid),
.down_addr(down_addr),
.down_data_valid(down_data_valid),
.down_data(down_data),
.up_en(up_en),
.up_next_frame(up_next_frame),
.up_frame_valid(up_frame_valid),
.up_addr_valid(up_addr_valid),
.up_addr(up_addr),
.up_data_valid(up_data_valid),
.up_data(up_data),
.dmar_en(dmar_en),
.dmar_addr(dmar_addr),
.dmar_remaining(dmar_remaining),
.dmar_next(dmar_next),
.dmaw_en(dmaw_en),
.dmaw_addr(dmaw_addr),
.dmaw_remaining(dmaw_remaining),
.dmaw_next(dmaw_next)
);
ac97_dma dma(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.wbm_adr_o(wbm_adr_o),
.wbm_cti_o(wbm_cti_o),
.wbm_we_o(wbm_we_o),
.wbm_cyc_o(wbm_cyc_o),
.wbm_stb_o(wbm_stb_o),
.wbm_ack_i(wbm_ack_i),
.wbm_dat_i(wbm_dat_i),
.wbm_dat_o(wbm_dat_o),
.down_en(down_en),
.down_next_frame(down_next_frame),
.down_pcmleft_valid(down_pcmleft_valid),
.down_pcmleft(down_pcmleft),
.down_pcmright_valid(down_pcmright_valid),
.down_pcmright(down_pcmright),
.up_en(up_en),
.up_next_frame(up_next_frame),
.up_frame_valid(up_frame_valid),
.up_pcmleft_valid(up_pcmleft_valid),
.up_pcmleft(up_pcmleft),
.up_pcmright_valid(up_pcmright_valid),
.up_pcmright(up_pcmright),
.dmar_en(dmar_en),
.dmar_addr(dmar_addr),
.dmar_remaining(dmar_remaining),
.dmar_next(dmar_next),
.dmaw_en(dmaw_en),
.dmaw_addr(dmaw_addr),
.dmaw_remaining(dmaw_remaining),
.dmaw_next(dmaw_next)
);
endmodule
|
class foo();
int my_field;
endclass // foo
class temp;
extern function test();
extern function test2();
function foo();
foo = 1;
endfunction // foo
extern function test3();
reg [31:0] b;
endclass // temp
class short extends temp;
logic a;
endclass
`define vmm_channel(A) A+A
module foo;
reg a;
reg [1:0] b;
initial begin
b = `vmm_channel(a);
end // initial begin
endmodule // foo
class A;
extern function int e1();
extern function int e2(int src,int dst);
extern static function int f1();
extern static function int f2(int src,int dst);
extern static function int f3(int src,int dst);
extern static function chandle f10(int src);
extern static function automatic int f11(int mcid);
extern function automatic int f13(int mcid);
static function int s1();
int i = 0;
endfunction
static function int s2();
int i = 0;
endfunction
function int f1();
int i = 0;
endfunction
function int f2();
int i = 0;
endfunction
endclass
|
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1.0); double fRand(double fMin, double fMax) { double f = (double)rand() / RAND_MAX; return fMin + f * (fMax - fMin); } template <class T> T min(T a, T b, T c) { return min(a, min(b, c)); } template <class T> T max(T a, T b, T c) { return max(a, max(b, c)); } long long power(long long x, int n) { if (n == 0) return 1; if (n & 1) return (x * power(x, n - 1)) % 1000000007; long long p = power(x, n / 2); return (p * p) % 1000000007; } int n, a[1000005]; long long fact[1000005], invFact[1000005]; long long C(long long n, long long k) { return ((fact[n] * invFact[k] % 1000000007) * invFact[n - k]) % 1000000007; } int main() { scanf( %d , &n); for (int u = (1); u <= (n); ++u) scanf( %d , &a[u]); fact[0] = invFact[0] = 1; for (int i = (1); i <= (1000005 - 1); ++i) fact[i] = (fact[i - 1] * i) % 1000000007; invFact[1000005 - 1] = power(fact[1000005 - 1], 1000000007 - 2); for (int i = (1000005 - 2); i >= (1); --i) invFact[i] = (invFact[i + 1] * (i + 1)) % 1000000007; sort(a + 1, a + n + 1); int j = n, ans = 0; for (int i = (n); i >= (1); --i) { while (j > 0 && a[j] >= a[i]) --j; if (a[i] != a[n]) { int k = n - j - 1; long long x = ((C(n, k + 1) * fact[k]) % 1000000007 * fact[n - k - 1]) % 1000000007; ans = (ans + a[i] * x) % 1000000007; } } printf( %d , ans); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFXBP_SYMBOL_V
`define SKY130_FD_SC_HD__SDFXBP_SYMBOL_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__sdfxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFXBP_SYMBOL_V
|
/* { ###################### # Author # # Gary # # 2021 # ###################### */ #include<bits/stdc++.h> #define rb(a,b,c) for(int a=b;a<=c;++a) #define rl(a,b,c) for(int a=b;a>=c;--a) #define LL long long #define IT iterator #define PB push_back #define II(a,b) make_pair(a,b) #define FIR first #define SEC second #define FREO freopen( check.out , w ,stdout) #define rep(a,b) for(int a=0;a<b;++a) #define SRAND mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()) #define random(a) rng()%a #define ALL(a) a.begin(),a.end() #define POB pop_back #define ff fflush(stdout) #define fastio ios::sync_with_stdio(false) #define check_min(a,b) a=min(a,b) #define check_max(a,b) a=max(a,b) using namespace std; //inline int read(){ // int x=0; // char ch=getchar(); // while(ch< 0 ||ch> 9 ){ // ch=getchar(); // } // while(ch>= 0 &&ch<= 9 ){ // x=(x<<1)+(x<<3)+(ch^48); // ch=getchar(); // } // return x; //} const int INF=0x3f3f3f3f; typedef pair<int,int> mp; /*} */ const int MAXN=1e5+233; vector<int> gra[MAXN]; vector<int> tree[MAXN]; int n,m; int vis[MAXN]; int num[MAXN]; bool leaf[MAXN]; int g[MAXN],f[MAXN][2],h[MAXN]; void dfs(int now,int pre){ for(auto it:gra[now]){ if(it!=pre){ if(vis[it]){ if(vis[it]<vis[now]){ num[it]--; num[now]++; } } else{ vis[it]=vis[now]+1; dfs(it,now); } } } } void gao(int now,int pre){ vis[now]=1; for(auto it:gra[now]) if(it!=pre){ if(!vis[it]){ gao(it,now); num[now]+=num[it]; // cout<<now<< <<it<< <<num[now]<<endl; } } if(!num[now]&&pre){ tree[pre].PB(now); tree[now].PB(pre); } } vector<mp> rest; bool cmp(int A,int B){ return f[A][1]-f[A][0]<f[B][1]-f[B][0]; } void calc(int now,int pre){ vis[now]=1; vector<int> sons; f[now][0]=0; bool all_leaf=true; for(auto it:gra[now]) if(it!=pre) calc(it,now),sons.PB(it),f[now][0]+=f[it][1],all_leaf&=leaf[it]; if((sons.size()&1)&&all_leaf) f[now][0]=INF; else f[now][0]+=(sons.size()+1)>>1; int sum=0; for(auto it:sons) sum+=f[it][0]; sort(ALL(sons),cmp); f[now][1]=INF; if(sons.size()==0){ f[now][1]=0; g[now]=now; h[now]=0; leaf[now]=true; } rb(i,1,sons.size()){ sum+=f[sons[i-1]][1]-f[sons[i-1]][0]; if(i>=sons.size()-1); else continue; // cout<< # <<now<< <<sum<< <<f[sons[i-1]][1]<< <<f[sons[i-1]][0]<<endl; if(i&1){ if(sum+i/2<f[now][1]){ f[now][1]=sum+i/2; g[now]=g[sons[0]]; h[now]=i; } } else{ if(leaf[sons[0]]) continue; if(sum+i/2<f[now][1]){ g[now]=g[sons[1]]; f[now][1]=sum+i/2; h[now]=i; } } } // cout<<now<< : <<f[now][0]<< <<f[now][1]<<endl; } void gao(int now,int ty,int pre){ vector<int> sons; for(auto it:gra[now]) if(it!=pre) sons.PB(it); if(ty==0){ int notleaf=-1; rep(i,sons.size()){ int now=i,nex=i+1; if((sons.size()&1)&¬leaf==-1&&!leaf[sons[now]]){ notleaf=sons[now]; now++; nex++; } if((sons.size()&1)&¬leaf==-1&&!leaf[sons[nex]]){ notleaf=sons[nex]; nex++; } if(nex>=sons.size()) break; rest.PB(II(g[sons[now]],g[sons[nex]])); i=nex; } if(notleaf!=-1){ rest.PB(II(g[notleaf],now)); } for(auto it:sons) gao(it,1,now);return; } if(sons.empty()) return; sort(ALL(sons),cmp); if((h[now])&1){ rb(i,1,h[now]-1){ rest.PB(II(g[sons[i]],g[sons[i+1]])); ++i; } } else{ rb(i,2,h[now]-1){ rest.PB(II(g[sons[i]],g[sons[i+1]])); ++i; } rest.PB(II(g[sons[0]],now)); } rb(i,1,h[now]) gao(sons[i-1],1,now); rb(i,h[now]+1,sons.size()) gao(sons[i-1],0,now); } void solve(){ rest.clear(); rb(i,1,n) gra[i].clear(),leaf[i]=false; rb(i,1,n) tree[i].clear(); rb(i,1,n) vis[i]=0; rb(i,1,n) num[i]=0; rb(i,1,m){ int si; scanf( %d ,&si); int pre=-1; rb(j,1,si){ int ai; scanf( %d ,&ai); if(pre!=-1) gra[pre].PB(ai),gra[ai].PB(pre); pre=ai; } } vis[1]=1; dfs(1,0); rb(i,1,n) vis[i]=0; gao(1,0); rb(i,1,n) vis[i]=0; rb(i,1,n) gra[i]=tree[i]; rb(i,1,n) if(!vis[i]){ calc(i,0); int ret=f[i][0],z=0; int sum=0; for(auto it:gra[i]){ sum+=f[it][1]; } for(auto it:gra[i]){ if(sum-f[it][1]+f[it][0]+gra[i].size()/2<ret){ ret=sum-f[it][1]+f[it][0]+gra[i].size()/2; z=it; } } if(z==0) gao(i,0,0); else{ gao(z,0,i); for(auto it:gra[i]) if(it!=z) gao(it,1,i); int pre=-1; for(auto it:gra[i]){ if(it!=z){ if(pre!=-1) rest.PB(II(g[pre],g[it])),pre=-1; else{ pre=it; } } } if(pre!=-1) rest.PB(II(g[pre],i)); } } printf( %d n ,int(rest.size())); for(auto it:rest){ printf( %d %d n ,it.FIR,it.SEC); } } int main(){ while(true){ scanf( %d%d ,&n,&m); if(!n&&!m){ break; } solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; struct event { int x[3], id; event() { x[0] = x[1] = x[2] = id = 0; } event(int xx, int yy, int zz, int idd) { x[0] = xx; x[1] = yy; x[2] = zz; id = idd; } }; int vc = 0; bool operator<(const event &a, const event &b) { if (a.x[vc] == b.x[vc]) return a.id < b.id; return a.x[vc] < b.x[vc]; } int ans[100005], ans_id[100005]; event G[3][200005]; void cdq(int L, int R, int now) { if (L >= R) return; vc = now; if (now == 2) { int last = -1, last_id = -1; for (int i = L; i <= R; ++i) { if (G[now][i].id > 0) { if (last_id != -1) { int &tmp = ans[G[now][i].id]; if (tmp == -1 || tmp < last) { tmp = last; ans_id[G[now][i].id] = last_id; } } } else { last = G[now][i].x[2]; last_id = -G[now][i].id; } } return; } int mid = (L + R) / 2, cnt = 0; cdq(L, mid, now); for (int i = L; i <= mid; ++i) if (G[now][i].id < 0) G[now + 1][++cnt] = G[now][i]; for (int i = mid + 1; i <= R; ++i) if (G[now][i].id > 0) G[now + 1][++cnt] = G[now][i]; vc = now + 1; sort(G[now + 1] + 1, G[now + 1] + cnt + 1); cdq(1, cnt, now + 1); cdq(mid + 1, R, now); } int main() { int n, m, i, j, k, l, cnt = 0; scanf( %d%d , &n, &m); for (i = 1; i <= n; ++i) { int x, y, z; scanf( %d%d%d , &x, &y, &z); G[0][++cnt] = event(x, -y, -z, -i); } for (i = 1; i <= m; ++i) { int x, y, z; scanf( %d%d%d , &x, &y, &z); G[0][++cnt] = event(x, -y, -z, i); } memset(ans, -1, sizeof(ans)); memset(ans_id, -1, sizeof(ans)); vc = 0; sort(G[0] + 1, G[0] + 1 + cnt); cdq(1, cnt, 0); for (i = 1; i <= m; ++i) printf( %d%c , ans_id[i], n [i == m]); } |
#include <bits/stdc++.h> using namespace std; using ll = long long; using vi = vector<int>; using pi = pair<int, int>; template <class T> bool ckmin(T& a, const T& b) { return b < a ? a = b, 1 : 0; } template <class T> bool ckmax(T& a, const T& b) { return b > a ? a = b, 1 : 0; } void setIO(string name = ) { cin.tie(0)->sync_with_stdio(0); if (int((name).size())) { freopen((name + .in ).c_str(), r , stdin); freopen((name + .out ).c_str(), w , stdout); } } const string yes = YES n , no = NO n ; const int MOD = 1e9 + 7; const int MX = 2e2 + 10; const ll INF = 1e18; const int dx[4] = {1, 0, -1, 0}, dy[4] = {0, 1, 0, -1}; const char dc[4] = { D , R , U , L }; string S; int K, A, B; bool dp[MX][MX]; vi ans; int main() { setIO(); cin >> K >> A >> B >> S; dp[0][0] = true; for (int i = 1; i <= K; ++i) for (int k = 1; k < MX; ++k) for (int j = A; j <= B; ++j) if (k - j >= 0) dp[i][k] |= dp[i - 1][k - j]; if (dp[K][int((S).size())] == false) return cout << No solution , 0; int num = K, sub = int((S).size()); ans.push_back(sub); while (num && sub) { for (int i = A; i <= B; ++i) { if (sub - i >= 0 && dp[num - 1][sub - i]) { --num; ans.push_back(sub - i); sub -= i; break; } } } reverse(begin(ans), end(ans)); for (int i = 0; i < int((ans).size()) - 1; ++i) { for (int j = ans[i]; j < ans[i + 1]; ++j) { cout << S[j]; } cout << n ; } return 0; } |
// `define DEBUG
module mixer #(
parameter NUM_CH_IN = 8, // must be multiple of NUM_CH_OUT
parameter NUM_CH_IN_LOG2 = 3,
parameter NUM_CH_OUT = 2,
parameter NUM_CH_OUT_LOG2 = 1,
parameter VOL_WIDTH = 32
)(
input wire clk, // 49.152Mhz
input wire rst,
input wire [(NUM_CH_IN-1):0] rst_ch,
output wire [(NUM_CH_IN-1):0] pop_o, // optional: ack_i accepted any time
input wire [(NUM_CH_IN-1):0] ack_i,
input wire [(NUM_CH_IN*24-1):0] data_i,
input wire [(NUM_CH_IN*VOL_WIDTH-1):0] vol_i,
input wire [(NUM_CH_OUT-1):0] pop_i,
output wire [23:0] data_o,
output wire [(NUM_CH_OUT-1):0] ack_o);
parameter MULT_LATENCY = 6;
// Input ringbuf
wire [23:0] buffered_data [(NUM_CH_IN-1):0];
genvar igi;
generate
for (igi = 0; igi < NUM_CH_IN; igi = igi + 1) begin:gi
ringbuf #(.LEN(4), .LEN_LOG2(2)) rb(
.clk(clk), .rst(rst | rst_ch[igi]),
.data_i(data_i[(igi*24) +: 24]), .we_i(ack_i[igi]),
.pop_i(pop_o[igi]), .offset_i(0), .data_o(buffered_data[igi]));
end
endgenerate
// Sequencer
// OUTPUT:
parameter TIMESLICE = NUM_CH_IN/NUM_CH_OUT + MULT_LATENCY + 1 + 1; // saturate 1clk, sum 1clk
parameter TIMESLICE_LOG2 = NUM_CH_IN_LOG2-NUM_CH_OUT_LOG2 + 4; // assumes MULT_LATENCY + 1 + 1 < 16
reg [(NUM_CH_IN_LOG2-1):0] processing_in_ch_ff;
reg [(NUM_CH_OUT_LOG2-1):0] processing_out_ch_ff;
reg [(TIMESLICE_LOG2-1):0] timeslice_counter;
wire end_of_cycle = (timeslice_counter == TIMESLICE-1) ? 1'b1 : 1'b0;
always @(posedge clk) begin
if (rst) begin
processing_in_ch_ff <= 0;
processing_out_ch_ff <= 0;
timeslice_counter <= 0;
end else if (end_of_cycle) begin
timeslice_counter <= 0;
if (processing_out_ch_ff == NUM_CH_OUT-1) begin
processing_in_ch_ff <= 0;
processing_out_ch_ff <= 0;
end else begin
processing_in_ch_ff <= processing_out_ch_ff + 1;
processing_out_ch_ff <= processing_out_ch_ff + 1;
end
end else begin
processing_in_ch_ff <= processing_in_ch_ff + NUM_CH_OUT;
timeslice_counter <= timeslice_counter + 1;
end
end
// Cycle validity checker
reg cycle_valid_ff;
// - pop_i latch
reg [(NUM_CH_OUT-1):0] ack_pop_ff;
wire [(NUM_CH_OUT-1):0] pop_i_latched;
genvar igo;
generate
for (igo = 0; igo < NUM_CH_OUT; igo = igo + 1) begin:go
pop_latch pop_latch(
.clk(clk), .rst(rst),
.pop_i(pop_i[igo]),
.ack_pop_i(ack_pop_ff[igo]), .pop_latched_o(pop_i_latched[igo]));
end
endgenerate
// - cycle validity check
always @(posedge clk) begin
ack_pop_ff <= 0;
if (rst) begin
cycle_valid_ff <= 1'b0;
end else if (timeslice_counter == 0) begin
ack_pop_ff <= 1 << processing_out_ch_ff;
end else if (timeslice_counter == 1) begin
cycle_valid_ff <= pop_i_latched[processing_out_ch_ff];
end
end
// Supply mpcand
// OUTPUT:
wire [23:0] mpcand = buffered_data[processing_in_ch_ff];
// Supply scale
wire [(VOL_WIDTH-1):0] scale = 32'h01_000000; //vol_i[(processing_in_ch_ff*VOL_WIDTH) +: VOL_WIDTH];
// Multiplier
// OUTPUT:
wire [31:0] mprod;
mpemu_scale mp(
.clk(clk),
.mpcand_i(mpcand), .scale_i(scale),
.mprod_o(mprod));
// Satulated product
reg [23:0] saturated_mprod_ff;
always @(posedge clk) begin
if (mprod[31] == 1'b0) begin
// sum +
if (mprod[30:23] == 8'b0000_0000)
saturated_mprod_ff <= {1'b0, mprod[22:0]};
else
saturated_mprod_ff <= 24'h7f_ffff; // overflow
end else begin
// sum -
if (mprod[30:23] == 8'b1111_1111)
saturated_mprod_ff <= {1'b1, mprod[22:0]};
else
saturated_mprod_ff <= 24'h80_0000; // underflow
end
end
// - drop first MULT_LATENCY + 1 saturated products
reg [(MULT_LATENCY+1-1):0] kill_result_ff;
always @(posedge clk) begin
if (end_of_cycle)
kill_result_ff <= 0;
else
kill_result_ff <= {1'b1, kill_result_ff[(MULT_LATENCY+1-1):1]};
end
wire product_valid = kill_result_ff[0];
// Adder
reg [23:0] sum_ff; // FIXME: this should be >24bit
function [23:0] saturated_add(
input [23:0] a,
input [23:0] b);
reg [24:0] aext;
reg [24:0] bext;
reg [24:0] sumext;
begin
aext = {a[23], a};
bext = {b[23], b};
sumext = $signed(aext) + $signed(bext);
case (sumext[24:23])
2'b00, 2'b11: // sum is in expressible range
saturated_add = sumext[23:0];
2'b01: // overflow
saturated_add = 24'h7f_ffff;
2'b10: // underflow
saturated_add = 24'h80_0000;
endcase
end
endfunction
always @(posedge clk) begin
if (!product_valid) begin
sum_ff <= 0;
end else begin
`ifdef DEBUG
if (cycle_valid_ff)
$display("mixer outch: %d curr_sum: %h. mpcand %h * mplier %h = %h",
processing_out_ch_ff, $signed(sum_ff), $signed(mp.delayed_a2), $signed(mp.delayed_b2), $signed(saturated_mprod_ff));
`endif
sum_ff <= saturated_add(sum_ff, saturated_mprod_ff);
end
end
// Result
assign data_o = sum_ff;
assign ack_o = (end_of_cycle & cycle_valid_ff) << processing_out_ch_ff;
assign pop_o = {(NUM_CH_IN/NUM_CH_OUT){ack_o}};
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFRTP_TB_V
`define SKY130_FD_SC_HDLL__SDFRTP_TB_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__sdfrtp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg RESET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 SCD = 1'b0;
#80 SCE = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 D = 1'b1;
#200 RESET_B = 1'b1;
#220 SCD = 1'b1;
#240 SCE = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 D = 1'b0;
#360 RESET_B = 1'b0;
#380 SCD = 1'b0;
#400 SCE = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 SCE = 1'b1;
#600 SCD = 1'b1;
#620 RESET_B = 1'b1;
#640 D = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 SCE = 1'bx;
#760 SCD = 1'bx;
#780 RESET_B = 1'bx;
#800 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hdll__sdfrtp dut (.D(D), .SCD(SCD), .SCE(SCE), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFRTP_TB_V
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_0_core_top_axi_basic_tx.v
// Version : 3.0
// //
// Description: //
// AXI to TRN TX module. Instantiates pipeline and throttle control TX //
// submodules. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_tx //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module pcie_7x_0_core_top_axi_basic_tx #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI TX
//-----------
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user
input s_axis_tx_tvalid, // TX data is valid
output s_axis_tx_tready, // TX ready for data
input [KEEP_WIDTH-1:0] s_axis_tx_tkeep, // TX strobe byte enables
input s_axis_tx_tlast, // TX data is last
input [3:0] s_axis_tx_tuser, // TX user signals
// User Misc.
//-----------
input user_turnoff_ok, // Turnoff OK from user
input user_tcfg_gnt, // Send cfg OK from user
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN TX
//-----------
output [C_DATA_WIDTH-1:0] trn_td, // TX data from block
output trn_tsof, // TX start of packet
output trn_teof, // TX end of packet
output trn_tsrc_rdy, // TX source ready
input trn_tdst_rdy, // TX destination ready
output trn_tsrc_dsc, // TX source discontinue
output [REM_WIDTH-1:0] trn_trem, // TX remainder
output trn_terrfwd, // TX error forward
output trn_tstr, // TX streaming enable
input [5:0] trn_tbuf_av, // TX buffers available
output trn_tecrc_gen, // TX ECRC generate
// TRN Misc.
//-----------
input trn_tcfg_req, // TX config request
output trn_tcfg_gnt, // RX config grant
input trn_lnk_up, // PCIe link up
// 7 Series/Virtex6 PM
//-----------
input [2:0] cfg_pcie_link_state, // Encoded PCIe link state
// Virtex6 PM
//-----------
input cfg_pm_send_pme_to, // PM send PME turnoff msg
input [1:0] cfg_pmcsr_powerstate, // PMCSR power state
input [31:0] trn_rdllp_data, // RX DLLP data
input trn_rdllp_src_rdy, // RX DLLP source ready
// Virtex6/Spartan6 PM
//-----------
input cfg_to_turnoff, // Turnoff request
output cfg_turnoff_ok, // Turnoff grant
// System
//-----------
input user_clk, // user clock from block
input user_rst // user reset from block
);
wire tready_thrtl;
//---------------------------------------------//
// TX Data Pipeline //
//---------------------------------------------//
pcie_7x_0_core_top_axi_basic_tx_pipeline #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_PM_PRIORITY( C_PM_PRIORITY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
) tx_pipeline_inst (
// Incoming AXI RX
//-----------
.s_axis_tx_tdata( s_axis_tx_tdata ),
.s_axis_tx_tready( s_axis_tx_tready ),
.s_axis_tx_tvalid( s_axis_tx_tvalid ),
.s_axis_tx_tkeep( s_axis_tx_tkeep ),
.s_axis_tx_tlast( s_axis_tx_tlast ),
.s_axis_tx_tuser( s_axis_tx_tuser ),
// Outgoing TRN TX
//-----------
.trn_td( trn_td ),
.trn_tsof( trn_tsof ),
.trn_teof( trn_teof ),
.trn_tsrc_rdy( trn_tsrc_rdy ),
.trn_tdst_rdy( trn_tdst_rdy ),
.trn_tsrc_dsc( trn_tsrc_dsc ),
.trn_trem( trn_trem ),
.trn_terrfwd( trn_terrfwd ),
.trn_tstr( trn_tstr ),
.trn_tecrc_gen( trn_tecrc_gen ),
.trn_lnk_up( trn_lnk_up ),
// System
//-----------
.tready_thrtl( tready_thrtl ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
//---------------------------------------------//
// TX Throttle Controller //
//---------------------------------------------//
generate
if(C_PM_PRIORITY == "FALSE") begin : thrtl_ctl_enabled
pcie_7x_0_core_top_axi_basic_tx_thrtl_ctl #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.C_ROOT_PORT( C_ROOT_PORT ),
.TCQ( TCQ )
) tx_thrl_ctl_inst (
// Outgoing AXI TX
//-----------
.s_axis_tx_tdata( s_axis_tx_tdata ),
.s_axis_tx_tvalid( s_axis_tx_tvalid ),
.s_axis_tx_tuser( s_axis_tx_tuser ),
.s_axis_tx_tlast( s_axis_tx_tlast ),
// User Misc.
//-----------
.user_turnoff_ok( user_turnoff_ok ),
.user_tcfg_gnt( user_tcfg_gnt ),
// Incoming TRN RX
//-----------
.trn_tbuf_av( trn_tbuf_av ),
.trn_tdst_rdy( trn_tdst_rdy ),
// TRN Misc.
//-----------
.trn_tcfg_req( trn_tcfg_req ),
.trn_tcfg_gnt( trn_tcfg_gnt ),
.trn_lnk_up( trn_lnk_up ),
// 7 Seriesq/Virtex6 PM
//-----------
.cfg_pcie_link_state( cfg_pcie_link_state ),
// Virtex6 PM
//-----------
.cfg_pm_send_pme_to( cfg_pm_send_pme_to ),
.cfg_pmcsr_powerstate( cfg_pmcsr_powerstate ),
.trn_rdllp_data( trn_rdllp_data ),
.trn_rdllp_src_rdy( trn_rdllp_src_rdy ),
// Spartan6 PM
//-----------
.cfg_to_turnoff( cfg_to_turnoff ),
.cfg_turnoff_ok( cfg_turnoff_ok ),
// System
//-----------
.tready_thrtl( tready_thrtl ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
end
else begin : thrtl_ctl_disabled
assign tready_thrtl = 1'b0;
assign cfg_turnoff_ok = user_turnoff_ok;
assign trn_tcfg_gnt = user_tcfg_gnt;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> int main() { std::ios::sync_with_stdio(false); int n; long long m, k; long long tmp; std::cin >> n >> m >> k; std::vector<long long> a; for (int i = 0; i < n; i++) { std::cin >> tmp; a.push_back(tmp); } std::sort(a.begin(), a.end()); std::cout << (m / (k + 1)) * (*(a.end() - 2)) + (m - (m / (k + 1))) * (*(a.end() - 1)); return 0; } |
module midi_in(clk, rst, midi_in,
ch_message,
chan, note, velocity, lsb, msb //параметры сообщений
);
input wire clk; // 50 MHz clock
input wire rst; // reset
input wire midi_in; // MIDI in data
//note control
output wire [3:0] chan; // номер канала, в который отправляется нота. в ПО считаются от 1 до 16. тут считаются с 0. То есть барабаны - 10й, тут будет 9.
output wire [6:0] note; // номер ноты 0 - это С-1, 12 - С0, 24 - С1
output wire [6:0] velocity;
output wire [6:0] lsb;
output wire [6:0] msb;
output wire [3:0] ch_message;
reg [23:0] midi_command; //миди команда 3 байта
reg [7:0] rcv_state;
//состояние приемника
//0 - ожидаем любой байт
//1 - принят первый байт сообщения канала nnnn одно из сообщений ниже, и ждем еще двух байт данных, у которых старший бит = 0, иначе это реалтайм сообщения
// 1000nnnn - note Off (Номер ноты(note); Динамика(velocity))
// 1001nnnn - note On (Номер ноты(note); Динамика(velocity))
// 1010nnnn - Polyphonic Key Prstsure (Номер ноты(note); Давление(velocity))
// 1011nnnn - Control change (Номер контроллера(lsb); Значение контроллера(msb))
// 1100nnnn - Program change (Номер программы(lsb); -)
// 1101nnnn - channel Prstsure (Давление(lsb); -)
// 1110nnnn - Pitch Wheel change (lsb;msb)
//2 - принят второй байт сообщения канала
//3 - принят третий байт сообщения канала и переход в 0
reg [7:0] byte1;
reg [7:0] byte2;
reg [7:0] byte3;
initial begin
//chan <= 4'b0000;
//note <= 7'd0;
//velocity <= 7'd0;
//lsb <= 7'd0;
//msb <= 7'd0;
//ch_message <= 4'd0;
rcv_state <= 8'b00000000;
byte1 <= 8'd0;
byte2 <= 8'd0;
byte3 <= 8'd0;
end
//midi rx
//бодген - модуль для генерации клока UART
// first register:
// baud_freq = 16*baud_rate / gcd(global_clock_freq, 16*baud_rate)
//Greatest Common Divisor - наибольший общий делитель. http://www.alcula.com/calculators/math/gcd/
//baud_freq = 16*31250 / gcd(50000000, 50000) = 500000 / 500000 = 1
// second register:
// baud_limit = (global_clock_freq / gcd(global_clock_freq, 16*baud_rate)) - baud_freq
//baud_limit = (50000000 / gcd(50000000, 500000)) - 1
// = ( 50000000 / 500000) - 1 = 99
wire port_clk;
wire [7:0] uart_command;
wire ucom_ready;
reg midi_command_ready;
initial midi_command_ready <= 0;
baud_gen BG( clk, rst, port_clk, 1, 99);
uart_rx URX( clk, rst, port_clk, midi_in, uart_command, ucom_ready );
always @ (posedge clk) begin
if (ucom_ready==1) begin
//Ожидаем сообщение
if (rcv_state==8'd0) begin
//в любом случае сбрасываем вообще все
//chan <= 4'b0000;
//note <= 7'd0;
//velocity <= 7'd0;
//lsb <= 7'd0;
//msb <= 7'd0;
//ch_message <= 4'd0;
rcv_state <= 8'b00000000;
byte1 <= 8'd0;
byte2 <= 8'd0;
byte3 <= 8'd0;
//если старший бит = 1, то это сообщение
//запоминаем байт
if (uart_command[7:7]==1'b1) byte1 <= uart_command;
//смена стейта
rcv_state <= ((uart_command[7:4]>=4'b1000)&&(uart_command[7:4]<=4'b1110)) ? 8'd01 : rcv_state;
end else if (rcv_state==8'd01) begin //ждем первый байт данных
//если старший бит = 0, то это данные
if (uart_command[7:7]==1'b0) byte2 <= uart_command;
//сменf стейта
rcv_state <= (uart_command[7:7]==1'b0) ? 8'd2 : rcv_state;
end else if (rcv_state==8'd02) begin //ждем второй байт данных
//если старший бит = 0, то это данные
if (uart_command[7:7]==1'b0) byte3 <= uart_command;
midi_command_ready <= 1;
//смена стейта
rcv_state <= (uart_command[7:7]==1'b0) ? 8'd0 : rcv_state;
end
end //ucom_ready
else begin
midi_command_ready <= 0;
end
end
assign chan = (midi_command_ready) ? byte1[3:0] : 4'b0000;
assign ch_message = (midi_command_ready) ? byte1[7:4] : 4'b0000;
wire PCCP = ((byte1[7:4]==4'b1100)||(byte1[7:4]==4'b1101)); // Program change, Channel pressure (MSB = 0)
assign lsb = (midi_command_ready) ? byte2[6:0] : 4'b0000;
assign msb = (midi_command_ready&&(!PCCP)) ? byte3[6:0] : 4'b0000;
//note off, note on, poly key pressure
wire note_info = ((byte1[7:4]==4'b1000)||(byte1[7:4]==4'b1001)||(byte1[7:4]==4'b1010));
assign note = (midi_command_ready && note_info) ? byte2[6:0] : 7'b0000000;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A21OI_4_V
`define SKY130_FD_SC_HS__A21OI_4_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog wrapper for a21oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a21oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a21oi_4 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a21oi_4 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A21OI_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MAJ3_PP_SYMBOL_V
`define SKY130_FD_SC_MS__MAJ3_PP_SYMBOL_V
/**
* maj3: 3-input majority vote.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__maj3 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__MAJ3_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { string s1; cin >> s1; int condition = 1; for (int i = 1; i <= s1.length(); i++) { if (s1[i] == s1[i - 1]) { condition++; if (condition == 7) { cout << YES << endl; return 0; } } else { condition = 1; } } cout << NO << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int gcd(int a, int b) { if (b == 0) return a; else return gcd(b, a % b); } int rev(int n) { int ret = 0; while (n != 0) { ret = (10 * ret) + (n % 10); n /= 10; } return ret; } int main() { int mx, my, w; int i, j, k, t; int ax, ay; vector<int> v; map<pair<int, int>, vector<int> > mp; scanf( %d%d%d , &mx, &my, &w); for (i = 1; i <= my; i++) { j = rev(i); k = gcd(i, j); mp[make_pair(i / k, j / k)].push_back(i); } vector<int> vec(my + 1, 0); vector<vector<int> > vv; vv.push_back(v); for (i = 1; i <= mx; i++) { j = rev(i); k = gcd(i, j); v = mp[make_pair(j / k, i / k)]; for (j = 0; j < v.size(); j++) vec[v[j]]++; vv.push_back(v); } long long ans = -1; for (i = mx, j = 0, k = 0; i > 0; i--) { if (k < w && j < my) { do { j++; k += vec[j]; } while (k < w && j < my); } if (k >= w && (ans == -1 || ans > (long long)i * j)) { ans = (long long)i * j; ax = i; ay = j; } for (t = 0; t < vv[i].size(); t++) { if (vv[i][t] <= j) k--; vec[vv[i][t]]--; } } if (ans == -1) printf( -1 n ); else printf( %d %d n , ax, ay); return 0; } |
/*
* Milkymist VJ SoC fjmem flasher
* Copyright (C) 2010 Michael Walle <>
* Copyright (C) 2008 Arnim Laeuger <>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*
* This core is derived from the VHDL version supplied with UrJTAG, written
* by Arnim Laeuger.
*
*/
module fjmem_core #(
parameter adr_width = 24,
parameter timing = 4'd6
) (
input sys_clk,
input sys_rst,
/* jtag */
input jtag_tck,
input jtag_rst,
input jtag_update,
input jtag_shift,
input jtag_tdi,
output jtag_tdo,
/* flash */
output [adr_width-1:0] flash_adr,
inout [15:0] flash_d,
output reg flash_oe_n,
output reg flash_we_n,
/* debug */
output fjmem_update
);
parameter INSTR_IDLE = 3'b000;
parameter INSTR_DETECT = 3'b111;
parameter INSTR_QUERY = 3'b110;
parameter INSTR_READ = 3'b001;
parameter INSTR_WRITE = 3'b010;
parameter aw = adr_width;
parameter sw = aw+21;
reg [sw-1:0] shift_r;
assign jtag_tdo = shift_r[0];
assign read = (instr == INSTR_READ);
assign write = (instr == INSTR_WRITE);
always @(posedge jtag_tck or posedge jtag_rst)
begin
if (jtag_rst) begin
shift_r <= {(sw){1'b0}};
end
else if (jtag_shift) begin
/* shift mode */
shift_r[sw-1:0] <= { jtag_tdi, shift_r[sw-1:1] };
end
else begin
/* capture mode */
shift_r[2:0] <= instr;
case (instr)
INSTR_READ:
begin
shift_r[3] <= ack_q;
shift_r[aw+20:aw+5] <= din;
end
INSTR_WRITE:
begin
end
INSTR_IDLE:
begin
shift_r <= {(sw){1'b0}};
end
INSTR_DETECT:
begin
shift_r[4] <= 1'b1;
shift_r[aw+4:5] <= {(aw){1'b0}};
shift_r[aw+20:aw+5] <= 16'b1111111111111111;
end
INSTR_QUERY:
begin
if (~block) begin
shift_r[aw+4:5] <= {(aw){1'b1}};
shift_r[aw+20:aw+5] <= 16'b1111111111111111;
end
else begin
shift_r[sw-1:3] <= {(sw-3){1'b0}};
end
end
default:
shift_r[sw-1:3] <= {(sw-3){1'bx}};
endcase
end
end
reg [2:0] instr;
reg block;
reg [aw-1:0] addr;
reg [15:0] dout;
reg strobe_toggle;
assign flash_d = (flash_oe_n) ? dout : 16'bz;
assign flash_adr = addr;
/*
* 2:0 : instr
* 3 : ack
* 4 : block
* (aw+4):5 : addr
* (aw+20):(aw+5) : data
*/
always @(posedge jtag_update or posedge jtag_rst)
begin
if (jtag_rst) begin
instr <= INSTR_IDLE;
block <= 1'b0;
addr <= {(aw){1'b0}};
dout <= 16'h0000;
strobe_toggle <= 1'b0;
end
else begin
instr <= shift_r[2:0];
block <= shift_r[4];
addr <= shift_r[aw+4:5];
dout <= shift_r[aw+20:aw+5];
strobe_toggle <= ~strobe_toggle;
end
end
wire strobe;
reg strobe_q;
reg strobe_qq;
reg strobe_qqq;
assign strobe = strobe_qq ^ strobe_qqq;
always @(posedge sys_clk)
begin
if (sys_rst) begin
strobe_q <= 1'b0;
strobe_qq <= 1'b0;
strobe_qqq <= 1'b0;
end
else begin
strobe_q <= strobe_toggle;
strobe_qq <= strobe_q;
strobe_qqq <= strobe_qq;
end
end
reg [3:0] counter;
reg counter_en;
wire counter_done = (counter == timing);
always @(posedge sys_clk)
begin
if (sys_rst)
counter <= 4'd0;
else begin
if (counter_en & ~counter_done)
counter <= counter + 4'd1;
else
counter <= 4'd0;
end
end
reg ack_q;
always @(posedge sys_clk)
begin
if (sys_rst)
ack_q <= 1'b0;
else
ack_q <= ack;
end
parameter IDLE = 2'd0;
parameter DELAYRD = 2'd1;
parameter DELAYWR = 2'd2;
parameter RD = 2'd3;
reg [15:0] din;
reg [1:0] state;
reg ack;
always @(posedge sys_clk)
begin
if (sys_rst) begin
flash_oe_n <= 1'b1;
flash_we_n <= 1'b1;
ack <= 1'b0;
din <= 16'h0000;
state <= IDLE;
end
else begin
flash_oe_n <= 1'b1;
flash_we_n <= 1'b1;
counter_en <= 1'b0;
case (state)
IDLE: begin
ack <= 1;
if (strobe)
if (read)
state <= DELAYRD;
else if (write)
state <= DELAYWR;
end
DELAYRD: begin
ack <= 0;
flash_oe_n <= 1'b0;
counter_en <= 1'b1;
if (counter_done)
state <= RD;
end
DELAYWR: begin
flash_we_n <= 1'b0;
counter_en <= 1'b1;
if (counter_done)
state <= IDLE;
end
RD: begin
counter_en <= 1'b0;
din <= flash_d;
state <= IDLE;
end
endcase
end
end
assign fjmem_update = strobe_toggle;
endmodule
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