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/*
* Copyright 2012, Homer Hsing <>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`define M 593 // M is the degree of the irreducible polynomial
`define WIDTH (2*`M-1) // width for a GF(3^M) element
`define WIDTH_D0 1187
module tiny(clk, reset, sel, addr, w, data, out, done);
input clk, reset;
input sel;
input [5:0] addr;
input w;
input [`WIDTH_D0:0] data;
output [`WIDTH_D0:0] out;
output done;
/* for FSM */
wire [5:0] fsm_addr;
/* for RAM */
wire [5:0] ram_a_addr, ram_b_addr;
wire [`WIDTH_D0:0] ram_b_data_in;
wire ram_a_w, ram_b_w;
wire [`WIDTH_D0:0] ram_a_data_out, ram_b_data_out;
/* for const */
wire [`WIDTH_D0:0] const0_out, const1_out;
wire const0_effective, const1_effective;
/* for muxer */
wire [`WIDTH_D0:0] muxer0_out, muxer1_out;
/* for ROM */
wire [8:0] rom_addr;
wire [28:0] rom_q;
/* for PE */
wire [10:0] pe_ctrl;
assign out = ram_a_data_out;
select
select0 (sel, addr, fsm_addr, w, ram_a_addr, ram_a_w);
rom
rom0 (clk, rom_addr, rom_q);
FSM
fsm0 (clk, reset, rom_addr, rom_q, fsm_addr, ram_b_addr, ram_b_w, pe_ctrl, done);
const_
const0 (clk, ram_a_addr, const0_out, const0_effective),
const1 (clk, ram_b_addr, const1_out, const1_effective);
ram
ram0 (clk, ram_a_w, ram_a_addr, data, ram_a_data_out, ram_b_w, ram_b_addr[5:0], ram_b_data_in, ram_b_data_out);
muxer
muxer0 (ram_a_data_out, const0_out, const0_effective, muxer0_out),
muxer1 (ram_b_data_out, const1_out, const1_effective, muxer1_out);
PE
pe0 (clk, reset, pe_ctrl, muxer1_out, muxer0_out[`WIDTH:0], muxer0_out[`WIDTH:0], ram_b_data_in[`WIDTH:0]);
assign ram_b_data_in[`WIDTH_D0:`WIDTH+1] = 0;
endmodule
module select(sel, addr_in, addr_fsm_in, w_in, addr_out, w_out);
input sel;
input [5:0] addr_in;
input [5:0] addr_fsm_in;
input w_in;
output [5:0] addr_out;
output w_out;
assign addr_out = sel ? addr_in : addr_fsm_in;
assign w_out = sel & w_in;
endmodule
module muxer(from_ram, from_const, const_effective, out);
input [`WIDTH_D0:0] from_ram, from_const;
input const_effective;
output [`WIDTH_D0:0] out;
assign out = const_effective ? from_const : from_ram;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k, t, i, j, ii, a; while (scanf( %d%d%d , &n, &k, &t) != EOF) { for (i = 1; i <= n; i++) { if ((i * k + 1) * 100 > t * n * k) break; } for (j = 0; j <= k; j++) { a = (i - 1) * k + j; if (n * k * t >= 100 * a && (a + 1) * 100 > t * n * k) { for (ii = 1; ii <= i - 1; ii++) printf( %d , k); printf( %d , j); for (ii = i + 1; ii <= n; ii++) printf( %d , 0); printf( n ); break; } } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 105; const int M = 505; const int MOD = int(1e9) + 7; const int INF = 0x3f3f3f3f; const double EPS = 1e-9; const double PI = acos(-1.0); const int dx[] = {-1, 1, 0, 0}; const int dy[] = {0, 0, -1, 1}; template <class T> inline T Min(T a, T b) { return a < b ? a : b; } template <class T> inline T Max(T a, T b) { return a > b ? a : b; } template <class T> inline T Min(T a, T b, T c) { return min(min(a, b), c); } template <class T> inline T Max(T a, T b, T c) { return max(max(a, b), c); } template <class T> inline T sqr(T a) { return a * a; } template <class T> inline T cub(T a) { return a * a * a; } template <class T> inline T gcd(T a, T b) { return b == 0 ? a : gcd(b, a % b); } template <class T> inline T lcm(T a, T b) { return a * b / gcd(a, b); } int main() { int a, b; while (scanf( %d%d , &a, &b) != EOF) { int i, tot = (a * (a - 1)) / 2; if (tot <= b) { printf( no solution n ); } else { for (i = 0; i < a; i++) { printf( %d %d n , 0, i); } } } return 0; } |
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE AC 97 Controller ////
//// Output FIFO ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: ac97_out_fifo.v,v 1.4 2002/09/19 06:30:56 rudi Exp $
//
// $Date: 2002/09/19 06:30:56 $
// $Revision: 1.4 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: ac97_out_fifo.v,v $
// Revision 1.4 2002/09/19 06:30:56 rudi
// Fixed a bug reported by Igor. Apparently this bug only shows up when
// the WB clock is very low (2x bit_clk). Updated Copyright header.
//
// Revision 1.3 2002/03/11 03:21:22 rudi
//
// - Added defines to select fifo depth between 4, 8 and 16 entries.
//
// Revision 1.1 2001/08/03 06:54:50 rudi
//
//
// - Changed to new directory structure
//
// Revision 1.1.1.1 2001/05/19 02:29:16 rudi
// Initial Checkin
//
//
//
//
`include "ac97_defines.v"
//`ifdef AC97_OUT_FIFO_DEPTH_4
// 4 Entry Deep version of the Output FIFO
module ac97_out_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);
input clk, rst;
input en;
input [1:0] mode;
input [31:0] din;
input we;
output [19:0] dout;
input re;
output [1:0] status;
output full;
output empty;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg [31:0] mem[0:3];
reg [2:0] wp;
reg [3:0] rp;
wire [2:0] wp_p1;
reg [1:0] status;
reg [19:0] dout;
wire [31:0] dout_tmp;
wire [15:0] dout_tmp1;
wire m16b;
reg empty;
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
assign m16b = (mode == 2'h0); // 16 Bit Mode
always @(posedge clk)
if(!en) wp <= #1 3'h0;
else
if(we) wp <= #1 wp_p1;
assign wp_p1 = wp + 3'h1;
always @(posedge clk)
if(!en) rp <= #1 4'h0;
else
if(re & m16b) rp <= #1 rp + 4'h1;
else
if(re & !m16b) rp <= #1 rp + 4'h2;
always @(posedge clk)
status <= #1 (wp[1:0] - rp[2:1]) - 2'h1;
wire [3:0] rp_p1 = rp[3:0] + 4'h1;
always @(posedge clk)
empty <= #1 (rp_p1[3:1] == wp[2:0]) & (m16b ? rp_p1[0] : 1'b1);
assign full = (wp[1:0] == rp[2:1]) & (wp[2] != rp[3]);
// Fifo Output
assign dout_tmp = mem[ rp[2:1] ];
// Fifo Output Half Word Select
assign dout_tmp1 = rp[0] ? dout_tmp[31:16] : dout_tmp[15:0];
always @(posedge clk)
if(!en) dout <= #1 20'h0;
else
if(re)
case(mode) // synopsys parallel_case full_case
2'h0: dout <= #1 {dout_tmp1, 4'h0}; // 16 Bit Output
2'h1: dout <= #1 {dout_tmp[17:0], 2'h0}; // 18 bit Output
2'h2: dout <= #1 dout_tmp[19:0]; // 20 Bit Output
endcase
always @(posedge clk)
if(we) mem[wp[1:0]] <= #1 din;
endmodule
//`endif
`ifdef AC97_OUT_FIFO_DEPTH_8
// 8 Entry Deep version of the Output FIFO
module ac97_out_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);
input clk, rst;
input en;
input [1:0] mode;
input [31:0] din;
input we;
output [19:0] dout;
input re;
output [1:0] status;
output full;
output empty;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg [31:0] mem[0:7];
reg [3:0] wp;
reg [4:0] rp;
wire [3:0] wp_p1;
reg [1:0] status;
reg [19:0] dout;
wire [31:0] dout_tmp;
wire [15:0] dout_tmp1;
wire m16b;
reg empty;
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
assign m16b = (mode == 2'h0); // 16 Bit Mode
always @(posedge clk)
if(!en) wp <= #1 4'h0;
else
if(we) wp <= #1 wp_p1;
assign wp_p1 = wp + 4'h1;
always @(posedge clk)
if(!en) rp <= #1 5'h0;
else
if(re & m16b) rp <= #1 rp + 5'h1;
else
if(re & !m16b) rp <= #1 rp + 5'h2;
always @(posedge clk)
status <= #1 (wp[2:1] - rp[3:2]) - 2'h1;
wire [4:0] rp_p1 = rp[4:0] + 5'h1;
always @(posedge clk)
empty <= #1 (rp_p1[4:1] == wp[3:0]) & (m16b ? rp_p1[0] : 1'b1);
assign full = (wp[2:0] == rp[3:1]) & (wp[3] != rp[4]);
// Fifo Output
assign dout_tmp = mem[ rp[3:1] ];
// Fifo Output Half Word Select
assign dout_tmp1 = rp[0] ? dout_tmp[31:16] : dout_tmp[15:0];
always @(posedge clk)
if(!en) dout <= #1 20'h0;
else
if(re)
case(mode) // synopsys parallel_case full_case
2'h0: dout <= #1 {dout_tmp1, 4'h0}; // 16 Bit Output
2'h1: dout <= #1 {dout_tmp[17:0], 2'h0}; // 18 bit Output
2'h2: dout <= #1 dout_tmp[19:0]; // 20 Bit Output
endcase
always @(posedge clk)
if(we) mem[wp[2:0]] <= #1 din;
endmodule
`endif
`ifdef AC97_OUT_FIFO_DEPTH_16
// 16 Entry Deep version of the Output FIFO
module ac97_out_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);
input clk, rst;
input en;
input [1:0] mode;
input [31:0] din;
input we;
output [19:0] dout;
input re;
output [1:0] status;
output full;
output empty;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg [31:0] mem[0:15];
reg [4:0] wp;
reg [5:0] rp;
wire [4:0] wp_p1;
reg [1:0] status;
reg [19:0] dout;
wire [31:0] dout_tmp;
wire [15:0] dout_tmp1;
wire m16b;
reg empty;
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
assign m16b = (mode == 2'h0); // 16 Bit Mode
always @(posedge clk)
if(!en) wp <= #1 5'h0;
else
if(we) wp <= #1 wp_p1;
assign wp_p1 = wp + 4'h1;
always @(posedge clk)
if(!en) rp <= #1 6'h0;
else
if(re & m16b) rp <= #1 rp + 6'h1;
else
if(re & !m16b) rp <= #1 rp + 6'h2;
always @(posedge clk)
status <= #1 (wp[3:2] - rp[4:3]) - 2'h1;
wire [5:0] rp_p1 = rp[5:0] + 6'h1;
always @(posedge clk)
empty <= #1 (rp_p1[5:1] == wp[4:0]) & (m16b ? rp_p1[0] : 1'b1);
assign full = (wp[3:0] == rp[4:1]) & (wp[4] != rp[5]);
// Fifo Output
assign dout_tmp = mem[ rp[4:1] ];
// Fifo Output Half Word Select
assign dout_tmp1 = rp[0] ? dout_tmp[31:16] : dout_tmp[15:0];
always @(posedge clk)
if(!en) dout <= #1 20'h0;
else
if(re)
case(mode) // synopsys parallel_case full_case
2'h0: dout <= #1 {dout_tmp1, 4'h0}; // 16 Bit Output
2'h1: dout <= #1 {dout_tmp[17:0], 2'h0}; // 18 bit Output
2'h2: dout <= #1 dout_tmp[19:0]; // 20 Bit Output
endcase
always @(posedge clk)
if(we) mem[wp[3:0]] <= #1 din;
endmodule
`endif
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Reset_Delay.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Reset_Delay
// Source Path: velocityControlHdl/Control_DQ_Currents/Control_Current/Reset_Delay
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Reset_Delay
(
CLK_IN,
reset,
enb_1_2000_0,
Reset_1,
In,
Out
);
input CLK_IN;
input reset;
input enb_1_2000_0;
input Reset_1;
input signed [31:0] In; // sfix32_En26
output signed [31:0] Out; // sfix32_En26
wire signed [31:0] Constant1_out1; // sfix32_En26
wire signed [31:0] Reset_Switch1_out1; // sfix32_En26
reg signed [31:0] In_Delay_out1; // sfix32_En26
wire signed [31:0] Constant_out1; // sfix32_En26
wire signed [31:0] Reset_Switch_out1; // sfix32_En26
// <S13>/Constant1
assign Constant1_out1 = 32'sb00000000000000000000000000000000;
// <S13>/Reset_Switch1
assign Reset_Switch1_out1 = (Reset_1 == 1'b0 ? In :
Constant1_out1);
// <S13>/In_Delay
always @(posedge CLK_IN)
begin : In_Delay_process
if (reset == 1'b1) begin
In_Delay_out1 <= 32'sb00000000000000000000000000000000;
end
else if (enb_1_2000_0) begin
In_Delay_out1 <= Reset_Switch1_out1;
end
end
// <S13>/Constant
assign Constant_out1 = 32'sb00000000000000000000000000000000;
// <S13>/Reset_Switch
assign Reset_Switch_out1 = (Reset_1 == 1'b0 ? In_Delay_out1 :
Constant_out1);
assign Out = Reset_Switch_out1;
endmodule // velocityControlHdl_Reset_Delay
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); int n; cin >> n; vector<string> a(n + 1), b(n + 1); vector<int> c(n + 1); vector<long long> f1(n + 1), f2(n + 1); for (int i = 1; i <= n; ++i) { cin >> c[i]; } for (int i = 1; i <= n; ++i) { cin >> a[i]; b[i] = a[i]; reverse(b[i].begin(), b[i].end()); } for (int i = 1; i <= n; ++i) { f1[i] = f2[i] = LLONG_MAX; if (f1[i - 1] != LLONG_MAX) { if (a[i] >= a[i - 1]) { f1[i] = min(f1[i], f1[i - 1]); } if (b[i] >= a[i - 1]) { f2[i] = min(f2[i], f1[i - 1] + c[i]); } } if (f2[i - 1] != LLONG_MAX) { if (a[i] >= b[i - 1]) { f1[i] = min(f1[i], f2[i - 1]); } if (b[i] >= b[i - 1]) { f2[i] = min(f2[i], f2[i - 1] + c[i]); } } } if (f1[n] == LLONG_MAX && f2[n] == LLONG_MAX) { cout << -1; } else { cout << min(f1[n], f2[n]); } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFRBP_BLACKBOX_V
`define SKY130_FD_SC_HVL__SDFRBP_BLACKBOX_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFRBP_BLACKBOX_V
|
// TOOL: vlog2tf
// DATE: Wed May 07 12:26:41 2014
// TITLE: Lattice Semiconductor Corporation
// MODULE: section3_schematic
// DESIGN: section3_schematic
// FILENAME: section3_schematic_tf.v
// PROJECT: Unknown
// VERSION: 2.0
// This file is auto generated by the Diamond
`timescale 1 ns / 1 ns
// Define Module for Test Fixture
module section3_schematic_tf();
// Inputs
reg A;
reg B;
reg C;
reg D;
// Outputs
wire SegA;
wire SegB;
wire SegC;
wire SegD;
wire SegE;
wire SegF;
wire SegG;
// Bidirs
// Instantiate the UUT
// Please check and add your parameters manually
section3_schematic UUT (
.A(A),
.B(B),
.C(C),
.D(D),
.SegA(SegA),
.SegB(SegB),
.SegC(SegC),
.SegD(SegD),
.SegE(SegE),
.SegF(SegF),
.SegG(SegG)
);
// Initialize Inputs
// You can add your stimulus here
initial begin
A = 0; B = 0; C = 0; D = 0;
#10 A = 0; B = 0; C = 0; D = 1;
#10 A = 0; B = 0; C = 1; D = 0;
#10 A = 0; B = 0; C = 1; D = 1;
#10 A = 0; B = 1; C = 0; D = 0;
#10 A = 0; B = 1; C = 0; D = 1;
#10 A = 0; B = 1; C = 1; D = 0;
#10 A = 0; B = 1; C = 1; D = 1;
#10 A = 1; B = 0; C = 0; D = 1;
#10 A = 1; B = 0; C = 1; D = 0;
#10 A = 1; B = 0; C = 1; D = 1;
#10 A = 1; B = 1; C = 0; D = 0;
#10 A = 1; B = 1; C = 0; D = 1;
#10 A = 1; B = 1; C = 1; D = 0;
#10 A = 1; B = 1; C = 1; D = 1;
end
endmodule // section3_schematic_tf |
#include <bits/stdc++.h> using namespace std; const long long INF = (long long)1e9 + 999999; const long long Mod = (long long)1e9 + 7; const long long MaXN = (long long)1e18; const int N = (int)1e6 + 7; const int MaXI = (int)1e9; const int Mass = (int)2e5; int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); int n; cin >> n; string s; cin >> s; int b = 0, g = 0, r = 0; for (int i = 0; i < s.size(); i++) { if (s[i] == B ) { b++; } if (s[i] == G ) { g++; } if (s[i] == R ) { r++; } } if (b == n) { cout << B ; return 0; } else if (g == n) { cout << G ; return 0; } else if (r == n) { cout << R ; return 0; } if (r > 1 || g > 1) { cout << B ; } else if (r == 1 && g == 1) { cout << B ; } if (b > 1 || r > 1) { cout << G ; } else if (b == 1 && r == 1) { cout << G ; } if (b > 1 || g > 1) { cout << R ; } else if (b == 1 && g == 1) { cout << R ; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD1_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__CLKDLYINV5SD1_FUNCTIONAL_PP_V
/**
* clkdlyinv5sd1: Clock Delay Inverter 5-stage 0.15um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__clkdlyinv5sd1 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV5SD1_FUNCTIONAL_PP_V |
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_cpu_jtag_debug_module_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
jdo[36];
assign take_no_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
~jdo[36];
assign take_action_tracemem_b = enable_action_strobe && (ir == 2'b01) &&
jdo[37];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21.02.2016 16:25:28
// Design Name:
// Module Name: ARINC429
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ARINC429(
input wire [1 : 0] nvel,
input wire [7 : 0] adr,
input wire [22 : 0] dat,
input wire GCLK,
output wire TXD0,
output wire TXD1,
input wire RXD0,
input wire RXD1,
input wire st,
output reg [7:0] sr_adr,
output reg [22:0] sr_dat,
output reg ce_wr,
input wire rec_disp, // reciever dispatcher
input wire reset
);
AR_TXD TX
(
.clk(GCLK),
.Nvel(nvel),
.ADR(adr),
.DAT(dat),
.st(st),
.TXD0(TXD0),
.TXD1(TXD1),
.reset(reset)
);
wire [7:0] sr_adr_1;
wire [22:0] sr_dat_1;
wire ce_wr_1;
AR_RXD RX
(
.clk(GCLK),
.in0(RXD0),
.in1(RXD1),
.sr_dat(sr_dat_1),
.sr_adr(sr_adr_1),
.ce_wr(ce_wr_1)
);
wire [7:0] sr_adr_2;
wire [22:0] sr_dat_2;
wire ce_wr_2;
AR_RXD_2 RX_2
(
.clk(GCLK),
.in0(RXD0),
.in1(RXD1),
.sr_dat(sr_dat_2),
.sr_adr(sr_adr_2),
.ce_wr(ce_wr_2)
);
always @(posedge GCLK)
begin
sr_dat <= rec_disp ? sr_dat_1 : sr_dat_2;
sr_adr <= rec_disp ? sr_adr_1 : sr_adr_2;
ce_wr <= rec_disp ? ce_wr_1 : ce_wr_2;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int L, f, b; int n; int pos[110]; map<int, int> lot; int findpos(int L) { map<int, int>::iterator cur, next; cur = lot.begin(), next = cur; next++; for (; next != lot.end(); cur++, next++) { int back = cur->first + cur->second, front = next->first; if (back + b + L + f <= front) return back + b; } return -1; } int main() { scanf( %d%d%d , &L, &b, &f); scanf( %d , &n); lot.clear(); lot.insert(make_pair(-b, 0)); lot.insert(make_pair(L + f, 0)); for (int i = 0; i < n; i++) { int a, b; scanf( %d%d , &a, &b); if (a == 1) { int pl = findpos(b); pos[i + 1] = pl; if (pl >= 0) lot.insert(make_pair(pl, b)); printf( %d n , pl); } else { if (pos[b] < 0) continue; lot.erase(pos[b]); } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__LSBUFISO0P_TB_V
`define SKY130_FD_SC_LP__LSBUFISO0P_TB_V
/**
* lsbufiso0p: ????.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__lsbufiso0p.v"
module top();
// Inputs are registered
reg SLEEP;
reg A;
reg DESTPWR;
reg VPWR;
reg VGND;
reg DESTVPB;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
DESTPWR = 1'bX;
DESTVPB = 1'bX;
SLEEP = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 DESTPWR = 1'b0;
#60 DESTVPB = 1'b0;
#80 SLEEP = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A = 1'b1;
#200 DESTPWR = 1'b1;
#220 DESTVPB = 1'b1;
#240 SLEEP = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A = 1'b0;
#360 DESTPWR = 1'b0;
#380 DESTVPB = 1'b0;
#400 SLEEP = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 SLEEP = 1'b1;
#600 DESTVPB = 1'b1;
#620 DESTPWR = 1'b1;
#640 A = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 SLEEP = 1'bx;
#760 DESTVPB = 1'bx;
#780 DESTPWR = 1'bx;
#800 A = 1'bx;
end
sky130_fd_sc_lp__lsbufiso0p dut (.SLEEP(SLEEP), .A(A), .DESTPWR(DESTPWR), .VPWR(VPWR), .VGND(VGND), .DESTVPB(DESTVPB), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__LSBUFISO0P_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A41OI_BLACKBOX_V
`define SKY130_FD_SC_HD__A41OI_BLACKBOX_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a41oi (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A41OI_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; string s[10100]; string sep; bool u[10100] = {false}; vector<string> str; string make(pair<string, string> p) { return ((p.first + sep + p.second) < (p.second + sep + p.first)) ? (p.first + sep + p.second) : (p.second + sep + p.first); } int main() { int n = 0, sumLeng = 0, len = 0; cin >> n; for (int i = 0; i < n; ++i) { cin >> s[i]; sumLeng += s[i].length(); } cin >> sep; len = sumLeng / (n / 2); sort(s, s + n); for (int i = 0; i < n; ++i) { if (u[i]) continue; int leng = s[i].length(); for (int j = 0; j < n; ++j) if (!u[j] && leng + s[j].length() == len && i != j) { str.push_back(make(make_pair(s[i], s[j]))); u[i] = true; u[j] = true; break; } } sort(str.begin(), str.end()); for (int i = 0; i < n / 2; ++i) cout << str[i] << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; void ga(int N, int *A) { for (int i(0); i < N; i++) scanf( %d , A + i); } char s[222222], r[222222]; int N, A, B; int main(void) { scanf( %s%s , s, r), N = strlen(s); for (int i(0); i < N; i++) if (s[i] ^ r[i]) A += s[i] == 52, B += s[i] != 52; printf( %d n , max(A, B)); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, q; char s[111111][12]; const int OFF = 128, BITS = 7, MASK = 127; int dy[111111][12], dx[111111][12]; char qu[5]; int mx; void go(int &y, int &x, int upTo) { for (int z = 0; z < (int)(mx); ++z) { if (s[y][x] == ^ ) { --y; if (y == upTo || y == 0) break; } else if (s[y][x] == < ) { if (--x == 0) break; } else { if (++x > m) break; } } } int main() { scanf( %d%d%d , &n, &m, &q); for (int i = 1; i <= n; ++i) scanf( %s , s[i] + 1), s[i][0] = s[i][m + 1] = f ; for (int i = 0; i < (int)(m + 2); ++i) s[0][i] = s[n + 1][i] = f ; mx = (OFF + 2) * m; for (int i = OFF; i <= n; i += OFF) for (int j = 1; j <= m; ++j) { int y = i, x = j; go(y, x, i - OFF); if (y != i - OFF && y != 0 && x != 0 && x != m + 1) dy[i][j] = -1; else { dy[i][j] = y; dx[i][j] = x; } } for (int query = 0; query < (int)(q); ++query) { scanf( %s , qu); if (qu[0] == C ) { int Y, X; scanf( %d%d%s , &Y, &X, qu); s[Y][X] = qu[0]; if (Y & MASK) { Y &= ~MASK; Y += OFF; } for (int j = 1; j <= m; ++j) { int y = Y, x = j; go(y, x, Y - OFF); if (y != Y - OFF && y != 0 && x != 0 && x != m + 1) dy[Y][j] = -1; else { dy[Y][j] = y; dx[Y][j] = x; } } } else { int y, x; scanf( %d%d , &y, &x); if (y & MASK) { int upTo = y & ~MASK; go(y, x, upTo); if (y != upTo && y != 0 && x != 0 && x != m + 1) { printf( -1 -1 n ); continue; } } bool flag = false; while (y != 0 && x != 0 && x != m + 1) { int newY = dy[y][x]; x = dx[y][x]; y = newY; if (y == -1) { printf( -1 -1 n ); flag = true; break; } } if (flag) continue; printf( %d %d n , y, x); } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1010; void solve() { int n, m; cin >> n >> m; vector<vector<long long>> a = vector<vector<long long>>(n, vector<long long>(m, 0)); for (int i = 0; i < n; ++i) for (int j = 0; j < m; ++j) cin >> a[i][j]; vector<long long> col(m, 0), row(n, 0); for (int i = 0; i < m; ++i) for (int j = 0; j < n; ++j) col[i] += a[j][i]; for (int i = 0; i < n; ++i) for (int j = 0; j < m; ++j) row[i] += a[i][j]; vector<long long> x(m + 1), y(n + 1); long long mn = LLONG_MAX; long long ans = 0; int ansx = 0; for (int i = 0; i <= m; ++i) { long long curx = i * 4; for (int j = 0; j < m; ++j) { long long curpos = j * 4 + 2; long long dx = curx - curpos; x[i] += dx * dx * col[j]; } if (x[i] < mn) { mn = x[i]; ansx = i; } } ans += mn; mn = LLONG_MAX; int ansy = 0; for (int i = 0; i <= n; ++i) { int cury = i * 4; for (int j = 0; j < n; ++j) { long long curpos = j * 4 + 2; long long dy = cury - curpos; y[i] += dy * dy * row[j]; } if (y[i] < mn) { mn = y[i]; ansy = i; } } ans += mn; cout << ans << n ; cout << ansy << << ansx << n ; } int main(void) { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int tc = 1; while (tc--) { solve(); } } |
#include <bits/stdc++.h> using namespace std; int main() { int q, v; cin >> q; for (int i = 0; i < q; i++) { cin >> v; if (v == 2) cout << 2 << n ; else { if (v % 2) cout << 1 << n ; else cout << 0 << n ; } } } |
// file: system_clk_wiz_0_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1____25.000______0.000______50.0______312.659____245.713
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________125.000____________0.010
`timescale 1ps/1ps
module system_clk_wiz_0_0_clk_wiz
(// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
// Status and control signals
input resetn,
output locked
);
// Input buffering
//------------------------------------
IBUF clkin1_ibufg
(.O (clk_in1_system_clk_wiz_0_0),
.I (clk_in1));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_system_clk_wiz_0_0;
wire clkfbout_buf_system_clk_wiz_0_0;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
wire reset_high;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (5),
.CLKFBOUT_MULT_F (36.500),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (36.500),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (8.0))
mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_system_clk_wiz_0_0),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clk_out1_system_clk_wiz_0_0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1_unused),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_system_clk_wiz_0_0),
.CLKIN1 (clk_in1_system_clk_wiz_0_0),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_int),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (reset_high));
assign reset_high = ~resetn;
assign locked = locked_int;
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_system_clk_wiz_0_0),
.I (clkfbout_system_clk_wiz_0_0));
BUFG clkout1_buf
(.O (clk_out1),
.I (clk_out1_system_clk_wiz_0_0));
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; vector<pair<int, int>> v(n); vector<int> v2(k); for (int i = 0; i < n; i++) { cin >> v[i].first; v[i].second = i + 1; } sort(v.begin(), v.end()); int sum = 0; for (int i = 0; i < k; i++) { sum += v[n - 1 - i].first; v2[i] = v[n - 1 - i].second; } cout << sum << endl; sort(v2.begin(), v2.end()); for (int i = k - 1; i > 0; i--) { v2[i] = v2[i] - v2[i - 1]; } int cnt = 0; for (int i = 0; i < k - 1; i++) { cout << v2[i] << ; cnt += v2[i]; } cout << n - cnt; return 0; } |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_ab_e
//
// Generated
// by: wig
// on: Wed Aug 18 12:44:01 2004
// cmd: H:/work/mix_new/MIX/mix_0.pl -strip -nodelta ../../constant.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_ab_e.v,v 1.4 2005/10/06 11:16:04 wig Exp $
// $Date: 2005/10/06 11:16:04 $
// $Log: inst_ab_e.v,v $
// Revision 1.4 2005/10/06 11:16:04 wig
// Got testcoverage up, fixed generic problem, prepared report
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.45 2004/08/09 15:48:14 wig Exp
//
// Generator: mix_0.pl Revision: 1.32 ,
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_ab_e
//
// No `defines in this module
module inst_ab_e
//
// Generated module inst_ab
//
(
bus20040728_altop_o1,
bus20040728_o1,
bus20040728_o2,
bus20040728_top_o1,
bus20050930,
bus20050930_2,
bus20050930_3,
bus20050930_p7,
const_04,
const_08_p,
const_09_p,
const_10_2,
inst_duo_2
);
// Generated Module Inputs:
input [3:0] const_04;
input [4:0] const_08_p;
input [2:0] const_09_p;
input [3:0] const_10_2;
input [7:0] inst_duo_2;
// Generated Module Outputs:
output [3:0] bus20040728_altop_o1;
output [1:0] bus20040728_o1;
output bus20040728_o2;
output [3:0] bus20040728_top_o1;
output [4:0] bus20050930;
output [4:0] bus20050930_3;
output [5:0] bus20050930_2;
output bus20050930_p7;
// Generated Wires:
wire [3:0] bus20040728_altop_o1;
wire [1:0] bus20040728_o1;
wire bus20040728_o2;
wire [3:0] bus20040728_top_o1;
wire [4:0] bus20050930;
wire [4:0] bus20050930_3;
wire [5:0] bus20050930_2;
wire bus20050930_p7;
wire [3:0] const_04;
wire [4:0] const_08_p;
wire [2:0] const_09_p;
wire [3:0] const_10_2;
wire [7:0] inst_duo_2;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of inst_ab_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
// Model of FIFO in Altera
module fifo_1c_4k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
parameter width = 32;
parameter depth = 4096;
//`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req
input [31:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [31:0] q;
output rdfull;
output rdempty;
output [7:0] rdusedw;
output wrfull;
output wrempty;
output [7:0] wrusedw;
reg [width-1:0] mem [0:depth-1];
reg [7:0] rdptr;
reg [7:0] wrptr;
`ifdef rd_req
reg [width-1:0] q;
`else
wire [width-1:0] q;
`endif
reg [7:0] rdusedw;
reg [7:0] wrusedw;
integer i;
always @( aclr)
begin
wrptr <= #1 0;
rdptr <= #1 0;
for(i=0;i<depth;i=i+1)
mem[i] <= #1 0;
end
always @(posedge wrclk)
if(wrreq)
begin
wrptr <= #1 wrptr+1;
mem[wrptr] <= #1 data;
end
always @(posedge rdclk)
if(rdreq)
begin
rdptr <= #1 rdptr+1;
`ifdef rd_req
q <= #1 mem[rdptr];
`endif
end
`ifdef rd_req
`else
assign q = mem[rdptr];
`endif
// Fix these
always @(posedge wrclk)
wrusedw <= #1 wrptr - rdptr;
always @(posedge rdclk)
rdusedw <= #1 wrptr - rdptr;
endmodule // fifo_1c_4k
|
////////////////////////////////////////////////////////////////////////////////
// //
// This file is placed into the Public Domain, for any use, without warranty. //
// 2012 by Iztok Jeras //
// SPDX-License-Identifier: CC0-1.0 //
// //
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// //
// This testbench contains a bus source and a bus drain. The source creates //
// address and data bus values, while the drain is the final destination of //
// such pairs. All source and drain transfers are logged into memories, which //
// are used at the end of simulation to check for data transfer correctness. //
// Inside the RLT wrapper there is a multiplexer and a demultiplexer, they //
// bus transfers into a 8bit data stream and back. Both stream input and //
// output are exposed, they are connected together into a loopback. //
// //
// ----------- --------------------- //
// | bso_mem | | wrap | //
// ----------- | | //
// ----------- | | ----------- | //
// | bsi src | ------------> | -> | mux | -> | -> - sto //
// ----------- | ----------- | \ //
// | | | loopback //
// ----------- | ----------- | / //
// | bso drn | <------------ | <- | demux | <- | <- - sti //
// ----------- | | ----------- | //
// ----------- | | //
// | bso_mem | | | //
// ----------- --------------------- //
// //
// PROTOCOL: //
// //
// The 'vld' signal is driven by the source to indicate valid data is //
// available, 'rdy' is used by the drain to indicate is is ready to accept //
// valid data. A data transfer only happens if both 'vld' & 'rdy' are active. //
// //
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
// include RTL files
`include "t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv"
`include "t_sv_bus_mux_demux/sv_bus_mux_demux_demux.sv"
`include "t_sv_bus_mux_demux/sv_bus_mux_demux_mux.sv"
`include "t_sv_bus_mux_demux/sv_bus_mux_demux_wrap.sv"
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
parameter SIZ = 10;
// system signals
//logic clk = 1'b1; // clock
logic rst = 1'b1; // reset
integer rst_cnt = 0;
// input bus
logic bsi_vld; // valid (chip select)
logic [31:0] bsi_adr; // address
logic [31:0] bsi_dat; // data
logic bsi_rdy; // ready (acknowledge)
logic bsi_trn; // data transfer
logic [31:0] bsi_mem [SIZ];
// output stream
logic sto_vld; // valid (chip select)
logic [7:0] sto_bus; // data bus
logic sto_rdy; // ready (acknowledge)
// input stream
logic sti_vld; // valid (chip select)
logic [7:0] sti_bus; // data bus
logic sti_rdy; // ready (acknowledge)
// output bus
logic bso_vld; // valid (chip select)
logic [31:0] bso_adr; // address
logic [31:0] bso_dat; // data
logic bso_rdy; // ready (acknowledge)
logic bso_trn; // data transfer
logic [31:0] bso_mem [SIZ];
integer bso_cnt = 0;
////////////////////////////////////////////////////////////////////////////////
// clock and reset
////////////////////////////////////////////////////////////////////////////////
// clock toggling
//always #5 clk = ~clk;
// reset is removed after a delay
always @ (posedge clk)
begin
rst_cnt <= rst_cnt + 1;
rst <= rst_cnt <= 3;
end
// reset is removed after a delay
always @ (posedge clk)
if (bso_cnt == SIZ) begin
if (bsi_mem === bso_mem) begin $write("*-* All Finished *-*\n"); $finish(); end
else begin $display ("FAILED"); $stop(); end
end
////////////////////////////////////////////////////////////////////////////////
// input data generator
////////////////////////////////////////////////////////////////////////////////
// input data transfer
assign bsi_trn = bsi_vld & bsi_rdy;
// valid (for SIZ transfers)
always @ (posedge clk, posedge rst)
if (rst) bsi_vld = 1'b0;
else bsi_vld = (bsi_adr < SIZ);
// address (increments every transfer)
always @ (posedge clk, posedge rst)
if (rst) bsi_adr <= 32'h00000000;
else if (bsi_trn) bsi_adr <= bsi_adr + 'd1;
// data (new random value generated after every transfer)
always @ (posedge clk, posedge rst)
if (rst) bsi_dat <= 32'h00000000;
else if (bsi_trn) bsi_dat <= $random();
// storing transferred data into memory for final check
always @ (posedge clk)
if (bsi_trn) bsi_mem [bsi_adr] <= bsi_dat;
////////////////////////////////////////////////////////////////////////////////
// RTL instance
////////////////////////////////////////////////////////////////////////////////
sv_bus_mux_demux_wrap wrap (
// system signals
.clk (clk),
.rst (rst),
// input bus
.bsi_vld (bsi_vld),
.bsi_adr (bsi_adr),
.bsi_dat (bsi_dat),
.bsi_rdy (bsi_rdy),
// output stream
.sto_vld (sto_vld),
.sto_bus (sto_bus),
.sto_rdy (sto_rdy),
// input stream
.sti_vld (sti_vld),
.sti_bus (sti_bus),
.sti_rdy (sti_rdy),
// output bus
.bso_vld (bso_vld),
.bso_adr (bso_adr),
.bso_dat (bso_dat),
.bso_rdy (bso_rdy)
);
// stream output from mux is looped back into stream input for demux
assign sti_vld = sto_vld;
assign sti_bus = sto_bus;
assign sto_rdy = sti_rdy;
////////////////////////////////////////////////////////////////////////////////
// output data monitor
////////////////////////////////////////////////////////////////////////////////
// input data transfer
assign bso_trn = bso_vld & bso_rdy;
// output transfer counter used to end the test
always @ (posedge clk, posedge rst)
if (rst) bso_cnt <= 0;
else if (bso_trn) bso_cnt <= bso_cnt + 1;
// storing transferred data into memory for final check
always @ (posedge clk)
if (bso_trn) bso_mem [bso_adr] <= bso_dat;
// every output transfer against expected value stored in memory
always @ (posedge clk)
if (bso_trn && (bsi_mem [bso_adr] !== bso_dat))
$display ("@%08h i:%08h o:%08h", bso_adr, bsi_mem [bso_adr], bso_dat);
// ready is active for SIZ transfers
always @ (posedge clk, posedge rst)
if (rst) bso_rdy = 1'b0;
else bso_rdy = 1'b1;
endmodule
|
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for eth_mac_mii
*/
module test_eth_mac_mii;
// Parameters
parameter TARGET = "SIM";
parameter CLOCK_INPUT_STYLE = "BUFIO2";
parameter ENABLE_PADDING = 1;
parameter MIN_FRAME_LENGTH = 64;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] tx_axis_tdata = 0;
reg tx_axis_tvalid = 0;
reg tx_axis_tlast = 0;
reg tx_axis_tuser = 0;
reg mii_rx_clk = 0;
reg [3:0] mii_rxd = 0;
reg mii_rx_dv = 0;
reg mii_rx_er = 0;
reg mii_tx_clk = 0;
reg [7:0] ifg_delay = 0;
// Outputs
wire rx_clk;
wire rx_rst;
wire tx_clk;
wire tx_rst;
wire tx_axis_tready;
wire [7:0] rx_axis_tdata;
wire rx_axis_tvalid;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire [3:0] mii_txd;
wire mii_tx_en;
wire mii_tx_er;
wire tx_error_underflow;
wire rx_error_bad_frame;
wire rx_error_bad_fcs;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
tx_axis_tdata,
tx_axis_tvalid,
tx_axis_tlast,
tx_axis_tuser,
mii_rx_clk,
mii_rxd,
mii_rx_dv,
mii_rx_er,
mii_tx_clk,
ifg_delay
);
$to_myhdl(
rx_clk,
rx_rst,
tx_clk,
tx_rst,
tx_axis_tready,
rx_axis_tdata,
rx_axis_tvalid,
rx_axis_tlast,
rx_axis_tuser,
mii_txd,
mii_tx_en,
mii_tx_er,
tx_error_underflow,
rx_error_bad_frame,
rx_error_bad_fcs
);
// dump file
$dumpfile("test_eth_mac_mii.lxt");
$dumpvars(0, test_eth_mac_mii);
end
eth_mac_mii #(
.TARGET(TARGET),
.CLOCK_INPUT_STYLE(CLOCK_INPUT_STYLE),
.ENABLE_PADDING(ENABLE_PADDING),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH)
)
UUT (
.rst(rst),
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.mii_rx_clk(mii_rx_clk),
.mii_rxd(mii_rxd),
.mii_rx_dv(mii_rx_dv),
.mii_rx_er(mii_rx_er),
.mii_tx_clk(mii_tx_clk),
.mii_txd(mii_txd),
.mii_tx_en(mii_tx_en),
.mii_tx_er(mii_tx_er),
.tx_error_underflow(tx_error_underflow),
.rx_error_bad_frame(rx_error_bad_frame),
.rx_error_bad_fcs(rx_error_bad_fcs),
.ifg_delay(ifg_delay)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string s; int m; int a[100005] = {0}; int b[100005] = {0}; cin >> s; s = + s; cin >> m; for (int i = 1; i <= s.length(); i++) { if (s[i] == s[i + 1]) a[i] = 1; } for (int i = 1; i <= s.length(); i++) { b[i] = b[i - 1] + a[i]; } while (m--) { int l, r, flag = 0; cin >> l >> r; flag = b[r - 1] - b[l - 1]; cout << flag << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; static const int INF = 500000000; template <class T> void debug(T a, T b) { for (; a != b; ++a) cerr << *a << ; cerr << endl; } int n, w, b; const long long int mod = 1000000009; int C[4005][4005]; int main() { for (int i = 0; i < 4003; ++i) { C[i][0] = 1; for (int j = 0; j < i; ++j) C[i][j + 1] = (C[i - 1][j + 1] + C[i - 1][j]) % mod; } cin >> n >> w >> b; long long int res = 0; for (int l = 1; l < n - 1; ++l) for (int r = l + 1; r < n; ++r) { int len = r - l, wlen = n - len; if (b - len < 0 || w - wlen < 0) continue; res += C[b - 1][b - len] * (long long int)C[w - 1][w - wlen] % mod; res %= mod; } for (int i = 0; i < w; ++i) res = res * (i + 1) % mod; for (int i = 0; i < b; ++i) res = res * (i + 1) % mod; cout << res << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYGATE4SD1_SYMBOL_V
`define SKY130_FD_SC_HD__DLYGATE4SD1_SYMBOL_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlygate4sd1 (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYGATE4SD1_SYMBOL_V
|
module fourbitmux2X1ToRegToReg(out, x, y, sel, clk); wire _00_; wire _01_; wire _02_; wire _03_; wire _04_; wire _05_; wire _06_; wire _07_; wire [3:0] \_mux4_1.out ; input clk; output [3:0] out; wire [3:0] r1; input sel; input [3:0] x; input [3:0] y; DFFPOSX1 _08_ ( .CLK(clk), .D(r1[0]), .Q(out[0]) ); DFFPOSX1 _09_ ( .CLK(clk), .D(r1[1]), .Q(out[1]) ); DFFPOSX1 _10_ ( .CLK(clk), .D(r1[2]), .Q(out[2]) ); DFFPOSX1 _11_ ( .CLK(clk), .D(r1[3]), .Q(out[3]) ); DFFPOSX1 _12_ ( .CLK(clk), .D(\_mux4_1.out [0]), .Q(r1[0]) ); DFFPOSX1 _13_ ( .CLK(clk), .D(\_mux4_1.out [1]), .Q(r1[1]) ); DFFPOSX1 _14_ ( .CLK(clk), .D(\_mux4_1.out [2]), .Q(r1[2]) ); DFFPOSX1 _15_ ( .CLK(clk), .D(\_mux4_1.out [3]), .Q(r1[3]) ); INVX1 _16_ ( .A(x[0]), .Y(_00_) ); NAND2X1 _17_ ( .A(y[0]), .B(sel), .Y(_01_) ); OAI21X1 _18_ ( .A(sel), .B(_00_), .C(_01_), .Y(\_mux4_1.out [0]) ); INVX1 _19_ ( .A(x[1]), .Y(_02_) ); NAND2X1 _20_ ( .A(sel), .B(y[1]), .Y(_03_) ); OAI21X1 _21_ ( .A(sel), .B(_02_), .C(_03_), .Y(\_mux4_1.out [1]) ); INVX1 _22_ ( .A(x[2]), .Y(_04_) ); NAND2X1 _23_ ( .A(sel), .B(y[2]), .Y(_05_) ); OAI21X1 _24_ ( .A(sel), .B(_04_), .C(_05_), .Y(\_mux4_1.out [2]) ); INVX1 _25_ ( .A(x[3]), .Y(_06_) ); NAND2X1 _26_ ( .A(sel), .B(y[3]), .Y(_07_) ); OAI21X1 _27_ ( .A(sel), .B(_06_), .C(_07_), .Y(\_mux4_1.out [3]) );endmodule
|
#include <bits/stdc++.h> using namespace std; signed main() { ios_base::sync_with_stdio(0); cin.tie(0); long long ct; cin >> ct; while (ct--) { long long n, k; cin >> n >> k; vector<long long> a(n), was(n + 1), s; long long tmp = 0; for (long long i = 0; i < (n); ++i) { cin >> a[i]; if (!was[a[i]]) { tmp++; was[a[i]]++; } } if (tmp > k) { cout << -1 n ; } else { for (long long i = 1; i < (n + 1); ++i) { if (tmp < k and !was[i]) { s.push_back(i); tmp++; } if (was[i]) s.push_back(i); } cout << n * s.size() << n ; for (long long i = 0; i < (n); ++i) { for (long long j = 0; j < (s.size()); ++j) { cout << s[j] << ; } } cout << n ; } } } |
#include <bits/stdc++.h> using namespace std; int ball[100005]; int main() { int n, m; cin >> n >> m; if (m % 2) { int basket = m / 2; while (n--) { cout << basket + 1 << n ; basket = m - basket - 1; if (basket <= m / 2) basket--; if (basket < 0) basket = m / 2; } } else { int basket = m / 2 - 1; while (n--) { cout << basket + 1 << n ; basket = m - basket - 1; if (basket < m / 2) basket--; if (basket < 0) basket = m / 2 - 1; } } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFRBP_BLACKBOX_V
`define SKY130_FD_SC_HD__SDFRBP_BLACKBOX_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFRBP_BLACKBOX_V
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
* adjusted to FML 8x16 by Zeus Gomez Marmolejo <>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module hpdmc #(
parameter csr_addr = 1'b0,
/*
* The depth of the SDRAM array, in bytes.
* Capacity (in bytes) is 2^sdram_depth.
*/
parameter sdram_depth = 23,
/*
* The number of column address bits of the SDRAM.
*/
parameter sdram_columndepth = 8,
/*
* Address Mapping :
* | ROW ADDRESS | BANK NUMBER | COL ADDRESS | for 16-bit words
* |depth-1 coldepth+2|coldepth+1 coldepth|coldepth-1 0|
* (depth for 16-bit words, which is sdram_depth-1)
*/
parameter sdram_addrdepth = sdram_depth-1-1-(sdram_columndepth+2)+1
)(
input sys_clk,
input sys_rst,
/* Control interface */
input [2:0] csr_a,
input csr_we,
input [15:0] csr_di,
output [15:0] csr_do,
/* Simple FML 8x16 interface to the memory contents */
input [sdram_depth-1:0] fml_adr,
input fml_stb,
input fml_we,
output fml_ack,
input [1:0] fml_sel,
input [15:0] fml_di,
output [15:0] fml_do,
/* SDRAM interface.
* The SDRAM clock should be driven synchronously to the system clock.
* It is not generated inside this core so you can take advantage of
* architecture-dependent clocking resources to generate a clean
* differential clock.
*/
output reg sdram_cke,
output reg sdram_cs_n,
output reg sdram_we_n,
output reg sdram_cas_n,
output reg sdram_ras_n,
output reg [sdram_addrdepth-1:0] sdram_adr,
output reg [1:0] sdram_ba,
output [1:0] sdram_dqm,
inout [15:0] sdram_dq
);
/* Register all control signals, leaving the possibility to use IOB registers */
wire sdram_cke_r;
wire sdram_cs_n_r;
wire sdram_we_n_r;
wire sdram_cas_n_r;
wire sdram_ras_n_r;
wire [sdram_addrdepth-1:0] sdram_adr_r;
wire [1:0] sdram_ba_r;
always @(posedge sys_clk) begin
sdram_cke <= sdram_cke_r;
sdram_cs_n <= sdram_cs_n_r;
sdram_we_n <= sdram_we_n_r;
sdram_cas_n <= sdram_cas_n_r;
sdram_ras_n <= sdram_ras_n_r;
sdram_ba <= sdram_ba_r;
sdram_adr <= sdram_adr_r;
end
/* Mux the control signals according to the "bypass" selection.
* CKE always comes from the control interface.
*/
wire bypass;
wire sdram_cs_n_bypass;
wire sdram_we_n_bypass;
wire sdram_cas_n_bypass;
wire sdram_ras_n_bypass;
wire [sdram_addrdepth-1:0] sdram_adr_bypass;
wire [1:0] sdram_ba_bypass;
wire sdram_cs_n_mgmt;
wire sdram_we_n_mgmt;
wire sdram_cas_n_mgmt;
wire sdram_ras_n_mgmt;
wire [sdram_addrdepth-1:0] sdram_adr_mgmt;
wire [1:0] sdram_ba_mgmt;
assign sdram_cs_n_r = bypass ? sdram_cs_n_bypass : sdram_cs_n_mgmt;
assign sdram_we_n_r = bypass ? sdram_we_n_bypass : sdram_we_n_mgmt;
assign sdram_cas_n_r = bypass ? sdram_cas_n_bypass : sdram_cas_n_mgmt;
assign sdram_ras_n_r = bypass ? sdram_ras_n_bypass : sdram_ras_n_mgmt;
assign sdram_adr_r = bypass ? sdram_adr_bypass : sdram_adr_mgmt;
assign sdram_ba_r = bypass ? sdram_ba_bypass : sdram_ba_mgmt;
/* Control interface */
wire sdram_rst;
wire [2:0] tim_rp;
wire [2:0] tim_rcd;
wire tim_cas;
wire [10:0] tim_refi;
wire [3:0] tim_rfc;
wire [1:0] tim_wr;
hpdmc_ctlif #(
.csr_addr (csr_addr),
.sdram_addrdepth (sdram_addrdepth)
) ctlif (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.csr_a(csr_a),
.csr_we(csr_we),
.csr_di(csr_di),
.csr_do(csr_do),
.bypass(bypass),
.sdram_rst(sdram_rst),
.sdram_cke(sdram_cke_r),
.sdram_cs_n(sdram_cs_n_bypass),
.sdram_we_n(sdram_we_n_bypass),
.sdram_cas_n(sdram_cas_n_bypass),
.sdram_ras_n(sdram_ras_n_bypass),
.sdram_adr(sdram_adr_bypass),
.sdram_ba(sdram_ba_bypass),
.tim_rp(tim_rp),
.tim_rcd(tim_rcd),
.tim_cas(tim_cas),
.tim_refi(tim_refi),
.tim_rfc(tim_rfc),
.tim_wr(tim_wr)
);
/* SDRAM management unit */
wire mgmt_stb;
wire mgmt_we;
wire [sdram_depth-1-1:0] mgmt_address;
wire mgmt_ack;
wire read;
wire write;
wire [3:0] concerned_bank;
wire read_safe;
wire write_safe;
wire [3:0] precharge_safe;
hpdmc_mgmt #(
.sdram_depth(sdram_depth),
.sdram_columndepth(sdram_columndepth)
) mgmt (
.sys_clk(sys_clk),
.sdram_rst(sdram_rst),
.tim_rp(tim_rp),
.tim_rcd(tim_rcd),
.tim_refi(tim_refi),
.tim_rfc(tim_rfc),
.stb(mgmt_stb),
.we(mgmt_we),
.address(mgmt_address),
.ack(mgmt_ack),
.read(read),
.write(write),
.concerned_bank(concerned_bank),
.read_safe(read_safe),
.write_safe(write_safe),
.precharge_safe(precharge_safe),
.sdram_cs_n(sdram_cs_n_mgmt),
.sdram_we_n(sdram_we_n_mgmt),
.sdram_cas_n(sdram_cas_n_mgmt),
.sdram_ras_n(sdram_ras_n_mgmt),
.sdram_adr(sdram_adr_mgmt),
.sdram_ba(sdram_ba_mgmt)
);
/* Bus interface */
wire data_ack;
hpdmc_busif #(
.sdram_depth(sdram_depth)
) busif (
.sys_clk(sys_clk),
.sdram_rst(sdram_rst),
.fml_adr(fml_adr),
.fml_stb(fml_stb),
.fml_we(fml_we),
.fml_ack(fml_ack),
.mgmt_stb(mgmt_stb),
.mgmt_we(mgmt_we),
.mgmt_address(mgmt_address),
.mgmt_ack(mgmt_ack),
.data_ack(data_ack)
);
/* Data path controller */
wire direction;
wire direction_r;
hpdmc_datactl datactl(
.sys_clk(sys_clk),
.sdram_rst(sdram_rst),
.read(read),
.write(write),
.concerned_bank(concerned_bank),
.read_safe(read_safe),
.write_safe(write_safe),
.precharge_safe(precharge_safe),
.ack(data_ack),
.direction(direction),
.direction_r(direction_r),
.tim_cas(tim_cas),
.tim_wr(tim_wr)
);
/* Data path */
hpdmc_sdrio sdrio(
.sys_clk(sys_clk),
.direction(direction),
.direction_r(direction_r),
/* Bit meaning is the opposite between
* the FML selection signal and SDRAM DQM pins.
*/
.mo(~fml_sel),
.dout(fml_di),
.di(fml_do),
.sdram_dqm(sdram_dqm),
.sdram_dq(sdram_dq)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, cnt = 0; long long a[623456], b[623456], v[9999999]; int main() { cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; v[a[i]] = 1; } for (int i = 1; i <= n; i++) { cin >> b[i]; v[b[i]] = 1; } for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { long long x = a[i] ^ b[j]; if (v[x]) { cnt++; } } } if (cnt % 2 == 0) cout << Karen ; else cout << Koyomi ; } |
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 20 02:52:39 2016
/////////////////////////////////////////////////////////////
module GDA_St_N8_M8_P5 ( in1, in2, res );
input [7:0] in1;
input [7:0] in2;
output [8:0] res;
wire n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43,
n44, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55;
OA21X1TS U32 ( .A0(in1[3]), .A1(in2[3]), .B0(n30), .Y(n48) );
OAI2BB2XLTS U33 ( .B0(n50), .B1(n55), .A0N(in1[6]), .A1N(in2[6]), .Y(n41) );
CLKAND2X2TS U34 ( .A(in2[0]), .B(in1[0]), .Y(n42) );
NAND2X1TS U35 ( .A(n36), .B(n33), .Y(n44) );
OAI21X1TS U36 ( .A0(n38), .A1(n53), .B0(n45), .Y(n39) );
OAI21X1TS U37 ( .A0(in1[2]), .A1(in2[2]), .B0(n36), .Y(n52) );
NAND2X2TS U38 ( .A(in1[2]), .B(in2[2]), .Y(n36) );
XOR2X1TS U39 ( .A(n49), .B(n47), .Y(res[5]) );
NAND2X1TS U40 ( .A(n30), .B(n43), .Y(n31) );
NAND2X1TS U41 ( .A(n46), .B(n45), .Y(n47) );
NAND4XLTS U42 ( .A(n49), .B(n48), .C(in2[1]), .D(in1[1]), .Y(n51) );
OAI21X2TS U43 ( .A0(in1[4]), .A1(in2[4]), .B0(n45), .Y(n53) );
NAND2X1TS U44 ( .A(n35), .B(n34), .Y(n33) );
NAND2X1TS U45 ( .A(in1[4]), .B(in2[4]), .Y(n45) );
INVX2TS U46 ( .A(n53), .Y(n32) );
NAND2X1TS U47 ( .A(in1[3]), .B(in2[3]), .Y(n30) );
INVX2TS U48 ( .A(n52), .Y(n35) );
NAND2X1TS U49 ( .A(n48), .B(n44), .Y(n43) );
NAND2X1TS U50 ( .A(n32), .B(n31), .Y(n46) );
OA21XLTS U51 ( .A0(n32), .A1(n31), .B0(n46), .Y(res[4]) );
OA21XLTS U52 ( .A0(n35), .A1(n34), .B0(n33), .Y(res[2]) );
AOI2BB1XLTS U53 ( .A0N(in2[0]), .A1N(in1[0]), .B0(n42), .Y(res[0]) );
CLKXOR2X2TS U54 ( .A(in1[5]), .B(in2[5]), .Y(n49) );
INVX2TS U55 ( .A(n36), .Y(n37) );
AOI22X1TS U56 ( .A0(in1[3]), .A1(in2[3]), .B0(n37), .B1(n48), .Y(n38) );
AOI22X1TS U57 ( .A0(in1[5]), .A1(in2[5]), .B0(n49), .B1(n39), .Y(n50) );
NAND2X1TS U58 ( .A(in1[6]), .B(in2[6]), .Y(n40) );
OAI21X1TS U59 ( .A0(in1[6]), .A1(in2[6]), .B0(n40), .Y(n55) );
CMPR32X2TS U60 ( .A(in2[7]), .B(in1[7]), .C(n41), .CO(res[8]), .S(res[7]) );
CMPR32X2TS U61 ( .A(in1[1]), .B(in2[1]), .C(n42), .CO(n34), .S(res[1]) );
OA21XLTS U62 ( .A0(n48), .A1(n44), .B0(n43), .Y(res[3]) );
OAI31X1TS U63 ( .A0(n53), .A1(n52), .A2(n51), .B0(n50), .Y(n54) );
XNOR2X1TS U64 ( .A(n55), .B(n54), .Y(res[6]) );
initial $sdf_annotate("GDA_St_N8_M8_P5_syn.sdf");
endmodule
|
#include <bits/stdc++.h> using namespace std; int arr[200000], arr2[200000]; int main() { int n, i; long long sum = 0; scanf( %d , &n); for (i = 0; i < n; i++) { scanf( %d , &arr[i]); arr2[i] = arr[i] + arr2[i - 1]; } for (i = 0; i < n; i++) { if (arr[i] == 0) { sum += arr2[i]; } } cout << sum; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { string s; int m; cin >> s >> m; while (m--) { int l, r, k; cin >> l >> r >> k; int init = l - 1; int len = r - l + 1; string ns = s; for (int i = init; i < r; i++) { int pos = init + (i - init + k) % len; ns[pos] = s[i]; } s = ns; } cout << s << endl; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 200025; int n, m, i, j, t, k, s, mod, a[maxn], fat[maxn]; bool flg, vis[maxn << 1]; inline int Pow(int x, int y, int mo) { int ret = 1; while (y) { if (y & 1) ret = 1ll * ret * x % mo; x = 1ll * x * x % mo; y >>= 1; } return ret; } int father(int x) { return x == fat[x] ? x : fat[x] = father(fat[x]); } void solve(int delt) { for (i = 1; i <= n; ++i) fat[i] = i; for (i = 1; i <= n; ++i) { k = (a[i] - delt + mod) % mod; t = lower_bound(a + 1, a + n + 1, k) - a; if (a[t] == k) fat[father(t)] = father(i); } t = 0; for (i = 1; i <= n; ++i) { if (fat[i] == i) t++; else fat[i] = i; } delt = delt * 1ll * Pow(t, mod - 2, mod) % mod; for (i = 1; i <= n; ++i) { k = (a[i] - delt + mod) % mod; t = lower_bound(a + 1, a + n + 1, k) - a; if (a[t] == k) fat[father(t)] = father(i); } for (i = 2; i <= n; ++i) if (father(i) ^ father(1)) break; if (i > n) { for (i = 1; i <= n; ++i) { k = (a[i] - delt + mod) % mod; t = lower_bound(a + 1, a + n + 1, k) - a; if (a[t] != k) break; } if (i > n) { if (flg) printf( %d %d n , a[1], delt); else t = (1ll * n * delt + a[1]) % mod, printf( %d %d n , t, delt); } else { if (flg) printf( %d %d n , a[i], delt); else t = (1ll * n * delt + a[i]) % mod, printf( %d %d n , t, delt); } exit(0); } } int main() { scanf( %d%d , &mod, &n); for (i = 1; i <= n; ++i) scanf( %d , &a[i]); a[n + 1] = mod + 114514; if (n == 1 || n == mod) { printf( %d %d n , a[1], 1); return 0; } if (n == 2) { printf( %d %d n , a[1], (a[2] - a[1] + mod) % mod); return 0; } sort(a + 1, a + n + 1); flg = 1; if (2 * n > mod) { flg = 0; for (i = 1; i <= n; ++i) vis[a[i]] = 1; n = 0; for (i = 0; i < mod; ++i) if (!vis[i]) a[++n] = i; a[n + 1] = mod + 114514; if (n == 1) { printf( %d %d n , (a[1] + 1) % mod, 1); return 0; } } solve(a[2] - a[1]); solve((a[1] - a[2] + mod) % mod); puts( -1 ); return 0; } |
// VGA¿ØÖÆÄ£¿é ¸ù¾Ýµ±Ç°É¨Ãèµ½µÄµãÊÇÄÄÒ»²¿·ÖÊä³öÏàÓ¦ÑÕÉ«
module VGA_Control
(
input clk,
input rst,
input [1:0]snake,
input [5:0]apple_x,
input [4:0]apple_y,
output reg[9:0]x_pos,
output reg[9:0]y_pos,
output reg hsync,
output reg vsync,
output reg [11:0] color_out
);
reg [19:0]clk_cnt;
reg [9:0]line_cnt;
reg clk_25M;
localparam NONE = 2'b00;
localparam HEAD = 2'b01;
localparam BODY = 2'b10;
localparam WALL = 2'b11;
localparam HEAD_COLOR = 12'b1010_1111_0000;
localparam BODY_COLOR = 12'b0001_1111_1111;
reg [3:0]lox;
reg [3:0]loy;
always@(posedge clk or negedge rst) begin
if(rst) begin
clk_cnt <= 0;
line_cnt <= 0;
hsync <= 1;
vsync <= 1;
end
else begin
x_pos <= clk_cnt - 144;
y_pos <= line_cnt - 33;
if(clk_cnt == 0) begin
hsync <= 0;
clk_cnt <= clk_cnt + 1;
end
else if(clk_cnt == 96) begin
hsync <= 1;
clk_cnt <= clk_cnt + 1;
end
else if(clk_cnt == 799) begin
clk_cnt <= 0;
line_cnt <= line_cnt + 1;
end
else clk_cnt <= clk_cnt + 1;
if(line_cnt == 0) begin
vsync <= 0;
end
else if(line_cnt == 2) begin
vsync <= 1;
end
else if(line_cnt == 521) begin
line_cnt <= 0;
vsync <= 0;
end
if(x_pos >= 0 && x_pos < 640 && y_pos >= 0 && y_pos < 480) begin
lox = x_pos[3:0];
loy = y_pos[3:0];
if(x_pos[9:4] == apple_x && y_pos[9:4] == apple_y)
case({loy,lox})
8'b0000_0000:color_out = 12'b0000_0000_0000;
default:color_out = 12'b0000_0000_1111;
endcase
else if(snake == NONE)
color_out = 12'b0000_0000_0000;
else if(snake == WALL)
color_out = 3'b101;
else if(snake == HEAD|snake == BODY) begin //¸ù¾Ýµ±Ç°É¨Ãèµ½µÄµãÊÇÄÄÒ»²¿·ÖÊä³öÏàÓ¦ÑÕÉ«
case({lox,loy})
8'b0000_0000:color_out = 12'b0000_0000_0000;
default:color_out = (snake == HEAD) ? HEAD_COLOR : BODY_COLOR;
endcase
end
end
else
color_out = 12'b0000_0000_0000;
end
end
endmodule |
#include <bits/stdc++.h> int f[100005]; int g[100005]; int h[1000005]; int v[100005]; int main() { int n, m = 0; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &f[i]); } for (int i = 1; i <= n; i++) { if (v[i] == 0) { if (f[i] == i) { m++; h[m] = i; v[i] = m; g[i] = m; } else { if (v[f[i]] == 0) { if (f[f[i]] == f[i]) { m++; h[m] = f[i]; v[f[i]] = m; g[f[i]] = m; g[i] = m; } else { puts( -1 ); return 0; } } else { g[i] = v[f[i]]; } } } } printf( %d n , m); for (int i = 1; i <= n; i++) { printf( %d , g[i]); } puts( ); for (int i = 1; i <= m; i++) { printf( %d , h[i]); } return 0; } |
#include <bits/stdc++.h> using namespace std; void solve() { int n,i,j=2,x,m,d,k; cin >> n; if(n%2==1) {cout << NO << endl;return;} while(j<1000000009 && j<=n) { if(n==j) { // cout << loop << endl; cout << YES << endl; return; } //cout << n << << j << endl; j*=2; } n=n/2; j=sqrt(n); if(j*j < n){ if(n%2==1) { cout << NO << endl;return; } n/=2; j=sqrt(n); if(j*j < n) { cout << NO << endl;return; } else { { cout << YES << endl;return; } } } //if(j%2==1) {cout << NO << endl;return;} cout << YES << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t=1; cin >> t; while(t--) solve(); } |
#include <bits/stdc++.h> using namespace std; int n; struct hh { int t, nxt; } edge[1000020 << 1]; int head[1000020], ecnt; void make_edge(int f, int t) { edge[++ecnt] = (hh){t, head[f]}; head[f] = ecnt; edge[++ecnt] = (hh){f, head[t]}; head[t] = ecnt; } int dep[1000020], size[1000020], son[1000020], fa[1000020]; void dfs1(int x, int fa) { dep[x] = dep[fa] + 1; size[x] = 1; for (int i = head[x]; i; i = edge[i].nxt) if (edge[i].t != fa) { dfs1(edge[i].t, x); size[x] += size[edge[i].t]; if (size[edge[i].t] > size[son[x]]) son[x] = edge[i].t; } } map<string, int> S[1000020]; int sum[1000020]; string a[1000020]; bool s[1000020]; void add(string s, int d, int t) { if (!S[d][s]) ++sum[d]; S[d][s] += t; if (!S[d][s]) --sum[d]; } void add(int x, int fa, int t) { add(a[x], dep[x], t); for (int i = head[x]; i; i = edge[i].nxt) if (edge[i].t != fa && !s[edge[i].t]) add(edge[i].t, x, t); } vector<pair<int, int> > q[1000020]; int ans[1000020]; void dfs2(int x, int fa, bool keep) { for (int i = head[x]; i; i = edge[i].nxt) if (edge[i].t != fa && edge[i].t != son[x]) dfs2(edge[i].t, x, 0); s[son[x]] = 1; if (son[x]) dfs2(son[x], x, 1); add(x, fa, 1); for (int i = 0; i < (int)q[x].size(); i++) ans[q[x][i].first] = sum[q[x][i].second]; s[son[x]] = 0; if (!keep) add(x, fa, -1); } int main() { ios::sync_with_stdio(false); int i, x, y, m; cin >> n; for (i = 1; i <= n; i++) { cin >> a[i] >> fa[i]; if (fa[i]) make_edge(fa[i], i); } for (i = 1; i <= n; i++) if (!fa[i]) dfs1(i, 0); cin >> m; for (i = 1; i <= m; i++) { cin >> x >> y; q[x].push_back(make_pair(i, dep[x] + y)); } for (i = 1; i <= n; i++) if (!fa[i]) dfs2(i, 0, 0); for (i = 1; i <= m; i++) printf( %d n , ans[i]); } |
#include <bits/stdc++.h> using namespace std; int main() { long long int i, j, n, k, s, min, max; cin >> n >> k; if (k % n) cout << k / n + 1; else cout << k / n; return 0; } |
// Copyright (c) 2000-2011 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision$
// $Date$
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
// Dual-Ported BRAM (WRITE FIRST)
module BRAM2(CLKA,
ENA,
WEA,
ADDRA,
DIA,
DOA,
CLKB,
ENB,
WEB,
ADDRB,
DIB,
DOB
);
parameter PIPELINED = 0;
parameter ADDR_WIDTH = 1;
parameter DATA_WIDTH = 1;
parameter MEMSIZE = 1;
input CLKA;
input ENA;
input WEA;
input [ADDR_WIDTH-1:0] ADDRA;
input [DATA_WIDTH-1:0] DIA;
output [DATA_WIDTH-1:0] DOA;
input CLKB;
input ENB;
input WEB;
input [ADDR_WIDTH-1:0] ADDRB;
input [DATA_WIDTH-1:0] DIB;
output [DATA_WIDTH-1:0] DOB;
(* RAM_STYLE = "BLOCK" *)
reg [DATA_WIDTH-1:0] RAM[0:MEMSIZE-1] /* synthesis syn_ramstyle="no_rw_check" */ ;
reg [DATA_WIDTH-1:0] DOA_R;
reg [DATA_WIDTH-1:0] DOB_R;
reg [DATA_WIDTH-1:0] DOA_R2;
reg [DATA_WIDTH-1:0] DOB_R2;
`ifdef BSV_NO_INITIAL_BLOCKS
`else
// synopsys translate_off
integer i;
initial
begin : init_block
for (i = 0; i < MEMSIZE; i = i + 1) begin
RAM[i] = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
DOA_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DOB_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DOA_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DOB_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
// synopsys translate_on
`endif // !`ifdef BSV_NO_INITIAL_BLOCKS
always @(posedge CLKA) begin
if (ENA) begin
if (WEA) begin
RAM[ADDRA] <= `BSV_ASSIGNMENT_DELAY DIA;
DOA_R <= `BSV_ASSIGNMENT_DELAY DIA;
end
else begin
DOA_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRA];
end
end
DOA_R2 <= `BSV_ASSIGNMENT_DELAY DOA_R;
end
always @(posedge CLKB) begin
if (ENB) begin
if (WEB) begin
RAM[ADDRB] <= `BSV_ASSIGNMENT_DELAY DIB;
DOB_R <= `BSV_ASSIGNMENT_DELAY DIB;
end
else begin
DOB_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRB];
end
end
DOB_R2 <= `BSV_ASSIGNMENT_DELAY DOB_R;
end
// Output drivers
assign DOA = (PIPELINED) ? DOA_R2 : DOA_R;
assign DOB = (PIPELINED) ? DOB_R2 : DOB_R;
endmodule // BRAM2
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n, m, mn, mx; cin >> n >> m >> mn >> mx; set<int> temp; for (int i = 0; i < m; ++i) { int x; cin >> x; temp.insert(x); } if (*temp.begin() < mn or *temp.rbegin() > mx) { cout << Incorrect << endl; return 0; } int off = 0; if (*temp.begin() != mn) off++; if (*temp.rbegin() != mx) off++; if (n - m >= off) { cout << Correct << endl; } else { cout << Incorrect << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e6 + 10; int vis[maxn]; vector<int> e[maxn]; vector<int> w[maxn]; int a[maxn]; int ans; void add_edge(int u, int v, int ww) { e[u].push_back(v); e[v].push_back(u); w[u].push_back(ww); w[v].push_back(ww); } void dfs(int num, int l, int c) { if (l > a[num] && c != 1) { c = 1; } if (c == 1) { ans++; } vis[num] = 1; int cc = e[num].size(); for (int i = 0; i < cc; i++) { if (!vis[e[num][i]]) { if (l < 0) l = 0; vis[e[num][i]] = 1; dfs(e[num][i], l + w[num][i], c); } } } int main() { memset(vis, 0, sizeof(vis)); int n; scanf( %d , &n); ans = 0; for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int i = 2; i <= n; i++) { int u = i, v, ww; scanf( %d%d , &v, &ww); add_edge(u, v, ww); } ans = 0; dfs(1, 0, 0); printf( %d n , ans); } |
#include <bits/stdc++.h> using namespace std; const int maxn = 3e3 + 5; int n, m; vector<int> g[maxn]; long long dis[maxn][maxn]; vector<pair<long long, long long> > from[maxn], to[maxn]; void bfs(int x) { queue<int> q; q.push(x); dis[x][x] = 0; while (!q.empty()) { int now = q.front(); q.pop(); for (int i : g[now]) { if (dis[x][i] == -1) { dis[x][i] = dis[x][now] + 1; q.push(i); } } } } int main() { memset(dis, -1, sizeof(dis)); scanf( %d%d , &n, &m); for (int u, v, i = 1; i <= m; i++) { scanf( %d%d , &u, &v); g[u].push_back(v); } for (int i = 1; i <= n; i++) bfs(i); for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { from[i].push_back({dis[i][j], j}); to[j].push_back({dis[i][j], i}); } } for (int i = 1; i <= n; i++) { sort(from[i].begin(), from[i].end(), greater<pair<long long, long long> >()); sort(to[i].begin(), to[i].end(), greater<pair<long long, long long> >()); } int a, b, c, d, cnt = 0; for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { if (i == j || dis[i][j] == -1) continue; for (int k = 0; k < 4; k++) { if (to[i][k].second == j || to[i][k].second == i) continue; for (int l = 0; l < 4; l++) { if (from[j][l].second == i || from[j][l].second == to[i][k].second || from[j][l].second == j) continue; if (to[i][k].first == -1 || from[j][l].first == -1) continue; long long now = dis[i][j] + to[i][k].first + from[j][l].first; if (now > cnt) { cnt = now; a = to[i][k].second, b = i, c = j, d = from[j][l].second; } } } } } printf( %d %d %d %d n , a, b, c, d); return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build Mon Oct 10 19:07:27 MDT 2016
// Date : Thu Sep 14 10:23:02 2017
// Host : PC4719 running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_0_stub.v
// Design : vio_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "vio,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe_in0, probe_in1, probe_in2, probe_in3,
probe_out0, probe_out1)
/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[0:0],probe_in1[0:0],probe_in2[0:0],probe_in3[0:0],probe_out0[0:0],probe_out1[0:0]" */;
input clk;
input [0:0]probe_in0;
input [0:0]probe_in1;
input [0:0]probe_in2;
input [0:0]probe_in3;
output [0:0]probe_out0;
output [0:0]probe_out1;
endmodule
|
#include <bits/stdc++.h> using namespace std; mt19937 rd(time(0)); vector<long long> v(100010), val(100010), con[100010], st(100010, 0), en(100010, 0), d(100010, 0); pair<long long, long long> t[20][100010]; long long cur = 0; void dfs(long long node, long long par, long long dep) { st[node] = ++cur; d[st[node]] = dep; for (auto i : con[node]) { if (i != par) dfs(i, node, dep + 1); } en[node] = cur; } void build(long long c, long long l, long long r) { if (l == r) t[c][l] = {d[l], val[l]}; else { long long mid = (l + r) / 2; build(c + 1, l, mid); build(c + 1, mid + 1, r); long long i = l, j = mid + 1, k = l; while (i <= mid && j <= r) { if (t[c + 1][i].first < t[c + 1][j].first) t[c][k++] = t[c + 1][i++]; else t[c][k++] = t[c + 1][j++]; } while (i <= mid) t[c][k++] = t[c + 1][i++]; while (j <= r) t[c][k++] = t[c + 1][j++]; for (i = l + 1; i <= r; i++) t[c][i].second = min(t[c][i].second, t[c][i - 1].second); } } long long query(long long c, long long l, long long r, long long l1, long long r1, long long k) { if (r1 < l || l1 > r) return 1000000007; if (l >= l1 && r <= r1) { pair<long long, long long> temp = {k, 1000000007}; long long w = upper_bound(t[c] + l, t[c] + r + 1, temp) - (t[c]); if (w == l) return 1000000007; return t[c][w - 1].second; } else { long long mid = (l + r) / 2; return min(query(c + 1, l, mid, l1, r1, k), query(c + 1, mid + 1, r, l1, r1, k)); } } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n, r, m, l, x, k; cin >> n >> r; for (long long i = 1; i < n + 1; i++) cin >> v[i]; for (long long i = 0; i < n - 1; i++) { long long u, v; cin >> u >> v; con[u].push_back(v); con[v].push_back(u); } dfs(r, -1, 0); for (long long i = 1; i <= n; i++) val[st[i]] = v[i]; build(1, 1, cur); cin >> m; l = 0; while (m--) { cin >> x >> k; x = (x + l) % n + 1; k = (k + l) % n; l = query(1, 1, cur, st[x], en[x], k + d[st[x]]); cout << l << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T> T sqr(T x) { return x * x; } template <typename T> T abs(T x) { return x > 0 ? x : -x; } int cur = 0; string get_next() { string ans = ; if (cur >= 26) { ans = B ; } else { ans = A ; } ans += (char)( a + cur % 26); cur++; return ans; } int main() { int n, k; cin >> n >> k; vector<bool> used(n - k + 1); for (int i = 0; i < n - k + 1; i++) { string s; cin >> s; if (s == NO ) { used[i] = true; } } vector<string> ans(n); for (int i = 0; i < n; i++) { if (i >= k - 1 && used[i - k + 1]) { ans[i] = ans[i - k + 1]; } else { ans[i] = get_next(); } } for (int i = 0; i < n; i++) { cout << ans[i] << ; } cout << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; string m[10]; bool win(int i, int j, int x, int y) { int X = 0; int O = 0; int D = 0; for (int c = 0; c < 5 && i >= 0 && i < 10 && j >= 0 && j < 10; i += x, j += y, c++) { if (m[i][j] == X ) { X++; } else if (m[i][j] == O ) { O++; } else { D++; } } return X == 4 && D == 1; } int main() { ios_base::sync_with_stdio(0); for (int i = 0; i < 10; i++) { cin >> m[i]; } for (int i = 0; i < 10; i++) { for (int j = 0; j < 10; j++) { if (m[i][j] == X ) { for (int kx = -1; kx < 2; kx++) { for (int ky = -1; ky < 2; ky++) { if (kx == 0 && ky == 0) continue; if (win(i, j, kx, ky)) { cout << YES ; return 0; } } } } } } cout << NO ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int inf = ~0u >> 2; const int N = 500010; int Max[N << 2]; struct node { int x, y, z; } in[N]; int tot, n; int num[N]; int max(int a, int b) { return a > b ? a : b; } void pushup(int rt) { Max[rt] = max(Max[rt << 1], Max[rt << 1 | 1]); } void build(int l, int r, int rt) { Max[rt] = 0; if (l == r) return; int m = (l + r) >> 1; build(l, m, rt << 1); build(m + 1, r, rt << 1 | 1); } void update(int p, int val, int l, int r, int rt) { if (l == r) { if (val > Max[rt]) Max[rt] = val; return; } int m = (l + r) >> 1; if (p <= m) update(p, val, l, m, rt << 1); else update(p, val, m + 1, r, rt << 1 | 1); pushup(rt); } int query(int L, int R, int l, int r, int rt) { if (L <= l && r <= R) return Max[rt]; int m = (l + r) >> 1; int ret = 0; if (L <= m) ret = max(ret, query(L, R, l, m, rt << 1)); if (R > m) ret = max(ret, query(L, R, m + 1, r, rt << 1 | 1)); return ret; } void init() { sort(num + 1, num + n + 1); tot = unique(num + 1, num + n + 1) - num - 1; build(1, tot, 1); for (int i = 1; i <= n; i++) in[i].x = lower_bound(num + 1, num + 1 + tot, in[i].x) - num; } inline int cmp(node a, node b) { return a.y > b.y; } int main() { int i, j, k; scanf( %d , &n); for (i = 1; i <= n; i++) { scanf( %d , &in[i].x); num[i] = in[i].x; } for (i = 1; i <= n; i++) scanf( %d , &in[i].y); for (i = 1; i <= n; i++) scanf( %d , &in[i].z); init(); sort(in + 1, in + n + 1, cmp); int ans = 0; for (i = 1; i <= n; i = j) { for (j = i; j <= n && in[j].y == in[i].y; j++) { int z; z = query(in[j].x + 1, tot, 1, tot, 1); if (z > in[j].z) ans++; } for (; i <= j - 1; i++) { update(in[i].x, in[i].z, 1, tot, 1); } } printf( %d n , ans); return 0; } |
//////////////////////////////////////////////////////////////////////////////////
//
// This file is part of the N64 RGB/YPbPr DAC project.
//
// Copyright (C) 2015-2021 by Peter Bartmann <>
//
// N64 RGB/YPbPr DAC is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//////////////////////////////////////////////////////////////////////////////////
//
// Company: Circuit-Board.de
// Engineer: borti4938
//
// Module Name: n64a_vdemux
// Project Name: N64 Advanced RGB/YPbPr DAC Mod
// Target Devices: Cyclone IV and Cyclone 10 LP devices
// Tool versions: Altera Quartus Prime
// Description: demux the video data from the input data stream
//
// Dependencies: vh/n64a_params.vh
//
//////////////////////////////////////////////////////////////////////////////////
module n64a_vdemux(
VCLK,
nVDSYNC,
nRST,
VD_i,
demuxparams_i,
vdata_valid_0,
vdata_r_sy_0,
vdata_valid_1,
vdata_r_1
);
`include "vh/n64adv_vparams.vh"
input VCLK;
input nVDSYNC;
input nRST;
input [color_width_i-1:0] VD_i;
input [ 2:0] demuxparams_i;
output reg vdata_valid_0 = 1'b0;
output [`VDATA_I_SY_SLICE] vdata_r_sy_0;
output reg vdata_valid_1 = 1'b0;
output reg [`VDATA_I_FU_SLICE] vdata_r_1 = {vdata_width_i{1'b0}}; // (unpacked array types in ports requires system verilog)
// unpack demux info
wire palmode = demuxparams_i[ 2];
wire ndo_deblur = demuxparams_i[ 1];
wire n16bit_mode = demuxparams_i[ 0];
wire posedge_nCSYNC = !vdata_r_0[3*color_width_i] & VD_i[0];
// start of rtl
reg [1:0] data_cnt = 2'b00;
reg nblank_rgb = 1'b1;
reg [`VDATA_I_FU_SLICE] vdata_r_0 = {vdata_width_i{1'b0}}; // buffer for sync, red, green and blue
always @(posedge VCLK or negedge nRST) // data register management
if (!nRST)
data_cnt <= 2'b00;
else begin
if (!nVDSYNC)
data_cnt <= 2'b01; // reset data counter
else
data_cnt <= data_cnt + 1'b1; // increment data counter
end
always @(posedge VCLK or negedge nRST)
if (!nRST) begin
nblank_rgb <= 1'b1;
end else if (!nVDSYNC) begin
if (ndo_deblur) begin
nblank_rgb <= 1'b1;
end else begin
if(posedge_nCSYNC) // posedge nCSYNC -> reset blanking
nblank_rgb <= palmode;
else
nblank_rgb <= ~nblank_rgb;
end
end
always @(posedge VCLK or negedge nRST) // data register management
if (!nRST) begin
vdata_valid_0 <= 1'b0;
vdata_r_0 <= {vdata_width_i{1'b0}};
vdata_valid_1 <= 1'b0;
vdata_r_1 <= {vdata_width_i{1'b0}};
end else begin
vdata_valid_0 <= 1'b0;
vdata_valid_1 <= 1'b0;
if (!nVDSYNC) begin
vdata_valid_1 <= 1'b1; // set also valid flag for
// shift data to output registers
vdata_r_1[`VDATA_I_SY_SLICE] <= vdata_r_0[`VDATA_I_SY_SLICE];
if (nblank_rgb) // deblur active: pass RGB only if not blanked
vdata_r_1[`VDATA_I_CO_SLICE] <= vdata_r_0[`VDATA_I_CO_SLICE];
// get new sync data
vdata_valid_0 <= 1'b1;
vdata_r_0[`VDATA_I_SY_SLICE] <= VD_i[3:0];
end else begin
// demux of RGB
case(data_cnt)
2'b01: vdata_r_0[`VDATA_I_RE_SLICE] <= n16bit_mode ? VD_i : {VD_i[6:2], 2'b00};
2'b10: vdata_r_0[`VDATA_I_GR_SLICE] <= n16bit_mode ? VD_i : {VD_i[6:1], 1'b0};
2'b11: vdata_r_0[`VDATA_I_BL_SLICE] <= n16bit_mode ? VD_i : {VD_i[6:2], 2'b00};
endcase
end
end
assign vdata_r_sy_0 = vdata_r_0[`VDATA_I_SY_SLICE];
endmodule
|
#include<bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; using pint = pair<int, int>; using pll = pair<ll, ll>; int main(){ int t; cin >> t; while(t--){ int k, n, m; cin >> k >> n >> m; queue<int> a, b; int size = k; for(int i = 0; i < n; i++){ int x; cin >> x; a.push(x); } for(int j = 0; j < m; j++){ int x; cin >> x; b.push(x); } bool ok = true; vector<int> ans; while(!a.empty() && !b.empty()){ int op; if(a.front() < b.front()){ op = a.front(); a.pop(); } else{ op = b.front(); b.pop(); } if(op == 0)size++; else{ if(op > size){ ok = false; break; } } ans.push_back(op); } if(ok){ int op; while(!a.empty()){ op = a.front(); a.pop(); if(op == 0)size++; else{ if(op > size){ ok = false; break; } } ans.push_back(op); } while(!b.empty()){ op = b.front(); b.pop(); if(op == 0)size++; else{ if(op > size){ ok = false; break; } } ans.push_back(op); } } if(ok){ for(int i = 0; i < ans.size(); i++)cout << ans[i] << ; cout << endl; } else{ cout << -1 << endl; } } } |
#include <bits/stdc++.h> using namespace std; template <class L, class R> ostream &operator<<(ostream &os, pair<L, R> P) { return os << ( << P.first << , << P.second << ) ; } template <class T> ostream &operator<<(ostream &os, vector<T> V) { os << [ ; for (auto vv : V) os << vv << , ; return os << ] ; } template <class TH> void _dbg(const char *sdbg, TH h) { cerr << sdbg << = << h << n ; } template <class TH, class... TA> void _dbg(const char *sdbg, TH h, TA... a) { while (*sdbg != , ) cerr << *sdbg++; cerr << = << h << , ; _dbg(sdbg + 1, a...); } const long long N = 4e5 + 7; long long n, a[N], pre[N], ansLen, ansIdx; double ans = -1.0; double sum(long long l, long long r) { return pre[r] - (l > 0 ? pre[l - 1] : 0); } double f(long long len, long long idx) { double ret = pre[idx] - pre[idx - len - 1]; ret += pre[n] - pre[n - len]; ret /= len + len + 1; ret -= a[idx]; if (ret > ans) { ans = ret; ansIdx = idx; ansLen = len; } return ret; } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; cin >> n; for (long long i = 1; i <= n; i++) cin >> a[i]; sort(a + 1, a + n + 1); for (long long i = 1; i <= n; i++) pre[i] = a[i] + pre[i - 1]; for (long long i = 1; i <= n; i++) { long long cnt = min(i - 1, n - i); long long lo = 0, hi = cnt; while (hi - lo > 3) { long long m1 = lo + (hi - lo) / 3, m2 = hi - (hi - lo) / 3; if (f(m1, i) < f(m2, i)) lo = m1; else hi = m2; } for (long long k = lo; k <= hi; k++) f(k, i); } cout << 2 * ansLen + 1 << n ; for (long long i = ansIdx; i >= ansIdx - ansLen; i--) cout << a[i] << ; for (long long i = n - ansLen + 1; i <= n; i++) cout << a[i] << ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int sMAX = 10010; const int MAX = 114514; const long long bMAX = 1919180; int main() { int t; cin >> t; while (t--) { string zs; cin >> zs; int ans = zs.size() + 1; int m[4] = {0, 0, 0, 0}; for (int i = 0; i < zs.size(); i++) { m[zs[i] - 0 ] = i + 1; if (m[1] && m[2] && m[3]) { int gsb = min(m[1], m[2]); ans = min(ans, max(m[1], max(m[2], m[3])) - min(gsb, m[3]) + 1); } } if (ans == zs.size() + 1) { cout << 0 << endl; } else cout << ans << endl; } return 0; } |
/*
* support_dma - processes DMA on the support memory
*
* Used for uploading code to the suport CPU
*
* Part of the CPC2 project: http://intelligenttoasters.blog
*
* Copyright (C)2017
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you can find a copy here:
* https://www.gnu.org/licenses/gpl-3.0.en.html
*
*/
`timescale 1ns/1ns
module support_dma (
input clk_i,
input enable_i, // When this goes high, it resets the state machine to first state
input d_avail_i, // Goes high when data is available
input [7:0] data_i,
output [15:0] adr_o, // DMA address
output [7:0] data_o,
output wr_o, // To memory
output rd_o, // To SPI
output n_reset_o // To clear the UART before starting
);
// Wire definitions ===========================================================================
// Registers ==================================================================================
reg [2:0] state = 3'd0;
reg [15:0] address = 0;
reg mem_wr = 0;
reg inbound_rd = 0, d_avail = 0;
reg n_reset = 1;
// Assignments ================================================================================
assign rd_o = inbound_rd;
assign data_o = data_i;
assign n_reset_o = n_reset;
//TESTING assign adr_o = {4'b1110,address[11:0]};
assign adr_o = address;
assign wr_o = mem_wr;
// Module connections =========================================================================
always @( posedge clk_i ) d_avail <= d_avail_i; // d_avail is set on negedge
// Simulation branches and control ============================================================
always @(negedge clk_i)
begin
case (state)
0 :begin
address <= 16'd0;
mem_wr <= 0;
inbound_rd <= 0;
if( enable_i ) state <= 3'd1;
end
1 :begin
n_reset <= 0;
state <= 3'd2;
end
2 :begin
n_reset <= 1; // Reset going high will update fifo counters, so wait another step
state <= 3'd3; // For the d_avail_i to be updated
end
3 :begin
if( !enable_i )
state <= 3'd0;
else
if( d_avail )
state <= 3'd4;
end
4 :begin
inbound_rd <= 1'b1; // read takes effect immediately
state <= 3'd5;
end
5 :begin
inbound_rd <= 1'b0;
mem_wr <= 1'b1; // Write only takes effect on next clock posedge
state <= 3'd6;
end
6 :begin
mem_wr <= 1'd0;
state <= 3'd7;
end
7 :begin
address <= address + 1'b1;
state <= 3'd3;
end
default:
state <= 3'd0;
endcase
end
// Other logic ================================================================================
endmodule
|
#include <bits/stdc++.h> using namespace std; int x, y; char a[1001][1001]; int n, c[1000000], ni[5001][5001]; bool vis[1001][1001], b[1000000]; int e[] = {1, -1, 0, 0}; int r[] = {0, 0, -1, 1}; void dfs(int i, int j, int n) { vis[i][j] = true; ni[i][j] = n; c[n]++; for (int g = 0; g < 4; g++) { int z = i + e[g], k = j + r[g]; if (a[z][k] == . && z >= 0 && z < x && k >= 0 && k < y && vis[z][k] == false) dfs(z, k, n); } } int main() { scanf( %d%d , &x, &y); for (int i = 0; i < x; i++) scanf( %s , &a[i]); int g = 1; for (int i = 0; i < x; i++) { for (int j = 0; j < y; j++) { if (a[i][j] == . && vis[i][j] == false) { dfs(i, j, g); g++; } } } for (int i = 0; i < x; i++) { for (int j = 0; j < y; j++) { if (a[i][j] == * ) { int sum = 1; for (int k = 0; k < 4; k++) { int z = i + e[k], d = j + r[k]; if (a[z][d] == . && b[ni[z][d]] == false && z >= 0 && z < x && d >= 0 && d < y) { sum += c[ni[z][d]]; b[ni[z][d]] = true; } } a[i][j] = sum % 10 + 48; for (int k = 0; k < 4; k++) { int z = i + e[k], d = j + r[k]; if (z >= 0 && z < x && d >= 0 && d < y && a[z][d] == . ) { b[ni[z][d]] = false; } } } } } for (int i = 0; i < x; i++) { for (int j = 0; j < y; j++) { printf( %c , a[i][j]); } cout << endl; } } |
/* This file is part of JT12.
JT12 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 21-03-2019
*/
// ADPCM-B counter
module jt10_adpcmb_cnt(
input rst_n,
input clk, // CPU clock
input cen, // clk & cen = 55 kHz
// counter control
input [15:0] delta_n,
input clr,
input on,
input acmd_up_b,
// Address
input [15:0] astart,
input [15:0] aend,
input arepeat,
output reg [23:0] addr,
output reg nibble_sel,
// Flag
output reg chon,
output reg flag,
input clr_flag,
output reg restart,
output reg adv
);
// Counter
reg [15:0] cnt;
always @(posedge clk or negedge rst_n)
if(!rst_n) begin
cnt <= 'd0;
adv <= 'b0;
end else if(cen) begin
if( clr) begin
cnt <= 'd0;
adv <= 'b0;
end else begin
if( on )
{adv, cnt} <= {1'b0, cnt} + {1'b0, delta_n };
else begin
cnt <= 'd0;
adv <= 1'b1; // let the rest of the signal chain advance
// when channel is off so all registers go to reset values
end
end
end
reg set_flag, last_set;
always @(posedge clk or negedge rst_n)
if(!rst_n) begin
flag <= 1'b0;
last_set <= 'b0;
end else begin
last_set <= set_flag;
if( clr_flag ) flag <= 1'b0;
if( !last_set && set_flag ) flag <= 1'b1;
end
// Address
always @(posedge clk or negedge rst_n)
if(!rst_n) begin
addr <= 'd0;
nibble_sel <= 'b0;
set_flag <= 'd0;
chon <= 'b0;
restart <= 'b0;
end else if( !on || clr ) begin
restart <= 'd0;
chon <= 'd0;
end else if( acmd_up_b && on ) begin
restart <= 'd1;
end else if( cen ) begin
if( restart && adv ) begin
addr <= {astart,8'd0};
nibble_sel <= 'b0;
restart <= 'd0;
chon <= 'd1;
end else if( chon && adv ) begin
if( { addr, nibble_sel } != { aend, 8'hFF, 1'b1 } ) begin
{ addr, nibble_sel } <= { addr, nibble_sel } + 25'd1;
set_flag <= 'd0;
end else if(arepeat) begin
restart <= 'd1;
end else begin
set_flag <= 'd1;
chon <= 'd0;
end
end
end // cen
endmodule // jt10_adpcmb_cnt
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR4_4_V
`define SKY130_FD_SC_LP__NOR4_4_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog wrapper for nor4 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nor4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor4_4 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor4_4 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR4_4_V
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; const long long infl = 0x3f3f3f3f3f3f3f3fLL; const long long infi = 0x3f3f3f3f; mt19937_64 mt(chrono::steady_clock::now().time_since_epoch().count()); const long long mod = 1e9 + 7; const long long N = 1e6 + 5; void solve() { long long m; cin >> m; cout << (m / 4 + 1) % mod * ((m / 2 - m / 4 + 1) % mod + mod) % mod << n ; } signed main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); cout << fixed << setprecision(15); long long t = 1; cin >> t; while (t--) solve(); return 0; } long long powm(long long a, long long b) { long long res = 1; while (b) { if (b & 1) res = (res * a) % mod; a = (a * a) % mod; b >>= 1; } return res; } long long divide(long long a, long long b) { return (a % mod) * powm(b, mod - 2) % mod; } long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } |
//64 registers, 32-bits each
module phy_reg_file (
input clk,
input rst,
//Read interface
input [5:0] p_rs, //Read Address 1
input [5:0] p_rt, //Read Address 2
output reg [31:0] rd_data_rs, //Read Data out1
output reg [31:0] rd_data_rt, //Read Data out2
//Write interface
input [5:0] p_rd, //From CDB.Tag (complete stage)
input [31:0] wr_data_in, //From CDB.Value (complete stage)
input RegDest_compl //RegDest from complete stage, it is 1 if this instruction writes register
);
wire clk2x, clk_buf;
reg [5:0] clked_rs;
reg [5:0] clked_rt;
wire [31:0] rd_data_a, rd_data_b;
wire [5:0] addra, addrb;
wire we;
assign we = RegDest_compl&~clk_buf; // only write if clk is high (second 1/2 of clk cycle)
assign addra = we?p_rd:clked_rs; //if write enabled, addr change to rd
assign addrb = we?p_rd:clked_rt;
//read on second clk edge of 2x clk
always@(posedge clk2x, negedge rst) begin
if(!rst) begin
clked_rs <= 6'h0;
clked_rt <= 6'h0;
end else begin
clked_rs <= p_rs;
clked_rt <= p_rt;
end
end
//clk the mem read outputs, keep same on clk high (when writing)
always@(posedge clk_buf, negedge rst) begin
if(!rst) begin
rd_data_rs <= 32'h0;
rd_data_rt <= 32'h0;
end else begin
rd_data_rs <= rd_data_a;
rd_data_rt <= rd_data_b;
end
end
clk_mult cm(.CLKIN_IN(clk),
.RST_IN(rst),
.CLKIN_IBUFG_OUT(),
.CLK0_OUT(clk_buf),
.CLK2X_OUT(clk2x),
.LOCKED_OUT());
blockram br_prf(
.clka(clk2x), //clock A
.wea(we), //write enable A
.addra(addra), //addr A (first phase write, second phase read)
.dina(wr_data_in), //data in A
.douta(rd_data_a), //data out A
.clkb(clk2x), //clock B
.web(we), //write enable B
.addrb(addrb), //addr B (first phase write, second phase read)
.dinb(wr_data_in), //data in B
.doutb(rd_data_b) //data out B
);
//we also need register bypass. When read address equals to write address, output after next clock edge will be the value to be written instead
//of the value from block RAM entry.
endmodule
|
#include <bits/stdc++.h> using namespace std; char s[5005]; int n, dp[5005][5]; const int inf = 1e7 + 5; int go(int id, int need) { if (id == n) return 0; if (dp[id][need] != -1) return dp[id][need]; int ans = 0; if (need == 1) { if (s[id] == a ) ans = max(1 + go(id + 1, 1), 1 + go(id + 1, 2)); else ans = max(go(id, 2), go(id + 1, 1)); } else if (need == 2) { if (s[id] == a ) ans = max(go(id, 3), go(id + 1, 2)); else ans = max(1 + go(id + 1, 2), 1 + go(id + 1, 3)); } else { if (s[id] == a ) ans = 1 + go(id + 1, 3); else ans = go(id + 1, 3); } return dp[id][need] = ans; } int main() { scanf( %s , s); n = strlen(s); memset(dp, -1, sizeof(dp)); printf( %d n , go(0, 1)); } |
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2017 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file score.v when simulating
// the core, score. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module score(
clka,
addra,
douta
);
input clka;
input [13 : 0] addra;
output [11 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(14),
.C_ADDRB_WIDTH(14),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("artix7"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("score.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(12000),
.C_READ_DEPTH_B(12000),
.C_READ_WIDTH_A(12),
.C_READ_WIDTH_B(12),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(12000),
.C_WRITE_DEPTH_B(12000),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(12),
.C_WRITE_WIDTH_B(12),
.C_XDEVICEFAMILY("artix7")
)
inst (
.CLKA(clka),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__TAPVGND_SYMBOL_V
`define SKY130_FD_SC_HD__TAPVGND_SYMBOL_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection
* 1 row down.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__tapvgnd ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__TAPVGND_SYMBOL_V
|
`timescale 1ns/1ps
module test();
reg clock, reset;
sopc sopc(
.clock(clock),
.reset(reset)
);
always #1 clock = ~clock;
initial begin
$dumpfile("dump.vcd");
$dumpvars;
$dumpvars(0, sopc.cpu.register.storage[2]);
$dumpvars(0, sopc.cpu.register.storage[5]);
$dumpvars(0, sopc.cpu.register.storage[7]);
$dumpvars(0, sopc.cpu.register.storage[8]);
$readmemh("rom.txt", sopc.rom.storage);
clock = 1'b0;
reset = 1'b1;
#20 reset = 1'b0;
#10 `AR(2, 32'h04040000);
#2 `AR(2, 32'h04040404);
#2 `AR(7, 32'h00000007);
#2 `AR(5, 32'h00000005);
#2 `AR(8, 32'h00000008);
#2 `AR(2, 32'h04040404); `AR(7, 32'h00000007); `AR(5, 32'h00000005); `AR(8, 32'h00000008);
#2 `AR(2, 32'h04040400);
#2 `AR(2, 32'h02020000);
#2 `AR(2, 32'h00020200);
#2 `AR(2, 32'h00001010);
#2 `AR(2, 32'h00001010);
#2 `AR(2, 32'h00001010); `AR(7, 32'h00000007); `AR(5, 32'h00000005); `AR(8, 32'h00000008);
#2 `AR(2, 32'h80800000);
#2 `AR(2, 32'h80800000);
#2 `AR(2, 32'hffff8080);
#2 `AR(2, 32'hffffff80);
`PASS;
end
endmodule |
#include <bits/stdc++.h> namespace fdd { int n, m1, m2; std::priority_queue<int> q[1010]; std::vector<int> v1, v2; void solve() { std::cin >> n; for (int i = 3; i < n; i++) { scanf( %d%d , &m1, &m2); if (m1 > m2) std::swap(m1, m2); q[m1].push(m2); } for (int i = 2; i <= n; i++) { while (!q[i].empty()) { m1 = q[i].top(); q[i].pop(); v1.push_back(i); v1.push_back(m1); } } for (int i = 3; i < n; i++) { scanf( %d%d , &m1, &m2); if (m1 > m2) std::swap(m1, m2); q[m1].push(m2); } for (int i = 2; i <= n; i++) { while (!q[i].empty()) { m1 = q[i].top(); q[i].pop(); if (q[i].empty()) m2 = i + 1; else m2 = q[i].top(); v2.push_back(1); v2.push_back(m2); } } printf( %d n , (v1.size() + v2.size()) >> 1); int l = v1.size(); for (int i = 0; i < l; i += 2) printf( %d %d n , v1[i], v1[i + 1]); l = v2.size(); for (int i = l - 1; i >= 0; i -= 2) printf( %d %d n , v2[i - 1], v2[i]); } } // namespace fdd int main() { fdd::solve(); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FAHCON_TB_V
`define SKY130_FD_SC_HS__FAHCON_TB_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__fahcon.v"
module top();
// Inputs are registered
reg A;
reg B;
reg CI;
reg VPWR;
reg VGND;
// Outputs are wires
wire COUT_N;
wire SUM;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
CI = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 CI = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 B = 1'b1;
#160 CI = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 B = 1'b0;
#260 CI = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 CI = 1'b1;
#380 B = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 CI = 1'bx;
#480 B = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hs__fahcon dut (.A(A), .B(B), .CI(CI), .VPWR(VPWR), .VGND(VGND), .COUT_N(COUT_N), .SUM(SUM));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__FAHCON_TB_V
|
#include <bits/stdc++.h> using namespace std; int main() { int size1; string s; vector<int> v; int arr[200]; cin >> size1 >> s; for (int i = 0; i < s.size(); i++) { if (s[i] == * ) v.push_back(i + 1); } for (int i = 0; i < v.size(); i++) { for (int count1 = 1; count1 <= 100; count1++) { int n = v[i] + count1; int counttimes = 0; for (int l = i + 1; l < v.size(); l++) { if (counttimes == 4) { cout << yes ; return 0; } if (n == v[l]) { n = v[l] + count1; counttimes++; } if (v[l] > n) break; } if (counttimes == 4) { cout << yes ; return 0; } } } cout << no ; return 0; } |
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: redDiskModule.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 173 11/01/2011 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module redDiskModule (
address,
clock,
q);
input [7:0] address;
input clock;
output [2:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [2:0] sub_wire0;
wire [2:0] q = sub_wire0[2:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({3{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "redDisk.mif",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 225,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.widthad_a = 8,
altsyncram_component.width_a = 3,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "redDisk.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "225"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
// Retrieval info: PRIVATE: WidthData NUMERIC "3"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "redDisk.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "225"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "3"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 3 0 OUTPUT NODEFVAL "q[2..0]"
// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 3 0 @q_a 0 0 3 0
// Retrieval info: GEN_FILE: TYPE_NORMAL redDiskModule.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL redDiskModule.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL redDiskModule.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL redDiskModule.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL redDiskModule_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL redDiskModule_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
module top;
reg [24*8-1:0] str;
real rval;
reg [7:0] array [0:7];
reg [7:0] array2 [8:15];
reg [7:0] array3 [-1:7];
integer idx, istr;
task clear_array;
for (idx = 0; idx < 8; idx = idx + 1) begin
array[idx] = 0;
array2[idx+8] = 0;
end
endtask
initial begin
// An invalid string.
$readmemb(str, array);
$readmemb(istr, array);
// Check a valid string.
str = "ivltests/readmemb.txt";
$readmemb(str, array);
for (idx = 0; idx < 8; idx = idx + 1) begin
if (array[idx] !== idx + 1) begin
$display("Failed: for index %0d of readmemb 1, expected %0d, got %0d",
idx, idx+1, array[idx]);
end
end
// Check a string with a non-printing character.
str[7:0] = 'd2;
$readmemb(str, array);
// This should load, but will print a warning about the real.
rval = 0.0;
clear_array;
$readmemb("ivltests/readmemb.txt", array, rval);
for (idx = 0; idx < 8; idx = idx + 1) begin
if (array[idx] !== idx + 1) begin
$display("Failed: for index %0d of readmemb 2, expected %0d, got %0d",
idx, idx+1, array[idx]);
end
end
// This should load, but will print a warning about the real.
rval = 7.0;
clear_array;
$readmemb("ivltests/readmemb.txt", array, 0, rval);
for (idx = 0; idx < 8; idx = idx + 1) begin
if (array[idx] !== idx + 1) begin
$display("Failed: for index %0d of readmemb 3, expected %0d, got %0d",
idx, idx+1, array[idx]);
end
end
// These should not load the array.
clear_array;
$readmemb("ivltests/readmemb.txt", array, -1, 7);
for (idx = 0; idx < 8; idx = idx + 1) begin
if (array[idx] !== 0) begin
$display("Failed: for index %0d of readmemb 4, expected 0, got %0d",
idx, array[idx]);
end
end
$readmemb("ivltests/readmemb.txt", array2, 7, 15);
for (idx = 8; idx < 16; idx = idx + 1) begin
if (array2[idx] !== 0) begin
$display("Failed: for index %0d of readmemb 5, expected 0, got %0d",
idx, array2[idx]);
end
end
$readmemb("ivltests/readmemb.txt", array, 0, 8);
for (idx = 0; idx < 8; idx = idx + 1) begin
if (array[idx] !== 0) begin
$display("Failed: for index %0d of readmemb 6, expected 0, got %0d",
idx, array[idx]);
end
end
$readmemb("ivltests/readmemb.txt", array2, 8, 16);
for (idx = 8; idx < 16; idx = idx + 1) begin
if (array2[idx] !== 0) begin
$display("Failed: for index %0d of readmemb 7, expected 0, got %0d",
idx, array2[idx]);
end
end
// Check that a warning is printed if we have the wrong number of values.
clear_array;
$readmemb("ivltests/readmemb.txt", array, 0, 6);
for (idx = 0; idx < 7; idx = idx + 1) begin
if (array[idx] !== idx + 1) begin
$display("Failed: for index %0d of readmemb 8, expected %0d, got %0d",
idx, idx+1, array[idx]);
end
end
if (array[7] !== 0) begin
$display("Failed: for index 7 of readmemb 8, expected 0, got %0d",
array[7]);
end
$readmemb("ivltests/readmemb.txt", array3, -1, 7);
for (idx = -1; idx < 7; idx = idx + 1) begin
if ($signed(array3[idx]) !== idx + 2) begin
$display("Failed: for index %0d of readmemb 9, expected %0d, got %0d",
idx, idx+2, array3[idx]);
end
end
if (array3[7] !== 8'bx) begin
$display("Failed: for index 7 of readmemb 9, expected 'dx, got %0d",
array3[7]);
end
// Check what an invalid token returns.
$readmemb("ivltests/readmem-error.txt", array);
// An invalid string.
str = 'bx;
$readmemh(str, array);
$readmemh(istr, array);
// Check a valid string.
str = "ivltests/readmemh.txt";
$readmemh(str, array);
for (idx = 0; idx < 8; idx = idx + 1) begin
if (array[idx] !== idx + 1) begin
$display("Failed: for index %0d of readmemh 1, expected %0d, got %0d",
idx, idx+1, array[idx]);
end
end
// Check a string with a non-printing character.
str[7:0] = 'd2;
$readmemh(str, array);
// This should load, but will print a warning about the real.
rval = 0.0;
clear_array;
$readmemh("ivltests/readmemh.txt", array, rval);
for (idx = 0; idx < 8; idx = idx + 1) begin
if (array[idx] !== idx + 1) begin
$display("Failed: for index %0d of readmemh 2, expected %0d, got %0d",
idx, idx+1, array[idx]);
end
end
// This should load, but will print a warning about the real.
rval = 7.0;
clear_array;
$readmemh("ivltests/readmemh.txt", array, 0, rval);
for (idx = 0; idx < 8; idx = idx + 1) begin
if (array[idx] !== idx + 1) begin
$display("Failed: for index %0d of readmemh 3, expected %0d, got %0d",
idx, idx+1, array[idx]);
end
end
// These should not load the array.
clear_array;
$readmemh("ivltests/readmemh.txt", array, -1, 7);
for (idx = 0; idx < 8; idx = idx + 1) begin
if (array[idx] !== 0) begin
$display("Failed: for index %0d of readmemh 4, expected 0, got %0d",
idx, array[idx]);
end
end
$readmemh("ivltests/readmemh.txt", array2, 7, 15);
for (idx = 8; idx < 16; idx = idx + 1) begin
if (array2[idx] !== 0) begin
$display("Failed: for index %0d of readmemh 5, expected 0, got %0d",
idx, array2[idx]);
end
end
$readmemh("ivltests/readmemh.txt", array, 0, 8);
for (idx = 0; idx < 8; idx = idx + 1) begin
if (array[idx] !== 0) begin
$display("Failed: for index %0d of readmemh 6, expected 0, got %0d",
idx, array[idx]);
end
end
$readmemh("ivltests/readmemh.txt", array2, 8, 16);
for (idx = 8; idx < 16; idx = idx + 1) begin
if (array2[idx] !== 0) begin
$display("Failed: for index %0d of readmemh 7, expected 0, got %0d",
idx, array2[idx]);
end
end
// Check that a warning is printed if we have the wrong number of values.
clear_array;
$readmemh("ivltests/readmemh.txt", array, 0, 6);
for (idx = 0; idx < 7; idx = idx + 1) begin
if (array[idx] !== idx + 1) begin
$display("Failed: for index %0d of readmemh 8, expected %0d, got %0d",
idx, idx+1, array[idx]);
end
end
if (array[7] !== 0) begin
$display("Failed: for index 7 of readmemh 8, expected 0, got %0d",
array[7]);
end
$readmemh("ivltests/readmemh.txt", array3, -1, 7);
for (idx = -1; idx < 7; idx = idx + 1) begin
if ($signed(array3[idx]) !== idx + 2) begin
$display("Failed: for index %0d of readmemh 9, expected %0d, got %0d",
idx, idx+2, array3[idx]);
end
end
if (array3[7] !== 8'bx) begin
$display("Failed: for index 7 of readmemh 9, expected 'dx, got %0d",
array3[7]);
end
// Check what an invalid token returns.
$readmemh("ivltests/readmem-error.txt", array);
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYGATE4SD2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__DLYGATE4SD2_FUNCTIONAL_PP_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__dlygate4sd2 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYGATE4SD2_FUNCTIONAL_PP_V |
module j1#(
//parameter bootram_file = "../image.ram" // For synthesis
parameter bootram_file = "./image.ram" // For simulation
)
(
// Inputs
sys_clk_i, sys_rst_i, io_din,
// Outputs
io_rd, io_wr, io_addr, io_dout);
input sys_clk_i; // main clock
input sys_rst_i; // reset
input [15:0] io_din; // io data in
output io_rd; // io read
output io_wr; // io write
output [15:0] io_addr; // io address
output [15:0] io_dout; // io data out
wire [15:0] insn;
wire [15:0] immediate = { 1'b0, insn[14:0] };
wire [15:0] ramrd;
reg [4:0] dsp;
reg [4:0] _dsp;
reg [15:0] st0;
reg [15:0] _st0;
wire [15:0] st1;
wire _dstkW; // D stack write
reg [12:0] pc;
reg [12:0] _pc;
reg [4:0] rsp;
reg [4:0] _rsp;
wire [15:0] rst0;
reg _rstkW; // R stack write
reg [15:0] _rstkD;
wire _ramWE; // RAM write enable
wire [15:0] pc_plus_1;
assign pc_plus_1 = pc + 1;
dp_ram #(13, 16, bootram_file)
ram0 ( .clk_b(sys_clk_i), .en_b(1), .dat_b(insn), .adr_b({_pc}),
.clk_a(sys_clk_i), .en_a(|_st0[15:14] == 0), .dat_a_out(ramrd), .dat_a(st1), .we_a(_ramWE & (_st0[15:14] == 0)), .adr_a(st0[15:1])
);
reg [15:0] dstack[0:31];
reg [15:0] rstack[0:31];
always @(posedge sys_clk_i)
begin
if (_dstkW)
dstack[_dsp] = st0;
if (_rstkW)
rstack[_rsp] = _rstkD;
end
assign st1 = dstack[dsp];
assign rst0 = rstack[rsp];
reg [3:0] st0sel;
always @*
begin
case (insn[14:13])
2'b00: st0sel = 0; // ubranch
2'b01: st0sel = 1; // 0branch
2'b10: st0sel = 0; // call
2'b11: st0sel = insn[11:8]; // ALU
default: st0sel = 4'bxxxx;
endcase
end
always @*
begin
if (insn[15])
_st0 = immediate;
else
case (st0sel)
4'b0000: _st0 = st0;
4'b0001: _st0 = st1;
4'b0010: _st0 = st0 + st1;
4'b0011: _st0 = st0 & st1;
4'b0100: _st0 = st0 | st1;
4'b0101: _st0 = st0 ^ st1;
4'b0110: _st0 = ~st0;
4'b0111: _st0 = {16{(st1 == st0)}};
4'b1000: _st0 = {16{($signed(st1) < $signed(st0))}};
4'b1001: _st0 = st1 >> st0[3:0];
4'b1010: _st0 = st0 - 1;
4'b1011: _st0 = rst0;
4'b1100: _st0 = |st0[15:14] ? io_din : ramrd;
4'b1101: _st0 = st1 << st0[3:0];
4'b1110: _st0 = {rsp, 3'b000, dsp};
4'b1111: _st0 = {16{(st1 < st0)}};
default: _st0 = 16'hxxxx;
endcase
end
wire is_alu = (insn[15:13] == 3'b011);
wire is_lit = (insn[15]);
assign io_rd = (is_alu & (insn[11:8] == 4'hc) & (|st0[15:14]));
assign io_wr = _ramWE;
assign io_addr = st0;
assign io_dout = st1;
assign _ramWE = is_alu & insn[5];
assign _dstkW = is_lit | (is_alu & insn[7]);
wire [1:0] dd = insn[1:0]; // D stack delta
wire [1:0] rd = insn[3:2]; // R stack delta
always @*
begin
if (is_lit) begin // literal
_dsp = dsp + 1;
_rsp = rsp;
_rstkW = 0;
_rstkD = _pc;
end else if (is_alu) begin
_dsp = dsp + {dd[1], dd[1], dd[1], dd};
_rsp = rsp + {rd[1], rd[1], rd[1], rd};
_rstkW = insn[6];
_rstkD = st0;
end else begin // jump/call
// predicated jump is like DROP
if (insn[15:13] == 3'b001) begin
_dsp = dsp - 1;
end else begin
_dsp = dsp;
end
if (insn[15:13] == 3'b010) begin // call
_rsp = rsp + 1;
_rstkW = 1;
_rstkD = {pc_plus_1[14:0], 1'b0};
end else begin
_rsp = rsp;
_rstkW = 0;
_rstkD = _pc;
end
end
end
always @*
begin
if (sys_rst_i)
_pc = pc;
else
if ((insn[15:13] == 3'b000) |
((insn[15:13] == 3'b001) & (|st0 == 0)) |
(insn[15:13] == 3'b010))
_pc = insn[12:0];
else if (is_alu & insn[12])
_pc = rst0[15:1];
else
_pc = pc_plus_1;
end
always @(posedge sys_clk_i)
begin
if (sys_rst_i) begin
pc <= 0;
dsp <= 0;
st0 <= 0;
rsp <= 0;
end else begin
dsp <= _dsp;
pc <= _pc;
st0 <= _st0;
rsp <= _rsp;
end
end
endmodule // j1
|
// generated by gen_VerilogEHR.py using VerilogEHR.mako
// Copyright (c) 2019 Massachusetts Institute of Technology
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
module EHRU_8 (
CLK,
read_0,
write_0,
EN_write_0,
read_1,
write_1,
EN_write_1,
read_2,
write_2,
EN_write_2,
read_3,
write_3,
EN_write_3,
read_4,
write_4,
EN_write_4,
read_5,
write_5,
EN_write_5,
read_6,
write_6,
EN_write_6,
read_7,
write_7,
EN_write_7
);
parameter DATA_SZ = 1;
parameter RESET_VAL = 0;
input CLK;
output [DATA_SZ-1:0] read_0;
input [DATA_SZ-1:0] write_0;
input EN_write_0;
output [DATA_SZ-1:0] read_1;
input [DATA_SZ-1:0] write_1;
input EN_write_1;
output [DATA_SZ-1:0] read_2;
input [DATA_SZ-1:0] write_2;
input EN_write_2;
output [DATA_SZ-1:0] read_3;
input [DATA_SZ-1:0] write_3;
input EN_write_3;
output [DATA_SZ-1:0] read_4;
input [DATA_SZ-1:0] write_4;
input EN_write_4;
output [DATA_SZ-1:0] read_5;
input [DATA_SZ-1:0] write_5;
input EN_write_5;
output [DATA_SZ-1:0] read_6;
input [DATA_SZ-1:0] write_6;
input EN_write_6;
output [DATA_SZ-1:0] read_7;
input [DATA_SZ-1:0] write_7;
input EN_write_7;
reg [DATA_SZ-1:0] r;
wire [DATA_SZ-1:0] wire_0;
wire [DATA_SZ-1:0] wire_1;
wire [DATA_SZ-1:0] wire_2;
wire [DATA_SZ-1:0] wire_3;
wire [DATA_SZ-1:0] wire_4;
wire [DATA_SZ-1:0] wire_5;
wire [DATA_SZ-1:0] wire_6;
wire [DATA_SZ-1:0] wire_7;
wire [DATA_SZ-1:0] wire_8;
assign wire_0 = r;
assign wire_1 = EN_write_0 ? write_0 : wire_0;
assign wire_2 = EN_write_1 ? write_1 : wire_1;
assign wire_3 = EN_write_2 ? write_2 : wire_2;
assign wire_4 = EN_write_3 ? write_3 : wire_3;
assign wire_5 = EN_write_4 ? write_4 : wire_4;
assign wire_6 = EN_write_5 ? write_5 : wire_5;
assign wire_7 = EN_write_6 ? write_6 : wire_6;
assign wire_8 = EN_write_7 ? write_7 : wire_7;
assign read_0 = wire_0;
assign read_1 = wire_1;
assign read_2 = wire_2;
assign read_3 = wire_3;
assign read_4 = wire_4;
assign read_5 = wire_5;
assign read_6 = wire_6;
assign read_7 = wire_7;
always @(posedge CLK) begin
r <= wire_8;
end
endmodule
|
#include <bits/stdc++.h> int dizi[100015]; int main() { int i, m, n, fark, k, j; scanf( %d %d %d %d , &m, &n, &k, &j); for (i = 1;; i++) { j = (j * m + n) % k; if (dizi[j]) { printf( %d , i - dizi[j]); break; } dizi[j] = i; } return 0; } |
/*
*******************************************************************************
* File Name : ada_idex_stage.v
* Project : ADA processor
* Version : 0.1
* Date : Aug 8th, 2014
* Author : Angel Terrones <>
*
* Disclaimer : Copyright © 2014 Angel Terrones
* Release under the MIT License.
*
* Description : Pipeline register: from Instruction Decode to Execution
*******************************************************************************
*/
`include "ada_defines.v"
module ada_idex_stage(
input clk, // Main clock
input rst, // Main reset
input [4:0] id_exu_operation, // ALU operation from ID stage
input [31:0] id_exu_port_a, // Data A
input [31:0] id_exu_port_b, // Data B
input [31:0] id_mem_store_data, // Data to Memory
input id_mem_write, // Mem write operation
input id_mem_read, // Mem read operation
input id_mem_byte, // byte operation
input id_mem_halfword, // halfword operation
input id_mem_sign_ext, // Sign/Zero extend data from memory
input id_mem_exu_mem_select, // Select data from EX or MEM
input [4:0] id_gpr_wa, // GPR write address
input id_gpr_we, // GPR write enable
input id_kernel_mode, // kernel mode in the moment of instruction decode
//input id_is_ds , // this instruction is a BDS/LDS
input [31:0] id_pc_current, // instruction's PC
input id_ex_can_exc, // EX instruction can generate an exception
input id_mem_can_exc, // MEM instruction can generate an exception
input id_flush, // Flush ID stage
input id_stall, // Stall ID stage
input ex_stall, // Stall EX stage
output reg [4:0] ex_exu_operation, // ALU operation to EX stage
output reg [31:0] ex_exu_port_a, // Data A
output reg [31:0] ex_exu_port_b, // Data B
output reg [31:0] ex_mem_store_data, // Data to memory
output reg ex_mem_write, // Mem write operation
output reg ex_mem_read, // Mem read operation
output reg ex_mem_byte, // byte operation
output reg ex_mem_halfword, // halfword operation
output reg ex_mem_sign_ext, // Sign/Zero extend data from memory
output reg ex_mem_exu_mem_select, // Select data from EX or MEM
output reg [4:0] ex_gpr_wa, // GPR write address
output reg ex_gpr_we, // GPR write enable
output reg ex_kernel_mode, // kernel mode in the moment of instruction decode
//output reg ex_is_ds, // this instruction is a BDS/LDS
output reg [31:0] ex_pc_current, // instruction's PC
output reg ex_ex_can_exc, // EX instruction can generate an exception
output reg ex_mem_can_exc // MEM instruction can generate an exception
);
//--------------------------------------------------------------------------
// Propagate signals
//--------------------------------------------------------------------------
always @(posedge clk) begin
ex_exu_operation <= (rst) ? 5'b0 : ((ex_stall) ? ex_exu_operation : ((id_stall | id_flush) ? 5'b0 : id_exu_operation));
ex_exu_port_a <= (rst) ? 32'b0 : ((ex_stall) ? ex_exu_port_a : id_exu_port_a);
ex_exu_port_b <= (rst) ? 32'b0 : ((ex_stall) ? ex_exu_port_b : id_exu_port_b);
ex_mem_store_data <= (rst) ? 32'b0 : ((ex_stall) ? ex_mem_store_data : id_mem_store_data);
ex_mem_write <= (rst) ? 1'b0 : ((ex_stall) ? ex_mem_write : ((id_stall | id_flush) ? 1'b0 : id_mem_write));
ex_mem_read <= (rst) ? 1'b0 : ((ex_stall) ? ex_mem_read : ((id_stall | id_flush) ? 1'b0 : id_mem_read));
ex_mem_byte <= (rst) ? 1'b0 : ((ex_stall) ? ex_mem_byte : id_mem_byte);
ex_mem_halfword <= (rst) ? 1'b0 : ((ex_stall) ? ex_mem_halfword : id_mem_halfword);
ex_mem_sign_ext <= (rst) ? 1'b0 : ((ex_stall) ? ex_mem_sign_ext : id_mem_sign_ext);
ex_mem_exu_mem_select <= (rst) ? 1'b0 : ((ex_stall) ? ex_mem_exu_mem_select : id_mem_exu_mem_select);
ex_gpr_wa <= (rst) ? 5'b0 : ((ex_stall) ? ex_gpr_wa : ((id_stall | id_flush) ? 5'b0 : id_gpr_wa));
ex_gpr_we <= (rst) ? 1'b0 : ((ex_stall) ? ex_gpr_we : ((id_stall | id_flush) ? 1'b0 : id_gpr_we));
ex_kernel_mode <= (rst) ? 1'b0 : ((ex_stall) ? ex_kernel_mode : ((id_stall | id_flush) ? 1'b0 : id_kernel_mode));
//ex_is_ds <= (rst) ? 1'b0 : ((ex_stall) ? ex_is_ds : id_is_ds );
ex_pc_current <= (rst) ? 32'b0 : ((ex_stall) ? ex_pc_current : id_pc_current);
ex_ex_can_exc <= (rst) ? 1'b0 : ((ex_stall) ? ex_ex_can_exc : ((id_stall | id_flush) ? 1'b0 : id_ex_can_exc));
ex_mem_can_exc <= (rst) ? 1'b0 : ((ex_stall) ? ex_mem_can_exc : ((id_stall | id_flush) ? 1'b0 : id_mem_can_exc));
end
endmodule
|
`include "../mem/im.v"
`include "../RF/reg_file2.v"
`include "../ALU/alu.v"
`include "../lib/mux5bit_2to1_2.v"
`include "../lib/mux32bit_4to1.v"
`include "../lib/mux32bit_2to1.v"
`include "../lib/mux32bit_2to1_2.v"
`include "../lib/sign_extend.v"
`include "../control/control2.v"
`include "../ALU/alu_control2.v"
`include "../mem/dm.v"
`include "../lib/shift_left_2.v"
`include "../lib/jump_addr.v"
module cpu(input clk,
output [31:0] alu_output, data, nxt_pc);
reg [31:0] pc;
wire [31:0] readData1, readData2, b;
wire regDest0, regDst1, regWrite, aluSrc, zero, memToReg0, memToReg1;
wire memRead, memWrite, branch, branch_ne, s_branch, jump;
wire [31:0] sExtended, alu_output, memData, writeData, j_addr, mux3_output, mux4_output;
wire [3:0] alu_ctrl;
wire [2:0] alu_op;
wire [4:0] writeReg;
wire [31:0] fa1_output, ex_shifted, pc_4;
initial pc <= 32'd0;
im i_mem(.clk(clk),
.data(data),
.addr(pc));
mux5bit_4to1 mux0(.i0(data[20:16]),
.i1(data[15:11]),
.i2(5'd31),
.s({regDst1, regDst0}),
.z(writeReg));
reg_file rf(.readReg1(data[25:21]),
.readReg2(data[20:16]),
.writeReg(writeReg),
.clk(clk),
.regWrite(regWrite),
.readData1(readData1),
.readData2(readData2),
.writeData(writeData));
sign_extend se(.a(data[15:0]), .b(sExtended));
mux32bit_2to1 mux1(.i0(readData2),
.i1(sExtended),
.s(aluSrc),
.z(b));
alu main_alu(.op(alu_ctrl), .a(readData1), .b(b), .z(alu_output), .zero(zero));
alu_control ac (.funct(data[5:0]), .alu_op(alu_op), .aluctrl(alu_ctrl));
control c(.op(data[31:26]),
.alu_op(alu_op),
.regDst0(regDst0),
.regDst1(regDst1),
.aluSrc(aluSrc),
.memToReg0(memToReg0),
.memToReg1(memToReg1),
.regWrite(regWrite),
.memRead(memRead),
.memWrite(memWrite),
.branch(branch),
.branch_ne(branch_ne),
.jump(jump));
dm mem(.clk(clk), .addr(alu_output), .writeData(readData2), .memWrite(memWrite), .memRead(memRead), .readData(memData));
mux32bit_4to1 mux2(.i0(alu_output), .i1(memData), .i2(pc_4), .s({memToReg1, memToReg0}), .z(writeData));
shift_left_2 sll2(.a(sExtended), .b(ex_shifted));
//alu fa1(.op(4'd2), .a(pc_4), .b(ex_shifted), .z(fa1_output));
alu fa1(.op(4'd2), .a(pc_4), .b(sExtended), .z(fa1_output));
wire int0, int1;
and (int0, branch, zero);
and (int1, branch_ne, ~zero);
or (s_branch, int0, int1);
wire jr;
and and1(jr , ~data[5], ~data[4], data[3], ~data[2], ~data[1], ~data[0]
, ~data[26], ~data[27],~data[28], ~data[29], ~data[30], ~data[31] );
//always @(*) jr = ~data[26] & ~data[27] & data[28] & ~data[29] & ~data[30] & ~data[31];
jump_addr ja(.inst(data[25:0]), .pc_4(pc_4[31:28]), .j_addr(j_addr));
//mux32bit_2to1 mux3(.i0(pc_4), .i1(fa1_output), .s(s_branch), .z(nxt_pc));
mux32bit_2to1_2 mux3(.i0(pc_4), .i1(fa1_output), .s(s_branch), .z(mux3_output));
mux32bit_2to1_2 mux4(.i0(mux3_output), .i1(j_addr), .s(jump), .z(mux4_output));
mux32bit_2to1_2 mux5(.i1(readData1), .i0(mux4_output), .z(nxt_pc), .s(jr));
//mux32bit_2to1 mux4(.i1(j_addr), .i0(mux3_output), .z(nxt_pc), .s(jump));
alu fa2(.op(4'd2), .a(pc), .b(32'd1), .z(pc_4));
always @(posedge clk) begin
pc <= nxt_pc;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; inline char nc() { static char buf[600000], *p1, *p2; return p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 600000, stdin), p1 == p2) ? EOF : *p1++; } long long rd() { long long x = 0; char ch = nc(); while (ch < 0 || ch > 9 ) ch = nc(); while (ch >= 0 && ch <= 9 ) x = (x << 3) + (x << 1) + ch - 0 , ch = nc(); return x; } const long long MAX_N = 5e5 + 25; long long n, m, q; long long cnt[MAX_N]; long long ans[MAX_N]; set<pair<long long, long long> > city; set<pair<long long, long long> >::iterator it; long long Fen[MAX_N]; long long num; long long Min; set<pair<long long, long long> > Q; void add(long long tmp) { tmp++; for (; tmp < MAX_N; tmp += tmp & -tmp) Fen[tmp]++; } long long get(long long tmp) { long long res = 0; long long id = 0; for (long long i = 20; ~i; i--) if (id + (1 << i) < MAX_N && ((id >> i) & 1) == 0) if (res + Fen[id + (1 << i)] < tmp) { res += Fen[id + (1 << i)]; id += (1 << i); } return id; } int main() { ios::sync_with_stdio(false), cin.tie(0); n = rd(); m = rd(); q = rd(); for (long long i = 0; i < n; i++) { long long tmp; tmp = rd(); tmp--; cnt[tmp]++; } for (long long i = 0; i < q; i++) { long long t; t = rd(); t -= n; Q.insert({t, i}); } for (long long i = 0; i < m; i++) city.insert({cnt[i], i}); num = 1; it = city.begin(); add(it->second); Min = it->first; city.erase(it); while (city.size() && city.begin()->first == Min) { num++; it = city.begin(); add(it->second); city.erase(it); } long long Y = 0; while (num != m) { while (Q.size() && Q.begin()->first <= Y + num) { it = Q.begin(); ans[it->second] = get(it->first - Y); Q.erase(it); } if (!Q.size()) break; Y += num; Min++; while (city.size() && city.begin()->first == Min) { num++; it = city.begin(); add(it->second); city.erase(it); } } while (Q.size()) { it = Q.begin(); ans[it->second] = (((it->first - Y) % m - 1) + m) % m; Q.erase(it); } for (long long i = 0; i < q; i++) printf( %lld , ans[i] + 1); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FA_PP_SYMBOL_V
`define SKY130_FD_SC_HS__FA_PP_SYMBOL_V
/**
* fa: Full adder.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__fa (
//# {{data|Data Signals}}
input A ,
input B ,
input CIN ,
output COUT,
output SUM ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__FA_PP_SYMBOL_V
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ba
//
// Generated
// by: wig
// on: Tue Jul 4 08:39:13 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ba.v,v 1.4 2007/03/05 13:33:58 wig Exp $
// $Date: 2007/03/05 13:33:58 $
// $Log: ent_ba.v,v $
// Revision 1.4 2007/03/05 13:33:58 wig
// Updated testcase output (only comments)!
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_ba
//
// No user `defines in this module
module ent_ba
//
// Generated Module inst_ba
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of ent_ba
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps / 1ps
`default_nettype none
module tcp_to_bus (
input wire BUS_RST,
input wire BUS_CLK,
// SiTCP TCP RX
output reg [15:0] TCP_RX_WC, // Rx FIFO write count[15:0] (Unused bits should be set 1)
input wire TCP_RX_WR, // Write enable
input wire [7:0] TCP_RX_DATA, // Write data[7:0]
//input wire TCP_TX_FULL, // Almost full flag
//output wire TCP_TX_WR, // Write enable
//output reg TCP_TX_DATA, // Write data[7:0]
// SiTCP RBCP (UDP)
input wire RBCP_ACT,
input wire [31:0] RBCP_ADDR,
input wire [7:0] RBCP_WD,
input wire RBCP_WE,
input wire RBCP_RE,
output reg RBCP_ACK,
output wire [7:0] RBCP_RD,
// BUS
output wire BUS_WR,
output wire BUS_RD,
output wire [31:0] BUS_ADD,
inout wire [7:0] BUS_DATA,
output reg INVALID
);
// TCP
wire TCP_RESET;
reg [15:0] LENGTH;
reg [15:0] BYTE_CNT;
reg [31:0] TCP_TO_BUS_ADD;
reg [15:0] RX_DATA_255_CNT;
wire TCP_TO_BUS_WR;
always @(posedge BUS_CLK)
if(BUS_RST) begin
TCP_RX_WC <= 0;
end else if(TCP_RX_WR) begin
TCP_RX_WC <= TCP_RX_WC + 1;
end else begin
TCP_RX_WC <= 0;
end
always @(posedge BUS_CLK)
if(BUS_RST) begin
BYTE_CNT <= 0;
end else if(INVALID || TCP_RESET) begin
BYTE_CNT <= 0;
end else if((BYTE_CNT >= 5) && ((BYTE_CNT - 5) == LENGTH)) begin
BYTE_CNT <= 0;
end else if(TCP_RX_WR) begin
BYTE_CNT <= BYTE_CNT + 1;
end else begin
BYTE_CNT <= BYTE_CNT;
end
// invalid signal will prevent from writing to BUS
// invalid signal will be reset when TCP write request is de-asserted
always @(posedge BUS_CLK)
if (BUS_RST)
INVALID <= 1'b0;
else if (TCP_RESET)
INVALID <= 1'b0;
// check for correct length, substract header size 6
// check for correct max. address
else if (({TCP_RX_DATA, LENGTH[7:0]} > 65529 && BYTE_CNT == 1) || ((LENGTH + {TCP_RX_DATA, TCP_TO_BUS_ADD[23:0]} > 33'h1_0000_0000) && BYTE_CNT == 5))
INVALID <= 1'b1;
else
INVALID <= INVALID;
always @(posedge BUS_CLK)
if(BUS_RST) begin
RX_DATA_255_CNT <= 0;
end else if(TCP_RX_WR && ~&TCP_RX_DATA) begin // TCP data is not 255
RX_DATA_255_CNT <= 0;
end else if(TCP_RX_WR && &TCP_RX_DATA && ~&RX_DATA_255_CNT) begin // TCP data is 255
RX_DATA_255_CNT <= RX_DATA_255_CNT + 1;
end else begin
RX_DATA_255_CNT <= RX_DATA_255_CNT;
end
assign TCP_RESET = (&TCP_RX_DATA && RX_DATA_255_CNT == 16'hff_fe && TCP_RX_WR) || ((&TCP_RX_DATA && &RX_DATA_255_CNT && TCP_RX_WR));
always @(posedge BUS_CLK)
if(BUS_RST) begin
LENGTH <= 0;
end else if(TCP_RX_WR && BYTE_CNT == 0) begin
LENGTH[7:0] <= TCP_RX_DATA;
end else if(TCP_RX_WR && BYTE_CNT == 1) begin
LENGTH[15:8] <= TCP_RX_DATA;
end else begin
LENGTH <= LENGTH;
end
assign TCP_TO_BUS_WR = (TCP_RX_WR && BYTE_CNT > 5 && !INVALID) ? 1'b1 : 1'b0;
always @(posedge BUS_CLK)
if(BUS_RST) begin
TCP_TO_BUS_ADD <= 0;
end else if(TCP_RX_WR && BYTE_CNT == 2) begin
TCP_TO_BUS_ADD[7:0] <= TCP_RX_DATA;
end else if(TCP_RX_WR && BYTE_CNT == 3) begin
TCP_TO_BUS_ADD[15:8] <= TCP_RX_DATA;
end else if(TCP_RX_WR && BYTE_CNT == 4) begin
TCP_TO_BUS_ADD[23:16] <= TCP_RX_DATA;
end else if(TCP_RX_WR && BYTE_CNT == 5) begin
TCP_TO_BUS_ADD[31:24] <= TCP_RX_DATA;
end else if(TCP_RX_WR && BYTE_CNT > 5) begin
TCP_TO_BUS_ADD <= TCP_TO_BUS_ADD + 1;
end else begin
TCP_TO_BUS_ADD <= TCP_TO_BUS_ADD;
end
// RBCP
wire RBCP_TO_BUS_WR;
always @(posedge BUS_CLK) begin
if(BUS_RST)
RBCP_ACK <= 0;
else begin
if (RBCP_ACK == 1)
RBCP_ACK <= 0;
else
RBCP_ACK <= (RBCP_WE | RBCP_RE) & ~TCP_TO_BUS_WR;
end
end
assign RBCP_TO_BUS_WR = RBCP_WE & RBCP_ACT;
assign RBCP_RD[7:0] = BUS_WR ? 8'bz : BUS_DATA;
// BUS
assign BUS_WR = TCP_TO_BUS_WR | RBCP_TO_BUS_WR;
assign BUS_RD = RBCP_RE & RBCP_ACT & ~BUS_WR;
assign BUS_ADD = (TCP_TO_BUS_WR) ? TCP_TO_BUS_ADD : RBCP_ADDR;
assign BUS_DATA = (BUS_WR) ? ((TCP_TO_BUS_WR) ? TCP_RX_DATA : RBCP_WD) : 8'bz;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: BMSTU
// Engineer: Oleg Odintsov
//
// Create Date: 15:09:47 01/19/2012
// Design Name:
// Module Name: ag_main
// Project Name: Agat Hardware Project
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ROM2kx8(input CLK, input[10:0] AB, input CS, output[7:0] DO);
reg[7:0] mem[0:2047];
reg[7:0] R;
assign DO = CS? R: 8'bZ;
always @(posedge CLK) if (CS) R <= mem[AB];
initial begin
`include "monitor7.v"
end
endmodule
module ag_main(
input clk50x,
input[3:0] btns,
input[3:0] switches,
output[7:0] leds,
output[3:0] controls,
output[4:0] vga_bus,
input[1:0] ps2_bus_in
);
// assign leds = 0;
// assign controls = 0;
// assign vga_bus = 0;
wire clk1, clk1x, clk10, clk50;
reg turbo = 0;
BUFG bg1(clk50, clk50x);
clk_div#5 cd5(clk50, clk10);
clk_div#10 cd10(clk10, clk1x);
BUFGMUX bgm1(clk1, clk1x, clk10, turbo);
// assign clk1 = turbo?clk10:clk1x;
wire clk_vram;
wire[13:0] AB2;
wire[15:0] DI2;
wire [15:0] AB; // address bus
wire [7:0] DI; // data in, read bus
wire [7:0] DO; // data out, write bus
wire read;
wire rom_cs, ram_cs;
wire phi_1, phi_2;
RAM32Kx8x16 base_ram(phi_2, AB[14:0], ram_cs, read, DI, DO,
clk_vram, AB2, 1, DI2);
ROM2kx8 rom1(phi_2, AB[10:0], rom_cs, DI);
wire [3:0] AB_HH = AB[15:12];
wire [3:0] AB_HL = AB[11:8];
wire [3:0] AB_LH = AB[7:4];
wire [3:0] AB_LL = AB[3:0];
wire [7:0] AB_H = AB[15:8];
wire [7:0] AB_L = AB[7:0];
wire AB_CXXX = (AB_HH == 4'hC);
wire AB_FXXX = (AB_HH == 4'hF);
wire AB_C0XX = AB_CXXX && !AB_HL;
wire AB_C00X = AB_C0XX && (AB_LH == 4'h0);
wire AB_C01X = AB_C0XX && (AB_LH == 4'h1);
wire AB_C02X = AB_C0XX && (AB_LH == 4'h2);
wire AB_C03X = AB_C0XX && (AB_LH == 4'h3);
wire AB_C04X = AB_C0XX && (AB_LH == 4'h4);
wire AB_C05X = AB_C0XX && (AB_LH == 4'h5);
wire AB_C7XX = AB_CXXX && (AB_HL == 4'h7);
reg timer_ints = 0;
assign rom_cs = AB_FXXX && AB[11]; // F800-FFFF
assign ram_cs = !AB[15];
reg reset_auto = 1;
wire reset;
wire WE = ~read; // write enable
supply0 IRQ; // interrupt request
wire NMI; // non-maskable interrupt request
supply1 RDY; // Ready signal. Pauses CPU when RDY=0
supply1 SO; // Set Overflow, not used.
wire SYNC;
assign NMI = timer_ints & vga_bus[0];
reg[7:0] vmode = 0;
wire[7:0] key_reg;
wire key_rus;
reg key_clear = 0;
wire key_rst, key_pause;
reg beep_reg = 0, tape_out_reg = 0;
assign reset = btns[0];
assign leds = AB[11:4];
assign controls = {1'b0, beep_reg ^ tape_out_reg, tape_out_reg, beep_reg};
ag_video video(clk50, vmode, clk_vram, AB2, DI2, vga_bus);
wire[1:0] ps2_bus;
signal_filter sf1(clk1, ps2_bus_in[0], ps2_bus[0]);
signal_filter sf2(clk1, ps2_bus_in[1], ps2_bus[1]);
ag_keyb keyb(phi_2, ps2_bus, key_reg, key_clear, key_rus, key_rst, key_pause);
assign DI = (AB_C00X && !WE)?key_reg:8'bZ;
wire reset_all = reset | reset_auto | key_rst;
always @(posedge phi_2) begin
turbo <= switches[0];
key_clear <= AB_C01X;
if (AB_C04X) timer_ints <= 1;
else if (AB_C05X || reset_all) timer_ints <= 0;
if (AB_C02X) tape_out_reg <= ~tape_out_reg;
if (AB_C03X) beep_reg <= ~beep_reg;
if (AB_C7XX) vmode <= AB_L;
end
always @(posedge vga_bus[0]) begin
reset_auto <= 0;
end
ag6502_ext_clock clk(clk50, clk1, phi_1, phi_2);
ag6502 cpu(clk1, phi_1, phi_2, AB, read, DI, DO,
RDY & ~key_pause, ~reset_all, ~IRQ, ~NMI, SO, SYNC);
endmodule
|
#include <bits/stdc++.h> using namespace std; map<double, int> a; double b[200007]; inline long long int read() { long long int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) x = x * 10 + ch - 0 , ch = getchar(); return x * f; } inline void writ(int x) { if (x < 0) putchar( - ), x = -x; if (x > 9) writ(x / 10); putchar(x % 10 + 0 ); } inline void write(int x) { writ(x); putchar( ); } int main() { a.clear(); int n = read(), x, y, z; for (int i = 1; i <= n; ++i) x = read(), y = read(), z = read(), b[i] = (double)(x + y) / z, ++a[b[i]]; for (int i = 1; i <= n; ++i) write(a[b[i]]); return 0; } |
//
// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
//
//
//
//
// Ports:
// Name I/O size props
// RDY_server_reset_request_put O 1 reg
// RDY_server_reset_response_get O 1
// read_rs1 O 64
// read_rs1_port2 O 64
// read_rs2 O 64
// CLK I 1 clock
// RST_N I 1 reset
// read_rs1_rs1 I 5
// read_rs1_port2_rs1 I 5
// read_rs2_rs2 I 5
// write_rd_rd I 5
// write_rd_rd_val I 64 reg
// EN_server_reset_request_put I 1
// EN_server_reset_response_get I 1
// EN_write_rd I 1
//
// Combinational paths from inputs to outputs:
// read_rs1_rs1 -> read_rs1
// read_rs1_port2_rs1 -> read_rs1_port2
// read_rs2_rs2 -> read_rs2
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkGPR_RegFile(CLK,
RST_N,
EN_server_reset_request_put,
RDY_server_reset_request_put,
EN_server_reset_response_get,
RDY_server_reset_response_get,
read_rs1_rs1,
read_rs1,
read_rs1_port2_rs1,
read_rs1_port2,
read_rs2_rs2,
read_rs2,
write_rd_rd,
write_rd_rd_val,
EN_write_rd);
input CLK;
input RST_N;
// action method server_reset_request_put
input EN_server_reset_request_put;
output RDY_server_reset_request_put;
// action method server_reset_response_get
input EN_server_reset_response_get;
output RDY_server_reset_response_get;
// value method read_rs1
input [4 : 0] read_rs1_rs1;
output [63 : 0] read_rs1;
// value method read_rs1_port2
input [4 : 0] read_rs1_port2_rs1;
output [63 : 0] read_rs1_port2;
// value method read_rs2
input [4 : 0] read_rs2_rs2;
output [63 : 0] read_rs2;
// action method write_rd
input [4 : 0] write_rd_rd;
input [63 : 0] write_rd_rd_val;
input EN_write_rd;
// signals for module outputs
wire [63 : 0] read_rs1, read_rs1_port2, read_rs2;
wire RDY_server_reset_request_put, RDY_server_reset_response_get;
// register rg_state
reg [1 : 0] rg_state;
reg [1 : 0] rg_state$D_IN;
wire rg_state$EN;
// ports of submodule f_reset_rsps
wire f_reset_rsps$CLR,
f_reset_rsps$DEQ,
f_reset_rsps$EMPTY_N,
f_reset_rsps$ENQ,
f_reset_rsps$FULL_N;
// ports of submodule regfile
wire [63 : 0] regfile$D_IN,
regfile$D_OUT_1,
regfile$D_OUT_2,
regfile$D_OUT_3;
wire [4 : 0] regfile$ADDR_1,
regfile$ADDR_2,
regfile$ADDR_3,
regfile$ADDR_4,
regfile$ADDR_5,
regfile$ADDR_IN;
wire regfile$WE;
// rule scheduling signals
wire CAN_FIRE_RL_rl_reset_loop,
CAN_FIRE_RL_rl_reset_start,
CAN_FIRE_server_reset_request_put,
CAN_FIRE_server_reset_response_get,
CAN_FIRE_write_rd,
WILL_FIRE_RL_rl_reset_loop,
WILL_FIRE_RL_rl_reset_start,
WILL_FIRE_server_reset_request_put,
WILL_FIRE_server_reset_response_get,
WILL_FIRE_write_rd;
// action method server_reset_request_put
assign RDY_server_reset_request_put = f_reset_rsps$FULL_N ;
assign CAN_FIRE_server_reset_request_put = f_reset_rsps$FULL_N ;
assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ;
// action method server_reset_response_get
assign RDY_server_reset_response_get =
rg_state == 2'd2 && f_reset_rsps$EMPTY_N ;
assign CAN_FIRE_server_reset_response_get =
rg_state == 2'd2 && f_reset_rsps$EMPTY_N ;
assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ;
// value method read_rs1
assign read_rs1 = (read_rs1_rs1 == 5'd0) ? 64'd0 : regfile$D_OUT_3 ;
// value method read_rs1_port2
assign read_rs1_port2 =
(read_rs1_port2_rs1 == 5'd0) ? 64'd0 : regfile$D_OUT_2 ;
// value method read_rs2
assign read_rs2 = (read_rs2_rs2 == 5'd0) ? 64'd0 : regfile$D_OUT_1 ;
// action method write_rd
assign CAN_FIRE_write_rd = 1'd1 ;
assign WILL_FIRE_write_rd = EN_write_rd ;
// submodule f_reset_rsps
FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(f_reset_rsps$ENQ),
.DEQ(f_reset_rsps$DEQ),
.CLR(f_reset_rsps$CLR),
.FULL_N(f_reset_rsps$FULL_N),
.EMPTY_N(f_reset_rsps$EMPTY_N));
// submodule regfile
RegFile #(.addr_width(32'd5),
.data_width(32'd64),
.lo(5'h0),
.hi(5'd31)) regfile(.CLK(CLK),
.ADDR_1(regfile$ADDR_1),
.ADDR_2(regfile$ADDR_2),
.ADDR_3(regfile$ADDR_3),
.ADDR_4(regfile$ADDR_4),
.ADDR_5(regfile$ADDR_5),
.ADDR_IN(regfile$ADDR_IN),
.D_IN(regfile$D_IN),
.WE(regfile$WE),
.D_OUT_1(regfile$D_OUT_1),
.D_OUT_2(regfile$D_OUT_2),
.D_OUT_3(regfile$D_OUT_3),
.D_OUT_4(),
.D_OUT_5());
// rule RL_rl_reset_start
assign CAN_FIRE_RL_rl_reset_start = rg_state == 2'd0 ;
assign WILL_FIRE_RL_rl_reset_start = rg_state == 2'd0 ;
// rule RL_rl_reset_loop
assign CAN_FIRE_RL_rl_reset_loop = rg_state == 2'd1 ;
assign WILL_FIRE_RL_rl_reset_loop = rg_state == 2'd1 ;
// register rg_state
always@(EN_server_reset_request_put or
WILL_FIRE_RL_rl_reset_loop or WILL_FIRE_RL_rl_reset_start)
case (1'b1)
EN_server_reset_request_put: rg_state$D_IN = 2'd0;
WILL_FIRE_RL_rl_reset_loop: rg_state$D_IN = 2'd2;
WILL_FIRE_RL_rl_reset_start: rg_state$D_IN = 2'd1;
default: rg_state$D_IN = 2'b10 /* unspecified value */ ;
endcase
assign rg_state$EN =
EN_server_reset_request_put || WILL_FIRE_RL_rl_reset_start ||
WILL_FIRE_RL_rl_reset_loop ;
// submodule f_reset_rsps
assign f_reset_rsps$ENQ = EN_server_reset_request_put ;
assign f_reset_rsps$DEQ = EN_server_reset_response_get ;
assign f_reset_rsps$CLR = 1'b0 ;
// submodule regfile
assign regfile$ADDR_1 = read_rs2_rs2 ;
assign regfile$ADDR_2 = read_rs1_port2_rs1 ;
assign regfile$ADDR_3 = read_rs1_rs1 ;
assign regfile$ADDR_4 = 5'h0 ;
assign regfile$ADDR_5 = 5'h0 ;
assign regfile$ADDR_IN = write_rd_rd ;
assign regfile$D_IN = write_rd_rd_val ;
assign regfile$WE = EN_write_rd && write_rd_rd != 5'd0 ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
rg_state <= `BSV_ASSIGNMENT_DELAY 2'd0;
end
else
begin
if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
rg_state = 2'h2;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkGPR_RegFile
|
#include <bits/stdc++.h> using namespace std; int main() { long long x; cin >> x; if (!x) cout << 0 << endl; else { if (x < 0) x = -1 * x; long long ans = 1, temp = 0; while (temp < x) { temp = temp + ans; ans++; } ans--; long long res = ans * (ans + 1) / 2 - x; if (!res) cout << ans << endl; else if (res % 2) { if (ans % 2) ans++; cout << ans + 1 << endl; } else cout << ans << endl; } return 0; } |
#include <bits/stdc++.h> const int N = 105; int n, m; char a[N][N]; struct Node { int ax, ay, bx, by, cx, cy; }; void work(int i, int j, int mask) { for (int x = 0; x < 2; ++x) { for (int y = 0; y < 2; ++y) { if (mask >> (x << 1 | y) & 1) { a[i][j] ^= 1, a[i][j + 1] ^= 1, a[i + 1][j] ^= 1, a[i + 1][j + 1] ^= 1; a[i + x][j + y] ^= 1; } } } } void solve() { std::cin >> n >> m; for (int i = 0; i < n; ++i) { std::cin >> a[i]; } std::vector<Node> ans; if ((n & 1) && (m & 1) && a[n - 1][m - 1] == 1 ) { ans.push_back({n - 1, m - 1, n - 2, m - 1, n - 1, m - 2}); a[n - 1][m - 1] = 0 ; a[n - 2][m - 1] ^= 1; a[n - 1][m - 2] ^= 1; } if (m & 1) { for (int i = 0; i < n - 1; i += 2) { if (a[i][m - 1] == 1 && a[i + 1][m - 1] == 1 ) { ans.push_back({i, m - 2, i, m - 1, i + 1, m - 1}); a[i][m - 2] ^= 1; } else if (a[i][m - 1] == 1 ) { ans.push_back({i, m - 2, i + 1, m - 2, i + 1, m - 1}); ans.push_back({i, m - 2, i, m - 1, i + 1, m - 1}); a[i + 1][m - 2] ^= 1; } else if (a[i + 1][m - 1] == 1 ) { ans.push_back({i, m - 2, i + 1, m - 2, i, m - 1}); ans.push_back({i, m - 2, i, m - 1, i + 1, m - 1}); a[i + 1][m - 2] ^= 1; } } --m; } if (n & 1) { for (int i = 0; i < m - 1; i += 2) { if (a[n - 1][i] == 1 && a[n - 1][i + 1] == 1 ) { ans.push_back({n - 2, i, n - 1, i, n - 1, i + 1}); a[n - 2][i] ^= 1; } else if (a[n - 1][i] == 1 ) { ans.push_back({n - 2, i, n - 2, i + 1, n - 1, i + 1}); ans.push_back({n - 2, i, n - 1, i, n - 1, i + 1}); a[n - 2][i + 1] ^= 1; } else if (a[n - 1][i + 1] == 1 ) { ans.push_back({n - 2, i, n - 2, i + 1, n - 1, i}); ans.push_back({n - 2, i, n - 1, i, n - 1, i + 1}); a[n - 2][i + 1] ^= 1; } } --n; } for (int i = 0; i < n; i += 2) { for (int j = 0; j < m; j += 2) { for (int k = 0; k < 16; ++k) { work(i, j, k); if (a[i][j] == 0 && a[i][j + 1] == 0 && a[i + 1][j] == 0 && a[i + 1][j + 1] == 0 ) { for (int x = 0; x < 2; ++x) { for (int y = 0; y < 2; ++y) { if (k >> (x << 1 | y) & 1) { std::vector<int> p; for (int dx = 0; dx < 2; ++dx) { for (int dy = 0; dy < 2; ++dy) { if (x != dx || y != dy) { p.push_back(i + dx); p.push_back(j + dy); } } } ans.push_back({p[0], p[1], p[2], p[3], p[4], p[5]}); } } } break; } work(i, j, k); } } } std::cout << ans.size() << n ; for (auto v : ans) { std::cout << v.ax + 1 << << v.ay + 1 << ; std::cout << v.bx + 1 << << v.by + 1 << ; std::cout << v.cx + 1 << << v.cy + 1 << n ; } } int main() { std::ios_base::sync_with_stdio(false); std::cin.tie(0); int T = 1; std::cin >> T; while (T--) { solve(); } } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 100; int main() { long long n, m, a[MAXN], st[MAXN]; scanf( %I64d %I64d , &n, &m); st[0] = 1; for (int i = 1; i <= n; i++) st[i] = st[i - 1] * 2; int l = 0; int r = n; for (int i = 1; i < n; i++) { if (m > st[n - i - 1]) { a[r - 1] = i; r--; m -= st[n - i - 1]; } else { a[l] = i; l++; } } a[l] = n; for (int i = 0; i < n; i++) printf( %I64d , a[i]); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKINVLP_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__CLKINVLP_PP_SYMBOL_V
/**
* clkinvlp: Lower power Clock tree inverter.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__clkinvlp (
//# {{data|Data Signals}}
input A ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKINVLP_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; bool comp(pair<int, int> a, pair<int, int> b) { return (a.first == b.first) ? a.second < b.second : a.first < b.first; } long long int modInverse(long long int a) { long long int m = 1000000007; long long int y = 0, x = 1; while (a > 1) { long long int q = a / m; long long int t = m; m = a % m, a = t; t = y; y = x - q * y; x = t; } if (x < 0) x += 1000000007; return x; } long long int binpow(long long int a, long long int p) { if (p == 0) return 1; long long int ret = binpow(a, p / 2); ret *= ret; ret %= 1000000007; if (p % 2) { ret *= a; ret %= 1000000007; } return ret; } int f[54][54][54][54]; char a[100], b[100]; int n; bool check(int x, int y) { return (a[x] == a[y] || b[x] == b[y]); } int dfs(int i, int j, int l, int r) { if (f[i][j][l][r]) return 0; if (i == 3) return check(j, r) && check(l, r); if (check(l, r)) if (dfs(i - 1, i - 3, j, r)) return 1; if (check(i - 3, r)) if (dfs(i - 1, r, j, l)) return 1; f[i][j][l][r] = 1; return 0; } void solve() { cin >> n; for (int i = 1; i <= n; i++) cin >> a[i] >> b[i]; if (n == 1 || dfs(n, n - 2, n - 1, n)) cout << YES ; else cout << NO ; return; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; int t = 1; while (t--) { solve(); } } |
#include <bits/stdc++.h> using namespace std; long long a[100009], b[100009], s[100009]; signed main() { ios_base::sync_with_stdio(false), cin.tie(NULL); long long i, j, n, m, c; cin >> n >> m >> c; for (i = 1; i <= n; i++) cin >> a[i]; for (i = 1; i <= m; i++) cin >> b[i], s[i] = (b[i] + s[i - 1]); long long x = n - m; for (i = 1; i <= n; i++) { long long t = min(i, m); long long g = min(i, min(n + 1 - i, x + 1)); long long y = s[t] - s[max(t - g, 0ll)]; a[i] = (a[i] + y) % c; } for (i = 1; i <= n; i++) cout << a[i] << ; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; using pii = pair<int, int>; using pll = pair<ll, ll>; using ld = long double; const int mod = 1e9 + 7; const ll inf = 2e9; const ll INF = 2e18; const ld EPS = 1e-7; const int N = 1e5 + 55; ll sx[N], sy[N]; void solve() { int n, m; cin >> n >> m; vector<vector<int>> a(n, vector<int>(m)); for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { cin >> a[i][j]; sx[i] += a[i][j]; sy[j] += a[i][j]; } } ll mx = 0; vector<ll> v; for (int i = 0; i < n; ++i) { v.clear(); for (int j = 0; j < m; ++j) { v.push_back(sy[j] - a[i][j]); sort(v.rbegin(), v.rend()); while (v.size() > 3) { v.pop_back(); } } ll cur = sx[i]; for (ll a : v) { cur += a; } mx = max(mx, cur); } for (int j = 0; j < m; ++j) { v.clear(); for (int i = 0; i < n; ++i) { v.push_back(sx[i] - a[i][j]); sort(v.rbegin(), v.rend()); while (v.size() > 3) { v.pop_back(); } } ll cur = sy[j]; for (ll a : v) { cur += a; } mx = max(mx, cur); } if (n > m) { for (int i = 0; i < m; ++i) { for (int k = i + 1; k < m; ++k) { v.clear(); for (int j = 0; j < n; ++j) { v.push_back(sx[j] - a[j][i] - a[j][k]); sort(v.rbegin(), v.rend()); while (v.size() > 2) { v.pop_back(); } } ll cur = sy[i] + sy[k]; for (ll a : v) { cur += a; } mx = max(mx, cur); } } } else { for (int i = 0; i < n; ++i) { for (int k = i + 1; k < n; ++k) { v.clear(); for (int j = 0; j < m; ++j) { v.push_back(sy[j] - a[i][j] - a[k][j]); sort(v.rbegin(), v.rend()); while (v.size() > 2) { v.pop_back(); } } ll cur = sx[i] + sx[k]; for (ll a : v) { cur += a; } mx = max(mx, cur); } } } sort(sx, sx + n); sort(sy, sy + m); for (ll i = n - 1, sum = 0; i >= max(0, n - 4); --i) { sum += sx[i]; mx = max(mx, sum); } for (ll i = m - 1, sum = 0; i >= max(0, m - 4); --i) { sum += sy[i]; mx = max(mx, sum); } cout << mx; } int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); ; int tt = 1; while (tt--) { solve(); cout << n ; } } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Case Western Reserve University
// Engineer: Matt McConnell
//
// Create Date: 22:14:00 09/09/2017
// Project Name: EECS301 Digital Design
// Design Name: Lab #4 Project
// Module Name: Calculator_Full_Adder
// Target Devices: Altera Cyclone V
// Tool versions: Quartus v17.0
// Description: Calculator Full Adder
//
// Dependencies:
//
//////////////////////////////////////////////////////////////////////////////////
module Calculator_Full_Adder
#(
parameter WIDTH = 4
)
(
// Operand Signals
input [WIDTH-1:0] A,
input [WIDTH-1:0] B,
input CIN,
// Result Signals
output [WIDTH-1:0] RES,
output COUT
);
wire signed [WIDTH:0] op_a;
wire signed [WIDTH:0] op_b;
//
// Sign Extend Input Data
//
assign op_a = { A[WIDTH-1], A };
assign op_b = { B[WIDTH-1], B };
//
// Signed Adder with Carry-In
//
assign { COUT, RES } = op_a + op_b + CIN;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int a[100001], b[100001]; int n, i, x, y; cin >> n; for (i = 0; i < n; i++) { cin >> a[i]; b[i] = a[i]; } sort(b, b + n); x = 0; while (a[x] == b[x] && x < n - 1) { x++; } y = n - 1; while (a[y] == b[y] && y > 0) { y--; } if (x > y) { x = 0; y = 0; } for (i = 0; i <= (y - x) / 2; i++) { swap(a[x + i], a[y - i]); } for (i = 0; i < n; i++) if (a[i] != b[i]) { i = n + 10; } if (i < n + 10) { cout << yes << endl; cout << x + 1 << << y + 1; } else { cout << no << endl; } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAPMET1_BEHAVIORAL_V
`define SKY130_FD_SC_MS__TAPMET1_BEHAVIORAL_V
/**
* tapmet1: Tap cell with isolated power and ground connections.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__tapmet1 ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAPMET1_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A22OI_SYMBOL_V
`define SKY130_FD_SC_LP__A22OI_SYMBOL_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a22oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A22OI_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n, p; cin >> n >> p; int cnt = 0; for (int i = 1; i < n; ++i) { for (int j = i + 1; j <= n; ++j) { if (cnt == 2 * n + p) break; cout << i << << j << n ; cnt++; } } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { string a, b; int mini = INT_MAX; cin >> a >> b; int az = a.size(); for (int i = -2000; i <= az; i++) { int ans = b.size(); for (int j = 0; j < b.size(); j++) { ans -= (i + j >= 0 && i + j < a.size() && a[i + j] == b[j]); } mini = min(mini, ans); } cout << mini; return 0; } |
#include <bits/stdc++.h> using namespace std; typedef pair<int, int> PII; long long qpow(long long a, long long b, long long m) { long long ans = 1; while (b) { if (b & 1) ans = ans * a % m; a = a * a % m, b >>= 1; } return ans; } long long qpow(long long a, long long b) { long long ans = 1; while (b) { if (b & 1) ans = ans * a; a = a * a, b >>= 1; } return ans; } long long qmul(long long a, long long b, long long m) { long long res = 0; while (b > 0) { if (b & 1) res = (res + a) % m; a = (a + a) % m; b >>= 1; } return res; } long long gcd(long long a, long long b) { return b == 0 ? a : gcd(b, a % b); } long long lcm(long long a, long long b) { return a / gcd(a, b) * b; } long long inv(long long t, long long p) { return t == 1 ? 1 : (p - p / t) * inv(p % t, p) % p; } long long exgcd(long long a, long long b, long long &x, long long &y) { if (b == 0) { x = 1; y = 0; return a; } long long r = exgcd(b, a % b, y, x); y -= (a / b) * x; return r; } long long inv1(long long a, long long p) { long long d, x, y; d = exgcd(a, p, x, y); return d == 1 ? (x % p + p) % p : -1; } template <typename T, typename B> T Add(T a, B b, long long m) { return a + b >= m ? (a + b) % m : a + b; } template <typename T, typename B> T Sub(T a, B b, long long m) { return a - b < 0 ? (a - b + m) % m : a - b; } template <class T> void _sf(T &x) { cin >> x; } void _sf(int &x) { scanf( %d , &x); } void _sf(long long &x) { scanf( %lld , &x); } void _sf(double &x) { scanf( %lf , &x); } void _sf(char &x) { scanf( %c , &x); } void _sf(char *x) { scanf( %s , x); } void sf() {} template <class T, class... U> void sf(T &head, U &...tail) { _sf(head); sf(tail...); } template <class T> void _pf(const T &x) { cout << x; } void _pf(const int &x) { printf( %d , x); } void _pf(const long long &x) { printf( %lld , x); } void _pf(const double &x) { printf( %.16f , x); } void _pf(const char &x) { putchar(x); } void _pf(const char *x) { printf( %s , x); } template <class T, class U> void _pf(const pair<T, U> &x) { pf(x.first); putchar( ); pf(x.second); } template <class T> void _pf(const vector<T> &x) { for (auto i = x.begin(); i != x.end(); _pf(*i++)) if (i != x.cbegin()) putchar( ); } void pf() {} template <class T, class... U> void pf(const T &head, const U &...tail) { _pf(head); putchar(sizeof...(tail) ? : n ); pf(tail...); } template <typename T> inline void read(T &x) { x = 0; static int p; p = 1; static char c; c = getchar(); while (!isdigit(c)) { if (c == - ) p = -1; c = getchar(); } while (isdigit(c)) { x = (x << 1) + (x << 3) + (c - 48); c = getchar(); } x *= p; } const bool IOS = false; const double PI = acos(-1); const double eps = 1e-8; const long long linf = 0x3f3f3f3f3f3f3f3f; const long long INV2 = 500000004; const long long mod = 1e9 + 7; const int inf = 0x3f3f3f3f; const int maxn = 1e6 + 100; char s1[maxn], s2[maxn]; long long a[maxn], b[maxn]; void init() { a[0] = b[0] = 1; for (int i = 1; i < maxn; ++i) { a[i] = (a[i - 1] * i) % mod; } b[maxn - 1] = qpow(a[maxn - 1], mod - 2, mod); for (int i = maxn - 1; i > 0; i--) b[i - 1] = b[i] * i % mod; } long long C(long long n, long long m) { if (n < m) return 0; return a[n] * b[m] % mod * b[n - m] % mod; } int cnt[256]; long long calc(char s[], int n) { memset(cnt, 0, sizeof(cnt)); for (int i = 1; i <= n; ++i) cnt[s1[i]]++; long long tmp = a[n]; for (int i = a ; i <= z ; ++i) tmp = tmp * b[cnt[i]] % mod; long long ret = 0; for (int i = 1; i <= n; ++i) { tmp = tmp * qpow(n - i + 1, mod - 2, mod) % mod; for (int j = a ; j < s[i]; ++j) if (cnt[j]) ret = (ret + tmp * cnt[j] % mod) % mod; tmp = tmp * cnt[s[i]] % mod; cnt[s[i]]--; if (cnt[s[i]] < 0) return ret; } return ret; } void Main(); int main() { if (IOS) std::ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); Main(); 0; return 0; } void Main() { init(); scanf( %s%s , s1 + 1, s2 + 1); int len = strlen(s1 + 1); long long res = calc(s2, len) - calc(s1, len); res--; res = (res % mod + mod) % mod; pf(res); } |
`default_nettype none
`timescale 1ns / 1ps
// The async_bridge core exposes an asynchronous, static RAM as a
// synchronous, Wishbone B4 compatible peripheral.
//
// NOTE: This module does not use the chip-enable input of the static
// RAM chip. It statically hardwires the _CE signal in an asserted
// state.
//
// NOTE: This module does not bind to inout pins. You must do this at
// the top-level, as how this is done will be FPGA-dependent.
//
// NOTE: This module exposes a STALL_O signal. However, this module
// currently never stalls the master. async_bridge will always
// acknowledge a transfer one cycle after it's registered.
module async_bridge(
input clk_i,
input reset_i,
input cyc_i,
input stb_i,
input we_i,
input [1:0] sel_i,
input [19:1] adr_i,
input [15:0] dat_i,
output ack_o,
output [15:0] dat_o,
output stall_o,
output _sram_ce,
output _sram_we,
output _sram_oe,
output _sram_ub,
output _sram_lb,
output [19:1] sram_a,
output [15:0] sram_d_out,
input [15:0] sram_d_in
);
reg transfer;
reg [1:0] selects;
reg write;
reg [15:0] data_in;
reg [19:1] address;
assign ack_o = transfer;
wire sram_we = transfer & write & ~clk_i;
wire sram_oe = transfer & ~write & ~clk_i;
assign _sram_ce = 0;
assign _sram_we = ~sram_we;
assign _sram_oe = ~sram_oe;
assign _sram_ub = ~selects[1];
assign _sram_lb = ~selects[0];
assign dat_o = sram_oe ? sram_d_in : 0;
assign sram_a = address;
assign sram_d_out = data_in;
assign stall_o = 0;
always @(posedge clk_i) begin
transfer <= cyc_i & stb_i;
selects <= sel_i;
write <= we_i;
address <= adr_i;
data_in <= dat_i;
end
endmodule
`ifndef SYNTHESIS
module async_bridge_tb();
reg clk_i, reset_i, cyc_i, stb_i, we_i;
reg [1:0] sel_i;
reg [19:1] adr_i;
reg [15:0] dat_i;
wire ack_o;
wire _sram_we, _sram_oe, _sram_ub, _sram_lb;
wire [15:0] dat_o, sram_d_out;
wire [19:1] sram_a;
async_bridge rc(
.clk_i(clk_i),
.reset_i(reset_i),
.cyc_i(cyc_i),
.stb_i(stb_i),
.we_i(we_i),
.sel_i(sel_i),
.adr_i(adr_i),
.ack_o(ack_o),
.dat_o(dat_o),
.dat_i(dat_i),
._sram_we(_sram_we),
._sram_oe(_sram_oe),
._sram_ub(_sram_ub),
._sram_lb(_sram_lb),
.sram_a(sram_a),
.sram_d_in(16'hF00D),
.sram_d_out(sram_d_out)
);
always begin
#5 clk_i <= ~clk_i;
end
initial begin
$dumpfile("async_bridge.vcd");
$dumpvars;
{clk_i, reset_i, cyc_i, stb_i, we_i, sel_i, adr_i, dat_i} = 0;
wait(~clk_i); wait(clk_i);
reset_i <= 1;
wait(~clk_i); wait(clk_i);
adr_i <= 0;
reset_i <= 0;
wait(~clk_i); wait(clk_i);
cyc_i <= 1;
stb_i <= 1;
wait(~clk_i); wait(clk_i);
stb_i <= 0;
wait(~clk_i); wait(clk_i);
stb_i <= 1;
wait(~clk_i); wait(clk_i);
sel_i <= 2'b01;
wait(~clk_i); wait(clk_i);
sel_i <= 2'b10;
wait(~clk_i); wait(clk_i);
sel_i <= 2'b11;
stb_i <= 0;
wait(~clk_i); wait(clk_i);
cyc_i <= 0;
sel_i <= 0;
wait(~clk_i); wait(clk_i);
wait(~clk_i); wait(clk_i);
cyc_i <= 1;
stb_i <= 1;
adr_i <= 20'h00000;
we_i <= 0;
wait(~clk_i); wait(clk_i);
adr_i <= 20'h00001;
wait(~clk_i); wait(clk_i);
adr_i <= 20'h00002;
wait(~clk_i); wait(clk_i);
adr_i <= 20'h00003;
wait(~clk_i); wait(clk_i);
adr_i <= 20'h00000;
we_i <= 1;
wait(~clk_i); wait(clk_i);
adr_i <= 20'h00001;
wait(~clk_i); wait(clk_i);
adr_i <= 20'h00002;
wait(~clk_i); wait(clk_i);
adr_i <= 20'h00003;
wait(~clk_i); wait(clk_i);
cyc_i <= 0;
stb_i <= 0;
#100;
$stop;
end
endmodule
`endif
|
Subsets and Splits