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`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////
//
// This file is part of Descrypt Ztex Bruteforcer
// Copyright (C) 2014 Alexey Osipov <giftsungiv3n at gmail dot com>
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
////////////////////////////////////////////////////////////////////////
module SP_block_test;
// Inputs
reg [47:0] Din;
// Outputs
wire [31:0] P_S;
// Instantiate the Unit Under Test (UUT)
SP_block uut (
.Din(Din),
.P_S(P_S)
);
initial begin
// Initialize Inputs
Din = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
Din = 48'b011000010001011110111010100001100110010100100111;
#100;
if(!(P_S == 32'b00100011010010101010100110111011)) $finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; vector<long long> a, b; for (int i = 0; i < n; i++) { long long temp; cin >> temp; long long p = sqrt(temp); if (p * p == temp) a.push_back(temp); else b.push_back(temp); } if (a.size() > b.size()) { int rem = a.size() - n / 2; for (int i = 0; i < a.size(); i++) { if (a[i] == 0) a[i] = 2; else a[i] = 1; } sort(a.begin(), a.end()); long long c = 0; for (int i = 0; i < a.size(); i++) { if (rem == 0) break; c += a[i]; rem--; } cout << c << n ; } else if (b.size() > a.size()) { int rem = b.size() - n / 2; for (int i = 0; i < b.size(); i++) { long long p = sqrt(b[i]); b[i] = min(abs(p * p - b[i]), abs((p + 1) * (p + 1) - b[i])); } sort(b.begin(), b.end()); long long c = 0; for (int i = 0; i < b.size(); i++) { if (rem == 0) break; c += b[i]; rem--; } cout << c << n ; } else cout << 0 n ; return 0; } |
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Parameter LE tells us if we are little-endian.
// Little-endian means send lower 16 bits first.
// Default is big endian (network order), send upper bits first.
module fifo72_to_fifo36
#(parameter LE=0)
(input clk, input reset, input clear,
input [71:0] f72_datain,
input f72_src_rdy_i,
output f72_dst_rdy_o,
output [35:0] f36_dataout,
output f36_src_rdy_o,
input f36_dst_rdy_i );
wire [35:0] f36_data_int;
wire f36_src_rdy_int, f36_dst_rdy_int;
wire [71:0] f72_data_int;
wire f72_src_rdy_int, f72_dst_rdy_int;
// Shortfifo on input to guarantee no deadlock
fifo_short #(.WIDTH(72)) head_fifo
(.clk(clk),.reset(reset),.clear(clear),
.datain(f72_datain), .src_rdy_i(f72_src_rdy_i), .dst_rdy_o(f72_dst_rdy_o),
.dataout(f72_data_int), .src_rdy_o(f72_src_rdy_int), .dst_rdy_i(f72_dst_rdy_int),
.space(),.occupied() );
// Main fifo72_to_fifo36, needs shortfifos to guarantee no deadlock
wire [2:0] f72_occ_int = f72_data_int[68:66];
wire f72_sof_int = f72_data_int[64];
wire f72_eof_int = f72_data_int[65];
reg phase;
wire half_line = f72_eof_int & ( (f72_occ_int==1)|(f72_occ_int==2)|(f72_occ_int==3)|(f72_occ_int==4) );
assign f36_data_int[31:0] = (LE ^ phase) ? f72_data_int[31:0] : f72_data_int[63:32];
assign f36_data_int[32] = phase ? 0 : f72_sof_int;
assign f36_data_int[33] = phase ? f72_eof_int : half_line;
assign f36_data_int[35:34] = f36_data_int[33] ? f72_occ_int[1:0] : 2'b00;
assign f36_src_rdy_int = f72_src_rdy_int;
assign f72_dst_rdy_int = (phase | half_line) & f36_dst_rdy_int;
wire f36_xfer = f36_src_rdy_int & f36_dst_rdy_int;
wire f72_xfer = f72_src_rdy_int & f72_dst_rdy_int;
always @(posedge clk)
if(reset)
phase <= 0;
else if(f72_xfer)
phase <= 0;
else if(f36_xfer)
phase <= 1;
// Shortfifo on output to guarantee no deadlock
fifo_short #(.WIDTH(36)) tail_fifo
(.clk(clk),.reset(reset),.clear(clear),
.datain(f36_data_int), .src_rdy_i(f36_src_rdy_int), .dst_rdy_o(f36_dst_rdy_int),
.dataout(f36_dataout), .src_rdy_o(f36_src_rdy_o), .dst_rdy_i(f36_dst_rdy_i),
.space(),.occupied() );
endmodule // fifo72_to_fifo36
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A211OI_BLACKBOX_V
`define SKY130_FD_SC_HDLL__A211OI_BLACKBOX_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a211oi (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A211OI_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O221AI_TB_V
`define SKY130_FD_SC_LS__O221AI_TB_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o221ai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 B1 = 1'b1;
#260 B2 = 1'b1;
#280 C1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 B1 = 1'b0;
#440 B2 = 1'b0;
#460 C1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 C1 = 1'b1;
#660 B2 = 1'b1;
#680 B1 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 C1 = 1'bx;
#840 B2 = 1'bx;
#860 B1 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_ls__o221ai dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O221AI_TB_V
|
#include <bits/stdc++.h> using namespace std; int ans[101000], mark[101000]; char s[101000]; int n, top, now, n_; int main() { do s[++n_] = getchar(); while (s[n_] != = ); scanf( %d , &n); mark[1] = 0; top = 1; for (int i = 3; i < n_; i += 4) mark[++top] = (s[i] == - ); now = 0; for (int i = 1; i <= top; i++) ans[i] = 1; for (int i = 1; i <= top; i++) if (mark[i]) now--; else now++; while (now != n) { if (now < n) { int q = 0; for (int i = 1; i <= top; i++) if (!mark[i] && ans[i] < n) { q = i; break; } if (!q) { printf( Impossible ); return 0; } int inc = min(n - ans[q], n - now); ans[q] += inc; now += inc; } else { int q = 0; for (int i = 1; i <= top; i++) if (mark[i] && ans[i] < n) { q = i; break; } if (!q) { printf( Impossible ); return 0; } int inc = min(n - ans[q], now - n); ans[q] += inc; now -= inc; } } printf( Possible n ); printf( %d , ans[1]); for (int i = 2; i <= top; i++) { putchar( ); if (mark[i]) putchar( - ); else putchar( + ); putchar( ); printf( %d , ans[i]); } printf( = %d , n); return 0; } |
#include <bits/stdc++.h> using namespace std; string tostr(int n) { stringstream rr; rr << n; return rr.str(); } long long qpow(long long n, long long k) { long long ans = 1; while (k) { if (k & 1) ans = ans * n; n = n * n; k >>= 1; } return ans; } const int mod = 1e9 + 7; const int mxn = 1e5 + 9; const int eps = 1e-9; int main() { ios_base::sync_with_stdio(false), cin.tie(NULL); int i, j, k, l, st; vector<char> v; string s, p; cin >> s; if (s[0] == - ) st = 1, cout << ( ; else st = 0; cout << $ ; p = s.substr(st); if (p.find( . ) == -1) for (i = p.size() - 1; i >= 0; i--) { v.push_back(p[i]); if ((p.size() - i) % 3 == 0 && i != 0) v.push_back( , ); } else for (i = p.find( . ) - 1; i >= 0; i--) { v.push_back(p[i]); if ((p.find( . ) - i) % 3 == 0 && i != 0) v.push_back( , ); } reverse(v.begin(), v.end()); for (auto c : v) cout << c; cout << . ; if (p.find( . ) == -1) cout << 00 ; else { cout << p[p.find( . ) + 1]; if (p[p.find( . ) + 2] != 0 ) cout << p[p.find( . ) + 2]; else cout << 0 ; } if (st == 1) cout << ) ; return 0; } |
#include <bits/stdc++.h> int main() { int N, Q; scanf( %d%d , &N, &Q); int et[N + 1]; memset(et, -1, sizeof(et)); while (Q-- > 0) { int t, k, d; scanf( %d%d%d , &t, &k, &d); int ans = -1; int as = 0; for (int i = 1; i <= N; i++) { if (t > et[i]) et[i] = -1; if (et[i] == -1) as++; } if (as >= k) { ans = 0; for (int i = 1; i <= N && k > 0; i++) { if (et[i] == -1) { ans += i; k--; et[i] = t + d - 1; } } } printf( %d n , ans); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; int arr[n]; for (int i = 0; i < n; i++) cin >> arr[i]; int cnt[n + 1]; memset(cnt, 0, sizeof cnt); cnt[0] = 1; int lvl = 0; int ind = 1; while (ind < n) { lvl++; for (int i = 0; i < cnt[lvl - 1] && i < n; i++) { int last = -1; while (ind < n && arr[ind] > last) { cnt[lvl]++; last = arr[ind]; ind++; } } } cout << lvl << endl; } } |
#include <bits/stdc++.h> int main() { char a[100009], c; int j = 0, i; while ((c = getchar()) != n ) { if (j == 0) { a[j] = c; j++; } else { if (a[j - 1] == c) { j--; } else { a[j] = c; j++; } } } if (j == 0) { printf( Yes n ); } else { printf( No n ); } } |
#include <bits/stdc++.h> using namespace std; long long a[200005]; int func(long a, long long x, long long f) { if (a - x > 0) { int tem; tem = (a - x) / (f + x); if (tem * (f + x) == (a - x)) return (a - x) / (f + x); else return (a - x) / (f + x) + 1; } else return 0; } int main() { int n; cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; long long x, f; cin >> x >> f; long long ans = 0; for (int i = 0; i < n; i++) { int tem = func(a[i], x, f); ans += tem; } cout << ans * f << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int i, j, k; j = (n * 2) - 1; cout << j << << 2 ; cout << endl << 1 2 ; } |
/***********************************************************************
File: pcim_top.v
Rev: 3.1.161
This is the top-level template file for Verilog designs.
The user should place his backend application design in the
userapp module.
Copyright (c) 2005-2007 Xilinx, Inc. All rights reserved.
***********************************************************************/
//`include "defines.v"
module pcim_top (
inout [31:0] AD, // PCI ports -- do not modify names!
inout [3:0] CBE,
inout PAR,
inout FRAME_N,
inout TRDY_N,
inout IRDY_N,
inout STOP_N,
inout DEVSEL_N,
input IDSEL,
output INTR_A,
inout PERR_N,
inout SERR_N,
output REQ_N,
input GNT_N,
input RST_N,
input PCLK, // Add user ports here
// Additional ports
output reg_hit, // Indicates a hit on the CPCI registers
output cnet_hit, // Indicates a hit on the CNET address range
output reg_we, // Write enable signal for CPCI registers
output cnet_we, // Write enable signal for CNET
output [31:0] pci_addr, // The address of the current transaction
output [31:0] pci_data, // The current data DWORD
output pci_data_vld, // Data on pci_data is valid
output [3:0] pci_be, // Byte enables for current transaction
output pci_retry, // Retry signal from CSRs
output pci_fatal, // Fatal signal from CSRs
input [31:0] reg_data, // Data to be read for registers
input [31:0] cnet_data, // Data to be read for CNET
input cnet_retry, // Generate a retry for CNET
input cnet_reprog, // Is CNET being reprogrammed?
input reg_vld, // Is the data on reg_data valid?
input cnet_vld, // Is the data on cnet_data valid?
input dma_vld, // Is the data on dma_data valid?
input intr_req, // Interrupt request
input dma_request, // Transaction request for DMA
input [31:0] dma_data, // Data from DMA block
input [3:0] dma_cbe, // Command/byte enables for DMA block
output dma_data_vld, // Indicates data should be captured
output dma_src_en, // Next piece of data should be provided
// on dma_data
input dma_wrdn, // Logic high = Write, low = read
input dma_complete, // Complete signal
output dma_lat_timeout, // Latency timer has expired
output dma_addr_st, // Indicates that the core is
// currently in the address phase
output dma_data_st, // Core in the data state
output clk, // Output clock signal
output pci_reset // Reset signal
);
// synthesis syn_edif_bit_format = "%u<%i>"
// synthesis syn_edif_scalar_format = "%u"
// synthesis syn_noclockbuf = 1
// synthesis syn_hier = "hard"
// Internal buses -- do not modify names!
wire [255:0] CFG;
wire [31:0] ADDR;
wire [31:0] ADIO;
wire [7:0] BASE_HIT;
wire [3:0] S_CBE;
wire [15:0] PCI_CMD;
wire [3:0] M_CBE;
wire [39:0] CSR;
wire [31:0] SUB_DATA;
// Instantiation of PCI Interface -- do not modify names!
pcim_lc PCI_CORE (
.AD_IO ( AD ),
.CBE_IO ( CBE ),
.PAR_IO ( PAR ),
.FRAME_IO ( FRAME_N ),
.TRDY_IO ( TRDY_N ),
.IRDY_IO ( IRDY_N ),
.STOP_IO ( STOP_N ),
.DEVSEL_IO ( DEVSEL_N ),
.IDSEL_I ( IDSEL ),
.INTA_O ( INTR_A ),
.PERR_IO ( PERR_N ),
.SERR_IO ( SERR_N ),
.REQ_O ( REQ_N ),
.GNT_I ( GNT_N ),
.RST_I ( RST_N ),
.PCLK ( PCLK ),
.FRAMEQ_N ( FRAMEQ_N ),
.TRDYQ_N ( TRDYQ_N ),
.IRDYQ_N ( IRDYQ_N ),
.STOPQ_N ( STOPQ_N ),
.DEVSELQ_N ( DEVSELQ_N ),
.ADDR ( ADDR ),
.ADIO ( ADIO ),
.CFG_VLD ( CFG_VLD ),
.CFG_HIT ( CFG_HIT ),
.C_TERM ( C_TERM ),
.C_READY ( C_READY ),
.ADDR_VLD ( ADDR_VLD ),
.BASE_HIT ( BASE_HIT ),
.S_TERM ( S_TERM ),
.S_READY ( S_READY ),
.S_ABORT ( S_ABORT ),
.S_WRDN ( S_WRDN ),
.S_SRC_EN ( S_SRC_EN ),
.S_DATA_VLD ( S_DATA_VLD ),
.S_CBE ( S_CBE ),
.PCI_CMD ( PCI_CMD ),
.REQUEST ( REQUEST ),
.REQUESTHOLD ( REQUESTHOLD ),
.COMPLETE ( COMPLETE ),
.M_WRDN ( M_WRDN ),
.M_READY ( M_READY ),
.M_SRC_EN ( M_SRC_EN ),
.M_DATA_VLD ( M_DATA_VLD ),
.M_CBE ( M_CBE ),
.TIME_OUT ( TIME_OUT ),
.CFG_SELF ( CFG_SELF ),
.M_DATA ( M_DATA ),
.DR_BUS ( DR_BUS ),
.I_IDLE ( I_IDLE ),
.M_ADDR_N ( M_ADDR_N ),
.IDLE ( IDLE ),
.B_BUSY ( B_BUSY ),
.S_DATA ( S_DATA ),
.BACKOFF ( BACKOFF ),
.INTR_N ( INTR_N ),
.PERRQ_N ( PERRQ_N ),
.SERRQ_N ( SERRQ_N ),
.KEEPOUT ( KEEPOUT ),
.CSR ( CSR ),
.SUB_DATA ( SUB_DATA ),
.CFG ( CFG ),
.RST ( RST ),
.CLK ( clk )
);
// Instantiation of the configuration module
cfg CFG_INST (
.CFG ( CFG )
);
// Instantiation of userapp back-end application template
pci_userapp USER_APP (
.FRAMEQ_N ( FRAMEQ_N ),
.TRDYQ_N ( TRDYQ_N ),
.IRDYQ_N ( IRDYQ_N ),
.STOPQ_N ( STOPQ_N ),
.DEVSELQ_N ( DEVSELQ_N ),
.ADDR ( ADDR ),
.ADIO ( ADIO ),
.CFG_VLD ( CFG_VLD ),
.CFG_HIT ( CFG_HIT ),
.C_TERM ( C_TERM ),
.C_READY ( C_READY ),
.ADDR_VLD ( ADDR_VLD ),
.BASE_HIT ( BASE_HIT ),
.S_TERM ( S_TERM ),
.S_READY ( S_READY ),
.S_ABORT ( S_ABORT ),
.S_WRDN ( S_WRDN ),
.S_SRC_EN ( S_SRC_EN ),
.S_DATA_VLD ( S_DATA_VLD ),
.S_CBE ( S_CBE ),
.PCI_CMD ( PCI_CMD ),
.REQUEST ( REQUEST ),
.REQUESTHOLD ( REQUESTHOLD ),
.COMPLETE ( COMPLETE ),
.M_WRDN ( M_WRDN ),
.M_READY ( M_READY ),
.M_SRC_EN ( M_SRC_EN ),
.M_DATA_VLD ( M_DATA_VLD ),
.M_CBE ( M_CBE ),
.TIME_OUT ( TIME_OUT ),
.CFG_SELF ( CFG_SELF ),
.M_DATA ( M_DATA ),
.DR_BUS ( DR_BUS ),
.I_IDLE ( I_IDLE ),
.M_ADDR_N ( M_ADDR_N ),
.IDLE ( IDLE ),
.B_BUSY ( B_BUSY ),
.S_DATA ( S_DATA ),
.BACKOFF ( BACKOFF ),
.INTR_N ( INTR_N ),
.PERRQ_N ( PERRQ_N ),
.SERRQ_N ( SERRQ_N ),
.KEEPOUT ( KEEPOUT ),
.CSR ( CSR ),
.SUB_DATA ( SUB_DATA ),
.CFG ( CFG ),
.RST ( RST ),
.CLK ( clk ),
.reg_hit (reg_hit),
.cnet_hit (cnet_hit),
.reg_we (reg_we),
.cnet_we (cnet_we),
.pci_addr (pci_addr),
.pci_data (pci_data),
.pci_data_vld (pci_data_vld),
.pci_be (pci_be),
.pci_retry (pci_retry),
.pci_fatal (pci_fatal),
.reg_data (reg_data),
.cnet_data (cnet_data),
.cnet_retry (cnet_retry),
.cnet_reprog (cnet_reprog),
.reg_vld (reg_vld),
.cnet_vld (cnet_vld),
.dma_vld (dma_vld),
.intr_req (intr_req),
.dma_request (dma_request),
.dma_data (dma_data),
.dma_cbe (dma_cbe),
.dma_data_vld (dma_data_vld),
.dma_src_en (dma_src_en),
.dma_wrdn (dma_wrdn),
.dma_complete (dma_complete),
.dma_lat_timeout (dma_lat_timeout),
.dma_addr_st (dma_addr_st),
.dma_data_st (dma_data_st)
);
assign pci_reset = RST;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 200005; vector<int> v[N]; int n, kk; int dis[N], ans[N]; void dfs1(int pos, int fa) { for (auto &i : v[pos]) if (i != fa) dfs1(i, pos), dis[pos] = max(dis[pos], dis[i]); ++dis[pos]; } bool dfs2(int pos, int fa, const multiset<int, greater<int>> &mt) { multiset<int, greater<int>> d; int mx = 0; for (auto &i : v[pos]) if (i != fa) d.insert(dis[i]); else mx = 1; bool fs = 1; for (auto &i : mt) { if (i == dis[pos] && fs) { fs = 0; continue; } mx = i + 1; break; } if (mx) d.insert(mx); while (d.size() > 3) d.erase(prev(d.end())); if (d.size() > 2 && *next(d.begin()) + *next(next(d.begin())) >= kk - 1) { cout << No << endl; return 0; } for (auto &i : v[pos]) if (i != fa && !dfs2(i, pos, d)) return 0; return 1; } int dep[N], f[N]; void dfs(int pos, int fa) { dep[pos] = dep[fa] + 1; f[pos] = fa; for (auto &i : v[pos]) if (i != fa) dfs(i, pos); } void dfs3(int pos, int fa, int cur, int dd) { ans[pos] = cur; for (auto &i : v[pos]) if (i != fa) dfs3(i, pos, (cur + dd + kk) % kk, dd); } int main() { ios::sync_with_stdio(false); cin >> n >> kk; int t1, t2; for (int i = 1; i < n; i++) { cin >> t1 >> t2; v[t1].push_back(t2); v[t2].push_back(t1); } dfs1(1, 0); if (kk != 2 && !dfs2(1, 0, {})) return 0; cout << Yes << endl; if (kk == 2) { dfs3(1, 0, 0, 1); for (int i = 1; i <= n; i++) cout << ans[i] + 1 << ; return 0; } dfs(1, 0); t1 = max_element(dep + 1, dep + n + 1) - dep; dfs(t1, 0); t2 = max_element(dep + 1, dep + n + 1) - dep; vector<int> d{t2}; while (f[t2]) d.push_back(t2 = f[t2]); int mid = (d.size() + 1) / 2 - 1; dfs3(d[mid], d[mid + 1], mid % kk, -1); dfs3(d[mid + 1], d[mid], (mid + 1) % kk, 1); for (int i = 1; i <= n; i++) cout << ans[i] + 1 << ; return 0; } |
#include <bits/stdc++.h> using namespace std; namespace Flandre_Scarlet { int I() { char c = getchar(); int x = 0; int f = 1; while (c < 0 or c > 9 ) f = (c == - ) ? -1 : 1, c = getchar(); while (c >= 0 and c <= 9 ) x = (x << 1) + (x << 3) + (c ^ 48), c = getchar(); return (x = (f == 1) ? x : -x); } template <typename T> void Rd(T& arg) { arg = I(); } template <typename T, typename... Types> void Rd(T& arg, Types&... args) { arg = I(); Rd(args...); } void RA(int* p, int n) { for (int i = 1; i <= n; ++i) *p = I(), ++p; } int n, a[200005]; void Input() { n = I(); RA(a + 1, n); } int st[200005][18]; short lg[200005]; inline int gcd(int a, int b) { while (b) { a ^= b ^= a ^= b; b %= a; } return a; } void SparseTable() { memset(lg, -1, sizeof(lg)); for (int i = 0; i <= 17; ++i) if ((1 << i) <= n) lg[1 << i] = i; for (int i = 1; i <= n; ++i) if (lg[i] == -1) lg[i] = lg[i - 1]; for (int i = 1; i <= n; ++i) st[i][0] = a[i]; for (int j = 1; j <= 17; ++j) { for (int i = 1; i <= n; ++i) st[i][j] = gcd(st[i][j - 1], st[i + (1 << (j - 1))][j - 1]); } } inline int Query(int l, int r) { int k = lg[r - l + 1]; return gcd(st[l][k], st[r - (1 << k) + 1][k]); } unordered_map<int, long long> ans; int GetNex(int l, int g) { if (Query(l, n) == g) return n + 1; int cur = l; for (int i = 17; i >= 0; --i) if (st[cur][i] % g == 0) cur = cur + (1 << i); return cur; } void Soviet() { SparseTable(); for (int i = n; i >= 1; --i) { int g = a[i]; for (register int l = i, r; l <= n; l = r) { r = GetNex(i, g); ans[g] += r - l; if (r == n + 1) break; g = gcd(g, a[r]); } } int q = I(); for (int i = 1; i <= q; ++i) printf( %lld n , ans[I()]); } void IsMyWife() { Input(); Soviet(); } } // namespace Flandre_Scarlet int main() { Flandre_Scarlet::IsMyWife(); getchar(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int oo = 1e9 + 9; const long long inf = 1e18 + 18; const int max6 = 1e6 + 6; const int modx = 1e9 + 123; const int mody = 997; const int base = 137; int t[max6]; int n, k; bool ok(int l, int r) { int cnt = 0; for (int i = l; i <= r; ++i) cnt += t[i] == 1; if (cnt) return false; int cur = 0; for (int i = r + 1; i <= n; ++i) { if (t[i] == 2) cur++; else cur = 0; if (cur > k) return false; } for (int i = 1; i < l; ++i) { if (t[i] == 2) cur++; else cur = 0; if (cur > k) return false; } return true; } int main() { cin >> n >> k; string s; cin >> s; for (int i = 1; i <= n; ++i) if (s[i - 1] == Y ) t[i] = 1; else if (s[i - 1] == N ) t[i] = 2; else if (s[i - 1] == ? ) t[i] = 3; int res = 0; for (int i = 1; i <= n; ++i) if (i == 1 || t[i - 1] == 1 || t[i - 1] == 3) { int j = i + k - 1; if (j == n || t[j + 1] == 1 || t[j + 1] == 3) if (ok(i, j)) res = 1; } cout << (res ? YES : NO ); } |
#include <bits/stdc++.h> #pragma GCC optimize( O2 ) using namespace std; int nrg, nrv; string s; bool gg(int pos) { if (pos < 2) return 0; return ((s[pos] >= 0 && s[pos] <= 9 ) && (s[pos - 1] >= 0 && s[pos - 1] <= 9 ) && (s[pos - 2] == . )); } deque<int> dg; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> s; for (int i = 0; i < s.size(); ++i) { if (s[i] >= a && s[i] <= z ) continue; int l = i; while (i < s.size() && !(s[i] >= a && s[i] <= z )) ++i; --i; int r = i; if (gg(r)) { nrv = nrv + (s[r] - 0 ) + 10 * (s[r - 1] - 0 ); r -= 3; } int ex = 1; while (r >= 0 && !(s[r] >= a && s[r] <= z )) { if (s[r] != . ) nrg = nrg + ex * (s[r] - 0 ), ex = ex * 10; --r; } } nrg += nrv / 100; nrv %= 100; do { dg.push_front(nrg % 10); nrg /= 10; } while (nrg); for (int i = 0; i < dg.size(); ++i) { if (i && (dg.size() - i) % 3 == 0) cout << . ; cout << dg[i]; } if (nrv) { cout << . ; if (nrv < 10) cout << 0 ; cout << nrv; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 5; bool isprime[N] = {1, 1, 0}; int sum[N] = {}; void YesIcan() { for (int i = 2; i * i <= N; ++i) { for (int j = i * i; j <= N; j += i) isprime[j] = true; } } int main() { YesIcan(); int a, b, k; cin >> a >> b >> k; for (int i = a; i <= b; ++i) { sum[i] = sum[i - 1]; if (!isprime[i]) ++sum[i]; } if (sum[b] < k) { cout << -1; return 0; } int i = a - 1, l = 1; for (; i <= b - l; ++i) { while (sum[i + l] - sum[i] < k && l <= b - a + 1 && i + l <= b) ++l; } cout << l; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O221A_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__O221A_PP_BLACKBOX_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o221a (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O221A_PP_BLACKBOX_V
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_t_e
//
// Generated
// by: wig
// on: Mon Oct 23 16:54:16 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bugver2006.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_t_e.v,v 1.1 2006/10/30 15:38:11 wig Exp $
// $Date: 2006/10/30 15:38:11 $
// $Log: inst_t_e.v,v $
// Revision 1.1 2006/10/30 15:38:11 wig
// Updated testcase bitsplice/rfe20060904a and added some bug testcases.
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.96 2006/10/23 08:31:06 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of inst_t_e
//
// No user `defines in this module
module inst_t_e
//
// Generated Module inst_t
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire only_low;
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_a
inst_a_e inst_a (
//__E_BAD_BOUNDS .only_low[__UNDEF__:1](only_low[__UNDEF__:1]) // Only ::low defined
);
// End of Generated Instance Port Map for inst_a
// Generated Instance Port Map for inst_b
inst_b_e inst_b (
//__E_BAD_BOUNDS .only_low[__UNDEF__:1](only_low[__UNDEF__:1]) // Only ::low defined
);
// End of Generated Instance Port Map for inst_b
endmodule
//
// End of Generated Module rtl of inst_t_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> int main() { long n, k, x, a, y; scanf( %ld %ld , &n, &k); a = n; x = n; while (x >= k) { y = x % k; x = x / k; a = a + x; x = x + y; } printf( %ld n , a); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__BUFINV_PP_SYMBOL_V
`define SKY130_FD_SC_LS__BUFINV_PP_SYMBOL_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__bufinv (
//# {{data|Data Signals}}
input A ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__BUFINV_PP_SYMBOL_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01:21:06 10/15/2013
// Design Name: Logica_Barra
// Module Name: C:/Users/Fabian/Documents/GitHub/taller-diseno-digital/Lab4/lab_pong/Test_Logica_Barra.v
// Project Name: lab_pong
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Logica_Barra
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Test_Logica_Barra;
// Inputs
reg clock;
reg reset;
reg actualizar_posicion;
reg revisar_bordes;
reg up_sync;
reg down_sync;
// Outputs
wire [8:0] barra_y;
// Instantiate the Unit Under Test (UUT)
Logica_Barra uut (
.clock(clock),
.reset(reset),
.actualizar_posicion(actualizar_posicion),
.revisar_bordes(revisar_bordes),
.up_sync(up_sync),
.down_sync(down_sync),
.barra_y(barra_y)
);
initial begin
// Initialize Inputs
clock = 0;
reset = 0;
actualizar_posicion = 0;
revisar_bordes = 0;
up_sync = 0;
down_sync = 1;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int m, n, N; cin >> m >> n; N = floor((m * n) / 2); cout << N; } |
//+FHDR------------------------------------------------------------------------
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
//GLADIC Open Source RTL
//-----------------------------------------------------------------------------
//FILE NAME :
//DEPARTMENT : IC Design / Verification
//AUTHOR : Felipe Fernandes da Costa
//AUTHOR’S EMAIL :
//-----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPTION
//1.0 YYYY-MM-DD name
//-----------------------------------------------------------------------------
//KEYWORDS : General file searching keywords, leave blank if none.
//-----------------------------------------------------------------------------
//PURPOSE : ECSS_E_ST_50_12C_31_july_2008
//-----------------------------------------------------------------------------
//PARAMETERS
//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
//e.g.DATA_WIDTH [32,16] : width of the data : 32:
//-----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy :
//Clock Domains :
//Critical Timing :
//Test Features :
//Asynchronous I/F :
//Scan Methodology :
//Instantiations :
//Synthesizable (y/n) :
//Other :
//-FHDR------------------------------------------------------------------------
module bit_capture_data(
input negedge_clk,
input posedge_clk,
input rx_resetn,
input rx_din,
output reg bit_d_0,//N
output reg bit_d_1,//P
output reg bit_d_2,//N
output reg bit_d_3,//P
output reg bit_d_4,//N
output reg bit_d_5,//P
output reg bit_d_6,//N
output reg bit_d_7,//P
output reg bit_d_8,//N
output reg bit_d_9//P
);
always@(posedge posedge_clk or negedge rx_resetn)
begin
if(!rx_resetn)
begin
bit_d_1 <= 1'b0;
bit_d_3 <= 1'b0;
bit_d_5 <= 1'b0;
bit_d_7 <= 1'b0;
bit_d_9 <= 1'b0;
end
else
begin
bit_d_1 <= rx_din;
bit_d_3 <= bit_d_1;
bit_d_5 <= bit_d_3;
bit_d_7 <= bit_d_5;
bit_d_9 <= bit_d_7;
end
end
always@(posedge negedge_clk or negedge rx_resetn)
begin
if(!rx_resetn)
begin
bit_d_0 <= 1'b0;
bit_d_2 <= 1'b0;
bit_d_4 <= 1'b0;
bit_d_6 <= 1'b0;
bit_d_8 <= 1'b0;
end
else
begin
bit_d_0 <= rx_din;
bit_d_2 <= bit_d_0;
bit_d_4 <= bit_d_2;
bit_d_6 <= bit_d_4;
bit_d_8 <= bit_d_6;
end
end
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for struct of ent_a
//
// Generated
// by: wig
// on: Fri Jul 7 06:37:54 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../bugver.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_a.v,v 1.4 2006/07/10 07:30:09 wig Exp $
// $Date: 2006/07/10 07:30:09 $
// $Log: ent_a.v,v $
// Revision 1.4 2006/07/10 07:30:09 wig
// Updated more testcasess.
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.91 2006/07/04 12:22:35 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module struct of ent_a
//
// No user `defines in this module
module ent_a
//
// Generated Module inst_a
//
(
p_mix_sc_sig_1_go,
p_mix_sc_sig_2_go,
p_mix_sc_sig_4_go
);
// Generated Module Outputs:
output p_mix_sc_sig_1_go;
output [31:0] p_mix_sc_sig_2_go;
output [31:0] p_mix_sc_sig_4_go;
// Generated Wires:
wire p_mix_sc_sig_1_go;
wire [31:0] p_mix_sc_sig_2_go;
wire [31:0] p_mix_sc_sig_4_go;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire sc_sig_1; // __W_PORT_SIGNAL_MAP_REQ
wire [31:0] sc_sig_2; // __W_PORT_SIGNAL_MAP_REQ
wire [31:0] sc_sig_4; // __W_PORT_SIGNAL_MAP_REQ
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
assign p_mix_sc_sig_1_go = sc_sig_1; // __I_O_BIT_PORT
assign p_mix_sc_sig_2_go = sc_sig_2; // __I_O_BUS_PORT
assign p_mix_sc_sig_4_go = sc_sig_4; // __I_O_BUS_PORT
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_aa
ent_aa inst_aa ( // is i_padframe / hier inst_aa inst_aa inst_a
.p_mix_sc_sig_2_go(sc_sig_2), // reverse orderreverse order
// multiline comments
.p_mix_sc_sig_4_go(sc_sig_4) // reverse order
// multiline comments
// line 3
// line 4
// line 5
// line 6
// line 7
// line 8
// line 9
// line 10
// ...[cut]...
);
// End of Generated Instance Port Map for inst_aa
// Generated Instance Port Map for inst_ab
ent_ab inst_ab ( // is i_vgca / hier inst_ab inst_ab inst_a
.p_mix_sc_sig_1_go(sc_sig_1), // bad conection bits detected
.p_mix_sc_sig_2_go(sc_sig_2) // reverse orderreverse order
// multiline comments
);
// End of Generated Instance Port Map for inst_ab
endmodule
//
// End of Generated Module struct of ent_a
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; int main() { int n, i, c = 1; cin >> n; int a[n + 1]; memset(a, 0, sizeof(a)); for (i = 0; i < n; i++) cin >> a[i]; for (i = 0; i < n; i++) { if (a[i] != a[i + 1]) c++; } cout << c - 1 << n ; } |
`define RC4_KEYREAD 4'h0
`define RC4_KSA1 4'h1
`define RC4_KSA2 4'h2
`define RC4_KSA3 4'h3
`define RC4_NEED 4'h7
`define RC4_PRGA1 4'h4
`define RC4_PRGA2 4'h5
`define RC4_PRGA3 4'h6
module rc4_old(ready, k, clk, rst, keyinput, need);
// parameters
parameter keylength = 8;
// outputs
output reg ready; // enable when generate prga
output reg [7:0] k; // value extracts from stream
// inputs
input clk;
input rst;
input [7:0] keyinput; // one byte of key per cycle
input need;
// internal
reg [7:0] key[0:keylength-1];
reg [3:0] state;
reg [7:0] stream[0:255];
reg [7:0] stream_temp;
reg [7:0] i;
reg [7:0] j;
reg [7:0] tmp;
initial begin
ready = 1;
state = `RC4_KEYREAD;
i = 8'h00;
j = 8'h00;
end
always @ (posedge clk) begin
if (rst) begin
ready = 0;
state = `RC4_KEYREAD;
i = 8'h00;
j = 8'h00;
end
case (state)
// read key every cylce until key length
`RC4_KEYREAD: begin
if (i == keylength) begin
state = `RC4_KSA1;
i = 8'h00;
end else begin
$display("key[%d] = %02X", i, keyinput);
key[i] = keyinput;
i = i + 8'h01;
end
end
// KSA 1
// initialize stream
`RC4_KSA1: begin
stream[i] = i;
if (i == 8'hff) begin
state = `RC4_KSA2;
i = 8'h00;
end else begin
i = i + 8'h01;
end
end
// KSA 2
// calcule j for use in next cycle
`RC4_KSA2: begin
state = `RC4_KSA3;
stream_temp = stream[i];
j = j + stream[i] + key[i % keylength];
end
// KSA 3
// swap values in stream
`RC4_KSA3: begin
stream[i] = stream[j];
// stream[j] = stream[i];
stream[j] = stream_temp;
if (i == 8'hff) begin
// ready to use prga
// state = `RC4_PRGA1;
state = `RC4_NEED;
i = 8'h01;
j = stream[1];
end else begin
state = `RC4_KSA2;
i = i + 8'h01;
end
end
`RC4_NEED: begin
if (need) state = `RC4_PRGA1;
end
// PRGA 1
// save data for swap
`RC4_PRGA1: begin
ready = 0;
state = `RC4_PRGA2;
stream_temp = stream[i];
end
// PRGA 2
// swap values in stream
`RC4_PRGA2: begin
state = `RC4_PRGA3;
stream[i] = stream[j];
// stream[j] = stream[i];
stream[j] = stream_temp;
tmp = stream[i] + stream[j];
end
// PRGA 3
// take k and then output
`RC4_PRGA3: begin
ready = 1;
k = stream[tmp];
// state = `RC4_PRGA1;
state = `RC4_NEED;
if (i == 8'hff) j = j + stream[0];
else j = j + stream[i + 1];
i = i + 1;
end
default: begin
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SEDFXBP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__SEDFXBP_BLACKBOX_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__sedfxbp (
Q ,
Q_N,
CLK,
D ,
DE ,
SCD,
SCE
);
output Q ;
output Q_N;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SEDFXBP_BLACKBOX_V
|
// MBT 9-7-2014
//
// two element fifo
//
// helpful interface on both input and output
//
// input : ready/valid flow control (rv->&)
// output: valid->yumi flow control ( v->r)
//
// see https://github.com/bespoke-silicon-group/basejump_stl/blob/master/docs/BaseJump_STL_DAC_2018_Camera_Ready.pdf
// to understand the flow control standards in BaseJump STL.
//
// INPUTS: although this module's inputs adheres to
// ready/valid protocol where both sender and receiver
// AND the two signals together to determine
// if transaction happened; in some cases, we
// know that the sender takes into account the
// ready signal before sending out valid, and the
// check is unnecessary. We use ready_THEN_valid_p
// to remove the check if it is unnecessary.
//
//
// note: ~v_o == fifo is empty.
//
`include "bsg_defines.v"
module bsg_two_fifo #(parameter `BSG_INV_PARAM(width_p)
, parameter verbose_p=0
// whether we should allow simultaneous enque and deque on full
, parameter allow_enq_deq_on_full_p=0
// necessarily, if we allow enq on ready low, then
// we are not using a ready/valid protocol
, parameter ready_THEN_valid_p=allow_enq_deq_on_full_p
)
(input clk_i
, input reset_i
// input side
, output ready_o // early
, input [width_p-1:0] data_i // late
, input v_i // late
// output side
, output v_o // early
, output[width_p-1:0] data_o // early
, input yumi_i // late
);
wire deq_i = yumi_i;
wire enq_i;
logic head_r, tail_r;
logic empty_r, full_r;
bsg_mem_1r1w #(.width_p(width_p)
,.els_p(2)
,.read_write_same_addr_p(allow_enq_deq_on_full_p)
) mem_1r1w
(.w_clk_i (clk_i )
,.w_reset_i(reset_i)
,.w_v_i (enq_i )
,.w_addr_i (tail_r )
,.w_data_i (data_i )
,.r_v_i (~empty_r)
,.r_addr_i (head_r )
,.r_data_o (data_o )
);
assign v_o = ~empty_r;
assign ready_o = ~full_r;
if (ready_THEN_valid_p)
assign enq_i = v_i;
else
assign enq_i = v_i & ~full_r;
always_ff @(posedge clk_i)
begin
if (reset_i)
begin
tail_r <= 1'b0;
head_r <= 1'b0;
empty_r <= 1'b1;
full_r <= 1'b0;
end
else
begin
if (enq_i)
tail_r <= ~tail_r;
if (deq_i)
head_r <= ~head_r;
// logic simplifies nicely for 2 element case
empty_r <= ( empty_r & ~enq_i)
| (~full_r & deq_i & ~enq_i);
if (allow_enq_deq_on_full_p)
full_r <= ( ~empty_r & enq_i & ~deq_i)
| ( full_r & ~(deq_i^enq_i));
else
full_r <= ( ~empty_r & enq_i & ~deq_i)
| ( full_r & ~deq_i);
end // else: !if(reset_i)
end // always_ff @
// synopsys translate_off
always_ff @(posedge clk_i)
begin
if (~reset_i)
begin
assert ({empty_r, deq_i} !== 2'b11)
else $error("invalid deque on empty fifo ", empty_r, deq_i);
if (allow_enq_deq_on_full_p)
begin
assert ({full_r,enq_i,deq_i} !== 3'b110)
else $error("invalid enque on full fifo ", full_r, enq_i);
end
else
assert ({full_r,enq_i} !== 2'b11)
else $error("invalid enque on full fifo ", full_r, enq_i);
assert ({full_r,empty_r} !== 2'b11)
else $error ("fifo full and empty at same time ", full_r, empty_r);
end // if (~reset_i)
end // always_ff @
always_ff @(posedge clk_i)
if (verbose_p)
begin
if (enq_i)
$display("### %m enq %x onto fifo",data_i);
if (deq_i)
$display("### %m deq %x from fifo",data_o);
end
// for debugging
wire [31:0] num_elements_debug = full_r + (empty_r==0);
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_two_fifo)
|
module StreamBuffer(
input rst_n,
input pclk,
input fclk,
input start,
input din_valid,
output din_ready,
input [7:0] din,
output [63:0] dout,
output dout_valid,
input dout_ready,
output burst_valid,
output [10:0] fifo_cnt
);
reg running;
`REG(pclk, running, 0, start ? 1 : running)
wire de2fifo_valid;
wire de2fifo_ready;
wire [63:0] de2fifo_data;
deserializer #(.INLOGBITS(3), .OUTLOGBITS(6)) inst_deserial(
.clk(pclk),
.rst_n(rst_n),
.in_valid(din_valid && running),
.in_ready(din_ready),
.in_data(din[7:0]),
.out_valid(de2fifo_valid),
.out_ready(de2fifo_ready),
.out_data(de2fifo_data)
);
wire vfifo_full;
wire vfifo_empty;
wire [8:0] vfifo_count;
fifo_64w_64r_512d sfifo_inst (
.rst(!rst_n), // input rst
.wr_clk(pclk), // input wr_clk
.rd_clk(fclk), // input rd_clk
.din(de2fifo_data[63:0]), // input [63 : 0] din
.wr_en(de2fifo_valid), // input wr_en
.rd_en(dout_ready), // input rd_en
.dout(dout), // output [63 : 0] dout
.full(vfifo_full), // output full
.empty(vfifo_empty), // output empty
.rd_data_count(vfifo_count), // output [8 : 0] rd_data_count
.wr_data_count() // output [8 : 0] wr_data_count
);
assign de2fifo_ready = !vfifo_full;
// I need to guarentee that 16 data entries are read out always
assign burst_valid = (vfifo_count > 9'd25);
assign dout_valid = !vfifo_empty;
assign fifo_cnt = vfifo_count;
endmodule // Conf
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100010; int n; int fa[maxn]; bool vis[maxn]; int cnt_loop = 0; vector<int> loop[maxn]; void get(int x, int id) { vis[x] = 1; loop[id].push_back(x); if (vis[fa[x]]) return; get(fa[x], id); } bool num[maxn]; int rid[maxn]; int main() { scanf( %d , &n); for (register int i = 1; i <= n; i++) { scanf( %d , &fa[i]); } for (register int i = 1; i <= n; i++) { if (!vis[i]) get(i, ++cnt_loop); } bool fg2 = 0; for (register int i = 1; i <= cnt_loop; i++) { num[loop[i].size()] = 1; rid[loop[i].size()] = i; if (((int)loop[i].size()) & 1) { fg2 = 1; } } if (num[1]) { printf( YES n ); for (register int i = 1; i <= cnt_loop; i++) { if (rid[1] == i) continue; for (register int j = 0; j < (int)loop[i].size(); j++) { printf( %d %d n , loop[rid[1]][0], loop[i][j]); } } } else if (num[2] && !fg2) { printf( YES n ); for (register int i = 1; i <= cnt_loop; i++) { if (rid[2] == i) { printf( %d %d n , loop[i][0], loop[i][1]); continue; } for (register int j = 0; j < (int)loop[i].size(); j++) { printf( %d %d n , loop[rid[2]][j & 1], loop[i][j]); } } } else { printf( NO n ); } return 0; } |
`include "minsoc_defines.v"
module OR1K_startup
(
input [6:2] wb_adr_i,
input wb_stb_i,
input wb_cyc_i,
output reg [31:0] wb_dat_o,
output reg wb_ack_o,
input wb_clk,
input wb_rst
);
always @ (posedge wb_clk or posedge wb_rst)
if (wb_rst)
wb_dat_o <= 32'h15000000;
else
case (wb_adr_i)
0 : wb_dat_o <= 32'h18000000;
1 : wb_dat_o <= 32'hA8200000;
2 : wb_dat_o <= { 16'h1880 , `APP_ADDR_SPI , 8'h00 };
3 : wb_dat_o <= 32'hA8A00520;
4 : wb_dat_o <= 32'hA8600001;
5 : wb_dat_o <= 32'h04000014;
6 : wb_dat_o <= 32'hD4041818;
7 : wb_dat_o <= 32'h04000012;
8 : wb_dat_o <= 32'hD4040000;
9 : wb_dat_o <= 32'hE0431804;
10 : wb_dat_o <= 32'h0400000F;
11 : wb_dat_o <= 32'h9C210008;
12 : wb_dat_o <= 32'h0400000D;
13 : wb_dat_o <= 32'hE1031804;
14 : wb_dat_o <= 32'hE4080000;
15 : wb_dat_o <= 32'h0FFFFFFB;
16 : wb_dat_o <= 32'hD4081800;
17 : wb_dat_o <= 32'h04000008;
18 : wb_dat_o <= 32'h9C210004;
19 : wb_dat_o <= 32'hD4011800;
20 : wb_dat_o <= 32'hE4011000;
21 : wb_dat_o <= 32'h0FFFFFFC;
22 : wb_dat_o <= 32'hA8C00100;
23 : wb_dat_o <= 32'h44003000;
24 : wb_dat_o <= 32'hD4040018;
25 : wb_dat_o <= 32'hD4042810;
26 : wb_dat_o <= 32'h84640010;
27 : wb_dat_o <= 32'hBC030520;
28 : wb_dat_o <= 32'h13FFFFFE;
29 : wb_dat_o <= 32'h15000000;
30 : wb_dat_o <= 32'h44004800;
31 : wb_dat_o <= 32'h84640000;
endcase
always @ (posedge wb_clk or posedge wb_rst)
if (wb_rst)
wb_ack_o <= 1'b0;
else
wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o;
endmodule // OR1K_startup
|
#include <bits/stdc++.h> const int mx = 1e6 + 5; const int inf = 0x3f3f3f3f; using namespace std; vector<int> ans; int dfs(long long int a, long long int b) { if (a > b) return 0; if (a == b) return 1; if (dfs(a * 2, b)) { ans.push_back(2 * a); return 1; } if (dfs(a * 10 + 1, b)) { ans.push_back(a * 10 + 1); return 1; } return 0; } int main() { ios::sync_with_stdio(0); cin.tie(0); int a, b; cin >> a >> b; if (dfs(a, b)) { printf( YES n%d n%d , int(1 + ans.size()), a); for (int i = ans.size() - 1; i >= 0; --i) printf( %d , ans[i]); puts( ); } else puts( NO ); return 0; } |
#include <bits/stdc++.h> using namespace std; void optimise() { ios_base::sync_with_stdio(false); cin.tie(NULL); } void solve() { string s; cin >> s; string s2; cin >> s2; sort(s.begin(), s.end()); for (long long int i = 0; i < s.size(); i++) { for (long long int j = i + 1; j < s.size(); j++) { string k = s; swap(k[i], k[j]); if (stoll(k) >= stoll(s) && stoll(k) <= stoll(s2)) s = k; } } cout << s; } signed main() { optimise(); long long int t = 1; while (t--) { solve(); } } |
#include <bits/stdc++.h> using namespace std; template <class T> bool chmax(T& a, const T& b) { if (a < b) { a = b; return 1; } return 0; } template <class T> bool chmin(T& a, const T& b) { if (b < a) { a = b; return 1; } return 0; } long long int gcd(long long int a, long long int b) { if (b == 0) return a; else return gcd(b, a % b); } long long int ceil(long long int a, long long int b) { return (a + b - 1) / b; } long long int digit(long long int a) { return (long long int)log10(a); } const long long int MOD = 1e9 + 7, INF = 1e18; long long int dx[8] = {1, 0, -1, 0, 1, -1, 1, -1}, dy[8] = {0, 1, 0, -1, -1, -1, 1, 1}; void YN(bool flag) { cout << (flag ? YES : NO ) << n ; } struct point { long long int r; long long int x, y; }; long long int N, K; int main() { cin >> N >> K; vector<long long int> arr(N); for (long long int i = (0), i_end_ = (N); i < i_end_; i++) { cin >> arr[i]; } sort((arr).begin(), (arr).end()); vector<pair<long long int, long long int> > vec; long long int curr = arr[0], cnt = 1; for (long long int i = (0), i_end_ = (N - 1); i < i_end_; i++) { if (arr[i + 1] != curr) { vec.push_back({curr, cnt}); curr = arr[i + 1]; cnt = 1; } else { cnt++; } } vec.push_back({curr, cnt}); N = ((long long int)(vec).size()); vector<long long int> sums_l(N); vector<long long int> sums_r(N); vector<long long int> sumn_l(N); vector<long long int> sumn_r(N); long long int sum = 0; for (long long int i = (0), i_end_ = (N - 1); i < i_end_; i++) { sum += vec[i].second; sums_l[i + 1] = sums_l[i] + (vec[i + 1].first - vec[i].first) * sum; sumn_l[i + 1] = sum; } sum = 0; for (long long int i = (0), i_end_ = (N - 1); i < i_end_; i++) { sum += vec[N - i - 1].second; sums_r[i + 1] = sums_r[i] + (vec[N - i - 1].first - vec[N - i - 2].first) * sum; sumn_r[i + 1] = sum; } long long int minv = INF; for (long long int i = (0), i_end_ = (((long long int)(vec).size())); i < i_end_; i++) { long long int rest = K - sums_l[i]; if (rest < 0) continue; long long int idx = upper_bound((sums_r).begin(), (sums_r).end(), rest) - sums_r.begin(); idx--; rest -= sums_r[idx]; long long int score = vec[N - idx - 1].first - vec[i].first; score -= rest / sumn_r[idx + 1]; chmin(minv, score); } for (long long int i = (0), i_end_ = (((long long int)(vec).size())); i < i_end_; i++) { long long int rest = K - sums_r[i]; if (rest < 0) continue; long long int idx = upper_bound((sums_l).begin(), (sums_l).end(), rest) - sums_l.begin(); idx--; rest -= sums_l[idx]; long long int score = vec[N - i - 1].first - vec[idx].first; score -= rest / sumn_l[idx + 1]; chmin(minv, score); } cout << max(0ll, minv) << n ; } |
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: bell.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module bell (
address,
clock,
q);
input [14:0] address;
input clock;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./audio_mifs/bell.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32768"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "15"
// Retrieval info: PRIVATE: WidthData NUMERIC "16"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./audio_mifs/bell.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32768"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 15 0 INPUT NODEFVAL "address[14..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
// Retrieval info: CONNECT: @address_a 0 0 15 0 address 0 0 15 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL bell.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL bell.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bell.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bell.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bell_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bell_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 505; int n, k; int a[MAXN], b[MAXN]; bool f[MAXN][MAXN]; int main() { scanf( %d%d , &n, &k); long long sum_a = 0, sum_b = 0; for (int i = 1; i <= n; i++) { scanf( %d%d , &a[i], &b[i]); sum_a += a[i]; sum_b += b[i]; } f[0][0] = true; for (int i = 1; i <= n; i++) { for (int j = 0; j < k; j++) { f[i][j] = f[i - 1][j]; for (int x = 0; x <= k; x++) { if (x <= a[i] && (k - x) <= b[i]) { f[i][j] = f[i][j] || f[i - 1][(j + k - x) % k]; } } } } long long ans = sum_a / k + sum_b / k; for (int x = 1; x < k; x++) { if (f[n][x]) { ans = max(ans, (sum_a - x) / k + (sum_b - (k - x)) / k + 1); } } printf( %lld n , ans); return 0; } |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : PIO_64_TX_ENGINE.v
// Version : 2.4
//-- Description: 64 bit Local-Link Transmit Unit.
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module PIO_64_TX_ENGINE #(
// RX/TX interface data width
parameter C_DATA_WIDTH = 64,
parameter TCQ = 1,
// KEEP width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8
)(
input clk,
input rst_n,
// AXIS
input s_axis_tx_tready,
output reg [C_DATA_WIDTH-1:0] s_axis_tx_tdata,
output reg [KEEP_WIDTH-1:0] s_axis_tx_tkeep,
output reg s_axis_tx_tlast,
output reg s_axis_tx_tvalid,
output tx_src_dsc,
input req_compl_i,
input req_compl_wd_i,
output reg compl_done_o,
input [2:0] req_tc_i,
input req_td_i,
input req_ep_i,
input [1:0] req_attr_i,
input [9:0] req_len_i,
input [15:0] req_rid_i,
input [7:0] req_tag_i,
input [7:0] req_be_i,
input [12:0] req_addr_i,
output [10:0] rd_addr_o,
output [3:0] rd_be_o,
input [31:0] rd_data_i,
input [15:0] completer_id_i,
input cfg_bus_mstr_enable_i
);
localparam PIO_64_CPLD_FMT_TYPE = 7'b10_01010;
localparam PIO_64_CPL_FMT_TYPE = 7'b00_01010;
localparam PIO_64_TX_RST_STATE = 1'b0;
localparam PIO_64_TX_CPLD_QW1 = 1'b1;
// Local registers
reg [11:0] byte_count;
reg [06:0] lower_addr;
reg req_compl_q;
reg req_compl_wd_q;
reg [0:0] state;
// Local wires
// Unused discontinue
assign tx_src_dsc = 1'b0;
/*
* Present address and byte enable to memory module
*/
assign rd_addr_o = req_addr_i[12:2];
assign rd_be_o = req_be_i[3:0];
/*
* Calculate byte count based on byte enable
*/
always @ (rd_be_o) begin
casex (rd_be_o[3:0])
4'b1xx1 : byte_count = 12'h004;
4'b01x1 : byte_count = 12'h003;
4'b1x10 : byte_count = 12'h003;
4'b0011 : byte_count = 12'h002;
4'b0110 : byte_count = 12'h002;
4'b1100 : byte_count = 12'h002;
4'b0001 : byte_count = 12'h001;
4'b0010 : byte_count = 12'h001;
4'b0100 : byte_count = 12'h001;
4'b1000 : byte_count = 12'h001;
4'b0000 : byte_count = 12'h001;
endcase
end
/*
* Calculate lower address based on byte enable
*/
always @ (rd_be_o or req_addr_i or req_compl_wd_q) begin
casex ({req_compl_wd_q, rd_be_o[3:0]})
5'b0_xxxx : lower_addr = 8'h0;
5'bx_0000 : lower_addr = {req_addr_i[6:2], 2'b00};
5'bx_xxx1 : lower_addr = {req_addr_i[6:2], 2'b00};
5'bx_xx10 : lower_addr = {req_addr_i[6:2], 2'b01};
5'bx_x100 : lower_addr = {req_addr_i[6:2], 2'b10};
5'bx_1000 : lower_addr = {req_addr_i[6:2], 2'b11};
endcase
end
always @ ( posedge clk ) begin
if (!rst_n ) begin
req_compl_q <= #TCQ 1'b0;
req_compl_wd_q <= #TCQ 1'b1;
end else begin
req_compl_q <= #TCQ req_compl_i;
req_compl_wd_q <= #TCQ req_compl_wd_i;
end
end
/*
* Generate Completion with 1 DW Payload
*/
always @ ( posedge clk ) begin
if (!rst_n ) begin
s_axis_tx_tlast <= #TCQ 1'b0;
s_axis_tx_tvalid <= #TCQ 1'b0;
s_axis_tx_tdata <= #TCQ {C_DATA_WIDTH{1'b0}};
s_axis_tx_tkeep <= #TCQ {KEEP_WIDTH{1'b1}};
compl_done_o <= #TCQ 1'b0;
state <= #TCQ PIO_64_TX_RST_STATE;
end else begin
case ( state )
PIO_64_TX_RST_STATE : begin
if (req_compl_q) begin
s_axis_tx_tlast <= #TCQ 1'b0;
s_axis_tx_tvalid <= #TCQ 1'b1;
// Swap DWORDS for AXI
s_axis_tx_tdata <= #TCQ { // Bits
completer_id_i, // 16
{3'b0}, // 3
{1'b0}, // 1
byte_count, // 12
{1'b0}, // 1
(req_compl_wd_q ?
PIO_64_CPLD_FMT_TYPE :
PIO_64_CPL_FMT_TYPE), // 7
{1'b0}, // 1
req_tc_i, // 3
{4'b0}, // 4
req_td_i, // 1
req_ep_i, // 1
req_attr_i, // 2
{2'b0}, // 2
req_len_i // 10
};
s_axis_tx_tkeep <= #TCQ 8'hFF;
// Wait in this state if the PCIe core does not accept
// the first beat of the packet
if (s_axis_tx_tready)
state <= #TCQ PIO_64_TX_CPLD_QW1;
else
state <= #TCQ PIO_64_TX_RST_STATE;
end else begin
s_axis_tx_tlast <= #TCQ 1'b0;
s_axis_tx_tvalid <= #TCQ 1'b0;
s_axis_tx_tdata <= #TCQ 64'b0;
s_axis_tx_tkeep <= #TCQ 8'hFF;
compl_done_o <= #TCQ 1'b0;
state <= #TCQ PIO_64_TX_RST_STATE;
end
end
PIO_64_TX_CPLD_QW1 : begin
if (s_axis_tx_tready) begin
s_axis_tx_tlast <= #TCQ 1'b1;
s_axis_tx_tvalid <= #TCQ 1'b1;
// Swap DWORDS for AXI
s_axis_tx_tdata <= #TCQ { // Bits
rd_data_i, // 32
req_rid_i, // 16
req_tag_i, // 8
{1'b0}, // 1
lower_addr // 7
};
// Here we select if the packet has data or
// not. The strobe signal will mask data
// when it is not needed. No reason to change
// the data bus.
if (req_compl_wd_q)
s_axis_tx_tkeep <= #TCQ 8'hFF;
else
s_axis_tx_tkeep <= #TCQ 8'h0F;
compl_done_o <= #TCQ 1'b1;
state <= #TCQ PIO_64_TX_RST_STATE;
end else
state <= #TCQ PIO_64_TX_CPLD_QW1;
end
endcase
end
end
endmodule // PIO_64_TX_ENGINE
|
#include <bits/stdc++.h> using namespace std; int main() { int res = 0; int n, x; cin >> n >> x; for (int i = 1; i <= n; ++i) { if (x % i == 0 && x / i <= n) ++res; } cout << res; } |
#include <bits/stdc++.h> using namespace std; long long n, l[100005], r[100005]; signed main() { scanf( %lld , &n); long long ans = 0; for (register long long i = 1; i <= n; i++) { scanf( %lld%lld , &l[i], &r[i]); } sort(l + 1, l + n + 1); sort(r + 1, r + n + 1); for (register long long i = 1; i <= n; i++) { ans += max(l[i], r[i]); } ans += n; cout << ans; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Wed Mar 01 09:52:04 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/ZyboIP/examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_inverter_1_0/system_inverter_1_0_sim_netlist.v
// Design : system_inverter_1_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_inverter_1_0,inverter,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "inverter,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_inverter_1_0
(x,
x_not);
input x;
output x_not;
wire x;
wire x_not;
LUT1 #(
.INIT(2'h1))
x_not_INST_0
(.I0(x),
.O(x_not));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; int main() { int n, perm[305], m[305][305]; char s[305]; scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d , &perm[i]); } memset(m, 0, sizeof(m)); for (int i = 0; i < n; i++) { scanf( %s , s); for (int j = 0; j < n; j++) { if (s[j] == 1 ) { m[i][j] = 1; } } } for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (m[i][j] == 1) { for (int a = 0; a < n; a++) { if (m[i][a] == 1 || m[j][a] == 1 || m[a][i] == 1 || m[a][j] == 1) { m[i][a] = 1; m[j][a] = 1; m[a][i] = 1; m[a][j] = 1; } } } } } for (int i = 0; i < n; i++) { for (int j = i + 1; j < n; j++) { if (m[i][j] && perm[j] < perm[i]) { swap(perm[j], perm[i]); } } } for (int i = 0; i < n; i++) { if (i != 0) { printf( ); } printf( %d , perm[i]); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 81; const int M = 2001; int n, k, m, ans = 1e9; int cache[N][2][N][N]; vector<pair<int, int> > g[N]; int dp(int idx, int dir, int dist, int taken) { if (taken == k) return 0; int &ans = cache[idx][dir][dist][taken]; if (ans != -1) return ans; ans = 1e9; for (auto &it : g[idx]) { if (abs(it.first - idx) <= dist) { if ((it.first - idx > 0 && dir > 0) || (idx - it.first > 0 && dir == 0)) { ans = min( ans, it.second + min(dp(it.first, dir, dist - abs(it.first - idx), taken + 1), dp(it.first, dir ^ 1, abs(it.first - idx) - 1, taken + 1))); } } } return ans; } int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; memset(cache, -1, sizeof(cache)); cin >> n >> k >> m; for (int i = 1; i <= m; i++) { int u, v, c; cin >> u >> v >> c; g[u].push_back({v, c}); } for (int i = 1; i <= n; i++) ans = min(ans, min(dp(i, 1, n - i, 1), dp(i, 0, i - 1, 1))); if (ans > 1e8) ans = -1; cout << ans; return 0; } |
//----------------------------------------------------------------------------
// user_logic.vhd - module
//----------------------------------------------------------------------------
//
// ***************************************************************************
// ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
// ** **
// ** Xilinx, Inc. **
// ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
// ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
// ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
// ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
// ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
// ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
// ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
// ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
// ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
// ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
// ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
// ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
// ** FOR A PARTICULAR PURPOSE. **
// ** **
// ***************************************************************************
//
//----------------------------------------------------------------------------
// Filename: user_logic.vhd
// Version: 1.04.a
// Description: User logic module.
// Date: Tue Jun 24 12:44:50 2008 (by Create and Import Peripheral Wizard)
// Verilog Standard: Verilog-2001
//----------------------------------------------------------------------------
// Naming Conventions:
// active low signals: "*_n"
// clock signals: "clk", "clk_div#", "clk_#x"
// reset signals: "rst", "rst_n"
// generics: "C_*"
// user defined types: "*_TYPE"
// state machine next state: "*_ns"
// state machine current state: "*_cs"
// combinatorial signals: "*_com"
// pipelined or register delay signals: "*_d#"
// counter signals: "*cnt*"
// clock enable signals: "*_ce"
// internal version of output port: "*_i"
// device pins: "*_pin"
// ports: "- Names begin with Uppercase"
// processes: "*_PROCESS"
// component instantiations: "<ENTITY_>I_<#|FUNC>"
//----------------------------------------------------------------------------
module user_logic
(
// -- ADD USER PORTS BELOW THIS LINE ---------------
//Eight EEPROM one-wire I/O ports (I/O/T control tri-state buffer in higher module)
DQ0_T,
DQ0_O,
DQ0_I,
DQ1_T,
DQ1_O,
DQ1_I,
DQ2_T,
DQ2_O,
DQ2_I,
DQ3_T,
DQ3_O,
DQ3_I,
DQ4_T,
DQ4_O,
DQ4_I,
DQ5_T,
DQ5_O,
DQ5_I,
DQ6_T,
DQ6_O,
DQ6_I,
DQ7_T,
DQ7_O,
DQ7_I,
// -- ADD USER PORTS ABOVE THIS LINE ---------------
// -- DO NOT EDIT BELOW THIS LINE ------------------
// -- Bus protocol ports, do not add to or delete
Bus2IP_Clk, // Bus to IP clock
Bus2IP_Reset, // Bus to IP reset
Bus2IP_Addr, // Bus to IP address bus
Bus2IP_CS, // Bus to IP chip select for user logic memory selection
Bus2IP_RNW, // Bus to IP read/not write
Bus2IP_Data, // Bus to IP data bus
Bus2IP_BE, // Bus to IP byte enables
IP2Bus_Data, // IP to Bus data bus
IP2Bus_RdAck, // IP to Bus read transfer acknowledgement
IP2Bus_WrAck, // IP to Bus write transfer acknowledgement
IP2Bus_Error // IP to Bus error response
// -- DO NOT EDIT ABOVE THIS LINE ------------------
); // user_logic
// -- ADD USER PARAMETERS BELOW THIS LINE ------------
// --USER parameters added here
// -- ADD USER PARAMETERS ABOVE THIS LINE ------------
// -- DO NOT EDIT BELOW THIS LINE --------------------
// -- Bus protocol parameters, do not add to or delete
parameter C_SLV_AWIDTH = 32;
parameter C_SLV_DWIDTH = 32;
parameter C_NUM_MEM = 1;
// -- DO NOT EDIT ABOVE THIS LINE --------------------
// -- ADD USER PORTS BELOW THIS LINE -----------------
output DQ0_T;
output DQ1_T;
output DQ2_T;
output DQ3_T;
output DQ4_T;
output DQ5_T;
output DQ6_T;
output DQ7_T;
output DQ0_O;
output DQ1_O;
output DQ2_O;
output DQ3_O;
output DQ4_O;
output DQ5_O;
output DQ6_O;
output DQ7_O;
input DQ0_I;
input DQ1_I;
input DQ2_I;
input DQ3_I;
input DQ4_I;
input DQ5_I;
input DQ6_I;
input DQ7_I;
// -- ADD USER PORTS ABOVE THIS LINE -----------------
// -- DO NOT EDIT BELOW THIS LINE --------------------
// -- Bus protocol ports, do not add to or delete
input Bus2IP_Clk;
input Bus2IP_Reset;
input [0 : C_SLV_AWIDTH-1] Bus2IP_Addr;
input [0 : C_NUM_MEM-1] Bus2IP_CS;
input Bus2IP_RNW;
input [0 : C_SLV_DWIDTH-1] Bus2IP_Data;
input [0 : C_SLV_DWIDTH/8-1] Bus2IP_BE;
output [0 : C_SLV_DWIDTH-1] IP2Bus_Data;
output IP2Bus_RdAck;
output IP2Bus_WrAck;
output IP2Bus_Error;
// -- DO NOT EDIT ABOVE THIS LINE --------------------
//----------------------------------------------------------------------------
// Implementation
//----------------------------------------------------------------------------
// --USER logic implementation added here
wire [ 7:0] OWM_rd_data;
wire [31:0] OWM_wt_data;
wire [31:0] OWM_addr;
assign OWM_wt_data = Bus2IP_Data;
assign OWM_addr = Bus2IP_Addr;
reg [ 2:0] OWM_rdwt_cycle;
reg OWM_wt_n;
reg OWM_rd_n;
reg OWM_rdwt_ack;
reg OWM_toutsup;
always @ (posedge Bus2IP_Clk or posedge Bus2IP_Reset)
begin
if (Bus2IP_Reset)
begin
OWM_rdwt_cycle <= 3'b000;
OWM_wt_n <= 1'b1;
OWM_rd_n <= 1'b1;
OWM_rdwt_ack <= 1'b0;
OWM_toutsup <= 1'b0;
end
else
begin
if ( ~Bus2IP_CS) OWM_rdwt_cycle <= 3'b000;
else if (OWM_rdwt_cycle == 3'b111) OWM_rdwt_cycle <= 3'b111;
else OWM_rdwt_cycle <= OWM_rdwt_cycle + 1;
OWM_wt_n <= ~( Bus2IP_CS & ~Bus2IP_RNW & (OWM_rdwt_cycle == 1)
| Bus2IP_CS & ~Bus2IP_RNW & (OWM_rdwt_cycle == 2)
);
OWM_rd_n <= ~( Bus2IP_CS & Bus2IP_RNW & (OWM_rdwt_cycle == 1)
| Bus2IP_CS & Bus2IP_RNW & (OWM_rdwt_cycle == 2)
| Bus2IP_CS & Bus2IP_RNW & (OWM_rdwt_cycle == 3)
| Bus2IP_CS & Bus2IP_RNW & (OWM_rdwt_cycle == 4)
);
OWM_rdwt_ack <= Bus2IP_CS & (OWM_rdwt_cycle == 4);
OWM_toutsup <= ~OWM_toutsup & Bus2IP_CS & (OWM_rdwt_cycle == 0)
| OWM_toutsup & Bus2IP_CS & ~OWM_rdwt_ack;
end
end
// ********** Instantiate the OWM core here... *****************************************
wire clk_1us_out;
OWM owm_instance
(
.ADDRESS(OWM_addr[4:2]),
.ADS_bar(1'b0),
.CLK(Bus2IP_Clk),
.EN_bar(1'b0),
.MR(Bus2IP_Reset),
.RD_bar(OWM_rd_n),
.WR_bar(OWM_wt_n),
.INTR(),
.STPZ(),
.DATA_IN(OWM_wt_data[7:0]),
.DATA_OUT(OWM_rd_data),
.DQ0_T(DQ0_T),
.DQ0_O(DQ0_O),
.DQ0_I(DQ0_I),
.DQ1_T(DQ1_T),
.DQ1_O(DQ1_O),
.DQ1_I(DQ1_I),
.DQ2_T(DQ2_T),
.DQ2_O(DQ2_O),
.DQ2_I(DQ2_I),
.DQ3_T(DQ3_T),
.DQ3_O(DQ3_O),
.DQ3_I(DQ3_I),
.DQ4_T(DQ4_T),
.DQ4_O(DQ4_O),
.DQ4_I(DQ4_I),
.DQ5_T(DQ5_T),
.DQ5_O(DQ5_O),
.DQ5_I(DQ5_I),
.DQ6_T(DQ6_T),
.DQ6_O(DQ6_O),
.DQ6_I(DQ6_I),
.DQ7_T(DQ7_T),
.DQ7_O(DQ7_O),
.DQ7_I(DQ7_I)
);
// Now connect signals to the OWM peripheral using the following mapping
// (instantiate the OWM core)...
//
// INTR -> IP2Bus_IntrEvent
// DATA_IN -> OWM_wt_data [7:0]
// DATA_OUT -> OWM_rd_data [7:0]
// A -> OWM_addr [2:0]
// ADS -> 1'b0;
// RD -> OWM_rd_n
// WR -> OWM_wt_n
// EN -> 1'b0;
// MR -> Bus2IP_Reset
// CLK -> Bus2IP_Clk
//
// *************************************************************************************
/*
reg [31:0] debug;
always @ (posedge OWM_wt_n or posedge Bus2IP_Reset)
begin
if (Bus2IP_Reset)
begin
debug <= 32'h00000000;
end
else
begin
debug <= {Bus2IP_CS,Bus2IP_RNW,OWM_rd_n,13'h0000,OWM_addr [7:0],OWM_wt_data [7:0]}
end
end
*/
assign IP2Bus_Data = {32{OWM_rdwt_ack}} & {24'h000000, OWM_rd_data};
// assign IP2Bus_Data = {32{OWM_rdwt_ack}} & {16'hFEDC,IP2Bus_Ack,OWM_rdwt_cycle,Bus2IP_Reset,Bus2IP_CS,OWM_wt_n,OWM_rd_n,OWM_rd_data};
assign IP2Bus_RdAck = OWM_rdwt_ack & Bus2IP_CS & Bus2IP_RNW;
assign IP2Bus_WrAck = OWM_rdwt_ack & Bus2IP_CS & ~Bus2IP_RNW;
assign IP2Bus_Error = 1'b0;
//synthesis attribute clock_signal of OWM_wt_n IS no
//synthesis attribute buffer_type of OWM_wt_n IS none
endmodule
|
/*
Anthony De Caria - May 22, 2014
This module creates a Shift Register with a seperate enable signal.
This specific module creates an output that is 14-bits wide.
*/
module ShiftRegisterWEnableSixteen(clk, resetn, enable, d, q);
//Define the inputs and outputs
input clk;
input resetn;
input enable;
input d;
output [15:0] q;
D_FF_with_Enable Zero(clk, resetn, enable, d, q[0]);
D_FF_with_Enable One(clk, resetn, enable, q[0], q[1]);
D_FF_with_Enable Two(clk, resetn, enable, q[1], q[2]);
D_FF_with_Enable Three(clk, resetn, enable, q[2], q[3]);
D_FF_with_Enable Four(clk, resetn, enable, q[3], q[4]);
D_FF_with_Enable Five(clk, resetn, enable, q[4], q[5]);
D_FF_with_Enable Six(clk, resetn, enable, q[5], q[6]);
D_FF_with_Enable Seven(clk, resetn, enable, q[6], q[7]);
D_FF_with_Enable Eight(clk, resetn, enable, q[7], q[8]);
D_FF_with_Enable Nine(clk, resetn, enable, q[8], q[9]);
D_FF_with_Enable Ten(clk, resetn, enable, q[9], q[10]);
D_FF_with_Enable Eleven(clk, resetn, enable, q[10], q[11]);
D_FF_with_Enable Twelve(clk, resetn, enable, q[11], q[12]);
D_FF_with_Enable Thirteen(clk, resetn, enable, q[12], q[13]);
D_FF_with_Enable Fourteen(clk, resetn, enable, q[13], q[14]);
D_FF_with_Enable Fifteen(clk, resetn, enable, q[14], q[15]);
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> inline T bigmod(T p, T e, T M) { long long int ret = 1; for (; e > 0; e >>= 1) { if (e & 1) ret = (ret * p) % M; p = (p * p) % M; } return (T)ret; } template <class T> inline T gcd(T a, T b) { if (b == 0) return a; return gcd(b, a % b); } template <class T> inline T modinverse(T a, T M) { return bigmod(a, M - 2, M); } template <class T> inline T bpow(T p, T e) { long long int ret = 1; for (; e > 0; e >>= 1) { if (e & 1) ret = (ret * p); p = (p * p); } return (T)ret; } int toInt(string s) { int sm; stringstream ss(s); ss >> sm; return sm; } int toLlint(string s) { long long int sm; stringstream ss(s); ss >> sm; return sm; } int ts, kk = 1; int n, a[1000006]; bool bl[1000006]; char s[1000006]; int p[2][2][1000006]; int dp(bool st, bool c, int i) { if (i == n) { if (c && st) return -1; return 0; } int &pr = p[st][c][i]; if (pr != -1) return pr; pr = 0; pr = max(pr, dp(st, 0, i + 1)); if (bl[i] == 0) { if (c == 0) pr = max(dp((i == 0) || st, 1, i + 1) + 1, pr); if (a[i] > 1) pr = max(dp(st, 1, i + 1) + 1, pr); } else { if (c == 0) pr = max(dp((i == 0) || st, 1, i + 1) + 1, pr); if (a[i] > 1) pr = max(dp(st, 1, i + 1) + 1, pr); } return pr; } void prnt(bool st, bool c, int i) { if (i == n) { puts( ); return; } int &pr = p[st][c][i]; if (dp(st, 0, i + 1) == pr) { prnt(st, 0, i + 1); return; } if (bl[i] == 0) { if (c == 0 && dp((i == 0), 1, i + 1) + 1 == pr) { printf( %d 0 0 n , i); prnt((i == 0), 1, i + 1); return; } if (a[i] > 1 && pr == dp(st, 1, i + 1) + 1) { printf( %d 0 1 n , i); prnt(st, 1, i + 1); return; } } else { if (c == 0 && dp((i == 0), 1, i + 1) + 1 == pr) { printf( %d 1 0 n , i); prnt((i == 0), 1, i + 1); return; } if (a[i] > 1 && pr == dp(st, 1, i + 1) + 1) { printf( %d 1 1 n , i); prnt(st, 1, i + 1); return; } } } int main() { int t, i, j, k; memset(p, -1, sizeof(p)); scanf( %s , s); k = strlen(s); bl[0] = s[0] - 0 ; n = 1; for (i = 0; i < k; i++) { if ((bool)(s[i] - 0 ) == bl[n - 1]) a[n - 1]++; else { bl[n] = (s[i] - 0 ); a[n++] = 1; } } if (n > 1 && bl[n - 1] == bl[0]) { a[0] += a[n - 1]; n--; } k = dp(0, 0, 0); printf( %d n , k); return 0; } |
//Test bench for 32 bit ripple carry adder
`include "lab6_6.v"
module ripple_carry_adder_test(); /* test bench module for first_module() */
reg [31:0] A, B;
reg C0;
wire [31:0] S;
wire Cout;
ripple_carry_adder_32bit test(S,Cout,A,B,C0);
initial begin
$monitor($time, "\tA=%d\tB=%d\tCin=%b\tS=%d\tCout=%b", A, B, C0, S, Cout);
A = 0; B = 0; C0 = 0;
#1
A = 0; B = 0; C0 = 1;
#1
A = 0; B = 1; C0 = 0;
#1
A = 1; B = 0; C0 = 0;
#1
A = 1; B = 1; C0 = 0;
#1
A = 1; B = 1; C0 = 1;
#1
A = 16777215; B = 16777215; C0 = 0;
#1
A = 16777215; B = 16777215; C0 = 1;
#1
A = ; B = 0; C0 = 0;
#1
A = ; B = 0; C0 = 1;
#1
A = ; B = 1; C0 = 0;
#1
A = ; B = 1; C0 = 1;
#1
A = 0; B = ; C0 = 0;
#1
A = 0; B = ; C0 = 1;
#1
A = 1; B = ; C0 = 0;
#1
A = 1; B = ; C0 = 1;
#1
A = ; B = ; C0 = 0;
#1
A = ; B = ; C0 = 1;
#1
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int min(long long int a, long long int b) { if (a < b) { return a; } else { return b; } } long long int max(long long int a, long long int b) { if (a > b) { return a; } else { return b; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; long long int t; cin >> t; while (t--) { long long int n; cin >> n; string str; cin >> str; if (n == 1) { cout << 1 << n ; continue; } if (n == 2) { if (str[0] == str[1]) { cout << 1 << n ; continue; } } vector<long long int> seg; long long int curr_length = 1; for (long long int i = 0; i < str.size() - 1; i++) { if (str[i] == str[i + 1]) { curr_length++; } else { seg.push_back(curr_length); curr_length = 1; } } seg.push_back(curr_length); long long int segtillnow = 0; long long int ans = 0; for (long long int i = 0; i < seg.size(); i++) { segtillnow++; if (seg[i] == 1) { continue; } else if (seg[i] > 1) { long long int operations = min(seg[i] - 1, segtillnow); ans += operations; segtillnow -= operations; } } ans += ((segtillnow + 1) / 2); cout << ans << n ; } } |
#include <bits/stdc++.h> using namespace std; int q, s, t, n, m, i, j, k, l; int main() { cin >> t >> s >> q; int t1; while (s < t) { s = q * s; i++; } cout << i << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxm = 2e6 + 5; struct task { int t, k, d; } tasks[maxm]; int times[110]; int main() { for (int i = 0; i < 110; ++i) { times[i] = 0; } int n, m; scanf( %d%d , &n, &m); for (int i = 0; i < m; ++i) { scanf( %d%d%d , &tasks[i].t, &tasks[i].k, &tasks[i].d); } for (int i = 0; i < m; ++i) { int num = 0, j = 1, res = 0; if (tasks[i].k > n) { printf( -1 n ); continue; } while (j <= n) { if (times[j] <= tasks[i].t) { num++; } if (num == tasks[i].k) break; j++; } j = 1; if (num == tasks[i].k) { int cnt = 0; while (j <= n) { if (times[j] <= tasks[i].t) { res += j; times[j] = tasks[i].t + tasks[i].d; cnt++; } if (cnt == tasks[i].k) break; j++; } printf( %d n , res); } else { printf( -1 n ); continue; } } } |
#include <bits/stdc++.h> using namespace std; void _print(long long int x) { cerr << x << ; } void _print(float x) { cerr << x << ; } void _print(double x) { cerr << x << ; } void _print(char x) { cerr << x << ; } void _print(string x) { cerr << x << ; } void _print(bool x) { cerr << x << ; } template <class T, class V> void _print(pair<T, V> x) { cerr << { ; _print(x.first); cerr << , ; _print(x.second); cerr << } ; } template <class T> void _print(vector<T> x) { cerr << [ ; for (T i : x) { _print(i); cerr << ; } cerr << ] ; } template <class T> void _print(set<T> x) { cerr << [ ; for (T i : x) { _print(i); cerr << ; } cerr << ] ; } template <class T> void _print(multiset<T> x) { cerr << [ ; for (T i : x) { _print(i); cerr << ; } cerr << ] ; } template <class T, class V> void _print(map<T, V> x) { cerr << [ ; for (auto i : x) { _print(i); cerr << ; } cerr << ] ; } void solve() { string s; cin >> s; long long int n = s.size(); if (n % 2 == 1) { cout << NO << endl; return; } for (long long int i = 0; i <= (n / 2) - 1; i++) { if (s[i] != s[i + (n / 2)]) { cout << NO << endl; return; } } cout << YES << endl; } signed main() { ios_base ::sync_with_stdio(false); cin.tie(NULL); clock_t start, end; start = clock(); long long int t; cin >> t; while (t--) { solve(); } end = clock(); double time_taken = double(end - start) / double(CLOCKS_PER_SEC); cerr << Time taken by program is : << fixed << time_taken << setprecision(5); cerr << sec << endl; return 0; } |
// misc simulator environment
// Copyright (C) 1998,2000,2003,2004,2007 Free Software Foundation, Inc.
// This file is part of Gforth.
// Gforth is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation, either version 3
// of the License, or (at your option) any later version.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, see http://www.gnu.org/licenses/.
`define L [0:l-1]
module main;
parameter l=16, d=10;
reg clock;
wire `L addr, data;
wire csel, rw, read, write;
reg `L mem[0:(1<<l)-1];
reg [0:7] keys[0:15];
integer inputq, fileno, start;
initial
begin
clock = 0;
for(start='h0000; start < 'h8000; start=start+1)
mem[start] = 0;
$readmemh("kernl-misc.hex", mem);
// fileno=$fopen("misc.out");
mem['hffff] = 1;
mem['hfffe] = 32;
keys[0]=99;
keys[1]=114;
keys[2]=32;
keys[3]=49;
keys[4]=32;
keys[5]=50;
keys[6]=32;
keys[7]=43;
keys[8]=32;
keys[9]=46;
keys[10]=13;
keys[11]=32;
inputq=0;
#d clock = 0;
#d clock = 0;
forever
begin
#d clock = ~clock;
end
end
assign #d
write = csel & ~rw,
read = csel & rw;
always @(posedge write)
#d if(addr == 'hfffc) $write("%c", data);
else
mem[addr] = data;
assign
data = (read & ~write) ? mem[addr] : {l{1'bz}};
always @(addr or read or write)
if(read & ~write & (addr == 'hfffe))
begin
#(d*4)
mem['hfffe] = { 8'b0, keys[inputq] };
inputq = inputq + 1;
if(inputq > 11) $finish;
end
misc #(l,d)
misc0(clock, data, addr, csel, rw);
endmodule /* main */
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Instantiate this block at the core level to conduct closed
// loop testing of the AC performance of the USRP2 SRAM interface
`define WIDTH 18
`define DEPTH 19
module test_sram_if
(
input clk,
input rst,
input [`WIDTH-1:0] RAM_D_pi,
output [`WIDTH-1:0] RAM_D_po,
output RAM_D_poe,
output [`DEPTH-1:0] RAM_A,
output RAM_WEn,
output RAM_CENn,
output RAM_LDn,
output RAM_OEn,
output RAM_CE1n,
output reg correct
);
reg [`DEPTH-1:0] write_count;
reg [`DEPTH-1:0] read_count;
reg enable;
reg write;
reg write_cycle;
reg read_cycle;
reg enable_reads;
reg [18:0] address;
reg [17:0] data_out;
wire [17:0] data_in;
wire data_in_valid;
reg [17:0] check_data;
reg [17:0] check_data_old;
reg [17:0] check_data_old2;
//
// Create counter that generates both external modulo 2^19 address and modulo 2^18 data to test RAM.
//
always @(posedge clk)
if (rst)
begin
write_count <= 19'h0;
read_count <= 19'h0;
end
else if (write_cycle) // Write cycle
if (write_count == 19'h7FFFF)
begin
write_count <= 19'h0;
end
else
begin
write_count <= write_count + 1'b1;
end
else if (read_cycle) // Read cycle
if (read_count == 19'h7FFFF)
begin
read_count <= 19'h0;
end
else
begin
read_count <= read_count + 1'b1;
end
always @(posedge clk)
if (rst)
begin
enable_reads <= 0;
read_cycle <= 0;
write_cycle <= 0;
end
else
begin
write_cycle <= ~write_cycle;
if (enable_reads)
read_cycle <= write_cycle;
if (write_count == 15) // Enable reads 15 writes after reset terminates.
enable_reads <= 1;
end // else: !if(rst)
always @(posedge clk)
if (rst)
begin
enable <= 0;
end
else if (write_cycle)
begin
address <= write_count;
data_out <= write_count[17:0];
enable <= 1;
write <= 1;
end
else if (read_cycle)
begin
address <= read_count;
check_data <= read_count[17:0];
check_data_old <= check_data;
check_data_old2 <= check_data_old;
enable <= 1;
write <= 0;
end
else
enable <= 0;
always @(posedge clk)
if (data_in_valid)
begin
correct <= (data_in == check_data_old2);
end
nobl_if nobl_if_i1
(
.clk(clk),
.rst(rst),
.RAM_D_pi(RAM_D_pi),
.RAM_D_po(RAM_D_po),
.RAM_D_poe(RAM_D_poe),
.RAM_A(RAM_A),
.RAM_WEn(RAM_WEn),
.RAM_CENn(RAM_CENn),
.RAM_LDn(RAM_LDn),
.RAM_OEn(RAM_OEn),
.RAM_CE1n(RAM_CE1n),
.address(address),
.data_out(data_out),
.data_in(data_in),
.data_in_valid(data_in_valid),
.write(write),
.enable(enable)
);
wire [35:0] CONTROL0;
reg [7:0] data_in_reg, data_out_reg, address_reg;
reg data_in_valid_reg,write_reg,enable_reg,correct_reg;
always @(posedge clk)
begin
data_in_reg <= data_in[7:0];
data_out_reg <= data_out[7:0];
data_in_valid_reg <= data_in_valid;
write_reg <= write;
enable_reg <= enable;
correct_reg <= correct;
address_reg <= address;
end
icon icon_i1
(
.CONTROL0(CONTROL0)
);
ila ila_i1
(
.CLK(clk),
.CONTROL(CONTROL0),
// .TRIG0(address_reg),
.TRIG0(data_in_reg[7:0]),
.TRIG1(data_out_reg[7:0]),
.TRIG2(address_reg[7:0]),
.TRIG3({data_in_valid_reg,write_reg,enable_reg,correct_reg})
);
endmodule // test_sram_if
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFXBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__DFXBP_BEHAVIORAL_PP_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_hvl__udp_dff_p_pp_pg_n.v"
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__dfxbp (
Q ,
Q_N ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire CLK_delayed;
wire buf0_out_Q ;
wire not0_out_qn;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
buf buf0 (buf0_out_Q , buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
not not0 (not0_out_qn, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (Q_N , not0_out_qn, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFXBP_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int int_inf = 0x3f3f3f3f; const long long int ll_inf = 0x3f3f3f3f3f3f3f3f; const int max_n = 1e5 + 5; bool g[max_n]; int head[max_n], nxt[max_n << 2], to[max_n << 2], cnt; int dis[max_n]; int n, start, end1; struct nodes { int dis, v; bool operator<(const struct nodes a) const { return dis > a.dis; } }; void add(int a, int b) { nxt[++cnt] = head[a]; head[a] = cnt; to[cnt] = b; return; } int max1; void dijkstra() { int i; for (i = 0; i <= n; i++) dis[i] = int_inf; dis[start] = 0; priority_queue<nodes> q; q.push((nodes){0, start}); while (!q.empty()) { nodes t = q.top(); q.pop(); if (t.dis > dis[t.v]) continue; dis[t.v] = t.dis; max1 = max(max1, t.dis); int tdis = t.dis + 1; if (g[t.v]) tdis = 1; if (t.v == end1) break; for (i = head[t.v]; i; i = nxt[i]) { if (tdis < dis[to[i]]) { dis[to[i]] = tdis; q.push((nodes){tdis, to[i]}); } } } return; } int main() { ios::sync_with_stdio(false); cin.tie(0); int i, j; int m, k; cin >> n >> m >> k; for (i = 0; i < k; i++) { int num; cin >> num; g[num] = true; } while (m--) { int a, b; cin >> a >> b; add(a, b); add(b, a); } cin >> start >> end1; if (!g[start]) { if (start == end1) cout << 0 << endl; else cout << -1 << endl; } else { max1 = -1; dijkstra(); cout << ((dis[end1] == int_inf) ? -1 : max1) << endl; } return 0; } |
`timescale 1ns / 1ps
module testRX;
// Inputs
reg clk;
wire baud_rate;
reg rx;
// Outputs
wire [7:0] d_out;
wire rx_done;
reg [7:0] dato = 'b10011001;
reg [7:0] dato2 = 'b01100110;
integer count = 0;
integer bit_count = 0;
BaudRateGenerator baud (
.clk(clk),
.out(baud_rate)
);
// Instantiate the Unit Under Test (UUT)
RX uut (
.clk(clk),
.baud_rate(baud_rate),
.rx(rx),
.d_out(d_out),
.rx_done(rx_done)
);
initial begin
// Initialize Inputs
clk = 0;
rx = 1;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
always
begin
#1; clk = 1;
#1; clk = 0;
end
always@(posedge baud_rate)
begin
count = count + 1;
end
always@(posedge baud_rate)
begin
if(count == 16)
begin
if(bit_count == 0)
begin
rx = 0;
bit_count = bit_count + 1;
end
else
begin
if(bit_count < 9)
begin
rx = dato[7];
dato = dato << 1;
end
if(bit_count == 9) rx = 1; //stop bit
if(bit_count == 11) rx = 0; //start bit
if(bit_count > 11 && bit_count < 20)
begin
rx = dato2[7];
dato2 = dato2 << 1;
end
if(bit_count == 21) rx = 1; //stop bit
bit_count = bit_count+1;
end
count = 0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, k, A[100005], B[100005], C[100005], sum, val; pair<long long, long long> E[100005]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> k; for (int i = 1; i <= n; i++) { cin >> A[i]; C[A[i]]++; } for (int i = 1; i <= k; i++) { if (C[i] == 0) val++; } for (int i = 1; i <= n; i++) { cin >> B[i]; E[i].first = B[i]; E[i].second = A[i]; } sort(E + 1, E + n + 1); k = 1; for (int i = 1; k <= val; i++) { if (C[E[i].second] > 1) { sum += E[i].first; C[E[i].second]--; k++; } } cout << sum << n ; } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: cpx_spc_rpt.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
`include "sys.h"
`include "iop.h"
`include "ifu.h"
`include "lsu.h"
module cpx_spc_rpt (/*AUTOARG*/
// Outputs
so, cpx_spc_data_cx3, cpx_spc_data_rdy_cx3,
cpx_spc_data_cx3_b144to140, cpx_spc_data_cx3_b120to118,
cpx_spc_data_cx3_b0, cpx_spc_data_cx3_b4, cpx_spc_data_cx3_b8,
cpx_spc_data_cx3_b12, cpx_spc_data_cx3_b16, cpx_spc_data_cx3_b20,
cpx_spc_data_cx3_b24, cpx_spc_data_cx3_b28, cpx_spc_data_cx3_b32,
cpx_spc_data_cx3_b35, cpx_spc_data_cx3_b38, cpx_spc_data_cx3_b41,
cpx_spc_data_cx3_b44, cpx_spc_data_cx3_b47, cpx_spc_data_cx3_b50,
cpx_spc_data_cx3_b53, cpx_spc_data_cx3_b56, cpx_spc_data_cx3_b60,
cpx_spc_data_cx3_b64, cpx_spc_data_cx3_b68, cpx_spc_data_cx3_b72,
cpx_spc_data_cx3_b76, cpx_spc_data_cx3_b80, cpx_spc_data_cx3_b84,
cpx_spc_data_cx3_b88, cpx_spc_data_cx3_b91, cpx_spc_data_cx3_b94,
cpx_spc_data_cx3_b97, cpx_spc_data_cx3_b100,
cpx_spc_data_cx3_b103, cpx_spc_data_cx3_b106,
cpx_spc_data_cx3_b109,
// Inputs
rclk, si, se, cpx_spc_data_cx2, cpx_spc_data_rdy_cx2
);
input rclk;
input si;
input se;
input [`CPX_WIDTH-1:0] cpx_spc_data_cx2;
input cpx_spc_data_rdy_cx2;
output so;
output [`CPX_WIDTH-1:0] cpx_spc_data_cx3;
output cpx_spc_data_rdy_cx3;
output [`CPX_WIDTH-1:140] cpx_spc_data_cx3_b144to140 ;
output [`CPX_INV_CID_HI:`CPX_INV_CID_LO] cpx_spc_data_cx3_b120to118 ;
output cpx_spc_data_cx3_b0 ;
output cpx_spc_data_cx3_b4 ;
output cpx_spc_data_cx3_b8 ;
output cpx_spc_data_cx3_b12 ;
output cpx_spc_data_cx3_b16 ;
output cpx_spc_data_cx3_b20 ;
output cpx_spc_data_cx3_b24 ;
output cpx_spc_data_cx3_b28 ;
output cpx_spc_data_cx3_b32 ;
output cpx_spc_data_cx3_b35 ;
output cpx_spc_data_cx3_b38 ;
output cpx_spc_data_cx3_b41 ;
output cpx_spc_data_cx3_b44 ;
output cpx_spc_data_cx3_b47 ;
output cpx_spc_data_cx3_b50 ;
output cpx_spc_data_cx3_b53 ;
output cpx_spc_data_cx3_b56 ;
output cpx_spc_data_cx3_b60 ;
output cpx_spc_data_cx3_b64 ;
output cpx_spc_data_cx3_b68 ;
output cpx_spc_data_cx3_b72 ;
output cpx_spc_data_cx3_b76 ;
output cpx_spc_data_cx3_b80 ;
output cpx_spc_data_cx3_b84 ;
output cpx_spc_data_cx3_b88 ;
output cpx_spc_data_cx3_b91 ;
output cpx_spc_data_cx3_b94 ;
output cpx_spc_data_cx3_b97 ;
output cpx_spc_data_cx3_b100 ;
output cpx_spc_data_cx3_b103 ;
output cpx_spc_data_cx3_b106 ;
output cpx_spc_data_cx3_b109 ;
reg [`CPX_WIDTH-1:0] cpx_spc_data_cx3;
reg cpx_spc_data_rdy_cx3;
always @(posedge rclk) begin
cpx_spc_data_cx3 <= cpx_spc_data_cx2;
cpx_spc_data_rdy_cx3 <= cpx_spc_data_rdy_cx2;
end
//timing fix: 9/5/03 - add separate buffer to lsu for signal that are used in bypass i.e. isolate from spu/ffu loading
assign cpx_spc_data_cx3_b144to140[`CPX_WIDTH-1:140] = cpx_spc_data_cx3[`CPX_WIDTH-1:140] ;
assign cpx_spc_data_cx3_b120to118[`CPX_INV_CID_HI:`CPX_INV_CID_LO] = cpx_spc_data_cx3[`CPX_INV_CID_HI:`CPX_INV_CID_LO] ;
assign cpx_spc_data_cx3_b0 = cpx_spc_data_cx3[0] ;
assign cpx_spc_data_cx3_b4 = cpx_spc_data_cx3[4] ;
assign cpx_spc_data_cx3_b8 = cpx_spc_data_cx3[8] ;
assign cpx_spc_data_cx3_b12 = cpx_spc_data_cx3[12] ;
assign cpx_spc_data_cx3_b16 = cpx_spc_data_cx3[16] ;
assign cpx_spc_data_cx3_b20 = cpx_spc_data_cx3[20] ;
assign cpx_spc_data_cx3_b24 = cpx_spc_data_cx3[24] ;
assign cpx_spc_data_cx3_b28 = cpx_spc_data_cx3[28] ;
assign cpx_spc_data_cx3_b32 = cpx_spc_data_cx3[32] ;
assign cpx_spc_data_cx3_b35 = cpx_spc_data_cx3[35] ;
assign cpx_spc_data_cx3_b38 = cpx_spc_data_cx3[38] ;
assign cpx_spc_data_cx3_b41 = cpx_spc_data_cx3[41] ;
assign cpx_spc_data_cx3_b44 = cpx_spc_data_cx3[44] ;
assign cpx_spc_data_cx3_b47 = cpx_spc_data_cx3[47] ;
assign cpx_spc_data_cx3_b50 = cpx_spc_data_cx3[50] ;
assign cpx_spc_data_cx3_b53 = cpx_spc_data_cx3[53] ;
assign cpx_spc_data_cx3_b56 = cpx_spc_data_cx3[56] ;
assign cpx_spc_data_cx3_b60 = cpx_spc_data_cx3[60] ;
assign cpx_spc_data_cx3_b64 = cpx_spc_data_cx3[64] ;
assign cpx_spc_data_cx3_b68 = cpx_spc_data_cx3[68] ;
assign cpx_spc_data_cx3_b72 = cpx_spc_data_cx3[72] ;
assign cpx_spc_data_cx3_b76 = cpx_spc_data_cx3[76] ;
assign cpx_spc_data_cx3_b80 = cpx_spc_data_cx3[80] ;
assign cpx_spc_data_cx3_b84 = cpx_spc_data_cx3[84] ;
assign cpx_spc_data_cx3_b88 = cpx_spc_data_cx3[88] ;
assign cpx_spc_data_cx3_b91 = cpx_spc_data_cx3[91] ;
assign cpx_spc_data_cx3_b94 = cpx_spc_data_cx3[94] ;
assign cpx_spc_data_cx3_b97 = cpx_spc_data_cx3[97] ;
assign cpx_spc_data_cx3_b100 = cpx_spc_data_cx3[100] ;
assign cpx_spc_data_cx3_b103 = cpx_spc_data_cx3[103] ;
assign cpx_spc_data_cx3_b106 = cpx_spc_data_cx3[106] ;
assign cpx_spc_data_cx3_b109 = cpx_spc_data_cx3[109] ;
endmodule
|
#include <bits/stdc++.h> using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); long long t; cin >> t; for (long long _ = 0; _ < t; ++_) { long long n; cin >> n; vector<long long> a(n + 1); for (long long i = 0; i < n; ++i) { cin >> a[i]; } long long l = a[0]; long long r = n; long long cur = l; string ans = Yes ; for (long long i = 0; i < n; ++i) { if (a[i] != cur) { ans = No ; } ++cur; if (a[i] == r) { r = l - 1; l = a[i + 1]; cur = l; } } cout << ans << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int num[105]; int main() { int n; cin >> n; for (int i = 1; i <= n; i++) { scanf( %1d , &num[i]); } int sum = 0; int flag = 0; for (int i = 1; i <= n; i++) { sum += num[i]; int t = 0; flag = 0; for (int j = i + 1; j <= n; j++) { if (num[j] == 0 && t == 0 && flag == 1) { if (j == n) { puts( YES ); return 0; } continue; } t += num[j]; if (t > sum) { break; } else if (t == sum) { t = 0; flag = 1; if (j == n) { puts( YES ); return 0; } } } } puts( NO ); return 0; } |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIEBus_pcie_pipe_misc.v
// Version : 1.11
//
// Description: Misc PIPE module for 7-Series PCIe Block
//
//
//
//--------------------------------------------------------------------------------
`timescale 1ps/1ps
module PCIEBus_pcie_pipe_misc #
(
parameter PIPE_PIPELINE_STAGES = 0 // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
)
(
input wire pipe_tx_rcvr_det_i , // PIPE Tx Receiver Detect
input wire pipe_tx_reset_i , // PIPE Tx Reset
input wire pipe_tx_rate_i , // PIPE Tx Rate
input wire pipe_tx_deemph_i , // PIPE Tx Deemphasis
input wire [2:0] pipe_tx_margin_i , // PIPE Tx Margin
input wire pipe_tx_swing_i , // PIPE Tx Swing
output wire pipe_tx_rcvr_det_o , // Pipelined PIPE Tx Receiver Detect
output wire pipe_tx_reset_o , // Pipelined PIPE Tx Reset
output wire pipe_tx_rate_o , // Pipelined PIPE Tx Rate
output wire pipe_tx_deemph_o , // Pipelined PIPE Tx Deemphasis
output wire [2:0] pipe_tx_margin_o , // Pipelined PIPE Tx Margin
output wire pipe_tx_swing_o , // Pipelined PIPE Tx Swing
input wire pipe_clk , // PIPE Clock
input wire rst_n // Reset
);
//******************************************************************//
// Reality check. //
//******************************************************************//
parameter TCQ = 1; // clock to out delay model
generate
if (PIPE_PIPELINE_STAGES == 0) begin : pipe_stages_0
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_i;
assign pipe_tx_reset_o = pipe_tx_reset_i;
assign pipe_tx_rate_o = pipe_tx_rate_i;
assign pipe_tx_deemph_o = pipe_tx_deemph_i;
assign pipe_tx_margin_o = pipe_tx_margin_i;
assign pipe_tx_swing_o = pipe_tx_swing_i;
end // if (PIPE_PIPELINE_STAGES == 0)
else if (PIPE_PIPELINE_STAGES == 1) begin : pipe_stages_1
reg pipe_tx_rcvr_det_q ;
reg pipe_tx_reset_q ;
reg pipe_tx_rate_q ;
reg pipe_tx_deemph_q ;
reg [2:0] pipe_tx_margin_q ;
reg pipe_tx_swing_q ;
always @(posedge pipe_clk) begin
if (rst_n)
begin
pipe_tx_rcvr_det_q <= #TCQ 0;
pipe_tx_reset_q <= #TCQ 1'b1;
pipe_tx_rate_q <= #TCQ 0;
pipe_tx_deemph_q <= #TCQ 1'b1;
pipe_tx_margin_q <= #TCQ 0;
pipe_tx_swing_q <= #TCQ 0;
end
else
begin
pipe_tx_rcvr_det_q <= #TCQ pipe_tx_rcvr_det_i;
pipe_tx_reset_q <= #TCQ pipe_tx_reset_i;
pipe_tx_rate_q <= #TCQ pipe_tx_rate_i;
pipe_tx_deemph_q <= #TCQ pipe_tx_deemph_i;
pipe_tx_margin_q <= #TCQ pipe_tx_margin_i;
pipe_tx_swing_q <= #TCQ pipe_tx_swing_i;
end
end
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_q;
assign pipe_tx_reset_o = pipe_tx_reset_q;
assign pipe_tx_rate_o = pipe_tx_rate_q;
assign pipe_tx_deemph_o = pipe_tx_deemph_q;
assign pipe_tx_margin_o = pipe_tx_margin_q;
assign pipe_tx_swing_o = pipe_tx_swing_q;
end // if (PIPE_PIPELINE_STAGES == 1)
else if (PIPE_PIPELINE_STAGES == 2) begin : pipe_stages_2
reg pipe_tx_rcvr_det_q ;
reg pipe_tx_reset_q ;
reg pipe_tx_rate_q ;
reg pipe_tx_deemph_q ;
reg [2:0] pipe_tx_margin_q ;
reg pipe_tx_swing_q ;
reg pipe_tx_rcvr_det_qq ;
reg pipe_tx_reset_qq ;
reg pipe_tx_rate_qq ;
reg pipe_tx_deemph_qq ;
reg [2:0] pipe_tx_margin_qq ;
reg pipe_tx_swing_qq ;
always @(posedge pipe_clk) begin
if (rst_n)
begin
pipe_tx_rcvr_det_q <= #TCQ 0;
pipe_tx_reset_q <= #TCQ 1'b1;
pipe_tx_rate_q <= #TCQ 0;
pipe_tx_deemph_q <= #TCQ 1'b1;
pipe_tx_margin_q <= #TCQ 0;
pipe_tx_swing_q <= #TCQ 0;
pipe_tx_rcvr_det_qq <= #TCQ 0;
pipe_tx_reset_qq <= #TCQ 1'b1;
pipe_tx_rate_qq <= #TCQ 0;
pipe_tx_deemph_qq <= #TCQ 1'b1;
pipe_tx_margin_qq <= #TCQ 0;
pipe_tx_swing_qq <= #TCQ 0;
end
else
begin
pipe_tx_rcvr_det_q <= #TCQ pipe_tx_rcvr_det_i;
pipe_tx_reset_q <= #TCQ pipe_tx_reset_i;
pipe_tx_rate_q <= #TCQ pipe_tx_rate_i;
pipe_tx_deemph_q <= #TCQ pipe_tx_deemph_i;
pipe_tx_margin_q <= #TCQ pipe_tx_margin_i;
pipe_tx_swing_q <= #TCQ pipe_tx_swing_i;
pipe_tx_rcvr_det_qq <= #TCQ pipe_tx_rcvr_det_q;
pipe_tx_reset_qq <= #TCQ pipe_tx_reset_q;
pipe_tx_rate_qq <= #TCQ pipe_tx_rate_q;
pipe_tx_deemph_qq <= #TCQ pipe_tx_deemph_q;
pipe_tx_margin_qq <= #TCQ pipe_tx_margin_q;
pipe_tx_swing_qq <= #TCQ pipe_tx_swing_q;
end
end
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_qq;
assign pipe_tx_reset_o = pipe_tx_reset_qq;
assign pipe_tx_rate_o = pipe_tx_rate_qq;
assign pipe_tx_deemph_o = pipe_tx_deemph_qq;
assign pipe_tx_margin_o = pipe_tx_margin_qq;
assign pipe_tx_swing_o = pipe_tx_swing_qq;
end // if (PIPE_PIPELINE_STAGES == 2)
endgenerate
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module ANN_fdiv_32ns_32ns_32_16
#(parameter
ID = 2,
NUM_STAGE = 16,
din0_WIDTH = 32,
din1_WIDTH = 32,
dout_WIDTH = 32
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [31:0] a_tdata;
wire b_tvalid;
wire [31:0] b_tdata;
wire r_tvalid;
wire [31:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
ANN_ap_fdiv_14_no_dsp_32 ANN_ap_fdiv_14_no_dsp_32_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1==='bx ? 'b0 : din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1==='bx ? 'b0 : din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAPVGND_BLACKBOX_V
`define SKY130_FD_SC_HS__TAPVGND_BLACKBOX_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection
* 1 row down.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__tapvgnd ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAPVGND_BLACKBOX_V
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*/
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the add-compare
/**
* Import the modules that will be tested for in this testbench
*
* Include statements for design modules/files need to be commented
* out when I use the Make environment - similar to that in
* Assignment/Homework 3.
*
* Else, the Make/Cadence environment will not be able to locate
* the files that need to be included.
*
* The Make/Cadence environment will automatically search all
* files in the design/ and include/ directories of the working
* directory for this project that uses the Make/Cadence
* environment
*
* If the ".f" files are used to run NC-Verilog to compile and
* simulate the Verilog testbench modules,
*/
`include "acs.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
module tb_acs();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the arbiter
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
wire [3:0] new_pm; // Output signal npm
wire decision; // Output signal d
// Declare "reg" signals: inputs to the DUT
reg [1:0] brch_m1; // Input signal - bm1
reg [1:0] brch_m2; // Input signal - bm2
reg [3:0] path_m1; // Input signal - pm1
reg [3:0] path_m2; // Input signal - pm2
/**
* Instantiate an instance of arbiter_LRU4 so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "arb"
*/
add_compare_select acs_cir (
// instance_name(signal name),
// Signal name can be the same as the instance name
new_pm,decision,path_m1,brch_m1,path_m2,brch_m2);
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
// @t=0,
path_m1 = 4'd0;
brch_m1 = 2'd0;
path_m2 = 4'd0;
brch_m2 = 2'd0;
// @t=1,
#1
path_m1 = 4'd0;
brch_m1 = 2'd1;
path_m2 = 4'd6;
brch_m2 = 2'd2;
// @t=2,
#1
path_m1 = 4'd7;
brch_m1 = 2'd2;
path_m2 = 4'd0;
brch_m2 = 2'd3;
// @t=3,
#1
path_m1 = 4'd14;
brch_m1 = 2'd1;
path_m2 = 4'd13;
brch_m2 = 2'd0;
// @t=4,
#1
path_m1 = 4'd9;
brch_m1 = 2'd3;
path_m2 = 4'd8;
brch_m2 = 2'd1;
// @t=5,
#1
path_m1 = 4'd15;
brch_m1 = 2'd1;
path_m2 = 4'd15;
brch_m2 = 2'd0;
// @t=6,
#1
path_m1 = 4'd15;
brch_m1 = 2'd1;
path_m2 = 4'd15;
brch_m2 = 2'd2;
// @t=7,
#1
path_m1 = 4'd13;
brch_m1 = 2'd3;
path_m2 = 4'd14;
brch_m2 = 2'd2;
// @t=8,
#1
path_m1 = 4'd14;
brch_m1 = 2'd3;
path_m2 = 4'd15;
brch_m2 = 2'd3;
// @t=9,
#1
path_m1 = 4'd15;
brch_m1 = 2'd3;
path_m2 = 4'd15;
brch_m2 = 2'd3;
// @t=10,
#1
path_m1 = 4'd16;
brch_m1 = 2'd8;
path_m2 = 4'd2;
brch_m2 = 2'd3;
// @t=11,
#1
path_m1 = 4'd12;
brch_m1 = 2'd2;
path_m2 = 4'd12;
brch_m2 = 2'd1;
// @t=12,
#1
path_m1 = 4'd9;
brch_m1 = 2'd1;
path_m2 = 4'd10;
brch_m2 = 2'd2;
#20;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; bool adj[200][200]; int bfs(int source, int dest) { bool vis[200]; for (int i = 0; i < 200; i++) vis[i] = 0; queue<pair<int, int> > qe; qe.push({source, 0}); while (!qe.empty()) { int node = qe.front().first; int d = qe.front().second; qe.pop(); if (node == dest) return d; vis[node] = 1; for (int i = 0; i < 200; i++) { if (adj[node][i] and !vis[i]) qe.push({i, d + 1}); } } return INT_MAX; } int main() { int n; cin >> n; vector<long long> arr; while (n--) { long long x; cin >> x; if (x != 0) arr.push_back(x); } n = arr.size(); if (n > 128) { cout << 3 << endl; return 0; } for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (arr[i] & arr[j]) adj[i][j] = 1; } } int min_cycle = INT_MAX; for (int i = 0; i < n; i++) { for (int j = i + 1; j < n; j++) { if (adj[i][j]) { adj[i][j] = 0; adj[j][i] = 0; int m = bfs(i, j); min_cycle = min(m, min_cycle); adj[i][j] = 1; adj[j][i] = 1; } } } if (min_cycle > 10000000) cout << -1 << endl; else cout << min_cycle + 1 << endl; } |
#include <bits/stdc++.h> using namespace std; long long int modexpo(long long int x, long long int y) { if (y == 0) return 1; if (y % 2) { long long int viky = modexpo(x, y / 2); return (((x * viky) % 1000000000) * viky) % 1000000000; } else { long long int viky = modexpo(x, y / 2); return (viky * viky) % 1000000000; } } long long int a[1111]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int t, i, j, l, m, n, r, q, k, c, x; cin >> n; for (i = 1; i < n; i++) { cin >> l >> r; a[r]++; a[l]++; } c = 0; for (i = 1; i <= n; i++) { if (a[i] == 1) c++; } cout << c; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, m; cin >> n >> m; char grid[n][m]; int x1 = 1e9, y1 = 1e9, x2 = 0, y2 = 0; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { cin >> grid[i][j]; if (grid[i][j] == X ) x1 = min(x1, i), y1 = min(y1, j), x2 = max(x2, i), y2 = max(y2, j); } bool ok = true; for (int i = x1; i <= x2; i++) for (int j = y1; j <= y2; j++) if (grid[i][j] != X ) ok = false; if (ok) cout << YES << endl; else cout << NO << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; long long modpow(long long a, long long b, long long mod = (long long)(1e9 + 7)) { if (!b) return 1; a %= mod; return modpow(a * a % mod, b / 2, mod) * (b & 1 ? a : 1) % mod; } mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); const int mxn = 1100; char string1[mxn]; char string2[mxn]; int xt1[mxn], xt2[mxn], xt3[mxn]; int bound[mxn]; int n, m; void solution() { long long answer = 0; scanf( %d , &n); scanf( %d , &m); for (int i = 0; i < n; i++) { scanf( %s , string2); long long composite = 0; for (int j = 0; j < m; j++) { if (string2[j] != string1[j]) { xt1[j] = xt2[j]; xt2[j] = xt3[j]; xt3[j] = 1; } else { xt3[j]++; } if (j > 0) { if (string2[j] == string2[j - 1]) bound[j]++; else bound[j] = 0; } if (xt1[j] >= xt2[j] && xt2[j] == xt3[j]) { composite++; if (bound[j] < xt3[j] * 3) composite = 1; } else composite = 0; string1[j] = string2[j]; answer += composite; } } cout << answer << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); solution(); return 0; } |
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 07/01/2009
This optional block is used for two purposes:
1) Relay response information back to the host typically in ST->MM mode.
This information is 'actual bytes transferred', 'error', and 'early termination'.
2) Relay response and interrupt information back to a prefetching master block
that will write the contents back to memory. Interrupt information is also passed
since the interrupt needs to occur when the prefetching master block overwrites
the descriptor in main memory and not when the event occurs. The host needs to read
the interrupt condition out of memory so it could potentially get out of sync if
the interrupt information wasn't buffered and delayed.
This block has three response port options: MM slave, ST source, and disabled.
When you don't need access to response information (MM->MM or MM->ST) or interrupts in
the case of a prefetching descriptor master then you can safely disable the port.
By disabling the port you will not consume any logic resources or on-chip memory blocks.
When the source port is enabled bit 52 of the data stream represents the "descriptor full"
condition. The descriptor prefetching master can use this signal to perform pipelined reads
without having to worry about flow control (since there is room for an entire descriptor to be
written). This is benefical as apposed to performing descriptor reads, buffering the data, then
writting it out to the descriptor buffer block.
Version 1.0
1.0 - If you attempt to use the wrong response port type you will be issued a warning
but allowed to generate. This is because in some cases you may not need the typical
behavior. For example if you perform MM->MM transfers with some streaming IP between
the read and write masters you still might need access to error bits. Likewise
if you don't enable the streaming sink port while using a descriptor pre-fetching block
you may not care if you get interrupted early and want to use the CSR block for interrupts
instead.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module response_block (
clk,
reset,
mm_response_readdata,
mm_response_read,
mm_response_address,
mm_response_byteenable,
mm_response_waitrequest,
src_response_data,
src_response_valid,
src_response_ready,
sw_reset,
response_watermark,
response_fifo_full,
response_fifo_empty,
done_strobe,
actual_bytes_transferred,
error,
early_termination,
transfer_complete_IRQ_mask,
error_IRQ_mask,
early_termination_IRQ_mask,
descriptor_buffer_full
);
parameter RESPONSE_PORT = 0; // when disabled all the outputs will be disconnected by the component wrapper
parameter FIFO_DEPTH = 256; // needs to be double the descriptor FIFO depth
parameter FIFO_DEPTH_LOG2 = 8;
localparam FIFO_WIDTH = (RESPONSE_PORT == 0)? 41 : 51; // when 'RESPONSE_PORT' is 1 then the response port is set to streaming and must pass the interrupt masks as well
input clk;
input reset;
output wire [31:0] mm_response_readdata;
input mm_response_read;
input mm_response_address; // only have 2 addresses
input [3:0] mm_response_byteenable;
output wire mm_response_waitrequest;
output wire [255:0] src_response_data; // not going to use all these bits, the remainder will be grounded
output wire src_response_valid;
input src_response_ready;
input sw_reset;
output wire [15:0] response_watermark;
output wire response_fifo_full;
output wire response_fifo_empty;
input done_strobe;
input [31:0] actual_bytes_transferred;
input [7:0] error;
input early_termination;
// all of these signals are only used the ST source response port since the pre-fetching master component will handle the interrupt generation as apposed to the CSR block
input transfer_complete_IRQ_mask;
input [7:0] error_IRQ_mask;
input early_termination_IRQ_mask;
input descriptor_buffer_full; // handy signal for the prefetching master to use so that it known when to blast a new descriptor into the dispatcher
/* internal signals and registers */
wire [FIFO_DEPTH_LOG2-1:0] fifo_used;
wire fifo_full;
wire fifo_empty;
wire fifo_read;
wire [FIFO_WIDTH-1:0] fifo_input;
wire [FIFO_WIDTH-1:0] fifo_output;
generate
if (RESPONSE_PORT == 0) // slave port used for response data
begin
assign fifo_input = {early_termination, error, actual_bytes_transferred};
assign fifo_read = (mm_response_read == 1) & (fifo_empty == 0) & (mm_response_address == 1) & (mm_response_byteenable[3] == 1); // reading from the upper byte (byte offset 7) pops the fifo
scfifo the_response_FIFO (
.clock (clk),
.aclr (reset),
.sclr (sw_reset),
.data (fifo_input),
.wrreq (done_strobe),
.rdreq (fifo_read),
.q (fifo_output),
.full (fifo_full),
.empty (fifo_empty),
.usedw (fifo_used)
);
defparam the_response_FIFO.lpm_width = FIFO_WIDTH;
defparam the_response_FIFO.lpm_numwords = FIFO_DEPTH;
defparam the_response_FIFO.lpm_widthu = FIFO_DEPTH_LOG2;
defparam the_response_FIFO.lpm_showahead = "ON";
defparam the_response_FIFO.use_eab = "ON";
defparam the_response_FIFO.overflow_checking = "OFF";
defparam the_response_FIFO.underflow_checking = "OFF";
defparam the_response_FIFO.add_ram_output_register = "ON";
defparam the_response_FIFO.lpm_type = "scfifo";
// either actual bytes transfered when address == 0 or {zero padding, early_termination, error[7:0]} when address = 1
assign mm_response_readdata = (mm_response_address == 0)? fifo_output[31:0] : {{23{1'b0}}, fifo_output[40:32]};
assign mm_response_waitrequest = fifo_empty;
assign response_watermark = {{(16-(FIFO_DEPTH_LOG2+1)){1'b0}}, fifo_full, fifo_used}; // zero padding plus the 'true used' FIFO amount
assign response_fifo_full = fifo_full;
assign response_fifo_empty = fifo_empty;
// no streaming port so ground all of its outputs
assign src_response_data = 0;
assign src_response_valid = 0;
end
else if (RESPONSE_PORT == 1) // streaming source port used for response data (prefetcher will catch this data)
begin
assign fifo_input = {early_termination_IRQ_mask, error_IRQ_mask, transfer_complete_IRQ_mask, early_termination, error, actual_bytes_transferred};
assign fifo_read = (fifo_empty == 0) & (src_response_ready == 1);
scfifo the_response_FIFO (
.clock (clk),
.aclr (reset | sw_reset),
.data (fifo_input),
.wrreq (done_strobe),
.rdreq (fifo_read),
.q (fifo_output),
.full (fifo_full),
.empty (fifo_empty),
.usedw (fifo_used)
);
defparam the_response_FIFO.lpm_width = FIFO_WIDTH;
defparam the_response_FIFO.lpm_numwords = FIFO_DEPTH;
defparam the_response_FIFO.lpm_widthu = FIFO_DEPTH_LOG2;
defparam the_response_FIFO.lpm_showahead = "ON";
defparam the_response_FIFO.use_eab = "ON";
defparam the_response_FIFO.overflow_checking = "OFF";
defparam the_response_FIFO.underflow_checking = "OFF";
defparam the_response_FIFO.add_ram_output_register = "ON";
defparam the_response_FIFO.lpm_type = "scfifo";
assign src_response_data = {{204{1'b0}}, descriptor_buffer_full, fifo_output}; // zero padding the upper bits, also sending out the descriptor buffer full signal to simplify the throttling in the prefetching master (bit 52)
assign src_response_valid = (fifo_empty == 0);
assign response_watermark = {{(16-(FIFO_DEPTH_LOG2+1)){1'b0}}, fifo_full, fifo_used}; // zero padding plus the 'true used' FIFO amount;
assign response_fifo_full = fifo_full;
assign response_fifo_empty = fifo_empty;
// no slave port so ground all of its outputs
assign mm_response_readdata = 0;
assign mm_response_waitrequest = 0;
end
else // no response port so grounding all outputs
begin
assign fifo_input = 0;
assign fifo_output = 0;
assign mm_response_readdata = 0;
assign mm_response_waitrequest = 0;
assign src_response_data = 0;
assign src_response_valid = 0;
assign response_watermark = 0;
assign response_fifo_full = 0;
assign response_fifo_empty = 0;
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__MUX2_SYMBOL_V
`define SKY130_FD_SC_HVL__MUX2_SYMBOL_V
/**
* mux2: 2-input multiplexer.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__mux2 (
//# {{data|Data Signals}}
input A0,
input A1,
output X ,
//# {{control|Control Signals}}
input S
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__MUX2_SYMBOL_V
|
#include <bits/stdc++.h> const int MAX = 1e3 + 5; using namespace std; int edge, mx, ans, seen[MAX], a, n, m, k, spec[MAX], check[MAX][MAX]; vector<int> adj[MAX]; vector<int> cur; void dfs(int node) { if (seen[node] == 1) return; seen[node] = 1; cur.push_back(node); for (int i = int(0); i <= int(adj[node].size() - 1); i++) dfs(adj[node][i]); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> n >> m >> k; for (int i = int(1); i <= int(k); i++) cin >> a, spec[a] = 1; for (int i = int(1); i <= int(m); i++) { int u, v; cin >> u >> v; adj[u].push_back(v); adj[v].push_back(u); check[u][v] = check[v][u] = 1; } for (int i = int(1); i <= int(n); i++) if (spec[i] == 1) { dfs(i); mx = max(int(cur.size()), mx); int comb = (cur.size() == 1 ? 0 : (cur.size() * (cur.size() - 1) / 2)); for (int i = int(0); i <= int(cur.size() - 1); i++) { for (int j = int(i + 1); j <= int(cur.size() - 1); j++) edge += check[cur[i]][cur[j]]; } ans += comb - edge; cur.clear(); edge = 0; } for (int i = int(1); i <= int(n); i++) { if (seen[i] == 1) continue; dfs(i); int comb = (cur.size() == 1 ? 0 : (cur.size() * (cur.size() - 1) / 2)); for (int i = int(0); i <= int(cur.size() - 1); i++) { for (int j = int(i + 1); j <= int(cur.size() - 1); j++) edge += check[cur[i]][cur[j]]; } ans += comb - edge; ans += mx * int(cur.size()); mx += cur.size(); cur.clear(); edge = 0; } cout << ans << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); vector<int> r(7, 0); string den; for (int i = 0; i < n; i++) { cin >> den; for (int j = 0; den[j] != 0 ; j++) { r[j] += den[j] == 1 ; } } int m = 0; for (int i = 0; i < 7; i++) { m = max(m, r[i]); } printf( %d n , m); getchar(); getchar(); } |
#include <bits/stdc++.h> inline int getx() { char c; int x; for (c = getchar(); c < 0 || c > 9 ; c = getchar()) ; for (x = 0; c >= 0 && c <= 9 ; c = getchar()) x = (x << 3) + (x << 1) + c - 0 ; return x; } bool upmax(int &a, const int &b) { return a < b ? a = b, 1 : 0; } const int MAX_N = 10050; int n, m; int v[MAX_N], c[MAX_N]; int f[MAX_N]; int main() { n = getx(), m = getx(); int c0 = getx(), d0 = getx(); for (int i = c0; i <= n; ++i) upmax(f[i], f[i - c0] + d0); for (int i = 1; i <= m; ++i) { int a = getx(), b = getx(), c = getx(), d = getx(); for (int p = b; p <= a; p += b) { for (int j = n; j >= c; --j) upmax(f[j], f[j - c] + d); } } printf( %d n , f[n]); } |
/**
* bsg_fpu_cmp.v
*
* @author Tommy Jung
*
* parameterized floating-point comparator.
*
* comparison
* - eq_o: equal
* - lt_o: less than
* - le_o: less or equal
*
* Note:
* - lt and le raises invalid exception if either input is NaN.
* - eq raises invalid exception only when there is signaling NaN input.
*
* min-max
* - if either input is signaling NaN, the result is canonical NaN.
* also, the invalid exception is raised.
* - if both inputs are quiet NaN, the result is canonical NaN.
* - if one is quiet NaN and the other is non-NaN,
* then the result is non-NaN input.
* - if both inputs are (positive or negative zero), then the output is
* positive zero.
*
*/
`include "bsg_defines.v"
`include "bsg_fpu_defines.vh"
module bsg_fpu_cmp
#(parameter `BSG_INV_PARAM(e_p)
, parameter `BSG_INV_PARAM(m_p)
)
(
input [e_p+m_p:0] a_i
, input [e_p+m_p:0] b_i
// comparison
, output logic eq_o
, output logic lt_o
, output logic le_o
, output logic lt_le_invalid_o
, output logic eq_invalid_o
// min-max
, output logic [e_p+m_p:0] min_o
, output logic [e_p+m_p:0] max_o
, output logic min_max_invalid_o
);
// preprocess
//
logic a_zero, a_nan, a_sig_nan, a_infty, a_sign;
logic b_zero, b_nan, b_sig_nan, b_infty, b_sign;
bsg_fpu_preprocess #(
.e_p(e_p)
,.m_p(m_p)
) a_preprocess (
.a_i(a_i)
,.zero_o(a_zero)
,.nan_o(a_nan)
,.sig_nan_o(a_sig_nan)
,.infty_o(a_infty)
,.exp_zero_o()
,.man_zero_o()
,.denormal_o()
,.sign_o(a_sign)
,.exp_o()
,.man_o()
);
bsg_fpu_preprocess #(
.e_p(e_p)
,.m_p(m_p)
) b_preprocess (
.a_i(b_i)
,.zero_o(b_zero)
,.nan_o(b_nan)
,.sig_nan_o(b_sig_nan)
,.infty_o(b_infty)
,.exp_zero_o()
,.man_zero_o()
,.denormal_o()
,.sign_o(b_sign)
,.exp_o()
,.man_o()
);
// compare
//
logic mag_a_lt;
bsg_less_than #(
.width_p(e_p+m_p)
) lt_mag (
.a_i(a_i[0+:e_p+m_p])
,.b_i(b_i[0+:e_p+m_p])
,.o(mag_a_lt)
);
// comparison
//
always_comb begin
if (a_nan | b_nan) begin
eq_o = 1'b0;
lt_o = 1'b0;
le_o = 1'b0;
lt_le_invalid_o = 1'b1;
eq_invalid_o = a_sig_nan | b_sig_nan;
end
else begin
if (a_zero & b_zero) begin
eq_o = 1'b1;
lt_o = 1'b0;
le_o = 1'b1;
lt_le_invalid_o = 1'b0;
eq_invalid_o = 1'b0;
end
else begin
// a and b are neither NaNs nor zeros.
// compare sign and compare magnitude.
eq_o = (a_i == b_i);
lt_le_invalid_o = 1'b0;
eq_invalid_o = 1'b0;
case ({a_sign, b_sign})
2'b00: begin
lt_o = mag_a_lt;
le_o = mag_a_lt | eq_o;
end
2'b01: begin
lt_o = 1'b0;
le_o = 1'b0;
end
2'b10: begin
lt_o = 1'b1;
le_o = 1'b1;
end
2'b11: begin
lt_o = ~mag_a_lt & ~eq_o;
le_o = ~mag_a_lt | eq_o;
end
endcase
end
end
end
// min-max
//
always_comb begin
if (a_nan & b_nan) begin
min_o = `BSG_FPU_QUIETNAN(e_p,m_p);
max_o = `BSG_FPU_QUIETNAN(e_p,m_p);
min_max_invalid_o = a_sig_nan | b_sig_nan;
end
else if (a_nan & ~b_nan) begin
min_o = b_i;
max_o = b_i;
min_max_invalid_o = a_sig_nan;
end
else if (~a_nan & b_nan) begin
min_o = a_i;
max_o = a_i;
min_max_invalid_o = b_sig_nan;
end
else begin
min_max_invalid_o = 1'b0;
if (a_zero & b_zero) begin
min_o = `BSG_FPU_ZERO(a_sign | b_sign, e_p, m_p);
max_o = `BSG_FPU_ZERO(a_sign & b_sign, e_p, m_p);
end
else if (lt_o) begin
min_o = a_i;
max_o = b_i;
end
else begin
min_o = b_i;
max_o = a_i;
end
end
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_fpu_cmp)
|
#include <bits/stdc++.h> using namespace std; int main() { const int MAX_N = 200000; int n; char s[MAX_N][20]; set<string> chat; scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %s , s[i]); } for (int i = n - 1; i >= 0; i--) { if (chat.find(s[i]) == chat.end()) { printf( %s n , s[i]); } chat.insert(s[i]); } return 0; } |
module clock_counter(
input clk_i, //often, "tags" are added to variables to denote what they do for the user
input reset_n, //here, 'i' is used for input and 'o' for the output, while 'n' specifies an active low signal ("not")
output reg clk_o
);
reg [14:0] count; //register stores the counter value so that it can be modified on a clock edge. register size needs to store as large of a number as the counter reaches
//for this implementation, count must reach 415999, so 2^n >= 415999, n = 19
always @ (posedge clk_i, negedge reset_n)
begin
count <= count + 1; //at every positive edge, the counter is increased by 1
if(!reset_n)
begin
clk_o <= 0;
count <= 0; //if reset (active low) is pushed, the counter is reset
end
else
if(count >= 5000) //initial 17330 //count value of greater than or equal to this value causes the output clock to be inverted. the resulting frequency will be input_frequency/(1+count_value)
begin //for this implementation, a frequency of 5 Hz was desired, so 2.08e6/5 - 1 = 415999
clk_o <= ~clk_o;
count <= 0; //resets the counter after the output clock has been inverted
end
end
endmodule |
#include <bits/stdc++.h> using namespace std; int main() { { long long int r, n, c, m, i, j, count = 0, x, a, b, y, sum = 0; long long int mn = 1e18, mx = 0, ans = 0, k, ind; long long int br = 0, T, rz = 0; string s = ; cin >> n; long long int a1, a2, a3, b1, b2, b3; cin >> a1 >> a2 >> a3; cin >> b1 >> b2 >> b3; mx = max(mx, a1 - b1 - b3); mx = max(mx, a2 - b1 - b2); mx = max(mx, a3 - b2 - b3); mn = 0; mn += min(a1, b2); mn += min(a2, b3); mn += min(a3, b1); cout << mx << << mn << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long MAXN = 1e6, mod = 1000000007; long long n, m, x, k, d, p, z, sum; vector<long long> v, ans; set<long long> st; int main() { cin >> n >> k; for (long long i = 1; i <= 2 * n; i *= 2) v.push_back(i - 1); if (k == 1) { cout << n; return 0; } else { for (int i = v.size() - 1; i >= 0; i--) { if (i == 0 || (v[i] >= n && v[i - 1] < n)) { cout << v[i]; return 0; } } } return 0; } |
#include <bits/stdc++.h> int a[100010]; int main() { int n; int b = 0, c = 0, d = 0, td = 0, ex1 = 0, ex2 = 0, ex; scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d , &a[i]); if (a[i] == 1) b++; else if (a[i] == 2) c++; else if (a[i] == 3) d++; else if (a[i] == 4) td++; } td += d; if (c % 2 == 0) { td += (c / 2); } else { ex2 = (c % 2); td += (c / 2); } if (b > d) { ex1 = b - d; } ex = (2 * ex2) + ex1; if (ex % 4 == 0) td += (ex / 4); else td += (ex / 4) + 1; printf( %d , td); return 0; } |
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010, 2011 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module minimac2_psync(
input clk1,
input i,
input clk2,
output o
);
reg level;
always @(posedge clk1)
if(i)
level <= ~level;
reg level1;
reg level2;
reg level3;
always @(posedge clk2) begin
level1 <= level;
level2 <= level1;
level3 <= level2;
end
assign o = level2 ^ level3;
initial begin
level <= 1'b0;
level1 <= 1'b0;
level2 <= 1'b0;
level3 <= 1'b0;
end
endmodule
|
// ###############################################################
// # FUNCTION: Synchronous clock divider that divides by integer
// ###############################################################
module clock_divider(/*AUTOARG*/
// Outputs
clkout, clkout90,
// Inputs
clkin, divcfg, reset
);
input clkin; // Input clock
input [3:0] divcfg; // Divide factor
input reset; // Counter init
output clkout; // Divided clock phase aligned with clkin
output clkout90; // Divided clock with 90deg phase shift with clkout
reg clkout_reg;
reg [7:0] counter;
reg [7:0] divcfg_dec;
reg [3:0] divcfg_reg;
reg [3:0] divcfg_change;
wire div2_sel;
wire div1_sel;
wire posedge_match;
wire negedge_match;
wire posedge90_match;
wire negedge90_match;
reg clkout90_div4;
reg clkout90_div2;
// ###################
// # Decode divcfg
// ###################
always @ (divcfg[3:0])
casez (divcfg[3:0])
4'b0001 : divcfg_dec[7:0] = 8'b00000010; // Divide by 2
4'b0010 : divcfg_dec[7:0] = 8'b00000100; // Divide by 4
4'b0011 : divcfg_dec[7:0] = 8'b00001000; // Divide by 8
4'b0100 : divcfg_dec[7:0] = 8'b00010000; // Divide by 16
4'b0101 : divcfg_dec[7:0] = 8'b00100000; // Divide by 32
4'b0110 : divcfg_dec[7:0] = 8'b01000000; // Divide by 64
4'b0111 : divcfg_dec[7:0] = 8'b10000000; // Divide by 128
default : divcfg_dec[7:0] = 8'b00000000; // others
endcase
//Divide by two special case
assign div2_sel = divcfg[3:0]==4'b0001;
assign div1_sel = divcfg[3:0]==4'b0000;
//Edge change detector (no need for synchronizer)
always @ (posedge clkin or posedge reset)
if(reset)
divcfg_change <=1'b0;
else
begin
divcfg_change <= (divcfg_reg[3:0]^divcfg[3:0]);
divcfg_reg[3:0] <=divcfg[3:0];
end
always @ (posedge clkin or posedge reset)
if(reset)
counter[7:0] <= 8'b000001;
else
if(posedge_match | divcfg_change)
counter[7:0] <= 8'b000001;// Self resetting
else
counter[7:0] <= (counter[7:0] + 8'b000001);
assign posedge_match = (counter[7:0]==divcfg_dec[7:0]);
assign negedge_match = (counter[7:0]=={1'b0,divcfg_dec[7:1]});
assign posedge90_match = (counter[7:0]==({2'b00,divcfg_dec[7:2]}));
assign negedge90_match = (counter[7:0]==({2'b00,divcfg_dec[7:2]} +
{1'b0,divcfg_dec[7:1]}));
always @ (posedge clkin or posedge reset)
if(reset)
clkout_reg <= 1'b0;
else if(posedge_match)
clkout_reg <= 1'b1;
else if(negedge_match)
clkout_reg <= 1'b0;
assign clkout = div1_sel ? clkin : clkout_reg;
always @ (posedge clkin)
clkout90_div4 <= posedge90_match ? 1'b1 :
negedge90_match ? 1'b0 :
clkout90_div4;
always @ (negedge clkin)
clkout90_div2 <= negedge_match ? 1'b1 :
posedge_match ? 1'b0 :
clkout90_div2;
assign clkout90 = div2_sel ? clkout90_div2 : clkout90_div4;
endmodule // clock_divider
/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Andreas Olofsson <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
|
#include <bits/stdc++.h> using namespace std; multiset<long long> s[200004]; long long a[200005]; long long su[200005]; int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); long long n, k; cin >> n >> k; for (long long i = 0; i < n; i++) { cin >> a[i]; } long long x; for (long long i = 0; i < n; i++) { x = 0; while (true) { s[a[i]].insert(x); su[a[i]] += x; if (s[a[i]].size() > k) { set<long long>::iterator pointer = s[a[i]].end(); pointer--; su[a[i]] -= *pointer; s[a[i]].erase(pointer); } if (a[i] == 0) break; a[i] /= 2; x++; } } long long minn = 1e9; for (long long i = 0; i < 200005; i++) { if (s[i].size() == k) { minn = min(minn, su[i]); } } cout << minn; return 0; } |
#include <bits/stdc++.h> using namespace std; typedef int nod[100010]; typedef int edg[200010]; int n, m; int e = 1; nod h; edg link, v, u; nod vis; nod fz; int ju; void creat(int x, int y) { link[++e] = h[x]; h[x] = e; v[e] = y; link[++e] = h[y]; h[y] = e; v[e] = x; } int dfs(int x) { if (vis[x]) return 0; else vis[x] = 1; for (int i = h[x]; i; i = link[i]) if (!u[i]) { u[i] = u[i ^ 1] = 1; if ((ju = dfs(v[i]))) printf( %d %d %d n , x, v[i], ju); else if (!fz[x]) fz[x] = v[i]; else printf( %d %d %d n , fz[x], x, v[i]), fz[x] = 0; } return fz[x]; } int main() { scanf( %d%d , &n, &m); if (m & 1) { printf( No solution n ); return 0; } for (int i = 1, x, y; i <= m; ++i) scanf( %d%d , &x, &y), creat(x, y); dfs(1); return 0; } |
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* Simple/useful components
*
*/
module LAG_data_reg (data_in, data_out, clk, rst_n);
input flit_t data_in;
output flit_t data_out;
input clk, rst_n;
always@(posedge clk) begin
if (!rst_n) begin
data_out <= '0;
end else begin
data_out <= data_in;
end
end
endmodule
module LAG_ctrl_reg (ctrl_in, ctrl_out, clk, rst_n);
input chan_cntrl_t ctrl_in;
output chan_cntrl_t ctrl_out;
input clk, rst_n;
always@(posedge clk) begin
if (!rst_n) begin
ctrl_out <= '0;
end else begin
ctrl_out <= ctrl_in;
end
end
endmodule
module LAG_pipelined_channel (data_in, ctrl_in, data_out, ctrl_out, clk, rst_n);
parameter stages = 0;
parameter nPC = 1; // Number of physical channels per trunk
input flit_t data_in[nPC-1:0];
input [nPC-1:0] ctrl_in;
output flit_t data_out[nPC-1:0];
output [nPC-1:0] ctrl_out;
input clk, rst_n;
genvar st, pc;
flit_t ch_reg[stages-1:0][nPC-1:0];
chan_cntrl_t ctrl_reg[stages-1:0];
generate
if (stages==0) begin
// no registers in channel
assign data_out = data_in;
assign ctrl_out = ctrl_in;
end else begin
for (st=0; st<stages; st++) begin:eachstage
if (st==0) begin
for (pc = 0; pc < nPC; pc++) begin:eachPC1
LAG_data_reg data_rg (.data_in(data_in[pc]), .data_out(ch_reg[0][pc]), .clk, .rst_n);
end
//LAG_ctrl_reg ctrl_rg (.ctrl_in(ctrl_in), .ctrl_out(ctrl_reg[0]), .clk, .rst_n);
end else begin
for (pc = 0; pc < nPC; pc++) begin:eachPC2
LAG_data_reg data_rg (.data_in(ch_reg[st-1][pc]), .data_out(ch_reg[st][pc]), .clk, .rst_n);
end
//LAG_ctrl_reg ctrl_rg (.ctrl_in(ctrl_reg[st-1]), .ctrl_out(ctrl_reg[st]), .clk, .rst_n);
end
end
assign data_out = ch_reg[stages-1];
//assign ctrl_out = ctrl_reg[stages-1];
assign ctrl_out = ctrl_in;
end
endgenerate
endmodule
//
// Multiplexer with one-hot encoded select input
//
// - output is '0 if no select input is asserted
//
module LAG_mux_oh_select (data_in, select, data_out);
parameter np = 4;
parameter max_links_num = 2;
parameter integer links[np][2] = '{'{2,2}, '{2,2}, '{2,2}, '{2,2}, '{2,2} };
input flit_t data_in [np*max_links_num-1:0];
input [np*max_links_num-1:0] select;
output flit_t data_out;
integer i,j;
always_comb
begin
data_out='0;
for (i=0; i<np; i++)
for (j=0; j < links[i][IN];j++)
if (select[i*max_links_num+j]) data_out = data_in[i*max_links_num+j];
end
endmodule // LAG_mux_oh_select
//
// Crossbar built from multiplexers, one-hot encoded select input
//
module LAG_crossbar_oh_select (data_in, select, data_out);
parameter np = 5;
parameter max_links_num = 2;
parameter integer links[np][2] = '{'{2,2}, '{2,2}, '{2,2}, '{2,2}, '{2,2} };
input flit_t data_in [np*max_links_num-1:0];
input [np*max_links_num-1:0][np*max_links_num-1:0] select; // n one-hot encoded select signals per output
output flit_t data_out [np*max_links_num-1:0];
genvar i,j;
generate
for (i=0; i<np; i++) begin:out_ports_1
for (j=0; j < links[i][OUT];j++) begin:out_links_1
LAG_mux_oh_select #(.np(np),
.max_links_num(max_links_num),
.links(links) ) xbarmux (data_in, select[i*max_links_num+j], data_out[i*max_links_num+j]);
end
end
endgenerate
endmodule // LAG_crossbar_oh_select
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR2_SYMBOL_V
`define SKY130_FD_SC_HS__NOR2_SYMBOL_V
/**
* nor2: 2-input NOR.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nor2 (
//# {{data|Data Signals}}
input A,
input B,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR2_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; char dat[1048576]; long long countSub(long long a, long long b, long long left, long long right, long long d) { long long low = b * d - a; if (low < 0) { if (a % b != 0) { low = b - a % b; } else { low = 0; } } long long high = left + right; if (low > high) return 0; high -= (high - low) % b; if (left > right) swap(left, right); long long ans = 0; long long firstcnt = 0, fb = low; long long secondcnt = 0, sb = 0; long long thirdcnt = 0, tb = 0; if (fb <= left) { if (high <= left) { firstcnt = (high - fb) / b + 1; } else { firstcnt = (left - fb) / b + 1; } } sb = fb + firstcnt * b; if (high >= sb && sb <= right) { if (high <= right) { secondcnt = (high - sb) / b + 1; } else if (high > right) { secondcnt = (right - sb) / b + 1; } } tb = sb + secondcnt * b; if (high >= tb) { thirdcnt = (high - tb) / b + 1; } if (firstcnt > 0) ans += ((fb + 1) + (fb + (firstcnt - 1) * b + 1)) * firstcnt / 2; if (secondcnt > 0) ans += ((left + 1) + (left + 1)) * secondcnt / 2; if (thirdcnt > 0) ans += ((left + right + 1 - (tb)) + (left + right + 1 - (tb + (thirdcnt - 1) * b))) * thirdcnt / 2; return ans; } int main() { scanf( %s , dat); int n = (int)strlen(dat); int n0 = 0, n1 = 0; for (int i = 0; i < n; i++) { if (dat[i] == 0 ) { n0++; } else { n1++; } } long long ans = 0; int maxratio = 0; for (int ratio = 0; ratio <= 100 || 12 * ratio * ratio <= n; ratio++) { maxratio = ratio; long long depth = 0; unordered_map<long long, int> cnt; cnt.reserve(n + 10); cnt[0] = 1; for (int i = 0; i < n; i++) { if (dat[i] == 0 ) { depth--; } else { depth += ratio; } ans += (cnt[depth]++); } } vector<int> ones; for (int i = 0; i < n; i++) if (dat[i] == 1 ) ones.emplace_back(i); for (int i = 0; i < ones.size(); i++) { for (int j = i; j < ones.size(); j++) { int onecnt = j - i + 1; if (onecnt * maxratio > n0) break; int left = (i == 0 ? ones[0] : (ones[i] - ones[i - 1] - 1)); int right = (j + 1 == ones.size() ? (n - 1 - ones[j]) : (ones[j + 1] - ones[j] - 1)); int zerocnt = ones[j] - ones[i] + 1 - onecnt; ans += countSub(zerocnt, onecnt, left, right, maxratio + 1); } } printf( %lld n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const long long inf = 1e15; const int N = 1e6 + 6; int n, q, b[N], t; queue<int> even, odd, ans; int main() { scanf( %d%d , &n, &q); for (int i = 1; i <= n; i++) { if (i % 2) odd.push(i); else even.push(i); } int len, Lipoter = 1, flag = 1; for (int i = 1; i <= q; i++) { scanf( %d , &t); if (t == 1) { scanf( %d , &len); flag = (flag + len + n) % n; if (flag == 0) flag = n; } else { if (flag % 2) { if (Lipoter == 0) { even.push(even.front()); even.pop(); } else Lipoter = 0; } else { if (Lipoter == 1) { odd.push(odd.front()); odd.pop(); } else Lipoter = 1; } if (flag % 2) flag++; else flag--; if (flag == 0) flag = n; } } if (Lipoter) { while (!even.empty() && !odd.empty()) { ans.push(odd.front()); odd.pop(); ans.push(even.front()); even.pop(); } } else { while (!even.empty() && !odd.empty()) { ans.push(even.front()); even.pop(); ans.push(odd.front()); odd.pop(); } } while (1) { if (ans.front() == 1) break; else { ans.push(ans.front()); ans.pop(); } } while (flag <= n) { b[flag++] = ans.front(); ans.pop(); } int cnt = 1; while (!ans.empty()) { b[cnt++] = ans.front(); ans.pop(); } for (int i = 1; i <= n; i++) printf( %d , b[i]); return 0; } |
/*
* Memory interface for VGA
* Copyright (C) 2010 Zeus Gomez Marmolejo <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga_cpu_mem_iface (
// Wishbone common signals
input wb_clk_i,
input wb_rst_i,
// Wishbone slave interface
input [16:1] wbs_adr_i,
input [ 1:0] wbs_sel_i,
input wbs_we_i,
input [15:0] wbs_dat_i,
output [15:0] wbs_dat_o,
input wbs_stb_i,
output wbs_ack_o,
// Wishbone master to SRAM
output [17:1] wbm_adr_o,
output [ 1:0] wbm_sel_o,
output wbm_we_o,
output [15:0] wbm_dat_o,
input [15:0] wbm_dat_i,
output wbm_stb_o,
input wbm_ack_i,
// VGA configuration registers
input chain_four,
input memory_mapping1,
input [ 1:0] write_mode,
input [ 1:0] raster_op,
input read_mode,
input [ 7:0] bitmask,
input [ 3:0] set_reset,
input [ 3:0] enable_set_reset,
input [ 3:0] map_mask,
input [ 1:0] read_map_select,
input [ 3:0] color_compare,
input [ 3:0] color_dont_care
);
// Registers and nets
wire read_stb;
wire write_stb;
wire rd_wbs_ack_o;
wire [15:0] rd_wbs_dat_o;
wire wr_wbs_ack_o;
wire [17:1] rd_wbm_adr_o;
wire [17:1] wr_wbm_adr_o;
wire rd_wbm_stb_o;
wire wr_wbm_stb_o;
wire rd_wbm_ack_i;
wire [ 1:0] wr_wbm_sel_o;
wire [15:0] wr_wbm_dat_o;
wire wr_wbm_ack_i;
wire [15:0] wbs_dat_o_c;
wire wbs_stb_i_c;
wire wbs_ack_o_c;
wire [17:1] wbm_adr_o_c;
wire [ 1:0] wbm_sel_o_c;
wire wbm_we_o_c;
wire [15:0] wbm_dat_o_c;
wire wbm_stb_o_c;
wire wbm_ack_i_c;
wire [7:0] latch0, latch1, latch2, latch3;
// Module instances
vga_read_iface read_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbs_adr_i (wbs_adr_i),
.wbs_sel_i (wbs_sel_i),
.wbs_dat_o (rd_wbs_dat_o),
.wbs_stb_i (read_stb),
.wbs_ack_o (rd_wbs_ack_o),
.wbm_adr_o (rd_wbm_adr_o),
.wbm_dat_i (wbm_dat_i),
.wbm_stb_o (rd_wbm_stb_o),
.wbm_ack_i (rd_wbm_ack_i),
.memory_mapping1 (memory_mapping1),
.read_mode (read_mode),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care),
.latch0 (latch0),
.latch1 (latch1),
.latch2 (latch2),
.latch3 (latch3)
);
vga_write_iface write_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbs_adr_i (wbs_adr_i),
.wbs_sel_i (wbs_sel_i),
.wbs_dat_i (wbs_dat_i),
.wbs_stb_i (write_stb),
.wbs_ack_o (wr_wbs_ack_o),
.wbm_adr_o (wr_wbm_adr_o),
.wbm_sel_o (wr_wbm_sel_o),
.wbm_dat_o (wr_wbm_dat_o),
.wbm_stb_o (wr_wbm_stb_o),
.wbm_ack_i (wr_wbm_ack_i),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.latch0 (latch0),
.latch1 (latch1),
.latch2 (latch2),
.latch3 (latch3)
);
vga_c4_iface c4_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbs_adr_i (wbs_adr_i),
.wbs_sel_i (wbs_sel_i),
.wbs_we_i (wbs_we_i),
.wbs_dat_i (wbs_dat_i),
.wbs_dat_o (wbs_dat_o_c),
.wbs_stb_i (wbs_stb_i_c),
.wbs_ack_o (wbs_ack_o_c),
.wbm_adr_o (wbm_adr_o_c),
.wbm_sel_o (wbm_sel_o_c),
.wbm_we_o (wbm_we_o_c),
.wbm_dat_o (wbm_dat_o_c),
.wbm_dat_i (wbm_dat_i),
.wbm_stb_o (wbm_stb_o_c),
.wbm_ack_i (wbm_ack_i_c)
);
// Continuous assignments
assign read_stb = wbs_stb_i & !wbs_we_i & !chain_four;
assign write_stb = wbs_stb_i & wbs_we_i & !chain_four;
assign rd_wbm_ack_i = !wbs_we_i & wbm_ack_i & !chain_four;
assign wr_wbm_ack_i = wbs_we_i & wbm_ack_i & !chain_four;
assign wbs_ack_o = chain_four ? wbs_ack_o_c
: (wbs_we_i ? wr_wbs_ack_o : rd_wbs_ack_o);
assign wbs_dat_o = chain_four ? wbs_dat_o_c : rd_wbs_dat_o;
assign wbm_adr_o = chain_four ? wbm_adr_o_c
: (wbs_we_i ? wr_wbm_adr_o : rd_wbm_adr_o);
assign wbm_stb_o = chain_four ? wbm_stb_o_c
: (wbs_we_i ? wr_wbm_stb_o : rd_wbm_stb_o);
assign wbm_sel_o = chain_four ? wbm_sel_o_c : wr_wbm_sel_o;
assign wbm_dat_o = chain_four ? wbm_dat_o_c : wr_wbm_dat_o;
assign wbm_we_o = chain_four & wbm_we_o_c
| !chain_four & wbs_we_i;
assign wbs_stb_i_c = chain_four & wbs_stb_i;
assign wbm_ack_i_c = chain_four & wbm_ack_i;
endmodule
|
/*============================================================================
This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point
Arithmetic Package, Release 1, by John R. Hauser.
Copyright 2019 The Regents of the University of California. All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
`include "HardFloat_consts.vi"
`include "HardFloat_specialize.vi"
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
module test_addRecFN_add#(parameter expWidth = 3, parameter sigWidth = 3);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
parameter maxNumErrors = 20;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
localparam formatWidth = expWidth + sigWidth;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
reg [(`floatControlWidth - 1):0] control;
reg [2:0] roundingMode;
reg [(formatWidth - 1):0] a, b, expectOut;
reg [4:0] expectExceptionFlags;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire [formatWidth:0] recA, recB, recExpectOut;
fNToRecFN#(expWidth, sigWidth) fNToRecFN_a(a, recA);
fNToRecFN#(expWidth, sigWidth) fNToRecFN_b(b, recB);
fNToRecFN#(expWidth, sigWidth)
fNToRecFN_expectOut(expectOut, recExpectOut);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire [formatWidth:0] recOut;
wire [4:0] exceptionFlags;
addRecFN#(expWidth, sigWidth)
addRecFN_add(
control, 1'b0, recA, recB, roundingMode, recOut, exceptionFlags);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire sameOut;
sameRecFN#(expWidth, sigWidth) sameRecFN(recOut, recExpectOut, sameOut);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
integer errorCount, count, partialCount;
initial begin
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
$fwrite('h80000002, "Testing 'addRecF%0d_add'", formatWidth);
if ($fscanf('h80000000, "%h %h", control, roundingMode) < 2) begin
$fdisplay('h80000002, ".\n--> Invalid test-cases input.");
`finish_fail;
end
$fdisplay(
'h80000002,
", control %H, rounding mode %0d:",
control,
roundingMode
);
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
errorCount = 0;
count = 0;
partialCount = 0;
begin :TestLoop
while (
$fscanf(
'h80000000,
"%h %h %h %h",
a,
b,
expectOut,
expectExceptionFlags
) == 4
) begin
#1;
partialCount = partialCount + 1;
if (partialCount == 10000) begin
count = count + 10000;
$fdisplay('h80000002, "%0d...", count);
partialCount = 0;
end
if (
!sameOut || (exceptionFlags !== expectExceptionFlags)
) begin
if (errorCount == 0) begin
$display(
"Errors found in 'addRecF%0d_add', control %H, rounding mode %0d:",
formatWidth,
control,
roundingMode
);
end
$write("%H %H", recA, recB);
if (formatWidth > 64) begin
$write("\n\t");
end else begin
$write(" ");
end
$write("=> %H %H", recOut, exceptionFlags);
if (formatWidth > 32) begin
$write("\n\t");
end else begin
$write(" ");
end
$display(
"expected %H %H", recExpectOut, expectExceptionFlags);
errorCount = errorCount + 1;
if (errorCount == maxNumErrors) disable TestLoop;
end
#1;
end
end
count = count + partialCount;
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
if (errorCount) begin
$fdisplay(
'h80000002,
"--> In %0d tests, %0d errors found.",
count,
errorCount
);
`finish_fail;
end else if (count == 0) begin
$fdisplay('h80000002, "--> Invalid test-cases input.");
`finish_fail;
end else begin
$display(
"In %0d tests, no errors found in 'addRecF%0d_add', control %H, rounding mode %0d.",
count,
formatWidth,
control,
roundingMode
);
end
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
$finish;
end
endmodule
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
module test_addRecF16_add;
test_addRecFN_add#(5, 11) test_addRecF16_add();
endmodule
module test_addRecF32_add;
test_addRecFN_add#(8, 24) test_addRecF32_add();
endmodule
module test_addRecF64_add;
test_addRecFN_add#(11, 53) test_addRecF64_add();
endmodule
module test_addRecF128_add;
test_addRecFN_add#(15, 113) test_addRecF128_add();
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 200010; int main() { int t; cin >> t; while (t--) { int a, b; cin >> a >> b; int s = abs(a - b); int ans = s / 5; s %= 5; if (s > 2) ans += 2; else if (s != 0) ans++; cout << ans << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = (int)1e6 + 5; vector<int> adjList[N]; unordered_set<int> remaining; bitset<N> inQ, nextToQ; vector<int> ans; void solve(int u) { remaining.erase(u); for (auto v : adjList[u]) { remaining.erase(v); } if (!remaining.empty()) { solve(*remaining.begin()); } if (!nextToQ[u]) { inQ[u] = 1; nextToQ[u] = 1; for (auto v : adjList[u]) { nextToQ[v] = 1; } ans.push_back(u); } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, m; cin >> n >> m; for (int i = 0; i < m; i++) { int u, v; cin >> u >> v; adjList[u].push_back(v); } for (int i = 1; i <= n; i++) { remaining.insert(i); } solve(1); cout << ans.size() << endl; for (auto u : ans) { cout << u << ; } cout << endl; } |
#include <bits/stdc++.h> using namespace std; long double EPS = 1e-9; long long cel(long long a, int b) { return ((a - 1) / b + 1); } long long gcd(long long a, long long b) { if (a < b) swap(a, b); return (b == 0) ? a : gcd(b, a % b); } long long lcm(long long a, long long b) { return (a * b) / gcd(a, b); } long long po(long long x, long long y) { long long ans = 1; while (y) { if (y & 1) { ans = (ans * x) % 1000000007; } y >>= 1; x = (x * x) % 1000000007; } return ans; } vector<int> v(3000); long long m = 0, n; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t, x, y, ans = 0; cin >> n; for (int i = 2; i < 1 << (n + 1); i++) cin >> v[i]; for (int i = (1 << n) - 1; i >= 1; i--) { ans += abs(v[i * 2] - v[i * 2 + 1]); v[i] += max(v[i * 2], v[i * 2 + 1]); } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; using lint = long long; using ld = long double; using pint = pair<int, int>; using plint = pair<lint, lint>; lint _pow(lint a, lint n) { if (n == 0) return 1; else { lint res = 1; lint buf = a; while (n > 0) { if (n % 2 == 1) { res *= buf; res %= 998244353LL; } buf *= buf; buf %= 998244353LL; n /= 2; } return res; } } int main() { ios::sync_with_stdio(false); cin.tie(0); int n; cin >> n; vector<int> c(n + 10, 0); for (lint i = 0; i < (int)n; i++) { int a; cin >> a; c[a]++; } lint ans = 0; vector<lint> dp(n + 10, 0); dp[0] = 1; vector<lint> rev(n + 10); for (lint i = 0; i < (int)n + 10; i++) rev[i] = _pow(i, 998244353LL - 2); for (lint i = 0; i < (int)n + 10; i++) { if (c[i] == 0) continue; if (c[i] >= 2) { for (lint j = 0; j < (int)n + 10; j++) { lint p = dp[j]; p *= c[i]; p %= 998244353LL; p *= c[i] - 1; p %= 998244353LL; p *= rev[n - j]; p %= 998244353LL; p *= rev[n - j - 1]; p %= 998244353LL; ans += p; ans %= 998244353LL; } } vector<lint> ndp(n + 10, 0); for (lint j = 0; j < (int)n + 10; j++) ndp[j] += dp[j]; for (lint j = 1; j < (int)n + 10; j++) { lint p = dp[j - 1]; p *= c[i]; p %= 998244353LL; p *= rev[n - j + 1]; p %= 998244353LL; ndp[j] += p; ndp[j] %= 998244353LL; } dp = ndp; } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> const int Maxn = 100000; const int Maxv = 100000; int n; struct Node { int x, y; Node(int _x = 0, int _y = 0) { x = _x, y = _y; } friend Node operator+(Node a, Node b) { return Node(a.x + b.x, a.y + b.y); } friend Node operator-(Node a, Node b) { return Node(a.x - b.x, a.y - b.y); } friend long long operator/(Node a, Node b) { return 1ll * a.x * b.y - 1ll * a.y * b.x; } long long find_len() { return 1ll * x * x + 1ll * y * y; } } a[Maxn * 6 + 5]; Node S; bool cmp_1_less(Node a, Node b) { if (a.x == b.x) { return a.y < b.y; } return a.x < b.x; } bool cmp_1_equal(Node a, Node b) { return a.x == b.x && a.y == b.y; } bool cmp_2(Node a, Node b) { if ((a - S) / (b - S) == 0) { return (a - S).find_len() < (b - S).find_len(); } return (a - S) / (b - S) > 0; } int len; int st[Maxn * 6 + 5], st_top; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { int x, y, v; scanf( %d%d%d , &x, &y, &v); if (x < v) { a[++len] = Node(0, std::max(y - v + x, 0)); a[++len] = Node(0, std::min(y + v - x, Maxv)); } else { a[++len] = Node(x - v, y); } if (x + v > Maxv) { a[++len] = Node(Maxv, std::max(y - v + (Maxv - x), 0)); a[++len] = Node(Maxv, std::min(y + v - (Maxv - x), Maxv)); } else { a[++len] = Node(x + v, y); } if (y < v) { a[++len] = Node(std::max(x - v + y, 0), 0); a[++len] = Node(std::min(x + v - y, Maxv), 0); } else { a[++len] = Node(x, y - v); } if (y + v > Maxv) { a[++len] = Node(std::max(x - v + (Maxv - y), 0), Maxv); a[++len] = Node(std::min(x + v - (Maxv - y), Maxv), Maxv); } else { a[++len] = Node(x, y + v); } } std::sort(a + 1, a + 1 + len, cmp_1_less); len = std::unique(a + 1, a + 1 + len, cmp_1_equal) - a - 1; S = a[1]; std::sort(a + 2, a + 1 + len, cmp_2); st[++st_top] = 1; for (int i = 2; i <= len; i++) { while (st_top > 1 && (a[i] - a[st[st_top]]) / (a[st[st_top]] - a[st[st_top - 1]]) >= 0) { st_top--; } st[++st_top] = i; } st[0] = st[st_top], st[st_top + 1] = st[1]; int pos = -1; double ans = 0; for (int i = 1; i <= st_top; i++) { Node e_a = a[st[i]] - a[st[i - 1]], e_b = a[st[i + 1]] - a[st[i]], e_c = a[st[i + 1]] - a[st[i - 1]]; double tmp = sqrt(e_a.find_len()) * sqrt(e_b.find_len()) * sqrt(e_c.find_len()) / (std::abs(e_a / e_b)); if (tmp > ans) { pos = i; ans = tmp; } } printf( %d %d n , a[st[pos - 1]].x, a[st[pos - 1]].y); printf( %d %d n , a[st[pos]].x, a[st[pos]].y); printf( %d %d n , a[st[pos + 1]].x, a[st[pos + 1]].y); return 0; } |
#include <bits/stdc++.h> const int maxn = 100010, mod = 998244353; int n, fac[maxn], ifac[maxn]; long long pw(long long a, int n = mod - 2) { long long b = 1; for (; n; n >>= 1) n& 1 ? b = b * a % mod : 1, a = a * a % mod; return b; } struct edge { int to; edge* next; } E[maxn * 2], *ne = E, *fir[maxn]; void link(int u, int v) { *ne = (edge){v, fir[u]}; fir[u] = ne++; } int fa[maxn], siz[maxn], son[maxn]; void init(int i) { siz[i] = 1; for (edge* e = fir[i]; e; e = e->next) if (e->to != fa[i]) { fa[e->to] = i; init(e->to); if (siz[e->to] > siz[son[i]]) son[i] = e->to; siz[i] += siz[e->to]; } } int cs[maxn]; std::vector<int> ps[maxn], f[maxn]; bool cmp(int i, int j) { return siz[i] < siz[j]; } std::vector<int> add(std::vector<int> a, std::vector<int> b) { std::vector<int> c; for (int i = 0; i < a.size() || i < b.size(); i++) c.push_back(((i < a.size() ? a[i] : 0) + (i < b.size() ? b[i] : 0)) % mod); return c; } int ws[1 << 17]; void dft(int* a, int n, bool r = 0) { int* w = ws + n / 2; w[0] = 1; w[1] = pw(3, (mod - 1) / n); if (r) w[1] = pw(w[1]); for (int i = 2; i < n / 2; i++) w[i] = 1ll * w[1] * w[i - 1] % mod; for (int i = n / 2; --i;) ws[i] = ws[i * 2]; w = ws + 1; for (int i = 0, j = 0, t; i < n; i++) { if (i < j) t = a[i], a[i] = a[j], a[j] = t; for (t = n / 2; (j ^= t) < t; t /= 2) ; } for (int i = 1; i < n; w += i, i *= 2) { for (int j = 0; j < n; j += i * 2) { for (int k = 0, t; k < i; k++) { t = 1ll * a[i + j + k] * w[k] % mod; a[i + j + k] = (a[j + k] + mod - t) % mod; a[j + k] = (a[j + k] + t) % mod; } } } if (r) { long long I = pw(n); for (int i = 0; i < n; i++) a[i] = a[i] * I % mod; } } int A[1 << 17], B[1 << 17]; std::vector<int> mul(std::vector<int> a, std::vector<int> b) { int n = a.size() - 1, m = b.size() - 1, N = 1; while (N <= n + m) N *= 2; for (int i = 0; i < N; i++) A[i] = i > n ? 0 : a[i], B[i] = i > m ? 0 : b[i]; dft(A, N); dft(B, N); for (int i = 0; i < N; i++) A[i] = 1ll * A[i] * B[i] % mod; dft(A, N, 1); std::vector<int> c; for (int i = 0; i <= n + m; i++) c.push_back(A[i]); return c; } std::pair<std::vector<int>, std::vector<int> > calc( std::vector<std::vector<int> >& a, int l, int r) { if (r - l == 1) return std::make_pair(a[l], a[l]); int pl = l, pr = r, sl = 0, sr = 0; while (pl < pr) sl < sr ? sl += a[pl++].size() - 1 : sr += a[--pr].size() - 1; std::pair<std::vector<int>, std::vector<int> > fl = calc(a, l, pl), fr = calc(a, pl, r); return std::make_pair(mul(fl.first, fr.first), add(fl.second, mul(fl.first, fr.second))); } void dc(int i) { for (int o = i; o; o = son[o]) for (edge* e = fir[o]; e; e = e->next) if (e->to != fa[o] && e->to != son[o]) dc(e->to); std::vector<std::vector<int> > a; for (int o = i; o; o = son[o]) { int *cl = cs, *cr = cs; std::vector<int>*pl = ps, *pr = ps; for (edge* e = fir[o]; e; e = e->next) if (e->to != fa[o] && e->to != son[o]) *cr++ = e->to; std::sort(cs, cr, cmp); for (int t = cr - cs; --t > 0;) { std::vector<int>* p[2]; for (int j = 0; j < 2; j++) { if (pl == pr || cl < cr && siz[*cl] < pl->size()) p[j] = f + *cl++; else p[j] = pl++; } *pr++ = mul(*p[0], *p[1]); } std::vector<int>&g = cl < cr ? f[*cl] : *pl, h; h.push_back(0); if (cl == cr && pl == pr) h.push_back(1); else for (int j = 0; j < g.size(); j++) h.push_back(g[j]); a.push_back(h); } f[i] = calc(a, 0, a.size()).second; f[i][0] = 1; } int main() { long long x; scanf( %d%lld , &n, &x); x %= mod; for (int i = 1, u, v; i < n; i++) scanf( %d%d , &u, &v), link(u, v), link(v, u); for (int i = *fac = 1; i <= n; i++) fac[i] = 1ll * fac[i - 1] * i % mod; ifac[n] = pw(fac[n]); for (int i = n; i; i--) ifac[i - 1] = 1ll * ifac[i] * i % mod; init(1); dc(1); int s = 0; for (int i = 1, w = 1; i <= n; i++) s = (s + 1ll * w * ifac[i - 1] % mod * f[1][i]) % mod, w = w * (x + i) % mod; printf( %d n , s); } |
#include <bits/stdc++.h> using namespace std; const int mod = 998244353; const int inf = 1 << 30; const int maxn = 100000 + 5; int tot, dfn[maxn << 1], ord[maxn << 1]; namespace hld { const int maxn = ::maxn << 1; struct edge { int to, nxt; } g[maxn]; int head[maxn], ecnt = 0; void add(int x, int y) { g[++ecnt] = {y, head[x]}; head[x] = ecnt; } int siz[maxn], dep[maxn], fa[maxn], son[maxn], top[maxn]; void dfs(int p, int d, int old) { dfn[p] = ++tot; ord[tot] = p; dep[p] = d; fa[p] = old; siz[p] = 1; int m = -1; for (int i = head[p]; i; i = g[i].nxt) { int v = g[i].to; if (v == fa[p]) continue; dfs(v, d + 1, p); siz[p] += siz[v]; if (siz[v] > m) son[p] = v, m = siz[v]; } } void dfs(int p, int tp) { top[p] = tp; if (!son[p]) return; dfs(son[p], tp); for (int i = head[p]; i; i = g[i].nxt) { int v = g[i].to; if (v == fa[p] || v == son[p]) continue; dfs(v, v); } } void build(int rt = 1) { memset(son, 0, sizeof(son)); dfs(rt, rt, 0); dfs(rt, rt); } int qlca(int x, int y) { while (top[x] != top[y]) { if (dep[top[x]] < dep[top[y]]) swap(x, y); x = fa[top[x]]; } if (dep[x] > dep[y]) swap(x, y); return x; } } // namespace hld vector<int> edge[maxn << 1]; struct sam { int sz, last, cnt[maxn << 1]; int len[maxn << 1], link[maxn << 1], ch[maxn << 1][26]; void clear() { for (int i = 1; i <= sz; i++) { len[i] = link[i] = cnt[i] = 0; memset(ch[i], 0, sizeof(ch[i])); } sz = last = 1; } sam() { clear(); } int insert(int c) { int cur = ++sz, p = last; len[cur] = len[last] + 1; cnt[cur] = 1; for (; p && !ch[p][c]; p = link[p]) ch[p][c] = cur; if (!p) link[cur] = 1; else { int q = ch[p][c]; if (len[p] + 1 == len[q]) link[cur] = q; else { int nq = ++sz; len[nq] = len[p] + 1; link[nq] = link[q]; link[q] = link[cur] = nq; memcpy(ch[nq], ch[q], sizeof ch[q]); for (; ch[p][c] == q; p = link[p]) ch[p][c] = nq; } } return last = cur; } void build(int tp) { if (tp == 0) { for (int i = 1; i <= sz; i++) { len[i]++; edge[link[i]].push_back(i); } } else { for (int i = 1; i <= sz; i++) { len[i]++; hld::add(link[i], i); } hld::build(); } } } ta, tb; int n; long long ans; char s[maxn]; int prepos[maxn], sufpos[maxn]; set<int> bag[maxn << 1]; long long val[maxn << 1]; void add(int u, int p) { auto it = bag[u].lower_bound(p); int node = -1, d = hld::dep[ord[p]]; if (it != bag[u].end()) { node = hld::qlca(ord[p], ord[*it]); } if (it != bag[u].begin()) { it--; int y = hld::qlca(ord[p], ord[*it]); if (node == -1 || abs(hld::dep[node] - d) > abs(hld::dep[y] - d)) node = y; } val[u] += tb.len[ord[p]]; if (node != -1) val[u] -= tb.len[node]; bag[u].insert(p); } void dfs(int u) { for (int v : edge[u]) { dfs(v); if (bag[v].size() > bag[u].size()) { swap(bag[u], bag[v]); val[u] = val[v]; } for (auto& x : bag[v]) add(u, x); } ans += (val[u] + 1) * (ta.len[u] - ta.len[ta.link[u]]); ; } int main() { scanf( %s , s + 1); n = strlen(s + 1); prepos[0] = sufpos[n + 1] = 1; for (int i = 1; i <= n; i++) { prepos[i] = ta.insert(s[i] - a ); } for (int i = n; i >= 1; i--) { sufpos[i] = tb.insert(s[i] - a ); } ta.build(0); tb.build(1); for (int i = 0; i < n; i++) { add(prepos[i], dfn[sufpos[i + 2]]); } dfs(1); cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, q; int kek[20]; long long a[696969]; void upd(int x, int v, int s = 0, int e = (1 << n) - 1, int d = n - 1, int p = 1) { if (s == e) { a[p] = v; return; } int m = (s + e) / 2; if (x <= m) { upd(x, v, s, m, d - 1, 2 * p + kek[d]); } else { upd(x, v, m + 1, e, d - 1, 2 * p + 1 - kek[d]); } a[p] = a[2 * p] + a[2 * p + 1]; } long long query(int s, int e, int ps = 0, int pe = (1 << n) - 1, int d = n - 1, int p = 1) { if (e < ps || pe < s) return 0; if (s <= ps && pe <= e) return a[p]; int pm = (ps + pe) / 2; return query(s, e, ps, pm, d - 1, 2 * p + kek[d]) + query(s, e, pm + 1, pe, d - 1, 2 * p + 1 - kek[d]); } int main() { scanf( %d %d , &n, &q); for (int i = 0; i < (1 << n); i++) { int x; scanf( %d , &x); upd(i, x); } while (q--) { int t; scanf( %d , &t); if (t == 1) { int x, v; scanf( %d %d , &x, &v); x--; upd(x, v); } if (t == 4) { int s, e; scanf( %d %d , &s, &e); printf( %lld n , query(s - 1, e - 1)); } if (t == 2) { int x; scanf( %d , &x); for (int i = 0; i < x; i++) kek[i] ^= 1; } if (t == 3) { int x; scanf( %d , &x); kek[x] ^= 1; } } } |
module image_to_ppfifo #(
parameter BUFFER_SIZE = 10
)(
input clk,
input rst,
input i_enable,
input i_hsync, // vga hsync signal
input i_vsync, // vga vsync signal
input [2:0] i_red, // vga red signal
input [2:0] i_green, // vga green signal
input [1:0] i_blue, // vga blue signal
output reg o_frame_finished,
//Memory FIFO Interface
output o_rfifo_ready,
input i_rfifo_activate,
input i_rfifo_strobe,
output [31:0] o_rfifo_data,
output [23:0] o_rfifo_size
);
//Local Parameters
localparam IDLE = 4'h0;
localparam PROCESS_IMAGE = 4'h1;
//Registers/Wires
reg r_prev_vsync;
wire w_neg_edge_vsync;
//ppfifo interface
wire [1:0] w_write_ready;
reg [1:0] r_write_activate;
wire [23:0] w_write_fifo_size;
reg r_write_strobe;
reg [23:0] r_write_count;
reg [31:0] r_write_data;
//Submodules
ppfifo p2m
#(
.DATA_WIDTH (32 ),
.ADDRESS_WIDTH (BUFFER_SIZE )
)fifo (
//universal input
.reset (rst ),
//write side
.write_clock (clk ),
.write_ready (w_write_ready ),
.write_activate (r_write_activate ),
.write_fifo_size (w_write_fifo_size ),
.write_strobe (r_write_strobe ),
.write_data (r_write_data ),
// .inactive (w_inactive ),
//read side
.read_clock (clk ),
.read_strobe (i_rfifo_strobe ),
.read_ready (o_rfifo_ready ),
.read_activate (i_rfifo_activate ),
.read_count (o_rfifo_size ),
.read_data (o_rfifo_data )
);
//Asynchronous Logic
assign w_neg_edge_vsync = (r_prev_vsync & !i_vsync);
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
r_write_activate <= 0;
r_write_strobe <= 0;
r_write_count <= 0;
r_write_data <= 0;
o_frame_finished <= 0;
r_prev_vsync <= 0;
end
else begin
o_frame_finished <= 0;
r_write_strobe <= 0;
if (i_enable && (r_write_activate == 0) && (w_write_ready > 0)) begin
r_write_count <= 0;
if (w_write_ready[0]) begin
r_write_activate[0] <= 1;
end
else begin
r_write_activate[1] <= 1;
end
end
if (i_enable && (r_write_activate > 0)) begin
if (i_hsync) begin
r_write_data <= {24'h000000, i_red, i_green, i_blue};
r_write_strobe <= 1;
r_write_count <= r_write_count + 1;
if (r_write_count >= w_write_fifo_size - 1) begin
r_write_activate <= 0;
end
end
else if (!i_hsync) begin
r_write_activate <= 0;
end
if (w_neg_edge_vsync) begin
o_frame_finished <= 1;
end
end
r_prev_vsync <= i_vsync;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLRBP_BEHAVIORAL_V
`define SKY130_FD_SC_LS__DLRBP_BEHAVIORAL_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dlrbp (
Q ,
Q_N ,
RESET_B,
D ,
GATE
);
// Module ports
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire RESET ;
reg notifier ;
wire D_delayed ;
wire GATE_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire buf_Q ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_ls__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLRBP_BEHAVIORAL_V |
Subsets and Splits