text
stringlengths 59
71.4k
|
|---|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR2B_BEHAVIORAL_V
`define SKY130_FD_SC_LS__NOR2B_BEHAVIORAL_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__nor2b (
Y ,
A ,
B_N
);
// Module ports
output Y ;
input A ;
input B_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire and0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A );
and and0 (and0_out_Y, not0_out, B_N );
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR2B_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; template <typename T> T gcd(T x, T y) { if (x < y) swap(x, y); while (y > 0) { T f = x % y; x = y; y = f; } return x; } struct Node { Node *l, *r; long long a, b; Node() : l(NULL), r(NULL), a(0), b(0) {} }; Node* makeTree(int fr, int to) { Node* node = new Node(); if (fr == to) return node; int m = (fr + to) / 2; node->l = makeTree(fr, m); node->r = makeTree(m + 1, to); return node; } Node* update(Node* _node, int fr, int to, int x1, int x2, long long a, long long b) { if (x2 < fr || x1 > to) return _node; Node* node = new Node(); *node = *_node; if (x1 <= fr && to <= x2) { node->a += a; node->b += b; return node; } int m = (fr + to) / 2; node->l = update(node->l, fr, m, x1, x2, a, b); node->r = update(node->r, m + 1, to, x1, x2, a, b); return node; } long long query(Node* node, int fr, int to, long long x) { long long res = node->a * x + node->b; if (fr == to) return res; int m = (fr + to) / 2; if (x <= m) return res + query(node->l, fr, m, x); else return res + query(node->r, m + 1, to, x); } Node* froot[75007]; const int maxx = 200002; int main(int argc, char* argv[]) { int n; std::cin.sync_with_stdio(false); std::cin.tie(nullptr); cin >> n; { froot[0] = makeTree(0, maxx); for (int i = 1; i <= n; i++) { int x1, x2, y1, a, b, y2; cin >> x1 >> x2 >> y1 >> a >> b >> y2; froot[i] = update(froot[i - 1], 0, maxx, 0, x1, 0, y1); froot[i] = update(froot[i], 0, maxx, x1 + 1, x2, a, b); froot[i] = update(froot[i], 0, maxx, x2 + 1, maxx, 0, y2); } int m; cin >> m; long long last = 0; while (m--) { int l, r, x; cin >> l >> r >> x; last = (last + x) % 1000000000ll; last = query(froot[r], 0, maxx, last) - query(froot[l - 1], 0, maxx, last); cout << last << endl; } } return 0; } |
// -------------------------------------------------------------
//
// File Name: hdlsrc\qpsk\Raised_Cosine_Receive_Filter.v
// Created: 2014-10-24 12:50:39
//
// Generated by MATLAB 8.3 and HDL Coder 3.4
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: Raised_Cosine_Receive_Filter
// Source Path: qpsk/Subsystem/Raised Cosine Receive Filter
// Hierarchy Level: 1
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module Raised_Cosine_Receive_Filter
(
clk,
reset,
enb_1_1_1,
In1_re,
In1_im,
Out1_re,
Out1_im
);
input clk;
input reset;
input enb_1_1_1;
input signed [15:0] In1_re; // sfix16_En15
input signed [15:0] In1_im; // sfix16_En15
output signed [15:0] Out1_re; // sfix16_En15
output signed [15:0] Out1_im; // sfix16_En15
wire signed [15:0] FIR_Decimation_out1_re; // sfix16_En15
wire signed [15:0] FIR_Decimation_out1_im; // sfix16_En15
FIR_Decimation u_FIR_Decimation (.clk(clk),
.enb_1_1_1(enb_1_1_1),
.reset(reset),
.FIR_Decimation_in_re(In1_re), // sfix16_En15
.FIR_Decimation_in_im(In1_im), // sfix16_En15
.FIR_Decimation_out_re(FIR_Decimation_out1_re), // sfix16_En15
.FIR_Decimation_out_im(FIR_Decimation_out1_im) // sfix16_En15
);
assign Out1_re = FIR_Decimation_out1_re;
assign Out1_im = FIR_Decimation_out1_im;
endmodule // Raised_Cosine_Receive_Filter
|
#include <bits/stdc++.h> using namespace std; inline int read() { int x = 0, f = 1; char ch = getchar(); while (!(ch >= 0 && ch <= 9 )) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + (ch - 0 ); ch = getchar(); } return x * f; } struct edge { int next, to; } e[900500]; vector<int> v[900500]; int cnt, head[900500], size[900500], col[900500]; bool used[900500], vis[900500]; inline void ins(int u, int v) { e[++cnt].to = v; e[cnt].next = head[u]; head[u] = cnt; } inline void insert(int u, int v) { ins(u, v); ins(v, u); } void dfs(int x) { int j = 1; vis[x] = 1; for (int i = 0; i < size[x]; i++) used[col[v[x][i]]] = 1; for (int i = 0; i < size[x]; i++) if (!col[v[x][i]]) { for (; used[j]; j++) ; used[col[v[x][i]] = j] = 1; } for (int i = 0; i < size[x]; i++) used[col[v[x][i]]] = 0; for (int i = head[x]; i; i = e[i].next) if (!vis[e[i].to]) dfs(e[i].to); } int main() { int n = read(), m = read(), ans = 0; for (int i = 1; i <= n; i++) { size[i] = read(); for (int j = 1; j <= size[i]; j++) v[i].push_back(read()); ans = max(ans, size[i]); } for (int i = 1; i < n; i++) insert(read(), read()); printf( %d n , ans ? ans : 1); dfs(1); for (int i = 1; i <= m; i++) printf( %d , col[i] ? col[i] : 1); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long INF = 1e15; long long binpow(long long a, long long b) { long long res = 1; while (b > 0) { if (b & 1) { res = res * a; } a = a * a; b >>= 1; } return res; } long long dp[205][205][205]; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long T; T = 1; while (T--) { long long n, k; string s, t; cin >> n >> k; cin >> s >> t; memset(dp, -1, sizeof(dp)); dp[0][0][0] = 0; long long i, j; for (i = 0; i < n; i++) { for (j = 0; j <= k; j++) { for (long long f0 = 0; f0 <= n; f0++) { if (dp[i][j][f0] == -1) { continue; } long long e0 = s[i] == t[0]; long long e1 = s[i] == t[1]; long long e01 = t[0] == t[1]; dp[i + 1][j][f0 + e0] = max(dp[i + 1][j][f0 + e0], dp[i][j][f0] + (e1 ? f0 : 0)); if (j + 1 <= k) dp[i + 1][j + 1][f0 + 1] = max(dp[i + 1][j + 1][f0 + 1], dp[i][j][f0] + (e01 ? f0 : 0)); if (j + 1 <= k) dp[i + 1][j + 1][f0 + e01] = max(dp[i + 1][j + 1][f0 + e01], dp[i][j][f0] + f0); } } } long long ans = 0; for (j = 0; j <= k; j++) { for (long long f0 = 0; f0 <= n; f0++) { ans = max(ans, dp[n][j][f0]); } } cout << ans << n ; } } |
#include <bits/stdc++.h> const int maxn = 5e5 + 5; using namespace std; char s[maxn]; int main() { scanf( %s , s); int k = strlen(s); char y = s[0]; for (int i = 0; i < k; i++) { if (s[i] > y) { cout << Ann << endl; } else { y = s[i]; cout << Mike << endl; } } return 0; } |
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 06/29/2009
This block is used to breakout the 256 bit streaming ports to and from the write master.
The information sent through the streaming ports is a bundle of wires and buses so it's
fairly inconvenient to constantly refer to them by their position amungst the 256 lines.
This block also provides a layer of abstraction since the descriptor buffers block has
no clue what format the descriptors are in except that the 'go' bit is written to. This
means that using this block you could move descriptor information around without affecting
the top level dispatcher logic.
1.0 06/29/2009 - First version of this block of wires
1.1 02/15/2011 - Added read_early_done_enable to the wire breakout
1.2 11/15/2012 - Added in an additional 32 bits of address for extended descriptors
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module read_signal_breakout (
read_command_data_in, // descriptor from the read FIFO
read_command_data_out, // reformated descriptor to the read master
// breakout of command information
read_address,
read_length,
read_transmit_channel,
read_generate_sop,
read_generate_eop,
read_park,
read_transfer_complete_IRQ_mask,
read_burst_count, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
read_stride, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
read_sequence_number, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
read_transmit_error,
read_early_done_enable,
// additional control information that needs to go out asynchronously with the command data
read_stop,
read_sw_reset
);
parameter DATA_WIDTH = 256; // 256 bits when enhanced settings are enabled otherwise 128 bits
input [DATA_WIDTH-1:0] read_command_data_in;
output wire [255:0] read_command_data_out;
output wire [63:0] read_address;
output wire [31:0] read_length;
output wire [7:0] read_transmit_channel;
output wire read_generate_sop;
output wire read_generate_eop;
output wire read_park;
output wire read_transfer_complete_IRQ_mask;
output wire [7:0] read_burst_count;
output wire [15:0] read_stride;
output wire [15:0] read_sequence_number;
output wire [7:0] read_transmit_error;
output wire read_early_done_enable;
input read_stop;
input read_sw_reset;
assign read_address[31:0] = read_command_data_in[31:0];
assign read_length = read_command_data_in[95:64];
generate
if (DATA_WIDTH == 256)
begin
assign read_early_done_enable = read_command_data_in[248];
assign read_transmit_error = read_command_data_in[247:240];
assign read_transmit_channel = read_command_data_in[231:224];
assign read_generate_sop = read_command_data_in[232];
assign read_generate_eop = read_command_data_in[233];
assign read_park = read_command_data_in[234];
assign read_transfer_complete_IRQ_mask = read_command_data_in[238];
assign read_burst_count = read_command_data_in[119:112];
assign read_stride = read_command_data_in[143:128];
assign read_sequence_number = read_command_data_in[111:96];
assign read_address[63:32] = read_command_data_in[191:160];
end
else
begin
assign read_early_done_enable = read_command_data_in[120];
assign read_transmit_error = read_command_data_in[119:112];
assign read_transmit_channel = read_command_data_in[103:96];
assign read_generate_sop = read_command_data_in[104];
assign read_generate_eop = read_command_data_in[105];
assign read_park = read_command_data_in[106];
assign read_transfer_complete_IRQ_mask = read_command_data_in[110];
assign read_burst_count = 8'h00;
assign read_stride = 16'h0000;
assign read_sequence_number = 16'h0000;
assign read_address[63:32] = 32'h00000000;
end
endgenerate
// big concat statement to glue all the signals back together to go out to the read master (MSBs to LSBs)
assign read_command_data_out = {{115{1'b0}}, // zero pad the upper 115 bits
read_address[63:32],
read_early_done_enable,
read_transmit_error,
read_stride,
read_burst_count,
read_sw_reset,
read_stop,
read_generate_eop,
read_generate_sop,
read_transmit_channel,
read_length,
read_address[31:0]};
endmodule
|
#include <bits/stdc++.h> using namespace std; struct lichao { int l, r, A; long long B; lichao() : l(0), r(0), A(0), B(0x7fffffffffffffffLL) {} }; const int SZ = 1 << 17; vector<int> adj[100000]; vector<lichao> tree(2 * SZ); int node_cnt, num[100000], A[100000], B[100000]; long long ans[100000]; int get_sign(long long a) { return a < 0 ? -1 : a > 0; } void add_tree2(int A, long long B, int p, int s = -SZ, int e = SZ - 1) { int m = (s + e) >> 1, &pA = tree[p].A; long long &pB = tree[p].B; long long ys = 1LL * A * s + B, ym = 1LL * A * m + B, ye = 1LL * A * e + B, pys = 1LL * pA * s + pB, pym = 1LL * pA * m + pB, pye = 1LL * pA * e + pB; if (ym < pym) { swap(A, pA); swap(B, pB); swap(ys, pys); swap(ym, pym); swap(ye, pye); } if (ys >= pys && ye >= pye) return; if (get_sign(ys - pys) * get_sign(ym - pym) < 0 || ym == pym && ys < pys) { if (tree[p].l == 0) tree[p].l = tree.size(), tree.push_back(lichao()); add_tree2(A, B, tree[p].l, s, m); } else { if (tree[p].r == 0) tree[p].r = tree.size(), tree.push_back(lichao()); add_tree2(A, B, tree[p].r, m + 1, e); } } void add_tree(int n, int A, long long B) { for (add_tree2(A, B, n += SZ); n >>= 1;) add_tree2(A, B, n); } long long get_min2(int x, int p, int s = -SZ, int e = SZ - 1) { int m = (s + e) >> 1; if (p == 0 || s == e) return 1LL * tree[p].A * x + tree[p].B; return min( 1LL * tree[p].A * x + tree[p].B, x <= m ? get_min2(x, tree[p].l, s, m) : get_min2(x, tree[p].r, m + 1, e)); } long long get_min(int s, int e, int x) { long long ret = 0x7fffffffffffffffLL; for (s |= SZ, e |= SZ; s <= e; s >>= 1, e >>= 1) { if (s & 1) ret = min(ret, get_min2(x, s++)); if (~e & 1) ret = min(ret, get_min2(x, e--)); } return ret; } void dfs(int c) { bool leaf = true; num[c] = ++node_cnt; for (auto n : adj[c]) if (num[n] == 0) { leaf = false; dfs(n); } ans[c] = (leaf ? 0 : get_min(num[c], node_cnt, A[c])); add_tree(num[c], B[c], ans[c]); } int main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ((void)0); ((void)0); ((void)0); int N; cin >> N; for (int i = 0; i < N; i++) cin >> A[i]; for (int i = 0; i < N; i++) cin >> B[i]; for (int i = 1; i < N; i++) { int a, b; cin >> a >> b; adj[--a].push_back(--b); adj[b].push_back(a); } dfs(0); for (int i = 0; i < N; i++) cout << ans[i] << ; return 0; } |
#include <bits/stdc++.h> using namespace std; long long MOD = 1000000007; int d[201][201]; pair<pair<int, int>, int> E[20000]; vector<std::pair<int, int> > Intervals; int n, m; bool check(int idx, int x) { int u = E[idx].first.first, v = E[idx].first.second, w = E[idx].second; Intervals.clear(); for (int i = 0; i < n; ++i) { int d1 = d[u][i], d2 = d[v][i]; if (d1 > x and d2 > x) return 0; int a = 0, b = w; a = min(w, x - d1) + 1; b = max(0, w - (x - d2)) - 1; if (d1 <= x and d2 <= x) { if (a > b) continue; else Intervals.push_back(std::make_pair(a, b)); } else if (d1 <= x) { if (a <= w) Intervals.push_back(std::make_pair(a, w)); } else { if (b >= 0) Intervals.push_back(std::make_pair(0, b)); } } if (Intervals.size() < 1) return 1; sort(Intervals.begin(), Intervals.end()); if (Intervals[0].first > 0) return 1; int maxY = Intervals[0].second; for (int i = 1; i < Intervals.size(); ++i) { if (Intervals[i].first > maxY) return 1; maxY = max(maxY, Intervals[i].second); } return maxY < w; } int solve(int idx) { int u = E[idx].first.first, v = E[idx].first.second; int l = 0, r = 0, m; for (int i = 0; i < n; ++i) { r = max(r, min(d[u][i], d[v][i])); } r += E[idx].second + 10; while (r - l > 1) { m = (l + r) >> 1; bool f = check(idx, m); if (f) r = m; else l = m; } if (check(idx, l)) return l; else return r; } int main() { int u, v, w; scanf( %d %d , &n, &m); for (int i = 0; i < (n); ++i) for (int j = 0; j < (n); ++j) d[i][j] = (i == j ? 0 : MOD); for (int i = 0; i < (m); ++i) { scanf( %d %d %d , &u, &v, &w); u -= 1, v -= 1, w <<= 1; d[u][v] = d[v][u] = w; E[i] = std::make_pair(std::make_pair(u, v), w); } for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) for (int k = 0; k < n; ++k) { d[j][k] = min(d[j][k], d[j][i] + d[i][k]); } } int ans = MOD; for (int i = 0; i < (m); ++i) ans = min(ans, solve(i)); cout << ans / 2.0 << endl; return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:29:10 04/17/2008
// Design Name:
// Module Name: DelayElement
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module pdl_block(i,o,t);
(* KEEP = "TRUE" *) (* S = "TRUE" *) input i;
(* KEEP = "TRUE" *) (* S = "TRUE" *) input t;
(* KEEP = "TRUE" *) (* S = "TRUE" *) output o;
(* KEEP = "TRUE" *) (* S = "TRUE" *) wire w;
(* KEEP = "TRUE" *) (* S = "TRUE" *) wire t;
(* BEL ="D6LUT" *) //(* LOCK_PINS = "all" *)
LUT6 #(
.INIT(64'h5655555555555555) // Specify LUT Contents
) LUT6_inst_1 (
.O(w), // LUT general output
.I0(i), // LUT input
.I1(t), // LUT input
.I2(t), // LUT input
.I3(t), // LUT input
.I4(t), // LUT input
.I5(t) // LUT input
);
// End of LUT6_inst instantiation
(* BEL ="D6LUT" *) //(* LOCK_PINS = "all" *)
LUT6 #(
.INIT(64'h5655555555555555) // Specify LUT Contents
) LUT6_inst_0 (
.O(o), // LUT general output
.I0(w), // LUT input
.I1(t), // LUT input
.I2(t), // LUT input
.I3(t), // LUT input
.I4(t), // LUT input
.I5(t) // LUT input
);
// End of LUT6_inst instantiation
endmodule |
//////////////////////////////////////////////////////////////////////////
// Department of Computer Science
// National Tsing Hua University
// Project : FIFO for CS4125 Digital System Design
// Module : fifo.v
// Author : Chih-Tsun Huang
// E-mail :
// Revision : 4
// Date : 2014/04/28
// Abstract :
// The top module of FIFO consists of FIFO controller and the RAM module.
// Note :
// 1. The purpose of this version is to provide a design style. It is
// not a complete module. Please fix any *unexpected feature* by
// yourself if any.
// 2. Feel free to rewrite this file header to your own.
//
module fifo (
input clk,
input rst_n,
input push,
input pop,
input [7:0] datain,
output empty,
output almost_empty,
output full,
output almost_full,
output error,
output [7:0] dataout
);
wire [4:0] addr;
wire cen;
wire oen;
wire wen;
wire [7:0] data_to_ram;
fifo_ctr controller (
.clk(clk),
.rst_n(rst_n),
.push(push),
.pop(pop),
.empty(empty),
.almost_empty(almost_empty),
.full(full),
.almost_full(almost_full),
.error(error),
.cen(cen),
.wen(wen),
.oen(oen),
.addr(addr)
);
// LAB NOTE:
// You should include the memory simulation model by your own
RAM32x8 ram (
.Q(dataout),
.CLK(clk),
.CEN(cen),
.WEN(wen),
.A(addr),
.D(datain),
.OEN(oen)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:58:11 07/01/2012
// Design Name:
// Module Name: Device_led
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module GPIO(input clk, //ʱÖÓ
input rst, //¸´Î»
input Start, //´®ÐÐɨÃèÆô¶¯
input EN, //PIO/LEDÏÔʾˢÐÂʹÄÜ
input [31:0] P_Data, //²¢ÐÐÊäÈ룬ÓÃÓÚ´®ÐÐÊä³öÊý¾Ý
output reg[1:0] counter_set, //ÓÃÓÚ¼ÆÊý/¶¨Ê±Ä£¿é¿ØÖÆ£¬±¾ÊµÑé²»ÓÃ
output [15:0] LED_out, //²¢ÐÐÊä³öÊý¾Ý
output wire ledclk, //´®ÐÐÒÆλʱÖÓ
output wire ledsout, //´®ÐÐÊä³ö
output wire ledclrn, //LEDÏÔʾÇåÁã
output wire LEDEN, //LEDÏÔʾˢÐÂʹÄÜ
output reg[13:0] GPIOf0 //´ýÓãºGPIO
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXQ = 2e5; vector<int> solve(int K, vector<tuple<uint32_t, uint32_t, int> > V) { uint32_t mask = (((uint32_t)1) << K) - 1; vector<int> HT(1 << K), LT(1 << K); for (auto [l, r, v] : V) if (v) { uint32_t lhi = l >> K, llo = l & mask; uint32_t rhi = r >> K, rlo = r & mask; if (lhi == rhi) { LT[llo]++; if (rlo != ((1 << K) - 1)) LT[rlo + 1]--; } else { LT[llo]++; LT[0]++; if (rlo != ((1 << K) - 1)) LT[rlo + 1]--; } HT[lhi]++; if (rhi != ((1 << K) - 1)) HT[rhi + 1]--; } for (int i = 0; i < (1 << K) - 1; ++i) HT[i + 1] += HT[i]; for (int i = 0; i < (1 << K); ++i) if (HT[i]) HT[i] = 1; for (int i = 0; i < (1 << K) - 1; ++i) LT[i + 1] += LT[i]; for (int i = 0; i < (1 << K); ++i) if (LT[i]) LT[i] = 1; auto ans = LT; copy(HT.begin(), HT.end(), back_inserter(ans)); for (int i = 0; i < (1 << K) - 1; ++i) HT[i + 1] += HT[i]; for (int i = 0; i < (1 << K) - 1; ++i) LT[i + 1] += LT[i]; auto SH = [&](int L, int R) { int ans = HT[R]; if (L) ans -= HT[L - 1]; return ans; }; auto SL = [&](int L, int R) { int ans = LT[R]; if (L) ans -= LT[L - 1]; return ans; }; for (auto [l, r, v] : V) if (!v) { uint32_t lhi = l >> K, llo = l & mask; uint32_t rhi = r >> K, rlo = r & mask; if (lhi == rhi) { if (SH(lhi, lhi) != 0 && SL(llo, rlo) != 0) return {}; } else { if (SH(lhi, lhi) != 0 && SL(llo, (1 << K) - 1) != 0) return {}; if (SH(lhi + 1, rhi - 1) != 0 && SL(0, (1 << K) - 1) != 0) return {}; if (SH(rhi, rhi) != 0 && SL(0, rlo) != 0) return {}; } } return ans; } int K, Q; uint32_t L[MAXQ], R[MAXQ], V[MAXQ]; int main() { scanf( %d%d , &K, &Q); for (int i = 0; i < Q; ++i) { scanf( % SCNu32 % SCNu32 % SCNu32, L + i, R + i, V + i); } vector<vector<int> > ans(16); for (int i = 0; i < 16; ++i) { vector<tuple<uint32_t, uint32_t, int> > P; for (int j = 0; j < Q; ++j) P.emplace_back(L[j], R[j], (V[j] >> i) & 1); ans[i] = solve(K, P); if (ans[i].size() == 0) { puts( impossible ); return 0; } } puts( possible ); for (int i = 0; i < (2 << K); ++i) { int r = 0; for (int j = 0; j < 16; ++j) if (ans[j][i]) r |= 1 << j; printf( %d n , r); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O22A_4_V
`define SKY130_FD_SC_LS__O22A_4_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog wrapper for o22a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o22a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o22a_4 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o22a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o22a_4 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o22a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O22A_4_V
|
#include <bits/stdc++.h> using namespace std; int dp[10000]; int main() { int N, M; cin >> N >> M; int T; double D; int ans = 0; for (int i = 0; i < N; i++) { cin >> T >> D; dp[T - 1]++; for (int j = 0; j < T - 1; j++) dp[T - 1] = max(dp[T - 1], dp[j] + 1); } for (int i = 0; i < M; i++) ans = max(ans, dp[i]); cout << N - ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int n = 0, T = 0; long long D[1003], g[1003]; long long x1[1003], xn[1003], Y1[1003], Yn[1003]; void getDisPre(long long x, int N, long long (&t1)[1003], long long (&tn)[1003]) { if (N == 0) { t1[0] = tn[0] = 0; return; } if (N == 1) { t1[1] = (x == 2); tn[1] = (x == 1); return; } if (x <= D[N - 1]) { getDisPre(x, N - 1, t1, tn); t1[N] = min(t1[N - 1], tn[N - 1] + 2); tn[N] = min(t1[N - 1], tn[N - 1]) + g[N - 2] + 1; } else { getDisPre(x - D[N - 1], N - 2, t1, tn); t1[N] = t1[N - 2] + 1; tn[N] = tn[N - 2]; } } long long dis(long long x, long long y, long long N) { if (N <= 1) return x != y; if (x > y) swap(x, y); if (x <= D[N - 1] && y <= D[N - 1]) return min(min(min(x1[N - 1] + Y1[N - 1], xn[N - 1] + Yn[N - 1]), min(x1[N - 1] + Yn[N - 1] + 2, xn[N - 1] + Y1[N - 1] + 2)), dis(x, y, N - 1)); else if (x <= D[N - 1]) return min(x1[N - 1], xn[N - 1]) + 1 + Y1[N - 2]; else return dis(x - D[N - 1], y - D[N - 1], N - 2); } int main() { scanf( %d %d , &T, &n); if (n > 80) n = 80; D[0] = 1; D[1] = 2; for (int i = 2; i <= n; ++i) D[i] = D[i - 1] + D[i - 2]; g[0] = 0; g[1] = 1; g[2] = 1; for (int i = 3; i <= n; ++i) g[i] = g[i - 2] + 1; for (int t = 1; t <= T; ++t) { long long x = 0, y = 0; scanf( %lld %lld , &x, &y); if (x > y) swap(x, y); getDisPre(x, n, x1, xn); getDisPre(y, n, Y1, Yn); printf( %lld n , dis(x, y, n)); } return 0; } |
// megafunction wizard: %Shift register (RAM-based)%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTSHIFT_TAPS
// ============================================================
// File Name: SHIFTREGRAM.v
// Megafunction Name(s):
// ALTSHIFT_TAPS
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module SHIFTREGRAM (
clken,
clock,
shiftin,
shiftout,
taps);
input clken;
input clock;
input [12:0] shiftin;
output [12:0] shiftout;
output [168:0] taps;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clken;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACLR NUMERIC "0"
// Retrieval info: PRIVATE: CLKEN NUMERIC "1"
// Retrieval info: PRIVATE: GROUP_TAPS NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: NUMBER_OF_TAPS NUMERIC "13"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: TAP_DISTANCE NUMERIC "5"
// Retrieval info: PRIVATE: WIDTH NUMERIC "13"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altshift_taps"
// Retrieval info: CONSTANT: NUMBER_OF_TAPS NUMERIC "13"
// Retrieval info: CONSTANT: TAP_DISTANCE NUMERIC "5"
// Retrieval info: CONSTANT: WIDTH NUMERIC "13"
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC "clken"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: shiftin 0 0 13 0 INPUT NODEFVAL "shiftin[12..0]"
// Retrieval info: USED_PORT: shiftout 0 0 13 0 OUTPUT NODEFVAL "shiftout[12..0]"
// Retrieval info: USED_PORT: taps 0 0 169 0 OUTPUT NODEFVAL "taps[168..0]"
// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @shiftin 0 0 13 0 shiftin 0 0 13 0
// Retrieval info: CONNECT: shiftout 0 0 13 0 @shiftout 0 0 13 0
// Retrieval info: CONNECT: taps 0 0 169 0 @taps 0 0 169 0
// Retrieval info: GEN_FILE: TYPE_NORMAL SHIFTREGRAM.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL SHIFTREGRAM.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL SHIFTREGRAM.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL SHIFTREGRAM.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL SHIFTREGRAM_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL SHIFTREGRAM_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// Copyright (c) 2014 CERN
// Maciej Suminski <>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Tests for various subprogram features (see the responding VHDL file for
// details).
module subprogram_test;
subprogram dut();
initial begin
#1; // wait for signal assignment
if(dut.negated !== 'b00111000) begin
$display("FAILED 1");
$finish;
end
if(dut.reversed != 'b11100001) begin
$display("FAILED 2");
$finish;
end
$display("PASSED");
end
endmodule
|
/*
File: toggle2pulse.v
This file is part of the Parallella FPGA Reference Design.
Copyright (C) 2013 Adapteva, Inc.
Contributed by Roman Trogan <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module toggle2pulse(/*AUTOARG*/
// Outputs
out,
// Inputs
clk, in, reset
);
//clocks
input clk;
input in;
output out;
//reset
input reset;
reg out_reg;
always @ (posedge clk or posedge reset)
if(reset)
out_reg <= 1'b0;
else
out_reg <= in;
assign out = in ^ out_reg;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t, i, j, b, p, f, h, c, sum; cin >> t; while (t--) { cin >> b >> p >> f >> h >> c; sum = 0; b /= 2; if (h < c) { if (b < f) { sum += (c * b); b = 0; } else if (b > f) { sum += (c * f); b -= f; } else { sum += (c * f); b = 0; } if (b > 0) { if (b < p) { sum += (h * b); } else if (b > p) { sum += (h * p); } else sum += (h * p); } } else if (h > c) { if (b < p) { sum += (h * b); b = 0; } else if (b > p) { sum += (h * p); b -= p; } else { sum += (h * p); b = 0; } if (b > 0) { if (b < f) { sum += (c * b); } else if (b > f) { sum += (c * f); } else sum += (c * f); } } else sum += (c * min(b, p + f)); cout << sum << endl; } } |
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module my_dff (
input d,
clk,
output reg q
);
always @(posedge clk) q <= d;
endmodule
module my_top (
inout wire pad,
input wire i,
input wire t,
output wire o,
input wire clk
);
wire i_r;
wire t_r;
wire o_r;
// IOB
assign pad = (t_r) ? i_r : 1'bz;
assign o_r = pad;
// DFFs
my_dff dff_i (
i,
clk,
i_r
);
my_dff dff_t (
t,
clk,
t_r
);
my_dff dff_o (
o_r,
clk,
o
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main(void) { int m; cin >> m; int C[m]; for (int i = 0; i < m; ++i) cin >> C[i]; int x, y; cin >> x >> y; int sum_1, sum_2; sum_1 = sum_2 = 0; int now = 0; for (int i = 0; i < m; ++i) sum_2 += C[i]; while (sum_1 < x || sum_1 > y || sum_2 < x || sum_2 > y) { if (now == m) break; sum_1 += C[now]; sum_2 -= C[now]; ++now; } if (now == m) cout << 0; else cout << now + 1; return 0; } |
#include<iostream> #include<bits/stdc++.h> using namespace std; #define boost ios_base::sync_with_stdio(false); cin.tie(NULL) #define ll unsigned long long int #define tinput int t; cin>>t; while(t--) #define rep(i,n,s) for((i)=(s); (i)<(n); (i)++) template <typename T> T getmini(T x, T y) { return (x<y)?x:y; } template <typename T> T getmaxi(T x, T y) { return (x>y)?x:y; } int main(){ #ifndef ONLINE_JUDGE freopen( b_input.txt , r , stdin); freopen( b_output.txt , w , stdout); #endif boost; tinput { int x, y; cin>>x>>y; int ans = x+y; if(abs(x-y)>1) { ans = ans + abs(x-y) - 1; } cout<<ans<<endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 3010; struct edge { int v, next, flag; } e[N << 2]; int head[N], cnt; void addedge(int u, int v, int flag) { e[cnt].v = v; e[cnt].flag = flag; e[cnt].next = head[u]; head[u] = cnt++; } int sum[N], dp[N]; void dfs(int u, int pre) { sum[u] = 0; for (int i = head[u]; i != -1; i = e[i].next) { if (e[i].v == pre) continue; dfs(e[i].v, u); int v = e[i].v; sum[u] += sum[v] + e[i].flag; } dp[u] = sum[u]; for (int i = head[u]; i != -1; i = e[i].next) { if (e[i].v == pre) continue; int v = e[i].v; dp[u] = min(dp[u], sum[u] - sum[v] + 1 - e[i].flag + dp[v] - e[i].flag); } } int main() { memset(head, -1, sizeof(head)); int n; scanf( %d , &n); for (int i = 1; i < n; i++) { int x, y, z; scanf( %d%d , &x, &y); addedge(x, y, 0); addedge(y, x, 1); } int ans = 0x7fffffff; for (int i = 1; i <= n; i++) { dfs(i, -1); for (int j = 1; j <= n; j++) { ans = min(ans, sum[i] - sum[j] + dp[j]); } } printf( %d n , ans); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08:18:40 03/03/2016
// Design Name:
// Module Name: register
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module register(clock_in, readReg1,readReg2, writeReg,writeData,regWrite, rst,readData1,readData2, led, switch, PC);
input clock_in;
input [25:21] readReg1;
input [20:16] readReg2;
input [4:0] writeReg;
input [31:0] writeData;
input regWrite;
input rst;
input [31:0] PC;
input [1:0] switch;
output [31:0] readData1;
output [31:0] readData2;
output reg[7:0] led;
reg[31:0] regFile[31:0];
reg[31:0] readData1;
reg[31:0] readData2;
integer i;
initial
begin
regFile[0] = 32'h00000000;
regFile[1] = 32'h00000001;
regFile[2] = 32'h00000002;
regFile[3] = 32'h00000003;
regFile[4] = 32'h00000004;
regFile[5] = 32'h00000005;
regFile[6] = 32'h00000006;
regFile[7] = 32'h00000007;
regFile[8] = 32'h00000008;
regFile[9] = 32'h00000009;
regFile[10] = 32'h0000000a;
regFile[11] = 32'h0000000b;
regFile[12] = 32'h0000000c;
regFile[13] = 32'h0000000d;
regFile[14] = 32'h0000000e;
regFile[15] = 32'h0000000f;
regFile[16] = 32'h00000010;
regFile[17] = 32'h00000011;
regFile[18] = 32'h00000012;
regFile[19] = 32'h00000013;
regFile[20] = 32'h00000014;
regFile[21] = 32'h00000015;
regFile[22] = 32'h00000016;
regFile[23] = 32'h00000017;
regFile[24] = 32'h00000018;
regFile[25] = 32'h00000019;
regFile[26] = 32'h0000001a;
regFile[27] = 32'h0000001b;
regFile[28] = 32'h0000001c;
regFile[29] = 32'h0000001d;
regFile[30] = 32'h0000001e;
regFile[31] = 32'h0000001f;
end
always @ (readReg1 or readReg2 or regWrite or writeReg or switch)
begin
readData1 = regFile[readReg1]; //¶ÁÊý¾Ý
readData2 = regFile[readReg2];
//¿ª¹Ø¿ØÖÆledµÆÏÔʾ¼Ä´æÆ÷»òPCµÄÖµ
case(switch)
0: led[7:0] = PC[7:0];
1: led[7:0] = regFile[1][7:0];
2: led[7:0] = regFile[2][7:0];
3: led[7:0] = regFile[3][7:0];
//led[7:4] = {regFile[2][3:0]};
endcase
end
always @ (negedge clock_in)
begin
if(rst)
begin
for(i = 0; i < 32; i = i + 1)
regFile[i] = 0; //reset½«¼Ä´æÆ÷ÇåÁã
end
else if(regWrite)
regFile[writeReg] = writeData; //дÊý¾Ý
end
endmodule |
#include <bits/stdc++.h> using namespace std; string s[505]; int n, par[505][505], a[505 * 505] = {0}, v[505 * 505] = {0}, p[505 * 505]; bool b[505 * 505] = {0}; int dfs(int x, int y, int k) { par[x][y] = k; int ret = 1; if (x > 0 && par[x - 1][y] == -1 && s[x - 1][y] == . ) ret += dfs(x - 1, y, k); if (x + 1 < n && par[x + 1][y] == -1 && s[x + 1][y] == . ) ret += dfs(x + 1, y, k); if (y > 0 && par[x][y - 1] == -1 && s[x][y - 1] == . ) ret += dfs(x, y - 1, k); if (y + 1 < n && par[x][y + 1] == -1 && s[x][y + 1] == . ) ret += dfs(x, y + 1, k); return ret; } void reset(int bx, int ex, int by, int ey) { int i, j; for (i = bx; i <= ex; i++) { for (j = by; j <= ey; j++) b[par[i][j]] = 0; } } int get_sum(int bx, int ex, int by, int ey) { int i, j, ret = 0, u; for (i = bx; i <= ex; i++) { for (j = by; j <= ey; j++) { if (s[i][j] == X ) continue; u = par[i][j]; if (v[u] == 0 && b[u] == 0) ret += a[u]; b[u] = 1; } } return ret; } int main() { std::ios_base::sync_with_stdio(0); int cases, caseno = 0, i, j, k, t, u, mx, sum, temp, sz = 0; cin >> n >> k; for (i = 0; i <= n - 1; i++) cin >> s[i]; memset(par, -1, sizeof(par)); for (i = 0; i <= n - 1; i++) { for (j = 0; j <= n - 1; j++) { if (s[i][j] == X ) { par[i][j] = sz; a[sz++] = 1; } else if (par[i][j] == -1) { a[sz] = dfs(i, j, sz); sz++; } } } mx = 0; for (i = 0; i <= n - k; i++) { sum = 0; memset(v, 0, sizeof(v)); for (t = i; t <= i + k - 1; t++) { for (j = 0; j <= k - 1; j++) { v[par[t][j]]++; if (v[par[t][j]] == 1) sum += a[par[t][j]]; } } for (j = 0; j <= n - k; j++) { temp = 0; if (j > 0) { for (t = i; t <= i + k - 1; t++) { u = par[t][j - 1]; v[u]--; if (v[u] == 0) sum -= a[u]; } for (t = i; t <= i + k - 1; t++) { u = par[t][j + k - 1]; v[u]++; if (v[u] == 1) sum += a[u]; } } if (i > 0) reset(i - 1, i - 1, j, j + k - 1); if (i + k < n) reset(i + k, i + k, j, j + k - 1); if (j > 0) reset(i, i + k - 1, j - 1, j - 1); if (j + k < n) reset(i, i + k - 1, j + k, j + k); if (i > 0) temp += get_sum(i - 1, i - 1, j, j + k - 1); if (i + k < n) temp += get_sum(i + k, i + k, j, j + k - 1); if (j > 0) temp += get_sum(i, i + k - 1, j - 1, j - 1); if (j + k < n) temp += get_sum(i, i + k - 1, j + k, j + k); mx = max(mx, sum + temp); } } cout << mx << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; const int mn = 1e5 + 1; ll n, d, a[mn], b[mn], ans = 1, cnt = 1, pos = 1, ansid[mn]; struct pairs { int val, id; pairs operator+(pairs A) { return (pairs){val + A.val, id + A.id}; } } tree[mn * 4], f[mn]; pairs maxp(pairs A, pairs B) { if (A.val == B.val) { if (A.id > B.id) return A; return B; } if (A.val < B.val) return B; return A; } void update(int l, int r, int id, int x, pairs p) { if (l > x || x > r) return; if (l == r) { tree[id] = p; return; } int mid = (l + r) / 2; update(l, mid, id * 2, x, p); update(mid + 1, r, id * 2 + 1, x, p); tree[id] = maxp(tree[id * 2], tree[id * 2 + 1]); } pairs get(int l, int r, int id, int x, int y) { if (l > y || x > r) return (pairs){0, 0}; if (x <= l && r <= y) return tree[id]; int mid = (l + r) / 2; return maxp(get(l, mid, id * 2, x, y), get(mid + 1, r, id * 2 + 1, x, y)); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> d; for (int i = 1; i <= n; ++i) { cin >> a[i]; b[i] = a[i]; } sort(b + 1, b + n + 1); for (int i = 1; i <= n; ++i) { int u = upper_bound(b + 1, b + n + 1, a[i] - d) - b - 1; int v = lower_bound(b + 1, b + n + 1, a[i] + d) - b; int k = lower_bound(b + 1, b + n + 1, a[i]) - b; if (u) f[i] = maxp(f[i], get(1, n, 1, 1, u) + (pairs){1, 0}); if (v <= n) f[i] = maxp(f[i], get(1, n, 1, v, n) + (pairs){1, 0}); f[i] = maxp(f[i], (pairs){1, i}); update(1, n, 1, k, (pairs){f[i].val, i}); if (ans < f[i].val) { ans = f[i].val; pos = i; } } cout << ans << n ; ansid[ans] = pos, cnt = ans - 1; while (cnt) ansid[cnt--] = f[ansid[cnt + 1]].id; for (int i = 1; i <= ans; ++i) cout << ansid[i] << ; cout << n ; return 0; } |
/*
* This tests the synthesis of a case statement that has an empty case.
*/
module main;
reg clk, bit, foo;
// Synchronous device that toggles whenever enabled by a high bit.
always @(posedge clk)
case (bit)
1'b0: ;
1'b1: foo <= ~foo;
endcase // case(bit)
(* ivl_synthesis_off *)
always begin
#5 clk = 1;
#5 clk = 0;
end
(* ivl_synthesis_off *)
initial begin
clk = 0;
bit = 0;
foo = 0;
# 6 $display("clk=%b, bit=%b, foo=%b", clk, bit, foo);
if (bit !== 0 || foo !== 0) begin
$display("FAILED");
$finish;
end
#10 $display("clk=%b, bit=%b, foo=%b", clk, bit, foo);
if (bit !== 0 || foo !== 0) begin
$display("FAILED");
$finish;
end
bit <= 1;
#10 $display("clk=%b, bit=%b, foo=%b", clk, bit, foo);
if (bit !== 1 || foo !== 1) begin
$display("FAILED");
$finish;
end
#10 $display("clk=%b, bit=%b, foo=%b", clk, bit, foo);
if (bit !== 1 || foo !== 0) begin
$display("FAILED");
$finish;
end
$display("PASSED");
$finish;
end
endmodule // main
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_sin (
enable,
clock,
dataa,
resetn,
result);
input enable;
input clock;
input resetn;
input [31:0] dataa;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
fp_sin fpc_sin(
.sysclk(clock),
.reset(~resetn),
.enable(enable),
.signin(dataa[31]),
.exponentin(dataa[30:23]),
.mantissain(dataa[22:0]),
.signout(sub_wire0[31]),
.exponentout(sub_wire0[30:23]),
.mantissaout(sub_wire0[22:0])
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MAX = 3e5 + 10; const long long INF = 1e18; const long long M = 1e6 + 10; int main() { int n, i, j, k, l, p, q; string s; cin >> n >> s; set<char> a; char st[3] = { R , G , B }; for (i = 0; i < n; i++) a.insert(s[i]); if (a.size() == 1) { cout << *a.begin(); return 0; } if (n == 2) { if (s[i] == s[i + 1]) cout << s[i]; else { for (i = 0; i < 3; i++) { if (a.find(st[i]) == a.end()) cout << st[i]; } } } else { if (a.size() == 3) cout << BGR ; else { char ch; string s2 = ; for (i = 0; i < 3; i++) { if (a.find(st[i]) == a.end()) ch = st[i]; } for (i = 0; i < 3; i++) { l = 0; for (j = 0; j < n; j++) { if (s[j] == st[i]) l++; } if (l == 1) { s2 += ch; s2 += st[i]; sort(s2.begin(), s2.end()); cout << s2; break; } } if (l != 1) cout << BGR ; } } } |
#include <bits/stdc++.h> int main() { int n, i, s = 0, m = 0, t; int a[100001]; scanf( %d , &n); for (i = 0; i < n; i++) { scanf( %d , a + i); s += a[i]; } t = a[0]; if (t > m) m = t; for (i = 1; i < n; i++) { if (t > 0) t += a[i]; else t = a[i]; if (t > m) m = t; } printf( %d n , 2 * m - s); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:28:18 08/24/2011
// Design Name:
// Module Name: q15_add
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module qadd #(
//Parameterized values
parameter Q = 15,
parameter N = 32
)
(
input [N-1:0] a,
input [N-1:0] b,
output [N-1:0] c
);
reg [N-1:0] res;
assign c = res;
always @(a,b) begin
// both negative or both positive
if(a[N-1] == b[N-1]) begin // Since they have the same sign, absolute magnitude increases
res[N-2:0] = a[N-2:0] + b[N-2:0]; // So we just add the two numbers
res[N-1] = a[N-1]; // and set the sign appropriately... Doesn't matter which one we use,
// they both have the same sign
// Do the sign last, on the off-chance there was an overflow...
end // Not doing any error checking on this...
// one of them is negative...
else if(a[N-1] == 0 && b[N-1] == 1) begin // subtract a-b
if( a[N-2:0] > b[N-2:0] ) begin // if a is greater than b,
res[N-2:0] = a[N-2:0] - b[N-2:0]; // then just subtract b from a
res[N-1] = 0; // and manually set the sign to positive
end
else begin // if a is less than b,
res[N-2:0] = b[N-2:0] - a[N-2:0]; // we'll actually subtract a from b to avoid a 2's complement answer
if (res[N-2:0] == 0)
res[N-1] = 0; // I don't like negative zero....
else
res[N-1] = 1; // and manually set the sign to negative
end
end
else begin // subtract b-a (a negative, b positive)
if( a[N-2:0] > b[N-2:0] ) begin // if a is greater than b,
res[N-2:0] = a[N-2:0] - b[N-2:0]; // we'll actually subtract b from a to avoid a 2's complement answer
if (res[N-2:0] == 0)
res[N-1] = 0; // I don't like negative zero....
else
res[N-1] = 1; // and manually set the sign to negative
end
else begin // if a is less than b,
res[N-2:0] = b[N-2:0] - a[N-2:0]; // then just subtract a from b
res[N-1] = 0; // and manually set the sign to positive
end
end
end
endmodule |
#include <bits/stdc++.h> using namespace std; const int dir[5][2] = {0, 1, 0, -1, 1, 0, -1, 0, 0, 0}; const int inf = 0x7fffffff; const int mod = 1000000; const int Max = 1000000; int temp[10], ans[Max]; void check(char *s) { int index = 0, dec, sum = 0, cnt = 0; dec = atoi(s); memset(temp, 0, sizeof(temp)); for (int i = 0; i < strlen(s); ++i) sum += s[i]; for (int i = max((dec - sum), 0); i <= dec; ++i) { int temp = i, t = i; while (temp) { t += (temp % 10); temp /= 10; } if (t == dec) { ans[cnt++] = i; } } printf( %d n , cnt); for (int i = 0; i < cnt; ++i) { printf( %d%c , ans[i], i == cnt - 1 ? n : ); } } int main() { char num[10]; scanf( %s , num); check(num); return 0; } |
#include <bits/stdc++.h> using namespace std; void fast() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); } int main() { fast(); long long int t = 1; while (t--) { long long int n, m; cin >> n >> m; long long int a[n][m], b[n][m]; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> a[i][j]; } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> b[i][j]; } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (a[i][j] > b[i][j]) { a[i][j] = b[i][j] + a[i][j]; b[i][j] = a[i][j] - b[i][j]; a[i][j] = a[i][j] - b[i][j]; } } } bool ans = 1; for (int i = 0; i < n; i++) { for (int j = 0; j < m - 1; j++) { if (a[i][j] >= a[i][j + 1]) { ans = 0; break; } if (b[i][j] >= b[i][j + 1]) { ans = 0; break; } } } for (int i = 0; i < n - 1; i++) { for (int j = 0; j < m; j++) { if (a[i][j] >= a[i + 1][j]) { ans = 0; break; } if (b[i][j] >= b[i + 1][j]) { ans = 0; break; } } } if (!ans) cout << Impossible ; else cout << Possible ; } } |
#include <bits/stdc++.h> using namespace std; int main() { int b, x; double a, c; cin >> a >> b >> c; a = ceil(a * (c / 100)); x = a; x -= b; if (x < 1) x = 0; cout << x << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__XNOR3_SYMBOL_V
`define SKY130_FD_SC_HD__XNOR3_SYMBOL_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__xnor3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__XNOR3_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__EINVN_1_V
`define SKY130_FD_SC_HDLL__EINVN_1_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog wrapper for einvn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__einvn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__einvn_1 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__einvn_1 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__EINVN_1_V
|
#include <bits/stdc++.h> using namespace std; vector<int> vec[10]; vector<vector<int> > vvv(183); queue<int> qu; map<string, int> mp; map<string, int>::iterator iter; bool ch[10] = {false}; int main() { string s1, s2; cin >> s1 >> s2; for (int i = 0; i < s1.length(); i++) { if (s1[i] >= s2[i]) s1[i] = s2[i]; else { cout << -1 << endl; return 0; } } cout << s1 << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int p = 998244353, inv2 = 499122177; inline void XOR(int *a, int lim, int type) { for (register int mid = 1; mid < lim; mid <<= 1) { for (register int i = mid << 1, j = 0; j < lim; j += i) { for (register int k = 0; k < mid; k++) { a[j + k] += a[j + k + mid]; if (a[j + k] >= p) a[j + k] -= p; a[j + k + mid] = a[j + k] - a[j + k + mid] - a[j + k + mid]; if (a[j + k + mid] >= p) a[j + k + mid] -= p; else while (a[j + k + mid] < 0) a[j + k + mid] += p; if (type == -1) a[j + k] = 1ll * a[j + k] * inv2 % p, a[j + k + mid] = 1ll * a[j + k + mid] * inv2 % p; } } } } int n, m, lim; char s[25][2000086]; int a[2000086], b[2000086]; int ans = 0x3f3f3f3f; int main() { scanf( %d%d , &n, &m), lim = 1 << n; for (int i = 1; i <= n; i++) scanf( %s , s[i] + 1); for (int i = 1; i <= m; i++) { int sum = 0; for (int j = 1, k = 1; j <= n; j++, k <<= 1) if (s[j][i] == 1 ) sum += k; ++a[sum]; } for (int i = 1; i <= lim; i++) { for (int j = i; j; j >>= 1) if (j & 1) ++b[i]; b[i] = min(b[i], n - b[i]); } XOR(a, lim, 1), XOR(b, lim, 1); for (int i = 0; i < lim; i++) a[i] = 1ll * a[i] * b[i] % p; XOR(a, lim, -1); for (int i = 0; i < lim; i++) ans = min(ans, a[i]); printf( %d , ans); } |
#include <bits/stdc++.h> using namespace std; int ar[50][50]; int n; int check(int r, int c) { int v = 0; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (ar[r][i] + ar[j][c] == ar[r][c]) { return 1; } } } return 0; } int main() { cin >> n; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) cin >> ar[i][j]; } int flag = 1; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (ar[i][j] != 1) { flag = flag && check(i, j); } if (!flag) { break; } } if (!flag) { break; } } if (flag) { cout << Yes << endl; } else { cout << No << endl; } } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: mb2cpx_sm.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/***************************************************************************
* mb2cpx_sm.v State machine for the MicroBlaze FSL to SPARC CPX interface
*
* $Id: $
***************************************************************************/
// Global header file includes
// Local header file includes
`include "ccx2mb.h"
module mb2cpx_sm (
// Outputs
cpx_fsl_s_read,
cpx_shift_out,
cpx_spc_data_rdy_cx2,
// Inputs
rclk,
reset_l,
fsl_cpx_s_exists,
fsl_cpx_s_control,
atomic_txn
);
parameter CPX_GEAR_RATIO = (((`CPX_WIDTH+3-1)/`FSL_D_WIDTH)+1);
parameter CPX_FSL_EXTRA_BITS = (`FSL_D_WIDTH * CPX_GEAR_RATIO) -
(`PCX_WIDTH+3);
parameter [2:0] CPX_FIRST_COUNT = CPX_GEAR_RATIO - 2;
parameter pCPX_IDLE = 0,
pCPX_SHIFT = 1,
pCPX_AT_WAIT = 2;
parameter CPX_IDLE = 3'b001,
CPX_SHIFT = 3'b010,
CPX_AT_WAIT = 3'b100;
// Outputs
output cpx_fsl_s_read;
output cpx_shift_out;
output cpx_spc_data_rdy_cx2;
// Inputs
input rclk;
input reset_l;
input fsl_cpx_s_exists;
input fsl_cpx_s_control;
input atomic_txn;
// Wire definitions for outputs
reg cpx_fsl_s_read;
reg cpx_shift_out;
wire cpx_spc_data_rdy_cx2;
// State machine to control the shifting of data
reg [2:0] curr_state;
reg [2:0] next_state;
reg [2:0] curr_count;
reg [2:0] next_count;
reg atomic_first;
reg atomic_second;
reg next_atomic_first;
reg next_atomic_second;
reg next_shift_out;
reg atomic_second_d1;
reg atomic_second_d2;
reg cpx_shift_out_d1;
always @ (posedge rclk) begin // Start with a synchronous reset
if (!reset_l) begin
curr_state <= CPX_IDLE;
curr_count <= 3'b000;
atomic_first <= 1'b0;
atomic_second <= 1'b0;
cpx_shift_out <= 1'b0;
end
else begin
curr_state <= next_state;
curr_count <= next_count;
atomic_first <= next_atomic_first;
atomic_second <= next_atomic_second;
cpx_shift_out <= next_shift_out;
end
end
always @(posedge rclk) begin
atomic_second_d1 <= atomic_second;
atomic_second_d2 <= atomic_second_d1;
cpx_shift_out_d1 <= cpx_shift_out;
end
always @ (curr_state or fsl_cpx_s_exists or fsl_cpx_s_control or
curr_count or atomic_txn or atomic_first or atomic_second) begin
case (1)
curr_state[pCPX_IDLE] : begin
next_atomic_second = 1'b0;
next_shift_out = 1'b0;
if (fsl_cpx_s_exists && fsl_cpx_s_control) begin
next_state = CPX_SHIFT;
next_count = CPX_FIRST_COUNT;
next_atomic_first = atomic_txn;
cpx_fsl_s_read = 1'b1;
end
// Expect that the control bit will be set for the first
// 32-bit sub-word of each transaction. Just a double-check
// to ensure we are in sync. Drop any initial words without
// a control bit
else if (fsl_cpx_s_exists && !fsl_cpx_s_control) begin
next_state = CPX_IDLE;
next_count = 3'b000;
next_atomic_first = 1'b0;
cpx_fsl_s_read = 1'b1;
end
else begin
next_state = CPX_IDLE;
next_count = 3'b000;
next_atomic_first = 1'b0;
cpx_fsl_s_read = 1'b0;
end
end
curr_state[pCPX_SHIFT] : begin
if (fsl_cpx_s_exists && curr_count == 3'b000) begin
if (atomic_first) begin
next_state = CPX_AT_WAIT;
next_count = curr_count;
next_atomic_first = 1'b0;
next_atomic_second = atomic_first;
cpx_fsl_s_read = 1'b1;
next_shift_out = 1'b1;
end
else begin
next_state = CPX_IDLE;
next_count = CPX_FIRST_COUNT;
next_atomic_first = 1'b0;
next_atomic_second = 1'b0;
cpx_fsl_s_read = 1'b1;
next_shift_out = 1'b1;
end
end
else if (fsl_cpx_s_exists) begin
next_state = CPX_SHIFT;
next_count = curr_count - 3'b001;
next_atomic_first = atomic_first;
next_atomic_second = atomic_second;
cpx_fsl_s_read = 1'b1;
next_shift_out = 1'b0;
end
else begin
next_state = CPX_SHIFT;
next_count = curr_count;
next_atomic_first = atomic_first;
next_atomic_second = atomic_second;
cpx_fsl_s_read = 1'b0;
next_shift_out = 1'b0;
end
end
curr_state[pCPX_AT_WAIT] : begin
next_atomic_first = atomic_first;
next_atomic_second = atomic_second;
next_shift_out = 1'b0;
if (fsl_cpx_s_exists && fsl_cpx_s_control) begin
next_state = CPX_SHIFT;
next_count = CPX_FIRST_COUNT;
cpx_fsl_s_read = 1'b1;
end
// Expect that the control bit will be set for the first
// 32-bit sub-word of each transaction. Just a double-check
// to ensure we are in sync. Drop any initial words without
// a control bit
else if (fsl_cpx_s_exists && !fsl_cpx_s_control) begin
next_state = CPX_AT_WAIT;
next_count = 3'b000;
cpx_fsl_s_read = 1'b1;
end
else begin
next_state = CPX_AT_WAIT;
next_count = 3'b000;
cpx_fsl_s_read = 1'b0;
end
end
default : begin
next_state = CPX_IDLE;
next_count = 3'b000;
next_atomic_first = 1'b0;
next_atomic_second = 1'b0;
cpx_fsl_s_read = 1'b0;
next_shift_out = 1'b0;
end
endcase
end
// Outputs of the state machine
assign cpx_spc_data_rdy_cx2 = (!atomic_second && !atomic_second_d2 &&
cpx_shift_out_d1) ||
(atomic_second_d1 && cpx_shift_out);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O41AI_SYMBOL_V
`define SKY130_FD_SC_LP__O41AI_SYMBOL_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o41ai (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input A4,
input B1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O41AI_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; using ld = long double; using ll = long long; using ull = unsigned long long; const int INF = 1 << 30; const ll LINF = 1LL << 60; const int SZ = 1 << 13; char buff[SZ], *pos = buff + SZ - 1; inline ll read() { ll x = 0; int f = 1, c = (++pos == buff + SZ ? fread(pos = buff, 1, SZ, stdin), *pos : *pos); for (; !isdigit(c); c = (++pos == buff + SZ ? fread(pos = buff, 1, SZ, stdin), *pos : *pos)) if (c == - ) f = -f; for (; isdigit(c); c = (++pos == buff + SZ ? fread(pos = buff, 1, SZ, stdin), *pos : *pos)) x = (x << 3) + (x << 1) + (c ^ 48); return x * f; } const int N = 5005; int n; int T; int t[N]; ld p[N], pw[N]; ld dp[2][N]; int main() { cout << fixed << setprecision(9); n = read(), T = read(); for (int i = 1; i <= n; ++i) p[i] = read() / 100.0, t[i] = read(), pw[i] = pow(1 - p[i], t[i] - 1); ld ans = 0; dp[0][0] = 1; int pp = 0, qq = 1; for (int i = 1; i <= n; ++i) { ld sum = 0; for (int j = 1; j <= T; ++j) { sum = sum * (1 - p[i]) + dp[pp][j - 1]; if (j >= t[i]) sum -= dp[pp][j - t[i]] * pw[i]; dp[qq][j] = sum * p[i]; if (j >= t[i]) dp[qq][j] += dp[pp][j - t[i]] * pw[i]; ans += dp[qq][j]; } swap(pp, qq); memset(dp[qq], 0, sizeof dp[qq]); } cout << ans; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD3_SYMBOL_V
`define SKY130_FD_SC_LS__CLKDLYINV5SD3_SYMBOL_V
/**
* clkdlyinv5sd3: Clock Delay Inverter 5-stage 0.50um length inner
* stage gate.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__clkdlyinv5sd3 (
//# {{data|Data Signals}}
input A,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV5SD3_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFSTP_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__SDFSTP_PP_BLACKBOX_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sdfstp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFSTP_PP_BLACKBOX_V
|
/**
* clock_divider.v - Microcoded Accumulator CPU
* Copyright (C) 2015 Orlando Arias, David Mascenik
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
module clock_divider(
input wire clk,
input wire res,
input wire [ 1 : 0] prescaler,
output wire clk_out
);
reg clk_div;
reg [ 2**16 - 1 : 0 ] counter;
reg [ 2**16 - 1 : 0 ] counter2;
assign clk_out = clk_div;
always @(prescaler or clk or counter or counter2) begin
case(prescaler)
2'b00: clk_div = clk;
2'b01: clk_div = counter[0];
2'b10: clk_div = counter[2**16 - 1];
2'b11: clk_div = counter2[2**8 - 1];
endcase
end
always @(posedge clk) begin
if(res) begin
counter <= {(2**22 - 1){1'b0}};
counter2 <= {(2**22 - 1){1'b0}};
end
else counter <= counter + 1'b1;
end
always @(counter[2**16 - 1])
counter2 <= counter2 + 1'b1;
endmodule
/* vim: set ts=4 tw=79 syntax=verilog */
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// The top level RAM module
//
// ====================================================================
module sirv_gnrl_ram
#(parameter DP = 32,
parameter DW = 32,
parameter FORCE_X2ZERO = 1,
parameter MW = 4,
parameter AW = 15
) (
input sd,
input ds,
input ls,
input rst_n,
input clk,
input cs,
input we,
input [AW-1:0] addr,
input [DW-1:0] din,
input [MW-1:0] wem,
output[DW-1:0] dout
);
//To add the ASIC or FPGA or Sim-model control here
// This is the Sim-model
//
`ifdef FPGA_SOURCE
sirv_sim_ram #(
.FORCE_X2ZERO (1'b0),
.DP (DP),
.AW (AW),
.MW (MW),
.DW (DW)
)u_sirv_sim_ram (
.clk (clk),
.din (din),
.addr (addr),
.cs (cs),
.we (we),
.wem (wem),
.dout (dout)
);
`else
sirv_sim_ram #(
.FORCE_X2ZERO (FORCE_X2ZERO),
.DP (DP),
.AW (AW),
.MW (MW),
.DW (DW)
)u_sirv_sim_ram (
.clk (clk),
.din (din),
.addr (addr),
.cs (cs),
.we (we),
.wem (wem),
.dout (dout)
);
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6; const long long inf = 1e17; long long overFlow(long long a, long long b) { if ((inf / a) < b) return 1; return 0; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); long long x0, y0, ax, ay, bx, by; cin >> x0 >> y0 >> ax >> ay >> bx >> by; long long xs, ys, t; cin >> xs >> ys >> t; vector<pair<long long, long long> > v; v.push_back({x0, y0}); while (true) { if (overFlow(x0, ax) || overFlow(y0, ay)) break; x0 = ax * x0 + bx, y0 = ay * y0 + by; v.push_back({x0, y0}); } if (v.size() > 100) assert(0); int ans = 0; for (int i = 0; i < v.size(); i++) { int cnt = 0; long long ds = abs(v[i].first - xs) + abs(v[i].second - ys); if (ds > t) continue; cnt++; for (int j = i - 1; j >= 0; j--) { ds += v[j + 1].first - v[j].first + v[j + 1].second - v[j].second; if (ds > t) break; cnt++; } if (ds > t) { ans = max(ans, cnt); continue; } int pr = 0; for (int j = i + 1; j < v.size(); j++) { ds += v[j].first - v[pr].first + v[j].second - v[pr].second; if (ds > t) break; cnt++; pr = j; } ans = max(ans, cnt); } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> char str[100010], out[100010], visited[100010]; int n, m, len, ar[100010], counter[256], tree[100010]; void update(int p, int v) { p++; while (p <= n) { tree[p] += v; p += (p & (-p)); } } int query(int p) { int res = 0; while (p) { res += tree[p]; p ^= (p & (-p)); } return res; } int range_query(int l, int r) { l++, r++; if (l > r) return 0; return (query(r) - query(--l)); } int main() { int i, j, k, l, c, res, flag; while (scanf( %d , &m) != EOF) { scanf( %s , str); n = strlen(str); memset(counter, 0, sizeof(counter)); memset(tree, 0, sizeof(tree)); for (i = 0; i < n; i++) counter[str[i]]++; for (c = a ; c <= z ; c++) { for (i = 0; i < n; i++) { if (str[i] == c) update(i, 1); } flag = 1; for (i = 0; (i + m) <= n; i++) { if (range_query(i, i + m - 1) == 0) { flag = 0; break; } } if (flag) break; } for (i = 0, len = 0; i < n; i++) { if (str[i] == c) { update(i, -1); ar[len++] = i; } } res = 0; memset(visited, 0, sizeof(visited)); for (i = 0, j = 0; (i + m) <= n; i++) { if (range_query(i, i + m - 1) == 0) { k = -1; while (j < len) { if ((ar[j] + m - 1) < i) j++; else { if (ar[j] > (i + m - 1)) break; k = j++; } } assert(k != -1); visited[k] = 1; update(ar[k], 1); } } for (i = 0; i < 100010; i++) res += visited[i]; len = 0; for (i = a ; i < c; i++) { for (j = 0; j < counter[i]; j++) { out[len++] = i; } } for (i = 0; i < res; i++) out[len++] = c; out[len] = 0; puts(out); } return 0; } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2013.4
// Copyright (C) 2013 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5(clk, reset, ce, a, b, s);
// ---- input/output ports list here ----
input clk;
input reset;
input ce;
input [17 - 1 : 0] a;
input [17 - 1 : 0] b;
output [17 - 1 : 0] s;
// ---- register and wire type variables list here ----
// wire for the primary inputs
wire [17 - 1 : 0] a_reg;
wire [17 - 1 : 0] b_reg;
// wires for each small adder
wire [5 - 1 : 0] a0_cb;
wire [5 - 1 : 0] b0_cb;
wire [10 - 1 : 5] a1_cb;
wire [10 - 1 : 5] b1_cb;
wire [15 - 1 : 10] a2_cb;
wire [15 - 1 : 10] b2_cb;
wire [17 - 1 : 15] a3_cb;
wire [17 - 1 : 15] b3_cb;
// registers for input register array
reg [5 - 1 : 0] a1_cb_regi1[1 - 1 : 0];
reg [5 - 1 : 0] b1_cb_regi1[1 - 1 : 0];
reg [5 - 1 : 0] a2_cb_regi2[2 - 1 : 0];
reg [5 - 1 : 0] b2_cb_regi2[2 - 1 : 0];
reg [2 - 1 : 0] a3_cb_regi3[3 - 1 : 0];
reg [2 - 1 : 0] b3_cb_regi3[3 - 1 : 0];
// wires for each full adder sum
wire [17 - 1 : 0] fas;
// wires and register for carry out bit
wire faccout_ini;
wire faccout0_co0;
wire faccout1_co1;
wire faccout2_co2;
wire faccout3_co3;
reg faccout0_co0_reg;
reg faccout1_co1_reg;
reg faccout2_co2_reg;
// registers for output register array
reg [5 - 1 : 0] s0_ca_rego0[2 - 0 : 0];
reg [5 - 1 : 0] s1_ca_rego1[2 - 1 : 0];
reg [5 - 1 : 0] s2_ca_rego2[2 - 2 : 0];
// wire for the temporary output
wire [17 - 1 : 0] s_tmp;
// ---- RTL code for assignment statements/always blocks/module instantiations here ----
assign a_reg = a;
assign b_reg = b;
// small adder input assigments
assign a0_cb = a_reg[5 - 1 : 0];
assign b0_cb = b_reg[5 - 1 : 0];
assign a1_cb = a_reg[10 - 1 : 5];
assign b1_cb = b_reg[10 - 1 : 5];
assign a2_cb = a_reg[15 - 1 : 10];
assign b2_cb = b_reg[15 - 1 : 10];
assign a3_cb = a_reg[17 - 1 : 15];
assign b3_cb = b_reg[17 - 1 : 15];
// input register array
always @ (posedge clk) begin
if (ce) begin
a1_cb_regi1 [0] <= a1_cb;
b1_cb_regi1 [0] <= b1_cb;
a2_cb_regi2 [0] <= a2_cb;
b2_cb_regi2 [0] <= b2_cb;
a3_cb_regi3 [0] <= a3_cb;
b3_cb_regi3 [0] <= b3_cb;
a2_cb_regi2 [1] <= a2_cb_regi2 [0];
b2_cb_regi2 [1] <= b2_cb_regi2 [0];
a3_cb_regi3 [1] <= a3_cb_regi3 [0];
b3_cb_regi3 [1] <= b3_cb_regi3 [0];
a3_cb_regi3 [2] <= a3_cb_regi3 [1];
b3_cb_regi3 [2] <= b3_cb_regi3 [1];
end
end
// carry out bit processing
always @ (posedge clk) begin
if (ce) begin
faccout0_co0_reg <= faccout0_co0;
faccout1_co1_reg <= faccout1_co1;
faccout2_co2_reg <= faccout2_co2;
end
end
// small adder generation
nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder u0 (
.faa ( a0_cb ),
.fab ( b0_cb ),
.facin ( faccout_ini ),
.fas ( fas[4:0] ),
.facout ( faccout0_co0 )
);
nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder u1 (
.faa ( a1_cb_regi1[0] ),
.fab ( b1_cb_regi1[0] ),
.facin ( faccout0_co0_reg),
.fas ( fas[9:5] ),
.facout ( faccout1_co1 )
);
nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder u2 (
.faa ( a2_cb_regi2[1] ),
.fab ( b2_cb_regi2[1] ),
.facin ( faccout1_co1_reg),
.fas ( fas[14:10] ),
.facout ( faccout2_co2 )
);
nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder_f u3 (
.faa ( a3_cb_regi3[2] ),
.fab ( b3_cb_regi3[2] ),
.facin ( faccout2_co2_reg ),
.fas ( fas[16 :15] ),
.facout ( faccout3_co3 )
);
assign faccout_ini = 1'b0;
// output register array
always @ (posedge clk) begin
if (ce) begin
s0_ca_rego0 [0] <= fas[5-1 : 0];
s1_ca_rego1 [0] <= fas[10-1 : 5];
s2_ca_rego2 [0] <= fas[15-1 : 10];
s0_ca_rego0 [1] <= s0_ca_rego0 [0];
s0_ca_rego0 [2] <= s0_ca_rego0 [1];
s1_ca_rego1 [1] <= s1_ca_rego1 [0];
end
end
// get the s_tmp, assign it to the primary output
assign s_tmp[5-1 : 0] = s0_ca_rego0[2];
assign s_tmp[10-1 : 5] = s1_ca_rego1[1];
assign s_tmp[15-1 : 10] = s2_ca_rego2[0];
assign s_tmp[17 - 1 : 15] = fas[16 :15];
assign s = s_tmp;
endmodule
// short adder
module nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder
#(parameter
N = 5
)(
input [N-1 : 0] faa,
input [N-1 : 0] fab,
input wire facin,
output [N-1 : 0] fas,
output wire facout
);
assign {facout, fas} = faa + fab + facin;
endmodule
// the final stage short adder
module nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder_f
#(parameter
N = 2
)(
input [N-1 : 0] faa,
input [N-1 : 0] fab,
input wire facin,
output [N-1 : 0] fas,
output wire facout
);
assign {facout, fas} = faa + fab + facin;
endmodule
`timescale 1 ns / 1 ps
module nfa_accept_samples_generic_hw_add_17ns_17s_17_4(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5 nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.a( din0 ),
.b( din1 ),
.s( dout ));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND4B_1_V
`define SKY130_FD_SC_LS__NAND4B_1_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog wrapper for nand4b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nand4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand4b_1 (
Y ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nand4b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand4b_1 (
Y ,
A_N,
B ,
C ,
D
);
output Y ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nand4b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND4B_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__BUF_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__BUF_PP_BLACKBOX_V
/**
* buf: Buffer.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__buf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__BUF_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EINVN_TB_V
`define SKY130_FD_SC_HD__EINVN_TB_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__einvn.v"
module top();
// Inputs are registered
reg A;
reg TE_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Z;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
TE_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 TE_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 TE_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 TE_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 TE_B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 TE_B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hd__einvn dut (.A(A), .TE_B(TE_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Z(Z));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__EINVN_TB_V
|
module recepcion(input rx,
output reg avail,
output reg [7:0] dout,
input wire clk_div);
initial begin
avail=0;
dout = 8'b00000000;
end
parameter RX_STATE_START = 2'b00;
parameter RX_STATE_DATA = 2'b01;
parameter RX_STATE_STOP = 2'b10;
reg [1:0] state = RX_STATE_START;
reg [3:0] bitpos = 0;
reg [7:0] scratch = 8'b00000000;
always @(negedge clk_div) begin
case (state)
RX_STATE_START: begin
avail<=0;
if (rx==0) begin
bitpos <= 0;
scratch <= 0;
state <= RX_STATE_DATA;
end
end
RX_STATE_DATA: begin
if(bitpos<=7) begin
scratch[bitpos] <= rx;
bitpos<=bitpos+1;
end
if (bitpos == 8)begin
state <= RX_STATE_STOP;
end
end
RX_STATE_STOP: begin
if (rx==1) begin
state <= RX_STATE_START;
dout <= scratch;
avail <= 1;
end
end
default: begin
state <= RX_STATE_START;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int s, a, b, c; cin >> s >> a >> b >> c; if (a == 0 && b == 0 && c == 0) { printf( %.10f %.10f %.10f n , s, 0, 0); } else { int sum = a + b + c; printf( %.10f %.10f %.10f n , ((double)a * s) / sum, ((double)b * s) / sum, ((double)c * s) / sum); } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__XNOR3_FUNCTIONAL_V
`define SKY130_FD_SC_LS__XNOR3_FUNCTIONAL_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__xnor3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Local signals
wire xnor0_out_X;
// Name Output Other arguments
xnor xnor0 (xnor0_out_X, A, B, C );
buf buf0 (X , xnor0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__XNOR3_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; bool isp(const int x) { if (x <= 1) return false; for (int i = 2; i * i <= x; ++i) if (x % i == 0) return false; return true; } int pow(int x, int e, const int MOD) { int r = 1; for (; e; e >>= 1, x = (long long)x * x % MOD) if (e & 1) r = (long long)r * x % MOD; return r; } bool isr(int n, int p) { for (int i = 2, q = p - 1; i * i <= q; ++i) if (q % i == 0) { if (pow(n, i, p) == 1 || pow(n, q / i, p) == 1) return false; } return true; } int main() { int n, x; scanf( %d%d , &n, &x); if (!isp(n + 1)) return puts( -1 ), 0; for (--x; x > 1; --x) if (isr(x, n + 1)) return printf( %d n , x), 0; return puts( -1 ), 0; } |
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: bigasfuckram.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.0.0 Build 145 04/22/2015 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module bigasfuckram (
address,
clock,
data,
wren,
q);
input [4:0] address;
input clock;
input [26:0] data;
input wren;
output [26:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [26:0] sub_wire0;
wire [26:0] q = sub_wire0[26:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 32,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 5,
altsyncram_component.width_a = 27,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "5"
// Retrieval info: PRIVATE: WidthData NUMERIC "27"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "27"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 5 0 INPUT NODEFVAL "address[4..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 27 0 INPUT NODEFVAL "data[26..0]"
// Retrieval info: USED_PORT: q 0 0 27 0 OUTPUT NODEFVAL "q[26..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 5 0 address 0 0 5 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 27 0 data 0 0 27 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 27 0 @q_a 0 0 27 0
// Retrieval info: GEN_FILE: TYPE_NORMAL bigasfuckram.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL bigasfuckram.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bigasfuckram.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bigasfuckram.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bigasfuckram_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bigasfuckram_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> int main() { int n; scanf( %d , &n); char str[n]; scanf( %s , &str); int count = 0; for (int i = 0; i < n; i++) if (str[i] == str[i + 1]) count++; printf( %d , count); return 0; } |
#include <bits/stdc++.h> using namespace std; int test() { long long n; cin >> n; long long cL = 0, cR = 0; long long si = 3 * 100001; long long *right = new long long[si], *left = new long long[si]; for (long long i = 0; i < si; i++) { right[i] = 0; left[i] = 0; } long long prop = 0, l = 0, r = 0; string temp; for (long long i = 0; i < n; i++) { cin >> temp; long long tempS = temp.size(); for (long long i = 0; i < tempS; i++) { if (temp[i] == ( ) { cL++; l++; } else { cR++; if (l != 0) l--; else r++; } } if (r != 0 && l != 0) { } else if (cR == cL) prop++; else if (cR > cL) right[cR - cL]++; else left[cL - cR]++; l = 0; r = 0; cL = 0; cR = 0; } long long S = 0; for (long long i = 0; i < si; i++) { if (right[i] != 0 && left[i] != 0) { S += right[i] * left[i]; } } S += prop * prop; cout << S; return 0; } int hacker() { return 0; } int main() { while (true) { return test(); cout << n n-- ; hacker(); cout << n n n----------------------------- n n n ; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A2BB2O_TB_V
`define SKY130_FD_SC_LS__A2BB2O_TB_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a2bb2o.v"
module top();
// Inputs are registered
reg A1_N;
reg A2_N;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1_N = 1'bX;
A2_N = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1_N = 1'b0;
#40 A2_N = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1_N = 1'b1;
#200 A2_N = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1_N = 1'b0;
#360 A2_N = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2_N = 1'b1;
#640 A1_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2_N = 1'bx;
#800 A1_N = 1'bx;
end
sky130_fd_sc_ls__a2bb2o dut (.A1_N(A1_N), .A2_N(A2_N), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A2BB2O_TB_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:43:04 03/22/2015
// Design Name: mux32bit2x1
// Module Name: C:/Users/Joseph/Documents/Xilinx/HW1/mux32bit2x1_test.v
// Project Name: HW1
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: mux32bit2x1
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module mux32bit2x1_test;
// Inputs
reg [31:0] In0;
reg [31:0] In1;
reg Sel;
// Outputs
wire [31:0] Y;
// Variables
integer i;
// Instantiate the Unit Under Test (UUT)
mux32bit2x1 uut (
.Y(Y),
.In0(In0),
.In1(In1),
.Sel(Sel)
);
initial begin
// Initialize Inputs Randomly.
In0 = $random % 1000 + 1000;
In1 = $random % 1000 + 1000;
Sel = $random % 2;
// Check for just 16 random cases. It is not feasible to exhaustively test all possible inputs.
for(i=0; i<16; i = i + 1)
begin
#10 In0 = $random % 1000 + 1000; In1 = $random % 1000 + 1000; Sel = $random % 2;
end
end
endmodule
|
module module5(clk_, rst_, bar, foo);
input clk_;
input rst_;
input [1:0] bar;
output foo;
parameter poser_tied = 1'b1;
parameter poser_width_in = 0+1-0+1;
parameter poser_width_out = 0+1;
parameter poser_grid_width = 2;
parameter poser_grid_depth = 1;
parameter [poser_grid_width-1:0] cellTypes [0:poser_grid_depth-1] = '{ 2'b00 };
wire [poser_width_in-1:0] poser_inputs;
assign poser_inputs = { bar };
wire [poser_width_out-1:0] poser_outputs;
assign { foo } = poser_outputs;
wire [poser_grid_width-1:0] poser_grid_output [0:poser_grid_depth-1];
wire poser_clk;
assign poser_clk = clk_;
wire poser_rst;
assign poser_rst = rst_;
for (genvar D = 0; D < poser_grid_depth; D++) begin
for (genvar W = 0; W < poser_grid_width; W++) begin
if (D == 0) begin
if (W == 0) begin
poserCell #(.cellType(cellTypes[D][W]), .activeRst(0)) pc (.clk(poser_clk),
.rst(poser_rst),
.i(^{ poser_tied ,
poser_inputs[W%poser_width_in] }),
.o(poser_grid_output[D][W]));
end else begin
poserCell #(.cellType(cellTypes[D][W]), .activeRst(0)) pc (.clk(poser_clk),
.rst(poser_rst),
.i(^{ poser_grid_output[D][W-1],
poser_inputs[W%poser_width_in] }),
.o(poser_grid_output[D][W]));
end
end else begin
if (W == 0) begin
poserCell #(.cellType(cellTypes[D][W]), .activeRst(0)) pc (.clk(poser_clk),
.rst(poser_rst),
.i(^{ poser_grid_output[D-1][W],
poser_grid_output[D-1][poser_grid_depth-1] }),
.o(poser_grid_output[D][W]));
end else begin
poserCell #(.cellType(cellTypes[D][W]), .activeRst(0)) pc (.clk(poser_clk),
.rst(poser_rst),
.i(^{ poser_grid_output[D-1][W],
poser_grid_output[D][W-1] }),
.o(poser_grid_output[D][W]));
end
end
end
end
generate
if (poser_width_out == 1) begin
poserMux #(.poser_mux_width_in(poser_grid_width)) pm (.i(poser_grid_output[poser_grid_depth-1]),
.o(poser_outputs));
end
else if (poser_grid_width == poser_width_out) begin
assign poser_outputs = poser_grid_output[poser_grid_depth-1];
end
else if (poser_grid_width > poser_width_out) begin
wire [poser_grid_width-1:0] poser_grid_output_last;
assign poser_grid_output_last = poser_grid_output[poser_grid_depth-1];
poserMux #(.poser_mux_width_in((poser_grid_width - poser_width_out) + 1)) pm (.i(poser_grid_output_last[poser_grid_width-1:poser_width_out-1]),
.o(poser_outputs[poser_width_out-1]));
assign poser_outputs[poser_width_out-2:0] = poser_grid_output_last[poser_width_out-2:0];
end
endgenerate
endmodule
|
module build_tree (
input wire in,
output [15:0] reg out,
output [3:0] reg out_addr,
output reg out_valid,
output reg done,
input wire CLK,
input wire Reset,
input wire EN
);
// the len = 4
// This means that there is no need for the initial 6 bits
// These 6 bits would normally tell the length of the values
// Our value length is always 4
reg [15:0] code;
reg [3:0] leaf;
reg [4:0] leaf_valid_sh;
reg [4:0] done_acc;
assign out_valid = leaf_valid[0];
always @ (negedge Reset or posedge CLK) begin
if (~Reset) begin
out <= 16'b0;
out_addr <= 4'b0;
out_valid <= 1'b0;
done <= 1'b0;
code <= 16'b0;
leaf; <= 4'b0;
leaf_valid_sh <= 5'b0;
done_acc <= 5'b0;
end
else begin
if (~leaf_valid[4]) begin
// We have not found a leaf
// We are traversing the tree
if(~in) begin
leaf_valid_sh <= 5'b0;
out <= 16'b0;
code <= {code[14:1], 1'b0};
end
else begin
// We have discovered a new leaf
// Now it is time to enter it in
leaf_valid_sh <= 5'b10000;
out <= code;
casex (code)
16'bxxxxxxxxxxxxxxx0 : code <= {00'b0, code[15:01], 1'b1};
16'bxxxxxxxxxxxxxx01 : code <= {01'b0, code[15:02], 1'b1};
16'bxxxxxxxxxxxxx011 : code <= {02'b0, code[15:03], 1'b1};
16'bxxxxxxxxxxxx0111 : code <= {03'b0, code[15:04], 1'b1};
16'bxxxxxxxxxxx01111 : code <= {04'b0, code[15:05], 1'b1};
16'bxxxxxxxxxx011111 : code <= {05'b0, code[15:06], 1'b1};
16'bxxxxxxxxx0111111 : code <= {06'b0, code[15:07], 1'b1};
16'bxxxxxxxx01111111 : code <= {07'b0, code[15:08], 1'b1};
16'bxxxxxxx011111111 : code <= {08'b0, code[15:09], 1'b1};
16'bxxxxxx0111111111 : code <= {09'b0, code[15:10], 1'b1};
16'bxxxxx01111111111 : code <= {10'b0, code[15:11], 1'b1};
16'bxxxx011111111111 : code <= {11'b0, code[15:12], 1'b1};
16'bxxx0111111111111 : code <= {12'b0, code[15:13], 1'b1};
16'bxx01111111111111 : code <= {13'b0, code[15:14], 1'b1};
16'bx011111111111111 : code <= {14'b0, code[15:15], 1'b1};
16'b0111111111111111 : code <= 16'h1;
end
end
else begin
// We have found a leaf
if(~leaf_valid[0]) begin
// Still entering in the leaf
leaf_valid <= {1'b1, leaf_valid[4:1]};
out <= out;
end
else begin
// Finished entering in the leaf
// Go back to tree traversal
done_acc <= done_acc + 1;
end
end
end
end
endmodule |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013 by Wilson Snyder.
interface ifc;
integer value;
endinterface
module t (/*AUTOARG*/
// Inputs
clk
);
`ifdef INLINE_A //verilator inline_module
`else //verilator no_inline_module
`endif
input clk;
integer cyc=1;
ifc itop1a();
ifc itop1b();
ifc itop2a();
ifc itop2b();
wrapper c1 (.isuba(itop1a),
.isubb(itop1b),
.i_valuea(14),
.i_valueb(15));
wrapper c2 (.isuba(itop2a),
.isubb(itop2b),
.i_valuea(24),
.i_valueb(25));
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==20) begin
if (itop1a.value != 14) $stop;
if (itop1b.value != 15) $stop;
if (itop2a.value != 24) $stop;
if (itop2b.value != 25) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module wrapper
(
ifc isuba,
ifc isubb,
input integer i_valuea,
input integer i_valueb
);
`ifdef INLINE_B //verilator inline_module
`else //verilator no_inline_module
`endif
lower subsuba (.isub(isuba), .i_value(i_valuea));
lower subsubb (.isub(isubb), .i_value(i_valueb));
endmodule
module lower
(
ifc isub,
input integer i_value
);
`ifdef INLINE_C //verilator inline_module
`else //verilator no_inline_module
`endif
always @* begin
isub.value = i_value;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); int n; string s; int finish_x, finish_y; cin >> n >> s >> finish_x >> finish_y; if (n < abs(finish_x) + abs(finish_y) || n % 2 != (abs(finish_x) + abs(finish_y)) % 2) { cout << -1; return 0; } vector<int> dx(n + 1), dy(n + 1); dx[n] = dy[n] = 0; map<char, pair<int, int>> m; m[ U ] = {0, 1}; m[ D ] = {0, -1}; m[ L ] = {-1, 0}; m[ R ] = {1, 0}; for (int i = n - 1; i >= 0; --i) { auto &[cdx, cdy] = m[s[i]]; dx[i] = dx[i + 1] + cdx; dy[i] = dy[i + 1] + cdy; } vector<int> x(n + 1), y(n + 1); x[0] = y[0] = 0; for (int i = 0; i < n; ++i) { auto [cdx, cdy] = m[s[i]]; x[i + 1] = x[i] + cdx; y[i + 1] = y[i] + cdy; } int l = -1, r = n; while (r - l > 1) { int m = (l + r) / 2; bool good = false; for (int i = 0; i <= n - m; ++i) { int u = x[i] + dx[i + m]; int v = y[i] + dy[i + m]; if (abs(finish_x - u) + abs(finish_y - v) <= m) { good = true; break; } } if (good) r = m; else l = m; } cout << r; } |
///////////////////////////////////////////////////////////////////////////////
/// Andrew Mattheisen
/// Zhiyang Ong
///
/// EE-577b 2007 fall
/// VITERBI DECODER
/// bmu module
///
///////////////////////////////////////////////////////////////////////////////
module bmu (cx0, cx1, bm0, bm1, bm2, bm3, bm4, bm5, bm6, bm7);
// outputs
output [1:0] bm0, bm1, bm2, bm3, bm4, bm5, bm6, bm7;
// inputs
input cx0, cx1;
// registers
reg [1:0] bm0, bm1, bm2, bm3, bm4, bm5, bm6, bm7;
always@ (cx0 or cx1)
begin
if (cx0==0 && cx1==0)
begin
bm0 <= 2'd0; // this is going from 00 to 00
bm1 <= 2'd2; // this is going from 00 to 10
bm2 <= 2'd2; // this is going from 01 to 00
bm3 <= 2'd0; // this is going from 01 to 10
bm4 <= 2'd1; // this is going from 10 to 01
bm5 <= 2'd1; // this is going from 10 to 11
bm6 <= 2'd1; // this is going from 11 to 01
bm7 <= 2'd1; // this is going from 11 to 11
end
else if (cx0==0 && cx1==1)
begin
bm0 <= 2'd1; // this is going from 00 to 00
bm1 <= 2'd1; // this is going from 00 to 10
bm2 <= 2'd1; // this is going from 01 to 00
bm3 <= 2'd1; // this is going from 01 to 10
bm4 <= 2'd2; // this is going from 10 to 01
bm5 <= 2'd0; // this is going from 10 to 11
bm6 <= 2'd0; // this is going from 11 to 01
bm7 <= 2'd2; // this is going from 11 to 11
end
else if (cx0==1 && cx1==0)
begin
bm0 <= 2'd1; // this is going from 00 to 00
bm1 <= 2'd1; // this is going from 00 to 10
bm2 <= 2'd1; // this is going from 01 to 00
bm3 <= 2'd1; // this is going from 01 to 10
bm4 <= 2'd0; // this is going from 10 to 01
bm5 <= 2'd2; // this is going from 10 to 11
bm6 <= 2'd2; // this is going from 11 to 01
bm7 <= 2'd0; // this is going from 11 to 11
end
else // if (cx0==1 && cx1==1)
begin
bm0 <= 2'd2; // this is going from 00 to 00
bm1 <= 2'd0; // this is going from 00 to 10
bm2 <= 2'd0; // this is going from 01 to 00
bm3 <= 2'd2; // this is going from 01 to 10
bm4 <= 2'd1; // this is going from 10 to 01
bm5 <= 2'd1; // this is going from 10 to 11
bm6 <= 2'd1; // this is going from 11 to 01
bm7 <= 2'd1; // this is going from 11 to 11
end
end // always @ (posedge clk)
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR4BB_1_V
`define SKY130_FD_SC_LS__OR4BB_1_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog wrapper for or4bb with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__or4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__or4bb_1 (
X ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__or4bb base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__or4bb_1 (
X ,
A ,
B ,
C_N,
D_N
);
output X ;
input A ;
input B ;
input C_N;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__or4bb base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR4BB_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFXTP_2_V
`define SKY130_FD_SC_MS__SDFXTP_2_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog wrapper for sdfxtp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__sdfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sdfxtp_2 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sdfxtp_2 (
Q ,
CLK,
D ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFXTP_2_V
|
#include <bits/stdc++.h> int main(void) { int b_cost, money, b_number; scanf( %d %d %d , &b_cost, &money, &b_number); int total_cost; int loan = 0; total_cost = b_cost; for (int i = 2; i <= b_number; i++) { total_cost += i * b_cost; } if (money < total_cost) { loan = total_cost - money; } printf( %d , loan); return 0; } |
// megafunction wizard: %ALTCLKCTRL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altclkctrl
// ============================================================
// File Name: PH2_CLK.v
// Megafunction Name(s):
// altclkctrl
//
// Simulation Library Files(s):
// cycloneii
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module PH2_CLK (
inclk,
outclk)/* synthesis synthesis_clearbox = 1 */;
input inclk;
output outclk;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: clock_inputs NUMERIC "1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION STRING "OFF"
// Retrieval info: CONSTANT: clock_type STRING "Global Clock"
// Retrieval info: USED_PORT: inclk 0 0 0 0 INPUT NODEFVAL "inclk"
// Retrieval info: USED_PORT: outclk 0 0 0 0 OUTPUT NODEFVAL "outclk"
// Retrieval info: CONNECT: @clkselect 0 0 2 0 GND 0 0 2 0
// Retrieval info: CONNECT: @ena 0 0 0 0 VCC 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 3 1 GND 0 0 3 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk 0 0 0 0
// Retrieval info: CONNECT: outclk 0 0 0 0 @outclk 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL PH2_CLK.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL PH2_CLK.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PH2_CLK.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PH2_CLK.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PH2_CLK_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL PH2_CLK_bb.v TRUE
// Retrieval info: LIB_FILE: cycloneii
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast,no-stack-protector,unroll-loops,fast-math ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4.1,sse4.2,avx,avx2,popcnt,tune=native ) static int a[100001], n, m, l, r, x, cnt; static bool type; inline static int read() { register int x = 0; static char ch = getchar(); while (ch < 0 || ch > 9 ) ch = getchar(); while (ch >= 0 && ch <= 9 ) x = (x << 1) + (x << 3) + (ch ^ 48), ch = getchar(); return x; } signed main(void) { n = read(), m = read(); for (register int i = 1; i <= n; ++i) a[i] = read(); for (; m--;) { type = (read() == 1); l = read(), r = read(), x = read(); if (type) for (register int i = l; i <= r; ++i) a[i] -= (a[i] > x) ? x : 0; else { cnt = 0; for (register int i = l; i <= r; ++i) cnt += (a[i] == x); printf( %d n , cnt); } } } |
#include <bits/stdc++.h> using namespace std; int gcd(int a, int b) { int c; while (a != 0) { c = a; a = b % a; b = c; } return b; } int main() { ios_base::sync_with_stdio(0); int n, m, b = 0; cin >> n >> m; vector<vector<int> > arr(n, vector<int>(4, 0)); for (int i = 0; i < n; i++) { if (b < m) { b++; arr[i][0] = b; } if (b < m) { b++; arr[i][3] = b; } } for (int i = 0; i < n; i++) { if (b < m) { b++; arr[i][1] = b; } if (b < m) { b++; arr[i][2] = b; } } for (int i = 0; i < n; i++) { if (arr[i][1] != 0) cout << arr[i][1] << ; if (arr[i][0] != 0) cout << arr[i][0] << ; if (arr[i][2] != 0) cout << arr[i][2] << ; if (arr[i][3] != 0) cout << arr[i][3] << ; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MAJ3_PP_SYMBOL_V
`define SKY130_FD_SC_HS__MAJ3_PP_SYMBOL_V
/**
* maj3: 3-input majority vote.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__maj3 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__MAJ3_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { string s; int l, i, j, k; cin >> s; for (i = 1; i < s.size() - 1; i++) { if (s[i] == A && ((s[i + 1] == B && s[i - 1] == C ) || (s[i - 1] == B && s[i + 1] == C ))) { printf( YES n ); return 0; } else if (s[i] == B && ((s[i + 1] == A && s[i - 1] == C ) || (s[i - 1] == A && s[i + 1] == C ))) { printf( YES n ); return 0; } else if (s[i] == C && ((s[i + 1] == B && s[i - 1] == A ) || (s[i - 1] == B && s[i + 1] == A ))) { printf( YES n ); return 0; } } printf( NO n ); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR3B_TB_V
`define SKY130_FD_SC_HS__OR3B_TB_V
/**
* or3b: 3-input OR, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__or3b.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C_N;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C_N = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C_N = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 B = 1'b1;
#160 C_N = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 B = 1'b0;
#260 C_N = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 C_N = 1'b1;
#380 B = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 C_N = 1'bx;
#480 B = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hs__or3b dut (.A(A), .B(B), .C_N(C_N), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR3B_TB_V
|
#include <bits/stdc++.h> #pragma GCC optimize( O999 ) using namespace std; int main() { ios::sync_with_stdio(0); cout << INTERCAL ; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EBUFN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__EBUFN_BEHAVIORAL_PP_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__ebufn (
VPWR,
VGND,
Z ,
A ,
TE_B
);
// Module ports
input VPWR;
input VGND;
output Z ;
input A ;
input TE_B;
// Local signals
wire u_vpwr_vgnd0_out_A ;
wire u_vpwr_vgnd1_out_teb;
// Name Output Other arguments
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_A , A, VPWR, VGND );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd1 (u_vpwr_vgnd1_out_teb, TE_B, VPWR, VGND );
bufif0 bufif00 (Z , u_vpwr_vgnd0_out_A, u_vpwr_vgnd1_out_teb);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__EBUFN_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int INF = 0x6fffffff; const int MINF = 0x80000000; const int mod = 1000000007; const int cons = 100001; const double pi = 3.141592653589793; int dy2[2] = {1, 0}; int dx2[2] = {0, -1}; int dy1[2] = {0, 1}; int dx1[2] = {1, 0}; int n, m; int main() { vector<vector<bool> > M; vector<vector<int> > km, lm; scanf( %d%d , &n, &m); M.resize(n + 1, vector<bool>(m + 1, false)); km.resize(n + 1, vector<int>(m + 1, -1)); lm.resize(n + 1, vector<int>(m + 1, -1)); vector<pair<int, int> > pos[10005]; queue<pair<int, int> > qu; qu.push(make_pair(1, 1)); km[1][1] = 2; pos[2].push_back(make_pair(1, 1)); while (!qu.empty()) { int y = qu.front().first; int x = qu.front().second; qu.pop(); for (int i = 0; i < 2; i++) { int ty = y + dy1[i]; int tx = x + dx1[i]; if (ty < 1 || ty > n || tx < 1 || tx > m) continue; if (km[ty][tx] != -1) continue; km[ty][tx] = km[y][x] + 1; pos[km[ty][tx]].push_back(make_pair(ty, tx)); qu.push(make_pair(ty, tx)); } } qu.push(make_pair(1, m)); lm[1][m] = 2; while (!qu.empty()) { int y = qu.front().first; int x = qu.front().second; qu.pop(); for (int i = 0; i < 2; i++) { int ty = y + dy2[i]; int tx = x + dx2[i]; if (ty < 1 || ty > n || tx < 1 || tx > m) continue; if (lm[ty][tx] != -1) continue; lm[ty][tx] = lm[y][x] + 1; qu.push(make_pair(ty, tx)); } } map<int, int> K, L; int k; scanf( %d , &k); for (int i = 1; i <= k; i++) { int x; scanf( %d , &x); K[x]++; } int l; scanf( %d , &l); for (int i = k + 1; i <= l + k; i++) { int x; scanf( %d , &x); L[x]++; } for (int i = n + m; i >= 2; i--) { for (int j = 0; j < pos[i].size(); j++) { int y = pos[i][j].first; int x = pos[i][j].second; int lvl = lm[y][x]; auto it = K.lower_bound(i); auto it2 = L.lower_bound(lvl); if (it == K.end() && it2 == L.end()) { puts( NO ); return 0; } else if (it == K.end()) { it2->second--; if (it2->second == 0) { L.erase(it2); } } else if (it2 == L.end()) { it->second--; if (it->second == 0) { K.erase(it); } } else { it2->second--; if (it2->second == 0) { L.erase(it2); } } } } puts( YES ); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int x, y, n, a, b; cin >> x >> y >> n; long double d = 10000000000, t, q; t = (long double)x / y; for (int i = 1; i <= n; i++) { q = abs(t - floor(t * i) / i); if (q < d) { a = floor(t * i); b = i; d = q; } q = abs(t - ceil(t * i) / i); if (q < d) { a = ceil(t * i); b = i; d = q; } } cout << a << / << b << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 100000 + 5; const double EPS = 1e-3; int n; int t[MAXN]; int g(double q) { bool ok = true; for (int i = 1; i < n; i++) if (fabs(double(t[i] - t[i - 1] * q)) > EPS) ok = false; if (ok) return 0; ok = true; for (int i = 2; i < n; i++) if (fabs(double(t[i] - t[i - 1] * q)) > EPS) ok = false; if (ok) return 1; ok = true; int prev = t[0]; for (int i = 1; i < n; i++) if (fabs(double(t[i] - prev * q)) > EPS) { if (!ok) return 2; ok = false; } else prev = t[i]; return 1; } int f() { if (n == 1) return 0; double q1 = 0, q2 = 0; if (t[0] != 0) q1 = double(t[1]) / t[0]; if (t[n - 2] != 0) q2 = double(t[n - 1]) / t[n - 2]; return min(g(q1), g(q2)); } int main() { scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d , &t[i]); printf( %d n , f()); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FILL_2_V
`define SKY130_FD_SC_HD__FILL_2_V
/**
* fill: Fill cell.
*
* Verilog wrapper for fill with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__fill.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__fill_2 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__fill base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__fill_2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__fill base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__FILL_2_V
|
#include <bits/stdc++.h> using namespace std; struct node { int days; int index; }; bool compare(node lhs, node rhs) { return (lhs.days < rhs.days); } int main() { int n, k; int sum = 0; scanf( %d%d , &n, &k); node a[n + 1]; for (int i = 1; i <= n; i++) { scanf( %d , &a[i].days); a[i].index = i; } sort(a + 1, a + n + 1, compare); int i = 1; sum = a[i].days; while (sum <= k) { i++; if (i <= n) sum += (a[i].days); else break; } printf( %d n , i - 1); if (i != 1) { for (int j = 1; j < i; j++) printf( %d , a[j].index); printf( n ); } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A222OI_FUNCTIONAL_V
`define SKY130_FD_SC_LS__A222OI_FUNCTIONAL_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__a222oi (
Y ,
A1,
A2,
B1,
B2,
C1,
C2
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire nand2_out ;
wire and0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
nand nand2 (nand2_out , C2, C1 );
and and0 (and0_out_Y, nand0_out, nand1_out, nand2_out);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A222OI_FUNCTIONAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAPMET1_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__TAPMET1_BEHAVIORAL_PP_V
/**
* tapmet1: Tap cell with isolated power and ground connections.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__tapmet1 (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAPMET1_BEHAVIORAL_PP_V |
module sr_04(echo,clk,rst_n,distance_reg);
input echo,clk,rst_n;
output distance_reg;
reg[9:0]distance_reg,cnt;
wire start,finish;
reg echo_reg1,echo_reg2;
parameter idle=2'b00;
parameter state1=2'b01;
parameter state2=2'b10;
reg [1:0]state;
assign start=echo_reg1&~echo_reg2; //posedge
assign finish=~echo_reg1&echo_reg2; //negedge
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)begin echo_reg1<=0;echo_reg2<=0;end
else begin echo_reg1<=echo;echo_reg2<=echo_reg1;end
if(!rst_n)begin state<=idle;cnt<=0;end
else begin
case(state)
idle: begin
if(start)begin state<=state1;end
else begin state<=idle;end
end
state1:begin
if(finish)begin state<=state2;end
else begin cnt<=cnt+1'b1;state<=state1;end
end
state2:begin
cnt<=0;
distance_reg<=cnt;
state<=idle;
end
default: state<=idle;
endcase
end
end
endmodule |
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.4 (win64) Build Tue Nov 18 18:29:27 MST 2014
// Date : Tue Jun 30 15:18:15 2015
// Host : Vangelis-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/Vfor/Documents/GitHub/Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/MemScore/MemScore_stub.v
// Design : MemScore
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tcsg324-3
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "dist_mem_gen_v8_0,Vivado 2014.4" *)
module MemScore(a, clk, spo)
/* synthesis syn_black_box black_box_pad_pin="a[7:0],clk,spo[11:0]" */;
input [7:0]a;
input clk;
output [11:0]spo;
endmodule
|
`include "defines.v"
module div (
input wire clk,
input wire rst,
input wire signed_div_i,
input wire[`RegBus] opdata1_i, // 被除数
input wire[`RegBus] opdata2_i, // 除数
input wire start_i,
input wire annul_i,
output reg[`DoubleRegBus] result_o,
output reg result_ready_o
);
wire[32:0] div_temp;
reg[5:0] cnt;
reg[`DoubleRegBus] dividend;
reg[1:0] state; // DivFree, DivOn, DivByZero, DivEnd 状态
reg[`RegBus] divisor;
wire[`RegBus] temp_op1;
wire[`RegBus] temp_op2;
// reg[1:0] new_state;
assign div_temp = dividend[63:31] - divisor;
// always @(posedge clk) begin
// if (rst == `RstEnable) begin
// state <= `DivFree;
// new_state <= `DivFree;
// end
// else begin
// state <= new_state;
// end
// end
assign temp_op1 = (signed_div_i == `DivSigned && opdata1_i[31] == 1'b1) ? (~opdata1_i + 1) : opdata1_i;
assign temp_op2 = (signed_div_i == `DivSigned && opdata2_i[31] == 1'b1) ? (~opdata2_i + 1) : opdata2_i;
// always @(*) begin
always @(posedge clk) begin
if (rst == `RstEnable) begin
state <= `DivFree;
result_ready_o <= `DivResultNotReady;
result_o <= {`ZeroWord, `ZeroWord};
end
else begin
case (state)
`DivFree: begin
if (start_i == `DivStart && annul_i == `DivNotAnnul) begin
if (opdata2_i == `ZeroWord) begin
state <= `DivByZero;
end
else begin
state <= `DivOn;
// new_state <= `DivOn;
cnt <= 0;
// if (signed_div_i == `DivSigned && opdata1_i[31] == 1'b1) begin
// temp_op1 <= ~opdata1_i + 1;
// end
// else begin
// temp_op1 <= opdata1_i;
// end
// if (signed_div_i == `DivSigned && opdata2_i[31] == 1'b1) begin
// temp_op2 <= ~opdata2_i + 1;
// end
// else begin
// temp_op2 <= opdata2_i;
// end
// test
// temp_op1 <= 32'h1111;
// temp_op2 <= 32'h2222;
dividend <= {`ZeroWord, temp_op1};
divisor <= temp_op2;
end
end
else begin
result_ready_o <= `DivResultNotReady;
result_o <= {`ZeroWord, `ZeroWord};
end
end
`DivOn: begin
if (annul_i == `DivNotAnnul) begin
if (cnt != 32) begin // 试商法还未结束
if (div_temp[32] == 1'b1) begin
// 表示 (minuted - n) 的结果小于 0
// dividend 左移一位
dividend <= {dividend[62:0], 1'b0};
end
else begin
dividend <= {div_temp[31:0], dividend[30:0], 1'b1};
end
cnt <= cnt + 1;
end
else begin // 试商法结束
if (signed_div_i == `DivSigned && (opdata1_i[31] ^ opdata2_i[31]) == 1'b1) begin
dividend[31:0] <= ~dividend[31:0] + 1;
end
if (signed_div_i == `DivSigned && opdata1_i[31] == 1'b1) begin
dividend[63:32] <= ~dividend[63:32] + 1;
end
state <= `DivEnd;
cnt <= 0;
end
end
else begin
state <= `DivFree;
end
end
`DivByZero: begin
dividend <= {`ZeroWord, `ZeroWord};
state <= `DivEnd;
end
`DivEnd: begin
result_o <= {dividend[63:32], dividend[31:0]};
result_ready_o <= `DivResultReady;
if (start_i == `DivNotStart) begin
state <= `DivFree;
result_ready_o <= `DivResultNotReady;
result_o <= {`ZeroWord, `ZeroWord};
end
end
endcase
end
end
endmodule |
#include <bits/stdc++.h> using namespace std; int N; char s[500010]; int c[30][500010]; int then(int x) { return x & -x; } void in(int o, int x, int k) { while (x <= N) { c[o][x] += k; x += then(x); } } int out(int o, int x) { int re = 0; while (x > 0) { re += c[o][x]; x -= then(x); } return re; } int main() { int Q; scanf( %s%d , s + 1, &Q); N = strlen(s + 1); for (int i = 1; i <= N; i++) in(s[i] - a , i, 1); for (int i = 1; i <= Q; i++) { int o; scanf( %d , &o); if (o == 1) { int k; char m; scanf( %d %c , &k, &m); in(s[k] - a , k, -1); in(m - a , k, 1); s[k] = m; } else { int x, y; scanf( %d%d , &x, &y); int give = 0; for (int i = 0; i <= 25; i++) if (out(i, y) - out(i, x - 1)) give++; printf( %d n , give); } } return 0; } |
#include <bits/stdc++.h> using namespace std; void solve() { long long n, k; cin >> n >> k; string s; cin >> s; vector<char> base(k, ? ); for (long long i = 0; i < n; i++) { if (s[i] == 1 ) { if (base[i % k] == 1 ) { continue; } if (base[i % k] == 0 ) { cout << NO << endl; return; } if (base[i % k] == ? ) { base[i % k] = 1 ; } } else if (s[i] == 0 ) { if (base[i % k] == 0 ) { continue; } if (base[i % k] == 1 ) { cout << NO << endl; return; } if (base[i % k] == ? ) { base[i % k] = 0 ; } } else { } } long long zero = 0, one = 0; for (long long i = 0; i < k; i++) { if (base[i] == 0 ) zero++; else if (base[i] == 1 ) one++; } if (one <= k / 2 && zero <= k / 2) cout << YES << endl; else { cout << NO << endl; } } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t = 1; cin >> t; while (t--) { solve(); } return 0; } |
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
// IMPORTANT: This requires an input text file named "rf1.fill"
// Non-synthesizable behavioral RTL model for the instruction memory
module instr_mem (instr_addr,instr,enb);
// load instr - take data out
// store - put data into the memory
// ===============================================================
// Output signals...
// Instruction obtained/addressed from instr_addr
output [0:31] instr;
// ===============================================================
// Input signals
// Address where the instruction is located
input [0:31] instr_addr;
/**
* Enable signal to indicate that the instruction memory shall be
* from an input text file named "rf1.fill"
*/
input enb;
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Definitions for the constants the instruction memory
// parameter PARAM_NAME = VALUE;
// ===============================================================
// Declare "reg" signals:
reg [0:31] instr; // Output signals
/**
* (256 word) depth and (31 bits per word) width
*/
reg [0:31] instr_mem [0:255]; // Store the data here
// Store instruction address in the instruction memory
reg [0:7] temp_instr_addr;
// ===============================================================
initial
begin
/**
* Read the input data for r from an input file named
* "rf1.fill"'
*
* The system task to read data from the file must be placed
* in an INITIAL block
*/
$readmemh("rf1.fill",instr_mem);
end
// A change in the instruction address activates this...
always @(instr_addr or enb)
begin
// If the instruction memory is enabled
if(enb)
begin
// Read the next instruction from the instruction memory
//temp_instr_addr<=instr_addr+3'd4;
//---------------------instr<=instr_mem[temp_instr_addr];
//temp_instr_addr<=temp_instr_addr>>2;
instr<=instr_mem[instr_addr];
//---------------------instr<=instr_mem[8'd5];
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> void chkmax(T& x, T y) { x = (x > y ? x : y); } template <class T> void chkmin(T& x, T y) { x = (x < y ? x : y); } int a[6], b[6]; int main() { for (int i = 0; i < (int)(4); ++i) scanf( %d%d , &a[i], &b[i]); for (int i = 0; i < (int)(2); ++i) { bool win = 1; int j = i ^ 1; for (int k = 0; k < (int)(2); ++k) { int p = k ^ 1; k += 2, p += 2; if (!(a[i] > b[k] && b[j] > a[p])) win = 0; k -= 2; } if (win) { printf( Team 1 n ); return 0; } } bool beat[2]; beat[0] = beat[1] = 0; for (int i = 0; i < (int)(2); ++i) { bool win = 1; int j = i ^ 1; i += 2, j += 2; for (int k = 0; k < (int)(2); ++k) { int p = k ^ 1; if (a[i] > b[k] && b[j] > a[p]) { beat[k] = 1; } } i -= 2; } if (beat[0] && beat[1]) { printf( Team 2 n ); return 0; } printf( Draw n ); return 0; } |
`timescale 1 ns/100 ps
// Version: 8.5 8.5.0.34
module dmem(WD,RD,WEN,REN,WADDR,RADDR,RWCLK,RESET);
input [7:0] WD;
output [7:0] RD;
input WEN, REN;
input [9:0] WADDR, RADDR;
input RWCLK, RESET;
wire VCC, GND;
VCC VCC_1_net(.Y(VCC));
GND GND_1_net(.Y(GND));
RAM4K9 dmem_R0C1(.ADDRA11(GND), .ADDRA10(GND), .ADDRA9(
WADDR[9]), .ADDRA8(WADDR[8]), .ADDRA7(WADDR[7]), .ADDRA6(
WADDR[6]), .ADDRA5(WADDR[5]), .ADDRA4(WADDR[4]), .ADDRA3(
WADDR[3]), .ADDRA2(WADDR[2]), .ADDRA1(WADDR[1]), .ADDRA0(
WADDR[0]), .ADDRB11(GND), .ADDRB10(GND), .ADDRB9(RADDR[9])
, .ADDRB8(RADDR[8]), .ADDRB7(RADDR[7]), .ADDRB6(RADDR[6]),
.ADDRB5(RADDR[5]), .ADDRB4(RADDR[4]), .ADDRB3(RADDR[3]),
.ADDRB2(RADDR[2]), .ADDRB1(RADDR[1]), .ADDRB0(RADDR[0]),
.DINA8(GND), .DINA7(GND), .DINA6(GND), .DINA5(GND),
.DINA4(GND), .DINA3(WD[7]), .DINA2(WD[6]), .DINA1(WD[5]),
.DINA0(WD[4]), .DINB8(GND), .DINB7(GND), .DINB6(GND),
.DINB5(GND), .DINB4(GND), .DINB3(GND), .DINB2(GND),
.DINB1(GND), .DINB0(GND), .WIDTHA0(GND), .WIDTHA1(VCC),
.WIDTHB0(GND), .WIDTHB1(VCC), .PIPEA(GND), .PIPEB(VCC),
.WMODEA(GND), .WMODEB(GND), .BLKA(WEN), .BLKB(REN), .WENA(
GND), .WENB(VCC), .CLKA(RWCLK), .CLKB(RWCLK), .RESET(
RESET), .DOUTA8(), .DOUTA7(), .DOUTA6(), .DOUTA5(),
.DOUTA4(), .DOUTA3(), .DOUTA2(), .DOUTA1(), .DOUTA0(),
.DOUTB8(), .DOUTB7(), .DOUTB6(), .DOUTB5(), .DOUTB4(),
.DOUTB3(RD[7]), .DOUTB2(RD[6]), .DOUTB1(RD[5]), .DOUTB0(
RD[4]));
RAM4K9 dmem_R0C0(.ADDRA11(GND), .ADDRA10(GND), .ADDRA9(
WADDR[9]), .ADDRA8(WADDR[8]), .ADDRA7(WADDR[7]), .ADDRA6(
WADDR[6]), .ADDRA5(WADDR[5]), .ADDRA4(WADDR[4]), .ADDRA3(
WADDR[3]), .ADDRA2(WADDR[2]), .ADDRA1(WADDR[1]), .ADDRA0(
WADDR[0]), .ADDRB11(GND), .ADDRB10(GND), .ADDRB9(RADDR[9])
, .ADDRB8(RADDR[8]), .ADDRB7(RADDR[7]), .ADDRB6(RADDR[6]),
.ADDRB5(RADDR[5]), .ADDRB4(RADDR[4]), .ADDRB3(RADDR[3]),
.ADDRB2(RADDR[2]), .ADDRB1(RADDR[1]), .ADDRB0(RADDR[0]),
.DINA8(GND), .DINA7(GND), .DINA6(GND), .DINA5(GND),
.DINA4(GND), .DINA3(WD[3]), .DINA2(WD[2]), .DINA1(WD[1]),
.DINA0(WD[0]), .DINB8(GND), .DINB7(GND), .DINB6(GND),
.DINB5(GND), .DINB4(GND), .DINB3(GND), .DINB2(GND),
.DINB1(GND), .DINB0(GND), .WIDTHA0(GND), .WIDTHA1(VCC),
.WIDTHB0(GND), .WIDTHB1(VCC), .PIPEA(GND), .PIPEB(VCC),
.WMODEA(GND), .WMODEB(GND), .BLKA(WEN), .BLKB(REN), .WENA(
GND), .WENB(VCC), .CLKA(RWCLK), .CLKB(RWCLK), .RESET(
RESET), .DOUTA8(), .DOUTA7(), .DOUTA6(), .DOUTA5(),
.DOUTA4(), .DOUTA3(), .DOUTA2(), .DOUTA1(), .DOUTA0(),
.DOUTB8(), .DOUTB7(), .DOUTB6(), .DOUTB5(), .DOUTB4(),
.DOUTB3(RD[3]), .DOUTB2(RD[2]), .DOUTB1(RD[1]), .DOUTB0(
RD[0]));
endmodule
|
#include <bits/stdc++.h> using namespace std; inline int read() { int x = 0, f = 1; char c = getchar(); while (!isdigit(c)) { if (c == - ) f = -1; c = getchar(); } while (isdigit(c)) { x = (x << 1) + (x << 3) + (c ^ 48); c = getchar(); } return f == 1 ? x : -x; } const int N = 3e5 + 4; long long ans = 0; int n, a[N], mx[N], mn[N], cnt[N << 1]; inline void solve(int l, int r) { if (l == r) return ++ans, void(); int mid = l + r >> 1; mx[mid] = mn[mid] = a[mid]; mx[mid + 1] = mn[mid + 1] = a[mid + 1]; for (int i = mid + 2; i <= r; i++) { mx[i] = (mx[i - 1] > a[i] ? mx[i - 1] : a[i]); mn[i] = (mn[i - 1] > a[i] ? a[i] : mn[i - 1]); } for (int i = mid - 1; i >= l; i--) { mx[i] = (mx[i + 1] > a[i] ? mx[i + 1] : a[i]); mn[i] = (mn[i + 1] > a[i] ? a[i] : mn[i + 1]); } int ll = mid, rr = mid; for (int i = mid + 1, x; i <= r; i++) { x = i - mx[i] + mn[i]; if (x >= l && x <= mid && mx[x] < mx[i] && mn[x] > mn[i]) ans++; while (ll >= l && mx[ll] < mx[i]) { cnt[N + mn[ll] - ll]++; ll--; } while (rr > ll && mn[rr] > mn[i]) { cnt[N + mn[rr] - rr]--; rr--; } ans += cnt[N + mx[i] - i]; } while (rr != ll) { cnt[N + mn[rr] - rr]--; rr--; } ll = rr = mid + 1; for (int i = mid, x; i >= l; i--) { x = mx[i] - mn[i] + i; if (x > mid && x <= r && mx[x] < mx[i] && mn[x] > mn[i]) ans++; while (rr <= r && mx[rr] < mx[i]) { cnt[mn[rr] + rr]++; rr++; } while (ll < rr && mn[ll] > mn[i]) { cnt[mn[ll] + ll]--; ll++; } ans += cnt[mx[i] + i]; } while (ll != rr) { cnt[mn[ll] + ll]--; ll++; } solve(l, mid); solve(mid + 1, r); } int main() { n = read(); for (int i = 1, u, v; i <= n; i++) { u = read(); v = read(); a[u] = v; } solve(1, n); cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 500010; int n, m; struct edge { int a, b, c, t; } e[N]; inline bool operator<(const edge &a, const edge &b) { return a.c < b.c; } struct union_find { int f[N], h[N], sz[N], cnt; struct oper { int x, fx, hx, szx, tc; } op[N * 2]; int l; void init() { l = 0, cnt = n; for (int i = 1; i <= n; i++) f[i] = i, h[i] = 0, sz[i] = 1; } int find(int x) { return f[x] == x ? x : find(f[x]); } void rewind(int t) { for (int i = l; i >= t + 1; i--) { int x = op[i].x; f[x] = op[i].fx, h[x] = op[i].hx; sz[x] = op[i].szx; cnt = op[i].tc; } l = t; } void merge(int a, int b) { int fa = find(a), fb = find(b); if (fa != fb) { if (h[fa] > h[fb]) swap(fa, fb); op[++l] = (oper){fa, f[fa], h[fa], sz[fa], cnt}, op[++l] = (oper){fb, f[fb], h[fb], sz[fb], cnt}; if (sz[fa] && sz[fb]) cnt -= 2; f[fa] = fb; h[fb] = max(h[fb], h[fa] + 1); sz[fb] ^= sz[fa]; } } } T; int j = 1, ans[N]; vector<int> ed[N << 2]; namespace seg { int a, b, c; void add(int x, int l, int r) { if (a <= l && r <= b) ed[x].push_back(c); else { if (a <= ((l + r) >> 1)) add((x << 1), l, ((l + r) >> 1)); if (b > ((l + r) >> 1)) add(((x << 1) | 1), ((l + r) >> 1) + 1, r); } } } // namespace seg void solve(int x, int l, int r) { int len = ed[x].size(), l0 = T.l; for (int i = 0; i < len; i++) T.merge(e[ed[x][i]].a, e[ed[x][i]].b); if (l == r) { ans[l] = ans[l + 1]; while (j <= m && T.cnt) { if (e[j].t <= l) { seg::a = e[j].t, seg::b = l - 1, seg::c = j; if (seg::a <= seg::b) seg::add(1, 1, m); T.merge(e[j].a, e[j].b); ans[l] = e[j].c; } j++; } if (T.cnt) ans[l] = -1; } else solve(((x << 1) | 1), ((l + r) >> 1) + 1, r), solve((x << 1), l, ((l + r) >> 1)); T.rewind(l0); } int main() { scanf( %d%d , &n, &m); T.init(); for (int i = 1; i <= m; i++) scanf( %d%d%d , &e[i].a, &e[i].b, &e[i].c), e[i].t = i; sort(e + 1, e + m + 1); solve(1, 1, m); for (int i = 1; i <= m; i++) printf( %d n , ans[i]); return 0; } |
#include <bits/stdc++.h> using namespace std; int Set(int N, int pos) { return N = N | (1 << pos); } int reset(int N, int pos) { return N = N & ~(1 << pos); } bool check(long long N, int pos) { return (bool)(N & (1LL << pos)); } int n, m, l, r; string s; char c1, c2; int main() { cin >> n >> m; cin >> s; for (int i = 1; i <= m; i++) { cin >> l >> r >> c1 >> c2; l--, r--; for (int j = l; j <= r; j++) { if (s[j] == c1) s[j] = c2; } } cout << s << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; inline void pisz(int n) { printf( %d n , n); } int dl[1000][1000]; int dr[1000][1000]; int ul[1000][1000]; int ur[1000][1000]; int g[1000][1000]; int n, m; int recdl(int i, int j) { if (i < 0 || i == n || j < 0 || j == m) return -1001001001; if (i == n - 1 && j == 0) return g[i][j]; if (dl[i][j] != -1) return dl[i][j]; return dl[i][j] = g[i][j] + (recdl(i + 1, j) < recdl(i, j - 1) ? recdl(i, j - 1) : recdl(i + 1, j)); } int recdr(int i, int j) { if (i < 0 || i == n || j < 0 || j == m) return -1001001001; if (i == n - 1 && j == m - 1) return g[i][j]; if (dr[i][j] != -1) return dr[i][j]; return dr[i][j] = g[i][j] + (recdr(i + 1, j) < recdr(i, j + 1) ? recdr(i, j + 1) : recdr(i + 1, j)); } int recul(int i, int j) { if (i < 0 || i == n || j < 0 || j == m) return -1001001001; if (i == 0 && j == 0) return g[i][j]; if (ul[i][j] != -1) return ul[i][j]; return ul[i][j] = g[i][j] + (recul(i - 1, j) < recul(i, j - 1) ? recul(i, j - 1) : recul(i - 1, j)); } int recur(int i, int j) { if (i < 0 || i == n || j < 0 || j == m) return -1001001001; if (i == 0 && j == m - 1) return g[i][j]; if (ur[i][j] != -1) return ur[i][j]; return ur[i][j] = g[i][j] + (recur(i - 1, j) < recur(i, j + 1) ? recur(i, j + 1) : recur(i - 1, j)); } int main() { cin >> n >> m; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) cin >> g[i][j]; memset(dl, -1, sizeof(dl)); memset(dr, -1, sizeof(dr)); memset(ul, -1, sizeof(ul)); memset(ur, -1, sizeof(ur)); int res = 0; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { int b1 = recul(i - 1, j) + recdl(i, j - 1); int a1 = recdr(i + 1, j) + recur(i, j + 1); int b2 = recul(i, j - 1) + recdl(i + 1, j); int a2 = recdr(i, j + 1) + recur(i - 1, j); res = (res < (b1 + a1 < b2 + a2 ? b2 + a2 : b1 + a1) ? (b1 + a1 < b2 + a2 ? b2 + a2 : b1 + a1) : res); } cout << res << endl; } |
#include <bits/stdc++.h> double const EPS = 3e-8; using namespace std; template <class T> T gcd(T a, T b) { return (b != 0 ? gcd<T>(b, a % b) : a); } template <class T> T lcm(T a, T b) { return (a / gcd<T>(a, b) * b); } struct debugger { template <typename T> debugger& operator,(const T& v) { cerr << v << t ; return *this; } } dbg; template <class A, class B> ostream& operator<<(ostream& o, const pair<A, B>& p) { return o << ( << p.first << , << p.second << ) ; } template <class T> ostream& operator<<(ostream& o, const vector<T>& v) { o << [ ; for (__typeof((v).end()) it = (v).begin(); it != (v).end(); ++it) o << *it << , ; return o << ] ; } template <class T> ostream& operator<<(ostream& o, const set<T>& v) { o << [ ; for (__typeof((v).end()) it = (v).begin(); it != (v).end(); ++it) o << *it << , ; return o << ] ; } template <class T> inline bool read(T& x) { int c = getchar(); int sgn = 1; while (~c && c < 0 || c > 9 ) { if (c == - ) sgn = -1; c = getchar(); } for (x = 0; ~c && 0 <= c && c <= 9 ; c = getchar()) x = x * 10 + c - 0 ; x *= sgn; return ~c; } int dx[] = {1, 0, -1, 0}; int dy[] = {0, 1, 0, -1}; const int NX = 1e6 + 10; int fromFront[NX], fromBack[NX]; string a, b; void solve(int cs) { cin >> a >> b; int asz = a.size(); int bsz = b.size(); int backIdx = bsz - 1; int cur = 0; for (int i = asz - 1; i >= 0; i--) { if (backIdx >= 0 && a[i] == b[backIdx]) { backIdx--; cur++; } fromBack[i] = cur; } int frontIdx = 0; cur = 0; for (int i = 0; i < asz; i++) { if (frontIdx < bsz && a[i] == b[frontIdx]) { frontIdx++; cur++; } fromFront[i] = cur; } int low = 0, high = 0; int ans = 0; while (high < asz) { int f = 0, b = 0; if (low > 0) f = fromFront[low - 1]; if (high + 1 < asz) b = fromBack[high + 1]; if (f + b >= bsz) { ans = max(ans, high - low + 1); } else { while (f + b < bsz && low <= high) { low++; f = fromFront[low - 1]; if (high + 1 < asz) b = fromBack[high + 1]; } } high++; } printf( %d n , ans); } int main() { int t = 1; for (int cs = 1; cs <= t; cs++) solve(cs); return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (clk);
input clk;
reg [2:0] a;
reg [2:0] b;
reg q;
f6 f6 (/*AUTOINST*/
// Outputs
.q (q),
// Inputs
.a (a[2:0]),
.b (b[2:0]),
.clk (clk));
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
a <= 3'b000;
b <= 3'b100;
end
if (cyc==2) begin
a <= 3'b011;
b <= 3'b001;
if (q != 1'b0) $stop;
end
if (cyc==3) begin
a <= 3'b011;
b <= 3'b011;
if (q != 1'b0) $stop;
end
if (cyc==9) begin
if (q != 1'b1) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module f6 (a, b, clk, q);
input [2:0] a;
input [2:0] b;
input clk;
output q;
reg out;
function func6;
reg result;
input [5:0] src;
begin
if (src[5:0] == 6'b011011) begin
result = 1'b1;
end
else begin
result = 1'b0;
end
func6 = result;
end
endfunction
wire [5:0] w6 = {a, b};
always @(posedge clk) begin
out <= func6(w6);
end
assign q = out;
endmodule
|
#include <bits/stdc++.h> uint32_t readu32() { int c; while ((c = getchar()) < 0 ) ; uint32_t n = c & 15U; while ((c = getchar()) >= 0 ) n = n * 10 + (c & 15U); return n; } uint64_t readu64() { int c; while ((c = getchar()) < 0 ) ; uint64_t n = c & 15U; while ((c = getchar()) >= 0 ) n = n * 10 + (c & 15U); return n; } int32_t read32() { int c; while ((c = getchar()) < - ) ; bool neg = c == - ; if (neg) c = getchar(); uint32_t n = c & 15U; while ((c = getchar()) >= 0 ) n = n * 10 + (c & 15U); return neg ? -(int32_t)n : n; } int64_t read64() { int c; while ((c = getchar()) < - ) ; bool neg = c == - ; if (neg) c = getchar(); uint64_t n = c & 15; while ((c = getchar()) >= 0 ) n = n * 10 + (c & 15U); return neg ? -(int64_t)n : n; } using namespace std; bool v[100005]; int p[100005]; int main() { ios_base::sync_with_stdio(0); int n = readu32(); for (int i = 1; i <= n; i++) p[i] = readu32(); int hub = 0, two = 0; bool hasodd = 0; for (int i = 1; i <= n; i++) { if (v[i]) continue; if (p[i] == i) hub = i; else if (p[p[i]] == i) two = i; else { int j = i; int cl = 0; for (;;) { v[j] = 1; j = p[j]; cl++; if (j == i) break; } if (cl & 1) hasodd = true; } } if (!hub && (hasodd || !two)) { cout << NO ; return 0; } printf( YES n ); if (hub) { for (int i = 1; i <= n; i++) if (i != hub) printf( %d %d n , i, hub); } else { memset(v, 0, sizeof(v)); int par[] = {two, p[two]}; v[par[0]] = v[par[1]] = 1; printf( %d %d n , par[0], par[1]); for (int i = 1; i <= n; i++) { if (v[i]) continue; int j = i, pa = 0; for (;; pa ^= 1) { v[j] = 1; printf( %d %d n , j, par[pa]); j = p[j]; if (j == i) break; } } } return 0; } |
Subsets and Splits