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#include <bits/stdc++.h> using namespace std; int report[105], folder[105]; int main() { int n; cin >> n; int k = 1, am = 0; for (int i = 1; i <= n; i++) cin >> report[i]; for (int i = 1; i <= n; i++) { if (report[i] < 0 && am == 2) { k++; folder[k]++; am = 1; } else { folder[k]++; if (report[i] < 0) am++; } } cout << k << endl; for (int i = 1; i <= k; i++) cout << folder[i] << ; return 0; } |
#include <bits/stdc++.h> using namespace std; long long i, j, n, t, sum = 0, k, c1 = 1; int main() { cin >> n; vector<string> c(n); vector<string> s(n); for (i = 0; i < n; i++) { cin >> c[i] >> s[i]; } for (i = 1; i < n; i++) { k = 0; for (j = i - 1; j >= 0; j--) { if (c[i] == c[j] && s[i] == s[j]) { k++; if (k != 0) { break; } } } if (k == 0) { c1++; } } cout << c1; } |
#include <bits/stdc++.h> #pragma GCC optimize( O2 ) using namespace std; const int N = 1e5 + 10; const long long mod = 1e9 + 7; const long long mod2 = 998244353; const int inf = 1e9; const int LOG = 22; long long pw(long long a, long long b, long long M) { return (!b ? 1 : (b & 1 ? (a * pw(a * a % M, b / 2, M)) % M : pw(a * a % M, b / 2, M))); } struct node { int mx1, mx2, cnt, lz; long long sum; node(int m1 = -inf, int m2 = -inf, int c = 0, int l = inf, long long s = 0) { mx1 = m1, mx2 = m2, cnt = c, lz = l, sum = s; } friend node operator|(node L, node R) { if (L.mx1 < R.mx1) swap(L, R); if (L.mx1 == R.mx1) L.cnt += R.cnt; else L.mx2 = max(L.mx2, R.mx1); L.mx2 = max(L.mx2, R.mx2); L.sum += R.sum; L.lz = inf; return L; } }; struct segment_beats { node seg[N << 2]; void shift(int v, int lz) { seg[v].lz = min(seg[v].lz, lz); seg[v].sum -= 1ll * seg[v].cnt * max(0, seg[v].mx1 - lz); seg[v].mx1 = min(seg[v].mx1, lz); } void second(int v, int tl, int tr) { if (tl == tr) return; shift(v << 1, seg[v].lz); shift(v << 1 | 1, seg[v].lz); } void change(int p, int x, int v = 1, int tl = 1, int tr = N - 1) { second(v, tl, tr); if (p > tr || p < tl) return; if (tl == tr) { seg[v] = node(x, -inf, 1, inf, x); return; } int mid = (tl + tr) >> 1; change(p, x, v << 1, tl, mid), change(p, x, v << 1 | 1, mid + 1, tr); seg[v] = seg[v << 1] | seg[v << 1 | 1]; } void upd(int l, int r, int x, int v = 1, int tl = 1, int tr = N - 1) { second(v, tl, tr); if (l > tr || r < tl || l > r || seg[v].mx1 <= x) return; if (l <= tl && tr <= r && seg[v].mx2 < x) { shift(v, x); return; } int mid = (tl + tr) >> 1; upd(l, r, x, v << 1, tl, mid), upd(l, r, x, v << 1 | 1, mid + 1, tr); seg[v] = seg[v << 1] | seg[v << 1 | 1]; } long long get(int l, int r, int v = 1, int tl = 1, int tr = N - 1) { second(v, tl, tr); if (l > tr || r < tl || l > r) return 0ll; if (l <= tl && tr <= r) { return seg[v].sum; } int mid = (tl + tr) >> 1; return get(l, r, v << 1, tl, mid) + get(l, r, v << 1 | 1, mid + 1, tr); } } seg1, seg2; struct segment { int lz[N << 2]; segment() { for (int i = 0; i < N << 2; i++) lz[i] = inf; } void upd(int l, int r, int x, int v = 1, int tl = 1, int tr = N - 1) { if (l > tr || r < tl || l > r) return; if (l <= tl && tr <= r) { lz[v] = min(lz[v], x); return; } int mid = (tl + tr) >> 1; upd(l, r, x, v << 1, tl, mid), upd(l, r, x, v << 1 | 1, mid + 1, tr); } int ask(int p, int v = 1, int tl = 1, int tr = N - 1) { if (tl == tr) { return lz[v]; } int mid = (tl + tr) >> 1; if (p <= mid) { return min(lz[v], ask(p, v << 1, tl, mid)); } return min(lz[v], ask(p, v << 1 | 1, mid + 1, tr)); } } Seg1, Seg2; set<int> st1, st2; int main() { for (int i = 1; i < N; i++) st1.insert(i), st2.insert(i); int n; scanf( %d , &n); for (int i = 1; i <= n; i++) { int tp, l, r; scanf( %d%d%d , &tp, &l, &r); r--; if (tp == 1) { int x; scanf( %d , &x); if (x < 0) { x = abs(x); seg1.upd(l, r, x); Seg1.upd(l, r, x); while (1) { auto it = st1.lower_bound(l); if (it == st1.end() || *it > r) break; int cu = *it; st1.erase(cu); if (st2.count(cu) == 0) { seg1.change(cu, x); seg2.change(cu, Seg2.ask(cu)); } } } else { seg2.upd(l, r, x); Seg2.upd(l, r, x); while (1) { auto it = st2.lower_bound(l); if (it == st2.end() || *it > r) break; int cu = *it; st2.erase(cu); if (st1.count(cu) == 0) { seg2.change(cu, x); seg1.change(cu, Seg1.ask(cu)); } } } } else { printf( %lld n , seg1.get(l, r) + seg2.get(l, r)); } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 300005, mod = 998244353; int qp(int a, int b) { int ans = 1; while (b) { if (b & 1) ans = 1ll * ans * a % mod; a = 1ll * a * a % mod; b >>= 1; } return ans; } int rv[N], w[N]; void ntt(vector<int> &a, int f) { int n = a.size(); for (int i = 0; i < n; i++) rv[i] = (rv[i >> 1] >> 1) | ((i & 1) * (n >> 1)); int wn = qp(f ? (mod + 1) / 3 : 3, (mod - 1) / n); w[0] = 1; for (int i = 1; i < n; i++) w[i] = 1ll * w[i - 1] * wn % mod; for (int i = 0; i < n; i++) if (i < rv[i]) swap(a[i], a[rv[i]]); for (int mid = 1; mid < n; mid <<= 1) { for (int i = 0; i < n; i += (mid << 1)) { for (int j = 0; j < mid; j++) { int x = a[i + j], y = 1ll * a[i + j + mid] * w[n / (mid << 1) * j] % mod; a[i + j] = (x + y >= mod ? x + y - mod : x + y); a[i + j + mid] = (x - y < 0 ? x - y + mod : x - y); } } } if (f) { int iv = qp(n, mod - 2); for (int i = 0; i < n; i++) a[i] = 1ll * a[i] * iv % mod; } } vector<int> mul(vector<int> a, vector<int> b) { int n = 1, m = a.size() + b.size() - 1; while (n < m) n <<= 1; a.resize(n), b.resize(n); ntt(a, 0), ntt(b, 0); for (int i = 0; i < n; i++) a[i] = 1ll * a[i] * b[i] % mod; ntt(a, 1); a.resize(m); return a; } vector<int> inv(vector<int> a) { int n = a.size(); if (n == 1) { a[0] = qp(a[0], mod - 2); return a; } int m = 1; while (m < (n << 1)) m <<= 1; vector<int> a0 = a; a0.resize((n + 1) / 2); vector<int> b0 = inv(a0); a.resize(m), b0.resize(m); ntt(a, 0), ntt(b0, 0); for (int i = 0; i < m; i++) a[i] = 1ll * b0[i] * (2 - 1ll * a[i] * b0[i] % mod + mod) % mod; ntt(a, 1); a.resize(n); return a; } vector<int> qd(vector<int> a) { int n = a.size(); for (int i = 1; i < n; i++) a[i - 1] = 1ll * a[i] * i % mod; a.pop_back(); return a; } vector<int> jf(vector<int> a) { int n = a.size(); a.push_back(0); for (int i = n; i >= 1; i--) a[i] = 1ll * a[i - 1] * qp(i, mod - 2) % mod; a[0] = 0; return a; } vector<int> ln(vector<int> a) { a = mul(qd(a), inv(a)); return jf(a); } vector<int> rev(vector<int> &a) { a[0] = 1; for (int i = 1; i < a.size(); i++) a[i] = (mod - a[i]) % mod; return a; } int n, m; int main() { scanf( %d%d , &n, &m); vector<int> a(n + 1), b(n + 1); int h = 1; int hh = 1; int cl = m / 2; for (int i = 1; i <= n; i++) { int t = (m + i) / 2; if ((m + i) & 1) { hh = 1ll * hh * (t - i + 1) % mod; h = 1ll * h * ((cl - i / 2 + mod) % mod) % mod; } else { hh = 1ll * hh * t % mod; h = 1LL * h * (cl + i / 2) % mod; } h = 1ll * h * qp(i, mod - 2) % mod; hh = 1ll * hh * qp(i, mod - 2) % mod; if (m & 1) h = hh; if (i & 1) b[i] = (((i / 2) & 1 ? -1 : 1) * h + mod) % mod; else a[i] = (((i / 2) & 1 ? 1 : -1) * h + mod) % mod; } auto d = mul(b, inv(rev(a))); auto c = rev(d); auto f = ln(inv(a)), g = ln(inv(c)); int ans = 1ll * n * (f[n] + g[n]) % mod; printf( %d n , ans); return 0; } |
//////////////////////////////////////////////////////////////////
////
////
//// AES CORE BLOCK
////
////
////
//// This file is part of the APB to AES128 project
////
//// http://www.opencores.org/cores/apbtoaes128/
////
////
////
//// Description
////
//// Implementation of APB IP core according to
////
//// aes128_spec IP core specification document.
////
////
////
//// To Do: Things are right here but always all block can suffer changes
////
////
////
////
////
//// Author(s): - Felipe Fernandes Da Costa,
////
/////////////////////////////////////////////////////////////////
////
////
//// Copyright (C) 2009 Authors and OPENCORES.ORG
////
////
////
//// This source file may be used and distributed without
////
//// restriction provided that this copyright statement is not
////
//// removed from the file and that any derivative work contains
//// the original copyright notice and the associated disclaimer.
////
////
//// This source file is free software; you can redistribute it
////
//// and/or modify it under the terms of the GNU Lesser General
////
//// Public License as published by the Free Software Foundation;
//// either version 2.1 of the License, or (at your option) any
////
//// later version.
////
////
////
//// This source is distributed in the hope that it will be
////
//// useful, but WITHOUT ANY WARRANTY; without even the implied
////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
////
//// PURPOSE. See the GNU Lesser General Public License for more
//// details.
////
////
////
//// You should have received a copy of the GNU Lesser General
////
//// Public License along with this source; if not, download it
////
//// from http://www.opencores.org/lgpl.shtml
////
////
///////////////////////////////////////////////////////////////////
module AES_GLADIC_tb;
reg PCLK;
wire PRESETn;
wire PSEL;
wire PENABLE;
wire PWRITE;
wire [31:0] PWDATA;
wire [31:0] PADDR;
wire [31:0] PRDATA;
wire PREADY;
wire PSLVERR;
wire int_ccf;
wire int_err;
wire dma_req_wr;
wire dma_req_rd;
wire [3:0] core_addr;
assign core_addr = PADDR[5:2];
aes_ip DUT (
.PCLK (PCLK),
.PRESETn (PRESETn),
.PENABLE (PENABLE),
.PSEL (PSEL),
.PWDATA (PWDATA),
.PADDR (core_addr),
.PWRITE(PWRITE),
.PRDATA (PRDATA),
.PREADY (PREADY),
.PSLVERR (PSLVERR),
.int_ccf(int_ccf),
.int_err(int_err),
.dma_req_wr(dma_req_wr),
.dma_req_rd(dma_req_rd)
);
integer i,a;
initial
begin
$dumpfile("AES_GLADIC_tb.vcd");
$dumpvars(0,AES_GLADIC_tb);
$init;
$init_reset;
end
initial PCLK = 1'b0;
always #(5) PCLK = ~PCLK;
//ECB
always@(posedge PCLK)
$bfm_encryption_ecb_aes128;
always@(posedge PCLK)
$bfm_encryption_ecb_dma_aes128;
always@(posedge PCLK)
$bfm_encryption_ccfie_ecb_aes128;
//CBC
always@(posedge PCLK)
$bfm_encryption_cbc_aes128;
always@(posedge PCLK)
$bfm_encryption_cbc_dma_aes128;
always@(posedge PCLK)
$bfm_encryption_ccfie_cbc_aes128;
//CTR
always@(posedge PCLK)
$bfm_encryption_ctr_aes128;
always@(posedge PCLK)
$bfm_encryption_ctr_dma_aes128;
always@(posedge PCLK)
$bfm_encryption_ccfie_ctr_aes128;
//ECB
always@(posedge PCLK)
$bfm_key_generation_ecb_aes128;
always@(posedge PCLK)
$bfm_key_generation_dma_ecb_aes128;
always@(posedge PCLK)
$bfm_key_generation_ccfie_ecb_aes128;
//CBC
always@(posedge PCLK)
$bfm_key_generation_cbc_aes128;
always@(posedge PCLK)
$bfm_key_generation_dma_cbc_aes128;
always@(posedge PCLK)
$bfm_key_generation_ccfie_cbc_aes128;
//CTR
always@(posedge PCLK)
$bfm_key_generation_ctr_aes128;
always@(posedge PCLK)
$bfm_key_generation_dma_ctr_aes128;
always@(posedge PCLK)
$bfm_key_generation_ccfie_ctr_aes128;
//ECB
always@(posedge PCLK)
$bfm_decryption_ecb_aes128;
always@(posedge PCLK)
$bfm_decryption_ecb_dma_aes128;
always@(posedge PCLK)
$bfm_decryption_ccfie_ecb_aes128;
//CBC
always@(posedge PCLK)
$bfm_decryption_cbc_aes128;
always@(posedge PCLK)
$bfm_decryption_cbc_dma_aes128;
always@(posedge PCLK)
$bfm_decryption_ccfie_cbc_aes128;
//CTR
always@(posedge PCLK)
$bfm_decryption_ctr_aes128;
always@(posedge PCLK)
$bfm_decryption_ctr_dma_aes128;
always@(posedge PCLK)
$bfm_decryption_ccfie_ctr_aes128;
//ECB
always@(posedge PCLK)
$bfm_derivation_decryption_ecb_aes128;
always@(posedge PCLK)
$bfm_derivation_decryption_dma_ecb_aes128;
always@(posedge PCLK)
$bfm_derivation_decryption_ccfie_ecb_aes128;
//CTR
always@(posedge PCLK)
$bfm_derivation_decryption_ctr_aes128;
always@(posedge PCLK)
$bfm_derivation_decryption_dma_ctr_aes128;
always@(posedge PCLK)
$bfm_derivation_decryption_ccfie_ctr_aes128;
//CBC
always@(posedge PCLK)
$bfm_derivation_decryption_cbc_aes128;
always@(posedge PCLK)
$bfm_derivation_decryption_dma_cbc_aes128;
always@(posedge PCLK)
$bfm_derivation_decryption_ccfie_cbc_aes128;
//SUFLE
always@(posedge PCLK)
$bfm_sufle_aes128;
//WRITE READ REGISTERS
always@(posedge PCLK)
$bfm_wr_aes128;
//TRY TO WRITE ON DINR WHILE CR[0] EQUAL 1
always@(posedge PCLK)
$bfm_wr_error_dinr_aes128;
//TRY TO READ/WRITE ON DOUTR/DINR WHILE CR[0] EQUAL 1
always@(posedge PCLK)
$bfm_wr_error_doutr_aes128;
//CHOOSE WHAT BFM WILL BE ENABLED
always@(posedge PCLK)
$bfm_generate_type;
//RESET DUT A FEW TIMES TO GO TO RIGHT STATE
always@(posedge PCLK)
$reset_aes128;
//THIS CATCH INFORMATION FROM INPUT and CHECK IT
always@(posedge PCLK)
begin
$monitor_aes;
@(posedge PENABLE);
end
//THIS MAKE REGISTER INITIAL ASSIGNMENT
always@(negedge PRESETn)
$init;
//FLAG USED TO FINISH SIMULATION PROGRAM
always@(posedge PCLK)
begin
wait(i == 1);
$finish();
end
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2007 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file tcam_bl.v when simulating
// the core, tcam_bl. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module tcam_bl(
clk,
cmp_data_mask,
cmp_din,
data_mask,
din,
we,
wr_addr,
busy,
match,
match_addr);
input clk;
input [31 : 0] cmp_data_mask;
input [31 : 0] cmp_din;
input [31 : 0] data_mask;
input [31 : 0] din;
input we;
input [10 : 0] wr_addr;
output busy;
output match;
output [2047 : 0] match_addr;
// synthesis translate_off
CAM_V5_1 #(
.c_addr_type(2),
.c_cmp_data_mask_width(32),
.c_cmp_din_width(32),
.c_data_mask_width(32),
.c_depth(2048),
.c_din_width(32),
.c_enable_rlocs(0),
.c_has_cmp_data_mask(1),
.c_has_cmp_din(1),
.c_has_data_mask(1),
.c_has_en(0),
.c_has_multiple_match(0),
.c_has_read_warning(0),
.c_has_single_match(0),
.c_has_we(1),
.c_has_wr_addr(1),
.c_match_addr_width(2048),
.c_match_resolution_type(0),
.c_mem_init(0),
.c_mem_init_file("tcam_bl.mif"),
.c_mem_type(0),
.c_read_cycles(1),
.c_reg_outputs(0),
.c_ternary_mode(2),
.c_width(32),
.c_wr_addr_width(11))
inst (
.CLK(clk),
.CMP_DATA_MASK(cmp_data_mask),
.CMP_DIN(cmp_din),
.DATA_MASK(data_mask),
.DIN(din),
.WE(we),
.WR_ADDR(wr_addr),
.BUSY(busy),
.MATCH(match),
.MATCH_ADDR(match_addr),
.EN(),
.MULTIPLE_MATCH(),
.READ_WARNING(),
.SINGLE_MATCH());
// synthesis translate_on
endmodule
|
// file: Clock.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1___100.000______0.000______50.0______400.000____150.000
// CLK_OUT2____50.000______0.000______50.0______200.000____150.000
// CLK_OUT3____25.000______0.000______50.0______300.000____150.000
// CLK_OUT4____10.000______0.000______50.0_____2200.000____150.000
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary______________50____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "Clock,clk_wiz_v3_6,{component_name=Clock,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=4,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
module Clock
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_100M,
output CLK_50M,
output CLK_25M,
output CLK_10M,
// Status and control signals
output LOCKED
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));
// Clocking primitive
//------------------------------------
// Instantiation of the DCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire psdone_unused;
wire locked_int;
wire [7:0] status_int;
wire clkfb;
wire clk0;
wire clk2x;
wire clkfx;
wire clkdv;
DCM_SP
#(.CLKDV_DIVIDE (2.000),
.CLKFX_DIVIDE (10),
.CLKFX_MULTIPLY (2),
.CLKIN_DIVIDE_BY_2 ("FALSE"),
.CLKIN_PERIOD (20.0),
.CLKOUT_PHASE_SHIFT ("NONE"),
.CLK_FEEDBACK ("2X"),
.DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
.PHASE_SHIFT (0),
.STARTUP_WAIT ("FALSE"))
dcm_sp_inst
// Input clock
(.CLKIN (clkin1),
.CLKFB (clkfb),
// Output clocks
.CLK0 (clk0),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.CLK2X (clk2x),
.CLK2X180 (),
.CLKFX (clkfx),
.CLKFX180 (),
.CLKDV (clkdv),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (locked_int),
.STATUS (status_int),
.RST (1'b0),
// Unused pin- tie low
.DSSEN (1'b0));
assign LOCKED = locked_int;
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfb),
.I (clk2x));
BUFG clkout1_buf
(.O (CLK_100M),
.I (clk2x));
BUFG clkout2_buf
(.O (CLK_50M),
.I (clk0));
BUFG clkout3_buf
(.O (CLK_25M),
.I (clkdv));
BUFG clkout4_buf
(.O (CLK_10M),
.I (clkfx));
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[n]; cin >> a[0]; int count = a[0]; int max = a[0]; for (int i = 1; i < n; i++) { cin >> a[i]; } for (int i = 1; i < n; i++) { count = count + a[i] - a[i - 1]; if (max < count) max = count; } cout << max; return 0; } |
#include <bits/stdc++.h> using namespace std; vector<vector<long long int> > dp; vector<long long int> a; long long int check(long long int l, long long int r) { if (l >= r) return 0; if (dp[l][r]) return dp[l][r]; if (l + 1 == r) { dp[l][r] = a[r]; return a[r]; } dp[l][r] = -1; for (int m = l + 1; m < r; ++m) { long long int lf = check(l, m), rt = check(m, r); if (lf > 0 && lf == rt) { dp[l][r] = lf + 1; return lf + 1; } } return dp[l][r]; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long int n; cin >> n; a.resize(n + 1); for (int i = 1; i <= n; ++i) cin >> a[i]; dp.assign(n + 1, vector<long long int>(n + 1, 0)); vector<long long int> ans(n + 1, 1e9); ans[0] = 0; for (int i = 0; i < n; ++i) { for (int j = i + 1; j <= n; ++j) { if (check(i, j) > 0) ans[j] = min(ans[j], ans[i] + 1); } } cout << ans[n]; } |
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's instruction fetch ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// PC, instruction fetch, interface to IC. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_if(
// Clock and reset
clk, rst,
// External i/f to IC
icpu_dat_i, icpu_ack_i, icpu_err_i, icpu_adr_i, icpu_tag_i,
// Internal i/f
if_freeze, if_insn, if_pc, flushpipe,
if_stall, no_more_dslot, genpc_refetch, rfe,
except_itlbmiss, except_immufault, except_ibuserr
);
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
//
// External i/f to IC
//
input [31:0] icpu_dat_i;
input icpu_ack_i;
input icpu_err_i;
input [31:0] icpu_adr_i;
input [3:0] icpu_tag_i;
//
// Internal i/f
//
input if_freeze;
output [31:0] if_insn;
output [31:0] if_pc;
input flushpipe;
output if_stall;
input no_more_dslot;
output genpc_refetch;
input rfe;
output except_itlbmiss;
output except_immufault;
output except_ibuserr;
//
// Internal wires and regs
//
reg [31:0] insn_saved;
reg [31:0] addr_saved;
reg saved;
//
// IF stage insn
//
assign if_insn = icpu_err_i | no_more_dslot | rfe ? {`OR1200_OR32_NOP, 26'h041_0000} : saved ? insn_saved : icpu_ack_i ? icpu_dat_i : {`OR1200_OR32_NOP, 26'h061_0000};
assign if_pc = saved ? addr_saved : icpu_adr_i;
// assign if_stall = !icpu_err_i & !icpu_ack_i & !saved & !no_more_dslot;
assign if_stall = !icpu_err_i & !icpu_ack_i & !saved;
assign genpc_refetch = saved & icpu_ack_i;
assign except_itlbmiss = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_TE) & !no_more_dslot;
assign except_immufault = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_PE) & !no_more_dslot;
assign except_ibuserr = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_BE) & !no_more_dslot;
//
// Flag for saved insn/address
//
always @(posedge clk or posedge rst)
if (rst)
saved <= #1 1'b0;
else if (flushpipe)
saved <= #1 1'b0;
else if (icpu_ack_i & if_freeze & !saved)
saved <= #1 1'b1;
else if (!if_freeze)
saved <= #1 1'b0;
//
// Store fetched instruction
//
always @(posedge clk or posedge rst)
if (rst)
insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
else if (flushpipe)
insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
else if (icpu_ack_i & if_freeze & !saved)
insn_saved <= #1 icpu_dat_i;
else if (!if_freeze)
insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
//
// Store fetched instruction's address
//
always @(posedge clk or posedge rst)
if (rst)
addr_saved <= #1 32'h00000000;
else if (flushpipe)
addr_saved <= #1 32'h00000000;
else if (icpu_ack_i & if_freeze & !saved)
addr_saved <= #1 icpu_adr_i;
else if (!if_freeze)
addr_saved <= #1 icpu_adr_i;
endmodule
|
#include <bits/stdc++.h> using namespace std; set<long long> mod; int main() { long long n, k; scanf( %I64d%I64d , &n, &k); bool result = true; for (long long i = 1LL; i <= k; i++) { long long x = n % i; if (mod.find(x) != mod.end()) { result = false; break; } mod.insert(x); } printf( %s n , result ? Yes : No ); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A31OI_SYMBOL_V
`define SKY130_FD_SC_LP__A31OI_SYMBOL_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a31oi (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A31OI_SYMBOL_V
|
#include <bits/stdc++.h> using std::max; const int MAXN = 500111; int N; struct Data { int Cnt, Id; long long Val; int next; Data() {} Data(int _c, int _i, long long _v) { Cnt = _c; Id = _i; Val = _v; } } T[MAXN << 2]; int Tcnt; namespace Map { struct Vert { int FE; long long Val; } V[MAXN]; struct Edge { int x, y; long long l; int next; } E[MAXN]; int Ecnt; void addE(int a, int b, long long c) { ++Ecnt; E[Ecnt].x = a; E[Ecnt].y = b; E[Ecnt].l = c; E[Ecnt].next = V[a].FE; V[a].FE = Ecnt; } void DFS(int at) { for (int k = V[at].FE, to; k > 0; k = E[k].next) { to = E[k].y; V[to].Val = V[at].Val + E[k].l; DFS(to); } } } // namespace Map namespace Tree { struct Vert { int FE; int Fa, Son; int Dep, Len; int Head; long long Ans; } V[MAXN]; struct Edge { int x, y, next; } E[MAXN << 1]; int Ecnt; void addE(int a, int b) { ++Ecnt; E[Ecnt].x = a; E[Ecnt].y = b; E[Ecnt].next = V[a].FE; V[a].FE = Ecnt; } void DFS1(int at) { for (int k = V[at].FE, to; k > 0; k = E[k].next) { to = E[k].y; if (to == V[at].Fa) continue; V[to].Dep = V[at].Dep + 1; V[to].Fa = at; DFS1(to); V[at].Len = max(V[at].Len, V[to].Len + 1); if (V[at].Son <= 0 || V[V[at].Son].Len < V[to].Len) V[at].Son = to; } } void Merge(int p, Data &A, Data &d) { d.Val += 1LL * V[p].Dep * A.Cnt; A.Val += 1LL * V[p].Dep * d.Cnt; Map::addE(A.Id, d.Id, d.Val - A.Val); A.Cnt += d.Cnt; } void DFS2(int at) { if (V[at].Son) DFS2(V[at].Son); T[++Tcnt] = Data(1, at, 0); V[at].Head = Tcnt; T[Tcnt].next = V[V[at].Son].Head; for (int k = V[at].FE, to; k > 0; k = E[k].next) { to = E[k].y; if (to == V[at].Fa || to == V[at].Son) continue; DFS2(to); for (int a = T[V[at].Head].next, p = V[to].Head; p > 0; a = T[a].next, p = T[p].next) { Merge(at, T[a], T[p]); } } } void DFS3(int at) { for (int k = V[at].FE, to; k > 0; k = E[k].next) { to = E[k].y; if (to == V[at].Fa) continue; V[to].Ans = V[at].Ans + Map::V[to].Val + V[at].Dep; DFS3(to); } } } // namespace Tree int main() { scanf( %d , &N); int Root; for (int i = 1, f; i <= N; ++i) { scanf( %d , &f); if (f == 0) Root = i; else { Tree::addE(i, f); Tree::addE(f, i); } } Tree::V[Root].Dep = 1; Tree::DFS1(Root); Tree::DFS2(Root); for (int p = Tree::V[Root].Head; p > 0; p = T[p].next) { Map::V[T[p].Id].Val = T[p].Val; Map::DFS(T[p].Id); } Tree::DFS3(Root); for (int i = 1; i <= N; ++i) printf( %I64d , Tree::V[i].Ans); puts( ); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND4B_2_V
`define SKY130_FD_SC_LS__AND4B_2_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog wrapper for and4b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__and4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and4b_2 (
X ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__and4b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and4b_2 (
X ,
A_N,
B ,
C ,
D
);
output X ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__and4b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND4B_2_V
|
#include <bits/stdc++.h> using namespace std; long long n, q; struct interv { long long l, r, ubonus, lbonus; interv(long long L, long long R, long long UBONUS, long long LBONUS) { l = L; r = R; ubonus = UBONUS; lbonus = LBONUS; } bool operator<(const interv& x) const { return r < x.r; } }; set<interv> s; set<interv>::iterator it; long long x, y, to; char dir[3]; long long ans; int main() { scanf( %lld %lld , &n, &q); s.insert(interv(1, n, 0, 0)); for (int i = 1; i <= q; i++) { scanf( %lld %lld , &x, &y); scanf( %s , dir); it = s.lower_bound(interv(0, x, 0, 0)); if (it == s.end()) { printf( 0 n ); continue; } long long b = (*it).r; long long a = (*it).l; long long ubonus = (*it).ubonus; long long lbonus = (*it).lbonus; if (x < a) { printf( 0 n ); continue; } if (dir[0] == U ) { ans = (b - a + 1) - (x - a) + ubonus; printf( %lld n , ans); s.erase(it); if (x - 1 >= 1 && a <= x - 1) s.insert(interv(a, x - 1, ans, lbonus)); if (x + 1 <= n && x + 1 <= b) s.insert(interv(x + 1, b, ubonus, 0)); } else { ans = (b - a + 1) - (b - x) + lbonus; printf( %lld n , ans); s.erase(it); if (x - 1 >= 1 && a <= x - 1) s.insert(interv(a, x - 1, 0, lbonus)); if (x + 1 <= n && x + 1 <= b) s.insert(interv(x + 1, b, ubonus, ans)); } } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A22O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__A22O_BEHAVIORAL_PP_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__a22o (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X , and1_out, and0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A22O_BEHAVIORAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O32AI_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__O32AI_FUNCTIONAL_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__o32ai (
Y ,
A1,
A2,
A3,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A3, A1, A2 );
nor nor1 (nor1_out , B1, B2 );
or or0 (or0_out_Y, nor1_out, nor0_out);
buf buf0 (Y , or0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O32AI_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; int n, ans, flag; int a[100005], b[100005], xb[100005]; void solve() { int i, j, ma; ans = -1; b[1] = xb[1] = 0; for (i = 2; i <= n; i++) { ma = 0; flag = 0; j = i - 1; while (a[j] < a[i] && j) { if (!b[j]) { flag = 1; break; } if (b[j] > ma) ma = b[j]; j = xb[j]; } if (!flag) b[i] = ma + 1; else b[i] = 0; xb[i] = j; } for (i = 1; i <= n; i++) { if (ans < b[i]) ans = b[i]; } } int main() { int i, j; while (~scanf( %d , &n)) { for (i = 1; i <= n; i++) { scanf( %d , &a[i]); } solve(); printf( %d n , ans); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 2e3; bool possible, check[N << 2], mark[N << 2]; vector<int> topol, from[N << 2], to[N << 2]; int n, m, c, d[N], com[N << 2], row[N], col[N], a[N][N], b[N][N]; void dfs_scc(int u, int c) { com[u] = c; mark[u] = true; for (auto v : to[u]) if (!mark[v]) dfs_scc(v, c); } void strongly_connected_components() { memset(mark, false, sizeof mark); for (int i = 0; i < n << 2; i++) if (check[i] && !mark[i]) dfs_scc(i, ++c); } void dfs_topolo(int u) { mark[u] = true; for (auto v : from[u]) if (!mark[v]) dfs_topolo(v); topol.push_back(u); } void topological_sort() { for (int i = 0; i < n << 2; i++) if (check[i] && !mark[i]) dfs_topolo(i); reverse(topol.begin(), topol.end()); } void input(int w) { for (int i = 0; i < n; i++) { string s; cin >> s; for (int j = 0; j < n; j++) (w ? a[i][j] : b[i][j]) = s[j] - 0 ; } } void add_edge(int u, int v) { check[u] = check[v] = true; from[u].push_back(v); from[v].push_back(u); to[u].push_back(v); to[v].push_back(u); } void add_clause(int u, int v) { add_edge(u ^ 1, v); add_edge(u, v ^ 1); } void F2(int u, int v) { int k = a[u][v] + b[u][v]; if (k == 1) (d[v] & 1 ? row[u] : col[v]) = 1; } void F1(int u, int v, int k) { k += a[u][v] + b[u][v]; if (k == 3) { add_clause(u << 1, (v + n) << 1); return; } if (k == 1) { cout << -1; exit(0); } if (k == 4 || (!a[u][v] && k == 2)) { add_clause(u << 1 ^ 1, (v + n) << 1); return; } } int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> n; input(1), input(0); string s; cin >> s; for (int i = 0; i < n; i++) d[i] = s[i] - 0 ; for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) d[i] == d[j] ? F1(i, j, d[i] + d[j]) : F2(i, j); topological_sort(); strongly_connected_components(); for (int i = 0; i < n << 1; i++) if (check[i << 1] && com[i << 1] == com[i << 1 ^ 1]) { cout << -1; return 0; } else if (check[i << 1] && com[i << 1] < com[i << 1 ^ 1]) i >= n ? col[i - n] = 1 : row[i] = true; int cnt = 0; for (int i = 0; i < n; i++) cnt += row[i] + col[i]; cout << cnt << endl; for (int i = 0; i < n; i++) if (row[i]) cout << row << i << endl; for (int i = 0; i < n; i++) if (col[i]) cout << col << i << endl; } |
#include <bits/stdc++.h> template <typename T, int NDIMS> struct tensor_view { static_assert(NDIMS >= 0, NDIMS must be nonnegative ); protected: std::array<int, NDIMS> shape; std::array<int, NDIMS> strides; T* data; tensor_view(std::array<int, NDIMS> shape_, std::array<int, NDIMS> strides_, T* data_) : shape(shape_), strides(strides_), data(data_) {} public: tensor_view() : shape{0}, strides{0}, data(nullptr) {} protected: int flatten_index(std::array<int, NDIMS> idx) const { int res = 0; for (int i = 0; i < NDIMS; i++) { res += idx[i] * strides[i]; } return res; } int flatten_index_checked(std::array<int, NDIMS> idx) const { int res = 0; for (int i = 0; i < NDIMS; i++) { assert(0 <= idx[i] && idx[i] < shape[i]); res += idx[i] * strides[i]; } return res; } public: T& operator[] (std::array<int, NDIMS> idx) const { return data[flatten_index(idx)]; } T& at(std::array<int, NDIMS> idx) const { return data[flatten_index_checked(idx)]; } template <int D = NDIMS> typename std::enable_if<(0 < D), tensor_view<T, NDIMS-1>>::type operator[] (int idx) const { std::array<int, NDIMS-1> nshape; std::copy(shape.begin()+1, shape.end(), nshape.begin()); std::array<int, NDIMS-1> nstrides; std::copy(strides.begin()+1, strides.end(), nstrides.begin()); T* ndata = data + (strides[0] * idx); return tensor_view<T, NDIMS-1>(nshape, nstrides, ndata); } template <int D = NDIMS> typename std::enable_if<(0 < D), tensor_view<T, NDIMS-1>>::type at(int idx) const { assert(0 <= idx && idx < shape[0]); return operator[](idx); } template <int D = NDIMS> typename std::enable_if<(0 == D), T&>::type operator * () const { return *data; } template <typename U, int D> friend struct tensor_view; template <typename U, int D> friend struct tensor; }; template <typename T, int NDIMS> struct tensor { static_assert(NDIMS >= 0, NDIMS must be nonnegative ); protected: std::array<int, NDIMS> shape; std::array<int, NDIMS> strides; int len; T* data; public: tensor() : shape{0}, strides{0}, len(0), data(nullptr) {} explicit tensor(std::array<int, NDIMS> shape_, const T& t = T()) { shape = shape_; strides[NDIMS-1] = 1; for (int i = NDIMS-1; i > 0; i--) { strides[i-1] = strides[i] * shape[i]; } len = strides[0] * shape[0]; data = new T[len]; std::fill(data, data + len, t); } tensor(const tensor& o) : shape(o.shape), strides(o.strides), len(o.len), data(new T[len]) { for (int i = 0; i < len; i++) { data[i] = o.data[i]; } } tensor& operator=(tensor&& o) noexcept { using std::swap; swap(shape, o.shape); swap(strides, o.strides); swap(len, o.len); swap(data, o.data); return *this; } tensor(tensor&& o) : tensor() { *this = std::move(o); } tensor& operator=(const tensor& o) { return *this = tensor(o); } ~tensor() { delete[] data; } using view_t = tensor_view<T, NDIMS>; view_t view() { return tensor_view<T, NDIMS>(shape, strides, data); } operator view_t() { return view(); } using const_view_t = tensor_view<const T, NDIMS>; const_view_t view() const { return tensor_view<const T, NDIMS>(shape, strides, data); } operator const_view_t() const { return view(); } T& operator[] (std::array<int, NDIMS> idx) { return view()[idx]; } T& at(std::array<int, NDIMS> idx) { return view().at(idx); } const T& operator[] (std::array<int, NDIMS> idx) const { return view()[idx]; } const T& at(std::array<int, NDIMS> idx) const { return view().at(idx); } template <int D = NDIMS> typename std::enable_if<(0 < D), tensor_view<T, NDIMS-1>>::type operator[] (int idx) { return view()[idx]; } template <int D = NDIMS> typename std::enable_if<(0 < D), tensor_view<T, NDIMS-1>>::type at(int idx) { return view().at(idx); } template <int D = NDIMS> typename std::enable_if<(0 < D), tensor_view<const T, NDIMS-1>>::type operator[] (int idx) const { return view()[idx]; } template <int D = NDIMS> typename std::enable_if<(0 < D), tensor_view<const T, NDIMS-1>>::type at(int idx) const { return view().at(idx); } template <int D = NDIMS> typename std::enable_if<(0 == D), T&>::type operator * () { return *view(); } template <int D = NDIMS> typename std::enable_if<(0 == D), const T&>::type operator * () const { return *view(); } }; template <typename T> void setmax(T& a, T b) { if (b > a) a = b; } int main() { using namespace std; ios_base::sync_with_stdio(false), cin.tie(nullptr); int N, Q; cin >> N >> Q; vector<int> A(N); for (int i = 0; i < N; i++) { cin >> A[i]; A[i] += i; } const int MAXK = 30; int S = 0; while (!((1 << S) >= N)) S++; tensor<pair<int, int>, 3> dp({S+1, N, MAXK+1}); { vector<pair<int, int>> stk; stk.reserve(N); for (int i = N-1; i >= 0; i--) { while (!stk.empty() && A[i] > stk.back().first) stk.pop_back(); stk.push_back({A[i], i}); int lo = -1, hi = int(stk.size())-1; while (hi - lo > 1) { int md = (lo + hi) / 2; if (stk[md].second <= A[i]) hi = md; else lo = md; } pair<int, int> cur = stk[hi]; dp[{0, i, 0}] = cur; for (int k = 1; k <= MAXK; k++) { if (A[i] + k < N) setmax(cur, {A[A[i]+k], A[i]+k}); dp[{0, i, k}] = cur; } } } for (int s = 1; s <= S; s++) { for (int i = 0; i < N; i++) { for (int k1 = 0; k1 <= MAXK; k1++) { int j = dp[{s-1, i, k1}].second; for (int k2 = 0; k1+k2 <= MAXK; k2++) { setmax(dp[{s, i, k1+k2}], dp[{s-1, j, k2}]); } } } } while (Q--) { int L, R, K; cin >> L >> R >> K; L--, R--; cout << [&]() -> int { if (L == R) return 0; vector<pair<int, int>> cur(K+1, {A[L], L}); vector<pair<int, int>> nxt(K+1); int resp = 0; auto is_done = [&](const vector<pair<int, int>>& v) { for (int k = 0; k <= K; k++) { if (v[k].first + (K-k) >= R) return true; } return false; }; if (is_done(cur)) return 1; int s = 0; while (true) { for (int k = 0; k <= K; k++) { nxt[k] = dp[{s, L, k}]; } if (is_done(nxt)) { break; } else { resp = (1 << s); s++; std::swap(nxt, cur); } } if (s) s--; while (s) { s--; std::copy(cur.begin(), cur.end(), nxt.begin()); for (int k = 0; k <= K; k++) { for (int l = 0; l <= K-k; l++) { setmax(nxt[l+k], dp[{s, cur[k].second, l}]); } } if (is_done(nxt)) { // do nothing } else { resp += 1 << s; std::swap(cur, nxt); } } resp++; return resp + 1; }() << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long m[1000001], cd, kq[100000]; map<long long, long long> ruler; int main() { cin >> cd; for (long long i = 1; i <= cd; i++) { cin >> m[i]; ruler[m[i]] = 1; } for (long long i = 1; i <= cd; i++) { long long e = 1; kq[e] = m[i]; long long t = m[i]; while (e <= cd) { if (ruler[t * 2] == 1) { kq[e + 1] = t * 2; t = t * 2; } else if (t % 3 == 0 && ruler[t / 3] == 1) { kq[e + 1] = t / 3; t = t / 3; } else break; e++; if (e == cd) { for (long long k = 1; k <= cd; k++) cout << kq[k] << ; exit(0); } } } } |
module etx_io (/*AUTOARG*/
// Outputs
txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n, txo_data_p,
txo_data_n, tx_wr_wait, tx_rd_wait,
// Inputs
tx_lclk_io, tx_lclk_div4, tx_lclk90, txi_wr_wait_p, txi_wr_wait_n,
txi_rd_wait_p, txi_rd_wait_n, tx_data_slow, tx_frame_slow
);
parameter PLATFORM = `CFG_PLATFORM;
parameter IOSTD_ELINK = "LVDS_25";
parameter PW = 104;
parameter ETYPE = 0; // 0 = parallella
// 1 = ephycard
//###########
//# reset, clocks
//##########
input tx_lclk_io; //fast ODDR
input tx_lclk_div4; //slow clock
input tx_lclk90; //fast 90deg shifted lclk
//###########
//# eLink pins
//###########
output txo_lclk_p, txo_lclk_n; // tx clock output
output txo_frame_p, txo_frame_n; // tx frame signal
output [7:0] txo_data_p, txo_data_n; // tx data (dual data rate)
input txi_wr_wait_p,txi_wr_wait_n; // tx write pushback
input txi_rd_wait_p, txi_rd_wait_n; // tx read pushback
//#############
//# Fabric interface
//#############
input [63:0] tx_data_slow; //data for burst or transaction
input [3:0] tx_frame_slow; //framing signal
output tx_wr_wait;
output tx_rd_wait;
//############
//# REGS
//############
reg [63:0] tx_data;
reg [3:0] tx_frame;
wire [15:0] tx_data16;
wire tx_frame16;
reg tx_wr_wait_sync;
reg tx_rd_wait_sync;
reg tx_wr_wait_reg;
reg tx_rd_wait_reg;
reg tx_wr_wait_reg2;
reg tx_rd_wait_reg2;
//############
//# WIRES
//############
wire [15:0] tx_data_mux;
wire txo_frame_ddr;
wire txo_lclk90;
wire tx_wr_wait_async;
wire tx_rd_wait_async;
wire [7:0] txo_data_ddr;
wire invert_pins;
//#########################################
//# Pins inverted for 64-core board
//#########################################
`ifdef TARGET_E64
assign invert_pins=1'b1;
`else
assign invert_pins=1'b0;
`endif
//#########################################
//# Synchronizatsion to fast domain
//#########################################
//Find the aligned edge
oh_edgealign edgealign0 (.firstedge (firstedge),
.fastclk (tx_lclk_io),
.slowclk (tx_lclk_div4)
);
//Data shift registers
always @ (posedge tx_lclk_io)
if(firstedge) //"load"
begin
tx_data[63:0] <= tx_data_slow[63:0]; //changes every 4 cycles
tx_frame[3:0] <= tx_frame_slow[3:0];
end
else //"shift"
begin
tx_data[63:0] <= {16'b0,tx_data[63:16]};
tx_frame[3:0] <= {tx_frame[2:0],1'b0};
end
assign tx_data16[15:0] = tx_data[15:0];
assign tx_frame16 = tx_frame[3];
//##############################################
//# Wait signal synchronization
//##############################################
always @ (negedge tx_lclk_io)
begin
tx_wr_wait_sync <= tx_wr_wait_async ^ invert_pins;
tx_rd_wait_sync <= tx_rd_wait_async ^ invert_pins;
end
//Looks like legacy elink puts out short wait pulses.
//Let's make sure they don't sneak through
always @ (posedge tx_lclk_div4)
begin
tx_wr_wait_reg <= tx_wr_wait_sync;
tx_wr_wait_reg2 <= tx_wr_wait_reg;
tx_rd_wait_reg <= tx_rd_wait_sync;
tx_rd_wait_reg2 <= tx_rd_wait_reg;
end
assign tx_wr_wait = tx_wr_wait_reg | tx_wr_wait_reg2;
assign tx_rd_wait = tx_rd_wait_reg | tx_rd_wait_reg2;
//############################################
//# IO DRIVER STUFF
//############################################
generate
genvar i;
if(PLATFORM=="ULTRASCALE")
begin : ultrascale
//DATA
for(i=0; i<8; i=i+1)
begin : gen_oddr
ODDRE1 oddr_data (.Q (txo_data_ddr[i]),
.C (tx_lclk_io),
.D1 (tx_data16[i+8] ^ invert_pins),
.D2 (tx_data16[i] ^ invert_pins));
end
//FRAME
ODDRE1 oddr_frame (.Q (txo_frame_ddr),
.C (tx_lclk_io),
.D1 (tx_frame16 ^ invert_pins),
.D2 (tx_frame16 ^ invert_pins));
//LCLK
ODDRE1 oddr_lclk (.Q (txo_lclk90),
.C (tx_lclk90),
.D1 (1'b1 ^ invert_pins),
.D2 (1'b0 ^ invert_pins));
end // block: ultrascale
else
begin : zynq
for(i=0; i<8; i=i+1)
begin : gen_oddr
ODDR #(.DDR_CLK_EDGE ("SAME_EDGE"))
oddr_data (
.Q (txo_data_ddr[i]),
.C (tx_lclk_io),
.CE (1'b1),
.D1 (tx_data16[i+8] ^ invert_pins),
.D2 (tx_data16[i] ^ invert_pins),
.R (1'b0),
.S (1'b0)
);
end
//FRAME
ODDR #(.DDR_CLK_EDGE ("SAME_EDGE"))
oddr_frame (
.Q (txo_frame_ddr),
.C (tx_lclk_io),
.CE (1'b1),
.D1 (tx_frame16 ^ invert_pins),
.D2 (tx_frame16 ^ invert_pins),
.R (1'b0), //reset
.S (1'b0)
);
//LCLK
ODDR #(.DDR_CLK_EDGE ("SAME_EDGE"))
oddr_lclk (
.Q (txo_lclk90),
.C (tx_lclk90),
.CE (1'b1),
.D1 (1'b1 ^ invert_pins),
.D2 (1'b0 ^ invert_pins),
.R (1'b0),//should be no reason to reset clock, static input
.S (1'b0)
);
end
endgenerate
//Buffer drivers
OBUFDS obufds_data[7:0] (.O (txo_data_p[7:0]),
.OB (txo_data_n[7:0]),
.I (txo_data_ddr[7:0]));
OBUFDS obufds_frame (.O (txo_frame_p),
.OB (txo_frame_n),
.I (txo_frame_ddr));
OBUFDS obufds_lclk (.O (txo_lclk_p),
.OB (txo_lclk_n),
.I (txo_lclk90));
//Wait inputs
generate
if(ETYPE==1)
begin
assign tx_wr_wait_async = txi_wr_wait_p;
end
else if (ETYPE==0)
begin
IBUFDS
#(.DIFF_TERM ("TRUE"), // Differential termination
.IOSTANDARD (IOSTD_ELINK))
ibufds_wrwait
(.I (txi_wr_wait_p),
.IB (txi_wr_wait_n),
.O (tx_wr_wait_async));
end
endgenerate
generate
if(PLATFORM=="ULTRASCALE")
IBUFDS
#(.DIFF_TERM ("TRUE"), // Differential termination
.IOSTANDARD (IOSTD_ELINK))
ibufds_rdwait
(.I (txi_rd_wait_p),
.IB (txi_rd_wait_n),
.O (tx_rd_wait_async));
else // ZYNQ
//On Parallella this signal comes in single-ended
assign tx_rd_wait_async = txi_rd_wait_p;
endgenerate
endmodule // etx_io
// Local Variables:
// verilog-library-directories:("." "../../emesh/hdl" "../../common/hdl")
// End:
|
(**********************************************************************)
(* Equations *)
(* Copyright (c) 2009-2020 Matthieu Sozeau <> *)
(**********************************************************************)
(* This file is distributed under the terms of the *)
(* GNU Lesser General Public License Version 2.1 *)
(**********************************************************************)
Require Import Equations.Init Equations.CoreTactics.
Set Warnings "-notation-overridden".
Require Import HoTT.Basics.Trunc HoTT.HSet.
Require Import Equations.HoTT.Logic Equations.HoTT.Relation
Equations.HoTT.Relation_Properties Equations.HoTT.WellFounded.
Set Universe Polymorphism.
(** A class for well foundedness proofs.
Instances can be derived automatically using [Derive Subterm for ind]. *)
Class WellFounded {A : Type} (R : Relation A) :=
wellfounded : well_founded R.
(** This class contains no-cyclicity proofs.
They can be derived from well-foundedness proofs for example.
*)
(** The proofs of [NoCycle] can be arbitrarily large, it doesn't
actually matter in the sense that they are used to prove
absurdity. *)
(* Cumulative *)
Class NoCyclePackage@{i|} (A : Type@{i}) :=
{ NoCycle : A -> A -> Type@{i};
noCycle : forall {a b}, NoCycle a b -> (a = b -> Empty) }.
(** These lemmas explains how to apply it during simplification. *)
(** We always generate a goal of the form [NoCycle x C[x]], using either
the left or right versions of the following lemma. *)
Lemma apply_noCycle_left@{i j|} {A : Type@{i}} {noconf : NoCyclePackage A}
(p q : A) {B : p = q -> Type@{j}} :
NoCycle@{i} p q -> (forall H : p = q, B H).
Proof.
intros noc eq. destruct (noCycle noc eq).
Defined.
Lemma apply_noCycle_right@{i j|} {A : Type@{i}} {noconf : NoCyclePackage A}
(p q : A) {B : p = q -> Type@{j}} :
NoCycle q p -> (forall H : p = q, B H).
Proof.
intros noc eq. destruct (noCycle noc (inverse eq)).
Defined.
(* Extraction Inline apply_noCycle_left apply_noCycle_right. *)
(** NoCycle can be decided using the well-founded subterm relation. *)
Definition NoCycle_WellFounded {A} (R : Relation A) (wfR : WellFounded R) : NoCyclePackage A :=
{| NoCycle := R;
noCycle := WellFounded.well_founded_irreflexive (wfR:=wfR) |}.
#[export]
Existing Instance NoCycle_WellFounded.
#[export] Hint Extern 30 (@NoCycle ?A (NoCycle_WellFounded ?R ?wfr) _ _) =>
hnf; typeclasses eauto with subterm_relation : typeclass_instances.
(** The NoConfusionPackage class provides a method for solving injectivity and discrimination
of constructors, represented by an equality on an inductive type [I]. The type of [noConfusion]
should be of the form [ Π Δ, (x y : I Δ) (x = y) -> NoConfusion x y ], where
[NoConfusion x y] for constructor-headed [x] and [y] will give equality of their arguments
or the absurd proposition in case of conflict.
This gives a general method for simplifying by discrimination or injectivity of constructors.
Some actual instances are defined later in the file using the more primitive [discriminate] and
[injection] tactics on which we can always fall back.
*)
Cumulative Class NoConfusionPackage@{i} (A : Type@{i}) := {
NoConfusion : A -> A -> Type@{i};
noConfusion : forall {a b}, NoConfusion a b -> a = b;
noConfusion_inv : forall {a b}, a = b -> NoConfusion a b;
noConfusion_sect : forall {a b} (e : NoConfusion a b), noConfusion_inv (noConfusion e) = e;
noConfusion_retr : forall {a b} (e : a = b), (noConfusion (noConfusion_inv e)) = e;
}.
(** This lemma explains how to apply it during simplification. *)
Lemma apply_noConfusion@{i j|} {A : Type@{i}} {noconf : NoConfusionPackage A}
(p q : A) {B : p = q -> Type@{j}} :
(forall e : NoConfusion p q, B (noConfusion e)) -> (forall e : p = q, B e).
Proof.
intros. generalize (noConfusion_retr e). destruct e.
intros eq. destruct eq. apply X.
Defined.
(* Extraction Inline apply_noConfusion. *)
(** Classes for types with UIP or decidable equality. *)
Class UIP@{i|} (A : Type@{i}) := uip : forall {x y : A} (e e' : x = y), e = e'.
#[export]
Instance IsHSet_UIP (A : Type) (H : IsHSet A) : UIP A.
Proof.
apply axiomK_hset in H. intros x y e e'.
red in H. destruct e'. apply H.
Defined.
(* By truncation, we also get those, we keep a single instance for HSet *)
Example IsHProp_UIP (A : Type) (H : IsHProp A) : UIP A := _.
Example Contr_UIP (A : Type) (H : Contr A) : UIP A := _.
Definition dec_eq {A} (x y : A) : Type := (x = y) + (x <> y).
Class EqDec@{i} (A : Type@{i}) := eq_dec : forall x y : A, sum@{i i} (x = y) (x = y -> Empty).
Class EqDecPoint (A : Type) (x : A) := eq_dec_point : forall y : A, (x = y) + (x <> y).
#[export]
Instance EqDec_EqDecPoint A `(EqDec A) (x : A) : EqDecPoint A x := eq_dec x.
(** For treating impossible cases. Equations corresponding to impossible
calls form instances of [ImpossibleCall (f args)]. *)
Class ImpossibleCall {A : Type} (a : A) : Type :=
is_impossible_call : Empty.
(** We have a trivial elimination operator for impossible calls. *)
Definition elim_impossible_call {A} (a : A) {imp : ImpossibleCall a} (P : A -> Type) : P a :=
match is_impossible_call with end.
(** The tactic tries to find a call of [f] and eliminate it. *)
Ltac impossible_call f := on_call f ltac:(fun t => apply (elim_impossible_call t)).
(** The [FunctionalInduction f] typeclass is meant to register functional induction
principles associated to a function [f]. Such principles are automatically
generated for definitions made using [Equations]. *)
Polymorphic
Class FunctionalInduction {A : Type} (f : A) :=
{ fun_ind_prf_ty : Type; fun_ind_prf : fun_ind_prf_ty }.
Register FunctionalInduction as equations.funind.class.
(** The [FunctionalElimination f] class declares elimination principles produced
from the functional induction principle for [f] to be used directly to eliminate
a call to [f]. This is the preferred method of proving results about a function.
[n] is the number of binders for parameters, predicates and methods of the
eliminator.
*)
Polymorphic
Class FunctionalElimination {A : Type} (f : A) (fun_elim_ty : Type) (n : nat) :=
fun_elim : fun_elim_ty.
Register FunctionalElimination as equations.funelim.class.
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t = 1; cin >> t; while (t-- > 0) { int n; cin >> n; string srr[n]; for (int i = 0; i < n; i++) { cin >> srr[i]; } vector<pair<int, int>> afirst(n); vector<pair<int, int>> bfirst(n); vector<pair<int, int>> cfirst(n); vector<pair<int, int>> dfirst(n); vector<pair<int, int>> efirst(n); for (int i = 0; i < n; i++) { int countabc[5] = {0}; for (int j = 0; j < srr[i].size(); j++) { countabc[srr[i][j] - a ]++; } afirst[i].first = 2 * countabc[0] - srr[i].size(); bfirst[i].first = 2 * countabc[1] - srr[i].size(); cfirst[i].first = 2 * countabc[2] - srr[i].size(); dfirst[i].first = 2 * countabc[3] - srr[i].size(); efirst[i].first = 2 * countabc[4] - srr[i].size(); afirst[i].second = i; bfirst[i].second = i; cfirst[i].second = i; dfirst[i].second = i; efirst[i].second = i; } sort(afirst.begin(), afirst.end()); sort(bfirst.begin(), bfirst.end()); sort(cfirst.begin(), cfirst.end()); sort(dfirst.begin(), dfirst.end()); sort(efirst.begin(), efirst.end()); int maxi = 0; int curr = 0; int total = 0; for (int i = n - 1; i >= 0; i--) { curr += afirst[i].first; if (curr >= 1) { total++; } else { break; } } maxi = max(maxi, total); curr = 0; total = 0; for (int i = n - 1; i >= 0; i--) { curr += bfirst[i].first; if (curr >= 1) { total++; } else { break; } } maxi = max(maxi, total); curr = 0; total = 0; for (int i = n - 1; i >= 0; i--) { curr += cfirst[i].first; if (curr >= 1) { total++; } else { break; } } maxi = max(maxi, total); curr = 0; total = 0; for (int i = n - 1; i >= 0; i--) { curr += dfirst[i].first; if (curr >= 1) { total++; } else { break; } } maxi = max(maxi, total); curr = 0; total = 0; for (int i = n - 1; i >= 0; i--) { curr += efirst[i].first; if (curr >= 1) { total++; } else { break; } } maxi = max(maxi, total); cout << maxi << endl; } return 0; } |
//Control circuit
`include "verilog/mips_instr_defines.v"
module control
(
input wire[5:0] instr_op_ctl_i,
input wire[5:0] instr_funct_ctl_i,
output wire reg_src_ctl_o,
output wire reg_dst_ctl_o,
output wire jump_ctl_o,
output wire branch_ctl_o,
output wire mem_read_ctl_o,
output wire mem_to_reg_ctl_o,
output wire[5:0] alu_op_ctl_o,
output wire mem_wr_ctl_o,
output wire[2:0] alu_src_ctl_o,
output wire reg_wr_ctl_o,
output wire sign_ext_ctl_o
);
wire reg_src_ctl;
wire reg_dst_ctl;
wire jump_ctl;
wire branch_ctl;
wire mem_read_ctl;
wire mem_to_reg_ctl;
wire[5:0] alu_op_ctl;
wire mem_wr_ctl;
wire[2:0] alu_src_ctl;
wire reg_wr_ctl;
wire sign_ext_ctl;
reg[17:0] controls;
assign reg_src_ctl_o = reg_src_ctl;
assign reg_dst_ctl_o = reg_dst_ctl;
assign jump_ctl_o = jump_ctl;
assign branch_ctl_o = branch_ctl;
assign mem_read_ctl_o = mem_read_ctl;
assign mem_to_reg_ctl_o = mem_to_reg_ctl;
assign alu_op_ctl_o = alu_op_ctl;
assign mem_wr_ctl_o = mem_wr_ctl;
assign alu_src_ctl_o = alu_src_ctl;
assign reg_wr_ctl_o = reg_wr_ctl;
assign sign_ext_ctl_o = sign_ext_ctl;
assign {reg_src_ctl, reg_dst_ctl, jump_ctl, branch_ctl, mem_read_ctl, mem_to_reg_ctl,
alu_op_ctl, mem_wr_ctl, alu_src_ctl, reg_wr_ctl, sign_ext_ctl} = controls;
always @ *
begin
case (instr_op_ctl_i)
//alu_op_ctl:
//6'b000_00_0: ADD
//6'b000_00_1: SUB
//6'b000_01_0: shift left
//6'b000_10_0: logical shift right
//6'b000_11_0: arithmetic shift right
//6'b001_00_0: logical OR
//6'b010_00_0: logical AND
//6'b011_00_0: logical NOR
//6'b100_00_0: logical XOR
//reg_src_ctl, reg_dst_ctl, jump_ctl, branch_ctl, mem_read_ctl, mem_to_reg_ctl, alu_op_ctl, mem_wr_ctl, alu_src_ctl, reg_wr_ctl, sign_ext
`ADDI : controls = 18'b0_0_0_0_0_0_000000_0_001_1_1; // I
`ADDIU : controls = 18'b0_0_0_0_0_0_000000_0_001_1_1; // I
`ANDI : controls = 18'b0_0_0_0_0_0_010000_0_001_1_0; // I
`SLTI : controls = 18'b0_0_0_0_0_0_101001_0_001_1_1; // I
`SLTIU : controls = 18'b0_0_0_0_0_0_110001_0_001_1_1; // I
`ORI : controls = 18'b0_0_0_0_0_0_001000_0_001_1_0; // I
`XORI : controls = 18'b0_0_0_0_0_0_100000_0_001_1_0; // I
`BEQ : controls = 18'b0_0_0_1_0_0_000001_0_000_0_1; // I
`BVAR : controls = 18'b0_0_0_1_0_0_000001_0_100_0_1; // I
`BGTZ : controls = 18'b0_0_0_1_0_0_000000_0_100_0_1; // I
`BLEZ : controls = 18'b0_0_0_1_0_0_000000_0_100_0_1; // I
`BNE : controls = 18'b0_0_0_1_0_0_000001_0_000_0_1; // I
`LB : controls = 18'b0_0_0_0_1_1_000000_0_001_1_1; // I
`LBU : controls = 18'b0_0_0_0_1_1_000000_0_001_1_1; // I
`LH : controls = 18'b0_0_0_0_1_1_000000_0_001_1_1; // I
`LHU : controls = 18'b0_0_0_0_1_1_000000_0_001_1_1; // I
`LUI : controls = 18'b0_0_0_0_1_1_000000_0_001_1_1; // I
`LW : controls = 18'b0_0_0_0_1_1_000000_0_001_1_1; // I
`SB : controls = 18'b0_0_0_0_0_0_000000_1_001_0_1; // I
`SH : controls = 18'b0_0_0_0_0_0_000000_1_001_0_1; // I
`SW : controls = 18'b0_0_0_0_0_0_000000_1_001_0_1; // I
`J : controls = 18'b0_0_1_0_0_0_000000_0_001_0_1; // J
`JAL : controls = 18'b0_0_1_0_0_0_000000_0_001_1_1; // J
5'b00000:
case (instr_funct_ctl_i)
//alu_op_ctl:
//6'b000_00_0: ADD
//6'b000_00_1: SUB
//6'b000_01_0: shift left
//6'b000_10_0: logical shift right
//6'b000_11_0: arithmetic shift right
//6'b001_00_0: logical OR
//6'b010_00_0: logical AND
//6'b011_00_0: logical NOR
//6'b100_00_0: logical XOR
//alu_src_ctl:
//3'b000: sends rf port 2 value to ALU
//3'b001: sends sign_imm to ALU
//3'b010: sends zero extended shamt value to ALU
//3'b100: send 32'b0 to ALU
//reg_src_ctl,reg_dst_ctl, jump_ctl, branch_ctl, mem_read_ctl, mem_to_reg_ctl, alu_op_ctl, mem_wr_ctl, alu_src_ctl, reg_wr_ctl,sign_ext_ctl
`ADD : controls = 18'b0_1_0_0_0_0_000000_0_000_1_0; // R
`ADDU : controls = 18'b0_1_0_0_0_0_000000_0_000_1_0; // R
`AND : controls = 18'b0_1_0_0_0_0_010000_0_000_1_0; // R
`DIV : controls = 18'b0_1_0_0_0_0_000000_0_000_1_0; // R
`DIVU : controls = 18'b0_1_0_0_0_0_000000_0_000_1_0; // R
`JALR : controls = 18'b0_1_0_0_0_0_000000_0_000_1_0; // R
`JR : controls = 18'b0_1_0_0_0_0_000000_0_000_1_0; // R
`MFHI : controls = 18'b0_1_0_0_0_0_000000_0_000_1_0; // R
`MFLO : controls = 18'b0_1_0_0_0_0_000000_0_000_1_0; // R
`MTHI : controls = 18'b0_1_0_0_0_0_000000_0_000_1_0; // R
`MTLO : controls = 18'b0_1_0_0_0_0_000000_0_000_1_0; // R
`MULT : controls = 18'b0_1_0_0_0_0_000000_0_000_1_0; // R
`MULTU : controls = 18'b0_1_0_0_0_0_000000_0_000_1_0; // R
`NOR : controls = 18'b0_1_0_0_0_0_011000_0_000_1_0; // R
`OR : controls = 18'b0_1_0_0_0_0_001000_0_000_1_0; // R
`SLLV : controls = 18'b1_1_0_0_0_0_000010_0_010_1_0; // R
`SLT : controls = 18'b0_1_0_0_0_0_101001_0_000_1_0; // R
`SLTU : controls = 18'b0_1_0_0_0_0_110001_0_000_1_0; // R
`SRA : controls = 18'b1_1_0_0_0_0_000110_0_010_1_0; // R
`SRAV : controls = 18'b1_1_0_0_0_0_000110_0_010_1_0; // R
`SRL : controls = 18'b1_1_0_0_0_0_000100_0_010_1_0; // R
`SRLV : controls = 18'b1_1_0_0_0_0_000100_0_010_1_0; // R
`SUB : controls = 18'b0_1_0_0_0_0_000001_0_000_1_0; // R
`SUBU : controls = 18'b0_1_0_0_0_0_000001_0_000_1_0; // R
`SYSCALL: controls = 18'b0_1_0_0_0_0_000000_0_000_0_0; // R
`XOR : controls = 18'b0_1_0_0_0_0_100000_0_000_1_0; // R
`SLL : controls = 18'b1_1_0_0_0_0_000010_0_010_1_0; // R
default : controls = 18'b0_1_0_0_0_0_000000_0_000_1_0;
endcase
default : controls = 18'b0_1_0_0_0_0_000000_0_000_0_0;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, x, y, ans; struct Edge { long long to, next; } edge[2 * 300001]; long long head[300001], sze; long long fa[300001], Tsze[300001], deep[300001]; inline char gc() { static char now[1 << 20], *S, *T; if (T == S) { T = (S = now) + fread(now, 1, 1 << 20, stdin); if (T == S) return EOF; } return *S++; } inline long long read() { long long res = 0; char c; while ((c = getchar()) < 0 || c > 9 ) ; res = (c ^ 48); while ((c = getchar()) >= 0 && c <= 9 ) res = (res << 3) + (res << 1) + (c ^ 48); return res; } inline void add(long long u, long long v) { edge[++sze] = (Edge){v, head[u]}, head[u] = sze; edge[++sze] = (Edge){u, head[v]}, head[v] = sze; } inline void dfs(long long u, long long f) { fa[u] = f, deep[u] = deep[f] + 1, Tsze[u] = 1; long long i; for (i = head[u]; i; i = edge[i].next) { long long v = edge[i].to; if (v == f) continue; dfs(v, u), Tsze[u] += Tsze[v]; } } inline long long ask() { if (deep[x] > deep[y]) swap(x, y); long long ok = 0, i; for (i = y; i; i = fa[i]) if (i == x) { ok = 1; break; } if (ok) return (n - Tsze[x] + 1) * Tsze[y]; return Tsze[x] * Tsze[y]; } signed main() { n = read(), x = read(), y = read(), ans = n * (n - 1); long long i; for (i = 1; i < n; i++) add(read(), read()); dfs(1, 0); long long a = x, b = y, ok = 0; for (; a; a = fa[a]) if (fa[a] == y) ans -= Tsze[x] * (n - Tsze[a]), ok = 1; for (; b; b = fa[b]) if (fa[b] == x) ans -= Tsze[y] * (n - Tsze[b]), ok = 1; if (!ok) ans -= Tsze[x] * Tsze[y]; printf( %lld , ans); return 0; } |
module AUDIO_DAC_FIFO ( // FIFO Side
iDATA,iWR,iWR_CLK,
oDATA,
// Audio Side
oAUD_BCK,
oAUD_DATA,
oAUD_LRCK,
oAUD_XCK,
// Control Signals
iCLK_18_4,
iRST_N );
parameter REF_CLK = 18432000; // 18.432 MHz
parameter SAMPLE_RATE = 48000; // 48 KHz
parameter DATA_WIDTH = 16; // 16 Bits
parameter CHANNEL_NUM = 2; // Dual Channel
// FIFO Side
input [DATA_WIDTH-1:0] iDATA;
input iWR;
input iWR_CLK;
output [DATA_WIDTH-1:0] oDATA;
wire [DATA_WIDTH-1:0] mDATA;
reg mDATA_RD;
// Audio Side
output oAUD_DATA;
output oAUD_LRCK;
output oAUD_BCK;
output oAUD_XCK;
reg oAUD_BCK;
// Control Signals
input iCLK_18_4;
input iRST_N;
// Internal Registers and Wires
reg [3:0] BCK_DIV;
reg [8:0] LRCK_1X_DIV;
reg [7:0] LRCK_2X_DIV;
reg [3:0] SEL_Cont;
////////////////////////////////////
reg [DATA_WIDTH-1:0] DATA_Out;
reg [DATA_WIDTH-1:0] DATA_Out_Tmp;
reg LRCK_1X;
reg LRCK_2X;
FIFO_16_256 u0 ( .data(iDATA),.wrreq(iWR),
.rdreq(mDATA_RD),.rdclk(iCLK_18_4),
.wrclk(iWR_CLK),.aclr(~iRST_N),
.q(mDATA),.wrfull(oDATA[0]));
assign oAUD_XCK = ~iCLK_18_4;
//////////// AUD_BCK Generator //////////////
always@(posedge iCLK_18_4 or negedge iRST_N)
begin
if(!iRST_N)
begin
BCK_DIV <= 0;
oAUD_BCK <= 0;
end
else
begin
if(BCK_DIV >= REF_CLK/(SAMPLE_RATE*DATA_WIDTH*CHANNEL_NUM*2)-1 )
begin
BCK_DIV <= 0;
oAUD_BCK <= ~oAUD_BCK;
end
else
BCK_DIV <= BCK_DIV+1;
end
end
//////////////////////////////////////////////////
//////////// AUD_LRCK Generator //////////////
always@(posedge iCLK_18_4 or negedge iRST_N)
begin
if(!iRST_N)
begin
LRCK_1X_DIV <= 0;
LRCK_2X_DIV <= 0;
LRCK_1X <= 0;
LRCK_2X <= 0;
end
else
begin
// LRCK 1X
if(LRCK_1X_DIV >= REF_CLK/(SAMPLE_RATE*2)-1 )
begin
LRCK_1X_DIV <= 0;
LRCK_1X <= ~LRCK_1X;
end
else
LRCK_1X_DIV <= LRCK_1X_DIV+1;
// LRCK 2X
if(LRCK_2X_DIV >= REF_CLK/(SAMPLE_RATE*4)-1 )
begin
LRCK_2X_DIV <= 0;
LRCK_2X <= ~LRCK_2X;
end
else
LRCK_2X_DIV <= LRCK_2X_DIV+1;
end
end
assign oAUD_LRCK = LRCK_1X;
//////////////////////////////////////////////////
////////// Read Signal Generator //////////////
always@(posedge iCLK_18_4 or negedge iRST_N)
begin
if(!iRST_N)
begin
mDATA_RD <= 0;
end
else
begin
if(LRCK_1X_DIV == REF_CLK/(SAMPLE_RATE*2)-1 )
mDATA_RD <= 1;
else
mDATA_RD <= 0;
end
end
//////////////////////////////////////////////////
////////////// DATA Latch //////////////////
always@(posedge iCLK_18_4 or negedge iRST_N)
begin
if(!iRST_N)
DATA_Out_Tmp <= 0;
else
begin
if(LRCK_2X_DIV == REF_CLK/(SAMPLE_RATE*4)-1 )
DATA_Out_Tmp <= mDATA;
end
end
always@(posedge iCLK_18_4 or negedge iRST_N)
begin
if(!iRST_N)
DATA_Out <= 0;
else
begin
if(LRCK_2X_DIV == REF_CLK/(SAMPLE_RATE*4)-3 )
DATA_Out <= DATA_Out_Tmp;
end
end
//////////////////////////////////////////////////
////////// 16 Bits PISO MSB First //////////////
always@(negedge oAUD_BCK or negedge iRST_N)
begin
if(!iRST_N)
SEL_Cont <= 0;
else
SEL_Cont <= SEL_Cont+1;
end
assign oAUD_DATA = DATA_Out[~SEL_Cont];
//////////////////////////////////////////////////
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2019 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
interface secret_intf();
logic secret_a;
integer secret_b;
endinterface
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
secret_sub secret_inst (.*);
secret_other secret_inst2 (.*);
endmodule
module secret_sub
(
input clk);
// verilator no_inline_module
integer secret_cyc;
real secret_cyc_r;
integer secret_o;
real secret_r;
export "DPI-C" task dpix_a_task;
task dpix_a_task(input int i, output int o); o = i + 1; endtask
import "DPI-C" context task dpii_a_task(input int i, output int o);
export "DPI-C" function dpix_a_func;
function int dpix_a_func(input int i); return i + 2; endfunction
import "DPI-C" context function int dpii_a_func(input int i);
// Test loop
always @ (posedge clk) begin
secret_cyc_r = $itor(secret_cyc)/10.0 - 5.0;
secret_cyc <= dpii_a_func(secret_cyc);
secret_r += 1.0 + $cos(secret_cyc_r);
dpix_a_task(secret_cyc, secret_o);
if (secret_cyc==90) begin
$write("*-* All Finished *-*\n");
end
end
endmodule
module secret_other
(
input clk);
integer secret_cyc;
always @ (posedge clk) begin
secret_cyc <= secret_cyc + 1;
if (secret_cyc==99) begin
$finish;
end
end
secret_intf secret_interface();
endmodule
|
#include <bits/stdc++.h> const long long INF = 0x3f3f3f3f; using namespace std; void sol() { long long n, m; while (cin >> n >> m) { string s; cin.ignore(); cin >> s; long long x[6][n]; string a[6] = { abc , acb , bca , bac , cab , cba }; memset(x, 0, sizeof(x)); ; for (long long i = 0; i < s.size(); i++) { if (i) { for (long long j = 0; j < 6; j++) { x[j][i] = x[j][i - 1]; if (s[i] != a[j][i % 3]) x[j][i]++; } } else { for (long long j = 0; j < 6; j++) { x[j][i] = 0; if (s[i] != a[j][i % 3]) x[j][i]++; } } } while (m--) { long long a, b; cin >> a >> b; long long ans = INF; if (a > 1) { for (long long i = 0; i < 6; i++) { ans = (x[i][b - 1] - x[i][a - 2] < ans ? x[i][b - 1] - x[i][a - 2] : ans); } } else { for (long long i = 0; i < 6; i++) { ans = (x[i][b - 1] < ans ? x[i][b - 1] : ans); } } cout << ans << n ; } } } signed main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); ; long long t = 1; while (t--) { sol(); cout.flush(); } return 0; } |
#include <bits/stdc++.h> using namespace std; int a[20]; int main() { int n, b[20]; cin >> n; for (int i = 0; i < n; i++) cin >> b[i]; int kol = 1; for (int i = 0; i < n; i++) kol *= 2; for (int i = 0; i < kol; i++) { int sum = 0; a[n - 1]++; for (int j = n - 1; j > 0; j--) { a[j - 1] = a[j] / 2 + a[j - 1]; a[j] %= 2; } for (int j = 0; j < n; j++) { if (a[j] == 1) sum += b[j]; else sum -= b[j]; } sum = abs(sum); sum %= 360; if (sum == 0) { cout << yes ; return 0; } } cout << no ; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long INF = 1e9; struct outgoing { long long wt = INF, to = -1; }; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; vector<long long> stations; vector<pair<long long, long long>> connections; long long n, i, j, k, t, temp; cin >> n; vector<outgoing> edge(n + 1); pair<long long, long long> vertices[n + 1]; long long cost[n + 1]; long long mult[n + 1]; for (i = 1; i <= n; i++) { cin >> vertices[i].first >> vertices[i].second; } for (i = 1; i <= n; i++) { cin >> cost[i]; edge[i].wt = cost[i]; edge[i].to = i; } for (i = 1; i <= n; i++) { cin >> mult[i]; } long long total = 0; vector<bool> selected(n + 1, false); for (i = 1; i <= n; i++) { long long v = -1; for (j = 1; j <= n; j++) { if (!selected[j] && (v == -1 || edge[j].wt < edge[v].wt)) { v = j; } } selected[v] = true; long long x_now = vertices[v].first; long long y_now = vertices[v].second; if (edge[v].to == v) { stations.push_back(v); } else { connections.push_back({v, edge[v].to}); } total += edge[v].wt; for (j = 1; j <= n; j++) { long long x_diff = fabs(vertices[j].first - vertices[v].first); long long y_diff = fabs(vertices[j].second - vertices[v].second); if ((mult[v] + mult[j]) * (x_diff + y_diff) < edge[j].wt) { edge[j].wt = (mult[v] + mult[j]) * (x_diff + y_diff); edge[j].to = v; } } } cout << total << endl; cout << stations.size() << endl; for (auto x : stations) { cout << x << ; } cout << n ; cout << connections.size() << endl; for (auto x : connections) { cout << x.first << << x.second << endl; } return 0; } |
#include <bits/stdc++.h> using std::cerr; using std::cin; using std::cout; using std::endl; using std::list; using std::map; using std::max; using std::min; using std::pair; using std::set; using std::sort; using std::string; using std::swap; using std::vector; const int MAXN = 100005; const long long INF = 100000000009; const long long MOD = (long long)1e9 + 7; bool used[MAXN]; bool cnt[MAXN][50]; int main() { std::ios_base::sync_with_stdio(false); std::cin.tie(nullptr); int n; cin >> n; string sec; cin >> sec; for (int i = 0; i < n; ++i) { if (sec[i] != * ) { used[(int)sec[i]] = true; } } int m; cin >> m; vector<string> needed; for (int i = 0; i < m; ++i) { string s; cin >> s; bool flag = true; for (int j = 0; j < n; ++j) { if (sec[j] == * ) { if (used[(int)s[j]]) { flag = false; break; } } else if (sec[j] != s[j]) { flag = false; break; } } if (flag) { needed.push_back(s); } } for (int j = 0; j < needed.size(); ++j) { for (int i = 0; i < n; ++i) { if (sec[i] == * ) { cnt[j][(int)needed[j][i] - a ] = true; } } } int ans = 0; for (int i = 0; i <= (int) z - (int) a ; ++i) { bool flag = true; for (int j = 0; j < needed.size(); ++j) { if (!cnt[j][i]) { flag = false; } } if (flag) { ++ans; } } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long INF = (long long)-1e18; const int N = 200 * 1000 + 100; vector<int> g[N]; vector<int> w[N]; vector<pair<long long, long long> > cur; long long add[N]; long long ans[N]; int a[N]; long long dfs2(int v) { ans[v] = add[v]; for (int i = 0; i < g[v].size(); i++) ans[v] += dfs2(g[v][i]); return ans[v]; } void dfs(int v, int par, long long h) { if (v != par) { long long dist = h - a[v]; vector<pair<long long, long long> >::iterator it = lower_bound( cur.begin(), cur.end(), pair<long long, long long>(dist, INF)); add[par]++; if (it != cur.begin()) { it--; add[it->second]--; } } cur.push_back(pair<long long, long long>(h, v)); for (int i = 0; i < g[v].size(); i++) dfs(g[v][i], v, h + w[v][i]); cur.pop_back(); } int main() { int n; cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; } for (int i = 1; i < n; i++) { int p, l; cin >> p >> l; p--; g[p].push_back(i); w[p].push_back(l); } dfs(0, 0, 0); dfs2(0); for (long long i = 0; i < n; i++) cout << ans[i] << ; cout << endl; } |
#include <bits/stdc++.h> using namespace std; const long long maxn = 1005, maxk = 12; string s, t; long long d[maxn][maxn][maxk][2]; long long n, m, k; int main() { ios_base::sync_with_stdio(false); cin >> n >> m >> k >> s >> t; for (long long i = 0; i <= n; i++) { for (long long j = 0; j <= m; j++) { for (long long z = 0; z <= k; z++) { long long temp = max(d[i][j][z][0], d[i][j][z][1]); d[i + 1][j][z][0] = max(d[i + 1][j][z][0], temp); d[i][j + 1][z][0] = max(d[i][j + 1][z][0], temp); if (s[i] == t[j]) { d[i + 1][j + 1][z + 1][1] = max(d[i + 1][j + 1][z + 1][1], d[i][j][z][0] + 1); if (z > 0) { d[i + 1][j + 1][z][1] = max(d[i + 1][j + 1][z][1], d[i][j][z][1] + 1); } } } } } cout << *max_element(d[n][m][0], d[n][m][k] + 2) << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { string a; cin >> a; if (a[0] >= a && a[0] <= z ) a[0] -= 32; cout << a; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLRBN_SYMBOL_V
`define SKY130_FD_SC_LP__DLRBN_SYMBOL_V
/**
* dlrbn: Delay latch, inverted reset, inverted enable,
* complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlrbn (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE_N
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLRBN_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main(int argc, char** argv) { int T; cin >> T; while (T--) { long long a, b, c, d; cin >> a >> b >> c >> d; d -= min(a, d / c) * c; if (d > b) puts( NO ); else puts( YES ); } return 0; } |
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: bg4_new.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module bg4_new (
address,
clock,
q);
input [14:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../sprites-new/bg4-new.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32768"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "15"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../sprites-new/bg4-new.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32768"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 15 0 INPUT NODEFVAL "address[14..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 15 0 address 0 0 15 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL bg4_new.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg4_new.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg4_new.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg4_new.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg4_new_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg4_new_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.2
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module Resize_opr_linearbkb_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk);
parameter DWIDTH = 8;
parameter AWIDTH = 13;
parameter MEM_SIZE = 4097;
input[AWIDTH-1:0] addr0;
input ce0;
output reg[DWIDTH-1:0] q0;
input[AWIDTH-1:0] addr1;
input ce1;
input[DWIDTH-1:0] d1;
input we1;
input clk;
(* ram_style = "block" *)reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
always @(posedge clk)
begin
if (ce0)
begin
q0 <= ram[addr0];
end
end
always @(posedge clk)
begin
if (ce1)
begin
if (we1)
begin
ram[addr1] <= d1;
end
end
end
endmodule
`timescale 1 ns / 1 ps
module Resize_opr_linearbkb(
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd4097;
parameter AddressWidth = 32'd13;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
output[DataWidth - 1:0] q0;
input[AddressWidth - 1:0] address1;
input ce1;
input we1;
input[DataWidth - 1:0] d1;
Resize_opr_linearbkb_ram Resize_opr_linearbkb_ram_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.q0( q0 ),
.addr1( address1 ),
.ce1( ce1 ),
.we1( we1 ),
.d1( d1 ));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; int n, m, rt; int p[20][N], sz[N]; bool vis[N]; int dep[N], yr[N]; int cur = 1, pos[N], chainhd[N], chain[N], rpos[N]; int L[100 * N], R[100 * N], t[100 * N], root[N], nxt = 1, num; int query[N], a[N], b[N], k[N], y[N]; vector<int> g[N]; void build(int id, int x, int y) { if (x == y) { return; } L[id] = nxt++; R[id] = nxt++; int mid = (x + y) >> 1; build(L[id], x, mid); build(R[id], mid + 1, y); } int update(int id, int x, int y, int l) { if (l < x or l > y) return id; int ID = nxt++; if (x == y) { t[ID] = t[id] + 1; return ID; } int mid = (x + y) >> 1; L[ID] = update(L[id], x, mid, l); R[ID] = update(R[id], mid + 1, y, l); t[ID] = t[L[ID]] + t[R[ID]]; return ID; } void dfs(int x) { vis[x] = 1; sz[x] = 1; for (auto it : g[x]) { if (!vis[it]) { dep[it] = dep[x] + 1; dfs(it); sz[x] += sz[it]; } } } void per_dfs(int x) { vis[x] = 1; root[x] = update(root[p[0][x]], 1, m, yr[x]); for (auto it : g[x]) { if (!vis[it]) { per_dfs(it); } } } int lca(int u, int v) { if (dep[u] < dep[v]) swap(u, v); int diff = dep[u] - dep[v]; for (int i = 0; i < 18; i++) { if ((diff >> i) & 1) u = p[i][u]; } if (u == v) return u; for (int i = 17; i > -1; i--) { if (p[i][u] != p[i][v]) { u = p[i][u]; v = p[i][v]; } } return p[0][u]; } void HLD(int x) { if (chainhd[num] == 0) chainhd[num] = x; pos[x] = cur; rpos[cur] = x; cur++; chain[x] = num; int mx = 0, hv = -1; for (auto it : g[x]) { if (it != p[0][x]) { if (sz[it] >= mx) { mx = sz[it]; hv = it; } } } if (hv == -1) return; HLD(hv); for (auto it : g[x]) { if (it != hv and it != p[0][x]) { num++; HLD(it); } } } int per_query(int id, int x, int y, int l, int r) { if (l > y or r < x) return 0; if (l <= x and r >= y) return t[id]; int mid = (x + y) >> 1; int ans = per_query(L[id], x, mid, l, r) + per_query(R[id], mid + 1, y, l, r); return ans; } int search(int u, int l, int r, int k, int y, int i) { if (k == 1 and (yr[u] <= y or yr[u] >= i)) return u; while (l < r) { int mid = (l + r) >> 1; int node = rpos[mid]; int x = per_query(root[u], 1, m, y + 1, i) - per_query(root[node], 1, m, y + 1, i); x = dep[u] - dep[node] - x; if (yr[node] <= y or yr[node] >= i) x++; if (x >= k) { l = mid + 1; } else { r = mid; } } return rpos[l - 1]; } int query_hld(int u, int v, int k, int y, int i) { u = p[0][u]; int a = chain[u], b = chain[v]; while (a != b) { int hd = chainhd[a]; int x = per_query(root[u], 1, m, y + 1, i) - per_query(root[hd], 1, m, y + 1, i); if (yr[hd] >= y + 1 and yr[hd] < i) x++; x = dep[u] - dep[hd] + 1 - x; if (x >= k) { int l = pos[hd], r = pos[u]; return search(u, l, r, k, y, i); } else { k -= x; u = p[0][hd]; a = chain[u]; } } if (u == v) { return -1; } int l = pos[v] + 1, r = pos[u]; return search(u, l, r, k, y, i); } int count(int u, int v, int y, int i) { u = p[0][u]; if (dep[u] <= dep[v]) return 0; int ans = per_query(root[u], 1, m, y + 1, i) - per_query(root[v], 1, m, y + 1, i); ans = dep[u] - dep[v] - ans; return ans; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &p[0][i]); if (p[0][i] == 0) { rt = i; continue; } g[p[0][i]].push_back(i); } for (int i = 1; i < 18; i++) { for (int j = 1; j <= n; j++) { if (p[i - 1][j] > 0) p[i][j] = p[i - 1][p[i - 1][j]]; } } dep[rt] = 1; dfs(rt); HLD(rt); scanf( %d , &m); build(nxt++, 1, m); int ty; for (int i = 1; i <= m; i++) { scanf( %d , &ty); if (ty == 1) { scanf( %d , &ty); yr[ty] = i; query[i] = 0; } else { query[i] = 1; scanf( %d%d%d%d , a + i, b + i, k + i, y + i); } } memset(vis, 0, sizeof(vis)); root[0] = 1; pos[0] = 0; chain[0] = 0; per_dfs(rt); for (int i = 1; i <= m; i++) { if (query[i]) { int l = lca(a[i], b[i]); if (a[i] == l) { int x = count(b[i], l, y[i], i); int ans; if (x >= k[i]) { ans = query_hld(b[i], l, x - k[i] + 1, y[i], i); } else { ans = -1; } printf( %d n , ans); } else if (b[i] == l) { int x = count(a[i], l, y[i], i); int ans; if (x >= k[i]) { ans = query_hld(a[i], l, k[i], y[i], i); } else { ans = -1; } printf( %d n , ans); } else { int x = count(a[i], l, y[i], i); int ans; if (x >= k[i]) { ans = query_hld(a[i], l, k[i], y[i], i); } else { k[i] -= x; if (yr[l] <= y[i] or yr[l] >= i) k[i]--; if (k[i] == 0) ans = l; else { x = count(b[i], l, y[i], i); if (x >= k[i]) ans = query_hld(b[i], l, x - k[i] + 1, y[i], i); else ans = -1; } } printf( %d n , ans); } } } } |
//lpm_divide CBX_SINGLE_OUTPUT_FILE="ON" LPM_DREPRESENTATION="UNSIGNED" LPM_HINT="LPM_REMAINDERPOSITIVE=TRUE" LPM_NREPRESENTATION="UNSIGNED" LPM_TYPE="LPM_DIVIDE" LPM_WIDTHD=32 LPM_WIDTHN=64 denom numer quotient remain
//VERSION_BEGIN 16.0 cbx_mgl 2016:04:27:18:06:48:SJ cbx_stratixii 2016:04:27:18:05:34:SJ cbx_util_mgl 2016:04:27:18:05:34:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = lpm_divide 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module mgpik
(
denom,
numer,
quotient,
remain) /* synthesis synthesis_clearbox=1 */;
input [31:0] denom;
input [63:0] numer;
output [63:0] quotient;
output [31:0] remain;
wire [63:0] wire_mgl_prim1_quotient;
wire [31:0] wire_mgl_prim1_remain;
lpm_divide mgl_prim1
(
.denom(denom),
.numer(numer),
.quotient(wire_mgl_prim1_quotient),
.remain(wire_mgl_prim1_remain));
defparam
mgl_prim1.lpm_drepresentation = "UNSIGNED",
mgl_prim1.lpm_nrepresentation = "UNSIGNED",
mgl_prim1.lpm_type = "LPM_DIVIDE",
mgl_prim1.lpm_widthd = 32,
mgl_prim1.lpm_widthn = 64,
mgl_prim1.lpm_hint = "LPM_REMAINDERPOSITIVE=TRUE";
assign
quotient = wire_mgl_prim1_quotient,
remain = wire_mgl_prim1_remain;
endmodule //mgpik
//VALID FILE
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFXBP_BLACKBOX_V
`define SKY130_FD_SC_LS__SDFXBP_BLACKBOX_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__sdfxbp (
Q ,
Q_N,
CLK,
D ,
SCD,
SCE
);
output Q ;
output Q_N;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFXBP_BLACKBOX_V
|
#include <bits/stdc++.h> long long nmax[11] = {0, 9, 99, 999, 9999, 99999, 999999, 9999999, 99999999, 999999999, 9999999999LL}; long long P[11][11]; long long cnt[11][11][11], C[11][11], totalcnt[11][11], tmp; long long nsel[11][11][11][11][11], fact[11], nways; int N, x, y, len, i, j, jstart, nx, ny, cnx, cny, difx, dify, nextx, nexty; void ComputeComb() { int i, j; C[0][0] = 1; for (i = 1; i < 11; i++) { C[i][0] = 1; for (j = 1; j <= i; j++) { C[i][j] = (C[i - 1][j - 1] + C[i - 1][j]) % 1000000007; } } } inline int extended_gcd(long long A, long long B, long long &X, long long &Y) { if (B == 0) { X = 1; Y = 0; return A; } long long X0, Y0, D; D = extended_gcd(B, A % B, X0, Y0); X = Y0; Y = X0 - (A / B) * Y0; return D; } long long inv[11]; void ComputeInv() { long long garbage; for (int i = 1; i < 11; i++) { extended_gcd(i, 1000000007, inv[i], garbage); inv[i] %= 1000000007; while (inv[i] < 0) inv[i] += 1000000007; } } void ComputeFact() { fact[0] = 1; for (int i = 1; i < 11; i++) { fact[i] = (fact[i - 1] * i) % 1000000007; } } void ComputeP() { int i, j; for (i = 0; i < 11; i++) { P[i][0] = 1; for (j = 1; j < 11; j++) P[i][j] = (P[i][j - 1] * i) % 1000000007; } } int digits[11], ndigits; void GetN(int N) { ndigits = 0; while (N > 0) { digits[ndigits] = N % 10; N /= 10; ndigits++; } } long long totalcnt2[11][11]; void TestBruteForce() { int x, y, i, j; for (i = 1; i <= N; i++) { x = y = 0; j = i; while (j > 0) { if (j % 10 == 4) x++; else if (j % 10 == 7) y++; j /= 10; } totalcnt2[x][y]++; } for (x = 0; x < 11; x++) for (y = 0; y < 11; y++) if (totalcnt[x][y] != totalcnt2[x][y]) { fprintf(stderr, !!! x=%d y=%d: %I64d %I64d n , x, y, totalcnt[x][y], totalcnt2[x][y]); } } int main() { ComputeComb(); ComputeInv(); ComputeFact(); ComputeP(); scanf( %d , &N); GetN(N); for (len = 1; len < 11; len++) for (x = 0; x < 11 && x <= len; x++) for (y = 0; y < 11 && x + y <= len; y++) { cnt[len][x][y] = 0; if (len < ndigits) { if (x == 0 && y == 0) tmp = P[8][len] % 1000000007; else { tmp = (C[len][x] * C[len - x][y]); tmp = (tmp * P[8][len - x - y]); } cnt[len][x][y] = tmp; } else if (len == ndigits) { nx = ny = 0; for (i = ndigits - 1; i >= 0; i--) { if (i == ndigits - 1) jstart = 1; else jstart = 0; for (j = jstart; j < digits[i]; j++) { cnx = nx; cny = ny; if (j == 4) cnx++; else if (j == 7) cny++; if (cnx <= x && cny <= y) { difx = x - cnx; dify = y - cny; if (difx == 0 && dify == 0) cnt[len][x][y] = (cnt[len][x][y] + P[8][i]); else cnt[len][x][y] = (cnt[len][x][y] + cnt[i][difx][dify]); } } if (digits[i] == 4) nx++; else if (digits[i] == 7) ny++; } if (nx == x && ny == y) cnt[len][x][y]++; } if (len >= ndigits - 1) { totalcnt[x][y] += cnt[len][x][y]; if (x == 0 && y == 0 && len == ndigits - 1) totalcnt[x][y]--; } } for (x = 0; x < 11; x++) for (y = 0; y < 11; y++) if (totalcnt[x][y] > 0) { } nways = 1; for (i = 0; i <= 6; i++) { if (i > 0) { nways = (nways * (totalcnt[0][0] - i + 1)) % 1000000007; nways = (nways * inv[i]) % 1000000007; } nsel[0][0][0][0][i] = nways; } for (x = 0; x < 11; x++) for (y = 0; y < 11; y++) for (nx = 0; nx < 11; nx++) for (ny = 0; ny < 11; ny++) for (i = 0; i <= 6; i++) if (nsel[x][y][nx][ny][i] > 0) { cnx = x; cny = y + 1; if (cny >= 11) { cnx++; cny = 0; } if (cnx >= 11) break; nways = 1; for (j = 0; j <= 6; j++) { nextx = nx + j * cnx; nexty = ny + j * cny; if (nextx >= 11 || nexty >= 11 || i + j > 6) break; if (j > 0) { nways = (nways * (totalcnt[cnx][cny] - j + 1)) % 1000000007; nways = (nways * inv[j]) % 1000000007; } tmp = (nways * nsel[x][y][nx][ny][i]) % 1000000007; nsel[cnx][cny][nextx][nexty][i + j] = (nsel[cnx][cny][nextx][nexty][i + j] + tmp) % 1000000007; } } long long answer = 0; for (x = 0; x < 11; x++) for (y = 0; y < 11; y++) for (nx = 0; nx < 11; nx++) for (ny = 0; ny < 11; ny++) if (nx + ny < x + y) { tmp = totalcnt[x][y]; tmp = (tmp * nsel[11 - 1][11 - 1][nx][ny][6]) % 1000000007; answer = (answer + tmp) % 1000000007; } printf( %I64d n , (answer * fact[6]) % 1000000007); return 0; } |
/*
* Milkyminer
*
* Copyright (c) 2011
* Copyleft 2012
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns/1ps
module system(
input clk50,
// UART
input uart_rx,
output uart_tx,
// GPIO
// input btn1,
// input btn2,
// input btn3,
output led1,
output led2
// Exp miner
//output [EXT_PORTS-1:0] extminer_txd,
//input [EXT_PORTS-1:0] extminer_rxd,
// Expansion connector
// input [11:0] exp
//DIP
);
// The LOOP_LOG2 parameter determines how unrolled the SHA-256
// calculations are. For example, a setting of 1 will completely
// unroll the calculations, resulting in 128 rounds and a large, fast
// design.
//
// A setting of 2 will result in 64 rounds, with half the size and
// half the speed. 3 will be 32 rounds, with 1/4th the size and speed.
// And so on.
//
// Valid range: [0, 5]
`ifdef CONFIG_LOOP_LOG2
parameter LOOP_LOG2 = `CONFIG_LOOP_LOG2;
`else
parameter LOOP_LOG2 = 5;
`endif
// No need to adjust these parameters
localparam [5:0] LOOP = (6'd1 << LOOP_LOG2);
// The nonce will always be larger at the time we discover a valid
// hash. This is its offset from the nonce that gave rise to the valid
// hash (except when LOOP_LOG2 == 0 or 1, where the offset is 131 or
// 66 respectively).
localparam [31:0] GOLDEN_NONCE_OFFSET = (32'd1 << (7 - LOOP_LOG2)) + 32'd1;
////
reg [255:0] state = 0;
reg [511:0] data = 0;
reg [31:0] nonce = 32'h00000000;
//// DCM
wire hash_clk;
wire hash_clk_dcm;
// 50/5*8 = 80Mhz
DCM_SP #(
.CLKDV_DIVIDE(2.0), // 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
.CLKFX_DIVIDE(5), // 1 to 32
.CLKFX_MULTIPLY(8), // 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(20.0),
.CLKOUT_PHASE_SHIFT("NONE"),
.CLK_FEEDBACK("NONE"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
.DUTY_CYCLE_CORRECTION("TRUE"),
.PHASE_SHIFT(0),
.STARTUP_WAIT("TRUE")
) clkgen_hash (
.CLK0(),
.CLK90(),
.CLK180(),
.CLK270(),
.CLK2X(),
.CLK2X180(),
.CLKDV(),
.CLKFX(hash_clk_dcm),
.CLKFX180(),
.LOCKED(),
.CLKFB(),
.CLKIN(clk50),
.RST(1'b0),
.PSEN(1'b0)
);
BUFG b1(
.I(hash_clk_dcm),
.O(hash_clk)
);
//// Hashers
wire [255:0] hash, hash2;
reg [5:0] cnt = 6'd0;
reg feedback = 1'b0;
sha256_transform #(.LOOP(LOOP)) uut (
.clk(hash_clk),
.feedback(feedback),
.cnt(cnt),
.rx_state(state),
.rx_input(data),
.tx_hash(hash)
);
sha256_transform #(.LOOP(LOOP)) uut2 (
.clk(hash_clk),
.feedback(feedback),
.cnt(cnt),
.rx_state(256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667),
.rx_input({256'h0000010000000000000000000000000000000000000000000000000080000000, hash}),
.tx_hash(hash2)
);
//// Virtual Wire Control
reg [255:0] midstate_buf = 0, data_buf = 0;
wire [255:0] midstate_vw, data2_vw;
serial_receive serrx (.clk(hash_clk), .RxD(uart_rx), .midstate(midstate_vw), .data2(data2_vw));
//// Virtual Wire Output
reg [31:0] golden_nonce = 0;
reg serial_send;
wire serial_busy;
serial_transmit sertx (.clk(hash_clk), .TxD(uart_tx), .send(serial_send), .busy(serial_busy), .word(golden_nonce));
//// Control Unit
reg is_golden_ticket = 1'b0;
reg feedback_d1 = 1'b1;
wire [5:0] cnt_next;
wire [31:0] nonce_next;
wire feedback_next;
wire reset;
assign reset = 1'b0;
assign cnt_next = reset ? 6'd0 : (LOOP == 1) ? 6'd0 : (cnt + 6'd1) & (LOOP-1);
// On the first count (cnt==0), load data from previous stage (no feedback)
// on 1..LOOP-1, take feedback from current stage
// This reduces the throughput by a factor of (LOOP), but also reduces the design size by the same amount
assign feedback_next = (LOOP == 1) ? 1'b0 : (cnt_next != {(LOOP_LOG2){1'b0}});
assign nonce_next =
reset ? 32'd0 :
feedback_next ? nonce : (nonce + 32'd1);
always @ (posedge hash_clk)
begin
midstate_buf <= midstate_vw;
data_buf <= data2_vw;
cnt <= cnt_next;
feedback <= feedback_next;
feedback_d1 <= feedback;
// Give new data to the hasher
state <= midstate_buf;
data <= {384'h000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000, nonce_next, data_buf[95:0]};
nonce <= nonce_next;
// Check to see if the last hash generated is valid.
is_golden_ticket <= (hash2[255:224] == 32'h00000000) && !feedback_d1;
if(is_golden_ticket)
begin
// TODO: Find a more compact calculation for this
if (LOOP == 1)
golden_nonce <= nonce - 32'd131;
else if (LOOP == 2)
golden_nonce <= nonce - 32'd66;
else
golden_nonce <= nonce - GOLDEN_NONCE_OFFSET;
if (!serial_busy) serial_send <= 1;
end // if (is_golden_ticket)
else
serial_send <= 0;
end
/* debug led serial */
//assign led1 = ~uart_rx;
assign led1 = |golden_nonce;
assign led2 = ~uart_tx;
endmodule
|
#include <bits/stdc++.h> #define fi first #define se second #define mp make_pair using namespace std; typedef pair <int, int> pii; struct UF { int fa[3010]; void clear(int n) { for (int i = 1; i <= n; i++) { fa[i] = i; } } int find(int x) { if (fa[x] == x) return x; return fa[x] = find(fa[x]); } void merge(int x, int y) { x = find(x), y = find(y); if (x == y) return ; fa[y] = x; } }uf; vector <int> ans; vector <pii> all; int G[3010][3010], in[3010], cnt[3010], nin[3010]; int n, m; void dfs(int x) { for (int i = 1; i <= n; i++) { if (!G[x][i]) continue; G[x][i] = G[i][x] = 0; dfs(i); } ans.push_back(x); } void print() { reverse(ans.begin(), ans.end()); printf( %d n , ans.size()); for (int i = 0; i < ans.size(); i++) { printf( %d , ans[i]); } printf( n ); } int main() { scanf( %d%d , &n, &m); for (int i = 0; i < m; i++) { int x, y; scanf( %d%d , &x, &y); G[x][y] = G[y][x] = 1, in[x]++, in[y]++; all.push_back(mp(x, y)); } int tot = 0; for (int i = 1; i <= n; i++) { tot += in[i] & 1; } if (tot <= 2) { int rt = 1; for (int i = 1; i <= n; i++) { if (in[i] & 1) { rt = i; break; } } dfs(rt); print(); return 0; } for (int i = 1; i <= n; i++) { if (in[i] % 2 == 0) continue; for (int j = 1; j <= n; j++) { if (G[i][j] || i == j) cnt[j]++; } } for (int i = 1; i <= n; i++) { if (cnt[i] < tot - 1) continue; for (int j = 1; j <= n; j++) { if (i == j) continue; if (cnt[i] == tot - 1 && G[i][j]) continue; if (in[j] % 2 == 0) continue; uf.clear(n); for (int i = 1; i <= n; i++) { nin[i] = 0; } for (int k = 0; k < all.size(); k++) { int x = all[k].fi, y = all[k].se; if ((x == i || y == i) && x + y - i != j && in[x + y - i] & 1) continue; uf.merge(x, y); nin[x]++, nin[y]++; } int eq = -1; for (int k = 1; k <= n; k++) { if (!nin[k]) continue; int val = uf.find(k); if (eq == -1) eq = val; if (eq != val) goto END; } for (int k = 1; k <= n; k++) { if (k == i || k == j) continue; if (in[k] & 1) { G[i][k] = G[k][i] = 0; ans.push_back(i); ans.push_back(k); } } ans.push_back(-1); dfs(j); print(); return 0; END:; } } printf( 0 n ); return 0; } |
`default_nettype none
`define WIDTH 16
module j1(
input wire clk,
input wire resetq,
output wire io_rd,
output wire io_wr,
output wire [15:0] mem_addr,
output wire mem_wr,
output wire [`WIDTH-1:0] dout,
input wire [`WIDTH-1:0] io_din,
output wire [12:0] code_addr,
input wire [15:0] insn);
reg [4:0] dsp, dspN; // data stack pointer
reg [`WIDTH-1:0] st0, st0N; // top of data stack
reg dstkW; // data stack write
reg [12:0] pc /* verilator public_flat */, pcN; // program counter
wire [12:0] pc_plus_1 = pc + 13'd1;
reg rstkW; // return stack write
wire [`WIDTH-1:0] rstkD; // return stack write value
reg reboot = 1;
assign mem_addr = st0[15:0];
assign code_addr = pcN;
// The D and R stacks
wire [`WIDTH-1:0] st1, rst0;
reg [1:0] dspI, rspI;
stack2 #(.DEPTH(16)) dstack(.clk(clk), .rd(st1), .we(dstkW), .wd(st0), .delta(dspI));
stack2 #(.DEPTH(19)) rstack(.clk(clk), .rd(rst0), .we(rstkW), .wd(rstkD), .delta(rspI));
// stack2 #(.DEPTH(24)) dstack(.clk(clk), .rd(st1), .we(dstkW), .wd(st0), .delta(dspI));
// stack2 #(.DEPTH(24)) rstack(.clk(clk), .rd(rst0), .we(rstkW), .wd(rstkD), .delta(rspI));
always @*
begin
// Compute the new value of st0
casez ({pc[12], insn[15:8]})
9'b1_???_?????: st0N = insn; // literal
9'b0_1??_?????: st0N = { {(`WIDTH - 15){1'b0}}, insn[14:0] }; // literal
9'b0_000_?????: st0N = st0; // jump
9'b0_010_?????: st0N = st0; // call
9'b0_001_?????: st0N = st1; // conditional jump
9'b0_011_?0000: st0N = st0; // ALU operations...
9'b0_011_?0001: st0N = st1;
9'b0_011_?0010: st0N = st0 + st1;
9'b0_011_?0011: st0N = st0 & st1;
9'b0_011_?0100: st0N = st0 | st1;
9'b0_011_?0101: st0N = st0 ^ st1;
9'b0_011_?0110: st0N = ~st0;
9'b0_011_?0111: st0N = {`WIDTH{(st1 == st0)}};
9'b0_011_?1000: st0N = {`WIDTH{($signed(st1) < $signed(st0))}};
9'b0_011_?1001: st0N = {st0[`WIDTH - 1], st0[`WIDTH - 1:1]};
9'b0_011_?1010: st0N = {st0[`WIDTH - 2:0], 1'b0};
9'b0_011_?1011: st0N = rst0;
9'b0_011_?1100: st0N = io_din;
9'b0_011_?1101: st0N = io_din;
9'b0_011_?1110: st0N = {{(`WIDTH - 5){1'b0}}, dsp};
9'b0_011_?1111: st0N = {`WIDTH{(st1 < st0)}};
default: st0N = {`WIDTH{1'bx}};
endcase
end
wire func_T_N = (insn[6:4] == 1);
wire func_T_R = (insn[6:4] == 2);
wire func_write = (insn[6:4] == 3);
wire func_iow = (insn[6:4] == 4);
wire func_ior = (insn[6:4] == 5);
wire is_alu = !pc[12] & (insn[15:13] == 3'b011);
assign mem_wr = !reboot & is_alu & func_write;
assign dout = st1;
assign io_wr = !reboot & is_alu & func_iow;
assign io_rd = !reboot & is_alu & func_ior;
assign rstkD = (insn[13] == 1'b0) ? {{(`WIDTH - 14){1'b0}}, pc_plus_1, 1'b0} : st0;
always @*
begin
casez ({pc[12], insn[15:13]})
4'b1_???,
4'b0_1??: {dstkW, dspI} = {1'b1, 2'b01};
4'b0_001: {dstkW, dspI} = {1'b0, 2'b11};
4'b0_011: {dstkW, dspI} = {func_T_N, {insn[1:0]}};
default: {dstkW, dspI} = {1'b0, 2'b00};
endcase
dspN = dsp + {dspI[1], dspI[1], dspI[1], dspI};
casez ({pc[12], insn[15:13]})
4'b1_???: {rstkW, rspI} = {1'b0, 2'b11};
4'b0_010: {rstkW, rspI} = {1'b1, 2'b01};
4'b0_011: {rstkW, rspI} = {func_T_R, insn[3:2]};
default: {rstkW, rspI} = {1'b0, 2'b00};
endcase
casez ({reboot, pc[12], insn[15:13], insn[7], |st0})
7'b1_0_???_?_?: pcN = 0;
7'b0_0_000_?_?,
7'b0_0_010_?_?,
7'b0_0_001_?_0: pcN = insn[12:0];
7'b0_1_???_?_?,
7'b0_0_011_1_?: pcN = rst0[13:1];
default: pcN = pc_plus_1;
endcase
end
always @(negedge resetq or posedge clk)
begin
if (!resetq) begin
reboot <= 1'b1;
{ pc, dsp, st0} <= 0;
end else begin
reboot <= 0;
{ pc, dsp, st0} <= { pcN, dspN, st0N };
end
end
endmodule
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
(* blackbox *)
module altsyncram(data_a, address_a, wren_a, rden_a, q_a, data_b, address_b, wren_b, rden_b,
q_b, clock0, clock1, clocken0, clocken1, clocken2, clocken3, aclr0, aclr1,
addressstall_a, addressstall_b);
parameter clock_enable_input_b = "ALTERNATE";
parameter clock_enable_input_a = "ALTERNATE";
parameter clock_enable_output_b = "NORMAL";
parameter clock_enable_output_a = "NORMAL";
parameter wrcontrol_aclr_a = "NONE";
parameter indata_aclr_a = "NONE";
parameter address_aclr_a = "NONE";
parameter outdata_aclr_a = "NONE";
parameter outdata_reg_a = "UNREGISTERED";
parameter operation_mode = "SINGLE_PORT";
parameter intended_device_family = "MAX 10 FPGA";
parameter outdata_reg_a = "UNREGISTERED";
parameter lpm_type = "altsyncram";
parameter init_type = "unused";
parameter ram_block_type = "AUTO";
parameter lpm_hint = "ENABLE_RUNTIME_MOD=NO";
parameter power_up_uninitialized = "FALSE";
parameter read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ";
parameter width_byteena_a = 1;
parameter numwords_b = 0;
parameter numwords_a = 0;
parameter widthad_b = 1;
parameter width_b = 1;
parameter widthad_a = 1;
parameter width_a = 1;
// Port A declarations
output [35:0] q_a;
input [35:0] data_a;
input [7:0] address_a;
input wren_a;
input rden_a;
// Port B declarations
output [35:0] q_b;
input [35:0] data_b;
input [7:0] address_b;
input wren_b;
input rden_b;
// Control signals
input clock0, clock1;
input clocken0, clocken1, clocken2, clocken3;
input aclr0, aclr1;
input addressstall_a;
input addressstall_b;
// TODO: Implement the correct simulation model
endmodule // altsyncram
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A22OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__A22OI_FUNCTIONAL_PP_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__a22oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y , nand0_out, nand1_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A22OI_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int M = 1200000; const int inf = 0x3f3f3f3f; int n, m, k; vector<int> g[M]; int ans; int dfs(int u, int f) { vector<int> v = {0, 0}; for (int to : g[u]) { if (to == f) continue; v.push_back(dfs(to, u)); } sort(v.begin(), v.end()); reverse(v.begin(), v.end()); int sz = g[u].size(); ans = max(ans, v[0] + v[1] + sz + 1); return v[0] + sz - 1; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t; cin >> t; for (int _ = (1); _ <= (t); ++_) { cin >> n; int u, v; for (int i = (1); i <= (n); ++i) g[i].clear(); for (int i = (2); i <= (n); ++i) { cin >> u >> v; g[u].push_back(v); g[v].push_back(u); } ans = 0; dfs(1, 1); cout << ans << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long f[2][1000005]; long long h[1000005]; int n; int main() { scanf( %d , &n); for (int i = (0); i < (n); i++) scanf( %lld , h + i); long long res = 0; for (int i = (1); i < (n + 1); i++) { long long mx = h[i - 1] - 1; f[1][i] = h[i - 1] - 1; if (i != 1) { if (h[i - 1] >= h[i - 2]) { long long mn = h[i - 1] - h[i - 2] + 1; f[1][i] += (mx - mn + 1) * f[0][i - 1]; } else { long long mn = 1; f[1][i] += (mx - mn + 1) * f[0][i - 1]; } } f[1][i] %= 1000000007ll; res += f[1][i]; if (i != n) { long long mn = h[i - 1] >= h[i] ? h[i - 1] - h[i] + 1 : 1; f[0][i] += mx - mn + 1; if (i != 1) { if (h[i - 1] >= h[i - 2]) { long long MN = max(mn, h[i - 1] - h[i - 2] + 1); f[0][i] += (mx - MN + 1) * f[0][i - 1]; } else { f[0][i] += (mx - mn + 1) * f[0][i - 1]; } } } f[0][i] %= 1000000007ll; } printf( %lld n , res % 1000000007ll); } |
/***********************************************************************************************************************
* Copyright (C) 2016 Andrew Zonenberg and contributors *
* *
* This program is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General *
* Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) *
* any later version. *
* *
* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied *
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for *
* more details. *
* *
* You should have received a copy of the GNU Lesser General Public License along with this program; if not, you may *
* find one here: *
* https://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt *
* or you may search the http://www.gnu.org website for the version 2.1 license, or you may write to the Free Software *
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA *
**********************************************************************************************************************/
`default_nettype none
/**
INPUTS:
PGA input on pin 8
OUTPUTS:
PGA output on pin 7
TEST PROCEDURE:
Sweep analog waveform from 0 to 500 mV on pin 8
Output should be 2x the input voltage
*/
module PGA(bg_ok, vin, pgaout);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// I/O declarations
(* LOC = "P20" *)
output wire bg_ok;
(* LOC = "P8" *)
(* IBUF_TYPE = "ANALOG" *)
input wire vin;
(* LOC = "P7" *)
(* IBUF_TYPE = "ANALOG" *)
output wire pgaout;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// System reset stuff
//Power-on reset
wire por_done;
GP_POR #(
.POR_TIME(500)
) por (
.RST_DONE(por_done)
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// 1.0V bandgap voltage reference (used by a lot of the mixed signal IP)
GP_BANDGAP #(
.AUTO_PWRDN(0),
.CHOPPER_EN(1),
.OUT_DELAY(550)
) bandgap (
.OK(bg_ok)
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Programmable-gain analog amplifier
GP_PGA #(
.GAIN(2),
.INPUT_MODE("SINGLE")
) pga (
.VIN_P(vin),
.VIN_N(),
.VIN_SEL(1'b1),
.VOUT(pgaout)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21OI_2_V
`define SKY130_FD_SC_HD__A21OI_2_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog wrapper for a21oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a21oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a21oi_2 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a21oi_2 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21OI_2_V
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ddr_of_pre_fifo.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Feb 08 2011
// \___\/\___\
//
//Device : 7 Series
//Design Name : DDR3 SDRAM
//Purpose : Extends the depth of a PHASER OUT_FIFO up to 4 entries
//Reference :
//Revision History :
//*****************************************************************************
/******************************************************************************
**$Id: ddr_of_pre_fifo.v,v 1.1 2011/06/02 08:35:07 mishra Exp $
**$Date: 2011/06/02 08:35:07 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_of_pre_fifo.v,v $
******************************************************************************/
`timescale 1 ps / 1 ps
module mig_7series_v2_3_ddr_of_pre_fifo #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter DEPTH = 4, // # of entries
parameter WIDTH = 32 // data bus width
)
(
input clk, // clock
input rst, // synchronous reset
input full_in, // FULL flag from OUT_FIFO
input wr_en_in, // write enable from controller
input [WIDTH-1:0] d_in, // write data from controller
output wr_en_out, // write enable to OUT_FIFO
output [WIDTH-1:0] d_out, // write data to OUT_FIFO
output afull // almost full signal to controller
);
// # of bits used to represent read/write pointers
localparam PTR_BITS
= (DEPTH == 2) ? 1 :
((DEPTH == 3) || (DEPTH == 4)) ? 2 :
(((DEPTH == 5) || (DEPTH == 6) ||
(DEPTH == 7) || (DEPTH == 8)) ? 3 :
DEPTH == 9 ? 4 : 'bx);
// Set watermark. Always give the MC 5 cycles to engage flow control.
localparam ALMOST_FULL_VALUE = DEPTH - 5;
integer i;
reg [WIDTH-1:0] mem[0:DEPTH-1] ;
reg [8:0] my_empty /* synthesis syn_maxfan = 3 */;
reg [5:0] my_full /* synthesis syn_maxfan = 3 */;
reg [PTR_BITS-1:0] rd_ptr /* synthesis syn_maxfan = 10 */;
reg [PTR_BITS-1:0] wr_ptr /* synthesis syn_maxfan = 10 */;
(* KEEP = "TRUE", max_fanout = 50 *) reg [PTR_BITS-1:0] rd_ptr_timing /* synthesis syn_maxfan = 10 */;
(* KEEP = "TRUE", max_fanout = 50 *) reg [PTR_BITS-1:0] wr_ptr_timing /* synthesis syn_maxfan = 10 */;
reg [PTR_BITS:0] entry_cnt;
wire [PTR_BITS-1:0] nxt_rd_ptr;
wire [PTR_BITS-1:0] nxt_wr_ptr;
wire [WIDTH-1:0] mem_out;
(* max_fanout = 50 *) wire wr_en;
assign d_out = my_empty[0] ? d_in : mem_out;
assign wr_en_out = !full_in && (!my_empty[1] || wr_en_in);
assign wr_en = wr_en_in & ((!my_empty[3] & !full_in)|(!my_full[2] & full_in));
always @ (posedge clk)
if (wr_en)
mem[wr_ptr] <= #TCQ d_in;
assign mem_out = mem[rd_ptr];
assign nxt_rd_ptr = (rd_ptr + 1'b1)%DEPTH;
always @ (posedge clk)
begin
if (rst) begin
rd_ptr <= 'b0;
rd_ptr_timing <= 'b0;
end
else if ((!my_empty[4]) & (!full_in)) begin
rd_ptr <= nxt_rd_ptr;
rd_ptr_timing <= nxt_rd_ptr;
end
end
always @ (posedge clk)
begin
if (rst)
my_empty <= 9'h1ff;
else begin
if (my_empty[2] & !my_full[3] & full_in & wr_en_in)
my_empty[3:0] <= 4'b0000;
else if (!my_empty[2] & !my_full[3] & !full_in & !wr_en_in) begin
my_empty[0] <= (nxt_rd_ptr == wr_ptr_timing);
my_empty[1] <= (nxt_rd_ptr == wr_ptr_timing);
my_empty[2] <= (nxt_rd_ptr == wr_ptr_timing);
my_empty[3] <= (nxt_rd_ptr == wr_ptr_timing);
end
if (my_empty[8] & !my_full[5] & full_in & wr_en_in)
my_empty[8:4] <= 5'b00000;
else if (!my_empty[8] & !my_full[5] & !full_in & !wr_en_in) begin
my_empty[4] <= (nxt_rd_ptr == wr_ptr_timing);
my_empty[5] <= (nxt_rd_ptr == wr_ptr_timing);
my_empty[6] <= (nxt_rd_ptr == wr_ptr_timing);
my_empty[7] <= (nxt_rd_ptr == wr_ptr_timing);
my_empty[8] <= (nxt_rd_ptr == wr_ptr_timing);
end
end
end
assign nxt_wr_ptr = (wr_ptr + 1'b1)%DEPTH;
always @ (posedge clk)
begin
if (rst) begin
wr_ptr <= 'b0;
wr_ptr_timing <= 'b0;
end
else if ((wr_en_in) & ((!my_empty[5] & !full_in) | (!my_full[1] & full_in))) begin
wr_ptr <= nxt_wr_ptr;
wr_ptr_timing <= nxt_wr_ptr;
end
end
always @ (posedge clk)
begin
if (rst)
my_full <= 6'b000000;
else if (!my_empty[6] & my_full[0] & !full_in & !wr_en_in)
my_full <= 6'b000000;
else if (!my_empty[6] & !my_full[0] & full_in & wr_en_in) begin
my_full[0] <= (nxt_wr_ptr == rd_ptr_timing);
my_full[1] <= (nxt_wr_ptr == rd_ptr_timing);
my_full[2] <= (nxt_wr_ptr == rd_ptr_timing);
my_full[3] <= (nxt_wr_ptr == rd_ptr_timing);
my_full[4] <= (nxt_wr_ptr == rd_ptr_timing);
my_full[5] <= (nxt_wr_ptr == rd_ptr_timing);
end
end
always @ (posedge clk)
begin
if (rst)
entry_cnt <= 'b0;
else if (wr_en_in & full_in & !my_full[4])
entry_cnt <= entry_cnt + 1'b1;
else if (!wr_en_in & !full_in & !my_empty[7])
entry_cnt <= entry_cnt - 1'b1;
end
assign afull = (entry_cnt >= ALMOST_FULL_VALUE);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int sum; vector<int> x; int main() { int n; cin >> n; x.push_back(-2099999999); for (int i = 0; i < n; i++) { int a; cin >> a; x.push_back(a); } sort(x.begin(), x.end()); for (int i = 1; i <= n; i++) sum += abs(i - x[i]); cout << sum << endl; } |
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: write_data_path.v
// /___/ /\ Date Last Modified:
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This is top level of write path .
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_0_write_data_path #(
parameter TCQ = 100,
parameter FAMILY = "SPARTAN6",
parameter MEM_TYPE = "DDR3",
parameter ADDR_WIDTH = 32,
parameter START_ADDR = 32'h00000000,
parameter BL_WIDTH = 6,
parameter nCK_PER_CLK = 4, // DRAM clock : MC clock
parameter MEM_BURST_LEN = 8,
parameter DWIDTH = 32,
parameter DATA_PATTERN = "DGEN_ALL", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
parameter NUM_DQ_PINS = 8,
parameter SEL_VICTIM_LINE = 3, // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
parameter MEM_COL_WIDTH = 10,
parameter EYE_TEST = "FALSE"
)
(
input clk_i,
input [9:0] rst_i,
output cmd_rdy_o,
input cmd_valid_i,
input cmd_validB_i,
input cmd_validC_i,
input [31:0] prbs_fseed_i,
input [3:0] data_mode_i,
input mem_init_done_i,
input wr_data_mask_gen_i,
// input [31:0] m_addr_i,
input [31:0] simple_data0 ,
input [31:0] simple_data1 ,
input [31:0] simple_data2 ,
input [31:0] simple_data3 ,
input [31:0] simple_data4 ,
input [31:0] simple_data5 ,
input [31:0] simple_data6 ,
input [31:0] simple_data7 ,
input [31:0] fixed_data_i,
input mode_load_i,
input [31:0] addr_i,
input [BL_WIDTH-1:0] bl_i,
// input [5:0] port_data_counts_i,// connect to data port fifo counts
input memc_cmd_full_i,
input data_rdy_i,
output data_valid_o,
output last_word_wr_o,
output [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] data_o,
output [(NUM_DQ_PINS*nCK_PER_CLK*2/8) - 1:0] data_mask_o,
output data_wr_end_o
);
wire data_valid;
reg cmd_rdy;
assign data_valid_o = data_valid;// & data_rdy_i;
mig_7series_v2_0_wr_data_gen #
(
.TCQ (TCQ),
.FAMILY (FAMILY),
.MEM_TYPE (MEM_TYPE),
.NUM_DQ_PINS (NUM_DQ_PINS),
.MEM_BURST_LEN (MEM_BURST_LEN),
.BL_WIDTH (BL_WIDTH),
.START_ADDR (START_ADDR),
.nCK_PER_CLK (nCK_PER_CLK),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
.DATA_PATTERN (DATA_PATTERN),
.DWIDTH (DWIDTH),
.COLUMN_WIDTH (MEM_COL_WIDTH),
.EYE_TEST (EYE_TEST)
)
wr_data_gen(
.clk_i (clk_i ),
.rst_i (rst_i[9:5]),
.prbs_fseed_i (prbs_fseed_i),
.wr_data_mask_gen_i (wr_data_mask_gen_i),
.mem_init_done_i (mem_init_done_i),
.data_mode_i (data_mode_i ),
.cmd_rdy_o (cmd_rdy_o ),
.cmd_valid_i (cmd_valid_i ),
.cmd_validB_i (cmd_validB_i ),
.cmd_validC_i (cmd_validC_i ),
.last_word_o (last_word_wr_o ),
// .port_data_counts_i (port_data_counts_i),
// .m_addr_i (m_addr_i ),
.fixed_data_i (fixed_data_i),
.simple_data0 (simple_data0),
.simple_data1 (simple_data1),
.simple_data2 (simple_data2),
.simple_data3 (simple_data3),
.simple_data4 (simple_data4),
.simple_data5 (simple_data5),
.simple_data6 (simple_data6),
.simple_data7 (simple_data7),
.mode_load_i (mode_load_i),
.addr_i (addr_i ),
.bl_i (bl_i ),
.memc_cmd_full_i (memc_cmd_full_i),
.data_rdy_i (data_rdy_i ),
.data_valid_o ( data_valid ),
.data_o (data_o ),
.data_wr_end_o (data_wr_end_o),
.data_mask_o (data_mask_o)
);
endmodule
|
`timescale 1 ps / 1 ps
module zynq_1_wrapper
(BRAM_PORTB_addr,
BRAM_PORTB_clk,
BRAM_PORTB_din,
BRAM_PORTB_dout,
BRAM_PORTB_we,
DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
fclk_out_25,
gpio,
spi_clk,
spi_out);
input [10:0]BRAM_PORTB_addr;
input BRAM_PORTB_clk;
input [7:0]BRAM_PORTB_din;
output [7:0]BRAM_PORTB_dout;
input [0:0]BRAM_PORTB_we;
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
output fclk_out_25;
output [31:0]gpio;
output spi_clk;
output spi_out;
wire [10:0]BRAM_PORTB_addr;
wire BRAM_PORTB_clk;
wire [7:0]BRAM_PORTB_din;
wire [7:0]BRAM_PORTB_dout;
wire [0:0]BRAM_PORTB_we;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
wire fclk_out_25;
wire [31:0]gpio;
wire spi_clk;
wire spi_out;
zynq_1 zynq_1_i
(.BRAM_PORTB_addr(BRAM_PORTB_addr),
.BRAM_PORTB_clk(BRAM_PORTB_clk),
.BRAM_PORTB_din(BRAM_PORTB_din),
.BRAM_PORTB_dout(BRAM_PORTB_dout),
.BRAM_PORTB_we(BRAM_PORTB_we),
.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
.fclk_out_25(fclk_out_25),
.gpio(gpio),
.spi_clk(spi_clk),
.spi_out(spi_out));
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:37:00 11/09/2016
// Design Name:
// Module Name: button_painter
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module button_painter(
input wire [1:0] row,
input wire [2:0] column,
input wire [3:0] in_row,
output reg [11:0] code
);
wire [4:0] d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, ds, dr, dm, dd, dmod, dsig, di;
reg [4:0] number;
reg [4:0] data;
num_0 n0 (
.in_row({in_row-2'b11}[2:0]),
.out_code(d0)
);
num_1 n1 (
.in_row({in_row-2'b11}[2:0]),
.out_code(d1)
);
num_2 n2 (
.in_row({in_row-2'b11}[2:0]),
.out_code(d2)
);
num_3 n3 (
.in_row({in_row-2'b11}[2:0]),
.out_code(d3)
);
num_4 n4 (
.in_row({in_row-2'b11}[2:0]),
.out_code(d4)
);
num_5 n5 (
.in_row({in_row-2'b11}[2:0]),
.out_code(d5)
);
num_6 n6 (
.in_row({in_row-2'b11}[2:0]),
.out_code(d6)
);
num_7 n7 (
.in_row({in_row-2'b11}[2:0]),
.out_code(d7)
);
num_8 n8 (
.in_row({in_row-2'b11}[2:0]),
.out_code(d8)
);
num_9 n9 (
.in_row({in_row-2'b11}[2:0]),
.out_code(d9)
);
bsuma bsum (
.in_row({in_row-2'b11}[2:0]),
.out_code(ds)
);
bresta bres (
.in_row({in_row-2'b11}[2:0]),
.out_code(dr)
);
bmultip bmul (
.in_row({in_row-2'b11}[2:0]),
.out_code(dm)
);
bdiv bd (
.in_row({in_row-2'b11}[2:0]),
.out_code(dd)
);
bmod bm (
.in_row({in_row-2'b11}[2:0]),
.out_code(dmod)
);
bigual bi (
.in_row({in_row-2'b11}[2:0]),
.out_code(di)
);
bsigno bsig (
.in_row({in_row-2'b11}[2:0]),
.out_code(dsig)
);
always @ *
begin
number = {(row * 6) + column}[4:0];
case (number)
5'b00000: data = d0;
5'b00001: data = d1;
5'b00010: data = d2;
5'b00011: data = d3;
5'b00100: data = d4;
5'b00101: data = d5;
5'b00110: data = d6;
5'b00111: data = d7;
5'b01000: data = d8;
5'b01001: data = d9;
5'b01010: data = ds;
5'b01011: data = dr;
5'b01100: data = dm;
5'b01101: data = dd;
5'b01110: data = dmod;
5'b01111: data = di;
5'b10000: data = dsig;
default: data = 5'b0;
endcase
code = 12'b0;
if((in_row > 2) && (in_row < 11))
code[8:4] = data;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYGATE4SD2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__DLYGATE4SD2_BEHAVIORAL_PP_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__dlygate4sd2 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYGATE4SD2_BEHAVIORAL_PP_V |
`timescale 1ns / 100ps
/* This module creates a byte-wide assembly of GPIA_BIT_INs.
*/
module GPIA_BYTE_IN(
input [7:0] out_i,
input [7:0] inp_i,
input [7:0] ddr_i,
input stb_i,
output [7:0] q_o
);
GPIA_BIT_IN bit0(
.out_i(out_i[0]),
.inp_i(inp_i[0]),
.ddr_i(ddr_i[0]),
.stb_i(stb_i),
.q_o(q_o[0])
);
GPIA_BIT_IN bit1(
.out_i(out_i[1]),
.inp_i(inp_i[1]),
.ddr_i(ddr_i[1]),
.stb_i(stb_i),
.q_o(q_o[1])
);
GPIA_BIT_IN bit2(
.out_i(out_i[2]),
.inp_i(inp_i[2]),
.ddr_i(ddr_i[2]),
.stb_i(stb_i),
.q_o(q_o[2])
);
GPIA_BIT_IN bit3(
.out_i(out_i[3]),
.inp_i(inp_i[3]),
.ddr_i(ddr_i[3]),
.stb_i(stb_i),
.q_o(q_o[3])
);
GPIA_BIT_IN bit4(
.out_i(out_i[4]),
.inp_i(inp_i[4]),
.ddr_i(ddr_i[4]),
.stb_i(stb_i),
.q_o(q_o[4])
);
GPIA_BIT_IN bit5(
.out_i(out_i[5]),
.inp_i(inp_i[5]),
.ddr_i(ddr_i[5]),
.stb_i(stb_i),
.q_o(q_o[5])
);
GPIA_BIT_IN bit6(
.out_i(out_i[6]),
.inp_i(inp_i[6]),
.ddr_i(ddr_i[6]),
.stb_i(stb_i),
.q_o(q_o[6])
);
GPIA_BIT_IN bit7(
.out_i(out_i[7]),
.inp_i(inp_i[7]),
.ddr_i(ddr_i[7]),
.stb_i(stb_i),
.q_o(q_o[7])
);
endmodule
|
//------------------------------------------------------------------------------
//
// Copyright 2011, Benjamin Gelb. All Rights Reserved.
// See LICENSE file for copying permission.
//
//------------------------------------------------------------------------------
//
// Author: Ben Gelb ()
//
// Brief Description:
// Reed-Solomon Encoder. Processes one symbol per clock.
//
//------------------------------------------------------------------------------
`ifndef _ZL_RS_ENCODER_V_
`define _ZL_RS_ENCODER_V_
`include "zl_gf_mul.v"
module zl_rs_encoder #
(
parameter N = 0, // codeword length
parameter K = 0, // message length
parameter M = 0, // symbol width
parameter G_x = 0, // RS generator polynomial
parameter Gf_poly = 0
)
(
input clk,
input rst_n,
//
input data_in_req,
output data_in_ack,
input [M-1:0] data_in,
//
output data_out_req,
input data_out_ack,
output [M-1:0] data_out
);
localparam Gf_width = M;
// unpack G_x vector
reg [M-1:0] g [0:N-K-1];
wire [M*(N-K)-1:0] g_x_packed;
assign g_x_packed = G_x;
integer i;
always @(*) begin
for(i=0;i<N-K;i=i+1) begin
g[i] = g_x_packed[M*(i+1)-1-:M];
end
end
reg [M-1:0] cur_sym_count;
wire cur_sym_is_data;
// stall logic
wire stall;
assign data_out_req = data_in_req;
assign data_in_ack = data_out_ack && cur_sym_is_data;
assign stall = !data_in_ack && !(data_out_ack && !cur_sym_is_data);
// keep symbol counter
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
cur_sym_count <= {M{1'b0}};
end
else if(!stall && cur_sym_count == N-1) begin
cur_sym_count <= {M{1'b0}};
end
else if(!stall) begin
cur_sym_count <= cur_sym_count + 1'b1;
end
end
// is output data or check symbols?
assign cur_sym_is_data = (cur_sym_count < K);
// encoder logic
wire [M-1:0] feedback;
wire [M-1:0] gf_mul_out [0:N-K-1];
reg [M-1:0] rs_check_reg [0:N-K-1];
genvar j;
generate
for(j=0;j<N-K;j=j+1) begin : gf_mul_blocks
zl_gf_mul #
(
.Gf_width(Gf_width),
.Gf_poly(Gf_poly)
)
gf_mul
(
.a(feedback),
.b(g[j]),
.out(gf_mul_out[j])
);
end
endgenerate
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
for(i=0;i<N-K;i=i+1) begin
rs_check_reg[i] <= {M{1'b0}};
end
end
else if(!stall) begin
rs_check_reg[0] <= gf_mul_out[0];
for(i=1;i<N-K;i=i+1) begin
rs_check_reg[i] <= rs_check_reg[i-1] ^ gf_mul_out[i];
end
end
end
assign feedback = (cur_sym_is_data ? rs_check_reg[N-K-1] ^ data_in : {M{1'b0}});
// output assignment
assign data_out = (cur_sym_is_data ? data_in : rs_check_reg[N-K-1]);
endmodule // zl_rs_encoder
`endif // _ZL_RS_ENCODER_V_
|
#include <bits/stdc++.h> using namespace std; const int inf(1010101010); struct uf { int par[5005], rank[5005]; int ff(int x) { return par[x] == x ? x : par[x] = ff(par[x]); } void uu(int x, int y) { x = ff(x), y = ff(y); if (x == y) return; if (rank[x] > rank[y]) par[y] = x; else if (rank[x] < rank[y]) par[x] = y; else rank[x]++, par[y] = x; } uf(int n) { for (int i(0); i < (n); i++) par[i] = i, rank[i] = 0; } }; int n, m, k; int wt[100005]; pair<int, int> e[100005]; int perm[100005]; struct mycmp { bool operator()(int i, int j) const { return wt[i] < wt[j]; } }; void kruskal_met_0(vector<int>& ret) { uf G(n); for (int i(0); i < (m); i++) { int eid(perm[i]), x(e[eid].first), y(e[eid].second); if (x == 0 || y == 0) { ret.push_back(eid); G.uu(x, y); } } for (int i(0); i < (m); i++) { int eid(perm[i]), x(e[eid].first), y(e[eid].second), xr(G.ff(x)), yr(G.ff(y)); if (xr - yr) { ret.push_back(eid); G.uu(x, y); } } for (int i(0); i < (n); i++) if (G.ff(i) != G.ff(0)) { puts( -1 ); exit(0); } } void kruskal_wo_0(vector<int>& ret) { uf G(n); for (int i(0); i < (m); i++) { int eid(perm[i]), x(e[eid].first), y(e[eid].second), xr(G.ff(x)), yr(G.ff(y)); if (x == 0 || y == 0) continue; if (xr - yr) { ret.push_back(eid); G.uu(x, y); } } } int koppel[5005]; int main() { cin >> n >> m >> k; int deg0(0); for (int i(0); i < (m); i++) { int x, y, w; cin >> x >> y >> w; x--, y--; wt[i] = w; e[i].first = x, e[i].second = y; if (x == 0 || y == 0) deg0++; } if (deg0 < k) { puts( -1 ); exit(0); } for (int i(0); i < (m); i++) perm[i] = i; sort(perm, perm + m, mycmp()); vector<int> mst_met, mst_wo; kruskal_met_0(mst_met); kruskal_wo_0(mst_wo); uf G(n); for (int i(0); i < (n); i++) koppel[i] = inf; vector<int> doen; for (__typeof((mst_met).end()) it((mst_met).begin()); it != (mst_met).end(); ++it) { int eid(*it), x(e[eid].first), y(e[eid].second), xr(G.ff(x)), yr(G.ff(y)); if (x == 0) koppel[yr] = wt[eid]; else if (y == 0) koppel[xr] = wt[eid]; else { int mi(min(koppel[xr], koppel[yr])); koppel[xr] = koppel[yr] = mi; G.uu(x, y); doen.push_back(eid); } } for (int iteratie(0); iteratie < (deg0 - k); iteratie++) { pair<int, int> opt(inf, 0); for (__typeof((mst_wo).end()) it((mst_wo).begin()); it != (mst_wo).end(); ++it) { int eid(*it), x(e[eid].first), y(e[eid].second), xr(G.ff(x)), yr(G.ff(y)); if (xr == yr) continue; opt = min(opt, make_pair(wt[eid] - max(koppel[xr], koppel[yr]), eid)); } if (opt.first == inf) { puts( -1 ); return 0; } int eid(opt.second), x(e[eid].first), y(e[eid].second), xr(G.ff(x)), yr(G.ff(y)); int mik(min(koppel[xr], koppel[yr])); koppel[xr] = koppel[yr] = mik; G.uu(x, y); doen.push_back(eid); } uf T(n); for (__typeof((doen).end()) it((doen).begin()); it != (doen).end(); ++it) { int eid(*it), x(e[eid].first), y(e[eid].second); assert(T.ff(x) != T.ff(y)); T.uu(x, y); } if (((int)(doen).size()) != n - 1 - k) { puts( -1 ); return 0; } for (int i(0); i < (m); i++) { int eid(perm[i]), x(e[eid].first), y(e[eid].second), xr(T.ff(x)), yr(T.ff(y)); if (x == 0 || y == 0) { if (xr - yr) { doen.push_back(eid); T.uu(x, y); } } } cout << ((int)(doen).size()) << endl; int som(0); for (__typeof((doen).end()) it((doen).begin()); it != (doen).end(); ++it) { cout << (*it + 1) << ; som += wt[*it]; } cout << endl; } |
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_lfsr12(
clk,
nrst,
ena,
word
);
input clk;
input nrst;
input ena;
output reg [11:0] word;
always @(posedge clk or negedge nrst) begin
if(~nrst) begin
word <= 12'b101001101011;
end
else if(ena) begin
word[11] <= word[0];
word[10] <= word[11];
word[9] <= word[10];
word[8] <= word[9];
word[7] <= word[8];
word[6] <= word[7];
word[5] <= word[6] ^ word[0];
word[4] <= word[5];
word[3] <= word[4] ^ word[0];
word[2] <= word[3];
word[1] <= word[2];
word[0] <= word[1] ^ word[0];
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; using int64 = long long; constexpr int64 P = 1000000007; struct FiniteField { private: int64 x; public: FiniteField(int64 x) : x(x) { if (x > P || x < 0) { cerr << Invalied FiniteField! << endl; exit(1); } } FiniteField() : x(0) {} int64 Value() const { return x; } inline FiniteField operator+(FiniteField o) const { FiniteField r(*this); r += o; return r; } inline FiniteField operator-(FiniteField o) const { FiniteField r(*this); r -= o; return r; } inline FiniteField operator*(FiniteField o) const { FiniteField r(*this); r *= o; return r; } inline FiniteField operator/(FiniteField o) const { FiniteField r(*this); r /= o; return r; } inline void operator+=(FiniteField o) { x = (x + o.x) % P; } inline void operator-=(FiniteField o) { x = (x + P - o.x) % P; } inline void operator*=(FiniteField o) { x = (x * o.x) % P; } void operator/=(FiniteField o) { int64 p = P - 2; while (p) { if (p % 2) { *this *= o; } o *= o; p /= 2; } } }; template <typename T> vector<vector<T>> operator*(const vector<vector<T>>& a1, const vector<vector<T>>& a2) { int n = a1.size(); int m = a1[0].size(); if (a2.size() != m) { cerr << Matrix dimensions don t match for multiplication! << endl; exit(1); } int l = a2[0].size(); vector<vector<T>> result(n, vector<T>(l)); for (int i = 0; i < n; i++) { for (int j = 0; j < l; j++) { for (int k = 0; k < m; k++) { result[i][j] += a1[i][k] * a2[k][j]; } } } return result; } template <typename T> vector<T> operator*(const vector<vector<T>>& matrix, const vector<T>& v) { int n = matrix.size(); int m = matrix[0].size(); if (v.size() != m) { cerr << Matrix and vector dimensions don t match for multiplication! << endl; exit(1); } vector<T> result(n); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { result[i] += matrix[i][j] * v[j]; } } return result; } template <typename T> vector<vector<T>> Make2DVector(int d1, int d2, T default_value) { return vector<vector<T>>(d1, vector<T>(d2, default_value)); } template <typename T> vector<vector<vector<T>>> Make3DVector(int d1, int d2, int d3, T default_value) { return vector<vector<vector<T>>>( d1, vector<vector<T>>(d2, vector<T>(d3, default_value))); } constexpr int DEBUG = 0; int main() { ios::sync_with_stdio(false); cin.tie(0); int64 n; int d; cin >> n >> d; auto shifts = Make3DVector<FiniteField>(d, d + 1, d + 1, 0); for (int k = 0; k < d; k++) { for (int i = 0; i < d; i++) { shifts[k][i][(i + k) % d] = 1; } shifts[k][d][d] = 1; } auto units = Make3DVector<FiniteField>(d, d + 1, d + 1, 0); for (int k = 0; k < d; k++) { for (int i = 0; i < d + 1; i++) { units[k][i][i] = 1; } for (int i = 0; i < d + 1; i++) { units[k][k][i] = 1; } } auto identity = Make2DVector<FiniteField>(d + 1, d + 1, 0); for (int i = 0; i < d + 1; i++) { identity[i][i] = 1; } map<int64, vector<vector<FiniteField>>> cache; function<vector<vector<FiniteField>>(int64)> find_matrix = [&](int64 p) -> vector<vector<FiniteField>> { if (cache.find(p) != cache.end()) { return cache.find(p)->second; } if (p <= d) { auto matrix = identity; for (int k = 0; k < p; k++) { matrix = units[k] * matrix; } return matrix; } int64 child_p = d; while ((p + child_p - 1) / child_p > d) child_p *= d; auto child = find_matrix(child_p); auto matrix = child; int64 remaining_p = p; remaining_p -= child_p; for (int k = 1; k < d; k++) { if (remaining_p >= child_p) { matrix = shifts[d - k] * child * shifts[k] * matrix; remaining_p -= child_p; } else if (remaining_p > 0) { matrix = shifts[d - k] * find_matrix(remaining_p) * shifts[k] * matrix; remaining_p = 0; } else { break; } } cache[p] = matrix; return matrix; }; if (DEBUG) cerr << PHASE 1 << endl; auto matrix = find_matrix(n); if (DEBUG) cerr << PHASE 2 << endl; vector<FiniteField> base_vector(d + 1); base_vector[d] = 1; auto final_vector = matrix * base_vector; FiniteField ans = 0; for (const auto& x : final_vector) ans += x; cout << ans.Value() << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); string s; int i = 0; cin >> s; int z = 0, o = 0; while (s[i] == 0 ) { i++; } for (; i < s.length(); i++) { if (s[i] == 0 ) { z++; } else { if (!o) { o = s.length() - i; } } } if (z >= 6 && o >= 7) { cout << Yes << n ; } else { cout << No << n ; } return 0; } |
// $Id: tss_max32.v,v 1.6 1999/01/20 17:34:54 wsnyder Exp $
//============================================================================
`time_scale
module tss_max32 (/*AUTOARG*/
// Outputs
max,
// Inputs
a, b
);
//======================================================================
// Inputs/Outputs
//======================================================================
input [31:0] a; // Time a
input [31:0] b; // Time b
output [31:0] max; // MAX (a,b)
//======================================================================
// Automatic Wire/Register Declarations
//======================================================================
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
// End of automatics
//======================================================================
// Comparison
//======================================================================
wire alessb; // a<b or carry
//Verilint 110 off // WARNING: Incompatible width
DW01_cmp2 #(31) cmp (.LT_LE(alessb), .GE_GT(unused_ok),
.A(a[30:0]),
.B(b[30:0]),
.LEQ(1'b0), .TC(1'b0));
//Verilint 110 on // WARNING: Incompatible width
// Note because a has more bits we MUST choose it if a[31:8]==b[31:8]!
wire sela = ((a[31] != b[31]) ^ alessb);
wire [31:0] max = (sela ? b : a);
endmodule
|
`default_nettype none
//`include "gci_std_display_parameter.h"
module gci_std_display_top #(
parameter P_VRAM_SIZE = 307200,
parameter P_VRAM_INDEX = 0,
parameter P_AREA_H = 640,
parameter P_AREA_V = 480,
parameter P_AREAA_HV_N = 19,
parameter P_MEM_ADDR_N = 23
)(
//System
input wire iCLOCK,
input wire inRESET,
input wire iRESET_SYNC,
//Display Clock
input wire iDISP_CLOCK,
//Write Reqest
input wire iIF_WR_REQ,
output wire oIF_WR_BUSY,
input wire iIF_WR_RW,
input wire [31:0] iIF_WR_ADDR,
input wire [31:0] iIF_WR_DATA,
//Read
output wire oIF_RD_VALID,
input wire iIF_RD_BUSY,
output wire oIF_RD_DATA,
//VRAM IF
output wire oVRAM_ARBIT_REQ,
input wire iVRAM_ARBIT_ACK,
output wire oVRAM_ARBIT_FINISH,
output wire oVRAM_ENA,
input wire iVRAM_BUSY,
output wire oVRAM_RW,
output wire [P_MEM_ADDR_N-1:0] oVRAM_ADDR,
output wire [31:0] oVRAM_DATA,
input wire iVRAM_VALID,
output wire oVRAM_BUSY,
input wire [31:0] iVRAM_DATA,
//Display
output wire oDISP_CLOCK,
output wire onDISP_RESET,
output wire oDISP_ENA,
output wire oDISP_BLANK,
output wire onDISP_HSYNC,
output wire onDISP_VSYNC,
output wire [9:0] oDISP_DATA_R,
output wire [9:0] oDISP_DATA_G,
output wire [9:0] oDISP_DATA_B
);
/****************************************************************
Hub Interface Controller
****************************************************************/
gci_std_display_hub_interface HUB_IF_CTRL(
//System
.iCLOCK(),
.inRESET(),
.iRESET_SYNC(),
//HUB(Reqest/Write)
.iHUB_REQ(),
.oHUB_BUSY(),
.iHUB_RW(),
.iHUB_ADDR(),
.iHUB_DATA(),
//HUB(Read)
.oHUB_VALID(),
.iHUB_BUSY(),
.oHUB_DATA(),
//Register(Request/Write)
.oREG_ENA(),
.oREG_RW(),
.oREG_ADDR(),
.oREG_DATA(),
//Register(Read)
.iREG_VALID(),
.oREG_BUSY(),
.iREG_DATA(),
//Command(Request/Write)
.oCOMM_VALID(),
.oCOMM_SEQ(),
.iCOMM_BUSY(),
.oCOMM_RW(),
.oCOMM_ADDR(),
.oCOMM_DATA(),
//Command(Read)
.iCOMM_VALID(),
.oCOMM_BUSY(),
.iCOMM_ADDR(),
.iCOMM_DATA()
);
/****************************************************************
Display Struct Register
****************************************************************/
wire register_info_charactor;
wire [1:0] register_info_color;
gci_std_display_register #(P_VRAM_SIZE) REGISTER(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iRESET_SYNC(1'b0),
//Write
.iWR_VALID(register_ctrl_condition && !register_busy_condition && iIF_WR_RW),
.iWR_ADDR(iIF_WR_ADDR[3:0]),
.iWR_DATA(iIF_WR_DATA),
//Read
.iRD_VALID(register_ctrl_condition && !register_busy_condition && !iIF_WR_RW),
.oRD_BUSY(),
.iRD_ADDR(iIF_WR_ADDR[3:0]),
.oRD_VALID(),
.iRD_BUSY(),
.oRD_DATA(),
//Info
.oINFO_CHARACTER(register_info_charactor),
.oINFO_COLOR(register_info_color)
);
/****************************************************************
Display Command Decoder
****************************************************************/
wire command2request_valid;
wire request2command_busy;
wire [P_MEM_ADDR_N:0] command2request_addr;
wire [23:0] command2request_data;
gci_std_display_command #(
P_AREA_H,
P_AREA_V,
P_AREAA_HV_N,
P_MEM_ADDR_N
)COMMAND(
.iCLOCK(),
.inRESET(),
//Register
.iREG_MODE(register_info_charactor), //[0]Bitmap | [1]Charactor
//BUS
.iIF_VALID(display_ctrl_condition && !display_busy_condition || sequence_ctrl_condition && !sequence_busy_condition),
.iIF_SEQ(sequence_ctrl_condition),
.oIF_BUSY(),
.iIF_RW(),
.iIF_ADDR(),
.iIF_DATA(),
//Output
.oIF_VALID(command2request_valid),
.iIF_BUSY(request2command_busy),
.oIF_ADDR(command2request_addr),
.oIF_DATA(command2request_data)
);
/****************************************************************
Display Write/Read Controller
****************************************************************/
wire request2vramif_req;
wire vramif2request_ack;
wire request2vramif_finish;
wire vramif2request_break;
wire vramif2request_busy;
wire request2vramif_ena;
wire request2vramif_rw;
wire [P_MEM_ADDR_N-1:0] request2vramif_addr;
wire [7:0] request2vramif_r;
wire [7:0] request2vramif_g;
wire [7:0] request2vramif_b;
wire vramif2request_valid;
wire request2vramif_busy;
wire [31:0] vramif2request_data;
gci_std_display_request_controller #(
P_AREA_H,
P_AREA_V,
P_AREAA_HV_N,
P_MEM_ADDR_N
)(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
//BUS
.iRQ_VALID(command2request_valid),
.oRQ_BUSY(request2command_busy),
.iRQ_ADDR(command2request_addr),
.iRQ_DATA(command2request_data),
//VRAM
.oRQ_VALID(),
.oRQ_BUSY(),
.oRQ_DATA(),
//VRAM IF
.oIF_REQ(request2vramif_req),
.iIF_ACK(vramif2request_ack),
.oIF_FINISH(request2vramif_finish),
.iIF_BREAK(vramif2request_break),
.iIF_BUSY(vramif2request_busy),
.oIF_ENA(request2vramif_ena),
.oIF_RW(request2vramif_rw),
.oIF_ADDR(request2vramif_addr),
.oIF_R(request2vramif_r),
.oIF_G(request2vramif_g),
.oIF_B(request2vramif_b),
.iIF_VALID(vramif2request_valid),
.oIF_BUSY(request2vramif_busy),
.iIF_DATA(vramif2request_data)
);
/****************************************************************
Vram Interface Controller
****************************************************************/
gci_std_display_vram_interface VRAM_IF_CTRL(
.iGCI_CLOCK(iGCI_CLOCK),
.inRESET(inRESET),
.iRESET_SYNC(1'b0),
//IF0 (Priority IF0>IF1)
.iIF0_REQ(vramread2vramif_req),
.oIF0_ACK(vramif2vramread_ack),
.iIF0_FINISH(vramread2vramif_finish),
.iIF0_ENA(vramread2vramif_ena),
.oIF0_BUSY(vramif2vramread_busy),
.iIF0_RW(1'b0),
.iIF0_ADDR(vramread2vramif_addr + P_VRAM_INDEX),
.iIF0_DATA(32'h0),
.oIF0_VALID(vramif2vramread_valid),
.iIF0_BUSY(1'b0),
.oIF0_DATA(vramif2vramread_data),
//IF1
.iIF1_REQ(request2vramif_req),
.oIF1_ACK(vramif2request_ack),
.iIF1_FINISH(request2vramif_finish),
.oIF1_BREAK(vramif2request_break),
.iIF1_ENA(request2vramif_ena),
.oIF1_BUSY(vramif2request_busy),
.iIF1_RW(request2vramif_rw),
.iIF1_ADDR(request2vramif_addr + P_VRAM_INDEX),
.iIF1_DATA(request2vramif_data),
.oIF1_VALID(vramif2request_valid),
.iIF1_BUSY(request2vramif_busy),
.oIF1_DATA(vramif2request_data),
//Vram Interface
.oVRAM_ARBIT_REQ(oVRAM_ARBIT_REQ),
.iVRAM_ARBIT_ACK(iVRAM_ARBIT_ACK),
.oVRAM_ARBIT_FINISH(oVRAM_ARBIT_FINISH),
.oVRAM_ENA(oVRAM_ENA),
.iVRAM_BUSY(iVRAM_BUSY),
.oVRAM_RW(oVRAM_RW),
.oVRAM_ADDR(oVRAM_ADDR),
.oVRAM_DATA(oVRAM_DATA),
.iVRAM_VALID(iVRAM_VALID),
.oVRAM_BUSY(oVRAM_BUSY),
.iVRAM_DATA(iVRAM_DATAs)
);
/****************************************************************
Display Data Read Controller
****************************************************************/
wire vramread2vramif_req;
wire vramif2vramread_ack;
wire vramread2vramif_finish;
wire vramread2vramif_ena;
wire vramif2vramread_busy;
wire [P_MEM_ADDR_N-:0] vramread2vramif_addr;
wire vramif2vramread_valid;
wire [31:0] vramif2vramread_data;
gci_std_display_data_read VRAM_READ_CTRL(
.iGCI_CLOCK(iGCI_CLOCK),
.iDISP_CLOCK(iDISP_CLOCK),
.inRESET(inRESET),
.iRESET_SYNC(iRESET_SYNC),
//Read Request
.iRD_ENA(disptiming_data_req),
.iRD_SYNC(disptiming_data_sync),
.oRD_VALID(),
.oRD_DATA_R(oDISP_DATA_R),
.oRD_DATA_G(oDISP_DATA_G),
.oRD_DATA_B(oDISP_DATA_B),
//Memory IF
.oIF_REQ(vramread2vramif_req),
.iIF_ACK(vramif2vramread_ack),
.oIF_FINISH(vramread2vramif_finish),
.oIF_ENA(vramread2vramif_ena),
.iIF_BUSY(vramif2vramread_busy),
.oIF_ADDR(vramread2vramif_addr),
.iIF_VALID(vramif2vramread_valid),
.iIF_DATA(vramif2vramread_data)
);
/****************************************************************
Display Timing Generator
****************************************************************/
//Display timing
gci_std_display_timing_generator DISPLAY_TIMING(
.iDISP_CLOCK(iDISP_CLOCK),
.inRESET(inRESET),
.iRESET_SYNC(1'b0),
.oDATA_REQ(disptiming_data_req),
.oDATA_SYNC(disptiming_data_sync),
.onDISP_RESET(onDISP_RESET),
.oDISP_ENA(oDISP_ENA),
.oDISP_BLANK(oDISP_BLANK),
.onDISP_VSYNC(onDISP_VSYNC),
.onDISP_HSYNC(onDISP_HSYNC)
);
//Assign
assign oDISP_CLOCK = iDISP_CLOCK;
assign oIF_WR_BUSY = bus_req_wait;
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; int n, m; long long f(const string& s) { long long res = 0; for (int i = 0; i + 1 < s.size(); ++i) { if (s[i] != s[i + 1]) { res += (m - 1) * (n - i - 1); } } return res; } long long g(const string& s) { long long res = 0; for (int i = 0; i + 1 < s.size(); ++i) if (s[i] != s[i + 1]) { int j = i + 1; while (j + 1 < s.size() && s[j + 1] == s[j - 1]) ++j; long long l = j - i + 1; res += l * (l - 1) / 2; i = j - 1; } return res; } int main() { string s; cin >> n >> m >> s; long long res = n * (m - 1) + f(s); reverse(s.begin(), s.end()); res += f(s) - g(s); cout << res << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int n, i, j, k, p, c, x, m, a, b, d, y, t; cin >> t; while (t--) { cin >> n >> a >> b >> c >> d; x = (a - b) * n; y = (a + b) * n; if ((y < (c - d)) || (x > (c + d))) cout << No << endl; else cout << Yes << endl; } } |
#include <bits/stdc++.h> using namespace std; long long int tc, n, m, k; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; cin >> n; long long int k1, k2; cin >> k1; queue<long long int> q1; for (__typeof(k1) i = (0) - ((0) > (k1)); i != (k1) - ((0) > (k1)); i += 1 - 2 * ((0) > (k1))) { long long int a; cin >> a; q1.push(a); } cin >> k2; queue<long long int> q2; for (__typeof(k2) i = (0) - ((0) > (k2)); i != (k2) - ((0) > (k2)); i += 1 - 2 * ((0) > (k2))) { long long int a; cin >> a; q2.push(a); } long long int af = q1.front(); long long int bf = q2.front(); long long int sa = ((int)(q1).size()); long long int sb = ((int)(q2).size()); long long int ans = 0; while (((int)(q1).size()) && ((int)(q2).size())) { long long int a = q1.front(); long long int b = q2.front(); if ((ans > 4e7)) { cout << -1; return 0; } if (a < b) { q2.push(a); q2.push(b); } else { q1.push(b); q1.push(a); } q1.pop(); q2.pop(); ans++; } cout << ans << ; if (((int)(q1).size()) == 0) cout << 2; else cout << 1; return 0; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXS = 75, MAXK = 10, MAXQ = 30; const long long INF = 0x3f3f3f3f3f3f3f3f; int x, k, n, q, c[MAXK]; struct node { int p, w; } d[MAXQ]; bool operator<(const node &aa, const node &bb) { return aa.p < bb.p; } int sta[MAXS], scn, cnt[300], id[300]; struct Matrix { long long s[MAXS][MAXS]; Matrix() { memset(s, 0x3f, sizeof(s)); } } X, A, pw[30]; Matrix operator*(const Matrix &aa, const Matrix &bb) { Matrix cc; for (int i = 1; i <= scn; i++) for (int j = 1; j <= scn; j++) for (int k = 1; k <= scn; k++) cc.s[i][j] = min(cc.s[i][j], aa.s[i][k] + bb.s[k][j]); return cc; } void build_pw() { pw[0] = X; for (int i = 1; i < 30; i++) pw[i] = pw[i - 1] * pw[i - 1]; } Matrix get(int a) { Matrix ret; for (int i = 1; i <= scn; i++) ret.s[i][i] = 0; for (int i = 0; i < 30; i++) if (a >> i & 1) ret = ret * pw[i]; return ret; } int main() { scanf( %d%d%d%d , &x, &k, &n, &q); for (int i = 1; i <= k; i++) scanf( %d , &c[i]); for (int i = 1; i <= q; i++) scanf( %d%d , &d[i].p, &d[i].w); sort(d + 1, d + q + 1); for (int s = 1; s < (1 << k); s++) { cnt[s] = cnt[s >> 1] + (s & 1); if (cnt[s] == x) sta[++scn] = s, id[s] = scn; } for (int i = 1; i <= scn; i++) { if (sta[i] & 1) { for (int j = 1; j <= k; j++) if (!(sta[i] >> j & 1)) X.s[i][id[(sta[i] | (1 << j)) >> 1]] = c[j]; } else X.s[i][id[sta[i] >> 1]] = 0; } build_pw(); int cur = 1; long long delta = 0; for (int i = 1; i <= scn; i++) A.s[i][i] = 0; for (int i = 1; i <= q; i++) { if (d[i].p > n - x) delta += d[i].w; else { A = A * get(d[i].p - cur), cur = d[i].p; for (int j = 1; j <= scn; j++) for (int k = 1; k <= scn; k++) if (sta[k] & 1) A.s[j][k] += d[i].w; } } A = A * get(n - x + 1 - cur); printf( %lld n , A.s[1][1] + delta); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int _; for (cin >> _; _; _--) { int n; scanf( %d , &n); double a = 3.1415926535 / n; double cosa = cos(a); double r = sqrt(0.5 / (1 - cosa)); a = a / 4; cosa = cos(a); printf( %.9lf n , r * cosa * 2); } return 0; } |
#include <bits/stdc++.h> int main() { int tc; scanf( %d , &tc); while (tc--) { int n, i, z = -1, o = -1, s = 0, max = -1; scanf( %d , &n); char ss[n + 5], at[2]; scanf( %s , ss); int a[n], b[n], zero[n], one[n]; for (i = 0; i < n; i++) { at[0] = ss[i]; at[1] = 0 ; a[i] = atoi(at); } for (i = 0; i < n; i++) { if (!a[i]) { if (o >= 0) { zero[++z] = one[o--]; b[i] = zero[z]; } else { zero[++z] = ++s; b[i] = zero[z]; } } if (a[i]) { if (z >= 0) { one[++o] = zero[z--]; b[i] = one[o]; } else { one[++o] = ++s; b[i] = one[o]; } } if (max < b[i]) max = b[i]; } printf( %d n , max); for (i = 0; i < n; i++) printf( %d , b[i]); printf( n ); } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__NAND3_BEHAVIORAL_PP_V
/**
* nand3: 3-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__nand3 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , B, A, C );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND3_BEHAVIORAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND3B_BEHAVIORAL_V
`define SKY130_FD_SC_MS__AND3B_BEHAVIORAL_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__and3b (
X ,
A_N,
B ,
C
);
// Module ports
output X ;
input A_N;
input B ;
input C ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire and0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X, C, not0_out, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND3B_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; int fun(pair<int, int> x, pair<int, int> y) { return x.second < y.second; } int main() { vector<pair<int, int> > vii; int n, k; cin >> n >> k; for (int i = 0; i < n; i++) { int x; cin >> x; vii.push_back(make_pair(x, x % 10)); } int sum; while (k > 0) { sort(vii.begin(), vii.end(), fun); sum = 0; int flg = 1; for (int i = 0; i < n; i++) { if (vii[i].first == 100) ; else flg = 0; } if (!flg) { for (int i = n - 1; i >= 0; i--) { if (vii[i].first >= 100) { sum += 10; continue; } if (k > 0) { int ink = ((vii[i].first + 10) / 10) * 10 - vii[i].first; if (ink > k) ink = k; k = k - ink; vii[i].first += ink; vii[i].second = vii[i].first % 10; } sum += vii[i].first / 10; } } else { sum = n * 10; break; } } printf( %d n , sum); return 0; } |
#include <bits/stdc++.h> using namespace std; void solve() { int v; cin >> v; int a[9]; int t = 100000, x; for (long long i = 0; i < 9; ++i) { cin >> a[i]; t = min(t, a[i]); } if (t > v) { cout << -1; return; } x = v / t; while (x--) { for (int i = 8; i >= 0; i--) { if (a[i] <= v && (v - a[i]) / t == x) { cout << i + 1; v -= a[i]; break; } } } } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; int t = 1; while (t--) { solve(); } } |
// bsg_front_side_bus_hop_in
//
// this implements the front side bus
// input side. it does *not* have backwards
// flow control, since nodes are supposed
// to have enough buffering to accept
// all incoming packets.
//
`include "bsg_defines.v"
module bsg_front_side_bus_hop_in_no_fc #(parameter `BSG_INV_PARAM(width_p))
( input clk_i
, input reset_i
, input [width_p-1:0] data_i
, input v_i
// 0 is to the next switch
// 1 is to the local switch
, output [1:0][width_p-1:0] data_o
, output [1:0] v_o
, input local_accept_i
);
logic [width_p-1:0] data_r;
logic v_r;
// fixme: trade logic/speed for power
// and avoid fake transitions
assign data_o[0] = data_r;
assign v_o[0] = v_r;
// to local node
assign data_o[1] = data_r;
assign v_o[1] = v_r & local_accept_i;
bsg_dff_reset #( .width_p($bits(v_r)) )
v_reg
( .clk_i ( clk_i )
, .reset_i( reset_i )
, .data_i ( v_i )
, .data_o ( v_r )
);
bsg_dff #( .width_p($bits(data_r)) )
data_reg
( .clk_i ( clk_i )
, .data_i( data_i )
, .data_o( data_r )
);
endmodule
`BSG_ABSTRACT_MODULE(bsg_front_side_bus_hop_in_no_fc)
|
`include "uart.vh"
module uart_rx(
input clk_i,
input rx_i,
output [DATA_LENGTH - 1 : 0] tx_o,
output tx_o_v
);
localparam SAMPLE_RATE = `UART_RX_SAMPLE_RATE;
localparam SAMPLE_UPPER = `UART_RX_SAMPLE_UPPER;
localparam SAMPLE_MID = `UART_RX_SAMPLE_MID;
localparam SAMPLE_LOWER = `UART_RX_SAMPLE_LOWER;
localparam SAMPLE_WIDTH = $clog2(SAMPLE_RATE);
localparam PACKET_LENGTH = `UART_PACKET_LENGTH;
localparam PACKET_WIDTH = $clog2(PACKET_LENGTH);
localparam DATA_LENGTH = `UART_DATA_LENGTH;
localparam DATA_WIDTH = $clog2(DATA_LENGTH);
localparam ST_IDLE = 2'd0;
localparam ST_START = 2'd1;
localparam ST_DATA = 2'd2;
localparam ST_STOP = 2'd3;
reg [2 : 0] state = ST_IDLE;
reg rx_i_d = 0;
reg [PACKET_WIDTH - 1 : 0] ctr_bit = 0;
reg [SAMPLE_WIDTH - 1 : 0] ctr_sample = 0;
reg [SAMPLE_RATE - 1 : 0] rx_i_shift = 0;
reg rx_vote = 0;
reg [DATA_LENGTH - 1 : 0] s_tx_o = 0;
assign tx_o = s_tx_o;
assign tx_o_v = state == ST_STOP & rx_vote & ctr_sample == SAMPLE_UPPER;
always @ (posedge clk_i)
begin
if (ctr_sample == SAMPLE_RATE | state == ST_IDLE)
begin
ctr_sample <= 0;
end
else
begin
ctr_sample <= ctr_sample + 1;
end
end
always @ (posedge clk_i)
begin
if (state == ST_IDLE)
begin
ctr_bit <= 0;
end
else if (ctr_sample == SAMPLE_RATE - 1)
begin
ctr_bit <= ctr_bit + 1;
end
end
always @ (posedge clk_i)
begin
rx_i_shift <= { {rx_i_shift[SAMPLE_RATE - 2 : 0]} , {rx_i} };
end
always @ (posedge clk_i)
begin
rx_vote <= (rx_i_shift[SAMPLE_UPPER] & rx_i_shift[SAMPLE_MID])
| (rx_i_shift[SAMPLE_UPPER] & rx_i_shift[SAMPLE_LOWER])
| (rx_i_shift[SAMPLE_MID] & rx_i_shift[SAMPLE_LOWER]);
end
always @ (posedge clk_i)
begin
if (ctr_sample == SAMPLE_RATE - 1)
begin
s_tx_o <= { {rx_vote}, {s_tx_o[DATA_LENGTH - 1 : 1]} };
end
end
always @ (posedge clk_i)
begin
rx_i_d <= rx_i;
end
always @ (posedge clk_i)
begin
case (state)
ST_IDLE:
if (~rx_i & rx_i_d)
begin
state <= ST_START;
end
ST_START:
if (ctr_sample == SAMPLE_RATE - 1)
begin
state <= ST_DATA;
end
ST_DATA:
if (ctr_bit == DATA_LENGTH & ctr_sample == SAMPLE_RATE - 1 )
begin
state <= ST_STOP;
end
ST_STOP:
if (ctr_bit == PACKET_LENGTH - 1 & ctr_sample == SAMPLE_UPPER)
begin
state <= ST_IDLE;
end
endcase // case (state)
end // always @ (posedge clk_rx_i)
endmodule
|
module lsu_in_flight_counter(
in_rd_en,
in_wr_en,
in_mem_ack,
out_lsu_ready,
clk,
rst
);
parameter MAX_INFLIGHT_DATA_MEM = 16;
parameter MAX_INFLIGHT_DATA_MEM_LOG2 = 4;
input [3:0] in_rd_en;
input [3:0] in_wr_en;
input in_mem_ack;
output out_lsu_ready;
input clk;
input rst;
wire rd_en;
wire wr_en;
wire [MAX_INFLIGHT_DATA_MEM_LOG2-1:0] in_flight_count;
reg [MAX_INFLIGHT_DATA_MEM_LOG2-1:0] next_count;
assign rd_en = |in_rd_en;
assign wr_en = |in_wr_en;
dff in_flight_store[MAX_INFLIGHT_DATA_MEM_LOG2-1:0](
.q(in_flight_count),
.d(next_count),
.clk(clk),
.rst(rst)
);
always @(rd_en or wr_en or in_mem_ack or in_flight_count)
begin
casex({rd_en, wr_en, in_mem_ack})
3'b000:
begin
next_count <= in_flight_count;
end
3'b001:
begin
next_count <= in_flight_count - 1'b1;
end
3'b010:
begin
next_count <= in_flight_count + 1'b1;
end
3'b011:
begin
next_count <= in_flight_count;
end
3'b100:
begin
next_count <= in_flight_count + 1'b1;
end
3'b101:
begin
next_count <= in_flight_count;
end
default:
begin
next_count <= {MAX_INFLIGHT_DATA_MEM_LOG2{1'bx}};
end
endcase
end
assign out_lsu_ready = (next_count == MAX_INFLIGHT_DATA_MEM-3) ? 1'b0 : 1'b1;
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> myvec[100001]; set<int> myset[2]; set<int>::iterator it; int mark[100001]; bool isbipartite(int src) { int color[100001]; memset(color, -1, sizeof(color)); queue<int> q; q.push(src); mark[src] = 1; color[src] = 1; myset[color[src]].insert(src); while (!q.empty()) { int u = q.front(); q.pop(); for (int v = 0; v < myvec[u].size(); v++) { if (color[myvec[u][v]] == -1) color[myvec[u][v]] = 1 - color[u], q.push(myvec[u][v]), myset[color[myvec[u][v]]].insert(myvec[u][v]), mark[myvec[u][v]] = 1; else if (color[myvec[u][v]] == color[u]) return false; } } return true; } int main() { long long int x, y; int a, b; cin >> a >> b; while (b--) { cin >> x >> y; myvec[x].push_back(y); myvec[y].push_back(x); } bool solve = true; for (int i = 1; i <= a; i++) { if (mark[i] == 0) { solve = (solve && isbipartite(i)); } } if (solve == true) { cout << myset[0].size() << endl; for (it = myset[0].begin(); it != myset[0].end(); it++) { cout << *it << ; } cout << endl; cout << myset[1].size() << endl; for (it = myset[1].begin(); it != myset[1].end(); it++) { cout << *it << ; } cout << endl; } else cout << -1 << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; long long MOD = 998244853; long long mpow(long long a, long long b) { if (b == 0) return 1; long long t1 = mpow(a, b / 2); t1 *= t1; t1 %= MOD; if (b % 2) t1 *= a; t1 %= MOD; return t1; } long long mpow(long long a, long long b, long long p) { if (b == 0) return 1; long long t1 = mpow(a, b / 2); t1 *= t1; t1 %= p; if (b % 2) t1 *= a; t1 %= p; return t1; } long long modinverse(long long a, long long m) { long long m0 = m; long long y = 0, x = 1; if (m == 1) return 0; while (a > 1) { long long q = a / m; long long t = m; m = a % m, a = t; t = y; y = x - q * y; x = t; } if (x < 0) x += m0; return x; } long long range(long long l, long long r) { return l + rand() % (r - l + 1); } void solve() { long long n, m; cin >> n >> m; vector<pair<long long, long long> > s; long long st = n + 1, en = 0; for (long long i = 0; i < m; i++) { pair<long long, long long> temp; cin >> temp.first >> temp.second; s.push_back(temp); st = min(st, temp.first); en = max(en, temp.first); } st--; en--; long long b[n]; for (long long i = 0; i < n; i++) cin >> b[i]; for (long long i = st; i < en + 1; i++) { bool bo = 1; pair<long long, long long> h[n]; for (long long i = 0; i < n; i++) h[i] = make_pair((long long)-1, (long long)-1); long long name = 1; for (auto it : s) { h[it.first - 1] = make_pair(it.second, name++); } for (long long j = st; j < i + 1; j++) { pair<long long, long long> temp = ((j == 0) ? make_pair((long long)0, (long long)0) : make_pair(h[j - 1].first + b[j], h[j - 1].second)); h[j] = max(h[j], temp); if (h[j].first < 0) bo = 0; } for (long long j = en; j >= i; j--) { pair<long long, long long> temp = ((j == n - 1) ? make_pair((long long)0, (long long)0) : make_pair(h[j + 1].first + b[j], h[j + 1].second)); h[j] = max(h[j], temp); if (h[j].first < 0) bo = 0; } if (!bo) continue; cout << i + 1 << n ; bool vis[m]; for (long long i = 0; i < m; i++) vis[i] = 0; for (long long j = i; j >= st; j--) { if (vis[h[j].second - 1] == 0) { cout << h[j].second << ; vis[h[j].second - 1] = 1; } } for (long long j = i; j < en + 1; j++) { if (vis[h[j].second - 1] == 0) { cout << h[j].second << ; vis[h[j].second - 1] = 1; } } for (long long j = 0; j < m; j++) { if (vis[j] == 0) { cout << j + 1 << ; vis[j] = 1; } } cout << n ; return; } cout << -1 << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long t = 1; for (long long i = 0; i < t; i++) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, x; cin >> n >> x; if (n == 3) { cout << >vv << endl << ^<. << endl << ^.< << endl; cout << 1 << << 3; } if (n == 5) { cout << >...v << endl << v.<.. << endl << ..^.. << endl << >.... << endl << ..^.< << endl; cout << 1 << << 1; } if (n == 100) { cout << >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>.>.>.>.>.>.>.>.>.> .>.>.>.>.>.>.>.>.>.>.>.>.>.>.>.>.v << endl; for (int i = 0; i < 49; i++) { cout << ^v.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<<<<<<<<< <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< << endl; cout << ^>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>.>.>.>.>.>.>.>.> .>.>.>.>.>.>.>.>.>.>.>.>.>.>.>.>.>.v << endl; } cout << ^<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<<<<<<<<<<< <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< << endl; cout << 1 << << 1; } } |
#include <bits/stdc++.h> const double EPS = 0.00000001; int main() { std::ios_base::sync_with_stdio(false); std::cin.tie(nullptr); int32_t t; std::cin >> t; for (int32_t cs = 1; cs <= t; cs++) { int32_t n, l; std::cin >> n >> l; std::vector<int32_t> a(n); for (auto &x : a) { std::cin >> x; } int32_t indL = 0, indR = n - 1, speed1 = 1, speed2 = 1; double pos1 = 0, pos2 = l; double currT = 0.0, ans; while (1) { if (indL > indR) { ans = currT + (pos2 - pos1) / (speed1 + speed2); break; } double t1 = ((double)a[indL] - pos1) / speed1; double t2 = ((double)pos2 - a[indR]) / speed2; if (indL == indR) { if (fabs(t1 - t2) < EPS) { ans = currT + t1; break; } } if (t1 < t2) { indL++; currT += t1; speed1++; pos1 = a[indL - 1]; pos2 -= t1 * speed2; } else { indR--; currT += t2; speed2++; pos1 += t2 * speed1; pos2 = a[indR + 1]; } } std::cout << std::fixed << std::setprecision(8); std::cout << ans << n ; } } |
#include <bits/stdc++.h> using namespace std; map<int, int> mp; std ::map<int, int>::iterator x, l, s; int main() { int n, p; cin >> n; mp[0] = 0; mp[1 << 30] = 0; for (int i = 0; i < n; i++) { cin >> p; x = mp.lower_bound(p); l = x--; s = x->second > l->second ? x : l; if (i) cout << s->first << ; mp[p] = s->second + 1; } } |
/*
* Titor - System - Minimal system to test the underlying processor
* Copyright (C) 2012 Sean Ryan Moore
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`ifdef INC_FSM_VGA
`else
`define INC_FSM_VGA
`timescale 1 ns / 100 ps
module FSM_VGA(
VGA_hsync,
VGA_vsync,
pixel_blank,
screen_row, screen_column,
reset,
clk
);
`include "definition/Definition.v"
output VGA_hsync;
output VGA_vsync;
output pixel_blank;
input clk;
input reset;
reg [WORD-1:0] pixel_row;
reg [WORD-1:0] pixel_column;
output wire [WORD-1:0] screen_row;
output wire [WORD-1:0] screen_column;
reg [WORD-1:0] state_vertical;
reg [WORD-1:0] state_horizontal;
wire active_row;
wire active_column;
wire [WORD-1:0] division;
// these values are simply doubled because I don't care about proper clock domains if the screen will still work
// some necessary constants for the 640 X 480 controller
localparam PIXEL_H = SCREEN_WIDTH,
PIXEL_V = SCREEN_HEIGHT,
FRONT_PORCH_H = 16,
FRONT_PORCH_V = 10,
PULSE_H = 96,
PULSE_V = 2,
BACK_PORCH_H = 48,
BACK_PORCH_V = 29;
localparam SYNC_H = (PIXEL_H + FRONT_PORCH_H + PULSE_H + BACK_PORCH_H),
SYNC_V = (PIXEL_V + FRONT_PORCH_V + PULSE_V + BACK_PORCH_V);
localparam MODE_0_H = 0,
MODE_0_V = 0,
MODE_1_H = MODE_0_H + PIXEL_H,
MODE_1_V = MODE_0_V + PIXEL_V,
MODE_2_H = MODE_1_H + FRONT_PORCH_H,
MODE_2_V = MODE_1_V + FRONT_PORCH_V,
MODE_3_H = MODE_2_H + PULSE_H,
MODE_3_V = MODE_2_V + PULSE_V;
localparam STATE_PIXEL = 0,
STATE_FRONT_PORCH = 1,
STATE_PULSE = 2,
STATE_BACK_PORCH = 3;
assign pixel_blank = !((state_horizontal == STATE_PIXEL) && (state_vertical == STATE_PIXEL));
assign VGA_hsync = !(state_horizontal==STATE_PULSE);
assign VGA_vsync = !(state_vertical ==STATE_PULSE);
// the "real" position of the electron gun
// these positions truly indicate what position is being displayed so long as pixel_blank is false
// otherwise the positions are invalid
always @(*) begin
if(state_vertical == STATE_PIXEL) pixel_row <= screen_row;
else pixel_row <= 0;
if(state_horizontal == STATE_PIXEL) pixel_column <= screen_column;
else pixel_column <= 0;
end
// VGA state-like classification machine
// this has two pieces that take in counters (specifically radix counters) and pop out a state based on them
always @(*) begin
if(screen_column < MODE_1_H) state_horizontal <= STATE_PIXEL;
else if(screen_column < MODE_2_H) state_horizontal <= STATE_FRONT_PORCH;
else if(screen_column < MODE_3_H) state_horizontal <= STATE_PULSE;
else state_horizontal <= STATE_BACK_PORCH;
if(screen_row < MODE_1_V) state_vertical <= STATE_PIXEL;
else if(screen_row < MODE_2_V) state_vertical <= STATE_FRONT_PORCH;
else if(screen_row < MODE_3_V) state_vertical <= STATE_PULSE;
else state_vertical <= STATE_BACK_PORCH;
end
wire [4-1:0] carry;
assign carry[0] = 1;
// chain of radix counters: screen_row <- screen column <- clock divide
Radix_Counter #(SYNC_V) counter_screen_row(
.carry_in(carry[2]),
.carry_out(carry[3]),
.count(screen_row),
.reset(reset),
.clk(clk)
);
Radix_Counter #(SYNC_H) counter_screen_column(
.carry_in(carry[1]),
.carry_out(carry[2]),
.count(screen_column),
.reset(reset),
.clk(clk)
);
Radix_Counter #(VGA_SLOW) counter_divide(
.carry_in(carry[0]),
.carry_out(carry[1]),
.count(division),
.reset(reset),
.clk(clk)
);
endmodule
`endif
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Arbiter module
*/
module arbiter #
(
parameter PORTS = 4,
// arbitration type: "PRIORITY" or "ROUND_ROBIN"
parameter TYPE = "PRIORITY",
// block type: "NONE", "REQUEST", "ACKNOWLEDGE"
parameter BLOCK = "NONE",
// LSB priority: "LOW", "HIGH"
parameter LSB_PRIORITY = "LOW"
)
(
input wire clk,
input wire rst,
input wire [PORTS-1:0] request,
input wire [PORTS-1:0] acknowledge,
output wire [PORTS-1:0] grant,
output wire grant_valid,
output wire [$clog2(PORTS)-1:0] grant_encoded
);
reg [PORTS-1:0] grant_reg = 0, grant_next;
reg grant_valid_reg = 0, grant_valid_next;
reg [$clog2(PORTS)-1:0] grant_encoded_reg = 0, grant_encoded_next;
assign grant_valid = grant_valid_reg;
assign grant = grant_reg;
assign grant_encoded = grant_encoded_reg;
wire request_valid;
wire [$clog2(PORTS)-1:0] request_index;
wire [PORTS-1:0] request_mask;
priority_encoder #(
.WIDTH(PORTS),
.LSB_PRIORITY(LSB_PRIORITY)
)
priority_encoder_inst (
.input_unencoded(request),
.output_valid(request_valid),
.output_encoded(request_index),
.output_unencoded(request_mask)
);
reg [PORTS-1:0] mask_reg = 0, mask_next;
wire masked_request_valid;
wire [$clog2(PORTS)-1:0] masked_request_index;
wire [PORTS-1:0] masked_request_mask;
priority_encoder #(
.WIDTH(PORTS),
.LSB_PRIORITY(LSB_PRIORITY)
)
priority_encoder_masked (
.input_unencoded(request & mask_reg),
.output_valid(masked_request_valid),
.output_encoded(masked_request_index),
.output_unencoded(masked_request_mask)
);
always @* begin
grant_next = 0;
grant_valid_next = 0;
grant_encoded_next = 0;
mask_next = mask_reg;
if (BLOCK == "REQUEST" && grant_reg & request) begin
// granted request still asserted; hold it
grant_valid_next = grant_valid_reg;
grant_next = grant_reg;
grant_encoded_next = grant_encoded_reg;
end else if (BLOCK == "ACKNOWLEDGE" && grant_valid && !(grant_reg & acknowledge)) begin
// granted request not yet acknowledged; hold it
grant_valid_next = grant_valid_reg;
grant_next = grant_reg;
grant_encoded_next = grant_encoded_reg;
end else if (request_valid) begin
if (TYPE == "PRIORITY") begin
grant_valid_next = 1;
grant_next = request_mask;
grant_encoded_next = request_index;
end else if (TYPE == "ROUND_ROBIN") begin
if (masked_request_valid) begin
grant_valid_next = 1;
grant_next = masked_request_mask;
grant_encoded_next = masked_request_index;
if (LSB_PRIORITY == "LOW") begin
mask_next = {PORTS{1'b1}} >> (PORTS - masked_request_index);
end else begin
mask_next = {PORTS{1'b1}} << (masked_request_index + 1);
end
end else begin
grant_valid_next = 1;
grant_next = request_mask;
grant_encoded_next = request_index;
if (LSB_PRIORITY == "LOW") begin
mask_next = {PORTS{1'b1}} >> (PORTS - request_index);
end else begin
mask_next = {PORTS{1'b1}} << (request_index + 1);
end
end
end
end
end
always @(posedge clk or posedge rst) begin
if (rst) begin
grant_reg <= 0;
grant_valid_reg <= 0;
grant_encoded_reg <= 0;
mask_reg <= 0;
end else begin
grant_reg <= grant_next;
grant_valid_reg <= grant_valid_next;
grant_encoded_reg <= grant_encoded_next;
mask_reg <= mask_next;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O31AI_1_V
`define SKY130_FD_SC_HDLL__O31AI_1_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog wrapper for o31ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o31ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o31ai_1 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__o31ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o31ai_1 (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__o31ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O31AI_1_V
|
#include <bits/stdc++.h> using namespace std; const int N = 2 * 1e5 + 100, mod = 1e9 + 7; int n, k, a, b; int dp[5010][5010], pr[5010][5010]; int add(int a, int b) { a += b; if (a < 0) a += mod; if (a >= mod) a -= mod; return a; } int main() { scanf( %d%d%d%d , &n, &a, &b, &k); dp[0][a] = 1; for (int i = 0; i <= k; i++) { if (i != 0) { for (int j = 1; j <= n; j++) { if (j > b) { int t = ((j + b) >> 1) + 1; dp[i][j] += add(add(pr[i - 1][n], -pr[i - 1][t - 1]), -dp[i - 1][j]); } else if (j < b) { int t = ((j + b - 1) >> 1); dp[i][j] += add(pr[i - 1][t], -dp[i - 1][j]); } } } for (int j = 1; j <= n; j++) { pr[i][j] = add(pr[i][j - 1], dp[i][j]); } } cout << pr[k][n] % mod; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: I.T.C.R
// Engineer: Jafet Chaves Barrantes
//
// Create Date: 17:02:57 02/28/2016
// Design Name:
// Module Name: Conversor_BCD_7seg
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Conversor_BCD_7seg
(
input wire [3:0] Valor_Decimal,
output reg [7:0] Code_7seg
);
//Descripción combinacional del valor decimal a código para el 7 segmentos
always @*
begin
case(Valor_Decimal)
4'h0: Code_7seg = 8'b00000011; //0
4'h1: Code_7seg = 8'b10011111; //1
4'h2: Code_7seg = 8'b00100101; //2
4'h3: Code_7seg = 8'b00001101; //3
4'h4: Code_7seg = 8'b10011001; //4
4'h5: Code_7seg = 8'b01001001; //5
4'h6: Code_7seg = 8'b01000001; //6
4'h7: Code_7seg = 8'b00011111; //8
4'h8: Code_7seg = 8'b00000001; //9
4'h9: Code_7seg = 8'b00001001; //Caso default no enciende el 7 seg
default: Code_7seg = 8'b11111111;
endcase
end
endmodule
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* FIFO
* ====
*
* Implementation notes:
*
* - Read and write pointers are simple ring counters
*
* - Number of items held in FIFO is recorded in shift register
* (Full/empty flags are most and least-significant bits of register)
*
* - Supports input and/or output registers on FIFO
*
* Examples:
*
* fifo_v #(.fifo_elements_t(int), .size(8)) myfifo (.*);
*
* Instantiates a FIFO that can hold up to 8 integers.
*
* fifo_v #(.fifo_elements_t(int), .size(8), .output_reg(1)) myfifo (.*);
*
* Instantiates a FIFO that can hold up to 8 integers with output register
*
* Output Register
* ===============
*
* Instantiate a FIFO of length (size-1) + an output register and bypass logic
*
* output_reg = 0 (default) - no output register
* output_reg = 1 - instantiate a single output register
*
* _
* ______ |\ | |
* _|-[_FIFO_]-->| |__| |__ Out
* |----------->| | |_|
* bypass |/ Reg.
*
*
* Input Register
* ==============
*
* input_reg = 0 (default) - no input register, FIFO receives data directly
* input_reg = 1 - assume **external** input register and bypass logic
* input_reg = 2 - instantiate input register and bypass logic
*
* In case 1. the FIFO is still of length 'size' as it is assumed the external
* input register is always enabled (used when building VC buffers).
*
* _ ______ |\
* | | |-[_FIFO_]-->| |___ Out
* | |__|___________>| |
* |_| |/
* Reg.
*
* Input and Output Registers
* ==========================
*
* Can set input_reg=2, output_reg=1 to create FIFO with both input and output
* registers. FIFO behaviour remains identical at the cycle-level with the
* addition of input/output registers.
*
* InReg OutReg
* _ ______ _
* | |---[_FIFO_]---| |
* | | |____________| |___|\
* |_| | |_| | |__ Out
* |__________________| |
* |/
* FIFO Initialisation
* ===================
*
* init_fifo_contents = 0 - FIFO is empty on reset
* init_fifo_contents = 1 - FIFO is nearly_full on reset (mem[i]=1'b1<<i, mem[size]=0)
* init_fifo_contents = 2 - FIFO is nearly empty on reset (mem[0]=1)
*
*
* ===============================================================================
*/
// other FIFO types: double buffered, two slower FIFOs + output register
// FIFOs with second entry outputs (as required by router)
// pending write input register
//
// - second output with output registers [two output registers?]
//
//`ifdef VCS
//import fifo_package::*;
//`endif
/************************************************************************************
*
* FIFO
*
************************************************************************************/
module LAG_fifo_v (push, pop, data_in, data_out, flags, clk, rst_n);
// max no. of entries
parameter size = 8;
input push, pop;
output fifov_flags_t flags;
input fifo_elements_t data_in;
output fifo_elements_t data_out;
input clk, rst_n;
logic fifo_push, fifo_pop;
fifo_elements_t fifo_data_out, data_out_tmp;
fifo_buffer #(.size(size))
fifo_buf (push, pop, data_in, data_out_tmp, clk, rst_n);
assign data_out = flags.empty ? '0 : data_out_tmp;
fifo_flags #(.size(size))
gen_flags(push, pop, flags, clk, rst_n);
endmodule // fifo_v
/************************************************************************************
*
* Maintain FIFO flags (full, nearly_full, nearly_empty and empty)
*
* This design uses a shift register to ensure flags are available quickly.
*
************************************************************************************/
module fifo_flags (push, pop, flags, clk, rst_n);
input push, pop;
output fifov_flags_t flags;
input clk, rst_n;
parameter size = 8;
reg [size:0] counter; // counter must hold 1..size + empty state
logic was_push, was_pop;
fifov_flags_t flags_reg;
logic add, sub, same;
/*
* maintain flags
*
*
* maintain shift register as counter to determine if FIFO is full or empty
* full=counter[size-1], empty=counter[0], etc..
* init: counter=1'b1;
* (push & !pop): shift left
* (pop & !push): shift right
*/
always@(posedge clk) begin
if (!rst_n) begin
counter<={{size{1'b0}},1'b1};
was_push<=1'b0;
was_pop<=1'b0;
end else begin
if (add) begin
assert (counter!={1'b1,{size{1'b0}}}) else $fatal;
counter <= {counter[size-1:0], 1'b0};
end else if (sub) begin
assert (counter!={{size{1'b0}},1'b1}) else $fatal;
counter <= {1'b0, counter[size:1]};
end
assert (counter!=0) else $fatal;
was_push<=push;
was_pop<=pop;
assert (push!==1'bx) else $fatal;
assert (pop!==1'bx) else $fatal;
end // else: !if(!rst_n)
end
assign add = was_push && !was_pop;
assign sub = was_pop && !was_push;
assign same = !(add || sub);
assign flags.full = (counter[size] && !sub) || (counter[size-1] && add);
assign flags.empty = (counter[0] && !add) || (counter[1] && sub);
assign flags.nearly_full = (counter[size-1] && same) || (counter[size] && sub) || (counter[size-2] && add);
assign flags.nearly_empty = (counter[1] && same) || (counter[0] && add) || (counter[2] && sub);
endmodule // fifo_flags
/************************************************************************************
*
* Simple core FIFO module
*
************************************************************************************/
module fifo_buffer (push, pop, data_in, data_out, clk, rst_n);
// max no. of entries
parameter int unsigned size = 4;
input push, pop;
input fifo_elements_t data_in;
output fifo_elements_t data_out;
input clk, rst_n;
// reg [size-1:0] rd_ptr, wt_ptr;
logic unsigned [size-1:0] rd_ptr, wt_ptr;
fifo_elements_t fifo_mem[0:size-1];
logic select_bypass;
integer i,j;
always@(posedge clk) begin
assert (size>=2) else $fatal();
if (!rst_n) begin
rd_ptr<={{size-1{1'b0}},1'b1};
wt_ptr<={{size-1{1'b0}},1'b1};
end else begin
if (push) begin
// enqueue new data
for (i=0; i<size; i++) begin
if (wt_ptr[i]==1'b1) begin
fifo_mem[i] <= data_in;
end
end
end
if (push) begin
// rotate write pointer
wt_ptr <= {wt_ptr[size-2:0], wt_ptr[size-1]};
end
if (pop) begin
// rotate read pointer
rd_ptr <= {rd_ptr[size-2:0], rd_ptr[size-1]};
end
end // else: !if(!rst_n)
end // always@ (posedge clk)
/*
*
* FIFO output is item pointed to by read pointer
*
*/
always_comb begin
//
// one bit of read pointer is always set, ensure synthesis tool
// doesn't add logic to force a default
//
data_out = 'x;
for (j=0; j<size; j++) begin
if (rd_ptr[j]==1'b1) begin
// output entry pointed to by read pointer
data_out = fifo_mem[j];
end
end
end
endmodule // fifo_buffer
|
#include <bits/stdc++.h> using namespace std; long long INF = 1e9; const int MAX = 1e5 + 7, N = 1e5 + 3; double pi = acos(-1); long long r, l, k, m, n, ans; int main() { cin >> n; cin >> k >> l; long long m1 = k - 1 + l - 1; long long m2 = n - k + n - l; if (m1 <= m2) { cout << White << endl; } else { cout << Black << endl; } return 0; } |
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: read_posted_fifo.v
// /___/ /\ Date Last Modified:
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This module instantiated by read_data_path module and sits between
// mcb_flow_control module and read_data_gen module to buffer up the
// commands that has sent to memory controller.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module read_posted_fifo #
(
parameter TCQ = 100,
parameter FAMILY = "SPARTAN6",
parameter MEM_BURST_LEN = 4,
parameter ADDR_WIDTH = 32,
parameter BL_WIDTH = 6
)
(
input clk_i,
input rst_i,
output reg cmd_rdy_o,
input memc_cmd_full_i,
input cmd_valid_i,
input data_valid_i,
input cmd_start_i,
input [ADDR_WIDTH-1:0] addr_i,
input [BL_WIDTH-1:0] bl_i,
input [2:0] cmd_sent,
input [5:0] bl_sent ,
input cmd_en_i ,
output gen_valid_o,
output [ADDR_WIDTH-1:0] gen_addr_o,
output [BL_WIDTH-1:0] gen_bl_o,
output rd_mdata_en
);
//reg empty_r;
//reg rd_first_data;
reg [10:0] INC_COUNTS;
reg rd_en_r;
wire full;
wire empty;
wire wr_en;
reg mcb_rd_fifo_port_almost_full;
reg [6:0] buf_avail_r;
reg [6:0] rd_data_received_counts;
reg [6:0] rd_data_counts_asked;
reg dfifo_has_enough_room;
reg [1:0] wait_cnt;
reg wait_done;
assign rd_mdata_en = rd_en_r;
generate
if (FAMILY == "SPARTAN6") begin: gen_sp6_cmd_rdy
always @ (posedge clk_i)
cmd_rdy_o <= #TCQ !full & dfifo_has_enough_room ;//& wait_done;
end
endgenerate
generate
if (FAMILY == "VIRTEX6") begin: gen_v6_cmd_rdy
always @ (posedge clk_i)
cmd_rdy_o <= #TCQ !full & wait_done;
end
endgenerate
always @ (posedge clk_i)
begin
if (rst_i)
wait_cnt <= #TCQ 'b0;
else if (cmd_rdy_o && cmd_valid_i)
wait_cnt <= #TCQ 2'b10;
else if (wait_cnt > 0)
wait_cnt <= #TCQ wait_cnt - 1'b1;
end
always @(posedge clk_i)
begin
if (rst_i)
wait_done <= #TCQ 1'b1;
else if (cmd_rdy_o && cmd_valid_i)
wait_done <= #TCQ 1'b0;
else if (wait_cnt == 0)
wait_done <= #TCQ 1'b1;
else
wait_done <= #TCQ 1'b0;
end
reg dfifo_has_enough_room_d1;
always @ (posedge clk_i)
begin
// dfifo_has_enough_room <= 1'b1;// #TCQ (buf_avail_r >= 32 ) ? 1'b1: 1'b0;
dfifo_has_enough_room <= #TCQ (buf_avail_r >= 32 ) ? 1'b1: 1'b0;
dfifo_has_enough_room_d1 <= #TCQ dfifo_has_enough_room ;
end
assign wr_en = cmd_valid_i & !full & dfifo_has_enough_room_d1 & wait_done;
/*localparam MEM_BURST_INT = MEM_BURST_LEN ;
generate
if (FAMILY == "VIRTEX6" ) begin : INC_COUNTS_V
always @ (posedge clk_i) begin
if ( (NUM_DQ_PINS >= 128 && NUM_DQ_PINS <= 144)) //256
INC_COUNTS <= #TCQ 64 * (MEM_BURST_INT/4);
else if ( (NUM_DQ_PINS >= 64 && NUM_DQ_PINS < 128)) //256
INC_COUNTS <= #TCQ 32 * (MEM_BURST_INT/4);
else if ((NUM_DQ_PINS >= 32) && (NUM_DQ_PINS < 64)) //128
INC_COUNTS <= #TCQ 16 * (MEM_BURST_INT/4) ;
else if ((NUM_DQ_PINS == 16) || (NUM_DQ_PINS == 24)) //64
INC_COUNTS <= #TCQ 8 * (MEM_BURST_INT/4);
else if ((NUM_DQ_PINS == 8) )
INC_COUNTS <= #TCQ 4 * (MEM_BURST_INT/4);
end
end
endgenerate
*/
always @ (posedge clk_i)
begin
if (rst_i) begin
rd_data_counts_asked <= #TCQ 'b0;
end
else if (cmd_en_i && cmd_sent[0] == 1 && ~memc_cmd_full_i) begin
// if (FAMILY == "SPARTAN6)
// rd_data_counts_asked <= #TCQ rd_data_counts_asked + (bl_sent + 7'b0000001) ;
// else
// begin
// if (MEM_BURST_LEN == 8)
rd_data_counts_asked <= #TCQ rd_data_counts_asked + 1'b1 ;
end
end
always @ (posedge clk_i)
begin
if (rst_i) begin
rd_data_received_counts <= #TCQ 'b0;
end
else if (data_valid_i) begin
rd_data_received_counts <= #TCQ rd_data_received_counts + 1'b1;
end
end
// calculate how many buf still available
always @ (posedge clk_i)
buf_avail_r <= #TCQ (rd_data_received_counts + 7'd64) - rd_data_counts_asked;
always @ (posedge clk_i) begin
rd_en_r <= #TCQ cmd_start_i;
// empty_r <= #TCQ empty;
end
// always @ (posedge clk_i)
// begin
// if (rst_i)
// rd_first_data <= #TCQ 1'b0;
// else if (~empty && empty_r)
// rd_first_data <= #TCQ 1'b1;
// end
assign gen_valid_o = !empty;
afifo #
(
.TCQ (TCQ),
.DSIZE (BL_WIDTH+ADDR_WIDTH),
.FIFO_DEPTH (16),
.ASIZE (4),
.SYNC (1) // set the SYNC to 1 because rd_clk = wr_clk to reduce latency
)
rd_fifo
(
.wr_clk (clk_i),
.rst (rst_i),
.wr_en (wr_en),
.wr_data ({bl_i,addr_i}),
.rd_en (rd_en_r),
.rd_clk (clk_i),
.rd_data ({gen_bl_o,gen_addr_o}),
.full (full),
.empty (empty),
.almost_full ()
);
endmodule
|
module main;
wire eq1, eq2, eq5;
wire ne1, ne2, ne5;
reg [7:0] x, y;
eqne dut(.eq1(eq1), .eq2(eq2), .eq5(eq5),
.ne1(ne1), .ne2(ne2), .ne5(ne5),
.x(x), .y(y));
initial begin
for (x = 0 ; x < 'h20 ; x = x+1)
for (y = 0 ; y < 'h20 ; y = y+1) begin
#1 $display("x=%h, y=%h: ", x, y,
"eq1=%b, eq2=%b, eq5=%b, ", eq1, eq2, eq5,
"ne1=%b, ne2=%b, ne5=%b", ne1, ne2, ne5);
if (eq1 !== (x[0] == y[0])) begin
$display("FAILED");
$finish;
end
if (eq2 !== (x[1:0] == y[1:0])) begin
$display("FAILED");
$finish;
end
if (eq5 !== (x[4:0] == y[4:0])) begin
$display("FAILED");
$finish;
end
if (ne1 !== (x[0] != y[0])) begin
$display("FAILED");
$finish;
end
if (ne2 !== (x[1:0] != y[1:0])) begin
$display("FAILED");
$finish;
end
if (ne5 !== (x[4:0] != y[4:0])) begin
$display("FAILED");
$finish;
end
end
$display("PASSED");
end
endmodule // main
|
`timescale 1ns / 1ps
/*
Copyright 2015, Google Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:29:02 11/06/2014
// Design Name:
// Module Name: trng_top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module trng (
input clk,
input en,
output [7:0] R
);
wire [7:0] a, c;
reg [7:0] b, d;
assign a = (en) ? ({ a[6:0], a[7] } ^ a ^ { a[0], a[7:1] } ^ 8'h80) : a;
always @(posedge clk)
begin
b <= a;
end
assign c = (d & 8'h96) ^ { d[6:0], 1'b0 } ^ { 1'b0, d[7:1] } ^ b;
always @(posedge clk)
begin
d <= (en) ? c : d;
end
assign R = d;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, a[105], p[105]; long long g[105]; long long d[105][105][105]; bool ok[105][105]; char c[105]; void read(int& x) { char c = getchar(); x = 0; while (!isdigit(c)) c = getchar(); while (isdigit(c)) { x = x * 10 + c - 0 ; c = getchar(); } } long long dp(int l, int r, int k) { if (ok[l][r]) return d[l][r][k] = g[r - l + k + 1]; if (d[l][r][k]) return d[l][r][k]; for (int i = l; i < r; i++) { d[l][r][k] = max(d[l][r][k], dp(l, i, 0) + dp(i + 1, r, k)); } for (int i = l; i < p[r]; i++) { if (c[i] == c[r] && c[i + 1] != c[r]) { d[l][r][k] = max(d[l][r][k], dp(l, i, k + r - p[r] + 1) + dp(i + 1, p[r] - 1, 0)); } } return d[l][r][k]; } int main() { read(n); scanf( %s , c + 1); for (int i = 1; i <= n; i++) { read(a[i]); g[i] = a[i]; } for (int i = 1; i <= n; i++) { for (int j = i; j >= 1; j--) { if (c[j] == c[i]) { p[i] = j; ok[j][i] = 1; } else break; } } for (int i = 2; i <= n; i++) for (int j = 1; j < i; j++) g[i] = max(g[i], g[j] + a[i - j]); printf( %lld n , dp(1, n, 0)); } |
#include <bits/stdc++.h> using namespace std; int N; vector<int> a, b, c; multiset<int> m; int main(void) { ios::sync_with_stdio(false); cin.tie(NULL), cout.tie(NULL); cin >> N; a.resize(N); b.resize(N); c.resize(N); for (int i = 0; i < N; i++) { cin >> a[i]; } for (int i = 0; i < N; i++) { cin >> b[i]; m.insert(b[i]); } for (int i = 0; i < N; i++) { int cur = N - a[i]; multiset<int>::iterator iter = m.lower_bound(cur); if (iter == m.end()) { iter = m.begin(); } c[i] = (a[i] + (*iter)) % N; m.erase(iter); } for (int i = 0; i < N; i++) { cout << c[i] << ; } return 0; } |
//begin #include <Core> /* * Package: StandardCodeLibrary.Core * Last Update: 2012-12-21 * */ #include <iostream> #include <fstream> #include <sstream> #include <iomanip> #include <utility> #include <vector> #include <list> #include <string> #include <stack> #include <queue> #include <deque> #include <set> #include <map> #include <algorithm> #include <functional> #include <numeric> #include <bitset> #include <complex> #include <cstdio> #include <cstring> #include <cmath> #include <cstdlib> #include <ctime> #include <climits> #if __GNUC__>=4 and __GNUC_MINOR__>=6 #include <ext/pb_ds/assoc_container.hpp> #include <ext/pb_ds/tree_policy.hpp> #include <ext/pb_ds/tag_and_trait.hpp> #endif using namespace std; #define lp for(;;) #define repf(i,a,b) for (int i=(a);i<(b);++i) #define rep(i,n) repf(i,0,n) #define ft(i,a,b) for (int i=(a);i<=(b);++i) #define fdt(i,a,b) for (int i=(a);i>=b;--i) #define feach(e,s) for (typeof((s).begin()) e=(s).begin();e!=(s).end();++e) #define fsubset(subset,set) for (int subset=set&(set-1);subset;subset=(subset-1)&set) #define forin(i,charset) for (cstr i=charset;*i;i++) #define whl while #define rtn return #define fl(x,y) memset((x),char(y),sizeof(x)) #define clr(x) fl(x,char(0)) #define cpy(x,y) memcpy(x,y,sizeof(x)) #define pb push_back #define mp make_pair #define ins insert #define rnk order_of_key #define sel find_by_order #define x first #define y second #define sz(x) (int((x).size())) #define all(x) (x).begin(),(x).end() #define srt(x) sort(all(x)) #define uniq(x) srt(x),(x).erase(unique(all(x)),x.end()) #define vec vector #define pr pair #define que queue #define prq priority_queue #define itr iterator #define sf scanf #define pf printf #define pdb(prcs,x) (cout<<setprecision(prcs)<<fixed<<(x)) #ifdef DEBUG #define prt(x) cerr<<#x = <<(x)<<endl #define asrtWA(s) do if(!(s))do{cerr<< assert( #s ) <<endl;}whl(0);whl(0) #define asrtTLE(s) do if(!(s))do{cerr<< assert( #s ) <<endl;}whl(0);whl(0) #define asrtMLE(s) do if(!(s))do{cerr<< assert( #s ) <<endl;}whl(0);whl(0) #define asrtOLE(s) do if(!(s))do{cerr<< assert( #s ) <<endl;}whl(0);whl(0) #define asrtRE(s) do if(!(s))do{cerr<< assert( #s ) <<endl;}whl(0);whl(0) #define runtime() cerr<< Used: <<db(clock())/CLOCKS_PER_SEC<< s <<endl #define input(in) do{}whl(0) #define output(out) do{}whl(0) #else #define endl (char( n )) #define prt(x) (cerr) #define asrtWA(s) do if(!(s))exit(0);whl(0) #define asrtTLE(s) do if(!(s))whl(1);whl(0) #define asrtMLE(s) do if(!(s))whl(new int);whl(0) #define asrtOLE(s) do if(!(s))whl(1)puts( OLE );whl(0) #define asrtRE(s) do if(!(s))*(int*)0=0;whl(0) #define runtime() cerr #define input(in) freopen(in, r ,stdin) #define output(out) freopen(out, w ,stdout) #endif typedef long long int lli; typedef double db; typedef const char* cstr; typedef string str; typedef vec<int> vi; typedef vec<vi> vvi; typedef vec<bool> vb; typedef vec<vb> vvb; typedef vec<str> vs; typedef pr<int,int> pii; typedef pr<lli,lli> pll; typedef pr<db,db> pdd; typedef pr<str,int> psi; typedef map<int,int> mii; typedef map<str,int> msi; typedef map<char,int> mci; typedef set<int> si; typedef set<str> ss; typedef que<int> qi; typedef prq<int> pqi; #if __GNUC__>=4 and __GNUC_MINOR__>=7 template<typename key,typename value>class ext_map:public __gnu_pbds::tree<key,value,less<key>,__gnu_pbds::rb_tree_tag,__gnu_pbds::tree_order_statistics_node_update>{}; template<typename key>class ext_set:public __gnu_pbds::tree<key,__gnu_pbds::null_type,less<key>,__gnu_pbds::rb_tree_tag,__gnu_pbds::tree_order_statistics_node_update>{}; #elif __GNUC__>=4 and __GNUC_MINOR__>=6 template<typename key,typename value>class ext_map:public __gnu_pbds::tree<key,value,less<key>,__gnu_pbds::rb_tree_tag,__gnu_pbds::tree_order_statistics_node_update>{}; template<typename key>class ext_set:public __gnu_pbds::tree<key,__gnu_pbds::null_mapped_type,less<key>,__gnu_pbds::rb_tree_tag,__gnu_pbds::tree_order_statistics_node_update>{}; #endif const int oo=(~0u)>>1; const lli ooll=(~0ull)>>1; const db inf=1e+10; const db eps=1e-10; const db pi=acos(-1.0); const int MOD=1000000007; template<typename type>inline bool cmax(type& a,const type& b){rtn a<b?a=b,true:false;} template<typename type>inline bool cmin(type& a,const type& b){rtn b<a?a=b,true:false;} template<typename type>inline type sqr(const type& x){rtn x*x;} inline int dbcmp(const db& a,const db& b){rtn (a>b+eps)-(a<b-eps);} inline int sgn(const db& x){rtn dbcmp(x,0);} template<typename ostream,typename type>ostream& operator<<(ostream& cout,const pr<type,type>& x){rtn cout<< ( <<x.x<< , <<x.y<< ) ;} template<typename type>pr<type,type> operator-(const pr<type,type>& x){rtn mp(-x.x,-x.y);} template<typename type>pr<type,type> operator+(const pr<type,type>& a,const pr<type,type>& b){rtn mp(a.x+b.x,a.y+b.y);} template<typename type>pr<type,type> operator-(const pr<type,type>& a,const pr<type,type>& b){rtn mp(a.x-b.x,a.y-b.y);} template<typename type>inline type cross(const pr<type,type>& a,const pr<type,type>& b,const pr<type,type>& c){rtn (b.x-a.x)*(c.y-a.y)-(b.y-a.y)*(c.x-a.x);} template<typename type>inline type dot(const pr<type,type>& a,const pr<type,type>& b,const pr<type,type>& c){rtn (b.x-a.x)*(c.x-a.x)+(b.y-a.y)*(c.y-a.y);} template<typename type>inline type gcd(type a,type b){if(b)whl((a%=b)&&(b%=a));rtn a+b;} template<typename type>inline type lcm(type a,type b){rtn a*b/gcd(a,b);} template<typename type>inline void bit_inc(vec<type>& st,int x,type inc){whl(x<sz(st))st[x]+=inc,x|=x+1;} template<typename type>inline type bit_sum(const vec<type>& st,int x){type s=0;whl(x>=0)s+=st[x],x=(x&(x+1))-1;rtn s;} template<typename type>inline type bit_kth(const vec<type>& st,int k){int x=0,y=0,z=0;whl((1<<(++y))<=sz(st));fdt(i,y-1,0){if((x+=1<<i)>sz(st)||z+st[x-1]>k)x-=1<<i;else z+=st[x-1];}rtn x;} inline void make_set(vi& st){rep(i,sz(st))st[i]=i;} inline int find_set(vi& st,int x){int y=x,z;whl(y!=st[y])y=st[y];whl(x!=st[x])z=st[x],st[x]=y,x=z;rtn y;} inline bool union_set(vi& st,int a,int b){a=find_set(st,a),b=find_set(st,b);rtn a!=b?st[a]=b,true:false;} template<typename type>inline void merge(type& a,type& b){if(sz(a)<sz(b))swap(a,b);whl(sz(b))a.insert(*b.begin()),b.erase(b.begin());} template<typename type>inline void merge(prq<type>& a,prq<type>& b){if(sz(a)<sz(b))swap(a,b);whl(sz(b))a.push(b.top()),b.pop();} struct Initializer{Initializer(){ios::sync_with_stdio(false);cin.tie(0);cout.tie(0);}~Initializer(){runtime();}}initializer; //end #include <Core> #define idx(l,r) (((l)+(r))|((l)!=(r))) #define rt idx(l,r) #define lrt idx(l,m) #define rrt idx(m+1,r) const int MAXN=100000; struct node { int cnt,size; lli sum[5]; }; int a[MAXN]; mii idx; node st[(MAXN<<1)-1]; void upd(int l,int r,int p,int v) { if (p<l||r<p) ; else if (p<=l&&r<=p) { st[rt].cnt+=v; if (st[rt].cnt) { st[rt].size=1; rep(i,5) st[rt].sum[i]=0; st[rt].sum[0]=a[p]; } else { st[rt].size=0; rep(i,5) st[rt].sum[i]=0; } } else { int m=(l+r)>>1; upd(l,m,p,v),upd(m+1,r,p,v); st[rt].size=st[lrt].size+st[rrt].size; rep(i,5) st[rt].sum[i]=st[lrt].sum[i]; rep(i,5) st[rt].sum[(st[lrt].size+i)%5]+=st[rrt].sum[i]; } } lli qry(int l,int r) { rtn l<=r?st[rt].sum[2]:0; } #undef rc #undef lc #undef p #undef idx str op[MAXN]; int opx[MAXN]; int opxcpy[MAXN]; int main() { int n; cin>>n; rep(i,n) { cin>>op[i]; if (op[i]!= sum ) cin>>opx[i]; } cpy(opxcpy,opx); sort(opxcpy,opxcpy+n); rep(i,n) if (!idx.count(opxcpy[i])) idx.insert(mp(a[sz(idx)]=opxcpy[i],sz(idx))); rep(i,n) { if (op[i]== add ) upd(0,sz(idx)-1,idx[opx[i]],+1); else if (op[i]== del ) upd(0,sz(idx)-1,idx[opx[i]],-1); else cout<<qry(0,sz(idx)-1)<<endl; } } |
#include <bits/stdc++.h> using namespace std; map<pair<string, string>, pair<int, int> > mp; set<pair<string, string> > st; int main() { int n, d; cin >> n >> d; for (int i = 0; i < n; ++i) { string s, q; int x; cin >> s >> q; scanf( %d , &x); if (mp.count({q, s})) { pair<int, int> a = mp[{q, s}]; int y = x - a.first; if (y <= d && y > 0) st.insert({min(s, q), max(s, q)}); y = x - a.second; if (y <= d && y > 0) st.insert({min(s, q), max(s, q)}); } if (!mp.count({s, q})) mp[{s, q}] = {x, x}; else { pair<int, int> a = mp[{s, q}]; if (x != a.first) a.second = a.first, a.first = x; mp[{s, q}] = a; } } cout << st.size() << endl; for (set<pair<string, string> >::iterator it = st.begin(); it != st.end(); it++) printf( %s %s n , it->first.c_str(), it->second.c_str()); return 0; } |
// ****************************************************************************
// Copyright : NUDT.
// ============================================================================
// FILE NAME : outPUT_CTL.v
// CREATE DATE : 2013-12-03
// AUTHOR : ZengQiang
// AUTHOR'S EMAIL :
// AUTHOR'S TEL :
// ============================================================================
// RELEASE HISTORY -------------------------------------------------------
// VERSION DATE AUTHOR DESCRIPTION
// 1.0 2013-12-03 ZengQiang Original Verison
// ============================================================================
// KEYWORDS : N/A
// ----------------------------------------------------------------------------
// PURPOSE : SLOTid determine PKT to slot?
// ----------------------------------------------------------------------------
// ============================================================================
// REUSE ISSUES
// Reset Strategy : Async clear,active high
// Clock Domains : clk
// Critical TiminG : N/A
// Instantiations : N/A
// Synthesizable : N/A
// Others : N/A
// ****************************************************************************
module OUTPUT_CTL(
clk,
reset,
in_egress_pkt_wr,
in_egress_pkt,
in_egress_pkt_valid_wr,
in_egress_pkt_valid,
out_egress_pkt_almostfull,
out_slot0_pkt,
out_slot0_pkt_wr,
out_slot0_pkt_valid,
out_slot0_pkt_valid_wr,
in_slot0_pkt_almostfull,
out_slot1_pkt,
out_slot1_pkt_wr,
out_slot1_pkt_valid,
out_slot1_pkt_valid_wr,
in_slot1_pkt_almostfull,
output_receive_pkt_add,
output_discard_error_pkt_add,
output_send_slot0_pkt_add,
output_send_slot1_pkt_add
);
input clk;
input reset;
input in_egress_pkt_wr;
input [133:0] in_egress_pkt;
input in_egress_pkt_valid_wr;
input in_egress_pkt_valid;
output wire out_egress_pkt_almostfull;
output reg [133:0] out_slot0_pkt;
output reg out_slot0_pkt_wr;
output reg out_slot0_pkt_valid;
output reg out_slot0_pkt_valid_wr;
input in_slot0_pkt_almostfull;
output reg [133:0] out_slot1_pkt;
output reg out_slot1_pkt_wr;
output reg out_slot1_pkt_valid;
output reg out_slot1_pkt_valid_wr;
input in_slot1_pkt_almostfull;
output reg output_receive_pkt_add;
output reg output_discard_error_pkt_add;
output reg output_send_slot0_pkt_add;
output reg output_send_slot1_pkt_add;
reg [2:0] xaui_channel;
reg [2:0] current_state;//transmit processed pkt to 4 paths by the outport in the metadata of pkt
parameter idle_s = 3'b000,
discard_s = 3'b001,
transmit_s = 3'b010,
wait_s = 3'b011,
pkt_cut_s = 3'b100;
always@(posedge clk or negedge reset)
if(!reset)
begin
out_slot0_pkt_wr <= 1'b0;
out_slot0_pkt <= 134'b0;
out_slot0_pkt_valid_wr <= 1'b0;
out_slot0_pkt_valid <= 1'b0;
out_slot1_pkt_wr <= 1'b0;
out_slot1_pkt <= 134'b0;
out_slot1_pkt_valid_wr <= 1'b0;
out_slot1_pkt_valid <= 1'b0;
in_egress_pkt_valid_rd <= 1'b0;
in_egress_pkt_rd <= 1'b0;
xaui_channel <= 3'b0;//slot ID
output_receive_pkt_add <= 1'b0;
output_discard_error_pkt_add <= 1'b0;
output_send_slot0_pkt_add <= 1'b0;
output_send_slot1_pkt_add <= 1'b0;
current_state <= idle_s;
end
else
begin
case(current_state)
idle_s:begin//judge and poll pkt from pcietx and iace fifo,and reverse order metadata
out_slot0_pkt_wr <= 1'b0;
out_slot0_pkt <= 134'b0;
out_slot0_pkt_valid_wr <= 1'b0;
out_slot0_pkt_valid <= 1'b0;
out_slot1_pkt_wr <= 1'b0;
out_slot1_pkt <= 134'b0;
out_slot1_pkt_valid_wr <= 1'b0;
out_slot1_pkt_valid <= 1'b0;
output_discard_error_pkt_add <= 1'b0;
output_send_slot0_pkt_add <= 1'b0;
output_send_slot1_pkt_add <= 1'b0;
if(in_egress_pkt_valid_empty == 1'b0) begin//judge and poll pkt from pcietx and iace fifo
if(in_egress_pkt_valid_q == 1'b1) begin
if(in_egress_pkt_q[110] == 1'b0) begin//SLOTid
if(in_slot0_pkt_almostfull == 1'b1) begin
current_state <= idle_s;
end
else begin
in_egress_pkt_rd <= 1'b1;
in_egress_pkt_valid_rd <= 1'b1;
xaui_channel <= in_egress_pkt_q[112:110];//slot ID
output_receive_pkt_add <= 1'b1;
current_state <= transmit_s;
end
end
else begin
if(in_slot1_pkt_almostfull == 1'b1) begin
current_state <= idle_s;
end
else begin
in_egress_pkt_rd <= 1'b1;
in_egress_pkt_valid_rd <= 1'b1;
xaui_channel <= in_egress_pkt_q[112:110];
output_receive_pkt_add <= 1'b1;
current_state <= transmit_s;
end
end
end
else begin
in_egress_pkt_rd <= 1'b1;
in_egress_pkt_valid_rd <= 1'b1;
current_state <= discard_s;
end
end
else
current_state <= idle_s;
end
discard_s:begin//discard the error pkt from pcietx
in_egress_pkt_valid_rd <= 1'b0;
if(in_egress_pkt_q[133:132]==2'b10)
begin
output_discard_error_pkt_add <= 1'b1;
in_egress_pkt_rd <= 1'b0;
current_state <= idle_s;
end
else
begin
current_state<= discard_s;
end
end
transmit_s:begin//transmit pkt body from pcietx
output_receive_pkt_add <= 1'b0;
in_egress_pkt_valid_rd <= 1'b0;
case(xaui_channel[2:0])//slot
3'b000:begin
out_slot0_pkt_wr <=1'b1;
out_slot0_pkt <= in_egress_pkt_q;
if(in_egress_pkt_q[133:132]==2'b10)//pkt tail
begin
in_egress_pkt_rd <= 1'b0;
out_slot0_pkt_valid_wr <= 1'b1;
output_send_slot0_pkt_add <= 1'b1;
out_slot0_pkt_valid <= 1'b1;
current_state<= idle_s;
end
else//pkt head and pkt middle
begin
in_egress_pkt_rd <= 1'b1;
current_state<= transmit_s;
end
end
3'b001:begin
out_slot1_pkt_wr <=1'b1;
out_slot1_pkt <=in_egress_pkt_q;
if(in_egress_pkt_q[133:132]==2'b10)//pkt tail
begin
in_egress_pkt_rd <= 1'b0;
out_slot1_pkt_valid_wr <= 1'b1;
output_send_slot1_pkt_add <= 1'b1;
out_slot1_pkt_valid <= 1'b1;
current_state <= idle_s;
end
else//pkt head and pkt middle
begin
in_egress_pkt_rd <=1'b1;
current_state<= transmit_s;
end
end
endcase
end
endcase
end
wire [7:0] in_egress_pkt_usedw;
assign out_egress_pkt_almostfull = in_egress_pkt_usedw[7];
reg in_egress_pkt_rd;
wire [133:0] in_egress_pkt_q;
fifo_256_134 egress_pkt(
.aclr(!reset),
.clock(clk),
.data(in_egress_pkt),
.rdreq(in_egress_pkt_rd),
.wrreq(in_egress_pkt_wr),
.q(in_egress_pkt_q),
.usedw(in_egress_pkt_usedw)
);
reg in_egress_pkt_valid_rd;
wire in_egress_pkt_valid_empty;
wire in_egress_pkt_valid_q;
fifo_64_1 egress_pkt_valid(
.aclr(!reset),
.clock(clk),
.data(in_egress_pkt_valid),
.rdreq(in_egress_pkt_valid_rd),
.wrreq(in_egress_pkt_valid_wr),
.empty(in_egress_pkt_valid_empty),
.q(in_egress_pkt_valid_q)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; constexpr int full = 0x7fffffff; bool is_valid(const vector<int> &idx, const int max_i, const int i) { if (max_i < 0) return true; if (idx.at(i) == max_i) { return is_valid(idx, max_i - 1, i + 1); } int j; for (j = 1; idx.at(i) + j <= max_i; j++) { if (idx.at(i + j) != idx.at(i) + j) { return false; } } return is_valid(idx, idx.at(i) - 1, i + j); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int Ncases, N; cin >> Ncases; for (int _case = 0; _case < Ncases; _case++) { cin >> N; int p; vector<int> idx(N, -1); for (int i = 0; i < N; i++) { cin >> p; idx.at(p - 1) = i; } bool repeat = false; for (const int v : idx) { if (v == -1) { cout << No << endl; repeat = true; break; } } if (!repeat) { if (is_valid(idx, N - 1, 0)) { cout << Yes << endl; } else { cout << No << endl; } } } return 0; } |
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