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/********************************************/
/* sync_fifo.v */
/* simple single-clock fifo */
/* */
/* 2011, */
/********************************************/
module sync_fifo #(
parameter FD = 16, // fifo depth
parameter DW = 32 // data width
)(
// system
input wire clk, // clock
input wire rst, // reset
// fifo input / output
input wire [ DW-1:0] fifo_in, // write data
output wire [ DW-1:0] fifo_out, // read data
// fifo control
input wire fifo_wr_en, // fifo write enable
input wire fifo_rd_en, // fifo read enable
// fifo status
output wire fifo_full, // fifo full
output wire fifo_empty // fifo empty
);
////////////////////////////////////////
// log function //
////////////////////////////////////////
function integer CLogB2;
input [31:0] d;
integer i;
begin
i = d;
for(CLogB2 = 0; i > 0; CLogB2 = CLogB2 + 1) i = i >> 1;
end
endfunction
////////////////////////////////////////
// local parameters //
////////////////////////////////////////
localparam FCW = CLogB2(FD-1) + 1;
localparam FPW = CLogB2(FD-1);
////////////////////////////////////////
// local signals //
////////////////////////////////////////
// fifo counter
reg [FCW-1:0] fifo_cnt;
// fifo write & read pointers
reg [FPW-1:0] fifo_wp, fifo_rp;
// fifo memory
reg [ DW-1:0] fifo_mem [0:FD-1];
////////////////////////////////////////
// logic //
////////////////////////////////////////
// FIFO write pointer
always @ (posedge clk or posedge rst)
begin
if (rst)
fifo_wp <= #1 1'b0;
else if (fifo_wr_en && !fifo_full)
fifo_wp <= #1 fifo_wp + 1'b1;
end
// FIFO write
always @ (posedge clk)
begin
if (fifo_wr_en && !fifo_full) fifo_mem[fifo_wp] <= #1 fifo_in;
end
// FIFO counter
always @ (posedge clk or posedge rst)
begin
if (rst)
fifo_cnt <= #1 'd0;
// read & no write
else if (fifo_rd_en && !fifo_wr_en && (fifo_cnt != 'd0))
fifo_cnt <= #1 fifo_cnt - 'd1;
// write & no read
else if (fifo_wr_en && !fifo_rd_en && (fifo_cnt != FD))
fifo_cnt <= #1 fifo_cnt + 'd1;
end
// FIFO full & empty
assign fifo_full = (fifo_cnt == (FD));
assign fifo_empty = (fifo_cnt == 'd0);
// FIFO read pointer
always @ (posedge clk or posedge rst)
begin
if (rst)
fifo_rp <= #1 1'b0;
else if (fifo_rd_en && !fifo_empty)
fifo_rp <= #1 fifo_rp + 1'b1;
end
// FIFO read
assign fifo_out = fifo_mem[fifo_rp];
endmodule
|
#include <bits/stdc++.h> using namespace std; const int fx[8] = {0, -1, -1, -1, 0, 1, 1, 1}; const int fy[8] = {1, 1, 0, -1, -1, -1, 0, 1}; const int maxn = 310; int vis[maxn][maxn][8][30]; int v[maxn][maxn]; int step[40]; queue<pair<int, int> > q; pair<int, int> mkstate(int x, int y, int d, int t) { return make_pair(x * 10000 + y, d * 10000 + t); } int main() { int n; cin >> n; for (int i = 0; i < n; i++) cin >> step[i]; while (!q.empty()) q.pop(); q.push(mkstate(155, 155, 0, 0)); vis[155][155][0][0] = true; while (!q.empty()) { pair<int, int> t = q.front(); q.pop(); int x = t.first / 10000; int y = t.first % 10000; int d = t.second / 10000; int th = t.second % 10000; for (int i = 0; i < step[th]; i++) { v[x + fx[d] * i][y + fy[d] * i] = 1; } int nx = x + fx[d] * (step[th] - 1); int ny = y + fy[d] * (step[th] - 1); int d1 = (d + 1) % 8; int x1 = nx + fx[d1]; int y1 = ny + fy[d1]; int d2 = (d - 1 + 8) % 8; int x2 = nx + fx[d2]; int y2 = ny + fy[d2]; pair<int, int> t1 = mkstate(x1, y1, d1, th + 1); pair<int, int> t2 = mkstate(x2, y2, d2, th + 1); if (th + 1 < n && !vis[x1][y1][d1][th + 1]) { q.push(t1); vis[x1][y1][d1][th + 1] = true; } if (th + 1 < n && !vis[x2][y2][d2][th + 1]) { q.push(t2); vis[x2][y2][d2][th + 1] = true; } } int ans = 0; for (int i = 0; i < maxn; i++) { for (int j = 0; j < maxn; j++) { if (v[i][j]) ans++; } } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; int x, cnt; vector<int> rj; bool good(int n) { bool t = false; for (int i = 20; i >= 0; i--) { if (n & (1 << i)) t = true; if (t && !(n & (1 << i))) return false; } return true; } int fix(int n) { bool t = false; for (int i = 20; i >= 0; i--) { if (n & (1 << i)) t = true; if (t && !(n & (1 << i))) { int m = (1 << (i + 1)) - 1; n ^= m; rj.push_back(i + 1); break; } } return n; } void stop(int n) { cout << n << n ; for (int i = 0; i < rj.size(); i++) { cout << rj[i] << ; } exit(0); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> x; if (good(x)) stop(cnt); while (true) { x = fix(x); cnt++; if (good(x)) stop(cnt); x++; cnt++; if (good(x)) stop(cnt); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 1029384756; const double PI = acos(-1); const double EPS = 0.0000000304; long long A, B, C; int main() { scanf( %I64d%I64d%I64d , &A, &B, &C); if ((A % 2) == (B % 2) && (B % 2) == (C % 2)) { printf( %I64d , A + B + C - max(A, max(B, C)) - min(A, min(B, C))); } else if (A % 2 == B % 2) { printf( %I64d , max(A, B)); } else if (A % 2 == C % 2) { printf( %I64d , max(A, C)); } else { printf( %I64d , max(B, C)); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = (1e9) + 7; bool mark[2501][101]; long long a[2501][101]; long long dp(int x, int y) { if (x > 0 && y == 0) return 0; if (x == 0 && y == 0) return 1; if (mark[x][y]) return a[x][y]; long long ans = 0; for (int i = 0; i <= min(25, x); i++) ans += dp(x - i, y - 1); a[x][y] = (ans % maxn); mark[x][y] = 1; return a[x][y]; } int main() { int t, counter; string s; cin >> t; for (int i = 0; i < t; i++) { cin >> s; counter = 0; for (int j = 0; j < s.size(); j++) counter += int(s[j] - a ); cout << (dp(counter, s.size()) + maxn - 1) % maxn << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long a[3000005], has[3000005], visited[2000005], dist[1000005]; long long pr[3000010]; long long addmod(long long n, long long m) { return ((n % 1000000007) + (m % 1000000007)) % 1000000007; } long long multmod(long long n, long long m) { return ((n % 1000000007) * (m % 1000000007)) % 1000000007; } long long submod(long long n, long long m) { return ((n % 1000000007) - (m % 1000000007) + 1000000007) % 1000000007; } void prime() { pr[0] = 1; pr[1] = 1; for (long long i = 2; i <= sqrt(3000010); i++) { for (long long j = 2 * i; j <= 3000010; j += i) { pr[j] = 1; } } } long long cntDiv(long long n) { long long cnt = 0; for (long long i = 1; i <= sqrt(n); i++) { if (n % i == 0) { if (n / i == i) cnt++; else cnt += 2; } } return cnt; } long long gcd(long long a, long long b) { if (a == 0) return b; return gcd(b % a, a); } long long has1[3000011], b[1000005], temp1[1000005]; vector<long long> mat[10001]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long x, y, z, w; cin >> x >> y >> z >> w; if (x + y == z + w || x + z == y + w || x + w == y + z || x == y + z + w || y == x + z + w || z == x + y + w || w == x + y + z) cout << YES ; else cout << NO ; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long int inf = 9e18; const long double pi = 2 * acos(0.0); long long int arr[100005]; void solve() { long long int n, k; cin >> n >> k; ; for (int i = 0; i < n; i++) cin >> arr[i]; ; long long int mn = inf, pos = 0; for (long long int i = 0; i < n; ++i) { if (arr[i] < mn) { mn = arr[i]; pos = i; } } long long int ans = 0; for (long long int i = 0; i < n; ++i) { if (i == pos) continue; long long int t = abs(k - arr[i]); ans += (t / mn); } cout << ans << n ; return; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long int tc = 1; cin >> tc; while (tc--) { solve(); } } |
#include <bits/stdc++.h> using namespace std; vector<int> e[200010]; struct Node { int sz, l; } c[200010]; bool cmp(const Node &p, const Node &q) { return (p.sz - p.l) > (q.sz - q.l); } void dfs(int x, int fa) { c[x].l = c[fa].l + 1; for (int i = 0; i < (int)e[x].size(); i++) { int y = e[x][i]; if (y == fa) continue; dfs(y, x); c[x].sz += c[y].sz; } c[x].sz++; } int main() { int n, k; scanf( %d%d , &n, &k); k = n - k; for (int i = 1; i < n; i++) { int a, b; scanf( %d%d , &a, &b); e[a].push_back(b); e[b].push_back(a); } dfs(1, 0); sort(c + 1, c + n + 1, cmp); long long ans = 0; for (int i = 1; i <= k; i++) { ans += (c[i].sz - c[i].l); } printf( %I64d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int q, n; int a[100010], b[100010]; int main() { scanf( %d , &q); while (q--) { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int i = 1; i <= n; i++) scanf( %d , &b[i]); int pos = 0, dis = 0, flag1 = 0, flag2 = 0; for (int i = 1; i <= n; i++) { if (a[i] != b[i] && flag1 == 0) { pos = i; dis = b[i] - a[i]; if (dis < 0) { flag2 = 1; break; } flag1 = 1; } else if (a[i] != b[i] && flag1 == 1) { if (b[i] - a[i] != dis || i != pos + 1) { flag2 = 1; break; } else pos = i; } } if (flag2) printf( NO n ); else printf( YES n ); } return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Wed May 03 18:20:15 2017
// Host : LAPTOP-IQ9G3D1I running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/andrewandre/Documents/GitHub/kernel-on-chip/hdl/projects/Nexys4/bd/ip/bd_clk_wiz_0_0/bd_clk_wiz_0_0_stub.v
// Design : bd_clk_wiz_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module bd_clk_wiz_0_0(clk_ref_i, aclk, sys_clk_i, resetn, clk_in1)
/* synthesis syn_black_box black_box_pad_pin="clk_ref_i,aclk,sys_clk_i,resetn,clk_in1" */;
output clk_ref_i;
output aclk;
output sys_clk_i;
input resetn;
input clk_in1;
endmodule
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module fx2_to_bus #(
parameter WIDTH = 16 // 16 bit bus from FX2
) (
input wire [WIDTH-1:0] ADD,
input wire RD_B, // neg active, two clock cycles
input wire WR_B, // neg active
input wire BUS_CLK, // FCLK
output wire [WIDTH-1:0] BUS_ADD,
output wire BUS_RD,
output wire BUS_WR,
output wire CS_FPGA
);
// remove offset from FX2
assign BUS_ADD = ADD - 16'h4000;
// chip select FPGA
assign CS_FPGA = ~ADD[15] & ADD[14];
// generate read strobe which one clock cycle long
// this is very important to prevent corrupted data
reg RD_B_FF;
always @(posedge BUS_CLK) begin
RD_B_FF <= RD_B;
end
assign BUS_RD = ~RD_B & RD_B_FF;
assign BUS_WR = ~WR_B;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, n1, n2; scanf( %d%d%d , &n, &n1, &n2); if (n1 > n2) swap(n1, n2); vector<double> X; double x; for (int i = 0; i < n; i++) { scanf( %lf , &x); X.push_back(x); } sort(X.begin(), X.end()); double sum1 = 0, sum2 = 0; for (int i = n - n1 - n2; i < n; i++) { if (i < n - n1) sum2 += X[i]; else sum1 += X[i]; } sum1 /= n1; sum2 /= n2; printf( %.8lf , sum1 + sum2); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; for (int p = 0; p < t; ++p) { int n; cin >> n; int d[2][n]; for (int i = 0; i <= 1; ++i) { for (int j = 0; j < n; ++j) cin >> d[i][j]; } if (n == 1) cout << 0 << endl; else { int suff[n], pref[n]; suff[0] = 0; pref[0] = 0; for (int i = 1; i < n; ++i) { suff[i] = d[0][n - i] + suff[i - 1]; pref[i] = d[1][i - 1] + pref[i - 1]; } int res = 2e9; for (int i = 0; i < n; ++i) { res = min(res, max(suff[n - 1 - i], pref[i])); } cout << res << endl; } } } |
#include <bits/stdc++.h> using namespace std; int read() { int x = 0, f = 1; char c = getchar(); while (c < 0 or c > 9 ) { if (c == - ) f = -f; c = getchar(); } while (c >= 0 and c <= 9 ) { x = x * 10 + c - 0 ; c = getchar(); } return x * f; } struct EDGE { int to, Next; } edge[400100]; struct DOTS { long long cnt, num[2], all, sum, dpth; vector<int> sons; } dot[200100]; int n; int h[200100], cnt; long long ans; bool vis[200100]; void add(int from, int to) { edge[++cnt].to = to; edge[cnt].Next = h[from]; h[from] = cnt; } void dfs(int t) { vis[t] = 1; dot[t].num[0]++; for (int i = h[t]; i; i = edge[i].Next) { int v = edge[i].to; if (!vis[v]) { dot[t].cnt++; dot[t].sons.push_back(v); dot[v].dpth = dot[t].dpth + 1; dfs(v); ans += dot[t].num[0] * dot[v].num[1] * 2 * dot[t].sum; ans %= 1000000007; ans -= dot[t].num[1] * dot[v].num[0] * 2 * dot[t].sum; ans %= 1000000007; dot[t].num[0] += dot[v].num[1]; dot[t].num[1] += dot[v].num[0]; } } ans += dot[t].sum; } void dp(int t) { for (int i = 0; i < dot[t].cnt; ++i) { int v = dot[t].sons[i]; ans += dot[v].num[0] * (dot[1].num[dot[v].dpth & 1] - dot[v].num[0]) * 2 * dot[v].sum; ans %= 1000000007; ans -= dot[v].num[1] * (dot[1].num[(dot[v].dpth ^ 1) & 1] - dot[v].num[1]) * 2 * dot[v].sum; ans %= 1000000007; dp(v); } } int main() { n = read(); for (int i = 1; i <= n; ++i) dot[i].sum = read(); for (int i = 1; i < n; ++i) { int u = read(); int v = read(); add(u, v); add(v, u); } dfs(1); dp(1); ans %= 1000000007; ans += 1000000007; ans %= 1000000007; printf( %lld , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; double pi = 4 * atan(1.0); double eps = 1e-9; string stringmin = ! ; string stringmax = ~ ; int main() { cout.precision(14); int n; cin >> n; vector<int> v(n), vlen(n); for (auto &i1 : v) cin >> i1; for (int i = 0; i < n; i++) { int f1 = 0; int q = i; for (int j = 0; j < 101; j++) { q = v[q] - 1; if (q == i) { f1 = 1; vlen[i] = j + 1; break; } } if (!f1) { cout << -1; return 0; } } for (auto &i1 : vlen) if ((i1 & 1) == 0) i1 >>= 1; long long ans = 1; for (int i = 2; i < 110; i++) { int maxcnt = 0; for (auto &i1 : vlen) { int cnt = 0; while (i1 % i == 0) { cnt++; i1 /= i; } maxcnt = max(cnt, maxcnt); } for (int j = 0; j < maxcnt; j++) ans *= i; } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; long long max(long long a, long long b) { if (a > b) return a; else return b; } long long min(long long a, long long b) { if (a < b) return a; else return b; } long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } int n, m, len1 = 1, len2 = 1, ans; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> m; for (int a = 7; a < n; a *= 7) len1 += 1; for (int b = 7; b < m; b *= 7) len2 += 1; if (len1 + len2 <= 7) { for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { vector<int> used(7, 0); for (int a = i, k = 0; k < len1; a /= 7, k++) used[a % 7] += 1; for (int b = j, k = 0; k < len2; b /= 7, k++) used[b % 7] += 1; if (*max_element(used.begin(), used.end()) <= 1) ans++; } } cout << ans; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A32OI_BLACKBOX_V
`define SKY130_FD_SC_LS__A32OI_BLACKBOX_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a32oi (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A32OI_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const long long mod = 998244353; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n; long long k; cin >> n >> k; if (!k) { cout << 0 n ; return 0; } vector<int> h(n); for (int i = 0; i < n; i++) { cin >> h[i]; } h.push_back(h[0]); long long** dp; dp = new long long*[n + 79]; for (int i = 0; i < n + 2; i++) { dp[i] = new long long[2 * n + 79]; for (int j = 0; j < 2 * n + 79; j++) { dp[i][j] = 0; } } dp[0][n + 1] = 1; for (int i = 1; i <= n; i++) { for (int score = 1; score <= 2 * n + 2; score++) { if (h[i] != h[i - 1]) { dp[i][score] += dp[i - 1][score - 1]; dp[i][score] += dp[i - 1][score + 1]; dp[i][score] += (dp[i - 1][score] * (k - 2ll)) % mod; } else { dp[i][score] = dp[i - 1][score] * k; } dp[i][score] %= mod; } } long long ans = 0; for (int score = n + 2; score <= 2 * n + 1; score++) { ans += dp[n][score]; } cout << (ans % mod) << endl; return 0; } |
module Mod_Teste(
input CLOCK_27,
input CLOCK_50,
input [3:0] KEY,
input [17:0] SW,
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
output [6:0] HEX6,
output [6:0] HEX7,
output [8:0] LEDG,
output [17:0] LEDR,
output LCD_ON, // LCD Power ON/OFF
output LCD_BLON, // LCD Back Light ON/OFF
output LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
output LCD_EN, // LCD Enable
output LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
inout [7:0] LCD_DATA, // LCD Data bus 8 bits
//////////////////////// GPIO ////////////////////////////////
inout [35:0] GPIO_0 = 36'hzzzzzzzzz, // GPIO Connection 0
inout [35:0] GPIO_1 = 36'hzzzzzzzzz
);
parameter WORD_WIDTH = 16;
parameter DR_WIDTH = 3;
parameter SB_WIDTH = DR_WIDTH;
parameter SA_WIDTH = DR_WIDTH;
parameter OPCODE_WIDTH = 7;
parameter CNTRL_WIDTH = DR_WIDTH+SB_WIDTH+SA_WIDTH+11;
parameter COUNTER_WIDTH = 4;
wire RST = KEY[0], CLK = KEY[3];
// LCD
assign LCD_ON = 1'b1;
assign LCD_BLON = 1'b1;
Output_LiquidCyrstalDisplay_TestModule LCD0 (
// Host Side
.iCLK ( CLOCK_50 ),
.iRST_N ( KEY[0] ),
// Data to display
.d0(PC_status), // 4 dígitos canto superior esquerdo
.d1(ADDR_bus), // 4 dígitos superior meio
.d2(INSTR_bus), // 4 dígitos canto superior direito
.d3(D_bus), // 4 dígitos canto inferior esquerdo
.d4(), // 4 dígitos inferior meio
.d5(), // 4 dígitos canto inferior direito
// LCD Side
.LCD_DATA( LCD_DATA ),
.LCD_RW( LCD_RW ),
.LCD_EN( LCD_EN ),
.LCD_RS( LCD_RS )
);
Computer CPU0 (
.COUNTER_bus(PC_status),
.ADDR_bus(ADDR_bus),
.DATA_bus(DATA_bus),
.CLK(KEY[3]),
.RST(KEY[0])
);
endmodule |
#include <bits/stdc++.h> using namespace std; const int mo = 1000000007; char S[2005], A[2][2005]; int ans, n, m, P[2][2005][2005], Q[2][2005][2005]; long long H[2005], w[2][2005], W[2005], N[2005]; bool IS(int u, int p, int q, int l, int r) { return (w[u][q] - w[u][p - 1]) * H[2000 - p] == (W[r] - W[l - 1]) * H[2000 - l]; } bool NS(int u, int p, int q, int l, int r) { return (w[u][q] - w[u][p - 1]) * H[2000 - p] == (N[l] - N[r + 1]) * H[1999 - m + r]; } int main() { scanf( %s , A[0] + 1); scanf( %s , A[1] + 1); n = strlen(A[0] + 1); scanf( %s , S + 1); m = strlen(S + 1); H[0] = 1; for (int i = 1; i <= 2000; ++i) H[i] = H[i - 1] * 29; for (int i = 1; i <= n; ++i) { w[0][i] = w[0][i - 1] + 1ll * (A[0][i] - a ) * H[i]; w[1][i] = w[1][i - 1] + 1ll * (A[1][i] - a ) * H[i]; } for (int i = 1; i <= m; ++i) W[i] = W[i - 1] + 1ll * (S[i] - a ) * H[i]; for (int i = m; i >= 1; --i) N[i] = N[i + 1] + 1ll * (S[i] - a ) * H[m - i + 1]; for (int u = 0; u < 2; ++u) for (int i = 0; i <= n + 1; ++i) P[u][i][m + 1] = Q[u][i][m + 1] = 1; for (int i = n; i; --i) for (int j = 1; j <= m; ++j) for (int u = 0, v = 1; u < 2; ++u, v = 0) if (A[u][i] == S[j]) { P[u][i][j] = P[u][i + 1][j + 1]; if (A[v][i] == S[j + 1]) (P[u][i][j] += P[v][i + 1][j + 2]) %= mo; if ((m - j + 1) % 2 == 0 && m - j + 1 <= (n - i + 1) * 2) { int x = m - j + 1 >> 1; if (x > 1 && IS(u, i, i + x - 1, j, j + x - 1) && NS(v, i, i + x - 1, j + x, m)) (++P[u][i][j]) %= mo; } } for (int i = 1; i <= n; ++i) for (int j = 1; j <= m; ++j) for (int u = 0, v = 1; u < 2; ++u, v = 0) if (A[u][i] == S[j]) { Q[u][i][j] = Q[u][i - 1][j + 1]; if (A[v][i] == S[j + 1]) (Q[u][i][j] += Q[v][i - 1][j + 2]) %= mo; if ((m - j + 1) % 2 == 0 && m - j + 1 <= i * 2) { int x = m - j + 1 >> 1; if (x > 1 && NS(u, i - x + 1, i, j, j + x - 1) && IS(v, i - x + 1, i, j + x, m)) (++Q[u][i][j]) %= mo; } } for (int i = 1; i <= n; ++i) for (int u = 0, v = 1; u < 2; ++u, v = 0) if (A[u][i] == S[1]) { if (m == 1) { ++ans; continue; } if (A[v][i] == S[2]) if (m == 2) ++ans; else (ans += (P[v][i + 1][3] + Q[v][i - 1][3]) % mo) %= mo; for (int j = 2; j <= m && j <= n - i + 1; ++j) { if (!IS(u, i, i + j - 1, 1, j)) break; if (j == m) { (++ans) %= mo; break; } if (A[v][i + j - 1] != S[j + 1]) continue; if (j + 1 == m) { (++ans) %= mo; continue; } if (j * 2 <= m) { if (NS(v, i, i + j - 1, j + 1, j * 2)) (ans += Q[v][i - 1][j * 2 + 1]) %= mo; } else if (NS(v, i + j - m + j, i + j - 1, j + 1, m)) (++ans) %= mo; (ans += P[v][i + j][j + 2]) %= mo; } for (int j = 2; j <= m && j <= i; ++j) { if (!NS(u, i - j + 1, i, 1, j)) break; if (j == m) { (++ans) %= mo; break; } if (A[v][i - j + 1] != S[j + 1]) continue; if (j + 1 == m) { (++ans) %= mo; continue; } if (j * 2 <= m) { if (IS(v, i - j + 1, i, j + 1, j * 2)) (ans += P[v][i + 1][j * 2 + 1]) %= mo; } else if (IS(v, i - j + 1, i - j + m - j, j + 1, m)) (++ans) %= mo; (ans += Q[v][i - j][j + 2]) %= mo; } } printf( %d n , ans); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:20:53 02/28/2016
// Design Name:
// Module Name: sequencDetector
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sequencDetector(
input in,
input reset,
input clock,
output reg out
);
reg [2:0] state;
parameter s0 = 3'b000, s1 = 3'b001, s2 = 3'b010, s3 = 3'b011, s4 = 3'b100, s5 = 3'b101;
always @(posedge clock)
begin
if (reset)
begin
state <= s0;
out <= 0 ;
end
else
case(state)
s0 : if (in) begin state <= s1; out <= 0 ; end
else begin state <= s0; out <= 0 ; end
s1 : if (in) begin state <= s1; out <= 0 ; end
else begin state <= s2; out <= 0 ; end
s2 : if (in) begin state <= s1; out <= 0 ; end
else begin state <= s3; out <= 0 ; end
s3 : if (in) begin state <= s1; out <= 0 ; end
else begin state <= s4; out <= 0 ; end
s4 : if (in) begin state <= s5; out <= 1 ; end
else begin state <= s0; out <= 0 ; end
s5 : if (in) begin state <= s1; out <= 0 ; end
else begin state <= s2; out <= 0 ; end
default: if (in) begin state <= s0; out <= 0 ; end
else begin state <= s0; out <= 0 ; end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1000000007; long double PI = 4 * atan(1); int n, r, val[2001], x, flag, ch[2001]; bool isChild[2001][2001]; pair<int, int> p[2001]; vector<int> v[2001]; queue<int> q1, q2, ans; void solve(int i) { int rem = ch[i] - p[i].second; while (ans.size()) { x = ans.front(); if (isChild[i][x]) { if (rem > 0) { val[x]++; q2.push(x); } else { if (rem == 0) { q2.push(i); val[i] = val[x] + 1; } q2.push(x); } rem--; } else { q1.push(x); } ans.pop(); } if (rem == 0 || !q2.size()) { q2.push(i); val[i] = 1; } while (q1.size() && q2.size()) { if (val[q1.front()] >= val[q2.front()]) { ans.push(q1.front()); q1.pop(); } else { ans.push(q2.front()); q2.pop(); } } while (q1.size()) { ans.push(q1.front()); q1.pop(); } while (q2.size()) { ans.push(q2.front()); q2.pop(); } } void dfs(int i, int p) { for (int a : v[i]) { if (a != p) { dfs(a, i); } } solve(i); return; } void calc(int par, int i, int p) { ch[par]++; isChild[par][i] = true; for (int a : v[i]) { if (a != p) { calc(par, a, i); } } } int main() { ios::sync_with_stdio(0), cin.tie(0); cin >> n; for (int i = 1; i < n + 1; i++) { cin >> p[i].first >> p[i].second; if (p[i].first != 0) v[p[i].first].push_back(i); else r = i; } for (int i = 1; i < n + 1; i++) calc(i, i, p[i].first), ch[i]--; for (int i = 1; i < n + 1; i++) { if (p[i].second > ch[i]) { cout << NO ; return 0; } } dfs(r, 0); cout << YES n ; for (int i = 1; i < n + 1; i++) cout << val[i] << ; return 0; } |
#include <bits/stdc++.h> using namespace std; map<long long, long long> mp[12]; long long a[200005], dig[200005]; long long state[200005][12]; int main() { long long n, k; scanf( %lld %lld , &n, &k); for (int i = 0; i < n; i++) scanf( %lld , &a[i]); for (int i = 0; i < n; i++) { dig[i] = log10(a[i]) + 1; } for (int i = 0; i < n; i++) { long long x = a[i]; long long tencnt = 1; while (tencnt < 11) { x = (x * 10LL) % k; mp[tencnt][x]++; state[i][tencnt] = x; tencnt++; } } long long ans = 0; for (int i = 0; i < n; i++) { long long len = dig[i]; long long m = (k - (a[i] % k)) % k; if (mp[len].count(m) == 0) continue; ans += mp[len][m]; } for (int i = 0; i < n; i++) { long long len = dig[i]; long long x = state[i][len]; if ((x + a[i]) % k == 0) { ans--; } } printf( %lld n , ans); } |
#include <bits/stdc++.h> using namespace std; string to_string(bool b) { return (b ? true : false ); } template <size_t N> string to_string(bitset<N> v) { string res = ; for (size_t i = 0; i < N; i++) { res += static_cast<char>( 0 + v[i]); } return res; } template <typename A> string to_string(A v) { bool first = true; string res = { ; for (const auto& x : v) { if (!first) { res += , ; } first = false; res += to_string(x); } res += } ; return res; } template <typename A, typename B> string to_string(pair<A, B> p) { return ( + to_string(p.first) + , + to_string(p.second) + ) ; } template <typename A, typename B, typename C> string to_string(tuple<A, B, C> p) { return ( + to_string(get<0>(p)) + , + to_string(get<1>(p)) + , + to_string(get<2>(p)) + ) ; } template <typename A, typename B, typename C, typename D> string to_string(tuple<A, B, C, D> p) { return ( + to_string(get<0>(p)) + , + to_string(get<1>(p)) + , + to_string(get<2>(p)) + , + to_string(get<3>(p)) + ) ; } void debug_out() { cerr << endl; } template <typename Head, typename... Tail> void debug_out(Head H, Tail... T) { cout << << to_string(H); debug_out(T...); } mt19937_64 rng(std::chrono::steady_clock::now().time_since_epoch().count()); template <typename T> using V = vector<T>; template <typename T> bool ckmin(T& a, const T& b) { return b < a ? a = b, 1 : 0; } template <typename T> bool ckmax(T& a, const T& b) { return a < b ? a = b, 1 : 0; } template <class T> using pqg = priority_queue<T, vector<T>, greater<T>>; const int dx[4] = {1, 0, -1, 0}, dy[4] = {0, 1, 0, -1}; using ll = long long; using db = long double; using vd = vector<db>; using vs = vector<string>; using pi = pair<int, int>; using vi = vector<int>; using vb = vector<bool>; using vl = vector<ll>; using vpi = vector<pi>; const int mod = 1000000007; const ll INF = 1e18; const db PI = acos((db)-1); constexpr int pct(int x) { return __builtin_popcount(x); } constexpr int bits(int x) { return x == 0 ? 0 : 31 - __builtin_clz(x); } constexpr int p2(int x) { return 1 << x; } constexpr int msk2(int x) { return p2(x) - 1; } const int mx = 1e5 + 10; int n, m; int arr[mx][10], nex[mx][10]; void solve() { cin >> n >> m; for (int j = (0); j < (m); ++j) for (int i = (0); i < (n); ++i) cin >> arr[i][j]; for (int j = (0); j < (m); ++j) { for (int i = (0); i < (n - 1); ++i) nex[arr[i][j]][j] = arr[i + 1][j]; } for (int j = (1); j < (m); ++j) { for (int i = (1); i < (n + 1); ++i) { if (nex[i][0] && (nex[i][0] != nex[i][j])) nex[i][0] = 0; } } ll ans = 0; int prev = -1; for (int i = (0); i < (n); ++i) { if (!nex[arr[i][0]][0]) { int len = i - prev; ans += 1LL * len * (len + 1) / 2; prev = i; } } cout << ans << n ; } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int tt = 1; for (int ii = 1; ii <= tt; ii++) solve(); } |
#include <bits/stdc++.h> using namespace std; string imp = Impossible n ; mt19937_64 rng(chrono::steady_clock::now().time_since_epoch().count()); clock_t startTime; double getCurrentTime() { return (double)(clock() - startTime) / CLOCKS_PER_SEC; } const int N = 1e5 + 1e3; long long MOD = 1e9 + 7; vector<int> aa[N]; int a[N], b[N], c[N]; int n, m, k, i, j; bool d[N]; string s; bool iscons(char c) { if (c != a && c != e && c != i && c != o && c != u ) return true; return false; } int main() { startTime = clock(); ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int tests = 1; while (tests--) { cin >> s; int ns = s.size(); if (ns < 3) { cout << s; return 0; } int cons = 0; if (iscons(s[1])) { if (iscons(s[0])) cons += 2; else cons++; } cout << s[0] << s[1]; for (int i = 2; i < ns; i++) { if (iscons(s[i])) { cons++; if (cons == 3) { if (s[i] == s[i - 1] && s[i - 1] == s[i - 2]) cons = 2; } } else cons = 0; if (cons == 3) { cout << ; cons = 1; } cout << s[i]; } } return 0; } |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:134217728 ) using namespace std; const long long MOD = 1000000000 + 7; const long long MAGIC = 123123123; const double PI = 4 * atan(1.); const double EPS = 1E-7; void time_elapsed() { cout << nTIME ELAPSED: << (double)clock() / CLOCKS_PER_SEC << sec n ; } struct frac; template <typename T> T gcd(T a, T b) { return ((b == 0) ? a : gcd(b, a % b)); } template <class T> T gcd(T a, T b, T& x, T& y) { if (!a) { x = 0, y = 1; return b; } T x1, y1; T d = gcd(b % a, a, x1, y1); x = y1 - (b / a) * x1; y = x1; return d; } template <typename T> T lcm(T a, T b) { return (a / gcd(a, b)) * b; } template <typename T, typename M> T neg_mod(T a, M mod) { return ((a % mod) + mod) % mod; } long long binpow(long long x, long long p) { long long res = 1; while (p) { if (p & 1) res *= x; x *= x; p >>= 1; } return res; } long long binpow_mod(long long x, long long p, long long m) { long long res = 1; while (p) { if (p & 1) res = (res * x) % m; x = (x * x) % m; p >>= 1; } return res; } struct cmp_for_set { bool operator()(const pair<long long, long long>& a, const pair<long long, long long>& b) const { return a > b; } }; string a, b; map<char, int> amap; bool check(int len, map<char, int>& need, string& res) { map<char, int> aa = amap; for (auto it : need) { if (aa[it.first] < it.second) { return false; } aa[it.first] -= it.second; if (aa[it.first] == 0) { aa.erase(it.first); } } res.resize(a.size()); for (int i = 0; i < len; ++i) { res[i] = b[i]; } if (len == b.size()) { return true; } char nxt = 0 - 1; for (auto it : aa) { if (it.first < b[len] && it.second > 0) { nxt = it.first; } } if (nxt == 0 - 1) { return false; } res[len] = nxt; aa[nxt]--; vector<char> toadd; for (auto it : aa) { for (int j = 0; j < it.second; ++j) { toadd.push_back(it.first); } } for (int i = 0; i < toadd.size(); ++i) { res[len + 1 + i] = toadd[(int)toadd.size() - 1 - i]; } return true; } int main() { cin >> a >> b; for (int i = 0; i < a.size(); ++i) { amap[a[i]]++; } string res = a; sort(res.begin(), res.end()); if (a.size() < b.size()) { sort(res.rbegin(), res.rend()); cout << res; return 0; } map<char, int> need; for (int i = 0; i <= b.size(); ++i) { string cur; if (check(i, need, cur)) { res = cur; } need[b[i]]++; } cout << res; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, y, a[(int)1e5 + 4]; unsigned long long x, sum; void error() { puts( -1 ); exit(0); } int main() { scanf( %d%I64d%d , &n, &x, &y); sum = (unsigned long long)n; if (n > y || (n == y && sum < x)) error(); for (int i = 0; i < n; i++) a[i] = 1; a[n - 1] += (y - n); if (sum - 1LL + (unsigned long long)a[n - 1] * (unsigned long long)a[n - 1] < x) error(); for (int i = 0; i < n; i++) printf( %d n , a[i]); return 0; } |
#include <bits/stdc++.h> using namespace std; long long ans; long long arr[300005][8]; long long a, b; bool ok(long long mid, long long n, long long m) { long long mx = (1LL << m) - 1; long long cnt[mx + 1]; for (int i = 0; i <= mx; i++) cnt[i] = 0; for (int i = 0; i < n; i++) { long long tem = 0; for (int j = 0; j < m; j++) { if (arr[i][j] >= mid) { tem = tem | (1LL << j); } } cnt[tem] = i + 1; } for (int i = 0; i <= mx; i++) { for (int j = i; j <= mx; j++) { if (cnt[i] && cnt[j]) { long long tem = i | j; if (tem == mx) { a = cnt[i]; b = cnt[j]; return true; } } } } return false; } int main() { ios_base::sync_with_stdio(0); cin.tie(nullptr); ; int n, m; cin >> n >> m; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) cin >> arr[i][j]; } long long lo = 0; long long hi = 1e9; a = 1; b = 1; while (lo <= hi) { long long mid = (lo + hi) / 2; if (ok(mid, n, m)) { ans = mid; lo = mid + 1; } else { hi = mid - 1; } } cout << a << << b << endl; return 0; } |
//==============================================================================
// File: $URL: svn+ssh:///public/Projects/GateLib/branches/dev/Publications/Tutorials/Publications/EECS150/Labs/ChipScopeSerial/Framework/Counter.v $
// Version: $Revision: 26904 $
// Author: Greg Gibeling (http://www.gdgib.com)
// Copyright: Copyright 2003-2010 UC Berkeley
//==============================================================================
//==============================================================================
// Section: License
//==============================================================================
// Copyright (c) 2003-2010, Regents of the University of California
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
//
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer
// in the documentation and/or other materials provided with the
// distribution.
// - Neither the name of the University of California, Berkeley nor the
// names of its contributors may be used to endorse or promote
// products derived from this software without specific prior
// written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
// ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//==============================================================================
//------------------------------------------------------------------------------
// Module: Counter
// Desc: Standard binary counter.
// Params: Width: The bitwidth of the counter.
// Limited:Should the counter saturate rather than roll over?
// Down: Should the counter count down (decrement) rather than
// up (increment)? Note that this will, obviously, affect
// the limit, if used.
// Author: <a href="http://www.gdgib.com/">Greg Gibeling</a>
// Version: $Revision: 26904 $
//------------------------------------------------------------------------------
module Counter(Clock, Reset, Set, Load, Enable, In, Count);
//--------------------------------------------------------------------------
// Parameters
//--------------------------------------------------------------------------
parameter Width = 32,
Limited = 0,
Down = 0,
Initial = {Width{1'bx}},
AsyncReset = 0,
AsyncSet = 0;
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// I/O
//--------------------------------------------------------------------------
input Clock, Reset, Set, Load, Enable;
input [Width-1:0] In;
output [Width-1:0] Count;
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Wires
//--------------------------------------------------------------------------
wire NoLimit;
wire RegEnable;
wire [Width-1:0] RegIn;
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Assigns
//--------------------------------------------------------------------------
assign NoLimit = !Limited;
assign RegEnable = Load | (Enable & (NoLimit | (Down ? |Count : ~&Count)));
assign RegIn = Load ? In : (Down ? (Count - 1) : (Count + 1));
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Register
//--------------------------------------------------------------------------
Register #( .Width( Width),
.Initial( Initial),
.AsyncReset( AsyncReset),
.AsyncSet( AsyncSet))
Register( .Clock( Clock),
.Reset( Reset),
.Set( Set),
.Enable( RegEnable),
.In( RegIn),
.Out( Count));
//--------------------------------------------------------------------------
endmodule
//------------------------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[1001]; int b[1001] = {0}; for (int i = 0; i < n; i++) { cin >> a[i]; b[a[i]] = 1; } sort(a, a + n); int ans = 0; int sum = a[n - 1] - a[0] + 1; cout << sum - n << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; long long dp[5005][5005]; long long solve(long long x, long long y) { if (x == 0 || y == 0) return 1; if (dp[x][y] == 0) dp[x][y] = (solve(x - 1, y - 1) * y + solve(x - 1, y)) % 998244353; return dp[x][y]; } int main() { long long n, m, k; while (scanf( %lld%lld%lld , &n, &m, &k) != EOF) { memset(dp, 0, sizeof(0)); printf( %lld n , (solve(n, m) * solve(m, k) % 998244353) * solve(k, n) % 998244353); } return 0; } |
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's WISHBONE BIU ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://opencores.org/project,or1k ////
//// ////
//// Description ////
//// Implements WISHBONE interface ////
//// ////
//// To Do: ////
//// - if biu_cyc/stb are deasserted and wb_ack_i is asserted ////
//// and this happens even before aborted_r is asssrted, ////
//// wb_ack_i will be delivered even though transfer is ////
//// internally considered already aborted. However most ////
//// wb_ack_i are externally registered and delayed. Normally ////
//// this shouldn't cause any problems. ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// $Log: or1200_iwb_biu.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// Major update:
// This module is obsolete.
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_iwb_biu();
// THIS MODULE IS OBSOLETE !!!
// COMPLETELY REWRITTEN or1200_wb_biu.v IS USED INSTEAD !!!
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Round-Robin Arbiter for R and B channel responses
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// arbiter_resp
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_9_arbiter_resp #
(
parameter C_FAMILY = "none",
parameter integer C_NUM_S = 4, // Number of requesting Slave ports = [2:16]
parameter integer C_NUM_S_LOG = 2, // Log2(C_NUM_S)
parameter integer C_GRANT_ENC = 0, // Enable encoded grant output
parameter integer C_GRANT_HOT = 1 // Enable 1-hot grant output
)
(
// Global Inputs
input wire ACLK,
input wire ARESET,
// Slave Ports
input wire [C_NUM_S-1:0] S_VALID, // Request from each slave
output wire [C_NUM_S-1:0] S_READY, // Grant response to each slave
// Master Ports
output wire [C_NUM_S_LOG-1:0] M_GRANT_ENC, // Granted slave index (encoded)
output wire [C_NUM_S-1:0] M_GRANT_HOT, // Granted slave index (1-hot)
output wire M_VALID, // Grant event
input wire M_READY
);
// Generates a binary coded from onehotone encoded
function [4:0] f_hot2enc
(
input [16:0] one_hot
);
begin
f_hot2enc[0] = |(one_hot & 17'b01010101010101010);
f_hot2enc[1] = |(one_hot & 17'b01100110011001100);
f_hot2enc[2] = |(one_hot & 17'b01111000011110000);
f_hot2enc[3] = |(one_hot & 17'b01111111100000000);
f_hot2enc[4] = |(one_hot & 17'b10000000000000000);
end
endfunction
(* use_clock_enable = "yes" *)
reg [C_NUM_S-1:0] chosen;
wire [C_NUM_S-1:0] grant_hot;
wire master_selected;
wire active_master;
wire need_arbitration;
wire m_valid_i;
wire [C_NUM_S-1:0] s_ready_i;
wire access_done;
reg [C_NUM_S-1:0] last_rr_hot;
wire [C_NUM_S-1:0] valid_rr;
reg [C_NUM_S-1:0] next_rr_hot;
reg [C_NUM_S*C_NUM_S-1:0] carry_rr;
reg [C_NUM_S*C_NUM_S-1:0] mask_rr;
integer i;
integer j;
integer n;
/////////////////////////////////////////////////////////////////////////////
//
// Implementation of the arbiter outputs independant of arbitration
//
/////////////////////////////////////////////////////////////////////////////
// Mask the current requests with the chosen master
assign grant_hot = chosen & S_VALID;
// See if we have a selected master
assign master_selected = |grant_hot[0+:C_NUM_S];
// See if we have current requests
assign active_master = |S_VALID;
// Access is completed
assign access_done = m_valid_i & M_READY;
// Need to handle if we drive S_ready combinatorial and without an IDLE state
// Drive S_READY on the master who has been chosen when we get a M_READY
assign s_ready_i = {C_NUM_S{M_READY}} & grant_hot[0+:C_NUM_S];
// Drive M_VALID if we have a selected master
assign m_valid_i = master_selected;
// If we have request and not a selected master, we need to arbitrate a new chosen
assign need_arbitration = (active_master & ~master_selected) | access_done;
// need internal signals of the output signals
assign M_VALID = m_valid_i;
assign S_READY = s_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Assign conditional onehot target output signal.
assign M_GRANT_HOT = (C_GRANT_HOT == 1) ? grant_hot[0+:C_NUM_S] : {C_NUM_S{1'b0}};
/////////////////////////////////////////////////////////////////////////////
// Assign conditional encoded target output signal.
assign M_GRANT_ENC = (C_GRANT_ENC == 1) ? f_hot2enc(grant_hot) : {C_NUM_S_LOG{1'b0}};
/////////////////////////////////////////////////////////////////////////////
// Select a new chosen when we need to arbitrate
// If we don't have a new chosen, keep the old one since it's a good chance
// that it will do another request
always @(posedge ACLK)
begin
if (ARESET) begin
chosen <= {C_NUM_S{1'b0}};
last_rr_hot <= {1'b1, {C_NUM_S-1{1'b0}}};
end else if (need_arbitration) begin
chosen <= next_rr_hot;
if (|next_rr_hot) last_rr_hot <= next_rr_hot;
end
end
assign valid_rr = S_VALID;
/////////////////////////////////////////////////////////////////////////////
// Round-robin arbiter
// Selects next request to grant from among inputs with PRIO = 0, if any.
/////////////////////////////////////////////////////////////////////////////
always @ * begin
next_rr_hot = 0;
for (i=0;i<C_NUM_S;i=i+1) begin
n = (i>0) ? (i-1) : (C_NUM_S-1);
carry_rr[i*C_NUM_S] = last_rr_hot[n];
mask_rr[i*C_NUM_S] = ~valid_rr[n];
for (j=1;j<C_NUM_S;j=j+1) begin
n = (i-j > 0) ? (i-j-1) : (C_NUM_S+i-j-1);
carry_rr[i*C_NUM_S+j] = carry_rr[i*C_NUM_S+j-1] | (last_rr_hot[n] & mask_rr[i*C_NUM_S+j-1]);
if (j < C_NUM_S-1) begin
mask_rr[i*C_NUM_S+j] = mask_rr[i*C_NUM_S+j-1] & ~valid_rr[n];
end
end
next_rr_hot[i] = valid_rr[i] & carry_rr[(i+1)*C_NUM_S-1];
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, m; cin >> n >> m; long long int a[n], k = 0, sum = 0; for (int x = 0; x < n; x++) { cin >> a[x]; } sort(a, a + n); for (int x = 0; x < m; x++) { if (a[x] < 0) { sum += a[x]; } } cout << -sum << endl; } |
// 8N1 UART Module, transmit only
module uart_tx_8n1 (
clk, // input clock
txbyte, // outgoing byte
senddata, // trigger tx
txdone, // outgoing byte sent
tx, // tx wire
);
/* Inputs */
input clk;
input[7:0] txbyte;
input senddata;
/* Outputs */
output txdone;
output tx;
/* Parameters */
parameter STATE_IDLE=8'd0;
parameter STATE_STARTTX=8'd1;
parameter STATE_TXING=8'd2;
parameter STATE_TXDONE=8'd3;
/* State variables */
reg[7:0] state=8'b0;
reg[7:0] buf_tx=8'b0;
reg[7:0] bits_sent=8'b0;
reg txbit=1'b1;
reg txdone=1'b0;
/* Wiring */
assign tx=txbit;
/* always */
always @ (posedge clk) begin
// start sending?
if (senddata == 1 && state == STATE_IDLE) begin
state <= STATE_STARTTX;
buf_tx <= txbyte;
txdone <= 1'b0;
end else if (state == STATE_IDLE) begin
// idle at high
txbit <= 1'b1;
txdone <= 1'b0;
end
// send start bit (low)
if (state == STATE_STARTTX) begin
txbit <= 1'b0;
state <= STATE_TXING;
end
// clock data out
if (state == STATE_TXING && bits_sent < 8'd8) begin
txbit <= buf_tx[0];
buf_tx <= buf_tx>>1;
bits_sent = bits_sent + 1;
end else if (state == STATE_TXING) begin
// send stop bit (high)
txbit <= 1'b1;
bits_sent <= 8'b0;
state <= STATE_TXDONE;
end
// tx done
if (state == STATE_TXDONE) begin
txdone <= 1'b1;
state <= STATE_IDLE;
end
end
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR3B_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__NOR3B_PP_SYMBOL_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__nor3b (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR3B_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1.0); const int maxn = 1e5 + 5; const int Inf = 1e9 + 7; int main() { int a, b; while (cin >> a >> b) { if (a == 0 && b == 0) { printf( NO n ); } else if (abs(a - b) <= 1) { printf( YES n ); } else { printf( NO n ); } } return 0; } |
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* SRL-based FIFO register (Tds ~ 100 ps)
*/
module srl_fifo_reg #
(
parameter WIDTH = 8
)
(
input wire clk,
input wire rst,
input wire write_en, // input valid
input wire [WIDTH-1:0] write_data,
input wire read_en, // output ready
output wire [WIDTH-1:0] read_data,
output wire full, // input not ready
output wire empty // output not valid
);
reg [WIDTH-1:0] data_reg[1:0];
reg valid_reg[1:0];
reg ptr_reg = 0;
reg full_reg = 0;
assign read_data = data_reg[ptr_reg];
assign full = full_reg;
assign empty = ~valid_reg[ptr_reg];
wire [WIDTH-1:0] data_reg_0 = data_reg[0];
wire [WIDTH-1:0] data_reg_1 = data_reg[1];
wire valid_reg_0 = valid_reg[0];
wire valid_reg_1 = valid_reg[1];
reg shift;
integer i;
initial begin
for (i = 0; i < 2; i = i + 1) begin
data_reg[i] <= 0;
valid_reg[i] <= 0;
end
end
always @(posedge clk) begin
if (rst) begin
ptr_reg <= 0;
end else begin
// transfer empty to full
full_reg <= ~read_en & ~empty;
// transfer in if not full
if (~full_reg) begin
data_reg[0] <= write_data;
valid_reg[0] <= write_en;
for (i = 0; i < 1; i = i + 1) begin
data_reg[i+1] <= data_reg[i];
valid_reg[i+1] <= valid_reg[i];
end
ptr_reg <= valid_reg[0];
end
if (read_en) begin
ptr_reg <= 0;
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKINVLP_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__CLKINVLP_FUNCTIONAL_V
/**
* clkinvlp: Lower power Clock tree inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__clkinvlp (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKINVLP_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; const long long MAX = 5005; vector<long long> arr(MAX); long long solve(long long l, long long r, long long cur) { if (l > r) return 0; long long mn = arr[l], idx = l; for (int i = l; i <= r; i++) { if (arr[i] < mn) { mn = arr[i]; idx = i; } } return min(r - l + 1, solve(l, idx - 1, mn) + solve(idx + 1, r, mn) + mn - cur); } int main() { ios_base::sync_with_stdio(0); int n; cin >> n; int ans = 0; for (int i = 0; i < n; i++) cin >> arr[i]; cout << solve(0, n - 1, 0) << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 1e9 + 7; const int maxn = 1e4 + 5; int n, b, q; int a[maxn], c[maxn]; inline int f(int x, int j) { return (x / 5) + (x % 5 >= j); } inline int calc(int j, int l, int r) { return f(r, j) - f(l - 1, j); } int main() { scanf( %d%d%d , &n, &b, &q); memset(a, -1, sizeof(a)); for (int i = (0); i < (q); ++i) { int x, k; scanf( %d%d , &x, &k); if (~a[x] && a[x] != k) { puts( unfair ); return 0; } a[x] = k; } if (~a[b] && a[b] != n) { puts( unfair ); return 0; } a[b] = n; a[0] = 0; for (int msk = (0); msk < (1 << 5); ++msk) { int x, g = 0, lst = 0; for (int i = (1); i <= (b); ++i) if (~a[i]) { int sub = 0, nin = 0; if (a[i] < a[lst]) { puts( unfair ); return 0; } for (int j = (0); j < (5); ++j) { if (msk >> j & 1) sub += calc(j, lst + 1, i); else nin += calc(j, lst + 1, i); } g += min(a[i] - a[lst], sub); if (a[i] - a[lst] > i - lst) { puts( unfair ); return 0; } lst = i; } x = __builtin_popcount(msk) * n / 5; if (x > g) { puts( unfair ); return 0; } } puts( fair ); return 0; } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_mask_rows_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_mask_rows_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_mask_rows_V_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_mask_rows_V_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> inline bool chkmin(T &x, T y) { return x > y ? x = y, 1 : 0; } template <typename T> inline bool chkmax(T &x, T y) { return x < y ? x = y, 1 : 0; } inline void read(int &x) { char ch = getchar(); int f = 1; x = 0; while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) x = x * 10 + ch - 0 , ch = getchar(); x *= f; } int n, m, p[100050], v[100050], nx[100050], pr[100050], id[100050]; set<pair<int, int> > se; int get(int x, int y) { if (x == y) return 1000000005; int d = (p[y] - p[x] + m) % m; if (x > y) d += v[y]; if (d <= v[x]) return 1; if (v[x] <= v[y]) return 1000000005; return (d - v[y] - 1) / (v[x] - v[y]) + 1; } bool cmp(int x, int y) { return p[x] < p[y]; } int main() { read(n), read(m); for (register int i = 1; i <= n; ++i) read(p[i]), --p[i], read(v[i]), id[i] = i; sort(id + 1, id + n + 1, cmp); for (register int i = 1; i <= n; ++i) pr[id[i]] = id[i - 1], nx[id[i]] = id[i + 1]; nx[pr[id[1]] = id[n]] = id[1]; for (register int i = 1; i <= n; ++i) se.insert(make_pair(get(i, nx[i]), i)); while (1) { set<pair<int, int> >::iterator it = se.begin(); if (it->first >= 1000000005) break; int u = it->second, t = it->first; se.erase(it); se.erase(make_pair(get(pr[u], u), pr[u])), se.erase(make_pair(get(nx[u], nx[nx[u]]), nx[u])); pr[nx[u] = nx[nx[u]]] = u; p[u] = (p[u] + t) % m, --v[u]; se.insert(make_pair(get(pr[u], u), pr[u])), se.insert(make_pair(get(u, nx[u]), u)); } printf( %d n , se.size()); for (auto v : se) printf( %d , v.second); puts( ); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long int k; cin >> k; if (k > 36) cout << -1; else { for (int i = 0; i < k / 2; i++) cout << 8; if (k % 2) cout << 4; } } |
`timescale 1 ns / 1 ps
// This component will be given the number of rows, and the size of each row
// (assume each row is the same size). With this information it will request
// all rows, and filter out the column of interest.
module filter_rows (
input clk,
input rst,
output done,
input [63:0] num_rows_in,
input [63:0] row_start_in,
input [63:0] row_skip_in,
input [63:0] rows_size_in, // size is passed in bytes
input [63:0] hash_mask_in,
output output_empty_out,
input output_read_en_in,
output [63:0] output_value_out,
output [63:0] output_hash_out,
input row_rq_stall_in,
output row_rq_vld_out,
output [47:0] row_rq_vadr_out,
output row_rs_stall_out,
input row_rs_vld_in,
input [63:0] row_rs_data_in
);
wire rows_done_s;
wire rows_output_empty_s;
wire [63:0] rows_output_value_s;
wire rows_read_en_s;
wire hash_done_s;
wire hash_afull_s;
stream_rows ROWS_0 (
.clk (clk),
.rst (rst),
.done (rows_done_s),
.num_rows_in (num_rows_in),
.rows_size_in (rows_size_in), // size is passed in bytes
.row_start_in (row_start_in),
.row_skip_in (row_skip_in),
.output_empty_out (rows_output_empty_s),
.output_read_en_in (rows_read_en_s),
.output_value_out (rows_output_value_s),
.row_rq_stall_in (row_rq_stall_in),
.row_rq_vld_out (row_rq_vld_out),
.row_rq_vadr_out (row_rq_vadr_out),
.row_rs_stall_out (row_rs_stall_out),
.row_rs_vld_in (row_rs_vld_in),
.row_rs_data_in (row_rs_data_in)
);
assign rows_read_en_s = !hash_afull_s && !rows_output_empty_s;
hash_phase HASH (
.clk (clk),
.rst (rst),
.done (hash_done_s),
.hash_mask_in (hash_mask_in),
.afull_out (hash_afull_s),
.write_en_in (rows_read_en_s),
.value_in (rows_output_value_s),
.empty_out (output_empty_out),
.read_en_in (output_read_en_in),
.value_out (output_value_out),
.hash_out (output_hash_out)
);
assign done = rows_done_s && hash_done_s;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 1; long long a[N]; int main() { ios_base::sync_with_stdio(0); int n; cin >> n; priority_queue<pair<long long, int>, vector<pair<long long, int>>, greater<pair<long long, int>>> q; for (int i = 1; i <= n; ++i) { int x; cin >> x; q.push({x, i}); } long long ans(0); while (!q.empty()) { pair<long long, int> p = q.top(); q.pop(); if (q.top().first == p.first && !q.empty()) { int x = q.top().second; q.pop(); q.push({p.first * 2, x}); } else { ans++; a[p.second] = p.first; } } cout << ans << endl; for (int i = 1; i <= n; ++i) if (a[i] != 0) cout << a[i] << ; cout << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; string s; cin >> s; int ans = 0; for (int i = 0; i < s.size(); i++) { if (((s[i] - 0 ) % 2) == 0) { ans = ans + i + 1; } } cout << ans; } |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PIO_EP.v
// Version : 1.11
//
// Description: Endpoint Programmed I/O module.
// Consists of Receive and Transmit modules and a Memory Aperture
//
//------------------------------------------------------------------------------
`timescale 1ps/1ps
module PIO_EP #(
parameter C_DATA_WIDTH = 64, // RX/TX interface data width
// Do not override parameters below this line
parameter KEEP_WIDTH = C_DATA_WIDTH / 8, // TSTRB width
parameter TCQ = 1
) (
input clk,
input rst_n,
// AXIS TX
input s_axis_tx_tready,
output [C_DATA_WIDTH-1:0] s_axis_tx_tdata,
output [KEEP_WIDTH-1:0] s_axis_tx_tkeep,
output s_axis_tx_tlast,
output s_axis_tx_tvalid,
output tx_src_dsc,
//AXIS RX
input [C_DATA_WIDTH-1:0] m_axis_rx_tdata,
input [KEEP_WIDTH-1:0] m_axis_rx_tkeep,
input m_axis_rx_tlast,
input m_axis_rx_tvalid,
output m_axis_rx_tready,
input [21:0] m_axis_rx_tuser,
output req_compl,
output compl_done,
input [15:0] cfg_completer_id
);
// Local wires
wire [10:0] rd_addr;
wire [3:0] rd_be;
wire [31:0] rd_data;
wire [10:0] wr_addr;
wire [7:0] wr_be;
wire [31:0] wr_data;
wire wr_en;
wire wr_busy;
wire req_compl_int;
wire req_compl_wd;
wire compl_done_int;
wire [2:0] req_tc;
wire req_td;
wire req_ep;
wire [1:0] req_attr;
wire [9:0] req_len;
wire [15:0] req_rid;
wire [7:0] req_tag;
wire [7:0] req_be;
wire [12:0] req_addr;
//
// ENDPOINT MEMORY : 8KB memory aperture implemented in FPGA BlockRAM(*)
//
PIO_EP_MEM_ACCESS #(
.TCQ( TCQ )
) EP_MEM_inst (
.clk(clk), // I
.rst_n(rst_n), // I
// Read Port
.rd_addr(rd_addr), // I [10:0]
.rd_be(rd_be), // I [3:0]
.rd_data(rd_data), // O [31:0]
// Write Port
.wr_addr(wr_addr), // I [10:0]
.wr_be(wr_be), // I [7:0]
.wr_data(wr_data), // I [31:0]
.wr_en(wr_en), // I
.wr_busy(wr_busy) // O
);
//
// Local-Link Receive Controller
//
PIO_RX_ENGINE #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH ),
.TCQ( TCQ )
) EP_RX_inst (
.clk(clk), // I
.rst_n(rst_n), // I
// AXIS RX
.m_axis_rx_tdata( m_axis_rx_tdata ), // I
.m_axis_rx_tkeep( m_axis_rx_tkeep ), // I
.m_axis_rx_tlast( m_axis_rx_tlast ), // I
.m_axis_rx_tvalid( m_axis_rx_tvalid ), // I
.m_axis_rx_tready( m_axis_rx_tready ), // O
.m_axis_rx_tuser ( m_axis_rx_tuser ), // I
// Handshake with Tx engine
.req_compl(req_compl_int), // O
.req_compl_wd(req_compl_wd), // O
.compl_done(compl_done_int), // I
.req_tc(req_tc), // O [2:0]
.req_td(req_td), // O
.req_ep(req_ep), // O
.req_attr(req_attr), // O [1:0]
.req_len(req_len), // O [9:0]
.req_rid(req_rid), // O [15:0]
.req_tag(req_tag), // O [7:0]
.req_be(req_be), // O [7:0]
.req_addr(req_addr), // O [12:0]
// Memory Write Port
.wr_addr(wr_addr), // O [10:0]
.wr_be(wr_be), // O [7:0]
.wr_data(wr_data), // O [31:0]
.wr_en(wr_en), // O
.wr_busy(wr_busy) // I
);
//
// Local-Link Transmit Controller
//
PIO_TX_ENGINE #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH ),
.TCQ( TCQ )
)EP_TX_inst(
.clk(clk), // I
.rst_n(rst_n), // I
// AXIS Tx
.s_axis_tx_tready( s_axis_tx_tready ), // I
.s_axis_tx_tdata( s_axis_tx_tdata ), // O
.s_axis_tx_tkeep( s_axis_tx_tkeep ), // O
.s_axis_tx_tlast( s_axis_tx_tlast ), // O
.s_axis_tx_tvalid( s_axis_tx_tvalid ), // O
.tx_src_dsc( tx_src_dsc ), // O
// Handshake with Rx engine
.req_compl(req_compl_int), // I
.req_compl_wd(req_compl_wd), // I
.compl_done(compl_done_int), // 0
.req_tc(req_tc), // I [2:0]
.req_td(req_td), // I
.req_ep(req_ep), // I
.req_attr(req_attr), // I [1:0]
.req_len(req_len), // I [9:0]
.req_rid(req_rid), // I [15:0]
.req_tag(req_tag), // I [7:0]
.req_be(req_be), // I [7:0]
.req_addr(req_addr), // I [12:0]
// Read Port
.rd_addr(rd_addr), // O [10:0]
.rd_be(rd_be), // O [3:0]
.rd_data(rd_data), // I [31:0]
.completer_id(cfg_completer_id) // I [15:0]
);
assign req_compl = req_compl_int;
assign compl_done = compl_done_int;
endmodule // PIO_EP
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR4BB_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__OR4BB_FUNCTIONAL_PP_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__or4bb (
X ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , D_N, C_N );
or or0 (or0_out_X , B, A, nand0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR4BB_FUNCTIONAL_PP_V |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_clk_gclk_inv_192x.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// --------------------------------------------------
// File: bw_clk_gclk_inv_192x.behV
// --------------------------------------------------
//
module bw_clk_gclk_inv_192x (
clkout,
clkin );
output clkout;
input clkin;
assign clkout = ~( clkin );
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 1; int mark[N], t[N], n; long long res; int main() { ios::sync_with_stdio(0); cin.tie(0); ; cin >> n; for (int i = (1); i <= (n); i += (1)) cin >> mark[i]; int cur = 0; for (int i = (n); i >= (1); i -= (1)) { cur = max(0, cur - 1); cur = max(cur, mark[i] + 1); t[i] = cur; } cur = 0; for (int i = (1); i <= (n); i += (1)) { cur = max(cur, t[i]); res += cur; } for (int i = (1); i <= (n); i += (1)) res -= (mark[i] + 1); cout << res << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; long long int power(long long int a, long long int b) { long long int ans = 1; while (b) { if (b & 1) { ans = ((ans % 1000000007) * (a % 1000000007)) % 1000000007; } a = ((a % 1000000007) * (a % 1000000007)) % 1000000007; b = b >> 1; } return ans; } long long int powe(long long int a, long long int b) { long long int ans = 1; while (b) { if (b & 1) { ans = a * ans; } a = a * a; b = b >> 1; } return ans; } void solve() { string s; cin >> s; vector<pair<char, long long int> > v; for (int i = 0; i < s.length(); i++) { long long int curlen = 1; while (i < s.length() - 1 && s[i + 1] == s[i]) { curlen++; i++; } v.push_back({s[i], curlen}); } if (v.size() % 2 == 0) { cout << 0 << endl; } else { int i = 0; for (i = 0; i < v.size() / 2; i++) { if (v[i].first == v[v.size() - 1 - i].first && v[i].second + v[v.size() - 1 - i].second >= 3) { } else { cout << 0 << endl; return; } } if (v[v.size() / 2].second >= 2) cout << v[v.size() / 2].second + 1 << endl; else cout << 0 << endl; return; } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; long long int t = 1; while (t > 0) { solve(); t--; } } |
// FSM top module, for text only
// FSM controlled by button purely
// test about text displaying
module game_text_top
(
input wire clk, reset,
input wire [1:0] btn,
// we use the button now to control the FSM
output wire hsync, vsync,
output wire [2:0] rgb
);
// symbolic state declaration
// you may use one-hot if you wish
localparam [1:0]
newgame = 2'b00,
// display the registration information
play = 2'b01,
newball = 2'b10,
over = 2'b11;
// display the game over information
// score and logo are displayed in all these stages
// signal declaration
reg [1:0] state_reg, state_next;
wire [9:0] pixel_x, pixel_y;
wire video_on, pixel_tick;
// pixel_tick is the same as refr_tick
wire [3:0] text_on;
wire [2:0] text_rgb;
reg [2:0] rgb_reg, rgb_next;
wire [3:0] dig0, dig1;
// without actual meaning
reg [1:0] ball_reg, ball_next;
// ball's number
// I have to use ball's number to change the state machine
// as usual
assign dig0 = 4'b0000;
assign dig1 = 4'b0000;
// I assume I don't worry about the actual score for now
// instantiate video synchronization unit
vga_sync vsync_unit
(.clk(clk), .reset(reset), .hsync(hsync), .vsync(vsync),
.video_on(video_on), .p_tick(pixel_tick),
.pixel_x(pixel_x), .pixel_y(pixel_y));
// instantiate text module
game_text game_text_unit
(.clk(clk),
.pix_x(pixel_x), .pix_y(pixel_y),
.dig0(dig0), .dig1(dig1), .ball(ball_reg),
.text_on(text_on), .text_rgb(text_rgb));
//=======================================================
// FSMD
//=======================================================
// FSMD state & data registers
always @(posedge clk, posedge reset)
if (reset)
begin
state_reg <= newgame;
ball_reg <= 0;
rgb_reg <= 0;
end
else
begin
state_reg <= state_next;
ball_reg <= ball_next;
if (pixel_tick)
rgb_reg <= rgb_next;
end
// FSMD next-state logic
always @*
begin
state_next = state_reg;
ball_next = ball_reg;
// the above two lines
case (state_reg)
newgame:
begin
ball_next = 2'b11; // three balls
if (btn != 2'b00) // button pressed
begin
state_next = play;
ball_next = ball_reg - 1;
end
end
play:
begin
if (btn == 2'b11)
begin
state_next = newball;
ball_next = ball_reg - 2;
end
end
newball:
if ((btn == 2'b00))
begin
state_next = over;
ball_next = 2'b00;
end
over:
state_next = newgame;
endcase
end
//=======================================================
// rgb multiplexing circuit
// without graph, text only
//=======================================================
always @*
if (~video_on)
rgb_next = "000"; // blank the edge/retrace
else
// display score, rule, or game over
if (text_on[3] ||
((state_reg==newgame) && text_on[1]) || // rule
((state_reg==over) && text_on[0]))
rgb_next = text_rgb;
else if (text_on[2]) // display logo
rgb_next = text_rgb;
else
rgb_next = 3'b110; // yellow background
// output
assign rgb = rgb_reg;
// designate to the output pin (buffer, reason as before)
// CPP should be familiar with this trend by now
endmodule
|
//+FHDR------------------------------------------------------------------------
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
//GLADIC Open Source RTL
//-----------------------------------------------------------------------------
//FILE NAME :
//DEPARTMENT : IC Design / Verification
//AUTHOR : Felipe Fernandes da Costa
//AUTHOR’S EMAIL :
//-----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPTION
//1.0 YYYY-MM-DD name
//-----------------------------------------------------------------------------
//KEYWORDS : General file searching keywords, leave blank if none.
//-----------------------------------------------------------------------------
//PURPOSE : ECSS_E_ST_50_12C_31_july_2008
//-----------------------------------------------------------------------------
//PARAMETERS
//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
//e.g.DATA_WIDTH [32,16] : width of the data : 32:
//-----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy :
//Clock Domains :
//Critical Timing :
//Test Features :
//Asynchronous I/F :
//Scan Methodology :
//Instantiations :
//Synthesizable (y/n) :
//Other :
//-FHDR------------------------------------------------------------------------
`timescale 1ns/1ns
module top_spw_ultra_light(
input pclk,
input ppllclk,
input resetn,
input top_sin,
input top_din,
input top_auto_start,
input top_link_start,
input top_link_disable,
input top_tx_write,
input [8:0] top_tx_data,
input top_tx_tick,
input [7:0] top_tx_time,
input credit_error_rx,
input top_send_fct_now,
output [8:0] datarx_flag,
output buffer_write,
output [7:0] time_out,
output tick_out,
output top_dout,
output top_sout,
output top_tx_ready,
output top_tx_ready_tick,
output [5:0] top_fsm
);
wire resetn_rx;
wire error_rx;
wire got_bit_rx;
wire got_null_rx;
wire got_nchar_rx;
wire got_time_code_rx;
wire got_fct_rx;
wire enable_tx;
wire send_null_tx;
wire send_fct_tx;
wire got_fct_flag_fsm;
FSM_SPW FSM(
.pclk(pclk),
.resetn(resetn),
.auto_start(top_auto_start),
.link_start(top_link_start),
.link_disable(top_link_disable),
.rx_error(error_rx),
.rx_credit_error(credit_error_rx),
.rx_got_bit(got_bit_rx),
.rx_got_null(got_null_rx),
.rx_got_nchar(got_nchar_rx),
.rx_got_time_code(got_time_code_rx),
.rx_got_fct(got_fct_flag_fsm),
.rx_resetn(resetn_rx),
.enable_tx(enable_tx),
.send_null_tx(send_null_tx),
.send_fct_tx(send_fct_tx),
.fsm_state(top_fsm)
);
RX_SPW RX(
.rx_din(top_din),
.rx_sin(top_sin),
.rx_resetn(resetn_rx),
.rx_error(error_rx),
.rx_got_bit(got_bit_rx),
.rx_got_null(got_null_rx),
.rx_got_nchar(got_nchar_rx),
.rx_got_time_code(got_time_code_rx),
.rx_got_fct(got_fct_rx),
.rx_got_fct_fsm(got_fct_flag_fsm),
.rx_data_flag(datarx_flag),
.rx_buffer_write(buffer_write),
.rx_time_out(time_out),
.rx_tick_out(tick_out)
);
TX_SPW TX(
.pclk_tx(ppllclk),
.data_tx_i(top_tx_data),
.txwrite_tx(top_tx_write),
.timecode_tx_i(top_tx_time),
.tickin_tx(top_tx_tick),
.enable_tx(enable_tx),
.send_null_tx(send_null_tx),
.send_fct_tx(send_fct_tx),
.gotfct_tx(got_fct_rx),
.send_fct_now(top_send_fct_now),
.tx_dout_e(top_dout),
.tx_sout_e(top_sout),
.ready_tx_data(top_tx_ready),
.ready_tx_timecode(top_tx_ready_tick)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int i, j, k, a, b, c, n, t, f, d; string s, v; map<char, int> ma, sa; vector<int> vv; map<char, int>::iterator it, ki; cin >> s; f = 0; c = 0; for (j = 0; j < s.size(); j++) { if ((s[j] >= A && s[j] <= Z )) { c++; } } if (c == s.size()) { for (j = 0; j < s.size(); j++) { cout << char(s[j] + 32); } cout << endl; } else if (s[0] >= a && s[0] <= z && c == s.size() - 1) { cout << char(s[0] - 32); for (j = 1; j < s.size(); j++) { cout << char(s[j] + 32); } cout << endl; } else { cout << s << endl; } return 0; } |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:268435456 ) using namespace std; const string IN_NAME = input.txt ; const string OUT_NAME = output.txt ; template <class T> T abs(T &x) { return ((x) >= 0) ? (x) : (-(x)); } template <class T> T sqr(T &x) { return (x) * (x); } template <class T> T min(T &a, T &b) { return ((a) < (b)) ? (a) : (b); } template <class T> T max(T &a, T &b) { return ((a) > (b)) ? (a) : (b); } int n, m; struct tree { int x, h, pL, pR; tree() {} bool operator<(const tree &t) const { return x < t.x; } }; struct mush { int x, z; mush() {} bool operator<(const mush &t) const { return x < t.x; } }; tree a[100010]; mush b[100010], tmpb[100010]; int binSearch(int x) { if (x < b[0].x) return -1; if (x > b[m - 1].x) return -m - 1; int left = 0, right = m - 1; while (right - left > 1) { int mid = (left + right) >> 1; if (b[mid].x == x) return mid; if (b[mid].x < x) left = mid + 1; else right = mid - 1; } for (int i = max(0, left - 4); i < min(m - 1, right + 3); i++) { if (b[i].x < x && x < b[i + 1].x) return -(i + 1) - 1; } return right; } double d[100010]; double db[100010]; int dk; void multQuery(int left, int right, double p) { if (left > right) return; int L = left / dk + 1; int R = right / dk - 1; if (L > R) { for (int i = left; i <= right; i++) d[i] *= p; } else { for (int i = left; i < L * dk; i++) d[i] *= p; for (int j = L; j <= R; j++) db[j] *= p; for (int i = (R + 1) * dk; i <= right; i++) d[i] *= p; } } double getQuery(int index) { return d[index] * db[index / dk]; } int main() { scanf( %d%d , &n, &m); for (int i = 0; i < n; i++) scanf( %d%d%d%d , &a[i].x, &a[i].h, &a[i].pL, &a[i].pR); for (int i = 0; i < m; i++) scanf( %d%d , &tmpb[i].x, &tmpb[i].z); sort(a, a + n); sort(tmpb, tmpb + m); int newM = 0; for (int i = 0; i < m; i++) { if (i == 0 || tmpb[i - 1].x < tmpb[i].x) { b[newM].x = tmpb[i].x; b[newM].z = tmpb[i].z; newM++; } else { b[newM - 1].z += tmpb[i].z; } } m = newM; for (int i = 0; i < n; i++) a[i].x *= 2; for (int i = 0; i < n; i++) a[i].h *= 2; for (int i = 0; i < m; i++) b[i].x *= 2; dk = (int)sqrt(m + 1e-9); for (int i = 0; i < m + 5; i++) { d[i] = db[i] = 1; } for (int i = 0; i < n; i++) { int leftIndex = binSearch(a[i].x - a[i].h - 1); int rightIndex = binSearch(a[i].x + a[i].h + 1); int thisLeftIndex = binSearch(a[i].x - 1); int thisRightIndex = binSearch(a[i].x + 1); leftIndex = ~leftIndex; rightIndex = ~rightIndex; thisLeftIndex = ~thisLeftIndex; thisRightIndex = ~thisRightIndex; multQuery(leftIndex, thisLeftIndex - 1, 1.0 - a[i].pL / 100.0); multQuery(thisRightIndex, rightIndex - 1, 1.0 - a[i].pR / 100.0); } double result = 0; for (int i = 0; i < m; i++) { result += getQuery(i) * b[i].z; } printf( %.12f , result); } |
#include <bits/stdc++.h> using namespace std; int main() { string str; cin >> str; if (str[0] > 96) { str[0] -= 32; } cout << str << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int inf = INT_MAX, df = 8e5 + 7; int i, j, k = 1, l, m, n, o, p, q, r, s, t, u, v, w, x, y, z, le[df], rig[df], c[df][26], ma[df << 1], head[df], pos[df << 1], tot, ans[df], fail[df], cnt, yet[df][26]; struct node { int sum, id; }; vector<node> vec[df]; struct edge { int to, nxt; } e[df << 1]; void add(int u, int v) { e[++o] = (edge){v, head[u]}, head[u] = o; return; } char ch[df], st[df]; void upd(int x, int y) { if (!x) return; for (int i = x; i <= 800000; i += (i & -i)) ma[i] += y; return; } int qry(int x) { int as = 0; for (int i = x; i; i -= (i & -i)) as += ma[i]; return as; } void insert1(int now, int v, int id) { if (!c[now][v]) c[now][v] = ++tot; pos[id] = c[now][v]; return; } void insert2(char *s, int id) { int len = strlen(s), now = 0; for (int i = (0); i <= (len - 1); ++i) { int v = s[i] - a ; if (!c[now][v]) c[now][v] = ++tot; now = c[now][v]; } pos[id + n] = now; return; } void init() { scanf( %d , &n); for (int i = (1); i <= (n); ++i) { int op, x; scanf( %d , &op); if (op == 1) { scanf( %s , ch), insert1(0, ch[0] - a , i); } if (op == 2) { scanf( %d , &x); scanf( %s , ch); insert1(pos[x], ch[0] - a , i); } } scanf( %d , &t); for (int i = (1); i <= (t); ++i) { int x; scanf( %d , &x), scanf( %s , st); insert2(st, i); vec[pos[x]].push_back((node){pos[i + n], i}); } return; } void build() { queue<int> que; for (int i = (0); i <= (25); ++i) if (c[0][i]) fail[c[0][i]] = 0, que.push(c[0][i]), yet[0][i] = 1; while (!que.empty()) { int u = que.front(); que.pop(); for (int i = (0); i <= (25); ++i) { if (c[u][i]) fail[c[u][i]] = c[fail[u]][i], yet[u][i] = 1, que.push(c[u][i]); else c[u][i] = c[fail[u]][i]; } } return; } void dfs1(int u) { le[u] = ++cnt; for (int i = head[u]; i; i = e[i].nxt) dfs1(e[i].to); rig[u] = cnt; return; } void dfs2(int u) { upd(le[u], 1); int siz = vec[u].size() - 1; for (int i = (0); i <= (siz); ++i) { int l = le[vec[u][i].sum], r = rig[vec[u][i].sum]; ans[vec[u][i].id] = qry(r) - qry(l - 1); } for (int i = (0); i <= (25); ++i) if (yet[u][i]) dfs2(c[u][i]); upd(le[u], -1); return; } int main() { init(); build(); for (int i = (1); i <= (tot); ++i) add(fail[i], i); dfs1(0); dfs2(0); for (int i = (1); i <= (t); ++i) printf( %d n , ans[i]); return 0; } |
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module hps_design_pio_0 (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg data_out;
wire out_port;
wire read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {1 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata;
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__EBUFN_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__EBUFN_BEHAVIORAL_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__ebufn (
Z ,
A ,
TE_B
);
// Module ports
output Z ;
input A ;
input TE_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
bufif0 bufif00 (Z , A, TE_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__EBUFN_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A21OI_TB_V
`define SKY130_FD_SC_HVL__A21OI_TB_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__a21oi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 B1 = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 B1 = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 B1 = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 B1 = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_hvl__a21oi dut (.A1(A1), .A2(A2), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A21OI_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYMETAL6S4S_1_V
`define SKY130_FD_SC_HS__DLYMETAL6S4S_1_V
/**
* dlymetal6s4s: 6-inverter delay with output from 4th inverter on
* horizontal route.
*
* Verilog wrapper for dlymetal6s4s with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dlymetal6s4s.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlymetal6s4s_1 (
X ,
A ,
VPWR,
VGND
);
output X ;
input A ;
input VPWR;
input VGND;
sky130_fd_sc_hs__dlymetal6s4s base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlymetal6s4s_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__dlymetal6s4s base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYMETAL6S4S_1_V
|
//****************************************************************************************************
//*---------------Copyright (c) 2016 C-L-G.FPGA1988.lichangbeiju. All rights reserved-----------------
//
// -- It to be define --
// -- ... --
// -- ... --
// -- ... --
//****************************************************************************************************
//File Information
//****************************************************************************************************
//File Name : bus_arbiter.v
//Project Name : azpr_soc
//Description : the bus arbiter.
//Github Address : github.com/C-L-G/azpr_soc/trunk/ic/digital/rtl/bus_arbiter.v
//License : CPL
//****************************************************************************************************
//Version Information
//****************************************************************************************************
//Create Date : 01-07-2016 17:00(1th Fri,July,2016)
//First Author : lichangbeiju
//Modify Date : 02-09-2016 14:20(1th Sun,July,2016)
//Last Author : lichangbeiju
//Version Number : 002
//Last Commit : 03-09-2016 14:30(1th Sun,July,2016)
//****************************************************************************************************
//Change History(latest change first)
//yyyy.mm.dd - Author - Your log of change
//****************************************************************************************************
//2016.12.08 - lichangbeiju - Change the include.
//2016.11.22 - lichangbeiju - Add the instance and io port.
//****************************************************************************************************
`include "../sys_include.h"
`include "bus.h"
module bus(
input wire clk ,//01 the system clock
input wire reset ,//01
//master 0
input wire m0_req_n ,//01
output wire m0_grant_n ,//01
input wire [`WordAddrBus] m0_addr ,//30 address
input wire m0_as_n ,//01
input wire m0_rw ,//01
input wire [`WordDataBus] m0_wr_data ,//32 write data
//master 1
input wire m1_req_n ,//01
output wire m1_grant_n ,//01
input wire [`WordAddrBus] m1_addr ,//30 address
input wire m1_as_n ,//01
input wire m1_rw ,//01
input wire [`WordDataBus] m1_wr_data ,//32 write data
//master 2
input wire m2_req_n ,//01
output wire m2_grant_n ,//01
input wire [`WordAddrBus] m2_addr ,//30 address
input wire m2_as_n ,//01
input wire m2_rw ,//01
input wire [`WordDataBus] m2_wr_data ,//32 write data
//master 3
input wire m3_req_n ,//01
output wire m3_grant_n ,//01
input wire [`WordAddrBus] m3_addr ,//30 address
input wire m3_as_n ,//01
input wire m3_rw ,//01
input wire [`WordDataBus] m3_wr_data ,//32 write data
//share
output wire [`WordAddrBus] s_addr ,//30 address
output wire s_as_n ,//01
output wire s_rw ,//01
output wire [`WordDataBus] s_wr_data ,//3
//slave 0
output wire s0_cs_n ,//01 chip select
input wire [`WordDataBus] s0_rd_data ,//32 write data
input wire s0_rdy_n ,//01
//slave 1
output wire s1_cs_n ,//01 chip select
input wire [`WordDataBus] s1_rd_data ,//32 write data
input wire s1_rdy_n ,//01
//slave 2
output wire s2_cs_n ,//01 chip select
input wire [`WordDataBus] s2_rd_data ,//32 write data
input wire s2_rdy_n ,//01
//slave 3
output wire s3_cs_n ,//01 chip select
input wire [`WordDataBus] s3_rd_data ,//32 write data
input wire s3_rdy_n ,//01
//slave 4
output wire s4_cs_n ,//01 chip select
input wire [`WordDataBus] s4_rd_data ,//32 write data
input wire s4_rdy_n ,//01
//slave 5
output wire s5_cs_n ,//01 chip select
input wire [`WordDataBus] s5_rd_data ,//32 write data
input wire s5_rdy_n ,//01
//slave 6
output wire s6_cs_n ,//01 chip select
input wire [`WordDataBus] s6_rd_data ,//32 write data
input wire s6_rdy_n ,//01
//slave 7
output wire s7_cs_n ,//01 chip select
input wire [`WordDataBus] s7_rd_data ,//32 write data
input wire s7_rdy_n ,//01
//share
output wire [`WordDataBus] m_rd_data ,//32
output wire m_rdy_n //01 Read
);
//************************************************************************************************
// 1.Parameter and constant define
//************************************************************************************************
//************************************************************************************************
// 2.Register and wire declaration
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 2.1 the output reg
//------------------------------------------------------------------------------------------------
// 2.2 the internal reg
//------------------------------------------------------------------------------------------------
//------------------------------------------------------------------------------------------------
// 2.x the test logic
//------------------------------------------------------------------------------------------------
//************************************************************************************************
// 3.Main code
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 3.1 the master grant logic
//------------------------------------------------------------------------------------------------
//------------------------------------------------------------------------------------------------
// 3.1 the master owner control logic
//------------------------------------------------------------------------------------------------
//------------------------------------------------------------------------------------------------
// 3.x the Test Logic
//------------------------------------------------------------------------------------------------
//************************************************************************************************
// 5.Sub module instantiation
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 5.1 the clk generate module
//------------------------------------------------------------------------------------------------
bus_arbiter bus_arbiter(
.clk (clk ),//01 In
.reset (reset ),//01 In
.m0_req_n (m0_req_n ),//01 In
.m0_grant_n (m0_grant_n ),//01 Out
.m1_req_n (m1_req_n ),//01 In
.m1_grant_n (m1_grant_n ),//01 Out
.m2_req_n (m2_req_n ),//01 In
.m2_grant_n (m2_grant_n ),//01 Out
.m3_req_n (m3_req_n ),//01 In
.m3_grant_n (m3_grant_n ) //01 Out
);
//------------------------------------------------------------------------------------------------
// 5.2 the system auxiliary module
//------------------------------------------------------------------------------------------------
bus_master_mux bus_master_mux(
.m0_addr (m0_addr ),//30 address
.m0_as_n (m0_as_n ),//01
.m0_rw (m0_rw ),//01
.m0_wr_data (m0_wr_data ),//32 write data
.m0_grant_n (m0_grant_n ),//01
.m1_addr (m1_addr ),//30 address
.m1_as_n (m1_as_n ),//01
.m1_rw (m1_rw ),//01
.m1_wr_data (m1_wr_data ),//32 write data
.m1_grant_n (m1_grant_n ),//01
.m2_addr (m2_addr ),//30 address
.m2_as_n (m2_as_n ),//01
.m2_rw (m2_rw ),//01
.m2_wr_data (m2_wr_data ),//32 write data
.m2_grant_n (m2_grant_n ),//01
.m3_addr (m3_addr ),//30 address
.m3_as_n (m3_as_n ),//01
.m3_rw (m3_rw ),//01
.m3_wr_data (m3_wr_data ),//32 write data
.m3_grant_n (m3_grant_n ),//01
.s_addr (s_addr ),//30
.s_as_n (s_as_n ),//01
.s_rw (s_rw ),//01
.s_wr_data (s_wr_data ) //3
);
//------------------------------------------------------------------------------------------------
// 4.3 the address dec
//------------------------------------------------------------------------------------------------
bus_addr_dec bus_addr_dec(
.s_addr (s_addr ),//30 address
.s0_cs_n (s0_cs_n ),//01 slave 0 chip select
.s1_cs_n (s1_cs_n ),//01 slave 1 chip select
.s2_cs_n (s2_cs_n ),//01 slave 2 chip select
.s3_cs_n (s3_cs_n ),//01 slave 3 chip select
.s4_cs_n (s4_cs_n ),//01 slave 4 chip select
.s5_cs_n (s5_cs_n ),//01 slave 5 chip select
.s6_cs_n (s6_cs_n ),//01 slave 6 chip select
.s7_cs_n (s7_cs_n ) //01 slave 7 chip selec
);
//------------------------------------------------------------------------------------------------
// 4.4 the udp/ip stack module
//------------------------------------------------------------------------------------------------
bus_slave_mux bus_slave_mux(
.s0_cs_n (s0_cs_n ),//01 chip select
.s0_rd_data (s0_rd_data ),//32 write data
.s0_rdy_n (s0_rdy_n ),//01
.s1_cs_n (s1_cs_n ),//01 chip select
.s1_rd_data (s1_rd_data ),//32 write data
.s1_rdy_n (s1_rdy_n ),//01
.s2_cs_n (s2_cs_n ),//01 chip select
.s2_rd_data (s2_rd_data ),//32 write data
.s2_rdy_n (s2_rdy_n ),//01
.s3_cs_n (s3_cs_n ),//01 chip select
.s3_rd_data (s3_rd_data ),//32 write data
.s3_rdy_n (s3_rdy_n ),//01
.s4_cs_n (s4_cs_n ),//01 chip select
.s4_rd_data (s4_rd_data ),//32 write data
.s4_rdy_n (s4_rdy_n ),//01
.s5_cs_n (s5_cs_n ),//01 chip select
.s5_rd_data (s5_rd_data ),//32 write data
.s5_rdy_n (s5_rdy_n ),//01
.s6_cs_n (s6_cs_n ),//01 chip select
.s6_rd_data (s6_rd_data ),//32 write data
.s6_rdy_n (s6_rdy_n ),//01
.s7_cs_n (s7_cs_n ),//01 chip select
.s7_rd_data (s7_rd_data ),//32 write data
.s7_rdy_n (s7_rdy_n ),//01
.m_rd_data (m_rd_data ),//32
.m_rdy_n (m_rdy_n ) //01 Read
);
endmodule
//****************************************************************************************************
//End of Module
//****************************************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2111AI_TB_V
`define SKY130_FD_SC_LS__O2111AI_TB_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o2111ai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg C1;
reg D1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
D1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 C1 = 1'b0;
#100 D1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 B1 = 1'b1;
#260 C1 = 1'b1;
#280 D1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 B1 = 1'b0;
#440 C1 = 1'b0;
#460 D1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 D1 = 1'b1;
#660 C1 = 1'b1;
#680 B1 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 D1 = 1'bx;
#840 C1 = 1'bx;
#860 B1 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_ls__o2111ai dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .D1(D1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2111AI_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFXTP_2_V
`define SKY130_FD_SC_LS__SDFXTP_2_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog wrapper for sdfxtp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__sdfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sdfxtp_2 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sdfxtp_2 (
Q ,
CLK,
D ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFXTP_2_V
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; int n; int fa[1000005], huan[1000005], zihuan[1000005], siz[1000005]; int find(int now) { return fa[now] == now ? now : fa[now] = find(fa[now]); } int main() { scanf( %d , &n); for (int i = 1; i <= 2 * n; i++) { fa[i] = i; siz[i] = 1; } for (int i = 1; i <= n; i++) { int x, y; scanf( %d%d , &x, &y); int x1 = find(x), y1 = find(y); if (x == y) zihuan[x1] = 1; if (x1 == y1) huan[y1] = 1; fa[x1] = y1; } for (int i = 1; i <= 2 * n; i++) { int x = find(i); if (x != i) { siz[x] += siz[i]; huan[x] |= huan[i]; zihuan[x] |= zihuan[i]; } } long long ans = 1; for (int i = 1; i <= 2 * n; i++) { if (find(i) == i) { if (zihuan[i]) continue; else if (huan[i]) ans = (ans * 2) % mod; else ans = (ans * siz[i]) % mod; } } printf( %I64d n , ans); } |
#include <bits/stdc++.h> using namespace std; int Rand(int x) { return rand() * rand() % x + 1; } const int INF = 0x3f3f3f3f, N = 5000005, M = 2000005, MOD = 1e9 + 7; long long qpow(long long a, long long b) { long long ret = 1; for (; b; b >>= 1, a = a * a % MOD) if (b & 1) ret = ret * a % MOD; return ret; } long long val[N]; map<int, int> g[N]; map<long long, int> has; int find(int id, int x) { if (x == g[id][x]) return x; return g[id][x] = find(id, g[id][x]); } void Union(int id, int x, int y) { int fx = find(id, x), fy = find(id, y); if (fx == fy) return; g[id][fy] = fx; } int cnt[N], ss; int main() { ios::sync_with_stdio(false); cin.tie(0), cout.tie(0); int n, m, c; cin >> n >> m >> c; for (int i = 1; i <= n; i++) cin >> val[i]; long long ans = qpow(2, c) * qpow(2, n) % MOD; for (int i = 1; i <= m; i++) { int u, v; cin >> u >> v; long long x = val[u] ^ val[v]; if (!has.count(x)) has[x] = ++ss, cnt[ss] = n; x = has[x]; if (!g[x][u]) g[x][u] = u; if (!g[x][v]) g[x][v] = v; if (find(x, u) == find(x, v)) continue; Union(x, u, v); ans = (ans - qpow(2, cnt[x]) + MOD) % MOD; cnt[x]--; ans = (ans + qpow(2, cnt[x]) + MOD) % MOD; } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long MAXN = 2e6; long long cnt[MAXN]; signed main() { long long n, m, k; ios_base::sync_with_stdio(false); cin >> n >> m >> k; vector<long long> f(n); vector<pair<long long, long long> > s(m); for (long long i = 0; i < n; i++) cin >> f[i]; for (long long i = 0; i < m; i++) cin >> s[i].first; for (long long i = 0; i < m; i++) s[i].second = i; sort(s.begin(), s.end()); reverse(s.begin(), s.end()); fill(cnt, cnt + MAXN, 0); for (auto ff : f) { if (ff < MAXN) { cnt[ff]++; } } long long taken = 0; bool flag = true; for (long long i = 0; flag && i < (n + k - 1) / k; i++) { taken += cnt[i]; long long needed = min(n, (i + 1) * k); flag &= (taken <= needed); } if (!flag) { cout << -1 << endl; } else { long long left = 0, right = m + 1; while (left + 1 < right) { long long med = (left + right) / 2; for (long long i = 0; i < med; i++) { if (s[i].first < MAXN) { cnt[s[i].first]++; } } taken = 0; bool flag = true; for (long long i = 0; flag && i < (n + k + med - 1) / k; i++) { taken += cnt[i]; long long needed = min(n + med, (i + 1) * k); flag &= (taken <= needed); } for (long long i = 0; i < med; i++) { if (s[i].first < MAXN) { cnt[s[i].first]--; } } if (flag) { left = med; } else { right = med; } } cout << left << endl; for (long long i = 0; i < left; i++) { cout << s[i].second + 1 << ; } } } |
#include <bits/stdc++.h> using namespace std; using ll = long long; const int M = 1e9 + 7; void madd(int& a, int b) { a += b; if (a >= M) a -= M; } int mult(int a, int b) { return (1LL * a * b) % M; } int modexp(int a, int b) { int res = 1; while (b > 0) { if (b & 1) res = mult(res, a); a = mult(a, a); b >>= 1; } return res; } int inverse(int x) { return modexp(x, M - 2); } const int maxn = 1e5 + 5; int n, a[maxn]; int cnt[maxn]; int mu[maxn]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; cnt[a[i]]++; } mu[1] = 1; for (int i = 1; i < maxn; i++) { for (int j = 2 * i; j < maxn; j += i) { mu[j] -= mu[i]; cnt[i] += cnt[j]; } } int ans = 0; for (int d = 1; d <= 100000; d++) { madd(ans, mult((mu[d] + M) % M, modexp(2, cnt[d]) - 1)); } cout << ans << n ; } |
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 3.4
// \ \ Application : MIG
// / / Filename : glbl.v
// /___/ /\ Date Last Modified : $Date: 2010/02/26 09:12:08 $
// \ \ / \ Date Created : Mon Jun 23 2008
// \___\/\___\
//
// Device : Virtex-6
// Design Name : DDR3 SDRAM
// Purpose :
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
|
module pulse_senor_read(clk,reset_n,chipselect,address,write,writedata,read,byteenable,readdata,pulse_in);
// this module is used to read the lacation senor and angle senor in inverted pendulum application
// pulse_in[0] connected to A port
//Gang Chen @ Fortiss Fb2
input clk;
input reset_n;
input chipselect;
input [1:0]address;
input write;
input [31:0] writedata;
input read;
input [3:0] byteenable;
output [31:0] readdata;
input [1:0]pulse_in;
reg [31:0] speed_count;
reg [31:0] speed_count1;
reg [31:0] current_count;
reg [31:0] control_reg;
reg [31:0] time_period;
reg speed_count_sel;
reg current_count_sel;
reg control_reg_sel;
reg time_period_sel;
reg [31:0] readdata;
reg pio_state1;
reg pio_state2;
reg [31:0] time_period_count;
reg clear_speed_count;
reg write_count;
wire stop_bit;
//wire update_time;
assign stop_bit=control_reg[0];
//assign update_time=control_reg[1];
//function apart
always@(negedge clk or negedge reset_n)
begin
if(!reset_n)
begin
pio_state1<=0;
pio_state2<=0;
end
else
begin
pio_state1<=pulse_in[0];
pio_state2<=pio_state1;
end
end
always@(posedge clk or negedge reset_n)
begin
if(!reset_n)
begin
current_count<=32'h80000000;
end
else
begin
if(stop_bit)
begin
current_count<=32'h80000000;
end
else
if(write & chipselect & current_count_sel)
begin
if(byteenable[0]) current_count[7:0]<=writedata[7:0];
if(byteenable[1]) current_count[15:8]<=writedata[15:8];
if(byteenable[2]) current_count[23:16]<=writedata[23:16];
if(byteenable[3]) current_count[31:24]<=writedata[31:24];
end
else
begin
if(pio_state1==1&&pio_state2==0)
begin
if(pulse_in[1])
current_count<=current_count+1;
else
current_count<=current_count-1;
end
end
end
end
always@(negedge clk or negedge reset_n)
begin
if(!reset_n)
begin
time_period_count<=32'h0FF307B0; //default period is 10 ms
clear_speed_count<=0;
end
else
begin
if(time_period_count[31])
begin
clear_speed_count<=1;
time_period_count[30:0]<=time_period[30:0];
time_period_count[31]<=0;
end
else
begin
clear_speed_count<=0;
time_period_count<=time_period_count+1;
end
end
end
always@(posedge clk or negedge reset_n)
begin
if(!reset_n)
begin
speed_count1<=32'h00000000;
speed_count<=32'h00000000;
end
else
begin
if(stop_bit)
begin
speed_count1<=32'h00000000;
speed_count<=32'h00000000;
end
else
if(clear_speed_count)
begin
speed_count1<=32'h00000000;
speed_count<=speed_count1;
end
else
begin
if(pio_state1==1&&pio_state2==0)
begin
if(pulse_in[1])
speed_count1<=speed_count1+1;
else
speed_count1<=speed_count1-1;
end
end
end
end
//bus interface
always @ (address)
begin
speed_count_sel<=0;
current_count_sel<=0;
control_reg_sel<=0;
time_period_sel<=0;
case(address)
2'b00:speed_count_sel<=1;
2'b01:current_count_sel<=1;
2'b10:control_reg_sel<=1;
2'b11:time_period_sel<=1;
endcase
end
//wirte control register
always @ (posedge clk or negedge reset_n)
begin
if(!reset_n)
control_reg<=0;
else
begin
if(write & chipselect & control_reg_sel)
begin
if(byteenable[0]) control_reg[7:0]<=writedata[7:0];
if(byteenable[1]) control_reg[15:8]<=writedata[15:8];
if(byteenable[2]) control_reg[23:16]<=writedata[23:16];
if(byteenable[3]) control_reg[31:24]<=writedata[31:24];
//control_reg<=writedata;
end
end
end
//wirte state register
always @ (posedge clk or negedge reset_n)
begin
if(!reset_n)
time_period<=32'h0FF307B0; //default period is 10 ms
else
begin
if(write & chipselect & time_period_sel)
begin
if(byteenable[0]) time_period[7:0]<=writedata[7:0];
if(byteenable[1]) time_period[15:8]<=writedata[15:8];
if(byteenable[2]) time_period[23:16]<=writedata[23:16];
if(byteenable[3]) time_period[31:24]<=writedata[31:24];
//time_period<=writedata;
end
end
end
//read register
always @ (address or read or speed_count or current_count or control_reg or time_period or chipselect)
begin
if(read & chipselect)
case(address)
2'b00:
begin
readdata<=speed_count;
end
2'b01:
begin
readdata<=current_count;
end
2'b10:
begin
readdata<=control_reg;
end
2'b11:
begin
readdata<=time_period;
end
endcase
end
endmodule |
#include <bits/stdc++.h> using namespace std; vector<int> v[27]; bool vis[27]; vector<pair<int, int> > pr; int cnt, flag; void dfs(int nod, int dest) { int i; vis[nod] = 1; if (nod == dest) { flag = 1; return; } for (i = 0; i < v[nod].size(); i++) { int curr = v[nod][i]; if (vis[curr] == 0) { dfs(curr, dest); } } return; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, i; cin >> n; string s1, s2; cin >> s1 >> s2; for (i = 0; i < n; i++) { flag = 0; memset(vis, 0, sizeof(vis)); int nod = s1[i] - a + 1; int dest = s2[i] - a + 1; dfs(nod, dest); if (flag == 0) { cnt++; pr.push_back(make_pair(nod, dest)); v[nod].push_back(dest); v[dest].push_back(nod); } } cout << cnt << endl; for (i = 0; i < pr.size(); i++) { char ch1 = pr[i].first + a - 1, ch2 = pr[i].second + a - 1; cout << ch1 << << ch2 << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long INF = (1ll << 60); const int N = 205; int n, m, _len; int nxt[N]; long long k; long long ADD(long long x, long long y) { return min(INF, x + y); } struct node { char pref[N]; char suff[N]; long long len; long long sum; } t[N * 4], eddd; char s[N * 4]; char ans[N]; node operator+(node a, node b) { node ans; ans.len = ADD(a.len, b.len); ans.sum = ADD(a.sum, b.sum); int l1 = min(a.len, 2ll * _len); int l2 = min(b.len, 2ll * _len); for (int i = (int)(1); i <= (int)(min(l1, _len)); i++) s[i] = a.pref[i]; for (int i = (int)(1); i <= (int)(min(l1, _len)); i++) s[l1 - i + 1] = a.suff[i]; for (int i = (int)(1); i <= (int)(min(l2, _len)); i++) s[l1 + i] = b.pref[i]; for (int i = (int)(1); i <= (int)(min(l2, _len)); i++) s[l1 + l2 - i + 1] = b.suff[i]; int p = 0; s[l1 + l2 + 1] = 0; for (int i = (int)(l1 - min(l1, _len - 1) + 1); i <= (int)(l1 + 1 + min(l2, _len - 1) - 1); i++) { for (; p && s[i] != ::ans[p + 1]; p = nxt[p]) ; if (s[i] == ::ans[p + 1]) ++p; if (p == _len) ++ans.sum, p = nxt[p]; } for (int i = (int)(1); i <= (int)(min(_len, l1 + l2)); i++) ans.pref[i] = s[i]; for (int i = (int)(1); i <= (int)(min(_len, l1 + l2)); i++) ans.suff[i] = s[l1 + l2 - i + 1]; return ans; } long long count(int l) { _len = l; nxt[1] = 0; for (int i = (int)(2); i <= (int)(l); i++) { int j = nxt[i - 1]; for (; j && ans[j + 1] != ans[i]; j = nxt[j]) ; nxt[i] = j + (ans[j + 1] == ans[i]); } t[0].pref[1] = t[0].suff[1] = 0 ; t[1].pref[1] = t[1].suff[1] = 1 ; eddd.pref[1] = eddd.suff[1] = 2 ; t[0].len = t[1].len = eddd.len = 1; t[0].sum = (l == 1 && ans[1] == 0 ); t[1].sum = (l == 1 && ans[1] == 1 ); eddd.sum = (l == 1 && ans[1] == 2 ); for (int i = (int)(2); i <= (int)(n); i++) { t[i] = t[i - 2] + t[i - 1]; } return (t[n] + eddd).sum; } int main() { scanf( %d%lld%d , &n, &k, &m); k++; for (int i = (int)(1); i <= (int)(m); i++) { ans[i] = 2 ; long long val = count(i); if (val >= k) break; k -= val; ans[i] = 0 ; val = count(i); if (val >= k) { putchar( 0 ); continue; } k -= val; ans[i] = 1 ; val = count(i); if (val >= k) { putchar( 1 ); continue; } assert(0); } } |
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; vector<string> ans; string email = ; bool isPoss = true; for (int i = 0; i < s.length(); i++) { if (s[i] == @ ) { if ((i + 1 < s.length()) && (s[i + 1] != @ )) { if (email == ) { isPoss = false; break; } else { email += s[i]; email += s[i + 1]; ans.push_back(email); i++; email = ; } } else { isPoss = false; break; } } else { email += s[i]; } } if ((email != ) && (isPoss) && (ans.size() > 0)) { ans[ans.size() - 1] = ans[ans.size() - 1] + email; } if ((ans.size() == 0) || (!isPoss)) { cout << No solution ; } else { cout << ans[0]; for (int i = 1; i < ans.size(); i++) { cout << , << ans[i]; } } } |
#include <bits/stdc++.h> using namespace std; const int MAX = 109; int a[MAX], n, k, t = 1e9, s; int main() { cin >> n; for (int i = 0; i < 2 * n - 1; i++) { cin >> a[i], s += abs(a[i]), t = min(t, abs(a[i])); if (a[i] < 0) k++; } if (k % 2 && n % 2 == 0) s -= 2 * t; cout << s; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:13:58 05/20/2014
// Design Name: Single_Cycle_CPU
// Module Name: C:/Users/Deus/Windows Sync/Xilinx Workspace/Single/test_t.v
// Project Name: Single
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Single_Cycle_CPU
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_t;
// Inputs
reg clk_in;
reg btn_t;
reg [5:0] sw;
// Outputs
wire [6:0] seg;
wire [3:0] an;
// Instantiate the Unit Under Test (UUT)
Single_Cycle_CPU uut (
.clk_in(clk_in),
.btn_t(btn_t),
.sw(sw),
.seg(seg),
.an(an)
);
initial begin
// Initialize Inputs
clk_in = 0;
btn_t = 0;
sw = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
always #10 clk_in = ~clk_in;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = 1e9 + 7; struct node { int x, d; }; vector<int> adj[100005]; vector<int> good[105]; int vis[100005]; int a[100005]; int d[100005][105]; void bfs(int s) { queue<node> q; for (int i = 0; i < good[s].size(); i++) { int v = good[s][i]; node tmp; tmp.x = v; tmp.d = 0; q.push(tmp); } while (!q.empty()) { node t = q.front(); q.pop(); d[t.x][s] = min(d[t.x][s], t.d); for (int i = 0; i < adj[t.x].size(); i++) { int v = adj[t.x][i]; if (vis[v] == 0) { vis[v] = 1; node tmp; tmp.x = v; tmp.d = t.d + 1; q.push(tmp); } } } } int main() { int n, m, k, s, u, v; scanf( %d%d%d%d , &n, &m, &k, &s); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); good[a[i]].push_back(i); } for (int i = 0; i < m; i++) { scanf( %d%d , &u, &v); adj[u].push_back(v); adj[v].push_back(u); } fill(d[0], d[0] + 105 * 100005, inf); for (int i = 1; i <= k; i++) { memset(vis, 0, sizeof(vis)); bfs(i); } for (int i = 1; i <= n; i++) { sort(d[i] + 1, d[i] + 1 + k); long long sum = 0; for (int j = 1; j <= s; j++) sum += d[i][j]; printf( %lld , sum); } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__MUX2I_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__MUX2I_BEHAVIORAL_PP_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1_n/sky130_fd_sc_ls__udp_mux_2to1_n.v"
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__mux2i (
Y ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire mux_2to1_n0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
sky130_fd_sc_ls__udp_mux_2to1_N mux_2to1_n0 (mux_2to1_n0_out_Y, A0, A1, S );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, mux_2to1_n0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__MUX2I_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; using lli = long long int; using pii = pair<int, int>; using vi = vector<int>; using vb = vector<bool>; using vvi = vector<vector<int>>; using vlli = vector<long long int>; using vpii = vector<pair<int, int>>; lli n, m, k, u, v, x, ans, curr, T; vlli c; lli fast_exp(lli base, lli exp) { lli res = 1; base = base % 1000000007; while (exp > 0) { if (exp % 2) res = (res * base) % 1000000007; base = (base * base) % 1000000007; exp /= 2; } return res % 1000000007; } template <class T> struct DSU { map<T, T> par; T comp_sz = n; T get(T u) { if (par.find(u) == par.end()) return u; return par[u] = get(par[u]); } void unite(T x, T y) { T X = get(x), Y = get(y); if (X == Y) return; par[Y] = X; --comp_sz; } }; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> m >> k; c.resize(n + 1); map<lli, DSU<lli>> virus; for (int i = 1; i <= n; i++) cin >> c[i]; for (int i = 1; i <= m; i++) { cin >> u >> v; x = c[u] ^ c[v]; virus[x].unite(u, v); } ans = ((fast_exp(2, k) - virus.size() + 1000000007) * fast_exp(2, n)) % 1000000007; for (auto i : virus) { curr = (i.second).comp_sz; ans = (ans + fast_exp(2, curr)) % 1000000007; } cout << ans; } |
#include <bits/stdc++.h> using namespace std; int n, m, u, v, cnt, ans; int t[1100000], nxt[1100000], to[1100000]; int a[1100000], b[1100000], c[1100000], f[1100000]; int vis[1100000]; void add(int u, int v) { nxt[cnt] = t[u], t[u] = cnt, to[cnt++] = v; } void dfs(int x) { vis[x] = true; for (int e = t[x]; ~e; e = nxt[e]) { int y = to[e]; to[e] = to[e ^ 1] = 0; if (y) { if (!vis[y]) dfs(y); if (f[y]) a[++ans] = x, b[ans] = y, c[ans] = f[y], f[y] = 0; else if (f[x]) a[++ans] = f[x], b[ans] = x, c[ans] = y, f[x] = 0; else f[x] = y; } } } int main() { memset(t, 0xff, sizeof(t)); cin >> n >> m; for (int i = 1; i <= m; ++i) cin >> u >> v, add(u, v), add(v, u); vis[0] = true; for (int i = 1; i <= n; ++i) if (!vis[i]) dfs(i); printf( %d n , ans); for (int i = 1; i <= ans; ++i) printf( %d %d %d n , a[i], b[i], c[i]); return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 150000; int b[maxn]; long long a[maxn]; int main(void) { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &b[i]); b[0] = b[n]; int id = 0; for (int i = 1; i <= n; i++) if (b[i] > b[i - 1]) { id = i; break; } if (id == 0) { if (b[1] == 0) { printf( YES n ); for (int i = 1; i <= n; i++) printf( 1%c , n [i == n]); } else printf( NO n ); return 0; } a[id] = max(b[id], 1); for (int i = 0; i < n - 1; i++) { int nid = id - 1; if (nid == 0) nid = n; int nnid = nid - 1; if (nnid == 0) nnid = n; a[nid] = b[nid]; if (b[nnid] >= b[nid]) a[nid] += ((b[nnid] - b[nid]) / a[id] + 1) * a[id]; if (a[nid] == 0) a[nid] = a[id]; id = nid; } a[n + 1] = a[1]; printf( YES n ); for (int i = 1; i <= n; i++) printf( %I64d%c , a[i], n [i == n]); return 0; } |
#include <bits/stdc++.h> using namespace std; struct pr { int a, b, n, x; pr(int a, int b, int n) : a(a), b(b), n(n) {} pr() : a(0), b(0), n(-1) {} }; int n, m; vector<pr> a, b; void connect(int x1, int& x2, int& y2) { if ((x2 != -1 && x2 != x1) || (y2 != -1 && y2 != x1)) { cout << -1; exit(0); } x2 = y2 = x1; } int main() { cin >> n >> m; for (int i = 0; i < n; i++) { int x, y; cin >> x >> y; a.push_back(pr(x, y, -1)); } for (int i = 0; i < m; i++) { int x, y; cin >> x >> y; b.push_back(pr(x, y, -1)); } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (a[i].a == b[j].a && a[i].b != b[j].b) connect(a[i].a, a[i].n, b[j].n); else if (a[i].b == b[j].b && a[i].a != b[j].a) connect(a[i].b, a[i].n, b[j].n); else if (a[i].a == b[j].b && a[i].b != b[j].a) connect(a[i].a, a[i].n, b[j].n); else if (a[i].b == b[j].a && a[i].a != b[j].b) connect(a[i].b, a[i].n, b[j].n); } } int ans = -1; for (int i = 0; i < n; i++) { if (a[i].n != -1) { if (ans == -1 || ans == a[i].n) ans = a[i].n; else { cout << 0; return 0; } } } cout << ans; return 0; } |
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_SYSTEMV3_MENU_DOWN (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input in_port;
input reset_n;
wire clk_en;
wire data_in;
wire read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {1 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m; int main() { scanf( %d%d , &n, &m); if (n == 1 && m == 2) { printf( 0 n1 1 n1 2 n1 1 n ); return 0; } if (n == 2 && m == 1) { printf( 0 n1 1 n2 1 n1 1 n ); return 0; } if (n * m % 2 == 1 || n == 1 || m == 1) { printf( %d n%d %d %d %d n , 1, n, m, 1, 1); for (int i = 1; i <= n; ++i) { if (i % 2 == 1) { for (int j = 1; j <= m; ++j) printf( %d %d n , i, j); } else { for (int j = m; j > 0; --j) printf( %d %d n , i, j); } } printf( %d %d n , 1, 1); } else if (n % 2 == 0) { printf( 0 n1 1 n ); for (int i = 1; i <= n; ++i) { if (i % 2 == 1) { for (int j = 2; j <= m; ++j) printf( %d %d n , i, j); } else { for (int j = m; j > 1; --j) printf( %d %d n , i, j); } } for (int i = n; i > 0; --i) printf( %d %d n , i, 1); } else { printf( 0 n1 1 n ); for (int j = 1; j <= m; ++j) { if (j % 2 == 1) { for (int i = 2; i <= n; ++i) printf( %d %d n , i, j); } else { for (int i = n; i > 1; --i) printf( %d %d n , i, j); } } for (int j = m; j > 0; --j) printf( %d %d n , 1, j); } return 0; } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: jbi_min_wrtrk.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/////////////////////////////////////////////////////////////////////////
//
//
// Top level Module: jbi_min_wrtrk
// Where Instantiated: jbi_min
//
// Description: WRI Tracker
//
// The WRI Tracker keeps count of the number of outstanding WRI (received by
// JBI but not yet acknowledged by SCTAG) and the oldest WRI in JBI. This block
// contains 3 counters: one WRI pending counter and two tag counters.
//
// The wri_pend counter is incremented when a WRI is inserted into a
// MemReqQ and decremented when SCTAG gives an acknowledgement (sends Write Ack packet).
// Because no more than one port can have outstanding WRI (issued WRI waiting for ack),
// only one counter is necessary for 4 SCTAGs.
//
// There are two 6-bit tag counters (upper bit to resolve wrap ambiguity):
// new_wri_tag[5:0] increments with each new WRI* received from Jbus (all WRI*
// are assigned a tag #) and oldest_wri_tag is incremented with each WrAck
// received from the SCTAGs.
//
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "jbi.h"
module jbi_min_wrtrk (/*AUTOARG*/
// Outputs
min_oldest_wri_tag, min_pre_wri_tag, wrtrk_new_wri_tag,
wrtrk_rq0_oldest_wri_tag, wrtrk_rq1_oldest_wri_tag,
wrtrk_rq2_oldest_wri_tag, wrtrk_rq3_oldest_wri_tag,
// Inputs
clk, rst_l, cpu_clk, cpu_rst_l, io_jbi_j_ad_ff, parse_wdq_push,
parse_hdr, parse_rw, parse_wrm, parse_subline_req, wdq_wr_vld,
mout_scb0_jbus_wr_ack, mout_scb1_jbus_wr_ack, mout_scb2_jbus_wr_ack,
mout_scb3_jbus_wr_ack
);
input clk;
input rst_l;
input cpu_clk;
input cpu_rst_l;
// Parse Block Interface
input [127:64] io_jbi_j_ad_ff;
input parse_wdq_push;
input parse_hdr;
input parse_rw;
input parse_wrm;
input parse_subline_req;
// Write Decomposition Interface
input wdq_wr_vld; // pushed write txn to a rhq
// Memory Outbound Interface - cpu clock domain
input mout_scb0_jbus_wr_ack;
input mout_scb1_jbus_wr_ack;
input mout_scb2_jbus_wr_ack;
input mout_scb3_jbus_wr_ack;
// To Non-Cache IO
output [`JBI_WRI_TAG_WIDTH-1:0] min_oldest_wri_tag; // same as wrtrk_oldest_wri_tag
output [`JBI_WRI_TAG_WIDTH-1:0] min_pre_wri_tag;
// Request Queue Interface
output [`JBI_WRI_TAG_WIDTH-1:0] wrtrk_new_wri_tag;
output [`JBI_WRI_TAG_WIDTH-1:0] wrtrk_rq0_oldest_wri_tag;
output [`JBI_WRI_TAG_WIDTH-1:0] wrtrk_rq1_oldest_wri_tag;
output [`JBI_WRI_TAG_WIDTH-1:0] wrtrk_rq2_oldest_wri_tag;
output [`JBI_WRI_TAG_WIDTH-1:0] wrtrk_rq3_oldest_wri_tag;
////////////////////////////////////////////////////////////////////////
// Interface signal type declarations
////////////////////////////////////////////////////////////////////////
wire [`JBI_WRI_TAG_WIDTH-1:0] min_oldest_wri_tag;
wire [`JBI_WRI_TAG_WIDTH-1:0] min_pre_wri_tag;
wire [`JBI_WRI_TAG_WIDTH-1:0] wrtrk_new_wri_tag;
wire [`JBI_WRI_TAG_WIDTH-1:0] wrtrk_rq0_oldest_wri_tag;
wire [`JBI_WRI_TAG_WIDTH-1:0] wrtrk_rq1_oldest_wri_tag;
wire [`JBI_WRI_TAG_WIDTH-1:0] wrtrk_rq2_oldest_wri_tag;
wire [`JBI_WRI_TAG_WIDTH-1:0] wrtrk_rq3_oldest_wri_tag;
////////////////////////////////////////////////////////////////////////
// Local signal declarations
////////////////////////////////////////////////////////////////////////
//
// Code start here
//
wire [`JBI_WRI_TAG_WIDTH-1:0] wrtrk_oldest_wri_tag;
reg [`JBI_WRI_TAG_WIDTH-1:0] next_wrtrk_new_wri_tag;
reg [`JBI_WRI_TAG_WIDTH-1:0] next_wrtrk_oldest_wri_tag;
reg [`JBI_WRI_TAG_WIDTH-1:0] next_min_pre_wri_tag;
wire incr_wrtrk_new_wri_tag;
wire incr_wrtrk_oldest_wri_tag;
wire [5:0] pre_tag_incr;
reg [63:0] be;
//*******************************************************************************
// New WRI Tag (JBUS CLK)
// - assigned to a txn as it exits WDQ
//*******************************************************************************
assign incr_wrtrk_new_wri_tag = wdq_wr_vld;
always @ ( /*AUTOSENSE*/incr_wrtrk_new_wri_tag or wrtrk_new_wri_tag) begin
if (incr_wrtrk_new_wri_tag)
next_wrtrk_new_wri_tag = wrtrk_new_wri_tag + 1'b1;
else
next_wrtrk_new_wri_tag = wrtrk_new_wri_tag;
end
//*******************************************************************************
// Predicted WRI Tag (JBUS CLK)
// - computed as a txn enters WDQ
// - predicts what new_wri_tag would be by calculating the number of WR8 txns
// a WRM will expand to (from right to left, look for 0<-1 transitions in groups
// of 8-bit BE)
// - used for PIO read returns and Mondos
//*******************************************************************************
always @ ( /*AUTOSENSE*/io_jbi_j_ad_ff or parse_wrm) begin
if (parse_wrm)
be = io_jbi_j_ad_ff[127:64];
else
be = { io_jbi_j_ad_ff[127:112], {48{1'b0}} };
end
jbi_min_wrtrk_ptag_sum u_wrtrk_ptag_sum
(.io_jbi_j_ad_ff(be[63:0]),
.pre_tag_incr(pre_tag_incr[5:0])
);
always @ ( /*AUTOSENSE*/min_pre_wri_tag or parse_hdr or parse_rw
or parse_subline_req or parse_wdq_push or parse_wrm
or pre_tag_incr) begin
if (parse_wdq_push & parse_hdr & ~parse_rw) begin
if (parse_wrm | parse_subline_req)
next_min_pre_wri_tag = min_pre_wri_tag
+ {{`JBI_WRI_TAG_WIDTH-6{1'b0}}, pre_tag_incr[5:0]};
else
next_min_pre_wri_tag = min_pre_wri_tag + 1'b1;
end
else
next_min_pre_wri_tag = min_pre_wri_tag;
end
//*******************************************************************************
// Oldest WRI Tag (CPU CLK)
//*******************************************************************************
assign incr_wrtrk_oldest_wri_tag = mout_scb0_jbus_wr_ack
| mout_scb1_jbus_wr_ack
| mout_scb2_jbus_wr_ack
| mout_scb3_jbus_wr_ack;
always @ ( /*AUTOSENSE*/incr_wrtrk_oldest_wri_tag
or wrtrk_oldest_wri_tag) begin
if (incr_wrtrk_oldest_wri_tag)
next_wrtrk_oldest_wri_tag = wrtrk_oldest_wri_tag + 1'b1;
else
next_wrtrk_oldest_wri_tag = wrtrk_oldest_wri_tag;
end
assign min_oldest_wri_tag = wrtrk_oldest_wri_tag;
assign wrtrk_rq0_oldest_wri_tag = wrtrk_oldest_wri_tag;
assign wrtrk_rq1_oldest_wri_tag = wrtrk_oldest_wri_tag;
assign wrtrk_rq2_oldest_wri_tag = wrtrk_oldest_wri_tag;
assign wrtrk_rq3_oldest_wri_tag = wrtrk_oldest_wri_tag;
//*******************************************************************************
// DFFRL Instantiations
//*******************************************************************************
//----------------------
// JBUS CLK
//----------------------
dffrl_ns #(`JBI_WRI_TAG_WIDTH) u_dffrl_wrtrk_new_wri_tag
(.din(next_wrtrk_new_wri_tag),
.clk(clk),
.rst_l(rst_l),
.q(wrtrk_new_wri_tag)
);
dffrl_ns #(`JBI_WRI_TAG_WIDTH) u_dffrl_min_pre_wri_tag
(.din(next_min_pre_wri_tag),
.clk(clk),
.rst_l(rst_l),
.q(min_pre_wri_tag)
);
//----------------------
// CPU CLK
//----------------------
dffrl_ns #(`JBI_WRI_TAG_WIDTH) u_dffrl_wrtrk_oldest_wri_tag
(.din(next_wrtrk_oldest_wri_tag),
.clk(cpu_clk),
.rst_l(cpu_rst_l),
.q(wrtrk_oldest_wri_tag)
);
//*******************************************************************************
// Rule Checks
//*******************************************************************************
//synopsys translate_off
//synopsys translate_on
endmodule
// Local Variables:
// verilog-library-directories:(".")
// verilog-auto-sense-defines-constant:t
// End:
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAPMET1_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__TAPMET1_FUNCTIONAL_PP_V
/**
* tapmet1: Tap cell with isolated power and ground connections.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__tapmet1 (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAPMET1_FUNCTIONAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR2B_FUNCTIONAL_V
`define SKY130_FD_SC_HD__NOR2B_FUNCTIONAL_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__nor2b (
Y ,
A ,
B_N
);
// Module ports
output Y ;
input A ;
input B_N;
// Local signals
wire not0_out ;
wire and0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A );
and and0 (and0_out_Y, not0_out, B_N );
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR2B_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR4B_4_V
`define SKY130_FD_SC_HD__OR4B_4_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog wrapper for or4b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__or4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__or4b_4 (
X ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__or4b_4 (
X ,
A ,
B ,
C ,
D_N
);
output X ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR4B_4_V
|
#include <bits/stdc++.h> using namespace std; int main() { int q; cin >> q; for (int i = 0; i < q; i++) { int n, r; cin >> n >> r; int arr[n]; for (int j = 0; j < n; j++) { cin >> arr[j]; } sort(arr, arr + n); int shots = 0, act[n], p = 0; act[0] = arr[0]; p++; for (int j = 1; j < n; j++) { if (arr[j] == arr[j - 1]) { } else { act[p] = arr[j]; p++; } } for (int j = 0; j < p; j++) { if (act[p - j - 1] - j * r <= 0) { break; } shots++; } cout << shots << endl; } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:52:27 05/20/2015
// Design Name:
// Module Name: cpu_fpga
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module cpu_fpga(
output [6:0] segdisp,
output [3:0] sel,
output clockout,
output rstout,
input btnclock,
input btnrst,
input clock
);
wire clockint, btnrstint;
assign clockout = clockint;
assign rstout = btnrst;
wire slowclk;
clock_slower #(.WIDTH(19)) slowed_clock(.y(slowclk), .clk(clock));
wire [15:0] curpc;
wire [15:0] reg_zero;
seven_seg_wrapper mysegwrapper(
.segdisplay(segdisp),
.segselect(sel),
.pcval({curpc[7:0],reg_zero[7:0]}), // Input is here.
.clock(clock),
.enable(slowclk)
);
// Clock Debouncer
debouncer clockinput(
.y(clockint),
.x(btnclock),
.clk(clock),
.clken(slowclk)
);
// Reset Debouncer
debouncer resetinput(
.y(btnrstint),
.x(btnrst),
.clk(clock),
.clken(slowclk)
);
// CPUs
cpu_behav my_cpu(
.prog_cnt(curpc),
.reg0(reg_zero),
.clk(clockint),
.rst(!btnrstint)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-8; const int iinf = INT_MAX; const long long linf = 2e18; const double dinf = 1e30; const int MOD = 1000000007; inline int read() { int X = 0, w = 0; char ch = 0; while (!isdigit(ch)) { w |= ch == - ; ch = getchar(); } while (isdigit(ch)) X = (X << 3) + (X << 1) + (ch ^ 48), ch = getchar(); return w ? -X : X; } void write(int x) { if (x < 0) putchar( - ), x = -x; if (x > 9) write(x / 10); putchar(x % 10 + 0 ); } void print(int x) { cout << x << n ; exit(0); } void PRINT(string x) { cout << x << n ; exit(0); } void douout(double x) { printf( %lf n , x + 0.0000000001); } long long ans = 1e18, a, b, mx = 1e18; int main() { cin >> a >> b; for (long long i = 1; i * i <= (a + b); i++) { if (a % i == 0) mx = min(mx, a / i); if (b % i == 0) mx = min(mx, b / i); if ((a + b) % i == 0 && (a + b) / i >= mx) ans = min(ans, 2 * i + 2 * ((a + b) / i)); } cout << ans; } |
#include <bits/stdc++.h> int n, m, l, x, oo = 1000000007, c[100005], a[100005], b[100005]; long long res = 1, ans; long long Exp(long long x, long long y) { long long res = 1; for (; y; y >>= 1, x = x * x % oo) if (y & 1) res = res * x % oo; return res; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &x), c[x]++; for (int i = 100005 - 5; i; i--) c[i - 1] += c[i]; for (int i = 1; c[i]; i++) { m = l = 0, res = 1; for (int j = 1; j * j <= i; j++) if (i % j == 0) { a[m++] = j; if (j * j - i) b[l++] = i / j; } while (l--) a[m++] = b[l]; for (int j = 1; j < m; j++) res = res * Exp(j, c[a[j - 1]] - c[a[j]]) % oo; ans = (ans + res * (Exp(m, c[i]) - Exp(m - 1, c[i]))) % oo; } printf( %d n , (ans + oo) % oo); return 0; } |
#include <bits/stdc++.h> using namespace std; int sum = 0; vector<vector<int>> mat; vector<string> mat2; void f1(vector<string>& ans, int f, string s) { if (f == 0) return; string s1 = to_string(f) + + s; ans.push_back(s1); sum += f * s.length(); vector<int> temp(2, 0); temp[0] = f; temp[1] = s.length(); mat.push_back(temp); mat2.push_back(s); } string frs(char c, int fre) { string ans = ; for (int i = 0; i < fre; i++) { ans = ans + c; } return ans; } int main() { int n, m, k; cin >> n >> m >> k; vector<string> ans; string s; int f = (m - 1) / 4; f1(ans, f, RRRR ); if ((m - 1) % 4) f1(ans, 1, frs( R , (m - 1) % 4)); f = (m - 1) / 4; f1(ans, f, LLLL ); if ((m - 1) % 4) f1(ans, 1, frs( L , (m - 1) % 4)); for (int i = 0; i < n - 1; i++) { f1(ans, 1, D ); f1(ans, m - 1, RUD ); f = (m - 1) / 4; f1(ans, f, LLLL ); if ((m - 1) % 4) f1(ans, 1, frs( L , (m - 1) % 4)); } f = (n - 1) / 4; f1(ans, f, UUUU ); if ((n - 1) % 4) f1(ans, 1, frs( U , (n - 1) % 4)); int N = ans.size(); if (sum < k) { cout << NO ; } else { cout << YES << endl; vector<string> v; int cur = 0; for (int i = 0; i < N; i++) { if (cur == k) break; int l = mat[i][0] * mat[i][1]; if (cur + l <= k) { v.push_back(ans[i]); cur += l; } else { int len = k - cur; f = len / mat[i][1]; string s; if (f) { s = to_string(f) + + mat2[i]; v.push_back(s); } if (len % (mat[i][1])) { s = 1 + mat2[i].substr(0, len % (mat[i][1])); v.push_back(s); } break; } } N = v.size(); cout << N << endl; for (int j = 0; j < N; j++) { cout << v[j] << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int l[1000000]; int one_line[5001][5001] = {0}; int summ[5001][5001] = {0}; int fac[5001]; int main() { int n, m, p; scanf( %d %d %d , &n, &m, &p); for (int i = 0; i < n; i++) scanf( %d , &l[i]); fac[0] = 1; for (int i = 1; i <= 5000; i++) fac[i] = ((fac[i - 1]) * (long long)i) % p; one_line[1][1] = 1; for (int i = 2; i <= 5000; i++) { for (int j = 1; j <= min(m, 5000); j++) { one_line[i][j] = (one_line[i - 1][j] * (long long)(j - 1) + one_line[i - 1][j - 1]) % p; } } summ[1][1] = m; for (int i = 2; i <= 5000; i++) { for (int j = 1; j <= min(m, 5000); j++) { summ[i][j] = (summ[i - 1][j] * (long long)(j - 1) + summ[i - 1][j - 1] * (long long)(m - j + 1)) % p; } } int prev_progress[5001] = {0}; int prev_l = 0; prev_progress[0] = 1; for (int i = 0; i < n; i++) { int next_progress[5001]; for (int j = 0; j <= l[i]; j++) next_progress[j] = 0; int tot1 = 0; for (int j = 0; j <= prev_l; j++) tot1 = (tot1 + prev_progress[j]) % p; int tot2 = 1; tot2 = (tot2 * (long long)m) % p; for (int j = 1; j < l[i]; j++) tot2 = (tot2 * (long long)(m - 1)) % p; for (int j = 1; j <= l[i]; j++) { next_progress[j] = (tot1 * (long long)summ[l[i]][j]) % p; int prev = 0; if (j <= prev_l) prev = prev_progress[j]; next_progress[j] -= (((prev * (long long)one_line[l[i]][j]) % p) * fac[j]) % p; if (next_progress[j] < 0) next_progress[j] += p; } for (int j = 0; j <= l[i]; j++) prev_progress[j] = next_progress[j]; prev_l = l[i]; } int res = 0; for (int i = 0; i <= prev_l; i++) res = (res + prev_progress[i]) % p; printf( %d n , res); } |
#include <bits/stdc++.h> using namespace std; int main() { int i, j, k, m, n, a = 0, b = 0; cin >> n >> m; k = n; k = k / 9; n = n % 9; if (n != 0) k++; for (i = 0; i < k; i++) cout << 54; cout << endl; for (i = 0; i < k - 1; i++) cout << 45; cout << 46; cout << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; struct node { int r, c, p; node() {} node(int _r, int _c, int _p) { r = _r, c = _c, p = _p; } }; const int MAXN = 1005; char g[MAXN][MAXN]; int dist[MAXN][MAXN]; int dx[] = {1, 0, -1, 0}; int dy[] = {0, 1, 0, -1}; int to_int(const char& c) { return c - 0 ; } bool is_digit(const char& c) { if ( 1 <= c && c <= 9 ) return true; return false; } void bfs(const int& r, const int& c, node s) { queue<node> q; q.push(s); memset(dist, -1, sizeof dist); dist[s.r][s.c] = 0; int xx, yy; while (!q.empty()) { s = q.front(); q.pop(); for (int i = 0; i < 4; ++i) { xx = dx[i] + s.r; yy = dy[i] + s.c; if (xx < 0 || xx >= r || yy < 0 || yy >= c || g[xx][yy] == T || dist[xx][yy] != -1) continue; dist[xx][yy] = dist[s.r][s.c] + 1; q.emplace(xx, yy, s.p); } } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int r, c, best, ans; vector<node> b; node s, f; while (cin >> r >> c) { for (int i = 0; i < r; ++i) { for (int j = 0; j < c; ++j) { cin >> g[i][j]; if (is_digit(g[i][j])) b.emplace_back(i, j, to_int(g[i][j])); if (g[i][j] == S ) s = node(i, j, 0); if (g[i][j] == E ) f = node(i, j, 0); } } bfs(r, c, f); ans = 0; best = dist[s.r][s.c]; for (node i : b) if (dist[i.r][i.c] <= best && dist[i.r][i.c] != -1) ans += i.p; cout << ans << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long a, b, sum = 0; vector<long long> A; int n; cin >> n; A.resize(n); for (int i = 0; i < n; i++) { cin >> a; sum += a; A[i] = sum; } b = sum / 2 + (sum % 2); a = 0; while (A[a] < b) a++; cout << a + 1; } |
#include <bits/stdc++.h> using namespace std; int main() { long long int t; cin >> t; while (t-- > 0) { long long int n, k, can = 0; cin >> n >> k; can += n / k; can = can * k; if (can < n) { if (n - can < k / 2) can += n - can; else can += k / 2; } cout << can << endl; } } |
#include <bits/stdc++.h> using namespace std; int main() { int q; cin >> q; while (q--) { long long x[3]; cin >> x[0] >> x[1] >> x[2]; sort(x, x + 3); x[2] -= x[1] - x[0]; cout << x[1] + x[2] / 2 << endl; } } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: Adam LLC
// Engineer: Adam Michael
//
// Create Date: 19:48:37 09/12/2015
// Design Name: SN74LS177Abehavior
// Module Name: C:/Users/adam/Documents/GitHub/Lab1SN74LS177A/SN74LS177AAbsoluteTime.v
// Project Name: Lab1SN74LS177A
////////////////////////////////////////////////////////////////////////////////
module SN74LS195AAbsoluteTime;
reg [3:0] P;
reg PE, J, K, CP, MR;
wire Q3not_gate, Q3not_behavior;
wire [3:0] Qbehavior, Qgates;
SN74LS195Agates GatesChip (Qgates, P, Q3not_gate, PE, J, K, CP, MR);
SN74LS195Abehavior BehaviorChip (Qbehavior, P, Q3not_behavior, PE, J, K, CP, MR);
always #5 CP = ~CP;
initial fork
MR = 1; P = 4'b1010; PE=0; J = 0; K = 0; CP = 0;
#5 MR = 0; #5 P = 4'b1010; #5 PE=0; #5 J = 0; #5 K = 0;
#23 MR = 1; #23 P = 4'b1010; #23 PE=0; #23 J = 1; #23 K = 1;
#41 MR = 1; #41 P = 4'b1010; #41 PE=1; #41 J = 1; #41 K = 1;
#59 MR = 1; #59 P = 4'b1010; #59 PE=1; #59 J = 0; #59 K = 0;
#77 MR = 1; #77 P = 4'b1010; #77 PE=1; #77 J = 1; #77 K = 0;
#103 MR = 1; #103 P = 4'b1010; #103 PE=1; #103 J = 0; #103 K = 1;
#153 $stop;
join
endmodule
|
Subsets and Splits