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#include <bits/stdc++.h> using namespace std; long long exgcd(long long a, long long b, long long &x, long long &y) { long long d = a; if (b != 0) { d = exgcd(b, a % b, y, x); y -= (a / b) * x; } else { x = 1; y = 0; } return d; } int main() { long long n, a, b, x, y, t; cin >> n >> a >> b; t = exgcd(a, b, x, y); if (n % t != 0 || (n < a && n < b)) { puts( NO ); } else { t = n / t; long long a1 = (t * x % b + b) % b, b1 = (t * y % a + a) % a; long long c = n - a1 * a - b1 * b; if (c % a == 0) a1 += c / a; else b1 += c / b; if (a1 < 0 || b1 < 0) puts( NO ); else { puts( YES ); cout << a1 << << b1; } } return 0; } |
module helloonechar #(parameter CLOCK_FREQ = 12000000, parameter BAUD_RATE = 9600)
(
input ext_clock,
output uart_tx_pin,
output uart_tx_led,
output counter_led,
output uart_clock_led);
wire reset;
/* uart tx */
wire uart_ready;
wire [7:0] uart_data;
wire uart_clock_enable;
wire uart_clock;
reg [32:0] count;
power_on_reset POR(
.clock(ext_clock),
.reset(reset));
always @(*) begin
uart_data = 8'h1f;
end
always @(negedge ext_clock or negedge reset) begin
if (~reset) begin
uart_clock_enable <= 1;
count <= 12000000;
end else begin
if (~uart_ready)
uart_clock_enable <= 0;
else begin
if (count == 0) begin
counter_led <= ~counter_led;
count <= 12000000;
uart_clock_enable <= 1;
end
else begin
count <= count - 1;
end
end
end
end
uart_tx #(.CLOCK_FREQ(CLOCK_FREQ), .BAUD_RATE(BAUD_RATE))
SERIAL (.read_data(uart_data),
.read_clock_enable(uart_clock_enable),
.reset(reset),
.ready(uart_ready),
.tx(uart_tx_pin),
.clock(ext_clock),
.uart_clock(uart_clock));
assign uart_tx_led = uart_tx_pin;
assign uart_clock_led = uart_clock;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int i, j, k, n, t = 1; while (t--) { cin >> n; vector<long> v(n), b(n), ans(n, 0); for (i = 0; i < n; i++) { cin >> v[i]; b[i] = v[i]; } for (i = n - 2; i >= 0; i--) { if (b[i + 1] >= v[i]) ans[i] = 1 + b[i + 1] - v[i]; b[i] = max(b[i], b[i + 1]); } for (i = 0; i < n; i++) { cout << ans[i] << ; } } return 0; } |
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: mux.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: A simple multiplexer
// Author: Dustin Richmond (@darichmond)
// TODO: Remove C_CLOG_NUM_INPUTS
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module mux
#(
parameter C_NUM_INPUTS = 4,
parameter C_CLOG_NUM_INPUTS = 2,
parameter C_WIDTH = 32,
parameter C_MUX_TYPE = "SELECT"
)
(
input [(C_NUM_INPUTS)*C_WIDTH-1:0] MUX_INPUTS,
input [C_CLOG_NUM_INPUTS-1:0] MUX_SELECT,
output [C_WIDTH-1:0] MUX_OUTPUT
);
`include "functions.vh"
generate
if(C_MUX_TYPE == "SELECT") begin
mux_select
#(/*AUTOINSTPARAM*/
// Parameters
.C_NUM_INPUTS (C_NUM_INPUTS),
.C_CLOG_NUM_INPUTS (C_CLOG_NUM_INPUTS),
.C_WIDTH (C_WIDTH))
mux_select_inst
(/*AUTOINST*/
// Outputs
.MUX_OUTPUT (MUX_OUTPUT[C_WIDTH-1:0]),
// Inputs
.MUX_INPUTS (MUX_INPUTS[(C_NUM_INPUTS)*C_WIDTH-1:0]),
.MUX_SELECT (MUX_SELECT[C_CLOG_NUM_INPUTS-1:0]));
end else if (C_MUX_TYPE == "SHIFT") begin
mux_shift
#(/*AUTOINSTPARAM*/
// Parameters
.C_NUM_INPUTS (C_NUM_INPUTS),
.C_CLOG_NUM_INPUTS (C_CLOG_NUM_INPUTS),
.C_WIDTH (C_WIDTH))
mux_shift_inst
(/*AUTOINST*/
// Outputs
.MUX_OUTPUT (MUX_OUTPUT[C_WIDTH-1:0]),
// Inputs
.MUX_INPUTS (MUX_INPUTS[(C_NUM_INPUTS)*C_WIDTH-1:0]),
.MUX_SELECT (MUX_SELECT[C_CLOG_NUM_INPUTS-1:0]));
end
endgenerate
endmodule
module mux_select
#(
parameter C_NUM_INPUTS = 4,
parameter C_CLOG_NUM_INPUTS = 2,
parameter C_WIDTH = 32
)
(
input [(C_NUM_INPUTS)*C_WIDTH-1:0] MUX_INPUTS,
input [C_CLOG_NUM_INPUTS-1:0] MUX_SELECT,
output [C_WIDTH-1:0] MUX_OUTPUT
);
genvar i;
wire [C_WIDTH-1:0] wMuxInputs[C_NUM_INPUTS-1:0];
assign MUX_OUTPUT = wMuxInputs[MUX_SELECT];
generate
for (i = 0; i < C_NUM_INPUTS ; i = i + 1) begin : gen_muxInputs_array
assign wMuxInputs[i] = MUX_INPUTS[i*C_WIDTH +: C_WIDTH];
end
endgenerate
endmodule
module mux_shift
#(
parameter C_NUM_INPUTS = 4,
parameter C_CLOG_NUM_INPUTS = 2,
parameter C_WIDTH = 32
)
(
input [(C_NUM_INPUTS)*C_WIDTH-1:0] MUX_INPUTS,
input [C_CLOG_NUM_INPUTS-1:0] MUX_SELECT,
output [C_WIDTH-1:0] MUX_OUTPUT
);
genvar i;
wire [C_WIDTH*C_NUM_INPUTS-1:0] wMuxInputs;
assign wMuxInputs = MUX_INPUTS >> MUX_SELECT;
assign MUX_OUTPUT = wMuxInputs[C_WIDTH-1:0];
endmodule
|
#include <bits/stdc++.h> #pragma comment(linker, /stack:200000000 ) #pragma GCC optimize( Ofast ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,tune=native ) using namespace std; const long long MOD = 1000000007LL, INF = 1e9, LINF = 1e18; const long double PI = 3.141592653589793116, EPS = 1e-9, GOLD = ((1 + sqrt(5)) / 2); template <class T> int getbit(T s, int i) { return (s >> 1) & 1; } template <class T> T onbit(T s, int i) { return s | (T(1) << i); } template <class T> T offbit(T s, int i) { return s & (~(T(1) << i)); } template <class T> int cntbit(T s) { return __builtin_popcount(s); } string s; long long n; vector<long long> cc(26, 0); void VarInput() { ios_base::sync_with_stdio(0); cin.tie(NULL); cin >> s; n = s.size(); } void ProSolve() { for (long long i = 0; i < n; i++) cc[s[i] - a ]++; long long appear = 0, onlyOne = 0; for (long long i = 0; i < 26; i++) { if (cc[i] > 0) appear++; if (cc[i] == 1) onlyOne++; } if (appear > 4) { cout << No ; return; } if (appear < 2) { cout << No ; return; } if (appear == 2 && onlyOne > 0) { cout << No ; return; } if (appear == 3 && onlyOne > 2) { cout << No ; return; } cout << Yes ; } int main() { VarInput(); ProSolve(); } |
#include <bits/stdc++.h> using namespace std; using ll = long long; int n, a[100005], sta[100005]; vector<int> V; int calc(int k) { while (k) { int d = k % 10; k /= 10; if (d != 4 && d != 7) return 0; } return 1; } using pii = pair<int, int>; int tar[100005], to[100005]; vector<pii> Ans; void Swap(int first, int second) { if (first == second) return; to[tar[first]] = second, to[tar[second]] = first; swap(tar[second], tar[first]); Ans.push_back(pii(first, second)); return; } int main() { V.resize(1100800); for (auto first : V) first = rand(); scanf( %d , &n); int g = 0, pos = -1; vector<pii> vec; for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); sta[i] = calc(a[i]); g += sta[i]; if (sta[i]) pos = i; vec.push_back(pii(a[i], i)); } sort(vec.begin(), vec.end()); for (int i = 0; i < vec.size(); i++) { tar[vec[i].second] = i + 1; to[i + 1] = vec[i].second; } if (g == 0) { bool flag = 0; for (int i = 1; i < n; i++) if (a[i] > a[i + 1]) flag = 1; if (flag) puts( -1 ); else puts( 0 ); } else { assert(pos > 0); for (int i = 1; i <= n; i++) { Swap(pos, i); pos = i; int prv = to[i]; Swap(pos, to[i]); pos = prv; } int sz = Ans.size(); printf( %d n , sz); for (auto first : Ans) { printf( %d %d n , first.first, first.second); } } return 0; } |
#include <bits/stdc++.h> using namespace std; vector<string> split(const string& s, char c) { vector<string> v; stringstream ss(s); string x; while (getline(ss, x, c)) v.push_back(move(x)); return move(v); } void err(vector<string>::iterator it) {} template <typename T, typename... Args> void err(vector<string>::iterator it, T a, Args... args) { cerr << it->substr((*it)[0] == , it->length()) << = << a << n ; err(++it, args...); } int N, M; int X[5013]; pair<long long, int> H[5013]; long long dp[5013][5013]; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> N >> M; for (int i = 0; i < N; i++) { cin >> X[i]; } long long housing = 0; for (int i = 1; i <= M; i++) { cin >> H[i].first >> H[i].second; housing += H[i].second; } if (N > housing) { cout << -1 << endl; return 0; } sort(X, X + N); sort(H + 1, H + M + 1); for (int i = 0; i < N; i++) { dp[0][i] = 1123456789123456789LL; } for (int i = 1; i <= M; i++) { long long allin = 0; deque<pair<long long, int> > mpq; mpq.push_back({0, -1}); for (int j = 0; j < N; j++) { allin += abs(X[j] - H[i].first); long long diff = dp[i - 1][j] - allin; while (mpq.size() && diff <= mpq.back().first) { mpq.pop_back(); } mpq.push_back({diff, j}); while (j - mpq.front().second > H[i].second) { mpq.pop_front(); } dp[i][j] = allin + mpq.front().first; } } cout << dp[M][N - 1] << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m, two, one; cin >> n >> m; if (m < n - 1 || m > 2 * n + 2) cout << -1 ; else { if (m < n) { cout << 0 ; n--; } while (m > 0 || n > 0) { two = max(m - n - 1, 0); one = min(2 * n + 2, m); if (two) { cout << 11 ; m -= 2; two--; } else if (one) { cout << 1 ; m--; one--; } if (n) cout << 0 ; n--; } } return 0; } |
#include <bits/stdc++.h> using namespace std; const double eps = 1e-10, pi = acos(-1.0); int main() { int n, t = 1; while (t--) { double a, b, x, y, v; double ans = 1000000000.00; cin >> a >> b; cin >> n; for (int i = 0; i < n; i++) { cin >> x >> y >> v; double d = sqrt(((x - a) * (x - a)) + ((y - b) * (y - b))); ans = min(ans, d / v); } printf( %0.08lf n , ans); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 4e5 + 10, LOG = 20; int n, q, F[N], T[N], P[N], D[N], Par[LOG][N]; pair<int, int> Q[N]; vector<int> Adj[N], Ap[N], V[N << 2]; void Pre(int v) { for (int i = 1; i < LOG; i++) Par[i][v] = Par[i - 1][Par[i - 1][v]]; for (auto X : Adj[v]) if (X != Par[0][v]) Par[0][X] = v, D[X] = D[v] + 1, Pre(X); } int LCA(int v, int u) { if (D[v] < D[u]) return (LCA(u, v)); for (int i = 0; i < LOG; i++) if ((D[v] - D[u]) & (1 << i)) v = Par[i][v]; if (v == u) return (v); for (int i = LOG - 1; ~i; i--) if (Par[i][v] != Par[i][u]) v = Par[i][v], u = Par[i][u]; return (Par[0][v]); } int Dist(int v, int u) { return (D[v] + D[u] - 2 * D[LCA(v, u)]); } int Find(int v) { if (P[v] < 0) return (v); return (Find(P[v])); } void Add(int i, int le, int ri, int id = 1, int l = 0, int r = q + 2) { if (ri <= l || r <= le) return; if (le <= l && r <= ri) { V[id].push_back(i); return; } Add(i, le, ri, id * 2, l, (l + r) >> 1); Add(i, le, ri, id * 2 + 1, (l + r) >> 1, r); } void DFS(int id, int l = 0, int r = q + 2) { vector<pair<int, pair<int, int> > > Op; for (auto i : V[id]) if (Find(F[i]) != Find(T[i])) { int v = Find(F[i]), u = Find(T[i]); if (P[v] > P[u]) swap(v, u); Op.push_back({u, {v, P[u]}}); P[v] += P[u]; P[u] = v; } if (r - l == 1) if (Q[l].first > 0) { if (Find(Q[l].first) == Find(Q[l].second)) printf( %d n , Dist(Q[l].first, Q[l].second)); else puts( -1 ); } if (r - l > 1) DFS(id * 2, l, (l + r) >> 1), DFS(id * 2 + 1, (l + r) >> 1, r); reverse(Op.begin(), Op.end()); for (auto X : Op) P[X.first] = X.second.second, P[X.second.first] -= P[X.first]; } int main() { scanf( %d , &n); for (int i = 1; i < n; i++) scanf( %d%d , &F[i], &T[i]), Ap[i].push_back(0), Adj[F[i]].push_back(T[i]), Adj[T[i]].push_back(F[i]); scanf( %d , &q); int tp, v, u; for (int i = 1; i <= q; i++) { scanf( %d%d , &tp, &v); if (tp < 3) Ap[v].push_back(i); else scanf( %d , &u), Q[i] = {v, u}; } for (int i = 1; i < n; i++) { Ap[i].push_back(q + 1); for (int j = 1; j < Ap[i].size(); j += 2) Add(i, Ap[i][j - 1], Ap[i][j]); } memset(P, -1, sizeof(P)); Pre(1); DFS(1); return (0); } |
#include <bits/stdc++.h> using namespace std; set<long long> s; map<long long, long long> m; vector<long long> v; long long n, a[100010], b[100010], dp[100010], mx = 0; bool mark[100010]; int main() { ios_base::sync_with_stdio(false); cin >> n; for (long long i = 1; i <= n; i++) { cin >> a[i]; if (i == 1) dp[i] = a[i]; else dp[i] = dp[i - 1] + a[i]; } for (long long i = 1; i <= n; i++) cin >> b[i]; for (long long i = n; i > 0; i--) { v.push_back(mx); long long r, l; mark[b[i]] = 1; if (b[i] < n) { if (mark[b[i] + 1] == 1) { set<long long>::iterator it = s.lower_bound(b[i]); r = *it; } else r = b[i]; } else r = b[i]; s.insert(r); if (b[i] > 1) { if (mark[b[i] - 1] == 1) { s.erase(b[i] - 1); } } m[r] = m[b[i] - 1] + dp[r] - dp[b[i] - 1]; if (m[r] > mx) mx = m[r]; } for (long long i = v.size() - 1; i >= 0; i--) cout << v[i] << endl; return 0; } |
#include <iostream> int main(void) { int count; std::cin >> count; for (int i = 0; i < count; ++i) { int number; std::cin >> number; int64_t sum = 0; for (int j = 0; j < number; ++j) { int part; std::cin >> part; sum += part; } std::cout << (sum % number) * (number - sum % number) << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int Inf = 1e9 + 7; int dp[107][107]; int par[107][107]; string t = .,!? ; bool check(char c) { return t.find(c) == string::npos; } void solve() { int t; cin >> t; for (int k = 0; k < t; k++) { int n; cin >> n; vector<string> users; for (int i = 0; i < n; i++) { string p; cin >> p; users.push_back(p); } sort(users.begin(), users.end()); map<string, int> id; for (int i = 0; i < n; i++) id[users[i]] = i; memset(dp, 0, sizeof(dp)); for (int i = 0; i < n; i++) dp[0][i] = 1; memset(par, -1, sizeof(par)); int m; cin >> m; string buf; getline(cin, buf); vector<string> message; for (int i = 0; i < m; i++) { string buf; getline(cin, buf); int pos = buf.find( : ); string user = buf.substr(0, pos); string msg = buf.substr(pos + 1); message.push_back(msg); vector<string> w; int p = 0, l = msg.size(); while (p < l) { while (p < l && !check(msg[p])) p++; int q = p; while (q < l && check(msg[q])) q++; string word = msg.substr(p, q - p); if (word != ) w.push_back(word); p = q; } int uid = id.count(user) == 0 ? -1 : id[user]; if (uid == -1) { for (int j = 0; j < n; j++) { if (find(w.begin(), w.end(), users[j]) != w.end()) continue; for (int jj = 0; jj < n; jj++) { if (dp[i][jj] == 1 && (i == 0 || j != jj)) { dp[i + 1][j] = 1; par[i + 1][j] = jj; } } } } else { for (int jj = 0; jj < n; jj++) { if (dp[i][jj] == 1 && (i == 0 || uid != jj)) { dp[i + 1][uid] = 1; par[i + 1][uid] = jj; } } } } vector<string> res; for (int i = 0; i < n; i++) if (dp[m][i] == 1) { int p = i, q = m; while (q > 0) { res.push_back(users[p]); p = par[q][p]; q--; } } if (res.empty()) { cout << Impossible << n ; } else { reverse(message.begin(), message.end()); for (int i = m - 1; i >= 0; --i) { ostringstream oss; oss << res[i]; oss << : ; oss << message[i]; cout << oss.str() << n ; } } } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cout.precision(9); cout << fixed; solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long fuck = 4e17; long long n, arr[100010]; vector<long long> ans; bool chk(long long x) { vector<int> diffs; for (int i = 0; i + 1 < n; i++) { long long next = arr[i + 1]; if (arr[i] <= x) next = min(arr[i + 1], x); long long d = next - arr[i]; if (diffs.size() == 0) diffs.push_back(d); else if (diffs[0] != d) return false; } return true; } int main() { scanf( %lld , &n); for (int i = 0; i < n; i++) scanf( %lld , &arr[i]); sort(arr, arr + n); if (n == 1) { printf( -1 ); return 0; } if (n == 2) { long long d = arr[1] - arr[0]; ans.push_back(arr[0] - d); ans.push_back(arr[1] + d); if (!(d & 1)) ans.push_back(arr[1] - d / 2); } else { long long prev = arr[1] - arr[0], another = fuck, pos; for (int i = 2; i < n; i++) { long long d = arr[i] - arr[i - 1]; if (d != prev && d != another && another != fuck) { printf( 0 ); return 0; } if (d != prev) { pos = i; another = arr[i] - arr[i - 1]; } } if (another == fuck) { ans.push_back(arr[0] - prev); ans.push_back(arr[n - 1] + prev); } else { if (prev == 2ll * another) ans.push_back(arr[1] - another); else if (another == prev * 2ll) ans.push_back(arr[pos] - prev); } } set<long long> res; for (int i = 0; i < ans.size(); i++) if (chk(ans[i])) res.insert(ans[i]); printf( %d n , res.size()); for (set<long long>::iterator it = res.begin(); it != res.end(); it++) printf( %lld , *it); return 0; } |
`timescale 1ns / 1ps
/*
-- Module Name: West First Minimal
-- Description: Algoritmo parcialmente adaptativo para el calculo de
de ruta en NoCs con topologia Mesh.
El algoritmo esta basado en el "Turn Model". Se puede
encontrar mas informacion en:
The turn model for adaptive routing
Christopher J. Glass
Lionel M. Ni
ProceedingsISCA '92 Proceedings of the 19th annual
international symposium on Computer architecture
Pages 278-287
Forma parte del modulo "Link Controller".
-- Dependencies: -- system.vh
-- Parameters: -- PORT_DIR: Direccion del puerto de entrada
conectado a este modulo {x+, y+
x-, y-}.
-- X_LOCAL: Direccion en dimension "x" del nodo
en la red.
-- Y_LOCAL: Direccion en dimension "y" del nodo
en la red.
-- Original Author: Héctor Cabrera
-- Current Author:
-- Notas:
(05/06/2015): Esta es una implementacion modificada del algoritmo
WF. Require modificarse para pasar la alteracion al
modulo wrapper (route_planner.v)
-- History:
-- Creacion 05 de Junio 2015
*/
`include "system.vh"
module dor_xy #(
parameter PORT_DIR = `X_POS,
parameter X_LOCAL = 2,
parameter Y_LOCAL = 2
)
(
// -- inputs --------------------------------------------- >>>>>
input wire done_field_din,
input wire [`ADDR_FIELD-1:0] x_field_din,
input wire [`ADDR_FIELD-1:0] y_field_din,
// -- outputs -------------------------------------------- >>>>>
output reg [3:0] valid_channels_dout
);
/*
-- Calculo de diferencia entre la direccion del nodo actual con la
direccion del nodo objetivo.
Banderas zero_x y zero_y indican que la diferencia es "0" en sus
respectivas dimensiones.
Banderas Xoffset y Yoffset el resultado de la diferencia entre la
direccion actual y la objetivo. Puede ser positiva o negativa.
*/
// -- Dimension X -------------------------------------------- >>>>>
wire Xoffset;
wire zero_x;
assign Xoffset = (x_field_din > X_LOCAL) ? 1'b1 : 1'b0;
assign zero_x = (x_field_din == X_LOCAL) ? 1'b1 : 1'b0;
// -- Dimension Y -------------------------------------------- >>>>>
wire Yoffset;
wire zero_y;
assign Yoffset = (y_field_din > Y_LOCAL) ? 1'b1 : 1'b0;
assign zero_y = (y_field_din == Y_LOCAL) ? 1'b1 : 1'b0;
/*
-- En base a la diferencia de la direccion actual y objetivo, se
selecciona las direcciones de salida que acercan al paquete a su
destino.
Existen 4 casos dependiendo del puerto de entrada ligado al
planificador de ruta. El caso activo se determina con el parametro
PORT_DIR. Solo las asignaciones del caso activo se toman
encuenta al momento de la sintesis.
Para detalles sobre la toma de desiciones del algoritmo consultar el
el paper citado en la cabecera de este archivo.
*/
// -- Seleccion de puertos de salida productivos ----------------- >>>>>
always @(*)
// -- Route Planner :: LC | PE ------------------------------- >>>>>
if (PORT_DIR == `PE)
begin
valid_channels_dout [`PE_YPOS] = (Yoffset) ? 1'b1 : 1'b0;
valid_channels_dout [`PE_YNEG] = (~Yoffset) ? 1'b1 : 1'b0;
valid_channels_dout [`PE_XPOS] = (zero_y & Xoffset) ? 1'b1 : 1'b0;
valid_channels_dout [`PE_XNEG] = (zero_y & ~Xoffset) ? 1'b1 : 1'b0;
end
// -- Route Planner :: LC | X+ ------------------------------- >>>>>
else if(PORT_DIR == `X_POS)
begin
valid_channels_dout [`XPOS_PE] = ~done_field_din;
valid_channels_dout [`XPOS_YPOS] = (Yoffset) ? 1'b1 : 1'b0;
valid_channels_dout [`XPOS_YNEG] = (~Yoffset) ? 1'b1 : 1'b0;
valid_channels_dout [`XPOS_XNEG] = (zero_y & ~Xoffset) ? 1'b1 : 1'b0;
end
// -- Route Planner :: LC | Y+ ------------------------------- >>>>>
else if(PORT_DIR == `Y_POS)
begin
valid_channels_dout [`YPOS_PE] = ~done_field_din;
valid_channels_dout [`YPOS_YNEG] = (~Yoffset) ? 1'b1 : 1'b0;
valid_channels_dout [`YPOS_XPOS] = (zero_y & Xoffset) ? 1'b1 : 1'b0;
valid_channels_dout [`YPOS_XNEG] = (zero_y & ~Xoffset) ? 1'b1 : 1'b0;
end
// -- Route Planner :: LC | X- ------------------------------- >>>>>
else if(PORT_DIR == `X_NEG)
begin
valid_channels_dout [`XNEG_PE] = ~done_field_din;
valid_channels_dout [`XNEG_YPOS] = (Yoffset) ? 1'b1 : 1'b0;
valid_channels_dout [`XNEG_YNEG] = (~Yoffset) ? 1'b1 : 1'b0;
valid_channels_dout [`XNEG_XPOS] = (zero_y & ~Xoffset) ? 1'b1 : 1'b0;
end
// -- Route Planner :: LC | Y- ------------------------------- >>>>>
else if(PORT_DIR == `Y_NEG)
begin
valid_channels_dout [`YNEG_PE] = ~done_field_din;
valid_channels_dout [`YNEG_YPOS] = (Yoffset) ? 1'b1 : 1'b0;
valid_channels_dout [`YNEG_XPOS] = (Yoffset) ? 1'b1 : 1'b0;
valid_channels_dout [`YNEG_XNEG] = (~Yoffset) ? 1'b1 : 1'b0;
end
endmodule // west_first_minimal
/* -- Plantilla de Instancia ------------------------------------- >>>>>
wire [3:0] valid_channels;
mdor_yx
#( .PORT_DIR (PORT_DIR),
.X_LOCAL (X_LOCAL),
.Y_LOCAL (Y_LOCAL)
)
dor_yx
(
// -- inputs --------------------------------------------- >>>>>
.done_field_din (done_field_din),
.x_field_din (x_field_din),
.y_field_din (y_field_din),
// -- outputs -------------------------------------------- >>>>>
.valid_channels_dout (valid_channels)
);
*/ |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__OR3_PP_BLACKBOX_V
`define SKY130_FD_SC_HVL__OR3_PP_BLACKBOX_V
/**
* or3: 3-input OR.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__or3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__OR3_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; using ll = long long; const int N = 3e6 + 44; const int X[] = {1, 0, -1, 0, 1, -1, 1, -1}; const int Y[] = {0, 1, 0, -1, 1, 1, -1, -1}; const int mod = 998244353; const int INF = 1e9; ll ans[N], add[N]; vector<int> g[N]; vector<pair<int, int> > query[N]; void dfs(int v = 0, int p = -1, int h = 0, ll sum = 0) { for (auto pairr : query[v]) { int d = pairr.first, x = pairr.second; add[h] += x; if (h + d + 1 < N) add[h + d + 1] -= x; } sum += add[h]; ans[v] = sum; for (int to : g[v]) if (to != p) { dfs(to, v, h + 1, sum); } for (auto pairr : query[v]) { int d = pairr.first, x = pairr.second; add[h] -= x; if (h + d + 1 < N) add[h + d + 1] += x; } } int main() { ios_base::sync_with_stdio(false), cin.tie(NULL); ; int n; cin >> n; for (int i = 1; i < n; ++i) { int u, v; cin >> u >> v; u--, v--; g[u].push_back(v); g[v].push_back(u); } int m; cin >> m; for (int i = 0; i < m; ++i) { int v, d, x; cin >> v >> d >> x; v--; query[v].push_back({d, x}); } dfs(); for (int i = 0; i < n; ++i) cout << ans[i] << ; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 100 + 10; string a[maxn], ans[maxn]; int main() { int n; while (cin >> n) { int cnt[2][26]; memset(cnt, 0, sizeof cnt); for (int i = 0; i < n; ++i) cin >> a[i], ++cnt[0][a[i][0] - A ]; multiset<string> Q; for (int i = 0; i < n; ++i) { string x; cin >> x; ++cnt[1][x[0] - A ]; Q.insert(x); } sort(a, a + n); int cur = 0; for (int i = 0; i < n; ++i) { string& t = a[i]; int id = t[0] - A ; for (multiset<string>::iterator it = Q.begin(); it != Q.end(); ++it) { const string& now = *it; int idx = now[0] - A ; if (now[0] == t[0]) { ans[cur++] = t + + now; --cnt[0][id]; --cnt[1][idx]; Q.erase(it); break; } else if (cnt[0][idx] < cnt[1][idx] && cnt[0][id] > cnt[1][id]) { ans[cur++] = t + + now; --cnt[0][id]; --cnt[1][idx]; Q.erase(it); break; } } } sort(ans, ans + cur); cout << ans[0]; for (int i = 1; i < cur; ++i) { cout << , << ans[i]; } cout << endl; } return 0; } |
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_nios2_gen2_0_cpu_debug_slave_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
#include <bits/stdc++.h> long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } inline long long qmul(long long a, long long b, long long m) { long long res = 0; while (b) { if (b & 1) res = (res + a) % m; a = (a << 1) % m; b = b >> 1; } return res; } inline long long qpow(long long a, long long b, long long m) { long long res = 1; while (b) { if (b & 1) res = (res * a) % m; a = (a * a) % m; b = b >> 1; } return res; } inline long long inv(long long x, long long q) { return qpow(x, q - 2, q); } using namespace std; const int N = 3e5 + 10; const double eps = 1e5; int arr[N]; int main() { std::ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; for (int i = 1; i <= n; i++) { cin >> arr[2 * i - 1]; cin >> arr[2 * i]; } int k; cin >> k; k--; int pos = upper_bound(arr + 1, arr + 2 * n + 1, k) - arr; cout << n - (pos - 1) / 2; } |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2017 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2018.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Bi-Directional IO
// /___/ /\ Filename : BIBUF.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module BIBUF
`ifdef XIL_TIMING
#(
parameter LOC = "UNPLACED"
)
`endif
(
inout IO,
inout PAD
);
// define constants
localparam MODULE_NAME = "BIBUF";
tri0 glblGSR = glbl.GSR;
// begin behavioral model
wire PAD_io;
wire IO_io;
assign #10 PAD_io = PAD;
assign #10 IO_io = IO;
assign (weak1, weak0) IO = PAD_io;
assign (weak1, weak0) PAD = IO_io;
// end behavioral model
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n; cin >> n; int a[n]; map<int, int> mp; for (int i = 0; i < n; i++) { cin >> a[i]; mp[a[i]]++; } long long ans = 0; for (int i = 0; i < n; i++) { for (int j = 0; j < 32; j++) { int p = 1 << j; if (p < a[i]) { continue; } ans += mp[p - a[i]]; if (a[i] == p - a[i]) { ans--; } } } ans /= 2; cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T> using maxpq = priority_queue<T, vector<T>, greater<T>>; template <typename T> using minpq = priority_queue<T>; int n, TOT; string a[305]; int HASH[305], len[305], p[100005]; inline int add(int a, int b) { long long c = a + b; if (c >= 1000000007) c -= 1000000007; return c; } inline int sub(int a, int b) { int c = a - b; if (c < 0) c += 1000000007; return c; } inline int mul(int a, int b) { return (a * 1ll * b) % 1000000007; } int power(int a, int b, int m = 1000000007) { int res = 1; while (b > 0) { if (b & 1) res = mul(res, a); a = mul(a, a); b >>= 1; } return res; } inline int Fermat(int a, int p = 1000000007) { return power(a, p - 2, p); } inline int Div(int a, int b) { return mul(a, Fermat(b)); } int base = 128; inline int h(char c) { return c; } inline int hsh(string s) { int t = 0; for (int i = (0); i < (s.size()); i++) { t = mul(t, base); t = add(t, h(s[i])); } return t; } int ans = 0; vector<pair<int, int>> adj[305]; void pre() { p[0] = 1; for (int i = (1); i < (100005); i++) { p[i] = mul(p[i - 1], base); } } void solve() { for (int l = (1); l < (n + 1); l++) { for (int i = (0); i < (n - l + 1); i++) { int j = i + l - 1; int t = HASH[i], tot = len[i]; for (int k = (i + 1); k < (j + 1); k++) { t = mul(t, p[len[k] + 1]); t = add(t, mul(h( ), p[len[k]])); t = add(t, HASH[k]); tot = tot + len[k] + 1; } adj[l].push_back({t, tot}); } } for (int l = (1); l < (n); l++) { for (int i = (0); i < (n - l + 1); i++) { bool b = 0; int tmp = TOT; for (int j = (i + l); j < (n - l + 1); j++) { if (adj[l][i].first != adj[l][j].first || adj[l][j].second != adj[l][j].second) continue; tmp += -adj[l][i].second + l; if (b == 0) b = 1, tmp += -adj[l][i].second + l; j += l - 1; } ans = min(ans, tmp); } } } int main() { clock_t clk = clock(); cerr << I will return... n ; cin >> n; for (int i = (0); i < (n); i++) cin >> a[i], len[i] = a[i].size(), TOT += len[i], HASH[i] = hsh(a[i]); TOT += n - 1; ans = TOT; pre(); solve(); cout << ans << n ; cerr << ...don t you ever hang your head. n ; cerr << Time (in ms): << double(clock() - clk) * 1000.0 / CLOCKS_PER_SEC << n ; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 3e5 + 5; const int MAXM = 2e6 + 5; char s[MAXN]; vector<int> v[MAXN]; multiset<int> ss[MAXN]; int trie[MAXN][26], fail[MAXN]; int pos[MAXN], dat[MAXN], siz[MAXN]; int fa[MAXN], dep[MAXN], top[MAXN], dfn[MAXN]; int rev[MAXN], son[MAXN], dfn_cnt, root, tree_cnt, tot; int ls[MAXM], rs[MAXM], val[MAXM]; inline int read() { int x = 0; char ch = getchar(); while (!isdigit(ch)) ch = getchar(); while (isdigit(ch)) { x = x * 10 + ch - 0 ; ch = getchar(); } return x; } inline void Max(int &x, int y) { if (x < y) x = y; } inline void insert(char *s, int id) { int len = strlen(s + 1), cur = 0; for (int i = 1; i <= len; i++) { int ch = s[i] - a ; if (!trie[cur][ch]) trie[cur][ch] = ++tot; cur = trie[cur][ch]; } pos[id] = cur, ss[cur].insert(dat[id]); } inline void build(int x = 0) { queue<int> q; for (int i = 0; i < 26; i++) if (trie[0][i]) q.push(trie[0][i]), v[0].push_back(trie[0][i]); while (!q.empty()) { x = q.front(), q.pop(); for (int i = 0; i < 26; i++) { int y = trie[x][i]; if (y) { fail[y] = trie[fail[x]][i]; v[fail[y]].push_back(y), q.push(y); } else trie[x][i] = trie[fail[x]][i]; } } } void dfs_son(int x, int fath) { siz[x] = 1; fa[x] = fath; dep[x] = dep[fath] + 1; for (auto y : v[x]) { dfs_son(y, x), siz[x] += siz[y]; if (son[x] || siz[y] > siz[son[x]]) son[x] = y; } } void dfs_chain(int x, int tp) { top[x] = tp; rev[dfn[x] = ++dfn_cnt] = x; if (son[x]) dfs_chain(son[x], tp); for (auto y : v[x]) { if (y == son[x]) continue; dfs_chain(y, y); } } inline void pushup(int cur) { val[cur] = max(val[ls[cur]], val[rs[cur]]); } void build(int l, int r, int &cur) { cur = ++tree_cnt; if (l == r) { val[cur] = *--ss[rev[l]].end(); return; } int mid = (l + r) >> 1; build(l, mid, ls[cur]); build(mid + 1, r, rs[cur]); pushup(cur); } void modify(int l, int r, int pos, int to, int cur) { if (l == r) return val[cur] = to, void(); int mid = (l + r) >> 1; if (pos <= mid) modify(l, mid, pos, to, ls[cur]); else modify(mid + 1, r, pos, to, rs[cur]); pushup(cur); } int query(int l, int r, int ql, int qr, int cur) { if (ql <= l && qr >= r) return val[cur]; int mid = (l + r) >> 1; if (ql > mid) return query(mid + 1, r, ql, qr, rs[cur]); if (qr <= mid) return query(l, mid, ql, qr, ls[cur]); return max(query(l, mid, ql, qr, ls[cur]), query(mid + 1, r, ql, qr, rs[cur])); } inline int query(int x) { int ans = -1; while (top[x]) { Max(ans, query(1, dfn_cnt, dfn[top[x]], dfn[x], root)); x = fa[top[x]]; } return max(ans, query(1, dfn_cnt, 1, dfn[x], root)); } inline int query(char *s) { int len = strlen(s + 1), cur = 0, ans = -1; for (int i = 1; i <= len; i++) { int ch = s[i] - a ; cur = trie[cur][ch]; Max(ans, query(cur)); } return ans; } int main() { int n = read(), m = read(); for (int i = 1; i <= n; i++) { scanf( %s , s + 1); insert(s, i); } for (int i = 0; i <= tot; i++) ss[i].insert(-1); build(); dfs_son(0, 0); dfs_chain(0, 0); build(1, dfn_cnt, root); while (m--) { int opt = read(); if (opt == 1) { int id = read(), x = read(); ss[pos[id]].erase(ss[pos[id]].find(dat[id])); ss[pos[id]].insert(dat[id] = x); modify(1, dfn_cnt, dfn[pos[id]], *--ss[pos[id]].end(), root); } else { scanf( %s , s + 1); printf( %d n , query(s)); } } return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Thu Oct 26 22:45:01 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/RATCPU/Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_Mux4x1_10_0_0/RAT_Mux4x1_10_0_0_stub.v
// Design : RAT_Mux4x1_10_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "Mux4x1_10,Vivado 2016.4" *)
module RAT_Mux4x1_10_0_0(A, B, C, D, SEL, X)
/* synthesis syn_black_box black_box_pad_pin="A[9:0],B[9:0],C[9:0],D[9:0],SEL[1:0],X[9:0]" */;
input [9:0]A;
input [9:0]B;
input [9:0]C;
input [9:0]D;
input [1:0]SEL;
output [9:0]X;
endmodule
|
#include <bits/stdc++.h> using namespace std; struct query { long long l, r, x; }; int n, a[109]; long long m; int main() { cin >> n >> m; vector<query> v; vector<long long> cp = {1LL << 60}; for (int i = 0; i < n; i++) { cin >> a[i]; int pr = sqrt(a[i]); for (int j = 1; j < pr; j++) { v.push_back(query{j, j + 1, (a[i] + j - 1) / j}); cp.push_back(j); } cp.push_back(pr); int r = (a[i] + pr - 1) / pr, ptr = pr; for (int j = r; j > 1; j--) { v.push_back(query{ptr, (a[i] + j - 2) / (j - 1), j}); ptr = v.back().r; cp.push_back(ptr); } v.push_back(query{ptr, 1LL << (59 + 1), 1}); } sort(cp.begin(), cp.end()); cp.erase(unique(cp.begin(), cp.end()), cp.end()); vector<long long> sum(cp.size()); for (query i : v) { int pl = lower_bound(cp.begin(), cp.end(), i.l) - cp.begin(); int pr = lower_bound(cp.begin(), cp.end(), i.r) - cp.begin(); sum[pl] += i.x; sum[pr] -= i.x; } for (int i = 1; i < cp.size(); i++) sum[i] += sum[i - 1]; long long ret = 0; for (int i = 0; i < cp.size() - 1; i++) { long long r = min(cp[i + 1] - 1, (m + sum[0]) / sum[i]); if (cp[i] <= r) ret = max(ret, r); } cout << ret << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; bool Check(int N, int pos) { return (bool)(N & (1 << pos)); } int Set(int N, int pos) { return (N | (1 << pos)); } long long BigMod(long long B, long long P, long long M) { long long R = 1; while (P > 0) { if (P % 2 == 1) { R = (R * B) % M; } P /= 2; B = (B * B) % M; } return R; } int n, m; vector<pair<double, int> > v; int dp[5005][5005][2]; inline int call(int pos, int got, int stat) { if (got > m) return 10000; if (pos == n) { if (got == m) return 0; else return 10000; } if (dp[pos][got][stat] != -1) return dp[pos][got][stat]; int ret = 0; int g = 0; if (v[pos].second != got and stat == 0) g = 1; ret = min(call(pos + 1, got, 0), call(pos, got + 1, 1)); return dp[pos][got][stat] = ret + g; } int main() { ios_base::sync_with_stdio(0); cin.tie(nullptr); memset(dp, -1, sizeof(dp)); cin >> n >> m; v.resize(n); for (int i = 0; i < n; i++) { cin >> v[i].second >> v[i].first; } sort(v.begin(), v.end()); int mx = 10000; for (int i = 0; i < m; i++) { mx = min(mx, call(0, i + 1, 0)); } cout << mx; } |
//------------------------------------------------------------------------------
// YF32 -- A small SOC implementation based on mlite (32-bit RISC CPU)
// @Taiwan
//------------------------------------------------------------------------------
//
// YF32 - A SOC implementation based on verilog ported mlite (32-bit RISC CPU)
// Copyright (C) 2003-2004 Yung-Fu Chen ()
//
//------------------------------------------------------------------------------
// FETURE
// . verilog ported mlite included
// . wishbone bus support
// . simple_pic (programmable interrupt controller)
// . most MIPS-I(TM) opcode support
// . do not support excption
// . do not support "unaligned memory accesses"
// . only user mode support
// . 32K byte ROM
// . 2K byte SRAM
// . UART/Timer are not fully tested yet
// . no internal tri-state bus
// TO DO
// . integrate UART
// . integrate LCD/VGA Controller
// . integrete PS/2 interface
//
//------------------------------------------------------------------------------
// Note:
// MIPS(R) is a registered trademark and MIPS I(TM) is a trademark of
// MIPS Technologies, Inc. in the United States and other countries.
// MIPS Technologies, Inc. does not endorse and is not associated with
// this project. OpenCores and Steve Rhoads are not affiliated in any way
// with MIPS Technologies, Inc.
//------------------------------------------------------------------------------
//
// FILE: reg_bank.v (tranlate from reg_bank.vhd from opencores.org)
//
// Vertsion: 1.0
//
// Date: 2004/03/22
//
// Author: Yung-Fu Chen ()
//
// MODIFICATION HISTORY:
// Date By Version Change Description
//============================================================
// 2004/03/22 yfchen 1.0 Translate from reg_bank.vhd
//------------------------------------------------------------------------------
//-------------------------------------------------------------------
// TITLE: Register Bank
// AUTHOR: Steve Rhoads ()
// DATE CREATED: 2/2/01
// FILENAME: reg_bank.vhd
// PROJECT: Plasma CPU core
// COPYRIGHT: Software placed into the public domain by the author.
// Software 'as is' without warranty. Author liable for nothing.
// DESCRIPTION:
// Implements a register bank with 32 registers that are 32-bits wide.
// There are two read-ports and one write port.
//-------------------------------------------------------------------
module reg_bank (clk, reset, pause, rs_index, rt_index, rd_index,
reg_source_out, reg_target_out, reg_dest_new, intr_enable);
input clk;
input reset;
input pause;
input [ 5:0] rs_index;
input [ 5:0] rt_index;
input [ 5:0] rd_index;
input [31:0] reg_dest_new;
output [31:0] reg_source_out;
output [31:0] reg_target_out;
output intr_enable;
reg [31:0] reg_target_out;
reg [31:0] reg_source_out;
reg intr_enable_reg;
wire intr_enable = intr_enable_reg ;
//controls access to dual-port memories
reg [ 4:0] addr_a1;
wire [ 4:0] addr_a2 = rt_index[4:0] ;
reg [ 4:0] addr_b;
reg write_enable;
wire [31:0] data_out1;
wire [31:0] data_out2;
always @(posedge clk or posedge reset) begin
if (reset)
intr_enable_reg <= 1'b0;
else
if (rd_index == 6'b101110)
//reg_epc CP0 14
intr_enable_reg <= 1'b0 ; //disable interrupts
else if (rd_index == 6'b101100)
intr_enable_reg <= reg_dest_new[0];
end
always @(rs_index or intr_enable_reg or data_out1 or rt_index or data_out2 or
rd_index or pause)
begin
//setup for first dual-port memory
if (rs_index == 6'b101110)
//reg_epc CP0 14
addr_a1 = 5'b00000;
else
addr_a1 = rs_index[4:0];
case (rs_index)
6'b000000 : reg_source_out = `ZERO;
6'b101100 : reg_source_out = {31'b0, intr_enable_reg};
6'b111111 : //interrupt vector address = 0x3c
reg_source_out = `INTERRUPT_VECTOR; //{24'b0, 8'b00111100};
default : reg_source_out = data_out1;
endcase
//setup for second dual-port memory
case (rt_index)
6'b000000 : reg_target_out = `ZERO;
default : reg_target_out = data_out2;
endcase
//setup second port (write port) for both dual-port memories
if (rd_index != 6'b000000 & rd_index != 6'b101100 & ~pause)
write_enable = 1'b1 ;
else
write_enable = 1'b0 ;
if (rd_index == 6'b101110)
//reg_epc CP0 14
addr_b = 5'b00000 ;
else
addr_b = rd_index[4:0] ;
end
//------------------------------------------------------------
//-- Pick only ONE of the dual-port RAM implementations below!
//------------------------------------------------------------
`ifdef reg_mem_type_TRI_PORT_MEM
// Option #1
// One tri-port RAM, two read-ports, one write-port
// 32 registers 32-bits wide
reg[31:0] tri_port_ram[31:0];
assign data_out1 = tri_port_ram[addr_a1];
assign data_out2 = tri_port_ram[addr_a2];
always @(posedge clk)
if (write_enable) tri_port_ram[addr_b] = reg_dest_new;
`endif //tri_port_mem
`ifdef reg_mem_type_DUAL_PORT_MEM
// Option #2
// Two dual-port RAMs, each with one read-port and one write-port
// According to the Xilinx answers database record #4075 this
// architecture may cause Synplify to infer synchronous dual-port
// RAM using RAM16x1D.
reg[31:0] dual_port_ram1[31:0];
reg[31:0] dual_port_ram2[31:0];
always @(addr_a1 or addr_a2 or dual_port_ram1) begin
data_out1 <= dual_port_ram1[addr_a1];
data_out2 <= dual_port_ram2[addr_a2];
end
always @(posedge clk) begin
if (write_enable) begin
dual_port_ram1[addr_b] = reg_dest_new;
dual_port_ram2[addr_b] = reg_dest_new;
end
end
`endif //dual_port_mem
`ifdef reg_mem_type_ALTERA_MEM
fpga_reg_bank fpga_reg_bank_inst (
.data ( reg_dest_new ),
.wraddress ( addr_b ),
.rdaddress_a ( addr_a1 ),
.rdaddress_b ( addr_a2 ),
.wren ( write_enable & clk ),
.qa ( data_out1 ),
.qb ( data_out2 )
);
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; bool cutPaper(int n, int x, int y) { int count = 1; while ( x % 2 == 0 || y % 2 == 0 ) { if ( x % 2 == 0 ){ x /= 2; count *= 2; }else if ( y % 2 == 0 ) { y /= 2; count *= 2; } if ( count >= n ) return true; } if ( count >= n ) return true; return false; } int main() { int t; cin >> t; while (t-- > 0) { int n, x, y; cin >> x >> y >> n; if (cutPaper(n, x, y)) { cout << YES << endl; } else { cout << NO << endl; } } } |
#include <bits/stdc++.h> using namespace std; int main() { int n; while (~scanf( %d , &n)) { int cnt = 1; while (n != 1) { if (n % 2 != 0) cnt++; n /= 2; } printf( %d n , cnt); } return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
parameter PAR = 3;
input clk;
`ifdef verilator
// Else it becomes a localparam, per IEEE 4.10.1, but we don't check it
defparam m3.FROMDEFP = 19;
`endif
m3 #(.P3(PAR),
.P2(2))
m3(.clk(clk));
integer cyc=1;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==1) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module m3
#(
parameter UNCH = 99,
parameter P1 = 10,
parameter P2 = 20,
P3 = 30
)
(/*AUTOARG*/
// Inputs
clk
);
input clk;
localparam LOC = 13;
parameter FROMDEFP = 11;
initial begin
$display("%x %x %x",P1,P2,P3);
end
always @ (posedge clk) begin
if (UNCH !== 99) $stop;
if (P1 !== 10) $stop;
if (P2 !== 2) $stop;
if (P3 !== 3) $stop;
`ifdef verilator
if (FROMDEFP !== 19) $stop;
`endif
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct Point { int x, y; Point(int x = 0, int y = 0) : x(x), y(y) {} Point operator-(const Point z) const { return Point(x - z.x, y - z.y); } friend long long Cross(Point a, Point b) { return 1ll * a.x * b.y - 1ll * a.y * b.x; } } a[2010], b[2010]; bool f[2010]; char ch[2010]; int main(int argc, char const *argv[]) { int n; cin >> n; for (int i = 0; i < n; i++) cin >> a[i].x >> a[i].y; cin >> ch; int p = 0; for (int i = 1; i < n; i++) if (a[i].y < a[p].y || a[i].y == a[p].y && a[i].x < a[p].x) p = i; f[p] = 1; cout << p + 1 << ; for (int i = 0; !i || ch[i - 1]; i++) { int x = -1; for (int j = 0; j < n; j++) if (!f[j]) { if (x == -1) x = j; else if (ch[i] == L ) if (Cross(a[j] - a[p], a[x] - a[p]) > 0) x = j; else ; else if (Cross(a[j] - a[p], a[x] - a[p]) < 0) x = j; } cout << x + 1 << ; f[x] = 1; p = x; } return 0; } |
/* ****************************************************************************
This Source Code Form is subject to the terms of the
Open Hardware Description License, v. 1.0. If a copy
of the OHDL was not distributed with this file, You
can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
Description: mor1kx PIC
Copyright (C) 2012 Authors
Author(s): Julius Baxter <>
***************************************************************************** */
`include "mor1kx-defines.v"
module mor1kx_pic
(/*AUTOARG*/
// Outputs
spr_picmr_o, spr_picsr_o, spr_bus_ack, spr_dat_o,
// Inputs
clk, rst, irq_i, spr_access_i, spr_we_i, spr_addr_i, spr_dat_i
);
parameter OPTION_PIC_TRIGGER="LEVEL";
parameter OPTION_PIC_NMI_WIDTH = 0;
input clk;
input rst;
input [31:0] irq_i;
output [31:0] spr_picmr_o;
output [31:0] spr_picsr_o;
// SPR Bus interface
input spr_access_i;
input spr_we_i;
input [15:0] spr_addr_i;
input [31:0] spr_dat_i;
output spr_bus_ack;
output [31:0] spr_dat_o;
// Registers
reg [31:0] spr_picmr;
reg [31:0] spr_picsr;
wire spr_picmr_access;
wire spr_picsr_access;
wire [31:0] irq_unmasked;
assign spr_picmr_o = spr_picmr;
assign spr_picsr_o = spr_picsr;
assign spr_picmr_access =
spr_access_i &
(`SPR_OFFSET(spr_addr_i) == `SPR_OFFSET(`OR1K_SPR_PICMR_ADDR));
assign spr_picsr_access =
spr_access_i &
(`SPR_OFFSET(spr_addr_i) == `SPR_OFFSET(`OR1K_SPR_PICSR_ADDR));
assign spr_bus_ack = spr_access_i;
assign spr_dat_o = (spr_access_i & spr_picsr_access) ? spr_picsr :
(spr_access_i & spr_picmr_access) ? spr_picmr :
0;
assign irq_unmasked = spr_picmr & irq_i;
generate
genvar irqline;
if (OPTION_PIC_TRIGGER=="EDGE") begin : edge_triggered
reg [31:0] irq_unmasked_r;
wire [31:0] irq_unmasked_edge;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
irq_unmasked_r <= 0;
else
irq_unmasked_r <= irq_unmasked;
for(irqline=0;irqline<32;irqline=irqline+1) begin: picgenerate
assign irq_unmasked_edge[irqline] = irq_unmasked[irqline] &
!irq_unmasked_r[irqline];
// PIC status register
always @(posedge clk `OR_ASYNC_RST)
if (rst)
spr_picsr[irqline] <= 0;
// Set
else if (irq_unmasked_edge[irqline])
spr_picsr[irqline] <= 1;
// Clear
else if (spr_we_i & spr_picsr_access & spr_dat_i[irqline])
spr_picsr[irqline] <= 0;
end
end else if (OPTION_PIC_TRIGGER=="LEVEL") begin : level_triggered
for(irqline=0;irqline<32;irqline=irqline+1)
begin: picsrlevelgenerate
// PIC status register
always @(*)
spr_picsr[irqline] <= irq_unmasked[irqline];
end
end // if (OPTION_PIC_TRIGGER=="LEVEL")
else if (OPTION_PIC_TRIGGER=="LATCHED_LEVEL") begin : latched_level
for(irqline=0;irqline<32;irqline=irqline+1)
begin: piclatchedlevelgenerate
// PIC status register
always @(posedge clk `OR_ASYNC_RST)
if (rst)
spr_picsr[irqline] <= 0;
else if (spr_we_i && spr_picsr_access)
spr_picsr[irqline] <= irq_unmasked[irqline] |
spr_dat_i[irqline];
else
spr_picsr[irqline] <= spr_picsr[irqline] |
irq_unmasked[irqline];
end // block: picgenerate
end // if (OPTION_PIC_TRIGGER=="EDGE")
else begin : invalid
initial begin
$display("Error - invalid PIC level detection option %s",
OPTION_PIC_TRIGGER);
$finish;
end
end // else: !if(OPTION_PIC_TRIGGER=="LEVEL")
endgenerate
// PIC (un)mask register
always @(posedge clk `OR_ASYNC_RST)
if (rst)
spr_picmr <= {{(32-OPTION_PIC_NMI_WIDTH){1'b0}},
{OPTION_PIC_NMI_WIDTH{1'b1}}};
else if (spr_we_i && spr_picmr_access)
spr_picmr <= {spr_dat_i[31:OPTION_PIC_NMI_WIDTH],
{OPTION_PIC_NMI_WIDTH{1'b1}}};
endmodule // mor1kx_pic
|
// #####################################################################################
// # Copyright (C) 1991-2008 Altera Corporation
// # Any megafunction design, and related netlist (encrypted or decrypted),
// # support information, device programming or simulation file, and any other
// # associated documentation or information provided by Altera or a partner
// # under Altera's Megafunction Partnership Program may be used only
// # to program PLD devices (but not masked PLD devices) from Altera. Any
// # other use of such megafunction design, netlist, support information,
// # device programming or simulation file, or any other related documentation
// # or information is prohibited for any other purpose, including, but not
// # limited to modification, reverse engineering, de-compiling, or use with
// # any other silicon devices, unless such use is explicitly licensed under
// # a separate agreement with Altera or a megafunction partner. Title to the
// # intellectual property, including patents, copyrights, trademarks, trade
// # secrets, or maskworks, embodied in any such megafunction design, netlist,
// # support information, device programming or simulation file, or any other
// # related documentation or information provided by Altera or a megafunction
// # partner, remains with Altera, the megafunction partner, or their respective
// # licensors. No other licenses, including any licenses needed under any third
// # party's intellectual property, are provided herein.
// #####################################################################################
// #####################################################################################
// # Loopback module for SOPC system simulation with
// # Altera Triple Speed Ethernet (TSE) Megacore
// #
// # Generated at Tue Mar 5 15:23:02 2013 as a SOPC Builder component
// #
// #####################################################################################
// # This is a module used to provide external loopback on the TSE megacore by supplying
// # necessary clocks and default signal values on the network side interface
// # (GMII/MII/TBI/Serial)
// #
// # - by default this module generate clocks for operation in Gigabit mode that is
// # of 8 ns clock period
// # - no support for forcing collision detection and carrier sense in MII mode
// # the mii_col and mii_crs signal always pulled to zero
// # - you are recomment to set the the MAC operation mode using register access
// # rather than directly pulling the control signals
// #
// #####################################################################################
`timescale 1ns / 1ps
module tse_mac2_loopback (
ref_clk,
txp,
rxp
);
output ref_clk;
input txp;
output rxp;
reg clk_tmp;
initial
clk_tmp <= 1'b0;
always
#4 clk_tmp <= ~clk_tmp;
reg reconfig_clk_tmp;
initial
reconfig_clk_tmp <= 1'b0;
always
#20 reconfig_clk_tmp <= ~reconfig_clk_tmp;
assign ref_clk = clk_tmp;
assign rxp=txp;
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ac
//
// Generated
// by: wig
// on: Tue Jul 4 08:39:13 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ac.v,v 1.3 2007/03/05 13:33:58 wig Exp $
// $Date: 2007/03/05 13:33:58 $
// $Log: ent_ac.v,v $
// Revision 1.3 2007/03/05 13:33:58 wig
// Updated testcase output (only comments)!
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_ac
//
// No user `defines in this module
module ent_ac
//
// Generated Module inst_ac
//
(
port_ac_2 // Use internally test2, no port generated
);
// Generated Module Outputs:
output port_ac_2;
// Generated Wires:
reg port_ac_2;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of ent_ac
//
//
//!End of Module/s
// --------------------------------------------------------------
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2011 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
real r, r2;
integer cyc = 0;
task check(integer line, real got, real ex);
if (got != ex) begin
if ((got > ex ? got - ex : ex - got) > 0.000001) begin
$display("%%Error: Line %0d: Bad result, got=%0.99g expect=%0.99g",line,got,ex);
$stop;
end
end
endtask
initial begin
// Check constant propagation
// Note $abs is not defined in SystemVerilog (as of 2012)
check(`__LINE__, $ceil(-1.2), -1);
check(`__LINE__, $ceil(1.2), 2);
check(`__LINE__, $exp(1.2), 3.3201169227365472380597566370852291584014892578125);
check(`__LINE__, $exp(0.0), 1);
check(`__LINE__, $exp(-1.2), 0.301194211912202136627314530414878390729427337646484375);
check(`__LINE__, $floor(-1.2), -2);
check(`__LINE__, $floor(1.2), 1);
check(`__LINE__, $ln(1.2), 0.1823215567939545922460098381634452380239963531494140625);
//check(`__LINE__, $ln(0), 0); // Bad value
//check(`__LINE__, $ln(-1.2), 0); // Bad value
check(`__LINE__, $log10(1.2), 0.07918124604762481755226843915806966833770275115966796875);
//check(`__LINE__, $log10(0), 0); // Bad value
//check(`__LINE__, $log10(-1.2), 0);
check(`__LINE__, $pow(2.3,1.2), 2.71689843249914897427288451581262052059173583984375);
check(`__LINE__, $pow(2.3,-1.2), 0.368066758785732861536388327294844202697277069091796875);
//check(`__LINE__, $pow(-2.3,1.2),0); // Bad value
check(`__LINE__, $sqrt(1.2), 1.095445115010332148841598609578795731067657470703125);
//check(`__LINE__, $sqrt(-1.2), 0); // Bad value
check(`__LINE__, ((1.5)**(1.25)), 1.660023);
check(`__LINE__, $acos (0.2), 1.369438406); // Arg1 is -1..1
check(`__LINE__, $acosh(1.2), 0.622362503);
check(`__LINE__, $asin (0.2), 0.201357920); // Arg1 is -1..1
check(`__LINE__, $asinh(1.2), 1.015973134);
check(`__LINE__, $atan (0.2), 0.197395559);
check(`__LINE__, $atan2(0.2,2.3), 0.086738338); // Arg1 is -1..1
check(`__LINE__, $atanh(0.2), 0.202732554); // Arg1 is -1..1
check(`__LINE__, $cos (1.2), 0.362357754);
check(`__LINE__, $cosh (1.2), 1.810655567);
check(`__LINE__, $hypot(1.2,2.3), 2.594224354);
check(`__LINE__, $sin (1.2), 0.932039085);
check(`__LINE__, $sinh (1.2), 1.509461355);
check(`__LINE__, $tan (1.2), 2.572151622);
check(`__LINE__, $tanh (1.2), 0.833654607);
end
real sum_ceil;
real sum_exp;
real sum_floor;
real sum_ln;
real sum_log10;
real sum_pow1;
real sum_pow2;
real sum_sqrt;
real sum_acos;
real sum_acosh;
real sum_asin;
real sum_asinh;
real sum_atan;
real sum_atan2;
real sum_atanh;
real sum_cos ;
real sum_cosh;
real sum_hypot;
real sum_sin;
real sum_sinh;
real sum_tan;
real sum_tanh;
// Test loop
always @ (posedge clk) begin
r = $itor(cyc)/10.0 - 5.0; // Crosses 0
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d r=%g s_ln=%0.12g\n", $time, cyc, r, sum_ln);
`endif
cyc <= cyc + 1;
if (cyc==0) begin
end
else if (cyc<90) begin
// Setup
sum_ceil += 1.0+$ceil(r);
sum_exp += 1.0+$exp(r);
sum_floor += 1.0+$floor(r);
if (r > 0.0) sum_ln += 1.0+$ln(r);
if (r > 0.0) sum_log10 += 1.0+$log10(r);
// Pow requires if arg1<0 then arg1 integral
sum_pow1 += 1.0+$pow(2.3,r);
if (r >= 0.0) sum_pow2 += 1.0+$pow(r,2.3);
if (r >= 0.0) sum_sqrt += 1.0+$sqrt(r);
if (r>=-1.0 && r<=1.0) sum_acos += 1.0+$acos (r);
if (r>=1.0) sum_acosh += 1.0+$acosh(r);
if (r>=-1.0 && r<=1.0) sum_asin += 1.0+$asin (r);
sum_asinh += 1.0+$asinh(r);
sum_atan += 1.0+$atan (r);
if (r>=-1.0 && r<=1.0) sum_atan2 += 1.0+$atan2(r,2.3);
if (r>=-1.0 && r<=1.0) sum_atanh += 1.0+$atanh(r);
sum_cos += 1.0+$cos (r);
sum_cosh += 1.0+$cosh (r);
sum_hypot += 1.0+$hypot(r,2.3);
sum_sin += 1.0+$sin (r);
sum_sinh += 1.0+$sinh (r);
sum_tan += 1.0+$tan (r);
sum_tanh += 1.0+$tanh (r);
end
else if (cyc==99) begin
check (`__LINE__, sum_ceil, 85);
check (`__LINE__, sum_exp, 608.06652950);
check (`__LINE__, sum_floor, 4);
check (`__LINE__, sum_ln, 55.830941633);
check (`__LINE__, sum_log10, 46.309585076);
check (`__LINE__, sum_pow1, 410.98798177);
check (`__LINE__, sum_pow2, 321.94765689);
check (`__LINE__, sum_sqrt, 92.269677253);
check (`__LINE__, sum_acos, 53.986722862);
check (`__LINE__, sum_acosh, 72.685208498);
check (`__LINE__, sum_asin, 21);
check (`__LINE__, sum_asinh, 67.034973416);
check (`__LINE__, sum_atan, 75.511045389);
check (`__LINE__, sum_atan2, 21);
check (`__LINE__, sum_atanh, 0);
check (`__LINE__, sum_cos, 72.042023124);
check (`__LINE__, sum_cosh, 1054.);
check (`__LINE__, sum_hypot, 388.92858406);
check (`__LINE__, sum_sin, 98.264184989);
check (`__LINE__, sum_sinh, -);
check (`__LINE__, sum_tan, 1.);
check (`__LINE__, sum_tanh, 79.003199681);
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND2B_BEHAVIORAL_V
`define SKY130_FD_SC_LS__NAND2B_BEHAVIORAL_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__nand2b (
Y ,
A_N,
B
);
// Module ports
output Y ;
input A_N;
input B ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire or0_out_Y;
// Name Output Other arguments
not not0 (not0_out , B );
or or0 (or0_out_Y, not0_out, A_N );
buf buf0 (Y , or0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND2B_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR2_LP2_V
`define SKY130_FD_SC_LP__OR2_LP2_V
/**
* or2: 2-input OR.
*
* Verilog wrapper for or2 with size for low power (alternative).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__or2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or2_lp2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__or2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or2_lp2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__or2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR2_LP2_V
|
#include <bits/stdc++.h> using ll = long long; using namespace std; int main() { cin.tie(nullptr); ios::sync_with_stdio(false); cout << fixed << setprecision(15); int t; cin >> t; for (ll _ = 0, _Len = (t); _ < _Len; ++_) { ll n; cin >> n; vector<ll> a(n); vector<pair<ll, ll>> sorted; for (ll i = 0, iLen = (n); i < iLen; ++i) { cin >> a[i]; sorted.emplace_back(a[i], i); } sort(sorted.begin(), sorted.end()); int comp_n = -1, prev_n = -1; vector<int> num_cnt; for (auto &[num, index] : sorted) { if (prev_n < num) { prev_n = num; comp_n++; num_cnt.emplace_back(0); } a[index] = comp_n; num_cnt.back()++; } map<int, int> mp; vector<int> current_cnt(num_cnt.size()); vector<vector<int>> dp(n + 1, vector<int>(3, 1)); int ans = 0; for (ll i = 0, iLen = (n); i < iLen; ++i) { current_cnt[a[i]]++; auto itr1 = mp.find(a[i]), itr2 = mp.find(a[i] - 1); if (itr1 != mp.end()) { int j = itr1->second; dp[i][0] = dp[j][0] + 1; dp[i][1] = dp[j][1] + 1; dp[i][2] = dp[j][2] + 1; } if (itr2 != mp.end()) { int j = itr2->second; dp[i][2] = max(dp[i][2], dp[j][0] + 1); if (current_cnt[a[i]] == 1) { dp[i][1] = max(dp[i][1], dp[j][0] + 1); } if (num_cnt[a[i] - 1] == current_cnt[a[i] - 1]) { dp[i][2] = max(dp[i][2], dp[j][1] + 1); } if (itr1 == mp.end() && num_cnt[a[i] - 1] == current_cnt[a[i] - 1]) { dp[i][1] = max(dp[i][1], dp[j][1] + 1); } } ans = max({ans, dp[i][0], dp[i][1], dp[i][2]}); mp[a[i]] = i; } cout << n - ans << n ; } return 0; } |
/**
* @module regfile
* @author sabertazimi
* @email
* @brief register files for MIPS CPU, contains 32 D flip-flop registers
* @param DATA_WIDTH data width
* @input clk clock signal
* @input we write enable signal
* @input raddrA read address (No.register) for A out port
* @input raddrB read address (No.register) for B out port
* @input waddr write address (No.register) for wdata (in port)
* @input wdata data to write into regfile
* @output regA A port output
* @output regB B port output
*/
module regfile
#(parameter DATA_WIDTH = 32)
(
input clk,
input rst,
input we,
input [4:0] raddrA,
input [4:0] raddrB,
input [4:0] waddr,
input [DATA_WIDTH-1:0] wdata,
output [DATA_WIDTH-1:0] regA,
output [DATA_WIDTH-1:0] regB,
output [DATA_WIDTH-1:0] v0_data,
output [DATA_WIDTH-1:0] a0_data
);
`include "defines.vh"
reg [4:0] i;
reg [DATA_WIDTH-1:0] regfile [0:31]; ///< three ported regfile contains 32 registers
always @ (posedge clk) begin
if (rst) begin
for (i = 0; i < 31; i = i + 1)
begin
regfile[i] <= 0;
end
end else if (we && waddr != 0) begin
regfile[waddr] <= wdata;
end
end
assign regA = (we && waddr == raddrA) ? wdata
: (raddrA != 0) ? regfile[raddrA]
: 0;
assign regB = (we && waddr == raddrB) ? wdata
: (raddrB != 0) ? regfile[raddrB]
: 0;
assign v0_data = regfile[`V0];
assign a0_data = regfile[`A0];
endmodule // regfile
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// --------------------------------------------------------------------------------
//| Avalon ST Idle Remover
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module altera_avalon_st_idle_remover (
// Interface: clk
input clk,
input reset_n,
// Interface: ST in
output reg in_ready,
input in_valid,
input [7: 0] in_data,
// Interface: ST out
input out_ready,
output reg out_valid,
output reg [7: 0] out_data
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg received_esc;
wire escape_char, idle_char;
// ---------------------------------------------------------------------
//| Thingofamagick
// ---------------------------------------------------------------------
assign idle_char = (in_data == 8'h4a);
assign escape_char = (in_data == 8'h4d);
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
received_esc <= 0;
end else begin
if (in_valid & in_ready) begin
if (escape_char & ~received_esc) begin
received_esc <= 1;
end else if (out_valid) begin
received_esc <= 0;
end
end
end
end
always @* begin
in_ready = out_ready;
//out valid when in_valid. Except when we get idle or escape
//however, if we have received an escape character, then we are valid
out_valid = in_valid & ~idle_char & (received_esc | ~escape_char);
out_data = received_esc ? (in_data ^ 8'h20) : in_data;
end
endmodule
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:16777216 ) using namespace std; const double PI = acos(-1.0); long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } pair<long long, int> all[2000111]; long long cntA, cntB; int cnt; int main() { long long a, b; cin >> a >> b; long long x = a * b / gcd(a, b); for (int i = (1), _b = (x / a - 1); i <= _b; i++) all[cnt++] = make_pair(a * i, 0); for (int i = (1), _b = (x / b - 1); i <= _b; i++) all[cnt++] = make_pair(b * i, 1); sort(all, all + cnt); long long last = 0; for (int i = 0, _a = (cnt); i < _a; i++) { if (all[i].second == 0) cntA += all[i].first - last; else cntB += all[i].first - last; last = all[i].first; } if (a > b) cntA += x - last; else cntB += x - last; if (cntA > cntB) puts( Dasha ); else if (cntA < cntB) puts( Masha ); else puts( Equal ); return 0; } |
#include <bits/stdc++.h> #pragma comment(linker, /stack:200000000 ) #pragma GCC optimize( Ofast ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,tune=native ) using namespace std; int n, m; vector<int> a; bool chk(int c) { int lst = a[0]; if (a[0] + c >= m) lst = 0; for (int i = 1; i <= (n - 1); ++i) { if (a[i] + c >= m + lst) continue; if (a[i] < lst && a[i] + c >= lst) continue; if (a[i] + c < lst) return false; lst = a[i]; } return true; } int main() { cin.sync_with_stdio(0); cin.tie(0); cin.exceptions(cin.failbit); cin >> n >> m; a.resize(n); for (int i = 0; i < (n); ++i) cin >> a[i]; bool sorted = true; for (int i = 0; i < (n); ++i) { if (i != 0 && a[i - 1] > a[i]) sorted = false; } if (sorted) { cout << 0 << endl; return 0; } int lo = 0, hi = m, mid = (hi + lo) / 2; while (hi - lo > 1) { if (chk(mid)) hi = mid; else lo = mid; mid = (hi + lo) / 2; } cout << hi << endl; return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 05.03.2016 20:20:22
// Design Name:
// Module Name: data_formatter
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module data_formatter
(
input wire GCLK,
input wire RST,
input wire dec,
input wire [7:0] temp_data_in,
input wire [15:0] x_axis_in,
input wire [15:0] y_axis_in,
input wire [15:0] z_axis_in,
output wire [15:0] x_axis_out,
output wire [15:0] y_axis_out,
output wire [15:0] z_axis_out,
output wire [15:0] temp_data_out,
//input wire tx_end,
output wire [15:0] ang_x,
output wire [15:0] ang_y,
output wire [15:0] ang_z
);
//---------------------------------------------------
// Clock for Pmod components
//---------------------------------------------------
wire dclk;
display_clk C1(
.clk(GCLK),
.RST(RST),
.dclk(dclk)
);
//---------------------------------------------------
// Formats data received from PmodGYRO
//---------------------------------------------------
data_controller C0_X(
.clk(GCLK),
.dclk(dclk),
.rst(RST),
.display_sel(dec),
.sel(2'b00),
.data(x_axis_in),
.frmt(x_axis_out)
);
data_controller C0_Y(
.clk(GCLK),
.dclk(dclk),
.rst(RST),
.display_sel(dec),
.sel(2'b01),
.data(y_axis_in),
.frmt(y_axis_out)
);
data_controller C0_Z(
.clk(GCLK),
.dclk(dclk),
.rst(RST),
.display_sel(dec),
.sel(2'b10),
.data(z_axis_in),
.frmt(z_axis_out)
);
data_controller C0_T(
.clk(GCLK),
.dclk(dclk),
.rst(RST),
.display_sel(dec),
.sel(2'b11),
.data({8'd0, temp_data_in}),
.frmt(temp_data_out)
);
reg [15:0] ax_acc = 0;
reg [15:0] ay_acc = 0;
reg [15:0] az_acc = 0;
always @(ang_x) begin
ax_acc <= RST ? 0 : ax_acc + ang_x;
end
data_controller C0_X_ACC(
.clk(GCLK),
.dclk(dclk),
.rst(RST),
.display_sel(dec),
.sel(2'b00),
.data(ax_acc),
.frmt(ang_x)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 5e5 + 5; int n, m, cnt, belong[N]; vector<int> g[N], ans[N]; int get(int x) { return belong[x] ? belong[x] = get(belong[x]) : x; } void dfs(int i) { ans[cnt].push_back(i); belong[i] = i + 1; for (int j = get(1), k = 0; j <= n; j = get(j + 1)) { for (; k < g[i].size() && g[i][k] < j; k++) ; if (k < g[i].size() && g[i][k] == j) continue; dfs(j); } } int main() { scanf( %d%d , &n, &m); while (m--) { int a, b; scanf( %d%d , &a, &b); g[a].push_back(b); g[b].push_back(a); } for (int i = 1; i <= n; i++) sort(g[i].begin(), g[i].end()); for (int i = 1; i <= n; i++) if (!belong[i]) { dfs(i); cnt++; } printf( %d n , cnt); for (int i = 0; i < cnt; i++) { printf( %u , ans[i].size()); for (int j = 0; j < ans[i].size(); j++) printf( %d , ans[i][j]); puts( ); } } |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast,no-stack-protector,unroll-loops,fast-math ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,sse4.1,sse4.2,popcnt,abm,mmx,avx ) using namespace std; const long long maxn = 1e5 + 20; const long long inf = (long long)2e9; const long double pi = asin(1) * 2; const long double eps = 1e-8; const long long mod = (long long)1e9 + 7; const long long ns = 97; mt19937 rnd(chrono::steady_clock::now().time_since_epoch().count()); long long dp[maxn], tin[maxn], up[maxn], was[maxn], used[maxn]; vector<long long> g[maxn], ans, order; long long timer = 0, flag = 1; void dfs(long long v) { used[v] = 1; tin[v] = timer++; dp[v] = tin[up[v]]; for (auto& u : g[v]) { if (!used[u]) dfs(u); dp[v] = min(dp[v], dp[u]); if (dp[u] < tin[v] && dp[u] != tin[up[v]]) flag = 0; } if (dp[v] < tin[up[v]]) flag = 0; order.push_back(v); } void dfs2(long long v) { used[v] = 1; for (auto& u : g[v]) if (!used[u]) dfs2(u); if (was[v]) ans.push_back(v); } signed main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); long long n, m; cin >> n >> m; for (long long i = 0; i < m; ++i) { long long a, b; cin >> a >> b; --a, --b; g[a].push_back(b); used[b] = 1; } for (long long i = 0; i < n; ++i) { cin >> up[i]; --up[i]; was[up[i]] = 1; } vector<long long> roots; for (long long i = 0; i < n; ++i) if (!used[i]) roots.push_back(i); for (auto& x : used) x = 0; for (auto& x : roots) dfs(x); if (!flag) { cout << -1; exit(0); } for (auto& x : used) x = 0; reverse(order.begin(), order.end()); for (long long i = 0; i < n; ++i) if (!used[i]) dfs2(i); cout << (long long)ans.size() << n ; for (auto& x : ans) cout << x + 1 << n ; } |
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Wishbone controller for ////
//// Single-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/minsoc/ ////
//// ////
//// Description ////
//// This Wishbone controller connects to the wrapper of ////
//// the single-port synchronous memory interface. ////
//// Besides universal memory due to onchip_ram it provides a ////
//// generic way to set the depth of the memory. ////
//// ////
//// To Do: ////
//// ////
//// Author(s): ////
//// - Raul Fajardo, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.gnu.org/licenses/lgpl.html ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// Revision History
//
// Revision 1.1 2009/10/02 16:49 fajardo
// Not using the oe signal (output enable) from
// memories, instead multiplexing the outputs
// between the different instantiated blocks
//
//
// Revision 1.0 2009/08/18 15:15:00 fajardo
// Created interface and tested
//
`include "minsoc_defines.v"
`define mem_init_file "uart-nocache.mif" //specific memory initalization file name, which can be intel hex(.hex) or Altera mif file
//if no initalization file used, give a name of "UNUSED"
module minsoc_onchip_ram_top (
wb_clk_i, wb_rst_i,
wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,
wb_stb_i, wb_ack_o, wb_err_o
);
//
// Parameters
//
parameter adr_width = 13; //Memory address width, is composed by blocks of aw_int, is not allowed to be less than 12
localparam aw_int = 11; //11 = 2048
localparam blocks = (1<<(adr_width-aw_int)); //generated memory contains "blocks" memory blocks of 2048x32 2048 depth x32 bit data
//
// I/O Ports
//
input wb_clk_i;
input wb_rst_i;
//
// WB slave i/f
//
input [31:0] wb_dat_i;
output [31:0] wb_dat_o;
input [31:0] wb_adr_i;
input [3:0] wb_sel_i;
input wb_we_i;
input wb_cyc_i;
input wb_stb_i;
output wb_ack_o;
output wb_err_o;
//
// Internal regs and wires
//
wire we;
wire [3:0] be_i;
wire [31:0] wb_dat_o;
reg ack_we;
reg ack_re;
//
// Aliases and simple assignments
//
assign wb_ack_o = ack_re | ack_we;
assign wb_err_o = wb_cyc_i & wb_stb_i & (|wb_adr_i[23:adr_width+2]); // If Access to > (8-bit leading prefix ignored)
assign we = wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[3:0]);
assign be_i = (wb_cyc_i & wb_stb_i) * wb_sel_i;
//
// Write acknowledge
//
always @ (negedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
ack_we <= 1'b0;
else
if (wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we)
ack_we <= #1 1'b1;
else
ack_we <= #1 1'b0;
end
//
// read acknowledge
//
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
ack_re <= 1'b0;
else
if (wb_cyc_i & wb_stb_i & ~wb_err_o & ~wb_we_i & ~ack_re)
ack_re <= #1 1'b1;
else
ack_re <= #1 1'b0;
end
`ifdef ALTERA_FPGA //only for altera memory initialization
//2^adr_width x 32bit single-port ram.
altsyncram altsyncram_component (
.wren_a (we),
.clock0 (wb_clk_i),
.byteena_a (be_i),
.address_a (wb_adr_i[adr_width+1:2]),
.data_a (wb_dat_i),
.q_a (wb_dat_o),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = `mem_init_file,
altsyncram_component.intended_device_family = "Stratix III",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.numwords_a = (1<<adr_width),
altsyncram_component.widthad_a = adr_width,
altsyncram_component.width_a = 32,
altsyncram_component.byte_size = 8,
altsyncram_component.width_byteena_a = 4;
`else //other FPGA Type
//Generic (multiple inputs x 1 output) MUX
localparam mux_in_nr = blocks;
localparam slices = adr_width-aw_int;
localparam mux_out_nr = blocks-1;
wire [31:0] int_dat_o[0:mux_in_nr-1];
wire [31:0] mux_out[0:mux_out_nr-1];
generate
genvar j, k;
for (j=0; j<slices; j=j+1) begin : SLICES
for (k=0; k<(mux_in_nr>>(j+1)); k=k+1) begin : MUX
if (j==0) begin
mux2 #
(
.dw(32)
)
mux_int(
.sel( wb_adr_i[aw_int+2+j] ),
.in1( int_dat_o[k*2] ),
.in2( int_dat_o[k*2+1] ),
.out( mux_out[k] )
);
end
else begin
mux2 #
(
.dw(32)
)
mux_int(
.sel( wb_adr_i[aw_int+2+j] ),
.in1( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2] ),
.in2( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2+1] ),
.out( mux_out[(mux_in_nr-(mux_in_nr>>j))+k] )
);
end
end
end
endgenerate
//last output = total output
assign wb_dat_o = mux_out[mux_out_nr-1];
//(mux_in_nr-(mux_in_nr>>j)):
//-Given sum of 2^i | i = x -> y series can be resumed to 2^(y+1)-2^x
//so, with this expression I'm evaluating how many times the internal loop has been run
wire [blocks-1:0] bank;
generate
genvar i;
for (i=0; i < blocks; i=i+1) begin : MEM
assign bank[i] = wb_adr_i[adr_width+1:aw_int+2] == i;
//BANK0
minsoc_onchip_ram block_ram_0 (
.clk(wb_clk_i),
.rst(wb_rst_i),
.addr(wb_adr_i[aw_int+1:2]),
.di(wb_dat_i[7:0]),
.doq(int_dat_o[i][7:0]),
.we(we & bank[i]),
.oe(1'b1),
.ce(be_i[0])
);
minsoc_onchip_ram block_ram_1 (
.clk(wb_clk_i),
.rst(wb_rst_i),
.addr(wb_adr_i[aw_int+1:2]),
.di(wb_dat_i[15:8]),
.doq(int_dat_o[i][15:8]),
.we(we & bank[i]),
.oe(1'b1),
.ce(be_i[1])
);
minsoc_onchip_ram block_ram_2 (
.clk(wb_clk_i),
.rst(wb_rst_i),
.addr(wb_adr_i[aw_int+1:2]),
.di(wb_dat_i[23:16]),
.doq(int_dat_o[i][23:16]),
.we(we & bank[i]),
.oe(1'b1),
.ce(be_i[2])
);
minsoc_onchip_ram block_ram_3 (
.clk(wb_clk_i),
.rst(wb_rst_i),
.addr(wb_adr_i[aw_int+1:2]),
.di(wb_dat_i[31:24]),
.doq(int_dat_o[i][31:24]),
.we(we & bank[i]),
.oe(1'b1),
.ce(be_i[3])
);
end
endgenerate
`endif
endmodule
module mux2(sel,in1,in2,out);
parameter dw = 32;
input sel;
input [dw-1:0] in1, in2;
output reg [dw-1:0] out;
always @ (sel or in1 or in2)
begin
case (sel)
1'b0: out = in1;
1'b1: out = in2;
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__UDP_DLATCH_P_PP_PG_N_TB_V
`define SKY130_FD_SC_HVL__UDP_DLATCH_P_PP_PG_N_TB_V
/**
* udp_dlatch$P_pp$PG$N: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__udp_dlatch_p_pp_pg_n.v"
module top();
// Inputs are registered
reg D;
reg NOTIFIER;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
NOTIFIER = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 NOTIFIER = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 D = 1'b1;
#120 NOTIFIER = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 D = 1'b0;
#200 NOTIFIER = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 NOTIFIER = 1'b1;
#320 D = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 NOTIFIER = 1'bx;
#400 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N dut (.D(D), .NOTIFIER(NOTIFIER), .VPWR(VPWR), .VGND(VGND), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__UDP_DLATCH_P_PP_PG_N_TB_V
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 100, M = 10 + 10, SQ = 333; pair<int, int> nxt[N][M]; char a[N][M]; bool mark[N][M]; int n, m, q; bool OK(pair<int, int> x) { return x.first > 0 && x.second > 0 && x.second <= m; } pair<int, int> go(int x, int y) { if (!OK({x, y})) return {x, y}; if (nxt[x][y].first != -2) return nxt[x][y]; if (a[x][y] == ^ ) return x % SQ ? nxt[x][y] = go(x - 1, y) : nxt[x][y] = {x - 1, y}; if (mark[x][y]) return nxt[x][y] = {-1, -1}; mark[x][y] = true; if (a[x][y] == > ) nxt[x][y] = go(x, y + 1); if (a[x][y] == < ) nxt[x][y] = go(x, y - 1); mark[x][y] = false; return nxt[x][y]; } int main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); for (int i = 0; i < N; i++) for (int j = 0; j < M; j++) nxt[i][j] = {-2, -2}; cin >> n >> m >> q; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) cin >> a[i][j]; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) go(i, j); while (q--) { char tp; int x, y; cin >> tp >> x >> y; if (tp == A ) { pair<int, int> tmp = {x, y}; while (OK(tmp)) tmp = nxt[tmp.first][tmp.second]; cout << tmp.first << << tmp.second << n ; } else { cin >> a[x][y]; int A = 0; while (A <= x) A += SQ; for (int i = x; i <= min(A, n); i++) for (int j = 1; j <= m; j++) nxt[i][j] = {-2, -2}; for (int i = x; i <= min(A, n); i++) for (int j = 1; j <= m; j++) go(i, j); } } } |
#include <bits/stdc++.h> using namespace std; inline int read() { int s = 0, w = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) w = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) s = s * 10 + ch - 0 , ch = getchar(); return s * w; } const int inf = 2e9 + 7; double eps = 1e-6; const int mod = 1e9 + 9; const int N = 1e3 + 10; const double pi = acos(-1.0); long long power(long long a, long long b) { long long res = 1; while (b) { if (b & 1) res = res * a % mod; a = a * a % mod; b >>= 1; } return res; } long long gcd(long long a, long long b) { return !b ? a : gcd(b, a % b); } long long exgcd(long long a, long long b, long long& x, long long& y) { long long c; return !b ? (x = 1, y = 0, a) : (c = exgcd(b, a % b, y, x), y -= (a / b) * x, c); } long long INV(long long a) { long long x, y; exgcd(a, mod, x, y); x %= mod; if (x < 0) x += mod; return x; } int n; long long dp[N][N][11]; struct AC { int tr[N][26], tot; int fail[N]; int tr2[N][26]; int Len[N]; bool key[N]; int insert(char s[]) { int u = 0; for (int i = 1; s[i]; i++) { int c = s[i] - a ; if (!tr[u][c]) tr[u][c] = ++tot; Len[tr[u][c]] = Len[u] + 1; u = tr[u][c]; } key[u] = 1; return u; } void build() { for (int i = 0; i <= tot; ++i) for (int j = 0; j <= 3; ++j) tr2[i][j] = tr[i][j]; queue<int> q; for (int i = 0; i <= 25; ++i) if (tr[0][i]) q.push(tr[0][i]); while (!q.empty()) { int u = q.front(); q.pop(); for (int i = 0; i <= 25; ++i) { if (tr[u][i]) { fail[tr[u][i]] = tr[fail[u]][i], q.push(tr[u][i]); } else tr[u][i] = tr[fail[u]][i]; } } } int dfs(int u, int len, int k) { bool ok = key[u]; int now = u; while (1) { now = fail[now]; if (Len[now] >= k && key[now]) { ok |= 1; break; } if (now == 0) break; } if (ok) k = 0; if (!u) return 0; if (dp[u][len][k] != -1) return dp[u][len][k]; if (len == n) { bool ok = key[u]; int now = u; while (1) { now = fail[now]; if (Len[now] >= k && key[now]) { ok |= 1; break; } if (now == 0) break; } return dp[u][len][k] = ok; } long long& res = dp[u][len][k] = 0; for (int i = 0; i <= 3; i++) { if (tr2[u][i]) res += dfs(tr2[u][i], len + 1, k + 1); else { int now = u; while (1) { now = fail[now]; if (Len[now] >= k && tr2[now][i]) { res += dfs(tr2[now][i], len + 1, k + 1); break; } if (now == 0) break; } } } res %= mod; return res; } int work() { memset(dp, -1, sizeof(dp)); long long res = 0; for (int i = 0; i <= 3; i++) res += dfs(tr[0][i], 1, 1); res %= mod; return res; } } ac; char s[N]; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int m; cin >> n >> m; map<char, char> mp; mp[ A ] = a ; mp[ C ] = b ; mp[ T ] = c ; mp[ G ] = d ; for (int i = 1; i <= m; ++i) { cin >> s + 1; for (int i = 1; i <= strlen(s + 1); ++i) s[i] = mp[s[i]]; ac.insert(s); } ac.build(); cout << ac.work() << n ; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A21O_BLACKBOX_V
`define SKY130_FD_SC_LS__A21O_BLACKBOX_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a21o (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A21O_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int N = 5005; vector<int> adj[N]; bool visited[N]; bool reach[N]; pair<int, int> has[N]; int cnt = 0; void dfs(int s) { if (!visited[s]) { visited[s] = 1; reach[s] = 1; for (int i = 0; i < adj[s].size(); i++) { dfs(adj[s][i]); } } } void dfs2(int s, int a) { if (!visited[s]) { visited[s] = 1; if (reach[s] == 0) has[a].first++; for (int i = 0; i < adj[s].size(); i++) { dfs2(adj[s][i], a); } } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, m, s; cin >> n >> m >> s; s--; for (int i = 0; i < m; i++) { int a, b; cin >> a >> b; a--; b--; adj[a].push_back(b); } dfs(s); for (int i = 0; i < n; i++) { has[i].second = i; } for (int i = 0; i < n; i++) { if (!reach[i]) { memset(visited, 0, sizeof(visited)); dfs2(i, i); } } sort(has, has + N); reverse(has, has + N); int ans = 0; cnt = 0; memset(visited, 0, sizeof(visited)); for (int i = 0; i < n; i++) { if (!reach[has[i].second]) { dfs(has[i].second); memset(visited, 0, sizeof(visited)); ans++; } } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = (int)1e6 + 10; const int mod = (int)1e9 + 7; const int inf = (1 << 30) - 1; int n, m, q; int a[maxn]; int good[maxn]; vector<int> g[maxn]; int p[maxn]; int dx[] = {-1, 1, 0, 0}; int dy[] = {0, 0, -1, 1}; char dir[] = { U , D , L , R }; int u[maxn]; int T; int b[maxn]; char c[maxn]; bool dfs(int v) { if (u[v] == T) return false; u[v] = T; for (int to : g[v]) { if (p[to] == -1) { p[to] = v; p[v] = to; return true; } } for (int to : g[v]) { if (good[p[to]] > 0) { p[p[to]] = -1; p[to] = v; p[v] = to; return true; } } for (int to : g[v]) { if (dfs(p[to])) { p[to] = v; p[v] = to; return true; } } return false; } void solve() { cin >> n >> m; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> a[i * m + j]; good[i * m + j] = 0; g[i * m + j].clear(); p[i * m + j] = -1; u[i * m + j] = 0; } } T = 0; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { for (int k = 0; k < 4; k++) { int x = i + dx[k]; int y = j + dy[k]; if (x >= 0 && x < n && y >= 0 && y < m) { if (a[i * m + j] > a[x * m + y]) { good[i * m + j] = 1; } else if (a[i * m + j] == a[x * m + y]) { g[i * m + j].emplace_back(x * m + y); } } } } } vector<int> li; for (int i = 0; i < n * m; i++) { if (good[i] == 0) { li.emplace_back(i); } } while (true) { int ok = false; T++; for (int i = 0; i < li.size(); i++) { if (p[li[i]] == -1 && dfs(li[i])) { ok = true; } } if (!ok) break; } for (int i = 0; i < n * m; i++) { if (good[i]) continue; if (p[i] == -1) { cout << NO n ; return; } } cout << YES n ; for (int i = 0; i < n * m; i++) { if (p[i] == -1) { for (int k = 0; k < 4; k++) { int x = i / m + dx[k]; int y = i % m + dy[k]; if (x >= 0 && x < n && y >= 0 && y < m) { if (a[i] > a[x * m + y]) { b[i] = a[i] - a[x * m + y]; c[i] = dir[k]; } } } } else { for (int k = 0; k < 4; k++) { int x = i / m + dx[k]; int y = i % m + dy[k]; if (x >= 0 && x < n && y >= 0 && y < m) { if (a[i] == a[x * m + y] && p[i] == x * m + y) { if (i < x * m + y) { b[i] = 1; } else { b[i] = a[i] - 1; } c[i] = dir[k]; } } } } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cout << b[i * m + j] << ; } cout << n ; } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cout << c[i * m + j] << ; } cout << n ; } } int main() { ios_base::sync_with_stdio(false); cin.tie(); cout.tie(); int t = 1; cin >> t; for (int i = 1; i <= t; i++) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; template <typename T> ostream &operator<<(ostream &o, const vector<T> &v) { for (size_t i = 0; i < v.size(); i++) o << v[i] << (i + 1 != v.size() ? : ); return o; } template <int n, class... T> typename enable_if<(n >= sizeof...(T))>::type _ot(ostream &, tuple<T...> const &) {} template <int n, class... T> typename enable_if<(n < sizeof...(T))>::type _ot(ostream &os, tuple<T...> const &t) { os << (n == 0 ? : , ) << get<n>(t); _ot<n + 1>(os, t); } template <class... T> ostream &operator<<(ostream &o, tuple<T...> const &t) { o << ( ; _ot<0>(o, t); o << ) ; return o; } template <class T, class U> ostream &operator<<(ostream &o, pair<T, U> const &p) { o << ( << p.first << , << p.second << ) ; return o; } int n; int cnt = 0; int ask(int y1, int x1, int y2, int x2) { cnt++; assert(cnt <= 4 * n); assert(abs(y2 - y1) + abs(x2 - x1) >= n - 1); if (y1 > y2) swap(y1, y2); if (x1 > x2) swap(x1, x2); cout << ? << y1 + 1 << << x1 + 1 << << y2 + 1 << << x2 + 1 << endl; string s; cin >> s; assert(s != BAD ); return s[0] == Y ; } string ans; int yy, xx; int dfs(int y1, int x1, int y2, int x2, int i, int ok, int rev) { if (!ok && !ask(y1, x1, y2, x2)) return 0; if (abs(y2 - y1) + abs(x2 - x1) == n - 1) return 1; int sg = y2 - y1 < 0 ? -1 : 1; if (rev) { if (dfs(y1, x1, y2 - sg, x2, i - sg, 0, rev)) { ans[i] = D ; } else if (dfs(y1, x1, y2, x2 - sg, i - sg, 1, rev)) { ans[i] = R ; } } else { if (dfs(y1, x1, y2, x2 - sg, i - sg, 0, rev)) { ans[i] = R ; } else if (dfs(y1, x1, y2 - sg, x2, i - sg, 1, rev)) { ans[i] = D ; } } return 1; } int main() { std::ios::sync_with_stdio(false), std::cin.tie(0); cin >> n; ans = string(2 * n - 2, - ); dfs(0, 0, n - 1, n - 1, 2 * n - 3, 1, 0); dfs(n - 1, n - 1, 0, 0, 0, 1, 1); assert((int)ans.find( - ) == -1); cout << ! << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; long long pw(long long a, long long b, long long md) { return (!b ? 1 : (b & 1 ? a * pw(a * a % md, b / 2, md) % md : pw(a * a % md, b / 2, md) % md)); } const long long MOD = 1e9 + 7, MAXN = 1e6 + 10; bool prime[MAXN]; long long n, ans, p; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; cin >> n; for (long long i = 0; i < MAXN; i++) prime[i] = true; for (int p = 2; p * p <= n; p++) { if (prime[p] == true) { for (int i = p * 2; i <= n; i += p) prime[i] = false; } } for (long long i = 1; i <= n; i++) { p = 0; for (long long j = 2; j <= i; j++) { if (i % j == 0 && prime[j]) p++; } if (p == 2) ans++; } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long nax = 105; long long a[nax]; signed main() { long long n, cnt0 = 0, cnt1 = 0; cin >> n; for (long long i = 1; i <= n; i++) { cin >> a[i]; if (a[i] == 0) cnt0++; else cnt1++; } if (cnt0 == n) { cout << 0 << endl; return 0; } else if (cnt1 == n) { cout << 1 << endl; return 0; } long long idx = 0; long long pdt = 1; for (long long i = 1; i <= n; i++) { if (a[i] == 1) { if (idx == 0) idx = i; else { long long temp = idx; pdt *= i - temp; idx = i; } } } cout << pdt << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long int N = 200001; const long long int M = 21; struct point { long long int x, y, cur; bool operator==(const point b) { if (this->x == b.x && this->y == b.y) return 1; return 0; } bool operator!=(const point b) { return !(*this == b); } friend bool operator<(const point a, const point b) { if (a.x != b.x) return a.x < b.x; return a.y < b.y; } }; void debug(stringstream &s) {} template <typename T, typename... Args> void debug(stringstream &s, T a, Args... args) { string word; s >> word; cout << word << = << a << endl; debug(s, args...); } bool overflow; long long int fast_exp(long long int x, long long int n) { if (n == 0) return 1; long long int ans; if (n % 2 == 0) { ans = fast_exp(x, n / 2); if (ans > ans * ans % 998244353) overflow = 1; ans = ans * ans % 998244353; } else { ans = fast_exp(x, n - 1); if (ans > ans * x % 998244353) overflow = 1; ans = ans * x % 998244353; } return ans; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int _ = 1; while (_--) { long long int n, m = 0, x = 0, y = 0, ans = 0, k; string s, sol; cin >> s; n = s.size(); set<long long int, greater<long long int>> c[26]; s = 0 + s; for (int i = 1; i <= n; i++) c[s[i] - a ].insert(i); long long int dp[n + 1][51]; memset(dp, -1, sizeof(dp)); for (int i = 0; i <= n; i++) dp[i][0] = n + 1; for (int i = 1; i <= n; i++) { for (int j = 1; j < 51; j++) { dp[i][j] = dp[i - 1][j]; x = dp[i - 1][j - 1]; auto it = c[s[i] - a ].upper_bound(x); if (it != c[s[i] - a ].end() && *it >= i) { dp[i][j] = max(dp[i][j], *it); } } } x = -1; for (int i = 50; i > 0; i--) { bool flag = 0; m = 0; for (int j = 1; j <= n; j++) { if (dp[j][i] != -1) { if (dp[j][i] - j >= m) { x = j; y = i; m = dp[j][i] - j; } flag = 1; } } if (flag) break; } for (int i = x; i > 0; i--) { if (dp[i - 1][y] != dp[i][y]) { if (dp[i][y] > i) sol = s[i] + sol + s[i]; else sol = s[i]; y--; } } cout << sol << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long mod; long long lgput(long long a, long long b) { if (b == 0) return 1; if (b == 1) return a % mod; long long c = lgput(a, b / 2); c = c * c % mod; if (b & 1) c = c * a % mod; return c; } map<long long, int> hh; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long n, k; cin >> n >> mod >> k; int i, j, z; for (i = 0; i < n; i++) { cin >> z; hh[(lgput(z, 4) - 1LL * k * z % mod + mod) % mod]++; } long long ans = 0; for (pair<int, int> cur : hh) ans += 1LL * cur.second * (cur.second - 1) / 2; cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; int dis[200009]; int con[200009]; bool cmp(int a, int b) { return a < b; } int main() { int i, p, j, n, t, y; int x; long long int nail; scanf( %d , &n); for (i = 0; i <= n - 1; i++) scanf( %d , &dis[i]); sort(dis, dis + n, cmp); nail = 99999999999; j = 0; y = 0; for (i = 1; i <= n - 1; i++) { x = dis[i] - dis[i - 1]; con[i] = x; if (x < nail) nail = x; } for (i = 1; i <= n - 1; i++) if (nail == con[i]) y++; printf( %lld %d n , nail, y); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long MXN = 2e5 + 10; const long long LOG = 21; const long long MXM = (1LL << LOG); const long long INF = 1e9; int n, m, ans; int dp[MXN], ps[MXN], Best[LOG][MXM]; string S[MXN]; int Cost(int i, int j) { for (int x = m; x; x--) { if (S[i].substr(m - x + 1, x) == S[j].substr(1, x)) { return m - x; } } return m; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); memset(dp, 31, sizeof dp), memset(Best, 31, sizeof Best); cin >> n, ans = INF; for (int i = 1; i <= n; i++) { cin >> S[i], m = (long long)S[i].size(); S[i] = 0 + S[i]; } ps[1] = dp[1] = m; for (int i = 2; i <= n; i++) ps[i] = ps[i - 1] + Cost(i - 1, i); for (int i = 2; i <= n; i++) { dp[i] = ps[i - 1] + m; long long mask = 0; for (int x = 0; x <= m; x++) { mask = mask * 2 + (S[i][x] - 0 ); if (Best[x][mask] < INF) { dp[i] = min(dp[i], ps[i - 1] + m - x + Best[x][mask]); } } mask = 0; for (int x = 0; x <= m; x++) { if (x && S[i - 1][m - x + 1] == 1 ) { mask += (1LL << (x - 1)); } Best[x][mask] = min(Best[x][mask], dp[i] - ps[i]); } } for (int i = 1; i <= n; i++) ans = min(ans, dp[i] + ps[n] - ps[i]); cout << ans << n ; return 0; } |
#include<bits/stdc++.h> using namespace std; void solve(){ int n; cin >> n; int a[n]; for(int i=0;i<n;i++){ cin >> a[i]; } vector<int> ans; ans.push_back(0); int current = a[0]; for(int i=1;i<n;i++){ int cans = (current|a[i])^a[i]; ans.push_back(cans); current = current|a[i]; } for(int i=0;i<n;i++){ cout << ans[i] << ; } cout << endl; } int main(){ int t=1; cin >> t; while(t--){ solve(); } } |
module lsuc_top (
clk,
reset_,
led,
switches,
segment_,
digit_enable_,
up_,
down_,
left_,
right_,
tx,
rx);
input clk;
input reset_;
output [7:0] led; // LogicSmart LEDs
input [6:0] switches; // LogicSmart toggle switches (first one is tied to reset)
output [6:0] segment_; // Seven segment display segments
output [3:0] digit_enable_; // Seven segment display digit enable
input up_; // D-pad up key
input down_; // D-pad down key
input left_; // D-pad left key
input right_; // D-pad right key
output tx; // UART transmit (to host computer)
input rx; // UART receive (from host computer)
// Top-level module for the LogicStart Microcontroller; instantiates all
// submodules and connects them together (provides no other logic).
wire clk;
wire reset_;
wire [31:0] mcs_addr;
wire mcs_ready;
wire [31:0] mcs_wr_data;
wire mcs_wr_enable;
wire [31:0] mcs_rd_data;
wire mcs_rd_enable;
wire [3:0] mcs_byte_enable;
wire [7:0] addr;
wire req;
wire [7:0] wr_data;
wire rnw;
wire gpio_cs;
wire [7:0] gpio_rd_data;
wire gpio_rdy;
wire disp_cs;
wire [7:0] disp_rd_data;
wire disp_rdy;
wire uart_cs;
wire [7:0] uart_rd_data;
wire uart_rdy;
// Bus controller instantiation ("distributes" MicroBlaze IO bus to local modules)
bus_arb bus_arb (
.clk(clk),
.reset_(reset_),
.mcs_addr(mcs_addr),
.mcs_ready(mcs_ready),
.mcs_wr_data(mcs_wr_data),
.mcs_wr_enable(mcs_wr_enable),
.mcs_rd_data(mcs_rd_data),
.mcs_rd_enable(mcs_rd_enable),
.mcs_byte_enable(mcs_byte_enable),
.addr(addr),
.req(req),
.rnw(rnw),
.wr_data(wr_data),
.gpio_cs(gpio_cs),
.gpio_rd_data(gpio_rd_data),
.gpio_rdy(gpio_rdy),
.disp_cs(disp_cs),
.disp_rd_data(disp_rd_data),
.disp_rdy(disp_rdy),
.uart_cs(uart_cs),
.uart_rd_data(uart_rd_data),
.uart_rdy(uart_rdy)
);
// GPIO control module (provides software interface to leds, switches and d-pad)
gpio_ctrl gpio_ctrl (
.clk(clk),
.reset_(reset_),
.leds(led),
.switches(switches),
.up(~up_),
.down(~down_),
.left(~left_),
.right(~right_),
.addr(addr),
.cs(gpio_cs),
.req(req),
.rnw(rnw),
.wr_data(wr_data),
.rd_data(gpio_rd_data),
.rdy(gpio_rdy)
);
// Display control module (provides software interface to 7-segment display)
disp_ctrl disp_ctrl (
.clk(clk),
.reset_(reset_),
.segments_(segment_),
.digit_enable_(digit_enable_),
.addr(addr),
.cs(disp_cs),
.req(req),
.rnw(rnw),
.wr_data(wr_data),
.rd_data(disp_rd_data),
.rdy(disp_rdy)
);
// UART control module (provides software interface to UART)
uart_ctrl uart_ctrl (
.clk(clk),
.reset_(reset_),
.tx(tx),
.rx(rx),
.addr(addr),
.cs(uart_cs),
.req(req),
.rnw(rnw),
.wr_data(wr_data),
.rd_data(uart_rd_data),
.rdy(uart_rdy)
);
// Xilinx MicroBlaze CPU core
microblaze_mcs_v1_4 mcs_0 (
.Clk(clk), // input Clk
.Reset(~reset_), // input Reset
.IO_Addr_Strobe(), // output IO_Addr_Strobe
.IO_Read_Strobe(mcs_rd_enable), // output IO_Read_Strobe
.IO_Write_Strobe(mcs_wr_enable), // output IO_Write_Strobe
.IO_Address(mcs_addr), // output [31 : 0] IO_Address
.IO_Byte_Enable(mcs_byte_enable), // output [3 : 0] IO_Byte_Enable
.IO_Write_Data(mcs_wr_data), // output [31 : 0] IO_Write_Data
.IO_Read_Data(mcs_rd_data), // input [31 : 0] IO_Read_Data
.IO_Ready(mcs_ready) // input IO_Ready
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRSDFRTN_SYMBOL_V
`define SKY130_FD_SC_LP__SRSDFRTN_SYMBOL_V
/**
* srsdfrtn: Scan flop with sleep mode, inverted reset, inverted
* clock, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__srsdfrtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK_N ,
//# {{power|Power}}
input SLEEP_B
);
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRSDFRTN_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; template <class T> inline T abs(T x) { return x < 0 ? -x : x; } const double EPS = 1e-9; int n, m, a[55], b[55], mx, ans, x; double cur; int main() { scanf( %d , &n); for (int i = 0; i < n; ++i) scanf( %d , a + i); scanf( %d , &m); for (int i = 0; i < m; ++i) scanf( %d , b + i); mx = 0; ans = 0; for (int i = 0; i < n; ++i) for (int j = 0; j < m; ++j) { cur = (b[j] + 0.) / a[i]; if (abs((int)cur - cur) < EPS) { x = (int)cur; if (x > mx) { mx = x; ans = 1; } else if (x == mx) ++ans; } } printf( %d , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int t = 1; while (t--) { long long n, min, cnt = 0, x; cin >> n; vector<long long> v(n); for (int i = 0; i < n; ++i) cin >> v[i]; min = *min_element(v.begin(), v.end()); for (int i = 0; i < n; ++i) { if (min == v[i]) { cnt++; x = i; } } if (cnt > 1) cout << Still Rozdil << endl; else cout << x + 1 << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; vector<pair<int, int> > arr[111]; int vis[111], maxs; void dfs(int now, int wei) { if (vis[now]) return; vis[now] = 1; maxs = max(maxs, wei); for (int e = 0; e < arr[now].size(); e++) { int next = arr[now][e].first, n_wei = wei + arr[now][e].second; if (vis[next]) continue; dfs(next, n_wei); } } int main(void) { int n; cin >> n; for (int e = 0; e < n - 1; e++) { int a, b, c; cin >> a >> b >> c; arr[a].push_back(make_pair(b, c)); arr[b].push_back(make_pair(a, c)); } dfs(0, 0); cout << maxs; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 3e5 + 7; const int inf = 1e9; char s[60][60]; char s1[60]; int l; int n; int num[60]; int check(char *s) { for (int i = 0; i < l; ++i) { int j; for (j = 0; j < l; ++j) { if (s1[j] != s[(j + i) % l]) break; } if (j >= l) return i; } return -1; } int main() { scanf( %d , &n); for (int i = 0; i < n; ++i) scanf( %s , s[i]); l = strlen(s[0]); int ans = inf; for (int i = 0; i < l; ++i) { int sum = 0; for (int j = 0; j < l; ++j) s1[j] = s[0][(j + i) % l]; for (int j = 0; j < n; ++j) { int t = check(s[j]); if (t == -1) { puts( -1 ); return 0; } sum += t; } ans = min(ans, sum); } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; long long arr[100005], ans[2]; int main() { int n, m; scanf( %d%d , &n, &m); for (int i = 0; i < n; i++) { scanf( %lld , arr + i); } for (int sum = 1; sum <= m << 1; sum++) { vector<int> vec = {0}; for (int i = 0; i < n; i++) { vec.push_back(arr[i] % sum); } vec.push_back(sum - 1); sort(vec.begin(), vec.end()); for (int i = n + 1, t = 0; i; i--, t ^= 1) { int x = max(vec[i - 1], vec[n - t] / 2) + 1, y = min(vec[i], m); int a = max(x, sum - y), b = min(y, sum - x); if (a <= b) ans[t] += b - a + 1; } } long long x = ((long long)m * m - ans[0] - ans[1]) / 2; printf( %lld %lld %lld %lld n , x, x, ans[1], ans[0]); return 0; } |
module mojo_top(
// 50MHz clock input
input clk,
// Input from reset button (active low)
input rst_n,
// cclk input from AVR, high when AVR is ready
input cclk,
// Outputs to the 8 onboard LEDs
output [7:0] led,
// AVR SPI connections
output spi_miso,
input spi_ss,
input spi_mosi,
input spi_sck,
// AVR ADC channel select
output [3:0] spi_channel,
// Serial connections
input avr_tx, // AVR Tx => FPGA Rx
output avr_rx, // AVR Rx => FPGA Tx
input avr_rx_busy, // AVR Rx buffer full
// external interfaces
output [7:0] dac, // external 8-bit dac
input [4:0] button // external buttons
);
wire rst = ~rst_n; // make reset active high
wire [3:0] gen; // hook up to wave generators
// these signals should be high-z when not used
assign spi_miso = 1'bz;
assign avr_rx = 1'bz;
assign spi_channel = 4'bzzzz;
// ADC input(s)
wire [3:0] channel;
wire new_sample;
wire [9:0] sample;
wire [3:0] sample_channel;
wire [7:0] adc_wire;
wire [24-1:0] m_period;
assign m_period = (1 << 8) * adc_wire;
// Button indicators
// XXX LEDs now tied to potentiometer
// assign led = {0,0,0,0,button[3:0]};
// DAC output levels on the 4 voices
//
localparam a0 = 16; // 8'd128;
localparam a1 = 32; // 8'd64;
localparam a2 = 64; // 8'd32;
localparam a3 = 128; // 8'd16;
// XXX Why does this fail to update?
// assign dac[7:0] = a0 & {8{gen[0] & button[0]}} +
// a1 & {8{gen[1] & button[1]}} +
// a2 & {8{gen[2] & button[2]}} +
// a3 & {8{gen[3] & button[3]}};
assign dac[7:0] = (gen[0] & button[0] ? a0 : 0) +
(gen[1] & button[1] ? a1 : 0) +
(gen[2] & button[2] ? a2 : 0) +
(gen[3] & button[3] ? a3 : 0);
// Square waveforms with 4 different frequencies
// (controlled by the p_i paramters) and 50% duty
// cycle (controlled by the compare parameters)
//
localparam p0 = 1 << 12;
localparam p1 = 1 << 14;
localparam p2 = 1 << 16;
localparam p3 = 1 << 18;
pwm pwm0 (
.clk(clk),
.rst(rst),
.period(p0),
.compare(p0/2),
.pwm(gen[0])
);
pwm pwm1 (
.rst(rst),
.clk(clk),
.period(p1),
.compare(p1/2),
.pwm(gen[1])
);
pwm pwm2 (
.rst(rst),
.clk(clk),
.period(p2),
.compare(p2/2),
.pwm(gen[2])
);
pwm pwm3 (
.rst(rst),
.clk(clk),
.period(m_period),
.compare(m_period/2),
.pwm(gen[3])
);
// PWM test
//
// generate 8 pulse waveforms and output to LED array
// genvar i;
// generate
// for (i = 0; i < 8; i=i+1) begin: pwm_gen_loop
// pwm #(.CTR_SIZE(3)) pwm (
// .rst(rst),
// .clk(clk),
// .compare(i),
// .pwm(led[i])
// );
// end
// endgenerate
// Blinker test
//
//assign led[7:1] = 7'b0101010;
//blinker blinkLastLed(.clk(clk), .rst(rst), .blink(led[0]));
// Interface with microcontroller
avr_interface avr_interface (
.clk(clk),
.rst(rst),
.cclk(cclk),
.spi_miso(spi_miso),
.spi_mosi(spi_mosi),
.spi_sck(spi_sck),
.spi_ss(spi_ss),
.spi_channel(spi_channel),
.tx(avr_rx),
.rx(avr_tx),
.channel(channel),
.new_sample(new_sample),
.sample(sample),
.sample_channel(sample_channel),
.tx_data(8'h00),
.new_tx_data(1'b0),
.tx_busy(),
.tx_block(avr_rx_busy),
.rx_data(),
.new_rx_data()
);
// ADC sampler
analog_input analog_input (
.clk(clk),
.rst(rst),
.channel(channel),
.new_sample(new_sample),
.sample(sample),
.sample_channel(sample_channel),
.out(adc_wire)
);
wire led_pwm_wire;
assign led = {8{led_pwm_wire}};
pwm led_pwm ( // 10bit PWM
.clk(clk),
.rst(rst),
.period({10{1'b1}}),
.compare(adc_wire),
.pwm(led_pwm_wire)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A211OI_SYMBOL_V
`define SKY130_FD_SC_LS__A211OI_SYMBOL_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a211oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A211OI_SYMBOL_V
|
#include <bits/stdc++.h> int v[1000001]; using namespace std; int main() { int a, b, c, d; scanf( %d%d%d%d , &a, &b, &c, &d); while (b <= 1000000) { v[b] = 1; b += a; } while (d <= 1000000) { if (v[d] == 1) { printf( %d , d); return 0; } d += c; } printf( -1 ); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Xilinx
// Engineer: Parimal Patel
// Create Date: 04/13/2017
// Module Name: trace_generator_controller
// Project Name: PYNQ
//////////////////////////////////////////////////////////////////////////////////
module trace_generator_controller #(parameter ADDR_WIDTH = 18)(
input clk,
// controls_input are multiple clocks wide as they are generated by GPIO write
// [0] = start, [1] = stop, [2] = DPG, [3] = FSM, [4] = Trace only, [5] = Step
// [5], [4] and [0] are used
input [5:0] controls_input,
input [ADDR_WIDTH-1:0] numSample, // Maximum number of samples = BRAM depth = 128K Words
input reset_n,
output reg trace_enb_1d
);
reg step_executed, step_executed_1;
wire start;
wire stop;
wire cnt_done;
wire step;
reg [ADDR_WIDTH-1:0] count;
reg trace_enb;
// pulsed output generation
pulse_gen sync_start(.async_in(controls_input[0]&controls_input[4]), .sync_clk(clk), .pulsed_out(start));
pulse_gen sync_stop(.async_in(controls_input[1]&controls_input[4]), .sync_clk(clk), .pulsed_out(stop));
pulse_gen sync_step(.async_in(controls_input[5]&controls_input[4]), .sync_clk(clk), .pulsed_out(step));
assign cnt_done = (count == (numSample-1)) ? 1'b1 : 1'b0;
always @(posedge clk)
if (!reset_n)
count <= 0;
else if((start) || (cnt_done) || (stop))
count <= 0;
else if(trace_enb | step_executed)
count <= count + 1;
else
count <= count;
always @(posedge clk)
if (!reset_n)
trace_enb_1d <= 0;
else
trace_enb_1d <= (trace_enb | step_executed);
always @(posedge clk)
if (!reset_n)
begin
trace_enb <= 0;
step_executed <= 0;
step_executed_1 <= 0;
end
else
begin
if(start) // start asserted
begin
trace_enb <= 1;
step_executed <= 0;
end
else if(stop) // stop asserted
begin
trace_enb <= 0;
step_executed <= 0;
end
else if (cnt_done)
begin
trace_enb <= 0;
end
else if(step)
begin
step_executed <= 1;
step_executed_1 <= 0;
end
else if(step_executed)
begin
step_executed <= 0;
step_executed_1 <= 1;
end
else if(step_executed_1)
begin
step_executed_1 <= 0;
end
else
begin
trace_enb <= trace_enb;
end
end
endmodule |
//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name I/O size props
// result_valid O 1
// result_value O 64 reg
// CLK I 1 clock
// RST_N I 1 reset
// put_args_x_is_signed I 1
// put_args_x I 32
// put_args_y_is_signed I 1
// put_args_y I 32
// EN_put_args I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkIntMul_32(CLK,
RST_N,
put_args_x_is_signed,
put_args_x,
put_args_y_is_signed,
put_args_y,
EN_put_args,
result_valid,
result_value);
input CLK;
input RST_N;
// action method put_args
input put_args_x_is_signed;
input [31 : 0] put_args_x;
input put_args_y_is_signed;
input [31 : 0] put_args_y;
input EN_put_args;
// value method result_valid
output result_valid;
// value method result_value
output [63 : 0] result_value;
// signals for module outputs
wire [63 : 0] result_value;
wire result_valid;
// register m_rg_isNeg
reg m_rg_isNeg;
wire m_rg_isNeg$D_IN, m_rg_isNeg$EN;
// register m_rg_signed
reg m_rg_signed;
wire m_rg_signed$D_IN, m_rg_signed$EN;
// register m_rg_state
reg [1 : 0] m_rg_state;
wire [1 : 0] m_rg_state$D_IN;
wire m_rg_state$EN;
// register m_rg_x
reg [63 : 0] m_rg_x;
wire [63 : 0] m_rg_x$D_IN;
wire m_rg_x$EN;
// register m_rg_xy
reg [63 : 0] m_rg_xy;
wire [63 : 0] m_rg_xy$D_IN;
wire m_rg_xy$EN;
// register m_rg_y
reg [31 : 0] m_rg_y;
wire [31 : 0] m_rg_y$D_IN;
wire m_rg_y$EN;
// rule scheduling signals
wire CAN_FIRE_RL_m_compute,
CAN_FIRE_put_args,
WILL_FIRE_RL_m_compute,
WILL_FIRE_put_args;
// inputs to muxes for submodule ports
wire [63 : 0] MUX_m_rg_x$write_1__VAL_1,
MUX_m_rg_x$write_1__VAL_2,
MUX_m_rg_xy$write_1__VAL_2;
wire [31 : 0] MUX_m_rg_y$write_1__VAL_1, MUX_m_rg_y$write_1__VAL_2;
// remaining internal signals
wire [63 : 0] x__h274, x__h367, xy___1__h291;
wire [31 : 0] _theResult___fst__h528,
_theResult___fst__h531,
_theResult___fst__h573,
_theResult___fst__h576,
_theResult___snd_fst__h568;
wire IF_put_args_x_is_signed_THEN_put_args_x_BIT_31_ETC___d34;
// action method put_args
assign CAN_FIRE_put_args = 1'd1 ;
assign WILL_FIRE_put_args = EN_put_args ;
// value method result_valid
assign result_valid = m_rg_state == 2'd2 ;
// value method result_value
assign result_value = m_rg_xy ;
// rule RL_m_compute
assign CAN_FIRE_RL_m_compute = m_rg_state == 2'd1 ;
assign WILL_FIRE_RL_m_compute = CAN_FIRE_RL_m_compute ;
// inputs to muxes for submodule ports
assign MUX_m_rg_x$write_1__VAL_1 = { 32'd0, _theResult___fst__h528 } ;
assign MUX_m_rg_x$write_1__VAL_2 = { m_rg_x[62:0], 1'd0 } ;
assign MUX_m_rg_xy$write_1__VAL_2 = (m_rg_y == 32'd0) ? x__h274 : x__h367 ;
assign MUX_m_rg_y$write_1__VAL_1 =
(put_args_x_is_signed && put_args_y_is_signed) ?
_theResult___fst__h576 :
_theResult___snd_fst__h568 ;
assign MUX_m_rg_y$write_1__VAL_2 = { 1'd0, m_rg_y[31:1] } ;
// register m_rg_isNeg
assign m_rg_isNeg$D_IN =
(put_args_x_is_signed && put_args_y_is_signed) ?
put_args_x[31] != put_args_y[31] :
IF_put_args_x_is_signed_THEN_put_args_x_BIT_31_ETC___d34 ;
assign m_rg_isNeg$EN = EN_put_args ;
// register m_rg_signed
assign m_rg_signed$D_IN = 1'b0 ;
assign m_rg_signed$EN = 1'b0 ;
// register m_rg_state
assign m_rg_state$D_IN = EN_put_args ? 2'd1 : 2'd2 ;
assign m_rg_state$EN =
WILL_FIRE_RL_m_compute && m_rg_y == 32'd0 || EN_put_args ;
// register m_rg_x
assign m_rg_x$D_IN =
EN_put_args ?
MUX_m_rg_x$write_1__VAL_1 :
MUX_m_rg_x$write_1__VAL_2 ;
assign m_rg_x$EN =
WILL_FIRE_RL_m_compute && m_rg_y != 32'd0 || EN_put_args ;
// register m_rg_xy
assign m_rg_xy$D_IN = EN_put_args ? 64'd0 : MUX_m_rg_xy$write_1__VAL_2 ;
assign m_rg_xy$EN =
WILL_FIRE_RL_m_compute && (m_rg_y == 32'd0 || m_rg_y[0]) ||
EN_put_args ;
// register m_rg_y
assign m_rg_y$D_IN =
EN_put_args ?
MUX_m_rg_y$write_1__VAL_1 :
MUX_m_rg_y$write_1__VAL_2 ;
assign m_rg_y$EN =
WILL_FIRE_RL_m_compute && m_rg_y != 32'd0 || EN_put_args ;
// remaining internal signals
assign IF_put_args_x_is_signed_THEN_put_args_x_BIT_31_ETC___d34 =
put_args_x_is_signed ?
put_args_x[31] :
put_args_y_is_signed && put_args_y[31] ;
assign _theResult___fst__h528 =
put_args_x_is_signed ? _theResult___fst__h531 : put_args_x ;
assign _theResult___fst__h531 = put_args_x[31] ? -put_args_x : put_args_x ;
assign _theResult___fst__h573 =
put_args_y_is_signed ? _theResult___fst__h576 : put_args_y ;
assign _theResult___fst__h576 = put_args_y[31] ? -put_args_y : put_args_y ;
assign _theResult___snd_fst__h568 =
put_args_x_is_signed ? put_args_y : _theResult___fst__h573 ;
assign x__h274 = m_rg_isNeg ? xy___1__h291 : m_rg_xy ;
assign x__h367 = m_rg_xy + m_rg_x ;
assign xy___1__h291 = -m_rg_xy ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
m_rg_state <= `BSV_ASSIGNMENT_DELAY 2'd0;
end
else
begin
if (m_rg_state$EN)
m_rg_state <= `BSV_ASSIGNMENT_DELAY m_rg_state$D_IN;
end
if (m_rg_isNeg$EN) m_rg_isNeg <= `BSV_ASSIGNMENT_DELAY m_rg_isNeg$D_IN;
if (m_rg_signed$EN) m_rg_signed <= `BSV_ASSIGNMENT_DELAY m_rg_signed$D_IN;
if (m_rg_x$EN) m_rg_x <= `BSV_ASSIGNMENT_DELAY m_rg_x$D_IN;
if (m_rg_xy$EN) m_rg_xy <= `BSV_ASSIGNMENT_DELAY m_rg_xy$D_IN;
if (m_rg_y$EN) m_rg_y <= `BSV_ASSIGNMENT_DELAY m_rg_y$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
m_rg_isNeg = 1'h0;
m_rg_signed = 1'h0;
m_rg_state = 2'h2;
m_rg_x = 64'hAAAAAAAAAAAAAAAA;
m_rg_xy = 64'hAAAAAAAAAAAAAAAA;
m_rg_y = 32'hAAAAAAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkIntMul_32
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_cpu_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
)
;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input test_ending;
input test_has_ended;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, m, i, j, k, c = 0, sm = 0, t = 0, ans = 0; cin >> n >> m; int a[n + 2], b[n + 2]; for (i = 0; i < n; i++) cin >> a[i]; for (i = 0; i < n; i++) { sm += a[i]; if (sm > m) { sm -= a[t]; ++t; } else { ++c; if (c < ans) ans = c; } if (c < 0) c = 0; } if (ans < c) ans = c; cout << ans << endl; return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC target( avx,avx2,fma ) using namespace std; using ll = long long; using ull = unsigned long long; template <typename T> void print(vector<T> v) { for (T i : v) cout << i << ; cout << n ; } template <typename T> void print(vector<vector<T>>& v) { for (vector<T>& vv : v) { for (T& i : vv) cout << i << ; cout << n ; } } template <typename T> void print(T&& t) { cout << t << n ; } template <typename T, typename... Args> void print(T&& t, Args&&... args) { cout << t << ; print(forward<Args>(args)...); } template <typename T> istream& operator>>(istream& is, vector<T>& v) { for (auto& i : v) is >> i; return is; } template <typename T> ostream& operator<<(ostream& os, vector<T>& v) { for (auto& i : v) os << i << ; return os; } void __print(int x) { cerr << x; } void __print(long x) { cerr << x; } void __print(long long x) { cerr << x; } void __print(unsigned x) { cerr << x; } void __print(unsigned long x) { cerr << x; } void __print(unsigned long long x) { cerr << x; } void __print(float x) { cerr << x; } void __print(double x) { cerr << x; } void __print(long double x) { cerr << x; } void __print(char x) { cerr << << x << ; } void __print(const char* x) { cerr << << x << ; } void __print(const string& x) { cerr << << x << ; } void __print(bool x) { cerr << (x ? true : false ); } template <typename T, typename V> void __print(const pair<T, V>& x) { cerr << { ; __print(x.first); cerr << , ; __print(x.second); cerr << } ; } template <typename T> void __print(const T& x) { int f = 0; cerr << { ; for (auto& i : x) cerr << (f++ ? , : ), __print(i); cerr << } ; } void _print() { cerr << ] n ; } template <typename T, typename... V> void _print(T t, V... v) { __print(t); if (sizeof...(v)) cerr << , ; _print(v...); } void loop() { ll n; cin >> n; vector<ll> a(n); cin >> a; if (n == 1) { print( Alice ); return; } vector<ll> inc, dec; inc.push_back(a[0]); for (ll i = 0; i < n - 1; i++) { if (a[i] < a[i + 1]) { inc.push_back(a[i + 1]); } else break; } dec.push_back(a[n - 1]); for (ll i = n - 1; i > 0; i--) { if (a[i] < a[i - 1]) { dec.push_back(a[i - 1]); } else break; } if (dec.size() % 2) { print( Alice ); return; } else if ((inc.size() - 1 + dec.size()) % 2 == 0) { print( Alice ); return; } print( Bob ); } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ll t; t = 1; while (t--) { loop(); } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O41AI_SYMBOL_V
`define SKY130_FD_SC_MS__O41AI_SYMBOL_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o41ai (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input A4,
input B1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O41AI_SYMBOL_V
|
/*
*
* Copyright (c) 2011-2012
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
module comm (
input hash_clk,
input rx_new_nonce,
input [31:0] rx_golden_nonce,
output [255:0] tx_midstate,
output [95:0] tx_data
);
reg [351:0] jtag_data_shift = 352'd0;
reg [255:0] midstate = 256'd0;
reg [95:0] data = 96'd0;
assign tx_midstate = midstate;
assign tx_data = data;
reg [31:0] golden_out = 32'd0;
reg [3:0] golden_count = 3'd0;
reg read = 1'b0;
wire [8:0] jtag_data;
wire full, empty;
reg [5:0] jtag_data_count = 6'd0;
wire golden_writing = golden_count[0];
jtag_fifo jtag_fifo_blk (
.rx_clk (hash_clk),
.rx_data ({golden_count, golden_out[7:0]}),
.wr_en (golden_writing & ~full),
.rd_en (read),
.tx_data (jtag_data),
.tx_full (full),
.tx_empty (empty)
);
always @ (posedge hash_clk)
begin
// Writing to JTAG
if (!golden_writing & rx_new_nonce)
begin
golden_out <= rx_golden_nonce;
golden_count <= 4'b1111;
end
else if (golden_writing & !full)
begin
golden_out <= golden_out >> 8;
golden_count <= {1'b0, golden_count[3:1]};
end
// Reading from JTAG
if (!empty & !read)
read <= 1'b1;
if (read)
begin
read <= 1'b0;
jtag_data_shift <= {jtag_data_shift[343:0], jtag_data[7:0]};
if (jtag_data[8] == 1'b0)
jtag_data_count <= 6'd1;
else if (jtag_data_count == 6'd43)
begin
jtag_data_count <= 6'd0;
{midstate, data} <= {jtag_data_shift[343:0], jtag_data[7:0]};
end
else
jtag_data_count <= jtag_data_count + 6'd1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 505, maxmax = 1000000; int n, javab[maxn][maxn]; vector<int> v; int dp(int l, int r) { int x = maxmax; if (l == r) { javab[l][r] = 1; return 1; } if (l == r - 1) { if (v[r] == v[l]) { javab[l][r] = 1; return 1; } else { javab[l][r] = 2; return 2; } } if (javab[l][r - 1] != 0) x = min(x, javab[l][r - 1] + 1); else { x = min(x, dp(l, r - 1) + 1); } for (int i = r - 1; i >= l; i--) { if (v[r] == v[i]) { if (i == l) { if (javab[l + 1][r - 1] != 0) { x = min(x, javab[l + 1][r - 1]); } else x = min(x, dp(l + 1, r - 1)); break; } if (javab[l][i - 1] != 0) { if (javab[i][r] != 0) { x = min(x, javab[l][i - 1] + javab[i][r]); } else { x = min(x, javab[l][i - 1] + dp(i, r)); } } else { if (javab[i][r] != 0) { x = min(x, dp(l, i - 1) + javab[i][r]); } else { x = min(x, dp(l, i - 1) + dp(i, r)); } } } } javab[l][r] = x; return x; } int main() { cin >> n; for (int i = 0; i < n; i++) { int x; cin >> x; v.push_back(x); } int javab = dp(0, v.size() - 1); cout << javab; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EDFXTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__EDFXTP_FUNCTIONAL_PP_V
/**
* edfxtp: Delay flop with loopback enable, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_hd__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__edfxtp (
Q ,
CLK ,
D ,
DE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D, DE );
sky130_fd_sc_hd__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__EDFXTP_FUNCTIONAL_PP_V |
//////////////////////////////////////////////////////////////////
// //
// Fetch - Instantiates the fetch stage sub-modules of //
// the Amber 25 Core //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// Instantiates the Cache and Wishbone I/F //
// Also contains a little bit of logic to decode memory //
// accesses to decide if they are cached or not //
// //
// Author(s): //
// - Conor Santifort, //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2011 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
module a25_fetch
(
input i_clk,
input i_mem_stall,
input i_exec_stall,
input i_conflict, // Decode stage stall pipeline because of an instruction conflict
output o_fetch_stall, // when this is asserted all registers
// in decode and exec stages are frozen
input i_system_rdy, // External system can stall core with this signal
input [31:0] i_iaddress,
input i_iaddress_valid,
input [31:0] i_iaddress_nxt, // un-registered version of address to the cache rams
output [31:0] o_fetch_instruction,
input i_cache_enable, // cache enable
input i_cache_flush, // cache flush
input [31:0] i_cacheable_area, // each bit corresponds to 2MB address space
output o_wb_req,
output [31:0] o_wb_address,
input [127:0] i_wb_read_data,
input i_wb_ready
);
`include "memory_configuration.v"
wire core_stall;
wire cache_stall;
wire [127:0] cache_read_data128;
wire [31:0] cache_read_data;
wire sel_cache;
wire uncached_instruction_read;
wire address_cachable;
wire icache_wb_req;
wire wait_wb;
reg wb_req_r = 'd0;
wire [31:0] wb_rdata32;
// ======================================
// Memory Decode
// ======================================
assign address_cachable = in_cachable_mem( i_iaddress ) && i_cacheable_area[i_iaddress[25:21]];
assign sel_cache = address_cachable && i_iaddress_valid && i_cache_enable;
// Don't start wishbone transfers when the cache is stalling the core
// The cache stalls the core during its initialization sequence
assign uncached_instruction_read = !sel_cache && i_iaddress_valid && !(cache_stall);
// Return read data either from the wishbone bus or the cache
assign cache_read_data = i_iaddress[3:2] == 2'd0 ? cache_read_data128[ 31: 0] :
i_iaddress[3:2] == 2'd1 ? cache_read_data128[ 63:32] :
i_iaddress[3:2] == 2'd2 ? cache_read_data128[ 95:64] :
cache_read_data128[127:96] ;
assign wb_rdata32 = i_iaddress[3:2] == 2'd0 ? i_wb_read_data[ 31: 0] :
i_iaddress[3:2] == 2'd1 ? i_wb_read_data[ 63:32] :
i_iaddress[3:2] == 2'd2 ? i_wb_read_data[ 95:64] :
i_wb_read_data[127:96] ;
assign o_fetch_instruction = sel_cache ? cache_read_data :
uncached_instruction_read ? wb_rdata32 :
32'hffeeddcc ;
// Stall the instruction decode and execute stages of the core
// when the fetch stage needs more than 1 cycle to return the requested
// read data
assign o_fetch_stall = !i_system_rdy || wait_wb || cache_stall;
assign o_wb_address = i_iaddress;
assign o_wb_req = icache_wb_req || uncached_instruction_read;
assign wait_wb = (o_wb_req || wb_req_r) && !i_wb_ready;
always @(posedge i_clk)
wb_req_r <= o_wb_req && !i_wb_ready;
assign core_stall = o_fetch_stall || i_mem_stall || i_exec_stall || i_conflict;
// ======================================
// L1 Instruction Cache
// ======================================
a25_icache u_cache (
.i_clk ( i_clk ),
.i_core_stall ( core_stall ),
.o_stall ( cache_stall ),
.i_select ( sel_cache ),
.i_address ( i_iaddress ),
.i_address_nxt ( i_iaddress_nxt ),
.i_cache_enable ( i_cache_enable ),
.i_cache_flush ( i_cache_flush ),
.o_read_data ( cache_read_data128 ),
.o_wb_req ( icache_wb_req ),
.i_wb_read_data ( i_wb_read_data ),
.i_wb_ready ( i_wb_ready )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int pos[4][2] = {{1, 0}, {0, 1}, {-1, 0}, {0, -1}}; int n; char s[510][510]; int v[510][510]; vector<pair<int, int> > vec, ans; int operator*(const pair<int, int> &a, const pair<int, int> &b) { return a.first * b.second - a.second * b.first; } pair<int, int> operator-(const pair<int, int> &a, const pair<int, int> &b) { return make_pair(a.first - b.first, a.second - b.second); } pair<int, int> stk[250010]; int main() { while (1) { ans.clear(); scanf( %d , &n); if (n == 0) break; for (int i = n; i >= 1; i--) scanf( %s , s[i] + 1); for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) v[i][j] = s[i][j] - 0 ; vec.clear(); for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { int cnt = 0; for (int k = -1; k <= 0; k++) { for (int l = -1; l <= 0; l++) { cnt += v[i + k][j + l]; } } if (cnt == 1) { if (v[i][j] == 1) vec.push_back(make_pair(i, j)); else if (v[i - 1][j] == 1) vec.push_back(make_pair(i - 2, j)); else if (v[i][j - 1] == 1) vec.push_back(make_pair(i, j - 2)); else vec.push_back(make_pair(i - 2, j - 2)); } } } for (auto &x : vec) swap(x.first, x.second); sort(vec.begin(), vec.end()); int top = 0; for (auto &x : vec) { while (top > 1 && (stk[top] - stk[top - 1]) * (x - stk[top]) >= 0) top--; stk[++top] = x; } for (int i = 1; i <= top; i++) ans.push_back(stk[i]); reverse(vec.begin(), vec.end()); top = 0; for (auto &x : vec) { while (top > 1 && (stk[top] - stk[top - 1]) * (x - stk[top]) >= 0) top--; stk[++top] = x; } for (int i = 2; i < top; i++) ans.push_back(stk[i]); printf( %d n , ans.size()); for (auto &x : ans) printf( %d %d n , x.first, x.second); } return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2008 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Outputs
q,
// Inputs
clk, d
);
input clk;
input d;
output wire [1:0] q;
// This demonstrates how warning disables should be propagated across module boundaries.
m1 m1 (/*AUTOINST*/
// Outputs
.q (q[1:0]),
// Inputs
.clk (clk),
.d (d));
endmodule
module m1
(
input clk,
input d,
output wire [1:0] q
);
m2 m2 (/*AUTOINST*/
// Outputs
.q (q[1:0]),
// Inputs
.clk (clk),
.d (d));
endmodule
module m2
(
input clk,
input d,
// Due to bug the below disable used to be ignored.
// verilator lint_off UNOPT
// verilator lint_off UNOPTFLAT
output reg [1:0] q
// verilator lint_on UNOPT
// verilator lint_on UNOPTFLAT
);
always @* begin
q[1] = d;
end
always @* begin
q[0] = q[1];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; set<int> s; cin >> n; int i, j; for (i = 0; i < n; i++) { cin >> j; if (j != 0) s.insert(j); } cout << s.size(); } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m, v; scanf( %d%d%d , &n, &m, &v); int spec = 1; if (m < n - 1 || m > (n - 1) * (n - 2) / 2 + 1) { printf( -1 n ); return 0; } if (spec == v) spec++; printf( %d %d n , v, spec); m--; for (int i = 1; i <= n; i++) { if (i == spec) continue; for (int j = i + 1; j <= n; j++) { if (j == spec) continue; printf( %d %d n , i, j); m--; if (m == 0) return 0; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, k; int a[1000000]; vector<pair<int, int> > ans; int main() { ios_base::sync_with_stdio(false); cin >> n >> k; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 1; i <= k; i++) { int high = 1, low = 1; for (int j = 2; j <= n; j++) { if (a[j] > a[high]) high = j; if (a[j] < a[low]) low = j; } if (high != low) { ans.push_back(make_pair(high, low)); a[high]--; a[low]++; } } int high = 1, low = 1; for (int j = 2; j <= n; j++) { if (a[j] > a[high]) high = j; if (a[j] < a[low]) low = j; } int s = ans.size(); cout << a[high] - a[low] << << s << endl; ; for (int i = 0; i <= s - 1; i++) cout << ans[i].first << << ans[i].second << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; int sum(int a, int b) { return a + b >= MOD ? a + b - MOD : a + b; } int sub(int a, int b) { return a - b < 0 ? a - b + MOD : a - b; } int mul(int a, int b) { return (1LL * a * b) % MOD; } const int MAXN = 1e6 + 7; int shuru[MAXN], shesh[MAXN]; int zero[MAXN]; int main() { ios::sync_with_stdio(false); cin.tie(0); string s; cin >> s; int n = s.size(); int zerosum = 1; int sheshsum = 0; int z = 0; for (int i = n - 1; i >= 0; i--) { if (s[i] == 0 ) { z++; if (i + z == n) zerosum = sum(zerosum, 1); zerosum = sub(zerosum, zero[z]); zero[z] = shuru[i + z]; zerosum = sum(zerosum, zero[z]); } else { z = 0; shesh[i] = zerosum; sheshsum = sum(sheshsum, shesh[i]); shuru[i] = sheshsum; } } if (z == n) { cout << n << n ; } else { cout << mul(z + 1, shuru[z]) << n ; } return 0; } |
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: ram.v
//
// *Module Description:
// Scalable RAM model
//
// *Author(s):
// - Olivier Girard,
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
module ram (
// OUTPUTs
ram_dout, // RAM data output
// INPUTs
ram_addr, // RAM address
ram_cen, // RAM chip enable (low active)
ram_clk, // RAM clock
ram_din, // RAM data input
ram_wen // RAM write enable (low active)
);
// PARAMETERs
//============
parameter ADDR_MSB = 6; // MSB of the address bus
parameter MEM_SIZE = 256; // Memory size in bytes
// OUTPUTs
//============
output [15:0] ram_dout; // RAM data output
// INPUTs
//============
input [ADDR_MSB:0] ram_addr; // RAM address
input ram_cen; // RAM chip enable (low active)
input ram_clk; // RAM clock
input [15:0] ram_din; // RAM data input
input [1:0] ram_wen; // RAM write enable (low active)
// RAM
//============
reg [15:0] mem [0:(MEM_SIZE/2)-1];
reg [ADDR_MSB:0] ram_addr_reg;
wire [15:0] mem_val = mem[ram_addr];
always @(posedge ram_clk)
if (~ram_cen & ram_addr<(MEM_SIZE/2))
begin
if (ram_wen==2'b00) mem[ram_addr] <= ram_din;
else if (ram_wen==2'b01) mem[ram_addr] <= {ram_din[15:8], mem_val[7:0]};
else if (ram_wen==2'b10) mem[ram_addr] <= {mem_val[15:8], ram_din[7:0]};
ram_addr_reg <= ram_addr;
end
assign ram_dout = mem[ram_addr_reg];
endmodule // ram
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O22A_SYMBOL_V
`define SKY130_FD_SC_LP__O22A_SYMBOL_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o22a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O22A_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, x1, x2, y1, y2; cin >> n >> m >> x1 >> y1 >> x2 >> y2; int dx = abs(x2 - x1); int dy = abs(y2 - y1); if (dx <= 4 && dy <= 2 || dy <= 4 && dx <= 2 || dx == 3 && dy == 3) { cout << First ; } else { cout << Second ; } } |
#include <bits/stdc++.h> using namespace std; int dp[5005][5005]; string s; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> s; memset(dp, -1, sizeof dp); int ans = 0; for (int i = 0; i < s.size(); i++) { int can_rev = 0; int cur = 0; for (int j = i; j < s.size(); j++) { if (cur == 0) ans++; if (s[j] == ( ) { cur++; } else if (s[j] == ) ) { cur--; if (cur < 0) { if (can_rev == 0) break; can_rev--; cur += 2; } } else { if (cur > 0) { cur--; can_rev++; } else { cur++; } } } if (cur == 0) ans++; ans--; } cout << ans << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int n; int s[4040][4040]; bool u[4040][4040], r[4040][4040]; int su[4040][4040], sr[4040][4040]; bool b[4040][4040]; int get(int x1, int y1, int x2, int y2) { return s[x2][y2] + s[x1 - 1][y1 - 1] - s[x1 - 1][y2] - s[x2][y1 - 1]; } struct Point { int x, y; Point() {} Point(int _x, int _y) { x = _x; y = _y; } bool operator<(const Point &b) const { if (x == b.x) return y < b.y; return x < b.x; } bool operator==(const Point &b) const { return x == b.x && y == b.y; } }; Point p[1010101]; int m; int X1[1010101], X2[1010101], Y1[1010101], Y2[1010101]; int out[1010101]; int ans = 0; int main() { std::ios::sync_with_stdio(false); cin >> n; for (int i = 1; i <= n; i++) { int x1, x2, y1, y2; cin >> x1 >> y1 >> x2 >> y2; X1[i] = x1; Y1[i] = y1; X2[i] = x2; Y2[i] = y2; for (int x = x1 + 1; x <= x2; x++) for (int y = y1 + 1; y <= y2; y++) b[x][y] = true; for (int x = x1; x < x2; x++) r[x][y1] = r[x][y2] = true; for (int y = y1; y < y2; y++) u[x1][y] = u[x2][y] = true; p[++m] = Point(x1, y1); p[++m] = Point(x1, y2); } sort(p + 1, p + 1 + m); m = unique(p + 1, p + 1 + m) - p - 1; s[0][0] = b[0][0]; su[0][0] = u[0][0]; sr[0][0] = r[0][0]; for (int j = 1; j <= 3005; j++) { s[0][j] = s[0][j - 1] + b[0][j]; su[0][j] = su[0][j - 1] + u[0][j]; sr[0][j] = r[0][j]; } for (int i = 1; i <= 3005; i++) { s[i][0] = s[i - 1][0] + b[i][0]; sr[i][0] = sr[i - 1][0] + r[i][0]; su[i][0] = u[i][0]; } for (int i = 1; i <= 3005; i++) for (int j = 1; j <= 3005; j++) { s[i][j] = s[i - 1][j] + s[i][j - 1] - s[i - 1][j - 1] + b[i][j]; su[i][j] = su[i][j - 1] + u[i][j]; sr[i][j] = sr[i - 1][j] + r[i][j]; } for (int i = 1; i <= m; i++) { int x = p[i].x, y = p[i].y; for (int j = i + 1; j <= m && p[j].x == x; j++) { int yy = p[j].y, len = p[j].y - y + 1; if (x + len - 1 > 3005) continue; int cnt = get(x + 1, y + 1, x + len - 1, y + len - 1); if (cnt != ((len - 1) * (len - 1))) continue; if (x == 0) { if (sr[x + len - 2][y] != len - 1) continue; if (sr[x + len - 2][yy] != len - 1) continue; } else { if (sr[x + len - 2][y] - sr[x - 1][y] != len - 1) continue; if (sr[x + len - 2][yy] - sr[x - 1][yy] != len - 1) continue; } if (y == 0) { if (su[x][yy - 1] != len - 1) continue; if (su[x + len - 1][yy - 1] != len - 1) continue; } else { if (su[x][yy - 1] - su[x][y - 1] != len - 1) continue; if (su[x + len - 1][yy - 1] - su[x + len - 1][y - 1] != len - 1) continue; } for (int k = 1; k <= n; k++) if (X1[k] >= x && X1[k] <= x + len - 1 && X2[k] >= x && X2[k] <= x + len - 1 && Y1[k] >= y && Y1[k] <= y + len - 1 && Y2[k] >= y && Y2[k] <= y + len - 1) { out[++ans] = k; } cout << YES << << ans << endl; for (int k = 1; k <= ans; k++) cout << out[k] << ; return 0; } } cout << NO << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m; scanf( %d %d , &n, &m); char s[n + 5]; scanf( %s , s); vector<int>* vp[30]; for (int i = 0; i <= 25; i++) vp[i] = new vector<int>(); for (int i = 0; s[i]; i++) { int now = s[i] - a ; vp[now]->push_back(i); } while (m--) { getchar(); char x, y; scanf( %c %c , &x, &y); int id1 = x - a ; int id2 = y - a ; swap(vp[id1], vp[id2]); } for (int i = 0; i <= 25; i++) { for (vector<int>::iterator it = vp[i]->begin(); it != vp[i]->end(); it++) { s[*it] = i + a ; } } printf( %s n , s); return 0; } |
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// Title : CRT Controller Data out
// File : dc_adout.v
// Author : Frank Bruno
// Created : 30-Dec-2005
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
module dc_adout
(
input pixclock,
input dcnreset,
input hnreset,
input vsync,
input cblank,
input rsuppr,
input [9:0] ff_stp,
input [9:0] ff_rls,
input [10:0] ovtl_y,
input [10:0] ovbr_y,
input [1:0] bpp,
input [127:0] crt_data,
input [7:0] vga_din,
input vga_en,
output reg [23:0] datdc_out,
output pop
);
reg [3:0] counter; // Cycle counter
reg [3:0] out_sel0, out_sel; // Delayed cycle count
reg [3:0] inc; // Increment value
reg cblankd; // Delayed cblank
reg [11:0] lcount; // Line Count
reg [9:0] pcount; // Page Counter
reg hdisbl;
reg vdisbl;
reg [31:0] crt_dat;
reg [7:0] vga_store; // Need one extra VGA storage cycle
wire [11:0] ff_yrls;
wire active; // High when we are actively counting
assign pop = cblank & (counter == 0);
assign active = ~(hdisbl & vdisbl & cblank & rsuppr);
// Determine the increment value - Registered so we won't multicycle
always @(posedge pixclock or negedge hnreset )
if(!hnreset) begin
inc <= 4'b0;
end else if (active)
casex (bpp)
2'b01: inc <= 4'h1; // 8 Bpp (unpacked)
2'b10: inc <= 4'h2; // 16 Bpp
default: inc <= 4'h4; // 32 Bpp
endcase // casex({greyscale_8bpp, bpp})
// Cycle Counter
always @(posedge pixclock or negedge hnreset )
if(!hnreset) begin
counter <= 4'b0;
end else if (!(vsync && cblank)) begin
counter <= 4'b0;
end else if (active) begin
counter <= counter + inc;
end
// Isolate data output so it will run even if all else is off
always @(posedge pixclock or negedge hnreset )
if(!hnreset) begin
vga_store <= 8'h0;
datdc_out <= 24'b0;
end else begin
// Delay the VGA data one cycle
vga_store <= vga_din;
// Data muxing from RAM
casex ({vga_en, bpp, out_sel[1:0]})
// VGA mode
5'b1_xx_xx: datdc_out <= {3{vga_store}};
// 8 bits per pixel.
5'b0_01_00: datdc_out <= {3{crt_dat[7:0]}};
5'b0_01_01: datdc_out <= {3{crt_dat[15:8]}};
5'b0_01_10: datdc_out <= {3{crt_dat[23:16]}};
5'b0_01_11: datdc_out <= {3{crt_dat[31:24]}};
// 16 bits per pixel.
5'b0_10_0x: datdc_out <= {8'h0, crt_dat[15:0]};
5'b0_10_1x: datdc_out <= {8'h0, crt_dat[31:16]};
// 32 bits per pixel.
5'b0_00_xx, 6'b0_0_11_xx: datdc_out <= crt_dat[23:0];
endcase // casex({greyscale_8bpp, bpp, out_sel})
end
always @(posedge pixclock or negedge hnreset )
if(!hnreset) begin
cblankd <= 1'b0;
lcount <= 12'b0;
pcount <= 10'b0;
hdisbl <= 1'b0;
vdisbl <= 1'b0;
out_sel0 <= 2'b0;
out_sel <= 2'b0;
end else if(!dcnreset) begin
cblankd <= 1'b0;
lcount <= 12'b0;
pcount <= 10'b0;
hdisbl <= 1'b0;
vdisbl <= 1'b0;
out_sel0 <= 2'b0;
out_sel <= 2'b0;
crt_dat <= 32'b0;
end else begin
// Delay the out select for muxing
out_sel0 <= counter;
out_sel <= out_sel0;
case (out_sel0[3:2])
2'd0: crt_dat <= crt_data[31:0];
2'd1: crt_dat <= crt_data[63:32];
2'd2: crt_dat <= crt_data[95:64];
2'd3: crt_dat <= crt_data[127:96];
endcase // case(out_sel0[3:2])
// Delay cblank for edge detection
cblankd <= cblank;
//count actual scan lines and pages to find where the output address
//should be held inside video overlay window. When the window ends,
//addresses have to point already to page where a valid data is stored.
// Line Counter
if (!(vsync & rsuppr)) lcount <= 12'b0; // unecessary tog supr
else if (cblankd & ~cblank) lcount <= lcount + 12'h1; // Count begin blank
// Page Counter
if(!(vsync & cblank & rsuppr)) pcount <= 10'b0; // don't toggle unnec
else if (pop) pcount <= pcount + 10'h1;
// Disable address increments
if (pcount == ff_stp) // Was Pcount_next. Fixme????
hdisbl <= 1'b1;
else if ((pcount == ff_rls) || !cblank) // Was Pcount_next. Fixme????
hdisbl <= 1'b0;
if (lcount == {1'b0,ovtl_y})
vdisbl <= 1'b1;
else if ((lcount == ff_yrls)|| !vsync)
vdisbl <= 1'b0;
end
assign ff_yrls = ovbr_y +1'b1;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int ax, ay, bx, by, cx, cy; double k1, k2, k3; int main() { long long int dis_ab, dis_ac, dis_bc, max_dis = -1; cin >> ax >> ay >> bx >> by >> cx >> cy; dis_ab = (ax - bx) * (ax - bx) + (ay - by) * (ay - by); k1 = (double)(ax - bx) / (ay - by); dis_ac = (ax - cx) * (ax - cx) + (ay - cy) * (ay - cy); k2 = (double)(ax - cx) / (ay - cy); dis_bc = (bx - cx) * (bx - cx) + (by - cy) * (by - cy); k3 = (double)(bx - cx) / (by - cy); if (k1 == k2 && k2 == k3) cout << No ; else { if (dis_ab == dis_bc) cout << Yes ; else cout << No ; } return 0; } |
module PS_flops_issue_lsu (
in_lsu_select,
in_wfid,
in_lds_base,
in_source_reg1,
in_source_reg2,
in_source_reg3,
in_mem_sgpr,
in_imm_value0,
in_imm_value1,
in_dest_reg,
in_opcode,
in_instr_pc,
out_lsu_select,
out_wfid,
out_lds_base,
out_source_reg1,
out_source_reg2,
out_source_reg3,
out_mem_sgpr,
out_imm_value0,
out_imm_value1,
out_dest_reg,
out_opcode,
out_instr_pc,
clk,
rst
);
input in_lsu_select;
input [5:0] in_wfid;
input [15:0] in_lds_base;
input [11:0] in_source_reg1;
input [11:0] in_source_reg2;
input [11:0] in_source_reg3;
input [11:0] in_mem_sgpr;
input [15:0] in_imm_value0;
input [31:0] in_imm_value1;
input [11:0] in_dest_reg;
input [31:0] in_opcode;
input [31:0] in_instr_pc;
input clk;
input rst;
output out_lsu_select;
output [5:0] out_wfid;
output [15:0] out_lds_base;
output [11:0] out_source_reg1;
output [11:0] out_source_reg2;
output [11:0] out_source_reg3;
output [11:0] out_mem_sgpr;
output [15:0] out_imm_value0;
output [31:0] out_imm_value1;
output [11:0] out_dest_reg;
output [31:0] out_opcode;
output [31:0] out_instr_pc;
//lsu_select is not enabled; all other flops are enabled
dff flop_lsu_select(
.q(out_lsu_select),
.d(in_lsu_select),
.clk(clk),
.rst(rst)
);
dff_en flop_wfid[5:0](
.q(out_wfid),
.d(in_wfid),
.clk(clk),
.rst(rst),
.en(in_lsu_select)
);
dff_en flop_lds_base[15:0](
.q(out_lds_base),
.d(in_lds_base),
.clk(clk),
.rst(rst),
.en(in_lsu_select)
);
dff_en flop_source_reg1[11:0](
.q(out_source_reg1),
.d(in_source_reg1),
.clk(clk),
.rst(rst),
.en(in_lsu_select)
);
dff_en flop_source_reg2[11:0](
.q(out_source_reg2),
.d(in_source_reg2),
.clk(clk),
.rst(rst),
.en(in_lsu_select)
);
dff_en flop_source_reg3[11:0](
.q(out_source_reg3),
.d(in_source_reg3),
.clk(clk),
.rst(rst),
.en(in_lsu_select)
);
dff_en flop_mem_sgpr[11:0](
.q(out_mem_sgpr),
.d(in_mem_sgpr),
.clk(clk),
.rst(rst),
.en(in_lsu_select)
);
dff_en flop_imm_value0[15:0](
.q(out_imm_value0),
.d(in_imm_value0),
.clk(clk),
.rst(rst),
.en(in_lsu_select)
);
dff_en flop_imm_value1[31:0](
.q(out_imm_value1),
.d(in_imm_value1),
.clk(clk),
.rst(rst),
.en(in_lsu_select)
);
dff_en flop_dest_reg[11:0](
.q(out_dest_reg),
.d(in_dest_reg),
.clk(clk),
.rst(rst),
.en(in_lsu_select)
);
dff_en flop_opcode[31:0](
.q(out_opcode),
.d(in_opcode),
.clk(clk),
.rst(rst),
.en(in_lsu_select)
);
dff_en flop_instr_pc[31:0](
.q(out_instr_pc),
.d(in_instr_pc),
.clk(clk),
.rst(rst),
.en(in_lsu_select)
);
endmodule
|
#include <bits/stdc++.h> using std::min; const int MAXL = 3000000 + 9, MAXM = 5000 + 9, M = 4194304; int tr[M + M]; int ask(int k) { int i; for (i = 1; i < M;) if (k > tr[i + i]) { k -= tr[i + i]; i += i + 1; } else i += i; return i - M; } void change(int u, int v) { for (u += M; u; u >>= 1) tr[u] += v; } int l[MAXM], r[MAXM]; int fa[MAXL]; char s[MAXL], ans[MAXL]; int main() { int k, m, i, j, t, tot; int ll, rr, ori; char *p; scanf( %s%d%d , s + 1, &k, &m); for (i = 1; i <= m; ++i) scanf( %d%d , l + i, r + i); for (i = 1; i <= k; ++i) change(i, 1); tot = k; for (i = m; i; --i) { if (r[i] + 1 > tot) continue; ll = r[i] - l[i] + 1; rr = min(tot, r[i] + ll); for (j = 1; j <= rr - r[i]; ++j) { m = ll >> 1; ori = j <= m ? l[i] - 1 + j + j : l[i] - 2 + 2 * (j - m); fa[t = ask(r[i] + 1)] = ask(ori); change(t, -1); } tot -= rr - r[i]; } p = s; for (i = 1; i <= k; ++i) ans[i] = fa[i] ? ans[fa[i]] : *++p; puts(ans + 1); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, a[500005], l = 1, r, b[500005]; queue<int> Q; bool flag = false; int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; ++i) a[i] = i & -i; for (int i = 1; i <= n; ++i) b[i] = 1; r = n; while (m--) { int opt, x, y; scanf( %d , &opt); if (opt == 1) { scanf( %d , &x); if (flag) x = r - x + 1; else x += l; if (r - x + 1 > x - l) while (l < x) { int tmp = 0; for (int j = l; j; j -= j & -j) tmp += a[j]; for (int j = l - 1; j; j -= j & -j) tmp -= a[j]; for (int j = l; j <= n; j += j & -j) a[j] -= tmp; b[x + x - l - 1] += b[l]; b[l] = 0; for (int j = x + x - l - 1; j <= n; j += j & -j) a[j] += tmp; l++; flag = false; } else while (r >= x) { for (int i = x; i <= r; ++i) { int tmp = 0; for (int j = i; j; j -= j & -j) tmp += a[j]; for (int j = i - 1; j; j -= j & -j) tmp -= a[j]; for (int j = i; j <= n; j += j & -j) a[j] -= tmp; b[i] = 0; Q.push(tmp); } for (int i = x - 1; i >= x - (r - x + 1); --i) { int tmp = Q.front(); Q.pop(); for (int j = i; j <= n; j += j & -j) a[j] += tmp; b[i] += tmp; } r = x - 1; flag = true; } } if (opt == 2) { scanf( %d%d , &x, &y); int xx, yy; if (flag) { xx = r - y; yy = r - x; x = xx, y = yy; } else x = x + l - 1, y = y + l - 1; int ans = 0; for (int j = y; j; j -= j & -j) ans += a[j]; for (int j = x; j; j -= j & -j) ans -= a[j]; printf( %d n , ans); } } } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_ifu_cmp35.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: sparc_ifu_cmp37
// Description:
// 37 bit comparator for MIL hit detection
*/
////////////////////////////////////////////////////////////////////////
module sparc_ifu_cmp35(/*AUTOARG*/
// Outputs
hit,
// Inputs
a, b, valid
);
input [34:0] a, b;
input valid;
output hit;
reg hit;
wire valid;
wire [34:0] a, b;
always @ (a or b or valid)
begin
if ((a==b) & valid)
hit = 1'b1;
else
hit = 1'b0;
end // always @ (a or b or valid)
endmodule // sparc_ifu_cmp35
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const long long INFF = 0x3f3f3f3f3f3f3f3fll; const long long M = 1e9 + 7; const long long maxn = 2e6 + 7; const double eps = 0.00000001; long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } template <typename T> inline T abs(T a) { return a > 0 ? a : -a; } template <typename T> inline T powMM(T a, T b) { T ret = 1; for (; b; b >>= 1ll, a = a * a % M) ret = 1ll * ret * a % M; return ret; } set<int> SET; set<int>::iterator it; int n, m, t; int i; int len; int mx; char a[maxn], s[maxn]; int main() { scanf( %d , &n); for (i = 0; i <= 2e6; i++) SET.insert(i); while (n--) { scanf( %s , s); len = strlen(s); scanf( %d , &m); while (m--) { scanf( %d , &t); t--; for (it = SET.lower_bound(t); it != SET.end() && *it < t + len; it = SET.lower_bound(t)) { a[*it] = s[*it - t]; if (mx < *it) mx = *it; SET.erase(it); } } } for (i = 0; i < mx + 1; i++) { if (a[i]) putchar(a[i]); else putchar( a ); } } |
Subsets and Splits