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// SPDX-License-Identifier: GPL-2.0-only
/* sound/soc/rockchip/rk_spdif.c
*
* ALSA SoC Audio Layer - Rockchip I2S Controller driver
*
* Copyright (c) 2014 Rockchip Electronics Co. Ltd.
* Author: Jianqun <[email protected]>
* Copyright (c) 2015 Collabora Ltd.
* Author: Sjoerd Simons <[email protected]>
*/
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/of_gpio.h>
#include <linux/clk.h>
#include <linux/pm_runtime.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>
#include <sound/pcm_params.h>
#include <sound/dmaengine_pcm.h>
#include "rockchip_spdif.h"
enum rk_spdif_type {
RK_SPDIF_RK3066,
RK_SPDIF_RK3188,
RK_SPDIF_RK3288,
RK_SPDIF_RK3366,
};
#define RK3288_GRF_SOC_CON2 0x24c
struct rk_spdif_dev {
struct device *dev;
struct clk *mclk;
struct clk *hclk;
struct snd_dmaengine_dai_dma_data playback_dma_data;
struct regmap *regmap;
};
static const struct of_device_id rk_spdif_match[] __maybe_unused = {
{ .compatible = "rockchip,rk3066-spdif",
.data = (void *)RK_SPDIF_RK3066 },
{ .compatible = "rockchip,rk3188-spdif",
.data = (void *)RK_SPDIF_RK3188 },
{ .compatible = "rockchip,rk3228-spdif",
.data = (void *)RK_SPDIF_RK3366 },
{ .compatible = "rockchip,rk3288-spdif",
.data = (void *)RK_SPDIF_RK3288 },
{ .compatible = "rockchip,rk3328-spdif",
.data = (void *)RK_SPDIF_RK3366 },
{ .compatible = "rockchip,rk3366-spdif",
.data = (void *)RK_SPDIF_RK3366 },
{ .compatible = "rockchip,rk3368-spdif",
.data = (void *)RK_SPDIF_RK3366 },
{ .compatible = "rockchip,rk3399-spdif",
.data = (void *)RK_SPDIF_RK3366 },
{ .compatible = "rockchip,rk3568-spdif",
.data = (void *)RK_SPDIF_RK3366 },
{},
};
MODULE_DEVICE_TABLE(of, rk_spdif_match);
static int __maybe_unused rk_spdif_runtime_suspend(struct device *dev)
{
struct rk_spdif_dev *spdif = dev_get_drvdata(dev);
regcache_cache_only(spdif->regmap, true);
clk_disable_unprepare(spdif->mclk);
clk_disable_unprepare(spdif->hclk);
return 0;
}
static int __maybe_unused rk_spdif_runtime_resume(struct device *dev)
{
struct rk_spdif_dev *spdif = dev_get_drvdata(dev);
int ret;
ret = clk_prepare_enable(spdif->mclk);
if (ret) {
dev_err(spdif->dev, "mclk clock enable failed %d\n", ret);
return ret;
}
ret = clk_prepare_enable(spdif->hclk);
if (ret) {
clk_disable_unprepare(spdif->mclk);
dev_err(spdif->dev, "hclk clock enable failed %d\n", ret);
return ret;
}
regcache_cache_only(spdif->regmap, false);
regcache_mark_dirty(spdif->regmap);
ret = regcache_sync(spdif->regmap);
if (ret) {
clk_disable_unprepare(spdif->mclk);
clk_disable_unprepare(spdif->hclk);
}
return ret;
}
static int rk_spdif_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct rk_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);
unsigned int val = SPDIF_CFGR_HALFWORD_ENABLE;
int srate, mclk;
int ret;
srate = params_rate(params);
mclk = srate * 128;
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
val |= SPDIF_CFGR_VDW_16;
break;
case SNDRV_PCM_FORMAT_S20_3LE:
val |= SPDIF_CFGR_VDW_20;
break;
case SNDRV_PCM_FORMAT_S24_LE:
val |= SPDIF_CFGR_VDW_24;
break;
default:
return -EINVAL;
}
/* Set clock and calculate divider */
ret = clk_set_rate(spdif->mclk, mclk);
if (ret != 0) {
dev_err(spdif->dev, "Failed to set module clock rate: %d\n",
ret);
return ret;
}
ret = regmap_update_bits(spdif->regmap, SPDIF_CFGR,
SPDIF_CFGR_CLK_DIV_MASK |
SPDIF_CFGR_HALFWORD_ENABLE |
SDPIF_CFGR_VDW_MASK, val);
return ret;
}
static int rk_spdif_trigger(struct snd_pcm_substream *substream,
int cmd, struct snd_soc_dai *dai)
{
struct rk_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);
int ret;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
ret = regmap_update_bits(spdif->regmap, SPDIF_DMACR,
SPDIF_DMACR_TDE_ENABLE |
SPDIF_DMACR_TDL_MASK,
SPDIF_DMACR_TDE_ENABLE |
SPDIF_DMACR_TDL(16));
if (ret != 0)
return ret;
ret = regmap_update_bits(spdif->regmap, SPDIF_XFER,
SPDIF_XFER_TXS_START,
SPDIF_XFER_TXS_START);
break;
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
ret = regmap_update_bits(spdif->regmap, SPDIF_DMACR,
SPDIF_DMACR_TDE_ENABLE,
SPDIF_DMACR_TDE_DISABLE);
if (ret != 0)
return ret;
ret = regmap_update_bits(spdif->regmap, SPDIF_XFER,
SPDIF_XFER_TXS_START,
SPDIF_XFER_TXS_STOP);
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
static int rk_spdif_dai_probe(struct snd_soc_dai *dai)
{
struct rk_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);
snd_soc_dai_dma_data_set_playback(dai, &spdif->playback_dma_data);
return 0;
}
static const struct snd_soc_dai_ops rk_spdif_dai_ops = {
.probe = rk_spdif_dai_probe,
.hw_params = rk_spdif_hw_params,
.trigger = rk_spdif_trigger,
};
static struct snd_soc_dai_driver rk_spdif_dai = {
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = (SNDRV_PCM_RATE_32000 |
SNDRV_PCM_RATE_44100 |
SNDRV_PCM_RATE_48000 |
SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000),
.formats = (SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S20_3LE |
SNDRV_PCM_FMTBIT_S24_LE),
},
.ops = &rk_spdif_dai_ops,
};
static const struct snd_soc_component_driver rk_spdif_component = {
.name = "rockchip-spdif",
.legacy_dai_naming = 1,
};
static bool rk_spdif_wr_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case SPDIF_CFGR:
case SPDIF_DMACR:
case SPDIF_INTCR:
case SPDIF_XFER:
case SPDIF_SMPDR:
return true;
default:
return false;
}
}
static bool rk_spdif_rd_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case SPDIF_CFGR:
case SPDIF_SDBLR:
case SPDIF_INTCR:
case SPDIF_INTSR:
case SPDIF_XFER:
case SPDIF_SMPDR:
return true;
default:
return false;
}
}
static bool rk_spdif_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case SPDIF_INTSR:
case SPDIF_SDBLR:
case SPDIF_SMPDR:
return true;
default:
return false;
}
}
static const struct regmap_config rk_spdif_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = SPDIF_SMPDR,
.writeable_reg = rk_spdif_wr_reg,
.readable_reg = rk_spdif_rd_reg,
.volatile_reg = rk_spdif_volatile_reg,
.cache_type = REGCACHE_FLAT,
};
static int rk_spdif_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct rk_spdif_dev *spdif;
const struct of_device_id *match;
struct resource *res;
void __iomem *regs;
int ret;
match = of_match_node(rk_spdif_match, np);
if (match->data == (void *)RK_SPDIF_RK3288) {
struct regmap *grf;
grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
if (IS_ERR(grf)) {
dev_err(&pdev->dev,
"rockchip_spdif missing 'rockchip,grf'\n");
return PTR_ERR(grf);
}
/* Select the 8 channel SPDIF solution on RK3288 as
* the 2 channel one does not appear to work
*/
regmap_write(grf, RK3288_GRF_SOC_CON2, BIT(1) << 16);
}
spdif = devm_kzalloc(&pdev->dev, sizeof(*spdif), GFP_KERNEL);
if (!spdif)
return -ENOMEM;
spdif->hclk = devm_clk_get(&pdev->dev, "hclk");
if (IS_ERR(spdif->hclk))
return PTR_ERR(spdif->hclk);
spdif->mclk = devm_clk_get(&pdev->dev, "mclk");
if (IS_ERR(spdif->mclk))
return PTR_ERR(spdif->mclk);
regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(regs))
return PTR_ERR(regs);
spdif->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "hclk", regs,
&rk_spdif_regmap_config);
if (IS_ERR(spdif->regmap))
return PTR_ERR(spdif->regmap);
spdif->playback_dma_data.addr = res->start + SPDIF_SMPDR;
spdif->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
spdif->playback_dma_data.maxburst = 4;
spdif->dev = &pdev->dev;
dev_set_drvdata(&pdev->dev, spdif);
pm_runtime_enable(&pdev->dev);
if (!pm_runtime_enabled(&pdev->dev)) {
ret = rk_spdif_runtime_resume(&pdev->dev);
if (ret)
goto err_pm_runtime;
}
ret = devm_snd_soc_register_component(&pdev->dev,
&rk_spdif_component,
&rk_spdif_dai, 1);
if (ret) {
dev_err(&pdev->dev, "Could not register DAI\n");
goto err_pm_suspend;
}
ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
if (ret) {
dev_err(&pdev->dev, "Could not register PCM\n");
goto err_pm_suspend;
}
return 0;
err_pm_suspend:
if (!pm_runtime_status_suspended(&pdev->dev))
rk_spdif_runtime_suspend(&pdev->dev);
err_pm_runtime:
pm_runtime_disable(&pdev->dev);
return ret;
}
static void rk_spdif_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
if (!pm_runtime_status_suspended(&pdev->dev))
rk_spdif_runtime_suspend(&pdev->dev);
}
static const struct dev_pm_ops rk_spdif_pm_ops = {
SET_RUNTIME_PM_OPS(rk_spdif_runtime_suspend, rk_spdif_runtime_resume,
NULL)
};
static struct platform_driver rk_spdif_driver = {
.probe = rk_spdif_probe,
.remove_new = rk_spdif_remove,
.driver = {
.name = "rockchip-spdif",
.of_match_table = of_match_ptr(rk_spdif_match),
.pm = &rk_spdif_pm_ops,
},
};
module_platform_driver(rk_spdif_driver);
MODULE_ALIAS("platform:rockchip-spdif");
MODULE_DESCRIPTION("ROCKCHIP SPDIF transceiver Interface");
MODULE_AUTHOR("Sjoerd Simons <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/rockchip/rockchip_spdif.c |
// SPDX-License-Identifier: GPL-2.0-only
// ALSA SoC Audio Layer - Rockchip I2S/TDM Controller driver
// Copyright (c) 2018 Rockchip Electronics Co. Ltd.
// Author: Sugar Zhang <[email protected]>
// Author: Nicolas Frattaroli <[email protected]>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/spinlock.h>
#include <sound/dmaengine_pcm.h>
#include <sound/pcm_params.h>
#include "rockchip_i2s_tdm.h"
#define DRV_NAME "rockchip-i2s-tdm"
#define DEFAULT_MCLK_FS 256
#define CH_GRP_MAX 4 /* The max channel 8 / 2 */
#define MULTIPLEX_CH_MAX 10
#define CLK_PPM_MIN -1000
#define CLK_PPM_MAX 1000
#define TRCM_TXRX 0
#define TRCM_TX 1
#define TRCM_RX 2
struct txrx_config {
u32 addr;
u32 reg;
u32 txonly;
u32 rxonly;
};
struct rk_i2s_soc_data {
u32 softrst_offset;
u32 grf_reg_offset;
u32 grf_shift;
int config_count;
const struct txrx_config *configs;
int (*init)(struct device *dev, u32 addr);
};
struct rk_i2s_tdm_dev {
struct device *dev;
struct clk *hclk;
struct clk *mclk_tx;
struct clk *mclk_rx;
/* The mclk_tx_src is parent of mclk_tx */
struct clk *mclk_tx_src;
/* The mclk_rx_src is parent of mclk_rx */
struct clk *mclk_rx_src;
/*
* The mclk_root0 and mclk_root1 are root parent and supplies for
* the different FS.
*
* e.g:
* mclk_root0 is VPLL0, used for FS=48000Hz
* mclk_root1 is VPLL1, used for FS=44100Hz
*/
struct clk *mclk_root0;
struct clk *mclk_root1;
struct regmap *regmap;
struct regmap *grf;
struct snd_dmaengine_dai_dma_data capture_dma_data;
struct snd_dmaengine_dai_dma_data playback_dma_data;
struct reset_control *tx_reset;
struct reset_control *rx_reset;
struct rk_i2s_soc_data *soc_data;
bool is_master_mode;
bool io_multiplex;
bool mclk_calibrate;
bool tdm_mode;
unsigned int mclk_rx_freq;
unsigned int mclk_tx_freq;
unsigned int mclk_root0_freq;
unsigned int mclk_root1_freq;
unsigned int mclk_root0_initial_freq;
unsigned int mclk_root1_initial_freq;
unsigned int frame_width;
unsigned int clk_trcm;
unsigned int i2s_sdis[CH_GRP_MAX];
unsigned int i2s_sdos[CH_GRP_MAX];
int clk_ppm;
int refcount;
spinlock_t lock; /* xfer lock */
bool has_playback;
bool has_capture;
struct snd_soc_dai_driver *dai;
};
static int to_ch_num(unsigned int val)
{
switch (val) {
case I2S_CHN_4:
return 4;
case I2S_CHN_6:
return 6;
case I2S_CHN_8:
return 8;
default:
return 2;
}
}
static void i2s_tdm_disable_unprepare_mclk(struct rk_i2s_tdm_dev *i2s_tdm)
{
clk_disable_unprepare(i2s_tdm->mclk_tx);
clk_disable_unprepare(i2s_tdm->mclk_rx);
if (i2s_tdm->mclk_calibrate) {
clk_disable_unprepare(i2s_tdm->mclk_tx_src);
clk_disable_unprepare(i2s_tdm->mclk_rx_src);
clk_disable_unprepare(i2s_tdm->mclk_root0);
clk_disable_unprepare(i2s_tdm->mclk_root1);
}
}
/**
* i2s_tdm_prepare_enable_mclk - prepare to enable all mclks, disable them on
* failure.
* @i2s_tdm: rk_i2s_tdm_dev struct
*
* This function attempts to enable all mclk clocks, but cleans up after
* itself on failure. Guarantees to balance its calls.
*
* Returns success (0) or negative errno.
*/
static int i2s_tdm_prepare_enable_mclk(struct rk_i2s_tdm_dev *i2s_tdm)
{
int ret = 0;
ret = clk_prepare_enable(i2s_tdm->mclk_tx);
if (ret)
goto err_mclk_tx;
ret = clk_prepare_enable(i2s_tdm->mclk_rx);
if (ret)
goto err_mclk_rx;
if (i2s_tdm->mclk_calibrate) {
ret = clk_prepare_enable(i2s_tdm->mclk_tx_src);
if (ret)
goto err_mclk_rx;
ret = clk_prepare_enable(i2s_tdm->mclk_rx_src);
if (ret)
goto err_mclk_rx_src;
ret = clk_prepare_enable(i2s_tdm->mclk_root0);
if (ret)
goto err_mclk_root0;
ret = clk_prepare_enable(i2s_tdm->mclk_root1);
if (ret)
goto err_mclk_root1;
}
return 0;
err_mclk_root1:
clk_disable_unprepare(i2s_tdm->mclk_root0);
err_mclk_root0:
clk_disable_unprepare(i2s_tdm->mclk_rx_src);
err_mclk_rx_src:
clk_disable_unprepare(i2s_tdm->mclk_tx_src);
err_mclk_rx:
clk_disable_unprepare(i2s_tdm->mclk_tx);
err_mclk_tx:
return ret;
}
static int __maybe_unused i2s_tdm_runtime_suspend(struct device *dev)
{
struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
regcache_cache_only(i2s_tdm->regmap, true);
i2s_tdm_disable_unprepare_mclk(i2s_tdm);
clk_disable_unprepare(i2s_tdm->hclk);
return 0;
}
static int __maybe_unused i2s_tdm_runtime_resume(struct device *dev)
{
struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
int ret;
ret = clk_prepare_enable(i2s_tdm->hclk);
if (ret)
goto err_hclk;
ret = i2s_tdm_prepare_enable_mclk(i2s_tdm);
if (ret)
goto err_mclk;
regcache_cache_only(i2s_tdm->regmap, false);
regcache_mark_dirty(i2s_tdm->regmap);
ret = regcache_sync(i2s_tdm->regmap);
if (ret)
goto err_regcache;
return 0;
err_regcache:
i2s_tdm_disable_unprepare_mclk(i2s_tdm);
err_mclk:
clk_disable_unprepare(i2s_tdm->hclk);
err_hclk:
return ret;
}
static inline struct rk_i2s_tdm_dev *to_info(struct snd_soc_dai *dai)
{
return snd_soc_dai_get_drvdata(dai);
}
/*
* Makes sure that both tx and rx are reset at the same time to sync lrck
* when clk_trcm > 0.
*/
static void rockchip_snd_xfer_sync_reset(struct rk_i2s_tdm_dev *i2s_tdm)
{
/* This is technically race-y.
*
* In an ideal world, we could atomically assert both resets at the
* same time, through an atomic bulk reset API. This API however does
* not exist, so what the downstream vendor code used to do was
* implement half a reset controller here and require the CRU to be
* passed to the driver as a device tree node. Violating abstractions
* like that is bad, especially when it influences something like the
* bindings which are supposed to describe the hardware, not whatever
* workarounds the driver needs, so it was dropped.
*
* In practice, asserting the resets one by one appears to work just
* fine for playback. During duplex (playback + capture) operation,
* this might become an issue, but that should be solved by the
* implementation of the aforementioned API, not by shoving a reset
* controller into an audio driver.
*/
reset_control_assert(i2s_tdm->tx_reset);
reset_control_assert(i2s_tdm->rx_reset);
udelay(10);
reset_control_deassert(i2s_tdm->tx_reset);
reset_control_deassert(i2s_tdm->rx_reset);
udelay(10);
}
static void rockchip_snd_reset(struct reset_control *rc)
{
reset_control_assert(rc);
udelay(10);
reset_control_deassert(rc);
udelay(10);
}
static void rockchip_snd_xfer_clear(struct rk_i2s_tdm_dev *i2s_tdm,
unsigned int clr)
{
unsigned int xfer_mask = 0;
unsigned int xfer_val = 0;
unsigned int val;
int retry = 10;
bool tx = clr & I2S_CLR_TXC;
bool rx = clr & I2S_CLR_RXC;
if (!(rx || tx))
return;
if (tx) {
xfer_mask = I2S_XFER_TXS_START;
xfer_val = I2S_XFER_TXS_STOP;
}
if (rx) {
xfer_mask |= I2S_XFER_RXS_START;
xfer_val |= I2S_XFER_RXS_STOP;
}
regmap_update_bits(i2s_tdm->regmap, I2S_XFER, xfer_mask, xfer_val);
udelay(150);
regmap_update_bits(i2s_tdm->regmap, I2S_CLR, clr, clr);
regmap_read(i2s_tdm->regmap, I2S_CLR, &val);
/* Wait on the clear operation to finish */
while (val) {
udelay(15);
regmap_read(i2s_tdm->regmap, I2S_CLR, &val);
retry--;
if (!retry) {
dev_warn(i2s_tdm->dev, "clear failed, reset %s%s\n",
tx ? "tx" : "", rx ? "rx" : "");
if (rx && tx)
rockchip_snd_xfer_sync_reset(i2s_tdm);
else if (tx)
rockchip_snd_reset(i2s_tdm->tx_reset);
else if (rx)
rockchip_snd_reset(i2s_tdm->rx_reset);
break;
}
}
}
static inline void rockchip_enable_tde(struct regmap *regmap)
{
regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_TDE_ENABLE,
I2S_DMACR_TDE_ENABLE);
}
static inline void rockchip_disable_tde(struct regmap *regmap)
{
regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_TDE_ENABLE,
I2S_DMACR_TDE_DISABLE);
}
static inline void rockchip_enable_rde(struct regmap *regmap)
{
regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_RDE_ENABLE,
I2S_DMACR_RDE_ENABLE);
}
static inline void rockchip_disable_rde(struct regmap *regmap)
{
regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_RDE_ENABLE,
I2S_DMACR_RDE_DISABLE);
}
/* only used when clk_trcm > 0 */
static void rockchip_snd_txrxctrl(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai, int on)
{
struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
unsigned long flags;
spin_lock_irqsave(&i2s_tdm->lock, flags);
if (on) {
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
rockchip_enable_tde(i2s_tdm->regmap);
else
rockchip_enable_rde(i2s_tdm->regmap);
if (++i2s_tdm->refcount == 1) {
rockchip_snd_xfer_sync_reset(i2s_tdm);
regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
I2S_XFER_TXS_START |
I2S_XFER_RXS_START,
I2S_XFER_TXS_START |
I2S_XFER_RXS_START);
}
} else {
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
rockchip_disable_tde(i2s_tdm->regmap);
else
rockchip_disable_rde(i2s_tdm->regmap);
if (--i2s_tdm->refcount == 0) {
rockchip_snd_xfer_clear(i2s_tdm,
I2S_CLR_TXC | I2S_CLR_RXC);
}
}
spin_unlock_irqrestore(&i2s_tdm->lock, flags);
}
static void rockchip_snd_txctrl(struct rk_i2s_tdm_dev *i2s_tdm, int on)
{
if (on) {
rockchip_enable_tde(i2s_tdm->regmap);
regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
I2S_XFER_TXS_START,
I2S_XFER_TXS_START);
} else {
rockchip_disable_tde(i2s_tdm->regmap);
rockchip_snd_xfer_clear(i2s_tdm, I2S_CLR_TXC);
}
}
static void rockchip_snd_rxctrl(struct rk_i2s_tdm_dev *i2s_tdm, int on)
{
if (on) {
rockchip_enable_rde(i2s_tdm->regmap);
regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
I2S_XFER_RXS_START,
I2S_XFER_RXS_START);
} else {
rockchip_disable_rde(i2s_tdm->regmap);
rockchip_snd_xfer_clear(i2s_tdm, I2S_CLR_RXC);
}
}
static int rockchip_i2s_tdm_set_fmt(struct snd_soc_dai *cpu_dai,
unsigned int fmt)
{
struct rk_i2s_tdm_dev *i2s_tdm = to_info(cpu_dai);
unsigned int mask, val, tdm_val, txcr_val, rxcr_val;
int ret;
bool is_tdm = i2s_tdm->tdm_mode;
ret = pm_runtime_resume_and_get(cpu_dai->dev);
if (ret < 0 && ret != -EACCES)
return ret;
mask = I2S_CKR_MSS_MASK;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BP_FP:
val = I2S_CKR_MSS_MASTER;
i2s_tdm->is_master_mode = true;
break;
case SND_SOC_DAIFMT_BC_FC:
val = I2S_CKR_MSS_SLAVE;
i2s_tdm->is_master_mode = false;
break;
default:
ret = -EINVAL;
goto err_pm_put;
}
regmap_update_bits(i2s_tdm->regmap, I2S_CKR, mask, val);
mask = I2S_CKR_CKP_MASK | I2S_CKR_TLP_MASK | I2S_CKR_RLP_MASK;
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
val = I2S_CKR_CKP_NORMAL |
I2S_CKR_TLP_NORMAL |
I2S_CKR_RLP_NORMAL;
break;
case SND_SOC_DAIFMT_NB_IF:
val = I2S_CKR_CKP_NORMAL |
I2S_CKR_TLP_INVERTED |
I2S_CKR_RLP_INVERTED;
break;
case SND_SOC_DAIFMT_IB_NF:
val = I2S_CKR_CKP_INVERTED |
I2S_CKR_TLP_NORMAL |
I2S_CKR_RLP_NORMAL;
break;
case SND_SOC_DAIFMT_IB_IF:
val = I2S_CKR_CKP_INVERTED |
I2S_CKR_TLP_INVERTED |
I2S_CKR_RLP_INVERTED;
break;
default:
ret = -EINVAL;
goto err_pm_put;
}
regmap_update_bits(i2s_tdm->regmap, I2S_CKR, mask, val);
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_RIGHT_J:
txcr_val = I2S_TXCR_IBM_RSJM;
rxcr_val = I2S_RXCR_IBM_RSJM;
break;
case SND_SOC_DAIFMT_LEFT_J:
txcr_val = I2S_TXCR_IBM_LSJM;
rxcr_val = I2S_RXCR_IBM_LSJM;
break;
case SND_SOC_DAIFMT_I2S:
txcr_val = I2S_TXCR_IBM_NORMAL;
rxcr_val = I2S_RXCR_IBM_NORMAL;
break;
case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 mode */
txcr_val = I2S_TXCR_TFS_PCM | I2S_TXCR_PBM_MODE(1);
rxcr_val = I2S_RXCR_TFS_PCM | I2S_RXCR_PBM_MODE(1);
break;
case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */
txcr_val = I2S_TXCR_TFS_PCM;
rxcr_val = I2S_RXCR_TFS_PCM;
break;
default:
ret = -EINVAL;
goto err_pm_put;
}
mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK;
regmap_update_bits(i2s_tdm->regmap, I2S_TXCR, mask, txcr_val);
mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK;
regmap_update_bits(i2s_tdm->regmap, I2S_RXCR, mask, rxcr_val);
if (is_tdm) {
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_RIGHT_J:
val = I2S_TXCR_TFS_TDM_I2S;
tdm_val = TDM_SHIFT_CTRL(2);
break;
case SND_SOC_DAIFMT_LEFT_J:
val = I2S_TXCR_TFS_TDM_I2S;
tdm_val = TDM_SHIFT_CTRL(1);
break;
case SND_SOC_DAIFMT_I2S:
val = I2S_TXCR_TFS_TDM_I2S;
tdm_val = TDM_SHIFT_CTRL(0);
break;
case SND_SOC_DAIFMT_DSP_A:
val = I2S_TXCR_TFS_TDM_PCM;
tdm_val = TDM_SHIFT_CTRL(0);
break;
case SND_SOC_DAIFMT_DSP_B:
val = I2S_TXCR_TFS_TDM_PCM;
tdm_val = TDM_SHIFT_CTRL(2);
break;
default:
ret = -EINVAL;
goto err_pm_put;
}
tdm_val |= TDM_FSYNC_WIDTH_SEL1(1);
tdm_val |= TDM_FSYNC_WIDTH_HALF_FRAME;
mask = I2S_TXCR_TFS_MASK;
regmap_update_bits(i2s_tdm->regmap, I2S_TXCR, mask, val);
regmap_update_bits(i2s_tdm->regmap, I2S_RXCR, mask, val);
mask = TDM_FSYNC_WIDTH_SEL1_MSK | TDM_FSYNC_WIDTH_SEL0_MSK |
TDM_SHIFT_CTRL_MSK;
regmap_update_bits(i2s_tdm->regmap, I2S_TDM_TXCR,
mask, tdm_val);
regmap_update_bits(i2s_tdm->regmap, I2S_TDM_RXCR,
mask, tdm_val);
}
err_pm_put:
pm_runtime_put(cpu_dai->dev);
return ret;
}
static void rockchip_i2s_tdm_xfer_pause(struct snd_pcm_substream *substream,
struct rk_i2s_tdm_dev *i2s_tdm)
{
int stream;
stream = SNDRV_PCM_STREAM_LAST - substream->stream;
if (stream == SNDRV_PCM_STREAM_PLAYBACK)
rockchip_disable_tde(i2s_tdm->regmap);
else
rockchip_disable_rde(i2s_tdm->regmap);
rockchip_snd_xfer_clear(i2s_tdm, I2S_CLR_TXC | I2S_CLR_RXC);
}
static void rockchip_i2s_tdm_xfer_resume(struct snd_pcm_substream *substream,
struct rk_i2s_tdm_dev *i2s_tdm)
{
int stream;
stream = SNDRV_PCM_STREAM_LAST - substream->stream;
if (stream == SNDRV_PCM_STREAM_PLAYBACK)
rockchip_enable_tde(i2s_tdm->regmap);
else
rockchip_enable_rde(i2s_tdm->regmap);
regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
I2S_XFER_TXS_START |
I2S_XFER_RXS_START,
I2S_XFER_TXS_START |
I2S_XFER_RXS_START);
}
static int rockchip_i2s_tdm_clk_set_rate(struct rk_i2s_tdm_dev *i2s_tdm,
struct clk *clk, unsigned long rate,
int ppm)
{
unsigned long rate_target;
int delta, ret;
if (ppm == i2s_tdm->clk_ppm)
return 0;
if (ppm < 0)
delta = -1;
else
delta = 1;
delta *= (int)div64_u64((u64)rate * (u64)abs(ppm) + 500000,
1000000);
rate_target = rate + delta;
if (!rate_target)
return -EINVAL;
ret = clk_set_rate(clk, rate_target);
if (ret)
return ret;
i2s_tdm->clk_ppm = ppm;
return 0;
}
static int rockchip_i2s_tdm_calibrate_mclk(struct rk_i2s_tdm_dev *i2s_tdm,
struct snd_pcm_substream *substream,
unsigned int lrck_freq)
{
struct clk *mclk_root;
struct clk *mclk_parent;
unsigned int mclk_root_freq;
unsigned int mclk_root_initial_freq;
unsigned int mclk_parent_freq;
unsigned int div, delta;
u64 ppm;
int ret;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
mclk_parent = i2s_tdm->mclk_tx_src;
else
mclk_parent = i2s_tdm->mclk_rx_src;
switch (lrck_freq) {
case 8000:
case 16000:
case 24000:
case 32000:
case 48000:
case 64000:
case 96000:
case 192000:
mclk_root = i2s_tdm->mclk_root0;
mclk_root_freq = i2s_tdm->mclk_root0_freq;
mclk_root_initial_freq = i2s_tdm->mclk_root0_initial_freq;
mclk_parent_freq = DEFAULT_MCLK_FS * 192000;
break;
case 11025:
case 22050:
case 44100:
case 88200:
case 176400:
mclk_root = i2s_tdm->mclk_root1;
mclk_root_freq = i2s_tdm->mclk_root1_freq;
mclk_root_initial_freq = i2s_tdm->mclk_root1_initial_freq;
mclk_parent_freq = DEFAULT_MCLK_FS * 176400;
break;
default:
dev_err(i2s_tdm->dev, "Invalid LRCK frequency: %u Hz\n",
lrck_freq);
return -EINVAL;
}
ret = clk_set_parent(mclk_parent, mclk_root);
if (ret)
return ret;
ret = rockchip_i2s_tdm_clk_set_rate(i2s_tdm, mclk_root,
mclk_root_freq, 0);
if (ret)
return ret;
delta = abs(mclk_root_freq % mclk_parent_freq - mclk_parent_freq);
ppm = div64_u64((uint64_t)delta * 1000000, (uint64_t)mclk_root_freq);
if (ppm) {
div = DIV_ROUND_CLOSEST(mclk_root_initial_freq, mclk_parent_freq);
if (!div)
return -EINVAL;
mclk_root_freq = mclk_parent_freq * round_up(div, 2);
ret = clk_set_rate(mclk_root, mclk_root_freq);
if (ret)
return ret;
i2s_tdm->mclk_root0_freq = clk_get_rate(i2s_tdm->mclk_root0);
i2s_tdm->mclk_root1_freq = clk_get_rate(i2s_tdm->mclk_root1);
}
return clk_set_rate(mclk_parent, mclk_parent_freq);
}
static int rockchip_i2s_tdm_set_mclk(struct rk_i2s_tdm_dev *i2s_tdm,
struct snd_pcm_substream *substream,
struct clk **mclk)
{
unsigned int mclk_freq;
int ret;
if (i2s_tdm->clk_trcm) {
if (i2s_tdm->mclk_tx_freq != i2s_tdm->mclk_rx_freq) {
dev_err(i2s_tdm->dev,
"clk_trcm, tx: %d and rx: %d should be the same\n",
i2s_tdm->mclk_tx_freq,
i2s_tdm->mclk_rx_freq);
return -EINVAL;
}
ret = clk_set_rate(i2s_tdm->mclk_tx, i2s_tdm->mclk_tx_freq);
if (ret)
return ret;
ret = clk_set_rate(i2s_tdm->mclk_rx, i2s_tdm->mclk_rx_freq);
if (ret)
return ret;
/* mclk_rx is also ok. */
*mclk = i2s_tdm->mclk_tx;
} else {
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
*mclk = i2s_tdm->mclk_tx;
mclk_freq = i2s_tdm->mclk_tx_freq;
} else {
*mclk = i2s_tdm->mclk_rx;
mclk_freq = i2s_tdm->mclk_rx_freq;
}
ret = clk_set_rate(*mclk, mclk_freq);
if (ret)
return ret;
}
return 0;
}
static int rockchip_i2s_ch_to_io(unsigned int ch, bool substream_capture)
{
if (substream_capture) {
switch (ch) {
case I2S_CHN_4:
return I2S_IO_6CH_OUT_4CH_IN;
case I2S_CHN_6:
return I2S_IO_4CH_OUT_6CH_IN;
case I2S_CHN_8:
return I2S_IO_2CH_OUT_8CH_IN;
default:
return I2S_IO_8CH_OUT_2CH_IN;
}
} else {
switch (ch) {
case I2S_CHN_4:
return I2S_IO_4CH_OUT_6CH_IN;
case I2S_CHN_6:
return I2S_IO_6CH_OUT_4CH_IN;
case I2S_CHN_8:
return I2S_IO_8CH_OUT_2CH_IN;
default:
return I2S_IO_2CH_OUT_8CH_IN;
}
}
}
static int rockchip_i2s_io_multiplex(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
int usable_chs = MULTIPLEX_CH_MAX;
unsigned int val = 0;
if (!i2s_tdm->io_multiplex)
return 0;
if (IS_ERR_OR_NULL(i2s_tdm->grf)) {
dev_err(i2s_tdm->dev,
"io multiplex not supported for this device\n");
return -EINVAL;
}
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
struct snd_pcm_str *playback_str =
&substream->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK];
if (playback_str->substream_opened) {
regmap_read(i2s_tdm->regmap, I2S_TXCR, &val);
val &= I2S_TXCR_CSR_MASK;
usable_chs = MULTIPLEX_CH_MAX - to_ch_num(val);
}
regmap_read(i2s_tdm->regmap, I2S_RXCR, &val);
val &= I2S_RXCR_CSR_MASK;
if (to_ch_num(val) > usable_chs) {
dev_err(i2s_tdm->dev,
"Capture channels (%d) > usable channels (%d)\n",
to_ch_num(val), usable_chs);
return -EINVAL;
}
rockchip_i2s_ch_to_io(val, true);
} else {
struct snd_pcm_str *capture_str =
&substream->pcm->streams[SNDRV_PCM_STREAM_CAPTURE];
if (capture_str->substream_opened) {
regmap_read(i2s_tdm->regmap, I2S_RXCR, &val);
val &= I2S_RXCR_CSR_MASK;
usable_chs = MULTIPLEX_CH_MAX - to_ch_num(val);
}
regmap_read(i2s_tdm->regmap, I2S_TXCR, &val);
val &= I2S_TXCR_CSR_MASK;
if (to_ch_num(val) > usable_chs) {
dev_err(i2s_tdm->dev,
"Playback channels (%d) > usable channels (%d)\n",
to_ch_num(val), usable_chs);
return -EINVAL;
}
}
val <<= i2s_tdm->soc_data->grf_shift;
val |= (I2S_IO_DIRECTION_MASK << i2s_tdm->soc_data->grf_shift) << 16;
regmap_write(i2s_tdm->grf, i2s_tdm->soc_data->grf_reg_offset, val);
return 0;
}
static int rockchip_i2s_trcm_mode(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai,
unsigned int div_bclk,
unsigned int div_lrck,
unsigned int fmt)
{
struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
unsigned long flags;
if (!i2s_tdm->clk_trcm)
return 0;
spin_lock_irqsave(&i2s_tdm->lock, flags);
if (i2s_tdm->refcount)
rockchip_i2s_tdm_xfer_pause(substream, i2s_tdm);
regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
I2S_CLKDIV_TXM_MASK | I2S_CLKDIV_RXM_MASK,
I2S_CLKDIV_TXM(div_bclk) | I2S_CLKDIV_RXM(div_bclk));
regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
I2S_CKR_TSD_MASK | I2S_CKR_RSD_MASK,
I2S_CKR_TSD(div_lrck) | I2S_CKR_RSD(div_lrck));
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
regmap_update_bits(i2s_tdm->regmap, I2S_TXCR,
I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
fmt);
else
regmap_update_bits(i2s_tdm->regmap, I2S_RXCR,
I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
fmt);
if (i2s_tdm->refcount)
rockchip_i2s_tdm_xfer_resume(substream, i2s_tdm);
spin_unlock_irqrestore(&i2s_tdm->lock, flags);
return 0;
}
static int rockchip_i2s_tdm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
struct clk *mclk;
int ret = 0;
unsigned int val = 0;
unsigned int mclk_rate, bclk_rate, div_bclk = 4, div_lrck = 64;
if (i2s_tdm->is_master_mode) {
if (i2s_tdm->mclk_calibrate)
rockchip_i2s_tdm_calibrate_mclk(i2s_tdm, substream,
params_rate(params));
ret = rockchip_i2s_tdm_set_mclk(i2s_tdm, substream, &mclk);
if (ret)
return ret;
mclk_rate = clk_get_rate(mclk);
bclk_rate = i2s_tdm->frame_width * params_rate(params);
if (!bclk_rate)
return -EINVAL;
div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
div_lrck = bclk_rate / params_rate(params);
}
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S8:
val |= I2S_TXCR_VDW(8);
break;
case SNDRV_PCM_FORMAT_S16_LE:
val |= I2S_TXCR_VDW(16);
break;
case SNDRV_PCM_FORMAT_S20_3LE:
val |= I2S_TXCR_VDW(20);
break;
case SNDRV_PCM_FORMAT_S24_LE:
val |= I2S_TXCR_VDW(24);
break;
case SNDRV_PCM_FORMAT_S32_LE:
val |= I2S_TXCR_VDW(32);
break;
default:
return -EINVAL;
}
switch (params_channels(params)) {
case 8:
val |= I2S_CHN_8;
break;
case 6:
val |= I2S_CHN_6;
break;
case 4:
val |= I2S_CHN_4;
break;
case 2:
val |= I2S_CHN_2;
break;
default:
return -EINVAL;
}
if (i2s_tdm->clk_trcm) {
rockchip_i2s_trcm_mode(substream, dai, div_bclk, div_lrck, val);
} else if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
I2S_CLKDIV_TXM_MASK,
I2S_CLKDIV_TXM(div_bclk));
regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
I2S_CKR_TSD_MASK,
I2S_CKR_TSD(div_lrck));
regmap_update_bits(i2s_tdm->regmap, I2S_TXCR,
I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
val);
} else {
regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
I2S_CLKDIV_RXM_MASK,
I2S_CLKDIV_RXM(div_bclk));
regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
I2S_CKR_RSD_MASK,
I2S_CKR_RSD(div_lrck));
regmap_update_bits(i2s_tdm->regmap, I2S_RXCR,
I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
val);
}
return rockchip_i2s_io_multiplex(substream, dai);
}
static int rockchip_i2s_tdm_trigger(struct snd_pcm_substream *substream,
int cmd, struct snd_soc_dai *dai)
{
struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
if (i2s_tdm->clk_trcm)
rockchip_snd_txrxctrl(substream, dai, 1);
else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
rockchip_snd_rxctrl(i2s_tdm, 1);
else
rockchip_snd_txctrl(i2s_tdm, 1);
break;
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
if (i2s_tdm->clk_trcm)
rockchip_snd_txrxctrl(substream, dai, 0);
else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
rockchip_snd_rxctrl(i2s_tdm, 0);
else
rockchip_snd_txctrl(i2s_tdm, 0);
break;
default:
return -EINVAL;
}
return 0;
}
static int rockchip_i2s_tdm_set_sysclk(struct snd_soc_dai *cpu_dai, int stream,
unsigned int freq, int dir)
{
struct rk_i2s_tdm_dev *i2s_tdm = to_info(cpu_dai);
/* Put set mclk rate into rockchip_i2s_tdm_set_mclk() */
if (i2s_tdm->clk_trcm) {
i2s_tdm->mclk_tx_freq = freq;
i2s_tdm->mclk_rx_freq = freq;
} else {
if (stream == SNDRV_PCM_STREAM_PLAYBACK)
i2s_tdm->mclk_tx_freq = freq;
else
i2s_tdm->mclk_rx_freq = freq;
}
dev_dbg(i2s_tdm->dev, "The target mclk_%s freq is: %d\n",
stream ? "rx" : "tx", freq);
return 0;
}
static int rockchip_i2s_tdm_clk_compensation_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
uinfo->count = 1;
uinfo->value.integer.min = CLK_PPM_MIN;
uinfo->value.integer.max = CLK_PPM_MAX;
uinfo->value.integer.step = 1;
return 0;
}
static int rockchip_i2s_tdm_clk_compensation_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
ucontrol->value.integer.value[0] = i2s_tdm->clk_ppm;
return 0;
}
static int rockchip_i2s_tdm_clk_compensation_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
int ret = 0, ppm = 0;
int changed = 0;
unsigned long old_rate;
if (ucontrol->value.integer.value[0] < CLK_PPM_MIN ||
ucontrol->value.integer.value[0] > CLK_PPM_MAX)
return -EINVAL;
ppm = ucontrol->value.integer.value[0];
old_rate = clk_get_rate(i2s_tdm->mclk_root0);
ret = rockchip_i2s_tdm_clk_set_rate(i2s_tdm, i2s_tdm->mclk_root0,
i2s_tdm->mclk_root0_freq, ppm);
if (ret)
return ret;
if (old_rate != clk_get_rate(i2s_tdm->mclk_root0))
changed = 1;
if (clk_is_match(i2s_tdm->mclk_root0, i2s_tdm->mclk_root1))
return changed;
old_rate = clk_get_rate(i2s_tdm->mclk_root1);
ret = rockchip_i2s_tdm_clk_set_rate(i2s_tdm, i2s_tdm->mclk_root1,
i2s_tdm->mclk_root1_freq, ppm);
if (ret)
return ret;
if (old_rate != clk_get_rate(i2s_tdm->mclk_root1))
changed = 1;
return changed;
}
static struct snd_kcontrol_new rockchip_i2s_tdm_compensation_control = {
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
.name = "PCM Clock Compensation in PPM",
.info = rockchip_i2s_tdm_clk_compensation_info,
.get = rockchip_i2s_tdm_clk_compensation_get,
.put = rockchip_i2s_tdm_clk_compensation_put,
};
static int rockchip_i2s_tdm_dai_probe(struct snd_soc_dai *dai)
{
struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
if (i2s_tdm->has_capture)
snd_soc_dai_dma_data_set_capture(dai, &i2s_tdm->capture_dma_data);
if (i2s_tdm->has_playback)
snd_soc_dai_dma_data_set_playback(dai, &i2s_tdm->playback_dma_data);
if (i2s_tdm->mclk_calibrate)
snd_soc_add_dai_controls(dai, &rockchip_i2s_tdm_compensation_control, 1);
return 0;
}
static int rockchip_dai_tdm_slot(struct snd_soc_dai *dai,
unsigned int tx_mask, unsigned int rx_mask,
int slots, int slot_width)
{
struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
unsigned int mask, val;
i2s_tdm->tdm_mode = true;
i2s_tdm->frame_width = slots * slot_width;
mask = TDM_SLOT_BIT_WIDTH_MSK | TDM_FRAME_WIDTH_MSK;
val = TDM_SLOT_BIT_WIDTH(slot_width) |
TDM_FRAME_WIDTH(slots * slot_width);
regmap_update_bits(i2s_tdm->regmap, I2S_TDM_TXCR,
mask, val);
regmap_update_bits(i2s_tdm->regmap, I2S_TDM_RXCR,
mask, val);
return 0;
}
static int rockchip_i2s_tdm_set_bclk_ratio(struct snd_soc_dai *dai,
unsigned int ratio)
{
struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
if (ratio < 32 || ratio > 512 || ratio % 2 == 1)
return -EINVAL;
i2s_tdm->frame_width = ratio;
return 0;
}
static const struct snd_soc_dai_ops rockchip_i2s_tdm_dai_ops = {
.probe = rockchip_i2s_tdm_dai_probe,
.hw_params = rockchip_i2s_tdm_hw_params,
.set_bclk_ratio = rockchip_i2s_tdm_set_bclk_ratio,
.set_sysclk = rockchip_i2s_tdm_set_sysclk,
.set_fmt = rockchip_i2s_tdm_set_fmt,
.set_tdm_slot = rockchip_dai_tdm_slot,
.trigger = rockchip_i2s_tdm_trigger,
};
static const struct snd_soc_component_driver rockchip_i2s_tdm_component = {
.name = DRV_NAME,
.legacy_dai_naming = 1,
};
static bool rockchip_i2s_tdm_wr_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case I2S_TXCR:
case I2S_RXCR:
case I2S_CKR:
case I2S_DMACR:
case I2S_INTCR:
case I2S_XFER:
case I2S_CLR:
case I2S_TXDR:
case I2S_TDM_TXCR:
case I2S_TDM_RXCR:
case I2S_CLKDIV:
return true;
default:
return false;
}
}
static bool rockchip_i2s_tdm_rd_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case I2S_TXCR:
case I2S_RXCR:
case I2S_CKR:
case I2S_DMACR:
case I2S_INTCR:
case I2S_XFER:
case I2S_CLR:
case I2S_TXDR:
case I2S_RXDR:
case I2S_TXFIFOLR:
case I2S_INTSR:
case I2S_RXFIFOLR:
case I2S_TDM_TXCR:
case I2S_TDM_RXCR:
case I2S_CLKDIV:
return true;
default:
return false;
}
}
static bool rockchip_i2s_tdm_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case I2S_TXFIFOLR:
case I2S_INTSR:
case I2S_CLR:
case I2S_TXDR:
case I2S_RXDR:
case I2S_RXFIFOLR:
return true;
default:
return false;
}
}
static bool rockchip_i2s_tdm_precious_reg(struct device *dev, unsigned int reg)
{
if (reg == I2S_RXDR)
return true;
return false;
}
static const struct reg_default rockchip_i2s_tdm_reg_defaults[] = {
{0x00, 0x7200000f},
{0x04, 0x01c8000f},
{0x08, 0x00001f1f},
{0x10, 0x001f0000},
{0x14, 0x01f00000},
{0x30, 0x00003eff},
{0x34, 0x00003eff},
{0x38, 0x00000707},
};
static const struct regmap_config rockchip_i2s_tdm_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = I2S_CLKDIV,
.reg_defaults = rockchip_i2s_tdm_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(rockchip_i2s_tdm_reg_defaults),
.writeable_reg = rockchip_i2s_tdm_wr_reg,
.readable_reg = rockchip_i2s_tdm_rd_reg,
.volatile_reg = rockchip_i2s_tdm_volatile_reg,
.precious_reg = rockchip_i2s_tdm_precious_reg,
.cache_type = REGCACHE_FLAT,
};
static int common_soc_init(struct device *dev, u32 addr)
{
struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
const struct txrx_config *configs = i2s_tdm->soc_data->configs;
u32 reg = 0, val = 0, trcm = i2s_tdm->clk_trcm;
int i;
if (trcm == TRCM_TXRX)
return 0;
if (IS_ERR_OR_NULL(i2s_tdm->grf)) {
dev_err(i2s_tdm->dev,
"no grf present but non-txrx TRCM specified\n");
return -EINVAL;
}
for (i = 0; i < i2s_tdm->soc_data->config_count; i++) {
if (addr != configs[i].addr)
continue;
reg = configs[i].reg;
if (trcm == TRCM_TX)
val = configs[i].txonly;
else
val = configs[i].rxonly;
if (reg)
regmap_write(i2s_tdm->grf, reg, val);
}
return 0;
}
static const struct txrx_config px30_txrx_config[] = {
{ 0xff060000, 0x184, PX30_I2S0_CLK_TXONLY, PX30_I2S0_CLK_RXONLY },
};
static const struct txrx_config rk1808_txrx_config[] = {
{ 0xff7e0000, 0x190, RK1808_I2S0_CLK_TXONLY, RK1808_I2S0_CLK_RXONLY },
};
static const struct txrx_config rk3308_txrx_config[] = {
{ 0xff300000, 0x308, RK3308_I2S0_CLK_TXONLY, RK3308_I2S0_CLK_RXONLY },
{ 0xff310000, 0x308, RK3308_I2S1_CLK_TXONLY, RK3308_I2S1_CLK_RXONLY },
};
static const struct txrx_config rk3568_txrx_config[] = {
{ 0xfe410000, 0x504, RK3568_I2S1_CLK_TXONLY, RK3568_I2S1_CLK_RXONLY },
{ 0xfe410000, 0x508, RK3568_I2S1_MCLK_TX_OE, RK3568_I2S1_MCLK_RX_OE },
{ 0xfe420000, 0x508, RK3568_I2S2_MCLK_OE, RK3568_I2S2_MCLK_OE },
{ 0xfe430000, 0x504, RK3568_I2S3_CLK_TXONLY, RK3568_I2S3_CLK_RXONLY },
{ 0xfe430000, 0x508, RK3568_I2S3_MCLK_TXONLY, RK3568_I2S3_MCLK_RXONLY },
{ 0xfe430000, 0x508, RK3568_I2S3_MCLK_OE, RK3568_I2S3_MCLK_OE },
};
static const struct txrx_config rv1126_txrx_config[] = {
{ 0xff800000, 0x10260, RV1126_I2S0_CLK_TXONLY, RV1126_I2S0_CLK_RXONLY },
};
static struct rk_i2s_soc_data px30_i2s_soc_data = {
.softrst_offset = 0x0300,
.configs = px30_txrx_config,
.config_count = ARRAY_SIZE(px30_txrx_config),
.init = common_soc_init,
};
static struct rk_i2s_soc_data rk1808_i2s_soc_data = {
.softrst_offset = 0x0300,
.configs = rk1808_txrx_config,
.config_count = ARRAY_SIZE(rk1808_txrx_config),
.init = common_soc_init,
};
static struct rk_i2s_soc_data rk3308_i2s_soc_data = {
.softrst_offset = 0x0400,
.grf_reg_offset = 0x0308,
.grf_shift = 5,
.configs = rk3308_txrx_config,
.config_count = ARRAY_SIZE(rk3308_txrx_config),
.init = common_soc_init,
};
static struct rk_i2s_soc_data rk3568_i2s_soc_data = {
.softrst_offset = 0x0400,
.configs = rk3568_txrx_config,
.config_count = ARRAY_SIZE(rk3568_txrx_config),
.init = common_soc_init,
};
static struct rk_i2s_soc_data rv1126_i2s_soc_data = {
.softrst_offset = 0x0300,
.configs = rv1126_txrx_config,
.config_count = ARRAY_SIZE(rv1126_txrx_config),
.init = common_soc_init,
};
static const struct of_device_id rockchip_i2s_tdm_match[] = {
{ .compatible = "rockchip,px30-i2s-tdm", .data = &px30_i2s_soc_data },
{ .compatible = "rockchip,rk1808-i2s-tdm", .data = &rk1808_i2s_soc_data },
{ .compatible = "rockchip,rk3308-i2s-tdm", .data = &rk3308_i2s_soc_data },
{ .compatible = "rockchip,rk3568-i2s-tdm", .data = &rk3568_i2s_soc_data },
{ .compatible = "rockchip,rk3588-i2s-tdm" },
{ .compatible = "rockchip,rv1126-i2s-tdm", .data = &rv1126_i2s_soc_data },
{},
};
static const struct snd_soc_dai_driver i2s_tdm_dai = {
.ops = &rockchip_i2s_tdm_dai_ops,
};
static int rockchip_i2s_tdm_init_dai(struct rk_i2s_tdm_dev *i2s_tdm)
{
struct snd_soc_dai_driver *dai;
struct property *dma_names;
const char *dma_name;
u64 formats = (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |
SNDRV_PCM_FMTBIT_S32_LE);
struct device_node *node = i2s_tdm->dev->of_node;
of_property_for_each_string(node, "dma-names", dma_names, dma_name) {
if (!strcmp(dma_name, "tx"))
i2s_tdm->has_playback = true;
if (!strcmp(dma_name, "rx"))
i2s_tdm->has_capture = true;
}
dai = devm_kmemdup(i2s_tdm->dev, &i2s_tdm_dai,
sizeof(*dai), GFP_KERNEL);
if (!dai)
return -ENOMEM;
if (i2s_tdm->has_playback) {
dai->playback.stream_name = "Playback";
dai->playback.channels_min = 2;
dai->playback.channels_max = 8;
dai->playback.rates = SNDRV_PCM_RATE_8000_192000;
dai->playback.formats = formats;
}
if (i2s_tdm->has_capture) {
dai->capture.stream_name = "Capture";
dai->capture.channels_min = 2;
dai->capture.channels_max = 8;
dai->capture.rates = SNDRV_PCM_RATE_8000_192000;
dai->capture.formats = formats;
}
if (i2s_tdm->clk_trcm != TRCM_TXRX)
dai->symmetric_rate = 1;
i2s_tdm->dai = dai;
return 0;
}
static int rockchip_i2s_tdm_path_check(struct rk_i2s_tdm_dev *i2s_tdm,
int num,
bool is_rx_path)
{
unsigned int *i2s_data;
int i, j;
if (is_rx_path)
i2s_data = i2s_tdm->i2s_sdis;
else
i2s_data = i2s_tdm->i2s_sdos;
for (i = 0; i < num; i++) {
if (i2s_data[i] > CH_GRP_MAX - 1) {
dev_err(i2s_tdm->dev,
"%s path i2s_data[%d]: %d is too high, max is: %d\n",
is_rx_path ? "RX" : "TX",
i, i2s_data[i], CH_GRP_MAX);
return -EINVAL;
}
for (j = 0; j < num; j++) {
if (i == j)
continue;
if (i2s_data[i] == i2s_data[j]) {
dev_err(i2s_tdm->dev,
"%s path invalid routed i2s_data: [%d]%d == [%d]%d\n",
is_rx_path ? "RX" : "TX",
i, i2s_data[i],
j, i2s_data[j]);
return -EINVAL;
}
}
}
return 0;
}
static void rockchip_i2s_tdm_tx_path_config(struct rk_i2s_tdm_dev *i2s_tdm,
int num)
{
int idx;
for (idx = 0; idx < num; idx++) {
regmap_update_bits(i2s_tdm->regmap, I2S_TXCR,
I2S_TXCR_PATH_MASK(idx),
I2S_TXCR_PATH(idx, i2s_tdm->i2s_sdos[idx]));
}
}
static void rockchip_i2s_tdm_rx_path_config(struct rk_i2s_tdm_dev *i2s_tdm,
int num)
{
int idx;
for (idx = 0; idx < num; idx++) {
regmap_update_bits(i2s_tdm->regmap, I2S_RXCR,
I2S_RXCR_PATH_MASK(idx),
I2S_RXCR_PATH(idx, i2s_tdm->i2s_sdis[idx]));
}
}
static void rockchip_i2s_tdm_path_config(struct rk_i2s_tdm_dev *i2s_tdm,
int num, bool is_rx_path)
{
if (is_rx_path)
rockchip_i2s_tdm_rx_path_config(i2s_tdm, num);
else
rockchip_i2s_tdm_tx_path_config(i2s_tdm, num);
}
static int rockchip_i2s_tdm_get_calibrate_mclks(struct rk_i2s_tdm_dev *i2s_tdm)
{
int num_mclks = 0;
i2s_tdm->mclk_tx_src = devm_clk_get(i2s_tdm->dev, "mclk_tx_src");
if (!IS_ERR(i2s_tdm->mclk_tx_src))
num_mclks++;
i2s_tdm->mclk_rx_src = devm_clk_get(i2s_tdm->dev, "mclk_rx_src");
if (!IS_ERR(i2s_tdm->mclk_rx_src))
num_mclks++;
i2s_tdm->mclk_root0 = devm_clk_get(i2s_tdm->dev, "mclk_root0");
if (!IS_ERR(i2s_tdm->mclk_root0))
num_mclks++;
i2s_tdm->mclk_root1 = devm_clk_get(i2s_tdm->dev, "mclk_root1");
if (!IS_ERR(i2s_tdm->mclk_root1))
num_mclks++;
if (num_mclks < 4 && num_mclks != 0)
return -ENOENT;
if (num_mclks == 4)
i2s_tdm->mclk_calibrate = 1;
return 0;
}
static int rockchip_i2s_tdm_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm,
struct device_node *np,
bool is_rx_path)
{
char *i2s_tx_path_prop = "rockchip,i2s-tx-route";
char *i2s_rx_path_prop = "rockchip,i2s-rx-route";
char *i2s_path_prop;
unsigned int *i2s_data;
int num, ret = 0;
if (is_rx_path) {
i2s_path_prop = i2s_rx_path_prop;
i2s_data = i2s_tdm->i2s_sdis;
} else {
i2s_path_prop = i2s_tx_path_prop;
i2s_data = i2s_tdm->i2s_sdos;
}
num = of_count_phandle_with_args(np, i2s_path_prop, NULL);
if (num < 0) {
if (num != -ENOENT) {
dev_err(i2s_tdm->dev,
"Failed to read '%s' num: %d\n",
i2s_path_prop, num);
ret = num;
}
return ret;
} else if (num != CH_GRP_MAX) {
dev_err(i2s_tdm->dev,
"The num: %d should be: %d\n", num, CH_GRP_MAX);
return -EINVAL;
}
ret = of_property_read_u32_array(np, i2s_path_prop,
i2s_data, num);
if (ret < 0) {
dev_err(i2s_tdm->dev,
"Failed to read '%s': %d\n",
i2s_path_prop, ret);
return ret;
}
ret = rockchip_i2s_tdm_path_check(i2s_tdm, num, is_rx_path);
if (ret < 0) {
dev_err(i2s_tdm->dev,
"Failed to check i2s data bus: %d\n", ret);
return ret;
}
rockchip_i2s_tdm_path_config(i2s_tdm, num, is_rx_path);
return 0;
}
static int rockchip_i2s_tdm_tx_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm,
struct device_node *np)
{
return rockchip_i2s_tdm_path_prepare(i2s_tdm, np, 0);
}
static int rockchip_i2s_tdm_rx_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm,
struct device_node *np)
{
return rockchip_i2s_tdm_path_prepare(i2s_tdm, np, 1);
}
static int rockchip_i2s_tdm_probe(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
const struct of_device_id *of_id;
struct rk_i2s_tdm_dev *i2s_tdm;
struct resource *res;
void __iomem *regs;
int ret;
i2s_tdm = devm_kzalloc(&pdev->dev, sizeof(*i2s_tdm), GFP_KERNEL);
if (!i2s_tdm)
return -ENOMEM;
i2s_tdm->dev = &pdev->dev;
of_id = of_match_device(rockchip_i2s_tdm_match, &pdev->dev);
if (!of_id)
return -EINVAL;
spin_lock_init(&i2s_tdm->lock);
i2s_tdm->soc_data = (struct rk_i2s_soc_data *)of_id->data;
i2s_tdm->frame_width = 64;
i2s_tdm->clk_trcm = TRCM_TXRX;
if (of_property_read_bool(node, "rockchip,trcm-sync-tx-only"))
i2s_tdm->clk_trcm = TRCM_TX;
if (of_property_read_bool(node, "rockchip,trcm-sync-rx-only")) {
if (i2s_tdm->clk_trcm) {
dev_err(i2s_tdm->dev, "invalid trcm-sync configuration\n");
return -EINVAL;
}
i2s_tdm->clk_trcm = TRCM_RX;
}
ret = rockchip_i2s_tdm_init_dai(i2s_tdm);
if (ret)
return ret;
i2s_tdm->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
i2s_tdm->tx_reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
"tx-m");
if (IS_ERR(i2s_tdm->tx_reset)) {
ret = PTR_ERR(i2s_tdm->tx_reset);
return dev_err_probe(i2s_tdm->dev, ret,
"Error in tx-m reset control\n");
}
i2s_tdm->rx_reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
"rx-m");
if (IS_ERR(i2s_tdm->rx_reset)) {
ret = PTR_ERR(i2s_tdm->rx_reset);
return dev_err_probe(i2s_tdm->dev, ret,
"Error in rx-m reset control\n");
}
i2s_tdm->hclk = devm_clk_get(&pdev->dev, "hclk");
if (IS_ERR(i2s_tdm->hclk)) {
return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->hclk),
"Failed to get clock hclk\n");
}
i2s_tdm->mclk_tx = devm_clk_get(&pdev->dev, "mclk_tx");
if (IS_ERR(i2s_tdm->mclk_tx)) {
return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->mclk_tx),
"Failed to get clock mclk_tx\n");
}
i2s_tdm->mclk_rx = devm_clk_get(&pdev->dev, "mclk_rx");
if (IS_ERR(i2s_tdm->mclk_rx)) {
return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->mclk_rx),
"Failed to get clock mclk_rx\n");
}
i2s_tdm->io_multiplex =
of_property_read_bool(node, "rockchip,io-multiplex");
ret = rockchip_i2s_tdm_get_calibrate_mclks(i2s_tdm);
if (ret)
return dev_err_probe(i2s_tdm->dev, ret,
"mclk-calibrate clocks missing");
regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(regs)) {
return dev_err_probe(i2s_tdm->dev, PTR_ERR(regs),
"Failed to get resource IORESOURCE_MEM\n");
}
i2s_tdm->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
&rockchip_i2s_tdm_regmap_config);
if (IS_ERR(i2s_tdm->regmap)) {
return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->regmap),
"Failed to initialise regmap\n");
}
if (i2s_tdm->has_playback) {
i2s_tdm->playback_dma_data.addr = res->start + I2S_TXDR;
i2s_tdm->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
i2s_tdm->playback_dma_data.maxburst = 8;
}
if (i2s_tdm->has_capture) {
i2s_tdm->capture_dma_data.addr = res->start + I2S_RXDR;
i2s_tdm->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
i2s_tdm->capture_dma_data.maxburst = 8;
}
ret = rockchip_i2s_tdm_tx_path_prepare(i2s_tdm, node);
if (ret < 0) {
dev_err(&pdev->dev, "I2S TX path prepare failed: %d\n", ret);
return ret;
}
ret = rockchip_i2s_tdm_rx_path_prepare(i2s_tdm, node);
if (ret < 0) {
dev_err(&pdev->dev, "I2S RX path prepare failed: %d\n", ret);
return ret;
}
dev_set_drvdata(&pdev->dev, i2s_tdm);
ret = clk_prepare_enable(i2s_tdm->hclk);
if (ret) {
return dev_err_probe(i2s_tdm->dev, ret,
"Failed to enable clock hclk\n");
}
ret = i2s_tdm_prepare_enable_mclk(i2s_tdm);
if (ret) {
ret = dev_err_probe(i2s_tdm->dev, ret,
"Failed to enable one or more mclks\n");
goto err_disable_hclk;
}
if (i2s_tdm->mclk_calibrate) {
i2s_tdm->mclk_root0_initial_freq = clk_get_rate(i2s_tdm->mclk_root0);
i2s_tdm->mclk_root1_initial_freq = clk_get_rate(i2s_tdm->mclk_root1);
i2s_tdm->mclk_root0_freq = i2s_tdm->mclk_root0_initial_freq;
i2s_tdm->mclk_root1_freq = i2s_tdm->mclk_root1_initial_freq;
}
pm_runtime_enable(&pdev->dev);
regmap_update_bits(i2s_tdm->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
I2S_DMACR_TDL(16));
regmap_update_bits(i2s_tdm->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
I2S_DMACR_RDL(16));
regmap_update_bits(i2s_tdm->regmap, I2S_CKR, I2S_CKR_TRCM_MASK,
i2s_tdm->clk_trcm << I2S_CKR_TRCM_SHIFT);
if (i2s_tdm->soc_data && i2s_tdm->soc_data->init)
i2s_tdm->soc_data->init(&pdev->dev, res->start);
ret = devm_snd_soc_register_component(&pdev->dev,
&rockchip_i2s_tdm_component,
i2s_tdm->dai, 1);
if (ret) {
dev_err(&pdev->dev, "Could not register DAI\n");
goto err_suspend;
}
ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
if (ret) {
dev_err(&pdev->dev, "Could not register PCM\n");
goto err_suspend;
}
return 0;
err_suspend:
if (!pm_runtime_status_suspended(&pdev->dev))
i2s_tdm_runtime_suspend(&pdev->dev);
pm_runtime_disable(&pdev->dev);
err_disable_hclk:
clk_disable_unprepare(i2s_tdm->hclk);
return ret;
}
static int rockchip_i2s_tdm_remove(struct platform_device *pdev)
{
if (!pm_runtime_status_suspended(&pdev->dev))
i2s_tdm_runtime_suspend(&pdev->dev);
pm_runtime_disable(&pdev->dev);
return 0;
}
static int __maybe_unused rockchip_i2s_tdm_suspend(struct device *dev)
{
struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
regcache_mark_dirty(i2s_tdm->regmap);
return 0;
}
static int __maybe_unused rockchip_i2s_tdm_resume(struct device *dev)
{
struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
int ret;
ret = pm_runtime_resume_and_get(dev);
if (ret < 0)
return ret;
ret = regcache_sync(i2s_tdm->regmap);
pm_runtime_put(dev);
return ret;
}
static const struct dev_pm_ops rockchip_i2s_tdm_pm_ops = {
SET_RUNTIME_PM_OPS(i2s_tdm_runtime_suspend, i2s_tdm_runtime_resume,
NULL)
SET_SYSTEM_SLEEP_PM_OPS(rockchip_i2s_tdm_suspend,
rockchip_i2s_tdm_resume)
};
static struct platform_driver rockchip_i2s_tdm_driver = {
.probe = rockchip_i2s_tdm_probe,
.remove = rockchip_i2s_tdm_remove,
.driver = {
.name = DRV_NAME,
.of_match_table = of_match_ptr(rockchip_i2s_tdm_match),
.pm = &rockchip_i2s_tdm_pm_ops,
},
};
module_platform_driver(rockchip_i2s_tdm_driver);
MODULE_DESCRIPTION("ROCKCHIP I2S/TDM ASoC Interface");
MODULE_AUTHOR("Sugar Zhang <[email protected]>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRV_NAME);
MODULE_DEVICE_TABLE(of, rockchip_i2s_tdm_match);
| linux-master | sound/soc/rockchip/rockchip_i2s_tdm.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Rockchip machine ASoC driver for boards using MAX98357A/RT5514/DA7219
*
* Copyright (c) 2016, ROCKCHIP CORPORATION. All rights reserved.
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/gpio.h>
#include <linux/of_gpio.h>
#include <linux/delay.h>
#include <linux/spi/spi.h>
#include <linux/i2c.h>
#include <linux/input.h>
#include <sound/core.h>
#include <sound/jack.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include "rockchip_i2s.h"
#include "../codecs/da7219.h"
#include "../codecs/rt5514.h"
#define DRV_NAME "rk3399-gru-sound"
#define SOUND_FS 256
static unsigned int dmic_wakeup_delay;
static struct snd_soc_jack rockchip_sound_jack;
/* Headset jack detection DAPM pins */
static struct snd_soc_jack_pin rockchip_sound_jack_pins[] = {
{
.pin = "Headphones",
.mask = SND_JACK_HEADPHONE,
},
{
.pin = "Headset Mic",
.mask = SND_JACK_MICROPHONE,
},
{
.pin = "Line Out",
.mask = SND_JACK_LINEOUT,
},
};
static const struct snd_soc_dapm_widget rockchip_dapm_widgets[] = {
SND_SOC_DAPM_HP("Headphones", NULL),
SND_SOC_DAPM_SPK("Speakers", NULL),
SND_SOC_DAPM_MIC("Headset Mic", NULL),
SND_SOC_DAPM_LINE("Line Out", NULL),
SND_SOC_DAPM_MIC("Int Mic", NULL),
SND_SOC_DAPM_LINE("HDMI", NULL),
};
static const struct snd_kcontrol_new rockchip_controls[] = {
SOC_DAPM_PIN_SWITCH("Headphones"),
SOC_DAPM_PIN_SWITCH("Speakers"),
SOC_DAPM_PIN_SWITCH("Headset Mic"),
SOC_DAPM_PIN_SWITCH("Line Out"),
SOC_DAPM_PIN_SWITCH("Int Mic"),
SOC_DAPM_PIN_SWITCH("HDMI"),
};
static int rockchip_sound_max98357a_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
unsigned int mclk;
int ret;
mclk = params_rate(params) * SOUND_FS;
ret = snd_soc_dai_set_sysclk(asoc_rtd_to_cpu(rtd, 0), 0, mclk, 0);
if (ret) {
dev_err(rtd->card->dev, "%s() error setting sysclk to %u: %d\n",
__func__, mclk, ret);
return ret;
}
return 0;
}
static int rockchip_sound_rt5514_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
unsigned int mclk;
int ret;
mclk = params_rate(params) * SOUND_FS;
ret = snd_soc_dai_set_sysclk(cpu_dai, 0, mclk,
SND_SOC_CLOCK_OUT);
if (ret < 0) {
dev_err(rtd->card->dev, "Can't set cpu clock out %d\n", ret);
return ret;
}
ret = snd_soc_dai_set_sysclk(codec_dai, RT5514_SCLK_S_MCLK,
mclk, SND_SOC_CLOCK_IN);
if (ret) {
dev_err(rtd->card->dev, "%s() error setting sysclk to %u: %d\n",
__func__, params_rate(params) * 512, ret);
return ret;
}
/* Wait for DMIC stable */
msleep(dmic_wakeup_delay);
return 0;
}
static int rockchip_sound_da7219_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
int mclk, ret;
/* in bypass mode, the mclk has to be one of the frequencies below */
switch (params_rate(params)) {
case 8000:
case 16000:
case 24000:
case 32000:
case 48000:
case 64000:
case 96000:
mclk = 12288000;
break;
case 11025:
case 22050:
case 44100:
case 88200:
mclk = 11289600;
break;
default:
return -EINVAL;
}
ret = snd_soc_dai_set_sysclk(cpu_dai, 0, mclk,
SND_SOC_CLOCK_OUT);
if (ret < 0) {
dev_err(codec_dai->dev, "Can't set cpu clock out %d\n", ret);
return ret;
}
ret = snd_soc_dai_set_sysclk(codec_dai, 0, mclk,
SND_SOC_CLOCK_IN);
if (ret < 0) {
dev_err(codec_dai->dev, "Can't set codec clock in %d\n", ret);
return ret;
}
ret = snd_soc_dai_set_pll(codec_dai, 0, DA7219_SYSCLK_MCLK, 0, 0);
if (ret < 0) {
dev_err(codec_dai->dev, "Can't set pll sysclk mclk %d\n", ret);
return ret;
}
return 0;
}
static struct snd_soc_jack cdn_dp_card_jack;
static int rockchip_sound_cdndp_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component;
struct snd_soc_card *card = rtd->card;
int ret;
/* Enable jack detection. */
ret = snd_soc_card_jack_new(card, "DP Jack", SND_JACK_LINEOUT,
&cdn_dp_card_jack);
if (ret) {
dev_err(card->dev, "Can't create DP Jack %d\n", ret);
return ret;
}
return snd_soc_component_set_jack(component, &cdn_dp_card_jack, NULL);
}
static int rockchip_sound_da7219_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component;
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
int ret;
/* We need default MCLK and PLL settings for the accessory detection */
ret = snd_soc_dai_set_sysclk(codec_dai, 0, 12288000,
SND_SOC_CLOCK_IN);
if (ret < 0) {
dev_err(codec_dai->dev, "Init can't set codec clock in %d\n", ret);
return ret;
}
ret = snd_soc_dai_set_pll(codec_dai, 0, DA7219_SYSCLK_MCLK, 0, 0);
if (ret < 0) {
dev_err(codec_dai->dev, "Init can't set pll sysclk mclk %d\n", ret);
return ret;
}
/* Enable Headset and 4 Buttons Jack detection */
ret = snd_soc_card_jack_new_pins(rtd->card, "Headset Jack",
SND_JACK_HEADSET | SND_JACK_LINEOUT |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3,
&rockchip_sound_jack,
rockchip_sound_jack_pins,
ARRAY_SIZE(rockchip_sound_jack_pins));
if (ret) {
dev_err(rtd->card->dev, "New Headset Jack failed! (%d)\n", ret);
return ret;
}
snd_jack_set_key(
rockchip_sound_jack.jack, SND_JACK_BTN_0, KEY_PLAYPAUSE);
snd_jack_set_key(
rockchip_sound_jack.jack, SND_JACK_BTN_1, KEY_VOLUMEUP);
snd_jack_set_key(
rockchip_sound_jack.jack, SND_JACK_BTN_2, KEY_VOLUMEDOWN);
snd_jack_set_key(
rockchip_sound_jack.jack, SND_JACK_BTN_3, KEY_VOICECOMMAND);
snd_soc_component_set_jack(component, &rockchip_sound_jack, NULL);
return 0;
}
static int rockchip_sound_dmic_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
unsigned int mclk;
int ret;
mclk = params_rate(params) * SOUND_FS;
ret = snd_soc_dai_set_sysclk(asoc_rtd_to_cpu(rtd, 0), 0, mclk, 0);
if (ret) {
dev_err(rtd->card->dev, "%s() error setting sysclk to %u: %d\n",
__func__, mclk, ret);
return ret;
}
/* Wait for DMIC stable */
msleep(dmic_wakeup_delay);
return 0;
}
static int rockchip_sound_startup(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
runtime->hw.formats = SNDRV_PCM_FMTBIT_S16_LE;
return snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_RATE,
8000, 96000);
}
static const struct snd_soc_ops rockchip_sound_max98357a_ops = {
.startup = rockchip_sound_startup,
.hw_params = rockchip_sound_max98357a_hw_params,
};
static const struct snd_soc_ops rockchip_sound_rt5514_ops = {
.startup = rockchip_sound_startup,
.hw_params = rockchip_sound_rt5514_hw_params,
};
static const struct snd_soc_ops rockchip_sound_da7219_ops = {
.startup = rockchip_sound_startup,
.hw_params = rockchip_sound_da7219_hw_params,
};
static const struct snd_soc_ops rockchip_sound_dmic_ops = {
.startup = rockchip_sound_startup,
.hw_params = rockchip_sound_dmic_hw_params,
};
static struct snd_soc_card rockchip_sound_card = {
.name = "rk3399-gru-sound",
.owner = THIS_MODULE,
.dapm_widgets = rockchip_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rockchip_dapm_widgets),
.controls = rockchip_controls,
.num_controls = ARRAY_SIZE(rockchip_controls),
};
enum {
DAILINK_CDNDP,
DAILINK_DA7219,
DAILINK_DMIC,
DAILINK_MAX98357A,
DAILINK_RT5514,
DAILINK_RT5514_DSP,
};
SND_SOC_DAILINK_DEFS(cdndp,
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "spdif-hifi")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(da7219,
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "da7219-hifi")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(dmic,
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "dmic-hifi")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(max98357a,
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "HiFi")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(rt5514,
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "rt5514-aif1")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(rt5514_dsp,
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
static const struct snd_soc_dai_link rockchip_dais[] = {
[DAILINK_CDNDP] = {
.name = "DP",
.stream_name = "DP PCM",
.init = rockchip_sound_cdndp_init,
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS,
SND_SOC_DAILINK_REG(cdndp),
},
[DAILINK_DA7219] = {
.name = "DA7219",
.stream_name = "DA7219 PCM",
.init = rockchip_sound_da7219_init,
.ops = &rockchip_sound_da7219_ops,
/* set da7219 as slave */
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS,
SND_SOC_DAILINK_REG(da7219),
},
[DAILINK_DMIC] = {
.name = "DMIC",
.stream_name = "DMIC PCM",
.ops = &rockchip_sound_dmic_ops,
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS,
SND_SOC_DAILINK_REG(dmic),
},
[DAILINK_MAX98357A] = {
.name = "MAX98357A",
.stream_name = "MAX98357A PCM",
.ops = &rockchip_sound_max98357a_ops,
/* set max98357a as slave */
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS,
SND_SOC_DAILINK_REG(max98357a),
},
[DAILINK_RT5514] = {
.name = "RT5514",
.stream_name = "RT5514 PCM",
.ops = &rockchip_sound_rt5514_ops,
/* set rt5514 as slave */
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS,
SND_SOC_DAILINK_REG(rt5514),
},
/* RT5514 DSP for voice wakeup via spi bus */
[DAILINK_RT5514_DSP] = {
.name = "RT5514 DSP",
.stream_name = "Wake on Voice",
SND_SOC_DAILINK_REG(rt5514_dsp),
},
};
static const struct snd_soc_dapm_route rockchip_sound_cdndp_routes[] = {
/* Output */
{"HDMI", NULL, "TX"},
};
static const struct snd_soc_dapm_route rockchip_sound_da7219_routes[] = {
/* Output */
{"Headphones", NULL, "HPL"},
{"Headphones", NULL, "HPR"},
/* Input */
{"MIC", NULL, "Headset Mic"},
};
static const struct snd_soc_dapm_route rockchip_sound_dmic_routes[] = {
/* Input */
{"DMic", NULL, "Int Mic"},
};
static const struct snd_soc_dapm_route rockchip_sound_max98357a_routes[] = {
/* Output */
{"Speakers", NULL, "Speaker"},
};
static const struct snd_soc_dapm_route rockchip_sound_rt5514_routes[] = {
/* Input */
{"DMIC1L", NULL, "Int Mic"},
{"DMIC1R", NULL, "Int Mic"},
};
struct rockchip_sound_route {
const struct snd_soc_dapm_route *routes;
int num_routes;
};
static const struct rockchip_sound_route rockchip_routes[] = {
[DAILINK_CDNDP] = {
.routes = rockchip_sound_cdndp_routes,
.num_routes = ARRAY_SIZE(rockchip_sound_cdndp_routes),
},
[DAILINK_DA7219] = {
.routes = rockchip_sound_da7219_routes,
.num_routes = ARRAY_SIZE(rockchip_sound_da7219_routes),
},
[DAILINK_DMIC] = {
.routes = rockchip_sound_dmic_routes,
.num_routes = ARRAY_SIZE(rockchip_sound_dmic_routes),
},
[DAILINK_MAX98357A] = {
.routes = rockchip_sound_max98357a_routes,
.num_routes = ARRAY_SIZE(rockchip_sound_max98357a_routes),
},
[DAILINK_RT5514] = {
.routes = rockchip_sound_rt5514_routes,
.num_routes = ARRAY_SIZE(rockchip_sound_rt5514_routes),
},
[DAILINK_RT5514_DSP] = {},
};
struct dailink_match_data {
const char *compatible;
struct bus_type *bus_type;
};
static const struct dailink_match_data dailink_match[] = {
[DAILINK_CDNDP] = {
.compatible = "rockchip,rk3399-cdn-dp",
},
[DAILINK_DA7219] = {
.compatible = "dlg,da7219",
},
[DAILINK_DMIC] = {
.compatible = "dmic-codec",
},
[DAILINK_MAX98357A] = {
.compatible = "maxim,max98357a",
},
[DAILINK_RT5514] = {
.compatible = "realtek,rt5514",
.bus_type = &i2c_bus_type,
},
[DAILINK_RT5514_DSP] = {
.compatible = "realtek,rt5514",
.bus_type = &spi_bus_type,
},
};
static int rockchip_sound_codec_node_match(struct device_node *np_codec)
{
struct device *dev;
int i;
for (i = 0; i < ARRAY_SIZE(dailink_match); i++) {
if (!of_device_is_compatible(np_codec,
dailink_match[i].compatible))
continue;
if (dailink_match[i].bus_type) {
dev = bus_find_device_by_of_node(dailink_match[i].bus_type,
np_codec);
if (!dev)
continue;
put_device(dev);
}
return i;
}
return -1;
}
static int rockchip_sound_of_parse_dais(struct device *dev,
struct snd_soc_card *card)
{
struct device_node *np_cpu, *np_cpu0, *np_cpu1;
struct device_node *np_codec;
struct snd_soc_dai_link *dai;
struct snd_soc_dapm_route *routes;
int i, index;
int num_routes;
card->dai_link = devm_kzalloc(dev, sizeof(rockchip_dais),
GFP_KERNEL);
if (!card->dai_link)
return -ENOMEM;
num_routes = 0;
for (i = 0; i < ARRAY_SIZE(rockchip_routes); i++)
num_routes += rockchip_routes[i].num_routes;
routes = devm_kcalloc(dev, num_routes, sizeof(*routes),
GFP_KERNEL);
if (!routes)
return -ENOMEM;
card->dapm_routes = routes;
np_cpu0 = of_parse_phandle(dev->of_node, "rockchip,cpu", 0);
np_cpu1 = of_parse_phandle(dev->of_node, "rockchip,cpu", 1);
card->num_dapm_routes = 0;
card->num_links = 0;
for (i = 0; i < ARRAY_SIZE(rockchip_dais); i++) {
np_codec = of_parse_phandle(dev->of_node,
"rockchip,codec", i);
if (!np_codec)
break;
if (!of_device_is_available(np_codec))
continue;
index = rockchip_sound_codec_node_match(np_codec);
if (index < 0)
continue;
switch (index) {
case DAILINK_CDNDP:
np_cpu = np_cpu1;
break;
case DAILINK_RT5514_DSP:
np_cpu = np_codec;
break;
default:
np_cpu = np_cpu0;
break;
}
if (!np_cpu) {
dev_err(dev, "Missing 'rockchip,cpu' for %s\n",
rockchip_dais[index].name);
return -EINVAL;
}
dai = &card->dai_link[card->num_links++];
*dai = rockchip_dais[index];
if (!dai->codecs->name)
dai->codecs->of_node = np_codec;
dai->platforms->of_node = np_cpu;
dai->cpus->of_node = np_cpu;
if (card->num_dapm_routes + rockchip_routes[index].num_routes >
num_routes) {
dev_err(dev, "Too many routes\n");
return -EINVAL;
}
memcpy(routes + card->num_dapm_routes,
rockchip_routes[index].routes,
rockchip_routes[index].num_routes * sizeof(*routes));
card->num_dapm_routes += rockchip_routes[index].num_routes;
}
return 0;
}
static int rockchip_sound_probe(struct platform_device *pdev)
{
struct snd_soc_card *card = &rockchip_sound_card;
int ret;
ret = rockchip_sound_of_parse_dais(&pdev->dev, card);
if (ret < 0) {
dev_err(&pdev->dev, "Failed to parse dais: %d\n", ret);
return ret;
}
/* Set DMIC wakeup delay */
ret = device_property_read_u32(&pdev->dev, "dmic-wakeup-delay-ms",
&dmic_wakeup_delay);
if (ret) {
dmic_wakeup_delay = 0;
dev_dbg(&pdev->dev,
"no optional property 'dmic-wakeup-delay-ms' found, default: no delay\n");
}
card->dev = &pdev->dev;
return devm_snd_soc_register_card(&pdev->dev, card);
}
static const struct of_device_id rockchip_sound_of_match[] = {
{ .compatible = "rockchip,rk3399-gru-sound", },
{},
};
static struct platform_driver rockchip_sound_driver = {
.probe = rockchip_sound_probe,
.driver = {
.name = DRV_NAME,
.of_match_table = rockchip_sound_of_match,
#ifdef CONFIG_PM
.pm = &snd_soc_pm_ops,
#endif
},
};
module_platform_driver(rockchip_sound_driver);
MODULE_AUTHOR("Xing Zheng <[email protected]>");
MODULE_DESCRIPTION("Rockchip ASoC Machine Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRV_NAME);
MODULE_DEVICE_TABLE(of, rockchip_sound_of_match);
| linux-master | sound/soc/rockchip/rk3399_gru_sound.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Rockchip machine ASoC driver for boards using a RT5645/RT5650 CODEC.
*
* Copyright (c) 2015, ROCKCHIP CORPORATION. All rights reserved.
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/gpio.h>
#include <linux/of_gpio.h>
#include <linux/delay.h>
#include <sound/core.h>
#include <sound/jack.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include "rockchip_i2s.h"
#include "../codecs/rt5645.h"
#define DRV_NAME "rockchip-snd-rt5645"
static struct snd_soc_jack headset_jack;
static struct snd_soc_jack_pin headset_jack_pins[] = {
{
.pin = "Headphones",
.mask = SND_JACK_HEADPHONE,
},
{
.pin = "Headset Mic",
.mask = SND_JACK_MICROPHONE,
},
};
static const struct snd_soc_dapm_widget rk_dapm_widgets[] = {
SND_SOC_DAPM_HP("Headphones", NULL),
SND_SOC_DAPM_SPK("Speakers", NULL),
SND_SOC_DAPM_MIC("Headset Mic", NULL),
SND_SOC_DAPM_MIC("Int Mic", NULL),
};
static const struct snd_soc_dapm_route rk_audio_map[] = {
/* Input Lines */
{"DMIC L2", NULL, "Int Mic"},
{"DMIC R2", NULL, "Int Mic"},
{"RECMIXL", NULL, "Headset Mic"},
{"RECMIXR", NULL, "Headset Mic"},
/* Output Lines */
{"Headphones", NULL, "HPOR"},
{"Headphones", NULL, "HPOL"},
{"Speakers", NULL, "SPOL"},
{"Speakers", NULL, "SPOR"},
};
static const struct snd_kcontrol_new rk_mc_controls[] = {
SOC_DAPM_PIN_SWITCH("Headphones"),
SOC_DAPM_PIN_SWITCH("Speakers"),
SOC_DAPM_PIN_SWITCH("Headset Mic"),
SOC_DAPM_PIN_SWITCH("Int Mic"),
};
static int rk_aif1_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
int ret = 0;
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
int mclk;
switch (params_rate(params)) {
case 8000:
case 16000:
case 24000:
case 32000:
case 48000:
case 64000:
case 96000:
mclk = 12288000;
break;
case 11025:
case 22050:
case 44100:
case 88200:
mclk = 11289600;
break;
default:
return -EINVAL;
}
ret = snd_soc_dai_set_sysclk(cpu_dai, 0, mclk,
SND_SOC_CLOCK_OUT);
if (ret < 0) {
dev_err(codec_dai->dev, "Can't set codec clock %d\n", ret);
return ret;
}
ret = snd_soc_dai_set_sysclk(codec_dai, 0, mclk,
SND_SOC_CLOCK_IN);
if (ret < 0) {
dev_err(codec_dai->dev, "Can't set codec clock %d\n", ret);
return ret;
}
return ret;
}
static int rk_init(struct snd_soc_pcm_runtime *runtime)
{
struct snd_soc_card *card = runtime->card;
int ret;
/* Enable Headset and 4 Buttons Jack detection */
ret = snd_soc_card_jack_new_pins(card, "Headset Jack",
SND_JACK_HEADPHONE | SND_JACK_MICROPHONE |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3,
&headset_jack,
headset_jack_pins,
ARRAY_SIZE(headset_jack_pins));
if (ret) {
dev_err(card->dev, "New Headset Jack failed! (%d)\n", ret);
return ret;
}
return rt5645_set_jack_detect(asoc_rtd_to_codec(runtime, 0)->component,
&headset_jack,
&headset_jack,
&headset_jack);
}
static const struct snd_soc_ops rk_aif1_ops = {
.hw_params = rk_aif1_hw_params,
};
SND_SOC_DAILINK_DEFS(pcm,
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "rt5645-aif1")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
static struct snd_soc_dai_link rk_dailink = {
.name = "rt5645",
.stream_name = "rt5645 PCM",
.init = rk_init,
.ops = &rk_aif1_ops,
/* set rt5645 as slave */
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS,
SND_SOC_DAILINK_REG(pcm),
};
static struct snd_soc_card snd_soc_card_rk = {
.name = "I2S-RT5650",
.owner = THIS_MODULE,
.dai_link = &rk_dailink,
.num_links = 1,
.dapm_widgets = rk_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rk_dapm_widgets),
.dapm_routes = rk_audio_map,
.num_dapm_routes = ARRAY_SIZE(rk_audio_map),
.controls = rk_mc_controls,
.num_controls = ARRAY_SIZE(rk_mc_controls),
};
static int snd_rk_mc_probe(struct platform_device *pdev)
{
int ret = 0;
struct snd_soc_card *card = &snd_soc_card_rk;
struct device_node *np = pdev->dev.of_node;
/* register the soc card */
card->dev = &pdev->dev;
rk_dailink.codecs->of_node = of_parse_phandle(np,
"rockchip,audio-codec", 0);
if (!rk_dailink.codecs->of_node) {
dev_err(&pdev->dev,
"Property 'rockchip,audio-codec' missing or invalid\n");
return -EINVAL;
}
rk_dailink.cpus->of_node = of_parse_phandle(np,
"rockchip,i2s-controller", 0);
if (!rk_dailink.cpus->of_node) {
dev_err(&pdev->dev,
"Property 'rockchip,i2s-controller' missing or invalid\n");
ret = -EINVAL;
goto put_codec_of_node;
}
rk_dailink.platforms->of_node = rk_dailink.cpus->of_node;
ret = snd_soc_of_parse_card_name(card, "rockchip,model");
if (ret) {
dev_err(&pdev->dev,
"Soc parse card name failed %d\n", ret);
goto put_cpu_of_node;
}
ret = devm_snd_soc_register_card(&pdev->dev, card);
if (ret) {
dev_err(&pdev->dev,
"Soc register card failed %d\n", ret);
goto put_cpu_of_node;
}
return ret;
put_cpu_of_node:
of_node_put(rk_dailink.cpus->of_node);
rk_dailink.cpus->of_node = NULL;
put_codec_of_node:
of_node_put(rk_dailink.codecs->of_node);
rk_dailink.codecs->of_node = NULL;
return ret;
}
static void snd_rk_mc_remove(struct platform_device *pdev)
{
of_node_put(rk_dailink.cpus->of_node);
rk_dailink.cpus->of_node = NULL;
of_node_put(rk_dailink.codecs->of_node);
rk_dailink.codecs->of_node = NULL;
}
static const struct of_device_id rockchip_rt5645_of_match[] = {
{ .compatible = "rockchip,rockchip-audio-rt5645", },
{},
};
MODULE_DEVICE_TABLE(of, rockchip_rt5645_of_match);
static struct platform_driver snd_rk_mc_driver = {
.probe = snd_rk_mc_probe,
.remove_new = snd_rk_mc_remove,
.driver = {
.name = DRV_NAME,
.pm = &snd_soc_pm_ops,
.of_match_table = rockchip_rt5645_of_match,
},
};
module_platform_driver(snd_rk_mc_driver);
MODULE_AUTHOR("Xing Zheng <[email protected]>");
MODULE_DESCRIPTION("Rockchip rt5645 machine ASoC driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRV_NAME);
| linux-master | sound/soc/rockchip/rockchip_rt5645.c |
// SPDX-License-Identifier: GPL-2.0
/*
* jh7110_tdm.c -- StarFive JH7110 TDM driver
*
* Copyright (C) 2023 StarFive Technology Co., Ltd.
*
* Author: Walker Chen <[email protected]>
*/
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/dmaengine.h>
#include <linux/module.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/types.h>
#include <sound/dmaengine_pcm.h>
#include <sound/initval.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#define TDM_PCMGBCR 0x00
#define PCMGBCR_ENABLE BIT(0)
#define CLKPOL_BIT 5
#define ELM_BIT 3
#define SYNCM_BIT 2
#define MS_BIT 1
#define TDM_PCMTXCR 0x04
#define PCMTXCR_TXEN BIT(0)
#define IFL_BIT 11
#define WL_BIT 8
#define SSCALE_BIT 4
#define SL_BIT 2
#define LRJ_BIT 1
#define TDM_PCMRXCR 0x08
#define PCMRXCR_RXEN BIT(0)
#define TDM_PCMDIV 0x0c
#define JH7110_TDM_FIFO 0x170c0000
#define JH7110_TDM_FIFO_DEPTH 32
enum TDM_MASTER_SLAVE_MODE {
TDM_AS_MASTER = 0,
TDM_AS_SLAVE,
};
enum TDM_CLKPOL {
/* tx raising and rx falling */
TDM_TX_RASING_RX_FALLING = 0,
/* tx falling and rx raising */
TDM_TX_FALLING_RX_RASING,
};
enum TDM_ELM {
/* only work while SYNCM=0 */
TDM_ELM_LATE = 0,
TDM_ELM_EARLY,
};
enum TDM_SYNCM {
/* short frame sync */
TDM_SYNCM_SHORT = 0,
/* long frame sync */
TDM_SYNCM_LONG,
};
enum TDM_IFL {
/* FIFO to send or received : half-1/2, Quarter-1/4 */
TDM_FIFO_HALF = 0,
TDM_FIFO_QUARTER,
};
enum TDM_WL {
/* send or received word length */
TDM_8BIT_WORD_LEN = 0,
TDM_16BIT_WORD_LEN,
TDM_20BIT_WORD_LEN,
TDM_24BIT_WORD_LEN,
TDM_32BIT_WORD_LEN,
};
enum TDM_SL {
/* send or received slot length */
TDM_8BIT_SLOT_LEN = 0,
TDM_16BIT_SLOT_LEN,
TDM_32BIT_SLOT_LEN,
};
enum TDM_LRJ {
/* left-justify or right-justify */
TDM_RIGHT_JUSTIFY = 0,
TDM_LEFT_JUSTIFT,
};
struct tdm_chan_cfg {
enum TDM_IFL ifl;
enum TDM_WL wl;
unsigned char sscale;
enum TDM_SL sl;
enum TDM_LRJ lrj;
unsigned char enable;
};
struct jh7110_tdm_dev {
void __iomem *tdm_base;
struct device *dev;
struct clk_bulk_data clks[6];
struct reset_control *resets;
enum TDM_CLKPOL clkpolity;
enum TDM_ELM elm;
enum TDM_SYNCM syncm;
enum TDM_MASTER_SLAVE_MODE ms_mode;
struct tdm_chan_cfg tx;
struct tdm_chan_cfg rx;
u16 syncdiv;
u32 samplerate;
u32 pcmclk;
/* data related to DMA transfers b/w tdm and DMAC */
struct snd_dmaengine_dai_dma_data play_dma_data;
struct snd_dmaengine_dai_dma_data capture_dma_data;
u32 saved_pcmgbcr;
u32 saved_pcmtxcr;
u32 saved_pcmrxcr;
u32 saved_pcmdiv;
};
static inline u32 jh7110_tdm_readl(struct jh7110_tdm_dev *tdm, u16 reg)
{
return readl_relaxed(tdm->tdm_base + reg);
}
static inline void jh7110_tdm_writel(struct jh7110_tdm_dev *tdm, u16 reg, u32 val)
{
writel_relaxed(val, tdm->tdm_base + reg);
}
static void jh7110_tdm_save_context(struct jh7110_tdm_dev *tdm,
struct snd_pcm_substream *substream)
{
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
tdm->saved_pcmtxcr = jh7110_tdm_readl(tdm, TDM_PCMTXCR);
else
tdm->saved_pcmrxcr = jh7110_tdm_readl(tdm, TDM_PCMRXCR);
}
static void jh7110_tdm_start(struct jh7110_tdm_dev *tdm,
struct snd_pcm_substream *substream)
{
u32 data;
data = jh7110_tdm_readl(tdm, TDM_PCMGBCR);
jh7110_tdm_writel(tdm, TDM_PCMGBCR, data | PCMGBCR_ENABLE);
/* restore context */
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
jh7110_tdm_writel(tdm, TDM_PCMTXCR, tdm->saved_pcmtxcr | PCMTXCR_TXEN);
else
jh7110_tdm_writel(tdm, TDM_PCMRXCR, tdm->saved_pcmrxcr | PCMRXCR_RXEN);
}
static void jh7110_tdm_stop(struct jh7110_tdm_dev *tdm,
struct snd_pcm_substream *substream)
{
unsigned int val;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
val = jh7110_tdm_readl(tdm, TDM_PCMTXCR);
val &= ~PCMTXCR_TXEN;
jh7110_tdm_writel(tdm, TDM_PCMTXCR, val);
} else {
val = jh7110_tdm_readl(tdm, TDM_PCMRXCR);
val &= ~PCMRXCR_RXEN;
jh7110_tdm_writel(tdm, TDM_PCMRXCR, val);
}
}
static int jh7110_tdm_syncdiv(struct jh7110_tdm_dev *tdm)
{
u32 sl, sscale, syncdiv;
if (tdm->rx.sl >= tdm->tx.sl)
sl = tdm->rx.sl;
else
sl = tdm->tx.sl;
if (tdm->rx.sscale >= tdm->tx.sscale)
sscale = tdm->rx.sscale;
else
sscale = tdm->tx.sscale;
syncdiv = tdm->pcmclk / tdm->samplerate - 1;
if ((syncdiv + 1) < (sl * sscale)) {
dev_err(tdm->dev, "Failed to set syncdiv!\n");
return -EINVAL;
}
if (tdm->syncm == TDM_SYNCM_LONG &&
(tdm->rx.sscale <= 1 || tdm->tx.sscale <= 1) &&
((syncdiv + 1) <= sl)) {
dev_err(tdm->dev, "Wrong syncdiv! It must be (syncdiv+1) > max[tx.sl, rx.sl]\n");
return -EINVAL;
}
jh7110_tdm_writel(tdm, TDM_PCMDIV, syncdiv);
return 0;
}
static int jh7110_tdm_config(struct jh7110_tdm_dev *tdm,
struct snd_pcm_substream *substream)
{
u32 datarx, datatx;
int ret;
ret = jh7110_tdm_syncdiv(tdm);
if (ret)
return ret;
datarx = (tdm->rx.ifl << IFL_BIT) |
(tdm->rx.wl << WL_BIT) |
(tdm->rx.sscale << SSCALE_BIT) |
(tdm->rx.sl << SL_BIT) |
(tdm->rx.lrj << LRJ_BIT);
datatx = (tdm->tx.ifl << IFL_BIT) |
(tdm->tx.wl << WL_BIT) |
(tdm->tx.sscale << SSCALE_BIT) |
(tdm->tx.sl << SL_BIT) |
(tdm->tx.lrj << LRJ_BIT);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
jh7110_tdm_writel(tdm, TDM_PCMTXCR, datatx);
else
jh7110_tdm_writel(tdm, TDM_PCMRXCR, datarx);
return 0;
}
static void jh7110_tdm_clk_disable(struct jh7110_tdm_dev *tdm)
{
clk_bulk_disable_unprepare(ARRAY_SIZE(tdm->clks), tdm->clks);
}
static int jh7110_tdm_clk_enable(struct jh7110_tdm_dev *tdm)
{
int ret;
ret = clk_bulk_prepare_enable(ARRAY_SIZE(tdm->clks), tdm->clks);
if (ret) {
dev_err(tdm->dev, "Failed to enable tdm clocks\n");
return ret;
}
ret = reset_control_deassert(tdm->resets);
if (ret) {
dev_err(tdm->dev, "Failed to deassert tdm resets\n");
goto dis_tdm_clk;
}
/* select tdm_ext clock as the clock source for tdm */
ret = clk_set_parent(tdm->clks[5].clk, tdm->clks[4].clk);
if (ret) {
dev_err(tdm->dev, "Can't set extern clock source for clk_tdm\n");
goto dis_tdm_clk;
}
return 0;
dis_tdm_clk:
clk_bulk_disable_unprepare(ARRAY_SIZE(tdm->clks), tdm->clks);
return ret;
}
static int jh7110_tdm_runtime_suspend(struct device *dev)
{
struct jh7110_tdm_dev *tdm = dev_get_drvdata(dev);
jh7110_tdm_clk_disable(tdm);
return 0;
}
static int jh7110_tdm_runtime_resume(struct device *dev)
{
struct jh7110_tdm_dev *tdm = dev_get_drvdata(dev);
return jh7110_tdm_clk_enable(tdm);
}
static int jh7110_tdm_system_suspend(struct device *dev)
{
struct jh7110_tdm_dev *tdm = dev_get_drvdata(dev);
/* save context */
tdm->saved_pcmgbcr = jh7110_tdm_readl(tdm, TDM_PCMGBCR);
tdm->saved_pcmdiv = jh7110_tdm_readl(tdm, TDM_PCMDIV);
return pm_runtime_force_suspend(dev);
}
static int jh7110_tdm_system_resume(struct device *dev)
{
struct jh7110_tdm_dev *tdm = dev_get_drvdata(dev);
/* restore context */
jh7110_tdm_writel(tdm, TDM_PCMGBCR, tdm->saved_pcmgbcr);
jh7110_tdm_writel(tdm, TDM_PCMDIV, tdm->saved_pcmdiv);
return pm_runtime_force_resume(dev);
}
static const struct snd_soc_component_driver jh7110_tdm_component = {
.name = "jh7110-tdm",
};
static int jh7110_tdm_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *cpu_dai)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai_link *dai_link = rtd->dai_link;
dai_link->trigger_stop = SND_SOC_TRIGGER_ORDER_LDC;
return 0;
}
static int jh7110_tdm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct jh7110_tdm_dev *tdm = snd_soc_dai_get_drvdata(dai);
int chan_wl, chan_sl, chan_nr;
unsigned int data_width;
unsigned int dma_bus_width;
struct snd_dmaengine_dai_dma_data *dma_data = NULL;
int ret;
data_width = params_width(params);
tdm->samplerate = params_rate(params);
tdm->pcmclk = params_channels(params) * tdm->samplerate * data_width;
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
chan_wl = TDM_16BIT_WORD_LEN;
chan_sl = TDM_16BIT_SLOT_LEN;
dma_bus_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
break;
case SNDRV_PCM_FORMAT_S32_LE:
chan_wl = TDM_32BIT_WORD_LEN;
chan_sl = TDM_32BIT_SLOT_LEN;
dma_bus_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
break;
default:
dev_err(tdm->dev, "tdm: unsupported PCM fmt");
return -EINVAL;
}
chan_nr = params_channels(params);
switch (chan_nr) {
case 1:
case 2:
case 4:
case 6:
case 8:
break;
default:
dev_err(tdm->dev, "channel not supported\n");
return -EINVAL;
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
tdm->tx.wl = chan_wl;
tdm->tx.sl = chan_sl;
tdm->tx.sscale = chan_nr;
tdm->play_dma_data.addr_width = dma_bus_width;
dma_data = &tdm->play_dma_data;
} else {
tdm->rx.wl = chan_wl;
tdm->rx.sl = chan_sl;
tdm->rx.sscale = chan_nr;
tdm->capture_dma_data.addr_width = dma_bus_width;
dma_data = &tdm->capture_dma_data;
}
snd_soc_dai_set_dma_data(dai, substream, dma_data);
ret = jh7110_tdm_config(tdm, substream);
if (ret)
return ret;
jh7110_tdm_save_context(tdm, substream);
return 0;
}
static int jh7110_tdm_trigger(struct snd_pcm_substream *substream,
int cmd, struct snd_soc_dai *dai)
{
struct jh7110_tdm_dev *tdm = snd_soc_dai_get_drvdata(dai);
int ret = 0;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
jh7110_tdm_start(tdm, substream);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
jh7110_tdm_stop(tdm, substream);
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
static int jh7110_tdm_set_dai_fmt(struct snd_soc_dai *cpu_dai,
unsigned int fmt)
{
struct jh7110_tdm_dev *tdm = snd_soc_dai_get_drvdata(cpu_dai);
unsigned int gbcr;
/* set master/slave audio interface */
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BP_FP:
/* cpu is master */
tdm->ms_mode = TDM_AS_MASTER;
break;
case SND_SOC_DAIFMT_BC_FC:
/* codec is master */
tdm->ms_mode = TDM_AS_SLAVE;
break;
case SND_SOC_DAIFMT_BC_FP:
case SND_SOC_DAIFMT_BP_FC:
return -EINVAL;
default:
dev_dbg(tdm->dev, "dwc : Invalid clock provider format\n");
return -EINVAL;
}
gbcr = (tdm->clkpolity << CLKPOL_BIT) |
(tdm->elm << ELM_BIT) |
(tdm->syncm << SYNCM_BIT) |
(tdm->ms_mode << MS_BIT);
jh7110_tdm_writel(tdm, TDM_PCMGBCR, gbcr);
return 0;
}
static int jh7110_tdm_dai_probe(struct snd_soc_dai *dai)
{
struct jh7110_tdm_dev *tdm = snd_soc_dai_get_drvdata(dai);
snd_soc_dai_init_dma_data(dai, &tdm->play_dma_data, &tdm->capture_dma_data);
snd_soc_dai_set_drvdata(dai, tdm);
return 0;
}
static const struct snd_soc_dai_ops jh7110_tdm_dai_ops = {
.probe = jh7110_tdm_dai_probe,
.startup = jh7110_tdm_startup,
.hw_params = jh7110_tdm_hw_params,
.trigger = jh7110_tdm_trigger,
.set_fmt = jh7110_tdm_set_dai_fmt,
};
#define JH7110_TDM_RATES SNDRV_PCM_RATE_8000_48000
#define JH7110_TDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver jh7110_tdm_dai = {
.name = "sf_tdm",
.id = 0,
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 8,
.rates = JH7110_TDM_RATES,
.formats = JH7110_TDM_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 8,
.rates = JH7110_TDM_RATES,
.formats = JH7110_TDM_FORMATS,
},
.ops = &jh7110_tdm_dai_ops,
.symmetric_rate = 1,
};
static const struct snd_pcm_hardware jh7110_pcm_hardware = {
.info = (SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_PAUSE |
SNDRV_PCM_INFO_RESUME |
SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_BLOCK_TRANSFER),
.buffer_bytes_max = 192512,
.period_bytes_min = 4096,
.period_bytes_max = 32768,
.periods_min = 1,
.periods_max = 48,
.fifo_size = 16,
};
static const struct snd_dmaengine_pcm_config jh7110_dmaengine_pcm_config = {
.pcm_hardware = &jh7110_pcm_hardware,
.prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
.prealloc_buffer_size = 192512,
};
static void jh7110_tdm_init_params(struct jh7110_tdm_dev *tdm)
{
tdm->clkpolity = TDM_TX_RASING_RX_FALLING;
tdm->elm = TDM_ELM_LATE;
tdm->syncm = TDM_SYNCM_SHORT;
tdm->rx.ifl = TDM_FIFO_HALF;
tdm->tx.ifl = TDM_FIFO_HALF;
tdm->rx.wl = TDM_16BIT_WORD_LEN;
tdm->tx.wl = TDM_16BIT_WORD_LEN;
tdm->rx.sscale = 2;
tdm->tx.sscale = 2;
tdm->rx.lrj = TDM_LEFT_JUSTIFT;
tdm->tx.lrj = TDM_LEFT_JUSTIFT;
tdm->play_dma_data.addr = JH7110_TDM_FIFO;
tdm->play_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
tdm->play_dma_data.fifo_size = JH7110_TDM_FIFO_DEPTH / 2;
tdm->play_dma_data.maxburst = 16;
tdm->capture_dma_data.addr = JH7110_TDM_FIFO;
tdm->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
tdm->capture_dma_data.fifo_size = JH7110_TDM_FIFO_DEPTH / 2;
tdm->capture_dma_data.maxburst = 8;
}
static int jh7110_tdm_clk_reset_get(struct platform_device *pdev,
struct jh7110_tdm_dev *tdm)
{
int ret;
tdm->clks[0].id = "mclk_inner";
tdm->clks[1].id = "tdm_ahb";
tdm->clks[2].id = "tdm_apb";
tdm->clks[3].id = "tdm_internal";
tdm->clks[4].id = "tdm_ext";
tdm->clks[5].id = "tdm";
ret = devm_clk_bulk_get(&pdev->dev, ARRAY_SIZE(tdm->clks), tdm->clks);
if (ret) {
dev_err(&pdev->dev, "Failed to get tdm clocks\n");
return ret;
}
tdm->resets = devm_reset_control_array_get_exclusive(&pdev->dev);
if (IS_ERR(tdm->resets)) {
dev_err(&pdev->dev, "Failed to get tdm resets\n");
return PTR_ERR(tdm->resets);
}
return 0;
}
static int jh7110_tdm_probe(struct platform_device *pdev)
{
struct jh7110_tdm_dev *tdm;
int ret;
tdm = devm_kzalloc(&pdev->dev, sizeof(*tdm), GFP_KERNEL);
if (!tdm)
return -ENOMEM;
tdm->tdm_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(tdm->tdm_base))
return PTR_ERR(tdm->tdm_base);
tdm->dev = &pdev->dev;
ret = jh7110_tdm_clk_reset_get(pdev, tdm);
if (ret) {
dev_err(&pdev->dev, "Failed to enable audio-tdm clock\n");
return ret;
}
jh7110_tdm_init_params(tdm);
dev_set_drvdata(&pdev->dev, tdm);
ret = devm_snd_soc_register_component(&pdev->dev, &jh7110_tdm_component,
&jh7110_tdm_dai, 1);
if (ret) {
dev_err(&pdev->dev, "Failed to register dai\n");
return ret;
}
ret = devm_snd_dmaengine_pcm_register(&pdev->dev,
&jh7110_dmaengine_pcm_config,
SND_DMAENGINE_PCM_FLAG_COMPAT);
if (ret) {
dev_err(&pdev->dev, "Could not register pcm: %d\n", ret);
return ret;
}
pm_runtime_enable(&pdev->dev);
if (!pm_runtime_enabled(&pdev->dev)) {
ret = jh7110_tdm_runtime_resume(&pdev->dev);
if (ret)
goto err_pm_disable;
}
return 0;
err_pm_disable:
pm_runtime_disable(&pdev->dev);
return ret;
}
static void jh7110_tdm_dev_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
}
static const struct of_device_id jh7110_tdm_of_match[] = {
{ .compatible = "starfive,jh7110-tdm", },
{}
};
MODULE_DEVICE_TABLE(of, jh7110_tdm_of_match);
static const struct dev_pm_ops jh7110_tdm_pm_ops = {
RUNTIME_PM_OPS(jh7110_tdm_runtime_suspend,
jh7110_tdm_runtime_resume, NULL)
SYSTEM_SLEEP_PM_OPS(jh7110_tdm_system_suspend,
jh7110_tdm_system_resume)
};
static struct platform_driver jh7110_tdm_driver = {
.driver = {
.name = "jh7110-tdm",
.of_match_table = jh7110_tdm_of_match,
.pm = pm_ptr(&jh7110_tdm_pm_ops),
},
.probe = jh7110_tdm_probe,
.remove_new = jh7110_tdm_dev_remove,
};
module_platform_driver(jh7110_tdm_driver);
MODULE_DESCRIPTION("StarFive JH7110 TDM ASoC Driver");
MODULE_AUTHOR("Walker Chen <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/starfive/jh7110_tdm.c |
// SPDX-License-Identifier: GPL-2.0
//
// Common functions for loongson I2S controller driver
//
// Copyright (C) 2023 Loongson Technology Corporation Limited.
// Author: Yingkun Meng <[email protected]>
//
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/pm_runtime.h>
#include <linux/dma-mapping.h>
#include <sound/soc.h>
#include <linux/regmap.h>
#include <sound/pcm_params.h>
#include "loongson_i2s.h"
#define LOONGSON_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE)
static int loongson_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct loongson_i2s *i2s = snd_soc_dai_get_drvdata(dai);
int ret = 0;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
regmap_update_bits(i2s->regmap, LS_I2S_CTRL,
I2S_CTRL_TX_EN | I2S_CTRL_TX_DMA_EN,
I2S_CTRL_TX_EN | I2S_CTRL_TX_DMA_EN);
else
regmap_update_bits(i2s->regmap, LS_I2S_CTRL,
I2S_CTRL_RX_EN | I2S_CTRL_RX_DMA_EN,
I2S_CTRL_RX_EN | I2S_CTRL_RX_DMA_EN);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
regmap_update_bits(i2s->regmap, LS_I2S_CTRL,
I2S_CTRL_TX_EN | I2S_CTRL_TX_DMA_EN, 0);
else
regmap_update_bits(i2s->regmap, LS_I2S_CTRL,
I2S_CTRL_RX_EN | I2S_CTRL_RX_DMA_EN, 0);
break;
default:
ret = -EINVAL;
}
return ret;
}
static int loongson_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct loongson_i2s *i2s = snd_soc_dai_get_drvdata(dai);
u32 clk_rate = i2s->clk_rate;
u32 sysclk = i2s->sysclk;
u32 bits = params_width(params);
u32 chans = params_channels(params);
u32 fs = params_rate(params);
u32 bclk_ratio, mclk_ratio;
u32 mclk_ratio_frac;
u32 val = 0;
switch (i2s->rev_id) {
case 0:
bclk_ratio = DIV_ROUND_CLOSEST(clk_rate,
(bits * chans * fs * 2)) - 1;
mclk_ratio = DIV_ROUND_CLOSEST(clk_rate, (sysclk * 2)) - 1;
/* According to 2k1000LA user manual, set bits == depth */
val |= (bits << 24);
val |= (bits << 16);
val |= (bclk_ratio << 8);
val |= mclk_ratio;
regmap_write(i2s->regmap, LS_I2S_CFG, val);
break;
case 1:
bclk_ratio = DIV_ROUND_CLOSEST(sysclk,
(bits * chans * fs * 2)) - 1;
mclk_ratio = clk_rate / sysclk;
mclk_ratio_frac = DIV_ROUND_CLOSEST_ULL(((u64)clk_rate << 16),
sysclk) - (mclk_ratio << 16);
regmap_read(i2s->regmap, LS_I2S_CFG, &val);
val |= (bits << 24);
val |= (bclk_ratio << 8);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
val |= (bits << 16);
else
val |= bits;
regmap_write(i2s->regmap, LS_I2S_CFG, val);
val = (mclk_ratio_frac << 16) | mclk_ratio;
regmap_write(i2s->regmap, LS_I2S_CFG1, val);
break;
default:
dev_err(i2s->dev, "I2S revision invalid\n");
return -EINVAL;
}
return 0;
}
static int loongson_i2s_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
unsigned int freq, int dir)
{
struct loongson_i2s *i2s = snd_soc_dai_get_drvdata(dai);
i2s->sysclk = freq;
return 0;
}
static int loongson_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct loongson_i2s *i2s = snd_soc_dai_get_drvdata(dai);
u32 val;
int ret;
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
break;
case SND_SOC_DAIFMT_RIGHT_J:
regmap_update_bits(i2s->regmap, LS_I2S_CTRL, I2S_CTRL_MSB,
I2S_CTRL_MSB);
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BC_FC:
break;
case SND_SOC_DAIFMT_BP_FC:
/* Enable master mode */
regmap_update_bits(i2s->regmap, LS_I2S_CTRL, I2S_CTRL_MASTER,
I2S_CTRL_MASTER);
if (i2s->rev_id == 1) {
ret = regmap_read_poll_timeout_atomic(i2s->regmap,
LS_I2S_CTRL, val,
val & I2S_CTRL_CLK_READY,
10, 500000);
if (ret < 0)
dev_warn(dai->dev, "wait BCLK ready timeout\n");
}
break;
case SND_SOC_DAIFMT_BC_FP:
/* Enable MCLK */
if (i2s->rev_id == 1) {
regmap_update_bits(i2s->regmap, LS_I2S_CTRL,
I2S_CTRL_MCLK_EN,
I2S_CTRL_MCLK_EN);
ret = regmap_read_poll_timeout_atomic(i2s->regmap,
LS_I2S_CTRL, val,
val & I2S_CTRL_MCLK_READY,
10, 500000);
if (ret < 0)
dev_warn(dai->dev, "wait MCLK ready timeout\n");
}
break;
case SND_SOC_DAIFMT_BP_FP:
/* Enable MCLK */
if (i2s->rev_id == 1) {
regmap_update_bits(i2s->regmap, LS_I2S_CTRL,
I2S_CTRL_MCLK_EN,
I2S_CTRL_MCLK_EN);
ret = regmap_read_poll_timeout_atomic(i2s->regmap,
LS_I2S_CTRL, val,
val & I2S_CTRL_MCLK_READY,
10, 500000);
if (ret < 0)
dev_warn(dai->dev, "wait MCLK ready timeout\n");
}
/* Enable master mode */
regmap_update_bits(i2s->regmap, LS_I2S_CTRL, I2S_CTRL_MASTER,
I2S_CTRL_MASTER);
if (i2s->rev_id == 1) {
ret = regmap_read_poll_timeout_atomic(i2s->regmap,
LS_I2S_CTRL, val,
val & I2S_CTRL_CLK_READY,
10, 500000);
if (ret < 0)
dev_warn(dai->dev, "wait BCLK ready timeout\n");
}
break;
default:
return -EINVAL;
}
return 0;
}
static int loongson_i2s_dai_probe(struct snd_soc_dai *cpu_dai)
{
struct loongson_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
snd_soc_dai_init_dma_data(cpu_dai, &i2s->playback_dma_data,
&i2s->capture_dma_data);
snd_soc_dai_set_drvdata(cpu_dai, i2s);
return 0;
}
static const struct snd_soc_dai_ops loongson_i2s_dai_ops = {
.probe = loongson_i2s_dai_probe,
.trigger = loongson_i2s_trigger,
.hw_params = loongson_i2s_hw_params,
.set_sysclk = loongson_i2s_set_dai_sysclk,
.set_fmt = loongson_i2s_set_fmt,
};
struct snd_soc_dai_driver loongson_i2s_dai = {
.name = "loongson-i2s",
.playback = {
.stream_name = "CPU-Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = LOONGSON_I2S_FORMATS,
},
.capture = {
.stream_name = "CPU-Capture",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = LOONGSON_I2S_FORMATS,
},
.ops = &loongson_i2s_dai_ops,
.symmetric_rate = 1,
};
static int i2s_suspend(struct device *dev)
{
struct loongson_i2s *i2s = dev_get_drvdata(dev);
regcache_cache_only(i2s->regmap, true);
return 0;
}
static int i2s_resume(struct device *dev)
{
struct loongson_i2s *i2s = dev_get_drvdata(dev);
int ret;
regcache_cache_only(i2s->regmap, false);
regcache_mark_dirty(i2s->regmap);
ret = regcache_sync(i2s->regmap);
return ret;
}
const struct dev_pm_ops loongson_i2s_pm = {
SYSTEM_SLEEP_PM_OPS(i2s_suspend, i2s_resume)
};
| linux-master | sound/soc/loongson/loongson_i2s.c |
// SPDX-License-Identifier: GPL-2.0
//
// loongson_i2s_pci.c -- Loongson I2S controller driver
//
// Copyright (C) 2023 Loongson Technology Corporation Limited
// Author: Yingkun Meng <[email protected]>
//
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/pm_runtime.h>
#include <linux/dma-mapping.h>
#include <linux/acpi.h>
#include <linux/pci.h>
#include <sound/soc.h>
#include "loongson_i2s.h"
#include "loongson_dma.h"
static bool loongson_i2s_wr_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case LS_I2S_CFG:
case LS_I2S_CTRL:
case LS_I2S_RX_DATA:
case LS_I2S_TX_DATA:
case LS_I2S_CFG1:
return true;
default:
return false;
};
}
static bool loongson_i2s_rd_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case LS_I2S_VER:
case LS_I2S_CFG:
case LS_I2S_CTRL:
case LS_I2S_RX_DATA:
case LS_I2S_TX_DATA:
case LS_I2S_CFG1:
return true;
default:
return false;
};
}
static bool loongson_i2s_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case LS_I2S_CFG:
case LS_I2S_CTRL:
case LS_I2S_RX_DATA:
case LS_I2S_TX_DATA:
case LS_I2S_CFG1:
return true;
default:
return false;
};
}
static const struct regmap_config loongson_i2s_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = LS_I2S_CFG1,
.writeable_reg = loongson_i2s_wr_reg,
.readable_reg = loongson_i2s_rd_reg,
.volatile_reg = loongson_i2s_volatile_reg,
.cache_type = REGCACHE_FLAT,
};
static int loongson_i2s_pci_probe(struct pci_dev *pdev,
const struct pci_device_id *pid)
{
const struct fwnode_handle *fwnode = pdev->dev.fwnode;
struct loongson_dma_data *tx_data, *rx_data;
struct loongson_i2s *i2s;
int ret;
if (pcim_enable_device(pdev)) {
dev_err(&pdev->dev, "pci_enable_device failed\n");
return -ENODEV;
}
i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
if (!i2s)
return -ENOMEM;
i2s->rev_id = pdev->revision;
i2s->dev = &pdev->dev;
pci_set_drvdata(pdev, i2s);
ret = pcim_iomap_regions(pdev, 1 << 0, dev_name(&pdev->dev));
if (ret < 0) {
dev_err(&pdev->dev, "iomap_regions failed\n");
return ret;
}
i2s->reg_base = pcim_iomap_table(pdev)[0];
i2s->regmap = devm_regmap_init_mmio(&pdev->dev, i2s->reg_base,
&loongson_i2s_regmap_config);
if (IS_ERR(i2s->regmap)) {
dev_err(&pdev->dev, "regmap_init_mmio failed\n");
return PTR_ERR(i2s->regmap);
}
tx_data = &i2s->tx_dma_data;
rx_data = &i2s->rx_dma_data;
tx_data->dev_addr = pci_resource_start(pdev, 0) + LS_I2S_TX_DATA;
tx_data->order_addr = i2s->reg_base + LS_I2S_TX_ORDER;
rx_data->dev_addr = pci_resource_start(pdev, 0) + LS_I2S_RX_DATA;
rx_data->order_addr = i2s->reg_base + LS_I2S_RX_ORDER;
tx_data->irq = fwnode_irq_get_byname(fwnode, "tx");
if (tx_data->irq < 0) {
dev_err(&pdev->dev, "dma tx irq invalid\n");
return tx_data->irq;
}
rx_data->irq = fwnode_irq_get_byname(fwnode, "rx");
if (rx_data->irq < 0) {
dev_err(&pdev->dev, "dma rx irq invalid\n");
return rx_data->irq;
}
device_property_read_u32(&pdev->dev, "clock-frequency", &i2s->clk_rate);
if (!i2s->clk_rate) {
dev_err(&pdev->dev, "clock-frequency property invalid\n");
return -EINVAL;
}
dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
if (i2s->rev_id == 1) {
regmap_write(i2s->regmap, LS_I2S_CTRL, I2S_CTRL_RESET);
udelay(200);
}
ret = devm_snd_soc_register_component(&pdev->dev,
&loongson_i2s_component,
&loongson_i2s_dai, 1);
if (ret) {
dev_err(&pdev->dev, "register DAI failed %d\n", ret);
return ret;
}
return 0;
}
static const struct pci_device_id loongson_i2s_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_LOONGSON, 0x7a27) },
{ },
};
MODULE_DEVICE_TABLE(pci, loongson_i2s_ids);
static struct pci_driver loongson_i2s_driver = {
.name = "loongson-i2s-pci",
.id_table = loongson_i2s_ids,
.probe = loongson_i2s_pci_probe,
.driver = {
.owner = THIS_MODULE,
.pm = pm_sleep_ptr(&loongson_i2s_pm),
},
};
module_pci_driver(loongson_i2s_driver);
MODULE_DESCRIPTION("Loongson I2S Master Mode ASoC Driver");
MODULE_AUTHOR("Loongson Technology Corporation Limited");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/loongson/loongson_i2s_pci.c |
// SPDX-License-Identifier: GPL-2.0
//
// Loongson ALSA SoC Platform (DMA) driver
//
// Copyright (C) 2023 Loongson Technology Corporation Limited
// Author: Yingkun Meng <[email protected]>
//
#include <linux/module.h>
#include <linux/io-64-nonatomic-lo-hi.h>
#include <linux/delay.h>
#include <linux/pm_runtime.h>
#include <linux/dma-mapping.h>
#include <sound/soc.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include "loongson_i2s.h"
/* DMA dma_order Register */
#define DMA_ORDER_STOP (1 << 4) /* DMA stop */
#define DMA_ORDER_START (1 << 3) /* DMA start */
#define DMA_ORDER_ASK_VALID (1 << 2) /* DMA ask valid flag */
#define DMA_ORDER_AXI_UNCO (1 << 1) /* Uncache access */
#define DMA_ORDER_ADDR_64 (1 << 0) /* 64bits address support */
#define DMA_ORDER_ASK_MASK (~0x1fUL) /* Ask addr mask */
#define DMA_ORDER_CTRL_MASK (0x0fUL) /* Control mask */
/*
* DMA registers descriptor.
*/
struct loongson_dma_desc {
u32 order; /* Next descriptor address register */
u32 saddr; /* Source address register */
u32 daddr; /* Device address register */
u32 length; /* Total length register */
u32 step_length; /* Memory stride register */
u32 step_times; /* Repeat time register */
u32 cmd; /* Command register */
u32 stats; /* Status register */
u32 order_hi; /* Next descriptor high address register */
u32 saddr_hi; /* High source address register */
u32 res[6]; /* Reserved */
} __packed;
struct loongson_runtime_data {
struct loongson_dma_data *dma_data;
struct loongson_dma_desc *dma_desc_arr;
dma_addr_t dma_desc_arr_phy;
int dma_desc_arr_size;
struct loongson_dma_desc *dma_pos_desc;
dma_addr_t dma_pos_desc_phy;
};
static const struct snd_pcm_hardware ls_pcm_hardware = {
.info = SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_RESUME |
SNDRV_PCM_INFO_PAUSE,
.formats = (SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S20_3LE |
SNDRV_PCM_FMTBIT_S24_LE),
.period_bytes_min = 128,
.period_bytes_max = 128 * 1024,
.periods_min = 1,
.periods_max = PAGE_SIZE / sizeof(struct loongson_dma_desc),
.buffer_bytes_max = 1024 * 1024,
};
static struct
loongson_dma_desc *dma_desc_save(struct loongson_runtime_data *prtd)
{
void __iomem *order_reg = prtd->dma_data->order_addr;
u64 val;
val = (u64)prtd->dma_pos_desc_phy & DMA_ORDER_ASK_MASK;
val |= (readq(order_reg) & DMA_ORDER_CTRL_MASK);
val |= DMA_ORDER_ASK_VALID;
writeq(val, order_reg);
while (readl(order_reg) & DMA_ORDER_ASK_VALID)
udelay(2);
return prtd->dma_pos_desc;
}
static int loongson_pcm_trigger(struct snd_soc_component *component,
struct snd_pcm_substream *substream, int cmd)
{
struct loongson_runtime_data *prtd = substream->runtime->private_data;
struct device *dev = substream->pcm->card->dev;
void __iomem *order_reg = prtd->dma_data->order_addr;
u64 val;
int ret = 0;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
val = prtd->dma_pos_desc_phy & DMA_ORDER_ASK_MASK;
if (dev->coherent_dma_mask == DMA_BIT_MASK(64))
val |= DMA_ORDER_ADDR_64;
else
val &= ~DMA_ORDER_ADDR_64;
val |= (readq(order_reg) & DMA_ORDER_CTRL_MASK);
val |= DMA_ORDER_START;
writeq(val, order_reg);
while ((readl(order_reg) & DMA_ORDER_START))
udelay(2);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
dma_desc_save(prtd);
/* dma stop */
val = readq(order_reg) | DMA_ORDER_STOP;
writeq(val, order_reg);
udelay(1000);
break;
default:
dev_err(dev, "Invalid pcm trigger operation\n");
return -EINVAL;
}
return ret;
}
static int loongson_pcm_hw_params(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct device *dev = substream->pcm->card->dev;
struct loongson_runtime_data *prtd = runtime->private_data;
size_t buf_len = params_buffer_bytes(params);
size_t period_len = params_period_bytes(params);
dma_addr_t order_addr, mem_addr;
struct loongson_dma_desc *desc;
u32 num_periods;
int i;
if (buf_len % period_len) {
dev_err(dev, "buf len not multiply of period len\n");
return -EINVAL;
}
num_periods = buf_len / period_len;
if (!num_periods || num_periods > prtd->dma_desc_arr_size) {
dev_err(dev, "dma data too small or too big\n");
return -EINVAL;
}
snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
runtime->dma_bytes = buf_len;
/* initialize dma descriptor array */
mem_addr = runtime->dma_addr;
order_addr = prtd->dma_desc_arr_phy;
for (i = 0; i < num_periods; i++) {
desc = &prtd->dma_desc_arr[i];
/* next descriptor physical address */
order_addr += sizeof(*desc);
desc->order = lower_32_bits(order_addr | BIT(0));
desc->order_hi = upper_32_bits(order_addr);
desc->saddr = lower_32_bits(mem_addr);
desc->saddr_hi = upper_32_bits(mem_addr);
desc->daddr = prtd->dma_data->dev_addr;
desc->cmd = BIT(0);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
desc->cmd |= BIT(12);
desc->length = period_len >> 2;
desc->step_length = 0;
desc->step_times = 1;
mem_addr += period_len;
}
desc = &prtd->dma_desc_arr[num_periods - 1];
desc->order = lower_32_bits(prtd->dma_desc_arr_phy | BIT(0));
desc->order_hi = upper_32_bits(prtd->dma_desc_arr_phy);
/* init position descriptor */
*prtd->dma_pos_desc = *prtd->dma_desc_arr;
return 0;
}
static snd_pcm_uframes_t
loongson_pcm_pointer(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct loongson_runtime_data *prtd = runtime->private_data;
struct loongson_dma_desc *desc;
snd_pcm_uframes_t x;
u64 addr;
desc = dma_desc_save(prtd);
addr = ((u64)desc->saddr_hi << 32) | desc->saddr;
x = bytes_to_frames(runtime, addr - runtime->dma_addr);
if (x == runtime->buffer_size)
x = 0;
return x;
}
static irqreturn_t loongson_pcm_dma_irq(int irq, void *devid)
{
struct snd_pcm_substream *substream = devid;
snd_pcm_period_elapsed(substream);
return IRQ_HANDLED;
}
static int loongson_pcm_open(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_card *card = substream->pcm->card;
struct loongson_runtime_data *prtd;
struct loongson_dma_data *dma_data;
int ret;
/*
* For mysterious reasons (and despite what the manual says)
* playback samples are lost if the DMA count is not a multiple
* of the DMA burst size. Let's add a rule to enforce that.
*/
snd_pcm_hw_constraint_step(runtime, 0,
SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 128);
snd_pcm_hw_constraint_step(runtime, 0,
SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 128);
snd_pcm_hw_constraint_integer(substream->runtime,
SNDRV_PCM_HW_PARAM_PERIODS);
snd_soc_set_runtime_hwparams(substream, &ls_pcm_hardware);
prtd = kzalloc(sizeof(*prtd), GFP_KERNEL);
if (!prtd)
return -ENOMEM;
prtd->dma_desc_arr = dma_alloc_coherent(card->dev, PAGE_SIZE,
&prtd->dma_desc_arr_phy,
GFP_KERNEL);
if (!prtd->dma_desc_arr) {
ret = -ENOMEM;
goto desc_err;
}
prtd->dma_desc_arr_size = PAGE_SIZE / sizeof(*prtd->dma_desc_arr);
prtd->dma_pos_desc = dma_alloc_coherent(card->dev,
sizeof(*prtd->dma_pos_desc),
&prtd->dma_pos_desc_phy,
GFP_KERNEL);
if (!prtd->dma_pos_desc) {
ret = -ENOMEM;
goto pos_err;
}
dma_data = snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(rtd, 0), substream);
prtd->dma_data = dma_data;
substream->runtime->private_data = prtd;
return 0;
pos_err:
dma_free_coherent(card->dev, PAGE_SIZE, prtd->dma_desc_arr,
prtd->dma_desc_arr_phy);
desc_err:
kfree(prtd);
return ret;
}
static int loongson_pcm_close(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_card *card = substream->pcm->card;
struct loongson_runtime_data *prtd = substream->runtime->private_data;
dma_free_coherent(card->dev, PAGE_SIZE, prtd->dma_desc_arr,
prtd->dma_desc_arr_phy);
dma_free_coherent(card->dev, sizeof(*prtd->dma_pos_desc),
prtd->dma_pos_desc, prtd->dma_pos_desc_phy);
kfree(prtd);
return 0;
}
static int loongson_pcm_mmap(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct vm_area_struct *vma)
{
return remap_pfn_range(vma, vma->vm_start,
substream->dma_buffer.addr >> PAGE_SHIFT,
vma->vm_end - vma->vm_start, vma->vm_page_prot);
}
static int loongson_pcm_new(struct snd_soc_component *component,
struct snd_soc_pcm_runtime *rtd)
{
struct snd_card *card = rtd->card->snd_card;
struct snd_pcm_substream *substream;
struct loongson_dma_data *dma_data;
unsigned int i;
int ret;
for_each_pcm_streams(i) {
substream = rtd->pcm->streams[i].substream;
if (!substream)
continue;
dma_data = snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(rtd, 0),
substream);
ret = devm_request_irq(card->dev, dma_data->irq,
loongson_pcm_dma_irq,
IRQF_TRIGGER_HIGH, LS_I2S_DRVNAME,
substream);
if (ret < 0) {
dev_err(card->dev, "request irq for DMA failed\n");
return ret;
}
}
return snd_pcm_set_fixed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV,
card->dev,
ls_pcm_hardware.buffer_bytes_max);
}
const struct snd_soc_component_driver loongson_i2s_component = {
.name = LS_I2S_DRVNAME,
.open = loongson_pcm_open,
.close = loongson_pcm_close,
.hw_params = loongson_pcm_hw_params,
.trigger = loongson_pcm_trigger,
.pointer = loongson_pcm_pointer,
.mmap = loongson_pcm_mmap,
.pcm_construct = loongson_pcm_new,
};
| linux-master | sound/soc/loongson/loongson_dma.c |
// SPDX-License-Identifier: GPL-2.0
//
// Loongson ASoC Audio Machine driver
//
// Copyright (C) 2023 Loongson Technology Corporation Limited
// Author: Yingkun Meng <[email protected]>
//
#include <linux/module.h>
#include <sound/soc.h>
#include <sound/soc-acpi.h>
#include <linux/acpi.h>
#include <linux/pci.h>
#include <sound/pcm_params.h>
static char codec_name[SND_ACPI_I2C_ID_LEN];
struct loongson_card_data {
struct snd_soc_card snd_card;
unsigned int mclk_fs;
};
static int loongson_card_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
struct loongson_card_data *ls_card = snd_soc_card_get_drvdata(rtd->card);
int ret, mclk;
if (ls_card->mclk_fs) {
mclk = ls_card->mclk_fs * params_rate(params);
ret = snd_soc_dai_set_sysclk(cpu_dai, 0, mclk,
SND_SOC_CLOCK_OUT);
if (ret < 0) {
dev_err(codec_dai->dev, "cpu_dai clock not set\n");
return ret;
}
ret = snd_soc_dai_set_sysclk(codec_dai, 0, mclk,
SND_SOC_CLOCK_IN);
if (ret < 0) {
dev_err(codec_dai->dev, "codec_dai clock not set\n");
return ret;
}
}
return 0;
}
static const struct snd_soc_ops loongson_ops = {
.hw_params = loongson_card_hw_params,
};
SND_SOC_DAILINK_DEFS(analog,
DAILINK_COMP_ARRAY(COMP_CPU("loongson-i2s")),
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
static struct snd_soc_dai_link loongson_dai_links[] = {
{
.name = "Loongson Audio Port",
.stream_name = "Loongson Audio",
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_IB_NF
| SND_SOC_DAIFMT_CBC_CFC,
SND_SOC_DAILINK_REG(analog),
.ops = &loongson_ops,
},
};
static int loongson_card_parse_acpi(struct loongson_card_data *data)
{
struct snd_soc_card *card = &data->snd_card;
struct fwnode_handle *fwnode = card->dev->fwnode;
struct fwnode_reference_args args;
const char *codec_dai_name;
struct acpi_device *adev;
struct device *phy_dev;
int ret, i;
/* fixup platform name based on reference node */
memset(&args, 0, sizeof(args));
ret = acpi_node_get_property_reference(fwnode, "cpu", 0, &args);
if (ret || !is_acpi_device_node(args.fwnode)) {
dev_err(card->dev, "No matching phy in ACPI table\n");
return ret ?: -ENOENT;
}
adev = to_acpi_device_node(args.fwnode);
phy_dev = acpi_get_first_physical_node(adev);
if (!phy_dev)
return -EPROBE_DEFER;
for (i = 0; i < card->num_links; i++)
loongson_dai_links[i].platforms->name = dev_name(phy_dev);
/* fixup codec name based on reference node */
memset(&args, 0, sizeof(args));
ret = acpi_node_get_property_reference(fwnode, "codec", 0, &args);
if (ret || !is_acpi_device_node(args.fwnode)) {
dev_err(card->dev, "No matching phy in ACPI table\n");
return ret ?: -ENOENT;
}
adev = to_acpi_device_node(args.fwnode);
snprintf(codec_name, sizeof(codec_name), "i2c-%s", acpi_dev_name(adev));
for (i = 0; i < card->num_links; i++)
loongson_dai_links[i].codecs->name = codec_name;
device_property_read_string(card->dev, "codec-dai-name",
&codec_dai_name);
for (i = 0; i < card->num_links; i++)
loongson_dai_links[i].codecs->dai_name = codec_dai_name;
return 0;
}
static int loongson_card_parse_of(struct loongson_card_data *data)
{
struct device_node *cpu, *codec;
struct snd_soc_card *card = &data->snd_card;
struct device *dev = card->dev;
int ret, i;
cpu = of_get_child_by_name(dev->of_node, "cpu");
if (!cpu) {
dev_err(dev, "platform property missing or invalid\n");
return -EINVAL;
}
codec = of_get_child_by_name(dev->of_node, "codec");
if (!codec) {
dev_err(dev, "audio-codec property missing or invalid\n");
ret = -EINVAL;
goto err;
}
for (i = 0; i < card->num_links; i++) {
ret = snd_soc_of_get_dlc(cpu, NULL, loongson_dai_links[i].cpus, 0);
if (ret < 0) {
dev_err(dev, "getting cpu dlc error (%d)\n", ret);
goto err;
}
ret = snd_soc_of_get_dlc(codec, NULL, loongson_dai_links[i].codecs, 0);
if (ret < 0) {
dev_err(dev, "getting codec dlc error (%d)\n", ret);
goto err;
}
}
of_node_put(cpu);
of_node_put(codec);
return 0;
err:
of_node_put(cpu);
of_node_put(codec);
return ret;
}
static int loongson_asoc_card_probe(struct platform_device *pdev)
{
struct loongson_card_data *ls_priv;
struct snd_soc_card *card;
int ret;
ls_priv = devm_kzalloc(&pdev->dev, sizeof(*ls_priv), GFP_KERNEL);
if (!ls_priv)
return -ENOMEM;
card = &ls_priv->snd_card;
card->dev = &pdev->dev;
card->owner = THIS_MODULE;
card->dai_link = loongson_dai_links;
card->num_links = ARRAY_SIZE(loongson_dai_links);
snd_soc_card_set_drvdata(card, ls_priv);
ret = device_property_read_string(&pdev->dev, "model", &card->name);
if (ret) {
dev_err(&pdev->dev, "Error parsing card name: %d\n", ret);
return ret;
}
ret = device_property_read_u32(&pdev->dev, "mclk-fs", &ls_priv->mclk_fs);
if (ret) {
dev_err(&pdev->dev, "Error parsing mclk-fs: %d\n", ret);
return ret;
}
if (has_acpi_companion(&pdev->dev))
ret = loongson_card_parse_acpi(ls_priv);
else
ret = loongson_card_parse_of(ls_priv);
if (ret < 0)
return ret;
ret = devm_snd_soc_register_card(&pdev->dev, card);
return ret;
}
static const struct of_device_id loongson_asoc_dt_ids[] = {
{ .compatible = "loongson,ls-audio-card" },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, loongson_asoc_dt_ids);
static struct platform_driver loongson_audio_driver = {
.probe = loongson_asoc_card_probe,
.driver = {
.name = "loongson-asoc-card",
.pm = &snd_soc_pm_ops,
.of_match_table = loongson_asoc_dt_ids,
},
};
module_platform_driver(loongson_audio_driver);
MODULE_DESCRIPTION("Loongson ASoc Sound Card driver");
MODULE_AUTHOR("Loongson Technology Corporation Limited");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/loongson/loongson_card.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (C) 2017 Samsung Electronics Co., Ltd.
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/module.h>
#include <sound/soc.h>
#include <sound/pcm_params.h>
#include "i2s.h"
#include "i2s-regs.h"
struct odroid_priv {
struct snd_soc_card card;
struct clk *clk_i2s_bus;
struct clk *sclk_i2s;
/* Spinlock protecting fields below */
spinlock_t lock;
unsigned int be_sample_rate;
bool be_active;
};
static int odroid_card_fe_startup(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
snd_pcm_hw_constraint_single(runtime, SNDRV_PCM_HW_PARAM_CHANNELS, 2);
return 0;
}
static int odroid_card_fe_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct odroid_priv *priv = snd_soc_card_get_drvdata(rtd->card);
unsigned long flags;
int ret = 0;
spin_lock_irqsave(&priv->lock, flags);
if (priv->be_active && priv->be_sample_rate != params_rate(params))
ret = -EINVAL;
spin_unlock_irqrestore(&priv->lock, flags);
return ret;
}
static const struct snd_soc_ops odroid_card_fe_ops = {
.startup = odroid_card_fe_startup,
.hw_params = odroid_card_fe_hw_params,
};
static int odroid_card_be_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct odroid_priv *priv = snd_soc_card_get_drvdata(rtd->card);
unsigned int pll_freq, rclk_freq, rfs;
unsigned long flags;
int ret;
switch (params_rate(params)) {
case 64000:
pll_freq = 196608001U;
rfs = 384;
break;
case 44100:
case 88200:
pll_freq = 180633609U;
rfs = 512;
break;
case 32000:
case 48000:
case 96000:
pll_freq = 196608001U;
rfs = 512;
break;
default:
return -EINVAL;
}
ret = clk_set_rate(priv->clk_i2s_bus, pll_freq / 2 + 1);
if (ret < 0)
return ret;
/*
* We add 2 to the rclk_freq value in order to avoid too low clock
* frequency values due to the EPLL output frequency not being exact
* multiple of the audio sampling rate.
*/
rclk_freq = params_rate(params) * rfs + 2;
ret = clk_set_rate(priv->sclk_i2s, rclk_freq);
if (ret < 0)
return ret;
if (rtd->dai_link->num_codecs > 1) {
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 1);
ret = snd_soc_dai_set_sysclk(codec_dai, 0, rclk_freq,
SND_SOC_CLOCK_IN);
if (ret < 0)
return ret;
}
spin_lock_irqsave(&priv->lock, flags);
priv->be_sample_rate = params_rate(params);
spin_unlock_irqrestore(&priv->lock, flags);
return 0;
}
static int odroid_card_be_trigger(struct snd_pcm_substream *substream, int cmd)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct odroid_priv *priv = snd_soc_card_get_drvdata(rtd->card);
unsigned long flags;
spin_lock_irqsave(&priv->lock, flags);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
priv->be_active = true;
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
priv->be_active = false;
break;
}
spin_unlock_irqrestore(&priv->lock, flags);
return 0;
}
static const struct snd_soc_ops odroid_card_be_ops = {
.hw_params = odroid_card_be_hw_params,
.trigger = odroid_card_be_trigger,
};
/* DAPM routes for backward compatibility with old DTS */
static const struct snd_soc_dapm_route odroid_dapm_routes[] = {
{ "I2S Playback", NULL, "Mixer DAI TX" },
{ "HiFi Playback", NULL, "Mixer DAI TX" },
};
SND_SOC_DAILINK_DEFS(primary,
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_PLATFORM("3830000.i2s")));
SND_SOC_DAILINK_DEFS(mixer,
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_DUMMY()));
SND_SOC_DAILINK_DEFS(secondary,
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_PLATFORM("3830000.i2s-sec")));
static struct snd_soc_dai_link odroid_card_dais[] = {
{
/* Primary FE <-> BE link */
.ops = &odroid_card_fe_ops,
.name = "Primary",
.stream_name = "Primary",
.dynamic = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(primary),
}, {
/* BE <-> CODECs link */
.name = "I2S Mixer",
.ops = &odroid_card_be_ops,
.no_pcm = 1,
.dpcm_playback = 1,
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS,
SND_SOC_DAILINK_REG(mixer),
}, {
/* Secondary FE <-> BE link */
.playback_only = 1,
.ops = &odroid_card_fe_ops,
.name = "Secondary",
.stream_name = "Secondary",
.dynamic = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(secondary),
}
};
static int odroid_audio_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *cpu_dai = NULL;
struct device_node *cpu, *codec;
struct odroid_priv *priv;
struct snd_soc_card *card;
struct snd_soc_dai_link *link, *codec_link;
int num_pcms, ret, i;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
card = &priv->card;
card->dev = dev;
card->owner = THIS_MODULE;
card->fully_routed = true;
spin_lock_init(&priv->lock);
snd_soc_card_set_drvdata(card, priv);
ret = snd_soc_of_parse_card_name(card, "model");
if (ret < 0)
return ret;
if (of_property_present(dev->of_node, "samsung,audio-widgets")) {
ret = snd_soc_of_parse_audio_simple_widgets(card,
"samsung,audio-widgets");
if (ret < 0)
return ret;
}
ret = 0;
if (of_property_present(dev->of_node, "audio-routing"))
ret = snd_soc_of_parse_audio_routing(card, "audio-routing");
else if (of_property_present(dev->of_node, "samsung,audio-routing"))
ret = snd_soc_of_parse_audio_routing(card, "samsung,audio-routing");
if (ret < 0)
return ret;
card->dai_link = odroid_card_dais;
card->num_links = ARRAY_SIZE(odroid_card_dais);
cpu = of_get_child_by_name(dev->of_node, "cpu");
codec = of_get_child_by_name(dev->of_node, "codec");
link = card->dai_link;
codec_link = &card->dai_link[1];
/*
* For backwards compatibility create the secondary CPU DAI link only
* if there are 2 CPU DAI entries in the cpu sound-dai property in DT.
* Also add required DAPM routes not available in old DTS.
*/
num_pcms = of_count_phandle_with_args(cpu, "sound-dai",
"#sound-dai-cells");
if (num_pcms == 1) {
card->dapm_routes = odroid_dapm_routes;
card->num_dapm_routes = ARRAY_SIZE(odroid_dapm_routes);
card->num_links--;
}
for (i = 0; i < num_pcms; i++, link += 2) {
ret = snd_soc_of_get_dai_name(cpu, &link->cpus->dai_name, i);
if (ret < 0)
break;
}
if (ret == 0) {
cpu_dai = of_parse_phandle(cpu, "sound-dai", 0);
if (!cpu_dai)
ret = -EINVAL;
}
of_node_put(cpu);
if (ret < 0)
goto err_put_node;
ret = snd_soc_of_get_dai_link_codecs(dev, codec, codec_link);
if (ret < 0)
goto err_put_cpu_dai;
/* Set capture capability only for boards with the MAX98090 CODEC */
if (codec_link->num_codecs > 1) {
card->dai_link[0].dpcm_capture = 1;
card->dai_link[1].dpcm_capture = 1;
}
priv->sclk_i2s = of_clk_get_by_name(cpu_dai, "i2s_opclk1");
if (IS_ERR(priv->sclk_i2s)) {
ret = PTR_ERR(priv->sclk_i2s);
goto err_put_cpu_dai;
}
priv->clk_i2s_bus = of_clk_get_by_name(cpu_dai, "iis");
if (IS_ERR(priv->clk_i2s_bus)) {
ret = PTR_ERR(priv->clk_i2s_bus);
goto err_put_sclk;
}
ret = devm_snd_soc_register_card(dev, card);
if (ret < 0) {
dev_err_probe(dev, ret, "snd_soc_register_card() failed\n");
goto err_put_clk_i2s;
}
of_node_put(cpu_dai);
of_node_put(codec);
return 0;
err_put_clk_i2s:
clk_put(priv->clk_i2s_bus);
err_put_sclk:
clk_put(priv->sclk_i2s);
err_put_cpu_dai:
of_node_put(cpu_dai);
snd_soc_of_put_dai_link_codecs(codec_link);
err_put_node:
of_node_put(codec);
return ret;
}
static void odroid_audio_remove(struct platform_device *pdev)
{
struct odroid_priv *priv = platform_get_drvdata(pdev);
snd_soc_of_put_dai_link_codecs(&priv->card.dai_link[1]);
clk_put(priv->sclk_i2s);
clk_put(priv->clk_i2s_bus);
}
static const struct of_device_id odroid_audio_of_match[] = {
{ .compatible = "hardkernel,odroid-xu3-audio" },
{ .compatible = "hardkernel,odroid-xu4-audio" },
{ .compatible = "samsung,odroid-xu3-audio" },
{ .compatible = "samsung,odroid-xu4-audio" },
{ },
};
MODULE_DEVICE_TABLE(of, odroid_audio_of_match);
static struct platform_driver odroid_audio_driver = {
.driver = {
.name = "odroid-audio",
.of_match_table = odroid_audio_of_match,
.pm = &snd_soc_pm_ops,
},
.probe = odroid_audio_probe,
.remove_new = odroid_audio_remove,
};
module_platform_driver(odroid_audio_driver);
MODULE_AUTHOR("Sylwester Nawrocki <[email protected]>");
MODULE_DESCRIPTION("Odroid XU3/XU4 audio support");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/samsung/odroid.c |
// SPDX-License-Identifier: GPL-2.0+
//
// Littlemill audio support
//
// Copyright 2011 Wolfson Microelectronics
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/jack.h>
#include <linux/gpio.h>
#include <linux/module.h>
#include "../codecs/wm8994.h"
static int sample_rate = 44100;
static int littlemill_set_bias_level(struct snd_soc_card *card,
struct snd_soc_dapm_context *dapm,
enum snd_soc_bias_level level)
{
struct snd_soc_pcm_runtime *rtd;
struct snd_soc_dai *aif1_dai;
int ret;
rtd = snd_soc_get_pcm_runtime(card, &card->dai_link[0]);
aif1_dai = asoc_rtd_to_codec(rtd, 0);
if (dapm->dev != aif1_dai->dev)
return 0;
switch (level) {
case SND_SOC_BIAS_PREPARE:
/*
* If we've not already clocked things via hw_params()
* then do so now, otherwise these are noops.
*/
if (dapm->bias_level == SND_SOC_BIAS_STANDBY) {
ret = snd_soc_dai_set_pll(aif1_dai, WM8994_FLL1,
WM8994_FLL_SRC_MCLK2, 32768,
sample_rate * 512);
if (ret < 0) {
pr_err("Failed to start FLL: %d\n", ret);
return ret;
}
ret = snd_soc_dai_set_sysclk(aif1_dai,
WM8994_SYSCLK_FLL1,
sample_rate * 512,
SND_SOC_CLOCK_IN);
if (ret < 0) {
pr_err("Failed to set SYSCLK: %d\n", ret);
return ret;
}
}
break;
default:
break;
}
return 0;
}
static int littlemill_set_bias_level_post(struct snd_soc_card *card,
struct snd_soc_dapm_context *dapm,
enum snd_soc_bias_level level)
{
struct snd_soc_pcm_runtime *rtd;
struct snd_soc_dai *aif1_dai;
int ret;
rtd = snd_soc_get_pcm_runtime(card, &card->dai_link[0]);
aif1_dai = asoc_rtd_to_codec(rtd, 0);
if (dapm->dev != aif1_dai->dev)
return 0;
switch (level) {
case SND_SOC_BIAS_STANDBY:
ret = snd_soc_dai_set_sysclk(aif1_dai, WM8994_SYSCLK_MCLK2,
32768, SND_SOC_CLOCK_IN);
if (ret < 0) {
pr_err("Failed to switch away from FLL1: %d\n", ret);
return ret;
}
ret = snd_soc_dai_set_pll(aif1_dai, WM8994_FLL1,
0, 0, 0);
if (ret < 0) {
pr_err("Failed to stop FLL1: %d\n", ret);
return ret;
}
break;
default:
break;
}
dapm->bias_level = level;
return 0;
}
static int littlemill_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
int ret;
sample_rate = params_rate(params);
ret = snd_soc_dai_set_pll(codec_dai, WM8994_FLL1,
WM8994_FLL_SRC_MCLK2, 32768,
sample_rate * 512);
if (ret < 0) {
pr_err("Failed to start FLL: %d\n", ret);
return ret;
}
ret = snd_soc_dai_set_sysclk(codec_dai,
WM8994_SYSCLK_FLL1,
sample_rate * 512,
SND_SOC_CLOCK_IN);
if (ret < 0) {
pr_err("Failed to set SYSCLK: %d\n", ret);
return ret;
}
return 0;
}
static const struct snd_soc_ops littlemill_ops = {
.hw_params = littlemill_hw_params,
};
static const struct snd_soc_pcm_stream baseband_params = {
.formats = SNDRV_PCM_FMTBIT_S32_LE,
.rate_min = 8000,
.rate_max = 8000,
.channels_min = 2,
.channels_max = 2,
};
SND_SOC_DAILINK_DEFS(cpu,
DAILINK_COMP_ARRAY(COMP_CPU("samsung-i2s.0")),
DAILINK_COMP_ARRAY(COMP_CODEC("wm8994-codec", "wm8994-aif1")),
DAILINK_COMP_ARRAY(COMP_PLATFORM("samsung-i2s.0")));
SND_SOC_DAILINK_DEFS(baseband,
DAILINK_COMP_ARRAY(COMP_CPU("wm8994-aif2")),
DAILINK_COMP_ARRAY(COMP_CODEC("wm1250-ev1.1-0027",
"wm1250-ev1")));
static struct snd_soc_dai_link littlemill_dai[] = {
{
.name = "CPU",
.stream_name = "CPU",
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF
| SND_SOC_DAIFMT_CBM_CFM,
.ops = &littlemill_ops,
SND_SOC_DAILINK_REG(cpu),
},
{
.name = "Baseband",
.stream_name = "Baseband",
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF
| SND_SOC_DAIFMT_CBM_CFM,
.ignore_suspend = 1,
.c2c_params = &baseband_params,
.num_c2c_params = 1,
SND_SOC_DAILINK_REG(baseband),
},
};
static int bbclk_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_card *card = w->dapm->card;
struct snd_soc_pcm_runtime *rtd;
struct snd_soc_dai *aif2_dai;
int ret;
rtd = snd_soc_get_pcm_runtime(card, &card->dai_link[1]);
aif2_dai = asoc_rtd_to_cpu(rtd, 0);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
ret = snd_soc_dai_set_pll(aif2_dai, WM8994_FLL2,
WM8994_FLL_SRC_BCLK, 64 * 8000,
8000 * 256);
if (ret < 0) {
pr_err("Failed to start FLL: %d\n", ret);
return ret;
}
ret = snd_soc_dai_set_sysclk(aif2_dai, WM8994_SYSCLK_FLL2,
8000 * 256,
SND_SOC_CLOCK_IN);
if (ret < 0) {
pr_err("Failed to set SYSCLK: %d\n", ret);
return ret;
}
break;
case SND_SOC_DAPM_POST_PMD:
ret = snd_soc_dai_set_sysclk(aif2_dai, WM8994_SYSCLK_MCLK2,
32768, SND_SOC_CLOCK_IN);
if (ret < 0) {
pr_err("Failed to switch away from FLL2: %d\n", ret);
return ret;
}
ret = snd_soc_dai_set_pll(aif2_dai, WM8994_FLL2,
0, 0, 0);
if (ret < 0) {
pr_err("Failed to stop FLL2: %d\n", ret);
return ret;
}
break;
default:
return -EINVAL;
}
return 0;
}
static const struct snd_kcontrol_new controls[] = {
SOC_DAPM_PIN_SWITCH("Headphone"),
SOC_DAPM_PIN_SWITCH("Headset Mic"),
SOC_DAPM_PIN_SWITCH("WM1250 Input"),
SOC_DAPM_PIN_SWITCH("WM1250 Output"),
};
static const struct snd_soc_dapm_widget widgets[] = {
SND_SOC_DAPM_HP("Headphone", NULL),
SND_SOC_DAPM_HP("Headset Mic", NULL),
SND_SOC_DAPM_MIC("AMIC", NULL),
SND_SOC_DAPM_MIC("DMIC", NULL),
SND_SOC_DAPM_SUPPLY_S("Baseband Clock", -1, SND_SOC_NOPM, 0, 0,
bbclk_ev,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
};
static const struct snd_soc_dapm_route audio_paths[] = {
{ "Headphone", NULL, "HPOUT1L" },
{ "Headphone", NULL, "HPOUT1R" },
{ "AMIC", NULL, "MICBIAS1" }, /* Default for AMICBIAS jumper */
{ "IN1LN", NULL, "AMIC" },
{ "DMIC", NULL, "MICBIAS2" }, /* Default for DMICBIAS jumper */
{ "DMIC1DAT", NULL, "DMIC" },
{ "DMIC2DAT", NULL, "DMIC" },
{ "AIF2CLK", NULL, "Baseband Clock" },
};
static struct snd_soc_jack littlemill_headset;
static struct snd_soc_jack_pin littlemill_headset_pins[] = {
{
.pin = "Headphone",
.mask = SND_JACK_HEADPHONE,
},
{
.pin = "Headset Mic",
.mask = SND_JACK_MICROPHONE,
},
};
static int littlemill_late_probe(struct snd_soc_card *card)
{
struct snd_soc_pcm_runtime *rtd;
struct snd_soc_component *component;
struct snd_soc_dai *aif1_dai;
struct snd_soc_dai *aif2_dai;
int ret;
rtd = snd_soc_get_pcm_runtime(card, &card->dai_link[0]);
component = asoc_rtd_to_codec(rtd, 0)->component;
aif1_dai = asoc_rtd_to_codec(rtd, 0);
rtd = snd_soc_get_pcm_runtime(card, &card->dai_link[1]);
aif2_dai = asoc_rtd_to_cpu(rtd, 0);
ret = snd_soc_dai_set_sysclk(aif1_dai, WM8994_SYSCLK_MCLK2,
32768, SND_SOC_CLOCK_IN);
if (ret < 0)
return ret;
ret = snd_soc_dai_set_sysclk(aif2_dai, WM8994_SYSCLK_MCLK2,
32768, SND_SOC_CLOCK_IN);
if (ret < 0)
return ret;
ret = snd_soc_card_jack_new_pins(card, "Headset",
SND_JACK_HEADSET | SND_JACK_MECHANICAL |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3 |
SND_JACK_BTN_4 | SND_JACK_BTN_5,
&littlemill_headset,
littlemill_headset_pins,
ARRAY_SIZE(littlemill_headset_pins));
if (ret)
return ret;
/* This will check device compatibility itself */
wm8958_mic_detect(component, &littlemill_headset, NULL, NULL, NULL, NULL);
/* As will this */
wm8994_mic_detect(component, &littlemill_headset, 1);
return 0;
}
static struct snd_soc_card littlemill = {
.name = "Littlemill",
.owner = THIS_MODULE,
.dai_link = littlemill_dai,
.num_links = ARRAY_SIZE(littlemill_dai),
.set_bias_level = littlemill_set_bias_level,
.set_bias_level_post = littlemill_set_bias_level_post,
.controls = controls,
.num_controls = ARRAY_SIZE(controls),
.dapm_widgets = widgets,
.num_dapm_widgets = ARRAY_SIZE(widgets),
.dapm_routes = audio_paths,
.num_dapm_routes = ARRAY_SIZE(audio_paths),
.late_probe = littlemill_late_probe,
};
static int littlemill_probe(struct platform_device *pdev)
{
struct snd_soc_card *card = &littlemill;
int ret;
card->dev = &pdev->dev;
ret = devm_snd_soc_register_card(&pdev->dev, card);
if (ret)
dev_err_probe(&pdev->dev, ret, "snd_soc_register_card() failed\n");
return ret;
}
static struct platform_driver littlemill_driver = {
.driver = {
.name = "littlemill",
.pm = &snd_soc_pm_ops,
},
.probe = littlemill_probe,
};
module_platform_driver(littlemill_driver);
MODULE_DESCRIPTION("Littlemill audio support");
MODULE_AUTHOR("Mark Brown <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:littlemill");
| linux-master | sound/soc/samsung/littlemill.c |
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (c) 2014, Insignal Co., Ltd.
//
// Author: Claude <[email protected]>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include "../codecs/wm8994.h"
#include "i2s.h"
static int arndale_rt5631_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
int rfs, ret;
unsigned long rclk;
rfs = 256;
rclk = params_rate(params) * rfs;
ret = snd_soc_dai_set_sysclk(cpu_dai, SAMSUNG_I2S_CDCLK,
0, SND_SOC_CLOCK_OUT);
if (ret < 0)
return ret;
ret = snd_soc_dai_set_sysclk(cpu_dai, SAMSUNG_I2S_RCLKSRC_0,
0, SND_SOC_CLOCK_OUT);
if (ret < 0)
return ret;
ret = snd_soc_dai_set_sysclk(codec_dai, 0, rclk, SND_SOC_CLOCK_OUT);
if (ret < 0)
return ret;
return 0;
}
static const struct snd_soc_ops arndale_rt5631_ops = {
.hw_params = arndale_rt5631_hw_params,
};
static int arndale_wm1811_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
unsigned int rfs, rclk;
/* Ensure AIF1CLK is >= 3 MHz for optimal performance */
if (params_width(params) == 24)
rfs = 384;
else if (params_rate(params) == 8000 || params_rate(params) == 11025)
rfs = 512;
else
rfs = 256;
rclk = params_rate(params) * rfs;
/*
* We add 1 to the frequency value to ensure proper EPLL setting
* for each audio sampling rate (see epll_24mhz_tbl in drivers/clk/
* samsung/clk-exynos5250.c for list of available EPLL rates).
* The CODEC uses clk API and the value will be rounded hence the MCLK1
* clock's frequency will still be exact multiple of the sample rate.
*/
return snd_soc_dai_set_sysclk(codec_dai, WM8994_SYSCLK_MCLK1,
rclk + 1, SND_SOC_CLOCK_IN);
}
static const struct snd_soc_ops arndale_wm1811_ops = {
.hw_params = arndale_wm1811_hw_params,
};
SND_SOC_DAILINK_DEFS(rt5631_hifi,
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "rt5631-aif1")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
static struct snd_soc_dai_link arndale_rt5631_dai[] = {
{
.name = "RT5631 HiFi",
.stream_name = "Primary",
.dai_fmt = SND_SOC_DAIFMT_I2S
| SND_SOC_DAIFMT_NB_NF
| SND_SOC_DAIFMT_CBS_CFS,
.ops = &arndale_rt5631_ops,
SND_SOC_DAILINK_REG(rt5631_hifi),
},
};
SND_SOC_DAILINK_DEFS(wm1811_hifi,
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "wm8994-aif1")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
static struct snd_soc_dai_link arndale_wm1811_dai[] = {
{
.name = "WM1811 HiFi",
.stream_name = "Primary",
.dai_fmt = SND_SOC_DAIFMT_I2S
| SND_SOC_DAIFMT_NB_NF
| SND_SOC_DAIFMT_CBM_CFM,
.ops = &arndale_wm1811_ops,
SND_SOC_DAILINK_REG(wm1811_hifi),
},
};
static struct snd_soc_card arndale_rt5631 = {
.name = "Arndale RT5631",
.owner = THIS_MODULE,
.dai_link = arndale_rt5631_dai,
.num_links = ARRAY_SIZE(arndale_rt5631_dai),
};
static struct snd_soc_card arndale_wm1811 = {
.name = "Arndale WM1811",
.owner = THIS_MODULE,
.dai_link = arndale_wm1811_dai,
.num_links = ARRAY_SIZE(arndale_wm1811_dai),
};
static void arndale_put_of_nodes(struct snd_soc_card *card)
{
struct snd_soc_dai_link *dai_link;
int i;
for_each_card_prelinks(card, i, dai_link) {
of_node_put(dai_link->cpus->of_node);
of_node_put(dai_link->codecs->of_node);
}
}
static int arndale_audio_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct snd_soc_card *card;
struct snd_soc_dai_link *dai_link;
int ret;
card = (struct snd_soc_card *)of_device_get_match_data(&pdev->dev);
card->dev = &pdev->dev;
dai_link = card->dai_link;
dai_link->cpus->of_node = of_parse_phandle(np, "samsung,audio-cpu", 0);
if (!dai_link->cpus->of_node) {
dev_err(&pdev->dev,
"Property 'samsung,audio-cpu' missing or invalid\n");
return -EINVAL;
}
if (!dai_link->platforms->name)
dai_link->platforms->of_node = dai_link->cpus->of_node;
dai_link->codecs->of_node = of_parse_phandle(np, "samsung,audio-codec", 0);
if (!dai_link->codecs->of_node) {
dev_err(&pdev->dev,
"Property 'samsung,audio-codec' missing or invalid\n");
ret = -EINVAL;
goto err_put_of_nodes;
}
ret = devm_snd_soc_register_card(card->dev, card);
if (ret) {
dev_err_probe(&pdev->dev, ret,
"snd_soc_register_card() failed\n");
goto err_put_of_nodes;
}
return 0;
err_put_of_nodes:
arndale_put_of_nodes(card);
return ret;
}
static void arndale_audio_remove(struct platform_device *pdev)
{
struct snd_soc_card *card = platform_get_drvdata(pdev);
arndale_put_of_nodes(card);
}
static const struct of_device_id arndale_audio_of_match[] = {
{ .compatible = "samsung,arndale-rt5631", .data = &arndale_rt5631 },
{ .compatible = "samsung,arndale-alc5631", .data = &arndale_rt5631 },
{ .compatible = "samsung,arndale-wm1811", .data = &arndale_wm1811 },
{},
};
MODULE_DEVICE_TABLE(of, arndale_audio_of_match);
static struct platform_driver arndale_audio_driver = {
.driver = {
.name = "arndale-audio",
.pm = &snd_soc_pm_ops,
.of_match_table = arndale_audio_of_match,
},
.probe = arndale_audio_probe,
.remove_new = arndale_audio_remove,
};
module_platform_driver(arndale_audio_driver);
MODULE_AUTHOR("Claude <[email protected]>");
MODULE_DESCRIPTION("ALSA SoC Driver for Arndale Board");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/samsung/arndale.c |
// SPDX-License-Identifier: GPL-2.0
//
// ASoC machine driver for Snow boards
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include "i2s.h"
#define FIN_PLL_RATE 24000000
SND_SOC_DAILINK_DEFS(links,
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
struct snow_priv {
struct snd_soc_dai_link dai_link;
struct clk *clk_i2s_bus;
};
static int snow_card_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
static const unsigned int pll_rate[] = {
73728000U, 67737602U, 49152000U, 45158401U, 32768001U
};
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snow_priv *priv = snd_soc_card_get_drvdata(rtd->card);
int bfs, psr, rfs, bitwidth;
unsigned long int rclk;
long int freq = -EINVAL;
int ret, i;
bitwidth = snd_pcm_format_width(params_format(params));
if (bitwidth < 0) {
dev_err(rtd->card->dev, "Invalid bit-width: %d\n", bitwidth);
return bitwidth;
}
if (bitwidth != 16 && bitwidth != 24) {
dev_err(rtd->card->dev, "Unsupported bit-width: %d\n", bitwidth);
return -EINVAL;
}
bfs = 2 * bitwidth;
switch (params_rate(params)) {
case 16000:
case 22050:
case 24000:
case 32000:
case 44100:
case 48000:
case 88200:
case 96000:
rfs = 8 * bfs;
break;
case 64000:
rfs = 384;
break;
case 8000:
case 11025:
case 12000:
rfs = 16 * bfs;
break;
default:
return -EINVAL;
}
rclk = params_rate(params) * rfs;
for (psr = 8; psr > 0; psr /= 2) {
for (i = 0; i < ARRAY_SIZE(pll_rate); i++) {
if ((pll_rate[i] - rclk * psr) <= 2) {
freq = pll_rate[i];
break;
}
}
}
if (freq < 0) {
dev_err(rtd->card->dev, "Unsupported RCLK rate: %lu\n", rclk);
return -EINVAL;
}
ret = clk_set_rate(priv->clk_i2s_bus, freq);
if (ret < 0) {
dev_err(rtd->card->dev, "I2S bus clock rate set failed\n");
return ret;
}
return 0;
}
static const struct snd_soc_ops snow_card_ops = {
.hw_params = snow_card_hw_params,
};
static int snow_late_probe(struct snd_soc_card *card)
{
struct snd_soc_pcm_runtime *rtd;
struct snd_soc_dai *codec_dai;
rtd = snd_soc_get_pcm_runtime(card, &card->dai_link[0]);
/* In the multi-codec case codec_dais 0 is MAX98095 and 1 is HDMI. */
codec_dai = asoc_rtd_to_codec(rtd, 0);
/* Set the MCLK rate for the codec */
return snd_soc_dai_set_sysclk(codec_dai, 0,
FIN_PLL_RATE, SND_SOC_CLOCK_IN);
}
static struct snd_soc_card snow_snd = {
.name = "Snow-I2S",
.owner = THIS_MODULE,
.late_probe = snow_late_probe,
};
static int snow_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct snd_soc_card *card = &snow_snd;
struct device_node *cpu, *codec;
struct snd_soc_dai_link *link;
struct snow_priv *priv;
int ret;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
link = &priv->dai_link;
link->dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS;
link->name = "Primary";
link->stream_name = link->name;
link->cpus = links_cpus;
link->num_cpus = ARRAY_SIZE(links_cpus);
link->codecs = links_codecs;
link->num_codecs = ARRAY_SIZE(links_codecs);
link->platforms = links_platforms;
link->num_platforms = ARRAY_SIZE(links_platforms);
card->dai_link = link;
card->num_links = 1;
card->dev = dev;
/* Try new DT bindings with HDMI support first. */
cpu = of_get_child_by_name(dev->of_node, "cpu");
if (cpu) {
link->ops = &snow_card_ops;
link->cpus->of_node = of_parse_phandle(cpu, "sound-dai", 0);
of_node_put(cpu);
if (!link->cpus->of_node) {
dev_err(dev, "Failed parsing cpu/sound-dai property\n");
return -EINVAL;
}
codec = of_get_child_by_name(dev->of_node, "codec");
ret = snd_soc_of_get_dai_link_codecs(dev, codec, link);
of_node_put(codec);
if (ret < 0) {
of_node_put(link->cpus->of_node);
dev_err(dev, "Failed parsing codec node\n");
return ret;
}
priv->clk_i2s_bus = of_clk_get_by_name(link->cpus->of_node,
"i2s_opclk0");
if (IS_ERR(priv->clk_i2s_bus)) {
snd_soc_of_put_dai_link_codecs(link);
of_node_put(link->cpus->of_node);
return PTR_ERR(priv->clk_i2s_bus);
}
} else {
link->codecs->dai_name = "HiFi";
link->cpus->of_node = of_parse_phandle(dev->of_node,
"samsung,i2s-controller", 0);
if (!link->cpus->of_node) {
dev_err(dev, "i2s-controller property parse error\n");
return -EINVAL;
}
link->codecs->of_node = of_parse_phandle(dev->of_node,
"samsung,audio-codec", 0);
if (!link->codecs->of_node) {
of_node_put(link->cpus->of_node);
dev_err(dev, "audio-codec property parse error\n");
return -EINVAL;
}
}
link->platforms->of_node = link->cpus->of_node;
/* Update card-name if provided through DT, else use default name */
snd_soc_of_parse_card_name(card, "samsung,model");
snd_soc_card_set_drvdata(card, priv);
ret = devm_snd_soc_register_card(dev, card);
if (ret)
return dev_err_probe(&pdev->dev, ret,
"snd_soc_register_card failed\n");
return 0;
}
static void snow_remove(struct platform_device *pdev)
{
struct snow_priv *priv = platform_get_drvdata(pdev);
struct snd_soc_dai_link *link = &priv->dai_link;
of_node_put(link->cpus->of_node);
of_node_put(link->codecs->of_node);
snd_soc_of_put_dai_link_codecs(link);
clk_put(priv->clk_i2s_bus);
}
static const struct of_device_id snow_of_match[] = {
{ .compatible = "google,snow-audio-max98090", },
{ .compatible = "google,snow-audio-max98091", },
{ .compatible = "google,snow-audio-max98095", },
{},
};
MODULE_DEVICE_TABLE(of, snow_of_match);
static struct platform_driver snow_driver = {
.driver = {
.name = "snow-audio",
.pm = &snd_soc_pm_ops,
.of_match_table = snow_of_match,
},
.probe = snow_probe,
.remove_new = snow_remove,
};
module_platform_driver(snow_driver);
MODULE_DESCRIPTION("ALSA SoC Audio machine driver for Snow");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/samsung/snow.c |
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2015 - 2016 Samsung Electronics Co., Ltd.
//
// Authors: Inha Song <[email protected]>
// Sylwester Nawrocki <[email protected]>
#include <linux/clk.h>
#include <linux/gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/module.h>
#include <linux/of.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include "i2s.h"
#include "../codecs/wm5110.h"
/*
* The source clock is XCLKOUT with its mux set to the external fixed rate
* oscillator (XXTI).
*/
#define MCLK_RATE 24000000U
#define TM2_DAI_AIF1 0
#define TM2_DAI_AIF2 1
struct tm2_machine_priv {
struct snd_soc_component *component;
unsigned int sysclk_rate;
struct gpio_desc *gpio_mic_bias;
};
static int tm2_start_sysclk(struct snd_soc_card *card)
{
struct tm2_machine_priv *priv = snd_soc_card_get_drvdata(card);
struct snd_soc_component *component = priv->component;
int ret;
ret = snd_soc_component_set_pll(component, WM5110_FLL1_REFCLK,
ARIZONA_FLL_SRC_MCLK1,
MCLK_RATE,
priv->sysclk_rate);
if (ret < 0) {
dev_err(component->dev, "Failed to set FLL1 source: %d\n", ret);
return ret;
}
ret = snd_soc_component_set_pll(component, WM5110_FLL1,
ARIZONA_FLL_SRC_MCLK1,
MCLK_RATE,
priv->sysclk_rate);
if (ret < 0) {
dev_err(component->dev, "Failed to start FLL1: %d\n", ret);
return ret;
}
ret = snd_soc_component_set_sysclk(component, ARIZONA_CLK_SYSCLK,
ARIZONA_CLK_SRC_FLL1,
priv->sysclk_rate,
SND_SOC_CLOCK_IN);
if (ret < 0) {
dev_err(component->dev, "Failed to set SYSCLK source: %d\n", ret);
return ret;
}
return 0;
}
static int tm2_stop_sysclk(struct snd_soc_card *card)
{
struct tm2_machine_priv *priv = snd_soc_card_get_drvdata(card);
struct snd_soc_component *component = priv->component;
int ret;
ret = snd_soc_component_set_pll(component, WM5110_FLL1, 0, 0, 0);
if (ret < 0) {
dev_err(component->dev, "Failed to stop FLL1: %d\n", ret);
return ret;
}
ret = snd_soc_component_set_sysclk(component, ARIZONA_CLK_SYSCLK,
ARIZONA_CLK_SRC_FLL1, 0, 0);
if (ret < 0) {
dev_err(component->dev, "Failed to stop SYSCLK: %d\n", ret);
return ret;
}
return 0;
}
static int tm2_aif1_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component;
struct tm2_machine_priv *priv = snd_soc_card_get_drvdata(rtd->card);
switch (params_rate(params)) {
case 4000:
case 8000:
case 12000:
case 16000:
case 24000:
case 32000:
case 48000:
case 96000:
case 192000:
/* Highest possible SYSCLK frequency: 147.456MHz */
priv->sysclk_rate = 147456000U;
break;
case 11025:
case 22050:
case 44100:
case 88200:
case 176400:
/* Highest possible SYSCLK frequency: 135.4752 MHz */
priv->sysclk_rate = 135475200U;
break;
default:
dev_err(component->dev, "Not supported sample rate: %d\n",
params_rate(params));
return -EINVAL;
}
return tm2_start_sysclk(rtd->card);
}
static const struct snd_soc_ops tm2_aif1_ops = {
.hw_params = tm2_aif1_hw_params,
};
static int tm2_aif2_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component;
unsigned int asyncclk_rate;
int ret;
switch (params_rate(params)) {
case 8000:
case 12000:
case 16000:
/* Highest possible ASYNCCLK frequency: 49.152MHz */
asyncclk_rate = 49152000U;
break;
case 11025:
/* Highest possible ASYNCCLK frequency: 45.1584 MHz */
asyncclk_rate = 45158400U;
break;
default:
dev_err(component->dev, "Not supported sample rate: %d\n",
params_rate(params));
return -EINVAL;
}
ret = snd_soc_component_set_pll(component, WM5110_FLL2_REFCLK,
ARIZONA_FLL_SRC_MCLK1,
MCLK_RATE,
asyncclk_rate);
if (ret < 0) {
dev_err(component->dev, "Failed to set FLL2 source: %d\n", ret);
return ret;
}
ret = snd_soc_component_set_pll(component, WM5110_FLL2,
ARIZONA_FLL_SRC_MCLK1,
MCLK_RATE,
asyncclk_rate);
if (ret < 0) {
dev_err(component->dev, "Failed to start FLL2: %d\n", ret);
return ret;
}
ret = snd_soc_component_set_sysclk(component, ARIZONA_CLK_ASYNCCLK,
ARIZONA_CLK_SRC_FLL2,
asyncclk_rate,
SND_SOC_CLOCK_IN);
if (ret < 0) {
dev_err(component->dev, "Failed to set ASYNCCLK source: %d\n", ret);
return ret;
}
return 0;
}
static int tm2_aif2_hw_free(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component;
int ret;
/* disable FLL2 */
ret = snd_soc_component_set_pll(component, WM5110_FLL2, ARIZONA_FLL_SRC_MCLK1,
0, 0);
if (ret < 0)
dev_err(component->dev, "Failed to stop FLL2: %d\n", ret);
return ret;
}
static const struct snd_soc_ops tm2_aif2_ops = {
.hw_params = tm2_aif2_hw_params,
.hw_free = tm2_aif2_hw_free,
};
static int tm2_hdmi_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
unsigned int bfs;
int bitwidth, ret;
bitwidth = snd_pcm_format_width(params_format(params));
if (bitwidth < 0) {
dev_err(rtd->card->dev, "Invalid bit-width: %d\n", bitwidth);
return bitwidth;
}
switch (bitwidth) {
case 48:
bfs = 64;
break;
case 16:
bfs = 32;
break;
default:
dev_err(rtd->card->dev, "Unsupported bit-width: %d\n", bitwidth);
return -EINVAL;
}
switch (params_rate(params)) {
case 48000:
case 96000:
case 192000:
break;
default:
dev_err(rtd->card->dev, "Unsupported sample rate: %d\n",
params_rate(params));
return -EINVAL;
}
ret = snd_soc_dai_set_sysclk(cpu_dai, SAMSUNG_I2S_OPCLK,
0, SAMSUNG_I2S_OPCLK_PCLK);
if (ret < 0)
return ret;
ret = snd_soc_dai_set_clkdiv(cpu_dai, SAMSUNG_I2S_DIV_BCLK, bfs);
if (ret < 0)
return ret;
return 0;
}
static const struct snd_soc_ops tm2_hdmi_ops = {
.hw_params = tm2_hdmi_hw_params,
};
static int tm2_mic_bias(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_card *card = w->dapm->card;
struct tm2_machine_priv *priv = snd_soc_card_get_drvdata(card);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
gpiod_set_value_cansleep(priv->gpio_mic_bias, 1);
break;
case SND_SOC_DAPM_POST_PMD:
gpiod_set_value_cansleep(priv->gpio_mic_bias, 0);
break;
}
return 0;
}
static int tm2_set_bias_level(struct snd_soc_card *card,
struct snd_soc_dapm_context *dapm,
enum snd_soc_bias_level level)
{
struct snd_soc_pcm_runtime *rtd;
rtd = snd_soc_get_pcm_runtime(card, &card->dai_link[0]);
if (dapm->dev != asoc_rtd_to_codec(rtd, 0)->dev)
return 0;
switch (level) {
case SND_SOC_BIAS_STANDBY:
if (card->dapm.bias_level == SND_SOC_BIAS_OFF)
tm2_start_sysclk(card);
break;
case SND_SOC_BIAS_OFF:
tm2_stop_sysclk(card);
break;
default:
break;
}
return 0;
}
static struct snd_soc_aux_dev tm2_speaker_amp_dev;
static int tm2_late_probe(struct snd_soc_card *card)
{
struct tm2_machine_priv *priv = snd_soc_card_get_drvdata(card);
unsigned int ch_map[] = { 0, 1 };
struct snd_soc_dai *amp_pdm_dai;
struct snd_soc_pcm_runtime *rtd;
struct snd_soc_dai *aif1_dai;
struct snd_soc_dai *aif2_dai;
int ret;
rtd = snd_soc_get_pcm_runtime(card, &card->dai_link[TM2_DAI_AIF1]);
aif1_dai = asoc_rtd_to_codec(rtd, 0);
priv->component = asoc_rtd_to_codec(rtd, 0)->component;
ret = snd_soc_dai_set_sysclk(aif1_dai, ARIZONA_CLK_SYSCLK, 0, 0);
if (ret < 0) {
dev_err(aif1_dai->dev, "Failed to set SYSCLK: %d\n", ret);
return ret;
}
rtd = snd_soc_get_pcm_runtime(card, &card->dai_link[TM2_DAI_AIF2]);
aif2_dai = asoc_rtd_to_codec(rtd, 0);
ret = snd_soc_dai_set_sysclk(aif2_dai, ARIZONA_CLK_ASYNCCLK, 0, 0);
if (ret < 0) {
dev_err(aif2_dai->dev, "Failed to set ASYNCCLK: %d\n", ret);
return ret;
}
amp_pdm_dai = snd_soc_find_dai(&tm2_speaker_amp_dev.dlc);
if (!amp_pdm_dai)
return -ENODEV;
/* Set the MAX98504 V/I sense PDM Tx DAI channel mapping */
ret = snd_soc_dai_set_channel_map(amp_pdm_dai, ARRAY_SIZE(ch_map),
ch_map, 0, NULL);
if (ret < 0)
return ret;
ret = snd_soc_dai_set_tdm_slot(amp_pdm_dai, 0x3, 0x0, 2, 16);
if (ret < 0)
return ret;
return 0;
}
static const struct snd_kcontrol_new tm2_controls[] = {
SOC_DAPM_PIN_SWITCH("HP"),
SOC_DAPM_PIN_SWITCH("SPK"),
SOC_DAPM_PIN_SWITCH("RCV"),
SOC_DAPM_PIN_SWITCH("VPS"),
SOC_DAPM_PIN_SWITCH("HDMI"),
SOC_DAPM_PIN_SWITCH("Main Mic"),
SOC_DAPM_PIN_SWITCH("Sub Mic"),
SOC_DAPM_PIN_SWITCH("Third Mic"),
SOC_DAPM_PIN_SWITCH("Headset Mic"),
};
static const struct snd_soc_dapm_widget tm2_dapm_widgets[] = {
SND_SOC_DAPM_HP("HP", NULL),
SND_SOC_DAPM_SPK("SPK", NULL),
SND_SOC_DAPM_SPK("RCV", NULL),
SND_SOC_DAPM_LINE("VPS", NULL),
SND_SOC_DAPM_LINE("HDMI", NULL),
SND_SOC_DAPM_MIC("Main Mic", tm2_mic_bias),
SND_SOC_DAPM_MIC("Sub Mic", NULL),
SND_SOC_DAPM_MIC("Third Mic", NULL),
SND_SOC_DAPM_MIC("Headset Mic", NULL),
};
static const struct snd_soc_component_driver tm2_component = {
.name = "tm2-audio",
};
static struct snd_soc_dai_driver tm2_ext_dai[] = {
{
.name = "Voice call",
.playback = {
.channels_min = 1,
.channels_max = 4,
.rate_min = 8000,
.rate_max = 48000,
.rates = (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |
SNDRV_PCM_RATE_48000),
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.capture = {
.channels_min = 1,
.channels_max = 4,
.rate_min = 8000,
.rate_max = 48000,
.rates = (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |
SNDRV_PCM_RATE_48000),
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
},
{
.name = "Bluetooth",
.playback = {
.channels_min = 1,
.channels_max = 4,
.rate_min = 8000,
.rate_max = 16000,
.rates = (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000),
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.capture = {
.channels_min = 1,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 16000,
.rates = (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000),
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
},
};
SND_SOC_DAILINK_DEFS(aif1,
DAILINK_COMP_ARRAY(COMP_CPU(SAMSUNG_I2S_DAI)),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "wm5110-aif1")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(voice,
DAILINK_COMP_ARRAY(COMP_CPU(SAMSUNG_I2S_DAI)),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "wm5110-aif2")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(bt,
DAILINK_COMP_ARRAY(COMP_CPU(SAMSUNG_I2S_DAI)),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "wm5110-aif3")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(hdmi,
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
static struct snd_soc_dai_link tm2_dai_links[] = {
{
.name = "WM5110 AIF1",
.stream_name = "HiFi Primary",
.ops = &tm2_aif1_ops,
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBM_CFM,
SND_SOC_DAILINK_REG(aif1),
}, {
.name = "WM5110 Voice",
.stream_name = "Voice call",
.ops = &tm2_aif2_ops,
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBM_CFM,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(voice),
}, {
.name = "WM5110 BT",
.stream_name = "Bluetooth",
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBM_CFM,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(bt),
}, {
.name = "HDMI",
.stream_name = "i2s1",
.ops = &tm2_hdmi_ops,
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS,
SND_SOC_DAILINK_REG(hdmi),
}
};
static struct snd_soc_card tm2_card = {
.owner = THIS_MODULE,
.dai_link = tm2_dai_links,
.controls = tm2_controls,
.num_controls = ARRAY_SIZE(tm2_controls),
.dapm_widgets = tm2_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(tm2_dapm_widgets),
.aux_dev = &tm2_speaker_amp_dev,
.num_aux_devs = 1,
.late_probe = tm2_late_probe,
.set_bias_level = tm2_set_bias_level,
};
static int tm2_probe(struct platform_device *pdev)
{
struct device_node *cpu_dai_node[2] = {};
struct device_node *codec_dai_node[2] = {};
const char *cells_name = NULL;
struct device *dev = &pdev->dev;
struct snd_soc_card *card = &tm2_card;
struct tm2_machine_priv *priv;
struct snd_soc_dai_link *dai_link;
int num_codecs, ret, i;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
snd_soc_card_set_drvdata(card, priv);
card->dev = dev;
priv->gpio_mic_bias = devm_gpiod_get(dev, "mic-bias", GPIOD_OUT_HIGH);
if (IS_ERR(priv->gpio_mic_bias)) {
dev_err(dev, "Failed to get mic bias gpio\n");
return PTR_ERR(priv->gpio_mic_bias);
}
ret = snd_soc_of_parse_card_name(card, "model");
if (ret < 0) {
dev_err(dev, "Card name is not specified\n");
return ret;
}
ret = snd_soc_of_parse_audio_routing(card, "audio-routing");
if (ret < 0) {
/* Backwards compatible way */
ret = snd_soc_of_parse_audio_routing(card, "samsung,audio-routing");
if (ret < 0) {
dev_err(dev, "Audio routing is not specified or invalid\n");
return ret;
}
}
card->aux_dev[0].dlc.of_node = of_parse_phandle(dev->of_node,
"audio-amplifier", 0);
if (!card->aux_dev[0].dlc.of_node) {
dev_err(dev, "audio-amplifier property invalid or missing\n");
return -EINVAL;
}
num_codecs = of_count_phandle_with_args(dev->of_node, "audio-codec",
NULL);
/* Skip the HDMI link if not specified in DT */
if (num_codecs > 1) {
card->num_links = ARRAY_SIZE(tm2_dai_links);
cells_name = "#sound-dai-cells";
} else {
card->num_links = ARRAY_SIZE(tm2_dai_links) - 1;
}
for (i = 0; i < num_codecs; i++) {
struct of_phandle_args args;
ret = of_parse_phandle_with_args(dev->of_node, "i2s-controller",
cells_name, i, &args);
if (ret) {
dev_err(dev, "i2s-controller property parse error: %d\n", i);
ret = -EINVAL;
goto dai_node_put;
}
cpu_dai_node[i] = args.np;
codec_dai_node[i] = of_parse_phandle(dev->of_node,
"audio-codec", i);
if (!codec_dai_node[i]) {
dev_err(dev, "audio-codec property parse error\n");
ret = -EINVAL;
goto dai_node_put;
}
}
/* Initialize WM5110 - I2S and HDMI - I2S1 DAI links */
for_each_card_prelinks(card, i, dai_link) {
unsigned int dai_index = 0; /* WM5110 */
dai_link->cpus->name = NULL;
dai_link->platforms->name = NULL;
if (num_codecs > 1 && i == card->num_links - 1)
dai_index = 1; /* HDMI */
dai_link->codecs->of_node = codec_dai_node[dai_index];
dai_link->cpus->of_node = cpu_dai_node[dai_index];
dai_link->platforms->of_node = cpu_dai_node[dai_index];
}
if (num_codecs > 1) {
struct of_phandle_args args;
/* HDMI DAI link (I2S1) */
i = card->num_links - 1;
ret = of_parse_phandle_with_fixed_args(dev->of_node,
"audio-codec", 0, 1, &args);
if (ret) {
dev_err(dev, "audio-codec property parse error\n");
goto dai_node_put;
}
ret = snd_soc_get_dai_name(&args, &card->dai_link[i].codecs->dai_name);
if (ret) {
dev_err(dev, "Unable to get codec_dai_name\n");
goto dai_node_put;
}
}
ret = devm_snd_soc_register_component(dev, &tm2_component,
tm2_ext_dai, ARRAY_SIZE(tm2_ext_dai));
if (ret < 0) {
dev_err(dev, "Failed to register component: %d\n", ret);
goto dai_node_put;
}
ret = devm_snd_soc_register_card(dev, card);
if (ret < 0) {
dev_err_probe(dev, ret, "Failed to register card\n");
goto dai_node_put;
}
dai_node_put:
for (i = 0; i < num_codecs; i++) {
of_node_put(codec_dai_node[i]);
of_node_put(cpu_dai_node[i]);
}
of_node_put(card->aux_dev[0].dlc.of_node);
return ret;
}
static int tm2_pm_prepare(struct device *dev)
{
struct snd_soc_card *card = dev_get_drvdata(dev);
return tm2_stop_sysclk(card);
}
static void tm2_pm_complete(struct device *dev)
{
struct snd_soc_card *card = dev_get_drvdata(dev);
tm2_start_sysclk(card);
}
static const struct dev_pm_ops tm2_pm_ops = {
.prepare = tm2_pm_prepare,
.suspend = snd_soc_suspend,
.resume = snd_soc_resume,
.complete = tm2_pm_complete,
.freeze = snd_soc_suspend,
.thaw = snd_soc_resume,
.poweroff = snd_soc_poweroff,
.restore = snd_soc_resume,
};
static const struct of_device_id tm2_of_match[] = {
{ .compatible = "samsung,tm2-audio" },
{ },
};
MODULE_DEVICE_TABLE(of, tm2_of_match);
static struct platform_driver tm2_driver = {
.driver = {
.name = "tm2-audio",
.pm = &tm2_pm_ops,
.of_match_table = tm2_of_match,
},
.probe = tm2_probe,
};
module_platform_driver(tm2_driver);
MODULE_AUTHOR("Inha Song <[email protected]>");
MODULE_DESCRIPTION("ALSA SoC Exynos TM2 Audio Support");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/samsung/tm2_wm5110.c |
// SPDX-License-Identifier: GPL-2.0+
#include "../codecs/wm8994.h"
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
/*
* Default CFG switch settings to use this driver:
* SMDKV310: CFG5-1000, CFG7-111111
*/
/*
* Configure audio route as :-
* $ amixer sset 'DAC1' on,on
* $ amixer sset 'Right Headphone Mux' 'DAC'
* $ amixer sset 'Left Headphone Mux' 'DAC'
* $ amixer sset 'DAC1R Mixer AIF1.1' on
* $ amixer sset 'DAC1L Mixer AIF1.1' on
* $ amixer sset 'IN2L' on
* $ amixer sset 'IN2L PGA IN2LN' on
* $ amixer sset 'MIXINL IN2L' on
* $ amixer sset 'AIF1ADC1L Mixer ADC/DMIC' on
* $ amixer sset 'IN2R' on
* $ amixer sset 'IN2R PGA IN2RN' on
* $ amixer sset 'MIXINR IN2R' on
* $ amixer sset 'AIF1ADC1R Mixer ADC/DMIC' on
*/
/* SMDK has a 16.934MHZ crystal attached to WM8994 */
#define SMDK_WM8994_FREQ 16934000
struct smdk_wm8994_data {
int mclk1_rate;
};
/* Default SMDKs */
static struct smdk_wm8994_data smdk_board_data = {
.mclk1_rate = SMDK_WM8994_FREQ,
};
static int smdk_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
unsigned int pll_out;
int ret;
/* AIF1CLK should be >=3MHz for optimal performance */
if (params_width(params) == 24)
pll_out = params_rate(params) * 384;
else if (params_rate(params) == 8000 || params_rate(params) == 11025)
pll_out = params_rate(params) * 512;
else
pll_out = params_rate(params) * 256;
ret = snd_soc_dai_set_pll(codec_dai, WM8994_FLL1, WM8994_FLL_SRC_MCLK1,
SMDK_WM8994_FREQ, pll_out);
if (ret < 0)
return ret;
ret = snd_soc_dai_set_sysclk(codec_dai, WM8994_SYSCLK_FLL1,
pll_out, SND_SOC_CLOCK_IN);
if (ret < 0)
return ret;
return 0;
}
/*
* SMDK WM8994 DAI operations.
*/
static const struct snd_soc_ops smdk_ops = {
.hw_params = smdk_hw_params,
};
static int smdk_wm8994_init_paiftx(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_dapm_context *dapm = &rtd->card->dapm;
/* Other pins NC */
snd_soc_dapm_nc_pin(dapm, "HPOUT2P");
snd_soc_dapm_nc_pin(dapm, "HPOUT2N");
snd_soc_dapm_nc_pin(dapm, "SPKOUTLN");
snd_soc_dapm_nc_pin(dapm, "SPKOUTLP");
snd_soc_dapm_nc_pin(dapm, "SPKOUTRP");
snd_soc_dapm_nc_pin(dapm, "SPKOUTRN");
snd_soc_dapm_nc_pin(dapm, "LINEOUT1N");
snd_soc_dapm_nc_pin(dapm, "LINEOUT1P");
snd_soc_dapm_nc_pin(dapm, "LINEOUT2N");
snd_soc_dapm_nc_pin(dapm, "LINEOUT2P");
snd_soc_dapm_nc_pin(dapm, "IN1LP");
snd_soc_dapm_nc_pin(dapm, "IN2LP:VXRN");
snd_soc_dapm_nc_pin(dapm, "IN1RP");
snd_soc_dapm_nc_pin(dapm, "IN2RP:VXRP");
return 0;
}
SND_SOC_DAILINK_DEFS(aif1,
DAILINK_COMP_ARRAY(COMP_CPU("samsung-i2s.0")),
DAILINK_COMP_ARRAY(COMP_CODEC("wm8994-codec", "wm8994-aif1")),
DAILINK_COMP_ARRAY(COMP_PLATFORM("samsung-i2s.0")));
SND_SOC_DAILINK_DEFS(fifo_tx,
DAILINK_COMP_ARRAY(COMP_CPU("samsung-i2s-sec")),
DAILINK_COMP_ARRAY(COMP_CODEC("wm8994-codec", "wm8994-aif1")),
DAILINK_COMP_ARRAY(COMP_PLATFORM("samsung-i2s-sec")));
static struct snd_soc_dai_link smdk_dai[] = {
{ /* Primary DAI i/f */
.name = "WM8994 AIF1",
.stream_name = "Pri_Dai",
.init = smdk_wm8994_init_paiftx,
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBM_CFM,
.ops = &smdk_ops,
SND_SOC_DAILINK_REG(aif1),
}, { /* Sec_Fifo Playback i/f */
.name = "Sec_FIFO TX",
.stream_name = "Sec_Dai",
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBM_CFM,
.ops = &smdk_ops,
SND_SOC_DAILINK_REG(fifo_tx),
},
};
static struct snd_soc_card smdk = {
.name = "SMDK-I2S",
.owner = THIS_MODULE,
.dai_link = smdk_dai,
.num_links = ARRAY_SIZE(smdk_dai),
};
static const struct of_device_id samsung_wm8994_of_match[] __maybe_unused = {
{ .compatible = "samsung,smdk-wm8994", .data = &smdk_board_data },
{},
};
MODULE_DEVICE_TABLE(of, samsung_wm8994_of_match);
static int smdk_audio_probe(struct platform_device *pdev)
{
int ret;
struct device_node *np = pdev->dev.of_node;
struct snd_soc_card *card = &smdk;
struct smdk_wm8994_data *board;
const struct of_device_id *id;
card->dev = &pdev->dev;
board = devm_kzalloc(&pdev->dev, sizeof(*board), GFP_KERNEL);
if (!board)
return -ENOMEM;
if (np) {
smdk_dai[0].cpus->dai_name = NULL;
smdk_dai[0].cpus->of_node = of_parse_phandle(np,
"samsung,i2s-controller", 0);
if (!smdk_dai[0].cpus->of_node) {
dev_err(&pdev->dev,
"Property 'samsung,i2s-controller' missing or invalid\n");
ret = -EINVAL;
return ret;
}
smdk_dai[0].platforms->name = NULL;
smdk_dai[0].platforms->of_node = smdk_dai[0].cpus->of_node;
}
id = of_match_device(samsung_wm8994_of_match, &pdev->dev);
if (id)
*board = *((struct smdk_wm8994_data *)id->data);
platform_set_drvdata(pdev, board);
ret = devm_snd_soc_register_card(&pdev->dev, card);
if (ret)
dev_err_probe(&pdev->dev, ret, "snd_soc_register_card() failed\n");
return ret;
}
static struct platform_driver smdk_audio_driver = {
.driver = {
.name = "smdk-audio-wm8994",
.of_match_table = of_match_ptr(samsung_wm8994_of_match),
.pm = &snd_soc_pm_ops,
},
.probe = smdk_audio_probe,
};
module_platform_driver(smdk_audio_driver);
MODULE_DESCRIPTION("ALSA SoC SMDK WM8994");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:smdk-audio-wm8994");
| linux-master | sound/soc/samsung/smdk_wm8994.c |
// SPDX-License-Identifier: GPL-2.0
//
// ALSA SoC Audio Layer - S3C PCM-Controller driver
//
// Copyright (c) 2009 Samsung Electronics Co. Ltd
// Author: Jaswinder Singh <[email protected]>
// based upon I2S drivers by Ben Dooks.
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include <sound/soc.h>
#include <sound/pcm_params.h>
#include <linux/platform_data/asoc-s3c.h>
#include "dma.h"
#include "pcm.h"
/*Register Offsets */
#define S3C_PCM_CTL 0x00
#define S3C_PCM_CLKCTL 0x04
#define S3C_PCM_TXFIFO 0x08
#define S3C_PCM_RXFIFO 0x0C
#define S3C_PCM_IRQCTL 0x10
#define S3C_PCM_IRQSTAT 0x14
#define S3C_PCM_FIFOSTAT 0x18
#define S3C_PCM_CLRINT 0x20
/* PCM_CTL Bit-Fields */
#define S3C_PCM_CTL_TXDIPSTICK_MASK 0x3f
#define S3C_PCM_CTL_TXDIPSTICK_SHIFT 13
#define S3C_PCM_CTL_RXDIPSTICK_MASK 0x3f
#define S3C_PCM_CTL_RXDIPSTICK_SHIFT 7
#define S3C_PCM_CTL_TXDMA_EN (0x1 << 6)
#define S3C_PCM_CTL_RXDMA_EN (0x1 << 5)
#define S3C_PCM_CTL_TXMSB_AFTER_FSYNC (0x1 << 4)
#define S3C_PCM_CTL_RXMSB_AFTER_FSYNC (0x1 << 3)
#define S3C_PCM_CTL_TXFIFO_EN (0x1 << 2)
#define S3C_PCM_CTL_RXFIFO_EN (0x1 << 1)
#define S3C_PCM_CTL_ENABLE (0x1 << 0)
/* PCM_CLKCTL Bit-Fields */
#define S3C_PCM_CLKCTL_SERCLK_EN (0x1 << 19)
#define S3C_PCM_CLKCTL_SERCLKSEL_PCLK (0x1 << 18)
#define S3C_PCM_CLKCTL_SCLKDIV_MASK 0x1ff
#define S3C_PCM_CLKCTL_SYNCDIV_MASK 0x1ff
#define S3C_PCM_CLKCTL_SCLKDIV_SHIFT 9
#define S3C_PCM_CLKCTL_SYNCDIV_SHIFT 0
/* PCM_TXFIFO Bit-Fields */
#define S3C_PCM_TXFIFO_DVALID (0x1 << 16)
#define S3C_PCM_TXFIFO_DATA_MSK (0xffff << 0)
/* PCM_RXFIFO Bit-Fields */
#define S3C_PCM_RXFIFO_DVALID (0x1 << 16)
#define S3C_PCM_RXFIFO_DATA_MSK (0xffff << 0)
/* PCM_IRQCTL Bit-Fields */
#define S3C_PCM_IRQCTL_IRQEN (0x1 << 14)
#define S3C_PCM_IRQCTL_WRDEN (0x1 << 12)
#define S3C_PCM_IRQCTL_TXEMPTYEN (0x1 << 11)
#define S3C_PCM_IRQCTL_TXALMSTEMPTYEN (0x1 << 10)
#define S3C_PCM_IRQCTL_TXFULLEN (0x1 << 9)
#define S3C_PCM_IRQCTL_TXALMSTFULLEN (0x1 << 8)
#define S3C_PCM_IRQCTL_TXSTARVEN (0x1 << 7)
#define S3C_PCM_IRQCTL_TXERROVRFLEN (0x1 << 6)
#define S3C_PCM_IRQCTL_RXEMPTEN (0x1 << 5)
#define S3C_PCM_IRQCTL_RXALMSTEMPTEN (0x1 << 4)
#define S3C_PCM_IRQCTL_RXFULLEN (0x1 << 3)
#define S3C_PCM_IRQCTL_RXALMSTFULLEN (0x1 << 2)
#define S3C_PCM_IRQCTL_RXSTARVEN (0x1 << 1)
#define S3C_PCM_IRQCTL_RXERROVRFLEN (0x1 << 0)
/* PCM_IRQSTAT Bit-Fields */
#define S3C_PCM_IRQSTAT_IRQPND (0x1 << 13)
#define S3C_PCM_IRQSTAT_WRD_XFER (0x1 << 12)
#define S3C_PCM_IRQSTAT_TXEMPTY (0x1 << 11)
#define S3C_PCM_IRQSTAT_TXALMSTEMPTY (0x1 << 10)
#define S3C_PCM_IRQSTAT_TXFULL (0x1 << 9)
#define S3C_PCM_IRQSTAT_TXALMSTFULL (0x1 << 8)
#define S3C_PCM_IRQSTAT_TXSTARV (0x1 << 7)
#define S3C_PCM_IRQSTAT_TXERROVRFL (0x1 << 6)
#define S3C_PCM_IRQSTAT_RXEMPT (0x1 << 5)
#define S3C_PCM_IRQSTAT_RXALMSTEMPT (0x1 << 4)
#define S3C_PCM_IRQSTAT_RXFULL (0x1 << 3)
#define S3C_PCM_IRQSTAT_RXALMSTFULL (0x1 << 2)
#define S3C_PCM_IRQSTAT_RXSTARV (0x1 << 1)
#define S3C_PCM_IRQSTAT_RXERROVRFL (0x1 << 0)
/* PCM_FIFOSTAT Bit-Fields */
#define S3C_PCM_FIFOSTAT_TXCNT_MSK (0x3f << 14)
#define S3C_PCM_FIFOSTAT_TXFIFOEMPTY (0x1 << 13)
#define S3C_PCM_FIFOSTAT_TXFIFOALMSTEMPTY (0x1 << 12)
#define S3C_PCM_FIFOSTAT_TXFIFOFULL (0x1 << 11)
#define S3C_PCM_FIFOSTAT_TXFIFOALMSTFULL (0x1 << 10)
#define S3C_PCM_FIFOSTAT_RXCNT_MSK (0x3f << 4)
#define S3C_PCM_FIFOSTAT_RXFIFOEMPTY (0x1 << 3)
#define S3C_PCM_FIFOSTAT_RXFIFOALMSTEMPTY (0x1 << 2)
#define S3C_PCM_FIFOSTAT_RXFIFOFULL (0x1 << 1)
#define S3C_PCM_FIFOSTAT_RXFIFOALMSTFULL (0x1 << 0)
/**
* struct s3c_pcm_info - S3C PCM Controller information
* @lock: Spin lock
* @dev: The parent device passed to use from the probe.
* @regs: The pointer to the device register block.
* @sclk_per_fs: number of sclk per frame sync
* @idleclk: Whether to keep PCMSCLK enabled even when idle (no active xfer)
* @pclk: the PCLK_PCM (pcm) clock pointer
* @cclk: the SCLK_AUDIO (audio-bus) clock pointer
* @dma_playback: DMA information for playback channel.
* @dma_capture: DMA information for capture channel.
*/
struct s3c_pcm_info {
spinlock_t lock;
struct device *dev;
void __iomem *regs;
unsigned int sclk_per_fs;
/* Whether to keep PCMSCLK enabled even when idle(no active xfer) */
unsigned int idleclk;
struct clk *pclk;
struct clk *cclk;
struct snd_dmaengine_dai_dma_data *dma_playback;
struct snd_dmaengine_dai_dma_data *dma_capture;
};
static struct snd_dmaengine_dai_dma_data s3c_pcm_stereo_out[] = {
[0] = {
.addr_width = 4,
},
[1] = {
.addr_width = 4,
},
};
static struct snd_dmaengine_dai_dma_data s3c_pcm_stereo_in[] = {
[0] = {
.addr_width = 4,
},
[1] = {
.addr_width = 4,
},
};
static struct s3c_pcm_info s3c_pcm[2];
static void s3c_pcm_snd_txctrl(struct s3c_pcm_info *pcm, int on)
{
void __iomem *regs = pcm->regs;
u32 ctl, clkctl;
clkctl = readl(regs + S3C_PCM_CLKCTL);
ctl = readl(regs + S3C_PCM_CTL);
ctl &= ~(S3C_PCM_CTL_TXDIPSTICK_MASK
<< S3C_PCM_CTL_TXDIPSTICK_SHIFT);
if (on) {
ctl |= S3C_PCM_CTL_TXDMA_EN;
ctl |= S3C_PCM_CTL_TXFIFO_EN;
ctl |= S3C_PCM_CTL_ENABLE;
ctl |= (0x4<<S3C_PCM_CTL_TXDIPSTICK_SHIFT);
clkctl |= S3C_PCM_CLKCTL_SERCLK_EN;
} else {
ctl &= ~S3C_PCM_CTL_TXDMA_EN;
ctl &= ~S3C_PCM_CTL_TXFIFO_EN;
if (!(ctl & S3C_PCM_CTL_RXFIFO_EN)) {
ctl &= ~S3C_PCM_CTL_ENABLE;
if (!pcm->idleclk)
clkctl |= S3C_PCM_CLKCTL_SERCLK_EN;
}
}
writel(clkctl, regs + S3C_PCM_CLKCTL);
writel(ctl, regs + S3C_PCM_CTL);
}
static void s3c_pcm_snd_rxctrl(struct s3c_pcm_info *pcm, int on)
{
void __iomem *regs = pcm->regs;
u32 ctl, clkctl;
ctl = readl(regs + S3C_PCM_CTL);
clkctl = readl(regs + S3C_PCM_CLKCTL);
ctl &= ~(S3C_PCM_CTL_RXDIPSTICK_MASK
<< S3C_PCM_CTL_RXDIPSTICK_SHIFT);
if (on) {
ctl |= S3C_PCM_CTL_RXDMA_EN;
ctl |= S3C_PCM_CTL_RXFIFO_EN;
ctl |= S3C_PCM_CTL_ENABLE;
ctl |= (0x20<<S3C_PCM_CTL_RXDIPSTICK_SHIFT);
clkctl |= S3C_PCM_CLKCTL_SERCLK_EN;
} else {
ctl &= ~S3C_PCM_CTL_RXDMA_EN;
ctl &= ~S3C_PCM_CTL_RXFIFO_EN;
if (!(ctl & S3C_PCM_CTL_TXFIFO_EN)) {
ctl &= ~S3C_PCM_CTL_ENABLE;
if (!pcm->idleclk)
clkctl |= S3C_PCM_CLKCTL_SERCLK_EN;
}
}
writel(clkctl, regs + S3C_PCM_CLKCTL);
writel(ctl, regs + S3C_PCM_CTL);
}
static int s3c_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct s3c_pcm_info *pcm = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
unsigned long flags;
dev_dbg(pcm->dev, "Entered %s\n", __func__);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
spin_lock_irqsave(&pcm->lock, flags);
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
s3c_pcm_snd_rxctrl(pcm, 1);
else
s3c_pcm_snd_txctrl(pcm, 1);
spin_unlock_irqrestore(&pcm->lock, flags);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
spin_lock_irqsave(&pcm->lock, flags);
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
s3c_pcm_snd_rxctrl(pcm, 0);
else
s3c_pcm_snd_txctrl(pcm, 0);
spin_unlock_irqrestore(&pcm->lock, flags);
break;
default:
return -EINVAL;
}
return 0;
}
static int s3c_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *socdai)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct s3c_pcm_info *pcm = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
void __iomem *regs = pcm->regs;
struct clk *clk;
int sclk_div, sync_div;
unsigned long flags;
u32 clkctl;
dev_dbg(pcm->dev, "Entered %s\n", __func__);
/* Strictly check for sample size */
switch (params_width(params)) {
case 16:
break;
default:
return -EINVAL;
}
spin_lock_irqsave(&pcm->lock, flags);
/* Get hold of the PCMSOURCE_CLK */
clkctl = readl(regs + S3C_PCM_CLKCTL);
if (clkctl & S3C_PCM_CLKCTL_SERCLKSEL_PCLK)
clk = pcm->pclk;
else
clk = pcm->cclk;
/* Set the SCLK divider */
sclk_div = clk_get_rate(clk) / pcm->sclk_per_fs /
params_rate(params) / 2 - 1;
clkctl &= ~(S3C_PCM_CLKCTL_SCLKDIV_MASK
<< S3C_PCM_CLKCTL_SCLKDIV_SHIFT);
clkctl |= ((sclk_div & S3C_PCM_CLKCTL_SCLKDIV_MASK)
<< S3C_PCM_CLKCTL_SCLKDIV_SHIFT);
/* Set the SYNC divider */
sync_div = pcm->sclk_per_fs - 1;
clkctl &= ~(S3C_PCM_CLKCTL_SYNCDIV_MASK
<< S3C_PCM_CLKCTL_SYNCDIV_SHIFT);
clkctl |= ((sync_div & S3C_PCM_CLKCTL_SYNCDIV_MASK)
<< S3C_PCM_CLKCTL_SYNCDIV_SHIFT);
writel(clkctl, regs + S3C_PCM_CLKCTL);
spin_unlock_irqrestore(&pcm->lock, flags);
dev_dbg(pcm->dev, "PCMSOURCE_CLK-%lu SCLK=%ufs SCLK_DIV=%d SYNC_DIV=%d\n",
clk_get_rate(clk), pcm->sclk_per_fs,
sclk_div, sync_div);
return 0;
}
static int s3c_pcm_set_fmt(struct snd_soc_dai *cpu_dai,
unsigned int fmt)
{
struct s3c_pcm_info *pcm = snd_soc_dai_get_drvdata(cpu_dai);
void __iomem *regs = pcm->regs;
unsigned long flags;
int ret = 0;
u32 ctl;
dev_dbg(pcm->dev, "Entered %s\n", __func__);
spin_lock_irqsave(&pcm->lock, flags);
ctl = readl(regs + S3C_PCM_CTL);
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_IB_NF:
/* Nothing to do, IB_NF by default */
break;
default:
dev_err(pcm->dev, "Unsupported clock inversion!\n");
ret = -EINVAL;
goto exit;
}
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BP_FP:
/* Nothing to do, Master by default */
break;
default:
dev_err(pcm->dev, "Unsupported master/slave format!\n");
ret = -EINVAL;
goto exit;
}
switch (fmt & SND_SOC_DAIFMT_CLOCK_MASK) {
case SND_SOC_DAIFMT_CONT:
pcm->idleclk = 1;
break;
case SND_SOC_DAIFMT_GATED:
pcm->idleclk = 0;
break;
default:
dev_err(pcm->dev, "Invalid Clock gating request!\n");
ret = -EINVAL;
goto exit;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
ctl |= S3C_PCM_CTL_TXMSB_AFTER_FSYNC;
ctl |= S3C_PCM_CTL_RXMSB_AFTER_FSYNC;
break;
case SND_SOC_DAIFMT_DSP_B:
ctl &= ~S3C_PCM_CTL_TXMSB_AFTER_FSYNC;
ctl &= ~S3C_PCM_CTL_RXMSB_AFTER_FSYNC;
break;
default:
dev_err(pcm->dev, "Unsupported data format!\n");
ret = -EINVAL;
goto exit;
}
writel(ctl, regs + S3C_PCM_CTL);
exit:
spin_unlock_irqrestore(&pcm->lock, flags);
return ret;
}
static int s3c_pcm_set_clkdiv(struct snd_soc_dai *cpu_dai,
int div_id, int div)
{
struct s3c_pcm_info *pcm = snd_soc_dai_get_drvdata(cpu_dai);
switch (div_id) {
case S3C_PCM_SCLK_PER_FS:
pcm->sclk_per_fs = div;
break;
default:
return -EINVAL;
}
return 0;
}
static int s3c_pcm_set_sysclk(struct snd_soc_dai *cpu_dai,
int clk_id, unsigned int freq, int dir)
{
struct s3c_pcm_info *pcm = snd_soc_dai_get_drvdata(cpu_dai);
void __iomem *regs = pcm->regs;
u32 clkctl = readl(regs + S3C_PCM_CLKCTL);
switch (clk_id) {
case S3C_PCM_CLKSRC_PCLK:
clkctl |= S3C_PCM_CLKCTL_SERCLKSEL_PCLK;
break;
case S3C_PCM_CLKSRC_MUX:
clkctl &= ~S3C_PCM_CLKCTL_SERCLKSEL_PCLK;
if (clk_get_rate(pcm->cclk) != freq)
clk_set_rate(pcm->cclk, freq);
break;
default:
return -EINVAL;
}
writel(clkctl, regs + S3C_PCM_CLKCTL);
return 0;
}
static int s3c_pcm_dai_probe(struct snd_soc_dai *dai)
{
struct s3c_pcm_info *pcm = snd_soc_dai_get_drvdata(dai);
snd_soc_dai_init_dma_data(dai, pcm->dma_playback, pcm->dma_capture);
return 0;
}
static const struct snd_soc_dai_ops s3c_pcm_dai_ops = {
.probe = s3c_pcm_dai_probe,
.set_sysclk = s3c_pcm_set_sysclk,
.set_clkdiv = s3c_pcm_set_clkdiv,
.trigger = s3c_pcm_trigger,
.hw_params = s3c_pcm_hw_params,
.set_fmt = s3c_pcm_set_fmt,
};
#define S3C_PCM_RATES SNDRV_PCM_RATE_8000_96000
#define S3C_PCM_DAI_DECLARE \
.symmetric_rate = 1, \
.ops = &s3c_pcm_dai_ops, \
.playback = { \
.channels_min = 2, \
.channels_max = 2, \
.rates = S3C_PCM_RATES, \
.formats = SNDRV_PCM_FMTBIT_S16_LE, \
}, \
.capture = { \
.channels_min = 2, \
.channels_max = 2, \
.rates = S3C_PCM_RATES, \
.formats = SNDRV_PCM_FMTBIT_S16_LE, \
}
static struct snd_soc_dai_driver s3c_pcm_dai[] = {
[0] = {
.name = "samsung-pcm.0",
S3C_PCM_DAI_DECLARE,
},
[1] = {
.name = "samsung-pcm.1",
S3C_PCM_DAI_DECLARE,
},
};
static const struct snd_soc_component_driver s3c_pcm_component = {
.name = "s3c-pcm",
.legacy_dai_naming = 1,
};
static int s3c_pcm_dev_probe(struct platform_device *pdev)
{
struct s3c_pcm_info *pcm;
struct resource *mem_res;
struct s3c_audio_pdata *pcm_pdata;
dma_filter_fn filter;
int ret;
/* Check for valid device index */
if ((pdev->id < 0) || pdev->id >= ARRAY_SIZE(s3c_pcm)) {
dev_err(&pdev->dev, "id %d out of range\n", pdev->id);
return -EINVAL;
}
pcm_pdata = pdev->dev.platform_data;
if (pcm_pdata && pcm_pdata->cfg_gpio && pcm_pdata->cfg_gpio(pdev)) {
dev_err(&pdev->dev, "Unable to configure gpio\n");
return -EINVAL;
}
pcm = &s3c_pcm[pdev->id];
pcm->dev = &pdev->dev;
spin_lock_init(&pcm->lock);
/* Default is 128fs */
pcm->sclk_per_fs = 128;
pcm->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem_res);
if (IS_ERR(pcm->regs))
return PTR_ERR(pcm->regs);
pcm->cclk = devm_clk_get(&pdev->dev, "audio-bus");
if (IS_ERR(pcm->cclk)) {
dev_err(&pdev->dev, "failed to get audio-bus clock\n");
return PTR_ERR(pcm->cclk);
}
ret = clk_prepare_enable(pcm->cclk);
if (ret)
return ret;
/* record our pcm structure for later use in the callbacks */
dev_set_drvdata(&pdev->dev, pcm);
pcm->pclk = devm_clk_get(&pdev->dev, "pcm");
if (IS_ERR(pcm->pclk)) {
dev_err(&pdev->dev, "failed to get pcm clock\n");
ret = PTR_ERR(pcm->pclk);
goto err_dis_cclk;
}
ret = clk_prepare_enable(pcm->pclk);
if (ret)
goto err_dis_cclk;
s3c_pcm_stereo_in[pdev->id].addr = mem_res->start + S3C_PCM_RXFIFO;
s3c_pcm_stereo_out[pdev->id].addr = mem_res->start + S3C_PCM_TXFIFO;
filter = NULL;
if (pcm_pdata) {
s3c_pcm_stereo_in[pdev->id].filter_data = pcm_pdata->dma_capture;
s3c_pcm_stereo_out[pdev->id].filter_data = pcm_pdata->dma_playback;
filter = pcm_pdata->dma_filter;
}
pcm->dma_capture = &s3c_pcm_stereo_in[pdev->id];
pcm->dma_playback = &s3c_pcm_stereo_out[pdev->id];
ret = samsung_asoc_dma_platform_register(&pdev->dev, filter,
NULL, NULL, NULL);
if (ret) {
dev_err(&pdev->dev, "failed to get register DMA: %d\n", ret);
goto err_dis_pclk;
}
pm_runtime_enable(&pdev->dev);
ret = devm_snd_soc_register_component(&pdev->dev, &s3c_pcm_component,
&s3c_pcm_dai[pdev->id], 1);
if (ret != 0) {
dev_err(&pdev->dev, "failed to get register DAI: %d\n", ret);
goto err_dis_pm;
}
return 0;
err_dis_pm:
pm_runtime_disable(&pdev->dev);
err_dis_pclk:
clk_disable_unprepare(pcm->pclk);
err_dis_cclk:
clk_disable_unprepare(pcm->cclk);
return ret;
}
static void s3c_pcm_dev_remove(struct platform_device *pdev)
{
struct s3c_pcm_info *pcm = &s3c_pcm[pdev->id];
pm_runtime_disable(&pdev->dev);
clk_disable_unprepare(pcm->cclk);
clk_disable_unprepare(pcm->pclk);
}
static struct platform_driver s3c_pcm_driver = {
.probe = s3c_pcm_dev_probe,
.remove_new = s3c_pcm_dev_remove,
.driver = {
.name = "samsung-pcm",
},
};
module_platform_driver(s3c_pcm_driver);
/* Module information */
MODULE_AUTHOR("Jaswinder Singh, <[email protected]>");
MODULE_DESCRIPTION("S3C PCM Controller Driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:samsung-pcm");
| linux-master | sound/soc/samsung/pcm.c |
// SPDX-License-Identifier: GPL-2.0+
//
// Midas audio support
//
// Copyright (C) 2018 Simon Shields <[email protected]>
// Copyright (C) 2020 Samsung Electronics Co., Ltd.
#include <linux/clk.h>
#include <linux/gpio/consumer.h>
#include <linux/mfd/wm8994/registers.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/regulator/consumer.h>
#include <sound/jack.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include "i2s.h"
#include "../codecs/wm8994.h"
/*
* The MCLK1 clock source is XCLKOUT with its mux set to the external fixed rate
* oscillator (XXTI).
*/
#define MCLK1_RATE 24000000U
#define MCLK2_RATE 32768U
#define DEFAULT_FLL1_RATE 11289600U
struct midas_priv {
struct regulator *reg_mic_bias;
struct regulator *reg_submic_bias;
struct gpio_desc *gpio_fm_sel;
struct gpio_desc *gpio_lineout_sel;
unsigned int fll1_rate;
struct snd_soc_jack headset_jack;
};
static struct snd_soc_jack_pin headset_jack_pins[] = {
{
.pin = "Headphone",
.mask = SND_JACK_HEADPHONE,
},
{
.pin = "Headset Mic",
.mask = SND_JACK_MICROPHONE,
},
};
static int midas_start_fll1(struct snd_soc_pcm_runtime *rtd, unsigned int rate)
{
struct snd_soc_card *card = rtd->card;
struct midas_priv *priv = snd_soc_card_get_drvdata(card);
struct snd_soc_dai *aif1_dai = asoc_rtd_to_codec(rtd, 0);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
int ret;
if (!rate)
rate = priv->fll1_rate;
/*
* If no new rate is requested, set FLL1 to a sane default for jack
* detection.
*/
if (!rate)
rate = DEFAULT_FLL1_RATE;
if (rate != priv->fll1_rate && priv->fll1_rate) {
/* while reconfiguring, switch to MCLK2 for SYSCLK */
ret = snd_soc_dai_set_sysclk(aif1_dai, WM8994_SYSCLK_MCLK2,
MCLK2_RATE, SND_SOC_CLOCK_IN);
if (ret < 0) {
dev_err(card->dev, "Unable to switch to MCLK2: %d\n", ret);
return ret;
}
}
ret = snd_soc_dai_set_pll(aif1_dai, WM8994_FLL1, WM8994_FLL_SRC_MCLK1,
MCLK1_RATE, rate);
if (ret < 0) {
dev_err(card->dev, "Failed to set FLL1 rate: %d\n", ret);
return ret;
}
priv->fll1_rate = rate;
ret = snd_soc_dai_set_sysclk(aif1_dai, WM8994_SYSCLK_FLL1,
priv->fll1_rate, SND_SOC_CLOCK_IN);
if (ret < 0) {
dev_err(card->dev, "Failed to set SYSCLK source: %d\n", ret);
return ret;
}
ret = snd_soc_dai_set_sysclk(cpu_dai, SAMSUNG_I2S_OPCLK, 0,
SAMSUNG_I2S_OPCLK_PCLK);
if (ret < 0) {
dev_err(card->dev, "Failed to set OPCLK source: %d\n", ret);
return ret;
}
return 0;
}
static int midas_stop_fll1(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_card *card = rtd->card;
struct midas_priv *priv = snd_soc_card_get_drvdata(card);
struct snd_soc_dai *aif1_dai = asoc_rtd_to_codec(rtd, 0);
int ret;
ret = snd_soc_dai_set_sysclk(aif1_dai, WM8994_SYSCLK_MCLK2,
MCLK2_RATE, SND_SOC_CLOCK_IN);
if (ret < 0) {
dev_err(card->dev, "Unable to switch to MCLK2: %d\n", ret);
return ret;
}
ret = snd_soc_dai_set_pll(aif1_dai, WM8994_FLL1, 0, 0, 0);
if (ret < 0) {
dev_err(card->dev, "Unable to stop FLL1: %d\n", ret);
return ret;
}
priv->fll1_rate = 0;
return 0;
}
static int midas_aif1_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
unsigned int pll_out;
/* AIF1CLK should be at least 3MHz for "optimal performance" */
if (params_rate(params) == 8000 || params_rate(params) == 11025)
pll_out = params_rate(params) * 512;
else
pll_out = params_rate(params) * 256;
return midas_start_fll1(rtd, pll_out);
}
static const struct snd_soc_ops midas_aif1_ops = {
.hw_params = midas_aif1_hw_params,
};
/*
* We only have a single external speaker, so mix stereo data
* to a single mono stream.
*/
static int midas_ext_spkmode(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *codec = snd_soc_dapm_to_component(w->dapm);
int ret = 0;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
ret = snd_soc_component_update_bits(codec, WM8994_SPKOUT_MIXERS,
WM8994_SPKMIXR_TO_SPKOUTL_MASK,
WM8994_SPKMIXR_TO_SPKOUTL);
break;
case SND_SOC_DAPM_POST_PMD:
ret = snd_soc_component_update_bits(codec, WM8994_SPKOUT_MIXERS,
WM8994_SPKMIXR_TO_SPKOUTL_MASK,
0);
break;
}
return ret;
}
static int midas_mic_bias(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_card *card = w->dapm->card;
struct midas_priv *priv = snd_soc_card_get_drvdata(card);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
return regulator_enable(priv->reg_mic_bias);
case SND_SOC_DAPM_POST_PMD:
return regulator_disable(priv->reg_mic_bias);
}
return 0;
}
static int midas_submic_bias(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_card *card = w->dapm->card;
struct midas_priv *priv = snd_soc_card_get_drvdata(card);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
return regulator_enable(priv->reg_submic_bias);
case SND_SOC_DAPM_POST_PMD:
return regulator_disable(priv->reg_submic_bias);
}
return 0;
}
static int midas_fm_set(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_card *card = w->dapm->card;
struct midas_priv *priv = snd_soc_card_get_drvdata(card);
if (!priv->gpio_fm_sel)
return 0;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
gpiod_set_value_cansleep(priv->gpio_fm_sel, 1);
break;
case SND_SOC_DAPM_POST_PMD:
gpiod_set_value_cansleep(priv->gpio_fm_sel, 0);
break;
}
return 0;
}
static int midas_line_set(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_card *card = w->dapm->card;
struct midas_priv *priv = snd_soc_card_get_drvdata(card);
if (!priv->gpio_lineout_sel)
return 0;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
gpiod_set_value_cansleep(priv->gpio_lineout_sel, 1);
break;
case SND_SOC_DAPM_POST_PMD:
gpiod_set_value_cansleep(priv->gpio_lineout_sel, 0);
break;
}
return 0;
}
static const struct snd_kcontrol_new midas_controls[] = {
SOC_DAPM_PIN_SWITCH("HP"),
SOC_DAPM_PIN_SWITCH("SPK"),
SOC_DAPM_PIN_SWITCH("RCV"),
SOC_DAPM_PIN_SWITCH("LINE"),
SOC_DAPM_PIN_SWITCH("HDMI"),
SOC_DAPM_PIN_SWITCH("Main Mic"),
SOC_DAPM_PIN_SWITCH("Sub Mic"),
SOC_DAPM_PIN_SWITCH("Headset Mic"),
SOC_DAPM_PIN_SWITCH("FM In"),
};
static const struct snd_soc_dapm_widget midas_dapm_widgets[] = {
SND_SOC_DAPM_HP("HP", NULL),
SND_SOC_DAPM_SPK("SPK", midas_ext_spkmode),
SND_SOC_DAPM_SPK("RCV", NULL),
/* FIXME: toggle MAX77693 on i9300/i9305 */
SND_SOC_DAPM_LINE("LINE", midas_line_set),
SND_SOC_DAPM_LINE("HDMI", NULL),
SND_SOC_DAPM_LINE("FM In", midas_fm_set),
SND_SOC_DAPM_HP("Headphone", NULL),
SND_SOC_DAPM_MIC("Headset Mic", NULL),
SND_SOC_DAPM_MIC("Main Mic", midas_mic_bias),
SND_SOC_DAPM_MIC("Sub Mic", midas_submic_bias),
};
static int midas_set_bias_level(struct snd_soc_card *card,
struct snd_soc_dapm_context *dapm,
enum snd_soc_bias_level level)
{
struct snd_soc_pcm_runtime *rtd = snd_soc_get_pcm_runtime(card,
&card->dai_link[0]);
struct snd_soc_dai *aif1_dai = asoc_rtd_to_codec(rtd, 0);
if (dapm->dev != aif1_dai->dev)
return 0;
switch (level) {
case SND_SOC_BIAS_STANDBY:
return midas_stop_fll1(rtd);
case SND_SOC_BIAS_PREPARE:
return midas_start_fll1(rtd, 0);
default:
break;
}
return 0;
}
static int midas_late_probe(struct snd_soc_card *card)
{
struct snd_soc_pcm_runtime *rtd = snd_soc_get_pcm_runtime(card,
&card->dai_link[0]);
struct snd_soc_dai *aif1_dai = asoc_rtd_to_codec(rtd, 0);
struct midas_priv *priv = snd_soc_card_get_drvdata(card);
int ret;
/* Use MCLK2 as SYSCLK for boot */
ret = snd_soc_dai_set_sysclk(aif1_dai, WM8994_SYSCLK_MCLK2, MCLK2_RATE,
SND_SOC_CLOCK_IN);
if (ret < 0) {
dev_err(aif1_dai->dev, "Failed to switch to MCLK2: %d\n", ret);
return ret;
}
ret = snd_soc_card_jack_new_pins(card, "Headset",
SND_JACK_HEADSET | SND_JACK_MECHANICAL |
SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2 |
SND_JACK_BTN_3 | SND_JACK_BTN_4 | SND_JACK_BTN_5,
&priv->headset_jack,
headset_jack_pins,
ARRAY_SIZE(headset_jack_pins));
if (ret)
return ret;
wm8958_mic_detect(aif1_dai->component, &priv->headset_jack,
NULL, NULL, NULL, NULL);
return 0;
}
static struct snd_soc_dai_driver midas_ext_dai[] = {
{
.name = "Voice call",
.playback = {
.channels_min = 1,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 16000,
.rates = (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000),
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.capture = {
.channels_min = 1,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 16000,
.rates = (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000),
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
},
{
.name = "Bluetooth",
.playback = {
.channels_min = 1,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 16000,
.rates = (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000),
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.capture = {
.channels_min = 1,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 16000,
.rates = (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000),
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
},
};
static const struct snd_soc_component_driver midas_component = {
.name = "midas-audio",
};
SND_SOC_DAILINK_DEFS(wm1811_hifi,
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "wm8994-aif1")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(wm1811_voice,
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "wm8994-aif2")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(wm1811_bt,
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "wm8994-aif3")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
static struct snd_soc_dai_link midas_dai[] = {
{
.name = "WM8994 AIF1",
.stream_name = "HiFi Primary",
.ops = &midas_aif1_ops,
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBM_CFM,
SND_SOC_DAILINK_REG(wm1811_hifi),
}, {
.name = "WM1811 Voice",
.stream_name = "Voice call",
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(wm1811_voice),
}, {
.name = "WM1811 BT",
.stream_name = "Bluetooth",
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(wm1811_bt),
},
};
static struct snd_soc_card midas_card = {
.name = "Midas WM1811",
.owner = THIS_MODULE,
.dai_link = midas_dai,
.num_links = ARRAY_SIZE(midas_dai),
.controls = midas_controls,
.num_controls = ARRAY_SIZE(midas_controls),
.dapm_widgets = midas_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(midas_dapm_widgets),
.set_bias_level = midas_set_bias_level,
.late_probe = midas_late_probe,
};
static int midas_probe(struct platform_device *pdev)
{
struct device_node *cpu_dai_node = NULL, *codec_dai_node = NULL;
struct device_node *cpu = NULL, *codec = NULL;
struct snd_soc_card *card = &midas_card;
struct device *dev = &pdev->dev;
static struct snd_soc_dai_link *dai_link;
struct midas_priv *priv;
int ret, i;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
snd_soc_card_set_drvdata(card, priv);
card->dev = dev;
priv->reg_mic_bias = devm_regulator_get(dev, "mic-bias");
if (IS_ERR(priv->reg_mic_bias)) {
dev_err(dev, "Failed to get mic bias regulator\n");
return PTR_ERR(priv->reg_mic_bias);
}
priv->reg_submic_bias = devm_regulator_get(dev, "submic-bias");
if (IS_ERR(priv->reg_submic_bias)) {
dev_err(dev, "Failed to get submic bias regulator\n");
return PTR_ERR(priv->reg_submic_bias);
}
priv->gpio_fm_sel = devm_gpiod_get_optional(dev, "fm-sel", GPIOD_OUT_HIGH);
if (IS_ERR(priv->gpio_fm_sel)) {
dev_err(dev, "Failed to get FM selection GPIO\n");
return PTR_ERR(priv->gpio_fm_sel);
}
priv->gpio_lineout_sel = devm_gpiod_get_optional(dev, "lineout-sel",
GPIOD_OUT_HIGH);
if (IS_ERR(priv->gpio_lineout_sel)) {
dev_err(dev, "Failed to get line out selection GPIO\n");
return PTR_ERR(priv->gpio_lineout_sel);
}
ret = snd_soc_of_parse_card_name(card, "model");
if (ret < 0) {
dev_err(dev, "Card name is not specified\n");
return ret;
}
ret = snd_soc_of_parse_audio_routing(card, "audio-routing");
if (ret < 0) {
/* Backwards compatible way */
ret = snd_soc_of_parse_audio_routing(card, "samsung,audio-routing");
if (ret < 0) {
dev_err(dev, "Audio routing invalid/unspecified\n");
return ret;
}
}
cpu = of_get_child_by_name(dev->of_node, "cpu");
if (!cpu)
return -EINVAL;
codec = of_get_child_by_name(dev->of_node, "codec");
if (!codec) {
of_node_put(cpu);
return -EINVAL;
}
cpu_dai_node = of_parse_phandle(cpu, "sound-dai", 0);
of_node_put(cpu);
if (!cpu_dai_node) {
dev_err(dev, "parsing cpu/sound-dai failed\n");
of_node_put(codec);
return -EINVAL;
}
codec_dai_node = of_parse_phandle(codec, "sound-dai", 0);
of_node_put(codec);
if (!codec_dai_node) {
dev_err(dev, "audio-codec property invalid/missing\n");
ret = -EINVAL;
goto put_cpu_dai_node;
}
for_each_card_prelinks(card, i, dai_link) {
dai_link->codecs->of_node = codec_dai_node;
dai_link->cpus->of_node = cpu_dai_node;
dai_link->platforms->of_node = cpu_dai_node;
}
ret = devm_snd_soc_register_component(dev, &midas_component,
midas_ext_dai, ARRAY_SIZE(midas_ext_dai));
if (ret < 0) {
dev_err(dev, "Failed to register component: %d\n", ret);
goto put_codec_dai_node;
}
ret = devm_snd_soc_register_card(dev, card);
if (ret < 0) {
dev_err(dev, "Failed to register card: %d\n", ret);
goto put_codec_dai_node;
}
return 0;
put_codec_dai_node:
of_node_put(codec_dai_node);
put_cpu_dai_node:
of_node_put(cpu_dai_node);
return ret;
}
static const struct of_device_id midas_of_match[] = {
{ .compatible = "samsung,midas-audio" },
{ },
};
MODULE_DEVICE_TABLE(of, midas_of_match);
static struct platform_driver midas_driver = {
.driver = {
.name = "midas-audio",
.of_match_table = midas_of_match,
.pm = &snd_soc_pm_ops,
},
.probe = midas_probe,
};
module_platform_driver(midas_driver);
MODULE_AUTHOR("Simon Shields <[email protected]>");
MODULE_DESCRIPTION("ASoC support for Midas");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/samsung/midas_wm1811.c |
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (c) 2011 Samsung Electronics Co., Ltd
// http://www.samsung.com
#include <linux/module.h>
#include <sound/soc.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include "../codecs/wm8994.h"
#include "pcm.h"
/*
* Board Settings:
* o '1' means 'ON'
* o '0' means 'OFF'
* o 'X' means 'Don't care'
*
* SMDKC210, SMDKV310: CFG3- 1001, CFG5-1000, CFG7-111111
*/
/*
* Configure audio route as :-
* $ amixer sset 'DAC1' on,on
* $ amixer sset 'Right Headphone Mux' 'DAC'
* $ amixer sset 'Left Headphone Mux' 'DAC'
* $ amixer sset 'DAC1R Mixer AIF1.1' on
* $ amixer sset 'DAC1L Mixer AIF1.1' on
* $ amixer sset 'IN2L' on
* $ amixer sset 'IN2L PGA IN2LN' on
* $ amixer sset 'MIXINL IN2L' on
* $ amixer sset 'AIF1ADC1L Mixer ADC/DMIC' on
* $ amixer sset 'IN2R' on
* $ amixer sset 'IN2R PGA IN2RN' on
* $ amixer sset 'MIXINR IN2R' on
* $ amixer sset 'AIF1ADC1R Mixer ADC/DMIC' on
*/
/* SMDK has a 16.9344MHZ crystal attached to WM8994 */
#define SMDK_WM8994_FREQ 16934400
static int smdk_wm8994_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
unsigned long mclk_freq;
int rfs, ret;
switch(params_rate(params)) {
case 8000:
rfs = 512;
break;
default:
dev_err(cpu_dai->dev, "%s:%d Sampling Rate %u not supported!\n",
__func__, __LINE__, params_rate(params));
return -EINVAL;
}
mclk_freq = params_rate(params) * rfs;
ret = snd_soc_dai_set_sysclk(codec_dai, WM8994_SYSCLK_FLL1,
mclk_freq, SND_SOC_CLOCK_IN);
if (ret < 0)
return ret;
ret = snd_soc_dai_set_pll(codec_dai, WM8994_FLL1, WM8994_FLL_SRC_MCLK1,
SMDK_WM8994_FREQ, mclk_freq);
if (ret < 0)
return ret;
/* Set PCM source clock on CPU */
ret = snd_soc_dai_set_sysclk(cpu_dai, S3C_PCM_CLKSRC_MUX,
mclk_freq, SND_SOC_CLOCK_IN);
if (ret < 0)
return ret;
/* Set SCLK_DIV for making bclk */
ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C_PCM_SCLK_PER_FS, rfs);
if (ret < 0)
return ret;
return 0;
}
static const struct snd_soc_ops smdk_wm8994_pcm_ops = {
.hw_params = smdk_wm8994_pcm_hw_params,
};
SND_SOC_DAILINK_DEFS(paif_pcm,
DAILINK_COMP_ARRAY(COMP_CPU("samsung-pcm.0")),
DAILINK_COMP_ARRAY(COMP_CODEC("wm8994-codec", "wm8994-aif1")),
DAILINK_COMP_ARRAY(COMP_PLATFORM("samsung-pcm.0")));
static struct snd_soc_dai_link smdk_dai[] = {
{
.name = "WM8994 PAIF PCM",
.stream_name = "Primary PCM",
.dai_fmt = SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF |
SND_SOC_DAIFMT_CBS_CFS,
.ops = &smdk_wm8994_pcm_ops,
SND_SOC_DAILINK_REG(paif_pcm),
},
};
static struct snd_soc_card smdk_pcm = {
.name = "SMDK-PCM",
.owner = THIS_MODULE,
.dai_link = smdk_dai,
.num_links = 1,
};
static int snd_smdk_probe(struct platform_device *pdev)
{
int ret = 0;
smdk_pcm.dev = &pdev->dev;
ret = devm_snd_soc_register_card(&pdev->dev, &smdk_pcm);
if (ret)
dev_err_probe(&pdev->dev, ret, "snd_soc_register_card failed\n");
return ret;
}
static struct platform_driver snd_smdk_driver = {
.driver = {
.name = "samsung-smdk-pcm",
},
.probe = snd_smdk_probe,
};
module_platform_driver(snd_smdk_driver);
MODULE_AUTHOR("Sangbeom Kim, <[email protected]>");
MODULE_DESCRIPTION("ALSA SoC SMDK WM8994 for PCM");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/samsung/smdk_wm8994pcm.c |
// SPDX-License-Identifier: GPL-2.0+
//
// Lowland audio support
//
// Copyright 2011 Wolfson Microelectronics
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/jack.h>
#include <linux/gpio.h>
#include <linux/module.h>
#include "../codecs/wm5100.h"
#include "../codecs/wm9081.h"
#define MCLK1_RATE (44100 * 512)
#define CLKOUT_RATE (44100 * 256)
static struct snd_soc_jack lowland_headset;
/* Headset jack detection DAPM pins */
static struct snd_soc_jack_pin lowland_headset_pins[] = {
{
.pin = "Headphone",
.mask = SND_JACK_HEADPHONE,
},
{
.pin = "Headset Mic",
.mask = SND_JACK_MICROPHONE,
},
{
.pin = "Line Out",
.mask = SND_JACK_LINEOUT,
},
};
static int lowland_wm5100_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component;
int ret;
ret = snd_soc_component_set_sysclk(component, WM5100_CLK_SYSCLK,
WM5100_CLKSRC_MCLK1, MCLK1_RATE,
SND_SOC_CLOCK_IN);
if (ret < 0) {
pr_err("Failed to set SYSCLK clock source: %d\n", ret);
return ret;
}
/* Clock OPCLK, used by the other audio components. */
ret = snd_soc_component_set_sysclk(component, WM5100_CLK_OPCLK, 0,
CLKOUT_RATE, 0);
if (ret < 0) {
pr_err("Failed to set OPCLK rate: %d\n", ret);
return ret;
}
ret = snd_soc_card_jack_new_pins(rtd->card, "Headset",
SND_JACK_LINEOUT | SND_JACK_HEADSET |
SND_JACK_BTN_0,
&lowland_headset, lowland_headset_pins,
ARRAY_SIZE(lowland_headset_pins));
if (ret)
return ret;
wm5100_detect(component, &lowland_headset);
return 0;
}
static int lowland_wm9081_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component;
snd_soc_dapm_nc_pin(&rtd->card->dapm, "LINEOUT");
/* At any time the WM9081 is active it will have this clock */
return snd_soc_component_set_sysclk(component, WM9081_SYSCLK_MCLK, 0,
CLKOUT_RATE, 0);
}
static const struct snd_soc_pcm_stream sub_params = {
.formats = SNDRV_PCM_FMTBIT_S32_LE,
.rate_min = 44100,
.rate_max = 44100,
.channels_min = 2,
.channels_max = 2,
};
SND_SOC_DAILINK_DEFS(cpu,
DAILINK_COMP_ARRAY(COMP_CPU("samsung-i2s.0")),
DAILINK_COMP_ARRAY(COMP_CODEC("wm5100.1-001a", "wm5100-aif1")),
DAILINK_COMP_ARRAY(COMP_PLATFORM("samsung-i2s.0")));
SND_SOC_DAILINK_DEFS(baseband,
DAILINK_COMP_ARRAY(COMP_CPU("wm5100-aif2")),
DAILINK_COMP_ARRAY(COMP_CODEC("wm1250-ev1.1-0027", "wm1250-ev1")));
SND_SOC_DAILINK_DEFS(speaker,
DAILINK_COMP_ARRAY(COMP_CPU("wm5100-aif3")),
DAILINK_COMP_ARRAY(COMP_CODEC("wm9081.1-006c", "wm9081-hifi")));
static struct snd_soc_dai_link lowland_dai[] = {
{
.name = "CPU",
.stream_name = "CPU",
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBM_CFM,
.init = lowland_wm5100_init,
SND_SOC_DAILINK_REG(cpu),
},
{
.name = "Baseband",
.stream_name = "Baseband",
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBM_CFM,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(baseband),
},
{
.name = "Sub Speaker",
.stream_name = "Sub Speaker",
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBM_CFM,
.ignore_suspend = 1,
.c2c_params = &sub_params,
.num_c2c_params = 1,
.init = lowland_wm9081_init,
SND_SOC_DAILINK_REG(speaker),
},
};
static struct snd_soc_codec_conf lowland_codec_conf[] = {
{
.dlc = COMP_CODEC_CONF("wm9081.1-006c"),
.name_prefix = "Sub",
},
};
static const struct snd_kcontrol_new controls[] = {
SOC_DAPM_PIN_SWITCH("Main Speaker"),
SOC_DAPM_PIN_SWITCH("Main DMIC"),
SOC_DAPM_PIN_SWITCH("Main AMIC"),
SOC_DAPM_PIN_SWITCH("WM1250 Input"),
SOC_DAPM_PIN_SWITCH("WM1250 Output"),
SOC_DAPM_PIN_SWITCH("Headphone"),
SOC_DAPM_PIN_SWITCH("Line Out"),
};
static const struct snd_soc_dapm_widget widgets[] = {
SND_SOC_DAPM_HP("Headphone", NULL),
SND_SOC_DAPM_MIC("Headset Mic", NULL),
SND_SOC_DAPM_LINE("Line Out", NULL),
SND_SOC_DAPM_SPK("Main Speaker", NULL),
SND_SOC_DAPM_MIC("Main AMIC", NULL),
SND_SOC_DAPM_MIC("Main DMIC", NULL),
};
static const struct snd_soc_dapm_route audio_paths[] = {
{ "Sub IN1", NULL, "HPOUT2L" },
{ "Sub IN2", NULL, "HPOUT2R" },
{ "Main Speaker", NULL, "Sub SPKN" },
{ "Main Speaker", NULL, "Sub SPKP" },
{ "Main Speaker", NULL, "SPKDAT1" },
};
static struct snd_soc_card lowland = {
.name = "Lowland",
.owner = THIS_MODULE,
.dai_link = lowland_dai,
.num_links = ARRAY_SIZE(lowland_dai),
.codec_conf = lowland_codec_conf,
.num_configs = ARRAY_SIZE(lowland_codec_conf),
.controls = controls,
.num_controls = ARRAY_SIZE(controls),
.dapm_widgets = widgets,
.num_dapm_widgets = ARRAY_SIZE(widgets),
.dapm_routes = audio_paths,
.num_dapm_routes = ARRAY_SIZE(audio_paths),
};
static int lowland_probe(struct platform_device *pdev)
{
struct snd_soc_card *card = &lowland;
int ret;
card->dev = &pdev->dev;
ret = devm_snd_soc_register_card(&pdev->dev, card);
if (ret)
dev_err_probe(&pdev->dev, ret, "snd_soc_register_card() failed\n");
return ret;
}
static struct platform_driver lowland_driver = {
.driver = {
.name = "lowland",
.pm = &snd_soc_pm_ops,
},
.probe = lowland_probe,
};
module_platform_driver(lowland_driver);
MODULE_DESCRIPTION("Lowland audio support");
MODULE_AUTHOR("Mark Brown <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:lowland");
| linux-master | sound/soc/samsung/lowland.c |
// SPDX-License-Identifier: GPL-2.0
//
// dmaengine.c - Samsung dmaengine wrapper
//
// Author: Mark Brown <[email protected]>
// Copyright 2013 Linaro
#include <linux/module.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/dmaengine_pcm.h>
#include <sound/soc.h>
#include "dma.h"
int samsung_asoc_dma_platform_register(struct device *dev, dma_filter_fn filter,
const char *tx, const char *rx,
struct device *dma_dev)
{
struct snd_dmaengine_pcm_config *pcm_conf;
pcm_conf = devm_kzalloc(dev, sizeof(*pcm_conf), GFP_KERNEL);
if (!pcm_conf)
return -ENOMEM;
pcm_conf->prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config;
pcm_conf->compat_filter_fn = filter;
pcm_conf->dma_dev = dma_dev;
pcm_conf->chan_names[SNDRV_PCM_STREAM_PLAYBACK] = tx;
pcm_conf->chan_names[SNDRV_PCM_STREAM_CAPTURE] = rx;
return devm_snd_dmaengine_pcm_register(dev, pcm_conf,
SND_DMAENGINE_PCM_FLAG_COMPAT);
}
EXPORT_SYMBOL_GPL(samsung_asoc_dma_platform_register);
MODULE_AUTHOR("Mark Brown <[email protected]>");
MODULE_DESCRIPTION("Samsung dmaengine ASoC driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/samsung/dmaengine.c |
// SPDX-License-Identifier: GPL-2.0
//
// ALSA SoC Audio Layer - Samsung S/PDIF Controller driver
//
// Copyright (c) 2010 Samsung Electronics Co. Ltd
// http://www.samsung.com/
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/module.h>
#include <sound/soc.h>
#include <sound/pcm_params.h>
#include <linux/platform_data/asoc-s3c.h>
#include "dma.h"
#include "spdif.h"
/* Registers */
#define CLKCON 0x00
#define CON 0x04
#define BSTAS 0x08
#define CSTAS 0x0C
#define DATA_OUTBUF 0x10
#define DCNT 0x14
#define BSTAS_S 0x18
#define DCNT_S 0x1C
#define CLKCTL_MASK 0x7
#define CLKCTL_MCLK_EXT (0x1 << 2)
#define CLKCTL_PWR_ON (0x1 << 0)
#define CON_MASK 0x3ffffff
#define CON_FIFO_TH_SHIFT 19
#define CON_FIFO_TH_MASK (0x7 << 19)
#define CON_USERDATA_23RDBIT (0x1 << 12)
#define CON_SW_RESET (0x1 << 5)
#define CON_MCLKDIV_MASK (0x3 << 3)
#define CON_MCLKDIV_256FS (0x0 << 3)
#define CON_MCLKDIV_384FS (0x1 << 3)
#define CON_MCLKDIV_512FS (0x2 << 3)
#define CON_PCM_MASK (0x3 << 1)
#define CON_PCM_16BIT (0x0 << 1)
#define CON_PCM_20BIT (0x1 << 1)
#define CON_PCM_24BIT (0x2 << 1)
#define CON_PCM_DATA (0x1 << 0)
#define CSTAS_MASK 0x3fffffff
#define CSTAS_SAMP_FREQ_MASK (0xF << 24)
#define CSTAS_SAMP_FREQ_44 (0x0 << 24)
#define CSTAS_SAMP_FREQ_48 (0x2 << 24)
#define CSTAS_SAMP_FREQ_32 (0x3 << 24)
#define CSTAS_SAMP_FREQ_96 (0xA << 24)
#define CSTAS_CATEGORY_MASK (0xFF << 8)
#define CSTAS_CATEGORY_CODE_CDP (0x01 << 8)
#define CSTAS_NO_COPYRIGHT (0x1 << 2)
/**
* struct samsung_spdif_info - Samsung S/PDIF Controller information
* @lock: Spin lock for S/PDIF.
* @dev: The parent device passed to use from the probe.
* @regs: The pointer to the device register block.
* @clk_rate: Current clock rate for calcurate ratio.
* @pclk: The peri-clock pointer for spdif master operation.
* @sclk: The source clock pointer for making sync signals.
* @saved_clkcon: Backup clkcon reg. in suspend.
* @saved_con: Backup con reg. in suspend.
* @saved_cstas: Backup cstas reg. in suspend.
* @dma_playback: DMA information for playback channel.
*/
struct samsung_spdif_info {
spinlock_t lock;
struct device *dev;
void __iomem *regs;
unsigned long clk_rate;
struct clk *pclk;
struct clk *sclk;
u32 saved_clkcon;
u32 saved_con;
u32 saved_cstas;
struct snd_dmaengine_dai_dma_data *dma_playback;
};
static struct snd_dmaengine_dai_dma_data spdif_stereo_out;
static struct samsung_spdif_info spdif_info;
static inline struct samsung_spdif_info
*component_to_info(struct snd_soc_component *component)
{
return snd_soc_component_get_drvdata(component);
}
static inline struct samsung_spdif_info *to_info(struct snd_soc_dai *cpu_dai)
{
return snd_soc_dai_get_drvdata(cpu_dai);
}
static void spdif_snd_txctrl(struct samsung_spdif_info *spdif, int on)
{
void __iomem *regs = spdif->regs;
u32 clkcon;
dev_dbg(spdif->dev, "Entered %s\n", __func__);
clkcon = readl(regs + CLKCON) & CLKCTL_MASK;
if (on)
writel(clkcon | CLKCTL_PWR_ON, regs + CLKCON);
else
writel(clkcon & ~CLKCTL_PWR_ON, regs + CLKCON);
}
static int spdif_set_sysclk(struct snd_soc_dai *cpu_dai,
int clk_id, unsigned int freq, int dir)
{
struct samsung_spdif_info *spdif = to_info(cpu_dai);
u32 clkcon;
dev_dbg(spdif->dev, "Entered %s\n", __func__);
clkcon = readl(spdif->regs + CLKCON);
if (clk_id == SND_SOC_SPDIF_INT_MCLK)
clkcon &= ~CLKCTL_MCLK_EXT;
else
clkcon |= CLKCTL_MCLK_EXT;
writel(clkcon, spdif->regs + CLKCON);
spdif->clk_rate = freq;
return 0;
}
static int spdif_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct samsung_spdif_info *spdif = to_info(asoc_rtd_to_cpu(rtd, 0));
unsigned long flags;
dev_dbg(spdif->dev, "Entered %s\n", __func__);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
spin_lock_irqsave(&spdif->lock, flags);
spdif_snd_txctrl(spdif, 1);
spin_unlock_irqrestore(&spdif->lock, flags);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
spin_lock_irqsave(&spdif->lock, flags);
spdif_snd_txctrl(spdif, 0);
spin_unlock_irqrestore(&spdif->lock, flags);
break;
default:
return -EINVAL;
}
return 0;
}
static int spdif_sysclk_ratios[] = {
512, 384, 256,
};
static int spdif_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *socdai)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct samsung_spdif_info *spdif = to_info(asoc_rtd_to_cpu(rtd, 0));
void __iomem *regs = spdif->regs;
struct snd_dmaengine_dai_dma_data *dma_data;
u32 con, clkcon, cstas;
unsigned long flags;
int i, ratio;
dev_dbg(spdif->dev, "Entered %s\n", __func__);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
dma_data = spdif->dma_playback;
else {
dev_err(spdif->dev, "Capture is not supported\n");
return -EINVAL;
}
snd_soc_dai_set_dma_data(asoc_rtd_to_cpu(rtd, 0), substream, dma_data);
spin_lock_irqsave(&spdif->lock, flags);
con = readl(regs + CON) & CON_MASK;
cstas = readl(regs + CSTAS) & CSTAS_MASK;
clkcon = readl(regs + CLKCON) & CLKCTL_MASK;
con &= ~CON_FIFO_TH_MASK;
con |= (0x7 << CON_FIFO_TH_SHIFT);
con |= CON_USERDATA_23RDBIT;
con |= CON_PCM_DATA;
con &= ~CON_PCM_MASK;
switch (params_width(params)) {
case 16:
con |= CON_PCM_16BIT;
break;
default:
dev_err(spdif->dev, "Unsupported data size.\n");
goto err;
}
ratio = spdif->clk_rate / params_rate(params);
for (i = 0; i < ARRAY_SIZE(spdif_sysclk_ratios); i++)
if (ratio == spdif_sysclk_ratios[i])
break;
if (i == ARRAY_SIZE(spdif_sysclk_ratios)) {
dev_err(spdif->dev, "Invalid clock ratio %ld/%d\n",
spdif->clk_rate, params_rate(params));
goto err;
}
con &= ~CON_MCLKDIV_MASK;
switch (ratio) {
case 256:
con |= CON_MCLKDIV_256FS;
break;
case 384:
con |= CON_MCLKDIV_384FS;
break;
case 512:
con |= CON_MCLKDIV_512FS;
break;
}
cstas &= ~CSTAS_SAMP_FREQ_MASK;
switch (params_rate(params)) {
case 44100:
cstas |= CSTAS_SAMP_FREQ_44;
break;
case 48000:
cstas |= CSTAS_SAMP_FREQ_48;
break;
case 32000:
cstas |= CSTAS_SAMP_FREQ_32;
break;
case 96000:
cstas |= CSTAS_SAMP_FREQ_96;
break;
default:
dev_err(spdif->dev, "Invalid sampling rate %d\n",
params_rate(params));
goto err;
}
cstas &= ~CSTAS_CATEGORY_MASK;
cstas |= CSTAS_CATEGORY_CODE_CDP;
cstas |= CSTAS_NO_COPYRIGHT;
writel(con, regs + CON);
writel(cstas, regs + CSTAS);
writel(clkcon, regs + CLKCON);
spin_unlock_irqrestore(&spdif->lock, flags);
return 0;
err:
spin_unlock_irqrestore(&spdif->lock, flags);
return -EINVAL;
}
static void spdif_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct samsung_spdif_info *spdif = to_info(asoc_rtd_to_cpu(rtd, 0));
void __iomem *regs = spdif->regs;
u32 con, clkcon;
dev_dbg(spdif->dev, "Entered %s\n", __func__);
con = readl(regs + CON) & CON_MASK;
clkcon = readl(regs + CLKCON) & CLKCTL_MASK;
writel(con | CON_SW_RESET, regs + CON);
cpu_relax();
writel(clkcon & ~CLKCTL_PWR_ON, regs + CLKCON);
}
#ifdef CONFIG_PM
static int spdif_suspend(struct snd_soc_component *component)
{
struct samsung_spdif_info *spdif = component_to_info(component);
u32 con = spdif->saved_con;
dev_dbg(spdif->dev, "Entered %s\n", __func__);
spdif->saved_clkcon = readl(spdif->regs + CLKCON) & CLKCTL_MASK;
spdif->saved_con = readl(spdif->regs + CON) & CON_MASK;
spdif->saved_cstas = readl(spdif->regs + CSTAS) & CSTAS_MASK;
writel(con | CON_SW_RESET, spdif->regs + CON);
cpu_relax();
return 0;
}
static int spdif_resume(struct snd_soc_component *component)
{
struct samsung_spdif_info *spdif = component_to_info(component);
dev_dbg(spdif->dev, "Entered %s\n", __func__);
writel(spdif->saved_clkcon, spdif->regs + CLKCON);
writel(spdif->saved_con, spdif->regs + CON);
writel(spdif->saved_cstas, spdif->regs + CSTAS);
return 0;
}
#else
#define spdif_suspend NULL
#define spdif_resume NULL
#endif
static const struct snd_soc_dai_ops spdif_dai_ops = {
.set_sysclk = spdif_set_sysclk,
.trigger = spdif_trigger,
.hw_params = spdif_hw_params,
.shutdown = spdif_shutdown,
};
static struct snd_soc_dai_driver samsung_spdif_dai = {
.name = "samsung-spdif",
.playback = {
.stream_name = "S/PDIF Playback",
.channels_min = 2,
.channels_max = 2,
.rates = (SNDRV_PCM_RATE_32000 |
SNDRV_PCM_RATE_44100 |
SNDRV_PCM_RATE_48000 |
SNDRV_PCM_RATE_96000),
.formats = SNDRV_PCM_FMTBIT_S16_LE, },
.ops = &spdif_dai_ops,
};
static const struct snd_soc_component_driver samsung_spdif_component = {
.name = "samsung-spdif",
.suspend = spdif_suspend,
.resume = spdif_resume,
.legacy_dai_naming = 1,
};
static int spdif_probe(struct platform_device *pdev)
{
struct s3c_audio_pdata *spdif_pdata;
struct resource *mem_res;
struct samsung_spdif_info *spdif;
dma_filter_fn filter;
int ret;
spdif_pdata = pdev->dev.platform_data;
dev_dbg(&pdev->dev, "Entered %s\n", __func__);
mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!mem_res) {
dev_err(&pdev->dev, "Unable to get register resource.\n");
return -ENXIO;
}
if (spdif_pdata && spdif_pdata->cfg_gpio
&& spdif_pdata->cfg_gpio(pdev)) {
dev_err(&pdev->dev, "Unable to configure GPIO pins\n");
return -EINVAL;
}
spdif = &spdif_info;
spdif->dev = &pdev->dev;
spin_lock_init(&spdif->lock);
spdif->pclk = devm_clk_get(&pdev->dev, "spdif");
if (IS_ERR(spdif->pclk)) {
dev_err(&pdev->dev, "failed to get peri-clock\n");
ret = -ENOENT;
goto err0;
}
ret = clk_prepare_enable(spdif->pclk);
if (ret)
goto err0;
spdif->sclk = devm_clk_get(&pdev->dev, "sclk_spdif");
if (IS_ERR(spdif->sclk)) {
dev_err(&pdev->dev, "failed to get internal source clock\n");
ret = -ENOENT;
goto err1;
}
ret = clk_prepare_enable(spdif->sclk);
if (ret)
goto err1;
/* Request S/PDIF Register's memory region */
if (!request_mem_region(mem_res->start,
resource_size(mem_res), "samsung-spdif")) {
dev_err(&pdev->dev, "Unable to request register region\n");
ret = -EBUSY;
goto err2;
}
spdif->regs = ioremap(mem_res->start, 0x100);
if (spdif->regs == NULL) {
dev_err(&pdev->dev, "Cannot ioremap registers\n");
ret = -ENXIO;
goto err3;
}
spdif_stereo_out.addr_width = 2;
spdif_stereo_out.addr = mem_res->start + DATA_OUTBUF;
filter = NULL;
if (spdif_pdata) {
spdif_stereo_out.filter_data = spdif_pdata->dma_playback;
filter = spdif_pdata->dma_filter;
}
spdif->dma_playback = &spdif_stereo_out;
ret = samsung_asoc_dma_platform_register(&pdev->dev, filter,
NULL, NULL, NULL);
if (ret) {
dev_err(&pdev->dev, "failed to register DMA: %d\n", ret);
goto err4;
}
dev_set_drvdata(&pdev->dev, spdif);
ret = devm_snd_soc_register_component(&pdev->dev,
&samsung_spdif_component, &samsung_spdif_dai, 1);
if (ret != 0) {
dev_err(&pdev->dev, "fail to register dai\n");
goto err4;
}
return 0;
err4:
iounmap(spdif->regs);
err3:
release_mem_region(mem_res->start, resource_size(mem_res));
err2:
clk_disable_unprepare(spdif->sclk);
err1:
clk_disable_unprepare(spdif->pclk);
err0:
return ret;
}
static void spdif_remove(struct platform_device *pdev)
{
struct samsung_spdif_info *spdif = &spdif_info;
struct resource *mem_res;
iounmap(spdif->regs);
mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
release_mem_region(mem_res->start, resource_size(mem_res));
clk_disable_unprepare(spdif->sclk);
clk_disable_unprepare(spdif->pclk);
}
static struct platform_driver samsung_spdif_driver = {
.probe = spdif_probe,
.remove_new = spdif_remove,
.driver = {
.name = "samsung-spdif",
},
};
module_platform_driver(samsung_spdif_driver);
MODULE_AUTHOR("Seungwhan Youn, <[email protected]>");
MODULE_DESCRIPTION("Samsung S/PDIF Controller Driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:samsung-spdif");
| linux-master | sound/soc/samsung/spdif.c |
// SPDX-License-Identifier: GPL-2.0+
//
// Tobermory audio support
//
// Copyright 2011 Wolfson Microelectronics
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/jack.h>
#include <linux/gpio.h>
#include <linux/module.h>
#include "../codecs/wm8962.h"
static int sample_rate = 44100;
static int tobermory_set_bias_level(struct snd_soc_card *card,
struct snd_soc_dapm_context *dapm,
enum snd_soc_bias_level level)
{
struct snd_soc_pcm_runtime *rtd;
struct snd_soc_dai *codec_dai;
int ret;
rtd = snd_soc_get_pcm_runtime(card, &card->dai_link[0]);
codec_dai = asoc_rtd_to_codec(rtd, 0);
if (dapm->dev != codec_dai->dev)
return 0;
switch (level) {
case SND_SOC_BIAS_PREPARE:
if (dapm->bias_level == SND_SOC_BIAS_STANDBY) {
ret = snd_soc_dai_set_pll(codec_dai, WM8962_FLL,
WM8962_FLL_MCLK, 32768,
sample_rate * 512);
if (ret < 0)
pr_err("Failed to start FLL: %d\n", ret);
ret = snd_soc_dai_set_sysclk(codec_dai,
WM8962_SYSCLK_FLL,
sample_rate * 512,
SND_SOC_CLOCK_IN);
if (ret < 0) {
pr_err("Failed to set SYSCLK: %d\n", ret);
snd_soc_dai_set_pll(codec_dai, WM8962_FLL,
0, 0, 0);
return ret;
}
}
break;
default:
break;
}
return 0;
}
static int tobermory_set_bias_level_post(struct snd_soc_card *card,
struct snd_soc_dapm_context *dapm,
enum snd_soc_bias_level level)
{
struct snd_soc_pcm_runtime *rtd;
struct snd_soc_dai *codec_dai;
int ret;
rtd = snd_soc_get_pcm_runtime(card, &card->dai_link[0]);
codec_dai = asoc_rtd_to_codec(rtd, 0);
if (dapm->dev != codec_dai->dev)
return 0;
switch (level) {
case SND_SOC_BIAS_STANDBY:
ret = snd_soc_dai_set_sysclk(codec_dai, WM8962_SYSCLK_MCLK,
32768, SND_SOC_CLOCK_IN);
if (ret < 0) {
pr_err("Failed to switch away from FLL: %d\n", ret);
return ret;
}
ret = snd_soc_dai_set_pll(codec_dai, WM8962_FLL,
0, 0, 0);
if (ret < 0) {
pr_err("Failed to stop FLL: %d\n", ret);
return ret;
}
break;
default:
break;
}
dapm->bias_level = level;
return 0;
}
static int tobermory_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
sample_rate = params_rate(params);
return 0;
}
static const struct snd_soc_ops tobermory_ops = {
.hw_params = tobermory_hw_params,
};
SND_SOC_DAILINK_DEFS(cpu,
DAILINK_COMP_ARRAY(COMP_CPU("samsung-i2s.0")),
DAILINK_COMP_ARRAY(COMP_CODEC("wm8962.1-001a", "wm8962")),
DAILINK_COMP_ARRAY(COMP_PLATFORM("samsung-i2s.0")));
static struct snd_soc_dai_link tobermory_dai[] = {
{
.name = "CPU",
.stream_name = "CPU",
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF
| SND_SOC_DAIFMT_CBM_CFM,
.ops = &tobermory_ops,
SND_SOC_DAILINK_REG(cpu),
},
};
static const struct snd_kcontrol_new controls[] = {
SOC_DAPM_PIN_SWITCH("Main Speaker"),
SOC_DAPM_PIN_SWITCH("DMIC"),
};
static const struct snd_soc_dapm_widget widgets[] = {
SND_SOC_DAPM_HP("Headphone", NULL),
SND_SOC_DAPM_MIC("Headset Mic", NULL),
SND_SOC_DAPM_MIC("DMIC", NULL),
SND_SOC_DAPM_MIC("AMIC", NULL),
SND_SOC_DAPM_SPK("Main Speaker", NULL),
};
static const struct snd_soc_dapm_route audio_paths[] = {
{ "Headphone", NULL, "HPOUTL" },
{ "Headphone", NULL, "HPOUTR" },
{ "Main Speaker", NULL, "SPKOUTL" },
{ "Main Speaker", NULL, "SPKOUTR" },
{ "Headset Mic", NULL, "MICBIAS" },
{ "IN4L", NULL, "Headset Mic" },
{ "IN4R", NULL, "Headset Mic" },
{ "AMIC", NULL, "MICBIAS" },
{ "IN1L", NULL, "AMIC" },
{ "IN1R", NULL, "AMIC" },
{ "DMIC", NULL, "MICBIAS" },
{ "DMICDAT", NULL, "DMIC" },
};
static struct snd_soc_jack tobermory_headset;
/* Headset jack detection DAPM pins */
static struct snd_soc_jack_pin tobermory_headset_pins[] = {
{
.pin = "Headset Mic",
.mask = SND_JACK_MICROPHONE,
},
{
.pin = "Headphone",
.mask = SND_JACK_MICROPHONE,
},
};
static int tobermory_late_probe(struct snd_soc_card *card)
{
struct snd_soc_pcm_runtime *rtd;
struct snd_soc_component *component;
struct snd_soc_dai *codec_dai;
int ret;
rtd = snd_soc_get_pcm_runtime(card, &card->dai_link[0]);
component = asoc_rtd_to_codec(rtd, 0)->component;
codec_dai = asoc_rtd_to_codec(rtd, 0);
ret = snd_soc_dai_set_sysclk(codec_dai, WM8962_SYSCLK_MCLK,
32768, SND_SOC_CLOCK_IN);
if (ret < 0)
return ret;
ret = snd_soc_card_jack_new_pins(card, "Headset", SND_JACK_HEADSET |
SND_JACK_BTN_0, &tobermory_headset,
tobermory_headset_pins,
ARRAY_SIZE(tobermory_headset_pins));
if (ret)
return ret;
wm8962_mic_detect(component, &tobermory_headset);
return 0;
}
static struct snd_soc_card tobermory = {
.name = "Tobermory",
.owner = THIS_MODULE,
.dai_link = tobermory_dai,
.num_links = ARRAY_SIZE(tobermory_dai),
.set_bias_level = tobermory_set_bias_level,
.set_bias_level_post = tobermory_set_bias_level_post,
.controls = controls,
.num_controls = ARRAY_SIZE(controls),
.dapm_widgets = widgets,
.num_dapm_widgets = ARRAY_SIZE(widgets),
.dapm_routes = audio_paths,
.num_dapm_routes = ARRAY_SIZE(audio_paths),
.fully_routed = true,
.late_probe = tobermory_late_probe,
};
static int tobermory_probe(struct platform_device *pdev)
{
struct snd_soc_card *card = &tobermory;
int ret;
card->dev = &pdev->dev;
ret = devm_snd_soc_register_card(&pdev->dev, card);
if (ret)
dev_err_probe(&pdev->dev, ret, "snd_soc_register_card() failed\n");
return ret;
}
static struct platform_driver tobermory_driver = {
.driver = {
.name = "tobermory",
.pm = &snd_soc_pm_ops,
},
.probe = tobermory_probe,
};
module_platform_driver(tobermory_driver);
MODULE_DESCRIPTION("Tobermory audio support");
MODULE_AUTHOR("Mark Brown <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:tobermory");
| linux-master | sound/soc/samsung/tobermory.c |
// SPDX-License-Identifier: GPL-2.0
//
// ALSA SoC Audio Layer - Samsung I2S Controller driver
//
// Copyright (c) 2010 Samsung Electronics Co. Ltd.
// Jaswinder Singh <[email protected]>
#include <dt-bindings/sound/samsung-i2s.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/pm_runtime.h>
#include <sound/soc.h>
#include <sound/pcm_params.h>
#include <linux/platform_data/asoc-s3c.h>
#include "dma.h"
#include "idma.h"
#include "i2s.h"
#include "i2s-regs.h"
#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
#define SAMSUNG_I2S_ID_PRIMARY 1
#define SAMSUNG_I2S_ID_SECONDARY 2
struct samsung_i2s_variant_regs {
unsigned int bfs_off;
unsigned int rfs_off;
unsigned int sdf_off;
unsigned int txr_off;
unsigned int rclksrc_off;
unsigned int mss_off;
unsigned int cdclkcon_off;
unsigned int lrp_off;
unsigned int bfs_mask;
unsigned int rfs_mask;
unsigned int ftx0cnt_off;
};
struct samsung_i2s_dai_data {
u32 quirks;
unsigned int pcm_rates;
const struct samsung_i2s_variant_regs *i2s_variant_regs;
void (*fixup_early)(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai);
void (*fixup_late)(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai);
};
struct i2s_dai {
/* Platform device for this DAI */
struct platform_device *pdev;
/* Frame clock */
unsigned frmclk;
/*
* Specifically requested RCLK, BCLK by machine driver.
* 0 indicates CPU driver is free to choose any value.
*/
unsigned rfs, bfs;
/* Pointer to the Primary_Fifo if this is Sec_Fifo, NULL otherwise */
struct i2s_dai *pri_dai;
/* Pointer to the Secondary_Fifo if it has one, NULL otherwise */
struct i2s_dai *sec_dai;
#define DAI_OPENED (1 << 0) /* DAI is opened */
#define DAI_MANAGER (1 << 1) /* DAI is the manager */
unsigned mode;
/* Driver for this DAI */
struct snd_soc_dai_driver *drv;
/* DMA parameters */
struct snd_dmaengine_dai_dma_data dma_playback;
struct snd_dmaengine_dai_dma_data dma_capture;
struct snd_dmaengine_dai_dma_data idma_playback;
dma_filter_fn filter;
struct samsung_i2s_priv *priv;
};
struct samsung_i2s_priv {
struct platform_device *pdev;
struct platform_device *pdev_sec;
/* Lock for cross interface checks */
spinlock_t pcm_lock;
/* CPU DAIs and their corresponding drivers */
struct i2s_dai *dai;
struct snd_soc_dai_driver *dai_drv;
int num_dais;
/* The I2S controller's core clock */
struct clk *clk;
/* Clock for generating I2S signals */
struct clk *op_clk;
/* Rate of RCLK source clock */
unsigned long rclk_srcrate;
/* Cache of selected I2S registers for system suspend */
u32 suspend_i2smod;
u32 suspend_i2scon;
u32 suspend_i2spsr;
const struct samsung_i2s_variant_regs *variant_regs;
void (*fixup_early)(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai);
void (*fixup_late)(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai);
u32 quirks;
/* The clock provider's data */
struct clk *clk_table[3];
struct clk_onecell_data clk_data;
/* Spinlock protecting member fields below */
spinlock_t lock;
/* Memory mapped SFR region */
void __iomem *addr;
/* A flag indicating the I2S slave mode operation */
bool slave_mode;
};
/* Returns true if this is the 'overlay' stereo DAI */
static inline bool is_secondary(struct i2s_dai *i2s)
{
return i2s->drv->id == SAMSUNG_I2S_ID_SECONDARY;
}
/* If this interface of the controller is transmitting data */
static inline bool tx_active(struct i2s_dai *i2s)
{
u32 active;
if (!i2s)
return false;
active = readl(i2s->priv->addr + I2SCON);
if (is_secondary(i2s))
active &= CON_TXSDMA_ACTIVE;
else
active &= CON_TXDMA_ACTIVE;
return active ? true : false;
}
/* Return pointer to the other DAI */
static inline struct i2s_dai *get_other_dai(struct i2s_dai *i2s)
{
return i2s->pri_dai ? : i2s->sec_dai;
}
/* If the other interface of the controller is transmitting data */
static inline bool other_tx_active(struct i2s_dai *i2s)
{
struct i2s_dai *other = get_other_dai(i2s);
return tx_active(other);
}
/* If any interface of the controller is transmitting data */
static inline bool any_tx_active(struct i2s_dai *i2s)
{
return tx_active(i2s) || other_tx_active(i2s);
}
/* If this interface of the controller is receiving data */
static inline bool rx_active(struct i2s_dai *i2s)
{
u32 active;
if (!i2s)
return false;
active = readl(i2s->priv->addr + I2SCON) & CON_RXDMA_ACTIVE;
return active ? true : false;
}
/* If the other interface of the controller is receiving data */
static inline bool other_rx_active(struct i2s_dai *i2s)
{
struct i2s_dai *other = get_other_dai(i2s);
return rx_active(other);
}
/* If any interface of the controller is receiving data */
static inline bool any_rx_active(struct i2s_dai *i2s)
{
return rx_active(i2s) || other_rx_active(i2s);
}
/* If the other DAI is transmitting or receiving data */
static inline bool other_active(struct i2s_dai *i2s)
{
return other_rx_active(i2s) || other_tx_active(i2s);
}
/* If this DAI is transmitting or receiving data */
static inline bool this_active(struct i2s_dai *i2s)
{
return tx_active(i2s) || rx_active(i2s);
}
/* If the controller is active anyway */
static inline bool any_active(struct i2s_dai *i2s)
{
return this_active(i2s) || other_active(i2s);
}
static inline struct i2s_dai *to_info(struct snd_soc_dai *dai)
{
struct samsung_i2s_priv *priv = snd_soc_dai_get_drvdata(dai);
return &priv->dai[dai->id - 1];
}
static inline bool is_opened(struct i2s_dai *i2s)
{
if (i2s && (i2s->mode & DAI_OPENED))
return true;
else
return false;
}
static inline bool is_manager(struct i2s_dai *i2s)
{
if (is_opened(i2s) && (i2s->mode & DAI_MANAGER))
return true;
else
return false;
}
/* Read RCLK of I2S (in multiples of LRCLK) */
static inline unsigned get_rfs(struct i2s_dai *i2s)
{
struct samsung_i2s_priv *priv = i2s->priv;
u32 rfs;
rfs = readl(priv->addr + I2SMOD) >> priv->variant_regs->rfs_off;
rfs &= priv->variant_regs->rfs_mask;
switch (rfs) {
case 7: return 192;
case 6: return 96;
case 5: return 128;
case 4: return 64;
case 3: return 768;
case 2: return 384;
case 1: return 512;
default: return 256;
}
}
/* Write RCLK of I2S (in multiples of LRCLK) */
static inline void set_rfs(struct i2s_dai *i2s, unsigned rfs)
{
struct samsung_i2s_priv *priv = i2s->priv;
u32 mod = readl(priv->addr + I2SMOD);
int rfs_shift = priv->variant_regs->rfs_off;
mod &= ~(priv->variant_regs->rfs_mask << rfs_shift);
switch (rfs) {
case 192:
mod |= (EXYNOS7_MOD_RCLK_192FS << rfs_shift);
break;
case 96:
mod |= (EXYNOS7_MOD_RCLK_96FS << rfs_shift);
break;
case 128:
mod |= (EXYNOS7_MOD_RCLK_128FS << rfs_shift);
break;
case 64:
mod |= (EXYNOS7_MOD_RCLK_64FS << rfs_shift);
break;
case 768:
mod |= (MOD_RCLK_768FS << rfs_shift);
break;
case 512:
mod |= (MOD_RCLK_512FS << rfs_shift);
break;
case 384:
mod |= (MOD_RCLK_384FS << rfs_shift);
break;
default:
mod |= (MOD_RCLK_256FS << rfs_shift);
break;
}
writel(mod, priv->addr + I2SMOD);
}
/* Read bit-clock of I2S (in multiples of LRCLK) */
static inline unsigned get_bfs(struct i2s_dai *i2s)
{
struct samsung_i2s_priv *priv = i2s->priv;
u32 bfs;
bfs = readl(priv->addr + I2SMOD) >> priv->variant_regs->bfs_off;
bfs &= priv->variant_regs->bfs_mask;
switch (bfs) {
case 8: return 256;
case 7: return 192;
case 6: return 128;
case 5: return 96;
case 4: return 64;
case 3: return 24;
case 2: return 16;
case 1: return 48;
default: return 32;
}
}
/* Write bit-clock of I2S (in multiples of LRCLK) */
static inline void set_bfs(struct i2s_dai *i2s, unsigned bfs)
{
struct samsung_i2s_priv *priv = i2s->priv;
u32 mod = readl(priv->addr + I2SMOD);
int tdm = priv->quirks & QUIRK_SUPPORTS_TDM;
int bfs_shift = priv->variant_regs->bfs_off;
/* Non-TDM I2S controllers do not support BCLK > 48 * FS */
if (!tdm && bfs > 48) {
dev_err(&i2s->pdev->dev, "Unsupported BCLK divider\n");
return;
}
mod &= ~(priv->variant_regs->bfs_mask << bfs_shift);
switch (bfs) {
case 48:
mod |= (MOD_BCLK_48FS << bfs_shift);
break;
case 32:
mod |= (MOD_BCLK_32FS << bfs_shift);
break;
case 24:
mod |= (MOD_BCLK_24FS << bfs_shift);
break;
case 16:
mod |= (MOD_BCLK_16FS << bfs_shift);
break;
case 64:
mod |= (EXYNOS5420_MOD_BCLK_64FS << bfs_shift);
break;
case 96:
mod |= (EXYNOS5420_MOD_BCLK_96FS << bfs_shift);
break;
case 128:
mod |= (EXYNOS5420_MOD_BCLK_128FS << bfs_shift);
break;
case 192:
mod |= (EXYNOS5420_MOD_BCLK_192FS << bfs_shift);
break;
case 256:
mod |= (EXYNOS5420_MOD_BCLK_256FS << bfs_shift);
break;
default:
dev_err(&i2s->pdev->dev, "Wrong BCLK Divider!\n");
return;
}
writel(mod, priv->addr + I2SMOD);
}
/* Sample size */
static inline int get_blc(struct i2s_dai *i2s)
{
int blc = readl(i2s->priv->addr + I2SMOD);
blc = (blc >> 13) & 0x3;
switch (blc) {
case 2: return 24;
case 1: return 8;
default: return 16;
}
}
/* TX channel control */
static void i2s_txctrl(struct i2s_dai *i2s, int on)
{
struct samsung_i2s_priv *priv = i2s->priv;
void __iomem *addr = priv->addr;
int txr_off = priv->variant_regs->txr_off;
u32 con = readl(addr + I2SCON);
u32 mod = readl(addr + I2SMOD) & ~(3 << txr_off);
if (on) {
con |= CON_ACTIVE;
con &= ~CON_TXCH_PAUSE;
if (is_secondary(i2s)) {
con |= CON_TXSDMA_ACTIVE;
con &= ~CON_TXSDMA_PAUSE;
} else {
con |= CON_TXDMA_ACTIVE;
con &= ~CON_TXDMA_PAUSE;
}
if (any_rx_active(i2s))
mod |= 2 << txr_off;
else
mod |= 0 << txr_off;
} else {
if (is_secondary(i2s)) {
con |= CON_TXSDMA_PAUSE;
con &= ~CON_TXSDMA_ACTIVE;
} else {
con |= CON_TXDMA_PAUSE;
con &= ~CON_TXDMA_ACTIVE;
}
if (other_tx_active(i2s)) {
writel(con, addr + I2SCON);
return;
}
con |= CON_TXCH_PAUSE;
if (any_rx_active(i2s))
mod |= 1 << txr_off;
else
con &= ~CON_ACTIVE;
}
writel(mod, addr + I2SMOD);
writel(con, addr + I2SCON);
}
/* RX Channel Control */
static void i2s_rxctrl(struct i2s_dai *i2s, int on)
{
struct samsung_i2s_priv *priv = i2s->priv;
void __iomem *addr = priv->addr;
int txr_off = priv->variant_regs->txr_off;
u32 con = readl(addr + I2SCON);
u32 mod = readl(addr + I2SMOD) & ~(3 << txr_off);
if (on) {
con |= CON_RXDMA_ACTIVE | CON_ACTIVE;
con &= ~(CON_RXDMA_PAUSE | CON_RXCH_PAUSE);
if (any_tx_active(i2s))
mod |= 2 << txr_off;
else
mod |= 1 << txr_off;
} else {
con |= CON_RXDMA_PAUSE | CON_RXCH_PAUSE;
con &= ~CON_RXDMA_ACTIVE;
if (any_tx_active(i2s))
mod |= 0 << txr_off;
else
con &= ~CON_ACTIVE;
}
writel(mod, addr + I2SMOD);
writel(con, addr + I2SCON);
}
/* Flush FIFO of an interface */
static inline void i2s_fifo(struct i2s_dai *i2s, u32 flush)
{
void __iomem *fic;
u32 val;
if (!i2s)
return;
if (is_secondary(i2s))
fic = i2s->priv->addr + I2SFICS;
else
fic = i2s->priv->addr + I2SFIC;
/* Flush the FIFO */
writel(readl(fic) | flush, fic);
/* Be patient */
val = msecs_to_loops(1) / 1000; /* 1 usec */
while (--val)
cpu_relax();
writel(readl(fic) & ~flush, fic);
}
static int i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id, unsigned int rfs,
int dir)
{
struct samsung_i2s_priv *priv = snd_soc_dai_get_drvdata(dai);
struct i2s_dai *i2s = to_info(dai);
struct i2s_dai *other = get_other_dai(i2s);
const struct samsung_i2s_variant_regs *i2s_regs = priv->variant_regs;
unsigned int cdcon_mask = 1 << i2s_regs->cdclkcon_off;
unsigned int rsrc_mask = 1 << i2s_regs->rclksrc_off;
u32 mod, mask, val = 0;
unsigned long flags;
int ret = 0;
pm_runtime_get_sync(dai->dev);
spin_lock_irqsave(&priv->lock, flags);
mod = readl(priv->addr + I2SMOD);
spin_unlock_irqrestore(&priv->lock, flags);
switch (clk_id) {
case SAMSUNG_I2S_OPCLK:
mask = MOD_OPCLK_MASK;
val = (dir << MOD_OPCLK_SHIFT) & MOD_OPCLK_MASK;
break;
case SAMSUNG_I2S_CDCLK:
mask = 1 << i2s_regs->cdclkcon_off;
/* Shouldn't matter in GATING(CLOCK_IN) mode */
if (dir == SND_SOC_CLOCK_IN)
rfs = 0;
if ((rfs && other && other->rfs && (other->rfs != rfs)) ||
(any_active(i2s) &&
(((dir == SND_SOC_CLOCK_IN)
&& !(mod & cdcon_mask)) ||
((dir == SND_SOC_CLOCK_OUT)
&& (mod & cdcon_mask))))) {
dev_err(&i2s->pdev->dev,
"%s:%d Other DAI busy\n", __func__, __LINE__);
ret = -EAGAIN;
goto err;
}
if (dir == SND_SOC_CLOCK_IN)
val = 1 << i2s_regs->cdclkcon_off;
i2s->rfs = rfs;
break;
case SAMSUNG_I2S_RCLKSRC_0: /* clock corrsponding to IISMOD[10] := 0 */
case SAMSUNG_I2S_RCLKSRC_1: /* clock corrsponding to IISMOD[10] := 1 */
mask = 1 << i2s_regs->rclksrc_off;
if ((priv->quirks & QUIRK_NO_MUXPSR)
|| (clk_id == SAMSUNG_I2S_RCLKSRC_0))
clk_id = 0;
else
clk_id = 1;
if (!any_active(i2s)) {
if (priv->op_clk && !IS_ERR(priv->op_clk)) {
if ((clk_id && !(mod & rsrc_mask)) ||
(!clk_id && (mod & rsrc_mask))) {
clk_disable_unprepare(priv->op_clk);
clk_put(priv->op_clk);
} else {
priv->rclk_srcrate =
clk_get_rate(priv->op_clk);
goto done;
}
}
if (clk_id)
priv->op_clk = clk_get(&i2s->pdev->dev,
"i2s_opclk1");
else
priv->op_clk = clk_get(&i2s->pdev->dev,
"i2s_opclk0");
if (WARN_ON(IS_ERR(priv->op_clk))) {
ret = PTR_ERR(priv->op_clk);
priv->op_clk = NULL;
goto err;
}
ret = clk_prepare_enable(priv->op_clk);
if (ret) {
clk_put(priv->op_clk);
priv->op_clk = NULL;
goto err;
}
priv->rclk_srcrate = clk_get_rate(priv->op_clk);
} else if ((!clk_id && (mod & rsrc_mask))
|| (clk_id && !(mod & rsrc_mask))) {
dev_err(&i2s->pdev->dev,
"%s:%d Other DAI busy\n", __func__, __LINE__);
ret = -EAGAIN;
goto err;
} else {
/* Call can't be on the active DAI */
goto done;
}
if (clk_id == 1)
val = 1 << i2s_regs->rclksrc_off;
break;
default:
dev_err(&i2s->pdev->dev, "We don't serve that!\n");
ret = -EINVAL;
goto err;
}
spin_lock_irqsave(&priv->lock, flags);
mod = readl(priv->addr + I2SMOD);
mod = (mod & ~mask) | val;
writel(mod, priv->addr + I2SMOD);
spin_unlock_irqrestore(&priv->lock, flags);
done:
pm_runtime_put(dai->dev);
return 0;
err:
pm_runtime_put(dai->dev);
return ret;
}
static int i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct samsung_i2s_priv *priv = snd_soc_dai_get_drvdata(dai);
struct i2s_dai *i2s = to_info(dai);
int lrp_shift, sdf_shift, sdf_mask, lrp_rlow, mod_slave;
u32 mod, tmp = 0;
unsigned long flags;
lrp_shift = priv->variant_regs->lrp_off;
sdf_shift = priv->variant_regs->sdf_off;
mod_slave = 1 << priv->variant_regs->mss_off;
sdf_mask = MOD_SDF_MASK << sdf_shift;
lrp_rlow = MOD_LR_RLOW << lrp_shift;
/* Format is priority */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_RIGHT_J:
tmp |= lrp_rlow;
tmp |= (MOD_SDF_MSB << sdf_shift);
break;
case SND_SOC_DAIFMT_LEFT_J:
tmp |= lrp_rlow;
tmp |= (MOD_SDF_LSB << sdf_shift);
break;
case SND_SOC_DAIFMT_I2S:
tmp |= (MOD_SDF_IIS << sdf_shift);
break;
default:
dev_err(&i2s->pdev->dev, "Format not supported\n");
return -EINVAL;
}
/*
* INV flag is relative to the FORMAT flag - if set it simply
* flips the polarity specified by the Standard
*/
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_NB_IF:
if (tmp & lrp_rlow)
tmp &= ~lrp_rlow;
else
tmp |= lrp_rlow;
break;
default:
dev_err(&i2s->pdev->dev, "Polarity not supported\n");
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BC_FC:
tmp |= mod_slave;
break;
case SND_SOC_DAIFMT_BP_FP:
/*
* Set default source clock in Master mode, only when the
* CLK_I2S_RCLK_SRC clock is not exposed so we ensure any
* clock configuration assigned in DT is not overwritten.
*/
if (priv->rclk_srcrate == 0 && priv->clk_data.clks == NULL)
i2s_set_sysclk(dai, SAMSUNG_I2S_RCLKSRC_0,
0, SND_SOC_CLOCK_IN);
break;
default:
dev_err(&i2s->pdev->dev, "master/slave format not supported\n");
return -EINVAL;
}
pm_runtime_get_sync(dai->dev);
spin_lock_irqsave(&priv->lock, flags);
mod = readl(priv->addr + I2SMOD);
/*
* Don't change the I2S mode if any controller is active on this
* channel.
*/
if (any_active(i2s) &&
((mod & (sdf_mask | lrp_rlow | mod_slave)) != tmp)) {
spin_unlock_irqrestore(&priv->lock, flags);
pm_runtime_put(dai->dev);
dev_err(&i2s->pdev->dev,
"%s:%d Other DAI busy\n", __func__, __LINE__);
return -EAGAIN;
}
mod &= ~(sdf_mask | lrp_rlow | mod_slave);
mod |= tmp;
writel(mod, priv->addr + I2SMOD);
priv->slave_mode = (mod & mod_slave);
spin_unlock_irqrestore(&priv->lock, flags);
pm_runtime_put(dai->dev);
return 0;
}
static int i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct samsung_i2s_priv *priv = snd_soc_dai_get_drvdata(dai);
struct i2s_dai *i2s = to_info(dai);
u32 mod, mask = 0, val = 0;
struct clk *rclksrc;
unsigned long flags;
WARN_ON(!pm_runtime_active(dai->dev));
if (!is_secondary(i2s))
mask |= (MOD_DC2_EN | MOD_DC1_EN);
switch (params_channels(params)) {
case 6:
val |= MOD_DC2_EN;
fallthrough;
case 4:
val |= MOD_DC1_EN;
break;
case 2:
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
i2s->dma_playback.addr_width = 4;
else
i2s->dma_capture.addr_width = 4;
break;
case 1:
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
i2s->dma_playback.addr_width = 2;
else
i2s->dma_capture.addr_width = 2;
break;
default:
dev_err(&i2s->pdev->dev, "%d channels not supported\n",
params_channels(params));
return -EINVAL;
}
if (is_secondary(i2s))
mask |= MOD_BLCS_MASK;
else
mask |= MOD_BLCP_MASK;
if (is_manager(i2s))
mask |= MOD_BLC_MASK;
switch (params_width(params)) {
case 8:
if (is_secondary(i2s))
val |= MOD_BLCS_8BIT;
else
val |= MOD_BLCP_8BIT;
if (is_manager(i2s))
val |= MOD_BLC_8BIT;
break;
case 16:
if (is_secondary(i2s))
val |= MOD_BLCS_16BIT;
else
val |= MOD_BLCP_16BIT;
if (is_manager(i2s))
val |= MOD_BLC_16BIT;
break;
case 24:
if (is_secondary(i2s))
val |= MOD_BLCS_24BIT;
else
val |= MOD_BLCP_24BIT;
if (is_manager(i2s))
val |= MOD_BLC_24BIT;
break;
default:
dev_err(&i2s->pdev->dev, "Format(%d) not supported\n",
params_format(params));
return -EINVAL;
}
spin_lock_irqsave(&priv->lock, flags);
mod = readl(priv->addr + I2SMOD);
mod = (mod & ~mask) | val;
writel(mod, priv->addr + I2SMOD);
spin_unlock_irqrestore(&priv->lock, flags);
snd_soc_dai_init_dma_data(dai, &i2s->dma_playback, &i2s->dma_capture);
i2s->frmclk = params_rate(params);
rclksrc = priv->clk_table[CLK_I2S_RCLK_SRC];
if (rclksrc && !IS_ERR(rclksrc))
priv->rclk_srcrate = clk_get_rate(rclksrc);
return 0;
}
/* We set constraints on the substream according to the version of I2S */
static int i2s_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct samsung_i2s_priv *priv = snd_soc_dai_get_drvdata(dai);
struct i2s_dai *i2s = to_info(dai);
struct i2s_dai *other = get_other_dai(i2s);
unsigned long flags;
pm_runtime_get_sync(dai->dev);
spin_lock_irqsave(&priv->pcm_lock, flags);
i2s->mode |= DAI_OPENED;
if (is_manager(other))
i2s->mode &= ~DAI_MANAGER;
else
i2s->mode |= DAI_MANAGER;
if (!any_active(i2s) && (priv->quirks & QUIRK_NEED_RSTCLR))
writel(CON_RSTCLR, i2s->priv->addr + I2SCON);
spin_unlock_irqrestore(&priv->pcm_lock, flags);
return 0;
}
static void i2s_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct samsung_i2s_priv *priv = snd_soc_dai_get_drvdata(dai);
struct i2s_dai *i2s = to_info(dai);
struct i2s_dai *other = get_other_dai(i2s);
unsigned long flags;
spin_lock_irqsave(&priv->pcm_lock, flags);
i2s->mode &= ~DAI_OPENED;
i2s->mode &= ~DAI_MANAGER;
if (is_opened(other))
other->mode |= DAI_MANAGER;
/* Reset any constraint on RFS and BFS */
i2s->rfs = 0;
i2s->bfs = 0;
spin_unlock_irqrestore(&priv->pcm_lock, flags);
pm_runtime_put(dai->dev);
}
static int config_setup(struct i2s_dai *i2s)
{
struct samsung_i2s_priv *priv = i2s->priv;
struct i2s_dai *other = get_other_dai(i2s);
unsigned rfs, bfs, blc;
u32 psr;
blc = get_blc(i2s);
bfs = i2s->bfs;
if (!bfs && other)
bfs = other->bfs;
/* Select least possible multiple(2) if no constraint set */
if (!bfs)
bfs = blc * 2;
rfs = i2s->rfs;
if (!rfs && other)
rfs = other->rfs;
if ((rfs == 256 || rfs == 512) && (blc == 24)) {
dev_err(&i2s->pdev->dev,
"%d-RFS not supported for 24-blc\n", rfs);
return -EINVAL;
}
if (!rfs) {
if (bfs == 16 || bfs == 32)
rfs = 256;
else
rfs = 384;
}
/* If already setup and running */
if (any_active(i2s) && (get_rfs(i2s) != rfs || get_bfs(i2s) != bfs)) {
dev_err(&i2s->pdev->dev,
"%s:%d Other DAI busy\n", __func__, __LINE__);
return -EAGAIN;
}
set_bfs(i2s, bfs);
set_rfs(i2s, rfs);
/* Don't bother with PSR in Slave mode */
if (priv->slave_mode)
return 0;
if (!(priv->quirks & QUIRK_NO_MUXPSR)) {
psr = priv->rclk_srcrate / i2s->frmclk / rfs;
writel(((psr - 1) << 8) | PSR_PSREN, priv->addr + I2SPSR);
dev_dbg(&i2s->pdev->dev,
"RCLK_SRC=%luHz PSR=%u, RCLK=%dfs, BCLK=%dfs\n",
priv->rclk_srcrate, psr, rfs, bfs);
}
return 0;
}
static int i2s_trigger(struct snd_pcm_substream *substream,
int cmd, struct snd_soc_dai *dai)
{
struct samsung_i2s_priv *priv = snd_soc_dai_get_drvdata(dai);
int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct i2s_dai *i2s = to_info(asoc_rtd_to_cpu(rtd, 0));
unsigned long flags;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
pm_runtime_get_sync(dai->dev);
if (priv->fixup_early)
priv->fixup_early(substream, dai);
spin_lock_irqsave(&priv->lock, flags);
if (config_setup(i2s)) {
spin_unlock_irqrestore(&priv->lock, flags);
return -EINVAL;
}
if (priv->fixup_late)
priv->fixup_late(substream, dai);
if (capture)
i2s_rxctrl(i2s, 1);
else
i2s_txctrl(i2s, 1);
spin_unlock_irqrestore(&priv->lock, flags);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
spin_lock_irqsave(&priv->lock, flags);
if (capture) {
i2s_rxctrl(i2s, 0);
i2s_fifo(i2s, FIC_RXFLUSH);
} else {
i2s_txctrl(i2s, 0);
i2s_fifo(i2s, FIC_TXFLUSH);
}
spin_unlock_irqrestore(&priv->lock, flags);
pm_runtime_put(dai->dev);
break;
}
return 0;
}
static int i2s_set_clkdiv(struct snd_soc_dai *dai,
int div_id, int div)
{
struct i2s_dai *i2s = to_info(dai);
struct i2s_dai *other = get_other_dai(i2s);
switch (div_id) {
case SAMSUNG_I2S_DIV_BCLK:
pm_runtime_get_sync(dai->dev);
if ((any_active(i2s) && div && (get_bfs(i2s) != div))
|| (other && other->bfs && (other->bfs != div))) {
pm_runtime_put(dai->dev);
dev_err(&i2s->pdev->dev,
"%s:%d Other DAI busy\n", __func__, __LINE__);
return -EAGAIN;
}
i2s->bfs = div;
pm_runtime_put(dai->dev);
break;
default:
dev_err(&i2s->pdev->dev,
"Invalid clock divider(%d)\n", div_id);
return -EINVAL;
}
return 0;
}
static snd_pcm_sframes_t
i2s_delay(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
{
struct samsung_i2s_priv *priv = snd_soc_dai_get_drvdata(dai);
struct i2s_dai *i2s = to_info(dai);
u32 reg = readl(priv->addr + I2SFIC);
snd_pcm_sframes_t delay;
WARN_ON(!pm_runtime_active(dai->dev));
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
delay = FIC_RXCOUNT(reg);
else if (is_secondary(i2s))
delay = FICS_TXCOUNT(readl(priv->addr + I2SFICS));
else
delay = (reg >> priv->variant_regs->ftx0cnt_off) & 0x7f;
return delay;
}
#ifdef CONFIG_PM
static int i2s_suspend(struct snd_soc_component *component)
{
return pm_runtime_force_suspend(component->dev);
}
static int i2s_resume(struct snd_soc_component *component)
{
return pm_runtime_force_resume(component->dev);
}
#else
#define i2s_suspend NULL
#define i2s_resume NULL
#endif
static int samsung_i2s_dai_probe(struct snd_soc_dai *dai)
{
struct samsung_i2s_priv *priv = snd_soc_dai_get_drvdata(dai);
struct i2s_dai *i2s = to_info(dai);
struct i2s_dai *other = get_other_dai(i2s);
unsigned long flags;
pm_runtime_get_sync(dai->dev);
if (is_secondary(i2s)) {
/* If this is probe on the secondary DAI */
snd_soc_dai_init_dma_data(dai, &i2s->dma_playback, NULL);
} else {
snd_soc_dai_init_dma_data(dai, &i2s->dma_playback,
&i2s->dma_capture);
if (priv->quirks & QUIRK_NEED_RSTCLR)
writel(CON_RSTCLR, priv->addr + I2SCON);
if (priv->quirks & QUIRK_SUPPORTS_IDMA)
idma_reg_addr_init(priv->addr,
other->idma_playback.addr);
}
/* Reset any constraint on RFS and BFS */
i2s->rfs = 0;
i2s->bfs = 0;
spin_lock_irqsave(&priv->lock, flags);
i2s_txctrl(i2s, 0);
i2s_rxctrl(i2s, 0);
i2s_fifo(i2s, FIC_TXFLUSH);
i2s_fifo(other, FIC_TXFLUSH);
i2s_fifo(i2s, FIC_RXFLUSH);
spin_unlock_irqrestore(&priv->lock, flags);
/* Gate CDCLK by default */
if (!is_opened(other))
i2s_set_sysclk(dai, SAMSUNG_I2S_CDCLK,
0, SND_SOC_CLOCK_IN);
pm_runtime_put(dai->dev);
return 0;
}
static int samsung_i2s_dai_remove(struct snd_soc_dai *dai)
{
struct samsung_i2s_priv *priv = snd_soc_dai_get_drvdata(dai);
struct i2s_dai *i2s = to_info(dai);
unsigned long flags;
pm_runtime_get_sync(dai->dev);
if (!is_secondary(i2s)) {
if (priv->quirks & QUIRK_NEED_RSTCLR) {
spin_lock_irqsave(&priv->lock, flags);
writel(0, priv->addr + I2SCON);
spin_unlock_irqrestore(&priv->lock, flags);
}
}
pm_runtime_put(dai->dev);
return 0;
}
static const struct snd_soc_dai_ops samsung_i2s_dai_ops = {
.probe = samsung_i2s_dai_probe,
.remove = samsung_i2s_dai_remove,
.trigger = i2s_trigger,
.hw_params = i2s_hw_params,
.set_fmt = i2s_set_fmt,
.set_clkdiv = i2s_set_clkdiv,
.set_sysclk = i2s_set_sysclk,
.startup = i2s_startup,
.shutdown = i2s_shutdown,
.delay = i2s_delay,
};
static const struct snd_soc_dapm_widget samsung_i2s_widgets[] = {
/* Backend DAI */
SND_SOC_DAPM_AIF_OUT("Mixer DAI TX", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("Mixer DAI RX", NULL, 0, SND_SOC_NOPM, 0, 0),
/* Playback Mixer */
SND_SOC_DAPM_MIXER("Playback Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
};
static const struct snd_soc_dapm_route samsung_i2s_dapm_routes[] = {
{ "Playback Mixer", NULL, "Primary Playback" },
{ "Playback Mixer", NULL, "Secondary Playback" },
{ "Mixer DAI TX", NULL, "Playback Mixer" },
{ "Primary Capture", NULL, "Mixer DAI RX" },
};
static const struct snd_soc_component_driver samsung_i2s_component = {
.name = "samsung-i2s",
.dapm_widgets = samsung_i2s_widgets,
.num_dapm_widgets = ARRAY_SIZE(samsung_i2s_widgets),
.dapm_routes = samsung_i2s_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(samsung_i2s_dapm_routes),
.suspend = i2s_suspend,
.resume = i2s_resume,
.legacy_dai_naming = 1,
};
#define SAMSUNG_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE)
static int i2s_alloc_dais(struct samsung_i2s_priv *priv,
const struct samsung_i2s_dai_data *i2s_dai_data,
int num_dais)
{
static const char *dai_names[] = { "samsung-i2s", "samsung-i2s-sec" };
static const char *stream_names[] = { "Primary Playback",
"Secondary Playback" };
struct snd_soc_dai_driver *dai_drv;
int i;
priv->dai = devm_kcalloc(&priv->pdev->dev, num_dais,
sizeof(struct i2s_dai), GFP_KERNEL);
if (!priv->dai)
return -ENOMEM;
priv->dai_drv = devm_kcalloc(&priv->pdev->dev, num_dais,
sizeof(*dai_drv), GFP_KERNEL);
if (!priv->dai_drv)
return -ENOMEM;
for (i = 0; i < num_dais; i++) {
dai_drv = &priv->dai_drv[i];
dai_drv->symmetric_rate = 1;
dai_drv->ops = &samsung_i2s_dai_ops;
dai_drv->playback.channels_min = 1;
dai_drv->playback.channels_max = 2;
dai_drv->playback.rates = i2s_dai_data->pcm_rates;
dai_drv->playback.formats = SAMSUNG_I2S_FMTS;
dai_drv->playback.stream_name = stream_names[i];
dai_drv->id = i + 1;
dai_drv->name = dai_names[i];
priv->dai[i].drv = &priv->dai_drv[i];
priv->dai[i].pdev = priv->pdev;
}
/* Initialize capture only for the primary DAI */
dai_drv = &priv->dai_drv[SAMSUNG_I2S_ID_PRIMARY - 1];
dai_drv->capture.channels_min = 1;
dai_drv->capture.channels_max = 2;
dai_drv->capture.rates = i2s_dai_data->pcm_rates;
dai_drv->capture.formats = SAMSUNG_I2S_FMTS;
dai_drv->capture.stream_name = "Primary Capture";
return 0;
}
#ifdef CONFIG_PM
static int i2s_runtime_suspend(struct device *dev)
{
struct samsung_i2s_priv *priv = dev_get_drvdata(dev);
priv->suspend_i2smod = readl(priv->addr + I2SMOD);
priv->suspend_i2scon = readl(priv->addr + I2SCON);
priv->suspend_i2spsr = readl(priv->addr + I2SPSR);
clk_disable_unprepare(priv->op_clk);
clk_disable_unprepare(priv->clk);
return 0;
}
static int i2s_runtime_resume(struct device *dev)
{
struct samsung_i2s_priv *priv = dev_get_drvdata(dev);
int ret;
ret = clk_prepare_enable(priv->clk);
if (ret)
return ret;
if (priv->op_clk) {
ret = clk_prepare_enable(priv->op_clk);
if (ret) {
clk_disable_unprepare(priv->clk);
return ret;
}
}
writel(priv->suspend_i2scon, priv->addr + I2SCON);
writel(priv->suspend_i2smod, priv->addr + I2SMOD);
writel(priv->suspend_i2spsr, priv->addr + I2SPSR);
return 0;
}
#endif /* CONFIG_PM */
static void i2s_unregister_clocks(struct samsung_i2s_priv *priv)
{
int i;
for (i = 0; i < priv->clk_data.clk_num; i++) {
if (!IS_ERR(priv->clk_table[i]))
clk_unregister(priv->clk_table[i]);
}
}
static void i2s_unregister_clock_provider(struct samsung_i2s_priv *priv)
{
of_clk_del_provider(priv->pdev->dev.of_node);
i2s_unregister_clocks(priv);
}
static int i2s_register_clock_provider(struct samsung_i2s_priv *priv)
{
const char * const i2s_clk_desc[] = { "cdclk", "rclk_src", "prescaler" };
const char *clk_name[2] = { "i2s_opclk0", "i2s_opclk1" };
const char *p_names[2] = { NULL };
struct device *dev = &priv->pdev->dev;
const struct samsung_i2s_variant_regs *reg_info = priv->variant_regs;
const char *i2s_clk_name[ARRAY_SIZE(i2s_clk_desc)];
struct clk *rclksrc;
int ret, i;
/* Register the clock provider only if it's expected in the DTB */
if (!of_property_present(dev->of_node, "#clock-cells"))
return 0;
/* Get the RCLKSRC mux clock parent clock names */
for (i = 0; i < ARRAY_SIZE(p_names); i++) {
rclksrc = clk_get(dev, clk_name[i]);
if (IS_ERR(rclksrc))
continue;
p_names[i] = __clk_get_name(rclksrc);
clk_put(rclksrc);
}
for (i = 0; i < ARRAY_SIZE(i2s_clk_desc); i++) {
i2s_clk_name[i] = devm_kasprintf(dev, GFP_KERNEL, "%s_%s",
dev_name(dev), i2s_clk_desc[i]);
if (!i2s_clk_name[i])
return -ENOMEM;
}
if (!(priv->quirks & QUIRK_NO_MUXPSR)) {
/* Activate the prescaler */
u32 val = readl(priv->addr + I2SPSR);
writel(val | PSR_PSREN, priv->addr + I2SPSR);
priv->clk_table[CLK_I2S_RCLK_SRC] = clk_register_mux(dev,
i2s_clk_name[CLK_I2S_RCLK_SRC], p_names,
ARRAY_SIZE(p_names),
CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
priv->addr + I2SMOD, reg_info->rclksrc_off,
1, 0, &priv->lock);
priv->clk_table[CLK_I2S_RCLK_PSR] = clk_register_divider(dev,
i2s_clk_name[CLK_I2S_RCLK_PSR],
i2s_clk_name[CLK_I2S_RCLK_SRC],
CLK_SET_RATE_PARENT,
priv->addr + I2SPSR, 8, 6, 0, &priv->lock);
p_names[0] = i2s_clk_name[CLK_I2S_RCLK_PSR];
priv->clk_data.clk_num = 2;
}
priv->clk_table[CLK_I2S_CDCLK] = clk_register_gate(dev,
i2s_clk_name[CLK_I2S_CDCLK], p_names[0],
CLK_SET_RATE_PARENT,
priv->addr + I2SMOD, reg_info->cdclkcon_off,
CLK_GATE_SET_TO_DISABLE, &priv->lock);
priv->clk_data.clk_num += 1;
priv->clk_data.clks = priv->clk_table;
ret = of_clk_add_provider(dev->of_node, of_clk_src_onecell_get,
&priv->clk_data);
if (ret < 0) {
dev_err(dev, "failed to add clock provider: %d\n", ret);
i2s_unregister_clocks(priv);
}
return ret;
}
/* Create platform device for the secondary PCM */
static int i2s_create_secondary_device(struct samsung_i2s_priv *priv)
{
struct platform_device *pdev_sec;
const char *devname;
int ret;
devname = devm_kasprintf(&priv->pdev->dev, GFP_KERNEL, "%s-sec",
dev_name(&priv->pdev->dev));
if (!devname)
return -ENOMEM;
pdev_sec = platform_device_alloc(devname, -1);
if (!pdev_sec)
return -ENOMEM;
pdev_sec->driver_override = kstrdup("samsung-i2s", GFP_KERNEL);
if (!pdev_sec->driver_override) {
platform_device_put(pdev_sec);
return -ENOMEM;
}
ret = platform_device_add(pdev_sec);
if (ret < 0) {
platform_device_put(pdev_sec);
return ret;
}
ret = device_attach(&pdev_sec->dev);
if (ret <= 0) {
platform_device_unregister(priv->pdev_sec);
dev_info(&pdev_sec->dev, "device_attach() failed\n");
return ret;
}
priv->pdev_sec = pdev_sec;
return 0;
}
static void i2s_delete_secondary_device(struct samsung_i2s_priv *priv)
{
platform_device_unregister(priv->pdev_sec);
priv->pdev_sec = NULL;
}
static int samsung_i2s_probe(struct platform_device *pdev)
{
struct i2s_dai *pri_dai, *sec_dai = NULL;
struct s3c_audio_pdata *i2s_pdata = pdev->dev.platform_data;
u32 regs_base, idma_addr = 0;
struct device_node *np = pdev->dev.of_node;
const struct samsung_i2s_dai_data *i2s_dai_data;
const struct platform_device_id *id;
struct samsung_i2s_priv *priv;
struct resource *res;
int num_dais, ret;
if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
i2s_dai_data = of_device_get_match_data(&pdev->dev);
} else {
id = platform_get_device_id(pdev);
/* Nothing to do if it is the secondary device probe */
if (!id)
return 0;
i2s_dai_data = (struct samsung_i2s_dai_data *)id->driver_data;
}
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
if (np) {
priv->quirks = i2s_dai_data->quirks;
priv->fixup_early = i2s_dai_data->fixup_early;
priv->fixup_late = i2s_dai_data->fixup_late;
} else {
if (!i2s_pdata) {
dev_err(&pdev->dev, "Missing platform data\n");
return -EINVAL;
}
priv->quirks = i2s_pdata->type.quirks;
}
num_dais = (priv->quirks & QUIRK_SEC_DAI) ? 2 : 1;
priv->pdev = pdev;
priv->variant_regs = i2s_dai_data->i2s_variant_regs;
ret = i2s_alloc_dais(priv, i2s_dai_data, num_dais);
if (ret < 0)
return ret;
pri_dai = &priv->dai[SAMSUNG_I2S_ID_PRIMARY - 1];
spin_lock_init(&priv->lock);
spin_lock_init(&priv->pcm_lock);
if (!np) {
pri_dai->dma_playback.filter_data = i2s_pdata->dma_playback;
pri_dai->dma_capture.filter_data = i2s_pdata->dma_capture;
pri_dai->filter = i2s_pdata->dma_filter;
idma_addr = i2s_pdata->type.idma_addr;
} else {
if (of_property_read_u32(np, "samsung,idma-addr",
&idma_addr)) {
if (priv->quirks & QUIRK_SUPPORTS_IDMA) {
dev_info(&pdev->dev, "idma address is not"\
"specified");
}
}
}
priv->addr = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(priv->addr))
return PTR_ERR(priv->addr);
regs_base = res->start;
priv->clk = devm_clk_get(&pdev->dev, "iis");
if (IS_ERR(priv->clk)) {
dev_err(&pdev->dev, "Failed to get iis clock\n");
return PTR_ERR(priv->clk);
}
ret = clk_prepare_enable(priv->clk);
if (ret != 0) {
dev_err(&pdev->dev, "failed to enable clock: %d\n", ret);
return ret;
}
pri_dai->dma_playback.addr = regs_base + I2STXD;
pri_dai->dma_capture.addr = regs_base + I2SRXD;
pri_dai->dma_playback.chan_name = "tx";
pri_dai->dma_capture.chan_name = "rx";
pri_dai->dma_playback.addr_width = 4;
pri_dai->dma_capture.addr_width = 4;
pri_dai->priv = priv;
if (priv->quirks & QUIRK_PRI_6CHAN)
pri_dai->drv->playback.channels_max = 6;
ret = samsung_asoc_dma_platform_register(&pdev->dev, pri_dai->filter,
"tx", "rx", NULL);
if (ret < 0)
goto err_disable_clk;
if (priv->quirks & QUIRK_SEC_DAI) {
sec_dai = &priv->dai[SAMSUNG_I2S_ID_SECONDARY - 1];
sec_dai->dma_playback.addr = regs_base + I2STXDS;
sec_dai->dma_playback.chan_name = "tx-sec";
if (!np) {
sec_dai->dma_playback.filter_data = i2s_pdata->dma_play_sec;
sec_dai->filter = i2s_pdata->dma_filter;
}
sec_dai->dma_playback.addr_width = 4;
sec_dai->idma_playback.addr = idma_addr;
sec_dai->pri_dai = pri_dai;
sec_dai->priv = priv;
pri_dai->sec_dai = sec_dai;
ret = i2s_create_secondary_device(priv);
if (ret < 0)
goto err_disable_clk;
ret = samsung_asoc_dma_platform_register(&priv->pdev_sec->dev,
sec_dai->filter, "tx-sec", NULL,
&pdev->dev);
if (ret < 0)
goto err_del_sec;
}
if (i2s_pdata && i2s_pdata->cfg_gpio && i2s_pdata->cfg_gpio(pdev)) {
dev_err(&pdev->dev, "Unable to configure gpio\n");
ret = -EINVAL;
goto err_del_sec;
}
dev_set_drvdata(&pdev->dev, priv);
ret = devm_snd_soc_register_component(&pdev->dev,
&samsung_i2s_component,
priv->dai_drv, num_dais);
if (ret < 0)
goto err_del_sec;
pm_runtime_set_active(&pdev->dev);
pm_runtime_enable(&pdev->dev);
ret = i2s_register_clock_provider(priv);
if (ret < 0)
goto err_disable_pm;
priv->op_clk = clk_get_parent(priv->clk_table[CLK_I2S_RCLK_SRC]);
return 0;
err_disable_pm:
pm_runtime_disable(&pdev->dev);
err_del_sec:
i2s_delete_secondary_device(priv);
err_disable_clk:
clk_disable_unprepare(priv->clk);
return ret;
}
static void samsung_i2s_remove(struct platform_device *pdev)
{
struct samsung_i2s_priv *priv = dev_get_drvdata(&pdev->dev);
/* The secondary device has no driver data assigned */
if (!priv)
return;
pm_runtime_get_sync(&pdev->dev);
pm_runtime_disable(&pdev->dev);
i2s_unregister_clock_provider(priv);
i2s_delete_secondary_device(priv);
clk_disable_unprepare(priv->clk);
pm_runtime_put_noidle(&pdev->dev);
}
static void fsd_i2s_fixup_early(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct i2s_dai *i2s = to_info(asoc_rtd_to_cpu(rtd, 0));
struct i2s_dai *other = get_other_dai(i2s);
if (!is_opened(other)) {
i2s_set_sysclk(dai, SAMSUNG_I2S_CDCLK, 0, SND_SOC_CLOCK_OUT);
i2s_set_sysclk(dai, SAMSUNG_I2S_OPCLK, 0, MOD_OPCLK_PCLK);
}
}
static void fsd_i2s_fixup_late(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct samsung_i2s_priv *priv = snd_soc_dai_get_drvdata(dai);
struct i2s_dai *i2s = to_info(asoc_rtd_to_cpu(rtd, 0));
struct i2s_dai *other = get_other_dai(i2s);
if (!is_opened(other))
writel(PSR_PSVAL(2) | PSR_PSREN, priv->addr + I2SPSR);
}
static const struct samsung_i2s_variant_regs i2sv3_regs = {
.bfs_off = 1,
.rfs_off = 3,
.sdf_off = 5,
.txr_off = 8,
.rclksrc_off = 10,
.mss_off = 11,
.cdclkcon_off = 12,
.lrp_off = 7,
.bfs_mask = 0x3,
.rfs_mask = 0x3,
.ftx0cnt_off = 8,
};
static const struct samsung_i2s_variant_regs i2sv6_regs = {
.bfs_off = 0,
.rfs_off = 4,
.sdf_off = 6,
.txr_off = 8,
.rclksrc_off = 10,
.mss_off = 11,
.cdclkcon_off = 12,
.lrp_off = 15,
.bfs_mask = 0xf,
.rfs_mask = 0x3,
.ftx0cnt_off = 8,
};
static const struct samsung_i2s_variant_regs i2sv7_regs = {
.bfs_off = 0,
.rfs_off = 4,
.sdf_off = 7,
.txr_off = 9,
.rclksrc_off = 11,
.mss_off = 12,
.cdclkcon_off = 22,
.lrp_off = 15,
.bfs_mask = 0xf,
.rfs_mask = 0x7,
.ftx0cnt_off = 0,
};
static const struct samsung_i2s_variant_regs i2sv5_i2s1_regs = {
.bfs_off = 0,
.rfs_off = 3,
.sdf_off = 6,
.txr_off = 8,
.rclksrc_off = 10,
.mss_off = 11,
.cdclkcon_off = 12,
.lrp_off = 15,
.bfs_mask = 0x7,
.rfs_mask = 0x7,
.ftx0cnt_off = 8,
};
static const struct samsung_i2s_dai_data i2sv3_dai_type = {
.quirks = QUIRK_NO_MUXPSR,
.pcm_rates = SNDRV_PCM_RATE_8000_96000,
.i2s_variant_regs = &i2sv3_regs,
};
static const struct samsung_i2s_dai_data i2sv5_dai_type __maybe_unused = {
.quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR |
QUIRK_SUPPORTS_IDMA,
.pcm_rates = SNDRV_PCM_RATE_8000_96000,
.i2s_variant_regs = &i2sv3_regs,
};
static const struct samsung_i2s_dai_data i2sv6_dai_type __maybe_unused = {
.quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR |
QUIRK_SUPPORTS_TDM | QUIRK_SUPPORTS_IDMA,
.pcm_rates = SNDRV_PCM_RATE_8000_96000,
.i2s_variant_regs = &i2sv6_regs,
};
static const struct samsung_i2s_dai_data i2sv7_dai_type __maybe_unused = {
.quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR |
QUIRK_SUPPORTS_TDM,
.pcm_rates = SNDRV_PCM_RATE_8000_192000,
.i2s_variant_regs = &i2sv7_regs,
};
static const struct samsung_i2s_dai_data i2sv5_dai_type_i2s1 __maybe_unused = {
.quirks = QUIRK_PRI_6CHAN | QUIRK_NEED_RSTCLR,
.pcm_rates = SNDRV_PCM_RATE_8000_96000,
.i2s_variant_regs = &i2sv5_i2s1_regs,
};
static const struct samsung_i2s_dai_data fsd_dai_type __maybe_unused = {
.quirks = QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR | QUIRK_SUPPORTS_TDM,
.pcm_rates = SNDRV_PCM_RATE_8000_192000,
.i2s_variant_regs = &i2sv7_regs,
.fixup_early = fsd_i2s_fixup_early,
.fixup_late = fsd_i2s_fixup_late,
};
static const struct platform_device_id samsung_i2s_driver_ids[] = {
{
.name = "samsung-i2s",
.driver_data = (kernel_ulong_t)&i2sv3_dai_type,
},
{},
};
MODULE_DEVICE_TABLE(platform, samsung_i2s_driver_ids);
#ifdef CONFIG_OF
static const struct of_device_id exynos_i2s_match[] = {
{
.compatible = "samsung,s3c6410-i2s",
.data = &i2sv3_dai_type,
}, {
.compatible = "samsung,s5pv210-i2s",
.data = &i2sv5_dai_type,
}, {
.compatible = "samsung,exynos5420-i2s",
.data = &i2sv6_dai_type,
}, {
.compatible = "samsung,exynos7-i2s",
.data = &i2sv7_dai_type,
}, {
.compatible = "samsung,exynos7-i2s1",
.data = &i2sv5_dai_type_i2s1,
}, {
.compatible = "tesla,fsd-i2s",
.data = &fsd_dai_type,
},
{},
};
MODULE_DEVICE_TABLE(of, exynos_i2s_match);
#endif
static const struct dev_pm_ops samsung_i2s_pm = {
SET_RUNTIME_PM_OPS(i2s_runtime_suspend,
i2s_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
};
static struct platform_driver samsung_i2s_driver = {
.probe = samsung_i2s_probe,
.remove_new = samsung_i2s_remove,
.id_table = samsung_i2s_driver_ids,
.driver = {
.name = "samsung-i2s",
.of_match_table = of_match_ptr(exynos_i2s_match),
.pm = &samsung_i2s_pm,
},
};
module_platform_driver(samsung_i2s_driver);
/* Module information */
MODULE_AUTHOR("Jaswinder Singh, <[email protected]>");
MODULE_DESCRIPTION("Samsung I2S Interface");
MODULE_ALIAS("platform:samsung-i2s");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/samsung/i2s.c |
// SPDX-License-Identifier: GPL-2.0+
//
// Bells audio support
//
// Copyright 2012 Wolfson Microelectronics
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/jack.h>
#include <linux/gpio.h>
#include <linux/module.h>
#include "../codecs/wm5102.h"
#include "../codecs/wm9081.h"
/* BCLK2 is fixed at this currently */
#define BCLK2_RATE (64 * 8000)
/*
* Expect a 24.576MHz crystal if one is fitted (the driver will function
* if this is not fitted).
*/
#define MCLK_RATE 24576000
#define SYS_AUDIO_RATE 44100
#define SYS_MCLK_RATE (SYS_AUDIO_RATE * 512)
#define DAI_AP_DSP 0
#define DAI_DSP_CODEC 1
#define DAI_CODEC_CP 2
#define DAI_CODEC_SUB 3
struct bells_drvdata {
int sysclk_rate;
int asyncclk_rate;
};
static struct bells_drvdata wm2200_drvdata = {
.sysclk_rate = 22579200,
};
static struct bells_drvdata wm5102_drvdata = {
.sysclk_rate = 45158400,
.asyncclk_rate = 49152000,
};
static struct bells_drvdata wm5110_drvdata = {
.sysclk_rate = 135475200,
.asyncclk_rate = 147456000,
};
static int bells_set_bias_level(struct snd_soc_card *card,
struct snd_soc_dapm_context *dapm,
enum snd_soc_bias_level level)
{
struct snd_soc_pcm_runtime *rtd;
struct snd_soc_dai *codec_dai;
struct snd_soc_component *component;
struct bells_drvdata *bells = card->drvdata;
int ret;
rtd = snd_soc_get_pcm_runtime(card, &card->dai_link[DAI_DSP_CODEC]);
codec_dai = asoc_rtd_to_codec(rtd, 0);
component = codec_dai->component;
if (dapm->dev != codec_dai->dev)
return 0;
switch (level) {
case SND_SOC_BIAS_PREPARE:
if (dapm->bias_level != SND_SOC_BIAS_STANDBY)
break;
ret = snd_soc_component_set_pll(component, WM5102_FLL1,
ARIZONA_FLL_SRC_MCLK1,
MCLK_RATE,
bells->sysclk_rate);
if (ret < 0)
pr_err("Failed to start FLL: %d\n", ret);
if (bells->asyncclk_rate) {
ret = snd_soc_component_set_pll(component, WM5102_FLL2,
ARIZONA_FLL_SRC_AIF2BCLK,
BCLK2_RATE,
bells->asyncclk_rate);
if (ret < 0)
pr_err("Failed to start FLL: %d\n", ret);
}
break;
default:
break;
}
return 0;
}
static int bells_set_bias_level_post(struct snd_soc_card *card,
struct snd_soc_dapm_context *dapm,
enum snd_soc_bias_level level)
{
struct snd_soc_pcm_runtime *rtd;
struct snd_soc_dai *codec_dai;
struct snd_soc_component *component;
struct bells_drvdata *bells = card->drvdata;
int ret;
rtd = snd_soc_get_pcm_runtime(card, &card->dai_link[DAI_DSP_CODEC]);
codec_dai = asoc_rtd_to_codec(rtd, 0);
component = codec_dai->component;
if (dapm->dev != codec_dai->dev)
return 0;
switch (level) {
case SND_SOC_BIAS_STANDBY:
ret = snd_soc_component_set_pll(component, WM5102_FLL1, 0, 0, 0);
if (ret < 0) {
pr_err("Failed to stop FLL: %d\n", ret);
return ret;
}
if (bells->asyncclk_rate) {
ret = snd_soc_component_set_pll(component, WM5102_FLL2,
0, 0, 0);
if (ret < 0) {
pr_err("Failed to stop FLL: %d\n", ret);
return ret;
}
}
break;
default:
break;
}
dapm->bias_level = level;
return 0;
}
static int bells_late_probe(struct snd_soc_card *card)
{
struct bells_drvdata *bells = card->drvdata;
struct snd_soc_pcm_runtime *rtd;
struct snd_soc_component *wm0010;
struct snd_soc_component *component;
struct snd_soc_dai *aif1_dai;
struct snd_soc_dai *aif2_dai;
struct snd_soc_dai *aif3_dai;
struct snd_soc_dai *wm9081_dai;
int ret;
rtd = snd_soc_get_pcm_runtime(card, &card->dai_link[DAI_AP_DSP]);
wm0010 = asoc_rtd_to_codec(rtd, 0)->component;
rtd = snd_soc_get_pcm_runtime(card, &card->dai_link[DAI_DSP_CODEC]);
component = asoc_rtd_to_codec(rtd, 0)->component;
aif1_dai = asoc_rtd_to_codec(rtd, 0);
ret = snd_soc_component_set_sysclk(component, ARIZONA_CLK_SYSCLK,
ARIZONA_CLK_SRC_FLL1,
bells->sysclk_rate,
SND_SOC_CLOCK_IN);
if (ret != 0) {
dev_err(component->dev, "Failed to set SYSCLK: %d\n", ret);
return ret;
}
ret = snd_soc_component_set_sysclk(wm0010, 0, 0, SYS_MCLK_RATE, 0);
if (ret != 0) {
dev_err(wm0010->dev, "Failed to set WM0010 clock: %d\n", ret);
return ret;
}
ret = snd_soc_dai_set_sysclk(aif1_dai, ARIZONA_CLK_SYSCLK, 0, 0);
if (ret != 0)
dev_err(aif1_dai->dev, "Failed to set AIF1 clock: %d\n", ret);
ret = snd_soc_component_set_sysclk(component, ARIZONA_CLK_OPCLK, 0,
SYS_MCLK_RATE, SND_SOC_CLOCK_OUT);
if (ret != 0)
dev_err(component->dev, "Failed to set OPCLK: %d\n", ret);
if (card->num_rtd == DAI_CODEC_CP)
return 0;
ret = snd_soc_component_set_sysclk(component, ARIZONA_CLK_ASYNCCLK,
ARIZONA_CLK_SRC_FLL2,
bells->asyncclk_rate,
SND_SOC_CLOCK_IN);
if (ret != 0) {
dev_err(component->dev, "Failed to set ASYNCCLK: %d\n", ret);
return ret;
}
rtd = snd_soc_get_pcm_runtime(card, &card->dai_link[DAI_CODEC_CP]);
aif2_dai = asoc_rtd_to_cpu(rtd, 0);
ret = snd_soc_dai_set_sysclk(aif2_dai, ARIZONA_CLK_ASYNCCLK, 0, 0);
if (ret != 0) {
dev_err(aif2_dai->dev, "Failed to set AIF2 clock: %d\n", ret);
return ret;
}
if (card->num_rtd == DAI_CODEC_SUB)
return 0;
rtd = snd_soc_get_pcm_runtime(card, &card->dai_link[DAI_CODEC_SUB]);
aif3_dai = asoc_rtd_to_cpu(rtd, 0);
wm9081_dai = asoc_rtd_to_codec(rtd, 0);
ret = snd_soc_dai_set_sysclk(aif3_dai, ARIZONA_CLK_SYSCLK, 0, 0);
if (ret != 0) {
dev_err(aif1_dai->dev, "Failed to set AIF1 clock: %d\n", ret);
return ret;
}
ret = snd_soc_component_set_sysclk(wm9081_dai->component, WM9081_SYSCLK_MCLK,
0, SYS_MCLK_RATE, 0);
if (ret != 0) {
dev_err(wm9081_dai->dev, "Failed to set MCLK: %d\n", ret);
return ret;
}
return 0;
}
static const struct snd_soc_pcm_stream baseband_params = {
.formats = SNDRV_PCM_FMTBIT_S32_LE,
.rate_min = 8000,
.rate_max = 8000,
.channels_min = 2,
.channels_max = 2,
};
static const struct snd_soc_pcm_stream sub_params = {
.formats = SNDRV_PCM_FMTBIT_S32_LE,
.rate_min = SYS_AUDIO_RATE,
.rate_max = SYS_AUDIO_RATE,
.channels_min = 2,
.channels_max = 2,
};
SND_SOC_DAILINK_DEFS(wm2200_cpu_dsp,
DAILINK_COMP_ARRAY(COMP_CPU("samsung-i2s.0")),
DAILINK_COMP_ARRAY(COMP_CODEC("spi0.0", "wm0010-sdi1")),
DAILINK_COMP_ARRAY(COMP_PLATFORM("samsung-i2s.0")));
SND_SOC_DAILINK_DEFS(wm2200_dsp_codec,
DAILINK_COMP_ARRAY(COMP_CPU("wm0010-sdi2")),
DAILINK_COMP_ARRAY(COMP_CODEC("wm2200.1-003a", "wm2200")));
static struct snd_soc_dai_link bells_dai_wm2200[] = {
{
.name = "CPU-DSP",
.stream_name = "CPU-DSP",
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF
| SND_SOC_DAIFMT_CBM_CFM,
SND_SOC_DAILINK_REG(wm2200_cpu_dsp),
},
{
.name = "DSP-CODEC",
.stream_name = "DSP-CODEC",
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF
| SND_SOC_DAIFMT_CBM_CFM,
.c2c_params = &sub_params,
.num_c2c_params = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(wm2200_dsp_codec),
},
};
SND_SOC_DAILINK_DEFS(wm5102_cpu_dsp,
DAILINK_COMP_ARRAY(COMP_CPU("samsung-i2s.0")),
DAILINK_COMP_ARRAY(COMP_CODEC("spi0.0", "wm0010-sdi1")),
DAILINK_COMP_ARRAY(COMP_PLATFORM("samsung-i2s.0")));
SND_SOC_DAILINK_DEFS(wm5102_dsp_codec,
DAILINK_COMP_ARRAY(COMP_CPU("wm0010-sdi2")),
DAILINK_COMP_ARRAY(COMP_CODEC("wm5102-codec", "wm5102-aif1")));
SND_SOC_DAILINK_DEFS(wm5102_baseband,
DAILINK_COMP_ARRAY(COMP_CPU("wm5102-aif2")),
DAILINK_COMP_ARRAY(COMP_CODEC("wm1250-ev1.1-0027", "wm1250-ev1")));
SND_SOC_DAILINK_DEFS(wm5102_sub,
DAILINK_COMP_ARRAY(COMP_CPU("wm5102-aif3")),
DAILINK_COMP_ARRAY(COMP_CODEC("wm9081.1-006c", "wm9081-hifi")));
static struct snd_soc_dai_link bells_dai_wm5102[] = {
{
.name = "CPU-DSP",
.stream_name = "CPU-DSP",
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF
| SND_SOC_DAIFMT_CBM_CFM,
SND_SOC_DAILINK_REG(wm5102_cpu_dsp),
},
{
.name = "DSP-CODEC",
.stream_name = "DSP-CODEC",
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF
| SND_SOC_DAIFMT_CBM_CFM,
.c2c_params = &sub_params,
.num_c2c_params = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(wm5102_dsp_codec),
},
{
.name = "Baseband",
.stream_name = "Baseband",
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF
| SND_SOC_DAIFMT_CBM_CFM,
.ignore_suspend = 1,
.c2c_params = &baseband_params,
.num_c2c_params = 1,
SND_SOC_DAILINK_REG(wm5102_baseband),
},
{
.name = "Sub",
.stream_name = "Sub",
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF
| SND_SOC_DAIFMT_CBS_CFS,
.ignore_suspend = 1,
.c2c_params = &sub_params,
.num_c2c_params = 1,
SND_SOC_DAILINK_REG(wm5102_sub),
},
};
SND_SOC_DAILINK_DEFS(wm5110_cpu_dsp,
DAILINK_COMP_ARRAY(COMP_CPU("samsung-i2s.0")),
DAILINK_COMP_ARRAY(COMP_CODEC("spi0.0", "wm0010-sdi1")),
DAILINK_COMP_ARRAY(COMP_PLATFORM("samsung-i2s.0")));
SND_SOC_DAILINK_DEFS(wm5110_dsp_codec,
DAILINK_COMP_ARRAY(COMP_CPU("wm0010-sdi2")),
DAILINK_COMP_ARRAY(COMP_CODEC("wm5110-codec", "wm5110-aif1")));
SND_SOC_DAILINK_DEFS(wm5110_baseband,
DAILINK_COMP_ARRAY(COMP_CPU("wm5110-aif2")),
DAILINK_COMP_ARRAY(COMP_CODEC("wm1250-ev1.1-0027", "wm1250-ev1")));
SND_SOC_DAILINK_DEFS(wm5110_sub,
DAILINK_COMP_ARRAY(COMP_CPU("wm5110-aif3")),
DAILINK_COMP_ARRAY(COMP_CODEC("wm9081.1-006c", "wm9081-hifi")));
static struct snd_soc_dai_link bells_dai_wm5110[] = {
{
.name = "CPU-DSP",
.stream_name = "CPU-DSP",
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF
| SND_SOC_DAIFMT_CBM_CFM,
SND_SOC_DAILINK_REG(wm5110_cpu_dsp),
},
{
.name = "DSP-CODEC",
.stream_name = "DSP-CODEC",
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF
| SND_SOC_DAIFMT_CBM_CFM,
.c2c_params = &sub_params,
.num_c2c_params = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(wm5110_dsp_codec),
},
{
.name = "Baseband",
.stream_name = "Baseband",
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF
| SND_SOC_DAIFMT_CBM_CFM,
.ignore_suspend = 1,
.c2c_params = &baseband_params,
.num_c2c_params = 1,
SND_SOC_DAILINK_REG(wm5110_baseband),
},
{
.name = "Sub",
.stream_name = "Sub",
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF
| SND_SOC_DAIFMT_CBS_CFS,
.ignore_suspend = 1,
.c2c_params = &sub_params,
.num_c2c_params = 1,
SND_SOC_DAILINK_REG(wm5110_sub),
},
};
static struct snd_soc_codec_conf bells_codec_conf[] = {
{
.dlc = COMP_CODEC_CONF("wm9081.1-006c"),
.name_prefix = "Sub",
},
};
static const struct snd_soc_dapm_widget bells_widgets[] = {
SND_SOC_DAPM_MIC("DMIC", NULL),
};
static const struct snd_soc_dapm_route bells_routes[] = {
{ "Sub CLK_SYS", NULL, "OPCLK" },
{ "CLKIN", NULL, "OPCLK" },
{ "DMIC", NULL, "MICBIAS2" },
{ "IN2L", NULL, "DMIC" },
{ "IN2R", NULL, "DMIC" },
};
static struct snd_soc_card bells_cards[] = {
{
.name = "Bells WM2200",
.owner = THIS_MODULE,
.dai_link = bells_dai_wm2200,
.num_links = ARRAY_SIZE(bells_dai_wm2200),
.codec_conf = bells_codec_conf,
.num_configs = ARRAY_SIZE(bells_codec_conf),
.late_probe = bells_late_probe,
.dapm_widgets = bells_widgets,
.num_dapm_widgets = ARRAY_SIZE(bells_widgets),
.dapm_routes = bells_routes,
.num_dapm_routes = ARRAY_SIZE(bells_routes),
.set_bias_level = bells_set_bias_level,
.set_bias_level_post = bells_set_bias_level_post,
.drvdata = &wm2200_drvdata,
},
{
.name = "Bells WM5102",
.owner = THIS_MODULE,
.dai_link = bells_dai_wm5102,
.num_links = ARRAY_SIZE(bells_dai_wm5102),
.codec_conf = bells_codec_conf,
.num_configs = ARRAY_SIZE(bells_codec_conf),
.late_probe = bells_late_probe,
.dapm_widgets = bells_widgets,
.num_dapm_widgets = ARRAY_SIZE(bells_widgets),
.dapm_routes = bells_routes,
.num_dapm_routes = ARRAY_SIZE(bells_routes),
.set_bias_level = bells_set_bias_level,
.set_bias_level_post = bells_set_bias_level_post,
.drvdata = &wm5102_drvdata,
},
{
.name = "Bells WM5110",
.owner = THIS_MODULE,
.dai_link = bells_dai_wm5110,
.num_links = ARRAY_SIZE(bells_dai_wm5110),
.codec_conf = bells_codec_conf,
.num_configs = ARRAY_SIZE(bells_codec_conf),
.late_probe = bells_late_probe,
.dapm_widgets = bells_widgets,
.num_dapm_widgets = ARRAY_SIZE(bells_widgets),
.dapm_routes = bells_routes,
.num_dapm_routes = ARRAY_SIZE(bells_routes),
.set_bias_level = bells_set_bias_level,
.set_bias_level_post = bells_set_bias_level_post,
.drvdata = &wm5110_drvdata,
},
};
static int bells_probe(struct platform_device *pdev)
{
int ret;
bells_cards[pdev->id].dev = &pdev->dev;
ret = devm_snd_soc_register_card(&pdev->dev, &bells_cards[pdev->id]);
if (ret)
dev_err(&pdev->dev,
"snd_soc_register_card(%s) failed: %d\n",
bells_cards[pdev->id].name, ret);
return ret;
}
static struct platform_driver bells_driver = {
.driver = {
.name = "bells",
.pm = &snd_soc_pm_ops,
},
.probe = bells_probe,
};
module_platform_driver(bells_driver);
MODULE_DESCRIPTION("Bells audio support");
MODULE_AUTHOR("Mark Brown <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:bells");
| linux-master | sound/soc/samsung/bells.c |
// SPDX-License-Identifier: GPL-2.0+
//
// Speyside audio support
//
// Copyright 2011 Wolfson Microelectronics
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/jack.h>
#include <linux/gpio.h>
#include <linux/module.h>
#include "../codecs/wm8996.h"
#include "../codecs/wm9081.h"
#define WM8996_HPSEL_GPIO 214
#define MCLK_AUDIO_RATE (512 * 48000)
static int speyside_set_bias_level(struct snd_soc_card *card,
struct snd_soc_dapm_context *dapm,
enum snd_soc_bias_level level)
{
struct snd_soc_pcm_runtime *rtd;
struct snd_soc_dai *codec_dai;
int ret;
rtd = snd_soc_get_pcm_runtime(card, &card->dai_link[1]);
codec_dai = asoc_rtd_to_codec(rtd, 0);
if (dapm->dev != codec_dai->dev)
return 0;
switch (level) {
case SND_SOC_BIAS_STANDBY:
ret = snd_soc_dai_set_sysclk(codec_dai, WM8996_SYSCLK_MCLK2,
32768, SND_SOC_CLOCK_IN);
if (ret < 0)
return ret;
ret = snd_soc_dai_set_pll(codec_dai, WM8996_FLL_MCLK2,
0, 0, 0);
if (ret < 0) {
pr_err("Failed to stop FLL\n");
return ret;
}
break;
default:
break;
}
return 0;
}
static int speyside_set_bias_level_post(struct snd_soc_card *card,
struct snd_soc_dapm_context *dapm,
enum snd_soc_bias_level level)
{
struct snd_soc_pcm_runtime *rtd;
struct snd_soc_dai *codec_dai;
int ret;
rtd = snd_soc_get_pcm_runtime(card, &card->dai_link[1]);
codec_dai = asoc_rtd_to_codec(rtd, 0);
if (dapm->dev != codec_dai->dev)
return 0;
switch (level) {
case SND_SOC_BIAS_PREPARE:
if (card->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
ret = snd_soc_dai_set_pll(codec_dai, 0,
WM8996_FLL_MCLK2,
32768, MCLK_AUDIO_RATE);
if (ret < 0) {
pr_err("Failed to start FLL\n");
return ret;
}
ret = snd_soc_dai_set_sysclk(codec_dai,
WM8996_SYSCLK_FLL,
MCLK_AUDIO_RATE,
SND_SOC_CLOCK_IN);
if (ret < 0)
return ret;
}
break;
default:
break;
}
card->dapm.bias_level = level;
return 0;
}
static struct snd_soc_jack speyside_headset;
/* Headset jack detection DAPM pins */
static struct snd_soc_jack_pin speyside_headset_pins[] = {
{
.pin = "Headset Mic",
.mask = SND_JACK_MICROPHONE,
},
};
/* Default the headphone selection to active high */
static int speyside_jack_polarity;
static int speyside_get_micbias(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
if (speyside_jack_polarity && (strcmp(source->name, "MICB1") == 0))
return 1;
if (!speyside_jack_polarity && (strcmp(source->name, "MICB2") == 0))
return 1;
return 0;
}
static void speyside_set_polarity(struct snd_soc_component *component,
int polarity)
{
speyside_jack_polarity = !polarity;
gpio_direction_output(WM8996_HPSEL_GPIO, speyside_jack_polarity);
/* Re-run DAPM to make sure we're using the correct mic bias */
snd_soc_dapm_sync(snd_soc_component_get_dapm(component));
}
static int speyside_wm0010_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_dai *dai = asoc_rtd_to_codec(rtd, 0);
int ret;
ret = snd_soc_dai_set_sysclk(dai, 0, MCLK_AUDIO_RATE, 0);
if (ret < 0)
return ret;
return 0;
}
static int speyside_wm8996_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_dai *dai = asoc_rtd_to_codec(rtd, 0);
struct snd_soc_component *component = dai->component;
int ret;
ret = snd_soc_dai_set_sysclk(dai, WM8996_SYSCLK_MCLK2, 32768, 0);
if (ret < 0)
return ret;
ret = gpio_request(WM8996_HPSEL_GPIO, "HP_SEL");
if (ret != 0)
pr_err("Failed to request HP_SEL GPIO: %d\n", ret);
gpio_direction_output(WM8996_HPSEL_GPIO, speyside_jack_polarity);
ret = snd_soc_card_jack_new_pins(rtd->card, "Headset",
SND_JACK_LINEOUT | SND_JACK_HEADSET |
SND_JACK_BTN_0,
&speyside_headset,
speyside_headset_pins,
ARRAY_SIZE(speyside_headset_pins));
if (ret)
return ret;
wm8996_detect(component, &speyside_headset, speyside_set_polarity);
return 0;
}
static int speyside_late_probe(struct snd_soc_card *card)
{
snd_soc_dapm_ignore_suspend(&card->dapm, "Headphone");
snd_soc_dapm_ignore_suspend(&card->dapm, "Headset Mic");
snd_soc_dapm_ignore_suspend(&card->dapm, "Main AMIC");
snd_soc_dapm_ignore_suspend(&card->dapm, "Main DMIC");
snd_soc_dapm_ignore_suspend(&card->dapm, "Main Speaker");
snd_soc_dapm_ignore_suspend(&card->dapm, "WM1250 Output");
snd_soc_dapm_ignore_suspend(&card->dapm, "WM1250 Input");
return 0;
}
static const struct snd_soc_pcm_stream dsp_codec_params = {
.formats = SNDRV_PCM_FMTBIT_S32_LE,
.rate_min = 48000,
.rate_max = 48000,
.channels_min = 2,
.channels_max = 2,
};
SND_SOC_DAILINK_DEFS(cpu_dsp,
DAILINK_COMP_ARRAY(COMP_CPU("samsung-i2s.0")),
DAILINK_COMP_ARRAY(COMP_CODEC("spi0.0", "wm0010-sdi1")),
DAILINK_COMP_ARRAY(COMP_PLATFORM("samsung-i2s.0")));
SND_SOC_DAILINK_DEFS(dsp_codec,
DAILINK_COMP_ARRAY(COMP_CPU("wm0010-sdi2")),
DAILINK_COMP_ARRAY(COMP_CODEC("wm8996.1-001a", "wm8996-aif1")));
SND_SOC_DAILINK_DEFS(baseband,
DAILINK_COMP_ARRAY(COMP_CPU("wm8996-aif2")),
DAILINK_COMP_ARRAY(COMP_CODEC("wm1250-ev1.1-0027", "wm1250-ev1")));
static struct snd_soc_dai_link speyside_dai[] = {
{
.name = "CPU-DSP",
.stream_name = "CPU-DSP",
.init = speyside_wm0010_init,
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF
| SND_SOC_DAIFMT_CBM_CFM,
SND_SOC_DAILINK_REG(cpu_dsp),
},
{
.name = "DSP-CODEC",
.stream_name = "DSP-CODEC",
.init = speyside_wm8996_init,
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF
| SND_SOC_DAIFMT_CBM_CFM,
.c2c_params = &dsp_codec_params,
.num_c2c_params = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(dsp_codec),
},
{
.name = "Baseband",
.stream_name = "Baseband",
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF
| SND_SOC_DAIFMT_CBM_CFM,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(baseband),
},
};
static int speyside_wm9081_init(struct snd_soc_component *component)
{
/* At any time the WM9081 is active it will have this clock */
return snd_soc_component_set_sysclk(component, WM9081_SYSCLK_MCLK, 0,
MCLK_AUDIO_RATE, 0);
}
static struct snd_soc_aux_dev speyside_aux_dev[] = {
{
.dlc = COMP_AUX("wm9081.1-006c"),
.init = speyside_wm9081_init,
},
};
static struct snd_soc_codec_conf speyside_codec_conf[] = {
{
.dlc = COMP_CODEC_CONF("wm9081.1-006c"),
.name_prefix = "Sub",
},
};
static const struct snd_kcontrol_new controls[] = {
SOC_DAPM_PIN_SWITCH("Main Speaker"),
SOC_DAPM_PIN_SWITCH("Main DMIC"),
SOC_DAPM_PIN_SWITCH("Main AMIC"),
SOC_DAPM_PIN_SWITCH("WM1250 Input"),
SOC_DAPM_PIN_SWITCH("WM1250 Output"),
SOC_DAPM_PIN_SWITCH("Headphone"),
};
static const struct snd_soc_dapm_widget widgets[] = {
SND_SOC_DAPM_HP("Headphone", NULL),
SND_SOC_DAPM_MIC("Headset Mic", NULL),
SND_SOC_DAPM_SPK("Main Speaker", NULL),
SND_SOC_DAPM_MIC("Main AMIC", NULL),
SND_SOC_DAPM_MIC("Main DMIC", NULL),
};
static const struct snd_soc_dapm_route audio_paths[] = {
{ "IN1RN", NULL, "MICB1" },
{ "IN1RP", NULL, "MICB1" },
{ "IN1RN", NULL, "MICB2" },
{ "IN1RP", NULL, "MICB2" },
{ "MICB1", NULL, "Headset Mic", speyside_get_micbias },
{ "MICB2", NULL, "Headset Mic", speyside_get_micbias },
{ "IN1LP", NULL, "MICB2" },
{ "IN1RN", NULL, "MICB1" },
{ "MICB2", NULL, "Main AMIC" },
{ "DMIC1DAT", NULL, "MICB1" },
{ "DMIC2DAT", NULL, "MICB1" },
{ "MICB1", NULL, "Main DMIC" },
{ "Headphone", NULL, "HPOUT1L" },
{ "Headphone", NULL, "HPOUT1R" },
{ "Sub IN1", NULL, "HPOUT2L" },
{ "Sub IN2", NULL, "HPOUT2R" },
{ "Main Speaker", NULL, "Sub SPKN" },
{ "Main Speaker", NULL, "Sub SPKP" },
{ "Main Speaker", NULL, "SPKDAT" },
};
static struct snd_soc_card speyside = {
.name = "Speyside",
.owner = THIS_MODULE,
.dai_link = speyside_dai,
.num_links = ARRAY_SIZE(speyside_dai),
.aux_dev = speyside_aux_dev,
.num_aux_devs = ARRAY_SIZE(speyside_aux_dev),
.codec_conf = speyside_codec_conf,
.num_configs = ARRAY_SIZE(speyside_codec_conf),
.set_bias_level = speyside_set_bias_level,
.set_bias_level_post = speyside_set_bias_level_post,
.controls = controls,
.num_controls = ARRAY_SIZE(controls),
.dapm_widgets = widgets,
.num_dapm_widgets = ARRAY_SIZE(widgets),
.dapm_routes = audio_paths,
.num_dapm_routes = ARRAY_SIZE(audio_paths),
.fully_routed = true,
.late_probe = speyside_late_probe,
};
static int speyside_probe(struct platform_device *pdev)
{
struct snd_soc_card *card = &speyside;
int ret;
card->dev = &pdev->dev;
ret = devm_snd_soc_register_card(&pdev->dev, card);
if (ret)
dev_err_probe(&pdev->dev, ret, "snd_soc_register_card() failed\n");
return ret;
}
static struct platform_driver speyside_driver = {
.driver = {
.name = "speyside",
.pm = &snd_soc_pm_ops,
},
.probe = speyside_probe,
};
module_platform_driver(speyside_driver);
MODULE_DESCRIPTION("Speyside audio support");
MODULE_AUTHOR("Mark Brown <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:speyside");
| linux-master | sound/soc/samsung/speyside.c |
// SPDX-License-Identifier: GPL-2.0+
//
// smdk_spdif.c - S/PDIF audio for SMDK
//
// Copyright (C) 2010 Samsung Electronics Co., Ltd.
#include <linux/clk.h>
#include <linux/module.h>
#include <sound/soc.h>
#include "spdif.h"
/* Audio clock settings are belonged to board specific part. Every
* board can set audio source clock setting which is matched with H/W
* like this function-'set_audio_clock_heirachy'.
*/
static int set_audio_clock_heirachy(struct platform_device *pdev)
{
struct clk *fout_epll, *mout_epll, *sclk_audio0, *sclk_spdif;
int ret = 0;
fout_epll = clk_get(NULL, "fout_epll");
if (IS_ERR(fout_epll)) {
printk(KERN_WARNING "%s: Cannot find fout_epll.\n",
__func__);
return -EINVAL;
}
mout_epll = clk_get(NULL, "mout_epll");
if (IS_ERR(mout_epll)) {
printk(KERN_WARNING "%s: Cannot find mout_epll.\n",
__func__);
ret = -EINVAL;
goto out1;
}
sclk_audio0 = clk_get(&pdev->dev, "sclk_audio");
if (IS_ERR(sclk_audio0)) {
printk(KERN_WARNING "%s: Cannot find sclk_audio.\n",
__func__);
ret = -EINVAL;
goto out2;
}
sclk_spdif = clk_get(NULL, "sclk_spdif");
if (IS_ERR(sclk_spdif)) {
printk(KERN_WARNING "%s: Cannot find sclk_spdif.\n",
__func__);
ret = -EINVAL;
goto out3;
}
/* Set audio clock hierarchy for S/PDIF */
clk_set_parent(mout_epll, fout_epll);
clk_set_parent(sclk_audio0, mout_epll);
clk_set_parent(sclk_spdif, sclk_audio0);
clk_put(sclk_spdif);
out3:
clk_put(sclk_audio0);
out2:
clk_put(mout_epll);
out1:
clk_put(fout_epll);
return ret;
}
/* We should haved to set clock directly on this part because of clock
* scheme of Samsudng SoCs did not support to set rates from abstrct
* clock of it's hierarchy.
*/
static int set_audio_clock_rate(unsigned long epll_rate,
unsigned long audio_rate)
{
struct clk *fout_epll, *sclk_spdif;
fout_epll = clk_get(NULL, "fout_epll");
if (IS_ERR(fout_epll)) {
printk(KERN_ERR "%s: failed to get fout_epll\n", __func__);
return -ENOENT;
}
clk_set_rate(fout_epll, epll_rate);
clk_put(fout_epll);
sclk_spdif = clk_get(NULL, "sclk_spdif");
if (IS_ERR(sclk_spdif)) {
printk(KERN_ERR "%s: failed to get sclk_spdif\n", __func__);
return -ENOENT;
}
clk_set_rate(sclk_spdif, audio_rate);
clk_put(sclk_spdif);
return 0;
}
static int smdk_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
unsigned long pll_out, rclk_rate;
int ret, ratio;
switch (params_rate(params)) {
case 44100:
pll_out = 45158400;
break;
case 32000:
case 48000:
case 96000:
pll_out = 49152000;
break;
default:
return -EINVAL;
}
/* Setting ratio to 512fs helps to use S/PDIF with HDMI without
* modify S/PDIF ASoC machine driver.
*/
ratio = 512;
rclk_rate = params_rate(params) * ratio;
/* Set audio source clock rates */
ret = set_audio_clock_rate(pll_out, rclk_rate);
if (ret < 0)
return ret;
/* Set S/PDIF uses internal source clock */
ret = snd_soc_dai_set_sysclk(cpu_dai, SND_SOC_SPDIF_INT_MCLK,
rclk_rate, SND_SOC_CLOCK_IN);
if (ret < 0)
return ret;
return ret;
}
static const struct snd_soc_ops smdk_spdif_ops = {
.hw_params = smdk_hw_params,
};
SND_SOC_DAILINK_DEFS(spdif,
DAILINK_COMP_ARRAY(COMP_CPU("samsung-spdif")),
DAILINK_COMP_ARRAY(COMP_CODEC("spdif-dit", "dit-hifi")),
DAILINK_COMP_ARRAY(COMP_PLATFORM("samsung-spdif")));
static struct snd_soc_dai_link smdk_dai = {
.name = "S/PDIF",
.stream_name = "S/PDIF PCM Playback",
.ops = &smdk_spdif_ops,
SND_SOC_DAILINK_REG(spdif),
};
static struct snd_soc_card smdk = {
.name = "SMDK-S/PDIF",
.owner = THIS_MODULE,
.dai_link = &smdk_dai,
.num_links = 1,
};
static struct platform_device *smdk_snd_spdif_dit_device;
static struct platform_device *smdk_snd_spdif_device;
static int __init smdk_init(void)
{
int ret;
smdk_snd_spdif_dit_device = platform_device_alloc("spdif-dit", -1);
if (!smdk_snd_spdif_dit_device)
return -ENOMEM;
ret = platform_device_add(smdk_snd_spdif_dit_device);
if (ret)
goto err1;
smdk_snd_spdif_device = platform_device_alloc("soc-audio", -1);
if (!smdk_snd_spdif_device) {
ret = -ENOMEM;
goto err2;
}
platform_set_drvdata(smdk_snd_spdif_device, &smdk);
ret = platform_device_add(smdk_snd_spdif_device);
if (ret)
goto err3;
/* Set audio clock hierarchy manually */
ret = set_audio_clock_heirachy(smdk_snd_spdif_device);
if (ret)
goto err4;
return 0;
err4:
platform_device_del(smdk_snd_spdif_device);
err3:
platform_device_put(smdk_snd_spdif_device);
err2:
platform_device_del(smdk_snd_spdif_dit_device);
err1:
platform_device_put(smdk_snd_spdif_dit_device);
return ret;
}
static void __exit smdk_exit(void)
{
platform_device_unregister(smdk_snd_spdif_device);
platform_device_unregister(smdk_snd_spdif_dit_device);
}
module_init(smdk_init);
module_exit(smdk_exit);
MODULE_AUTHOR("Seungwhan Youn, <[email protected]>");
MODULE_DESCRIPTION("ALSA SoC SMDK+S/PDIF");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/samsung/smdk_spdif.c |
// SPDX-License-Identifier: GPL-2.0+
#include <linux/extcon.h>
#include <linux/iio/consumer.h>
#include <linux/input-event-codes.h>
#include <linux/mfd/wm8994/registers.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/regulator/consumer.h>
#include <sound/jack.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include "i2s.h"
#include "../codecs/wm8994.h"
#define ARIES_MCLK1_FREQ 24000000
struct aries_wm8994_variant {
unsigned int modem_dai_fmt;
bool has_fm_radio;
};
struct aries_wm8994_data {
struct extcon_dev *usb_extcon;
struct regulator *reg_main_micbias;
struct regulator *reg_headset_micbias;
struct gpio_desc *gpio_headset_detect;
struct gpio_desc *gpio_headset_key;
struct gpio_desc *gpio_earpath_sel;
struct iio_channel *adc;
const struct aries_wm8994_variant *variant;
};
/* USB dock */
static struct snd_soc_jack aries_dock;
static struct snd_soc_jack_pin dock_pins[] = {
{
.pin = "LINE",
.mask = SND_JACK_LINEOUT,
},
};
static int aries_extcon_notifier(struct notifier_block *this,
unsigned long connected, void *_cmd)
{
if (connected)
snd_soc_jack_report(&aries_dock, SND_JACK_LINEOUT,
SND_JACK_LINEOUT);
else
snd_soc_jack_report(&aries_dock, 0, SND_JACK_LINEOUT);
return NOTIFY_DONE;
}
static struct notifier_block aries_extcon_notifier_block = {
.notifier_call = aries_extcon_notifier,
};
/* Headset jack */
static struct snd_soc_jack aries_headset;
static struct snd_soc_jack_pin jack_pins[] = {
{
.pin = "HP",
.mask = SND_JACK_HEADPHONE,
}, {
.pin = "Headset Mic",
.mask = SND_JACK_MICROPHONE,
},
};
static struct snd_soc_jack_zone headset_zones[] = {
{
.min_mv = 0,
.max_mv = 241,
.jack_type = SND_JACK_HEADPHONE,
}, {
.min_mv = 242,
.max_mv = 2980,
.jack_type = SND_JACK_HEADSET,
}, {
.min_mv = 2981,
.max_mv = UINT_MAX,
.jack_type = SND_JACK_HEADPHONE,
},
};
static irqreturn_t headset_det_irq_thread(int irq, void *data)
{
struct aries_wm8994_data *priv = (struct aries_wm8994_data *) data;
int ret = 0;
int time_left_ms = 300;
int adc;
while (time_left_ms > 0) {
if (!gpiod_get_value(priv->gpio_headset_detect)) {
snd_soc_jack_report(&aries_headset, 0,
SND_JACK_HEADSET);
gpiod_set_value(priv->gpio_earpath_sel, 0);
return IRQ_HANDLED;
}
msleep(20);
time_left_ms -= 20;
}
/* Temporarily enable micbias and earpath selector */
ret = regulator_enable(priv->reg_headset_micbias);
if (ret)
pr_err("%s failed to enable micbias: %d", __func__, ret);
gpiod_set_value(priv->gpio_earpath_sel, 1);
ret = iio_read_channel_processed(priv->adc, &adc);
if (ret < 0) {
/* failed to read ADC, so assume headphone */
pr_err("%s failed to read ADC, assuming headphones", __func__);
snd_soc_jack_report(&aries_headset, SND_JACK_HEADPHONE,
SND_JACK_HEADSET);
} else {
snd_soc_jack_report(&aries_headset,
snd_soc_jack_get_type(&aries_headset, adc),
SND_JACK_HEADSET);
}
ret = regulator_disable(priv->reg_headset_micbias);
if (ret)
pr_err("%s failed disable micbias: %d", __func__, ret);
/* Disable earpath selector when no mic connected */
if (!(aries_headset.status & SND_JACK_MICROPHONE))
gpiod_set_value(priv->gpio_earpath_sel, 0);
return IRQ_HANDLED;
}
static int headset_button_check(void *data)
{
struct aries_wm8994_data *priv = (struct aries_wm8994_data *) data;
/* Filter out keypresses when 4 pole jack not detected */
if (gpiod_get_value_cansleep(priv->gpio_headset_key) &&
aries_headset.status & SND_JACK_MICROPHONE)
return SND_JACK_BTN_0;
return 0;
}
static struct snd_soc_jack_gpio headset_button_gpio[] = {
{
.name = "Media Button",
.report = SND_JACK_BTN_0,
.debounce_time = 30,
.jack_status_check = headset_button_check,
},
};
static int aries_spk_cfg(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_card *card = w->dapm->card;
struct snd_soc_pcm_runtime *rtd;
struct snd_soc_component *component;
int ret = 0;
rtd = snd_soc_get_pcm_runtime(card, &card->dai_link[0]);
component = asoc_rtd_to_codec(rtd, 0)->component;
/**
* We have an odd setup - the SPKMODE pin is pulled up so
* we only have access to the left side SPK configs,
* but SPKOUTR isn't bridged so when playing back in
* stereo, we only get the left hand channel. The only
* option we're left with is to force the AIF into mono
* mode.
*/
switch (event) {
case SND_SOC_DAPM_POST_PMU:
ret = snd_soc_component_update_bits(component,
WM8994_AIF1_DAC1_FILTERS_1,
WM8994_AIF1DAC1_MONO, WM8994_AIF1DAC1_MONO);
break;
case SND_SOC_DAPM_PRE_PMD:
ret = snd_soc_component_update_bits(component,
WM8994_AIF1_DAC1_FILTERS_1,
WM8994_AIF1DAC1_MONO, 0);
break;
}
return ret;
}
static int aries_main_bias(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_card *card = w->dapm->card;
struct aries_wm8994_data *priv = snd_soc_card_get_drvdata(card);
int ret = 0;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
ret = regulator_enable(priv->reg_main_micbias);
break;
case SND_SOC_DAPM_POST_PMD:
ret = regulator_disable(priv->reg_main_micbias);
break;
}
return ret;
}
static int aries_headset_bias(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_card *card = w->dapm->card;
struct aries_wm8994_data *priv = snd_soc_card_get_drvdata(card);
int ret = 0;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
ret = regulator_enable(priv->reg_headset_micbias);
break;
case SND_SOC_DAPM_POST_PMD:
ret = regulator_disable(priv->reg_headset_micbias);
break;
}
return ret;
}
static const struct snd_kcontrol_new aries_controls[] = {
SOC_DAPM_PIN_SWITCH("Modem In"),
SOC_DAPM_PIN_SWITCH("Modem Out"),
};
static const struct snd_soc_dapm_widget aries_dapm_widgets[] = {
SND_SOC_DAPM_HP("HP", NULL),
SND_SOC_DAPM_SPK("SPK", aries_spk_cfg),
SND_SOC_DAPM_SPK("RCV", NULL),
SND_SOC_DAPM_LINE("LINE", NULL),
SND_SOC_DAPM_MIC("Main Mic", aries_main_bias),
SND_SOC_DAPM_MIC("Headset Mic", aries_headset_bias),
SND_SOC_DAPM_MIC("Bluetooth Mic", NULL),
SND_SOC_DAPM_SPK("Bluetooth SPK", NULL),
SND_SOC_DAPM_LINE("Modem In", NULL),
SND_SOC_DAPM_LINE("Modem Out", NULL),
/* This must be last as it is conditionally not used */
SND_SOC_DAPM_LINE("FM In", NULL),
};
static int aries_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
unsigned int pll_out;
int ret;
/* AIF1CLK should be >=3MHz for optimal performance */
if (params_width(params) == 24)
pll_out = params_rate(params) * 384;
else if (params_rate(params) == 8000 || params_rate(params) == 11025)
pll_out = params_rate(params) * 512;
else
pll_out = params_rate(params) * 256;
ret = snd_soc_dai_set_pll(codec_dai, WM8994_FLL1, WM8994_FLL_SRC_MCLK1,
ARIES_MCLK1_FREQ, pll_out);
if (ret < 0)
return ret;
ret = snd_soc_dai_set_sysclk(codec_dai, WM8994_SYSCLK_FLL1,
pll_out, SND_SOC_CLOCK_IN);
if (ret < 0)
return ret;
return 0;
}
static int aries_hw_free(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
int ret;
/* Switch sysclk to MCLK1 */
ret = snd_soc_dai_set_sysclk(codec_dai, WM8994_SYSCLK_MCLK1,
ARIES_MCLK1_FREQ, SND_SOC_CLOCK_IN);
if (ret < 0)
return ret;
/* Stop PLL */
ret = snd_soc_dai_set_pll(codec_dai, WM8994_FLL1, WM8994_FLL_SRC_MCLK1,
ARIES_MCLK1_FREQ, 0);
if (ret < 0)
return ret;
return 0;
}
/*
* Main DAI operations
*/
static const struct snd_soc_ops aries_ops = {
.hw_params = aries_hw_params,
.hw_free = aries_hw_free,
};
static int aries_baseband_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
unsigned int pll_out;
int ret;
pll_out = 8000 * 512;
/* Set the codec FLL */
ret = snd_soc_dai_set_pll(codec_dai, WM8994_FLL2, WM8994_FLL_SRC_MCLK1,
ARIES_MCLK1_FREQ, pll_out);
if (ret < 0)
return ret;
/* Set the codec system clock */
ret = snd_soc_dai_set_sysclk(codec_dai, WM8994_SYSCLK_FLL2,
pll_out, SND_SOC_CLOCK_IN);
if (ret < 0)
return ret;
return 0;
}
static int aries_late_probe(struct snd_soc_card *card)
{
struct aries_wm8994_data *priv = snd_soc_card_get_drvdata(card);
int ret, irq;
ret = snd_soc_card_jack_new_pins(card, "Dock", SND_JACK_LINEOUT,
&aries_dock, dock_pins, ARRAY_SIZE(dock_pins));
if (ret)
return ret;
ret = devm_extcon_register_notifier(card->dev,
priv->usb_extcon, EXTCON_JACK_LINE_OUT,
&aries_extcon_notifier_block);
if (ret)
return ret;
if (extcon_get_state(priv->usb_extcon,
EXTCON_JACK_LINE_OUT) > 0)
snd_soc_jack_report(&aries_dock, SND_JACK_LINEOUT,
SND_JACK_LINEOUT);
else
snd_soc_jack_report(&aries_dock, 0, SND_JACK_LINEOUT);
ret = snd_soc_card_jack_new_pins(card, "Headset",
SND_JACK_HEADSET | SND_JACK_BTN_0,
&aries_headset,
jack_pins, ARRAY_SIZE(jack_pins));
if (ret)
return ret;
ret = snd_soc_jack_add_zones(&aries_headset, ARRAY_SIZE(headset_zones),
headset_zones);
if (ret)
return ret;
irq = gpiod_to_irq(priv->gpio_headset_detect);
if (irq < 0) {
dev_err(card->dev, "Failed to map headset detect gpio to irq");
return -EINVAL;
}
ret = devm_request_threaded_irq(card->dev, irq, NULL,
headset_det_irq_thread,
IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
IRQF_ONESHOT, "headset_detect", priv);
if (ret) {
dev_err(card->dev, "Failed to request headset detect irq");
return ret;
}
headset_button_gpio[0].data = priv;
headset_button_gpio[0].desc = priv->gpio_headset_key;
snd_jack_set_key(aries_headset.jack, SND_JACK_BTN_0, KEY_MEDIA);
return snd_soc_jack_add_gpios(&aries_headset,
ARRAY_SIZE(headset_button_gpio), headset_button_gpio);
}
static const struct snd_soc_pcm_stream baseband_params = {
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.rate_min = 8000,
.rate_max = 8000,
.channels_min = 1,
.channels_max = 1,
};
static const struct snd_soc_pcm_stream bluetooth_params = {
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.rate_min = 8000,
.rate_max = 8000,
.channels_min = 1,
.channels_max = 2,
};
static const struct snd_soc_dapm_widget aries_modem_widgets[] = {
SND_SOC_DAPM_INPUT("Modem RX"),
SND_SOC_DAPM_OUTPUT("Modem TX"),
};
static const struct snd_soc_dapm_route aries_modem_routes[] = {
{ "Modem Capture", NULL, "Modem RX" },
{ "Modem TX", NULL, "Modem Playback" },
};
static const struct snd_soc_component_driver aries_component = {
.name = "aries-audio",
.dapm_widgets = aries_modem_widgets,
.num_dapm_widgets = ARRAY_SIZE(aries_modem_widgets),
.dapm_routes = aries_modem_routes,
.num_dapm_routes = ARRAY_SIZE(aries_modem_routes),
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static struct snd_soc_dai_driver aries_ext_dai[] = {
{
.name = "Voice call",
.playback = {
.stream_name = "Modem Playback",
.channels_min = 1,
.channels_max = 1,
.rate_min = 8000,
.rate_max = 8000,
.rates = SNDRV_PCM_RATE_8000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.capture = {
.stream_name = "Modem Capture",
.channels_min = 1,
.channels_max = 1,
.rate_min = 8000,
.rate_max = 8000,
.rates = SNDRV_PCM_RATE_8000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
},
};
SND_SOC_DAILINK_DEFS(aif1,
DAILINK_COMP_ARRAY(COMP_CPU(SAMSUNG_I2S_DAI)),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "wm8994-aif1")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(baseband,
DAILINK_COMP_ARRAY(COMP_CPU("Voice call")),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "wm8994-aif2")));
SND_SOC_DAILINK_DEFS(bluetooth,
DAILINK_COMP_ARRAY(COMP_CPU("bt-sco-pcm")),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "wm8994-aif3")));
static struct snd_soc_dai_link aries_dai[] = {
{
.name = "WM8994 AIF1",
.stream_name = "HiFi",
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBM_CFM,
.ops = &aries_ops,
SND_SOC_DAILINK_REG(aif1),
},
{
.name = "WM8994 AIF2",
.stream_name = "Baseband",
.init = &aries_baseband_init,
.c2c_params = &baseband_params,
.num_c2c_params = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(baseband),
},
{
.name = "WM8994 AIF3",
.stream_name = "Bluetooth",
.c2c_params = &bluetooth_params,
.num_c2c_params = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(bluetooth),
},
};
static struct snd_soc_card aries_card = {
.name = "ARIES",
.owner = THIS_MODULE,
.dai_link = aries_dai,
.num_links = ARRAY_SIZE(aries_dai),
.controls = aries_controls,
.num_controls = ARRAY_SIZE(aries_controls),
.dapm_widgets = aries_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(aries_dapm_widgets),
.late_probe = aries_late_probe,
};
static const struct aries_wm8994_variant fascinate4g_variant = {
.modem_dai_fmt = SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBS_CFS
| SND_SOC_DAIFMT_IB_NF,
.has_fm_radio = false,
};
static const struct aries_wm8994_variant aries_variant = {
.modem_dai_fmt = SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBM_CFM
| SND_SOC_DAIFMT_IB_NF,
.has_fm_radio = true,
};
static const struct of_device_id samsung_wm8994_of_match[] = {
{
.compatible = "samsung,fascinate4g-wm8994",
.data = &fascinate4g_variant,
},
{
.compatible = "samsung,aries-wm8994",
.data = &aries_variant,
},
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, samsung_wm8994_of_match);
static int aries_audio_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct device_node *cpu, *codec, *extcon_np;
struct device *dev = &pdev->dev;
struct snd_soc_card *card = &aries_card;
struct aries_wm8994_data *priv;
struct snd_soc_dai_link *dai_link;
const struct of_device_id *match;
enum iio_chan_type channel_type;
int ret, i;
if (!np)
return -EINVAL;
card->dev = dev;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
snd_soc_card_set_drvdata(card, priv);
match = of_match_node(samsung_wm8994_of_match, np);
priv->variant = match->data;
/* Remove FM widget if not present */
if (!priv->variant->has_fm_radio)
card->num_dapm_widgets--;
priv->reg_main_micbias = devm_regulator_get(dev, "main-micbias");
if (IS_ERR(priv->reg_main_micbias)) {
dev_err(dev, "Failed to get main micbias regulator\n");
return PTR_ERR(priv->reg_main_micbias);
}
priv->reg_headset_micbias = devm_regulator_get(dev, "headset-micbias");
if (IS_ERR(priv->reg_headset_micbias)) {
dev_err(dev, "Failed to get headset micbias regulator\n");
return PTR_ERR(priv->reg_headset_micbias);
}
priv->gpio_earpath_sel = devm_gpiod_get(dev, "earpath-sel",
GPIOD_OUT_LOW);
if (IS_ERR(priv->gpio_earpath_sel)) {
dev_err(dev, "Failed to get earpath selector gpio");
return PTR_ERR(priv->gpio_earpath_sel);
}
extcon_np = of_parse_phandle(np, "extcon", 0);
priv->usb_extcon = extcon_find_edev_by_node(extcon_np);
of_node_put(extcon_np);
if (IS_ERR(priv->usb_extcon))
return dev_err_probe(dev, PTR_ERR(priv->usb_extcon),
"Failed to get extcon device");
priv->adc = devm_iio_channel_get(dev, "headset-detect");
if (IS_ERR(priv->adc))
return dev_err_probe(dev, PTR_ERR(priv->adc),
"Failed to get ADC channel");
ret = iio_get_channel_type(priv->adc, &channel_type);
if (ret)
return dev_err_probe(dev, ret,
"Failed to get ADC channel type");
if (channel_type != IIO_VOLTAGE)
return -EINVAL;
priv->gpio_headset_key = devm_gpiod_get(dev, "headset-key",
GPIOD_IN);
if (IS_ERR(priv->gpio_headset_key)) {
dev_err(dev, "Failed to get headset key gpio");
return PTR_ERR(priv->gpio_headset_key);
}
priv->gpio_headset_detect = devm_gpiod_get(dev,
"headset-detect", GPIOD_IN);
if (IS_ERR(priv->gpio_headset_detect)) {
dev_err(dev, "Failed to get headset detect gpio");
return PTR_ERR(priv->gpio_headset_detect);
}
/* Update card-name if provided through DT, else use default name */
snd_soc_of_parse_card_name(card, "model");
ret = snd_soc_of_parse_audio_routing(card, "audio-routing");
if (ret < 0) {
/* Backwards compatible way */
ret = snd_soc_of_parse_audio_routing(card, "samsung,audio-routing");
if (ret < 0) {
dev_err(dev, "Audio routing invalid/unspecified\n");
return ret;
}
}
aries_dai[1].dai_fmt = priv->variant->modem_dai_fmt;
cpu = of_get_child_by_name(dev->of_node, "cpu");
if (!cpu)
return -EINVAL;
codec = of_get_child_by_name(dev->of_node, "codec");
if (!codec) {
ret = -EINVAL;
goto out;
}
for_each_card_prelinks(card, i, dai_link) {
dai_link->codecs->of_node = of_parse_phandle(codec,
"sound-dai", 0);
if (!dai_link->codecs->of_node) {
ret = -EINVAL;
goto out;
}
}
/* Set CPU and platform of_node for main DAI */
aries_dai[0].cpus->of_node = of_parse_phandle(cpu,
"sound-dai", 0);
if (!aries_dai[0].cpus->of_node) {
ret = -EINVAL;
goto out;
}
aries_dai[0].platforms->of_node = aries_dai[0].cpus->of_node;
/* Set CPU of_node for BT DAI */
aries_dai[2].cpus->of_node = of_parse_phandle(cpu,
"sound-dai", 1);
if (!aries_dai[2].cpus->of_node) {
ret = -EINVAL;
goto out;
}
ret = devm_snd_soc_register_component(dev, &aries_component,
aries_ext_dai, ARRAY_SIZE(aries_ext_dai));
if (ret < 0) {
dev_err(dev, "Failed to register component: %d\n", ret);
goto out;
}
ret = devm_snd_soc_register_card(dev, card);
if (ret)
dev_err(dev, "snd_soc_register_card() failed:%d\n", ret);
out:
of_node_put(cpu);
of_node_put(codec);
return ret;
}
static struct platform_driver aries_audio_driver = {
.driver = {
.name = "aries-audio-wm8994",
.of_match_table = of_match_ptr(samsung_wm8994_of_match),
.pm = &snd_soc_pm_ops,
},
.probe = aries_audio_probe,
};
module_platform_driver(aries_audio_driver);
MODULE_DESCRIPTION("ALSA SoC ARIES WM8994");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:aries-audio-wm8994");
| linux-master | sound/soc/samsung/aries_wm8994.c |
// SPDX-License-Identifier: GPL-2.0+
//
// idma.c - I2S0 internal DMA driver
//
// Copyright (c) 2011 Samsung Electronics Co., Ltd.
// http://www.samsung.com
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include "i2s.h"
#include "idma.h"
#include "i2s-regs.h"
#define ST_RUNNING (1<<0)
#define ST_OPENED (1<<1)
static const struct snd_pcm_hardware idma_hardware = {
.info = SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_BLOCK_TRANSFER |
SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_PAUSE |
SNDRV_PCM_INFO_RESUME,
.buffer_bytes_max = MAX_IDMA_BUFFER,
.period_bytes_min = 128,
.period_bytes_max = MAX_IDMA_PERIOD,
.periods_min = 1,
.periods_max = 2,
};
struct idma_ctrl {
spinlock_t lock;
int state;
dma_addr_t start;
dma_addr_t pos;
dma_addr_t end;
dma_addr_t period;
dma_addr_t periodsz;
void *token;
void (*cb)(void *dt, int bytes_xfer);
};
static struct idma_info {
spinlock_t lock;
void __iomem *regs;
dma_addr_t lp_tx_addr;
} idma;
static int idma_irq;
static void idma_getpos(dma_addr_t *src)
{
*src = idma.lp_tx_addr +
(readl(idma.regs + I2STRNCNT) & 0xffffff) * 4;
}
static int idma_enqueue(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct idma_ctrl *prtd = substream->runtime->private_data;
u32 val;
spin_lock(&prtd->lock);
prtd->token = (void *) substream;
spin_unlock(&prtd->lock);
/* Internal DMA Level0 Interrupt Address */
val = idma.lp_tx_addr + prtd->periodsz;
writel(val, idma.regs + I2SLVL0ADDR);
/* Start address0 of I2S internal DMA operation. */
val = idma.lp_tx_addr;
writel(val, idma.regs + I2SSTR0);
/*
* Transfer block size for I2S internal DMA.
* Should decide transfer size before start dma operation
*/
val = readl(idma.regs + I2SSIZE);
val &= ~(I2SSIZE_TRNMSK << I2SSIZE_SHIFT);
val |= (((runtime->dma_bytes >> 2) &
I2SSIZE_TRNMSK) << I2SSIZE_SHIFT);
writel(val, idma.regs + I2SSIZE);
val = readl(idma.regs + I2SAHB);
val |= AHB_INTENLVL0;
writel(val, idma.regs + I2SAHB);
return 0;
}
static void idma_setcallbk(struct snd_pcm_substream *substream,
void (*cb)(void *, int))
{
struct idma_ctrl *prtd = substream->runtime->private_data;
spin_lock(&prtd->lock);
prtd->cb = cb;
spin_unlock(&prtd->lock);
}
static void idma_control(int op)
{
u32 val = readl(idma.regs + I2SAHB);
spin_lock(&idma.lock);
switch (op) {
case LPAM_DMA_START:
val |= (AHB_INTENLVL0 | AHB_DMAEN);
break;
case LPAM_DMA_STOP:
val &= ~(AHB_INTENLVL0 | AHB_DMAEN);
break;
default:
spin_unlock(&idma.lock);
return;
}
writel(val, idma.regs + I2SAHB);
spin_unlock(&idma.lock);
}
static void idma_done(void *id, int bytes_xfer)
{
struct snd_pcm_substream *substream = id;
struct idma_ctrl *prtd = substream->runtime->private_data;
if (prtd && (prtd->state & ST_RUNNING))
snd_pcm_period_elapsed(substream);
}
static int idma_hw_params(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct idma_ctrl *prtd = substream->runtime->private_data;
u32 mod = readl(idma.regs + I2SMOD);
u32 ahb = readl(idma.regs + I2SAHB);
ahb |= (AHB_DMARLD | AHB_INTMASK);
mod |= MOD_TXS_IDMA;
writel(ahb, idma.regs + I2SAHB);
writel(mod, idma.regs + I2SMOD);
snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
runtime->dma_bytes = params_buffer_bytes(params);
prtd->start = prtd->pos = runtime->dma_addr;
prtd->period = params_periods(params);
prtd->periodsz = params_period_bytes(params);
prtd->end = runtime->dma_addr + runtime->dma_bytes;
idma_setcallbk(substream, idma_done);
return 0;
}
static int idma_hw_free(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
snd_pcm_set_runtime_buffer(substream, NULL);
return 0;
}
static int idma_prepare(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct idma_ctrl *prtd = substream->runtime->private_data;
prtd->pos = prtd->start;
/* flush the DMA channel */
idma_control(LPAM_DMA_STOP);
idma_enqueue(substream);
return 0;
}
static int idma_trigger(struct snd_soc_component *component,
struct snd_pcm_substream *substream, int cmd)
{
struct idma_ctrl *prtd = substream->runtime->private_data;
int ret = 0;
spin_lock(&prtd->lock);
switch (cmd) {
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
prtd->state |= ST_RUNNING;
idma_control(LPAM_DMA_START);
break;
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
prtd->state &= ~ST_RUNNING;
idma_control(LPAM_DMA_STOP);
break;
default:
ret = -EINVAL;
break;
}
spin_unlock(&prtd->lock);
return ret;
}
static snd_pcm_uframes_t
idma_pointer(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct idma_ctrl *prtd = runtime->private_data;
dma_addr_t src;
unsigned long res;
spin_lock(&prtd->lock);
idma_getpos(&src);
res = src - prtd->start;
spin_unlock(&prtd->lock);
return bytes_to_frames(substream->runtime, res);
}
static int idma_mmap(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct vm_area_struct *vma)
{
struct snd_pcm_runtime *runtime = substream->runtime;
unsigned long size, offset;
/* From snd_pcm_lib_mmap_iomem */
vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
size = vma->vm_end - vma->vm_start;
offset = vma->vm_pgoff << PAGE_SHIFT;
return io_remap_pfn_range(vma, vma->vm_start,
(runtime->dma_addr + offset) >> PAGE_SHIFT,
size, vma->vm_page_prot);
}
static irqreturn_t iis_irq(int irqno, void *dev_id)
{
struct idma_ctrl *prtd = (struct idma_ctrl *)dev_id;
u32 iisahb, val, addr;
iisahb = readl(idma.regs + I2SAHB);
val = (iisahb & AHB_LVL0INT) ? AHB_CLRLVL0INT : 0;
if (val) {
iisahb |= val;
writel(iisahb, idma.regs + I2SAHB);
addr = readl(idma.regs + I2SLVL0ADDR) - idma.lp_tx_addr;
addr += prtd->periodsz;
addr %= (u32)(prtd->end - prtd->start);
addr += idma.lp_tx_addr;
writel(addr, idma.regs + I2SLVL0ADDR);
if (prtd->cb)
prtd->cb(prtd->token, prtd->period);
}
return IRQ_HANDLED;
}
static int idma_open(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct idma_ctrl *prtd;
int ret;
snd_soc_set_runtime_hwparams(substream, &idma_hardware);
prtd = kzalloc(sizeof(struct idma_ctrl), GFP_KERNEL);
if (prtd == NULL)
return -ENOMEM;
ret = request_irq(idma_irq, iis_irq, 0, "i2s", prtd);
if (ret < 0) {
pr_err("fail to claim i2s irq , ret = %d\n", ret);
kfree(prtd);
return ret;
}
spin_lock_init(&prtd->lock);
runtime->private_data = prtd;
return 0;
}
static int idma_close(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct idma_ctrl *prtd = runtime->private_data;
free_irq(idma_irq, prtd);
if (!prtd)
pr_err("idma_close called with prtd == NULL\n");
kfree(prtd);
return 0;
}
static void idma_free(struct snd_soc_component *component,
struct snd_pcm *pcm)
{
struct snd_pcm_substream *substream;
struct snd_dma_buffer *buf;
substream = pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
if (!substream)
return;
buf = &substream->dma_buffer;
if (!buf->area)
return;
iounmap((void __iomem *)buf->area);
buf->area = NULL;
buf->addr = 0;
}
static int preallocate_idma_buffer(struct snd_pcm *pcm, int stream)
{
struct snd_pcm_substream *substream = pcm->streams[stream].substream;
struct snd_dma_buffer *buf = &substream->dma_buffer;
buf->dev.dev = pcm->card->dev;
buf->private_data = NULL;
/* Assign PCM buffer pointers */
buf->dev.type = SNDRV_DMA_TYPE_CONTINUOUS;
buf->addr = idma.lp_tx_addr;
buf->bytes = idma_hardware.buffer_bytes_max;
buf->area = (unsigned char * __force)ioremap(buf->addr, buf->bytes);
if (!buf->area)
return -ENOMEM;
return 0;
}
static int idma_new(struct snd_soc_component *component,
struct snd_soc_pcm_runtime *rtd)
{
struct snd_card *card = rtd->card->snd_card;
struct snd_pcm *pcm = rtd->pcm;
int ret;
ret = dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(32));
if (ret)
return ret;
if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) {
ret = preallocate_idma_buffer(pcm,
SNDRV_PCM_STREAM_PLAYBACK);
}
return ret;
}
void idma_reg_addr_init(void __iomem *regs, dma_addr_t addr)
{
spin_lock_init(&idma.lock);
idma.regs = regs;
idma.lp_tx_addr = addr;
}
EXPORT_SYMBOL_GPL(idma_reg_addr_init);
static const struct snd_soc_component_driver asoc_idma_platform = {
.open = idma_open,
.close = idma_close,
.trigger = idma_trigger,
.pointer = idma_pointer,
.mmap = idma_mmap,
.hw_params = idma_hw_params,
.hw_free = idma_hw_free,
.prepare = idma_prepare,
.pcm_construct = idma_new,
.pcm_destruct = idma_free,
};
static int asoc_idma_platform_probe(struct platform_device *pdev)
{
idma_irq = platform_get_irq(pdev, 0);
if (idma_irq < 0)
return idma_irq;
return devm_snd_soc_register_component(&pdev->dev, &asoc_idma_platform,
NULL, 0);
}
static struct platform_driver asoc_idma_driver = {
.driver = {
.name = "samsung-idma",
},
.probe = asoc_idma_platform_probe,
};
module_platform_driver(asoc_idma_driver);
MODULE_AUTHOR("Jaswinder Singh, <[email protected]>");
MODULE_DESCRIPTION("Samsung ASoC IDMA Driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/samsung/idma.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2010, Lars-Peter Clausen <[email protected]>
*/
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/dmaengine_pcm.h>
#define JZ_REG_AIC_CONF 0x00
#define JZ_REG_AIC_CTRL 0x04
#define JZ_REG_AIC_I2S_FMT 0x10
#define JZ_REG_AIC_FIFO_STATUS 0x14
#define JZ_REG_AIC_I2S_STATUS 0x1c
#define JZ_REG_AIC_CLK_DIV 0x30
#define JZ_REG_AIC_FIFO 0x34
#define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6)
#define JZ_AIC_CONF_INTERNAL_CODEC BIT(5)
#define JZ_AIC_CONF_I2S BIT(4)
#define JZ_AIC_CONF_RESET BIT(3)
#define JZ_AIC_CONF_BIT_CLK_MASTER BIT(2)
#define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1)
#define JZ_AIC_CONF_ENABLE BIT(0)
#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE GENMASK(21, 19)
#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE GENMASK(18, 16)
#define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15)
#define JZ_AIC_CTRL_ENABLE_TX_DMA BIT(14)
#define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11)
#define JZ_AIC_CTRL_SWITCH_ENDIANNESS BIT(10)
#define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED BIT(9)
#define JZ_AIC_CTRL_TFLUSH BIT(8)
#define JZ_AIC_CTRL_RFLUSH BIT(7)
#define JZ_AIC_CTRL_ENABLE_ROR_INT BIT(6)
#define JZ_AIC_CTRL_ENABLE_TUR_INT BIT(5)
#define JZ_AIC_CTRL_ENABLE_RFS_INT BIT(4)
#define JZ_AIC_CTRL_ENABLE_TFS_INT BIT(3)
#define JZ_AIC_CTRL_ENABLE_LOOPBACK BIT(2)
#define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1)
#define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0)
#define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12)
#define JZ_AIC_I2S_FMT_DISABLE_BIT_ICLK BIT(13)
#define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK BIT(4)
#define JZ_AIC_I2S_FMT_MSB BIT(0)
#define JZ_AIC_I2S_STATUS_BUSY BIT(2)
struct i2s_soc_info {
struct snd_soc_dai_driver *dai;
struct reg_field field_rx_fifo_thresh;
struct reg_field field_tx_fifo_thresh;
struct reg_field field_i2sdiv_capture;
struct reg_field field_i2sdiv_playback;
bool shared_fifo_flush;
};
struct jz4740_i2s {
struct regmap *regmap;
struct regmap_field *field_rx_fifo_thresh;
struct regmap_field *field_tx_fifo_thresh;
struct regmap_field *field_i2sdiv_capture;
struct regmap_field *field_i2sdiv_playback;
struct clk *clk_aic;
struct clk *clk_i2s;
struct snd_dmaengine_dai_dma_data playback_dma_data;
struct snd_dmaengine_dai_dma_data capture_dma_data;
const struct i2s_soc_info *soc_info;
};
static int jz4740_i2s_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
int ret;
/*
* When we can flush FIFOs independently, only flush the FIFO
* that is starting up. We can do this when the DAI is active
* because it does not disturb other active substreams.
*/
if (!i2s->soc_info->shared_fifo_flush) {
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_TFLUSH);
else
regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_RFLUSH);
}
if (snd_soc_dai_active(dai))
return 0;
/*
* When there is a shared flush bit for both FIFOs, the TFLUSH
* bit flushes both FIFOs. Flushing while the DAI is active would
* cause FIFO underruns in other active substreams so we have to
* guard this behind the snd_soc_dai_active() check.
*/
if (i2s->soc_info->shared_fifo_flush)
regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_TFLUSH);
ret = clk_prepare_enable(i2s->clk_i2s);
if (ret)
return ret;
regmap_set_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE);
return 0;
}
static void jz4740_i2s_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
if (snd_soc_dai_active(dai))
return;
regmap_clear_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE);
clk_disable_unprepare(i2s->clk_i2s);
}
static int jz4740_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
uint32_t mask;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
mask = JZ_AIC_CTRL_ENABLE_PLAYBACK | JZ_AIC_CTRL_ENABLE_TX_DMA;
else
mask = JZ_AIC_CTRL_ENABLE_CAPTURE | JZ_AIC_CTRL_ENABLE_RX_DMA;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, mask);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
regmap_clear_bits(i2s->regmap, JZ_REG_AIC_CTRL, mask);
break;
default:
return -EINVAL;
}
return 0;
}
static int jz4740_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
const unsigned int conf_mask = JZ_AIC_CONF_BIT_CLK_MASTER |
JZ_AIC_CONF_SYNC_CLK_MASTER;
unsigned int conf = 0, format = 0;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BP_FP:
conf |= JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER;
format |= JZ_AIC_I2S_FMT_ENABLE_SYS_CLK;
break;
case SND_SOC_DAIFMT_BC_FP:
conf |= JZ_AIC_CONF_SYNC_CLK_MASTER;
break;
case SND_SOC_DAIFMT_BP_FC:
conf |= JZ_AIC_CONF_BIT_CLK_MASTER;
break;
case SND_SOC_DAIFMT_BC_FC:
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_MSB:
format |= JZ_AIC_I2S_FMT_MSB;
break;
case SND_SOC_DAIFMT_I2S:
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
default:
return -EINVAL;
}
regmap_update_bits(i2s->regmap, JZ_REG_AIC_CONF, conf_mask, conf);
regmap_write(i2s->regmap, JZ_REG_AIC_I2S_FMT, format);
return 0;
}
static int jz4740_i2s_get_i2sdiv(unsigned long mclk, unsigned long rate,
unsigned long i2sdiv_max)
{
unsigned long div, rate1, rate2, err1, err2;
div = mclk / (64 * rate);
if (div == 0)
div = 1;
rate1 = mclk / (64 * div);
rate2 = mclk / (64 * (div + 1));
err1 = abs(rate1 - rate);
err2 = abs(rate2 - rate);
/*
* Choose the divider that produces the smallest error in the
* output rate and reject dividers with a 5% or higher error.
* In the event that both dividers are outside the acceptable
* error margin, reject the rate to prevent distorted audio.
* (The number 5% is arbitrary.)
*/
if (div <= i2sdiv_max && err1 <= err2 && err1 < rate/20)
return div;
if (div < i2sdiv_max && err2 < rate/20)
return div + 1;
return -EINVAL;
}
static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
struct regmap_field *div_field;
unsigned long i2sdiv_max;
unsigned int sample_size;
uint32_t ctrl, conf;
int div = 1;
regmap_read(i2s->regmap, JZ_REG_AIC_CTRL, &ctrl);
regmap_read(i2s->regmap, JZ_REG_AIC_CONF, &conf);
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S8:
sample_size = 0;
break;
case SNDRV_PCM_FORMAT_S16_LE:
sample_size = 1;
break;
case SNDRV_PCM_FORMAT_S20_LE:
sample_size = 3;
break;
case SNDRV_PCM_FORMAT_S24_LE:
sample_size = 4;
break;
default:
return -EINVAL;
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
ctrl &= ~JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE;
ctrl |= FIELD_PREP(JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE, sample_size);
if (params_channels(params) == 1)
ctrl |= JZ_AIC_CTRL_MONO_TO_STEREO;
else
ctrl &= ~JZ_AIC_CTRL_MONO_TO_STEREO;
div_field = i2s->field_i2sdiv_playback;
i2sdiv_max = GENMASK(i2s->soc_info->field_i2sdiv_playback.msb,
i2s->soc_info->field_i2sdiv_playback.lsb);
} else {
ctrl &= ~JZ_AIC_CTRL_INPUT_SAMPLE_SIZE;
ctrl |= FIELD_PREP(JZ_AIC_CTRL_INPUT_SAMPLE_SIZE, sample_size);
div_field = i2s->field_i2sdiv_capture;
i2sdiv_max = GENMASK(i2s->soc_info->field_i2sdiv_capture.msb,
i2s->soc_info->field_i2sdiv_capture.lsb);
}
/*
* Only calculate I2SDIV if we're supplying the bit or frame clock.
* If the codec is supplying both clocks then the divider output is
* unused, and we don't want it to limit the allowed sample rates.
*/
if (conf & (JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER)) {
div = jz4740_i2s_get_i2sdiv(clk_get_rate(i2s->clk_i2s),
params_rate(params), i2sdiv_max);
if (div < 0)
return div;
}
regmap_write(i2s->regmap, JZ_REG_AIC_CTRL, ctrl);
regmap_field_write(div_field, div - 1);
return 0;
}
static int jz4740_i2s_dai_probe(struct snd_soc_dai *dai)
{
struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
snd_soc_dai_init_dma_data(dai, &i2s->playback_dma_data,
&i2s->capture_dma_data);
return 0;
}
static const struct snd_soc_dai_ops jz4740_i2s_dai_ops = {
.probe = jz4740_i2s_dai_probe,
.startup = jz4740_i2s_startup,
.shutdown = jz4740_i2s_shutdown,
.trigger = jz4740_i2s_trigger,
.hw_params = jz4740_i2s_hw_params,
.set_fmt = jz4740_i2s_set_fmt,
};
#define JZ4740_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | \
SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S20_LE | \
SNDRV_PCM_FMTBIT_S24_LE)
static struct snd_soc_dai_driver jz4740_i2s_dai = {
.playback = {
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_CONTINUOUS,
.formats = JZ4740_I2S_FMTS,
},
.capture = {
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_CONTINUOUS,
.formats = JZ4740_I2S_FMTS,
},
.symmetric_rate = 1,
.ops = &jz4740_i2s_dai_ops,
};
static const struct i2s_soc_info jz4740_i2s_soc_info = {
.dai = &jz4740_i2s_dai,
.field_rx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 12, 15),
.field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 8, 11),
.field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3),
.field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3),
.shared_fifo_flush = true,
};
static const struct i2s_soc_info jz4760_i2s_soc_info = {
.dai = &jz4740_i2s_dai,
.field_rx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 24, 27),
.field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20),
.field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3),
.field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3),
};
static const struct i2s_soc_info x1000_i2s_soc_info = {
.dai = &jz4740_i2s_dai,
.field_rx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 24, 27),
.field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20),
.field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 8),
.field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 8),
};
static struct snd_soc_dai_driver jz4770_i2s_dai = {
.playback = {
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_CONTINUOUS,
.formats = JZ4740_I2S_FMTS,
},
.capture = {
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_CONTINUOUS,
.formats = JZ4740_I2S_FMTS,
},
.ops = &jz4740_i2s_dai_ops,
};
static const struct i2s_soc_info jz4770_i2s_soc_info = {
.dai = &jz4770_i2s_dai,
.field_rx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 24, 27),
.field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20),
.field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 8, 11),
.field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3),
};
static const struct i2s_soc_info jz4780_i2s_soc_info = {
.dai = &jz4770_i2s_dai,
.field_rx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 24, 27),
.field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20),
.field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 8, 11),
.field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3),
};
static int jz4740_i2s_suspend(struct snd_soc_component *component)
{
struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component);
if (snd_soc_component_active(component)) {
regmap_clear_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE);
clk_disable_unprepare(i2s->clk_i2s);
}
clk_disable_unprepare(i2s->clk_aic);
return 0;
}
static int jz4740_i2s_resume(struct snd_soc_component *component)
{
struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component);
int ret;
ret = clk_prepare_enable(i2s->clk_aic);
if (ret)
return ret;
if (snd_soc_component_active(component)) {
ret = clk_prepare_enable(i2s->clk_i2s);
if (ret) {
clk_disable_unprepare(i2s->clk_aic);
return ret;
}
regmap_set_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE);
}
return 0;
}
static int jz4740_i2s_probe(struct snd_soc_component *component)
{
struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component);
int ret;
ret = clk_prepare_enable(i2s->clk_aic);
if (ret)
return ret;
regmap_write(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET);
regmap_write(i2s->regmap, JZ_REG_AIC_CONF,
JZ_AIC_CONF_OVERFLOW_PLAY_LAST |
JZ_AIC_CONF_I2S | JZ_AIC_CONF_INTERNAL_CODEC);
regmap_field_write(i2s->field_rx_fifo_thresh, 7);
regmap_field_write(i2s->field_tx_fifo_thresh, 8);
return 0;
}
static void jz4740_i2s_remove(struct snd_soc_component *component)
{
struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component);
clk_disable_unprepare(i2s->clk_aic);
}
static const struct snd_soc_component_driver jz4740_i2s_component = {
.name = "jz4740-i2s",
.probe = jz4740_i2s_probe,
.remove = jz4740_i2s_remove,
.suspend = jz4740_i2s_suspend,
.resume = jz4740_i2s_resume,
.legacy_dai_naming = 1,
};
static const struct of_device_id jz4740_of_matches[] = {
{ .compatible = "ingenic,jz4740-i2s", .data = &jz4740_i2s_soc_info },
{ .compatible = "ingenic,jz4760-i2s", .data = &jz4760_i2s_soc_info },
{ .compatible = "ingenic,jz4770-i2s", .data = &jz4770_i2s_soc_info },
{ .compatible = "ingenic,jz4780-i2s", .data = &jz4780_i2s_soc_info },
{ .compatible = "ingenic,x1000-i2s", .data = &x1000_i2s_soc_info },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, jz4740_of_matches);
static int jz4740_i2s_init_regmap_fields(struct device *dev,
struct jz4740_i2s *i2s)
{
i2s->field_rx_fifo_thresh =
devm_regmap_field_alloc(dev, i2s->regmap,
i2s->soc_info->field_rx_fifo_thresh);
if (IS_ERR(i2s->field_rx_fifo_thresh))
return PTR_ERR(i2s->field_rx_fifo_thresh);
i2s->field_tx_fifo_thresh =
devm_regmap_field_alloc(dev, i2s->regmap,
i2s->soc_info->field_tx_fifo_thresh);
if (IS_ERR(i2s->field_tx_fifo_thresh))
return PTR_ERR(i2s->field_tx_fifo_thresh);
i2s->field_i2sdiv_capture =
devm_regmap_field_alloc(dev, i2s->regmap,
i2s->soc_info->field_i2sdiv_capture);
if (IS_ERR(i2s->field_i2sdiv_capture))
return PTR_ERR(i2s->field_i2sdiv_capture);
i2s->field_i2sdiv_playback =
devm_regmap_field_alloc(dev, i2s->regmap,
i2s->soc_info->field_i2sdiv_playback);
if (IS_ERR(i2s->field_i2sdiv_playback))
return PTR_ERR(i2s->field_i2sdiv_playback);
return 0;
}
static const struct regmap_config jz4740_i2s_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = JZ_REG_AIC_FIFO,
};
static int jz4740_i2s_dev_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct jz4740_i2s *i2s;
struct resource *mem;
void __iomem *regs;
int ret;
i2s = devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL);
if (!i2s)
return -ENOMEM;
i2s->soc_info = device_get_match_data(dev);
regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
if (IS_ERR(regs))
return PTR_ERR(regs);
i2s->playback_dma_data.maxburst = 16;
i2s->playback_dma_data.addr = mem->start + JZ_REG_AIC_FIFO;
i2s->capture_dma_data.maxburst = 16;
i2s->capture_dma_data.addr = mem->start + JZ_REG_AIC_FIFO;
i2s->clk_aic = devm_clk_get(dev, "aic");
if (IS_ERR(i2s->clk_aic))
return PTR_ERR(i2s->clk_aic);
i2s->clk_i2s = devm_clk_get(dev, "i2s");
if (IS_ERR(i2s->clk_i2s))
return PTR_ERR(i2s->clk_i2s);
i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
&jz4740_i2s_regmap_config);
if (IS_ERR(i2s->regmap))
return PTR_ERR(i2s->regmap);
ret = jz4740_i2s_init_regmap_fields(dev, i2s);
if (ret)
return ret;
platform_set_drvdata(pdev, i2s);
ret = devm_snd_soc_register_component(dev, &jz4740_i2s_component,
i2s->soc_info->dai, 1);
if (ret)
return ret;
return devm_snd_dmaengine_pcm_register(dev, NULL,
SND_DMAENGINE_PCM_FLAG_COMPAT);
}
static struct platform_driver jz4740_i2s_driver = {
.probe = jz4740_i2s_dev_probe,
.driver = {
.name = "jz4740-i2s",
.of_match_table = jz4740_of_matches,
},
};
module_platform_driver(jz4740_i2s_driver);
MODULE_AUTHOR("Lars-Peter Clausen, <[email protected]>");
MODULE_DESCRIPTION("Ingenic JZ4740 SoC I2S driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:jz4740-i2s");
| linux-master | sound/soc/jz4740/jz4740-i2s.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* STM32 ALSA SoC Digital Audio Interface (I2S) driver.
*
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
* Author(s): Olivier Moysan <[email protected]> for STMicroelectronics.
*/
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/spinlock.h>
#include <sound/dmaengine_pcm.h>
#include <sound/pcm_params.h>
#define STM32_I2S_CR1_REG 0x0
#define STM32_I2S_CFG1_REG 0x08
#define STM32_I2S_CFG2_REG 0x0C
#define STM32_I2S_IER_REG 0x10
#define STM32_I2S_SR_REG 0x14
#define STM32_I2S_IFCR_REG 0x18
#define STM32_I2S_TXDR_REG 0X20
#define STM32_I2S_RXDR_REG 0x30
#define STM32_I2S_CGFR_REG 0X50
#define STM32_I2S_HWCFGR_REG 0x3F0
#define STM32_I2S_VERR_REG 0x3F4
#define STM32_I2S_IPIDR_REG 0x3F8
#define STM32_I2S_SIDR_REG 0x3FC
/* Bit definition for SPI2S_CR1 register */
#define I2S_CR1_SPE BIT(0)
#define I2S_CR1_CSTART BIT(9)
#define I2S_CR1_CSUSP BIT(10)
#define I2S_CR1_HDDIR BIT(11)
#define I2S_CR1_SSI BIT(12)
#define I2S_CR1_CRC33_17 BIT(13)
#define I2S_CR1_RCRCI BIT(14)
#define I2S_CR1_TCRCI BIT(15)
/* Bit definition for SPI_CFG2 register */
#define I2S_CFG2_IOSWP_SHIFT 15
#define I2S_CFG2_IOSWP BIT(I2S_CFG2_IOSWP_SHIFT)
#define I2S_CFG2_LSBFRST BIT(23)
#define I2S_CFG2_AFCNTR BIT(31)
/* Bit definition for SPI_CFG1 register */
#define I2S_CFG1_FTHVL_SHIFT 5
#define I2S_CFG1_FTHVL_MASK GENMASK(8, I2S_CFG1_FTHVL_SHIFT)
#define I2S_CFG1_FTHVL_SET(x) ((x) << I2S_CFG1_FTHVL_SHIFT)
#define I2S_CFG1_TXDMAEN BIT(15)
#define I2S_CFG1_RXDMAEN BIT(14)
/* Bit definition for SPI2S_IER register */
#define I2S_IER_RXPIE BIT(0)
#define I2S_IER_TXPIE BIT(1)
#define I2S_IER_DPXPIE BIT(2)
#define I2S_IER_EOTIE BIT(3)
#define I2S_IER_TXTFIE BIT(4)
#define I2S_IER_UDRIE BIT(5)
#define I2S_IER_OVRIE BIT(6)
#define I2S_IER_CRCEIE BIT(7)
#define I2S_IER_TIFREIE BIT(8)
#define I2S_IER_MODFIE BIT(9)
#define I2S_IER_TSERFIE BIT(10)
/* Bit definition for SPI2S_SR register */
#define I2S_SR_RXP BIT(0)
#define I2S_SR_TXP BIT(1)
#define I2S_SR_DPXP BIT(2)
#define I2S_SR_EOT BIT(3)
#define I2S_SR_TXTF BIT(4)
#define I2S_SR_UDR BIT(5)
#define I2S_SR_OVR BIT(6)
#define I2S_SR_CRCERR BIT(7)
#define I2S_SR_TIFRE BIT(8)
#define I2S_SR_MODF BIT(9)
#define I2S_SR_TSERF BIT(10)
#define I2S_SR_SUSP BIT(11)
#define I2S_SR_TXC BIT(12)
#define I2S_SR_RXPLVL GENMASK(14, 13)
#define I2S_SR_RXWNE BIT(15)
#define I2S_SR_MASK GENMASK(15, 0)
/* Bit definition for SPI_IFCR register */
#define I2S_IFCR_EOTC BIT(3)
#define I2S_IFCR_TXTFC BIT(4)
#define I2S_IFCR_UDRC BIT(5)
#define I2S_IFCR_OVRC BIT(6)
#define I2S_IFCR_CRCEC BIT(7)
#define I2S_IFCR_TIFREC BIT(8)
#define I2S_IFCR_MODFC BIT(9)
#define I2S_IFCR_TSERFC BIT(10)
#define I2S_IFCR_SUSPC BIT(11)
#define I2S_IFCR_MASK GENMASK(11, 3)
/* Bit definition for SPI_I2SCGFR register */
#define I2S_CGFR_I2SMOD BIT(0)
#define I2S_CGFR_I2SCFG_SHIFT 1
#define I2S_CGFR_I2SCFG_MASK GENMASK(3, I2S_CGFR_I2SCFG_SHIFT)
#define I2S_CGFR_I2SCFG_SET(x) ((x) << I2S_CGFR_I2SCFG_SHIFT)
#define I2S_CGFR_I2SSTD_SHIFT 4
#define I2S_CGFR_I2SSTD_MASK GENMASK(5, I2S_CGFR_I2SSTD_SHIFT)
#define I2S_CGFR_I2SSTD_SET(x) ((x) << I2S_CGFR_I2SSTD_SHIFT)
#define I2S_CGFR_PCMSYNC BIT(7)
#define I2S_CGFR_DATLEN_SHIFT 8
#define I2S_CGFR_DATLEN_MASK GENMASK(9, I2S_CGFR_DATLEN_SHIFT)
#define I2S_CGFR_DATLEN_SET(x) ((x) << I2S_CGFR_DATLEN_SHIFT)
#define I2S_CGFR_CHLEN_SHIFT 10
#define I2S_CGFR_CHLEN BIT(I2S_CGFR_CHLEN_SHIFT)
#define I2S_CGFR_CKPOL BIT(11)
#define I2S_CGFR_FIXCH BIT(12)
#define I2S_CGFR_WSINV BIT(13)
#define I2S_CGFR_DATFMT BIT(14)
#define I2S_CGFR_I2SDIV_SHIFT 16
#define I2S_CGFR_I2SDIV_BIT_H 23
#define I2S_CGFR_I2SDIV_MASK GENMASK(I2S_CGFR_I2SDIV_BIT_H,\
I2S_CGFR_I2SDIV_SHIFT)
#define I2S_CGFR_I2SDIV_SET(x) ((x) << I2S_CGFR_I2SDIV_SHIFT)
#define I2S_CGFR_I2SDIV_MAX ((1 << (I2S_CGFR_I2SDIV_BIT_H -\
I2S_CGFR_I2SDIV_SHIFT)) - 1)
#define I2S_CGFR_ODD_SHIFT 24
#define I2S_CGFR_ODD BIT(I2S_CGFR_ODD_SHIFT)
#define I2S_CGFR_MCKOE BIT(25)
/* Registers below apply to I2S version 1.1 and more */
/* Bit definition for SPI_HWCFGR register */
#define I2S_HWCFGR_I2S_SUPPORT_MASK GENMASK(15, 12)
/* Bit definition for SPI_VERR register */
#define I2S_VERR_MIN_MASK GENMASK(3, 0)
#define I2S_VERR_MAJ_MASK GENMASK(7, 4)
/* Bit definition for SPI_IPIDR register */
#define I2S_IPIDR_ID_MASK GENMASK(31, 0)
/* Bit definition for SPI_SIDR register */
#define I2S_SIDR_ID_MASK GENMASK(31, 0)
#define I2S_IPIDR_NUMBER 0x00130022
enum i2s_master_mode {
I2S_MS_NOT_SET,
I2S_MS_MASTER,
I2S_MS_SLAVE,
};
enum i2s_mode {
I2S_I2SMOD_TX_SLAVE,
I2S_I2SMOD_RX_SLAVE,
I2S_I2SMOD_TX_MASTER,
I2S_I2SMOD_RX_MASTER,
I2S_I2SMOD_FD_SLAVE,
I2S_I2SMOD_FD_MASTER,
};
enum i2s_fifo_th {
I2S_FIFO_TH_NONE,
I2S_FIFO_TH_ONE_QUARTER,
I2S_FIFO_TH_HALF,
I2S_FIFO_TH_THREE_QUARTER,
I2S_FIFO_TH_FULL,
};
enum i2s_std {
I2S_STD_I2S,
I2S_STD_LEFT_J,
I2S_STD_RIGHT_J,
I2S_STD_DSP,
};
enum i2s_datlen {
I2S_I2SMOD_DATLEN_16,
I2S_I2SMOD_DATLEN_24,
I2S_I2SMOD_DATLEN_32,
};
#define STM32_I2S_FIFO_SIZE 16
#define STM32_I2S_IS_MASTER(x) ((x)->ms_flg == I2S_MS_MASTER)
#define STM32_I2S_IS_SLAVE(x) ((x)->ms_flg == I2S_MS_SLAVE)
#define STM32_I2S_NAME_LEN 32
#define STM32_I2S_RATE_11K 11025
/**
* struct stm32_i2s_data - private data of I2S
* @regmap_conf: I2S register map configuration pointer
* @regmap: I2S register map pointer
* @pdev: device data pointer
* @dai_drv: DAI driver pointer
* @dma_data_tx: dma configuration data for tx channel
* @dma_data_rx: dma configuration data for tx channel
* @substream: PCM substream data pointer
* @i2sclk: kernel clock feeding the I2S clock generator
* @i2smclk: master clock from I2S mclk provider
* @pclk: peripheral clock driving bus interface
* @x8kclk: I2S parent clock for sampling frequencies multiple of 8kHz
* @x11kclk: I2S parent clock for sampling frequencies multiple of 11kHz
* @base: mmio register base virtual address
* @phys_addr: I2S registers physical base address
* @lock_fd: lock to manage race conditions in full duplex mode
* @irq_lock: prevent race condition with IRQ
* @mclk_rate: master clock frequency (Hz)
* @fmt: DAI protocol
* @divider: prescaler division ratio
* @div: prescaler div field
* @odd: prescaler odd field
* @refcount: keep count of opened streams on I2S
* @ms_flg: master mode flag.
*/
struct stm32_i2s_data {
const struct regmap_config *regmap_conf;
struct regmap *regmap;
struct platform_device *pdev;
struct snd_soc_dai_driver *dai_drv;
struct snd_dmaengine_dai_dma_data dma_data_tx;
struct snd_dmaengine_dai_dma_data dma_data_rx;
struct snd_pcm_substream *substream;
struct clk *i2sclk;
struct clk *i2smclk;
struct clk *pclk;
struct clk *x8kclk;
struct clk *x11kclk;
void __iomem *base;
dma_addr_t phys_addr;
spinlock_t lock_fd; /* Manage race conditions for full duplex */
spinlock_t irq_lock; /* used to prevent race condition with IRQ */
unsigned int mclk_rate;
unsigned int fmt;
unsigned int divider;
unsigned int div;
bool odd;
int refcount;
int ms_flg;
};
struct stm32_i2smclk_data {
struct clk_hw hw;
unsigned long freq;
struct stm32_i2s_data *i2s_data;
};
#define to_mclk_data(_hw) container_of(_hw, struct stm32_i2smclk_data, hw)
static int stm32_i2s_calc_clk_div(struct stm32_i2s_data *i2s,
unsigned long input_rate,
unsigned long output_rate)
{
unsigned int ratio, div, divider = 1;
bool odd;
ratio = DIV_ROUND_CLOSEST(input_rate, output_rate);
/* Check the parity of the divider */
odd = ratio & 0x1;
/* Compute the div prescaler */
div = ratio >> 1;
/* If div is 0 actual divider is 1 */
if (div) {
divider = ((2 * div) + odd);
dev_dbg(&i2s->pdev->dev, "Divider: 2*%d(div)+%d(odd) = %d\n",
div, odd, divider);
}
/* Division by three is not allowed by I2S prescaler */
if ((div == 1 && odd) || div > I2S_CGFR_I2SDIV_MAX) {
dev_err(&i2s->pdev->dev, "Wrong divider setting\n");
return -EINVAL;
}
if (input_rate % divider)
dev_dbg(&i2s->pdev->dev,
"Rate not accurate. requested (%ld), actual (%ld)\n",
output_rate, input_rate / divider);
i2s->div = div;
i2s->odd = odd;
i2s->divider = divider;
return 0;
}
static int stm32_i2s_set_clk_div(struct stm32_i2s_data *i2s)
{
u32 cgfr, cgfr_mask;
cgfr = I2S_CGFR_I2SDIV_SET(i2s->div) | (i2s->odd << I2S_CGFR_ODD_SHIFT);
cgfr_mask = I2S_CGFR_I2SDIV_MASK | I2S_CGFR_ODD;
return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
cgfr_mask, cgfr);
}
static int stm32_i2s_set_parent_clock(struct stm32_i2s_data *i2s,
unsigned int rate)
{
struct platform_device *pdev = i2s->pdev;
struct clk *parent_clk;
int ret;
if (!(rate % STM32_I2S_RATE_11K))
parent_clk = i2s->x11kclk;
else
parent_clk = i2s->x8kclk;
ret = clk_set_parent(i2s->i2sclk, parent_clk);
if (ret)
dev_err(&pdev->dev,
"Error %d setting i2sclk parent clock\n", ret);
return ret;
}
static long stm32_i2smclk_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
struct stm32_i2s_data *i2s = mclk->i2s_data;
int ret;
ret = stm32_i2s_calc_clk_div(i2s, *prate, rate);
if (ret)
return ret;
mclk->freq = *prate / i2s->divider;
return mclk->freq;
}
static unsigned long stm32_i2smclk_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
return mclk->freq;
}
static int stm32_i2smclk_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
struct stm32_i2s_data *i2s = mclk->i2s_data;
int ret;
ret = stm32_i2s_calc_clk_div(i2s, parent_rate, rate);
if (ret)
return ret;
ret = stm32_i2s_set_clk_div(i2s);
if (ret)
return ret;
mclk->freq = rate;
return 0;
}
static int stm32_i2smclk_enable(struct clk_hw *hw)
{
struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
struct stm32_i2s_data *i2s = mclk->i2s_data;
dev_dbg(&i2s->pdev->dev, "Enable master clock\n");
return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
I2S_CGFR_MCKOE, I2S_CGFR_MCKOE);
}
static void stm32_i2smclk_disable(struct clk_hw *hw)
{
struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
struct stm32_i2s_data *i2s = mclk->i2s_data;
dev_dbg(&i2s->pdev->dev, "Disable master clock\n");
regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG, I2S_CGFR_MCKOE, 0);
}
static const struct clk_ops mclk_ops = {
.enable = stm32_i2smclk_enable,
.disable = stm32_i2smclk_disable,
.recalc_rate = stm32_i2smclk_recalc_rate,
.round_rate = stm32_i2smclk_round_rate,
.set_rate = stm32_i2smclk_set_rate,
};
static int stm32_i2s_add_mclk_provider(struct stm32_i2s_data *i2s)
{
struct clk_hw *hw;
struct stm32_i2smclk_data *mclk;
struct device *dev = &i2s->pdev->dev;
const char *pname = __clk_get_name(i2s->i2sclk);
char *mclk_name, *p, *s = (char *)pname;
int ret, i = 0;
mclk = devm_kzalloc(dev, sizeof(*mclk), GFP_KERNEL);
if (!mclk)
return -ENOMEM;
mclk_name = devm_kcalloc(dev, sizeof(char),
STM32_I2S_NAME_LEN, GFP_KERNEL);
if (!mclk_name)
return -ENOMEM;
/*
* Forge mclk clock name from parent clock name and suffix.
* String after "_" char is stripped in parent name.
*/
p = mclk_name;
while (*s && *s != '_' && (i < (STM32_I2S_NAME_LEN - 7))) {
*p++ = *s++;
i++;
}
strcat(p, "_mclk");
mclk->hw.init = CLK_HW_INIT(mclk_name, pname, &mclk_ops, 0);
mclk->i2s_data = i2s;
hw = &mclk->hw;
dev_dbg(dev, "Register master clock %s\n", mclk_name);
ret = devm_clk_hw_register(&i2s->pdev->dev, hw);
if (ret) {
dev_err(dev, "mclk register fails with error %d\n", ret);
return ret;
}
i2s->i2smclk = hw->clk;
/* register mclk provider */
return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
}
static irqreturn_t stm32_i2s_isr(int irq, void *devid)
{
struct stm32_i2s_data *i2s = (struct stm32_i2s_data *)devid;
struct platform_device *pdev = i2s->pdev;
u32 sr, ier;
unsigned long flags;
int err = 0;
regmap_read(i2s->regmap, STM32_I2S_SR_REG, &sr);
regmap_read(i2s->regmap, STM32_I2S_IER_REG, &ier);
flags = sr & ier;
if (!flags) {
dev_dbg(&pdev->dev, "Spurious IRQ sr=0x%08x, ier=0x%08x\n",
sr, ier);
return IRQ_NONE;
}
regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
I2S_IFCR_MASK, flags);
if (flags & I2S_SR_OVR) {
dev_dbg(&pdev->dev, "Overrun\n");
err = 1;
}
if (flags & I2S_SR_UDR) {
dev_dbg(&pdev->dev, "Underrun\n");
err = 1;
}
if (flags & I2S_SR_TIFRE)
dev_dbg(&pdev->dev, "Frame error\n");
spin_lock(&i2s->irq_lock);
if (err && i2s->substream)
snd_pcm_stop_xrun(i2s->substream);
spin_unlock(&i2s->irq_lock);
return IRQ_HANDLED;
}
static bool stm32_i2s_readable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case STM32_I2S_CR1_REG:
case STM32_I2S_CFG1_REG:
case STM32_I2S_CFG2_REG:
case STM32_I2S_IER_REG:
case STM32_I2S_SR_REG:
case STM32_I2S_RXDR_REG:
case STM32_I2S_CGFR_REG:
case STM32_I2S_HWCFGR_REG:
case STM32_I2S_VERR_REG:
case STM32_I2S_IPIDR_REG:
case STM32_I2S_SIDR_REG:
return true;
default:
return false;
}
}
static bool stm32_i2s_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case STM32_I2S_SR_REG:
case STM32_I2S_RXDR_REG:
return true;
default:
return false;
}
}
static bool stm32_i2s_writeable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case STM32_I2S_CR1_REG:
case STM32_I2S_CFG1_REG:
case STM32_I2S_CFG2_REG:
case STM32_I2S_IER_REG:
case STM32_I2S_IFCR_REG:
case STM32_I2S_TXDR_REG:
case STM32_I2S_CGFR_REG:
return true;
default:
return false;
}
}
static int stm32_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
{
struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
u32 cgfr;
u32 cgfr_mask = I2S_CGFR_I2SSTD_MASK | I2S_CGFR_CKPOL |
I2S_CGFR_WSINV | I2S_CGFR_I2SCFG_MASK;
dev_dbg(cpu_dai->dev, "fmt %x\n", fmt);
/*
* winv = 0 : default behavior (high/low) for all standards
* ckpol = 0 for all standards.
*/
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_I2S);
break;
case SND_SOC_DAIFMT_MSB:
cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_LEFT_J);
break;
case SND_SOC_DAIFMT_LSB:
cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_RIGHT_J);
break;
case SND_SOC_DAIFMT_DSP_A:
cgfr = I2S_CGFR_I2SSTD_SET(I2S_STD_DSP);
break;
/* DSP_B not mapped on I2S PCM long format. 1 bit offset does not fit */
default:
dev_err(cpu_dai->dev, "Unsupported protocol %#x\n",
fmt & SND_SOC_DAIFMT_FORMAT_MASK);
return -EINVAL;
}
/* DAI clock strobing */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
cgfr |= I2S_CGFR_CKPOL;
break;
case SND_SOC_DAIFMT_NB_IF:
cgfr |= I2S_CGFR_WSINV;
break;
case SND_SOC_DAIFMT_IB_IF:
cgfr |= I2S_CGFR_CKPOL;
cgfr |= I2S_CGFR_WSINV;
break;
default:
dev_err(cpu_dai->dev, "Unsupported strobing %#x\n",
fmt & SND_SOC_DAIFMT_INV_MASK);
return -EINVAL;
}
/* DAI clock master masks */
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BC_FC:
i2s->ms_flg = I2S_MS_SLAVE;
break;
case SND_SOC_DAIFMT_BP_FP:
i2s->ms_flg = I2S_MS_MASTER;
break;
default:
dev_err(cpu_dai->dev, "Unsupported mode %#x\n",
fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK);
return -EINVAL;
}
i2s->fmt = fmt;
return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
cgfr_mask, cgfr);
}
static int stm32_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
int clk_id, unsigned int freq, int dir)
{
struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
int ret = 0;
dev_dbg(cpu_dai->dev, "I2S MCLK frequency is %uHz. mode: %s, dir: %s\n",
freq, STM32_I2S_IS_MASTER(i2s) ? "master" : "slave",
dir ? "output" : "input");
/* MCLK generation is available only in master mode */
if (dir == SND_SOC_CLOCK_OUT && STM32_I2S_IS_MASTER(i2s)) {
if (!i2s->i2smclk) {
dev_dbg(cpu_dai->dev, "No MCLK registered\n");
return 0;
}
/* Assume shutdown if requested frequency is 0Hz */
if (!freq) {
/* Release mclk rate only if rate was actually set */
if (i2s->mclk_rate) {
clk_rate_exclusive_put(i2s->i2smclk);
i2s->mclk_rate = 0;
}
return regmap_update_bits(i2s->regmap,
STM32_I2S_CGFR_REG,
I2S_CGFR_MCKOE, 0);
}
/* If master clock is used, set parent clock now */
ret = stm32_i2s_set_parent_clock(i2s, freq);
if (ret)
return ret;
ret = clk_set_rate_exclusive(i2s->i2smclk, freq);
if (ret) {
dev_err(cpu_dai->dev, "Could not set mclk rate\n");
return ret;
}
ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
I2S_CGFR_MCKOE, I2S_CGFR_MCKOE);
if (!ret)
i2s->mclk_rate = freq;
}
return ret;
}
static int stm32_i2s_configure_clock(struct snd_soc_dai *cpu_dai,
struct snd_pcm_hw_params *params)
{
struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
unsigned long i2s_clock_rate;
unsigned int nb_bits, frame_len;
unsigned int rate = params_rate(params);
u32 cgfr;
int ret;
if (!(rate % 11025))
clk_set_parent(i2s->i2sclk, i2s->x11kclk);
else
clk_set_parent(i2s->i2sclk, i2s->x8kclk);
i2s_clock_rate = clk_get_rate(i2s->i2sclk);
/*
* mckl = mclk_ratio x ws
* i2s mode : mclk_ratio = 256
* dsp mode : mclk_ratio = 128
*
* mclk on
* i2s mode : div = i2s_clk / (mclk_ratio * ws)
* dsp mode : div = i2s_clk / (mclk_ratio * ws)
* mclk off
* i2s mode : div = i2s_clk / (nb_bits x ws)
* dsp mode : div = i2s_clk / (nb_bits x ws)
*/
if (i2s->mclk_rate) {
ret = stm32_i2s_calc_clk_div(i2s, i2s_clock_rate,
i2s->mclk_rate);
if (ret)
return ret;
} else {
frame_len = 32;
if ((i2s->fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
SND_SOC_DAIFMT_DSP_A)
frame_len = 16;
/* master clock not enabled */
ret = regmap_read(i2s->regmap, STM32_I2S_CGFR_REG, &cgfr);
if (ret < 0)
return ret;
nb_bits = frame_len * (FIELD_GET(I2S_CGFR_CHLEN, cgfr) + 1);
ret = stm32_i2s_calc_clk_div(i2s, i2s_clock_rate,
(nb_bits * rate));
if (ret)
return ret;
}
ret = stm32_i2s_set_clk_div(i2s);
if (ret < 0)
return ret;
/* Set bitclock and frameclock to their inactive state */
return regmap_update_bits(i2s->regmap, STM32_I2S_CFG2_REG,
I2S_CFG2_AFCNTR, I2S_CFG2_AFCNTR);
}
static int stm32_i2s_configure(struct snd_soc_dai *cpu_dai,
struct snd_pcm_hw_params *params,
struct snd_pcm_substream *substream)
{
struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
int format = params_width(params);
u32 cfgr, cfgr_mask, cfg1;
unsigned int fthlv;
int ret;
switch (format) {
case 16:
cfgr = I2S_CGFR_DATLEN_SET(I2S_I2SMOD_DATLEN_16);
cfgr_mask = I2S_CGFR_DATLEN_MASK | I2S_CGFR_CHLEN;
break;
case 32:
cfgr = I2S_CGFR_DATLEN_SET(I2S_I2SMOD_DATLEN_32) |
I2S_CGFR_CHLEN;
cfgr_mask = I2S_CGFR_DATLEN_MASK | I2S_CGFR_CHLEN;
break;
default:
dev_err(cpu_dai->dev, "Unexpected format %d", format);
return -EINVAL;
}
if (STM32_I2S_IS_SLAVE(i2s)) {
cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_FD_SLAVE);
/* As data length is either 16 or 32 bits, fixch always set */
cfgr |= I2S_CGFR_FIXCH;
cfgr_mask |= I2S_CGFR_FIXCH;
} else {
cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_FD_MASTER);
}
cfgr_mask |= I2S_CGFR_I2SCFG_MASK;
ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
cfgr_mask, cfgr);
if (ret < 0)
return ret;
fthlv = STM32_I2S_FIFO_SIZE * I2S_FIFO_TH_ONE_QUARTER / 4;
cfg1 = I2S_CFG1_FTHVL_SET(fthlv - 1);
return regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
I2S_CFG1_FTHVL_MASK, cfg1);
}
static int stm32_i2s_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *cpu_dai)
{
struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
unsigned long flags;
int ret;
spin_lock_irqsave(&i2s->irq_lock, flags);
i2s->substream = substream;
spin_unlock_irqrestore(&i2s->irq_lock, flags);
if ((i2s->fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_DSP_A)
snd_pcm_hw_constraint_single(substream->runtime,
SNDRV_PCM_HW_PARAM_CHANNELS, 2);
ret = clk_prepare_enable(i2s->i2sclk);
if (ret < 0) {
dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret);
return ret;
}
return regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
I2S_IFCR_MASK, I2S_IFCR_MASK);
}
static int stm32_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *cpu_dai)
{
struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
int ret;
ret = stm32_i2s_configure(cpu_dai, params, substream);
if (ret < 0) {
dev_err(cpu_dai->dev, "Configuration returned error %d\n", ret);
return ret;
}
if (STM32_I2S_IS_MASTER(i2s))
ret = stm32_i2s_configure_clock(cpu_dai, params);
return ret;
}
static int stm32_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *cpu_dai)
{
struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
bool playback_flg = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
u32 cfg1_mask, ier;
int ret;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
/* Enable i2s */
dev_dbg(cpu_dai->dev, "start I2S %s\n",
playback_flg ? "playback" : "capture");
cfg1_mask = I2S_CFG1_RXDMAEN | I2S_CFG1_TXDMAEN;
regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
cfg1_mask, cfg1_mask);
ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG,
I2S_CR1_SPE, I2S_CR1_SPE);
if (ret < 0) {
dev_err(cpu_dai->dev, "Error %d enabling I2S\n", ret);
return ret;
}
ret = regmap_write_bits(i2s->regmap, STM32_I2S_CR1_REG,
I2S_CR1_CSTART, I2S_CR1_CSTART);
if (ret < 0) {
dev_err(cpu_dai->dev, "Error %d starting I2S\n", ret);
return ret;
}
regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
I2S_IFCR_MASK, I2S_IFCR_MASK);
spin_lock(&i2s->lock_fd);
i2s->refcount++;
if (playback_flg) {
ier = I2S_IER_UDRIE;
} else {
ier = I2S_IER_OVRIE;
if (STM32_I2S_IS_MASTER(i2s) && i2s->refcount == 1)
/* dummy write to gate bus clocks */
regmap_write(i2s->regmap,
STM32_I2S_TXDR_REG, 0);
}
spin_unlock(&i2s->lock_fd);
if (STM32_I2S_IS_SLAVE(i2s))
ier |= I2S_IER_TIFREIE;
regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG, ier, ier);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
dev_dbg(cpu_dai->dev, "stop I2S %s\n",
playback_flg ? "playback" : "capture");
if (playback_flg)
regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG,
I2S_IER_UDRIE,
(unsigned int)~I2S_IER_UDRIE);
else
regmap_update_bits(i2s->regmap, STM32_I2S_IER_REG,
I2S_IER_OVRIE,
(unsigned int)~I2S_IER_OVRIE);
spin_lock(&i2s->lock_fd);
i2s->refcount--;
if (i2s->refcount) {
spin_unlock(&i2s->lock_fd);
break;
}
ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG,
I2S_CR1_SPE, 0);
if (ret < 0) {
dev_err(cpu_dai->dev, "Error %d disabling I2S\n", ret);
spin_unlock(&i2s->lock_fd);
return ret;
}
spin_unlock(&i2s->lock_fd);
cfg1_mask = I2S_CFG1_RXDMAEN | I2S_CFG1_TXDMAEN;
regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
cfg1_mask, 0);
break;
default:
return -EINVAL;
}
return 0;
}
static void stm32_i2s_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *cpu_dai)
{
struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
unsigned long flags;
clk_disable_unprepare(i2s->i2sclk);
spin_lock_irqsave(&i2s->irq_lock, flags);
i2s->substream = NULL;
spin_unlock_irqrestore(&i2s->irq_lock, flags);
}
static int stm32_i2s_dai_probe(struct snd_soc_dai *cpu_dai)
{
struct stm32_i2s_data *i2s = dev_get_drvdata(cpu_dai->dev);
struct snd_dmaengine_dai_dma_data *dma_data_tx = &i2s->dma_data_tx;
struct snd_dmaengine_dai_dma_data *dma_data_rx = &i2s->dma_data_rx;
/* Buswidth will be set by framework */
dma_data_tx->addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
dma_data_tx->addr = (dma_addr_t)(i2s->phys_addr) + STM32_I2S_TXDR_REG;
dma_data_tx->maxburst = 1;
dma_data_rx->addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
dma_data_rx->addr = (dma_addr_t)(i2s->phys_addr) + STM32_I2S_RXDR_REG;
dma_data_rx->maxburst = 1;
snd_soc_dai_init_dma_data(cpu_dai, dma_data_tx, dma_data_rx);
return 0;
}
static const struct regmap_config stm32_h7_i2s_regmap_conf = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = STM32_I2S_SIDR_REG,
.readable_reg = stm32_i2s_readable_reg,
.volatile_reg = stm32_i2s_volatile_reg,
.writeable_reg = stm32_i2s_writeable_reg,
.num_reg_defaults_raw = STM32_I2S_SIDR_REG / sizeof(u32) + 1,
.fast_io = true,
.cache_type = REGCACHE_FLAT,
};
static const struct snd_soc_dai_ops stm32_i2s_pcm_dai_ops = {
.probe = stm32_i2s_dai_probe,
.set_sysclk = stm32_i2s_set_sysclk,
.set_fmt = stm32_i2s_set_dai_fmt,
.startup = stm32_i2s_startup,
.hw_params = stm32_i2s_hw_params,
.trigger = stm32_i2s_trigger,
.shutdown = stm32_i2s_shutdown,
};
static const struct snd_pcm_hardware stm32_i2s_pcm_hw = {
.info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP,
.buffer_bytes_max = 8 * PAGE_SIZE,
.period_bytes_min = 1024,
.period_bytes_max = 4 * PAGE_SIZE,
.periods_min = 2,
.periods_max = 8,
};
static const struct snd_dmaengine_pcm_config stm32_i2s_pcm_config = {
.pcm_hardware = &stm32_i2s_pcm_hw,
.prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
.prealloc_buffer_size = PAGE_SIZE * 8,
};
static const struct snd_soc_component_driver stm32_i2s_component = {
.name = "stm32-i2s",
.legacy_dai_naming = 1,
};
static void stm32_i2s_dai_init(struct snd_soc_pcm_stream *stream,
char *stream_name)
{
stream->stream_name = stream_name;
stream->channels_min = 1;
stream->channels_max = 2;
stream->rates = SNDRV_PCM_RATE_8000_192000;
stream->formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S32_LE;
}
static int stm32_i2s_dais_init(struct platform_device *pdev,
struct stm32_i2s_data *i2s)
{
struct snd_soc_dai_driver *dai_ptr;
dai_ptr = devm_kzalloc(&pdev->dev, sizeof(struct snd_soc_dai_driver),
GFP_KERNEL);
if (!dai_ptr)
return -ENOMEM;
dai_ptr->ops = &stm32_i2s_pcm_dai_ops;
dai_ptr->id = 1;
stm32_i2s_dai_init(&dai_ptr->playback, "playback");
stm32_i2s_dai_init(&dai_ptr->capture, "capture");
i2s->dai_drv = dai_ptr;
return 0;
}
static const struct of_device_id stm32_i2s_ids[] = {
{
.compatible = "st,stm32h7-i2s",
.data = &stm32_h7_i2s_regmap_conf
},
{},
};
static int stm32_i2s_parse_dt(struct platform_device *pdev,
struct stm32_i2s_data *i2s)
{
struct device_node *np = pdev->dev.of_node;
const struct of_device_id *of_id;
struct reset_control *rst;
struct resource *res;
int irq, ret;
if (!np)
return -ENODEV;
of_id = of_match_device(stm32_i2s_ids, &pdev->dev);
if (of_id)
i2s->regmap_conf = (const struct regmap_config *)of_id->data;
else
return -EINVAL;
i2s->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(i2s->base))
return PTR_ERR(i2s->base);
i2s->phys_addr = res->start;
/* Get clocks */
i2s->pclk = devm_clk_get(&pdev->dev, "pclk");
if (IS_ERR(i2s->pclk))
return dev_err_probe(&pdev->dev, PTR_ERR(i2s->pclk),
"Could not get pclk\n");
i2s->i2sclk = devm_clk_get(&pdev->dev, "i2sclk");
if (IS_ERR(i2s->i2sclk))
return dev_err_probe(&pdev->dev, PTR_ERR(i2s->i2sclk),
"Could not get i2sclk\n");
i2s->x8kclk = devm_clk_get(&pdev->dev, "x8k");
if (IS_ERR(i2s->x8kclk))
return dev_err_probe(&pdev->dev, PTR_ERR(i2s->x8kclk),
"Could not get x8k parent clock\n");
i2s->x11kclk = devm_clk_get(&pdev->dev, "x11k");
if (IS_ERR(i2s->x11kclk))
return dev_err_probe(&pdev->dev, PTR_ERR(i2s->x11kclk),
"Could not get x11k parent clock\n");
/* Register mclk provider if requested */
if (of_property_present(np, "#clock-cells")) {
ret = stm32_i2s_add_mclk_provider(i2s);
if (ret < 0)
return ret;
}
/* Get irqs */
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
ret = devm_request_irq(&pdev->dev, irq, stm32_i2s_isr, 0,
dev_name(&pdev->dev), i2s);
if (ret) {
dev_err(&pdev->dev, "irq request returned %d\n", ret);
return ret;
}
/* Reset */
rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
if (IS_ERR(rst))
return dev_err_probe(&pdev->dev, PTR_ERR(rst),
"Reset controller error\n");
reset_control_assert(rst);
udelay(2);
reset_control_deassert(rst);
return 0;
}
static void stm32_i2s_remove(struct platform_device *pdev)
{
snd_dmaengine_pcm_unregister(&pdev->dev);
snd_soc_unregister_component(&pdev->dev);
pm_runtime_disable(&pdev->dev);
}
static int stm32_i2s_probe(struct platform_device *pdev)
{
struct stm32_i2s_data *i2s;
u32 val;
int ret;
i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
if (!i2s)
return -ENOMEM;
i2s->pdev = pdev;
i2s->ms_flg = I2S_MS_NOT_SET;
spin_lock_init(&i2s->lock_fd);
spin_lock_init(&i2s->irq_lock);
platform_set_drvdata(pdev, i2s);
ret = stm32_i2s_parse_dt(pdev, i2s);
if (ret)
return ret;
ret = stm32_i2s_dais_init(pdev, i2s);
if (ret)
return ret;
i2s->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "pclk",
i2s->base, i2s->regmap_conf);
if (IS_ERR(i2s->regmap))
return dev_err_probe(&pdev->dev, PTR_ERR(i2s->regmap),
"Regmap init error\n");
ret = snd_dmaengine_pcm_register(&pdev->dev, &stm32_i2s_pcm_config, 0);
if (ret)
return dev_err_probe(&pdev->dev, ret, "PCM DMA register error\n");
ret = snd_soc_register_component(&pdev->dev, &stm32_i2s_component,
i2s->dai_drv, 1);
if (ret) {
snd_dmaengine_pcm_unregister(&pdev->dev);
return ret;
}
/* Set SPI/I2S in i2s mode */
ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
I2S_CGFR_I2SMOD, I2S_CGFR_I2SMOD);
if (ret)
goto error;
ret = regmap_read(i2s->regmap, STM32_I2S_IPIDR_REG, &val);
if (ret)
goto error;
if (val == I2S_IPIDR_NUMBER) {
ret = regmap_read(i2s->regmap, STM32_I2S_HWCFGR_REG, &val);
if (ret)
goto error;
if (!FIELD_GET(I2S_HWCFGR_I2S_SUPPORT_MASK, val)) {
dev_err(&pdev->dev,
"Device does not support i2s mode\n");
ret = -EPERM;
goto error;
}
ret = regmap_read(i2s->regmap, STM32_I2S_VERR_REG, &val);
if (ret)
goto error;
dev_dbg(&pdev->dev, "I2S version: %lu.%lu registered\n",
FIELD_GET(I2S_VERR_MAJ_MASK, val),
FIELD_GET(I2S_VERR_MIN_MASK, val));
}
pm_runtime_enable(&pdev->dev);
return ret;
error:
stm32_i2s_remove(pdev);
return ret;
}
MODULE_DEVICE_TABLE(of, stm32_i2s_ids);
#ifdef CONFIG_PM_SLEEP
static int stm32_i2s_suspend(struct device *dev)
{
struct stm32_i2s_data *i2s = dev_get_drvdata(dev);
regcache_cache_only(i2s->regmap, true);
regcache_mark_dirty(i2s->regmap);
return 0;
}
static int stm32_i2s_resume(struct device *dev)
{
struct stm32_i2s_data *i2s = dev_get_drvdata(dev);
regcache_cache_only(i2s->regmap, false);
return regcache_sync(i2s->regmap);
}
#endif /* CONFIG_PM_SLEEP */
static const struct dev_pm_ops stm32_i2s_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(stm32_i2s_suspend, stm32_i2s_resume)
};
static struct platform_driver stm32_i2s_driver = {
.driver = {
.name = "st,stm32-i2s",
.of_match_table = stm32_i2s_ids,
.pm = &stm32_i2s_pm_ops,
},
.probe = stm32_i2s_probe,
.remove_new = stm32_i2s_remove,
};
module_platform_driver(stm32_i2s_driver);
MODULE_DESCRIPTION("STM32 Soc i2s Interface");
MODULE_AUTHOR("Olivier Moysan, <[email protected]>");
MODULE_ALIAS("platform:stm32-i2s");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/stm/stm32_i2s.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* STM32 ALSA SoC Digital Audio Interface (SAI) driver.
*
* Copyright (C) 2016, STMicroelectronics - All Rights Reserved
* Author(s): Olivier Moysan <[email protected]> for STMicroelectronics.
*/
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/pinctrl/consumer.h>
#include <linux/reset.h>
#include <sound/dmaengine_pcm.h>
#include <sound/core.h>
#include "stm32_sai.h"
static const struct stm32_sai_conf stm32_sai_conf_f4 = {
.version = STM_SAI_STM32F4,
.fifo_size = 8,
.has_spdif_pdm = false,
};
/*
* Default settings for stm32 H7 socs and next.
* These default settings will be overridden if the soc provides
* support of hardware configuration registers.
*/
static const struct stm32_sai_conf stm32_sai_conf_h7 = {
.version = STM_SAI_STM32H7,
.fifo_size = 8,
.has_spdif_pdm = true,
};
static const struct of_device_id stm32_sai_ids[] = {
{ .compatible = "st,stm32f4-sai", .data = (void *)&stm32_sai_conf_f4 },
{ .compatible = "st,stm32h7-sai", .data = (void *)&stm32_sai_conf_h7 },
{}
};
static int stm32_sai_pclk_disable(struct device *dev)
{
struct stm32_sai_data *sai = dev_get_drvdata(dev);
clk_disable_unprepare(sai->pclk);
return 0;
}
static int stm32_sai_pclk_enable(struct device *dev)
{
struct stm32_sai_data *sai = dev_get_drvdata(dev);
int ret;
ret = clk_prepare_enable(sai->pclk);
if (ret) {
dev_err(&sai->pdev->dev, "failed to enable clock: %d\n", ret);
return ret;
}
return 0;
}
static int stm32_sai_sync_conf_client(struct stm32_sai_data *sai, int synci)
{
int ret;
/* Enable peripheral clock to allow GCR register access */
ret = stm32_sai_pclk_enable(&sai->pdev->dev);
if (ret)
return ret;
writel_relaxed(FIELD_PREP(SAI_GCR_SYNCIN_MASK, (synci - 1)), sai->base);
stm32_sai_pclk_disable(&sai->pdev->dev);
return 0;
}
static int stm32_sai_sync_conf_provider(struct stm32_sai_data *sai, int synco)
{
u32 prev_synco;
int ret;
/* Enable peripheral clock to allow GCR register access */
ret = stm32_sai_pclk_enable(&sai->pdev->dev);
if (ret)
return ret;
dev_dbg(&sai->pdev->dev, "Set %pOFn%s as synchro provider\n",
sai->pdev->dev.of_node,
synco == STM_SAI_SYNC_OUT_A ? "A" : "B");
prev_synco = FIELD_GET(SAI_GCR_SYNCOUT_MASK, readl_relaxed(sai->base));
if (prev_synco != STM_SAI_SYNC_OUT_NONE && synco != prev_synco) {
dev_err(&sai->pdev->dev, "%pOFn%s already set as sync provider\n",
sai->pdev->dev.of_node,
prev_synco == STM_SAI_SYNC_OUT_A ? "A" : "B");
stm32_sai_pclk_disable(&sai->pdev->dev);
return -EINVAL;
}
writel_relaxed(FIELD_PREP(SAI_GCR_SYNCOUT_MASK, synco), sai->base);
stm32_sai_pclk_disable(&sai->pdev->dev);
return 0;
}
static int stm32_sai_set_sync(struct stm32_sai_data *sai_client,
struct device_node *np_provider,
int synco, int synci)
{
struct platform_device *pdev = of_find_device_by_node(np_provider);
struct stm32_sai_data *sai_provider;
int ret;
if (!pdev) {
dev_err(&sai_client->pdev->dev,
"Device not found for node %pOFn\n", np_provider);
of_node_put(np_provider);
return -ENODEV;
}
sai_provider = platform_get_drvdata(pdev);
if (!sai_provider) {
dev_err(&sai_client->pdev->dev,
"SAI sync provider data not found\n");
ret = -EINVAL;
goto error;
}
/* Configure sync client */
ret = stm32_sai_sync_conf_client(sai_client, synci);
if (ret < 0)
goto error;
/* Configure sync provider */
ret = stm32_sai_sync_conf_provider(sai_provider, synco);
error:
put_device(&pdev->dev);
of_node_put(np_provider);
return ret;
}
static int stm32_sai_probe(struct platform_device *pdev)
{
struct stm32_sai_data *sai;
struct reset_control *rst;
const struct of_device_id *of_id;
u32 val;
int ret;
sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
if (!sai)
return -ENOMEM;
sai->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(sai->base))
return PTR_ERR(sai->base);
of_id = of_match_device(stm32_sai_ids, &pdev->dev);
if (of_id)
memcpy(&sai->conf, (const struct stm32_sai_conf *)of_id->data,
sizeof(struct stm32_sai_conf));
else
return -EINVAL;
if (!STM_SAI_IS_F4(sai)) {
sai->pclk = devm_clk_get(&pdev->dev, "pclk");
if (IS_ERR(sai->pclk))
return dev_err_probe(&pdev->dev, PTR_ERR(sai->pclk),
"missing bus clock pclk\n");
}
sai->clk_x8k = devm_clk_get(&pdev->dev, "x8k");
if (IS_ERR(sai->clk_x8k))
return dev_err_probe(&pdev->dev, PTR_ERR(sai->clk_x8k),
"missing x8k parent clock\n");
sai->clk_x11k = devm_clk_get(&pdev->dev, "x11k");
if (IS_ERR(sai->clk_x11k))
return dev_err_probe(&pdev->dev, PTR_ERR(sai->clk_x11k),
"missing x11k parent clock\n");
/* init irqs */
sai->irq = platform_get_irq(pdev, 0);
if (sai->irq < 0)
return sai->irq;
/* reset */
rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
if (IS_ERR(rst))
return dev_err_probe(&pdev->dev, PTR_ERR(rst),
"Reset controller error\n");
reset_control_assert(rst);
udelay(2);
reset_control_deassert(rst);
/* Enable peripheral clock to allow register access */
ret = clk_prepare_enable(sai->pclk);
if (ret) {
dev_err(&pdev->dev, "failed to enable clock: %d\n", ret);
return ret;
}
val = FIELD_GET(SAI_IDR_ID_MASK,
readl_relaxed(sai->base + STM_SAI_IDR));
if (val == SAI_IPIDR_NUMBER) {
val = readl_relaxed(sai->base + STM_SAI_HWCFGR);
sai->conf.fifo_size = FIELD_GET(SAI_HWCFGR_FIFO_SIZE, val);
sai->conf.has_spdif_pdm = !!FIELD_GET(SAI_HWCFGR_SPDIF_PDM,
val);
val = readl_relaxed(sai->base + STM_SAI_VERR);
sai->conf.version = val;
dev_dbg(&pdev->dev, "SAI version: %lu.%lu registered\n",
FIELD_GET(SAI_VERR_MAJ_MASK, val),
FIELD_GET(SAI_VERR_MIN_MASK, val));
}
clk_disable_unprepare(sai->pclk);
sai->pdev = pdev;
sai->set_sync = &stm32_sai_set_sync;
platform_set_drvdata(pdev, sai);
return devm_of_platform_populate(&pdev->dev);
}
#ifdef CONFIG_PM_SLEEP
/*
* When pins are shared by two sai sub instances, pins have to be defined
* in sai parent node. In this case, pins state is not managed by alsa fw.
* These pins are managed in suspend/resume callbacks.
*/
static int stm32_sai_suspend(struct device *dev)
{
struct stm32_sai_data *sai = dev_get_drvdata(dev);
int ret;
ret = stm32_sai_pclk_enable(dev);
if (ret)
return ret;
sai->gcr = readl_relaxed(sai->base);
stm32_sai_pclk_disable(dev);
return pinctrl_pm_select_sleep_state(dev);
}
static int stm32_sai_resume(struct device *dev)
{
struct stm32_sai_data *sai = dev_get_drvdata(dev);
int ret;
ret = stm32_sai_pclk_enable(dev);
if (ret)
return ret;
writel_relaxed(sai->gcr, sai->base);
stm32_sai_pclk_disable(dev);
return pinctrl_pm_select_default_state(dev);
}
#endif /* CONFIG_PM_SLEEP */
static const struct dev_pm_ops stm32_sai_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(stm32_sai_suspend, stm32_sai_resume)
};
MODULE_DEVICE_TABLE(of, stm32_sai_ids);
static struct platform_driver stm32_sai_driver = {
.driver = {
.name = "st,stm32-sai",
.of_match_table = stm32_sai_ids,
.pm = &stm32_sai_pm_ops,
},
.probe = stm32_sai_probe,
};
module_platform_driver(stm32_sai_driver);
MODULE_DESCRIPTION("STM32 Soc SAI Interface");
MODULE_AUTHOR("Olivier Moysan <[email protected]>");
MODULE_ALIAS("platform:st,stm32-sai");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/stm/stm32_sai.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* STM32 ALSA SoC Digital Audio Interface (SPDIF-rx) driver.
*
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
* Author(s): Olivier Moysan <[email protected]> for STMicroelectronics.
*/
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <sound/dmaengine_pcm.h>
#include <sound/pcm_params.h>
/* SPDIF-rx Register Map */
#define STM32_SPDIFRX_CR 0x00
#define STM32_SPDIFRX_IMR 0x04
#define STM32_SPDIFRX_SR 0x08
#define STM32_SPDIFRX_IFCR 0x0C
#define STM32_SPDIFRX_DR 0x10
#define STM32_SPDIFRX_CSR 0x14
#define STM32_SPDIFRX_DIR 0x18
#define STM32_SPDIFRX_VERR 0x3F4
#define STM32_SPDIFRX_IDR 0x3F8
#define STM32_SPDIFRX_SIDR 0x3FC
/* Bit definition for SPDIF_CR register */
#define SPDIFRX_CR_SPDIFEN_SHIFT 0
#define SPDIFRX_CR_SPDIFEN_MASK GENMASK(1, SPDIFRX_CR_SPDIFEN_SHIFT)
#define SPDIFRX_CR_SPDIFENSET(x) ((x) << SPDIFRX_CR_SPDIFEN_SHIFT)
#define SPDIFRX_CR_RXDMAEN BIT(2)
#define SPDIFRX_CR_RXSTEO BIT(3)
#define SPDIFRX_CR_DRFMT_SHIFT 4
#define SPDIFRX_CR_DRFMT_MASK GENMASK(5, SPDIFRX_CR_DRFMT_SHIFT)
#define SPDIFRX_CR_DRFMTSET(x) ((x) << SPDIFRX_CR_DRFMT_SHIFT)
#define SPDIFRX_CR_PMSK BIT(6)
#define SPDIFRX_CR_VMSK BIT(7)
#define SPDIFRX_CR_CUMSK BIT(8)
#define SPDIFRX_CR_PTMSK BIT(9)
#define SPDIFRX_CR_CBDMAEN BIT(10)
#define SPDIFRX_CR_CHSEL_SHIFT 11
#define SPDIFRX_CR_CHSEL BIT(SPDIFRX_CR_CHSEL_SHIFT)
#define SPDIFRX_CR_NBTR_SHIFT 12
#define SPDIFRX_CR_NBTR_MASK GENMASK(13, SPDIFRX_CR_NBTR_SHIFT)
#define SPDIFRX_CR_NBTRSET(x) ((x) << SPDIFRX_CR_NBTR_SHIFT)
#define SPDIFRX_CR_WFA BIT(14)
#define SPDIFRX_CR_INSEL_SHIFT 16
#define SPDIFRX_CR_INSEL_MASK GENMASK(18, PDIFRX_CR_INSEL_SHIFT)
#define SPDIFRX_CR_INSELSET(x) ((x) << SPDIFRX_CR_INSEL_SHIFT)
#define SPDIFRX_CR_CKSEN_SHIFT 20
#define SPDIFRX_CR_CKSEN BIT(20)
#define SPDIFRX_CR_CKSBKPEN BIT(21)
/* Bit definition for SPDIFRX_IMR register */
#define SPDIFRX_IMR_RXNEI BIT(0)
#define SPDIFRX_IMR_CSRNEIE BIT(1)
#define SPDIFRX_IMR_PERRIE BIT(2)
#define SPDIFRX_IMR_OVRIE BIT(3)
#define SPDIFRX_IMR_SBLKIE BIT(4)
#define SPDIFRX_IMR_SYNCDIE BIT(5)
#define SPDIFRX_IMR_IFEIE BIT(6)
#define SPDIFRX_XIMR_MASK GENMASK(6, 0)
/* Bit definition for SPDIFRX_SR register */
#define SPDIFRX_SR_RXNE BIT(0)
#define SPDIFRX_SR_CSRNE BIT(1)
#define SPDIFRX_SR_PERR BIT(2)
#define SPDIFRX_SR_OVR BIT(3)
#define SPDIFRX_SR_SBD BIT(4)
#define SPDIFRX_SR_SYNCD BIT(5)
#define SPDIFRX_SR_FERR BIT(6)
#define SPDIFRX_SR_SERR BIT(7)
#define SPDIFRX_SR_TERR BIT(8)
#define SPDIFRX_SR_WIDTH5_SHIFT 16
#define SPDIFRX_SR_WIDTH5_MASK GENMASK(30, PDIFRX_SR_WIDTH5_SHIFT)
#define SPDIFRX_SR_WIDTH5SET(x) ((x) << SPDIFRX_SR_WIDTH5_SHIFT)
/* Bit definition for SPDIFRX_IFCR register */
#define SPDIFRX_IFCR_PERRCF BIT(2)
#define SPDIFRX_IFCR_OVRCF BIT(3)
#define SPDIFRX_IFCR_SBDCF BIT(4)
#define SPDIFRX_IFCR_SYNCDCF BIT(5)
#define SPDIFRX_XIFCR_MASK GENMASK(5, 2)
/* Bit definition for SPDIFRX_DR register (DRFMT = 0b00) */
#define SPDIFRX_DR0_DR_SHIFT 0
#define SPDIFRX_DR0_DR_MASK GENMASK(23, SPDIFRX_DR0_DR_SHIFT)
#define SPDIFRX_DR0_DRSET(x) ((x) << SPDIFRX_DR0_DR_SHIFT)
#define SPDIFRX_DR0_PE BIT(24)
#define SPDIFRX_DR0_V BIT(25)
#define SPDIFRX_DR0_U BIT(26)
#define SPDIFRX_DR0_C BIT(27)
#define SPDIFRX_DR0_PT_SHIFT 28
#define SPDIFRX_DR0_PT_MASK GENMASK(29, SPDIFRX_DR0_PT_SHIFT)
#define SPDIFRX_DR0_PTSET(x) ((x) << SPDIFRX_DR0_PT_SHIFT)
/* Bit definition for SPDIFRX_DR register (DRFMT = 0b01) */
#define SPDIFRX_DR1_PE BIT(0)
#define SPDIFRX_DR1_V BIT(1)
#define SPDIFRX_DR1_U BIT(2)
#define SPDIFRX_DR1_C BIT(3)
#define SPDIFRX_DR1_PT_SHIFT 4
#define SPDIFRX_DR1_PT_MASK GENMASK(5, SPDIFRX_DR1_PT_SHIFT)
#define SPDIFRX_DR1_PTSET(x) ((x) << SPDIFRX_DR1_PT_SHIFT)
#define SPDIFRX_DR1_DR_SHIFT 8
#define SPDIFRX_DR1_DR_MASK GENMASK(31, SPDIFRX_DR1_DR_SHIFT)
#define SPDIFRX_DR1_DRSET(x) ((x) << SPDIFRX_DR1_DR_SHIFT)
/* Bit definition for SPDIFRX_DR register (DRFMT = 0b10) */
#define SPDIFRX_DR1_DRNL1_SHIFT 0
#define SPDIFRX_DR1_DRNL1_MASK GENMASK(15, SPDIFRX_DR1_DRNL1_SHIFT)
#define SPDIFRX_DR1_DRNL1SET(x) ((x) << SPDIFRX_DR1_DRNL1_SHIFT)
#define SPDIFRX_DR1_DRNL2_SHIFT 16
#define SPDIFRX_DR1_DRNL2_MASK GENMASK(31, SPDIFRX_DR1_DRNL2_SHIFT)
#define SPDIFRX_DR1_DRNL2SET(x) ((x) << SPDIFRX_DR1_DRNL2_SHIFT)
/* Bit definition for SPDIFRX_CSR register */
#define SPDIFRX_CSR_USR_SHIFT 0
#define SPDIFRX_CSR_USR_MASK GENMASK(15, SPDIFRX_CSR_USR_SHIFT)
#define SPDIFRX_CSR_USRGET(x) (((x) & SPDIFRX_CSR_USR_MASK)\
>> SPDIFRX_CSR_USR_SHIFT)
#define SPDIFRX_CSR_CS_SHIFT 16
#define SPDIFRX_CSR_CS_MASK GENMASK(23, SPDIFRX_CSR_CS_SHIFT)
#define SPDIFRX_CSR_CSGET(x) (((x) & SPDIFRX_CSR_CS_MASK)\
>> SPDIFRX_CSR_CS_SHIFT)
#define SPDIFRX_CSR_SOB BIT(24)
/* Bit definition for SPDIFRX_DIR register */
#define SPDIFRX_DIR_THI_SHIFT 0
#define SPDIFRX_DIR_THI_MASK GENMASK(12, SPDIFRX_DIR_THI_SHIFT)
#define SPDIFRX_DIR_THI_SET(x) ((x) << SPDIFRX_DIR_THI_SHIFT)
#define SPDIFRX_DIR_TLO_SHIFT 16
#define SPDIFRX_DIR_TLO_MASK GENMASK(28, SPDIFRX_DIR_TLO_SHIFT)
#define SPDIFRX_DIR_TLO_SET(x) ((x) << SPDIFRX_DIR_TLO_SHIFT)
#define SPDIFRX_SPDIFEN_DISABLE 0x0
#define SPDIFRX_SPDIFEN_SYNC 0x1
#define SPDIFRX_SPDIFEN_ENABLE 0x3
/* Bit definition for SPDIFRX_VERR register */
#define SPDIFRX_VERR_MIN_MASK GENMASK(3, 0)
#define SPDIFRX_VERR_MAJ_MASK GENMASK(7, 4)
/* Bit definition for SPDIFRX_IDR register */
#define SPDIFRX_IDR_ID_MASK GENMASK(31, 0)
/* Bit definition for SPDIFRX_SIDR register */
#define SPDIFRX_SIDR_SID_MASK GENMASK(31, 0)
#define SPDIFRX_IPIDR_NUMBER 0x00130041
#define SPDIFRX_IN1 0x1
#define SPDIFRX_IN2 0x2
#define SPDIFRX_IN3 0x3
#define SPDIFRX_IN4 0x4
#define SPDIFRX_IN5 0x5
#define SPDIFRX_IN6 0x6
#define SPDIFRX_IN7 0x7
#define SPDIFRX_IN8 0x8
#define SPDIFRX_NBTR_NONE 0x0
#define SPDIFRX_NBTR_3 0x1
#define SPDIFRX_NBTR_15 0x2
#define SPDIFRX_NBTR_63 0x3
#define SPDIFRX_DRFMT_RIGHT 0x0
#define SPDIFRX_DRFMT_LEFT 0x1
#define SPDIFRX_DRFMT_PACKED 0x2
/* 192 CS bits in S/PDIF frame. i.e 24 CS bytes */
#define SPDIFRX_CS_BYTES_NB 24
#define SPDIFRX_UB_BYTES_NB 48
/*
* CSR register is retrieved as a 32 bits word
* It contains 1 channel status byte and 2 user data bytes
* 2 S/PDIF frames are acquired to get all CS/UB bits
*/
#define SPDIFRX_CSR_BUF_LENGTH (SPDIFRX_CS_BYTES_NB * 4 * 2)
/**
* struct stm32_spdifrx_data - private data of SPDIFRX
* @pdev: device data pointer
* @base: mmio register base virtual address
* @regmap: SPDIFRX register map pointer
* @regmap_conf: SPDIFRX register map configuration pointer
* @cs_completion: channel status retrieving completion
* @kclk: kernel clock feeding the SPDIFRX clock generator
* @dma_params: dma configuration data for rx channel
* @substream: PCM substream data pointer
* @dmab: dma buffer info pointer
* @ctrl_chan: dma channel for S/PDIF control bits
* @desc:dma async transaction descriptor
* @slave_config: dma slave channel runtime config pointer
* @phys_addr: SPDIFRX registers physical base address
* @lock: synchronization enabling lock
* @irq_lock: prevent race condition with IRQ on stream state
* @cs: channel status buffer
* @ub: user data buffer
* @irq: SPDIFRX interrupt line
* @refcount: keep count of opened DMA channels
*/
struct stm32_spdifrx_data {
struct platform_device *pdev;
void __iomem *base;
struct regmap *regmap;
const struct regmap_config *regmap_conf;
struct completion cs_completion;
struct clk *kclk;
struct snd_dmaengine_dai_dma_data dma_params;
struct snd_pcm_substream *substream;
struct snd_dma_buffer *dmab;
struct dma_chan *ctrl_chan;
struct dma_async_tx_descriptor *desc;
struct dma_slave_config slave_config;
dma_addr_t phys_addr;
spinlock_t lock; /* Sync enabling lock */
spinlock_t irq_lock; /* Prevent race condition on stream state */
unsigned char cs[SPDIFRX_CS_BYTES_NB];
unsigned char ub[SPDIFRX_UB_BYTES_NB];
int irq;
int refcount;
};
static void stm32_spdifrx_dma_complete(void *data)
{
struct stm32_spdifrx_data *spdifrx = (struct stm32_spdifrx_data *)data;
struct platform_device *pdev = spdifrx->pdev;
u32 *p_start = (u32 *)spdifrx->dmab->area;
u32 *p_end = p_start + (2 * SPDIFRX_CS_BYTES_NB) - 1;
u32 *ptr = p_start;
u16 *ub_ptr = (short *)spdifrx->ub;
int i = 0;
regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
SPDIFRX_CR_CBDMAEN,
(unsigned int)~SPDIFRX_CR_CBDMAEN);
if (!spdifrx->dmab->area)
return;
while (ptr <= p_end) {
if (*ptr & SPDIFRX_CSR_SOB)
break;
ptr++;
}
if (ptr > p_end) {
dev_err(&pdev->dev, "Start of S/PDIF block not found\n");
return;
}
while (i < SPDIFRX_CS_BYTES_NB) {
spdifrx->cs[i] = (unsigned char)SPDIFRX_CSR_CSGET(*ptr);
*ub_ptr++ = SPDIFRX_CSR_USRGET(*ptr++);
if (ptr > p_end) {
dev_err(&pdev->dev, "Failed to get channel status\n");
return;
}
i++;
}
complete(&spdifrx->cs_completion);
}
static int stm32_spdifrx_dma_ctrl_start(struct stm32_spdifrx_data *spdifrx)
{
dma_cookie_t cookie;
int err;
spdifrx->desc = dmaengine_prep_slave_single(spdifrx->ctrl_chan,
spdifrx->dmab->addr,
SPDIFRX_CSR_BUF_LENGTH,
DMA_DEV_TO_MEM,
DMA_CTRL_ACK);
if (!spdifrx->desc)
return -EINVAL;
spdifrx->desc->callback = stm32_spdifrx_dma_complete;
spdifrx->desc->callback_param = spdifrx;
cookie = dmaengine_submit(spdifrx->desc);
err = dma_submit_error(cookie);
if (err)
return -EINVAL;
dma_async_issue_pending(spdifrx->ctrl_chan);
return 0;
}
static void stm32_spdifrx_dma_ctrl_stop(struct stm32_spdifrx_data *spdifrx)
{
dmaengine_terminate_async(spdifrx->ctrl_chan);
}
static int stm32_spdifrx_start_sync(struct stm32_spdifrx_data *spdifrx)
{
int cr, cr_mask, imr, ret;
unsigned long flags;
/* Enable IRQs */
imr = SPDIFRX_IMR_IFEIE | SPDIFRX_IMR_SYNCDIE | SPDIFRX_IMR_PERRIE;
ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR, imr, imr);
if (ret)
return ret;
spin_lock_irqsave(&spdifrx->lock, flags);
spdifrx->refcount++;
regmap_read(spdifrx->regmap, STM32_SPDIFRX_CR, &cr);
if (!(cr & SPDIFRX_CR_SPDIFEN_MASK)) {
/*
* Start sync if SPDIFRX is still in idle state.
* SPDIFRX reception enabled when sync done
*/
dev_dbg(&spdifrx->pdev->dev, "start synchronization\n");
/*
* SPDIFRX configuration:
* Wait for activity before starting sync process. This avoid
* to issue sync errors when spdif signal is missing on input.
* Preamble, CS, user, validity and parity error bits not copied
* to DR register.
*/
cr = SPDIFRX_CR_WFA | SPDIFRX_CR_PMSK | SPDIFRX_CR_VMSK |
SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK | SPDIFRX_CR_RXSTEO;
cr_mask = cr;
cr |= SPDIFRX_CR_NBTRSET(SPDIFRX_NBTR_63);
cr_mask |= SPDIFRX_CR_NBTR_MASK;
cr |= SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_SYNC);
cr_mask |= SPDIFRX_CR_SPDIFEN_MASK;
ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
cr_mask, cr);
if (ret < 0)
dev_err(&spdifrx->pdev->dev,
"Failed to start synchronization\n");
}
spin_unlock_irqrestore(&spdifrx->lock, flags);
return ret;
}
static void stm32_spdifrx_stop(struct stm32_spdifrx_data *spdifrx)
{
int cr, cr_mask, reg;
unsigned long flags;
spin_lock_irqsave(&spdifrx->lock, flags);
if (--spdifrx->refcount) {
spin_unlock_irqrestore(&spdifrx->lock, flags);
return;
}
cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_DISABLE);
cr_mask = SPDIFRX_CR_SPDIFEN_MASK | SPDIFRX_CR_RXDMAEN;
regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, cr_mask, cr);
regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR,
SPDIFRX_XIMR_MASK, 0);
regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IFCR,
SPDIFRX_XIFCR_MASK, SPDIFRX_XIFCR_MASK);
/* dummy read to clear CSRNE and RXNE in status register */
regmap_read(spdifrx->regmap, STM32_SPDIFRX_DR, ®);
regmap_read(spdifrx->regmap, STM32_SPDIFRX_CSR, ®);
spin_unlock_irqrestore(&spdifrx->lock, flags);
}
static int stm32_spdifrx_dma_ctrl_register(struct device *dev,
struct stm32_spdifrx_data *spdifrx)
{
int ret;
spdifrx->ctrl_chan = dma_request_chan(dev, "rx-ctrl");
if (IS_ERR(spdifrx->ctrl_chan))
return dev_err_probe(dev, PTR_ERR(spdifrx->ctrl_chan),
"dma_request_slave_channel error\n");
spdifrx->dmab = devm_kzalloc(dev, sizeof(struct snd_dma_buffer),
GFP_KERNEL);
if (!spdifrx->dmab)
return -ENOMEM;
spdifrx->dmab->dev.type = SNDRV_DMA_TYPE_DEV_IRAM;
spdifrx->dmab->dev.dev = dev;
ret = snd_dma_alloc_pages(spdifrx->dmab->dev.type, dev,
SPDIFRX_CSR_BUF_LENGTH, spdifrx->dmab);
if (ret < 0) {
dev_err(dev, "snd_dma_alloc_pages returned error %d\n", ret);
return ret;
}
spdifrx->slave_config.direction = DMA_DEV_TO_MEM;
spdifrx->slave_config.src_addr = (dma_addr_t)(spdifrx->phys_addr +
STM32_SPDIFRX_CSR);
spdifrx->slave_config.dst_addr = spdifrx->dmab->addr;
spdifrx->slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
spdifrx->slave_config.src_maxburst = 1;
ret = dmaengine_slave_config(spdifrx->ctrl_chan,
&spdifrx->slave_config);
if (ret < 0) {
dev_err(dev, "dmaengine_slave_config returned error %d\n", ret);
spdifrx->ctrl_chan = NULL;
}
return ret;
};
static const char * const spdifrx_enum_input[] = {
"in0", "in1", "in2", "in3"
};
/* By default CS bits are retrieved from channel A */
static const char * const spdifrx_enum_cs_channel[] = {
"A", "B"
};
static SOC_ENUM_SINGLE_DECL(ctrl_enum_input,
STM32_SPDIFRX_CR, SPDIFRX_CR_INSEL_SHIFT,
spdifrx_enum_input);
static SOC_ENUM_SINGLE_DECL(ctrl_enum_cs_channel,
STM32_SPDIFRX_CR, SPDIFRX_CR_CHSEL_SHIFT,
spdifrx_enum_cs_channel);
static int stm32_spdifrx_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
uinfo->count = 1;
return 0;
}
static int stm32_spdifrx_ub_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
uinfo->count = 1;
return 0;
}
static int stm32_spdifrx_get_ctrl_data(struct stm32_spdifrx_data *spdifrx)
{
int ret = 0;
memset(spdifrx->cs, 0, SPDIFRX_CS_BYTES_NB);
memset(spdifrx->ub, 0, SPDIFRX_UB_BYTES_NB);
ret = stm32_spdifrx_dma_ctrl_start(spdifrx);
if (ret < 0)
return ret;
ret = clk_prepare_enable(spdifrx->kclk);
if (ret) {
dev_err(&spdifrx->pdev->dev, "Enable kclk failed: %d\n", ret);
return ret;
}
ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
SPDIFRX_CR_CBDMAEN, SPDIFRX_CR_CBDMAEN);
if (ret < 0)
goto end;
ret = stm32_spdifrx_start_sync(spdifrx);
if (ret < 0)
goto end;
if (wait_for_completion_interruptible_timeout(&spdifrx->cs_completion,
msecs_to_jiffies(100))
<= 0) {
dev_dbg(&spdifrx->pdev->dev, "Failed to get control data\n");
ret = -EAGAIN;
}
stm32_spdifrx_stop(spdifrx);
stm32_spdifrx_dma_ctrl_stop(spdifrx);
end:
clk_disable_unprepare(spdifrx->kclk);
return ret;
}
static int stm32_spdifrx_capture_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
stm32_spdifrx_get_ctrl_data(spdifrx);
ucontrol->value.iec958.status[0] = spdifrx->cs[0];
ucontrol->value.iec958.status[1] = spdifrx->cs[1];
ucontrol->value.iec958.status[2] = spdifrx->cs[2];
ucontrol->value.iec958.status[3] = spdifrx->cs[3];
ucontrol->value.iec958.status[4] = spdifrx->cs[4];
return 0;
}
static int stm32_spdif_user_bits_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
stm32_spdifrx_get_ctrl_data(spdifrx);
ucontrol->value.iec958.status[0] = spdifrx->ub[0];
ucontrol->value.iec958.status[1] = spdifrx->ub[1];
ucontrol->value.iec958.status[2] = spdifrx->ub[2];
ucontrol->value.iec958.status[3] = spdifrx->ub[3];
ucontrol->value.iec958.status[4] = spdifrx->ub[4];
return 0;
}
static struct snd_kcontrol_new stm32_spdifrx_iec_ctrls[] = {
/* Channel status control */
{
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
.name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
.access = SNDRV_CTL_ELEM_ACCESS_READ |
SNDRV_CTL_ELEM_ACCESS_VOLATILE,
.info = stm32_spdifrx_info,
.get = stm32_spdifrx_capture_get,
},
/* User bits control */
{
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
.name = "IEC958 User Bit Capture Default",
.access = SNDRV_CTL_ELEM_ACCESS_READ |
SNDRV_CTL_ELEM_ACCESS_VOLATILE,
.info = stm32_spdifrx_ub_info,
.get = stm32_spdif_user_bits_get,
},
};
static struct snd_kcontrol_new stm32_spdifrx_ctrls[] = {
SOC_ENUM("SPDIFRX input", ctrl_enum_input),
SOC_ENUM("SPDIFRX CS channel", ctrl_enum_cs_channel),
};
static int stm32_spdifrx_dai_register_ctrls(struct snd_soc_dai *cpu_dai)
{
int ret;
ret = snd_soc_add_dai_controls(cpu_dai, stm32_spdifrx_iec_ctrls,
ARRAY_SIZE(stm32_spdifrx_iec_ctrls));
if (ret < 0)
return ret;
return snd_soc_add_component_controls(cpu_dai->component,
stm32_spdifrx_ctrls,
ARRAY_SIZE(stm32_spdifrx_ctrls));
}
static int stm32_spdifrx_dai_probe(struct snd_soc_dai *cpu_dai)
{
struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(cpu_dai->dev);
spdifrx->dma_params.addr = (dma_addr_t)(spdifrx->phys_addr +
STM32_SPDIFRX_DR);
spdifrx->dma_params.maxburst = 1;
snd_soc_dai_init_dma_data(cpu_dai, NULL, &spdifrx->dma_params);
return stm32_spdifrx_dai_register_ctrls(cpu_dai);
}
static bool stm32_spdifrx_readable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case STM32_SPDIFRX_CR:
case STM32_SPDIFRX_IMR:
case STM32_SPDIFRX_SR:
case STM32_SPDIFRX_IFCR:
case STM32_SPDIFRX_DR:
case STM32_SPDIFRX_CSR:
case STM32_SPDIFRX_DIR:
case STM32_SPDIFRX_VERR:
case STM32_SPDIFRX_IDR:
case STM32_SPDIFRX_SIDR:
return true;
default:
return false;
}
}
static bool stm32_spdifrx_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case STM32_SPDIFRX_DR:
case STM32_SPDIFRX_CSR:
case STM32_SPDIFRX_SR:
case STM32_SPDIFRX_DIR:
return true;
default:
return false;
}
}
static bool stm32_spdifrx_writeable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case STM32_SPDIFRX_CR:
case STM32_SPDIFRX_IMR:
case STM32_SPDIFRX_IFCR:
return true;
default:
return false;
}
}
static const struct regmap_config stm32_h7_spdifrx_regmap_conf = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = STM32_SPDIFRX_SIDR,
.readable_reg = stm32_spdifrx_readable_reg,
.volatile_reg = stm32_spdifrx_volatile_reg,
.writeable_reg = stm32_spdifrx_writeable_reg,
.num_reg_defaults_raw = STM32_SPDIFRX_SIDR / sizeof(u32) + 1,
.fast_io = true,
.cache_type = REGCACHE_FLAT,
};
static irqreturn_t stm32_spdifrx_isr(int irq, void *devid)
{
struct stm32_spdifrx_data *spdifrx = (struct stm32_spdifrx_data *)devid;
struct platform_device *pdev = spdifrx->pdev;
unsigned int cr, mask, sr, imr;
unsigned int flags, sync_state;
int err = 0, err_xrun = 0;
regmap_read(spdifrx->regmap, STM32_SPDIFRX_SR, &sr);
regmap_read(spdifrx->regmap, STM32_SPDIFRX_IMR, &imr);
mask = imr & SPDIFRX_XIMR_MASK;
/* SERR, TERR, FERR IRQs are generated if IFEIE is set */
if (mask & SPDIFRX_IMR_IFEIE)
mask |= (SPDIFRX_IMR_IFEIE << 1) | (SPDIFRX_IMR_IFEIE << 2);
flags = sr & mask;
if (!flags) {
dev_err(&pdev->dev, "Unexpected IRQ. rflags=%#x, imr=%#x\n",
sr, imr);
return IRQ_NONE;
}
/* Clear IRQs */
regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IFCR,
SPDIFRX_XIFCR_MASK, flags);
if (flags & SPDIFRX_SR_PERR) {
dev_dbg(&pdev->dev, "Parity error\n");
err_xrun = 1;
}
if (flags & SPDIFRX_SR_OVR) {
dev_dbg(&pdev->dev, "Overrun error\n");
err_xrun = 1;
}
if (flags & SPDIFRX_SR_SBD)
dev_dbg(&pdev->dev, "Synchronization block detected\n");
if (flags & SPDIFRX_SR_SYNCD) {
dev_dbg(&pdev->dev, "Synchronization done\n");
/* Enable spdifrx */
cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_ENABLE);
regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
SPDIFRX_CR_SPDIFEN_MASK, cr);
}
if (flags & SPDIFRX_SR_FERR) {
dev_dbg(&pdev->dev, "Frame error\n");
err = 1;
}
if (flags & SPDIFRX_SR_SERR) {
dev_dbg(&pdev->dev, "Synchronization error\n");
err = 1;
}
if (flags & SPDIFRX_SR_TERR) {
dev_dbg(&pdev->dev, "Timeout error\n");
err = 1;
}
if (err) {
regmap_read(spdifrx->regmap, STM32_SPDIFRX_CR, &cr);
sync_state = FIELD_GET(SPDIFRX_CR_SPDIFEN_MASK, cr) &&
SPDIFRX_SPDIFEN_SYNC;
/* SPDIFRX is in STATE_STOP. Disable SPDIFRX to clear errors */
cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_DISABLE);
regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
SPDIFRX_CR_SPDIFEN_MASK, cr);
/* If SPDIFRX was in STATE_SYNC, retry synchro */
if (sync_state) {
cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_SYNC);
regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
SPDIFRX_CR_SPDIFEN_MASK, cr);
return IRQ_HANDLED;
}
spin_lock(&spdifrx->irq_lock);
if (spdifrx->substream)
snd_pcm_stop(spdifrx->substream,
SNDRV_PCM_STATE_DISCONNECTED);
spin_unlock(&spdifrx->irq_lock);
return IRQ_HANDLED;
}
spin_lock(&spdifrx->irq_lock);
if (err_xrun && spdifrx->substream)
snd_pcm_stop_xrun(spdifrx->substream);
spin_unlock(&spdifrx->irq_lock);
return IRQ_HANDLED;
}
static int stm32_spdifrx_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *cpu_dai)
{
struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
unsigned long flags;
int ret;
spin_lock_irqsave(&spdifrx->irq_lock, flags);
spdifrx->substream = substream;
spin_unlock_irqrestore(&spdifrx->irq_lock, flags);
ret = clk_prepare_enable(spdifrx->kclk);
if (ret)
dev_err(&spdifrx->pdev->dev, "Enable kclk failed: %d\n", ret);
return ret;
}
static int stm32_spdifrx_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *cpu_dai)
{
struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
int data_size = params_width(params);
int fmt;
switch (data_size) {
case 16:
fmt = SPDIFRX_DRFMT_PACKED;
break;
case 32:
fmt = SPDIFRX_DRFMT_LEFT;
break;
default:
dev_err(&spdifrx->pdev->dev, "Unexpected data format\n");
return -EINVAL;
}
/*
* Set buswidth to 4 bytes for all data formats.
* Packed format: transfer 2 x 2 bytes samples
* Left format: transfer 1 x 3 bytes samples + 1 dummy byte
*/
spdifrx->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
snd_soc_dai_init_dma_data(cpu_dai, NULL, &spdifrx->dma_params);
return regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
SPDIFRX_CR_DRFMT_MASK,
SPDIFRX_CR_DRFMTSET(fmt));
}
static int stm32_spdifrx_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *cpu_dai)
{
struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
int ret = 0;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR,
SPDIFRX_IMR_OVRIE, SPDIFRX_IMR_OVRIE);
regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
SPDIFRX_CR_RXDMAEN, SPDIFRX_CR_RXDMAEN);
ret = stm32_spdifrx_start_sync(spdifrx);
break;
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
case SNDRV_PCM_TRIGGER_STOP:
stm32_spdifrx_stop(spdifrx);
break;
default:
return -EINVAL;
}
return ret;
}
static void stm32_spdifrx_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *cpu_dai)
{
struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
unsigned long flags;
spin_lock_irqsave(&spdifrx->irq_lock, flags);
spdifrx->substream = NULL;
spin_unlock_irqrestore(&spdifrx->irq_lock, flags);
clk_disable_unprepare(spdifrx->kclk);
}
static const struct snd_soc_dai_ops stm32_spdifrx_pcm_dai_ops = {
.probe = stm32_spdifrx_dai_probe,
.startup = stm32_spdifrx_startup,
.hw_params = stm32_spdifrx_hw_params,
.trigger = stm32_spdifrx_trigger,
.shutdown = stm32_spdifrx_shutdown,
};
static struct snd_soc_dai_driver stm32_spdifrx_dai[] = {
{
.capture = {
.stream_name = "CPU-Capture",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = SNDRV_PCM_FMTBIT_S32_LE |
SNDRV_PCM_FMTBIT_S16_LE,
},
.ops = &stm32_spdifrx_pcm_dai_ops,
}
};
static const struct snd_pcm_hardware stm32_spdifrx_pcm_hw = {
.info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP,
.buffer_bytes_max = 8 * PAGE_SIZE,
.period_bytes_min = 1024,
.period_bytes_max = 4 * PAGE_SIZE,
.periods_min = 2,
.periods_max = 8,
};
static const struct snd_soc_component_driver stm32_spdifrx_component = {
.name = "stm32-spdifrx",
.legacy_dai_naming = 1,
};
static const struct snd_dmaengine_pcm_config stm32_spdifrx_pcm_config = {
.pcm_hardware = &stm32_spdifrx_pcm_hw,
.prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
};
static const struct of_device_id stm32_spdifrx_ids[] = {
{
.compatible = "st,stm32h7-spdifrx",
.data = &stm32_h7_spdifrx_regmap_conf
},
{}
};
static int stm32_spdifrx_parse_of(struct platform_device *pdev,
struct stm32_spdifrx_data *spdifrx)
{
struct device_node *np = pdev->dev.of_node;
const struct of_device_id *of_id;
struct resource *res;
if (!np)
return -ENODEV;
of_id = of_match_device(stm32_spdifrx_ids, &pdev->dev);
if (of_id)
spdifrx->regmap_conf =
(const struct regmap_config *)of_id->data;
else
return -EINVAL;
spdifrx->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(spdifrx->base))
return PTR_ERR(spdifrx->base);
spdifrx->phys_addr = res->start;
spdifrx->kclk = devm_clk_get(&pdev->dev, "kclk");
if (IS_ERR(spdifrx->kclk))
return dev_err_probe(&pdev->dev, PTR_ERR(spdifrx->kclk),
"Could not get kclk\n");
spdifrx->irq = platform_get_irq(pdev, 0);
if (spdifrx->irq < 0)
return spdifrx->irq;
return 0;
}
static void stm32_spdifrx_remove(struct platform_device *pdev)
{
struct stm32_spdifrx_data *spdifrx = platform_get_drvdata(pdev);
if (spdifrx->ctrl_chan)
dma_release_channel(spdifrx->ctrl_chan);
if (spdifrx->dmab)
snd_dma_free_pages(spdifrx->dmab);
snd_dmaengine_pcm_unregister(&pdev->dev);
snd_soc_unregister_component(&pdev->dev);
pm_runtime_disable(&pdev->dev);
}
static int stm32_spdifrx_probe(struct platform_device *pdev)
{
struct stm32_spdifrx_data *spdifrx;
struct reset_control *rst;
const struct snd_dmaengine_pcm_config *pcm_config = NULL;
u32 ver, idr;
int ret;
spdifrx = devm_kzalloc(&pdev->dev, sizeof(*spdifrx), GFP_KERNEL);
if (!spdifrx)
return -ENOMEM;
spdifrx->pdev = pdev;
init_completion(&spdifrx->cs_completion);
spin_lock_init(&spdifrx->lock);
spin_lock_init(&spdifrx->irq_lock);
platform_set_drvdata(pdev, spdifrx);
ret = stm32_spdifrx_parse_of(pdev, spdifrx);
if (ret)
return ret;
spdifrx->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "kclk",
spdifrx->base,
spdifrx->regmap_conf);
if (IS_ERR(spdifrx->regmap))
return dev_err_probe(&pdev->dev, PTR_ERR(spdifrx->regmap),
"Regmap init error\n");
ret = devm_request_irq(&pdev->dev, spdifrx->irq, stm32_spdifrx_isr, 0,
dev_name(&pdev->dev), spdifrx);
if (ret) {
dev_err(&pdev->dev, "IRQ request returned %d\n", ret);
return ret;
}
rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
if (IS_ERR(rst))
return dev_err_probe(&pdev->dev, PTR_ERR(rst),
"Reset controller error\n");
reset_control_assert(rst);
udelay(2);
reset_control_deassert(rst);
pcm_config = &stm32_spdifrx_pcm_config;
ret = snd_dmaengine_pcm_register(&pdev->dev, pcm_config, 0);
if (ret)
return dev_err_probe(&pdev->dev, ret, "PCM DMA register error\n");
ret = snd_soc_register_component(&pdev->dev,
&stm32_spdifrx_component,
stm32_spdifrx_dai,
ARRAY_SIZE(stm32_spdifrx_dai));
if (ret) {
snd_dmaengine_pcm_unregister(&pdev->dev);
return ret;
}
ret = stm32_spdifrx_dma_ctrl_register(&pdev->dev, spdifrx);
if (ret)
goto error;
ret = regmap_read(spdifrx->regmap, STM32_SPDIFRX_IDR, &idr);
if (ret)
goto error;
if (idr == SPDIFRX_IPIDR_NUMBER) {
ret = regmap_read(spdifrx->regmap, STM32_SPDIFRX_VERR, &ver);
if (ret)
goto error;
dev_dbg(&pdev->dev, "SPDIFRX version: %lu.%lu registered\n",
FIELD_GET(SPDIFRX_VERR_MAJ_MASK, ver),
FIELD_GET(SPDIFRX_VERR_MIN_MASK, ver));
}
pm_runtime_enable(&pdev->dev);
return ret;
error:
stm32_spdifrx_remove(pdev);
return ret;
}
MODULE_DEVICE_TABLE(of, stm32_spdifrx_ids);
#ifdef CONFIG_PM_SLEEP
static int stm32_spdifrx_suspend(struct device *dev)
{
struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(dev);
regcache_cache_only(spdifrx->regmap, true);
regcache_mark_dirty(spdifrx->regmap);
return 0;
}
static int stm32_spdifrx_resume(struct device *dev)
{
struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(dev);
regcache_cache_only(spdifrx->regmap, false);
return regcache_sync(spdifrx->regmap);
}
#endif /* CONFIG_PM_SLEEP */
static const struct dev_pm_ops stm32_spdifrx_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(stm32_spdifrx_suspend, stm32_spdifrx_resume)
};
static struct platform_driver stm32_spdifrx_driver = {
.driver = {
.name = "st,stm32-spdifrx",
.of_match_table = stm32_spdifrx_ids,
.pm = &stm32_spdifrx_pm_ops,
},
.probe = stm32_spdifrx_probe,
.remove_new = stm32_spdifrx_remove,
};
module_platform_driver(stm32_spdifrx_driver);
MODULE_DESCRIPTION("STM32 Soc spdifrx Interface");
MODULE_AUTHOR("Olivier Moysan, <[email protected]>");
MODULE_ALIAS("platform:stm32-spdifrx");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/stm/stm32_spdifrx.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* STM32 ALSA SoC Digital Audio Interface (SAI) driver.
*
* Copyright (C) 2016, STMicroelectronics - All Rights Reserved
* Author(s): Olivier Moysan <[email protected]> for STMicroelectronics.
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <sound/asoundef.h>
#include <sound/core.h>
#include <sound/dmaengine_pcm.h>
#include <sound/pcm_params.h>
#include "stm32_sai.h"
#define SAI_FREE_PROTOCOL 0x0
#define SAI_SPDIF_PROTOCOL 0x1
#define SAI_SLOT_SIZE_AUTO 0x0
#define SAI_SLOT_SIZE_16 0x1
#define SAI_SLOT_SIZE_32 0x2
#define SAI_DATASIZE_8 0x2
#define SAI_DATASIZE_10 0x3
#define SAI_DATASIZE_16 0x4
#define SAI_DATASIZE_20 0x5
#define SAI_DATASIZE_24 0x6
#define SAI_DATASIZE_32 0x7
#define STM_SAI_DAI_NAME_SIZE 15
#define STM_SAI_IS_PLAYBACK(ip) ((ip)->dir == SNDRV_PCM_STREAM_PLAYBACK)
#define STM_SAI_IS_CAPTURE(ip) ((ip)->dir == SNDRV_PCM_STREAM_CAPTURE)
#define STM_SAI_A_ID 0x0
#define STM_SAI_B_ID 0x1
#define STM_SAI_IS_SUB_A(x) ((x)->id == STM_SAI_A_ID)
#define SAI_SYNC_NONE 0x0
#define SAI_SYNC_INTERNAL 0x1
#define SAI_SYNC_EXTERNAL 0x2
#define STM_SAI_PROTOCOL_IS_SPDIF(ip) ((ip)->spdif)
#define STM_SAI_HAS_SPDIF(x) ((x)->pdata->conf.has_spdif_pdm)
#define STM_SAI_HAS_PDM(x) ((x)->pdata->conf.has_spdif_pdm)
#define STM_SAI_HAS_EXT_SYNC(x) (!STM_SAI_IS_F4(sai->pdata))
#define SAI_IEC60958_BLOCK_FRAMES 192
#define SAI_IEC60958_STATUS_BYTES 24
#define SAI_MCLK_NAME_LEN 32
#define SAI_RATE_11K 11025
/**
* struct stm32_sai_sub_data - private data of SAI sub block (block A or B)
* @pdev: device data pointer
* @regmap: SAI register map pointer
* @regmap_config: SAI sub block register map configuration pointer
* @dma_params: dma configuration data for rx or tx channel
* @cpu_dai_drv: DAI driver data pointer
* @cpu_dai: DAI runtime data pointer
* @substream: PCM substream data pointer
* @pdata: SAI block parent data pointer
* @np_sync_provider: synchronization provider node
* @sai_ck: kernel clock feeding the SAI clock generator
* @sai_mclk: master clock from SAI mclk provider
* @phys_addr: SAI registers physical base address
* @mclk_rate: SAI block master clock frequency (Hz). set at init
* @id: SAI sub block id corresponding to sub-block A or B
* @dir: SAI block direction (playback or capture). set at init
* @master: SAI block mode flag. (true=master, false=slave) set at init
* @spdif: SAI S/PDIF iec60958 mode flag. set at init
* @fmt: SAI block format. relevant only for custom protocols. set at init
* @sync: SAI block synchronization mode. (none, internal or external)
* @synco: SAI block ext sync source (provider setting). (none, sub-block A/B)
* @synci: SAI block ext sync source (client setting). (SAI sync provider index)
* @fs_length: frame synchronization length. depends on protocol settings
* @slots: rx or tx slot number
* @slot_width: rx or tx slot width in bits
* @slot_mask: rx or tx active slots mask. set at init or at runtime
* @data_size: PCM data width. corresponds to PCM substream width.
* @spdif_frm_cnt: S/PDIF playback frame counter
* @iec958: iec958 data
* @ctrl_lock: control lock
* @irq_lock: prevent race condition with IRQ
*/
struct stm32_sai_sub_data {
struct platform_device *pdev;
struct regmap *regmap;
const struct regmap_config *regmap_config;
struct snd_dmaengine_dai_dma_data dma_params;
struct snd_soc_dai_driver cpu_dai_drv;
struct snd_soc_dai *cpu_dai;
struct snd_pcm_substream *substream;
struct stm32_sai_data *pdata;
struct device_node *np_sync_provider;
struct clk *sai_ck;
struct clk *sai_mclk;
dma_addr_t phys_addr;
unsigned int mclk_rate;
unsigned int id;
int dir;
bool master;
bool spdif;
int fmt;
int sync;
int synco;
int synci;
int fs_length;
int slots;
int slot_width;
int slot_mask;
int data_size;
unsigned int spdif_frm_cnt;
struct snd_aes_iec958 iec958;
struct mutex ctrl_lock; /* protect resources accessed by controls */
spinlock_t irq_lock; /* used to prevent race condition with IRQ */
};
enum stm32_sai_fifo_th {
STM_SAI_FIFO_TH_EMPTY,
STM_SAI_FIFO_TH_QUARTER,
STM_SAI_FIFO_TH_HALF,
STM_SAI_FIFO_TH_3_QUARTER,
STM_SAI_FIFO_TH_FULL,
};
static bool stm32_sai_sub_readable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case STM_SAI_CR1_REGX:
case STM_SAI_CR2_REGX:
case STM_SAI_FRCR_REGX:
case STM_SAI_SLOTR_REGX:
case STM_SAI_IMR_REGX:
case STM_SAI_SR_REGX:
case STM_SAI_CLRFR_REGX:
case STM_SAI_DR_REGX:
case STM_SAI_PDMCR_REGX:
case STM_SAI_PDMLY_REGX:
return true;
default:
return false;
}
}
static bool stm32_sai_sub_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case STM_SAI_DR_REGX:
case STM_SAI_SR_REGX:
return true;
default:
return false;
}
}
static bool stm32_sai_sub_writeable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case STM_SAI_CR1_REGX:
case STM_SAI_CR2_REGX:
case STM_SAI_FRCR_REGX:
case STM_SAI_SLOTR_REGX:
case STM_SAI_IMR_REGX:
case STM_SAI_CLRFR_REGX:
case STM_SAI_DR_REGX:
case STM_SAI_PDMCR_REGX:
case STM_SAI_PDMLY_REGX:
return true;
default:
return false;
}
}
static int stm32_sai_sub_reg_up(struct stm32_sai_sub_data *sai,
unsigned int reg, unsigned int mask,
unsigned int val)
{
int ret;
ret = clk_enable(sai->pdata->pclk);
if (ret < 0)
return ret;
ret = regmap_update_bits(sai->regmap, reg, mask, val);
clk_disable(sai->pdata->pclk);
return ret;
}
static int stm32_sai_sub_reg_wr(struct stm32_sai_sub_data *sai,
unsigned int reg, unsigned int mask,
unsigned int val)
{
int ret;
ret = clk_enable(sai->pdata->pclk);
if (ret < 0)
return ret;
ret = regmap_write_bits(sai->regmap, reg, mask, val);
clk_disable(sai->pdata->pclk);
return ret;
}
static int stm32_sai_sub_reg_rd(struct stm32_sai_sub_data *sai,
unsigned int reg, unsigned int *val)
{
int ret;
ret = clk_enable(sai->pdata->pclk);
if (ret < 0)
return ret;
ret = regmap_read(sai->regmap, reg, val);
clk_disable(sai->pdata->pclk);
return ret;
}
static const struct regmap_config stm32_sai_sub_regmap_config_f4 = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = STM_SAI_DR_REGX,
.readable_reg = stm32_sai_sub_readable_reg,
.volatile_reg = stm32_sai_sub_volatile_reg,
.writeable_reg = stm32_sai_sub_writeable_reg,
.fast_io = true,
.cache_type = REGCACHE_FLAT,
};
static const struct regmap_config stm32_sai_sub_regmap_config_h7 = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = STM_SAI_PDMLY_REGX,
.readable_reg = stm32_sai_sub_readable_reg,
.volatile_reg = stm32_sai_sub_volatile_reg,
.writeable_reg = stm32_sai_sub_writeable_reg,
.fast_io = true,
.cache_type = REGCACHE_FLAT,
};
static int snd_pcm_iec958_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
uinfo->count = 1;
return 0;
}
static int snd_pcm_iec958_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *uctl)
{
struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol);
mutex_lock(&sai->ctrl_lock);
memcpy(uctl->value.iec958.status, sai->iec958.status, 4);
mutex_unlock(&sai->ctrl_lock);
return 0;
}
static int snd_pcm_iec958_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *uctl)
{
struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol);
mutex_lock(&sai->ctrl_lock);
memcpy(sai->iec958.status, uctl->value.iec958.status, 4);
mutex_unlock(&sai->ctrl_lock);
return 0;
}
static const struct snd_kcontrol_new iec958_ctls = {
.access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
SNDRV_CTL_ELEM_ACCESS_VOLATILE),
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
.name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
.info = snd_pcm_iec958_info,
.get = snd_pcm_iec958_get,
.put = snd_pcm_iec958_put,
};
struct stm32_sai_mclk_data {
struct clk_hw hw;
unsigned long freq;
struct stm32_sai_sub_data *sai_data;
};
#define to_mclk_data(_hw) container_of(_hw, struct stm32_sai_mclk_data, hw)
#define STM32_SAI_MAX_CLKS 1
static int stm32_sai_get_clk_div(struct stm32_sai_sub_data *sai,
unsigned long input_rate,
unsigned long output_rate)
{
int version = sai->pdata->conf.version;
int div;
div = DIV_ROUND_CLOSEST(input_rate, output_rate);
if (div > SAI_XCR1_MCKDIV_MAX(version)) {
dev_err(&sai->pdev->dev, "Divider %d out of range\n", div);
return -EINVAL;
}
dev_dbg(&sai->pdev->dev, "SAI divider %d\n", div);
if (input_rate % div)
dev_dbg(&sai->pdev->dev,
"Rate not accurate. requested (%ld), actual (%ld)\n",
output_rate, input_rate / div);
return div;
}
static int stm32_sai_set_clk_div(struct stm32_sai_sub_data *sai,
unsigned int div)
{
int version = sai->pdata->conf.version;
int ret, cr1, mask;
if (div > SAI_XCR1_MCKDIV_MAX(version)) {
dev_err(&sai->pdev->dev, "Divider %d out of range\n", div);
return -EINVAL;
}
mask = SAI_XCR1_MCKDIV_MASK(SAI_XCR1_MCKDIV_WIDTH(version));
cr1 = SAI_XCR1_MCKDIV_SET(div);
ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, mask, cr1);
if (ret < 0)
dev_err(&sai->pdev->dev, "Failed to update CR1 register\n");
return ret;
}
static int stm32_sai_set_parent_clock(struct stm32_sai_sub_data *sai,
unsigned int rate)
{
struct platform_device *pdev = sai->pdev;
struct clk *parent_clk = sai->pdata->clk_x8k;
int ret;
if (!(rate % SAI_RATE_11K))
parent_clk = sai->pdata->clk_x11k;
ret = clk_set_parent(sai->sai_ck, parent_clk);
if (ret)
dev_err(&pdev->dev, " Error %d setting sai_ck parent clock. %s",
ret, ret == -EBUSY ?
"Active stream rates conflict\n" : "\n");
return ret;
}
static long stm32_sai_mclk_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
struct stm32_sai_sub_data *sai = mclk->sai_data;
int div;
div = stm32_sai_get_clk_div(sai, *prate, rate);
if (div < 0)
return div;
mclk->freq = *prate / div;
return mclk->freq;
}
static unsigned long stm32_sai_mclk_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
return mclk->freq;
}
static int stm32_sai_mclk_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
struct stm32_sai_sub_data *sai = mclk->sai_data;
int div, ret;
div = stm32_sai_get_clk_div(sai, parent_rate, rate);
if (div < 0)
return div;
ret = stm32_sai_set_clk_div(sai, div);
if (ret)
return ret;
mclk->freq = rate;
return 0;
}
static int stm32_sai_mclk_enable(struct clk_hw *hw)
{
struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
struct stm32_sai_sub_data *sai = mclk->sai_data;
dev_dbg(&sai->pdev->dev, "Enable master clock\n");
return stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX,
SAI_XCR1_MCKEN, SAI_XCR1_MCKEN);
}
static void stm32_sai_mclk_disable(struct clk_hw *hw)
{
struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
struct stm32_sai_sub_data *sai = mclk->sai_data;
dev_dbg(&sai->pdev->dev, "Disable master clock\n");
stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, SAI_XCR1_MCKEN, 0);
}
static const struct clk_ops mclk_ops = {
.enable = stm32_sai_mclk_enable,
.disable = stm32_sai_mclk_disable,
.recalc_rate = stm32_sai_mclk_recalc_rate,
.round_rate = stm32_sai_mclk_round_rate,
.set_rate = stm32_sai_mclk_set_rate,
};
static int stm32_sai_add_mclk_provider(struct stm32_sai_sub_data *sai)
{
struct clk_hw *hw;
struct stm32_sai_mclk_data *mclk;
struct device *dev = &sai->pdev->dev;
const char *pname = __clk_get_name(sai->sai_ck);
char *mclk_name, *p, *s = (char *)pname;
int ret, i = 0;
mclk = devm_kzalloc(dev, sizeof(*mclk), GFP_KERNEL);
if (!mclk)
return -ENOMEM;
mclk_name = devm_kcalloc(dev, sizeof(char),
SAI_MCLK_NAME_LEN, GFP_KERNEL);
if (!mclk_name)
return -ENOMEM;
/*
* Forge mclk clock name from parent clock name and suffix.
* String after "_" char is stripped in parent name.
*/
p = mclk_name;
while (*s && *s != '_' && (i < (SAI_MCLK_NAME_LEN - 7))) {
*p++ = *s++;
i++;
}
STM_SAI_IS_SUB_A(sai) ? strcat(p, "a_mclk") : strcat(p, "b_mclk");
mclk->hw.init = CLK_HW_INIT(mclk_name, pname, &mclk_ops, 0);
mclk->sai_data = sai;
hw = &mclk->hw;
dev_dbg(dev, "Register master clock %s\n", mclk_name);
ret = devm_clk_hw_register(&sai->pdev->dev, hw);
if (ret) {
dev_err(dev, "mclk register returned %d\n", ret);
return ret;
}
sai->sai_mclk = hw->clk;
/* register mclk provider */
return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
}
static irqreturn_t stm32_sai_isr(int irq, void *devid)
{
struct stm32_sai_sub_data *sai = (struct stm32_sai_sub_data *)devid;
struct platform_device *pdev = sai->pdev;
unsigned int sr, imr, flags;
snd_pcm_state_t status = SNDRV_PCM_STATE_RUNNING;
stm32_sai_sub_reg_rd(sai, STM_SAI_IMR_REGX, &imr);
stm32_sai_sub_reg_rd(sai, STM_SAI_SR_REGX, &sr);
flags = sr & imr;
if (!flags)
return IRQ_NONE;
stm32_sai_sub_reg_wr(sai, STM_SAI_CLRFR_REGX, SAI_XCLRFR_MASK,
SAI_XCLRFR_MASK);
if (!sai->substream) {
dev_err(&pdev->dev, "Device stopped. Spurious IRQ 0x%x\n", sr);
return IRQ_NONE;
}
if (flags & SAI_XIMR_OVRUDRIE) {
dev_err(&pdev->dev, "IRQ %s\n",
STM_SAI_IS_PLAYBACK(sai) ? "underrun" : "overrun");
status = SNDRV_PCM_STATE_XRUN;
}
if (flags & SAI_XIMR_MUTEDETIE)
dev_dbg(&pdev->dev, "IRQ mute detected\n");
if (flags & SAI_XIMR_WCKCFGIE) {
dev_err(&pdev->dev, "IRQ wrong clock configuration\n");
status = SNDRV_PCM_STATE_DISCONNECTED;
}
if (flags & SAI_XIMR_CNRDYIE)
dev_err(&pdev->dev, "IRQ Codec not ready\n");
if (flags & SAI_XIMR_AFSDETIE) {
dev_err(&pdev->dev, "IRQ Anticipated frame synchro\n");
status = SNDRV_PCM_STATE_XRUN;
}
if (flags & SAI_XIMR_LFSDETIE) {
dev_err(&pdev->dev, "IRQ Late frame synchro\n");
status = SNDRV_PCM_STATE_XRUN;
}
spin_lock(&sai->irq_lock);
if (status != SNDRV_PCM_STATE_RUNNING && sai->substream)
snd_pcm_stop_xrun(sai->substream);
spin_unlock(&sai->irq_lock);
return IRQ_HANDLED;
}
static int stm32_sai_set_sysclk(struct snd_soc_dai *cpu_dai,
int clk_id, unsigned int freq, int dir)
{
struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
int ret;
if (dir == SND_SOC_CLOCK_OUT && sai->sai_mclk) {
ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX,
SAI_XCR1_NODIV,
freq ? 0 : SAI_XCR1_NODIV);
if (ret < 0)
return ret;
/* Assume shutdown if requested frequency is 0Hz */
if (!freq) {
/* Release mclk rate only if rate was actually set */
if (sai->mclk_rate) {
clk_rate_exclusive_put(sai->sai_mclk);
sai->mclk_rate = 0;
}
return 0;
}
/* If master clock is used, set parent clock now */
ret = stm32_sai_set_parent_clock(sai, freq);
if (ret)
return ret;
ret = clk_set_rate_exclusive(sai->sai_mclk, freq);
if (ret) {
dev_err(cpu_dai->dev,
ret == -EBUSY ?
"Active streams have incompatible rates" :
"Could not set mclk rate\n");
return ret;
}
dev_dbg(cpu_dai->dev, "SAI MCLK frequency is %uHz\n", freq);
sai->mclk_rate = freq;
}
return 0;
}
static int stm32_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
u32 rx_mask, int slots, int slot_width)
{
struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
int slotr, slotr_mask, slot_size;
if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
dev_warn(cpu_dai->dev, "Slot setting relevant only for TDM\n");
return 0;
}
dev_dbg(cpu_dai->dev, "Masks tx/rx:%#x/%#x, slots:%d, width:%d\n",
tx_mask, rx_mask, slots, slot_width);
switch (slot_width) {
case 16:
slot_size = SAI_SLOT_SIZE_16;
break;
case 32:
slot_size = SAI_SLOT_SIZE_32;
break;
default:
slot_size = SAI_SLOT_SIZE_AUTO;
break;
}
slotr = SAI_XSLOTR_SLOTSZ_SET(slot_size) |
SAI_XSLOTR_NBSLOT_SET(slots - 1);
slotr_mask = SAI_XSLOTR_SLOTSZ_MASK | SAI_XSLOTR_NBSLOT_MASK;
/* tx/rx mask set in machine init, if slot number defined in DT */
if (STM_SAI_IS_PLAYBACK(sai)) {
sai->slot_mask = tx_mask;
slotr |= SAI_XSLOTR_SLOTEN_SET(tx_mask);
}
if (STM_SAI_IS_CAPTURE(sai)) {
sai->slot_mask = rx_mask;
slotr |= SAI_XSLOTR_SLOTEN_SET(rx_mask);
}
slotr_mask |= SAI_XSLOTR_SLOTEN_MASK;
stm32_sai_sub_reg_up(sai, STM_SAI_SLOTR_REGX, slotr_mask, slotr);
sai->slot_width = slot_width;
sai->slots = slots;
return 0;
}
static int stm32_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
{
struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
int cr1, frcr = 0;
int cr1_mask, frcr_mask = 0;
int ret;
dev_dbg(cpu_dai->dev, "fmt %x\n", fmt);
/* Do not generate master by default */
cr1 = SAI_XCR1_NODIV;
cr1_mask = SAI_XCR1_NODIV;
cr1_mask |= SAI_XCR1_PRTCFG_MASK;
if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
cr1 |= SAI_XCR1_PRTCFG_SET(SAI_SPDIF_PROTOCOL);
goto conf_update;
}
cr1 |= SAI_XCR1_PRTCFG_SET(SAI_FREE_PROTOCOL);
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
/* SCK active high for all protocols */
case SND_SOC_DAIFMT_I2S:
cr1 |= SAI_XCR1_CKSTR;
frcr |= SAI_XFRCR_FSOFF | SAI_XFRCR_FSDEF;
break;
/* Left justified */
case SND_SOC_DAIFMT_MSB:
frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF;
break;
/* Right justified */
case SND_SOC_DAIFMT_LSB:
frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF;
break;
case SND_SOC_DAIFMT_DSP_A:
frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF;
break;
case SND_SOC_DAIFMT_DSP_B:
frcr |= SAI_XFRCR_FSPOL;
break;
default:
dev_err(cpu_dai->dev, "Unsupported protocol %#x\n",
fmt & SND_SOC_DAIFMT_FORMAT_MASK);
return -EINVAL;
}
cr1_mask |= SAI_XCR1_CKSTR;
frcr_mask |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF |
SAI_XFRCR_FSDEF;
/* DAI clock strobing. Invert setting previously set */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
cr1 ^= SAI_XCR1_CKSTR;
break;
case SND_SOC_DAIFMT_NB_IF:
frcr ^= SAI_XFRCR_FSPOL;
break;
case SND_SOC_DAIFMT_IB_IF:
/* Invert fs & sck */
cr1 ^= SAI_XCR1_CKSTR;
frcr ^= SAI_XFRCR_FSPOL;
break;
default:
dev_err(cpu_dai->dev, "Unsupported strobing %#x\n",
fmt & SND_SOC_DAIFMT_INV_MASK);
return -EINVAL;
}
cr1_mask |= SAI_XCR1_CKSTR;
frcr_mask |= SAI_XFRCR_FSPOL;
stm32_sai_sub_reg_up(sai, STM_SAI_FRCR_REGX, frcr_mask, frcr);
/* DAI clock master masks */
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BC_FC:
/* codec is master */
cr1 |= SAI_XCR1_SLAVE;
sai->master = false;
break;
case SND_SOC_DAIFMT_BP_FP:
sai->master = true;
break;
default:
dev_err(cpu_dai->dev, "Unsupported mode %#x\n",
fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK);
return -EINVAL;
}
/* Set slave mode if sub-block is synchronized with another SAI */
if (sai->sync) {
dev_dbg(cpu_dai->dev, "Synchronized SAI configured as slave\n");
cr1 |= SAI_XCR1_SLAVE;
sai->master = false;
}
cr1_mask |= SAI_XCR1_SLAVE;
conf_update:
ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, cr1_mask, cr1);
if (ret < 0) {
dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
return ret;
}
sai->fmt = fmt;
return 0;
}
static int stm32_sai_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *cpu_dai)
{
struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
int imr, cr2, ret;
unsigned long flags;
spin_lock_irqsave(&sai->irq_lock, flags);
sai->substream = substream;
spin_unlock_irqrestore(&sai->irq_lock, flags);
if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
snd_pcm_hw_constraint_mask64(substream->runtime,
SNDRV_PCM_HW_PARAM_FORMAT,
SNDRV_PCM_FMTBIT_S32_LE);
snd_pcm_hw_constraint_single(substream->runtime,
SNDRV_PCM_HW_PARAM_CHANNELS, 2);
}
ret = clk_prepare_enable(sai->sai_ck);
if (ret < 0) {
dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret);
return ret;
}
/* Enable ITs */
stm32_sai_sub_reg_wr(sai, STM_SAI_CLRFR_REGX,
SAI_XCLRFR_MASK, SAI_XCLRFR_MASK);
imr = SAI_XIMR_OVRUDRIE;
if (STM_SAI_IS_CAPTURE(sai)) {
stm32_sai_sub_reg_rd(sai, STM_SAI_CR2_REGX, &cr2);
if (cr2 & SAI_XCR2_MUTECNT_MASK)
imr |= SAI_XIMR_MUTEDETIE;
}
if (sai->master)
imr |= SAI_XIMR_WCKCFGIE;
else
imr |= SAI_XIMR_AFSDETIE | SAI_XIMR_LFSDETIE;
stm32_sai_sub_reg_up(sai, STM_SAI_IMR_REGX,
SAI_XIMR_MASK, imr);
return 0;
}
static int stm32_sai_set_config(struct snd_soc_dai *cpu_dai,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
int cr1, cr1_mask, ret;
/*
* DMA bursts increment is set to 4 words.
* SAI fifo threshold is set to half fifo, to keep enough space
* for DMA incoming bursts.
*/
stm32_sai_sub_reg_wr(sai, STM_SAI_CR2_REGX,
SAI_XCR2_FFLUSH | SAI_XCR2_FTH_MASK,
SAI_XCR2_FFLUSH |
SAI_XCR2_FTH_SET(STM_SAI_FIFO_TH_HALF));
/* DS bits in CR1 not set for SPDIF (size forced to 24 bits).*/
if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
sai->spdif_frm_cnt = 0;
return 0;
}
/* Mode, data format and channel config */
cr1_mask = SAI_XCR1_DS_MASK;
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S8:
cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_8);
break;
case SNDRV_PCM_FORMAT_S16_LE:
cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_16);
break;
case SNDRV_PCM_FORMAT_S32_LE:
cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_32);
break;
default:
dev_err(cpu_dai->dev, "Data format not supported\n");
return -EINVAL;
}
cr1_mask |= SAI_XCR1_MONO;
if ((sai->slots == 2) && (params_channels(params) == 1))
cr1 |= SAI_XCR1_MONO;
ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, cr1_mask, cr1);
if (ret < 0) {
dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
return ret;
}
return 0;
}
static int stm32_sai_set_slots(struct snd_soc_dai *cpu_dai)
{
struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
int slotr, slot_sz;
stm32_sai_sub_reg_rd(sai, STM_SAI_SLOTR_REGX, &slotr);
/*
* If SLOTSZ is set to auto in SLOTR, align slot width on data size
* By default slot width = data size, if not forced from DT
*/
slot_sz = slotr & SAI_XSLOTR_SLOTSZ_MASK;
if (slot_sz == SAI_XSLOTR_SLOTSZ_SET(SAI_SLOT_SIZE_AUTO))
sai->slot_width = sai->data_size;
if (sai->slot_width < sai->data_size) {
dev_err(cpu_dai->dev,
"Data size %d larger than slot width\n",
sai->data_size);
return -EINVAL;
}
/* Slot number is set to 2, if not specified in DT */
if (!sai->slots)
sai->slots = 2;
/* The number of slots in the audio frame is equal to NBSLOT[3:0] + 1*/
stm32_sai_sub_reg_up(sai, STM_SAI_SLOTR_REGX,
SAI_XSLOTR_NBSLOT_MASK,
SAI_XSLOTR_NBSLOT_SET((sai->slots - 1)));
/* Set default slots mask if not already set from DT */
if (!(slotr & SAI_XSLOTR_SLOTEN_MASK)) {
sai->slot_mask = (1 << sai->slots) - 1;
stm32_sai_sub_reg_up(sai,
STM_SAI_SLOTR_REGX, SAI_XSLOTR_SLOTEN_MASK,
SAI_XSLOTR_SLOTEN_SET(sai->slot_mask));
}
dev_dbg(cpu_dai->dev, "Slots %d, slot width %d\n",
sai->slots, sai->slot_width);
return 0;
}
static void stm32_sai_set_frame(struct snd_soc_dai *cpu_dai)
{
struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
int fs_active, offset, format;
int frcr, frcr_mask;
format = sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
sai->fs_length = sai->slot_width * sai->slots;
fs_active = sai->fs_length / 2;
if ((format == SND_SOC_DAIFMT_DSP_A) ||
(format == SND_SOC_DAIFMT_DSP_B))
fs_active = 1;
frcr = SAI_XFRCR_FRL_SET((sai->fs_length - 1));
frcr |= SAI_XFRCR_FSALL_SET((fs_active - 1));
frcr_mask = SAI_XFRCR_FRL_MASK | SAI_XFRCR_FSALL_MASK;
dev_dbg(cpu_dai->dev, "Frame length %d, frame active %d\n",
sai->fs_length, fs_active);
stm32_sai_sub_reg_up(sai, STM_SAI_FRCR_REGX, frcr_mask, frcr);
if ((sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_LSB) {
offset = sai->slot_width - sai->data_size;
stm32_sai_sub_reg_up(sai, STM_SAI_SLOTR_REGX,
SAI_XSLOTR_FBOFF_MASK,
SAI_XSLOTR_FBOFF_SET(offset));
}
}
static void stm32_sai_init_iec958_status(struct stm32_sai_sub_data *sai)
{
unsigned char *cs = sai->iec958.status;
cs[0] = IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_NONE;
cs[1] = IEC958_AES1_CON_GENERAL;
cs[2] = IEC958_AES2_CON_SOURCE_UNSPEC | IEC958_AES2_CON_CHANNEL_UNSPEC;
cs[3] = IEC958_AES3_CON_CLOCK_1000PPM | IEC958_AES3_CON_FS_NOTID;
}
static void stm32_sai_set_iec958_status(struct stm32_sai_sub_data *sai,
struct snd_pcm_runtime *runtime)
{
if (!runtime)
return;
/* Force the sample rate according to runtime rate */
mutex_lock(&sai->ctrl_lock);
switch (runtime->rate) {
case 22050:
sai->iec958.status[3] = IEC958_AES3_CON_FS_22050;
break;
case 44100:
sai->iec958.status[3] = IEC958_AES3_CON_FS_44100;
break;
case 88200:
sai->iec958.status[3] = IEC958_AES3_CON_FS_88200;
break;
case 176400:
sai->iec958.status[3] = IEC958_AES3_CON_FS_176400;
break;
case 24000:
sai->iec958.status[3] = IEC958_AES3_CON_FS_24000;
break;
case 48000:
sai->iec958.status[3] = IEC958_AES3_CON_FS_48000;
break;
case 96000:
sai->iec958.status[3] = IEC958_AES3_CON_FS_96000;
break;
case 192000:
sai->iec958.status[3] = IEC958_AES3_CON_FS_192000;
break;
case 32000:
sai->iec958.status[3] = IEC958_AES3_CON_FS_32000;
break;
default:
sai->iec958.status[3] = IEC958_AES3_CON_FS_NOTID;
break;
}
mutex_unlock(&sai->ctrl_lock);
}
static int stm32_sai_configure_clock(struct snd_soc_dai *cpu_dai,
struct snd_pcm_hw_params *params)
{
struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
int div = 0, cr1 = 0;
int sai_clk_rate, mclk_ratio, den;
unsigned int rate = params_rate(params);
int ret;
if (!sai->sai_mclk) {
ret = stm32_sai_set_parent_clock(sai, rate);
if (ret)
return ret;
}
sai_clk_rate = clk_get_rate(sai->sai_ck);
if (STM_SAI_IS_F4(sai->pdata)) {
/* mclk on (NODIV=0)
* mclk_rate = 256 * fs
* MCKDIV = 0 if sai_ck < 3/2 * mclk_rate
* MCKDIV = sai_ck / (2 * mclk_rate) otherwise
* mclk off (NODIV=1)
* MCKDIV ignored. sck = sai_ck
*/
if (!sai->mclk_rate)
return 0;
if (2 * sai_clk_rate >= 3 * sai->mclk_rate) {
div = stm32_sai_get_clk_div(sai, sai_clk_rate,
2 * sai->mclk_rate);
if (div < 0)
return div;
}
} else {
/*
* TDM mode :
* mclk on
* MCKDIV = sai_ck / (ws x 256) (NOMCK=0. OSR=0)
* MCKDIV = sai_ck / (ws x 512) (NOMCK=0. OSR=1)
* mclk off
* MCKDIV = sai_ck / (frl x ws) (NOMCK=1)
* Note: NOMCK/NODIV correspond to same bit.
*/
if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
div = stm32_sai_get_clk_div(sai, sai_clk_rate,
rate * 128);
if (div < 0)
return div;
} else {
if (sai->mclk_rate) {
mclk_ratio = sai->mclk_rate / rate;
if (mclk_ratio == 512) {
cr1 = SAI_XCR1_OSR;
} else if (mclk_ratio != 256) {
dev_err(cpu_dai->dev,
"Wrong mclk ratio %d\n",
mclk_ratio);
return -EINVAL;
}
stm32_sai_sub_reg_up(sai,
STM_SAI_CR1_REGX,
SAI_XCR1_OSR, cr1);
div = stm32_sai_get_clk_div(sai, sai_clk_rate,
sai->mclk_rate);
if (div < 0)
return div;
} else {
/* mclk-fs not set, master clock not active */
den = sai->fs_length * params_rate(params);
div = stm32_sai_get_clk_div(sai, sai_clk_rate,
den);
if (div < 0)
return div;
}
}
}
return stm32_sai_set_clk_div(sai, div);
}
static int stm32_sai_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *cpu_dai)
{
struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
int ret;
sai->data_size = params_width(params);
if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
/* Rate not already set in runtime structure */
substream->runtime->rate = params_rate(params);
stm32_sai_set_iec958_status(sai, substream->runtime);
} else {
ret = stm32_sai_set_slots(cpu_dai);
if (ret < 0)
return ret;
stm32_sai_set_frame(cpu_dai);
}
ret = stm32_sai_set_config(cpu_dai, substream, params);
if (ret)
return ret;
if (sai->master)
ret = stm32_sai_configure_clock(cpu_dai, params);
return ret;
}
static int stm32_sai_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *cpu_dai)
{
struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
int ret;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
dev_dbg(cpu_dai->dev, "Enable DMA and SAI\n");
stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX,
SAI_XCR1_DMAEN, SAI_XCR1_DMAEN);
/* Enable SAI */
ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX,
SAI_XCR1_SAIEN, SAI_XCR1_SAIEN);
if (ret < 0)
dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
break;
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
case SNDRV_PCM_TRIGGER_STOP:
dev_dbg(cpu_dai->dev, "Disable DMA and SAI\n");
stm32_sai_sub_reg_up(sai, STM_SAI_IMR_REGX,
SAI_XIMR_MASK, 0);
stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX,
SAI_XCR1_SAIEN,
(unsigned int)~SAI_XCR1_SAIEN);
ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX,
SAI_XCR1_DMAEN,
(unsigned int)~SAI_XCR1_DMAEN);
if (ret < 0)
dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
if (STM_SAI_PROTOCOL_IS_SPDIF(sai))
sai->spdif_frm_cnt = 0;
break;
default:
return -EINVAL;
}
return ret;
}
static void stm32_sai_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *cpu_dai)
{
struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
unsigned long flags;
stm32_sai_sub_reg_up(sai, STM_SAI_IMR_REGX, SAI_XIMR_MASK, 0);
clk_disable_unprepare(sai->sai_ck);
spin_lock_irqsave(&sai->irq_lock, flags);
sai->substream = NULL;
spin_unlock_irqrestore(&sai->irq_lock, flags);
}
static int stm32_sai_pcm_new(struct snd_soc_pcm_runtime *rtd,
struct snd_soc_dai *cpu_dai)
{
struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev);
struct snd_kcontrol_new knew = iec958_ctls;
if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
dev_dbg(&sai->pdev->dev, "%s: register iec controls", __func__);
knew.device = rtd->pcm->device;
return snd_ctl_add(rtd->pcm->card, snd_ctl_new1(&knew, sai));
}
return 0;
}
static int stm32_sai_dai_probe(struct snd_soc_dai *cpu_dai)
{
struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev);
int cr1 = 0, cr1_mask, ret;
sai->cpu_dai = cpu_dai;
sai->dma_params.addr = (dma_addr_t)(sai->phys_addr + STM_SAI_DR_REGX);
/*
* DMA supports 4, 8 or 16 burst sizes. Burst size 4 is the best choice,
* as it allows bytes, half-word and words transfers. (See DMA fifos
* constraints).
*/
sai->dma_params.maxburst = 4;
if (sai->pdata->conf.fifo_size < 8)
sai->dma_params.maxburst = 1;
/* Buswidth will be set by framework at runtime */
sai->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
if (STM_SAI_IS_PLAYBACK(sai))
snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params, NULL);
else
snd_soc_dai_init_dma_data(cpu_dai, NULL, &sai->dma_params);
/* Next settings are not relevant for spdif mode */
if (STM_SAI_PROTOCOL_IS_SPDIF(sai))
return 0;
cr1_mask = SAI_XCR1_RX_TX;
if (STM_SAI_IS_CAPTURE(sai))
cr1 |= SAI_XCR1_RX_TX;
/* Configure synchronization */
if (sai->sync == SAI_SYNC_EXTERNAL) {
/* Configure synchro client and provider */
ret = sai->pdata->set_sync(sai->pdata, sai->np_sync_provider,
sai->synco, sai->synci);
if (ret)
return ret;
}
cr1_mask |= SAI_XCR1_SYNCEN_MASK;
cr1 |= SAI_XCR1_SYNCEN_SET(sai->sync);
return stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, cr1_mask, cr1);
}
static const struct snd_soc_dai_ops stm32_sai_pcm_dai_ops = {
.probe = stm32_sai_dai_probe,
.set_sysclk = stm32_sai_set_sysclk,
.set_fmt = stm32_sai_set_dai_fmt,
.set_tdm_slot = stm32_sai_set_dai_tdm_slot,
.startup = stm32_sai_startup,
.hw_params = stm32_sai_hw_params,
.trigger = stm32_sai_trigger,
.shutdown = stm32_sai_shutdown,
.pcm_new = stm32_sai_pcm_new,
};
static const struct snd_soc_dai_ops stm32_sai_pcm_dai_ops2 = {
.probe = stm32_sai_dai_probe,
.set_sysclk = stm32_sai_set_sysclk,
.set_fmt = stm32_sai_set_dai_fmt,
.set_tdm_slot = stm32_sai_set_dai_tdm_slot,
.startup = stm32_sai_startup,
.hw_params = stm32_sai_hw_params,
.trigger = stm32_sai_trigger,
.shutdown = stm32_sai_shutdown,
};
static int stm32_sai_pcm_process_spdif(struct snd_pcm_substream *substream,
int channel, unsigned long hwoff,
unsigned long bytes)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev);
int *ptr = (int *)(runtime->dma_area + hwoff +
channel * (runtime->dma_bytes / runtime->channels));
ssize_t cnt = bytes_to_samples(runtime, bytes);
unsigned int frm_cnt = sai->spdif_frm_cnt;
unsigned int byte;
unsigned int mask;
do {
*ptr = ((*ptr >> 8) & 0x00ffffff);
/* Set channel status bit */
byte = frm_cnt >> 3;
mask = 1 << (frm_cnt - (byte << 3));
if (sai->iec958.status[byte] & mask)
*ptr |= 0x04000000;
ptr++;
if (!(cnt % 2))
frm_cnt++;
if (frm_cnt == SAI_IEC60958_BLOCK_FRAMES)
frm_cnt = 0;
} while (--cnt);
sai->spdif_frm_cnt = frm_cnt;
return 0;
}
/* No support of mmap in S/PDIF mode */
static const struct snd_pcm_hardware stm32_sai_pcm_hw_spdif = {
.info = SNDRV_PCM_INFO_INTERLEAVED,
.buffer_bytes_max = 8 * PAGE_SIZE,
.period_bytes_min = 1024,
.period_bytes_max = PAGE_SIZE,
.periods_min = 2,
.periods_max = 8,
};
static const struct snd_pcm_hardware stm32_sai_pcm_hw = {
.info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP,
.buffer_bytes_max = 8 * PAGE_SIZE,
.period_bytes_min = 1024, /* 5ms at 48kHz */
.period_bytes_max = PAGE_SIZE,
.periods_min = 2,
.periods_max = 8,
};
static struct snd_soc_dai_driver stm32_sai_playback_dai = {
.id = 1, /* avoid call to fmt_single_name() */
.playback = {
.channels_min = 1,
.channels_max = 16,
.rate_min = 8000,
.rate_max = 192000,
.rates = SNDRV_PCM_RATE_CONTINUOUS,
/* DMA does not support 24 bits transfers */
.formats =
SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S32_LE,
},
.ops = &stm32_sai_pcm_dai_ops,
};
static struct snd_soc_dai_driver stm32_sai_capture_dai = {
.id = 1, /* avoid call to fmt_single_name() */
.capture = {
.channels_min = 1,
.channels_max = 16,
.rate_min = 8000,
.rate_max = 192000,
.rates = SNDRV_PCM_RATE_CONTINUOUS,
/* DMA does not support 24 bits transfers */
.formats =
SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S32_LE,
},
.ops = &stm32_sai_pcm_dai_ops2,
};
static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config = {
.pcm_hardware = &stm32_sai_pcm_hw,
.prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
};
static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config_spdif = {
.pcm_hardware = &stm32_sai_pcm_hw_spdif,
.prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
.process = stm32_sai_pcm_process_spdif,
};
static const struct snd_soc_component_driver stm32_component = {
.name = "stm32-sai",
.legacy_dai_naming = 1,
};
static const struct of_device_id stm32_sai_sub_ids[] = {
{ .compatible = "st,stm32-sai-sub-a",
.data = (void *)STM_SAI_A_ID},
{ .compatible = "st,stm32-sai-sub-b",
.data = (void *)STM_SAI_B_ID},
{}
};
MODULE_DEVICE_TABLE(of, stm32_sai_sub_ids);
static int stm32_sai_sub_parse_of(struct platform_device *pdev,
struct stm32_sai_sub_data *sai)
{
struct device_node *np = pdev->dev.of_node;
struct resource *res;
void __iomem *base;
struct of_phandle_args args;
int ret;
if (!np)
return -ENODEV;
base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(base))
return PTR_ERR(base);
sai->phys_addr = res->start;
sai->regmap_config = &stm32_sai_sub_regmap_config_f4;
/* Note: PDM registers not available for sub-block B */
if (STM_SAI_HAS_PDM(sai) && STM_SAI_IS_SUB_A(sai))
sai->regmap_config = &stm32_sai_sub_regmap_config_h7;
/*
* Do not manage peripheral clock through regmap framework as this
* can lead to circular locking issue with sai master clock provider.
* Manage peripheral clock directly in driver instead.
*/
sai->regmap = devm_regmap_init_mmio(&pdev->dev, base,
sai->regmap_config);
if (IS_ERR(sai->regmap))
return dev_err_probe(&pdev->dev, PTR_ERR(sai->regmap),
"Regmap init error\n");
/* Get direction property */
if (of_property_match_string(np, "dma-names", "tx") >= 0) {
sai->dir = SNDRV_PCM_STREAM_PLAYBACK;
} else if (of_property_match_string(np, "dma-names", "rx") >= 0) {
sai->dir = SNDRV_PCM_STREAM_CAPTURE;
} else {
dev_err(&pdev->dev, "Unsupported direction\n");
return -EINVAL;
}
/* Get spdif iec60958 property */
sai->spdif = false;
if (of_property_present(np, "st,iec60958")) {
if (!STM_SAI_HAS_SPDIF(sai) ||
sai->dir == SNDRV_PCM_STREAM_CAPTURE) {
dev_err(&pdev->dev, "S/PDIF IEC60958 not supported\n");
return -EINVAL;
}
stm32_sai_init_iec958_status(sai);
sai->spdif = true;
sai->master = true;
}
/* Get synchronization property */
args.np = NULL;
ret = of_parse_phandle_with_fixed_args(np, "st,sync", 1, 0, &args);
if (ret < 0 && ret != -ENOENT) {
dev_err(&pdev->dev, "Failed to get st,sync property\n");
return ret;
}
sai->sync = SAI_SYNC_NONE;
if (args.np) {
if (args.np == np) {
dev_err(&pdev->dev, "%pOFn sync own reference\n", np);
of_node_put(args.np);
return -EINVAL;
}
sai->np_sync_provider = of_get_parent(args.np);
if (!sai->np_sync_provider) {
dev_err(&pdev->dev, "%pOFn parent node not found\n",
np);
of_node_put(args.np);
return -ENODEV;
}
sai->sync = SAI_SYNC_INTERNAL;
if (sai->np_sync_provider != sai->pdata->pdev->dev.of_node) {
if (!STM_SAI_HAS_EXT_SYNC(sai)) {
dev_err(&pdev->dev,
"External synchro not supported\n");
of_node_put(args.np);
return -EINVAL;
}
sai->sync = SAI_SYNC_EXTERNAL;
sai->synci = args.args[0];
if (sai->synci < 1 ||
(sai->synci > (SAI_GCR_SYNCIN_MAX + 1))) {
dev_err(&pdev->dev, "Wrong SAI index\n");
of_node_put(args.np);
return -EINVAL;
}
if (of_property_match_string(args.np, "compatible",
"st,stm32-sai-sub-a") >= 0)
sai->synco = STM_SAI_SYNC_OUT_A;
if (of_property_match_string(args.np, "compatible",
"st,stm32-sai-sub-b") >= 0)
sai->synco = STM_SAI_SYNC_OUT_B;
if (!sai->synco) {
dev_err(&pdev->dev, "Unknown SAI sub-block\n");
of_node_put(args.np);
return -EINVAL;
}
}
dev_dbg(&pdev->dev, "%s synchronized with %s\n",
pdev->name, args.np->full_name);
}
of_node_put(args.np);
sai->sai_ck = devm_clk_get(&pdev->dev, "sai_ck");
if (IS_ERR(sai->sai_ck))
return dev_err_probe(&pdev->dev, PTR_ERR(sai->sai_ck),
"Missing kernel clock sai_ck\n");
ret = clk_prepare(sai->pdata->pclk);
if (ret < 0)
return ret;
if (STM_SAI_IS_F4(sai->pdata))
return 0;
/* Register mclk provider if requested */
if (of_property_present(np, "#clock-cells")) {
ret = stm32_sai_add_mclk_provider(sai);
if (ret < 0)
return ret;
} else {
sai->sai_mclk = devm_clk_get_optional(&pdev->dev, "MCLK");
if (IS_ERR(sai->sai_mclk))
return PTR_ERR(sai->sai_mclk);
}
return 0;
}
static int stm32_sai_sub_probe(struct platform_device *pdev)
{
struct stm32_sai_sub_data *sai;
const struct of_device_id *of_id;
const struct snd_dmaengine_pcm_config *conf = &stm32_sai_pcm_config;
int ret;
sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
if (!sai)
return -ENOMEM;
of_id = of_match_device(stm32_sai_sub_ids, &pdev->dev);
if (!of_id)
return -EINVAL;
sai->id = (uintptr_t)of_id->data;
sai->pdev = pdev;
mutex_init(&sai->ctrl_lock);
spin_lock_init(&sai->irq_lock);
platform_set_drvdata(pdev, sai);
sai->pdata = dev_get_drvdata(pdev->dev.parent);
if (!sai->pdata) {
dev_err(&pdev->dev, "Parent device data not available\n");
return -EINVAL;
}
ret = stm32_sai_sub_parse_of(pdev, sai);
if (ret)
return ret;
if (STM_SAI_IS_PLAYBACK(sai))
sai->cpu_dai_drv = stm32_sai_playback_dai;
else
sai->cpu_dai_drv = stm32_sai_capture_dai;
sai->cpu_dai_drv.name = dev_name(&pdev->dev);
ret = devm_request_irq(&pdev->dev, sai->pdata->irq, stm32_sai_isr,
IRQF_SHARED, dev_name(&pdev->dev), sai);
if (ret) {
dev_err(&pdev->dev, "IRQ request returned %d\n", ret);
return ret;
}
if (STM_SAI_PROTOCOL_IS_SPDIF(sai))
conf = &stm32_sai_pcm_config_spdif;
ret = snd_dmaengine_pcm_register(&pdev->dev, conf, 0);
if (ret)
return dev_err_probe(&pdev->dev, ret, "Could not register pcm dma\n");
ret = snd_soc_register_component(&pdev->dev, &stm32_component,
&sai->cpu_dai_drv, 1);
if (ret) {
snd_dmaengine_pcm_unregister(&pdev->dev);
return ret;
}
pm_runtime_enable(&pdev->dev);
return 0;
}
static void stm32_sai_sub_remove(struct platform_device *pdev)
{
struct stm32_sai_sub_data *sai = dev_get_drvdata(&pdev->dev);
clk_unprepare(sai->pdata->pclk);
snd_dmaengine_pcm_unregister(&pdev->dev);
snd_soc_unregister_component(&pdev->dev);
pm_runtime_disable(&pdev->dev);
}
#ifdef CONFIG_PM_SLEEP
static int stm32_sai_sub_suspend(struct device *dev)
{
struct stm32_sai_sub_data *sai = dev_get_drvdata(dev);
int ret;
ret = clk_enable(sai->pdata->pclk);
if (ret < 0)
return ret;
regcache_cache_only(sai->regmap, true);
regcache_mark_dirty(sai->regmap);
clk_disable(sai->pdata->pclk);
return 0;
}
static int stm32_sai_sub_resume(struct device *dev)
{
struct stm32_sai_sub_data *sai = dev_get_drvdata(dev);
int ret;
ret = clk_enable(sai->pdata->pclk);
if (ret < 0)
return ret;
regcache_cache_only(sai->regmap, false);
ret = regcache_sync(sai->regmap);
clk_disable(sai->pdata->pclk);
return ret;
}
#endif /* CONFIG_PM_SLEEP */
static const struct dev_pm_ops stm32_sai_sub_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(stm32_sai_sub_suspend, stm32_sai_sub_resume)
};
static struct platform_driver stm32_sai_sub_driver = {
.driver = {
.name = "st,stm32-sai-sub",
.of_match_table = stm32_sai_sub_ids,
.pm = &stm32_sai_sub_pm_ops,
},
.probe = stm32_sai_sub_probe,
.remove_new = stm32_sai_sub_remove,
};
module_platform_driver(stm32_sai_sub_driver);
MODULE_DESCRIPTION("STM32 Soc SAI sub-block Interface");
MODULE_AUTHOR("Olivier Moysan <[email protected]>");
MODULE_ALIAS("platform:st,stm32-sai-sub");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/stm/stm32_sai_sub.c |
// SPDX-License-Identifier: GPL-2.0
/*
* This file is part of STM32 DFSDM ASoC DAI driver
*
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
* Authors: Arnaud Pouliquen <[email protected]>
* Olivier Moysan <[email protected]>
*/
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
#include <linux/iio/iio.h>
#include <linux/iio/consumer.h>
#include <linux/iio/adc/stm32-dfsdm-adc.h>
#include <sound/pcm.h>
#include <sound/soc.h>
#define STM32_ADFSDM_DRV_NAME "stm32-adfsdm"
#define DFSDM_MAX_PERIOD_SIZE (PAGE_SIZE / 2)
#define DFSDM_MAX_PERIODS 6
struct stm32_adfsdm_priv {
struct snd_soc_dai_driver dai_drv;
struct snd_pcm_substream *substream;
struct device *dev;
/* IIO */
struct iio_channel *iio_ch;
struct iio_cb_buffer *iio_cb;
bool iio_active;
/* PCM buffer */
unsigned char *pcm_buff;
unsigned int pos;
struct mutex lock; /* protect against race condition on iio state */
};
static const struct snd_pcm_hardware stm32_adfsdm_pcm_hw = {
.info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER |
SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_PAUSE,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
.channels_min = 1,
.channels_max = 1,
.periods_min = 2,
.periods_max = DFSDM_MAX_PERIODS,
.period_bytes_max = DFSDM_MAX_PERIOD_SIZE,
.buffer_bytes_max = DFSDM_MAX_PERIODS * DFSDM_MAX_PERIOD_SIZE
};
static void stm32_adfsdm_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct stm32_adfsdm_priv *priv = snd_soc_dai_get_drvdata(dai);
mutex_lock(&priv->lock);
if (priv->iio_active) {
iio_channel_stop_all_cb(priv->iio_cb);
priv->iio_active = false;
}
mutex_unlock(&priv->lock);
}
static int stm32_adfsdm_dai_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct stm32_adfsdm_priv *priv = snd_soc_dai_get_drvdata(dai);
int ret;
mutex_lock(&priv->lock);
if (priv->iio_active) {
iio_channel_stop_all_cb(priv->iio_cb);
priv->iio_active = false;
}
ret = iio_write_channel_attribute(priv->iio_ch,
substream->runtime->rate, 0,
IIO_CHAN_INFO_SAMP_FREQ);
if (ret < 0) {
dev_err(dai->dev, "%s: Failed to set %d sampling rate\n",
__func__, substream->runtime->rate);
goto out;
}
if (!priv->iio_active) {
ret = iio_channel_start_all_cb(priv->iio_cb);
if (!ret)
priv->iio_active = true;
else
dev_err(dai->dev, "%s: IIO channel start failed (%d)\n",
__func__, ret);
}
out:
mutex_unlock(&priv->lock);
return ret;
}
static int stm32_adfsdm_set_sysclk(struct snd_soc_dai *dai, int clk_id,
unsigned int freq, int dir)
{
struct stm32_adfsdm_priv *priv = snd_soc_dai_get_drvdata(dai);
ssize_t size;
char str_freq[10];
dev_dbg(dai->dev, "%s: Enter for freq %d\n", __func__, freq);
/* Set IIO frequency if CODEC is master as clock comes from SPI_IN */
snprintf(str_freq, sizeof(str_freq), "%u\n", freq);
size = iio_write_channel_ext_info(priv->iio_ch, "spi_clk_freq",
str_freq, sizeof(str_freq));
if (size != sizeof(str_freq)) {
dev_err(dai->dev, "%s: Failed to set SPI clock\n",
__func__);
return -EINVAL;
}
return 0;
}
static const struct snd_soc_dai_ops stm32_adfsdm_dai_ops = {
.shutdown = stm32_adfsdm_shutdown,
.prepare = stm32_adfsdm_dai_prepare,
.set_sysclk = stm32_adfsdm_set_sysclk,
};
static const struct snd_soc_dai_driver stm32_adfsdm_dai = {
.capture = {
.channels_min = 1,
.channels_max = 1,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S32_LE,
.rates = SNDRV_PCM_RATE_CONTINUOUS,
.rate_min = 8000,
.rate_max = 48000,
},
.ops = &stm32_adfsdm_dai_ops,
};
static const struct snd_soc_component_driver stm32_adfsdm_dai_component = {
.name = "stm32_dfsdm_audio",
.legacy_dai_naming = 1,
};
static void stm32_memcpy_32to16(void *dest, const void *src, size_t n)
{
unsigned int i = 0;
u16 *d = (u16 *)dest, *s = (u16 *)src;
s++;
for (i = n >> 1; i > 0; i--) {
*d++ = *s++;
s++;
}
}
static int stm32_afsdm_pcm_cb(const void *data, size_t size, void *private)
{
struct stm32_adfsdm_priv *priv = private;
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(priv->substream);
u8 *pcm_buff = priv->pcm_buff;
u8 *src_buff = (u8 *)data;
unsigned int old_pos = priv->pos;
size_t buff_size = snd_pcm_lib_buffer_bytes(priv->substream);
size_t period_size = snd_pcm_lib_period_bytes(priv->substream);
size_t cur_size, src_size = size;
snd_pcm_format_t format = priv->substream->runtime->format;
if (format == SNDRV_PCM_FORMAT_S16_LE)
src_size >>= 1;
cur_size = src_size;
dev_dbg(rtd->dev, "%s: buff_add :%pK, pos = %d, size = %zu\n",
__func__, &pcm_buff[priv->pos], priv->pos, src_size);
if ((priv->pos + src_size) > buff_size) {
if (format == SNDRV_PCM_FORMAT_S16_LE)
stm32_memcpy_32to16(&pcm_buff[priv->pos], src_buff,
buff_size - priv->pos);
else
memcpy(&pcm_buff[priv->pos], src_buff,
buff_size - priv->pos);
cur_size -= buff_size - priv->pos;
priv->pos = 0;
}
if (format == SNDRV_PCM_FORMAT_S16_LE)
stm32_memcpy_32to16(&pcm_buff[priv->pos],
&src_buff[src_size - cur_size], cur_size);
else
memcpy(&pcm_buff[priv->pos], &src_buff[src_size - cur_size],
cur_size);
priv->pos = (priv->pos + cur_size) % buff_size;
if (cur_size != src_size || (old_pos && (old_pos % period_size < size)))
snd_pcm_period_elapsed(priv->substream);
return 0;
}
static int stm32_adfsdm_trigger(struct snd_soc_component *component,
struct snd_pcm_substream *substream, int cmd)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct stm32_adfsdm_priv *priv =
snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
priv->pos = 0;
return stm32_dfsdm_get_buff_cb(priv->iio_ch->indio_dev,
stm32_afsdm_pcm_cb, priv);
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_STOP:
return stm32_dfsdm_release_buff_cb(priv->iio_ch->indio_dev);
}
return -EINVAL;
}
static int stm32_adfsdm_pcm_open(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct stm32_adfsdm_priv *priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
int ret;
ret = snd_soc_set_runtime_hwparams(substream, &stm32_adfsdm_pcm_hw);
if (!ret)
priv->substream = substream;
return ret;
}
static int stm32_adfsdm_pcm_close(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct stm32_adfsdm_priv *priv =
snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
priv->substream = NULL;
return 0;
}
static snd_pcm_uframes_t stm32_adfsdm_pcm_pointer(
struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct stm32_adfsdm_priv *priv =
snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
return bytes_to_frames(substream->runtime, priv->pos);
}
static int stm32_adfsdm_pcm_hw_params(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct stm32_adfsdm_priv *priv =
snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
priv->pcm_buff = substream->runtime->dma_area;
return iio_channel_cb_set_buffer_watermark(priv->iio_cb,
params_period_size(params));
}
static int stm32_adfsdm_pcm_new(struct snd_soc_component *component,
struct snd_soc_pcm_runtime *rtd)
{
struct snd_pcm *pcm = rtd->pcm;
struct stm32_adfsdm_priv *priv =
snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
unsigned int size = DFSDM_MAX_PERIODS * DFSDM_MAX_PERIOD_SIZE;
snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
priv->dev, size, size);
return 0;
}
static int stm32_adfsdm_dummy_cb(const void *data, void *private)
{
/*
* This dummy callback is requested by iio_channel_get_all_cb() API,
* but the stm32_dfsdm_get_buff_cb() API is used instead, to optimize
* DMA transfers.
*/
return 0;
}
static void stm32_adfsdm_cleanup(void *data)
{
iio_channel_release_all_cb(data);
}
static struct snd_soc_component_driver stm32_adfsdm_soc_platform = {
.open = stm32_adfsdm_pcm_open,
.close = stm32_adfsdm_pcm_close,
.hw_params = stm32_adfsdm_pcm_hw_params,
.trigger = stm32_adfsdm_trigger,
.pointer = stm32_adfsdm_pcm_pointer,
.pcm_construct = stm32_adfsdm_pcm_new,
};
static const struct of_device_id stm32_adfsdm_of_match[] = {
{.compatible = "st,stm32h7-dfsdm-dai"},
{}
};
MODULE_DEVICE_TABLE(of, stm32_adfsdm_of_match);
static int stm32_adfsdm_probe(struct platform_device *pdev)
{
struct stm32_adfsdm_priv *priv;
struct snd_soc_component *component;
int ret;
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->dev = &pdev->dev;
priv->dai_drv = stm32_adfsdm_dai;
mutex_init(&priv->lock);
dev_set_drvdata(&pdev->dev, priv);
ret = devm_snd_soc_register_component(&pdev->dev,
&stm32_adfsdm_dai_component,
&priv->dai_drv, 1);
if (ret < 0)
return ret;
/* Associate iio channel */
priv->iio_ch = devm_iio_channel_get_all(&pdev->dev);
if (IS_ERR(priv->iio_ch))
return PTR_ERR(priv->iio_ch);
priv->iio_cb = iio_channel_get_all_cb(&pdev->dev, &stm32_adfsdm_dummy_cb, NULL);
if (IS_ERR(priv->iio_cb))
return PTR_ERR(priv->iio_cb);
ret = devm_add_action_or_reset(&pdev->dev, stm32_adfsdm_cleanup, priv->iio_cb);
if (ret < 0) {
dev_err(&pdev->dev, "Unable to add action\n");
return ret;
}
component = devm_kzalloc(&pdev->dev, sizeof(*component), GFP_KERNEL);
if (!component)
return -ENOMEM;
ret = snd_soc_component_initialize(component,
&stm32_adfsdm_soc_platform,
&pdev->dev);
if (ret < 0)
return ret;
#ifdef CONFIG_DEBUG_FS
component->debugfs_prefix = "pcm";
#endif
ret = snd_soc_add_component(component, NULL, 0);
if (ret < 0) {
dev_err(&pdev->dev, "%s: Failed to register PCM platform\n",
__func__);
return ret;
}
pm_runtime_enable(&pdev->dev);
return ret;
}
static void stm32_adfsdm_remove(struct platform_device *pdev)
{
snd_soc_unregister_component(&pdev->dev);
pm_runtime_disable(&pdev->dev);
}
static struct platform_driver stm32_adfsdm_driver = {
.driver = {
.name = STM32_ADFSDM_DRV_NAME,
.of_match_table = stm32_adfsdm_of_match,
},
.probe = stm32_adfsdm_probe,
.remove_new = stm32_adfsdm_remove,
};
module_platform_driver(stm32_adfsdm_driver);
MODULE_DESCRIPTION("stm32 DFSDM DAI driver");
MODULE_AUTHOR("Arnaud Pouliquen <[email protected]>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" STM32_ADFSDM_DRV_NAME);
| linux-master | sound/soc/stm/stm32_adfsdm.c |
// SPDX-License-Identifier: GPL-2.0
//
// mt8192-mt6359-rt1015-rt5682.c --
// MT8192-MT6359-RT1015-RT6358 ALSA SoC machine driver
//
// Copyright (c) 2020 MediaTek Inc.
// Author: Jiaxin Yu <[email protected]>
//
#include <linux/input.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/pm_runtime.h>
#include <sound/jack.h>
#include <sound/pcm_params.h>
#include <sound/rt5682.h>
#include <sound/soc.h>
#include "../../codecs/mt6359.h"
#include "../../codecs/rt1015.h"
#include "../../codecs/rt5682.h"
#include "../common/mtk-afe-platform-driver.h"
#include "mt8192-afe-common.h"
#include "mt8192-afe-clk.h"
#include "mt8192-afe-gpio.h"
#define DRIVER_NAME "mt8192_mt6359"
#define RT1015_CODEC_DAI "rt1015-aif"
#define RT1015_DEV0_NAME "rt1015.1-0028"
#define RT1015_DEV1_NAME "rt1015.1-0029"
#define RT1015_RT5682_CARD_NAME "mt8192_mt6359_rt1015_rt5682"
#define RT1015P_RT5682_CARD_NAME "mt8192_mt6359_rt1015p_rt5682"
#define RT1015P_RT5682S_CARD_NAME "mt8192_mt6359_rt1015p_rt5682s"
#define RT1015_RT5682_OF_NAME "mediatek,mt8192_mt6359_rt1015_rt5682"
#define RT1015P_RT5682_OF_NAME "mediatek,mt8192_mt6359_rt1015p_rt5682"
#define RT1015P_RT5682S_OF_NAME "mediatek,mt8192_mt6359_rt1015p_rt5682s"
struct mt8192_mt6359_priv {
struct snd_soc_jack headset_jack;
struct snd_soc_jack hdmi_jack;
};
/* Headset jack detection DAPM pins */
static struct snd_soc_jack_pin mt8192_jack_pins[] = {
{
.pin = "Headphone Jack",
.mask = SND_JACK_HEADPHONE,
},
{
.pin = "Headset Mic",
.mask = SND_JACK_MICROPHONE,
},
};
static int mt8192_rt1015_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_card *card = rtd->card;
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct snd_soc_dai *codec_dai;
unsigned int rate = params_rate(params);
unsigned int mclk_fs_ratio = 128;
unsigned int mclk_fs = rate * mclk_fs_ratio;
int ret, i;
for_each_rtd_codec_dais(rtd, i, codec_dai) {
ret = snd_soc_dai_set_pll(codec_dai, 0,
RT1015_PLL_S_BCLK,
params_rate(params) * 64,
params_rate(params) * 256);
if (ret) {
dev_err(card->dev, "failed to set pll\n");
return ret;
}
ret = snd_soc_dai_set_sysclk(codec_dai,
RT1015_SCLK_S_PLL,
params_rate(params) * 256,
SND_SOC_CLOCK_IN);
if (ret) {
dev_err(card->dev, "failed to set sysclk\n");
return ret;
}
}
return snd_soc_dai_set_sysclk(cpu_dai, 0, mclk_fs, SND_SOC_CLOCK_OUT);
}
static int mt8192_rt5682x_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_card *card = rtd->card;
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
unsigned int rate = params_rate(params);
unsigned int mclk_fs_ratio = 128;
unsigned int mclk_fs = rate * mclk_fs_ratio;
int bitwidth;
int ret;
bitwidth = snd_pcm_format_width(params_format(params));
if (bitwidth < 0) {
dev_err(card->dev, "invalid bit width: %d\n", bitwidth);
return bitwidth;
}
ret = snd_soc_dai_set_tdm_slot(codec_dai, 0x00, 0x0, 0x2, bitwidth);
if (ret) {
dev_err(card->dev, "failed to set tdm slot\n");
return ret;
}
ret = snd_soc_dai_set_pll(codec_dai, RT5682_PLL1,
RT5682_PLL1_S_BCLK1,
params_rate(params) * 64,
params_rate(params) * 512);
if (ret) {
dev_err(card->dev, "failed to set pll\n");
return ret;
}
ret = snd_soc_dai_set_sysclk(codec_dai,
RT5682_SCLK_S_PLL1,
params_rate(params) * 512,
SND_SOC_CLOCK_IN);
if (ret) {
dev_err(card->dev, "failed to set sysclk\n");
return ret;
}
return snd_soc_dai_set_sysclk(cpu_dai, 0, mclk_fs, SND_SOC_CLOCK_OUT);
}
static const struct snd_soc_ops mt8192_rt1015_i2s_ops = {
.hw_params = mt8192_rt1015_i2s_hw_params,
};
static const struct snd_soc_ops mt8192_rt5682x_i2s_ops = {
.hw_params = mt8192_rt5682x_i2s_hw_params,
};
static int mt8192_mt6359_mtkaif_calibration(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_component *cmpnt_afe =
snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
struct snd_soc_component *cmpnt_codec =
asoc_rtd_to_codec(rtd, 0)->component;
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt_afe);
struct mt8192_afe_private *afe_priv = afe->platform_priv;
int phase;
unsigned int monitor;
int test_done_1, test_done_2, test_done_3;
int cycle_1, cycle_2, cycle_3;
int prev_cycle_1, prev_cycle_2, prev_cycle_3;
int chosen_phase_1, chosen_phase_2, chosen_phase_3;
int counter;
int mtkaif_calib_ok;
pm_runtime_get_sync(afe->dev);
mt8192_afe_gpio_request(afe->dev, true, MT8192_DAI_ADDA, 1);
mt8192_afe_gpio_request(afe->dev, true, MT8192_DAI_ADDA, 0);
mt8192_afe_gpio_request(afe->dev, true, MT8192_DAI_ADDA_CH34, 1);
mt8192_afe_gpio_request(afe->dev, true, MT8192_DAI_ADDA_CH34, 0);
mt6359_mtkaif_calibration_enable(cmpnt_codec);
/* set clock protocol 2 */
regmap_update_bits(afe->regmap, AFE_AUD_PAD_TOP, 0xff, 0x38);
regmap_update_bits(afe->regmap, AFE_AUD_PAD_TOP, 0xff, 0x39);
/* set test type to synchronizer pulse */
regmap_update_bits(afe_priv->topckgen,
CKSYS_AUD_TOP_CFG, 0xffff, 0x4);
mtkaif_calib_ok = true;
afe_priv->mtkaif_calibration_num_phase = 42; /* mt6359: 0 ~ 42 */
afe_priv->mtkaif_chosen_phase[0] = -1;
afe_priv->mtkaif_chosen_phase[1] = -1;
afe_priv->mtkaif_chosen_phase[2] = -1;
for (phase = 0;
phase <= afe_priv->mtkaif_calibration_num_phase &&
mtkaif_calib_ok;
phase++) {
mt6359_set_mtkaif_calibration_phase(cmpnt_codec,
phase, phase, phase);
regmap_update_bits(afe_priv->topckgen,
CKSYS_AUD_TOP_CFG, 0x1, 0x1);
test_done_1 = 0;
test_done_2 = 0;
test_done_3 = 0;
cycle_1 = -1;
cycle_2 = -1;
cycle_3 = -1;
counter = 0;
while (test_done_1 == 0 ||
test_done_2 == 0 ||
test_done_3 == 0) {
regmap_read(afe_priv->topckgen,
CKSYS_AUD_TOP_MON, &monitor);
test_done_1 = (monitor >> 28) & 0x1;
test_done_2 = (monitor >> 29) & 0x1;
test_done_3 = (monitor >> 30) & 0x1;
if (test_done_1 == 1)
cycle_1 = monitor & 0xf;
if (test_done_2 == 1)
cycle_2 = (monitor >> 4) & 0xf;
if (test_done_3 == 1)
cycle_3 = (monitor >> 8) & 0xf;
/* handle if never test done */
if (++counter > 10000) {
dev_err(afe->dev, "%s(), test fail, cycle_1 %d, cycle_2 %d, cycle_3 %d, monitor 0x%x\n",
__func__,
cycle_1, cycle_2, cycle_3, monitor);
mtkaif_calib_ok = false;
break;
}
}
if (phase == 0) {
prev_cycle_1 = cycle_1;
prev_cycle_2 = cycle_2;
prev_cycle_3 = cycle_3;
}
if (cycle_1 != prev_cycle_1 &&
afe_priv->mtkaif_chosen_phase[0] < 0) {
afe_priv->mtkaif_chosen_phase[0] = phase - 1;
afe_priv->mtkaif_phase_cycle[0] = prev_cycle_1;
}
if (cycle_2 != prev_cycle_2 &&
afe_priv->mtkaif_chosen_phase[1] < 0) {
afe_priv->mtkaif_chosen_phase[1] = phase - 1;
afe_priv->mtkaif_phase_cycle[1] = prev_cycle_2;
}
if (cycle_3 != prev_cycle_3 &&
afe_priv->mtkaif_chosen_phase[2] < 0) {
afe_priv->mtkaif_chosen_phase[2] = phase - 1;
afe_priv->mtkaif_phase_cycle[2] = prev_cycle_3;
}
regmap_update_bits(afe_priv->topckgen,
CKSYS_AUD_TOP_CFG, 0x1, 0x0);
if (afe_priv->mtkaif_chosen_phase[0] >= 0 &&
afe_priv->mtkaif_chosen_phase[1] >= 0 &&
afe_priv->mtkaif_chosen_phase[2] >= 0)
break;
}
if (afe_priv->mtkaif_chosen_phase[0] < 0)
chosen_phase_1 = 0;
else
chosen_phase_1 = afe_priv->mtkaif_chosen_phase[0];
if (afe_priv->mtkaif_chosen_phase[1] < 0)
chosen_phase_2 = 0;
else
chosen_phase_2 = afe_priv->mtkaif_chosen_phase[1];
if (afe_priv->mtkaif_chosen_phase[2] < 0)
chosen_phase_3 = 0;
else
chosen_phase_3 = afe_priv->mtkaif_chosen_phase[2];
mt6359_set_mtkaif_calibration_phase(cmpnt_codec,
chosen_phase_1,
chosen_phase_2,
chosen_phase_3);
/* disable rx fifo */
regmap_update_bits(afe->regmap, AFE_AUD_PAD_TOP, 0xff, 0x38);
mt6359_mtkaif_calibration_disable(cmpnt_codec);
mt8192_afe_gpio_request(afe->dev, false, MT8192_DAI_ADDA, 1);
mt8192_afe_gpio_request(afe->dev, false, MT8192_DAI_ADDA, 0);
mt8192_afe_gpio_request(afe->dev, false, MT8192_DAI_ADDA_CH34, 1);
mt8192_afe_gpio_request(afe->dev, false, MT8192_DAI_ADDA_CH34, 0);
pm_runtime_put(afe->dev);
dev_dbg(afe->dev, "%s(), mtkaif_chosen_phase[0/1/2]:%d/%d/%d\n",
__func__,
afe_priv->mtkaif_chosen_phase[0],
afe_priv->mtkaif_chosen_phase[1],
afe_priv->mtkaif_chosen_phase[2]);
return 0;
}
static int mt8192_mt6359_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_component *cmpnt_afe =
snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
struct snd_soc_component *cmpnt_codec =
asoc_rtd_to_codec(rtd, 0)->component;
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt_afe);
struct mt8192_afe_private *afe_priv = afe->platform_priv;
/* set mtkaif protocol */
mt6359_set_mtkaif_protocol(cmpnt_codec,
MT6359_MTKAIF_PROTOCOL_2_CLK_P2);
afe_priv->mtkaif_protocol = MTKAIF_PROTOCOL_2_CLK_P2;
/* mtkaif calibration */
mt8192_mt6359_mtkaif_calibration(rtd);
return 0;
}
static int mt8192_rt5682_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_component *cmpnt_afe =
snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt_afe);
struct snd_soc_component *cmpnt_codec =
asoc_rtd_to_codec(rtd, 0)->component;
struct mt8192_mt6359_priv *priv = snd_soc_card_get_drvdata(rtd->card);
struct snd_soc_jack *jack = &priv->headset_jack;
int ret;
ret = mt8192_dai_i2s_set_share(afe, "I2S8", "I2S9");
if (ret) {
dev_err(rtd->dev, "Failed to set up shared clocks\n");
return ret;
}
ret = snd_soc_card_jack_new_pins(rtd->card, "Headset Jack",
SND_JACK_HEADSET | SND_JACK_BTN_0 |
SND_JACK_BTN_1 | SND_JACK_BTN_2 |
SND_JACK_BTN_3,
jack, mt8192_jack_pins,
ARRAY_SIZE(mt8192_jack_pins));
if (ret) {
dev_err(rtd->dev, "Headset Jack creation failed: %d\n", ret);
return ret;
}
snd_jack_set_key(jack->jack, SND_JACK_BTN_0, KEY_PLAYPAUSE);
snd_jack_set_key(jack->jack, SND_JACK_BTN_1, KEY_VOICECOMMAND);
snd_jack_set_key(jack->jack, SND_JACK_BTN_2, KEY_VOLUMEUP);
snd_jack_set_key(jack->jack, SND_JACK_BTN_3, KEY_VOLUMEDOWN);
return snd_soc_component_set_jack(cmpnt_codec, jack, NULL);
};
static int mt8192_mt6359_hdmi_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_component *cmpnt_codec =
asoc_rtd_to_codec(rtd, 0)->component;
struct mt8192_mt6359_priv *priv = snd_soc_card_get_drvdata(rtd->card);
int ret;
ret = snd_soc_card_jack_new(rtd->card, "HDMI Jack", SND_JACK_LINEOUT,
&priv->hdmi_jack);
if (ret) {
dev_err(rtd->dev, "HDMI Jack creation failed: %d\n", ret);
return ret;
}
return snd_soc_component_set_jack(cmpnt_codec, &priv->hdmi_jack, NULL);
}
static int mt8192_i2s_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
struct snd_pcm_hw_params *params)
{
/* fix BE i2s format to S24_LE, clean param mask first */
snd_mask_reset_range(hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT),
0, (__force unsigned int)SNDRV_PCM_FORMAT_LAST);
params_set_format(params, SNDRV_PCM_FORMAT_S24_LE);
return 0;
}
static int
mt8192_mt6359_cap1_startup(struct snd_pcm_substream *substream)
{
static const unsigned int channels[] = {
1, 2, 4
};
static const struct snd_pcm_hw_constraint_list constraints_channels = {
.count = ARRAY_SIZE(channels),
.list = channels,
.mask = 0,
};
static const unsigned int rates[] = {
8000, 16000, 32000, 48000, 96000, 192000
};
static const struct snd_pcm_hw_constraint_list constraints_rates = {
.count = ARRAY_SIZE(rates),
.list = rates,
.mask = 0,
};
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_pcm_runtime *runtime = substream->runtime;
int ret;
ret = snd_pcm_hw_constraint_list(runtime, 0,
SNDRV_PCM_HW_PARAM_CHANNELS,
&constraints_channels);
if (ret < 0) {
dev_err(rtd->dev, "hw_constraint_list channels failed\n");
return ret;
}
ret = snd_pcm_hw_constraint_list(runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
&constraints_rates);
if (ret < 0) {
dev_err(rtd->dev, "hw_constraint_list rate failed\n");
return ret;
}
return 0;
}
static const struct snd_soc_ops mt8192_mt6359_capture1_ops = {
.startup = mt8192_mt6359_cap1_startup,
};
static int
mt8192_mt6359_rt5682_startup(struct snd_pcm_substream *substream)
{
static const unsigned int channels[] = {
1, 2
};
static const struct snd_pcm_hw_constraint_list constraints_channels = {
.count = ARRAY_SIZE(channels),
.list = channels,
.mask = 0,
};
static const unsigned int rates[] = {
48000
};
static const struct snd_pcm_hw_constraint_list constraints_rates = {
.count = ARRAY_SIZE(rates),
.list = rates,
.mask = 0,
};
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_pcm_runtime *runtime = substream->runtime;
int ret;
ret = snd_pcm_hw_constraint_list(runtime, 0,
SNDRV_PCM_HW_PARAM_CHANNELS,
&constraints_channels);
if (ret < 0) {
dev_err(rtd->dev, "hw_constraint_list channels failed\n");
return ret;
}
ret = snd_pcm_hw_constraint_list(runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
&constraints_rates);
if (ret < 0) {
dev_err(rtd->dev, "hw_constraint_list rate failed\n");
return ret;
}
return 0;
}
static const struct snd_soc_ops mt8192_mt6359_rt5682_ops = {
.startup = mt8192_mt6359_rt5682_startup,
};
/* FE */
SND_SOC_DAILINK_DEFS(playback1,
DAILINK_COMP_ARRAY(COMP_CPU("DL1")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(playback12,
DAILINK_COMP_ARRAY(COMP_CPU("DL12")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(playback2,
DAILINK_COMP_ARRAY(COMP_CPU("DL2")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(playback3,
DAILINK_COMP_ARRAY(COMP_CPU("DL3")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(playback4,
DAILINK_COMP_ARRAY(COMP_CPU("DL4")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(playback5,
DAILINK_COMP_ARRAY(COMP_CPU("DL5")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(playback6,
DAILINK_COMP_ARRAY(COMP_CPU("DL6")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(playback7,
DAILINK_COMP_ARRAY(COMP_CPU("DL7")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(playback8,
DAILINK_COMP_ARRAY(COMP_CPU("DL8")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(playback9,
DAILINK_COMP_ARRAY(COMP_CPU("DL9")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture1,
DAILINK_COMP_ARRAY(COMP_CPU("UL1")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture2,
DAILINK_COMP_ARRAY(COMP_CPU("UL2")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture3,
DAILINK_COMP_ARRAY(COMP_CPU("UL3")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture4,
DAILINK_COMP_ARRAY(COMP_CPU("UL4")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture5,
DAILINK_COMP_ARRAY(COMP_CPU("UL5")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture6,
DAILINK_COMP_ARRAY(COMP_CPU("UL6")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture7,
DAILINK_COMP_ARRAY(COMP_CPU("UL7")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture8,
DAILINK_COMP_ARRAY(COMP_CPU("UL8")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture_mono1,
DAILINK_COMP_ARRAY(COMP_CPU("UL_MONO_1")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture_mono2,
DAILINK_COMP_ARRAY(COMP_CPU("UL_MONO_2")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture_mono3,
DAILINK_COMP_ARRAY(COMP_CPU("UL_MONO_3")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(playback_hdmi,
DAILINK_COMP_ARRAY(COMP_CPU("HDMI")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
/* BE */
SND_SOC_DAILINK_DEFS(primary_codec,
DAILINK_COMP_ARRAY(COMP_CPU("ADDA")),
DAILINK_COMP_ARRAY(COMP_CODEC("mt6359-sound",
"mt6359-snd-codec-aif1"),
COMP_CODEC("dmic-codec",
"dmic-hifi")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(primary_codec_ch34,
DAILINK_COMP_ARRAY(COMP_CPU("ADDA_CH34")),
DAILINK_COMP_ARRAY(COMP_CODEC("mt6359-sound",
"mt6359-snd-codec-aif2")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(ap_dmic,
DAILINK_COMP_ARRAY(COMP_CPU("AP_DMIC")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(ap_dmic_ch34,
DAILINK_COMP_ARRAY(COMP_CPU("AP_DMIC_CH34")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(i2s0,
DAILINK_COMP_ARRAY(COMP_CPU("I2S0")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(i2s1,
DAILINK_COMP_ARRAY(COMP_CPU("I2S1")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(i2s2,
DAILINK_COMP_ARRAY(COMP_CPU("I2S2")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(i2s3,
DAILINK_COMP_ARRAY(COMP_CPU("I2S3")),
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(i2s5,
DAILINK_COMP_ARRAY(COMP_CPU("I2S5")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(i2s6,
DAILINK_COMP_ARRAY(COMP_CPU("I2S6")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(i2s7,
DAILINK_COMP_ARRAY(COMP_CPU("I2S7")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(i2s8,
DAILINK_COMP_ARRAY(COMP_CPU("I2S8")),
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(i2s9,
DAILINK_COMP_ARRAY(COMP_CPU("I2S9")),
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(connsys_i2s,
DAILINK_COMP_ARRAY(COMP_CPU("CONNSYS_I2S")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(pcm1,
DAILINK_COMP_ARRAY(COMP_CPU("PCM 1")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(pcm2,
DAILINK_COMP_ARRAY(COMP_CPU("PCM 2")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(tdm,
DAILINK_COMP_ARRAY(COMP_CPU("TDM")),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "i2s-hifi")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
static struct snd_soc_dai_link mt8192_mt6359_dai_links[] = {
/* Front End DAI links */
{
.name = "Playback_1",
.stream_name = "Playback_1",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(playback1),
},
{
.name = "Playback_12",
.stream_name = "Playback_12",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(playback12),
},
{
.name = "Playback_2",
.stream_name = "Playback_2",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(playback2),
},
{
.name = "Playback_3",
.stream_name = "Playback_3",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
.ops = &mt8192_mt6359_rt5682_ops,
SND_SOC_DAILINK_REG(playback3),
},
{
.name = "Playback_4",
.stream_name = "Playback_4",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(playback4),
},
{
.name = "Playback_5",
.stream_name = "Playback_5",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(playback5),
},
{
.name = "Playback_6",
.stream_name = "Playback_6",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(playback6),
},
{
.name = "Playback_7",
.stream_name = "Playback_7",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(playback7),
},
{
.name = "Playback_8",
.stream_name = "Playback_8",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(playback8),
},
{
.name = "Playback_9",
.stream_name = "Playback_9",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(playback9),
},
{
.name = "Capture_1",
.stream_name = "Capture_1",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_capture = 1,
.ops = &mt8192_mt6359_capture1_ops,
SND_SOC_DAILINK_REG(capture1),
},
{
.name = "Capture_2",
.stream_name = "Capture_2",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_capture = 1,
.ops = &mt8192_mt6359_rt5682_ops,
SND_SOC_DAILINK_REG(capture2),
},
{
.name = "Capture_3",
.stream_name = "Capture_3",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(capture3),
},
{
.name = "Capture_4",
.stream_name = "Capture_4",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(capture4),
},
{
.name = "Capture_5",
.stream_name = "Capture_5",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(capture5),
},
{
.name = "Capture_6",
.stream_name = "Capture_6",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(capture6),
},
{
.name = "Capture_7",
.stream_name = "Capture_7",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(capture7),
},
{
.name = "Capture_8",
.stream_name = "Capture_8",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(capture8),
},
{
.name = "Capture_Mono_1",
.stream_name = "Capture_Mono_1",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(capture_mono1),
},
{
.name = "Capture_Mono_2",
.stream_name = "Capture_Mono_2",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(capture_mono2),
},
{
.name = "Capture_Mono_3",
.stream_name = "Capture_Mono_3",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(capture_mono3),
},
{
.name = "playback_hdmi",
.stream_name = "Playback_HDMI",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(playback_hdmi),
},
/* Back End DAI links */
{
.name = "Primary Codec",
.no_pcm = 1,
.dpcm_playback = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
.init = mt8192_mt6359_init,
SND_SOC_DAILINK_REG(primary_codec),
},
{
.name = "Primary Codec CH34",
.no_pcm = 1,
.dpcm_playback = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(primary_codec_ch34),
},
{
.name = "AP_DMIC",
.no_pcm = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(ap_dmic),
},
{
.name = "AP_DMIC_CH34",
.no_pcm = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(ap_dmic_ch34),
},
{
.name = "I2S0",
.no_pcm = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
.be_hw_params_fixup = mt8192_i2s_hw_params_fixup,
SND_SOC_DAILINK_REG(i2s0),
},
{
.name = "I2S1",
.no_pcm = 1,
.dpcm_playback = 1,
.ignore_suspend = 1,
.be_hw_params_fixup = mt8192_i2s_hw_params_fixup,
SND_SOC_DAILINK_REG(i2s1),
},
{
.name = "I2S2",
.no_pcm = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
.be_hw_params_fixup = mt8192_i2s_hw_params_fixup,
SND_SOC_DAILINK_REG(i2s2),
},
{
.name = "I2S3",
.no_pcm = 1,
.dpcm_playback = 1,
.ignore_suspend = 1,
.be_hw_params_fixup = mt8192_i2s_hw_params_fixup,
SND_SOC_DAILINK_REG(i2s3),
},
{
.name = "I2S5",
.no_pcm = 1,
.dpcm_playback = 1,
.ignore_suspend = 1,
.be_hw_params_fixup = mt8192_i2s_hw_params_fixup,
SND_SOC_DAILINK_REG(i2s5),
},
{
.name = "I2S6",
.no_pcm = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
.be_hw_params_fixup = mt8192_i2s_hw_params_fixup,
SND_SOC_DAILINK_REG(i2s6),
},
{
.name = "I2S7",
.no_pcm = 1,
.dpcm_playback = 1,
.ignore_suspend = 1,
.be_hw_params_fixup = mt8192_i2s_hw_params_fixup,
SND_SOC_DAILINK_REG(i2s7),
},
{
.name = "I2S8",
.no_pcm = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
.init = mt8192_rt5682_init,
.be_hw_params_fixup = mt8192_i2s_hw_params_fixup,
SND_SOC_DAILINK_REG(i2s8),
.ops = &mt8192_rt5682x_i2s_ops,
},
{
.name = "I2S9",
.no_pcm = 1,
.dpcm_playback = 1,
.ignore_suspend = 1,
.be_hw_params_fixup = mt8192_i2s_hw_params_fixup,
SND_SOC_DAILINK_REG(i2s9),
.ops = &mt8192_rt5682x_i2s_ops,
},
{
.name = "CONNSYS_I2S",
.no_pcm = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(connsys_i2s),
},
{
.name = "PCM 1",
.no_pcm = 1,
.dpcm_playback = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(pcm1),
},
{
.name = "PCM 2",
.no_pcm = 1,
.dpcm_playback = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(pcm2),
},
{
.name = "TDM",
.no_pcm = 1,
.dai_fmt = SND_SOC_DAIFMT_DSP_A |
SND_SOC_DAIFMT_IB_NF |
SND_SOC_DAIFMT_CBM_CFM,
.dpcm_playback = 1,
.ignore_suspend = 1,
.be_hw_params_fixup = mt8192_i2s_hw_params_fixup,
.ignore = 1,
.init = mt8192_mt6359_hdmi_init,
SND_SOC_DAILINK_REG(tdm),
},
};
static const struct snd_soc_dapm_widget
mt8192_mt6359_rt1015_rt5682_widgets[] = {
SND_SOC_DAPM_SPK("Left Spk", NULL),
SND_SOC_DAPM_SPK("Right Spk", NULL),
SND_SOC_DAPM_HP("Headphone Jack", NULL),
SND_SOC_DAPM_MIC("Headset Mic", NULL),
SND_SOC_DAPM_OUTPUT("TDM Out"),
};
static const struct snd_soc_dapm_route mt8192_mt6359_rt1015_rt5682_routes[] = {
/* speaker */
{ "Left Spk", NULL, "Left SPO" },
{ "Right Spk", NULL, "Right SPO" },
/* headset */
{ "Headphone Jack", NULL, "HPOL" },
{ "Headphone Jack", NULL, "HPOR" },
{ "IN1P", NULL, "Headset Mic" },
/* TDM */
{ "TDM Out", NULL, "TDM" },
};
static const struct snd_kcontrol_new mt8192_mt6359_rt1015_rt5682_controls[] = {
SOC_DAPM_PIN_SWITCH("Left Spk"),
SOC_DAPM_PIN_SWITCH("Right Spk"),
SOC_DAPM_PIN_SWITCH("Headphone Jack"),
SOC_DAPM_PIN_SWITCH("Headset Mic"),
};
static struct snd_soc_codec_conf rt1015_amp_conf[] = {
{
.dlc = COMP_CODEC_CONF(RT1015_DEV0_NAME),
.name_prefix = "Left",
},
{
.dlc = COMP_CODEC_CONF(RT1015_DEV1_NAME),
.name_prefix = "Right",
},
};
static struct snd_soc_card mt8192_mt6359_rt1015_rt5682_card = {
.name = RT1015_RT5682_CARD_NAME,
.driver_name = DRIVER_NAME,
.owner = THIS_MODULE,
.dai_link = mt8192_mt6359_dai_links,
.num_links = ARRAY_SIZE(mt8192_mt6359_dai_links),
.controls = mt8192_mt6359_rt1015_rt5682_controls,
.num_controls = ARRAY_SIZE(mt8192_mt6359_rt1015_rt5682_controls),
.dapm_widgets = mt8192_mt6359_rt1015_rt5682_widgets,
.num_dapm_widgets = ARRAY_SIZE(mt8192_mt6359_rt1015_rt5682_widgets),
.dapm_routes = mt8192_mt6359_rt1015_rt5682_routes,
.num_dapm_routes = ARRAY_SIZE(mt8192_mt6359_rt1015_rt5682_routes),
.codec_conf = rt1015_amp_conf,
.num_configs = ARRAY_SIZE(rt1015_amp_conf),
};
static const struct snd_soc_dapm_widget mt8192_mt6359_rt1015p_rt5682x_widgets[] = {
SND_SOC_DAPM_SPK("Speakers", NULL),
SND_SOC_DAPM_HP("Headphone Jack", NULL),
SND_SOC_DAPM_MIC("Headset Mic", NULL),
};
static const struct snd_soc_dapm_route mt8192_mt6359_rt1015p_rt5682x_routes[] = {
/* speaker */
{ "Speakers", NULL, "Speaker" },
/* headset */
{ "Headphone Jack", NULL, "HPOL" },
{ "Headphone Jack", NULL, "HPOR" },
{ "IN1P", NULL, "Headset Mic" },
};
static const struct snd_kcontrol_new mt8192_mt6359_rt1015p_rt5682x_controls[] = {
SOC_DAPM_PIN_SWITCH("Speakers"),
SOC_DAPM_PIN_SWITCH("Headphone Jack"),
SOC_DAPM_PIN_SWITCH("Headset Mic"),
};
static struct snd_soc_card mt8192_mt6359_rt1015p_rt5682x_card = {
.driver_name = DRIVER_NAME,
.owner = THIS_MODULE,
.dai_link = mt8192_mt6359_dai_links,
.num_links = ARRAY_SIZE(mt8192_mt6359_dai_links),
.controls = mt8192_mt6359_rt1015p_rt5682x_controls,
.num_controls = ARRAY_SIZE(mt8192_mt6359_rt1015p_rt5682x_controls),
.dapm_widgets = mt8192_mt6359_rt1015p_rt5682x_widgets,
.num_dapm_widgets = ARRAY_SIZE(mt8192_mt6359_rt1015p_rt5682x_widgets),
.dapm_routes = mt8192_mt6359_rt1015p_rt5682x_routes,
.num_dapm_routes = ARRAY_SIZE(mt8192_mt6359_rt1015p_rt5682x_routes),
};
static int mt8192_mt6359_card_set_be_link(struct snd_soc_card *card,
struct snd_soc_dai_link *link,
struct device_node *node,
char *link_name)
{
int ret;
if (node && strcmp(link->name, link_name) == 0) {
ret = snd_soc_of_get_dai_link_codecs(card->dev, node, link);
if (ret < 0) {
dev_err_probe(card->dev, ret, "get dai link codecs fail\n");
return ret;
}
}
return 0;
}
static int mt8192_mt6359_dev_probe(struct platform_device *pdev)
{
struct snd_soc_card *card;
struct device_node *platform_node, *hdmi_codec, *headset_codec, *speaker_codec;
int ret, i;
struct snd_soc_dai_link *dai_link;
struct mt8192_mt6359_priv *priv;
card = (struct snd_soc_card *)of_device_get_match_data(&pdev->dev);
if (!card)
return -EINVAL;
card->dev = &pdev->dev;
if (of_device_is_compatible(pdev->dev.of_node, RT1015P_RT5682_OF_NAME))
card->name = RT1015P_RT5682_CARD_NAME;
else if (of_device_is_compatible(pdev->dev.of_node, RT1015P_RT5682S_OF_NAME))
card->name = RT1015P_RT5682S_CARD_NAME;
else
dev_dbg(&pdev->dev, "No need to set card name\n");
hdmi_codec = of_parse_phandle(pdev->dev.of_node, "mediatek,hdmi-codec", 0);
if (!hdmi_codec)
dev_dbg(&pdev->dev, "The machine has no hdmi-codec\n");
platform_node = of_parse_phandle(pdev->dev.of_node, "mediatek,platform", 0);
if (!platform_node) {
ret = -EINVAL;
dev_err_probe(&pdev->dev, ret, "Property 'platform' missing or invalid\n");
goto err_platform_node;
}
speaker_codec = of_get_child_by_name(pdev->dev.of_node, "speaker-codecs");
if (!speaker_codec) {
ret = -EINVAL;
dev_err_probe(&pdev->dev, ret, "Property 'speaker-codecs' missing or invalid\n");
goto err_speaker_codec;
}
headset_codec = of_get_child_by_name(pdev->dev.of_node, "headset-codec");
if (!headset_codec) {
ret = -EINVAL;
dev_err_probe(&pdev->dev, ret, "Property 'headset-codec' missing or invalid\n");
goto err_headset_codec;
}
for_each_card_prelinks(card, i, dai_link) {
ret = mt8192_mt6359_card_set_be_link(card, dai_link, speaker_codec, "I2S3");
if (ret) {
dev_err_probe(&pdev->dev, ret, "%s set speaker_codec fail\n",
dai_link->name);
goto err_probe;
}
ret = mt8192_mt6359_card_set_be_link(card, dai_link, headset_codec, "I2S8");
if (ret) {
dev_err_probe(&pdev->dev, ret, "%s set headset_codec fail\n",
dai_link->name);
goto err_probe;
}
ret = mt8192_mt6359_card_set_be_link(card, dai_link, headset_codec, "I2S9");
if (ret) {
dev_err_probe(&pdev->dev, ret, "%s set headset_codec fail\n",
dai_link->name);
goto err_probe;
}
if (hdmi_codec && strcmp(dai_link->name, "TDM") == 0) {
dai_link->codecs->of_node = hdmi_codec;
dai_link->ignore = 0;
}
if (strcmp(dai_link->codecs[0].dai_name, RT1015_CODEC_DAI) == 0)
dai_link->ops = &mt8192_rt1015_i2s_ops;
if (!dai_link->platforms->name)
dai_link->platforms->of_node = platform_node;
}
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv) {
ret = -ENOMEM;
goto err_probe;
}
snd_soc_card_set_drvdata(card, priv);
ret = mt8192_afe_gpio_init(&pdev->dev);
if (ret) {
dev_err_probe(&pdev->dev, ret, "%s init gpio error\n", __func__);
goto err_probe;
}
ret = devm_snd_soc_register_card(&pdev->dev, card);
if (ret)
dev_err_probe(&pdev->dev, ret, "%s snd_soc_register_card fail\n", __func__);
err_probe:
of_node_put(headset_codec);
err_headset_codec:
of_node_put(speaker_codec);
err_speaker_codec:
of_node_put(platform_node);
err_platform_node:
of_node_put(hdmi_codec);
return ret;
}
#ifdef CONFIG_OF
static const struct of_device_id mt8192_mt6359_dt_match[] = {
{
.compatible = RT1015_RT5682_OF_NAME,
.data = &mt8192_mt6359_rt1015_rt5682_card,
},
{
.compatible = RT1015P_RT5682_OF_NAME,
.data = &mt8192_mt6359_rt1015p_rt5682x_card,
},
{
.compatible = RT1015P_RT5682S_OF_NAME,
.data = &mt8192_mt6359_rt1015p_rt5682x_card,
},
{}
};
MODULE_DEVICE_TABLE(of, mt8192_mt6359_dt_match);
#endif
static const struct dev_pm_ops mt8192_mt6359_pm_ops = {
.poweroff = snd_soc_poweroff,
.restore = snd_soc_resume,
};
static struct platform_driver mt8192_mt6359_driver = {
.driver = {
.name = DRIVER_NAME,
#ifdef CONFIG_OF
.of_match_table = mt8192_mt6359_dt_match,
#endif
.pm = &mt8192_mt6359_pm_ops,
},
.probe = mt8192_mt6359_dev_probe,
};
module_platform_driver(mt8192_mt6359_driver);
/* Module information */
MODULE_DESCRIPTION("MT8192-MT6359 ALSA SoC machine driver");
MODULE_AUTHOR("Jiaxin Yu <[email protected]>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("mt8192_mt6359 soc card");
| linux-master | sound/soc/mediatek/mt8192/mt8192-mt6359-rt1015-rt5682.c |
// SPDX-License-Identifier: GPL-2.0
//
// mt8192-afe-gpio.c -- Mediatek 8192 afe gpio ctrl
//
// Copyright (c) 2020 MediaTek Inc.
// Author: Shane Chien <[email protected]>
//
#include <linux/gpio.h>
#include <linux/pinctrl/consumer.h>
#include "mt8192-afe-common.h"
#include "mt8192-afe-gpio.h"
static struct pinctrl *aud_pinctrl;
enum mt8192_afe_gpio {
MT8192_AFE_GPIO_DAT_MISO_OFF,
MT8192_AFE_GPIO_DAT_MISO_ON,
MT8192_AFE_GPIO_DAT_MOSI_OFF,
MT8192_AFE_GPIO_DAT_MOSI_ON,
MT8192_AFE_GPIO_DAT_MISO_CH34_OFF,
MT8192_AFE_GPIO_DAT_MISO_CH34_ON,
MT8192_AFE_GPIO_DAT_MOSI_CH34_OFF,
MT8192_AFE_GPIO_DAT_MOSI_CH34_ON,
MT8192_AFE_GPIO_I2S0_OFF,
MT8192_AFE_GPIO_I2S0_ON,
MT8192_AFE_GPIO_I2S1_OFF,
MT8192_AFE_GPIO_I2S1_ON,
MT8192_AFE_GPIO_I2S2_OFF,
MT8192_AFE_GPIO_I2S2_ON,
MT8192_AFE_GPIO_I2S3_OFF,
MT8192_AFE_GPIO_I2S3_ON,
MT8192_AFE_GPIO_I2S5_OFF,
MT8192_AFE_GPIO_I2S5_ON,
MT8192_AFE_GPIO_I2S6_OFF,
MT8192_AFE_GPIO_I2S6_ON,
MT8192_AFE_GPIO_I2S7_OFF,
MT8192_AFE_GPIO_I2S7_ON,
MT8192_AFE_GPIO_I2S8_OFF,
MT8192_AFE_GPIO_I2S8_ON,
MT8192_AFE_GPIO_I2S9_OFF,
MT8192_AFE_GPIO_I2S9_ON,
MT8192_AFE_GPIO_VOW_DAT_OFF,
MT8192_AFE_GPIO_VOW_DAT_ON,
MT8192_AFE_GPIO_VOW_CLK_OFF,
MT8192_AFE_GPIO_VOW_CLK_ON,
MT8192_AFE_GPIO_CLK_MOSI_OFF,
MT8192_AFE_GPIO_CLK_MOSI_ON,
MT8192_AFE_GPIO_TDM_OFF,
MT8192_AFE_GPIO_TDM_ON,
MT8192_AFE_GPIO_GPIO_NUM
};
struct audio_gpio_attr {
const char *name;
bool gpio_prepare;
struct pinctrl_state *gpioctrl;
};
static struct audio_gpio_attr aud_gpios[MT8192_AFE_GPIO_GPIO_NUM] = {
[MT8192_AFE_GPIO_DAT_MISO_OFF] = {"aud_dat_miso_off", false, NULL},
[MT8192_AFE_GPIO_DAT_MISO_ON] = {"aud_dat_miso_on", false, NULL},
[MT8192_AFE_GPIO_DAT_MOSI_OFF] = {"aud_dat_mosi_off", false, NULL},
[MT8192_AFE_GPIO_DAT_MOSI_ON] = {"aud_dat_mosi_on", false, NULL},
[MT8192_AFE_GPIO_I2S0_OFF] = {"aud_gpio_i2s0_off", false, NULL},
[MT8192_AFE_GPIO_I2S0_ON] = {"aud_gpio_i2s0_on", false, NULL},
[MT8192_AFE_GPIO_I2S1_OFF] = {"aud_gpio_i2s1_off", false, NULL},
[MT8192_AFE_GPIO_I2S1_ON] = {"aud_gpio_i2s1_on", false, NULL},
[MT8192_AFE_GPIO_I2S2_OFF] = {"aud_gpio_i2s2_off", false, NULL},
[MT8192_AFE_GPIO_I2S2_ON] = {"aud_gpio_i2s2_on", false, NULL},
[MT8192_AFE_GPIO_I2S3_OFF] = {"aud_gpio_i2s3_off", false, NULL},
[MT8192_AFE_GPIO_I2S3_ON] = {"aud_gpio_i2s3_on", false, NULL},
[MT8192_AFE_GPIO_I2S5_OFF] = {"aud_gpio_i2s5_off", false, NULL},
[MT8192_AFE_GPIO_I2S5_ON] = {"aud_gpio_i2s5_on", false, NULL},
[MT8192_AFE_GPIO_I2S6_OFF] = {"aud_gpio_i2s6_off", false, NULL},
[MT8192_AFE_GPIO_I2S6_ON] = {"aud_gpio_i2s6_on", false, NULL},
[MT8192_AFE_GPIO_I2S7_OFF] = {"aud_gpio_i2s7_off", false, NULL},
[MT8192_AFE_GPIO_I2S7_ON] = {"aud_gpio_i2s7_on", false, NULL},
[MT8192_AFE_GPIO_I2S8_OFF] = {"aud_gpio_i2s8_off", false, NULL},
[MT8192_AFE_GPIO_I2S8_ON] = {"aud_gpio_i2s8_on", false, NULL},
[MT8192_AFE_GPIO_I2S9_OFF] = {"aud_gpio_i2s9_off", false, NULL},
[MT8192_AFE_GPIO_I2S9_ON] = {"aud_gpio_i2s9_on", false, NULL},
[MT8192_AFE_GPIO_TDM_OFF] = {"aud_gpio_tdm_off", false, NULL},
[MT8192_AFE_GPIO_TDM_ON] = {"aud_gpio_tdm_on", false, NULL},
[MT8192_AFE_GPIO_VOW_DAT_OFF] = {"vow_dat_miso_off", false, NULL},
[MT8192_AFE_GPIO_VOW_DAT_ON] = {"vow_dat_miso_on", false, NULL},
[MT8192_AFE_GPIO_VOW_CLK_OFF] = {"vow_clk_miso_off", false, NULL},
[MT8192_AFE_GPIO_VOW_CLK_ON] = {"vow_clk_miso_on", false, NULL},
[MT8192_AFE_GPIO_DAT_MISO_CH34_OFF] = {"aud_dat_miso_ch34_off",
false, NULL},
[MT8192_AFE_GPIO_DAT_MISO_CH34_ON] = {"aud_dat_miso_ch34_on",
false, NULL},
[MT8192_AFE_GPIO_DAT_MOSI_CH34_OFF] = {"aud_dat_mosi_ch34_off",
false, NULL},
[MT8192_AFE_GPIO_DAT_MOSI_CH34_ON] = {"aud_dat_mosi_ch34_on",
false, NULL},
[MT8192_AFE_GPIO_CLK_MOSI_OFF] = {"aud_clk_mosi_off", false, NULL},
[MT8192_AFE_GPIO_CLK_MOSI_ON] = {"aud_clk_mosi_on", false, NULL},
};
static DEFINE_MUTEX(gpio_request_mutex);
static int mt8192_afe_gpio_select(struct device *dev,
enum mt8192_afe_gpio type)
{
int ret;
if (type < 0 || type >= MT8192_AFE_GPIO_GPIO_NUM) {
dev_err(dev, "%s(), error, invalid gpio type %d\n",
__func__, type);
return -EINVAL;
}
if (!aud_gpios[type].gpio_prepare) {
dev_warn(dev, "%s(), error, gpio type %d not prepared\n",
__func__, type);
return -EIO;
}
ret = pinctrl_select_state(aud_pinctrl,
aud_gpios[type].gpioctrl);
if (ret) {
dev_dbg(dev, "%s(), error, can not set gpio type %d\n",
__func__, type);
}
return ret;
}
int mt8192_afe_gpio_init(struct device *dev)
{
int i, ret;
aud_pinctrl = devm_pinctrl_get(dev);
if (IS_ERR(aud_pinctrl)) {
ret = PTR_ERR(aud_pinctrl);
dev_err(dev, "%s(), ret %d, cannot get aud_pinctrl!\n",
__func__, ret);
return ret;
}
for (i = 0; i < ARRAY_SIZE(aud_gpios); i++) {
aud_gpios[i].gpioctrl = pinctrl_lookup_state(aud_pinctrl,
aud_gpios[i].name);
if (IS_ERR(aud_gpios[i].gpioctrl)) {
ret = PTR_ERR(aud_gpios[i].gpioctrl);
dev_dbg(dev, "%s(), pinctrl_lookup_state %s fail, ret %d\n",
__func__, aud_gpios[i].name, ret);
} else {
aud_gpios[i].gpio_prepare = true;
}
}
mt8192_afe_gpio_select(dev, MT8192_AFE_GPIO_CLK_MOSI_ON);
/* gpio status init */
mt8192_afe_gpio_request(dev, false, MT8192_DAI_ADDA, 0);
mt8192_afe_gpio_request(dev, false, MT8192_DAI_ADDA, 1);
return 0;
}
EXPORT_SYMBOL(mt8192_afe_gpio_init);
static int mt8192_afe_gpio_adda_dl(struct device *dev, bool enable)
{
if (enable) {
return mt8192_afe_gpio_select(dev,
MT8192_AFE_GPIO_DAT_MOSI_ON);
} else {
return mt8192_afe_gpio_select(dev,
MT8192_AFE_GPIO_DAT_MOSI_OFF);
}
}
static int mt8192_afe_gpio_adda_ul(struct device *dev, bool enable)
{
if (enable) {
return mt8192_afe_gpio_select(dev,
MT8192_AFE_GPIO_DAT_MISO_ON);
} else {
return mt8192_afe_gpio_select(dev,
MT8192_AFE_GPIO_DAT_MISO_OFF);
}
}
static int mt8192_afe_gpio_adda_ch34_dl(struct device *dev, bool enable)
{
if (enable) {
return mt8192_afe_gpio_select(dev,
MT8192_AFE_GPIO_DAT_MOSI_CH34_ON);
} else {
return mt8192_afe_gpio_select(dev,
MT8192_AFE_GPIO_DAT_MOSI_CH34_OFF);
}
}
static int mt8192_afe_gpio_adda_ch34_ul(struct device *dev, bool enable)
{
if (enable) {
return mt8192_afe_gpio_select(dev,
MT8192_AFE_GPIO_DAT_MISO_CH34_ON);
} else {
return mt8192_afe_gpio_select(dev,
MT8192_AFE_GPIO_DAT_MISO_CH34_OFF);
}
}
int mt8192_afe_gpio_request(struct device *dev, bool enable,
int dai, int uplink)
{
mutex_lock(&gpio_request_mutex);
switch (dai) {
case MT8192_DAI_ADDA:
if (uplink)
mt8192_afe_gpio_adda_ul(dev, enable);
else
mt8192_afe_gpio_adda_dl(dev, enable);
break;
case MT8192_DAI_ADDA_CH34:
if (uplink)
mt8192_afe_gpio_adda_ch34_ul(dev, enable);
else
mt8192_afe_gpio_adda_ch34_dl(dev, enable);
break;
case MT8192_DAI_I2S_0:
if (enable)
mt8192_afe_gpio_select(dev, MT8192_AFE_GPIO_I2S0_ON);
else
mt8192_afe_gpio_select(dev, MT8192_AFE_GPIO_I2S0_OFF);
break;
case MT8192_DAI_I2S_1:
if (enable)
mt8192_afe_gpio_select(dev, MT8192_AFE_GPIO_I2S1_ON);
else
mt8192_afe_gpio_select(dev, MT8192_AFE_GPIO_I2S1_OFF);
break;
case MT8192_DAI_I2S_2:
if (enable)
mt8192_afe_gpio_select(dev, MT8192_AFE_GPIO_I2S2_ON);
else
mt8192_afe_gpio_select(dev, MT8192_AFE_GPIO_I2S2_OFF);
break;
case MT8192_DAI_I2S_3:
if (enable)
mt8192_afe_gpio_select(dev, MT8192_AFE_GPIO_I2S3_ON);
else
mt8192_afe_gpio_select(dev, MT8192_AFE_GPIO_I2S3_OFF);
break;
case MT8192_DAI_I2S_5:
if (enable)
mt8192_afe_gpio_select(dev, MT8192_AFE_GPIO_I2S5_ON);
else
mt8192_afe_gpio_select(dev, MT8192_AFE_GPIO_I2S5_OFF);
break;
case MT8192_DAI_I2S_6:
if (enable)
mt8192_afe_gpio_select(dev, MT8192_AFE_GPIO_I2S6_ON);
else
mt8192_afe_gpio_select(dev, MT8192_AFE_GPIO_I2S6_OFF);
break;
case MT8192_DAI_I2S_7:
if (enable)
mt8192_afe_gpio_select(dev, MT8192_AFE_GPIO_I2S7_ON);
else
mt8192_afe_gpio_select(dev, MT8192_AFE_GPIO_I2S7_OFF);
break;
case MT8192_DAI_I2S_8:
if (enable)
mt8192_afe_gpio_select(dev, MT8192_AFE_GPIO_I2S8_ON);
else
mt8192_afe_gpio_select(dev, MT8192_AFE_GPIO_I2S8_OFF);
break;
case MT8192_DAI_I2S_9:
if (enable)
mt8192_afe_gpio_select(dev, MT8192_AFE_GPIO_I2S9_ON);
else
mt8192_afe_gpio_select(dev, MT8192_AFE_GPIO_I2S9_OFF);
break;
case MT8192_DAI_TDM:
if (enable)
mt8192_afe_gpio_select(dev, MT8192_AFE_GPIO_TDM_ON);
else
mt8192_afe_gpio_select(dev, MT8192_AFE_GPIO_TDM_OFF);
break;
case MT8192_DAI_VOW:
if (enable) {
mt8192_afe_gpio_select(dev,
MT8192_AFE_GPIO_VOW_CLK_ON);
mt8192_afe_gpio_select(dev,
MT8192_AFE_GPIO_VOW_DAT_ON);
} else {
mt8192_afe_gpio_select(dev,
MT8192_AFE_GPIO_VOW_CLK_OFF);
mt8192_afe_gpio_select(dev,
MT8192_AFE_GPIO_VOW_DAT_OFF);
}
break;
default:
mutex_unlock(&gpio_request_mutex);
dev_warn(dev, "%s(), invalid dai %d\n", __func__, dai);
return -EINVAL;
}
mutex_unlock(&gpio_request_mutex);
return 0;
}
EXPORT_SYMBOL(mt8192_afe_gpio_request);
| linux-master | sound/soc/mediatek/mt8192/mt8192-afe-gpio.c |
// SPDX-License-Identifier: GPL-2.0
//
// MediaTek ALSA SoC Audio DAI I2S Control
//
// Copyright (c) 2020 MediaTek Inc.
// Author: Shane Chien <[email protected]>
//
#include <linux/regmap.h>
#include <sound/pcm_params.h>
#include "mt8192-afe-common.h"
#include "mt8192-interconnection.h"
enum AUD_TX_LCH_RPT {
AUD_TX_LCH_RPT_NO_REPEAT = 0,
AUD_TX_LCH_RPT_REPEAT = 1
};
enum AUD_VBT_16K_MODE {
AUD_VBT_16K_MODE_DISABLE = 0,
AUD_VBT_16K_MODE_ENABLE = 1
};
enum AUD_EXT_MODEM {
AUD_EXT_MODEM_SELECT_INTERNAL = 0,
AUD_EXT_MODEM_SELECT_EXTERNAL = 1
};
enum AUD_PCM_SYNC_TYPE {
/* bck sync length = 1 */
AUD_PCM_ONE_BCK_CYCLE_SYNC = 0,
/* bck sync length = PCM_INTF_CON1[9:13] */
AUD_PCM_EXTENDED_BCK_CYCLE_SYNC = 1
};
enum AUD_BT_MODE {
AUD_BT_MODE_DUAL_MIC_ON_TX = 0,
AUD_BT_MODE_SINGLE_MIC_ON_TX = 1
};
enum AUD_PCM_AFIFO_SRC {
/* slave mode & external modem uses different crystal */
AUD_PCM_AFIFO_ASRC = 0,
/* slave mode & external modem uses the same crystal */
AUD_PCM_AFIFO_AFIFO = 1
};
enum AUD_PCM_CLOCK_SOURCE {
AUD_PCM_CLOCK_MASTER_MODE = 0,
AUD_PCM_CLOCK_SLAVE_MODE = 1
};
enum AUD_PCM_WLEN {
AUD_PCM_WLEN_PCM_32_BCK_CYCLES = 0,
AUD_PCM_WLEN_PCM_64_BCK_CYCLES = 1
};
enum AUD_PCM_MODE {
AUD_PCM_MODE_PCM_MODE_8K = 0,
AUD_PCM_MODE_PCM_MODE_16K = 1,
AUD_PCM_MODE_PCM_MODE_32K = 2,
AUD_PCM_MODE_PCM_MODE_48K = 3,
};
enum AUD_PCM_FMT {
AUD_PCM_FMT_I2S = 0,
AUD_PCM_FMT_EIAJ = 1,
AUD_PCM_FMT_PCM_MODE_A = 2,
AUD_PCM_FMT_PCM_MODE_B = 3
};
enum AUD_BCLK_OUT_INV {
AUD_BCLK_OUT_INV_NO_INVERSE = 0,
AUD_BCLK_OUT_INV_INVERSE = 1
};
enum AUD_PCM_EN {
AUD_PCM_EN_DISABLE = 0,
AUD_PCM_EN_ENABLE = 1
};
/* dai component */
static const struct snd_kcontrol_new mtk_pcm_1_playback_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN7,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN7,
I_DL2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN7_1,
I_DL4_CH1, 1, 0),
};
static const struct snd_kcontrol_new mtk_pcm_1_playback_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN8,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN8,
I_DL2_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN8_1,
I_DL4_CH2, 1, 0),
};
static const struct snd_kcontrol_new mtk_pcm_1_playback_ch4_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1", AFE_CONN27,
I_I2S0_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2", AFE_CONN27,
I_I2S0_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN27,
I_DL1_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1", AFE_CONN27,
I_I2S2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2", AFE_CONN27,
I_I2S2_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN27_1,
I_DL4_CH1, 1, 0),
};
static const struct snd_kcontrol_new mtk_pcm_2_playback_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN17,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN17,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN17,
I_ADDA_UL_CH3, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN17,
I_DL2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN17_1,
I_DL4_CH1, 1, 0),
};
static const struct snd_kcontrol_new mtk_pcm_2_playback_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN18,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN18,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN18,
I_ADDA_UL_CH3, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN18,
I_DL2_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN18_1,
I_DL4_CH2, 1, 0),
};
static const struct snd_kcontrol_new mtk_pcm_2_playback_ch3_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN23,
I_ADDA_UL_CH3, 1, 0),
};
static const struct snd_kcontrol_new mtk_pcm_2_playback_ch4_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1", AFE_CONN24,
I_I2S0_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2", AFE_CONN24,
I_I2S0_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN24,
I_DL1_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1", AFE_CONN24,
I_I2S2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2", AFE_CONN24,
I_I2S2_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN24_1,
I_DL4_CH1, 1, 0),
};
static const struct snd_kcontrol_new mtk_pcm_2_playback_ch5_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2", AFE_CONN25,
I_I2S0_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN25,
I_DL1_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2", AFE_CONN25,
I_I2S2_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN25_1,
I_DL4_CH2, 1, 0),
};
static int mtk_pcm_en_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
dev_info(afe->dev, "%s(), name %s, event 0x%x\n",
__func__, w->name, event);
return 0;
}
static const struct snd_soc_dapm_widget mtk_dai_pcm_widgets[] = {
/* inter-connections */
SND_SOC_DAPM_MIXER("PCM_1_PB_CH1", SND_SOC_NOPM, 0, 0,
mtk_pcm_1_playback_ch1_mix,
ARRAY_SIZE(mtk_pcm_1_playback_ch1_mix)),
SND_SOC_DAPM_MIXER("PCM_1_PB_CH2", SND_SOC_NOPM, 0, 0,
mtk_pcm_1_playback_ch2_mix,
ARRAY_SIZE(mtk_pcm_1_playback_ch2_mix)),
SND_SOC_DAPM_MIXER("PCM_1_PB_CH4", SND_SOC_NOPM, 0, 0,
mtk_pcm_1_playback_ch4_mix,
ARRAY_SIZE(mtk_pcm_1_playback_ch4_mix)),
SND_SOC_DAPM_MIXER("PCM_2_PB_CH1", SND_SOC_NOPM, 0, 0,
mtk_pcm_2_playback_ch1_mix,
ARRAY_SIZE(mtk_pcm_2_playback_ch1_mix)),
SND_SOC_DAPM_MIXER("PCM_2_PB_CH2", SND_SOC_NOPM, 0, 0,
mtk_pcm_2_playback_ch2_mix,
ARRAY_SIZE(mtk_pcm_2_playback_ch2_mix)),
SND_SOC_DAPM_MIXER("PCM_2_PB_CH3", SND_SOC_NOPM, 0, 0,
mtk_pcm_2_playback_ch3_mix,
ARRAY_SIZE(mtk_pcm_2_playback_ch3_mix)),
SND_SOC_DAPM_MIXER("PCM_2_PB_CH4", SND_SOC_NOPM, 0, 0,
mtk_pcm_2_playback_ch4_mix,
ARRAY_SIZE(mtk_pcm_2_playback_ch4_mix)),
SND_SOC_DAPM_MIXER("PCM_2_PB_CH5", SND_SOC_NOPM, 0, 0,
mtk_pcm_2_playback_ch5_mix,
ARRAY_SIZE(mtk_pcm_2_playback_ch5_mix)),
SND_SOC_DAPM_SUPPLY("PCM_1_EN",
PCM_INTF_CON1, PCM_EN_SFT, 0,
mtk_pcm_en_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY("PCM_2_EN",
PCM2_INTF_CON, PCM2_EN_SFT, 0,
mtk_pcm_en_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_INPUT("MD1_TO_AFE"),
SND_SOC_DAPM_INPUT("MD2_TO_AFE"),
SND_SOC_DAPM_OUTPUT("AFE_TO_MD1"),
SND_SOC_DAPM_OUTPUT("AFE_TO_MD2"),
};
static const struct snd_soc_dapm_route mtk_dai_pcm_routes[] = {
{"PCM 1 Playback", NULL, "PCM_1_PB_CH1"},
{"PCM 1 Playback", NULL, "PCM_1_PB_CH2"},
{"PCM 1 Playback", NULL, "PCM_1_PB_CH4"},
{"PCM 2 Playback", NULL, "PCM_2_PB_CH1"},
{"PCM 2 Playback", NULL, "PCM_2_PB_CH2"},
{"PCM 2 Playback", NULL, "PCM_2_PB_CH3"},
{"PCM 2 Playback", NULL, "PCM_2_PB_CH4"},
{"PCM 2 Playback", NULL, "PCM_2_PB_CH5"},
{"PCM 1 Playback", NULL, "PCM_1_EN"},
{"PCM 2 Playback", NULL, "PCM_2_EN"},
{"PCM 1 Capture", NULL, "PCM_1_EN"},
{"PCM 2 Capture", NULL, "PCM_2_EN"},
{"AFE_TO_MD1", NULL, "PCM 2 Playback"},
{"AFE_TO_MD2", NULL, "PCM 1 Playback"},
{"PCM 2 Capture", NULL, "MD1_TO_AFE"},
{"PCM 1 Capture", NULL, "MD2_TO_AFE"},
{"PCM_1_PB_CH1", "DL2_CH1", "DL2"},
{"PCM_1_PB_CH2", "DL2_CH2", "DL2"},
{"PCM_1_PB_CH4", "DL1_CH1", "DL1"},
{"PCM_2_PB_CH1", "DL2_CH1", "DL2"},
{"PCM_2_PB_CH2", "DL2_CH2", "DL2"},
{"PCM_2_PB_CH4", "DL1_CH1", "DL1"},
{"PCM_1_PB_CH1", "DL4_CH1", "DL4"},
{"PCM_1_PB_CH2", "DL4_CH2", "DL4"},
{"PCM_1_PB_CH4", "DL4_CH1", "DL4"},
{"PCM_2_PB_CH1", "DL4_CH1", "DL4"},
{"PCM_2_PB_CH2", "DL4_CH2", "DL4"},
{"PCM_2_PB_CH4", "DL4_CH1", "DL4"},
{"PCM_1_PB_CH4", "I2S0_CH1", "I2S0"},
{"PCM_2_PB_CH4", "I2S2_CH1", "I2S2"},
{"PCM_2_PB_CH5", "DL1_CH2", "DL1"},
{"PCM_2_PB_CH5", "DL4_CH2", "DL4"},
{"PCM_2_PB_CH5", "I2S0_CH2", "I2S0"},
{"PCM_2_PB_CH5", "I2S2_CH2", "I2S2"},
};
/* dai ops */
static int mtk_dai_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct snd_soc_dapm_widget *p = snd_soc_dai_get_widget_playback(dai);
struct snd_soc_dapm_widget *c = snd_soc_dai_get_widget_capture(dai);
unsigned int rate = params_rate(params);
unsigned int rate_reg = mt8192_rate_transform(afe->dev, rate, dai->id);
unsigned int pcm_con = 0;
dev_info(afe->dev, "%s(), id %d, stream %d, rate %d, rate_reg %d, widget active p %d, c %d\n",
__func__,
dai->id,
substream->stream,
rate,
rate_reg,
p->active,
c->active);
if (p->active || c->active)
return 0;
switch (dai->id) {
case MT8192_DAI_PCM_1:
pcm_con |= AUD_BCLK_OUT_INV_NO_INVERSE << PCM_BCLK_OUT_INV_SFT;
pcm_con |= AUD_TX_LCH_RPT_NO_REPEAT << PCM_TX_LCH_RPT_SFT;
pcm_con |= AUD_VBT_16K_MODE_DISABLE << PCM_VBT_16K_MODE_SFT;
pcm_con |= AUD_EXT_MODEM_SELECT_INTERNAL << PCM_EXT_MODEM_SFT;
pcm_con |= 0 << PCM_SYNC_LENGTH_SFT;
pcm_con |= AUD_PCM_ONE_BCK_CYCLE_SYNC << PCM_SYNC_TYPE_SFT;
pcm_con |= AUD_BT_MODE_DUAL_MIC_ON_TX << PCM_BT_MODE_SFT;
pcm_con |= AUD_PCM_AFIFO_AFIFO << PCM_BYP_ASRC_SFT;
pcm_con |= AUD_PCM_CLOCK_SLAVE_MODE << PCM_SLAVE_SFT;
pcm_con |= rate_reg << PCM_MODE_SFT;
pcm_con |= AUD_PCM_FMT_PCM_MODE_B << PCM_FMT_SFT;
regmap_update_bits(afe->regmap, PCM_INTF_CON1,
0xfffffffe, pcm_con);
break;
case MT8192_DAI_PCM_2:
pcm_con |= AUD_TX_LCH_RPT_NO_REPEAT << PCM2_TX_LCH_RPT_SFT;
pcm_con |= AUD_VBT_16K_MODE_DISABLE << PCM2_VBT_16K_MODE_SFT;
pcm_con |= AUD_BT_MODE_DUAL_MIC_ON_TX << PCM2_BT_MODE_SFT;
pcm_con |= AUD_PCM_AFIFO_AFIFO << PCM2_AFIFO_SFT;
pcm_con |= AUD_PCM_WLEN_PCM_32_BCK_CYCLES << PCM2_WLEN_SFT;
pcm_con |= rate_reg << PCM2_MODE_SFT;
pcm_con |= AUD_PCM_FMT_PCM_MODE_B << PCM2_FMT_SFT;
regmap_update_bits(afe->regmap, PCM2_INTF_CON,
0xfffffffe, pcm_con);
break;
default:
dev_warn(afe->dev, "%s(), id %d not support\n",
__func__, dai->id);
return -EINVAL;
}
return 0;
}
static const struct snd_soc_dai_ops mtk_dai_pcm_ops = {
.hw_params = mtk_dai_pcm_hw_params,
};
/* dai driver */
#define MTK_PCM_RATES (SNDRV_PCM_RATE_8000 |\
SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 |\
SNDRV_PCM_RATE_48000)
#define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver mtk_dai_pcm_driver[] = {
{
.name = "PCM 1",
.id = MT8192_DAI_PCM_1,
.playback = {
.stream_name = "PCM 1 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.capture = {
.stream_name = "PCM 1 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_dai_pcm_ops,
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
},
{
.name = "PCM 2",
.id = MT8192_DAI_PCM_2,
.playback = {
.stream_name = "PCM 2 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.capture = {
.stream_name = "PCM 2 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_dai_pcm_ops,
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
},
};
int mt8192_dai_pcm_register(struct mtk_base_afe *afe)
{
struct mtk_base_afe_dai *dai;
dev_info(afe->dev, "%s()\n", __func__);
dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
if (!dai)
return -ENOMEM;
list_add(&dai->list, &afe->sub_dais);
dai->dai_drivers = mtk_dai_pcm_driver;
dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_pcm_driver);
dai->dapm_widgets = mtk_dai_pcm_widgets;
dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_pcm_widgets);
dai->dapm_routes = mtk_dai_pcm_routes;
dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_pcm_routes);
return 0;
}
| linux-master | sound/soc/mediatek/mt8192/mt8192-dai-pcm.c |
// SPDX-License-Identifier: GPL-2.0
//
// mt8192-afe-clk.c -- Mediatek 8192 afe clock ctrl
//
// Copyright (c) 2020 MediaTek Inc.
// Author: Shane Chien <[email protected]>
//
#include <linux/arm-smccc.h>
#include <linux/clk.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>
#include "mt8192-afe-clk.h"
#include "mt8192-afe-common.h"
static const char *aud_clks[CLK_NUM] = {
[CLK_AFE] = "aud_afe_clk",
[CLK_TML] = "aud_tml_clk",
[CLK_APLL22M] = "aud_apll22m_clk",
[CLK_APLL24M] = "aud_apll24m_clk",
[CLK_APLL1_TUNER] = "aud_apll1_tuner_clk",
[CLK_APLL2_TUNER] = "aud_apll2_tuner_clk",
[CLK_NLE] = "aud_nle",
[CLK_INFRA_SYS_AUDIO] = "aud_infra_clk",
[CLK_INFRA_AUDIO_26M] = "aud_infra_26m_clk",
[CLK_MUX_AUDIO] = "top_mux_audio",
[CLK_MUX_AUDIOINTBUS] = "top_mux_audio_int",
[CLK_TOP_MAINPLL_D4_D4] = "top_mainpll_d4_d4",
[CLK_TOP_MUX_AUD_1] = "top_mux_aud_1",
[CLK_TOP_APLL1_CK] = "top_apll1_ck",
[CLK_TOP_MUX_AUD_2] = "top_mux_aud_2",
[CLK_TOP_APLL2_CK] = "top_apll2_ck",
[CLK_TOP_MUX_AUD_ENG1] = "top_mux_aud_eng1",
[CLK_TOP_APLL1_D4] = "top_apll1_d4",
[CLK_TOP_MUX_AUD_ENG2] = "top_mux_aud_eng2",
[CLK_TOP_APLL2_D4] = "top_apll2_d4",
[CLK_TOP_MUX_AUDIO_H] = "top_mux_audio_h",
[CLK_TOP_I2S0_M_SEL] = "top_i2s0_m_sel",
[CLK_TOP_I2S1_M_SEL] = "top_i2s1_m_sel",
[CLK_TOP_I2S2_M_SEL] = "top_i2s2_m_sel",
[CLK_TOP_I2S3_M_SEL] = "top_i2s3_m_sel",
[CLK_TOP_I2S4_M_SEL] = "top_i2s4_m_sel",
[CLK_TOP_I2S5_M_SEL] = "top_i2s5_m_sel",
[CLK_TOP_I2S6_M_SEL] = "top_i2s6_m_sel",
[CLK_TOP_I2S7_M_SEL] = "top_i2s7_m_sel",
[CLK_TOP_I2S8_M_SEL] = "top_i2s8_m_sel",
[CLK_TOP_I2S9_M_SEL] = "top_i2s9_m_sel",
[CLK_TOP_APLL12_DIV0] = "top_apll12_div0",
[CLK_TOP_APLL12_DIV1] = "top_apll12_div1",
[CLK_TOP_APLL12_DIV2] = "top_apll12_div2",
[CLK_TOP_APLL12_DIV3] = "top_apll12_div3",
[CLK_TOP_APLL12_DIV4] = "top_apll12_div4",
[CLK_TOP_APLL12_DIVB] = "top_apll12_divb",
[CLK_TOP_APLL12_DIV5] = "top_apll12_div5",
[CLK_TOP_APLL12_DIV6] = "top_apll12_div6",
[CLK_TOP_APLL12_DIV7] = "top_apll12_div7",
[CLK_TOP_APLL12_DIV8] = "top_apll12_div8",
[CLK_TOP_APLL12_DIV9] = "top_apll12_div9",
[CLK_CLK26M] = "top_clk26m_clk",
};
int mt8192_set_audio_int_bus_parent(struct mtk_base_afe *afe,
int clk_id)
{
struct mt8192_afe_private *afe_priv = afe->platform_priv;
int ret;
ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIOINTBUS],
afe_priv->clk[clk_id]);
if (ret) {
dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[CLK_MUX_AUDIOINTBUS],
aud_clks[clk_id], ret);
}
return ret;
}
static int apll1_mux_setting(struct mtk_base_afe *afe, bool enable)
{
struct mt8192_afe_private *afe_priv = afe->platform_priv;
int ret;
if (enable) {
ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_1]);
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_1], ret);
goto EXIT;
}
ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1],
afe_priv->clk[CLK_TOP_APLL1_CK]);
if (ret) {
dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_1],
aud_clks[CLK_TOP_APLL1_CK], ret);
goto EXIT;
}
/* 180.6336 / 4 = 45.1584MHz */
ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]);
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_ENG1], ret);
goto EXIT;
}
ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1],
afe_priv->clk[CLK_TOP_APLL1_D4]);
if (ret) {
dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_ENG1],
aud_clks[CLK_TOP_APLL1_D4], ret);
goto EXIT;
}
} else {
ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1],
afe_priv->clk[CLK_CLK26M]);
if (ret) {
dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_ENG1],
aud_clks[CLK_CLK26M], ret);
goto EXIT;
}
clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]);
ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1],
afe_priv->clk[CLK_CLK26M]);
if (ret) {
dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_1],
aud_clks[CLK_CLK26M], ret);
goto EXIT;
}
clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_1]);
}
EXIT:
return ret;
}
static int apll2_mux_setting(struct mtk_base_afe *afe, bool enable)
{
struct mt8192_afe_private *afe_priv = afe->platform_priv;
int ret;
if (enable) {
ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_2]);
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_2], ret);
goto EXIT;
}
ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2],
afe_priv->clk[CLK_TOP_APLL2_CK]);
if (ret) {
dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_2],
aud_clks[CLK_TOP_APLL2_CK], ret);
goto EXIT;
}
/* 196.608 / 4 = 49.152MHz */
ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]);
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_ENG2], ret);
goto EXIT;
}
ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2],
afe_priv->clk[CLK_TOP_APLL2_D4]);
if (ret) {
dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_ENG2],
aud_clks[CLK_TOP_APLL2_D4], ret);
goto EXIT;
}
} else {
ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2],
afe_priv->clk[CLK_CLK26M]);
if (ret) {
dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_ENG2],
aud_clks[CLK_CLK26M], ret);
goto EXIT;
}
clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]);
ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2],
afe_priv->clk[CLK_CLK26M]);
if (ret) {
dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_2],
aud_clks[CLK_CLK26M], ret);
goto EXIT;
}
clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_2]);
}
EXIT:
return ret;
}
int mt8192_afe_enable_clock(struct mtk_base_afe *afe)
{
struct mt8192_afe_private *afe_priv = afe->platform_priv;
int ret;
ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_SYS_AUDIO]);
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_INFRA_SYS_AUDIO], ret);
goto EXIT;
}
ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_AUDIO_26M]);
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_INFRA_AUDIO_26M], ret);
goto EXIT;
}
ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIO]);
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_MUX_AUDIO], ret);
goto EXIT;
}
ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIO],
afe_priv->clk[CLK_CLK26M]);
if (ret) {
dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[CLK_MUX_AUDIO],
aud_clks[CLK_CLK26M], ret);
goto EXIT;
}
ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_MUX_AUDIOINTBUS], ret);
goto EXIT;
}
ret = mt8192_set_audio_int_bus_parent(afe, CLK_CLK26M);
if (ret) {
dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[CLK_MUX_AUDIOINTBUS],
aud_clks[CLK_CLK26M], ret);
goto EXIT;
}
ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUDIO_H],
afe_priv->clk[CLK_TOP_APLL2_CK]);
if (ret) {
dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUDIO_H],
aud_clks[CLK_TOP_APLL2_CK], ret);
goto EXIT;
}
ret = clk_prepare_enable(afe_priv->clk[CLK_AFE]);
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_AFE], ret);
goto EXIT;
}
EXIT:
return ret;
}
void mt8192_afe_disable_clock(struct mtk_base_afe *afe)
{
struct mt8192_afe_private *afe_priv = afe->platform_priv;
clk_disable_unprepare(afe_priv->clk[CLK_AFE]);
mt8192_set_audio_int_bus_parent(afe, CLK_CLK26M);
clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIO]);
clk_disable_unprepare(afe_priv->clk[CLK_INFRA_AUDIO_26M]);
clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUDIO]);
}
int mt8192_apll1_enable(struct mtk_base_afe *afe)
{
struct mt8192_afe_private *afe_priv = afe->platform_priv;
int ret;
/* setting for APLL */
apll1_mux_setting(afe, true);
ret = clk_prepare_enable(afe_priv->clk[CLK_APLL22M]);
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_APLL22M], ret);
goto EXIT;
}
ret = clk_prepare_enable(afe_priv->clk[CLK_APLL1_TUNER]);
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_APLL1_TUNER], ret);
goto EXIT;
}
regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG,
0x0000FFF7, 0x00000832);
regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0x1, 0x1);
regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
AFE_22M_ON_MASK_SFT,
0x1 << AFE_22M_ON_SFT);
EXIT:
return ret;
}
void mt8192_apll1_disable(struct mtk_base_afe *afe)
{
struct mt8192_afe_private *afe_priv = afe->platform_priv;
regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
AFE_22M_ON_MASK_SFT,
0x0 << AFE_22M_ON_SFT);
regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0x1, 0x0);
clk_disable_unprepare(afe_priv->clk[CLK_APLL1_TUNER]);
clk_disable_unprepare(afe_priv->clk[CLK_APLL22M]);
apll1_mux_setting(afe, false);
}
int mt8192_apll2_enable(struct mtk_base_afe *afe)
{
struct mt8192_afe_private *afe_priv = afe->platform_priv;
int ret;
/* setting for APLL */
apll2_mux_setting(afe, true);
ret = clk_prepare_enable(afe_priv->clk[CLK_APLL24M]);
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_APLL24M], ret);
goto EXIT;
}
ret = clk_prepare_enable(afe_priv->clk[CLK_APLL2_TUNER]);
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_APLL2_TUNER], ret);
goto EXIT;
}
regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG,
0x0000FFF7, 0x00000634);
regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0x1, 0x1);
regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
AFE_24M_ON_MASK_SFT,
0x1 << AFE_24M_ON_SFT);
EXIT:
return ret;
}
void mt8192_apll2_disable(struct mtk_base_afe *afe)
{
struct mt8192_afe_private *afe_priv = afe->platform_priv;
regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
AFE_24M_ON_MASK_SFT,
0x0 << AFE_24M_ON_SFT);
regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0x1, 0x0);
clk_disable_unprepare(afe_priv->clk[CLK_APLL2_TUNER]);
clk_disable_unprepare(afe_priv->clk[CLK_APLL24M]);
apll2_mux_setting(afe, false);
}
int mt8192_get_apll_rate(struct mtk_base_afe *afe, int apll)
{
return (apll == MT8192_APLL1) ? 180633600 : 196608000;
}
int mt8192_get_apll_by_rate(struct mtk_base_afe *afe, int rate)
{
return ((rate % 8000) == 0) ? MT8192_APLL2 : MT8192_APLL1;
}
int mt8192_get_apll_by_name(struct mtk_base_afe *afe, const char *name)
{
if (strcmp(name, APLL1_W_NAME) == 0)
return MT8192_APLL1;
else
return MT8192_APLL2;
}
/* mck */
struct mt8192_mck_div {
int m_sel_id;
int div_clk_id;
/* below will be deprecated */
int div_pdn_reg;
int div_pdn_mask_sft;
int div_reg;
int div_mask_sft;
int div_mask;
int div_sft;
int div_apll_sel_reg;
int div_apll_sel_mask_sft;
int div_apll_sel_sft;
};
static const struct mt8192_mck_div mck_div[MT8192_MCK_NUM] = {
[MT8192_I2S0_MCK] = {
.m_sel_id = CLK_TOP_I2S0_M_SEL,
.div_clk_id = CLK_TOP_APLL12_DIV0,
.div_pdn_reg = CLK_AUDDIV_0,
.div_pdn_mask_sft = APLL12_DIV0_PDN_MASK_SFT,
.div_reg = CLK_AUDDIV_2,
.div_mask_sft = APLL12_CK_DIV0_MASK_SFT,
.div_mask = APLL12_CK_DIV0_MASK,
.div_sft = APLL12_CK_DIV0_SFT,
.div_apll_sel_reg = CLK_AUDDIV_0,
.div_apll_sel_mask_sft = APLL_I2S0_MCK_SEL_MASK_SFT,
.div_apll_sel_sft = APLL_I2S0_MCK_SEL_SFT,
},
[MT8192_I2S1_MCK] = {
.m_sel_id = CLK_TOP_I2S1_M_SEL,
.div_clk_id = CLK_TOP_APLL12_DIV1,
.div_pdn_reg = CLK_AUDDIV_0,
.div_pdn_mask_sft = APLL12_DIV1_PDN_MASK_SFT,
.div_reg = CLK_AUDDIV_2,
.div_mask_sft = APLL12_CK_DIV1_MASK_SFT,
.div_mask = APLL12_CK_DIV1_MASK,
.div_sft = APLL12_CK_DIV1_SFT,
.div_apll_sel_reg = CLK_AUDDIV_0,
.div_apll_sel_mask_sft = APLL_I2S1_MCK_SEL_MASK_SFT,
.div_apll_sel_sft = APLL_I2S1_MCK_SEL_SFT,
},
[MT8192_I2S2_MCK] = {
.m_sel_id = CLK_TOP_I2S2_M_SEL,
.div_clk_id = CLK_TOP_APLL12_DIV2,
.div_pdn_reg = CLK_AUDDIV_0,
.div_pdn_mask_sft = APLL12_DIV2_PDN_MASK_SFT,
.div_reg = CLK_AUDDIV_2,
.div_mask_sft = APLL12_CK_DIV2_MASK_SFT,
.div_mask = APLL12_CK_DIV2_MASK,
.div_sft = APLL12_CK_DIV2_SFT,
.div_apll_sel_reg = CLK_AUDDIV_0,
.div_apll_sel_mask_sft = APLL_I2S2_MCK_SEL_MASK_SFT,
.div_apll_sel_sft = APLL_I2S2_MCK_SEL_SFT,
},
[MT8192_I2S3_MCK] = {
.m_sel_id = CLK_TOP_I2S3_M_SEL,
.div_clk_id = CLK_TOP_APLL12_DIV3,
.div_pdn_reg = CLK_AUDDIV_0,
.div_pdn_mask_sft = APLL12_DIV3_PDN_MASK_SFT,
.div_reg = CLK_AUDDIV_2,
.div_mask_sft = APLL12_CK_DIV3_MASK_SFT,
.div_mask = APLL12_CK_DIV3_MASK,
.div_sft = APLL12_CK_DIV3_SFT,
.div_apll_sel_reg = CLK_AUDDIV_0,
.div_apll_sel_mask_sft = APLL_I2S3_MCK_SEL_MASK_SFT,
.div_apll_sel_sft = APLL_I2S3_MCK_SEL_SFT,
},
[MT8192_I2S4_MCK] = {
.m_sel_id = CLK_TOP_I2S4_M_SEL,
.div_clk_id = CLK_TOP_APLL12_DIV4,
.div_pdn_reg = CLK_AUDDIV_0,
.div_pdn_mask_sft = APLL12_DIV4_PDN_MASK_SFT,
.div_reg = CLK_AUDDIV_3,
.div_mask_sft = APLL12_CK_DIV4_MASK_SFT,
.div_mask = APLL12_CK_DIV4_MASK,
.div_sft = APLL12_CK_DIV4_SFT,
.div_apll_sel_reg = CLK_AUDDIV_0,
.div_apll_sel_mask_sft = APLL_I2S4_MCK_SEL_MASK_SFT,
.div_apll_sel_sft = APLL_I2S4_MCK_SEL_SFT,
},
[MT8192_I2S4_BCK] = {
.m_sel_id = -1,
.div_clk_id = CLK_TOP_APLL12_DIVB,
.div_pdn_reg = CLK_AUDDIV_0,
.div_pdn_mask_sft = APLL12_DIVB_PDN_MASK_SFT,
.div_reg = CLK_AUDDIV_2,
.div_mask_sft = APLL12_CK_DIVB_MASK_SFT,
.div_mask = APLL12_CK_DIVB_MASK,
.div_sft = APLL12_CK_DIVB_SFT,
},
[MT8192_I2S5_MCK] = {
.m_sel_id = CLK_TOP_I2S5_M_SEL,
.div_clk_id = CLK_TOP_APLL12_DIV5,
.div_pdn_reg = CLK_AUDDIV_0,
.div_pdn_mask_sft = APLL12_DIV5_PDN_MASK_SFT,
.div_reg = CLK_AUDDIV_3,
.div_mask_sft = APLL12_CK_DIV5_MASK_SFT,
.div_mask = APLL12_CK_DIV5_MASK,
.div_sft = APLL12_CK_DIV5_SFT,
.div_apll_sel_reg = CLK_AUDDIV_0,
.div_apll_sel_mask_sft = APLL_I2S5_MCK_SEL_MASK_SFT,
.div_apll_sel_sft = APLL_I2S5_MCK_SEL_SFT,
},
[MT8192_I2S6_MCK] = {
.m_sel_id = CLK_TOP_I2S6_M_SEL,
.div_clk_id = CLK_TOP_APLL12_DIV6,
.div_pdn_reg = CLK_AUDDIV_0,
.div_pdn_mask_sft = APLL12_DIV6_PDN_MASK_SFT,
.div_reg = CLK_AUDDIV_3,
.div_mask_sft = APLL12_CK_DIV6_MASK_SFT,
.div_mask = APLL12_CK_DIV6_MASK,
.div_sft = APLL12_CK_DIV6_SFT,
.div_apll_sel_reg = CLK_AUDDIV_0,
.div_apll_sel_mask_sft = APLL_I2S6_MCK_SEL_MASK_SFT,
.div_apll_sel_sft = APLL_I2S6_MCK_SEL_SFT,
},
[MT8192_I2S7_MCK] = {
.m_sel_id = CLK_TOP_I2S7_M_SEL,
.div_clk_id = CLK_TOP_APLL12_DIV7,
.div_pdn_reg = CLK_AUDDIV_0,
.div_pdn_mask_sft = APLL12_DIV7_PDN_MASK_SFT,
.div_reg = CLK_AUDDIV_4,
.div_mask_sft = APLL12_CK_DIV7_MASK_SFT,
.div_mask = APLL12_CK_DIV7_MASK,
.div_sft = APLL12_CK_DIV7_SFT,
.div_apll_sel_reg = CLK_AUDDIV_0,
.div_apll_sel_mask_sft = APLL_I2S7_MCK_SEL_MASK_SFT,
.div_apll_sel_sft = APLL_I2S7_MCK_SEL_SFT,
},
[MT8192_I2S8_MCK] = {
.m_sel_id = CLK_TOP_I2S8_M_SEL,
.div_clk_id = CLK_TOP_APLL12_DIV8,
.div_pdn_reg = CLK_AUDDIV_0,
.div_pdn_mask_sft = APLL12_DIV8_PDN_MASK_SFT,
.div_reg = CLK_AUDDIV_4,
.div_mask_sft = APLL12_CK_DIV8_MASK_SFT,
.div_mask = APLL12_CK_DIV8_MASK,
.div_sft = APLL12_CK_DIV8_SFT,
.div_apll_sel_reg = CLK_AUDDIV_0,
.div_apll_sel_mask_sft = APLL_I2S8_MCK_SEL_MASK_SFT,
.div_apll_sel_sft = APLL_I2S8_MCK_SEL_SFT,
},
[MT8192_I2S9_MCK] = {
.m_sel_id = CLK_TOP_I2S9_M_SEL,
.div_clk_id = CLK_TOP_APLL12_DIV9,
.div_pdn_reg = CLK_AUDDIV_0,
.div_pdn_mask_sft = APLL12_DIV9_PDN_MASK_SFT,
.div_reg = CLK_AUDDIV_4,
.div_mask_sft = APLL12_CK_DIV9_MASK_SFT,
.div_mask = APLL12_CK_DIV9_MASK,
.div_sft = APLL12_CK_DIV9_SFT,
.div_apll_sel_reg = CLK_AUDDIV_0,
.div_apll_sel_mask_sft = APLL_I2S9_MCK_SEL_MASK_SFT,
.div_apll_sel_sft = APLL_I2S9_MCK_SEL_SFT,
},
};
int mt8192_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate)
{
struct mt8192_afe_private *afe_priv = afe->platform_priv;
int apll = mt8192_get_apll_by_rate(afe, rate);
int apll_clk_id = apll == MT8192_APLL1 ?
CLK_TOP_MUX_AUD_1 : CLK_TOP_MUX_AUD_2;
int m_sel_id = mck_div[mck_id].m_sel_id;
int div_clk_id = mck_div[mck_id].div_clk_id;
int ret;
/* select apll */
if (m_sel_id >= 0) {
ret = clk_prepare_enable(afe_priv->clk[m_sel_id]);
if (ret) {
dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
__func__, aud_clks[m_sel_id], ret);
return ret;
}
ret = clk_set_parent(afe_priv->clk[m_sel_id],
afe_priv->clk[apll_clk_id]);
if (ret) {
dev_err(afe->dev, "%s(), clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[m_sel_id],
aud_clks[apll_clk_id], ret);
return ret;
}
}
/* enable div, set rate */
ret = clk_prepare_enable(afe_priv->clk[div_clk_id]);
if (ret) {
dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
__func__, aud_clks[div_clk_id], ret);
return ret;
}
ret = clk_set_rate(afe_priv->clk[div_clk_id], rate);
if (ret) {
dev_err(afe->dev, "%s(), clk_set_rate %s, rate %d, fail %d\n",
__func__, aud_clks[div_clk_id],
rate, ret);
return ret;
}
return 0;
}
void mt8192_mck_disable(struct mtk_base_afe *afe, int mck_id)
{
struct mt8192_afe_private *afe_priv = afe->platform_priv;
int m_sel_id = mck_div[mck_id].m_sel_id;
int div_clk_id = mck_div[mck_id].div_clk_id;
clk_disable_unprepare(afe_priv->clk[div_clk_id]);
if (m_sel_id >= 0)
clk_disable_unprepare(afe_priv->clk[m_sel_id]);
}
int mt8192_init_clock(struct mtk_base_afe *afe)
{
struct mt8192_afe_private *afe_priv = afe->platform_priv;
struct device_node *of_node = afe->dev->of_node;
int i = 0;
afe_priv->clk = devm_kcalloc(afe->dev, CLK_NUM, sizeof(*afe_priv->clk),
GFP_KERNEL);
if (!afe_priv->clk)
return -ENOMEM;
for (i = 0; i < CLK_NUM; i++) {
afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);
if (IS_ERR(afe_priv->clk[i])) {
dev_warn(afe->dev, "%s devm_clk_get %s fail, ret %ld\n",
__func__,
aud_clks[i], PTR_ERR(afe_priv->clk[i]));
afe_priv->clk[i] = NULL;
}
}
afe_priv->apmixedsys = syscon_regmap_lookup_by_phandle(of_node,
"mediatek,apmixedsys");
if (IS_ERR(afe_priv->apmixedsys)) {
dev_err(afe->dev, "%s() Cannot find apmixedsys controller: %ld\n",
__func__, PTR_ERR(afe_priv->apmixedsys));
return PTR_ERR(afe_priv->apmixedsys);
}
afe_priv->topckgen = syscon_regmap_lookup_by_phandle(of_node,
"mediatek,topckgen");
if (IS_ERR(afe_priv->topckgen)) {
dev_err(afe->dev, "%s() Cannot find topckgen controller: %ld\n",
__func__, PTR_ERR(afe_priv->topckgen));
return PTR_ERR(afe_priv->topckgen);
}
afe_priv->infracfg = syscon_regmap_lookup_by_phandle(of_node,
"mediatek,infracfg");
if (IS_ERR(afe_priv->infracfg)) {
dev_err(afe->dev, "%s() Cannot find infracfg: %ld\n",
__func__, PTR_ERR(afe_priv->infracfg));
return PTR_ERR(afe_priv->infracfg);
}
return 0;
}
| linux-master | sound/soc/mediatek/mt8192/mt8192-afe-clk.c |
// SPDX-License-Identifier: GPL-2.0
//
// MediaTek ALSA SoC Audio DAI ADDA Control
//
// Copyright (c) 2020 MediaTek Inc.
// Author: Shane Chien <[email protected]>
//
#include <linux/delay.h>
#include <linux/regmap.h>
#include "mt8192-afe-clk.h"
#include "mt8192-afe-common.h"
#include "mt8192-afe-gpio.h"
#include "mt8192-interconnection.h"
enum {
UL_IIR_SW = 0,
UL_IIR_5HZ,
UL_IIR_10HZ,
UL_IIR_25HZ,
UL_IIR_50HZ,
UL_IIR_75HZ,
};
enum {
AUDIO_SDM_LEVEL_MUTE = 0,
AUDIO_SDM_LEVEL_NORMAL = 0x1d,
/* if you change level normal */
/* you need to change formula of hp impedance and dc trim too */
};
enum {
AUDIO_SDM_2ND = 0,
AUDIO_SDM_3RD,
};
enum {
DELAY_DATA_MISO1 = 0,
DELAY_DATA_MISO2,
};
enum {
MTK_AFE_ADDA_DL_RATE_8K = 0,
MTK_AFE_ADDA_DL_RATE_11K = 1,
MTK_AFE_ADDA_DL_RATE_12K = 2,
MTK_AFE_ADDA_DL_RATE_16K = 3,
MTK_AFE_ADDA_DL_RATE_22K = 4,
MTK_AFE_ADDA_DL_RATE_24K = 5,
MTK_AFE_ADDA_DL_RATE_32K = 6,
MTK_AFE_ADDA_DL_RATE_44K = 7,
MTK_AFE_ADDA_DL_RATE_48K = 8,
MTK_AFE_ADDA_DL_RATE_96K = 9,
MTK_AFE_ADDA_DL_RATE_192K = 10,
};
enum {
MTK_AFE_ADDA_UL_RATE_8K = 0,
MTK_AFE_ADDA_UL_RATE_16K = 1,
MTK_AFE_ADDA_UL_RATE_32K = 2,
MTK_AFE_ADDA_UL_RATE_48K = 3,
MTK_AFE_ADDA_UL_RATE_96K = 4,
MTK_AFE_ADDA_UL_RATE_192K = 5,
MTK_AFE_ADDA_UL_RATE_48K_HD = 6,
};
#define SDM_AUTO_RESET_THRESHOLD 0x190000
static unsigned int adda_dl_rate_transform(struct mtk_base_afe *afe,
unsigned int rate)
{
switch (rate) {
case 8000:
return MTK_AFE_ADDA_DL_RATE_8K;
case 11025:
return MTK_AFE_ADDA_DL_RATE_11K;
case 12000:
return MTK_AFE_ADDA_DL_RATE_12K;
case 16000:
return MTK_AFE_ADDA_DL_RATE_16K;
case 22050:
return MTK_AFE_ADDA_DL_RATE_22K;
case 24000:
return MTK_AFE_ADDA_DL_RATE_24K;
case 32000:
return MTK_AFE_ADDA_DL_RATE_32K;
case 44100:
return MTK_AFE_ADDA_DL_RATE_44K;
case 48000:
return MTK_AFE_ADDA_DL_RATE_48K;
case 96000:
return MTK_AFE_ADDA_DL_RATE_96K;
case 192000:
return MTK_AFE_ADDA_DL_RATE_192K;
default:
dev_warn(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
__func__, rate);
return MTK_AFE_ADDA_DL_RATE_48K;
}
}
static unsigned int adda_ul_rate_transform(struct mtk_base_afe *afe,
unsigned int rate)
{
switch (rate) {
case 8000:
return MTK_AFE_ADDA_UL_RATE_8K;
case 16000:
return MTK_AFE_ADDA_UL_RATE_16K;
case 32000:
return MTK_AFE_ADDA_UL_RATE_32K;
case 48000:
return MTK_AFE_ADDA_UL_RATE_48K;
case 96000:
return MTK_AFE_ADDA_UL_RATE_96K;
case 192000:
return MTK_AFE_ADDA_UL_RATE_192K;
default:
dev_warn(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
__func__, rate);
return MTK_AFE_ADDA_UL_RATE_48K;
}
}
/* dai component */
static const struct snd_kcontrol_new mtk_adda_dl_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN3, I_DL1_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1", AFE_CONN3, I_DL12_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN3, I_DL2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN3, I_DL3_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN3_1, I_DL4_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN3_1, I_DL5_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN3_1, I_DL6_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1", AFE_CONN3_1, I_DL8_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN3,
I_ADDA_UL_CH3, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN3,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN3,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1", AFE_CONN3,
I_GAIN1_OUT_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN3,
I_PCM_1_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN3,
I_PCM_2_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH1", AFE_CONN3_1,
I_SRC_1_OUT_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("SRC_2_OUT_CH1", AFE_CONN3_1,
I_SRC_2_OUT_CH1, 1, 0),
};
static const struct snd_kcontrol_new mtk_adda_dl_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN4, I_DL1_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN4, I_DL1_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2", AFE_CONN4, I_DL12_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN4, I_DL2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN4, I_DL2_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN4, I_DL3_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN4, I_DL3_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN4_1, I_DL4_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN4_1, I_DL5_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN4_1, I_DL6_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2", AFE_CONN4_1, I_DL8_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN4,
I_ADDA_UL_CH3, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN4,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN4,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2", AFE_CONN4,
I_GAIN1_OUT_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN4,
I_PCM_1_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN4,
I_PCM_2_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN4,
I_PCM_1_CAP_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN4,
I_PCM_2_CAP_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH2", AFE_CONN4_1,
I_SRC_1_OUT_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("SRC_2_OUT_CH2", AFE_CONN4_1,
I_SRC_2_OUT_CH2, 1, 0),
};
static const struct snd_kcontrol_new mtk_adda_dl_ch3_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN52, I_DL1_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1", AFE_CONN52, I_DL12_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN52, I_DL2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN52, I_DL3_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN52_1, I_DL4_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN52_1, I_DL5_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN52_1, I_DL6_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN52,
I_ADDA_UL_CH3, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN52,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN52,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1", AFE_CONN52,
I_GAIN1_OUT_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN52,
I_PCM_1_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN52,
I_PCM_2_CAP_CH1, 1, 0),
};
static const struct snd_kcontrol_new mtk_adda_dl_ch4_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN53, I_DL1_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN53, I_DL1_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2", AFE_CONN53, I_DL12_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN53, I_DL2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN53, I_DL2_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN53, I_DL3_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN53, I_DL3_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN53_1, I_DL4_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN53_1, I_DL5_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN53_1, I_DL6_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN53,
I_ADDA_UL_CH3, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN53,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN53,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2", AFE_CONN53,
I_GAIN1_OUT_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN53,
I_PCM_1_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN53,
I_PCM_2_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN53,
I_PCM_1_CAP_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN53,
I_PCM_2_CAP_CH2, 1, 0),
};
static const struct snd_kcontrol_new mtk_stf_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN19,
I_ADDA_UL_CH1, 1, 0),
};
static const struct snd_kcontrol_new mtk_stf_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN20,
I_ADDA_UL_CH2, 1, 0),
};
enum {
SUPPLY_SEQ_ADDA_AFE_ON,
SUPPLY_SEQ_ADDA_DL_ON,
SUPPLY_SEQ_ADDA_AUD_PAD_TOP,
SUPPLY_SEQ_ADDA_MTKAIF_CFG,
SUPPLY_SEQ_ADDA6_MTKAIF_CFG,
SUPPLY_SEQ_ADDA_FIFO,
SUPPLY_SEQ_ADDA_AP_DMIC,
SUPPLY_SEQ_ADDA_UL_ON,
};
static int mtk_adda_ul_src_dmic(struct mtk_base_afe *afe, int id)
{
unsigned int reg;
switch (id) {
case MT8192_DAI_ADDA:
case MT8192_DAI_AP_DMIC:
reg = AFE_ADDA_UL_SRC_CON0;
break;
case MT8192_DAI_ADDA_CH34:
case MT8192_DAI_AP_DMIC_CH34:
reg = AFE_ADDA6_UL_SRC_CON0;
break;
default:
return -EINVAL;
}
/* dmic mode, 3.25M*/
regmap_update_bits(afe->regmap, reg,
DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT,
0x0);
regmap_update_bits(afe->regmap, reg,
DMIC_LOW_POWER_MODE_CTL_MASK_SFT,
0x0);
/* turn on dmic, ch1, ch2 */
regmap_update_bits(afe->regmap, reg,
UL_SDM_3_LEVEL_CTL_MASK_SFT,
0x1 << UL_SDM_3_LEVEL_CTL_SFT);
regmap_update_bits(afe->regmap, reg,
UL_MODE_3P25M_CH1_CTL_MASK_SFT,
0x1 << UL_MODE_3P25M_CH1_CTL_SFT);
regmap_update_bits(afe->regmap, reg,
UL_MODE_3P25M_CH2_CTL_MASK_SFT,
0x1 << UL_MODE_3P25M_CH2_CTL_SFT);
return 0;
}
static int mtk_adda_ul_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8192_afe_private *afe_priv = afe->platform_priv;
int mtkaif_dmic = afe_priv->mtkaif_dmic;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
mt8192_afe_gpio_request(afe->dev, true, MT8192_DAI_ADDA, 1);
/* update setting to dmic */
if (mtkaif_dmic) {
/* mtkaif_rxif_data_mode = 1, dmic */
regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0,
0x1, 0x1);
/* dmic mode, 3.25M*/
regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0,
MTKAIF_RXIF_VOICE_MODE_MASK_SFT,
0x0);
mtk_adda_ul_src_dmic(afe, MT8192_DAI_ADDA);
}
break;
case SND_SOC_DAPM_POST_PMD:
/* should delayed 1/fs(smallest is 8k) = 125us before afe off */
usleep_range(125, 135);
mt8192_afe_gpio_request(afe->dev, false, MT8192_DAI_ADDA, 1);
break;
default:
break;
}
return 0;
}
static int mtk_adda_ch34_ul_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8192_afe_private *afe_priv = afe->platform_priv;
int mtkaif_dmic = afe_priv->mtkaif_dmic_ch34;
int mtkaif_adda6_only = afe_priv->mtkaif_adda6_only;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
mt8192_afe_gpio_request(afe->dev, true, MT8192_DAI_ADDA_CH34,
1);
/* update setting to dmic */
if (mtkaif_dmic) {
/* mtkaif_rxif_data_mode = 1, dmic */
regmap_update_bits(afe->regmap,
AFE_ADDA6_MTKAIF_RX_CFG0,
0x1, 0x1);
/* dmic mode, 3.25M*/
regmap_update_bits(afe->regmap,
AFE_ADDA6_MTKAIF_RX_CFG0,
MTKAIF_RXIF_VOICE_MODE_MASK_SFT,
0x0);
mtk_adda_ul_src_dmic(afe, MT8192_DAI_ADDA_CH34);
}
/* when using adda6 without adda enabled,
* RG_ADDA6_MTKAIF_RX_SYNC_WORD2_DISABLE_SFT need to be set or
* data cannot be received.
*/
if (mtkaif_adda6_only) {
regmap_update_bits(afe->regmap,
AFE_ADDA_MTKAIF_SYNCWORD_CFG,
0x1 << 23, 0x1 << 23);
}
break;
case SND_SOC_DAPM_POST_PMD:
/* should delayed 1/fs(smallest is 8k) = 125us before afe off */
usleep_range(125, 135);
mt8192_afe_gpio_request(afe->dev, false, MT8192_DAI_ADDA_CH34,
1);
/* reset dmic */
afe_priv->mtkaif_dmic_ch34 = 0;
if (mtkaif_adda6_only) {
regmap_update_bits(afe->regmap,
AFE_ADDA_MTKAIF_SYNCWORD_CFG,
0x1 << 23, 0x0 << 23);
}
break;
default:
break;
}
return 0;
}
static int mtk_adda_pad_top_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8192_afe_private *afe_priv = afe->platform_priv;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2_CLK_P2)
regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x38);
else
regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x30);
break;
default:
break;
}
return 0;
}
static int mtk_adda_mtkaif_cfg_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8192_afe_private *afe_priv = afe->platform_priv;
int delay_data;
int delay_cycle;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2_CLK_P2) {
/* set protocol 2 */
regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0,
0x00010000);
regmap_write(afe->regmap, AFE_ADDA6_MTKAIF_CFG0,
0x00010000);
if (strcmp(w->name, "ADDA_MTKAIF_CFG") == 0 &&
(afe_priv->mtkaif_chosen_phase[0] < 0 ||
afe_priv->mtkaif_chosen_phase[1] < 0)) {
dev_warn(afe->dev,
"%s(), mtkaif_chosen_phase[0/1]:%d/%d\n",
__func__,
afe_priv->mtkaif_chosen_phase[0],
afe_priv->mtkaif_chosen_phase[1]);
break;
} else if (strcmp(w->name, "ADDA6_MTKAIF_CFG") == 0 &&
afe_priv->mtkaif_chosen_phase[2] < 0) {
dev_warn(afe->dev,
"%s(), mtkaif_chosen_phase[2]:%d\n",
__func__,
afe_priv->mtkaif_chosen_phase[2]);
break;
}
/* mtkaif_rxif_clkinv_adc inverse for calibration */
regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_CFG0,
MTKAIF_RXIF_CLKINV_ADC_MASK_SFT,
0x1 << MTKAIF_RXIF_CLKINV_ADC_SFT);
regmap_update_bits(afe->regmap, AFE_ADDA6_MTKAIF_CFG0,
MTKAIF_RXIF_CLKINV_ADC_MASK_SFT,
0x1 << MTKAIF_RXIF_CLKINV_ADC_SFT);
/* set delay for ch12 */
if (afe_priv->mtkaif_phase_cycle[0] >=
afe_priv->mtkaif_phase_cycle[1]) {
delay_data = DELAY_DATA_MISO1;
delay_cycle = afe_priv->mtkaif_phase_cycle[0] -
afe_priv->mtkaif_phase_cycle[1];
} else {
delay_data = DELAY_DATA_MISO2;
delay_cycle = afe_priv->mtkaif_phase_cycle[1] -
afe_priv->mtkaif_phase_cycle[0];
}
regmap_update_bits(afe->regmap,
AFE_ADDA_MTKAIF_RX_CFG2,
MTKAIF_RXIF_DELAY_DATA_MASK_SFT,
delay_data <<
MTKAIF_RXIF_DELAY_DATA_SFT);
regmap_update_bits(afe->regmap,
AFE_ADDA_MTKAIF_RX_CFG2,
MTKAIF_RXIF_DELAY_CYCLE_MASK_SFT,
delay_cycle <<
MTKAIF_RXIF_DELAY_CYCLE_SFT);
/* set delay between ch3 and ch2 */
if (afe_priv->mtkaif_phase_cycle[2] >=
afe_priv->mtkaif_phase_cycle[1]) {
delay_data = DELAY_DATA_MISO1; /* ch3 */
delay_cycle = afe_priv->mtkaif_phase_cycle[2] -
afe_priv->mtkaif_phase_cycle[1];
} else {
delay_data = DELAY_DATA_MISO2; /* ch2 */
delay_cycle = afe_priv->mtkaif_phase_cycle[1] -
afe_priv->mtkaif_phase_cycle[2];
}
regmap_update_bits(afe->regmap,
AFE_ADDA6_MTKAIF_RX_CFG2,
MTKAIF_RXIF_DELAY_DATA_MASK_SFT,
delay_data <<
MTKAIF_RXIF_DELAY_DATA_SFT);
regmap_update_bits(afe->regmap,
AFE_ADDA6_MTKAIF_RX_CFG2,
MTKAIF_RXIF_DELAY_CYCLE_MASK_SFT,
delay_cycle <<
MTKAIF_RXIF_DELAY_CYCLE_SFT);
} else if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2) {
regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0,
0x00010000);
regmap_write(afe->regmap, AFE_ADDA6_MTKAIF_CFG0,
0x00010000);
} else {
regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 0x0);
regmap_write(afe->regmap, AFE_ADDA6_MTKAIF_CFG0, 0x0);
}
break;
default:
break;
}
return 0;
}
static int mtk_adda_dl_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
mt8192_afe_gpio_request(afe->dev, true, MT8192_DAI_ADDA, 0);
break;
case SND_SOC_DAPM_POST_PMD:
/* should delayed 1/fs(smallest is 8k) = 125us before afe off */
usleep_range(125, 135);
mt8192_afe_gpio_request(afe->dev, false, MT8192_DAI_ADDA, 0);
break;
default:
break;
}
return 0;
}
static int mtk_adda_ch34_dl_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
mt8192_afe_gpio_request(afe->dev, true, MT8192_DAI_ADDA_CH34,
0);
break;
case SND_SOC_DAPM_POST_PMD:
/* should delayed 1/fs(smallest is 8k) = 125us before afe off */
usleep_range(125, 135);
mt8192_afe_gpio_request(afe->dev, false, MT8192_DAI_ADDA_CH34,
0);
break;
default:
break;
}
return 0;
}
/* stf */
static int stf_positive_gain_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8192_afe_private *afe_priv = afe->platform_priv;
ucontrol->value.integer.value[0] = afe_priv->stf_positive_gain_db;
return 0;
}
static int stf_positive_gain_set(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8192_afe_private *afe_priv = afe->platform_priv;
int gain_db = ucontrol->value.integer.value[0];
bool change = false;
afe_priv->stf_positive_gain_db = gain_db;
if (gain_db >= 0 && gain_db <= 24) {
regmap_update_bits_check(afe->regmap,
AFE_SIDETONE_GAIN,
POSITIVE_GAIN_MASK_SFT,
(gain_db / 6) << POSITIVE_GAIN_SFT,
&change);
} else {
return -EINVAL;
}
return change;
}
static int mt8192_adda_dmic_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8192_afe_private *afe_priv = afe->platform_priv;
ucontrol->value.integer.value[0] = afe_priv->mtkaif_dmic;
return 0;
}
static int mt8192_adda_dmic_set(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8192_afe_private *afe_priv = afe->platform_priv;
int dmic_on;
bool change;
dmic_on = ucontrol->value.integer.value[0];
change = (afe_priv->mtkaif_dmic != dmic_on) ||
(afe_priv->mtkaif_dmic_ch34 != dmic_on);
afe_priv->mtkaif_dmic = dmic_on;
afe_priv->mtkaif_dmic_ch34 = dmic_on;
return change;
}
static int mt8192_adda6_only_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8192_afe_private *afe_priv = afe->platform_priv;
ucontrol->value.integer.value[0] = afe_priv->mtkaif_adda6_only;
return 0;
}
static int mt8192_adda6_only_set(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8192_afe_private *afe_priv = afe->platform_priv;
int mtkaif_adda6_only;
bool change;
mtkaif_adda6_only = ucontrol->value.integer.value[0];
change = afe_priv->mtkaif_adda6_only != mtkaif_adda6_only;
afe_priv->mtkaif_adda6_only = mtkaif_adda6_only;
return change;
}
static const struct snd_kcontrol_new mtk_adda_controls[] = {
SOC_SINGLE("Sidetone_Gain", AFE_SIDETONE_GAIN,
SIDE_TONE_GAIN_SFT, SIDE_TONE_GAIN_MASK, 0),
SOC_SINGLE_EXT("Sidetone_Positive_Gain_dB", SND_SOC_NOPM, 0, 24, 0,
stf_positive_gain_get, stf_positive_gain_set),
SOC_SINGLE("ADDA_DL_GAIN", AFE_ADDA_DL_SRC2_CON1,
DL_2_GAIN_CTL_PRE_SFT, DL_2_GAIN_CTL_PRE_MASK, 0),
SOC_SINGLE_BOOL_EXT("MTKAIF_DMIC Switch", 0,
mt8192_adda_dmic_get, mt8192_adda_dmic_set),
SOC_SINGLE_BOOL_EXT("MTKAIF_ADDA6_ONLY Switch", 0,
mt8192_adda6_only_get, mt8192_adda6_only_set),
};
static const struct snd_kcontrol_new stf_ctl =
SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0);
static const u16 stf_coeff_table_16k[] = {
0x049C, 0x09E8, 0x09E0, 0x089C,
0xFF54, 0xF488, 0xEAFC, 0xEBAC,
0xfA40, 0x17AC, 0x3D1C, 0x6028,
0x7538
};
static const u16 stf_coeff_table_32k[] = {
0xFE52, 0x0042, 0x00C5, 0x0194,
0x029A, 0x03B7, 0x04BF, 0x057D,
0x05BE, 0x0555, 0x0426, 0x0230,
0xFF92, 0xFC89, 0xF973, 0xF6C6,
0xF500, 0xF49D, 0xF603, 0xF970,
0xFEF3, 0x065F, 0x0F4F, 0x1928,
0x2329, 0x2C80, 0x345E, 0x3A0D,
0x3D08
};
static const u16 stf_coeff_table_48k[] = {
0x0401, 0xFFB0, 0xFF5A, 0xFECE,
0xFE10, 0xFD28, 0xFC21, 0xFB08,
0xF9EF, 0xF8E8, 0xF80A, 0xF76C,
0xF724, 0xF746, 0xF7E6, 0xF90F,
0xFACC, 0xFD1E, 0xFFFF, 0x0364,
0x0737, 0x0B62, 0x0FC1, 0x1431,
0x188A, 0x1CA4, 0x2056, 0x237D,
0x25F9, 0x27B0, 0x2890
};
static int mtk_stf_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
size_t half_tap_num;
const u16 *stf_coeff_table;
unsigned int ul_rate, reg_value;
size_t coef_addr;
regmap_read(afe->regmap, AFE_ADDA_UL_SRC_CON0, &ul_rate);
ul_rate = ul_rate >> UL_VOICE_MODE_CH1_CH2_CTL_SFT;
ul_rate = ul_rate & UL_VOICE_MODE_CH1_CH2_CTL_MASK;
if (ul_rate == MTK_AFE_ADDA_UL_RATE_48K) {
half_tap_num = ARRAY_SIZE(stf_coeff_table_48k);
stf_coeff_table = stf_coeff_table_48k;
} else if (ul_rate == MTK_AFE_ADDA_UL_RATE_32K) {
half_tap_num = ARRAY_SIZE(stf_coeff_table_32k);
stf_coeff_table = stf_coeff_table_32k;
} else {
half_tap_num = ARRAY_SIZE(stf_coeff_table_16k);
stf_coeff_table = stf_coeff_table_16k;
}
regmap_read(afe->regmap, AFE_SIDETONE_CON1, ®_value);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* set side tone gain = 0 */
regmap_update_bits(afe->regmap,
AFE_SIDETONE_GAIN,
SIDE_TONE_GAIN_MASK_SFT,
0);
regmap_update_bits(afe->regmap,
AFE_SIDETONE_GAIN,
POSITIVE_GAIN_MASK_SFT,
0);
/* don't bypass stf */
regmap_update_bits(afe->regmap,
AFE_SIDETONE_CON1,
0x1f << 27,
0x0);
/* set stf half tap num */
regmap_update_bits(afe->regmap,
AFE_SIDETONE_CON1,
SIDE_TONE_HALF_TAP_NUM_MASK_SFT,
half_tap_num << SIDE_TONE_HALF_TAP_NUM_SFT);
/* set side tone coefficient */
regmap_read(afe->regmap, AFE_SIDETONE_CON0, ®_value);
for (coef_addr = 0; coef_addr < half_tap_num; coef_addr++) {
bool old_w_ready = (reg_value >> W_RDY_SFT) & 0x1;
bool new_w_ready = 0;
int try_cnt = 0;
regmap_update_bits(afe->regmap,
AFE_SIDETONE_CON0,
0x39FFFFF,
(1 << R_W_EN_SFT) |
(1 << R_W_SEL_SFT) |
(0 << SEL_CH2_SFT) |
(coef_addr <<
SIDE_TONE_COEFFICIENT_ADDR_SFT) |
stf_coeff_table[coef_addr]);
/* wait until flag write_ready changed */
for (try_cnt = 0; try_cnt < 10; try_cnt++) {
regmap_read(afe->regmap,
AFE_SIDETONE_CON0, ®_value);
new_w_ready = (reg_value >> W_RDY_SFT) & 0x1;
/* flip => ok */
if (new_w_ready == old_w_ready) {
udelay(3);
if (try_cnt == 9) {
dev_warn(afe->dev,
"%s(), write coeff not ready",
__func__);
}
} else {
break;
}
}
/* need write -> read -> write to write next coeff */
regmap_update_bits(afe->regmap,
AFE_SIDETONE_CON0,
R_W_SEL_MASK_SFT,
0x0);
}
break;
case SND_SOC_DAPM_POST_PMD:
/* bypass stf */
regmap_update_bits(afe->regmap,
AFE_SIDETONE_CON1,
0x1f << 27,
0x1f << 27);
/* set side tone gain = 0 */
regmap_update_bits(afe->regmap,
AFE_SIDETONE_GAIN,
SIDE_TONE_GAIN_MASK_SFT,
0);
regmap_update_bits(afe->regmap,
AFE_SIDETONE_GAIN,
POSITIVE_GAIN_MASK_SFT,
0);
break;
default:
break;
}
return 0;
}
/* stf mux */
enum {
STF_SRC_ADDA_ADDA6 = 0,
STF_SRC_O19O20,
};
static const char *const stf_o19o20_mux_map[] = {
"ADDA_ADDA6",
"O19O20",
};
static int stf_o19o20_mux_map_value[] = {
STF_SRC_ADDA_ADDA6,
STF_SRC_O19O20,
};
static SOC_VALUE_ENUM_SINGLE_DECL(stf_o19o20_mux_map_enum,
AFE_SIDETONE_CON1,
STF_SOURCE_FROM_O19O20_SFT,
STF_SOURCE_FROM_O19O20_MASK,
stf_o19o20_mux_map,
stf_o19o20_mux_map_value);
static const struct snd_kcontrol_new stf_o19O20_mux_control =
SOC_DAPM_ENUM("STF_O19O20_MUX", stf_o19o20_mux_map_enum);
enum {
STF_SRC_ADDA = 0,
STF_SRC_ADDA6,
};
static const char *const stf_adda_mux_map[] = {
"ADDA",
"ADDA6",
};
static int stf_adda_mux_map_value[] = {
STF_SRC_ADDA,
STF_SRC_ADDA6,
};
static SOC_VALUE_ENUM_SINGLE_DECL(stf_adda_mux_map_enum,
AFE_SIDETONE_CON1,
STF_O19O20_OUT_EN_SEL_SFT,
STF_O19O20_OUT_EN_SEL_MASK,
stf_adda_mux_map,
stf_adda_mux_map_value);
static const struct snd_kcontrol_new stf_adda_mux_control =
SOC_DAPM_ENUM("STF_ADDA_MUX", stf_adda_mux_map_enum);
/* ADDA UL MUX */
enum {
ADDA_UL_MUX_MTKAIF = 0,
ADDA_UL_MUX_AP_DMIC,
ADDA_UL_MUX_MASK = 0x1,
};
static const char * const adda_ul_mux_map[] = {
"MTKAIF", "AP_DMIC"
};
static int adda_ul_map_value[] = {
ADDA_UL_MUX_MTKAIF,
ADDA_UL_MUX_AP_DMIC,
};
static SOC_VALUE_ENUM_SINGLE_DECL(adda_ul_mux_map_enum,
SND_SOC_NOPM,
0,
ADDA_UL_MUX_MASK,
adda_ul_mux_map,
adda_ul_map_value);
static const struct snd_kcontrol_new adda_ul_mux_control =
SOC_DAPM_ENUM("ADDA_UL_MUX Select", adda_ul_mux_map_enum);
static const struct snd_kcontrol_new adda_ch34_ul_mux_control =
SOC_DAPM_ENUM("ADDA_CH34_UL_MUX Select", adda_ul_mux_map_enum);
static const struct snd_soc_dapm_widget mtk_dai_adda_widgets[] = {
/* inter-connections */
SND_SOC_DAPM_MIXER("ADDA_DL_CH1", SND_SOC_NOPM, 0, 0,
mtk_adda_dl_ch1_mix,
ARRAY_SIZE(mtk_adda_dl_ch1_mix)),
SND_SOC_DAPM_MIXER("ADDA_DL_CH2", SND_SOC_NOPM, 0, 0,
mtk_adda_dl_ch2_mix,
ARRAY_SIZE(mtk_adda_dl_ch2_mix)),
SND_SOC_DAPM_MIXER("ADDA_DL_CH3", SND_SOC_NOPM, 0, 0,
mtk_adda_dl_ch3_mix,
ARRAY_SIZE(mtk_adda_dl_ch3_mix)),
SND_SOC_DAPM_MIXER("ADDA_DL_CH4", SND_SOC_NOPM, 0, 0,
mtk_adda_dl_ch4_mix,
ARRAY_SIZE(mtk_adda_dl_ch4_mix)),
SND_SOC_DAPM_SUPPLY_S("ADDA Enable", SUPPLY_SEQ_ADDA_AFE_ON,
AFE_ADDA_UL_DL_CON0, ADDA_AFE_ON_SFT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ADDA Playback Enable", SUPPLY_SEQ_ADDA_DL_ON,
AFE_ADDA_DL_SRC2_CON0,
DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0,
mtk_adda_dl_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("ADDA CH34 Playback Enable",
SUPPLY_SEQ_ADDA_DL_ON,
AFE_ADDA_3RD_DAC_DL_SRC2_CON0,
DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0,
mtk_adda_ch34_dl_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("ADDA Capture Enable", SUPPLY_SEQ_ADDA_UL_ON,
AFE_ADDA_UL_SRC_CON0,
UL_SRC_ON_TMP_CTL_SFT, 0,
mtk_adda_ul_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("ADDA CH34 Capture Enable", SUPPLY_SEQ_ADDA_UL_ON,
AFE_ADDA6_UL_SRC_CON0,
UL_SRC_ON_TMP_CTL_SFT, 0,
mtk_adda_ch34_ul_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("AUD_PAD_TOP", SUPPLY_SEQ_ADDA_AUD_PAD_TOP,
AFE_AUD_PAD_TOP,
RG_RX_FIFO_ON_SFT, 0,
mtk_adda_pad_top_event,
SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_SUPPLY_S("ADDA_MTKAIF_CFG", SUPPLY_SEQ_ADDA_MTKAIF_CFG,
SND_SOC_NOPM, 0, 0,
mtk_adda_mtkaif_cfg_event,
SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_SUPPLY_S("ADDA6_MTKAIF_CFG", SUPPLY_SEQ_ADDA6_MTKAIF_CFG,
SND_SOC_NOPM, 0, 0,
mtk_adda_mtkaif_cfg_event,
SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_SUPPLY_S("AP_DMIC_EN", SUPPLY_SEQ_ADDA_AP_DMIC,
AFE_ADDA_UL_SRC_CON0,
UL_AP_DMIC_ON_SFT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY_S("AP_DMIC_CH34_EN", SUPPLY_SEQ_ADDA_AP_DMIC,
AFE_ADDA6_UL_SRC_CON0,
UL_AP_DMIC_ON_SFT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ADDA_FIFO", SUPPLY_SEQ_ADDA_FIFO,
AFE_ADDA_UL_DL_CON0,
AFE_ADDA_FIFO_AUTO_RST_SFT, 1,
NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ADDA_CH34_FIFO", SUPPLY_SEQ_ADDA_FIFO,
AFE_ADDA_UL_DL_CON0,
AFE_ADDA6_FIFO_AUTO_RST_SFT, 1,
NULL, 0),
SND_SOC_DAPM_MUX("ADDA_UL_Mux", SND_SOC_NOPM, 0, 0,
&adda_ul_mux_control),
SND_SOC_DAPM_MUX("ADDA_CH34_UL_Mux", SND_SOC_NOPM, 0, 0,
&adda_ch34_ul_mux_control),
SND_SOC_DAPM_INPUT("AP_DMIC_INPUT"),
SND_SOC_DAPM_INPUT("AP_DMIC_CH34_INPUT"),
/* stf */
SND_SOC_DAPM_SWITCH_E("Sidetone Filter",
AFE_SIDETONE_CON1, SIDE_TONE_ON_SFT, 0,
&stf_ctl,
mtk_stf_event,
SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX("STF_O19O20_MUX", SND_SOC_NOPM, 0, 0,
&stf_o19O20_mux_control),
SND_SOC_DAPM_MUX("STF_ADDA_MUX", SND_SOC_NOPM, 0, 0,
&stf_adda_mux_control),
SND_SOC_DAPM_MIXER("STF_CH1", SND_SOC_NOPM, 0, 0,
mtk_stf_ch1_mix,
ARRAY_SIZE(mtk_stf_ch1_mix)),
SND_SOC_DAPM_MIXER("STF_CH2", SND_SOC_NOPM, 0, 0,
mtk_stf_ch2_mix,
ARRAY_SIZE(mtk_stf_ch2_mix)),
SND_SOC_DAPM_OUTPUT("STF_OUTPUT"),
/* clock */
SND_SOC_DAPM_CLOCK_SUPPLY("top_mux_audio_h"),
SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_clk"),
SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_predis_clk"),
SND_SOC_DAPM_CLOCK_SUPPLY("aud_3rd_dac_clk"),
SND_SOC_DAPM_CLOCK_SUPPLY("aud_3rd_dac_predis_clk"),
SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc_clk"),
SND_SOC_DAPM_CLOCK_SUPPLY("aud_adda6_adc_clk"),
};
static const struct snd_soc_dapm_route mtk_dai_adda_routes[] = {
/* playback */
{"ADDA_DL_CH1", "DL1_CH1", "DL1"},
{"ADDA_DL_CH2", "DL1_CH1", "DL1"},
{"ADDA_DL_CH2", "DL1_CH2", "DL1"},
{"ADDA_DL_CH1", "DL12_CH1", "DL12"},
{"ADDA_DL_CH2", "DL12_CH2", "DL12"},
{"ADDA_DL_CH1", "DL6_CH1", "DL6"},
{"ADDA_DL_CH2", "DL6_CH2", "DL6"},
{"ADDA_DL_CH1", "DL8_CH1", "DL8"},
{"ADDA_DL_CH2", "DL8_CH2", "DL8"},
{"ADDA_DL_CH1", "DL2_CH1", "DL2"},
{"ADDA_DL_CH2", "DL2_CH1", "DL2"},
{"ADDA_DL_CH2", "DL2_CH2", "DL2"},
{"ADDA_DL_CH1", "DL3_CH1", "DL3"},
{"ADDA_DL_CH2", "DL3_CH1", "DL3"},
{"ADDA_DL_CH2", "DL3_CH2", "DL3"},
{"ADDA_DL_CH1", "DL4_CH1", "DL4"},
{"ADDA_DL_CH2", "DL4_CH2", "DL4"},
{"ADDA_DL_CH1", "DL5_CH1", "DL5"},
{"ADDA_DL_CH2", "DL5_CH2", "DL5"},
{"ADDA Playback", NULL, "ADDA_DL_CH1"},
{"ADDA Playback", NULL, "ADDA_DL_CH2"},
{"ADDA Playback", NULL, "ADDA Enable"},
{"ADDA Playback", NULL, "ADDA Playback Enable"},
{"ADDA_DL_CH3", "DL1_CH1", "DL1"},
{"ADDA_DL_CH4", "DL1_CH1", "DL1"},
{"ADDA_DL_CH4", "DL1_CH2", "DL1"},
{"ADDA_DL_CH3", "DL12_CH1", "DL12"},
{"ADDA_DL_CH4", "DL12_CH2", "DL12"},
{"ADDA_DL_CH3", "DL6_CH1", "DL6"},
{"ADDA_DL_CH4", "DL6_CH2", "DL6"},
{"ADDA_DL_CH3", "DL2_CH1", "DL2"},
{"ADDA_DL_CH4", "DL2_CH1", "DL2"},
{"ADDA_DL_CH4", "DL2_CH2", "DL2"},
{"ADDA_DL_CH3", "DL3_CH1", "DL3"},
{"ADDA_DL_CH4", "DL3_CH1", "DL3"},
{"ADDA_DL_CH4", "DL3_CH2", "DL3"},
{"ADDA_DL_CH3", "DL4_CH1", "DL4"},
{"ADDA_DL_CH4", "DL4_CH2", "DL4"},
{"ADDA_DL_CH3", "DL5_CH1", "DL5"},
{"ADDA_DL_CH4", "DL5_CH2", "DL5"},
{"ADDA CH34 Playback", NULL, "ADDA_DL_CH3"},
{"ADDA CH34 Playback", NULL, "ADDA_DL_CH4"},
{"ADDA CH34 Playback", NULL, "ADDA Enable"},
{"ADDA CH34 Playback", NULL, "ADDA CH34 Playback Enable"},
/* capture */
{"ADDA_UL_Mux", "MTKAIF", "ADDA Capture"},
{"ADDA_UL_Mux", "AP_DMIC", "AP DMIC Capture"},
{"ADDA_CH34_UL_Mux", "MTKAIF", "ADDA CH34 Capture"},
{"ADDA_CH34_UL_Mux", "AP_DMIC", "AP DMIC CH34 Capture"},
{"ADDA Capture", NULL, "ADDA Enable"},
{"ADDA Capture", NULL, "ADDA Capture Enable"},
{"ADDA Capture", NULL, "AUD_PAD_TOP"},
{"ADDA Capture", NULL, "ADDA_MTKAIF_CFG"},
{"AP DMIC Capture", NULL, "ADDA Enable"},
{"AP DMIC Capture", NULL, "ADDA Capture Enable"},
{"AP DMIC Capture", NULL, "ADDA_FIFO"},
{"AP DMIC Capture", NULL, "AP_DMIC_EN"},
{"ADDA CH34 Capture", NULL, "ADDA Enable"},
{"ADDA CH34 Capture", NULL, "ADDA CH34 Capture Enable"},
{"ADDA CH34 Capture", NULL, "AUD_PAD_TOP"},
{"ADDA CH34 Capture", NULL, "ADDA6_MTKAIF_CFG"},
{"AP DMIC CH34 Capture", NULL, "ADDA Enable"},
{"AP DMIC CH34 Capture", NULL, "ADDA CH34 Capture Enable"},
{"AP DMIC CH34 Capture", NULL, "ADDA_CH34_FIFO"},
{"AP DMIC CH34 Capture", NULL, "AP_DMIC_CH34_EN"},
{"AP DMIC Capture", NULL, "AP_DMIC_INPUT"},
{"AP DMIC CH34 Capture", NULL, "AP_DMIC_CH34_INPUT"},
/* sidetone filter */
{"STF_ADDA_MUX", "ADDA", "ADDA_UL_Mux"},
{"STF_ADDA_MUX", "ADDA6", "ADDA_CH34_UL_Mux"},
{"STF_O19O20_MUX", "ADDA_ADDA6", "STF_ADDA_MUX"},
{"STF_O19O20_MUX", "O19O20", "STF_CH1"},
{"STF_O19O20_MUX", "O19O20", "STF_CH2"},
{"Sidetone Filter", "Switch", "STF_O19O20_MUX"},
{"STF_OUTPUT", NULL, "Sidetone Filter"},
{"ADDA Playback", NULL, "Sidetone Filter"},
{"ADDA CH34 Playback", NULL, "Sidetone Filter"},
/* clk */
{"ADDA Playback", NULL, "aud_dac_clk"},
{"ADDA Playback", NULL, "aud_dac_predis_clk"},
{"ADDA CH34 Playback", NULL, "aud_3rd_dac_clk"},
{"ADDA CH34 Playback", NULL, "aud_3rd_dac_predis_clk"},
{"ADDA Capture Enable", NULL, "aud_adc_clk"},
{"ADDA CH34 Capture Enable", NULL, "aud_adda6_adc_clk"},
};
/* dai ops */
static int mtk_dai_adda_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
unsigned int rate = params_rate(params);
int id = dai->id;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
unsigned int dl_src2_con0 = 0;
unsigned int dl_src2_con1 = 0;
/* set sampling rate */
dl_src2_con0 = adda_dl_rate_transform(afe, rate) <<
DL_2_INPUT_MODE_CTL_SFT;
/* set output mode, UP_SAMPLING_RATE_X8 */
dl_src2_con0 |= (0x3 << DL_2_OUTPUT_SEL_CTL_SFT);
/* turn off mute function */
dl_src2_con0 |= (0x01 << DL_2_MUTE_CH2_OFF_CTL_PRE_SFT);
dl_src2_con0 |= (0x01 << DL_2_MUTE_CH1_OFF_CTL_PRE_SFT);
/* set voice input data if input sample rate is 8k or 16k */
if (rate == 8000 || rate == 16000)
dl_src2_con0 |= 0x01 << DL_2_VOICE_MODE_CTL_PRE_SFT;
/* SA suggest apply -0.3db to audio/speech path */
dl_src2_con1 = MTK_AFE_ADDA_DL_GAIN_NORMAL <<
DL_2_GAIN_CTL_PRE_SFT;
/* turn on down-link gain */
dl_src2_con0 |= (0x01 << DL_2_GAIN_ON_CTL_PRE_SFT);
if (id == MT8192_DAI_ADDA) {
/* clean predistortion */
regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON0, 0);
regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON1, 0);
regmap_write(afe->regmap,
AFE_ADDA_DL_SRC2_CON0, dl_src2_con0);
regmap_write(afe->regmap,
AFE_ADDA_DL_SRC2_CON1, dl_src2_con1);
/* set sdm gain */
regmap_update_bits(afe->regmap,
AFE_ADDA_DL_SDM_DCCOMP_CON,
ATTGAIN_CTL_MASK_SFT,
AUDIO_SDM_LEVEL_NORMAL <<
ATTGAIN_CTL_SFT);
/* 2nd sdm */
regmap_update_bits(afe->regmap,
AFE_ADDA_DL_SDM_DCCOMP_CON,
USE_3RD_SDM_MASK_SFT,
AUDIO_SDM_2ND << USE_3RD_SDM_SFT);
/* sdm auto reset */
regmap_write(afe->regmap,
AFE_ADDA_DL_SDM_AUTO_RESET_CON,
SDM_AUTO_RESET_THRESHOLD);
regmap_update_bits(afe->regmap,
AFE_ADDA_DL_SDM_AUTO_RESET_CON,
ADDA_SDM_AUTO_RESET_ONOFF_MASK_SFT,
0x1 << ADDA_SDM_AUTO_RESET_ONOFF_SFT);
} else {
/* clean predistortion */
regmap_write(afe->regmap,
AFE_ADDA_3RD_DAC_PREDIS_CON0, 0);
regmap_write(afe->regmap,
AFE_ADDA_3RD_DAC_PREDIS_CON1, 0);
regmap_write(afe->regmap, AFE_ADDA_3RD_DAC_DL_SRC2_CON0,
dl_src2_con0);
regmap_write(afe->regmap, AFE_ADDA_3RD_DAC_DL_SRC2_CON1,
dl_src2_con1);
/* set sdm gain */
regmap_update_bits(afe->regmap,
AFE_ADDA_3RD_DAC_DL_SDM_DCCOMP_CON,
ATTGAIN_CTL_MASK_SFT,
AUDIO_SDM_LEVEL_NORMAL <<
ATTGAIN_CTL_SFT);
/* 2nd sdm */
regmap_update_bits(afe->regmap,
AFE_ADDA_3RD_DAC_DL_SDM_DCCOMP_CON,
USE_3RD_SDM_MASK_SFT,
AUDIO_SDM_2ND << USE_3RD_SDM_SFT);
/* sdm auto reset */
regmap_write(afe->regmap,
AFE_ADDA_3RD_DAC_DL_SDM_AUTO_RESET_CON,
SDM_AUTO_RESET_THRESHOLD);
regmap_update_bits(afe->regmap,
AFE_ADDA_3RD_DAC_DL_SDM_AUTO_RESET_CON,
ADDA_3RD_DAC_SDM_AUTO_RESET_ONOFF_MASK_SFT,
0x1 << ADDA_3RD_DAC_SDM_AUTO_RESET_ONOFF_SFT);
}
} else {
unsigned int voice_mode = 0;
unsigned int ul_src_con0 = 0; /* default value */
voice_mode = adda_ul_rate_transform(afe, rate);
ul_src_con0 |= (voice_mode << 17) & (0x7 << 17);
/* enable iir */
ul_src_con0 |= (1 << UL_IIR_ON_TMP_CTL_SFT) &
UL_IIR_ON_TMP_CTL_MASK_SFT;
ul_src_con0 |= (UL_IIR_SW << UL_IIRMODE_CTL_SFT) &
UL_IIRMODE_CTL_MASK_SFT;
switch (id) {
case MT8192_DAI_ADDA:
case MT8192_DAI_AP_DMIC:
/* 35Hz @ 48k */
regmap_write(afe->regmap,
AFE_ADDA_IIR_COEF_02_01, 0x00000000);
regmap_write(afe->regmap,
AFE_ADDA_IIR_COEF_04_03, 0x00003FB8);
regmap_write(afe->regmap,
AFE_ADDA_IIR_COEF_06_05, 0x3FB80000);
regmap_write(afe->regmap,
AFE_ADDA_IIR_COEF_08_07, 0x3FB80000);
regmap_write(afe->regmap,
AFE_ADDA_IIR_COEF_10_09, 0x0000C048);
regmap_write(afe->regmap,
AFE_ADDA_UL_SRC_CON0, ul_src_con0);
/* Using Internal ADC */
regmap_update_bits(afe->regmap,
AFE_ADDA_TOP_CON0,
0x1 << 0,
0x0 << 0);
/* mtkaif_rxif_data_mode = 0, amic */
regmap_update_bits(afe->regmap,
AFE_ADDA_MTKAIF_RX_CFG0,
0x1 << 0,
0x0 << 0);
break;
case MT8192_DAI_ADDA_CH34:
case MT8192_DAI_AP_DMIC_CH34:
/* 35Hz @ 48k */
regmap_write(afe->regmap,
AFE_ADDA6_IIR_COEF_02_01, 0x00000000);
regmap_write(afe->regmap,
AFE_ADDA6_IIR_COEF_04_03, 0x00003FB8);
regmap_write(afe->regmap,
AFE_ADDA6_IIR_COEF_06_05, 0x3FB80000);
regmap_write(afe->regmap,
AFE_ADDA6_IIR_COEF_08_07, 0x3FB80000);
regmap_write(afe->regmap,
AFE_ADDA6_IIR_COEF_10_09, 0x0000C048);
regmap_write(afe->regmap,
AFE_ADDA6_UL_SRC_CON0, ul_src_con0);
/* Using Internal ADC */
regmap_update_bits(afe->regmap,
AFE_ADDA6_TOP_CON0,
0x1 << 0,
0x0 << 0);
/* mtkaif_rxif_data_mode = 0, amic */
regmap_update_bits(afe->regmap,
AFE_ADDA6_MTKAIF_RX_CFG0,
0x1 << 0,
0x0 << 0);
break;
default:
break;
}
/* ap dmic */
switch (id) {
case MT8192_DAI_AP_DMIC:
case MT8192_DAI_AP_DMIC_CH34:
mtk_adda_ul_src_dmic(afe, id);
break;
default:
break;
}
}
return 0;
}
static const struct snd_soc_dai_ops mtk_dai_adda_ops = {
.hw_params = mtk_dai_adda_hw_params,
};
/* dai driver */
#define MTK_ADDA_PLAYBACK_RATES (SNDRV_PCM_RATE_8000_48000 |\
SNDRV_PCM_RATE_96000 |\
SNDRV_PCM_RATE_192000)
#define MTK_ADDA_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 |\
SNDRV_PCM_RATE_48000 |\
SNDRV_PCM_RATE_96000 |\
SNDRV_PCM_RATE_192000)
#define MTK_ADDA_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver mtk_dai_adda_driver[] = {
{
.name = "ADDA",
.id = MT8192_DAI_ADDA,
.playback = {
.stream_name = "ADDA Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_ADDA_PLAYBACK_RATES,
.formats = MTK_ADDA_FORMATS,
},
.capture = {
.stream_name = "ADDA Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_ADDA_CAPTURE_RATES,
.formats = MTK_ADDA_FORMATS,
},
.ops = &mtk_dai_adda_ops,
},
{
.name = "ADDA_CH34",
.id = MT8192_DAI_ADDA_CH34,
.playback = {
.stream_name = "ADDA CH34 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_ADDA_PLAYBACK_RATES,
.formats = MTK_ADDA_FORMATS,
},
.capture = {
.stream_name = "ADDA CH34 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_ADDA_CAPTURE_RATES,
.formats = MTK_ADDA_FORMATS,
},
.ops = &mtk_dai_adda_ops,
},
{
.name = "AP_DMIC",
.id = MT8192_DAI_AP_DMIC,
.capture = {
.stream_name = "AP DMIC Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_ADDA_CAPTURE_RATES,
.formats = MTK_ADDA_FORMATS,
},
.ops = &mtk_dai_adda_ops,
},
{
.name = "AP_DMIC_CH34",
.id = MT8192_DAI_AP_DMIC_CH34,
.capture = {
.stream_name = "AP DMIC CH34 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_ADDA_CAPTURE_RATES,
.formats = MTK_ADDA_FORMATS,
},
.ops = &mtk_dai_adda_ops,
},
};
int mt8192_dai_adda_register(struct mtk_base_afe *afe)
{
struct mtk_base_afe_dai *dai;
struct mt8192_afe_private *afe_priv = afe->platform_priv;
dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
if (!dai)
return -ENOMEM;
list_add(&dai->list, &afe->sub_dais);
dai->dai_drivers = mtk_dai_adda_driver;
dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_adda_driver);
dai->controls = mtk_adda_controls;
dai->num_controls = ARRAY_SIZE(mtk_adda_controls);
dai->dapm_widgets = mtk_dai_adda_widgets;
dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_adda_widgets);
dai->dapm_routes = mtk_dai_adda_routes;
dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_adda_routes);
/* ap dmic priv share with adda */
afe_priv->dai_priv[MT8192_DAI_AP_DMIC] =
afe_priv->dai_priv[MT8192_DAI_ADDA];
afe_priv->dai_priv[MT8192_DAI_AP_DMIC_CH34] =
afe_priv->dai_priv[MT8192_DAI_ADDA_CH34];
return 0;
}
| linux-master | sound/soc/mediatek/mt8192/mt8192-dai-adda.c |
// SPDX-License-Identifier: GPL-2.0
//
// Mediatek ALSA SoC AFE platform driver for 8192
//
// Copyright (c) 2020 MediaTek Inc.
// Author: Shane Chien <[email protected]>
//
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/module.h>
#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/pm_runtime.h>
#include <linux/reset.h>
#include <sound/soc.h>
#include "../common/mtk-afe-fe-dai.h"
#include "../common/mtk-afe-platform-driver.h"
#include "mt8192-afe-common.h"
#include "mt8192-afe-clk.h"
#include "mt8192-afe-gpio.h"
#include "mt8192-interconnection.h"
static const struct snd_pcm_hardware mt8192_afe_hardware = {
.info = (SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_MMAP_VALID),
.formats = (SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE |
SNDRV_PCM_FMTBIT_S32_LE),
.period_bytes_min = 96,
.period_bytes_max = 4 * 48 * 1024,
.periods_min = 2,
.periods_max = 256,
.buffer_bytes_max = 4 * 48 * 1024,
.fifo_size = 0,
};
static int mt8192_memif_fs(struct snd_pcm_substream *substream,
unsigned int rate)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_component *component =
snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
int id = asoc_rtd_to_cpu(rtd, 0)->id;
return mt8192_rate_transform(afe->dev, rate, id);
}
static int mt8192_get_dai_fs(struct mtk_base_afe *afe,
int dai_id, unsigned int rate)
{
return mt8192_rate_transform(afe->dev, rate, dai_id);
}
static int mt8192_irq_fs(struct snd_pcm_substream *substream, unsigned int rate)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_component *component =
snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
return mt8192_general_rate_transform(afe->dev, rate);
}
static int mt8192_get_memif_pbuf_size(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
if ((runtime->period_size * 1000) / runtime->rate > 10)
return MT8192_MEMIF_PBUF_SIZE_256_BYTES;
else
return MT8192_MEMIF_PBUF_SIZE_32_BYTES;
}
#define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\
SNDRV_PCM_RATE_88200 |\
SNDRV_PCM_RATE_96000 |\
SNDRV_PCM_RATE_176400 |\
SNDRV_PCM_RATE_192000)
#define MTK_PCM_DAI_RATES (SNDRV_PCM_RATE_8000 |\
SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 |\
SNDRV_PCM_RATE_48000)
#define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver mt8192_memif_dai_driver[] = {
/* FE DAIs: memory intefaces to CPU */
{
.name = "DL1",
.id = MT8192_MEMIF_DL1,
.playback = {
.stream_name = "DL1",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_afe_fe_ops,
},
{
.name = "DL12",
.id = MT8192_MEMIF_DL12,
.playback = {
.stream_name = "DL12",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_afe_fe_ops,
},
{
.name = "DL2",
.id = MT8192_MEMIF_DL2,
.playback = {
.stream_name = "DL2",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_afe_fe_ops,
},
{
.name = "DL3",
.id = MT8192_MEMIF_DL3,
.playback = {
.stream_name = "DL3",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_afe_fe_ops,
},
{
.name = "DL4",
.id = MT8192_MEMIF_DL4,
.playback = {
.stream_name = "DL4",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_afe_fe_ops,
},
{
.name = "DL5",
.id = MT8192_MEMIF_DL5,
.playback = {
.stream_name = "DL5",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_afe_fe_ops,
},
{
.name = "DL6",
.id = MT8192_MEMIF_DL6,
.playback = {
.stream_name = "DL6",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_afe_fe_ops,
},
{
.name = "DL7",
.id = MT8192_MEMIF_DL7,
.playback = {
.stream_name = "DL7",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_afe_fe_ops,
},
{
.name = "DL8",
.id = MT8192_MEMIF_DL8,
.playback = {
.stream_name = "DL8",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_afe_fe_ops,
},
{
.name = "DL9",
.id = MT8192_MEMIF_DL9,
.playback = {
.stream_name = "DL9",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_afe_fe_ops,
},
{
.name = "UL1",
.id = MT8192_MEMIF_VUL12,
.capture = {
.stream_name = "UL1",
.channels_min = 1,
.channels_max = 4,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_afe_fe_ops,
},
{
.name = "UL2",
.id = MT8192_MEMIF_AWB,
.capture = {
.stream_name = "UL2",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_afe_fe_ops,
},
{
.name = "UL3",
.id = MT8192_MEMIF_VUL2,
.capture = {
.stream_name = "UL3",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_afe_fe_ops,
},
{
.name = "UL4",
.id = MT8192_MEMIF_AWB2,
.capture = {
.stream_name = "UL4",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_afe_fe_ops,
},
{
.name = "UL5",
.id = MT8192_MEMIF_VUL3,
.capture = {
.stream_name = "UL5",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_afe_fe_ops,
},
{
.name = "UL6",
.id = MT8192_MEMIF_VUL4,
.capture = {
.stream_name = "UL6",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_afe_fe_ops,
},
{
.name = "UL7",
.id = MT8192_MEMIF_VUL5,
.capture = {
.stream_name = "UL7",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_afe_fe_ops,
},
{
.name = "UL8",
.id = MT8192_MEMIF_VUL6,
.capture = {
.stream_name = "UL8",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_afe_fe_ops,
},
{
.name = "UL_MONO_1",
.id = MT8192_MEMIF_MOD_DAI,
.capture = {
.stream_name = "UL_MONO_1",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_DAI_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_afe_fe_ops,
},
{
.name = "UL_MONO_2",
.id = MT8192_MEMIF_DAI,
.capture = {
.stream_name = "UL_MONO_2",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_DAI_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_afe_fe_ops,
},
{
.name = "UL_MONO_3",
.id = MT8192_MEMIF_DAI2,
.capture = {
.stream_name = "UL_MONO_3",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_DAI_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_afe_fe_ops,
},
{
.name = "HDMI",
.id = MT8192_MEMIF_HDMI,
.playback = {
.stream_name = "HDMI",
.channels_min = 2,
.channels_max = 8,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_afe_fe_ops,
},
};
static int ul_tinyconn_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
unsigned int reg_shift;
unsigned int reg_mask_shift;
dev_dbg(afe->dev, "%s(), event 0x%x\n", __func__, event);
if (strstr(w->name, "UL1")) {
reg_shift = VUL1_USE_TINY_SFT;
reg_mask_shift = VUL1_USE_TINY_MASK_SFT;
} else if (strstr(w->name, "UL2")) {
reg_shift = VUL2_USE_TINY_SFT;
reg_mask_shift = VUL2_USE_TINY_MASK_SFT;
} else if (strstr(w->name, "UL3")) {
reg_shift = VUL12_USE_TINY_SFT;
reg_mask_shift = VUL12_USE_TINY_MASK_SFT;
} else if (strstr(w->name, "UL4")) {
reg_shift = AWB2_USE_TINY_SFT;
reg_mask_shift = AWB2_USE_TINY_MASK_SFT;
} else {
reg_shift = AWB2_USE_TINY_SFT;
reg_mask_shift = AWB2_USE_TINY_MASK_SFT;
dev_warn(afe->dev, "%s(), err widget name %s, default use UL4",
__func__, w->name);
}
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
regmap_update_bits(afe->regmap, AFE_MEMIF_CONN, reg_mask_shift,
0x1 << reg_shift);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_update_bits(afe->regmap, AFE_MEMIF_CONN, reg_mask_shift,
0x0 << reg_shift);
break;
default:
break;
}
return 0;
}
/* dma widget & routes*/
static const struct snd_kcontrol_new memif_ul1_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN21,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN21,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN21,
I_ADDA_UL_CH3, 1, 0),
};
static const struct snd_kcontrol_new memif_ul1_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN22,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN22,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN22,
I_ADDA_UL_CH3, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN22,
I_ADDA_UL_CH4, 1, 0),
};
static const struct snd_kcontrol_new memif_ul1_ch3_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN9,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN9,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN9,
I_ADDA_UL_CH3, 1, 0),
};
static const struct snd_kcontrol_new memif_ul1_ch4_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN10,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN10,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN10,
I_ADDA_UL_CH3, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN10,
I_ADDA_UL_CH4, 1, 0),
};
static const struct snd_kcontrol_new memif_ul2_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1", AFE_CONN5,
I_I2S0_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN5,
I_DL1_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1", AFE_CONN5,
I_DL12_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN5,
I_DL2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN5,
I_DL3_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN5_1,
I_DL4_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN5_1,
I_DL5_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN5_1,
I_DL6_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN5,
I_PCM_1_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN5,
I_PCM_2_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1", AFE_CONN5,
I_I2S2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I2S6_CH1", AFE_CONN5_1,
I_I2S6_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I2S8_CH1", AFE_CONN5_1,
I_I2S8_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("CONNSYS_I2S_CH1", AFE_CONN5_1,
I_CONNSYS_I2S_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH1", AFE_CONN5_1,
I_SRC_1_OUT_CH1, 1, 0),
};
static const struct snd_kcontrol_new memif_ul2_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2", AFE_CONN6,
I_I2S0_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN6,
I_DL1_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2", AFE_CONN6,
I_DL12_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN6,
I_DL2_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN6,
I_DL3_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN6_1,
I_DL4_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN6_1,
I_DL5_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN6_1,
I_DL6_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN6,
I_PCM_1_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN6,
I_PCM_2_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2", AFE_CONN6,
I_I2S2_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I2S6_CH2", AFE_CONN6_1,
I_I2S6_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I2S8_CH2", AFE_CONN6_1,
I_I2S8_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("CONNSYS_I2S_CH2", AFE_CONN6_1,
I_CONNSYS_I2S_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH2", AFE_CONN6_1,
I_SRC_1_OUT_CH2, 1, 0),
};
static const struct snd_kcontrol_new memif_ul3_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("CONNSYS_I2S_CH1", AFE_CONN32_1,
I_CONNSYS_I2S_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN32,
I_DL1_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN32,
I_DL2_CH1, 1, 0),
};
static const struct snd_kcontrol_new memif_ul3_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("CONNSYS_I2S_CH2", AFE_CONN33_1,
I_CONNSYS_I2S_CH2, 1, 0),
};
static const struct snd_kcontrol_new memif_ul4_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN38,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1", AFE_CONN38,
I_I2S0_CH1, 1, 0),
};
static const struct snd_kcontrol_new memif_ul4_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN39,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2", AFE_CONN39,
I_I2S0_CH2, 1, 0),
};
static const struct snd_kcontrol_new memif_ul5_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN44,
I_ADDA_UL_CH1, 1, 0),
};
static const struct snd_kcontrol_new memif_ul5_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN45,
I_ADDA_UL_CH2, 1, 0),
};
static const struct snd_kcontrol_new memif_ul6_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN46,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN46,
I_DL1_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1", AFE_CONN46,
I_DL12_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN46_1,
I_DL6_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN46,
I_DL2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN46,
I_DL3_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN46_1,
I_DL4_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN46,
I_PCM_1_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN46,
I_PCM_2_CAP_CH1, 1, 0),
};
static const struct snd_kcontrol_new memif_ul6_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN47,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN47,
I_DL1_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2", AFE_CONN47,
I_DL12_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN47_1,
I_DL6_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN47,
I_DL2_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN47,
I_DL3_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN47_1,
I_DL4_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN47,
I_PCM_1_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN47,
I_PCM_2_CAP_CH1, 1, 0),
};
static const struct snd_kcontrol_new memif_ul7_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN48,
I_ADDA_UL_CH1, 1, 0),
};
static const struct snd_kcontrol_new memif_ul7_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN49,
I_ADDA_UL_CH2, 1, 0),
};
static const struct snd_kcontrol_new memif_ul8_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN50,
I_ADDA_UL_CH1, 1, 0),
};
static const struct snd_kcontrol_new memif_ul8_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN51,
I_ADDA_UL_CH2, 1, 0),
};
static const struct snd_kcontrol_new memif_ul_mono_1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN12,
I_PCM_1_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN12,
I_PCM_2_CAP_CH1, 1, 0),
};
static const struct snd_kcontrol_new memif_ul_mono_2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN11,
I_ADDA_UL_CH1, 1, 0),
};
static const struct snd_kcontrol_new memif_ul_mono_3_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN35,
I_ADDA_UL_CH1, 1, 0),
};
/* TINYCONN MUX */
enum {
TINYCONN_CH1_MUX_I2S0 = 0x14,
TINYCONN_CH2_MUX_I2S0 = 0x15,
TINYCONN_CH1_MUX_I2S6 = 0x1a,
TINYCONN_CH2_MUX_I2S6 = 0x1b,
TINYCONN_CH1_MUX_I2S8 = 0x1c,
TINYCONN_CH2_MUX_I2S8 = 0x1d,
TINYCONN_MUX_NONE = 0x1f,
};
static const char * const tinyconn_mux_map[] = {
"NONE",
"I2S0_CH1",
"I2S0_CH2",
"I2S6_CH1",
"I2S6_CH2",
"I2S8_CH1",
"I2S8_CH2",
};
static int tinyconn_mux_map_value[] = {
TINYCONN_MUX_NONE,
TINYCONN_CH1_MUX_I2S0,
TINYCONN_CH2_MUX_I2S0,
TINYCONN_CH1_MUX_I2S6,
TINYCONN_CH2_MUX_I2S6,
TINYCONN_CH1_MUX_I2S8,
TINYCONN_CH2_MUX_I2S8,
};
static SOC_VALUE_ENUM_SINGLE_DECL(ul4_tinyconn_ch1_mux_map_enum,
AFE_TINY_CONN0,
O_2_CFG_SFT,
O_2_CFG_MASK,
tinyconn_mux_map,
tinyconn_mux_map_value);
static SOC_VALUE_ENUM_SINGLE_DECL(ul4_tinyconn_ch2_mux_map_enum,
AFE_TINY_CONN0,
O_3_CFG_SFT,
O_3_CFG_MASK,
tinyconn_mux_map,
tinyconn_mux_map_value);
static const struct snd_kcontrol_new ul4_tinyconn_ch1_mux_control =
SOC_DAPM_ENUM("UL4_TINYCONN_CH1_MUX", ul4_tinyconn_ch1_mux_map_enum);
static const struct snd_kcontrol_new ul4_tinyconn_ch2_mux_control =
SOC_DAPM_ENUM("UL4_TINYCONN_CH2_MUX", ul4_tinyconn_ch2_mux_map_enum);
static const struct snd_soc_dapm_widget mt8192_memif_widgets[] = {
/* inter-connections */
SND_SOC_DAPM_MIXER("UL1_CH1", SND_SOC_NOPM, 0, 0,
memif_ul1_ch1_mix, ARRAY_SIZE(memif_ul1_ch1_mix)),
SND_SOC_DAPM_MIXER("UL1_CH2", SND_SOC_NOPM, 0, 0,
memif_ul1_ch2_mix, ARRAY_SIZE(memif_ul1_ch2_mix)),
SND_SOC_DAPM_MIXER("UL1_CH3", SND_SOC_NOPM, 0, 0,
memif_ul1_ch3_mix, ARRAY_SIZE(memif_ul1_ch3_mix)),
SND_SOC_DAPM_MIXER("UL1_CH4", SND_SOC_NOPM, 0, 0,
memif_ul1_ch4_mix, ARRAY_SIZE(memif_ul1_ch4_mix)),
SND_SOC_DAPM_MIXER("UL2_CH1", SND_SOC_NOPM, 0, 0,
memif_ul2_ch1_mix, ARRAY_SIZE(memif_ul2_ch1_mix)),
SND_SOC_DAPM_MIXER("UL2_CH2", SND_SOC_NOPM, 0, 0,
memif_ul2_ch2_mix, ARRAY_SIZE(memif_ul2_ch2_mix)),
SND_SOC_DAPM_MIXER("UL3_CH1", SND_SOC_NOPM, 0, 0,
memif_ul3_ch1_mix, ARRAY_SIZE(memif_ul3_ch1_mix)),
SND_SOC_DAPM_MIXER("UL3_CH2", SND_SOC_NOPM, 0, 0,
memif_ul3_ch2_mix, ARRAY_SIZE(memif_ul3_ch2_mix)),
SND_SOC_DAPM_MIXER("UL4_CH1", SND_SOC_NOPM, 0, 0,
memif_ul4_ch1_mix, ARRAY_SIZE(memif_ul4_ch1_mix)),
SND_SOC_DAPM_MIXER("UL4_CH2", SND_SOC_NOPM, 0, 0,
memif_ul4_ch2_mix, ARRAY_SIZE(memif_ul4_ch2_mix)),
SND_SOC_DAPM_MUX_E("UL4_TINYCONN_CH1_MUX", SND_SOC_NOPM, 0, 0,
&ul4_tinyconn_ch1_mux_control,
ul_tinyconn_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_MUX_E("UL4_TINYCONN_CH2_MUX", SND_SOC_NOPM, 0, 0,
&ul4_tinyconn_ch2_mux_control,
ul_tinyconn_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_MIXER("UL5_CH1", SND_SOC_NOPM, 0, 0,
memif_ul5_ch1_mix, ARRAY_SIZE(memif_ul5_ch1_mix)),
SND_SOC_DAPM_MIXER("UL5_CH2", SND_SOC_NOPM, 0, 0,
memif_ul5_ch2_mix, ARRAY_SIZE(memif_ul5_ch2_mix)),
SND_SOC_DAPM_MIXER("UL6_CH1", SND_SOC_NOPM, 0, 0,
memif_ul6_ch1_mix, ARRAY_SIZE(memif_ul6_ch1_mix)),
SND_SOC_DAPM_MIXER("UL6_CH2", SND_SOC_NOPM, 0, 0,
memif_ul6_ch2_mix, ARRAY_SIZE(memif_ul6_ch2_mix)),
SND_SOC_DAPM_MIXER("UL7_CH1", SND_SOC_NOPM, 0, 0,
memif_ul7_ch1_mix, ARRAY_SIZE(memif_ul7_ch1_mix)),
SND_SOC_DAPM_MIXER("UL7_CH2", SND_SOC_NOPM, 0, 0,
memif_ul7_ch2_mix, ARRAY_SIZE(memif_ul7_ch2_mix)),
SND_SOC_DAPM_MIXER("UL8_CH1", SND_SOC_NOPM, 0, 0,
memif_ul8_ch1_mix, ARRAY_SIZE(memif_ul8_ch1_mix)),
SND_SOC_DAPM_MIXER("UL8_CH2", SND_SOC_NOPM, 0, 0,
memif_ul8_ch2_mix, ARRAY_SIZE(memif_ul8_ch2_mix)),
SND_SOC_DAPM_MIXER("UL_MONO_1_CH1", SND_SOC_NOPM, 0, 0,
memif_ul_mono_1_mix,
ARRAY_SIZE(memif_ul_mono_1_mix)),
SND_SOC_DAPM_MIXER("UL_MONO_2_CH1", SND_SOC_NOPM, 0, 0,
memif_ul_mono_2_mix,
ARRAY_SIZE(memif_ul_mono_2_mix)),
SND_SOC_DAPM_MIXER("UL_MONO_3_CH1", SND_SOC_NOPM, 0, 0,
memif_ul_mono_3_mix,
ARRAY_SIZE(memif_ul_mono_3_mix)),
SND_SOC_DAPM_INPUT("UL1_VIRTUAL_INPUT"),
SND_SOC_DAPM_INPUT("UL2_VIRTUAL_INPUT"),
SND_SOC_DAPM_INPUT("UL6_VIRTUAL_INPUT"),
};
static const struct snd_soc_dapm_route mt8192_memif_routes[] = {
{"UL1", NULL, "UL1_CH1"},
{"UL1", NULL, "UL1_CH2"},
{"UL1", NULL, "UL1_CH3"},
{"UL1", NULL, "UL1_CH4"},
{"UL1_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"},
{"UL1_CH1", "ADDA_UL_CH2", "ADDA_UL_Mux"},
{"UL1_CH1", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"},
{"UL1_CH2", "ADDA_UL_CH1", "ADDA_UL_Mux"},
{"UL1_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"},
{"UL1_CH2", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"},
{"UL1_CH2", "ADDA_UL_CH4", "ADDA_CH34_UL_Mux"},
{"UL1_CH3", "ADDA_UL_CH1", "ADDA_UL_Mux"},
{"UL1_CH3", "ADDA_UL_CH2", "ADDA_UL_Mux"},
{"UL1_CH3", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"},
{"UL1_CH4", "ADDA_UL_CH1", "ADDA_UL_Mux"},
{"UL1_CH4", "ADDA_UL_CH2", "ADDA_UL_Mux"},
{"UL1_CH4", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"},
{"UL1_CH4", "ADDA_UL_CH4", "ADDA_CH34_UL_Mux"},
{"UL2", NULL, "UL2_CH1"},
{"UL2", NULL, "UL2_CH2"},
{"UL2_CH1", "I2S0_CH1", "I2S0"},
{"UL2_CH2", "I2S0_CH2", "I2S0"},
{"UL2_CH1", "I2S2_CH1", "I2S2"},
{"UL2_CH2", "I2S2_CH2", "I2S2"},
{"UL2_CH1", "I2S6_CH1", "I2S6"},
{"UL2_CH2", "I2S6_CH2", "I2S6"},
{"UL2_CH1", "I2S8_CH1", "I2S8"},
{"UL2_CH2", "I2S8_CH2", "I2S8"},
{"UL2_CH1", "PCM_1_CAP_CH1", "PCM 1 Capture"},
{"UL2_CH2", "PCM_1_CAP_CH1", "PCM 1 Capture"},
{"UL2_CH1", "PCM_2_CAP_CH1", "PCM 2 Capture"},
{"UL2_CH2", "PCM_2_CAP_CH1", "PCM 2 Capture"},
{"UL_MONO_1", NULL, "UL_MONO_1_CH1"},
{"UL_MONO_1_CH1", "PCM_1_CAP_CH1", "PCM 1 Capture"},
{"UL_MONO_1_CH1", "PCM_2_CAP_CH1", "PCM 2 Capture"},
{"UL_MONO_2", NULL, "UL_MONO_2_CH1"},
{"UL_MONO_2_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"},
{"UL_MONO_3", NULL, "UL_MONO_3_CH1"},
{"UL_MONO_3_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"},
{"UL2_CH1", "CONNSYS_I2S_CH1", "Connsys I2S"},
{"UL2_CH2", "CONNSYS_I2S_CH2", "Connsys I2S"},
{"UL3", NULL, "UL3_CH1"},
{"UL3", NULL, "UL3_CH2"},
{"UL3_CH1", "CONNSYS_I2S_CH1", "Connsys I2S"},
{"UL3_CH2", "CONNSYS_I2S_CH2", "Connsys I2S"},
{"UL4", NULL, "UL4_CH1"},
{"UL4", NULL, "UL4_CH2"},
{"UL4", NULL, "UL4_TINYCONN_CH1_MUX"},
{"UL4", NULL, "UL4_TINYCONN_CH2_MUX"},
{"UL4_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"},
{"UL4_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"},
{"UL4_CH1", "I2S0_CH1", "I2S0"},
{"UL4_CH2", "I2S0_CH2", "I2S0"},
{"UL4_TINYCONN_CH1_MUX", "I2S0_CH1", "I2S0"},
{"UL4_TINYCONN_CH2_MUX", "I2S0_CH2", "I2S0"},
{"UL5", NULL, "UL5_CH1"},
{"UL5", NULL, "UL5_CH2"},
{"UL5_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"},
{"UL5_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"},
{"UL6", NULL, "UL6_CH1"},
{"UL6", NULL, "UL6_CH2"},
{"UL6_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"},
{"UL6_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"},
{"UL6_CH1", "PCM_1_CAP_CH1", "PCM 1 Capture"},
{"UL6_CH2", "PCM_1_CAP_CH1", "PCM 1 Capture"},
{"UL6_CH1", "PCM_2_CAP_CH1", "PCM 2 Capture"},
{"UL6_CH2", "PCM_2_CAP_CH1", "PCM 2 Capture"},
{"UL7", NULL, "UL7_CH1"},
{"UL7", NULL, "UL7_CH2"},
{"UL7_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"},
{"UL7_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"},
{"UL8", NULL, "UL8_CH1"},
{"UL8", NULL, "UL8_CH2"},
{"UL8_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"},
{"UL8_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"},
};
static const struct mtk_base_memif_data memif_data[MT8192_MEMIF_NUM] = {
[MT8192_MEMIF_DL1] = {
.name = "DL1",
.id = MT8192_MEMIF_DL1,
.reg_ofs_base = AFE_DL1_BASE,
.reg_ofs_cur = AFE_DL1_CUR,
.reg_ofs_end = AFE_DL1_END,
.reg_ofs_base_msb = AFE_DL1_BASE_MSB,
.reg_ofs_cur_msb = AFE_DL1_CUR_MSB,
.reg_ofs_end_msb = AFE_DL1_END_MSB,
.fs_reg = AFE_DL1_CON0,
.fs_shift = DL1_MODE_SFT,
.fs_maskbit = DL1_MODE_MASK,
.mono_reg = AFE_DL1_CON0,
.mono_shift = DL1_MONO_SFT,
.enable_reg = AFE_DAC_CON0,
.enable_shift = DL1_ON_SFT,
.hd_reg = AFE_DL1_CON0,
.hd_shift = DL1_HD_MODE_SFT,
.hd_align_reg = AFE_DL1_CON0,
.hd_align_mshift = DL1_HALIGN_SFT,
.pbuf_reg = AFE_DL1_CON0,
.pbuf_shift = DL1_PBUF_SIZE_SFT,
.minlen_reg = AFE_DL1_CON0,
.minlen_shift = DL1_MINLEN_SFT,
},
[MT8192_MEMIF_DL12] = {
.name = "DL12",
.id = MT8192_MEMIF_DL12,
.reg_ofs_base = AFE_DL12_BASE,
.reg_ofs_cur = AFE_DL12_CUR,
.reg_ofs_end = AFE_DL12_END,
.reg_ofs_base_msb = AFE_DL12_BASE_MSB,
.reg_ofs_cur_msb = AFE_DL12_CUR_MSB,
.reg_ofs_end_msb = AFE_DL12_END_MSB,
.fs_reg = AFE_DL12_CON0,
.fs_shift = DL12_MODE_SFT,
.fs_maskbit = DL12_MODE_MASK,
.mono_reg = AFE_DL12_CON0,
.mono_shift = DL12_MONO_SFT,
.enable_reg = AFE_DAC_CON0,
.enable_shift = DL12_ON_SFT,
.hd_reg = AFE_DL12_CON0,
.hd_shift = DL12_HD_MODE_SFT,
.hd_align_reg = AFE_DL12_CON0,
.hd_align_mshift = DL12_HALIGN_SFT,
.pbuf_reg = AFE_DL12_CON0,
.pbuf_shift = DL12_PBUF_SIZE_SFT,
.minlen_reg = AFE_DL12_CON0,
.minlen_shift = DL12_MINLEN_SFT,
},
[MT8192_MEMIF_DL2] = {
.name = "DL2",
.id = MT8192_MEMIF_DL2,
.reg_ofs_base = AFE_DL2_BASE,
.reg_ofs_cur = AFE_DL2_CUR,
.reg_ofs_end = AFE_DL2_END,
.reg_ofs_base_msb = AFE_DL2_BASE_MSB,
.reg_ofs_cur_msb = AFE_DL2_CUR_MSB,
.reg_ofs_end_msb = AFE_DL2_END_MSB,
.fs_reg = AFE_DL2_CON0,
.fs_shift = DL2_MODE_SFT,
.fs_maskbit = DL2_MODE_MASK,
.mono_reg = AFE_DL2_CON0,
.mono_shift = DL2_MONO_SFT,
.enable_reg = AFE_DAC_CON0,
.enable_shift = DL2_ON_SFT,
.hd_reg = AFE_DL2_CON0,
.hd_shift = DL2_HD_MODE_SFT,
.hd_align_reg = AFE_DL2_CON0,
.hd_align_mshift = DL2_HALIGN_SFT,
.pbuf_reg = AFE_DL2_CON0,
.pbuf_shift = DL2_PBUF_SIZE_SFT,
.minlen_reg = AFE_DL2_CON0,
.minlen_shift = DL2_MINLEN_SFT,
},
[MT8192_MEMIF_DL3] = {
.name = "DL3",
.id = MT8192_MEMIF_DL3,
.reg_ofs_base = AFE_DL3_BASE,
.reg_ofs_cur = AFE_DL3_CUR,
.reg_ofs_end = AFE_DL3_END,
.reg_ofs_base_msb = AFE_DL3_BASE_MSB,
.reg_ofs_cur_msb = AFE_DL3_CUR_MSB,
.reg_ofs_end_msb = AFE_DL3_END_MSB,
.fs_reg = AFE_DL3_CON0,
.fs_shift = DL3_MODE_SFT,
.fs_maskbit = DL3_MODE_MASK,
.mono_reg = AFE_DL3_CON0,
.mono_shift = DL3_MONO_SFT,
.enable_reg = AFE_DAC_CON0,
.enable_shift = DL3_ON_SFT,
.hd_reg = AFE_DL3_CON0,
.hd_shift = DL3_HD_MODE_SFT,
.hd_align_reg = AFE_DL3_CON0,
.hd_align_mshift = DL3_HALIGN_SFT,
.pbuf_reg = AFE_DL3_CON0,
.pbuf_shift = DL3_PBUF_SIZE_SFT,
.minlen_reg = AFE_DL3_CON0,
.minlen_shift = DL3_MINLEN_SFT,
},
[MT8192_MEMIF_DL4] = {
.name = "DL4",
.id = MT8192_MEMIF_DL4,
.reg_ofs_base = AFE_DL4_BASE,
.reg_ofs_cur = AFE_DL4_CUR,
.reg_ofs_end = AFE_DL4_END,
.reg_ofs_base_msb = AFE_DL4_BASE_MSB,
.reg_ofs_cur_msb = AFE_DL4_CUR_MSB,
.reg_ofs_end_msb = AFE_DL4_END_MSB,
.fs_reg = AFE_DL4_CON0,
.fs_shift = DL4_MODE_SFT,
.fs_maskbit = DL4_MODE_MASK,
.mono_reg = AFE_DL4_CON0,
.mono_shift = DL4_MONO_SFT,
.enable_reg = AFE_DAC_CON0,
.enable_shift = DL4_ON_SFT,
.hd_reg = AFE_DL4_CON0,
.hd_shift = DL4_HD_MODE_SFT,
.hd_align_reg = AFE_DL4_CON0,
.hd_align_mshift = DL4_HALIGN_SFT,
.pbuf_reg = AFE_DL4_CON0,
.pbuf_shift = DL4_PBUF_SIZE_SFT,
.minlen_reg = AFE_DL4_CON0,
.minlen_shift = DL4_MINLEN_SFT,
},
[MT8192_MEMIF_DL5] = {
.name = "DL5",
.id = MT8192_MEMIF_DL5,
.reg_ofs_base = AFE_DL5_BASE,
.reg_ofs_cur = AFE_DL5_CUR,
.reg_ofs_end = AFE_DL5_END,
.reg_ofs_base_msb = AFE_DL5_BASE_MSB,
.reg_ofs_cur_msb = AFE_DL5_CUR_MSB,
.reg_ofs_end_msb = AFE_DL5_END_MSB,
.fs_reg = AFE_DL5_CON0,
.fs_shift = DL5_MODE_SFT,
.fs_maskbit = DL5_MODE_MASK,
.mono_reg = AFE_DL5_CON0,
.mono_shift = DL5_MONO_SFT,
.enable_reg = AFE_DAC_CON0,
.enable_shift = DL5_ON_SFT,
.hd_reg = AFE_DL5_CON0,
.hd_shift = DL5_HD_MODE_SFT,
.hd_align_reg = AFE_DL5_CON0,
.hd_align_mshift = DL5_HALIGN_SFT,
.pbuf_reg = AFE_DL5_CON0,
.pbuf_shift = DL5_PBUF_SIZE_SFT,
.minlen_reg = AFE_DL5_CON0,
.minlen_shift = DL5_MINLEN_SFT,
},
[MT8192_MEMIF_DL6] = {
.name = "DL6",
.id = MT8192_MEMIF_DL6,
.reg_ofs_base = AFE_DL6_BASE,
.reg_ofs_cur = AFE_DL6_CUR,
.reg_ofs_end = AFE_DL6_END,
.reg_ofs_base_msb = AFE_DL6_BASE_MSB,
.reg_ofs_cur_msb = AFE_DL6_CUR_MSB,
.reg_ofs_end_msb = AFE_DL6_END_MSB,
.fs_reg = AFE_DL6_CON0,
.fs_shift = DL6_MODE_SFT,
.fs_maskbit = DL6_MODE_MASK,
.mono_reg = AFE_DL6_CON0,
.mono_shift = DL6_MONO_SFT,
.enable_reg = AFE_DAC_CON0,
.enable_shift = DL6_ON_SFT,
.hd_reg = AFE_DL6_CON0,
.hd_shift = DL6_HD_MODE_SFT,
.hd_align_reg = AFE_DL6_CON0,
.hd_align_mshift = DL6_HALIGN_SFT,
.pbuf_reg = AFE_DL6_CON0,
.pbuf_shift = DL6_PBUF_SIZE_SFT,
.minlen_reg = AFE_DL6_CON0,
.minlen_shift = DL6_MINLEN_SFT,
},
[MT8192_MEMIF_DL7] = {
.name = "DL7",
.id = MT8192_MEMIF_DL7,
.reg_ofs_base = AFE_DL7_BASE,
.reg_ofs_cur = AFE_DL7_CUR,
.reg_ofs_end = AFE_DL7_END,
.reg_ofs_base_msb = AFE_DL7_BASE_MSB,
.reg_ofs_cur_msb = AFE_DL7_CUR_MSB,
.reg_ofs_end_msb = AFE_DL7_END_MSB,
.fs_reg = AFE_DL7_CON0,
.fs_shift = DL7_MODE_SFT,
.fs_maskbit = DL7_MODE_MASK,
.mono_reg = AFE_DL7_CON0,
.mono_shift = DL7_MONO_SFT,
.enable_reg = AFE_DAC_CON0,
.enable_shift = DL7_ON_SFT,
.hd_reg = AFE_DL7_CON0,
.hd_shift = DL7_HD_MODE_SFT,
.hd_align_reg = AFE_DL7_CON0,
.hd_align_mshift = DL7_HALIGN_SFT,
.pbuf_reg = AFE_DL7_CON0,
.pbuf_shift = DL7_PBUF_SIZE_SFT,
.minlen_reg = AFE_DL7_CON0,
.minlen_shift = DL7_MINLEN_SFT,
},
[MT8192_MEMIF_DL8] = {
.name = "DL8",
.id = MT8192_MEMIF_DL8,
.reg_ofs_base = AFE_DL8_BASE,
.reg_ofs_cur = AFE_DL8_CUR,
.reg_ofs_end = AFE_DL8_END,
.reg_ofs_base_msb = AFE_DL8_BASE_MSB,
.reg_ofs_cur_msb = AFE_DL8_CUR_MSB,
.reg_ofs_end_msb = AFE_DL8_END_MSB,
.fs_reg = AFE_DL8_CON0,
.fs_shift = DL8_MODE_SFT,
.fs_maskbit = DL8_MODE_MASK,
.mono_reg = AFE_DL8_CON0,
.mono_shift = DL8_MONO_SFT,
.enable_reg = AFE_DAC_CON0,
.enable_shift = DL8_ON_SFT,
.hd_reg = AFE_DL8_CON0,
.hd_shift = DL8_HD_MODE_SFT,
.hd_align_reg = AFE_DL8_CON0,
.hd_align_mshift = DL8_HALIGN_SFT,
.pbuf_reg = AFE_DL8_CON0,
.pbuf_shift = DL8_PBUF_SIZE_SFT,
.minlen_reg = AFE_DL8_CON0,
.minlen_shift = DL8_MINLEN_SFT,
},
[MT8192_MEMIF_DL9] = {
.name = "DL9",
.id = MT8192_MEMIF_DL9,
.reg_ofs_base = AFE_DL9_BASE,
.reg_ofs_cur = AFE_DL9_CUR,
.reg_ofs_end = AFE_DL9_END,
.reg_ofs_base_msb = AFE_DL9_BASE_MSB,
.reg_ofs_cur_msb = AFE_DL9_CUR_MSB,
.reg_ofs_end_msb = AFE_DL9_END_MSB,
.fs_reg = AFE_DL9_CON0,
.fs_shift = DL9_MODE_SFT,
.fs_maskbit = DL9_MODE_MASK,
.mono_reg = AFE_DL9_CON0,
.mono_shift = DL9_MONO_SFT,
.enable_reg = AFE_DAC_CON0,
.enable_shift = DL9_ON_SFT,
.hd_reg = AFE_DL9_CON0,
.hd_shift = DL9_HD_MODE_SFT,
.hd_align_reg = AFE_DL9_CON0,
.hd_align_mshift = DL9_HALIGN_SFT,
.pbuf_reg = AFE_DL9_CON0,
.pbuf_shift = DL9_PBUF_SIZE_SFT,
.minlen_reg = AFE_DL9_CON0,
.minlen_shift = DL9_MINLEN_SFT,
},
[MT8192_MEMIF_DAI] = {
.name = "DAI",
.id = MT8192_MEMIF_DAI,
.reg_ofs_base = AFE_DAI_BASE,
.reg_ofs_cur = AFE_DAI_CUR,
.reg_ofs_end = AFE_DAI_END,
.reg_ofs_base_msb = AFE_DAI_BASE_MSB,
.reg_ofs_cur_msb = AFE_DAI_CUR_MSB,
.reg_ofs_end_msb = AFE_DAI_END_MSB,
.fs_reg = AFE_DAI_CON0,
.fs_shift = DAI_MODE_SFT,
.fs_maskbit = DAI_MODE_MASK,
.mono_reg = AFE_DAI_CON0,
.mono_shift = DAI_DUPLICATE_WR_SFT,
.mono_invert = 1,
.enable_reg = AFE_DAC_CON0,
.enable_shift = DAI_ON_SFT,
.hd_reg = AFE_DAI_CON0,
.hd_shift = DAI_HD_MODE_SFT,
.hd_align_reg = AFE_DAI_CON0,
.hd_align_mshift = DAI_HALIGN_SFT,
},
[MT8192_MEMIF_MOD_DAI] = {
.name = "MOD_DAI",
.id = MT8192_MEMIF_MOD_DAI,
.reg_ofs_base = AFE_MOD_DAI_BASE,
.reg_ofs_cur = AFE_MOD_DAI_CUR,
.reg_ofs_end = AFE_MOD_DAI_END,
.reg_ofs_base_msb = AFE_MOD_DAI_BASE_MSB,
.reg_ofs_cur_msb = AFE_MOD_DAI_CUR_MSB,
.reg_ofs_end_msb = AFE_MOD_DAI_END_MSB,
.fs_reg = AFE_MOD_DAI_CON0,
.fs_shift = MOD_DAI_MODE_SFT,
.fs_maskbit = MOD_DAI_MODE_MASK,
.mono_reg = AFE_MOD_DAI_CON0,
.mono_shift = MOD_DAI_DUPLICATE_WR_SFT,
.mono_invert = 1,
.enable_reg = AFE_DAC_CON0,
.enable_shift = MOD_DAI_ON_SFT,
.hd_reg = AFE_MOD_DAI_CON0,
.hd_shift = MOD_DAI_HD_MODE_SFT,
.hd_align_reg = AFE_MOD_DAI_CON0,
.hd_align_mshift = MOD_DAI_HALIGN_SFT,
},
[MT8192_MEMIF_DAI2] = {
.name = "DAI2",
.id = MT8192_MEMIF_DAI2,
.reg_ofs_base = AFE_DAI2_BASE,
.reg_ofs_cur = AFE_DAI2_CUR,
.reg_ofs_end = AFE_DAI2_END,
.reg_ofs_base_msb = AFE_DAI2_BASE_MSB,
.reg_ofs_cur_msb = AFE_DAI2_CUR_MSB,
.reg_ofs_end_msb = AFE_DAI2_END_MSB,
.fs_reg = AFE_DAI2_CON0,
.fs_shift = DAI2_MODE_SFT,
.fs_maskbit = DAI2_MODE_MASK,
.mono_reg = AFE_DAI2_CON0,
.mono_shift = DAI2_DUPLICATE_WR_SFT,
.mono_invert = 1,
.enable_reg = AFE_DAC_CON0,
.enable_shift = DAI2_ON_SFT,
.hd_reg = AFE_DAI2_CON0,
.hd_shift = DAI2_HD_MODE_SFT,
.hd_align_reg = AFE_DAI2_CON0,
.hd_align_mshift = DAI2_HALIGN_SFT,
},
[MT8192_MEMIF_VUL12] = {
.name = "VUL12",
.id = MT8192_MEMIF_VUL12,
.reg_ofs_base = AFE_VUL12_BASE,
.reg_ofs_cur = AFE_VUL12_CUR,
.reg_ofs_end = AFE_VUL12_END,
.reg_ofs_base_msb = AFE_VUL12_BASE_MSB,
.reg_ofs_cur_msb = AFE_VUL12_CUR_MSB,
.reg_ofs_end_msb = AFE_VUL12_END_MSB,
.fs_reg = AFE_VUL12_CON0,
.fs_shift = VUL12_MODE_SFT,
.fs_maskbit = VUL12_MODE_MASK,
.mono_reg = AFE_VUL12_CON0,
.mono_shift = VUL12_MONO_SFT,
.quad_ch_reg = AFE_VUL12_CON0,
.quad_ch_shift = VUL12_4CH_EN_SFT,
.quad_ch_mask = VUL12_4CH_EN_MASK,
.enable_reg = AFE_DAC_CON0,
.enable_shift = VUL12_ON_SFT,
.hd_reg = AFE_VUL12_CON0,
.hd_shift = VUL12_HD_MODE_SFT,
.hd_align_reg = AFE_VUL12_CON0,
.hd_align_mshift = VUL12_HALIGN_SFT,
},
[MT8192_MEMIF_VUL2] = {
.name = "VUL2",
.id = MT8192_MEMIF_VUL2,
.reg_ofs_base = AFE_VUL2_BASE,
.reg_ofs_cur = AFE_VUL2_CUR,
.reg_ofs_end = AFE_VUL2_END,
.reg_ofs_base_msb = AFE_VUL2_BASE_MSB,
.reg_ofs_cur_msb = AFE_VUL2_CUR_MSB,
.reg_ofs_end_msb = AFE_VUL2_END_MSB,
.fs_reg = AFE_VUL2_CON0,
.fs_shift = VUL2_MODE_SFT,
.fs_maskbit = VUL2_MODE_MASK,
.mono_reg = AFE_VUL2_CON0,
.mono_shift = VUL2_MONO_SFT,
.enable_reg = AFE_DAC_CON0,
.enable_shift = VUL2_ON_SFT,
.hd_reg = AFE_VUL2_CON0,
.hd_shift = VUL2_HD_MODE_SFT,
.hd_align_reg = AFE_VUL2_CON0,
.hd_align_mshift = VUL2_HALIGN_SFT,
},
[MT8192_MEMIF_AWB] = {
.name = "AWB",
.id = MT8192_MEMIF_AWB,
.reg_ofs_base = AFE_AWB_BASE,
.reg_ofs_cur = AFE_AWB_CUR,
.reg_ofs_end = AFE_AWB_END,
.reg_ofs_base_msb = AFE_AWB_BASE_MSB,
.reg_ofs_cur_msb = AFE_AWB_CUR_MSB,
.reg_ofs_end_msb = AFE_AWB_END_MSB,
.fs_reg = AFE_AWB_CON0,
.fs_shift = AWB_MODE_SFT,
.fs_maskbit = AWB_MODE_MASK,
.mono_reg = AFE_AWB_CON0,
.mono_shift = AWB_MONO_SFT,
.enable_reg = AFE_DAC_CON0,
.enable_shift = AWB_ON_SFT,
.hd_reg = AFE_AWB_CON0,
.hd_shift = AWB_HD_MODE_SFT,
.hd_align_reg = AFE_AWB_CON0,
.hd_align_mshift = AWB_HALIGN_SFT,
},
[MT8192_MEMIF_AWB2] = {
.name = "AWB2",
.id = MT8192_MEMIF_AWB2,
.reg_ofs_base = AFE_AWB2_BASE,
.reg_ofs_cur = AFE_AWB2_CUR,
.reg_ofs_end = AFE_AWB2_END,
.reg_ofs_base_msb = AFE_AWB2_BASE_MSB,
.reg_ofs_cur_msb = AFE_AWB2_CUR_MSB,
.reg_ofs_end_msb = AFE_AWB2_END_MSB,
.fs_reg = AFE_AWB2_CON0,
.fs_shift = AWB2_MODE_SFT,
.fs_maskbit = AWB2_MODE_MASK,
.mono_reg = AFE_AWB2_CON0,
.mono_shift = AWB2_MONO_SFT,
.enable_reg = AFE_DAC_CON0,
.enable_shift = AWB2_ON_SFT,
.hd_reg = AFE_AWB2_CON0,
.hd_shift = AWB2_HD_MODE_SFT,
.hd_align_reg = AFE_AWB2_CON0,
.hd_align_mshift = AWB2_HALIGN_SFT,
},
[MT8192_MEMIF_VUL3] = {
.name = "VUL3",
.id = MT8192_MEMIF_VUL3,
.reg_ofs_base = AFE_VUL3_BASE,
.reg_ofs_cur = AFE_VUL3_CUR,
.reg_ofs_end = AFE_VUL3_END,
.reg_ofs_base_msb = AFE_VUL3_BASE_MSB,
.reg_ofs_cur_msb = AFE_VUL3_CUR_MSB,
.reg_ofs_end_msb = AFE_VUL3_END_MSB,
.fs_reg = AFE_VUL3_CON0,
.fs_shift = VUL3_MODE_SFT,
.fs_maskbit = VUL3_MODE_MASK,
.mono_reg = AFE_VUL3_CON0,
.mono_shift = VUL3_MONO_SFT,
.enable_reg = AFE_DAC_CON0,
.enable_shift = VUL3_ON_SFT,
.hd_reg = AFE_VUL3_CON0,
.hd_shift = VUL3_HD_MODE_SFT,
.hd_align_reg = AFE_VUL3_CON0,
.hd_align_mshift = VUL3_HALIGN_SFT,
},
[MT8192_MEMIF_VUL4] = {
.name = "VUL4",
.id = MT8192_MEMIF_VUL4,
.reg_ofs_base = AFE_VUL4_BASE,
.reg_ofs_cur = AFE_VUL4_CUR,
.reg_ofs_end = AFE_VUL4_END,
.reg_ofs_base_msb = AFE_VUL4_BASE_MSB,
.reg_ofs_cur_msb = AFE_VUL4_CUR_MSB,
.reg_ofs_end_msb = AFE_VUL4_END_MSB,
.fs_reg = AFE_VUL4_CON0,
.fs_shift = VUL4_MODE_SFT,
.fs_maskbit = VUL4_MODE_MASK,
.mono_reg = AFE_VUL4_CON0,
.mono_shift = VUL4_MONO_SFT,
.enable_reg = AFE_DAC_CON0,
.enable_shift = VUL4_ON_SFT,
.hd_reg = AFE_VUL4_CON0,
.hd_shift = VUL4_HD_MODE_SFT,
.hd_align_reg = AFE_VUL4_CON0,
.hd_align_mshift = VUL4_HALIGN_SFT,
},
[MT8192_MEMIF_VUL5] = {
.name = "VUL5",
.id = MT8192_MEMIF_VUL5,
.reg_ofs_base = AFE_VUL5_BASE,
.reg_ofs_cur = AFE_VUL5_CUR,
.reg_ofs_end = AFE_VUL5_END,
.reg_ofs_base_msb = AFE_VUL5_BASE_MSB,
.reg_ofs_cur_msb = AFE_VUL5_CUR_MSB,
.reg_ofs_end_msb = AFE_VUL5_END_MSB,
.fs_reg = AFE_VUL5_CON0,
.fs_shift = VUL5_MODE_SFT,
.fs_maskbit = VUL5_MODE_MASK,
.mono_reg = AFE_VUL5_CON0,
.mono_shift = VUL5_MONO_SFT,
.enable_reg = AFE_DAC_CON0,
.enable_shift = VUL5_ON_SFT,
.hd_reg = AFE_VUL5_CON0,
.hd_shift = VUL5_HD_MODE_SFT,
.hd_align_reg = AFE_VUL5_CON0,
.hd_align_mshift = VUL5_HALIGN_SFT,
},
[MT8192_MEMIF_VUL6] = {
.name = "VUL6",
.id = MT8192_MEMIF_VUL6,
.reg_ofs_base = AFE_VUL6_BASE,
.reg_ofs_cur = AFE_VUL6_CUR,
.reg_ofs_end = AFE_VUL6_END,
.reg_ofs_base_msb = AFE_VUL6_BASE_MSB,
.reg_ofs_cur_msb = AFE_VUL6_CUR_MSB,
.reg_ofs_end_msb = AFE_VUL6_END_MSB,
.fs_reg = AFE_VUL6_CON0,
.fs_shift = VUL6_MODE_SFT,
.fs_maskbit = VUL6_MODE_MASK,
.mono_reg = AFE_VUL6_CON0,
.mono_shift = VUL6_MONO_SFT,
.enable_reg = AFE_DAC_CON0,
.enable_shift = VUL6_ON_SFT,
.hd_reg = AFE_VUL6_CON0,
.hd_shift = VUL6_HD_MODE_SFT,
.hd_align_reg = AFE_VUL6_CON0,
.hd_align_mshift = VUL6_HALIGN_SFT,
},
[MT8192_MEMIF_HDMI] = {
.name = "HDMI",
.id = MT8192_MEMIF_HDMI,
.reg_ofs_base = AFE_HDMI_OUT_BASE,
.reg_ofs_cur = AFE_HDMI_OUT_CUR,
.reg_ofs_end = AFE_HDMI_OUT_END,
.reg_ofs_base_msb = AFE_HDMI_OUT_BASE_MSB,
.reg_ofs_cur_msb = AFE_HDMI_OUT_CUR_MSB,
.reg_ofs_end_msb = AFE_HDMI_OUT_END_MSB,
.fs_reg = -1,
.fs_shift = -1,
.fs_maskbit = -1,
.mono_reg = -1,
.mono_shift = -1,
.enable_reg = AFE_DAC_CON0,
.enable_shift = HDMI_OUT_ON_SFT,
.hd_reg = AFE_HDMI_OUT_CON0,
.hd_shift = HDMI_OUT_HD_MODE_SFT,
.hd_align_reg = AFE_HDMI_OUT_CON0,
.hd_align_mshift = HDMI_OUT_HALIGN_SFT,
.pbuf_reg = AFE_HDMI_OUT_CON0,
.minlen_reg = AFE_HDMI_OUT_CON0,
.minlen_shift = HDMI_OUT_MINLEN_SFT,
},
};
static const struct mtk_base_irq_data irq_data[MT8192_IRQ_NUM] = {
[MT8192_IRQ_0] = {
.id = MT8192_IRQ_0,
.irq_cnt_reg = AFE_IRQ_MCU_CNT0,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON1,
.irq_fs_shift = IRQ0_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ0_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ0_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ0_MCU_CLR_SFT,
},
[MT8192_IRQ_1] = {
.id = MT8192_IRQ_1,
.irq_cnt_reg = AFE_IRQ_MCU_CNT1,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON1,
.irq_fs_shift = IRQ1_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ1_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ1_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ1_MCU_CLR_SFT,
},
[MT8192_IRQ_2] = {
.id = MT8192_IRQ_2,
.irq_cnt_reg = AFE_IRQ_MCU_CNT2,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON1,
.irq_fs_shift = IRQ2_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ2_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ2_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ2_MCU_CLR_SFT,
},
[MT8192_IRQ_3] = {
.id = MT8192_IRQ_3,
.irq_cnt_reg = AFE_IRQ_MCU_CNT3,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON1,
.irq_fs_shift = IRQ3_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ3_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ3_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ3_MCU_CLR_SFT,
},
[MT8192_IRQ_4] = {
.id = MT8192_IRQ_4,
.irq_cnt_reg = AFE_IRQ_MCU_CNT4,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON1,
.irq_fs_shift = IRQ4_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ4_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ4_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ4_MCU_CLR_SFT,
},
[MT8192_IRQ_5] = {
.id = MT8192_IRQ_5,
.irq_cnt_reg = AFE_IRQ_MCU_CNT5,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON1,
.irq_fs_shift = IRQ5_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ5_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ5_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ5_MCU_CLR_SFT,
},
[MT8192_IRQ_6] = {
.id = MT8192_IRQ_6,
.irq_cnt_reg = AFE_IRQ_MCU_CNT6,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON1,
.irq_fs_shift = IRQ6_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ6_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ6_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ6_MCU_CLR_SFT,
},
[MT8192_IRQ_7] = {
.id = MT8192_IRQ_7,
.irq_cnt_reg = AFE_IRQ_MCU_CNT7,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON1,
.irq_fs_shift = IRQ7_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ7_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ7_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ7_MCU_CLR_SFT,
},
[MT8192_IRQ_8] = {
.id = MT8192_IRQ_8,
.irq_cnt_reg = AFE_IRQ_MCU_CNT8,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON2,
.irq_fs_shift = IRQ8_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ8_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ8_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ8_MCU_CLR_SFT,
},
[MT8192_IRQ_9] = {
.id = MT8192_IRQ_9,
.irq_cnt_reg = AFE_IRQ_MCU_CNT9,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON2,
.irq_fs_shift = IRQ9_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ9_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ9_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ9_MCU_CLR_SFT,
},
[MT8192_IRQ_10] = {
.id = MT8192_IRQ_10,
.irq_cnt_reg = AFE_IRQ_MCU_CNT10,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON2,
.irq_fs_shift = IRQ10_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ10_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ10_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ10_MCU_CLR_SFT,
},
[MT8192_IRQ_11] = {
.id = MT8192_IRQ_11,
.irq_cnt_reg = AFE_IRQ_MCU_CNT11,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON2,
.irq_fs_shift = IRQ11_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ11_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ11_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ11_MCU_CLR_SFT,
},
[MT8192_IRQ_12] = {
.id = MT8192_IRQ_12,
.irq_cnt_reg = AFE_IRQ_MCU_CNT12,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON2,
.irq_fs_shift = IRQ12_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ12_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ12_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ12_MCU_CLR_SFT,
},
[MT8192_IRQ_13] = {
.id = MT8192_IRQ_13,
.irq_cnt_reg = AFE_IRQ_MCU_CNT13,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON2,
.irq_fs_shift = IRQ13_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ13_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ13_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ13_MCU_CLR_SFT,
},
[MT8192_IRQ_14] = {
.id = MT8192_IRQ_14,
.irq_cnt_reg = AFE_IRQ_MCU_CNT14,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON2,
.irq_fs_shift = IRQ14_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ14_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ14_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ14_MCU_CLR_SFT,
},
[MT8192_IRQ_15] = {
.id = MT8192_IRQ_15,
.irq_cnt_reg = AFE_IRQ_MCU_CNT15,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON2,
.irq_fs_shift = IRQ15_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ15_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ15_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ15_MCU_CLR_SFT,
},
[MT8192_IRQ_16] = {
.id = MT8192_IRQ_16,
.irq_cnt_reg = AFE_IRQ_MCU_CNT16,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON3,
.irq_fs_shift = IRQ16_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ16_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ16_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ16_MCU_CLR_SFT,
},
[MT8192_IRQ_17] = {
.id = MT8192_IRQ_17,
.irq_cnt_reg = AFE_IRQ_MCU_CNT17,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON3,
.irq_fs_shift = IRQ17_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ17_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ17_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ17_MCU_CLR_SFT,
},
[MT8192_IRQ_18] = {
.id = MT8192_IRQ_18,
.irq_cnt_reg = AFE_IRQ_MCU_CNT18,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON3,
.irq_fs_shift = IRQ18_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ18_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ18_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ18_MCU_CLR_SFT,
},
[MT8192_IRQ_19] = {
.id = MT8192_IRQ_19,
.irq_cnt_reg = AFE_IRQ_MCU_CNT19,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON3,
.irq_fs_shift = IRQ19_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ19_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ19_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ19_MCU_CLR_SFT,
},
[MT8192_IRQ_20] = {
.id = MT8192_IRQ_20,
.irq_cnt_reg = AFE_IRQ_MCU_CNT20,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON3,
.irq_fs_shift = IRQ20_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ20_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ20_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ20_MCU_CLR_SFT,
},
[MT8192_IRQ_21] = {
.id = MT8192_IRQ_21,
.irq_cnt_reg = AFE_IRQ_MCU_CNT21,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON3,
.irq_fs_shift = IRQ21_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ21_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ21_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ21_MCU_CLR_SFT,
},
[MT8192_IRQ_22] = {
.id = MT8192_IRQ_22,
.irq_cnt_reg = AFE_IRQ_MCU_CNT22,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON3,
.irq_fs_shift = IRQ22_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ22_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ22_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ22_MCU_CLR_SFT,
},
[MT8192_IRQ_23] = {
.id = MT8192_IRQ_23,
.irq_cnt_reg = AFE_IRQ_MCU_CNT23,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON3,
.irq_fs_shift = IRQ23_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ23_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ23_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ23_MCU_CLR_SFT,
},
[MT8192_IRQ_24] = {
.id = MT8192_IRQ_24,
.irq_cnt_reg = AFE_IRQ_MCU_CNT24,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON4,
.irq_fs_shift = IRQ24_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ24_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ24_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ24_MCU_CLR_SFT,
},
[MT8192_IRQ_25] = {
.id = MT8192_IRQ_25,
.irq_cnt_reg = AFE_IRQ_MCU_CNT25,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON4,
.irq_fs_shift = IRQ25_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ25_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ25_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ25_MCU_CLR_SFT,
},
[MT8192_IRQ_26] = {
.id = MT8192_IRQ_26,
.irq_cnt_reg = AFE_IRQ_MCU_CNT26,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON4,
.irq_fs_shift = IRQ26_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ26_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ26_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ26_MCU_CLR_SFT,
},
[MT8192_IRQ_31] = {
.id = MT8192_IRQ_31,
.irq_cnt_reg = AFE_IRQ_MCU_CNT31,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = -1,
.irq_fs_shift = -1,
.irq_fs_maskbit = -1,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ31_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ31_MCU_CLR_SFT,
},
};
static const int memif_irq_usage[MT8192_MEMIF_NUM] = {
[MT8192_MEMIF_DL1] = MT8192_IRQ_0,
[MT8192_MEMIF_DL2] = MT8192_IRQ_1,
[MT8192_MEMIF_DL3] = MT8192_IRQ_2,
[MT8192_MEMIF_DL4] = MT8192_IRQ_3,
[MT8192_MEMIF_DL5] = MT8192_IRQ_4,
[MT8192_MEMIF_DL6] = MT8192_IRQ_5,
[MT8192_MEMIF_DL7] = MT8192_IRQ_6,
[MT8192_MEMIF_DL8] = MT8192_IRQ_7,
[MT8192_MEMIF_DL9] = MT8192_IRQ_8,
[MT8192_MEMIF_DL12] = MT8192_IRQ_9,
[MT8192_MEMIF_DAI] = MT8192_IRQ_10,
[MT8192_MEMIF_MOD_DAI] = MT8192_IRQ_11,
[MT8192_MEMIF_DAI2] = MT8192_IRQ_12,
[MT8192_MEMIF_VUL12] = MT8192_IRQ_13,
[MT8192_MEMIF_VUL2] = MT8192_IRQ_14,
[MT8192_MEMIF_AWB] = MT8192_IRQ_15,
[MT8192_MEMIF_AWB2] = MT8192_IRQ_16,
[MT8192_MEMIF_VUL3] = MT8192_IRQ_17,
[MT8192_MEMIF_VUL4] = MT8192_IRQ_18,
[MT8192_MEMIF_VUL5] = MT8192_IRQ_19,
[MT8192_MEMIF_VUL6] = MT8192_IRQ_20,
[MT8192_MEMIF_HDMI] = MT8192_IRQ_31,
};
static bool mt8192_is_volatile_reg(struct device *dev, unsigned int reg)
{
/* these auto-gen reg has read-only bit, so put it as volatile */
/* volatile reg cannot be cached, so cannot be set when power off */
switch (reg) {
case AUDIO_TOP_CON0: /* reg bit controlled by CCF */
case AUDIO_TOP_CON1: /* reg bit controlled by CCF */
case AUDIO_TOP_CON2:
case AUDIO_TOP_CON3:
case AFE_DL1_CUR_MSB:
case AFE_DL1_CUR:
case AFE_DL1_END:
case AFE_DL2_CUR_MSB:
case AFE_DL2_CUR:
case AFE_DL2_END:
case AFE_DL3_CUR_MSB:
case AFE_DL3_CUR:
case AFE_DL3_END:
case AFE_DL4_CUR_MSB:
case AFE_DL4_CUR:
case AFE_DL4_END:
case AFE_DL12_CUR_MSB:
case AFE_DL12_CUR:
case AFE_DL12_END:
case AFE_ADDA_SRC_DEBUG_MON0:
case AFE_ADDA_SRC_DEBUG_MON1:
case AFE_ADDA_UL_SRC_MON0:
case AFE_ADDA_UL_SRC_MON1:
case AFE_SECURE_CON0:
case AFE_SRAM_BOUND:
case AFE_SECURE_CON1:
case AFE_VUL_CUR_MSB:
case AFE_VUL_CUR:
case AFE_VUL_END:
case AFE_ADDA_3RD_DAC_DL_SDM_FIFO_MON:
case AFE_ADDA_3RD_DAC_DL_SRC_LCH_MON:
case AFE_ADDA_3RD_DAC_DL_SRC_RCH_MON:
case AFE_ADDA_3RD_DAC_DL_SDM_OUT_MON:
case AFE_SIDETONE_MON:
case AFE_SIDETONE_CON0:
case AFE_SIDETONE_COEFF:
case AFE_VUL2_CUR_MSB:
case AFE_VUL2_CUR:
case AFE_VUL2_END:
case AFE_VUL3_CUR_MSB:
case AFE_VUL3_CUR:
case AFE_VUL3_END:
case AFE_I2S_MON:
case AFE_DAC_MON:
case AFE_IRQ0_MCU_CNT_MON:
case AFE_IRQ6_MCU_CNT_MON:
case AFE_VUL4_CUR_MSB:
case AFE_VUL4_CUR:
case AFE_VUL4_END:
case AFE_VUL12_CUR_MSB:
case AFE_VUL12_CUR:
case AFE_VUL12_END:
case AFE_IRQ3_MCU_CNT_MON:
case AFE_IRQ4_MCU_CNT_MON:
case AFE_IRQ_MCU_STATUS:
case AFE_IRQ_MCU_CLR:
case AFE_IRQ_MCU_MON2:
case AFE_IRQ1_MCU_CNT_MON:
case AFE_IRQ2_MCU_CNT_MON:
case AFE_IRQ5_MCU_CNT_MON:
case AFE_IRQ7_MCU_CNT_MON:
case AFE_IRQ_MCU_MISS_CLR:
case AFE_GAIN1_CUR:
case AFE_GAIN2_CUR:
case AFE_SRAM_DELSEL_CON1:
case PCM_INTF_CON2:
case FPGA_CFG0:
case FPGA_CFG1:
case FPGA_CFG2:
case FPGA_CFG3:
case AUDIO_TOP_DBG_MON0:
case AUDIO_TOP_DBG_MON1:
case AFE_IRQ8_MCU_CNT_MON:
case AFE_IRQ11_MCU_CNT_MON:
case AFE_IRQ12_MCU_CNT_MON:
case AFE_IRQ9_MCU_CNT_MON:
case AFE_IRQ10_MCU_CNT_MON:
case AFE_IRQ13_MCU_CNT_MON:
case AFE_IRQ14_MCU_CNT_MON:
case AFE_IRQ15_MCU_CNT_MON:
case AFE_IRQ16_MCU_CNT_MON:
case AFE_IRQ17_MCU_CNT_MON:
case AFE_IRQ18_MCU_CNT_MON:
case AFE_IRQ19_MCU_CNT_MON:
case AFE_IRQ20_MCU_CNT_MON:
case AFE_IRQ21_MCU_CNT_MON:
case AFE_IRQ22_MCU_CNT_MON:
case AFE_IRQ23_MCU_CNT_MON:
case AFE_IRQ24_MCU_CNT_MON:
case AFE_IRQ25_MCU_CNT_MON:
case AFE_IRQ26_MCU_CNT_MON:
case AFE_IRQ31_MCU_CNT_MON:
case AFE_CBIP_MON0:
case AFE_CBIP_SLV_MUX_MON0:
case AFE_CBIP_SLV_DECODER_MON0:
case AFE_ADDA6_MTKAIF_MON0:
case AFE_ADDA6_MTKAIF_MON1:
case AFE_AWB_CUR_MSB:
case AFE_AWB_CUR:
case AFE_AWB_END:
case AFE_AWB2_CUR_MSB:
case AFE_AWB2_CUR:
case AFE_AWB2_END:
case AFE_DAI_CUR_MSB:
case AFE_DAI_CUR:
case AFE_DAI_END:
case AFE_DAI2_CUR_MSB:
case AFE_DAI2_CUR:
case AFE_DAI2_END:
case AFE_ADDA6_SRC_DEBUG_MON0:
case AFE_ADD6A_UL_SRC_MON0:
case AFE_ADDA6_UL_SRC_MON1:
case AFE_MOD_DAI_CUR_MSB:
case AFE_MOD_DAI_CUR:
case AFE_MOD_DAI_END:
case AFE_HDMI_OUT_CUR_MSB:
case AFE_HDMI_OUT_CUR:
case AFE_HDMI_OUT_END:
case AFE_AWB_RCH_MON:
case AFE_AWB_LCH_MON:
case AFE_VUL_RCH_MON:
case AFE_VUL_LCH_MON:
case AFE_VUL12_RCH_MON:
case AFE_VUL12_LCH_MON:
case AFE_VUL2_RCH_MON:
case AFE_VUL2_LCH_MON:
case AFE_DAI_DATA_MON:
case AFE_MOD_DAI_DATA_MON:
case AFE_DAI2_DATA_MON:
case AFE_AWB2_RCH_MON:
case AFE_AWB2_LCH_MON:
case AFE_VUL3_RCH_MON:
case AFE_VUL3_LCH_MON:
case AFE_VUL4_RCH_MON:
case AFE_VUL4_LCH_MON:
case AFE_VUL5_RCH_MON:
case AFE_VUL5_LCH_MON:
case AFE_VUL6_RCH_MON:
case AFE_VUL6_LCH_MON:
case AFE_DL1_RCH_MON:
case AFE_DL1_LCH_MON:
case AFE_DL2_RCH_MON:
case AFE_DL2_LCH_MON:
case AFE_DL12_RCH1_MON:
case AFE_DL12_LCH1_MON:
case AFE_DL12_RCH2_MON:
case AFE_DL12_LCH2_MON:
case AFE_DL3_RCH_MON:
case AFE_DL3_LCH_MON:
case AFE_DL4_RCH_MON:
case AFE_DL4_LCH_MON:
case AFE_DL5_RCH_MON:
case AFE_DL5_LCH_MON:
case AFE_DL6_RCH_MON:
case AFE_DL6_LCH_MON:
case AFE_DL7_RCH_MON:
case AFE_DL7_LCH_MON:
case AFE_DL8_RCH_MON:
case AFE_DL8_LCH_MON:
case AFE_VUL5_CUR_MSB:
case AFE_VUL5_CUR:
case AFE_VUL5_END:
case AFE_VUL6_CUR_MSB:
case AFE_VUL6_CUR:
case AFE_VUL6_END:
case AFE_ADDA_DL_SDM_FIFO_MON:
case AFE_ADDA_DL_SRC_LCH_MON:
case AFE_ADDA_DL_SRC_RCH_MON:
case AFE_ADDA_DL_SDM_OUT_MON:
case AFE_CONNSYS_I2S_MON:
case AFE_ASRC_2CH_CON0:
case AFE_ASRC_2CH_CON2:
case AFE_ASRC_2CH_CON3:
case AFE_ASRC_2CH_CON4:
case AFE_ASRC_2CH_CON5:
case AFE_ASRC_2CH_CON7:
case AFE_ASRC_2CH_CON8:
case AFE_ASRC_2CH_CON12:
case AFE_ASRC_2CH_CON13:
case AFE_DL9_CUR_MSB:
case AFE_DL9_CUR:
case AFE_DL9_END:
case AFE_ADDA_MTKAIF_MON0:
case AFE_ADDA_MTKAIF_MON1:
case AFE_DL_NLE_R_MON0:
case AFE_DL_NLE_R_MON1:
case AFE_DL_NLE_R_MON2:
case AFE_DL_NLE_L_MON0:
case AFE_DL_NLE_L_MON1:
case AFE_DL_NLE_L_MON2:
case AFE_GENERAL1_ASRC_2CH_CON0:
case AFE_GENERAL1_ASRC_2CH_CON2:
case AFE_GENERAL1_ASRC_2CH_CON3:
case AFE_GENERAL1_ASRC_2CH_CON4:
case AFE_GENERAL1_ASRC_2CH_CON5:
case AFE_GENERAL1_ASRC_2CH_CON7:
case AFE_GENERAL1_ASRC_2CH_CON8:
case AFE_GENERAL1_ASRC_2CH_CON12:
case AFE_GENERAL1_ASRC_2CH_CON13:
case AFE_GENERAL2_ASRC_2CH_CON0:
case AFE_GENERAL2_ASRC_2CH_CON2:
case AFE_GENERAL2_ASRC_2CH_CON3:
case AFE_GENERAL2_ASRC_2CH_CON4:
case AFE_GENERAL2_ASRC_2CH_CON5:
case AFE_GENERAL2_ASRC_2CH_CON7:
case AFE_GENERAL2_ASRC_2CH_CON8:
case AFE_GENERAL2_ASRC_2CH_CON12:
case AFE_GENERAL2_ASRC_2CH_CON13:
case AFE_DL9_RCH_MON:
case AFE_DL9_LCH_MON:
case AFE_DL5_CUR_MSB:
case AFE_DL5_CUR:
case AFE_DL5_END:
case AFE_DL6_CUR_MSB:
case AFE_DL6_CUR:
case AFE_DL6_END:
case AFE_DL7_CUR_MSB:
case AFE_DL7_CUR:
case AFE_DL7_END:
case AFE_DL8_CUR_MSB:
case AFE_DL8_CUR:
case AFE_DL8_END:
case AFE_PROT_SIDEBAND_MON:
case AFE_DOMAIN_SIDEBAND0_MON:
case AFE_DOMAIN_SIDEBAND1_MON:
case AFE_DOMAIN_SIDEBAND2_MON:
case AFE_DOMAIN_SIDEBAND3_MON:
case AFE_APLL1_TUNER_CFG: /* [20:31] is monitor */
case AFE_APLL2_TUNER_CFG: /* [20:31] is monitor */
case AFE_DAC_CON0:
case AFE_IRQ_MCU_CON0:
case AFE_IRQ_MCU_EN:
return true;
default:
return false;
};
}
static const struct regmap_config mt8192_afe_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.volatile_reg = mt8192_is_volatile_reg,
.max_register = AFE_MAX_REGISTER,
.num_reg_defaults_raw = AFE_MAX_REGISTER,
.cache_type = REGCACHE_FLAT,
};
static irqreturn_t mt8192_afe_irq_handler(int irq_id, void *dev)
{
struct mtk_base_afe *afe = dev;
struct mtk_base_afe_irq *irq;
unsigned int status;
unsigned int status_mcu;
unsigned int mcu_en;
int ret;
int i;
/* get irq that is sent to MCU */
regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &mcu_en);
ret = regmap_read(afe->regmap, AFE_IRQ_MCU_STATUS, &status);
/* only care IRQ which is sent to MCU */
status_mcu = status & mcu_en & AFE_IRQ_STATUS_BITS;
if (ret || status_mcu == 0) {
dev_err(afe->dev, "%s(), irq status err, ret %d, status 0x%x, mcu_en 0x%x\n",
__func__, ret, status, mcu_en);
goto err_irq;
}
for (i = 0; i < MT8192_MEMIF_NUM; i++) {
struct mtk_base_afe_memif *memif = &afe->memif[i];
if (!memif->substream)
continue;
if (memif->irq_usage < 0)
continue;
irq = &afe->irqs[memif->irq_usage];
if (status_mcu & (1 << irq->irq_data->irq_en_shift))
snd_pcm_period_elapsed(memif->substream);
}
err_irq:
/* clear irq */
regmap_write(afe->regmap,
AFE_IRQ_MCU_CLR,
status_mcu);
return IRQ_HANDLED;
}
static int mt8192_afe_runtime_suspend(struct device *dev)
{
struct mtk_base_afe *afe = dev_get_drvdata(dev);
struct mt8192_afe_private *afe_priv = afe->platform_priv;
unsigned int value;
int ret;
if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
goto skip_regmap;
/* disable AFE */
regmap_update_bits(afe->regmap, AFE_DAC_CON0, AFE_ON_MASK_SFT, 0x0);
ret = regmap_read_poll_timeout(afe->regmap,
AFE_DAC_MON,
value,
(value & AFE_ON_RETM_MASK_SFT) == 0,
20,
1 * 1000 * 1000);
if (ret)
dev_warn(afe->dev, "%s(), ret %d\n", __func__, ret);
/* make sure all irq status are cleared */
regmap_write(afe->regmap, AFE_IRQ_MCU_CLR, 0xffffffff);
regmap_write(afe->regmap, AFE_IRQ_MCU_CLR, 0xffffffff);
/* reset sgen */
regmap_write(afe->regmap, AFE_SINEGEN_CON0, 0x0);
regmap_update_bits(afe->regmap, AFE_SINEGEN_CON2,
INNER_LOOP_BACK_MODE_MASK_SFT,
0x3f << INNER_LOOP_BACK_MODE_SFT);
/* cache only */
regcache_cache_only(afe->regmap, true);
regcache_mark_dirty(afe->regmap);
skip_regmap:
mt8192_afe_disable_clock(afe);
return 0;
}
static int mt8192_afe_runtime_resume(struct device *dev)
{
struct mtk_base_afe *afe = dev_get_drvdata(dev);
struct mt8192_afe_private *afe_priv = afe->platform_priv;
int ret;
ret = mt8192_afe_enable_clock(afe);
if (ret)
return ret;
if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
goto skip_regmap;
regcache_cache_only(afe->regmap, false);
regcache_sync(afe->regmap);
/* enable audio sys DCM for power saving */
regmap_update_bits(afe_priv->infracfg,
PERI_BUS_DCM_CTRL, 0x1 << 29, 0x1 << 29);
regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, 0x1 << 29, 0x1 << 29);
/* force cpu use 8_24 format when writing 32bit data */
regmap_update_bits(afe->regmap, AFE_MEMIF_CON0,
CPU_HD_ALIGN_MASK_SFT, 0 << CPU_HD_ALIGN_SFT);
/* set all output port to 24bit */
regmap_write(afe->regmap, AFE_CONN_24BIT, 0xffffffff);
regmap_write(afe->regmap, AFE_CONN_24BIT_1, 0xffffffff);
/* enable AFE */
regmap_update_bits(afe->regmap, AFE_DAC_CON0, AFE_ON_MASK_SFT, 0x1);
skip_regmap:
return 0;
}
static int mt8192_afe_component_probe(struct snd_soc_component *component)
{
return mtk_afe_add_sub_dai_control(component);
}
static const struct snd_soc_component_driver mt8192_afe_component = {
.name = AFE_PCM_NAME,
.probe = mt8192_afe_component_probe,
.pointer = mtk_afe_pcm_pointer,
.pcm_construct = mtk_afe_pcm_new,
};
static const struct snd_soc_component_driver mt8192_afe_pcm_component = {
.name = "mt8192-afe-pcm-dai",
};
static int mt8192_dai_memif_register(struct mtk_base_afe *afe)
{
struct mtk_base_afe_dai *dai;
dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
if (!dai)
return -ENOMEM;
list_add(&dai->list, &afe->sub_dais);
dai->dai_drivers = mt8192_memif_dai_driver;
dai->num_dai_drivers = ARRAY_SIZE(mt8192_memif_dai_driver);
dai->dapm_widgets = mt8192_memif_widgets;
dai->num_dapm_widgets = ARRAY_SIZE(mt8192_memif_widgets);
dai->dapm_routes = mt8192_memif_routes;
dai->num_dapm_routes = ARRAY_SIZE(mt8192_memif_routes);
return 0;
}
typedef int (*dai_register_cb)(struct mtk_base_afe *);
static const dai_register_cb dai_register_cbs[] = {
mt8192_dai_adda_register,
mt8192_dai_i2s_register,
mt8192_dai_pcm_register,
mt8192_dai_tdm_register,
mt8192_dai_memif_register,
};
static int mt8192_afe_pcm_dev_probe(struct platform_device *pdev)
{
struct mtk_base_afe *afe;
struct mt8192_afe_private *afe_priv;
struct device *dev;
struct reset_control *rstc;
int i, ret, irq_id;
ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(34));
if (ret)
return ret;
afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
if (!afe)
return -ENOMEM;
platform_set_drvdata(pdev, afe);
afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),
GFP_KERNEL);
if (!afe->platform_priv)
return -ENOMEM;
afe_priv = afe->platform_priv;
afe->dev = &pdev->dev;
dev = afe->dev;
/* init audio related clock */
ret = mt8192_init_clock(afe);
if (ret) {
dev_err(dev, "init clock error\n");
return ret;
}
/* reset controller to reset audio regs before regmap cache */
rstc = devm_reset_control_get_exclusive(dev, "audiosys");
if (IS_ERR(rstc)) {
ret = PTR_ERR(rstc);
dev_err(dev, "could not get audiosys reset:%d\n", ret);
return ret;
}
ret = reset_control_reset(rstc);
if (ret) {
dev_err(dev, "failed to trigger audio reset:%d\n", ret);
return ret;
}
pm_runtime_enable(&pdev->dev);
if (!pm_runtime_enabled(&pdev->dev))
goto err_pm_disable;
/* regmap init */
afe->regmap = syscon_node_to_regmap(dev->parent->of_node);
if (IS_ERR(afe->regmap)) {
dev_err(dev, "could not get regmap from parent\n");
ret = PTR_ERR(afe->regmap);
goto err_pm_disable;
}
ret = regmap_attach_dev(dev, afe->regmap, &mt8192_afe_regmap_config);
if (ret) {
dev_warn(dev, "regmap_attach_dev fail, ret %d\n", ret);
goto err_pm_disable;
}
/* enable clock for regcache get default value from hw */
afe_priv->pm_runtime_bypass_reg_ctl = true;
pm_runtime_get_sync(&pdev->dev);
ret = regmap_reinit_cache(afe->regmap, &mt8192_afe_regmap_config);
if (ret) {
dev_err(dev, "regmap_reinit_cache fail, ret %d\n", ret);
goto err_pm_disable;
}
pm_runtime_put_sync(&pdev->dev);
afe_priv->pm_runtime_bypass_reg_ctl = false;
regcache_cache_only(afe->regmap, true);
regcache_mark_dirty(afe->regmap);
/* init memif */
afe->memif_size = MT8192_MEMIF_NUM;
afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),
GFP_KERNEL);
if (!afe->memif) {
ret = -ENOMEM;
goto err_pm_disable;
}
for (i = 0; i < afe->memif_size; i++) {
afe->memif[i].data = &memif_data[i];
afe->memif[i].irq_usage = memif_irq_usage[i];
afe->memif[i].const_irq = 1;
}
mutex_init(&afe->irq_alloc_lock); /* needed when dynamic irq */
/* init irq */
afe->irqs_size = MT8192_IRQ_NUM;
afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
GFP_KERNEL);
if (!afe->irqs) {
ret = -ENOMEM;
goto err_pm_disable;
}
for (i = 0; i < afe->irqs_size; i++)
afe->irqs[i].irq_data = &irq_data[i];
/* request irq */
irq_id = platform_get_irq(pdev, 0);
if (irq_id < 0) {
ret = irq_id;
goto err_pm_disable;
}
ret = devm_request_irq(dev, irq_id, mt8192_afe_irq_handler,
IRQF_TRIGGER_NONE, "asys-isr", (void *)afe);
if (ret) {
dev_err(dev, "could not request_irq for Afe_ISR_Handle\n");
goto err_pm_disable;
}
/* init sub_dais */
INIT_LIST_HEAD(&afe->sub_dais);
for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) {
ret = dai_register_cbs[i](afe);
if (ret) {
dev_warn(afe->dev, "dai register i %d fail, ret %d\n",
i, ret);
goto err_pm_disable;
}
}
/* init dai_driver and component_driver */
ret = mtk_afe_combine_sub_dai(afe);
if (ret) {
dev_warn(afe->dev, "mtk_afe_combine_sub_dai fail, ret %d\n",
ret);
goto err_pm_disable;
}
/* others */
afe->mtk_afe_hardware = &mt8192_afe_hardware;
afe->memif_fs = mt8192_memif_fs;
afe->irq_fs = mt8192_irq_fs;
afe->get_dai_fs = mt8192_get_dai_fs;
afe->get_memif_pbuf_size = mt8192_get_memif_pbuf_size;
afe->memif_32bit_supported = 1;
afe->runtime_resume = mt8192_afe_runtime_resume;
afe->runtime_suspend = mt8192_afe_runtime_suspend;
/* register platform */
ret = devm_snd_soc_register_component(&pdev->dev,
&mt8192_afe_component, NULL, 0);
if (ret) {
dev_warn(dev, "err_platform\n");
goto err_pm_disable;
}
ret = devm_snd_soc_register_component(&pdev->dev,
&mt8192_afe_pcm_component,
afe->dai_drivers,
afe->num_dai_drivers);
if (ret) {
dev_warn(dev, "err_dai_component\n");
goto err_pm_disable;
}
return 0;
err_pm_disable:
pm_runtime_disable(&pdev->dev);
return ret;
}
static void mt8192_afe_pcm_dev_remove(struct platform_device *pdev)
{
struct mtk_base_afe *afe = platform_get_drvdata(pdev);
pm_runtime_disable(&pdev->dev);
if (!pm_runtime_status_suspended(&pdev->dev))
mt8192_afe_runtime_suspend(&pdev->dev);
/* disable afe clock */
mt8192_afe_disable_clock(afe);
}
static const struct of_device_id mt8192_afe_pcm_dt_match[] = {
{ .compatible = "mediatek,mt8192-audio", },
{},
};
MODULE_DEVICE_TABLE(of, mt8192_afe_pcm_dt_match);
static const struct dev_pm_ops mt8192_afe_pm_ops = {
SET_RUNTIME_PM_OPS(mt8192_afe_runtime_suspend,
mt8192_afe_runtime_resume, NULL)
};
static struct platform_driver mt8192_afe_pcm_driver = {
.driver = {
.name = "mt8192-audio",
.of_match_table = mt8192_afe_pcm_dt_match,
.pm = &mt8192_afe_pm_ops,
},
.probe = mt8192_afe_pcm_dev_probe,
.remove_new = mt8192_afe_pcm_dev_remove,
};
module_platform_driver(mt8192_afe_pcm_driver);
MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 8192");
MODULE_AUTHOR("Shane Chien <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/mediatek/mt8192/mt8192-afe-pcm.c |
// SPDX-License-Identifier: GPL-2.0
//
// MediaTek ALSA SoC Audio DAI TDM Control
//
// Copyright (c) 2020 MediaTek Inc.
// Author: Shane Chien <[email protected]>
#include <linux/regmap.h>
#include <sound/pcm_params.h>
#include "mt8192-afe-clk.h"
#include "mt8192-afe-common.h"
#include "mt8192-afe-gpio.h"
#include "mt8192-interconnection.h"
struct mtk_afe_tdm_priv {
int id;
int bck_id;
int bck_rate;
int tdm_out_mode;
int bck_invert;
int lck_invert;
int mclk_id;
int mclk_multiple; /* according to sample rate */
int mclk_rate;
int mclk_apll;
};
enum {
TDM_OUT_I2S = 0,
TDM_OUT_DSP_A = 1,
TDM_OUT_DSP_B = 2,
};
enum {
TDM_BCK_NON_INV = 0,
TDM_BCK_INV = 1,
};
enum {
TDM_LCK_NON_INV = 0,
TDM_LCK_INV = 1,
};
enum {
TDM_WLEN_16_BIT = 1,
TDM_WLEN_32_BIT = 2,
};
enum {
TDM_CHANNEL_BCK_16 = 0,
TDM_CHANNEL_BCK_24 = 1,
TDM_CHANNEL_BCK_32 = 2,
};
enum {
TDM_CHANNEL_NUM_2 = 0,
TDM_CHANNEL_NUM_4 = 1,
TDM_CHANNEL_NUM_8 = 2,
};
enum {
TDM_CH_START_O30_O31 = 0,
TDM_CH_START_O32_O33,
TDM_CH_START_O34_O35,
TDM_CH_START_O36_O37,
TDM_CH_ZERO,
};
static unsigned int get_tdm_wlen(snd_pcm_format_t format)
{
return snd_pcm_format_physical_width(format) <= 16 ?
TDM_WLEN_16_BIT : TDM_WLEN_32_BIT;
}
static unsigned int get_tdm_channel_bck(snd_pcm_format_t format)
{
return snd_pcm_format_physical_width(format) <= 16 ?
TDM_CHANNEL_BCK_16 : TDM_CHANNEL_BCK_32;
}
static unsigned int get_tdm_lrck_width(snd_pcm_format_t format)
{
return snd_pcm_format_physical_width(format) - 1;
}
static unsigned int get_tdm_ch(unsigned int ch)
{
switch (ch) {
case 1:
case 2:
return TDM_CHANNEL_NUM_2;
case 3:
case 4:
return TDM_CHANNEL_NUM_4;
case 5:
case 6:
case 7:
case 8:
default:
return TDM_CHANNEL_NUM_8;
}
}
static unsigned int get_tdm_ch_fixup(unsigned int channels)
{
if (channels > 4)
return 8;
else if (channels > 2)
return 4;
else
return 2;
}
static unsigned int get_tdm_ch_per_sdata(unsigned int mode,
unsigned int channels)
{
if (mode == TDM_OUT_DSP_A || mode == TDM_OUT_DSP_B)
return get_tdm_ch_fixup(channels);
else
return 2;
}
/* interconnection */
enum {
HDMI_CONN_CH0 = 0,
HDMI_CONN_CH1,
HDMI_CONN_CH2,
HDMI_CONN_CH3,
HDMI_CONN_CH4,
HDMI_CONN_CH5,
HDMI_CONN_CH6,
HDMI_CONN_CH7,
};
static const char *const hdmi_conn_mux_map[] = {
"CH0", "CH1", "CH2", "CH3",
"CH4", "CH5", "CH6", "CH7",
};
static int hdmi_conn_mux_map_value[] = {
HDMI_CONN_CH0,
HDMI_CONN_CH1,
HDMI_CONN_CH2,
HDMI_CONN_CH3,
HDMI_CONN_CH4,
HDMI_CONN_CH5,
HDMI_CONN_CH6,
HDMI_CONN_CH7,
};
static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch0_mux_map_enum,
AFE_HDMI_CONN0,
HDMI_O_0_SFT,
HDMI_O_0_MASK,
hdmi_conn_mux_map,
hdmi_conn_mux_map_value);
static const struct snd_kcontrol_new hdmi_ch0_mux_control =
SOC_DAPM_ENUM("HDMI_CH0_MUX", hdmi_ch0_mux_map_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch1_mux_map_enum,
AFE_HDMI_CONN0,
HDMI_O_1_SFT,
HDMI_O_1_MASK,
hdmi_conn_mux_map,
hdmi_conn_mux_map_value);
static const struct snd_kcontrol_new hdmi_ch1_mux_control =
SOC_DAPM_ENUM("HDMI_CH1_MUX", hdmi_ch1_mux_map_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch2_mux_map_enum,
AFE_HDMI_CONN0,
HDMI_O_2_SFT,
HDMI_O_2_MASK,
hdmi_conn_mux_map,
hdmi_conn_mux_map_value);
static const struct snd_kcontrol_new hdmi_ch2_mux_control =
SOC_DAPM_ENUM("HDMI_CH2_MUX", hdmi_ch2_mux_map_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch3_mux_map_enum,
AFE_HDMI_CONN0,
HDMI_O_3_SFT,
HDMI_O_3_MASK,
hdmi_conn_mux_map,
hdmi_conn_mux_map_value);
static const struct snd_kcontrol_new hdmi_ch3_mux_control =
SOC_DAPM_ENUM("HDMI_CH3_MUX", hdmi_ch3_mux_map_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch4_mux_map_enum,
AFE_HDMI_CONN0,
HDMI_O_4_SFT,
HDMI_O_4_MASK,
hdmi_conn_mux_map,
hdmi_conn_mux_map_value);
static const struct snd_kcontrol_new hdmi_ch4_mux_control =
SOC_DAPM_ENUM("HDMI_CH4_MUX", hdmi_ch4_mux_map_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch5_mux_map_enum,
AFE_HDMI_CONN0,
HDMI_O_5_SFT,
HDMI_O_5_MASK,
hdmi_conn_mux_map,
hdmi_conn_mux_map_value);
static const struct snd_kcontrol_new hdmi_ch5_mux_control =
SOC_DAPM_ENUM("HDMI_CH5_MUX", hdmi_ch5_mux_map_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch6_mux_map_enum,
AFE_HDMI_CONN0,
HDMI_O_6_SFT,
HDMI_O_6_MASK,
hdmi_conn_mux_map,
hdmi_conn_mux_map_value);
static const struct snd_kcontrol_new hdmi_ch6_mux_control =
SOC_DAPM_ENUM("HDMI_CH6_MUX", hdmi_ch6_mux_map_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch7_mux_map_enum,
AFE_HDMI_CONN0,
HDMI_O_7_SFT,
HDMI_O_7_MASK,
hdmi_conn_mux_map,
hdmi_conn_mux_map_value);
static const struct snd_kcontrol_new hdmi_ch7_mux_control =
SOC_DAPM_ENUM("HDMI_CH7_MUX", hdmi_ch7_mux_map_enum);
enum {
SUPPLY_SEQ_APLL,
SUPPLY_SEQ_TDM_MCK_EN,
SUPPLY_SEQ_TDM_BCK_EN,
SUPPLY_SEQ_TDM_EN,
};
static int get_tdm_id_by_name(const char *name)
{
return MT8192_DAI_TDM;
}
static int mtk_tdm_en_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8192_afe_private *afe_priv = afe->platform_priv;
int dai_id = get_tdm_id_by_name(w->name);
struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[dai_id];
if (!tdm_priv) {
dev_warn(afe->dev, "%s(), tdm_priv == NULL", __func__);
return -EINVAL;
}
dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x\n",
__func__, w->name, event);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
mt8192_afe_gpio_request(afe->dev, true, tdm_priv->id, 0);
break;
case SND_SOC_DAPM_POST_PMD:
mt8192_afe_gpio_request(afe->dev, false, tdm_priv->id, 0);
break;
default:
break;
}
return 0;
}
static int mtk_tdm_bck_en_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8192_afe_private *afe_priv = afe->platform_priv;
int dai_id = get_tdm_id_by_name(w->name);
struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[dai_id];
if (!tdm_priv) {
dev_warn(afe->dev, "%s(), tdm_priv == NULL", __func__);
return -EINVAL;
}
dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x, dai_id %d\n",
__func__, w->name, event, dai_id);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
mt8192_mck_enable(afe, tdm_priv->bck_id, tdm_priv->bck_rate);
break;
case SND_SOC_DAPM_POST_PMD:
mt8192_mck_disable(afe, tdm_priv->bck_id);
break;
default:
break;
}
return 0;
}
static int mtk_tdm_mck_en_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8192_afe_private *afe_priv = afe->platform_priv;
int dai_id = get_tdm_id_by_name(w->name);
struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[dai_id];
if (!tdm_priv) {
dev_warn(afe->dev, "%s(), tdm_priv == NULL", __func__);
return -EINVAL;
}
dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x, dai_id %d\n",
__func__, w->name, event, dai_id);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
mt8192_mck_enable(afe, tdm_priv->mclk_id, tdm_priv->mclk_rate);
break;
case SND_SOC_DAPM_POST_PMD:
tdm_priv->mclk_rate = 0;
mt8192_mck_disable(afe, tdm_priv->mclk_id);
break;
default:
break;
}
return 0;
}
static const struct snd_soc_dapm_widget mtk_dai_tdm_widgets[] = {
SND_SOC_DAPM_MUX("HDMI_CH0_MUX", SND_SOC_NOPM, 0, 0,
&hdmi_ch0_mux_control),
SND_SOC_DAPM_MUX("HDMI_CH1_MUX", SND_SOC_NOPM, 0, 0,
&hdmi_ch1_mux_control),
SND_SOC_DAPM_MUX("HDMI_CH2_MUX", SND_SOC_NOPM, 0, 0,
&hdmi_ch2_mux_control),
SND_SOC_DAPM_MUX("HDMI_CH3_MUX", SND_SOC_NOPM, 0, 0,
&hdmi_ch3_mux_control),
SND_SOC_DAPM_MUX("HDMI_CH4_MUX", SND_SOC_NOPM, 0, 0,
&hdmi_ch4_mux_control),
SND_SOC_DAPM_MUX("HDMI_CH5_MUX", SND_SOC_NOPM, 0, 0,
&hdmi_ch5_mux_control),
SND_SOC_DAPM_MUX("HDMI_CH6_MUX", SND_SOC_NOPM, 0, 0,
&hdmi_ch6_mux_control),
SND_SOC_DAPM_MUX("HDMI_CH7_MUX", SND_SOC_NOPM, 0, 0,
&hdmi_ch7_mux_control),
SND_SOC_DAPM_CLOCK_SUPPLY("aud_tdm_clk"),
SND_SOC_DAPM_SUPPLY_S("TDM_EN", SUPPLY_SEQ_TDM_EN,
AFE_TDM_CON1, TDM_EN_SFT, 0,
mtk_tdm_en_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("TDM_BCK", SUPPLY_SEQ_TDM_BCK_EN,
SND_SOC_NOPM, 0, 0,
mtk_tdm_bck_en_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("TDM_MCK", SUPPLY_SEQ_TDM_MCK_EN,
SND_SOC_NOPM, 0, 0,
mtk_tdm_mck_en_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
};
static int mtk_afe_tdm_apll_connect(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_dapm_widget *w = sink;
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8192_afe_private *afe_priv = afe->platform_priv;
int dai_id = get_tdm_id_by_name(w->name);
struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[dai_id];
int cur_apll;
/* which apll */
cur_apll = mt8192_get_apll_by_name(afe, source->name);
return (tdm_priv->mclk_apll == cur_apll) ? 1 : 0;
}
static const struct snd_soc_dapm_route mtk_dai_tdm_routes[] = {
{"HDMI_CH0_MUX", "CH0", "HDMI"},
{"HDMI_CH0_MUX", "CH1", "HDMI"},
{"HDMI_CH0_MUX", "CH2", "HDMI"},
{"HDMI_CH0_MUX", "CH3", "HDMI"},
{"HDMI_CH0_MUX", "CH4", "HDMI"},
{"HDMI_CH0_MUX", "CH5", "HDMI"},
{"HDMI_CH0_MUX", "CH6", "HDMI"},
{"HDMI_CH0_MUX", "CH7", "HDMI"},
{"HDMI_CH1_MUX", "CH0", "HDMI"},
{"HDMI_CH1_MUX", "CH1", "HDMI"},
{"HDMI_CH1_MUX", "CH2", "HDMI"},
{"HDMI_CH1_MUX", "CH3", "HDMI"},
{"HDMI_CH1_MUX", "CH4", "HDMI"},
{"HDMI_CH1_MUX", "CH5", "HDMI"},
{"HDMI_CH1_MUX", "CH6", "HDMI"},
{"HDMI_CH1_MUX", "CH7", "HDMI"},
{"HDMI_CH2_MUX", "CH0", "HDMI"},
{"HDMI_CH2_MUX", "CH1", "HDMI"},
{"HDMI_CH2_MUX", "CH2", "HDMI"},
{"HDMI_CH2_MUX", "CH3", "HDMI"},
{"HDMI_CH2_MUX", "CH4", "HDMI"},
{"HDMI_CH2_MUX", "CH5", "HDMI"},
{"HDMI_CH2_MUX", "CH6", "HDMI"},
{"HDMI_CH2_MUX", "CH7", "HDMI"},
{"HDMI_CH3_MUX", "CH0", "HDMI"},
{"HDMI_CH3_MUX", "CH1", "HDMI"},
{"HDMI_CH3_MUX", "CH2", "HDMI"},
{"HDMI_CH3_MUX", "CH3", "HDMI"},
{"HDMI_CH3_MUX", "CH4", "HDMI"},
{"HDMI_CH3_MUX", "CH5", "HDMI"},
{"HDMI_CH3_MUX", "CH6", "HDMI"},
{"HDMI_CH3_MUX", "CH7", "HDMI"},
{"HDMI_CH4_MUX", "CH0", "HDMI"},
{"HDMI_CH4_MUX", "CH1", "HDMI"},
{"HDMI_CH4_MUX", "CH2", "HDMI"},
{"HDMI_CH4_MUX", "CH3", "HDMI"},
{"HDMI_CH4_MUX", "CH4", "HDMI"},
{"HDMI_CH4_MUX", "CH5", "HDMI"},
{"HDMI_CH4_MUX", "CH6", "HDMI"},
{"HDMI_CH4_MUX", "CH7", "HDMI"},
{"HDMI_CH5_MUX", "CH0", "HDMI"},
{"HDMI_CH5_MUX", "CH1", "HDMI"},
{"HDMI_CH5_MUX", "CH2", "HDMI"},
{"HDMI_CH5_MUX", "CH3", "HDMI"},
{"HDMI_CH5_MUX", "CH4", "HDMI"},
{"HDMI_CH5_MUX", "CH5", "HDMI"},
{"HDMI_CH5_MUX", "CH6", "HDMI"},
{"HDMI_CH5_MUX", "CH7", "HDMI"},
{"HDMI_CH6_MUX", "CH0", "HDMI"},
{"HDMI_CH6_MUX", "CH1", "HDMI"},
{"HDMI_CH6_MUX", "CH2", "HDMI"},
{"HDMI_CH6_MUX", "CH3", "HDMI"},
{"HDMI_CH6_MUX", "CH4", "HDMI"},
{"HDMI_CH6_MUX", "CH5", "HDMI"},
{"HDMI_CH6_MUX", "CH6", "HDMI"},
{"HDMI_CH6_MUX", "CH7", "HDMI"},
{"HDMI_CH7_MUX", "CH0", "HDMI"},
{"HDMI_CH7_MUX", "CH1", "HDMI"},
{"HDMI_CH7_MUX", "CH2", "HDMI"},
{"HDMI_CH7_MUX", "CH3", "HDMI"},
{"HDMI_CH7_MUX", "CH4", "HDMI"},
{"HDMI_CH7_MUX", "CH5", "HDMI"},
{"HDMI_CH7_MUX", "CH6", "HDMI"},
{"HDMI_CH7_MUX", "CH7", "HDMI"},
{"TDM", NULL, "HDMI_CH0_MUX"},
{"TDM", NULL, "HDMI_CH1_MUX"},
{"TDM", NULL, "HDMI_CH2_MUX"},
{"TDM", NULL, "HDMI_CH3_MUX"},
{"TDM", NULL, "HDMI_CH4_MUX"},
{"TDM", NULL, "HDMI_CH5_MUX"},
{"TDM", NULL, "HDMI_CH6_MUX"},
{"TDM", NULL, "HDMI_CH7_MUX"},
{"TDM", NULL, "aud_tdm_clk"},
{"TDM", NULL, "TDM_BCK"},
{"TDM", NULL, "TDM_EN"},
{"TDM_BCK", NULL, "TDM_MCK"},
{"TDM_MCK", NULL, APLL1_W_NAME, mtk_afe_tdm_apll_connect},
{"TDM_MCK", NULL, APLL2_W_NAME, mtk_afe_tdm_apll_connect},
};
/* dai ops */
static int mtk_dai_tdm_cal_mclk(struct mtk_base_afe *afe,
struct mtk_afe_tdm_priv *tdm_priv,
int freq)
{
int apll;
int apll_rate;
apll = mt8192_get_apll_by_rate(afe, freq);
apll_rate = mt8192_get_apll_rate(afe, apll);
if (!freq || freq > apll_rate) {
dev_warn(afe->dev,
"%s(), freq(%d Hz) invalid\n", __func__, freq);
return -EINVAL;
}
if (apll_rate % freq != 0) {
dev_warn(afe->dev,
"%s(), APLL cannot generate %d Hz", __func__, freq);
return -EINVAL;
}
tdm_priv->mclk_rate = freq;
tdm_priv->mclk_apll = apll;
return 0;
}
static int mtk_dai_tdm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8192_afe_private *afe_priv = afe->platform_priv;
int tdm_id = dai->id;
struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[tdm_id];
unsigned int tdm_out_mode = tdm_priv->tdm_out_mode;
unsigned int rate = params_rate(params);
unsigned int channels = params_channels(params);
unsigned int out_channels_per_sdata =
get_tdm_ch_per_sdata(tdm_out_mode, channels);
snd_pcm_format_t format = params_format(params);
unsigned int tdm_con = 0;
/* calculate mclk_rate, if not set explicitly */
if (!tdm_priv->mclk_rate) {
tdm_priv->mclk_rate = rate * tdm_priv->mclk_multiple;
mtk_dai_tdm_cal_mclk(afe,
tdm_priv,
tdm_priv->mclk_rate);
}
/* calculate bck */
tdm_priv->bck_rate = rate *
out_channels_per_sdata *
snd_pcm_format_physical_width(format);
if (tdm_priv->bck_rate > tdm_priv->mclk_rate)
dev_warn(afe->dev, "%s(), bck_rate > mclk_rate rate", __func__);
if (tdm_priv->mclk_rate % tdm_priv->bck_rate != 0)
dev_warn(afe->dev, "%s(), bck cannot generate", __func__);
dev_dbg(afe->dev, "%s(), id %d, rate %d, channels %d, format %d, mclk_rate %d, bck_rate %d\n",
__func__,
tdm_id, rate, channels, format,
tdm_priv->mclk_rate, tdm_priv->bck_rate);
dev_dbg(afe->dev, "%s(), out_channels_per_sdata = %d\n",
__func__, out_channels_per_sdata);
/* set tdm */
if (tdm_priv->bck_invert)
regmap_update_bits(afe->regmap, AUDIO_TOP_CON3,
BCK_INVERSE_MASK_SFT,
0x1 << BCK_INVERSE_SFT);
if (tdm_priv->lck_invert)
tdm_con |= 1 << LRCK_INVERSE_SFT;
if (tdm_priv->tdm_out_mode == TDM_OUT_I2S) {
tdm_con |= 1 << DELAY_DATA_SFT;
tdm_con |= get_tdm_lrck_width(format) << LRCK_TDM_WIDTH_SFT;
} else if (tdm_priv->tdm_out_mode == TDM_OUT_DSP_A) {
tdm_con |= 0 << DELAY_DATA_SFT;
tdm_con |= 0 << LRCK_TDM_WIDTH_SFT;
} else if (tdm_priv->tdm_out_mode == TDM_OUT_DSP_B) {
tdm_con |= 1 << DELAY_DATA_SFT;
tdm_con |= 0 << LRCK_TDM_WIDTH_SFT;
}
tdm_con |= 1 << LEFT_ALIGN_SFT;
tdm_con |= get_tdm_wlen(format) << WLEN_SFT;
tdm_con |= get_tdm_ch(out_channels_per_sdata) << CHANNEL_NUM_SFT;
tdm_con |= get_tdm_channel_bck(format) << CHANNEL_BCK_CYCLES_SFT;
regmap_write(afe->regmap, AFE_TDM_CON1, tdm_con);
if (out_channels_per_sdata == 2) {
switch (channels) {
case 1:
case 2:
tdm_con = TDM_CH_START_O30_O31 << ST_CH_PAIR_SOUT0_SFT;
tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT1_SFT;
tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT2_SFT;
tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT3_SFT;
break;
case 3:
case 4:
tdm_con = TDM_CH_START_O30_O31 << ST_CH_PAIR_SOUT0_SFT;
tdm_con |= TDM_CH_START_O32_O33 << ST_CH_PAIR_SOUT1_SFT;
tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT2_SFT;
tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT3_SFT;
break;
case 5:
case 6:
tdm_con = TDM_CH_START_O30_O31 << ST_CH_PAIR_SOUT0_SFT;
tdm_con |= TDM_CH_START_O32_O33 << ST_CH_PAIR_SOUT1_SFT;
tdm_con |= TDM_CH_START_O34_O35 << ST_CH_PAIR_SOUT2_SFT;
tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT3_SFT;
break;
case 7:
case 8:
tdm_con = TDM_CH_START_O30_O31 << ST_CH_PAIR_SOUT0_SFT;
tdm_con |= TDM_CH_START_O32_O33 << ST_CH_PAIR_SOUT1_SFT;
tdm_con |= TDM_CH_START_O34_O35 << ST_CH_PAIR_SOUT2_SFT;
tdm_con |= TDM_CH_START_O36_O37 << ST_CH_PAIR_SOUT3_SFT;
break;
default:
tdm_con = 0;
}
} else {
tdm_con = TDM_CH_START_O30_O31 << ST_CH_PAIR_SOUT0_SFT;
tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT1_SFT;
tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT2_SFT;
tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT3_SFT;
}
regmap_write(afe->regmap, AFE_TDM_CON2, tdm_con);
regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0,
HDMI_CH_NUM_MASK_SFT,
channels << HDMI_CH_NUM_SFT);
return 0;
}
static int mtk_dai_tdm_set_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct mtk_base_afe *afe = dev_get_drvdata(dai->dev);
struct mt8192_afe_private *afe_priv = afe->platform_priv;
struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[dai->id];
if (!tdm_priv) {
dev_warn(afe->dev, "%s(), tdm_priv == NULL", __func__);
return -EINVAL;
}
if (dir != SND_SOC_CLOCK_OUT) {
dev_warn(afe->dev, "%s(), dir != SND_SOC_CLOCK_OUT", __func__);
return -EINVAL;
}
dev_dbg(afe->dev, "%s(), freq %d\n", __func__, freq);
return mtk_dai_tdm_cal_mclk(afe, tdm_priv, freq);
}
static int mtk_dai_tdm_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct mtk_base_afe *afe = dev_get_drvdata(dai->dev);
struct mt8192_afe_private *afe_priv = afe->platform_priv;
struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[dai->id];
if (!tdm_priv) {
dev_warn(afe->dev, "%s(), tdm_priv == NULL", __func__);
return -EINVAL;
}
/* DAI mode*/
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
tdm_priv->tdm_out_mode = TDM_OUT_I2S;
break;
case SND_SOC_DAIFMT_DSP_A:
tdm_priv->tdm_out_mode = TDM_OUT_DSP_A;
break;
case SND_SOC_DAIFMT_DSP_B:
tdm_priv->tdm_out_mode = TDM_OUT_DSP_B;
break;
default:
tdm_priv->tdm_out_mode = TDM_OUT_I2S;
}
/* DAI clock inversion*/
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
tdm_priv->bck_invert = TDM_BCK_NON_INV;
tdm_priv->lck_invert = TDM_LCK_NON_INV;
break;
case SND_SOC_DAIFMT_NB_IF:
tdm_priv->bck_invert = TDM_BCK_NON_INV;
tdm_priv->lck_invert = TDM_LCK_INV;
break;
case SND_SOC_DAIFMT_IB_NF:
tdm_priv->bck_invert = TDM_BCK_INV;
tdm_priv->lck_invert = TDM_LCK_NON_INV;
break;
case SND_SOC_DAIFMT_IB_IF:
default:
tdm_priv->bck_invert = TDM_BCK_INV;
tdm_priv->lck_invert = TDM_LCK_INV;
break;
}
return 0;
}
static const struct snd_soc_dai_ops mtk_dai_tdm_ops = {
.hw_params = mtk_dai_tdm_hw_params,
.set_sysclk = mtk_dai_tdm_set_sysclk,
.set_fmt = mtk_dai_tdm_set_fmt,
};
/* dai driver */
#define MTK_TDM_RATES (SNDRV_PCM_RATE_8000_48000 |\
SNDRV_PCM_RATE_88200 |\
SNDRV_PCM_RATE_96000 |\
SNDRV_PCM_RATE_176400 |\
SNDRV_PCM_RATE_192000)
#define MTK_TDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver mtk_dai_tdm_driver[] = {
{
.name = "TDM",
.id = MT8192_DAI_TDM,
.playback = {
.stream_name = "TDM",
.channels_min = 2,
.channels_max = 8,
.rates = MTK_TDM_RATES,
.formats = MTK_TDM_FORMATS,
},
.ops = &mtk_dai_tdm_ops,
},
};
static struct mtk_afe_tdm_priv *init_tdm_priv_data(struct mtk_base_afe *afe)
{
struct mtk_afe_tdm_priv *tdm_priv;
tdm_priv = devm_kzalloc(afe->dev, sizeof(struct mtk_afe_tdm_priv),
GFP_KERNEL);
if (!tdm_priv)
return NULL;
tdm_priv->mclk_multiple = 512;
tdm_priv->bck_id = MT8192_I2S4_BCK;
tdm_priv->mclk_id = MT8192_I2S4_MCK;
tdm_priv->id = MT8192_DAI_TDM;
return tdm_priv;
}
int mt8192_dai_tdm_register(struct mtk_base_afe *afe)
{
struct mt8192_afe_private *afe_priv = afe->platform_priv;
struct mtk_afe_tdm_priv *tdm_priv;
struct mtk_base_afe_dai *dai;
dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
if (!dai)
return -ENOMEM;
list_add(&dai->list, &afe->sub_dais);
dai->dai_drivers = mtk_dai_tdm_driver;
dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_tdm_driver);
dai->dapm_widgets = mtk_dai_tdm_widgets;
dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_tdm_widgets);
dai->dapm_routes = mtk_dai_tdm_routes;
dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_tdm_routes);
tdm_priv = init_tdm_priv_data(afe);
if (!tdm_priv)
return -ENOMEM;
afe_priv->dai_priv[MT8192_DAI_TDM] = tdm_priv;
return 0;
}
| linux-master | sound/soc/mediatek/mt8192/mt8192-dai-tdm.c |
// SPDX-License-Identifier: GPL-2.0
//
// MediaTek ALSA SoC Audio Control
//
// Copyright (c) 2020 MediaTek Inc.
// Author: Shane Chien <[email protected]>
//
#include "mt8192-afe-common.h"
enum {
MTK_AFE_RATE_8K = 0,
MTK_AFE_RATE_11K = 1,
MTK_AFE_RATE_12K = 2,
MTK_AFE_RATE_384K = 3,
MTK_AFE_RATE_16K = 4,
MTK_AFE_RATE_22K = 5,
MTK_AFE_RATE_24K = 6,
MTK_AFE_RATE_352K = 7,
MTK_AFE_RATE_32K = 8,
MTK_AFE_RATE_44K = 9,
MTK_AFE_RATE_48K = 10,
MTK_AFE_RATE_88K = 11,
MTK_AFE_RATE_96K = 12,
MTK_AFE_RATE_176K = 13,
MTK_AFE_RATE_192K = 14,
MTK_AFE_RATE_260K = 15,
};
enum {
MTK_AFE_DAI_MEMIF_RATE_8K = 0,
MTK_AFE_DAI_MEMIF_RATE_16K = 1,
MTK_AFE_DAI_MEMIF_RATE_32K = 2,
MTK_AFE_DAI_MEMIF_RATE_48K = 3,
};
enum {
MTK_AFE_PCM_RATE_8K = 0,
MTK_AFE_PCM_RATE_16K = 1,
MTK_AFE_PCM_RATE_32K = 2,
MTK_AFE_PCM_RATE_48K = 3,
};
unsigned int mt8192_general_rate_transform(struct device *dev,
unsigned int rate)
{
switch (rate) {
case 8000:
return MTK_AFE_RATE_8K;
case 11025:
return MTK_AFE_RATE_11K;
case 12000:
return MTK_AFE_RATE_12K;
case 16000:
return MTK_AFE_RATE_16K;
case 22050:
return MTK_AFE_RATE_22K;
case 24000:
return MTK_AFE_RATE_24K;
case 32000:
return MTK_AFE_RATE_32K;
case 44100:
return MTK_AFE_RATE_44K;
case 48000:
return MTK_AFE_RATE_48K;
case 88200:
return MTK_AFE_RATE_88K;
case 96000:
return MTK_AFE_RATE_96K;
case 176400:
return MTK_AFE_RATE_176K;
case 192000:
return MTK_AFE_RATE_192K;
case 260000:
return MTK_AFE_RATE_260K;
case 352800:
return MTK_AFE_RATE_352K;
case 384000:
return MTK_AFE_RATE_384K;
default:
dev_warn(dev, "%s(), rate %u invalid, use %d!!!\n",
__func__,
rate, MTK_AFE_RATE_48K);
return MTK_AFE_RATE_48K;
}
}
static unsigned int dai_memif_rate_transform(struct device *dev,
unsigned int rate)
{
switch (rate) {
case 8000:
return MTK_AFE_DAI_MEMIF_RATE_8K;
case 16000:
return MTK_AFE_DAI_MEMIF_RATE_16K;
case 32000:
return MTK_AFE_DAI_MEMIF_RATE_32K;
case 48000:
return MTK_AFE_DAI_MEMIF_RATE_48K;
default:
dev_warn(dev, "%s(), rate %u invalid, use %d!!!\n",
__func__,
rate, MTK_AFE_DAI_MEMIF_RATE_16K);
return MTK_AFE_DAI_MEMIF_RATE_16K;
}
}
static unsigned int pcm_rate_transform(struct device *dev,
unsigned int rate)
{
switch (rate) {
case 8000:
return MTK_AFE_PCM_RATE_8K;
case 16000:
return MTK_AFE_PCM_RATE_16K;
case 32000:
return MTK_AFE_PCM_RATE_32K;
case 48000:
return MTK_AFE_PCM_RATE_48K;
default:
dev_warn(dev, "%s(), rate %u invalid, use %d!!!\n",
__func__,
rate, MTK_AFE_PCM_RATE_32K);
return MTK_AFE_PCM_RATE_32K;
}
}
unsigned int mt8192_rate_transform(struct device *dev,
unsigned int rate, int aud_blk)
{
switch (aud_blk) {
case MT8192_MEMIF_DAI:
case MT8192_MEMIF_MOD_DAI:
return dai_memif_rate_transform(dev, rate);
case MT8192_DAI_PCM_1:
case MT8192_DAI_PCM_2:
return pcm_rate_transform(dev, rate);
default:
return mt8192_general_rate_transform(dev, rate);
}
}
int mt8192_dai_set_priv(struct mtk_base_afe *afe, int id,
int priv_size, const void *priv_data)
{
struct mt8192_afe_private *afe_priv = afe->platform_priv;
void *temp_data;
temp_data = devm_kzalloc(afe->dev,
priv_size,
GFP_KERNEL);
if (!temp_data)
return -ENOMEM;
if (priv_data)
memcpy(temp_data, priv_data, priv_size);
afe_priv->dai_priv[id] = temp_data;
return 0;
}
| linux-master | sound/soc/mediatek/mt8192/mt8192-afe-control.c |
// SPDX-License-Identifier: GPL-2.0
//
// MediaTek ALSA SoC Audio DAI I2S Control
//
// Copyright (c) 2020 MediaTek Inc.
// Author: Shane Chien <[email protected]>
//
#include <linux/bitops.h>
#include <linux/regmap.h>
#include <sound/pcm_params.h>
#include "mt8192-afe-clk.h"
#include "mt8192-afe-common.h"
#include "mt8192-afe-gpio.h"
#include "mt8192-interconnection.h"
enum {
I2S_FMT_EIAJ = 0,
I2S_FMT_I2S = 1,
};
enum {
I2S_WLEN_16_BIT = 0,
I2S_WLEN_32_BIT = 1,
};
enum {
I2S_HD_NORMAL = 0,
I2S_HD_LOW_JITTER = 1,
};
enum {
I2S1_SEL_O28_O29 = 0,
I2S1_SEL_O03_O04 = 1,
};
enum {
I2S_IN_PAD_CONNSYS = 0,
I2S_IN_PAD_IO_MUX = 1,
};
struct mtk_afe_i2s_priv {
int id;
int rate; /* for determine which apll to use */
int low_jitter_en;
int share_i2s_id;
int mclk_id;
int mclk_rate;
int mclk_apll;
};
static unsigned int get_i2s_wlen(snd_pcm_format_t format)
{
return snd_pcm_format_physical_width(format) <= 16 ?
I2S_WLEN_16_BIT : I2S_WLEN_32_BIT;
}
#define MTK_AFE_I2S0_KCONTROL_NAME "I2S0_HD_Mux"
#define MTK_AFE_I2S1_KCONTROL_NAME "I2S1_HD_Mux"
#define MTK_AFE_I2S2_KCONTROL_NAME "I2S2_HD_Mux"
#define MTK_AFE_I2S3_KCONTROL_NAME "I2S3_HD_Mux"
#define MTK_AFE_I2S5_KCONTROL_NAME "I2S5_HD_Mux"
#define MTK_AFE_I2S6_KCONTROL_NAME "I2S6_HD_Mux"
#define MTK_AFE_I2S7_KCONTROL_NAME "I2S7_HD_Mux"
#define MTK_AFE_I2S8_KCONTROL_NAME "I2S8_HD_Mux"
#define MTK_AFE_I2S9_KCONTROL_NAME "I2S9_HD_Mux"
#define I2S0_HD_EN_W_NAME "I2S0_HD_EN"
#define I2S1_HD_EN_W_NAME "I2S1_HD_EN"
#define I2S2_HD_EN_W_NAME "I2S2_HD_EN"
#define I2S3_HD_EN_W_NAME "I2S3_HD_EN"
#define I2S5_HD_EN_W_NAME "I2S5_HD_EN"
#define I2S6_HD_EN_W_NAME "I2S6_HD_EN"
#define I2S7_HD_EN_W_NAME "I2S7_HD_EN"
#define I2S8_HD_EN_W_NAME "I2S8_HD_EN"
#define I2S9_HD_EN_W_NAME "I2S9_HD_EN"
#define I2S0_MCLK_EN_W_NAME "I2S0_MCLK_EN"
#define I2S1_MCLK_EN_W_NAME "I2S1_MCLK_EN"
#define I2S2_MCLK_EN_W_NAME "I2S2_MCLK_EN"
#define I2S3_MCLK_EN_W_NAME "I2S3_MCLK_EN"
#define I2S5_MCLK_EN_W_NAME "I2S5_MCLK_EN"
#define I2S6_MCLK_EN_W_NAME "I2S6_MCLK_EN"
#define I2S7_MCLK_EN_W_NAME "I2S7_MCLK_EN"
#define I2S8_MCLK_EN_W_NAME "I2S8_MCLK_EN"
#define I2S9_MCLK_EN_W_NAME "I2S9_MCLK_EN"
static int get_i2s_id_by_name(struct mtk_base_afe *afe,
const char *name)
{
if (strncmp(name, "I2S0", 4) == 0)
return MT8192_DAI_I2S_0;
else if (strncmp(name, "I2S1", 4) == 0)
return MT8192_DAI_I2S_1;
else if (strncmp(name, "I2S2", 4) == 0)
return MT8192_DAI_I2S_2;
else if (strncmp(name, "I2S3", 4) == 0)
return MT8192_DAI_I2S_3;
else if (strncmp(name, "I2S5", 4) == 0)
return MT8192_DAI_I2S_5;
else if (strncmp(name, "I2S6", 4) == 0)
return MT8192_DAI_I2S_6;
else if (strncmp(name, "I2S7", 4) == 0)
return MT8192_DAI_I2S_7;
else if (strncmp(name, "I2S8", 4) == 0)
return MT8192_DAI_I2S_8;
else if (strncmp(name, "I2S9", 4) == 0)
return MT8192_DAI_I2S_9;
else
return -EINVAL;
}
static struct mtk_afe_i2s_priv *get_i2s_priv_by_name(struct mtk_base_afe *afe,
const char *name)
{
struct mt8192_afe_private *afe_priv = afe->platform_priv;
int dai_id = get_i2s_id_by_name(afe, name);
if (dai_id < 0)
return NULL;
return afe_priv->dai_priv[dai_id];
}
/* low jitter control */
static const char * const mt8192_i2s_hd_str[] = {
"Normal", "Low_Jitter"
};
static SOC_ENUM_SINGLE_EXT_DECL(mt8192_i2s_enum, mt8192_i2s_hd_str);
static int mt8192_i2s_hd_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mtk_afe_i2s_priv *i2s_priv;
i2s_priv = get_i2s_priv_by_name(afe, kcontrol->id.name);
if (!i2s_priv) {
dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__);
return -EINVAL;
}
ucontrol->value.integer.value[0] = i2s_priv->low_jitter_en;
return 0;
}
static int mt8192_i2s_hd_set(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mtk_afe_i2s_priv *i2s_priv;
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
int hd_en;
if (ucontrol->value.enumerated.item[0] >= e->items)
return -EINVAL;
hd_en = ucontrol->value.integer.value[0];
dev_dbg(afe->dev, "%s(), kcontrol name %s, hd_en %d\n",
__func__, kcontrol->id.name, hd_en);
i2s_priv = get_i2s_priv_by_name(afe, kcontrol->id.name);
if (!i2s_priv) {
dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__);
return -EINVAL;
}
i2s_priv->low_jitter_en = hd_en;
return 0;
}
static const struct snd_kcontrol_new mtk_dai_i2s_controls[] = {
SOC_ENUM_EXT(MTK_AFE_I2S0_KCONTROL_NAME, mt8192_i2s_enum,
mt8192_i2s_hd_get, mt8192_i2s_hd_set),
SOC_ENUM_EXT(MTK_AFE_I2S1_KCONTROL_NAME, mt8192_i2s_enum,
mt8192_i2s_hd_get, mt8192_i2s_hd_set),
SOC_ENUM_EXT(MTK_AFE_I2S2_KCONTROL_NAME, mt8192_i2s_enum,
mt8192_i2s_hd_get, mt8192_i2s_hd_set),
SOC_ENUM_EXT(MTK_AFE_I2S3_KCONTROL_NAME, mt8192_i2s_enum,
mt8192_i2s_hd_get, mt8192_i2s_hd_set),
SOC_ENUM_EXT(MTK_AFE_I2S5_KCONTROL_NAME, mt8192_i2s_enum,
mt8192_i2s_hd_get, mt8192_i2s_hd_set),
SOC_ENUM_EXT(MTK_AFE_I2S6_KCONTROL_NAME, mt8192_i2s_enum,
mt8192_i2s_hd_get, mt8192_i2s_hd_set),
SOC_ENUM_EXT(MTK_AFE_I2S7_KCONTROL_NAME, mt8192_i2s_enum,
mt8192_i2s_hd_get, mt8192_i2s_hd_set),
SOC_ENUM_EXT(MTK_AFE_I2S8_KCONTROL_NAME, mt8192_i2s_enum,
mt8192_i2s_hd_get, mt8192_i2s_hd_set),
SOC_ENUM_EXT(MTK_AFE_I2S9_KCONTROL_NAME, mt8192_i2s_enum,
mt8192_i2s_hd_get, mt8192_i2s_hd_set),
};
/* dai component */
/* i2s virtual mux to output widget */
static const char * const i2s_mux_map[] = {
"Normal", "Dummy_Widget",
};
static int i2s_mux_map_value[] = {
0, 1,
};
static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(i2s_mux_map_enum,
SND_SOC_NOPM,
0,
1,
i2s_mux_map,
i2s_mux_map_value);
static const struct snd_kcontrol_new i2s0_in_mux_control =
SOC_DAPM_ENUM("I2S0 In Select", i2s_mux_map_enum);
static const struct snd_kcontrol_new i2s8_in_mux_control =
SOC_DAPM_ENUM("I2S8 In Select", i2s_mux_map_enum);
static const struct snd_kcontrol_new i2s1_out_mux_control =
SOC_DAPM_ENUM("I2S1 Out Select", i2s_mux_map_enum);
static const struct snd_kcontrol_new i2s3_out_mux_control =
SOC_DAPM_ENUM("I2S3 Out Select", i2s_mux_map_enum);
static const struct snd_kcontrol_new i2s5_out_mux_control =
SOC_DAPM_ENUM("I2S5 Out Select", i2s_mux_map_enum);
static const struct snd_kcontrol_new i2s7_out_mux_control =
SOC_DAPM_ENUM("I2S7 Out Select", i2s_mux_map_enum);
static const struct snd_kcontrol_new i2s9_out_mux_control =
SOC_DAPM_ENUM("I2S9 Out Select", i2s_mux_map_enum);
/* Tinyconn Mux */
enum {
TINYCONN_CH1_MUX_DL1 = 0x0,
TINYCONN_CH2_MUX_DL1 = 0x1,
TINYCONN_CH1_MUX_DL12 = 0x2,
TINYCONN_CH2_MUX_DL12 = 0x3,
TINYCONN_CH1_MUX_DL2 = 0x4,
TINYCONN_CH2_MUX_DL2 = 0x5,
TINYCONN_CH1_MUX_DL3 = 0x6,
TINYCONN_CH2_MUX_DL3 = 0x7,
TINYCONN_MUX_NONE = 0x1f,
};
static const char * const tinyconn_mux_map[] = {
"NONE",
"DL1_CH1",
"DL1_CH2",
"DL12_CH1",
"DL12_CH2",
"DL2_CH1",
"DL2_CH2",
"DL3_CH1",
"DL3_CH2",
};
static int tinyconn_mux_map_value[] = {
TINYCONN_MUX_NONE,
TINYCONN_CH1_MUX_DL1,
TINYCONN_CH2_MUX_DL1,
TINYCONN_CH1_MUX_DL12,
TINYCONN_CH2_MUX_DL12,
TINYCONN_CH1_MUX_DL2,
TINYCONN_CH2_MUX_DL2,
TINYCONN_CH1_MUX_DL3,
TINYCONN_CH2_MUX_DL3,
};
static SOC_VALUE_ENUM_SINGLE_DECL(i2s1_tinyconn_ch1_mux_map_enum,
AFE_TINY_CONN5,
O_20_CFG_SFT,
O_20_CFG_MASK,
tinyconn_mux_map,
tinyconn_mux_map_value);
static const struct snd_kcontrol_new i2s1_tinyconn_ch1_mux_control =
SOC_DAPM_ENUM("i2s1 ch1 tinyconn Select",
i2s1_tinyconn_ch1_mux_map_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(i2s1_tinyconn_ch2_mux_map_enum,
AFE_TINY_CONN5,
O_21_CFG_SFT,
O_21_CFG_MASK,
tinyconn_mux_map,
tinyconn_mux_map_value);
static const struct snd_kcontrol_new i2s1_tinyconn_ch2_mux_control =
SOC_DAPM_ENUM("i2s1 ch2 tinyconn Select",
i2s1_tinyconn_ch2_mux_map_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(i2s3_tinyconn_ch1_mux_map_enum,
AFE_TINY_CONN5,
O_22_CFG_SFT,
O_22_CFG_MASK,
tinyconn_mux_map,
tinyconn_mux_map_value);
static const struct snd_kcontrol_new i2s3_tinyconn_ch1_mux_control =
SOC_DAPM_ENUM("i2s3 ch1 tinyconn Select",
i2s3_tinyconn_ch1_mux_map_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(i2s3_tinyconn_ch2_mux_map_enum,
AFE_TINY_CONN5,
O_23_CFG_SFT,
O_23_CFG_MASK,
tinyconn_mux_map,
tinyconn_mux_map_value);
static const struct snd_kcontrol_new i2s3_tinyconn_ch2_mux_control =
SOC_DAPM_ENUM("i2s3 ch2 tinyconn Select",
i2s3_tinyconn_ch2_mux_map_enum);
/* i2s in lpbk */
static const char * const i2s_lpbk_mux_map[] = {
"Normal", "Lpbk",
};
static int i2s_lpbk_mux_map_value[] = {
0, 1,
};
static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(i2s0_lpbk_mux_map_enum,
AFE_I2S_CON,
I2S_LOOPBACK_SFT,
1,
i2s_lpbk_mux_map,
i2s_lpbk_mux_map_value);
static const struct snd_kcontrol_new i2s0_lpbk_mux_control =
SOC_DAPM_ENUM("I2S Lpbk Select", i2s0_lpbk_mux_map_enum);
static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(i2s2_lpbk_mux_map_enum,
AFE_I2S_CON2,
I2S3_LOOPBACK_SFT,
1,
i2s_lpbk_mux_map,
i2s_lpbk_mux_map_value);
static const struct snd_kcontrol_new i2s2_lpbk_mux_control =
SOC_DAPM_ENUM("I2S Lpbk Select", i2s2_lpbk_mux_map_enum);
/* interconnection */
static const struct snd_kcontrol_new mtk_i2s3_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN0, I_DL1_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN0, I_DL2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN0, I_DL3_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1", AFE_CONN0, I_DL12_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN0_1, I_DL6_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN0_1, I_DL4_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN0_1, I_DL5_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1", AFE_CONN0_1, I_DL8_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL9_CH1", AFE_CONN0_1, I_DL9_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1", AFE_CONN0,
I_GAIN1_OUT_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN0,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN0,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN0,
I_ADDA_UL_CH3, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN0,
I_PCM_1_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN0,
I_PCM_2_CAP_CH1, 1, 0),
};
static const struct snd_kcontrol_new mtk_i2s3_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN1, I_DL1_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN1, I_DL2_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN1, I_DL3_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2", AFE_CONN1, I_DL12_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN1_1, I_DL6_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN1_1, I_DL4_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN1_1, I_DL5_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2", AFE_CONN1_1, I_DL8_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL9_CH2", AFE_CONN1_1, I_DL9_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2", AFE_CONN1,
I_GAIN1_OUT_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN1,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN1,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN1,
I_ADDA_UL_CH3, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN1,
I_PCM_1_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN1,
I_PCM_2_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN1,
I_PCM_1_CAP_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN1,
I_PCM_2_CAP_CH2, 1, 0),
};
static const struct snd_kcontrol_new mtk_i2s1_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN28, I_DL1_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN28, I_DL2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN28, I_DL3_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1", AFE_CONN28, I_DL12_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN28_1, I_DL6_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN28_1, I_DL4_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN28_1, I_DL5_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1", AFE_CONN28_1, I_DL8_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL9_CH1", AFE_CONN28_1, I_DL9_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1", AFE_CONN28,
I_GAIN1_OUT_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN28,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN28,
I_PCM_1_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN28,
I_PCM_2_CAP_CH1, 1, 0),
};
static const struct snd_kcontrol_new mtk_i2s1_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN29, I_DL1_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN29, I_DL2_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN29, I_DL3_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2", AFE_CONN29, I_DL12_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN29_1, I_DL6_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN29_1, I_DL4_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN29_1, I_DL5_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2", AFE_CONN29_1, I_DL8_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL9_CH2", AFE_CONN29_1, I_DL9_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2", AFE_CONN29,
I_GAIN1_OUT_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN29,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN29,
I_PCM_1_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN29,
I_PCM_2_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN29,
I_PCM_1_CAP_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN29,
I_PCM_2_CAP_CH2, 1, 0),
};
static const struct snd_kcontrol_new mtk_i2s5_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN30, I_DL1_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN30, I_DL2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN30, I_DL3_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1", AFE_CONN30, I_DL12_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN30_1, I_DL6_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN30_1, I_DL4_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN30_1, I_DL5_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1", AFE_CONN30_1, I_DL8_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL9_CH1", AFE_CONN30_1, I_DL9_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1", AFE_CONN30,
I_GAIN1_OUT_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN30,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN30,
I_PCM_1_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN30,
I_PCM_2_CAP_CH1, 1, 0),
};
static const struct snd_kcontrol_new mtk_i2s5_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN31, I_DL1_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN31, I_DL2_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN31, I_DL3_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2", AFE_CONN31, I_DL12_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN31_1, I_DL6_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN31_1, I_DL4_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN31_1, I_DL5_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2", AFE_CONN31_1, I_DL8_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL9_CH2", AFE_CONN31_1, I_DL9_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2", AFE_CONN31,
I_GAIN1_OUT_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN31,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN31,
I_PCM_1_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN31,
I_PCM_2_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN31,
I_PCM_1_CAP_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN31,
I_PCM_2_CAP_CH2, 1, 0),
};
static const struct snd_kcontrol_new mtk_i2s7_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN54, I_DL1_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN54, I_DL2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN54, I_DL3_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1", AFE_CONN54, I_DL12_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN54_1, I_DL6_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN54_1, I_DL4_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN54_1, I_DL5_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL9_CH1", AFE_CONN54_1, I_DL9_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1", AFE_CONN54,
I_GAIN1_OUT_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN54,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN54,
I_PCM_1_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN54,
I_PCM_2_CAP_CH1, 1, 0),
};
static const struct snd_kcontrol_new mtk_i2s7_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN55, I_DL1_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN55, I_DL2_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN55, I_DL3_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2", AFE_CONN55, I_DL12_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN55_1, I_DL6_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN55_1, I_DL4_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN55_1, I_DL5_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL9_CH2", AFE_CONN55_1, I_DL9_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2", AFE_CONN55,
I_GAIN1_OUT_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN55,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN55,
I_PCM_1_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN55,
I_PCM_2_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN55,
I_PCM_1_CAP_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN55,
I_PCM_2_CAP_CH2, 1, 0),
};
static const struct snd_kcontrol_new mtk_i2s9_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN56, I_DL1_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN56, I_DL2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN56, I_DL3_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1", AFE_CONN56, I_DL12_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN56_1, I_DL6_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN56_1, I_DL4_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN56_1, I_DL5_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1", AFE_CONN56_1, I_DL8_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL9_CH1", AFE_CONN56_1, I_DL9_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1", AFE_CONN56,
I_GAIN1_OUT_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN56,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN56,
I_PCM_1_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN56,
I_PCM_2_CAP_CH1, 1, 0),
};
static const struct snd_kcontrol_new mtk_i2s9_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN57, I_DL1_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN57, I_DL2_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN57, I_DL3_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2", AFE_CONN57, I_DL12_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN57_1, I_DL6_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN57_1, I_DL4_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN57_1, I_DL5_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2", AFE_CONN57_1, I_DL8_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL9_CH2", AFE_CONN57_1, I_DL9_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2", AFE_CONN57,
I_GAIN1_OUT_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN57,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN57,
I_PCM_1_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN57,
I_PCM_2_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN57,
I_PCM_1_CAP_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN57,
I_PCM_2_CAP_CH2, 1, 0),
};
enum {
SUPPLY_SEQ_APLL,
SUPPLY_SEQ_I2S_MCLK_EN,
SUPPLY_SEQ_I2S_HD_EN,
SUPPLY_SEQ_I2S_EN,
};
static int mtk_i2s_en_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mtk_afe_i2s_priv *i2s_priv;
i2s_priv = get_i2s_priv_by_name(afe, w->name);
if (!i2s_priv) {
dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__);
return -EINVAL;
}
dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x\n",
__func__, w->name, event);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
mt8192_afe_gpio_request(afe->dev, true, i2s_priv->id, 0);
break;
case SND_SOC_DAPM_POST_PMD:
mt8192_afe_gpio_request(afe->dev, false, i2s_priv->id, 0);
break;
default:
break;
}
return 0;
}
static int mtk_apll_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x\n",
__func__, w->name, event);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
if (strcmp(w->name, APLL1_W_NAME) == 0)
mt8192_apll1_enable(afe);
else
mt8192_apll2_enable(afe);
break;
case SND_SOC_DAPM_POST_PMD:
if (strcmp(w->name, APLL1_W_NAME) == 0)
mt8192_apll1_disable(afe);
else
mt8192_apll2_disable(afe);
break;
default:
break;
}
return 0;
}
static int i2s_out_tinyconn_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
unsigned int reg;
unsigned int reg_shift;
unsigned int reg_mask_shift;
dev_dbg(afe->dev, "%s(), event 0x%x\n", __func__, event);
if (strstr(w->name, "I2S1")) {
reg = AFE_I2S_CON1;
reg_shift = I2S2_32BIT_EN_SFT;
reg_mask_shift = I2S2_32BIT_EN_MASK_SFT;
} else if (strstr(w->name, "I2S3")) {
reg = AFE_I2S_CON3;
reg_shift = I2S4_32BIT_EN_SFT;
reg_mask_shift = I2S4_32BIT_EN_MASK_SFT;
} else if (strstr(w->name, "I2S5")) {
reg = AFE_I2S_CON4;
reg_shift = I2S5_32BIT_EN_SFT;
reg_mask_shift = I2S5_32BIT_EN_MASK_SFT;
} else if (strstr(w->name, "I2S7")) {
reg = AFE_I2S_CON7;
reg_shift = I2S7_32BIT_EN_SFT;
reg_mask_shift = I2S7_32BIT_EN_MASK_SFT;
} else if (strstr(w->name, "I2S9")) {
reg = AFE_I2S_CON9;
reg_shift = I2S9_32BIT_EN_SFT;
reg_mask_shift = I2S9_32BIT_EN_MASK_SFT;
} else {
reg = AFE_I2S_CON1;
reg_shift = I2S2_32BIT_EN_SFT;
reg_mask_shift = I2S2_32BIT_EN_MASK_SFT;
dev_warn(afe->dev, "%s(), error widget name %s, use i2s1\n",
__func__, w->name);
}
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
regmap_update_bits(afe->regmap, reg, reg_mask_shift,
0x1 << reg_shift);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_update_bits(afe->regmap, reg, reg_mask_shift,
0x0 << reg_shift);
break;
default:
break;
}
return 0;
}
static int mtk_mclk_en_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mtk_afe_i2s_priv *i2s_priv;
dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x\n",
__func__, w->name, event);
i2s_priv = get_i2s_priv_by_name(afe, w->name);
if (!i2s_priv) {
dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__);
return -EINVAL;
}
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
mt8192_mck_enable(afe, i2s_priv->mclk_id, i2s_priv->mclk_rate);
break;
case SND_SOC_DAPM_POST_PMD:
i2s_priv->mclk_rate = 0;
mt8192_mck_disable(afe, i2s_priv->mclk_id);
break;
default:
break;
}
return 0;
}
static const struct snd_soc_dapm_widget mtk_dai_i2s_widgets[] = {
SND_SOC_DAPM_INPUT("CONNSYS"),
SND_SOC_DAPM_MIXER("I2S1_CH1", SND_SOC_NOPM, 0, 0,
mtk_i2s1_ch1_mix,
ARRAY_SIZE(mtk_i2s1_ch1_mix)),
SND_SOC_DAPM_MIXER("I2S1_CH2", SND_SOC_NOPM, 0, 0,
mtk_i2s1_ch2_mix,
ARRAY_SIZE(mtk_i2s1_ch2_mix)),
SND_SOC_DAPM_MIXER("I2S3_CH1", SND_SOC_NOPM, 0, 0,
mtk_i2s3_ch1_mix,
ARRAY_SIZE(mtk_i2s3_ch1_mix)),
SND_SOC_DAPM_MIXER("I2S3_CH2", SND_SOC_NOPM, 0, 0,
mtk_i2s3_ch2_mix,
ARRAY_SIZE(mtk_i2s3_ch2_mix)),
SND_SOC_DAPM_MIXER("I2S5_CH1", SND_SOC_NOPM, 0, 0,
mtk_i2s5_ch1_mix,
ARRAY_SIZE(mtk_i2s5_ch1_mix)),
SND_SOC_DAPM_MIXER("I2S5_CH2", SND_SOC_NOPM, 0, 0,
mtk_i2s5_ch2_mix,
ARRAY_SIZE(mtk_i2s5_ch2_mix)),
SND_SOC_DAPM_MIXER("I2S7_CH1", SND_SOC_NOPM, 0, 0,
mtk_i2s7_ch1_mix,
ARRAY_SIZE(mtk_i2s7_ch1_mix)),
SND_SOC_DAPM_MIXER("I2S7_CH2", SND_SOC_NOPM, 0, 0,
mtk_i2s7_ch2_mix,
ARRAY_SIZE(mtk_i2s7_ch2_mix)),
SND_SOC_DAPM_MIXER("I2S9_CH1", SND_SOC_NOPM, 0, 0,
mtk_i2s9_ch1_mix,
ARRAY_SIZE(mtk_i2s9_ch1_mix)),
SND_SOC_DAPM_MIXER("I2S9_CH2", SND_SOC_NOPM, 0, 0,
mtk_i2s9_ch2_mix,
ARRAY_SIZE(mtk_i2s9_ch2_mix)),
SND_SOC_DAPM_MUX_E("I2S1_TINYCONN_CH1_MUX", SND_SOC_NOPM, 0, 0,
&i2s1_tinyconn_ch1_mux_control,
i2s_out_tinyconn_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_MUX_E("I2S1_TINYCONN_CH2_MUX", SND_SOC_NOPM, 0, 0,
&i2s1_tinyconn_ch2_mux_control,
i2s_out_tinyconn_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_MUX_E("I2S3_TINYCONN_CH1_MUX", SND_SOC_NOPM, 0, 0,
&i2s3_tinyconn_ch1_mux_control,
i2s_out_tinyconn_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_MUX_E("I2S3_TINYCONN_CH2_MUX", SND_SOC_NOPM, 0, 0,
&i2s3_tinyconn_ch2_mux_control,
i2s_out_tinyconn_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
/* i2s en*/
SND_SOC_DAPM_SUPPLY_S("I2S0_EN", SUPPLY_SEQ_I2S_EN,
AFE_I2S_CON, I2S_EN_SFT, 0,
mtk_i2s_en_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("I2S1_EN", SUPPLY_SEQ_I2S_EN,
AFE_I2S_CON1, I2S_EN_SFT, 0,
mtk_i2s_en_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("I2S2_EN", SUPPLY_SEQ_I2S_EN,
AFE_I2S_CON2, I2S_EN_SFT, 0,
mtk_i2s_en_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("I2S3_EN", SUPPLY_SEQ_I2S_EN,
AFE_I2S_CON3, I2S_EN_SFT, 0,
mtk_i2s_en_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("I2S5_EN", SUPPLY_SEQ_I2S_EN,
AFE_I2S_CON4, I2S5_EN_SFT, 0,
mtk_i2s_en_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("I2S6_EN", SUPPLY_SEQ_I2S_EN,
AFE_I2S_CON6, I2S6_EN_SFT, 0,
mtk_i2s_en_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("I2S7_EN", SUPPLY_SEQ_I2S_EN,
AFE_I2S_CON7, I2S7_EN_SFT, 0,
mtk_i2s_en_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("I2S8_EN", SUPPLY_SEQ_I2S_EN,
AFE_I2S_CON8, I2S8_EN_SFT, 0,
mtk_i2s_en_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("I2S9_EN", SUPPLY_SEQ_I2S_EN,
AFE_I2S_CON9, I2S9_EN_SFT, 0,
mtk_i2s_en_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
/* i2s hd en */
SND_SOC_DAPM_SUPPLY_S(I2S0_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
AFE_I2S_CON, I2S1_HD_EN_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S(I2S1_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
AFE_I2S_CON1, I2S2_HD_EN_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S(I2S2_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
AFE_I2S_CON2, I2S3_HD_EN_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S(I2S3_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
AFE_I2S_CON3, I2S4_HD_EN_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S(I2S5_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
AFE_I2S_CON4, I2S5_HD_EN_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S(I2S6_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
AFE_I2S_CON6, I2S6_HD_EN_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S(I2S7_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
AFE_I2S_CON7, I2S7_HD_EN_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S(I2S8_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
AFE_I2S_CON8, I2S8_HD_EN_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S(I2S9_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
AFE_I2S_CON9, I2S9_HD_EN_SFT, 0, NULL, 0),
/* i2s mclk en */
SND_SOC_DAPM_SUPPLY_S(I2S0_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
SND_SOC_NOPM, 0, 0,
mtk_mclk_en_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S(I2S1_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
SND_SOC_NOPM, 0, 0,
mtk_mclk_en_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S(I2S2_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
SND_SOC_NOPM, 0, 0,
mtk_mclk_en_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S(I2S3_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
SND_SOC_NOPM, 0, 0,
mtk_mclk_en_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S(I2S5_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
SND_SOC_NOPM, 0, 0,
mtk_mclk_en_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S(I2S6_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
SND_SOC_NOPM, 0, 0,
mtk_mclk_en_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S(I2S7_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
SND_SOC_NOPM, 0, 0,
mtk_mclk_en_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S(I2S8_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
SND_SOC_NOPM, 0, 0,
mtk_mclk_en_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S(I2S9_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
SND_SOC_NOPM, 0, 0,
mtk_mclk_en_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
/* apll */
SND_SOC_DAPM_SUPPLY_S(APLL1_W_NAME, SUPPLY_SEQ_APLL,
SND_SOC_NOPM, 0, 0,
mtk_apll_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S(APLL2_W_NAME, SUPPLY_SEQ_APLL,
SND_SOC_NOPM, 0, 0,
mtk_apll_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
/* allow i2s on without codec on */
SND_SOC_DAPM_OUTPUT("I2S_DUMMY_OUT"),
SND_SOC_DAPM_MUX("I2S1_Out_Mux",
SND_SOC_NOPM, 0, 0, &i2s1_out_mux_control),
SND_SOC_DAPM_MUX("I2S3_Out_Mux",
SND_SOC_NOPM, 0, 0, &i2s3_out_mux_control),
SND_SOC_DAPM_MUX("I2S5_Out_Mux",
SND_SOC_NOPM, 0, 0, &i2s5_out_mux_control),
SND_SOC_DAPM_MUX("I2S7_Out_Mux",
SND_SOC_NOPM, 0, 0, &i2s7_out_mux_control),
SND_SOC_DAPM_MUX("I2S9_Out_Mux",
SND_SOC_NOPM, 0, 0, &i2s9_out_mux_control),
SND_SOC_DAPM_INPUT("I2S_DUMMY_IN"),
SND_SOC_DAPM_MUX("I2S0_In_Mux",
SND_SOC_NOPM, 0, 0, &i2s0_in_mux_control),
SND_SOC_DAPM_MUX("I2S8_In_Mux",
SND_SOC_NOPM, 0, 0, &i2s8_in_mux_control),
/* i2s in lpbk */
SND_SOC_DAPM_MUX("I2S0_Lpbk_Mux",
SND_SOC_NOPM, 0, 0, &i2s0_lpbk_mux_control),
SND_SOC_DAPM_MUX("I2S2_Lpbk_Mux",
SND_SOC_NOPM, 0, 0, &i2s2_lpbk_mux_control),
};
static int mtk_afe_i2s_share_connect(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_dapm_widget *w = sink;
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mtk_afe_i2s_priv *i2s_priv;
i2s_priv = get_i2s_priv_by_name(afe, sink->name);
if (!i2s_priv) {
dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__);
return 0;
}
if (i2s_priv->share_i2s_id < 0)
return 0;
return i2s_priv->share_i2s_id == get_i2s_id_by_name(afe, source->name);
}
static int mtk_afe_i2s_hd_connect(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_dapm_widget *w = sink;
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mtk_afe_i2s_priv *i2s_priv;
i2s_priv = get_i2s_priv_by_name(afe, sink->name);
if (!i2s_priv) {
dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__);
return 0;
}
if (get_i2s_id_by_name(afe, sink->name) ==
get_i2s_id_by_name(afe, source->name))
return i2s_priv->low_jitter_en;
/* check if share i2s need hd en */
if (i2s_priv->share_i2s_id < 0)
return 0;
if (i2s_priv->share_i2s_id == get_i2s_id_by_name(afe, source->name))
return i2s_priv->low_jitter_en;
return 0;
}
static int mtk_afe_i2s_apll_connect(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_dapm_widget *w = sink;
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mtk_afe_i2s_priv *i2s_priv;
int cur_apll;
int i2s_need_apll;
i2s_priv = get_i2s_priv_by_name(afe, w->name);
if (!i2s_priv) {
dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__);
return 0;
}
/* which apll */
cur_apll = mt8192_get_apll_by_name(afe, source->name);
/* choose APLL from i2s rate */
i2s_need_apll = mt8192_get_apll_by_rate(afe, i2s_priv->rate);
if (i2s_need_apll == cur_apll)
return 1;
return 0;
}
static int mtk_afe_i2s_mclk_connect(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_dapm_widget *w = sink;
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mtk_afe_i2s_priv *i2s_priv;
i2s_priv = get_i2s_priv_by_name(afe, sink->name);
if (!i2s_priv) {
dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__);
return 0;
}
if (get_i2s_id_by_name(afe, sink->name) ==
get_i2s_id_by_name(afe, source->name))
return (i2s_priv->mclk_rate > 0) ? 1 : 0;
/* check if share i2s need mclk */
if (i2s_priv->share_i2s_id < 0)
return 0;
if (i2s_priv->share_i2s_id == get_i2s_id_by_name(afe, source->name))
return (i2s_priv->mclk_rate > 0) ? 1 : 0;
return 0;
}
static int mtk_afe_mclk_apll_connect(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_dapm_widget *w = sink;
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mtk_afe_i2s_priv *i2s_priv;
int cur_apll;
i2s_priv = get_i2s_priv_by_name(afe, w->name);
if (!i2s_priv) {
dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__);
return 0;
}
/* which apll */
cur_apll = mt8192_get_apll_by_name(afe, source->name);
if (i2s_priv->mclk_apll == cur_apll)
return 1;
return 0;
}
static const struct snd_soc_dapm_route mtk_dai_i2s_routes[] = {
{"Connsys I2S", NULL, "CONNSYS"},
/* i2s0 */
{"I2S0", NULL, "I2S0_EN"},
{"I2S0", NULL, "I2S1_EN", mtk_afe_i2s_share_connect},
{"I2S0", NULL, "I2S2_EN", mtk_afe_i2s_share_connect},
{"I2S0", NULL, "I2S3_EN", mtk_afe_i2s_share_connect},
{"I2S0", NULL, "I2S5_EN", mtk_afe_i2s_share_connect},
{"I2S0", NULL, "I2S6_EN", mtk_afe_i2s_share_connect},
{"I2S0", NULL, "I2S7_EN", mtk_afe_i2s_share_connect},
{"I2S0", NULL, "I2S8_EN", mtk_afe_i2s_share_connect},
{"I2S0", NULL, "I2S9_EN", mtk_afe_i2s_share_connect},
{"I2S0", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S0", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S0", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S0", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S0", NULL, I2S5_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S0", NULL, I2S6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S0", NULL, I2S7_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S0", NULL, I2S8_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S0", NULL, I2S9_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{I2S0_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
{I2S0_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
{"I2S0", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S0", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S0", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S0", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S0", NULL, I2S5_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S0", NULL, I2S6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S0", NULL, I2S7_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S0", NULL, I2S8_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S0", NULL, I2S9_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{I2S0_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
{I2S0_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
/* i2s1 */
{"I2S1_CH1", "DL1_CH1", "DL1"},
{"I2S1_CH2", "DL1_CH2", "DL1"},
{"I2S1_TINYCONN_CH1_MUX", "DL1_CH1", "DL1"},
{"I2S1_TINYCONN_CH2_MUX", "DL1_CH2", "DL1"},
{"I2S1_CH1", "DL2_CH1", "DL2"},
{"I2S1_CH2", "DL2_CH2", "DL2"},
{"I2S1_TINYCONN_CH1_MUX", "DL2_CH1", "DL2"},
{"I2S1_TINYCONN_CH2_MUX", "DL2_CH2", "DL2"},
{"I2S1_CH1", "DL3_CH1", "DL3"},
{"I2S1_CH2", "DL3_CH2", "DL3"},
{"I2S1_TINYCONN_CH1_MUX", "DL3_CH1", "DL3"},
{"I2S1_TINYCONN_CH2_MUX", "DL3_CH2", "DL3"},
{"I2S1_CH1", "DL12_CH1", "DL12"},
{"I2S1_CH2", "DL12_CH2", "DL12"},
{"I2S1_TINYCONN_CH1_MUX", "DL12_CH1", "DL12"},
{"I2S1_TINYCONN_CH2_MUX", "DL12_CH2", "DL12"},
{"I2S1_CH1", "DL4_CH1", "DL4"},
{"I2S1_CH2", "DL4_CH2", "DL4"},
{"I2S1_CH1", "DL5_CH1", "DL5"},
{"I2S1_CH2", "DL5_CH2", "DL5"},
{"I2S1_CH1", "DL6_CH1", "DL6"},
{"I2S1_CH2", "DL6_CH2", "DL6"},
{"I2S1_CH1", "DL8_CH1", "DL8"},
{"I2S1_CH2", "DL8_CH2", "DL8"},
{"I2S1", NULL, "I2S1_CH1"},
{"I2S1", NULL, "I2S1_CH2"},
{"I2S1", NULL, "I2S3_TINYCONN_CH1_MUX"},
{"I2S1", NULL, "I2S3_TINYCONN_CH2_MUX"},
{"I2S1", NULL, "I2S0_EN", mtk_afe_i2s_share_connect},
{"I2S1", NULL, "I2S1_EN"},
{"I2S1", NULL, "I2S2_EN", mtk_afe_i2s_share_connect},
{"I2S1", NULL, "I2S3_EN", mtk_afe_i2s_share_connect},
{"I2S1", NULL, "I2S5_EN", mtk_afe_i2s_share_connect},
{"I2S1", NULL, "I2S6_EN", mtk_afe_i2s_share_connect},
{"I2S1", NULL, "I2S7_EN", mtk_afe_i2s_share_connect},
{"I2S1", NULL, "I2S8_EN", mtk_afe_i2s_share_connect},
{"I2S1", NULL, "I2S9_EN", mtk_afe_i2s_share_connect},
{"I2S1", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S1", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S1", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S1", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S1", NULL, I2S5_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S1", NULL, I2S6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S1", NULL, I2S7_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S1", NULL, I2S8_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S1", NULL, I2S9_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{I2S1_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
{I2S1_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
{"I2S1", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S1", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S1", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S1", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S1", NULL, I2S5_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S1", NULL, I2S6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S1", NULL, I2S7_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S1", NULL, I2S8_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S1", NULL, I2S9_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{I2S1_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
{I2S1_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
/* i2s2 */
{"I2S2", NULL, "I2S0_EN", mtk_afe_i2s_share_connect},
{"I2S2", NULL, "I2S1_EN", mtk_afe_i2s_share_connect},
{"I2S2", NULL, "I2S2_EN"},
{"I2S2", NULL, "I2S3_EN", mtk_afe_i2s_share_connect},
{"I2S2", NULL, "I2S5_EN", mtk_afe_i2s_share_connect},
{"I2S2", NULL, "I2S6_EN", mtk_afe_i2s_share_connect},
{"I2S2", NULL, "I2S7_EN", mtk_afe_i2s_share_connect},
{"I2S2", NULL, "I2S8_EN", mtk_afe_i2s_share_connect},
{"I2S2", NULL, "I2S9_EN", mtk_afe_i2s_share_connect},
{"I2S2", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S2", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S2", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S2", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S2", NULL, I2S5_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S2", NULL, I2S6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S2", NULL, I2S7_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S2", NULL, I2S8_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S2", NULL, I2S9_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{I2S2_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
{I2S2_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
{"I2S2", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S2", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S2", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S2", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S2", NULL, I2S5_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S2", NULL, I2S6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S2", NULL, I2S7_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S2", NULL, I2S8_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S2", NULL, I2S9_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{I2S2_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
{I2S2_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
/* i2s3 */
{"I2S3_CH1", "DL1_CH1", "DL1"},
{"I2S3_CH2", "DL1_CH2", "DL1"},
{"I2S3_TINYCONN_CH1_MUX", "DL1_CH1", "DL1"},
{"I2S3_TINYCONN_CH2_MUX", "DL1_CH2", "DL1"},
{"I2S3_CH1", "DL2_CH1", "DL2"},
{"I2S3_CH2", "DL2_CH2", "DL2"},
{"I2S3_TINYCONN_CH1_MUX", "DL2_CH1", "DL2"},
{"I2S3_TINYCONN_CH2_MUX", "DL2_CH2", "DL2"},
{"I2S3_CH1", "DL3_CH1", "DL3"},
{"I2S3_CH2", "DL3_CH2", "DL3"},
{"I2S3_TINYCONN_CH1_MUX", "DL3_CH1", "DL3"},
{"I2S3_TINYCONN_CH2_MUX", "DL3_CH2", "DL3"},
{"I2S3_CH1", "DL12_CH1", "DL12"},
{"I2S3_CH2", "DL12_CH2", "DL12"},
{"I2S3_TINYCONN_CH1_MUX", "DL12_CH1", "DL12"},
{"I2S3_TINYCONN_CH2_MUX", "DL12_CH2", "DL12"},
{"I2S3_CH1", "DL4_CH1", "DL4"},
{"I2S3_CH2", "DL4_CH2", "DL4"},
{"I2S3_CH1", "DL5_CH1", "DL5"},
{"I2S3_CH2", "DL5_CH2", "DL5"},
{"I2S3_CH1", "DL6_CH1", "DL6"},
{"I2S3_CH2", "DL6_CH2", "DL6"},
{"I2S3_CH1", "DL8_CH1", "DL8"},
{"I2S3_CH2", "DL8_CH2", "DL8"},
{"I2S3", NULL, "I2S3_CH1"},
{"I2S3", NULL, "I2S3_CH2"},
{"I2S3", NULL, "I2S3_TINYCONN_CH1_MUX"},
{"I2S3", NULL, "I2S3_TINYCONN_CH2_MUX"},
{"I2S3", NULL, "I2S0_EN", mtk_afe_i2s_share_connect},
{"I2S3", NULL, "I2S1_EN", mtk_afe_i2s_share_connect},
{"I2S3", NULL, "I2S2_EN", mtk_afe_i2s_share_connect},
{"I2S3", NULL, "I2S3_EN"},
{"I2S3", NULL, "I2S5_EN", mtk_afe_i2s_share_connect},
{"I2S3", NULL, "I2S6_EN", mtk_afe_i2s_share_connect},
{"I2S3", NULL, "I2S7_EN", mtk_afe_i2s_share_connect},
{"I2S3", NULL, "I2S8_EN", mtk_afe_i2s_share_connect},
{"I2S3", NULL, "I2S9_EN", mtk_afe_i2s_share_connect},
{"I2S3", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S3", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S3", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S3", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S3", NULL, I2S5_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S3", NULL, I2S6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S3", NULL, I2S7_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S3", NULL, I2S8_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S3", NULL, I2S9_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{I2S3_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
{I2S3_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
{"I2S3", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S3", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S3", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S3", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S3", NULL, I2S5_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S3", NULL, I2S6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S3", NULL, I2S7_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S3", NULL, I2S8_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S3", NULL, I2S9_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{I2S3_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
{I2S3_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
/* i2s5 */
{"I2S5_CH1", "DL1_CH1", "DL1"},
{"I2S5_CH2", "DL1_CH2", "DL1"},
{"I2S5_CH1", "DL2_CH1", "DL2"},
{"I2S5_CH2", "DL2_CH2", "DL2"},
{"I2S5_CH1", "DL3_CH1", "DL3"},
{"I2S5_CH2", "DL3_CH2", "DL3"},
{"I2S5_CH1", "DL12_CH1", "DL12"},
{"I2S5_CH2", "DL12_CH2", "DL12"},
{"I2S5_CH1", "DL4_CH1", "DL4"},
{"I2S5_CH2", "DL4_CH2", "DL4"},
{"I2S5_CH1", "DL5_CH1", "DL5"},
{"I2S5_CH2", "DL5_CH2", "DL5"},
{"I2S5_CH1", "DL6_CH1", "DL6"},
{"I2S5_CH2", "DL6_CH2", "DL6"},
{"I2S5_CH1", "DL8_CH1", "DL8"},
{"I2S5_CH2", "DL8_CH2", "DL8"},
{"I2S5", NULL, "I2S5_CH1"},
{"I2S5", NULL, "I2S5_CH2"},
{"I2S5", NULL, "I2S0_EN", mtk_afe_i2s_share_connect},
{"I2S5", NULL, "I2S1_EN", mtk_afe_i2s_share_connect},
{"I2S5", NULL, "I2S2_EN", mtk_afe_i2s_share_connect},
{"I2S5", NULL, "I2S3_EN", mtk_afe_i2s_share_connect},
{"I2S5", NULL, "I2S5_EN"},
{"I2S5", NULL, "I2S6_EN", mtk_afe_i2s_share_connect},
{"I2S5", NULL, "I2S7_EN", mtk_afe_i2s_share_connect},
{"I2S5", NULL, "I2S8_EN", mtk_afe_i2s_share_connect},
{"I2S5", NULL, "I2S9_EN", mtk_afe_i2s_share_connect},
{"I2S5", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S5", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S5", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S5", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S5", NULL, I2S5_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S5", NULL, I2S6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S5", NULL, I2S7_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S5", NULL, I2S8_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S5", NULL, I2S9_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{I2S5_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
{I2S5_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
{"I2S5", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S5", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S5", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S5", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S5", NULL, I2S5_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S5", NULL, I2S6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S5", NULL, I2S7_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S5", NULL, I2S8_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S5", NULL, I2S9_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{I2S5_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
{I2S5_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
/* i2s6 */
{"I2S6", NULL, "I2S0_EN", mtk_afe_i2s_share_connect},
{"I2S6", NULL, "I2S1_EN", mtk_afe_i2s_share_connect},
{"I2S6", NULL, "I2S2_EN", mtk_afe_i2s_share_connect},
{"I2S6", NULL, "I2S3_EN", mtk_afe_i2s_share_connect},
{"I2S6", NULL, "I2S5_EN", mtk_afe_i2s_share_connect},
{"I2S6", NULL, "I2S6_EN"},
{"I2S6", NULL, "I2S7_EN", mtk_afe_i2s_share_connect},
{"I2S6", NULL, "I2S8_EN", mtk_afe_i2s_share_connect},
{"I2S6", NULL, "I2S9_EN", mtk_afe_i2s_share_connect},
{"I2S6", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S6", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S6", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S6", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S6", NULL, I2S5_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S6", NULL, I2S6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S6", NULL, I2S7_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S6", NULL, I2S8_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S6", NULL, I2S9_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{I2S6_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
{I2S6_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
{"I2S6", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S6", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S6", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S6", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S6", NULL, I2S5_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S6", NULL, I2S6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S6", NULL, I2S7_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S6", NULL, I2S8_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S6", NULL, I2S9_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{I2S6_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
{I2S6_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
/* i2s7 */
{"I2S7", NULL, "I2S7_CH1"},
{"I2S7", NULL, "I2S7_CH2"},
{"I2S7", NULL, "I2S0_EN", mtk_afe_i2s_share_connect},
{"I2S7", NULL, "I2S1_EN", mtk_afe_i2s_share_connect},
{"I2S7", NULL, "I2S2_EN", mtk_afe_i2s_share_connect},
{"I2S7", NULL, "I2S3_EN", mtk_afe_i2s_share_connect},
{"I2S7", NULL, "I2S5_EN", mtk_afe_i2s_share_connect},
{"I2S7", NULL, "I2S6_EN", mtk_afe_i2s_share_connect},
{"I2S7", NULL, "I2S7_EN"},
{"I2S7", NULL, "I2S8_EN", mtk_afe_i2s_share_connect},
{"I2S7", NULL, "I2S9_EN", mtk_afe_i2s_share_connect},
{"I2S7", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S7", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S7", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S7", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S7", NULL, I2S5_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S7", NULL, I2S6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S7", NULL, I2S7_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S7", NULL, I2S8_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S7", NULL, I2S9_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{I2S7_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
{I2S7_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
{"I2S7", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S7", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S7", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S7", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S7", NULL, I2S5_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S7", NULL, I2S6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S7", NULL, I2S7_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S7", NULL, I2S8_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S7", NULL, I2S9_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{I2S7_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
{I2S7_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
/* i2s8 */
{"I2S8", NULL, "I2S0_EN", mtk_afe_i2s_share_connect},
{"I2S8", NULL, "I2S1_EN", mtk_afe_i2s_share_connect},
{"I2S8", NULL, "I2S2_EN", mtk_afe_i2s_share_connect},
{"I2S8", NULL, "I2S3_EN", mtk_afe_i2s_share_connect},
{"I2S8", NULL, "I2S5_EN", mtk_afe_i2s_share_connect},
{"I2S8", NULL, "I2S6_EN", mtk_afe_i2s_share_connect},
{"I2S8", NULL, "I2S7_EN", mtk_afe_i2s_share_connect},
{"I2S8", NULL, "I2S8_EN"},
{"I2S8", NULL, "I2S9_EN", mtk_afe_i2s_share_connect},
{"I2S8", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S8", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S8", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S8", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S8", NULL, I2S5_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S8", NULL, I2S6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S8", NULL, I2S7_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S8", NULL, I2S8_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S8", NULL, I2S9_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{I2S8_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
{I2S8_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
{"I2S8", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S8", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S8", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S8", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S8", NULL, I2S5_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S8", NULL, I2S6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S8", NULL, I2S7_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S8", NULL, I2S8_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S8", NULL, I2S9_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{I2S8_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
{I2S8_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
/* i2s9 */
{"I2S9_CH1", "DL1_CH1", "DL1"},
{"I2S9_CH2", "DL1_CH2", "DL1"},
{"I2S9_CH1", "DL2_CH1", "DL2"},
{"I2S9_CH2", "DL2_CH2", "DL2"},
{"I2S9_CH1", "DL3_CH1", "DL3"},
{"I2S9_CH2", "DL3_CH2", "DL3"},
{"I2S9_CH1", "DL12_CH1", "DL12"},
{"I2S9_CH2", "DL12_CH2", "DL12"},
{"I2S9_CH1", "DL4_CH1", "DL4"},
{"I2S9_CH2", "DL4_CH2", "DL4"},
{"I2S9_CH1", "DL5_CH1", "DL5"},
{"I2S9_CH2", "DL5_CH2", "DL5"},
{"I2S9_CH1", "DL6_CH1", "DL6"},
{"I2S9_CH2", "DL6_CH2", "DL6"},
{"I2S9_CH1", "DL8_CH1", "DL8"},
{"I2S9_CH2", "DL8_CH2", "DL8"},
{"I2S9_CH1", "DL9_CH1", "DL9"},
{"I2S9_CH2", "DL9_CH2", "DL9"},
{"I2S9", NULL, "I2S9_CH1"},
{"I2S9", NULL, "I2S9_CH2"},
{"I2S9", NULL, "I2S0_EN", mtk_afe_i2s_share_connect},
{"I2S9", NULL, "I2S1_EN", mtk_afe_i2s_share_connect},
{"I2S9", NULL, "I2S2_EN", mtk_afe_i2s_share_connect},
{"I2S9", NULL, "I2S3_EN", mtk_afe_i2s_share_connect},
{"I2S9", NULL, "I2S5_EN", mtk_afe_i2s_share_connect},
{"I2S9", NULL, "I2S6_EN", mtk_afe_i2s_share_connect},
{"I2S9", NULL, "I2S7_EN", mtk_afe_i2s_share_connect},
{"I2S9", NULL, "I2S8_EN", mtk_afe_i2s_share_connect},
{"I2S9", NULL, "I2S9_EN"},
{"I2S9", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S9", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S9", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S9", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S9", NULL, I2S5_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S9", NULL, I2S6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S9", NULL, I2S7_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S9", NULL, I2S8_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S9", NULL, I2S9_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{I2S9_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
{I2S9_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
{"I2S9", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S9", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S9", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S9", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S9", NULL, I2S5_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S9", NULL, I2S6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S9", NULL, I2S7_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S9", NULL, I2S8_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S9", NULL, I2S9_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{I2S9_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
{I2S9_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
/* allow i2s on without codec on */
{"I2S0", NULL, "I2S0_In_Mux"},
{"I2S0_In_Mux", "Dummy_Widget", "I2S_DUMMY_IN"},
{"I2S8", NULL, "I2S8_In_Mux"},
{"I2S8_In_Mux", "Dummy_Widget", "I2S_DUMMY_IN"},
{"I2S1_Out_Mux", "Dummy_Widget", "I2S1"},
{"I2S_DUMMY_OUT", NULL, "I2S1_Out_Mux"},
{"I2S3_Out_Mux", "Dummy_Widget", "I2S3"},
{"I2S_DUMMY_OUT", NULL, "I2S3_Out_Mux"},
{"I2S5_Out_Mux", "Dummy_Widget", "I2S5"},
{"I2S_DUMMY_OUT", NULL, "I2S5_Out_Mux"},
{"I2S7_Out_Mux", "Dummy_Widget", "I2S7"},
{"I2S_DUMMY_OUT", NULL, "I2S7_Out_Mux"},
{"I2S9_Out_Mux", "Dummy_Widget", "I2S9"},
{"I2S_DUMMY_OUT", NULL, "I2S9_Out_Mux"},
/* i2s in lpbk */
{"I2S0_Lpbk_Mux", "Lpbk", "I2S3"},
{"I2S2_Lpbk_Mux", "Lpbk", "I2S1"},
{"I2S0", NULL, "I2S0_Lpbk_Mux"},
{"I2S2", NULL, "I2S2_Lpbk_Mux"},
};
/* dai ops */
static int mtk_dai_connsys_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
unsigned int rate = params_rate(params);
unsigned int rate_reg = mt8192_rate_transform(afe->dev,
rate, dai->id);
unsigned int i2s_con = 0;
dev_dbg(afe->dev, "%s(), id %d, stream %d, rate %d\n",
__func__, dai->id, substream->stream, rate);
/* non-inverse, i2s mode, proxy mode, 16bits, from connsys */
i2s_con |= 0 << INV_PAD_CTRL_SFT;
i2s_con |= I2S_FMT_I2S << I2S_FMT_SFT;
i2s_con |= 1 << I2S_SRC_SFT;
i2s_con |= get_i2s_wlen(SNDRV_PCM_FORMAT_S16_LE) << I2S_WLEN_SFT;
i2s_con |= 0 << I2SIN_PAD_SEL_SFT;
regmap_write(afe->regmap, AFE_CONNSYS_I2S_CON, i2s_con);
/* use asrc */
regmap_update_bits(afe->regmap,
AFE_CONNSYS_I2S_CON,
I2S_BYPSRC_MASK_SFT,
0x0 << I2S_BYPSRC_SFT);
/* proxy mode, set i2s for asrc */
regmap_update_bits(afe->regmap,
AFE_CONNSYS_I2S_CON,
I2S_MODE_MASK_SFT,
rate_reg << I2S_MODE_SFT);
switch (rate) {
case 32000:
regmap_write(afe->regmap, AFE_ASRC_2CH_CON3, 0x140000);
break;
case 44100:
regmap_write(afe->regmap, AFE_ASRC_2CH_CON3, 0x001B9000);
break;
default:
regmap_write(afe->regmap, AFE_ASRC_2CH_CON3, 0x001E0000);
break;
}
/* Calibration setting */
regmap_write(afe->regmap, AFE_ASRC_2CH_CON4, 0x00140000);
regmap_write(afe->regmap, AFE_ASRC_2CH_CON9, 0x00036000);
regmap_write(afe->regmap, AFE_ASRC_2CH_CON10, 0x0002FC00);
regmap_write(afe->regmap, AFE_ASRC_2CH_CON6, 0x00007EF4);
regmap_write(afe->regmap, AFE_ASRC_2CH_CON5, 0x00FF5986);
/* 0:Stereo 1:Mono */
regmap_update_bits(afe->regmap,
AFE_ASRC_2CH_CON2,
CHSET_IS_MONO_MASK_SFT,
0x0 << CHSET_IS_MONO_SFT);
return 0;
}
static int mtk_dai_connsys_i2s_trigger(struct snd_pcm_substream *substream,
int cmd, struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8192_afe_private *afe_priv = afe->platform_priv;
dev_dbg(afe->dev, "%s(), cmd %d, stream %d\n",
__func__, cmd, substream->stream);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
/* i2s enable */
regmap_update_bits(afe->regmap,
AFE_CONNSYS_I2S_CON,
I2S_EN_MASK_SFT,
0x1 << I2S_EN_SFT);
/* calibrator enable */
regmap_update_bits(afe->regmap,
AFE_ASRC_2CH_CON5,
CALI_EN_MASK_SFT,
0x1 << CALI_EN_SFT);
/* asrc enable */
regmap_update_bits(afe->regmap,
AFE_ASRC_2CH_CON0,
CON0_CHSET_STR_CLR_MASK_SFT,
0x1 << CON0_CHSET_STR_CLR_SFT);
regmap_update_bits(afe->regmap,
AFE_ASRC_2CH_CON0,
CON0_ASM_ON_MASK_SFT,
0x1 << CON0_ASM_ON_SFT);
afe_priv->dai_on[dai->id] = true;
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
regmap_update_bits(afe->regmap,
AFE_ASRC_2CH_CON0,
CON0_ASM_ON_MASK_SFT,
0 << CON0_ASM_ON_SFT);
regmap_update_bits(afe->regmap,
AFE_ASRC_2CH_CON5,
CALI_EN_MASK_SFT,
0 << CALI_EN_SFT);
/* i2s disable */
regmap_update_bits(afe->regmap,
AFE_CONNSYS_I2S_CON,
I2S_EN_MASK_SFT,
0x0 << I2S_EN_SFT);
/* bypass asrc */
regmap_update_bits(afe->regmap,
AFE_CONNSYS_I2S_CON,
I2S_BYPSRC_MASK_SFT,
0x1 << I2S_BYPSRC_SFT);
afe_priv->dai_on[dai->id] = false;
break;
default:
return -EINVAL;
}
return 0;
}
static const struct snd_soc_dai_ops mtk_dai_connsys_i2s_ops = {
.hw_params = mtk_dai_connsys_i2s_hw_params,
.trigger = mtk_dai_connsys_i2s_trigger,
};
/* i2s */
static int mtk_dai_i2s_config(struct mtk_base_afe *afe,
struct snd_pcm_hw_params *params,
int i2s_id)
{
struct mt8192_afe_private *afe_priv = afe->platform_priv;
struct mtk_afe_i2s_priv *i2s_priv = afe_priv->dai_priv[i2s_id];
unsigned int rate = params_rate(params);
unsigned int rate_reg = mt8192_rate_transform(afe->dev,
rate, i2s_id);
snd_pcm_format_t format = params_format(params);
unsigned int i2s_con = 0;
int ret = 0;
dev_dbg(afe->dev, "%s(), id %d, rate %d, format %d\n",
__func__, i2s_id, rate, format);
if (i2s_priv)
i2s_priv->rate = rate;
else
dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__);
switch (i2s_id) {
case MT8192_DAI_I2S_0:
i2s_con = I2S_IN_PAD_IO_MUX << I2SIN_PAD_SEL_SFT;
i2s_con |= rate_reg << I2S_OUT_MODE_SFT;
i2s_con |= I2S_FMT_I2S << I2S_FMT_SFT;
i2s_con |= get_i2s_wlen(format) << I2S_WLEN_SFT;
regmap_update_bits(afe->regmap, AFE_I2S_CON,
0xffffeffe, i2s_con);
break;
case MT8192_DAI_I2S_1:
i2s_con = I2S1_SEL_O28_O29 << I2S2_SEL_O03_O04_SFT;
i2s_con |= rate_reg << I2S2_OUT_MODE_SFT;
i2s_con |= I2S_FMT_I2S << I2S2_FMT_SFT;
i2s_con |= get_i2s_wlen(format) << I2S2_WLEN_SFT;
regmap_update_bits(afe->regmap, AFE_I2S_CON1,
0xffffeffe, i2s_con);
break;
case MT8192_DAI_I2S_2:
i2s_con = 8 << I2S3_UPDATE_WORD_SFT;
i2s_con |= rate_reg << I2S3_OUT_MODE_SFT;
i2s_con |= I2S_FMT_I2S << I2S3_FMT_SFT;
i2s_con |= get_i2s_wlen(format) << I2S3_WLEN_SFT;
regmap_update_bits(afe->regmap, AFE_I2S_CON2,
0xffffeffe, i2s_con);
break;
case MT8192_DAI_I2S_3:
i2s_con = rate_reg << I2S4_OUT_MODE_SFT;
i2s_con |= I2S_FMT_I2S << I2S4_FMT_SFT;
i2s_con |= get_i2s_wlen(format) << I2S4_WLEN_SFT;
regmap_update_bits(afe->regmap, AFE_I2S_CON3,
0xffffeffe, i2s_con);
break;
case MT8192_DAI_I2S_5:
i2s_con = rate_reg << I2S5_OUT_MODE_SFT;
i2s_con |= I2S_FMT_I2S << I2S5_FMT_SFT;
i2s_con |= get_i2s_wlen(format) << I2S5_WLEN_SFT;
regmap_update_bits(afe->regmap, AFE_I2S_CON4,
0xffffeffe, i2s_con);
break;
case MT8192_DAI_I2S_6:
i2s_con = rate_reg << I2S6_OUT_MODE_SFT;
i2s_con |= I2S_FMT_I2S << I2S6_FMT_SFT;
i2s_con |= get_i2s_wlen(format) << I2S6_WLEN_SFT;
regmap_update_bits(afe->regmap, AFE_I2S_CON6,
0xffffeffe, i2s_con);
break;
case MT8192_DAI_I2S_7:
i2s_con = rate_reg << I2S7_OUT_MODE_SFT;
i2s_con |= I2S_FMT_I2S << I2S7_FMT_SFT;
i2s_con |= get_i2s_wlen(format) << I2S7_WLEN_SFT;
regmap_update_bits(afe->regmap, AFE_I2S_CON7,
0xffffeffe, i2s_con);
break;
case MT8192_DAI_I2S_8:
i2s_con = rate_reg << I2S8_OUT_MODE_SFT;
i2s_con |= I2S_FMT_I2S << I2S8_FMT_SFT;
i2s_con |= get_i2s_wlen(format) << I2S8_WLEN_SFT;
regmap_update_bits(afe->regmap, AFE_I2S_CON8,
0xffffeffe, i2s_con);
break;
case MT8192_DAI_I2S_9:
i2s_con = rate_reg << I2S9_OUT_MODE_SFT;
i2s_con |= I2S_FMT_I2S << I2S9_FMT_SFT;
i2s_con |= get_i2s_wlen(format) << I2S9_WLEN_SFT;
regmap_update_bits(afe->regmap, AFE_I2S_CON9,
0xffffeffe, i2s_con);
break;
default:
dev_warn(afe->dev, "%s(), id %d not support\n",
__func__, i2s_id);
return -EINVAL;
}
/* set share i2s */
if (i2s_priv && i2s_priv->share_i2s_id >= 0)
ret = mtk_dai_i2s_config(afe, params, i2s_priv->share_i2s_id);
return ret;
}
static int mtk_dai_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
return mtk_dai_i2s_config(afe, params, dai->id);
}
static int mtk_dai_i2s_set_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct mtk_base_afe *afe = dev_get_drvdata(dai->dev);
struct mt8192_afe_private *afe_priv = afe->platform_priv;
struct mtk_afe_i2s_priv *i2s_priv = afe_priv->dai_priv[dai->id];
int apll;
int apll_rate;
if (!i2s_priv) {
dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__);
return -EINVAL;
}
if (dir != SND_SOC_CLOCK_OUT) {
dev_warn(afe->dev, "%s(), dir != SND_SOC_CLOCK_OUT", __func__);
return -EINVAL;
}
dev_dbg(afe->dev, "%s(), freq %d\n", __func__, freq);
apll = mt8192_get_apll_by_rate(afe, freq);
apll_rate = mt8192_get_apll_rate(afe, apll);
if (freq > apll_rate) {
dev_warn(afe->dev, "%s(), freq > apll rate", __func__);
return -EINVAL;
}
if (apll_rate % freq != 0) {
dev_warn(afe->dev, "%s(), APLL can't gen freq Hz", __func__);
return -EINVAL;
}
i2s_priv->mclk_rate = freq;
i2s_priv->mclk_apll = apll;
if (i2s_priv->share_i2s_id > 0) {
struct mtk_afe_i2s_priv *share_i2s_priv;
share_i2s_priv = afe_priv->dai_priv[i2s_priv->share_i2s_id];
if (!share_i2s_priv) {
dev_warn(afe->dev, "%s(), share_i2s_priv = NULL",
__func__);
return -EINVAL;
}
share_i2s_priv->mclk_rate = i2s_priv->mclk_rate;
share_i2s_priv->mclk_apll = i2s_priv->mclk_apll;
}
return 0;
}
static const struct snd_soc_dai_ops mtk_dai_i2s_ops = {
.hw_params = mtk_dai_i2s_hw_params,
.set_sysclk = mtk_dai_i2s_set_sysclk,
};
/* dai driver */
#define MTK_CONNSYS_I2S_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
#define MTK_I2S_RATES (SNDRV_PCM_RATE_8000_48000 |\
SNDRV_PCM_RATE_88200 |\
SNDRV_PCM_RATE_96000 |\
SNDRV_PCM_RATE_176400 |\
SNDRV_PCM_RATE_192000)
#define MTK_I2S_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver mtk_dai_i2s_driver[] = {
{
.name = "CONNSYS_I2S",
.id = MT8192_DAI_CONNSYS_I2S,
.capture = {
.stream_name = "Connsys I2S",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_CONNSYS_I2S_RATES,
.formats = MTK_I2S_FORMATS,
},
.ops = &mtk_dai_connsys_i2s_ops,
},
{
.name = "I2S0",
.id = MT8192_DAI_I2S_0,
.capture = {
.stream_name = "I2S0",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_I2S_RATES,
.formats = MTK_I2S_FORMATS,
},
.ops = &mtk_dai_i2s_ops,
},
{
.name = "I2S1",
.id = MT8192_DAI_I2S_1,
.playback = {
.stream_name = "I2S1",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_I2S_RATES,
.formats = MTK_I2S_FORMATS,
},
.ops = &mtk_dai_i2s_ops,
},
{
.name = "I2S2",
.id = MT8192_DAI_I2S_2,
.capture = {
.stream_name = "I2S2",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_I2S_RATES,
.formats = MTK_I2S_FORMATS,
},
.ops = &mtk_dai_i2s_ops,
},
{
.name = "I2S3",
.id = MT8192_DAI_I2S_3,
.playback = {
.stream_name = "I2S3",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_I2S_RATES,
.formats = MTK_I2S_FORMATS,
},
.ops = &mtk_dai_i2s_ops,
},
{
.name = "I2S5",
.id = MT8192_DAI_I2S_5,
.playback = {
.stream_name = "I2S5",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_I2S_RATES,
.formats = MTK_I2S_FORMATS,
},
.ops = &mtk_dai_i2s_ops,
},
{
.name = "I2S6",
.id = MT8192_DAI_I2S_6,
.capture = {
.stream_name = "I2S6",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_I2S_RATES,
.formats = MTK_I2S_FORMATS,
},
.ops = &mtk_dai_i2s_ops,
},
{
.name = "I2S7",
.id = MT8192_DAI_I2S_7,
.playback = {
.stream_name = "I2S7",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_I2S_RATES,
.formats = MTK_I2S_FORMATS,
},
.ops = &mtk_dai_i2s_ops,
},
{
.name = "I2S8",
.id = MT8192_DAI_I2S_8,
.capture = {
.stream_name = "I2S8",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_I2S_RATES,
.formats = MTK_I2S_FORMATS,
},
.ops = &mtk_dai_i2s_ops,
},
{
.name = "I2S9",
.id = MT8192_DAI_I2S_9,
.playback = {
.stream_name = "I2S9",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_I2S_RATES,
.formats = MTK_I2S_FORMATS,
},
.ops = &mtk_dai_i2s_ops,
}
};
/* this enum is merely for mtk_afe_i2s_priv declare */
enum {
DAI_I2S0 = 0,
DAI_I2S1,
DAI_I2S2,
DAI_I2S3,
DAI_I2S5,
DAI_I2S6,
DAI_I2S7,
DAI_I2S8,
DAI_I2S9,
DAI_I2S_NUM,
};
static const struct mtk_afe_i2s_priv mt8192_i2s_priv[DAI_I2S_NUM] = {
[DAI_I2S0] = {
.id = MT8192_DAI_I2S_0,
.mclk_id = MT8192_I2S0_MCK,
.share_i2s_id = -1,
},
[DAI_I2S1] = {
.id = MT8192_DAI_I2S_1,
.mclk_id = MT8192_I2S1_MCK,
.share_i2s_id = -1,
},
[DAI_I2S2] = {
.id = MT8192_DAI_I2S_2,
.mclk_id = MT8192_I2S2_MCK,
.share_i2s_id = -1,
},
[DAI_I2S3] = {
.id = MT8192_DAI_I2S_3,
.mclk_id = MT8192_I2S3_MCK,
.share_i2s_id = -1,
},
[DAI_I2S5] = {
.id = MT8192_DAI_I2S_5,
.mclk_id = MT8192_I2S5_MCK,
.share_i2s_id = -1,
},
[DAI_I2S6] = {
.id = MT8192_DAI_I2S_6,
.mclk_id = MT8192_I2S6_MCK,
.share_i2s_id = -1,
},
[DAI_I2S7] = {
.id = MT8192_DAI_I2S_7,
.mclk_id = MT8192_I2S7_MCK,
.share_i2s_id = -1,
},
[DAI_I2S8] = {
.id = MT8192_DAI_I2S_8,
.mclk_id = MT8192_I2S8_MCK,
.share_i2s_id = -1,
},
[DAI_I2S9] = {
.id = MT8192_DAI_I2S_9,
.mclk_id = MT8192_I2S9_MCK,
.share_i2s_id = -1,
},
};
/**
* mt8192_dai_i2s_set_share() - Set up I2S ports to share a single clock.
* @afe: Pointer to &struct mtk_base_afe
* @main_i2s_name: The name of the I2S port that will provide the clock
* @secondary_i2s_name: The name of the I2S port that will use this clock
*/
int mt8192_dai_i2s_set_share(struct mtk_base_afe *afe, const char *main_i2s_name,
const char *secondary_i2s_name)
{
struct mtk_afe_i2s_priv *secondary_i2s_priv;
int main_i2s_id;
secondary_i2s_priv = get_i2s_priv_by_name(afe, secondary_i2s_name);
if (!secondary_i2s_priv)
return -EINVAL;
main_i2s_id = get_i2s_id_by_name(afe, main_i2s_name);
if (main_i2s_id < 0)
return main_i2s_id;
secondary_i2s_priv->share_i2s_id = main_i2s_id;
return 0;
}
EXPORT_SYMBOL_GPL(mt8192_dai_i2s_set_share);
static int mt8192_dai_i2s_set_priv(struct mtk_base_afe *afe)
{
int i;
int ret;
for (i = 0; i < DAI_I2S_NUM; i++) {
ret = mt8192_dai_set_priv(afe, mt8192_i2s_priv[i].id,
sizeof(struct mtk_afe_i2s_priv),
&mt8192_i2s_priv[i]);
if (ret)
return ret;
}
return 0;
}
int mt8192_dai_i2s_register(struct mtk_base_afe *afe)
{
struct mtk_base_afe_dai *dai;
int ret;
dev_dbg(afe->dev, "%s()\n", __func__);
dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
if (!dai)
return -ENOMEM;
list_add(&dai->list, &afe->sub_dais);
dai->dai_drivers = mtk_dai_i2s_driver;
dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_i2s_driver);
dai->controls = mtk_dai_i2s_controls;
dai->num_controls = ARRAY_SIZE(mtk_dai_i2s_controls);
dai->dapm_widgets = mtk_dai_i2s_widgets;
dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_i2s_widgets);
dai->dapm_routes = mtk_dai_i2s_routes;
dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_i2s_routes);
/* set all dai i2s private data */
ret = mt8192_dai_i2s_set_priv(afe);
if (ret)
return ret;
return 0;
}
| linux-master | sound/soc/mediatek/mt8192/mt8192-dai-i2s.c |
// SPDX-License-Identifier: GPL-2.0
/*
* mt8195-afe-clk.c -- Mediatek 8195 afe clock ctrl
*
* Copyright (c) 2021 MediaTek Inc.
* Author: Bicycle Tsai <[email protected]>
* Trevor Wu <[email protected]>
*/
#include <linux/clk.h>
#include "mt8195-afe-common.h"
#include "mt8195-afe-clk.h"
#include "mt8195-reg.h"
#include "mt8195-audsys-clk.h"
static const char *aud_clks[MT8195_CLK_NUM] = {
/* xtal */
[MT8195_CLK_XTAL_26M] = "clk26m",
/* divider */
[MT8195_CLK_TOP_APLL1] = "apll1_ck",
[MT8195_CLK_TOP_APLL2] = "apll2_ck",
[MT8195_CLK_TOP_APLL12_DIV0] = "apll12_div0",
[MT8195_CLK_TOP_APLL12_DIV1] = "apll12_div1",
[MT8195_CLK_TOP_APLL12_DIV2] = "apll12_div2",
[MT8195_CLK_TOP_APLL12_DIV3] = "apll12_div3",
[MT8195_CLK_TOP_APLL12_DIV9] = "apll12_div9",
/* mux */
[MT8195_CLK_TOP_A1SYS_HP_SEL] = "a1sys_hp_sel",
[MT8195_CLK_TOP_AUD_INTBUS_SEL] = "aud_intbus_sel",
[MT8195_CLK_TOP_AUDIO_H_SEL] = "audio_h_sel",
[MT8195_CLK_TOP_AUDIO_LOCAL_BUS_SEL] = "audio_local_bus_sel",
[MT8195_CLK_TOP_DPTX_M_SEL] = "dptx_m_sel",
[MT8195_CLK_TOP_I2SO1_M_SEL] = "i2so1_m_sel",
[MT8195_CLK_TOP_I2SO2_M_SEL] = "i2so2_m_sel",
[MT8195_CLK_TOP_I2SI1_M_SEL] = "i2si1_m_sel",
[MT8195_CLK_TOP_I2SI2_M_SEL] = "i2si2_m_sel",
/* clock gate */
[MT8195_CLK_INFRA_AO_AUDIO_26M_B] = "infra_ao_audio_26m_b",
[MT8195_CLK_SCP_ADSP_AUDIODSP] = "scp_adsp_audiodsp",
/* afe clock gate */
[MT8195_CLK_AUD_AFE] = "aud_afe",
[MT8195_CLK_AUD_APLL1_TUNER] = "aud_apll1_tuner",
[MT8195_CLK_AUD_APLL2_TUNER] = "aud_apll2_tuner",
[MT8195_CLK_AUD_APLL] = "aud_apll",
[MT8195_CLK_AUD_APLL2] = "aud_apll2",
[MT8195_CLK_AUD_DAC] = "aud_dac",
[MT8195_CLK_AUD_ADC] = "aud_adc",
[MT8195_CLK_AUD_DAC_HIRES] = "aud_dac_hires",
[MT8195_CLK_AUD_A1SYS_HP] = "aud_a1sys_hp",
[MT8195_CLK_AUD_ADC_HIRES] = "aud_adc_hires",
[MT8195_CLK_AUD_ADDA6_ADC] = "aud_adda6_adc",
[MT8195_CLK_AUD_ADDA6_ADC_HIRES] = "aud_adda6_adc_hires",
[MT8195_CLK_AUD_I2SIN] = "aud_i2sin",
[MT8195_CLK_AUD_TDM_IN] = "aud_tdm_in",
[MT8195_CLK_AUD_I2S_OUT] = "aud_i2s_out",
[MT8195_CLK_AUD_TDM_OUT] = "aud_tdm_out",
[MT8195_CLK_AUD_HDMI_OUT] = "aud_hdmi_out",
[MT8195_CLK_AUD_ASRC11] = "aud_asrc11",
[MT8195_CLK_AUD_ASRC12] = "aud_asrc12",
[MT8195_CLK_AUD_A1SYS] = "aud_a1sys",
[MT8195_CLK_AUD_A2SYS] = "aud_a2sys",
[MT8195_CLK_AUD_PCMIF] = "aud_pcmif",
[MT8195_CLK_AUD_MEMIF_UL1] = "aud_memif_ul1",
[MT8195_CLK_AUD_MEMIF_UL2] = "aud_memif_ul2",
[MT8195_CLK_AUD_MEMIF_UL3] = "aud_memif_ul3",
[MT8195_CLK_AUD_MEMIF_UL4] = "aud_memif_ul4",
[MT8195_CLK_AUD_MEMIF_UL5] = "aud_memif_ul5",
[MT8195_CLK_AUD_MEMIF_UL6] = "aud_memif_ul6",
[MT8195_CLK_AUD_MEMIF_UL8] = "aud_memif_ul8",
[MT8195_CLK_AUD_MEMIF_UL9] = "aud_memif_ul9",
[MT8195_CLK_AUD_MEMIF_UL10] = "aud_memif_ul10",
[MT8195_CLK_AUD_MEMIF_DL2] = "aud_memif_dl2",
[MT8195_CLK_AUD_MEMIF_DL3] = "aud_memif_dl3",
[MT8195_CLK_AUD_MEMIF_DL6] = "aud_memif_dl6",
[MT8195_CLK_AUD_MEMIF_DL7] = "aud_memif_dl7",
[MT8195_CLK_AUD_MEMIF_DL8] = "aud_memif_dl8",
[MT8195_CLK_AUD_MEMIF_DL10] = "aud_memif_dl10",
[MT8195_CLK_AUD_MEMIF_DL11] = "aud_memif_dl11",
};
struct mt8195_afe_tuner_cfg {
unsigned int id;
int apll_div_reg;
unsigned int apll_div_shift;
unsigned int apll_div_maskbit;
unsigned int apll_div_default;
int ref_ck_sel_reg;
unsigned int ref_ck_sel_shift;
unsigned int ref_ck_sel_maskbit;
unsigned int ref_ck_sel_default;
int tuner_en_reg;
unsigned int tuner_en_shift;
unsigned int tuner_en_maskbit;
int upper_bound_reg;
unsigned int upper_bound_shift;
unsigned int upper_bound_maskbit;
unsigned int upper_bound_default;
spinlock_t ctrl_lock; /* lock for apll tuner ctrl*/
int ref_cnt;
};
static struct mt8195_afe_tuner_cfg mt8195_afe_tuner_cfgs[MT8195_AUD_PLL_NUM] = {
[MT8195_AUD_PLL1] = {
.id = MT8195_AUD_PLL1,
.apll_div_reg = AFE_APLL_TUNER_CFG,
.apll_div_shift = 4,
.apll_div_maskbit = 0xf,
.apll_div_default = 0x7,
.ref_ck_sel_reg = AFE_APLL_TUNER_CFG,
.ref_ck_sel_shift = 1,
.ref_ck_sel_maskbit = 0x3,
.ref_ck_sel_default = 0x2,
.tuner_en_reg = AFE_APLL_TUNER_CFG,
.tuner_en_shift = 0,
.tuner_en_maskbit = 0x1,
.upper_bound_reg = AFE_APLL_TUNER_CFG,
.upper_bound_shift = 8,
.upper_bound_maskbit = 0xff,
.upper_bound_default = 0x3,
},
[MT8195_AUD_PLL2] = {
.id = MT8195_AUD_PLL2,
.apll_div_reg = AFE_APLL_TUNER_CFG1,
.apll_div_shift = 4,
.apll_div_maskbit = 0xf,
.apll_div_default = 0x7,
.ref_ck_sel_reg = AFE_APLL_TUNER_CFG1,
.ref_ck_sel_shift = 1,
.ref_ck_sel_maskbit = 0x3,
.ref_ck_sel_default = 0x1,
.tuner_en_reg = AFE_APLL_TUNER_CFG1,
.tuner_en_shift = 0,
.tuner_en_maskbit = 0x1,
.upper_bound_reg = AFE_APLL_TUNER_CFG1,
.upper_bound_shift = 8,
.upper_bound_maskbit = 0xff,
.upper_bound_default = 0x3,
},
[MT8195_AUD_PLL3] = {
.id = MT8195_AUD_PLL3,
.apll_div_reg = AFE_EARC_APLL_TUNER_CFG,
.apll_div_shift = 4,
.apll_div_maskbit = 0x3f,
.apll_div_default = 0x3,
.ref_ck_sel_reg = AFE_EARC_APLL_TUNER_CFG,
.ref_ck_sel_shift = 24,
.ref_ck_sel_maskbit = 0x3,
.ref_ck_sel_default = 0x0,
.tuner_en_reg = AFE_EARC_APLL_TUNER_CFG,
.tuner_en_shift = 0,
.tuner_en_maskbit = 0x1,
.upper_bound_reg = AFE_EARC_APLL_TUNER_CFG,
.upper_bound_shift = 12,
.upper_bound_maskbit = 0xff,
.upper_bound_default = 0x4,
},
[MT8195_AUD_PLL4] = {
.id = MT8195_AUD_PLL4,
.apll_div_reg = AFE_SPDIFIN_APLL_TUNER_CFG,
.apll_div_shift = 4,
.apll_div_maskbit = 0x3f,
.apll_div_default = 0x7,
.ref_ck_sel_reg = AFE_SPDIFIN_APLL_TUNER_CFG1,
.ref_ck_sel_shift = 8,
.ref_ck_sel_maskbit = 0x1,
.ref_ck_sel_default = 0,
.tuner_en_reg = AFE_SPDIFIN_APLL_TUNER_CFG,
.tuner_en_shift = 0,
.tuner_en_maskbit = 0x1,
.upper_bound_reg = AFE_SPDIFIN_APLL_TUNER_CFG,
.upper_bound_shift = 12,
.upper_bound_maskbit = 0xff,
.upper_bound_default = 0x4,
},
[MT8195_AUD_PLL5] = {
.id = MT8195_AUD_PLL5,
.apll_div_reg = AFE_LINEIN_APLL_TUNER_CFG,
.apll_div_shift = 4,
.apll_div_maskbit = 0x3f,
.apll_div_default = 0x3,
.ref_ck_sel_reg = AFE_LINEIN_APLL_TUNER_CFG,
.ref_ck_sel_shift = 24,
.ref_ck_sel_maskbit = 0x1,
.ref_ck_sel_default = 0,
.tuner_en_reg = AFE_LINEIN_APLL_TUNER_CFG,
.tuner_en_shift = 0,
.tuner_en_maskbit = 0x1,
.upper_bound_reg = AFE_LINEIN_APLL_TUNER_CFG,
.upper_bound_shift = 12,
.upper_bound_maskbit = 0xff,
.upper_bound_default = 0x4,
},
};
static struct mt8195_afe_tuner_cfg *mt8195_afe_found_apll_tuner(unsigned int id)
{
if (id >= MT8195_AUD_PLL_NUM)
return NULL;
return &mt8195_afe_tuner_cfgs[id];
}
static int mt8195_afe_init_apll_tuner(unsigned int id)
{
struct mt8195_afe_tuner_cfg *cfg = mt8195_afe_found_apll_tuner(id);
if (!cfg)
return -EINVAL;
cfg->ref_cnt = 0;
spin_lock_init(&cfg->ctrl_lock);
return 0;
}
static int mt8195_afe_setup_apll_tuner(struct mtk_base_afe *afe,
unsigned int id)
{
const struct mt8195_afe_tuner_cfg *cfg = mt8195_afe_found_apll_tuner(id);
if (!cfg)
return -EINVAL;
regmap_update_bits(afe->regmap, cfg->apll_div_reg,
cfg->apll_div_maskbit << cfg->apll_div_shift,
cfg->apll_div_default << cfg->apll_div_shift);
regmap_update_bits(afe->regmap, cfg->ref_ck_sel_reg,
cfg->ref_ck_sel_maskbit << cfg->ref_ck_sel_shift,
cfg->ref_ck_sel_default << cfg->ref_ck_sel_shift);
regmap_update_bits(afe->regmap, cfg->upper_bound_reg,
cfg->upper_bound_maskbit << cfg->upper_bound_shift,
cfg->upper_bound_default << cfg->upper_bound_shift);
return 0;
}
static int mt8195_afe_enable_tuner_clk(struct mtk_base_afe *afe,
unsigned int id)
{
struct mt8195_afe_private *afe_priv = afe->platform_priv;
switch (id) {
case MT8195_AUD_PLL1:
mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL]);
mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL1_TUNER]);
break;
case MT8195_AUD_PLL2:
mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL2]);
mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL2_TUNER]);
break;
default:
break;
}
return 0;
}
static int mt8195_afe_disable_tuner_clk(struct mtk_base_afe *afe,
unsigned int id)
{
struct mt8195_afe_private *afe_priv = afe->platform_priv;
switch (id) {
case MT8195_AUD_PLL1:
mt8195_afe_disable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL1_TUNER]);
mt8195_afe_disable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL]);
break;
case MT8195_AUD_PLL2:
mt8195_afe_disable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL2_TUNER]);
mt8195_afe_disable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL2]);
break;
default:
break;
}
return 0;
}
static int mt8195_afe_enable_apll_tuner(struct mtk_base_afe *afe,
unsigned int id)
{
struct mt8195_afe_tuner_cfg *cfg = mt8195_afe_found_apll_tuner(id);
unsigned long flags;
int ret;
if (!cfg)
return -EINVAL;
ret = mt8195_afe_setup_apll_tuner(afe, id);
if (ret)
return ret;
ret = mt8195_afe_enable_tuner_clk(afe, id);
if (ret)
return ret;
spin_lock_irqsave(&cfg->ctrl_lock, flags);
cfg->ref_cnt++;
if (cfg->ref_cnt == 1)
regmap_update_bits(afe->regmap,
cfg->tuner_en_reg,
cfg->tuner_en_maskbit << cfg->tuner_en_shift,
1 << cfg->tuner_en_shift);
spin_unlock_irqrestore(&cfg->ctrl_lock, flags);
return 0;
}
static int mt8195_afe_disable_apll_tuner(struct mtk_base_afe *afe,
unsigned int id)
{
struct mt8195_afe_tuner_cfg *cfg = mt8195_afe_found_apll_tuner(id);
unsigned long flags;
int ret;
if (!cfg)
return -EINVAL;
spin_lock_irqsave(&cfg->ctrl_lock, flags);
cfg->ref_cnt--;
if (cfg->ref_cnt == 0)
regmap_update_bits(afe->regmap,
cfg->tuner_en_reg,
cfg->tuner_en_maskbit << cfg->tuner_en_shift,
0 << cfg->tuner_en_shift);
else if (cfg->ref_cnt < 0)
cfg->ref_cnt = 0;
spin_unlock_irqrestore(&cfg->ctrl_lock, flags);
ret = mt8195_afe_disable_tuner_clk(afe, id);
if (ret)
return ret;
return 0;
}
int mt8195_afe_get_mclk_source_clk_id(int sel)
{
switch (sel) {
case MT8195_MCK_SEL_26M:
return MT8195_CLK_XTAL_26M;
case MT8195_MCK_SEL_APLL1:
return MT8195_CLK_TOP_APLL1;
case MT8195_MCK_SEL_APLL2:
return MT8195_CLK_TOP_APLL2;
default:
return -EINVAL;
}
}
int mt8195_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll)
{
struct mt8195_afe_private *afe_priv = afe->platform_priv;
int clk_id = mt8195_afe_get_mclk_source_clk_id(apll);
if (clk_id < 0) {
dev_dbg(afe->dev, "invalid clk id\n");
return 0;
}
return clk_get_rate(afe_priv->clk[clk_id]);
}
int mt8195_afe_get_default_mclk_source_by_rate(int rate)
{
return ((rate % 8000) == 0) ?
MT8195_MCK_SEL_APLL1 : MT8195_MCK_SEL_APLL2;
}
int mt8195_afe_init_clock(struct mtk_base_afe *afe)
{
struct mt8195_afe_private *afe_priv = afe->platform_priv;
int i, ret;
mt8195_audsys_clk_register(afe);
afe_priv->clk =
devm_kcalloc(afe->dev, MT8195_CLK_NUM, sizeof(*afe_priv->clk),
GFP_KERNEL);
if (!afe_priv->clk)
return -ENOMEM;
for (i = 0; i < MT8195_CLK_NUM; i++) {
afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);
if (IS_ERR(afe_priv->clk[i])) {
dev_dbg(afe->dev, "%s(), devm_clk_get %s fail, ret %ld\n",
__func__, aud_clks[i],
PTR_ERR(afe_priv->clk[i]));
return PTR_ERR(afe_priv->clk[i]);
}
}
/* initial tuner */
for (i = 0; i < MT8195_AUD_PLL_NUM; i++) {
ret = mt8195_afe_init_apll_tuner(i);
if (ret) {
dev_dbg(afe->dev, "%s(), init apll_tuner%d failed",
__func__, (i + 1));
return -EINVAL;
}
}
return 0;
}
int mt8195_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk)
{
int ret;
if (clk) {
ret = clk_prepare_enable(clk);
if (ret) {
dev_dbg(afe->dev, "%s(), failed to enable clk\n",
__func__);
return ret;
}
} else {
dev_dbg(afe->dev, "NULL clk\n");
}
return 0;
}
EXPORT_SYMBOL_GPL(mt8195_afe_enable_clk);
void mt8195_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk)
{
if (clk)
clk_disable_unprepare(clk);
else
dev_dbg(afe->dev, "NULL clk\n");
}
EXPORT_SYMBOL_GPL(mt8195_afe_disable_clk);
int mt8195_afe_prepare_clk(struct mtk_base_afe *afe, struct clk *clk)
{
int ret;
if (clk) {
ret = clk_prepare(clk);
if (ret) {
dev_dbg(afe->dev, "%s(), failed to prepare clk\n",
__func__);
return ret;
}
} else {
dev_dbg(afe->dev, "NULL clk\n");
}
return 0;
}
void mt8195_afe_unprepare_clk(struct mtk_base_afe *afe, struct clk *clk)
{
if (clk)
clk_unprepare(clk);
else
dev_dbg(afe->dev, "NULL clk\n");
}
int mt8195_afe_enable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk)
{
int ret;
if (clk) {
ret = clk_enable(clk);
if (ret) {
dev_dbg(afe->dev, "%s(), failed to clk enable\n",
__func__);
return ret;
}
} else {
dev_dbg(afe->dev, "NULL clk\n");
}
return 0;
}
void mt8195_afe_disable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk)
{
if (clk)
clk_disable(clk);
else
dev_dbg(afe->dev, "NULL clk\n");
}
int mt8195_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk,
unsigned int rate)
{
int ret;
if (clk) {
ret = clk_set_rate(clk, rate);
if (ret) {
dev_dbg(afe->dev, "%s(), failed to set clk rate\n",
__func__);
return ret;
}
}
return 0;
}
int mt8195_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk,
struct clk *parent)
{
int ret;
if (clk && parent) {
ret = clk_set_parent(clk, parent);
if (ret) {
dev_dbg(afe->dev, "%s(), failed to set clk parent\n",
__func__);
return ret;
}
}
return 0;
}
static unsigned int get_top_cg_reg(unsigned int cg_type)
{
switch (cg_type) {
case MT8195_TOP_CG_A1SYS_TIMING:
case MT8195_TOP_CG_A2SYS_TIMING:
case MT8195_TOP_CG_26M_TIMING:
return ASYS_TOP_CON;
default:
return 0;
}
}
static unsigned int get_top_cg_mask(unsigned int cg_type)
{
switch (cg_type) {
case MT8195_TOP_CG_A1SYS_TIMING:
return ASYS_TOP_CON_A1SYS_TIMING_ON;
case MT8195_TOP_CG_A2SYS_TIMING:
return ASYS_TOP_CON_A2SYS_TIMING_ON;
case MT8195_TOP_CG_26M_TIMING:
return ASYS_TOP_CON_26M_TIMING_ON;
default:
return 0;
}
}
static unsigned int get_top_cg_on_val(unsigned int cg_type)
{
switch (cg_type) {
case MT8195_TOP_CG_A1SYS_TIMING:
case MT8195_TOP_CG_A2SYS_TIMING:
case MT8195_TOP_CG_26M_TIMING:
return get_top_cg_mask(cg_type);
default:
return 0;
}
}
static unsigned int get_top_cg_off_val(unsigned int cg_type)
{
switch (cg_type) {
case MT8195_TOP_CG_A1SYS_TIMING:
case MT8195_TOP_CG_A2SYS_TIMING:
case MT8195_TOP_CG_26M_TIMING:
return 0;
default:
return get_top_cg_mask(cg_type);
}
}
static int mt8195_afe_enable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)
{
unsigned int reg = get_top_cg_reg(cg_type);
unsigned int mask = get_top_cg_mask(cg_type);
unsigned int val = get_top_cg_on_val(cg_type);
regmap_update_bits(afe->regmap, reg, mask, val);
return 0;
}
static int mt8195_afe_disable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)
{
unsigned int reg = get_top_cg_reg(cg_type);
unsigned int mask = get_top_cg_mask(cg_type);
unsigned int val = get_top_cg_off_val(cg_type);
regmap_update_bits(afe->regmap, reg, mask, val);
return 0;
}
int mt8195_afe_enable_reg_rw_clk(struct mtk_base_afe *afe)
{
struct mt8195_afe_private *afe_priv = afe->platform_priv;
int i;
static const unsigned int clk_array[] = {
MT8195_CLK_SCP_ADSP_AUDIODSP, /* bus clock for infra */
MT8195_CLK_TOP_AUDIO_H_SEL, /* clock for ADSP bus */
MT8195_CLK_TOP_AUDIO_LOCAL_BUS_SEL, /* bus clock for DRAM access */
MT8195_CLK_TOP_AUD_INTBUS_SEL, /* bus clock for AFE SRAM access */
MT8195_CLK_INFRA_AO_AUDIO_26M_B, /* audio 26M clock */
MT8195_CLK_AUD_AFE, /* AFE HW master switch */
MT8195_CLK_AUD_A1SYS_HP, /* AFE HW clock*/
MT8195_CLK_AUD_A1SYS, /* AFE HW clock */
};
for (i = 0; i < ARRAY_SIZE(clk_array); i++)
mt8195_afe_enable_clk(afe, afe_priv->clk[clk_array[i]]);
return 0;
}
int mt8195_afe_disable_reg_rw_clk(struct mtk_base_afe *afe)
{
struct mt8195_afe_private *afe_priv = afe->platform_priv;
int i;
static const unsigned int clk_array[] = {
MT8195_CLK_AUD_A1SYS,
MT8195_CLK_AUD_A1SYS_HP,
MT8195_CLK_AUD_AFE,
MT8195_CLK_INFRA_AO_AUDIO_26M_B,
MT8195_CLK_TOP_AUD_INTBUS_SEL,
MT8195_CLK_TOP_AUDIO_LOCAL_BUS_SEL,
MT8195_CLK_TOP_AUDIO_H_SEL,
MT8195_CLK_SCP_ADSP_AUDIODSP,
};
for (i = 0; i < ARRAY_SIZE(clk_array); i++)
mt8195_afe_disable_clk(afe, afe_priv->clk[clk_array[i]]);
return 0;
}
static int mt8195_afe_enable_afe_on(struct mtk_base_afe *afe)
{
regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1);
return 0;
}
static int mt8195_afe_disable_afe_on(struct mtk_base_afe *afe)
{
regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x0);
return 0;
}
static int mt8195_afe_enable_timing_sys(struct mtk_base_afe *afe)
{
struct mt8195_afe_private *afe_priv = afe->platform_priv;
int i;
static const unsigned int clk_array[] = {
MT8195_CLK_AUD_A1SYS,
MT8195_CLK_AUD_A2SYS,
};
static const unsigned int cg_array[] = {
MT8195_TOP_CG_A1SYS_TIMING,
MT8195_TOP_CG_A2SYS_TIMING,
MT8195_TOP_CG_26M_TIMING,
};
for (i = 0; i < ARRAY_SIZE(clk_array); i++)
mt8195_afe_enable_clk(afe, afe_priv->clk[clk_array[i]]);
for (i = 0; i < ARRAY_SIZE(cg_array); i++)
mt8195_afe_enable_top_cg(afe, cg_array[i]);
return 0;
}
static int mt8195_afe_disable_timing_sys(struct mtk_base_afe *afe)
{
struct mt8195_afe_private *afe_priv = afe->platform_priv;
int i;
static const unsigned int clk_array[] = {
MT8195_CLK_AUD_A2SYS,
MT8195_CLK_AUD_A1SYS,
};
static const unsigned int cg_array[] = {
MT8195_TOP_CG_26M_TIMING,
MT8195_TOP_CG_A2SYS_TIMING,
MT8195_TOP_CG_A1SYS_TIMING,
};
for (i = 0; i < ARRAY_SIZE(cg_array); i++)
mt8195_afe_disable_top_cg(afe, cg_array[i]);
for (i = 0; i < ARRAY_SIZE(clk_array); i++)
mt8195_afe_disable_clk(afe, afe_priv->clk[clk_array[i]]);
return 0;
}
int mt8195_afe_enable_main_clock(struct mtk_base_afe *afe)
{
mt8195_afe_enable_timing_sys(afe);
mt8195_afe_enable_afe_on(afe);
mt8195_afe_enable_apll_tuner(afe, MT8195_AUD_PLL1);
mt8195_afe_enable_apll_tuner(afe, MT8195_AUD_PLL2);
return 0;
}
int mt8195_afe_disable_main_clock(struct mtk_base_afe *afe)
{
mt8195_afe_disable_apll_tuner(afe, MT8195_AUD_PLL2);
mt8195_afe_disable_apll_tuner(afe, MT8195_AUD_PLL1);
mt8195_afe_disable_afe_on(afe);
mt8195_afe_disable_timing_sys(afe);
return 0;
}
| linux-master | sound/soc/mediatek/mt8195/mt8195-afe-clk.c |
// SPDX-License-Identifier: GPL-2.0
/*
* mt8195-mt6359.c --
* MT8195-MT6359 ALSA SoC machine driver code
*
* Copyright (c) 2022 MediaTek Inc.
* Author: Trevor Wu <[email protected]>
* YC Hung <[email protected]>
*/
#include <linux/input.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/pm_runtime.h>
#include <sound/jack.h>
#include <sound/pcm_params.h>
#include <sound/rt5682.h>
#include <sound/soc.h>
#include "../../codecs/mt6359.h"
#include "../../codecs/rt1011.h"
#include "../../codecs/rt5682.h"
#include "../common/mtk-afe-platform-driver.h"
#include "../common/mtk-dsp-sof-common.h"
#include "../common/mtk-soc-card.h"
#include "mt8195-afe-clk.h"
#include "mt8195-afe-common.h"
#define RT1011_SPEAKER_AMP_PRESENT BIT(0)
#define RT1019_SPEAKER_AMP_PRESENT BIT(1)
#define MAX98390_SPEAKER_AMP_PRESENT BIT(2)
#define RT1011_CODEC_DAI "rt1011-aif"
#define RT1011_DEV0_NAME "rt1011.2-0038"
#define RT1011_DEV1_NAME "rt1011.2-0039"
#define RT1019_CODEC_DAI "HiFi"
#define RT1019_DEV0_NAME "rt1019p"
#define MAX98390_CODEC_DAI "max98390-aif1"
#define MAX98390_DEV0_NAME "max98390.2-0038" /* right */
#define MAX98390_DEV1_NAME "max98390.2-0039" /* left */
#define RT5682_CODEC_DAI "rt5682-aif1"
#define RT5682_DEV0_NAME "rt5682.2-001a"
#define RT5682S_CODEC_DAI "rt5682s-aif1"
#define RT5682S_DEV0_NAME "rt5682s.2-001a"
#define SOF_DMA_DL2 "SOF_DMA_DL2"
#define SOF_DMA_DL3 "SOF_DMA_DL3"
#define SOF_DMA_UL4 "SOF_DMA_UL4"
#define SOF_DMA_UL5 "SOF_DMA_UL5"
struct mt8195_card_data {
const char *name;
unsigned long quirk;
};
struct mt8195_mt6359_priv {
struct snd_soc_jack headset_jack;
struct snd_soc_jack dp_jack;
struct snd_soc_jack hdmi_jack;
struct clk *i2so1_mclk;
};
/* Headset jack detection DAPM pins */
static struct snd_soc_jack_pin mt8195_jack_pins[] = {
{
.pin = "Headphone",
.mask = SND_JACK_HEADPHONE,
},
{
.pin = "Headset Mic",
.mask = SND_JACK_MICROPHONE,
},
};
static const struct snd_soc_dapm_widget mt8195_mt6359_widgets[] = {
SND_SOC_DAPM_HP("Headphone", NULL),
SND_SOC_DAPM_MIC("Headset Mic", NULL),
SND_SOC_DAPM_MIXER(SOF_DMA_DL2, SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER(SOF_DMA_DL3, SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER(SOF_DMA_UL4, SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER(SOF_DMA_UL5, SND_SOC_NOPM, 0, 0, NULL, 0),
};
static const struct snd_soc_dapm_route mt8195_mt6359_routes[] = {
/* headset */
{ "Headphone", NULL, "HPOL" },
{ "Headphone", NULL, "HPOR" },
{ "IN1P", NULL, "Headset Mic" },
/* SOF Uplink */
{SOF_DMA_UL4, NULL, "O034"},
{SOF_DMA_UL4, NULL, "O035"},
{SOF_DMA_UL5, NULL, "O036"},
{SOF_DMA_UL5, NULL, "O037"},
/* SOF Downlink */
{"I070", NULL, SOF_DMA_DL2},
{"I071", NULL, SOF_DMA_DL2},
{"I020", NULL, SOF_DMA_DL3},
{"I021", NULL, SOF_DMA_DL3},
};
static const struct snd_kcontrol_new mt8195_mt6359_controls[] = {
SOC_DAPM_PIN_SWITCH("Headphone"),
SOC_DAPM_PIN_SWITCH("Headset Mic"),
};
static const struct snd_soc_dapm_widget mt8195_dual_speaker_widgets[] = {
SND_SOC_DAPM_SPK("Left Spk", NULL),
SND_SOC_DAPM_SPK("Right Spk", NULL),
};
static const struct snd_kcontrol_new mt8195_dual_speaker_controls[] = {
SOC_DAPM_PIN_SWITCH("Left Spk"),
SOC_DAPM_PIN_SWITCH("Right Spk"),
};
static const struct snd_soc_dapm_widget mt8195_speaker_widgets[] = {
SND_SOC_DAPM_SPK("Ext Spk", NULL),
};
static const struct snd_kcontrol_new mt8195_speaker_controls[] = {
SOC_DAPM_PIN_SWITCH("Ext Spk"),
};
static const struct snd_soc_dapm_route mt8195_rt1011_routes[] = {
{ "Left Spk", NULL, "Left SPO" },
{ "Right Spk", NULL, "Right SPO" },
};
static const struct snd_soc_dapm_route mt8195_rt1019_routes[] = {
{ "Ext Spk", NULL, "Speaker" },
};
static const struct snd_soc_dapm_route mt8195_max98390_routes[] = {
{ "Left Spk", NULL, "Left BE_OUT" },
{ "Right Spk", NULL, "Right BE_OUT" },
};
#define CKSYS_AUD_TOP_CFG 0x032c
#define CKSYS_AUD_TOP_MON 0x0330
static int mt8195_mt6359_mtkaif_calibration(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_component *cmpnt_afe =
snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
struct snd_soc_component *cmpnt_codec =
asoc_rtd_to_codec(rtd, 0)->component;
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt_afe);
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtkaif_param *param = &afe_priv->mtkaif_params;
int chosen_phase_1, chosen_phase_2, chosen_phase_3;
int prev_cycle_1, prev_cycle_2, prev_cycle_3;
int test_done_1, test_done_2, test_done_3;
int cycle_1, cycle_2, cycle_3;
int mtkaif_chosen_phase[MT8195_MTKAIF_MISO_NUM];
int mtkaif_phase_cycle[MT8195_MTKAIF_MISO_NUM];
int mtkaif_calibration_num_phase;
bool mtkaif_calibration_ok;
unsigned int monitor = 0;
int counter;
int phase;
int i;
dev_dbg(afe->dev, "%s(), start\n", __func__);
param->mtkaif_calibration_ok = false;
for (i = 0; i < MT8195_MTKAIF_MISO_NUM; i++) {
param->mtkaif_chosen_phase[i] = -1;
param->mtkaif_phase_cycle[i] = 0;
mtkaif_chosen_phase[i] = -1;
mtkaif_phase_cycle[i] = 0;
}
if (IS_ERR(afe_priv->topckgen)) {
dev_info(afe->dev, "%s() Cannot find topckgen controller\n",
__func__);
return 0;
}
pm_runtime_get_sync(afe->dev);
mt6359_mtkaif_calibration_enable(cmpnt_codec);
/* set test type to synchronizer pulse */
regmap_update_bits(afe_priv->topckgen,
CKSYS_AUD_TOP_CFG, 0xffff, 0x4);
mtkaif_calibration_num_phase = 42; /* mt6359: 0 ~ 42 */
mtkaif_calibration_ok = true;
for (phase = 0;
phase <= mtkaif_calibration_num_phase && mtkaif_calibration_ok;
phase++) {
mt6359_set_mtkaif_calibration_phase(cmpnt_codec,
phase, phase, phase);
regmap_update_bits(afe_priv->topckgen,
CKSYS_AUD_TOP_CFG, 0x1, 0x1);
test_done_1 = 0;
test_done_2 = 0;
test_done_3 = 0;
cycle_1 = -1;
cycle_2 = -1;
cycle_3 = -1;
counter = 0;
while (!(test_done_1 & test_done_2 & test_done_3)) {
regmap_read(afe_priv->topckgen,
CKSYS_AUD_TOP_MON, &monitor);
test_done_1 = (monitor >> 28) & 0x1;
test_done_2 = (monitor >> 29) & 0x1;
test_done_3 = (monitor >> 30) & 0x1;
if (test_done_1 == 1)
cycle_1 = monitor & 0xf;
if (test_done_2 == 1)
cycle_2 = (monitor >> 4) & 0xf;
if (test_done_3 == 1)
cycle_3 = (monitor >> 8) & 0xf;
/* handle if never test done */
if (++counter > 10000) {
dev_info(afe->dev, "%s(), test fail, cycle_1 %d, cycle_2 %d, cycle_3 %d, monitor 0x%x\n",
__func__,
cycle_1, cycle_2, cycle_3, monitor);
mtkaif_calibration_ok = false;
break;
}
}
if (phase == 0) {
prev_cycle_1 = cycle_1;
prev_cycle_2 = cycle_2;
prev_cycle_3 = cycle_3;
}
if (cycle_1 != prev_cycle_1 &&
mtkaif_chosen_phase[MT8195_MTKAIF_MISO_0] < 0) {
mtkaif_chosen_phase[MT8195_MTKAIF_MISO_0] = phase - 1;
mtkaif_phase_cycle[MT8195_MTKAIF_MISO_0] = prev_cycle_1;
}
if (cycle_2 != prev_cycle_2 &&
mtkaif_chosen_phase[MT8195_MTKAIF_MISO_1] < 0) {
mtkaif_chosen_phase[MT8195_MTKAIF_MISO_1] = phase - 1;
mtkaif_phase_cycle[MT8195_MTKAIF_MISO_1] = prev_cycle_2;
}
if (cycle_3 != prev_cycle_3 &&
mtkaif_chosen_phase[MT8195_MTKAIF_MISO_2] < 0) {
mtkaif_chosen_phase[MT8195_MTKAIF_MISO_2] = phase - 1;
mtkaif_phase_cycle[MT8195_MTKAIF_MISO_2] = prev_cycle_3;
}
regmap_update_bits(afe_priv->topckgen,
CKSYS_AUD_TOP_CFG, 0x1, 0x0);
if (mtkaif_chosen_phase[MT8195_MTKAIF_MISO_0] >= 0 &&
mtkaif_chosen_phase[MT8195_MTKAIF_MISO_1] >= 0 &&
mtkaif_chosen_phase[MT8195_MTKAIF_MISO_2] >= 0)
break;
}
if (mtkaif_chosen_phase[MT8195_MTKAIF_MISO_0] < 0) {
mtkaif_calibration_ok = false;
chosen_phase_1 = 0;
} else {
chosen_phase_1 = mtkaif_chosen_phase[MT8195_MTKAIF_MISO_0];
}
if (mtkaif_chosen_phase[MT8195_MTKAIF_MISO_1] < 0) {
mtkaif_calibration_ok = false;
chosen_phase_2 = 0;
} else {
chosen_phase_2 = mtkaif_chosen_phase[MT8195_MTKAIF_MISO_1];
}
if (mtkaif_chosen_phase[MT8195_MTKAIF_MISO_2] < 0) {
mtkaif_calibration_ok = false;
chosen_phase_3 = 0;
} else {
chosen_phase_3 = mtkaif_chosen_phase[MT8195_MTKAIF_MISO_2];
}
mt6359_set_mtkaif_calibration_phase(cmpnt_codec,
chosen_phase_1,
chosen_phase_2,
chosen_phase_3);
mt6359_mtkaif_calibration_disable(cmpnt_codec);
pm_runtime_put(afe->dev);
param->mtkaif_calibration_ok = mtkaif_calibration_ok;
param->mtkaif_chosen_phase[MT8195_MTKAIF_MISO_0] = chosen_phase_1;
param->mtkaif_chosen_phase[MT8195_MTKAIF_MISO_1] = chosen_phase_2;
param->mtkaif_chosen_phase[MT8195_MTKAIF_MISO_2] = chosen_phase_3;
for (i = 0; i < MT8195_MTKAIF_MISO_NUM; i++)
param->mtkaif_phase_cycle[i] = mtkaif_phase_cycle[i];
dev_info(afe->dev, "%s(), end, calibration ok %d\n",
__func__, param->mtkaif_calibration_ok);
return 0;
}
static int mt8195_mt6359_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_component *cmpnt_codec =
asoc_rtd_to_codec(rtd, 0)->component;
/* set mtkaif protocol */
mt6359_set_mtkaif_protocol(cmpnt_codec,
MT6359_MTKAIF_PROTOCOL_2_CLK_P2);
/* mtkaif calibration */
mt8195_mt6359_mtkaif_calibration(rtd);
return 0;
}
static int mt8195_hdmitx_dptx_startup(struct snd_pcm_substream *substream)
{
static const unsigned int rates[] = {
48000
};
static const unsigned int channels[] = {
2, 4, 6, 8
};
static const struct snd_pcm_hw_constraint_list constraints_rates = {
.count = ARRAY_SIZE(rates),
.list = rates,
.mask = 0,
};
static const struct snd_pcm_hw_constraint_list constraints_channels = {
.count = ARRAY_SIZE(channels),
.list = channels,
.mask = 0,
};
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_pcm_runtime *runtime = substream->runtime;
int ret;
ret = snd_pcm_hw_constraint_list(runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
&constraints_rates);
if (ret < 0) {
dev_err(rtd->dev, "hw_constraint_list rate failed\n");
return ret;
}
ret = snd_pcm_hw_constraint_list(runtime, 0,
SNDRV_PCM_HW_PARAM_CHANNELS,
&constraints_channels);
if (ret < 0) {
dev_err(rtd->dev, "hw_constraint_list channel failed\n");
return ret;
}
return 0;
}
static const struct snd_soc_ops mt8195_hdmitx_dptx_playback_ops = {
.startup = mt8195_hdmitx_dptx_startup,
};
static int mt8195_dptx_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
return snd_soc_dai_set_sysclk(cpu_dai, 0, params_rate(params) * 256,
SND_SOC_CLOCK_OUT);
}
static const struct snd_soc_ops mt8195_dptx_ops = {
.hw_params = mt8195_dptx_hw_params,
};
static int mt8195_dptx_codec_init(struct snd_soc_pcm_runtime *rtd)
{
struct mtk_soc_card_data *soc_card_data = snd_soc_card_get_drvdata(rtd->card);
struct mt8195_mt6359_priv *priv = soc_card_data->mach_priv;
struct snd_soc_component *cmpnt_codec =
asoc_rtd_to_codec(rtd, 0)->component;
int ret;
ret = snd_soc_card_jack_new(rtd->card, "DP Jack", SND_JACK_LINEOUT,
&priv->dp_jack);
if (ret)
return ret;
return snd_soc_component_set_jack(cmpnt_codec, &priv->dp_jack, NULL);
}
static int mt8195_hdmi_codec_init(struct snd_soc_pcm_runtime *rtd)
{
struct mtk_soc_card_data *soc_card_data = snd_soc_card_get_drvdata(rtd->card);
struct mt8195_mt6359_priv *priv = soc_card_data->mach_priv;
struct snd_soc_component *cmpnt_codec =
asoc_rtd_to_codec(rtd, 0)->component;
int ret;
ret = snd_soc_card_jack_new(rtd->card, "HDMI Jack", SND_JACK_LINEOUT,
&priv->hdmi_jack);
if (ret)
return ret;
return snd_soc_component_set_jack(cmpnt_codec, &priv->hdmi_jack, NULL);
}
static int mt8195_dptx_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
struct snd_pcm_hw_params *params)
{
/* fix BE i2s format to S24_LE, clean param mask first */
snd_mask_reset_range(hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT),
0, (__force unsigned int)SNDRV_PCM_FORMAT_LAST);
params_set_format(params, SNDRV_PCM_FORMAT_S24_LE);
return 0;
}
static int mt8195_playback_startup(struct snd_pcm_substream *substream)
{
static const unsigned int rates[] = {
48000
};
static const unsigned int channels[] = {
2
};
static const struct snd_pcm_hw_constraint_list constraints_rates = {
.count = ARRAY_SIZE(rates),
.list = rates,
.mask = 0,
};
static const struct snd_pcm_hw_constraint_list constraints_channels = {
.count = ARRAY_SIZE(channels),
.list = channels,
.mask = 0,
};
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_pcm_runtime *runtime = substream->runtime;
int ret;
ret = snd_pcm_hw_constraint_list(runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
&constraints_rates);
if (ret < 0) {
dev_err(rtd->dev, "hw_constraint_list rate failed\n");
return ret;
}
ret = snd_pcm_hw_constraint_list(runtime, 0,
SNDRV_PCM_HW_PARAM_CHANNELS,
&constraints_channels);
if (ret < 0) {
dev_err(rtd->dev, "hw_constraint_list channel failed\n");
return ret;
}
return 0;
}
static const struct snd_soc_ops mt8195_playback_ops = {
.startup = mt8195_playback_startup,
};
static int mt8195_capture_startup(struct snd_pcm_substream *substream)
{
static const unsigned int rates[] = {
48000
};
static const unsigned int channels[] = {
1, 2
};
static const struct snd_pcm_hw_constraint_list constraints_rates = {
.count = ARRAY_SIZE(rates),
.list = rates,
.mask = 0,
};
static const struct snd_pcm_hw_constraint_list constraints_channels = {
.count = ARRAY_SIZE(channels),
.list = channels,
.mask = 0,
};
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_pcm_runtime *runtime = substream->runtime;
int ret;
ret = snd_pcm_hw_constraint_list(runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
&constraints_rates);
if (ret < 0) {
dev_err(rtd->dev, "hw_constraint_list rate failed\n");
return ret;
}
ret = snd_pcm_hw_constraint_list(runtime, 0,
SNDRV_PCM_HW_PARAM_CHANNELS,
&constraints_channels);
if (ret < 0) {
dev_err(rtd->dev, "hw_constraint_list channel failed\n");
return ret;
}
return 0;
}
static const struct snd_soc_ops mt8195_capture_ops = {
.startup = mt8195_capture_startup,
};
static int mt8195_rt5682_etdm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_card *card = rtd->card;
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
unsigned int rate = params_rate(params);
int bitwidth;
int ret;
bitwidth = snd_pcm_format_width(params_format(params));
if (bitwidth < 0) {
dev_err(card->dev, "invalid bit width: %d\n", bitwidth);
return bitwidth;
}
ret = snd_soc_dai_set_tdm_slot(codec_dai, 0x00, 0x0, 0x2, bitwidth);
if (ret) {
dev_err(card->dev, "failed to set tdm slot\n");
return ret;
}
ret = snd_soc_dai_set_pll(codec_dai, RT5682_PLL1, RT5682_PLL1_S_MCLK,
rate * 256, rate * 512);
if (ret) {
dev_err(card->dev, "failed to set pll\n");
return ret;
}
ret = snd_soc_dai_set_sysclk(codec_dai, RT5682_SCLK_S_PLL1,
rate * 512, SND_SOC_CLOCK_IN);
if (ret) {
dev_err(card->dev, "failed to set sysclk\n");
return ret;
}
return snd_soc_dai_set_sysclk(cpu_dai, 0, rate * 256,
SND_SOC_CLOCK_OUT);
}
static const struct snd_soc_ops mt8195_rt5682_etdm_ops = {
.hw_params = mt8195_rt5682_etdm_hw_params,
};
static int mt8195_rt5682_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_component *cmpnt_codec =
asoc_rtd_to_codec(rtd, 0)->component;
struct mtk_soc_card_data *soc_card_data = snd_soc_card_get_drvdata(rtd->card);
struct mt8195_mt6359_priv *priv = soc_card_data->mach_priv;
struct snd_soc_jack *jack = &priv->headset_jack;
struct snd_soc_component *cmpnt_afe =
snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt_afe);
struct mt8195_afe_private *afe_priv = afe->platform_priv;
int ret;
priv->i2so1_mclk = afe_priv->clk[MT8195_CLK_TOP_APLL12_DIV2];
ret = snd_soc_card_jack_new_pins(rtd->card, "Headset Jack",
SND_JACK_HEADSET | SND_JACK_BTN_0 |
SND_JACK_BTN_1 | SND_JACK_BTN_2 |
SND_JACK_BTN_3,
jack, mt8195_jack_pins,
ARRAY_SIZE(mt8195_jack_pins));
if (ret) {
dev_err(rtd->dev, "Headset Jack creation failed: %d\n", ret);
return ret;
}
snd_jack_set_key(jack->jack, SND_JACK_BTN_0, KEY_PLAYPAUSE);
snd_jack_set_key(jack->jack, SND_JACK_BTN_1, KEY_VOICECOMMAND);
snd_jack_set_key(jack->jack, SND_JACK_BTN_2, KEY_VOLUMEUP);
snd_jack_set_key(jack->jack, SND_JACK_BTN_3, KEY_VOLUMEDOWN);
ret = snd_soc_component_set_jack(cmpnt_codec, jack, NULL);
if (ret) {
dev_err(rtd->dev, "Headset Jack set failed: %d\n", ret);
return ret;
}
return 0;
};
static int mt8195_rt1011_etdm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai *codec_dai;
struct snd_soc_card *card = rtd->card;
int srate, i, ret;
srate = params_rate(params);
for_each_rtd_codec_dais(rtd, i, codec_dai) {
ret = snd_soc_dai_set_pll(codec_dai, 0, RT1011_PLL1_S_BCLK,
64 * srate, 256 * srate);
if (ret < 0) {
dev_err(card->dev, "codec_dai clock not set\n");
return ret;
}
ret = snd_soc_dai_set_sysclk(codec_dai,
RT1011_FS_SYS_PRE_S_PLL1,
256 * srate, SND_SOC_CLOCK_IN);
if (ret < 0) {
dev_err(card->dev, "codec_dai clock not set\n");
return ret;
}
}
return 0;
}
static const struct snd_soc_ops mt8195_rt1011_etdm_ops = {
.hw_params = mt8195_rt1011_etdm_hw_params,
};
static int mt8195_sof_be_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_component *cmpnt_afe = NULL;
struct snd_soc_pcm_runtime *runtime;
/* find afe component */
for_each_card_rtds(rtd->card, runtime) {
cmpnt_afe = snd_soc_rtdcom_lookup(runtime, AFE_PCM_NAME);
if (cmpnt_afe)
break;
}
if (cmpnt_afe && !pm_runtime_active(cmpnt_afe->dev)) {
dev_err(rtd->dev, "afe pm runtime is not active!!\n");
return -EINVAL;
}
return 0;
}
static const struct snd_soc_ops mt8195_sof_be_ops = {
.hw_params = mt8195_sof_be_hw_params,
};
static int mt8195_rt1011_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_card *card = rtd->card;
int ret;
ret = snd_soc_dapm_new_controls(&card->dapm, mt8195_dual_speaker_widgets,
ARRAY_SIZE(mt8195_dual_speaker_widgets));
if (ret) {
dev_err(rtd->dev, "unable to add dapm controls, ret %d\n", ret);
/* Don't need to add routes if widget addition failed */
return ret;
}
ret = snd_soc_add_card_controls(card, mt8195_dual_speaker_controls,
ARRAY_SIZE(mt8195_dual_speaker_controls));
if (ret) {
dev_err(rtd->dev, "unable to add card controls, ret %d\n", ret);
return ret;
}
ret = snd_soc_dapm_add_routes(&card->dapm, mt8195_rt1011_routes,
ARRAY_SIZE(mt8195_rt1011_routes));
if (ret)
dev_err(rtd->dev, "unable to add dapm routes, ret %d\n", ret);
return ret;
}
static int mt8195_rt1019_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_card *card = rtd->card;
int ret;
ret = snd_soc_dapm_new_controls(&card->dapm, mt8195_speaker_widgets,
ARRAY_SIZE(mt8195_speaker_widgets));
if (ret) {
dev_err(rtd->dev, "unable to add dapm controls, ret %d\n", ret);
/* Don't need to add routes if widget addition failed */
return ret;
}
ret = snd_soc_add_card_controls(card, mt8195_speaker_controls,
ARRAY_SIZE(mt8195_speaker_controls));
if (ret) {
dev_err(rtd->dev, "unable to add card controls, ret %d\n", ret);
return ret;
}
ret = snd_soc_dapm_add_routes(&card->dapm, mt8195_rt1019_routes,
ARRAY_SIZE(mt8195_rt1019_routes));
if (ret)
dev_err(rtd->dev, "unable to add dapm routes, ret %d\n", ret);
return ret;
}
static int mt8195_max98390_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_card *card = rtd->card;
int ret;
ret = snd_soc_dapm_new_controls(&card->dapm, mt8195_dual_speaker_widgets,
ARRAY_SIZE(mt8195_dual_speaker_widgets));
if (ret) {
dev_err(rtd->dev, "unable to add dapm controls, ret %d\n", ret);
/* Don't need to add routes if widget addition failed */
return ret;
}
ret = snd_soc_add_card_controls(card, mt8195_dual_speaker_controls,
ARRAY_SIZE(mt8195_dual_speaker_controls));
if (ret) {
dev_err(rtd->dev, "unable to add card controls, ret %d\n", ret);
return ret;
}
ret = snd_soc_dapm_add_routes(&card->dapm, mt8195_max98390_routes,
ARRAY_SIZE(mt8195_max98390_routes));
if (ret)
dev_err(rtd->dev, "unable to add dapm routes, ret %d\n", ret);
return ret;
}
static int mt8195_etdm_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
struct snd_pcm_hw_params *params)
{
/* fix BE i2s format to S24_LE, clean param mask first */
snd_mask_reset_range(hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT),
0, (__force unsigned int)SNDRV_PCM_FORMAT_LAST);
params_set_format(params, SNDRV_PCM_FORMAT_S24_LE);
return 0;
}
static int mt8195_set_bias_level_post(struct snd_soc_card *card,
struct snd_soc_dapm_context *dapm, enum snd_soc_bias_level level)
{
struct snd_soc_component *component = dapm->component;
struct mtk_soc_card_data *soc_card_data = snd_soc_card_get_drvdata(card);
struct mt8195_mt6359_priv *priv = soc_card_data->mach_priv;
int ret;
/*
* It's required to control mclk directly in the set_bias_level_post
* function for rt5682 and rt5682s codec, or the unexpected pop happens
* at the end of playback.
*/
if (!component ||
(strcmp(component->name, RT5682_DEV0_NAME) &&
strcmp(component->name, RT5682S_DEV0_NAME)))
return 0;
switch (level) {
case SND_SOC_BIAS_OFF:
if (!__clk_is_enabled(priv->i2so1_mclk))
return 0;
clk_disable_unprepare(priv->i2so1_mclk);
dev_dbg(card->dev, "Disable i2so1 mclk\n");
break;
case SND_SOC_BIAS_ON:
ret = clk_prepare_enable(priv->i2so1_mclk);
if (ret) {
dev_err(card->dev, "Can't enable i2so1 mclk: %d\n", ret);
return ret;
}
dev_dbg(card->dev, "Enable i2so1 mclk\n");
break;
default:
break;
}
return 0;
}
enum {
DAI_LINK_DL2_FE,
DAI_LINK_DL3_FE,
DAI_LINK_DL6_FE,
DAI_LINK_DL7_FE,
DAI_LINK_DL8_FE,
DAI_LINK_DL10_FE,
DAI_LINK_DL11_FE,
DAI_LINK_UL1_FE,
DAI_LINK_UL2_FE,
DAI_LINK_UL3_FE,
DAI_LINK_UL4_FE,
DAI_LINK_UL5_FE,
DAI_LINK_UL6_FE,
DAI_LINK_UL8_FE,
DAI_LINK_UL9_FE,
DAI_LINK_UL10_FE,
DAI_LINK_DL_SRC_BE,
DAI_LINK_DPTX_BE,
DAI_LINK_ETDM1_IN_BE,
DAI_LINK_ETDM2_IN_BE,
DAI_LINK_ETDM1_OUT_BE,
DAI_LINK_ETDM2_OUT_BE,
DAI_LINK_ETDM3_OUT_BE,
DAI_LINK_PCM1_BE,
DAI_LINK_UL_SRC1_BE,
DAI_LINK_UL_SRC2_BE,
DAI_LINK_REGULAR_LAST = DAI_LINK_UL_SRC2_BE,
DAI_LINK_SOF_START,
DAI_LINK_SOF_DL2_BE = DAI_LINK_SOF_START,
DAI_LINK_SOF_DL3_BE,
DAI_LINK_SOF_UL4_BE,
DAI_LINK_SOF_UL5_BE,
DAI_LINK_SOF_END = DAI_LINK_SOF_UL5_BE,
};
#define DAI_LINK_REGULAR_NUM (DAI_LINK_REGULAR_LAST + 1)
/* FE */
SND_SOC_DAILINK_DEFS(DL2_FE,
DAILINK_COMP_ARRAY(COMP_CPU("DL2")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(DL3_FE,
DAILINK_COMP_ARRAY(COMP_CPU("DL3")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(DL6_FE,
DAILINK_COMP_ARRAY(COMP_CPU("DL6")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(DL7_FE,
DAILINK_COMP_ARRAY(COMP_CPU("DL7")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(DL8_FE,
DAILINK_COMP_ARRAY(COMP_CPU("DL8")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(DL10_FE,
DAILINK_COMP_ARRAY(COMP_CPU("DL10")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(DL11_FE,
DAILINK_COMP_ARRAY(COMP_CPU("DL11")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(UL1_FE,
DAILINK_COMP_ARRAY(COMP_CPU("UL1")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(UL2_FE,
DAILINK_COMP_ARRAY(COMP_CPU("UL2")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(UL3_FE,
DAILINK_COMP_ARRAY(COMP_CPU("UL3")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(UL4_FE,
DAILINK_COMP_ARRAY(COMP_CPU("UL4")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(UL5_FE,
DAILINK_COMP_ARRAY(COMP_CPU("UL5")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(UL6_FE,
DAILINK_COMP_ARRAY(COMP_CPU("UL6")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(UL8_FE,
DAILINK_COMP_ARRAY(COMP_CPU("UL8")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(UL9_FE,
DAILINK_COMP_ARRAY(COMP_CPU("UL9")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(UL10_FE,
DAILINK_COMP_ARRAY(COMP_CPU("UL10")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
/* BE */
SND_SOC_DAILINK_DEFS(DL_SRC_BE,
DAILINK_COMP_ARRAY(COMP_CPU("DL_SRC")),
DAILINK_COMP_ARRAY(COMP_CODEC("mt6359-sound",
"mt6359-snd-codec-aif1")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(DPTX_BE,
DAILINK_COMP_ARRAY(COMP_CPU("DPTX")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(ETDM1_IN_BE,
DAILINK_COMP_ARRAY(COMP_CPU("ETDM1_IN")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(ETDM2_IN_BE,
DAILINK_COMP_ARRAY(COMP_CPU("ETDM2_IN")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(ETDM1_OUT_BE,
DAILINK_COMP_ARRAY(COMP_CPU("ETDM1_OUT")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(ETDM2_OUT_BE,
DAILINK_COMP_ARRAY(COMP_CPU("ETDM2_OUT")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(ETDM3_OUT_BE,
DAILINK_COMP_ARRAY(COMP_CPU("ETDM3_OUT")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(PCM1_BE,
DAILINK_COMP_ARRAY(COMP_CPU("PCM1")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(UL_SRC1_BE,
DAILINK_COMP_ARRAY(COMP_CPU("UL_SRC1")),
DAILINK_COMP_ARRAY(COMP_CODEC("mt6359-sound",
"mt6359-snd-codec-aif1"),
COMP_CODEC("dmic-codec",
"dmic-hifi")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(UL_SRC2_BE,
DAILINK_COMP_ARRAY(COMP_CPU("UL_SRC2")),
DAILINK_COMP_ARRAY(COMP_CODEC("mt6359-sound",
"mt6359-snd-codec-aif2")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(AFE_SOF_DL2,
DAILINK_COMP_ARRAY(COMP_CPU("SOF_DL2")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(AFE_SOF_DL3,
DAILINK_COMP_ARRAY(COMP_CPU("SOF_DL3")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(AFE_SOF_UL4,
DAILINK_COMP_ARRAY(COMP_CPU("SOF_UL4")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(AFE_SOF_UL5,
DAILINK_COMP_ARRAY(COMP_CPU("SOF_UL5")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
/* codec */
SND_SOC_DAILINK_DEF(rt1019_comps,
DAILINK_COMP_ARRAY(COMP_CODEC(RT1019_DEV0_NAME,
RT1019_CODEC_DAI)));
SND_SOC_DAILINK_DEF(rt1011_comps,
DAILINK_COMP_ARRAY(COMP_CODEC(RT1011_DEV0_NAME,
RT1011_CODEC_DAI),
COMP_CODEC(RT1011_DEV1_NAME,
RT1011_CODEC_DAI)));
SND_SOC_DAILINK_DEF(max98390_comps,
DAILINK_COMP_ARRAY(COMP_CODEC(MAX98390_DEV0_NAME,
MAX98390_CODEC_DAI),
COMP_CODEC(MAX98390_DEV1_NAME,
MAX98390_CODEC_DAI)));
static const struct sof_conn_stream g_sof_conn_streams[] = {
{ "ETDM2_OUT_BE", "AFE_SOF_DL2", SOF_DMA_DL2, SNDRV_PCM_STREAM_PLAYBACK},
{ "ETDM1_OUT_BE", "AFE_SOF_DL3", SOF_DMA_DL3, SNDRV_PCM_STREAM_PLAYBACK},
{ "UL_SRC1_BE", "AFE_SOF_UL4", SOF_DMA_UL4, SNDRV_PCM_STREAM_CAPTURE},
{ "ETDM2_IN_BE", "AFE_SOF_UL5", SOF_DMA_UL5, SNDRV_PCM_STREAM_CAPTURE},
};
static struct snd_soc_dai_link mt8195_mt6359_dai_links[] = {
/* FE */
[DAI_LINK_DL2_FE] = {
.name = "DL2_FE",
.stream_name = "DL2 Playback",
.trigger = {
SND_SOC_DPCM_TRIGGER_POST,
SND_SOC_DPCM_TRIGGER_POST,
},
.dynamic = 1,
.dpcm_playback = 1,
.ops = &mt8195_playback_ops,
SND_SOC_DAILINK_REG(DL2_FE),
},
[DAI_LINK_DL3_FE] = {
.name = "DL3_FE",
.stream_name = "DL3 Playback",
.trigger = {
SND_SOC_DPCM_TRIGGER_POST,
SND_SOC_DPCM_TRIGGER_POST,
},
.dynamic = 1,
.dpcm_playback = 1,
.ops = &mt8195_playback_ops,
SND_SOC_DAILINK_REG(DL3_FE),
},
[DAI_LINK_DL6_FE] = {
.name = "DL6_FE",
.stream_name = "DL6 Playback",
.trigger = {
SND_SOC_DPCM_TRIGGER_POST,
SND_SOC_DPCM_TRIGGER_POST,
},
.dynamic = 1,
.dpcm_playback = 1,
.ops = &mt8195_playback_ops,
SND_SOC_DAILINK_REG(DL6_FE),
},
[DAI_LINK_DL7_FE] = {
.name = "DL7_FE",
.stream_name = "DL7 Playback",
.trigger = {
SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE,
},
.dynamic = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(DL7_FE),
},
[DAI_LINK_DL8_FE] = {
.name = "DL8_FE",
.stream_name = "DL8 Playback",
.trigger = {
SND_SOC_DPCM_TRIGGER_POST,
SND_SOC_DPCM_TRIGGER_POST,
},
.dynamic = 1,
.dpcm_playback = 1,
.ops = &mt8195_playback_ops,
SND_SOC_DAILINK_REG(DL8_FE),
},
[DAI_LINK_DL10_FE] = {
.name = "DL10_FE",
.stream_name = "DL10 Playback",
.trigger = {
SND_SOC_DPCM_TRIGGER_POST,
SND_SOC_DPCM_TRIGGER_POST,
},
.dynamic = 1,
.dpcm_playback = 1,
.ops = &mt8195_hdmitx_dptx_playback_ops,
SND_SOC_DAILINK_REG(DL10_FE),
},
[DAI_LINK_DL11_FE] = {
.name = "DL11_FE",
.stream_name = "DL11 Playback",
.trigger = {
SND_SOC_DPCM_TRIGGER_POST,
SND_SOC_DPCM_TRIGGER_POST,
},
.dynamic = 1,
.dpcm_playback = 1,
.ops = &mt8195_playback_ops,
SND_SOC_DAILINK_REG(DL11_FE),
},
[DAI_LINK_UL1_FE] = {
.name = "UL1_FE",
.stream_name = "UL1 Capture",
.trigger = {
SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE,
},
.dynamic = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(UL1_FE),
},
[DAI_LINK_UL2_FE] = {
.name = "UL2_FE",
.stream_name = "UL2 Capture",
.trigger = {
SND_SOC_DPCM_TRIGGER_POST,
SND_SOC_DPCM_TRIGGER_POST,
},
.dynamic = 1,
.dpcm_capture = 1,
.ops = &mt8195_capture_ops,
SND_SOC_DAILINK_REG(UL2_FE),
},
[DAI_LINK_UL3_FE] = {
.name = "UL3_FE",
.stream_name = "UL3 Capture",
.trigger = {
SND_SOC_DPCM_TRIGGER_POST,
SND_SOC_DPCM_TRIGGER_POST,
},
.dynamic = 1,
.dpcm_capture = 1,
.ops = &mt8195_capture_ops,
SND_SOC_DAILINK_REG(UL3_FE),
},
[DAI_LINK_UL4_FE] = {
.name = "UL4_FE",
.stream_name = "UL4 Capture",
.trigger = {
SND_SOC_DPCM_TRIGGER_POST,
SND_SOC_DPCM_TRIGGER_POST,
},
.dynamic = 1,
.dpcm_capture = 1,
.ops = &mt8195_capture_ops,
SND_SOC_DAILINK_REG(UL4_FE),
},
[DAI_LINK_UL5_FE] = {
.name = "UL5_FE",
.stream_name = "UL5 Capture",
.trigger = {
SND_SOC_DPCM_TRIGGER_POST,
SND_SOC_DPCM_TRIGGER_POST,
},
.dynamic = 1,
.dpcm_capture = 1,
.ops = &mt8195_capture_ops,
SND_SOC_DAILINK_REG(UL5_FE),
},
[DAI_LINK_UL6_FE] = {
.name = "UL6_FE",
.stream_name = "UL6 Capture",
.trigger = {
SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE,
},
.dynamic = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(UL6_FE),
},
[DAI_LINK_UL8_FE] = {
.name = "UL8_FE",
.stream_name = "UL8 Capture",
.trigger = {
SND_SOC_DPCM_TRIGGER_POST,
SND_SOC_DPCM_TRIGGER_POST,
},
.dynamic = 1,
.dpcm_capture = 1,
.ops = &mt8195_capture_ops,
SND_SOC_DAILINK_REG(UL8_FE),
},
[DAI_LINK_UL9_FE] = {
.name = "UL9_FE",
.stream_name = "UL9 Capture",
.trigger = {
SND_SOC_DPCM_TRIGGER_POST,
SND_SOC_DPCM_TRIGGER_POST,
},
.dynamic = 1,
.dpcm_capture = 1,
.ops = &mt8195_capture_ops,
SND_SOC_DAILINK_REG(UL9_FE),
},
[DAI_LINK_UL10_FE] = {
.name = "UL10_FE",
.stream_name = "UL10 Capture",
.trigger = {
SND_SOC_DPCM_TRIGGER_POST,
SND_SOC_DPCM_TRIGGER_POST,
},
.dynamic = 1,
.dpcm_capture = 1,
.ops = &mt8195_capture_ops,
SND_SOC_DAILINK_REG(UL10_FE),
},
/* BE */
[DAI_LINK_DL_SRC_BE] = {
.name = "DL_SRC_BE",
.no_pcm = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(DL_SRC_BE),
},
[DAI_LINK_DPTX_BE] = {
.name = "DPTX_BE",
.no_pcm = 1,
.dpcm_playback = 1,
.ops = &mt8195_dptx_ops,
.be_hw_params_fixup = mt8195_dptx_hw_params_fixup,
SND_SOC_DAILINK_REG(DPTX_BE),
},
[DAI_LINK_ETDM1_IN_BE] = {
.name = "ETDM1_IN_BE",
.no_pcm = 1,
.dai_fmt = SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(ETDM1_IN_BE),
},
[DAI_LINK_ETDM2_IN_BE] = {
.name = "ETDM2_IN_BE",
.no_pcm = 1,
.dai_fmt = SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS,
.dpcm_capture = 1,
.init = mt8195_rt5682_init,
.ops = &mt8195_rt5682_etdm_ops,
.be_hw_params_fixup = mt8195_etdm_hw_params_fixup,
SND_SOC_DAILINK_REG(ETDM2_IN_BE),
},
[DAI_LINK_ETDM1_OUT_BE] = {
.name = "ETDM1_OUT_BE",
.no_pcm = 1,
.dai_fmt = SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS,
.dpcm_playback = 1,
.ops = &mt8195_rt5682_etdm_ops,
.be_hw_params_fixup = mt8195_etdm_hw_params_fixup,
SND_SOC_DAILINK_REG(ETDM1_OUT_BE),
},
[DAI_LINK_ETDM2_OUT_BE] = {
.name = "ETDM2_OUT_BE",
.no_pcm = 1,
.dai_fmt = SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(ETDM2_OUT_BE),
},
[DAI_LINK_ETDM3_OUT_BE] = {
.name = "ETDM3_OUT_BE",
.no_pcm = 1,
.dai_fmt = SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(ETDM3_OUT_BE),
},
[DAI_LINK_PCM1_BE] = {
.name = "PCM1_BE",
.no_pcm = 1,
.dai_fmt = SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS,
.dpcm_playback = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(PCM1_BE),
},
[DAI_LINK_UL_SRC1_BE] = {
.name = "UL_SRC1_BE",
.no_pcm = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(UL_SRC1_BE),
},
[DAI_LINK_UL_SRC2_BE] = {
.name = "UL_SRC2_BE",
.no_pcm = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(UL_SRC2_BE),
},
/* SOF BE */
[DAI_LINK_SOF_DL2_BE] = {
.name = "AFE_SOF_DL2",
.no_pcm = 1,
.dpcm_playback = 1,
.ops = &mt8195_sof_be_ops,
SND_SOC_DAILINK_REG(AFE_SOF_DL2),
},
[DAI_LINK_SOF_DL3_BE] = {
.name = "AFE_SOF_DL3",
.no_pcm = 1,
.dpcm_playback = 1,
.ops = &mt8195_sof_be_ops,
SND_SOC_DAILINK_REG(AFE_SOF_DL3),
},
[DAI_LINK_SOF_UL4_BE] = {
.name = "AFE_SOF_UL4",
.no_pcm = 1,
.dpcm_capture = 1,
.ops = &mt8195_sof_be_ops,
SND_SOC_DAILINK_REG(AFE_SOF_UL4),
},
[DAI_LINK_SOF_UL5_BE] = {
.name = "AFE_SOF_UL5",
.no_pcm = 1,
.dpcm_capture = 1,
.ops = &mt8195_sof_be_ops,
SND_SOC_DAILINK_REG(AFE_SOF_UL5),
},
};
static struct snd_soc_codec_conf rt1011_codec_conf[] = {
{
.dlc = COMP_CODEC_CONF(RT1011_DEV0_NAME),
.name_prefix = "Left",
},
{
.dlc = COMP_CODEC_CONF(RT1011_DEV1_NAME),
.name_prefix = "Right",
},
};
static struct snd_soc_codec_conf max98390_codec_conf[] = {
{
.dlc = COMP_CODEC_CONF(MAX98390_DEV0_NAME),
.name_prefix = "Right",
},
{
.dlc = COMP_CODEC_CONF(MAX98390_DEV1_NAME),
.name_prefix = "Left",
},
};
static struct snd_soc_card mt8195_mt6359_soc_card = {
.owner = THIS_MODULE,
.dai_link = mt8195_mt6359_dai_links,
.num_links = ARRAY_SIZE(mt8195_mt6359_dai_links),
.controls = mt8195_mt6359_controls,
.num_controls = ARRAY_SIZE(mt8195_mt6359_controls),
.dapm_widgets = mt8195_mt6359_widgets,
.num_dapm_widgets = ARRAY_SIZE(mt8195_mt6359_widgets),
.dapm_routes = mt8195_mt6359_routes,
.num_dapm_routes = ARRAY_SIZE(mt8195_mt6359_routes),
.set_bias_level_post = mt8195_set_bias_level_post,
};
/* fixup the BE DAI link to match any values from topology */
static int mt8195_dai_link_fixup(struct snd_soc_pcm_runtime *rtd,
struct snd_pcm_hw_params *params)
{
int ret;
ret = mtk_sof_dai_link_fixup(rtd, params);
if (!strcmp(rtd->dai_link->name, "ETDM2_IN_BE") ||
!strcmp(rtd->dai_link->name, "ETDM1_OUT_BE")) {
mt8195_etdm_hw_params_fixup(rtd, params);
}
return ret;
}
static int mt8195_mt6359_dev_probe(struct platform_device *pdev)
{
struct snd_soc_card *card = &mt8195_mt6359_soc_card;
struct snd_soc_dai_link *dai_link;
struct mtk_soc_card_data *soc_card_data;
struct mt8195_mt6359_priv *mach_priv;
struct device_node *platform_node, *adsp_node, *dp_node, *hdmi_node;
struct mt8195_card_data *card_data;
int is5682s = 0;
int init6359 = 0;
int sof_on = 0;
int ret, i;
card_data = (struct mt8195_card_data *)of_device_get_match_data(&pdev->dev);
card->dev = &pdev->dev;
ret = snd_soc_of_parse_card_name(card, "model");
if (ret) {
dev_err(&pdev->dev, "%s new card name parsing error %d\n",
__func__, ret);
return ret;
}
if (!card->name)
card->name = card_data->name;
if (strstr(card->name, "_5682s"))
is5682s = 1;
soc_card_data = devm_kzalloc(&pdev->dev, sizeof(*card_data), GFP_KERNEL);
if (!soc_card_data)
return -ENOMEM;
mach_priv = devm_kzalloc(&pdev->dev, sizeof(*mach_priv), GFP_KERNEL);
if (!mach_priv)
return -ENOMEM;
soc_card_data->mach_priv = mach_priv;
adsp_node = of_parse_phandle(pdev->dev.of_node, "mediatek,adsp", 0);
if (adsp_node) {
struct mtk_sof_priv *sof_priv;
sof_priv = devm_kzalloc(&pdev->dev, sizeof(*sof_priv), GFP_KERNEL);
if (!sof_priv) {
ret = -ENOMEM;
goto err_kzalloc;
}
sof_priv->conn_streams = g_sof_conn_streams;
sof_priv->num_streams = ARRAY_SIZE(g_sof_conn_streams);
sof_priv->sof_dai_link_fixup = mt8195_dai_link_fixup;
soc_card_data->sof_priv = sof_priv;
card->probe = mtk_sof_card_probe;
card->late_probe = mtk_sof_card_late_probe;
if (!card->topology_shortname_created) {
snprintf(card->topology_shortname, 32, "sof-%s", card->name);
card->topology_shortname_created = true;
}
card->name = card->topology_shortname;
sof_on = 1;
}
if (of_property_read_bool(pdev->dev.of_node, "mediatek,dai-link")) {
ret = mtk_sof_dailink_parse_of(card, pdev->dev.of_node,
"mediatek,dai-link",
mt8195_mt6359_dai_links,
ARRAY_SIZE(mt8195_mt6359_dai_links));
if (ret) {
dev_dbg(&pdev->dev, "Parse dai-link fail\n");
goto err_parse_of;
}
} else {
if (!sof_on)
card->num_links = DAI_LINK_REGULAR_NUM;
}
platform_node = of_parse_phandle(pdev->dev.of_node,
"mediatek,platform", 0);
if (!platform_node) {
dev_dbg(&pdev->dev, "Property 'platform' missing or invalid\n");
ret = -EINVAL;
goto err_platform_node;
}
dp_node = of_parse_phandle(pdev->dev.of_node, "mediatek,dptx-codec", 0);
hdmi_node = of_parse_phandle(pdev->dev.of_node,
"mediatek,hdmi-codec", 0);
for_each_card_prelinks(card, i, dai_link) {
if (!dai_link->platforms->name) {
if (!strncmp(dai_link->name, "AFE_SOF", strlen("AFE_SOF")) && sof_on)
dai_link->platforms->of_node = adsp_node;
else
dai_link->platforms->of_node = platform_node;
}
if (strcmp(dai_link->name, "DPTX_BE") == 0) {
if (!dp_node) {
dev_dbg(&pdev->dev, "No property 'dptx-codec'\n");
} else {
dai_link->codecs->of_node = dp_node;
dai_link->codecs->name = NULL;
dai_link->codecs->dai_name = "i2s-hifi";
dai_link->init = mt8195_dptx_codec_init;
}
} else if (strcmp(dai_link->name, "ETDM3_OUT_BE") == 0) {
if (!hdmi_node) {
dev_dbg(&pdev->dev, "No property 'hdmi-codec'\n");
} else {
dai_link->codecs->of_node = hdmi_node;
dai_link->codecs->name = NULL;
dai_link->codecs->dai_name = "i2s-hifi";
dai_link->init = mt8195_hdmi_codec_init;
}
} else if (strcmp(dai_link->name, "ETDM1_OUT_BE") == 0 ||
strcmp(dai_link->name, "ETDM2_IN_BE") == 0) {
dai_link->codecs->name =
is5682s ? RT5682S_DEV0_NAME : RT5682_DEV0_NAME;
dai_link->codecs->dai_name =
is5682s ? RT5682S_CODEC_DAI : RT5682_CODEC_DAI;
} else if (strcmp(dai_link->name, "DL_SRC_BE") == 0 ||
strcmp(dai_link->name, "UL_SRC1_BE") == 0 ||
strcmp(dai_link->name, "UL_SRC2_BE") == 0) {
if (!init6359) {
dai_link->init = mt8195_mt6359_init;
init6359 = 1;
}
} else if (strcmp(dai_link->name, "ETDM2_OUT_BE") == 0) {
switch (card_data->quirk) {
case RT1011_SPEAKER_AMP_PRESENT:
dai_link->codecs = rt1011_comps;
dai_link->num_codecs = ARRAY_SIZE(rt1011_comps);
dai_link->init = mt8195_rt1011_init;
dai_link->ops = &mt8195_rt1011_etdm_ops;
dai_link->be_hw_params_fixup = mt8195_etdm_hw_params_fixup;
card->codec_conf = rt1011_codec_conf;
card->num_configs = ARRAY_SIZE(rt1011_codec_conf);
break;
case RT1019_SPEAKER_AMP_PRESENT:
dai_link->codecs = rt1019_comps;
dai_link->num_codecs = ARRAY_SIZE(rt1019_comps);
dai_link->init = mt8195_rt1019_init;
break;
case MAX98390_SPEAKER_AMP_PRESENT:
dai_link->codecs = max98390_comps;
dai_link->num_codecs = ARRAY_SIZE(max98390_comps);
dai_link->init = mt8195_max98390_init;
card->codec_conf = max98390_codec_conf;
card->num_configs = ARRAY_SIZE(max98390_codec_conf);
break;
default:
break;
}
}
}
snd_soc_card_set_drvdata(card, soc_card_data);
ret = devm_snd_soc_register_card(&pdev->dev, card);
of_node_put(platform_node);
of_node_put(dp_node);
of_node_put(hdmi_node);
err_kzalloc:
err_parse_of:
err_platform_node:
of_node_put(adsp_node);
return ret;
}
static struct mt8195_card_data mt8195_mt6359_rt1019_rt5682_card = {
.name = "mt8195_r1019_5682",
.quirk = RT1019_SPEAKER_AMP_PRESENT,
};
static struct mt8195_card_data mt8195_mt6359_rt1011_rt5682_card = {
.name = "mt8195_r1011_5682",
.quirk = RT1011_SPEAKER_AMP_PRESENT,
};
static struct mt8195_card_data mt8195_mt6359_max98390_rt5682_card = {
.name = "mt8195_m98390_r5682",
.quirk = MAX98390_SPEAKER_AMP_PRESENT,
};
static const struct of_device_id mt8195_mt6359_dt_match[] = {
{
.compatible = "mediatek,mt8195_mt6359_rt1019_rt5682",
.data = &mt8195_mt6359_rt1019_rt5682_card,
},
{
.compatible = "mediatek,mt8195_mt6359_rt1011_rt5682",
.data = &mt8195_mt6359_rt1011_rt5682_card,
},
{
.compatible = "mediatek,mt8195_mt6359_max98390_rt5682",
.data = &mt8195_mt6359_max98390_rt5682_card,
},
{},
};
MODULE_DEVICE_TABLE(of, mt8195_mt6359_dt_match);
static struct platform_driver mt8195_mt6359_driver = {
.driver = {
.name = "mt8195_mt6359",
.of_match_table = mt8195_mt6359_dt_match,
.pm = &snd_soc_pm_ops,
},
.probe = mt8195_mt6359_dev_probe,
};
module_platform_driver(mt8195_mt6359_driver);
/* Module information */
MODULE_DESCRIPTION("MT8195-MT6359 ALSA SoC machine driver");
MODULE_AUTHOR("Trevor Wu <[email protected]>");
MODULE_AUTHOR("YC Hung <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("mt8195_mt6359 soc card");
| linux-master | sound/soc/mediatek/mt8195/mt8195-mt6359.c |
// SPDX-License-Identifier: GPL-2.0
/*
* MediaTek ALSA SoC Audio DAI PCM I/F Control
*
* Copyright (c) 2020 MediaTek Inc.
* Author: Bicycle Tsai <[email protected]>
* Trevor Wu <[email protected]>
*/
#include <linux/regmap.h>
#include <sound/pcm_params.h>
#include "mt8195-afe-clk.h"
#include "mt8195-afe-common.h"
#include "mt8195-reg.h"
enum {
MTK_DAI_PCM_FMT_I2S,
MTK_DAI_PCM_FMT_EIAJ,
MTK_DAI_PCM_FMT_MODEA,
MTK_DAI_PCM_FMT_MODEB,
};
enum {
MTK_DAI_PCM_CLK_A1SYS,
MTK_DAI_PCM_CLK_A2SYS,
MTK_DAI_PCM_CLK_26M_48K,
MTK_DAI_PCM_CLK_26M_441K,
};
struct mtk_dai_pcm_rate {
unsigned int rate;
unsigned int reg_value;
};
struct mtk_dai_pcmif_priv {
unsigned int slave_mode;
unsigned int lrck_inv;
unsigned int bck_inv;
unsigned int format;
};
static const struct mtk_dai_pcm_rate mtk_dai_pcm_rates[] = {
{ .rate = 8000, .reg_value = 0, },
{ .rate = 16000, .reg_value = 1, },
{ .rate = 32000, .reg_value = 2, },
{ .rate = 48000, .reg_value = 3, },
{ .rate = 11025, .reg_value = 1, },
{ .rate = 22050, .reg_value = 2, },
{ .rate = 44100, .reg_value = 3, },
};
static int mtk_dai_pcm_mode(unsigned int rate)
{
int i;
for (i = 0; i < ARRAY_SIZE(mtk_dai_pcm_rates); i++)
if (mtk_dai_pcm_rates[i].rate == rate)
return mtk_dai_pcm_rates[i].reg_value;
return -EINVAL;
}
static const struct snd_kcontrol_new mtk_dai_pcm_o000_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN0, 0, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN0_2, 6, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_pcm_o001_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN1, 1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN1_2, 7, 1, 0),
};
static const struct snd_soc_dapm_widget mtk_dai_pcm_widgets[] = {
SND_SOC_DAPM_MIXER("I002", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I003", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("O000", SND_SOC_NOPM, 0, 0,
mtk_dai_pcm_o000_mix,
ARRAY_SIZE(mtk_dai_pcm_o000_mix)),
SND_SOC_DAPM_MIXER("O001", SND_SOC_NOPM, 0, 0,
mtk_dai_pcm_o001_mix,
ARRAY_SIZE(mtk_dai_pcm_o001_mix)),
SND_SOC_DAPM_SUPPLY("PCM_EN", PCM_INTF_CON1,
PCM_INTF_CON1_PCM_EN_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_INPUT("PCM1_INPUT"),
SND_SOC_DAPM_OUTPUT("PCM1_OUTPUT"),
SND_SOC_DAPM_CLOCK_SUPPLY("aud_asrc11"),
SND_SOC_DAPM_CLOCK_SUPPLY("aud_asrc12"),
SND_SOC_DAPM_CLOCK_SUPPLY("aud_pcmif"),
};
static const struct snd_soc_dapm_route mtk_dai_pcm_routes[] = {
{"I002", NULL, "PCM1 Capture"},
{"I003", NULL, "PCM1 Capture"},
{"O000", "I000 Switch", "I000"},
{"O001", "I001 Switch", "I001"},
{"O000", "I070 Switch", "I070"},
{"O001", "I071 Switch", "I071"},
{"PCM1 Playback", NULL, "O000"},
{"PCM1 Playback", NULL, "O001"},
{"PCM1 Playback", NULL, "PCM_EN"},
{"PCM1 Playback", NULL, "aud_asrc12"},
{"PCM1 Playback", NULL, "aud_pcmif"},
{"PCM1 Capture", NULL, "PCM_EN"},
{"PCM1 Capture", NULL, "aud_asrc11"},
{"PCM1 Capture", NULL, "aud_pcmif"},
{"PCM1_OUTPUT", NULL, "PCM1 Playback"},
{"PCM1 Capture", NULL, "PCM1_INPUT"},
};
static int mtk_dai_pcm_configure(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_pcm_runtime * const runtime = substream->runtime;
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_pcmif_priv *pcmif_priv;
unsigned int slave_mode;
unsigned int lrck_inv;
unsigned int bck_inv;
unsigned int fmt;
unsigned int bit_width = dai->sample_bits;
unsigned int val = 0;
unsigned int mask = 0;
int fs = 0;
int mode = 0;
if (dai->id != MT8195_AFE_IO_PCM)
return -EINVAL;
pcmif_priv = afe_priv->dai_priv[dai->id];
slave_mode = pcmif_priv->slave_mode;
lrck_inv = pcmif_priv->lrck_inv;
bck_inv = pcmif_priv->bck_inv;
fmt = pcmif_priv->format;
/* sync freq mode */
fs = mt8195_afe_fs_timing(runtime->rate);
if (fs < 0)
return -EINVAL;
val |= PCM_INTF_CON2_SYNC_FREQ_MODE(fs);
mask |= PCM_INTF_CON2_SYNC_FREQ_MODE_MASK;
/* clk domain sel */
if (runtime->rate % 8000)
val |= PCM_INTF_CON2_CLK_DOMAIN_SEL(MTK_DAI_PCM_CLK_26M_441K);
else
val |= PCM_INTF_CON2_CLK_DOMAIN_SEL(MTK_DAI_PCM_CLK_26M_48K);
mask |= PCM_INTF_CON2_CLK_DOMAIN_SEL_MASK;
regmap_update_bits(afe->regmap, PCM_INTF_CON2, mask, val);
val = 0;
mask = 0;
/* pcm mode */
mode = mtk_dai_pcm_mode(runtime->rate);
if (mode < 0)
return -EINVAL;
val |= PCM_INTF_CON1_PCM_MODE(mode);
mask |= PCM_INTF_CON1_PCM_MODE_MASK;
/* pcm format */
val |= PCM_INTF_CON1_PCM_FMT(fmt);
mask |= PCM_INTF_CON1_PCM_FMT_MASK;
/* pcm sync length */
if (fmt == MTK_DAI_PCM_FMT_MODEA ||
fmt == MTK_DAI_PCM_FMT_MODEB)
val |= PCM_INTF_CON1_SYNC_LENGTH(1);
else
val |= PCM_INTF_CON1_SYNC_LENGTH(bit_width);
mask |= PCM_INTF_CON1_SYNC_LENGTH_MASK;
/* pcm bits, word length */
if (bit_width > 16) {
val |= PCM_INTF_CON1_PCM_24BIT;
val |= PCM_INTF_CON1_PCM_WLEN_64BCK;
} else {
val |= PCM_INTF_CON1_PCM_16BIT;
val |= PCM_INTF_CON1_PCM_WLEN_32BCK;
}
mask |= PCM_INTF_CON1_PCM_BIT_MASK;
mask |= PCM_INTF_CON1_PCM_WLEN_MASK;
/* master/slave */
if (!slave_mode) {
val |= PCM_INTF_CON1_PCM_MASTER;
if (lrck_inv)
val |= PCM_INTF_CON1_SYNC_OUT_INV;
if (bck_inv)
val |= PCM_INTF_CON1_BCLK_OUT_INV;
mask |= PCM_INTF_CON1_CLK_OUT_INV_MASK;
} else {
val |= PCM_INTF_CON1_PCM_SLAVE;
if (lrck_inv)
val |= PCM_INTF_CON1_SYNC_IN_INV;
if (bck_inv)
val |= PCM_INTF_CON1_BCLK_IN_INV;
mask |= PCM_INTF_CON1_CLK_IN_INV_MASK;
/* TODO: add asrc setting for slave mode */
}
mask |= PCM_INTF_CON1_PCM_M_S_MASK;
regmap_update_bits(afe->regmap, PCM_INTF_CON1, mask, val);
return 0;
}
/* dai ops */
static int mtk_dai_pcm_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_dapm_widget *p = snd_soc_dai_get_widget_playback(dai);
struct snd_soc_dapm_widget *c = snd_soc_dai_get_widget_capture(dai);
dev_dbg(dai->dev, "%s(), id %d, stream %d, widget active p %d, c %d\n",
__func__, dai->id, substream->stream,
p->active, c->active);
if (p->active || c->active)
return 0;
return mtk_dai_pcm_configure(substream, dai);
}
static int mtk_dai_pcm_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_pcmif_priv *pcmif_priv;
dev_dbg(dai->dev, "%s fmt 0x%x\n", __func__, fmt);
if (dai->id != MT8195_AFE_IO_PCM)
return -EINVAL;
pcmif_priv = afe_priv->dai_priv[dai->id];
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
pcmif_priv->format = MTK_DAI_PCM_FMT_I2S;
break;
case SND_SOC_DAIFMT_DSP_A:
pcmif_priv->format = MTK_DAI_PCM_FMT_MODEA;
break;
case SND_SOC_DAIFMT_DSP_B:
pcmif_priv->format = MTK_DAI_PCM_FMT_MODEB;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
pcmif_priv->bck_inv = 0;
pcmif_priv->lrck_inv = 0;
break;
case SND_SOC_DAIFMT_NB_IF:
pcmif_priv->bck_inv = 0;
pcmif_priv->lrck_inv = 1;
break;
case SND_SOC_DAIFMT_IB_NF:
pcmif_priv->bck_inv = 1;
pcmif_priv->lrck_inv = 0;
break;
case SND_SOC_DAIFMT_IB_IF:
pcmif_priv->bck_inv = 1;
pcmif_priv->lrck_inv = 1;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BC_FC:
pcmif_priv->slave_mode = 1;
break;
case SND_SOC_DAIFMT_BP_FP:
pcmif_priv->slave_mode = 0;
break;
default:
return -EINVAL;
}
return 0;
}
static const struct snd_soc_dai_ops mtk_dai_pcm_ops = {
.prepare = mtk_dai_pcm_prepare,
.set_fmt = mtk_dai_pcm_set_fmt,
};
/* dai driver */
#define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000)
#define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver mtk_dai_pcm_driver[] = {
{
.name = "PCM1",
.id = MT8195_AFE_IO_PCM,
.playback = {
.stream_name = "PCM1 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.capture = {
.stream_name = "PCM1 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_dai_pcm_ops,
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
},
};
static int init_pcmif_priv_data(struct mtk_base_afe *afe)
{
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_pcmif_priv *pcmif_priv;
pcmif_priv = devm_kzalloc(afe->dev, sizeof(struct mtk_dai_pcmif_priv),
GFP_KERNEL);
if (!pcmif_priv)
return -ENOMEM;
afe_priv->dai_priv[MT8195_AFE_IO_PCM] = pcmif_priv;
return 0;
}
int mt8195_dai_pcm_register(struct mtk_base_afe *afe)
{
struct mtk_base_afe_dai *dai;
dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
if (!dai)
return -ENOMEM;
list_add(&dai->list, &afe->sub_dais);
dai->dai_drivers = mtk_dai_pcm_driver;
dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_pcm_driver);
dai->dapm_widgets = mtk_dai_pcm_widgets;
dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_pcm_widgets);
dai->dapm_routes = mtk_dai_pcm_routes;
dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_pcm_routes);
return init_pcmif_priv_data(afe);
}
| linux-master | sound/soc/mediatek/mt8195/mt8195-dai-pcm.c |
// SPDX-License-Identifier: GPL-2.0
/*
* mt8195-audsys-clk.h -- Mediatek 8195 audsys clock control
*
* Copyright (c) 2021 MediaTek Inc.
* Author: Trevor Wu <[email protected]>
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#include "mt8195-afe-common.h"
#include "mt8195-audsys-clk.h"
#include "mt8195-audsys-clkid.h"
#include "mt8195-reg.h"
struct afe_gate {
int id;
const char *name;
const char *parent_name;
int reg;
u8 bit;
const struct clk_ops *ops;
unsigned long flags;
u8 cg_flags;
};
#define GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, _flags, _cgflags) {\
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.reg = _reg, \
.bit = _bit, \
.flags = _flags, \
.cg_flags = _cgflags, \
}
#define GATE_AFE(_id, _name, _parent, _reg, _bit) \
GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, \
CLK_SET_RATE_PARENT, CLK_GATE_SET_TO_DISABLE)
#define GATE_AUD0(_id, _name, _parent, _bit) \
GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON0, _bit)
#define GATE_AUD1(_id, _name, _parent, _bit) \
GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON1, _bit)
#define GATE_AUD3(_id, _name, _parent, _bit) \
GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON3, _bit)
#define GATE_AUD4(_id, _name, _parent, _bit) \
GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON4, _bit)
#define GATE_AUD5(_id, _name, _parent, _bit) \
GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON5, _bit)
#define GATE_AUD6(_id, _name, _parent, _bit) \
GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON6, _bit)
static const struct afe_gate aud_clks[CLK_AUD_NR_CLK] = {
/* AUD0 */
GATE_AUD0(CLK_AUD_AFE, "aud_afe", "top_a1sys_hp", 2),
GATE_AUD0(CLK_AUD_LRCK_CNT, "aud_lrck_cnt", "top_a1sys_hp", 4),
GATE_AUD0(CLK_AUD_SPDIFIN_TUNER_APLL, "aud_spdifin_tuner_apll", "top_apll4", 10),
GATE_AUD0(CLK_AUD_SPDIFIN_TUNER_DBG, "aud_spdifin_tuner_dbg", "top_apll4", 11),
GATE_AUD0(CLK_AUD_UL_TML, "aud_ul_tml", "top_a1sys_hp", 18),
GATE_AUD0(CLK_AUD_APLL1_TUNER, "aud_apll1_tuner", "top_apll1", 19),
GATE_AUD0(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner", "top_apll2", 20),
GATE_AUD0(CLK_AUD_TOP0_SPDF, "aud_top0_spdf", "top_aud_iec_clk", 21),
GATE_AUD0(CLK_AUD_APLL, "aud_apll", "top_apll1", 23),
GATE_AUD0(CLK_AUD_APLL2, "aud_apll2", "top_apll2", 24),
GATE_AUD0(CLK_AUD_DAC, "aud_dac", "top_a1sys_hp", 25),
GATE_AUD0(CLK_AUD_DAC_PREDIS, "aud_dac_predis", "top_a1sys_hp", 26),
GATE_AUD0(CLK_AUD_TML, "aud_tml", "top_a1sys_hp", 27),
GATE_AUD0(CLK_AUD_ADC, "aud_adc", "top_a1sys_hp", 28),
GATE_AUD0(CLK_AUD_DAC_HIRES, "aud_dac_hires", "top_audio_h", 31),
/* AUD1 */
GATE_AUD1(CLK_AUD_A1SYS_HP, "aud_a1sys_hp", "top_a1sys_hp", 2),
GATE_AUD1(CLK_AUD_AFE_DMIC1, "aud_afe_dmic1", "top_a1sys_hp", 10),
GATE_AUD1(CLK_AUD_AFE_DMIC2, "aud_afe_dmic2", "top_a1sys_hp", 11),
GATE_AUD1(CLK_AUD_AFE_DMIC3, "aud_afe_dmic3", "top_a1sys_hp", 12),
GATE_AUD1(CLK_AUD_AFE_DMIC4, "aud_afe_dmic4", "top_a1sys_hp", 13),
GATE_AUD1(CLK_AUD_AFE_26M_DMIC_TM, "aud_afe_26m_dmic_tm", "top_a1sys_hp", 14),
GATE_AUD1(CLK_AUD_UL_TML_HIRES, "aud_ul_tml_hires", "top_audio_h", 16),
GATE_AUD1(CLK_AUD_ADC_HIRES, "aud_adc_hires", "top_audio_h", 17),
GATE_AUD1(CLK_AUD_ADDA6_ADC, "aud_adda6_adc", "top_a1sys_hp", 18),
GATE_AUD1(CLK_AUD_ADDA6_ADC_HIRES, "aud_adda6_adc_hires", "top_audio_h", 19),
/* AUD3 */
GATE_AUD3(CLK_AUD_LINEIN_TUNER, "aud_linein_tuner", "top_apll5", 5),
GATE_AUD3(CLK_AUD_EARC_TUNER, "aud_earc_tuner", "top_apll3", 7),
/* AUD4 */
GATE_AUD4(CLK_AUD_I2SIN, "aud_i2sin", "top_a1sys_hp", 0),
GATE_AUD4(CLK_AUD_TDM_IN, "aud_tdm_in", "top_a1sys_hp", 1),
GATE_AUD4(CLK_AUD_I2S_OUT, "aud_i2s_out", "top_a1sys_hp", 6),
GATE_AUD4(CLK_AUD_TDM_OUT, "aud_tdm_out", "top_a1sys_hp", 7),
GATE_AUD4(CLK_AUD_HDMI_OUT, "aud_hdmi_out", "top_a1sys_hp", 8),
GATE_AUD4(CLK_AUD_ASRC11, "aud_asrc11", "top_a1sys_hp", 16),
GATE_AUD4(CLK_AUD_ASRC12, "aud_asrc12", "top_a1sys_hp", 17),
GATE_AUD4(CLK_AUD_MULTI_IN, "aud_multi_in", "mphone_slave_b", 19),
GATE_AUD4(CLK_AUD_INTDIR, "aud_intdir", "top_intdir", 20),
GATE_AUD4(CLK_AUD_A1SYS, "aud_a1sys", "top_a1sys_hp", 21),
GATE_AUD4(CLK_AUD_A2SYS, "aud_a2sys", "top_a2sys_hf", 22),
GATE_AUD4(CLK_AUD_PCMIF, "aud_pcmif", "top_a1sys_hp", 24),
GATE_AUD4(CLK_AUD_A3SYS, "aud_a3sys", "top_a3sys_hf", 30),
GATE_AUD4(CLK_AUD_A4SYS, "aud_a4sys", "top_a4sys_hf", 31),
/* AUD5 */
GATE_AUD5(CLK_AUD_MEMIF_UL1, "aud_memif_ul1", "top_a1sys_hp", 0),
GATE_AUD5(CLK_AUD_MEMIF_UL2, "aud_memif_ul2", "top_a1sys_hp", 1),
GATE_AUD5(CLK_AUD_MEMIF_UL3, "aud_memif_ul3", "top_a1sys_hp", 2),
GATE_AUD5(CLK_AUD_MEMIF_UL4, "aud_memif_ul4", "top_a1sys_hp", 3),
GATE_AUD5(CLK_AUD_MEMIF_UL5, "aud_memif_ul5", "top_a1sys_hp", 4),
GATE_AUD5(CLK_AUD_MEMIF_UL6, "aud_memif_ul6", "top_a1sys_hp", 5),
GATE_AUD5(CLK_AUD_MEMIF_UL8, "aud_memif_ul8", "top_a1sys_hp", 7),
GATE_AUD5(CLK_AUD_MEMIF_UL9, "aud_memif_ul9", "top_a1sys_hp", 8),
GATE_AUD5(CLK_AUD_MEMIF_UL10, "aud_memif_ul10", "top_a1sys_hp", 9),
GATE_AUD5(CLK_AUD_MEMIF_DL2, "aud_memif_dl2", "top_a1sys_hp", 18),
GATE_AUD5(CLK_AUD_MEMIF_DL3, "aud_memif_dl3", "top_a1sys_hp", 19),
GATE_AUD5(CLK_AUD_MEMIF_DL6, "aud_memif_dl6", "top_a1sys_hp", 22),
GATE_AUD5(CLK_AUD_MEMIF_DL7, "aud_memif_dl7", "top_a1sys_hp", 23),
GATE_AUD5(CLK_AUD_MEMIF_DL8, "aud_memif_dl8", "top_a1sys_hp", 24),
GATE_AUD5(CLK_AUD_MEMIF_DL10, "aud_memif_dl10", "top_a1sys_hp", 26),
GATE_AUD5(CLK_AUD_MEMIF_DL11, "aud_memif_dl11", "top_a1sys_hp", 27),
/* AUD6 */
GATE_AUD6(CLK_AUD_GASRC0, "aud_gasrc0", "top_asm_h", 0),
GATE_AUD6(CLK_AUD_GASRC1, "aud_gasrc1", "top_asm_h", 1),
GATE_AUD6(CLK_AUD_GASRC2, "aud_gasrc2", "top_asm_h", 2),
GATE_AUD6(CLK_AUD_GASRC3, "aud_gasrc3", "top_asm_h", 3),
GATE_AUD6(CLK_AUD_GASRC4, "aud_gasrc4", "top_asm_h", 4),
GATE_AUD6(CLK_AUD_GASRC5, "aud_gasrc5", "top_asm_h", 5),
GATE_AUD6(CLK_AUD_GASRC6, "aud_gasrc6", "top_asm_h", 6),
GATE_AUD6(CLK_AUD_GASRC7, "aud_gasrc7", "top_asm_h", 7),
GATE_AUD6(CLK_AUD_GASRC8, "aud_gasrc8", "top_asm_h", 8),
GATE_AUD6(CLK_AUD_GASRC9, "aud_gasrc9", "top_asm_h", 9),
GATE_AUD6(CLK_AUD_GASRC10, "aud_gasrc10", "top_asm_h", 10),
GATE_AUD6(CLK_AUD_GASRC11, "aud_gasrc11", "top_asm_h", 11),
GATE_AUD6(CLK_AUD_GASRC12, "aud_gasrc12", "top_asm_h", 12),
GATE_AUD6(CLK_AUD_GASRC13, "aud_gasrc13", "top_asm_h", 13),
GATE_AUD6(CLK_AUD_GASRC14, "aud_gasrc14", "top_asm_h", 14),
GATE_AUD6(CLK_AUD_GASRC15, "aud_gasrc15", "top_asm_h", 15),
GATE_AUD6(CLK_AUD_GASRC16, "aud_gasrc16", "top_asm_h", 16),
GATE_AUD6(CLK_AUD_GASRC17, "aud_gasrc17", "top_asm_h", 17),
GATE_AUD6(CLK_AUD_GASRC18, "aud_gasrc18", "top_asm_h", 18),
GATE_AUD6(CLK_AUD_GASRC19, "aud_gasrc19", "top_asm_h", 19),
};
static void mt8195_audsys_clk_unregister(void *data)
{
struct mtk_base_afe *afe = data;
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct clk *clk;
struct clk_lookup *cl;
int i;
if (!afe_priv)
return;
for (i = 0; i < CLK_AUD_NR_CLK; i++) {
cl = afe_priv->lookup[i];
if (!cl)
continue;
clk = cl->clk;
clk_unregister_gate(clk);
clkdev_drop(cl);
}
}
int mt8195_audsys_clk_register(struct mtk_base_afe *afe)
{
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct clk *clk;
struct clk_lookup *cl;
int i;
afe_priv->lookup = devm_kcalloc(afe->dev, CLK_AUD_NR_CLK,
sizeof(*afe_priv->lookup),
GFP_KERNEL);
if (!afe_priv->lookup)
return -ENOMEM;
for (i = 0; i < ARRAY_SIZE(aud_clks); i++) {
const struct afe_gate *gate = &aud_clks[i];
clk = clk_register_gate(afe->dev, gate->name, gate->parent_name,
gate->flags, afe->base_addr + gate->reg,
gate->bit, gate->cg_flags, NULL);
if (IS_ERR(clk)) {
dev_err(afe->dev, "Failed to register clk %s: %ld\n",
gate->name, PTR_ERR(clk));
continue;
}
/* add clk_lookup for devm_clk_get(SND_SOC_DAPM_CLOCK_SUPPLY) */
cl = kzalloc(sizeof(*cl), GFP_KERNEL);
if (!cl)
return -ENOMEM;
cl->clk = clk;
cl->con_id = gate->name;
cl->dev_id = dev_name(afe->dev);
clkdev_add(cl);
afe_priv->lookup[i] = cl;
}
return devm_add_action_or_reset(afe->dev, mt8195_audsys_clk_unregister, afe);
}
| linux-master | sound/soc/mediatek/mt8195/mt8195-audsys-clk.c |
// SPDX-License-Identifier: GPL-2.0
/*
* MediaTek ALSA SoC Audio DAI eTDM Control
*
* Copyright (c) 2021 MediaTek Inc.
* Author: Bicycle Tsai <[email protected]>
* Trevor Wu <[email protected]>
*/
#include <linux/delay.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <sound/pcm_params.h>
#include "mt8195-afe-clk.h"
#include "mt8195-afe-common.h"
#include "mt8195-reg.h"
#define MT8195_ETDM_MAX_CHANNELS 24
#define MT8195_ETDM_NORMAL_MAX_BCK_RATE 24576000
#define ETDM_TO_DAI_ID(x) ((x) + MT8195_AFE_IO_ETDM_START)
#define ENUM_TO_STR(x) #x
enum {
MTK_DAI_ETDM_FORMAT_I2S = 0,
MTK_DAI_ETDM_FORMAT_LJ,
MTK_DAI_ETDM_FORMAT_RJ,
MTK_DAI_ETDM_FORMAT_EIAJ,
MTK_DAI_ETDM_FORMAT_DSPA,
MTK_DAI_ETDM_FORMAT_DSPB,
};
enum {
MTK_DAI_ETDM_DATA_ONE_PIN = 0,
MTK_DAI_ETDM_DATA_MULTI_PIN,
};
enum {
ETDM_IN,
ETDM_OUT,
};
enum {
ETDM_IN_FROM_PAD,
ETDM_IN_FROM_ETDM_OUT1,
ETDM_IN_FROM_ETDM_OUT2,
};
enum {
ETDM_IN_SLAVE_FROM_PAD,
ETDM_IN_SLAVE_FROM_ETDM_OUT1,
ETDM_IN_SLAVE_FROM_ETDM_OUT2,
};
enum {
ETDM_OUT_SLAVE_FROM_PAD,
ETDM_OUT_SLAVE_FROM_ETDM_IN1,
ETDM_OUT_SLAVE_FROM_ETDM_IN2,
};
enum {
COWORK_ETDM_NONE = 0,
COWORK_ETDM_IN1_M = 2,
COWORK_ETDM_IN1_S = 3,
COWORK_ETDM_IN2_M = 4,
COWORK_ETDM_IN2_S = 5,
COWORK_ETDM_OUT1_M = 10,
COWORK_ETDM_OUT1_S = 11,
COWORK_ETDM_OUT2_M = 12,
COWORK_ETDM_OUT2_S = 13,
COWORK_ETDM_OUT3_M = 14,
COWORK_ETDM_OUT3_S = 15,
};
enum {
ETDM_RELATCH_TIMING_A1A2SYS,
ETDM_RELATCH_TIMING_A3SYS,
ETDM_RELATCH_TIMING_A4SYS,
};
enum {
ETDM_SYNC_NONE,
ETDM_SYNC_FROM_IN1,
ETDM_SYNC_FROM_IN2,
ETDM_SYNC_FROM_OUT1,
ETDM_SYNC_FROM_OUT2,
ETDM_SYNC_FROM_OUT3,
};
struct etdm_con_reg {
unsigned int con0;
unsigned int con1;
unsigned int con2;
unsigned int con3;
unsigned int con4;
unsigned int con5;
};
struct mtk_dai_etdm_rate {
unsigned int rate;
unsigned int reg_value;
};
struct mtk_dai_etdm_priv {
unsigned int clock_mode;
unsigned int data_mode;
bool slave_mode;
bool lrck_inv;
bool bck_inv;
unsigned int format;
unsigned int slots;
unsigned int lrck_width;
unsigned int mclk_freq;
unsigned int mclk_apll;
unsigned int mclk_dir;
int cowork_source_id; //dai id
unsigned int cowork_slv_count;
int cowork_slv_id[MT8195_AFE_IO_ETDM_NUM - 1]; //dai_id
bool in_disable_ch[MT8195_ETDM_MAX_CHANNELS];
unsigned int en_ref_cnt;
};
static const struct mtk_dai_etdm_rate mt8195_etdm_rates[] = {
{ .rate = 8000, .reg_value = 0, },
{ .rate = 12000, .reg_value = 1, },
{ .rate = 16000, .reg_value = 2, },
{ .rate = 24000, .reg_value = 3, },
{ .rate = 32000, .reg_value = 4, },
{ .rate = 48000, .reg_value = 5, },
{ .rate = 96000, .reg_value = 7, },
{ .rate = 192000, .reg_value = 9, },
{ .rate = 384000, .reg_value = 11, },
{ .rate = 11025, .reg_value = 16, },
{ .rate = 22050, .reg_value = 17, },
{ .rate = 44100, .reg_value = 18, },
{ .rate = 88200, .reg_value = 19, },
{ .rate = 176400, .reg_value = 20, },
{ .rate = 352800, .reg_value = 21, },
};
static bool mt8195_afe_etdm_is_valid(int id)
{
switch (id) {
case MT8195_AFE_IO_ETDM1_IN:
fallthrough;
case MT8195_AFE_IO_ETDM2_IN:
fallthrough;
case MT8195_AFE_IO_ETDM1_OUT:
fallthrough;
case MT8195_AFE_IO_ETDM2_OUT:
fallthrough;
case MT8195_AFE_IO_DPTX:
fallthrough;
case MT8195_AFE_IO_ETDM3_OUT:
return true;
default:
return false;
}
}
static bool mt8195_afe_hdmitx_dptx_is_valid(int id)
{
switch (id) {
case MT8195_AFE_IO_DPTX:
fallthrough;
case MT8195_AFE_IO_ETDM3_OUT:
return true;
default:
return false;
}
}
static int get_etdm_fs_timing(unsigned int rate)
{
int i;
for (i = 0; i < ARRAY_SIZE(mt8195_etdm_rates); i++)
if (mt8195_etdm_rates[i].rate == rate)
return mt8195_etdm_rates[i].reg_value;
return -EINVAL;
}
static unsigned int get_etdm_ch_fixup(unsigned int channels)
{
if (channels > 16)
return 24;
else if (channels > 8)
return 16;
else if (channels > 4)
return 8;
else if (channels > 2)
return 4;
else
return 2;
}
static int get_etdm_reg(unsigned int dai_id, struct etdm_con_reg *etdm_reg)
{
switch (dai_id) {
case MT8195_AFE_IO_ETDM1_IN:
etdm_reg->con0 = ETDM_IN1_CON0;
etdm_reg->con1 = ETDM_IN1_CON1;
etdm_reg->con2 = ETDM_IN1_CON2;
etdm_reg->con3 = ETDM_IN1_CON3;
etdm_reg->con4 = ETDM_IN1_CON4;
etdm_reg->con5 = ETDM_IN1_CON5;
break;
case MT8195_AFE_IO_ETDM2_IN:
etdm_reg->con0 = ETDM_IN2_CON0;
etdm_reg->con1 = ETDM_IN2_CON1;
etdm_reg->con2 = ETDM_IN2_CON2;
etdm_reg->con3 = ETDM_IN2_CON3;
etdm_reg->con4 = ETDM_IN2_CON4;
etdm_reg->con5 = ETDM_IN2_CON5;
break;
case MT8195_AFE_IO_ETDM1_OUT:
etdm_reg->con0 = ETDM_OUT1_CON0;
etdm_reg->con1 = ETDM_OUT1_CON1;
etdm_reg->con2 = ETDM_OUT1_CON2;
etdm_reg->con3 = ETDM_OUT1_CON3;
etdm_reg->con4 = ETDM_OUT1_CON4;
etdm_reg->con5 = ETDM_OUT1_CON5;
break;
case MT8195_AFE_IO_ETDM2_OUT:
etdm_reg->con0 = ETDM_OUT2_CON0;
etdm_reg->con1 = ETDM_OUT2_CON1;
etdm_reg->con2 = ETDM_OUT2_CON2;
etdm_reg->con3 = ETDM_OUT2_CON3;
etdm_reg->con4 = ETDM_OUT2_CON4;
etdm_reg->con5 = ETDM_OUT2_CON5;
break;
case MT8195_AFE_IO_ETDM3_OUT:
case MT8195_AFE_IO_DPTX:
etdm_reg->con0 = ETDM_OUT3_CON0;
etdm_reg->con1 = ETDM_OUT3_CON1;
etdm_reg->con2 = ETDM_OUT3_CON2;
etdm_reg->con3 = ETDM_OUT3_CON3;
etdm_reg->con4 = ETDM_OUT3_CON4;
etdm_reg->con5 = ETDM_OUT3_CON5;
break;
default:
return -EINVAL;
}
return 0;
}
static int get_etdm_dir(unsigned int dai_id)
{
switch (dai_id) {
case MT8195_AFE_IO_ETDM1_IN:
case MT8195_AFE_IO_ETDM2_IN:
return ETDM_IN;
case MT8195_AFE_IO_ETDM1_OUT:
case MT8195_AFE_IO_ETDM2_OUT:
case MT8195_AFE_IO_ETDM3_OUT:
return ETDM_OUT;
default:
return -EINVAL;
}
}
static int get_etdm_wlen(unsigned int bitwidth)
{
return bitwidth <= 16 ? 16 : 32;
}
static int is_cowork_mode(struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_etdm_priv *etdm_data;
if (!mt8195_afe_etdm_is_valid(dai->id))
return -EINVAL;
etdm_data = afe_priv->dai_priv[dai->id];
return (etdm_data->cowork_slv_count > 0 ||
etdm_data->cowork_source_id != COWORK_ETDM_NONE);
}
static int sync_to_dai_id(int source_sel)
{
switch (source_sel) {
case ETDM_SYNC_FROM_IN1:
return MT8195_AFE_IO_ETDM1_IN;
case ETDM_SYNC_FROM_IN2:
return MT8195_AFE_IO_ETDM2_IN;
case ETDM_SYNC_FROM_OUT1:
return MT8195_AFE_IO_ETDM1_OUT;
case ETDM_SYNC_FROM_OUT2:
return MT8195_AFE_IO_ETDM2_OUT;
case ETDM_SYNC_FROM_OUT3:
return MT8195_AFE_IO_ETDM3_OUT;
default:
return 0;
}
}
static int get_etdm_cowork_master_id(struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_etdm_priv *etdm_data;
int dai_id;
if (!mt8195_afe_etdm_is_valid(dai->id))
return -EINVAL;
etdm_data = afe_priv->dai_priv[dai->id];
dai_id = etdm_data->cowork_source_id;
if (dai_id == COWORK_ETDM_NONE)
dai_id = dai->id;
return dai_id;
}
static const struct snd_kcontrol_new mtk_dai_etdm_o048_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN48, 20, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN48, 22, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN48_1, 14, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN48_2, 6, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o049_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN49, 21, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN49, 23, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN49_1, 15, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN49_2, 7, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o050_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN50, 24, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN50_1, 16, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o051_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN51, 25, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN51_1, 17, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o052_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN52, 26, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN52_1, 18, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o053_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN53, 27, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN53_1, 19, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o054_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN54, 28, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN54_1, 20, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o055_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN55, 29, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN55_1, 21, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o056_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I030 Switch", AFE_CONN56, 30, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I054 Switch", AFE_CONN56_1, 22, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o057_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I031 Switch", AFE_CONN57, 31, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I055 Switch", AFE_CONN57_1, 23, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o058_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I032 Switch", AFE_CONN58_1, 0, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I056 Switch", AFE_CONN58_1, 24, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o059_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I033 Switch", AFE_CONN59_1, 1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I057 Switch", AFE_CONN59_1, 25, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o060_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I034 Switch", AFE_CONN60_1, 2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I058 Switch", AFE_CONN60_1, 26, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o061_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I035 Switch", AFE_CONN61_1, 3, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I059 Switch", AFE_CONN61_1, 27, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o062_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I036 Switch", AFE_CONN62_1, 4, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I060 Switch", AFE_CONN62_1, 28, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o063_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I037 Switch", AFE_CONN63_1, 5, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I061 Switch", AFE_CONN63_1, 29, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o064_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I038 Switch", AFE_CONN64_1, 6, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I062 Switch", AFE_CONN64_1, 30, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o065_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I039 Switch", AFE_CONN65_1, 7, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I063 Switch", AFE_CONN65_1, 31, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o066_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I040 Switch", AFE_CONN66_1, 8, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I064 Switch", AFE_CONN66_2, 0, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o067_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I041 Switch", AFE_CONN67_1, 9, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I065 Switch", AFE_CONN67_2, 1, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o068_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I042 Switch", AFE_CONN68_1, 10, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I066 Switch", AFE_CONN68_2, 2, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o069_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I043 Switch", AFE_CONN69_1, 11, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I067 Switch", AFE_CONN69_2, 3, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o070_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I044 Switch", AFE_CONN70_1, 12, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I068 Switch", AFE_CONN70_2, 4, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o071_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I045 Switch", AFE_CONN71_1, 13, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I069 Switch", AFE_CONN71_2, 5, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o072_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN72, 20, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN72, 22, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN72_1, 14, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN72_2, 6, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o073_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN73, 21, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN73, 23, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN73_1, 15, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN73_2, 7, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o074_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN74, 24, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN74_1, 16, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o075_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN75, 25, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN75_1, 17, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o076_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN76, 26, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN76_1, 18, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o077_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN77, 27, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN77_1, 19, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o078_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN78, 28, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN78_1, 20, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o079_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN79, 29, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN79_1, 21, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o080_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I030 Switch", AFE_CONN80, 30, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I054 Switch", AFE_CONN80_1, 22, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o081_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I031 Switch", AFE_CONN81, 31, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I055 Switch", AFE_CONN81_1, 23, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o082_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I032 Switch", AFE_CONN82_1, 0, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I056 Switch", AFE_CONN82_1, 24, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o083_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I033 Switch", AFE_CONN83_1, 1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I057 Switch", AFE_CONN83_1, 25, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o084_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I034 Switch", AFE_CONN84_1, 2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I058 Switch", AFE_CONN84_1, 26, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o085_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I035 Switch", AFE_CONN85_1, 3, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I059 Switch", AFE_CONN85_1, 27, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o086_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I036 Switch", AFE_CONN86_1, 4, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I060 Switch", AFE_CONN86_1, 28, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o087_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I037 Switch", AFE_CONN87_1, 5, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I061 Switch", AFE_CONN87_1, 29, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o088_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I038 Switch", AFE_CONN88_1, 6, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I062 Switch", AFE_CONN88_1, 30, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o089_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I039 Switch", AFE_CONN89_1, 7, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I063 Switch", AFE_CONN89_1, 31, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o090_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I040 Switch", AFE_CONN90_1, 8, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I064 Switch", AFE_CONN90_2, 0, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o091_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I041 Switch", AFE_CONN91_1, 9, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I065 Switch", AFE_CONN91_2, 1, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o092_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I042 Switch", AFE_CONN92_1, 10, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I066 Switch", AFE_CONN92_2, 2, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o093_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I043 Switch", AFE_CONN93_1, 11, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I067 Switch", AFE_CONN93_2, 3, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o094_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I044 Switch", AFE_CONN94_1, 12, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I068 Switch", AFE_CONN94_2, 4, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o095_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I045 Switch", AFE_CONN95_1, 13, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I069 Switch", AFE_CONN95_2, 5, 1, 0),
};
static const char * const mt8195_etdm_clk_src_sel_text[] = {
"26m",
"a1sys_a2sys",
"a3sys",
"a4sys",
};
static SOC_ENUM_SINGLE_EXT_DECL(etdmout_clk_src_enum,
mt8195_etdm_clk_src_sel_text);
static const char * const hdmitx_dptx_mux_map[] = {
"Disconnect", "Connect",
};
static int hdmitx_dptx_mux_map_value[] = {
0, 1,
};
/* HDMI_OUT_MUX */
static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(hdmi_out_mux_map_enum,
SND_SOC_NOPM,
0,
1,
hdmitx_dptx_mux_map,
hdmitx_dptx_mux_map_value);
static const struct snd_kcontrol_new hdmi_out_mux_control =
SOC_DAPM_ENUM("HDMI_OUT_MUX", hdmi_out_mux_map_enum);
/* DPTX_OUT_MUX */
static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(dptx_out_mux_map_enum,
SND_SOC_NOPM,
0,
1,
hdmitx_dptx_mux_map,
hdmitx_dptx_mux_map_value);
static const struct snd_kcontrol_new dptx_out_mux_control =
SOC_DAPM_ENUM("DPTX_OUT_MUX", dptx_out_mux_map_enum);
/* HDMI_CH0_MUX ~ HDMI_CH7_MUX */
static const char *const afe_conn_hdmi_mux_map[] = {
"CH0", "CH1", "CH2", "CH3", "CH4", "CH5", "CH6", "CH7",
};
static int afe_conn_hdmi_mux_map_value[] = {
0, 1, 2, 3, 4, 5, 6, 7,
};
static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch0_mux_map_enum,
AFE_TDMOUT_CONN0,
0,
0xf,
afe_conn_hdmi_mux_map,
afe_conn_hdmi_mux_map_value);
static const struct snd_kcontrol_new hdmi_ch0_mux_control =
SOC_DAPM_ENUM("HDMI_CH0_MUX", hdmi_ch0_mux_map_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch1_mux_map_enum,
AFE_TDMOUT_CONN0,
4,
0xf,
afe_conn_hdmi_mux_map,
afe_conn_hdmi_mux_map_value);
static const struct snd_kcontrol_new hdmi_ch1_mux_control =
SOC_DAPM_ENUM("HDMI_CH1_MUX", hdmi_ch1_mux_map_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch2_mux_map_enum,
AFE_TDMOUT_CONN0,
8,
0xf,
afe_conn_hdmi_mux_map,
afe_conn_hdmi_mux_map_value);
static const struct snd_kcontrol_new hdmi_ch2_mux_control =
SOC_DAPM_ENUM("HDMI_CH2_MUX", hdmi_ch2_mux_map_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch3_mux_map_enum,
AFE_TDMOUT_CONN0,
12,
0xf,
afe_conn_hdmi_mux_map,
afe_conn_hdmi_mux_map_value);
static const struct snd_kcontrol_new hdmi_ch3_mux_control =
SOC_DAPM_ENUM("HDMI_CH3_MUX", hdmi_ch3_mux_map_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch4_mux_map_enum,
AFE_TDMOUT_CONN0,
16,
0xf,
afe_conn_hdmi_mux_map,
afe_conn_hdmi_mux_map_value);
static const struct snd_kcontrol_new hdmi_ch4_mux_control =
SOC_DAPM_ENUM("HDMI_CH4_MUX", hdmi_ch4_mux_map_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch5_mux_map_enum,
AFE_TDMOUT_CONN0,
20,
0xf,
afe_conn_hdmi_mux_map,
afe_conn_hdmi_mux_map_value);
static const struct snd_kcontrol_new hdmi_ch5_mux_control =
SOC_DAPM_ENUM("HDMI_CH5_MUX", hdmi_ch5_mux_map_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch6_mux_map_enum,
AFE_TDMOUT_CONN0,
24,
0xf,
afe_conn_hdmi_mux_map,
afe_conn_hdmi_mux_map_value);
static const struct snd_kcontrol_new hdmi_ch6_mux_control =
SOC_DAPM_ENUM("HDMI_CH6_MUX", hdmi_ch6_mux_map_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch7_mux_map_enum,
AFE_TDMOUT_CONN0,
28,
0xf,
afe_conn_hdmi_mux_map,
afe_conn_hdmi_mux_map_value);
static const struct snd_kcontrol_new hdmi_ch7_mux_control =
SOC_DAPM_ENUM("HDMI_CH7_MUX", hdmi_ch7_mux_map_enum);
static int mt8195_etdm_clk_src_sel_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
unsigned int source = ucontrol->value.enumerated.item[0];
unsigned int val;
unsigned int mask;
unsigned int reg;
if (source >= e->items)
return -EINVAL;
reg = 0;
if (!strcmp(kcontrol->id.name, "ETDM_OUT1_Clock_Source")) {
reg = ETDM_OUT1_CON4;
mask = ETDM_OUT_CON4_CLOCK_MASK;
val = ETDM_OUT_CON4_CLOCK(source);
} else if (!strcmp(kcontrol->id.name, "ETDM_OUT2_Clock_Source")) {
reg = ETDM_OUT2_CON4;
mask = ETDM_OUT_CON4_CLOCK_MASK;
val = ETDM_OUT_CON4_CLOCK(source);
} else if (!strcmp(kcontrol->id.name, "ETDM_OUT3_Clock_Source")) {
reg = ETDM_OUT3_CON4;
mask = ETDM_OUT_CON4_CLOCK_MASK;
val = ETDM_OUT_CON4_CLOCK(source);
} else if (!strcmp(kcontrol->id.name, "ETDM_IN1_Clock_Source")) {
reg = ETDM_IN1_CON2;
mask = ETDM_IN_CON2_CLOCK_MASK;
val = ETDM_IN_CON2_CLOCK(source);
} else if (!strcmp(kcontrol->id.name, "ETDM_IN2_Clock_Source")) {
reg = ETDM_IN2_CON2;
mask = ETDM_IN_CON2_CLOCK_MASK;
val = ETDM_IN_CON2_CLOCK(source);
}
if (reg)
regmap_update_bits(afe->regmap, reg, mask, val);
return 0;
}
static int mt8195_etdm_clk_src_sel_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
unsigned int value = 0;
unsigned int reg = 0;
unsigned int mask = 0;
unsigned int shift = 0;
if (!strcmp(kcontrol->id.name, "ETDM_OUT1_Clock_Source")) {
reg = ETDM_OUT1_CON4;
mask = ETDM_OUT_CON4_CLOCK_MASK;
shift = ETDM_OUT_CON4_CLOCK_SHIFT;
} else if (!strcmp(kcontrol->id.name, "ETDM_OUT2_Clock_Source")) {
reg = ETDM_OUT2_CON4;
mask = ETDM_OUT_CON4_CLOCK_MASK;
shift = ETDM_OUT_CON4_CLOCK_SHIFT;
} else if (!strcmp(kcontrol->id.name, "ETDM_OUT3_Clock_Source")) {
reg = ETDM_OUT3_CON4;
mask = ETDM_OUT_CON4_CLOCK_MASK;
shift = ETDM_OUT_CON4_CLOCK_SHIFT;
} else if (!strcmp(kcontrol->id.name, "ETDM_IN1_Clock_Source")) {
reg = ETDM_IN1_CON2;
mask = ETDM_IN_CON2_CLOCK_MASK;
shift = ETDM_IN_CON2_CLOCK_SHIFT;
} else if (!strcmp(kcontrol->id.name, "ETDM_IN2_Clock_Source")) {
reg = ETDM_IN2_CON2;
mask = ETDM_IN_CON2_CLOCK_MASK;
shift = ETDM_IN_CON2_CLOCK_SHIFT;
}
if (reg)
regmap_read(afe->regmap, reg, &value);
value &= mask;
value >>= shift;
ucontrol->value.enumerated.item[0] = value;
return 0;
}
static const struct snd_kcontrol_new mtk_dai_etdm_controls[] = {
SOC_ENUM_EXT("ETDM_OUT1_Clock_Source",
etdmout_clk_src_enum,
mt8195_etdm_clk_src_sel_get,
mt8195_etdm_clk_src_sel_put),
SOC_ENUM_EXT("ETDM_OUT2_Clock_Source",
etdmout_clk_src_enum,
mt8195_etdm_clk_src_sel_get,
mt8195_etdm_clk_src_sel_put),
SOC_ENUM_EXT("ETDM_OUT3_Clock_Source",
etdmout_clk_src_enum,
mt8195_etdm_clk_src_sel_get,
mt8195_etdm_clk_src_sel_put),
SOC_ENUM_EXT("ETDM_IN1_Clock_Source",
etdmout_clk_src_enum,
mt8195_etdm_clk_src_sel_get,
mt8195_etdm_clk_src_sel_put),
SOC_ENUM_EXT("ETDM_IN2_Clock_Source",
etdmout_clk_src_enum,
mt8195_etdm_clk_src_sel_get,
mt8195_etdm_clk_src_sel_put),
};
static const struct snd_soc_dapm_widget mtk_dai_etdm_widgets[] = {
/* eTDM_IN2 */
SND_SOC_DAPM_MIXER("I012", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I013", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I014", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I015", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I016", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I017", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I018", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I019", SND_SOC_NOPM, 0, 0, NULL, 0),
/* eTDM_IN1 */
SND_SOC_DAPM_MIXER("I072", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I073", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I074", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I075", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I076", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I077", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I078", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I079", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I080", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I081", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I082", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I083", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I084", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I085", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I086", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I087", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I088", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I089", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I090", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I091", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I092", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I093", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I094", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I095", SND_SOC_NOPM, 0, 0, NULL, 0),
/* eTDM_OUT2 */
SND_SOC_DAPM_MIXER("O048", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o048_mix,
ARRAY_SIZE(mtk_dai_etdm_o048_mix)),
SND_SOC_DAPM_MIXER("O049", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o049_mix,
ARRAY_SIZE(mtk_dai_etdm_o049_mix)),
SND_SOC_DAPM_MIXER("O050", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o050_mix,
ARRAY_SIZE(mtk_dai_etdm_o050_mix)),
SND_SOC_DAPM_MIXER("O051", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o051_mix,
ARRAY_SIZE(mtk_dai_etdm_o051_mix)),
SND_SOC_DAPM_MIXER("O052", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o052_mix,
ARRAY_SIZE(mtk_dai_etdm_o052_mix)),
SND_SOC_DAPM_MIXER("O053", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o053_mix,
ARRAY_SIZE(mtk_dai_etdm_o053_mix)),
SND_SOC_DAPM_MIXER("O054", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o054_mix,
ARRAY_SIZE(mtk_dai_etdm_o054_mix)),
SND_SOC_DAPM_MIXER("O055", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o055_mix,
ARRAY_SIZE(mtk_dai_etdm_o055_mix)),
SND_SOC_DAPM_MIXER("O056", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o056_mix,
ARRAY_SIZE(mtk_dai_etdm_o056_mix)),
SND_SOC_DAPM_MIXER("O057", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o057_mix,
ARRAY_SIZE(mtk_dai_etdm_o057_mix)),
SND_SOC_DAPM_MIXER("O058", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o058_mix,
ARRAY_SIZE(mtk_dai_etdm_o058_mix)),
SND_SOC_DAPM_MIXER("O059", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o059_mix,
ARRAY_SIZE(mtk_dai_etdm_o059_mix)),
SND_SOC_DAPM_MIXER("O060", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o060_mix,
ARRAY_SIZE(mtk_dai_etdm_o060_mix)),
SND_SOC_DAPM_MIXER("O061", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o061_mix,
ARRAY_SIZE(mtk_dai_etdm_o061_mix)),
SND_SOC_DAPM_MIXER("O062", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o062_mix,
ARRAY_SIZE(mtk_dai_etdm_o062_mix)),
SND_SOC_DAPM_MIXER("O063", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o063_mix,
ARRAY_SIZE(mtk_dai_etdm_o063_mix)),
SND_SOC_DAPM_MIXER("O064", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o064_mix,
ARRAY_SIZE(mtk_dai_etdm_o064_mix)),
SND_SOC_DAPM_MIXER("O065", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o065_mix,
ARRAY_SIZE(mtk_dai_etdm_o065_mix)),
SND_SOC_DAPM_MIXER("O066", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o066_mix,
ARRAY_SIZE(mtk_dai_etdm_o066_mix)),
SND_SOC_DAPM_MIXER("O067", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o067_mix,
ARRAY_SIZE(mtk_dai_etdm_o067_mix)),
SND_SOC_DAPM_MIXER("O068", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o068_mix,
ARRAY_SIZE(mtk_dai_etdm_o068_mix)),
SND_SOC_DAPM_MIXER("O069", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o069_mix,
ARRAY_SIZE(mtk_dai_etdm_o069_mix)),
SND_SOC_DAPM_MIXER("O070", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o070_mix,
ARRAY_SIZE(mtk_dai_etdm_o070_mix)),
SND_SOC_DAPM_MIXER("O071", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o071_mix,
ARRAY_SIZE(mtk_dai_etdm_o071_mix)),
/* eTDM_OUT1 */
SND_SOC_DAPM_MIXER("O072", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o072_mix,
ARRAY_SIZE(mtk_dai_etdm_o072_mix)),
SND_SOC_DAPM_MIXER("O073", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o073_mix,
ARRAY_SIZE(mtk_dai_etdm_o073_mix)),
SND_SOC_DAPM_MIXER("O074", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o074_mix,
ARRAY_SIZE(mtk_dai_etdm_o074_mix)),
SND_SOC_DAPM_MIXER("O075", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o075_mix,
ARRAY_SIZE(mtk_dai_etdm_o075_mix)),
SND_SOC_DAPM_MIXER("O076", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o076_mix,
ARRAY_SIZE(mtk_dai_etdm_o076_mix)),
SND_SOC_DAPM_MIXER("O077", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o077_mix,
ARRAY_SIZE(mtk_dai_etdm_o077_mix)),
SND_SOC_DAPM_MIXER("O078", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o078_mix,
ARRAY_SIZE(mtk_dai_etdm_o078_mix)),
SND_SOC_DAPM_MIXER("O079", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o079_mix,
ARRAY_SIZE(mtk_dai_etdm_o079_mix)),
SND_SOC_DAPM_MIXER("O080", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o080_mix,
ARRAY_SIZE(mtk_dai_etdm_o080_mix)),
SND_SOC_DAPM_MIXER("O081", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o081_mix,
ARRAY_SIZE(mtk_dai_etdm_o081_mix)),
SND_SOC_DAPM_MIXER("O082", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o082_mix,
ARRAY_SIZE(mtk_dai_etdm_o082_mix)),
SND_SOC_DAPM_MIXER("O083", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o083_mix,
ARRAY_SIZE(mtk_dai_etdm_o083_mix)),
SND_SOC_DAPM_MIXER("O084", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o084_mix,
ARRAY_SIZE(mtk_dai_etdm_o084_mix)),
SND_SOC_DAPM_MIXER("O085", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o085_mix,
ARRAY_SIZE(mtk_dai_etdm_o085_mix)),
SND_SOC_DAPM_MIXER("O086", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o086_mix,
ARRAY_SIZE(mtk_dai_etdm_o086_mix)),
SND_SOC_DAPM_MIXER("O087", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o087_mix,
ARRAY_SIZE(mtk_dai_etdm_o087_mix)),
SND_SOC_DAPM_MIXER("O088", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o088_mix,
ARRAY_SIZE(mtk_dai_etdm_o088_mix)),
SND_SOC_DAPM_MIXER("O089", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o089_mix,
ARRAY_SIZE(mtk_dai_etdm_o089_mix)),
SND_SOC_DAPM_MIXER("O090", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o090_mix,
ARRAY_SIZE(mtk_dai_etdm_o090_mix)),
SND_SOC_DAPM_MIXER("O091", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o091_mix,
ARRAY_SIZE(mtk_dai_etdm_o091_mix)),
SND_SOC_DAPM_MIXER("O092", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o092_mix,
ARRAY_SIZE(mtk_dai_etdm_o092_mix)),
SND_SOC_DAPM_MIXER("O093", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o093_mix,
ARRAY_SIZE(mtk_dai_etdm_o093_mix)),
SND_SOC_DAPM_MIXER("O094", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o094_mix,
ARRAY_SIZE(mtk_dai_etdm_o094_mix)),
SND_SOC_DAPM_MIXER("O095", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o095_mix,
ARRAY_SIZE(mtk_dai_etdm_o095_mix)),
/* eTDM_OUT3 */
SND_SOC_DAPM_MUX("HDMI_OUT_MUX", SND_SOC_NOPM, 0, 0,
&hdmi_out_mux_control),
SND_SOC_DAPM_MUX("DPTX_OUT_MUX", SND_SOC_NOPM, 0, 0,
&dptx_out_mux_control),
SND_SOC_DAPM_MUX("HDMI_CH0_MUX", SND_SOC_NOPM, 0, 0,
&hdmi_ch0_mux_control),
SND_SOC_DAPM_MUX("HDMI_CH1_MUX", SND_SOC_NOPM, 0, 0,
&hdmi_ch1_mux_control),
SND_SOC_DAPM_MUX("HDMI_CH2_MUX", SND_SOC_NOPM, 0, 0,
&hdmi_ch2_mux_control),
SND_SOC_DAPM_MUX("HDMI_CH3_MUX", SND_SOC_NOPM, 0, 0,
&hdmi_ch3_mux_control),
SND_SOC_DAPM_MUX("HDMI_CH4_MUX", SND_SOC_NOPM, 0, 0,
&hdmi_ch4_mux_control),
SND_SOC_DAPM_MUX("HDMI_CH5_MUX", SND_SOC_NOPM, 0, 0,
&hdmi_ch5_mux_control),
SND_SOC_DAPM_MUX("HDMI_CH6_MUX", SND_SOC_NOPM, 0, 0,
&hdmi_ch6_mux_control),
SND_SOC_DAPM_MUX("HDMI_CH7_MUX", SND_SOC_NOPM, 0, 0,
&hdmi_ch7_mux_control),
SND_SOC_DAPM_INPUT("ETDM_INPUT"),
SND_SOC_DAPM_OUTPUT("ETDM_OUTPUT"),
};
static const struct snd_soc_dapm_route mtk_dai_etdm_routes[] = {
{"I012", NULL, "ETDM2 Capture"},
{"I013", NULL, "ETDM2 Capture"},
{"I014", NULL, "ETDM2 Capture"},
{"I015", NULL, "ETDM2 Capture"},
{"I016", NULL, "ETDM2 Capture"},
{"I017", NULL, "ETDM2 Capture"},
{"I018", NULL, "ETDM2 Capture"},
{"I019", NULL, "ETDM2 Capture"},
{"I072", NULL, "ETDM1 Capture"},
{"I073", NULL, "ETDM1 Capture"},
{"I074", NULL, "ETDM1 Capture"},
{"I075", NULL, "ETDM1 Capture"},
{"I076", NULL, "ETDM1 Capture"},
{"I077", NULL, "ETDM1 Capture"},
{"I078", NULL, "ETDM1 Capture"},
{"I079", NULL, "ETDM1 Capture"},
{"I080", NULL, "ETDM1 Capture"},
{"I081", NULL, "ETDM1 Capture"},
{"I082", NULL, "ETDM1 Capture"},
{"I083", NULL, "ETDM1 Capture"},
{"I084", NULL, "ETDM1 Capture"},
{"I085", NULL, "ETDM1 Capture"},
{"I086", NULL, "ETDM1 Capture"},
{"I087", NULL, "ETDM1 Capture"},
{"I088", NULL, "ETDM1 Capture"},
{"I089", NULL, "ETDM1 Capture"},
{"I090", NULL, "ETDM1 Capture"},
{"I091", NULL, "ETDM1 Capture"},
{"I092", NULL, "ETDM1 Capture"},
{"I093", NULL, "ETDM1 Capture"},
{"I094", NULL, "ETDM1 Capture"},
{"I095", NULL, "ETDM1 Capture"},
{"UL8", NULL, "ETDM1 Capture"},
{"UL3", NULL, "ETDM2 Capture"},
{"ETDM2 Playback", NULL, "O048"},
{"ETDM2 Playback", NULL, "O049"},
{"ETDM2 Playback", NULL, "O050"},
{"ETDM2 Playback", NULL, "O051"},
{"ETDM2 Playback", NULL, "O052"},
{"ETDM2 Playback", NULL, "O053"},
{"ETDM2 Playback", NULL, "O054"},
{"ETDM2 Playback", NULL, "O055"},
{"ETDM2 Playback", NULL, "O056"},
{"ETDM2 Playback", NULL, "O057"},
{"ETDM2 Playback", NULL, "O058"},
{"ETDM2 Playback", NULL, "O059"},
{"ETDM2 Playback", NULL, "O060"},
{"ETDM2 Playback", NULL, "O061"},
{"ETDM2 Playback", NULL, "O062"},
{"ETDM2 Playback", NULL, "O063"},
{"ETDM2 Playback", NULL, "O064"},
{"ETDM2 Playback", NULL, "O065"},
{"ETDM2 Playback", NULL, "O066"},
{"ETDM2 Playback", NULL, "O067"},
{"ETDM2 Playback", NULL, "O068"},
{"ETDM2 Playback", NULL, "O069"},
{"ETDM2 Playback", NULL, "O070"},
{"ETDM2 Playback", NULL, "O071"},
{"ETDM1 Playback", NULL, "O072"},
{"ETDM1 Playback", NULL, "O073"},
{"ETDM1 Playback", NULL, "O074"},
{"ETDM1 Playback", NULL, "O075"},
{"ETDM1 Playback", NULL, "O076"},
{"ETDM1 Playback", NULL, "O077"},
{"ETDM1 Playback", NULL, "O078"},
{"ETDM1 Playback", NULL, "O079"},
{"ETDM1 Playback", NULL, "O080"},
{"ETDM1 Playback", NULL, "O081"},
{"ETDM1 Playback", NULL, "O082"},
{"ETDM1 Playback", NULL, "O083"},
{"ETDM1 Playback", NULL, "O084"},
{"ETDM1 Playback", NULL, "O085"},
{"ETDM1 Playback", NULL, "O086"},
{"ETDM1 Playback", NULL, "O087"},
{"ETDM1 Playback", NULL, "O088"},
{"ETDM1 Playback", NULL, "O089"},
{"ETDM1 Playback", NULL, "O090"},
{"ETDM1 Playback", NULL, "O091"},
{"ETDM1 Playback", NULL, "O092"},
{"ETDM1 Playback", NULL, "O093"},
{"ETDM1 Playback", NULL, "O094"},
{"ETDM1 Playback", NULL, "O095"},
{"O048", "I020 Switch", "I020"},
{"O049", "I021 Switch", "I021"},
{"O048", "I022 Switch", "I022"},
{"O049", "I023 Switch", "I023"},
{"O050", "I024 Switch", "I024"},
{"O051", "I025 Switch", "I025"},
{"O052", "I026 Switch", "I026"},
{"O053", "I027 Switch", "I027"},
{"O054", "I028 Switch", "I028"},
{"O055", "I029 Switch", "I029"},
{"O056", "I030 Switch", "I030"},
{"O057", "I031 Switch", "I031"},
{"O058", "I032 Switch", "I032"},
{"O059", "I033 Switch", "I033"},
{"O060", "I034 Switch", "I034"},
{"O061", "I035 Switch", "I035"},
{"O062", "I036 Switch", "I036"},
{"O063", "I037 Switch", "I037"},
{"O064", "I038 Switch", "I038"},
{"O065", "I039 Switch", "I039"},
{"O066", "I040 Switch", "I040"},
{"O067", "I041 Switch", "I041"},
{"O068", "I042 Switch", "I042"},
{"O069", "I043 Switch", "I043"},
{"O070", "I044 Switch", "I044"},
{"O071", "I045 Switch", "I045"},
{"O048", "I046 Switch", "I046"},
{"O049", "I047 Switch", "I047"},
{"O050", "I048 Switch", "I048"},
{"O051", "I049 Switch", "I049"},
{"O052", "I050 Switch", "I050"},
{"O053", "I051 Switch", "I051"},
{"O054", "I052 Switch", "I052"},
{"O055", "I053 Switch", "I053"},
{"O056", "I054 Switch", "I054"},
{"O057", "I055 Switch", "I055"},
{"O058", "I056 Switch", "I056"},
{"O059", "I057 Switch", "I057"},
{"O060", "I058 Switch", "I058"},
{"O061", "I059 Switch", "I059"},
{"O062", "I060 Switch", "I060"},
{"O063", "I061 Switch", "I061"},
{"O064", "I062 Switch", "I062"},
{"O065", "I063 Switch", "I063"},
{"O066", "I064 Switch", "I064"},
{"O067", "I065 Switch", "I065"},
{"O068", "I066 Switch", "I066"},
{"O069", "I067 Switch", "I067"},
{"O070", "I068 Switch", "I068"},
{"O071", "I069 Switch", "I069"},
{"O048", "I070 Switch", "I070"},
{"O049", "I071 Switch", "I071"},
{"O072", "I020 Switch", "I020"},
{"O073", "I021 Switch", "I021"},
{"O072", "I022 Switch", "I022"},
{"O073", "I023 Switch", "I023"},
{"O074", "I024 Switch", "I024"},
{"O075", "I025 Switch", "I025"},
{"O076", "I026 Switch", "I026"},
{"O077", "I027 Switch", "I027"},
{"O078", "I028 Switch", "I028"},
{"O079", "I029 Switch", "I029"},
{"O080", "I030 Switch", "I030"},
{"O081", "I031 Switch", "I031"},
{"O082", "I032 Switch", "I032"},
{"O083", "I033 Switch", "I033"},
{"O084", "I034 Switch", "I034"},
{"O085", "I035 Switch", "I035"},
{"O086", "I036 Switch", "I036"},
{"O087", "I037 Switch", "I037"},
{"O088", "I038 Switch", "I038"},
{"O089", "I039 Switch", "I039"},
{"O090", "I040 Switch", "I040"},
{"O091", "I041 Switch", "I041"},
{"O092", "I042 Switch", "I042"},
{"O093", "I043 Switch", "I043"},
{"O094", "I044 Switch", "I044"},
{"O095", "I045 Switch", "I045"},
{"O072", "I046 Switch", "I046"},
{"O073", "I047 Switch", "I047"},
{"O074", "I048 Switch", "I048"},
{"O075", "I049 Switch", "I049"},
{"O076", "I050 Switch", "I050"},
{"O077", "I051 Switch", "I051"},
{"O078", "I052 Switch", "I052"},
{"O079", "I053 Switch", "I053"},
{"O080", "I054 Switch", "I054"},
{"O081", "I055 Switch", "I055"},
{"O082", "I056 Switch", "I056"},
{"O083", "I057 Switch", "I057"},
{"O084", "I058 Switch", "I058"},
{"O085", "I059 Switch", "I059"},
{"O086", "I060 Switch", "I060"},
{"O087", "I061 Switch", "I061"},
{"O088", "I062 Switch", "I062"},
{"O089", "I063 Switch", "I063"},
{"O090", "I064 Switch", "I064"},
{"O091", "I065 Switch", "I065"},
{"O092", "I066 Switch", "I066"},
{"O093", "I067 Switch", "I067"},
{"O094", "I068 Switch", "I068"},
{"O095", "I069 Switch", "I069"},
{"O072", "I070 Switch", "I070"},
{"O073", "I071 Switch", "I071"},
{"HDMI_CH0_MUX", "CH0", "DL10"},
{"HDMI_CH0_MUX", "CH1", "DL10"},
{"HDMI_CH0_MUX", "CH2", "DL10"},
{"HDMI_CH0_MUX", "CH3", "DL10"},
{"HDMI_CH0_MUX", "CH4", "DL10"},
{"HDMI_CH0_MUX", "CH5", "DL10"},
{"HDMI_CH0_MUX", "CH6", "DL10"},
{"HDMI_CH0_MUX", "CH7", "DL10"},
{"HDMI_CH1_MUX", "CH0", "DL10"},
{"HDMI_CH1_MUX", "CH1", "DL10"},
{"HDMI_CH1_MUX", "CH2", "DL10"},
{"HDMI_CH1_MUX", "CH3", "DL10"},
{"HDMI_CH1_MUX", "CH4", "DL10"},
{"HDMI_CH1_MUX", "CH5", "DL10"},
{"HDMI_CH1_MUX", "CH6", "DL10"},
{"HDMI_CH1_MUX", "CH7", "DL10"},
{"HDMI_CH2_MUX", "CH0", "DL10"},
{"HDMI_CH2_MUX", "CH1", "DL10"},
{"HDMI_CH2_MUX", "CH2", "DL10"},
{"HDMI_CH2_MUX", "CH3", "DL10"},
{"HDMI_CH2_MUX", "CH4", "DL10"},
{"HDMI_CH2_MUX", "CH5", "DL10"},
{"HDMI_CH2_MUX", "CH6", "DL10"},
{"HDMI_CH2_MUX", "CH7", "DL10"},
{"HDMI_CH3_MUX", "CH0", "DL10"},
{"HDMI_CH3_MUX", "CH1", "DL10"},
{"HDMI_CH3_MUX", "CH2", "DL10"},
{"HDMI_CH3_MUX", "CH3", "DL10"},
{"HDMI_CH3_MUX", "CH4", "DL10"},
{"HDMI_CH3_MUX", "CH5", "DL10"},
{"HDMI_CH3_MUX", "CH6", "DL10"},
{"HDMI_CH3_MUX", "CH7", "DL10"},
{"HDMI_CH4_MUX", "CH0", "DL10"},
{"HDMI_CH4_MUX", "CH1", "DL10"},
{"HDMI_CH4_MUX", "CH2", "DL10"},
{"HDMI_CH4_MUX", "CH3", "DL10"},
{"HDMI_CH4_MUX", "CH4", "DL10"},
{"HDMI_CH4_MUX", "CH5", "DL10"},
{"HDMI_CH4_MUX", "CH6", "DL10"},
{"HDMI_CH4_MUX", "CH7", "DL10"},
{"HDMI_CH5_MUX", "CH0", "DL10"},
{"HDMI_CH5_MUX", "CH1", "DL10"},
{"HDMI_CH5_MUX", "CH2", "DL10"},
{"HDMI_CH5_MUX", "CH3", "DL10"},
{"HDMI_CH5_MUX", "CH4", "DL10"},
{"HDMI_CH5_MUX", "CH5", "DL10"},
{"HDMI_CH5_MUX", "CH6", "DL10"},
{"HDMI_CH5_MUX", "CH7", "DL10"},
{"HDMI_CH6_MUX", "CH0", "DL10"},
{"HDMI_CH6_MUX", "CH1", "DL10"},
{"HDMI_CH6_MUX", "CH2", "DL10"},
{"HDMI_CH6_MUX", "CH3", "DL10"},
{"HDMI_CH6_MUX", "CH4", "DL10"},
{"HDMI_CH6_MUX", "CH5", "DL10"},
{"HDMI_CH6_MUX", "CH6", "DL10"},
{"HDMI_CH6_MUX", "CH7", "DL10"},
{"HDMI_CH7_MUX", "CH0", "DL10"},
{"HDMI_CH7_MUX", "CH1", "DL10"},
{"HDMI_CH7_MUX", "CH2", "DL10"},
{"HDMI_CH7_MUX", "CH3", "DL10"},
{"HDMI_CH7_MUX", "CH4", "DL10"},
{"HDMI_CH7_MUX", "CH5", "DL10"},
{"HDMI_CH7_MUX", "CH6", "DL10"},
{"HDMI_CH7_MUX", "CH7", "DL10"},
{"HDMI_OUT_MUX", "Connect", "HDMI_CH0_MUX"},
{"HDMI_OUT_MUX", "Connect", "HDMI_CH1_MUX"},
{"HDMI_OUT_MUX", "Connect", "HDMI_CH2_MUX"},
{"HDMI_OUT_MUX", "Connect", "HDMI_CH3_MUX"},
{"HDMI_OUT_MUX", "Connect", "HDMI_CH4_MUX"},
{"HDMI_OUT_MUX", "Connect", "HDMI_CH5_MUX"},
{"HDMI_OUT_MUX", "Connect", "HDMI_CH6_MUX"},
{"HDMI_OUT_MUX", "Connect", "HDMI_CH7_MUX"},
{"DPTX_OUT_MUX", "Connect", "HDMI_CH0_MUX"},
{"DPTX_OUT_MUX", "Connect", "HDMI_CH1_MUX"},
{"DPTX_OUT_MUX", "Connect", "HDMI_CH2_MUX"},
{"DPTX_OUT_MUX", "Connect", "HDMI_CH3_MUX"},
{"DPTX_OUT_MUX", "Connect", "HDMI_CH4_MUX"},
{"DPTX_OUT_MUX", "Connect", "HDMI_CH5_MUX"},
{"DPTX_OUT_MUX", "Connect", "HDMI_CH6_MUX"},
{"DPTX_OUT_MUX", "Connect", "HDMI_CH7_MUX"},
{"ETDM3 Playback", NULL, "HDMI_OUT_MUX"},
{"DPTX Playback", NULL, "DPTX_OUT_MUX"},
{"ETDM_OUTPUT", NULL, "DPTX Playback"},
{"ETDM_OUTPUT", NULL, "ETDM1 Playback"},
{"ETDM_OUTPUT", NULL, "ETDM2 Playback"},
{"ETDM_OUTPUT", NULL, "ETDM3 Playback"},
{"ETDM1 Capture", NULL, "ETDM_INPUT"},
{"ETDM2 Capture", NULL, "ETDM_INPUT"},
};
static int mt8195_afe_enable_etdm(struct mtk_base_afe *afe, int dai_id)
{
int ret = 0;
struct etdm_con_reg etdm_reg;
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_etdm_priv *etdm_data;
unsigned long flags;
if (!mt8195_afe_etdm_is_valid(dai_id))
return -EINVAL;
etdm_data = afe_priv->dai_priv[dai_id];
spin_lock_irqsave(&afe_priv->afe_ctrl_lock, flags);
etdm_data->en_ref_cnt++;
if (etdm_data->en_ref_cnt == 1) {
ret = get_etdm_reg(dai_id, &etdm_reg);
if (ret < 0)
goto out;
regmap_update_bits(afe->regmap, etdm_reg.con0,
ETDM_CON0_EN, ETDM_CON0_EN);
}
out:
spin_unlock_irqrestore(&afe_priv->afe_ctrl_lock, flags);
return ret;
}
static int mt8195_afe_disable_etdm(struct mtk_base_afe *afe, int dai_id)
{
int ret = 0;
struct etdm_con_reg etdm_reg;
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_etdm_priv *etdm_data;
unsigned long flags;
if (!mt8195_afe_etdm_is_valid(dai_id))
return -EINVAL;
etdm_data = afe_priv->dai_priv[dai_id];
spin_lock_irqsave(&afe_priv->afe_ctrl_lock, flags);
if (etdm_data->en_ref_cnt > 0) {
etdm_data->en_ref_cnt--;
if (etdm_data->en_ref_cnt == 0) {
ret = get_etdm_reg(dai_id, &etdm_reg);
if (ret < 0)
goto out;
regmap_update_bits(afe->regmap, etdm_reg.con0,
ETDM_CON0_EN, 0);
}
}
out:
spin_unlock_irqrestore(&afe_priv->afe_ctrl_lock, flags);
return ret;
}
static int etdm_cowork_slv_sel(int id, int slave_mode)
{
if (slave_mode) {
switch (id) {
case MT8195_AFE_IO_ETDM1_IN:
return COWORK_ETDM_IN1_S;
case MT8195_AFE_IO_ETDM2_IN:
return COWORK_ETDM_IN2_S;
case MT8195_AFE_IO_ETDM1_OUT:
return COWORK_ETDM_OUT1_S;
case MT8195_AFE_IO_ETDM2_OUT:
return COWORK_ETDM_OUT2_S;
case MT8195_AFE_IO_ETDM3_OUT:
return COWORK_ETDM_OUT3_S;
default:
return -EINVAL;
}
} else {
switch (id) {
case MT8195_AFE_IO_ETDM1_IN:
return COWORK_ETDM_IN1_M;
case MT8195_AFE_IO_ETDM2_IN:
return COWORK_ETDM_IN2_M;
case MT8195_AFE_IO_ETDM1_OUT:
return COWORK_ETDM_OUT1_M;
case MT8195_AFE_IO_ETDM2_OUT:
return COWORK_ETDM_OUT2_M;
case MT8195_AFE_IO_ETDM3_OUT:
return COWORK_ETDM_OUT3_M;
default:
return -EINVAL;
}
}
}
static int mt8195_etdm_sync_mode_configure(struct mtk_base_afe *afe, int dai_id)
{
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_etdm_priv *etdm_data;
unsigned int reg = 0;
unsigned int mask;
unsigned int val;
int cowork_source_sel;
if (!mt8195_afe_etdm_is_valid(dai_id))
return -EINVAL;
etdm_data = afe_priv->dai_priv[dai_id];
if (etdm_data->cowork_source_id == COWORK_ETDM_NONE)
return 0;
cowork_source_sel = etdm_cowork_slv_sel(etdm_data->cowork_source_id,
etdm_data->slave_mode);
if (cowork_source_sel < 0)
return cowork_source_sel;
switch (dai_id) {
case MT8195_AFE_IO_ETDM1_IN:
reg = ETDM_COWORK_CON1;
mask = ETDM_IN1_SLAVE_SEL_MASK;
val = ETDM_IN1_SLAVE_SEL(cowork_source_sel);
break;
case MT8195_AFE_IO_ETDM2_IN:
reg = ETDM_COWORK_CON2;
mask = ETDM_IN2_SLAVE_SEL_MASK;
val = ETDM_IN2_SLAVE_SEL(cowork_source_sel);
break;
case MT8195_AFE_IO_ETDM1_OUT:
reg = ETDM_COWORK_CON0;
mask = ETDM_OUT1_SLAVE_SEL_MASK;
val = ETDM_OUT1_SLAVE_SEL(cowork_source_sel);
break;
case MT8195_AFE_IO_ETDM2_OUT:
reg = ETDM_COWORK_CON2;
mask = ETDM_OUT2_SLAVE_SEL_MASK;
val = ETDM_OUT2_SLAVE_SEL(cowork_source_sel);
break;
case MT8195_AFE_IO_ETDM3_OUT:
reg = ETDM_COWORK_CON2;
mask = ETDM_OUT3_SLAVE_SEL_MASK;
val = ETDM_OUT3_SLAVE_SEL(cowork_source_sel);
break;
default:
return 0;
}
regmap_update_bits(afe->regmap, reg, mask, val);
return 0;
}
static int mtk_dai_etdm_get_cg_id_by_dai_id(int dai_id)
{
int cg_id = -1;
switch (dai_id) {
case MT8195_AFE_IO_DPTX:
cg_id = MT8195_CLK_AUD_HDMI_OUT;
break;
case MT8195_AFE_IO_ETDM1_IN:
cg_id = MT8195_CLK_AUD_TDM_IN;
break;
case MT8195_AFE_IO_ETDM2_IN:
cg_id = MT8195_CLK_AUD_I2SIN;
break;
case MT8195_AFE_IO_ETDM1_OUT:
cg_id = MT8195_CLK_AUD_TDM_OUT;
break;
case MT8195_AFE_IO_ETDM2_OUT:
cg_id = MT8195_CLK_AUD_I2S_OUT;
break;
case MT8195_AFE_IO_ETDM3_OUT:
cg_id = MT8195_CLK_AUD_HDMI_OUT;
break;
default:
break;
}
return cg_id;
}
static int mtk_dai_etdm_get_clk_id_by_dai_id(int dai_id)
{
int clk_id = -1;
switch (dai_id) {
case MT8195_AFE_IO_DPTX:
clk_id = MT8195_CLK_TOP_DPTX_M_SEL;
break;
case MT8195_AFE_IO_ETDM1_IN:
clk_id = MT8195_CLK_TOP_I2SI1_M_SEL;
break;
case MT8195_AFE_IO_ETDM2_IN:
clk_id = MT8195_CLK_TOP_I2SI2_M_SEL;
break;
case MT8195_AFE_IO_ETDM1_OUT:
clk_id = MT8195_CLK_TOP_I2SO1_M_SEL;
break;
case MT8195_AFE_IO_ETDM2_OUT:
clk_id = MT8195_CLK_TOP_I2SO2_M_SEL;
break;
case MT8195_AFE_IO_ETDM3_OUT:
default:
break;
}
return clk_id;
}
static int mtk_dai_etdm_get_clkdiv_id_by_dai_id(int dai_id)
{
int clk_id = -1;
switch (dai_id) {
case MT8195_AFE_IO_DPTX:
clk_id = MT8195_CLK_TOP_APLL12_DIV9;
break;
case MT8195_AFE_IO_ETDM1_IN:
clk_id = MT8195_CLK_TOP_APLL12_DIV0;
break;
case MT8195_AFE_IO_ETDM2_IN:
clk_id = MT8195_CLK_TOP_APLL12_DIV1;
break;
case MT8195_AFE_IO_ETDM1_OUT:
clk_id = MT8195_CLK_TOP_APLL12_DIV2;
break;
case MT8195_AFE_IO_ETDM2_OUT:
clk_id = MT8195_CLK_TOP_APLL12_DIV3;
break;
case MT8195_AFE_IO_ETDM3_OUT:
default:
break;
}
return clk_id;
}
static int mtk_dai_etdm_enable_mclk(struct mtk_base_afe *afe, int dai_id)
{
struct mt8195_afe_private *afe_priv = afe->platform_priv;
int clkdiv_id = mtk_dai_etdm_get_clkdiv_id_by_dai_id(dai_id);
if (clkdiv_id < 0)
return -EINVAL;
mt8195_afe_enable_clk(afe, afe_priv->clk[clkdiv_id]);
return 0;
}
static int mtk_dai_etdm_disable_mclk(struct mtk_base_afe *afe, int dai_id)
{
struct mt8195_afe_private *afe_priv = afe->platform_priv;
int clkdiv_id = mtk_dai_etdm_get_clkdiv_id_by_dai_id(dai_id);
if (clkdiv_id < 0)
return -EINVAL;
mt8195_afe_disable_clk(afe, afe_priv->clk[clkdiv_id]);
return 0;
}
/* dai ops */
static int mtk_dai_etdm_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_etdm_priv *mst_etdm_data;
int cg_id;
int mst_dai_id;
int slv_dai_id;
int i;
if (is_cowork_mode(dai)) {
mst_dai_id = get_etdm_cowork_master_id(dai);
if (!mt8195_afe_etdm_is_valid(mst_dai_id))
return -EINVAL;
mtk_dai_etdm_enable_mclk(afe, mst_dai_id);
cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(mst_dai_id);
if (cg_id >= 0)
mt8195_afe_enable_clk(afe, afe_priv->clk[cg_id]);
mst_etdm_data = afe_priv->dai_priv[mst_dai_id];
for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) {
slv_dai_id = mst_etdm_data->cowork_slv_id[i];
cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(slv_dai_id);
if (cg_id >= 0)
mt8195_afe_enable_clk(afe,
afe_priv->clk[cg_id]);
}
} else {
mtk_dai_etdm_enable_mclk(afe, dai->id);
cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id);
if (cg_id >= 0)
mt8195_afe_enable_clk(afe, afe_priv->clk[cg_id]);
}
return 0;
}
static void mtk_dai_etdm_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_etdm_priv *mst_etdm_data;
int cg_id;
int mst_dai_id;
int slv_dai_id;
int i;
if (is_cowork_mode(dai)) {
mst_dai_id = get_etdm_cowork_master_id(dai);
if (!mt8195_afe_etdm_is_valid(mst_dai_id))
return;
cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(mst_dai_id);
if (cg_id >= 0)
mt8195_afe_disable_clk(afe, afe_priv->clk[cg_id]);
mst_etdm_data = afe_priv->dai_priv[mst_dai_id];
for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) {
slv_dai_id = mst_etdm_data->cowork_slv_id[i];
cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(slv_dai_id);
if (cg_id >= 0)
mt8195_afe_disable_clk(afe,
afe_priv->clk[cg_id]);
}
mtk_dai_etdm_disable_mclk(afe, mst_dai_id);
} else {
cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id);
if (cg_id >= 0)
mt8195_afe_disable_clk(afe, afe_priv->clk[cg_id]);
mtk_dai_etdm_disable_mclk(afe, dai->id);
}
}
static int mtk_dai_etdm_fifo_mode(struct mtk_base_afe *afe,
int dai_id, unsigned int rate)
{
unsigned int mode = 0;
unsigned int reg = 0;
unsigned int val = 0;
unsigned int mask = (ETDM_IN_AFIFO_MODE_MASK | ETDM_IN_USE_AFIFO);
if (rate != 0)
mode = mt8195_afe_fs_timing(rate);
switch (dai_id) {
case MT8195_AFE_IO_ETDM1_IN:
reg = ETDM_IN1_AFIFO_CON;
if (rate == 0)
mode = MT8195_ETDM_IN1_1X_EN;
break;
case MT8195_AFE_IO_ETDM2_IN:
reg = ETDM_IN2_AFIFO_CON;
if (rate == 0)
mode = MT8195_ETDM_IN2_1X_EN;
break;
default:
return -EINVAL;
}
val = (mode | ETDM_IN_USE_AFIFO);
regmap_update_bits(afe->regmap, reg, mask, val);
return 0;
}
static int mtk_dai_etdm_in_configure(struct mtk_base_afe *afe,
unsigned int rate,
unsigned int channels,
int dai_id)
{
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_etdm_priv *etdm_data;
struct etdm_con_reg etdm_reg;
bool slave_mode;
unsigned int data_mode;
unsigned int lrck_width;
unsigned int val = 0;
unsigned int mask = 0;
int i;
int ret;
if (!mt8195_afe_etdm_is_valid(dai_id))
return -EINVAL;
etdm_data = afe_priv->dai_priv[dai_id];
slave_mode = etdm_data->slave_mode;
data_mode = etdm_data->data_mode;
lrck_width = etdm_data->lrck_width;
dev_dbg(afe->dev, "%s rate %u channels %u, id %d\n",
__func__, rate, channels, dai_id);
ret = get_etdm_reg(dai_id, &etdm_reg);
if (ret < 0)
return ret;
if (etdm_data->cowork_source_id != COWORK_ETDM_NONE)
slave_mode = true;
/* afifo */
if (slave_mode)
mtk_dai_etdm_fifo_mode(afe, dai_id, 0);
else
mtk_dai_etdm_fifo_mode(afe, dai_id, rate);
/* con1 */
if (lrck_width > 0) {
mask |= (ETDM_IN_CON1_LRCK_AUTO_MODE |
ETDM_IN_CON1_LRCK_WIDTH_MASK);
val |= ETDM_IN_CON1_LRCK_WIDTH(lrck_width);
}
regmap_update_bits(afe->regmap, etdm_reg.con1, mask, val);
mask = 0;
val = 0;
/* con2 */
if (!slave_mode) {
mask |= ETDM_IN_CON2_UPDATE_GAP_MASK;
if (rate == 352800 || rate == 384000)
val |= ETDM_IN_CON2_UPDATE_GAP(4);
else
val |= ETDM_IN_CON2_UPDATE_GAP(3);
}
mask |= (ETDM_IN_CON2_MULTI_IP_2CH_MODE |
ETDM_IN_CON2_MULTI_IP_TOTAL_CH_MASK);
if (data_mode == MTK_DAI_ETDM_DATA_MULTI_PIN) {
val |= ETDM_IN_CON2_MULTI_IP_2CH_MODE |
ETDM_IN_CON2_MULTI_IP_TOTAL_CH(channels);
}
regmap_update_bits(afe->regmap, etdm_reg.con2, mask, val);
mask = 0;
val = 0;
/* con3 */
mask |= ETDM_IN_CON3_DISABLE_OUT_MASK;
for (i = 0; i < channels; i += 2) {
if (etdm_data->in_disable_ch[i] &&
etdm_data->in_disable_ch[i + 1])
val |= ETDM_IN_CON3_DISABLE_OUT(i >> 1);
}
if (!slave_mode) {
mask |= ETDM_IN_CON3_FS_MASK;
val |= ETDM_IN_CON3_FS(get_etdm_fs_timing(rate));
}
regmap_update_bits(afe->regmap, etdm_reg.con3, mask, val);
mask = 0;
val = 0;
/* con4 */
mask |= (ETDM_IN_CON4_MASTER_LRCK_INV | ETDM_IN_CON4_MASTER_BCK_INV |
ETDM_IN_CON4_SLAVE_LRCK_INV | ETDM_IN_CON4_SLAVE_BCK_INV);
if (slave_mode) {
if (etdm_data->lrck_inv)
val |= ETDM_IN_CON4_SLAVE_LRCK_INV;
if (etdm_data->bck_inv)
val |= ETDM_IN_CON4_SLAVE_BCK_INV;
} else {
if (etdm_data->lrck_inv)
val |= ETDM_IN_CON4_MASTER_LRCK_INV;
if (etdm_data->bck_inv)
val |= ETDM_IN_CON4_MASTER_BCK_INV;
}
regmap_update_bits(afe->regmap, etdm_reg.con4, mask, val);
mask = 0;
val = 0;
/* con5 */
mask |= ETDM_IN_CON5_LR_SWAP_MASK;
mask |= ETDM_IN_CON5_ENABLE_ODD_MASK;
for (i = 0; i < channels; i += 2) {
if (etdm_data->in_disable_ch[i] &&
!etdm_data->in_disable_ch[i + 1]) {
if (i == (channels - 2))
val |= ETDM_IN_CON5_LR_SWAP(15);
else
val |= ETDM_IN_CON5_LR_SWAP(i >> 1);
val |= ETDM_IN_CON5_ENABLE_ODD(i >> 1);
} else if (!etdm_data->in_disable_ch[i] &&
etdm_data->in_disable_ch[i + 1]) {
val |= ETDM_IN_CON5_ENABLE_ODD(i >> 1);
}
}
regmap_update_bits(afe->regmap, etdm_reg.con5, mask, val);
return 0;
}
static int mtk_dai_etdm_out_configure(struct mtk_base_afe *afe,
unsigned int rate,
unsigned int channels,
int dai_id)
{
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_etdm_priv *etdm_data;
struct etdm_con_reg etdm_reg;
bool slave_mode;
unsigned int lrck_width;
unsigned int val = 0;
unsigned int mask = 0;
int ret;
int fs = 0;
if (!mt8195_afe_etdm_is_valid(dai_id))
return -EINVAL;
etdm_data = afe_priv->dai_priv[dai_id];
slave_mode = etdm_data->slave_mode;
lrck_width = etdm_data->lrck_width;
dev_dbg(afe->dev, "%s rate %u channels %u, id %d\n",
__func__, rate, channels, dai_id);
ret = get_etdm_reg(dai_id, &etdm_reg);
if (ret < 0)
return ret;
if (etdm_data->cowork_source_id != COWORK_ETDM_NONE)
slave_mode = true;
/* con0 */
mask = ETDM_OUT_CON0_RELATCH_DOMAIN_MASK;
val = ETDM_OUT_CON0_RELATCH_DOMAIN(ETDM_RELATCH_TIMING_A1A2SYS);
regmap_update_bits(afe->regmap, etdm_reg.con0, mask, val);
mask = 0;
val = 0;
/* con1 */
if (lrck_width > 0) {
mask |= (ETDM_OUT_CON1_LRCK_AUTO_MODE |
ETDM_OUT_CON1_LRCK_WIDTH_MASK);
val |= ETDM_OUT_CON1_LRCK_WIDTH(lrck_width);
}
regmap_update_bits(afe->regmap, etdm_reg.con1, mask, val);
mask = 0;
val = 0;
if (slave_mode) {
/* con2 */
mask = (ETDM_OUT_CON2_LRCK_DELAY_BCK_INV |
ETDM_OUT_CON2_LRCK_DELAY_0P5T_EN);
val = (ETDM_OUT_CON2_LRCK_DELAY_BCK_INV |
ETDM_OUT_CON2_LRCK_DELAY_0P5T_EN);
regmap_update_bits(afe->regmap, etdm_reg.con2,
mask, val);
mask = 0;
val = 0;
} else {
/* con4 */
mask |= ETDM_OUT_CON4_FS_MASK;
val |= ETDM_OUT_CON4_FS(get_etdm_fs_timing(rate));
}
mask |= ETDM_OUT_CON4_RELATCH_EN_MASK;
if (dai_id == MT8195_AFE_IO_ETDM1_OUT)
fs = MT8195_ETDM_OUT1_1X_EN;
else if (dai_id == MT8195_AFE_IO_ETDM2_OUT)
fs = MT8195_ETDM_OUT2_1X_EN;
val |= ETDM_OUT_CON4_RELATCH_EN(fs);
regmap_update_bits(afe->regmap, etdm_reg.con4, mask, val);
mask = 0;
val = 0;
/* con5 */
mask |= (ETDM_OUT_CON5_MASTER_LRCK_INV | ETDM_OUT_CON5_MASTER_BCK_INV |
ETDM_OUT_CON5_SLAVE_LRCK_INV | ETDM_OUT_CON5_SLAVE_BCK_INV);
if (slave_mode) {
if (etdm_data->lrck_inv)
val |= ETDM_OUT_CON5_SLAVE_LRCK_INV;
if (etdm_data->bck_inv)
val |= ETDM_OUT_CON5_SLAVE_BCK_INV;
} else {
if (etdm_data->lrck_inv)
val |= ETDM_OUT_CON5_MASTER_LRCK_INV;
if (etdm_data->bck_inv)
val |= ETDM_OUT_CON5_MASTER_BCK_INV;
}
regmap_update_bits(afe->regmap, etdm_reg.con5, mask, val);
return 0;
}
static int mtk_dai_etdm_mclk_configure(struct mtk_base_afe *afe, int dai_id)
{
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_etdm_priv *etdm_data;
int clk_id = mtk_dai_etdm_get_clk_id_by_dai_id(dai_id);
int clkdiv_id = mtk_dai_etdm_get_clkdiv_id_by_dai_id(dai_id);
int apll;
int apll_clk_id;
struct etdm_con_reg etdm_reg;
unsigned int val = 0;
unsigned int mask = 0;
int ret = 0;
if (clk_id < 0 || clkdiv_id < 0)
return 0;
if (!mt8195_afe_etdm_is_valid(dai_id))
return -EINVAL;
etdm_data = afe_priv->dai_priv[dai_id];
ret = get_etdm_reg(dai_id, &etdm_reg);
if (ret < 0)
return ret;
mask |= ETDM_CON1_MCLK_OUTPUT;
if (etdm_data->mclk_dir == SND_SOC_CLOCK_OUT)
val |= ETDM_CON1_MCLK_OUTPUT;
regmap_update_bits(afe->regmap, etdm_reg.con1, mask, val);
if (etdm_data->mclk_freq) {
apll = etdm_data->mclk_apll;
apll_clk_id = mt8195_afe_get_mclk_source_clk_id(apll);
if (apll_clk_id < 0)
return apll_clk_id;
/* select apll */
ret = mt8195_afe_set_clk_parent(afe, afe_priv->clk[clk_id],
afe_priv->clk[apll_clk_id]);
if (ret)
return ret;
/* set rate */
ret = mt8195_afe_set_clk_rate(afe, afe_priv->clk[clkdiv_id],
etdm_data->mclk_freq);
} else {
if (etdm_data->mclk_dir == SND_SOC_CLOCK_OUT)
dev_dbg(afe->dev, "%s mclk freq = 0\n", __func__);
}
return ret;
}
static int mtk_dai_etdm_configure(struct mtk_base_afe *afe,
unsigned int rate,
unsigned int channels,
unsigned int bit_width,
int dai_id)
{
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_etdm_priv *etdm_data;
struct etdm_con_reg etdm_reg;
bool slave_mode;
unsigned int etdm_channels;
unsigned int val = 0;
unsigned int mask = 0;
unsigned int bck;
unsigned int wlen = get_etdm_wlen(bit_width);
int ret;
if (!mt8195_afe_etdm_is_valid(dai_id))
return -EINVAL;
etdm_data = afe_priv->dai_priv[dai_id];
slave_mode = etdm_data->slave_mode;
ret = get_etdm_reg(dai_id, &etdm_reg);
if (ret < 0)
return ret;
if (etdm_data->cowork_source_id != COWORK_ETDM_NONE)
slave_mode = true;
dev_dbg(afe->dev, "%s fmt %u data %u lrck %d-%u bck %d, clock %u slv %u\n",
__func__, etdm_data->format, etdm_data->data_mode,
etdm_data->lrck_inv, etdm_data->lrck_width, etdm_data->bck_inv,
etdm_data->clock_mode, etdm_data->slave_mode);
dev_dbg(afe->dev, "%s rate %u channels %u bitwidth %u, id %d\n",
__func__, rate, channels, bit_width, dai_id);
etdm_channels = (etdm_data->data_mode == MTK_DAI_ETDM_DATA_ONE_PIN) ?
get_etdm_ch_fixup(channels) : 2;
bck = rate * etdm_channels * wlen;
if (bck > MT8195_ETDM_NORMAL_MAX_BCK_RATE) {
dev_info(afe->dev, "%s bck rate %u not support\n",
__func__, bck);
return -EINVAL;
}
/* con0 */
mask |= ETDM_CON0_BIT_LEN_MASK;
val |= ETDM_CON0_BIT_LEN(bit_width);
mask |= ETDM_CON0_WORD_LEN_MASK;
val |= ETDM_CON0_WORD_LEN(wlen);
mask |= ETDM_CON0_FORMAT_MASK;
val |= ETDM_CON0_FORMAT(etdm_data->format);
mask |= ETDM_CON0_CH_NUM_MASK;
val |= ETDM_CON0_CH_NUM(etdm_channels);
mask |= ETDM_CON0_SLAVE_MODE;
if (slave_mode) {
if (dai_id == MT8195_AFE_IO_ETDM1_OUT &&
etdm_data->cowork_source_id == COWORK_ETDM_NONE) {
dev_info(afe->dev, "%s id %d only support master mode\n",
__func__, dai_id);
return -EINVAL;
}
val |= ETDM_CON0_SLAVE_MODE;
}
regmap_update_bits(afe->regmap, etdm_reg.con0, mask, val);
if (get_etdm_dir(dai_id) == ETDM_IN)
mtk_dai_etdm_in_configure(afe, rate, channels, dai_id);
else
mtk_dai_etdm_out_configure(afe, rate, channels, dai_id);
return 0;
}
static int mtk_dai_etdm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
int ret = 0;
unsigned int rate = params_rate(params);
unsigned int bit_width = params_width(params);
unsigned int channels = params_channels(params);
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_etdm_priv *mst_etdm_data;
int mst_dai_id;
int slv_dai_id;
int i;
dev_dbg(afe->dev, "%s '%s' period %u-%u\n",
__func__, snd_pcm_stream_str(substream),
params_period_size(params), params_periods(params));
if (is_cowork_mode(dai)) {
mst_dai_id = get_etdm_cowork_master_id(dai);
if (!mt8195_afe_etdm_is_valid(mst_dai_id))
return -EINVAL;
ret = mtk_dai_etdm_mclk_configure(afe, mst_dai_id);
if (ret)
return ret;
ret = mtk_dai_etdm_configure(afe, rate, channels,
bit_width, mst_dai_id);
if (ret)
return ret;
mst_etdm_data = afe_priv->dai_priv[mst_dai_id];
for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) {
slv_dai_id = mst_etdm_data->cowork_slv_id[i];
ret = mtk_dai_etdm_configure(afe, rate, channels,
bit_width, slv_dai_id);
if (ret)
return ret;
ret = mt8195_etdm_sync_mode_configure(afe, slv_dai_id);
if (ret)
return ret;
}
} else {
ret = mtk_dai_etdm_mclk_configure(afe, dai->id);
if (ret)
return ret;
ret = mtk_dai_etdm_configure(afe, rate, channels,
bit_width, dai->id);
}
return ret;
}
static int mtk_dai_etdm_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
int ret = 0;
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_etdm_priv *mst_etdm_data;
int mst_dai_id;
int slv_dai_id;
int i;
dev_dbg(afe->dev, "%s(), cmd %d, dai id %d\n", __func__, cmd, dai->id);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
if (is_cowork_mode(dai)) {
mst_dai_id = get_etdm_cowork_master_id(dai);
if (!mt8195_afe_etdm_is_valid(mst_dai_id))
return -EINVAL;
mst_etdm_data = afe_priv->dai_priv[mst_dai_id];
//open master first
ret |= mt8195_afe_enable_etdm(afe, mst_dai_id);
for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) {
slv_dai_id = mst_etdm_data->cowork_slv_id[i];
ret |= mt8195_afe_enable_etdm(afe, slv_dai_id);
}
} else {
ret = mt8195_afe_enable_etdm(afe, dai->id);
}
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
if (is_cowork_mode(dai)) {
mst_dai_id = get_etdm_cowork_master_id(dai);
if (!mt8195_afe_etdm_is_valid(mst_dai_id))
return -EINVAL;
mst_etdm_data = afe_priv->dai_priv[mst_dai_id];
for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) {
slv_dai_id = mst_etdm_data->cowork_slv_id[i];
ret |= mt8195_afe_disable_etdm(afe, slv_dai_id);
}
// close master at last
ret |= mt8195_afe_disable_etdm(afe, mst_dai_id);
} else {
ret = mt8195_afe_disable_etdm(afe, dai->id);
}
break;
default:
break;
}
return ret;
}
static int mtk_dai_etdm_cal_mclk(struct mtk_base_afe *afe, int freq, int dai_id)
{
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_etdm_priv *etdm_data;
int apll;
int apll_rate;
if (!mt8195_afe_etdm_is_valid(dai_id))
return -EINVAL;
etdm_data = afe_priv->dai_priv[dai_id];
if (freq == 0) {
etdm_data->mclk_freq = freq;
return 0;
}
apll = mt8195_afe_get_default_mclk_source_by_rate(freq);
apll_rate = mt8195_afe_get_mclk_source_rate(afe, apll);
if (freq > apll_rate) {
dev_info(afe->dev, "freq %d > apll rate %d\n", freq, apll_rate);
return -EINVAL;
}
if (apll_rate % freq != 0) {
dev_info(afe->dev, "APLL%d cannot generate freq Hz\n", apll);
return -EINVAL;
}
etdm_data->mclk_apll = apll;
etdm_data->mclk_freq = freq;
return 0;
}
static int mtk_dai_etdm_set_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_etdm_priv *etdm_data;
int dai_id;
dev_dbg(dai->dev, "%s id %d freq %u, dir %d\n",
__func__, dai->id, freq, dir);
if (is_cowork_mode(dai))
dai_id = get_etdm_cowork_master_id(dai);
else
dai_id = dai->id;
if (!mt8195_afe_etdm_is_valid(dai_id))
return -EINVAL;
etdm_data = afe_priv->dai_priv[dai_id];
etdm_data->mclk_dir = dir;
return mtk_dai_etdm_cal_mclk(afe, freq, dai_id);
}
static int mtk_dai_etdm_set_tdm_slot(struct snd_soc_dai *dai,
unsigned int tx_mask, unsigned int rx_mask,
int slots, int slot_width)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_etdm_priv *etdm_data;
if (!mt8195_afe_etdm_is_valid(dai->id))
return -EINVAL;
etdm_data = afe_priv->dai_priv[dai->id];
dev_dbg(dai->dev, "%s id %d slot_width %d\n",
__func__, dai->id, slot_width);
etdm_data->slots = slots;
etdm_data->lrck_width = slot_width;
return 0;
}
static int mtk_dai_etdm_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_etdm_priv *etdm_data;
if (!mt8195_afe_etdm_is_valid(dai->id))
return -EINVAL;
etdm_data = afe_priv->dai_priv[dai->id];
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
etdm_data->format = MTK_DAI_ETDM_FORMAT_I2S;
break;
case SND_SOC_DAIFMT_LEFT_J:
etdm_data->format = MTK_DAI_ETDM_FORMAT_LJ;
break;
case SND_SOC_DAIFMT_RIGHT_J:
etdm_data->format = MTK_DAI_ETDM_FORMAT_RJ;
break;
case SND_SOC_DAIFMT_DSP_A:
etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPA;
break;
case SND_SOC_DAIFMT_DSP_B:
etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPB;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
etdm_data->bck_inv = false;
etdm_data->lrck_inv = false;
break;
case SND_SOC_DAIFMT_NB_IF:
etdm_data->bck_inv = false;
etdm_data->lrck_inv = true;
break;
case SND_SOC_DAIFMT_IB_NF:
etdm_data->bck_inv = true;
etdm_data->lrck_inv = false;
break;
case SND_SOC_DAIFMT_IB_IF:
etdm_data->bck_inv = true;
etdm_data->lrck_inv = true;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BC_FC:
etdm_data->slave_mode = true;
break;
case SND_SOC_DAIFMT_BP_FP:
etdm_data->slave_mode = false;
break;
default:
return -EINVAL;
}
return 0;
}
static int mtk_dai_hdmitx_dptx_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8195_afe_private *afe_priv = afe->platform_priv;
int cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id);
if (cg_id >= 0)
mt8195_afe_enable_clk(afe, afe_priv->clk[cg_id]);
mtk_dai_etdm_enable_mclk(afe, dai->id);
return 0;
}
static void mtk_dai_hdmitx_dptx_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8195_afe_private *afe_priv = afe->platform_priv;
int cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id);
mtk_dai_etdm_disable_mclk(afe, dai->id);
if (cg_id >= 0)
mt8195_afe_disable_clk(afe, afe_priv->clk[cg_id]);
}
static unsigned int mtk_dai_get_dptx_ch_en(unsigned int channel)
{
switch (channel) {
case 1 ... 2:
return AFE_DPTX_CON_CH_EN_2CH;
case 3 ... 4:
return AFE_DPTX_CON_CH_EN_4CH;
case 5 ... 6:
return AFE_DPTX_CON_CH_EN_6CH;
case 7 ... 8:
return AFE_DPTX_CON_CH_EN_8CH;
default:
return AFE_DPTX_CON_CH_EN_2CH;
}
}
static unsigned int mtk_dai_get_dptx_ch(unsigned int ch)
{
return (ch > 2) ?
AFE_DPTX_CON_CH_NUM_8CH : AFE_DPTX_CON_CH_NUM_2CH;
}
static unsigned int mtk_dai_get_dptx_wlen(snd_pcm_format_t format)
{
return snd_pcm_format_physical_width(format) <= 16 ?
AFE_DPTX_CON_16BIT : AFE_DPTX_CON_24BIT;
}
static int mtk_dai_hdmitx_dptx_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_etdm_priv *etdm_data;
unsigned int rate = params_rate(params);
unsigned int channels = params_channels(params);
snd_pcm_format_t format = params_format(params);
int width = snd_pcm_format_physical_width(format);
int ret = 0;
if (!mt8195_afe_hdmitx_dptx_is_valid(dai->id))
return -EINVAL;
etdm_data = afe_priv->dai_priv[dai->id];
/* dptx configure */
if (dai->id == MT8195_AFE_IO_DPTX) {
regmap_update_bits(afe->regmap, AFE_DPTX_CON,
AFE_DPTX_CON_CH_EN_MASK,
mtk_dai_get_dptx_ch_en(channels));
regmap_update_bits(afe->regmap, AFE_DPTX_CON,
AFE_DPTX_CON_CH_NUM_MASK,
mtk_dai_get_dptx_ch(channels));
regmap_update_bits(afe->regmap, AFE_DPTX_CON,
AFE_DPTX_CON_16BIT_MASK,
mtk_dai_get_dptx_wlen(format));
if (mtk_dai_get_dptx_ch(channels) == AFE_DPTX_CON_CH_NUM_8CH) {
etdm_data->data_mode = MTK_DAI_ETDM_DATA_ONE_PIN;
channels = 8;
} else {
channels = 2;
}
} else {
etdm_data->data_mode = MTK_DAI_ETDM_DATA_MULTI_PIN;
}
ret = mtk_dai_etdm_mclk_configure(afe, dai->id);
if (ret)
return ret;
ret = mtk_dai_etdm_configure(afe, rate, channels, width, dai->id);
return ret;
}
static int mtk_dai_hdmitx_dptx_trigger(struct snd_pcm_substream *substream,
int cmd,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
int ret = 0;
dev_dbg(afe->dev, "%s(), cmd %d, dai id %d\n", __func__, cmd, dai->id);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
/* enable dptx interface */
if (dai->id == MT8195_AFE_IO_DPTX)
regmap_update_bits(afe->regmap, AFE_DPTX_CON,
AFE_DPTX_CON_ON_MASK,
AFE_DPTX_CON_ON);
/* enable etdm_out3 */
ret = mt8195_afe_enable_etdm(afe, dai->id);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
/* disable etdm_out3 */
ret = mt8195_afe_disable_etdm(afe, dai->id);
/* disable dptx interface */
if (dai->id == MT8195_AFE_IO_DPTX)
regmap_update_bits(afe->regmap, AFE_DPTX_CON,
AFE_DPTX_CON_ON_MASK, 0);
break;
default:
return -EINVAL;
}
return ret;
}
static int mtk_dai_hdmitx_dptx_set_sysclk(struct snd_soc_dai *dai,
int clk_id,
unsigned int freq,
int dir)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_etdm_priv *etdm_data;
if (!mt8195_afe_hdmitx_dptx_is_valid(dai->id))
return -EINVAL;
etdm_data = afe_priv->dai_priv[dai->id];
dev_dbg(dai->dev, "%s id %d freq %u, dir %d\n",
__func__, dai->id, freq, dir);
etdm_data->mclk_dir = dir;
return mtk_dai_etdm_cal_mclk(afe, freq, dai->id);
}
/* dai driver */
#define MTK_ETDM_RATES (SNDRV_PCM_RATE_8000_384000)
#define MTK_ETDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
static int mtk_dai_etdm_probe(struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_etdm_priv *etdm_data;
dev_dbg(dai->dev, "%s id %d\n", __func__, dai->id);
if (!mt8195_afe_etdm_is_valid(dai->id))
return -EINVAL;
etdm_data = afe_priv->dai_priv[dai->id];
if (etdm_data->mclk_freq) {
dev_dbg(afe->dev, "MCLK always on, rate %d\n",
etdm_data->mclk_freq);
pm_runtime_get_sync(afe->dev);
mtk_dai_etdm_mclk_configure(afe, dai->id);
mtk_dai_etdm_enable_mclk(afe, dai->id);
pm_runtime_put_sync(afe->dev);
}
return 0;
}
static const struct snd_soc_dai_ops mtk_dai_hdmitx_dptx_ops = {
.startup = mtk_dai_hdmitx_dptx_startup,
.shutdown = mtk_dai_hdmitx_dptx_shutdown,
.hw_params = mtk_dai_hdmitx_dptx_hw_params,
.trigger = mtk_dai_hdmitx_dptx_trigger,
.set_sysclk = mtk_dai_hdmitx_dptx_set_sysclk,
.set_fmt = mtk_dai_etdm_set_fmt,
};
static const struct snd_soc_dai_ops mtk_dai_hdmitx_dptx_ops2 = {
.probe = mtk_dai_etdm_probe,
.startup = mtk_dai_hdmitx_dptx_startup,
.shutdown = mtk_dai_hdmitx_dptx_shutdown,
.hw_params = mtk_dai_hdmitx_dptx_hw_params,
.trigger = mtk_dai_hdmitx_dptx_trigger,
.set_sysclk = mtk_dai_hdmitx_dptx_set_sysclk,
.set_fmt = mtk_dai_etdm_set_fmt,
};
static const struct snd_soc_dai_ops mtk_dai_etdm_ops = {
.probe = mtk_dai_etdm_probe,
.startup = mtk_dai_etdm_startup,
.shutdown = mtk_dai_etdm_shutdown,
.hw_params = mtk_dai_etdm_hw_params,
.trigger = mtk_dai_etdm_trigger,
.set_sysclk = mtk_dai_etdm_set_sysclk,
.set_fmt = mtk_dai_etdm_set_fmt,
.set_tdm_slot = mtk_dai_etdm_set_tdm_slot,
};
static struct snd_soc_dai_driver mtk_dai_etdm_driver[] = {
{
.name = "DPTX",
.id = MT8195_AFE_IO_DPTX,
.playback = {
.stream_name = "DPTX Playback",
.channels_min = 1,
.channels_max = 8,
.rates = MTK_ETDM_RATES,
.formats = MTK_ETDM_FORMATS,
},
.ops = &mtk_dai_hdmitx_dptx_ops,
},
{
.name = "ETDM1_IN",
.id = MT8195_AFE_IO_ETDM1_IN,
.capture = {
.stream_name = "ETDM1 Capture",
.channels_min = 1,
.channels_max = 24,
.rates = MTK_ETDM_RATES,
.formats = MTK_ETDM_FORMATS,
},
.ops = &mtk_dai_etdm_ops,
},
{
.name = "ETDM2_IN",
.id = MT8195_AFE_IO_ETDM2_IN,
.capture = {
.stream_name = "ETDM2 Capture",
.channels_min = 1,
.channels_max = 16,
.rates = MTK_ETDM_RATES,
.formats = MTK_ETDM_FORMATS,
},
.ops = &mtk_dai_etdm_ops,
},
{
.name = "ETDM1_OUT",
.id = MT8195_AFE_IO_ETDM1_OUT,
.playback = {
.stream_name = "ETDM1 Playback",
.channels_min = 1,
.channels_max = 24,
.rates = MTK_ETDM_RATES,
.formats = MTK_ETDM_FORMATS,
},
.ops = &mtk_dai_etdm_ops,
},
{
.name = "ETDM2_OUT",
.id = MT8195_AFE_IO_ETDM2_OUT,
.playback = {
.stream_name = "ETDM2 Playback",
.channels_min = 1,
.channels_max = 24,
.rates = MTK_ETDM_RATES,
.formats = MTK_ETDM_FORMATS,
},
.ops = &mtk_dai_etdm_ops,
},
{
.name = "ETDM3_OUT",
.id = MT8195_AFE_IO_ETDM3_OUT,
.playback = {
.stream_name = "ETDM3 Playback",
.channels_min = 1,
.channels_max = 8,
.rates = MTK_ETDM_RATES,
.formats = MTK_ETDM_FORMATS,
},
.ops = &mtk_dai_hdmitx_dptx_ops2,
},
};
static void mt8195_etdm_update_sync_info(struct mtk_base_afe *afe)
{
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_etdm_priv *etdm_data;
struct mtk_dai_etdm_priv *mst_data;
int i;
int mst_dai_id;
for (i = MT8195_AFE_IO_ETDM_START; i < MT8195_AFE_IO_ETDM_END; i++) {
etdm_data = afe_priv->dai_priv[i];
if (etdm_data->cowork_source_id != COWORK_ETDM_NONE) {
mst_dai_id = etdm_data->cowork_source_id;
if (!mt8195_afe_etdm_is_valid(mst_dai_id)) {
dev_err(afe->dev, "%s invalid dai id %d\n",
__func__, mst_dai_id);
return;
}
mst_data = afe_priv->dai_priv[mst_dai_id];
if (mst_data->cowork_source_id != COWORK_ETDM_NONE)
dev_info(afe->dev, "%s [%d] wrong sync source\n"
, __func__, i);
mst_data->cowork_slv_id[mst_data->cowork_slv_count] = i;
mst_data->cowork_slv_count++;
}
}
}
static void mt8195_dai_etdm_parse_of(struct mtk_base_afe *afe)
{
const struct device_node *of_node = afe->dev->of_node;
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_etdm_priv *etdm_data;
int i, j;
char prop[48];
u8 disable_chn[MT8195_ETDM_MAX_CHANNELS];
int max_chn = MT8195_ETDM_MAX_CHANNELS;
u32 sel;
int ret;
int dai_id;
unsigned int sync_id;
struct {
const char *name;
const unsigned int sync_id;
} of_afe_etdms[MT8195_AFE_IO_ETDM_NUM] = {
{"etdm-in1", ETDM_SYNC_FROM_IN1},
{"etdm-in2", ETDM_SYNC_FROM_IN2},
{"etdm-out1", ETDM_SYNC_FROM_OUT1},
{"etdm-out2", ETDM_SYNC_FROM_OUT2},
{"etdm-out3", ETDM_SYNC_FROM_OUT3},
};
for (i = 0; i < MT8195_AFE_IO_ETDM_NUM; i++) {
dai_id = ETDM_TO_DAI_ID(i);
if (!mt8195_afe_etdm_is_valid(dai_id)) {
dev_err(afe->dev, "%s invalid dai id %d\n",
__func__, dai_id);
return;
}
etdm_data = afe_priv->dai_priv[dai_id];
ret = snprintf(prop, sizeof(prop),
"mediatek,%s-mclk-always-on-rate",
of_afe_etdms[i].name);
if (ret < 0) {
dev_info(afe->dev, "%s snprintf err=%d\n",
__func__, ret);
return;
}
ret = of_property_read_u32(of_node, prop, &sel);
if (ret == 0) {
etdm_data->mclk_dir = SND_SOC_CLOCK_OUT;
if (mtk_dai_etdm_cal_mclk(afe, sel, dai_id))
dev_info(afe->dev, "%s unsupported mclk %uHz\n",
__func__, sel);
}
ret = snprintf(prop, sizeof(prop),
"mediatek,%s-multi-pin-mode",
of_afe_etdms[i].name);
if (ret < 0) {
dev_info(afe->dev, "%s snprintf err=%d\n",
__func__, ret);
return;
}
etdm_data->data_mode = of_property_read_bool(of_node, prop);
ret = snprintf(prop, sizeof(prop),
"mediatek,%s-cowork-source",
of_afe_etdms[i].name);
if (ret < 0) {
dev_info(afe->dev, "%s snprintf err=%d\n",
__func__, ret);
return;
}
ret = of_property_read_u32(of_node, prop, &sel);
if (ret == 0) {
if (sel >= MT8195_AFE_IO_ETDM_NUM) {
dev_info(afe->dev, "%s invalid id=%d\n",
__func__, sel);
etdm_data->cowork_source_id = COWORK_ETDM_NONE;
} else {
sync_id = of_afe_etdms[sel].sync_id;
etdm_data->cowork_source_id =
sync_to_dai_id(sync_id);
}
} else {
etdm_data->cowork_source_id = COWORK_ETDM_NONE;
}
}
/* etdm in only */
for (i = 0; i < 2; i++) {
dai_id = ETDM_TO_DAI_ID(i);
etdm_data = afe_priv->dai_priv[dai_id];
ret = snprintf(prop, sizeof(prop),
"mediatek,%s-chn-disabled",
of_afe_etdms[i].name);
if (ret < 0) {
dev_info(afe->dev, "%s snprintf err=%d\n",
__func__, ret);
return;
}
ret = of_property_read_variable_u8_array(of_node, prop,
disable_chn,
1, max_chn);
if (ret < 0)
continue;
for (j = 0; j < ret; j++) {
if (disable_chn[j] >= MT8195_ETDM_MAX_CHANNELS)
dev_info(afe->dev, "%s [%d] invalid chn %u\n",
__func__, j, disable_chn[j]);
else
etdm_data->in_disable_ch[disable_chn[j]] = true;
}
}
mt8195_etdm_update_sync_info(afe);
}
static int init_etdm_priv_data(struct mtk_base_afe *afe)
{
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_etdm_priv *etdm_priv;
int i;
for (i = MT8195_AFE_IO_ETDM_START; i < MT8195_AFE_IO_ETDM_END; i++) {
etdm_priv = devm_kzalloc(afe->dev,
sizeof(struct mtk_dai_etdm_priv),
GFP_KERNEL);
if (!etdm_priv)
return -ENOMEM;
afe_priv->dai_priv[i] = etdm_priv;
}
afe_priv->dai_priv[MT8195_AFE_IO_DPTX] =
afe_priv->dai_priv[MT8195_AFE_IO_ETDM3_OUT];
mt8195_dai_etdm_parse_of(afe);
return 0;
}
int mt8195_dai_etdm_register(struct mtk_base_afe *afe)
{
struct mtk_base_afe_dai *dai;
dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
if (!dai)
return -ENOMEM;
list_add(&dai->list, &afe->sub_dais);
dai->dai_drivers = mtk_dai_etdm_driver;
dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_etdm_driver);
dai->dapm_widgets = mtk_dai_etdm_widgets;
dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_etdm_widgets);
dai->dapm_routes = mtk_dai_etdm_routes;
dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_etdm_routes);
dai->controls = mtk_dai_etdm_controls;
dai->num_controls = ARRAY_SIZE(mtk_dai_etdm_controls);
return init_etdm_priv_data(afe);
}
| linux-master | sound/soc/mediatek/mt8195/mt8195-dai-etdm.c |
// SPDX-License-Identifier: GPL-2.0
/*
* MediaTek ALSA SoC Audio DAI ADDA Control
*
* Copyright (c) 2021 MediaTek Inc.
* Author: Bicycle Tsai <[email protected]>
* Trevor Wu <[email protected]>
*/
#include <linux/delay.h>
#include <linux/regmap.h>
#include "mt8195-afe-clk.h"
#include "mt8195-afe-common.h"
#include "mt8195-reg.h"
#define ADDA_DL_GAIN_LOOPBACK 0x1800
#define ADDA_HIRES_THRES 48000
enum {
SUPPLY_SEQ_CLOCK_SEL,
SUPPLY_SEQ_CLOCK_ON,
SUPPLY_SEQ_ADDA_DL_ON,
SUPPLY_SEQ_ADDA_MTKAIF_CFG,
SUPPLY_SEQ_ADDA_UL_ON,
SUPPLY_SEQ_ADDA_AFE_ON,
};
enum {
MTK_AFE_ADDA_DL_RATE_8K = 0,
MTK_AFE_ADDA_DL_RATE_11K = 1,
MTK_AFE_ADDA_DL_RATE_12K = 2,
MTK_AFE_ADDA_DL_RATE_16K = 3,
MTK_AFE_ADDA_DL_RATE_22K = 4,
MTK_AFE_ADDA_DL_RATE_24K = 5,
MTK_AFE_ADDA_DL_RATE_32K = 6,
MTK_AFE_ADDA_DL_RATE_44K = 7,
MTK_AFE_ADDA_DL_RATE_48K = 8,
MTK_AFE_ADDA_DL_RATE_96K = 9,
MTK_AFE_ADDA_DL_RATE_192K = 10,
};
enum {
MTK_AFE_ADDA_UL_RATE_8K = 0,
MTK_AFE_ADDA_UL_RATE_16K = 1,
MTK_AFE_ADDA_UL_RATE_32K = 2,
MTK_AFE_ADDA_UL_RATE_48K = 3,
MTK_AFE_ADDA_UL_RATE_96K = 4,
MTK_AFE_ADDA_UL_RATE_192K = 5,
};
enum {
DELAY_DATA_MISO1 = 0,
DELAY_DATA_MISO0 = 1,
DELAY_DATA_MISO2 = 1,
};
enum {
MTK_AFE_ADDA,
MTK_AFE_ADDA6,
};
struct mtk_dai_adda_priv {
bool hires_required;
};
static unsigned int afe_adda_dl_rate_transform(struct mtk_base_afe *afe,
unsigned int rate)
{
switch (rate) {
case 8000:
return MTK_AFE_ADDA_DL_RATE_8K;
case 11025:
return MTK_AFE_ADDA_DL_RATE_11K;
case 12000:
return MTK_AFE_ADDA_DL_RATE_12K;
case 16000:
return MTK_AFE_ADDA_DL_RATE_16K;
case 22050:
return MTK_AFE_ADDA_DL_RATE_22K;
case 24000:
return MTK_AFE_ADDA_DL_RATE_24K;
case 32000:
return MTK_AFE_ADDA_DL_RATE_32K;
case 44100:
return MTK_AFE_ADDA_DL_RATE_44K;
case 48000:
return MTK_AFE_ADDA_DL_RATE_48K;
case 96000:
return MTK_AFE_ADDA_DL_RATE_96K;
case 192000:
return MTK_AFE_ADDA_DL_RATE_192K;
default:
dev_info(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
__func__, rate);
return MTK_AFE_ADDA_DL_RATE_48K;
}
}
static unsigned int afe_adda_ul_rate_transform(struct mtk_base_afe *afe,
unsigned int rate)
{
switch (rate) {
case 8000:
return MTK_AFE_ADDA_UL_RATE_8K;
case 16000:
return MTK_AFE_ADDA_UL_RATE_16K;
case 32000:
return MTK_AFE_ADDA_UL_RATE_32K;
case 48000:
return MTK_AFE_ADDA_UL_RATE_48K;
case 96000:
return MTK_AFE_ADDA_UL_RATE_96K;
case 192000:
return MTK_AFE_ADDA_UL_RATE_192K;
default:
dev_info(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
__func__, rate);
return MTK_AFE_ADDA_UL_RATE_48K;
}
}
static int mt8195_adda_mtkaif_init(struct mtk_base_afe *afe)
{
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtkaif_param *param = &afe_priv->mtkaif_params;
int delay_data;
int delay_cycle;
unsigned int mask = 0;
unsigned int val = 0;
/* set rx protocol 2 & mtkaif_rxif_clkinv_adc inverse */
mask = (MTKAIF_RXIF_CLKINV_ADC | MTKAIF_RXIF_PROTOCOL2);
val = (MTKAIF_RXIF_CLKINV_ADC | MTKAIF_RXIF_PROTOCOL2);
regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_CFG0, mask, val);
regmap_update_bits(afe->regmap, AFE_ADDA6_MTKAIF_CFG0, mask, val);
mask = RG_RX_PROTOCOL2;
val = RG_RX_PROTOCOL2;
regmap_update_bits(afe->regmap, AFE_AUD_PAD_TOP, mask, val);
if (!param->mtkaif_calibration_ok) {
dev_info(afe->dev, "%s(), calibration fail\n", __func__);
return 0;
}
/* set delay for ch1, ch2 */
if (param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_0] >=
param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_1]) {
delay_data = DELAY_DATA_MISO1;
delay_cycle =
param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_0] -
param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_1];
} else {
delay_data = DELAY_DATA_MISO0;
delay_cycle =
param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_1] -
param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_0];
}
val = 0;
mask = (MTKAIF_RXIF_DELAY_DATA | MTKAIF_RXIF_DELAY_CYCLE_MASK);
val |= MTKAIF_RXIF_DELAY_CYCLE(delay_cycle) &
MTKAIF_RXIF_DELAY_CYCLE_MASK;
val |= delay_data << MTKAIF_RXIF_DELAY_DATA_SHIFT;
regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG2, mask, val);
/* set delay between ch3 and ch2 */
if (param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_2] >=
param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_1]) {
delay_data = DELAY_DATA_MISO1;
delay_cycle =
param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_2] -
param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_1];
} else {
delay_data = DELAY_DATA_MISO2;
delay_cycle =
param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_1] -
param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_2];
}
val = 0;
mask = (MTKAIF_RXIF_DELAY_DATA | MTKAIF_RXIF_DELAY_CYCLE_MASK);
val |= MTKAIF_RXIF_DELAY_CYCLE(delay_cycle) &
MTKAIF_RXIF_DELAY_CYCLE_MASK;
val |= delay_data << MTKAIF_RXIF_DELAY_DATA_SHIFT;
regmap_update_bits(afe->regmap, AFE_ADDA6_MTKAIF_RX_CFG2, mask, val);
return 0;
}
static int mtk_adda_mtkaif_cfg_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
__func__, w->name, event);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
mt8195_adda_mtkaif_init(afe);
break;
default:
break;
}
return 0;
}
static int mtk_adda_dl_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
__func__, w->name, event);
switch (event) {
case SND_SOC_DAPM_POST_PMD:
/* should delayed 1/fs(smallest is 8k) = 125us before afe off */
usleep_range(125, 135);
break;
default:
break;
}
return 0;
}
static void mtk_adda_ul_mictype(struct mtk_base_afe *afe, int adda, bool dmic)
{
unsigned int reg = 0;
unsigned int mask = 0;
unsigned int val = 0;
switch (adda) {
case MTK_AFE_ADDA:
reg = AFE_ADDA_UL_SRC_CON0;
break;
case MTK_AFE_ADDA6:
reg = AFE_ADDA6_UL_SRC_CON0;
break;
default:
dev_info(afe->dev, "%s(), wrong parameter\n", __func__);
return;
}
mask = (UL_SDM3_LEVEL_CTL | UL_MODE_3P25M_CH1_CTL |
UL_MODE_3P25M_CH2_CTL);
/* turn on dmic, ch1, ch2 */
if (dmic)
val = mask;
regmap_update_bits(afe->regmap, reg, mask, val);
}
static int mtk_adda_ul_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtkaif_param *param = &afe_priv->mtkaif_params;
dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
__func__, w->name, event);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
mtk_adda_ul_mictype(afe, MTK_AFE_ADDA, param->mtkaif_dmic_on);
break;
case SND_SOC_DAPM_POST_PMD:
/* should delayed 1/fs(smallest is 8k) = 125us before afe off */
usleep_range(125, 135);
break;
default:
break;
}
return 0;
}
static int mtk_adda6_ul_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtkaif_param *param = &afe_priv->mtkaif_params;
unsigned int val;
dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
__func__, w->name, event);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
mtk_adda_ul_mictype(afe, MTK_AFE_ADDA6, param->mtkaif_dmic_on);
val = (param->mtkaif_adda6_only ?
ADDA6_MTKAIF_RX_SYNC_WORD2_DISABLE : 0);
regmap_update_bits(afe->regmap,
AFE_ADDA_MTKAIF_SYNCWORD_CFG,
ADDA6_MTKAIF_RX_SYNC_WORD2_DISABLE,
val);
break;
case SND_SOC_DAPM_POST_PMD:
/* should delayed 1/fs(smallest is 8k) = 125us before afe off */
usleep_range(125, 135);
break;
default:
break;
}
return 0;
}
static int mtk_audio_hires_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct clk *clk = afe_priv->clk[MT8195_CLK_TOP_AUDIO_H_SEL];
struct clk *clk_parent;
dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
__func__, w->name, event);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
clk_parent = afe_priv->clk[MT8195_CLK_TOP_APLL1];
break;
case SND_SOC_DAPM_POST_PMD:
clk_parent = afe_priv->clk[MT8195_CLK_XTAL_26M];
break;
default:
return 0;
}
mt8195_afe_set_clk_parent(afe, clk, clk_parent);
return 0;
}
static struct mtk_dai_adda_priv *get_adda_priv_by_name(struct mtk_base_afe *afe,
const char *name)
{
struct mt8195_afe_private *afe_priv = afe->platform_priv;
int dai_id;
if (strstr(name, "aud_adc_hires"))
dai_id = MT8195_AFE_IO_UL_SRC1;
else if (strstr(name, "aud_adda6_adc_hires"))
dai_id = MT8195_AFE_IO_UL_SRC2;
else if (strstr(name, "aud_dac_hires"))
dai_id = MT8195_AFE_IO_DL_SRC;
else
return NULL;
return afe_priv->dai_priv[dai_id];
}
static int mtk_afe_adda_hires_connect(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_dapm_widget *w = source;
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mtk_dai_adda_priv *adda_priv;
adda_priv = get_adda_priv_by_name(afe, w->name);
if (!adda_priv) {
dev_info(afe->dev, "adda_priv == NULL");
return 0;
}
return (adda_priv->hires_required) ? 1 : 0;
}
static const struct snd_kcontrol_new mtk_dai_adda_o176_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN176, 0, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I002 Switch", AFE_CONN176, 2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN176, 20, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN176, 22, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN176_2, 6, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_adda_o177_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN177, 1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I003 Switch", AFE_CONN177, 3, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN177, 21, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN177, 23, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN177_2, 7, 1, 0),
};
static const char * const adda_dlgain_mux_map[] = {
"Bypass", "Connect",
};
static SOC_ENUM_SINGLE_DECL(adda_dlgain_mux_map_enum,
SND_SOC_NOPM, 0,
adda_dlgain_mux_map);
static const struct snd_kcontrol_new adda_dlgain_mux_control =
SOC_DAPM_ENUM("DL_GAIN_MUX", adda_dlgain_mux_map_enum);
static const struct snd_soc_dapm_widget mtk_dai_adda_widgets[] = {
SND_SOC_DAPM_MIXER("I168", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I169", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I170", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I171", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("O176", SND_SOC_NOPM, 0, 0,
mtk_dai_adda_o176_mix,
ARRAY_SIZE(mtk_dai_adda_o176_mix)),
SND_SOC_DAPM_MIXER("O177", SND_SOC_NOPM, 0, 0,
mtk_dai_adda_o177_mix,
ARRAY_SIZE(mtk_dai_adda_o177_mix)),
SND_SOC_DAPM_SUPPLY_S("ADDA Enable", SUPPLY_SEQ_ADDA_AFE_ON,
AFE_ADDA_UL_DL_CON0,
ADDA_AFE_ON_SHIFT, 0,
NULL,
0),
SND_SOC_DAPM_SUPPLY_S("ADDA Playback Enable", SUPPLY_SEQ_ADDA_DL_ON,
AFE_ADDA_DL_SRC2_CON0,
DL_2_SRC_ON_TMP_CTRL_PRE_SHIFT, 0,
mtk_adda_dl_event,
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("ADDA Capture Enable", SUPPLY_SEQ_ADDA_UL_ON,
AFE_ADDA_UL_SRC_CON0,
UL_SRC_ON_TMP_CTL_SHIFT, 0,
mtk_adda_ul_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("ADDA6 Capture Enable", SUPPLY_SEQ_ADDA_UL_ON,
AFE_ADDA6_UL_SRC_CON0,
UL_SRC_ON_TMP_CTL_SHIFT, 0,
mtk_adda6_ul_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("AUDIO_HIRES", SUPPLY_SEQ_CLOCK_SEL,
SND_SOC_NOPM,
0, 0,
mtk_audio_hires_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("ADDA_MTKAIF_CFG", SUPPLY_SEQ_ADDA_MTKAIF_CFG,
SND_SOC_NOPM,
0, 0,
mtk_adda_mtkaif_cfg_event,
SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_MUX("DL_GAIN_MUX", SND_SOC_NOPM, 0, 0,
&adda_dlgain_mux_control),
SND_SOC_DAPM_PGA("DL_GAIN", AFE_ADDA_DL_SRC2_CON0,
DL_2_GAIN_ON_CTL_PRE_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_INPUT("ADDA_INPUT"),
SND_SOC_DAPM_OUTPUT("ADDA_OUTPUT"),
SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac"),
SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc"),
SND_SOC_DAPM_CLOCK_SUPPLY("aud_adda6_adc"),
SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_hires"),
SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc_hires"),
SND_SOC_DAPM_CLOCK_SUPPLY("aud_adda6_adc_hires"),
};
static const struct snd_soc_dapm_route mtk_dai_adda_routes[] = {
{"ADDA Capture", NULL, "ADDA Enable"},
{"ADDA Capture", NULL, "ADDA Capture Enable"},
{"ADDA Capture", NULL, "ADDA_MTKAIF_CFG"},
{"ADDA Capture", NULL, "aud_adc"},
{"ADDA Capture", NULL, "aud_adc_hires", mtk_afe_adda_hires_connect},
{"aud_adc_hires", NULL, "AUDIO_HIRES"},
{"ADDA6 Capture", NULL, "ADDA Enable"},
{"ADDA6 Capture", NULL, "ADDA6 Capture Enable"},
{"ADDA6 Capture", NULL, "ADDA_MTKAIF_CFG"},
{"ADDA6 Capture", NULL, "aud_adda6_adc"},
{"ADDA6 Capture", NULL, "aud_adda6_adc_hires",
mtk_afe_adda_hires_connect},
{"aud_adda6_adc_hires", NULL, "AUDIO_HIRES"},
{"I168", NULL, "ADDA Capture"},
{"I169", NULL, "ADDA Capture"},
{"I170", NULL, "ADDA6 Capture"},
{"I171", NULL, "ADDA6 Capture"},
{"ADDA Playback", NULL, "ADDA Enable"},
{"ADDA Playback", NULL, "ADDA Playback Enable"},
{"ADDA Playback", NULL, "aud_dac"},
{"ADDA Playback", NULL, "aud_dac_hires", mtk_afe_adda_hires_connect},
{"aud_dac_hires", NULL, "AUDIO_HIRES"},
{"DL_GAIN", NULL, "O176"},
{"DL_GAIN", NULL, "O177"},
{"DL_GAIN_MUX", "Bypass", "O176"},
{"DL_GAIN_MUX", "Bypass", "O177"},
{"DL_GAIN_MUX", "Connect", "DL_GAIN"},
{"ADDA Playback", NULL, "DL_GAIN_MUX"},
{"O176", "I000 Switch", "I000"},
{"O177", "I001 Switch", "I001"},
{"O176", "I002 Switch", "I002"},
{"O177", "I003 Switch", "I003"},
{"O176", "I020 Switch", "I020"},
{"O177", "I021 Switch", "I021"},
{"O176", "I022 Switch", "I022"},
{"O177", "I023 Switch", "I023"},
{"O176", "I070 Switch", "I070"},
{"O177", "I071 Switch", "I071"},
{"ADDA Capture", NULL, "ADDA_INPUT"},
{"ADDA6 Capture", NULL, "ADDA_INPUT"},
{"ADDA_OUTPUT", NULL, "ADDA Playback"},
};
static int mt8195_adda_dl_gain_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
unsigned int reg = AFE_ADDA_DL_SRC2_CON1;
unsigned int mask = DL_2_GAIN_CTL_PRE_MASK;
unsigned int value = (unsigned int)(ucontrol->value.integer.value[0]);
regmap_update_bits(afe->regmap, reg, mask, DL_2_GAIN_CTL_PRE(value));
return 0;
}
static int mt8195_adda_dl_gain_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
unsigned int reg = AFE_ADDA_DL_SRC2_CON1;
unsigned int mask = DL_2_GAIN_CTL_PRE_MASK;
unsigned int value = 0;
regmap_read(afe->regmap, reg, &value);
ucontrol->value.integer.value[0] = ((value & mask) >>
DL_2_GAIN_CTL_PRE_SHIFT);
return 0;
}
static int mt8195_adda6_only_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtkaif_param *param = &afe_priv->mtkaif_params;
ucontrol->value.integer.value[0] = param->mtkaif_adda6_only;
return 0;
}
static int mt8195_adda6_only_set(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtkaif_param *param = &afe_priv->mtkaif_params;
int mtkaif_adda6_only;
mtkaif_adda6_only = ucontrol->value.integer.value[0];
dev_info(afe->dev, "%s(), kcontrol name %s, mtkaif_adda6_only %d\n",
__func__, kcontrol->id.name, mtkaif_adda6_only);
param->mtkaif_adda6_only = mtkaif_adda6_only;
return 0;
}
static int mt8195_adda_dmic_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtkaif_param *param = &afe_priv->mtkaif_params;
ucontrol->value.integer.value[0] = param->mtkaif_dmic_on;
return 0;
}
static int mt8195_adda_dmic_set(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtkaif_param *param = &afe_priv->mtkaif_params;
int dmic_on;
dmic_on = ucontrol->value.integer.value[0];
dev_dbg(afe->dev, "%s(), kcontrol name %s, dmic_on %d\n",
__func__, kcontrol->id.name, dmic_on);
param->mtkaif_dmic_on = dmic_on;
return 0;
}
static const struct snd_kcontrol_new mtk_dai_adda_controls[] = {
SOC_SINGLE_EXT("ADDA_DL_Gain", SND_SOC_NOPM, 0, 65535, 0,
mt8195_adda_dl_gain_get, mt8195_adda_dl_gain_put),
SOC_SINGLE_BOOL_EXT("MTKAIF_DMIC", 0,
mt8195_adda_dmic_get, mt8195_adda_dmic_set),
SOC_SINGLE_BOOL_EXT("MTKAIF_ADDA6_ONLY", 0,
mt8195_adda6_only_get,
mt8195_adda6_only_set),
};
static int mtk_dai_da_configure(struct mtk_base_afe *afe,
unsigned int rate, int id)
{
unsigned int val = 0;
unsigned int mask = 0;
/* set sampling rate */
mask |= DL_2_INPUT_MODE_CTL_MASK;
val |= DL_2_INPUT_MODE_CTL(afe_adda_dl_rate_transform(afe, rate));
/* turn off saturation */
mask |= DL_2_CH1_SATURATION_EN_CTL;
mask |= DL_2_CH2_SATURATION_EN_CTL;
/* turn off mute function */
mask |= DL_2_MUTE_CH1_OFF_CTL_PRE;
mask |= DL_2_MUTE_CH2_OFF_CTL_PRE;
val |= DL_2_MUTE_CH1_OFF_CTL_PRE;
val |= DL_2_MUTE_CH2_OFF_CTL_PRE;
/* set voice input data if input sample rate is 8k or 16k */
mask |= DL_2_VOICE_MODE_CTL_PRE;
if (rate == 8000 || rate == 16000)
val |= DL_2_VOICE_MODE_CTL_PRE;
regmap_update_bits(afe->regmap, AFE_ADDA_DL_SRC2_CON0, mask, val);
mask = 0;
val = 0;
/* new 2nd sdm */
mask |= DL_USE_NEW_2ND_SDM;
val |= DL_USE_NEW_2ND_SDM;
regmap_update_bits(afe->regmap, AFE_ADDA_DL_SDM_DCCOMP_CON, mask, val);
return 0;
}
static int mtk_dai_ad_configure(struct mtk_base_afe *afe,
unsigned int rate, int id)
{
unsigned int val = 0;
unsigned int mask = 0;
mask |= UL_VOICE_MODE_CTL_MASK;
val |= UL_VOICE_MODE_CTL(afe_adda_ul_rate_transform(afe, rate));
switch (id) {
case MT8195_AFE_IO_UL_SRC1:
regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0,
mask, val);
break;
case MT8195_AFE_IO_UL_SRC2:
regmap_update_bits(afe->regmap, AFE_ADDA6_UL_SRC_CON0,
mask, val);
break;
default:
break;
}
return 0;
}
static int mtk_dai_adda_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_adda_priv *adda_priv;
unsigned int rate = params_rate(params);
int ret;
if (dai->id != MT8195_AFE_IO_DL_SRC &&
dai->id != MT8195_AFE_IO_UL_SRC1 &&
dai->id != MT8195_AFE_IO_UL_SRC2)
return -EINVAL;
adda_priv = afe_priv->dai_priv[dai->id];
dev_dbg(afe->dev, "%s(), id %d, stream %d, rate %d\n",
__func__, dai->id, substream->stream, rate);
if (rate > ADDA_HIRES_THRES)
adda_priv->hires_required = 1;
else
adda_priv->hires_required = 0;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
ret = mtk_dai_da_configure(afe, rate, dai->id);
else
ret = mtk_dai_ad_configure(afe, rate, dai->id);
return ret;
}
static const struct snd_soc_dai_ops mtk_dai_adda_ops = {
.hw_params = mtk_dai_adda_hw_params,
};
/* dai driver */
#define MTK_ADDA_PLAYBACK_RATES (SNDRV_PCM_RATE_8000_48000 |\
SNDRV_PCM_RATE_96000 |\
SNDRV_PCM_RATE_192000)
#define MTK_ADDA_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 |\
SNDRV_PCM_RATE_48000 |\
SNDRV_PCM_RATE_96000 |\
SNDRV_PCM_RATE_192000)
#define MTK_ADDA_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver mtk_dai_adda_driver[] = {
{
.name = "DL_SRC",
.id = MT8195_AFE_IO_DL_SRC,
.playback = {
.stream_name = "ADDA Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_ADDA_PLAYBACK_RATES,
.formats = MTK_ADDA_FORMATS,
},
.ops = &mtk_dai_adda_ops,
},
{
.name = "UL_SRC1",
.id = MT8195_AFE_IO_UL_SRC1,
.capture = {
.stream_name = "ADDA Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_ADDA_CAPTURE_RATES,
.formats = MTK_ADDA_FORMATS,
},
.ops = &mtk_dai_adda_ops,
},
{
.name = "UL_SRC2",
.id = MT8195_AFE_IO_UL_SRC2,
.capture = {
.stream_name = "ADDA6 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_ADDA_CAPTURE_RATES,
.formats = MTK_ADDA_FORMATS,
},
.ops = &mtk_dai_adda_ops,
},
};
static int init_adda_priv_data(struct mtk_base_afe *afe)
{
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_adda_priv *adda_priv;
static const int adda_dai_list[] = {
MT8195_AFE_IO_DL_SRC,
MT8195_AFE_IO_UL_SRC1,
MT8195_AFE_IO_UL_SRC2
};
int i;
for (i = 0; i < ARRAY_SIZE(adda_dai_list); i++) {
adda_priv = devm_kzalloc(afe->dev,
sizeof(struct mtk_dai_adda_priv),
GFP_KERNEL);
if (!adda_priv)
return -ENOMEM;
afe_priv->dai_priv[adda_dai_list[i]] = adda_priv;
}
return 0;
}
int mt8195_dai_adda_register(struct mtk_base_afe *afe)
{
struct mtk_base_afe_dai *dai;
dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
if (!dai)
return -ENOMEM;
list_add(&dai->list, &afe->sub_dais);
dai->dai_drivers = mtk_dai_adda_driver;
dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_adda_driver);
dai->dapm_widgets = mtk_dai_adda_widgets;
dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_adda_widgets);
dai->dapm_routes = mtk_dai_adda_routes;
dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_adda_routes);
dai->controls = mtk_dai_adda_controls;
dai->num_controls = ARRAY_SIZE(mtk_dai_adda_controls);
return init_adda_priv_data(afe);
}
| linux-master | sound/soc/mediatek/mt8195/mt8195-dai-adda.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Mediatek ALSA SoC AFE platform driver for 8195
*
* Copyright (c) 2021 MediaTek Inc.
* Author: Bicycle Tsai <[email protected]>
* Trevor Wu <[email protected]>
*/
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/module.h>
#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/of_reserved_mem.h>
#include <linux/pm_runtime.h>
#include <linux/reset.h>
#include "mt8195-afe-common.h"
#include "mt8195-afe-clk.h"
#include "mt8195-reg.h"
#include "../common/mtk-afe-platform-driver.h"
#include "../common/mtk-afe-fe-dai.h"
#define MT8195_MEMIF_BUFFER_BYTES_ALIGN (0x40)
#define MT8195_MEMIF_DL7_MAX_PERIOD_SIZE (0x3fff)
struct mtk_dai_memif_priv {
unsigned int asys_timing_sel;
};
static const struct snd_pcm_hardware mt8195_afe_hardware = {
.info = SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_MMAP_VALID,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE |
SNDRV_PCM_FMTBIT_S32_LE,
.period_bytes_min = 64,
.period_bytes_max = 256 * 1024,
.periods_min = 2,
.periods_max = 256,
.buffer_bytes_max = 256 * 2 * 1024,
};
struct mt8195_afe_rate {
unsigned int rate;
unsigned int reg_value;
};
static const struct mt8195_afe_rate mt8195_afe_rates[] = {
{ .rate = 8000, .reg_value = 0, },
{ .rate = 12000, .reg_value = 1, },
{ .rate = 16000, .reg_value = 2, },
{ .rate = 24000, .reg_value = 3, },
{ .rate = 32000, .reg_value = 4, },
{ .rate = 48000, .reg_value = 5, },
{ .rate = 96000, .reg_value = 6, },
{ .rate = 192000, .reg_value = 7, },
{ .rate = 384000, .reg_value = 8, },
{ .rate = 7350, .reg_value = 16, },
{ .rate = 11025, .reg_value = 17, },
{ .rate = 14700, .reg_value = 18, },
{ .rate = 22050, .reg_value = 19, },
{ .rate = 29400, .reg_value = 20, },
{ .rate = 44100, .reg_value = 21, },
{ .rate = 88200, .reg_value = 22, },
{ .rate = 176400, .reg_value = 23, },
{ .rate = 352800, .reg_value = 24, },
};
int mt8195_afe_fs_timing(unsigned int rate)
{
int i;
for (i = 0; i < ARRAY_SIZE(mt8195_afe_rates); i++)
if (mt8195_afe_rates[i].rate == rate)
return mt8195_afe_rates[i].reg_value;
return -EINVAL;
}
static int mt8195_memif_fs(struct snd_pcm_substream *substream,
unsigned int rate)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_component *component =
snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
int id = asoc_rtd_to_cpu(rtd, 0)->id;
struct mtk_base_afe_memif *memif = &afe->memif[id];
int fs = mt8195_afe_fs_timing(rate);
switch (memif->data->id) {
case MT8195_AFE_MEMIF_DL10:
fs = MT8195_ETDM_OUT3_1X_EN;
break;
case MT8195_AFE_MEMIF_UL8:
fs = MT8195_ETDM_IN1_NX_EN;
break;
case MT8195_AFE_MEMIF_UL3:
fs = MT8195_ETDM_IN2_NX_EN;
break;
default:
break;
}
return fs;
}
static int mt8195_irq_fs(struct snd_pcm_substream *substream,
unsigned int rate)
{
int fs = mt8195_memif_fs(substream, rate);
switch (fs) {
case MT8195_ETDM_IN1_NX_EN:
fs = MT8195_ETDM_IN1_1X_EN;
break;
case MT8195_ETDM_IN2_NX_EN:
fs = MT8195_ETDM_IN2_1X_EN;
break;
default:
break;
}
return fs;
}
enum {
MT8195_AFE_CM0,
MT8195_AFE_CM1,
MT8195_AFE_CM2,
MT8195_AFE_CM_NUM,
};
struct mt8195_afe_channel_merge {
int id;
int reg;
unsigned int sel_shift;
unsigned int sel_maskbit;
unsigned int sel_default;
unsigned int ch_num_shift;
unsigned int ch_num_maskbit;
unsigned int en_shift;
unsigned int en_maskbit;
unsigned int update_cnt_shift;
unsigned int update_cnt_maskbit;
unsigned int update_cnt_default;
};
static const struct mt8195_afe_channel_merge
mt8195_afe_cm[MT8195_AFE_CM_NUM] = {
[MT8195_AFE_CM0] = {
.id = MT8195_AFE_CM0,
.reg = AFE_CM0_CON,
.sel_shift = 30,
.sel_maskbit = 0x1,
.sel_default = 1,
.ch_num_shift = 2,
.ch_num_maskbit = 0x3f,
.en_shift = 0,
.en_maskbit = 0x1,
.update_cnt_shift = 16,
.update_cnt_maskbit = 0x1fff,
.update_cnt_default = 0x3,
},
[MT8195_AFE_CM1] = {
.id = MT8195_AFE_CM1,
.reg = AFE_CM1_CON,
.sel_shift = 30,
.sel_maskbit = 0x1,
.sel_default = 1,
.ch_num_shift = 2,
.ch_num_maskbit = 0x1f,
.en_shift = 0,
.en_maskbit = 0x1,
.update_cnt_shift = 16,
.update_cnt_maskbit = 0x1fff,
.update_cnt_default = 0x3,
},
[MT8195_AFE_CM2] = {
.id = MT8195_AFE_CM2,
.reg = AFE_CM2_CON,
.sel_shift = 30,
.sel_maskbit = 0x1,
.sel_default = 1,
.ch_num_shift = 2,
.ch_num_maskbit = 0x1f,
.en_shift = 0,
.en_maskbit = 0x1,
.update_cnt_shift = 16,
.update_cnt_maskbit = 0x1fff,
.update_cnt_default = 0x3,
},
};
static int mt8195_afe_memif_is_ul(int id)
{
if (id >= MT8195_AFE_MEMIF_UL_START && id < MT8195_AFE_MEMIF_END)
return 1;
else
return 0;
}
static const struct mt8195_afe_channel_merge*
mt8195_afe_found_cm(struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
int id = -EINVAL;
if (mt8195_afe_memif_is_ul(dai->id) == 0)
return NULL;
switch (dai->id) {
case MT8195_AFE_MEMIF_UL9:
id = MT8195_AFE_CM0;
break;
case MT8195_AFE_MEMIF_UL2:
id = MT8195_AFE_CM1;
break;
case MT8195_AFE_MEMIF_UL10:
id = MT8195_AFE_CM2;
break;
default:
break;
}
if (id < 0) {
dev_dbg(afe->dev, "%s, memif %d cannot find CM!\n",
__func__, dai->id);
return NULL;
}
return &mt8195_afe_cm[id];
}
static int mt8195_afe_config_cm(struct mtk_base_afe *afe,
const struct mt8195_afe_channel_merge *cm,
unsigned int channels)
{
if (!cm)
return -EINVAL;
regmap_update_bits(afe->regmap,
cm->reg,
cm->sel_maskbit << cm->sel_shift,
cm->sel_default << cm->sel_shift);
regmap_update_bits(afe->regmap,
cm->reg,
cm->ch_num_maskbit << cm->ch_num_shift,
(channels - 1) << cm->ch_num_shift);
regmap_update_bits(afe->regmap,
cm->reg,
cm->update_cnt_maskbit << cm->update_cnt_shift,
cm->update_cnt_default << cm->update_cnt_shift);
return 0;
}
static int mt8195_afe_enable_cm(struct mtk_base_afe *afe,
const struct mt8195_afe_channel_merge *cm,
bool enable)
{
if (!cm)
return -EINVAL;
regmap_update_bits(afe->regmap,
cm->reg,
cm->en_maskbit << cm->en_shift,
enable << cm->en_shift);
return 0;
}
static int
mt8195_afe_paired_memif_clk_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai,
int enable)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8195_afe_private *afe_priv = afe->platform_priv;
int id = asoc_rtd_to_cpu(rtd, 0)->id;
int clk_id;
if (id != MT8195_AFE_MEMIF_DL8 && id != MT8195_AFE_MEMIF_DL10)
return 0;
if (enable) {
clk_id = MT8195_CLK_AUD_MEMIF_DL10;
mt8195_afe_prepare_clk(afe, afe_priv->clk[clk_id]);
clk_id = MT8195_CLK_AUD_MEMIF_DL8;
mt8195_afe_prepare_clk(afe, afe_priv->clk[clk_id]);
} else {
clk_id = MT8195_CLK_AUD_MEMIF_DL8;
mt8195_afe_unprepare_clk(afe, afe_priv->clk[clk_id]);
clk_id = MT8195_CLK_AUD_MEMIF_DL10;
mt8195_afe_unprepare_clk(afe, afe_priv->clk[clk_id]);
}
return 0;
}
static int
mt8195_afe_paired_memif_clk_enable(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai,
int enable)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8195_afe_private *afe_priv = afe->platform_priv;
int id = asoc_rtd_to_cpu(rtd, 0)->id;
int clk_id;
if (id != MT8195_AFE_MEMIF_DL8 && id != MT8195_AFE_MEMIF_DL10)
return 0;
if (enable) {
/* DL8_DL10_MEM */
clk_id = MT8195_CLK_AUD_MEMIF_DL10;
mt8195_afe_enable_clk_atomic(afe, afe_priv->clk[clk_id]);
udelay(1);
/* DL8_DL10_AGENT */
clk_id = MT8195_CLK_AUD_MEMIF_DL8;
mt8195_afe_enable_clk_atomic(afe, afe_priv->clk[clk_id]);
} else {
/* DL8_DL10_AGENT */
clk_id = MT8195_CLK_AUD_MEMIF_DL8;
mt8195_afe_disable_clk_atomic(afe, afe_priv->clk[clk_id]);
/* DL8_DL10_MEM */
clk_id = MT8195_CLK_AUD_MEMIF_DL10;
mt8195_afe_disable_clk_atomic(afe, afe_priv->clk[clk_id]);
}
return 0;
}
static int mt8195_afe_fe_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_pcm_runtime *runtime = substream->runtime;
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
int id = asoc_rtd_to_cpu(rtd, 0)->id;
int ret = 0;
mt8195_afe_paired_memif_clk_prepare(substream, dai, 1);
ret = mtk_afe_fe_startup(substream, dai);
snd_pcm_hw_constraint_step(runtime, 0,
SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
MT8195_MEMIF_BUFFER_BYTES_ALIGN);
if (id != MT8195_AFE_MEMIF_DL7)
goto out;
ret = snd_pcm_hw_constraint_minmax(runtime,
SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
1,
MT8195_MEMIF_DL7_MAX_PERIOD_SIZE);
if (ret < 0)
dev_dbg(afe->dev, "hw_constraint_minmax failed\n");
out:
return ret;
}
static void mt8195_afe_fe_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
mtk_afe_fe_shutdown(substream, dai);
mt8195_afe_paired_memif_clk_prepare(substream, dai, 0);
}
static int mt8195_afe_fe_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
int id = asoc_rtd_to_cpu(rtd, 0)->id;
struct mtk_base_afe_memif *memif = &afe->memif[id];
const struct mtk_base_memif_data *data = memif->data;
const struct mt8195_afe_channel_merge *cm = mt8195_afe_found_cm(dai);
unsigned int ch_num = params_channels(params);
mt8195_afe_config_cm(afe, cm, params_channels(params));
if (data->ch_num_reg >= 0) {
regmap_update_bits(afe->regmap, data->ch_num_reg,
data->ch_num_maskbit << data->ch_num_shift,
ch_num << data->ch_num_shift);
}
return mtk_afe_fe_hw_params(substream, params, dai);
}
static int mt8195_afe_fe_hw_free(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
return mtk_afe_fe_hw_free(substream, dai);
}
static int mt8195_afe_fe_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
return mtk_afe_fe_prepare(substream, dai);
}
static int mt8195_afe_fe_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
int ret = 0;
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
const struct mt8195_afe_channel_merge *cm = mt8195_afe_found_cm(dai);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
mt8195_afe_enable_cm(afe, cm, true);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
mt8195_afe_enable_cm(afe, cm, false);
break;
default:
break;
}
ret = mtk_afe_fe_trigger(substream, cmd, dai);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
mt8195_afe_paired_memif_clk_enable(substream, dai, 1);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
mt8195_afe_paired_memif_clk_enable(substream, dai, 0);
break;
default:
break;
}
return ret;
}
static int mt8195_afe_fe_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
return 0;
}
static const struct snd_soc_dai_ops mt8195_afe_fe_dai_ops = {
.startup = mt8195_afe_fe_startup,
.shutdown = mt8195_afe_fe_shutdown,
.hw_params = mt8195_afe_fe_hw_params,
.hw_free = mt8195_afe_fe_hw_free,
.prepare = mt8195_afe_fe_prepare,
.trigger = mt8195_afe_fe_trigger,
.set_fmt = mt8195_afe_fe_set_fmt,
};
#define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\
SNDRV_PCM_RATE_88200 |\
SNDRV_PCM_RATE_96000 |\
SNDRV_PCM_RATE_176400 |\
SNDRV_PCM_RATE_192000 |\
SNDRV_PCM_RATE_352800 |\
SNDRV_PCM_RATE_384000)
#define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver mt8195_memif_dai_driver[] = {
/* FE DAIs: memory intefaces to CPU */
{
.name = "DL2",
.id = MT8195_AFE_MEMIF_DL2,
.playback = {
.stream_name = "DL2",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8195_afe_fe_dai_ops,
},
{
.name = "DL3",
.id = MT8195_AFE_MEMIF_DL3,
.playback = {
.stream_name = "DL3",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8195_afe_fe_dai_ops,
},
{
.name = "DL6",
.id = MT8195_AFE_MEMIF_DL6,
.playback = {
.stream_name = "DL6",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8195_afe_fe_dai_ops,
},
{
.name = "DL7",
.id = MT8195_AFE_MEMIF_DL7,
.playback = {
.stream_name = "DL7",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8195_afe_fe_dai_ops,
},
{
.name = "DL8",
.id = MT8195_AFE_MEMIF_DL8,
.playback = {
.stream_name = "DL8",
.channels_min = 1,
.channels_max = 24,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8195_afe_fe_dai_ops,
},
{
.name = "DL10",
.id = MT8195_AFE_MEMIF_DL10,
.playback = {
.stream_name = "DL10",
.channels_min = 1,
.channels_max = 8,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8195_afe_fe_dai_ops,
},
{
.name = "DL11",
.id = MT8195_AFE_MEMIF_DL11,
.playback = {
.stream_name = "DL11",
.channels_min = 1,
.channels_max = 48,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8195_afe_fe_dai_ops,
},
{
.name = "UL1",
.id = MT8195_AFE_MEMIF_UL1,
.capture = {
.stream_name = "UL1",
.channels_min = 1,
.channels_max = 8,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8195_afe_fe_dai_ops,
},
{
.name = "UL2",
.id = MT8195_AFE_MEMIF_UL2,
.capture = {
.stream_name = "UL2",
.channels_min = 1,
.channels_max = 8,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8195_afe_fe_dai_ops,
},
{
.name = "UL3",
.id = MT8195_AFE_MEMIF_UL3,
.capture = {
.stream_name = "UL3",
.channels_min = 1,
.channels_max = 16,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8195_afe_fe_dai_ops,
},
{
.name = "UL4",
.id = MT8195_AFE_MEMIF_UL4,
.capture = {
.stream_name = "UL4",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8195_afe_fe_dai_ops,
},
{
.name = "UL5",
.id = MT8195_AFE_MEMIF_UL5,
.capture = {
.stream_name = "UL5",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8195_afe_fe_dai_ops,
},
{
.name = "UL6",
.id = MT8195_AFE_MEMIF_UL6,
.capture = {
.stream_name = "UL6",
.channels_min = 1,
.channels_max = 8,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8195_afe_fe_dai_ops,
},
{
.name = "UL8",
.id = MT8195_AFE_MEMIF_UL8,
.capture = {
.stream_name = "UL8",
.channels_min = 1,
.channels_max = 24,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8195_afe_fe_dai_ops,
},
{
.name = "UL9",
.id = MT8195_AFE_MEMIF_UL9,
.capture = {
.stream_name = "UL9",
.channels_min = 1,
.channels_max = 32,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8195_afe_fe_dai_ops,
},
{
.name = "UL10",
.id = MT8195_AFE_MEMIF_UL10,
.capture = {
.stream_name = "UL10",
.channels_min = 1,
.channels_max = 4,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8195_afe_fe_dai_ops,
},
};
static const struct snd_kcontrol_new o002_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN2, 0, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN2, 12, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN2, 20, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN2, 22, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN2_2, 6, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I072 Switch", AFE_CONN2_2, 8, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN2_5, 8, 1, 0),
};
static const struct snd_kcontrol_new o003_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN3, 1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN3, 13, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN3, 21, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN3, 23, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN3_2, 7, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I073 Switch", AFE_CONN3_2, 9, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN3_5, 9, 1, 0),
};
static const struct snd_kcontrol_new o004_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN4, 0, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I014 Switch", AFE_CONN4, 14, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN4, 24, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I074 Switch", AFE_CONN4_2, 10, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I170 Switch", AFE_CONN4_5, 10, 1, 0),
};
static const struct snd_kcontrol_new o005_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN5, 1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I015 Switch", AFE_CONN5, 15, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN5, 25, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I075 Switch", AFE_CONN5_2, 11, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I171 Switch", AFE_CONN5_5, 11, 1, 0),
};
static const struct snd_kcontrol_new o006_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN6, 0, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I016 Switch", AFE_CONN6, 16, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN6, 26, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I076 Switch", AFE_CONN6_2, 12, 1, 0),
};
static const struct snd_kcontrol_new o007_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN7, 1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I017 Switch", AFE_CONN7, 17, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN7, 27, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I077 Switch", AFE_CONN7_2, 13, 1, 0),
};
static const struct snd_kcontrol_new o008_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I018 Switch", AFE_CONN8, 18, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN8, 28, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I078 Switch", AFE_CONN8_2, 14, 1, 0),
};
static const struct snd_kcontrol_new o009_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I019 Switch", AFE_CONN9, 19, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN9, 29, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I079 Switch", AFE_CONN9_2, 15, 1, 0),
};
static const struct snd_kcontrol_new o010_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN10, 22, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I030 Switch", AFE_CONN10, 30, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN10_1, 14, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I072 Switch", AFE_CONN10_2, 8, 1, 0),
};
static const struct snd_kcontrol_new o011_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN11, 23, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I031 Switch", AFE_CONN11, 31, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN11_1, 15, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I073 Switch", AFE_CONN11_2, 9, 1, 0),
};
static const struct snd_kcontrol_new o012_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN12, 24, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I032 Switch", AFE_CONN12_1, 0, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN12_1, 16, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I074 Switch", AFE_CONN12_2, 10, 1, 0),
};
static const struct snd_kcontrol_new o013_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN13, 25, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I033 Switch", AFE_CONN13_1, 1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN13_1, 17, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I075 Switch", AFE_CONN13_2, 11, 1, 0),
};
static const struct snd_kcontrol_new o014_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN14, 26, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I034 Switch", AFE_CONN14_1, 2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN14_1, 18, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I076 Switch", AFE_CONN14_2, 12, 1, 0),
};
static const struct snd_kcontrol_new o015_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN15, 27, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I035 Switch", AFE_CONN15_1, 3, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN15_1, 19, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I077 Switch", AFE_CONN15_2, 13, 1, 0),
};
static const struct snd_kcontrol_new o016_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN16, 28, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I036 Switch", AFE_CONN16_1, 4, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN16_1, 20, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I078 Switch", AFE_CONN16_2, 14, 1, 0),
};
static const struct snd_kcontrol_new o017_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN17, 29, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I037 Switch", AFE_CONN17_1, 5, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN17_1, 21, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I079 Switch", AFE_CONN17_2, 15, 1, 0),
};
static const struct snd_kcontrol_new o018_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I038 Switch", AFE_CONN18_1, 6, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I080 Switch", AFE_CONN18_2, 16, 1, 0),
};
static const struct snd_kcontrol_new o019_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I039 Switch", AFE_CONN19_1, 7, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I081 Switch", AFE_CONN19_2, 17, 1, 0),
};
static const struct snd_kcontrol_new o020_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I040 Switch", AFE_CONN20_1, 8, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I082 Switch", AFE_CONN20_2, 18, 1, 0),
};
static const struct snd_kcontrol_new o021_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I041 Switch", AFE_CONN21_1, 9, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I083 Switch", AFE_CONN21_2, 19, 1, 0),
};
static const struct snd_kcontrol_new o022_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I042 Switch", AFE_CONN22_1, 10, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I084 Switch", AFE_CONN22_2, 20, 1, 0),
};
static const struct snd_kcontrol_new o023_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I043 Switch", AFE_CONN23_1, 11, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I085 Switch", AFE_CONN23_2, 21, 1, 0),
};
static const struct snd_kcontrol_new o024_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I044 Switch", AFE_CONN24_1, 12, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I086 Switch", AFE_CONN24_2, 22, 1, 0),
};
static const struct snd_kcontrol_new o025_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I045 Switch", AFE_CONN25_1, 13, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I087 Switch", AFE_CONN25_2, 23, 1, 0),
};
static const struct snd_kcontrol_new o026_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN26_1, 14, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I088 Switch", AFE_CONN26_2, 24, 1, 0),
};
static const struct snd_kcontrol_new o027_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN27_1, 15, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I089 Switch", AFE_CONN27_2, 25, 1, 0),
};
static const struct snd_kcontrol_new o028_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN28_1, 16, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I090 Switch", AFE_CONN28_2, 26, 1, 0),
};
static const struct snd_kcontrol_new o029_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN29_1, 17, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I091 Switch", AFE_CONN29_2, 27, 1, 0),
};
static const struct snd_kcontrol_new o030_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN30_1, 18, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I092 Switch", AFE_CONN30_2, 28, 1, 0),
};
static const struct snd_kcontrol_new o031_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN31_1, 19, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I093 Switch", AFE_CONN31_2, 29, 1, 0),
};
static const struct snd_kcontrol_new o032_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN32_1, 20, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I094 Switch", AFE_CONN32_2, 30, 1, 0),
};
static const struct snd_kcontrol_new o033_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN33_1, 21, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I095 Switch", AFE_CONN33_2, 31, 1, 0),
};
static const struct snd_kcontrol_new o034_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN34, 0, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I002 Switch", AFE_CONN34, 2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN34, 12, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN34, 20, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN34_2, 6, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I072 Switch", AFE_CONN34_2, 8, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN34_5, 8, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I170 Switch", AFE_CONN34_5, 10, 1, 0),
};
static const struct snd_kcontrol_new o035_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN35, 1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I003 Switch", AFE_CONN35, 3, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN35, 13, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN35, 21, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN35_2, 7, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I073 Switch", AFE_CONN35_2, 9, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I137 Switch", AFE_CONN35_4, 9, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I139 Switch", AFE_CONN35_4, 11, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN35_5, 8, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN35_5, 9, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I170 Switch", AFE_CONN35_5, 10, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I171 Switch", AFE_CONN35_5, 11, 1, 0),
};
static const struct snd_kcontrol_new o036_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN36, 0, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN36, 12, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN36, 20, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN36_2, 6, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN36_5, 8, 1, 0),
};
static const struct snd_kcontrol_new o037_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN37, 1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN37, 13, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN37, 21, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN37_2, 7, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN37_5, 9, 1, 0),
};
static const struct snd_kcontrol_new o038_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN38, 22, 1, 0),
};
static const struct snd_kcontrol_new o039_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN39, 23, 1, 0),
};
static const struct snd_kcontrol_new o040_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I002 Switch", AFE_CONN40, 2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN40, 12, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN40, 22, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN40_5, 8, 1, 0),
};
static const struct snd_kcontrol_new o041_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I003 Switch", AFE_CONN41, 3, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN41, 13, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN41, 23, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN41_5, 9, 1, 0),
};
static const struct snd_kcontrol_new o042_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I014 Switch", AFE_CONN42, 14, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN42, 24, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I170 Switch", AFE_CONN42_5, 10, 1, 0),
};
static const struct snd_kcontrol_new o043_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I015 Switch", AFE_CONN43, 15, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN43, 25, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I171 Switch", AFE_CONN43_5, 11, 1, 0),
};
static const struct snd_kcontrol_new o044_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I016 Switch", AFE_CONN44, 16, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN44, 26, 1, 0),
};
static const struct snd_kcontrol_new o045_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I017 Switch", AFE_CONN45, 17, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN45, 27, 1, 0),
};
static const struct snd_kcontrol_new o046_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I018 Switch", AFE_CONN46, 18, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN46, 28, 1, 0),
};
static const struct snd_kcontrol_new o047_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I019 Switch", AFE_CONN47, 19, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN47, 29, 1, 0),
};
static const struct snd_kcontrol_new o182_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN182, 24, 1, 0),
};
static const struct snd_kcontrol_new o183_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN183, 25, 1, 0),
};
static const char * const dl8_dl11_data_sel_mux_text[] = {
"dl8", "dl11",
};
static SOC_ENUM_SINGLE_DECL(dl8_dl11_data_sel_mux_enum,
AFE_DAC_CON2, 0, dl8_dl11_data_sel_mux_text);
static const struct snd_kcontrol_new dl8_dl11_data_sel_mux =
SOC_DAPM_ENUM("DL8_DL11 Sink", dl8_dl11_data_sel_mux_enum);
static const struct snd_soc_dapm_widget mt8195_memif_widgets[] = {
/* DL6 */
SND_SOC_DAPM_MIXER("I000", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I001", SND_SOC_NOPM, 0, 0, NULL, 0),
/* DL3 */
SND_SOC_DAPM_MIXER("I020", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I021", SND_SOC_NOPM, 0, 0, NULL, 0),
/* DL11 */
SND_SOC_DAPM_MIXER("I022", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I023", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I024", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I025", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I026", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I027", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I028", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I029", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I030", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I031", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I032", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I033", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I034", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I035", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I036", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I037", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I038", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I039", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I040", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I041", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I042", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I043", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I044", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I045", SND_SOC_NOPM, 0, 0, NULL, 0),
/* DL11/DL8 */
SND_SOC_DAPM_MIXER("I046", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I047", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I048", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I049", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I050", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I051", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I052", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I053", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I054", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I055", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I056", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I057", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I058", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I059", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I060", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I061", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I062", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I063", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I064", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I065", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I066", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I067", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I068", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I069", SND_SOC_NOPM, 0, 0, NULL, 0),
/* DL2 */
SND_SOC_DAPM_MIXER("I070", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I071", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MUX("DL8_DL11 Mux",
SND_SOC_NOPM, 0, 0, &dl8_dl11_data_sel_mux),
/* UL9 */
SND_SOC_DAPM_MIXER("O002", SND_SOC_NOPM, 0, 0,
o002_mix, ARRAY_SIZE(o002_mix)),
SND_SOC_DAPM_MIXER("O003", SND_SOC_NOPM, 0, 0,
o003_mix, ARRAY_SIZE(o003_mix)),
SND_SOC_DAPM_MIXER("O004", SND_SOC_NOPM, 0, 0,
o004_mix, ARRAY_SIZE(o004_mix)),
SND_SOC_DAPM_MIXER("O005", SND_SOC_NOPM, 0, 0,
o005_mix, ARRAY_SIZE(o005_mix)),
SND_SOC_DAPM_MIXER("O006", SND_SOC_NOPM, 0, 0,
o006_mix, ARRAY_SIZE(o006_mix)),
SND_SOC_DAPM_MIXER("O007", SND_SOC_NOPM, 0, 0,
o007_mix, ARRAY_SIZE(o007_mix)),
SND_SOC_DAPM_MIXER("O008", SND_SOC_NOPM, 0, 0,
o008_mix, ARRAY_SIZE(o008_mix)),
SND_SOC_DAPM_MIXER("O009", SND_SOC_NOPM, 0, 0,
o009_mix, ARRAY_SIZE(o009_mix)),
SND_SOC_DAPM_MIXER("O010", SND_SOC_NOPM, 0, 0,
o010_mix, ARRAY_SIZE(o010_mix)),
SND_SOC_DAPM_MIXER("O011", SND_SOC_NOPM, 0, 0,
o011_mix, ARRAY_SIZE(o011_mix)),
SND_SOC_DAPM_MIXER("O012", SND_SOC_NOPM, 0, 0,
o012_mix, ARRAY_SIZE(o012_mix)),
SND_SOC_DAPM_MIXER("O013", SND_SOC_NOPM, 0, 0,
o013_mix, ARRAY_SIZE(o013_mix)),
SND_SOC_DAPM_MIXER("O014", SND_SOC_NOPM, 0, 0,
o014_mix, ARRAY_SIZE(o014_mix)),
SND_SOC_DAPM_MIXER("O015", SND_SOC_NOPM, 0, 0,
o015_mix, ARRAY_SIZE(o015_mix)),
SND_SOC_DAPM_MIXER("O016", SND_SOC_NOPM, 0, 0,
o016_mix, ARRAY_SIZE(o016_mix)),
SND_SOC_DAPM_MIXER("O017", SND_SOC_NOPM, 0, 0,
o017_mix, ARRAY_SIZE(o017_mix)),
SND_SOC_DAPM_MIXER("O018", SND_SOC_NOPM, 0, 0,
o018_mix, ARRAY_SIZE(o018_mix)),
SND_SOC_DAPM_MIXER("O019", SND_SOC_NOPM, 0, 0,
o019_mix, ARRAY_SIZE(o019_mix)),
SND_SOC_DAPM_MIXER("O020", SND_SOC_NOPM, 0, 0,
o020_mix, ARRAY_SIZE(o020_mix)),
SND_SOC_DAPM_MIXER("O021", SND_SOC_NOPM, 0, 0,
o021_mix, ARRAY_SIZE(o021_mix)),
SND_SOC_DAPM_MIXER("O022", SND_SOC_NOPM, 0, 0,
o022_mix, ARRAY_SIZE(o022_mix)),
SND_SOC_DAPM_MIXER("O023", SND_SOC_NOPM, 0, 0,
o023_mix, ARRAY_SIZE(o023_mix)),
SND_SOC_DAPM_MIXER("O024", SND_SOC_NOPM, 0, 0,
o024_mix, ARRAY_SIZE(o024_mix)),
SND_SOC_DAPM_MIXER("O025", SND_SOC_NOPM, 0, 0,
o025_mix, ARRAY_SIZE(o025_mix)),
SND_SOC_DAPM_MIXER("O026", SND_SOC_NOPM, 0, 0,
o026_mix, ARRAY_SIZE(o026_mix)),
SND_SOC_DAPM_MIXER("O027", SND_SOC_NOPM, 0, 0,
o027_mix, ARRAY_SIZE(o027_mix)),
SND_SOC_DAPM_MIXER("O028", SND_SOC_NOPM, 0, 0,
o028_mix, ARRAY_SIZE(o028_mix)),
SND_SOC_DAPM_MIXER("O029", SND_SOC_NOPM, 0, 0,
o029_mix, ARRAY_SIZE(o029_mix)),
SND_SOC_DAPM_MIXER("O030", SND_SOC_NOPM, 0, 0,
o030_mix, ARRAY_SIZE(o030_mix)),
SND_SOC_DAPM_MIXER("O031", SND_SOC_NOPM, 0, 0,
o031_mix, ARRAY_SIZE(o031_mix)),
SND_SOC_DAPM_MIXER("O032", SND_SOC_NOPM, 0, 0,
o032_mix, ARRAY_SIZE(o032_mix)),
SND_SOC_DAPM_MIXER("O033", SND_SOC_NOPM, 0, 0,
o033_mix, ARRAY_SIZE(o033_mix)),
/* UL4 */
SND_SOC_DAPM_MIXER("O034", SND_SOC_NOPM, 0, 0,
o034_mix, ARRAY_SIZE(o034_mix)),
SND_SOC_DAPM_MIXER("O035", SND_SOC_NOPM, 0, 0,
o035_mix, ARRAY_SIZE(o035_mix)),
/* UL5 */
SND_SOC_DAPM_MIXER("O036", SND_SOC_NOPM, 0, 0,
o036_mix, ARRAY_SIZE(o036_mix)),
SND_SOC_DAPM_MIXER("O037", SND_SOC_NOPM, 0, 0,
o037_mix, ARRAY_SIZE(o037_mix)),
/* UL10 */
SND_SOC_DAPM_MIXER("O038", SND_SOC_NOPM, 0, 0,
o038_mix, ARRAY_SIZE(o038_mix)),
SND_SOC_DAPM_MIXER("O039", SND_SOC_NOPM, 0, 0,
o039_mix, ARRAY_SIZE(o039_mix)),
SND_SOC_DAPM_MIXER("O182", SND_SOC_NOPM, 0, 0,
o182_mix, ARRAY_SIZE(o182_mix)),
SND_SOC_DAPM_MIXER("O183", SND_SOC_NOPM, 0, 0,
o183_mix, ARRAY_SIZE(o183_mix)),
/* UL2 */
SND_SOC_DAPM_MIXER("O040", SND_SOC_NOPM, 0, 0,
o040_mix, ARRAY_SIZE(o040_mix)),
SND_SOC_DAPM_MIXER("O041", SND_SOC_NOPM, 0, 0,
o041_mix, ARRAY_SIZE(o041_mix)),
SND_SOC_DAPM_MIXER("O042", SND_SOC_NOPM, 0, 0,
o042_mix, ARRAY_SIZE(o042_mix)),
SND_SOC_DAPM_MIXER("O043", SND_SOC_NOPM, 0, 0,
o043_mix, ARRAY_SIZE(o043_mix)),
SND_SOC_DAPM_MIXER("O044", SND_SOC_NOPM, 0, 0,
o044_mix, ARRAY_SIZE(o044_mix)),
SND_SOC_DAPM_MIXER("O045", SND_SOC_NOPM, 0, 0,
o045_mix, ARRAY_SIZE(o045_mix)),
SND_SOC_DAPM_MIXER("O046", SND_SOC_NOPM, 0, 0,
o046_mix, ARRAY_SIZE(o046_mix)),
SND_SOC_DAPM_MIXER("O047", SND_SOC_NOPM, 0, 0,
o047_mix, ARRAY_SIZE(o047_mix)),
};
static const struct snd_soc_dapm_route mt8195_memif_routes[] = {
{"I000", NULL, "DL6"},
{"I001", NULL, "DL6"},
{"I020", NULL, "DL3"},
{"I021", NULL, "DL3"},
{"I022", NULL, "DL11"},
{"I023", NULL, "DL11"},
{"I024", NULL, "DL11"},
{"I025", NULL, "DL11"},
{"I026", NULL, "DL11"},
{"I027", NULL, "DL11"},
{"I028", NULL, "DL11"},
{"I029", NULL, "DL11"},
{"I030", NULL, "DL11"},
{"I031", NULL, "DL11"},
{"I032", NULL, "DL11"},
{"I033", NULL, "DL11"},
{"I034", NULL, "DL11"},
{"I035", NULL, "DL11"},
{"I036", NULL, "DL11"},
{"I037", NULL, "DL11"},
{"I038", NULL, "DL11"},
{"I039", NULL, "DL11"},
{"I040", NULL, "DL11"},
{"I041", NULL, "DL11"},
{"I042", NULL, "DL11"},
{"I043", NULL, "DL11"},
{"I044", NULL, "DL11"},
{"I045", NULL, "DL11"},
{"DL8_DL11 Mux", "dl8", "DL8"},
{"DL8_DL11 Mux", "dl11", "DL11"},
{"I046", NULL, "DL8_DL11 Mux"},
{"I047", NULL, "DL8_DL11 Mux"},
{"I048", NULL, "DL8_DL11 Mux"},
{"I049", NULL, "DL8_DL11 Mux"},
{"I050", NULL, "DL8_DL11 Mux"},
{"I051", NULL, "DL8_DL11 Mux"},
{"I052", NULL, "DL8_DL11 Mux"},
{"I053", NULL, "DL8_DL11 Mux"},
{"I054", NULL, "DL8_DL11 Mux"},
{"I055", NULL, "DL8_DL11 Mux"},
{"I056", NULL, "DL8_DL11 Mux"},
{"I057", NULL, "DL8_DL11 Mux"},
{"I058", NULL, "DL8_DL11 Mux"},
{"I059", NULL, "DL8_DL11 Mux"},
{"I060", NULL, "DL8_DL11 Mux"},
{"I061", NULL, "DL8_DL11 Mux"},
{"I062", NULL, "DL8_DL11 Mux"},
{"I063", NULL, "DL8_DL11 Mux"},
{"I064", NULL, "DL8_DL11 Mux"},
{"I065", NULL, "DL8_DL11 Mux"},
{"I066", NULL, "DL8_DL11 Mux"},
{"I067", NULL, "DL8_DL11 Mux"},
{"I068", NULL, "DL8_DL11 Mux"},
{"I069", NULL, "DL8_DL11 Mux"},
{"I070", NULL, "DL2"},
{"I071", NULL, "DL2"},
{"UL9", NULL, "O002"},
{"UL9", NULL, "O003"},
{"UL9", NULL, "O004"},
{"UL9", NULL, "O005"},
{"UL9", NULL, "O006"},
{"UL9", NULL, "O007"},
{"UL9", NULL, "O008"},
{"UL9", NULL, "O009"},
{"UL9", NULL, "O010"},
{"UL9", NULL, "O011"},
{"UL9", NULL, "O012"},
{"UL9", NULL, "O013"},
{"UL9", NULL, "O014"},
{"UL9", NULL, "O015"},
{"UL9", NULL, "O016"},
{"UL9", NULL, "O017"},
{"UL9", NULL, "O018"},
{"UL9", NULL, "O019"},
{"UL9", NULL, "O020"},
{"UL9", NULL, "O021"},
{"UL9", NULL, "O022"},
{"UL9", NULL, "O023"},
{"UL9", NULL, "O024"},
{"UL9", NULL, "O025"},
{"UL9", NULL, "O026"},
{"UL9", NULL, "O027"},
{"UL9", NULL, "O028"},
{"UL9", NULL, "O029"},
{"UL9", NULL, "O030"},
{"UL9", NULL, "O031"},
{"UL9", NULL, "O032"},
{"UL9", NULL, "O033"},
{"UL4", NULL, "O034"},
{"UL4", NULL, "O035"},
{"UL5", NULL, "O036"},
{"UL5", NULL, "O037"},
{"UL10", NULL, "O038"},
{"UL10", NULL, "O039"},
{"UL10", NULL, "O182"},
{"UL10", NULL, "O183"},
{"UL2", NULL, "O040"},
{"UL2", NULL, "O041"},
{"UL2", NULL, "O042"},
{"UL2", NULL, "O043"},
{"UL2", NULL, "O044"},
{"UL2", NULL, "O045"},
{"UL2", NULL, "O046"},
{"UL2", NULL, "O047"},
{"O004", "I000 Switch", "I000"},
{"O005", "I001 Switch", "I001"},
{"O006", "I000 Switch", "I000"},
{"O007", "I001 Switch", "I001"},
{"O010", "I022 Switch", "I022"},
{"O011", "I023 Switch", "I023"},
{"O012", "I024 Switch", "I024"},
{"O013", "I025 Switch", "I025"},
{"O014", "I026 Switch", "I026"},
{"O015", "I027 Switch", "I027"},
{"O016", "I028 Switch", "I028"},
{"O017", "I029 Switch", "I029"},
{"O010", "I046 Switch", "I046"},
{"O011", "I047 Switch", "I047"},
{"O012", "I048 Switch", "I048"},
{"O013", "I049 Switch", "I049"},
{"O014", "I050 Switch", "I050"},
{"O015", "I051 Switch", "I051"},
{"O016", "I052 Switch", "I052"},
{"O017", "I053 Switch", "I053"},
{"O002", "I022 Switch", "I022"},
{"O003", "I023 Switch", "I023"},
{"O004", "I024 Switch", "I024"},
{"O005", "I025 Switch", "I025"},
{"O006", "I026 Switch", "I026"},
{"O007", "I027 Switch", "I027"},
{"O008", "I028 Switch", "I028"},
{"O009", "I029 Switch", "I029"},
{"O010", "I030 Switch", "I030"},
{"O011", "I031 Switch", "I031"},
{"O012", "I032 Switch", "I032"},
{"O013", "I033 Switch", "I033"},
{"O014", "I034 Switch", "I034"},
{"O015", "I035 Switch", "I035"},
{"O016", "I036 Switch", "I036"},
{"O017", "I037 Switch", "I037"},
{"O018", "I038 Switch", "I038"},
{"O019", "I039 Switch", "I039"},
{"O020", "I040 Switch", "I040"},
{"O021", "I041 Switch", "I041"},
{"O022", "I042 Switch", "I042"},
{"O023", "I043 Switch", "I043"},
{"O024", "I044 Switch", "I044"},
{"O025", "I045 Switch", "I045"},
{"O026", "I046 Switch", "I046"},
{"O027", "I047 Switch", "I047"},
{"O028", "I048 Switch", "I048"},
{"O029", "I049 Switch", "I049"},
{"O030", "I050 Switch", "I050"},
{"O031", "I051 Switch", "I051"},
{"O032", "I052 Switch", "I052"},
{"O033", "I053 Switch", "I053"},
{"O002", "I000 Switch", "I000"},
{"O003", "I001 Switch", "I001"},
{"O002", "I020 Switch", "I020"},
{"O003", "I021 Switch", "I021"},
{"O002", "I070 Switch", "I070"},
{"O003", "I071 Switch", "I071"},
{"O034", "I000 Switch", "I000"},
{"O035", "I001 Switch", "I001"},
{"O034", "I002 Switch", "I002"},
{"O035", "I003 Switch", "I003"},
{"O034", "I012 Switch", "I012"},
{"O035", "I013 Switch", "I013"},
{"O034", "I020 Switch", "I020"},
{"O035", "I021 Switch", "I021"},
{"O034", "I070 Switch", "I070"},
{"O035", "I071 Switch", "I071"},
{"O034", "I072 Switch", "I072"},
{"O035", "I073 Switch", "I073"},
{"O036", "I000 Switch", "I000"},
{"O037", "I001 Switch", "I001"},
{"O036", "I012 Switch", "I012"},
{"O037", "I013 Switch", "I013"},
{"O036", "I020 Switch", "I020"},
{"O037", "I021 Switch", "I021"},
{"O036", "I070 Switch", "I070"},
{"O037", "I071 Switch", "I071"},
{"O036", "I168 Switch", "I168"},
{"O037", "I169 Switch", "I169"},
{"O038", "I022 Switch", "I022"},
{"O039", "I023 Switch", "I023"},
{"O182", "I024 Switch", "I024"},
{"O183", "I025 Switch", "I025"},
{"O040", "I022 Switch", "I022"},
{"O041", "I023 Switch", "I023"},
{"O042", "I024 Switch", "I024"},
{"O043", "I025 Switch", "I025"},
{"O044", "I026 Switch", "I026"},
{"O045", "I027 Switch", "I027"},
{"O046", "I028 Switch", "I028"},
{"O047", "I029 Switch", "I029"},
{"O040", "I002 Switch", "I002"},
{"O041", "I003 Switch", "I003"},
{"O002", "I012 Switch", "I012"},
{"O003", "I013 Switch", "I013"},
{"O004", "I014 Switch", "I014"},
{"O005", "I015 Switch", "I015"},
{"O006", "I016 Switch", "I016"},
{"O007", "I017 Switch", "I017"},
{"O008", "I018 Switch", "I018"},
{"O009", "I019 Switch", "I019"},
{"O040", "I012 Switch", "I012"},
{"O041", "I013 Switch", "I013"},
{"O042", "I014 Switch", "I014"},
{"O043", "I015 Switch", "I015"},
{"O044", "I016 Switch", "I016"},
{"O045", "I017 Switch", "I017"},
{"O046", "I018 Switch", "I018"},
{"O047", "I019 Switch", "I019"},
{"O002", "I072 Switch", "I072"},
{"O003", "I073 Switch", "I073"},
{"O004", "I074 Switch", "I074"},
{"O005", "I075 Switch", "I075"},
{"O006", "I076 Switch", "I076"},
{"O007", "I077 Switch", "I077"},
{"O008", "I078 Switch", "I078"},
{"O009", "I079 Switch", "I079"},
{"O010", "I072 Switch", "I072"},
{"O011", "I073 Switch", "I073"},
{"O012", "I074 Switch", "I074"},
{"O013", "I075 Switch", "I075"},
{"O014", "I076 Switch", "I076"},
{"O015", "I077 Switch", "I077"},
{"O016", "I078 Switch", "I078"},
{"O017", "I079 Switch", "I079"},
{"O018", "I080 Switch", "I080"},
{"O019", "I081 Switch", "I081"},
{"O020", "I082 Switch", "I082"},
{"O021", "I083 Switch", "I083"},
{"O022", "I084 Switch", "I084"},
{"O023", "I085 Switch", "I085"},
{"O024", "I086 Switch", "I086"},
{"O025", "I087 Switch", "I087"},
{"O026", "I088 Switch", "I088"},
{"O027", "I089 Switch", "I089"},
{"O028", "I090 Switch", "I090"},
{"O029", "I091 Switch", "I091"},
{"O030", "I092 Switch", "I092"},
{"O031", "I093 Switch", "I093"},
{"O032", "I094 Switch", "I094"},
{"O033", "I095 Switch", "I095"},
{"O002", "I168 Switch", "I168"},
{"O003", "I169 Switch", "I169"},
{"O004", "I170 Switch", "I170"},
{"O005", "I171 Switch", "I171"},
{"O034", "I168 Switch", "I168"},
{"O035", "I168 Switch", "I168"},
{"O035", "I169 Switch", "I169"},
{"O034", "I170 Switch", "I170"},
{"O035", "I170 Switch", "I170"},
{"O035", "I171 Switch", "I171"},
{"O040", "I168 Switch", "I168"},
{"O041", "I169 Switch", "I169"},
{"O042", "I170 Switch", "I170"},
{"O043", "I171 Switch", "I171"},
};
static const char * const mt8195_afe_1x_en_sel_text[] = {
"a1sys_a2sys", "a3sys", "a4sys",
};
static const unsigned int mt8195_afe_1x_en_sel_values[] = {
0, 1, 2,
};
static int mt8195_memif_1x_en_sel_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_memif_priv *memif_priv;
unsigned int dai_id = kcontrol->id.device;
long val = ucontrol->value.integer.value[0];
int ret = 0;
memif_priv = afe_priv->dai_priv[dai_id];
if (val == memif_priv->asys_timing_sel)
return 0;
ret = snd_soc_put_enum_double(kcontrol, ucontrol);
memif_priv->asys_timing_sel = val;
return ret;
}
static int mt8195_asys_irq_1x_en_sel_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
struct mt8195_afe_private *afe_priv = afe->platform_priv;
unsigned int id = kcontrol->id.device;
long val = ucontrol->value.integer.value[0];
int ret = 0;
if (val == afe_priv->irq_priv[id].asys_timing_sel)
return 0;
ret = snd_soc_put_enum_double(kcontrol, ucontrol);
afe_priv->irq_priv[id].asys_timing_sel = val;
return ret;
}
static SOC_VALUE_ENUM_SINGLE_DECL(dl2_1x_en_sel_enum,
A3_A4_TIMING_SEL1, 18, 0x3,
mt8195_afe_1x_en_sel_text,
mt8195_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(dl3_1x_en_sel_enum,
A3_A4_TIMING_SEL1, 20, 0x3,
mt8195_afe_1x_en_sel_text,
mt8195_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(dl6_1x_en_sel_enum,
A3_A4_TIMING_SEL1, 22, 0x3,
mt8195_afe_1x_en_sel_text,
mt8195_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(dl7_1x_en_sel_enum,
A3_A4_TIMING_SEL1, 24, 0x3,
mt8195_afe_1x_en_sel_text,
mt8195_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(dl8_1x_en_sel_enum,
A3_A4_TIMING_SEL1, 26, 0x3,
mt8195_afe_1x_en_sel_text,
mt8195_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(dl10_1x_en_sel_enum,
A3_A4_TIMING_SEL1, 28, 0x3,
mt8195_afe_1x_en_sel_text,
mt8195_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(dl11_1x_en_sel_enum,
A3_A4_TIMING_SEL1, 30, 0x3,
mt8195_afe_1x_en_sel_text,
mt8195_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(ul1_1x_en_sel_enum,
A3_A4_TIMING_SEL1, 0, 0x3,
mt8195_afe_1x_en_sel_text,
mt8195_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(ul2_1x_en_sel_enum,
A3_A4_TIMING_SEL1, 2, 0x3,
mt8195_afe_1x_en_sel_text,
mt8195_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(ul3_1x_en_sel_enum,
A3_A4_TIMING_SEL1, 4, 0x3,
mt8195_afe_1x_en_sel_text,
mt8195_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(ul4_1x_en_sel_enum,
A3_A4_TIMING_SEL1, 6, 0x3,
mt8195_afe_1x_en_sel_text,
mt8195_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(ul5_1x_en_sel_enum,
A3_A4_TIMING_SEL1, 8, 0x3,
mt8195_afe_1x_en_sel_text,
mt8195_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(ul6_1x_en_sel_enum,
A3_A4_TIMING_SEL1, 10, 0x3,
mt8195_afe_1x_en_sel_text,
mt8195_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(ul8_1x_en_sel_enum,
A3_A4_TIMING_SEL1, 12, 0x3,
mt8195_afe_1x_en_sel_text,
mt8195_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(ul9_1x_en_sel_enum,
A3_A4_TIMING_SEL1, 14, 0x3,
mt8195_afe_1x_en_sel_text,
mt8195_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(ul10_1x_en_sel_enum,
A3_A4_TIMING_SEL1, 16, 0x3,
mt8195_afe_1x_en_sel_text,
mt8195_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq1_1x_en_sel_enum,
A3_A4_TIMING_SEL6, 0, 0x3,
mt8195_afe_1x_en_sel_text,
mt8195_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq2_1x_en_sel_enum,
A3_A4_TIMING_SEL6, 2, 0x3,
mt8195_afe_1x_en_sel_text,
mt8195_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq3_1x_en_sel_enum,
A3_A4_TIMING_SEL6, 4, 0x3,
mt8195_afe_1x_en_sel_text,
mt8195_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq4_1x_en_sel_enum,
A3_A4_TIMING_SEL6, 6, 0x3,
mt8195_afe_1x_en_sel_text,
mt8195_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq5_1x_en_sel_enum,
A3_A4_TIMING_SEL6, 8, 0x3,
mt8195_afe_1x_en_sel_text,
mt8195_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq6_1x_en_sel_enum,
A3_A4_TIMING_SEL6, 10, 0x3,
mt8195_afe_1x_en_sel_text,
mt8195_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq7_1x_en_sel_enum,
A3_A4_TIMING_SEL6, 12, 0x3,
mt8195_afe_1x_en_sel_text,
mt8195_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq8_1x_en_sel_enum,
A3_A4_TIMING_SEL6, 14, 0x3,
mt8195_afe_1x_en_sel_text,
mt8195_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq9_1x_en_sel_enum,
A3_A4_TIMING_SEL6, 16, 0x3,
mt8195_afe_1x_en_sel_text,
mt8195_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq10_1x_en_sel_enum,
A3_A4_TIMING_SEL6, 18, 0x3,
mt8195_afe_1x_en_sel_text,
mt8195_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq11_1x_en_sel_enum,
A3_A4_TIMING_SEL6, 20, 0x3,
mt8195_afe_1x_en_sel_text,
mt8195_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq12_1x_en_sel_enum,
A3_A4_TIMING_SEL6, 22, 0x3,
mt8195_afe_1x_en_sel_text,
mt8195_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq13_1x_en_sel_enum,
A3_A4_TIMING_SEL6, 24, 0x3,
mt8195_afe_1x_en_sel_text,
mt8195_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq14_1x_en_sel_enum,
A3_A4_TIMING_SEL6, 26, 0x3,
mt8195_afe_1x_en_sel_text,
mt8195_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq15_1x_en_sel_enum,
A3_A4_TIMING_SEL6, 28, 0x3,
mt8195_afe_1x_en_sel_text,
mt8195_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq16_1x_en_sel_enum,
A3_A4_TIMING_SEL6, 30, 0x3,
mt8195_afe_1x_en_sel_text,
mt8195_afe_1x_en_sel_values);
static const struct snd_kcontrol_new mt8195_memif_controls[] = {
MT8195_SOC_ENUM_EXT("dl2_1x_en_sel",
dl2_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8195_memif_1x_en_sel_put,
MT8195_AFE_MEMIF_DL2),
MT8195_SOC_ENUM_EXT("dl3_1x_en_sel",
dl3_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8195_memif_1x_en_sel_put,
MT8195_AFE_MEMIF_DL3),
MT8195_SOC_ENUM_EXT("dl6_1x_en_sel",
dl6_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8195_memif_1x_en_sel_put,
MT8195_AFE_MEMIF_DL6),
MT8195_SOC_ENUM_EXT("dl7_1x_en_sel",
dl7_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8195_memif_1x_en_sel_put,
MT8195_AFE_MEMIF_DL7),
MT8195_SOC_ENUM_EXT("dl8_1x_en_sel",
dl8_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8195_memif_1x_en_sel_put,
MT8195_AFE_MEMIF_DL8),
MT8195_SOC_ENUM_EXT("dl10_1x_en_sel",
dl10_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8195_memif_1x_en_sel_put,
MT8195_AFE_MEMIF_DL10),
MT8195_SOC_ENUM_EXT("dl11_1x_en_sel",
dl11_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8195_memif_1x_en_sel_put,
MT8195_AFE_MEMIF_DL11),
MT8195_SOC_ENUM_EXT("ul1_1x_en_sel",
ul1_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8195_memif_1x_en_sel_put,
MT8195_AFE_MEMIF_UL1),
MT8195_SOC_ENUM_EXT("ul2_1x_en_sel",
ul2_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8195_memif_1x_en_sel_put,
MT8195_AFE_MEMIF_UL2),
MT8195_SOC_ENUM_EXT("ul3_1x_en_sel",
ul3_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8195_memif_1x_en_sel_put,
MT8195_AFE_MEMIF_UL3),
MT8195_SOC_ENUM_EXT("ul4_1x_en_sel",
ul4_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8195_memif_1x_en_sel_put,
MT8195_AFE_MEMIF_UL4),
MT8195_SOC_ENUM_EXT("ul5_1x_en_sel",
ul5_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8195_memif_1x_en_sel_put,
MT8195_AFE_MEMIF_UL5),
MT8195_SOC_ENUM_EXT("ul6_1x_en_sel",
ul6_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8195_memif_1x_en_sel_put,
MT8195_AFE_MEMIF_UL6),
MT8195_SOC_ENUM_EXT("ul8_1x_en_sel",
ul8_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8195_memif_1x_en_sel_put,
MT8195_AFE_MEMIF_UL8),
MT8195_SOC_ENUM_EXT("ul9_1x_en_sel",
ul9_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8195_memif_1x_en_sel_put,
MT8195_AFE_MEMIF_UL9),
MT8195_SOC_ENUM_EXT("ul10_1x_en_sel",
ul10_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8195_memif_1x_en_sel_put,
MT8195_AFE_MEMIF_UL10),
MT8195_SOC_ENUM_EXT("asys_irq1_1x_en_sel",
asys_irq1_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8195_asys_irq_1x_en_sel_put,
MT8195_AFE_IRQ_13),
MT8195_SOC_ENUM_EXT("asys_irq2_1x_en_sel",
asys_irq2_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8195_asys_irq_1x_en_sel_put,
MT8195_AFE_IRQ_14),
MT8195_SOC_ENUM_EXT("asys_irq3_1x_en_sel",
asys_irq3_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8195_asys_irq_1x_en_sel_put,
MT8195_AFE_IRQ_15),
MT8195_SOC_ENUM_EXT("asys_irq4_1x_en_sel",
asys_irq4_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8195_asys_irq_1x_en_sel_put,
MT8195_AFE_IRQ_16),
MT8195_SOC_ENUM_EXT("asys_irq5_1x_en_sel",
asys_irq5_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8195_asys_irq_1x_en_sel_put,
MT8195_AFE_IRQ_17),
MT8195_SOC_ENUM_EXT("asys_irq6_1x_en_sel",
asys_irq6_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8195_asys_irq_1x_en_sel_put,
MT8195_AFE_IRQ_18),
MT8195_SOC_ENUM_EXT("asys_irq7_1x_en_sel",
asys_irq7_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8195_asys_irq_1x_en_sel_put,
MT8195_AFE_IRQ_19),
MT8195_SOC_ENUM_EXT("asys_irq8_1x_en_sel",
asys_irq8_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8195_asys_irq_1x_en_sel_put,
MT8195_AFE_IRQ_20),
MT8195_SOC_ENUM_EXT("asys_irq9_1x_en_sel",
asys_irq9_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8195_asys_irq_1x_en_sel_put,
MT8195_AFE_IRQ_21),
MT8195_SOC_ENUM_EXT("asys_irq10_1x_en_sel",
asys_irq10_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8195_asys_irq_1x_en_sel_put,
MT8195_AFE_IRQ_22),
MT8195_SOC_ENUM_EXT("asys_irq11_1x_en_sel",
asys_irq11_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8195_asys_irq_1x_en_sel_put,
MT8195_AFE_IRQ_23),
MT8195_SOC_ENUM_EXT("asys_irq12_1x_en_sel",
asys_irq12_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8195_asys_irq_1x_en_sel_put,
MT8195_AFE_IRQ_24),
MT8195_SOC_ENUM_EXT("asys_irq13_1x_en_sel",
asys_irq13_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8195_asys_irq_1x_en_sel_put,
MT8195_AFE_IRQ_25),
MT8195_SOC_ENUM_EXT("asys_irq14_1x_en_sel",
asys_irq14_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8195_asys_irq_1x_en_sel_put,
MT8195_AFE_IRQ_26),
MT8195_SOC_ENUM_EXT("asys_irq15_1x_en_sel",
asys_irq15_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8195_asys_irq_1x_en_sel_put,
MT8195_AFE_IRQ_27),
MT8195_SOC_ENUM_EXT("asys_irq16_1x_en_sel",
asys_irq16_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8195_asys_irq_1x_en_sel_put,
MT8195_AFE_IRQ_28),
};
static const struct snd_soc_component_driver mt8195_afe_pcm_dai_component = {
.name = "mt8195-afe-pcm-dai",
};
static const struct mtk_base_memif_data memif_data[MT8195_AFE_MEMIF_NUM] = {
[MT8195_AFE_MEMIF_DL2] = {
.name = "DL2",
.id = MT8195_AFE_MEMIF_DL2,
.reg_ofs_base = AFE_DL2_BASE,
.reg_ofs_cur = AFE_DL2_CUR,
.reg_ofs_end = AFE_DL2_END,
.fs_reg = AFE_MEMIF_AGENT_FS_CON0,
.fs_shift = 10,
.fs_maskbit = 0x1f,
.mono_reg = -1,
.mono_shift = 0,
.int_odd_flag_reg = -1,
.int_odd_flag_shift = 0,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 18,
.hd_reg = AFE_DL2_CON0,
.hd_shift = 5,
.agent_disable_reg = AUDIO_TOP_CON5,
.agent_disable_shift = 18,
.ch_num_reg = AFE_DL2_CON0,
.ch_num_shift = 0,
.ch_num_maskbit = 0x1f,
.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
.msb_shift = 18,
.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
.msb_end_shift = 18,
},
[MT8195_AFE_MEMIF_DL3] = {
.name = "DL3",
.id = MT8195_AFE_MEMIF_DL3,
.reg_ofs_base = AFE_DL3_BASE,
.reg_ofs_cur = AFE_DL3_CUR,
.reg_ofs_end = AFE_DL3_END,
.fs_reg = AFE_MEMIF_AGENT_FS_CON0,
.fs_shift = 15,
.fs_maskbit = 0x1f,
.mono_reg = -1,
.mono_shift = 0,
.int_odd_flag_reg = -1,
.int_odd_flag_shift = 0,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 19,
.hd_reg = AFE_DL3_CON0,
.hd_shift = 5,
.agent_disable_reg = AUDIO_TOP_CON5,
.agent_disable_shift = 19,
.ch_num_reg = AFE_DL3_CON0,
.ch_num_shift = 0,
.ch_num_maskbit = 0x1f,
.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
.msb_shift = 19,
.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
.msb_end_shift = 19,
},
[MT8195_AFE_MEMIF_DL6] = {
.name = "DL6",
.id = MT8195_AFE_MEMIF_DL6,
.reg_ofs_base = AFE_DL6_BASE,
.reg_ofs_cur = AFE_DL6_CUR,
.reg_ofs_end = AFE_DL6_END,
.fs_reg = AFE_MEMIF_AGENT_FS_CON1,
.fs_shift = 0,
.fs_maskbit = 0x1f,
.mono_reg = -1,
.mono_shift = 0,
.int_odd_flag_reg = -1,
.int_odd_flag_shift = 0,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 22,
.hd_reg = AFE_DL6_CON0,
.hd_shift = 5,
.agent_disable_reg = AUDIO_TOP_CON5,
.agent_disable_shift = 22,
.ch_num_reg = AFE_DL6_CON0,
.ch_num_shift = 0,
.ch_num_maskbit = 0x1f,
.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
.msb_shift = 22,
.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
.msb_end_shift = 22,
},
[MT8195_AFE_MEMIF_DL7] = {
.name = "DL7",
.id = MT8195_AFE_MEMIF_DL7,
.reg_ofs_base = AFE_DL7_BASE,
.reg_ofs_cur = AFE_DL7_CUR,
.reg_ofs_end = AFE_DL7_END,
.fs_reg = -1,
.fs_shift = 0,
.fs_maskbit = 0,
.mono_reg = -1,
.mono_shift = 0,
.int_odd_flag_reg = -1,
.int_odd_flag_shift = 0,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 23,
.hd_reg = AFE_DL7_CON0,
.hd_shift = 5,
.agent_disable_reg = AUDIO_TOP_CON5,
.agent_disable_shift = 23,
.ch_num_reg = AFE_DL7_CON0,
.ch_num_shift = 0,
.ch_num_maskbit = 0x1f,
.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
.msb_shift = 23,
.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
.msb_end_shift = 23,
},
[MT8195_AFE_MEMIF_DL8] = {
.name = "DL8",
.id = MT8195_AFE_MEMIF_DL8,
.reg_ofs_base = AFE_DL8_BASE,
.reg_ofs_cur = AFE_DL8_CUR,
.reg_ofs_end = AFE_DL8_END,
.fs_reg = AFE_MEMIF_AGENT_FS_CON1,
.fs_shift = 10,
.fs_maskbit = 0x1f,
.mono_reg = -1,
.mono_shift = 0,
.int_odd_flag_reg = -1,
.int_odd_flag_shift = 0,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 24,
.hd_reg = AFE_DL8_CON0,
.hd_shift = 6,
.agent_disable_reg = -1,
.agent_disable_shift = 0,
.ch_num_reg = AFE_DL8_CON0,
.ch_num_shift = 0,
.ch_num_maskbit = 0x3f,
.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
.msb_shift = 24,
.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
.msb_end_shift = 24,
},
[MT8195_AFE_MEMIF_DL10] = {
.name = "DL10",
.id = MT8195_AFE_MEMIF_DL10,
.reg_ofs_base = AFE_DL10_BASE,
.reg_ofs_cur = AFE_DL10_CUR,
.reg_ofs_end = AFE_DL10_END,
.fs_reg = AFE_MEMIF_AGENT_FS_CON1,
.fs_shift = 20,
.fs_maskbit = 0x1f,
.mono_reg = -1,
.mono_shift = 0,
.int_odd_flag_reg = -1,
.int_odd_flag_shift = 0,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 26,
.hd_reg = AFE_DL10_CON0,
.hd_shift = 5,
.agent_disable_reg = -1,
.agent_disable_shift = 0,
.ch_num_reg = AFE_DL10_CON0,
.ch_num_shift = 0,
.ch_num_maskbit = 0x1f,
.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
.msb_shift = 26,
.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
.msb_end_shift = 26,
},
[MT8195_AFE_MEMIF_DL11] = {
.name = "DL11",
.id = MT8195_AFE_MEMIF_DL11,
.reg_ofs_base = AFE_DL11_BASE,
.reg_ofs_cur = AFE_DL11_CUR,
.reg_ofs_end = AFE_DL11_END,
.fs_reg = AFE_MEMIF_AGENT_FS_CON1,
.fs_shift = 25,
.fs_maskbit = 0x1f,
.mono_reg = -1,
.mono_shift = 0,
.int_odd_flag_reg = -1,
.int_odd_flag_shift = 0,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 27,
.hd_reg = AFE_DL11_CON0,
.hd_shift = 7,
.agent_disable_reg = AUDIO_TOP_CON5,
.agent_disable_shift = 27,
.ch_num_reg = AFE_DL11_CON0,
.ch_num_shift = 0,
.ch_num_maskbit = 0x7f,
.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
.msb_shift = 27,
.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
.msb_end_shift = 27,
},
[MT8195_AFE_MEMIF_UL1] = {
.name = "UL1",
.id = MT8195_AFE_MEMIF_UL1,
.reg_ofs_base = AFE_UL1_BASE,
.reg_ofs_cur = AFE_UL1_CUR,
.reg_ofs_end = AFE_UL1_END,
.fs_reg = -1,
.fs_shift = 0,
.fs_maskbit = 0,
.mono_reg = AFE_UL1_CON0,
.mono_shift = 1,
.int_odd_flag_reg = AFE_UL1_CON0,
.int_odd_flag_shift = 0,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 1,
.hd_reg = AFE_UL1_CON0,
.hd_shift = 5,
.agent_disable_reg = AUDIO_TOP_CON5,
.agent_disable_shift = 0,
.ch_num_reg = -1,
.ch_num_shift = 0,
.ch_num_maskbit = 0,
.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
.msb_shift = 0,
.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
.msb_end_shift = 0,
},
[MT8195_AFE_MEMIF_UL2] = {
.name = "UL2",
.id = MT8195_AFE_MEMIF_UL2,
.reg_ofs_base = AFE_UL2_BASE,
.reg_ofs_cur = AFE_UL2_CUR,
.reg_ofs_end = AFE_UL2_END,
.fs_reg = AFE_MEMIF_AGENT_FS_CON2,
.fs_shift = 5,
.fs_maskbit = 0x1f,
.mono_reg = AFE_UL2_CON0,
.mono_shift = 1,
.int_odd_flag_reg = AFE_UL2_CON0,
.int_odd_flag_shift = 0,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 2,
.hd_reg = AFE_UL2_CON0,
.hd_shift = 5,
.agent_disable_reg = AUDIO_TOP_CON5,
.agent_disable_shift = 1,
.ch_num_reg = -1,
.ch_num_shift = 0,
.ch_num_maskbit = 0,
.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
.msb_shift = 1,
.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
.msb_end_shift = 1,
},
[MT8195_AFE_MEMIF_UL3] = {
.name = "UL3",
.id = MT8195_AFE_MEMIF_UL3,
.reg_ofs_base = AFE_UL3_BASE,
.reg_ofs_cur = AFE_UL3_CUR,
.reg_ofs_end = AFE_UL3_END,
.fs_reg = AFE_MEMIF_AGENT_FS_CON2,
.fs_shift = 10,
.fs_maskbit = 0x1f,
.mono_reg = AFE_UL3_CON0,
.mono_shift = 1,
.int_odd_flag_reg = AFE_UL3_CON0,
.int_odd_flag_shift = 0,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 3,
.hd_reg = AFE_UL3_CON0,
.hd_shift = 5,
.agent_disable_reg = AUDIO_TOP_CON5,
.agent_disable_shift = 2,
.ch_num_reg = -1,
.ch_num_shift = 0,
.ch_num_maskbit = 0,
.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
.msb_shift = 2,
.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
.msb_end_shift = 2,
},
[MT8195_AFE_MEMIF_UL4] = {
.name = "UL4",
.id = MT8195_AFE_MEMIF_UL4,
.reg_ofs_base = AFE_UL4_BASE,
.reg_ofs_cur = AFE_UL4_CUR,
.reg_ofs_end = AFE_UL4_END,
.fs_reg = AFE_MEMIF_AGENT_FS_CON2,
.fs_shift = 15,
.fs_maskbit = 0x1f,
.mono_reg = AFE_UL4_CON0,
.mono_shift = 1,
.int_odd_flag_reg = AFE_UL4_CON0,
.int_odd_flag_shift = 0,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 4,
.hd_reg = AFE_UL4_CON0,
.hd_shift = 5,
.agent_disable_reg = AUDIO_TOP_CON5,
.agent_disable_shift = 3,
.ch_num_reg = -1,
.ch_num_shift = 0,
.ch_num_maskbit = 0,
.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
.msb_shift = 3,
.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
.msb_end_shift = 3,
},
[MT8195_AFE_MEMIF_UL5] = {
.name = "UL5",
.id = MT8195_AFE_MEMIF_UL5,
.reg_ofs_base = AFE_UL5_BASE,
.reg_ofs_cur = AFE_UL5_CUR,
.reg_ofs_end = AFE_UL5_END,
.fs_reg = AFE_MEMIF_AGENT_FS_CON2,
.fs_shift = 20,
.fs_maskbit = 0x1f,
.mono_reg = AFE_UL5_CON0,
.mono_shift = 1,
.int_odd_flag_reg = AFE_UL5_CON0,
.int_odd_flag_shift = 0,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 5,
.hd_reg = AFE_UL5_CON0,
.hd_shift = 5,
.agent_disable_reg = AUDIO_TOP_CON5,
.agent_disable_shift = 4,
.ch_num_reg = -1,
.ch_num_shift = 0,
.ch_num_maskbit = 0,
.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
.msb_shift = 4,
.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
.msb_end_shift = 4,
},
[MT8195_AFE_MEMIF_UL6] = {
.name = "UL6",
.id = MT8195_AFE_MEMIF_UL6,
.reg_ofs_base = AFE_UL6_BASE,
.reg_ofs_cur = AFE_UL6_CUR,
.reg_ofs_end = AFE_UL6_END,
.fs_reg = -1,
.fs_shift = 0,
.fs_maskbit = 0,
.mono_reg = AFE_UL6_CON0,
.mono_shift = 1,
.int_odd_flag_reg = AFE_UL6_CON0,
.int_odd_flag_shift = 0,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 6,
.hd_reg = AFE_UL6_CON0,
.hd_shift = 5,
.agent_disable_reg = AUDIO_TOP_CON5,
.agent_disable_shift = 5,
.ch_num_reg = -1,
.ch_num_shift = 0,
.ch_num_maskbit = 0,
.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
.msb_shift = 5,
.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
.msb_end_shift = 5,
},
[MT8195_AFE_MEMIF_UL8] = {
.name = "UL8",
.id = MT8195_AFE_MEMIF_UL8,
.reg_ofs_base = AFE_UL8_BASE,
.reg_ofs_cur = AFE_UL8_CUR,
.reg_ofs_end = AFE_UL8_END,
.fs_reg = AFE_MEMIF_AGENT_FS_CON3,
.fs_shift = 5,
.fs_maskbit = 0x1f,
.mono_reg = AFE_UL8_CON0,
.mono_shift = 1,
.int_odd_flag_reg = AFE_UL8_CON0,
.int_odd_flag_shift = 0,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 8,
.hd_reg = AFE_UL8_CON0,
.hd_shift = 5,
.agent_disable_reg = AUDIO_TOP_CON5,
.agent_disable_shift = 7,
.ch_num_reg = -1,
.ch_num_shift = 0,
.ch_num_maskbit = 0,
.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
.msb_shift = 7,
.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
.msb_end_shift = 7,
},
[MT8195_AFE_MEMIF_UL9] = {
.name = "UL9",
.id = MT8195_AFE_MEMIF_UL9,
.reg_ofs_base = AFE_UL9_BASE,
.reg_ofs_cur = AFE_UL9_CUR,
.reg_ofs_end = AFE_UL9_END,
.fs_reg = AFE_MEMIF_AGENT_FS_CON3,
.fs_shift = 10,
.fs_maskbit = 0x1f,
.mono_reg = AFE_UL9_CON0,
.mono_shift = 1,
.int_odd_flag_reg = AFE_UL9_CON0,
.int_odd_flag_shift = 0,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 9,
.hd_reg = AFE_UL9_CON0,
.hd_shift = 5,
.agent_disable_reg = AUDIO_TOP_CON5,
.agent_disable_shift = 8,
.ch_num_reg = -1,
.ch_num_shift = 0,
.ch_num_maskbit = 0,
.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
.msb_shift = 8,
.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
.msb_end_shift = 8,
},
[MT8195_AFE_MEMIF_UL10] = {
.name = "UL10",
.id = MT8195_AFE_MEMIF_UL10,
.reg_ofs_base = AFE_UL10_BASE,
.reg_ofs_cur = AFE_UL10_CUR,
.reg_ofs_end = AFE_UL10_END,
.fs_reg = AFE_MEMIF_AGENT_FS_CON3,
.fs_shift = 15,
.fs_maskbit = 0x1f,
.mono_reg = AFE_UL10_CON0,
.mono_shift = 1,
.int_odd_flag_reg = AFE_UL10_CON0,
.int_odd_flag_shift = 0,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 10,
.hd_reg = AFE_UL10_CON0,
.hd_shift = 5,
.agent_disable_reg = AUDIO_TOP_CON5,
.agent_disable_shift = 9,
.ch_num_reg = -1,
.ch_num_shift = 0,
.ch_num_maskbit = 0,
.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
.msb_shift = 9,
.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
.msb_end_shift = 9,
},
};
static const struct mtk_base_irq_data irq_data_array[MT8195_AFE_IRQ_NUM] = {
[MT8195_AFE_IRQ_1] = {
.id = MT8195_AFE_IRQ_1,
.irq_cnt_reg = -1,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0,
.irq_fs_reg = -1,
.irq_fs_shift = 0,
.irq_fs_maskbit = 0,
.irq_en_reg = AFE_IRQ1_CON,
.irq_en_shift = 31,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = 0,
.irq_status_shift = 16,
},
[MT8195_AFE_IRQ_2] = {
.id = MT8195_AFE_IRQ_2,
.irq_cnt_reg = -1,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0,
.irq_fs_reg = -1,
.irq_fs_shift = 0,
.irq_fs_maskbit = 0,
.irq_en_reg = AFE_IRQ2_CON,
.irq_en_shift = 31,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = 1,
.irq_status_shift = 17,
},
[MT8195_AFE_IRQ_3] = {
.id = MT8195_AFE_IRQ_3,
.irq_cnt_reg = AFE_IRQ3_CON,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0xffffff,
.irq_fs_reg = -1,
.irq_fs_shift = 0,
.irq_fs_maskbit = 0,
.irq_en_reg = AFE_IRQ3_CON,
.irq_en_shift = 31,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = 2,
.irq_status_shift = 18,
},
[MT8195_AFE_IRQ_8] = {
.id = MT8195_AFE_IRQ_8,
.irq_cnt_reg = -1,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0,
.irq_fs_reg = -1,
.irq_fs_shift = 0,
.irq_fs_maskbit = 0,
.irq_en_reg = AFE_IRQ8_CON,
.irq_en_shift = 31,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = 7,
.irq_status_shift = 23,
},
[MT8195_AFE_IRQ_9] = {
.id = MT8195_AFE_IRQ_9,
.irq_cnt_reg = AFE_IRQ9_CON,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0xffffff,
.irq_fs_reg = -1,
.irq_fs_shift = 0,
.irq_fs_maskbit = 0,
.irq_en_reg = AFE_IRQ9_CON,
.irq_en_shift = 31,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = 8,
.irq_status_shift = 24,
},
[MT8195_AFE_IRQ_10] = {
.id = MT8195_AFE_IRQ_10,
.irq_cnt_reg = -1,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0,
.irq_fs_reg = -1,
.irq_fs_shift = 0,
.irq_fs_maskbit = 0,
.irq_en_reg = AFE_IRQ10_CON,
.irq_en_shift = 31,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = 9,
.irq_status_shift = 25,
},
[MT8195_AFE_IRQ_13] = {
.id = MT8195_AFE_IRQ_13,
.irq_cnt_reg = ASYS_IRQ1_CON,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0xffffff,
.irq_fs_reg = ASYS_IRQ1_CON,
.irq_fs_shift = 24,
.irq_fs_maskbit = 0x1ffff,
.irq_en_reg = ASYS_IRQ1_CON,
.irq_en_shift = 31,
.irq_clr_reg = ASYS_IRQ_CLR,
.irq_clr_shift = 0,
.irq_status_shift = 0,
},
[MT8195_AFE_IRQ_14] = {
.id = MT8195_AFE_IRQ_14,
.irq_cnt_reg = ASYS_IRQ2_CON,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0xffffff,
.irq_fs_reg = ASYS_IRQ2_CON,
.irq_fs_shift = 24,
.irq_fs_maskbit = 0x1ffff,
.irq_en_reg = ASYS_IRQ2_CON,
.irq_en_shift = 31,
.irq_clr_reg = ASYS_IRQ_CLR,
.irq_clr_shift = 1,
.irq_status_shift = 1,
},
[MT8195_AFE_IRQ_15] = {
.id = MT8195_AFE_IRQ_15,
.irq_cnt_reg = ASYS_IRQ3_CON,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0xffffff,
.irq_fs_reg = ASYS_IRQ3_CON,
.irq_fs_shift = 24,
.irq_fs_maskbit = 0x1ffff,
.irq_en_reg = ASYS_IRQ3_CON,
.irq_en_shift = 31,
.irq_clr_reg = ASYS_IRQ_CLR,
.irq_clr_shift = 2,
.irq_status_shift = 2,
},
[MT8195_AFE_IRQ_16] = {
.id = MT8195_AFE_IRQ_16,
.irq_cnt_reg = ASYS_IRQ4_CON,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0xffffff,
.irq_fs_reg = ASYS_IRQ4_CON,
.irq_fs_shift = 24,
.irq_fs_maskbit = 0x1ffff,
.irq_en_reg = ASYS_IRQ4_CON,
.irq_en_shift = 31,
.irq_clr_reg = ASYS_IRQ_CLR,
.irq_clr_shift = 3,
.irq_status_shift = 3,
},
[MT8195_AFE_IRQ_17] = {
.id = MT8195_AFE_IRQ_17,
.irq_cnt_reg = ASYS_IRQ5_CON,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0xffffff,
.irq_fs_reg = ASYS_IRQ5_CON,
.irq_fs_shift = 24,
.irq_fs_maskbit = 0x1ffff,
.irq_en_reg = ASYS_IRQ5_CON,
.irq_en_shift = 31,
.irq_clr_reg = ASYS_IRQ_CLR,
.irq_clr_shift = 4,
.irq_status_shift = 4,
},
[MT8195_AFE_IRQ_18] = {
.id = MT8195_AFE_IRQ_18,
.irq_cnt_reg = ASYS_IRQ6_CON,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0xffffff,
.irq_fs_reg = ASYS_IRQ6_CON,
.irq_fs_shift = 24,
.irq_fs_maskbit = 0x1ffff,
.irq_en_reg = ASYS_IRQ6_CON,
.irq_en_shift = 31,
.irq_clr_reg = ASYS_IRQ_CLR,
.irq_clr_shift = 5,
.irq_status_shift = 5,
},
[MT8195_AFE_IRQ_19] = {
.id = MT8195_AFE_IRQ_19,
.irq_cnt_reg = ASYS_IRQ7_CON,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0xffffff,
.irq_fs_reg = ASYS_IRQ7_CON,
.irq_fs_shift = 24,
.irq_fs_maskbit = 0x1ffff,
.irq_en_reg = ASYS_IRQ7_CON,
.irq_en_shift = 31,
.irq_clr_reg = ASYS_IRQ_CLR,
.irq_clr_shift = 6,
.irq_status_shift = 6,
},
[MT8195_AFE_IRQ_20] = {
.id = MT8195_AFE_IRQ_20,
.irq_cnt_reg = ASYS_IRQ8_CON,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0xffffff,
.irq_fs_reg = ASYS_IRQ8_CON,
.irq_fs_shift = 24,
.irq_fs_maskbit = 0x1ffff,
.irq_en_reg = ASYS_IRQ8_CON,
.irq_en_shift = 31,
.irq_clr_reg = ASYS_IRQ_CLR,
.irq_clr_shift = 7,
.irq_status_shift = 7,
},
[MT8195_AFE_IRQ_21] = {
.id = MT8195_AFE_IRQ_21,
.irq_cnt_reg = ASYS_IRQ9_CON,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0xffffff,
.irq_fs_reg = ASYS_IRQ9_CON,
.irq_fs_shift = 24,
.irq_fs_maskbit = 0x1ffff,
.irq_en_reg = ASYS_IRQ9_CON,
.irq_en_shift = 31,
.irq_clr_reg = ASYS_IRQ_CLR,
.irq_clr_shift = 8,
.irq_status_shift = 8,
},
[MT8195_AFE_IRQ_22] = {
.id = MT8195_AFE_IRQ_22,
.irq_cnt_reg = ASYS_IRQ10_CON,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0xffffff,
.irq_fs_reg = ASYS_IRQ10_CON,
.irq_fs_shift = 24,
.irq_fs_maskbit = 0x1ffff,
.irq_en_reg = ASYS_IRQ10_CON,
.irq_en_shift = 31,
.irq_clr_reg = ASYS_IRQ_CLR,
.irq_clr_shift = 9,
.irq_status_shift = 9,
},
[MT8195_AFE_IRQ_23] = {
.id = MT8195_AFE_IRQ_23,
.irq_cnt_reg = ASYS_IRQ11_CON,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0xffffff,
.irq_fs_reg = ASYS_IRQ11_CON,
.irq_fs_shift = 24,
.irq_fs_maskbit = 0x1ffff,
.irq_en_reg = ASYS_IRQ11_CON,
.irq_en_shift = 31,
.irq_clr_reg = ASYS_IRQ_CLR,
.irq_clr_shift = 10,
.irq_status_shift = 10,
},
[MT8195_AFE_IRQ_24] = {
.id = MT8195_AFE_IRQ_24,
.irq_cnt_reg = ASYS_IRQ12_CON,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0xffffff,
.irq_fs_reg = ASYS_IRQ12_CON,
.irq_fs_shift = 24,
.irq_fs_maskbit = 0x1ffff,
.irq_en_reg = ASYS_IRQ12_CON,
.irq_en_shift = 31,
.irq_clr_reg = ASYS_IRQ_CLR,
.irq_clr_shift = 11,
.irq_status_shift = 11,
},
[MT8195_AFE_IRQ_25] = {
.id = MT8195_AFE_IRQ_25,
.irq_cnt_reg = ASYS_IRQ13_CON,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0xffffff,
.irq_fs_reg = ASYS_IRQ13_CON,
.irq_fs_shift = 24,
.irq_fs_maskbit = 0x1ffff,
.irq_en_reg = ASYS_IRQ13_CON,
.irq_en_shift = 31,
.irq_clr_reg = ASYS_IRQ_CLR,
.irq_clr_shift = 12,
.irq_status_shift = 12,
},
[MT8195_AFE_IRQ_26] = {
.id = MT8195_AFE_IRQ_26,
.irq_cnt_reg = ASYS_IRQ14_CON,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0xffffff,
.irq_fs_reg = ASYS_IRQ14_CON,
.irq_fs_shift = 24,
.irq_fs_maskbit = 0x1ffff,
.irq_en_reg = ASYS_IRQ14_CON,
.irq_en_shift = 31,
.irq_clr_reg = ASYS_IRQ_CLR,
.irq_clr_shift = 13,
.irq_status_shift = 13,
},
[MT8195_AFE_IRQ_27] = {
.id = MT8195_AFE_IRQ_27,
.irq_cnt_reg = ASYS_IRQ15_CON,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0xffffff,
.irq_fs_reg = ASYS_IRQ15_CON,
.irq_fs_shift = 24,
.irq_fs_maskbit = 0x1ffff,
.irq_en_reg = ASYS_IRQ15_CON,
.irq_en_shift = 31,
.irq_clr_reg = ASYS_IRQ_CLR,
.irq_clr_shift = 14,
.irq_status_shift = 14,
},
[MT8195_AFE_IRQ_28] = {
.id = MT8195_AFE_IRQ_28,
.irq_cnt_reg = ASYS_IRQ16_CON,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0xffffff,
.irq_fs_reg = ASYS_IRQ16_CON,
.irq_fs_shift = 24,
.irq_fs_maskbit = 0x1ffff,
.irq_en_reg = ASYS_IRQ16_CON,
.irq_en_shift = 31,
.irq_clr_reg = ASYS_IRQ_CLR,
.irq_clr_shift = 15,
.irq_status_shift = 15,
},
};
static const int mt8195_afe_memif_const_irqs[MT8195_AFE_MEMIF_NUM] = {
[MT8195_AFE_MEMIF_DL2] = MT8195_AFE_IRQ_13,
[MT8195_AFE_MEMIF_DL3] = MT8195_AFE_IRQ_14,
[MT8195_AFE_MEMIF_DL6] = MT8195_AFE_IRQ_15,
[MT8195_AFE_MEMIF_DL7] = MT8195_AFE_IRQ_1,
[MT8195_AFE_MEMIF_DL8] = MT8195_AFE_IRQ_16,
[MT8195_AFE_MEMIF_DL10] = MT8195_AFE_IRQ_17,
[MT8195_AFE_MEMIF_DL11] = MT8195_AFE_IRQ_18,
[MT8195_AFE_MEMIF_UL1] = MT8195_AFE_IRQ_3,
[MT8195_AFE_MEMIF_UL2] = MT8195_AFE_IRQ_19,
[MT8195_AFE_MEMIF_UL3] = MT8195_AFE_IRQ_20,
[MT8195_AFE_MEMIF_UL4] = MT8195_AFE_IRQ_21,
[MT8195_AFE_MEMIF_UL5] = MT8195_AFE_IRQ_22,
[MT8195_AFE_MEMIF_UL6] = MT8195_AFE_IRQ_9,
[MT8195_AFE_MEMIF_UL8] = MT8195_AFE_IRQ_23,
[MT8195_AFE_MEMIF_UL9] = MT8195_AFE_IRQ_24,
[MT8195_AFE_MEMIF_UL10] = MT8195_AFE_IRQ_25,
};
static bool mt8195_is_volatile_reg(struct device *dev, unsigned int reg)
{
/* these auto-gen reg has read-only bit, so put it as volatile */
/* volatile reg cannot be cached, so cannot be set when power off */
switch (reg) {
case AUDIO_TOP_CON0:
case AUDIO_TOP_CON1:
case AUDIO_TOP_CON3:
case AUDIO_TOP_CON4:
case AUDIO_TOP_CON5:
case AUDIO_TOP_CON6:
case ASYS_IRQ_CLR:
case ASYS_IRQ_STATUS:
case ASYS_IRQ_MON1:
case ASYS_IRQ_MON2:
case AFE_IRQ_MCU_CLR:
case AFE_IRQ_STATUS:
case AFE_IRQ3_CON_MON:
case AFE_IRQ_MCU_MON2:
case ADSP_IRQ_STATUS:
case AUDIO_TOP_STA0:
case AUDIO_TOP_STA1:
case AFE_GAIN1_CUR:
case AFE_GAIN2_CUR:
case AFE_IEC_BURST_INFO:
case AFE_IEC_CHL_STAT0:
case AFE_IEC_CHL_STAT1:
case AFE_IEC_CHR_STAT0:
case AFE_IEC_CHR_STAT1:
case AFE_SPDIFIN_CHSTS1:
case AFE_SPDIFIN_CHSTS2:
case AFE_SPDIFIN_CHSTS3:
case AFE_SPDIFIN_CHSTS4:
case AFE_SPDIFIN_CHSTS5:
case AFE_SPDIFIN_CHSTS6:
case AFE_SPDIFIN_DEBUG1:
case AFE_SPDIFIN_DEBUG2:
case AFE_SPDIFIN_DEBUG3:
case AFE_SPDIFIN_DEBUG4:
case AFE_SPDIFIN_EC:
case AFE_SPDIFIN_CKLOCK_CFG:
case AFE_SPDIFIN_BR_DBG1:
case AFE_SPDIFIN_CKFBDIV:
case AFE_SPDIFIN_INT_EXT:
case AFE_SPDIFIN_INT_EXT2:
case SPDIFIN_FREQ_STATUS:
case SPDIFIN_USERCODE1:
case SPDIFIN_USERCODE2:
case SPDIFIN_USERCODE3:
case SPDIFIN_USERCODE4:
case SPDIFIN_USERCODE5:
case SPDIFIN_USERCODE6:
case SPDIFIN_USERCODE7:
case SPDIFIN_USERCODE8:
case SPDIFIN_USERCODE9:
case SPDIFIN_USERCODE10:
case SPDIFIN_USERCODE11:
case SPDIFIN_USERCODE12:
case AFE_LINEIN_APLL_TUNER_MON:
case AFE_EARC_APLL_TUNER_MON:
case AFE_CM0_MON:
case AFE_CM1_MON:
case AFE_CM2_MON:
case AFE_MPHONE_MULTI_DET_MON0:
case AFE_MPHONE_MULTI_DET_MON1:
case AFE_MPHONE_MULTI_DET_MON2:
case AFE_MPHONE_MULTI2_DET_MON0:
case AFE_MPHONE_MULTI2_DET_MON1:
case AFE_MPHONE_MULTI2_DET_MON2:
case AFE_ADDA_MTKAIF_MON0:
case AFE_ADDA_MTKAIF_MON1:
case AFE_AUD_PAD_TOP:
case AFE_ADDA6_MTKAIF_MON0:
case AFE_ADDA6_MTKAIF_MON1:
case AFE_ADDA6_SRC_DEBUG_MON0:
case AFE_ADDA6_UL_SRC_MON0:
case AFE_ADDA6_UL_SRC_MON1:
case AFE_ASRC11_NEW_CON8:
case AFE_ASRC11_NEW_CON9:
case AFE_ASRC12_NEW_CON8:
case AFE_ASRC12_NEW_CON9:
case AFE_LRCK_CNT:
case AFE_DAC_MON0:
case AFE_DL2_CUR:
case AFE_DL3_CUR:
case AFE_DL6_CUR:
case AFE_DL7_CUR:
case AFE_DL8_CUR:
case AFE_DL10_CUR:
case AFE_DL11_CUR:
case AFE_UL1_CUR:
case AFE_UL2_CUR:
case AFE_UL3_CUR:
case AFE_UL4_CUR:
case AFE_UL5_CUR:
case AFE_UL6_CUR:
case AFE_UL8_CUR:
case AFE_UL9_CUR:
case AFE_UL10_CUR:
case AFE_DL8_CHK_SUM1:
case AFE_DL8_CHK_SUM2:
case AFE_DL8_CHK_SUM3:
case AFE_DL8_CHK_SUM4:
case AFE_DL8_CHK_SUM5:
case AFE_DL8_CHK_SUM6:
case AFE_DL10_CHK_SUM1:
case AFE_DL10_CHK_SUM2:
case AFE_DL10_CHK_SUM3:
case AFE_DL10_CHK_SUM4:
case AFE_DL10_CHK_SUM5:
case AFE_DL10_CHK_SUM6:
case AFE_DL11_CHK_SUM1:
case AFE_DL11_CHK_SUM2:
case AFE_DL11_CHK_SUM3:
case AFE_DL11_CHK_SUM4:
case AFE_DL11_CHK_SUM5:
case AFE_DL11_CHK_SUM6:
case AFE_UL1_CHK_SUM1:
case AFE_UL1_CHK_SUM2:
case AFE_UL2_CHK_SUM1:
case AFE_UL2_CHK_SUM2:
case AFE_UL3_CHK_SUM1:
case AFE_UL3_CHK_SUM2:
case AFE_UL4_CHK_SUM1:
case AFE_UL4_CHK_SUM2:
case AFE_UL5_CHK_SUM1:
case AFE_UL5_CHK_SUM2:
case AFE_UL6_CHK_SUM1:
case AFE_UL6_CHK_SUM2:
case AFE_UL8_CHK_SUM1:
case AFE_UL8_CHK_SUM2:
case AFE_DL2_CHK_SUM1:
case AFE_DL2_CHK_SUM2:
case AFE_DL3_CHK_SUM1:
case AFE_DL3_CHK_SUM2:
case AFE_DL6_CHK_SUM1:
case AFE_DL6_CHK_SUM2:
case AFE_DL7_CHK_SUM1:
case AFE_DL7_CHK_SUM2:
case AFE_UL9_CHK_SUM1:
case AFE_UL9_CHK_SUM2:
case AFE_BUS_MON1:
case UL1_MOD2AGT_CNT_LAT:
case UL2_MOD2AGT_CNT_LAT:
case UL3_MOD2AGT_CNT_LAT:
case UL4_MOD2AGT_CNT_LAT:
case UL5_MOD2AGT_CNT_LAT:
case UL6_MOD2AGT_CNT_LAT:
case UL8_MOD2AGT_CNT_LAT:
case UL9_MOD2AGT_CNT_LAT:
case UL10_MOD2AGT_CNT_LAT:
case AFE_MEMIF_BUF_FULL_MON:
case AFE_MEMIF_BUF_MON1:
case AFE_MEMIF_BUF_MON3:
case AFE_MEMIF_BUF_MON4:
case AFE_MEMIF_BUF_MON5:
case AFE_MEMIF_BUF_MON6:
case AFE_MEMIF_BUF_MON7:
case AFE_MEMIF_BUF_MON8:
case AFE_MEMIF_BUF_MON9:
case AFE_MEMIF_BUF_MON10:
case DL2_AGENT2MODULE_CNT:
case DL3_AGENT2MODULE_CNT:
case DL6_AGENT2MODULE_CNT:
case DL7_AGENT2MODULE_CNT:
case DL8_AGENT2MODULE_CNT:
case DL10_AGENT2MODULE_CNT:
case DL11_AGENT2MODULE_CNT:
case UL1_MODULE2AGENT_CNT:
case UL2_MODULE2AGENT_CNT:
case UL3_MODULE2AGENT_CNT:
case UL4_MODULE2AGENT_CNT:
case UL5_MODULE2AGENT_CNT:
case UL6_MODULE2AGENT_CNT:
case UL8_MODULE2AGENT_CNT:
case UL9_MODULE2AGENT_CNT:
case UL10_MODULE2AGENT_CNT:
case AFE_DMIC0_SRC_DEBUG_MON0:
case AFE_DMIC0_UL_SRC_MON0:
case AFE_DMIC0_UL_SRC_MON1:
case AFE_DMIC1_SRC_DEBUG_MON0:
case AFE_DMIC1_UL_SRC_MON0:
case AFE_DMIC1_UL_SRC_MON1:
case AFE_DMIC2_SRC_DEBUG_MON0:
case AFE_DMIC2_UL_SRC_MON0:
case AFE_DMIC2_UL_SRC_MON1:
case AFE_DMIC3_SRC_DEBUG_MON0:
case AFE_DMIC3_UL_SRC_MON0:
case AFE_DMIC3_UL_SRC_MON1:
case DMIC_GAIN1_CUR:
case DMIC_GAIN2_CUR:
case DMIC_GAIN3_CUR:
case DMIC_GAIN4_CUR:
case ETDM_IN1_MONITOR:
case ETDM_IN2_MONITOR:
case ETDM_OUT1_MONITOR:
case ETDM_OUT2_MONITOR:
case ETDM_OUT3_MONITOR:
case AFE_ADDA_SRC_DEBUG_MON0:
case AFE_ADDA_SRC_DEBUG_MON1:
case AFE_ADDA_DL_SDM_FIFO_MON:
case AFE_ADDA_DL_SRC_LCH_MON:
case AFE_ADDA_DL_SRC_RCH_MON:
case AFE_ADDA_DL_SDM_OUT_MON:
case AFE_GASRC0_NEW_CON8:
case AFE_GASRC0_NEW_CON9:
case AFE_GASRC0_NEW_CON12:
case AFE_GASRC1_NEW_CON8:
case AFE_GASRC1_NEW_CON9:
case AFE_GASRC1_NEW_CON12:
case AFE_GASRC2_NEW_CON8:
case AFE_GASRC2_NEW_CON9:
case AFE_GASRC2_NEW_CON12:
case AFE_GASRC3_NEW_CON8:
case AFE_GASRC3_NEW_CON9:
case AFE_GASRC3_NEW_CON12:
case AFE_GASRC4_NEW_CON8:
case AFE_GASRC4_NEW_CON9:
case AFE_GASRC4_NEW_CON12:
case AFE_GASRC5_NEW_CON8:
case AFE_GASRC5_NEW_CON9:
case AFE_GASRC5_NEW_CON12:
case AFE_GASRC6_NEW_CON8:
case AFE_GASRC6_NEW_CON9:
case AFE_GASRC6_NEW_CON12:
case AFE_GASRC7_NEW_CON8:
case AFE_GASRC7_NEW_CON9:
case AFE_GASRC7_NEW_CON12:
case AFE_GASRC8_NEW_CON8:
case AFE_GASRC8_NEW_CON9:
case AFE_GASRC8_NEW_CON12:
case AFE_GASRC9_NEW_CON8:
case AFE_GASRC9_NEW_CON9:
case AFE_GASRC9_NEW_CON12:
case AFE_GASRC10_NEW_CON8:
case AFE_GASRC10_NEW_CON9:
case AFE_GASRC10_NEW_CON12:
case AFE_GASRC11_NEW_CON8:
case AFE_GASRC11_NEW_CON9:
case AFE_GASRC11_NEW_CON12:
case AFE_GASRC12_NEW_CON8:
case AFE_GASRC12_NEW_CON9:
case AFE_GASRC12_NEW_CON12:
case AFE_GASRC13_NEW_CON8:
case AFE_GASRC13_NEW_CON9:
case AFE_GASRC13_NEW_CON12:
case AFE_GASRC14_NEW_CON8:
case AFE_GASRC14_NEW_CON9:
case AFE_GASRC14_NEW_CON12:
case AFE_GASRC15_NEW_CON8:
case AFE_GASRC15_NEW_CON9:
case AFE_GASRC15_NEW_CON12:
case AFE_GASRC16_NEW_CON8:
case AFE_GASRC16_NEW_CON9:
case AFE_GASRC16_NEW_CON12:
case AFE_GASRC17_NEW_CON8:
case AFE_GASRC17_NEW_CON9:
case AFE_GASRC17_NEW_CON12:
case AFE_GASRC18_NEW_CON8:
case AFE_GASRC18_NEW_CON9:
case AFE_GASRC18_NEW_CON12:
case AFE_GASRC19_NEW_CON8:
case AFE_GASRC19_NEW_CON9:
case AFE_GASRC19_NEW_CON12:
return true;
default:
return false;
};
}
static const struct regmap_config mt8195_afe_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.volatile_reg = mt8195_is_volatile_reg,
.max_register = AFE_MAX_REGISTER,
.num_reg_defaults_raw = ((AFE_MAX_REGISTER / 4) + 1),
.cache_type = REGCACHE_FLAT,
};
#define AFE_IRQ_CLR_BITS (0x387)
#define ASYS_IRQ_CLR_BITS (0xffff)
static irqreturn_t mt8195_afe_irq_handler(int irq_id, void *dev_id)
{
struct mtk_base_afe *afe = dev_id;
unsigned int val = 0;
unsigned int asys_irq_clr_bits = 0;
unsigned int afe_irq_clr_bits = 0;
unsigned int irq_status_bits = 0;
unsigned int irq_clr_bits = 0;
unsigned int mcu_irq_mask = 0;
int i = 0;
int ret = 0;
ret = regmap_read(afe->regmap, AFE_IRQ_STATUS, &val);
if (ret) {
dev_info(afe->dev, "%s irq status err\n", __func__);
afe_irq_clr_bits = AFE_IRQ_CLR_BITS;
asys_irq_clr_bits = ASYS_IRQ_CLR_BITS;
goto err_irq;
}
ret = regmap_read(afe->regmap, AFE_IRQ_MASK, &mcu_irq_mask);
if (ret) {
dev_info(afe->dev, "%s read irq mask err\n", __func__);
afe_irq_clr_bits = AFE_IRQ_CLR_BITS;
asys_irq_clr_bits = ASYS_IRQ_CLR_BITS;
goto err_irq;
}
/* only clr cpu irq */
val &= mcu_irq_mask;
for (i = 0; i < MT8195_AFE_MEMIF_NUM; i++) {
struct mtk_base_afe_memif *memif = &afe->memif[i];
struct mtk_base_irq_data const *irq_data;
if (memif->irq_usage < 0)
continue;
irq_data = afe->irqs[memif->irq_usage].irq_data;
irq_status_bits = BIT(irq_data->irq_status_shift);
irq_clr_bits = BIT(irq_data->irq_clr_shift);
if (!(val & irq_status_bits))
continue;
if (irq_data->irq_clr_reg == ASYS_IRQ_CLR)
asys_irq_clr_bits |= irq_clr_bits;
else
afe_irq_clr_bits |= irq_clr_bits;
snd_pcm_period_elapsed(memif->substream);
}
err_irq:
/* clear irq */
if (asys_irq_clr_bits)
regmap_write(afe->regmap, ASYS_IRQ_CLR, asys_irq_clr_bits);
if (afe_irq_clr_bits)
regmap_write(afe->regmap, AFE_IRQ_MCU_CLR, afe_irq_clr_bits);
return IRQ_HANDLED;
}
static int mt8195_afe_runtime_suspend(struct device *dev)
{
struct mtk_base_afe *afe = dev_get_drvdata(dev);
struct mt8195_afe_private *afe_priv = afe->platform_priv;
if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
goto skip_regmap;
mt8195_afe_disable_main_clock(afe);
regcache_cache_only(afe->regmap, true);
regcache_mark_dirty(afe->regmap);
skip_regmap:
mt8195_afe_disable_reg_rw_clk(afe);
return 0;
}
static int mt8195_afe_runtime_resume(struct device *dev)
{
struct mtk_base_afe *afe = dev_get_drvdata(dev);
struct mt8195_afe_private *afe_priv = afe->platform_priv;
mt8195_afe_enable_reg_rw_clk(afe);
if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
goto skip_regmap;
regcache_cache_only(afe->regmap, false);
regcache_sync(afe->regmap);
mt8195_afe_enable_main_clock(afe);
skip_regmap:
return 0;
}
static int mt8195_afe_component_probe(struct snd_soc_component *component)
{
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
int ret = 0;
snd_soc_component_init_regmap(component, afe->regmap);
ret = mtk_afe_add_sub_dai_control(component);
return ret;
}
static const struct snd_soc_component_driver mt8195_afe_component = {
.name = AFE_PCM_NAME,
.pointer = mtk_afe_pcm_pointer,
.pcm_construct = mtk_afe_pcm_new,
.probe = mt8195_afe_component_probe,
};
static int init_memif_priv_data(struct mtk_base_afe *afe)
{
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_memif_priv *memif_priv;
int i;
for (i = MT8195_AFE_MEMIF_START; i < MT8195_AFE_MEMIF_END; i++) {
memif_priv = devm_kzalloc(afe->dev,
sizeof(struct mtk_dai_memif_priv),
GFP_KERNEL);
if (!memif_priv)
return -ENOMEM;
afe_priv->dai_priv[i] = memif_priv;
}
return 0;
}
static int mt8195_dai_memif_register(struct mtk_base_afe *afe)
{
struct mtk_base_afe_dai *dai;
dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
if (!dai)
return -ENOMEM;
list_add(&dai->list, &afe->sub_dais);
dai->dai_drivers = mt8195_memif_dai_driver;
dai->num_dai_drivers = ARRAY_SIZE(mt8195_memif_dai_driver);
dai->dapm_widgets = mt8195_memif_widgets;
dai->num_dapm_widgets = ARRAY_SIZE(mt8195_memif_widgets);
dai->dapm_routes = mt8195_memif_routes;
dai->num_dapm_routes = ARRAY_SIZE(mt8195_memif_routes);
dai->controls = mt8195_memif_controls;
dai->num_controls = ARRAY_SIZE(mt8195_memif_controls);
return init_memif_priv_data(afe);
}
typedef int (*dai_register_cb)(struct mtk_base_afe *);
static const dai_register_cb dai_register_cbs[] = {
mt8195_dai_adda_register,
mt8195_dai_etdm_register,
mt8195_dai_pcm_register,
mt8195_dai_memif_register,
};
static const struct reg_sequence mt8195_afe_reg_defaults[] = {
{ AFE_IRQ_MASK, 0x387ffff },
{ AFE_IRQ3_CON, BIT(30) },
{ AFE_IRQ9_CON, BIT(30) },
{ ETDM_IN1_CON4, 0x12000100 },
{ ETDM_IN2_CON4, 0x12000100 },
};
static const struct reg_sequence mt8195_cg_patch[] = {
{ AUDIO_TOP_CON0, 0xfffffffb },
{ AUDIO_TOP_CON1, 0xfffffff8 },
};
static int mt8195_afe_pcm_dev_probe(struct platform_device *pdev)
{
struct mtk_base_afe *afe;
struct mt8195_afe_private *afe_priv;
struct device *dev = &pdev->dev;
struct reset_control *rstc;
int i, irq_id, ret;
struct snd_soc_component *component;
ret = of_reserved_mem_device_init(dev);
if (ret)
return dev_err_probe(dev, ret, "failed to assign memory region\n");
ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(33));
if (ret)
return ret;
afe = devm_kzalloc(dev, sizeof(*afe), GFP_KERNEL);
if (!afe)
return -ENOMEM;
afe->platform_priv = devm_kzalloc(dev, sizeof(*afe_priv),
GFP_KERNEL);
if (!afe->platform_priv)
return -ENOMEM;
afe_priv = afe->platform_priv;
afe->dev = &pdev->dev;
afe->base_addr = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(afe->base_addr))
return PTR_ERR(afe->base_addr);
/* initial audio related clock */
ret = mt8195_afe_init_clock(afe);
if (ret)
return dev_err_probe(dev, ret, "init clock error\n");
/* reset controller to reset audio regs before regmap cache */
rstc = devm_reset_control_get_exclusive(dev, "audiosys");
if (IS_ERR(rstc))
return dev_err_probe(dev, PTR_ERR(rstc), "could not get audiosys reset\n");
ret = reset_control_reset(rstc);
if (ret)
return dev_err_probe(dev, ret, "failed to trigger audio reset\n");
spin_lock_init(&afe_priv->afe_ctrl_lock);
mutex_init(&afe->irq_alloc_lock);
/* irq initialize */
afe->irqs_size = MT8195_AFE_IRQ_NUM;
afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
GFP_KERNEL);
if (!afe->irqs)
return -ENOMEM;
for (i = 0; i < afe->irqs_size; i++)
afe->irqs[i].irq_data = &irq_data_array[i];
/* init memif */
afe->memif_size = MT8195_AFE_MEMIF_NUM;
afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),
GFP_KERNEL);
if (!afe->memif)
return -ENOMEM;
for (i = 0; i < afe->memif_size; i++) {
afe->memif[i].data = &memif_data[i];
afe->memif[i].irq_usage = mt8195_afe_memif_const_irqs[i];
afe->memif[i].const_irq = 1;
afe->irqs[afe->memif[i].irq_usage].irq_occupyed = true;
}
/* request irq */
irq_id = platform_get_irq(pdev, 0);
if (irq_id < 0)
return -ENXIO;
ret = devm_request_irq(dev, irq_id, mt8195_afe_irq_handler,
IRQF_TRIGGER_NONE, "asys-isr", (void *)afe);
if (ret)
return dev_err_probe(dev, ret, "could not request_irq for asys-isr\n");
/* init sub_dais */
INIT_LIST_HEAD(&afe->sub_dais);
for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) {
ret = dai_register_cbs[i](afe);
if (ret)
return dev_err_probe(dev, ret, "dai cb%i register fail\n", i);
}
/* init dai_driver and component_driver */
ret = mtk_afe_combine_sub_dai(afe);
if (ret)
return dev_err_probe(dev, ret, "mtk_afe_combine_sub_dai fail\n");
afe->mtk_afe_hardware = &mt8195_afe_hardware;
afe->memif_fs = mt8195_memif_fs;
afe->irq_fs = mt8195_irq_fs;
afe->runtime_resume = mt8195_afe_runtime_resume;
afe->runtime_suspend = mt8195_afe_runtime_suspend;
platform_set_drvdata(pdev, afe);
afe_priv->topckgen = syscon_regmap_lookup_by_phandle(dev->of_node, "mediatek,topckgen");
if (IS_ERR(afe_priv->topckgen))
dev_dbg(afe->dev, "Cannot find topckgen controller: %ld\n",
PTR_ERR(afe_priv->topckgen));
/* enable clock for regcache get default value from hw */
afe_priv->pm_runtime_bypass_reg_ctl = true;
ret = devm_pm_runtime_enable(dev);
if (ret)
return ret;
ret = pm_runtime_resume_and_get(dev);
if (ret)
return dev_err_probe(dev, ret, "Failed to resume device\n");
afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr,
&mt8195_afe_regmap_config);
if (IS_ERR(afe->regmap)) {
ret = PTR_ERR(afe->regmap);
goto err_pm_put;
}
ret = regmap_register_patch(afe->regmap, mt8195_cg_patch,
ARRAY_SIZE(mt8195_cg_patch));
if (ret < 0) {
dev_err(dev, "Failed to apply cg patch\n");
goto err_pm_put;
}
/* register component */
ret = devm_snd_soc_register_component(dev, &mt8195_afe_component,
NULL, 0);
if (ret) {
dev_warn(dev, "err_platform\n");
goto err_pm_put;
}
component = devm_kzalloc(dev, sizeof(*component), GFP_KERNEL);
if (!component) {
ret = -ENOMEM;
goto err_pm_put;
}
ret = snd_soc_component_initialize(component,
&mt8195_afe_pcm_dai_component,
dev);
if (ret)
goto err_pm_put;
#ifdef CONFIG_DEBUG_FS
component->debugfs_prefix = "pcm";
#endif
ret = snd_soc_add_component(component,
afe->dai_drivers,
afe->num_dai_drivers);
if (ret) {
dev_warn(dev, "err_dai_component\n");
goto err_pm_put;
}
ret = regmap_multi_reg_write(afe->regmap, mt8195_afe_reg_defaults,
ARRAY_SIZE(mt8195_afe_reg_defaults));
if (ret)
goto err_pm_put;
ret = pm_runtime_put_sync(dev);
if (ret)
return dev_err_probe(dev, ret, "Failed to suspend device\n");
afe_priv->pm_runtime_bypass_reg_ctl = false;
regcache_cache_only(afe->regmap, true);
regcache_mark_dirty(afe->regmap);
return 0;
err_pm_put:
pm_runtime_put_sync(dev);
return ret;
}
static void mt8195_afe_pcm_dev_remove(struct platform_device *pdev)
{
snd_soc_unregister_component(&pdev->dev);
pm_runtime_disable(&pdev->dev);
if (!pm_runtime_status_suspended(&pdev->dev))
mt8195_afe_runtime_suspend(&pdev->dev);
}
static const struct of_device_id mt8195_afe_pcm_dt_match[] = {
{.compatible = "mediatek,mt8195-audio", },
{},
};
MODULE_DEVICE_TABLE(of, mt8195_afe_pcm_dt_match);
static const struct dev_pm_ops mt8195_afe_pm_ops = {
SET_RUNTIME_PM_OPS(mt8195_afe_runtime_suspend,
mt8195_afe_runtime_resume, NULL)
};
static struct platform_driver mt8195_afe_pcm_driver = {
.driver = {
.name = "mt8195-audio",
.of_match_table = mt8195_afe_pcm_dt_match,
.pm = &mt8195_afe_pm_ops,
},
.probe = mt8195_afe_pcm_dev_probe,
.remove_new = mt8195_afe_pcm_dev_remove,
};
module_platform_driver(mt8195_afe_pcm_driver);
MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 8195");
MODULE_AUTHOR("Bicycle Tsai <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/mediatek/mt8195/mt8195-afe-pcm.c |
// SPDX-License-Identifier: GPL-2.0
/*
* mt2701-wm8960.c -- MT2701 WM8960 ALSA SoC machine driver
*
* Copyright (c) 2017 MediaTek Inc.
* Author: Ryder Lee <[email protected]>
*/
#include <linux/module.h>
#include <sound/soc.h>
#include "mt2701-afe-common.h"
static const struct snd_soc_dapm_widget mt2701_wm8960_widgets[] = {
SND_SOC_DAPM_HP("Headphone", NULL),
SND_SOC_DAPM_MIC("AMIC", NULL),
};
static const struct snd_kcontrol_new mt2701_wm8960_controls[] = {
SOC_DAPM_PIN_SWITCH("Headphone"),
SOC_DAPM_PIN_SWITCH("AMIC"),
};
static int mt2701_wm8960_be_ops_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
unsigned int mclk_rate;
unsigned int rate = params_rate(params);
unsigned int div_mclk_over_bck = rate > 192000 ? 2 : 4;
unsigned int div_bck_over_lrck = 64;
mclk_rate = rate * div_bck_over_lrck * div_mclk_over_bck;
snd_soc_dai_set_sysclk(cpu_dai, 0, mclk_rate, SND_SOC_CLOCK_OUT);
snd_soc_dai_set_sysclk(codec_dai, 0, mclk_rate, SND_SOC_CLOCK_IN);
return 0;
}
static const struct snd_soc_ops mt2701_wm8960_be_ops = {
.hw_params = mt2701_wm8960_be_ops_hw_params
};
SND_SOC_DAILINK_DEFS(playback,
DAILINK_COMP_ARRAY(COMP_CPU("PCMO0")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture,
DAILINK_COMP_ARRAY(COMP_CPU("PCM0")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(codec,
DAILINK_COMP_ARRAY(COMP_CPU("I2S0")),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "wm8960-hifi")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
static struct snd_soc_dai_link mt2701_wm8960_dai_links[] = {
/* FE */
{
.name = "wm8960-playback",
.stream_name = "wm8960-playback",
.trigger = {SND_SOC_DPCM_TRIGGER_POST,
SND_SOC_DPCM_TRIGGER_POST},
.dynamic = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(playback),
},
{
.name = "wm8960-capture",
.stream_name = "wm8960-capture",
.trigger = {SND_SOC_DPCM_TRIGGER_POST,
SND_SOC_DPCM_TRIGGER_POST},
.dynamic = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(capture),
},
/* BE */
{
.name = "wm8960-codec",
.no_pcm = 1,
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS
| SND_SOC_DAIFMT_GATED,
.ops = &mt2701_wm8960_be_ops,
.dpcm_playback = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(codec),
},
};
static struct snd_soc_card mt2701_wm8960_card = {
.name = "mt2701-wm8960",
.owner = THIS_MODULE,
.dai_link = mt2701_wm8960_dai_links,
.num_links = ARRAY_SIZE(mt2701_wm8960_dai_links),
.controls = mt2701_wm8960_controls,
.num_controls = ARRAY_SIZE(mt2701_wm8960_controls),
.dapm_widgets = mt2701_wm8960_widgets,
.num_dapm_widgets = ARRAY_SIZE(mt2701_wm8960_widgets),
};
static int mt2701_wm8960_machine_probe(struct platform_device *pdev)
{
struct snd_soc_card *card = &mt2701_wm8960_card;
struct device_node *platform_node, *codec_node;
struct snd_soc_dai_link *dai_link;
int ret, i;
platform_node = of_parse_phandle(pdev->dev.of_node,
"mediatek,platform", 0);
if (!platform_node) {
dev_err(&pdev->dev, "Property 'platform' missing or invalid\n");
return -EINVAL;
}
for_each_card_prelinks(card, i, dai_link) {
if (dai_link->platforms->name)
continue;
dai_link->platforms->of_node = platform_node;
}
card->dev = &pdev->dev;
codec_node = of_parse_phandle(pdev->dev.of_node,
"mediatek,audio-codec", 0);
if (!codec_node) {
dev_err(&pdev->dev,
"Property 'audio-codec' missing or invalid\n");
ret = -EINVAL;
goto put_platform_node;
}
for_each_card_prelinks(card, i, dai_link) {
if (dai_link->codecs->name)
continue;
dai_link->codecs->of_node = codec_node;
}
ret = snd_soc_of_parse_audio_routing(card, "audio-routing");
if (ret) {
dev_err(&pdev->dev, "failed to parse audio-routing: %d\n", ret);
goto put_codec_node;
}
ret = devm_snd_soc_register_card(&pdev->dev, card);
if (ret)
dev_err(&pdev->dev, "%s snd_soc_register_card fail %d\n",
__func__, ret);
put_codec_node:
of_node_put(codec_node);
put_platform_node:
of_node_put(platform_node);
return ret;
}
#ifdef CONFIG_OF
static const struct of_device_id mt2701_wm8960_machine_dt_match[] = {
{.compatible = "mediatek,mt2701-wm8960-machine",},
{}
};
MODULE_DEVICE_TABLE(of, mt2701_wm8960_machine_dt_match);
#endif
static struct platform_driver mt2701_wm8960_machine = {
.driver = {
.name = "mt2701-wm8960",
#ifdef CONFIG_OF
.of_match_table = mt2701_wm8960_machine_dt_match,
#endif
},
.probe = mt2701_wm8960_machine_probe,
};
module_platform_driver(mt2701_wm8960_machine);
/* Module information */
MODULE_DESCRIPTION("MT2701 WM8960 ALSA SoC machine driver");
MODULE_AUTHOR("Ryder Lee <[email protected]>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("mt2701 wm8960 soc card");
| linux-master | sound/soc/mediatek/mt2701/mt2701-wm8960.c |
// SPDX-License-Identifier: GPL-2.0
/*
* mt2701-cs42448.c -- MT2701 CS42448 ALSA SoC machine driver
*
* Copyright (c) 2016 MediaTek Inc.
* Author: Ir Lian <[email protected]>
* Garlic Tseng <[email protected]>
*/
#include <linux/module.h>
#include <sound/soc.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/pinctrl/consumer.h>
#include <linux/of_gpio.h>
#include "mt2701-afe-common.h"
struct mt2701_cs42448_private {
int i2s1_in_mux;
int i2s1_in_mux_gpio_sel_1;
int i2s1_in_mux_gpio_sel_2;
};
static const char * const i2sin_mux_switch_text[] = {
"ADC_SDOUT2",
"ADC_SDOUT3",
"I2S_IN_1",
"I2S_IN_2",
};
static const struct soc_enum i2sin_mux_enum =
SOC_ENUM_SINGLE_EXT(4, i2sin_mux_switch_text);
static int mt2701_cs42448_i2sin1_mux_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
struct mt2701_cs42448_private *priv = snd_soc_card_get_drvdata(card);
ucontrol->value.integer.value[0] = priv->i2s1_in_mux;
return 0;
}
static int mt2701_cs42448_i2sin1_mux_set(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
struct mt2701_cs42448_private *priv = snd_soc_card_get_drvdata(card);
if (ucontrol->value.integer.value[0] == priv->i2s1_in_mux)
return 0;
switch (ucontrol->value.integer.value[0]) {
case 0:
gpio_set_value(priv->i2s1_in_mux_gpio_sel_1, 0);
gpio_set_value(priv->i2s1_in_mux_gpio_sel_2, 0);
break;
case 1:
gpio_set_value(priv->i2s1_in_mux_gpio_sel_1, 1);
gpio_set_value(priv->i2s1_in_mux_gpio_sel_2, 0);
break;
case 2:
gpio_set_value(priv->i2s1_in_mux_gpio_sel_1, 0);
gpio_set_value(priv->i2s1_in_mux_gpio_sel_2, 1);
break;
case 3:
gpio_set_value(priv->i2s1_in_mux_gpio_sel_1, 1);
gpio_set_value(priv->i2s1_in_mux_gpio_sel_2, 1);
break;
default:
dev_warn(card->dev, "%s invalid setting\n", __func__);
}
priv->i2s1_in_mux = ucontrol->value.integer.value[0];
return 0;
}
static const struct snd_soc_dapm_widget
mt2701_cs42448_asoc_card_dapm_widgets[] = {
SND_SOC_DAPM_LINE("Line Out Jack", NULL),
SND_SOC_DAPM_MIC("AMIC", NULL),
SND_SOC_DAPM_LINE("Tuner In", NULL),
SND_SOC_DAPM_LINE("Satellite Tuner In", NULL),
SND_SOC_DAPM_LINE("AUX In", NULL),
};
static const struct snd_kcontrol_new mt2701_cs42448_controls[] = {
SOC_DAPM_PIN_SWITCH("Line Out Jack"),
SOC_DAPM_PIN_SWITCH("AMIC"),
SOC_DAPM_PIN_SWITCH("Tuner In"),
SOC_DAPM_PIN_SWITCH("Satellite Tuner In"),
SOC_DAPM_PIN_SWITCH("AUX In"),
SOC_ENUM_EXT("I2SIN1_MUX_Switch", i2sin_mux_enum,
mt2701_cs42448_i2sin1_mux_get,
mt2701_cs42448_i2sin1_mux_set),
};
static const unsigned int mt2701_cs42448_sampling_rates[] = {48000};
static const struct snd_pcm_hw_constraint_list mt2701_cs42448_constraints_rates = {
.count = ARRAY_SIZE(mt2701_cs42448_sampling_rates),
.list = mt2701_cs42448_sampling_rates,
.mask = 0,
};
static int mt2701_cs42448_fe_ops_startup(struct snd_pcm_substream *substream)
{
int err;
err = snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
&mt2701_cs42448_constraints_rates);
if (err < 0) {
dev_err(substream->pcm->card->dev,
"%s snd_pcm_hw_constraint_list failed: 0x%x\n",
__func__, err);
return err;
}
return 0;
}
static const struct snd_soc_ops mt2701_cs42448_48k_fe_ops = {
.startup = mt2701_cs42448_fe_ops_startup,
};
static int mt2701_cs42448_be_ops_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
unsigned int mclk_rate;
unsigned int rate = params_rate(params);
unsigned int div_mclk_over_bck = rate > 192000 ? 2 : 4;
unsigned int div_bck_over_lrck = 64;
mclk_rate = rate * div_bck_over_lrck * div_mclk_over_bck;
/* mt2701 mclk */
snd_soc_dai_set_sysclk(cpu_dai, 0, mclk_rate, SND_SOC_CLOCK_OUT);
/* codec mclk */
snd_soc_dai_set_sysclk(codec_dai, 0, mclk_rate, SND_SOC_CLOCK_IN);
return 0;
}
static const struct snd_soc_ops mt2701_cs42448_be_ops = {
.hw_params = mt2701_cs42448_be_ops_hw_params
};
enum {
DAI_LINK_FE_MULTI_CH_OUT,
DAI_LINK_FE_PCM0_IN,
DAI_LINK_FE_PCM1_IN,
DAI_LINK_FE_BT_OUT,
DAI_LINK_FE_BT_IN,
DAI_LINK_BE_I2S0,
DAI_LINK_BE_I2S1,
DAI_LINK_BE_I2S2,
DAI_LINK_BE_I2S3,
DAI_LINK_BE_MRG_BT,
};
SND_SOC_DAILINK_DEFS(fe_multi_ch_out,
DAILINK_COMP_ARRAY(COMP_CPU("PCM_multi")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(fe_pcm0_in,
DAILINK_COMP_ARRAY(COMP_CPU("PCM0")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(fe_pcm1_in,
DAILINK_COMP_ARRAY(COMP_CPU("PCM1")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(fe_bt_out,
DAILINK_COMP_ARRAY(COMP_CPU("PCM_BT_DL")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(fe_bt_in,
DAILINK_COMP_ARRAY(COMP_CPU("PCM_BT_UL")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(be_i2s0,
DAILINK_COMP_ARRAY(COMP_CPU("I2S0")),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "cs42448")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(be_i2s1,
DAILINK_COMP_ARRAY(COMP_CPU("I2S1")),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "cs42448")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(be_i2s2,
DAILINK_COMP_ARRAY(COMP_CPU("I2S2")),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "cs42448")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(be_i2s3,
DAILINK_COMP_ARRAY(COMP_CPU("I2S3")),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "cs42448")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(be_mrg_bt,
DAILINK_COMP_ARRAY(COMP_CPU("MRG BT")),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "bt-sco-pcm-wb")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
static struct snd_soc_dai_link mt2701_cs42448_dai_links[] = {
/* FE */
[DAI_LINK_FE_MULTI_CH_OUT] = {
.name = "mt2701-cs42448-multi-ch-out",
.stream_name = "mt2701-cs42448-multi-ch-out",
.trigger = {SND_SOC_DPCM_TRIGGER_POST,
SND_SOC_DPCM_TRIGGER_POST},
.ops = &mt2701_cs42448_48k_fe_ops,
.dynamic = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(fe_multi_ch_out),
},
[DAI_LINK_FE_PCM0_IN] = {
.name = "mt2701-cs42448-pcm0",
.stream_name = "mt2701-cs42448-pcm0-data-UL",
.trigger = {SND_SOC_DPCM_TRIGGER_POST,
SND_SOC_DPCM_TRIGGER_POST},
.ops = &mt2701_cs42448_48k_fe_ops,
.dynamic = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(fe_pcm0_in),
},
[DAI_LINK_FE_PCM1_IN] = {
.name = "mt2701-cs42448-pcm1-data-UL",
.stream_name = "mt2701-cs42448-pcm1-data-UL",
.trigger = {SND_SOC_DPCM_TRIGGER_POST,
SND_SOC_DPCM_TRIGGER_POST},
.ops = &mt2701_cs42448_48k_fe_ops,
.dynamic = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(fe_pcm1_in),
},
[DAI_LINK_FE_BT_OUT] = {
.name = "mt2701-cs42448-pcm-BT-out",
.stream_name = "mt2701-cs42448-pcm-BT",
.trigger = {SND_SOC_DPCM_TRIGGER_POST,
SND_SOC_DPCM_TRIGGER_POST},
.dynamic = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(fe_bt_out),
},
[DAI_LINK_FE_BT_IN] = {
.name = "mt2701-cs42448-pcm-BT-in",
.stream_name = "mt2701-cs42448-pcm-BT",
.trigger = {SND_SOC_DPCM_TRIGGER_POST,
SND_SOC_DPCM_TRIGGER_POST},
.dynamic = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(fe_bt_in),
},
/* BE */
[DAI_LINK_BE_I2S0] = {
.name = "mt2701-cs42448-I2S0",
.no_pcm = 1,
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS
| SND_SOC_DAIFMT_GATED,
.ops = &mt2701_cs42448_be_ops,
.dpcm_playback = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(be_i2s0),
},
[DAI_LINK_BE_I2S1] = {
.name = "mt2701-cs42448-I2S1",
.no_pcm = 1,
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS
| SND_SOC_DAIFMT_GATED,
.ops = &mt2701_cs42448_be_ops,
.dpcm_playback = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(be_i2s1),
},
[DAI_LINK_BE_I2S2] = {
.name = "mt2701-cs42448-I2S2",
.no_pcm = 1,
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS
| SND_SOC_DAIFMT_GATED,
.ops = &mt2701_cs42448_be_ops,
.dpcm_playback = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(be_i2s2),
},
[DAI_LINK_BE_I2S3] = {
.name = "mt2701-cs42448-I2S3",
.no_pcm = 1,
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS
| SND_SOC_DAIFMT_GATED,
.ops = &mt2701_cs42448_be_ops,
.dpcm_playback = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(be_i2s3),
},
[DAI_LINK_BE_MRG_BT] = {
.name = "mt2701-cs42448-MRG-BT",
.no_pcm = 1,
.dpcm_playback = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(be_mrg_bt),
},
};
static struct snd_soc_card mt2701_cs42448_soc_card = {
.name = "mt2701-cs42448",
.owner = THIS_MODULE,
.dai_link = mt2701_cs42448_dai_links,
.num_links = ARRAY_SIZE(mt2701_cs42448_dai_links),
.controls = mt2701_cs42448_controls,
.num_controls = ARRAY_SIZE(mt2701_cs42448_controls),
.dapm_widgets = mt2701_cs42448_asoc_card_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(mt2701_cs42448_asoc_card_dapm_widgets),
};
static int mt2701_cs42448_machine_probe(struct platform_device *pdev)
{
struct snd_soc_card *card = &mt2701_cs42448_soc_card;
int ret;
int i;
struct device_node *platform_node, *codec_node, *codec_node_bt_mrg;
struct mt2701_cs42448_private *priv =
devm_kzalloc(&pdev->dev, sizeof(struct mt2701_cs42448_private),
GFP_KERNEL);
struct device *dev = &pdev->dev;
struct snd_soc_dai_link *dai_link;
if (!priv)
return -ENOMEM;
platform_node = of_parse_phandle(pdev->dev.of_node,
"mediatek,platform", 0);
if (!platform_node) {
dev_err(&pdev->dev, "Property 'platform' missing or invalid\n");
return -EINVAL;
}
for_each_card_prelinks(card, i, dai_link) {
if (dai_link->platforms->name)
continue;
dai_link->platforms->of_node = platform_node;
}
card->dev = dev;
codec_node = of_parse_phandle(pdev->dev.of_node,
"mediatek,audio-codec", 0);
if (!codec_node) {
dev_err(&pdev->dev,
"Property 'audio-codec' missing or invalid\n");
return -EINVAL;
}
for_each_card_prelinks(card, i, dai_link) {
if (dai_link->codecs->name)
continue;
dai_link->codecs->of_node = codec_node;
}
codec_node_bt_mrg = of_parse_phandle(pdev->dev.of_node,
"mediatek,audio-codec-bt-mrg", 0);
if (!codec_node_bt_mrg) {
dev_err(&pdev->dev,
"Property 'audio-codec-bt-mrg' missing or invalid\n");
return -EINVAL;
}
mt2701_cs42448_dai_links[DAI_LINK_BE_MRG_BT].codecs->of_node
= codec_node_bt_mrg;
ret = snd_soc_of_parse_audio_routing(card, "audio-routing");
if (ret) {
dev_err(&pdev->dev, "failed to parse audio-routing: %d\n", ret);
return ret;
}
priv->i2s1_in_mux_gpio_sel_1 =
of_get_named_gpio(dev->of_node, "i2s1-in-sel-gpio1", 0);
if (gpio_is_valid(priv->i2s1_in_mux_gpio_sel_1)) {
ret = devm_gpio_request(dev, priv->i2s1_in_mux_gpio_sel_1,
"i2s1_in_mux_gpio_sel_1");
if (ret)
dev_warn(&pdev->dev, "%s devm_gpio_request fail %d\n",
__func__, ret);
gpio_direction_output(priv->i2s1_in_mux_gpio_sel_1, 0);
}
priv->i2s1_in_mux_gpio_sel_2 =
of_get_named_gpio(dev->of_node, "i2s1-in-sel-gpio2", 0);
if (gpio_is_valid(priv->i2s1_in_mux_gpio_sel_2)) {
ret = devm_gpio_request(dev, priv->i2s1_in_mux_gpio_sel_2,
"i2s1_in_mux_gpio_sel_2");
if (ret)
dev_warn(&pdev->dev, "%s devm_gpio_request fail2 %d\n",
__func__, ret);
gpio_direction_output(priv->i2s1_in_mux_gpio_sel_2, 0);
}
snd_soc_card_set_drvdata(card, priv);
ret = devm_snd_soc_register_card(&pdev->dev, card);
if (ret)
dev_err(&pdev->dev, "%s snd_soc_register_card fail %d\n",
__func__, ret);
return ret;
}
#ifdef CONFIG_OF
static const struct of_device_id mt2701_cs42448_machine_dt_match[] = {
{.compatible = "mediatek,mt2701-cs42448-machine",},
{}
};
MODULE_DEVICE_TABLE(of, mt2701_cs42448_machine_dt_match);
#endif
static struct platform_driver mt2701_cs42448_machine = {
.driver = {
.name = "mt2701-cs42448",
#ifdef CONFIG_OF
.of_match_table = mt2701_cs42448_machine_dt_match,
#endif
},
.probe = mt2701_cs42448_machine_probe,
};
module_platform_driver(mt2701_cs42448_machine);
/* Module information */
MODULE_DESCRIPTION("MT2701 CS42448 ALSA SoC machine driver");
MODULE_AUTHOR("Ir Lian <[email protected]>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("mt2701 cs42448 soc card");
| linux-master | sound/soc/mediatek/mt2701/mt2701-cs42448.c |
// SPDX-License-Identifier: GPL-2.0
/*
* mt2701-afe-clock-ctrl.c -- Mediatek 2701 afe clock ctrl
*
* Copyright (c) 2016 MediaTek Inc.
* Author: Garlic Tseng <[email protected]>
* Ryder Lee <[email protected]>
*/
#include "mt2701-afe-common.h"
#include "mt2701-afe-clock-ctrl.h"
static const char *const base_clks[] = {
[MT2701_INFRA_SYS_AUDIO] = "infra_sys_audio_clk",
[MT2701_TOP_AUD_MCLK_SRC0] = "top_audio_mux1_sel",
[MT2701_TOP_AUD_MCLK_SRC1] = "top_audio_mux2_sel",
[MT2701_TOP_AUD_A1SYS] = "top_audio_a1sys_hp",
[MT2701_TOP_AUD_A2SYS] = "top_audio_a2sys_hp",
[MT2701_AUDSYS_AFE] = "audio_afe_pd",
[MT2701_AUDSYS_AFE_CONN] = "audio_afe_conn_pd",
[MT2701_AUDSYS_A1SYS] = "audio_a1sys_pd",
[MT2701_AUDSYS_A2SYS] = "audio_a2sys_pd",
};
int mt2701_init_clock(struct mtk_base_afe *afe)
{
struct mt2701_afe_private *afe_priv = afe->platform_priv;
int i;
for (i = 0; i < MT2701_BASE_CLK_NUM; i++) {
afe_priv->base_ck[i] = devm_clk_get(afe->dev, base_clks[i]);
if (IS_ERR(afe_priv->base_ck[i])) {
dev_err(afe->dev, "failed to get %s\n", base_clks[i]);
return PTR_ERR(afe_priv->base_ck[i]);
}
}
/* Get I2S related clocks */
for (i = 0; i < afe_priv->soc->i2s_num; i++) {
struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[i];
struct clk *i2s_ck;
char name[13];
snprintf(name, sizeof(name), "i2s%d_src_sel", i);
i2s_path->sel_ck = devm_clk_get(afe->dev, name);
if (IS_ERR(i2s_path->sel_ck)) {
dev_err(afe->dev, "failed to get %s\n", name);
return PTR_ERR(i2s_path->sel_ck);
}
snprintf(name, sizeof(name), "i2s%d_src_div", i);
i2s_path->div_ck = devm_clk_get(afe->dev, name);
if (IS_ERR(i2s_path->div_ck)) {
dev_err(afe->dev, "failed to get %s\n", name);
return PTR_ERR(i2s_path->div_ck);
}
snprintf(name, sizeof(name), "i2s%d_mclk_en", i);
i2s_path->mclk_ck = devm_clk_get(afe->dev, name);
if (IS_ERR(i2s_path->mclk_ck)) {
dev_err(afe->dev, "failed to get %s\n", name);
return PTR_ERR(i2s_path->mclk_ck);
}
snprintf(name, sizeof(name), "i2so%d_hop_ck", i);
i2s_ck = devm_clk_get(afe->dev, name);
if (IS_ERR(i2s_ck)) {
dev_err(afe->dev, "failed to get %s\n", name);
return PTR_ERR(i2s_ck);
}
i2s_path->hop_ck[SNDRV_PCM_STREAM_PLAYBACK] = i2s_ck;
snprintf(name, sizeof(name), "i2si%d_hop_ck", i);
i2s_ck = devm_clk_get(afe->dev, name);
if (IS_ERR(i2s_ck)) {
dev_err(afe->dev, "failed to get %s\n", name);
return PTR_ERR(i2s_ck);
}
i2s_path->hop_ck[SNDRV_PCM_STREAM_CAPTURE] = i2s_ck;
snprintf(name, sizeof(name), "asrc%d_out_ck", i);
i2s_path->asrco_ck = devm_clk_get(afe->dev, name);
if (IS_ERR(i2s_path->asrco_ck)) {
dev_err(afe->dev, "failed to get %s\n", name);
return PTR_ERR(i2s_path->asrco_ck);
}
}
/* Some platforms may support BT path */
afe_priv->mrgif_ck = devm_clk_get(afe->dev, "audio_mrgif_pd");
if (IS_ERR(afe_priv->mrgif_ck)) {
if (PTR_ERR(afe_priv->mrgif_ck) == -EPROBE_DEFER)
return -EPROBE_DEFER;
afe_priv->mrgif_ck = NULL;
}
return 0;
}
int mt2701_afe_enable_i2s(struct mtk_base_afe *afe,
struct mt2701_i2s_path *i2s_path,
int dir)
{
int ret;
ret = clk_prepare_enable(i2s_path->asrco_ck);
if (ret) {
dev_err(afe->dev, "failed to enable ASRC clock %d\n", ret);
return ret;
}
ret = clk_prepare_enable(i2s_path->hop_ck[dir]);
if (ret) {
dev_err(afe->dev, "failed to enable I2S clock %d\n", ret);
goto err_hop_ck;
}
return 0;
err_hop_ck:
clk_disable_unprepare(i2s_path->asrco_ck);
return ret;
}
void mt2701_afe_disable_i2s(struct mtk_base_afe *afe,
struct mt2701_i2s_path *i2s_path,
int dir)
{
clk_disable_unprepare(i2s_path->hop_ck[dir]);
clk_disable_unprepare(i2s_path->asrco_ck);
}
int mt2701_afe_enable_mclk(struct mtk_base_afe *afe, int id)
{
struct mt2701_afe_private *afe_priv = afe->platform_priv;
struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[id];
return clk_prepare_enable(i2s_path->mclk_ck);
}
void mt2701_afe_disable_mclk(struct mtk_base_afe *afe, int id)
{
struct mt2701_afe_private *afe_priv = afe->platform_priv;
struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[id];
clk_disable_unprepare(i2s_path->mclk_ck);
}
int mt2701_enable_btmrg_clk(struct mtk_base_afe *afe)
{
struct mt2701_afe_private *afe_priv = afe->platform_priv;
return clk_prepare_enable(afe_priv->mrgif_ck);
}
void mt2701_disable_btmrg_clk(struct mtk_base_afe *afe)
{
struct mt2701_afe_private *afe_priv = afe->platform_priv;
clk_disable_unprepare(afe_priv->mrgif_ck);
}
static int mt2701_afe_enable_audsys(struct mtk_base_afe *afe)
{
struct mt2701_afe_private *afe_priv = afe->platform_priv;
int ret;
/* Enable infra clock gate */
ret = clk_prepare_enable(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]);
if (ret)
return ret;
/* Enable top a1sys clock gate */
ret = clk_prepare_enable(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]);
if (ret)
goto err_a1sys;
/* Enable top a2sys clock gate */
ret = clk_prepare_enable(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]);
if (ret)
goto err_a2sys;
/* Internal clock gates */
ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
if (ret)
goto err_afe;
ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
if (ret)
goto err_audio_a1sys;
ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_A2SYS]);
if (ret)
goto err_audio_a2sys;
ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_AFE_CONN]);
if (ret)
goto err_afe_conn;
return 0;
err_afe_conn:
clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A2SYS]);
err_audio_a2sys:
clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
err_audio_a1sys:
clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
err_afe:
clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]);
err_a2sys:
clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]);
err_a1sys:
clk_disable_unprepare(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]);
return ret;
}
static void mt2701_afe_disable_audsys(struct mtk_base_afe *afe)
{
struct mt2701_afe_private *afe_priv = afe->platform_priv;
clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE_CONN]);
clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A2SYS]);
clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]);
clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]);
clk_disable_unprepare(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]);
}
int mt2701_afe_enable_clock(struct mtk_base_afe *afe)
{
int ret;
/* Enable audio system */
ret = mt2701_afe_enable_audsys(afe);
if (ret) {
dev_err(afe->dev, "failed to enable audio system %d\n", ret);
return ret;
}
regmap_update_bits(afe->regmap, ASYS_TOP_CON,
ASYS_TOP_CON_ASYS_TIMING_ON,
ASYS_TOP_CON_ASYS_TIMING_ON);
regmap_update_bits(afe->regmap, AFE_DAC_CON0,
AFE_DAC_CON0_AFE_ON,
AFE_DAC_CON0_AFE_ON);
/* Configure ASRC */
regmap_write(afe->regmap, PWR1_ASM_CON1, PWR1_ASM_CON1_INIT_VAL);
regmap_write(afe->regmap, PWR2_ASM_CON1, PWR2_ASM_CON1_INIT_VAL);
return 0;
}
int mt2701_afe_disable_clock(struct mtk_base_afe *afe)
{
regmap_update_bits(afe->regmap, ASYS_TOP_CON,
ASYS_TOP_CON_ASYS_TIMING_ON, 0);
regmap_update_bits(afe->regmap, AFE_DAC_CON0,
AFE_DAC_CON0_AFE_ON, 0);
mt2701_afe_disable_audsys(afe);
return 0;
}
int mt2701_mclk_configuration(struct mtk_base_afe *afe, int id)
{
struct mt2701_afe_private *priv = afe->platform_priv;
struct mt2701_i2s_path *i2s_path = &priv->i2s_path[id];
int ret = -EINVAL;
/* Set mclk source */
if (!(MT2701_PLL_DOMAIN_0_RATE % i2s_path->mclk_rate))
ret = clk_set_parent(i2s_path->sel_ck,
priv->base_ck[MT2701_TOP_AUD_MCLK_SRC0]);
else if (!(MT2701_PLL_DOMAIN_1_RATE % i2s_path->mclk_rate))
ret = clk_set_parent(i2s_path->sel_ck,
priv->base_ck[MT2701_TOP_AUD_MCLK_SRC1]);
if (ret) {
dev_err(afe->dev, "failed to set mclk source\n");
return ret;
}
/* Set mclk divider */
ret = clk_set_rate(i2s_path->div_ck, i2s_path->mclk_rate);
if (ret) {
dev_err(afe->dev, "failed to set mclk divider %d\n", ret);
return ret;
}
return 0;
}
| linux-master | sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Mediatek ALSA SoC AFE platform driver for 2701
*
* Copyright (c) 2016 MediaTek Inc.
* Author: Garlic Tseng <[email protected]>
* Ir Lian <[email protected]>
* Ryder Lee <[email protected]>
*/
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/pm_runtime.h>
#include "mt2701-afe-common.h"
#include "mt2701-afe-clock-ctrl.h"
#include "../common/mtk-afe-platform-driver.h"
#include "../common/mtk-afe-fe-dai.h"
static const struct snd_pcm_hardware mt2701_afe_hardware = {
.info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED
| SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE
| SNDRV_PCM_FMTBIT_S32_LE,
.period_bytes_min = 1024,
.period_bytes_max = 1024 * 256,
.periods_min = 4,
.periods_max = 1024,
.buffer_bytes_max = 1024 * 1024,
.fifo_size = 0,
};
struct mt2701_afe_rate {
unsigned int rate;
unsigned int regvalue;
};
static const struct mt2701_afe_rate mt2701_afe_i2s_rates[] = {
{ .rate = 8000, .regvalue = 0 },
{ .rate = 12000, .regvalue = 1 },
{ .rate = 16000, .regvalue = 2 },
{ .rate = 24000, .regvalue = 3 },
{ .rate = 32000, .regvalue = 4 },
{ .rate = 48000, .regvalue = 5 },
{ .rate = 96000, .regvalue = 6 },
{ .rate = 192000, .regvalue = 7 },
{ .rate = 384000, .regvalue = 8 },
{ .rate = 7350, .regvalue = 16 },
{ .rate = 11025, .regvalue = 17 },
{ .rate = 14700, .regvalue = 18 },
{ .rate = 22050, .regvalue = 19 },
{ .rate = 29400, .regvalue = 20 },
{ .rate = 44100, .regvalue = 21 },
{ .rate = 88200, .regvalue = 22 },
{ .rate = 176400, .regvalue = 23 },
{ .rate = 352800, .regvalue = 24 },
};
static const unsigned int mt2701_afe_backup_list[] = {
AUDIO_TOP_CON0,
AUDIO_TOP_CON4,
AUDIO_TOP_CON5,
ASYS_TOP_CON,
AFE_CONN0,
AFE_CONN1,
AFE_CONN2,
AFE_CONN3,
AFE_CONN15,
AFE_CONN16,
AFE_CONN17,
AFE_CONN18,
AFE_CONN19,
AFE_CONN20,
AFE_CONN21,
AFE_CONN22,
AFE_DAC_CON0,
AFE_MEMIF_PBUF_SIZE,
};
static int mt2701_dai_num_to_i2s(struct mtk_base_afe *afe, int num)
{
struct mt2701_afe_private *afe_priv = afe->platform_priv;
int val = num - MT2701_IO_I2S;
if (val < 0 || val >= afe_priv->soc->i2s_num) {
dev_err(afe->dev, "%s, num not available, num %d, val %d\n",
__func__, num, val);
return -EINVAL;
}
return val;
}
static int mt2701_afe_i2s_fs(unsigned int sample_rate)
{
int i;
for (i = 0; i < ARRAY_SIZE(mt2701_afe_i2s_rates); i++)
if (mt2701_afe_i2s_rates[i].rate == sample_rate)
return mt2701_afe_i2s_rates[i].regvalue;
return -EINVAL;
}
static int mt2701_afe_i2s_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt2701_afe_private *afe_priv = afe->platform_priv;
int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
bool mode = afe_priv->soc->has_one_heart_mode;
if (i2s_num < 0)
return i2s_num;
return mt2701_afe_enable_mclk(afe, mode ? 1 : i2s_num);
}
static int mt2701_afe_i2s_path_disable(struct mtk_base_afe *afe,
struct mt2701_i2s_path *i2s_path,
int stream_dir)
{
const struct mt2701_i2s_data *i2s_data = i2s_path->i2s_data[stream_dir];
if (--i2s_path->on[stream_dir] < 0)
i2s_path->on[stream_dir] = 0;
if (i2s_path->on[stream_dir])
return 0;
/* disable i2s */
regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg,
ASYS_I2S_CON_I2S_EN, 0);
mt2701_afe_disable_i2s(afe, i2s_path, stream_dir);
return 0;
}
static void mt2701_afe_i2s_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt2701_afe_private *afe_priv = afe->platform_priv;
int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
struct mt2701_i2s_path *i2s_path;
bool mode = afe_priv->soc->has_one_heart_mode;
if (i2s_num < 0)
return;
i2s_path = &afe_priv->i2s_path[i2s_num];
if (i2s_path->occupied[substream->stream])
i2s_path->occupied[substream->stream] = 0;
else
goto exit;
mt2701_afe_i2s_path_disable(afe, i2s_path, substream->stream);
/* need to disable i2s-out path when disable i2s-in */
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
mt2701_afe_i2s_path_disable(afe, i2s_path, !substream->stream);
exit:
/* disable mclk */
mt2701_afe_disable_mclk(afe, mode ? 1 : i2s_num);
}
static int mt2701_i2s_path_enable(struct mtk_base_afe *afe,
struct mt2701_i2s_path *i2s_path,
int stream_dir, int rate)
{
const struct mt2701_i2s_data *i2s_data = i2s_path->i2s_data[stream_dir];
struct mt2701_afe_private *afe_priv = afe->platform_priv;
int reg, fs, w_len = 1; /* now we support bck 64bits only */
unsigned int mask, val;
/* no need to enable if already done */
if (++i2s_path->on[stream_dir] != 1)
return 0;
fs = mt2701_afe_i2s_fs(rate);
mask = ASYS_I2S_CON_FS |
ASYS_I2S_CON_I2S_COUPLE_MODE | /* 0 */
ASYS_I2S_CON_I2S_MODE |
ASYS_I2S_CON_WIDE_MODE;
val = ASYS_I2S_CON_FS_SET(fs) |
ASYS_I2S_CON_I2S_MODE |
ASYS_I2S_CON_WIDE_MODE_SET(w_len);
if (stream_dir == SNDRV_PCM_STREAM_CAPTURE) {
mask |= ASYS_I2S_IN_PHASE_FIX;
val |= ASYS_I2S_IN_PHASE_FIX;
reg = ASMI_TIMING_CON1;
} else {
if (afe_priv->soc->has_one_heart_mode) {
mask |= ASYS_I2S_CON_ONE_HEART_MODE;
val |= ASYS_I2S_CON_ONE_HEART_MODE;
}
reg = ASMO_TIMING_CON1;
}
regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg, mask, val);
regmap_update_bits(afe->regmap, reg,
i2s_data->i2s_asrc_fs_mask
<< i2s_data->i2s_asrc_fs_shift,
fs << i2s_data->i2s_asrc_fs_shift);
/* enable i2s */
mt2701_afe_enable_i2s(afe, i2s_path, stream_dir);
/* reset i2s hw status before enable */
regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg,
ASYS_I2S_CON_RESET, ASYS_I2S_CON_RESET);
udelay(1);
regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg,
ASYS_I2S_CON_RESET, 0);
udelay(1);
regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg,
ASYS_I2S_CON_I2S_EN, ASYS_I2S_CON_I2S_EN);
return 0;
}
static int mt2701_afe_i2s_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt2701_afe_private *afe_priv = afe->platform_priv;
int ret, i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
struct mt2701_i2s_path *i2s_path;
bool mode = afe_priv->soc->has_one_heart_mode;
if (i2s_num < 0)
return i2s_num;
i2s_path = &afe_priv->i2s_path[i2s_num];
if (i2s_path->occupied[substream->stream])
return -EBUSY;
ret = mt2701_mclk_configuration(afe, mode ? 1 : i2s_num);
if (ret)
return ret;
i2s_path->occupied[substream->stream] = 1;
/* need to enable i2s-out path when enable i2s-in */
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
mt2701_i2s_path_enable(afe, i2s_path, !substream->stream,
substream->runtime->rate);
mt2701_i2s_path_enable(afe, i2s_path, substream->stream,
substream->runtime->rate);
return 0;
}
static int mt2701_afe_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
unsigned int freq, int dir)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt2701_afe_private *afe_priv = afe->platform_priv;
int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
bool mode = afe_priv->soc->has_one_heart_mode;
if (i2s_num < 0)
return i2s_num;
/* mclk */
if (dir == SND_SOC_CLOCK_IN) {
dev_warn(dai->dev, "The SoCs doesn't support mclk input\n");
return -EINVAL;
}
afe_priv->i2s_path[mode ? 1 : i2s_num].mclk_rate = freq;
return 0;
}
static int mt2701_btmrg_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt2701_afe_private *afe_priv = afe->platform_priv;
int ret;
ret = mt2701_enable_btmrg_clk(afe);
if (ret)
return ret;
afe_priv->mrg_enable[substream->stream] = 1;
return 0;
}
static int mt2701_btmrg_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
int stream_fs;
u32 val, msk;
stream_fs = params_rate(params);
if (stream_fs != 8000 && stream_fs != 16000) {
dev_err(afe->dev, "unsupported rate %d\n", stream_fs);
return -EINVAL;
}
regmap_update_bits(afe->regmap, AFE_MRGIF_CON,
AFE_MRGIF_CON_I2S_MODE_MASK,
AFE_MRGIF_CON_I2S_MODE_32K);
val = AFE_DAIBT_CON0_BT_FUNC_EN | AFE_DAIBT_CON0_BT_FUNC_RDY
| AFE_DAIBT_CON0_MRG_USE;
msk = val;
if (stream_fs == 16000)
val |= AFE_DAIBT_CON0_BT_WIDE_MODE_EN;
msk |= AFE_DAIBT_CON0_BT_WIDE_MODE_EN;
regmap_update_bits(afe->regmap, AFE_DAIBT_CON0, msk, val);
regmap_update_bits(afe->regmap, AFE_DAIBT_CON0,
AFE_DAIBT_CON0_DAIBT_EN,
AFE_DAIBT_CON0_DAIBT_EN);
regmap_update_bits(afe->regmap, AFE_MRGIF_CON,
AFE_MRGIF_CON_MRG_I2S_EN,
AFE_MRGIF_CON_MRG_I2S_EN);
regmap_update_bits(afe->regmap, AFE_MRGIF_CON,
AFE_MRGIF_CON_MRG_EN,
AFE_MRGIF_CON_MRG_EN);
return 0;
}
static void mt2701_btmrg_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt2701_afe_private *afe_priv = afe->platform_priv;
/* if the other direction stream is not occupied */
if (!afe_priv->mrg_enable[!substream->stream]) {
regmap_update_bits(afe->regmap, AFE_DAIBT_CON0,
AFE_DAIBT_CON0_DAIBT_EN, 0);
regmap_update_bits(afe->regmap, AFE_MRGIF_CON,
AFE_MRGIF_CON_MRG_EN, 0);
regmap_update_bits(afe->regmap, AFE_MRGIF_CON,
AFE_MRGIF_CON_MRG_I2S_EN, 0);
mt2701_disable_btmrg_clk(afe);
}
afe_priv->mrg_enable[substream->stream] = 0;
}
static int mt2701_simple_fe_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mtk_base_afe_memif *memif_tmp;
int stream_dir = substream->stream;
/* can't run single DL & DLM at the same time */
if (stream_dir == SNDRV_PCM_STREAM_PLAYBACK) {
memif_tmp = &afe->memif[MT2701_MEMIF_DLM];
if (memif_tmp->substream) {
dev_warn(afe->dev, "memif is not available");
return -EBUSY;
}
}
return mtk_afe_fe_startup(substream, dai);
}
static int mt2701_simple_fe_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
int stream_dir = substream->stream;
/* single DL use PAIR_INTERLEAVE */
if (stream_dir == SNDRV_PCM_STREAM_PLAYBACK)
regmap_update_bits(afe->regmap,
AFE_MEMIF_PBUF_SIZE,
AFE_MEMIF_PBUF_SIZE_DLM_MASK,
AFE_MEMIF_PBUF_SIZE_PAIR_INTERLEAVE);
return mtk_afe_fe_hw_params(substream, params, dai);
}
static int mt2701_dlm_fe_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mtk_base_afe_memif *memif_tmp;
const struct mtk_base_memif_data *memif_data;
int i;
for (i = MT2701_MEMIF_DL1; i < MT2701_MEMIF_DL_SINGLE_NUM; ++i) {
memif_tmp = &afe->memif[i];
if (memif_tmp->substream)
return -EBUSY;
}
/* enable agent for all signal DL (due to hw design) */
for (i = MT2701_MEMIF_DL1; i < MT2701_MEMIF_DL_SINGLE_NUM; ++i) {
memif_data = afe->memif[i].data;
regmap_update_bits(afe->regmap,
memif_data->agent_disable_reg,
1 << memif_data->agent_disable_shift,
0 << memif_data->agent_disable_shift);
}
return mtk_afe_fe_startup(substream, dai);
}
static void mt2701_dlm_fe_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
const struct mtk_base_memif_data *memif_data;
int i;
for (i = MT2701_MEMIF_DL1; i < MT2701_MEMIF_DL_SINGLE_NUM; ++i) {
memif_data = afe->memif[i].data;
regmap_update_bits(afe->regmap,
memif_data->agent_disable_reg,
1 << memif_data->agent_disable_shift,
1 << memif_data->agent_disable_shift);
}
return mtk_afe_fe_shutdown(substream, dai);
}
static int mt2701_dlm_fe_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
int channels = params_channels(params);
regmap_update_bits(afe->regmap,
AFE_MEMIF_PBUF_SIZE,
AFE_MEMIF_PBUF_SIZE_DLM_MASK,
AFE_MEMIF_PBUF_SIZE_FULL_INTERLEAVE);
regmap_update_bits(afe->regmap,
AFE_MEMIF_PBUF_SIZE,
AFE_MEMIF_PBUF_SIZE_DLM_BYTE_MASK,
AFE_MEMIF_PBUF_SIZE_DLM_32BYTES);
regmap_update_bits(afe->regmap,
AFE_MEMIF_PBUF_SIZE,
AFE_MEMIF_PBUF_SIZE_DLM_CH_MASK,
AFE_MEMIF_PBUF_SIZE_DLM_CH(channels));
return mtk_afe_fe_hw_params(substream, params, dai);
}
static int mt2701_dlm_fe_trigger(struct snd_pcm_substream *substream,
int cmd, struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mtk_base_afe_memif *memif_tmp = &afe->memif[MT2701_MEMIF_DL1];
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
regmap_update_bits(afe->regmap, memif_tmp->data->enable_reg,
1 << memif_tmp->data->enable_shift,
1 << memif_tmp->data->enable_shift);
mtk_afe_fe_trigger(substream, cmd, dai);
return 0;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
mtk_afe_fe_trigger(substream, cmd, dai);
regmap_update_bits(afe->regmap, memif_tmp->data->enable_reg,
1 << memif_tmp->data->enable_shift, 0);
return 0;
default:
return -EINVAL;
}
}
static int mt2701_memif_fs(struct snd_pcm_substream *substream,
unsigned int rate)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
int fs;
if (asoc_rtd_to_cpu(rtd, 0)->id != MT2701_MEMIF_ULBT)
fs = mt2701_afe_i2s_fs(rate);
else
fs = (rate == 16000 ? 1 : 0);
return fs;
}
static int mt2701_irq_fs(struct snd_pcm_substream *substream, unsigned int rate)
{
return mt2701_afe_i2s_fs(rate);
}
/* FE DAIs */
static const struct snd_soc_dai_ops mt2701_single_memif_dai_ops = {
.startup = mt2701_simple_fe_startup,
.shutdown = mtk_afe_fe_shutdown,
.hw_params = mt2701_simple_fe_hw_params,
.hw_free = mtk_afe_fe_hw_free,
.prepare = mtk_afe_fe_prepare,
.trigger = mtk_afe_fe_trigger,
};
static const struct snd_soc_dai_ops mt2701_dlm_memif_dai_ops = {
.startup = mt2701_dlm_fe_startup,
.shutdown = mt2701_dlm_fe_shutdown,
.hw_params = mt2701_dlm_fe_hw_params,
.hw_free = mtk_afe_fe_hw_free,
.prepare = mtk_afe_fe_prepare,
.trigger = mt2701_dlm_fe_trigger,
};
/* I2S BE DAIs */
static const struct snd_soc_dai_ops mt2701_afe_i2s_ops = {
.startup = mt2701_afe_i2s_startup,
.shutdown = mt2701_afe_i2s_shutdown,
.prepare = mt2701_afe_i2s_prepare,
.set_sysclk = mt2701_afe_i2s_set_sysclk,
};
/* MRG BE DAIs */
static const struct snd_soc_dai_ops mt2701_btmrg_ops = {
.startup = mt2701_btmrg_startup,
.shutdown = mt2701_btmrg_shutdown,
.hw_params = mt2701_btmrg_hw_params,
};
static struct snd_soc_dai_driver mt2701_afe_pcm_dais[] = {
/* FE DAIs: memory intefaces to CPU */
{
.name = "PCMO0",
.id = MT2701_MEMIF_DL1,
.playback = {
.stream_name = "DL1",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = (SNDRV_PCM_FMTBIT_S16_LE
| SNDRV_PCM_FMTBIT_S24_LE
| SNDRV_PCM_FMTBIT_S32_LE)
},
.ops = &mt2701_single_memif_dai_ops,
},
{
.name = "PCM_multi",
.id = MT2701_MEMIF_DLM,
.playback = {
.stream_name = "DLM",
.channels_min = 1,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = (SNDRV_PCM_FMTBIT_S16_LE
| SNDRV_PCM_FMTBIT_S24_LE
| SNDRV_PCM_FMTBIT_S32_LE)
},
.ops = &mt2701_dlm_memif_dai_ops,
},
{
.name = "PCM0",
.id = MT2701_MEMIF_UL1,
.capture = {
.stream_name = "UL1",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = (SNDRV_PCM_FMTBIT_S16_LE
| SNDRV_PCM_FMTBIT_S24_LE
| SNDRV_PCM_FMTBIT_S32_LE)
},
.ops = &mt2701_single_memif_dai_ops,
},
{
.name = "PCM1",
.id = MT2701_MEMIF_UL2,
.capture = {
.stream_name = "UL2",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = (SNDRV_PCM_FMTBIT_S16_LE
| SNDRV_PCM_FMTBIT_S24_LE
| SNDRV_PCM_FMTBIT_S32_LE)
},
.ops = &mt2701_single_memif_dai_ops,
},
{
.name = "PCM_BT_DL",
.id = MT2701_MEMIF_DLBT,
.playback = {
.stream_name = "DLBT",
.channels_min = 1,
.channels_max = 1,
.rates = (SNDRV_PCM_RATE_8000
| SNDRV_PCM_RATE_16000),
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.ops = &mt2701_single_memif_dai_ops,
},
{
.name = "PCM_BT_UL",
.id = MT2701_MEMIF_ULBT,
.capture = {
.stream_name = "ULBT",
.channels_min = 1,
.channels_max = 1,
.rates = (SNDRV_PCM_RATE_8000
| SNDRV_PCM_RATE_16000),
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.ops = &mt2701_single_memif_dai_ops,
},
/* BE DAIs */
{
.name = "I2S0",
.id = MT2701_IO_I2S,
.playback = {
.stream_name = "I2S0 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = (SNDRV_PCM_FMTBIT_S16_LE
| SNDRV_PCM_FMTBIT_S24_LE
| SNDRV_PCM_FMTBIT_S32_LE)
},
.capture = {
.stream_name = "I2S0 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = (SNDRV_PCM_FMTBIT_S16_LE
| SNDRV_PCM_FMTBIT_S24_LE
| SNDRV_PCM_FMTBIT_S32_LE)
},
.ops = &mt2701_afe_i2s_ops,
.symmetric_rate = 1,
},
{
.name = "I2S1",
.id = MT2701_IO_2ND_I2S,
.playback = {
.stream_name = "I2S1 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = (SNDRV_PCM_FMTBIT_S16_LE
| SNDRV_PCM_FMTBIT_S24_LE
| SNDRV_PCM_FMTBIT_S32_LE)
},
.capture = {
.stream_name = "I2S1 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = (SNDRV_PCM_FMTBIT_S16_LE
| SNDRV_PCM_FMTBIT_S24_LE
| SNDRV_PCM_FMTBIT_S32_LE)
},
.ops = &mt2701_afe_i2s_ops,
.symmetric_rate = 1,
},
{
.name = "I2S2",
.id = MT2701_IO_3RD_I2S,
.playback = {
.stream_name = "I2S2 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = (SNDRV_PCM_FMTBIT_S16_LE
| SNDRV_PCM_FMTBIT_S24_LE
| SNDRV_PCM_FMTBIT_S32_LE)
},
.capture = {
.stream_name = "I2S2 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = (SNDRV_PCM_FMTBIT_S16_LE
| SNDRV_PCM_FMTBIT_S24_LE
| SNDRV_PCM_FMTBIT_S32_LE)
},
.ops = &mt2701_afe_i2s_ops,
.symmetric_rate = 1,
},
{
.name = "I2S3",
.id = MT2701_IO_4TH_I2S,
.playback = {
.stream_name = "I2S3 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = (SNDRV_PCM_FMTBIT_S16_LE
| SNDRV_PCM_FMTBIT_S24_LE
| SNDRV_PCM_FMTBIT_S32_LE)
},
.capture = {
.stream_name = "I2S3 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = (SNDRV_PCM_FMTBIT_S16_LE
| SNDRV_PCM_FMTBIT_S24_LE
| SNDRV_PCM_FMTBIT_S32_LE)
},
.ops = &mt2701_afe_i2s_ops,
.symmetric_rate = 1,
},
{
.name = "MRG BT",
.id = MT2701_IO_MRG,
.playback = {
.stream_name = "BT Playback",
.channels_min = 1,
.channels_max = 1,
.rates = (SNDRV_PCM_RATE_8000
| SNDRV_PCM_RATE_16000),
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.capture = {
.stream_name = "BT Capture",
.channels_min = 1,
.channels_max = 1,
.rates = (SNDRV_PCM_RATE_8000
| SNDRV_PCM_RATE_16000),
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.ops = &mt2701_btmrg_ops,
.symmetric_rate = 1,
}
};
static const struct snd_kcontrol_new mt2701_afe_o00_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I00 Switch", AFE_CONN0, 0, 1, 0),
};
static const struct snd_kcontrol_new mt2701_afe_o01_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I01 Switch", AFE_CONN1, 1, 1, 0),
};
static const struct snd_kcontrol_new mt2701_afe_o02_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I02 Switch", AFE_CONN2, 2, 1, 0),
};
static const struct snd_kcontrol_new mt2701_afe_o03_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I03 Switch", AFE_CONN3, 3, 1, 0),
};
static const struct snd_kcontrol_new mt2701_afe_o14_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I26 Switch", AFE_CONN14, 26, 1, 0),
};
static const struct snd_kcontrol_new mt2701_afe_o15_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I12 Switch", AFE_CONN15, 12, 1, 0),
};
static const struct snd_kcontrol_new mt2701_afe_o16_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I13 Switch", AFE_CONN16, 13, 1, 0),
};
static const struct snd_kcontrol_new mt2701_afe_o17_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I14 Switch", AFE_CONN17, 14, 1, 0),
};
static const struct snd_kcontrol_new mt2701_afe_o18_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I15 Switch", AFE_CONN18, 15, 1, 0),
};
static const struct snd_kcontrol_new mt2701_afe_o19_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I16 Switch", AFE_CONN19, 16, 1, 0),
};
static const struct snd_kcontrol_new mt2701_afe_o20_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I17 Switch", AFE_CONN20, 17, 1, 0),
};
static const struct snd_kcontrol_new mt2701_afe_o21_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I18 Switch", AFE_CONN21, 18, 1, 0),
};
static const struct snd_kcontrol_new mt2701_afe_o22_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I19 Switch", AFE_CONN22, 19, 1, 0),
};
static const struct snd_kcontrol_new mt2701_afe_o31_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I35 Switch", AFE_CONN41, 9, 1, 0),
};
static const struct snd_kcontrol_new mt2701_afe_i02_mix[] = {
SOC_DAPM_SINGLE("I2S0 Switch", SND_SOC_NOPM, 0, 1, 0),
};
static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s0[] = {
SOC_DAPM_SINGLE_AUTODISABLE("Multich I2S0 Out Switch",
ASYS_I2SO1_CON, 26, 1, 0),
};
static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s1[] = {
SOC_DAPM_SINGLE_AUTODISABLE("Multich I2S1 Out Switch",
ASYS_I2SO2_CON, 26, 1, 0),
};
static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s2[] = {
SOC_DAPM_SINGLE_AUTODISABLE("Multich I2S2 Out Switch",
PWR2_TOP_CON, 17, 1, 0),
};
static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s3[] = {
SOC_DAPM_SINGLE_AUTODISABLE("Multich I2S3 Out Switch",
PWR2_TOP_CON, 18, 1, 0),
};
static const struct snd_soc_dapm_widget mt2701_afe_pcm_widgets[] = {
/* inter-connections */
SND_SOC_DAPM_MIXER("I00", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I01", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I02", SND_SOC_NOPM, 0, 0, mt2701_afe_i02_mix,
ARRAY_SIZE(mt2701_afe_i02_mix)),
SND_SOC_DAPM_MIXER("I03", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I12", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I13", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I14", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I15", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I16", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I17", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I18", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I19", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I26", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I35", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("O00", SND_SOC_NOPM, 0, 0, mt2701_afe_o00_mix,
ARRAY_SIZE(mt2701_afe_o00_mix)),
SND_SOC_DAPM_MIXER("O01", SND_SOC_NOPM, 0, 0, mt2701_afe_o01_mix,
ARRAY_SIZE(mt2701_afe_o01_mix)),
SND_SOC_DAPM_MIXER("O02", SND_SOC_NOPM, 0, 0, mt2701_afe_o02_mix,
ARRAY_SIZE(mt2701_afe_o02_mix)),
SND_SOC_DAPM_MIXER("O03", SND_SOC_NOPM, 0, 0, mt2701_afe_o03_mix,
ARRAY_SIZE(mt2701_afe_o03_mix)),
SND_SOC_DAPM_MIXER("O14", SND_SOC_NOPM, 0, 0, mt2701_afe_o14_mix,
ARRAY_SIZE(mt2701_afe_o14_mix)),
SND_SOC_DAPM_MIXER("O15", SND_SOC_NOPM, 0, 0, mt2701_afe_o15_mix,
ARRAY_SIZE(mt2701_afe_o15_mix)),
SND_SOC_DAPM_MIXER("O16", SND_SOC_NOPM, 0, 0, mt2701_afe_o16_mix,
ARRAY_SIZE(mt2701_afe_o16_mix)),
SND_SOC_DAPM_MIXER("O17", SND_SOC_NOPM, 0, 0, mt2701_afe_o17_mix,
ARRAY_SIZE(mt2701_afe_o17_mix)),
SND_SOC_DAPM_MIXER("O18", SND_SOC_NOPM, 0, 0, mt2701_afe_o18_mix,
ARRAY_SIZE(mt2701_afe_o18_mix)),
SND_SOC_DAPM_MIXER("O19", SND_SOC_NOPM, 0, 0, mt2701_afe_o19_mix,
ARRAY_SIZE(mt2701_afe_o19_mix)),
SND_SOC_DAPM_MIXER("O20", SND_SOC_NOPM, 0, 0, mt2701_afe_o20_mix,
ARRAY_SIZE(mt2701_afe_o20_mix)),
SND_SOC_DAPM_MIXER("O21", SND_SOC_NOPM, 0, 0, mt2701_afe_o21_mix,
ARRAY_SIZE(mt2701_afe_o21_mix)),
SND_SOC_DAPM_MIXER("O22", SND_SOC_NOPM, 0, 0, mt2701_afe_o22_mix,
ARRAY_SIZE(mt2701_afe_o22_mix)),
SND_SOC_DAPM_MIXER("O31", SND_SOC_NOPM, 0, 0, mt2701_afe_o31_mix,
ARRAY_SIZE(mt2701_afe_o31_mix)),
SND_SOC_DAPM_MIXER("I12I13", SND_SOC_NOPM, 0, 0,
mt2701_afe_multi_ch_out_i2s0,
ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s0)),
SND_SOC_DAPM_MIXER("I14I15", SND_SOC_NOPM, 0, 0,
mt2701_afe_multi_ch_out_i2s1,
ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s1)),
SND_SOC_DAPM_MIXER("I16I17", SND_SOC_NOPM, 0, 0,
mt2701_afe_multi_ch_out_i2s2,
ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s2)),
SND_SOC_DAPM_MIXER("I18I19", SND_SOC_NOPM, 0, 0,
mt2701_afe_multi_ch_out_i2s3,
ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s3)),
};
static const struct snd_soc_dapm_route mt2701_afe_pcm_routes[] = {
{"I12", NULL, "DL1"},
{"I13", NULL, "DL1"},
{"I35", NULL, "DLBT"},
{"I2S0 Playback", NULL, "O15"},
{"I2S0 Playback", NULL, "O16"},
{"I2S1 Playback", NULL, "O17"},
{"I2S1 Playback", NULL, "O18"},
{"I2S2 Playback", NULL, "O19"},
{"I2S2 Playback", NULL, "O20"},
{"I2S3 Playback", NULL, "O21"},
{"I2S3 Playback", NULL, "O22"},
{"BT Playback", NULL, "O31"},
{"UL1", NULL, "O00"},
{"UL1", NULL, "O01"},
{"UL2", NULL, "O02"},
{"UL2", NULL, "O03"},
{"ULBT", NULL, "O14"},
{"I00", NULL, "I2S0 Capture"},
{"I01", NULL, "I2S0 Capture"},
{"I02", NULL, "I2S1 Capture"},
{"I03", NULL, "I2S1 Capture"},
/* I02,03 link to UL2, also need to open I2S0 */
{"I02", "I2S0 Switch", "I2S0 Capture"},
{"I26", NULL, "BT Capture"},
{"I12I13", "Multich I2S0 Out Switch", "DLM"},
{"I14I15", "Multich I2S1 Out Switch", "DLM"},
{"I16I17", "Multich I2S2 Out Switch", "DLM"},
{"I18I19", "Multich I2S3 Out Switch", "DLM"},
{ "I12", NULL, "I12I13" },
{ "I13", NULL, "I12I13" },
{ "I14", NULL, "I14I15" },
{ "I15", NULL, "I14I15" },
{ "I16", NULL, "I16I17" },
{ "I17", NULL, "I16I17" },
{ "I18", NULL, "I18I19" },
{ "I19", NULL, "I18I19" },
{ "O00", "I00 Switch", "I00" },
{ "O01", "I01 Switch", "I01" },
{ "O02", "I02 Switch", "I02" },
{ "O03", "I03 Switch", "I03" },
{ "O14", "I26 Switch", "I26" },
{ "O15", "I12 Switch", "I12" },
{ "O16", "I13 Switch", "I13" },
{ "O17", "I14 Switch", "I14" },
{ "O18", "I15 Switch", "I15" },
{ "O19", "I16 Switch", "I16" },
{ "O20", "I17 Switch", "I17" },
{ "O21", "I18 Switch", "I18" },
{ "O22", "I19 Switch", "I19" },
{ "O31", "I35 Switch", "I35" },
};
static int mt2701_afe_pcm_probe(struct snd_soc_component *component)
{
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
snd_soc_component_init_regmap(component, afe->regmap);
return 0;
}
static const struct snd_soc_component_driver mt2701_afe_pcm_dai_component = {
.probe = mt2701_afe_pcm_probe,
.name = "mt2701-afe-pcm-dai",
.dapm_widgets = mt2701_afe_pcm_widgets,
.num_dapm_widgets = ARRAY_SIZE(mt2701_afe_pcm_widgets),
.dapm_routes = mt2701_afe_pcm_routes,
.num_dapm_routes = ARRAY_SIZE(mt2701_afe_pcm_routes),
.suspend = mtk_afe_suspend,
.resume = mtk_afe_resume,
};
static const struct mtk_base_memif_data memif_data_array[MT2701_MEMIF_NUM] = {
{
.name = "DL1",
.id = MT2701_MEMIF_DL1,
.reg_ofs_base = AFE_DL1_BASE,
.reg_ofs_cur = AFE_DL1_CUR,
.fs_reg = AFE_DAC_CON1,
.fs_shift = 0,
.fs_maskbit = 0x1f,
.mono_reg = AFE_DAC_CON3,
.mono_shift = 16,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 1,
.hd_reg = AFE_MEMIF_HD_CON0,
.hd_shift = 0,
.agent_disable_reg = AUDIO_TOP_CON5,
.agent_disable_shift = 6,
.msb_reg = -1,
},
{
.name = "DL2",
.id = MT2701_MEMIF_DL2,
.reg_ofs_base = AFE_DL2_BASE,
.reg_ofs_cur = AFE_DL2_CUR,
.fs_reg = AFE_DAC_CON1,
.fs_shift = 5,
.fs_maskbit = 0x1f,
.mono_reg = AFE_DAC_CON3,
.mono_shift = 17,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 2,
.hd_reg = AFE_MEMIF_HD_CON0,
.hd_shift = 2,
.agent_disable_reg = AUDIO_TOP_CON5,
.agent_disable_shift = 7,
.msb_reg = -1,
},
{
.name = "DL3",
.id = MT2701_MEMIF_DL3,
.reg_ofs_base = AFE_DL3_BASE,
.reg_ofs_cur = AFE_DL3_CUR,
.fs_reg = AFE_DAC_CON1,
.fs_shift = 10,
.fs_maskbit = 0x1f,
.mono_reg = AFE_DAC_CON3,
.mono_shift = 18,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 3,
.hd_reg = AFE_MEMIF_HD_CON0,
.hd_shift = 4,
.agent_disable_reg = AUDIO_TOP_CON5,
.agent_disable_shift = 8,
.msb_reg = -1,
},
{
.name = "DL4",
.id = MT2701_MEMIF_DL4,
.reg_ofs_base = AFE_DL4_BASE,
.reg_ofs_cur = AFE_DL4_CUR,
.fs_reg = AFE_DAC_CON1,
.fs_shift = 15,
.fs_maskbit = 0x1f,
.mono_reg = AFE_DAC_CON3,
.mono_shift = 19,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 4,
.hd_reg = AFE_MEMIF_HD_CON0,
.hd_shift = 6,
.agent_disable_reg = AUDIO_TOP_CON5,
.agent_disable_shift = 9,
.msb_reg = -1,
},
{
.name = "DL5",
.id = MT2701_MEMIF_DL5,
.reg_ofs_base = AFE_DL5_BASE,
.reg_ofs_cur = AFE_DL5_CUR,
.fs_reg = AFE_DAC_CON1,
.fs_shift = 20,
.fs_maskbit = 0x1f,
.mono_reg = AFE_DAC_CON3,
.mono_shift = 20,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 5,
.hd_reg = AFE_MEMIF_HD_CON0,
.hd_shift = 8,
.agent_disable_reg = AUDIO_TOP_CON5,
.agent_disable_shift = 10,
.msb_reg = -1,
},
{
.name = "DLM",
.id = MT2701_MEMIF_DLM,
.reg_ofs_base = AFE_DLMCH_BASE,
.reg_ofs_cur = AFE_DLMCH_CUR,
.fs_reg = AFE_DAC_CON1,
.fs_shift = 0,
.fs_maskbit = 0x1f,
.mono_reg = -1,
.mono_shift = -1,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 7,
.hd_reg = AFE_MEMIF_PBUF_SIZE,
.hd_shift = 28,
.agent_disable_reg = AUDIO_TOP_CON5,
.agent_disable_shift = 12,
.msb_reg = -1,
},
{
.name = "UL1",
.id = MT2701_MEMIF_UL1,
.reg_ofs_base = AFE_VUL_BASE,
.reg_ofs_cur = AFE_VUL_CUR,
.fs_reg = AFE_DAC_CON2,
.fs_shift = 0,
.fs_maskbit = 0x1f,
.mono_reg = AFE_DAC_CON4,
.mono_shift = 0,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 10,
.hd_reg = AFE_MEMIF_HD_CON1,
.hd_shift = 0,
.agent_disable_reg = AUDIO_TOP_CON5,
.agent_disable_shift = 0,
.msb_reg = -1,
},
{
.name = "UL2",
.id = MT2701_MEMIF_UL2,
.reg_ofs_base = AFE_UL2_BASE,
.reg_ofs_cur = AFE_UL2_CUR,
.fs_reg = AFE_DAC_CON2,
.fs_shift = 5,
.fs_maskbit = 0x1f,
.mono_reg = AFE_DAC_CON4,
.mono_shift = 2,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 11,
.hd_reg = AFE_MEMIF_HD_CON1,
.hd_shift = 2,
.agent_disable_reg = AUDIO_TOP_CON5,
.agent_disable_shift = 1,
.msb_reg = -1,
},
{
.name = "UL3",
.id = MT2701_MEMIF_UL3,
.reg_ofs_base = AFE_UL3_BASE,
.reg_ofs_cur = AFE_UL3_CUR,
.fs_reg = AFE_DAC_CON2,
.fs_shift = 10,
.fs_maskbit = 0x1f,
.mono_reg = AFE_DAC_CON4,
.mono_shift = 4,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 12,
.hd_reg = AFE_MEMIF_HD_CON0,
.hd_shift = 0,
.agent_disable_reg = AUDIO_TOP_CON5,
.agent_disable_shift = 2,
.msb_reg = -1,
},
{
.name = "UL4",
.id = MT2701_MEMIF_UL4,
.reg_ofs_base = AFE_UL4_BASE,
.reg_ofs_cur = AFE_UL4_CUR,
.fs_reg = AFE_DAC_CON2,
.fs_shift = 15,
.fs_maskbit = 0x1f,
.mono_reg = AFE_DAC_CON4,
.mono_shift = 6,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 13,
.hd_reg = AFE_MEMIF_HD_CON0,
.hd_shift = 6,
.agent_disable_reg = AUDIO_TOP_CON5,
.agent_disable_shift = 3,
.msb_reg = -1,
},
{
.name = "UL5",
.id = MT2701_MEMIF_UL5,
.reg_ofs_base = AFE_UL5_BASE,
.reg_ofs_cur = AFE_UL5_CUR,
.fs_reg = AFE_DAC_CON2,
.fs_shift = 20,
.mono_reg = AFE_DAC_CON4,
.mono_shift = 8,
.fs_maskbit = 0x1f,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 14,
.hd_reg = AFE_MEMIF_HD_CON0,
.hd_shift = 8,
.agent_disable_reg = AUDIO_TOP_CON5,
.agent_disable_shift = 4,
.msb_reg = -1,
},
{
.name = "DLBT",
.id = MT2701_MEMIF_DLBT,
.reg_ofs_base = AFE_ARB1_BASE,
.reg_ofs_cur = AFE_ARB1_CUR,
.fs_reg = AFE_DAC_CON3,
.fs_shift = 10,
.fs_maskbit = 0x1f,
.mono_reg = AFE_DAC_CON3,
.mono_shift = 22,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 8,
.hd_reg = AFE_MEMIF_HD_CON0,
.hd_shift = 14,
.agent_disable_reg = AUDIO_TOP_CON5,
.agent_disable_shift = 13,
.msb_reg = -1,
},
{
.name = "ULBT",
.id = MT2701_MEMIF_ULBT,
.reg_ofs_base = AFE_DAI_BASE,
.reg_ofs_cur = AFE_DAI_CUR,
.fs_reg = AFE_DAC_CON2,
.fs_shift = 30,
.fs_maskbit = 0x1,
.mono_reg = -1,
.mono_shift = -1,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 17,
.hd_reg = AFE_MEMIF_HD_CON1,
.hd_shift = 20,
.agent_disable_reg = AUDIO_TOP_CON5,
.agent_disable_shift = 16,
.msb_reg = -1,
},
};
static const struct mtk_base_irq_data irq_data[MT2701_IRQ_ASYS_END] = {
{
.id = MT2701_IRQ_ASYS_IRQ1,
.irq_cnt_reg = ASYS_IRQ1_CON,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0xffffff,
.irq_fs_reg = ASYS_IRQ1_CON,
.irq_fs_shift = 24,
.irq_fs_maskbit = 0x1f,
.irq_en_reg = ASYS_IRQ1_CON,
.irq_en_shift = 31,
.irq_clr_reg = ASYS_IRQ_CLR,
.irq_clr_shift = 0,
},
{
.id = MT2701_IRQ_ASYS_IRQ2,
.irq_cnt_reg = ASYS_IRQ2_CON,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0xffffff,
.irq_fs_reg = ASYS_IRQ2_CON,
.irq_fs_shift = 24,
.irq_fs_maskbit = 0x1f,
.irq_en_reg = ASYS_IRQ2_CON,
.irq_en_shift = 31,
.irq_clr_reg = ASYS_IRQ_CLR,
.irq_clr_shift = 1,
},
{
.id = MT2701_IRQ_ASYS_IRQ3,
.irq_cnt_reg = ASYS_IRQ3_CON,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0xffffff,
.irq_fs_reg = ASYS_IRQ3_CON,
.irq_fs_shift = 24,
.irq_fs_maskbit = 0x1f,
.irq_en_reg = ASYS_IRQ3_CON,
.irq_en_shift = 31,
.irq_clr_reg = ASYS_IRQ_CLR,
.irq_clr_shift = 2,
}
};
static const struct mt2701_i2s_data mt2701_i2s_data[][2] = {
{
{ ASYS_I2SO1_CON, 0, 0x1f },
{ ASYS_I2SIN1_CON, 0, 0x1f },
},
{
{ ASYS_I2SO2_CON, 5, 0x1f },
{ ASYS_I2SIN2_CON, 5, 0x1f },
},
{
{ ASYS_I2SO3_CON, 10, 0x1f },
{ ASYS_I2SIN3_CON, 10, 0x1f },
},
{
{ ASYS_I2SO4_CON, 15, 0x1f },
{ ASYS_I2SIN4_CON, 15, 0x1f },
},
/* TODO - extend control registers supported by newer SoCs */
};
static irqreturn_t mt2701_asys_isr(int irq_id, void *dev)
{
int id;
struct mtk_base_afe *afe = dev;
struct mtk_base_afe_memif *memif;
struct mtk_base_afe_irq *irq;
u32 status;
regmap_read(afe->regmap, ASYS_IRQ_STATUS, &status);
regmap_write(afe->regmap, ASYS_IRQ_CLR, status);
for (id = 0; id < MT2701_MEMIF_NUM; ++id) {
memif = &afe->memif[id];
if (memif->irq_usage < 0)
continue;
irq = &afe->irqs[memif->irq_usage];
if (status & 1 << irq->irq_data->irq_clr_shift)
snd_pcm_period_elapsed(memif->substream);
}
return IRQ_HANDLED;
}
static int mt2701_afe_runtime_suspend(struct device *dev)
{
struct mtk_base_afe *afe = dev_get_drvdata(dev);
return mt2701_afe_disable_clock(afe);
}
static int mt2701_afe_runtime_resume(struct device *dev)
{
struct mtk_base_afe *afe = dev_get_drvdata(dev);
return mt2701_afe_enable_clock(afe);
}
static int mt2701_afe_pcm_dev_probe(struct platform_device *pdev)
{
struct mtk_base_afe *afe;
struct mt2701_afe_private *afe_priv;
struct device *dev;
int i, irq_id, ret;
afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
if (!afe)
return -ENOMEM;
afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),
GFP_KERNEL);
if (!afe->platform_priv)
return -ENOMEM;
afe_priv = afe->platform_priv;
afe_priv->soc = of_device_get_match_data(&pdev->dev);
afe->dev = &pdev->dev;
dev = afe->dev;
afe_priv->i2s_path = devm_kcalloc(dev,
afe_priv->soc->i2s_num,
sizeof(struct mt2701_i2s_path),
GFP_KERNEL);
if (!afe_priv->i2s_path)
return -ENOMEM;
irq_id = platform_get_irq_byname(pdev, "asys");
if (irq_id < 0)
return irq_id;
ret = devm_request_irq(dev, irq_id, mt2701_asys_isr,
IRQF_TRIGGER_NONE, "asys-isr", (void *)afe);
if (ret) {
dev_err(dev, "could not request_irq for asys-isr\n");
return ret;
}
afe->regmap = syscon_node_to_regmap(dev->parent->of_node);
if (IS_ERR(afe->regmap)) {
dev_err(dev, "could not get regmap from parent\n");
return PTR_ERR(afe->regmap);
}
mutex_init(&afe->irq_alloc_lock);
/* memif initialize */
afe->memif_size = MT2701_MEMIF_NUM;
afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),
GFP_KERNEL);
if (!afe->memif)
return -ENOMEM;
for (i = 0; i < afe->memif_size; i++) {
afe->memif[i].data = &memif_data_array[i];
afe->memif[i].irq_usage = -1;
}
/* irq initialize */
afe->irqs_size = MT2701_IRQ_ASYS_END;
afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
GFP_KERNEL);
if (!afe->irqs)
return -ENOMEM;
for (i = 0; i < afe->irqs_size; i++)
afe->irqs[i].irq_data = &irq_data[i];
/* I2S initialize */
for (i = 0; i < afe_priv->soc->i2s_num; i++) {
afe_priv->i2s_path[i].i2s_data[SNDRV_PCM_STREAM_PLAYBACK] =
&mt2701_i2s_data[i][SNDRV_PCM_STREAM_PLAYBACK];
afe_priv->i2s_path[i].i2s_data[SNDRV_PCM_STREAM_CAPTURE] =
&mt2701_i2s_data[i][SNDRV_PCM_STREAM_CAPTURE];
}
afe->mtk_afe_hardware = &mt2701_afe_hardware;
afe->memif_fs = mt2701_memif_fs;
afe->irq_fs = mt2701_irq_fs;
afe->reg_back_up_list = mt2701_afe_backup_list;
afe->reg_back_up_list_num = ARRAY_SIZE(mt2701_afe_backup_list);
afe->runtime_resume = mt2701_afe_runtime_resume;
afe->runtime_suspend = mt2701_afe_runtime_suspend;
/* initial audio related clock */
ret = mt2701_init_clock(afe);
if (ret) {
dev_err(dev, "init clock error\n");
return ret;
}
platform_set_drvdata(pdev, afe);
pm_runtime_enable(dev);
if (!pm_runtime_enabled(dev)) {
ret = mt2701_afe_runtime_resume(dev);
if (ret)
goto err_pm_disable;
}
pm_runtime_get_sync(dev);
ret = devm_snd_soc_register_component(&pdev->dev, &mtk_afe_pcm_platform,
NULL, 0);
if (ret) {
dev_warn(dev, "err_platform\n");
goto err_platform;
}
ret = devm_snd_soc_register_component(&pdev->dev,
&mt2701_afe_pcm_dai_component,
mt2701_afe_pcm_dais,
ARRAY_SIZE(mt2701_afe_pcm_dais));
if (ret) {
dev_warn(dev, "err_dai_component\n");
goto err_platform;
}
return 0;
err_platform:
pm_runtime_put_sync(dev);
err_pm_disable:
pm_runtime_disable(dev);
return ret;
}
static void mt2701_afe_pcm_dev_remove(struct platform_device *pdev)
{
pm_runtime_put_sync(&pdev->dev);
pm_runtime_disable(&pdev->dev);
if (!pm_runtime_status_suspended(&pdev->dev))
mt2701_afe_runtime_suspend(&pdev->dev);
}
static const struct mt2701_soc_variants mt2701_soc_v1 = {
.i2s_num = 4,
};
static const struct mt2701_soc_variants mt2701_soc_v2 = {
.has_one_heart_mode = true,
.i2s_num = 4,
};
static const struct of_device_id mt2701_afe_pcm_dt_match[] = {
{ .compatible = "mediatek,mt2701-audio", .data = &mt2701_soc_v1 },
{ .compatible = "mediatek,mt7622-audio", .data = &mt2701_soc_v2 },
{},
};
MODULE_DEVICE_TABLE(of, mt2701_afe_pcm_dt_match);
static const struct dev_pm_ops mt2701_afe_pm_ops = {
SET_RUNTIME_PM_OPS(mt2701_afe_runtime_suspend,
mt2701_afe_runtime_resume, NULL)
};
static struct platform_driver mt2701_afe_pcm_driver = {
.driver = {
.name = "mt2701-audio",
.of_match_table = mt2701_afe_pcm_dt_match,
.pm = &mt2701_afe_pm_ops,
},
.probe = mt2701_afe_pcm_dev_probe,
.remove_new = mt2701_afe_pcm_dev_remove,
};
module_platform_driver(mt2701_afe_pcm_driver);
MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 2701");
MODULE_AUTHOR("Garlic Tseng <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/mediatek/mt2701/mt2701-afe-pcm.c |
// SPDX-License-Identifier: GPL-2.0
//
// mt6797-mt6351.c -- MT6797 MT6351 ALSA SoC machine driver
//
// Copyright (c) 2018 MediaTek Inc.
// Author: KaiChieh Chuang <[email protected]>
#include <linux/module.h>
#include <sound/soc.h>
#include "mt6797-afe-common.h"
SND_SOC_DAILINK_DEFS(playback_1,
DAILINK_COMP_ARRAY(COMP_CPU("DL1")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(playback_2,
DAILINK_COMP_ARRAY(COMP_CPU("DL2")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(playback_3,
DAILINK_COMP_ARRAY(COMP_CPU("DL3")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture_1,
DAILINK_COMP_ARRAY(COMP_CPU("UL1")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture_2,
DAILINK_COMP_ARRAY(COMP_CPU("UL2")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture_3,
DAILINK_COMP_ARRAY(COMP_CPU("UL3")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture_mono_1,
DAILINK_COMP_ARRAY(COMP_CPU("UL_MONO_1")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(hostless_lpbk,
DAILINK_COMP_ARRAY(COMP_CPU("Hostless LPBK DAI")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(hostless_speech,
DAILINK_COMP_ARRAY(COMP_CPU("Hostless Speech DAI")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(primary_codec,
DAILINK_COMP_ARRAY(COMP_CPU("ADDA")),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "mt6351-snd-codec-aif1")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(pcm1,
DAILINK_COMP_ARRAY(COMP_CPU("PCM 1")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(pcm2,
DAILINK_COMP_ARRAY(COMP_CPU("PCM 2")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
static struct snd_soc_dai_link mt6797_mt6351_dai_links[] = {
/* FE */
{
.name = "Playback_1",
.stream_name = "Playback_1",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(playback_1),
},
{
.name = "Playback_2",
.stream_name = "Playback_2",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(playback_2),
},
{
.name = "Playback_3",
.stream_name = "Playback_3",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(playback_3),
},
{
.name = "Capture_1",
.stream_name = "Capture_1",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(capture_1),
},
{
.name = "Capture_2",
.stream_name = "Capture_2",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(capture_2),
},
{
.name = "Capture_3",
.stream_name = "Capture_3",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(capture_3),
},
{
.name = "Capture_Mono_1",
.stream_name = "Capture_Mono_1",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(capture_mono_1),
},
{
.name = "Hostless_LPBK",
.stream_name = "Hostless_LPBK",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(hostless_lpbk),
},
{
.name = "Hostless_Speech",
.stream_name = "Hostless_Speech",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(hostless_speech),
},
/* BE */
{
.name = "Primary Codec",
.no_pcm = 1,
.dpcm_playback = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(primary_codec),
},
{
.name = "PCM 1",
.no_pcm = 1,
.dpcm_playback = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(pcm1),
},
{
.name = "PCM 2",
.no_pcm = 1,
.dpcm_playback = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(pcm2),
},
};
static struct snd_soc_card mt6797_mt6351_card = {
.name = "mt6797-mt6351",
.owner = THIS_MODULE,
.dai_link = mt6797_mt6351_dai_links,
.num_links = ARRAY_SIZE(mt6797_mt6351_dai_links),
};
static int mt6797_mt6351_dev_probe(struct platform_device *pdev)
{
struct snd_soc_card *card = &mt6797_mt6351_card;
struct device_node *platform_node, *codec_node;
struct snd_soc_dai_link *dai_link;
int ret, i;
card->dev = &pdev->dev;
platform_node = of_parse_phandle(pdev->dev.of_node,
"mediatek,platform", 0);
if (!platform_node) {
dev_err(&pdev->dev, "Property 'platform' missing or invalid\n");
return -EINVAL;
}
for_each_card_prelinks(card, i, dai_link) {
if (dai_link->platforms->name)
continue;
dai_link->platforms->of_node = platform_node;
}
codec_node = of_parse_phandle(pdev->dev.of_node,
"mediatek,audio-codec", 0);
if (!codec_node) {
dev_err(&pdev->dev,
"Property 'audio-codec' missing or invalid\n");
ret = -EINVAL;
goto put_platform_node;
}
for_each_card_prelinks(card, i, dai_link) {
if (dai_link->codecs->name)
continue;
dai_link->codecs->of_node = codec_node;
}
ret = devm_snd_soc_register_card(&pdev->dev, card);
if (ret)
dev_err(&pdev->dev, "%s snd_soc_register_card fail %d\n",
__func__, ret);
of_node_put(codec_node);
put_platform_node:
of_node_put(platform_node);
return ret;
}
#ifdef CONFIG_OF
static const struct of_device_id mt6797_mt6351_dt_match[] = {
{.compatible = "mediatek,mt6797-mt6351-sound",},
{}
};
MODULE_DEVICE_TABLE(of, mt6797_mt6351_dt_match);
#endif
static struct platform_driver mt6797_mt6351_driver = {
.driver = {
.name = "mt6797-mt6351",
#ifdef CONFIG_OF
.of_match_table = mt6797_mt6351_dt_match,
#endif
},
.probe = mt6797_mt6351_dev_probe,
};
module_platform_driver(mt6797_mt6351_driver);
/* Module information */
MODULE_DESCRIPTION("MT6797 MT6351 ALSA SoC machine driver");
MODULE_AUTHOR("KaiChieh Chuang <[email protected]>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("mt6797 mt6351 soc card");
| linux-master | sound/soc/mediatek/mt6797/mt6797-mt6351.c |
// SPDX-License-Identifier: GPL-2.0
//
// mt6797-afe-clk.c -- Mediatek 6797 afe clock ctrl
//
// Copyright (c) 2018 MediaTek Inc.
// Author: KaiChieh Chuang <[email protected]>
#include <linux/clk.h>
#include "mt6797-afe-common.h"
#include "mt6797-afe-clk.h"
enum {
CLK_INFRA_SYS_AUD,
CLK_INFRA_SYS_AUD_26M,
CLK_TOP_MUX_AUD,
CLK_TOP_MUX_AUD_BUS,
CLK_TOP_SYSPLL3_D4,
CLK_TOP_SYSPLL1_D4,
CLK_CLK26M,
CLK_NUM
};
static const char *aud_clks[CLK_NUM] = {
[CLK_INFRA_SYS_AUD] = "infra_sys_audio_clk",
[CLK_INFRA_SYS_AUD_26M] = "infra_sys_audio_26m",
[CLK_TOP_MUX_AUD] = "top_mux_audio",
[CLK_TOP_MUX_AUD_BUS] = "top_mux_aud_intbus",
[CLK_TOP_SYSPLL3_D4] = "top_sys_pll3_d4",
[CLK_TOP_SYSPLL1_D4] = "top_sys_pll1_d4",
[CLK_CLK26M] = "top_clk26m_clk",
};
int mt6797_init_clock(struct mtk_base_afe *afe)
{
struct mt6797_afe_private *afe_priv = afe->platform_priv;
int i;
afe_priv->clk = devm_kcalloc(afe->dev, CLK_NUM, sizeof(*afe_priv->clk),
GFP_KERNEL);
if (!afe_priv->clk)
return -ENOMEM;
for (i = 0; i < CLK_NUM; i++) {
afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);
if (IS_ERR(afe_priv->clk[i])) {
dev_err(afe->dev, "%s(), devm_clk_get %s fail, ret %ld\n",
__func__, aud_clks[i],
PTR_ERR(afe_priv->clk[i]));
return PTR_ERR(afe_priv->clk[i]);
}
}
return 0;
}
int mt6797_afe_enable_clock(struct mtk_base_afe *afe)
{
struct mt6797_afe_private *afe_priv = afe->platform_priv;
int ret;
ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_SYS_AUD]);
if (ret) {
dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_INFRA_SYS_AUD], ret);
goto CLK_INFRA_SYS_AUDIO_ERR;
}
ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_SYS_AUD_26M]);
if (ret) {
dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_INFRA_SYS_AUD_26M], ret);
goto CLK_INFRA_SYS_AUD_26M_ERR;
}
ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD]);
if (ret) {
dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD], ret);
goto CLK_MUX_AUDIO_ERR;
}
ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD],
afe_priv->clk[CLK_CLK26M]);
if (ret) {
dev_err(afe->dev, "%s(), clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD],
aud_clks[CLK_CLK26M], ret);
goto CLK_MUX_AUDIO_ERR;
}
ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_BUS]);
if (ret) {
dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_BUS], ret);
goto CLK_MUX_AUDIO_INTBUS_ERR;
}
return ret;
CLK_MUX_AUDIO_INTBUS_ERR:
clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_BUS]);
CLK_MUX_AUDIO_ERR:
clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD]);
CLK_INFRA_SYS_AUD_26M_ERR:
clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUD_26M]);
CLK_INFRA_SYS_AUDIO_ERR:
clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUD]);
return 0;
}
int mt6797_afe_disable_clock(struct mtk_base_afe *afe)
{
struct mt6797_afe_private *afe_priv = afe->platform_priv;
clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_BUS]);
clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD]);
clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUD_26M]);
clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUD]);
return 0;
}
| linux-master | sound/soc/mediatek/mt6797/mt6797-afe-clk.c |
// SPDX-License-Identifier: GPL-2.0
//
// MediaTek ALSA SoC Audio DAI Hostless Control
//
// Copyright (c) 2018 MediaTek Inc.
// Author: KaiChieh Chuang <[email protected]>
#include "mt6797-afe-common.h"
/* dai component */
static const struct snd_soc_dapm_route mtk_dai_hostless_routes[] = {
/* Hostless ADDA Loopback */
{"ADDA_DL_CH1", "ADDA_UL_CH1", "Hostless LPBK DL"},
{"ADDA_DL_CH1", "ADDA_UL_CH2", "Hostless LPBK DL"},
{"ADDA_DL_CH2", "ADDA_UL_CH1", "Hostless LPBK DL"},
{"ADDA_DL_CH2", "ADDA_UL_CH2", "Hostless LPBK DL"},
{"Hostless LPBK UL", NULL, "ADDA Capture"},
/* Hostless Speech */
{"ADDA_DL_CH1", "PCM_1_CAP_CH1", "Hostless Speech DL"},
{"ADDA_DL_CH2", "PCM_1_CAP_CH1", "Hostless Speech DL"},
{"ADDA_DL_CH2", "PCM_1_CAP_CH2", "Hostless Speech DL"},
{"ADDA_DL_CH1", "PCM_2_CAP_CH1", "Hostless Speech DL"},
{"ADDA_DL_CH2", "PCM_2_CAP_CH1", "Hostless Speech DL"},
{"ADDA_DL_CH2", "PCM_2_CAP_CH2", "Hostless Speech DL"},
{"PCM_1_PB_CH1", "ADDA_UL_CH1", "Hostless Speech DL"},
{"PCM_1_PB_CH2", "ADDA_UL_CH2", "Hostless Speech DL"},
{"PCM_2_PB_CH1", "ADDA_UL_CH1", "Hostless Speech DL"},
{"PCM_2_PB_CH2", "ADDA_UL_CH2", "Hostless Speech DL"},
{"Hostless Speech UL", NULL, "PCM 1 Capture"},
{"Hostless Speech UL", NULL, "PCM 2 Capture"},
{"Hostless Speech UL", NULL, "ADDA Capture"},
};
/* dai ops */
static int mtk_dai_hostless_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
return snd_soc_set_runtime_hwparams(substream, afe->mtk_afe_hardware);
}
static const struct snd_soc_dai_ops mtk_dai_hostless_ops = {
.startup = mtk_dai_hostless_startup,
};
/* dai driver */
#define MTK_HOSTLESS_RATES (SNDRV_PCM_RATE_8000_48000 |\
SNDRV_PCM_RATE_88200 |\
SNDRV_PCM_RATE_96000 |\
SNDRV_PCM_RATE_176400 |\
SNDRV_PCM_RATE_192000)
#define MTK_HOSTLESS_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver mtk_dai_hostless_driver[] = {
{
.name = "Hostless LPBK DAI",
.id = MT6797_DAI_HOSTLESS_LPBK,
.playback = {
.stream_name = "Hostless LPBK DL",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_HOSTLESS_RATES,
.formats = MTK_HOSTLESS_FORMATS,
},
.capture = {
.stream_name = "Hostless LPBK UL",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_HOSTLESS_RATES,
.formats = MTK_HOSTLESS_FORMATS,
},
.ops = &mtk_dai_hostless_ops,
},
{
.name = "Hostless Speech DAI",
.id = MT6797_DAI_HOSTLESS_SPEECH,
.playback = {
.stream_name = "Hostless Speech DL",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_HOSTLESS_RATES,
.formats = MTK_HOSTLESS_FORMATS,
},
.capture = {
.stream_name = "Hostless Speech UL",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_HOSTLESS_RATES,
.formats = MTK_HOSTLESS_FORMATS,
},
.ops = &mtk_dai_hostless_ops,
},
};
int mt6797_dai_hostless_register(struct mtk_base_afe *afe)
{
struct mtk_base_afe_dai *dai;
dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
if (!dai)
return -ENOMEM;
list_add(&dai->list, &afe->sub_dais);
dai->dai_drivers = mtk_dai_hostless_driver;
dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_hostless_driver);
dai->dapm_routes = mtk_dai_hostless_routes;
dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_hostless_routes);
return 0;
}
| linux-master | sound/soc/mediatek/mt6797/mt6797-dai-hostless.c |
// SPDX-License-Identifier: GPL-2.0
//
// MediaTek ALSA SoC Audio DAI I2S Control
//
// Copyright (c) 2018 MediaTek Inc.
// Author: KaiChieh Chuang <[email protected]>
#include <linux/regmap.h>
#include <sound/pcm_params.h>
#include "mt6797-afe-common.h"
#include "mt6797-interconnection.h"
#include "mt6797-reg.h"
enum AUD_TX_LCH_RPT {
AUD_TX_LCH_RPT_NO_REPEAT = 0,
AUD_TX_LCH_RPT_REPEAT = 1
};
enum AUD_VBT_16K_MODE {
AUD_VBT_16K_MODE_DISABLE = 0,
AUD_VBT_16K_MODE_ENABLE = 1
};
enum AUD_EXT_MODEM {
AUD_EXT_MODEM_SELECT_INTERNAL = 0,
AUD_EXT_MODEM_SELECT_EXTERNAL = 1
};
enum AUD_PCM_SYNC_TYPE {
/* bck sync length = 1 */
AUD_PCM_ONE_BCK_CYCLE_SYNC = 0,
/* bck sync length = PCM_INTF_CON1[9:13] */
AUD_PCM_EXTENDED_BCK_CYCLE_SYNC = 1
};
enum AUD_BT_MODE {
AUD_BT_MODE_DUAL_MIC_ON_TX = 0,
AUD_BT_MODE_SINGLE_MIC_ON_TX = 1
};
enum AUD_PCM_AFIFO_SRC {
/* slave mode & external modem uses different crystal */
AUD_PCM_AFIFO_ASRC = 0,
/* slave mode & external modem uses the same crystal */
AUD_PCM_AFIFO_AFIFO = 1
};
enum AUD_PCM_CLOCK_SOURCE {
AUD_PCM_CLOCK_MASTER_MODE = 0,
AUD_PCM_CLOCK_SLAVE_MODE = 1
};
enum AUD_PCM_WLEN {
AUD_PCM_WLEN_PCM_32_BCK_CYCLES = 0,
AUD_PCM_WLEN_PCM_64_BCK_CYCLES = 1
};
enum AUD_PCM_MODE {
AUD_PCM_MODE_PCM_MODE_8K = 0,
AUD_PCM_MODE_PCM_MODE_16K = 1,
AUD_PCM_MODE_PCM_MODE_32K = 2,
AUD_PCM_MODE_PCM_MODE_48K = 3,
};
enum AUD_PCM_FMT {
AUD_PCM_FMT_I2S = 0,
AUD_PCM_FMT_EIAJ = 1,
AUD_PCM_FMT_PCM_MODE_A = 2,
AUD_PCM_FMT_PCM_MODE_B = 3
};
enum AUD_BCLK_OUT_INV {
AUD_BCLK_OUT_INV_NO_INVERSE = 0,
AUD_BCLK_OUT_INV_INVERSE = 1
};
enum AUD_PCM_EN {
AUD_PCM_EN_DISABLE = 0,
AUD_PCM_EN_ENABLE = 1
};
/* dai component */
static const struct snd_kcontrol_new mtk_pcm_1_playback_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN7,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN7,
I_DL2_CH1, 1, 0),
};
static const struct snd_kcontrol_new mtk_pcm_1_playback_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN8,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN8,
I_DL2_CH2, 1, 0),
};
static const struct snd_kcontrol_new mtk_pcm_1_playback_ch4_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN27,
I_DL1_CH1, 1, 0),
};
static const struct snd_kcontrol_new mtk_pcm_2_playback_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN17,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN17,
I_DL2_CH1, 1, 0),
};
static const struct snd_kcontrol_new mtk_pcm_2_playback_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN18,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN18,
I_DL2_CH2, 1, 0),
};
static const struct snd_kcontrol_new mtk_pcm_2_playback_ch4_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN24,
I_DL1_CH1, 1, 0),
};
static const struct snd_soc_dapm_widget mtk_dai_pcm_widgets[] = {
/* inter-connections */
SND_SOC_DAPM_MIXER("PCM_1_PB_CH1", SND_SOC_NOPM, 0, 0,
mtk_pcm_1_playback_ch1_mix,
ARRAY_SIZE(mtk_pcm_1_playback_ch1_mix)),
SND_SOC_DAPM_MIXER("PCM_1_PB_CH2", SND_SOC_NOPM, 0, 0,
mtk_pcm_1_playback_ch2_mix,
ARRAY_SIZE(mtk_pcm_1_playback_ch2_mix)),
SND_SOC_DAPM_MIXER("PCM_1_PB_CH4", SND_SOC_NOPM, 0, 0,
mtk_pcm_1_playback_ch4_mix,
ARRAY_SIZE(mtk_pcm_1_playback_ch4_mix)),
SND_SOC_DAPM_MIXER("PCM_2_PB_CH1", SND_SOC_NOPM, 0, 0,
mtk_pcm_2_playback_ch1_mix,
ARRAY_SIZE(mtk_pcm_2_playback_ch1_mix)),
SND_SOC_DAPM_MIXER("PCM_2_PB_CH2", SND_SOC_NOPM, 0, 0,
mtk_pcm_2_playback_ch2_mix,
ARRAY_SIZE(mtk_pcm_2_playback_ch2_mix)),
SND_SOC_DAPM_MIXER("PCM_2_PB_CH4", SND_SOC_NOPM, 0, 0,
mtk_pcm_2_playback_ch4_mix,
ARRAY_SIZE(mtk_pcm_2_playback_ch4_mix)),
SND_SOC_DAPM_SUPPLY("PCM_1_EN", PCM_INTF_CON1, PCM_EN_SFT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY("PCM_2_EN", PCM2_INTF_CON, PCM2_EN_SFT, 0,
NULL, 0),
SND_SOC_DAPM_INPUT("MD1_TO_AFE"),
SND_SOC_DAPM_INPUT("MD2_TO_AFE"),
SND_SOC_DAPM_OUTPUT("AFE_TO_MD1"),
SND_SOC_DAPM_OUTPUT("AFE_TO_MD2"),
};
static const struct snd_soc_dapm_route mtk_dai_pcm_routes[] = {
{"PCM 1 Playback", NULL, "PCM_1_PB_CH1"},
{"PCM 1 Playback", NULL, "PCM_1_PB_CH2"},
{"PCM 1 Playback", NULL, "PCM_1_PB_CH4"},
{"PCM 2 Playback", NULL, "PCM_2_PB_CH1"},
{"PCM 2 Playback", NULL, "PCM_2_PB_CH2"},
{"PCM 2 Playback", NULL, "PCM_2_PB_CH4"},
{"PCM 1 Playback", NULL, "PCM_1_EN"},
{"PCM 2 Playback", NULL, "PCM_2_EN"},
{"PCM 1 Capture", NULL, "PCM_1_EN"},
{"PCM 2 Capture", NULL, "PCM_2_EN"},
{"AFE_TO_MD1", NULL, "PCM 2 Playback"},
{"AFE_TO_MD2", NULL, "PCM 1 Playback"},
{"PCM 2 Capture", NULL, "MD1_TO_AFE"},
{"PCM 1 Capture", NULL, "MD2_TO_AFE"},
{"PCM_1_PB_CH1", "DL2_CH1", "DL2"},
{"PCM_1_PB_CH2", "DL2_CH2", "DL2"},
{"PCM_1_PB_CH4", "DL1_CH1", "DL1"},
{"PCM_2_PB_CH1", "DL2_CH1", "DL2"},
{"PCM_2_PB_CH2", "DL2_CH2", "DL2"},
{"PCM_2_PB_CH4", "DL1_CH1", "DL1"},
};
/* dai ops */
static int mtk_dai_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct snd_soc_dapm_widget *p = snd_soc_dai_get_widget_playback(dai);
struct snd_soc_dapm_widget *c = snd_soc_dai_get_widget_capture(dai);
unsigned int rate = params_rate(params);
unsigned int rate_reg = mt6797_rate_transform(afe->dev, rate, dai->id);
unsigned int pcm_con = 0;
dev_dbg(afe->dev, "%s(), id %d, stream %d, rate %d, rate_reg %d, widget active p %d, c %d\n",
__func__,
dai->id,
substream->stream,
rate,
rate_reg,
p->active,
c->active);
if (p->active || c->active)
return 0;
switch (dai->id) {
case MT6797_DAI_PCM_1:
pcm_con |= AUD_BCLK_OUT_INV_NO_INVERSE << PCM_BCLK_OUT_INV_SFT;
pcm_con |= AUD_TX_LCH_RPT_NO_REPEAT << PCM_TX_LCH_RPT_SFT;
pcm_con |= AUD_VBT_16K_MODE_DISABLE << PCM_VBT_16K_MODE_SFT;
pcm_con |= AUD_EXT_MODEM_SELECT_INTERNAL << PCM_EXT_MODEM_SFT;
pcm_con |= 0 << PCM_SYNC_LENGTH_SFT;
pcm_con |= AUD_PCM_ONE_BCK_CYCLE_SYNC << PCM_SYNC_TYPE_SFT;
pcm_con |= AUD_BT_MODE_DUAL_MIC_ON_TX << PCM_BT_MODE_SFT;
pcm_con |= AUD_PCM_AFIFO_AFIFO << PCM_BYP_ASRC_SFT;
pcm_con |= AUD_PCM_CLOCK_SLAVE_MODE << PCM_SLAVE_SFT;
pcm_con |= rate_reg << PCM_MODE_SFT;
pcm_con |= AUD_PCM_FMT_PCM_MODE_B << PCM_FMT_SFT;
regmap_update_bits(afe->regmap, PCM_INTF_CON1,
0xfffffffe, pcm_con);
break;
case MT6797_DAI_PCM_2:
pcm_con |= AUD_TX_LCH_RPT_NO_REPEAT << PCM2_TX_LCH_RPT_SFT;
pcm_con |= AUD_VBT_16K_MODE_DISABLE << PCM2_VBT_16K_MODE_SFT;
pcm_con |= AUD_BT_MODE_DUAL_MIC_ON_TX << PCM2_BT_MODE_SFT;
pcm_con |= AUD_PCM_AFIFO_AFIFO << PCM2_AFIFO_SFT;
pcm_con |= AUD_PCM_WLEN_PCM_32_BCK_CYCLES << PCM2_WLEN_SFT;
pcm_con |= rate_reg << PCM2_MODE_SFT;
pcm_con |= AUD_PCM_FMT_PCM_MODE_B << PCM2_FMT_SFT;
regmap_update_bits(afe->regmap, PCM2_INTF_CON,
0xfffffffe, pcm_con);
break;
default:
dev_warn(afe->dev, "%s(), id %d not support\n",
__func__, dai->id);
return -EINVAL;
}
return 0;
}
static const struct snd_soc_dai_ops mtk_dai_pcm_ops = {
.hw_params = mtk_dai_pcm_hw_params,
};
/* dai driver */
#define MTK_PCM_RATES (SNDRV_PCM_RATE_8000 |\
SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 |\
SNDRV_PCM_RATE_48000)
#define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver mtk_dai_pcm_driver[] = {
{
.name = "PCM 1",
.id = MT6797_DAI_PCM_1,
.playback = {
.stream_name = "PCM 1 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.capture = {
.stream_name = "PCM 1 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_dai_pcm_ops,
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
},
{
.name = "PCM 2",
.id = MT6797_DAI_PCM_2,
.playback = {
.stream_name = "PCM 2 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.capture = {
.stream_name = "PCM 2 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_dai_pcm_ops,
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
},
};
int mt6797_dai_pcm_register(struct mtk_base_afe *afe)
{
struct mtk_base_afe_dai *dai;
dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
if (!dai)
return -ENOMEM;
list_add(&dai->list, &afe->sub_dais);
dai->dai_drivers = mtk_dai_pcm_driver;
dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_pcm_driver);
dai->dapm_widgets = mtk_dai_pcm_widgets;
dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_pcm_widgets);
dai->dapm_routes = mtk_dai_pcm_routes;
dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_pcm_routes);
return 0;
}
| linux-master | sound/soc/mediatek/mt6797/mt6797-dai-pcm.c |
// SPDX-License-Identifier: GPL-2.0
//
// Mediatek ALSA SoC AFE platform driver for 6797
//
// Copyright (c) 2018 MediaTek Inc.
// Author: KaiChieh Chuang <[email protected]>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/pm_runtime.h>
#include "mt6797-afe-common.h"
#include "mt6797-afe-clk.h"
#include "mt6797-interconnection.h"
#include "mt6797-reg.h"
#include "../common/mtk-afe-platform-driver.h"
#include "../common/mtk-afe-fe-dai.h"
enum {
MTK_AFE_RATE_8K = 0,
MTK_AFE_RATE_11K = 1,
MTK_AFE_RATE_12K = 2,
MTK_AFE_RATE_384K = 3,
MTK_AFE_RATE_16K = 4,
MTK_AFE_RATE_22K = 5,
MTK_AFE_RATE_24K = 6,
MTK_AFE_RATE_130K = 7,
MTK_AFE_RATE_32K = 8,
MTK_AFE_RATE_44K = 9,
MTK_AFE_RATE_48K = 10,
MTK_AFE_RATE_88K = 11,
MTK_AFE_RATE_96K = 12,
MTK_AFE_RATE_174K = 13,
MTK_AFE_RATE_192K = 14,
MTK_AFE_RATE_260K = 15,
};
enum {
MTK_AFE_DAI_MEMIF_RATE_8K = 0,
MTK_AFE_DAI_MEMIF_RATE_16K = 1,
MTK_AFE_DAI_MEMIF_RATE_32K = 2,
};
enum {
MTK_AFE_PCM_RATE_8K = 0,
MTK_AFE_PCM_RATE_16K = 1,
MTK_AFE_PCM_RATE_32K = 2,
MTK_AFE_PCM_RATE_48K = 3,
};
unsigned int mt6797_general_rate_transform(struct device *dev,
unsigned int rate)
{
switch (rate) {
case 8000:
return MTK_AFE_RATE_8K;
case 11025:
return MTK_AFE_RATE_11K;
case 12000:
return MTK_AFE_RATE_12K;
case 16000:
return MTK_AFE_RATE_16K;
case 22050:
return MTK_AFE_RATE_22K;
case 24000:
return MTK_AFE_RATE_24K;
case 32000:
return MTK_AFE_RATE_32K;
case 44100:
return MTK_AFE_RATE_44K;
case 48000:
return MTK_AFE_RATE_48K;
case 88200:
return MTK_AFE_RATE_88K;
case 96000:
return MTK_AFE_RATE_96K;
case 130000:
return MTK_AFE_RATE_130K;
case 176400:
return MTK_AFE_RATE_174K;
case 192000:
return MTK_AFE_RATE_192K;
case 260000:
return MTK_AFE_RATE_260K;
default:
dev_warn(dev, "%s(), rate %u invalid, use %d!!!\n",
__func__, rate, MTK_AFE_RATE_48K);
return MTK_AFE_RATE_48K;
}
}
static unsigned int dai_memif_rate_transform(struct device *dev,
unsigned int rate)
{
switch (rate) {
case 8000:
return MTK_AFE_DAI_MEMIF_RATE_8K;
case 16000:
return MTK_AFE_DAI_MEMIF_RATE_16K;
case 32000:
return MTK_AFE_DAI_MEMIF_RATE_32K;
default:
dev_warn(dev, "%s(), rate %u invalid, use %d!!!\n",
__func__, rate, MTK_AFE_DAI_MEMIF_RATE_16K);
return MTK_AFE_DAI_MEMIF_RATE_16K;
}
}
unsigned int mt6797_rate_transform(struct device *dev,
unsigned int rate, int aud_blk)
{
switch (aud_blk) {
case MT6797_MEMIF_DAI:
case MT6797_MEMIF_MOD_DAI:
return dai_memif_rate_transform(dev, rate);
default:
return mt6797_general_rate_transform(dev, rate);
}
}
static const struct snd_pcm_hardware mt6797_afe_hardware = {
.info = SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_MMAP_VALID,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE |
SNDRV_PCM_FMTBIT_S32_LE,
.period_bytes_min = 256,
.period_bytes_max = 4 * 48 * 1024,
.periods_min = 2,
.periods_max = 256,
.buffer_bytes_max = 8 * 48 * 1024,
.fifo_size = 0,
};
static int mt6797_memif_fs(struct snd_pcm_substream *substream,
unsigned int rate)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_component *component =
snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
int id = asoc_rtd_to_cpu(rtd, 0)->id;
return mt6797_rate_transform(afe->dev, rate, id);
}
static int mt6797_irq_fs(struct snd_pcm_substream *substream, unsigned int rate)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_component *component =
snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
return mt6797_general_rate_transform(afe->dev, rate);
}
#define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\
SNDRV_PCM_RATE_88200 |\
SNDRV_PCM_RATE_96000 |\
SNDRV_PCM_RATE_176400 |\
SNDRV_PCM_RATE_192000)
#define MTK_PCM_DAI_RATES (SNDRV_PCM_RATE_8000 |\
SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000)
#define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver mt6797_memif_dai_driver[] = {
/* FE DAIs: memory intefaces to CPU */
{
.name = "DL1",
.id = MT6797_MEMIF_DL1,
.playback = {
.stream_name = "DL1",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_afe_fe_ops,
},
{
.name = "DL2",
.id = MT6797_MEMIF_DL2,
.playback = {
.stream_name = "DL2",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_afe_fe_ops,
},
{
.name = "DL3",
.id = MT6797_MEMIF_DL3,
.playback = {
.stream_name = "DL3",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_afe_fe_ops,
},
{
.name = "UL1",
.id = MT6797_MEMIF_VUL12,
.capture = {
.stream_name = "UL1",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_afe_fe_ops,
},
{
.name = "UL2",
.id = MT6797_MEMIF_AWB,
.capture = {
.stream_name = "UL2",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_afe_fe_ops,
},
{
.name = "UL3",
.id = MT6797_MEMIF_VUL,
.capture = {
.stream_name = "UL3",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_afe_fe_ops,
},
{
.name = "UL_MONO_1",
.id = MT6797_MEMIF_MOD_DAI,
.capture = {
.stream_name = "UL_MONO_1",
.channels_min = 1,
.channels_max = 1,
.rates = MTK_PCM_DAI_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_afe_fe_ops,
},
{
.name = "UL_MONO_2",
.id = MT6797_MEMIF_DAI,
.capture = {
.stream_name = "UL_MONO_2",
.channels_min = 1,
.channels_max = 1,
.rates = MTK_PCM_DAI_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_afe_fe_ops,
},
};
/* dma widget & routes*/
static const struct snd_kcontrol_new memif_ul1_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN21,
I_ADDA_UL_CH1, 1, 0),
};
static const struct snd_kcontrol_new memif_ul1_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN22,
I_ADDA_UL_CH2, 1, 0),
};
static const struct snd_kcontrol_new memif_ul2_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN5,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN5,
I_DL1_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN5,
I_DL2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN5,
I_DL3_CH1, 1, 0),
};
static const struct snd_kcontrol_new memif_ul2_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN6,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN6,
I_DL1_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN6,
I_DL2_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN6,
I_DL3_CH2, 1, 0),
};
static const struct snd_kcontrol_new memif_ul3_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN9,
I_ADDA_UL_CH1, 1, 0),
};
static const struct snd_kcontrol_new memif_ul3_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN10,
I_ADDA_UL_CH2, 1, 0),
};
static const struct snd_kcontrol_new memif_ul_mono_1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN12,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN12,
I_ADDA_UL_CH2, 1, 0),
};
static const struct snd_kcontrol_new memif_ul_mono_2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN11,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN11,
I_ADDA_UL_CH2, 1, 0),
};
static const struct snd_soc_dapm_widget mt6797_memif_widgets[] = {
/* memif */
SND_SOC_DAPM_MIXER("UL1_CH1", SND_SOC_NOPM, 0, 0,
memif_ul1_ch1_mix, ARRAY_SIZE(memif_ul1_ch1_mix)),
SND_SOC_DAPM_MIXER("UL1_CH2", SND_SOC_NOPM, 0, 0,
memif_ul1_ch2_mix, ARRAY_SIZE(memif_ul1_ch2_mix)),
SND_SOC_DAPM_MIXER("UL2_CH1", SND_SOC_NOPM, 0, 0,
memif_ul2_ch1_mix, ARRAY_SIZE(memif_ul2_ch1_mix)),
SND_SOC_DAPM_MIXER("UL2_CH2", SND_SOC_NOPM, 0, 0,
memif_ul2_ch2_mix, ARRAY_SIZE(memif_ul2_ch2_mix)),
SND_SOC_DAPM_MIXER("UL3_CH1", SND_SOC_NOPM, 0, 0,
memif_ul3_ch1_mix, ARRAY_SIZE(memif_ul3_ch1_mix)),
SND_SOC_DAPM_MIXER("UL3_CH2", SND_SOC_NOPM, 0, 0,
memif_ul3_ch2_mix, ARRAY_SIZE(memif_ul3_ch2_mix)),
SND_SOC_DAPM_MIXER("UL_MONO_1_CH1", SND_SOC_NOPM, 0, 0,
memif_ul_mono_1_mix,
ARRAY_SIZE(memif_ul_mono_1_mix)),
SND_SOC_DAPM_MIXER("UL_MONO_2_CH1", SND_SOC_NOPM, 0, 0,
memif_ul_mono_2_mix,
ARRAY_SIZE(memif_ul_mono_2_mix)),
};
static const struct snd_soc_dapm_route mt6797_memif_routes[] = {
/* capture */
{"UL1", NULL, "UL1_CH1"},
{"UL1", NULL, "UL1_CH2"},
{"UL1_CH1", "ADDA_UL_CH1", "ADDA Capture"},
{"UL1_CH2", "ADDA_UL_CH2", "ADDA Capture"},
{"UL2", NULL, "UL2_CH1"},
{"UL2", NULL, "UL2_CH2"},
{"UL2_CH1", "ADDA_UL_CH1", "ADDA Capture"},
{"UL2_CH2", "ADDA_UL_CH2", "ADDA Capture"},
{"UL3", NULL, "UL3_CH1"},
{"UL3", NULL, "UL3_CH2"},
{"UL3_CH1", "ADDA_UL_CH1", "ADDA Capture"},
{"UL3_CH2", "ADDA_UL_CH2", "ADDA Capture"},
{"UL_MONO_1", NULL, "UL_MONO_1_CH1"},
{"UL_MONO_1_CH1", "ADDA_UL_CH1", "ADDA Capture"},
{"UL_MONO_1_CH1", "ADDA_UL_CH2", "ADDA Capture"},
{"UL_MONO_2", NULL, "UL_MONO_2_CH1"},
{"UL_MONO_2_CH1", "ADDA_UL_CH1", "ADDA Capture"},
{"UL_MONO_2_CH1", "ADDA_UL_CH2", "ADDA Capture"},
};
static const struct snd_soc_component_driver mt6797_afe_pcm_dai_component = {
.name = "mt6797-afe-pcm-dai",
};
static const struct mtk_base_memif_data memif_data[MT6797_MEMIF_NUM] = {
[MT6797_MEMIF_DL1] = {
.name = "DL1",
.id = MT6797_MEMIF_DL1,
.reg_ofs_base = AFE_DL1_BASE,
.reg_ofs_cur = AFE_DL1_CUR,
.fs_reg = AFE_DAC_CON1,
.fs_shift = DL1_MODE_SFT,
.fs_maskbit = DL1_MODE_MASK,
.mono_reg = AFE_DAC_CON1,
.mono_shift = DL1_DATA_SFT,
.enable_reg = AFE_DAC_CON0,
.enable_shift = DL1_ON_SFT,
.hd_reg = AFE_MEMIF_HD_MODE,
.hd_shift = DL1_HD_SFT,
.agent_disable_reg = -1,
.msb_reg = -1,
},
[MT6797_MEMIF_DL2] = {
.name = "DL2",
.id = MT6797_MEMIF_DL2,
.reg_ofs_base = AFE_DL2_BASE,
.reg_ofs_cur = AFE_DL2_CUR,
.fs_reg = AFE_DAC_CON1,
.fs_shift = DL2_MODE_SFT,
.fs_maskbit = DL2_MODE_MASK,
.mono_reg = AFE_DAC_CON1,
.mono_shift = DL2_DATA_SFT,
.enable_reg = AFE_DAC_CON0,
.enable_shift = DL2_ON_SFT,
.hd_reg = AFE_MEMIF_HD_MODE,
.hd_shift = DL2_HD_SFT,
.agent_disable_reg = -1,
.msb_reg = -1,
},
[MT6797_MEMIF_DL3] = {
.name = "DL3",
.id = MT6797_MEMIF_DL3,
.reg_ofs_base = AFE_DL3_BASE,
.reg_ofs_cur = AFE_DL3_CUR,
.fs_reg = AFE_DAC_CON0,
.fs_shift = DL3_MODE_SFT,
.fs_maskbit = DL3_MODE_MASK,
.mono_reg = AFE_DAC_CON1,
.mono_shift = DL3_DATA_SFT,
.enable_reg = AFE_DAC_CON0,
.enable_shift = DL3_ON_SFT,
.hd_reg = AFE_MEMIF_HD_MODE,
.hd_shift = DL3_HD_SFT,
.agent_disable_reg = -1,
.msb_reg = -1,
},
[MT6797_MEMIF_VUL] = {
.name = "VUL",
.id = MT6797_MEMIF_VUL,
.reg_ofs_base = AFE_VUL_BASE,
.reg_ofs_cur = AFE_VUL_CUR,
.fs_reg = AFE_DAC_CON1,
.fs_shift = VUL_MODE_SFT,
.fs_maskbit = VUL_MODE_MASK,
.mono_reg = AFE_DAC_CON1,
.mono_shift = VUL_DATA_SFT,
.enable_reg = AFE_DAC_CON0,
.enable_shift = VUL_ON_SFT,
.hd_reg = AFE_MEMIF_HD_MODE,
.hd_shift = VUL_HD_SFT,
.agent_disable_reg = -1,
.msb_reg = -1,
},
[MT6797_MEMIF_AWB] = {
.name = "AWB",
.id = MT6797_MEMIF_AWB,
.reg_ofs_base = AFE_AWB_BASE,
.reg_ofs_cur = AFE_AWB_CUR,
.fs_reg = AFE_DAC_CON1,
.fs_shift = AWB_MODE_SFT,
.fs_maskbit = AWB_MODE_MASK,
.mono_reg = AFE_DAC_CON1,
.mono_shift = AWB_DATA_SFT,
.enable_reg = AFE_DAC_CON0,
.enable_shift = AWB_ON_SFT,
.hd_reg = AFE_MEMIF_HD_MODE,
.hd_shift = AWB_HD_SFT,
.agent_disable_reg = -1,
.msb_reg = -1,
},
[MT6797_MEMIF_VUL12] = {
.name = "VUL12",
.id = MT6797_MEMIF_VUL12,
.reg_ofs_base = AFE_VUL_D2_BASE,
.reg_ofs_cur = AFE_VUL_D2_CUR,
.fs_reg = AFE_DAC_CON0,
.fs_shift = VUL_DATA2_MODE_SFT,
.fs_maskbit = VUL_DATA2_MODE_MASK,
.mono_reg = AFE_DAC_CON0,
.mono_shift = VUL_DATA2_DATA_SFT,
.enable_reg = AFE_DAC_CON0,
.enable_shift = VUL_DATA2_ON_SFT,
.hd_reg = AFE_MEMIF_HD_MODE,
.hd_shift = VUL_DATA2_HD_SFT,
.agent_disable_reg = -1,
.msb_reg = -1,
},
[MT6797_MEMIF_DAI] = {
.name = "DAI",
.id = MT6797_MEMIF_DAI,
.reg_ofs_base = AFE_DAI_BASE,
.reg_ofs_cur = AFE_DAI_CUR,
.fs_reg = AFE_DAC_CON0,
.fs_shift = DAI_MODE_SFT,
.fs_maskbit = DAI_MODE_MASK,
.mono_reg = -1,
.mono_shift = 0,
.enable_reg = AFE_DAC_CON0,
.enable_shift = DAI_ON_SFT,
.hd_reg = AFE_MEMIF_HD_MODE,
.hd_shift = DAI_HD_SFT,
.agent_disable_reg = -1,
.msb_reg = -1,
},
[MT6797_MEMIF_MOD_DAI] = {
.name = "MOD_DAI",
.id = MT6797_MEMIF_MOD_DAI,
.reg_ofs_base = AFE_MOD_DAI_BASE,
.reg_ofs_cur = AFE_MOD_DAI_CUR,
.fs_reg = AFE_DAC_CON1,
.fs_shift = MOD_DAI_MODE_SFT,
.fs_maskbit = MOD_DAI_MODE_MASK,
.mono_reg = -1,
.mono_shift = 0,
.enable_reg = AFE_DAC_CON0,
.enable_shift = MOD_DAI_ON_SFT,
.hd_reg = AFE_MEMIF_HD_MODE,
.hd_shift = MOD_DAI_HD_SFT,
.agent_disable_reg = -1,
.msb_reg = -1,
},
};
static const struct mtk_base_irq_data irq_data[MT6797_IRQ_NUM] = {
[MT6797_IRQ_1] = {
.id = MT6797_IRQ_1,
.irq_cnt_reg = AFE_IRQ_MCU_CNT1,
.irq_cnt_shift = AFE_IRQ_MCU_CNT1_SFT,
.irq_cnt_maskbit = AFE_IRQ_MCU_CNT1_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON,
.irq_fs_shift = IRQ1_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ1_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON,
.irq_en_shift = IRQ1_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ1_MCU_CLR_SFT,
},
[MT6797_IRQ_2] = {
.id = MT6797_IRQ_2,
.irq_cnt_reg = AFE_IRQ_MCU_CNT2,
.irq_cnt_shift = AFE_IRQ_MCU_CNT2_SFT,
.irq_cnt_maskbit = AFE_IRQ_MCU_CNT2_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON,
.irq_fs_shift = IRQ2_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ2_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON,
.irq_en_shift = IRQ2_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ2_MCU_CLR_SFT,
},
[MT6797_IRQ_3] = {
.id = MT6797_IRQ_3,
.irq_cnt_reg = AFE_IRQ_MCU_CNT3,
.irq_cnt_shift = AFE_IRQ_MCU_CNT3_SFT,
.irq_cnt_maskbit = AFE_IRQ_MCU_CNT3_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON,
.irq_fs_shift = IRQ3_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ3_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON,
.irq_en_shift = IRQ3_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ3_MCU_CLR_SFT,
},
[MT6797_IRQ_4] = {
.id = MT6797_IRQ_4,
.irq_cnt_reg = AFE_IRQ_MCU_CNT4,
.irq_cnt_shift = AFE_IRQ_MCU_CNT4_SFT,
.irq_cnt_maskbit = AFE_IRQ_MCU_CNT4_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON,
.irq_fs_shift = IRQ4_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ4_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON,
.irq_en_shift = IRQ4_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ4_MCU_CLR_SFT,
},
[MT6797_IRQ_7] = {
.id = MT6797_IRQ_7,
.irq_cnt_reg = AFE_IRQ_MCU_CNT7,
.irq_cnt_shift = AFE_IRQ_MCU_CNT7_SFT,
.irq_cnt_maskbit = AFE_IRQ_MCU_CNT7_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON,
.irq_fs_shift = IRQ7_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ7_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON,
.irq_en_shift = IRQ7_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ7_MCU_CLR_SFT,
},
};
static const struct regmap_config mt6797_afe_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = AFE_MAX_REGISTER,
};
static irqreturn_t mt6797_afe_irq_handler(int irq_id, void *dev)
{
struct mtk_base_afe *afe = dev;
struct mtk_base_afe_irq *irq;
unsigned int status;
unsigned int mcu_en;
int ret;
int i;
irqreturn_t irq_ret = IRQ_HANDLED;
/* get irq that is sent to MCU */
regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &mcu_en);
ret = regmap_read(afe->regmap, AFE_IRQ_MCU_STATUS, &status);
if (ret || (status & mcu_en) == 0) {
dev_err(afe->dev, "%s(), irq status err, ret %d, status 0x%x, mcu_en 0x%x\n",
__func__, ret, status, mcu_en);
/* only clear IRQ which is sent to MCU */
status = mcu_en & AFE_IRQ_STATUS_BITS;
irq_ret = IRQ_NONE;
goto err_irq;
}
for (i = 0; i < MT6797_MEMIF_NUM; i++) {
struct mtk_base_afe_memif *memif = &afe->memif[i];
if (!memif->substream)
continue;
irq = &afe->irqs[memif->irq_usage];
if (status & (1 << irq->irq_data->irq_en_shift))
snd_pcm_period_elapsed(memif->substream);
}
err_irq:
/* clear irq */
regmap_write(afe->regmap,
AFE_IRQ_MCU_CLR,
status & AFE_IRQ_STATUS_BITS);
return irq_ret;
}
static int mt6797_afe_runtime_suspend(struct device *dev)
{
struct mtk_base_afe *afe = dev_get_drvdata(dev);
unsigned int afe_on_retm;
int retry = 0;
/* disable AFE */
regmap_update_bits(afe->regmap, AFE_DAC_CON0, AFE_ON_MASK_SFT, 0x0);
do {
regmap_read(afe->regmap, AFE_DAC_CON0, &afe_on_retm);
if ((afe_on_retm & AFE_ON_RETM_MASK_SFT) == 0)
break;
udelay(10);
} while (++retry < 100000);
if (retry)
dev_warn(afe->dev, "%s(), retry %d\n", __func__, retry);
/* make sure all irq status are cleared */
regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CLR, 0xffff, 0xffff);
return mt6797_afe_disable_clock(afe);
}
static int mt6797_afe_runtime_resume(struct device *dev)
{
struct mtk_base_afe *afe = dev_get_drvdata(dev);
int ret;
ret = mt6797_afe_enable_clock(afe);
if (ret)
return ret;
/* irq signal to mcu only */
regmap_write(afe->regmap, AFE_IRQ_MCU_EN, AFE_IRQ_MCU_EN_MASK_SFT);
/* force all memif use normal mode */
regmap_update_bits(afe->regmap, AFE_MEMIF_HDALIGN,
0x7ff << 16, 0x7ff << 16);
/* force cpu use normal mode when access sram data */
regmap_update_bits(afe->regmap, AFE_MEMIF_MSB,
CPU_COMPACT_MODE_MASK_SFT, 0);
/* force cpu use 8_24 format when writing 32bit data */
regmap_update_bits(afe->regmap, AFE_MEMIF_MSB,
CPU_HD_ALIGN_MASK_SFT, 0);
/* set all output port to 24bit */
regmap_update_bits(afe->regmap, AFE_CONN_24BIT,
0x3fffffff, 0x3fffffff);
/* enable AFE */
regmap_update_bits(afe->regmap, AFE_DAC_CON0,
AFE_ON_MASK_SFT,
0x1 << AFE_ON_SFT);
return 0;
}
static int mt6797_afe_component_probe(struct snd_soc_component *component)
{
return mtk_afe_add_sub_dai_control(component);
}
static const struct snd_soc_component_driver mt6797_afe_component = {
.name = AFE_PCM_NAME,
.probe = mt6797_afe_component_probe,
.pointer = mtk_afe_pcm_pointer,
.pcm_construct = mtk_afe_pcm_new,
};
static int mt6797_dai_memif_register(struct mtk_base_afe *afe)
{
struct mtk_base_afe_dai *dai;
dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
if (!dai)
return -ENOMEM;
list_add(&dai->list, &afe->sub_dais);
dai->dai_drivers = mt6797_memif_dai_driver;
dai->num_dai_drivers = ARRAY_SIZE(mt6797_memif_dai_driver);
dai->dapm_widgets = mt6797_memif_widgets;
dai->num_dapm_widgets = ARRAY_SIZE(mt6797_memif_widgets);
dai->dapm_routes = mt6797_memif_routes;
dai->num_dapm_routes = ARRAY_SIZE(mt6797_memif_routes);
return 0;
}
typedef int (*dai_register_cb)(struct mtk_base_afe *);
static const dai_register_cb dai_register_cbs[] = {
mt6797_dai_adda_register,
mt6797_dai_pcm_register,
mt6797_dai_hostless_register,
mt6797_dai_memif_register,
};
static int mt6797_afe_pcm_dev_probe(struct platform_device *pdev)
{
struct mtk_base_afe *afe;
struct mt6797_afe_private *afe_priv;
struct device *dev;
int i, irq_id, ret;
afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
if (!afe)
return -ENOMEM;
afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),
GFP_KERNEL);
if (!afe->platform_priv)
return -ENOMEM;
afe_priv = afe->platform_priv;
afe->dev = &pdev->dev;
dev = afe->dev;
/* initial audio related clock */
ret = mt6797_init_clock(afe);
if (ret) {
dev_err(dev, "init clock error\n");
return ret;
}
/* regmap init */
afe->base_addr = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(afe->base_addr))
return PTR_ERR(afe->base_addr);
afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr,
&mt6797_afe_regmap_config);
if (IS_ERR(afe->regmap))
return PTR_ERR(afe->regmap);
/* init memif */
afe->memif_size = MT6797_MEMIF_NUM;
afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),
GFP_KERNEL);
if (!afe->memif)
return -ENOMEM;
for (i = 0; i < afe->memif_size; i++) {
afe->memif[i].data = &memif_data[i];
afe->memif[i].irq_usage = -1;
}
mutex_init(&afe->irq_alloc_lock);
/* irq initialize */
afe->irqs_size = MT6797_IRQ_NUM;
afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
GFP_KERNEL);
if (!afe->irqs)
return -ENOMEM;
for (i = 0; i < afe->irqs_size; i++)
afe->irqs[i].irq_data = &irq_data[i];
/* request irq */
irq_id = platform_get_irq(pdev, 0);
if (irq_id < 0)
return irq_id;
ret = devm_request_irq(dev, irq_id, mt6797_afe_irq_handler,
IRQF_TRIGGER_NONE, "asys-isr", (void *)afe);
if (ret) {
dev_err(dev, "could not request_irq for asys-isr\n");
return ret;
}
/* init sub_dais */
INIT_LIST_HEAD(&afe->sub_dais);
for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) {
ret = dai_register_cbs[i](afe);
if (ret) {
dev_warn(afe->dev, "dai register i %d fail, ret %d\n",
i, ret);
return ret;
}
}
/* init dai_driver and component_driver */
ret = mtk_afe_combine_sub_dai(afe);
if (ret) {
dev_warn(afe->dev, "mtk_afe_combine_sub_dai fail, ret %d\n",
ret);
return ret;
}
afe->mtk_afe_hardware = &mt6797_afe_hardware;
afe->memif_fs = mt6797_memif_fs;
afe->irq_fs = mt6797_irq_fs;
afe->runtime_resume = mt6797_afe_runtime_resume;
afe->runtime_suspend = mt6797_afe_runtime_suspend;
platform_set_drvdata(pdev, afe);
pm_runtime_enable(dev);
if (!pm_runtime_enabled(dev))
goto err_pm_disable;
pm_runtime_get_sync(&pdev->dev);
/* register component */
ret = devm_snd_soc_register_component(dev, &mt6797_afe_component,
NULL, 0);
if (ret) {
dev_warn(dev, "err_platform\n");
goto err_pm_disable;
}
ret = devm_snd_soc_register_component(afe->dev,
&mt6797_afe_pcm_dai_component,
afe->dai_drivers,
afe->num_dai_drivers);
if (ret) {
dev_warn(dev, "err_dai_component\n");
goto err_pm_disable;
}
return 0;
err_pm_disable:
pm_runtime_disable(dev);
return ret;
}
static void mt6797_afe_pcm_dev_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
if (!pm_runtime_status_suspended(&pdev->dev))
mt6797_afe_runtime_suspend(&pdev->dev);
pm_runtime_put_sync(&pdev->dev);
}
static const struct of_device_id mt6797_afe_pcm_dt_match[] = {
{ .compatible = "mediatek,mt6797-audio", },
{},
};
MODULE_DEVICE_TABLE(of, mt6797_afe_pcm_dt_match);
static const struct dev_pm_ops mt6797_afe_pm_ops = {
SET_RUNTIME_PM_OPS(mt6797_afe_runtime_suspend,
mt6797_afe_runtime_resume, NULL)
};
static struct platform_driver mt6797_afe_pcm_driver = {
.driver = {
.name = "mt6797-audio",
.of_match_table = mt6797_afe_pcm_dt_match,
.pm = &mt6797_afe_pm_ops,
},
.probe = mt6797_afe_pcm_dev_probe,
.remove_new = mt6797_afe_pcm_dev_remove,
};
module_platform_driver(mt6797_afe_pcm_driver);
MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 6797");
MODULE_AUTHOR("KaiChieh Chuang <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/mediatek/mt6797/mt6797-afe-pcm.c |
// SPDX-License-Identifier: GPL-2.0
//
// MediaTek ALSA SoC Audio DAI ADDA Control
//
// Copyright (c) 2018 MediaTek Inc.
// Author: KaiChieh Chuang <[email protected]>
#include <linux/regmap.h>
#include <linux/delay.h>
#include "mt6797-afe-common.h"
#include "mt6797-interconnection.h"
#include "mt6797-reg.h"
enum {
MTK_AFE_ADDA_DL_RATE_8K = 0,
MTK_AFE_ADDA_DL_RATE_11K = 1,
MTK_AFE_ADDA_DL_RATE_12K = 2,
MTK_AFE_ADDA_DL_RATE_16K = 3,
MTK_AFE_ADDA_DL_RATE_22K = 4,
MTK_AFE_ADDA_DL_RATE_24K = 5,
MTK_AFE_ADDA_DL_RATE_32K = 6,
MTK_AFE_ADDA_DL_RATE_44K = 7,
MTK_AFE_ADDA_DL_RATE_48K = 8,
MTK_AFE_ADDA_DL_RATE_96K = 9,
MTK_AFE_ADDA_DL_RATE_192K = 10,
};
enum {
MTK_AFE_ADDA_UL_RATE_8K = 0,
MTK_AFE_ADDA_UL_RATE_16K = 1,
MTK_AFE_ADDA_UL_RATE_32K = 2,
MTK_AFE_ADDA_UL_RATE_48K = 3,
MTK_AFE_ADDA_UL_RATE_96K = 4,
MTK_AFE_ADDA_UL_RATE_192K = 5,
MTK_AFE_ADDA_UL_RATE_48K_HD = 6,
};
static unsigned int adda_dl_rate_transform(struct mtk_base_afe *afe,
unsigned int rate)
{
switch (rate) {
case 8000:
return MTK_AFE_ADDA_DL_RATE_8K;
case 11025:
return MTK_AFE_ADDA_DL_RATE_11K;
case 12000:
return MTK_AFE_ADDA_DL_RATE_12K;
case 16000:
return MTK_AFE_ADDA_DL_RATE_16K;
case 22050:
return MTK_AFE_ADDA_DL_RATE_22K;
case 24000:
return MTK_AFE_ADDA_DL_RATE_24K;
case 32000:
return MTK_AFE_ADDA_DL_RATE_32K;
case 44100:
return MTK_AFE_ADDA_DL_RATE_44K;
case 48000:
return MTK_AFE_ADDA_DL_RATE_48K;
case 96000:
return MTK_AFE_ADDA_DL_RATE_96K;
case 192000:
return MTK_AFE_ADDA_DL_RATE_192K;
default:
dev_warn(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
__func__, rate);
return MTK_AFE_ADDA_DL_RATE_48K;
}
}
static unsigned int adda_ul_rate_transform(struct mtk_base_afe *afe,
unsigned int rate)
{
switch (rate) {
case 8000:
return MTK_AFE_ADDA_UL_RATE_8K;
case 16000:
return MTK_AFE_ADDA_UL_RATE_16K;
case 32000:
return MTK_AFE_ADDA_UL_RATE_32K;
case 48000:
return MTK_AFE_ADDA_UL_RATE_48K;
case 96000:
return MTK_AFE_ADDA_UL_RATE_96K;
case 192000:
return MTK_AFE_ADDA_UL_RATE_192K;
default:
dev_warn(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
__func__, rate);
return MTK_AFE_ADDA_UL_RATE_48K;
}
}
/* dai component */
static const struct snd_kcontrol_new mtk_adda_dl_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN3, I_DL1_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN3, I_DL2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN3, I_DL3_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN3,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN3,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN3,
I_PCM_1_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN3,
I_PCM_2_CAP_CH1, 1, 0),
};
static const struct snd_kcontrol_new mtk_adda_dl_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN4, I_DL1_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN4, I_DL1_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN4, I_DL2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN4, I_DL2_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN4, I_DL3_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN4, I_DL3_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN4,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN4,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN4,
I_PCM_1_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN4,
I_PCM_2_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN4,
I_PCM_1_CAP_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN4,
I_PCM_2_CAP_CH2, 1, 0),
};
static int mtk_adda_ul_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
__func__, w->name, event);
switch (event) {
case SND_SOC_DAPM_POST_PMD:
/* should delayed 1/fs(smallest is 8k) = 125us before afe off */
usleep_range(125, 135);
break;
default:
break;
}
return 0;
}
enum {
SUPPLY_SEQ_AUD_TOP_PDN,
SUPPLY_SEQ_ADDA_AFE_ON,
SUPPLY_SEQ_ADDA_DL_ON,
SUPPLY_SEQ_ADDA_UL_ON,
};
static const struct snd_soc_dapm_widget mtk_dai_adda_widgets[] = {
/* adda */
SND_SOC_DAPM_MIXER("ADDA_DL_CH1", SND_SOC_NOPM, 0, 0,
mtk_adda_dl_ch1_mix,
ARRAY_SIZE(mtk_adda_dl_ch1_mix)),
SND_SOC_DAPM_MIXER("ADDA_DL_CH2", SND_SOC_NOPM, 0, 0,
mtk_adda_dl_ch2_mix,
ARRAY_SIZE(mtk_adda_dl_ch2_mix)),
SND_SOC_DAPM_SUPPLY_S("ADDA Enable", SUPPLY_SEQ_ADDA_AFE_ON,
AFE_ADDA_UL_DL_CON0, ADDA_AFE_ON_SFT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ADDA Playback Enable", SUPPLY_SEQ_ADDA_DL_ON,
AFE_ADDA_DL_SRC2_CON0,
DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ADDA Capture Enable", SUPPLY_SEQ_ADDA_UL_ON,
AFE_ADDA_UL_SRC_CON0,
UL_SRC_ON_TMP_CTL_SFT, 0,
mtk_adda_ul_event,
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("aud_dac_clk", SUPPLY_SEQ_AUD_TOP_PDN,
AUDIO_TOP_CON0, PDN_DAC_SFT, 1,
NULL, 0),
SND_SOC_DAPM_SUPPLY_S("aud_dac_predis_clk", SUPPLY_SEQ_AUD_TOP_PDN,
AUDIO_TOP_CON0, PDN_DAC_PREDIS_SFT, 1,
NULL, 0),
SND_SOC_DAPM_SUPPLY_S("aud_adc_clk", SUPPLY_SEQ_AUD_TOP_PDN,
AUDIO_TOP_CON0, PDN_ADC_SFT, 1,
NULL, 0),
SND_SOC_DAPM_CLOCK_SUPPLY("mtkaif_26m_clk"),
};
static const struct snd_soc_dapm_route mtk_dai_adda_routes[] = {
/* playback */
{"ADDA_DL_CH1", "DL1_CH1", "DL1"},
{"ADDA_DL_CH2", "DL1_CH1", "DL1"},
{"ADDA_DL_CH2", "DL1_CH2", "DL1"},
{"ADDA_DL_CH1", "DL2_CH1", "DL2"},
{"ADDA_DL_CH2", "DL2_CH1", "DL2"},
{"ADDA_DL_CH2", "DL2_CH2", "DL2"},
{"ADDA_DL_CH1", "DL3_CH1", "DL3"},
{"ADDA_DL_CH2", "DL3_CH1", "DL3"},
{"ADDA_DL_CH2", "DL3_CH2", "DL3"},
{"ADDA Playback", NULL, "ADDA_DL_CH1"},
{"ADDA Playback", NULL, "ADDA_DL_CH2"},
/* adda enable */
{"ADDA Playback", NULL, "ADDA Enable"},
{"ADDA Playback", NULL, "ADDA Playback Enable"},
{"ADDA Capture", NULL, "ADDA Enable"},
{"ADDA Capture", NULL, "ADDA Capture Enable"},
/* clk */
{"ADDA Playback", NULL, "mtkaif_26m_clk"},
{"ADDA Playback", NULL, "aud_dac_clk"},
{"ADDA Playback", NULL, "aud_dac_predis_clk"},
{"ADDA Capture", NULL, "mtkaif_26m_clk"},
{"ADDA Capture", NULL, "aud_adc_clk"},
};
/* dai ops */
static int mtk_dai_adda_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
unsigned int rate = params_rate(params);
dev_dbg(afe->dev, "%s(), id %d, stream %d, rate %d\n",
__func__, dai->id, substream->stream, rate);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
unsigned int dl_src2_con0 = 0;
unsigned int dl_src2_con1 = 0;
/* clean predistortion */
regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON0, 0);
regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON1, 0);
/* set input sampling rate */
dl_src2_con0 = adda_dl_rate_transform(afe, rate) << 28;
/* set output mode */
switch (rate) {
case 192000:
dl_src2_con0 |= (0x1 << 24); /* UP_SAMPLING_RATE_X2 */
dl_src2_con0 |= 1 << 14;
break;
case 96000:
dl_src2_con0 |= (0x2 << 24); /* UP_SAMPLING_RATE_X4 */
dl_src2_con0 |= 1 << 14;
break;
default:
dl_src2_con0 |= (0x3 << 24); /* UP_SAMPLING_RATE_X8 */
break;
}
/* turn off mute function */
dl_src2_con0 |= (0x03 << 11);
/* set voice input data if input sample rate is 8k or 16k */
if (rate == 8000 || rate == 16000)
dl_src2_con0 |= 0x01 << 5;
if (rate < 96000) {
/* SA suggest apply -0.3db to audio/speech path */
dl_src2_con1 = 0xf74f0000;
} else {
/* SA suggest apply -0.3db to audio/speech path
* with DL gain set to half,
* 0xFFFF = 0dB -> 0x8000 = 0dB when 96k, 192k
*/
dl_src2_con1 = 0x7ba70000;
}
/* turn on down-link gain */
dl_src2_con0 = dl_src2_con0 | (0x01 << 1);
regmap_write(afe->regmap, AFE_ADDA_DL_SRC2_CON0, dl_src2_con0);
regmap_write(afe->regmap, AFE_ADDA_DL_SRC2_CON1, dl_src2_con1);
} else {
unsigned int voice_mode = 0;
unsigned int ul_src_con0 = 0; /* default value */
/* Using Internal ADC */
regmap_update_bits(afe->regmap,
AFE_ADDA_TOP_CON0,
0x1 << 0,
0x0 << 0);
voice_mode = adda_ul_rate_transform(afe, rate);
ul_src_con0 |= (voice_mode << 17) & (0x7 << 17);
/* up8x txif sat on */
regmap_write(afe->regmap, AFE_ADDA_NEWIF_CFG0, 0x03F87201);
if (rate >= 96000) { /* hires */
/* use hires format [1 0 23] */
regmap_update_bits(afe->regmap,
AFE_ADDA_NEWIF_CFG0,
0x1 << 5,
0x1 << 5);
regmap_update_bits(afe->regmap,
AFE_ADDA_NEWIF_CFG2,
0xf << 28,
voice_mode << 28);
} else { /* normal 8~48k */
/* use fixed 260k anc path */
regmap_update_bits(afe->regmap,
AFE_ADDA_NEWIF_CFG2,
0xf << 28,
8 << 28);
/* ul_use_cic_out */
ul_src_con0 |= 0x1 << 20;
}
regmap_update_bits(afe->regmap,
AFE_ADDA_NEWIF_CFG2,
0xf << 28,
8 << 28);
regmap_update_bits(afe->regmap,
AFE_ADDA_UL_SRC_CON0,
0xfffffffe,
ul_src_con0);
}
return 0;
}
static const struct snd_soc_dai_ops mtk_dai_adda_ops = {
.hw_params = mtk_dai_adda_hw_params,
};
/* dai driver */
#define MTK_ADDA_PLAYBACK_RATES (SNDRV_PCM_RATE_8000_48000 |\
SNDRV_PCM_RATE_96000 |\
SNDRV_PCM_RATE_192000)
#define MTK_ADDA_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 |\
SNDRV_PCM_RATE_48000 |\
SNDRV_PCM_RATE_96000 |\
SNDRV_PCM_RATE_192000)
#define MTK_ADDA_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver mtk_dai_adda_driver[] = {
{
.name = "ADDA",
.id = MT6797_DAI_ADDA,
.playback = {
.stream_name = "ADDA Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_ADDA_PLAYBACK_RATES,
.formats = MTK_ADDA_FORMATS,
},
.capture = {
.stream_name = "ADDA Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_ADDA_CAPTURE_RATES,
.formats = MTK_ADDA_FORMATS,
},
.ops = &mtk_dai_adda_ops,
},
};
int mt6797_dai_adda_register(struct mtk_base_afe *afe)
{
struct mtk_base_afe_dai *dai;
dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
if (!dai)
return -ENOMEM;
list_add(&dai->list, &afe->sub_dais);
dai->dai_drivers = mtk_dai_adda_driver;
dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_adda_driver);
dai->dapm_widgets = mtk_dai_adda_widgets;
dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_adda_widgets);
dai->dapm_routes = mtk_dai_adda_routes;
dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_adda_routes);
return 0;
}
| linux-master | sound/soc/mediatek/mt6797/mt6797-dai-adda.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Mediatek 8173 ALSA SoC AFE platform driver
*
* Copyright (c) 2015 MediaTek Inc.
* Author: Koro Chen <[email protected]>
* Sascha Hauer <[email protected]>
* Hidalgo Huang <[email protected]>
* Ir Lian <[email protected]>
*/
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/dma-mapping.h>
#include <linux/pm_runtime.h>
#include <sound/soc.h>
#include "mt8173-afe-common.h"
#include "../common/mtk-base-afe.h"
#include "../common/mtk-afe-platform-driver.h"
#include "../common/mtk-afe-fe-dai.h"
/*****************************************************************************
* R E G I S T E R D E F I N I T I O N
*****************************************************************************/
#define AUDIO_TOP_CON0 0x0000
#define AUDIO_TOP_CON1 0x0004
#define AFE_DAC_CON0 0x0010
#define AFE_DAC_CON1 0x0014
#define AFE_I2S_CON1 0x0034
#define AFE_I2S_CON2 0x0038
#define AFE_CONN_24BIT 0x006c
#define AFE_MEMIF_MSB 0x00cc
#define AFE_CONN1 0x0024
#define AFE_CONN2 0x0028
#define AFE_CONN3 0x002c
#define AFE_CONN7 0x0460
#define AFE_CONN8 0x0464
#define AFE_HDMI_CONN0 0x0390
/* Memory interface */
#define AFE_DL1_BASE 0x0040
#define AFE_DL1_CUR 0x0044
#define AFE_DL1_END 0x0048
#define AFE_DL2_BASE 0x0050
#define AFE_DL2_CUR 0x0054
#define AFE_AWB_BASE 0x0070
#define AFE_AWB_CUR 0x007c
#define AFE_VUL_BASE 0x0080
#define AFE_VUL_CUR 0x008c
#define AFE_VUL_END 0x0088
#define AFE_DAI_BASE 0x0090
#define AFE_DAI_CUR 0x009c
#define AFE_MOD_PCM_BASE 0x0330
#define AFE_MOD_PCM_CUR 0x033c
#define AFE_HDMI_OUT_BASE 0x0374
#define AFE_HDMI_OUT_CUR 0x0378
#define AFE_HDMI_OUT_END 0x037c
#define AFE_ADDA_TOP_CON0 0x0120
#define AFE_ADDA2_TOP_CON0 0x0600
#define AFE_HDMI_OUT_CON0 0x0370
#define AFE_IRQ_MCU_CON 0x03a0
#define AFE_IRQ_STATUS 0x03a4
#define AFE_IRQ_CLR 0x03a8
#define AFE_IRQ_CNT1 0x03ac
#define AFE_IRQ_CNT2 0x03b0
#define AFE_IRQ_MCU_EN 0x03b4
#define AFE_IRQ_CNT5 0x03bc
#define AFE_IRQ_CNT7 0x03dc
#define AFE_TDM_CON1 0x0548
#define AFE_TDM_CON2 0x054c
#define AFE_IRQ_STATUS_BITS 0xff
/* AUDIO_TOP_CON0 (0x0000) */
#define AUD_TCON0_PDN_SPDF (0x1 << 21)
#define AUD_TCON0_PDN_HDMI (0x1 << 20)
#define AUD_TCON0_PDN_24M (0x1 << 9)
#define AUD_TCON0_PDN_22M (0x1 << 8)
#define AUD_TCON0_PDN_AFE (0x1 << 2)
/* AFE_I2S_CON1 (0x0034) */
#define AFE_I2S_CON1_LOW_JITTER_CLK (0x1 << 12)
#define AFE_I2S_CON1_RATE(x) (((x) & 0xf) << 8)
#define AFE_I2S_CON1_FORMAT_I2S (0x1 << 3)
#define AFE_I2S_CON1_EN (0x1 << 0)
/* AFE_I2S_CON2 (0x0038) */
#define AFE_I2S_CON2_LOW_JITTER_CLK (0x1 << 12)
#define AFE_I2S_CON2_RATE(x) (((x) & 0xf) << 8)
#define AFE_I2S_CON2_FORMAT_I2S (0x1 << 3)
#define AFE_I2S_CON2_EN (0x1 << 0)
/* AFE_CONN_24BIT (0x006c) */
#define AFE_CONN_24BIT_O04 (0x1 << 4)
#define AFE_CONN_24BIT_O03 (0x1 << 3)
/* AFE_HDMI_CONN0 (0x0390) */
#define AFE_HDMI_CONN0_O37_I37 (0x7 << 21)
#define AFE_HDMI_CONN0_O36_I36 (0x6 << 18)
#define AFE_HDMI_CONN0_O35_I33 (0x3 << 15)
#define AFE_HDMI_CONN0_O34_I32 (0x2 << 12)
#define AFE_HDMI_CONN0_O33_I35 (0x5 << 9)
#define AFE_HDMI_CONN0_O32_I34 (0x4 << 6)
#define AFE_HDMI_CONN0_O31_I31 (0x1 << 3)
#define AFE_HDMI_CONN0_O30_I30 (0x0 << 0)
/* AFE_TDM_CON1 (0x0548) */
#define AFE_TDM_CON1_LRCK_WIDTH(x) (((x) - 1) << 24)
#define AFE_TDM_CON1_32_BCK_CYCLES (0x2 << 12)
#define AFE_TDM_CON1_WLEN_32BIT (0x2 << 8)
#define AFE_TDM_CON1_MSB_ALIGNED (0x1 << 4)
#define AFE_TDM_CON1_1_BCK_DELAY (0x1 << 3)
#define AFE_TDM_CON1_LRCK_INV (0x1 << 2)
#define AFE_TDM_CON1_BCK_INV (0x1 << 1)
#define AFE_TDM_CON1_EN (0x1 << 0)
enum afe_tdm_ch_start {
AFE_TDM_CH_START_O30_O31 = 0,
AFE_TDM_CH_START_O32_O33,
AFE_TDM_CH_START_O34_O35,
AFE_TDM_CH_START_O36_O37,
AFE_TDM_CH_ZERO,
};
static const unsigned int mt8173_afe_backup_list[] = {
AUDIO_TOP_CON0,
AFE_CONN1,
AFE_CONN2,
AFE_CONN7,
AFE_CONN8,
AFE_DAC_CON1,
AFE_DL1_BASE,
AFE_DL1_END,
AFE_VUL_BASE,
AFE_VUL_END,
AFE_HDMI_OUT_BASE,
AFE_HDMI_OUT_END,
AFE_HDMI_CONN0,
AFE_DAC_CON0,
};
struct mt8173_afe_private {
struct clk *clocks[MT8173_CLK_NUM];
};
static const struct snd_pcm_hardware mt8173_afe_hardware = {
.info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_MMAP_VALID),
.buffer_bytes_max = 256 * 1024,
.period_bytes_min = 512,
.period_bytes_max = 128 * 1024,
.periods_min = 2,
.periods_max = 256,
.fifo_size = 0,
};
struct mt8173_afe_rate {
unsigned int rate;
unsigned int regvalue;
};
static const struct mt8173_afe_rate mt8173_afe_i2s_rates[] = {
{ .rate = 8000, .regvalue = 0 },
{ .rate = 11025, .regvalue = 1 },
{ .rate = 12000, .regvalue = 2 },
{ .rate = 16000, .regvalue = 4 },
{ .rate = 22050, .regvalue = 5 },
{ .rate = 24000, .regvalue = 6 },
{ .rate = 32000, .regvalue = 8 },
{ .rate = 44100, .regvalue = 9 },
{ .rate = 48000, .regvalue = 10 },
{ .rate = 88000, .regvalue = 11 },
{ .rate = 96000, .regvalue = 12 },
{ .rate = 174000, .regvalue = 13 },
{ .rate = 192000, .regvalue = 14 },
};
static int mt8173_afe_i2s_fs(unsigned int sample_rate)
{
int i;
for (i = 0; i < ARRAY_SIZE(mt8173_afe_i2s_rates); i++)
if (mt8173_afe_i2s_rates[i].rate == sample_rate)
return mt8173_afe_i2s_rates[i].regvalue;
return -EINVAL;
}
static int mt8173_afe_set_i2s(struct mtk_base_afe *afe, unsigned int rate)
{
unsigned int val;
int fs = mt8173_afe_i2s_fs(rate);
if (fs < 0)
return -EINVAL;
/* from external ADC */
regmap_update_bits(afe->regmap, AFE_ADDA_TOP_CON0, 0x1, 0x1);
regmap_update_bits(afe->regmap, AFE_ADDA2_TOP_CON0, 0x1, 0x1);
/* set input */
val = AFE_I2S_CON2_LOW_JITTER_CLK |
AFE_I2S_CON2_RATE(fs) |
AFE_I2S_CON2_FORMAT_I2S;
regmap_update_bits(afe->regmap, AFE_I2S_CON2, ~AFE_I2S_CON2_EN, val);
/* set output */
val = AFE_I2S_CON1_LOW_JITTER_CLK |
AFE_I2S_CON1_RATE(fs) |
AFE_I2S_CON1_FORMAT_I2S;
regmap_update_bits(afe->regmap, AFE_I2S_CON1, ~AFE_I2S_CON1_EN, val);
return 0;
}
static void mt8173_afe_set_i2s_enable(struct mtk_base_afe *afe, bool enable)
{
unsigned int val;
regmap_read(afe->regmap, AFE_I2S_CON2, &val);
if (!!(val & AFE_I2S_CON2_EN) == enable)
return;
/* input */
regmap_update_bits(afe->regmap, AFE_I2S_CON2, 0x1, enable);
/* output */
regmap_update_bits(afe->regmap, AFE_I2S_CON1, 0x1, enable);
}
static int mt8173_afe_dais_enable_clks(struct mtk_base_afe *afe,
struct clk *m_ck, struct clk *b_ck)
{
int ret;
if (m_ck) {
ret = clk_prepare_enable(m_ck);
if (ret) {
dev_err(afe->dev, "Failed to enable m_ck\n");
return ret;
}
}
if (b_ck) {
ret = clk_prepare_enable(b_ck);
if (ret) {
dev_err(afe->dev, "Failed to enable b_ck\n");
return ret;
}
}
return 0;
}
static int mt8173_afe_dais_set_clks(struct mtk_base_afe *afe,
struct clk *m_ck, unsigned int mck_rate,
struct clk *b_ck, unsigned int bck_rate)
{
int ret;
if (m_ck) {
ret = clk_set_rate(m_ck, mck_rate);
if (ret) {
dev_err(afe->dev, "Failed to set m_ck rate\n");
return ret;
}
}
if (b_ck) {
ret = clk_set_rate(b_ck, bck_rate);
if (ret) {
dev_err(afe->dev, "Failed to set b_ck rate\n");
return ret;
}
}
return 0;
}
static void mt8173_afe_dais_disable_clks(struct mtk_base_afe *afe,
struct clk *m_ck, struct clk *b_ck)
{
clk_disable_unprepare(m_ck);
clk_disable_unprepare(b_ck);
}
static int mt8173_afe_i2s_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
if (snd_soc_dai_active(dai))
return 0;
regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M, 0);
return 0;
}
static void mt8173_afe_i2s_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
if (snd_soc_dai_active(dai))
return;
mt8173_afe_set_i2s_enable(afe, false);
regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M,
AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M);
}
static int mt8173_afe_i2s_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_pcm_runtime * const runtime = substream->runtime;
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8173_afe_private *afe_priv = afe->platform_priv;
int ret;
mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S1_M],
runtime->rate * 256, NULL, 0);
mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S2_M],
runtime->rate * 256, NULL, 0);
/* config I2S */
ret = mt8173_afe_set_i2s(afe, substream->runtime->rate);
if (ret)
return ret;
mt8173_afe_set_i2s_enable(afe, true);
return 0;
}
static int mt8173_afe_hdmi_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8173_afe_private *afe_priv = afe->platform_priv;
if (snd_soc_dai_active(dai))
return 0;
mt8173_afe_dais_enable_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M],
afe_priv->clocks[MT8173_CLK_I2S3_B]);
return 0;
}
static void mt8173_afe_hdmi_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8173_afe_private *afe_priv = afe->platform_priv;
if (snd_soc_dai_active(dai))
return;
mt8173_afe_dais_disable_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M],
afe_priv->clocks[MT8173_CLK_I2S3_B]);
}
static int mt8173_afe_hdmi_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_pcm_runtime * const runtime = substream->runtime;
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8173_afe_private *afe_priv = afe->platform_priv;
unsigned int val;
mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M],
runtime->rate * 128,
afe_priv->clocks[MT8173_CLK_I2S3_B],
runtime->rate * runtime->channels * 32);
val = AFE_TDM_CON1_BCK_INV |
AFE_TDM_CON1_LRCK_INV |
AFE_TDM_CON1_1_BCK_DELAY |
AFE_TDM_CON1_MSB_ALIGNED | /* I2S mode */
AFE_TDM_CON1_WLEN_32BIT |
AFE_TDM_CON1_32_BCK_CYCLES |
AFE_TDM_CON1_LRCK_WIDTH(32);
regmap_update_bits(afe->regmap, AFE_TDM_CON1, ~AFE_TDM_CON1_EN, val);
/* set tdm2 config */
switch (runtime->channels) {
case 1:
case 2:
val = AFE_TDM_CH_START_O30_O31;
val |= (AFE_TDM_CH_ZERO << 4);
val |= (AFE_TDM_CH_ZERO << 8);
val |= (AFE_TDM_CH_ZERO << 12);
break;
case 3:
case 4:
val = AFE_TDM_CH_START_O30_O31;
val |= (AFE_TDM_CH_START_O32_O33 << 4);
val |= (AFE_TDM_CH_ZERO << 8);
val |= (AFE_TDM_CH_ZERO << 12);
break;
case 5:
case 6:
val = AFE_TDM_CH_START_O30_O31;
val |= (AFE_TDM_CH_START_O32_O33 << 4);
val |= (AFE_TDM_CH_START_O34_O35 << 8);
val |= (AFE_TDM_CH_ZERO << 12);
break;
case 7:
case 8:
val = AFE_TDM_CH_START_O30_O31;
val |= (AFE_TDM_CH_START_O32_O33 << 4);
val |= (AFE_TDM_CH_START_O34_O35 << 8);
val |= (AFE_TDM_CH_START_O36_O37 << 12);
break;
default:
val = 0;
}
regmap_update_bits(afe->regmap, AFE_TDM_CON2, 0x0000ffff, val);
regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0,
0x000000f0, runtime->channels << 4);
return 0;
}
static int mt8173_afe_hdmi_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
dev_info(afe->dev, "%s cmd=%d %s\n", __func__, cmd, dai->name);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF, 0);
/* set connections: O30~O37: L/R/LS/RS/C/LFE/CH7/CH8 */
regmap_write(afe->regmap, AFE_HDMI_CONN0,
AFE_HDMI_CONN0_O30_I30 |
AFE_HDMI_CONN0_O31_I31 |
AFE_HDMI_CONN0_O32_I34 |
AFE_HDMI_CONN0_O33_I35 |
AFE_HDMI_CONN0_O34_I32 |
AFE_HDMI_CONN0_O35_I33 |
AFE_HDMI_CONN0_O36_I36 |
AFE_HDMI_CONN0_O37_I37);
/* enable Out control */
regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0, 0x1, 0x1);
/* enable tdm */
regmap_update_bits(afe->regmap, AFE_TDM_CON1, 0x1, 0x1);
return 0;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
/* disable tdm */
regmap_update_bits(afe->regmap, AFE_TDM_CON1, 0x1, 0);
/* disable Out control */
regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0, 0x1, 0);
regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF,
AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF);
return 0;
default:
return -EINVAL;
}
}
static int mt8173_memif_fs(struct snd_pcm_substream *substream,
unsigned int rate)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
struct mtk_base_afe_memif *memif = &afe->memif[asoc_rtd_to_cpu(rtd, 0)->id];
int fs;
if (memif->data->id == MT8173_AFE_MEMIF_DAI ||
memif->data->id == MT8173_AFE_MEMIF_MOD_DAI) {
switch (rate) {
case 8000:
fs = 0;
break;
case 16000:
fs = 1;
break;
case 32000:
fs = 2;
break;
default:
return -EINVAL;
}
} else {
fs = mt8173_afe_i2s_fs(rate);
}
return fs;
}
static int mt8173_irq_fs(struct snd_pcm_substream *substream, unsigned int rate)
{
return mt8173_afe_i2s_fs(rate);
}
/* BE DAIs */
static const struct snd_soc_dai_ops mt8173_afe_i2s_ops = {
.startup = mt8173_afe_i2s_startup,
.shutdown = mt8173_afe_i2s_shutdown,
.prepare = mt8173_afe_i2s_prepare,
};
static const struct snd_soc_dai_ops mt8173_afe_hdmi_ops = {
.startup = mt8173_afe_hdmi_startup,
.shutdown = mt8173_afe_hdmi_shutdown,
.prepare = mt8173_afe_hdmi_prepare,
.trigger = mt8173_afe_hdmi_trigger,
};
static struct snd_soc_dai_driver mt8173_afe_pcm_dais[] = {
/* FE DAIs: memory intefaces to CPU */
{
.name = "DL1", /* downlink 1 */
.id = MT8173_AFE_MEMIF_DL1,
.playback = {
.stream_name = "DL1",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.ops = &mtk_afe_fe_ops,
}, {
.name = "VUL", /* voice uplink */
.id = MT8173_AFE_MEMIF_VUL,
.capture = {
.stream_name = "VUL",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.ops = &mtk_afe_fe_ops,
}, {
/* BE DAIs */
.name = "I2S",
.id = MT8173_AFE_IO_I2S,
.playback = {
.stream_name = "I2S Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.capture = {
.stream_name = "I2S Capture",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.ops = &mt8173_afe_i2s_ops,
.symmetric_rate = 1,
},
};
static struct snd_soc_dai_driver mt8173_afe_hdmi_dais[] = {
/* FE DAIs */
{
.name = "HDMI",
.id = MT8173_AFE_MEMIF_HDMI,
.playback = {
.stream_name = "HDMI",
.channels_min = 2,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.ops = &mtk_afe_fe_ops,
}, {
/* BE DAIs */
.name = "HDMIO",
.id = MT8173_AFE_IO_HDMI,
.playback = {
.stream_name = "HDMIO Playback",
.channels_min = 2,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.ops = &mt8173_afe_hdmi_ops,
},
};
static const struct snd_kcontrol_new mt8173_afe_o03_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I05 Switch", AFE_CONN1, 21, 1, 0),
};
static const struct snd_kcontrol_new mt8173_afe_o04_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I06 Switch", AFE_CONN2, 6, 1, 0),
};
static const struct snd_kcontrol_new mt8173_afe_o09_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I03 Switch", AFE_CONN3, 0, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I17 Switch", AFE_CONN7, 30, 1, 0),
};
static const struct snd_kcontrol_new mt8173_afe_o10_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I04 Switch", AFE_CONN3, 3, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I18 Switch", AFE_CONN8, 0, 1, 0),
};
static const struct snd_soc_dapm_widget mt8173_afe_pcm_widgets[] = {
/* inter-connections */
SND_SOC_DAPM_MIXER("I03", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I04", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I05", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I06", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I17", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I18", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("O03", SND_SOC_NOPM, 0, 0,
mt8173_afe_o03_mix, ARRAY_SIZE(mt8173_afe_o03_mix)),
SND_SOC_DAPM_MIXER("O04", SND_SOC_NOPM, 0, 0,
mt8173_afe_o04_mix, ARRAY_SIZE(mt8173_afe_o04_mix)),
SND_SOC_DAPM_MIXER("O09", SND_SOC_NOPM, 0, 0,
mt8173_afe_o09_mix, ARRAY_SIZE(mt8173_afe_o09_mix)),
SND_SOC_DAPM_MIXER("O10", SND_SOC_NOPM, 0, 0,
mt8173_afe_o10_mix, ARRAY_SIZE(mt8173_afe_o10_mix)),
};
static const struct snd_soc_dapm_route mt8173_afe_pcm_routes[] = {
{"I05", NULL, "DL1"},
{"I06", NULL, "DL1"},
{"I2S Playback", NULL, "O03"},
{"I2S Playback", NULL, "O04"},
{"VUL", NULL, "O09"},
{"VUL", NULL, "O10"},
{"I03", NULL, "I2S Capture"},
{"I04", NULL, "I2S Capture"},
{"I17", NULL, "I2S Capture"},
{"I18", NULL, "I2S Capture"},
{ "O03", "I05 Switch", "I05" },
{ "O04", "I06 Switch", "I06" },
{ "O09", "I17 Switch", "I17" },
{ "O09", "I03 Switch", "I03" },
{ "O10", "I18 Switch", "I18" },
{ "O10", "I04 Switch", "I04" },
};
static const struct snd_soc_dapm_route mt8173_afe_hdmi_routes[] = {
{"HDMIO Playback", NULL, "HDMI"},
};
static const struct snd_soc_component_driver mt8173_afe_pcm_dai_component = {
.name = "mt8173-afe-pcm-dai",
.dapm_widgets = mt8173_afe_pcm_widgets,
.num_dapm_widgets = ARRAY_SIZE(mt8173_afe_pcm_widgets),
.dapm_routes = mt8173_afe_pcm_routes,
.num_dapm_routes = ARRAY_SIZE(mt8173_afe_pcm_routes),
.suspend = mtk_afe_suspend,
.resume = mtk_afe_resume,
};
static const struct snd_soc_component_driver mt8173_afe_hdmi_dai_component = {
.name = "mt8173-afe-hdmi-dai",
.dapm_routes = mt8173_afe_hdmi_routes,
.num_dapm_routes = ARRAY_SIZE(mt8173_afe_hdmi_routes),
.suspend = mtk_afe_suspend,
.resume = mtk_afe_resume,
};
static const char *aud_clks[MT8173_CLK_NUM] = {
[MT8173_CLK_INFRASYS_AUD] = "infra_sys_audio_clk",
[MT8173_CLK_TOP_PDN_AUD] = "top_pdn_audio",
[MT8173_CLK_TOP_PDN_AUD_BUS] = "top_pdn_aud_intbus",
[MT8173_CLK_I2S0_M] = "i2s0_m",
[MT8173_CLK_I2S1_M] = "i2s1_m",
[MT8173_CLK_I2S2_M] = "i2s2_m",
[MT8173_CLK_I2S3_M] = "i2s3_m",
[MT8173_CLK_I2S3_B] = "i2s3_b",
[MT8173_CLK_BCK0] = "bck0",
[MT8173_CLK_BCK1] = "bck1",
};
static const struct mtk_base_memif_data memif_data[MT8173_AFE_MEMIF_NUM] = {
{
.name = "DL1",
.id = MT8173_AFE_MEMIF_DL1,
.reg_ofs_base = AFE_DL1_BASE,
.reg_ofs_cur = AFE_DL1_CUR,
.fs_reg = AFE_DAC_CON1,
.fs_shift = 0,
.fs_maskbit = 0xf,
.mono_reg = AFE_DAC_CON1,
.mono_shift = 21,
.hd_reg = -1,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 1,
.msb_reg = AFE_MEMIF_MSB,
.msb_shift = 0,
.agent_disable_reg = -1,
}, {
.name = "DL2",
.id = MT8173_AFE_MEMIF_DL2,
.reg_ofs_base = AFE_DL2_BASE,
.reg_ofs_cur = AFE_DL2_CUR,
.fs_reg = AFE_DAC_CON1,
.fs_shift = 4,
.fs_maskbit = 0xf,
.mono_reg = AFE_DAC_CON1,
.mono_shift = 22,
.hd_reg = -1,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 2,
.msb_reg = AFE_MEMIF_MSB,
.msb_shift = 1,
.agent_disable_reg = -1,
}, {
.name = "VUL",
.id = MT8173_AFE_MEMIF_VUL,
.reg_ofs_base = AFE_VUL_BASE,
.reg_ofs_cur = AFE_VUL_CUR,
.fs_reg = AFE_DAC_CON1,
.fs_shift = 16,
.fs_maskbit = 0xf,
.mono_reg = AFE_DAC_CON1,
.mono_shift = 27,
.hd_reg = -1,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 3,
.msb_reg = AFE_MEMIF_MSB,
.msb_shift = 6,
.agent_disable_reg = -1,
}, {
.name = "DAI",
.id = MT8173_AFE_MEMIF_DAI,
.reg_ofs_base = AFE_DAI_BASE,
.reg_ofs_cur = AFE_DAI_CUR,
.fs_reg = AFE_DAC_CON0,
.fs_shift = 24,
.fs_maskbit = 0x3,
.mono_reg = -1,
.mono_shift = -1,
.hd_reg = -1,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 4,
.msb_reg = AFE_MEMIF_MSB,
.msb_shift = 5,
.agent_disable_reg = -1,
}, {
.name = "AWB",
.id = MT8173_AFE_MEMIF_AWB,
.reg_ofs_base = AFE_AWB_BASE,
.reg_ofs_cur = AFE_AWB_CUR,
.fs_reg = AFE_DAC_CON1,
.fs_shift = 12,
.fs_maskbit = 0xf,
.mono_reg = AFE_DAC_CON1,
.mono_shift = 24,
.hd_reg = -1,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 6,
.msb_reg = AFE_MEMIF_MSB,
.msb_shift = 3,
.agent_disable_reg = -1,
}, {
.name = "MOD_DAI",
.id = MT8173_AFE_MEMIF_MOD_DAI,
.reg_ofs_base = AFE_MOD_PCM_BASE,
.reg_ofs_cur = AFE_MOD_PCM_CUR,
.fs_reg = AFE_DAC_CON1,
.fs_shift = 30,
.fs_maskbit = 0x3,
.mono_reg = AFE_DAC_CON1,
.mono_shift = 30,
.hd_reg = -1,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 7,
.msb_reg = AFE_MEMIF_MSB,
.msb_shift = 4,
.agent_disable_reg = -1,
}, {
.name = "HDMI",
.id = MT8173_AFE_MEMIF_HDMI,
.reg_ofs_base = AFE_HDMI_OUT_BASE,
.reg_ofs_cur = AFE_HDMI_OUT_CUR,
.fs_reg = -1,
.fs_shift = -1,
.fs_maskbit = -1,
.mono_reg = -1,
.mono_shift = -1,
.hd_reg = -1,
.enable_reg = -1,
.msb_reg = AFE_MEMIF_MSB,
.msb_shift = 8,
.agent_disable_reg = -1,
},
};
static const struct mtk_base_irq_data irq_data[MT8173_AFE_IRQ_NUM] = {
{
.id = MT8173_AFE_IRQ_DL1,
.irq_cnt_reg = AFE_IRQ_CNT1,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0x3ffff,
.irq_en_reg = AFE_IRQ_MCU_CON,
.irq_en_shift = 0,
.irq_fs_reg = AFE_IRQ_MCU_CON,
.irq_fs_shift = 4,
.irq_fs_maskbit = 0xf,
.irq_clr_reg = AFE_IRQ_CLR,
.irq_clr_shift = 0,
}, {
.id = MT8173_AFE_IRQ_DL2,
.irq_cnt_reg = AFE_IRQ_CNT1,
.irq_cnt_shift = 20,
.irq_cnt_maskbit = 0x3ffff,
.irq_en_reg = AFE_IRQ_MCU_CON,
.irq_en_shift = 2,
.irq_fs_reg = AFE_IRQ_MCU_CON,
.irq_fs_shift = 16,
.irq_fs_maskbit = 0xf,
.irq_clr_reg = AFE_IRQ_CLR,
.irq_clr_shift = 2,
}, {
.id = MT8173_AFE_IRQ_VUL,
.irq_cnt_reg = AFE_IRQ_CNT2,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0x3ffff,
.irq_en_reg = AFE_IRQ_MCU_CON,
.irq_en_shift = 1,
.irq_fs_reg = AFE_IRQ_MCU_CON,
.irq_fs_shift = 8,
.irq_fs_maskbit = 0xf,
.irq_clr_reg = AFE_IRQ_CLR,
.irq_clr_shift = 1,
}, {
.id = MT8173_AFE_IRQ_DAI,
.irq_cnt_reg = AFE_IRQ_CNT2,
.irq_cnt_shift = 20,
.irq_cnt_maskbit = 0x3ffff,
.irq_en_reg = AFE_IRQ_MCU_CON,
.irq_en_shift = 3,
.irq_fs_reg = AFE_IRQ_MCU_CON,
.irq_fs_shift = 20,
.irq_fs_maskbit = 0xf,
.irq_clr_reg = AFE_IRQ_CLR,
.irq_clr_shift = 3,
}, {
.id = MT8173_AFE_IRQ_AWB,
.irq_cnt_reg = AFE_IRQ_CNT7,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0x3ffff,
.irq_en_reg = AFE_IRQ_MCU_CON,
.irq_en_shift = 14,
.irq_fs_reg = AFE_IRQ_MCU_CON,
.irq_fs_shift = 24,
.irq_fs_maskbit = 0xf,
.irq_clr_reg = AFE_IRQ_CLR,
.irq_clr_shift = 6,
}, {
.id = MT8173_AFE_IRQ_DAI,
.irq_cnt_reg = AFE_IRQ_CNT2,
.irq_cnt_shift = 20,
.irq_cnt_maskbit = 0x3ffff,
.irq_en_reg = AFE_IRQ_MCU_CON,
.irq_en_shift = 3,
.irq_fs_reg = AFE_IRQ_MCU_CON,
.irq_fs_shift = 20,
.irq_fs_maskbit = 0xf,
.irq_clr_reg = AFE_IRQ_CLR,
.irq_clr_shift = 3,
}, {
.id = MT8173_AFE_IRQ_HDMI,
.irq_cnt_reg = AFE_IRQ_CNT5,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0x3ffff,
.irq_en_reg = AFE_IRQ_MCU_CON,
.irq_en_shift = 12,
.irq_fs_reg = -1,
.irq_fs_maskbit = -1,
.irq_clr_reg = AFE_IRQ_CLR,
.irq_clr_shift = 4,
},
};
static const struct regmap_config mt8173_afe_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = AFE_ADDA2_TOP_CON0,
.cache_type = REGCACHE_NONE,
};
static irqreturn_t mt8173_afe_irq_handler(int irq, void *dev_id)
{
struct mtk_base_afe *afe = dev_id;
unsigned int reg_value;
int i, ret;
ret = regmap_read(afe->regmap, AFE_IRQ_STATUS, ®_value);
if (ret) {
dev_err(afe->dev, "%s irq status err\n", __func__);
reg_value = AFE_IRQ_STATUS_BITS;
goto err_irq;
}
for (i = 0; i < MT8173_AFE_MEMIF_NUM; i++) {
struct mtk_base_afe_memif *memif = &afe->memif[i];
struct mtk_base_afe_irq *irq_p;
if (memif->irq_usage < 0)
continue;
irq_p = &afe->irqs[memif->irq_usage];
if (!(reg_value & (1 << irq_p->irq_data->irq_clr_shift)))
continue;
snd_pcm_period_elapsed(memif->substream);
}
err_irq:
/* clear irq */
regmap_write(afe->regmap, AFE_IRQ_CLR,
reg_value & AFE_IRQ_STATUS_BITS);
return IRQ_HANDLED;
}
static int mt8173_afe_runtime_suspend(struct device *dev)
{
struct mtk_base_afe *afe = dev_get_drvdata(dev);
struct mt8173_afe_private *afe_priv = afe->platform_priv;
/* disable AFE */
regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0);
/* disable AFE clk */
regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
AUD_TCON0_PDN_AFE, AUD_TCON0_PDN_AFE);
clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S1_M]);
clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S2_M]);
clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_BCK0]);
clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_BCK1]);
clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD]);
clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD_BUS]);
clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_INFRASYS_AUD]);
return 0;
}
static int mt8173_afe_runtime_resume(struct device *dev)
{
struct mtk_base_afe *afe = dev_get_drvdata(dev);
struct mt8173_afe_private *afe_priv = afe->platform_priv;
int ret;
ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_INFRASYS_AUD]);
if (ret)
return ret;
ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD_BUS]);
if (ret)
goto err_infra;
ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD]);
if (ret)
goto err_top_aud_bus;
ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_BCK0]);
if (ret)
goto err_top_aud;
ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_BCK1]);
if (ret)
goto err_bck0;
ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_I2S1_M]);
if (ret)
goto err_i2s1_m;
ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_I2S2_M]);
if (ret)
goto err_i2s2_m;
/* enable AFE clk */
regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, AUD_TCON0_PDN_AFE, 0);
/* set O3/O4 16bits */
regmap_update_bits(afe->regmap, AFE_CONN_24BIT,
AFE_CONN_24BIT_O03 | AFE_CONN_24BIT_O04, 0);
/* unmask all IRQs */
regmap_update_bits(afe->regmap, AFE_IRQ_MCU_EN, 0xff, 0xff);
/* enable AFE */
regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1);
return 0;
err_i2s1_m:
clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S1_M]);
err_i2s2_m:
clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S2_M]);
err_bck0:
clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_BCK0]);
err_top_aud:
clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD]);
err_top_aud_bus:
clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD_BUS]);
err_infra:
clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_INFRASYS_AUD]);
return ret;
}
static int mt8173_afe_init_audio_clk(struct mtk_base_afe *afe)
{
size_t i;
struct mt8173_afe_private *afe_priv = afe->platform_priv;
for (i = 0; i < ARRAY_SIZE(aud_clks); i++) {
afe_priv->clocks[i] = devm_clk_get(afe->dev, aud_clks[i]);
if (IS_ERR(afe_priv->clocks[i])) {
dev_err(afe->dev, "%s devm_clk_get %s fail\n",
__func__, aud_clks[i]);
return PTR_ERR(afe_priv->clocks[i]);
}
}
clk_set_rate(afe_priv->clocks[MT8173_CLK_BCK0], 22579200); /* 22M */
clk_set_rate(afe_priv->clocks[MT8173_CLK_BCK1], 24576000); /* 24M */
return 0;
}
static int mt8173_afe_pcm_dev_probe(struct platform_device *pdev)
{
int ret, i;
int irq_id;
struct mtk_base_afe *afe;
struct mt8173_afe_private *afe_priv;
struct snd_soc_component *comp_pcm, *comp_hdmi;
ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(33));
if (ret)
return ret;
afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
if (!afe)
return -ENOMEM;
afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),
GFP_KERNEL);
afe_priv = afe->platform_priv;
if (!afe_priv)
return -ENOMEM;
afe->dev = &pdev->dev;
irq_id = platform_get_irq(pdev, 0);
if (irq_id <= 0)
return irq_id < 0 ? irq_id : -ENXIO;
afe->base_addr = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(afe->base_addr))
return PTR_ERR(afe->base_addr);
afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr,
&mt8173_afe_regmap_config);
if (IS_ERR(afe->regmap))
return PTR_ERR(afe->regmap);
/* initial audio related clock */
ret = mt8173_afe_init_audio_clk(afe);
if (ret) {
dev_err(afe->dev, "mt8173_afe_init_audio_clk fail\n");
return ret;
}
/* memif % irq initialize*/
afe->memif_size = MT8173_AFE_MEMIF_NUM;
afe->memif = devm_kcalloc(afe->dev, afe->memif_size,
sizeof(*afe->memif), GFP_KERNEL);
if (!afe->memif)
return -ENOMEM;
afe->irqs_size = MT8173_AFE_IRQ_NUM;
afe->irqs = devm_kcalloc(afe->dev, afe->irqs_size,
sizeof(*afe->irqs), GFP_KERNEL);
if (!afe->irqs)
return -ENOMEM;
for (i = 0; i < afe->irqs_size; i++) {
afe->memif[i].data = &memif_data[i];
afe->irqs[i].irq_data = &irq_data[i];
afe->irqs[i].irq_occupyed = true;
afe->memif[i].irq_usage = i;
afe->memif[i].const_irq = 1;
}
afe->mtk_afe_hardware = &mt8173_afe_hardware;
afe->memif_fs = mt8173_memif_fs;
afe->irq_fs = mt8173_irq_fs;
platform_set_drvdata(pdev, afe);
pm_runtime_enable(&pdev->dev);
if (!pm_runtime_enabled(&pdev->dev)) {
ret = mt8173_afe_runtime_resume(&pdev->dev);
if (ret)
goto err_pm_disable;
}
afe->reg_back_up_list = mt8173_afe_backup_list;
afe->reg_back_up_list_num = ARRAY_SIZE(mt8173_afe_backup_list);
afe->runtime_resume = mt8173_afe_runtime_resume;
afe->runtime_suspend = mt8173_afe_runtime_suspend;
ret = devm_snd_soc_register_component(&pdev->dev,
&mtk_afe_pcm_platform,
NULL, 0);
if (ret)
goto err_pm_disable;
comp_pcm = devm_kzalloc(&pdev->dev, sizeof(*comp_pcm), GFP_KERNEL);
if (!comp_pcm) {
ret = -ENOMEM;
goto err_pm_disable;
}
ret = snd_soc_component_initialize(comp_pcm,
&mt8173_afe_pcm_dai_component,
&pdev->dev);
if (ret)
goto err_pm_disable;
#ifdef CONFIG_DEBUG_FS
comp_pcm->debugfs_prefix = "pcm";
#endif
ret = snd_soc_add_component(comp_pcm,
mt8173_afe_pcm_dais,
ARRAY_SIZE(mt8173_afe_pcm_dais));
if (ret)
goto err_pm_disable;
comp_hdmi = devm_kzalloc(&pdev->dev, sizeof(*comp_hdmi), GFP_KERNEL);
if (!comp_hdmi) {
ret = -ENOMEM;
goto err_cleanup_components;
}
ret = snd_soc_component_initialize(comp_hdmi,
&mt8173_afe_hdmi_dai_component,
&pdev->dev);
if (ret)
goto err_cleanup_components;
#ifdef CONFIG_DEBUG_FS
comp_hdmi->debugfs_prefix = "hdmi";
#endif
ret = snd_soc_add_component(comp_hdmi,
mt8173_afe_hdmi_dais,
ARRAY_SIZE(mt8173_afe_hdmi_dais));
if (ret)
goto err_cleanup_components;
ret = devm_request_irq(afe->dev, irq_id, mt8173_afe_irq_handler,
0, "Afe_ISR_Handle", (void *)afe);
if (ret) {
dev_err(afe->dev, "could not request_irq\n");
goto err_cleanup_components;
}
dev_info(&pdev->dev, "MT8173 AFE driver initialized.\n");
return 0;
err_cleanup_components:
snd_soc_unregister_component(&pdev->dev);
err_pm_disable:
pm_runtime_disable(&pdev->dev);
return ret;
}
static void mt8173_afe_pcm_dev_remove(struct platform_device *pdev)
{
snd_soc_unregister_component(&pdev->dev);
pm_runtime_disable(&pdev->dev);
if (!pm_runtime_status_suspended(&pdev->dev))
mt8173_afe_runtime_suspend(&pdev->dev);
}
static const struct of_device_id mt8173_afe_pcm_dt_match[] = {
{ .compatible = "mediatek,mt8173-afe-pcm", },
{ }
};
MODULE_DEVICE_TABLE(of, mt8173_afe_pcm_dt_match);
static const struct dev_pm_ops mt8173_afe_pm_ops = {
SET_RUNTIME_PM_OPS(mt8173_afe_runtime_suspend,
mt8173_afe_runtime_resume, NULL)
};
static struct platform_driver mt8173_afe_pcm_driver = {
.driver = {
.name = "mt8173-afe-pcm",
.of_match_table = mt8173_afe_pcm_dt_match,
.pm = &mt8173_afe_pm_ops,
},
.probe = mt8173_afe_pcm_dev_probe,
.remove_new = mt8173_afe_pcm_dev_remove,
};
module_platform_driver(mt8173_afe_pcm_driver);
MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver");
MODULE_AUTHOR("Koro Chen <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/mediatek/mt8173/mt8173-afe-pcm.c |
// SPDX-License-Identifier: GPL-2.0
/*
* mt8173-max98090.c -- MT8173 MAX98090 ALSA SoC machine driver
*
* Copyright (c) 2015 MediaTek Inc.
* Author: Koro Chen <[email protected]>
*/
#include <linux/module.h>
#include <sound/soc.h>
#include <sound/jack.h>
#include <linux/gpio.h>
#include "../../codecs/max98090.h"
static struct snd_soc_jack mt8173_max98090_jack;
static struct snd_soc_jack_pin mt8173_max98090_jack_pins[] = {
{
.pin = "Headphone",
.mask = SND_JACK_HEADPHONE,
},
{
.pin = "Headset Mic",
.mask = SND_JACK_MICROPHONE,
},
};
static const struct snd_soc_dapm_widget mt8173_max98090_widgets[] = {
SND_SOC_DAPM_SPK("Speaker", NULL),
SND_SOC_DAPM_MIC("Int Mic", NULL),
SND_SOC_DAPM_HP("Headphone", NULL),
SND_SOC_DAPM_MIC("Headset Mic", NULL),
};
static const struct snd_soc_dapm_route mt8173_max98090_routes[] = {
{"Speaker", NULL, "SPKL"},
{"Speaker", NULL, "SPKR"},
{"DMICL", NULL, "Int Mic"},
{"Headphone", NULL, "HPL"},
{"Headphone", NULL, "HPR"},
{"Headset Mic", NULL, "MICBIAS"},
{"IN34", NULL, "Headset Mic"},
};
static const struct snd_kcontrol_new mt8173_max98090_controls[] = {
SOC_DAPM_PIN_SWITCH("Speaker"),
SOC_DAPM_PIN_SWITCH("Int Mic"),
SOC_DAPM_PIN_SWITCH("Headphone"),
SOC_DAPM_PIN_SWITCH("Headset Mic"),
};
static int mt8173_max98090_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
return snd_soc_dai_set_sysclk(codec_dai, 0, params_rate(params) * 256,
SND_SOC_CLOCK_IN);
}
static const struct snd_soc_ops mt8173_max98090_ops = {
.hw_params = mt8173_max98090_hw_params,
};
static int mt8173_max98090_init(struct snd_soc_pcm_runtime *runtime)
{
int ret;
struct snd_soc_card *card = runtime->card;
struct snd_soc_component *component = asoc_rtd_to_codec(runtime, 0)->component;
/* enable jack detection */
ret = snd_soc_card_jack_new_pins(card, "Headphone", SND_JACK_HEADSET,
&mt8173_max98090_jack,
mt8173_max98090_jack_pins,
ARRAY_SIZE(mt8173_max98090_jack_pins));
if (ret) {
dev_err(card->dev, "Can't create a new Jack %d\n", ret);
return ret;
}
return max98090_mic_detect(component, &mt8173_max98090_jack);
}
SND_SOC_DAILINK_DEFS(playback,
DAILINK_COMP_ARRAY(COMP_CPU("DL1")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture,
DAILINK_COMP_ARRAY(COMP_CPU("VUL")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(hifi,
DAILINK_COMP_ARRAY(COMP_CPU("I2S")),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "HiFi")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
/* Digital audio interface glue - connects codec <---> CPU */
static struct snd_soc_dai_link mt8173_max98090_dais[] = {
/* Front End DAI links */
{
.name = "MAX98090 Playback",
.stream_name = "MAX98090 Playback",
.trigger = {SND_SOC_DPCM_TRIGGER_POST, SND_SOC_DPCM_TRIGGER_POST},
.dynamic = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(playback),
},
{
.name = "MAX98090 Capture",
.stream_name = "MAX98090 Capture",
.trigger = {SND_SOC_DPCM_TRIGGER_POST, SND_SOC_DPCM_TRIGGER_POST},
.dynamic = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(capture),
},
/* Back End DAI links */
{
.name = "Codec",
.no_pcm = 1,
.init = mt8173_max98090_init,
.ops = &mt8173_max98090_ops,
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS,
.dpcm_playback = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(hifi),
},
};
static struct snd_soc_card mt8173_max98090_card = {
.name = "mt8173-max98090",
.owner = THIS_MODULE,
.dai_link = mt8173_max98090_dais,
.num_links = ARRAY_SIZE(mt8173_max98090_dais),
.controls = mt8173_max98090_controls,
.num_controls = ARRAY_SIZE(mt8173_max98090_controls),
.dapm_widgets = mt8173_max98090_widgets,
.num_dapm_widgets = ARRAY_SIZE(mt8173_max98090_widgets),
.dapm_routes = mt8173_max98090_routes,
.num_dapm_routes = ARRAY_SIZE(mt8173_max98090_routes),
};
static int mt8173_max98090_dev_probe(struct platform_device *pdev)
{
struct snd_soc_card *card = &mt8173_max98090_card;
struct device_node *codec_node, *platform_node;
struct snd_soc_dai_link *dai_link;
int ret, i;
platform_node = of_parse_phandle(pdev->dev.of_node,
"mediatek,platform", 0);
if (!platform_node) {
dev_err(&pdev->dev, "Property 'platform' missing or invalid\n");
return -EINVAL;
}
for_each_card_prelinks(card, i, dai_link) {
if (dai_link->platforms->name)
continue;
dai_link->platforms->of_node = platform_node;
}
codec_node = of_parse_phandle(pdev->dev.of_node,
"mediatek,audio-codec", 0);
if (!codec_node) {
dev_err(&pdev->dev,
"Property 'audio-codec' missing or invalid\n");
ret = -EINVAL;
goto put_platform_node;
}
for_each_card_prelinks(card, i, dai_link) {
if (dai_link->codecs->name)
continue;
dai_link->codecs->of_node = codec_node;
}
card->dev = &pdev->dev;
ret = devm_snd_soc_register_card(&pdev->dev, card);
of_node_put(codec_node);
put_platform_node:
of_node_put(platform_node);
return ret;
}
static const struct of_device_id mt8173_max98090_dt_match[] = {
{ .compatible = "mediatek,mt8173-max98090", },
{ }
};
MODULE_DEVICE_TABLE(of, mt8173_max98090_dt_match);
static struct platform_driver mt8173_max98090_driver = {
.driver = {
.name = "mt8173-max98090",
.of_match_table = mt8173_max98090_dt_match,
.pm = &snd_soc_pm_ops,
},
.probe = mt8173_max98090_dev_probe,
};
module_platform_driver(mt8173_max98090_driver);
/* Module information */
MODULE_DESCRIPTION("MT8173 MAX98090 ALSA SoC machine driver");
MODULE_AUTHOR("Koro Chen <[email protected]>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:mt8173-max98090");
| linux-master | sound/soc/mediatek/mt8173/mt8173-max98090.c |
// SPDX-License-Identifier: GPL-2.0
/*
* mt8173-rt5650-rt5514.c -- MT8173 machine driver with RT5650/5514 codecs
*
* Copyright (c) 2016 MediaTek Inc.
* Author: Koro Chen <[email protected]>
*/
#include <linux/module.h>
#include <linux/gpio.h>
#include <linux/of_gpio.h>
#include <sound/soc.h>
#include <sound/jack.h>
#include "../../codecs/rt5645.h"
#define MCLK_FOR_CODECS 12288000
static const struct snd_soc_dapm_widget mt8173_rt5650_rt5514_widgets[] = {
SND_SOC_DAPM_SPK("Speaker", NULL),
SND_SOC_DAPM_MIC("Int Mic", NULL),
SND_SOC_DAPM_HP("Headphone", NULL),
SND_SOC_DAPM_MIC("Headset Mic", NULL),
};
static const struct snd_soc_dapm_route mt8173_rt5650_rt5514_routes[] = {
{"Speaker", NULL, "SPOL"},
{"Speaker", NULL, "SPOR"},
{"Sub DMIC1L", NULL, "Int Mic"},
{"Sub DMIC1R", NULL, "Int Mic"},
{"Headphone", NULL, "HPOL"},
{"Headphone", NULL, "HPOR"},
{"IN1P", NULL, "Headset Mic"},
{"IN1N", NULL, "Headset Mic"},
};
static const struct snd_kcontrol_new mt8173_rt5650_rt5514_controls[] = {
SOC_DAPM_PIN_SWITCH("Speaker"),
SOC_DAPM_PIN_SWITCH("Int Mic"),
SOC_DAPM_PIN_SWITCH("Headphone"),
SOC_DAPM_PIN_SWITCH("Headset Mic"),
};
static struct snd_soc_jack_pin mt8173_rt5650_rt5514_jack_pins[] = {
{
.pin = "Headphone",
.mask = SND_JACK_HEADPHONE,
},
{
.pin = "Headset Mic",
.mask = SND_JACK_MICROPHONE,
},
};
static int mt8173_rt5650_rt5514_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai *codec_dai;
int i, ret;
for_each_rtd_codec_dais(rtd, i, codec_dai) {
/* pll from mclk 12.288M */
ret = snd_soc_dai_set_pll(codec_dai, 0, 0, MCLK_FOR_CODECS,
params_rate(params) * 512);
if (ret)
return ret;
/* sysclk from pll */
ret = snd_soc_dai_set_sysclk(codec_dai, 1,
params_rate(params) * 512,
SND_SOC_CLOCK_IN);
if (ret)
return ret;
}
return 0;
}
static const struct snd_soc_ops mt8173_rt5650_rt5514_ops = {
.hw_params = mt8173_rt5650_rt5514_hw_params,
};
static struct snd_soc_jack mt8173_rt5650_rt5514_jack;
static int mt8173_rt5650_rt5514_init(struct snd_soc_pcm_runtime *runtime)
{
struct snd_soc_card *card = runtime->card;
struct snd_soc_component *component = asoc_rtd_to_codec(runtime, 0)->component;
int ret;
rt5645_sel_asrc_clk_src(component,
RT5645_DA_STEREO_FILTER |
RT5645_AD_STEREO_FILTER,
RT5645_CLK_SEL_I2S1_ASRC);
/* enable jack detection */
ret = snd_soc_card_jack_new_pins(card, "Headset Jack",
SND_JACK_HEADPHONE | SND_JACK_MICROPHONE |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3,
&mt8173_rt5650_rt5514_jack,
mt8173_rt5650_rt5514_jack_pins,
ARRAY_SIZE(mt8173_rt5650_rt5514_jack_pins));
if (ret) {
dev_err(card->dev, "Can't new Headset Jack %d\n", ret);
return ret;
}
return rt5645_set_jack_detect(component,
&mt8173_rt5650_rt5514_jack,
&mt8173_rt5650_rt5514_jack,
&mt8173_rt5650_rt5514_jack);
}
enum {
DAI_LINK_PLAYBACK,
DAI_LINK_CAPTURE,
DAI_LINK_CODEC_I2S,
};
SND_SOC_DAILINK_DEFS(playback,
DAILINK_COMP_ARRAY(COMP_CPU("DL1")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture,
DAILINK_COMP_ARRAY(COMP_CPU("VUL")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(codec,
DAILINK_COMP_ARRAY(COMP_CPU("I2S")),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "rt5645-aif1"),
COMP_CODEC(NULL, "rt5514-aif1")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
/* Digital audio interface glue - connects codec <---> CPU */
static struct snd_soc_dai_link mt8173_rt5650_rt5514_dais[] = {
/* Front End DAI links */
[DAI_LINK_PLAYBACK] = {
.name = "rt5650_rt5514 Playback",
.stream_name = "rt5650_rt5514 Playback",
.trigger = {SND_SOC_DPCM_TRIGGER_POST, SND_SOC_DPCM_TRIGGER_POST},
.dynamic = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(playback),
},
[DAI_LINK_CAPTURE] = {
.name = "rt5650_rt5514 Capture",
.stream_name = "rt5650_rt5514 Capture",
.trigger = {SND_SOC_DPCM_TRIGGER_POST, SND_SOC_DPCM_TRIGGER_POST},
.dynamic = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(capture),
},
/* Back End DAI links */
[DAI_LINK_CODEC_I2S] = {
.name = "Codec",
.no_pcm = 1,
.init = mt8173_rt5650_rt5514_init,
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS,
.ops = &mt8173_rt5650_rt5514_ops,
.ignore_pmdown_time = 1,
.dpcm_playback = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(codec),
},
};
static struct snd_soc_codec_conf mt8173_rt5650_rt5514_codec_conf[] = {
{
.name_prefix = "Sub",
},
};
static struct snd_soc_card mt8173_rt5650_rt5514_card = {
.name = "mtk-rt5650-rt5514",
.owner = THIS_MODULE,
.dai_link = mt8173_rt5650_rt5514_dais,
.num_links = ARRAY_SIZE(mt8173_rt5650_rt5514_dais),
.codec_conf = mt8173_rt5650_rt5514_codec_conf,
.num_configs = ARRAY_SIZE(mt8173_rt5650_rt5514_codec_conf),
.controls = mt8173_rt5650_rt5514_controls,
.num_controls = ARRAY_SIZE(mt8173_rt5650_rt5514_controls),
.dapm_widgets = mt8173_rt5650_rt5514_widgets,
.num_dapm_widgets = ARRAY_SIZE(mt8173_rt5650_rt5514_widgets),
.dapm_routes = mt8173_rt5650_rt5514_routes,
.num_dapm_routes = ARRAY_SIZE(mt8173_rt5650_rt5514_routes),
};
static int mt8173_rt5650_rt5514_dev_probe(struct platform_device *pdev)
{
struct snd_soc_card *card = &mt8173_rt5650_rt5514_card;
struct device_node *platform_node;
struct snd_soc_dai_link *dai_link;
int i, ret;
platform_node = of_parse_phandle(pdev->dev.of_node,
"mediatek,platform", 0);
if (!platform_node) {
dev_err(&pdev->dev, "Property 'platform' missing or invalid\n");
return -EINVAL;
}
for_each_card_prelinks(card, i, dai_link) {
if (dai_link->platforms->name)
continue;
dai_link->platforms->of_node = platform_node;
}
mt8173_rt5650_rt5514_dais[DAI_LINK_CODEC_I2S].codecs[0].of_node =
of_parse_phandle(pdev->dev.of_node, "mediatek,audio-codec", 0);
if (!mt8173_rt5650_rt5514_dais[DAI_LINK_CODEC_I2S].codecs[0].of_node) {
dev_err(&pdev->dev,
"Property 'audio-codec' missing or invalid\n");
ret = -EINVAL;
goto out;
}
mt8173_rt5650_rt5514_dais[DAI_LINK_CODEC_I2S].codecs[1].of_node =
of_parse_phandle(pdev->dev.of_node, "mediatek,audio-codec", 1);
if (!mt8173_rt5650_rt5514_dais[DAI_LINK_CODEC_I2S].codecs[1].of_node) {
dev_err(&pdev->dev,
"Property 'audio-codec' missing or invalid\n");
ret = -EINVAL;
goto out;
}
mt8173_rt5650_rt5514_codec_conf[0].dlc.of_node =
mt8173_rt5650_rt5514_dais[DAI_LINK_CODEC_I2S].codecs[1].of_node;
card->dev = &pdev->dev;
ret = devm_snd_soc_register_card(&pdev->dev, card);
out:
of_node_put(platform_node);
return ret;
}
static const struct of_device_id mt8173_rt5650_rt5514_dt_match[] = {
{ .compatible = "mediatek,mt8173-rt5650-rt5514", },
{ }
};
MODULE_DEVICE_TABLE(of, mt8173_rt5650_rt5514_dt_match);
static struct platform_driver mt8173_rt5650_rt5514_driver = {
.driver = {
.name = "mtk-rt5650-rt5514",
.of_match_table = mt8173_rt5650_rt5514_dt_match,
.pm = &snd_soc_pm_ops,
},
.probe = mt8173_rt5650_rt5514_dev_probe,
};
module_platform_driver(mt8173_rt5650_rt5514_driver);
/* Module information */
MODULE_DESCRIPTION("MT8173 RT5650 and RT5514 SoC machine driver");
MODULE_AUTHOR("Koro Chen <[email protected]>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:mtk-rt5650-rt5514");
| linux-master | sound/soc/mediatek/mt8173/mt8173-rt5650-rt5514.c |
// SPDX-License-Identifier: GPL-2.0
/*
* mt8173-rt5650.c -- MT8173 machine driver with RT5650 codecs
*
* Copyright (c) 2016 MediaTek Inc.
* Author: Koro Chen <[email protected]>
*/
#include <linux/module.h>
#include <linux/gpio.h>
#include <linux/of_gpio.h>
#include <sound/soc.h>
#include <sound/jack.h>
#include "../../codecs/rt5645.h"
#define MCLK_FOR_CODECS 12288000
enum mt8173_rt5650_mclk {
MT8173_RT5650_MCLK_EXTERNAL = 0,
MT8173_RT5650_MCLK_INTERNAL,
};
struct mt8173_rt5650_platform_data {
enum mt8173_rt5650_mclk pll_from;
/* 0 = external oscillator; 1 = internal source from mt8173 */
};
static struct mt8173_rt5650_platform_data mt8173_rt5650_priv = {
.pll_from = MT8173_RT5650_MCLK_EXTERNAL,
};
static const struct snd_soc_dapm_widget mt8173_rt5650_widgets[] = {
SND_SOC_DAPM_SPK("Ext Spk", NULL),
SND_SOC_DAPM_MIC("Int Mic", NULL),
SND_SOC_DAPM_HP("Headphone", NULL),
SND_SOC_DAPM_MIC("Headset Mic", NULL),
};
static const struct snd_soc_dapm_route mt8173_rt5650_routes[] = {
{"Ext Spk", NULL, "SPOL"},
{"Ext Spk", NULL, "SPOR"},
{"DMIC L1", NULL, "Int Mic"},
{"DMIC R1", NULL, "Int Mic"},
{"Headphone", NULL, "HPOL"},
{"Headphone", NULL, "HPOR"},
{"IN1P", NULL, "Headset Mic"},
{"IN1N", NULL, "Headset Mic"},
};
static const struct snd_kcontrol_new mt8173_rt5650_controls[] = {
SOC_DAPM_PIN_SWITCH("Ext Spk"),
SOC_DAPM_PIN_SWITCH("Int Mic"),
SOC_DAPM_PIN_SWITCH("Headphone"),
SOC_DAPM_PIN_SWITCH("Headset Mic"),
};
static struct snd_soc_jack_pin mt8173_rt5650_jack_pins[] = {
{
.pin = "Headphone",
.mask = SND_JACK_HEADPHONE,
},
{
.pin = "Headset Mic",
.mask = SND_JACK_MICROPHONE,
},
};
static int mt8173_rt5650_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
unsigned int mclk_clock;
struct snd_soc_dai *codec_dai;
int i, ret;
switch (mt8173_rt5650_priv.pll_from) {
case MT8173_RT5650_MCLK_EXTERNAL:
/* mclk = 12.288M */
mclk_clock = MCLK_FOR_CODECS;
break;
case MT8173_RT5650_MCLK_INTERNAL:
/* mclk = sampling rate*256 */
mclk_clock = params_rate(params) * 256;
break;
default:
/* mclk = 12.288M */
mclk_clock = MCLK_FOR_CODECS;
break;
}
for_each_rtd_codec_dais(rtd, i, codec_dai) {
/* pll from mclk */
ret = snd_soc_dai_set_pll(codec_dai, 0, 0, mclk_clock,
params_rate(params) * 512);
if (ret)
return ret;
/* sysclk from pll */
ret = snd_soc_dai_set_sysclk(codec_dai, 1,
params_rate(params) * 512,
SND_SOC_CLOCK_IN);
if (ret)
return ret;
}
return 0;
}
static const struct snd_soc_ops mt8173_rt5650_ops = {
.hw_params = mt8173_rt5650_hw_params,
};
static struct snd_soc_jack mt8173_rt5650_jack, mt8173_rt5650_hdmi_jack;
static int mt8173_rt5650_init(struct snd_soc_pcm_runtime *runtime)
{
struct snd_soc_card *card = runtime->card;
struct snd_soc_component *component = asoc_rtd_to_codec(runtime, 0)->component;
const char *codec_capture_dai = asoc_rtd_to_codec(runtime, 1)->name;
int ret;
rt5645_sel_asrc_clk_src(component,
RT5645_DA_STEREO_FILTER,
RT5645_CLK_SEL_I2S1_ASRC);
if (!strcmp(codec_capture_dai, "rt5645-aif1")) {
rt5645_sel_asrc_clk_src(component,
RT5645_AD_STEREO_FILTER,
RT5645_CLK_SEL_I2S1_ASRC);
} else if (!strcmp(codec_capture_dai, "rt5645-aif2")) {
rt5645_sel_asrc_clk_src(component,
RT5645_AD_STEREO_FILTER,
RT5645_CLK_SEL_I2S2_ASRC);
} else {
dev_warn(card->dev,
"Only one dai codec found in DTS, enabled rt5645 AD filter\n");
rt5645_sel_asrc_clk_src(component,
RT5645_AD_STEREO_FILTER,
RT5645_CLK_SEL_I2S1_ASRC);
}
/* enable jack detection */
ret = snd_soc_card_jack_new_pins(card, "Headset Jack",
SND_JACK_HEADPHONE | SND_JACK_MICROPHONE |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3,
&mt8173_rt5650_jack,
mt8173_rt5650_jack_pins,
ARRAY_SIZE(mt8173_rt5650_jack_pins));
if (ret) {
dev_err(card->dev, "Can't new Headset Jack %d\n", ret);
return ret;
}
return rt5645_set_jack_detect(component,
&mt8173_rt5650_jack,
&mt8173_rt5650_jack,
&mt8173_rt5650_jack);
}
static int mt8173_rt5650_hdmi_init(struct snd_soc_pcm_runtime *rtd)
{
int ret;
ret = snd_soc_card_jack_new(rtd->card, "HDMI Jack", SND_JACK_LINEOUT,
&mt8173_rt5650_hdmi_jack);
if (ret)
return ret;
return snd_soc_component_set_jack(asoc_rtd_to_codec(rtd, 0)->component,
&mt8173_rt5650_hdmi_jack, NULL);
}
enum {
DAI_LINK_PLAYBACK,
DAI_LINK_CAPTURE,
DAI_LINK_HDMI,
DAI_LINK_CODEC_I2S,
DAI_LINK_HDMI_I2S,
};
SND_SOC_DAILINK_DEFS(playback,
DAILINK_COMP_ARRAY(COMP_CPU("DL1")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture,
DAILINK_COMP_ARRAY(COMP_CPU("VUL")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(hdmi_pcm,
DAILINK_COMP_ARRAY(COMP_CPU("HDMI")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(codec,
DAILINK_COMP_ARRAY(COMP_CPU("I2S")),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "rt5645-aif1"), /* Playback */
COMP_CODEC(NULL, "rt5645-aif1")),/* Capture */
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(hdmi_be,
DAILINK_COMP_ARRAY(COMP_CPU("HDMIO")),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "i2s-hifi")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
/* Digital audio interface glue - connects codec <---> CPU */
static struct snd_soc_dai_link mt8173_rt5650_dais[] = {
/* Front End DAI links */
[DAI_LINK_PLAYBACK] = {
.name = "rt5650 Playback",
.stream_name = "rt5650 Playback",
.trigger = {SND_SOC_DPCM_TRIGGER_POST, SND_SOC_DPCM_TRIGGER_POST},
.dynamic = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(playback),
},
[DAI_LINK_CAPTURE] = {
.name = "rt5650 Capture",
.stream_name = "rt5650 Capture",
.trigger = {SND_SOC_DPCM_TRIGGER_POST, SND_SOC_DPCM_TRIGGER_POST},
.dynamic = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(capture),
},
[DAI_LINK_HDMI] = {
.name = "HDMI",
.stream_name = "HDMI PCM",
.trigger = {SND_SOC_DPCM_TRIGGER_POST, SND_SOC_DPCM_TRIGGER_POST},
.dynamic = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(hdmi_pcm),
},
/* Back End DAI links */
[DAI_LINK_CODEC_I2S] = {
.name = "Codec",
.no_pcm = 1,
.init = mt8173_rt5650_init,
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS,
.ops = &mt8173_rt5650_ops,
.ignore_pmdown_time = 1,
.dpcm_playback = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(codec),
},
[DAI_LINK_HDMI_I2S] = {
.name = "HDMI BE",
.no_pcm = 1,
.dpcm_playback = 1,
.init = mt8173_rt5650_hdmi_init,
SND_SOC_DAILINK_REG(hdmi_be),
},
};
static struct snd_soc_card mt8173_rt5650_card = {
.name = "mtk-rt5650",
.owner = THIS_MODULE,
.dai_link = mt8173_rt5650_dais,
.num_links = ARRAY_SIZE(mt8173_rt5650_dais),
.controls = mt8173_rt5650_controls,
.num_controls = ARRAY_SIZE(mt8173_rt5650_controls),
.dapm_widgets = mt8173_rt5650_widgets,
.num_dapm_widgets = ARRAY_SIZE(mt8173_rt5650_widgets),
.dapm_routes = mt8173_rt5650_routes,
.num_dapm_routes = ARRAY_SIZE(mt8173_rt5650_routes),
};
static int mt8173_rt5650_dev_probe(struct platform_device *pdev)
{
struct snd_soc_card *card = &mt8173_rt5650_card;
struct device_node *platform_node;
struct device_node *np;
const char *codec_capture_dai;
struct snd_soc_dai_link *dai_link;
int i, ret;
platform_node = of_parse_phandle(pdev->dev.of_node,
"mediatek,platform", 0);
if (!platform_node) {
dev_err(&pdev->dev, "Property 'platform' missing or invalid\n");
return -EINVAL;
}
for_each_card_prelinks(card, i, dai_link) {
if (dai_link->platforms->name)
continue;
dai_link->platforms->of_node = platform_node;
}
mt8173_rt5650_dais[DAI_LINK_CODEC_I2S].codecs[0].of_node =
of_parse_phandle(pdev->dev.of_node, "mediatek,audio-codec", 0);
if (!mt8173_rt5650_dais[DAI_LINK_CODEC_I2S].codecs[0].of_node) {
dev_err(&pdev->dev,
"Property 'audio-codec' missing or invalid\n");
ret = -EINVAL;
goto put_platform_node;
}
mt8173_rt5650_dais[DAI_LINK_CODEC_I2S].codecs[1].of_node =
mt8173_rt5650_dais[DAI_LINK_CODEC_I2S].codecs[0].of_node;
np = of_get_child_by_name(pdev->dev.of_node, "codec-capture");
if (np) {
ret = snd_soc_of_get_dai_name(np, &codec_capture_dai, 0);
of_node_put(np);
if (ret < 0) {
dev_err(&pdev->dev,
"%s codec_capture_dai name fail %d\n",
__func__, ret);
goto put_platform_node;
}
mt8173_rt5650_dais[DAI_LINK_CODEC_I2S].codecs[1].dai_name =
codec_capture_dai;
}
if (device_property_present(&pdev->dev, "mediatek,mclk")) {
ret = device_property_read_u32(&pdev->dev,
"mediatek,mclk",
&mt8173_rt5650_priv.pll_from);
if (ret) {
dev_err(&pdev->dev,
"%s snd_soc_register_card fail %d\n",
__func__, ret);
}
}
mt8173_rt5650_dais[DAI_LINK_HDMI_I2S].codecs->of_node =
of_parse_phandle(pdev->dev.of_node, "mediatek,audio-codec", 1);
if (!mt8173_rt5650_dais[DAI_LINK_HDMI_I2S].codecs->of_node) {
dev_err(&pdev->dev,
"Property 'audio-codec' missing or invalid\n");
ret = -EINVAL;
goto put_platform_node;
}
card->dev = &pdev->dev;
ret = devm_snd_soc_register_card(&pdev->dev, card);
put_platform_node:
of_node_put(platform_node);
return ret;
}
static const struct of_device_id mt8173_rt5650_dt_match[] = {
{ .compatible = "mediatek,mt8173-rt5650", },
{ }
};
MODULE_DEVICE_TABLE(of, mt8173_rt5650_dt_match);
static struct platform_driver mt8173_rt5650_driver = {
.driver = {
.name = "mtk-rt5650",
.of_match_table = mt8173_rt5650_dt_match,
.pm = &snd_soc_pm_ops,
},
.probe = mt8173_rt5650_dev_probe,
};
module_platform_driver(mt8173_rt5650_driver);
/* Module information */
MODULE_DESCRIPTION("MT8173 RT5650 SoC machine driver");
MODULE_AUTHOR("Koro Chen <[email protected]>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:mtk-rt5650");
| linux-master | sound/soc/mediatek/mt8173/mt8173-rt5650.c |
// SPDX-License-Identifier: GPL-2.0
/*
* mt8173-rt5650-rt5676.c -- MT8173 machine driver with RT5650/5676 codecs
*
* Copyright (c) 2015 MediaTek Inc.
* Author: Koro Chen <[email protected]>
*/
#include <linux/module.h>
#include <linux/gpio.h>
#include <linux/of_gpio.h>
#include <sound/soc.h>
#include <sound/jack.h>
#include "../../codecs/rt5645.h"
#include "../../codecs/rt5677.h"
#define MCLK_FOR_CODECS 12288000
static const struct snd_soc_dapm_widget mt8173_rt5650_rt5676_widgets[] = {
SND_SOC_DAPM_SPK("Speaker", NULL),
SND_SOC_DAPM_MIC("Int Mic", NULL),
SND_SOC_DAPM_HP("Headphone", NULL),
SND_SOC_DAPM_MIC("Headset Mic", NULL),
};
static const struct snd_soc_dapm_route mt8173_rt5650_rt5676_routes[] = {
{"Speaker", NULL, "SPOL"},
{"Speaker", NULL, "SPOR"},
{"Speaker", NULL, "Sub AIF2TX"}, /* IF2 ADC to 5650 */
{"Sub DMIC L1", NULL, "Int Mic"}, /* DMIC from 5676 */
{"Sub DMIC R1", NULL, "Int Mic"},
{"Headphone", NULL, "HPOL"},
{"Headphone", NULL, "HPOR"},
{"Headphone", NULL, "Sub AIF2TX"}, /* IF2 ADC to 5650 */
{"IN1P", NULL, "Headset Mic"},
{"IN1N", NULL, "Headset Mic"},
{"Sub AIF2RX", NULL, "Headset Mic"}, /* IF2 DAC from 5650 */
};
static const struct snd_kcontrol_new mt8173_rt5650_rt5676_controls[] = {
SOC_DAPM_PIN_SWITCH("Speaker"),
SOC_DAPM_PIN_SWITCH("Int Mic"),
SOC_DAPM_PIN_SWITCH("Headphone"),
SOC_DAPM_PIN_SWITCH("Headset Mic"),
};
static struct snd_soc_jack_pin mt8173_rt5650_rt5676_jack_pins[] = {
{
.pin = "Headphone",
.mask = SND_JACK_HEADPHONE,
},
{
.pin = "Headset Mic",
.mask = SND_JACK_MICROPHONE,
},
};
static int mt8173_rt5650_rt5676_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai *codec_dai;
int i, ret;
for_each_rtd_codec_dais(rtd, i, codec_dai) {
/* pll from mclk 12.288M */
ret = snd_soc_dai_set_pll(codec_dai, 0, 0, MCLK_FOR_CODECS,
params_rate(params) * 512);
if (ret)
return ret;
/* sysclk from pll */
ret = snd_soc_dai_set_sysclk(codec_dai, 1,
params_rate(params) * 512,
SND_SOC_CLOCK_IN);
if (ret)
return ret;
}
return 0;
}
static const struct snd_soc_ops mt8173_rt5650_rt5676_ops = {
.hw_params = mt8173_rt5650_rt5676_hw_params,
};
static struct snd_soc_jack mt8173_rt5650_rt5676_jack;
static int mt8173_rt5650_rt5676_init(struct snd_soc_pcm_runtime *runtime)
{
struct snd_soc_card *card = runtime->card;
struct snd_soc_component *component = asoc_rtd_to_codec(runtime, 0)->component;
struct snd_soc_component *component_sub = asoc_rtd_to_codec(runtime, 1)->component;
int ret;
rt5645_sel_asrc_clk_src(component,
RT5645_DA_STEREO_FILTER |
RT5645_AD_STEREO_FILTER,
RT5645_CLK_SEL_I2S1_ASRC);
rt5677_sel_asrc_clk_src(component_sub,
RT5677_DA_STEREO_FILTER |
RT5677_AD_STEREO1_FILTER,
RT5677_CLK_SEL_I2S1_ASRC);
rt5677_sel_asrc_clk_src(component_sub,
RT5677_AD_STEREO2_FILTER |
RT5677_I2S2_SOURCE,
RT5677_CLK_SEL_I2S2_ASRC);
/* enable jack detection */
ret = snd_soc_card_jack_new_pins(card, "Headset Jack",
SND_JACK_HEADPHONE | SND_JACK_MICROPHONE |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3,
&mt8173_rt5650_rt5676_jack,
mt8173_rt5650_rt5676_jack_pins,
ARRAY_SIZE(mt8173_rt5650_rt5676_jack_pins));
if (ret) {
dev_err(card->dev, "Can't new Headset Jack %d\n", ret);
return ret;
}
return rt5645_set_jack_detect(component,
&mt8173_rt5650_rt5676_jack,
&mt8173_rt5650_rt5676_jack,
&mt8173_rt5650_rt5676_jack);
}
enum {
DAI_LINK_PLAYBACK,
DAI_LINK_CAPTURE,
DAI_LINK_HDMI,
DAI_LINK_CODEC_I2S,
DAI_LINK_HDMI_I2S,
DAI_LINK_INTERCODEC
};
SND_SOC_DAILINK_DEFS(playback,
DAILINK_COMP_ARRAY(COMP_CPU("DL1")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture,
DAILINK_COMP_ARRAY(COMP_CPU("VUL")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(hdmi_pcm,
DAILINK_COMP_ARRAY(COMP_CPU("HDMI")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(codec,
DAILINK_COMP_ARRAY(COMP_CPU("I2S")),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "rt5645-aif1"),
COMP_CODEC(NULL, "rt5677-aif1")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(hdmi_be,
DAILINK_COMP_ARRAY(COMP_CPU("HDMIO")),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "i2s-hifi")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(intercodec,
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "rt5677-aif2")),
DAILINK_COMP_ARRAY(COMP_DUMMY()));
/* Digital audio interface glue - connects codec <---> CPU */
static struct snd_soc_dai_link mt8173_rt5650_rt5676_dais[] = {
/* Front End DAI links */
[DAI_LINK_PLAYBACK] = {
.name = "rt5650_rt5676 Playback",
.stream_name = "rt5650_rt5676 Playback",
.trigger = {SND_SOC_DPCM_TRIGGER_POST, SND_SOC_DPCM_TRIGGER_POST},
.dynamic = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(playback),
},
[DAI_LINK_CAPTURE] = {
.name = "rt5650_rt5676 Capture",
.stream_name = "rt5650_rt5676 Capture",
.trigger = {SND_SOC_DPCM_TRIGGER_POST, SND_SOC_DPCM_TRIGGER_POST},
.dynamic = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(capture),
},
[DAI_LINK_HDMI] = {
.name = "HDMI",
.stream_name = "HDMI PCM",
.trigger = {SND_SOC_DPCM_TRIGGER_POST, SND_SOC_DPCM_TRIGGER_POST},
.dynamic = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(hdmi_pcm),
},
/* Back End DAI links */
[DAI_LINK_CODEC_I2S] = {
.name = "Codec",
.no_pcm = 1,
.init = mt8173_rt5650_rt5676_init,
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS,
.ops = &mt8173_rt5650_rt5676_ops,
.ignore_pmdown_time = 1,
.dpcm_playback = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(codec),
},
[DAI_LINK_HDMI_I2S] = {
.name = "HDMI BE",
.no_pcm = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(hdmi_be),
},
/* rt5676 <-> rt5650 intercodec link: Sets rt5676 I2S2 as master */
[DAI_LINK_INTERCODEC] = {
.name = "rt5650_rt5676 intercodec",
.stream_name = "rt5650_rt5676 intercodec",
.no_pcm = 1,
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBM_CFM,
SND_SOC_DAILINK_REG(intercodec),
},
};
static struct snd_soc_codec_conf mt8173_rt5650_rt5676_codec_conf[] = {
{
.name_prefix = "Sub",
},
};
static struct snd_soc_card mt8173_rt5650_rt5676_card = {
.name = "mtk-rt5650-rt5676",
.owner = THIS_MODULE,
.dai_link = mt8173_rt5650_rt5676_dais,
.num_links = ARRAY_SIZE(mt8173_rt5650_rt5676_dais),
.codec_conf = mt8173_rt5650_rt5676_codec_conf,
.num_configs = ARRAY_SIZE(mt8173_rt5650_rt5676_codec_conf),
.controls = mt8173_rt5650_rt5676_controls,
.num_controls = ARRAY_SIZE(mt8173_rt5650_rt5676_controls),
.dapm_widgets = mt8173_rt5650_rt5676_widgets,
.num_dapm_widgets = ARRAY_SIZE(mt8173_rt5650_rt5676_widgets),
.dapm_routes = mt8173_rt5650_rt5676_routes,
.num_dapm_routes = ARRAY_SIZE(mt8173_rt5650_rt5676_routes),
};
static int mt8173_rt5650_rt5676_dev_probe(struct platform_device *pdev)
{
struct snd_soc_card *card = &mt8173_rt5650_rt5676_card;
struct device_node *platform_node;
struct snd_soc_dai_link *dai_link;
int i, ret;
platform_node = of_parse_phandle(pdev->dev.of_node,
"mediatek,platform", 0);
if (!platform_node) {
dev_err(&pdev->dev, "Property 'platform' missing or invalid\n");
return -EINVAL;
}
for_each_card_prelinks(card, i, dai_link) {
if (dai_link->platforms->name)
continue;
dai_link->platforms->of_node = platform_node;
}
mt8173_rt5650_rt5676_dais[DAI_LINK_CODEC_I2S].codecs[0].of_node =
of_parse_phandle(pdev->dev.of_node, "mediatek,audio-codec", 0);
if (!mt8173_rt5650_rt5676_dais[DAI_LINK_CODEC_I2S].codecs[0].of_node) {
dev_err(&pdev->dev,
"Property 'audio-codec' missing or invalid\n");
ret = -EINVAL;
goto put_node;
}
mt8173_rt5650_rt5676_dais[DAI_LINK_CODEC_I2S].codecs[1].of_node =
of_parse_phandle(pdev->dev.of_node, "mediatek,audio-codec", 1);
if (!mt8173_rt5650_rt5676_dais[DAI_LINK_CODEC_I2S].codecs[1].of_node) {
dev_err(&pdev->dev,
"Property 'audio-codec' missing or invalid\n");
ret = -EINVAL;
goto put_node;
}
mt8173_rt5650_rt5676_codec_conf[0].dlc.of_node =
mt8173_rt5650_rt5676_dais[DAI_LINK_CODEC_I2S].codecs[1].of_node;
mt8173_rt5650_rt5676_dais[DAI_LINK_INTERCODEC].codecs->of_node =
mt8173_rt5650_rt5676_dais[DAI_LINK_CODEC_I2S].codecs[1].of_node;
mt8173_rt5650_rt5676_dais[DAI_LINK_HDMI_I2S].codecs->of_node =
of_parse_phandle(pdev->dev.of_node, "mediatek,audio-codec", 2);
if (!mt8173_rt5650_rt5676_dais[DAI_LINK_HDMI_I2S].codecs->of_node) {
dev_err(&pdev->dev,
"Property 'audio-codec' missing or invalid\n");
ret = -EINVAL;
goto put_node;
}
card->dev = &pdev->dev;
ret = devm_snd_soc_register_card(&pdev->dev, card);
put_node:
of_node_put(platform_node);
return ret;
}
static const struct of_device_id mt8173_rt5650_rt5676_dt_match[] = {
{ .compatible = "mediatek,mt8173-rt5650-rt5676", },
{ }
};
MODULE_DEVICE_TABLE(of, mt8173_rt5650_rt5676_dt_match);
static struct platform_driver mt8173_rt5650_rt5676_driver = {
.driver = {
.name = "mtk-rt5650-rt5676",
.of_match_table = mt8173_rt5650_rt5676_dt_match,
.pm = &snd_soc_pm_ops,
},
.probe = mt8173_rt5650_rt5676_dev_probe,
};
module_platform_driver(mt8173_rt5650_rt5676_driver);
/* Module information */
MODULE_DESCRIPTION("MT8173 RT5650 and RT5676 SoC machine driver");
MODULE_AUTHOR("Koro Chen <[email protected]>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:mtk-rt5650-rt5676");
| linux-master | sound/soc/mediatek/mt8173/mt8173-rt5650-rt5676.c |
// SPDX-License-Identifier: GPL-2.0
//
// MediaTek ALSA SoC Audio DAI Hostless Control
//
// Copyright (c) 2022 MediaTek Inc.
// Author: Jiaxin Yu <[email protected]>
#include "mt8186-afe-common.h"
static const struct snd_pcm_hardware mt8186_hostless_hardware = {
.info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_MMAP_VALID),
.period_bytes_min = 256,
.period_bytes_max = 4 * 48 * 1024,
.periods_min = 2,
.periods_max = 256,
.buffer_bytes_max = 4 * 48 * 1024,
.fifo_size = 0,
};
/* dai component */
static const struct snd_soc_dapm_route mtk_dai_hostless_routes[] = {
/* Hostless ADDA Loopback */
{"ADDA_DL_CH1", "ADDA_UL_CH1 Switch", "Hostless LPBK DL"},
{"ADDA_DL_CH1", "ADDA_UL_CH2 Switch", "Hostless LPBK DL"},
{"ADDA_DL_CH2", "ADDA_UL_CH1 Switch", "Hostless LPBK DL"},
{"ADDA_DL_CH2", "ADDA_UL_CH2 Switch", "Hostless LPBK DL"},
{"I2S1_CH1", "ADDA_UL_CH1 Switch", "Hostless LPBK DL"},
{"I2S1_CH2", "ADDA_UL_CH2 Switch", "Hostless LPBK DL"},
{"I2S3_CH1", "ADDA_UL_CH1 Switch", "Hostless LPBK DL"},
{"I2S3_CH1", "ADDA_UL_CH2 Switch", "Hostless LPBK DL"},
{"I2S3_CH2", "ADDA_UL_CH1 Switch", "Hostless LPBK DL"},
{"I2S3_CH2", "ADDA_UL_CH2 Switch", "Hostless LPBK DL"},
{"Hostless LPBK UL", NULL, "ADDA_UL_Mux"},
/* Hostelss FM */
/* connsys_i2s to hw gain 1*/
{"Hostless FM UL", NULL, "Connsys I2S"},
{"HW_GAIN1_IN_CH1", "CONNSYS_I2S_CH1 Switch", "Hostless FM DL"},
{"HW_GAIN1_IN_CH2", "CONNSYS_I2S_CH2 Switch", "Hostless FM DL"},
/* hw gain to adda dl */
{"Hostless FM UL", NULL, "HW Gain 1 Out"},
{"ADDA_DL_CH1", "GAIN1_OUT_CH1 Switch", "Hostless FM DL"},
{"ADDA_DL_CH2", "GAIN1_OUT_CH2 Switch", "Hostless FM DL"},
/* hw gain to i2s3 */
{"I2S3_CH1", "GAIN1_OUT_CH1 Switch", "Hostless FM DL"},
{"I2S3_CH2", "GAIN1_OUT_CH2 Switch", "Hostless FM DL"},
/* hw gain to i2s1 */
{"I2S1_CH1", "GAIN1_OUT_CH1 Switch", "Hostless FM DL"},
{"I2S1_CH2", "GAIN1_OUT_CH2 Switch", "Hostless FM DL"},
/* Hostless_SRC */
{"ADDA_DL_CH1", "SRC_1_OUT_CH1 Switch", "Hostless_SRC_1_DL"},
{"ADDA_DL_CH2", "SRC_1_OUT_CH2 Switch", "Hostless_SRC_1_DL"},
{"I2S1_CH1", "SRC_1_OUT_CH1 Switch", "Hostless_SRC_1_DL"},
{"I2S1_CH2", "SRC_1_OUT_CH2 Switch", "Hostless_SRC_1_DL"},
{"I2S3_CH1", "SRC_1_OUT_CH1 Switch", "Hostless_SRC_1_DL"},
{"I2S3_CH2", "SRC_1_OUT_CH2 Switch", "Hostless_SRC_1_DL"},
{"Hostless_SRC_1_UL", NULL, "HW_SRC_1_Out"},
/* Hostless_SRC_bargein */
{"HW_SRC_1_IN_CH1", "I2S0_CH1 Switch", "Hostless_SRC_Bargein_DL"},
{"HW_SRC_1_IN_CH2", "I2S0_CH2 Switch", "Hostless_SRC_Bargein_DL"},
{"Hostless_SRC_Bargein_UL", NULL, "I2S0"},
/* Hostless AAudio */
{"Hostless HW Gain AAudio In", NULL, "HW Gain 2 In"},
{"Hostless SRC AAudio UL", NULL, "HW Gain 2 Out"},
{"HW_SRC_2_IN_CH1", "HW_GAIN2_OUT_CH1 Switch", "Hostless SRC AAudio DL"},
{"HW_SRC_2_IN_CH2", "HW_GAIN2_OUT_CH2 Switch", "Hostless SRC AAudio DL"},
};
/* dai ops */
static int mtk_dai_hostless_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct snd_pcm_runtime *runtime = substream->runtime;
int ret;
snd_soc_set_runtime_hwparams(substream, &mt8186_hostless_hardware);
ret = snd_pcm_hw_constraint_integer(runtime,
SNDRV_PCM_HW_PARAM_PERIODS);
if (ret < 0) {
dev_err(afe->dev, "snd_pcm_hw_constraint_integer failed\n");
return ret;
}
return 0;
}
static const struct snd_soc_dai_ops mtk_dai_hostless_ops = {
.startup = mtk_dai_hostless_startup,
};
/* dai driver */
#define MTK_HOSTLESS_RATES (SNDRV_PCM_RATE_8000_48000 |\
SNDRV_PCM_RATE_88200 |\
SNDRV_PCM_RATE_96000 |\
SNDRV_PCM_RATE_176400 |\
SNDRV_PCM_RATE_192000)
#define MTK_HOSTLESS_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver mtk_dai_hostless_driver[] = {
{
.name = "Hostless LPBK DAI",
.id = MT8186_DAI_HOSTLESS_LPBK,
.playback = {
.stream_name = "Hostless LPBK DL",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_HOSTLESS_RATES,
.formats = MTK_HOSTLESS_FORMATS,
},
.capture = {
.stream_name = "Hostless LPBK UL",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_HOSTLESS_RATES,
.formats = MTK_HOSTLESS_FORMATS,
},
.ops = &mtk_dai_hostless_ops,
},
{
.name = "Hostless FM DAI",
.id = MT8186_DAI_HOSTLESS_FM,
.playback = {
.stream_name = "Hostless FM DL",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_HOSTLESS_RATES,
.formats = MTK_HOSTLESS_FORMATS,
},
.capture = {
.stream_name = "Hostless FM UL",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_HOSTLESS_RATES,
.formats = MTK_HOSTLESS_FORMATS,
},
.ops = &mtk_dai_hostless_ops,
},
{
.name = "Hostless_SRC_1_DAI",
.id = MT8186_DAI_HOSTLESS_SRC_1,
.playback = {
.stream_name = "Hostless_SRC_1_DL",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_HOSTLESS_RATES,
.formats = MTK_HOSTLESS_FORMATS,
},
.capture = {
.stream_name = "Hostless_SRC_1_UL",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_HOSTLESS_RATES,
.formats = MTK_HOSTLESS_FORMATS,
},
.ops = &mtk_dai_hostless_ops,
},
{
.name = "Hostless_SRC_Bargein_DAI",
.id = MT8186_DAI_HOSTLESS_SRC_BARGEIN,
.playback = {
.stream_name = "Hostless_SRC_Bargein_DL",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_HOSTLESS_RATES,
.formats = MTK_HOSTLESS_FORMATS,
},
.capture = {
.stream_name = "Hostless_SRC_Bargein_UL",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_HOSTLESS_RATES,
.formats = MTK_HOSTLESS_FORMATS,
},
.ops = &mtk_dai_hostless_ops,
},
/* BE dai */
{
.name = "Hostless_UL1 DAI",
.id = MT8186_DAI_HOSTLESS_UL1,
.capture = {
.stream_name = "Hostless_UL1 UL",
.channels_min = 1,
.channels_max = 4,
.rates = MTK_HOSTLESS_RATES,
.formats = MTK_HOSTLESS_FORMATS,
},
.ops = &mtk_dai_hostless_ops,
},
{
.name = "Hostless_UL2 DAI",
.id = MT8186_DAI_HOSTLESS_UL2,
.capture = {
.stream_name = "Hostless_UL2 UL",
.channels_min = 1,
.channels_max = 4,
.rates = MTK_HOSTLESS_RATES,
.formats = MTK_HOSTLESS_FORMATS,
},
.ops = &mtk_dai_hostless_ops,
},
{
.name = "Hostless_UL3 DAI",
.id = MT8186_DAI_HOSTLESS_UL3,
.capture = {
.stream_name = "Hostless_UL3 UL",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_HOSTLESS_RATES,
.formats = MTK_HOSTLESS_FORMATS,
},
.ops = &mtk_dai_hostless_ops,
},
{
.name = "Hostless_UL5 DAI",
.id = MT8186_DAI_HOSTLESS_UL5,
.capture = {
.stream_name = "Hostless_UL5 UL",
.channels_min = 1,
.channels_max = 12,
.rates = MTK_HOSTLESS_RATES,
.formats = MTK_HOSTLESS_FORMATS,
},
.ops = &mtk_dai_hostless_ops,
},
{
.name = "Hostless_UL6 DAI",
.id = MT8186_DAI_HOSTLESS_UL6,
.capture = {
.stream_name = "Hostless_UL6 UL",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_HOSTLESS_RATES,
.formats = MTK_HOSTLESS_FORMATS,
},
.ops = &mtk_dai_hostless_ops,
},
{
.name = "Hostless HW Gain AAudio DAI",
.id = MT8186_DAI_HOSTLESS_HW_GAIN_AAUDIO,
.capture = {
.stream_name = "Hostless HW Gain AAudio In",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_HOSTLESS_RATES,
.formats = MTK_HOSTLESS_FORMATS,
},
.ops = &mtk_dai_hostless_ops,
},
{
.name = "Hostless SRC AAudio DAI",
.id = MT8186_DAI_HOSTLESS_SRC_AAUDIO,
.playback = {
.stream_name = "Hostless SRC AAudio DL",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_HOSTLESS_RATES,
.formats = MTK_HOSTLESS_FORMATS,
},
.capture = {
.stream_name = "Hostless SRC AAudio UL",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_HOSTLESS_RATES,
.formats = MTK_HOSTLESS_FORMATS,
},
.ops = &mtk_dai_hostless_ops,
},
};
int mt8186_dai_hostless_register(struct mtk_base_afe *afe)
{
struct mtk_base_afe_dai *dai;
dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
if (!dai)
return -ENOMEM;
list_add(&dai->list, &afe->sub_dais);
dai->dai_drivers = mtk_dai_hostless_driver;
dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_hostless_driver);
dai->dapm_routes = mtk_dai_hostless_routes;
dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_hostless_routes);
return 0;
}
| linux-master | sound/soc/mediatek/mt8186/mt8186-dai-hostless.c |
// SPDX-License-Identifier: GPL-2.0
//
// mt8186-afe-gpio.c -- Mediatek 8186 afe gpio ctrl
//
// Copyright (c) 2022 MediaTek Inc.
// Author: Jiaxin Yu <[email protected]>
#include <linux/gpio.h>
#include <linux/pinctrl/consumer.h>
#include "mt8186-afe-common.h"
#include "mt8186-afe-gpio.h"
static struct pinctrl *aud_pinctrl;
enum mt8186_afe_gpio {
MT8186_AFE_GPIO_CLK_MOSI_OFF,
MT8186_AFE_GPIO_CLK_MOSI_ON,
MT8186_AFE_GPIO_CLK_MISO_OFF,
MT8186_AFE_GPIO_CLK_MISO_ON,
MT8186_AFE_GPIO_DAT_MISO_OFF,
MT8186_AFE_GPIO_DAT_MISO_ON,
MT8186_AFE_GPIO_DAT_MOSI_OFF,
MT8186_AFE_GPIO_DAT_MOSI_ON,
MT8186_AFE_GPIO_I2S0_OFF,
MT8186_AFE_GPIO_I2S0_ON,
MT8186_AFE_GPIO_I2S1_OFF,
MT8186_AFE_GPIO_I2S1_ON,
MT8186_AFE_GPIO_I2S2_OFF,
MT8186_AFE_GPIO_I2S2_ON,
MT8186_AFE_GPIO_I2S3_OFF,
MT8186_AFE_GPIO_I2S3_ON,
MT8186_AFE_GPIO_TDM_OFF,
MT8186_AFE_GPIO_TDM_ON,
MT8186_AFE_GPIO_PCM_OFF,
MT8186_AFE_GPIO_PCM_ON,
MT8186_AFE_GPIO_GPIO_NUM
};
struct audio_gpio_attr {
const char *name;
bool gpio_prepare;
struct pinctrl_state *gpioctrl;
};
static struct audio_gpio_attr aud_gpios[MT8186_AFE_GPIO_GPIO_NUM] = {
[MT8186_AFE_GPIO_CLK_MOSI_OFF] = {"aud_clk_mosi_off", false, NULL},
[MT8186_AFE_GPIO_CLK_MOSI_ON] = {"aud_clk_mosi_on", false, NULL},
[MT8186_AFE_GPIO_CLK_MISO_OFF] = {"aud_clk_miso_off", false, NULL},
[MT8186_AFE_GPIO_CLK_MISO_ON] = {"aud_clk_miso_on", false, NULL},
[MT8186_AFE_GPIO_DAT_MISO_OFF] = {"aud_dat_miso_off", false, NULL},
[MT8186_AFE_GPIO_DAT_MISO_ON] = {"aud_dat_miso_on", false, NULL},
[MT8186_AFE_GPIO_DAT_MOSI_OFF] = {"aud_dat_mosi_off", false, NULL},
[MT8186_AFE_GPIO_DAT_MOSI_ON] = {"aud_dat_mosi_on", false, NULL},
[MT8186_AFE_GPIO_I2S0_OFF] = {"aud_gpio_i2s0_off", false, NULL},
[MT8186_AFE_GPIO_I2S0_ON] = {"aud_gpio_i2s0_on", false, NULL},
[MT8186_AFE_GPIO_I2S1_OFF] = {"aud_gpio_i2s1_off", false, NULL},
[MT8186_AFE_GPIO_I2S1_ON] = {"aud_gpio_i2s1_on", false, NULL},
[MT8186_AFE_GPIO_I2S2_OFF] = {"aud_gpio_i2s2_off", false, NULL},
[MT8186_AFE_GPIO_I2S2_ON] = {"aud_gpio_i2s2_on", false, NULL},
[MT8186_AFE_GPIO_I2S3_OFF] = {"aud_gpio_i2s3_off", false, NULL},
[MT8186_AFE_GPIO_I2S3_ON] = {"aud_gpio_i2s3_on", false, NULL},
[MT8186_AFE_GPIO_TDM_OFF] = {"aud_gpio_tdm_off", false, NULL},
[MT8186_AFE_GPIO_TDM_ON] = {"aud_gpio_tdm_on", false, NULL},
[MT8186_AFE_GPIO_PCM_OFF] = {"aud_gpio_pcm_off", false, NULL},
[MT8186_AFE_GPIO_PCM_ON] = {"aud_gpio_pcm_on", false, NULL},
};
static DEFINE_MUTEX(gpio_request_mutex);
int mt8186_afe_gpio_init(struct device *dev)
{
int i, j, ret;
aud_pinctrl = devm_pinctrl_get(dev);
if (IS_ERR(aud_pinctrl)) {
ret = PTR_ERR(aud_pinctrl);
dev_err(dev, "%s(), ret %d, cannot get aud_pinctrl!\n",
__func__, ret);
return ret;
}
for (i = 0; i < ARRAY_SIZE(aud_gpios); i++) {
aud_gpios[i].gpioctrl = pinctrl_lookup_state(aud_pinctrl,
aud_gpios[i].name);
if (IS_ERR(aud_gpios[i].gpioctrl)) {
ret = PTR_ERR(aud_gpios[i].gpioctrl);
dev_dbg(dev, "%s(), pinctrl_lookup_state %s fail, ret %d\n",
__func__, aud_gpios[i].name, ret);
} else {
aud_gpios[i].gpio_prepare = true;
}
}
/* gpio status init */
for (i = MT8186_DAI_ADDA; i <= MT8186_DAI_TDM_IN; i++) {
for (j = 0; j <= 1; j++)
mt8186_afe_gpio_request(dev, false, i, j);
}
return 0;
}
EXPORT_SYMBOL_GPL(mt8186_afe_gpio_init);
static int mt8186_afe_gpio_select(struct device *dev,
enum mt8186_afe_gpio type)
{
int ret = 0;
if (type < 0 || type >= MT8186_AFE_GPIO_GPIO_NUM) {
dev_dbg(dev, "%s(), error, invalid gpio type %d\n",
__func__, type);
return -EINVAL;
}
if (!aud_gpios[type].gpio_prepare) {
dev_dbg(dev, "%s(), error, gpio type %d not prepared\n",
__func__, type);
return -EIO;
}
ret = pinctrl_select_state(aud_pinctrl,
aud_gpios[type].gpioctrl);
if (ret) {
dev_dbg(dev, "%s(), error, can not set gpio type %d\n",
__func__, type);
return ret;
}
return 0;
}
static int mt8186_afe_gpio_adda_dl(struct device *dev, bool enable)
{
int ret;
if (enable) {
ret = mt8186_afe_gpio_select(dev, MT8186_AFE_GPIO_CLK_MOSI_ON);
if (ret) {
dev_dbg(dev, "%s(), MOSI CLK ON select fail!\n", __func__);
return ret;
}
ret = mt8186_afe_gpio_select(dev, MT8186_AFE_GPIO_DAT_MOSI_ON);
if (ret) {
dev_dbg(dev, "%s(), MOSI DAT ON select fail!\n", __func__);
return ret;
}
} else {
ret = mt8186_afe_gpio_select(dev, MT8186_AFE_GPIO_DAT_MOSI_OFF);
if (ret) {
dev_dbg(dev, "%s(), MOSI DAT OFF select fail!\n", __func__);
return ret;
}
ret = mt8186_afe_gpio_select(dev, MT8186_AFE_GPIO_CLK_MOSI_OFF);
if (ret) {
dev_dbg(dev, "%s(), MOSI CLK ON select fail!\n", __func__);
return ret;
}
}
return 0;
}
static int mt8186_afe_gpio_adda_ul(struct device *dev, bool enable)
{
int ret;
if (enable) {
ret = mt8186_afe_gpio_select(dev, MT8186_AFE_GPIO_CLK_MISO_ON);
if (ret) {
dev_dbg(dev, "%s(), MISO CLK ON select fail!\n", __func__);
return ret;
}
ret = mt8186_afe_gpio_select(dev, MT8186_AFE_GPIO_DAT_MISO_ON);
if (ret) {
dev_dbg(dev, "%s(), MISO DAT ON select fail!\n", __func__);
return ret;
}
} else {
ret = mt8186_afe_gpio_select(dev, MT8186_AFE_GPIO_DAT_MISO_OFF);
if (ret) {
dev_dbg(dev, "%s(), MISO DAT OFF select fail!\n", __func__);
return ret;
}
ret = mt8186_afe_gpio_select(dev, MT8186_AFE_GPIO_CLK_MISO_OFF);
if (ret) {
dev_dbg(dev, "%s(), MISO CLK OFF select fail!\n", __func__);
return ret;
}
}
return 0;
}
int mt8186_afe_gpio_request(struct device *dev, bool enable,
int dai, int uplink)
{
enum mt8186_afe_gpio sel;
int ret = -EINVAL;
mutex_lock(&gpio_request_mutex);
switch (dai) {
case MT8186_DAI_ADDA:
if (uplink)
ret = mt8186_afe_gpio_adda_ul(dev, enable);
else
ret = mt8186_afe_gpio_adda_dl(dev, enable);
goto unlock;
case MT8186_DAI_I2S_0:
sel = enable ? MT8186_AFE_GPIO_I2S0_ON : MT8186_AFE_GPIO_I2S0_OFF;
break;
case MT8186_DAI_I2S_1:
sel = enable ? MT8186_AFE_GPIO_I2S1_ON : MT8186_AFE_GPIO_I2S1_OFF;
break;
case MT8186_DAI_I2S_2:
sel = enable ? MT8186_AFE_GPIO_I2S2_ON : MT8186_AFE_GPIO_I2S2_OFF;
break;
case MT8186_DAI_I2S_3:
sel = enable ? MT8186_AFE_GPIO_I2S3_ON : MT8186_AFE_GPIO_I2S3_OFF;
break;
case MT8186_DAI_TDM_IN:
sel = enable ? MT8186_AFE_GPIO_TDM_ON : MT8186_AFE_GPIO_TDM_OFF;
break;
case MT8186_DAI_PCM:
sel = enable ? MT8186_AFE_GPIO_PCM_ON : MT8186_AFE_GPIO_PCM_OFF;
break;
default:
dev_dbg(dev, "%s(), invalid dai %d\n", __func__, dai);
goto unlock;
}
ret = mt8186_afe_gpio_select(dev, sel);
unlock:
mutex_unlock(&gpio_request_mutex);
return ret;
}
| linux-master | sound/soc/mediatek/mt8186/mt8186-afe-gpio.c |
// SPDX-License-Identifier: GPL-2.0
//
// mt8186-mt6366-da7219-max98357.c
// -- MT8186-MT6366-DA7219-MAX98357 ALSA SoC machine driver
//
// Copyright (c) 2022 MediaTek Inc.
// Author: Jiaxin Yu <[email protected]>
//
#include <linux/input.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <sound/jack.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include "../../codecs/da7219.h"
#include "../../codecs/mt6358.h"
#include "../common/mtk-afe-platform-driver.h"
#include "../common/mtk-dsp-sof-common.h"
#include "../common/mtk-soc-card.h"
#include "mt8186-afe-common.h"
#include "mt8186-afe-clk.h"
#include "mt8186-afe-gpio.h"
#include "mt8186-mt6366-common.h"
#define DA7219_CODEC_DAI "da7219-hifi"
#define DA7219_DEV_NAME "da7219.5-001a"
#define SOF_DMA_DL1 "SOF_DMA_DL1"
#define SOF_DMA_DL2 "SOF_DMA_DL2"
#define SOF_DMA_UL1 "SOF_DMA_UL1"
#define SOF_DMA_UL2 "SOF_DMA_UL2"
struct mt8186_mt6366_da7219_max98357_priv {
struct snd_soc_jack headset_jack, hdmi_jack;
};
/* Headset jack detection DAPM pins */
static struct snd_soc_jack_pin mt8186_jack_pins[] = {
{
.pin = "Headphones",
.mask = SND_JACK_HEADPHONE,
},
{
.pin = "Headset Mic",
.mask = SND_JACK_MICROPHONE,
},
{
.pin = "Line Out",
.mask = SND_JACK_LINEOUT,
},
};
static struct snd_soc_codec_conf mt8186_mt6366_da7219_max98357_codec_conf[] = {
{
.dlc = COMP_CODEC_CONF("mt6358-sound"),
.name_prefix = "Mt6366",
},
{
.dlc = COMP_CODEC_CONF("bt-sco"),
.name_prefix = "Mt8186 bt",
},
{
.dlc = COMP_CODEC_CONF("hdmi-audio-codec"),
.name_prefix = "Mt8186 hdmi",
},
};
static int mt8186_da7219_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_component *cmpnt_afe =
snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt_afe);
struct mtk_soc_card_data *soc_card_data =
snd_soc_card_get_drvdata(rtd->card);
struct mt8186_mt6366_da7219_max98357_priv *priv = soc_card_data->mach_priv;
struct snd_soc_jack *jack = &priv->headset_jack;
struct snd_soc_component *cmpnt_codec =
asoc_rtd_to_codec(rtd, 0)->component;
int ret;
ret = mt8186_dai_i2s_set_share(afe, "I2S1", "I2S0");
if (ret) {
dev_err(rtd->dev, "Failed to set up shared clocks\n");
return ret;
}
/* Enable Headset and 4 Buttons Jack detection */
ret = snd_soc_card_jack_new_pins(rtd->card, "Headset Jack",
SND_JACK_HEADSET | SND_JACK_BTN_0 |
SND_JACK_BTN_1 | SND_JACK_BTN_2 |
SND_JACK_BTN_3 | SND_JACK_LINEOUT,
jack, mt8186_jack_pins,
ARRAY_SIZE(mt8186_jack_pins));
if (ret) {
dev_err(rtd->dev, "Headset Jack creation failed: %d\n", ret);
return ret;
}
snd_jack_set_key(jack->jack, SND_JACK_BTN_0, KEY_PLAYPAUSE);
snd_jack_set_key(jack->jack, SND_JACK_BTN_1, KEY_VOLUMEUP);
snd_jack_set_key(jack->jack, SND_JACK_BTN_2, KEY_VOLUMEDOWN);
snd_jack_set_key(jack->jack, SND_JACK_BTN_3, KEY_VOICECOMMAND);
snd_soc_component_set_jack(cmpnt_codec, &priv->headset_jack, NULL);
return 0;
}
static int mt8186_da7219_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai *codec_dai;
unsigned int rate = params_rate(params);
unsigned int mclk_fs_ratio = 256;
unsigned int mclk_fs = rate * mclk_fs_ratio;
unsigned int freq;
int ret, j;
ret = snd_soc_dai_set_sysclk(asoc_rtd_to_cpu(rtd, 0), 0,
mclk_fs, SND_SOC_CLOCK_OUT);
if (ret < 0) {
dev_err(rtd->dev, "failed to set cpu dai sysclk: %d\n", ret);
return ret;
}
for_each_rtd_codec_dais(rtd, j, codec_dai) {
if (!strcmp(codec_dai->component->name, DA7219_DEV_NAME)) {
ret = snd_soc_dai_set_sysclk(codec_dai,
DA7219_CLKSRC_MCLK,
mclk_fs,
SND_SOC_CLOCK_IN);
if (ret < 0) {
dev_err(rtd->dev, "failed to set sysclk: %d\n",
ret);
return ret;
}
if ((rate % 8000) == 0)
freq = DA7219_PLL_FREQ_OUT_98304;
else
freq = DA7219_PLL_FREQ_OUT_90316;
ret = snd_soc_dai_set_pll(codec_dai, 0,
DA7219_SYSCLK_PLL_SRM,
0, freq);
if (ret) {
dev_err(rtd->dev, "failed to start PLL: %d\n",
ret);
return ret;
}
}
}
return 0;
}
static int mt8186_da7219_i2s_hw_free(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai *codec_dai;
int ret = 0, j;
for_each_rtd_codec_dais(rtd, j, codec_dai) {
if (!strcmp(codec_dai->component->name, DA7219_DEV_NAME)) {
ret = snd_soc_dai_set_pll(codec_dai,
0, DA7219_SYSCLK_MCLK, 0, 0);
if (ret < 0) {
dev_err(rtd->dev, "failed to stop PLL: %d\n",
ret);
return ret;
}
}
}
return 0;
}
static const struct snd_soc_ops mt8186_da7219_i2s_ops = {
.hw_params = mt8186_da7219_i2s_hw_params,
.hw_free = mt8186_da7219_i2s_hw_free,
};
static int mt8186_mt6366_da7219_max98357_hdmi_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_component *cmpnt_afe =
snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt_afe);
struct snd_soc_component *cmpnt_codec =
asoc_rtd_to_codec(rtd, 0)->component;
struct mtk_soc_card_data *soc_card_data =
snd_soc_card_get_drvdata(rtd->card);
struct mt8186_mt6366_da7219_max98357_priv *priv = soc_card_data->mach_priv;
int ret;
ret = mt8186_dai_i2s_set_share(afe, "I2S2", "I2S3");
if (ret) {
dev_err(rtd->dev, "Failed to set up shared clocks\n");
return ret;
}
ret = snd_soc_card_jack_new(rtd->card, "HDMI Jack", SND_JACK_LINEOUT, &priv->hdmi_jack);
if (ret) {
dev_err(rtd->dev, "HDMI Jack creation failed: %d\n", ret);
return ret;
}
return snd_soc_component_set_jack(cmpnt_codec, &priv->hdmi_jack, NULL);
}
static int mt8186_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
struct snd_pcm_hw_params *params,
snd_pcm_format_t fmt)
{
struct snd_interval *channels = hw_param_interval(params,
SNDRV_PCM_HW_PARAM_CHANNELS);
dev_dbg(rtd->dev, "%s(), fix format to %d\n", __func__, fmt);
/* fix BE i2s channel to 2 channel */
channels->min = 2;
channels->max = 2;
/* clean param mask first */
snd_mask_reset_range(hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT),
0, (__force unsigned int)SNDRV_PCM_FORMAT_LAST);
params_set_format(params, fmt);
return 0;
}
static int mt8186_i2s_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
struct snd_pcm_hw_params *params)
{
return mt8186_hw_params_fixup(rtd, params, SNDRV_PCM_FORMAT_S32_LE);
}
static int mt8186_anx7625_i2s_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
struct snd_pcm_hw_params *params)
{
return mt8186_hw_params_fixup(rtd, params, SNDRV_PCM_FORMAT_S24_LE);
}
/* fixup the BE DAI link to match any values from topology */
static int mt8186_sof_dai_link_fixup(struct snd_soc_pcm_runtime *rtd,
struct snd_pcm_hw_params *params)
{
int ret;
ret = mtk_sof_dai_link_fixup(rtd, params);
if (!strcmp(rtd->dai_link->name, "I2S0") ||
!strcmp(rtd->dai_link->name, "I2S1") ||
!strcmp(rtd->dai_link->name, "I2S2"))
mt8186_i2s_hw_params_fixup(rtd, params);
else if (!strcmp(rtd->dai_link->name, "I2S3"))
mt8186_anx7625_i2s_hw_params_fixup(rtd, params);
return ret;
}
static int mt8186_mt6366_da7219_max98357_playback_startup(struct snd_pcm_substream *substream)
{
static const unsigned int rates[] = {
48000
};
static const unsigned int channels[] = {
2
};
static const struct snd_pcm_hw_constraint_list constraints_rates = {
.count = ARRAY_SIZE(rates),
.list = rates,
.mask = 0,
};
static const struct snd_pcm_hw_constraint_list constraints_channels = {
.count = ARRAY_SIZE(channels),
.list = channels,
.mask = 0,
};
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_pcm_runtime *runtime = substream->runtime;
int ret;
ret = snd_pcm_hw_constraint_list(runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
&constraints_rates);
if (ret < 0) {
dev_err(rtd->dev, "hw_constraint_list rate failed\n");
return ret;
}
ret = snd_pcm_hw_constraint_list(runtime, 0,
SNDRV_PCM_HW_PARAM_CHANNELS,
&constraints_channels);
if (ret < 0) {
dev_err(rtd->dev, "hw_constraint_list channel failed\n");
return ret;
}
return 0;
}
static const struct snd_soc_ops mt8186_mt6366_da7219_max98357_playback_ops = {
.startup = mt8186_mt6366_da7219_max98357_playback_startup,
};
static int mt8186_mt6366_da7219_max98357_capture_startup(struct snd_pcm_substream *substream)
{
static const unsigned int rates[] = {
48000
};
static const unsigned int channels[] = {
1, 2
};
static const struct snd_pcm_hw_constraint_list constraints_rates = {
.count = ARRAY_SIZE(rates),
.list = rates,
.mask = 0,
};
static const struct snd_pcm_hw_constraint_list constraints_channels = {
.count = ARRAY_SIZE(channels),
.list = channels,
.mask = 0,
};
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_pcm_runtime *runtime = substream->runtime;
int ret;
ret = snd_pcm_hw_constraint_list(runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
&constraints_rates);
if (ret < 0) {
dev_err(rtd->dev, "hw_constraint_list rate failed\n");
return ret;
}
ret = snd_pcm_hw_constraint_list(runtime, 0,
SNDRV_PCM_HW_PARAM_CHANNELS,
&constraints_channels);
if (ret < 0) {
dev_err(rtd->dev, "hw_constraint_list channel failed\n");
return ret;
}
return 0;
}
static const struct snd_soc_ops mt8186_mt6366_da7219_max98357_capture_ops = {
.startup = mt8186_mt6366_da7219_max98357_capture_startup,
};
/* FE */
SND_SOC_DAILINK_DEFS(playback1,
DAILINK_COMP_ARRAY(COMP_CPU("DL1")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(playback12,
DAILINK_COMP_ARRAY(COMP_CPU("DL12")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(playback2,
DAILINK_COMP_ARRAY(COMP_CPU("DL2")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(playback3,
DAILINK_COMP_ARRAY(COMP_CPU("DL3")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(playback4,
DAILINK_COMP_ARRAY(COMP_CPU("DL4")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(playback5,
DAILINK_COMP_ARRAY(COMP_CPU("DL5")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(playback6,
DAILINK_COMP_ARRAY(COMP_CPU("DL6")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(playback7,
DAILINK_COMP_ARRAY(COMP_CPU("DL7")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(playback8,
DAILINK_COMP_ARRAY(COMP_CPU("DL8")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture1,
DAILINK_COMP_ARRAY(COMP_CPU("UL1")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture2,
DAILINK_COMP_ARRAY(COMP_CPU("UL2")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture3,
DAILINK_COMP_ARRAY(COMP_CPU("UL3")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture4,
DAILINK_COMP_ARRAY(COMP_CPU("UL4")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture5,
DAILINK_COMP_ARRAY(COMP_CPU("UL5")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture6,
DAILINK_COMP_ARRAY(COMP_CPU("UL6")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture7,
DAILINK_COMP_ARRAY(COMP_CPU("UL7")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
/* hostless */
SND_SOC_DAILINK_DEFS(hostless_lpbk,
DAILINK_COMP_ARRAY(COMP_CPU("Hostless LPBK DAI")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(hostless_fm,
DAILINK_COMP_ARRAY(COMP_CPU("Hostless FM DAI")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(hostless_src1,
DAILINK_COMP_ARRAY(COMP_CPU("Hostless_SRC_1_DAI")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(hostless_src_bargein,
DAILINK_COMP_ARRAY(COMP_CPU("Hostless_SRC_Bargein_DAI")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
/* BE */
SND_SOC_DAILINK_DEFS(adda,
DAILINK_COMP_ARRAY(COMP_CPU("ADDA")),
DAILINK_COMP_ARRAY(COMP_CODEC("mt6358-sound",
"mt6358-snd-codec-aif1"),
COMP_CODEC("dmic-codec",
"dmic-hifi")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(i2s0,
DAILINK_COMP_ARRAY(COMP_CPU("I2S0")),
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(i2s1,
DAILINK_COMP_ARRAY(COMP_CPU("I2S1")),
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(i2s2,
DAILINK_COMP_ARRAY(COMP_CPU("I2S2")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(i2s3,
DAILINK_COMP_ARRAY(COMP_CPU("I2S3")),
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(hw_gain1,
DAILINK_COMP_ARRAY(COMP_CPU("HW Gain 1")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(hw_gain2,
DAILINK_COMP_ARRAY(COMP_CPU("HW Gain 2")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(hw_src1,
DAILINK_COMP_ARRAY(COMP_CPU("HW_SRC_1")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(hw_src2,
DAILINK_COMP_ARRAY(COMP_CPU("HW_SRC_2")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(connsys_i2s,
DAILINK_COMP_ARRAY(COMP_CPU("CONNSYS_I2S")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(pcm1,
DAILINK_COMP_ARRAY(COMP_CPU("PCM 1")),
DAILINK_COMP_ARRAY(COMP_CODEC("bt-sco", "bt-sco-pcm-wb")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(tdm_in,
DAILINK_COMP_ARRAY(COMP_CPU("TDM IN")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
/* hostless */
SND_SOC_DAILINK_DEFS(hostless_ul1,
DAILINK_COMP_ARRAY(COMP_CPU("Hostless_UL1 DAI")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(hostless_ul2,
DAILINK_COMP_ARRAY(COMP_CPU("Hostless_UL2 DAI")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(hostless_ul3,
DAILINK_COMP_ARRAY(COMP_CPU("Hostless_UL3 DAI")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(hostless_ul5,
DAILINK_COMP_ARRAY(COMP_CPU("Hostless_UL5 DAI")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(hostless_ul6,
DAILINK_COMP_ARRAY(COMP_CPU("Hostless_UL6 DAI")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(hostless_hw_gain_aaudio,
DAILINK_COMP_ARRAY(COMP_CPU("Hostless HW Gain AAudio DAI")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(hostless_src_aaudio,
DAILINK_COMP_ARRAY(COMP_CPU("Hostless SRC AAudio DAI")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(AFE_SOF_DL1,
DAILINK_COMP_ARRAY(COMP_CPU("SOF_DL1")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(AFE_SOF_DL2,
DAILINK_COMP_ARRAY(COMP_CPU("SOF_DL2")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(AFE_SOF_UL1,
DAILINK_COMP_ARRAY(COMP_CPU("SOF_UL1")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(AFE_SOF_UL2,
DAILINK_COMP_ARRAY(COMP_CPU("SOF_UL2")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
static const struct sof_conn_stream g_sof_conn_streams[] = {
{ "I2S1", "AFE_SOF_DL1", SOF_DMA_DL1, SNDRV_PCM_STREAM_PLAYBACK},
{ "I2S3", "AFE_SOF_DL2", SOF_DMA_DL2, SNDRV_PCM_STREAM_PLAYBACK},
{ "Primary Codec", "AFE_SOF_UL1", SOF_DMA_UL1, SNDRV_PCM_STREAM_CAPTURE},
{ "I2S0", "AFE_SOF_UL2", SOF_DMA_UL2, SNDRV_PCM_STREAM_CAPTURE},
};
static struct snd_soc_dai_link mt8186_mt6366_da7219_max98357_dai_links[] = {
/* Front End DAI links */
{
.name = "Playback_1",
.stream_name = "Playback_1",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
.dpcm_merged_format = 1,
.dpcm_merged_chan = 1,
.dpcm_merged_rate = 1,
.ops = &mt8186_mt6366_da7219_max98357_playback_ops,
SND_SOC_DAILINK_REG(playback1),
},
{
.name = "Playback_12",
.stream_name = "Playback_12",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(playback12),
},
{
.name = "Playback_2",
.stream_name = "Playback_2",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
.dpcm_merged_format = 1,
.dpcm_merged_chan = 1,
.dpcm_merged_rate = 1,
SND_SOC_DAILINK_REG(playback2),
},
{
.name = "Playback_3",
.stream_name = "Playback_3",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
.dpcm_merged_format = 1,
.dpcm_merged_chan = 1,
.dpcm_merged_rate = 1,
.ops = &mt8186_mt6366_da7219_max98357_playback_ops,
SND_SOC_DAILINK_REG(playback3),
},
{
.name = "Playback_4",
.stream_name = "Playback_4",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(playback4),
},
{
.name = "Playback_5",
.stream_name = "Playback_5",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(playback5),
},
{
.name = "Playback_6",
.stream_name = "Playback_6",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(playback6),
},
{
.name = "Playback_7",
.stream_name = "Playback_7",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(playback7),
},
{
.name = "Playback_8",
.stream_name = "Playback_8",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(playback8),
},
{
.name = "Capture_1",
.stream_name = "Capture_1",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(capture1),
},
{
.name = "Capture_2",
.stream_name = "Capture_2",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_capture = 1,
.dpcm_merged_format = 1,
.dpcm_merged_chan = 1,
.dpcm_merged_rate = 1,
.ops = &mt8186_mt6366_da7219_max98357_capture_ops,
SND_SOC_DAILINK_REG(capture2),
},
{
.name = "Capture_3",
.stream_name = "Capture_3",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(capture3),
},
{
.name = "Capture_4",
.stream_name = "Capture_4",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_capture = 1,
.dpcm_merged_format = 1,
.dpcm_merged_chan = 1,
.dpcm_merged_rate = 1,
.ops = &mt8186_mt6366_da7219_max98357_capture_ops,
SND_SOC_DAILINK_REG(capture4),
},
{
.name = "Capture_5",
.stream_name = "Capture_5",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(capture5),
},
{
.name = "Capture_6",
.stream_name = "Capture_6",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_capture = 1,
.dpcm_merged_format = 1,
.dpcm_merged_chan = 1,
.dpcm_merged_rate = 1,
SND_SOC_DAILINK_REG(capture6),
},
{
.name = "Capture_7",
.stream_name = "Capture_7",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(capture7),
},
{
.name = "Hostless_LPBK",
.stream_name = "Hostless_LPBK",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(hostless_lpbk),
},
{
.name = "Hostless_FM",
.stream_name = "Hostless_FM",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(hostless_fm),
},
{
.name = "Hostless_SRC_1",
.stream_name = "Hostless_SRC_1",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(hostless_src1),
},
{
.name = "Hostless_SRC_Bargein",
.stream_name = "Hostless_SRC_Bargein",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(hostless_src_bargein),
},
{
.name = "Hostless_HW_Gain_AAudio",
.stream_name = "Hostless_HW_Gain_AAudio",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(hostless_hw_gain_aaudio),
},
{
.name = "Hostless_SRC_AAudio",
.stream_name = "Hostless_SRC_AAudio",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(hostless_src_aaudio),
},
/* Back End DAI links */
{
.name = "Primary Codec",
.no_pcm = 1,
.dpcm_playback = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
.init = mt8186_mt6366_init,
SND_SOC_DAILINK_REG(adda),
},
{
.name = "I2S3",
.no_pcm = 1,
.dai_fmt = SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_IB_IF |
SND_SOC_DAIFMT_CBM_CFM,
.dpcm_playback = 1,
.ignore_suspend = 1,
.init = mt8186_mt6366_da7219_max98357_hdmi_init,
.be_hw_params_fixup = mt8186_anx7625_i2s_hw_params_fixup,
SND_SOC_DAILINK_REG(i2s3),
},
{
.name = "I2S0",
.no_pcm = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
.be_hw_params_fixup = mt8186_i2s_hw_params_fixup,
.ops = &mt8186_da7219_i2s_ops,
SND_SOC_DAILINK_REG(i2s0),
},
{
.name = "I2S1",
.no_pcm = 1,
.dpcm_playback = 1,
.ignore_suspend = 1,
.be_hw_params_fixup = mt8186_i2s_hw_params_fixup,
.init = mt8186_da7219_init,
.ops = &mt8186_da7219_i2s_ops,
SND_SOC_DAILINK_REG(i2s1),
},
{
.name = "I2S2",
.no_pcm = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
.be_hw_params_fixup = mt8186_i2s_hw_params_fixup,
SND_SOC_DAILINK_REG(i2s2),
},
{
.name = "HW Gain 1",
.no_pcm = 1,
.dpcm_playback = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(hw_gain1),
},
{
.name = "HW Gain 2",
.no_pcm = 1,
.dpcm_playback = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(hw_gain2),
},
{
.name = "HW_SRC_1",
.no_pcm = 1,
.dpcm_playback = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(hw_src1),
},
{
.name = "HW_SRC_2",
.no_pcm = 1,
.dpcm_playback = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(hw_src2),
},
{
.name = "CONNSYS_I2S",
.no_pcm = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(connsys_i2s),
},
{
.name = "PCM 1",
.dai_fmt = SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_NB_IF,
.no_pcm = 1,
.dpcm_playback = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(pcm1),
},
{
.name = "TDM IN",
.no_pcm = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(tdm_in),
},
/* dummy BE for ul memif to record from dl memif */
{
.name = "Hostless_UL1",
.no_pcm = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(hostless_ul1),
},
{
.name = "Hostless_UL2",
.no_pcm = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(hostless_ul2),
},
{
.name = "Hostless_UL3",
.no_pcm = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(hostless_ul3),
},
{
.name = "Hostless_UL5",
.no_pcm = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(hostless_ul5),
},
{
.name = "Hostless_UL6",
.no_pcm = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(hostless_ul6),
},
/* SOF BE */
{
.name = "AFE_SOF_DL1",
.no_pcm = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(AFE_SOF_DL1),
},
{
.name = "AFE_SOF_DL2",
.no_pcm = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(AFE_SOF_DL2),
},
{
.name = "AFE_SOF_UL1",
.no_pcm = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(AFE_SOF_UL1),
},
{
.name = "AFE_SOF_UL2",
.no_pcm = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(AFE_SOF_UL2),
},
};
static const struct snd_soc_dapm_widget
mt8186_mt6366_da7219_max98357_widgets[] = {
SND_SOC_DAPM_SPK("Speakers", NULL),
SND_SOC_DAPM_HP("Headphones", NULL),
SND_SOC_DAPM_MIC("Headset Mic", NULL),
SND_SOC_DAPM_LINE("Line Out", NULL),
SND_SOC_DAPM_OUTPUT("HDMI1"),
SND_SOC_DAPM_MIXER(SOF_DMA_DL1, SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER(SOF_DMA_DL2, SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER(SOF_DMA_UL1, SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER(SOF_DMA_UL2, SND_SOC_NOPM, 0, 0, NULL, 0),
};
static const struct snd_soc_dapm_route
mt8186_mt6366_da7219_max98357_routes[] = {
/* SPK */
{ "Speakers", NULL, "Speaker"},
/* Headset */
{ "Headphones", NULL, "HPL" },
{ "Headphones", NULL, "HPR" },
{ "MIC", NULL, "Headset Mic" },
/* HDMI */
{ "HDMI1", NULL, "TX"},
/* SOF Uplink */
{SOF_DMA_UL1, NULL, "UL1_CH1"},
{SOF_DMA_UL1, NULL, "UL1_CH2"},
{SOF_DMA_UL2, NULL, "UL2_CH1"},
{SOF_DMA_UL2, NULL, "UL2_CH2"},
/* SOF Downlink */
{"DSP_DL1_VIRT", NULL, SOF_DMA_DL1},
{"DSP_DL2_VIRT", NULL, SOF_DMA_DL2},
};
static const struct snd_kcontrol_new
mt8186_mt6366_da7219_max98357_controls[] = {
SOC_DAPM_PIN_SWITCH("Speakers"),
SOC_DAPM_PIN_SWITCH("Headphones"),
SOC_DAPM_PIN_SWITCH("Headset Mic"),
SOC_DAPM_PIN_SWITCH("Line Out"),
SOC_DAPM_PIN_SWITCH("HDMI1"),
};
static struct snd_soc_card mt8186_mt6366_da7219_max98357_soc_card = {
.name = "mt8186_da7219_max98357",
.owner = THIS_MODULE,
.dai_link = mt8186_mt6366_da7219_max98357_dai_links,
.num_links = ARRAY_SIZE(mt8186_mt6366_da7219_max98357_dai_links),
.controls = mt8186_mt6366_da7219_max98357_controls,
.num_controls = ARRAY_SIZE(mt8186_mt6366_da7219_max98357_controls),
.dapm_widgets = mt8186_mt6366_da7219_max98357_widgets,
.num_dapm_widgets = ARRAY_SIZE(mt8186_mt6366_da7219_max98357_widgets),
.dapm_routes = mt8186_mt6366_da7219_max98357_routes,
.num_dapm_routes = ARRAY_SIZE(mt8186_mt6366_da7219_max98357_routes),
.codec_conf = mt8186_mt6366_da7219_max98357_codec_conf,
.num_configs = ARRAY_SIZE(mt8186_mt6366_da7219_max98357_codec_conf),
};
static int mt8186_mt6366_da7219_max98357_dev_probe(struct platform_device *pdev)
{
struct snd_soc_card *card;
struct snd_soc_dai_link *dai_link;
struct mtk_soc_card_data *soc_card_data;
struct mt8186_mt6366_da7219_max98357_priv *mach_priv;
struct device_node *platform_node, *headset_codec, *playback_codec, *adsp_node;
int sof_on = 0;
int ret, i;
card = (struct snd_soc_card *)device_get_match_data(&pdev->dev);
if (!card)
return -EINVAL;
card->dev = &pdev->dev;
soc_card_data = devm_kzalloc(&pdev->dev, sizeof(*soc_card_data), GFP_KERNEL);
if (!soc_card_data)
return -ENOMEM;
mach_priv = devm_kzalloc(&pdev->dev, sizeof(*mach_priv), GFP_KERNEL);
if (!mach_priv)
return -ENOMEM;
soc_card_data->mach_priv = mach_priv;
adsp_node = of_parse_phandle(pdev->dev.of_node, "mediatek,adsp", 0);
if (adsp_node) {
struct mtk_sof_priv *sof_priv;
sof_priv = devm_kzalloc(&pdev->dev, sizeof(*sof_priv), GFP_KERNEL);
if (!sof_priv) {
ret = -ENOMEM;
goto err_adsp_node;
}
sof_priv->conn_streams = g_sof_conn_streams;
sof_priv->num_streams = ARRAY_SIZE(g_sof_conn_streams);
sof_priv->sof_dai_link_fixup = mt8186_sof_dai_link_fixup;
soc_card_data->sof_priv = sof_priv;
card->probe = mtk_sof_card_probe;
card->late_probe = mtk_sof_card_late_probe;
if (!card->topology_shortname_created) {
snprintf(card->topology_shortname, 32, "sof-%s", card->name);
card->topology_shortname_created = true;
}
card->name = card->topology_shortname;
sof_on = 1;
} else {
dev_dbg(&pdev->dev, "Probe without adsp\n");
}
if (of_property_read_bool(pdev->dev.of_node, "mediatek,dai-link")) {
ret = mtk_sof_dailink_parse_of(card, pdev->dev.of_node,
"mediatek,dai-link",
mt8186_mt6366_da7219_max98357_dai_links,
ARRAY_SIZE(mt8186_mt6366_da7219_max98357_dai_links));
if (ret) {
dev_dbg(&pdev->dev, "Parse dai-link fail\n");
goto err_adsp_node;
}
} else {
if (!sof_on)
card->num_links = ARRAY_SIZE(mt8186_mt6366_da7219_max98357_dai_links)
- ARRAY_SIZE(g_sof_conn_streams);
}
platform_node = of_parse_phandle(pdev->dev.of_node, "mediatek,platform", 0);
if (!platform_node) {
ret = -EINVAL;
dev_err_probe(&pdev->dev, ret, "Property 'platform' missing or invalid\n");
goto err_platform_node;
}
playback_codec = of_get_child_by_name(pdev->dev.of_node, "playback-codecs");
if (!playback_codec) {
ret = -EINVAL;
dev_err_probe(&pdev->dev, ret, "Property 'speaker-codecs' missing or invalid\n");
goto err_playback_codec;
}
headset_codec = of_get_child_by_name(pdev->dev.of_node, "headset-codec");
if (!headset_codec) {
ret = -EINVAL;
dev_err_probe(&pdev->dev, ret, "Property 'headset-codec' missing or invalid\n");
goto err_headset_codec;
}
for_each_card_prelinks(card, i, dai_link) {
ret = mt8186_mt6366_card_set_be_link(card, dai_link, playback_codec, "I2S3");
if (ret) {
dev_err_probe(&pdev->dev, ret, "%s set speaker_codec fail\n",
dai_link->name);
goto err_probe;
}
ret = mt8186_mt6366_card_set_be_link(card, dai_link, headset_codec, "I2S0");
if (ret) {
dev_err_probe(&pdev->dev, ret, "%s set headset_codec fail\n",
dai_link->name);
goto err_probe;
}
ret = mt8186_mt6366_card_set_be_link(card, dai_link, headset_codec, "I2S1");
if (ret) {
dev_err_probe(&pdev->dev, ret, "%s set headset_codec fail\n",
dai_link->name);
goto err_probe;
}
if (!strncmp(dai_link->name, "AFE_SOF", strlen("AFE_SOF")) && sof_on)
dai_link->platforms->of_node = adsp_node;
if (!dai_link->platforms->name && !dai_link->platforms->of_node)
dai_link->platforms->of_node = platform_node;
}
snd_soc_card_set_drvdata(card, soc_card_data);
ret = mt8186_afe_gpio_init(&pdev->dev);
if (ret) {
dev_err_probe(&pdev->dev, ret, "%s init gpio error\n", __func__);
goto err_probe;
}
ret = devm_snd_soc_register_card(&pdev->dev, card);
if (ret)
dev_err_probe(&pdev->dev, ret, "%s snd_soc_register_card fail\n", __func__);
err_probe:
of_node_put(headset_codec);
err_headset_codec:
of_node_put(playback_codec);
err_playback_codec:
of_node_put(platform_node);
err_platform_node:
err_adsp_node:
of_node_put(adsp_node);
return ret;
}
#if IS_ENABLED(CONFIG_OF)
static const struct of_device_id mt8186_mt6366_da7219_max98357_dt_match[] = {
{ .compatible = "mediatek,mt8186-mt6366-da7219-max98357-sound",
.data = &mt8186_mt6366_da7219_max98357_soc_card,
},
{}
};
MODULE_DEVICE_TABLE(of, mt8186_mt6366_da7219_max98357_dt_match);
#endif
static struct platform_driver mt8186_mt6366_da7219_max98357_driver = {
.driver = {
.name = "mt8186_mt6366_da7219_max98357",
#if IS_ENABLED(CONFIG_OF)
.of_match_table = mt8186_mt6366_da7219_max98357_dt_match,
#endif
.pm = &snd_soc_pm_ops,
},
.probe = mt8186_mt6366_da7219_max98357_dev_probe,
};
module_platform_driver(mt8186_mt6366_da7219_max98357_driver);
/* Module information */
MODULE_DESCRIPTION("MT8186-MT6366-DA7219-MAX98357 ALSA SoC machine driver");
MODULE_AUTHOR("Jiaxin Yu <[email protected]>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("mt8186_mt6366_da7219_max98357 soc card");
| linux-master | sound/soc/mediatek/mt8186/mt8186-mt6366-da7219-max98357.c |
// SPDX-License-Identifier: GPL-2.0
//
// MediaTek ALSA SoC Audio DAI I2S Control
//
// Copyright (c) 2022 MediaTek Inc.
// Author: Jiaxin Yu <[email protected]>
#include <linux/regmap.h>
#include <sound/pcm_params.h>
#include "mt8186-afe-common.h"
#include "mt8186-afe-gpio.h"
#include "mt8186-interconnection.h"
struct mtk_afe_pcm_priv {
unsigned int id;
unsigned int fmt;
unsigned int bck_invert;
unsigned int lck_invert;
};
enum aud_tx_lch_rpt {
AUD_TX_LCH_RPT_NO_REPEAT = 0,
AUD_TX_LCH_RPT_REPEAT = 1
};
enum aud_vbt_16k_mode {
AUD_VBT_16K_MODE_DISABLE = 0,
AUD_VBT_16K_MODE_ENABLE = 1
};
enum aud_ext_modem {
AUD_EXT_MODEM_SELECT_INTERNAL = 0,
AUD_EXT_MODEM_SELECT_EXTERNAL = 1
};
enum aud_pcm_sync_type {
/* bck sync length = 1 */
AUD_PCM_ONE_BCK_CYCLE_SYNC = 0,
/* bck sync length = PCM_INTF_CON1[9:13] */
AUD_PCM_EXTENDED_BCK_CYCLE_SYNC = 1
};
enum aud_bt_mode {
AUD_BT_MODE_DUAL_MIC_ON_TX = 0,
AUD_BT_MODE_SINGLE_MIC_ON_TX = 1
};
enum aud_pcm_afifo_src {
/* slave mode & external modem uses different crystal */
AUD_PCM_AFIFO_ASRC = 0,
/* slave mode & external modem uses the same crystal */
AUD_PCM_AFIFO_AFIFO = 1
};
enum aud_pcm_clock_source {
AUD_PCM_CLOCK_MASTER_MODE = 0,
AUD_PCM_CLOCK_SLAVE_MODE = 1
};
enum aud_pcm_wlen {
AUD_PCM_WLEN_PCM_32_BCK_CYCLES = 0,
AUD_PCM_WLEN_PCM_64_BCK_CYCLES = 1
};
enum aud_pcm_24bit {
AUD_PCM_24BIT_PCM_16_BITS = 0,
AUD_PCM_24BIT_PCM_24_BITS = 1
};
enum aud_pcm_mode {
AUD_PCM_MODE_PCM_MODE_8K = 0,
AUD_PCM_MODE_PCM_MODE_16K = 1,
AUD_PCM_MODE_PCM_MODE_32K = 2,
AUD_PCM_MODE_PCM_MODE_48K = 3,
};
enum aud_pcm_fmt {
AUD_PCM_FMT_I2S = 0,
AUD_PCM_FMT_EIAJ = 1,
AUD_PCM_FMT_PCM_MODE_A = 2,
AUD_PCM_FMT_PCM_MODE_B = 3
};
enum aud_bclk_out_inv {
AUD_BCLK_OUT_INV_NO_INVERSE = 0,
AUD_BCLK_OUT_INV_INVERSE = 1
};
enum aud_lrclk_out_inv {
AUD_LRCLK_OUT_INV_NO_INVERSE = 0,
AUD_LRCLK_OUT_INV_INVERSE = 1
};
enum aud_pcm_en {
AUD_PCM_EN_DISABLE = 0,
AUD_PCM_EN_ENABLE = 1
};
/* dai component */
static const struct snd_kcontrol_new mtk_pcm_1_playback_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN7,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN7,
I_DL2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN7_1,
I_DL4_CH1, 1, 0),
};
static const struct snd_kcontrol_new mtk_pcm_1_playback_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN8,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN8,
I_DL2_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN8_1,
I_DL4_CH2, 1, 0),
};
static int mtk_pcm_en_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
__func__, w->name, event);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
mt8186_afe_gpio_request(afe->dev, true, MT8186_DAI_PCM, 0);
break;
case SND_SOC_DAPM_POST_PMD:
mt8186_afe_gpio_request(afe->dev, false, MT8186_DAI_PCM, 0);
break;
}
return 0;
}
/* pcm in/out lpbk */
static const char * const pcm_lpbk_mux_map[] = {
"Normal", "Lpbk",
};
static int pcm_lpbk_mux_map_value[] = {
0, 1,
};
static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(pcm_in_lpbk_mux_map_enum,
PCM_INTF_CON1,
PCM_I2S_PCM_LOOPBACK_SFT,
1,
pcm_lpbk_mux_map,
pcm_lpbk_mux_map_value);
static const struct snd_kcontrol_new pcm_in_lpbk_mux_control =
SOC_DAPM_ENUM("PCM In Lpbk Select", pcm_in_lpbk_mux_map_enum);
static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(pcm_out_lpbk_mux_map_enum,
PCM_INTF_CON1,
PCM_I2S_PCM_LOOPBACK_SFT,
1,
pcm_lpbk_mux_map,
pcm_lpbk_mux_map_value);
static const struct snd_kcontrol_new pcm_out_lpbk_mux_control =
SOC_DAPM_ENUM("PCM Out Lpbk Select", pcm_out_lpbk_mux_map_enum);
static const struct snd_soc_dapm_widget mtk_dai_pcm_widgets[] = {
/* inter-connections */
SND_SOC_DAPM_MIXER("PCM_1_PB_CH1", SND_SOC_NOPM, 0, 0,
mtk_pcm_1_playback_ch1_mix,
ARRAY_SIZE(mtk_pcm_1_playback_ch1_mix)),
SND_SOC_DAPM_MIXER("PCM_1_PB_CH2", SND_SOC_NOPM, 0, 0,
mtk_pcm_1_playback_ch2_mix,
ARRAY_SIZE(mtk_pcm_1_playback_ch2_mix)),
SND_SOC_DAPM_SUPPLY("PCM_1_EN",
PCM_INTF_CON1, PCM_EN_SFT, 0,
mtk_pcm_en_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
/* pcm in lpbk */
SND_SOC_DAPM_MUX("PCM_In_Lpbk_Mux",
SND_SOC_NOPM, 0, 0, &pcm_in_lpbk_mux_control),
/* pcm out lpbk */
SND_SOC_DAPM_MUX("PCM_Out_Lpbk_Mux",
SND_SOC_NOPM, 0, 0, &pcm_out_lpbk_mux_control),
};
static const struct snd_soc_dapm_route mtk_dai_pcm_routes[] = {
{"PCM 1 Playback", NULL, "PCM_1_PB_CH1"},
{"PCM 1 Playback", NULL, "PCM_1_PB_CH2"},
{"PCM 1 Playback", NULL, "PCM_1_EN"},
{"PCM 1 Capture", NULL, "PCM_1_EN"},
{"PCM_1_PB_CH1", "DL2_CH1 Switch", "DL2"},
{"PCM_1_PB_CH2", "DL2_CH2 Switch", "DL2"},
{"PCM_1_PB_CH1", "DL4_CH1 Switch", "DL4"},
{"PCM_1_PB_CH2", "DL4_CH2 Switch", "DL4"},
/* pcm out lpbk */
{"PCM_Out_Lpbk_Mux", "Lpbk", "PCM 1 Playback"},
{"I2S0", NULL, "PCM_Out_Lpbk_Mux"},
/* pcm in lpbk */
{"PCM_In_Lpbk_Mux", "Lpbk", "PCM 1 Capture"},
{"I2S3", NULL, "PCM_In_Lpbk_Mux"},
};
/* dai ops */
static int mtk_dai_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8186_afe_private *afe_priv = afe->platform_priv;
struct snd_soc_dapm_widget *p = snd_soc_dai_get_widget_playback(dai);
struct snd_soc_dapm_widget *c = snd_soc_dai_get_widget_capture(dai);
int pcm_id = dai->id;
struct mtk_afe_pcm_priv *pcm_priv = afe_priv->dai_priv[pcm_id];
unsigned int rate = params_rate(params);
unsigned int rate_reg = mt8186_rate_transform(afe->dev, rate, dai->id);
snd_pcm_format_t format = params_format(params);
unsigned int data_width =
snd_pcm_format_width(format);
unsigned int wlen_width =
snd_pcm_format_physical_width(format);
unsigned int pcm_con = 0;
dev_dbg(afe->dev, "%s(), id %d, stream %d, widget active p %d, c %d\n",
__func__, dai->id, substream->stream, p->active, c->active);
dev_dbg(afe->dev, "%s(), rate %d, rate_reg %d, data_width %d, wlen_width %d\n",
__func__, rate, rate_reg, data_width, wlen_width);
if (p->active || c->active)
return 0;
switch (dai->id) {
case MT8186_DAI_PCM:
pcm_con |= AUD_TX_LCH_RPT_NO_REPEAT << PCM_TX_LCH_RPT_SFT;
pcm_con |= AUD_VBT_16K_MODE_DISABLE << PCM_VBT_16K_MODE_SFT;
pcm_con |= AUD_EXT_MODEM_SELECT_EXTERNAL << PCM_EXT_MODEM_SFT;
pcm_con |= AUD_PCM_ONE_BCK_CYCLE_SYNC << PCM_SYNC_TYPE_SFT;
pcm_con |= AUD_BT_MODE_DUAL_MIC_ON_TX << PCM_BT_MODE_SFT;
pcm_con |= AUD_PCM_AFIFO_AFIFO << PCM_BYP_ASRC_SFT;
pcm_con |= AUD_PCM_CLOCK_MASTER_MODE << PCM_SLAVE_SFT;
pcm_con |= 0 << PCM_SYNC_LENGTH_SFT;
/* sampling rate */
pcm_con |= rate_reg << PCM_MODE_SFT;
/* format */
pcm_con |= pcm_priv->fmt << PCM_FMT_SFT;
/* 24bit data width */
if (data_width > 16)
pcm_con |= AUD_PCM_24BIT_PCM_24_BITS << PCM_24BIT_SFT;
else
pcm_con |= AUD_PCM_24BIT_PCM_16_BITS << PCM_24BIT_SFT;
/* wlen width*/
if (wlen_width > 16)
pcm_con |= AUD_PCM_WLEN_PCM_64_BCK_CYCLES << PCM_WLEN_SFT;
else
pcm_con |= AUD_PCM_WLEN_PCM_32_BCK_CYCLES << PCM_WLEN_SFT;
/* clock invert */
pcm_con |= pcm_priv->lck_invert << PCM_SYNC_OUT_INV_SFT;
pcm_con |= pcm_priv->bck_invert << PCM_BCLK_OUT_INV_SFT;
regmap_update_bits(afe->regmap, PCM_INTF_CON1, 0xfffffffe, pcm_con);
break;
default:
dev_err(afe->dev, "%s(), id %d not support\n", __func__, dai->id);
return -EINVAL;
}
return 0;
}
static int mtk_dai_pcm_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8186_afe_private *afe_priv = afe->platform_priv;
struct mtk_afe_pcm_priv *pcm_priv = afe_priv->dai_priv[dai->id];
/* DAI mode*/
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
pcm_priv->fmt = AUD_PCM_FMT_I2S;
break;
case SND_SOC_DAIFMT_LEFT_J:
pcm_priv->fmt = AUD_PCM_FMT_EIAJ;
break;
case SND_SOC_DAIFMT_DSP_A:
pcm_priv->fmt = AUD_PCM_FMT_PCM_MODE_A;
break;
case SND_SOC_DAIFMT_DSP_B:
pcm_priv->fmt = AUD_PCM_FMT_PCM_MODE_B;
break;
default:
pcm_priv->fmt = AUD_PCM_FMT_I2S;
}
/* DAI clock inversion*/
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
pcm_priv->bck_invert = AUD_BCLK_OUT_INV_NO_INVERSE;
pcm_priv->lck_invert = AUD_LRCLK_OUT_INV_NO_INVERSE;
break;
case SND_SOC_DAIFMT_NB_IF:
pcm_priv->bck_invert = AUD_BCLK_OUT_INV_NO_INVERSE;
pcm_priv->lck_invert = AUD_BCLK_OUT_INV_INVERSE;
break;
case SND_SOC_DAIFMT_IB_NF:
pcm_priv->bck_invert = AUD_BCLK_OUT_INV_INVERSE;
pcm_priv->lck_invert = AUD_LRCLK_OUT_INV_NO_INVERSE;
break;
case SND_SOC_DAIFMT_IB_IF:
pcm_priv->bck_invert = AUD_BCLK_OUT_INV_INVERSE;
pcm_priv->lck_invert = AUD_BCLK_OUT_INV_INVERSE;
break;
default:
pcm_priv->bck_invert = AUD_BCLK_OUT_INV_NO_INVERSE;
pcm_priv->lck_invert = AUD_LRCLK_OUT_INV_NO_INVERSE;
break;
}
return 0;
}
static const struct snd_soc_dai_ops mtk_dai_pcm_ops = {
.hw_params = mtk_dai_pcm_hw_params,
.set_fmt = mtk_dai_pcm_set_fmt,
};
/* dai driver */
#define MTK_PCM_RATES (SNDRV_PCM_RATE_8000 |\
SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 |\
SNDRV_PCM_RATE_48000)
#define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver mtk_dai_pcm_driver[] = {
{
.name = "PCM 1",
.id = MT8186_DAI_PCM,
.playback = {
.stream_name = "PCM 1 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.capture = {
.stream_name = "PCM 1 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_dai_pcm_ops,
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
},
};
static struct mtk_afe_pcm_priv *init_pcm_priv_data(struct mtk_base_afe *afe)
{
struct mtk_afe_pcm_priv *pcm_priv;
pcm_priv = devm_kzalloc(afe->dev, sizeof(struct mtk_afe_pcm_priv),
GFP_KERNEL);
if (!pcm_priv)
return NULL;
pcm_priv->id = MT8186_DAI_PCM;
pcm_priv->fmt = AUD_PCM_FMT_I2S;
pcm_priv->bck_invert = AUD_BCLK_OUT_INV_NO_INVERSE;
pcm_priv->lck_invert = AUD_LRCLK_OUT_INV_NO_INVERSE;
return pcm_priv;
}
int mt8186_dai_pcm_register(struct mtk_base_afe *afe)
{
struct mt8186_afe_private *afe_priv = afe->platform_priv;
struct mtk_afe_pcm_priv *pcm_priv;
struct mtk_base_afe_dai *dai;
dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
if (!dai)
return -ENOMEM;
list_add(&dai->list, &afe->sub_dais);
dai->dai_drivers = mtk_dai_pcm_driver;
dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_pcm_driver);
dai->dapm_widgets = mtk_dai_pcm_widgets;
dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_pcm_widgets);
dai->dapm_routes = mtk_dai_pcm_routes;
dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_pcm_routes);
pcm_priv = init_pcm_priv_data(afe);
if (!pcm_priv)
return -ENOMEM;
afe_priv->dai_priv[MT8186_DAI_PCM] = pcm_priv;
return 0;
}
| linux-master | sound/soc/mediatek/mt8186/mt8186-dai-pcm.c |
// SPDX-License-Identifier: GPL-2.0
//
// mt8186-afe-clk.c -- Mediatek 8186 afe clock ctrl
//
// Copyright (c) 2022 MediaTek Inc.
// Author: Jiaxin Yu <[email protected]>
#include <linux/clk.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>
#include "mt8186-afe-common.h"
#include "mt8186-afe-clk.h"
#include "mt8186-audsys-clk.h"
static const char *aud_clks[CLK_NUM] = {
[CLK_AFE] = "aud_afe_clk",
[CLK_DAC] = "aud_dac_clk",
[CLK_DAC_PREDIS] = "aud_dac_predis_clk",
[CLK_ADC] = "aud_adc_clk",
[CLK_TML] = "aud_tml_clk",
[CLK_APLL22M] = "aud_apll22m_clk",
[CLK_APLL24M] = "aud_apll24m_clk",
[CLK_APLL1_TUNER] = "aud_apll_tuner_clk",
[CLK_APLL2_TUNER] = "aud_apll2_tuner_clk",
[CLK_TDM] = "aud_tdm_clk",
[CLK_NLE] = "aud_nle_clk",
[CLK_DAC_HIRES] = "aud_dac_hires_clk",
[CLK_ADC_HIRES] = "aud_adc_hires_clk",
[CLK_I2S1_BCLK] = "aud_i2s1_bclk",
[CLK_I2S2_BCLK] = "aud_i2s2_bclk",
[CLK_I2S3_BCLK] = "aud_i2s3_bclk",
[CLK_I2S4_BCLK] = "aud_i2s4_bclk",
[CLK_CONNSYS_I2S_ASRC] = "aud_connsys_i2s_asrc",
[CLK_GENERAL1_ASRC] = "aud_general1_asrc",
[CLK_GENERAL2_ASRC] = "aud_general2_asrc",
[CLK_ADC_HIRES_TML] = "aud_adc_hires_tml",
[CLK_ADDA6_ADC] = "aud_adda6_adc",
[CLK_ADDA6_ADC_HIRES] = "aud_adda6_adc_hires",
[CLK_3RD_DAC] = "aud_3rd_dac",
[CLK_3RD_DAC_PREDIS] = "aud_3rd_dac_predis",
[CLK_3RD_DAC_TML] = "aud_3rd_dac_tml",
[CLK_3RD_DAC_HIRES] = "aud_3rd_dac_hires",
[CLK_ETDM_IN1_BCLK] = "aud_etdm_in1_bclk",
[CLK_ETDM_OUT1_BCLK] = "aud_etdm_out1_bclk",
[CLK_INFRA_SYS_AUDIO] = "aud_infra_clk",
[CLK_INFRA_AUDIO_26M] = "mtkaif_26m_clk",
[CLK_MUX_AUDIO] = "top_mux_audio",
[CLK_MUX_AUDIOINTBUS] = "top_mux_audio_int",
[CLK_TOP_MAINPLL_D2_D4] = "top_mainpll_d2_d4",
[CLK_TOP_MUX_AUD_1] = "top_mux_aud_1",
[CLK_TOP_APLL1_CK] = "top_apll1_ck",
[CLK_TOP_MUX_AUD_2] = "top_mux_aud_2",
[CLK_TOP_APLL2_CK] = "top_apll2_ck",
[CLK_TOP_MUX_AUD_ENG1] = "top_mux_aud_eng1",
[CLK_TOP_APLL1_D8] = "top_apll1_d8",
[CLK_TOP_MUX_AUD_ENG2] = "top_mux_aud_eng2",
[CLK_TOP_APLL2_D8] = "top_apll2_d8",
[CLK_TOP_MUX_AUDIO_H] = "top_mux_audio_h",
[CLK_TOP_I2S0_M_SEL] = "top_i2s0_m_sel",
[CLK_TOP_I2S1_M_SEL] = "top_i2s1_m_sel",
[CLK_TOP_I2S2_M_SEL] = "top_i2s2_m_sel",
[CLK_TOP_I2S4_M_SEL] = "top_i2s4_m_sel",
[CLK_TOP_TDM_M_SEL] = "top_tdm_m_sel",
[CLK_TOP_APLL12_DIV0] = "top_apll12_div0",
[CLK_TOP_APLL12_DIV1] = "top_apll12_div1",
[CLK_TOP_APLL12_DIV2] = "top_apll12_div2",
[CLK_TOP_APLL12_DIV4] = "top_apll12_div4",
[CLK_TOP_APLL12_DIV_TDM] = "top_apll12_div_tdm",
[CLK_CLK26M] = "top_clk26m_clk",
};
int mt8186_set_audio_int_bus_parent(struct mtk_base_afe *afe,
int clk_id)
{
struct mt8186_afe_private *afe_priv = afe->platform_priv;
int ret;
ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIOINTBUS],
afe_priv->clk[clk_id]);
if (ret) {
dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[CLK_MUX_AUDIOINTBUS],
aud_clks[clk_id], ret);
return ret;
}
return 0;
}
static int apll1_mux_setting(struct mtk_base_afe *afe, bool enable)
{
struct mt8186_afe_private *afe_priv = afe->platform_priv;
int ret;
if (enable) {
ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_1]);
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_1], ret);
return ret;
}
ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1],
afe_priv->clk[CLK_TOP_APLL1_CK]);
if (ret) {
dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_1],
aud_clks[CLK_TOP_APLL1_CK], ret);
return ret;
}
/* 180.6336 / 8 = 22.5792MHz */
ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]);
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_ENG1], ret);
return ret;
}
ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1],
afe_priv->clk[CLK_TOP_APLL1_D8]);
if (ret) {
dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_ENG1],
aud_clks[CLK_TOP_APLL1_D8], ret);
return ret;
}
} else {
ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1],
afe_priv->clk[CLK_CLK26M]);
if (ret) {
dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_ENG1],
aud_clks[CLK_CLK26M], ret);
return ret;
}
clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]);
ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1],
afe_priv->clk[CLK_CLK26M]);
if (ret) {
dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_1],
aud_clks[CLK_CLK26M], ret);
return ret;
}
clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_1]);
}
return 0;
}
static int apll2_mux_setting(struct mtk_base_afe *afe, bool enable)
{
struct mt8186_afe_private *afe_priv = afe->platform_priv;
int ret;
if (enable) {
ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_2]);
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_2], ret);
return ret;
}
ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2],
afe_priv->clk[CLK_TOP_APLL2_CK]);
if (ret) {
dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_2],
aud_clks[CLK_TOP_APLL2_CK], ret);
return ret;
}
/* 196.608 / 8 = 24.576MHz */
ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]);
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_ENG2], ret);
return ret;
}
ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2],
afe_priv->clk[CLK_TOP_APLL2_D8]);
if (ret) {
dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_ENG2],
aud_clks[CLK_TOP_APLL2_D8], ret);
return ret;
}
} else {
ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2],
afe_priv->clk[CLK_CLK26M]);
if (ret) {
dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_ENG2],
aud_clks[CLK_CLK26M], ret);
return ret;
}
clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]);
ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2],
afe_priv->clk[CLK_CLK26M]);
if (ret) {
dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUD_2],
aud_clks[CLK_CLK26M], ret);
return ret;
}
clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_2]);
}
return 0;
}
int mt8186_afe_enable_cgs(struct mtk_base_afe *afe)
{
struct mt8186_afe_private *afe_priv = afe->platform_priv;
int ret = 0;
int i;
for (i = CLK_I2S1_BCLK; i <= CLK_ETDM_OUT1_BCLK; i++) {
ret = clk_prepare_enable(afe_priv->clk[i]);
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[i], ret);
return ret;
}
}
return 0;
}
void mt8186_afe_disable_cgs(struct mtk_base_afe *afe)
{
struct mt8186_afe_private *afe_priv = afe->platform_priv;
int i;
for (i = CLK_I2S1_BCLK; i <= CLK_ETDM_OUT1_BCLK; i++)
clk_disable_unprepare(afe_priv->clk[i]);
}
int mt8186_afe_enable_clock(struct mtk_base_afe *afe)
{
struct mt8186_afe_private *afe_priv = afe->platform_priv;
int ret = 0;
ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_SYS_AUDIO]);
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_INFRA_SYS_AUDIO], ret);
goto clk_infra_sys_audio_err;
}
ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_AUDIO_26M]);
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_INFRA_AUDIO_26M], ret);
goto clk_infra_audio_26m_err;
}
ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIO]);
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_MUX_AUDIO], ret);
goto clk_mux_audio_err;
}
ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIO],
afe_priv->clk[CLK_CLK26M]);
if (ret) {
dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[CLK_MUX_AUDIO],
aud_clks[CLK_CLK26M], ret);
goto clk_mux_audio_err;
}
ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_MUX_AUDIOINTBUS], ret);
goto clk_mux_audio_intbus_err;
}
ret = mt8186_set_audio_int_bus_parent(afe,
CLK_TOP_MAINPLL_D2_D4);
if (ret)
goto clk_mux_audio_intbus_parent_err;
ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUDIO_H],
afe_priv->clk[CLK_TOP_APLL2_CK]);
if (ret) {
dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[CLK_TOP_MUX_AUDIO_H],
aud_clks[CLK_TOP_APLL2_CK], ret);
goto clk_mux_audio_h_parent_err;
}
ret = clk_prepare_enable(afe_priv->clk[CLK_AFE]);
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_AFE], ret);
goto clk_afe_err;
}
return 0;
clk_afe_err:
clk_disable_unprepare(afe_priv->clk[CLK_AFE]);
clk_mux_audio_h_parent_err:
clk_mux_audio_intbus_parent_err:
mt8186_set_audio_int_bus_parent(afe, CLK_CLK26M);
clk_mux_audio_intbus_err:
clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
clk_mux_audio_err:
clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIO]);
clk_infra_sys_audio_err:
clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUDIO]);
clk_infra_audio_26m_err:
clk_disable_unprepare(afe_priv->clk[CLK_INFRA_AUDIO_26M]);
return ret;
}
void mt8186_afe_disable_clock(struct mtk_base_afe *afe)
{
struct mt8186_afe_private *afe_priv = afe->platform_priv;
clk_disable_unprepare(afe_priv->clk[CLK_AFE]);
mt8186_set_audio_int_bus_parent(afe, CLK_CLK26M);
clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIO]);
clk_disable_unprepare(afe_priv->clk[CLK_INFRA_AUDIO_26M]);
clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUDIO]);
}
int mt8186_afe_suspend_clock(struct mtk_base_afe *afe)
{
struct mt8186_afe_private *afe_priv = afe->platform_priv;
int ret;
/* set audio int bus to 26M */
ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
if (ret) {
dev_info(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_MUX_AUDIOINTBUS], ret);
goto clk_mux_audio_intbus_err;
}
ret = mt8186_set_audio_int_bus_parent(afe, CLK_CLK26M);
if (ret)
goto clk_mux_audio_intbus_parent_err;
clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
return 0;
clk_mux_audio_intbus_parent_err:
mt8186_set_audio_int_bus_parent(afe, CLK_TOP_MAINPLL_D2_D4);
clk_mux_audio_intbus_err:
clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
return ret;
}
int mt8186_afe_resume_clock(struct mtk_base_afe *afe)
{
struct mt8186_afe_private *afe_priv = afe->platform_priv;
int ret;
/* set audio int bus to normal working clock */
ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
if (ret) {
dev_info(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_MUX_AUDIOINTBUS], ret);
goto clk_mux_audio_intbus_err;
}
ret = mt8186_set_audio_int_bus_parent(afe,
CLK_TOP_MAINPLL_D2_D4);
if (ret)
goto clk_mux_audio_intbus_parent_err;
clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
return 0;
clk_mux_audio_intbus_parent_err:
mt8186_set_audio_int_bus_parent(afe, CLK_CLK26M);
clk_mux_audio_intbus_err:
clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
return ret;
}
int mt8186_apll1_enable(struct mtk_base_afe *afe)
{
struct mt8186_afe_private *afe_priv = afe->platform_priv;
int ret;
/* setting for APLL */
apll1_mux_setting(afe, true);
ret = clk_prepare_enable(afe_priv->clk[CLK_APLL22M]);
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_APLL22M], ret);
goto err_clk_apll22m;
}
ret = clk_prepare_enable(afe_priv->clk[CLK_APLL1_TUNER]);
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_APLL1_TUNER], ret);
goto err_clk_apll1_tuner;
}
regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0xfff7, 0x832);
regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0x1, 0x1);
regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
AFE_22M_ON_MASK_SFT, BIT(AFE_22M_ON_SFT));
return 0;
err_clk_apll1_tuner:
clk_disable_unprepare(afe_priv->clk[CLK_APLL1_TUNER]);
err_clk_apll22m:
clk_disable_unprepare(afe_priv->clk[CLK_APLL22M]);
return ret;
}
void mt8186_apll1_disable(struct mtk_base_afe *afe)
{
struct mt8186_afe_private *afe_priv = afe->platform_priv;
regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
AFE_22M_ON_MASK_SFT, 0);
regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0x1, 0);
clk_disable_unprepare(afe_priv->clk[CLK_APLL1_TUNER]);
clk_disable_unprepare(afe_priv->clk[CLK_APLL22M]);
apll1_mux_setting(afe, false);
}
int mt8186_apll2_enable(struct mtk_base_afe *afe)
{
struct mt8186_afe_private *afe_priv = afe->platform_priv;
int ret;
/* setting for APLL */
apll2_mux_setting(afe, true);
ret = clk_prepare_enable(afe_priv->clk[CLK_APLL24M]);
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_APLL24M], ret);
goto err_clk_apll24m;
}
ret = clk_prepare_enable(afe_priv->clk[CLK_APLL2_TUNER]);
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[CLK_APLL2_TUNER], ret);
goto err_clk_apll2_tuner;
}
regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0xfff7, 0x634);
regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0x1, 0x1);
regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
AFE_24M_ON_MASK_SFT, BIT(AFE_24M_ON_SFT));
return 0;
err_clk_apll2_tuner:
clk_disable_unprepare(afe_priv->clk[CLK_APLL2_TUNER]);
err_clk_apll24m:
clk_disable_unprepare(afe_priv->clk[CLK_APLL24M]);
return ret;
}
void mt8186_apll2_disable(struct mtk_base_afe *afe)
{
struct mt8186_afe_private *afe_priv = afe->platform_priv;
regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
AFE_24M_ON_MASK_SFT, 0);
regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0x1, 0);
clk_disable_unprepare(afe_priv->clk[CLK_APLL2_TUNER]);
clk_disable_unprepare(afe_priv->clk[CLK_APLL24M]);
apll2_mux_setting(afe, false);
}
int mt8186_get_apll_rate(struct mtk_base_afe *afe, int apll)
{
return (apll == MT8186_APLL1) ? 180633600 : 196608000;
}
int mt8186_get_apll_by_rate(struct mtk_base_afe *afe, int rate)
{
return ((rate % 8000) == 0) ? MT8186_APLL2 : MT8186_APLL1;
}
int mt8186_get_apll_by_name(struct mtk_base_afe *afe, const char *name)
{
if (strcmp(name, APLL1_W_NAME) == 0)
return MT8186_APLL1;
return MT8186_APLL2;
}
/* mck */
struct mt8186_mck_div {
u32 m_sel_id;
u32 div_clk_id;
};
static const struct mt8186_mck_div mck_div[MT8186_MCK_NUM] = {
[MT8186_I2S0_MCK] = {
.m_sel_id = CLK_TOP_I2S0_M_SEL,
.div_clk_id = CLK_TOP_APLL12_DIV0,
},
[MT8186_I2S1_MCK] = {
.m_sel_id = CLK_TOP_I2S1_M_SEL,
.div_clk_id = CLK_TOP_APLL12_DIV1,
},
[MT8186_I2S2_MCK] = {
.m_sel_id = CLK_TOP_I2S2_M_SEL,
.div_clk_id = CLK_TOP_APLL12_DIV2,
},
[MT8186_I2S4_MCK] = {
.m_sel_id = CLK_TOP_I2S4_M_SEL,
.div_clk_id = CLK_TOP_APLL12_DIV4,
},
[MT8186_TDM_MCK] = {
.m_sel_id = CLK_TOP_TDM_M_SEL,
.div_clk_id = CLK_TOP_APLL12_DIV_TDM,
},
};
int mt8186_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate)
{
struct mt8186_afe_private *afe_priv = afe->platform_priv;
int apll = mt8186_get_apll_by_rate(afe, rate);
int apll_clk_id = apll == MT8186_APLL1 ?
CLK_TOP_MUX_AUD_1 : CLK_TOP_MUX_AUD_2;
int m_sel_id = mck_div[mck_id].m_sel_id;
int div_clk_id = mck_div[mck_id].div_clk_id;
int ret;
/* select apll */
if (m_sel_id >= 0) {
ret = clk_prepare_enable(afe_priv->clk[m_sel_id]);
if (ret) {
dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
__func__, aud_clks[m_sel_id], ret);
return ret;
}
ret = clk_set_parent(afe_priv->clk[m_sel_id],
afe_priv->clk[apll_clk_id]);
if (ret) {
dev_err(afe->dev, "%s(), clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[m_sel_id],
aud_clks[apll_clk_id], ret);
return ret;
}
}
/* enable div, set rate */
ret = clk_prepare_enable(afe_priv->clk[div_clk_id]);
if (ret) {
dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
__func__, aud_clks[div_clk_id], ret);
return ret;
}
ret = clk_set_rate(afe_priv->clk[div_clk_id], rate);
if (ret) {
dev_err(afe->dev, "%s(), clk_set_rate %s, rate %d, fail %d\n",
__func__, aud_clks[div_clk_id], rate, ret);
return ret;
}
return 0;
}
void mt8186_mck_disable(struct mtk_base_afe *afe, int mck_id)
{
struct mt8186_afe_private *afe_priv = afe->platform_priv;
int m_sel_id = mck_div[mck_id].m_sel_id;
int div_clk_id = mck_div[mck_id].div_clk_id;
clk_disable_unprepare(afe_priv->clk[div_clk_id]);
if (m_sel_id >= 0)
clk_disable_unprepare(afe_priv->clk[m_sel_id]);
}
int mt8186_init_clock(struct mtk_base_afe *afe)
{
struct mt8186_afe_private *afe_priv = afe->platform_priv;
struct device_node *of_node = afe->dev->of_node;
int i = 0;
mt8186_audsys_clk_register(afe);
afe_priv->clk = devm_kcalloc(afe->dev, CLK_NUM, sizeof(*afe_priv->clk),
GFP_KERNEL);
if (!afe_priv->clk)
return -ENOMEM;
for (i = 0; i < CLK_NUM; i++) {
afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);
if (IS_ERR(afe_priv->clk[i])) {
dev_err(afe->dev, "%s devm_clk_get %s fail, ret %ld\n",
__func__,
aud_clks[i], PTR_ERR(afe_priv->clk[i]));
afe_priv->clk[i] = NULL;
}
}
afe_priv->apmixedsys = syscon_regmap_lookup_by_phandle(of_node,
"mediatek,apmixedsys");
if (IS_ERR(afe_priv->apmixedsys)) {
dev_err(afe->dev, "%s() Cannot find apmixedsys controller: %ld\n",
__func__, PTR_ERR(afe_priv->apmixedsys));
return PTR_ERR(afe_priv->apmixedsys);
}
afe_priv->topckgen = syscon_regmap_lookup_by_phandle(of_node,
"mediatek,topckgen");
if (IS_ERR(afe_priv->topckgen)) {
dev_err(afe->dev, "%s() Cannot find topckgen controller: %ld\n",
__func__, PTR_ERR(afe_priv->topckgen));
return PTR_ERR(afe_priv->topckgen);
}
afe_priv->infracfg = syscon_regmap_lookup_by_phandle(of_node,
"mediatek,infracfg");
if (IS_ERR(afe_priv->infracfg)) {
dev_err(afe->dev, "%s() Cannot find infracfg: %ld\n",
__func__, PTR_ERR(afe_priv->infracfg));
return PTR_ERR(afe_priv->infracfg);
}
return 0;
}
| linux-master | sound/soc/mediatek/mt8186/mt8186-afe-clk.c |
// SPDX-License-Identifier: GPL-2.0
//
// MediaTek ALSA SoC Audio Control
//
// Copyright (c) 2022 MediaTek Inc.
// Author: Jiaxin Yu <[email protected]>
#include "mt8186-afe-common.h"
enum {
MTK_AFE_RATE_8K = 0,
MTK_AFE_RATE_11K,
MTK_AFE_RATE_12K,
MTK_AFE_RATE_384K,
MTK_AFE_RATE_16K,
MTK_AFE_RATE_22K,
MTK_AFE_RATE_24K,
MTK_AFE_RATE_352K,
MTK_AFE_RATE_32K,
MTK_AFE_RATE_44K,
MTK_AFE_RATE_48K,
MTK_AFE_RATE_88K,
MTK_AFE_RATE_96K,
MTK_AFE_RATE_176K,
MTK_AFE_RATE_192K,
MTK_AFE_RATE_260K,
};
enum {
MTK_AFE_PCM_RATE_8K = 0,
MTK_AFE_PCM_RATE_16K,
MTK_AFE_PCM_RATE_32K,
MTK_AFE_PCM_RATE_48K,
};
enum {
MTK_AFE_TDM_RATE_8K = 0,
MTK_AFE_TDM_RATE_12K,
MTK_AFE_TDM_RATE_16K,
MTK_AFE_TDM_RATE_24K,
MTK_AFE_TDM_RATE_32K,
MTK_AFE_TDM_RATE_48K,
MTK_AFE_TDM_RATE_64K,
MTK_AFE_TDM_RATE_96K,
MTK_AFE_TDM_RATE_128K,
MTK_AFE_TDM_RATE_192K,
MTK_AFE_TDM_RATE_256K,
MTK_AFE_TDM_RATE_384K,
MTK_AFE_TDM_RATE_11K,
MTK_AFE_TDM_RATE_22K,
MTK_AFE_TDM_RATE_44K,
MTK_AFE_TDM_RATE_88K,
MTK_AFE_TDM_RATE_176K,
MTK_AFE_TDM_RATE_352K,
};
enum {
MTK_AFE_TDM_RELATCH_RATE_8K = 0,
MTK_AFE_TDM_RELATCH_RATE_11K,
MTK_AFE_TDM_RELATCH_RATE_12K,
MTK_AFE_TDM_RELATCH_RATE_16K,
MTK_AFE_TDM_RELATCH_RATE_22K,
MTK_AFE_TDM_RELATCH_RATE_24K,
MTK_AFE_TDM_RELATCH_RATE_32K,
MTK_AFE_TDM_RELATCH_RATE_44K,
MTK_AFE_TDM_RELATCH_RATE_48K,
MTK_AFE_TDM_RELATCH_RATE_88K,
MTK_AFE_TDM_RELATCH_RATE_96K,
MTK_AFE_TDM_RELATCH_RATE_176K,
MTK_AFE_TDM_RELATCH_RATE_192K,
MTK_AFE_TDM_RELATCH_RATE_352K,
MTK_AFE_TDM_RELATCH_RATE_384K,
};
unsigned int mt8186_general_rate_transform(struct device *dev, unsigned int rate)
{
switch (rate) {
case 8000:
return MTK_AFE_RATE_8K;
case 11025:
return MTK_AFE_RATE_11K;
case 12000:
return MTK_AFE_RATE_12K;
case 16000:
return MTK_AFE_RATE_16K;
case 22050:
return MTK_AFE_RATE_22K;
case 24000:
return MTK_AFE_RATE_24K;
case 32000:
return MTK_AFE_RATE_32K;
case 44100:
return MTK_AFE_RATE_44K;
case 48000:
return MTK_AFE_RATE_48K;
case 88200:
return MTK_AFE_RATE_88K;
case 96000:
return MTK_AFE_RATE_96K;
case 176400:
return MTK_AFE_RATE_176K;
case 192000:
return MTK_AFE_RATE_192K;
case 260000:
return MTK_AFE_RATE_260K;
case 352800:
return MTK_AFE_RATE_352K;
case 384000:
return MTK_AFE_RATE_384K;
default:
dev_err(dev, "%s(), rate %u invalid, use %d!!!\n",
__func__, rate, MTK_AFE_RATE_48K);
}
return MTK_AFE_RATE_48K;
}
static unsigned int tdm_rate_transform(struct device *dev, unsigned int rate)
{
switch (rate) {
case 8000:
return MTK_AFE_TDM_RATE_8K;
case 11025:
return MTK_AFE_TDM_RATE_11K;
case 12000:
return MTK_AFE_TDM_RATE_12K;
case 16000:
return MTK_AFE_TDM_RATE_16K;
case 22050:
return MTK_AFE_TDM_RATE_22K;
case 24000:
return MTK_AFE_TDM_RATE_24K;
case 32000:
return MTK_AFE_TDM_RATE_32K;
case 44100:
return MTK_AFE_TDM_RATE_44K;
case 48000:
return MTK_AFE_TDM_RATE_48K;
case 64000:
return MTK_AFE_TDM_RATE_64K;
case 88200:
return MTK_AFE_TDM_RATE_88K;
case 96000:
return MTK_AFE_TDM_RATE_96K;
case 128000:
return MTK_AFE_TDM_RATE_128K;
case 176400:
return MTK_AFE_TDM_RATE_176K;
case 192000:
return MTK_AFE_TDM_RATE_192K;
case 256000:
return MTK_AFE_TDM_RATE_256K;
case 352800:
return MTK_AFE_TDM_RATE_352K;
case 384000:
return MTK_AFE_TDM_RATE_384K;
default:
dev_err(dev, "%s(), rate %u invalid, use %d!!!\n",
__func__, rate, MTK_AFE_TDM_RATE_48K);
}
return MTK_AFE_TDM_RATE_48K;
}
static unsigned int pcm_rate_transform(struct device *dev, unsigned int rate)
{
switch (rate) {
case 8000:
return MTK_AFE_PCM_RATE_8K;
case 16000:
return MTK_AFE_PCM_RATE_16K;
case 32000:
return MTK_AFE_PCM_RATE_32K;
case 48000:
return MTK_AFE_PCM_RATE_48K;
default:
dev_err(dev, "%s(), rate %u invalid, use %d!!!\n",
__func__, rate, MTK_AFE_PCM_RATE_48K);
}
return MTK_AFE_PCM_RATE_48K;
}
unsigned int mt8186_tdm_relatch_rate_transform(struct device *dev, unsigned int rate)
{
switch (rate) {
case 8000:
return MTK_AFE_TDM_RELATCH_RATE_8K;
case 11025:
return MTK_AFE_TDM_RELATCH_RATE_11K;
case 12000:
return MTK_AFE_TDM_RELATCH_RATE_12K;
case 16000:
return MTK_AFE_TDM_RELATCH_RATE_16K;
case 22050:
return MTK_AFE_TDM_RELATCH_RATE_22K;
case 24000:
return MTK_AFE_TDM_RELATCH_RATE_24K;
case 32000:
return MTK_AFE_TDM_RELATCH_RATE_32K;
case 44100:
return MTK_AFE_TDM_RELATCH_RATE_44K;
case 48000:
return MTK_AFE_TDM_RELATCH_RATE_48K;
case 88200:
return MTK_AFE_TDM_RELATCH_RATE_88K;
case 96000:
return MTK_AFE_TDM_RELATCH_RATE_96K;
case 176400:
return MTK_AFE_TDM_RELATCH_RATE_176K;
case 192000:
return MTK_AFE_TDM_RELATCH_RATE_192K;
case 352800:
return MTK_AFE_TDM_RELATCH_RATE_352K;
case 384000:
return MTK_AFE_TDM_RELATCH_RATE_384K;
default:
dev_err(dev, "%s(), rate %u invalid, use %d!!!\n",
__func__, rate, MTK_AFE_TDM_RELATCH_RATE_48K);
}
return MTK_AFE_TDM_RELATCH_RATE_48K;
}
unsigned int mt8186_rate_transform(struct device *dev, unsigned int rate, int aud_blk)
{
switch (aud_blk) {
case MT8186_DAI_PCM:
return pcm_rate_transform(dev, rate);
case MT8186_DAI_TDM_IN:
return tdm_rate_transform(dev, rate);
default:
return mt8186_general_rate_transform(dev, rate);
}
}
int mt8186_dai_set_priv(struct mtk_base_afe *afe, int id, int priv_size, const void *priv_data)
{
struct mt8186_afe_private *afe_priv = afe->platform_priv;
void *temp_data;
temp_data = devm_kzalloc(afe->dev,
priv_size,
GFP_KERNEL);
if (!temp_data)
return -ENOMEM;
if (priv_data)
memcpy(temp_data, priv_data, priv_size);
afe_priv->dai_priv[id] = temp_data;
return 0;
}
| linux-master | sound/soc/mediatek/mt8186/mt8186-afe-control.c |
// SPDX-License-Identifier: GPL-2.0
//
// mt8186-audsys-clk.h -- Mediatek 8186 audsys clock control
//
// Copyright (c) 2022 MediaTek Inc.
// Author: Jiaxin Yu <[email protected]>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#include "mt8186-afe-common.h"
#include "mt8186-audsys-clk.h"
#include "mt8186-audsys-clkid.h"
#include "mt8186-reg.h"
struct afe_gate {
int id;
const char *name;
const char *parent_name;
int reg;
u8 bit;
const struct clk_ops *ops;
unsigned long flags;
u8 cg_flags;
};
#define GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, _flags, _cgflags) {\
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.reg = _reg, \
.bit = _bit, \
.flags = _flags, \
.cg_flags = _cgflags, \
}
#define GATE_AFE(_id, _name, _parent, _reg, _bit) \
GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, \
CLK_SET_RATE_PARENT, CLK_GATE_SET_TO_DISABLE)
#define GATE_AUD0(_id, _name, _parent, _bit) \
GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON0, _bit)
#define GATE_AUD1(_id, _name, _parent, _bit) \
GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON1, _bit)
#define GATE_AUD2(_id, _name, _parent, _bit) \
GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON2, _bit)
static const struct afe_gate aud_clks[CLK_AUD_NR_CLK] = {
/* AUD0 */
GATE_AUD0(CLK_AUD_AFE, "aud_afe_clk", "top_audio", 2),
GATE_AUD0(CLK_AUD_22M, "aud_apll22m_clk", "top_aud_engen1", 8),
GATE_AUD0(CLK_AUD_24M, "aud_apll24m_clk", "top_aud_engen2", 9),
GATE_AUD0(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner_clk", "top_aud_engen2", 18),
GATE_AUD0(CLK_AUD_APLL_TUNER, "aud_apll_tuner_clk", "top_aud_engen1", 19),
GATE_AUD0(CLK_AUD_TDM, "aud_tdm_clk", "top_aud_1", 20),
GATE_AUD0(CLK_AUD_ADC, "aud_adc_clk", "top_audio", 24),
GATE_AUD0(CLK_AUD_DAC, "aud_dac_clk", "top_audio", 25),
GATE_AUD0(CLK_AUD_DAC_PREDIS, "aud_dac_predis_clk", "top_audio", 26),
GATE_AUD0(CLK_AUD_TML, "aud_tml_clk", "top_audio", 27),
GATE_AUD0(CLK_AUD_NLE, "aud_nle_clk", "top_audio", 28),
/* AUD1 */
GATE_AUD1(CLK_AUD_I2S1_BCLK, "aud_i2s1_bclk", "top_audio", 4),
GATE_AUD1(CLK_AUD_I2S2_BCLK, "aud_i2s2_bclk", "top_audio", 5),
GATE_AUD1(CLK_AUD_I2S3_BCLK, "aud_i2s3_bclk", "top_audio", 6),
GATE_AUD1(CLK_AUD_I2S4_BCLK, "aud_i2s4_bclk", "top_audio", 7),
GATE_AUD1(CLK_AUD_CONNSYS_I2S_ASRC, "aud_connsys_i2s_asrc", "top_audio", 12),
GATE_AUD1(CLK_AUD_GENERAL1_ASRC, "aud_general1_asrc", "top_audio", 13),
GATE_AUD1(CLK_AUD_GENERAL2_ASRC, "aud_general2_asrc", "top_audio", 14),
GATE_AUD1(CLK_AUD_DAC_HIRES, "aud_dac_hires_clk", "top_audio_h", 15),
GATE_AUD1(CLK_AUD_ADC_HIRES, "aud_adc_hires_clk", "top_audio_h", 16),
GATE_AUD1(CLK_AUD_ADC_HIRES_TML, "aud_adc_hires_tml", "top_audio_h", 17),
GATE_AUD1(CLK_AUD_ADDA6_ADC, "aud_adda6_adc", "top_audio", 20),
GATE_AUD1(CLK_AUD_ADDA6_ADC_HIRES, "aud_adda6_adc_hires", "top_audio_h", 21),
GATE_AUD1(CLK_AUD_3RD_DAC, "aud_3rd_dac", "top_audio", 28),
GATE_AUD1(CLK_AUD_3RD_DAC_PREDIS, "aud_3rd_dac_predis", "top_audio", 29),
GATE_AUD1(CLK_AUD_3RD_DAC_TML, "aud_3rd_dac_tml", "top_audio", 30),
GATE_AUD1(CLK_AUD_3RD_DAC_HIRES, "aud_3rd_dac_hires", "top_audio_h", 31),
/* AUD2 */
GATE_AUD2(CLK_AUD_ETDM_IN1_BCLK, "aud_etdm_in1_bclk", "top_audio", 23),
GATE_AUD2(CLK_AUD_ETDM_OUT1_BCLK, "aud_etdm_out1_bclk", "top_audio", 24),
};
static void mt8186_audsys_clk_unregister(void *data)
{
struct mtk_base_afe *afe = data;
struct mt8186_afe_private *afe_priv = afe->platform_priv;
struct clk *clk;
struct clk_lookup *cl;
int i;
if (!afe_priv)
return;
for (i = 0; i < CLK_AUD_NR_CLK; i++) {
cl = afe_priv->lookup[i];
if (!cl)
continue;
clk = cl->clk;
clk_unregister_gate(clk);
clkdev_drop(cl);
}
}
int mt8186_audsys_clk_register(struct mtk_base_afe *afe)
{
struct mt8186_afe_private *afe_priv = afe->platform_priv;
struct clk *clk;
struct clk_lookup *cl;
int i;
afe_priv->lookup = devm_kcalloc(afe->dev, CLK_AUD_NR_CLK,
sizeof(*afe_priv->lookup),
GFP_KERNEL);
if (!afe_priv->lookup)
return -ENOMEM;
for (i = 0; i < ARRAY_SIZE(aud_clks); i++) {
const struct afe_gate *gate = &aud_clks[i];
clk = clk_register_gate(afe->dev, gate->name, gate->parent_name,
gate->flags, afe->base_addr + gate->reg,
gate->bit, gate->cg_flags, NULL);
if (IS_ERR(clk)) {
dev_err(afe->dev, "Failed to register clk %s: %ld\n",
gate->name, PTR_ERR(clk));
continue;
}
/* add clk_lookup for devm_clk_get(SND_SOC_DAPM_CLOCK_SUPPLY) */
cl = kzalloc(sizeof(*cl), GFP_KERNEL);
if (!cl)
return -ENOMEM;
cl->clk = clk;
cl->con_id = gate->name;
cl->dev_id = dev_name(afe->dev);
clkdev_add(cl);
afe_priv->lookup[i] = cl;
}
return devm_add_action_or_reset(afe->dev, mt8186_audsys_clk_unregister, afe);
}
| linux-master | sound/soc/mediatek/mt8186/mt8186-audsys-clk.c |
// SPDX-License-Identifier: GPL-2.0
//
// Mediatek ALSA SoC AFE platform driver for 8186
//
// Copyright (c) 2022 MediaTek Inc.
// Author: Jiaxin Yu <[email protected]>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/pm_runtime.h>
#include <linux/reset.h>
#include <sound/soc.h>
#include "../common/mtk-afe-platform-driver.h"
#include "../common/mtk-afe-fe-dai.h"
#include "mt8186-afe-common.h"
#include "mt8186-afe-clk.h"
#include "mt8186-afe-gpio.h"
#include "mt8186-interconnection.h"
static const struct snd_pcm_hardware mt8186_afe_hardware = {
.info = (SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_MMAP_VALID),
.formats = (SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE |
SNDRV_PCM_FMTBIT_S32_LE),
.period_bytes_min = 96,
.period_bytes_max = 4 * 48 * 1024,
.periods_min = 2,
.periods_max = 256,
.buffer_bytes_max = 4 * 48 * 1024,
.fifo_size = 0,
};
static int mt8186_fe_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct snd_pcm_runtime *runtime = substream->runtime;
int id = asoc_rtd_to_cpu(rtd, 0)->id;
struct mtk_base_afe_memif *memif = &afe->memif[id];
const struct snd_pcm_hardware *mtk_afe_hardware = afe->mtk_afe_hardware;
int ret;
memif->substream = substream;
snd_pcm_hw_constraint_step(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 16);
snd_soc_set_runtime_hwparams(substream, mtk_afe_hardware);
ret = snd_pcm_hw_constraint_integer(runtime,
SNDRV_PCM_HW_PARAM_PERIODS);
if (ret < 0) {
dev_err(afe->dev, "snd_pcm_hw_constraint_integer failed\n");
return ret;
}
/* dynamic allocate irq to memif */
if (memif->irq_usage < 0) {
int irq_id = mtk_dynamic_irq_acquire(afe);
if (irq_id != afe->irqs_size) {
/* link */
memif->irq_usage = irq_id;
} else {
dev_err(afe->dev, "%s() error: no more asys irq\n",
__func__);
return -EBUSY;
}
}
return 0;
}
static void mt8186_fe_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8186_afe_private *afe_priv = afe->platform_priv;
int id = asoc_rtd_to_cpu(rtd, 0)->id;
struct mtk_base_afe_memif *memif = &afe->memif[id];
int irq_id = memif->irq_usage;
memif->substream = NULL;
afe_priv->irq_cnt[id] = 0;
afe_priv->xrun_assert[id] = 0;
if (!memif->const_irq) {
mtk_dynamic_irq_release(afe, irq_id);
memif->irq_usage = -1;
memif->substream = NULL;
}
}
static int mt8186_fe_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
int id = asoc_rtd_to_cpu(rtd, 0)->id;
unsigned int channels = params_channels(params);
unsigned int rate = params_rate(params);
int ret;
ret = mtk_afe_fe_hw_params(substream, params, dai);
if (ret)
return ret;
/* channel merge configuration, enable control is in UL5_IN_MUX */
if (id == MT8186_MEMIF_VUL3) {
int update_cnt = 8;
unsigned int val = 0;
unsigned int mask = 0;
int fs_mode = mt8186_rate_transform(afe->dev, rate, id);
/* set rate, channel, update cnt, disable sgen */
val = fs_mode << CM1_FS_SELECT_SFT |
(channels - 1) << CHANNEL_MERGE0_CHNUM_SFT |
update_cnt << CHANNEL_MERGE0_UPDATE_CNT_SFT;
mask = CM1_FS_SELECT_MASK_SFT |
CHANNEL_MERGE0_CHNUM_MASK_SFT |
CHANNEL_MERGE0_UPDATE_CNT_MASK_SFT;
regmap_update_bits(afe->regmap, AFE_CM1_CON, mask, val);
}
return 0;
}
static int mt8186_fe_hw_free(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
int ret;
ret = mtk_afe_fe_hw_free(substream, dai);
if (ret) {
dev_err(afe->dev, "%s failed\n", __func__);
return ret;
}
return 0;
}
static int mt8186_fe_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_pcm_runtime * const runtime = substream->runtime;
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8186_afe_private *afe_priv = afe->platform_priv;
int id = asoc_rtd_to_cpu(rtd, 0)->id;
struct mtk_base_afe_memif *memif = &afe->memif[id];
int irq_id = memif->irq_usage;
struct mtk_base_afe_irq *irqs = &afe->irqs[irq_id];
const struct mtk_base_irq_data *irq_data = irqs->irq_data;
unsigned int rate = runtime->rate;
unsigned int counter;
int fs;
int ret;
dev_dbg(afe->dev, "%s(), %s cmd %d, irq_id %d\n",
__func__, memif->data->name, cmd, irq_id);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
ret = mtk_memif_set_enable(afe, id);
if (ret) {
dev_err(afe->dev, "%s(), error, id %d, memif enable, ret %d\n",
__func__, id, ret);
return ret;
}
/*
* for small latency record
* ul memif need read some data before irq enable
*/
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE &&
((runtime->period_size * 1000) / rate <= 10))
udelay(300);
/* set irq counter */
if (afe_priv->irq_cnt[id] > 0)
counter = afe_priv->irq_cnt[id];
else
counter = runtime->period_size;
regmap_update_bits(afe->regmap, irq_data->irq_cnt_reg,
irq_data->irq_cnt_maskbit
<< irq_data->irq_cnt_shift,
counter << irq_data->irq_cnt_shift);
/* set irq fs */
fs = afe->irq_fs(substream, runtime->rate);
if (fs < 0)
return -EINVAL;
regmap_update_bits(afe->regmap, irq_data->irq_fs_reg,
irq_data->irq_fs_maskbit
<< irq_data->irq_fs_shift,
fs << irq_data->irq_fs_shift);
/* enable interrupt */
if (runtime->stop_threshold != ~(0U))
regmap_update_bits(afe->regmap,
irq_data->irq_en_reg,
1 << irq_data->irq_en_shift,
1 << irq_data->irq_en_shift);
return 0;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
if (afe_priv->xrun_assert[id] > 0) {
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
int avail = snd_pcm_capture_avail(runtime);
/* alsa can trigger stop/start when occur xrun */
if (avail >= runtime->buffer_size)
dev_dbg(afe->dev, "%s(), id %d, xrun assert\n",
__func__, id);
}
}
ret = mtk_memif_set_disable(afe, id);
if (ret)
dev_err(afe->dev, "%s(), error, id %d, memif enable, ret %d\n",
__func__, id, ret);
/* disable interrupt */
if (runtime->stop_threshold != ~(0U))
regmap_update_bits(afe->regmap,
irq_data->irq_en_reg,
1 << irq_data->irq_en_shift,
0 << irq_data->irq_en_shift);
/* clear pending IRQ */
regmap_write(afe->regmap, irq_data->irq_clr_reg,
1 << irq_data->irq_clr_shift);
return ret;
default:
return -EINVAL;
}
}
static int mt8186_memif_fs(struct snd_pcm_substream *substream,
unsigned int rate)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_component *component =
snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
int id = asoc_rtd_to_cpu(rtd, 0)->id;
return mt8186_rate_transform(afe->dev, rate, id);
}
static int mt8186_get_dai_fs(struct mtk_base_afe *afe,
int dai_id, unsigned int rate)
{
return mt8186_rate_transform(afe->dev, rate, dai_id);
}
static int mt8186_irq_fs(struct snd_pcm_substream *substream, unsigned int rate)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_component *component =
snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
return mt8186_general_rate_transform(afe->dev, rate);
}
static int mt8186_get_memif_pbuf_size(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
if ((runtime->period_size * 1000) / runtime->rate > 10)
return MT8186_MEMIF_PBUF_SIZE_256_BYTES;
return MT8186_MEMIF_PBUF_SIZE_32_BYTES;
}
static int mt8186_fe_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_pcm_runtime * const runtime = substream->runtime;
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
int id = asoc_rtd_to_cpu(rtd, 0)->id;
struct mtk_base_afe_memif *memif = &afe->memif[id];
int irq_id = memif->irq_usage;
struct mtk_base_afe_irq *irqs = &afe->irqs[irq_id];
const struct mtk_base_irq_data *irq_data = irqs->irq_data;
unsigned int counter = runtime->period_size;
int fs;
int ret;
ret = mtk_afe_fe_prepare(substream, dai);
if (ret)
return ret;
/* set irq counter */
regmap_update_bits(afe->regmap, irq_data->irq_cnt_reg,
irq_data->irq_cnt_maskbit
<< irq_data->irq_cnt_shift,
counter << irq_data->irq_cnt_shift);
/* set irq fs */
fs = afe->irq_fs(substream, runtime->rate);
if (fs < 0)
return -EINVAL;
regmap_update_bits(afe->regmap, irq_data->irq_fs_reg,
irq_data->irq_fs_maskbit
<< irq_data->irq_fs_shift,
fs << irq_data->irq_fs_shift);
return 0;
}
/* FE DAIs */
static const struct snd_soc_dai_ops mt8186_memif_dai_ops = {
.startup = mt8186_fe_startup,
.shutdown = mt8186_fe_shutdown,
.hw_params = mt8186_fe_hw_params,
.hw_free = mt8186_fe_hw_free,
.prepare = mt8186_fe_prepare,
.trigger = mt8186_fe_trigger,
};
#define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\
SNDRV_PCM_RATE_88200 |\
SNDRV_PCM_RATE_96000 |\
SNDRV_PCM_RATE_176400 |\
SNDRV_PCM_RATE_192000)
#define MTK_PCM_DAI_RATES (SNDRV_PCM_RATE_8000 |\
SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 |\
SNDRV_PCM_RATE_48000)
#define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver mt8186_memif_dai_driver[] = {
/* FE DAIs: memory intefaces to CPU */
{
.name = "DL1",
.id = MT8186_MEMIF_DL1,
.playback = {
.stream_name = "DL1",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8186_memif_dai_ops,
},
{
.name = "DL12",
.id = MT8186_MEMIF_DL12,
.playback = {
.stream_name = "DL12",
.channels_min = 1,
.channels_max = 4,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8186_memif_dai_ops,
},
{
.name = "DL2",
.id = MT8186_MEMIF_DL2,
.playback = {
.stream_name = "DL2",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8186_memif_dai_ops,
},
{
.name = "DL3",
.id = MT8186_MEMIF_DL3,
.playback = {
.stream_name = "DL3",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8186_memif_dai_ops,
},
{
.name = "DL4",
.id = MT8186_MEMIF_DL4,
.playback = {
.stream_name = "DL4",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8186_memif_dai_ops,
},
{
.name = "DL5",
.id = MT8186_MEMIF_DL5,
.playback = {
.stream_name = "DL5",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8186_memif_dai_ops,
},
{
.name = "DL6",
.id = MT8186_MEMIF_DL6,
.playback = {
.stream_name = "DL6",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8186_memif_dai_ops,
},
{
.name = "DL7",
.id = MT8186_MEMIF_DL7,
.playback = {
.stream_name = "DL7",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8186_memif_dai_ops,
},
{
.name = "DL8",
.id = MT8186_MEMIF_DL8,
.playback = {
.stream_name = "DL8",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8186_memif_dai_ops,
},
{
.name = "UL1",
.id = MT8186_MEMIF_VUL12,
.capture = {
.stream_name = "UL1",
.channels_min = 1,
.channels_max = 4,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8186_memif_dai_ops,
},
{
.name = "UL2",
.id = MT8186_MEMIF_AWB,
.capture = {
.stream_name = "UL2",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8186_memif_dai_ops,
},
{
.name = "UL3",
.id = MT8186_MEMIF_VUL2,
.capture = {
.stream_name = "UL3",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8186_memif_dai_ops,
},
{
.name = "UL4",
.id = MT8186_MEMIF_AWB2,
.capture = {
.stream_name = "UL4",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8186_memif_dai_ops,
},
{
.name = "UL5",
.id = MT8186_MEMIF_VUL3,
.capture = {
.stream_name = "UL5",
.channels_min = 1,
.channels_max = 12,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8186_memif_dai_ops,
},
{
.name = "UL6",
.id = MT8186_MEMIF_VUL4,
.capture = {
.stream_name = "UL6",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8186_memif_dai_ops,
},
{
.name = "UL7",
.id = MT8186_MEMIF_VUL5,
.capture = {
.stream_name = "UL7",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8186_memif_dai_ops,
},
{
.name = "UL8",
.id = MT8186_MEMIF_VUL6,
.capture = {
.stream_name = "UL8",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8186_memif_dai_ops,
}
};
/* kcontrol */
static int mt8186_irq_cnt1_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8186_afe_private *afe_priv = afe->platform_priv;
ucontrol->value.integer.value[0] =
afe_priv->irq_cnt[MT8186_PRIMARY_MEMIF];
return 0;
}
static int mt8186_irq_cnt1_set(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8186_afe_private *afe_priv = afe->platform_priv;
int memif_num = MT8186_PRIMARY_MEMIF;
struct mtk_base_afe_memif *memif = &afe->memif[memif_num];
int irq_id = memif->irq_usage;
int irq_cnt = afe_priv->irq_cnt[memif_num];
dev_dbg(afe->dev, "%s(), irq_id %d, irq_cnt = %d, value = %ld\n",
__func__, irq_id, irq_cnt, ucontrol->value.integer.value[0]);
if (irq_cnt == ucontrol->value.integer.value[0])
return 0;
irq_cnt = ucontrol->value.integer.value[0];
afe_priv->irq_cnt[memif_num] = irq_cnt;
if (!pm_runtime_status_suspended(afe->dev) && irq_id >= 0) {
struct mtk_base_afe_irq *irqs = &afe->irqs[irq_id];
const struct mtk_base_irq_data *irq_data = irqs->irq_data;
regmap_update_bits(afe->regmap, irq_data->irq_cnt_reg,
irq_data->irq_cnt_maskbit
<< irq_data->irq_cnt_shift,
irq_cnt << irq_data->irq_cnt_shift);
} else {
dev_dbg(afe->dev, "%s(), suspended || irq_id %d, not set\n",
__func__, irq_id);
}
return 1;
}
static int mt8186_irq_cnt2_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8186_afe_private *afe_priv = afe->platform_priv;
ucontrol->value.integer.value[0] =
afe_priv->irq_cnt[MT8186_RECORD_MEMIF];
return 0;
}
static int mt8186_irq_cnt2_set(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8186_afe_private *afe_priv = afe->platform_priv;
int memif_num = MT8186_RECORD_MEMIF;
struct mtk_base_afe_memif *memif = &afe->memif[memif_num];
int irq_id = memif->irq_usage;
int irq_cnt = afe_priv->irq_cnt[memif_num];
dev_dbg(afe->dev, "%s(), irq_id %d, irq_cnt = %d, value = %ld\n",
__func__, irq_id, irq_cnt, ucontrol->value.integer.value[0]);
if (irq_cnt == ucontrol->value.integer.value[0])
return 0;
irq_cnt = ucontrol->value.integer.value[0];
afe_priv->irq_cnt[memif_num] = irq_cnt;
if (!pm_runtime_status_suspended(afe->dev) && irq_id >= 0) {
struct mtk_base_afe_irq *irqs = &afe->irqs[irq_id];
const struct mtk_base_irq_data *irq_data = irqs->irq_data;
regmap_update_bits(afe->regmap, irq_data->irq_cnt_reg,
irq_data->irq_cnt_maskbit
<< irq_data->irq_cnt_shift,
irq_cnt << irq_data->irq_cnt_shift);
} else {
dev_dbg(afe->dev, "%s(), suspended || irq_id %d, not set\n",
__func__, irq_id);
}
return 1;
}
static int mt8186_record_xrun_assert_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8186_afe_private *afe_priv = afe->platform_priv;
int xrun_assert = afe_priv->xrun_assert[MT8186_RECORD_MEMIF];
ucontrol->value.integer.value[0] = xrun_assert;
return 0;
}
static int mt8186_record_xrun_assert_set(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8186_afe_private *afe_priv = afe->platform_priv;
int xrun_assert = ucontrol->value.integer.value[0];
dev_dbg(afe->dev, "%s(), xrun_assert %d\n", __func__, xrun_assert);
if (xrun_assert == afe_priv->xrun_assert[MT8186_RECORD_MEMIF])
return 0;
afe_priv->xrun_assert[MT8186_RECORD_MEMIF] = xrun_assert;
return 1;
}
static const struct snd_kcontrol_new mt8186_pcm_kcontrols[] = {
SOC_SINGLE_EXT("Audio IRQ1 CNT", SND_SOC_NOPM, 0, 0x3ffff, 0,
mt8186_irq_cnt1_get, mt8186_irq_cnt1_set),
SOC_SINGLE_EXT("Audio IRQ2 CNT", SND_SOC_NOPM, 0, 0x3ffff, 0,
mt8186_irq_cnt2_get, mt8186_irq_cnt2_set),
SOC_SINGLE_EXT("record_xrun_assert", SND_SOC_NOPM, 0, 0x1, 0,
mt8186_record_xrun_assert_get,
mt8186_record_xrun_assert_set),
};
/* dma widget & routes*/
static const struct snd_kcontrol_new memif_ul1_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN21,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN21,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3 Switch", AFE_CONN21,
I_ADDA_UL_CH3, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH1 Switch", AFE_CONN21_1,
I_TDM_IN_CH1, 1, 0),
};
static const struct snd_kcontrol_new memif_ul1_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN22,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN22,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3 Switch", AFE_CONN22,
I_ADDA_UL_CH3, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4 Switch", AFE_CONN22,
I_ADDA_UL_CH4, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH2 Switch", AFE_CONN22_1,
I_TDM_IN_CH2, 1, 0),
};
static const struct snd_kcontrol_new memif_ul1_ch3_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN9,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN9,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3 Switch", AFE_CONN9,
I_ADDA_UL_CH3, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH3 Switch", AFE_CONN9_1,
I_TDM_IN_CH3, 1, 0),
};
static const struct snd_kcontrol_new memif_ul1_ch4_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN10,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN10,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3 Switch", AFE_CONN10,
I_ADDA_UL_CH3, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4 Switch", AFE_CONN10,
I_ADDA_UL_CH4, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH4 Switch", AFE_CONN10_1,
I_TDM_IN_CH4, 1, 0),
};
static const struct snd_kcontrol_new memif_ul2_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1 Switch", AFE_CONN5,
I_I2S0_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN5,
I_DL1_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1 Switch", AFE_CONN5,
I_DL12_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN5,
I_DL2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN5,
I_DL3_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN5_1,
I_DL4_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN5_1,
I_DL5_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1 Switch", AFE_CONN5_1,
I_DL6_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1 Switch", AFE_CONN5,
I_PCM_1_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1 Switch", AFE_CONN5,
I_I2S2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("CONNSYS_I2S_CH1 Switch", AFE_CONN5_1,
I_CONNSYS_I2S_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH1 Switch", AFE_CONN5_1,
I_SRC_1_OUT_CH1, 1, 0),
};
static const struct snd_kcontrol_new memif_ul2_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2 Switch", AFE_CONN6,
I_I2S0_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN6,
I_DL1_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN6,
I_DL12_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN6,
I_DL2_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN6,
I_DL3_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN6_1,
I_DL4_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2 Switch", AFE_CONN6_1,
I_DL5_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2 Switch", AFE_CONN6_1,
I_DL6_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2 Switch", AFE_CONN6,
I_PCM_1_CAP_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2 Switch", AFE_CONN6,
I_I2S2_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("CONNSYS_I2S_CH2 Switch", AFE_CONN6_1,
I_CONNSYS_I2S_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH2 Switch", AFE_CONN6_1,
I_SRC_1_OUT_CH2, 1, 0),
};
static const struct snd_kcontrol_new memif_ul3_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("CONNSYS_I2S_CH1 Switch", AFE_CONN32_1,
I_CONNSYS_I2S_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN32,
I_DL1_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN32,
I_DL2_CH1, 1, 0),
};
static const struct snd_kcontrol_new memif_ul3_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("CONNSYS_I2S_CH2 Switch", AFE_CONN33_1,
I_CONNSYS_I2S_CH2, 1, 0),
};
static const struct snd_kcontrol_new memif_ul4_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN38,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1 Switch", AFE_CONN38,
I_I2S0_CH1, 1, 0),
};
static const struct snd_kcontrol_new memif_ul4_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN39,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2 Switch", AFE_CONN39,
I_I2S0_CH2, 1, 0),
};
static const struct snd_kcontrol_new memif_ul5_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN44,
I_ADDA_UL_CH1, 1, 0),
};
static const struct snd_kcontrol_new memif_ul5_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN45,
I_ADDA_UL_CH2, 1, 0),
};
static const struct snd_kcontrol_new memif_ul6_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN46,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN46,
I_DL1_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1 Switch", AFE_CONN46,
I_DL12_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1 Switch", AFE_CONN46_1,
I_DL6_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN46,
I_DL2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN46,
I_DL3_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN46_1,
I_DL4_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1 Switch", AFE_CONN46,
I_PCM_1_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1 Switch", AFE_CONN46,
I_GAIN1_OUT_CH1, 1, 0),
};
static const struct snd_kcontrol_new memif_ul6_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN47,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN47,
I_DL1_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN47,
I_DL12_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2 Switch", AFE_CONN47_1,
I_DL6_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN47,
I_DL2_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN47,
I_DL3_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN47_1,
I_DL4_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2 Switch", AFE_CONN47,
I_PCM_1_CAP_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2 Switch", AFE_CONN47,
I_GAIN1_OUT_CH2, 1, 0),
};
static const struct snd_kcontrol_new memif_ul7_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN48,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN2_OUT_CH1 Switch", AFE_CONN48,
I_GAIN2_OUT_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_2_OUT_CH1 Switch", AFE_CONN48_1,
I_SRC_2_OUT_CH1, 1, 0),
};
static const struct snd_kcontrol_new memif_ul7_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN49,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN2_OUT_CH2 Switch", AFE_CONN49,
I_GAIN2_OUT_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_2_OUT_CH2 Switch", AFE_CONN49_1,
I_SRC_2_OUT_CH2, 1, 0),
};
static const struct snd_kcontrol_new memif_ul8_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN50,
I_ADDA_UL_CH1, 1, 0),
};
static const struct snd_kcontrol_new memif_ul8_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN51,
I_ADDA_UL_CH2, 1, 0),
};
static const struct snd_kcontrol_new hw_cm1_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH1 Switch", AFE_CONN58_1,
I_TDM_IN_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1 Switch", AFE_CONN58,
I_I2S0_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1 Switch", AFE_CONN58,
I_I2S2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN58,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN58,
I_DL1_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1 Switch", AFE_CONN58,
I_DL12_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH3 Switch", AFE_CONN58,
I_DL12_CH3, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN58,
I_DL2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN58,
I_DL3_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN58_1,
I_DL4_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN58_1,
I_DL5_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH1 Switch", AFE_CONN58_1,
I_SRC_1_OUT_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH1 Switch", AFE_CONN58_1,
I_SRC_2_OUT_CH1, 1, 0),
};
static const struct snd_kcontrol_new hw_cm1_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH2 Switch", AFE_CONN59_1,
I_TDM_IN_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2 Switch", AFE_CONN59,
I_I2S0_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2 Switch", AFE_CONN59,
I_I2S2_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN59,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN59,
I_DL1_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN59,
I_DL12_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH4 Switch", AFE_CONN59,
I_DL12_CH4, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN59,
I_DL2_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN59,
I_DL3_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN59_1,
I_DL4_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2 Switch", AFE_CONN59_1,
I_DL5_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH2 Switch", AFE_CONN59_1,
I_SRC_1_OUT_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH2 Switch", AFE_CONN59_1,
I_SRC_2_OUT_CH2, 1, 0),
};
static const struct snd_kcontrol_new hw_cm1_ch3_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH3 Switch", AFE_CONN60_1,
I_TDM_IN_CH3, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1 Switch", AFE_CONN60,
I_I2S0_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1 Switch", AFE_CONN60,
I_I2S2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN60,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN60,
I_DL1_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1 Switch", AFE_CONN60,
I_DL12_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH3 Switch", AFE_CONN60,
I_DL12_CH3, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN60,
I_DL2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN60,
I_DL3_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN60_1,
I_DL4_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN60_1,
I_DL5_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH1 Switch", AFE_CONN60_1,
I_SRC_1_OUT_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH1 Switch", AFE_CONN60_1,
I_SRC_2_OUT_CH1, 1, 0),
};
static const struct snd_kcontrol_new hw_cm1_ch4_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH4 Switch", AFE_CONN61_1,
I_TDM_IN_CH4, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2 Switch", AFE_CONN61,
I_I2S0_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2 Switch", AFE_CONN61,
I_I2S2_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN61,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN61,
I_DL1_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN61,
I_DL12_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH4 Switch", AFE_CONN61,
I_DL12_CH4, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN61,
I_DL2_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN61,
I_DL3_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN61_1,
I_DL4_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2 Switch", AFE_CONN61_1,
I_DL5_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH2 Switch", AFE_CONN61_1,
I_SRC_1_OUT_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH2 Switch", AFE_CONN61_1,
I_SRC_2_OUT_CH2, 1, 0),
};
static const struct snd_kcontrol_new hw_cm1_ch5_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH5 Switch", AFE_CONN62_1,
I_TDM_IN_CH5, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1 Switch", AFE_CONN62,
I_I2S0_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1 Switch", AFE_CONN62,
I_I2S2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN62,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN62,
I_DL1_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1 Switch", AFE_CONN62,
I_DL12_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH3 Switch", AFE_CONN62,
I_DL12_CH3, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN62,
I_DL2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN62,
I_DL3_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN62_1,
I_DL4_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN62_1,
I_DL5_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH1 Switch", AFE_CONN62_1,
I_SRC_1_OUT_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH1 Switch", AFE_CONN62_1,
I_SRC_2_OUT_CH1, 1, 0),
};
static const struct snd_kcontrol_new hw_cm1_ch6_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH6 Switch", AFE_CONN63_1,
I_TDM_IN_CH6, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2 Switch", AFE_CONN63,
I_I2S0_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2 Switch", AFE_CONN63,
I_I2S2_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN63,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN63,
I_DL1_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN63,
I_DL12_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH4 Switch", AFE_CONN63,
I_DL12_CH4, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN63,
I_DL2_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN63,
I_DL3_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN63_1,
I_DL4_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2 Switch", AFE_CONN63_1,
I_DL5_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH2 Switch", AFE_CONN63_1,
I_SRC_1_OUT_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH2 Switch", AFE_CONN63_1,
I_SRC_2_OUT_CH2, 1, 0),
};
static const struct snd_kcontrol_new hw_cm1_ch7_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH7 Switch", AFE_CONN64_1,
I_TDM_IN_CH7, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1 Switch", AFE_CONN64,
I_I2S0_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1 Switch", AFE_CONN64,
I_I2S2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN64,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN64,
I_DL1_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1v", AFE_CONN64,
I_DL12_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH3 Switch", AFE_CONN64,
I_DL12_CH3, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN64,
I_DL2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN64,
I_DL3_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN64_1,
I_DL4_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN64_1,
I_DL5_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH1 Switch", AFE_CONN64_1,
I_SRC_1_OUT_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH1 Switch", AFE_CONN64_1,
I_SRC_2_OUT_CH1, 1, 0),
};
static const struct snd_kcontrol_new hw_cm1_ch8_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH8 Switch", AFE_CONN65_1,
I_TDM_IN_CH8, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2 Switch", AFE_CONN65,
I_I2S0_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2 Switch", AFE_CONN65,
I_I2S2_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN65,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN65,
I_DL1_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN65,
I_DL12_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH4 Switch", AFE_CONN65,
I_DL12_CH4, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN65,
I_DL2_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN65,
I_DL3_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN65_1,
I_DL4_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2 Switch", AFE_CONN65_1,
I_DL5_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH2 Switch", AFE_CONN65_1,
I_SRC_1_OUT_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH2 Switch", AFE_CONN65_1,
I_SRC_2_OUT_CH2, 1, 0),
};
static const struct snd_kcontrol_new hw_cm1_ch9_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1 Switch", AFE_CONN66,
I_I2S0_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1 Switch", AFE_CONN66,
I_I2S2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN66,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN66,
I_DL1_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1 Switch", AFE_CONN66,
I_DL12_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH3 Switch", AFE_CONN66,
I_DL12_CH3, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN66,
I_DL2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN66,
I_DL3_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN66_1,
I_DL4_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN66_1,
I_DL5_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH1 Switch", AFE_CONN66_1,
I_SRC_1_OUT_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH1 Switch", AFE_CONN66_1,
I_SRC_2_OUT_CH1, 1, 0),
};
static const struct snd_kcontrol_new hw_cm1_ch10_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2 Switch", AFE_CONN67,
I_I2S0_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2 Switch", AFE_CONN67,
I_I2S2_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN67,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN67,
I_DL1_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN67,
I_DL12_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH4 Switch", AFE_CONN67,
I_DL12_CH4, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN67,
I_DL2_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN67,
I_DL3_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN67_1,
I_DL4_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2 Switch", AFE_CONN67_1,
I_DL5_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH2 Switch", AFE_CONN67_1,
I_SRC_1_OUT_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH2 Switch", AFE_CONN67_1,
I_SRC_2_OUT_CH2, 1, 0),
};
static const struct snd_kcontrol_new hw_cm1_ch11_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1 Switch", AFE_CONN68,
I_I2S0_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1 Switch", AFE_CONN68,
I_I2S2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN68,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN68,
I_DL1_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1 Switch", AFE_CONN68,
I_DL12_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH3 Switch", AFE_CONN68,
I_DL12_CH3, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN68,
I_DL2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN68,
I_DL3_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN68_1,
I_DL4_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN68_1,
I_DL5_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH1 Switch", AFE_CONN68_1,
I_SRC_1_OUT_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH1 Switch", AFE_CONN68_1,
I_SRC_2_OUT_CH1, 1, 0),
};
static const struct snd_kcontrol_new hw_cm1_ch12_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2 Switch", AFE_CONN69,
I_I2S0_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2 Switch", AFE_CONN69,
I_I2S2_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN69,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN69,
I_DL1_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN69,
I_DL12_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH4 Switch", AFE_CONN69,
I_DL12_CH4, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN69,
I_DL2_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN69,
I_DL3_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN69_1,
I_DL4_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2 Switch", AFE_CONN69_1,
I_DL5_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH2 Switch", AFE_CONN69_1,
I_SRC_1_OUT_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH2 Switch", AFE_CONN69_1,
I_SRC_2_OUT_CH2, 1, 0),
};
/* ADDA UL MUX */
enum {
UL5_IN_MUX_CM1 = 0,
UL5_IN_MUX_NORMAL,
UL5_IN_MUX_MASK = 0x1,
};
static const char * const ul5_in_mux_map[] = {
"UL5_IN_FROM_CM1", "UL5_IN_FROM_Normal"
};
static int ul5_in_map_value[] = {
UL5_IN_MUX_CM1,
UL5_IN_MUX_NORMAL,
};
static SOC_VALUE_ENUM_SINGLE_DECL(ul5_in_mux_map_enum,
AFE_CM1_CON,
VUL3_BYPASS_CM_SFT,
VUL3_BYPASS_CM_MASK,
ul5_in_mux_map,
ul5_in_map_value);
static const struct snd_kcontrol_new ul5_in_mux_control =
SOC_DAPM_ENUM("UL5_IN_MUX Select", ul5_in_mux_map_enum);
static const struct snd_soc_dapm_widget mt8186_memif_widgets[] = {
/* inter-connections */
SND_SOC_DAPM_MIXER("UL1_CH1", SND_SOC_NOPM, 0, 0,
memif_ul1_ch1_mix, ARRAY_SIZE(memif_ul1_ch1_mix)),
SND_SOC_DAPM_MIXER("UL1_CH2", SND_SOC_NOPM, 0, 0,
memif_ul1_ch2_mix, ARRAY_SIZE(memif_ul1_ch2_mix)),
SND_SOC_DAPM_MIXER("UL1_CH3", SND_SOC_NOPM, 0, 0,
memif_ul1_ch3_mix, ARRAY_SIZE(memif_ul1_ch3_mix)),
SND_SOC_DAPM_MIXER("UL1_CH4", SND_SOC_NOPM, 0, 0,
memif_ul1_ch4_mix, ARRAY_SIZE(memif_ul1_ch4_mix)),
SND_SOC_DAPM_MIXER("UL2_CH1", SND_SOC_NOPM, 0, 0,
memif_ul2_ch1_mix, ARRAY_SIZE(memif_ul2_ch1_mix)),
SND_SOC_DAPM_MIXER("UL2_CH2", SND_SOC_NOPM, 0, 0,
memif_ul2_ch2_mix, ARRAY_SIZE(memif_ul2_ch2_mix)),
SND_SOC_DAPM_MIXER("UL3_CH1", SND_SOC_NOPM, 0, 0,
memif_ul3_ch1_mix, ARRAY_SIZE(memif_ul3_ch1_mix)),
SND_SOC_DAPM_MIXER("UL3_CH2", SND_SOC_NOPM, 0, 0,
memif_ul3_ch2_mix, ARRAY_SIZE(memif_ul3_ch2_mix)),
SND_SOC_DAPM_MIXER("UL4_CH1", SND_SOC_NOPM, 0, 0,
memif_ul4_ch1_mix, ARRAY_SIZE(memif_ul4_ch1_mix)),
SND_SOC_DAPM_MIXER("UL4_CH2", SND_SOC_NOPM, 0, 0,
memif_ul4_ch2_mix, ARRAY_SIZE(memif_ul4_ch2_mix)),
SND_SOC_DAPM_MIXER("UL5_CH1", SND_SOC_NOPM, 0, 0,
memif_ul5_ch1_mix, ARRAY_SIZE(memif_ul5_ch1_mix)),
SND_SOC_DAPM_MIXER("UL5_CH2", SND_SOC_NOPM, 0, 0,
memif_ul5_ch2_mix, ARRAY_SIZE(memif_ul5_ch2_mix)),
SND_SOC_DAPM_MIXER("UL6_CH1", SND_SOC_NOPM, 0, 0,
memif_ul6_ch1_mix, ARRAY_SIZE(memif_ul6_ch1_mix)),
SND_SOC_DAPM_MIXER("UL6_CH2", SND_SOC_NOPM, 0, 0,
memif_ul6_ch2_mix, ARRAY_SIZE(memif_ul6_ch2_mix)),
SND_SOC_DAPM_MIXER("UL7_CH1", SND_SOC_NOPM, 0, 0,
memif_ul7_ch1_mix, ARRAY_SIZE(memif_ul7_ch1_mix)),
SND_SOC_DAPM_MIXER("UL7_CH2", SND_SOC_NOPM, 0, 0,
memif_ul7_ch2_mix, ARRAY_SIZE(memif_ul7_ch2_mix)),
SND_SOC_DAPM_MIXER("UL8_CH1", SND_SOC_NOPM, 0, 0,
memif_ul8_ch1_mix, ARRAY_SIZE(memif_ul8_ch1_mix)),
SND_SOC_DAPM_MIXER("UL8_CH2", SND_SOC_NOPM, 0, 0,
memif_ul8_ch2_mix, ARRAY_SIZE(memif_ul8_ch2_mix)),
SND_SOC_DAPM_MIXER("UL5_2CH", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("HW_CM1", SND_SOC_NOPM, 0, 0, NULL, 0),
/* CM1 en*/
SND_SOC_DAPM_SUPPLY_S("CM1_EN", 0, AFE_CM1_CON,
CHANNEL_MERGE0_EN_SFT, 0, NULL,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER("HW_CM1_CH1", SND_SOC_NOPM, 0, 0,
hw_cm1_ch1_mix, ARRAY_SIZE(hw_cm1_ch1_mix)),
SND_SOC_DAPM_MIXER("HW_CM1_CH2", SND_SOC_NOPM, 0, 0,
hw_cm1_ch2_mix, ARRAY_SIZE(hw_cm1_ch2_mix)),
SND_SOC_DAPM_MIXER("HW_CM1_CH3", SND_SOC_NOPM, 0, 0,
hw_cm1_ch3_mix, ARRAY_SIZE(hw_cm1_ch3_mix)),
SND_SOC_DAPM_MIXER("HW_CM1_CH4", SND_SOC_NOPM, 0, 0,
hw_cm1_ch4_mix, ARRAY_SIZE(hw_cm1_ch4_mix)),
SND_SOC_DAPM_MIXER("HW_CM1_CH5", SND_SOC_NOPM, 0, 0,
hw_cm1_ch5_mix, ARRAY_SIZE(hw_cm1_ch5_mix)),
SND_SOC_DAPM_MIXER("HW_CM1_CH6", SND_SOC_NOPM, 0, 0,
hw_cm1_ch6_mix, ARRAY_SIZE(hw_cm1_ch6_mix)),
SND_SOC_DAPM_MIXER("HW_CM1_CH7", SND_SOC_NOPM, 0, 0,
hw_cm1_ch7_mix, ARRAY_SIZE(hw_cm1_ch7_mix)),
SND_SOC_DAPM_MIXER("HW_CM1_CH8", SND_SOC_NOPM, 0, 0,
hw_cm1_ch8_mix, ARRAY_SIZE(hw_cm1_ch8_mix)),
SND_SOC_DAPM_MIXER("HW_CM1_CH9", SND_SOC_NOPM, 0, 0,
hw_cm1_ch9_mix, ARRAY_SIZE(hw_cm1_ch9_mix)),
SND_SOC_DAPM_MIXER("HW_CM1_CH10", SND_SOC_NOPM, 0, 0,
hw_cm1_ch10_mix, ARRAY_SIZE(hw_cm1_ch10_mix)),
SND_SOC_DAPM_MIXER("HW_CM1_CH11", SND_SOC_NOPM, 0, 0,
hw_cm1_ch11_mix, ARRAY_SIZE(hw_cm1_ch11_mix)),
SND_SOC_DAPM_MIXER("HW_CM1_CH12", SND_SOC_NOPM, 0, 0,
hw_cm1_ch12_mix, ARRAY_SIZE(hw_cm1_ch12_mix)),
SND_SOC_DAPM_MUX("UL5_IN_MUX", SND_SOC_NOPM, 0, 0,
&ul5_in_mux_control),
SND_SOC_DAPM_MIXER("DSP_DL1_VIRT", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("DSP_DL2_VIRT", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_INPUT("UL1_VIRTUAL_INPUT"),
SND_SOC_DAPM_INPUT("UL2_VIRTUAL_INPUT"),
SND_SOC_DAPM_INPUT("UL3_VIRTUAL_INPUT"),
SND_SOC_DAPM_INPUT("UL4_VIRTUAL_INPUT"),
SND_SOC_DAPM_INPUT("UL5_VIRTUAL_INPUT"),
SND_SOC_DAPM_INPUT("UL6_VIRTUAL_INPUT"),
};
static const struct snd_soc_dapm_route mt8186_memif_routes[] = {
{"UL1", NULL, "UL1_CH1"},
{"UL1", NULL, "UL1_CH2"},
{"UL1", NULL, "UL1_CH3"},
{"UL1", NULL, "UL1_CH4"},
{"UL1_CH1", "ADDA_UL_CH1 Switch", "ADDA_UL_Mux"},
{"UL1_CH1", "ADDA_UL_CH2 Switch", "ADDA_UL_Mux"},
{"UL1_CH2", "ADDA_UL_CH1 Switch", "ADDA_UL_Mux"},
{"UL1_CH2", "ADDA_UL_CH2 Switch", "ADDA_UL_Mux"},
{"UL1_CH3", "ADDA_UL_CH1 Switch", "ADDA_UL_Mux"},
{"UL1_CH3", "ADDA_UL_CH2 Switch", "ADDA_UL_Mux"},
{"UL1_CH4", "ADDA_UL_CH1 Switch", "ADDA_UL_Mux"},
{"UL1_CH4", "ADDA_UL_CH2 Switch", "ADDA_UL_Mux"},
{"UL1_CH1", "TDM_IN_CH1 Switch", "TDM IN"},
{"UL1_CH2", "TDM_IN_CH2 Switch", "TDM IN"},
{"UL1_CH3", "TDM_IN_CH3 Switch", "TDM IN"},
{"UL1_CH4", "TDM_IN_CH4 Switch", "TDM IN"},
{"UL2", NULL, "UL2_CH1"},
{"UL2", NULL, "UL2_CH2"},
/* cannot connect FE to FE directly */
{"UL2_CH1", "DL1_CH1 Switch", "Hostless_UL2 UL"},
{"UL2_CH2", "DL1_CH2 Switch", "Hostless_UL2 UL"},
{"UL2_CH1", "DL12_CH1 Switch", "Hostless_UL2 UL"},
{"UL2_CH2", "DL12_CH2 Switch", "Hostless_UL2 UL"},
{"UL2_CH1", "DL6_CH1 Switch", "Hostless_UL2 UL"},
{"UL2_CH2", "DL6_CH2 Switch", "Hostless_UL2 UL"},
{"UL2_CH1", "DL2_CH1 Switch", "Hostless_UL2 UL"},
{"UL2_CH2", "DL2_CH2 Switch", "Hostless_UL2 UL"},
{"UL2_CH1", "DL3_CH1 Switch", "Hostless_UL2 UL"},
{"UL2_CH2", "DL3_CH2 Switch", "Hostless_UL2 UL"},
{"UL2_CH1", "DL4_CH1 Switch", "Hostless_UL2 UL"},
{"UL2_CH2", "DL4_CH2 Switch", "Hostless_UL2 UL"},
{"UL2_CH1", "DL5_CH1 Switch", "Hostless_UL2 UL"},
{"UL2_CH2", "DL5_CH2 Switch", "Hostless_UL2 UL"},
{"Hostless_UL2 UL", NULL, "UL2_VIRTUAL_INPUT"},
{"UL2_CH1", "I2S0_CH1 Switch", "I2S0"},
{"UL2_CH2", "I2S0_CH2 Switch", "I2S0"},
{"UL2_CH1", "I2S2_CH1 Switch", "I2S2"},
{"UL2_CH2", "I2S2_CH2 Switch", "I2S2"},
{"UL2_CH1", "PCM_1_CAP_CH1 Switch", "PCM 1 Capture"},
{"UL2_CH2", "PCM_1_CAP_CH2 Switch", "PCM 1 Capture"},
{"UL2_CH1", "CONNSYS_I2S_CH1 Switch", "Connsys I2S"},
{"UL2_CH2", "CONNSYS_I2S_CH2 Switch", "Connsys I2S"},
{"UL2_CH1", "SRC_1_OUT_CH1 Switch", "HW_SRC_1_Out"},
{"UL2_CH2", "SRC_1_OUT_CH2 Switch", "HW_SRC_1_Out"},
{"UL3", NULL, "UL3_CH1"},
{"UL3", NULL, "UL3_CH2"},
{"UL3_CH1", "CONNSYS_I2S_CH1 Switch", "Connsys I2S"},
{"UL3_CH2", "CONNSYS_I2S_CH2 Switch", "Connsys I2S"},
{"UL4", NULL, "UL4_CH1"},
{"UL4", NULL, "UL4_CH2"},
{"UL4_CH1", "ADDA_UL_CH1 Switch", "ADDA_UL_Mux"},
{"UL4_CH2", "ADDA_UL_CH2 Switch", "ADDA_UL_Mux"},
{"UL4_CH1", "I2S0_CH1 Switch", "I2S0"},
{"UL4_CH2", "I2S0_CH2 Switch", "I2S0"},
{"UL5", NULL, "UL5_IN_MUX"},
{"UL5_IN_MUX", "UL5_IN_FROM_Normal", "UL5_2CH"},
{"UL5_IN_MUX", "UL5_IN_FROM_CM1", "HW_CM1"},
{"UL5_2CH", NULL, "UL5_CH1"},
{"UL5_2CH", NULL, "UL5_CH2"},
{"UL5_CH1", "ADDA_UL_CH1 Switch", "ADDA_UL_Mux"},
{"UL5_CH2", "ADDA_UL_CH2 Switch", "ADDA_UL_Mux"},
{"HW_CM1", NULL, "CM1_EN"},
{"HW_CM1", NULL, "HW_CM1_CH1"},
{"HW_CM1", NULL, "HW_CM1_CH2"},
{"HW_CM1", NULL, "HW_CM1_CH3"},
{"HW_CM1", NULL, "HW_CM1_CH4"},
{"HW_CM1", NULL, "HW_CM1_CH5"},
{"HW_CM1", NULL, "HW_CM1_CH6"},
{"HW_CM1", NULL, "HW_CM1_CH7"},
{"HW_CM1", NULL, "HW_CM1_CH8"},
{"HW_CM1", NULL, "HW_CM1_CH9"},
{"HW_CM1", NULL, "HW_CM1_CH10"},
{"HW_CM1", NULL, "HW_CM1_CH11"},
{"HW_CM1", NULL, "HW_CM1_CH12"},
{"HW_CM1_CH1", "TDM_IN_CH1 Switch", "TDM IN"},
{"HW_CM1_CH2", "TDM_IN_CH2 Switch", "TDM IN"},
{"HW_CM1_CH3", "TDM_IN_CH3 Switch", "TDM IN"},
{"HW_CM1_CH4", "TDM_IN_CH4 Switch", "TDM IN"},
{"HW_CM1_CH5", "TDM_IN_CH5 Switch", "TDM IN"},
{"HW_CM1_CH6", "TDM_IN_CH6 Switch", "TDM IN"},
{"HW_CM1_CH7", "TDM_IN_CH7 Switch", "TDM IN"},
{"HW_CM1_CH8", "TDM_IN_CH8 Switch", "TDM IN"},
{"HW_CM1_CH9", "DL1_CH1 Switch", "Hostless_UL5 UL"},
{"HW_CM1_CH10", "DL1_CH2 Switch", "Hostless_UL5 UL"},
{"HW_CM1_CH3", "DL1_CH1 Switch", "Hostless_UL5 UL"},
{"HW_CM1_CH4", "DL1_CH2 Switch", "Hostless_UL5 UL"},
{"HW_CM1_CH3", "DL3_CH1 Switch", "Hostless_UL5 UL"},
{"HW_CM1_CH4", "DL3_CH2 Switch", "Hostless_UL5 UL"},
{"HW_CM1_CH5", "HW_SRC1_OUT_CH1 Switch", "HW_SRC_1_Out"},
{"HW_CM1_CH6", "HW_SRC1_OUT_CH2 Switch", "HW_SRC_1_Out"},
{"HW_CM1_CH9", "DL12_CH1 Switch", "Hostless_UL5 UL"},
{"HW_CM1_CH10", "DL12_CH2 Switch", "Hostless_UL5 UL"},
{"HW_CM1_CH11", "DL12_CH3 Switch", "Hostless_UL5 UL"},
{"HW_CM1_CH12", "DL12_CH4 Switch", "Hostless_UL5 UL"},
{"Hostless_UL5 UL", NULL, "UL5_VIRTUAL_INPUT"},
{"UL6", NULL, "UL6_CH1"},
{"UL6", NULL, "UL6_CH2"},
{"UL6_CH1", "ADDA_UL_CH1 Switch", "ADDA_UL_Mux"},
{"UL6_CH2", "ADDA_UL_CH2 Switch", "ADDA_UL_Mux"},
{"UL6_CH1", "DL1_CH1 Switch", "Hostless_UL6 UL"},
{"UL6_CH2", "DL1_CH2 Switch", "Hostless_UL6 UL"},
{"UL6_CH1", "DL2_CH1 Switch", "Hostless_UL6 UL"},
{"UL6_CH2", "DL2_CH2 Switch", "Hostless_UL6 UL"},
{"UL6_CH1", "DL12_CH1 Switch", "Hostless_UL6 UL"},
{"UL6_CH2", "DL12_CH2 Switch", "Hostless_UL6 UL"},
{"UL6_CH1", "DL6_CH1 Switch", "Hostless_UL6 UL"},
{"UL6_CH2", "DL6_CH2 Switch", "Hostless_UL6 UL"},
{"UL6_CH1", "DL3_CH1 Switch", "Hostless_UL6 UL"},
{"UL6_CH2", "DL3_CH2 Switch", "Hostless_UL6 UL"},
{"UL6_CH1", "DL4_CH1 Switch", "Hostless_UL6 UL"},
{"UL6_CH2", "DL4_CH2 Switch", "Hostless_UL6 UL"},
{"Hostless_UL6 UL", NULL, "UL6_VIRTUAL_INPUT"},
{"UL6_CH1", "PCM_1_CAP_CH1 Switch", "PCM 1 Capture"},
{"UL6_CH2", "PCM_1_CAP_CH2 Switch", "PCM 1 Capture"},
{"UL6_CH1", "GAIN1_OUT_CH1 Switch", "HW Gain 1 Out"},
{"UL6_CH2", "GAIN1_OUT_CH2 Switch", "HW Gain 1 Out"},
{"UL7", NULL, "UL7_CH1"},
{"UL7", NULL, "UL7_CH2"},
{"UL7_CH1", "ADDA_UL_CH1 Switch", "ADDA_UL_Mux"},
{"UL7_CH2", "ADDA_UL_CH2 Switch", "ADDA_UL_Mux"},
{"UL7_CH1", "HW_GAIN2_OUT_CH1 Switch", "HW Gain 2 Out"},
{"UL7_CH2", "HW_GAIN2_OUT_CH2 Switch", "HW Gain 2 Out"},
{"UL7_CH1", "HW_SRC_2_OUT_CH1 Switch", "HW_SRC_2_Out"},
{"UL7_CH2", "HW_SRC_2_OUT_CH2 Switch", "HW_SRC_2_Out"},
{"UL8", NULL, "UL8_CH1"},
{"UL8", NULL, "UL8_CH2"},
{"UL8_CH1", "ADDA_UL_CH1 Switch", "ADDA_UL_Mux"},
{"UL8_CH2", "ADDA_UL_CH2 Switch", "ADDA_UL_Mux"},
{"HW_GAIN2_IN_CH1", "ADDA_UL_CH1 Switch", "ADDA_UL_Mux"},
{"HW_GAIN2_IN_CH2", "ADDA_UL_CH2 Switch", "ADDA_UL_Mux"},
};
static const struct mtk_base_memif_data memif_data[MT8186_MEMIF_NUM] = {
[MT8186_MEMIF_DL1] = {
.name = "DL1",
.id = MT8186_MEMIF_DL1,
.reg_ofs_base = AFE_DL1_BASE,
.reg_ofs_cur = AFE_DL1_CUR,
.reg_ofs_end = AFE_DL1_END,
.reg_ofs_base_msb = AFE_DL1_BASE_MSB,
.reg_ofs_cur_msb = AFE_DL1_CUR_MSB,
.reg_ofs_end_msb = AFE_DL1_END_MSB,
.fs_reg = AFE_DL1_CON0,
.fs_shift = DL1_MODE_SFT,
.fs_maskbit = DL1_MODE_MASK,
.mono_reg = AFE_DL1_CON0,
.mono_shift = DL1_MONO_SFT,
.enable_reg = AFE_DAC_CON0,
.enable_shift = DL1_ON_SFT,
.hd_reg = AFE_DL1_CON0,
.hd_shift = DL1_HD_MODE_SFT,
.hd_align_reg = AFE_DL1_CON0,
.hd_align_mshift = DL1_HALIGN_SFT,
.agent_disable_reg = -1,
.agent_disable_shift = -1,
.msb_reg = -1,
.msb_shift = -1,
.pbuf_reg = AFE_DL1_CON0,
.pbuf_mask = DL1_PBUF_SIZE_MASK,
.pbuf_shift = DL1_PBUF_SIZE_SFT,
.minlen_reg = AFE_DL1_CON0,
.minlen_mask = DL1_MINLEN_MASK,
.minlen_shift = DL1_MINLEN_SFT,
},
[MT8186_MEMIF_DL12] = {
.name = "DL12",
.id = MT8186_MEMIF_DL12,
.reg_ofs_base = AFE_DL12_BASE,
.reg_ofs_cur = AFE_DL12_CUR,
.reg_ofs_end = AFE_DL12_END,
.reg_ofs_base_msb = AFE_DL12_BASE_MSB,
.reg_ofs_cur_msb = AFE_DL12_CUR_MSB,
.reg_ofs_end_msb = AFE_DL12_END_MSB,
.fs_reg = AFE_DL12_CON0,
.fs_shift = DL12_MODE_SFT,
.fs_maskbit = DL12_MODE_MASK,
.mono_reg = AFE_DL12_CON0,
.mono_shift = DL12_MONO_SFT,
.quad_ch_reg = AFE_DL12_CON0,
.quad_ch_mask = DL12_4CH_EN_MASK,
.quad_ch_shift = DL12_4CH_EN_SFT,
.enable_reg = AFE_DAC_CON0,
.enable_shift = DL12_ON_SFT,
.hd_reg = AFE_DL12_CON0,
.hd_shift = DL12_HD_MODE_SFT,
.hd_align_reg = AFE_DL12_CON0,
.hd_align_mshift = DL12_HALIGN_SFT,
.agent_disable_reg = -1,
.agent_disable_shift = -1,
.msb_reg = -1,
.msb_shift = -1,
.pbuf_reg = AFE_DL12_CON0,
.pbuf_mask = DL12_PBUF_SIZE_MASK,
.pbuf_shift = DL12_PBUF_SIZE_SFT,
.minlen_reg = AFE_DL12_CON0,
.minlen_mask = DL12_MINLEN_MASK,
.minlen_shift = DL12_MINLEN_SFT,
},
[MT8186_MEMIF_DL2] = {
.name = "DL2",
.id = MT8186_MEMIF_DL2,
.reg_ofs_base = AFE_DL2_BASE,
.reg_ofs_cur = AFE_DL2_CUR,
.reg_ofs_end = AFE_DL2_END,
.reg_ofs_base_msb = AFE_DL2_BASE_MSB,
.reg_ofs_cur_msb = AFE_DL2_CUR_MSB,
.reg_ofs_end_msb = AFE_DL2_END_MSB,
.fs_reg = AFE_DL2_CON0,
.fs_shift = DL2_MODE_SFT,
.fs_maskbit = DL2_MODE_MASK,
.mono_reg = AFE_DL2_CON0,
.mono_shift = DL2_MONO_SFT,
.enable_reg = AFE_DAC_CON0,
.enable_shift = DL2_ON_SFT,
.hd_reg = AFE_DL2_CON0,
.hd_shift = DL2_HD_MODE_SFT,
.hd_align_reg = AFE_DL2_CON0,
.hd_align_mshift = DL2_HALIGN_SFT,
.agent_disable_reg = -1,
.agent_disable_shift = -1,
.msb_reg = -1,
.msb_shift = -1,
.pbuf_reg = AFE_DL2_CON0,
.pbuf_mask = DL2_PBUF_SIZE_MASK,
.pbuf_shift = DL2_PBUF_SIZE_SFT,
.minlen_reg = AFE_DL2_CON0,
.minlen_mask = DL2_MINLEN_MASK,
.minlen_shift = DL2_MINLEN_SFT,
},
[MT8186_MEMIF_DL3] = {
.name = "DL3",
.id = MT8186_MEMIF_DL3,
.reg_ofs_base = AFE_DL3_BASE,
.reg_ofs_cur = AFE_DL3_CUR,
.reg_ofs_end = AFE_DL3_END,
.reg_ofs_base_msb = AFE_DL3_BASE_MSB,
.reg_ofs_cur_msb = AFE_DL3_CUR_MSB,
.reg_ofs_end_msb = AFE_DL3_END_MSB,
.fs_reg = AFE_DL3_CON0,
.fs_shift = DL3_MODE_SFT,
.fs_maskbit = DL3_MODE_MASK,
.mono_reg = AFE_DL3_CON0,
.mono_shift = DL3_MONO_SFT,
.enable_reg = AFE_DAC_CON0,
.enable_shift = DL3_ON_SFT,
.hd_reg = AFE_DL3_CON0,
.hd_shift = DL3_HD_MODE_SFT,
.hd_align_reg = AFE_DL3_CON0,
.hd_align_mshift = DL3_HALIGN_SFT,
.agent_disable_reg = -1,
.agent_disable_shift = -1,
.msb_reg = -1,
.msb_shift = -1,
.pbuf_reg = AFE_DL3_CON0,
.pbuf_mask = DL3_PBUF_SIZE_MASK,
.pbuf_shift = DL3_PBUF_SIZE_SFT,
.minlen_reg = AFE_DL3_CON0,
.minlen_mask = DL3_MINLEN_MASK,
.minlen_shift = DL3_MINLEN_SFT,
},
[MT8186_MEMIF_DL4] = {
.name = "DL4",
.id = MT8186_MEMIF_DL4,
.reg_ofs_base = AFE_DL4_BASE,
.reg_ofs_cur = AFE_DL4_CUR,
.reg_ofs_end = AFE_DL4_END,
.reg_ofs_base_msb = AFE_DL4_BASE_MSB,
.reg_ofs_cur_msb = AFE_DL4_CUR_MSB,
.reg_ofs_end_msb = AFE_DL4_END_MSB,
.fs_reg = AFE_DL4_CON0,
.fs_shift = DL4_MODE_SFT,
.fs_maskbit = DL4_MODE_MASK,
.mono_reg = AFE_DL4_CON0,
.mono_shift = DL4_MONO_SFT,
.enable_reg = AFE_DAC_CON0,
.enable_shift = DL4_ON_SFT,
.hd_reg = AFE_DL4_CON0,
.hd_shift = DL4_HD_MODE_SFT,
.hd_align_reg = AFE_DL4_CON0,
.hd_align_mshift = DL4_HALIGN_SFT,
.agent_disable_reg = -1,
.agent_disable_shift = -1,
.msb_reg = -1,
.msb_shift = -1,
.pbuf_reg = AFE_DL4_CON0,
.pbuf_mask = DL4_PBUF_SIZE_MASK,
.pbuf_shift = DL4_PBUF_SIZE_SFT,
.minlen_reg = AFE_DL4_CON0,
.minlen_mask = DL4_MINLEN_MASK,
.minlen_shift = DL4_MINLEN_SFT,
},
[MT8186_MEMIF_DL5] = {
.name = "DL5",
.id = MT8186_MEMIF_DL5,
.reg_ofs_base = AFE_DL5_BASE,
.reg_ofs_cur = AFE_DL5_CUR,
.reg_ofs_end = AFE_DL5_END,
.reg_ofs_base_msb = AFE_DL5_BASE_MSB,
.reg_ofs_cur_msb = AFE_DL5_CUR_MSB,
.reg_ofs_end_msb = AFE_DL5_END_MSB,
.fs_reg = AFE_DL5_CON0,
.fs_shift = DL5_MODE_SFT,
.fs_maskbit = DL5_MODE_MASK,
.mono_reg = AFE_DL5_CON0,
.mono_shift = DL5_MONO_SFT,
.enable_reg = AFE_DAC_CON0,
.enable_shift = DL5_ON_SFT,
.hd_reg = AFE_DL5_CON0,
.hd_shift = DL5_HD_MODE_SFT,
.hd_align_reg = AFE_DL5_CON0,
.hd_align_mshift = DL5_HALIGN_SFT,
.agent_disable_reg = -1,
.agent_disable_shift = -1,
.msb_reg = -1,
.msb_shift = -1,
.pbuf_reg = AFE_DL5_CON0,
.pbuf_mask = DL5_PBUF_SIZE_MASK,
.pbuf_shift = DL5_PBUF_SIZE_SFT,
.minlen_reg = AFE_DL5_CON0,
.minlen_mask = DL5_MINLEN_MASK,
.minlen_shift = DL5_MINLEN_SFT,
},
[MT8186_MEMIF_DL6] = {
.name = "DL6",
.id = MT8186_MEMIF_DL6,
.reg_ofs_base = AFE_DL6_BASE,
.reg_ofs_cur = AFE_DL6_CUR,
.reg_ofs_end = AFE_DL6_END,
.reg_ofs_base_msb = AFE_DL6_BASE_MSB,
.reg_ofs_cur_msb = AFE_DL6_CUR_MSB,
.reg_ofs_end_msb = AFE_DL6_END_MSB,
.fs_reg = AFE_DL6_CON0,
.fs_shift = DL6_MODE_SFT,
.fs_maskbit = DL6_MODE_MASK,
.mono_reg = AFE_DL6_CON0,
.mono_shift = DL6_MONO_SFT,
.enable_reg = AFE_DAC_CON0,
.enable_shift = DL6_ON_SFT,
.hd_reg = AFE_DL6_CON0,
.hd_shift = DL6_HD_MODE_SFT,
.hd_align_reg = AFE_DL6_CON0,
.hd_align_mshift = DL6_HALIGN_SFT,
.agent_disable_reg = -1,
.agent_disable_shift = -1,
.msb_reg = -1,
.msb_shift = -1,
.pbuf_reg = AFE_DL6_CON0,
.pbuf_mask = DL6_PBUF_SIZE_MASK,
.pbuf_shift = DL6_PBUF_SIZE_SFT,
.minlen_reg = AFE_DL6_CON0,
.minlen_mask = DL6_MINLEN_MASK,
.minlen_shift = DL6_MINLEN_SFT,
},
[MT8186_MEMIF_DL7] = {
.name = "DL7",
.id = MT8186_MEMIF_DL7,
.reg_ofs_base = AFE_DL7_BASE,
.reg_ofs_cur = AFE_DL7_CUR,
.reg_ofs_end = AFE_DL7_END,
.reg_ofs_base_msb = AFE_DL7_BASE_MSB,
.reg_ofs_cur_msb = AFE_DL7_CUR_MSB,
.reg_ofs_end_msb = AFE_DL7_END_MSB,
.fs_reg = AFE_DL7_CON0,
.fs_shift = DL7_MODE_SFT,
.fs_maskbit = DL7_MODE_MASK,
.mono_reg = AFE_DL7_CON0,
.mono_shift = DL7_MONO_SFT,
.enable_reg = AFE_DAC_CON0,
.enable_shift = DL7_ON_SFT,
.hd_reg = AFE_DL7_CON0,
.hd_shift = DL7_HD_MODE_SFT,
.hd_align_reg = AFE_DL7_CON0,
.hd_align_mshift = DL7_HALIGN_SFT,
.agent_disable_reg = -1,
.agent_disable_shift = -1,
.msb_reg = -1,
.msb_shift = -1,
.pbuf_reg = AFE_DL7_CON0,
.pbuf_mask = DL7_PBUF_SIZE_MASK,
.pbuf_shift = DL7_PBUF_SIZE_SFT,
.minlen_reg = AFE_DL7_CON0,
.minlen_mask = DL7_MINLEN_MASK,
.minlen_shift = DL7_MINLEN_SFT,
},
[MT8186_MEMIF_DL8] = {
.name = "DL8",
.id = MT8186_MEMIF_DL8,
.reg_ofs_base = AFE_DL8_BASE,
.reg_ofs_cur = AFE_DL8_CUR,
.reg_ofs_end = AFE_DL8_END,
.reg_ofs_base_msb = AFE_DL8_BASE_MSB,
.reg_ofs_cur_msb = AFE_DL8_CUR_MSB,
.reg_ofs_end_msb = AFE_DL8_END_MSB,
.fs_reg = AFE_DL8_CON0,
.fs_shift = DL8_MODE_SFT,
.fs_maskbit = DL8_MODE_MASK,
.mono_reg = AFE_DL8_CON0,
.mono_shift = DL8_MONO_SFT,
.enable_reg = AFE_DAC_CON0,
.enable_shift = DL8_ON_SFT,
.hd_reg = AFE_DL8_CON0,
.hd_shift = DL8_HD_MODE_SFT,
.hd_align_reg = AFE_DL8_CON0,
.hd_align_mshift = DL8_HALIGN_SFT,
.agent_disable_reg = -1,
.agent_disable_shift = -1,
.msb_reg = -1,
.msb_shift = -1,
.pbuf_reg = AFE_DL8_CON0,
.pbuf_mask = DL8_PBUF_SIZE_MASK,
.pbuf_shift = DL8_PBUF_SIZE_SFT,
.minlen_reg = AFE_DL8_CON0,
.minlen_mask = DL8_MINLEN_MASK,
.minlen_shift = DL8_MINLEN_SFT,
},
[MT8186_MEMIF_VUL12] = {
.name = "VUL12",
.id = MT8186_MEMIF_VUL12,
.reg_ofs_base = AFE_VUL12_BASE,
.reg_ofs_cur = AFE_VUL12_CUR,
.reg_ofs_end = AFE_VUL12_END,
.reg_ofs_base_msb = AFE_VUL12_BASE_MSB,
.reg_ofs_cur_msb = AFE_VUL12_CUR_MSB,
.reg_ofs_end_msb = AFE_VUL12_END_MSB,
.fs_reg = AFE_VUL12_CON0,
.fs_shift = VUL12_MODE_SFT,
.fs_maskbit = VUL12_MODE_MASK,
.mono_reg = AFE_VUL12_CON0,
.mono_shift = VUL12_MONO_SFT,
.quad_ch_reg = AFE_VUL12_CON0,
.quad_ch_mask = VUL12_4CH_EN_MASK,
.quad_ch_shift = VUL12_4CH_EN_SFT,
.enable_reg = AFE_DAC_CON0,
.enable_shift = VUL12_ON_SFT,
.hd_reg = AFE_VUL12_CON0,
.hd_shift = VUL12_HD_MODE_SFT,
.hd_align_reg = AFE_VUL12_CON0,
.hd_align_mshift = VUL12_HALIGN_SFT,
.agent_disable_reg = -1,
.agent_disable_shift = -1,
.msb_reg = -1,
.msb_shift = -1,
},
[MT8186_MEMIF_VUL2] = {
.name = "VUL2",
.id = MT8186_MEMIF_VUL2,
.reg_ofs_base = AFE_VUL2_BASE,
.reg_ofs_cur = AFE_VUL2_CUR,
.reg_ofs_end = AFE_VUL2_END,
.reg_ofs_base_msb = AFE_VUL2_BASE_MSB,
.reg_ofs_cur_msb = AFE_VUL2_CUR_MSB,
.reg_ofs_end_msb = AFE_VUL2_END_MSB,
.fs_reg = AFE_VUL2_CON0,
.fs_shift = VUL2_MODE_SFT,
.fs_maskbit = VUL2_MODE_MASK,
.mono_reg = AFE_VUL2_CON0,
.mono_shift = VUL2_MONO_SFT,
.enable_reg = AFE_DAC_CON0,
.enable_shift = VUL2_ON_SFT,
.hd_reg = AFE_VUL2_CON0,
.hd_shift = VUL2_HD_MODE_SFT,
.hd_align_reg = AFE_VUL2_CON0,
.hd_align_mshift = VUL2_HALIGN_SFT,
.agent_disable_reg = -1,
.agent_disable_shift = -1,
.msb_reg = -1,
.msb_shift = -1,
},
[MT8186_MEMIF_AWB] = {
.name = "AWB",
.id = MT8186_MEMIF_AWB,
.reg_ofs_base = AFE_AWB_BASE,
.reg_ofs_cur = AFE_AWB_CUR,
.reg_ofs_end = AFE_AWB_END,
.reg_ofs_base_msb = AFE_AWB_BASE_MSB,
.reg_ofs_cur_msb = AFE_AWB_CUR_MSB,
.reg_ofs_end_msb = AFE_AWB_END_MSB,
.fs_reg = AFE_AWB_CON0,
.fs_shift = AWB_MODE_SFT,
.fs_maskbit = AWB_MODE_MASK,
.mono_reg = AFE_AWB_CON0,
.mono_shift = AWB_MONO_SFT,
.enable_reg = AFE_DAC_CON0,
.enable_shift = AWB_ON_SFT,
.hd_reg = AFE_AWB_CON0,
.hd_shift = AWB_HD_MODE_SFT,
.hd_align_reg = AFE_AWB_CON0,
.hd_align_mshift = AWB_HALIGN_SFT,
.agent_disable_reg = -1,
.agent_disable_shift = -1,
.msb_reg = -1,
.msb_shift = -1,
},
[MT8186_MEMIF_AWB2] = {
.name = "AWB2",
.id = MT8186_MEMIF_AWB2,
.reg_ofs_base = AFE_AWB2_BASE,
.reg_ofs_cur = AFE_AWB2_CUR,
.reg_ofs_end = AFE_AWB2_END,
.reg_ofs_base_msb = AFE_AWB2_BASE_MSB,
.reg_ofs_cur_msb = AFE_AWB2_CUR_MSB,
.reg_ofs_end_msb = AFE_AWB2_END_MSB,
.fs_reg = AFE_AWB2_CON0,
.fs_shift = AWB2_MODE_SFT,
.fs_maskbit = AWB2_MODE_MASK,
.mono_reg = AFE_AWB2_CON0,
.mono_shift = AWB2_MONO_SFT,
.enable_reg = AFE_DAC_CON0,
.enable_shift = AWB2_ON_SFT,
.hd_reg = AFE_AWB2_CON0,
.hd_shift = AWB2_HD_MODE_SFT,
.hd_align_reg = AFE_AWB2_CON0,
.hd_align_mshift = AWB2_HALIGN_SFT,
.agent_disable_reg = -1,
.agent_disable_shift = -1,
.msb_reg = -1,
.msb_shift = -1,
},
[MT8186_MEMIF_VUL3] = {
.name = "VUL3",
.id = MT8186_MEMIF_VUL3,
.reg_ofs_base = AFE_VUL3_BASE,
.reg_ofs_cur = AFE_VUL3_CUR,
.reg_ofs_end = AFE_VUL3_END,
.reg_ofs_base_msb = AFE_VUL3_BASE_MSB,
.reg_ofs_cur_msb = AFE_VUL3_CUR_MSB,
.reg_ofs_end_msb = AFE_VUL3_END_MSB,
.fs_reg = AFE_VUL3_CON0,
.fs_shift = VUL3_MODE_SFT,
.fs_maskbit = VUL3_MODE_MASK,
.mono_reg = AFE_VUL3_CON0,
.mono_shift = VUL3_MONO_SFT,
.enable_reg = AFE_DAC_CON0,
.enable_shift = VUL3_ON_SFT,
.hd_reg = AFE_VUL3_CON0,
.hd_shift = VUL3_HD_MODE_SFT,
.hd_align_reg = AFE_VUL3_CON0,
.hd_align_mshift = VUL3_HALIGN_SFT,
.agent_disable_reg = -1,
.agent_disable_shift = -1,
.msb_reg = -1,
.msb_shift = -1,
},
[MT8186_MEMIF_VUL4] = {
.name = "VUL4",
.id = MT8186_MEMIF_VUL4,
.reg_ofs_base = AFE_VUL4_BASE,
.reg_ofs_cur = AFE_VUL4_CUR,
.reg_ofs_end = AFE_VUL4_END,
.reg_ofs_base_msb = AFE_VUL4_BASE_MSB,
.reg_ofs_cur_msb = AFE_VUL4_CUR_MSB,
.reg_ofs_end_msb = AFE_VUL4_END_MSB,
.fs_reg = AFE_VUL4_CON0,
.fs_shift = VUL4_MODE_SFT,
.fs_maskbit = VUL4_MODE_MASK,
.mono_reg = AFE_VUL4_CON0,
.mono_shift = VUL4_MONO_SFT,
.enable_reg = AFE_DAC_CON0,
.enable_shift = VUL4_ON_SFT,
.hd_reg = AFE_VUL4_CON0,
.hd_shift = VUL4_HD_MODE_SFT,
.hd_align_reg = AFE_VUL4_CON0,
.hd_align_mshift = VUL4_HALIGN_SFT,
.agent_disable_reg = -1,
.agent_disable_shift = -1,
.msb_reg = -1,
.msb_shift = -1,
},
[MT8186_MEMIF_VUL5] = {
.name = "VUL5",
.id = MT8186_MEMIF_VUL5,
.reg_ofs_base = AFE_VUL5_BASE,
.reg_ofs_cur = AFE_VUL5_CUR,
.reg_ofs_end = AFE_VUL5_END,
.reg_ofs_base_msb = AFE_VUL5_BASE_MSB,
.reg_ofs_cur_msb = AFE_VUL5_CUR_MSB,
.reg_ofs_end_msb = AFE_VUL5_END_MSB,
.fs_reg = AFE_VUL5_CON0,
.fs_shift = VUL5_MODE_SFT,
.fs_maskbit = VUL5_MODE_MASK,
.mono_reg = AFE_VUL5_CON0,
.mono_shift = VUL5_MONO_SFT,
.enable_reg = AFE_DAC_CON0,
.enable_shift = VUL5_ON_SFT,
.hd_reg = AFE_VUL5_CON0,
.hd_shift = VUL5_HD_MODE_SFT,
.hd_align_reg = AFE_VUL5_CON0,
.hd_align_mshift = VUL5_HALIGN_SFT,
.agent_disable_reg = -1,
.agent_disable_shift = -1,
.msb_reg = -1,
.msb_shift = -1,
},
[MT8186_MEMIF_VUL6] = {
.name = "VUL6",
.id = MT8186_MEMIF_VUL6,
.reg_ofs_base = AFE_VUL6_BASE,
.reg_ofs_cur = AFE_VUL6_CUR,
.reg_ofs_end = AFE_VUL6_END,
.reg_ofs_base_msb = AFE_VUL6_BASE_MSB,
.reg_ofs_cur_msb = AFE_VUL6_CUR_MSB,
.reg_ofs_end_msb = AFE_VUL6_END_MSB,
.fs_reg = AFE_VUL6_CON0,
.fs_shift = VUL6_MODE_SFT,
.fs_maskbit = VUL6_MODE_MASK,
.mono_reg = AFE_VUL6_CON0,
.mono_shift = VUL6_MONO_SFT,
.enable_reg = AFE_DAC_CON0,
.enable_shift = VUL6_ON_SFT,
.hd_reg = AFE_VUL6_CON0,
.hd_shift = VUL6_HD_MODE_SFT,
.hd_align_reg = AFE_VUL6_CON0,
.hd_align_mshift = VUL6_HALIGN_SFT,
.agent_disable_reg = -1,
.agent_disable_shift = -1,
.msb_reg = -1,
.msb_shift = -1,
},
};
static const struct mtk_base_irq_data irq_data[MT8186_IRQ_NUM] = {
[MT8186_IRQ_0] = {
.id = MT8186_IRQ_0,
.irq_cnt_reg = AFE_IRQ_MCU_CNT0,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON1,
.irq_fs_shift = IRQ0_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ0_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ0_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ0_MCU_CLR_SFT,
},
[MT8186_IRQ_1] = {
.id = MT8186_IRQ_1,
.irq_cnt_reg = AFE_IRQ_MCU_CNT1,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON1,
.irq_fs_shift = IRQ1_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ1_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ1_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ1_MCU_CLR_SFT,
},
[MT8186_IRQ_2] = {
.id = MT8186_IRQ_2,
.irq_cnt_reg = AFE_IRQ_MCU_CNT2,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON1,
.irq_fs_shift = IRQ2_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ2_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ2_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ2_MCU_CLR_SFT,
},
[MT8186_IRQ_3] = {
.id = MT8186_IRQ_3,
.irq_cnt_reg = AFE_IRQ_MCU_CNT3,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON1,
.irq_fs_shift = IRQ3_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ3_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ3_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ3_MCU_CLR_SFT,
},
[MT8186_IRQ_4] = {
.id = MT8186_IRQ_4,
.irq_cnt_reg = AFE_IRQ_MCU_CNT4,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON1,
.irq_fs_shift = IRQ4_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ4_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ4_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ4_MCU_CLR_SFT,
},
[MT8186_IRQ_5] = {
.id = MT8186_IRQ_5,
.irq_cnt_reg = AFE_IRQ_MCU_CNT5,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON1,
.irq_fs_shift = IRQ5_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ5_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ5_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ5_MCU_CLR_SFT,
},
[MT8186_IRQ_6] = {
.id = MT8186_IRQ_6,
.irq_cnt_reg = AFE_IRQ_MCU_CNT6,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON1,
.irq_fs_shift = IRQ6_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ6_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ6_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ6_MCU_CLR_SFT,
},
[MT8186_IRQ_7] = {
.id = MT8186_IRQ_7,
.irq_cnt_reg = AFE_IRQ_MCU_CNT7,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON1,
.irq_fs_shift = IRQ7_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ7_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ7_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ7_MCU_CLR_SFT,
},
[MT8186_IRQ_8] = {
.id = MT8186_IRQ_8,
.irq_cnt_reg = AFE_IRQ_MCU_CNT8,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON2,
.irq_fs_shift = IRQ8_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ8_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ8_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ8_MCU_CLR_SFT,
},
[MT8186_IRQ_9] = {
.id = MT8186_IRQ_9,
.irq_cnt_reg = AFE_IRQ_MCU_CNT9,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON2,
.irq_fs_shift = IRQ9_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ9_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ9_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ9_MCU_CLR_SFT,
},
[MT8186_IRQ_10] = {
.id = MT8186_IRQ_10,
.irq_cnt_reg = AFE_IRQ_MCU_CNT10,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON2,
.irq_fs_shift = IRQ10_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ10_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ10_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ10_MCU_CLR_SFT,
},
[MT8186_IRQ_11] = {
.id = MT8186_IRQ_11,
.irq_cnt_reg = AFE_IRQ_MCU_CNT11,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON2,
.irq_fs_shift = IRQ11_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ11_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ11_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ11_MCU_CLR_SFT,
},
[MT8186_IRQ_12] = {
.id = MT8186_IRQ_12,
.irq_cnt_reg = AFE_IRQ_MCU_CNT12,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON2,
.irq_fs_shift = IRQ12_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ12_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ12_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ12_MCU_CLR_SFT,
},
[MT8186_IRQ_13] = {
.id = MT8186_IRQ_13,
.irq_cnt_reg = AFE_IRQ_MCU_CNT13,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON2,
.irq_fs_shift = IRQ13_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ13_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ13_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ13_MCU_CLR_SFT,
},
[MT8186_IRQ_14] = {
.id = MT8186_IRQ_14,
.irq_cnt_reg = AFE_IRQ_MCU_CNT14,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON2,
.irq_fs_shift = IRQ14_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ14_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ14_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ14_MCU_CLR_SFT,
},
[MT8186_IRQ_15] = {
.id = MT8186_IRQ_15,
.irq_cnt_reg = AFE_IRQ_MCU_CNT15,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON2,
.irq_fs_shift = IRQ15_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ15_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ15_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ15_MCU_CLR_SFT,
},
[MT8186_IRQ_16] = {
.id = MT8186_IRQ_16,
.irq_cnt_reg = AFE_IRQ_MCU_CNT16,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON3,
.irq_fs_shift = IRQ16_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ16_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ16_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ16_MCU_CLR_SFT,
},
[MT8186_IRQ_17] = {
.id = MT8186_IRQ_17,
.irq_cnt_reg = AFE_IRQ_MCU_CNT17,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON3,
.irq_fs_shift = IRQ17_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ17_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ17_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ17_MCU_CLR_SFT,
},
[MT8186_IRQ_18] = {
.id = MT8186_IRQ_18,
.irq_cnt_reg = AFE_IRQ_MCU_CNT18,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON3,
.irq_fs_shift = IRQ18_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ18_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ18_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ18_MCU_CLR_SFT,
},
[MT8186_IRQ_19] = {
.id = MT8186_IRQ_19,
.irq_cnt_reg = AFE_IRQ_MCU_CNT19,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON3,
.irq_fs_shift = IRQ19_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ19_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ19_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ19_MCU_CLR_SFT,
},
[MT8186_IRQ_20] = {
.id = MT8186_IRQ_20,
.irq_cnt_reg = AFE_IRQ_MCU_CNT20,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON3,
.irq_fs_shift = IRQ20_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ20_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ20_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ20_MCU_CLR_SFT,
},
[MT8186_IRQ_21] = {
.id = MT8186_IRQ_21,
.irq_cnt_reg = AFE_IRQ_MCU_CNT21,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON3,
.irq_fs_shift = IRQ21_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ21_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ21_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ21_MCU_CLR_SFT,
},
[MT8186_IRQ_22] = {
.id = MT8186_IRQ_22,
.irq_cnt_reg = AFE_IRQ_MCU_CNT22,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON3,
.irq_fs_shift = IRQ22_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ22_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ22_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ22_MCU_CLR_SFT,
},
[MT8186_IRQ_23] = {
.id = MT8186_IRQ_23,
.irq_cnt_reg = AFE_IRQ_MCU_CNT23,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON3,
.irq_fs_shift = IRQ23_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ23_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ23_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ23_MCU_CLR_SFT,
},
[MT8186_IRQ_24] = {
.id = MT8186_IRQ_24,
.irq_cnt_reg = AFE_IRQ_MCU_CNT24,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON4,
.irq_fs_shift = IRQ24_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ24_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ24_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ24_MCU_CLR_SFT,
},
[MT8186_IRQ_25] = {
.id = MT8186_IRQ_25,
.irq_cnt_reg = AFE_IRQ_MCU_CNT25,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON4,
.irq_fs_shift = IRQ25_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ25_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ25_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ25_MCU_CLR_SFT,
},
[MT8186_IRQ_26] = {
.id = MT8186_IRQ_26,
.irq_cnt_reg = AFE_IRQ_MCU_CNT26,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ_MCU_CON4,
.irq_fs_shift = IRQ26_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ26_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ26_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ26_MCU_CLR_SFT,
},
};
static const int memif_irq_usage[MT8186_MEMIF_NUM] = {
/* TODO: verify each memif & irq */
[MT8186_MEMIF_DL1] = MT8186_IRQ_0,
[MT8186_MEMIF_DL2] = MT8186_IRQ_1,
[MT8186_MEMIF_DL3] = MT8186_IRQ_2,
[MT8186_MEMIF_DL4] = MT8186_IRQ_3,
[MT8186_MEMIF_DL5] = MT8186_IRQ_4,
[MT8186_MEMIF_DL6] = MT8186_IRQ_5,
[MT8186_MEMIF_DL7] = MT8186_IRQ_6,
[MT8186_MEMIF_DL8] = MT8186_IRQ_7,
[MT8186_MEMIF_DL12] = MT8186_IRQ_9,
[MT8186_MEMIF_VUL12] = MT8186_IRQ_10,
[MT8186_MEMIF_VUL2] = MT8186_IRQ_11,
[MT8186_MEMIF_AWB] = MT8186_IRQ_12,
[MT8186_MEMIF_AWB2] = MT8186_IRQ_13,
[MT8186_MEMIF_VUL3] = MT8186_IRQ_14,
[MT8186_MEMIF_VUL4] = MT8186_IRQ_15,
[MT8186_MEMIF_VUL5] = MT8186_IRQ_16,
[MT8186_MEMIF_VUL6] = MT8186_IRQ_17,
};
static bool mt8186_is_volatile_reg(struct device *dev, unsigned int reg)
{
/* these auto-gen reg has read-only bit, so put it as volatile */
/* volatile reg cannot be cached, so cannot be set when power off */
switch (reg) {
case AUDIO_TOP_CON0: /* reg bit controlled by CCF */
case AUDIO_TOP_CON1: /* reg bit controlled by CCF */
case AUDIO_TOP_CON2:
case AUDIO_TOP_CON3:
case AFE_DAC_CON0:
case AFE_DL1_CUR_MSB:
case AFE_DL1_CUR:
case AFE_DL1_END:
case AFE_DL2_CUR_MSB:
case AFE_DL2_CUR:
case AFE_DL2_END:
case AFE_DL3_CUR_MSB:
case AFE_DL3_CUR:
case AFE_DL3_END:
case AFE_DL4_CUR_MSB:
case AFE_DL4_CUR:
case AFE_DL4_END:
case AFE_DL12_CUR_MSB:
case AFE_DL12_CUR:
case AFE_DL12_END:
case AFE_ADDA_SRC_DEBUG_MON0:
case AFE_ADDA_SRC_DEBUG_MON1:
case AFE_ADDA_UL_SRC_MON0:
case AFE_ADDA_UL_SRC_MON1:
case AFE_SECURE_CON0:
case AFE_SRAM_BOUND:
case AFE_SECURE_CON1:
case AFE_VUL_CUR_MSB:
case AFE_VUL_CUR:
case AFE_VUL_END:
case AFE_SIDETONE_MON:
case AFE_SIDETONE_CON0:
case AFE_SIDETONE_COEFF:
case AFE_VUL2_CUR_MSB:
case AFE_VUL2_CUR:
case AFE_VUL2_END:
case AFE_VUL3_CUR_MSB:
case AFE_VUL3_CUR:
case AFE_VUL3_END:
case AFE_I2S_MON:
case AFE_DAC_MON:
case AFE_IRQ0_MCU_CNT_MON:
case AFE_IRQ6_MCU_CNT_MON:
case AFE_VUL4_CUR_MSB:
case AFE_VUL4_CUR:
case AFE_VUL4_END:
case AFE_VUL12_CUR_MSB:
case AFE_VUL12_CUR:
case AFE_VUL12_END:
case AFE_IRQ3_MCU_CNT_MON:
case AFE_IRQ4_MCU_CNT_MON:
case AFE_IRQ_MCU_STATUS:
case AFE_IRQ_MCU_CLR:
case AFE_IRQ_MCU_MON2:
case AFE_IRQ1_MCU_CNT_MON:
case AFE_IRQ2_MCU_CNT_MON:
case AFE_IRQ5_MCU_CNT_MON:
case AFE_IRQ7_MCU_CNT_MON:
case AFE_IRQ_MCU_MISS_CLR:
case AFE_GAIN1_CUR:
case AFE_GAIN2_CUR:
case AFE_SRAM_DELSEL_CON1:
case PCM_INTF_CON2:
case FPGA_CFG0:
case FPGA_CFG1:
case FPGA_CFG2:
case FPGA_CFG3:
case AUDIO_TOP_DBG_MON0:
case AUDIO_TOP_DBG_MON1:
case AFE_IRQ8_MCU_CNT_MON:
case AFE_IRQ11_MCU_CNT_MON:
case AFE_IRQ12_MCU_CNT_MON:
case AFE_IRQ9_MCU_CNT_MON:
case AFE_IRQ10_MCU_CNT_MON:
case AFE_IRQ13_MCU_CNT_MON:
case AFE_IRQ14_MCU_CNT_MON:
case AFE_IRQ15_MCU_CNT_MON:
case AFE_IRQ16_MCU_CNT_MON:
case AFE_IRQ17_MCU_CNT_MON:
case AFE_IRQ18_MCU_CNT_MON:
case AFE_IRQ19_MCU_CNT_MON:
case AFE_IRQ20_MCU_CNT_MON:
case AFE_IRQ21_MCU_CNT_MON:
case AFE_IRQ22_MCU_CNT_MON:
case AFE_IRQ23_MCU_CNT_MON:
case AFE_IRQ24_MCU_CNT_MON:
case AFE_IRQ25_MCU_CNT_MON:
case AFE_IRQ26_MCU_CNT_MON:
case AFE_IRQ31_MCU_CNT_MON:
case AFE_CBIP_MON0:
case AFE_CBIP_SLV_MUX_MON0:
case AFE_CBIP_SLV_DECODER_MON0:
case AFE_ADDA6_MTKAIF_MON0:
case AFE_ADDA6_MTKAIF_MON1:
case AFE_AWB_CUR_MSB:
case AFE_AWB_CUR:
case AFE_AWB_END:
case AFE_AWB2_CUR_MSB:
case AFE_AWB2_CUR:
case AFE_AWB2_END:
case AFE_DAI_CUR_MSB:
case AFE_DAI_CUR:
case AFE_DAI_END:
case AFE_DAI2_CUR_MSB:
case AFE_DAI2_CUR:
case AFE_DAI2_END:
case AFE_ADDA6_SRC_DEBUG_MON0:
case AFE_ADD6A_UL_SRC_MON0:
case AFE_ADDA6_UL_SRC_MON1:
case AFE_MOD_DAI_CUR_MSB:
case AFE_MOD_DAI_CUR:
case AFE_MOD_DAI_END:
case AFE_AWB_RCH_MON:
case AFE_AWB_LCH_MON:
case AFE_VUL_RCH_MON:
case AFE_VUL_LCH_MON:
case AFE_VUL12_RCH_MON:
case AFE_VUL12_LCH_MON:
case AFE_VUL2_RCH_MON:
case AFE_VUL2_LCH_MON:
case AFE_DAI_DATA_MON:
case AFE_MOD_DAI_DATA_MON:
case AFE_DAI2_DATA_MON:
case AFE_AWB2_RCH_MON:
case AFE_AWB2_LCH_MON:
case AFE_VUL3_RCH_MON:
case AFE_VUL3_LCH_MON:
case AFE_VUL4_RCH_MON:
case AFE_VUL4_LCH_MON:
case AFE_VUL5_RCH_MON:
case AFE_VUL5_LCH_MON:
case AFE_VUL6_RCH_MON:
case AFE_VUL6_LCH_MON:
case AFE_DL1_RCH_MON:
case AFE_DL1_LCH_MON:
case AFE_DL2_RCH_MON:
case AFE_DL2_LCH_MON:
case AFE_DL12_RCH1_MON:
case AFE_DL12_LCH1_MON:
case AFE_DL12_RCH2_MON:
case AFE_DL12_LCH2_MON:
case AFE_DL3_RCH_MON:
case AFE_DL3_LCH_MON:
case AFE_DL4_RCH_MON:
case AFE_DL4_LCH_MON:
case AFE_DL5_RCH_MON:
case AFE_DL5_LCH_MON:
case AFE_DL6_RCH_MON:
case AFE_DL6_LCH_MON:
case AFE_DL7_RCH_MON:
case AFE_DL7_LCH_MON:
case AFE_DL8_RCH_MON:
case AFE_DL8_LCH_MON:
case AFE_VUL5_CUR_MSB:
case AFE_VUL5_CUR:
case AFE_VUL5_END:
case AFE_VUL6_CUR_MSB:
case AFE_VUL6_CUR:
case AFE_VUL6_END:
case AFE_ADDA_DL_SDM_FIFO_MON:
case AFE_ADDA_DL_SRC_LCH_MON:
case AFE_ADDA_DL_SRC_RCH_MON:
case AFE_ADDA_DL_SDM_OUT_MON:
case AFE_CONNSYS_I2S_MON:
case AFE_ASRC_2CH_CON0:
case AFE_ASRC_2CH_CON2:
case AFE_ASRC_2CH_CON3:
case AFE_ASRC_2CH_CON4:
case AFE_ASRC_2CH_CON5:
case AFE_ASRC_2CH_CON7:
case AFE_ASRC_2CH_CON8:
case AFE_ASRC_2CH_CON12:
case AFE_ASRC_2CH_CON13:
case AFE_ADDA_MTKAIF_MON0:
case AFE_ADDA_MTKAIF_MON1:
case AFE_AUD_PAD_TOP:
case AFE_DL_NLE_R_MON0:
case AFE_DL_NLE_R_MON1:
case AFE_DL_NLE_R_MON2:
case AFE_DL_NLE_L_MON0:
case AFE_DL_NLE_L_MON1:
case AFE_DL_NLE_L_MON2:
case AFE_GENERAL1_ASRC_2CH_CON0:
case AFE_GENERAL1_ASRC_2CH_CON2:
case AFE_GENERAL1_ASRC_2CH_CON3:
case AFE_GENERAL1_ASRC_2CH_CON4:
case AFE_GENERAL1_ASRC_2CH_CON5:
case AFE_GENERAL1_ASRC_2CH_CON7:
case AFE_GENERAL1_ASRC_2CH_CON8:
case AFE_GENERAL1_ASRC_2CH_CON12:
case AFE_GENERAL1_ASRC_2CH_CON13:
case AFE_GENERAL2_ASRC_2CH_CON0:
case AFE_GENERAL2_ASRC_2CH_CON2:
case AFE_GENERAL2_ASRC_2CH_CON3:
case AFE_GENERAL2_ASRC_2CH_CON4:
case AFE_GENERAL2_ASRC_2CH_CON5:
case AFE_GENERAL2_ASRC_2CH_CON7:
case AFE_GENERAL2_ASRC_2CH_CON8:
case AFE_GENERAL2_ASRC_2CH_CON12:
case AFE_GENERAL2_ASRC_2CH_CON13:
case AFE_DL5_CUR_MSB:
case AFE_DL5_CUR:
case AFE_DL5_END:
case AFE_DL6_CUR_MSB:
case AFE_DL6_CUR:
case AFE_DL6_END:
case AFE_DL7_CUR_MSB:
case AFE_DL7_CUR:
case AFE_DL7_END:
case AFE_DL8_CUR_MSB:
case AFE_DL8_CUR:
case AFE_DL8_END:
case AFE_PROT_SIDEBAND_MON:
case AFE_DOMAIN_SIDEBAND0_MON:
case AFE_DOMAIN_SIDEBAND1_MON:
case AFE_DOMAIN_SIDEBAND2_MON:
case AFE_DOMAIN_SIDEBAND3_MON:
case AFE_APLL1_TUNER_CFG: /* [20:31] is monitor */
case AFE_APLL2_TUNER_CFG: /* [20:31] is monitor */
return true;
default:
return false;
};
}
static const struct regmap_config mt8186_afe_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.volatile_reg = mt8186_is_volatile_reg,
.max_register = AFE_MAX_REGISTER,
.num_reg_defaults_raw = AFE_MAX_REGISTER,
.cache_type = REGCACHE_FLAT,
};
static irqreturn_t mt8186_afe_irq_handler(int irq_id, void *dev)
{
struct mtk_base_afe *afe = dev;
struct mtk_base_afe_irq *irq;
unsigned int status;
unsigned int status_mcu;
unsigned int mcu_en;
int ret;
int i;
/* get irq that is sent to MCU */
ret = regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &mcu_en);
if (ret) {
dev_err(afe->dev, "%s, get irq direction fail, ret %d", __func__, ret);
return ret;
}
ret = regmap_read(afe->regmap, AFE_IRQ_MCU_STATUS, &status);
/* only care IRQ which is sent to MCU */
status_mcu = status & mcu_en & AFE_IRQ_STATUS_BITS;
if (ret || status_mcu == 0) {
dev_err(afe->dev, "%s(), irq status err, ret %d, status 0x%x, mcu_en 0x%x\n",
__func__, ret, status, mcu_en);
goto err_irq;
}
for (i = 0; i < MT8186_MEMIF_NUM; i++) {
struct mtk_base_afe_memif *memif = &afe->memif[i];
if (!memif->substream)
continue;
if (memif->irq_usage < 0)
continue;
irq = &afe->irqs[memif->irq_usage];
if (status_mcu & (1 << irq->irq_data->irq_en_shift))
snd_pcm_period_elapsed(memif->substream);
}
err_irq:
/* clear irq */
regmap_write(afe->regmap, AFE_IRQ_MCU_CLR, status_mcu);
return IRQ_HANDLED;
}
static int mt8186_afe_runtime_suspend(struct device *dev)
{
struct mtk_base_afe *afe = dev_get_drvdata(dev);
struct mt8186_afe_private *afe_priv = afe->platform_priv;
unsigned int value = 0;
int ret;
if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
goto skip_regmap;
/* disable AFE */
regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x0);
ret = regmap_read_poll_timeout(afe->regmap,
AFE_DAC_MON,
value,
(value & AFE_ON_RETM_MASK_SFT) == 0,
20,
1 * 1000 * 1000);
if (ret) {
dev_err(afe->dev, "%s(), ret %d\n", __func__, ret);
return ret;
}
/* make sure all irq status are cleared */
regmap_write(afe->regmap, AFE_IRQ_MCU_CLR, 0xffffffff);
regmap_write(afe->regmap, AFE_IRQ_MCU_CLR, 0xffffffff);
/* reset sgen */
regmap_write(afe->regmap, AFE_SINEGEN_CON0, 0x0);
regmap_update_bits(afe->regmap, AFE_SINEGEN_CON2,
INNER_LOOP_BACK_MODE_MASK_SFT,
0x3f << INNER_LOOP_BACK_MODE_SFT);
/* cache only */
regcache_cache_only(afe->regmap, true);
regcache_mark_dirty(afe->regmap);
skip_regmap:
mt8186_afe_disable_cgs(afe);
mt8186_afe_disable_clock(afe);
return 0;
}
static int mt8186_afe_runtime_resume(struct device *dev)
{
struct mtk_base_afe *afe = dev_get_drvdata(dev);
struct mt8186_afe_private *afe_priv = afe->platform_priv;
int ret;
ret = mt8186_afe_enable_clock(afe);
if (ret)
return ret;
ret = mt8186_afe_enable_cgs(afe);
if (ret)
return ret;
if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
goto skip_regmap;
regcache_cache_only(afe->regmap, false);
regcache_sync(afe->regmap);
/* enable audio sys DCM for power saving */
regmap_update_bits(afe_priv->infracfg, PERI_BUS_DCM_CTRL, BIT(29), BIT(29));
regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, BIT(29), BIT(29));
/* force cpu use 8_24 format when writing 32bit data */
regmap_update_bits(afe->regmap, AFE_MEMIF_CON0, CPU_HD_ALIGN_MASK_SFT, 0);
/* set all output port to 24bit */
regmap_write(afe->regmap, AFE_CONN_24BIT, 0xffffffff);
regmap_write(afe->regmap, AFE_CONN_24BIT_1, 0xffffffff);
/* enable AFE */
regmap_update_bits(afe->regmap, AFE_DAC_CON0, AUDIO_AFE_ON_MASK_SFT, BIT(0));
skip_regmap:
return 0;
}
static int mt8186_afe_component_probe(struct snd_soc_component *component)
{
mtk_afe_add_sub_dai_control(component);
mt8186_add_misc_control(component);
return 0;
}
static const struct snd_soc_component_driver mt8186_afe_component = {
.name = AFE_PCM_NAME,
.pcm_construct = mtk_afe_pcm_new,
.pointer = mtk_afe_pcm_pointer,
.probe = mt8186_afe_component_probe,
};
static int mt8186_dai_memif_register(struct mtk_base_afe *afe)
{
struct mtk_base_afe_dai *dai;
dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
if (!dai)
return -ENOMEM;
list_add(&dai->list, &afe->sub_dais);
dai->dai_drivers = mt8186_memif_dai_driver;
dai->num_dai_drivers = ARRAY_SIZE(mt8186_memif_dai_driver);
dai->controls = mt8186_pcm_kcontrols;
dai->num_controls = ARRAY_SIZE(mt8186_pcm_kcontrols);
dai->dapm_widgets = mt8186_memif_widgets;
dai->num_dapm_widgets = ARRAY_SIZE(mt8186_memif_widgets);
dai->dapm_routes = mt8186_memif_routes;
dai->num_dapm_routes = ARRAY_SIZE(mt8186_memif_routes);
return 0;
}
typedef int (*dai_register_cb)(struct mtk_base_afe *);
static const dai_register_cb dai_register_cbs[] = {
mt8186_dai_adda_register,
mt8186_dai_i2s_register,
mt8186_dai_tdm_register,
mt8186_dai_hw_gain_register,
mt8186_dai_src_register,
mt8186_dai_pcm_register,
mt8186_dai_hostless_register,
mt8186_dai_memif_register,
};
static int mt8186_afe_pcm_dev_probe(struct platform_device *pdev)
{
struct mtk_base_afe *afe;
struct mt8186_afe_private *afe_priv;
struct reset_control *rstc;
struct device *dev = &pdev->dev;
int i, ret, irq_id;
ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(34));
if (ret)
return ret;
afe = devm_kzalloc(dev, sizeof(*afe), GFP_KERNEL);
if (!afe)
return -ENOMEM;
platform_set_drvdata(pdev, afe);
afe->platform_priv = devm_kzalloc(dev, sizeof(*afe_priv), GFP_KERNEL);
if (!afe->platform_priv)
return -ENOMEM;
afe_priv = afe->platform_priv;
afe->dev = &pdev->dev;
afe->base_addr = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(afe->base_addr))
return PTR_ERR(afe->base_addr);
/* init audio related clock */
ret = mt8186_init_clock(afe);
if (ret) {
dev_err(dev, "init clock error, ret %d\n", ret);
return ret;
}
/* init memif */
afe->memif_32bit_supported = 0;
afe->memif_size = MT8186_MEMIF_NUM;
afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif), GFP_KERNEL);
if (!afe->memif)
return -ENOMEM;
for (i = 0; i < afe->memif_size; i++) {
afe->memif[i].data = &memif_data[i];
afe->memif[i].irq_usage = memif_irq_usage[i];
afe->memif[i].const_irq = 1;
}
mutex_init(&afe->irq_alloc_lock); /* needed when dynamic irq */
/* init irq */
afe->irqs_size = MT8186_IRQ_NUM;
afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
GFP_KERNEL);
if (!afe->irqs)
return -ENOMEM;
for (i = 0; i < afe->irqs_size; i++)
afe->irqs[i].irq_data = &irq_data[i];
/* request irq */
irq_id = platform_get_irq(pdev, 0);
if (irq_id <= 0)
return dev_err_probe(dev, irq_id < 0 ? irq_id : -ENXIO,
"no irq found");
ret = devm_request_irq(dev, irq_id, mt8186_afe_irq_handler,
IRQF_TRIGGER_NONE,
"Afe_ISR_Handle", (void *)afe);
if (ret)
return dev_err_probe(dev, ret, "could not request_irq for Afe_ISR_Handle\n");
ret = enable_irq_wake(irq_id);
if (ret < 0)
return dev_err_probe(dev, ret, "enable_irq_wake %d\n", irq_id);
/* init sub_dais */
INIT_LIST_HEAD(&afe->sub_dais);
for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) {
ret = dai_register_cbs[i](afe);
if (ret)
return dev_err_probe(dev, ret, "dai register i %d fail\n", i);
}
/* init dai_driver and component_driver */
ret = mtk_afe_combine_sub_dai(afe);
if (ret)
return dev_err_probe(dev, ret, "mtk_afe_combine_sub_dai fail\n");
/* reset controller to reset audio regs before regmap cache */
rstc = devm_reset_control_get_exclusive(dev, "audiosys");
if (IS_ERR(rstc))
return dev_err_probe(dev, PTR_ERR(rstc), "could not get audiosys reset\n");
ret = reset_control_reset(rstc);
if (ret)
return dev_err_probe(dev, ret, "failed to trigger audio reset\n");
/* enable clock for regcache get default value from hw */
afe_priv->pm_runtime_bypass_reg_ctl = true;
ret = devm_pm_runtime_enable(dev);
if (ret)
return ret;
ret = pm_runtime_resume_and_get(dev);
if (ret)
return dev_err_probe(dev, ret, "failed to resume device\n");
afe->regmap = devm_regmap_init_mmio(dev, afe->base_addr,
&mt8186_afe_regmap_config);
if (IS_ERR(afe->regmap)) {
ret = PTR_ERR(afe->regmap);
goto err_pm_disable;
}
/* others */
afe->mtk_afe_hardware = &mt8186_afe_hardware;
afe->memif_fs = mt8186_memif_fs;
afe->irq_fs = mt8186_irq_fs;
afe->get_dai_fs = mt8186_get_dai_fs;
afe->get_memif_pbuf_size = mt8186_get_memif_pbuf_size;
afe->runtime_resume = mt8186_afe_runtime_resume;
afe->runtime_suspend = mt8186_afe_runtime_suspend;
/* register platform */
dev_dbg(dev, "%s(), devm_snd_soc_register_component\n", __func__);
ret = devm_snd_soc_register_component(dev,
&mt8186_afe_component,
afe->dai_drivers,
afe->num_dai_drivers);
if (ret) {
dev_err(dev, "err_dai_component\n");
goto err_pm_disable;
}
ret = pm_runtime_put_sync(dev);
if (ret) {
pm_runtime_get_noresume(dev);
dev_err(dev, "failed to suspend device: %d\n", ret);
goto err_pm_disable;
}
afe_priv->pm_runtime_bypass_reg_ctl = false;
regcache_cache_only(afe->regmap, true);
regcache_mark_dirty(afe->regmap);
return 0;
err_pm_disable:
pm_runtime_put_noidle(dev);
pm_runtime_set_suspended(dev);
return ret;
}
static const struct of_device_id mt8186_afe_pcm_dt_match[] = {
{ .compatible = "mediatek,mt8186-sound", },
{},
};
MODULE_DEVICE_TABLE(of, mt8186_afe_pcm_dt_match);
static const struct dev_pm_ops mt8186_afe_pm_ops = {
SET_RUNTIME_PM_OPS(mt8186_afe_runtime_suspend,
mt8186_afe_runtime_resume, NULL)
};
static struct platform_driver mt8186_afe_pcm_driver = {
.driver = {
.name = "mt8186-audio",
.of_match_table = mt8186_afe_pcm_dt_match,
.pm = &mt8186_afe_pm_ops,
},
.probe = mt8186_afe_pcm_dev_probe,
};
module_platform_driver(mt8186_afe_pcm_driver);
MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 8186");
MODULE_AUTHOR("Jiaxin Yu <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/mediatek/mt8186/mt8186-afe-pcm.c |
// SPDX-License-Identifier: GPL-2.0
//
// MediaTek ALSA SoC Audio Misc Control
//
// Copyright (c) 2022 MediaTek Inc.
// Author: Jiaxin Yu <[email protected]>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/io.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include "../common/mtk-afe-fe-dai.h"
#include "../common/mtk-afe-platform-driver.h"
#include "mt8186-afe-common.h"
static const char * const mt8186_sgen_mode_str[] = {
"I0I1", "I2", "I3I4", "I5I6",
"I7I8", "I9I22", "I10I11", "I12I13",
"I14I21", "I15I16", "I17I18", "I19I20",
"I23I24", "I25I26", "I27I28", "I33",
"I34I35", "I36I37", "I38I39", "I40I41",
"I42I43", "I44I45", "I46I47", "I48I49",
"I56I57", "I58I59", "I60I61", "I62I63",
"O0O1", "O2", "O3O4", "O5O6",
"O7O8", "O9O10", "O11", "O12",
"O13O14", "O15O16", "O17O18", "O19O20",
"O21O22", "O23O24", "O25", "O28O29",
"O34", "O35", "O32O33", "O36O37",
"O38O39", "O30O31", "O40O41", "O42O43",
"O44O45", "O46O47", "O48O49", "O50O51",
"O58O59", "O60O61", "O62O63", "O64O65",
"O66O67", "O68O69", "O26O27", "OFF",
};
static const int mt8186_sgen_mode_idx[] = {
0, 2, 4, 6,
8, 22, 10, 12,
14, -1, 18, 20,
24, 26, 28, 33,
34, 36, 38, 40,
42, 44, 46, 48,
56, 58, 60, 62,
128, 130, 132, 134,
135, 138, 139, 140,
142, 144, 166, 148,
150, 152, 153, 156,
162, 163, 160, 164,
166, -1, 168, 170,
172, 174, 176, 178,
186, 188, 190, 192,
194, 196, -1, -1,
};
static const char * const mt8186_sgen_rate_str[] = {
"8K", "11K", "12K", "16K",
"22K", "24K", "32K", "44K",
"48K", "88k", "96k", "176k",
"192k"
};
static const int mt8186_sgen_rate_idx[] = {
0, 1, 2, 4,
5, 6, 8, 9,
10, 11, 12, 13,
14
};
/* this order must match reg bit amp_div_ch1/2 */
static const char * const mt8186_sgen_amp_str[] = {
"1/128", "1/64", "1/32", "1/16", "1/8", "1/4", "1/2", "1" };
static int mt8186_sgen_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8186_afe_private *afe_priv = afe->platform_priv;
ucontrol->value.integer.value[0] = afe_priv->sgen_mode;
return 0;
}
static int mt8186_sgen_set(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8186_afe_private *afe_priv = afe->platform_priv;
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
int mode;
int mode_idx;
if (ucontrol->value.enumerated.item[0] >= e->items)
return -EINVAL;
mode = ucontrol->value.integer.value[0];
mode_idx = mt8186_sgen_mode_idx[mode];
dev_dbg(afe->dev, "%s(), mode %d, mode_idx %d\n",
__func__, mode, mode_idx);
if (mode == afe_priv->sgen_mode)
return 0;
if (mode_idx >= 0) {
regmap_update_bits(afe->regmap, AFE_SINEGEN_CON2,
INNER_LOOP_BACK_MODE_MASK_SFT,
mode_idx << INNER_LOOP_BACK_MODE_SFT);
regmap_update_bits(afe->regmap, AFE_SINEGEN_CON0,
DAC_EN_MASK_SFT, BIT(DAC_EN_SFT));
} else {
/* disable sgen */
regmap_update_bits(afe->regmap, AFE_SINEGEN_CON0,
DAC_EN_MASK_SFT, 0);
regmap_update_bits(afe->regmap, AFE_SINEGEN_CON2,
INNER_LOOP_BACK_MODE_MASK_SFT,
0x3f << INNER_LOOP_BACK_MODE_SFT);
}
afe_priv->sgen_mode = mode;
return 1;
}
static int mt8186_sgen_rate_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8186_afe_private *afe_priv = afe->platform_priv;
ucontrol->value.integer.value[0] = afe_priv->sgen_rate;
return 0;
}
static int mt8186_sgen_rate_set(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8186_afe_private *afe_priv = afe->platform_priv;
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
int rate;
if (ucontrol->value.enumerated.item[0] >= e->items)
return -EINVAL;
rate = ucontrol->value.integer.value[0];
dev_dbg(afe->dev, "%s(), rate %d\n", __func__, rate);
if (rate == afe_priv->sgen_rate)
return 0;
regmap_update_bits(afe->regmap, AFE_SINEGEN_CON0,
SINE_MODE_CH1_MASK_SFT,
mt8186_sgen_rate_idx[rate] << SINE_MODE_CH1_SFT);
regmap_update_bits(afe->regmap, AFE_SINEGEN_CON0,
SINE_MODE_CH2_MASK_SFT,
mt8186_sgen_rate_idx[rate] << SINE_MODE_CH2_SFT);
afe_priv->sgen_rate = rate;
return 1;
}
static int mt8186_sgen_amplitude_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8186_afe_private *afe_priv = afe->platform_priv;
ucontrol->value.integer.value[0] = afe_priv->sgen_amplitude;
return 0;
}
static int mt8186_sgen_amplitude_set(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8186_afe_private *afe_priv = afe->platform_priv;
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
int amplitude;
if (ucontrol->value.enumerated.item[0] >= e->items)
return -EINVAL;
amplitude = ucontrol->value.integer.value[0];
if (amplitude > AMP_DIV_CH1_MASK) {
dev_err(afe->dev, "%s(), amplitude %d invalid\n",
__func__, amplitude);
return -EINVAL;
}
dev_dbg(afe->dev, "%s(), amplitude %d\n", __func__, amplitude);
if (amplitude == afe_priv->sgen_amplitude)
return 0;
regmap_update_bits(afe->regmap, AFE_SINEGEN_CON0,
AMP_DIV_CH1_MASK_SFT,
amplitude << AMP_DIV_CH1_SFT);
regmap_update_bits(afe->regmap, AFE_SINEGEN_CON0,
AMP_DIV_CH2_MASK_SFT,
amplitude << AMP_DIV_CH2_SFT);
afe_priv->sgen_amplitude = amplitude;
return 1;
}
static const struct soc_enum mt8186_afe_sgen_enum[] = {
SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt8186_sgen_mode_str),
mt8186_sgen_mode_str),
SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt8186_sgen_rate_str),
mt8186_sgen_rate_str),
SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt8186_sgen_amp_str),
mt8186_sgen_amp_str),
};
static const struct snd_kcontrol_new mt8186_afe_sgen_controls[] = {
SOC_ENUM_EXT("Audio_SineGen_Switch", mt8186_afe_sgen_enum[0],
mt8186_sgen_get, mt8186_sgen_set),
SOC_ENUM_EXT("Audio_SineGen_SampleRate", mt8186_afe_sgen_enum[1],
mt8186_sgen_rate_get, mt8186_sgen_rate_set),
SOC_ENUM_EXT("Audio_SineGen_Amplitude", mt8186_afe_sgen_enum[2],
mt8186_sgen_amplitude_get, mt8186_sgen_amplitude_set),
SOC_SINGLE("Audio_SineGen_Mute_Ch1", AFE_SINEGEN_CON0,
MUTE_SW_CH1_MASK_SFT, MUTE_SW_CH1_MASK, 0),
SOC_SINGLE("Audio_SineGen_Mute_Ch2", AFE_SINEGEN_CON0,
MUTE_SW_CH2_MASK_SFT, MUTE_SW_CH2_MASK, 0),
SOC_SINGLE("Audio_SineGen_Freq_Div_Ch1", AFE_SINEGEN_CON0,
FREQ_DIV_CH1_SFT, FREQ_DIV_CH1_MASK, 0),
SOC_SINGLE("Audio_SineGen_Freq_Div_Ch2", AFE_SINEGEN_CON0,
FREQ_DIV_CH2_SFT, FREQ_DIV_CH2_MASK, 0),
};
int mt8186_add_misc_control(struct snd_soc_component *component)
{
snd_soc_add_component_controls(component,
mt8186_afe_sgen_controls,
ARRAY_SIZE(mt8186_afe_sgen_controls));
return 0;
}
| linux-master | sound/soc/mediatek/mt8186/mt8186-misc-control.c |
// SPDX-License-Identifier: GPL-2.0
//
// MediaTek ALSA SoC Audio DAI TDM Control
//
// Copyright (c) 2022 MediaTek Inc.
// Author: Jiaxin Yu <[email protected]>
#include <linux/regmap.h>
#include <sound/pcm_params.h>
#include "mt8186-afe-clk.h"
#include "mt8186-afe-common.h"
#include "mt8186-afe-gpio.h"
#include "mt8186-interconnection.h"
#define TDM_HD_EN_W_NAME "TDM_HD_EN"
#define TDM_MCLK_EN_W_NAME "TDM_MCLK_EN"
#define MTK_AFE_TDM_KCONTROL_NAME "TDM_HD_Mux"
struct mtk_afe_tdm_priv {
unsigned int id;
unsigned int rate; /* for determine which apll to use */
unsigned int bck_invert;
unsigned int lck_invert;
unsigned int lrck_width;
unsigned int mclk_id;
unsigned int mclk_multiple; /* according to sample rate */
unsigned int mclk_rate;
unsigned int mclk_apll;
unsigned int tdm_mode;
unsigned int data_mode;
unsigned int slave_mode;
unsigned int low_jitter_en;
};
enum {
TDM_IN_I2S = 0,
TDM_IN_LJ = 1,
TDM_IN_RJ = 2,
TDM_IN_DSP_A = 4,
TDM_IN_DSP_B = 5,
};
enum {
TDM_DATA_ONE_PIN = 0,
TDM_DATA_MULTI_PIN,
};
enum {
TDM_BCK_NON_INV = 0,
TDM_BCK_INV = 1,
};
enum {
TDM_LCK_NON_INV = 0,
TDM_LCK_INV = 1,
};
static unsigned int get_tdm_lrck_width(snd_pcm_format_t format,
unsigned int mode)
{
if (mode == TDM_IN_DSP_A || mode == TDM_IN_DSP_B)
return 0;
return snd_pcm_format_physical_width(format) - 1;
}
static unsigned int get_tdm_ch_fixup(unsigned int channels)
{
if (channels > 4)
return 8;
else if (channels > 2)
return 4;
return 2;
}
static unsigned int get_tdm_ch_per_sdata(unsigned int mode,
unsigned int channels)
{
if (mode == TDM_IN_DSP_A || mode == TDM_IN_DSP_B)
return get_tdm_ch_fixup(channels);
return 2;
}
enum {
SUPPLY_SEQ_APLL,
SUPPLY_SEQ_TDM_MCK_EN,
SUPPLY_SEQ_TDM_HD_EN,
SUPPLY_SEQ_TDM_EN,
};
static int get_tdm_id_by_name(const char *name)
{
return MT8186_DAI_TDM_IN;
}
static int mtk_tdm_en_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8186_afe_private *afe_priv = afe->platform_priv;
int dai_id = get_tdm_id_by_name(w->name);
struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[dai_id];
dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x\n",
__func__, w->name, event);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
mt8186_afe_gpio_request(afe->dev, true, tdm_priv->id, 0);
break;
case SND_SOC_DAPM_POST_PMD:
mt8186_afe_gpio_request(afe->dev, false, tdm_priv->id, 0);
break;
default:
break;
}
return 0;
}
static int mtk_tdm_mck_en_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8186_afe_private *afe_priv = afe->platform_priv;
int dai_id = get_tdm_id_by_name(w->name);
struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[dai_id];
dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x, dai_id %d\n",
__func__, w->name, event, dai_id);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
mt8186_mck_enable(afe, tdm_priv->mclk_id, tdm_priv->mclk_rate);
break;
case SND_SOC_DAPM_POST_PMD:
tdm_priv->mclk_rate = 0;
mt8186_mck_disable(afe, tdm_priv->mclk_id);
break;
default:
break;
}
return 0;
}
/* dai component */
/* tdm virtual mux to output widget */
static const char * const tdm_mux_map[] = {
"Normal", "Dummy_Widget",
};
static int tdm_mux_map_value[] = {
0, 1,
};
static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(tdm_mux_map_enum,
SND_SOC_NOPM,
0,
1,
tdm_mux_map,
tdm_mux_map_value);
static const struct snd_kcontrol_new tdm_in_mux_control =
SOC_DAPM_ENUM("TDM In Select", tdm_mux_map_enum);
static const struct snd_soc_dapm_widget mtk_dai_tdm_widgets[] = {
SND_SOC_DAPM_CLOCK_SUPPLY("aud_tdm_clk"),
SND_SOC_DAPM_SUPPLY_S("TDM_EN", SUPPLY_SEQ_TDM_EN,
ETDM_IN1_CON0, ETDM_IN1_CON0_REG_ETDM_IN_EN_SFT,
0, mtk_tdm_en_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
/* tdm hd en */
SND_SOC_DAPM_SUPPLY_S(TDM_HD_EN_W_NAME, SUPPLY_SEQ_TDM_HD_EN,
ETDM_IN1_CON2, ETDM_IN1_CON2_REG_CLOCK_SOURCE_SEL_SFT,
0, NULL,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S(TDM_MCLK_EN_W_NAME, SUPPLY_SEQ_TDM_MCK_EN,
SND_SOC_NOPM, 0, 0,
mtk_tdm_mck_en_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_INPUT("TDM_DUMMY_IN"),
SND_SOC_DAPM_MUX("TDM_In_Mux",
SND_SOC_NOPM, 0, 0, &tdm_in_mux_control),
};
static int mtk_afe_tdm_mclk_connect(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_dapm_widget *w = sink;
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8186_afe_private *afe_priv = afe->platform_priv;
int dai_id = get_tdm_id_by_name(w->name);
struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[dai_id];
return (tdm_priv->mclk_rate > 0) ? 1 : 0;
}
static int mtk_afe_tdm_mclk_apll_connect(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_dapm_widget *w = sink;
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8186_afe_private *afe_priv = afe->platform_priv;
int dai_id = get_tdm_id_by_name(w->name);
struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[dai_id];
int cur_apll;
/* which apll */
cur_apll = mt8186_get_apll_by_name(afe, source->name);
return (tdm_priv->mclk_apll == cur_apll) ? 1 : 0;
}
static int mtk_afe_tdm_hd_connect(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_dapm_widget *w = sink;
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8186_afe_private *afe_priv = afe->platform_priv;
int dai_id = get_tdm_id_by_name(w->name);
struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[dai_id];
return tdm_priv->low_jitter_en;
}
static int mtk_afe_tdm_apll_connect(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_dapm_widget *w = sink;
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8186_afe_private *afe_priv = afe->platform_priv;
int dai_id = get_tdm_id_by_name(w->name);
struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[dai_id];
int cur_apll;
int tdm_need_apll;
/* which apll */
cur_apll = mt8186_get_apll_by_name(afe, source->name);
/* choose APLL from tdm rate */
tdm_need_apll = mt8186_get_apll_by_rate(afe, tdm_priv->rate);
return (tdm_need_apll == cur_apll) ? 1 : 0;
}
/* low jitter control */
static const char * const mt8186_tdm_hd_str[] = {
"Normal", "Low_Jitter"
};
static const struct soc_enum mt8186_tdm_enum[] = {
SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt8186_tdm_hd_str),
mt8186_tdm_hd_str),
};
static int mt8186_tdm_hd_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8186_afe_private *afe_priv = afe->platform_priv;
int dai_id = get_tdm_id_by_name(kcontrol->id.name);
struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[dai_id];
ucontrol->value.integer.value[0] = tdm_priv->low_jitter_en;
return 0;
}
static int mt8186_tdm_hd_set(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8186_afe_private *afe_priv = afe->platform_priv;
int dai_id = get_tdm_id_by_name(kcontrol->id.name);
struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[dai_id];
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
int hd_en;
if (ucontrol->value.enumerated.item[0] >= e->items)
return -EINVAL;
hd_en = ucontrol->value.integer.value[0];
dev_dbg(afe->dev, "%s(), kcontrol name %s, hd_en %d\n",
__func__, kcontrol->id.name, hd_en);
if (tdm_priv->low_jitter_en == hd_en)
return 0;
tdm_priv->low_jitter_en = hd_en;
return 1;
}
static const struct snd_kcontrol_new mtk_dai_tdm_controls[] = {
SOC_ENUM_EXT(MTK_AFE_TDM_KCONTROL_NAME, mt8186_tdm_enum[0],
mt8186_tdm_hd_get, mt8186_tdm_hd_set),
};
static const struct snd_soc_dapm_route mtk_dai_tdm_routes[] = {
{"TDM IN", NULL, "aud_tdm_clk"},
{"TDM IN", NULL, "TDM_EN"},
{"TDM IN", NULL, TDM_HD_EN_W_NAME, mtk_afe_tdm_hd_connect},
{TDM_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_tdm_apll_connect},
{TDM_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_tdm_apll_connect},
{"TDM IN", NULL, TDM_MCLK_EN_W_NAME, mtk_afe_tdm_mclk_connect},
{TDM_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_tdm_mclk_apll_connect},
{TDM_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_tdm_mclk_apll_connect},
/* allow tdm on without codec on */
{"TDM IN", NULL, "TDM_In_Mux"},
{"TDM_In_Mux", "Dummy_Widget", "TDM_DUMMY_IN"},
};
/* dai ops */
static int mtk_dai_tdm_cal_mclk(struct mtk_base_afe *afe,
struct mtk_afe_tdm_priv *tdm_priv,
int freq)
{
int apll;
int apll_rate;
apll = mt8186_get_apll_by_rate(afe, freq);
apll_rate = mt8186_get_apll_rate(afe, apll);
if (!freq || freq > apll_rate) {
dev_err(afe->dev,
"%s(), freq(%d Hz) invalid\n", __func__, freq);
return -EINVAL;
}
if (apll_rate % freq != 0) {
dev_err(afe->dev,
"%s(), APLL cannot generate %d Hz", __func__, freq);
return -EINVAL;
}
tdm_priv->mclk_rate = freq;
tdm_priv->mclk_apll = apll;
return 0;
}
static int mtk_dai_tdm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8186_afe_private *afe_priv = afe->platform_priv;
int tdm_id = dai->id;
struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[tdm_id];
unsigned int tdm_mode = tdm_priv->tdm_mode;
unsigned int data_mode = tdm_priv->data_mode;
unsigned int rate = params_rate(params);
unsigned int channels = params_channels(params);
snd_pcm_format_t format = params_format(params);
unsigned int bit_width =
snd_pcm_format_physical_width(format);
unsigned int tdm_channels = (data_mode == TDM_DATA_ONE_PIN) ?
get_tdm_ch_per_sdata(tdm_mode, channels) : 2;
unsigned int lrck_width =
get_tdm_lrck_width(format, tdm_mode);
unsigned int tdm_con = 0;
bool slave_mode = tdm_priv->slave_mode;
bool lrck_inv = tdm_priv->lck_invert;
bool bck_inv = tdm_priv->bck_invert;
unsigned int tran_rate;
unsigned int tran_relatch_rate;
tdm_priv->rate = rate;
tran_rate = mt8186_rate_transform(afe->dev, rate, dai->id);
tran_relatch_rate = mt8186_tdm_relatch_rate_transform(afe->dev, rate);
/* calculate mclk_rate, if not set explicitly */
if (!tdm_priv->mclk_rate) {
tdm_priv->mclk_rate = rate * tdm_priv->mclk_multiple;
mtk_dai_tdm_cal_mclk(afe, tdm_priv, tdm_priv->mclk_rate);
}
/* ETDM_IN1_CON0 */
tdm_con |= slave_mode << ETDM_IN1_CON0_REG_SLAVE_MODE_SFT;
tdm_con |= tdm_mode << ETDM_IN1_CON0_REG_FMT_SFT;
tdm_con |= (bit_width - 1) << ETDM_IN1_CON0_REG_BIT_LENGTH_SFT;
tdm_con |= (bit_width - 1) << ETDM_IN1_CON0_REG_WORD_LENGTH_SFT;
tdm_con |= (tdm_channels - 1) << ETDM_IN1_CON0_REG_CH_NUM_SFT;
/* need to disable sync mode otherwise this may cause latch data error */
tdm_con |= 0 << ETDM_IN1_CON0_REG_SYNC_MODE_SFT;
/* relatch 1x en clock fix to h26m */
tdm_con |= 0 << ETDM_IN1_CON0_REG_RELATCH_1X_EN_SEL_DOMAIN_SFT;
regmap_update_bits(afe->regmap, ETDM_IN1_CON0, ETDM_IN_CON0_CTRL_MASK, tdm_con);
/* ETDM_IN1_CON1 */
tdm_con = 0;
tdm_con |= 0 << ETDM_IN1_CON1_REG_LRCK_AUTO_MODE_SFT;
tdm_con |= 1 << ETDM_IN1_CON1_PINMUX_MCLK_CTRL_OE_SFT;
tdm_con |= (lrck_width - 1) << ETDM_IN1_CON1_REG_LRCK_WIDTH_SFT;
regmap_update_bits(afe->regmap, ETDM_IN1_CON1, ETDM_IN_CON1_CTRL_MASK, tdm_con);
/* ETDM_IN1_CON3 */
tdm_con = 0;
tdm_con = ETDM_IN_CON3_FS(tran_rate);
regmap_update_bits(afe->regmap, ETDM_IN1_CON3, ETDM_IN_CON3_CTRL_MASK, tdm_con);
/* ETDM_IN1_CON4 */
tdm_con = 0;
tdm_con = ETDM_IN_CON4_FS(tran_relatch_rate);
if (slave_mode) {
if (lrck_inv)
tdm_con |= ETDM_IN_CON4_CON0_SLAVE_LRCK_INV;
if (bck_inv)
tdm_con |= ETDM_IN_CON4_CON0_SLAVE_BCK_INV;
} else {
if (lrck_inv)
tdm_con |= ETDM_IN_CON4_CON0_MASTER_LRCK_INV;
if (bck_inv)
tdm_con |= ETDM_IN_CON4_CON0_MASTER_BCK_INV;
}
regmap_update_bits(afe->regmap, ETDM_IN1_CON4, ETDM_IN_CON4_CTRL_MASK, tdm_con);
/* ETDM_IN1_CON2 */
tdm_con = 0;
if (data_mode == TDM_DATA_MULTI_PIN) {
tdm_con |= ETDM_IN_CON2_MULTI_IP_2CH_MODE;
tdm_con |= ETDM_IN_CON2_MULTI_IP_CH(channels);
}
regmap_update_bits(afe->regmap, ETDM_IN1_CON2, ETDM_IN_CON2_CTRL_MASK, tdm_con);
/* ETDM_IN1_CON8 */
tdm_con = 0;
if (slave_mode) {
tdm_con |= 1 << ETDM_IN1_CON8_REG_ETDM_USE_AFIFO_SFT;
tdm_con |= 0 << ETDM_IN1_CON8_REG_AFIFO_CLOCK_DOMAIN_SEL_SFT;
tdm_con |= ETDM_IN_CON8_FS(tran_relatch_rate);
} else {
tdm_con |= 0 << ETDM_IN1_CON8_REG_ETDM_USE_AFIFO_SFT;
}
regmap_update_bits(afe->regmap, ETDM_IN1_CON8, ETDM_IN_CON8_CTRL_MASK, tdm_con);
return 0;
}
static int mtk_dai_tdm_set_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct mtk_base_afe *afe = dev_get_drvdata(dai->dev);
struct mt8186_afe_private *afe_priv = afe->platform_priv;
struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[dai->id];
if (dir != SND_SOC_CLOCK_IN) {
dev_err(afe->dev, "%s(), dir != SND_SOC_CLOCK_OUT", __func__);
return -EINVAL;
}
dev_dbg(afe->dev, "%s(), freq %d\n", __func__, freq);
return mtk_dai_tdm_cal_mclk(afe, tdm_priv, freq);
}
static int mtk_dai_tdm_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct mtk_base_afe *afe = dev_get_drvdata(dai->dev);
struct mt8186_afe_private *afe_priv = afe->platform_priv;
struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[dai->id];
/* DAI mode*/
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
tdm_priv->tdm_mode = TDM_IN_I2S;
tdm_priv->data_mode = TDM_DATA_MULTI_PIN;
break;
case SND_SOC_DAIFMT_LEFT_J:
tdm_priv->tdm_mode = TDM_IN_LJ;
tdm_priv->data_mode = TDM_DATA_MULTI_PIN;
break;
case SND_SOC_DAIFMT_RIGHT_J:
tdm_priv->tdm_mode = TDM_IN_RJ;
tdm_priv->data_mode = TDM_DATA_MULTI_PIN;
break;
case SND_SOC_DAIFMT_DSP_A:
tdm_priv->tdm_mode = TDM_IN_DSP_A;
tdm_priv->data_mode = TDM_DATA_ONE_PIN;
break;
case SND_SOC_DAIFMT_DSP_B:
tdm_priv->tdm_mode = TDM_IN_DSP_B;
tdm_priv->data_mode = TDM_DATA_ONE_PIN;
break;
default:
dev_err(afe->dev, "%s(), invalid DAIFMT_FORMAT_MASK", __func__);
return -EINVAL;
}
/* DAI clock inversion*/
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
tdm_priv->bck_invert = TDM_BCK_NON_INV;
tdm_priv->lck_invert = TDM_LCK_NON_INV;
break;
case SND_SOC_DAIFMT_NB_IF:
tdm_priv->bck_invert = TDM_BCK_NON_INV;
tdm_priv->lck_invert = TDM_LCK_INV;
break;
case SND_SOC_DAIFMT_IB_NF:
tdm_priv->bck_invert = TDM_BCK_INV;
tdm_priv->lck_invert = TDM_LCK_NON_INV;
break;
case SND_SOC_DAIFMT_IB_IF:
tdm_priv->bck_invert = TDM_BCK_INV;
tdm_priv->lck_invert = TDM_LCK_INV;
break;
default:
dev_err(afe->dev, "%s(), invalid DAIFMT_INV_MASK", __func__);
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BP_FP:
tdm_priv->slave_mode = false;
break;
case SND_SOC_DAIFMT_BC_FC:
tdm_priv->slave_mode = true;
break;
default:
dev_err(afe->dev, "%s(), invalid DAIFMT_CLOCK_PROVIDER_MASK",
__func__);
return -EINVAL;
}
return 0;
}
static int mtk_dai_tdm_set_tdm_slot(struct snd_soc_dai *dai,
unsigned int tx_mask,
unsigned int rx_mask,
int slots,
int slot_width)
{
struct mtk_base_afe *afe = dev_get_drvdata(dai->dev);
struct mt8186_afe_private *afe_priv = afe->platform_priv;
struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[dai->id];
dev_dbg(dai->dev, "%s %d slot_width %d\n", __func__, dai->id, slot_width);
tdm_priv->lrck_width = slot_width;
return 0;
}
static const struct snd_soc_dai_ops mtk_dai_tdm_ops = {
.hw_params = mtk_dai_tdm_hw_params,
.set_sysclk = mtk_dai_tdm_set_sysclk,
.set_fmt = mtk_dai_tdm_set_fmt,
.set_tdm_slot = mtk_dai_tdm_set_tdm_slot,
};
/* dai driver */
#define MTK_TDM_RATES (SNDRV_PCM_RATE_8000_48000 |\
SNDRV_PCM_RATE_88200 |\
SNDRV_PCM_RATE_96000 |\
SNDRV_PCM_RATE_176400 |\
SNDRV_PCM_RATE_192000)
#define MTK_TDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver mtk_dai_tdm_driver[] = {
{
.name = "TDM IN",
.id = MT8186_DAI_TDM_IN,
.capture = {
.stream_name = "TDM IN",
.channels_min = 2,
.channels_max = 8,
.rates = MTK_TDM_RATES,
.formats = MTK_TDM_FORMATS,
},
.ops = &mtk_dai_tdm_ops,
},
};
static struct mtk_afe_tdm_priv *init_tdm_priv_data(struct mtk_base_afe *afe)
{
struct mtk_afe_tdm_priv *tdm_priv;
tdm_priv = devm_kzalloc(afe->dev, sizeof(struct mtk_afe_tdm_priv),
GFP_KERNEL);
if (!tdm_priv)
return NULL;
tdm_priv->mclk_multiple = 512;
tdm_priv->mclk_id = MT8186_TDM_MCK;
tdm_priv->id = MT8186_DAI_TDM_IN;
return tdm_priv;
}
int mt8186_dai_tdm_register(struct mtk_base_afe *afe)
{
struct mt8186_afe_private *afe_priv = afe->platform_priv;
struct mtk_afe_tdm_priv *tdm_priv;
struct mtk_base_afe_dai *dai;
dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
if (!dai)
return -ENOMEM;
list_add(&dai->list, &afe->sub_dais);
dai->dai_drivers = mtk_dai_tdm_driver;
dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_tdm_driver);
dai->controls = mtk_dai_tdm_controls;
dai->num_controls = ARRAY_SIZE(mtk_dai_tdm_controls);
dai->dapm_widgets = mtk_dai_tdm_widgets;
dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_tdm_widgets);
dai->dapm_routes = mtk_dai_tdm_routes;
dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_tdm_routes);
tdm_priv = init_tdm_priv_data(afe);
if (!tdm_priv)
return -ENOMEM;
afe_priv->dai_priv[MT8186_DAI_TDM_IN] = tdm_priv;
return 0;
}
| linux-master | sound/soc/mediatek/mt8186/mt8186-dai-tdm.c |
// SPDX-License-Identifier: GPL-2.0
//
// MediaTek ALSA SoC Audio DAI HW Gain Control
//
// Copyright (c) 2022 MediaTek Inc.
// Author: Jiaxin Yu <[email protected]>
#include <linux/regmap.h>
#include "mt8186-afe-common.h"
#include "mt8186-interconnection.h"
#define HW_GAIN_1_EN_W_NAME "HW GAIN 1 Enable"
#define HW_GAIN_2_EN_W_NAME "HW GAIN 2 Enable"
/* dai component */
static const struct snd_kcontrol_new mtk_hw_gain1_in_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("CONNSYS_I2S_CH1 Switch", AFE_CONN13_1,
I_CONNSYS_I2S_CH1, 1, 0),
};
static const struct snd_kcontrol_new mtk_hw_gain1_in_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("CONNSYS_I2S_CH2 Switch", AFE_CONN14_1,
I_CONNSYS_I2S_CH2, 1, 0),
};
static const struct snd_kcontrol_new mtk_hw_gain2_in_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN15,
I_ADDA_UL_CH1, 1, 0),
};
static const struct snd_kcontrol_new mtk_hw_gain2_in_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN16,
I_ADDA_UL_CH2, 1, 0),
};
static int mtk_hw_gain_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
unsigned int gain_cur;
unsigned int gain_con1;
dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x\n",
__func__, w->name, event);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
if (strcmp(w->name, HW_GAIN_1_EN_W_NAME) == 0) {
gain_cur = AFE_GAIN1_CUR;
gain_con1 = AFE_GAIN1_CON1;
} else {
gain_cur = AFE_GAIN2_CUR;
gain_con1 = AFE_GAIN2_CON1;
}
/* let hw gain ramp up, set cur gain to 0 */
regmap_update_bits(afe->regmap, gain_cur, AFE_GAIN1_CUR_MASK_SFT, 0);
/* set target gain to 0 */
regmap_update_bits(afe->regmap, gain_con1, GAIN1_TARGET_MASK_SFT, 0);
break;
default:
break;
}
return 0;
}
static const struct snd_soc_dapm_widget mtk_dai_hw_gain_widgets[] = {
/* inter-connections */
SND_SOC_DAPM_MIXER("HW_GAIN1_IN_CH1", SND_SOC_NOPM, 0, 0,
mtk_hw_gain1_in_ch1_mix,
ARRAY_SIZE(mtk_hw_gain1_in_ch1_mix)),
SND_SOC_DAPM_MIXER("HW_GAIN1_IN_CH2", SND_SOC_NOPM, 0, 0,
mtk_hw_gain1_in_ch2_mix,
ARRAY_SIZE(mtk_hw_gain1_in_ch2_mix)),
SND_SOC_DAPM_MIXER("HW_GAIN2_IN_CH1", SND_SOC_NOPM, 0, 0,
mtk_hw_gain2_in_ch1_mix,
ARRAY_SIZE(mtk_hw_gain2_in_ch1_mix)),
SND_SOC_DAPM_MIXER("HW_GAIN2_IN_CH2", SND_SOC_NOPM, 0, 0,
mtk_hw_gain2_in_ch2_mix,
ARRAY_SIZE(mtk_hw_gain2_in_ch2_mix)),
SND_SOC_DAPM_SUPPLY(HW_GAIN_1_EN_W_NAME,
AFE_GAIN1_CON0, GAIN1_ON_SFT, 0,
mtk_hw_gain_event,
SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_SUPPLY(HW_GAIN_2_EN_W_NAME,
AFE_GAIN2_CON0, GAIN2_ON_SFT, 0,
mtk_hw_gain_event,
SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_INPUT("HW Gain 1 Out Endpoint"),
SND_SOC_DAPM_INPUT("HW Gain 2 Out Endpoint"),
SND_SOC_DAPM_OUTPUT("HW Gain 1 In Endpoint"),
};
static const struct snd_soc_dapm_route mtk_dai_hw_gain_routes[] = {
{"HW Gain 1 In", NULL, "HW_GAIN1_IN_CH1"},
{"HW Gain 1 In", NULL, "HW_GAIN1_IN_CH2"},
{"HW Gain 2 In", NULL, "HW_GAIN2_IN_CH1"},
{"HW Gain 2 In", NULL, "HW_GAIN2_IN_CH2"},
{"HW Gain 1 In", NULL, HW_GAIN_1_EN_W_NAME},
{"HW Gain 1 Out", NULL, HW_GAIN_1_EN_W_NAME},
{"HW Gain 2 In", NULL, HW_GAIN_2_EN_W_NAME},
{"HW Gain 2 Out", NULL, HW_GAIN_2_EN_W_NAME},
{"HW Gain 1 In Endpoint", NULL, "HW Gain 1 In"},
{"HW Gain 1 Out", NULL, "HW Gain 1 Out Endpoint"},
{"HW Gain 2 Out", NULL, "HW Gain 2 Out Endpoint"},
};
static const struct snd_kcontrol_new mtk_hw_gain_controls[] = {
SOC_SINGLE("HW Gain 1 Volume", AFE_GAIN1_CON1,
GAIN1_TARGET_SFT, GAIN1_TARGET_MASK, 0),
SOC_SINGLE("HW Gain 2 Volume", AFE_GAIN2_CON1,
GAIN2_TARGET_SFT, GAIN2_TARGET_MASK, 0),
};
/* dai ops */
static int mtk_dai_gain_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
unsigned int rate = params_rate(params);
unsigned int rate_reg = mt8186_rate_transform(afe->dev, rate, dai->id);
dev_dbg(afe->dev, "%s(), id %d, stream %d, rate %d\n",
__func__, dai->id, substream->stream, rate);
/* rate */
regmap_update_bits(afe->regmap,
dai->id == MT8186_DAI_HW_GAIN_1 ?
AFE_GAIN1_CON0 : AFE_GAIN2_CON0,
GAIN1_MODE_MASK_SFT,
rate_reg << GAIN1_MODE_SFT);
/* sample per step */
regmap_update_bits(afe->regmap,
dai->id == MT8186_DAI_HW_GAIN_1 ?
AFE_GAIN1_CON0 : AFE_GAIN2_CON0,
GAIN1_SAMPLE_PER_STEP_MASK_SFT,
(dai->id == MT8186_DAI_HW_GAIN_1 ? 0x40 : 0x0) <<
GAIN1_SAMPLE_PER_STEP_SFT);
return 0;
}
static const struct snd_soc_dai_ops mtk_dai_gain_ops = {
.hw_params = mtk_dai_gain_hw_params,
};
/* dai driver */
#define MTK_HW_GAIN_RATES (SNDRV_PCM_RATE_8000_48000 |\
SNDRV_PCM_RATE_88200 |\
SNDRV_PCM_RATE_96000 |\
SNDRV_PCM_RATE_176400 |\
SNDRV_PCM_RATE_192000)
#define MTK_HW_GAIN_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver mtk_dai_gain_driver[] = {
{
.name = "HW Gain 1",
.id = MT8186_DAI_HW_GAIN_1,
.playback = {
.stream_name = "HW Gain 1 In",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_HW_GAIN_RATES,
.formats = MTK_HW_GAIN_FORMATS,
},
.capture = {
.stream_name = "HW Gain 1 Out",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_HW_GAIN_RATES,
.formats = MTK_HW_GAIN_FORMATS,
},
.ops = &mtk_dai_gain_ops,
.symmetric_rate = 1,
.symmetric_channels = 1,
.symmetric_sample_bits = 1,
},
{
.name = "HW Gain 2",
.id = MT8186_DAI_HW_GAIN_2,
.playback = {
.stream_name = "HW Gain 2 In",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_HW_GAIN_RATES,
.formats = MTK_HW_GAIN_FORMATS,
},
.capture = {
.stream_name = "HW Gain 2 Out",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_HW_GAIN_RATES,
.formats = MTK_HW_GAIN_FORMATS,
},
.ops = &mtk_dai_gain_ops,
.symmetric_rate = 1,
.symmetric_channels = 1,
.symmetric_sample_bits = 1,
},
};
int mt8186_dai_hw_gain_register(struct mtk_base_afe *afe)
{
struct mtk_base_afe_dai *dai;
dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
if (!dai)
return -ENOMEM;
list_add(&dai->list, &afe->sub_dais);
dai->dai_drivers = mtk_dai_gain_driver;
dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_gain_driver);
dai->controls = mtk_hw_gain_controls;
dai->num_controls = ARRAY_SIZE(mtk_hw_gain_controls);
dai->dapm_widgets = mtk_dai_hw_gain_widgets;
dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_hw_gain_widgets);
dai->dapm_routes = mtk_dai_hw_gain_routes;
dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_hw_gain_routes);
return 0;
}
| linux-master | sound/soc/mediatek/mt8186/mt8186-dai-hw-gain.c |
// SPDX-License-Identifier: GPL-2.0
//
// mt8186-mt6366-rt1019-rt5682s.c
// -- MT8186-MT6366-RT1019-RT5682S ALSA SoC machine driver
//
// Copyright (c) 2022 MediaTek Inc.
// Author: Jiaxin Yu <[email protected]>
//
#include <linux/gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/input.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <sound/jack.h>
#include <sound/pcm_params.h>
#include <sound/rt5682.h>
#include <sound/soc.h>
#include "../../codecs/mt6358.h"
#include "../../codecs/rt5682.h"
#include "../common/mtk-afe-platform-driver.h"
#include "../common/mtk-dsp-sof-common.h"
#include "../common/mtk-soc-card.h"
#include "mt8186-afe-common.h"
#include "mt8186-afe-clk.h"
#include "mt8186-afe-gpio.h"
#include "mt8186-mt6366-common.h"
#define RT1019_CODEC_DAI "HiFi"
#define RT1019_DEV0_NAME "rt1019p"
#define RT5682S_CODEC_DAI "rt5682s-aif1"
#define RT5682S_DEV0_NAME "rt5682s.5-001a"
#define SOF_DMA_DL1 "SOF_DMA_DL1"
#define SOF_DMA_DL2 "SOF_DMA_DL2"
#define SOF_DMA_UL1 "SOF_DMA_UL1"
#define SOF_DMA_UL2 "SOF_DMA_UL2"
struct mt8186_mt6366_rt1019_rt5682s_priv {
struct snd_soc_jack headset_jack, hdmi_jack;
struct gpio_desc *dmic_sel;
int dmic_switch;
};
/* Headset jack detection DAPM pins */
static struct snd_soc_jack_pin mt8186_jack_pins[] = {
{
.pin = "Headphone",
.mask = SND_JACK_HEADPHONE,
},
{
.pin = "Headset Mic",
.mask = SND_JACK_MICROPHONE,
},
};
static struct snd_soc_codec_conf mt8186_mt6366_rt1019_rt5682s_codec_conf[] = {
{
.dlc = COMP_CODEC_CONF("mt6358-sound"),
.name_prefix = "Mt6366",
},
{
.dlc = COMP_CODEC_CONF("bt-sco"),
.name_prefix = "Mt8186 bt",
},
{
.dlc = COMP_CODEC_CONF("hdmi-audio-codec"),
.name_prefix = "Mt8186 hdmi",
},
};
static int dmic_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kcontrol);
struct mtk_soc_card_data *soc_card_data =
snd_soc_card_get_drvdata(dapm->card);
struct mt8186_mt6366_rt1019_rt5682s_priv *priv = soc_card_data->mach_priv;
ucontrol->value.integer.value[0] = priv->dmic_switch;
return 0;
}
static int dmic_set(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kcontrol);
struct mtk_soc_card_data *soc_card_data =
snd_soc_card_get_drvdata(dapm->card);
struct mt8186_mt6366_rt1019_rt5682s_priv *priv = soc_card_data->mach_priv;
priv->dmic_switch = ucontrol->value.integer.value[0];
if (priv->dmic_sel) {
gpiod_set_value(priv->dmic_sel, priv->dmic_switch);
dev_dbg(dapm->card->dev, "dmic_set_value %d\n",
priv->dmic_switch);
}
return 0;
}
static const char * const dmic_mux_text[] = {
"Front Mic",
"Rear Mic",
};
static SOC_ENUM_SINGLE_DECL(mt8186_dmic_enum,
SND_SOC_NOPM, 0, dmic_mux_text);
static const struct snd_kcontrol_new mt8186_dmic_mux_control =
SOC_DAPM_ENUM_EXT("DMIC Select Mux", mt8186_dmic_enum,
dmic_get, dmic_set);
static const struct snd_soc_dapm_widget dmic_widgets[] = {
SND_SOC_DAPM_MIC("DMIC", NULL),
SND_SOC_DAPM_MUX("Dmic Mux", SND_SOC_NOPM, 0, 0, &mt8186_dmic_mux_control),
};
static const struct snd_soc_dapm_route dmic_map[] = {
/* digital mics */
{"Dmic Mux", "Front Mic", "DMIC"},
{"Dmic Mux", "Rear Mic", "DMIC"},
};
static int primary_codec_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_card *card = rtd->card;
struct mtk_soc_card_data *soc_card_data = snd_soc_card_get_drvdata(card);
struct mt8186_mt6366_rt1019_rt5682s_priv *priv = soc_card_data->mach_priv;
int ret;
ret = mt8186_mt6366_init(rtd);
if (ret) {
dev_err(card->dev, "mt8186_mt6366_init failed: %d\n", ret);
return ret;
}
if (!priv->dmic_sel) {
dev_dbg(card->dev, "dmic_sel is null\n");
return 0;
}
ret = snd_soc_dapm_new_controls(&card->dapm, dmic_widgets,
ARRAY_SIZE(dmic_widgets));
if (ret) {
dev_err(card->dev, "DMic widget addition failed: %d\n", ret);
/* Don't need to add routes if widget addition failed */
return ret;
}
ret = snd_soc_dapm_add_routes(&card->dapm, dmic_map,
ARRAY_SIZE(dmic_map));
if (ret)
dev_err(card->dev, "DMic map addition failed: %d\n", ret);
return ret;
}
static int mt8186_rt5682s_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_component *cmpnt_afe =
snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt_afe);
struct mtk_soc_card_data *soc_card_data =
snd_soc_card_get_drvdata(rtd->card);
struct mt8186_mt6366_rt1019_rt5682s_priv *priv = soc_card_data->mach_priv;
struct snd_soc_jack *jack = &priv->headset_jack;
struct snd_soc_component *cmpnt_codec =
asoc_rtd_to_codec(rtd, 0)->component;
int ret;
ret = mt8186_dai_i2s_set_share(afe, "I2S1", "I2S0");
if (ret) {
dev_err(rtd->dev, "Failed to set up shared clocks\n");
return ret;
}
ret = snd_soc_card_jack_new_pins(rtd->card, "Headset Jack",
SND_JACK_HEADSET | SND_JACK_BTN_0 |
SND_JACK_BTN_1 | SND_JACK_BTN_2 |
SND_JACK_BTN_3,
jack, mt8186_jack_pins,
ARRAY_SIZE(mt8186_jack_pins));
if (ret) {
dev_err(rtd->dev, "Headset Jack creation failed: %d\n", ret);
return ret;
}
snd_jack_set_key(jack->jack, SND_JACK_BTN_0, KEY_PLAYPAUSE);
snd_jack_set_key(jack->jack, SND_JACK_BTN_1, KEY_VOICECOMMAND);
snd_jack_set_key(jack->jack, SND_JACK_BTN_2, KEY_VOLUMEUP);
snd_jack_set_key(jack->jack, SND_JACK_BTN_3, KEY_VOLUMEDOWN);
return snd_soc_component_set_jack(cmpnt_codec, jack, NULL);
}
static int mt8186_rt5682s_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_card *card = rtd->card;
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
unsigned int rate = params_rate(params);
unsigned int mclk_fs_ratio = 128;
unsigned int mclk_fs = rate * mclk_fs_ratio;
int bitwidth;
int ret;
bitwidth = snd_pcm_format_width(params_format(params));
if (bitwidth < 0) {
dev_err(card->dev, "invalid bit width: %d\n", bitwidth);
return bitwidth;
}
ret = snd_soc_dai_set_tdm_slot(codec_dai, 0x00, 0x0, 0x2, bitwidth);
if (ret) {
dev_err(card->dev, "failed to set tdm slot\n");
return ret;
}
ret = snd_soc_dai_set_pll(codec_dai, RT5682_PLL1,
RT5682_PLL1_S_BCLK1,
params_rate(params) * 64,
params_rate(params) * 512);
if (ret) {
dev_err(card->dev, "failed to set pll\n");
return ret;
}
ret = snd_soc_dai_set_sysclk(codec_dai,
RT5682_SCLK_S_PLL1,
params_rate(params) * 512,
SND_SOC_CLOCK_IN);
if (ret) {
dev_err(card->dev, "failed to set sysclk\n");
return ret;
}
return snd_soc_dai_set_sysclk(cpu_dai, 0, mclk_fs, SND_SOC_CLOCK_OUT);
}
static const struct snd_soc_ops mt8186_rt5682s_i2s_ops = {
.hw_params = mt8186_rt5682s_i2s_hw_params,
};
static int mt8186_mt6366_rt1019_rt5682s_hdmi_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_component *cmpnt_afe =
snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt_afe);
struct snd_soc_component *cmpnt_codec =
asoc_rtd_to_codec(rtd, 0)->component;
struct mtk_soc_card_data *soc_card_data =
snd_soc_card_get_drvdata(rtd->card);
struct mt8186_mt6366_rt1019_rt5682s_priv *priv = soc_card_data->mach_priv;
int ret;
ret = mt8186_dai_i2s_set_share(afe, "I2S2", "I2S3");
if (ret) {
dev_err(rtd->dev, "Failed to set up shared clocks\n");
return ret;
}
ret = snd_soc_card_jack_new(rtd->card, "HDMI Jack", SND_JACK_LINEOUT, &priv->hdmi_jack);
if (ret) {
dev_err(rtd->dev, "HDMI Jack creation failed: %d\n", ret);
return ret;
}
return snd_soc_component_set_jack(cmpnt_codec, &priv->hdmi_jack, NULL);
}
static int mt8186_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
struct snd_pcm_hw_params *params,
snd_pcm_format_t fmt)
{
struct snd_interval *channels = hw_param_interval(params,
SNDRV_PCM_HW_PARAM_CHANNELS);
dev_dbg(rtd->dev, "%s(), fix format to %d\n", __func__, fmt);
/* fix BE i2s channel to 2 channel */
channels->min = 2;
channels->max = 2;
/* clean param mask first */
snd_mask_reset_range(hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT),
0, (__force unsigned int)SNDRV_PCM_FORMAT_LAST);
params_set_format(params, fmt);
return 0;
}
static int mt8186_i2s_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
struct snd_pcm_hw_params *params)
{
return mt8186_hw_params_fixup(rtd, params, SNDRV_PCM_FORMAT_S24_LE);
}
static int mt8186_it6505_i2s_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
struct snd_pcm_hw_params *params)
{
return mt8186_hw_params_fixup(rtd, params, SNDRV_PCM_FORMAT_S32_LE);
}
/* fixup the BE DAI link to match any values from topology */
static int mt8186_sof_dai_link_fixup(struct snd_soc_pcm_runtime *rtd,
struct snd_pcm_hw_params *params)
{
int ret;
ret = mtk_sof_dai_link_fixup(rtd, params);
if (!strcmp(rtd->dai_link->name, "I2S0") ||
!strcmp(rtd->dai_link->name, "I2S1") ||
!strcmp(rtd->dai_link->name, "I2S2"))
mt8186_i2s_hw_params_fixup(rtd, params);
else if (!strcmp(rtd->dai_link->name, "I2S3"))
mt8186_it6505_i2s_hw_params_fixup(rtd, params);
return ret;
}
static int mt8186_mt6366_rt1019_rt5682s_playback_startup(struct snd_pcm_substream *substream)
{
static const unsigned int rates[] = {
48000
};
static const unsigned int channels[] = {
2
};
static const struct snd_pcm_hw_constraint_list constraints_rates = {
.count = ARRAY_SIZE(rates),
.list = rates,
.mask = 0,
};
static const struct snd_pcm_hw_constraint_list constraints_channels = {
.count = ARRAY_SIZE(channels),
.list = channels,
.mask = 0,
};
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_pcm_runtime *runtime = substream->runtime;
int ret;
ret = snd_pcm_hw_constraint_list(runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
&constraints_rates);
if (ret < 0) {
dev_err(rtd->dev, "hw_constraint_list rate failed\n");
return ret;
}
ret = snd_pcm_hw_constraint_list(runtime, 0,
SNDRV_PCM_HW_PARAM_CHANNELS,
&constraints_channels);
if (ret < 0) {
dev_err(rtd->dev, "hw_constraint_list channel failed\n");
return ret;
}
return 0;
}
static const struct snd_soc_ops mt8186_mt6366_rt1019_rt5682s_playback_ops = {
.startup = mt8186_mt6366_rt1019_rt5682s_playback_startup,
};
static int mt8186_mt6366_rt1019_rt5682s_capture_startup(struct snd_pcm_substream *substream)
{
static const unsigned int rates[] = {
48000
};
static const unsigned int channels[] = {
1, 2
};
static const struct snd_pcm_hw_constraint_list constraints_rates = {
.count = ARRAY_SIZE(rates),
.list = rates,
.mask = 0,
};
static const struct snd_pcm_hw_constraint_list constraints_channels = {
.count = ARRAY_SIZE(channels),
.list = channels,
.mask = 0,
};
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_pcm_runtime *runtime = substream->runtime;
int ret;
ret = snd_pcm_hw_constraint_list(runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
&constraints_rates);
if (ret < 0) {
dev_err(rtd->dev, "hw_constraint_list rate failed\n");
return ret;
}
ret = snd_pcm_hw_constraint_list(runtime, 0,
SNDRV_PCM_HW_PARAM_CHANNELS,
&constraints_channels);
if (ret < 0) {
dev_err(rtd->dev, "hw_constraint_list channel failed\n");
return ret;
}
return 0;
}
static const struct snd_soc_ops mt8186_mt6366_rt1019_rt5682s_capture_ops = {
.startup = mt8186_mt6366_rt1019_rt5682s_capture_startup,
};
/* FE */
SND_SOC_DAILINK_DEFS(playback1,
DAILINK_COMP_ARRAY(COMP_CPU("DL1")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(playback12,
DAILINK_COMP_ARRAY(COMP_CPU("DL12")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(playback2,
DAILINK_COMP_ARRAY(COMP_CPU("DL2")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(playback3,
DAILINK_COMP_ARRAY(COMP_CPU("DL3")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(playback4,
DAILINK_COMP_ARRAY(COMP_CPU("DL4")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(playback5,
DAILINK_COMP_ARRAY(COMP_CPU("DL5")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(playback6,
DAILINK_COMP_ARRAY(COMP_CPU("DL6")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(playback7,
DAILINK_COMP_ARRAY(COMP_CPU("DL7")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(playback8,
DAILINK_COMP_ARRAY(COMP_CPU("DL8")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture1,
DAILINK_COMP_ARRAY(COMP_CPU("UL1")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture2,
DAILINK_COMP_ARRAY(COMP_CPU("UL2")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture3,
DAILINK_COMP_ARRAY(COMP_CPU("UL3")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture4,
DAILINK_COMP_ARRAY(COMP_CPU("UL4")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture5,
DAILINK_COMP_ARRAY(COMP_CPU("UL5")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture6,
DAILINK_COMP_ARRAY(COMP_CPU("UL6")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture7,
DAILINK_COMP_ARRAY(COMP_CPU("UL7")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
/* hostless */
SND_SOC_DAILINK_DEFS(hostless_lpbk,
DAILINK_COMP_ARRAY(COMP_CPU("Hostless LPBK DAI")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(hostless_fm,
DAILINK_COMP_ARRAY(COMP_CPU("Hostless FM DAI")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(hostless_src1,
DAILINK_COMP_ARRAY(COMP_CPU("Hostless_SRC_1_DAI")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(hostless_src_bargein,
DAILINK_COMP_ARRAY(COMP_CPU("Hostless_SRC_Bargein_DAI")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
/* BE */
SND_SOC_DAILINK_DEFS(adda,
DAILINK_COMP_ARRAY(COMP_CPU("ADDA")),
DAILINK_COMP_ARRAY(COMP_CODEC("mt6358-sound",
"mt6358-snd-codec-aif1"),
COMP_CODEC("dmic-codec",
"dmic-hifi")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(i2s0,
DAILINK_COMP_ARRAY(COMP_CPU("I2S0")),
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(i2s1,
DAILINK_COMP_ARRAY(COMP_CPU("I2S1")),
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(i2s2,
DAILINK_COMP_ARRAY(COMP_CPU("I2S2")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(i2s3,
DAILINK_COMP_ARRAY(COMP_CPU("I2S3")),
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(hw_gain1,
DAILINK_COMP_ARRAY(COMP_CPU("HW Gain 1")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(hw_gain2,
DAILINK_COMP_ARRAY(COMP_CPU("HW Gain 2")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(hw_src1,
DAILINK_COMP_ARRAY(COMP_CPU("HW_SRC_1")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(hw_src2,
DAILINK_COMP_ARRAY(COMP_CPU("HW_SRC_2")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(connsys_i2s,
DAILINK_COMP_ARRAY(COMP_CPU("CONNSYS_I2S")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(pcm1,
DAILINK_COMP_ARRAY(COMP_CPU("PCM 1")),
DAILINK_COMP_ARRAY(COMP_CODEC("bt-sco", "bt-sco-pcm-wb")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(tdm_in,
DAILINK_COMP_ARRAY(COMP_CPU("TDM IN")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
/* hostless */
SND_SOC_DAILINK_DEFS(hostless_ul1,
DAILINK_COMP_ARRAY(COMP_CPU("Hostless_UL1 DAI")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(hostless_ul2,
DAILINK_COMP_ARRAY(COMP_CPU("Hostless_UL2 DAI")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(hostless_ul3,
DAILINK_COMP_ARRAY(COMP_CPU("Hostless_UL3 DAI")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(hostless_ul5,
DAILINK_COMP_ARRAY(COMP_CPU("Hostless_UL5 DAI")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(hostless_ul6,
DAILINK_COMP_ARRAY(COMP_CPU("Hostless_UL6 DAI")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(hostless_hw_gain_aaudio,
DAILINK_COMP_ARRAY(COMP_CPU("Hostless HW Gain AAudio DAI")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(hostless_src_aaudio,
DAILINK_COMP_ARRAY(COMP_CPU("Hostless SRC AAudio DAI")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(AFE_SOF_DL1,
DAILINK_COMP_ARRAY(COMP_CPU("SOF_DL1")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(AFE_SOF_DL2,
DAILINK_COMP_ARRAY(COMP_CPU("SOF_DL2")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(AFE_SOF_UL1,
DAILINK_COMP_ARRAY(COMP_CPU("SOF_UL1")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(AFE_SOF_UL2,
DAILINK_COMP_ARRAY(COMP_CPU("SOF_UL2")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
static const struct sof_conn_stream g_sof_conn_streams[] = {
{ "I2S1", "AFE_SOF_DL1", SOF_DMA_DL1, SNDRV_PCM_STREAM_PLAYBACK},
{ "I2S3", "AFE_SOF_DL2", SOF_DMA_DL2, SNDRV_PCM_STREAM_PLAYBACK},
{ "Primary Codec", "AFE_SOF_UL1", SOF_DMA_UL1, SNDRV_PCM_STREAM_CAPTURE},
{ "I2S0", "AFE_SOF_UL2", SOF_DMA_UL2, SNDRV_PCM_STREAM_CAPTURE},
};
static struct snd_soc_dai_link mt8186_mt6366_rt1019_rt5682s_dai_links[] = {
/* Front End DAI links */
{
.name = "Playback_1",
.stream_name = "Playback_1",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
.dpcm_merged_format = 1,
.dpcm_merged_chan = 1,
.dpcm_merged_rate = 1,
.ops = &mt8186_mt6366_rt1019_rt5682s_playback_ops,
SND_SOC_DAILINK_REG(playback1),
},
{
.name = "Playback_12",
.stream_name = "Playback_12",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(playback12),
},
{
.name = "Playback_2",
.stream_name = "Playback_2",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
.dpcm_merged_format = 1,
.dpcm_merged_chan = 1,
.dpcm_merged_rate = 1,
SND_SOC_DAILINK_REG(playback2),
},
{
.name = "Playback_3",
.stream_name = "Playback_3",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
.dpcm_merged_format = 1,
.dpcm_merged_chan = 1,
.dpcm_merged_rate = 1,
.ops = &mt8186_mt6366_rt1019_rt5682s_playback_ops,
SND_SOC_DAILINK_REG(playback3),
},
{
.name = "Playback_4",
.stream_name = "Playback_4",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(playback4),
},
{
.name = "Playback_5",
.stream_name = "Playback_5",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(playback5),
},
{
.name = "Playback_6",
.stream_name = "Playback_6",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(playback6),
},
{
.name = "Playback_7",
.stream_name = "Playback_7",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(playback7),
},
{
.name = "Playback_8",
.stream_name = "Playback_8",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(playback8),
},
{
.name = "Capture_1",
.stream_name = "Capture_1",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(capture1),
},
{
.name = "Capture_2",
.stream_name = "Capture_2",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_capture = 1,
.dpcm_merged_format = 1,
.dpcm_merged_chan = 1,
.dpcm_merged_rate = 1,
.ops = &mt8186_mt6366_rt1019_rt5682s_capture_ops,
SND_SOC_DAILINK_REG(capture2),
},
{
.name = "Capture_3",
.stream_name = "Capture_3",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(capture3),
},
{
.name = "Capture_4",
.stream_name = "Capture_4",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_capture = 1,
.dpcm_merged_format = 1,
.dpcm_merged_chan = 1,
.dpcm_merged_rate = 1,
.ops = &mt8186_mt6366_rt1019_rt5682s_capture_ops,
SND_SOC_DAILINK_REG(capture4),
},
{
.name = "Capture_5",
.stream_name = "Capture_5",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(capture5),
},
{
.name = "Capture_6",
.stream_name = "Capture_6",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_capture = 1,
.dpcm_merged_format = 1,
.dpcm_merged_chan = 1,
.dpcm_merged_rate = 1,
SND_SOC_DAILINK_REG(capture6),
},
{
.name = "Capture_7",
.stream_name = "Capture_7",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(capture7),
},
{
.name = "Hostless_LPBK",
.stream_name = "Hostless_LPBK",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(hostless_lpbk),
},
{
.name = "Hostless_FM",
.stream_name = "Hostless_FM",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(hostless_fm),
},
{
.name = "Hostless_SRC_1",
.stream_name = "Hostless_SRC_1",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(hostless_src1),
},
{
.name = "Hostless_SRC_Bargein",
.stream_name = "Hostless_SRC_Bargein",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(hostless_src_bargein),
},
{
.name = "Hostless_HW_Gain_AAudio",
.stream_name = "Hostless_HW_Gain_AAudio",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(hostless_hw_gain_aaudio),
},
{
.name = "Hostless_SRC_AAudio",
.stream_name = "Hostless_SRC_AAudio",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(hostless_src_aaudio),
},
/* Back End DAI links */
{
.name = "Primary Codec",
.no_pcm = 1,
.dpcm_playback = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
.init = primary_codec_init,
SND_SOC_DAILINK_REG(adda),
},
{
.name = "I2S3",
.no_pcm = 1,
.dai_fmt = SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_IB_IF |
SND_SOC_DAIFMT_CBM_CFM,
.dpcm_playback = 1,
.ignore_suspend = 1,
.init = mt8186_mt6366_rt1019_rt5682s_hdmi_init,
.be_hw_params_fixup = mt8186_it6505_i2s_hw_params_fixup,
SND_SOC_DAILINK_REG(i2s3),
},
{
.name = "I2S0",
.no_pcm = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
.be_hw_params_fixup = mt8186_i2s_hw_params_fixup,
.ops = &mt8186_rt5682s_i2s_ops,
SND_SOC_DAILINK_REG(i2s0),
},
{
.name = "I2S1",
.no_pcm = 1,
.dpcm_playback = 1,
.ignore_suspend = 1,
.be_hw_params_fixup = mt8186_i2s_hw_params_fixup,
.init = mt8186_rt5682s_init,
.ops = &mt8186_rt5682s_i2s_ops,
SND_SOC_DAILINK_REG(i2s1),
},
{
.name = "I2S2",
.no_pcm = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
.be_hw_params_fixup = mt8186_i2s_hw_params_fixup,
SND_SOC_DAILINK_REG(i2s2),
},
{
.name = "HW Gain 1",
.no_pcm = 1,
.dpcm_playback = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(hw_gain1),
},
{
.name = "HW Gain 2",
.no_pcm = 1,
.dpcm_playback = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(hw_gain2),
},
{
.name = "HW_SRC_1",
.no_pcm = 1,
.dpcm_playback = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(hw_src1),
},
{
.name = "HW_SRC_2",
.no_pcm = 1,
.dpcm_playback = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(hw_src2),
},
{
.name = "CONNSYS_I2S",
.no_pcm = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(connsys_i2s),
},
{
.name = "PCM 1",
.dai_fmt = SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_NB_IF,
.no_pcm = 1,
.dpcm_playback = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(pcm1),
},
{
.name = "TDM IN",
.no_pcm = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(tdm_in),
},
/* dummy BE for ul memif to record from dl memif */
{
.name = "Hostless_UL1",
.no_pcm = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(hostless_ul1),
},
{
.name = "Hostless_UL2",
.no_pcm = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(hostless_ul2),
},
{
.name = "Hostless_UL3",
.no_pcm = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(hostless_ul3),
},
{
.name = "Hostless_UL5",
.no_pcm = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(hostless_ul5),
},
{
.name = "Hostless_UL6",
.no_pcm = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(hostless_ul6),
},
/* SOF BE */
{
.name = "AFE_SOF_DL1",
.no_pcm = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(AFE_SOF_DL1),
},
{
.name = "AFE_SOF_DL2",
.no_pcm = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(AFE_SOF_DL2),
},
{
.name = "AFE_SOF_UL1",
.no_pcm = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(AFE_SOF_UL1),
},
{
.name = "AFE_SOF_UL2",
.no_pcm = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(AFE_SOF_UL2),
},
};
static const struct snd_soc_dapm_widget
mt8186_mt6366_rt1019_rt5682s_widgets[] = {
SND_SOC_DAPM_SPK("Speakers", NULL),
SND_SOC_DAPM_HP("Headphone", NULL),
SND_SOC_DAPM_MIC("Headset Mic", NULL),
SND_SOC_DAPM_OUTPUT("HDMI1"),
SND_SOC_DAPM_MIXER(SOF_DMA_DL1, SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER(SOF_DMA_DL2, SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER(SOF_DMA_UL1, SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER(SOF_DMA_UL2, SND_SOC_NOPM, 0, 0, NULL, 0),
};
static const struct snd_soc_dapm_route
mt8186_mt6366_rt1019_rt5682s_routes[] = {
/* SPK */
{ "Speakers", NULL, "Speaker" },
/* Headset */
{ "Headphone", NULL, "HPOL" },
{ "Headphone", NULL, "HPOR" },
{ "IN1P", NULL, "Headset Mic" },
/* HDMI */
{ "HDMI1", NULL, "TX" },
/* SOF Uplink */
{SOF_DMA_UL1, NULL, "UL1_CH1"},
{SOF_DMA_UL1, NULL, "UL1_CH2"},
{SOF_DMA_UL2, NULL, "UL2_CH1"},
{SOF_DMA_UL2, NULL, "UL2_CH2"},
/* SOF Downlink */
{"DSP_DL1_VIRT", NULL, SOF_DMA_DL1},
{"DSP_DL2_VIRT", NULL, SOF_DMA_DL2},
};
static const struct snd_kcontrol_new
mt8186_mt6366_rt1019_rt5682s_controls[] = {
SOC_DAPM_PIN_SWITCH("Speakers"),
SOC_DAPM_PIN_SWITCH("Headphone"),
SOC_DAPM_PIN_SWITCH("Headset Mic"),
SOC_DAPM_PIN_SWITCH("HDMI1"),
};
static struct snd_soc_card mt8186_mt6366_rt1019_rt5682s_soc_card = {
.name = "mt8186_rt1019_rt5682s",
.owner = THIS_MODULE,
.dai_link = mt8186_mt6366_rt1019_rt5682s_dai_links,
.num_links = ARRAY_SIZE(mt8186_mt6366_rt1019_rt5682s_dai_links),
.controls = mt8186_mt6366_rt1019_rt5682s_controls,
.num_controls = ARRAY_SIZE(mt8186_mt6366_rt1019_rt5682s_controls),
.dapm_widgets = mt8186_mt6366_rt1019_rt5682s_widgets,
.num_dapm_widgets = ARRAY_SIZE(mt8186_mt6366_rt1019_rt5682s_widgets),
.dapm_routes = mt8186_mt6366_rt1019_rt5682s_routes,
.num_dapm_routes = ARRAY_SIZE(mt8186_mt6366_rt1019_rt5682s_routes),
.codec_conf = mt8186_mt6366_rt1019_rt5682s_codec_conf,
.num_configs = ARRAY_SIZE(mt8186_mt6366_rt1019_rt5682s_codec_conf),
};
static struct snd_soc_card mt8186_mt6366_rt5682s_max98360_soc_card = {
.name = "mt8186_rt5682s_max98360",
.owner = THIS_MODULE,
.dai_link = mt8186_mt6366_rt1019_rt5682s_dai_links,
.num_links = ARRAY_SIZE(mt8186_mt6366_rt1019_rt5682s_dai_links),
.controls = mt8186_mt6366_rt1019_rt5682s_controls,
.num_controls = ARRAY_SIZE(mt8186_mt6366_rt1019_rt5682s_controls),
.dapm_widgets = mt8186_mt6366_rt1019_rt5682s_widgets,
.num_dapm_widgets = ARRAY_SIZE(mt8186_mt6366_rt1019_rt5682s_widgets),
.dapm_routes = mt8186_mt6366_rt1019_rt5682s_routes,
.num_dapm_routes = ARRAY_SIZE(mt8186_mt6366_rt1019_rt5682s_routes),
.codec_conf = mt8186_mt6366_rt1019_rt5682s_codec_conf,
.num_configs = ARRAY_SIZE(mt8186_mt6366_rt1019_rt5682s_codec_conf),
};
static int mt8186_mt6366_rt1019_rt5682s_dev_probe(struct platform_device *pdev)
{
struct snd_soc_card *card;
struct snd_soc_dai_link *dai_link;
struct mtk_soc_card_data *soc_card_data;
struct mt8186_mt6366_rt1019_rt5682s_priv *mach_priv;
struct device_node *platform_node, *headset_codec, *playback_codec, *adsp_node;
int sof_on = 0;
int ret, i;
card = (struct snd_soc_card *)device_get_match_data(&pdev->dev);
if (!card)
return -EINVAL;
card->dev = &pdev->dev;
soc_card_data = devm_kzalloc(&pdev->dev, sizeof(*soc_card_data), GFP_KERNEL);
if (!soc_card_data)
return -ENOMEM;
mach_priv = devm_kzalloc(&pdev->dev, sizeof(*mach_priv), GFP_KERNEL);
if (!mach_priv)
return -ENOMEM;
soc_card_data->mach_priv = mach_priv;
mach_priv->dmic_sel = devm_gpiod_get_optional(&pdev->dev,
"dmic", GPIOD_OUT_LOW);
if (IS_ERR(mach_priv->dmic_sel)) {
dev_err(&pdev->dev, "DMIC gpio failed err=%ld\n",
PTR_ERR(mach_priv->dmic_sel));
return PTR_ERR(mach_priv->dmic_sel);
}
adsp_node = of_parse_phandle(pdev->dev.of_node, "mediatek,adsp", 0);
if (adsp_node) {
struct mtk_sof_priv *sof_priv;
sof_priv = devm_kzalloc(&pdev->dev, sizeof(*sof_priv), GFP_KERNEL);
if (!sof_priv) {
ret = -ENOMEM;
goto err_adsp_node;
}
sof_priv->conn_streams = g_sof_conn_streams;
sof_priv->num_streams = ARRAY_SIZE(g_sof_conn_streams);
sof_priv->sof_dai_link_fixup = mt8186_sof_dai_link_fixup;
soc_card_data->sof_priv = sof_priv;
card->probe = mtk_sof_card_probe;
card->late_probe = mtk_sof_card_late_probe;
if (!card->topology_shortname_created) {
snprintf(card->topology_shortname, 32, "sof-%s", card->name);
card->topology_shortname_created = true;
}
card->name = card->topology_shortname;
sof_on = 1;
} else {
dev_dbg(&pdev->dev, "Probe without adsp\n");
}
if (of_property_read_bool(pdev->dev.of_node, "mediatek,dai-link")) {
ret = mtk_sof_dailink_parse_of(card, pdev->dev.of_node,
"mediatek,dai-link",
mt8186_mt6366_rt1019_rt5682s_dai_links,
ARRAY_SIZE(mt8186_mt6366_rt1019_rt5682s_dai_links));
if (ret) {
dev_dbg(&pdev->dev, "Parse dai-link fail\n");
goto err_adsp_node;
}
} else {
if (!sof_on)
card->num_links = ARRAY_SIZE(mt8186_mt6366_rt1019_rt5682s_dai_links)
- ARRAY_SIZE(g_sof_conn_streams);
}
platform_node = of_parse_phandle(pdev->dev.of_node, "mediatek,platform", 0);
if (!platform_node) {
ret = -EINVAL;
dev_err_probe(&pdev->dev, ret, "Property 'platform' missing or invalid\n");
goto err_platform_node;
}
playback_codec = of_get_child_by_name(pdev->dev.of_node, "playback-codecs");
if (!playback_codec) {
ret = -EINVAL;
dev_err_probe(&pdev->dev, ret, "Property 'speaker-codecs' missing or invalid\n");
goto err_playback_codec;
}
headset_codec = of_get_child_by_name(pdev->dev.of_node, "headset-codec");
if (!headset_codec) {
ret = -EINVAL;
dev_err_probe(&pdev->dev, ret, "Property 'headset-codec' missing or invalid\n");
goto err_headset_codec;
}
for_each_card_prelinks(card, i, dai_link) {
ret = mt8186_mt6366_card_set_be_link(card, dai_link, playback_codec, "I2S3");
if (ret) {
dev_err_probe(&pdev->dev, ret, "%s set speaker_codec fail\n",
dai_link->name);
goto err_probe;
}
ret = mt8186_mt6366_card_set_be_link(card, dai_link, headset_codec, "I2S0");
if (ret) {
dev_err_probe(&pdev->dev, ret, "%s set headset_codec fail\n",
dai_link->name);
goto err_probe;
}
ret = mt8186_mt6366_card_set_be_link(card, dai_link, headset_codec, "I2S1");
if (ret) {
dev_err_probe(&pdev->dev, ret, "%s set headset_codec fail\n",
dai_link->name);
goto err_probe;
}
if (!strncmp(dai_link->name, "AFE_SOF", strlen("AFE_SOF")) && sof_on)
dai_link->platforms->of_node = adsp_node;
if (!dai_link->platforms->name && !dai_link->platforms->of_node)
dai_link->platforms->of_node = platform_node;
}
snd_soc_card_set_drvdata(card, soc_card_data);
ret = mt8186_afe_gpio_init(&pdev->dev);
if (ret) {
dev_err_probe(&pdev->dev, ret, "%s init gpio error\n", __func__);
goto err_probe;
}
ret = devm_snd_soc_register_card(&pdev->dev, card);
if (ret)
dev_err_probe(&pdev->dev, ret, "%s snd_soc_register_card fail\n", __func__);
err_probe:
of_node_put(headset_codec);
err_headset_codec:
of_node_put(playback_codec);
err_playback_codec:
of_node_put(platform_node);
err_platform_node:
err_adsp_node:
of_node_put(adsp_node);
return ret;
}
#if IS_ENABLED(CONFIG_OF)
static const struct of_device_id mt8186_mt6366_rt1019_rt5682s_dt_match[] = {
{
.compatible = "mediatek,mt8186-mt6366-rt1019-rt5682s-sound",
.data = &mt8186_mt6366_rt1019_rt5682s_soc_card,
},
{
.compatible = "mediatek,mt8186-mt6366-rt5682s-max98360-sound",
.data = &mt8186_mt6366_rt5682s_max98360_soc_card,
},
{}
};
MODULE_DEVICE_TABLE(of, mt8186_mt6366_rt1019_rt5682s_dt_match);
#endif
static struct platform_driver mt8186_mt6366_rt1019_rt5682s_driver = {
.driver = {
.name = "mt8186_mt6366_rt1019_rt5682s",
#if IS_ENABLED(CONFIG_OF)
.of_match_table = mt8186_mt6366_rt1019_rt5682s_dt_match,
#endif
.pm = &snd_soc_pm_ops,
},
.probe = mt8186_mt6366_rt1019_rt5682s_dev_probe,
};
module_platform_driver(mt8186_mt6366_rt1019_rt5682s_driver);
/* Module information */
MODULE_DESCRIPTION("MT8186-MT6366-RT1019-RT5682S ALSA SoC machine driver");
MODULE_AUTHOR("Jiaxin Yu <[email protected]>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("mt8186_mt6366_rt1019_rt5682s soc card");
| linux-master | sound/soc/mediatek/mt8186/mt8186-mt6366-rt1019-rt5682s.c |
// SPDX-License-Identifier: GPL-2.0
//
// MediaTek ALSA SoC Audio DAI ADDA Control
//
// Copyright (c) 2022 MediaTek Inc.
// Author: Jiaxin Yu <[email protected]>
#include <linux/regmap.h>
#include <linux/delay.h>
#include "mt8186-afe-clk.h"
#include "mt8186-afe-common.h"
#include "mt8186-afe-gpio.h"
#include "mt8186-interconnection.h"
enum {
UL_IIR_SW = 0,
UL_IIR_5HZ,
UL_IIR_10HZ,
UL_IIR_25HZ,
UL_IIR_50HZ,
UL_IIR_75HZ,
};
enum {
AUDIO_SDM_LEVEL_MUTE = 0,
AUDIO_SDM_LEVEL_NORMAL = 0x1d,
/* if you change level normal */
/* you need to change formula of hp impedance and dc trim too */
};
enum {
AUDIO_SDM_2ND = 0,
AUDIO_SDM_3RD,
};
enum {
DELAY_DATA_MISO1 = 0,
DELAY_DATA_MISO2,
};
enum {
MTK_AFE_ADDA_DL_RATE_8K = 0,
MTK_AFE_ADDA_DL_RATE_11K = 1,
MTK_AFE_ADDA_DL_RATE_12K = 2,
MTK_AFE_ADDA_DL_RATE_16K = 3,
MTK_AFE_ADDA_DL_RATE_22K = 4,
MTK_AFE_ADDA_DL_RATE_24K = 5,
MTK_AFE_ADDA_DL_RATE_32K = 6,
MTK_AFE_ADDA_DL_RATE_44K = 7,
MTK_AFE_ADDA_DL_RATE_48K = 8,
MTK_AFE_ADDA_DL_RATE_96K = 9,
MTK_AFE_ADDA_DL_RATE_192K = 10,
};
enum {
MTK_AFE_ADDA_UL_RATE_8K = 0,
MTK_AFE_ADDA_UL_RATE_16K = 1,
MTK_AFE_ADDA_UL_RATE_32K = 2,
MTK_AFE_ADDA_UL_RATE_48K = 3,
MTK_AFE_ADDA_UL_RATE_96K = 4,
MTK_AFE_ADDA_UL_RATE_192K = 5,
MTK_AFE_ADDA_UL_RATE_48K_HD = 6,
};
#define SDM_AUTO_RESET_THRESHOLD 0x190000
struct mtk_afe_adda_priv {
int dl_rate;
int ul_rate;
};
static struct mtk_afe_adda_priv *get_adda_priv_by_name(struct mtk_base_afe *afe,
const char *name)
{
struct mt8186_afe_private *afe_priv = afe->platform_priv;
int dai_id;
if (strncmp(name, "aud_dac", 7) == 0 || strncmp(name, "aud_adc", 7) == 0)
dai_id = MT8186_DAI_ADDA;
else
return NULL;
return afe_priv->dai_priv[dai_id];
}
static unsigned int adda_dl_rate_transform(struct mtk_base_afe *afe,
unsigned int rate)
{
switch (rate) {
case 8000:
return MTK_AFE_ADDA_DL_RATE_8K;
case 11025:
return MTK_AFE_ADDA_DL_RATE_11K;
case 12000:
return MTK_AFE_ADDA_DL_RATE_12K;
case 16000:
return MTK_AFE_ADDA_DL_RATE_16K;
case 22050:
return MTK_AFE_ADDA_DL_RATE_22K;
case 24000:
return MTK_AFE_ADDA_DL_RATE_24K;
case 32000:
return MTK_AFE_ADDA_DL_RATE_32K;
case 44100:
return MTK_AFE_ADDA_DL_RATE_44K;
case 48000:
return MTK_AFE_ADDA_DL_RATE_48K;
case 96000:
return MTK_AFE_ADDA_DL_RATE_96K;
case 192000:
return MTK_AFE_ADDA_DL_RATE_192K;
default:
dev_dbg(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
__func__, rate);
}
return MTK_AFE_ADDA_DL_RATE_48K;
}
static unsigned int adda_ul_rate_transform(struct mtk_base_afe *afe,
unsigned int rate)
{
switch (rate) {
case 8000:
return MTK_AFE_ADDA_UL_RATE_8K;
case 16000:
return MTK_AFE_ADDA_UL_RATE_16K;
case 32000:
return MTK_AFE_ADDA_UL_RATE_32K;
case 48000:
return MTK_AFE_ADDA_UL_RATE_48K;
case 96000:
return MTK_AFE_ADDA_UL_RATE_96K;
case 192000:
return MTK_AFE_ADDA_UL_RATE_192K;
default:
dev_dbg(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
__func__, rate);
}
return MTK_AFE_ADDA_UL_RATE_48K;
}
/* dai component */
static const struct snd_kcontrol_new mtk_adda_dl_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN3, I_DL1_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1 Switch", AFE_CONN3, I_DL12_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN3, I_DL2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN3, I_DL3_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN3_1, I_DL4_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN3_1, I_DL5_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1 Switch", AFE_CONN3_1, I_DL6_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1 Switch", AFE_CONN3_1, I_DL8_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN3,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN3,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1 Switch", AFE_CONN3,
I_GAIN1_OUT_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1 Switch", AFE_CONN3,
I_PCM_1_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1 Switch", AFE_CONN3,
I_PCM_2_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH1 Switch", AFE_CONN3_1,
I_SRC_1_OUT_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("SRC_2_OUT_CH1 Switch", AFE_CONN3_1,
I_SRC_2_OUT_CH1, 1, 0),
};
static const struct snd_kcontrol_new mtk_adda_dl_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN4, I_DL1_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN4, I_DL1_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN4, I_DL12_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN4, I_DL2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN4, I_DL2_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN4, I_DL3_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN4, I_DL3_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN4_1, I_DL4_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2 Switch", AFE_CONN4_1, I_DL5_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2 Switch", AFE_CONN4_1, I_DL6_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2 Switch", AFE_CONN4_1, I_DL8_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN4,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN4,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2 Switch", AFE_CONN4,
I_GAIN1_OUT_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2 Switch", AFE_CONN4,
I_PCM_1_CAP_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2 Switch", AFE_CONN4,
I_PCM_2_CAP_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH2 Switch", AFE_CONN4_1,
I_SRC_1_OUT_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("SRC_2_OUT_CH2 Switch", AFE_CONN4_1,
I_SRC_2_OUT_CH2, 1, 0),
};
enum {
SUPPLY_SEQ_ADDA_AFE_ON,
SUPPLY_SEQ_ADDA_DL_ON,
SUPPLY_SEQ_ADDA_AUD_PAD_TOP,
SUPPLY_SEQ_ADDA_MTKAIF_CFG,
SUPPLY_SEQ_ADDA_FIFO,
SUPPLY_SEQ_ADDA_AP_DMIC,
SUPPLY_SEQ_ADDA_UL_ON,
};
static int mtk_adda_ul_src_dmic(struct mtk_base_afe *afe, int id)
{
unsigned int reg;
switch (id) {
case MT8186_DAI_ADDA:
case MT8186_DAI_AP_DMIC:
reg = AFE_ADDA_UL_SRC_CON0;
break;
default:
return -EINVAL;
}
/* dmic mode, 3.25M*/
regmap_update_bits(afe->regmap, reg,
DIGMIC_3P25M_1P625M_SEL_MASK_SFT, 0);
regmap_update_bits(afe->regmap, reg,
DMIC_LOW_POWER_CTL_MASK_SFT, 0);
/* turn on dmic, ch1, ch2 */
regmap_update_bits(afe->regmap, reg,
UL_SDM_3_LEVEL_MASK_SFT,
BIT(UL_SDM_3_LEVEL_SFT));
regmap_update_bits(afe->regmap, reg,
UL_MODE_3P25M_CH1_CTL_MASK_SFT,
BIT(UL_MODE_3P25M_CH1_CTL_SFT));
regmap_update_bits(afe->regmap, reg,
UL_MODE_3P25M_CH2_CTL_MASK_SFT,
BIT(UL_MODE_3P25M_CH2_CTL_SFT));
return 0;
}
static int mtk_adda_ul_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8186_afe_private *afe_priv = afe->platform_priv;
int mtkaif_dmic = afe_priv->mtkaif_dmic;
dev_dbg(afe->dev, "%s(), name %s, event 0x%x, mtkaif_dmic %d\n",
__func__, w->name, event, mtkaif_dmic);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
mt8186_afe_gpio_request(afe->dev, true, MT8186_DAI_ADDA, 1);
/* update setting to dmic */
if (mtkaif_dmic) {
/* mtkaif_rxif_data_mode = 1, dmic */
regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0,
0x1, 0x1);
/* dmic mode, 3.25M*/
regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0,
MTKAIF_RXIF_VOICE_MODE_MASK_SFT,
0x0);
mtk_adda_ul_src_dmic(afe, MT8186_DAI_ADDA);
}
break;
case SND_SOC_DAPM_POST_PMD:
/* should delayed 1/fs(smallest is 8k) = 125us before afe off */
usleep_range(125, 135);
mt8186_afe_gpio_request(afe->dev, false, MT8186_DAI_ADDA, 1);
break;
default:
break;
}
return 0;
}
static int mtk_adda_pad_top_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8186_afe_private *afe_priv = afe->platform_priv;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2_CLK_P2)
regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x39);
else
regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x31);
break;
default:
break;
}
return 0;
}
static int mtk_adda_mtkaif_cfg_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8186_afe_private *afe_priv = afe->platform_priv;
int delay_data;
int delay_cycle;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2_CLK_P2) {
/* set protocol 2 */
regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 0x10000);
/* mtkaif_rxif_clkinv_adc inverse */
regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_CFG0,
MTKAIF_RXIF_CLKINV_ADC_MASK_SFT,
BIT(MTKAIF_RXIF_CLKINV_ADC_SFT));
if (strcmp(w->name, "ADDA_MTKAIF_CFG") == 0) {
if (afe_priv->mtkaif_chosen_phase[0] < 0 &&
afe_priv->mtkaif_chosen_phase[1] < 0) {
dev_err(afe->dev,
"%s(), calib fail mtkaif_chosen_phase[0/1]:%d/%d\n",
__func__,
afe_priv->mtkaif_chosen_phase[0],
afe_priv->mtkaif_chosen_phase[1]);
break;
}
if (afe_priv->mtkaif_chosen_phase[0] < 0 ||
afe_priv->mtkaif_chosen_phase[1] < 0) {
dev_err(afe->dev,
"%s(), skip delay setting mtkaif_chosen_phase[0/1]:%d/%d\n",
__func__,
afe_priv->mtkaif_chosen_phase[0],
afe_priv->mtkaif_chosen_phase[1]);
break;
}
}
/* set delay for ch12 */
if (afe_priv->mtkaif_phase_cycle[0] >=
afe_priv->mtkaif_phase_cycle[1]) {
delay_data = DELAY_DATA_MISO1;
delay_cycle = afe_priv->mtkaif_phase_cycle[0] -
afe_priv->mtkaif_phase_cycle[1];
} else {
delay_data = DELAY_DATA_MISO2;
delay_cycle = afe_priv->mtkaif_phase_cycle[1] -
afe_priv->mtkaif_phase_cycle[0];
}
regmap_update_bits(afe->regmap,
AFE_ADDA_MTKAIF_RX_CFG2,
MTKAIF_RXIF_DELAY_DATA_MASK_SFT,
delay_data <<
MTKAIF_RXIF_DELAY_DATA_SFT);
regmap_update_bits(afe->regmap,
AFE_ADDA_MTKAIF_RX_CFG2,
MTKAIF_RXIF_DELAY_CYCLE_MASK_SFT,
delay_cycle <<
MTKAIF_RXIF_DELAY_CYCLE_SFT);
} else if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2) {
regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 0x10000);
} else {
regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 0);
}
break;
default:
break;
}
return 0;
}
static int mtk_adda_dl_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
__func__, w->name, event);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
mt8186_afe_gpio_request(afe->dev, true, MT8186_DAI_ADDA, 0);
break;
case SND_SOC_DAPM_POST_PMD:
/* should delayed 1/fs(smallest is 8k) = 125us before afe off */
usleep_range(125, 135);
mt8186_afe_gpio_request(afe->dev, false, MT8186_DAI_ADDA, 0);
break;
default:
break;
}
return 0;
}
static int mt8186_adda_dmic_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8186_afe_private *afe_priv = afe->platform_priv;
ucontrol->value.integer.value[0] = afe_priv->mtkaif_dmic;
return 0;
}
static int mt8186_adda_dmic_set(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8186_afe_private *afe_priv = afe->platform_priv;
int dmic_on;
dmic_on = ucontrol->value.integer.value[0];
dev_dbg(afe->dev, "%s(), kcontrol name %s, dmic_on %d\n",
__func__, kcontrol->id.name, dmic_on);
if (afe_priv->mtkaif_dmic == dmic_on)
return 0;
afe_priv->mtkaif_dmic = dmic_on;
return 1;
}
static const struct snd_kcontrol_new mtk_adda_controls[] = {
SOC_SINGLE("ADDA_DL_GAIN", AFE_ADDA_DL_SRC2_CON1,
DL_2_GAIN_CTL_PRE_SFT, DL_2_GAIN_CTL_PRE_MASK, 0),
SOC_SINGLE_BOOL_EXT("MTKAIF_DMIC Switch", 0,
mt8186_adda_dmic_get, mt8186_adda_dmic_set),
};
/* ADDA UL MUX */
enum {
ADDA_UL_MUX_MTKAIF = 0,
ADDA_UL_MUX_AP_DMIC,
ADDA_UL_MUX_MASK = 0x1,
};
static const char * const adda_ul_mux_map[] = {
"MTKAIF", "AP_DMIC"
};
static int adda_ul_map_value[] = {
ADDA_UL_MUX_MTKAIF,
ADDA_UL_MUX_AP_DMIC,
};
static SOC_VALUE_ENUM_SINGLE_DECL(adda_ul_mux_map_enum,
SND_SOC_NOPM,
0,
ADDA_UL_MUX_MASK,
adda_ul_mux_map,
adda_ul_map_value);
static const struct snd_kcontrol_new adda_ul_mux_control =
SOC_DAPM_ENUM("ADDA_UL_MUX Select", adda_ul_mux_map_enum);
static const struct snd_soc_dapm_widget mtk_dai_adda_widgets[] = {
/* inter-connections */
SND_SOC_DAPM_MIXER("ADDA_DL_CH1", SND_SOC_NOPM, 0, 0,
mtk_adda_dl_ch1_mix,
ARRAY_SIZE(mtk_adda_dl_ch1_mix)),
SND_SOC_DAPM_MIXER("ADDA_DL_CH2", SND_SOC_NOPM, 0, 0,
mtk_adda_dl_ch2_mix,
ARRAY_SIZE(mtk_adda_dl_ch2_mix)),
SND_SOC_DAPM_SUPPLY_S("ADDA Enable", SUPPLY_SEQ_ADDA_AFE_ON,
AFE_ADDA_UL_DL_CON0, ADDA_AFE_ON_SFT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ADDA Playback Enable", SUPPLY_SEQ_ADDA_DL_ON,
AFE_ADDA_DL_SRC2_CON0,
DL_2_SRC_ON_CTL_PRE_SFT, 0,
mtk_adda_dl_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("ADDA Capture Enable", SUPPLY_SEQ_ADDA_UL_ON,
AFE_ADDA_UL_SRC_CON0,
UL_SRC_ON_CTL_SFT, 0,
mtk_adda_ul_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("AUD_PAD_TOP", SUPPLY_SEQ_ADDA_AUD_PAD_TOP,
0, 0, 0,
mtk_adda_pad_top_event,
SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_SUPPLY_S("ADDA_MTKAIF_CFG", SUPPLY_SEQ_ADDA_MTKAIF_CFG,
SND_SOC_NOPM, 0, 0,
mtk_adda_mtkaif_cfg_event,
SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_SUPPLY_S("AP_DMIC_EN", SUPPLY_SEQ_ADDA_AP_DMIC,
AFE_ADDA_UL_SRC_CON0,
UL_AP_DMIC_ON_SFT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ADDA_FIFO", SUPPLY_SEQ_ADDA_FIFO,
AFE_ADDA_UL_DL_CON0,
AFE_ADDA_FIFO_AUTO_RST_SFT, 1,
NULL, 0),
SND_SOC_DAPM_MUX("ADDA_UL_Mux", SND_SOC_NOPM, 0, 0,
&adda_ul_mux_control),
SND_SOC_DAPM_INPUT("AP_DMIC_INPUT"),
/* clock */
SND_SOC_DAPM_CLOCK_SUPPLY("top_mux_audio_h"),
SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_clk"),
SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_hires_clk"),
SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_predis_clk"),
SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc_clk"),
SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc_hires_clk"),
};
#define HIRES_THRESHOLD 48000
static int mtk_afe_dac_hires_connect(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_dapm_widget *w = source;
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mtk_afe_adda_priv *adda_priv;
adda_priv = get_adda_priv_by_name(afe, w->name);
if (!adda_priv) {
dev_err(afe->dev, "%s(), adda_priv == NULL", __func__);
return 0;
}
return (adda_priv->dl_rate > HIRES_THRESHOLD) ? 1 : 0;
}
static int mtk_afe_adc_hires_connect(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_dapm_widget *w = source;
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mtk_afe_adda_priv *adda_priv;
adda_priv = get_adda_priv_by_name(afe, w->name);
if (!adda_priv) {
dev_err(afe->dev, "%s(), adda_priv == NULL", __func__);
return 0;
}
return (adda_priv->ul_rate > HIRES_THRESHOLD) ? 1 : 0;
}
static const struct snd_soc_dapm_route mtk_dai_adda_routes[] = {
/* playback */
{"ADDA_DL_CH1", "DL1_CH1 Switch", "DL1"},
{"ADDA_DL_CH2", "DL1_CH1 Switch", "DL1"},
{"ADDA_DL_CH2", "DL1_CH2 Switch", "DL1"},
{"ADDA_DL_CH1", "DL12_CH1 Switch", "DL12"},
{"ADDA_DL_CH2", "DL12_CH2 Switch", "DL12"},
{"ADDA_DL_CH1", "DL6_CH1 Switch", "DL6"},
{"ADDA_DL_CH2", "DL6_CH2 Switch", "DL6"},
{"ADDA_DL_CH1", "DL8_CH1 Switch", "DL8"},
{"ADDA_DL_CH2", "DL8_CH2 Switch", "DL8"},
{"ADDA_DL_CH1", "DL2_CH1 Switch", "DL2"},
{"ADDA_DL_CH2", "DL2_CH1 Switch", "DL2"},
{"ADDA_DL_CH2", "DL2_CH2 Switch", "DL2"},
{"ADDA_DL_CH1", "DL3_CH1 Switch", "DL3"},
{"ADDA_DL_CH2", "DL3_CH1 Switch", "DL3"},
{"ADDA_DL_CH2", "DL3_CH2 Switch", "DL3"},
{"ADDA_DL_CH1", "DL4_CH1 Switch", "DL4"},
{"ADDA_DL_CH2", "DL4_CH2 Switch", "DL4"},
{"ADDA_DL_CH1", "DL5_CH1 Switch", "DL5"},
{"ADDA_DL_CH2", "DL5_CH2 Switch", "DL5"},
{"ADDA Playback", NULL, "ADDA_DL_CH1"},
{"ADDA Playback", NULL, "ADDA_DL_CH2"},
{"ADDA Playback", NULL, "ADDA Enable"},
{"ADDA Playback", NULL, "ADDA Playback Enable"},
/* capture */
{"ADDA_UL_Mux", "MTKAIF", "ADDA Capture"},
{"ADDA_UL_Mux", "AP_DMIC", "AP DMIC Capture"},
{"ADDA Capture", NULL, "ADDA Enable"},
{"ADDA Capture", NULL, "ADDA Capture Enable"},
{"ADDA Capture", NULL, "AUD_PAD_TOP"},
{"ADDA Capture", NULL, "ADDA_MTKAIF_CFG"},
{"AP DMIC Capture", NULL, "ADDA Enable"},
{"AP DMIC Capture", NULL, "ADDA Capture Enable"},
{"AP DMIC Capture", NULL, "ADDA_FIFO"},
{"AP DMIC Capture", NULL, "AP_DMIC_EN"},
{"AP DMIC Capture", NULL, "AP_DMIC_INPUT"},
/* clk */
{"ADDA Playback", NULL, "aud_dac_clk"},
{"ADDA Playback", NULL, "aud_dac_predis_clk"},
{"ADDA Playback", NULL, "aud_dac_hires_clk", mtk_afe_dac_hires_connect},
{"ADDA Capture Enable", NULL, "aud_adc_clk"},
{"ADDA Capture Enable", NULL, "aud_adc_hires_clk",
mtk_afe_adc_hires_connect},
/* hires source from apll1 */
{"top_mux_audio_h", NULL, APLL2_W_NAME},
{"aud_dac_hires_clk", NULL, "top_mux_audio_h"},
{"aud_adc_hires_clk", NULL, "top_mux_audio_h"},
};
/* dai ops */
static int mtk_dai_adda_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8186_afe_private *afe_priv = afe->platform_priv;
unsigned int rate = params_rate(params);
int id = dai->id;
struct mtk_afe_adda_priv *adda_priv = afe_priv->dai_priv[id];
dev_dbg(afe->dev, "%s(), id %d, stream %d, rate %d\n",
__func__, id, substream->stream, rate);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
unsigned int dl_src2_con0;
unsigned int dl_src2_con1;
adda_priv->dl_rate = rate;
/* set sampling rate */
dl_src2_con0 = adda_dl_rate_transform(afe, rate) <<
DL_2_INPUT_MODE_CTL_SFT;
/* set output mode, UP_SAMPLING_RATE_X8 */
dl_src2_con0 |= (0x3 << DL_2_OUTPUT_SEL_CTL_SFT);
/* turn off mute function */
dl_src2_con0 |= BIT(DL_2_MUTE_CH2_OFF_CTL_PRE_SFT);
dl_src2_con0 |= BIT(DL_2_MUTE_CH1_OFF_CTL_PRE_SFT);
/* set voice input data if input sample rate is 8k or 16k */
if (rate == 8000 || rate == 16000)
dl_src2_con0 |= BIT(DL_2_VOICE_MODE_CTL_PRE_SFT);
/* SA suggest apply -0.3db to audio/speech path */
dl_src2_con1 = MTK_AFE_ADDA_DL_GAIN_NORMAL <<
DL_2_GAIN_CTL_PRE_SFT;
/* turn on down-link gain */
dl_src2_con0 |= BIT(DL_2_GAIN_ON_CTL_PRE_SFT);
if (id == MT8186_DAI_ADDA) {
/* clean predistortion */
regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON0, 0);
regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON1, 0);
regmap_write(afe->regmap,
AFE_ADDA_DL_SRC2_CON0, dl_src2_con0);
regmap_write(afe->regmap,
AFE_ADDA_DL_SRC2_CON1, dl_src2_con1);
/* set sdm gain */
regmap_update_bits(afe->regmap,
AFE_ADDA_DL_SDM_DCCOMP_CON,
ATTGAIN_CTL_MASK_SFT,
AUDIO_SDM_LEVEL_NORMAL <<
ATTGAIN_CTL_SFT);
/* Use new 2nd sdm */
regmap_update_bits(afe->regmap,
AFE_ADDA_DL_SDM_DITHER_CON,
AFE_DL_SDM_DITHER_64TAP_EN_MASK_SFT,
BIT(AFE_DL_SDM_DITHER_64TAP_EN_SFT));
regmap_update_bits(afe->regmap,
AFE_ADDA_DL_SDM_AUTO_RESET_CON,
AFE_DL_USE_NEW_2ND_SDM_MASK_SFT,
BIT(AFE_DL_USE_NEW_2ND_SDM_SFT));
regmap_update_bits(afe->regmap,
AFE_ADDA_DL_SDM_DCCOMP_CON,
USE_3RD_SDM_MASK_SFT,
AUDIO_SDM_2ND << USE_3RD_SDM_SFT);
/* sdm auto reset */
regmap_write(afe->regmap,
AFE_ADDA_DL_SDM_AUTO_RESET_CON,
SDM_AUTO_RESET_THRESHOLD);
regmap_update_bits(afe->regmap,
AFE_ADDA_DL_SDM_AUTO_RESET_CON,
SDM_AUTO_RESET_TEST_ON_MASK_SFT,
BIT(SDM_AUTO_RESET_TEST_ON_SFT));
}
} else {
unsigned int ul_src_con0 = 0;
unsigned int voice_mode = adda_ul_rate_transform(afe, rate);
adda_priv->ul_rate = rate;
ul_src_con0 |= (voice_mode << 17) & (0x7 << 17);
/* enable iir */
ul_src_con0 |= (1 << UL_IIR_ON_TMP_CTL_SFT) &
UL_IIR_ON_TMP_CTL_MASK_SFT;
ul_src_con0 |= (UL_IIR_SW << UL_IIRMODE_CTL_SFT) &
UL_IIRMODE_CTL_MASK_SFT;
switch (id) {
case MT8186_DAI_ADDA:
case MT8186_DAI_AP_DMIC:
/* 35Hz @ 48k */
regmap_write(afe->regmap,
AFE_ADDA_IIR_COEF_02_01, 0);
regmap_write(afe->regmap,
AFE_ADDA_IIR_COEF_04_03, 0x3fb8);
regmap_write(afe->regmap,
AFE_ADDA_IIR_COEF_06_05, 0x3fb80000);
regmap_write(afe->regmap,
AFE_ADDA_IIR_COEF_08_07, 0x3fb80000);
regmap_write(afe->regmap,
AFE_ADDA_IIR_COEF_10_09, 0xc048);
regmap_write(afe->regmap,
AFE_ADDA_UL_SRC_CON0, ul_src_con0);
/* Using Internal ADC */
regmap_update_bits(afe->regmap, AFE_ADDA_TOP_CON0, BIT(0), 0);
/* mtkaif_rxif_data_mode = 0, amic */
regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0, BIT(0), 0);
break;
default:
break;
}
/* ap dmic */
switch (id) {
case MT8186_DAI_AP_DMIC:
mtk_adda_ul_src_dmic(afe, id);
break;
default:
break;
}
}
return 0;
}
static const struct snd_soc_dai_ops mtk_dai_adda_ops = {
.hw_params = mtk_dai_adda_hw_params,
};
/* dai driver */
#define MTK_ADDA_PLAYBACK_RATES (SNDRV_PCM_RATE_8000_48000 |\
SNDRV_PCM_RATE_96000 |\
SNDRV_PCM_RATE_192000)
#define MTK_ADDA_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 |\
SNDRV_PCM_RATE_48000 |\
SNDRV_PCM_RATE_96000 |\
SNDRV_PCM_RATE_192000)
#define MTK_ADDA_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver mtk_dai_adda_driver[] = {
{
.name = "ADDA",
.id = MT8186_DAI_ADDA,
.playback = {
.stream_name = "ADDA Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_ADDA_PLAYBACK_RATES,
.formats = MTK_ADDA_FORMATS,
},
.capture = {
.stream_name = "ADDA Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_ADDA_CAPTURE_RATES,
.formats = MTK_ADDA_FORMATS,
},
.ops = &mtk_dai_adda_ops,
},
{
.name = "AP_DMIC",
.id = MT8186_DAI_AP_DMIC,
.capture = {
.stream_name = "AP DMIC Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_ADDA_CAPTURE_RATES,
.formats = MTK_ADDA_FORMATS,
},
.ops = &mtk_dai_adda_ops,
},
};
int mt8186_dai_adda_register(struct mtk_base_afe *afe)
{
struct mtk_base_afe_dai *dai;
struct mt8186_afe_private *afe_priv = afe->platform_priv;
int ret;
dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
if (!dai)
return -ENOMEM;
list_add(&dai->list, &afe->sub_dais);
dai->dai_drivers = mtk_dai_adda_driver;
dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_adda_driver);
dai->controls = mtk_adda_controls;
dai->num_controls = ARRAY_SIZE(mtk_adda_controls);
dai->dapm_widgets = mtk_dai_adda_widgets;
dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_adda_widgets);
dai->dapm_routes = mtk_dai_adda_routes;
dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_adda_routes);
/* set dai priv */
ret = mt8186_dai_set_priv(afe, MT8186_DAI_ADDA,
sizeof(struct mtk_afe_adda_priv), NULL);
if (ret)
return ret;
/* ap dmic priv share with adda */
afe_priv->dai_priv[MT8186_DAI_AP_DMIC] =
afe_priv->dai_priv[MT8186_DAI_ADDA];
return 0;
}
| linux-master | sound/soc/mediatek/mt8186/mt8186-dai-adda.c |
// SPDX-License-Identifier: GPL-2.0
//
// mt8186-mt6366-common.c
// -- MT8186 MT6366 ALSA common driver
//
// Copyright (c) 2022 MediaTek Inc.
// Author: Jiaxin Yu <[email protected]>
//
#include <sound/soc.h>
#include "../../codecs/mt6358.h"
#include "../common/mtk-afe-platform-driver.h"
#include "mt8186-afe-common.h"
#include "mt8186-mt6366-common.h"
int mt8186_mt6366_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_component *cmpnt_afe =
snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
struct snd_soc_component *cmpnt_codec =
asoc_rtd_to_codec(rtd, 0)->component;
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt_afe);
struct mt8186_afe_private *afe_priv = afe->platform_priv;
struct snd_soc_dapm_context *dapm = &rtd->card->dapm;
int ret;
/* set mtkaif protocol */
mt6358_set_mtkaif_protocol(cmpnt_codec,
MT6358_MTKAIF_PROTOCOL_1);
afe_priv->mtkaif_protocol = MT6358_MTKAIF_PROTOCOL_1;
ret = snd_soc_dapm_sync(dapm);
if (ret) {
dev_err(rtd->dev, "failed to snd_soc_dapm_sync\n");
return ret;
}
return 0;
}
EXPORT_SYMBOL_GPL(mt8186_mt6366_init);
int mt8186_mt6366_card_set_be_link(struct snd_soc_card *card,
struct snd_soc_dai_link *link,
struct device_node *node,
char *link_name)
{
int ret;
if (node && strcmp(link->name, link_name) == 0) {
ret = snd_soc_of_get_dai_link_codecs(card->dev, node, link);
if (ret < 0)
return dev_err_probe(card->dev, ret, "get dai link codecs fail\n");
}
return 0;
}
EXPORT_SYMBOL_GPL(mt8186_mt6366_card_set_be_link);
| linux-master | sound/soc/mediatek/mt8186/mt8186-mt6366-common.c |
// SPDX-License-Identifier: GPL-2.0
//
// MediaTek ALSA SoC Audio DAI I2S Control
//
// Copyright (c) 2022 MediaTek Inc.
// Author: Jiaxin Yu <[email protected]>
#include <linux/bitops.h>
#include <linux/regmap.h>
#include <sound/pcm_params.h>
#include "mt8186-afe-clk.h"
#include "mt8186-afe-common.h"
#include "mt8186-afe-gpio.h"
#include "mt8186-interconnection.h"
enum {
I2S_FMT_EIAJ = 0,
I2S_FMT_I2S = 1,
};
enum {
I2S_WLEN_16_BIT = 0,
I2S_WLEN_32_BIT = 1,
};
enum {
I2S_HD_NORMAL = 0,
I2S_HD_LOW_JITTER = 1,
};
enum {
I2S1_SEL_O28_O29 = 0,
I2S1_SEL_O03_O04 = 1,
};
enum {
I2S_IN_PAD_CONNSYS = 0,
I2S_IN_PAD_IO_MUX = 1,
};
struct mtk_afe_i2s_priv {
int id;
int rate; /* for determine which apll to use */
int low_jitter_en;
int master; /* only i2s0 has slave mode*/
int share_i2s_id;
int mclk_id;
int mclk_rate;
int mclk_apll;
};
static unsigned int get_i2s_wlen(snd_pcm_format_t format)
{
return snd_pcm_format_physical_width(format) <= 16 ?
I2S_WLEN_16_BIT : I2S_WLEN_32_BIT;
}
#define MTK_AFE_I2S0_KCONTROL_NAME "I2S0_HD_Mux"
#define MTK_AFE_I2S1_KCONTROL_NAME "I2S1_HD_Mux"
#define MTK_AFE_I2S2_KCONTROL_NAME "I2S2_HD_Mux"
#define MTK_AFE_I2S3_KCONTROL_NAME "I2S3_HD_Mux"
#define MTK_AFE_I2S0_SRC_KCONTROL_NAME "I2S0_SRC_Mux"
#define I2S0_HD_EN_W_NAME "I2S0_HD_EN"
#define I2S1_HD_EN_W_NAME "I2S1_HD_EN"
#define I2S2_HD_EN_W_NAME "I2S2_HD_EN"
#define I2S3_HD_EN_W_NAME "I2S3_HD_EN"
#define I2S0_MCLK_EN_W_NAME "I2S0_MCLK_EN"
#define I2S1_MCLK_EN_W_NAME "I2S1_MCLK_EN"
#define I2S2_MCLK_EN_W_NAME "I2S2_MCLK_EN"
#define I2S3_MCLK_EN_W_NAME "I2S3_MCLK_EN"
static int get_i2s_id_by_name(struct mtk_base_afe *afe,
const char *name)
{
if (strncmp(name, "I2S0", 4) == 0)
return MT8186_DAI_I2S_0;
else if (strncmp(name, "I2S1", 4) == 0)
return MT8186_DAI_I2S_1;
else if (strncmp(name, "I2S2", 4) == 0)
return MT8186_DAI_I2S_2;
else if (strncmp(name, "I2S3", 4) == 0)
return MT8186_DAI_I2S_3;
return -EINVAL;
}
static struct mtk_afe_i2s_priv *get_i2s_priv_by_name(struct mtk_base_afe *afe,
const char *name)
{
struct mt8186_afe_private *afe_priv = afe->platform_priv;
int dai_id = get_i2s_id_by_name(afe, name);
if (dai_id < 0)
return NULL;
return afe_priv->dai_priv[dai_id];
}
/* low jitter control */
static const char * const mt8186_i2s_hd_str[] = {
"Normal", "Low_Jitter"
};
static const struct soc_enum mt8186_i2s_enum[] = {
SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt8186_i2s_hd_str),
mt8186_i2s_hd_str),
};
static int mt8186_i2s_hd_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mtk_afe_i2s_priv *i2s_priv;
i2s_priv = get_i2s_priv_by_name(afe, kcontrol->id.name);
ucontrol->value.integer.value[0] = i2s_priv->low_jitter_en;
return 0;
}
static int mt8186_i2s_hd_set(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mtk_afe_i2s_priv *i2s_priv;
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
int hd_en;
if (ucontrol->value.enumerated.item[0] >= e->items)
return -EINVAL;
hd_en = ucontrol->value.integer.value[0];
dev_dbg(afe->dev, "%s(), kcontrol name %s, hd_en %d\n",
__func__, kcontrol->id.name, hd_en);
i2s_priv = get_i2s_priv_by_name(afe, kcontrol->id.name);
if (i2s_priv->low_jitter_en == hd_en)
return 0;
i2s_priv->low_jitter_en = hd_en;
return 1;
}
static const struct snd_kcontrol_new mtk_dai_i2s_controls[] = {
SOC_ENUM_EXT(MTK_AFE_I2S0_KCONTROL_NAME, mt8186_i2s_enum[0],
mt8186_i2s_hd_get, mt8186_i2s_hd_set),
SOC_ENUM_EXT(MTK_AFE_I2S1_KCONTROL_NAME, mt8186_i2s_enum[0],
mt8186_i2s_hd_get, mt8186_i2s_hd_set),
SOC_ENUM_EXT(MTK_AFE_I2S2_KCONTROL_NAME, mt8186_i2s_enum[0],
mt8186_i2s_hd_get, mt8186_i2s_hd_set),
SOC_ENUM_EXT(MTK_AFE_I2S3_KCONTROL_NAME, mt8186_i2s_enum[0],
mt8186_i2s_hd_get, mt8186_i2s_hd_set),
};
/* dai component */
/* i2s virtual mux to output widget */
static const char * const i2s_mux_map[] = {
"Normal", "Dummy_Widget",
};
static int i2s_mux_map_value[] = {
0, 1,
};
static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(i2s_mux_map_enum,
SND_SOC_NOPM,
0,
1,
i2s_mux_map,
i2s_mux_map_value);
static const struct snd_kcontrol_new i2s0_in_mux_control =
SOC_DAPM_ENUM("I2S0 In Select", i2s_mux_map_enum);
static const struct snd_kcontrol_new i2s1_out_mux_control =
SOC_DAPM_ENUM("I2S1 Out Select", i2s_mux_map_enum);
static const struct snd_kcontrol_new i2s2_in_mux_control =
SOC_DAPM_ENUM("I2S2 In Select", i2s_mux_map_enum);
static const struct snd_kcontrol_new i2s3_out_mux_control =
SOC_DAPM_ENUM("I2S3 Out Select", i2s_mux_map_enum);
/* i2s in lpbk */
static const char * const i2s_lpbk_mux_map[] = {
"Normal", "Lpbk",
};
static int i2s_lpbk_mux_map_value[] = {
0, 1,
};
static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(i2s0_lpbk_mux_map_enum,
AFE_I2S_CON,
I2S_LOOPBACK_SFT,
1,
i2s_lpbk_mux_map,
i2s_lpbk_mux_map_value);
static const struct snd_kcontrol_new i2s0_lpbk_mux_control =
SOC_DAPM_ENUM("I2S Lpbk Select", i2s0_lpbk_mux_map_enum);
static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(i2s2_lpbk_mux_map_enum,
AFE_I2S_CON2,
I2S3_LOOPBACK_SFT,
1,
i2s_lpbk_mux_map,
i2s_lpbk_mux_map_value);
static const struct snd_kcontrol_new i2s2_lpbk_mux_control =
SOC_DAPM_ENUM("I2S Lpbk Select", i2s2_lpbk_mux_map_enum);
/* interconnection */
static const struct snd_kcontrol_new mtk_i2s3_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN0,
I_DL1_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN0,
I_DL2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN0,
I_DL3_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1 Switch", AFE_CONN0,
I_DL12_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH3 Switch", AFE_CONN0,
I_DL12_CH3, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1 Switch", AFE_CONN0_1,
I_DL6_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN0_1,
I_DL4_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN0_1,
I_DL5_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1 Switch", AFE_CONN0_1,
I_DL8_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1 Switch", AFE_CONN0,
I_GAIN1_OUT_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN0,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN0,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3 Switch", AFE_CONN0,
I_ADDA_UL_CH3, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1 Switch", AFE_CONN0,
I_PCM_1_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH1 Switch", AFE_CONN0_1,
I_SRC_1_OUT_CH1, 1, 0),
};
static const struct snd_kcontrol_new mtk_i2s3_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN1,
I_DL1_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN1,
I_DL2_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN1,
I_DL3_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN1,
I_DL12_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH4 Switch", AFE_CONN1,
I_DL12_CH4, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2 Switch", AFE_CONN1_1,
I_DL6_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN1_1,
I_DL4_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2 Switch", AFE_CONN1_1,
I_DL5_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2 Switch", AFE_CONN1_1,
I_DL8_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2 Switch", AFE_CONN1,
I_GAIN1_OUT_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN1,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN1,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3 Switch", AFE_CONN1,
I_ADDA_UL_CH3, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2 Switch", AFE_CONN1,
I_PCM_1_CAP_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2 Switch", AFE_CONN1,
I_PCM_2_CAP_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH2 Switch", AFE_CONN1_1,
I_SRC_1_OUT_CH2, 1, 0),
};
static const struct snd_kcontrol_new mtk_i2s1_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN28,
I_DL1_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN28,
I_DL2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN28,
I_DL3_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1 Switch", AFE_CONN28,
I_DL12_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH3 Switch", AFE_CONN28,
I_DL12_CH3, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1 Switch", AFE_CONN28_1,
I_DL6_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN28_1,
I_DL4_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN28_1,
I_DL5_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1 Switch", AFE_CONN28_1,
I_DL8_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1 Switch", AFE_CONN28,
I_GAIN1_OUT_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN28,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1 Switch", AFE_CONN28,
I_PCM_1_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH1 Switch", AFE_CONN28_1,
I_SRC_1_OUT_CH1, 1, 0),
};
static const struct snd_kcontrol_new mtk_i2s1_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN29,
I_DL1_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN29,
I_DL2_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN29,
I_DL3_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN29,
I_DL12_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH4 Switch", AFE_CONN29,
I_DL12_CH4, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2 Switch", AFE_CONN29_1,
I_DL6_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN29_1,
I_DL4_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2 Switch", AFE_CONN29_1,
I_DL5_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2 Switch", AFE_CONN29_1,
I_DL8_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2 Switch", AFE_CONN29,
I_GAIN1_OUT_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN29,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2 Switch", AFE_CONN29,
I_PCM_1_CAP_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2 Switch", AFE_CONN29,
I_PCM_2_CAP_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH2 Switch", AFE_CONN29_1,
I_SRC_1_OUT_CH2, 1, 0),
};
enum {
SUPPLY_SEQ_APLL,
SUPPLY_SEQ_I2S_MCLK_EN,
SUPPLY_SEQ_I2S_HD_EN,
SUPPLY_SEQ_I2S_EN,
};
static int mtk_i2s_en_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mtk_afe_i2s_priv *i2s_priv;
i2s_priv = get_i2s_priv_by_name(afe, w->name);
dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x\n",
__func__, w->name, event);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
mt8186_afe_gpio_request(afe->dev, true, i2s_priv->id, 0);
break;
case SND_SOC_DAPM_POST_PMD:
mt8186_afe_gpio_request(afe->dev, false, i2s_priv->id, 0);
break;
default:
break;
}
return 0;
}
static int mtk_apll_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x\n",
__func__, w->name, event);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
if (strcmp(w->name, APLL1_W_NAME) == 0)
mt8186_apll1_enable(afe);
else
mt8186_apll2_enable(afe);
break;
case SND_SOC_DAPM_POST_PMD:
if (strcmp(w->name, APLL1_W_NAME) == 0)
mt8186_apll1_disable(afe);
else
mt8186_apll2_disable(afe);
break;
default:
break;
}
return 0;
}
static int mtk_mclk_en_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mtk_afe_i2s_priv *i2s_priv;
dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x\n",
__func__, w->name, event);
i2s_priv = get_i2s_priv_by_name(afe, w->name);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
mt8186_mck_enable(afe, i2s_priv->mclk_id, i2s_priv->mclk_rate);
break;
case SND_SOC_DAPM_POST_PMD:
i2s_priv->mclk_rate = 0;
mt8186_mck_disable(afe, i2s_priv->mclk_id);
break;
default:
break;
}
return 0;
}
static const struct snd_soc_dapm_widget mtk_dai_i2s_widgets[] = {
SND_SOC_DAPM_INPUT("CONNSYS"),
SND_SOC_DAPM_MIXER("I2S1_CH1", SND_SOC_NOPM, 0, 0,
mtk_i2s1_ch1_mix,
ARRAY_SIZE(mtk_i2s1_ch1_mix)),
SND_SOC_DAPM_MIXER("I2S1_CH2", SND_SOC_NOPM, 0, 0,
mtk_i2s1_ch2_mix,
ARRAY_SIZE(mtk_i2s1_ch2_mix)),
SND_SOC_DAPM_MIXER("I2S3_CH1", SND_SOC_NOPM, 0, 0,
mtk_i2s3_ch1_mix,
ARRAY_SIZE(mtk_i2s3_ch1_mix)),
SND_SOC_DAPM_MIXER("I2S3_CH2", SND_SOC_NOPM, 0, 0,
mtk_i2s3_ch2_mix,
ARRAY_SIZE(mtk_i2s3_ch2_mix)),
/* i2s en*/
SND_SOC_DAPM_SUPPLY_S("I2S0_EN", SUPPLY_SEQ_I2S_EN,
AFE_I2S_CON, I2S_EN_SFT, 0,
mtk_i2s_en_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("I2S1_EN", SUPPLY_SEQ_I2S_EN,
AFE_I2S_CON1, I2S_EN_SFT, 0,
mtk_i2s_en_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("I2S2_EN", SUPPLY_SEQ_I2S_EN,
AFE_I2S_CON2, I2S_EN_SFT, 0,
mtk_i2s_en_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("I2S3_EN", SUPPLY_SEQ_I2S_EN,
AFE_I2S_CON3, I2S_EN_SFT, 0,
mtk_i2s_en_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
/* i2s hd en */
SND_SOC_DAPM_SUPPLY_S(I2S0_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
AFE_I2S_CON, I2S1_HD_EN_SFT, 0, NULL,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S(I2S1_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
AFE_I2S_CON1, I2S2_HD_EN_SFT, 0, NULL,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S(I2S2_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
AFE_I2S_CON2, I2S3_HD_EN_SFT, 0, NULL,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S(I2S3_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
AFE_I2S_CON3, I2S4_HD_EN_SFT, 0, NULL,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
/* i2s mclk en */
SND_SOC_DAPM_SUPPLY_S(I2S0_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
SND_SOC_NOPM, 0, 0,
mtk_mclk_en_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S(I2S1_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
SND_SOC_NOPM, 0, 0,
mtk_mclk_en_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S(I2S2_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
SND_SOC_NOPM, 0, 0,
mtk_mclk_en_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S(I2S3_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
SND_SOC_NOPM, 0, 0,
mtk_mclk_en_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
/* apll */
SND_SOC_DAPM_SUPPLY_S(APLL1_W_NAME, SUPPLY_SEQ_APLL,
SND_SOC_NOPM, 0, 0,
mtk_apll_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S(APLL2_W_NAME, SUPPLY_SEQ_APLL,
SND_SOC_NOPM, 0, 0,
mtk_apll_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
/* allow i2s on without codec on */
SND_SOC_DAPM_OUTPUT("I2S_DUMMY_OUT"),
SND_SOC_DAPM_MUX("I2S1_Out_Mux",
SND_SOC_NOPM, 0, 0, &i2s1_out_mux_control),
SND_SOC_DAPM_MUX("I2S3_Out_Mux",
SND_SOC_NOPM, 0, 0, &i2s3_out_mux_control),
SND_SOC_DAPM_INPUT("I2S_DUMMY_IN"),
SND_SOC_DAPM_MUX("I2S0_In_Mux",
SND_SOC_NOPM, 0, 0, &i2s0_in_mux_control),
SND_SOC_DAPM_MUX("I2S2_In_Mux",
SND_SOC_NOPM, 0, 0, &i2s2_in_mux_control),
/* i2s in lpbk */
SND_SOC_DAPM_MUX("I2S0_Lpbk_Mux",
SND_SOC_NOPM, 0, 0, &i2s0_lpbk_mux_control),
SND_SOC_DAPM_MUX("I2S2_Lpbk_Mux",
SND_SOC_NOPM, 0, 0, &i2s2_lpbk_mux_control),
};
static int mtk_afe_i2s_share_connect(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_dapm_widget *w = sink;
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mtk_afe_i2s_priv *i2s_priv;
i2s_priv = get_i2s_priv_by_name(afe, sink->name);
if (i2s_priv->share_i2s_id < 0)
return 0;
return i2s_priv->share_i2s_id == get_i2s_id_by_name(afe, source->name);
}
static int mtk_afe_i2s_hd_connect(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_dapm_widget *w = sink;
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mtk_afe_i2s_priv *i2s_priv;
i2s_priv = get_i2s_priv_by_name(afe, sink->name);
if (get_i2s_id_by_name(afe, sink->name) ==
get_i2s_id_by_name(afe, source->name))
return i2s_priv->low_jitter_en;
/* check if share i2s need hd en */
if (i2s_priv->share_i2s_id < 0)
return 0;
if (i2s_priv->share_i2s_id == get_i2s_id_by_name(afe, source->name))
return i2s_priv->low_jitter_en;
return 0;
}
static int mtk_afe_i2s_apll_connect(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_dapm_widget *w = sink;
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mtk_afe_i2s_priv *i2s_priv;
int cur_apll;
int i2s_need_apll;
i2s_priv = get_i2s_priv_by_name(afe, w->name);
/* which apll */
cur_apll = mt8186_get_apll_by_name(afe, source->name);
/* choose APLL from i2s rate */
i2s_need_apll = mt8186_get_apll_by_rate(afe, i2s_priv->rate);
return (i2s_need_apll == cur_apll) ? 1 : 0;
}
static int mtk_afe_i2s_mclk_connect(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_dapm_widget *w = sink;
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mtk_afe_i2s_priv *i2s_priv;
i2s_priv = get_i2s_priv_by_name(afe, sink->name);
if (get_i2s_id_by_name(afe, sink->name) ==
get_i2s_id_by_name(afe, source->name))
return (i2s_priv->mclk_rate > 0) ? 1 : 0;
/* check if share i2s need mclk */
if (i2s_priv->share_i2s_id < 0)
return 0;
if (i2s_priv->share_i2s_id == get_i2s_id_by_name(afe, source->name))
return (i2s_priv->mclk_rate > 0) ? 1 : 0;
return 0;
}
static int mtk_afe_mclk_apll_connect(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_dapm_widget *w = sink;
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mtk_afe_i2s_priv *i2s_priv;
int cur_apll;
i2s_priv = get_i2s_priv_by_name(afe, w->name);
/* which apll */
cur_apll = mt8186_get_apll_by_name(afe, source->name);
return (i2s_priv->mclk_apll == cur_apll) ? 1 : 0;
}
static const struct snd_soc_dapm_route mtk_dai_i2s_routes[] = {
{"Connsys I2S", NULL, "CONNSYS"},
/* i2s0 */
{"I2S0", NULL, "I2S0_EN"},
{"I2S0", NULL, "I2S1_EN", mtk_afe_i2s_share_connect},
{"I2S0", NULL, "I2S2_EN", mtk_afe_i2s_share_connect},
{"I2S0", NULL, "I2S3_EN", mtk_afe_i2s_share_connect},
{"I2S0", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S0", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S0", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S0", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{I2S0_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
{I2S0_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
{"I2S0", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S0", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S0", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S0", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{I2S0_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
{I2S0_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
/* i2s1 */
{"I2S1_CH1", "DL1_CH1 Switch", "DL1"},
{"I2S1_CH2", "DL1_CH2 Switch", "DL1"},
{"I2S1_CH1", "DL1_CH1 Switch", "DSP_DL1_VIRT"},
{"I2S1_CH2", "DL1_CH2 Switch", "DSP_DL1_VIRT"},
{"I2S1_CH1", "DL2_CH1 Switch", "DL2"},
{"I2S1_CH2", "DL2_CH2 Switch", "DL2"},
{"I2S1_CH1", "DL2_CH1 Switch", "DSP_DL2_VIRT"},
{"I2S1_CH2", "DL2_CH2 Switch", "DSP_DL2_VIRT"},
{"I2S1_CH1", "DL3_CH1 Switch", "DL3"},
{"I2S1_CH2", "DL3_CH2 Switch", "DL3"},
{"I2S1_CH1", "DL12_CH1 Switch", "DL12"},
{"I2S1_CH2", "DL12_CH2 Switch", "DL12"},
{"I2S1_CH1", "DL12_CH3 Switch", "DL12"},
{"I2S1_CH2", "DL12_CH4 Switch", "DL12"},
{"I2S1_CH1", "DL6_CH1 Switch", "DL6"},
{"I2S1_CH2", "DL6_CH2 Switch", "DL6"},
{"I2S1_CH1", "DL4_CH1 Switch", "DL4"},
{"I2S1_CH2", "DL4_CH2 Switch", "DL4"},
{"I2S1_CH1", "DL5_CH1 Switch", "DL5"},
{"I2S1_CH2", "DL5_CH2 Switch", "DL5"},
{"I2S1_CH1", "DL8_CH1 Switch", "DL8"},
{"I2S1_CH2", "DL8_CH2 Switch", "DL8"},
{"I2S1", NULL, "I2S1_CH1"},
{"I2S1", NULL, "I2S1_CH2"},
{"I2S1", NULL, "I2S0_EN", mtk_afe_i2s_share_connect},
{"I2S1", NULL, "I2S1_EN"},
{"I2S1", NULL, "I2S2_EN", mtk_afe_i2s_share_connect},
{"I2S1", NULL, "I2S3_EN", mtk_afe_i2s_share_connect},
{"I2S1", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S1", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S1", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S1", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{I2S1_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
{I2S1_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
{"I2S1", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S1", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S1", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S1", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{I2S1_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
{I2S1_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
/* i2s2 */
{"I2S2", NULL, "I2S0_EN", mtk_afe_i2s_share_connect},
{"I2S2", NULL, "I2S1_EN", mtk_afe_i2s_share_connect},
{"I2S2", NULL, "I2S2_EN"},
{"I2S2", NULL, "I2S3_EN", mtk_afe_i2s_share_connect},
{"I2S2", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S2", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S2", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S2", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{I2S2_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
{I2S2_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
{"I2S2", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S2", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S2", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S2", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{I2S2_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
{I2S2_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
/* i2s3 */
{"I2S3_CH1", "DL1_CH1 Switch", "DL1"},
{"I2S3_CH2", "DL1_CH2 Switch", "DL1"},
{"I2S3_CH1", "DL1_CH1 Switch", "DSP_DL1_VIRT"},
{"I2S3_CH2", "DL1_CH2 Switch", "DSP_DL1_VIRT"},
{"I2S3_CH1", "DL2_CH1 Switch", "DL2"},
{"I2S3_CH2", "DL2_CH2 Switch", "DL2"},
{"I2S3_CH1", "DL2_CH1 Switch", "DSP_DL2_VIRT"},
{"I2S3_CH2", "DL2_CH2 Switch", "DSP_DL2_VIRT"},
{"I2S3_CH1", "DL3_CH1 Switch", "DL3"},
{"I2S3_CH2", "DL3_CH2 Switch", "DL3"},
{"I2S3_CH1", "DL12_CH1 Switch", "DL12"},
{"I2S3_CH2", "DL12_CH2 Switch", "DL12"},
{"I2S3_CH1", "DL12_CH3 Switch", "DL12"},
{"I2S3_CH2", "DL12_CH4 Switch", "DL12"},
{"I2S3_CH1", "DL6_CH1 Switch", "DL6"},
{"I2S3_CH2", "DL6_CH2 Switch", "DL6"},
{"I2S3_CH1", "DL4_CH1 Switch", "DL4"},
{"I2S3_CH2", "DL4_CH2 Switch", "DL4"},
{"I2S3_CH1", "DL5_CH1 Switch", "DL5"},
{"I2S3_CH2", "DL5_CH2 Switch", "DL5"},
{"I2S3_CH1", "DL8_CH1 Switch", "DL8"},
{"I2S3_CH2", "DL8_CH2 Switch", "DL8"},
{"I2S3", NULL, "I2S3_CH1"},
{"I2S3", NULL, "I2S3_CH2"},
{"I2S3", NULL, "I2S0_EN", mtk_afe_i2s_share_connect},
{"I2S3", NULL, "I2S1_EN", mtk_afe_i2s_share_connect},
{"I2S3", NULL, "I2S2_EN", mtk_afe_i2s_share_connect},
{"I2S3", NULL, "I2S3_EN"},
{"I2S3", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S3", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S3", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S3", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{I2S3_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
{I2S3_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
{"I2S3", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S3", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S3", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S3", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{I2S3_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
{I2S3_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
/* allow i2s on without codec on */
{"I2S0", NULL, "I2S0_In_Mux"},
{"I2S0_In_Mux", "Dummy_Widget", "I2S_DUMMY_IN"},
{"I2S1_Out_Mux", "Dummy_Widget", "I2S1"},
{"I2S_DUMMY_OUT", NULL, "I2S1_Out_Mux"},
{"I2S2", NULL, "I2S2_In_Mux"},
{"I2S2_In_Mux", "Dummy_Widget", "I2S_DUMMY_IN"},
{"I2S3_Out_Mux", "Dummy_Widget", "I2S3"},
{"I2S_DUMMY_OUT", NULL, "I2S3_Out_Mux"},
/* i2s in lpbk */
{"I2S0_Lpbk_Mux", "Lpbk", "I2S3"},
{"I2S2_Lpbk_Mux", "Lpbk", "I2S1"},
{"I2S0", NULL, "I2S0_Lpbk_Mux"},
{"I2S2", NULL, "I2S2_Lpbk_Mux"},
};
/* dai ops */
static int mtk_dai_connsys_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
unsigned int rate = params_rate(params);
unsigned int rate_reg = mt8186_rate_transform(afe->dev,
rate, dai->id);
unsigned int i2s_con = 0;
dev_dbg(afe->dev, "%s(), id %d, stream %d, rate %d\n",
__func__, dai->id, substream->stream, rate);
/* non-inverse, i2s mode, slave, 16bits, from connsys */
i2s_con |= 0 << INV_PAD_CTRL_SFT;
i2s_con |= I2S_FMT_I2S << I2S_FMT_SFT;
i2s_con |= 1 << I2S_SRC_SFT;
i2s_con |= get_i2s_wlen(SNDRV_PCM_FORMAT_S16_LE) << I2S_WLEN_SFT;
i2s_con |= 0 << I2SIN_PAD_SEL_SFT;
regmap_write(afe->regmap, AFE_CONNSYS_I2S_CON, i2s_con);
/* use asrc */
regmap_update_bits(afe->regmap, AFE_CONNSYS_I2S_CON,
I2S_BYPSRC_MASK_SFT, 0);
/* slave mode, set i2s for asrc */
regmap_update_bits(afe->regmap, AFE_CONNSYS_I2S_CON,
I2S_MODE_MASK_SFT, rate_reg << I2S_MODE_SFT);
if (rate == 44100)
regmap_write(afe->regmap, AFE_ASRC_2CH_CON3, 0x1b9000);
else if (rate == 32000)
regmap_write(afe->regmap, AFE_ASRC_2CH_CON3, 0x140000);
else
regmap_write(afe->regmap, AFE_ASRC_2CH_CON3, 0x1e0000);
/* Calibration setting */
regmap_write(afe->regmap, AFE_ASRC_2CH_CON4, 0x140000);
regmap_write(afe->regmap, AFE_ASRC_2CH_CON9, 0x36000);
regmap_write(afe->regmap, AFE_ASRC_2CH_CON10, 0x2fc00);
regmap_write(afe->regmap, AFE_ASRC_2CH_CON6, 0x7ef4);
regmap_write(afe->regmap, AFE_ASRC_2CH_CON5, 0xff5986);
/* 0:Stereo 1:Mono */
regmap_update_bits(afe->regmap, AFE_ASRC_2CH_CON2,
CHSET_IS_MONO_MASK_SFT, 0);
return 0;
}
static int mtk_dai_connsys_i2s_trigger(struct snd_pcm_substream *substream,
int cmd, struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8186_afe_private *afe_priv = afe->platform_priv;
dev_dbg(afe->dev, "%s(), cmd %d, stream %d\n",
__func__, cmd, substream->stream);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
/* i2s enable */
regmap_update_bits(afe->regmap,
AFE_CONNSYS_I2S_CON,
I2S_EN_MASK_SFT,
BIT(I2S_EN_SFT));
/* calibrator enable */
regmap_update_bits(afe->regmap,
AFE_ASRC_2CH_CON5,
CALI_EN_MASK_SFT,
BIT(CALI_EN_SFT));
/* asrc enable */
regmap_update_bits(afe->regmap,
AFE_ASRC_2CH_CON0,
CON0_CHSET_STR_CLR_MASK_SFT,
BIT(CON0_CHSET_STR_CLR_SFT));
regmap_update_bits(afe->regmap,
AFE_ASRC_2CH_CON0,
CON0_ASM_ON_MASK_SFT,
BIT(CON0_ASM_ON_SFT));
afe_priv->dai_on[dai->id] = true;
return 0;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
regmap_update_bits(afe->regmap, AFE_ASRC_2CH_CON0,
CON0_ASM_ON_MASK_SFT, 0);
regmap_update_bits(afe->regmap, AFE_ASRC_2CH_CON5,
CALI_EN_MASK_SFT, 0);
/* i2s disable */
regmap_update_bits(afe->regmap, AFE_CONNSYS_I2S_CON,
I2S_EN_MASK_SFT, 0);
/* bypass asrc */
regmap_update_bits(afe->regmap, AFE_CONNSYS_I2S_CON,
I2S_BYPSRC_MASK_SFT, BIT(I2S_BYPSRC_SFT));
afe_priv->dai_on[dai->id] = false;
return 0;
default:
return -EINVAL;
}
return 0;
}
static const struct snd_soc_dai_ops mtk_dai_connsys_i2s_ops = {
.hw_params = mtk_dai_connsys_i2s_hw_params,
.trigger = mtk_dai_connsys_i2s_trigger,
};
/* i2s */
static int mtk_dai_i2s_config(struct mtk_base_afe *afe,
struct snd_pcm_hw_params *params,
int i2s_id)
{
struct mt8186_afe_private *afe_priv = afe->platform_priv;
struct mtk_afe_i2s_priv *i2s_priv = afe_priv->dai_priv[i2s_id];
unsigned int rate = params_rate(params);
unsigned int rate_reg = mt8186_rate_transform(afe->dev,
rate, i2s_id);
snd_pcm_format_t format = params_format(params);
unsigned int i2s_con = 0;
int ret;
dev_dbg(afe->dev, "%s(), id %d, rate %d, format %d\n",
__func__, i2s_id, rate, format);
i2s_priv->rate = rate;
switch (i2s_id) {
case MT8186_DAI_I2S_0:
i2s_con = I2S_IN_PAD_IO_MUX << I2SIN_PAD_SEL_SFT;
i2s_con |= rate_reg << I2S_OUT_MODE_SFT;
i2s_con |= I2S_FMT_I2S << I2S_FMT_SFT;
i2s_con |= get_i2s_wlen(format) << I2S_WLEN_SFT;
regmap_update_bits(afe->regmap, AFE_I2S_CON,
0xffffeffa, i2s_con);
break;
case MT8186_DAI_I2S_1:
i2s_con = I2S1_SEL_O28_O29 << I2S2_SEL_O03_O04_SFT;
i2s_con |= rate_reg << I2S2_OUT_MODE_SFT;
i2s_con |= I2S_FMT_I2S << I2S2_FMT_SFT;
i2s_con |= get_i2s_wlen(format) << I2S2_WLEN_SFT;
regmap_update_bits(afe->regmap, AFE_I2S_CON1,
0xffffeffa, i2s_con);
break;
case MT8186_DAI_I2S_2:
i2s_con = 8 << I2S3_UPDATE_WORD_SFT;
i2s_con |= rate_reg << I2S3_OUT_MODE_SFT;
i2s_con |= I2S_FMT_I2S << I2S3_FMT_SFT;
i2s_con |= get_i2s_wlen(format) << I2S3_WLEN_SFT;
regmap_update_bits(afe->regmap, AFE_I2S_CON2,
0xffffeffa, i2s_con);
break;
case MT8186_DAI_I2S_3:
i2s_con = rate_reg << I2S4_OUT_MODE_SFT;
i2s_con |= I2S_FMT_I2S << I2S4_FMT_SFT;
i2s_con |= get_i2s_wlen(format) << I2S4_WLEN_SFT;
regmap_update_bits(afe->regmap, AFE_I2S_CON3,
0xffffeffa, i2s_con);
break;
default:
dev_err(afe->dev, "%s(), id %d not support\n",
__func__, i2s_id);
return -EINVAL;
}
/* set share i2s */
if (i2s_priv->share_i2s_id >= 0) {
ret = mtk_dai_i2s_config(afe, params, i2s_priv->share_i2s_id);
if (ret)
return ret;
}
return 0;
}
static int mtk_dai_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
return mtk_dai_i2s_config(afe, params, dai->id);
}
static int mtk_dai_i2s_set_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct mtk_base_afe *afe = dev_get_drvdata(dai->dev);
struct mt8186_afe_private *afe_priv = afe->platform_priv;
struct mtk_afe_i2s_priv *i2s_priv = afe_priv->dai_priv[dai->id];
int apll;
int apll_rate;
if (dir != SND_SOC_CLOCK_OUT) {
dev_err(afe->dev, "%s(), dir != SND_SOC_CLOCK_OUT", __func__);
return -EINVAL;
}
dev_dbg(afe->dev, "%s(), freq %d\n", __func__, freq);
apll = mt8186_get_apll_by_rate(afe, freq);
apll_rate = mt8186_get_apll_rate(afe, apll);
if (freq > apll_rate) {
dev_err(afe->dev, "%s(), freq > apll rate", __func__);
return -EINVAL;
}
if (apll_rate % freq != 0) {
dev_err(afe->dev, "%s(), APLL cannot generate freq Hz", __func__);
return -EINVAL;
}
i2s_priv->mclk_rate = freq;
i2s_priv->mclk_apll = apll;
if (i2s_priv->share_i2s_id > 0) {
struct mtk_afe_i2s_priv *share_i2s_priv;
share_i2s_priv = afe_priv->dai_priv[i2s_priv->share_i2s_id];
if (!share_i2s_priv) {
dev_err(afe->dev, "%s(), share_i2s_priv == NULL", __func__);
return -EINVAL;
}
share_i2s_priv->mclk_rate = i2s_priv->mclk_rate;
share_i2s_priv->mclk_apll = i2s_priv->mclk_apll;
}
return 0;
}
static const struct snd_soc_dai_ops mtk_dai_i2s_ops = {
.hw_params = mtk_dai_i2s_hw_params,
.set_sysclk = mtk_dai_i2s_set_sysclk,
};
/* dai driver */
#define MTK_CONNSYS_I2S_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
#define MTK_I2S_RATES (SNDRV_PCM_RATE_8000_48000 |\
SNDRV_PCM_RATE_88200 |\
SNDRV_PCM_RATE_96000 |\
SNDRV_PCM_RATE_176400 |\
SNDRV_PCM_RATE_192000)
#define MTK_I2S_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver mtk_dai_i2s_driver[] = {
{
.name = "CONNSYS_I2S",
.id = MT8186_DAI_CONNSYS_I2S,
.capture = {
.stream_name = "Connsys I2S",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_CONNSYS_I2S_RATES,
.formats = MTK_I2S_FORMATS,
},
.ops = &mtk_dai_connsys_i2s_ops,
},
{
.name = "I2S0",
.id = MT8186_DAI_I2S_0,
.capture = {
.stream_name = "I2S0",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_I2S_RATES,
.formats = MTK_I2S_FORMATS,
},
.ops = &mtk_dai_i2s_ops,
},
{
.name = "I2S1",
.id = MT8186_DAI_I2S_1,
.playback = {
.stream_name = "I2S1",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_I2S_RATES,
.formats = MTK_I2S_FORMATS,
},
.ops = &mtk_dai_i2s_ops,
},
{
.name = "I2S2",
.id = MT8186_DAI_I2S_2,
.capture = {
.stream_name = "I2S2",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_I2S_RATES,
.formats = MTK_I2S_FORMATS,
},
.ops = &mtk_dai_i2s_ops,
},
{
.name = "I2S3",
.id = MT8186_DAI_I2S_3,
.playback = {
.stream_name = "I2S3",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_I2S_RATES,
.formats = MTK_I2S_FORMATS,
},
.ops = &mtk_dai_i2s_ops,
}
};
/* this enum is merely for mtk_afe_i2s_priv declare */
enum {
DAI_I2S0 = 0,
DAI_I2S1,
DAI_I2S2,
DAI_I2S3,
DAI_I2S_NUM,
};
static const struct mtk_afe_i2s_priv mt8186_i2s_priv[DAI_I2S_NUM] = {
[DAI_I2S0] = {
.id = MT8186_DAI_I2S_0,
.mclk_id = MT8186_I2S0_MCK,
.share_i2s_id = -1,
},
[DAI_I2S1] = {
.id = MT8186_DAI_I2S_1,
.mclk_id = MT8186_I2S1_MCK,
.share_i2s_id = -1,
},
[DAI_I2S2] = {
.id = MT8186_DAI_I2S_2,
.mclk_id = MT8186_I2S2_MCK,
.share_i2s_id = -1,
},
[DAI_I2S3] = {
.id = MT8186_DAI_I2S_3,
/* clock gate naming is hf_faud_i2s4_m_ck*/
.mclk_id = MT8186_I2S4_MCK,
.share_i2s_id = -1,
}
};
/**
* mt8186_dai_i2s_set_share() - Set up I2S ports to share a single clock.
* @afe: Pointer to &struct mtk_base_afe
* @main_i2s_name: The name of the I2S port that will provide the clock
* @secondary_i2s_name: The name of the I2S port that will use this clock
*/
int mt8186_dai_i2s_set_share(struct mtk_base_afe *afe, const char *main_i2s_name,
const char *secondary_i2s_name)
{
struct mtk_afe_i2s_priv *secondary_i2s_priv;
int main_i2s_id;
secondary_i2s_priv = get_i2s_priv_by_name(afe, secondary_i2s_name);
if (!secondary_i2s_priv)
return -EINVAL;
main_i2s_id = get_i2s_id_by_name(afe, main_i2s_name);
if (main_i2s_id < 0)
return main_i2s_id;
secondary_i2s_priv->share_i2s_id = main_i2s_id;
return 0;
}
EXPORT_SYMBOL_GPL(mt8186_dai_i2s_set_share);
static int mt8186_dai_i2s_set_priv(struct mtk_base_afe *afe)
{
int i;
int ret;
for (i = 0; i < DAI_I2S_NUM; i++) {
ret = mt8186_dai_set_priv(afe, mt8186_i2s_priv[i].id,
sizeof(struct mtk_afe_i2s_priv),
&mt8186_i2s_priv[i]);
if (ret)
return ret;
}
return 0;
}
int mt8186_dai_i2s_register(struct mtk_base_afe *afe)
{
struct mtk_base_afe_dai *dai;
int ret;
dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
if (!dai)
return -ENOMEM;
list_add(&dai->list, &afe->sub_dais);
dai->dai_drivers = mtk_dai_i2s_driver;
dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_i2s_driver);
dai->controls = mtk_dai_i2s_controls;
dai->num_controls = ARRAY_SIZE(mtk_dai_i2s_controls);
dai->dapm_widgets = mtk_dai_i2s_widgets;
dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_i2s_widgets);
dai->dapm_routes = mtk_dai_i2s_routes;
dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_i2s_routes);
/* set all dai i2s private data */
ret = mt8186_dai_i2s_set_priv(afe);
if (ret)
return ret;
return 0;
}
| linux-master | sound/soc/mediatek/mt8186/mt8186-dai-i2s.c |
// SPDX-License-Identifier: GPL-2.0
//
// MediaTek ALSA SoC Audio DAI SRC Control
//
// Copyright (c) 2022 MediaTek Inc.
// Author: Jiaxin Yu <[email protected]>
#include <linux/regmap.h>
#include "mt8186-afe-common.h"
#include "mt8186-interconnection.h"
struct mtk_afe_src_priv {
int dl_rate;
int ul_rate;
};
static const unsigned int src_iir_coeff_32_to_16[] = {
0x0dbae6, 0xff9b0a, 0x0dbae6, 0x05e488, 0xe072b9, 0x000002,
0x0dbae6, 0x000f3b, 0x0dbae6, 0x06a537, 0xe17d79, 0x000002,
0x0dbae6, 0x01246a, 0x0dbae6, 0x087261, 0xe306be, 0x000002,
0x0dbae6, 0x03437d, 0x0dbae6, 0x0bc16f, 0xe57c87, 0x000002,
0x0dbae6, 0x072981, 0x0dbae6, 0x111dd3, 0xe94f2a, 0x000002,
0x0dbae6, 0x0dc4a6, 0x0dbae6, 0x188611, 0xee85a0, 0x000002,
0x0dbae6, 0x168b9a, 0x0dbae6, 0x200e8f, 0xf3ccf1, 0x000002,
0x000000, 0x1b75cb, 0x1b75cb, 0x2374a2, 0x000000, 0x000001
};
static const unsigned int src_iir_coeff_44_to_16[] = {
0x09ae28, 0xf7d97d, 0x09ae28, 0x212a3d, 0xe0ac3a, 0x000002,
0x09ae28, 0xf8525a, 0x09ae28, 0x216d72, 0xe234be, 0x000002,
0x09ae28, 0xf980f5, 0x09ae28, 0x22a057, 0xe45a81, 0x000002,
0x09ae28, 0xfc0a08, 0x09ae28, 0x24d3bd, 0xe7752d, 0x000002,
0x09ae28, 0x016162, 0x09ae28, 0x27da01, 0xeb6ea8, 0x000002,
0x09ae28, 0x0b67df, 0x09ae28, 0x2aca4a, 0xef34c4, 0x000002,
0x000000, 0x135c50, 0x135c50, 0x2c1079, 0x000000, 0x000001
};
static const unsigned int src_iir_coeff_44_to_32[] = {
0x096966, 0x0c4d35, 0x096966, 0xedee81, 0xf05070, 0x000003,
0x12d2cc, 0x193910, 0x12d2cc, 0xddbf4f, 0xe21e1d, 0x000002,
0x12d2cc, 0x1a9e60, 0x12d2cc, 0xe18916, 0xe470fd, 0x000002,
0x12d2cc, 0x1d06e0, 0x12d2cc, 0xe8a4a6, 0xe87b24, 0x000002,
0x12d2cc, 0x207578, 0x12d2cc, 0xf4fe62, 0xef5917, 0x000002,
0x12d2cc, 0x24055f, 0x12d2cc, 0x05ee2b, 0xf8b502, 0x000002,
0x000000, 0x25a599, 0x25a599, 0x0fabe2, 0x000000, 0x000001
};
static const unsigned int src_iir_coeff_48_to_16[] = {
0x0296a4, 0xfd69dd, 0x0296a4, 0x209439, 0xe01ff9, 0x000002,
0x0f4ff3, 0xf0d6d4, 0x0f4ff3, 0x209bc9, 0xe076c3, 0x000002,
0x0e8490, 0xf1fe63, 0x0e8490, 0x20cfd6, 0xe12124, 0x000002,
0x14852f, 0xed794a, 0x14852f, 0x21503d, 0xe28b32, 0x000002,
0x136222, 0xf17677, 0x136222, 0x225be1, 0xe56964, 0x000002,
0x0a8d85, 0xfc4a97, 0x0a8d85, 0x24310c, 0xea6952, 0x000002,
0x05eff5, 0x043455, 0x05eff5, 0x4ced8f, 0xe134d6, 0x000001,
0x000000, 0x3aebe6, 0x3aebe6, 0x04f3b0, 0x000000, 0x000004
};
static const unsigned int src_iir_coeff_48_to_32[] = {
0x10c1b8, 0x10a7df, 0x10c1b8, 0xe7514e, 0xe0b41f, 0x000002,
0x10c1b8, 0x116257, 0x10c1b8, 0xe9402f, 0xe25aaa, 0x000002,
0x10c1b8, 0x130c89, 0x10c1b8, 0xed3cc3, 0xe4dddb, 0x000002,
0x10c1b8, 0x1600dd, 0x10c1b8, 0xf48000, 0xe90c55, 0x000002,
0x10c1b8, 0x1a672e, 0x10c1b8, 0x00494c, 0xefa807, 0x000002,
0x10c1b8, 0x1f38e6, 0x10c1b8, 0x0ee076, 0xf7c5f3, 0x000002,
0x000000, 0x218370, 0x218370, 0x168b40, 0x000000, 0x000001
};
static const unsigned int src_iir_coeff_48_to_44[] = {
0x0bf71c, 0x170f3f, 0x0bf71c, 0xe3a4c8, 0xf096cb, 0x000003,
0x0bf71c, 0x17395e, 0x0bf71c, 0xe58085, 0xf210c8, 0x000003,
0x0bf71c, 0x1782bd, 0x0bf71c, 0xe95ef6, 0xf4c899, 0x000003,
0x0bf71c, 0x17cd97, 0x0bf71c, 0xf1608a, 0xfa3b18, 0x000003,
0x000000, 0x2fdc6f, 0x2fdc6f, 0xf15663, 0x000000, 0x000001
};
static const unsigned int src_iir_coeff_96_to_16[] = {
0x0805a1, 0xf21ae3, 0x0805a1, 0x3840bb, 0xe02a2e, 0x000002,
0x0d5dd8, 0xe8f259, 0x0d5dd8, 0x1c0af6, 0xf04700, 0x000003,
0x0bb422, 0xec08d9, 0x0bb422, 0x1bfccc, 0xf09216, 0x000003,
0x08fde6, 0xf108be, 0x08fde6, 0x1bf096, 0xf10ae0, 0x000003,
0x0ae311, 0xeeeda3, 0x0ae311, 0x37c646, 0xe385f5, 0x000002,
0x044089, 0xfa7242, 0x044089, 0x37a785, 0xe56526, 0x000002,
0x00c75c, 0xffb947, 0x00c75c, 0x378ba3, 0xe72c5f, 0x000002,
0x000000, 0x0ef76e, 0x0ef76e, 0x377fda, 0x000000, 0x000001,
};
static const unsigned int src_iir_coeff_96_to_44[] = {
0x08b543, 0xfd80f4, 0x08b543, 0x0e2332, 0xe06ed0, 0x000002,
0x1b6038, 0xf90e7e, 0x1b6038, 0x0ec1ac, 0xe16f66, 0x000002,
0x188478, 0xfbb921, 0x188478, 0x105859, 0xe2e596, 0x000002,
0x13eff3, 0xffa707, 0x13eff3, 0x13455c, 0xe533b7, 0x000002,
0x0dc239, 0x03d458, 0x0dc239, 0x17f120, 0xe8b617, 0x000002,
0x0745f1, 0x05d790, 0x0745f1, 0x1e3d75, 0xed5f18, 0x000002,
0x05641f, 0x085e2b, 0x05641f, 0x48efd0, 0xe3e9c8, 0x000001,
0x000000, 0x28f632, 0x28f632, 0x273905, 0x000000, 0x000001,
};
static unsigned int mtk_get_src_freq_mode(struct mtk_base_afe *afe, int rate)
{
switch (rate) {
case 8000:
return 0x50000;
case 11025:
return 0x6e400;
case 12000:
return 0x78000;
case 16000:
return 0xa0000;
case 22050:
return 0xdc800;
case 24000:
return 0xf0000;
case 32000:
return 0x140000;
case 44100:
return 0x1b9000;
case 48000:
return 0x1e0000;
case 88200:
return 0x372000;
case 96000:
return 0x3c0000;
case 176400:
return 0x6e4000;
case 192000:
return 0x780000;
default:
dev_err(afe->dev, "%s(), rate %d invalid!!!\n",
__func__, rate);
return 0;
}
}
static const unsigned int *get_iir_coeff(unsigned int rate_in,
unsigned int rate_out,
unsigned int *param_num)
{
if (rate_in == 32000 && rate_out == 16000) {
*param_num = ARRAY_SIZE(src_iir_coeff_32_to_16);
return src_iir_coeff_32_to_16;
} else if (rate_in == 44100 && rate_out == 16000) {
*param_num = ARRAY_SIZE(src_iir_coeff_44_to_16);
return src_iir_coeff_44_to_16;
} else if (rate_in == 44100 && rate_out == 32000) {
*param_num = ARRAY_SIZE(src_iir_coeff_44_to_32);
return src_iir_coeff_44_to_32;
} else if ((rate_in == 48000 && rate_out == 16000) ||
(rate_in == 96000 && rate_out == 32000)) {
*param_num = ARRAY_SIZE(src_iir_coeff_48_to_16);
return src_iir_coeff_48_to_16;
} else if (rate_in == 48000 && rate_out == 32000) {
*param_num = ARRAY_SIZE(src_iir_coeff_48_to_32);
return src_iir_coeff_48_to_32;
} else if (rate_in == 48000 && rate_out == 44100) {
*param_num = ARRAY_SIZE(src_iir_coeff_48_to_44);
return src_iir_coeff_48_to_44;
} else if (rate_in == 96000 && rate_out == 16000) {
*param_num = ARRAY_SIZE(src_iir_coeff_96_to_16);
return src_iir_coeff_96_to_16;
} else if ((rate_in == 96000 && rate_out == 44100) ||
(rate_in == 48000 && rate_out == 22050)) {
*param_num = ARRAY_SIZE(src_iir_coeff_96_to_44);
return src_iir_coeff_96_to_44;
}
*param_num = 0;
return NULL;
}
static int mtk_set_src_1_param(struct mtk_base_afe *afe, int id)
{
struct mt8186_afe_private *afe_priv = afe->platform_priv;
struct mtk_afe_src_priv *src_priv = afe_priv->dai_priv[id];
unsigned int iir_coeff_num;
unsigned int iir_stage;
int rate_in = src_priv->dl_rate;
int rate_out = src_priv->ul_rate;
unsigned int out_freq_mode = mtk_get_src_freq_mode(afe, rate_out);
unsigned int in_freq_mode = mtk_get_src_freq_mode(afe, rate_in);
/* set out freq mode */
regmap_update_bits(afe->regmap, AFE_GENERAL1_ASRC_2CH_CON3,
G_SRC_ASM_FREQ_4_MASK_SFT,
out_freq_mode << G_SRC_ASM_FREQ_4_SFT);
/* set in freq mode */
regmap_update_bits(afe->regmap, AFE_GENERAL1_ASRC_2CH_CON4,
G_SRC_ASM_FREQ_5_MASK_SFT,
in_freq_mode << G_SRC_ASM_FREQ_5_SFT);
regmap_write(afe->regmap, AFE_GENERAL1_ASRC_2CH_CON5, 0x3f5986);
regmap_write(afe->regmap, AFE_GENERAL1_ASRC_2CH_CON5, 0x3f5987);
regmap_write(afe->regmap, AFE_GENERAL1_ASRC_2CH_CON6, 0x1fbd);
regmap_write(afe->regmap, AFE_GENERAL1_ASRC_2CH_CON2, 0);
/* set iir if in_rate > out_rate */
if (rate_in > rate_out) {
int i;
const unsigned int *iir_coeff = get_iir_coeff(rate_in, rate_out,
&iir_coeff_num);
if (iir_coeff_num == 0 || !iir_coeff) {
dev_err(afe->dev, "%s(), iir coeff error, num %d, coeff %p\n",
__func__, iir_coeff_num, iir_coeff);
return -EINVAL;
}
/* COEFF_SRAM_CTRL */
regmap_update_bits(afe->regmap, AFE_GENERAL1_ASRC_2CH_CON0,
G_SRC_COEFF_SRAM_CTRL_MASK_SFT,
BIT(G_SRC_COEFF_SRAM_CTRL_SFT));
/* Clear coeff history to r/w coeff from the first position */
regmap_update_bits(afe->regmap, AFE_GENERAL1_ASRC_2CH_CON13,
G_SRC_COEFF_SRAM_ADR_MASK_SFT, 0);
/* Write SRC coeff, should not read the reg during write */
for (i = 0; i < iir_coeff_num; i++)
regmap_write(afe->regmap, AFE_GENERAL1_ASRC_2CH_CON12,
iir_coeff[i]);
/* disable sram access */
regmap_update_bits(afe->regmap, AFE_GENERAL1_ASRC_2CH_CON0,
G_SRC_COEFF_SRAM_CTRL_MASK_SFT, 0);
/* CHSET_IIR_STAGE */
iir_stage = (iir_coeff_num / 6) - 1;
regmap_update_bits(afe->regmap, AFE_GENERAL1_ASRC_2CH_CON2,
G_SRC_CHSET_IIR_STAGE_MASK_SFT,
iir_stage << G_SRC_CHSET_IIR_STAGE_SFT);
/* CHSET_IIR_EN */
regmap_update_bits(afe->regmap, AFE_GENERAL1_ASRC_2CH_CON2,
G_SRC_CHSET_IIR_EN_MASK_SFT,
BIT(G_SRC_CHSET_IIR_EN_SFT));
} else {
/* CHSET_IIR_EN off */
regmap_update_bits(afe->regmap, AFE_GENERAL1_ASRC_2CH_CON2,
G_SRC_CHSET_IIR_EN_MASK_SFT, 0);
}
return 0;
}
static int mtk_set_src_2_param(struct mtk_base_afe *afe, int id)
{
struct mt8186_afe_private *afe_priv = afe->platform_priv;
struct mtk_afe_src_priv *src_priv = afe_priv->dai_priv[id];
unsigned int iir_coeff_num;
unsigned int iir_stage;
int rate_in = src_priv->dl_rate;
int rate_out = src_priv->ul_rate;
unsigned int out_freq_mode = mtk_get_src_freq_mode(afe, rate_out);
unsigned int in_freq_mode = mtk_get_src_freq_mode(afe, rate_in);
/* set out freq mode */
regmap_update_bits(afe->regmap, AFE_GENERAL2_ASRC_2CH_CON3,
G_SRC_ASM_FREQ_4_MASK_SFT,
out_freq_mode << G_SRC_ASM_FREQ_4_SFT);
/* set in freq mode */
regmap_update_bits(afe->regmap, AFE_GENERAL2_ASRC_2CH_CON4,
G_SRC_ASM_FREQ_5_MASK_SFT,
in_freq_mode << G_SRC_ASM_FREQ_5_SFT);
regmap_write(afe->regmap, AFE_GENERAL2_ASRC_2CH_CON5, 0x3f5986);
regmap_write(afe->regmap, AFE_GENERAL2_ASRC_2CH_CON5, 0x3f5987);
regmap_write(afe->regmap, AFE_GENERAL2_ASRC_2CH_CON6, 0x1fbd);
regmap_write(afe->regmap, AFE_GENERAL2_ASRC_2CH_CON2, 0);
/* set iir if in_rate > out_rate */
if (rate_in > rate_out) {
int i;
const unsigned int *iir_coeff = get_iir_coeff(rate_in, rate_out,
&iir_coeff_num);
if (iir_coeff_num == 0 || !iir_coeff) {
dev_err(afe->dev, "%s(), iir coeff error, num %d, coeff %p\n",
__func__, iir_coeff_num, iir_coeff);
return -EINVAL;
}
/* COEFF_SRAM_CTRL */
regmap_update_bits(afe->regmap, AFE_GENERAL2_ASRC_2CH_CON0,
G_SRC_COEFF_SRAM_CTRL_MASK_SFT,
BIT(G_SRC_COEFF_SRAM_CTRL_SFT));
/* Clear coeff history to r/w coeff from the first position */
regmap_update_bits(afe->regmap, AFE_GENERAL2_ASRC_2CH_CON13,
G_SRC_COEFF_SRAM_ADR_MASK_SFT, 0);
/* Write SRC coeff, should not read the reg during write */
for (i = 0; i < iir_coeff_num; i++)
regmap_write(afe->regmap, AFE_GENERAL2_ASRC_2CH_CON12,
iir_coeff[i]);
/* disable sram access */
regmap_update_bits(afe->regmap, AFE_GENERAL2_ASRC_2CH_CON0,
G_SRC_COEFF_SRAM_CTRL_MASK_SFT, 0);
/* CHSET_IIR_STAGE */
iir_stage = (iir_coeff_num / 6) - 1;
regmap_update_bits(afe->regmap, AFE_GENERAL2_ASRC_2CH_CON2,
G_SRC_CHSET_IIR_STAGE_MASK_SFT,
iir_stage << G_SRC_CHSET_IIR_STAGE_SFT);
/* CHSET_IIR_EN */
regmap_update_bits(afe->regmap, AFE_GENERAL2_ASRC_2CH_CON2,
G_SRC_CHSET_IIR_EN_MASK_SFT,
BIT(G_SRC_CHSET_IIR_EN_SFT));
} else {
/* CHSET_IIR_EN off */
regmap_update_bits(afe->regmap, AFE_GENERAL2_ASRC_2CH_CON2,
G_SRC_CHSET_IIR_EN_MASK_SFT, 0);
}
return 0;
}
#define HW_SRC_1_EN_W_NAME "HW_SRC_1_Enable"
#define HW_SRC_2_EN_W_NAME "HW_SRC_2_Enable"
static int mtk_hw_src_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8186_afe_private *afe_priv = afe->platform_priv;
int id;
struct mtk_afe_src_priv *src_priv;
unsigned int reg;
if (strcmp(w->name, HW_SRC_1_EN_W_NAME) == 0)
id = MT8186_DAI_SRC_1;
else
id = MT8186_DAI_SRC_2;
src_priv = afe_priv->dai_priv[id];
dev_dbg(afe->dev,
"%s(), name %s, event 0x%x, id %d, src_priv %p, dl_rate %d, ul_rate %d\n",
__func__, w->name, event, id, src_priv,
src_priv->dl_rate, src_priv->ul_rate);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
if (id == MT8186_DAI_SRC_1)
mtk_set_src_1_param(afe, id);
else
mtk_set_src_2_param(afe, id);
break;
case SND_SOC_DAPM_POST_PMU:
reg = (id == MT8186_DAI_SRC_1) ?
AFE_GENERAL1_ASRC_2CH_CON0 : AFE_GENERAL2_ASRC_2CH_CON0;
/* ASM_ON */
regmap_update_bits(afe->regmap, reg,
G_SRC_ASM_ON_MASK_SFT,
BIT(G_SRC_ASM_ON_SFT));
/* CHSET_ON */
regmap_update_bits(afe->regmap, reg,
G_SRC_CHSET_ON_MASK_SFT,
BIT(G_SRC_CHSET_ON_SFT));
/* CHSET_STR_CLR */
regmap_update_bits(afe->regmap, reg,
G_SRC_CHSET_STR_CLR_MASK_SFT,
BIT(G_SRC_CHSET_STR_CLR_SFT));
break;
case SND_SOC_DAPM_PRE_PMD:
reg = (id == MT8186_DAI_SRC_1) ?
AFE_GENERAL1_ASRC_2CH_CON0 : AFE_GENERAL2_ASRC_2CH_CON0;
/* ASM_OFF */
regmap_update_bits(afe->regmap, reg, G_SRC_ASM_ON_MASK_SFT, 0);
/* CHSET_OFF */
regmap_update_bits(afe->regmap, reg, G_SRC_CHSET_ON_MASK_SFT, 0);
/* CHSET_STR_CLR */
regmap_update_bits(afe->regmap, reg, G_SRC_CHSET_STR_CLR_MASK_SFT, 0);
break;
default:
break;
}
return 0;
}
/* dai component */
static const struct snd_kcontrol_new mtk_hw_src_1_in_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN40,
I_DL1_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN40,
I_DL2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN40,
I_DL3_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN40_1,
I_DL4_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1 Switch", AFE_CONN40_1,
I_DL6_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1 Switch", AFE_CONN40,
I_I2S0_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN40_1,
I_DL5_CH1, 1, 0),
};
static const struct snd_kcontrol_new mtk_hw_src_1_in_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN41,
I_DL1_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN41,
I_DL2_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN41,
I_DL3_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN41_1,
I_DL4_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2 Switch", AFE_CONN41_1,
I_DL6_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2 Switch", AFE_CONN41,
I_I2S0_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2 Switch", AFE_CONN41_1,
I_DL5_CH2, 1, 0),
};
static const struct snd_kcontrol_new mtk_hw_src_2_in_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN42,
I_DL1_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN42,
I_DL2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN42,
I_DL3_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN42,
I_DL4_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN42_1,
I_DL5_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1 Switch", AFE_CONN42_1,
I_DL6_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN2_OUT_CH1 Switch", AFE_CONN42,
I_GAIN2_OUT_CH1, 1, 0),
};
static const struct snd_kcontrol_new mtk_hw_src_2_in_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN43,
I_DL1_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN43,
I_DL2_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN43,
I_DL3_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN43,
I_DL4_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2 Switch", AFE_CONN43_1,
I_DL5_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2 Switch", AFE_CONN43_1,
I_DL6_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN2_OUT_CH2 Switch", AFE_CONN43,
I_GAIN2_OUT_CH2, 1, 0),
};
static const struct snd_soc_dapm_widget mtk_dai_src_widgets[] = {
/* inter-connections */
SND_SOC_DAPM_MIXER("HW_SRC_1_IN_CH1", SND_SOC_NOPM, 0, 0,
mtk_hw_src_1_in_ch1_mix,
ARRAY_SIZE(mtk_hw_src_1_in_ch1_mix)),
SND_SOC_DAPM_MIXER("HW_SRC_1_IN_CH2", SND_SOC_NOPM, 0, 0,
mtk_hw_src_1_in_ch2_mix,
ARRAY_SIZE(mtk_hw_src_1_in_ch2_mix)),
SND_SOC_DAPM_MIXER("HW_SRC_2_IN_CH1", SND_SOC_NOPM, 0, 0,
mtk_hw_src_2_in_ch1_mix,
ARRAY_SIZE(mtk_hw_src_2_in_ch1_mix)),
SND_SOC_DAPM_MIXER("HW_SRC_2_IN_CH2", SND_SOC_NOPM, 0, 0,
mtk_hw_src_2_in_ch2_mix,
ARRAY_SIZE(mtk_hw_src_2_in_ch2_mix)),
SND_SOC_DAPM_SUPPLY(HW_SRC_1_EN_W_NAME,
GENERAL_ASRC_EN_ON, GENERAL1_ASRC_EN_ON_SFT, 0,
mtk_hw_src_event,
SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_SUPPLY(HW_SRC_2_EN_W_NAME,
GENERAL_ASRC_EN_ON, GENERAL2_ASRC_EN_ON_SFT, 0,
mtk_hw_src_event,
SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_INPUT("HW SRC 1 Out Endpoint"),
SND_SOC_DAPM_INPUT("HW SRC 2 Out Endpoint"),
SND_SOC_DAPM_OUTPUT("HW SRC 1 In Endpoint"),
SND_SOC_DAPM_OUTPUT("HW SRC 2 In Endpoint"),
};
static int mtk_afe_src_en_connect(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_dapm_widget *w = source;
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8186_afe_private *afe_priv = afe->platform_priv;
struct mtk_afe_src_priv *src_priv;
if (strcmp(w->name, HW_SRC_1_EN_W_NAME) == 0)
src_priv = afe_priv->dai_priv[MT8186_DAI_SRC_1];
else
src_priv = afe_priv->dai_priv[MT8186_DAI_SRC_2];
dev_dbg(afe->dev,
"%s(), source %s, sink %s, dl_rate %d, ul_rate %d\n",
__func__, source->name, sink->name,
src_priv->dl_rate, src_priv->ul_rate);
return (src_priv->dl_rate > 0 && src_priv->ul_rate > 0) ? 1 : 0;
}
static const struct snd_soc_dapm_route mtk_dai_src_routes[] = {
{"HW_SRC_1_IN_CH1", "DL1_CH1 Switch", "DL1"},
{"HW_SRC_1_IN_CH2", "DL1_CH2 Switch", "DL1"},
{"HW_SRC_2_IN_CH1", "DL1_CH1 Switch", "DL1"},
{"HW_SRC_2_IN_CH2", "DL1_CH2 Switch", "DL1"},
{"HW_SRC_1_IN_CH1", "DL2_CH1 Switch", "DL2"},
{"HW_SRC_1_IN_CH2", "DL2_CH2 Switch", "DL2"},
{"HW_SRC_2_IN_CH1", "DL2_CH1 Switch", "DL2"},
{"HW_SRC_2_IN_CH2", "DL2_CH2 Switch", "DL2"},
{"HW_SRC_1_IN_CH1", "DL3_CH1 Switch", "DL3"},
{"HW_SRC_1_IN_CH2", "DL3_CH2 Switch", "DL3"},
{"HW_SRC_2_IN_CH1", "DL3_CH1 Switch", "DL3"},
{"HW_SRC_2_IN_CH2", "DL3_CH2 Switch", "DL3"},
{"HW_SRC_1_IN_CH1", "DL6_CH1 Switch", "DL6"},
{"HW_SRC_1_IN_CH2", "DL6_CH2 Switch", "DL6"},
{"HW_SRC_2_IN_CH1", "DL6_CH1 Switch", "DL6"},
{"HW_SRC_2_IN_CH2", "DL6_CH2 Switch", "DL6"},
{"HW_SRC_1_IN_CH1", "DL5_CH1 Switch", "DL5"},
{"HW_SRC_1_IN_CH2", "DL5_CH2 Switch", "DL5"},
{"HW_SRC_2_IN_CH1", "DL5_CH1 Switch", "DL5"},
{"HW_SRC_2_IN_CH2", "DL5_CH2 Switch", "DL5"},
{"HW_SRC_1_IN_CH1", "DL4_CH1 Switch", "DL4"},
{"HW_SRC_1_IN_CH2", "DL4_CH2 Switch", "DL4"},
{"HW_SRC_2_IN_CH1", "DL4_CH1 Switch", "DL4"},
{"HW_SRC_2_IN_CH2", "DL4_CH2 Switch", "DL4"},
{"HW_SRC_1_In", NULL, "HW_SRC_1_IN_CH1"},
{"HW_SRC_1_In", NULL, "HW_SRC_1_IN_CH2"},
{"HW_SRC_2_In", NULL, "HW_SRC_2_IN_CH1"},
{"HW_SRC_2_In", NULL, "HW_SRC_2_IN_CH2"},
{"HW_SRC_1_In", NULL, HW_SRC_1_EN_W_NAME, mtk_afe_src_en_connect},
{"HW_SRC_1_Out", NULL, HW_SRC_1_EN_W_NAME, mtk_afe_src_en_connect},
{"HW_SRC_2_In", NULL, HW_SRC_2_EN_W_NAME, mtk_afe_src_en_connect},
{"HW_SRC_2_Out", NULL, HW_SRC_2_EN_W_NAME, mtk_afe_src_en_connect},
{"HW SRC 1 In Endpoint", NULL, "HW_SRC_1_In"},
{"HW SRC 2 In Endpoint", NULL, "HW_SRC_2_In"},
{"HW_SRC_1_Out", NULL, "HW SRC 1 Out Endpoint"},
{"HW_SRC_2_Out", NULL, "HW SRC 2 Out Endpoint"},
};
/* dai ops */
static int mtk_dai_src_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8186_afe_private *afe_priv = afe->platform_priv;
int id = dai->id;
struct mtk_afe_src_priv *src_priv = afe_priv->dai_priv[id];
unsigned int sft, mask;
unsigned int rate = params_rate(params);
unsigned int rate_reg = mt8186_rate_transform(afe->dev, rate, id);
dev_dbg(afe->dev, "%s(), id %d, stream %d, rate %d\n",
__func__, id, substream->stream, rate);
/* rate */
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
src_priv->dl_rate = rate;
if (id == MT8186_DAI_SRC_1) {
sft = GENERAL1_ASRCIN_MODE_SFT;
mask = GENERAL1_ASRCIN_MODE_MASK;
} else {
sft = GENERAL2_ASRCIN_MODE_SFT;
mask = GENERAL2_ASRCIN_MODE_MASK;
}
} else {
src_priv->ul_rate = rate;
if (id == MT8186_DAI_SRC_1) {
sft = GENERAL1_ASRCOUT_MODE_SFT;
mask = GENERAL1_ASRCOUT_MODE_MASK;
} else {
sft = GENERAL2_ASRCOUT_MODE_SFT;
mask = GENERAL2_ASRCOUT_MODE_MASK;
}
}
regmap_update_bits(afe->regmap, GENERAL_ASRC_MODE, mask << sft, rate_reg << sft);
return 0;
}
static int mtk_dai_src_hw_free(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8186_afe_private *afe_priv = afe->platform_priv;
int id = dai->id;
struct mtk_afe_src_priv *src_priv = afe_priv->dai_priv[id];
dev_dbg(afe->dev, "%s(), id %d, stream %d\n",
__func__, id, substream->stream);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
src_priv->dl_rate = 0;
else
src_priv->ul_rate = 0;
return 0;
}
static const struct snd_soc_dai_ops mtk_dai_src_ops = {
.hw_params = mtk_dai_src_hw_params,
.hw_free = mtk_dai_src_hw_free,
};
/* dai driver */
#define MTK_SRC_RATES (SNDRV_PCM_RATE_8000_48000 |\
SNDRV_PCM_RATE_88200 |\
SNDRV_PCM_RATE_96000 |\
SNDRV_PCM_RATE_176400 |\
SNDRV_PCM_RATE_192000)
#define MTK_SRC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver mtk_dai_src_driver[] = {
{
.name = "HW_SRC_1",
.id = MT8186_DAI_SRC_1,
.playback = {
.stream_name = "HW_SRC_1_In",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_SRC_RATES,
.formats = MTK_SRC_FORMATS,
},
.capture = {
.stream_name = "HW_SRC_1_Out",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_SRC_RATES,
.formats = MTK_SRC_FORMATS,
},
.ops = &mtk_dai_src_ops,
},
{
.name = "HW_SRC_2",
.id = MT8186_DAI_SRC_2,
.playback = {
.stream_name = "HW_SRC_2_In",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_SRC_RATES,
.formats = MTK_SRC_FORMATS,
},
.capture = {
.stream_name = "HW_SRC_2_Out",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_SRC_RATES,
.formats = MTK_SRC_FORMATS,
},
.ops = &mtk_dai_src_ops,
},
};
int mt8186_dai_src_register(struct mtk_base_afe *afe)
{
struct mtk_base_afe_dai *dai;
int ret;
dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
if (!dai)
return -ENOMEM;
list_add(&dai->list, &afe->sub_dais);
dai->dai_drivers = mtk_dai_src_driver;
dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_src_driver);
dai->dapm_widgets = mtk_dai_src_widgets;
dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_src_widgets);
dai->dapm_routes = mtk_dai_src_routes;
dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_src_routes);
/* set dai priv */
ret = mt8186_dai_set_priv(afe, MT8186_DAI_SRC_1,
sizeof(struct mtk_afe_src_priv), NULL);
if (ret)
return ret;
ret = mt8186_dai_set_priv(afe, MT8186_DAI_SRC_2,
sizeof(struct mtk_afe_src_priv), NULL);
if (ret)
return ret;
return 0;
}
| linux-master | sound/soc/mediatek/mt8186/mt8186-dai-src.c |
// SPDX-License-Identifier: GPL-2.0
/*
* mt8188-mt6359.c -- MT8188-MT6359 ALSA SoC machine driver
*
* Copyright (c) 2022 MediaTek Inc.
* Author: Trevor Wu <[email protected]>
*/
#include <linux/bitfield.h>
#include <linux/input.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/pm_runtime.h>
#include <sound/jack.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include "mt8188-afe-common.h"
#include "../../codecs/nau8825.h"
#include "../../codecs/mt6359.h"
#include "../common/mtk-afe-platform-driver.h"
#include "../common/mtk-soundcard-driver.h"
#define CKSYS_AUD_TOP_CFG 0x032c
#define RG_TEST_ON BIT(0)
#define RG_TEST_TYPE BIT(2)
#define CKSYS_AUD_TOP_MON 0x0330
#define TEST_MISO_COUNT_1 GENMASK(3, 0)
#define TEST_MISO_COUNT_2 GENMASK(7, 4)
#define TEST_MISO_DONE_1 BIT(28)
#define TEST_MISO_DONE_2 BIT(29)
#define NAU8825_HS_PRESENT BIT(0)
/*
* Maxim MAX98390
*/
#define MAX98390_CODEC_DAI "max98390-aif1"
#define MAX98390_DEV0_NAME "max98390.0-0038" /* rear right */
#define MAX98390_DEV1_NAME "max98390.0-0039" /* rear left */
#define MAX98390_DEV2_NAME "max98390.0-003a" /* front right */
#define MAX98390_DEV3_NAME "max98390.0-003b" /* front left */
/*
* Nau88l25
*/
#define NAU8825_CODEC_DAI "nau8825-hifi"
/* FE */
SND_SOC_DAILINK_DEFS(playback2,
DAILINK_COMP_ARRAY(COMP_CPU("DL2")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(playback3,
DAILINK_COMP_ARRAY(COMP_CPU("DL3")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(playback6,
DAILINK_COMP_ARRAY(COMP_CPU("DL6")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(playback7,
DAILINK_COMP_ARRAY(COMP_CPU("DL7")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(playback8,
DAILINK_COMP_ARRAY(COMP_CPU("DL8")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(playback10,
DAILINK_COMP_ARRAY(COMP_CPU("DL10")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(playback11,
DAILINK_COMP_ARRAY(COMP_CPU("DL11")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture1,
DAILINK_COMP_ARRAY(COMP_CPU("UL1")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture2,
DAILINK_COMP_ARRAY(COMP_CPU("UL2")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture3,
DAILINK_COMP_ARRAY(COMP_CPU("UL3")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture4,
DAILINK_COMP_ARRAY(COMP_CPU("UL4")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture5,
DAILINK_COMP_ARRAY(COMP_CPU("UL5")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture6,
DAILINK_COMP_ARRAY(COMP_CPU("UL6")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture8,
DAILINK_COMP_ARRAY(COMP_CPU("UL8")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture9,
DAILINK_COMP_ARRAY(COMP_CPU("UL9")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture10,
DAILINK_COMP_ARRAY(COMP_CPU("UL10")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
/* BE */
SND_SOC_DAILINK_DEFS(dl_src,
DAILINK_COMP_ARRAY(COMP_CPU("DL_SRC")),
DAILINK_COMP_ARRAY(COMP_CODEC("mt6359-sound",
"mt6359-snd-codec-aif1")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(dptx,
DAILINK_COMP_ARRAY(COMP_CPU("DPTX")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(etdm1_in,
DAILINK_COMP_ARRAY(COMP_CPU("ETDM1_IN")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(etdm2_in,
DAILINK_COMP_ARRAY(COMP_CPU("ETDM2_IN")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(etdm1_out,
DAILINK_COMP_ARRAY(COMP_CPU("ETDM1_OUT")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(etdm2_out,
DAILINK_COMP_ARRAY(COMP_CPU("ETDM2_OUT")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(etdm3_out,
DAILINK_COMP_ARRAY(COMP_CPU("ETDM3_OUT")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(pcm1,
DAILINK_COMP_ARRAY(COMP_CPU("PCM1")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(ul_src,
DAILINK_COMP_ARRAY(COMP_CPU("UL_SRC")),
DAILINK_COMP_ARRAY(COMP_CODEC("mt6359-sound",
"mt6359-snd-codec-aif1"),
COMP_CODEC("dmic-codec",
"dmic-hifi")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
struct mt8188_mt6359_priv {
struct snd_soc_jack dp_jack;
struct snd_soc_jack hdmi_jack;
struct snd_soc_jack headset_jack;
void *private_data;
};
static struct snd_soc_jack_pin mt8188_hdmi_jack_pins[] = {
{
.pin = "HDMI",
.mask = SND_JACK_LINEOUT,
},
};
static struct snd_soc_jack_pin mt8188_dp_jack_pins[] = {
{
.pin = "DP",
.mask = SND_JACK_LINEOUT,
},
};
static struct snd_soc_jack_pin nau8825_jack_pins[] = {
{
.pin = "Headphone Jack",
.mask = SND_JACK_HEADPHONE,
},
{
.pin = "Headset Mic",
.mask = SND_JACK_MICROPHONE,
},
};
struct mt8188_card_data {
const char *name;
unsigned long quirk;
};
static const struct snd_kcontrol_new mt8188_dumb_spk_controls[] = {
SOC_DAPM_PIN_SWITCH("Ext Spk"),
};
static const struct snd_soc_dapm_widget mt8188_dumb_spk_widgets[] = {
SND_SOC_DAPM_SPK("Ext Spk", NULL),
};
static const struct snd_kcontrol_new mt8188_dual_spk_controls[] = {
SOC_DAPM_PIN_SWITCH("Left Spk"),
SOC_DAPM_PIN_SWITCH("Right Spk"),
};
static const struct snd_soc_dapm_widget mt8188_dual_spk_widgets[] = {
SND_SOC_DAPM_SPK("Left Spk", NULL),
SND_SOC_DAPM_SPK("Right Spk", NULL),
};
static const struct snd_kcontrol_new mt8188_rear_spk_controls[] = {
SOC_DAPM_PIN_SWITCH("Rear Left Spk"),
SOC_DAPM_PIN_SWITCH("Rear Right Spk"),
};
static const struct snd_soc_dapm_widget mt8188_rear_spk_widgets[] = {
SND_SOC_DAPM_SPK("Rear Left Spk", NULL),
SND_SOC_DAPM_SPK("Rear Right Spk", NULL),
};
static const struct snd_soc_dapm_widget mt8188_mt6359_widgets[] = {
SND_SOC_DAPM_HP("Headphone", NULL),
SND_SOC_DAPM_MIC("Headset Mic", NULL),
SND_SOC_DAPM_SINK("HDMI"),
SND_SOC_DAPM_SINK("DP"),
};
static const struct snd_kcontrol_new mt8188_mt6359_controls[] = {
SOC_DAPM_PIN_SWITCH("Headphone"),
SOC_DAPM_PIN_SWITCH("Headset Mic"),
};
static const struct snd_soc_dapm_widget mt8188_nau8825_widgets[] = {
SND_SOC_DAPM_HP("Headphone Jack", NULL),
};
static const struct snd_kcontrol_new mt8188_nau8825_controls[] = {
SOC_DAPM_PIN_SWITCH("Headphone Jack"),
};
static int mt8188_mt6359_mtkaif_calibration(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_component *cmpnt_afe =
snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
struct snd_soc_component *cmpnt_codec =
asoc_rtd_to_codec(rtd, 0)->component;
struct mtk_base_afe *afe;
struct mt8188_afe_private *afe_priv;
struct mtkaif_param *param;
int chosen_phase_1, chosen_phase_2;
int prev_cycle_1, prev_cycle_2;
u8 test_done_1, test_done_2;
int cycle_1, cycle_2;
int mtkaif_chosen_phase[MT8188_MTKAIF_MISO_NUM];
int mtkaif_phase_cycle[MT8188_MTKAIF_MISO_NUM];
int mtkaif_calibration_num_phase;
bool mtkaif_calibration_ok;
u32 monitor = 0;
int counter;
int phase;
int i;
if (!cmpnt_afe)
return -EINVAL;
afe = snd_soc_component_get_drvdata(cmpnt_afe);
afe_priv = afe->platform_priv;
param = &afe_priv->mtkaif_params;
dev_dbg(afe->dev, "%s(), start\n", __func__);
param->mtkaif_calibration_ok = false;
for (i = 0; i < MT8188_MTKAIF_MISO_NUM; i++) {
param->mtkaif_chosen_phase[i] = -1;
param->mtkaif_phase_cycle[i] = 0;
mtkaif_chosen_phase[i] = -1;
mtkaif_phase_cycle[i] = 0;
}
if (IS_ERR(afe_priv->topckgen)) {
dev_info(afe->dev, "%s() Cannot find topckgen controller\n",
__func__);
return 0;
}
pm_runtime_get_sync(afe->dev);
mt6359_mtkaif_calibration_enable(cmpnt_codec);
/* set test type to synchronizer pulse */
regmap_write(afe_priv->topckgen, CKSYS_AUD_TOP_CFG, RG_TEST_TYPE);
mtkaif_calibration_num_phase = 42; /* mt6359: 0 ~ 42 */
mtkaif_calibration_ok = true;
for (phase = 0;
phase <= mtkaif_calibration_num_phase && mtkaif_calibration_ok;
phase++) {
mt6359_set_mtkaif_calibration_phase(cmpnt_codec,
phase, phase, phase);
regmap_set_bits(afe_priv->topckgen, CKSYS_AUD_TOP_CFG, RG_TEST_ON);
test_done_1 = 0;
test_done_2 = 0;
cycle_1 = -1;
cycle_2 = -1;
counter = 0;
while (!(test_done_1 & test_done_2)) {
regmap_read(afe_priv->topckgen,
CKSYS_AUD_TOP_MON, &monitor);
test_done_1 = FIELD_GET(TEST_MISO_DONE_1, monitor);
test_done_2 = FIELD_GET(TEST_MISO_DONE_2, monitor);
if (test_done_1 == 1)
cycle_1 = FIELD_GET(TEST_MISO_COUNT_1, monitor);
if (test_done_2 == 1)
cycle_2 = FIELD_GET(TEST_MISO_COUNT_2, monitor);
/* handle if never test done */
if (++counter > 10000) {
dev_err(afe->dev, "%s(), test fail, cycle_1 %d, cycle_2 %d, monitor 0x%x\n",
__func__, cycle_1, cycle_2, monitor);
mtkaif_calibration_ok = false;
break;
}
}
if (phase == 0) {
prev_cycle_1 = cycle_1;
prev_cycle_2 = cycle_2;
}
if (cycle_1 != prev_cycle_1 &&
mtkaif_chosen_phase[MT8188_MTKAIF_MISO_0] < 0) {
mtkaif_chosen_phase[MT8188_MTKAIF_MISO_0] = phase - 1;
mtkaif_phase_cycle[MT8188_MTKAIF_MISO_0] = prev_cycle_1;
}
if (cycle_2 != prev_cycle_2 &&
mtkaif_chosen_phase[MT8188_MTKAIF_MISO_1] < 0) {
mtkaif_chosen_phase[MT8188_MTKAIF_MISO_1] = phase - 1;
mtkaif_phase_cycle[MT8188_MTKAIF_MISO_1] = prev_cycle_2;
}
regmap_clear_bits(afe_priv->topckgen, CKSYS_AUD_TOP_CFG, RG_TEST_ON);
if (mtkaif_chosen_phase[MT8188_MTKAIF_MISO_0] >= 0 &&
mtkaif_chosen_phase[MT8188_MTKAIF_MISO_1] >= 0)
break;
}
if (mtkaif_chosen_phase[MT8188_MTKAIF_MISO_0] < 0) {
mtkaif_calibration_ok = false;
chosen_phase_1 = 0;
} else {
chosen_phase_1 = mtkaif_chosen_phase[MT8188_MTKAIF_MISO_0];
}
if (mtkaif_chosen_phase[MT8188_MTKAIF_MISO_1] < 0) {
mtkaif_calibration_ok = false;
chosen_phase_2 = 0;
} else {
chosen_phase_2 = mtkaif_chosen_phase[MT8188_MTKAIF_MISO_1];
}
mt6359_set_mtkaif_calibration_phase(cmpnt_codec,
chosen_phase_1,
chosen_phase_2,
0);
mt6359_mtkaif_calibration_disable(cmpnt_codec);
pm_runtime_put(afe->dev);
param->mtkaif_calibration_ok = mtkaif_calibration_ok;
param->mtkaif_chosen_phase[MT8188_MTKAIF_MISO_0] = chosen_phase_1;
param->mtkaif_chosen_phase[MT8188_MTKAIF_MISO_1] = chosen_phase_2;
for (i = 0; i < MT8188_MTKAIF_MISO_NUM; i++)
param->mtkaif_phase_cycle[i] = mtkaif_phase_cycle[i];
dev_dbg(afe->dev, "%s(), end, calibration ok %d\n",
__func__, param->mtkaif_calibration_ok);
return 0;
}
static int mt8188_mt6359_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_component *cmpnt_codec =
asoc_rtd_to_codec(rtd, 0)->component;
/* set mtkaif protocol */
mt6359_set_mtkaif_protocol(cmpnt_codec,
MT6359_MTKAIF_PROTOCOL_2_CLK_P2);
/* mtkaif calibration */
mt8188_mt6359_mtkaif_calibration(rtd);
return 0;
}
enum {
DAI_LINK_DL2_FE,
DAI_LINK_DL3_FE,
DAI_LINK_DL6_FE,
DAI_LINK_DL7_FE,
DAI_LINK_DL8_FE,
DAI_LINK_DL10_FE,
DAI_LINK_DL11_FE,
DAI_LINK_UL1_FE,
DAI_LINK_UL2_FE,
DAI_LINK_UL3_FE,
DAI_LINK_UL4_FE,
DAI_LINK_UL5_FE,
DAI_LINK_UL6_FE,
DAI_LINK_UL8_FE,
DAI_LINK_UL9_FE,
DAI_LINK_UL10_FE,
DAI_LINK_DL_SRC_BE,
DAI_LINK_DPTX_BE,
DAI_LINK_ETDM1_IN_BE,
DAI_LINK_ETDM2_IN_BE,
DAI_LINK_ETDM1_OUT_BE,
DAI_LINK_ETDM2_OUT_BE,
DAI_LINK_ETDM3_OUT_BE,
DAI_LINK_PCM1_BE,
DAI_LINK_UL_SRC_BE,
};
static int mt8188_dptx_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
unsigned int rate = params_rate(params);
unsigned int mclk_fs_ratio = 256;
unsigned int mclk_fs = rate * mclk_fs_ratio;
struct snd_soc_dai *dai = asoc_rtd_to_cpu(rtd, 0);
return snd_soc_dai_set_sysclk(dai, 0, mclk_fs, SND_SOC_CLOCK_OUT);
}
static const struct snd_soc_ops mt8188_dptx_ops = {
.hw_params = mt8188_dptx_hw_params,
};
static int mt8188_dptx_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
struct snd_pcm_hw_params *params)
{
/* fix BE i2s format to 32bit, clean param mask first */
snd_mask_reset_range(hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT),
0, (__force unsigned int)SNDRV_PCM_FORMAT_LAST);
params_set_format(params, SNDRV_PCM_FORMAT_S32_LE);
return 0;
}
static int mt8188_hdmi_codec_init(struct snd_soc_pcm_runtime *rtd)
{
struct mt8188_mt6359_priv *priv = snd_soc_card_get_drvdata(rtd->card);
struct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component;
int ret = 0;
ret = snd_soc_card_jack_new_pins(rtd->card, "HDMI Jack",
SND_JACK_LINEOUT, &priv->hdmi_jack,
mt8188_hdmi_jack_pins,
ARRAY_SIZE(mt8188_hdmi_jack_pins));
if (ret) {
dev_err(rtd->dev, "%s, new jack failed: %d\n", __func__, ret);
return ret;
}
ret = snd_soc_component_set_jack(component, &priv->hdmi_jack, NULL);
if (ret) {
dev_err(rtd->dev, "%s, set jack failed on %s (ret=%d)\n",
__func__, component->name, ret);
return ret;
}
return 0;
}
static int mt8188_dptx_codec_init(struct snd_soc_pcm_runtime *rtd)
{
struct mt8188_mt6359_priv *priv = snd_soc_card_get_drvdata(rtd->card);
struct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component;
int ret = 0;
ret = snd_soc_card_jack_new_pins(rtd->card, "DP Jack", SND_JACK_LINEOUT,
&priv->dp_jack, mt8188_dp_jack_pins,
ARRAY_SIZE(mt8188_dp_jack_pins));
if (ret) {
dev_err(rtd->dev, "%s, new jack failed: %d\n", __func__, ret);
return ret;
}
ret = snd_soc_component_set_jack(component, &priv->dp_jack, NULL);
if (ret) {
dev_err(rtd->dev, "%s, set jack failed on %s (ret=%d)\n",
__func__, component->name, ret);
return ret;
}
return 0;
}
static int mt8188_dumb_amp_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_card *card = rtd->card;
int ret = 0;
ret = snd_soc_dapm_new_controls(&card->dapm, mt8188_dumb_spk_widgets,
ARRAY_SIZE(mt8188_dumb_spk_widgets));
if (ret) {
dev_err(rtd->dev, "unable to add Dumb Speaker dapm, ret %d\n", ret);
return ret;
}
ret = snd_soc_add_card_controls(card, mt8188_dumb_spk_controls,
ARRAY_SIZE(mt8188_dumb_spk_controls));
if (ret) {
dev_err(rtd->dev, "unable to add Dumb card controls, ret %d\n", ret);
return ret;
}
return 0;
}
static int mt8188_max98390_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
unsigned int bit_width = params_width(params);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct snd_soc_dai *codec_dai;
int i;
snd_soc_dai_set_tdm_slot(cpu_dai, 0xf, 0xf, 4, bit_width);
for_each_rtd_codec_dais(rtd, i, codec_dai) {
if (!strcmp(codec_dai->component->name, MAX98390_DEV0_NAME))
snd_soc_dai_set_tdm_slot(codec_dai, 0x8, 0x3, 4, bit_width);
if (!strcmp(codec_dai->component->name, MAX98390_DEV1_NAME))
snd_soc_dai_set_tdm_slot(codec_dai, 0x4, 0x3, 4, bit_width);
if (!strcmp(codec_dai->component->name, MAX98390_DEV2_NAME))
snd_soc_dai_set_tdm_slot(codec_dai, 0x2, 0x3, 4, bit_width);
if (!strcmp(codec_dai->component->name, MAX98390_DEV3_NAME))
snd_soc_dai_set_tdm_slot(codec_dai, 0x1, 0x3, 4, bit_width);
}
return 0;
}
static const struct snd_soc_ops mt8188_max98390_ops = {
.hw_params = mt8188_max98390_hw_params,
};
static int mt8188_max98390_codec_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_card *card = rtd->card;
int ret;
/* add regular speakers dapm route */
ret = snd_soc_dapm_new_controls(&card->dapm, mt8188_dual_spk_widgets,
ARRAY_SIZE(mt8188_dual_spk_widgets));
if (ret) {
dev_err(rtd->dev, "unable to add Left/Right Speaker widget, ret %d\n", ret);
return ret;
}
ret = snd_soc_add_card_controls(card, mt8188_dual_spk_controls,
ARRAY_SIZE(mt8188_dual_spk_controls));
if (ret) {
dev_err(rtd->dev, "unable to add Left/Right card controls, ret %d\n", ret);
return ret;
}
if (rtd->dai_link->num_codecs <= 2)
return 0;
/* add widgets/controls/dapm for rear speakers */
ret = snd_soc_dapm_new_controls(&card->dapm, mt8188_rear_spk_widgets,
ARRAY_SIZE(mt8188_rear_spk_widgets));
if (ret) {
dev_err(rtd->dev, "unable to add Rear Speaker widget, ret %d\n", ret);
/* Don't need to add routes if widget addition failed */
return ret;
}
ret = snd_soc_add_card_controls(card, mt8188_rear_spk_controls,
ARRAY_SIZE(mt8188_rear_spk_controls));
if (ret) {
dev_err(rtd->dev, "unable to add Rear card controls, ret %d\n", ret);
return ret;
}
return 0;
}
static int mt8188_nau8825_codec_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_card *card = rtd->card;
struct mt8188_mt6359_priv *priv = snd_soc_card_get_drvdata(card);
struct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component;
struct snd_soc_jack *jack = &priv->headset_jack;
int ret;
ret = snd_soc_dapm_new_controls(&card->dapm, mt8188_nau8825_widgets,
ARRAY_SIZE(mt8188_nau8825_widgets));
if (ret) {
dev_err(rtd->dev, "unable to add nau8825 card widget, ret %d\n", ret);
return ret;
}
ret = snd_soc_add_card_controls(card, mt8188_nau8825_controls,
ARRAY_SIZE(mt8188_nau8825_controls));
if (ret) {
dev_err(rtd->dev, "unable to add nau8825 card controls, ret %d\n", ret);
return ret;
}
ret = snd_soc_card_jack_new_pins(rtd->card, "Headset Jack",
SND_JACK_HEADSET | SND_JACK_BTN_0 |
SND_JACK_BTN_1 | SND_JACK_BTN_2 |
SND_JACK_BTN_3,
jack,
nau8825_jack_pins,
ARRAY_SIZE(nau8825_jack_pins));
if (ret) {
dev_err(rtd->dev, "Headset Jack creation failed: %d\n", ret);
return ret;
}
snd_jack_set_key(jack->jack, SND_JACK_BTN_0, KEY_PLAYPAUSE);
snd_jack_set_key(jack->jack, SND_JACK_BTN_1, KEY_VOICECOMMAND);
snd_jack_set_key(jack->jack, SND_JACK_BTN_2, KEY_VOLUMEUP);
snd_jack_set_key(jack->jack, SND_JACK_BTN_3, KEY_VOLUMEDOWN);
ret = snd_soc_component_set_jack(component, jack, NULL);
if (ret) {
dev_err(rtd->dev, "Headset Jack call-back failed: %d\n", ret);
return ret;
}
return 0;
};
static void mt8188_nau8825_codec_exit(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component;
snd_soc_component_set_jack(component, NULL, NULL);
}
static int mt8188_nau8825_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
unsigned int rate = params_rate(params);
unsigned int bit_width = params_width(params);
int clk_freq, ret;
clk_freq = rate * 2 * bit_width;
/* Configure clock for codec */
ret = snd_soc_dai_set_sysclk(codec_dai, NAU8825_CLK_FLL_BLK, 0,
SND_SOC_CLOCK_IN);
if (ret < 0) {
dev_err(codec_dai->dev, "can't set BCLK clock %d\n", ret);
return ret;
}
/* Configure pll for codec */
ret = snd_soc_dai_set_pll(codec_dai, 0, 0, clk_freq,
params_rate(params) * 256);
if (ret < 0) {
dev_err(codec_dai->dev, "can't set BCLK: %d\n", ret);
return ret;
}
return 0;
}
static const struct snd_soc_ops mt8188_nau8825_ops = {
.hw_params = mt8188_nau8825_hw_params,
};
static struct snd_soc_dai_link mt8188_mt6359_dai_links[] = {
/* FE */
[DAI_LINK_DL2_FE] = {
.name = "DL2_FE",
.stream_name = "DL2 Playback",
.trigger = {
SND_SOC_DPCM_TRIGGER_POST,
SND_SOC_DPCM_TRIGGER_POST,
},
.dynamic = 1,
.dpcm_playback = 1,
.dpcm_merged_chan = 1,
.dpcm_merged_rate = 1,
.dpcm_merged_format = 1,
SND_SOC_DAILINK_REG(playback2),
},
[DAI_LINK_DL3_FE] = {
.name = "DL3_FE",
.stream_name = "DL3 Playback",
.trigger = {
SND_SOC_DPCM_TRIGGER_POST,
SND_SOC_DPCM_TRIGGER_POST,
},
.dynamic = 1,
.dpcm_playback = 1,
.dpcm_merged_chan = 1,
.dpcm_merged_rate = 1,
.dpcm_merged_format = 1,
SND_SOC_DAILINK_REG(playback3),
},
[DAI_LINK_DL6_FE] = {
.name = "DL6_FE",
.stream_name = "DL6 Playback",
.trigger = {
SND_SOC_DPCM_TRIGGER_POST,
SND_SOC_DPCM_TRIGGER_POST,
},
.dynamic = 1,
.dpcm_playback = 1,
.dpcm_merged_chan = 1,
.dpcm_merged_rate = 1,
.dpcm_merged_format = 1,
SND_SOC_DAILINK_REG(playback6),
},
[DAI_LINK_DL7_FE] = {
.name = "DL7_FE",
.stream_name = "DL7 Playback",
.trigger = {
SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE,
},
.dynamic = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(playback7),
},
[DAI_LINK_DL8_FE] = {
.name = "DL8_FE",
.stream_name = "DL8 Playback",
.trigger = {
SND_SOC_DPCM_TRIGGER_POST,
SND_SOC_DPCM_TRIGGER_POST,
},
.dynamic = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(playback8),
},
[DAI_LINK_DL10_FE] = {
.name = "DL10_FE",
.stream_name = "DL10 Playback",
.trigger = {
SND_SOC_DPCM_TRIGGER_POST,
SND_SOC_DPCM_TRIGGER_POST,
},
.dynamic = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(playback10),
},
[DAI_LINK_DL11_FE] = {
.name = "DL11_FE",
.stream_name = "DL11 Playback",
.trigger = {
SND_SOC_DPCM_TRIGGER_POST,
SND_SOC_DPCM_TRIGGER_POST,
},
.dynamic = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(playback11),
},
[DAI_LINK_UL1_FE] = {
.name = "UL1_FE",
.stream_name = "UL1 Capture",
.trigger = {
SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE,
},
.dynamic = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(capture1),
},
[DAI_LINK_UL2_FE] = {
.name = "UL2_FE",
.stream_name = "UL2 Capture",
.trigger = {
SND_SOC_DPCM_TRIGGER_POST,
SND_SOC_DPCM_TRIGGER_POST,
},
.dynamic = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(capture2),
},
[DAI_LINK_UL3_FE] = {
.name = "UL3_FE",
.stream_name = "UL3 Capture",
.trigger = {
SND_SOC_DPCM_TRIGGER_POST,
SND_SOC_DPCM_TRIGGER_POST,
},
.dynamic = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(capture3),
},
[DAI_LINK_UL4_FE] = {
.name = "UL4_FE",
.stream_name = "UL4 Capture",
.trigger = {
SND_SOC_DPCM_TRIGGER_POST,
SND_SOC_DPCM_TRIGGER_POST,
},
.dynamic = 1,
.dpcm_capture = 1,
.dpcm_merged_chan = 1,
.dpcm_merged_rate = 1,
.dpcm_merged_format = 1,
SND_SOC_DAILINK_REG(capture4),
},
[DAI_LINK_UL5_FE] = {
.name = "UL5_FE",
.stream_name = "UL5 Capture",
.trigger = {
SND_SOC_DPCM_TRIGGER_POST,
SND_SOC_DPCM_TRIGGER_POST,
},
.dynamic = 1,
.dpcm_capture = 1,
.dpcm_merged_chan = 1,
.dpcm_merged_rate = 1,
.dpcm_merged_format = 1,
SND_SOC_DAILINK_REG(capture5),
},
[DAI_LINK_UL6_FE] = {
.name = "UL6_FE",
.stream_name = "UL6 Capture",
.trigger = {
SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE,
},
.dynamic = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(capture6),
},
[DAI_LINK_UL8_FE] = {
.name = "UL8_FE",
.stream_name = "UL8 Capture",
.trigger = {
SND_SOC_DPCM_TRIGGER_POST,
SND_SOC_DPCM_TRIGGER_POST,
},
.dynamic = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(capture8),
},
[DAI_LINK_UL9_FE] = {
.name = "UL9_FE",
.stream_name = "UL9 Capture",
.trigger = {
SND_SOC_DPCM_TRIGGER_POST,
SND_SOC_DPCM_TRIGGER_POST,
},
.dynamic = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(capture9),
},
[DAI_LINK_UL10_FE] = {
.name = "UL10_FE",
.stream_name = "UL10 Capture",
.trigger = {
SND_SOC_DPCM_TRIGGER_POST,
SND_SOC_DPCM_TRIGGER_POST,
},
.dynamic = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(capture10),
},
/* BE */
[DAI_LINK_DL_SRC_BE] = {
.name = "DL_SRC_BE",
.no_pcm = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(dl_src),
},
[DAI_LINK_DPTX_BE] = {
.name = "DPTX_BE",
.ops = &mt8188_dptx_ops,
.be_hw_params_fixup = mt8188_dptx_hw_params_fixup,
.no_pcm = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(dptx),
},
[DAI_LINK_ETDM1_IN_BE] = {
.name = "ETDM1_IN_BE",
.no_pcm = 1,
.dai_fmt = SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBP_CFP,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(etdm1_in),
},
[DAI_LINK_ETDM2_IN_BE] = {
.name = "ETDM2_IN_BE",
.no_pcm = 1,
.dai_fmt = SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBP_CFP,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(etdm2_in),
},
[DAI_LINK_ETDM1_OUT_BE] = {
.name = "ETDM1_OUT_BE",
.no_pcm = 1,
.dai_fmt = SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBC_CFC,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(etdm1_out),
},
[DAI_LINK_ETDM2_OUT_BE] = {
.name = "ETDM2_OUT_BE",
.no_pcm = 1,
.dai_fmt = SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBC_CFC,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(etdm2_out),
},
[DAI_LINK_ETDM3_OUT_BE] = {
.name = "ETDM3_OUT_BE",
.no_pcm = 1,
.dai_fmt = SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBC_CFC,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(etdm3_out),
},
[DAI_LINK_PCM1_BE] = {
.name = "PCM1_BE",
.no_pcm = 1,
.dai_fmt = SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBC_CFC,
.dpcm_playback = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(pcm1),
},
[DAI_LINK_UL_SRC_BE] = {
.name = "UL_SRC_BE",
.no_pcm = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(ul_src),
},
};
static void mt8188_fixup_controls(struct snd_soc_card *card)
{
struct mt8188_mt6359_priv *priv = snd_soc_card_get_drvdata(card);
struct mt8188_card_data *card_data = (struct mt8188_card_data *)priv->private_data;
struct snd_kcontrol *kctl;
if (card_data->quirk & NAU8825_HS_PRESENT) {
struct snd_soc_dapm_widget *w, *next_w;
for_each_card_widgets_safe(card, w, next_w) {
if (strcmp(w->name, "Headphone"))
continue;
snd_soc_dapm_free_widget(w);
}
kctl = snd_ctl_find_id_mixer(card->snd_card, "Headphone Switch");
if (kctl)
snd_ctl_remove(card->snd_card, kctl);
else
dev_warn(card->dev, "Cannot find ctl : Headphone Switch\n");
}
}
static struct snd_soc_card mt8188_mt6359_soc_card = {
.owner = THIS_MODULE,
.dai_link = mt8188_mt6359_dai_links,
.num_links = ARRAY_SIZE(mt8188_mt6359_dai_links),
.dapm_widgets = mt8188_mt6359_widgets,
.num_dapm_widgets = ARRAY_SIZE(mt8188_mt6359_widgets),
.controls = mt8188_mt6359_controls,
.num_controls = ARRAY_SIZE(mt8188_mt6359_controls),
.fixup_controls = mt8188_fixup_controls,
};
static int mt8188_mt6359_dev_probe(struct platform_device *pdev)
{
struct snd_soc_card *card = &mt8188_mt6359_soc_card;
struct device_node *platform_node;
struct mt8188_mt6359_priv *priv;
struct mt8188_card_data *card_data;
struct snd_soc_dai_link *dai_link;
bool init_mt6359 = false;
bool init_nau8825 = false;
bool init_max98390 = false;
bool init_dumb = false;
int ret, i;
card_data = (struct mt8188_card_data *)of_device_get_match_data(&pdev->dev);
card->dev = &pdev->dev;
ret = snd_soc_of_parse_card_name(card, "model");
if (ret)
return dev_err_probe(&pdev->dev, ret, "%s new card name parsing error\n",
__func__);
if (!card->name)
card->name = card_data->name;
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
if (of_property_read_bool(pdev->dev.of_node, "audio-routing")) {
ret = snd_soc_of_parse_audio_routing(card, "audio-routing");
if (ret)
return ret;
}
platform_node = of_parse_phandle(pdev->dev.of_node,
"mediatek,platform", 0);
if (!platform_node) {
ret = -EINVAL;
return dev_err_probe(&pdev->dev, ret, "Property 'platform' missing or invalid\n");
}
ret = parse_dai_link_info(card);
if (ret)
goto err;
for_each_card_prelinks(card, i, dai_link) {
if (!dai_link->platforms->name)
dai_link->platforms->of_node = platform_node;
if (strcmp(dai_link->name, "DPTX_BE") == 0) {
if (strcmp(dai_link->codecs->dai_name, "snd-soc-dummy-dai"))
dai_link->init = mt8188_dptx_codec_init;
} else if (strcmp(dai_link->name, "ETDM3_OUT_BE") == 0) {
if (strcmp(dai_link->codecs->dai_name, "snd-soc-dummy-dai"))
dai_link->init = mt8188_hdmi_codec_init;
} else if (strcmp(dai_link->name, "DL_SRC_BE") == 0 ||
strcmp(dai_link->name, "UL_SRC_BE") == 0) {
if (!init_mt6359) {
dai_link->init = mt8188_mt6359_init;
init_mt6359 = true;
}
} else if (strcmp(dai_link->name, "ETDM1_OUT_BE") == 0 ||
strcmp(dai_link->name, "ETDM2_OUT_BE") == 0 ||
strcmp(dai_link->name, "ETDM1_IN_BE") == 0 ||
strcmp(dai_link->name, "ETDM2_IN_BE") == 0) {
if (!strcmp(dai_link->codecs->dai_name, MAX98390_CODEC_DAI)) {
dai_link->ops = &mt8188_max98390_ops;
if (!init_max98390) {
dai_link->init = mt8188_max98390_codec_init;
init_max98390 = true;
}
} else if (!strcmp(dai_link->codecs->dai_name, NAU8825_CODEC_DAI)) {
dai_link->ops = &mt8188_nau8825_ops;
if (!init_nau8825) {
dai_link->init = mt8188_nau8825_codec_init;
dai_link->exit = mt8188_nau8825_codec_exit;
init_nau8825 = true;
}
} else {
if (strcmp(dai_link->codecs->dai_name, "snd-soc-dummy-dai")) {
if (!init_dumb) {
dai_link->init = mt8188_dumb_amp_init;
init_dumb = true;
}
}
}
}
}
priv->private_data = card_data;
snd_soc_card_set_drvdata(card, priv);
ret = devm_snd_soc_register_card(&pdev->dev, card);
if (ret)
dev_err_probe(&pdev->dev, ret, "%s snd_soc_register_card fail\n",
__func__);
err:
of_node_put(platform_node);
clean_card_reference(card);
return ret;
}
static struct mt8188_card_data mt8188_evb_card = {
.name = "mt8188_mt6359",
};
static struct mt8188_card_data mt8188_nau8825_card = {
.name = "mt8188_nau8825",
.quirk = NAU8825_HS_PRESENT,
};
static const struct of_device_id mt8188_mt6359_dt_match[] = {
{ .compatible = "mediatek,mt8188-mt6359-evb", .data = &mt8188_evb_card, },
{ .compatible = "mediatek,mt8188-nau8825", .data = &mt8188_nau8825_card, },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, mt8188_mt6359_dt_match);
static struct platform_driver mt8188_mt6359_driver = {
.driver = {
.name = "mt8188_mt6359",
.of_match_table = mt8188_mt6359_dt_match,
.pm = &snd_soc_pm_ops,
},
.probe = mt8188_mt6359_dev_probe,
};
module_platform_driver(mt8188_mt6359_driver);
/* Module information */
MODULE_DESCRIPTION("MT8188-MT6359 ALSA SoC machine driver");
MODULE_AUTHOR("Trevor Wu <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("mt8188 mt6359 soc card");
| linux-master | sound/soc/mediatek/mt8188/mt8188-mt6359.c |
// SPDX-License-Identifier: GPL-2.0
/*
* mt8188-audsys-clk.c -- MediaTek 8188 audsys clock control
*
* Copyright (c) 2022 MediaTek Inc.
* Author: Chun-Chia Chiu <[email protected]>
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#include "mt8188-afe-common.h"
#include "mt8188-audsys-clk.h"
#include "mt8188-audsys-clkid.h"
#include "mt8188-reg.h"
struct afe_gate {
int id;
const char *name;
const char *parent_name;
int reg;
u8 bit;
const struct clk_ops *ops;
unsigned long flags;
u8 cg_flags;
};
#define GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, _flags, _cgflags) {\
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.reg = _reg, \
.bit = _bit, \
.flags = _flags, \
.cg_flags = _cgflags, \
}
#define GATE_AFE(_id, _name, _parent, _reg, _bit) \
GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, \
CLK_SET_RATE_PARENT, CLK_GATE_SET_TO_DISABLE)
#define GATE_AUD0(_id, _name, _parent, _bit) \
GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON0, _bit)
#define GATE_AUD1(_id, _name, _parent, _bit) \
GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON1, _bit)
#define GATE_AUD3(_id, _name, _parent, _bit) \
GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON3, _bit)
#define GATE_AUD4(_id, _name, _parent, _bit) \
GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON4, _bit)
#define GATE_AUD5(_id, _name, _parent, _bit) \
GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON5, _bit)
#define GATE_AUD6(_id, _name, _parent, _bit) \
GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON6, _bit)
static const struct afe_gate aud_clks[CLK_AUD_NR_CLK] = {
/* AUD0 */
GATE_AUD0(CLK_AUD_AFE, "aud_afe", "top_a1sys_hp", 2),
GATE_AUD0(CLK_AUD_LRCK_CNT, "aud_lrck_cnt", "top_a1sys_hp", 4),
GATE_AUD0(CLK_AUD_SPDIFIN_TUNER_APLL, "aud_spdifin_tuner_apll", "top_apll4", 10),
GATE_AUD0(CLK_AUD_SPDIFIN_TUNER_DBG, "aud_spdifin_tuner_dbg", "top_apll4", 11),
GATE_AUD0(CLK_AUD_UL_TML, "aud_ul_tml", "top_a1sys_hp", 18),
GATE_AUD0(CLK_AUD_APLL1_TUNER, "aud_apll1_tuner", "top_apll1", 19),
GATE_AUD0(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner", "top_apll2", 20),
GATE_AUD0(CLK_AUD_TOP0_SPDF, "aud_top0_spdf", "top_aud_iec_clk", 21),
GATE_AUD0(CLK_AUD_APLL, "aud_apll", "top_apll1", 23),
GATE_AUD0(CLK_AUD_APLL2, "aud_apll2", "top_apll2", 24),
GATE_AUD0(CLK_AUD_DAC, "aud_dac", "top_a1sys_hp", 25),
GATE_AUD0(CLK_AUD_DAC_PREDIS, "aud_dac_predis", "top_a1sys_hp", 26),
GATE_AUD0(CLK_AUD_TML, "aud_tml", "top_a1sys_hp", 27),
GATE_AUD0(CLK_AUD_ADC, "aud_adc", "top_a1sys_hp", 28),
GATE_AUD0(CLK_AUD_DAC_HIRES, "aud_dac_hires", "top_audio_h", 31),
/* AUD1 */
GATE_AUD1(CLK_AUD_A1SYS_HP, "aud_a1sys_hp", "top_a1sys_hp", 2),
GATE_AUD1(CLK_AUD_AFE_DMIC1, "aud_afe_dmic1", "top_a1sys_hp", 10),
GATE_AUD1(CLK_AUD_AFE_DMIC2, "aud_afe_dmic2", "top_a1sys_hp", 11),
GATE_AUD1(CLK_AUD_AFE_DMIC3, "aud_afe_dmic3", "top_a1sys_hp", 12),
GATE_AUD1(CLK_AUD_AFE_DMIC4, "aud_afe_dmic4", "top_a1sys_hp", 13),
GATE_AUD1(CLK_AUD_AFE_26M_DMIC_TM, "aud_afe_26m_dmic_tm", "top_a1sys_hp", 14),
GATE_AUD1(CLK_AUD_UL_TML_HIRES, "aud_ul_tml_hires", "top_audio_h", 16),
GATE_AUD1(CLK_AUD_ADC_HIRES, "aud_adc_hires", "top_audio_h", 17),
/* AUD3 */
GATE_AUD3(CLK_AUD_LINEIN_TUNER, "aud_linein_tuner", "top_apll5", 5),
GATE_AUD3(CLK_AUD_EARC_TUNER, "aud_earc_tuner", "top_apll3", 7),
/* AUD4 */
GATE_AUD4(CLK_AUD_I2SIN, "aud_i2sin", "top_a1sys_hp", 0),
GATE_AUD4(CLK_AUD_TDM_IN, "aud_tdm_in", "top_a1sys_hp", 1),
GATE_AUD4(CLK_AUD_I2S_OUT, "aud_i2s_out", "top_a1sys_hp", 6),
GATE_AUD4(CLK_AUD_TDM_OUT, "aud_tdm_out", "top_a1sys_hp", 7),
GATE_AUD4(CLK_AUD_HDMI_OUT, "aud_hdmi_out", "top_a1sys_hp", 8),
GATE_AUD4(CLK_AUD_ASRC11, "aud_asrc11", "top_a1sys_hp", 16),
GATE_AUD4(CLK_AUD_ASRC12, "aud_asrc12", "top_a1sys_hp", 17),
GATE_AUD4(CLK_AUD_MULTI_IN, "aud_multi_in", "mphone_slave_b", 19),
GATE_AUD4(CLK_AUD_INTDIR, "aud_intdir", "top_intdir", 20),
GATE_AUD4(CLK_AUD_A1SYS, "aud_a1sys", "top_a1sys_hp", 21),
GATE_AUD4(CLK_AUD_A2SYS, "aud_a2sys", "top_a2sys", 22),
GATE_AUD4(CLK_AUD_PCMIF, "aud_pcmif", "top_a1sys_hp", 24),
GATE_AUD4(CLK_AUD_A3SYS, "aud_a3sys", "top_a3sys", 30),
GATE_AUD4(CLK_AUD_A4SYS, "aud_a4sys", "top_a4sys", 31),
/* AUD5 */
GATE_AUD5(CLK_AUD_MEMIF_UL1, "aud_memif_ul1", "top_a1sys_hp", 0),
GATE_AUD5(CLK_AUD_MEMIF_UL2, "aud_memif_ul2", "top_a1sys_hp", 1),
GATE_AUD5(CLK_AUD_MEMIF_UL3, "aud_memif_ul3", "top_a1sys_hp", 2),
GATE_AUD5(CLK_AUD_MEMIF_UL4, "aud_memif_ul4", "top_a1sys_hp", 3),
GATE_AUD5(CLK_AUD_MEMIF_UL5, "aud_memif_ul5", "top_a1sys_hp", 4),
GATE_AUD5(CLK_AUD_MEMIF_UL6, "aud_memif_ul6", "top_a1sys_hp", 5),
GATE_AUD5(CLK_AUD_MEMIF_UL8, "aud_memif_ul8", "top_a1sys_hp", 7),
GATE_AUD5(CLK_AUD_MEMIF_UL9, "aud_memif_ul9", "top_a1sys_hp", 8),
GATE_AUD5(CLK_AUD_MEMIF_UL10, "aud_memif_ul10", "top_a1sys_hp", 9),
GATE_AUD5(CLK_AUD_MEMIF_DL2, "aud_memif_dl2", "top_a1sys_hp", 18),
GATE_AUD5(CLK_AUD_MEMIF_DL3, "aud_memif_dl3", "top_a1sys_hp", 19),
GATE_AUD5(CLK_AUD_MEMIF_DL6, "aud_memif_dl6", "top_a1sys_hp", 22),
GATE_AUD5(CLK_AUD_MEMIF_DL7, "aud_memif_dl7", "top_a1sys_hp", 23),
GATE_AUD5(CLK_AUD_MEMIF_DL8, "aud_memif_dl8", "top_a1sys_hp", 24),
GATE_AUD5(CLK_AUD_MEMIF_DL10, "aud_memif_dl10", "top_a1sys_hp", 26),
GATE_AUD5(CLK_AUD_MEMIF_DL11, "aud_memif_dl11", "top_a1sys_hp", 27),
/* AUD6 */
GATE_AUD6(CLK_AUD_GASRC0, "aud_gasrc0", "top_asm_h", 0),
GATE_AUD6(CLK_AUD_GASRC1, "aud_gasrc1", "top_asm_h", 1),
GATE_AUD6(CLK_AUD_GASRC2, "aud_gasrc2", "top_asm_h", 2),
GATE_AUD6(CLK_AUD_GASRC3, "aud_gasrc3", "top_asm_h", 3),
GATE_AUD6(CLK_AUD_GASRC4, "aud_gasrc4", "top_asm_h", 4),
GATE_AUD6(CLK_AUD_GASRC5, "aud_gasrc5", "top_asm_h", 5),
GATE_AUD6(CLK_AUD_GASRC6, "aud_gasrc6", "top_asm_h", 6),
GATE_AUD6(CLK_AUD_GASRC7, "aud_gasrc7", "top_asm_h", 7),
GATE_AUD6(CLK_AUD_GASRC8, "aud_gasrc8", "top_asm_h", 8),
GATE_AUD6(CLK_AUD_GASRC9, "aud_gasrc9", "top_asm_h", 9),
GATE_AUD6(CLK_AUD_GASRC10, "aud_gasrc10", "top_asm_h", 10),
GATE_AUD6(CLK_AUD_GASRC11, "aud_gasrc11", "top_asm_h", 11),
};
static void mt8188_audsys_clk_unregister(void *data)
{
struct mtk_base_afe *afe = data;
struct mt8188_afe_private *afe_priv = afe->platform_priv;
struct clk *clk;
struct clk_lookup *cl;
int i;
if (!afe_priv)
return;
for (i = 0; i < CLK_AUD_NR_CLK; i++) {
cl = afe_priv->lookup[i];
if (!cl)
continue;
clk = cl->clk;
clk_unregister_gate(clk);
clkdev_drop(cl);
}
}
int mt8188_audsys_clk_register(struct mtk_base_afe *afe)
{
struct mt8188_afe_private *afe_priv = afe->platform_priv;
struct clk *clk;
struct clk_lookup *cl;
int i;
afe_priv->lookup = devm_kcalloc(afe->dev, CLK_AUD_NR_CLK,
sizeof(*afe_priv->lookup),
GFP_KERNEL);
if (!afe_priv->lookup)
return -ENOMEM;
for (i = 0; i < ARRAY_SIZE(aud_clks); i++) {
const struct afe_gate *gate = &aud_clks[i];
clk = clk_register_gate(afe->dev, gate->name, gate->parent_name,
gate->flags, afe->base_addr + gate->reg,
gate->bit, gate->cg_flags, NULL);
if (IS_ERR(clk)) {
dev_err(afe->dev, "Failed to register clk %s: %ld\n",
gate->name, PTR_ERR(clk));
continue;
}
/* add clk_lookup for devm_clk_get(SND_SOC_DAPM_CLOCK_SUPPLY) */
cl = kzalloc(sizeof(*cl), GFP_KERNEL);
if (!cl)
return -ENOMEM;
cl->clk = clk;
cl->con_id = gate->name;
cl->dev_id = dev_name(afe->dev);
cl->clk_hw = NULL;
clkdev_add(cl);
afe_priv->lookup[i] = cl;
}
return devm_add_action_or_reset(afe->dev, mt8188_audsys_clk_unregister, afe);
}
| linux-master | sound/soc/mediatek/mt8188/mt8188-audsys-clk.c |
// SPDX-License-Identifier: GPL-2.0
/*
* MediaTek ALSA SoC Audio DAI ADDA Control
*
* Copyright (c) 2022 MediaTek Inc.
* Author: Bicycle Tsai <[email protected]>
* Trevor Wu <[email protected]>
* Chun-Chia Chiu <[email protected]>
*/
#include <linux/bitfield.h>
#include <linux/delay.h>
#include <linux/regmap.h>
#include "mt8188-afe-clk.h"
#include "mt8188-afe-common.h"
#include "mt8188-reg.h"
#define ADDA_HIRES_THRES 48000
enum {
SUPPLY_SEQ_ADDA_DL_ON,
SUPPLY_SEQ_ADDA_MTKAIF_CFG,
SUPPLY_SEQ_ADDA_UL_ON,
SUPPLY_SEQ_ADDA_AFE_ON,
};
enum {
MTK_AFE_ADDA_DL_RATE_8K = 0,
MTK_AFE_ADDA_DL_RATE_11K = 1,
MTK_AFE_ADDA_DL_RATE_12K = 2,
MTK_AFE_ADDA_DL_RATE_16K = 3,
MTK_AFE_ADDA_DL_RATE_22K = 4,
MTK_AFE_ADDA_DL_RATE_24K = 5,
MTK_AFE_ADDA_DL_RATE_32K = 6,
MTK_AFE_ADDA_DL_RATE_44K = 7,
MTK_AFE_ADDA_DL_RATE_48K = 8,
MTK_AFE_ADDA_DL_RATE_96K = 9,
MTK_AFE_ADDA_DL_RATE_192K = 10,
};
enum {
MTK_AFE_ADDA_UL_RATE_8K = 0,
MTK_AFE_ADDA_UL_RATE_16K = 1,
MTK_AFE_ADDA_UL_RATE_32K = 2,
MTK_AFE_ADDA_UL_RATE_48K = 3,
MTK_AFE_ADDA_UL_RATE_96K = 4,
MTK_AFE_ADDA_UL_RATE_192K = 5,
};
enum {
DELAY_DATA_MISO1 = 0,
DELAY_DATA_MISO0 = 1,
};
struct mtk_dai_adda_priv {
bool hires_required;
};
static unsigned int afe_adda_dl_rate_transform(struct mtk_base_afe *afe,
unsigned int rate)
{
switch (rate) {
case 8000:
return MTK_AFE_ADDA_DL_RATE_8K;
case 11025:
return MTK_AFE_ADDA_DL_RATE_11K;
case 12000:
return MTK_AFE_ADDA_DL_RATE_12K;
case 16000:
return MTK_AFE_ADDA_DL_RATE_16K;
case 22050:
return MTK_AFE_ADDA_DL_RATE_22K;
case 24000:
return MTK_AFE_ADDA_DL_RATE_24K;
case 32000:
return MTK_AFE_ADDA_DL_RATE_32K;
case 44100:
return MTK_AFE_ADDA_DL_RATE_44K;
case 48000:
return MTK_AFE_ADDA_DL_RATE_48K;
case 96000:
return MTK_AFE_ADDA_DL_RATE_96K;
case 192000:
return MTK_AFE_ADDA_DL_RATE_192K;
default:
dev_info(afe->dev, "%s(), rate %u invalid, use 48kHz!!!\n",
__func__, rate);
return MTK_AFE_ADDA_DL_RATE_48K;
}
}
static unsigned int afe_adda_ul_rate_transform(struct mtk_base_afe *afe,
unsigned int rate)
{
switch (rate) {
case 8000:
return MTK_AFE_ADDA_UL_RATE_8K;
case 16000:
return MTK_AFE_ADDA_UL_RATE_16K;
case 32000:
return MTK_AFE_ADDA_UL_RATE_32K;
case 48000:
return MTK_AFE_ADDA_UL_RATE_48K;
case 96000:
return MTK_AFE_ADDA_UL_RATE_96K;
case 192000:
return MTK_AFE_ADDA_UL_RATE_192K;
default:
dev_info(afe->dev, "%s(), rate %u invalid, use 48kHz!!!\n",
__func__, rate);
return MTK_AFE_ADDA_UL_RATE_48K;
}
}
static int mt8188_adda_mtkaif_init(struct mtk_base_afe *afe)
{
struct mt8188_afe_private *afe_priv = afe->platform_priv;
struct mtkaif_param *param = &afe_priv->mtkaif_params;
int delay_data;
int delay_cycle;
unsigned int mask = 0;
unsigned int val = 0;
/* set rx protocol 2 & mtkaif_rxif_clkinv_adc inverse */
regmap_set_bits(afe->regmap, AFE_ADDA_MTKAIF_CFG0,
MTKAIF_RXIF_CLKINV_ADC | MTKAIF_RXIF_PROTOCOL2);
regmap_set_bits(afe->regmap, AFE_AUD_PAD_TOP, RG_RX_PROTOCOL2);
if (!param->mtkaif_calibration_ok) {
dev_info(afe->dev, "%s(), calibration fail\n", __func__);
return 0;
}
/* set delay for ch1, ch2 */
if (param->mtkaif_phase_cycle[MT8188_MTKAIF_MISO_0] >=
param->mtkaif_phase_cycle[MT8188_MTKAIF_MISO_1]) {
delay_data = DELAY_DATA_MISO1;
delay_cycle =
param->mtkaif_phase_cycle[MT8188_MTKAIF_MISO_0] -
param->mtkaif_phase_cycle[MT8188_MTKAIF_MISO_1];
} else {
delay_data = DELAY_DATA_MISO0;
delay_cycle =
param->mtkaif_phase_cycle[MT8188_MTKAIF_MISO_1] -
param->mtkaif_phase_cycle[MT8188_MTKAIF_MISO_0];
}
val = 0;
mask = (MTKAIF_RXIF_DELAY_DATA | MTKAIF_RXIF_DELAY_CYCLE_MASK);
val |= FIELD_PREP(MTKAIF_RXIF_DELAY_CYCLE_MASK, delay_cycle);
val |= FIELD_PREP(MTKAIF_RXIF_DELAY_DATA, delay_data);
regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG2, mask, val);
return 0;
}
static int mtk_adda_mtkaif_cfg_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
__func__, w->name, event);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
mt8188_adda_mtkaif_init(afe);
break;
default:
break;
}
return 0;
}
static int mtk_adda_dl_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
__func__, w->name, event);
switch (event) {
case SND_SOC_DAPM_POST_PMD:
/* should delayed 1/fs(smallest is 8k) = 125us before afe off */
usleep_range(125, 135);
break;
default:
break;
}
return 0;
}
static void mtk_adda_ul_mictype(struct mtk_base_afe *afe, bool dmic)
{
unsigned int reg = AFE_ADDA_UL_SRC_CON0;
unsigned int val;
val = (UL_SDM3_LEVEL_CTL | UL_MODE_3P25M_CH1_CTL |
UL_MODE_3P25M_CH2_CTL);
/* turn on dmic, ch1, ch2 */
if (dmic)
regmap_set_bits(afe->regmap, reg, val);
else
regmap_clear_bits(afe->regmap, reg, val);
}
static int mtk_adda_ul_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8188_afe_private *afe_priv = afe->platform_priv;
struct mtkaif_param *param = &afe_priv->mtkaif_params;
dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
__func__, w->name, event);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
mtk_adda_ul_mictype(afe, param->mtkaif_dmic_on);
break;
case SND_SOC_DAPM_POST_PMD:
/* should delayed 1/fs(smallest is 8k) = 125us before afe off */
usleep_range(125, 135);
break;
default:
break;
}
return 0;
}
static struct mtk_dai_adda_priv *get_adda_priv_by_name(struct mtk_base_afe *afe,
const char *name)
{
struct mt8188_afe_private *afe_priv = afe->platform_priv;
if (strstr(name, "aud_adc_hires"))
return afe_priv->dai_priv[MT8188_AFE_IO_UL_SRC];
else if (strstr(name, "aud_dac_hires"))
return afe_priv->dai_priv[MT8188_AFE_IO_DL_SRC];
else
return NULL;
}
static int mtk_afe_adda_hires_connect(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_dapm_widget *w = source;
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mtk_dai_adda_priv *adda_priv;
adda_priv = get_adda_priv_by_name(afe, w->name);
if (!adda_priv) {
dev_dbg(afe->dev, "adda_priv == NULL");
return 0;
}
return (adda_priv->hires_required) ? 1 : 0;
}
static const struct snd_kcontrol_new mtk_dai_adda_o176_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN176, 0, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I002 Switch", AFE_CONN176, 2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN176, 20, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN176, 22, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN176_2, 6, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_adda_o177_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN177, 1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I003 Switch", AFE_CONN177, 3, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN177, 21, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN177, 23, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN177_2, 7, 1, 0),
};
static const char * const adda_dlgain_mux_map[] = {
"Bypass", "Connect",
};
static SOC_ENUM_SINGLE_DECL(adda_dlgain_mux_map_enum,
SND_SOC_NOPM, 0,
adda_dlgain_mux_map);
static const struct snd_kcontrol_new adda_dlgain_mux_control =
SOC_DAPM_ENUM("DL_GAIN_MUX", adda_dlgain_mux_map_enum);
static const struct snd_soc_dapm_widget mtk_dai_adda_widgets[] = {
SND_SOC_DAPM_MIXER("I168", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I169", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("O176", SND_SOC_NOPM, 0, 0,
mtk_dai_adda_o176_mix,
ARRAY_SIZE(mtk_dai_adda_o176_mix)),
SND_SOC_DAPM_MIXER("O177", SND_SOC_NOPM, 0, 0,
mtk_dai_adda_o177_mix,
ARRAY_SIZE(mtk_dai_adda_o177_mix)),
SND_SOC_DAPM_SUPPLY_S("ADDA Enable", SUPPLY_SEQ_ADDA_AFE_ON,
AFE_ADDA_UL_DL_CON0,
ADDA_AFE_ON_SHIFT, 0,
NULL,
0),
SND_SOC_DAPM_SUPPLY_S("ADDA Playback Enable", SUPPLY_SEQ_ADDA_DL_ON,
AFE_ADDA_DL_SRC2_CON0,
DL_2_SRC_ON_TMP_CTRL_PRE_SHIFT, 0,
mtk_adda_dl_event,
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("ADDA Capture Enable", SUPPLY_SEQ_ADDA_UL_ON,
AFE_ADDA_UL_SRC_CON0,
UL_SRC_ON_TMP_CTL_SHIFT, 0,
mtk_adda_ul_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("ADDA_MTKAIF_CFG", SUPPLY_SEQ_ADDA_MTKAIF_CFG,
SND_SOC_NOPM,
0, 0,
mtk_adda_mtkaif_cfg_event,
SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_MUX("DL_GAIN_MUX", SND_SOC_NOPM, 0, 0,
&adda_dlgain_mux_control),
SND_SOC_DAPM_PGA("DL_GAIN", AFE_ADDA_DL_SRC2_CON0,
DL_2_GAIN_ON_CTL_PRE_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_INPUT("ADDA_INPUT"),
SND_SOC_DAPM_OUTPUT("ADDA_OUTPUT"),
SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac"),
SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc"),
SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_hires"),
SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc_hires"),
};
static const struct snd_soc_dapm_route mtk_dai_adda_routes[] = {
{"ADDA Capture", NULL, "ADDA Enable"},
{"ADDA Capture", NULL, "ADDA Capture Enable"},
{"ADDA Capture", NULL, "ADDA_MTKAIF_CFG"},
{"ADDA Capture", NULL, "aud_adc"},
{"ADDA Capture", NULL, "aud_adc_hires", mtk_afe_adda_hires_connect},
{"I168", NULL, "ADDA Capture"},
{"I169", NULL, "ADDA Capture"},
{"ADDA Playback", NULL, "ADDA Enable"},
{"ADDA Playback", NULL, "ADDA Playback Enable"},
{"ADDA Playback", NULL, "aud_dac"},
{"ADDA Playback", NULL, "aud_dac_hires", mtk_afe_adda_hires_connect},
{"DL_GAIN", NULL, "O176"},
{"DL_GAIN", NULL, "O177"},
{"DL_GAIN_MUX", "Bypass", "O176"},
{"DL_GAIN_MUX", "Bypass", "O177"},
{"DL_GAIN_MUX", "Connect", "DL_GAIN"},
{"ADDA Playback", NULL, "DL_GAIN_MUX"},
{"O176", "I000 Switch", "I000"},
{"O177", "I001 Switch", "I001"},
{"O176", "I002 Switch", "I002"},
{"O177", "I003 Switch", "I003"},
{"O176", "I020 Switch", "I020"},
{"O177", "I021 Switch", "I021"},
{"O176", "I022 Switch", "I022"},
{"O177", "I023 Switch", "I023"},
{"O176", "I070 Switch", "I070"},
{"O177", "I071 Switch", "I071"},
{"ADDA Capture", NULL, "ADDA_INPUT"},
{"ADDA_OUTPUT", NULL, "ADDA Playback"},
};
static int mt8188_adda_dmic_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8188_afe_private *afe_priv = afe->platform_priv;
struct mtkaif_param *param = &afe_priv->mtkaif_params;
ucontrol->value.integer.value[0] = param->mtkaif_dmic_on;
return 0;
}
static int mt8188_adda_dmic_set(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8188_afe_private *afe_priv = afe->platform_priv;
struct mtkaif_param *param = &afe_priv->mtkaif_params;
int dmic_on;
dmic_on = !!ucontrol->value.integer.value[0];
dev_dbg(afe->dev, "%s(), kcontrol name %s, dmic_on %d\n",
__func__, kcontrol->id.name, dmic_on);
if (param->mtkaif_dmic_on == dmic_on)
return 0;
param->mtkaif_dmic_on = dmic_on;
return 1;
}
static const struct snd_kcontrol_new mtk_dai_adda_controls[] = {
SOC_SINGLE("ADDA_DL_GAIN", AFE_ADDA_DL_SRC2_CON1,
DL_2_GAIN_CTL_PRE_SHIFT, 65535, 0),
SOC_SINGLE_BOOL_EXT("MTKAIF_DMIC Switch", 0,
mt8188_adda_dmic_get, mt8188_adda_dmic_set),
};
static int mtk_dai_da_configure(struct mtk_base_afe *afe,
unsigned int rate, int id)
{
unsigned int val = 0;
unsigned int mask = 0;
/* set sampling rate */
mask |= DL_2_INPUT_MODE_CTL_MASK;
val |= FIELD_PREP(DL_2_INPUT_MODE_CTL_MASK,
afe_adda_dl_rate_transform(afe, rate));
/* turn off saturation */
mask |= DL_2_CH1_SATURATION_EN_CTL;
mask |= DL_2_CH2_SATURATION_EN_CTL;
/* turn off mute function */
mask |= DL_2_MUTE_CH1_OFF_CTL_PRE;
mask |= DL_2_MUTE_CH2_OFF_CTL_PRE;
val |= DL_2_MUTE_CH1_OFF_CTL_PRE;
val |= DL_2_MUTE_CH2_OFF_CTL_PRE;
/* set voice input data if input sample rate is 8k or 16k */
mask |= DL_2_VOICE_MODE_CTL_PRE;
if (rate == 8000 || rate == 16000)
val |= DL_2_VOICE_MODE_CTL_PRE;
regmap_update_bits(afe->regmap, AFE_ADDA_DL_SRC2_CON0, mask, val);
/* new 2nd sdm */
regmap_set_bits(afe->regmap, AFE_ADDA_DL_SDM_DCCOMP_CON,
DL_USE_NEW_2ND_SDM);
return 0;
}
static int mtk_dai_ad_configure(struct mtk_base_afe *afe,
unsigned int rate, int id)
{
unsigned int val;
unsigned int mask;
mask = UL_VOICE_MODE_CTL_MASK;
val = FIELD_PREP(UL_VOICE_MODE_CTL_MASK,
afe_adda_ul_rate_transform(afe, rate));
regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0,
mask, val);
return 0;
}
static int mtk_dai_adda_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8188_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_adda_priv *adda_priv = afe_priv->dai_priv[dai->id];
unsigned int rate = params_rate(params);
int id = dai->id;
int ret = 0;
dev_dbg(afe->dev, "%s(), id %d, stream %d, rate %u\n",
__func__, id, substream->stream, rate);
adda_priv->hires_required = (rate > ADDA_HIRES_THRES);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
ret = mtk_dai_da_configure(afe, rate, id);
else
ret = mtk_dai_ad_configure(afe, rate, id);
return ret;
}
static const struct snd_soc_dai_ops mtk_dai_adda_ops = {
.hw_params = mtk_dai_adda_hw_params,
};
/* dai driver */
#define MTK_ADDA_PLAYBACK_RATES (SNDRV_PCM_RATE_8000_48000 |\
SNDRV_PCM_RATE_96000 |\
SNDRV_PCM_RATE_192000)
#define MTK_ADDA_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 |\
SNDRV_PCM_RATE_48000 |\
SNDRV_PCM_RATE_96000 |\
SNDRV_PCM_RATE_192000)
#define MTK_ADDA_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver mtk_dai_adda_driver[] = {
{
.name = "DL_SRC",
.id = MT8188_AFE_IO_DL_SRC,
.playback = {
.stream_name = "ADDA Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_ADDA_PLAYBACK_RATES,
.formats = MTK_ADDA_FORMATS,
},
.ops = &mtk_dai_adda_ops,
},
{
.name = "UL_SRC",
.id = MT8188_AFE_IO_UL_SRC,
.capture = {
.stream_name = "ADDA Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_ADDA_CAPTURE_RATES,
.formats = MTK_ADDA_FORMATS,
},
.ops = &mtk_dai_adda_ops,
},
};
static int init_adda_priv_data(struct mtk_base_afe *afe)
{
struct mt8188_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_adda_priv *adda_priv;
int adda_dai_list[] = {MT8188_AFE_IO_DL_SRC, MT8188_AFE_IO_UL_SRC};
int i;
for (i = 0; i < ARRAY_SIZE(adda_dai_list); i++) {
adda_priv = devm_kzalloc(afe->dev,
sizeof(struct mtk_dai_adda_priv),
GFP_KERNEL);
if (!adda_priv)
return -ENOMEM;
afe_priv->dai_priv[adda_dai_list[i]] = adda_priv;
}
return 0;
}
int mt8188_dai_adda_register(struct mtk_base_afe *afe)
{
struct mtk_base_afe_dai *dai;
dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
if (!dai)
return -ENOMEM;
list_add(&dai->list, &afe->sub_dais);
dai->dai_drivers = mtk_dai_adda_driver;
dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_adda_driver);
dai->dapm_widgets = mtk_dai_adda_widgets;
dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_adda_widgets);
dai->dapm_routes = mtk_dai_adda_routes;
dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_adda_routes);
dai->controls = mtk_dai_adda_controls;
dai->num_controls = ARRAY_SIZE(mtk_dai_adda_controls);
return init_adda_priv_data(afe);
}
| linux-master | sound/soc/mediatek/mt8188/mt8188-dai-adda.c |
// SPDX-License-Identifier: GPL-2.0
/*
* MediaTek ALSA SoC AFE platform driver for 8188
*
* Copyright (c) 2022 MediaTek Inc.
* Author: Bicycle Tsai <[email protected]>
* Trevor Wu <[email protected]>
* Chun-Chia Chiu <[email protected]>
*/
#include <linux/arm-smccc.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/module.h>
#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/of_reserved_mem.h>
#include <linux/pm_runtime.h>
#include <linux/soc/mediatek/infracfg.h>
#include <linux/reset.h>
#include <sound/pcm_params.h>
#include "mt8188-afe-common.h"
#include "mt8188-afe-clk.h"
#include "mt8188-reg.h"
#include "../common/mtk-afe-platform-driver.h"
#include "../common/mtk-afe-fe-dai.h"
#define MT8188_MEMIF_BUFFER_BYTES_ALIGN (0x40)
#define MT8188_MEMIF_DL7_MAX_PERIOD_SIZE (0x3fff)
#define MEMIF_AXI_MINLEN 9 /* register default value */
struct mtk_dai_memif_priv {
unsigned int asys_timing_sel;
unsigned int fs_timing;
};
static const struct snd_pcm_hardware mt8188_afe_hardware = {
.info = SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_MMAP_VALID,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE |
SNDRV_PCM_FMTBIT_S32_LE,
.period_bytes_min = 64,
.period_bytes_max = 256 * 1024,
.periods_min = 2,
.periods_max = 256,
.buffer_bytes_max = 256 * 2 * 1024,
};
struct mt8188_afe_rate {
unsigned int rate;
unsigned int reg_value;
};
static const struct mt8188_afe_rate mt8188_afe_rates[] = {
{ .rate = 8000, .reg_value = 0, },
{ .rate = 12000, .reg_value = 1, },
{ .rate = 16000, .reg_value = 2, },
{ .rate = 24000, .reg_value = 3, },
{ .rate = 32000, .reg_value = 4, },
{ .rate = 48000, .reg_value = 5, },
{ .rate = 96000, .reg_value = 6, },
{ .rate = 192000, .reg_value = 7, },
{ .rate = 384000, .reg_value = 8, },
{ .rate = 7350, .reg_value = 16, },
{ .rate = 11025, .reg_value = 17, },
{ .rate = 14700, .reg_value = 18, },
{ .rate = 22050, .reg_value = 19, },
{ .rate = 29400, .reg_value = 20, },
{ .rate = 44100, .reg_value = 21, },
{ .rate = 88200, .reg_value = 22, },
{ .rate = 176400, .reg_value = 23, },
{ .rate = 352800, .reg_value = 24, },
};
int mt8188_afe_fs_timing(unsigned int rate)
{
int i;
for (i = 0; i < ARRAY_SIZE(mt8188_afe_rates); i++)
if (mt8188_afe_rates[i].rate == rate)
return mt8188_afe_rates[i].reg_value;
return -EINVAL;
}
static int mt8188_memif_fs(struct snd_pcm_substream *substream,
unsigned int rate)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_component *component = NULL;
struct mtk_base_afe *afe = NULL;
struct mt8188_afe_private *afe_priv = NULL;
struct mtk_base_afe_memif *memif = NULL;
struct mtk_dai_memif_priv *memif_priv = NULL;
int fs = mt8188_afe_fs_timing(rate);
int id = asoc_rtd_to_cpu(rtd, 0)->id;
if (id < 0)
return -EINVAL;
component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
if (!component)
return -EINVAL;
afe = snd_soc_component_get_drvdata(component);
memif = &afe->memif[id];
switch (memif->data->id) {
case MT8188_AFE_MEMIF_DL10:
fs = MT8188_ETDM_OUT3_1X_EN;
break;
case MT8188_AFE_MEMIF_UL8:
fs = MT8188_ETDM_IN1_NX_EN;
break;
case MT8188_AFE_MEMIF_UL3:
fs = MT8188_ETDM_IN2_NX_EN;
break;
default:
afe_priv = afe->platform_priv;
memif_priv = afe_priv->dai_priv[id];
if (memif_priv->fs_timing)
fs = memif_priv->fs_timing;
break;
}
return fs;
}
static int mt8188_irq_fs(struct snd_pcm_substream *substream,
unsigned int rate)
{
int fs = mt8188_memif_fs(substream, rate);
switch (fs) {
case MT8188_ETDM_IN1_NX_EN:
fs = MT8188_ETDM_IN1_1X_EN;
break;
case MT8188_ETDM_IN2_NX_EN:
fs = MT8188_ETDM_IN2_1X_EN;
break;
default:
break;
}
return fs;
}
enum {
MT8188_AFE_CM0,
MT8188_AFE_CM1,
MT8188_AFE_CM2,
MT8188_AFE_CM_NUM,
};
struct mt8188_afe_channel_merge {
int id;
int reg;
unsigned int sel_shift;
unsigned int sel_maskbit;
unsigned int sel_default;
unsigned int ch_num_shift;
unsigned int ch_num_maskbit;
unsigned int en_shift;
unsigned int en_maskbit;
unsigned int update_cnt_shift;
unsigned int update_cnt_maskbit;
unsigned int update_cnt_default;
};
static const struct mt8188_afe_channel_merge
mt8188_afe_cm[MT8188_AFE_CM_NUM] = {
[MT8188_AFE_CM0] = {
.id = MT8188_AFE_CM0,
.reg = AFE_CM0_CON,
.sel_shift = 30,
.sel_maskbit = 0x1,
.sel_default = 1,
.ch_num_shift = 2,
.ch_num_maskbit = 0x3f,
.en_shift = 0,
.en_maskbit = 0x1,
.update_cnt_shift = 16,
.update_cnt_maskbit = 0x1fff,
.update_cnt_default = 0x3,
},
[MT8188_AFE_CM1] = {
.id = MT8188_AFE_CM1,
.reg = AFE_CM1_CON,
.sel_shift = 30,
.sel_maskbit = 0x1,
.sel_default = 1,
.ch_num_shift = 2,
.ch_num_maskbit = 0x1f,
.en_shift = 0,
.en_maskbit = 0x1,
.update_cnt_shift = 16,
.update_cnt_maskbit = 0x1fff,
.update_cnt_default = 0x3,
},
[MT8188_AFE_CM2] = {
.id = MT8188_AFE_CM2,
.reg = AFE_CM2_CON,
.sel_shift = 30,
.sel_maskbit = 0x1,
.sel_default = 1,
.ch_num_shift = 2,
.ch_num_maskbit = 0x1f,
.en_shift = 0,
.en_maskbit = 0x1,
.update_cnt_shift = 16,
.update_cnt_maskbit = 0x1fff,
.update_cnt_default = 0x3,
},
};
static int mt8188_afe_memif_is_ul(int id)
{
if (id >= MT8188_AFE_MEMIF_UL_START && id < MT8188_AFE_MEMIF_END)
return 1;
else
return 0;
}
static const struct mt8188_afe_channel_merge *
mt8188_afe_found_cm(struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
int id = -EINVAL;
if (mt8188_afe_memif_is_ul(dai->id) == 0)
return NULL;
switch (dai->id) {
case MT8188_AFE_MEMIF_UL9:
id = MT8188_AFE_CM0;
break;
case MT8188_AFE_MEMIF_UL2:
id = MT8188_AFE_CM1;
break;
case MT8188_AFE_MEMIF_UL10:
id = MT8188_AFE_CM2;
break;
default:
break;
}
if (id < 0) {
dev_dbg(afe->dev, "%s, memif %d cannot find CM!\n", __func__, dai->id);
return NULL;
}
return &mt8188_afe_cm[id];
}
static int mt8188_afe_config_cm(struct mtk_base_afe *afe,
const struct mt8188_afe_channel_merge *cm,
unsigned int channels)
{
if (!cm)
return -EINVAL;
regmap_update_bits(afe->regmap,
cm->reg,
cm->sel_maskbit << cm->sel_shift,
cm->sel_default << cm->sel_shift);
regmap_update_bits(afe->regmap,
cm->reg,
cm->ch_num_maskbit << cm->ch_num_shift,
(channels - 1) << cm->ch_num_shift);
regmap_update_bits(afe->regmap,
cm->reg,
cm->update_cnt_maskbit << cm->update_cnt_shift,
cm->update_cnt_default << cm->update_cnt_shift);
return 0;
}
static int mt8188_afe_enable_cm(struct mtk_base_afe *afe,
const struct mt8188_afe_channel_merge *cm,
bool enable)
{
if (!cm)
return -EINVAL;
regmap_update_bits(afe->regmap,
cm->reg,
cm->en_maskbit << cm->en_shift,
enable << cm->en_shift);
return 0;
}
static int mt8188_afe_fe_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_pcm_runtime *runtime = substream->runtime;
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
int id = asoc_rtd_to_cpu(rtd, 0)->id;
int ret;
ret = mtk_afe_fe_startup(substream, dai);
snd_pcm_hw_constraint_step(runtime, 0,
SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
MT8188_MEMIF_BUFFER_BYTES_ALIGN);
if (id != MT8188_AFE_MEMIF_DL7)
goto out;
ret = snd_pcm_hw_constraint_minmax(runtime,
SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 1,
MT8188_MEMIF_DL7_MAX_PERIOD_SIZE);
if (ret < 0)
dev_dbg(afe->dev, "hw_constraint_minmax failed\n");
out:
return ret;
}
static void mt8188_afe_fe_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
mtk_afe_fe_shutdown(substream, dai);
}
static int mt8188_afe_fe_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
int id = asoc_rtd_to_cpu(rtd, 0)->id;
struct mtk_base_afe_memif *memif = &afe->memif[id];
const struct mtk_base_memif_data *data = memif->data;
const struct mt8188_afe_channel_merge *cm = mt8188_afe_found_cm(dai);
unsigned int channels = params_channels(params);
mt8188_afe_config_cm(afe, cm, channels);
if (data->ch_num_reg >= 0) {
regmap_update_bits(afe->regmap, data->ch_num_reg,
data->ch_num_maskbit << data->ch_num_shift,
channels << data->ch_num_shift);
}
return mtk_afe_fe_hw_params(substream, params, dai);
}
static int mt8188_afe_fe_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
const struct mt8188_afe_channel_merge *cm = mt8188_afe_found_cm(dai);
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_pcm_runtime * const runtime = substream->runtime;
int id = asoc_rtd_to_cpu(rtd, 0)->id;
struct mtk_base_afe_memif *memif = &afe->memif[id];
struct mtk_base_afe_irq *irqs = &afe->irqs[memif->irq_usage];
const struct mtk_base_irq_data *irq_data = irqs->irq_data;
unsigned int counter = runtime->period_size;
int fs;
int ret;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
mt8188_afe_enable_cm(afe, cm, true);
ret = mtk_memif_set_enable(afe, id);
if (ret) {
dev_err(afe->dev, "%s(), error, id %d, memif enable, ret %d\n",
__func__, id, ret);
return ret;
}
/* set irq counter */
regmap_update_bits(afe->regmap, irq_data->irq_cnt_reg,
irq_data->irq_cnt_maskbit << irq_data->irq_cnt_shift,
counter << irq_data->irq_cnt_shift);
/* set irq fs */
fs = afe->irq_fs(substream, runtime->rate);
if (fs < 0)
return -EINVAL;
if (irq_data->irq_fs_reg >= 0)
regmap_update_bits(afe->regmap, irq_data->irq_fs_reg,
irq_data->irq_fs_maskbit << irq_data->irq_fs_shift,
fs << irq_data->irq_fs_shift);
/* delay for uplink */
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
u32 sample_delay;
sample_delay = ((MEMIF_AXI_MINLEN + 1) * 64 +
(runtime->channels * runtime->sample_bits - 1)) /
(runtime->channels * runtime->sample_bits) + 1;
udelay(sample_delay * 1000000 / runtime->rate);
}
/* enable interrupt */
regmap_set_bits(afe->regmap, irq_data->irq_en_reg,
BIT(irq_data->irq_en_shift));
return 0;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
mt8188_afe_enable_cm(afe, cm, false);
ret = mtk_memif_set_disable(afe, id);
if (ret)
dev_err(afe->dev, "%s(), error, id %d, memif enable, ret %d\n",
__func__, id, ret);
/* disable interrupt */
regmap_clear_bits(afe->regmap, irq_data->irq_en_reg,
BIT(irq_data->irq_en_shift));
/* and clear pending IRQ */
regmap_write(afe->regmap, irq_data->irq_clr_reg,
BIT(irq_data->irq_clr_shift));
return ret;
default:
return -EINVAL;
}
}
static const struct snd_soc_dai_ops mt8188_afe_fe_dai_ops = {
.startup = mt8188_afe_fe_startup,
.shutdown = mt8188_afe_fe_shutdown,
.hw_params = mt8188_afe_fe_hw_params,
.hw_free = mtk_afe_fe_hw_free,
.prepare = mtk_afe_fe_prepare,
.trigger = mt8188_afe_fe_trigger,
};
#define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\
SNDRV_PCM_RATE_88200 |\
SNDRV_PCM_RATE_96000 |\
SNDRV_PCM_RATE_176400 |\
SNDRV_PCM_RATE_192000 |\
SNDRV_PCM_RATE_352800 |\
SNDRV_PCM_RATE_384000)
#define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver mt8188_memif_dai_driver[] = {
/* FE DAIs: memory intefaces to CPU */
{
.name = "DL2",
.id = MT8188_AFE_MEMIF_DL2,
.playback = {
.stream_name = "DL2",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8188_afe_fe_dai_ops,
},
{
.name = "DL3",
.id = MT8188_AFE_MEMIF_DL3,
.playback = {
.stream_name = "DL3",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8188_afe_fe_dai_ops,
},
{
.name = "DL6",
.id = MT8188_AFE_MEMIF_DL6,
.playback = {
.stream_name = "DL6",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8188_afe_fe_dai_ops,
},
{
.name = "DL7",
.id = MT8188_AFE_MEMIF_DL7,
.playback = {
.stream_name = "DL7",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8188_afe_fe_dai_ops,
},
{
.name = "DL8",
.id = MT8188_AFE_MEMIF_DL8,
.playback = {
.stream_name = "DL8",
.channels_min = 1,
.channels_max = 16,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8188_afe_fe_dai_ops,
},
{
.name = "DL10",
.id = MT8188_AFE_MEMIF_DL10,
.playback = {
.stream_name = "DL10",
.channels_min = 1,
.channels_max = 8,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8188_afe_fe_dai_ops,
},
{
.name = "DL11",
.id = MT8188_AFE_MEMIF_DL11,
.playback = {
.stream_name = "DL11",
.channels_min = 1,
.channels_max = 32,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8188_afe_fe_dai_ops,
},
{
.name = "UL1",
.id = MT8188_AFE_MEMIF_UL1,
.capture = {
.stream_name = "UL1",
.channels_min = 1,
.channels_max = 8,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8188_afe_fe_dai_ops,
},
{
.name = "UL2",
.id = MT8188_AFE_MEMIF_UL2,
.capture = {
.stream_name = "UL2",
.channels_min = 1,
.channels_max = 8,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8188_afe_fe_dai_ops,
},
{
.name = "UL3",
.id = MT8188_AFE_MEMIF_UL3,
.capture = {
.stream_name = "UL3",
.channels_min = 1,
.channels_max = 16,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8188_afe_fe_dai_ops,
},
{
.name = "UL4",
.id = MT8188_AFE_MEMIF_UL4,
.capture = {
.stream_name = "UL4",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8188_afe_fe_dai_ops,
},
{
.name = "UL5",
.id = MT8188_AFE_MEMIF_UL5,
.capture = {
.stream_name = "UL5",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8188_afe_fe_dai_ops,
},
{
.name = "UL6",
.id = MT8188_AFE_MEMIF_UL6,
.capture = {
.stream_name = "UL6",
.channels_min = 1,
.channels_max = 8,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8188_afe_fe_dai_ops,
},
{
.name = "UL8",
.id = MT8188_AFE_MEMIF_UL8,
.capture = {
.stream_name = "UL8",
.channels_min = 1,
.channels_max = 24,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8188_afe_fe_dai_ops,
},
{
.name = "UL9",
.id = MT8188_AFE_MEMIF_UL9,
.capture = {
.stream_name = "UL9",
.channels_min = 1,
.channels_max = 32,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8188_afe_fe_dai_ops,
},
{
.name = "UL10",
.id = MT8188_AFE_MEMIF_UL10,
.capture = {
.stream_name = "UL10",
.channels_min = 1,
.channels_max = 4,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mt8188_afe_fe_dai_ops,
},
};
static const struct snd_kcontrol_new o002_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN2, 0, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN2, 12, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN2, 20, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN2, 22, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN2_2, 6, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I072 Switch", AFE_CONN2_2, 8, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN2_5, 8, 1, 0),
};
static const struct snd_kcontrol_new o003_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN3, 1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN3, 13, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN3, 21, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN3, 23, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN3_2, 7, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I073 Switch", AFE_CONN3_2, 9, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN3_5, 9, 1, 0),
};
static const struct snd_kcontrol_new o004_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN4, 0, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I014 Switch", AFE_CONN4, 14, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN4, 24, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I074 Switch", AFE_CONN4_2, 10, 1, 0),
};
static const struct snd_kcontrol_new o005_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN5, 1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I015 Switch", AFE_CONN5, 15, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN5, 25, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I075 Switch", AFE_CONN5_2, 11, 1, 0),
};
static const struct snd_kcontrol_new o006_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN6, 0, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I016 Switch", AFE_CONN6, 16, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN6, 26, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I076 Switch", AFE_CONN6_2, 12, 1, 0),
};
static const struct snd_kcontrol_new o007_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN7, 1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I017 Switch", AFE_CONN7, 17, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN7, 27, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I077 Switch", AFE_CONN7_2, 13, 1, 0),
};
static const struct snd_kcontrol_new o008_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I018 Switch", AFE_CONN8, 18, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN8, 28, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I078 Switch", AFE_CONN8_2, 14, 1, 0),
};
static const struct snd_kcontrol_new o009_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I019 Switch", AFE_CONN9, 19, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN9, 29, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I079 Switch", AFE_CONN9_2, 15, 1, 0),
};
static const struct snd_kcontrol_new o010_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN10, 22, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I030 Switch", AFE_CONN10, 30, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN10_1, 14, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I072 Switch", AFE_CONN10_2, 8, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I080 Switch", AFE_CONN10_2, 16, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I188 Switch", AFE_CONN10_5, 28, 1, 0),
};
static const struct snd_kcontrol_new o011_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN11, 23, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I031 Switch", AFE_CONN11, 31, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN11_1, 15, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I073 Switch", AFE_CONN11_2, 9, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I081 Switch", AFE_CONN11_2, 17, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I189 Switch", AFE_CONN11_5, 29, 1, 0),
};
static const struct snd_kcontrol_new o012_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN12, 24, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I032 Switch", AFE_CONN12_1, 0, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN12_1, 16, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I074 Switch", AFE_CONN12_2, 10, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I082 Switch", AFE_CONN12_2, 18, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I190 Switch", AFE_CONN12_5, 30, 1, 0),
};
static const struct snd_kcontrol_new o013_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN13, 25, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I033 Switch", AFE_CONN13_1, 1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN13_1, 17, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I075 Switch", AFE_CONN13_2, 11, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I083 Switch", AFE_CONN13_2, 19, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I191 Switch", AFE_CONN13_5, 31, 1, 0),
};
static const struct snd_kcontrol_new o014_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN14, 26, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I034 Switch", AFE_CONN14_1, 2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN14_1, 18, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I076 Switch", AFE_CONN14_2, 12, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I084 Switch", AFE_CONN14_2, 20, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I192 Switch", AFE_CONN14_6, 0, 1, 0),
};
static const struct snd_kcontrol_new o015_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN15, 27, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I035 Switch", AFE_CONN15_1, 3, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN15_1, 19, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I077 Switch", AFE_CONN15_2, 13, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I085 Switch", AFE_CONN15_2, 21, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I193 Switch", AFE_CONN15_6, 1, 1, 0),
};
static const struct snd_kcontrol_new o016_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN16, 28, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I036 Switch", AFE_CONN16_1, 4, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN16_1, 20, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I078 Switch", AFE_CONN16_2, 14, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I086 Switch", AFE_CONN16_2, 22, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I194 Switch", AFE_CONN16_6, 2, 1, 0),
};
static const struct snd_kcontrol_new o017_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN17, 29, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I037 Switch", AFE_CONN17_1, 5, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN17_1, 21, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I079 Switch", AFE_CONN17_2, 15, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I087 Switch", AFE_CONN17_2, 23, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I195 Switch", AFE_CONN17_6, 3, 1, 0),
};
static const struct snd_kcontrol_new o018_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I080 Switch", AFE_CONN18_2, 16, 1, 0),
};
static const struct snd_kcontrol_new o019_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I081 Switch", AFE_CONN19_2, 17, 1, 0),
};
static const struct snd_kcontrol_new o020_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I082 Switch", AFE_CONN20_2, 18, 1, 0),
};
static const struct snd_kcontrol_new o021_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I083 Switch", AFE_CONN21_2, 19, 1, 0),
};
static const struct snd_kcontrol_new o022_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I084 Switch", AFE_CONN22_2, 20, 1, 0),
};
static const struct snd_kcontrol_new o023_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I085 Switch", AFE_CONN23_2, 21, 1, 0),
};
static const struct snd_kcontrol_new o024_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I086 Switch", AFE_CONN24_2, 22, 1, 0),
};
static const struct snd_kcontrol_new o025_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I087 Switch", AFE_CONN25_2, 23, 1, 0),
};
static const struct snd_kcontrol_new o026_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN26_1, 14, 1, 0),
};
static const struct snd_kcontrol_new o027_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN27_1, 15, 1, 0),
};
static const struct snd_kcontrol_new o028_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN28_1, 16, 1, 0),
};
static const struct snd_kcontrol_new o029_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN29_1, 17, 1, 0),
};
static const struct snd_kcontrol_new o030_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN30_1, 18, 1, 0),
};
static const struct snd_kcontrol_new o031_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN31_1, 19, 1, 0),
};
static const struct snd_kcontrol_new o032_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN32_1, 20, 1, 0),
};
static const struct snd_kcontrol_new o033_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN33_1, 21, 1, 0),
};
static const struct snd_kcontrol_new o034_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN34, 0, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I002 Switch", AFE_CONN34, 2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN34, 12, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN34, 20, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN34_2, 6, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I072 Switch", AFE_CONN34_2, 8, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN34_5, 8, 1, 0),
};
static const struct snd_kcontrol_new o035_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN35, 1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I003 Switch", AFE_CONN35, 3, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN35, 13, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN35, 21, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN35_2, 7, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I073 Switch", AFE_CONN35_2, 9, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN35_5, 8, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN35_5, 9, 1, 0),
};
static const struct snd_kcontrol_new o036_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN36, 0, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN36, 12, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN36, 20, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN36_2, 6, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN36_5, 8, 1, 0),
};
static const struct snd_kcontrol_new o037_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN37, 1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN37, 13, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN37, 21, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN37_2, 7, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN37_5, 9, 1, 0),
};
static const struct snd_kcontrol_new o038_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN38, 22, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN38_5, 8, 1, 0),
};
static const struct snd_kcontrol_new o039_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN39, 23, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN39_5, 9, 1, 0),
};
static const struct snd_kcontrol_new o040_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I002 Switch", AFE_CONN40, 2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN40, 12, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN40, 22, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN40_5, 8, 1, 0),
};
static const struct snd_kcontrol_new o041_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I003 Switch", AFE_CONN41, 3, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN41, 13, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN41, 23, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN41_5, 9, 1, 0),
};
static const struct snd_kcontrol_new o042_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I014 Switch", AFE_CONN42, 14, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN42, 24, 1, 0),
};
static const struct snd_kcontrol_new o043_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I015 Switch", AFE_CONN43, 15, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN43, 25, 1, 0),
};
static const struct snd_kcontrol_new o044_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I016 Switch", AFE_CONN44, 16, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN44, 26, 1, 0),
};
static const struct snd_kcontrol_new o045_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I017 Switch", AFE_CONN45, 17, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN45, 27, 1, 0),
};
static const struct snd_kcontrol_new o046_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I018 Switch", AFE_CONN46, 18, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN46, 28, 1, 0),
};
static const struct snd_kcontrol_new o047_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I019 Switch", AFE_CONN47, 19, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN47, 29, 1, 0),
};
static const struct snd_kcontrol_new o182_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN182, 20, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN182, 22, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN182, 24, 1, 0),
};
static const struct snd_kcontrol_new o183_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN183, 21, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN183, 23, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN183, 25, 1, 0),
};
static const char * const dl8_dl11_data_sel_mux_text[] = {
"dl8", "dl11",
};
static SOC_ENUM_SINGLE_DECL(dl8_dl11_data_sel_mux_enum,
AFE_DAC_CON2, 0, dl8_dl11_data_sel_mux_text);
static const struct snd_kcontrol_new dl8_dl11_data_sel_mux =
SOC_DAPM_ENUM("DL8_DL11 Sink",
dl8_dl11_data_sel_mux_enum);
static const struct snd_soc_dapm_widget mt8188_memif_widgets[] = {
/* DL6 */
SND_SOC_DAPM_MIXER("I000", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I001", SND_SOC_NOPM, 0, 0, NULL, 0),
/* DL3 */
SND_SOC_DAPM_MIXER("I020", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I021", SND_SOC_NOPM, 0, 0, NULL, 0),
/* DL11 */
SND_SOC_DAPM_MIXER("I022", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I023", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I024", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I025", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I026", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I027", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I028", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I029", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I030", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I031", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I032", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I033", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I034", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I035", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I036", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I037", SND_SOC_NOPM, 0, 0, NULL, 0),
/* DL11/DL8 */
SND_SOC_DAPM_MIXER("I046", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I047", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I048", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I049", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I050", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I051", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I052", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I053", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I054", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I055", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I056", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I057", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I058", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I059", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I060", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I061", SND_SOC_NOPM, 0, 0, NULL, 0),
/* DL2 */
SND_SOC_DAPM_MIXER("I070", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I071", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MUX("DL8_DL11 Mux",
SND_SOC_NOPM, 0, 0, &dl8_dl11_data_sel_mux),
/* UL9 */
SND_SOC_DAPM_MIXER("O002", SND_SOC_NOPM, 0, 0,
o002_mix, ARRAY_SIZE(o002_mix)),
SND_SOC_DAPM_MIXER("O003", SND_SOC_NOPM, 0, 0,
o003_mix, ARRAY_SIZE(o003_mix)),
SND_SOC_DAPM_MIXER("O004", SND_SOC_NOPM, 0, 0,
o004_mix, ARRAY_SIZE(o004_mix)),
SND_SOC_DAPM_MIXER("O005", SND_SOC_NOPM, 0, 0,
o005_mix, ARRAY_SIZE(o005_mix)),
SND_SOC_DAPM_MIXER("O006", SND_SOC_NOPM, 0, 0,
o006_mix, ARRAY_SIZE(o006_mix)),
SND_SOC_DAPM_MIXER("O007", SND_SOC_NOPM, 0, 0,
o007_mix, ARRAY_SIZE(o007_mix)),
SND_SOC_DAPM_MIXER("O008", SND_SOC_NOPM, 0, 0,
o008_mix, ARRAY_SIZE(o008_mix)),
SND_SOC_DAPM_MIXER("O009", SND_SOC_NOPM, 0, 0,
o009_mix, ARRAY_SIZE(o009_mix)),
SND_SOC_DAPM_MIXER("O010", SND_SOC_NOPM, 0, 0,
o010_mix, ARRAY_SIZE(o010_mix)),
SND_SOC_DAPM_MIXER("O011", SND_SOC_NOPM, 0, 0,
o011_mix, ARRAY_SIZE(o011_mix)),
SND_SOC_DAPM_MIXER("O012", SND_SOC_NOPM, 0, 0,
o012_mix, ARRAY_SIZE(o012_mix)),
SND_SOC_DAPM_MIXER("O013", SND_SOC_NOPM, 0, 0,
o013_mix, ARRAY_SIZE(o013_mix)),
SND_SOC_DAPM_MIXER("O014", SND_SOC_NOPM, 0, 0,
o014_mix, ARRAY_SIZE(o014_mix)),
SND_SOC_DAPM_MIXER("O015", SND_SOC_NOPM, 0, 0,
o015_mix, ARRAY_SIZE(o015_mix)),
SND_SOC_DAPM_MIXER("O016", SND_SOC_NOPM, 0, 0,
o016_mix, ARRAY_SIZE(o016_mix)),
SND_SOC_DAPM_MIXER("O017", SND_SOC_NOPM, 0, 0,
o017_mix, ARRAY_SIZE(o017_mix)),
SND_SOC_DAPM_MIXER("O018", SND_SOC_NOPM, 0, 0,
o018_mix, ARRAY_SIZE(o018_mix)),
SND_SOC_DAPM_MIXER("O019", SND_SOC_NOPM, 0, 0,
o019_mix, ARRAY_SIZE(o019_mix)),
SND_SOC_DAPM_MIXER("O020", SND_SOC_NOPM, 0, 0,
o020_mix, ARRAY_SIZE(o020_mix)),
SND_SOC_DAPM_MIXER("O021", SND_SOC_NOPM, 0, 0,
o021_mix, ARRAY_SIZE(o021_mix)),
SND_SOC_DAPM_MIXER("O022", SND_SOC_NOPM, 0, 0,
o022_mix, ARRAY_SIZE(o022_mix)),
SND_SOC_DAPM_MIXER("O023", SND_SOC_NOPM, 0, 0,
o023_mix, ARRAY_SIZE(o023_mix)),
SND_SOC_DAPM_MIXER("O024", SND_SOC_NOPM, 0, 0,
o024_mix, ARRAY_SIZE(o024_mix)),
SND_SOC_DAPM_MIXER("O025", SND_SOC_NOPM, 0, 0,
o025_mix, ARRAY_SIZE(o025_mix)),
SND_SOC_DAPM_MIXER("O026", SND_SOC_NOPM, 0, 0,
o026_mix, ARRAY_SIZE(o026_mix)),
SND_SOC_DAPM_MIXER("O027", SND_SOC_NOPM, 0, 0,
o027_mix, ARRAY_SIZE(o027_mix)),
SND_SOC_DAPM_MIXER("O028", SND_SOC_NOPM, 0, 0,
o028_mix, ARRAY_SIZE(o028_mix)),
SND_SOC_DAPM_MIXER("O029", SND_SOC_NOPM, 0, 0,
o029_mix, ARRAY_SIZE(o029_mix)),
SND_SOC_DAPM_MIXER("O030", SND_SOC_NOPM, 0, 0,
o030_mix, ARRAY_SIZE(o030_mix)),
SND_SOC_DAPM_MIXER("O031", SND_SOC_NOPM, 0, 0,
o031_mix, ARRAY_SIZE(o031_mix)),
SND_SOC_DAPM_MIXER("O032", SND_SOC_NOPM, 0, 0,
o032_mix, ARRAY_SIZE(o032_mix)),
SND_SOC_DAPM_MIXER("O033", SND_SOC_NOPM, 0, 0,
o033_mix, ARRAY_SIZE(o033_mix)),
/* UL4 */
SND_SOC_DAPM_MIXER("O034", SND_SOC_NOPM, 0, 0,
o034_mix, ARRAY_SIZE(o034_mix)),
SND_SOC_DAPM_MIXER("O035", SND_SOC_NOPM, 0, 0,
o035_mix, ARRAY_SIZE(o035_mix)),
/* UL5 */
SND_SOC_DAPM_MIXER("O036", SND_SOC_NOPM, 0, 0,
o036_mix, ARRAY_SIZE(o036_mix)),
SND_SOC_DAPM_MIXER("O037", SND_SOC_NOPM, 0, 0,
o037_mix, ARRAY_SIZE(o037_mix)),
/* UL10 */
SND_SOC_DAPM_MIXER("O038", SND_SOC_NOPM, 0, 0,
o038_mix, ARRAY_SIZE(o038_mix)),
SND_SOC_DAPM_MIXER("O039", SND_SOC_NOPM, 0, 0,
o039_mix, ARRAY_SIZE(o039_mix)),
SND_SOC_DAPM_MIXER("O182", SND_SOC_NOPM, 0, 0,
o182_mix, ARRAY_SIZE(o182_mix)),
SND_SOC_DAPM_MIXER("O183", SND_SOC_NOPM, 0, 0,
o183_mix, ARRAY_SIZE(o183_mix)),
/* UL2 */
SND_SOC_DAPM_MIXER("O040", SND_SOC_NOPM, 0, 0,
o040_mix, ARRAY_SIZE(o040_mix)),
SND_SOC_DAPM_MIXER("O041", SND_SOC_NOPM, 0, 0,
o041_mix, ARRAY_SIZE(o041_mix)),
SND_SOC_DAPM_MIXER("O042", SND_SOC_NOPM, 0, 0,
o042_mix, ARRAY_SIZE(o042_mix)),
SND_SOC_DAPM_MIXER("O043", SND_SOC_NOPM, 0, 0,
o043_mix, ARRAY_SIZE(o043_mix)),
SND_SOC_DAPM_MIXER("O044", SND_SOC_NOPM, 0, 0,
o044_mix, ARRAY_SIZE(o044_mix)),
SND_SOC_DAPM_MIXER("O045", SND_SOC_NOPM, 0, 0,
o045_mix, ARRAY_SIZE(o045_mix)),
SND_SOC_DAPM_MIXER("O046", SND_SOC_NOPM, 0, 0,
o046_mix, ARRAY_SIZE(o046_mix)),
SND_SOC_DAPM_MIXER("O047", SND_SOC_NOPM, 0, 0,
o047_mix, ARRAY_SIZE(o047_mix)),
};
static const struct snd_soc_dapm_route mt8188_memif_routes[] = {
{"I000", NULL, "DL6"},
{"I001", NULL, "DL6"},
{"I020", NULL, "DL3"},
{"I021", NULL, "DL3"},
{"I022", NULL, "DL11"},
{"I023", NULL, "DL11"},
{"I024", NULL, "DL11"},
{"I025", NULL, "DL11"},
{"I026", NULL, "DL11"},
{"I027", NULL, "DL11"},
{"I028", NULL, "DL11"},
{"I029", NULL, "DL11"},
{"I030", NULL, "DL11"},
{"I031", NULL, "DL11"},
{"I032", NULL, "DL11"},
{"I033", NULL, "DL11"},
{"I034", NULL, "DL11"},
{"I035", NULL, "DL11"},
{"I036", NULL, "DL11"},
{"I037", NULL, "DL11"},
{"DL8_DL11 Mux", "dl8", "DL8"},
{"DL8_DL11 Mux", "dl11", "DL11"},
{"I046", NULL, "DL8_DL11 Mux"},
{"I047", NULL, "DL8_DL11 Mux"},
{"I048", NULL, "DL8_DL11 Mux"},
{"I049", NULL, "DL8_DL11 Mux"},
{"I050", NULL, "DL8_DL11 Mux"},
{"I051", NULL, "DL8_DL11 Mux"},
{"I052", NULL, "DL8_DL11 Mux"},
{"I053", NULL, "DL8_DL11 Mux"},
{"I054", NULL, "DL8_DL11 Mux"},
{"I055", NULL, "DL8_DL11 Mux"},
{"I056", NULL, "DL8_DL11 Mux"},
{"I057", NULL, "DL8_DL11 Mux"},
{"I058", NULL, "DL8_DL11 Mux"},
{"I059", NULL, "DL8_DL11 Mux"},
{"I060", NULL, "DL8_DL11 Mux"},
{"I061", NULL, "DL8_DL11 Mux"},
{"I070", NULL, "DL2"},
{"I071", NULL, "DL2"},
{"UL9", NULL, "O002"},
{"UL9", NULL, "O003"},
{"UL9", NULL, "O004"},
{"UL9", NULL, "O005"},
{"UL9", NULL, "O006"},
{"UL9", NULL, "O007"},
{"UL9", NULL, "O008"},
{"UL9", NULL, "O009"},
{"UL9", NULL, "O010"},
{"UL9", NULL, "O011"},
{"UL9", NULL, "O012"},
{"UL9", NULL, "O013"},
{"UL9", NULL, "O014"},
{"UL9", NULL, "O015"},
{"UL9", NULL, "O016"},
{"UL9", NULL, "O017"},
{"UL9", NULL, "O018"},
{"UL9", NULL, "O019"},
{"UL9", NULL, "O020"},
{"UL9", NULL, "O021"},
{"UL9", NULL, "O022"},
{"UL9", NULL, "O023"},
{"UL9", NULL, "O024"},
{"UL9", NULL, "O025"},
{"UL9", NULL, "O026"},
{"UL9", NULL, "O027"},
{"UL9", NULL, "O028"},
{"UL9", NULL, "O029"},
{"UL9", NULL, "O030"},
{"UL9", NULL, "O031"},
{"UL9", NULL, "O032"},
{"UL9", NULL, "O033"},
{"UL4", NULL, "O034"},
{"UL4", NULL, "O035"},
{"UL5", NULL, "O036"},
{"UL5", NULL, "O037"},
{"UL10", NULL, "O038"},
{"UL10", NULL, "O039"},
{"UL10", NULL, "O182"},
{"UL10", NULL, "O183"},
{"UL2", NULL, "O040"},
{"UL2", NULL, "O041"},
{"UL2", NULL, "O042"},
{"UL2", NULL, "O043"},
{"UL2", NULL, "O044"},
{"UL2", NULL, "O045"},
{"UL2", NULL, "O046"},
{"UL2", NULL, "O047"},
{"O004", "I000 Switch", "I000"},
{"O005", "I001 Switch", "I001"},
{"O006", "I000 Switch", "I000"},
{"O007", "I001 Switch", "I001"},
{"O010", "I022 Switch", "I022"},
{"O011", "I023 Switch", "I023"},
{"O012", "I024 Switch", "I024"},
{"O013", "I025 Switch", "I025"},
{"O014", "I026 Switch", "I026"},
{"O015", "I027 Switch", "I027"},
{"O016", "I028 Switch", "I028"},
{"O017", "I029 Switch", "I029"},
{"O010", "I046 Switch", "I046"},
{"O011", "I047 Switch", "I047"},
{"O012", "I048 Switch", "I048"},
{"O013", "I049 Switch", "I049"},
{"O014", "I050 Switch", "I050"},
{"O015", "I051 Switch", "I051"},
{"O016", "I052 Switch", "I052"},
{"O017", "I053 Switch", "I053"},
{"O002", "I022 Switch", "I022"},
{"O003", "I023 Switch", "I023"},
{"O004", "I024 Switch", "I024"},
{"O005", "I025 Switch", "I025"},
{"O006", "I026 Switch", "I026"},
{"O007", "I027 Switch", "I027"},
{"O008", "I028 Switch", "I028"},
{"O009", "I029 Switch", "I029"},
{"O010", "I030 Switch", "I030"},
{"O011", "I031 Switch", "I031"},
{"O012", "I032 Switch", "I032"},
{"O013", "I033 Switch", "I033"},
{"O014", "I034 Switch", "I034"},
{"O015", "I035 Switch", "I035"},
{"O016", "I036 Switch", "I036"},
{"O017", "I037 Switch", "I037"},
{"O026", "I046 Switch", "I046"},
{"O027", "I047 Switch", "I047"},
{"O028", "I048 Switch", "I048"},
{"O029", "I049 Switch", "I049"},
{"O030", "I050 Switch", "I050"},
{"O031", "I051 Switch", "I051"},
{"O032", "I052 Switch", "I052"},
{"O033", "I053 Switch", "I053"},
{"O002", "I000 Switch", "I000"},
{"O003", "I001 Switch", "I001"},
{"O002", "I020 Switch", "I020"},
{"O003", "I021 Switch", "I021"},
{"O002", "I070 Switch", "I070"},
{"O003", "I071 Switch", "I071"},
{"O034", "I000 Switch", "I000"},
{"O035", "I001 Switch", "I001"},
{"O034", "I002 Switch", "I002"},
{"O035", "I003 Switch", "I003"},
{"O034", "I012 Switch", "I012"},
{"O035", "I013 Switch", "I013"},
{"O034", "I020 Switch", "I020"},
{"O035", "I021 Switch", "I021"},
{"O034", "I070 Switch", "I070"},
{"O035", "I071 Switch", "I071"},
{"O034", "I072 Switch", "I072"},
{"O035", "I073 Switch", "I073"},
{"O036", "I000 Switch", "I000"},
{"O037", "I001 Switch", "I001"},
{"O036", "I012 Switch", "I012"},
{"O037", "I013 Switch", "I013"},
{"O036", "I020 Switch", "I020"},
{"O037", "I021 Switch", "I021"},
{"O036", "I070 Switch", "I070"},
{"O037", "I071 Switch", "I071"},
{"O036", "I168 Switch", "I168"},
{"O037", "I169 Switch", "I169"},
{"O038", "I022 Switch", "I022"},
{"O039", "I023 Switch", "I023"},
{"O182", "I024 Switch", "I024"},
{"O183", "I025 Switch", "I025"},
{"O038", "I168 Switch", "I168"},
{"O039", "I169 Switch", "I169"},
{"O182", "I020 Switch", "I020"},
{"O183", "I021 Switch", "I021"},
{"O182", "I022 Switch", "I022"},
{"O183", "I023 Switch", "I023"},
{"O040", "I022 Switch", "I022"},
{"O041", "I023 Switch", "I023"},
{"O042", "I024 Switch", "I024"},
{"O043", "I025 Switch", "I025"},
{"O044", "I026 Switch", "I026"},
{"O045", "I027 Switch", "I027"},
{"O046", "I028 Switch", "I028"},
{"O047", "I029 Switch", "I029"},
{"O040", "I002 Switch", "I002"},
{"O041", "I003 Switch", "I003"},
{"O002", "I012 Switch", "I012"},
{"O003", "I013 Switch", "I013"},
{"O004", "I014 Switch", "I014"},
{"O005", "I015 Switch", "I015"},
{"O006", "I016 Switch", "I016"},
{"O007", "I017 Switch", "I017"},
{"O008", "I018 Switch", "I018"},
{"O009", "I019 Switch", "I019"},
{"O010", "I188 Switch", "I188"},
{"O011", "I189 Switch", "I189"},
{"O012", "I190 Switch", "I190"},
{"O013", "I191 Switch", "I191"},
{"O014", "I192 Switch", "I192"},
{"O015", "I193 Switch", "I193"},
{"O016", "I194 Switch", "I194"},
{"O017", "I195 Switch", "I195"},
{"O040", "I012 Switch", "I012"},
{"O041", "I013 Switch", "I013"},
{"O042", "I014 Switch", "I014"},
{"O043", "I015 Switch", "I015"},
{"O044", "I016 Switch", "I016"},
{"O045", "I017 Switch", "I017"},
{"O046", "I018 Switch", "I018"},
{"O047", "I019 Switch", "I019"},
{"O002", "I072 Switch", "I072"},
{"O003", "I073 Switch", "I073"},
{"O004", "I074 Switch", "I074"},
{"O005", "I075 Switch", "I075"},
{"O006", "I076 Switch", "I076"},
{"O007", "I077 Switch", "I077"},
{"O008", "I078 Switch", "I078"},
{"O009", "I079 Switch", "I079"},
{"O010", "I080 Switch", "I080"},
{"O011", "I081 Switch", "I081"},
{"O012", "I082 Switch", "I082"},
{"O013", "I083 Switch", "I083"},
{"O014", "I084 Switch", "I084"},
{"O015", "I085 Switch", "I085"},
{"O016", "I086 Switch", "I086"},
{"O017", "I087 Switch", "I087"},
{"O010", "I072 Switch", "I072"},
{"O011", "I073 Switch", "I073"},
{"O012", "I074 Switch", "I074"},
{"O013", "I075 Switch", "I075"},
{"O014", "I076 Switch", "I076"},
{"O015", "I077 Switch", "I077"},
{"O016", "I078 Switch", "I078"},
{"O017", "I079 Switch", "I079"},
{"O018", "I080 Switch", "I080"},
{"O019", "I081 Switch", "I081"},
{"O020", "I082 Switch", "I082"},
{"O021", "I083 Switch", "I083"},
{"O022", "I084 Switch", "I084"},
{"O023", "I085 Switch", "I085"},
{"O024", "I086 Switch", "I086"},
{"O025", "I087 Switch", "I087"},
{"O002", "I168 Switch", "I168"},
{"O003", "I169 Switch", "I169"},
{"O034", "I168 Switch", "I168"},
{"O035", "I168 Switch", "I168"},
{"O035", "I169 Switch", "I169"},
{"O040", "I168 Switch", "I168"},
{"O041", "I169 Switch", "I169"},
};
static const char * const mt8188_afe_1x_en_sel_text[] = {
"a1sys_a2sys", "a3sys", "a4sys",
};
static const unsigned int mt8188_afe_1x_en_sel_values[] = {
0, 1, 2,
};
static SOC_VALUE_ENUM_SINGLE_DECL(dl2_1x_en_sel_enum,
A3_A4_TIMING_SEL1, 18, 0x3,
mt8188_afe_1x_en_sel_text,
mt8188_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(dl3_1x_en_sel_enum,
A3_A4_TIMING_SEL1, 20, 0x3,
mt8188_afe_1x_en_sel_text,
mt8188_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(dl6_1x_en_sel_enum,
A3_A4_TIMING_SEL1, 22, 0x3,
mt8188_afe_1x_en_sel_text,
mt8188_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(dl7_1x_en_sel_enum,
A3_A4_TIMING_SEL1, 24, 0x3,
mt8188_afe_1x_en_sel_text,
mt8188_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(dl8_1x_en_sel_enum,
A3_A4_TIMING_SEL1, 26, 0x3,
mt8188_afe_1x_en_sel_text,
mt8188_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(dl10_1x_en_sel_enum,
A3_A4_TIMING_SEL1, 28, 0x3,
mt8188_afe_1x_en_sel_text,
mt8188_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(dl11_1x_en_sel_enum,
A3_A4_TIMING_SEL1, 30, 0x3,
mt8188_afe_1x_en_sel_text,
mt8188_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(ul1_1x_en_sel_enum,
A3_A4_TIMING_SEL1, 0, 0x3,
mt8188_afe_1x_en_sel_text,
mt8188_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(ul2_1x_en_sel_enum,
A3_A4_TIMING_SEL1, 2, 0x3,
mt8188_afe_1x_en_sel_text,
mt8188_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(ul3_1x_en_sel_enum,
A3_A4_TIMING_SEL1, 4, 0x3,
mt8188_afe_1x_en_sel_text,
mt8188_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(ul4_1x_en_sel_enum,
A3_A4_TIMING_SEL1, 6, 0x3,
mt8188_afe_1x_en_sel_text,
mt8188_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(ul5_1x_en_sel_enum,
A3_A4_TIMING_SEL1, 8, 0x3,
mt8188_afe_1x_en_sel_text,
mt8188_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(ul6_1x_en_sel_enum,
A3_A4_TIMING_SEL1, 10, 0x3,
mt8188_afe_1x_en_sel_text,
mt8188_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(ul8_1x_en_sel_enum,
A3_A4_TIMING_SEL1, 12, 0x3,
mt8188_afe_1x_en_sel_text,
mt8188_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(ul9_1x_en_sel_enum,
A3_A4_TIMING_SEL1, 14, 0x3,
mt8188_afe_1x_en_sel_text,
mt8188_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(ul10_1x_en_sel_enum,
A3_A4_TIMING_SEL1, 16, 0x3,
mt8188_afe_1x_en_sel_text,
mt8188_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq1_1x_en_sel_enum,
A3_A4_TIMING_SEL6, 0, 0x3,
mt8188_afe_1x_en_sel_text,
mt8188_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq2_1x_en_sel_enum,
A3_A4_TIMING_SEL6, 2, 0x3,
mt8188_afe_1x_en_sel_text,
mt8188_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq3_1x_en_sel_enum,
A3_A4_TIMING_SEL6, 4, 0x3,
mt8188_afe_1x_en_sel_text,
mt8188_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq4_1x_en_sel_enum,
A3_A4_TIMING_SEL6, 6, 0x3,
mt8188_afe_1x_en_sel_text,
mt8188_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq5_1x_en_sel_enum,
A3_A4_TIMING_SEL6, 8, 0x3,
mt8188_afe_1x_en_sel_text,
mt8188_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq6_1x_en_sel_enum,
A3_A4_TIMING_SEL6, 10, 0x3,
mt8188_afe_1x_en_sel_text,
mt8188_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq7_1x_en_sel_enum,
A3_A4_TIMING_SEL6, 12, 0x3,
mt8188_afe_1x_en_sel_text,
mt8188_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq8_1x_en_sel_enum,
A3_A4_TIMING_SEL6, 14, 0x3,
mt8188_afe_1x_en_sel_text,
mt8188_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq9_1x_en_sel_enum,
A3_A4_TIMING_SEL6, 16, 0x3,
mt8188_afe_1x_en_sel_text,
mt8188_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq10_1x_en_sel_enum,
A3_A4_TIMING_SEL6, 18, 0x3,
mt8188_afe_1x_en_sel_text,
mt8188_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq11_1x_en_sel_enum,
A3_A4_TIMING_SEL6, 20, 0x3,
mt8188_afe_1x_en_sel_text,
mt8188_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq12_1x_en_sel_enum,
A3_A4_TIMING_SEL6, 22, 0x3,
mt8188_afe_1x_en_sel_text,
mt8188_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq13_1x_en_sel_enum,
A3_A4_TIMING_SEL6, 24, 0x3,
mt8188_afe_1x_en_sel_text,
mt8188_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq14_1x_en_sel_enum,
A3_A4_TIMING_SEL6, 26, 0x3,
mt8188_afe_1x_en_sel_text,
mt8188_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq15_1x_en_sel_enum,
A3_A4_TIMING_SEL6, 28, 0x3,
mt8188_afe_1x_en_sel_text,
mt8188_afe_1x_en_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq16_1x_en_sel_enum,
A3_A4_TIMING_SEL6, 30, 0x3,
mt8188_afe_1x_en_sel_text,
mt8188_afe_1x_en_sel_values);
static const char * const mt8188_afe_fs_timing_sel_text[] = {
"asys",
"etdmout1_1x_en",
"etdmout2_1x_en",
"etdmout3_1x_en",
"etdmin1_1x_en",
"etdmin2_1x_en",
"etdmin1_nx_en",
"etdmin2_nx_en",
};
static const unsigned int mt8188_afe_fs_timing_sel_values[] = {
0,
MT8188_ETDM_OUT1_1X_EN,
MT8188_ETDM_OUT2_1X_EN,
MT8188_ETDM_OUT3_1X_EN,
MT8188_ETDM_IN1_1X_EN,
MT8188_ETDM_IN2_1X_EN,
MT8188_ETDM_IN1_NX_EN,
MT8188_ETDM_IN2_NX_EN,
};
static SOC_VALUE_ENUM_SINGLE_DECL(dl2_fs_timing_sel_enum,
SND_SOC_NOPM, 0, 0,
mt8188_afe_fs_timing_sel_text,
mt8188_afe_fs_timing_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(dl3_fs_timing_sel_enum,
SND_SOC_NOPM, 0, 0,
mt8188_afe_fs_timing_sel_text,
mt8188_afe_fs_timing_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(dl6_fs_timing_sel_enum,
SND_SOC_NOPM, 0, 0,
mt8188_afe_fs_timing_sel_text,
mt8188_afe_fs_timing_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(dl8_fs_timing_sel_enum,
SND_SOC_NOPM, 0, 0,
mt8188_afe_fs_timing_sel_text,
mt8188_afe_fs_timing_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(dl11_fs_timing_sel_enum,
SND_SOC_NOPM, 0, 0,
mt8188_afe_fs_timing_sel_text,
mt8188_afe_fs_timing_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(ul2_fs_timing_sel_enum,
SND_SOC_NOPM, 0, 0,
mt8188_afe_fs_timing_sel_text,
mt8188_afe_fs_timing_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(ul4_fs_timing_sel_enum,
SND_SOC_NOPM, 0, 0,
mt8188_afe_fs_timing_sel_text,
mt8188_afe_fs_timing_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(ul5_fs_timing_sel_enum,
SND_SOC_NOPM, 0, 0,
mt8188_afe_fs_timing_sel_text,
mt8188_afe_fs_timing_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(ul9_fs_timing_sel_enum,
SND_SOC_NOPM, 0, 0,
mt8188_afe_fs_timing_sel_text,
mt8188_afe_fs_timing_sel_values);
static SOC_VALUE_ENUM_SINGLE_DECL(ul10_fs_timing_sel_enum,
SND_SOC_NOPM, 0, 0,
mt8188_afe_fs_timing_sel_text,
mt8188_afe_fs_timing_sel_values);
static int mt8188_memif_1x_en_sel_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
struct mt8188_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_memif_priv *memif_priv;
unsigned int dai_id = kcontrol->id.device;
long val = ucontrol->value.integer.value[0];
int ret = 0;
memif_priv = afe_priv->dai_priv[dai_id];
if (val == memif_priv->asys_timing_sel)
return 0;
ret = snd_soc_put_enum_double(kcontrol, ucontrol);
memif_priv->asys_timing_sel = val;
return ret;
}
static int mt8188_asys_irq_1x_en_sel_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
struct mt8188_afe_private *afe_priv = afe->platform_priv;
unsigned int id = kcontrol->id.device;
long val = ucontrol->value.integer.value[0];
int ret = 0;
if (val == afe_priv->irq_priv[id].asys_timing_sel)
return 0;
ret = snd_soc_put_enum_double(kcontrol, ucontrol);
afe_priv->irq_priv[id].asys_timing_sel = val;
return ret;
}
static int mt8188_memif_fs_timing_sel_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
struct mt8188_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_memif_priv *memif_priv;
unsigned int dai_id = kcontrol->id.device;
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
memif_priv = afe_priv->dai_priv[dai_id];
ucontrol->value.enumerated.item[0] =
snd_soc_enum_val_to_item(e, memif_priv->fs_timing);
return 0;
}
static int mt8188_memif_fs_timing_sel_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
struct mt8188_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_memif_priv *memif_priv;
unsigned int dai_id = kcontrol->id.device;
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned int *item = ucontrol->value.enumerated.item;
unsigned int prev_item = 0;
if (item[0] >= e->items)
return -EINVAL;
memif_priv = afe_priv->dai_priv[dai_id];
prev_item = snd_soc_enum_val_to_item(e, memif_priv->fs_timing);
if (item[0] == prev_item)
return 0;
memif_priv->fs_timing = snd_soc_enum_item_to_val(e, item[0]);
return 1;
}
static const struct snd_kcontrol_new mt8188_memif_controls[] = {
MT8188_SOC_ENUM_EXT("dl2_1x_en_sel",
dl2_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8188_memif_1x_en_sel_put,
MT8188_AFE_MEMIF_DL2),
MT8188_SOC_ENUM_EXT("dl3_1x_en_sel",
dl3_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8188_memif_1x_en_sel_put,
MT8188_AFE_MEMIF_DL3),
MT8188_SOC_ENUM_EXT("dl6_1x_en_sel",
dl6_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8188_memif_1x_en_sel_put,
MT8188_AFE_MEMIF_DL6),
MT8188_SOC_ENUM_EXT("dl7_1x_en_sel",
dl7_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8188_memif_1x_en_sel_put,
MT8188_AFE_MEMIF_DL7),
MT8188_SOC_ENUM_EXT("dl8_1x_en_sel",
dl8_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8188_memif_1x_en_sel_put,
MT8188_AFE_MEMIF_DL8),
MT8188_SOC_ENUM_EXT("dl10_1x_en_sel",
dl10_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8188_memif_1x_en_sel_put,
MT8188_AFE_MEMIF_DL10),
MT8188_SOC_ENUM_EXT("dl11_1x_en_sel",
dl11_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8188_memif_1x_en_sel_put,
MT8188_AFE_MEMIF_DL11),
MT8188_SOC_ENUM_EXT("ul1_1x_en_sel",
ul1_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8188_memif_1x_en_sel_put,
MT8188_AFE_MEMIF_UL1),
MT8188_SOC_ENUM_EXT("ul2_1x_en_sel",
ul2_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8188_memif_1x_en_sel_put,
MT8188_AFE_MEMIF_UL2),
MT8188_SOC_ENUM_EXT("ul3_1x_en_sel",
ul3_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8188_memif_1x_en_sel_put,
MT8188_AFE_MEMIF_UL3),
MT8188_SOC_ENUM_EXT("ul4_1x_en_sel",
ul4_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8188_memif_1x_en_sel_put,
MT8188_AFE_MEMIF_UL4),
MT8188_SOC_ENUM_EXT("ul5_1x_en_sel",
ul5_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8188_memif_1x_en_sel_put,
MT8188_AFE_MEMIF_UL5),
MT8188_SOC_ENUM_EXT("ul6_1x_en_sel",
ul6_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8188_memif_1x_en_sel_put,
MT8188_AFE_MEMIF_UL6),
MT8188_SOC_ENUM_EXT("ul8_1x_en_sel",
ul8_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8188_memif_1x_en_sel_put,
MT8188_AFE_MEMIF_UL8),
MT8188_SOC_ENUM_EXT("ul9_1x_en_sel",
ul9_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8188_memif_1x_en_sel_put,
MT8188_AFE_MEMIF_UL9),
MT8188_SOC_ENUM_EXT("ul10_1x_en_sel",
ul10_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8188_memif_1x_en_sel_put,
MT8188_AFE_MEMIF_UL10),
MT8188_SOC_ENUM_EXT("asys_irq1_1x_en_sel",
asys_irq1_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8188_asys_irq_1x_en_sel_put,
MT8188_AFE_IRQ_13),
MT8188_SOC_ENUM_EXT("asys_irq2_1x_en_sel",
asys_irq2_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8188_asys_irq_1x_en_sel_put,
MT8188_AFE_IRQ_14),
MT8188_SOC_ENUM_EXT("asys_irq3_1x_en_sel",
asys_irq3_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8188_asys_irq_1x_en_sel_put,
MT8188_AFE_IRQ_15),
MT8188_SOC_ENUM_EXT("asys_irq4_1x_en_sel",
asys_irq4_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8188_asys_irq_1x_en_sel_put,
MT8188_AFE_IRQ_16),
MT8188_SOC_ENUM_EXT("asys_irq5_1x_en_sel",
asys_irq5_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8188_asys_irq_1x_en_sel_put,
MT8188_AFE_IRQ_17),
MT8188_SOC_ENUM_EXT("asys_irq6_1x_en_sel",
asys_irq6_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8188_asys_irq_1x_en_sel_put,
MT8188_AFE_IRQ_18),
MT8188_SOC_ENUM_EXT("asys_irq7_1x_en_sel",
asys_irq7_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8188_asys_irq_1x_en_sel_put,
MT8188_AFE_IRQ_19),
MT8188_SOC_ENUM_EXT("asys_irq8_1x_en_sel",
asys_irq8_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8188_asys_irq_1x_en_sel_put,
MT8188_AFE_IRQ_20),
MT8188_SOC_ENUM_EXT("asys_irq9_1x_en_sel",
asys_irq9_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8188_asys_irq_1x_en_sel_put,
MT8188_AFE_IRQ_21),
MT8188_SOC_ENUM_EXT("asys_irq10_1x_en_sel",
asys_irq10_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8188_asys_irq_1x_en_sel_put,
MT8188_AFE_IRQ_22),
MT8188_SOC_ENUM_EXT("asys_irq11_1x_en_sel",
asys_irq11_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8188_asys_irq_1x_en_sel_put,
MT8188_AFE_IRQ_23),
MT8188_SOC_ENUM_EXT("asys_irq12_1x_en_sel",
asys_irq12_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8188_asys_irq_1x_en_sel_put,
MT8188_AFE_IRQ_24),
MT8188_SOC_ENUM_EXT("asys_irq13_1x_en_sel",
asys_irq13_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8188_asys_irq_1x_en_sel_put,
MT8188_AFE_IRQ_25),
MT8188_SOC_ENUM_EXT("asys_irq14_1x_en_sel",
asys_irq14_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8188_asys_irq_1x_en_sel_put,
MT8188_AFE_IRQ_26),
MT8188_SOC_ENUM_EXT("asys_irq15_1x_en_sel",
asys_irq15_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8188_asys_irq_1x_en_sel_put,
MT8188_AFE_IRQ_27),
MT8188_SOC_ENUM_EXT("asys_irq16_1x_en_sel",
asys_irq16_1x_en_sel_enum,
snd_soc_get_enum_double,
mt8188_asys_irq_1x_en_sel_put,
MT8188_AFE_IRQ_28),
MT8188_SOC_ENUM_EXT("dl2_fs_timing_sel",
dl2_fs_timing_sel_enum,
mt8188_memif_fs_timing_sel_get,
mt8188_memif_fs_timing_sel_put,
MT8188_AFE_MEMIF_DL2),
MT8188_SOC_ENUM_EXT("dl3_fs_timing_sel",
dl3_fs_timing_sel_enum,
mt8188_memif_fs_timing_sel_get,
mt8188_memif_fs_timing_sel_put,
MT8188_AFE_MEMIF_DL3),
MT8188_SOC_ENUM_EXT("dl6_fs_timing_sel",
dl6_fs_timing_sel_enum,
mt8188_memif_fs_timing_sel_get,
mt8188_memif_fs_timing_sel_put,
MT8188_AFE_MEMIF_DL6),
MT8188_SOC_ENUM_EXT("dl8_fs_timing_sel",
dl8_fs_timing_sel_enum,
mt8188_memif_fs_timing_sel_get,
mt8188_memif_fs_timing_sel_put,
MT8188_AFE_MEMIF_DL8),
MT8188_SOC_ENUM_EXT("dl11_fs_timing_sel",
dl11_fs_timing_sel_enum,
mt8188_memif_fs_timing_sel_get,
mt8188_memif_fs_timing_sel_put,
MT8188_AFE_MEMIF_DL11),
MT8188_SOC_ENUM_EXT("ul2_fs_timing_sel",
ul2_fs_timing_sel_enum,
mt8188_memif_fs_timing_sel_get,
mt8188_memif_fs_timing_sel_put,
MT8188_AFE_MEMIF_UL2),
MT8188_SOC_ENUM_EXT("ul4_fs_timing_sel",
ul4_fs_timing_sel_enum,
mt8188_memif_fs_timing_sel_get,
mt8188_memif_fs_timing_sel_put,
MT8188_AFE_MEMIF_UL4),
MT8188_SOC_ENUM_EXT("ul5_fs_timing_sel",
ul5_fs_timing_sel_enum,
mt8188_memif_fs_timing_sel_get,
mt8188_memif_fs_timing_sel_put,
MT8188_AFE_MEMIF_UL5),
MT8188_SOC_ENUM_EXT("ul9_fs_timing_sel",
ul9_fs_timing_sel_enum,
mt8188_memif_fs_timing_sel_get,
mt8188_memif_fs_timing_sel_put,
MT8188_AFE_MEMIF_UL9),
MT8188_SOC_ENUM_EXT("ul10_fs_timing_sel",
ul10_fs_timing_sel_enum,
mt8188_memif_fs_timing_sel_get,
mt8188_memif_fs_timing_sel_put,
MT8188_AFE_MEMIF_UL10),
};
static const struct mtk_base_memif_data memif_data[MT8188_AFE_MEMIF_NUM] = {
[MT8188_AFE_MEMIF_DL2] = {
.name = "DL2",
.id = MT8188_AFE_MEMIF_DL2,
.reg_ofs_base = AFE_DL2_BASE,
.reg_ofs_cur = AFE_DL2_CUR,
.reg_ofs_end = AFE_DL2_END,
.fs_reg = AFE_MEMIF_AGENT_FS_CON0,
.fs_shift = 10,
.fs_maskbit = 0x1f,
.mono_reg = -1,
.mono_shift = 0,
.int_odd_flag_reg = -1,
.int_odd_flag_shift = 0,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 18,
.hd_reg = AFE_DL2_CON0,
.hd_shift = 5,
.agent_disable_reg = AUDIO_TOP_CON5,
.agent_disable_shift = 18,
.ch_num_reg = AFE_DL2_CON0,
.ch_num_shift = 0,
.ch_num_maskbit = 0x1f,
.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
.msb_shift = 18,
.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
.msb_end_shift = 18,
},
[MT8188_AFE_MEMIF_DL3] = {
.name = "DL3",
.id = MT8188_AFE_MEMIF_DL3,
.reg_ofs_base = AFE_DL3_BASE,
.reg_ofs_cur = AFE_DL3_CUR,
.reg_ofs_end = AFE_DL3_END,
.fs_reg = AFE_MEMIF_AGENT_FS_CON0,
.fs_shift = 15,
.fs_maskbit = 0x1f,
.mono_reg = -1,
.mono_shift = 0,
.int_odd_flag_reg = -1,
.int_odd_flag_shift = 0,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 19,
.hd_reg = AFE_DL3_CON0,
.hd_shift = 5,
.agent_disable_reg = AUDIO_TOP_CON5,
.agent_disable_shift = 19,
.ch_num_reg = AFE_DL3_CON0,
.ch_num_shift = 0,
.ch_num_maskbit = 0x1f,
.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
.msb_shift = 19,
.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
.msb_end_shift = 19,
},
[MT8188_AFE_MEMIF_DL6] = {
.name = "DL6",
.id = MT8188_AFE_MEMIF_DL6,
.reg_ofs_base = AFE_DL6_BASE,
.reg_ofs_cur = AFE_DL6_CUR,
.reg_ofs_end = AFE_DL6_END,
.fs_reg = AFE_MEMIF_AGENT_FS_CON1,
.fs_shift = 0,
.fs_maskbit = 0x1f,
.mono_reg = -1,
.mono_shift = 0,
.int_odd_flag_reg = -1,
.int_odd_flag_shift = 0,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 22,
.hd_reg = AFE_DL6_CON0,
.hd_shift = 5,
.agent_disable_reg = AUDIO_TOP_CON5,
.agent_disable_shift = 22,
.ch_num_reg = AFE_DL6_CON0,
.ch_num_shift = 0,
.ch_num_maskbit = 0x1f,
.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
.msb_shift = 22,
.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
.msb_end_shift = 22,
},
[MT8188_AFE_MEMIF_DL7] = {
.name = "DL7",
.id = MT8188_AFE_MEMIF_DL7,
.reg_ofs_base = AFE_DL7_BASE,
.reg_ofs_cur = AFE_DL7_CUR,
.reg_ofs_end = AFE_DL7_END,
.fs_reg = -1,
.fs_shift = 0,
.fs_maskbit = 0,
.mono_reg = -1,
.mono_shift = 0,
.int_odd_flag_reg = -1,
.int_odd_flag_shift = 0,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 23,
.hd_reg = AFE_DL7_CON0,
.hd_shift = 5,
.agent_disable_reg = AUDIO_TOP_CON5,
.agent_disable_shift = 23,
.ch_num_reg = AFE_DL7_CON0,
.ch_num_shift = 0,
.ch_num_maskbit = 0x1f,
.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
.msb_shift = 23,
.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
.msb_end_shift = 23,
},
[MT8188_AFE_MEMIF_DL8] = {
.name = "DL8",
.id = MT8188_AFE_MEMIF_DL8,
.reg_ofs_base = AFE_DL8_BASE,
.reg_ofs_cur = AFE_DL8_CUR,
.reg_ofs_end = AFE_DL8_END,
.fs_reg = AFE_MEMIF_AGENT_FS_CON1,
.fs_shift = 10,
.fs_maskbit = 0x1f,
.mono_reg = -1,
.mono_shift = 0,
.int_odd_flag_reg = -1,
.int_odd_flag_shift = 0,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 24,
.hd_reg = AFE_DL8_CON0,
.hd_shift = 6,
.agent_disable_reg = AUDIO_TOP_CON5,
.agent_disable_shift = 24,
.ch_num_reg = AFE_DL8_CON0,
.ch_num_shift = 0,
.ch_num_maskbit = 0x3f,
.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
.msb_shift = 24,
.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
.msb_end_shift = 24,
},
[MT8188_AFE_MEMIF_DL10] = {
.name = "DL10",
.id = MT8188_AFE_MEMIF_DL10,
.reg_ofs_base = AFE_DL10_BASE,
.reg_ofs_cur = AFE_DL10_CUR,
.reg_ofs_end = AFE_DL10_END,
.fs_reg = AFE_MEMIF_AGENT_FS_CON1,
.fs_shift = 20,
.fs_maskbit = 0x1f,
.mono_reg = -1,
.mono_shift = 0,
.int_odd_flag_reg = -1,
.int_odd_flag_shift = 0,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 26,
.hd_reg = AFE_DL10_CON0,
.hd_shift = 5,
.agent_disable_reg = AUDIO_TOP_CON5,
.agent_disable_shift = 26,
.ch_num_reg = AFE_DL10_CON0,
.ch_num_shift = 0,
.ch_num_maskbit = 0x1f,
.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
.msb_shift = 26,
.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
.msb_end_shift = 26,
},
[MT8188_AFE_MEMIF_DL11] = {
.name = "DL11",
.id = MT8188_AFE_MEMIF_DL11,
.reg_ofs_base = AFE_DL11_BASE,
.reg_ofs_cur = AFE_DL11_CUR,
.reg_ofs_end = AFE_DL11_END,
.fs_reg = AFE_MEMIF_AGENT_FS_CON1,
.fs_shift = 25,
.fs_maskbit = 0x1f,
.mono_reg = -1,
.mono_shift = 0,
.int_odd_flag_reg = -1,
.int_odd_flag_shift = 0,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 27,
.hd_reg = AFE_DL11_CON0,
.hd_shift = 7,
.agent_disable_reg = AUDIO_TOP_CON5,
.agent_disable_shift = 27,
.ch_num_reg = AFE_DL11_CON0,
.ch_num_shift = 0,
.ch_num_maskbit = 0x7f,
.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
.msb_shift = 27,
.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
.msb_end_shift = 27,
},
[MT8188_AFE_MEMIF_UL1] = {
.name = "UL1",
.id = MT8188_AFE_MEMIF_UL1,
.reg_ofs_base = AFE_UL1_BASE,
.reg_ofs_cur = AFE_UL1_CUR,
.reg_ofs_end = AFE_UL1_END,
.fs_reg = -1,
.fs_shift = 0,
.fs_maskbit = 0,
.mono_reg = AFE_UL1_CON0,
.mono_shift = 1,
.int_odd_flag_reg = AFE_UL1_CON0,
.int_odd_flag_shift = 0,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 1,
.hd_reg = AFE_UL1_CON0,
.hd_shift = 5,
.agent_disable_reg = AUDIO_TOP_CON5,
.agent_disable_shift = 0,
.ch_num_reg = -1,
.ch_num_shift = 0,
.ch_num_maskbit = 0,
.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
.msb_shift = 0,
.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
.msb_end_shift = 0,
},
[MT8188_AFE_MEMIF_UL2] = {
.name = "UL2",
.id = MT8188_AFE_MEMIF_UL2,
.reg_ofs_base = AFE_UL2_BASE,
.reg_ofs_cur = AFE_UL2_CUR,
.reg_ofs_end = AFE_UL2_END,
.fs_reg = AFE_MEMIF_AGENT_FS_CON2,
.fs_shift = 5,
.fs_maskbit = 0x1f,
.mono_reg = AFE_UL2_CON0,
.mono_shift = 1,
.int_odd_flag_reg = AFE_UL2_CON0,
.int_odd_flag_shift = 0,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 2,
.hd_reg = AFE_UL2_CON0,
.hd_shift = 5,
.agent_disable_reg = AUDIO_TOP_CON5,
.agent_disable_shift = 1,
.ch_num_reg = -1,
.ch_num_shift = 0,
.ch_num_maskbit = 0,
.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
.msb_shift = 1,
.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
.msb_end_shift = 1,
},
[MT8188_AFE_MEMIF_UL3] = {
.name = "UL3",
.id = MT8188_AFE_MEMIF_UL3,
.reg_ofs_base = AFE_UL3_BASE,
.reg_ofs_cur = AFE_UL3_CUR,
.reg_ofs_end = AFE_UL3_END,
.fs_reg = AFE_MEMIF_AGENT_FS_CON2,
.fs_shift = 10,
.fs_maskbit = 0x1f,
.mono_reg = AFE_UL3_CON0,
.mono_shift = 1,
.int_odd_flag_reg = AFE_UL3_CON0,
.int_odd_flag_shift = 0,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 3,
.hd_reg = AFE_UL3_CON0,
.hd_shift = 5,
.agent_disable_reg = AUDIO_TOP_CON5,
.agent_disable_shift = 2,
.ch_num_reg = -1,
.ch_num_shift = 0,
.ch_num_maskbit = 0,
.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
.msb_shift = 2,
.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
.msb_end_shift = 2,
},
[MT8188_AFE_MEMIF_UL4] = {
.name = "UL4",
.id = MT8188_AFE_MEMIF_UL4,
.reg_ofs_base = AFE_UL4_BASE,
.reg_ofs_cur = AFE_UL4_CUR,
.reg_ofs_end = AFE_UL4_END,
.fs_reg = AFE_MEMIF_AGENT_FS_CON2,
.fs_shift = 15,
.fs_maskbit = 0x1f,
.mono_reg = AFE_UL4_CON0,
.mono_shift = 1,
.int_odd_flag_reg = AFE_UL4_CON0,
.int_odd_flag_shift = 0,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 4,
.hd_reg = AFE_UL4_CON0,
.hd_shift = 5,
.agent_disable_reg = AUDIO_TOP_CON5,
.agent_disable_shift = 3,
.ch_num_reg = -1,
.ch_num_shift = 0,
.ch_num_maskbit = 0,
.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
.msb_shift = 3,
.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
.msb_end_shift = 3,
},
[MT8188_AFE_MEMIF_UL5] = {
.name = "UL5",
.id = MT8188_AFE_MEMIF_UL5,
.reg_ofs_base = AFE_UL5_BASE,
.reg_ofs_cur = AFE_UL5_CUR,
.reg_ofs_end = AFE_UL5_END,
.fs_reg = AFE_MEMIF_AGENT_FS_CON2,
.fs_shift = 20,
.fs_maskbit = 0x1f,
.mono_reg = AFE_UL5_CON0,
.mono_shift = 1,
.int_odd_flag_reg = AFE_UL5_CON0,
.int_odd_flag_shift = 0,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 5,
.hd_reg = AFE_UL5_CON0,
.hd_shift = 5,
.agent_disable_reg = AUDIO_TOP_CON5,
.agent_disable_shift = 4,
.ch_num_reg = -1,
.ch_num_shift = 0,
.ch_num_maskbit = 0,
.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
.msb_shift = 4,
.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
.msb_end_shift = 4,
},
[MT8188_AFE_MEMIF_UL6] = {
.name = "UL6",
.id = MT8188_AFE_MEMIF_UL6,
.reg_ofs_base = AFE_UL6_BASE,
.reg_ofs_cur = AFE_UL6_CUR,
.reg_ofs_end = AFE_UL6_END,
.fs_reg = -1,
.fs_shift = 0,
.fs_maskbit = 0,
.mono_reg = AFE_UL6_CON0,
.mono_shift = 1,
.int_odd_flag_reg = AFE_UL6_CON0,
.int_odd_flag_shift = 0,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 6,
.hd_reg = AFE_UL6_CON0,
.hd_shift = 5,
.agent_disable_reg = AUDIO_TOP_CON5,
.agent_disable_shift = 5,
.ch_num_reg = -1,
.ch_num_shift = 0,
.ch_num_maskbit = 0,
.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
.msb_shift = 5,
.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
.msb_end_shift = 5,
},
[MT8188_AFE_MEMIF_UL8] = {
.name = "UL8",
.id = MT8188_AFE_MEMIF_UL8,
.reg_ofs_base = AFE_UL8_BASE,
.reg_ofs_cur = AFE_UL8_CUR,
.reg_ofs_end = AFE_UL8_END,
.fs_reg = AFE_MEMIF_AGENT_FS_CON3,
.fs_shift = 5,
.fs_maskbit = 0x1f,
.mono_reg = AFE_UL8_CON0,
.mono_shift = 1,
.int_odd_flag_reg = AFE_UL8_CON0,
.int_odd_flag_shift = 0,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 8,
.hd_reg = AFE_UL8_CON0,
.hd_shift = 5,
.agent_disable_reg = AUDIO_TOP_CON5,
.agent_disable_shift = 7,
.ch_num_reg = -1,
.ch_num_shift = 0,
.ch_num_maskbit = 0,
.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
.msb_shift = 7,
.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
.msb_end_shift = 7,
},
[MT8188_AFE_MEMIF_UL9] = {
.name = "UL9",
.id = MT8188_AFE_MEMIF_UL9,
.reg_ofs_base = AFE_UL9_BASE,
.reg_ofs_cur = AFE_UL9_CUR,
.reg_ofs_end = AFE_UL9_END,
.fs_reg = AFE_MEMIF_AGENT_FS_CON3,
.fs_shift = 10,
.fs_maskbit = 0x1f,
.mono_reg = AFE_UL9_CON0,
.mono_shift = 1,
.int_odd_flag_reg = AFE_UL9_CON0,
.int_odd_flag_shift = 0,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 9,
.hd_reg = AFE_UL9_CON0,
.hd_shift = 5,
.agent_disable_reg = AUDIO_TOP_CON5,
.agent_disable_shift = 8,
.ch_num_reg = -1,
.ch_num_shift = 0,
.ch_num_maskbit = 0,
.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
.msb_shift = 8,
.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
.msb_end_shift = 8,
},
[MT8188_AFE_MEMIF_UL10] = {
.name = "UL10",
.id = MT8188_AFE_MEMIF_UL10,
.reg_ofs_base = AFE_UL10_BASE,
.reg_ofs_cur = AFE_UL10_CUR,
.reg_ofs_end = AFE_UL10_END,
.fs_reg = AFE_MEMIF_AGENT_FS_CON3,
.fs_shift = 15,
.fs_maskbit = 0x1f,
.mono_reg = AFE_UL10_CON0,
.mono_shift = 1,
.int_odd_flag_reg = AFE_UL10_CON0,
.int_odd_flag_shift = 0,
.enable_reg = AFE_DAC_CON0,
.enable_shift = 10,
.hd_reg = AFE_UL10_CON0,
.hd_shift = 5,
.agent_disable_reg = AUDIO_TOP_CON5,
.agent_disable_shift = 9,
.ch_num_reg = -1,
.ch_num_shift = 0,
.ch_num_maskbit = 0,
.msb_reg = AFE_NORMAL_BASE_ADR_MSB,
.msb_shift = 9,
.msb_end_reg = AFE_NORMAL_END_ADR_MSB,
.msb_end_shift = 9,
},
};
static const struct mtk_base_irq_data irq_data[MT8188_AFE_IRQ_NUM] = {
[MT8188_AFE_IRQ_1] = {
.id = MT8188_AFE_IRQ_1,
.irq_cnt_reg = -1,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0,
.irq_fs_reg = -1,
.irq_fs_shift = 0,
.irq_fs_maskbit = 0,
.irq_en_reg = AFE_IRQ1_CON,
.irq_en_shift = 31,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = 0,
.irq_status_shift = 16,
},
[MT8188_AFE_IRQ_2] = {
.id = MT8188_AFE_IRQ_2,
.irq_cnt_reg = -1,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0,
.irq_fs_reg = -1,
.irq_fs_shift = 0,
.irq_fs_maskbit = 0,
.irq_en_reg = AFE_IRQ2_CON,
.irq_en_shift = 31,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = 1,
.irq_status_shift = 17,
},
[MT8188_AFE_IRQ_3] = {
.id = MT8188_AFE_IRQ_3,
.irq_cnt_reg = AFE_IRQ3_CON,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0xffffff,
.irq_fs_reg = -1,
.irq_fs_shift = 0,
.irq_fs_maskbit = 0,
.irq_en_reg = AFE_IRQ3_CON,
.irq_en_shift = 31,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = 2,
.irq_status_shift = 18,
},
[MT8188_AFE_IRQ_8] = {
.id = MT8188_AFE_IRQ_8,
.irq_cnt_reg = -1,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0,
.irq_fs_reg = -1,
.irq_fs_shift = 0,
.irq_fs_maskbit = 0,
.irq_en_reg = AFE_IRQ8_CON,
.irq_en_shift = 31,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = 7,
.irq_status_shift = 23,
},
[MT8188_AFE_IRQ_9] = {
.id = MT8188_AFE_IRQ_9,
.irq_cnt_reg = AFE_IRQ9_CON,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0xffffff,
.irq_fs_reg = -1,
.irq_fs_shift = 0,
.irq_fs_maskbit = 0,
.irq_en_reg = AFE_IRQ9_CON,
.irq_en_shift = 31,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = 8,
.irq_status_shift = 24,
},
[MT8188_AFE_IRQ_10] = {
.id = MT8188_AFE_IRQ_10,
.irq_cnt_reg = -1,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0,
.irq_fs_reg = -1,
.irq_fs_shift = 0,
.irq_fs_maskbit = 0,
.irq_en_reg = AFE_IRQ10_CON,
.irq_en_shift = 31,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = 9,
.irq_status_shift = 25,
},
[MT8188_AFE_IRQ_13] = {
.id = MT8188_AFE_IRQ_13,
.irq_cnt_reg = ASYS_IRQ1_CON,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0xffffff,
.irq_fs_reg = ASYS_IRQ1_CON,
.irq_fs_shift = 24,
.irq_fs_maskbit = 0x1ffff,
.irq_en_reg = ASYS_IRQ1_CON,
.irq_en_shift = 31,
.irq_clr_reg = ASYS_IRQ_CLR,
.irq_clr_shift = 0,
.irq_status_shift = 0,
},
[MT8188_AFE_IRQ_14] = {
.id = MT8188_AFE_IRQ_14,
.irq_cnt_reg = ASYS_IRQ2_CON,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0xffffff,
.irq_fs_reg = ASYS_IRQ2_CON,
.irq_fs_shift = 24,
.irq_fs_maskbit = 0x1ffff,
.irq_en_reg = ASYS_IRQ2_CON,
.irq_en_shift = 31,
.irq_clr_reg = ASYS_IRQ_CLR,
.irq_clr_shift = 1,
.irq_status_shift = 1,
},
[MT8188_AFE_IRQ_15] = {
.id = MT8188_AFE_IRQ_15,
.irq_cnt_reg = ASYS_IRQ3_CON,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0xffffff,
.irq_fs_reg = ASYS_IRQ3_CON,
.irq_fs_shift = 24,
.irq_fs_maskbit = 0x1ffff,
.irq_en_reg = ASYS_IRQ3_CON,
.irq_en_shift = 31,
.irq_clr_reg = ASYS_IRQ_CLR,
.irq_clr_shift = 2,
.irq_status_shift = 2,
},
[MT8188_AFE_IRQ_16] = {
.id = MT8188_AFE_IRQ_16,
.irq_cnt_reg = ASYS_IRQ4_CON,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0xffffff,
.irq_fs_reg = ASYS_IRQ4_CON,
.irq_fs_shift = 24,
.irq_fs_maskbit = 0x1ffff,
.irq_en_reg = ASYS_IRQ4_CON,
.irq_en_shift = 31,
.irq_clr_reg = ASYS_IRQ_CLR,
.irq_clr_shift = 3,
.irq_status_shift = 3,
},
[MT8188_AFE_IRQ_17] = {
.id = MT8188_AFE_IRQ_17,
.irq_cnt_reg = ASYS_IRQ5_CON,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0xffffff,
.irq_fs_reg = ASYS_IRQ5_CON,
.irq_fs_shift = 24,
.irq_fs_maskbit = 0x1ffff,
.irq_en_reg = ASYS_IRQ5_CON,
.irq_en_shift = 31,
.irq_clr_reg = ASYS_IRQ_CLR,
.irq_clr_shift = 4,
.irq_status_shift = 4,
},
[MT8188_AFE_IRQ_18] = {
.id = MT8188_AFE_IRQ_18,
.irq_cnt_reg = ASYS_IRQ6_CON,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0xffffff,
.irq_fs_reg = ASYS_IRQ6_CON,
.irq_fs_shift = 24,
.irq_fs_maskbit = 0x1ffff,
.irq_en_reg = ASYS_IRQ6_CON,
.irq_en_shift = 31,
.irq_clr_reg = ASYS_IRQ_CLR,
.irq_clr_shift = 5,
.irq_status_shift = 5,
},
[MT8188_AFE_IRQ_19] = {
.id = MT8188_AFE_IRQ_19,
.irq_cnt_reg = ASYS_IRQ7_CON,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0xffffff,
.irq_fs_reg = ASYS_IRQ7_CON,
.irq_fs_shift = 24,
.irq_fs_maskbit = 0x1ffff,
.irq_en_reg = ASYS_IRQ7_CON,
.irq_en_shift = 31,
.irq_clr_reg = ASYS_IRQ_CLR,
.irq_clr_shift = 6,
.irq_status_shift = 6,
},
[MT8188_AFE_IRQ_20] = {
.id = MT8188_AFE_IRQ_20,
.irq_cnt_reg = ASYS_IRQ8_CON,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0xffffff,
.irq_fs_reg = ASYS_IRQ8_CON,
.irq_fs_shift = 24,
.irq_fs_maskbit = 0x1ffff,
.irq_en_reg = ASYS_IRQ8_CON,
.irq_en_shift = 31,
.irq_clr_reg = ASYS_IRQ_CLR,
.irq_clr_shift = 7,
.irq_status_shift = 7,
},
[MT8188_AFE_IRQ_21] = {
.id = MT8188_AFE_IRQ_21,
.irq_cnt_reg = ASYS_IRQ9_CON,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0xffffff,
.irq_fs_reg = ASYS_IRQ9_CON,
.irq_fs_shift = 24,
.irq_fs_maskbit = 0x1ffff,
.irq_en_reg = ASYS_IRQ9_CON,
.irq_en_shift = 31,
.irq_clr_reg = ASYS_IRQ_CLR,
.irq_clr_shift = 8,
.irq_status_shift = 8,
},
[MT8188_AFE_IRQ_22] = {
.id = MT8188_AFE_IRQ_22,
.irq_cnt_reg = ASYS_IRQ10_CON,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0xffffff,
.irq_fs_reg = ASYS_IRQ10_CON,
.irq_fs_shift = 24,
.irq_fs_maskbit = 0x1ffff,
.irq_en_reg = ASYS_IRQ10_CON,
.irq_en_shift = 31,
.irq_clr_reg = ASYS_IRQ_CLR,
.irq_clr_shift = 9,
.irq_status_shift = 9,
},
[MT8188_AFE_IRQ_23] = {
.id = MT8188_AFE_IRQ_23,
.irq_cnt_reg = ASYS_IRQ11_CON,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0xffffff,
.irq_fs_reg = ASYS_IRQ11_CON,
.irq_fs_shift = 24,
.irq_fs_maskbit = 0x1ffff,
.irq_en_reg = ASYS_IRQ11_CON,
.irq_en_shift = 31,
.irq_clr_reg = ASYS_IRQ_CLR,
.irq_clr_shift = 10,
.irq_status_shift = 10,
},
[MT8188_AFE_IRQ_24] = {
.id = MT8188_AFE_IRQ_24,
.irq_cnt_reg = ASYS_IRQ12_CON,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0xffffff,
.irq_fs_reg = ASYS_IRQ12_CON,
.irq_fs_shift = 24,
.irq_fs_maskbit = 0x1ffff,
.irq_en_reg = ASYS_IRQ12_CON,
.irq_en_shift = 31,
.irq_clr_reg = ASYS_IRQ_CLR,
.irq_clr_shift = 11,
.irq_status_shift = 11,
},
[MT8188_AFE_IRQ_25] = {
.id = MT8188_AFE_IRQ_25,
.irq_cnt_reg = ASYS_IRQ13_CON,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0xffffff,
.irq_fs_reg = ASYS_IRQ13_CON,
.irq_fs_shift = 24,
.irq_fs_maskbit = 0x1ffff,
.irq_en_reg = ASYS_IRQ13_CON,
.irq_en_shift = 31,
.irq_clr_reg = ASYS_IRQ_CLR,
.irq_clr_shift = 12,
.irq_status_shift = 12,
},
[MT8188_AFE_IRQ_26] = {
.id = MT8188_AFE_IRQ_26,
.irq_cnt_reg = ASYS_IRQ14_CON,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0xffffff,
.irq_fs_reg = ASYS_IRQ14_CON,
.irq_fs_shift = 24,
.irq_fs_maskbit = 0x1ffff,
.irq_en_reg = ASYS_IRQ14_CON,
.irq_en_shift = 31,
.irq_clr_reg = ASYS_IRQ_CLR,
.irq_clr_shift = 13,
.irq_status_shift = 13,
},
[MT8188_AFE_IRQ_27] = {
.id = MT8188_AFE_IRQ_27,
.irq_cnt_reg = ASYS_IRQ15_CON,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0xffffff,
.irq_fs_reg = ASYS_IRQ15_CON,
.irq_fs_shift = 24,
.irq_fs_maskbit = 0x1ffff,
.irq_en_reg = ASYS_IRQ15_CON,
.irq_en_shift = 31,
.irq_clr_reg = ASYS_IRQ_CLR,
.irq_clr_shift = 14,
.irq_status_shift = 14,
},
[MT8188_AFE_IRQ_28] = {
.id = MT8188_AFE_IRQ_28,
.irq_cnt_reg = ASYS_IRQ16_CON,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0xffffff,
.irq_fs_reg = ASYS_IRQ16_CON,
.irq_fs_shift = 24,
.irq_fs_maskbit = 0x1ffff,
.irq_en_reg = ASYS_IRQ16_CON,
.irq_en_shift = 31,
.irq_clr_reg = ASYS_IRQ_CLR,
.irq_clr_shift = 15,
.irq_status_shift = 15,
},
};
static const int mt8188_afe_memif_const_irqs[MT8188_AFE_MEMIF_NUM] = {
[MT8188_AFE_MEMIF_DL2] = MT8188_AFE_IRQ_13,
[MT8188_AFE_MEMIF_DL3] = MT8188_AFE_IRQ_14,
[MT8188_AFE_MEMIF_DL6] = MT8188_AFE_IRQ_15,
[MT8188_AFE_MEMIF_DL7] = MT8188_AFE_IRQ_1,
[MT8188_AFE_MEMIF_DL8] = MT8188_AFE_IRQ_16,
[MT8188_AFE_MEMIF_DL10] = MT8188_AFE_IRQ_17,
[MT8188_AFE_MEMIF_DL11] = MT8188_AFE_IRQ_18,
[MT8188_AFE_MEMIF_UL1] = MT8188_AFE_IRQ_3,
[MT8188_AFE_MEMIF_UL2] = MT8188_AFE_IRQ_19,
[MT8188_AFE_MEMIF_UL3] = MT8188_AFE_IRQ_20,
[MT8188_AFE_MEMIF_UL4] = MT8188_AFE_IRQ_21,
[MT8188_AFE_MEMIF_UL5] = MT8188_AFE_IRQ_22,
[MT8188_AFE_MEMIF_UL6] = MT8188_AFE_IRQ_9,
[MT8188_AFE_MEMIF_UL8] = MT8188_AFE_IRQ_23,
[MT8188_AFE_MEMIF_UL9] = MT8188_AFE_IRQ_24,
[MT8188_AFE_MEMIF_UL10] = MT8188_AFE_IRQ_25,
};
static bool mt8188_is_volatile_reg(struct device *dev, unsigned int reg)
{
/* these auto-gen reg has read-only bit, so put it as volatile */
/* volatile reg cannot be cached, so cannot be set when power off */
switch (reg) {
case AUDIO_TOP_CON0:
case AUDIO_TOP_CON1:
case AUDIO_TOP_CON3:
case AUDIO_TOP_CON4:
case AUDIO_TOP_CON5:
case AUDIO_TOP_CON6:
case ASYS_IRQ_CLR:
case ASYS_IRQ_STATUS:
case ASYS_IRQ_MON1:
case ASYS_IRQ_MON2:
case AFE_IRQ_MCU_CLR:
case AFE_IRQ_STATUS:
case AFE_IRQ3_CON_MON:
case AFE_IRQ_MCU_MON2:
case ADSP_IRQ_STATUS:
case AUDIO_TOP_STA0:
case AUDIO_TOP_STA1:
case AFE_GAIN1_CUR:
case AFE_GAIN2_CUR:
case AFE_IEC_BURST_INFO:
case AFE_IEC_CHL_STAT0:
case AFE_IEC_CHL_STAT1:
case AFE_IEC_CHR_STAT0:
case AFE_IEC_CHR_STAT1:
case AFE_SPDIFIN_CHSTS1:
case AFE_SPDIFIN_CHSTS2:
case AFE_SPDIFIN_CHSTS3:
case AFE_SPDIFIN_CHSTS4:
case AFE_SPDIFIN_CHSTS5:
case AFE_SPDIFIN_CHSTS6:
case AFE_SPDIFIN_DEBUG1:
case AFE_SPDIFIN_DEBUG2:
case AFE_SPDIFIN_DEBUG3:
case AFE_SPDIFIN_DEBUG4:
case AFE_SPDIFIN_EC:
case AFE_SPDIFIN_CKLOCK_CFG:
case AFE_SPDIFIN_BR_DBG1:
case AFE_SPDIFIN_CKFBDIV:
case AFE_SPDIFIN_INT_EXT:
case AFE_SPDIFIN_INT_EXT2:
case SPDIFIN_FREQ_STATUS:
case SPDIFIN_USERCODE1:
case SPDIFIN_USERCODE2:
case SPDIFIN_USERCODE3:
case SPDIFIN_USERCODE4:
case SPDIFIN_USERCODE5:
case SPDIFIN_USERCODE6:
case SPDIFIN_USERCODE7:
case SPDIFIN_USERCODE8:
case SPDIFIN_USERCODE9:
case SPDIFIN_USERCODE10:
case SPDIFIN_USERCODE11:
case SPDIFIN_USERCODE12:
case AFE_LINEIN_APLL_TUNER_MON:
case AFE_EARC_APLL_TUNER_MON:
case AFE_CM0_MON:
case AFE_CM1_MON:
case AFE_CM2_MON:
case AFE_MPHONE_MULTI_DET_MON0:
case AFE_MPHONE_MULTI_DET_MON1:
case AFE_MPHONE_MULTI_DET_MON2:
case AFE_MPHONE_MULTI2_DET_MON0:
case AFE_MPHONE_MULTI2_DET_MON1:
case AFE_MPHONE_MULTI2_DET_MON2:
case AFE_ADDA_MTKAIF_MON0:
case AFE_ADDA_MTKAIF_MON1:
case AFE_AUD_PAD_TOP:
case AFE_ADDA6_MTKAIF_MON0:
case AFE_ADDA6_MTKAIF_MON1:
case AFE_ADDA6_SRC_DEBUG_MON0:
case AFE_ADDA6_UL_SRC_MON0:
case AFE_ADDA6_UL_SRC_MON1:
case AFE_ASRC11_NEW_CON8:
case AFE_ASRC11_NEW_CON9:
case AFE_ASRC12_NEW_CON8:
case AFE_ASRC12_NEW_CON9:
case AFE_LRCK_CNT:
case AFE_DAC_MON0:
case AFE_DL2_CUR:
case AFE_DL3_CUR:
case AFE_DL6_CUR:
case AFE_DL7_CUR:
case AFE_DL8_CUR:
case AFE_DL10_CUR:
case AFE_DL11_CUR:
case AFE_UL1_CUR:
case AFE_UL2_CUR:
case AFE_UL3_CUR:
case AFE_UL4_CUR:
case AFE_UL5_CUR:
case AFE_UL6_CUR:
case AFE_UL8_CUR:
case AFE_UL9_CUR:
case AFE_UL10_CUR:
case AFE_DL8_CHK_SUM1:
case AFE_DL8_CHK_SUM2:
case AFE_DL8_CHK_SUM3:
case AFE_DL8_CHK_SUM4:
case AFE_DL8_CHK_SUM5:
case AFE_DL8_CHK_SUM6:
case AFE_DL10_CHK_SUM1:
case AFE_DL10_CHK_SUM2:
case AFE_DL10_CHK_SUM3:
case AFE_DL10_CHK_SUM4:
case AFE_DL10_CHK_SUM5:
case AFE_DL10_CHK_SUM6:
case AFE_DL11_CHK_SUM1:
case AFE_DL11_CHK_SUM2:
case AFE_DL11_CHK_SUM3:
case AFE_DL11_CHK_SUM4:
case AFE_DL11_CHK_SUM5:
case AFE_DL11_CHK_SUM6:
case AFE_UL1_CHK_SUM1:
case AFE_UL1_CHK_SUM2:
case AFE_UL2_CHK_SUM1:
case AFE_UL2_CHK_SUM2:
case AFE_UL3_CHK_SUM1:
case AFE_UL3_CHK_SUM2:
case AFE_UL4_CHK_SUM1:
case AFE_UL4_CHK_SUM2:
case AFE_UL5_CHK_SUM1:
case AFE_UL5_CHK_SUM2:
case AFE_UL6_CHK_SUM1:
case AFE_UL6_CHK_SUM2:
case AFE_UL8_CHK_SUM1:
case AFE_UL8_CHK_SUM2:
case AFE_DL2_CHK_SUM1:
case AFE_DL2_CHK_SUM2:
case AFE_DL3_CHK_SUM1:
case AFE_DL3_CHK_SUM2:
case AFE_DL6_CHK_SUM1:
case AFE_DL6_CHK_SUM2:
case AFE_DL7_CHK_SUM1:
case AFE_DL7_CHK_SUM2:
case AFE_UL9_CHK_SUM1:
case AFE_UL9_CHK_SUM2:
case AFE_BUS_MON1:
case UL1_MOD2AGT_CNT_LAT:
case UL2_MOD2AGT_CNT_LAT:
case UL3_MOD2AGT_CNT_LAT:
case UL4_MOD2AGT_CNT_LAT:
case UL5_MOD2AGT_CNT_LAT:
case UL6_MOD2AGT_CNT_LAT:
case UL8_MOD2AGT_CNT_LAT:
case UL9_MOD2AGT_CNT_LAT:
case UL10_MOD2AGT_CNT_LAT:
case AFE_MEMIF_BUF_FULL_MON:
case AFE_MEMIF_BUF_MON1:
case AFE_MEMIF_BUF_MON3:
case AFE_MEMIF_BUF_MON4:
case AFE_MEMIF_BUF_MON5:
case AFE_MEMIF_BUF_MON6:
case AFE_MEMIF_BUF_MON7:
case AFE_MEMIF_BUF_MON8:
case AFE_MEMIF_BUF_MON9:
case AFE_MEMIF_BUF_MON10:
case DL2_AGENT2MODULE_CNT:
case DL3_AGENT2MODULE_CNT:
case DL6_AGENT2MODULE_CNT:
case DL7_AGENT2MODULE_CNT:
case DL8_AGENT2MODULE_CNT:
case DL10_AGENT2MODULE_CNT:
case DL11_AGENT2MODULE_CNT:
case UL1_MODULE2AGENT_CNT:
case UL2_MODULE2AGENT_CNT:
case UL3_MODULE2AGENT_CNT:
case UL4_MODULE2AGENT_CNT:
case UL5_MODULE2AGENT_CNT:
case UL6_MODULE2AGENT_CNT:
case UL8_MODULE2AGENT_CNT:
case UL9_MODULE2AGENT_CNT:
case UL10_MODULE2AGENT_CNT:
case AFE_DMIC0_SRC_DEBUG_MON0:
case AFE_DMIC0_UL_SRC_MON0:
case AFE_DMIC0_UL_SRC_MON1:
case AFE_DMIC1_SRC_DEBUG_MON0:
case AFE_DMIC1_UL_SRC_MON0:
case AFE_DMIC1_UL_SRC_MON1:
case AFE_DMIC2_SRC_DEBUG_MON0:
case AFE_DMIC2_UL_SRC_MON0:
case AFE_DMIC2_UL_SRC_MON1:
case AFE_DMIC3_SRC_DEBUG_MON0:
case AFE_DMIC3_UL_SRC_MON0:
case AFE_DMIC3_UL_SRC_MON1:
case DMIC_GAIN1_CUR:
case DMIC_GAIN2_CUR:
case DMIC_GAIN3_CUR:
case DMIC_GAIN4_CUR:
case ETDM_IN1_MONITOR:
case ETDM_IN2_MONITOR:
case ETDM_OUT1_MONITOR:
case ETDM_OUT2_MONITOR:
case ETDM_OUT3_MONITOR:
case AFE_ADDA_SRC_DEBUG_MON0:
case AFE_ADDA_SRC_DEBUG_MON1:
case AFE_ADDA_DL_SDM_FIFO_MON:
case AFE_ADDA_DL_SRC_LCH_MON:
case AFE_ADDA_DL_SRC_RCH_MON:
case AFE_ADDA_DL_SDM_OUT_MON:
case AFE_GASRC0_NEW_CON8:
case AFE_GASRC0_NEW_CON9:
case AFE_GASRC0_NEW_CON12:
case AFE_GASRC1_NEW_CON8:
case AFE_GASRC1_NEW_CON9:
case AFE_GASRC1_NEW_CON12:
case AFE_GASRC2_NEW_CON8:
case AFE_GASRC2_NEW_CON9:
case AFE_GASRC2_NEW_CON12:
case AFE_GASRC3_NEW_CON8:
case AFE_GASRC3_NEW_CON9:
case AFE_GASRC3_NEW_CON12:
case AFE_GASRC4_NEW_CON8:
case AFE_GASRC4_NEW_CON9:
case AFE_GASRC4_NEW_CON12:
case AFE_GASRC5_NEW_CON8:
case AFE_GASRC5_NEW_CON9:
case AFE_GASRC5_NEW_CON12:
case AFE_GASRC6_NEW_CON8:
case AFE_GASRC6_NEW_CON9:
case AFE_GASRC6_NEW_CON12:
case AFE_GASRC7_NEW_CON8:
case AFE_GASRC7_NEW_CON9:
case AFE_GASRC7_NEW_CON12:
case AFE_GASRC8_NEW_CON8:
case AFE_GASRC8_NEW_CON9:
case AFE_GASRC8_NEW_CON12:
case AFE_GASRC9_NEW_CON8:
case AFE_GASRC9_NEW_CON9:
case AFE_GASRC9_NEW_CON12:
case AFE_GASRC10_NEW_CON8:
case AFE_GASRC10_NEW_CON9:
case AFE_GASRC10_NEW_CON12:
case AFE_GASRC11_NEW_CON8:
case AFE_GASRC11_NEW_CON9:
case AFE_GASRC11_NEW_CON12:
return true;
default:
return false;
};
}
static const struct regmap_config mt8188_afe_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.volatile_reg = mt8188_is_volatile_reg,
.max_register = AFE_MAX_REGISTER,
.num_reg_defaults_raw = ((AFE_MAX_REGISTER / 4) + 1),
.cache_type = REGCACHE_FLAT,
};
#define AFE_IRQ_CLR_BITS (0x387)
#define ASYS_IRQ_CLR_BITS (0xffff)
static irqreturn_t mt8188_afe_irq_handler(int irq_id, void *dev_id)
{
struct mtk_base_afe *afe = dev_id;
unsigned int val = 0;
unsigned int asys_irq_clr_bits = 0;
unsigned int afe_irq_clr_bits = 0;
unsigned int irq_status_bits = 0;
unsigned int irq_clr_bits = 0;
unsigned int mcu_irq_mask = 0;
int i = 0;
int ret = 0;
ret = regmap_read(afe->regmap, AFE_IRQ_STATUS, &val);
if (ret) {
dev_err(afe->dev, "%s irq status err\n", __func__);
afe_irq_clr_bits = AFE_IRQ_CLR_BITS;
asys_irq_clr_bits = ASYS_IRQ_CLR_BITS;
goto err_irq;
}
ret = regmap_read(afe->regmap, AFE_IRQ_MASK, &mcu_irq_mask);
if (ret) {
dev_err(afe->dev, "%s read irq mask err\n", __func__);
afe_irq_clr_bits = AFE_IRQ_CLR_BITS;
asys_irq_clr_bits = ASYS_IRQ_CLR_BITS;
goto err_irq;
}
/* only clr cpu irq */
val &= mcu_irq_mask;
for (i = 0; i < MT8188_AFE_MEMIF_NUM; i++) {
struct mtk_base_afe_memif *memif = &afe->memif[i];
struct mtk_base_irq_data const *irq_data;
if (memif->irq_usage < 0)
continue;
irq_data = afe->irqs[memif->irq_usage].irq_data;
irq_status_bits = BIT(irq_data->irq_status_shift);
irq_clr_bits = BIT(irq_data->irq_clr_shift);
if (!(val & irq_status_bits))
continue;
if (irq_data->irq_clr_reg == ASYS_IRQ_CLR)
asys_irq_clr_bits |= irq_clr_bits;
else
afe_irq_clr_bits |= irq_clr_bits;
snd_pcm_period_elapsed(memif->substream);
}
err_irq:
/* clear irq */
if (asys_irq_clr_bits)
regmap_write(afe->regmap, ASYS_IRQ_CLR, asys_irq_clr_bits);
if (afe_irq_clr_bits)
regmap_write(afe->regmap, AFE_IRQ_MCU_CLR, afe_irq_clr_bits);
return IRQ_HANDLED;
}
static int mt8188_afe_runtime_suspend(struct device *dev)
{
struct mtk_base_afe *afe = dev_get_drvdata(dev);
struct mt8188_afe_private *afe_priv = afe->platform_priv;
if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
goto skip_regmap;
mt8188_afe_disable_main_clock(afe);
regcache_cache_only(afe->regmap, true);
regcache_mark_dirty(afe->regmap);
skip_regmap:
mt8188_afe_disable_reg_rw_clk(afe);
return 0;
}
static int mt8188_afe_runtime_resume(struct device *dev)
{
struct mtk_base_afe *afe = dev_get_drvdata(dev);
struct mt8188_afe_private *afe_priv = afe->platform_priv;
struct arm_smccc_res res;
arm_smccc_smc(MTK_SIP_AUDIO_CONTROL,
MTK_AUDIO_SMC_OP_DOMAIN_SIDEBANDS,
0, 0, 0, 0, 0, 0, &res);
mt8188_afe_enable_reg_rw_clk(afe);
if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
goto skip_regmap;
regcache_cache_only(afe->regmap, false);
regcache_sync(afe->regmap);
mt8188_afe_enable_main_clock(afe);
skip_regmap:
return 0;
}
static int mt8188_afe_component_probe(struct snd_soc_component *component)
{
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
int ret;
snd_soc_component_init_regmap(component, afe->regmap);
ret = mtk_afe_add_sub_dai_control(component);
return ret;
}
static const struct snd_soc_component_driver mt8188_afe_component = {
.name = AFE_PCM_NAME,
.pointer = mtk_afe_pcm_pointer,
.pcm_construct = mtk_afe_pcm_new,
.probe = mt8188_afe_component_probe,
};
static int init_memif_priv_data(struct mtk_base_afe *afe)
{
struct mt8188_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_memif_priv *memif_priv;
int i;
for (i = MT8188_AFE_MEMIF_START; i < MT8188_AFE_MEMIF_END; i++) {
memif_priv = devm_kzalloc(afe->dev,
sizeof(struct mtk_dai_memif_priv),
GFP_KERNEL);
if (!memif_priv)
return -ENOMEM;
afe_priv->dai_priv[i] = memif_priv;
}
return 0;
}
static int mt8188_dai_memif_register(struct mtk_base_afe *afe)
{
struct mtk_base_afe_dai *dai;
dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
if (!dai)
return -ENOMEM;
list_add(&dai->list, &afe->sub_dais);
dai->dai_drivers = mt8188_memif_dai_driver;
dai->num_dai_drivers = ARRAY_SIZE(mt8188_memif_dai_driver);
dai->dapm_widgets = mt8188_memif_widgets;
dai->num_dapm_widgets = ARRAY_SIZE(mt8188_memif_widgets);
dai->dapm_routes = mt8188_memif_routes;
dai->num_dapm_routes = ARRAY_SIZE(mt8188_memif_routes);
dai->controls = mt8188_memif_controls;
dai->num_controls = ARRAY_SIZE(mt8188_memif_controls);
return init_memif_priv_data(afe);
}
typedef int (*dai_register_cb)(struct mtk_base_afe *);
static const dai_register_cb dai_register_cbs[] = {
mt8188_dai_adda_register,
mt8188_dai_etdm_register,
mt8188_dai_pcm_register,
mt8188_dai_memif_register,
};
static const struct reg_sequence mt8188_afe_reg_defaults[] = {
{ AFE_IRQ_MASK, 0x387ffff },
{ AFE_IRQ3_CON, BIT(30) },
{ AFE_IRQ9_CON, BIT(30) },
{ ETDM_IN1_CON4, 0x12000100 },
{ ETDM_IN2_CON4, 0x12000100 },
};
static const struct reg_sequence mt8188_cg_patch[] = {
{ AUDIO_TOP_CON0, 0xfffffffb },
{ AUDIO_TOP_CON1, 0xfffffff8 },
};
static int mt8188_afe_init_registers(struct mtk_base_afe *afe)
{
return regmap_multi_reg_write(afe->regmap,
mt8188_afe_reg_defaults,
ARRAY_SIZE(mt8188_afe_reg_defaults));
}
static int mt8188_afe_parse_of(struct mtk_base_afe *afe,
struct device_node *np)
{
#if IS_ENABLED(CONFIG_SND_SOC_MT6359)
struct mt8188_afe_private *afe_priv = afe->platform_priv;
afe_priv->topckgen = syscon_regmap_lookup_by_phandle(afe->dev->of_node,
"mediatek,topckgen");
if (IS_ERR(afe_priv->topckgen))
return dev_err_probe(afe->dev, PTR_ERR(afe_priv->topckgen),
"%s() Cannot find topckgen controller\n",
__func__);
#endif
return 0;
}
#define MT8188_DELAY_US 10
#define MT8188_TIMEOUT_US USEC_PER_SEC
static int bus_protect_enable(struct regmap *regmap)
{
int ret;
u32 val;
u32 mask;
val = 0;
mask = MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP1;
regmap_write(regmap, MT8188_TOP_AXI_PROT_EN_2_SET, mask);
ret = regmap_read_poll_timeout(regmap, MT8188_TOP_AXI_PROT_EN_2_STA,
val, (val & mask) == mask,
MT8188_DELAY_US, MT8188_TIMEOUT_US);
if (ret)
return ret;
val = 0;
mask = MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP2;
regmap_write(regmap, MT8188_TOP_AXI_PROT_EN_2_SET, mask);
ret = regmap_read_poll_timeout(regmap, MT8188_TOP_AXI_PROT_EN_2_STA,
val, (val & mask) == mask,
MT8188_DELAY_US, MT8188_TIMEOUT_US);
return ret;
}
static int bus_protect_disable(struct regmap *regmap)
{
int ret;
u32 val;
u32 mask;
val = 0;
mask = MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP2;
regmap_write(regmap, MT8188_TOP_AXI_PROT_EN_2_CLR, mask);
ret = regmap_read_poll_timeout(regmap, MT8188_TOP_AXI_PROT_EN_2_STA,
val, !(val & mask),
MT8188_DELAY_US, MT8188_TIMEOUT_US);
if (ret)
return ret;
val = 0;
mask = MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP1;
regmap_write(regmap, MT8188_TOP_AXI_PROT_EN_2_CLR, mask);
ret = regmap_read_poll_timeout(regmap, MT8188_TOP_AXI_PROT_EN_2_STA,
val, !(val & mask),
MT8188_DELAY_US, MT8188_TIMEOUT_US);
return ret;
}
static int mt8188_afe_pcm_dev_probe(struct platform_device *pdev)
{
struct mtk_base_afe *afe;
struct mt8188_afe_private *afe_priv;
struct device *dev = &pdev->dev;
struct reset_control *rstc;
struct regmap *infra_ao;
int i, irq_id, ret;
ret = of_reserved_mem_device_init(dev);
if (ret)
dev_dbg(dev, "failed to assign memory region: %d\n", ret);
ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(33));
if (ret)
return ret;
afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
if (!afe)
return -ENOMEM;
afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),
GFP_KERNEL);
if (!afe->platform_priv)
return -ENOMEM;
afe_priv = afe->platform_priv;
afe->dev = &pdev->dev;
afe->base_addr = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(afe->base_addr))
return dev_err_probe(dev, PTR_ERR(afe->base_addr),
"AFE base_addr not found\n");
infra_ao = syscon_regmap_lookup_by_phandle(dev->of_node,
"mediatek,infracfg");
if (IS_ERR(infra_ao))
return dev_err_probe(dev, PTR_ERR(infra_ao),
"%s() Cannot find infra_ao controller\n",
__func__);
/* reset controller to reset audio regs before regmap cache */
rstc = devm_reset_control_get_exclusive(dev, "audiosys");
if (IS_ERR(rstc))
return dev_err_probe(dev, PTR_ERR(rstc),
"could not get audiosys reset\n");
ret = bus_protect_enable(infra_ao);
if (ret) {
dev_err(dev, "bus_protect_enable failed\n");
return ret;
}
ret = reset_control_reset(rstc);
if (ret) {
dev_err(dev, "failed to trigger audio reset:%d\n", ret);
return ret;
}
ret = bus_protect_disable(infra_ao);
if (ret) {
dev_err(dev, "bus_protect_disable failed\n");
return ret;
}
/* initial audio related clock */
ret = mt8188_afe_init_clock(afe);
if (ret)
return dev_err_probe(dev, ret, "init clock error");
spin_lock_init(&afe_priv->afe_ctrl_lock);
mutex_init(&afe->irq_alloc_lock);
/* irq initialize */
afe->irqs_size = MT8188_AFE_IRQ_NUM;
afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
GFP_KERNEL);
if (!afe->irqs)
return -ENOMEM;
for (i = 0; i < afe->irqs_size; i++)
afe->irqs[i].irq_data = &irq_data[i];
/* init memif */
afe->memif_size = MT8188_AFE_MEMIF_NUM;
afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),
GFP_KERNEL);
if (!afe->memif)
return -ENOMEM;
for (i = 0; i < afe->memif_size; i++) {
afe->memif[i].data = &memif_data[i];
afe->memif[i].irq_usage = mt8188_afe_memif_const_irqs[i];
afe->memif[i].const_irq = 1;
afe->irqs[afe->memif[i].irq_usage].irq_occupyed = true;
}
/* request irq */
irq_id = platform_get_irq(pdev, 0);
if (irq_id < 0)
return dev_err_probe(dev, irq_id, "no irq found");
ret = devm_request_irq(dev, irq_id, mt8188_afe_irq_handler,
IRQF_TRIGGER_NONE, "asys-isr", (void *)afe);
if (ret)
return dev_err_probe(dev, ret, "could not request_irq for asys-isr\n");
/* init sub_dais */
INIT_LIST_HEAD(&afe->sub_dais);
for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) {
ret = dai_register_cbs[i](afe);
if (ret)
return dev_err_probe(dev, ret, "dai register i %d fail\n", i);
}
/* init dai_driver and component_driver */
ret = mtk_afe_combine_sub_dai(afe);
if (ret)
return dev_err_probe(dev, ret, "mtk_afe_combine_sub_dai fail\n");
afe->mtk_afe_hardware = &mt8188_afe_hardware;
afe->memif_fs = mt8188_memif_fs;
afe->irq_fs = mt8188_irq_fs;
afe->runtime_resume = mt8188_afe_runtime_resume;
afe->runtime_suspend = mt8188_afe_runtime_suspend;
platform_set_drvdata(pdev, afe);
ret = mt8188_afe_parse_of(afe, pdev->dev.of_node);
if (ret)
return ret;
ret = devm_pm_runtime_enable(dev);
if (ret)
return ret;
/* enable clock for regcache get default value from hw */
afe_priv->pm_runtime_bypass_reg_ctl = true;
ret = pm_runtime_resume_and_get(dev);
if (ret)
return dev_err_probe(dev, ret, "failed to resume device\n");
afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr,
&mt8188_afe_regmap_config);
if (IS_ERR(afe->regmap)) {
ret = PTR_ERR(afe->regmap);
goto err_pm_put;
}
ret = regmap_register_patch(afe->regmap, mt8188_cg_patch,
ARRAY_SIZE(mt8188_cg_patch));
if (ret < 0) {
dev_info(dev, "Failed to apply cg patch\n");
goto err_pm_put;
}
/* register component */
ret = devm_snd_soc_register_component(dev, &mt8188_afe_component,
afe->dai_drivers, afe->num_dai_drivers);
if (ret) {
dev_warn(dev, "err_platform\n");
goto err_pm_put;
}
mt8188_afe_init_registers(afe);
pm_runtime_put_sync(&pdev->dev);
afe_priv->pm_runtime_bypass_reg_ctl = false;
regcache_cache_only(afe->regmap, true);
regcache_mark_dirty(afe->regmap);
return 0;
err_pm_put:
pm_runtime_put_sync(dev);
return ret;
}
static const struct of_device_id mt8188_afe_pcm_dt_match[] = {
{ .compatible = "mediatek,mt8188-afe", },
{},
};
MODULE_DEVICE_TABLE(of, mt8188_afe_pcm_dt_match);
static const struct dev_pm_ops mt8188_afe_pm_ops = {
SET_RUNTIME_PM_OPS(mt8188_afe_runtime_suspend,
mt8188_afe_runtime_resume, NULL)
};
static struct platform_driver mt8188_afe_pcm_driver = {
.driver = {
.name = "mt8188-audio",
.of_match_table = mt8188_afe_pcm_dt_match,
.pm = &mt8188_afe_pm_ops,
},
.probe = mt8188_afe_pcm_dev_probe,
};
module_platform_driver(mt8188_afe_pcm_driver);
MODULE_DESCRIPTION("MediaTek SoC AFE platform driver for ALSA 8188");
MODULE_AUTHOR("Chun-Chia.Chiu <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/mediatek/mt8188/mt8188-afe-pcm.c |
// SPDX-License-Identifier: GPL-2.0
/*
* MediaTek ALSA SoC Audio DAI eTDM Control
*
* Copyright (c) 2022 MediaTek Inc.
* Author: Bicycle Tsai <[email protected]>
* Trevor Wu <[email protected]>
* Chun-Chia Chiu <[email protected]>
*/
#include <linux/bitfield.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <sound/pcm_params.h>
#include "mt8188-afe-clk.h"
#include "mt8188-afe-common.h"
#include "mt8188-reg.h"
#define MT8188_ETDM_MAX_CHANNELS 16
#define MT8188_ETDM_NORMAL_MAX_BCK_RATE 24576000
#define ETDM_TO_DAI_ID(x) ((x) + MT8188_AFE_IO_ETDM_START)
#define ENUM_TO_STR(x) #x
enum {
SUPPLY_SEQ_APLL,
SUPPLY_SEQ_ETDM_MCLK,
SUPPLY_SEQ_ETDM_CG,
SUPPLY_SEQ_DPTX_EN,
SUPPLY_SEQ_ETDM_EN,
};
enum {
MTK_DAI_ETDM_FORMAT_I2S = 0,
MTK_DAI_ETDM_FORMAT_LJ,
MTK_DAI_ETDM_FORMAT_RJ,
MTK_DAI_ETDM_FORMAT_EIAJ,
MTK_DAI_ETDM_FORMAT_DSPA,
MTK_DAI_ETDM_FORMAT_DSPB,
};
enum {
MTK_DAI_ETDM_DATA_ONE_PIN = 0,
MTK_DAI_ETDM_DATA_MULTI_PIN,
};
enum {
ETDM_IN,
ETDM_OUT,
};
enum {
COWORK_ETDM_NONE = 0,
COWORK_ETDM_IN1_M = 2,
COWORK_ETDM_IN1_S = 3,
COWORK_ETDM_IN2_M = 4,
COWORK_ETDM_IN2_S = 5,
COWORK_ETDM_OUT1_M = 10,
COWORK_ETDM_OUT1_S = 11,
COWORK_ETDM_OUT2_M = 12,
COWORK_ETDM_OUT2_S = 13,
COWORK_ETDM_OUT3_M = 14,
COWORK_ETDM_OUT3_S = 15,
};
enum {
ETDM_RELATCH_TIMING_A1A2SYS,
ETDM_RELATCH_TIMING_A3SYS,
ETDM_RELATCH_TIMING_A4SYS,
};
enum {
ETDM_SYNC_NONE,
ETDM_SYNC_FROM_IN1 = 2,
ETDM_SYNC_FROM_IN2 = 4,
ETDM_SYNC_FROM_OUT1 = 10,
ETDM_SYNC_FROM_OUT2 = 12,
ETDM_SYNC_FROM_OUT3 = 14,
};
struct etdm_con_reg {
unsigned int con0;
unsigned int con1;
unsigned int con2;
unsigned int con3;
unsigned int con4;
unsigned int con5;
};
struct mtk_dai_etdm_rate {
unsigned int rate;
unsigned int reg_value;
};
struct mtk_dai_etdm_priv {
unsigned int data_mode;
bool slave_mode;
bool lrck_inv;
bool bck_inv;
unsigned int rate;
unsigned int format;
unsigned int slots;
unsigned int lrck_width;
unsigned int mclk_freq;
unsigned int mclk_fixed_apll;
unsigned int mclk_apll;
unsigned int mclk_dir;
int cowork_source_id; //dai id
unsigned int cowork_slv_count;
int cowork_slv_id[MT8188_AFE_IO_ETDM_NUM - 1]; //dai_id
bool in_disable_ch[MT8188_ETDM_MAX_CHANNELS];
};
static const struct mtk_dai_etdm_rate mt8188_etdm_rates[] = {
{ .rate = 8000, .reg_value = 0, },
{ .rate = 12000, .reg_value = 1, },
{ .rate = 16000, .reg_value = 2, },
{ .rate = 24000, .reg_value = 3, },
{ .rate = 32000, .reg_value = 4, },
{ .rate = 48000, .reg_value = 5, },
{ .rate = 96000, .reg_value = 7, },
{ .rate = 192000, .reg_value = 9, },
{ .rate = 384000, .reg_value = 11, },
{ .rate = 11025, .reg_value = 16, },
{ .rate = 22050, .reg_value = 17, },
{ .rate = 44100, .reg_value = 18, },
{ .rate = 88200, .reg_value = 19, },
{ .rate = 176400, .reg_value = 20, },
{ .rate = 352800, .reg_value = 21, },
};
static int get_etdm_fs_timing(unsigned int rate)
{
int i;
for (i = 0; i < ARRAY_SIZE(mt8188_etdm_rates); i++)
if (mt8188_etdm_rates[i].rate == rate)
return mt8188_etdm_rates[i].reg_value;
return -EINVAL;
}
static unsigned int get_etdm_ch_fixup(unsigned int channels)
{
if (channels > 16)
return 24;
else if (channels > 8)
return 16;
else if (channels > 4)
return 8;
else if (channels > 2)
return 4;
else
return 2;
}
static int get_etdm_reg(unsigned int dai_id, struct etdm_con_reg *etdm_reg)
{
switch (dai_id) {
case MT8188_AFE_IO_ETDM1_IN:
etdm_reg->con0 = ETDM_IN1_CON0;
etdm_reg->con1 = ETDM_IN1_CON1;
etdm_reg->con2 = ETDM_IN1_CON2;
etdm_reg->con3 = ETDM_IN1_CON3;
etdm_reg->con4 = ETDM_IN1_CON4;
etdm_reg->con5 = ETDM_IN1_CON5;
break;
case MT8188_AFE_IO_ETDM2_IN:
etdm_reg->con0 = ETDM_IN2_CON0;
etdm_reg->con1 = ETDM_IN2_CON1;
etdm_reg->con2 = ETDM_IN2_CON2;
etdm_reg->con3 = ETDM_IN2_CON3;
etdm_reg->con4 = ETDM_IN2_CON4;
etdm_reg->con5 = ETDM_IN2_CON5;
break;
case MT8188_AFE_IO_ETDM1_OUT:
etdm_reg->con0 = ETDM_OUT1_CON0;
etdm_reg->con1 = ETDM_OUT1_CON1;
etdm_reg->con2 = ETDM_OUT1_CON2;
etdm_reg->con3 = ETDM_OUT1_CON3;
etdm_reg->con4 = ETDM_OUT1_CON4;
etdm_reg->con5 = ETDM_OUT1_CON5;
break;
case MT8188_AFE_IO_ETDM2_OUT:
etdm_reg->con0 = ETDM_OUT2_CON0;
etdm_reg->con1 = ETDM_OUT2_CON1;
etdm_reg->con2 = ETDM_OUT2_CON2;
etdm_reg->con3 = ETDM_OUT2_CON3;
etdm_reg->con4 = ETDM_OUT2_CON4;
etdm_reg->con5 = ETDM_OUT2_CON5;
break;
case MT8188_AFE_IO_ETDM3_OUT:
case MT8188_AFE_IO_DPTX:
etdm_reg->con0 = ETDM_OUT3_CON0;
etdm_reg->con1 = ETDM_OUT3_CON1;
etdm_reg->con2 = ETDM_OUT3_CON2;
etdm_reg->con3 = ETDM_OUT3_CON3;
etdm_reg->con4 = ETDM_OUT3_CON4;
etdm_reg->con5 = ETDM_OUT3_CON5;
break;
default:
return -EINVAL;
}
return 0;
}
static int get_etdm_dir(unsigned int dai_id)
{
switch (dai_id) {
case MT8188_AFE_IO_ETDM1_IN:
case MT8188_AFE_IO_ETDM2_IN:
return ETDM_IN;
case MT8188_AFE_IO_ETDM1_OUT:
case MT8188_AFE_IO_ETDM2_OUT:
case MT8188_AFE_IO_ETDM3_OUT:
return ETDM_OUT;
default:
return -EINVAL;
}
}
static int get_etdm_wlen(unsigned int bitwidth)
{
return bitwidth <= 16 ? 16 : 32;
}
static bool is_valid_etdm_dai(int dai_id)
{
switch (dai_id) {
case MT8188_AFE_IO_ETDM1_IN:
fallthrough;
case MT8188_AFE_IO_ETDM2_IN:
fallthrough;
case MT8188_AFE_IO_ETDM1_OUT:
fallthrough;
case MT8188_AFE_IO_ETDM2_OUT:
fallthrough;
case MT8188_AFE_IO_DPTX:
fallthrough;
case MT8188_AFE_IO_ETDM3_OUT:
return true;
default:
return false;
}
}
static int is_cowork_mode(struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8188_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_etdm_priv *etdm_data;
if (!is_valid_etdm_dai(dai->id))
return -EINVAL;
etdm_data = afe_priv->dai_priv[dai->id];
return (etdm_data->cowork_slv_count > 0 ||
etdm_data->cowork_source_id != COWORK_ETDM_NONE);
}
static int sync_to_dai_id(int source_sel)
{
switch (source_sel) {
case ETDM_SYNC_FROM_IN1:
return MT8188_AFE_IO_ETDM1_IN;
case ETDM_SYNC_FROM_IN2:
return MT8188_AFE_IO_ETDM2_IN;
case ETDM_SYNC_FROM_OUT1:
return MT8188_AFE_IO_ETDM1_OUT;
case ETDM_SYNC_FROM_OUT2:
return MT8188_AFE_IO_ETDM2_OUT;
case ETDM_SYNC_FROM_OUT3:
return MT8188_AFE_IO_ETDM3_OUT;
default:
return 0;
}
}
static int get_etdm_cowork_master_id(struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8188_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_etdm_priv *etdm_data;
int dai_id;
if (!is_valid_etdm_dai(dai->id))
return -EINVAL;
etdm_data = afe_priv->dai_priv[dai->id];
dai_id = etdm_data->cowork_source_id;
if (dai_id == COWORK_ETDM_NONE)
dai_id = dai->id;
return dai_id;
}
static int mtk_dai_etdm_get_cg_id_by_dai_id(int dai_id)
{
switch (dai_id) {
case MT8188_AFE_IO_DPTX:
return MT8188_CLK_AUD_HDMI_OUT;
case MT8188_AFE_IO_ETDM1_IN:
return MT8188_CLK_AUD_TDM_IN;
case MT8188_AFE_IO_ETDM2_IN:
return MT8188_CLK_AUD_I2SIN;
case MT8188_AFE_IO_ETDM1_OUT:
return MT8188_CLK_AUD_TDM_OUT;
case MT8188_AFE_IO_ETDM2_OUT:
return MT8188_CLK_AUD_I2S_OUT;
case MT8188_AFE_IO_ETDM3_OUT:
return MT8188_CLK_AUD_HDMI_OUT;
default:
return -EINVAL;
}
}
static int mtk_dai_etdm_get_clk_id_by_dai_id(int dai_id)
{
switch (dai_id) {
case MT8188_AFE_IO_DPTX:
return MT8188_CLK_TOP_DPTX_M_SEL;
case MT8188_AFE_IO_ETDM1_IN:
return MT8188_CLK_TOP_I2SI1_M_SEL;
case MT8188_AFE_IO_ETDM2_IN:
return MT8188_CLK_TOP_I2SI2_M_SEL;
case MT8188_AFE_IO_ETDM1_OUT:
return MT8188_CLK_TOP_I2SO1_M_SEL;
case MT8188_AFE_IO_ETDM2_OUT:
return MT8188_CLK_TOP_I2SO2_M_SEL;
case MT8188_AFE_IO_ETDM3_OUT:
default:
return -EINVAL;
}
}
static int mtk_dai_etdm_get_clkdiv_id_by_dai_id(int dai_id)
{
switch (dai_id) {
case MT8188_AFE_IO_DPTX:
return MT8188_CLK_TOP_APLL12_DIV9;
case MT8188_AFE_IO_ETDM1_IN:
return MT8188_CLK_TOP_APLL12_DIV0;
case MT8188_AFE_IO_ETDM2_IN:
return MT8188_CLK_TOP_APLL12_DIV1;
case MT8188_AFE_IO_ETDM1_OUT:
return MT8188_CLK_TOP_APLL12_DIV2;
case MT8188_AFE_IO_ETDM2_OUT:
return MT8188_CLK_TOP_APLL12_DIV3;
case MT8188_AFE_IO_ETDM3_OUT:
default:
return -EINVAL;
}
}
static int get_etdm_id_by_name(struct mtk_base_afe *afe,
const char *name)
{
if (!strncmp(name, "ETDM1_IN", strlen("ETDM1_IN")))
return MT8188_AFE_IO_ETDM1_IN;
else if (!strncmp(name, "ETDM2_IN", strlen("ETDM2_IN")))
return MT8188_AFE_IO_ETDM2_IN;
else if (!strncmp(name, "ETDM1_OUT", strlen("ETDM1_OUT")))
return MT8188_AFE_IO_ETDM1_OUT;
else if (!strncmp(name, "ETDM2_OUT", strlen("ETDM2_OUT")))
return MT8188_AFE_IO_ETDM2_OUT;
else if (!strncmp(name, "ETDM3_OUT", strlen("ETDM3_OUT")))
return MT8188_AFE_IO_ETDM3_OUT;
else if (!strncmp(name, "DPTX", strlen("DPTX")))
return MT8188_AFE_IO_ETDM3_OUT;
else
return -EINVAL;
}
static struct mtk_dai_etdm_priv *get_etdm_priv_by_name(struct mtk_base_afe *afe,
const char *name)
{
struct mt8188_afe_private *afe_priv = afe->platform_priv;
int dai_id = get_etdm_id_by_name(afe, name);
if (dai_id < MT8188_AFE_IO_ETDM_START ||
dai_id >= MT8188_AFE_IO_ETDM_END)
return NULL;
return afe_priv->dai_priv[dai_id];
}
static int mtk_dai_etdm_enable_mclk(struct mtk_base_afe *afe, int dai_id)
{
struct mt8188_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_etdm_priv *etdm_data;
struct etdm_con_reg etdm_reg;
unsigned int val = 0;
unsigned int mask;
int clkmux_id = mtk_dai_etdm_get_clk_id_by_dai_id(dai_id);
int clkdiv_id = mtk_dai_etdm_get_clkdiv_id_by_dai_id(dai_id);
int apll_clk_id;
int apll;
int ret;
if (!is_valid_etdm_dai(dai_id))
return -EINVAL;
etdm_data = afe_priv->dai_priv[dai_id];
apll = etdm_data->mclk_apll;
apll_clk_id = mt8188_afe_get_mclk_source_clk_id(apll);
if (clkmux_id < 0 || clkdiv_id < 0)
return -EINVAL;
if (apll_clk_id < 0)
return apll_clk_id;
ret = get_etdm_reg(dai_id, &etdm_reg);
if (ret < 0)
return ret;
mask = ETDM_CON1_MCLK_OUTPUT;
if (etdm_data->mclk_dir == SND_SOC_CLOCK_OUT)
val = ETDM_CON1_MCLK_OUTPUT;
regmap_update_bits(afe->regmap, etdm_reg.con1, mask, val);
/* enable parent clock before select apll*/
mt8188_afe_enable_clk(afe, afe_priv->clk[clkmux_id]);
/* select apll */
ret = mt8188_afe_set_clk_parent(afe, afe_priv->clk[clkmux_id],
afe_priv->clk[apll_clk_id]);
if (ret)
return ret;
/* set rate */
ret = mt8188_afe_set_clk_rate(afe, afe_priv->clk[clkdiv_id],
etdm_data->mclk_freq);
mt8188_afe_enable_clk(afe, afe_priv->clk[clkdiv_id]);
return 0;
}
static int mtk_dai_etdm_disable_mclk(struct mtk_base_afe *afe, int dai_id)
{
struct mt8188_afe_private *afe_priv = afe->platform_priv;
int clkmux_id = mtk_dai_etdm_get_clk_id_by_dai_id(dai_id);
int clkdiv_id = mtk_dai_etdm_get_clkdiv_id_by_dai_id(dai_id);
if (clkmux_id < 0 || clkdiv_id < 0)
return -EINVAL;
mt8188_afe_disable_clk(afe, afe_priv->clk[clkdiv_id]);
mt8188_afe_disable_clk(afe, afe_priv->clk[clkmux_id]);
return 0;
}
static int mtk_afe_etdm_apll_connect(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_dapm_widget *w = sink;
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mtk_dai_etdm_priv *etdm_priv;
int cur_apll;
int need_apll;
etdm_priv = get_etdm_priv_by_name(afe, w->name);
if (!etdm_priv) {
dev_dbg(afe->dev, "etdm_priv == NULL\n");
return 0;
}
cur_apll = mt8188_get_apll_by_name(afe, source->name);
need_apll = mt8188_get_apll_by_rate(afe, etdm_priv->rate);
return (need_apll == cur_apll) ? 1 : 0;
}
static int mtk_afe_mclk_apll_connect(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_dapm_widget *w = sink;
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mtk_dai_etdm_priv *etdm_priv;
int cur_apll;
etdm_priv = get_etdm_priv_by_name(afe, w->name);
cur_apll = mt8188_get_apll_by_name(afe, source->name);
return (etdm_priv->mclk_apll == cur_apll) ? 1 : 0;
}
static int mtk_etdm_mclk_connect(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_dapm_widget *w = sink;
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8188_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_etdm_priv *etdm_priv;
int mclk_id;
mclk_id = get_etdm_id_by_name(afe, source->name);
if (mclk_id < 0) {
dev_dbg(afe->dev, "mclk_id < 0\n");
return 0;
}
etdm_priv = get_etdm_priv_by_name(afe, w->name);
if (!etdm_priv) {
dev_dbg(afe->dev, "etdm_priv == NULL\n");
return 0;
}
if (get_etdm_id_by_name(afe, sink->name) == mclk_id)
return !!(etdm_priv->mclk_freq > 0);
if (etdm_priv->cowork_source_id == mclk_id) {
etdm_priv = afe_priv->dai_priv[mclk_id];
return !!(etdm_priv->mclk_freq > 0);
}
return 0;
}
static int mtk_etdm_cowork_connect(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_dapm_widget *w = sink;
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8188_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_etdm_priv *etdm_priv;
int source_id;
int i;
source_id = get_etdm_id_by_name(afe, source->name);
if (source_id < 0) {
dev_dbg(afe->dev, "%s() source_id < 0\n", __func__);
return 0;
}
etdm_priv = get_etdm_priv_by_name(afe, w->name);
if (!etdm_priv) {
dev_dbg(afe->dev, "%s() etdm_priv == NULL\n", __func__);
return 0;
}
if (etdm_priv->cowork_source_id != COWORK_ETDM_NONE) {
if (etdm_priv->cowork_source_id == source_id)
return 1;
etdm_priv = afe_priv->dai_priv[etdm_priv->cowork_source_id];
for (i = 0; i < etdm_priv->cowork_slv_count; i++) {
if (etdm_priv->cowork_slv_id[i] == source_id)
return 1;
}
} else {
for (i = 0; i < etdm_priv->cowork_slv_count; i++) {
if (etdm_priv->cowork_slv_id[i] == source_id)
return 1;
}
}
return 0;
}
static int mtk_apll_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x\n",
__func__, w->name, event);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
if (strcmp(w->name, APLL1_W_NAME) == 0)
mt8188_apll1_enable(afe);
else
mt8188_apll2_enable(afe);
break;
case SND_SOC_DAPM_POST_PMD:
if (strcmp(w->name, APLL1_W_NAME) == 0)
mt8188_apll1_disable(afe);
else
mt8188_apll2_disable(afe);
break;
default:
break;
}
return 0;
}
static int mtk_etdm_mclk_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
int mclk_id = get_etdm_id_by_name(afe, w->name);
if (mclk_id < 0) {
dev_dbg(afe->dev, "%s() mclk_id < 0\n", __func__);
return 0;
}
dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x\n",
__func__, w->name, event);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
mtk_dai_etdm_enable_mclk(afe, mclk_id);
break;
case SND_SOC_DAPM_POST_PMD:
mtk_dai_etdm_disable_mclk(afe, mclk_id);
break;
default:
break;
}
return 0;
}
static int mtk_dptx_mclk_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x\n",
__func__, w->name, event);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
mtk_dai_etdm_enable_mclk(afe, MT8188_AFE_IO_DPTX);
break;
case SND_SOC_DAPM_POST_PMD:
mtk_dai_etdm_disable_mclk(afe, MT8188_AFE_IO_DPTX);
break;
default:
break;
}
return 0;
}
static int mtk_etdm_cg_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8188_afe_private *afe_priv = afe->platform_priv;
int etdm_id;
int cg_id;
etdm_id = get_etdm_id_by_name(afe, w->name);
if (etdm_id < 0) {
dev_dbg(afe->dev, "%s() etdm_id < 0\n", __func__);
return 0;
}
cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(etdm_id);
if (cg_id < 0) {
dev_dbg(afe->dev, "%s() cg_id < 0\n", __func__);
return 0;
}
dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x\n",
__func__, w->name, event);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
mt8188_afe_enable_clk(afe, afe_priv->clk[cg_id]);
break;
case SND_SOC_DAPM_POST_PMD:
mt8188_afe_disable_clk(afe, afe_priv->clk[cg_id]);
break;
default:
break;
}
return 0;
}
static int mtk_etdm3_cg_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8188_afe_private *afe_priv = afe->platform_priv;
dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x\n",
__func__, w->name, event);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_HDMI_OUT]);
break;
case SND_SOC_DAPM_POST_PMD:
mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_HDMI_OUT]);
break;
default:
break;
}
return 0;
}
static const struct snd_kcontrol_new mtk_dai_etdm_o048_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN48, 20, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN48, 22, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN48_1, 14, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN48_2, 6, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o049_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN49, 21, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN49, 23, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN49_1, 15, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN49_2, 7, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o050_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN50, 24, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN50_1, 16, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o051_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN51, 25, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN51_1, 17, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o052_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN52, 26, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN52_1, 18, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o053_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN53, 27, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN53_1, 19, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o054_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN54, 28, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN54_1, 20, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o055_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN55, 29, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN55_1, 21, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o056_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I030 Switch", AFE_CONN56, 30, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I054 Switch", AFE_CONN56_1, 22, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o057_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I031 Switch", AFE_CONN57, 31, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I055 Switch", AFE_CONN57_1, 23, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o058_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I032 Switch", AFE_CONN58_1, 0, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I056 Switch", AFE_CONN58_1, 24, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o059_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I033 Switch", AFE_CONN59_1, 1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I057 Switch", AFE_CONN59_1, 25, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o060_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I034 Switch", AFE_CONN60_1, 2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I058 Switch", AFE_CONN60_1, 26, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o061_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I035 Switch", AFE_CONN61_1, 3, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I059 Switch", AFE_CONN61_1, 27, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o062_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I036 Switch", AFE_CONN62_1, 4, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I060 Switch", AFE_CONN62_1, 28, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o063_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I037 Switch", AFE_CONN63_1, 5, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I061 Switch", AFE_CONN63_1, 29, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o072_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN72, 20, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN72, 22, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN72_1, 14, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN72_2, 6, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o073_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN73, 21, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN73, 23, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN73_1, 15, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN73_2, 7, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o074_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN74, 24, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN74_1, 16, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o075_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN75, 25, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN75_1, 17, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o076_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN76, 26, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN76_1, 18, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o077_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN77, 27, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN77_1, 19, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o078_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN78, 28, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN78_1, 20, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o079_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN79, 29, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN79_1, 21, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o080_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I030 Switch", AFE_CONN80, 30, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I054 Switch", AFE_CONN80_1, 22, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o081_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I031 Switch", AFE_CONN81, 31, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I055 Switch", AFE_CONN81_1, 23, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o082_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I032 Switch", AFE_CONN82_1, 0, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I056 Switch", AFE_CONN82_1, 24, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o083_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I033 Switch", AFE_CONN83_1, 1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I057 Switch", AFE_CONN83_1, 25, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o084_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I034 Switch", AFE_CONN84_1, 2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I058 Switch", AFE_CONN84_1, 26, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o085_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I035 Switch", AFE_CONN85_1, 3, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I059 Switch", AFE_CONN85_1, 27, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o086_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I036 Switch", AFE_CONN86_1, 4, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I060 Switch", AFE_CONN86_1, 28, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_etdm_o087_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I037 Switch", AFE_CONN87_1, 5, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I061 Switch", AFE_CONN87_1, 29, 1, 0),
};
static const char * const mt8188_etdm_clk_src_sel_text[] = {
"26m",
"a1sys_a2sys",
"a3sys",
"a4sys",
};
static SOC_ENUM_SINGLE_EXT_DECL(etdmout_clk_src_enum,
mt8188_etdm_clk_src_sel_text);
static const char * const hdmitx_dptx_mux_map[] = {
"Disconnect", "Connect",
};
static int hdmitx_dptx_mux_map_value[] = {
0, 1,
};
/* HDMI_OUT_MUX */
static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(hdmi_out_mux_map_enum,
SND_SOC_NOPM,
0,
1,
hdmitx_dptx_mux_map,
hdmitx_dptx_mux_map_value);
static const struct snd_kcontrol_new hdmi_out_mux_control =
SOC_DAPM_ENUM("HDMI_OUT_MUX", hdmi_out_mux_map_enum);
/* DPTX_OUT_MUX */
static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(dptx_out_mux_map_enum,
SND_SOC_NOPM,
0,
1,
hdmitx_dptx_mux_map,
hdmitx_dptx_mux_map_value);
static const struct snd_kcontrol_new dptx_out_mux_control =
SOC_DAPM_ENUM("DPTX_OUT_MUX", dptx_out_mux_map_enum);
/* HDMI_CH0_MUX ~ HDMI_CH7_MUX */
static const char *const afe_conn_hdmi_mux_map[] = {
"CH0", "CH1", "CH2", "CH3", "CH4", "CH5", "CH6", "CH7",
};
static int afe_conn_hdmi_mux_map_value[] = {
0, 1, 2, 3, 4, 5, 6, 7,
};
static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch0_mux_map_enum,
AFE_TDMOUT_CONN0,
0,
0xf,
afe_conn_hdmi_mux_map,
afe_conn_hdmi_mux_map_value);
static const struct snd_kcontrol_new hdmi_ch0_mux_control =
SOC_DAPM_ENUM("HDMI_CH0_MUX", hdmi_ch0_mux_map_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch1_mux_map_enum,
AFE_TDMOUT_CONN0,
4,
0xf,
afe_conn_hdmi_mux_map,
afe_conn_hdmi_mux_map_value);
static const struct snd_kcontrol_new hdmi_ch1_mux_control =
SOC_DAPM_ENUM("HDMI_CH1_MUX", hdmi_ch1_mux_map_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch2_mux_map_enum,
AFE_TDMOUT_CONN0,
8,
0xf,
afe_conn_hdmi_mux_map,
afe_conn_hdmi_mux_map_value);
static const struct snd_kcontrol_new hdmi_ch2_mux_control =
SOC_DAPM_ENUM("HDMI_CH2_MUX", hdmi_ch2_mux_map_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch3_mux_map_enum,
AFE_TDMOUT_CONN0,
12,
0xf,
afe_conn_hdmi_mux_map,
afe_conn_hdmi_mux_map_value);
static const struct snd_kcontrol_new hdmi_ch3_mux_control =
SOC_DAPM_ENUM("HDMI_CH3_MUX", hdmi_ch3_mux_map_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch4_mux_map_enum,
AFE_TDMOUT_CONN0,
16,
0xf,
afe_conn_hdmi_mux_map,
afe_conn_hdmi_mux_map_value);
static const struct snd_kcontrol_new hdmi_ch4_mux_control =
SOC_DAPM_ENUM("HDMI_CH4_MUX", hdmi_ch4_mux_map_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch5_mux_map_enum,
AFE_TDMOUT_CONN0,
20,
0xf,
afe_conn_hdmi_mux_map,
afe_conn_hdmi_mux_map_value);
static const struct snd_kcontrol_new hdmi_ch5_mux_control =
SOC_DAPM_ENUM("HDMI_CH5_MUX", hdmi_ch5_mux_map_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch6_mux_map_enum,
AFE_TDMOUT_CONN0,
24,
0xf,
afe_conn_hdmi_mux_map,
afe_conn_hdmi_mux_map_value);
static const struct snd_kcontrol_new hdmi_ch6_mux_control =
SOC_DAPM_ENUM("HDMI_CH6_MUX", hdmi_ch6_mux_map_enum);
static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch7_mux_map_enum,
AFE_TDMOUT_CONN0,
28,
0xf,
afe_conn_hdmi_mux_map,
afe_conn_hdmi_mux_map_value);
static const struct snd_kcontrol_new hdmi_ch7_mux_control =
SOC_DAPM_ENUM("HDMI_CH7_MUX", hdmi_ch7_mux_map_enum);
static int mt8188_etdm_clk_src_sel_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
unsigned int source = ucontrol->value.enumerated.item[0];
unsigned int val;
unsigned int old_val;
unsigned int mask;
unsigned int reg;
if (source >= e->items)
return -EINVAL;
if (!strcmp(kcontrol->id.name, "ETDM_OUT1_Clock_Source")) {
reg = ETDM_OUT1_CON4;
mask = ETDM_OUT_CON4_CLOCK_MASK;
val = FIELD_PREP(ETDM_OUT_CON4_CLOCK_MASK, source);
} else if (!strcmp(kcontrol->id.name, "ETDM_OUT2_Clock_Source")) {
reg = ETDM_OUT2_CON4;
mask = ETDM_OUT_CON4_CLOCK_MASK;
val = FIELD_PREP(ETDM_OUT_CON4_CLOCK_MASK, source);
} else if (!strcmp(kcontrol->id.name, "ETDM_OUT3_Clock_Source")) {
reg = ETDM_OUT3_CON4;
mask = ETDM_OUT_CON4_CLOCK_MASK;
val = FIELD_PREP(ETDM_OUT_CON4_CLOCK_MASK, source);
} else if (!strcmp(kcontrol->id.name, "ETDM_IN1_Clock_Source")) {
reg = ETDM_IN1_CON2;
mask = ETDM_IN_CON2_CLOCK_MASK;
val = FIELD_PREP(ETDM_IN_CON2_CLOCK_MASK, source);
} else if (!strcmp(kcontrol->id.name, "ETDM_IN2_Clock_Source")) {
reg = ETDM_IN2_CON2;
mask = ETDM_IN_CON2_CLOCK_MASK;
val = FIELD_PREP(ETDM_IN_CON2_CLOCK_MASK, source);
} else {
return -EINVAL;
}
regmap_read(afe->regmap, reg, &old_val);
old_val &= mask;
if (old_val == val)
return 0;
regmap_update_bits(afe->regmap, reg, mask, val);
return 1;
}
static int mt8188_etdm_clk_src_sel_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component =
snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
unsigned int value;
unsigned int reg;
unsigned int mask;
unsigned int shift;
if (!strcmp(kcontrol->id.name, "ETDM_OUT1_Clock_Source")) {
reg = ETDM_OUT1_CON4;
mask = ETDM_OUT_CON4_CLOCK_MASK;
shift = ETDM_OUT_CON4_CLOCK_SHIFT;
} else if (!strcmp(kcontrol->id.name, "ETDM_OUT2_Clock_Source")) {
reg = ETDM_OUT2_CON4;
mask = ETDM_OUT_CON4_CLOCK_MASK;
shift = ETDM_OUT_CON4_CLOCK_SHIFT;
} else if (!strcmp(kcontrol->id.name, "ETDM_OUT3_Clock_Source")) {
reg = ETDM_OUT3_CON4;
mask = ETDM_OUT_CON4_CLOCK_MASK;
shift = ETDM_OUT_CON4_CLOCK_SHIFT;
} else if (!strcmp(kcontrol->id.name, "ETDM_IN1_Clock_Source")) {
reg = ETDM_IN1_CON2;
mask = ETDM_IN_CON2_CLOCK_MASK;
shift = ETDM_IN_CON2_CLOCK_SHIFT;
} else if (!strcmp(kcontrol->id.name, "ETDM_IN2_Clock_Source")) {
reg = ETDM_IN2_CON2;
mask = ETDM_IN_CON2_CLOCK_MASK;
shift = ETDM_IN_CON2_CLOCK_SHIFT;
} else {
return -EINVAL;
}
regmap_read(afe->regmap, reg, &value);
value &= mask;
value >>= shift;
ucontrol->value.enumerated.item[0] = value;
return 0;
}
static const struct snd_kcontrol_new mtk_dai_etdm_controls[] = {
SOC_ENUM_EXT("ETDM_OUT1_Clock_Source", etdmout_clk_src_enum,
mt8188_etdm_clk_src_sel_get,
mt8188_etdm_clk_src_sel_put),
SOC_ENUM_EXT("ETDM_OUT2_Clock_Source", etdmout_clk_src_enum,
mt8188_etdm_clk_src_sel_get,
mt8188_etdm_clk_src_sel_put),
SOC_ENUM_EXT("ETDM_OUT3_Clock_Source", etdmout_clk_src_enum,
mt8188_etdm_clk_src_sel_get,
mt8188_etdm_clk_src_sel_put),
SOC_ENUM_EXT("ETDM_IN1_Clock_Source", etdmout_clk_src_enum,
mt8188_etdm_clk_src_sel_get,
mt8188_etdm_clk_src_sel_put),
SOC_ENUM_EXT("ETDM_IN2_Clock_Source", etdmout_clk_src_enum,
mt8188_etdm_clk_src_sel_get,
mt8188_etdm_clk_src_sel_put),
};
static const struct snd_soc_dapm_widget mtk_dai_etdm_widgets[] = {
/* eTDM_IN2 */
SND_SOC_DAPM_MIXER("I012", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I013", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I014", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I015", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I016", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I017", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I018", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I019", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I188", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I189", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I190", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I191", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I192", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I193", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I194", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I195", SND_SOC_NOPM, 0, 0, NULL, 0),
/* eTDM_IN1 */
SND_SOC_DAPM_MIXER("I072", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I073", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I074", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I075", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I076", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I077", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I078", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I079", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I080", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I081", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I082", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I083", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I084", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I085", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I086", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I087", SND_SOC_NOPM, 0, 0, NULL, 0),
/* eTDM_OUT2 */
SND_SOC_DAPM_MIXER("O048", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o048_mix, ARRAY_SIZE(mtk_dai_etdm_o048_mix)),
SND_SOC_DAPM_MIXER("O049", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o049_mix, ARRAY_SIZE(mtk_dai_etdm_o049_mix)),
SND_SOC_DAPM_MIXER("O050", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o050_mix, ARRAY_SIZE(mtk_dai_etdm_o050_mix)),
SND_SOC_DAPM_MIXER("O051", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o051_mix, ARRAY_SIZE(mtk_dai_etdm_o051_mix)),
SND_SOC_DAPM_MIXER("O052", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o052_mix, ARRAY_SIZE(mtk_dai_etdm_o052_mix)),
SND_SOC_DAPM_MIXER("O053", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o053_mix, ARRAY_SIZE(mtk_dai_etdm_o053_mix)),
SND_SOC_DAPM_MIXER("O054", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o054_mix, ARRAY_SIZE(mtk_dai_etdm_o054_mix)),
SND_SOC_DAPM_MIXER("O055", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o055_mix, ARRAY_SIZE(mtk_dai_etdm_o055_mix)),
SND_SOC_DAPM_MIXER("O056", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o056_mix, ARRAY_SIZE(mtk_dai_etdm_o056_mix)),
SND_SOC_DAPM_MIXER("O057", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o057_mix, ARRAY_SIZE(mtk_dai_etdm_o057_mix)),
SND_SOC_DAPM_MIXER("O058", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o058_mix, ARRAY_SIZE(mtk_dai_etdm_o058_mix)),
SND_SOC_DAPM_MIXER("O059", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o059_mix, ARRAY_SIZE(mtk_dai_etdm_o059_mix)),
SND_SOC_DAPM_MIXER("O060", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o060_mix, ARRAY_SIZE(mtk_dai_etdm_o060_mix)),
SND_SOC_DAPM_MIXER("O061", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o061_mix, ARRAY_SIZE(mtk_dai_etdm_o061_mix)),
SND_SOC_DAPM_MIXER("O062", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o062_mix, ARRAY_SIZE(mtk_dai_etdm_o062_mix)),
SND_SOC_DAPM_MIXER("O063", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o063_mix, ARRAY_SIZE(mtk_dai_etdm_o063_mix)),
/* eTDM_OUT1 */
SND_SOC_DAPM_MIXER("O072", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o072_mix, ARRAY_SIZE(mtk_dai_etdm_o072_mix)),
SND_SOC_DAPM_MIXER("O073", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o073_mix, ARRAY_SIZE(mtk_dai_etdm_o073_mix)),
SND_SOC_DAPM_MIXER("O074", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o074_mix, ARRAY_SIZE(mtk_dai_etdm_o074_mix)),
SND_SOC_DAPM_MIXER("O075", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o075_mix, ARRAY_SIZE(mtk_dai_etdm_o075_mix)),
SND_SOC_DAPM_MIXER("O076", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o076_mix, ARRAY_SIZE(mtk_dai_etdm_o076_mix)),
SND_SOC_DAPM_MIXER("O077", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o077_mix, ARRAY_SIZE(mtk_dai_etdm_o077_mix)),
SND_SOC_DAPM_MIXER("O078", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o078_mix, ARRAY_SIZE(mtk_dai_etdm_o078_mix)),
SND_SOC_DAPM_MIXER("O079", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o079_mix, ARRAY_SIZE(mtk_dai_etdm_o079_mix)),
SND_SOC_DAPM_MIXER("O080", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o080_mix, ARRAY_SIZE(mtk_dai_etdm_o080_mix)),
SND_SOC_DAPM_MIXER("O081", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o081_mix, ARRAY_SIZE(mtk_dai_etdm_o081_mix)),
SND_SOC_DAPM_MIXER("O082", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o082_mix, ARRAY_SIZE(mtk_dai_etdm_o082_mix)),
SND_SOC_DAPM_MIXER("O083", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o083_mix, ARRAY_SIZE(mtk_dai_etdm_o083_mix)),
SND_SOC_DAPM_MIXER("O084", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o084_mix, ARRAY_SIZE(mtk_dai_etdm_o084_mix)),
SND_SOC_DAPM_MIXER("O085", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o085_mix, ARRAY_SIZE(mtk_dai_etdm_o085_mix)),
SND_SOC_DAPM_MIXER("O086", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o086_mix, ARRAY_SIZE(mtk_dai_etdm_o086_mix)),
SND_SOC_DAPM_MIXER("O087", SND_SOC_NOPM, 0, 0,
mtk_dai_etdm_o087_mix, ARRAY_SIZE(mtk_dai_etdm_o087_mix)),
/* eTDM_OUT3 */
SND_SOC_DAPM_MUX("HDMI_OUT_MUX", SND_SOC_NOPM, 0, 0,
&hdmi_out_mux_control),
SND_SOC_DAPM_MUX("DPTX_OUT_MUX", SND_SOC_NOPM, 0, 0,
&dptx_out_mux_control),
SND_SOC_DAPM_MUX("HDMI_CH0_MUX", SND_SOC_NOPM, 0, 0,
&hdmi_ch0_mux_control),
SND_SOC_DAPM_MUX("HDMI_CH1_MUX", SND_SOC_NOPM, 0, 0,
&hdmi_ch1_mux_control),
SND_SOC_DAPM_MUX("HDMI_CH2_MUX", SND_SOC_NOPM, 0, 0,
&hdmi_ch2_mux_control),
SND_SOC_DAPM_MUX("HDMI_CH3_MUX", SND_SOC_NOPM, 0, 0,
&hdmi_ch3_mux_control),
SND_SOC_DAPM_MUX("HDMI_CH4_MUX", SND_SOC_NOPM, 0, 0,
&hdmi_ch4_mux_control),
SND_SOC_DAPM_MUX("HDMI_CH5_MUX", SND_SOC_NOPM, 0, 0,
&hdmi_ch5_mux_control),
SND_SOC_DAPM_MUX("HDMI_CH6_MUX", SND_SOC_NOPM, 0, 0,
&hdmi_ch6_mux_control),
SND_SOC_DAPM_MUX("HDMI_CH7_MUX", SND_SOC_NOPM, 0, 0,
&hdmi_ch7_mux_control),
/* mclk en */
SND_SOC_DAPM_SUPPLY_S("ETDM1_IN_MCLK", SUPPLY_SEQ_ETDM_MCLK,
SND_SOC_NOPM, 0, 0,
mtk_etdm_mclk_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("ETDM2_IN_MCLK", SUPPLY_SEQ_ETDM_MCLK,
SND_SOC_NOPM, 0, 0,
mtk_etdm_mclk_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("ETDM1_OUT_MCLK", SUPPLY_SEQ_ETDM_MCLK,
SND_SOC_NOPM, 0, 0,
mtk_etdm_mclk_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("ETDM2_OUT_MCLK", SUPPLY_SEQ_ETDM_MCLK,
SND_SOC_NOPM, 0, 0,
mtk_etdm_mclk_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("DPTX_MCLK", SUPPLY_SEQ_ETDM_MCLK,
SND_SOC_NOPM, 0, 0,
mtk_dptx_mclk_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
/* cg */
SND_SOC_DAPM_SUPPLY_S("ETDM1_IN_CG", SUPPLY_SEQ_ETDM_CG,
SND_SOC_NOPM, 0, 0,
mtk_etdm_cg_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("ETDM2_IN_CG", SUPPLY_SEQ_ETDM_CG,
SND_SOC_NOPM, 0, 0,
mtk_etdm_cg_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("ETDM1_OUT_CG", SUPPLY_SEQ_ETDM_CG,
SND_SOC_NOPM, 0, 0,
mtk_etdm_cg_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("ETDM2_OUT_CG", SUPPLY_SEQ_ETDM_CG,
SND_SOC_NOPM, 0, 0,
mtk_etdm_cg_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("ETDM3_OUT_CG", SUPPLY_SEQ_ETDM_CG,
SND_SOC_NOPM, 0, 0,
mtk_etdm3_cg_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
/* en */
SND_SOC_DAPM_SUPPLY_S("ETDM1_IN_EN", SUPPLY_SEQ_ETDM_EN,
ETDM_IN1_CON0, ETDM_CON0_EN_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ETDM2_IN_EN", SUPPLY_SEQ_ETDM_EN,
ETDM_IN2_CON0, ETDM_CON0_EN_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ETDM1_OUT_EN", SUPPLY_SEQ_ETDM_EN,
ETDM_OUT1_CON0, ETDM_CON0_EN_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ETDM2_OUT_EN", SUPPLY_SEQ_ETDM_EN,
ETDM_OUT2_CON0, ETDM_CON0_EN_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ETDM3_OUT_EN", SUPPLY_SEQ_ETDM_EN,
ETDM_OUT3_CON0, ETDM_CON0_EN_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DPTX_EN", SUPPLY_SEQ_DPTX_EN,
AFE_DPTX_CON, AFE_DPTX_CON_ON_SHIFT, 0, NULL, 0),
/* apll */
SND_SOC_DAPM_SUPPLY_S(APLL1_W_NAME, SUPPLY_SEQ_APLL,
SND_SOC_NOPM, 0, 0,
mtk_apll_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S(APLL2_W_NAME, SUPPLY_SEQ_APLL,
SND_SOC_NOPM, 0, 0,
mtk_apll_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_INPUT("ETDM_INPUT"),
SND_SOC_DAPM_OUTPUT("ETDM_OUTPUT"),
};
static const struct snd_soc_dapm_route mtk_dai_etdm_routes[] = {
/* mclk */
{"ETDM1_IN", NULL, "ETDM1_IN_MCLK", mtk_etdm_mclk_connect},
{"ETDM1_IN", NULL, "ETDM2_IN_MCLK", mtk_etdm_mclk_connect},
{"ETDM1_IN", NULL, "ETDM1_OUT_MCLK", mtk_etdm_mclk_connect},
{"ETDM1_IN", NULL, "ETDM2_OUT_MCLK", mtk_etdm_mclk_connect},
{"ETDM2_IN", NULL, "ETDM1_IN_MCLK", mtk_etdm_mclk_connect},
{"ETDM2_IN", NULL, "ETDM2_IN_MCLK", mtk_etdm_mclk_connect},
{"ETDM2_IN", NULL, "ETDM1_OUT_MCLK", mtk_etdm_mclk_connect},
{"ETDM2_IN", NULL, "ETDM2_OUT_MCLK", mtk_etdm_mclk_connect},
{"ETDM1_OUT", NULL, "ETDM1_IN_MCLK", mtk_etdm_mclk_connect},
{"ETDM1_OUT", NULL, "ETDM2_IN_MCLK", mtk_etdm_mclk_connect},
{"ETDM1_OUT", NULL, "ETDM1_OUT_MCLK", mtk_etdm_mclk_connect},
{"ETDM1_OUT", NULL, "ETDM2_OUT_MCLK", mtk_etdm_mclk_connect},
{"ETDM2_OUT", NULL, "ETDM1_IN_MCLK", mtk_etdm_mclk_connect},
{"ETDM2_OUT", NULL, "ETDM2_IN_MCLK", mtk_etdm_mclk_connect},
{"ETDM2_OUT", NULL, "ETDM1_OUT_MCLK", mtk_etdm_mclk_connect},
{"ETDM2_OUT", NULL, "ETDM2_OUT_MCLK", mtk_etdm_mclk_connect},
{"DPTX", NULL, "DPTX_MCLK"},
{"ETDM1_IN_MCLK", NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
{"ETDM1_IN_MCLK", NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
{"ETDM2_IN_MCLK", NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
{"ETDM2_IN_MCLK", NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
{"ETDM1_OUT_MCLK", NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
{"ETDM1_OUT_MCLK", NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
{"ETDM2_OUT_MCLK", NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
{"ETDM2_OUT_MCLK", NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
{"DPTX_MCLK", NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
{"DPTX_MCLK", NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
/* cg */
{"ETDM1_IN", NULL, "ETDM1_IN_CG"},
{"ETDM1_IN", NULL, "ETDM2_IN_CG", mtk_etdm_cowork_connect},
{"ETDM1_IN", NULL, "ETDM1_OUT_CG", mtk_etdm_cowork_connect},
{"ETDM1_IN", NULL, "ETDM2_OUT_CG", mtk_etdm_cowork_connect},
{"ETDM2_IN", NULL, "ETDM1_IN_CG", mtk_etdm_cowork_connect},
{"ETDM2_IN", NULL, "ETDM2_IN_CG"},
{"ETDM2_IN", NULL, "ETDM1_OUT_CG", mtk_etdm_cowork_connect},
{"ETDM2_IN", NULL, "ETDM2_OUT_CG", mtk_etdm_cowork_connect},
{"ETDM1_OUT", NULL, "ETDM1_IN_CG", mtk_etdm_cowork_connect},
{"ETDM1_OUT", NULL, "ETDM2_IN_CG", mtk_etdm_cowork_connect},
{"ETDM1_OUT", NULL, "ETDM1_OUT_CG"},
{"ETDM1_OUT", NULL, "ETDM2_OUT_CG", mtk_etdm_cowork_connect},
{"ETDM2_OUT", NULL, "ETDM1_IN_CG", mtk_etdm_cowork_connect},
{"ETDM2_OUT", NULL, "ETDM2_IN_CG", mtk_etdm_cowork_connect},
{"ETDM2_OUT", NULL, "ETDM1_OUT_CG", mtk_etdm_cowork_connect},
{"ETDM2_OUT", NULL, "ETDM2_OUT_CG"},
{"ETDM3_OUT", NULL, "ETDM3_OUT_CG"},
{"DPTX", NULL, "ETDM3_OUT_CG"},
/* en */
{"ETDM1_IN", NULL, "ETDM1_IN_EN"},
{"ETDM1_IN", NULL, "ETDM2_IN_EN", mtk_etdm_cowork_connect},
{"ETDM1_IN", NULL, "ETDM1_OUT_EN", mtk_etdm_cowork_connect},
{"ETDM1_IN", NULL, "ETDM2_OUT_EN", mtk_etdm_cowork_connect},
{"ETDM2_IN", NULL, "ETDM1_IN_EN", mtk_etdm_cowork_connect},
{"ETDM2_IN", NULL, "ETDM2_IN_EN"},
{"ETDM2_IN", NULL, "ETDM1_OUT_EN", mtk_etdm_cowork_connect},
{"ETDM2_IN", NULL, "ETDM2_OUT_EN", mtk_etdm_cowork_connect},
{"ETDM1_OUT", NULL, "ETDM1_IN_EN", mtk_etdm_cowork_connect},
{"ETDM1_OUT", NULL, "ETDM2_IN_EN", mtk_etdm_cowork_connect},
{"ETDM1_OUT", NULL, "ETDM1_OUT_EN"},
{"ETDM1_OUT", NULL, "ETDM2_OUT_EN", mtk_etdm_cowork_connect},
{"ETDM2_OUT", NULL, "ETDM1_IN_EN", mtk_etdm_cowork_connect},
{"ETDM2_OUT", NULL, "ETDM2_IN_EN", mtk_etdm_cowork_connect},
{"ETDM2_OUT", NULL, "ETDM1_OUT_EN", mtk_etdm_cowork_connect},
{"ETDM2_OUT", NULL, "ETDM2_OUT_EN"},
{"ETDM3_OUT", NULL, "ETDM3_OUT_EN"},
{"DPTX", NULL, "ETDM3_OUT_EN"},
{"DPTX", NULL, "DPTX_EN"},
{"ETDM1_IN_EN", NULL, APLL1_W_NAME, mtk_afe_etdm_apll_connect},
{"ETDM1_IN_EN", NULL, APLL2_W_NAME, mtk_afe_etdm_apll_connect},
{"ETDM2_IN_EN", NULL, APLL1_W_NAME, mtk_afe_etdm_apll_connect},
{"ETDM2_IN_EN", NULL, APLL2_W_NAME, mtk_afe_etdm_apll_connect},
{"ETDM1_OUT_EN", NULL, APLL1_W_NAME, mtk_afe_etdm_apll_connect},
{"ETDM1_OUT_EN", NULL, APLL2_W_NAME, mtk_afe_etdm_apll_connect},
{"ETDM2_OUT_EN", NULL, APLL1_W_NAME, mtk_afe_etdm_apll_connect},
{"ETDM2_OUT_EN", NULL, APLL2_W_NAME, mtk_afe_etdm_apll_connect},
{"ETDM3_OUT_EN", NULL, APLL1_W_NAME, mtk_afe_etdm_apll_connect},
{"ETDM3_OUT_EN", NULL, APLL2_W_NAME, mtk_afe_etdm_apll_connect},
{"I012", NULL, "ETDM2_IN"},
{"I013", NULL, "ETDM2_IN"},
{"I014", NULL, "ETDM2_IN"},
{"I015", NULL, "ETDM2_IN"},
{"I016", NULL, "ETDM2_IN"},
{"I017", NULL, "ETDM2_IN"},
{"I018", NULL, "ETDM2_IN"},
{"I019", NULL, "ETDM2_IN"},
{"I188", NULL, "ETDM2_IN"},
{"I189", NULL, "ETDM2_IN"},
{"I190", NULL, "ETDM2_IN"},
{"I191", NULL, "ETDM2_IN"},
{"I192", NULL, "ETDM2_IN"},
{"I193", NULL, "ETDM2_IN"},
{"I194", NULL, "ETDM2_IN"},
{"I195", NULL, "ETDM2_IN"},
{"I072", NULL, "ETDM1_IN"},
{"I073", NULL, "ETDM1_IN"},
{"I074", NULL, "ETDM1_IN"},
{"I075", NULL, "ETDM1_IN"},
{"I076", NULL, "ETDM1_IN"},
{"I077", NULL, "ETDM1_IN"},
{"I078", NULL, "ETDM1_IN"},
{"I079", NULL, "ETDM1_IN"},
{"I080", NULL, "ETDM1_IN"},
{"I081", NULL, "ETDM1_IN"},
{"I082", NULL, "ETDM1_IN"},
{"I083", NULL, "ETDM1_IN"},
{"I084", NULL, "ETDM1_IN"},
{"I085", NULL, "ETDM1_IN"},
{"I086", NULL, "ETDM1_IN"},
{"I087", NULL, "ETDM1_IN"},
{"UL8", NULL, "ETDM1_IN"},
{"UL3", NULL, "ETDM2_IN"},
{"ETDM2_OUT", NULL, "O048"},
{"ETDM2_OUT", NULL, "O049"},
{"ETDM2_OUT", NULL, "O050"},
{"ETDM2_OUT", NULL, "O051"},
{"ETDM2_OUT", NULL, "O052"},
{"ETDM2_OUT", NULL, "O053"},
{"ETDM2_OUT", NULL, "O054"},
{"ETDM2_OUT", NULL, "O055"},
{"ETDM2_OUT", NULL, "O056"},
{"ETDM2_OUT", NULL, "O057"},
{"ETDM2_OUT", NULL, "O058"},
{"ETDM2_OUT", NULL, "O059"},
{"ETDM2_OUT", NULL, "O060"},
{"ETDM2_OUT", NULL, "O061"},
{"ETDM2_OUT", NULL, "O062"},
{"ETDM2_OUT", NULL, "O063"},
{"ETDM1_OUT", NULL, "O072"},
{"ETDM1_OUT", NULL, "O073"},
{"ETDM1_OUT", NULL, "O074"},
{"ETDM1_OUT", NULL, "O075"},
{"ETDM1_OUT", NULL, "O076"},
{"ETDM1_OUT", NULL, "O077"},
{"ETDM1_OUT", NULL, "O078"},
{"ETDM1_OUT", NULL, "O079"},
{"ETDM1_OUT", NULL, "O080"},
{"ETDM1_OUT", NULL, "O081"},
{"ETDM1_OUT", NULL, "O082"},
{"ETDM1_OUT", NULL, "O083"},
{"ETDM1_OUT", NULL, "O084"},
{"ETDM1_OUT", NULL, "O085"},
{"ETDM1_OUT", NULL, "O086"},
{"ETDM1_OUT", NULL, "O087"},
{"O048", "I020 Switch", "I020"},
{"O049", "I021 Switch", "I021"},
{"O048", "I022 Switch", "I022"},
{"O049", "I023 Switch", "I023"},
{"O050", "I024 Switch", "I024"},
{"O051", "I025 Switch", "I025"},
{"O052", "I026 Switch", "I026"},
{"O053", "I027 Switch", "I027"},
{"O054", "I028 Switch", "I028"},
{"O055", "I029 Switch", "I029"},
{"O056", "I030 Switch", "I030"},
{"O057", "I031 Switch", "I031"},
{"O058", "I032 Switch", "I032"},
{"O059", "I033 Switch", "I033"},
{"O060", "I034 Switch", "I034"},
{"O061", "I035 Switch", "I035"},
{"O062", "I036 Switch", "I036"},
{"O063", "I037 Switch", "I037"},
{"O048", "I046 Switch", "I046"},
{"O049", "I047 Switch", "I047"},
{"O050", "I048 Switch", "I048"},
{"O051", "I049 Switch", "I049"},
{"O052", "I050 Switch", "I050"},
{"O053", "I051 Switch", "I051"},
{"O054", "I052 Switch", "I052"},
{"O055", "I053 Switch", "I053"},
{"O056", "I054 Switch", "I054"},
{"O057", "I055 Switch", "I055"},
{"O058", "I056 Switch", "I056"},
{"O059", "I057 Switch", "I057"},
{"O060", "I058 Switch", "I058"},
{"O061", "I059 Switch", "I059"},
{"O062", "I060 Switch", "I060"},
{"O063", "I061 Switch", "I061"},
{"O048", "I070 Switch", "I070"},
{"O049", "I071 Switch", "I071"},
{"O072", "I020 Switch", "I020"},
{"O073", "I021 Switch", "I021"},
{"O072", "I022 Switch", "I022"},
{"O073", "I023 Switch", "I023"},
{"O074", "I024 Switch", "I024"},
{"O075", "I025 Switch", "I025"},
{"O076", "I026 Switch", "I026"},
{"O077", "I027 Switch", "I027"},
{"O078", "I028 Switch", "I028"},
{"O079", "I029 Switch", "I029"},
{"O080", "I030 Switch", "I030"},
{"O081", "I031 Switch", "I031"},
{"O082", "I032 Switch", "I032"},
{"O083", "I033 Switch", "I033"},
{"O084", "I034 Switch", "I034"},
{"O085", "I035 Switch", "I035"},
{"O086", "I036 Switch", "I036"},
{"O087", "I037 Switch", "I037"},
{"O072", "I046 Switch", "I046"},
{"O073", "I047 Switch", "I047"},
{"O074", "I048 Switch", "I048"},
{"O075", "I049 Switch", "I049"},
{"O076", "I050 Switch", "I050"},
{"O077", "I051 Switch", "I051"},
{"O078", "I052 Switch", "I052"},
{"O079", "I053 Switch", "I053"},
{"O080", "I054 Switch", "I054"},
{"O081", "I055 Switch", "I055"},
{"O082", "I056 Switch", "I056"},
{"O083", "I057 Switch", "I057"},
{"O084", "I058 Switch", "I058"},
{"O085", "I059 Switch", "I059"},
{"O086", "I060 Switch", "I060"},
{"O087", "I061 Switch", "I061"},
{"O072", "I070 Switch", "I070"},
{"O073", "I071 Switch", "I071"},
{"HDMI_CH0_MUX", "CH0", "DL10"},
{"HDMI_CH0_MUX", "CH1", "DL10"},
{"HDMI_CH0_MUX", "CH2", "DL10"},
{"HDMI_CH0_MUX", "CH3", "DL10"},
{"HDMI_CH0_MUX", "CH4", "DL10"},
{"HDMI_CH0_MUX", "CH5", "DL10"},
{"HDMI_CH0_MUX", "CH6", "DL10"},
{"HDMI_CH0_MUX", "CH7", "DL10"},
{"HDMI_CH1_MUX", "CH0", "DL10"},
{"HDMI_CH1_MUX", "CH1", "DL10"},
{"HDMI_CH1_MUX", "CH2", "DL10"},
{"HDMI_CH1_MUX", "CH3", "DL10"},
{"HDMI_CH1_MUX", "CH4", "DL10"},
{"HDMI_CH1_MUX", "CH5", "DL10"},
{"HDMI_CH1_MUX", "CH6", "DL10"},
{"HDMI_CH1_MUX", "CH7", "DL10"},
{"HDMI_CH2_MUX", "CH0", "DL10"},
{"HDMI_CH2_MUX", "CH1", "DL10"},
{"HDMI_CH2_MUX", "CH2", "DL10"},
{"HDMI_CH2_MUX", "CH3", "DL10"},
{"HDMI_CH2_MUX", "CH4", "DL10"},
{"HDMI_CH2_MUX", "CH5", "DL10"},
{"HDMI_CH2_MUX", "CH6", "DL10"},
{"HDMI_CH2_MUX", "CH7", "DL10"},
{"HDMI_CH3_MUX", "CH0", "DL10"},
{"HDMI_CH3_MUX", "CH1", "DL10"},
{"HDMI_CH3_MUX", "CH2", "DL10"},
{"HDMI_CH3_MUX", "CH3", "DL10"},
{"HDMI_CH3_MUX", "CH4", "DL10"},
{"HDMI_CH3_MUX", "CH5", "DL10"},
{"HDMI_CH3_MUX", "CH6", "DL10"},
{"HDMI_CH3_MUX", "CH7", "DL10"},
{"HDMI_CH4_MUX", "CH0", "DL10"},
{"HDMI_CH4_MUX", "CH1", "DL10"},
{"HDMI_CH4_MUX", "CH2", "DL10"},
{"HDMI_CH4_MUX", "CH3", "DL10"},
{"HDMI_CH4_MUX", "CH4", "DL10"},
{"HDMI_CH4_MUX", "CH5", "DL10"},
{"HDMI_CH4_MUX", "CH6", "DL10"},
{"HDMI_CH4_MUX", "CH7", "DL10"},
{"HDMI_CH5_MUX", "CH0", "DL10"},
{"HDMI_CH5_MUX", "CH1", "DL10"},
{"HDMI_CH5_MUX", "CH2", "DL10"},
{"HDMI_CH5_MUX", "CH3", "DL10"},
{"HDMI_CH5_MUX", "CH4", "DL10"},
{"HDMI_CH5_MUX", "CH5", "DL10"},
{"HDMI_CH5_MUX", "CH6", "DL10"},
{"HDMI_CH5_MUX", "CH7", "DL10"},
{"HDMI_CH6_MUX", "CH0", "DL10"},
{"HDMI_CH6_MUX", "CH1", "DL10"},
{"HDMI_CH6_MUX", "CH2", "DL10"},
{"HDMI_CH6_MUX", "CH3", "DL10"},
{"HDMI_CH6_MUX", "CH4", "DL10"},
{"HDMI_CH6_MUX", "CH5", "DL10"},
{"HDMI_CH6_MUX", "CH6", "DL10"},
{"HDMI_CH6_MUX", "CH7", "DL10"},
{"HDMI_CH7_MUX", "CH0", "DL10"},
{"HDMI_CH7_MUX", "CH1", "DL10"},
{"HDMI_CH7_MUX", "CH2", "DL10"},
{"HDMI_CH7_MUX", "CH3", "DL10"},
{"HDMI_CH7_MUX", "CH4", "DL10"},
{"HDMI_CH7_MUX", "CH5", "DL10"},
{"HDMI_CH7_MUX", "CH6", "DL10"},
{"HDMI_CH7_MUX", "CH7", "DL10"},
{"HDMI_OUT_MUX", "Connect", "HDMI_CH0_MUX"},
{"HDMI_OUT_MUX", "Connect", "HDMI_CH1_MUX"},
{"HDMI_OUT_MUX", "Connect", "HDMI_CH2_MUX"},
{"HDMI_OUT_MUX", "Connect", "HDMI_CH3_MUX"},
{"HDMI_OUT_MUX", "Connect", "HDMI_CH4_MUX"},
{"HDMI_OUT_MUX", "Connect", "HDMI_CH5_MUX"},
{"HDMI_OUT_MUX", "Connect", "HDMI_CH6_MUX"},
{"HDMI_OUT_MUX", "Connect", "HDMI_CH7_MUX"},
{"DPTX_OUT_MUX", "Connect", "HDMI_CH0_MUX"},
{"DPTX_OUT_MUX", "Connect", "HDMI_CH1_MUX"},
{"DPTX_OUT_MUX", "Connect", "HDMI_CH2_MUX"},
{"DPTX_OUT_MUX", "Connect", "HDMI_CH3_MUX"},
{"DPTX_OUT_MUX", "Connect", "HDMI_CH4_MUX"},
{"DPTX_OUT_MUX", "Connect", "HDMI_CH5_MUX"},
{"DPTX_OUT_MUX", "Connect", "HDMI_CH6_MUX"},
{"DPTX_OUT_MUX", "Connect", "HDMI_CH7_MUX"},
{"ETDM3_OUT", NULL, "HDMI_OUT_MUX"},
{"DPTX", NULL, "DPTX_OUT_MUX"},
{"ETDM_OUTPUT", NULL, "DPTX"},
{"ETDM_OUTPUT", NULL, "ETDM1_OUT"},
{"ETDM_OUTPUT", NULL, "ETDM2_OUT"},
{"ETDM_OUTPUT", NULL, "ETDM3_OUT"},
{"ETDM1_IN", NULL, "ETDM_INPUT"},
{"ETDM2_IN", NULL, "ETDM_INPUT"},
};
static int etdm_cowork_slv_sel(int id, int slave_mode)
{
if (slave_mode) {
switch (id) {
case MT8188_AFE_IO_ETDM1_IN:
return COWORK_ETDM_IN1_S;
case MT8188_AFE_IO_ETDM2_IN:
return COWORK_ETDM_IN2_S;
case MT8188_AFE_IO_ETDM1_OUT:
return COWORK_ETDM_OUT1_S;
case MT8188_AFE_IO_ETDM2_OUT:
return COWORK_ETDM_OUT2_S;
case MT8188_AFE_IO_ETDM3_OUT:
return COWORK_ETDM_OUT3_S;
default:
return -EINVAL;
}
} else {
switch (id) {
case MT8188_AFE_IO_ETDM1_IN:
return COWORK_ETDM_IN1_M;
case MT8188_AFE_IO_ETDM2_IN:
return COWORK_ETDM_IN2_M;
case MT8188_AFE_IO_ETDM1_OUT:
return COWORK_ETDM_OUT1_M;
case MT8188_AFE_IO_ETDM2_OUT:
return COWORK_ETDM_OUT2_M;
case MT8188_AFE_IO_ETDM3_OUT:
return COWORK_ETDM_OUT3_M;
default:
return -EINVAL;
}
}
}
static int etdm_cowork_sync_sel(int id)
{
switch (id) {
case MT8188_AFE_IO_ETDM1_IN:
return ETDM_SYNC_FROM_IN1;
case MT8188_AFE_IO_ETDM2_IN:
return ETDM_SYNC_FROM_IN2;
case MT8188_AFE_IO_ETDM1_OUT:
return ETDM_SYNC_FROM_OUT1;
case MT8188_AFE_IO_ETDM2_OUT:
return ETDM_SYNC_FROM_OUT2;
case MT8188_AFE_IO_ETDM3_OUT:
return ETDM_SYNC_FROM_OUT3;
default:
return -EINVAL;
}
}
static int mt8188_etdm_sync_mode_slv(struct mtk_base_afe *afe, int dai_id)
{
struct mt8188_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_etdm_priv *etdm_data;
unsigned int reg = 0;
unsigned int mask;
unsigned int val;
int cowork_source_sel;
if (!is_valid_etdm_dai(dai_id))
return -EINVAL;
etdm_data = afe_priv->dai_priv[dai_id];
cowork_source_sel = etdm_cowork_slv_sel(etdm_data->cowork_source_id,
true);
if (cowork_source_sel < 0)
return cowork_source_sel;
switch (dai_id) {
case MT8188_AFE_IO_ETDM1_IN:
reg = ETDM_COWORK_CON1;
mask = ETDM_IN1_SLAVE_SEL_MASK;
val = FIELD_PREP(ETDM_IN1_SLAVE_SEL_MASK, cowork_source_sel);
break;
case MT8188_AFE_IO_ETDM2_IN:
reg = ETDM_COWORK_CON2;
mask = ETDM_IN2_SLAVE_SEL_MASK;
val = FIELD_PREP(ETDM_IN2_SLAVE_SEL_MASK, cowork_source_sel);
break;
case MT8188_AFE_IO_ETDM1_OUT:
reg = ETDM_COWORK_CON0;
mask = ETDM_OUT1_SLAVE_SEL_MASK;
val = FIELD_PREP(ETDM_OUT1_SLAVE_SEL_MASK, cowork_source_sel);
break;
case MT8188_AFE_IO_ETDM2_OUT:
reg = ETDM_COWORK_CON2;
mask = ETDM_OUT2_SLAVE_SEL_MASK;
val = FIELD_PREP(ETDM_OUT2_SLAVE_SEL_MASK, cowork_source_sel);
break;
case MT8188_AFE_IO_ETDM3_OUT:
reg = ETDM_COWORK_CON2;
mask = ETDM_OUT3_SLAVE_SEL_MASK;
val = FIELD_PREP(ETDM_OUT3_SLAVE_SEL_MASK, cowork_source_sel);
break;
default:
return 0;
}
regmap_update_bits(afe->regmap, reg, mask, val);
return 0;
}
static int mt8188_etdm_sync_mode_mst(struct mtk_base_afe *afe, int dai_id)
{
struct mt8188_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_etdm_priv *etdm_data;
struct etdm_con_reg etdm_reg;
unsigned int reg = 0;
unsigned int mask;
unsigned int val;
int cowork_source_sel;
int ret;
if (!is_valid_etdm_dai(dai_id))
return -EINVAL;
etdm_data = afe_priv->dai_priv[dai_id];
cowork_source_sel = etdm_cowork_sync_sel(etdm_data->cowork_source_id);
if (cowork_source_sel < 0)
return cowork_source_sel;
switch (dai_id) {
case MT8188_AFE_IO_ETDM1_IN:
reg = ETDM_COWORK_CON1;
mask = ETDM_IN1_SYNC_SEL_MASK;
val = FIELD_PREP(ETDM_IN1_SYNC_SEL_MASK, cowork_source_sel);
break;
case MT8188_AFE_IO_ETDM2_IN:
reg = ETDM_COWORK_CON2;
mask = ETDM_IN2_SYNC_SEL_MASK;
val = FIELD_PREP(ETDM_IN2_SYNC_SEL_MASK, cowork_source_sel);
break;
case MT8188_AFE_IO_ETDM1_OUT:
reg = ETDM_COWORK_CON0;
mask = ETDM_OUT1_SYNC_SEL_MASK;
val = FIELD_PREP(ETDM_OUT1_SYNC_SEL_MASK, cowork_source_sel);
break;
case MT8188_AFE_IO_ETDM2_OUT:
reg = ETDM_COWORK_CON2;
mask = ETDM_OUT2_SYNC_SEL_MASK;
val = FIELD_PREP(ETDM_OUT2_SYNC_SEL_MASK, cowork_source_sel);
break;
case MT8188_AFE_IO_ETDM3_OUT:
reg = ETDM_COWORK_CON2;
mask = ETDM_OUT3_SYNC_SEL_MASK;
val = FIELD_PREP(ETDM_OUT3_SYNC_SEL_MASK, cowork_source_sel);
break;
default:
return 0;
}
ret = get_etdm_reg(dai_id, &etdm_reg);
if (ret < 0)
return ret;
regmap_update_bits(afe->regmap, reg, mask, val);
regmap_set_bits(afe->regmap, etdm_reg.con0, ETDM_CON0_SYNC_MODE);
return 0;
}
static int mt8188_etdm_sync_mode_configure(struct mtk_base_afe *afe, int dai_id)
{
struct mt8188_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_etdm_priv *etdm_data;
if (!is_valid_etdm_dai(dai_id))
return -EINVAL;
etdm_data = afe_priv->dai_priv[dai_id];
if (etdm_data->cowork_source_id == COWORK_ETDM_NONE)
return 0;
if (etdm_data->slave_mode)
mt8188_etdm_sync_mode_slv(afe, dai_id);
else
mt8188_etdm_sync_mode_mst(afe, dai_id);
return 0;
}
/* dai ops */
static int mtk_dai_etdm_fifo_mode(struct mtk_base_afe *afe,
int dai_id, unsigned int rate)
{
unsigned int mode = 0;
unsigned int reg = 0;
unsigned int val = 0;
unsigned int mask = (ETDM_IN_AFIFO_MODE_MASK | ETDM_IN_USE_AFIFO);
if (rate != 0)
mode = mt8188_afe_fs_timing(rate);
switch (dai_id) {
case MT8188_AFE_IO_ETDM1_IN:
reg = ETDM_IN1_AFIFO_CON;
if (rate == 0)
mode = MT8188_ETDM_IN1_1X_EN;
break;
case MT8188_AFE_IO_ETDM2_IN:
reg = ETDM_IN2_AFIFO_CON;
if (rate == 0)
mode = MT8188_ETDM_IN2_1X_EN;
break;
default:
return -EINVAL;
}
val = (mode | ETDM_IN_USE_AFIFO);
regmap_update_bits(afe->regmap, reg, mask, val);
return 0;
}
static int mtk_dai_etdm_in_configure(struct mtk_base_afe *afe,
unsigned int rate,
unsigned int channels,
int dai_id)
{
struct mt8188_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_etdm_priv *etdm_data;
struct etdm_con_reg etdm_reg;
bool slave_mode;
unsigned int data_mode;
unsigned int lrck_width;
unsigned int val = 0;
unsigned int mask = 0;
int ret;
int i;
if (!is_valid_etdm_dai(dai_id))
return -EINVAL;
etdm_data = afe_priv->dai_priv[dai_id];
slave_mode = etdm_data->slave_mode;
data_mode = etdm_data->data_mode;
lrck_width = etdm_data->lrck_width;
dev_dbg(afe->dev, "%s rate %u channels %u, id %d\n",
__func__, rate, channels, dai_id);
ret = get_etdm_reg(dai_id, &etdm_reg);
if (ret < 0)
return ret;
/* afifo */
if (slave_mode)
mtk_dai_etdm_fifo_mode(afe, dai_id, 0);
else
mtk_dai_etdm_fifo_mode(afe, dai_id, rate);
/* con1 */
if (lrck_width > 0) {
mask |= (ETDM_IN_CON1_LRCK_AUTO_MODE |
ETDM_IN_CON1_LRCK_WIDTH_MASK);
val |= FIELD_PREP(ETDM_IN_CON1_LRCK_WIDTH_MASK, lrck_width - 1);
}
regmap_update_bits(afe->regmap, etdm_reg.con1, mask, val);
mask = 0;
val = 0;
/* con2 */
if (!slave_mode) {
mask |= ETDM_IN_CON2_UPDATE_GAP_MASK;
if (rate == 352800 || rate == 384000)
val |= FIELD_PREP(ETDM_IN_CON2_UPDATE_GAP_MASK, 4);
else
val |= FIELD_PREP(ETDM_IN_CON2_UPDATE_GAP_MASK, 3);
}
mask |= (ETDM_IN_CON2_MULTI_IP_2CH_MODE |
ETDM_IN_CON2_MULTI_IP_TOTAL_CH_MASK);
if (data_mode == MTK_DAI_ETDM_DATA_MULTI_PIN) {
val |= ETDM_IN_CON2_MULTI_IP_2CH_MODE |
FIELD_PREP(ETDM_IN_CON2_MULTI_IP_TOTAL_CH_MASK, channels - 1);
}
regmap_update_bits(afe->regmap, etdm_reg.con2, mask, val);
mask = 0;
val = 0;
/* con3 */
mask |= ETDM_IN_CON3_DISABLE_OUT_MASK;
for (i = 0; i < channels; i += 2) {
if (etdm_data->in_disable_ch[i] &&
etdm_data->in_disable_ch[i + 1])
val |= ETDM_IN_CON3_DISABLE_OUT(i >> 1);
}
if (!slave_mode) {
mask |= ETDM_IN_CON3_FS_MASK;
val |= FIELD_PREP(ETDM_IN_CON3_FS_MASK, get_etdm_fs_timing(rate));
}
regmap_update_bits(afe->regmap, etdm_reg.con3, mask, val);
mask = 0;
val = 0;
/* con4 */
mask |= (ETDM_IN_CON4_MASTER_LRCK_INV | ETDM_IN_CON4_MASTER_BCK_INV |
ETDM_IN_CON4_SLAVE_LRCK_INV | ETDM_IN_CON4_SLAVE_BCK_INV);
if (slave_mode) {
if (etdm_data->lrck_inv)
val |= ETDM_IN_CON4_SLAVE_LRCK_INV;
if (etdm_data->bck_inv)
val |= ETDM_IN_CON4_SLAVE_BCK_INV;
} else {
if (etdm_data->lrck_inv)
val |= ETDM_IN_CON4_MASTER_LRCK_INV;
if (etdm_data->bck_inv)
val |= ETDM_IN_CON4_MASTER_BCK_INV;
}
regmap_update_bits(afe->regmap, etdm_reg.con4, mask, val);
mask = 0;
val = 0;
/* con5 */
mask |= ETDM_IN_CON5_LR_SWAP_MASK;
mask |= ETDM_IN_CON5_ENABLE_ODD_MASK;
for (i = 0; i < channels; i += 2) {
if (etdm_data->in_disable_ch[i] &&
!etdm_data->in_disable_ch[i + 1]) {
val |= ETDM_IN_CON5_LR_SWAP(i >> 1);
val |= ETDM_IN_CON5_ENABLE_ODD(i >> 1);
} else if (!etdm_data->in_disable_ch[i] &&
etdm_data->in_disable_ch[i + 1]) {
val |= ETDM_IN_CON5_ENABLE_ODD(i >> 1);
}
}
regmap_update_bits(afe->regmap, etdm_reg.con5, mask, val);
return 0;
}
static int mtk_dai_etdm_out_configure(struct mtk_base_afe *afe,
unsigned int rate,
unsigned int channels,
int dai_id)
{
struct mt8188_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_etdm_priv *etdm_data;
struct etdm_con_reg etdm_reg;
bool slave_mode;
unsigned int lrck_width;
unsigned int val = 0;
unsigned int mask = 0;
int fs = 0;
int ret;
if (!is_valid_etdm_dai(dai_id))
return -EINVAL;
etdm_data = afe_priv->dai_priv[dai_id];
slave_mode = etdm_data->slave_mode;
lrck_width = etdm_data->lrck_width;
dev_dbg(afe->dev, "%s rate %u channels %u, id %d\n",
__func__, rate, channels, dai_id);
ret = get_etdm_reg(dai_id, &etdm_reg);
if (ret < 0)
return ret;
/* con0 */
mask = ETDM_OUT_CON0_RELATCH_DOMAIN_MASK;
val = FIELD_PREP(ETDM_OUT_CON0_RELATCH_DOMAIN_MASK,
ETDM_RELATCH_TIMING_A1A2SYS);
regmap_update_bits(afe->regmap, etdm_reg.con0, mask, val);
mask = 0;
val = 0;
/* con1 */
if (lrck_width > 0) {
mask |= (ETDM_OUT_CON1_LRCK_AUTO_MODE |
ETDM_OUT_CON1_LRCK_WIDTH_MASK);
val |= FIELD_PREP(ETDM_OUT_CON1_LRCK_WIDTH_MASK, lrck_width - 1);
}
regmap_update_bits(afe->regmap, etdm_reg.con1, mask, val);
mask = 0;
val = 0;
if (!slave_mode) {
/* con4 */
mask |= ETDM_OUT_CON4_FS_MASK;
val |= FIELD_PREP(ETDM_OUT_CON4_FS_MASK, get_etdm_fs_timing(rate));
}
mask |= ETDM_OUT_CON4_RELATCH_EN_MASK;
if (dai_id == MT8188_AFE_IO_ETDM1_OUT)
fs = MT8188_ETDM_OUT1_1X_EN;
else if (dai_id == MT8188_AFE_IO_ETDM2_OUT)
fs = MT8188_ETDM_OUT2_1X_EN;
val |= FIELD_PREP(ETDM_OUT_CON4_RELATCH_EN_MASK, fs);
regmap_update_bits(afe->regmap, etdm_reg.con4, mask, val);
mask = 0;
val = 0;
/* con5 */
mask |= (ETDM_OUT_CON5_MASTER_LRCK_INV | ETDM_OUT_CON5_MASTER_BCK_INV |
ETDM_OUT_CON5_SLAVE_LRCK_INV | ETDM_OUT_CON5_SLAVE_BCK_INV);
if (slave_mode) {
if (etdm_data->lrck_inv)
val |= ETDM_OUT_CON5_SLAVE_LRCK_INV;
if (etdm_data->bck_inv)
val |= ETDM_OUT_CON5_SLAVE_BCK_INV;
} else {
if (etdm_data->lrck_inv)
val |= ETDM_OUT_CON5_MASTER_LRCK_INV;
if (etdm_data->bck_inv)
val |= ETDM_OUT_CON5_MASTER_BCK_INV;
}
regmap_update_bits(afe->regmap, etdm_reg.con5, mask, val);
return 0;
}
static int mtk_dai_etdm_configure(struct mtk_base_afe *afe,
unsigned int rate,
unsigned int channels,
unsigned int bit_width,
int dai_id)
{
struct mt8188_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_etdm_priv *etdm_data;
struct etdm_con_reg etdm_reg;
bool slave_mode;
unsigned int etdm_channels;
unsigned int val = 0;
unsigned int mask = 0;
unsigned int bck;
unsigned int wlen = get_etdm_wlen(bit_width);
int ret;
if (!is_valid_etdm_dai(dai_id))
return -EINVAL;
etdm_data = afe_priv->dai_priv[dai_id];
slave_mode = etdm_data->slave_mode;
etdm_data->rate = rate;
ret = get_etdm_reg(dai_id, &etdm_reg);
if (ret < 0)
return ret;
dev_dbg(afe->dev, "%s fmt %u data %u lrck %d-%u bck %d, slv %u\n",
__func__, etdm_data->format, etdm_data->data_mode,
etdm_data->lrck_inv, etdm_data->lrck_width, etdm_data->bck_inv,
etdm_data->slave_mode);
dev_dbg(afe->dev, "%s rate %u channels %u bitwidth %u, id %d\n",
__func__, rate, channels, bit_width, dai_id);
etdm_channels = (etdm_data->data_mode == MTK_DAI_ETDM_DATA_ONE_PIN) ?
get_etdm_ch_fixup(channels) : 2;
bck = rate * etdm_channels * wlen;
if (bck > MT8188_ETDM_NORMAL_MAX_BCK_RATE) {
dev_err(afe->dev, "%s bck rate %u not support\n",
__func__, bck);
return -EINVAL;
}
/* con0 */
mask |= ETDM_CON0_BIT_LEN_MASK;
val |= FIELD_PREP(ETDM_CON0_BIT_LEN_MASK, bit_width - 1);
mask |= ETDM_CON0_WORD_LEN_MASK;
val |= FIELD_PREP(ETDM_CON0_WORD_LEN_MASK, wlen - 1);
mask |= ETDM_CON0_FORMAT_MASK;
val |= FIELD_PREP(ETDM_CON0_FORMAT_MASK, etdm_data->format);
mask |= ETDM_CON0_CH_NUM_MASK;
val |= FIELD_PREP(ETDM_CON0_CH_NUM_MASK, etdm_channels - 1);
mask |= ETDM_CON0_SLAVE_MODE;
if (slave_mode) {
if (dai_id == MT8188_AFE_IO_ETDM1_OUT) {
dev_err(afe->dev, "%s id %d only support master mode\n",
__func__, dai_id);
return -EINVAL;
}
val |= ETDM_CON0_SLAVE_MODE;
}
regmap_update_bits(afe->regmap, etdm_reg.con0, mask, val);
if (get_etdm_dir(dai_id) == ETDM_IN)
mtk_dai_etdm_in_configure(afe, rate, channels, dai_id);
else
mtk_dai_etdm_out_configure(afe, rate, channels, dai_id);
return 0;
}
static int mtk_dai_etdm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
unsigned int rate = params_rate(params);
unsigned int bit_width = params_width(params);
unsigned int channels = params_channels(params);
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8188_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_etdm_priv *mst_etdm_data;
int mst_dai_id;
int slv_dai_id;
int ret;
int i;
dev_dbg(afe->dev, "%s '%s' period %u-%u\n",
__func__, snd_pcm_stream_str(substream),
params_period_size(params), params_periods(params));
if (is_cowork_mode(dai)) {
mst_dai_id = get_etdm_cowork_master_id(dai);
if (!is_valid_etdm_dai(mst_dai_id))
return -EINVAL;
mst_etdm_data = afe_priv->dai_priv[mst_dai_id];
if (mst_etdm_data->slots)
channels = mst_etdm_data->slots;
ret = mtk_dai_etdm_configure(afe, rate, channels,
bit_width, mst_dai_id);
if (ret)
return ret;
for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) {
slv_dai_id = mst_etdm_data->cowork_slv_id[i];
ret = mtk_dai_etdm_configure(afe, rate, channels,
bit_width, slv_dai_id);
if (ret)
return ret;
ret = mt8188_etdm_sync_mode_configure(afe, slv_dai_id);
if (ret)
return ret;
}
} else {
if (!is_valid_etdm_dai(dai->id))
return -EINVAL;
mst_etdm_data = afe_priv->dai_priv[dai->id];
if (mst_etdm_data->slots)
channels = mst_etdm_data->slots;
ret = mtk_dai_etdm_configure(afe, rate, channels,
bit_width, dai->id);
if (ret)
return ret;
}
return 0;
}
static int mtk_dai_etdm_cal_mclk(struct mtk_base_afe *afe, int freq, int dai_id)
{
struct mt8188_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_etdm_priv *etdm_data;
int apll_rate;
int apll;
if (!is_valid_etdm_dai(dai_id))
return -EINVAL;
etdm_data = afe_priv->dai_priv[dai_id];
if (freq == 0) {
etdm_data->mclk_freq = freq;
return 0;
}
if (etdm_data->mclk_fixed_apll == 0)
apll = mt8188_afe_get_default_mclk_source_by_rate(freq);
else
apll = etdm_data->mclk_apll;
apll_rate = mt8188_afe_get_mclk_source_rate(afe, apll);
if (freq > apll_rate) {
dev_err(afe->dev, "freq %d > apll rate %d\n", freq, apll_rate);
return -EINVAL;
}
if (apll_rate % freq != 0) {
dev_err(afe->dev, "APLL%d cannot generate freq Hz\n", apll);
return -EINVAL;
}
if (etdm_data->mclk_fixed_apll == 0)
etdm_data->mclk_apll = apll;
etdm_data->mclk_freq = freq;
return 0;
}
static int mtk_dai_etdm_set_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8188_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_etdm_priv *etdm_data;
int dai_id;
dev_dbg(dai->dev, "%s id %d freq %u, dir %d\n",
__func__, dai->id, freq, dir);
if (is_cowork_mode(dai))
dai_id = get_etdm_cowork_master_id(dai);
else
dai_id = dai->id;
if (!is_valid_etdm_dai(dai_id))
return -EINVAL;
etdm_data = afe_priv->dai_priv[dai_id];
etdm_data->mclk_dir = dir;
return mtk_dai_etdm_cal_mclk(afe, freq, dai_id);
}
static int mtk_dai_etdm_set_tdm_slot(struct snd_soc_dai *dai,
unsigned int tx_mask, unsigned int rx_mask,
int slots, int slot_width)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8188_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_etdm_priv *etdm_data;
int dai_id;
if (is_cowork_mode(dai))
dai_id = get_etdm_cowork_master_id(dai);
else
dai_id = dai->id;
if (!is_valid_etdm_dai(dai_id))
return -EINVAL;
etdm_data = afe_priv->dai_priv[dai_id];
dev_dbg(dai->dev, "%s id %d slot_width %d\n",
__func__, dai->id, slot_width);
etdm_data->slots = slots;
etdm_data->lrck_width = slot_width;
return 0;
}
static int mtk_dai_etdm_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8188_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_etdm_priv *etdm_data;
if (!is_valid_etdm_dai(dai->id))
return -EINVAL;
etdm_data = afe_priv->dai_priv[dai->id];
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
etdm_data->format = MTK_DAI_ETDM_FORMAT_I2S;
break;
case SND_SOC_DAIFMT_LEFT_J:
etdm_data->format = MTK_DAI_ETDM_FORMAT_LJ;
break;
case SND_SOC_DAIFMT_RIGHT_J:
etdm_data->format = MTK_DAI_ETDM_FORMAT_RJ;
break;
case SND_SOC_DAIFMT_DSP_A:
etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPA;
break;
case SND_SOC_DAIFMT_DSP_B:
etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPB;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
etdm_data->bck_inv = false;
etdm_data->lrck_inv = false;
break;
case SND_SOC_DAIFMT_NB_IF:
etdm_data->bck_inv = false;
etdm_data->lrck_inv = true;
break;
case SND_SOC_DAIFMT_IB_NF:
etdm_data->bck_inv = true;
etdm_data->lrck_inv = false;
break;
case SND_SOC_DAIFMT_IB_IF:
etdm_data->bck_inv = true;
etdm_data->lrck_inv = true;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BC_FC:
etdm_data->slave_mode = true;
break;
case SND_SOC_DAIFMT_BP_FP:
etdm_data->slave_mode = false;
break;
default:
return -EINVAL;
}
return 0;
}
static unsigned int mtk_dai_get_dptx_ch_en(unsigned int channel)
{
switch (channel) {
case 1 ... 2:
return AFE_DPTX_CON_CH_EN_2CH;
case 3 ... 4:
return AFE_DPTX_CON_CH_EN_4CH;
case 5 ... 6:
return AFE_DPTX_CON_CH_EN_6CH;
case 7 ... 8:
return AFE_DPTX_CON_CH_EN_8CH;
default:
return AFE_DPTX_CON_CH_EN_2CH;
}
}
static unsigned int mtk_dai_get_dptx_ch(unsigned int ch)
{
return (ch > 2) ?
AFE_DPTX_CON_CH_NUM_8CH : AFE_DPTX_CON_CH_NUM_2CH;
}
static unsigned int mtk_dai_get_dptx_wlen(snd_pcm_format_t format)
{
return snd_pcm_format_physical_width(format) <= 16 ?
AFE_DPTX_CON_16BIT : AFE_DPTX_CON_24BIT;
}
static int mtk_dai_hdmitx_dptx_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8188_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_etdm_priv *etdm_data;
unsigned int rate = params_rate(params);
unsigned int channels = params_channels(params);
snd_pcm_format_t format = params_format(params);
int width = snd_pcm_format_physical_width(format);
int ret;
if (!is_valid_etdm_dai(dai->id))
return -EINVAL;
etdm_data = afe_priv->dai_priv[dai->id];
/* dptx configure */
if (dai->id == MT8188_AFE_IO_DPTX) {
regmap_update_bits(afe->regmap, AFE_DPTX_CON,
AFE_DPTX_CON_CH_EN_MASK,
mtk_dai_get_dptx_ch_en(channels));
regmap_update_bits(afe->regmap, AFE_DPTX_CON,
AFE_DPTX_CON_CH_NUM_MASK,
mtk_dai_get_dptx_ch(channels));
regmap_update_bits(afe->regmap, AFE_DPTX_CON,
AFE_DPTX_CON_16BIT_MASK,
mtk_dai_get_dptx_wlen(format));
if (mtk_dai_get_dptx_ch(channels) == AFE_DPTX_CON_CH_NUM_8CH) {
etdm_data->data_mode = MTK_DAI_ETDM_DATA_ONE_PIN;
channels = 8;
} else {
channels = 2;
}
} else {
etdm_data->data_mode = MTK_DAI_ETDM_DATA_MULTI_PIN;
}
ret = mtk_dai_etdm_configure(afe, rate, channels, width, dai->id);
return ret;
}
static int mtk_dai_hdmitx_dptx_set_sysclk(struct snd_soc_dai *dai,
int clk_id,
unsigned int freq,
int dir)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8188_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_etdm_priv *etdm_data;
if (!is_valid_etdm_dai(dai->id))
return -EINVAL;
etdm_data = afe_priv->dai_priv[dai->id];
dev_dbg(dai->dev, "%s id %d freq %u, dir %d\n",
__func__, dai->id, freq, dir);
etdm_data->mclk_dir = dir;
return mtk_dai_etdm_cal_mclk(afe, freq, dai->id);
}
static const struct snd_soc_dai_ops mtk_dai_etdm_ops = {
.hw_params = mtk_dai_etdm_hw_params,
.set_sysclk = mtk_dai_etdm_set_sysclk,
.set_fmt = mtk_dai_etdm_set_fmt,
.set_tdm_slot = mtk_dai_etdm_set_tdm_slot,
};
static const struct snd_soc_dai_ops mtk_dai_hdmitx_dptx_ops = {
.hw_params = mtk_dai_hdmitx_dptx_hw_params,
.set_sysclk = mtk_dai_hdmitx_dptx_set_sysclk,
.set_fmt = mtk_dai_etdm_set_fmt,
};
/* dai driver */
#define MTK_ETDM_RATES (SNDRV_PCM_RATE_8000_192000)
#define MTK_ETDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver mtk_dai_etdm_driver[] = {
{
.name = "DPTX",
.id = MT8188_AFE_IO_DPTX,
.playback = {
.stream_name = "DPTX",
.channels_min = 1,
.channels_max = 8,
.rates = MTK_ETDM_RATES,
.formats = MTK_ETDM_FORMATS,
},
.ops = &mtk_dai_hdmitx_dptx_ops,
},
{
.name = "ETDM1_IN",
.id = MT8188_AFE_IO_ETDM1_IN,
.capture = {
.stream_name = "ETDM1_IN",
.channels_min = 1,
.channels_max = 16,
.rates = MTK_ETDM_RATES,
.formats = MTK_ETDM_FORMATS,
},
.ops = &mtk_dai_etdm_ops,
},
{
.name = "ETDM2_IN",
.id = MT8188_AFE_IO_ETDM2_IN,
.capture = {
.stream_name = "ETDM2_IN",
.channels_min = 1,
.channels_max = 16,
.rates = MTK_ETDM_RATES,
.formats = MTK_ETDM_FORMATS,
},
.ops = &mtk_dai_etdm_ops,
},
{
.name = "ETDM1_OUT",
.id = MT8188_AFE_IO_ETDM1_OUT,
.playback = {
.stream_name = "ETDM1_OUT",
.channels_min = 1,
.channels_max = 16,
.rates = MTK_ETDM_RATES,
.formats = MTK_ETDM_FORMATS,
},
.ops = &mtk_dai_etdm_ops,
},
{
.name = "ETDM2_OUT",
.id = MT8188_AFE_IO_ETDM2_OUT,
.playback = {
.stream_name = "ETDM2_OUT",
.channels_min = 1,
.channels_max = 16,
.rates = MTK_ETDM_RATES,
.formats = MTK_ETDM_FORMATS,
},
.ops = &mtk_dai_etdm_ops,
},
{
.name = "ETDM3_OUT",
.id = MT8188_AFE_IO_ETDM3_OUT,
.playback = {
.stream_name = "ETDM3_OUT",
.channels_min = 1,
.channels_max = 8,
.rates = MTK_ETDM_RATES,
.formats = MTK_ETDM_FORMATS,
},
.ops = &mtk_dai_hdmitx_dptx_ops,
},
};
static void mt8188_etdm_update_sync_info(struct mtk_base_afe *afe)
{
struct mt8188_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_etdm_priv *etdm_data;
struct mtk_dai_etdm_priv *mst_data;
int mst_dai_id;
int i;
for (i = MT8188_AFE_IO_ETDM_START; i < MT8188_AFE_IO_ETDM_END; i++) {
etdm_data = afe_priv->dai_priv[i];
if (etdm_data->cowork_source_id != COWORK_ETDM_NONE) {
mst_dai_id = etdm_data->cowork_source_id;
mst_data = afe_priv->dai_priv[mst_dai_id];
if (mst_data->cowork_source_id != COWORK_ETDM_NONE)
dev_err(afe->dev, "%s [%d] wrong sync source\n",
__func__, i);
mst_data->cowork_slv_id[mst_data->cowork_slv_count] = i;
mst_data->cowork_slv_count++;
}
}
}
static void mt8188_dai_etdm_parse_of(struct mtk_base_afe *afe)
{
const struct device_node *of_node = afe->dev->of_node;
struct mt8188_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_etdm_priv *etdm_data;
char prop[48];
u8 disable_chn[MT8188_ETDM_MAX_CHANNELS];
int max_chn = MT8188_ETDM_MAX_CHANNELS;
unsigned int sync_id;
u32 sel;
int ret;
int dai_id;
int i, j;
struct {
const char *name;
const unsigned int sync_id;
} of_afe_etdms[MT8188_AFE_IO_ETDM_NUM] = {
{"etdm-in1", ETDM_SYNC_FROM_IN1},
{"etdm-in2", ETDM_SYNC_FROM_IN2},
{"etdm-out1", ETDM_SYNC_FROM_OUT1},
{"etdm-out2", ETDM_SYNC_FROM_OUT2},
{"etdm-out3", ETDM_SYNC_FROM_OUT3},
};
for (i = 0; i < MT8188_AFE_IO_ETDM_NUM; i++) {
dai_id = ETDM_TO_DAI_ID(i);
etdm_data = afe_priv->dai_priv[dai_id];
snprintf(prop, sizeof(prop), "mediatek,%s-multi-pin-mode",
of_afe_etdms[i].name);
etdm_data->data_mode = of_property_read_bool(of_node, prop);
snprintf(prop, sizeof(prop), "mediatek,%s-cowork-source",
of_afe_etdms[i].name);
ret = of_property_read_u32(of_node, prop, &sel);
if (ret == 0) {
if (sel >= MT8188_AFE_IO_ETDM_NUM) {
dev_err(afe->dev, "%s invalid id=%d\n",
__func__, sel);
etdm_data->cowork_source_id = COWORK_ETDM_NONE;
} else {
sync_id = of_afe_etdms[sel].sync_id;
etdm_data->cowork_source_id =
sync_to_dai_id(sync_id);
}
} else {
etdm_data->cowork_source_id = COWORK_ETDM_NONE;
}
}
/* etdm in only */
for (i = 0; i < 2; i++) {
dai_id = ETDM_TO_DAI_ID(i);
etdm_data = afe_priv->dai_priv[dai_id];
snprintf(prop, sizeof(prop), "mediatek,%s-chn-disabled",
of_afe_etdms[i].name);
ret = of_property_read_variable_u8_array(of_node, prop,
disable_chn,
1, max_chn);
if (ret < 0)
continue;
for (j = 0; j < ret; j++) {
if (disable_chn[j] >= MT8188_ETDM_MAX_CHANNELS)
dev_err(afe->dev, "%s [%d] invalid chn %u\n",
__func__, j, disable_chn[j]);
else
etdm_data->in_disable_ch[disable_chn[j]] = true;
}
}
mt8188_etdm_update_sync_info(afe);
}
static int init_etdm_priv_data(struct mtk_base_afe *afe)
{
struct mt8188_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_etdm_priv *etdm_priv;
int i;
for (i = MT8188_AFE_IO_ETDM_START; i < MT8188_AFE_IO_ETDM_END; i++) {
etdm_priv = devm_kzalloc(afe->dev,
sizeof(struct mtk_dai_etdm_priv),
GFP_KERNEL);
if (!etdm_priv)
return -ENOMEM;
afe_priv->dai_priv[i] = etdm_priv;
}
afe_priv->dai_priv[MT8188_AFE_IO_DPTX] =
afe_priv->dai_priv[MT8188_AFE_IO_ETDM3_OUT];
mt8188_dai_etdm_parse_of(afe);
return 0;
}
int mt8188_dai_etdm_register(struct mtk_base_afe *afe)
{
struct mtk_base_afe_dai *dai;
dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
if (!dai)
return -ENOMEM;
list_add(&dai->list, &afe->sub_dais);
dai->dai_drivers = mtk_dai_etdm_driver;
dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_etdm_driver);
dai->dapm_widgets = mtk_dai_etdm_widgets;
dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_etdm_widgets);
dai->dapm_routes = mtk_dai_etdm_routes;
dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_etdm_routes);
dai->controls = mtk_dai_etdm_controls;
dai->num_controls = ARRAY_SIZE(mtk_dai_etdm_controls);
return init_etdm_priv_data(afe);
}
| linux-master | sound/soc/mediatek/mt8188/mt8188-dai-etdm.c |
// SPDX-License-Identifier: GPL-2.0
/*
* mt8188-afe-clk.c -- MediaTek 8188 afe clock ctrl
*
* Copyright (c) 2022 MediaTek Inc.
* Author: Bicycle Tsai <[email protected]>
* Trevor Wu <[email protected]>
* Chun-Chia Chiu <[email protected]>
*/
#include <linux/clk.h>
#include "mt8188-afe-common.h"
#include "mt8188-afe-clk.h"
#include "mt8188-audsys-clk.h"
#include "mt8188-reg.h"
static const char *aud_clks[MT8188_CLK_NUM] = {
/* xtal */
[MT8188_CLK_XTAL_26M] = "clk26m",
/* pll */
[MT8188_CLK_APMIXED_APLL1] = "apll1",
[MT8188_CLK_APMIXED_APLL2] = "apll2",
/* divider */
[MT8188_CLK_TOP_APLL1_D4] = "apll1_d4",
[MT8188_CLK_TOP_APLL2_D4] = "apll2_d4",
[MT8188_CLK_TOP_APLL12_DIV0] = "apll12_div0",
[MT8188_CLK_TOP_APLL12_DIV1] = "apll12_div1",
[MT8188_CLK_TOP_APLL12_DIV2] = "apll12_div2",
[MT8188_CLK_TOP_APLL12_DIV3] = "apll12_div3",
[MT8188_CLK_TOP_APLL12_DIV4] = "apll12_div4",
[MT8188_CLK_TOP_APLL12_DIV9] = "apll12_div9",
/* mux */
[MT8188_CLK_TOP_A1SYS_HP_SEL] = "top_a1sys_hp",
[MT8188_CLK_TOP_A2SYS_SEL] = "top_a2sys",
[MT8188_CLK_TOP_AUD_IEC_SEL] = "top_aud_iec",
[MT8188_CLK_TOP_AUD_INTBUS_SEL] = "top_aud_intbus",
[MT8188_CLK_TOP_AUDIO_H_SEL] = "top_audio_h",
[MT8188_CLK_TOP_AUDIO_LOCAL_BUS_SEL] = "top_audio_local_bus",
[MT8188_CLK_TOP_DPTX_M_SEL] = "top_dptx",
[MT8188_CLK_TOP_I2SO1_M_SEL] = "top_i2so1",
[MT8188_CLK_TOP_I2SO2_M_SEL] = "top_i2so2",
[MT8188_CLK_TOP_I2SI1_M_SEL] = "top_i2si1",
[MT8188_CLK_TOP_I2SI2_M_SEL] = "top_i2si2",
/* clock gate */
[MT8188_CLK_ADSP_AUDIO_26M] = "adsp_audio_26m",
/* afe clock gate */
[MT8188_CLK_AUD_AFE] = "aud_afe",
[MT8188_CLK_AUD_APLL1_TUNER] = "aud_apll1_tuner",
[MT8188_CLK_AUD_APLL2_TUNER] = "aud_apll2_tuner",
[MT8188_CLK_AUD_APLL] = "aud_apll",
[MT8188_CLK_AUD_APLL2] = "aud_apll2",
[MT8188_CLK_AUD_DAC] = "aud_dac",
[MT8188_CLK_AUD_ADC] = "aud_adc",
[MT8188_CLK_AUD_DAC_HIRES] = "aud_dac_hires",
[MT8188_CLK_AUD_A1SYS_HP] = "aud_a1sys_hp",
[MT8188_CLK_AUD_ADC_HIRES] = "aud_adc_hires",
[MT8188_CLK_AUD_I2SIN] = "aud_i2sin",
[MT8188_CLK_AUD_TDM_IN] = "aud_tdm_in",
[MT8188_CLK_AUD_I2S_OUT] = "aud_i2s_out",
[MT8188_CLK_AUD_TDM_OUT] = "aud_tdm_out",
[MT8188_CLK_AUD_HDMI_OUT] = "aud_hdmi_out",
[MT8188_CLK_AUD_ASRC11] = "aud_asrc11",
[MT8188_CLK_AUD_ASRC12] = "aud_asrc12",
[MT8188_CLK_AUD_A1SYS] = "aud_a1sys",
[MT8188_CLK_AUD_A2SYS] = "aud_a2sys",
[MT8188_CLK_AUD_PCMIF] = "aud_pcmif",
[MT8188_CLK_AUD_MEMIF_UL1] = "aud_memif_ul1",
[MT8188_CLK_AUD_MEMIF_UL2] = "aud_memif_ul2",
[MT8188_CLK_AUD_MEMIF_UL3] = "aud_memif_ul3",
[MT8188_CLK_AUD_MEMIF_UL4] = "aud_memif_ul4",
[MT8188_CLK_AUD_MEMIF_UL5] = "aud_memif_ul5",
[MT8188_CLK_AUD_MEMIF_UL6] = "aud_memif_ul6",
[MT8188_CLK_AUD_MEMIF_UL8] = "aud_memif_ul8",
[MT8188_CLK_AUD_MEMIF_UL9] = "aud_memif_ul9",
[MT8188_CLK_AUD_MEMIF_UL10] = "aud_memif_ul10",
[MT8188_CLK_AUD_MEMIF_DL2] = "aud_memif_dl2",
[MT8188_CLK_AUD_MEMIF_DL3] = "aud_memif_dl3",
[MT8188_CLK_AUD_MEMIF_DL6] = "aud_memif_dl6",
[MT8188_CLK_AUD_MEMIF_DL7] = "aud_memif_dl7",
[MT8188_CLK_AUD_MEMIF_DL8] = "aud_memif_dl8",
[MT8188_CLK_AUD_MEMIF_DL10] = "aud_memif_dl10",
[MT8188_CLK_AUD_MEMIF_DL11] = "aud_memif_dl11",
};
struct mt8188_afe_tuner_cfg {
unsigned int id;
int apll_div_reg;
unsigned int apll_div_shift;
unsigned int apll_div_maskbit;
unsigned int apll_div_default;
int ref_ck_sel_reg;
unsigned int ref_ck_sel_shift;
unsigned int ref_ck_sel_maskbit;
unsigned int ref_ck_sel_default;
int tuner_en_reg;
unsigned int tuner_en_shift;
unsigned int tuner_en_maskbit;
int upper_bound_reg;
unsigned int upper_bound_shift;
unsigned int upper_bound_maskbit;
unsigned int upper_bound_default;
spinlock_t ctrl_lock; /* lock for apll tuner ctrl*/
int ref_cnt;
};
static struct mt8188_afe_tuner_cfg
mt8188_afe_tuner_cfgs[MT8188_AUD_PLL_NUM] = {
[MT8188_AUD_PLL1] = {
.id = MT8188_AUD_PLL1,
.apll_div_reg = AFE_APLL_TUNER_CFG,
.apll_div_shift = 4,
.apll_div_maskbit = 0xf,
.apll_div_default = 0x7,
.ref_ck_sel_reg = AFE_APLL_TUNER_CFG,
.ref_ck_sel_shift = 1,
.ref_ck_sel_maskbit = 0x3,
.ref_ck_sel_default = 0x2,
.tuner_en_reg = AFE_APLL_TUNER_CFG,
.tuner_en_shift = 0,
.tuner_en_maskbit = 0x1,
.upper_bound_reg = AFE_APLL_TUNER_CFG,
.upper_bound_shift = 8,
.upper_bound_maskbit = 0xff,
.upper_bound_default = 0x3,
},
[MT8188_AUD_PLL2] = {
.id = MT8188_AUD_PLL2,
.apll_div_reg = AFE_APLL_TUNER_CFG1,
.apll_div_shift = 4,
.apll_div_maskbit = 0xf,
.apll_div_default = 0x7,
.ref_ck_sel_reg = AFE_APLL_TUNER_CFG1,
.ref_ck_sel_shift = 1,
.ref_ck_sel_maskbit = 0x3,
.ref_ck_sel_default = 0x1,
.tuner_en_reg = AFE_APLL_TUNER_CFG1,
.tuner_en_shift = 0,
.tuner_en_maskbit = 0x1,
.upper_bound_reg = AFE_APLL_TUNER_CFG1,
.upper_bound_shift = 8,
.upper_bound_maskbit = 0xff,
.upper_bound_default = 0x3,
},
[MT8188_AUD_PLL3] = {
.id = MT8188_AUD_PLL3,
.apll_div_reg = AFE_EARC_APLL_TUNER_CFG,
.apll_div_shift = 4,
.apll_div_maskbit = 0x3f,
.apll_div_default = 0x3,
.ref_ck_sel_reg = AFE_EARC_APLL_TUNER_CFG,
.ref_ck_sel_shift = 24,
.ref_ck_sel_maskbit = 0x3,
.ref_ck_sel_default = 0x0,
.tuner_en_reg = AFE_EARC_APLL_TUNER_CFG,
.tuner_en_shift = 0,
.tuner_en_maskbit = 0x1,
.upper_bound_reg = AFE_EARC_APLL_TUNER_CFG,
.upper_bound_shift = 12,
.upper_bound_maskbit = 0xff,
.upper_bound_default = 0x4,
},
[MT8188_AUD_PLL4] = {
.id = MT8188_AUD_PLL4,
.apll_div_reg = AFE_SPDIFIN_APLL_TUNER_CFG,
.apll_div_shift = 4,
.apll_div_maskbit = 0x3f,
.apll_div_default = 0x7,
.ref_ck_sel_reg = AFE_SPDIFIN_APLL_TUNER_CFG1,
.ref_ck_sel_shift = 8,
.ref_ck_sel_maskbit = 0x1,
.ref_ck_sel_default = 0,
.tuner_en_reg = AFE_SPDIFIN_APLL_TUNER_CFG,
.tuner_en_shift = 0,
.tuner_en_maskbit = 0x1,
.upper_bound_reg = AFE_SPDIFIN_APLL_TUNER_CFG,
.upper_bound_shift = 12,
.upper_bound_maskbit = 0xff,
.upper_bound_default = 0x4,
},
[MT8188_AUD_PLL5] = {
.id = MT8188_AUD_PLL5,
.apll_div_reg = AFE_LINEIN_APLL_TUNER_CFG,
.apll_div_shift = 4,
.apll_div_maskbit = 0x3f,
.apll_div_default = 0x3,
.ref_ck_sel_reg = AFE_LINEIN_APLL_TUNER_CFG,
.ref_ck_sel_shift = 24,
.ref_ck_sel_maskbit = 0x1,
.ref_ck_sel_default = 0,
.tuner_en_reg = AFE_LINEIN_APLL_TUNER_CFG,
.tuner_en_shift = 0,
.tuner_en_maskbit = 0x1,
.upper_bound_reg = AFE_LINEIN_APLL_TUNER_CFG,
.upper_bound_shift = 12,
.upper_bound_maskbit = 0xff,
.upper_bound_default = 0x4,
},
};
static struct mt8188_afe_tuner_cfg *mt8188_afe_found_apll_tuner(unsigned int id)
{
if (id >= MT8188_AUD_PLL_NUM)
return NULL;
return &mt8188_afe_tuner_cfgs[id];
}
static int mt8188_afe_init_apll_tuner(unsigned int id)
{
struct mt8188_afe_tuner_cfg *cfg = mt8188_afe_found_apll_tuner(id);
if (!cfg)
return -EINVAL;
cfg->ref_cnt = 0;
spin_lock_init(&cfg->ctrl_lock);
return 0;
}
static int mt8188_afe_setup_apll_tuner(struct mtk_base_afe *afe, unsigned int id)
{
const struct mt8188_afe_tuner_cfg *cfg = mt8188_afe_found_apll_tuner(id);
if (!cfg)
return -EINVAL;
regmap_update_bits(afe->regmap,
cfg->apll_div_reg,
cfg->apll_div_maskbit << cfg->apll_div_shift,
cfg->apll_div_default << cfg->apll_div_shift);
regmap_update_bits(afe->regmap,
cfg->ref_ck_sel_reg,
cfg->ref_ck_sel_maskbit << cfg->ref_ck_sel_shift,
cfg->ref_ck_sel_default << cfg->ref_ck_sel_shift);
regmap_update_bits(afe->regmap,
cfg->upper_bound_reg,
cfg->upper_bound_maskbit << cfg->upper_bound_shift,
cfg->upper_bound_default << cfg->upper_bound_shift);
return 0;
}
static int mt8188_afe_enable_tuner_clk(struct mtk_base_afe *afe,
unsigned int id)
{
struct mt8188_afe_private *afe_priv = afe->platform_priv;
switch (id) {
case MT8188_AUD_PLL1:
mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL]);
mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL1_TUNER]);
break;
case MT8188_AUD_PLL2:
mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL2]);
mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL2_TUNER]);
break;
default:
return -EINVAL;
}
return 0;
}
static int mt8188_afe_disable_tuner_clk(struct mtk_base_afe *afe,
unsigned int id)
{
struct mt8188_afe_private *afe_priv = afe->platform_priv;
switch (id) {
case MT8188_AUD_PLL1:
mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL1_TUNER]);
mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL]);
break;
case MT8188_AUD_PLL2:
mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL2_TUNER]);
mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL2]);
break;
default:
return -EINVAL;
}
return 0;
}
static int mt8188_afe_enable_apll_tuner(struct mtk_base_afe *afe, unsigned int id)
{
struct mt8188_afe_tuner_cfg *cfg = mt8188_afe_found_apll_tuner(id);
unsigned long flags;
int ret;
if (!cfg)
return -EINVAL;
ret = mt8188_afe_setup_apll_tuner(afe, id);
if (ret)
return ret;
ret = mt8188_afe_enable_tuner_clk(afe, id);
if (ret)
return ret;
spin_lock_irqsave(&cfg->ctrl_lock, flags);
cfg->ref_cnt++;
if (cfg->ref_cnt == 1)
regmap_update_bits(afe->regmap,
cfg->tuner_en_reg,
cfg->tuner_en_maskbit << cfg->tuner_en_shift,
BIT(cfg->tuner_en_shift));
spin_unlock_irqrestore(&cfg->ctrl_lock, flags);
return 0;
}
static int mt8188_afe_disable_apll_tuner(struct mtk_base_afe *afe, unsigned int id)
{
struct mt8188_afe_tuner_cfg *cfg = mt8188_afe_found_apll_tuner(id);
unsigned long flags;
int ret;
if (!cfg)
return -EINVAL;
spin_lock_irqsave(&cfg->ctrl_lock, flags);
cfg->ref_cnt--;
if (cfg->ref_cnt == 0)
regmap_update_bits(afe->regmap,
cfg->tuner_en_reg,
cfg->tuner_en_maskbit << cfg->tuner_en_shift,
0 << cfg->tuner_en_shift);
else if (cfg->ref_cnt < 0)
cfg->ref_cnt = 0;
spin_unlock_irqrestore(&cfg->ctrl_lock, flags);
ret = mt8188_afe_disable_tuner_clk(afe, id);
if (ret)
return ret;
return 0;
}
int mt8188_afe_get_mclk_source_clk_id(int sel)
{
switch (sel) {
case MT8188_MCK_SEL_26M:
return MT8188_CLK_XTAL_26M;
case MT8188_MCK_SEL_APLL1:
return MT8188_CLK_APMIXED_APLL1;
case MT8188_MCK_SEL_APLL2:
return MT8188_CLK_APMIXED_APLL2;
default:
return -EINVAL;
}
}
int mt8188_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll)
{
struct mt8188_afe_private *afe_priv = afe->platform_priv;
int clk_id = mt8188_afe_get_mclk_source_clk_id(apll);
if (clk_id < 0) {
dev_dbg(afe->dev, "invalid clk id\n");
return 0;
}
return clk_get_rate(afe_priv->clk[clk_id]);
}
int mt8188_afe_get_default_mclk_source_by_rate(int rate)
{
return ((rate % 8000) == 0) ?
MT8188_MCK_SEL_APLL1 : MT8188_MCK_SEL_APLL2;
}
int mt8188_get_apll_by_rate(struct mtk_base_afe *afe, int rate)
{
return ((rate % 8000) == 0) ? MT8188_AUD_PLL1 : MT8188_AUD_PLL2;
}
int mt8188_get_apll_by_name(struct mtk_base_afe *afe, const char *name)
{
if (strcmp(name, APLL1_W_NAME) == 0)
return MT8188_AUD_PLL1;
return MT8188_AUD_PLL2;
}
int mt8188_afe_init_clock(struct mtk_base_afe *afe)
{
struct mt8188_afe_private *afe_priv = afe->platform_priv;
int i, ret;
ret = mt8188_audsys_clk_register(afe);
if (ret) {
dev_err(afe->dev, "register audsys clk fail %d\n", ret);
return ret;
}
afe_priv->clk =
devm_kcalloc(afe->dev, MT8188_CLK_NUM, sizeof(*afe_priv->clk),
GFP_KERNEL);
if (!afe_priv->clk)
return -ENOMEM;
for (i = 0; i < MT8188_CLK_NUM; i++) {
afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);
if (IS_ERR(afe_priv->clk[i])) {
dev_err(afe->dev, "%s(), devm_clk_get %s fail, ret %ld\n",
__func__, aud_clks[i],
PTR_ERR(afe_priv->clk[i]));
return PTR_ERR(afe_priv->clk[i]);
}
}
/* initial tuner */
for (i = 0; i < MT8188_AUD_PLL_NUM; i++) {
ret = mt8188_afe_init_apll_tuner(i);
if (ret) {
dev_info(afe->dev, "%s(), init apll_tuner%d failed",
__func__, (i + 1));
return -EINVAL;
}
}
return 0;
}
int mt8188_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk)
{
int ret;
if (clk) {
ret = clk_prepare_enable(clk);
if (ret) {
dev_dbg(afe->dev, "%s(), failed to enable clk\n",
__func__);
return ret;
}
} else {
dev_dbg(afe->dev, "NULL clk\n");
}
return 0;
}
EXPORT_SYMBOL_GPL(mt8188_afe_enable_clk);
void mt8188_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk)
{
if (clk)
clk_disable_unprepare(clk);
else
dev_dbg(afe->dev, "NULL clk\n");
}
EXPORT_SYMBOL_GPL(mt8188_afe_disable_clk);
int mt8188_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk,
unsigned int rate)
{
int ret;
if (clk) {
ret = clk_set_rate(clk, rate);
if (ret) {
dev_dbg(afe->dev, "%s(), failed to set clk rate\n",
__func__);
return ret;
}
}
return 0;
}
int mt8188_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk,
struct clk *parent)
{
int ret;
if (clk && parent) {
ret = clk_set_parent(clk, parent);
if (ret) {
dev_dbg(afe->dev, "%s(), failed to set clk parent %d\n",
__func__, ret);
return ret;
}
}
return 0;
}
static unsigned int get_top_cg_reg(unsigned int cg_type)
{
switch (cg_type) {
case MT8188_TOP_CG_A1SYS_TIMING:
case MT8188_TOP_CG_A2SYS_TIMING:
case MT8188_TOP_CG_26M_TIMING:
return ASYS_TOP_CON;
default:
return 0;
}
}
static unsigned int get_top_cg_mask(unsigned int cg_type)
{
switch (cg_type) {
case MT8188_TOP_CG_A1SYS_TIMING:
return ASYS_TOP_CON_A1SYS_TIMING_ON;
case MT8188_TOP_CG_A2SYS_TIMING:
return ASYS_TOP_CON_A2SYS_TIMING_ON;
case MT8188_TOP_CG_26M_TIMING:
return ASYS_TOP_CON_26M_TIMING_ON;
default:
return 0;
}
}
static unsigned int get_top_cg_on_val(unsigned int cg_type)
{
switch (cg_type) {
case MT8188_TOP_CG_A1SYS_TIMING:
case MT8188_TOP_CG_A2SYS_TIMING:
case MT8188_TOP_CG_26M_TIMING:
return get_top_cg_mask(cg_type);
default:
return 0;
}
}
static unsigned int get_top_cg_off_val(unsigned int cg_type)
{
switch (cg_type) {
case MT8188_TOP_CG_A1SYS_TIMING:
case MT8188_TOP_CG_A2SYS_TIMING:
case MT8188_TOP_CG_26M_TIMING:
return 0;
default:
return get_top_cg_mask(cg_type);
}
}
static int mt8188_afe_enable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)
{
unsigned int reg = get_top_cg_reg(cg_type);
unsigned int mask = get_top_cg_mask(cg_type);
unsigned int val = get_top_cg_on_val(cg_type);
regmap_update_bits(afe->regmap, reg, mask, val);
return 0;
}
static int mt8188_afe_disable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)
{
unsigned int reg = get_top_cg_reg(cg_type);
unsigned int mask = get_top_cg_mask(cg_type);
unsigned int val = get_top_cg_off_val(cg_type);
regmap_update_bits(afe->regmap, reg, mask, val);
return 0;
}
int mt8188_afe_enable_reg_rw_clk(struct mtk_base_afe *afe)
{
struct mt8188_afe_private *afe_priv = afe->platform_priv;
/* bus clock for AFE external access, like DRAM */
mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_AUDIO_LOCAL_BUS_SEL]);
/* bus clock for AFE internal access, like AFE SRAM */
mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_AUD_INTBUS_SEL]);
/* audio 26m clock source */
mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_ADSP_AUDIO_26M]);
/* AFE hw clock */
mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_AFE]);
mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS_HP]);
mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]);
return 0;
}
int mt8188_afe_disable_reg_rw_clk(struct mtk_base_afe *afe)
{
struct mt8188_afe_private *afe_priv = afe->platform_priv;
mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]);
mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS_HP]);
mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_AFE]);
mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_ADSP_AUDIO_26M]);
mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_AUD_INTBUS_SEL]);
mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_AUDIO_LOCAL_BUS_SEL]);
return 0;
}
static int mt8188_afe_enable_afe_on(struct mtk_base_afe *afe)
{
regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1);
return 0;
}
static int mt8188_afe_disable_afe_on(struct mtk_base_afe *afe)
{
regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x0);
return 0;
}
static int mt8188_afe_enable_a1sys(struct mtk_base_afe *afe)
{
struct mt8188_afe_private *afe_priv = afe->platform_priv;
int ret;
ret = mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]);
if (ret)
return ret;
return mt8188_afe_enable_top_cg(afe, MT8188_TOP_CG_A1SYS_TIMING);
}
static int mt8188_afe_disable_a1sys(struct mtk_base_afe *afe)
{
struct mt8188_afe_private *afe_priv = afe->platform_priv;
mt8188_afe_disable_top_cg(afe, MT8188_TOP_CG_A1SYS_TIMING);
mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]);
return 0;
}
static int mt8188_afe_enable_a2sys(struct mtk_base_afe *afe)
{
struct mt8188_afe_private *afe_priv = afe->platform_priv;
int ret;
ret = mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A2SYS]);
if (ret)
return ret;
return mt8188_afe_enable_top_cg(afe, MT8188_TOP_CG_A2SYS_TIMING);
}
static int mt8188_afe_disable_a2sys(struct mtk_base_afe *afe)
{
struct mt8188_afe_private *afe_priv = afe->platform_priv;
mt8188_afe_disable_top_cg(afe, MT8188_TOP_CG_A2SYS_TIMING);
mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A2SYS]);
return 0;
}
int mt8188_apll1_enable(struct mtk_base_afe *afe)
{
struct mt8188_afe_private *afe_priv = afe->platform_priv;
int ret;
ret = mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_APLL1_D4]);
if (ret)
return ret;
ret = mt8188_afe_set_clk_parent(afe, afe_priv->clk[MT8188_CLK_TOP_A1SYS_HP_SEL],
afe_priv->clk[MT8188_CLK_TOP_APLL1_D4]);
if (ret)
goto err_clk_parent;
ret = mt8188_afe_enable_apll_tuner(afe, MT8188_AUD_PLL1);
if (ret)
goto err_apll_tuner;
ret = mt8188_afe_enable_a1sys(afe);
if (ret)
goto err_a1sys;
return 0;
err_a1sys:
mt8188_afe_disable_apll_tuner(afe, MT8188_AUD_PLL1);
err_apll_tuner:
mt8188_afe_set_clk_parent(afe, afe_priv->clk[MT8188_CLK_TOP_A1SYS_HP_SEL],
afe_priv->clk[MT8188_CLK_XTAL_26M]);
err_clk_parent:
mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_APLL1_D4]);
return ret;
}
int mt8188_apll1_disable(struct mtk_base_afe *afe)
{
struct mt8188_afe_private *afe_priv = afe->platform_priv;
mt8188_afe_disable_a1sys(afe);
mt8188_afe_disable_apll_tuner(afe, MT8188_AUD_PLL1);
mt8188_afe_set_clk_parent(afe, afe_priv->clk[MT8188_CLK_TOP_A1SYS_HP_SEL],
afe_priv->clk[MT8188_CLK_XTAL_26M]);
mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_APLL1_D4]);
return 0;
}
int mt8188_apll2_enable(struct mtk_base_afe *afe)
{
int ret;
ret = mt8188_afe_enable_apll_tuner(afe, MT8188_AUD_PLL2);
if (ret)
return ret;
ret = mt8188_afe_enable_a2sys(afe);
if (ret)
goto err_a2sys;
return 0;
err_a2sys:
mt8188_afe_disable_apll_tuner(afe, MT8188_AUD_PLL2);
return ret;
}
int mt8188_apll2_disable(struct mtk_base_afe *afe)
{
mt8188_afe_disable_a2sys(afe);
mt8188_afe_disable_apll_tuner(afe, MT8188_AUD_PLL2);
return 0;
}
int mt8188_afe_enable_main_clock(struct mtk_base_afe *afe)
{
mt8188_afe_enable_top_cg(afe, MT8188_TOP_CG_26M_TIMING);
mt8188_afe_enable_afe_on(afe);
return 0;
}
int mt8188_afe_disable_main_clock(struct mtk_base_afe *afe)
{
mt8188_afe_disable_afe_on(afe);
mt8188_afe_disable_top_cg(afe, MT8188_TOP_CG_26M_TIMING);
return 0;
}
| linux-master | sound/soc/mediatek/mt8188/mt8188-afe-clk.c |
// SPDX-License-Identifier: GPL-2.0
/*
* MediaTek ALSA SoC Audio DAI PCM I/F Control
*
* Copyright (c) 2022 MediaTek Inc.
* Author: Bicycle Tsai <[email protected]>
* Trevor Wu <[email protected]>
* Chun-Chia Chiu <[email protected]>
*/
#include <linux/bitfield.h>
#include <linux/regmap.h>
#include <sound/pcm_params.h>
#include "mt8188-afe-clk.h"
#include "mt8188-afe-common.h"
#include "mt8188-reg.h"
enum {
MTK_DAI_PCM_FMT_I2S,
MTK_DAI_PCM_FMT_EIAJ,
MTK_DAI_PCM_FMT_MODEA,
MTK_DAI_PCM_FMT_MODEB,
};
enum {
MTK_DAI_PCM_CLK_A1SYS,
MTK_DAI_PCM_CLK_A2SYS,
MTK_DAI_PCM_CLK_26M_48K,
MTK_DAI_PCM_CLK_26M_441K,
};
struct mtk_dai_pcm_rate {
unsigned int rate;
unsigned int reg_value;
};
struct mtk_dai_pcmif_priv {
unsigned int slave_mode;
unsigned int lrck_inv;
unsigned int bck_inv;
unsigned int format;
};
static const struct mtk_dai_pcm_rate mtk_dai_pcm_rates[] = {
{ .rate = 8000, .reg_value = 0, },
{ .rate = 16000, .reg_value = 1, },
{ .rate = 32000, .reg_value = 2, },
{ .rate = 48000, .reg_value = 3, },
{ .rate = 11025, .reg_value = 1, },
{ .rate = 22050, .reg_value = 2, },
{ .rate = 44100, .reg_value = 3, },
};
static int mtk_dai_pcm_mode(unsigned int rate)
{
int i;
for (i = 0; i < ARRAY_SIZE(mtk_dai_pcm_rates); i++)
if (mtk_dai_pcm_rates[i].rate == rate)
return mtk_dai_pcm_rates[i].reg_value;
return -EINVAL;
}
static const struct snd_kcontrol_new mtk_dai_pcm_o000_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN0, 0, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN0_2, 6, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_pcm_o001_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN1, 1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN1_2, 7, 1, 0),
};
static const struct snd_soc_dapm_widget mtk_dai_pcm_widgets[] = {
SND_SOC_DAPM_MIXER("I002", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I003", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("O000", SND_SOC_NOPM, 0, 0,
mtk_dai_pcm_o000_mix,
ARRAY_SIZE(mtk_dai_pcm_o000_mix)),
SND_SOC_DAPM_MIXER("O001", SND_SOC_NOPM, 0, 0,
mtk_dai_pcm_o001_mix,
ARRAY_SIZE(mtk_dai_pcm_o001_mix)),
SND_SOC_DAPM_SUPPLY("PCM_1_EN", PCM_INTF_CON1, 0, 0, NULL, 0),
SND_SOC_DAPM_INPUT("PCM1_INPUT"),
SND_SOC_DAPM_OUTPUT("PCM1_OUTPUT"),
SND_SOC_DAPM_CLOCK_SUPPLY("aud_asrc11"),
SND_SOC_DAPM_CLOCK_SUPPLY("aud_asrc12"),
SND_SOC_DAPM_CLOCK_SUPPLY("aud_pcmif"),
};
static const struct snd_soc_dapm_route mtk_dai_pcm_routes[] = {
{"I002", NULL, "PCM1 Capture"},
{"I003", NULL, "PCM1 Capture"},
{"O000", "I000 Switch", "I000"},
{"O001", "I001 Switch", "I001"},
{"O000", "I070 Switch", "I070"},
{"O001", "I071 Switch", "I071"},
{"PCM1 Playback", NULL, "O000"},
{"PCM1 Playback", NULL, "O001"},
{"PCM1 Playback", NULL, "PCM_1_EN"},
{"PCM1 Playback", NULL, "aud_asrc12"},
{"PCM1 Playback", NULL, "aud_pcmif"},
{"PCM1 Capture", NULL, "PCM_1_EN"},
{"PCM1 Capture", NULL, "aud_asrc11"},
{"PCM1 Capture", NULL, "aud_pcmif"},
{"PCM1_OUTPUT", NULL, "PCM1 Playback"},
{"PCM1 Capture", NULL, "PCM1_INPUT"},
};
static int mtk_dai_pcm_configure(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_pcm_runtime * const runtime = substream->runtime;
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8188_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_pcmif_priv *pcmif_priv = NULL;
unsigned int slave_mode;
unsigned int lrck_inv;
unsigned int bck_inv;
unsigned int fmt;
unsigned int bit_width = dai->sample_bits;
unsigned int val = 0;
unsigned int mask = 0;
int fs = 0;
int mode = 0;
if (dai->id < 0)
return -EINVAL;
pcmif_priv = afe_priv->dai_priv[dai->id];
slave_mode = pcmif_priv->slave_mode;
lrck_inv = pcmif_priv->lrck_inv;
bck_inv = pcmif_priv->bck_inv;
fmt = pcmif_priv->format;
/* sync freq mode */
fs = mt8188_afe_fs_timing(runtime->rate);
if (fs < 0)
return -EINVAL;
val |= FIELD_PREP(PCM_INTF_CON2_SYNC_FREQ_MODE_MASK, fs);
mask |= PCM_INTF_CON2_SYNC_FREQ_MODE_MASK;
/* clk domain sel */
if (runtime->rate % 8000)
val |= FIELD_PREP(PCM_INTF_CON2_CLK_DOMAIN_SEL_MASK,
MTK_DAI_PCM_CLK_26M_441K);
else
val |= FIELD_PREP(PCM_INTF_CON2_CLK_DOMAIN_SEL_MASK,
MTK_DAI_PCM_CLK_26M_48K);
mask |= PCM_INTF_CON2_CLK_DOMAIN_SEL_MASK;
regmap_update_bits(afe->regmap, PCM_INTF_CON2, mask, val);
val = 0;
mask = 0;
/* pcm mode */
mode = mtk_dai_pcm_mode(runtime->rate);
if (mode < 0)
return -EINVAL;
val |= FIELD_PREP(PCM_INTF_CON1_PCM_MODE_MASK, mode);
mask |= PCM_INTF_CON1_PCM_MODE_MASK;
/* pcm format */
val |= FIELD_PREP(PCM_INTF_CON1_PCM_FMT_MASK, fmt);
mask |= PCM_INTF_CON1_PCM_FMT_MASK;
/* pcm sync length */
if (fmt == MTK_DAI_PCM_FMT_MODEA ||
fmt == MTK_DAI_PCM_FMT_MODEB)
val |= FIELD_PREP(PCM_INTF_CON1_SYNC_LENGTH_MASK, 1);
else
val |= FIELD_PREP(PCM_INTF_CON1_SYNC_LENGTH_MASK, bit_width);
mask |= PCM_INTF_CON1_SYNC_LENGTH_MASK;
/* pcm bits, word length */
if (bit_width > 16) {
val |= PCM_INTF_CON1_PCM_24BIT;
val |= PCM_INTF_CON1_PCM_WLEN_64BCK;
} else {
val |= PCM_INTF_CON1_PCM_16BIT;
val |= PCM_INTF_CON1_PCM_WLEN_32BCK;
}
mask |= PCM_INTF_CON1_PCM_BIT_MASK;
mask |= PCM_INTF_CON1_PCM_WLEN_MASK;
/* master/slave */
if (!slave_mode) {
val |= PCM_INTF_CON1_PCM_MASTER;
if (lrck_inv)
val |= PCM_INTF_CON1_SYNC_OUT_INV;
if (bck_inv)
val |= PCM_INTF_CON1_BCLK_OUT_INV;
mask |= PCM_INTF_CON1_CLK_OUT_INV_MASK;
} else {
val |= PCM_INTF_CON1_PCM_SLAVE;
if (lrck_inv)
val |= PCM_INTF_CON1_SYNC_IN_INV;
if (bck_inv)
val |= PCM_INTF_CON1_BCLK_IN_INV;
mask |= PCM_INTF_CON1_CLK_IN_INV_MASK;
// TODO: add asrc setting for slave mode
}
mask |= PCM_INTF_CON1_PCM_M_S_MASK;
regmap_update_bits(afe->regmap, PCM_INTF_CON1, mask, val);
return 0;
}
/* dai ops */
static int mtk_dai_pcm_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
if (snd_soc_dai_get_widget_playback(dai)->active ||
snd_soc_dai_get_widget_capture(dai)->active)
return 0;
return mtk_dai_pcm_configure(substream, dai);
}
static int mtk_dai_pcm_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8188_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_pcmif_priv *pcmif_priv = NULL;
dev_dbg(dai->dev, "%s fmt 0x%x\n", __func__, fmt);
if (dai->id < 0)
return -EINVAL;
pcmif_priv = afe_priv->dai_priv[dai->id];
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
pcmif_priv->format = MTK_DAI_PCM_FMT_I2S;
break;
case SND_SOC_DAIFMT_DSP_A:
pcmif_priv->format = MTK_DAI_PCM_FMT_MODEA;
break;
case SND_SOC_DAIFMT_DSP_B:
pcmif_priv->format = MTK_DAI_PCM_FMT_MODEB;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
pcmif_priv->bck_inv = 0;
pcmif_priv->lrck_inv = 0;
break;
case SND_SOC_DAIFMT_NB_IF:
pcmif_priv->bck_inv = 0;
pcmif_priv->lrck_inv = 1;
break;
case SND_SOC_DAIFMT_IB_NF:
pcmif_priv->bck_inv = 1;
pcmif_priv->lrck_inv = 0;
break;
case SND_SOC_DAIFMT_IB_IF:
pcmif_priv->bck_inv = 1;
pcmif_priv->lrck_inv = 1;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BC_FC:
pcmif_priv->slave_mode = 1;
break;
case SND_SOC_DAIFMT_BP_FP:
pcmif_priv->slave_mode = 0;
break;
default:
return -EINVAL;
}
return 0;
}
static const struct snd_soc_dai_ops mtk_dai_pcm_ops = {
.prepare = mtk_dai_pcm_prepare,
.set_fmt = mtk_dai_pcm_set_fmt,
};
/* dai driver */
#define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000)
#define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver mtk_dai_pcm_driver[] = {
{
.name = "PCM1",
.id = MT8188_AFE_IO_PCM,
.playback = {
.stream_name = "PCM1 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.capture = {
.stream_name = "PCM1 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_dai_pcm_ops,
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
},
};
static int init_pcmif_priv_data(struct mtk_base_afe *afe)
{
struct mt8188_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_pcmif_priv *pcmif_priv;
pcmif_priv = devm_kzalloc(afe->dev, sizeof(struct mtk_dai_pcmif_priv),
GFP_KERNEL);
if (!pcmif_priv)
return -ENOMEM;
afe_priv->dai_priv[MT8188_AFE_IO_PCM] = pcmif_priv;
return 0;
}
int mt8188_dai_pcm_register(struct mtk_base_afe *afe)
{
struct mtk_base_afe_dai *dai;
dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
if (!dai)
return -ENOMEM;
list_add(&dai->list, &afe->sub_dais);
dai->dai_drivers = mtk_dai_pcm_driver;
dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_pcm_driver);
dai->dapm_widgets = mtk_dai_pcm_widgets;
dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_pcm_widgets);
dai->dapm_routes = mtk_dai_pcm_routes;
dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_pcm_routes);
return init_pcmif_priv_data(afe);
}
| linux-master | sound/soc/mediatek/mt8188/mt8188-dai-pcm.c |
// SPDX-License-Identifier: GPL-2.0
/*
* mtk-afe-platform-driver.c -- Mediatek afe platform driver
*
* Copyright (c) 2016 MediaTek Inc.
* Author: Garlic Tseng <[email protected]>
*/
#include <linux/module.h>
#include <linux/dma-mapping.h>
#include <sound/soc.h>
#include "mtk-afe-platform-driver.h"
#include "mtk-base-afe.h"
int mtk_afe_combine_sub_dai(struct mtk_base_afe *afe)
{
struct mtk_base_afe_dai *dai;
size_t num_dai_drivers = 0, dai_idx = 0;
/* calcualte total dai driver size */
list_for_each_entry(dai, &afe->sub_dais, list) {
num_dai_drivers += dai->num_dai_drivers;
}
dev_info(afe->dev, "%s(), num of dai %zd\n", __func__, num_dai_drivers);
/* combine sub_dais */
afe->num_dai_drivers = num_dai_drivers;
afe->dai_drivers = devm_kcalloc(afe->dev,
num_dai_drivers,
sizeof(struct snd_soc_dai_driver),
GFP_KERNEL);
if (!afe->dai_drivers)
return -ENOMEM;
list_for_each_entry(dai, &afe->sub_dais, list) {
/* dai driver */
memcpy(&afe->dai_drivers[dai_idx],
dai->dai_drivers,
dai->num_dai_drivers *
sizeof(struct snd_soc_dai_driver));
dai_idx += dai->num_dai_drivers;
}
return 0;
}
EXPORT_SYMBOL_GPL(mtk_afe_combine_sub_dai);
int mtk_afe_add_sub_dai_control(struct snd_soc_component *component)
{
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
struct mtk_base_afe_dai *dai;
list_for_each_entry(dai, &afe->sub_dais, list) {
if (dai->controls)
snd_soc_add_component_controls(component,
dai->controls,
dai->num_controls);
if (dai->dapm_widgets)
snd_soc_dapm_new_controls(&component->dapm,
dai->dapm_widgets,
dai->num_dapm_widgets);
}
/* add routes after all widgets are added */
list_for_each_entry(dai, &afe->sub_dais, list) {
if (dai->dapm_routes)
snd_soc_dapm_add_routes(&component->dapm,
dai->dapm_routes,
dai->num_dapm_routes);
}
snd_soc_dapm_new_widgets(component->dapm.card);
return 0;
}
EXPORT_SYMBOL_GPL(mtk_afe_add_sub_dai_control);
snd_pcm_uframes_t mtk_afe_pcm_pointer(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
struct mtk_base_afe_memif *memif = &afe->memif[asoc_rtd_to_cpu(rtd, 0)->id];
const struct mtk_base_memif_data *memif_data = memif->data;
struct regmap *regmap = afe->regmap;
struct device *dev = afe->dev;
int reg_ofs_base = memif_data->reg_ofs_base;
int reg_ofs_cur = memif_data->reg_ofs_cur;
unsigned int hw_ptr = 0, hw_base = 0;
int ret, pcm_ptr_bytes;
ret = regmap_read(regmap, reg_ofs_cur, &hw_ptr);
if (ret || hw_ptr == 0) {
dev_err(dev, "%s hw_ptr err\n", __func__);
pcm_ptr_bytes = 0;
goto POINTER_RETURN_FRAMES;
}
ret = regmap_read(regmap, reg_ofs_base, &hw_base);
if (ret || hw_base == 0) {
dev_err(dev, "%s hw_ptr err\n", __func__);
pcm_ptr_bytes = 0;
goto POINTER_RETURN_FRAMES;
}
pcm_ptr_bytes = hw_ptr - hw_base;
POINTER_RETURN_FRAMES:
return bytes_to_frames(substream->runtime, pcm_ptr_bytes);
}
EXPORT_SYMBOL_GPL(mtk_afe_pcm_pointer);
int mtk_afe_pcm_new(struct snd_soc_component *component,
struct snd_soc_pcm_runtime *rtd)
{
size_t size;
struct snd_pcm *pcm = rtd->pcm;
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
size = afe->mtk_afe_hardware->buffer_bytes_max;
snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
afe->dev, size, size);
return 0;
}
EXPORT_SYMBOL_GPL(mtk_afe_pcm_new);
const struct snd_soc_component_driver mtk_afe_pcm_platform = {
.name = AFE_PCM_NAME,
.pointer = mtk_afe_pcm_pointer,
.pcm_construct = mtk_afe_pcm_new,
};
EXPORT_SYMBOL_GPL(mtk_afe_pcm_platform);
MODULE_DESCRIPTION("Mediatek simple platform driver");
MODULE_AUTHOR("Garlic Tseng <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/mediatek/common/mtk-afe-platform-driver.c |
// SPDX-License-Identifier: GPL-2.0
/*
* mtk-afe-fe-dais.c -- Mediatek afe fe dai operator
*
* Copyright (c) 2016 MediaTek Inc.
* Author: Garlic Tseng <[email protected]>
*/
#include <linux/io.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include "mtk-afe-platform-driver.h"
#include <sound/pcm_params.h>
#include "mtk-afe-fe-dai.h"
#include "mtk-base-afe.h"
#define AFE_BASE_END_OFFSET 8
static int mtk_regmap_update_bits(struct regmap *map, int reg,
unsigned int mask,
unsigned int val, int shift)
{
if (reg < 0 || WARN_ON_ONCE(shift < 0))
return 0;
return regmap_update_bits(map, reg, mask << shift, val << shift);
}
static int mtk_regmap_write(struct regmap *map, int reg, unsigned int val)
{
if (reg < 0)
return 0;
return regmap_write(map, reg, val);
}
int mtk_afe_fe_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct snd_pcm_runtime *runtime = substream->runtime;
int memif_num = asoc_rtd_to_cpu(rtd, 0)->id;
struct mtk_base_afe_memif *memif = &afe->memif[memif_num];
const struct snd_pcm_hardware *mtk_afe_hardware = afe->mtk_afe_hardware;
int ret;
memif->substream = substream;
snd_pcm_hw_constraint_step(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 16);
/* enable agent */
mtk_regmap_update_bits(afe->regmap, memif->data->agent_disable_reg,
1, 0, memif->data->agent_disable_shift);
snd_soc_set_runtime_hwparams(substream, mtk_afe_hardware);
/*
* Capture cannot use ping-pong buffer since hw_ptr at IRQ may be
* smaller than period_size due to AFE's internal buffer.
* This easily leads to overrun when avail_min is period_size.
* One more period can hold the possible unread buffer.
*/
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
int periods_max = mtk_afe_hardware->periods_max;
ret = snd_pcm_hw_constraint_minmax(runtime,
SNDRV_PCM_HW_PARAM_PERIODS,
3, periods_max);
if (ret < 0) {
dev_err(afe->dev, "hw_constraint_minmax failed\n");
return ret;
}
}
ret = snd_pcm_hw_constraint_integer(runtime,
SNDRV_PCM_HW_PARAM_PERIODS);
if (ret < 0)
dev_err(afe->dev, "snd_pcm_hw_constraint_integer failed\n");
/* dynamic allocate irq to memif */
if (memif->irq_usage < 0) {
int irq_id = mtk_dynamic_irq_acquire(afe);
if (irq_id != afe->irqs_size) {
/* link */
memif->irq_usage = irq_id;
} else {
dev_err(afe->dev, "%s() error: no more asys irq\n",
__func__);
ret = -EBUSY;
}
}
return ret;
}
EXPORT_SYMBOL_GPL(mtk_afe_fe_startup);
void mtk_afe_fe_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mtk_base_afe_memif *memif = &afe->memif[asoc_rtd_to_cpu(rtd, 0)->id];
int irq_id;
irq_id = memif->irq_usage;
mtk_regmap_update_bits(afe->regmap, memif->data->agent_disable_reg,
1, 1, memif->data->agent_disable_shift);
if (!memif->const_irq) {
mtk_dynamic_irq_release(afe, irq_id);
memif->irq_usage = -1;
memif->substream = NULL;
}
}
EXPORT_SYMBOL_GPL(mtk_afe_fe_shutdown);
int mtk_afe_fe_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
int id = asoc_rtd_to_cpu(rtd, 0)->id;
struct mtk_base_afe_memif *memif = &afe->memif[id];
int ret;
unsigned int channels = params_channels(params);
unsigned int rate = params_rate(params);
snd_pcm_format_t format = params_format(params);
if (afe->request_dram_resource)
afe->request_dram_resource(afe->dev);
dev_dbg(afe->dev, "%s(), %s, ch %d, rate %d, fmt %d, dma_addr %pad, dma_area %p, dma_bytes 0x%zx\n",
__func__, memif->data->name,
channels, rate, format,
&substream->runtime->dma_addr,
substream->runtime->dma_area,
substream->runtime->dma_bytes);
memset_io((void __force __iomem *)substream->runtime->dma_area, 0,
substream->runtime->dma_bytes);
/* set addr */
ret = mtk_memif_set_addr(afe, id,
substream->runtime->dma_area,
substream->runtime->dma_addr,
substream->runtime->dma_bytes);
if (ret) {
dev_err(afe->dev, "%s(), error, id %d, set addr, ret %d\n",
__func__, id, ret);
return ret;
}
/* set channel */
ret = mtk_memif_set_channel(afe, id, channels);
if (ret) {
dev_err(afe->dev, "%s(), error, id %d, set channel %d, ret %d\n",
__func__, id, channels, ret);
return ret;
}
/* set rate */
ret = mtk_memif_set_rate_substream(substream, id, rate);
if (ret) {
dev_err(afe->dev, "%s(), error, id %d, set rate %d, ret %d\n",
__func__, id, rate, ret);
return ret;
}
/* set format */
ret = mtk_memif_set_format(afe, id, format);
if (ret) {
dev_err(afe->dev, "%s(), error, id %d, set format %d, ret %d\n",
__func__, id, format, ret);
return ret;
}
return 0;
}
EXPORT_SYMBOL_GPL(mtk_afe_fe_hw_params);
int mtk_afe_fe_hw_free(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
if (afe->release_dram_resource)
afe->release_dram_resource(afe->dev);
return 0;
}
EXPORT_SYMBOL_GPL(mtk_afe_fe_hw_free);
int mtk_afe_fe_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_pcm_runtime * const runtime = substream->runtime;
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
int id = asoc_rtd_to_cpu(rtd, 0)->id;
struct mtk_base_afe_memif *memif = &afe->memif[id];
struct mtk_base_afe_irq *irqs = &afe->irqs[memif->irq_usage];
const struct mtk_base_irq_data *irq_data = irqs->irq_data;
unsigned int counter = runtime->period_size;
int fs;
int ret;
dev_dbg(afe->dev, "%s %s cmd=%d\n", __func__, memif->data->name, cmd);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
ret = mtk_memif_set_enable(afe, id);
if (ret) {
dev_err(afe->dev, "%s(), error, id %d, memif enable, ret %d\n",
__func__, id, ret);
return ret;
}
/* set irq counter */
mtk_regmap_update_bits(afe->regmap, irq_data->irq_cnt_reg,
irq_data->irq_cnt_maskbit, counter,
irq_data->irq_cnt_shift);
/* set irq fs */
fs = afe->irq_fs(substream, runtime->rate);
if (fs < 0)
return -EINVAL;
mtk_regmap_update_bits(afe->regmap, irq_data->irq_fs_reg,
irq_data->irq_fs_maskbit, fs,
irq_data->irq_fs_shift);
/* enable interrupt */
mtk_regmap_update_bits(afe->regmap, irq_data->irq_en_reg,
1, 1, irq_data->irq_en_shift);
return 0;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
ret = mtk_memif_set_disable(afe, id);
if (ret) {
dev_err(afe->dev, "%s(), error, id %d, memif enable, ret %d\n",
__func__, id, ret);
}
/* disable interrupt */
mtk_regmap_update_bits(afe->regmap, irq_data->irq_en_reg,
1, 0, irq_data->irq_en_shift);
/* and clear pending IRQ */
mtk_regmap_write(afe->regmap, irq_data->irq_clr_reg,
1 << irq_data->irq_clr_shift);
return ret;
default:
return -EINVAL;
}
}
EXPORT_SYMBOL_GPL(mtk_afe_fe_trigger);
int mtk_afe_fe_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
int id = asoc_rtd_to_cpu(rtd, 0)->id;
int pbuf_size;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
if (afe->get_memif_pbuf_size) {
pbuf_size = afe->get_memif_pbuf_size(substream);
mtk_memif_set_pbuf_size(afe, id, pbuf_size);
}
}
return 0;
}
EXPORT_SYMBOL_GPL(mtk_afe_fe_prepare);
const struct snd_soc_dai_ops mtk_afe_fe_ops = {
.startup = mtk_afe_fe_startup,
.shutdown = mtk_afe_fe_shutdown,
.hw_params = mtk_afe_fe_hw_params,
.hw_free = mtk_afe_fe_hw_free,
.prepare = mtk_afe_fe_prepare,
.trigger = mtk_afe_fe_trigger,
};
EXPORT_SYMBOL_GPL(mtk_afe_fe_ops);
int mtk_dynamic_irq_acquire(struct mtk_base_afe *afe)
{
int i;
mutex_lock(&afe->irq_alloc_lock);
for (i = 0; i < afe->irqs_size; ++i) {
if (afe->irqs[i].irq_occupyed == 0) {
afe->irqs[i].irq_occupyed = 1;
mutex_unlock(&afe->irq_alloc_lock);
return i;
}
}
mutex_unlock(&afe->irq_alloc_lock);
return afe->irqs_size;
}
EXPORT_SYMBOL_GPL(mtk_dynamic_irq_acquire);
int mtk_dynamic_irq_release(struct mtk_base_afe *afe, int irq_id)
{
mutex_lock(&afe->irq_alloc_lock);
if (irq_id >= 0 && irq_id < afe->irqs_size) {
afe->irqs[irq_id].irq_occupyed = 0;
mutex_unlock(&afe->irq_alloc_lock);
return 0;
}
mutex_unlock(&afe->irq_alloc_lock);
return -EINVAL;
}
EXPORT_SYMBOL_GPL(mtk_dynamic_irq_release);
int mtk_afe_suspend(struct snd_soc_component *component)
{
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
struct device *dev = afe->dev;
struct regmap *regmap = afe->regmap;
int i;
if (pm_runtime_status_suspended(dev) || afe->suspended)
return 0;
if (!afe->reg_back_up)
afe->reg_back_up =
devm_kcalloc(dev, afe->reg_back_up_list_num,
sizeof(unsigned int), GFP_KERNEL);
if (afe->reg_back_up) {
for (i = 0; i < afe->reg_back_up_list_num; i++)
regmap_read(regmap, afe->reg_back_up_list[i],
&afe->reg_back_up[i]);
}
afe->suspended = true;
afe->runtime_suspend(dev);
return 0;
}
EXPORT_SYMBOL_GPL(mtk_afe_suspend);
int mtk_afe_resume(struct snd_soc_component *component)
{
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
struct device *dev = afe->dev;
struct regmap *regmap = afe->regmap;
int i;
if (pm_runtime_status_suspended(dev) || !afe->suspended)
return 0;
afe->runtime_resume(dev);
if (!afe->reg_back_up) {
dev_dbg(dev, "%s no reg_backup\n", __func__);
} else {
for (i = 0; i < afe->reg_back_up_list_num; i++)
mtk_regmap_write(regmap, afe->reg_back_up_list[i],
afe->reg_back_up[i]);
}
afe->suspended = false;
return 0;
}
EXPORT_SYMBOL_GPL(mtk_afe_resume);
int mtk_memif_set_enable(struct mtk_base_afe *afe, int id)
{
struct mtk_base_afe_memif *memif = &afe->memif[id];
if (memif->data->enable_shift < 0) {
dev_warn(afe->dev, "%s(), error, id %d, enable_shift < 0\n",
__func__, id);
return 0;
}
return mtk_regmap_update_bits(afe->regmap, memif->data->enable_reg,
1, 1, memif->data->enable_shift);
}
EXPORT_SYMBOL_GPL(mtk_memif_set_enable);
int mtk_memif_set_disable(struct mtk_base_afe *afe, int id)
{
struct mtk_base_afe_memif *memif = &afe->memif[id];
if (memif->data->enable_shift < 0) {
dev_warn(afe->dev, "%s(), error, id %d, enable_shift < 0\n",
__func__, id);
return 0;
}
return mtk_regmap_update_bits(afe->regmap, memif->data->enable_reg,
1, 0, memif->data->enable_shift);
}
EXPORT_SYMBOL_GPL(mtk_memif_set_disable);
int mtk_memif_set_addr(struct mtk_base_afe *afe, int id,
unsigned char *dma_area,
dma_addr_t dma_addr,
size_t dma_bytes)
{
struct mtk_base_afe_memif *memif = &afe->memif[id];
int msb_at_bit33 = upper_32_bits(dma_addr) ? 1 : 0;
unsigned int phys_buf_addr = lower_32_bits(dma_addr);
unsigned int phys_buf_addr_upper_32 = upper_32_bits(dma_addr);
memif->dma_area = dma_area;
memif->dma_addr = dma_addr;
memif->dma_bytes = dma_bytes;
/* start */
mtk_regmap_write(afe->regmap, memif->data->reg_ofs_base,
phys_buf_addr);
/* end */
if (memif->data->reg_ofs_end)
mtk_regmap_write(afe->regmap,
memif->data->reg_ofs_end,
phys_buf_addr + dma_bytes - 1);
else
mtk_regmap_write(afe->regmap,
memif->data->reg_ofs_base +
AFE_BASE_END_OFFSET,
phys_buf_addr + dma_bytes - 1);
/* set start, end, upper 32 bits */
if (memif->data->reg_ofs_base_msb) {
mtk_regmap_write(afe->regmap, memif->data->reg_ofs_base_msb,
phys_buf_addr_upper_32);
mtk_regmap_write(afe->regmap,
memif->data->reg_ofs_end_msb,
phys_buf_addr_upper_32);
}
/*
* set MSB to 33-bit, for memif address
* only for memif base address, if msb_end_reg exists
*/
if (memif->data->msb_reg)
mtk_regmap_update_bits(afe->regmap, memif->data->msb_reg,
1, msb_at_bit33, memif->data->msb_shift);
/* set MSB to 33-bit, for memif end address */
if (memif->data->msb_end_reg)
mtk_regmap_update_bits(afe->regmap, memif->data->msb_end_reg,
1, msb_at_bit33,
memif->data->msb_end_shift);
return 0;
}
EXPORT_SYMBOL_GPL(mtk_memif_set_addr);
int mtk_memif_set_channel(struct mtk_base_afe *afe,
int id, unsigned int channel)
{
struct mtk_base_afe_memif *memif = &afe->memif[id];
unsigned int mono;
if (memif->data->mono_shift < 0)
return 0;
if (memif->data->quad_ch_mask) {
unsigned int quad_ch = (channel == 4) ? 1 : 0;
mtk_regmap_update_bits(afe->regmap, memif->data->quad_ch_reg,
memif->data->quad_ch_mask,
quad_ch, memif->data->quad_ch_shift);
}
if (memif->data->mono_invert)
mono = (channel == 1) ? 0 : 1;
else
mono = (channel == 1) ? 1 : 0;
/* for specific configuration of memif mono mode */
if (memif->data->int_odd_flag_reg)
mtk_regmap_update_bits(afe->regmap,
memif->data->int_odd_flag_reg,
1, mono,
memif->data->int_odd_flag_shift);
return mtk_regmap_update_bits(afe->regmap, memif->data->mono_reg,
1, mono, memif->data->mono_shift);
}
EXPORT_SYMBOL_GPL(mtk_memif_set_channel);
static int mtk_memif_set_rate_fs(struct mtk_base_afe *afe,
int id, int fs)
{
struct mtk_base_afe_memif *memif = &afe->memif[id];
if (memif->data->fs_shift >= 0)
mtk_regmap_update_bits(afe->regmap, memif->data->fs_reg,
memif->data->fs_maskbit,
fs, memif->data->fs_shift);
return 0;
}
int mtk_memif_set_rate(struct mtk_base_afe *afe,
int id, unsigned int rate)
{
int fs = 0;
if (!afe->get_dai_fs) {
dev_err(afe->dev, "%s(), error, afe->get_dai_fs == NULL\n",
__func__);
return -EINVAL;
}
fs = afe->get_dai_fs(afe, id, rate);
if (fs < 0)
return -EINVAL;
return mtk_memif_set_rate_fs(afe, id, fs);
}
EXPORT_SYMBOL_GPL(mtk_memif_set_rate);
int mtk_memif_set_rate_substream(struct snd_pcm_substream *substream,
int id, unsigned int rate)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_component *component =
snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
int fs = 0;
if (!afe->memif_fs) {
dev_err(afe->dev, "%s(), error, afe->memif_fs == NULL\n",
__func__);
return -EINVAL;
}
fs = afe->memif_fs(substream, rate);
if (fs < 0)
return -EINVAL;
return mtk_memif_set_rate_fs(afe, id, fs);
}
EXPORT_SYMBOL_GPL(mtk_memif_set_rate_substream);
int mtk_memif_set_format(struct mtk_base_afe *afe,
int id, snd_pcm_format_t format)
{
struct mtk_base_afe_memif *memif = &afe->memif[id];
int hd_audio = 0;
int hd_align = 0;
/* set hd mode */
switch (format) {
case SNDRV_PCM_FORMAT_S16_LE:
case SNDRV_PCM_FORMAT_U16_LE:
hd_audio = 0;
break;
case SNDRV_PCM_FORMAT_S32_LE:
case SNDRV_PCM_FORMAT_U32_LE:
if (afe->memif_32bit_supported) {
hd_audio = 2;
hd_align = 0;
} else {
hd_audio = 1;
hd_align = 1;
}
break;
case SNDRV_PCM_FORMAT_S24_LE:
case SNDRV_PCM_FORMAT_U24_LE:
hd_audio = 1;
break;
default:
dev_err(afe->dev, "%s() error: unsupported format %d\n",
__func__, format);
break;
}
mtk_regmap_update_bits(afe->regmap, memif->data->hd_reg,
0x3, hd_audio, memif->data->hd_shift);
mtk_regmap_update_bits(afe->regmap, memif->data->hd_align_reg,
0x1, hd_align, memif->data->hd_align_mshift);
return 0;
}
EXPORT_SYMBOL_GPL(mtk_memif_set_format);
int mtk_memif_set_pbuf_size(struct mtk_base_afe *afe,
int id, int pbuf_size)
{
const struct mtk_base_memif_data *memif_data = afe->memif[id].data;
if (memif_data->pbuf_mask == 0 || memif_data->minlen_mask == 0)
return 0;
mtk_regmap_update_bits(afe->regmap, memif_data->pbuf_reg,
memif_data->pbuf_mask,
pbuf_size, memif_data->pbuf_shift);
mtk_regmap_update_bits(afe->regmap, memif_data->minlen_reg,
memif_data->minlen_mask,
pbuf_size, memif_data->minlen_shift);
return 0;
}
EXPORT_SYMBOL_GPL(mtk_memif_set_pbuf_size);
MODULE_DESCRIPTION("Mediatek simple fe dai operator");
MODULE_AUTHOR("Garlic Tseng <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/mediatek/common/mtk-afe-fe-dai.c |
// SPDX-License-Identifier: GPL-2.0
/*
* mtk-dsp-sof-common.c -- MediaTek dsp sof common ctrl
*
* Copyright (c) 2022 MediaTek Inc.
* Author: Chunxu Li <[email protected]>
*/
#include "mtk-dsp-sof-common.h"
#include "mtk-soc-card.h"
/* fixup the BE DAI link to match any values from topology */
int mtk_sof_dai_link_fixup(struct snd_soc_pcm_runtime *rtd,
struct snd_pcm_hw_params *params)
{
struct snd_soc_card *card = rtd->card;
struct mtk_soc_card_data *soc_card_data = snd_soc_card_get_drvdata(card);
struct mtk_sof_priv *sof_priv = soc_card_data->sof_priv;
int i, j, ret = 0;
for (i = 0; i < sof_priv->num_streams; i++) {
struct snd_soc_dai *cpu_dai;
struct snd_soc_pcm_runtime *runtime;
struct snd_soc_dai_link *sof_dai_link = NULL;
const struct sof_conn_stream *conn = &sof_priv->conn_streams[i];
if (strcmp(rtd->dai_link->name, conn->normal_link))
continue;
for_each_card_rtds(card, runtime) {
if (strcmp(runtime->dai_link->name, conn->sof_link))
continue;
for_each_rtd_cpu_dais(runtime, j, cpu_dai) {
if (snd_soc_dai_stream_active(cpu_dai, conn->stream_dir) > 0) {
sof_dai_link = runtime->dai_link;
break;
}
}
break;
}
if (sof_dai_link && sof_dai_link->be_hw_params_fixup)
ret = sof_dai_link->be_hw_params_fixup(runtime, params);
break;
}
return ret;
}
EXPORT_SYMBOL_GPL(mtk_sof_dai_link_fixup);
int mtk_sof_card_probe(struct snd_soc_card *card)
{
int i;
struct snd_soc_dai_link *dai_link;
/* Set stream_name to help sof bind widgets */
for_each_card_prelinks(card, i, dai_link) {
if (dai_link->no_pcm && !dai_link->stream_name && dai_link->name)
dai_link->stream_name = dai_link->name;
}
return 0;
}
EXPORT_SYMBOL_GPL(mtk_sof_card_probe);
int mtk_sof_card_late_probe(struct snd_soc_card *card)
{
struct snd_soc_pcm_runtime *rtd;
struct snd_soc_component *sof_comp = NULL;
struct mtk_soc_card_data *soc_card_data =
snd_soc_card_get_drvdata(card);
struct mtk_sof_priv *sof_priv = soc_card_data->sof_priv;
int i;
/* 1. find sof component */
for_each_card_rtds(card, rtd) {
sof_comp = snd_soc_rtdcom_lookup(rtd, "sof-audio-component");
if (sof_comp)
break;
}
if (!sof_comp) {
dev_info(card->dev, "probe without sof-audio-component\n");
return 0;
}
/* 2. add route path and fixup callback */
for (i = 0; i < sof_priv->num_streams; i++) {
const struct sof_conn_stream *conn = &sof_priv->conn_streams[i];
struct snd_soc_pcm_runtime *sof_rtd = NULL;
struct snd_soc_pcm_runtime *normal_rtd = NULL;
for_each_card_rtds(card, rtd) {
if (!strcmp(rtd->dai_link->name, conn->sof_link)) {
sof_rtd = rtd;
continue;
}
if (!strcmp(rtd->dai_link->name, conn->normal_link)) {
normal_rtd = rtd;
continue;
}
if (normal_rtd && sof_rtd)
break;
}
if (normal_rtd && sof_rtd) {
int j;
struct snd_soc_dai *cpu_dai;
for_each_rtd_cpu_dais(sof_rtd, j, cpu_dai) {
struct snd_soc_dapm_route route;
struct snd_soc_dapm_path *p = NULL;
struct snd_soc_dapm_widget *widget = snd_soc_dai_get_widget(cpu_dai, conn->stream_dir);
memset(&route, 0, sizeof(route));
if (conn->stream_dir == SNDRV_PCM_STREAM_CAPTURE && widget) {
snd_soc_dapm_widget_for_each_sink_path(widget, p) {
route.source = conn->sof_dma;
route.sink = p->sink->name;
snd_soc_dapm_add_routes(&card->dapm, &route, 1);
}
} else if (conn->stream_dir == SNDRV_PCM_STREAM_PLAYBACK && widget) {
snd_soc_dapm_widget_for_each_source_path(widget, p) {
route.source = p->source->name;
route.sink = conn->sof_dma;
snd_soc_dapm_add_routes(&card->dapm, &route, 1);
}
} else {
dev_err(cpu_dai->dev, "stream dir and widget not pair\n");
}
}
sof_rtd->dai_link->be_hw_params_fixup =
sof_comp->driver->be_hw_params_fixup;
if (sof_priv->sof_dai_link_fixup)
normal_rtd->dai_link->be_hw_params_fixup =
sof_priv->sof_dai_link_fixup;
else
normal_rtd->dai_link->be_hw_params_fixup = mtk_sof_dai_link_fixup;
}
}
return 0;
}
EXPORT_SYMBOL_GPL(mtk_sof_card_late_probe);
int mtk_sof_dailink_parse_of(struct snd_soc_card *card, struct device_node *np,
const char *propname, struct snd_soc_dai_link *pre_dai_links,
int pre_num_links)
{
struct device *dev = card->dev;
struct snd_soc_dai_link *parsed_dai_link;
const char *dai_name = NULL;
int i, j, ret, num_links, parsed_num_links = 0;
num_links = of_property_count_strings(np, "mediatek,dai-link");
if (num_links < 0 || num_links > card->num_links) {
dev_dbg(dev, "number of dai-link is invalid\n");
return -EINVAL;
}
parsed_dai_link = devm_kcalloc(dev, num_links, sizeof(*parsed_dai_link), GFP_KERNEL);
if (!parsed_dai_link)
return -ENOMEM;
for (i = 0; i < num_links; i++) {
ret = of_property_read_string_index(np, propname, i, &dai_name);
if (ret) {
dev_dbg(dev, "ASoC: Property '%s' index %d could not be read: %d\n",
propname, i, ret);
return ret;
}
dev_dbg(dev, "ASoC: Property get dai_name:%s\n", dai_name);
for (j = 0; j < pre_num_links; j++) {
if (!strcmp(dai_name, pre_dai_links[j].name)) {
memcpy(&parsed_dai_link[parsed_num_links++], &pre_dai_links[j],
sizeof(struct snd_soc_dai_link));
break;
}
}
}
if (parsed_num_links != num_links)
return -EINVAL;
card->dai_link = parsed_dai_link;
card->num_links = parsed_num_links;
return 0;
}
EXPORT_SYMBOL_GPL(mtk_sof_dailink_parse_of);
| linux-master | sound/soc/mediatek/common/mtk-dsp-sof-common.c |
// SPDX-License-Identifier: GPL-2.0
//
// Mediatek ALSA BT SCO CVSD/MSBC Driver
//
// Copyright (c) 2019 MediaTek Inc.
// Author: KaiChieh Chuang <[email protected]>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/sched/clock.h>
#include <sound/soc.h>
#define BTCVSD_SND_NAME "mtk-btcvsd-snd"
#define BT_CVSD_TX_NREADY BIT(21)
#define BT_CVSD_RX_READY BIT(22)
#define BT_CVSD_TX_UNDERFLOW BIT(23)
#define BT_CVSD_RX_OVERFLOW BIT(24)
#define BT_CVSD_INTERRUPT BIT(31)
#define BT_CVSD_CLEAR \
(BT_CVSD_TX_NREADY | BT_CVSD_RX_READY | BT_CVSD_TX_UNDERFLOW |\
BT_CVSD_RX_OVERFLOW | BT_CVSD_INTERRUPT)
/* TX */
#define SCO_TX_ENCODE_SIZE (60)
/* 18 = 6 * 180 / SCO_TX_ENCODE_SIZE */
#define SCO_TX_PACKER_BUF_NUM (18)
/* RX */
#define SCO_RX_PLC_SIZE (30)
#define SCO_RX_PACKER_BUF_NUM (64)
#define SCO_RX_PACKET_MASK (0x3F)
#define SCO_CVSD_PACKET_VALID_SIZE 2
#define SCO_PACKET_120 120
#define SCO_PACKET_180 180
#define BTCVSD_RX_PACKET_SIZE (SCO_RX_PLC_SIZE + SCO_CVSD_PACKET_VALID_SIZE)
#define BTCVSD_TX_PACKET_SIZE (SCO_TX_ENCODE_SIZE)
#define BTCVSD_RX_BUF_SIZE (BTCVSD_RX_PACKET_SIZE * SCO_RX_PACKER_BUF_NUM)
#define BTCVSD_TX_BUF_SIZE (BTCVSD_TX_PACKET_SIZE * SCO_TX_PACKER_BUF_NUM)
enum bt_sco_state {
BT_SCO_STATE_IDLE,
BT_SCO_STATE_RUNNING,
BT_SCO_STATE_ENDING,
BT_SCO_STATE_LOOPBACK,
};
enum bt_sco_direct {
BT_SCO_DIRECT_BT2ARM,
BT_SCO_DIRECT_ARM2BT,
};
enum bt_sco_packet_len {
BT_SCO_CVSD_30 = 0,
BT_SCO_CVSD_60,
BT_SCO_CVSD_90,
BT_SCO_CVSD_120,
BT_SCO_CVSD_10,
BT_SCO_CVSD_20,
BT_SCO_CVSD_MAX,
};
enum BT_SCO_BAND {
BT_SCO_NB,
BT_SCO_WB,
};
struct mtk_btcvsd_snd_hw_info {
unsigned int num_valid_addr;
unsigned long bt_sram_addr[20];
unsigned int packet_length;
unsigned int packet_num;
};
struct mtk_btcvsd_snd_stream {
struct snd_pcm_substream *substream;
int stream;
enum bt_sco_state state;
unsigned int packet_size;
unsigned int buf_size;
u8 temp_packet_buf[SCO_PACKET_180];
int packet_w;
int packet_r;
snd_pcm_uframes_t prev_frame;
int prev_packet_idx;
unsigned int xrun:1;
unsigned int timeout:1;
unsigned int mute:1;
unsigned int trigger_start:1;
unsigned int wait_flag:1;
unsigned int rw_cnt;
unsigned long long time_stamp;
unsigned long long buf_data_equivalent_time;
struct mtk_btcvsd_snd_hw_info buffer_info;
};
struct mtk_btcvsd_snd {
struct device *dev;
int irq_id;
struct regmap *infra;
void __iomem *bt_pkv_base;
void __iomem *bt_sram_bank2_base;
unsigned int infra_misc_offset;
unsigned int conn_bt_cvsd_mask;
unsigned int cvsd_mcu_read_offset;
unsigned int cvsd_mcu_write_offset;
unsigned int cvsd_packet_indicator;
u32 *bt_reg_pkt_r;
u32 *bt_reg_pkt_w;
u32 *bt_reg_ctl;
unsigned int irq_disabled:1;
spinlock_t tx_lock; /* spinlock for bt tx stream control */
spinlock_t rx_lock; /* spinlock for bt rx stream control */
wait_queue_head_t tx_wait;
wait_queue_head_t rx_wait;
struct mtk_btcvsd_snd_stream *tx;
struct mtk_btcvsd_snd_stream *rx;
u8 tx_packet_buf[BTCVSD_TX_BUF_SIZE];
u8 rx_packet_buf[BTCVSD_RX_BUF_SIZE];
enum BT_SCO_BAND band;
};
struct mtk_btcvsd_snd_time_buffer_info {
unsigned long long data_count_equi_time;
unsigned long long time_stamp_us;
};
static const unsigned int btsco_packet_valid_mask[BT_SCO_CVSD_MAX][6] = {
{0x1, 0x1 << 1, 0x1 << 2, 0x1 << 3, 0x1 << 4, 0x1 << 5},
{0x1, 0x1, 0x2, 0x2, 0x4, 0x4},
{0x1, 0x1, 0x1, 0x2, 0x2, 0x2},
{0x1, 0x1, 0x1, 0x1, 0x0, 0x0},
{0x7, 0x7 << 3, 0x7 << 6, 0x7 << 9, 0x7 << 12, 0x7 << 15},
{0x3, 0x3 << 1, 0x3 << 3, 0x3 << 4, 0x3 << 6, 0x3 << 7},
};
static const unsigned int btsco_packet_info[BT_SCO_CVSD_MAX][4] = {
{30, 6, SCO_PACKET_180 / SCO_TX_ENCODE_SIZE,
SCO_PACKET_180 / SCO_RX_PLC_SIZE},
{60, 3, SCO_PACKET_180 / SCO_TX_ENCODE_SIZE,
SCO_PACKET_180 / SCO_RX_PLC_SIZE},
{90, 2, SCO_PACKET_180 / SCO_TX_ENCODE_SIZE,
SCO_PACKET_180 / SCO_RX_PLC_SIZE},
{120, 1, SCO_PACKET_120 / SCO_TX_ENCODE_SIZE,
SCO_PACKET_120 / SCO_RX_PLC_SIZE},
{10, 18, SCO_PACKET_180 / SCO_TX_ENCODE_SIZE,
SCO_PACKET_180 / SCO_RX_PLC_SIZE},
{20, 9, SCO_PACKET_180 / SCO_TX_ENCODE_SIZE,
SCO_PACKET_180 / SCO_RX_PLC_SIZE},
};
static const u8 table_msbc_silence[SCO_PACKET_180] = {
0x01, 0x38, 0xad, 0x00, 0x00, 0xc5, 0x00, 0x00, 0x00, 0x00,
0x77, 0x6d, 0xb6, 0xdd, 0xdb, 0x6d, 0xb7, 0x76, 0xdb, 0x6d,
0xdd, 0xb6, 0xdb, 0x77, 0x6d, 0xb6, 0xdd, 0xdb, 0x6d, 0xb7,
0x76, 0xdb, 0x6d, 0xdd, 0xb6, 0xdb, 0x77, 0x6d, 0xb6, 0xdd,
0xdb, 0x6d, 0xb7, 0x76, 0xdb, 0x6d, 0xdd, 0xb6, 0xdb, 0x77,
0x6d, 0xb6, 0xdd, 0xdb, 0x6d, 0xb7, 0x76, 0xdb, 0x6c, 0x00,
0x01, 0xc8, 0xad, 0x00, 0x00, 0xc5, 0x00, 0x00, 0x00, 0x00,
0x77, 0x6d, 0xb6, 0xdd, 0xdb, 0x6d, 0xb7, 0x76, 0xdb, 0x6d,
0xdd, 0xb6, 0xdb, 0x77, 0x6d, 0xb6, 0xdd, 0xdb, 0x6d, 0xb7,
0x76, 0xdb, 0x6d, 0xdd, 0xb6, 0xdb, 0x77, 0x6d, 0xb6, 0xdd,
0xdb, 0x6d, 0xb7, 0x76, 0xdb, 0x6d, 0xdd, 0xb6, 0xdb, 0x77,
0x6d, 0xb6, 0xdd, 0xdb, 0x6d, 0xb7, 0x76, 0xdb, 0x6c, 0x00,
0x01, 0xf8, 0xad, 0x00, 0x00, 0xc5, 0x00, 0x00, 0x00, 0x00,
0x77, 0x6d, 0xb6, 0xdd, 0xdb, 0x6d, 0xb7, 0x76, 0xdb, 0x6d,
0xdd, 0xb6, 0xdb, 0x77, 0x6d, 0xb6, 0xdd, 0xdb, 0x6d, 0xb7,
0x76, 0xdb, 0x6d, 0xdd, 0xb6, 0xdb, 0x77, 0x6d, 0xb6, 0xdd,
0xdb, 0x6d, 0xb7, 0x76, 0xdb, 0x6d, 0xdd, 0xb6, 0xdb, 0x77,
0x6d, 0xb6, 0xdd, 0xdb, 0x6d, 0xb7, 0x76, 0xdb, 0x6c, 0x00
};
static void mtk_btcvsd_snd_irq_enable(struct mtk_btcvsd_snd *bt)
{
regmap_update_bits(bt->infra, bt->infra_misc_offset,
bt->conn_bt_cvsd_mask, 0);
}
static void mtk_btcvsd_snd_irq_disable(struct mtk_btcvsd_snd *bt)
{
regmap_update_bits(bt->infra, bt->infra_misc_offset,
bt->conn_bt_cvsd_mask, bt->conn_bt_cvsd_mask);
}
static void mtk_btcvsd_snd_set_state(struct mtk_btcvsd_snd *bt,
struct mtk_btcvsd_snd_stream *bt_stream,
int state)
{
dev_dbg(bt->dev, "%s(), stream %d, state %d, tx->state %d, rx->state %d, irq_disabled %d\n",
__func__,
bt_stream->stream, state,
bt->tx->state, bt->rx->state, bt->irq_disabled);
bt_stream->state = state;
if (bt->tx->state == BT_SCO_STATE_IDLE &&
bt->rx->state == BT_SCO_STATE_IDLE) {
if (!bt->irq_disabled) {
disable_irq(bt->irq_id);
mtk_btcvsd_snd_irq_disable(bt);
bt->irq_disabled = 1;
}
} else {
if (bt->irq_disabled) {
enable_irq(bt->irq_id);
mtk_btcvsd_snd_irq_enable(bt);
bt->irq_disabled = 0;
}
}
}
static int mtk_btcvsd_snd_tx_init(struct mtk_btcvsd_snd *bt)
{
memset(bt->tx, 0, sizeof(*bt->tx));
memset(bt->tx_packet_buf, 0, sizeof(bt->tx_packet_buf));
bt->tx->packet_size = BTCVSD_TX_PACKET_SIZE;
bt->tx->buf_size = BTCVSD_TX_BUF_SIZE;
bt->tx->timeout = 0;
bt->tx->rw_cnt = 0;
bt->tx->stream = SNDRV_PCM_STREAM_PLAYBACK;
return 0;
}
static int mtk_btcvsd_snd_rx_init(struct mtk_btcvsd_snd *bt)
{
memset(bt->rx, 0, sizeof(*bt->rx));
memset(bt->rx_packet_buf, 0, sizeof(bt->rx_packet_buf));
bt->rx->packet_size = BTCVSD_RX_PACKET_SIZE;
bt->rx->buf_size = BTCVSD_RX_BUF_SIZE;
bt->rx->timeout = 0;
bt->rx->rw_cnt = 0;
bt->rx->stream = SNDRV_PCM_STREAM_CAPTURE;
return 0;
}
static void get_tx_time_stamp(struct mtk_btcvsd_snd *bt,
struct mtk_btcvsd_snd_time_buffer_info *ts)
{
ts->time_stamp_us = bt->tx->time_stamp;
ts->data_count_equi_time = bt->tx->buf_data_equivalent_time;
}
static void get_rx_time_stamp(struct mtk_btcvsd_snd *bt,
struct mtk_btcvsd_snd_time_buffer_info *ts)
{
ts->time_stamp_us = bt->rx->time_stamp;
ts->data_count_equi_time = bt->rx->buf_data_equivalent_time;
}
static int btcvsd_bytes_to_frame(struct snd_pcm_substream *substream,
int bytes)
{
int count = bytes;
struct snd_pcm_runtime *runtime = substream->runtime;
if (runtime->format == SNDRV_PCM_FORMAT_S32_LE ||
runtime->format == SNDRV_PCM_FORMAT_U32_LE)
count = count >> 2;
else
count = count >> 1;
count = count / runtime->channels;
return count;
}
static void mtk_btcvsd_snd_data_transfer(enum bt_sco_direct dir,
u8 *src, u8 *dst,
unsigned int blk_size,
unsigned int blk_num)
{
unsigned int i, j;
if (blk_size == 60 || blk_size == 120 || blk_size == 20) {
u32 *src_32 = (u32 *)src;
u32 *dst_32 = (u32 *)dst;
for (i = 0; i < (blk_size * blk_num / 4); i++)
*dst_32++ = *src_32++;
} else {
u16 *src_16 = (u16 *)src;
u16 *dst_16 = (u16 *)dst;
for (j = 0; j < blk_num; j++) {
for (i = 0; i < (blk_size / 2); i++)
*dst_16++ = *src_16++;
if (dir == BT_SCO_DIRECT_BT2ARM)
src_16++;
else
dst_16++;
}
}
}
/* write encoded mute data to bt sram */
static int btcvsd_tx_clean_buffer(struct mtk_btcvsd_snd *bt)
{
unsigned int i;
unsigned int num_valid_addr;
unsigned long flags;
enum BT_SCO_BAND band = bt->band;
/* prepare encoded mute data */
if (band == BT_SCO_NB)
memset(bt->tx->temp_packet_buf, 170, SCO_PACKET_180);
else
memcpy(bt->tx->temp_packet_buf,
table_msbc_silence, SCO_PACKET_180);
/* write mute data to bt tx sram buffer */
spin_lock_irqsave(&bt->tx_lock, flags);
num_valid_addr = bt->tx->buffer_info.num_valid_addr;
dev_info(bt->dev, "%s(), band %d, num_valid_addr %u\n",
__func__, band, num_valid_addr);
for (i = 0; i < num_valid_addr; i++) {
void *dst;
dev_info(bt->dev, "%s(), clean addr 0x%lx\n", __func__,
bt->tx->buffer_info.bt_sram_addr[i]);
dst = (void *)bt->tx->buffer_info.bt_sram_addr[i];
mtk_btcvsd_snd_data_transfer(BT_SCO_DIRECT_ARM2BT,
bt->tx->temp_packet_buf, dst,
bt->tx->buffer_info.packet_length,
bt->tx->buffer_info.packet_num);
}
spin_unlock_irqrestore(&bt->tx_lock, flags);
return 0;
}
static int mtk_btcvsd_read_from_bt(struct mtk_btcvsd_snd *bt,
enum bt_sco_packet_len packet_type,
unsigned int packet_length,
unsigned int packet_num,
unsigned int blk_size,
unsigned int control)
{
unsigned int i;
int pv;
u8 *src;
unsigned int packet_buf_ofs;
unsigned long flags;
unsigned long connsys_addr_rx, ap_addr_rx;
connsys_addr_rx = *bt->bt_reg_pkt_r;
ap_addr_rx = (unsigned long)bt->bt_sram_bank2_base +
(connsys_addr_rx & 0xFFFF);
if (connsys_addr_rx == 0xdeadfeed) {
/* bt return 0xdeadfeed if read register during bt sleep */
dev_warn(bt->dev, "%s(), connsys_addr_rx == 0xdeadfeed",
__func__);
return -EIO;
}
src = (u8 *)ap_addr_rx;
mtk_btcvsd_snd_data_transfer(BT_SCO_DIRECT_BT2ARM, src,
bt->rx->temp_packet_buf, packet_length,
packet_num);
spin_lock_irqsave(&bt->rx_lock, flags);
for (i = 0; i < blk_size; i++) {
packet_buf_ofs = (bt->rx->packet_w & SCO_RX_PACKET_MASK) *
bt->rx->packet_size;
memcpy(bt->rx_packet_buf + packet_buf_ofs,
bt->rx->temp_packet_buf + (SCO_RX_PLC_SIZE * i),
SCO_RX_PLC_SIZE);
if ((control & btsco_packet_valid_mask[packet_type][i]) ==
btsco_packet_valid_mask[packet_type][i])
pv = 1;
else
pv = 0;
packet_buf_ofs += SCO_RX_PLC_SIZE;
memcpy(bt->rx_packet_buf + packet_buf_ofs, (void *)&pv,
SCO_CVSD_PACKET_VALID_SIZE);
bt->rx->packet_w++;
}
spin_unlock_irqrestore(&bt->rx_lock, flags);
return 0;
}
static int mtk_btcvsd_write_to_bt(struct mtk_btcvsd_snd *bt,
enum bt_sco_packet_len packet_type,
unsigned int packet_length,
unsigned int packet_num,
unsigned int blk_size)
{
unsigned int i;
unsigned long flags;
u8 *dst;
unsigned long connsys_addr_tx, ap_addr_tx;
bool new_ap_addr_tx = true;
connsys_addr_tx = *bt->bt_reg_pkt_w;
ap_addr_tx = (unsigned long)bt->bt_sram_bank2_base +
(connsys_addr_tx & 0xFFFF);
if (connsys_addr_tx == 0xdeadfeed) {
/* bt return 0xdeadfeed if read register during bt sleep */
dev_warn(bt->dev, "%s(), connsys_addr_tx == 0xdeadfeed\n",
__func__);
return -EIO;
}
spin_lock_irqsave(&bt->tx_lock, flags);
for (i = 0; i < blk_size; i++) {
memcpy(bt->tx->temp_packet_buf + (bt->tx->packet_size * i),
(bt->tx_packet_buf +
(bt->tx->packet_r % SCO_TX_PACKER_BUF_NUM) *
bt->tx->packet_size),
bt->tx->packet_size);
bt->tx->packet_r++;
}
spin_unlock_irqrestore(&bt->tx_lock, flags);
dst = (u8 *)ap_addr_tx;
if (!bt->tx->mute) {
mtk_btcvsd_snd_data_transfer(BT_SCO_DIRECT_ARM2BT,
bt->tx->temp_packet_buf, dst,
packet_length, packet_num);
}
/* store bt tx buffer sram info */
bt->tx->buffer_info.packet_length = packet_length;
bt->tx->buffer_info.packet_num = packet_num;
for (i = 0; i < bt->tx->buffer_info.num_valid_addr; i++) {
if (bt->tx->buffer_info.bt_sram_addr[i] == ap_addr_tx) {
new_ap_addr_tx = false;
break;
}
}
if (new_ap_addr_tx) {
unsigned int next_idx;
spin_lock_irqsave(&bt->tx_lock, flags);
bt->tx->buffer_info.num_valid_addr++;
next_idx = bt->tx->buffer_info.num_valid_addr - 1;
bt->tx->buffer_info.bt_sram_addr[next_idx] = ap_addr_tx;
spin_unlock_irqrestore(&bt->tx_lock, flags);
dev_info(bt->dev, "%s(), new ap_addr_tx = 0x%lx, num_valid_addr %d\n",
__func__, ap_addr_tx,
bt->tx->buffer_info.num_valid_addr);
}
if (bt->tx->mute)
btcvsd_tx_clean_buffer(bt);
return 0;
}
static irqreturn_t mtk_btcvsd_snd_irq_handler(int irq_id, void *dev)
{
struct mtk_btcvsd_snd *bt = dev;
unsigned int packet_type, packet_num, packet_length;
unsigned int buf_cnt_tx, buf_cnt_rx, control;
if (bt->rx->state != BT_SCO_STATE_RUNNING &&
bt->rx->state != BT_SCO_STATE_ENDING &&
bt->tx->state != BT_SCO_STATE_RUNNING &&
bt->tx->state != BT_SCO_STATE_ENDING &&
bt->tx->state != BT_SCO_STATE_LOOPBACK) {
dev_warn(bt->dev, "%s(), in idle state: rx->state: %d, tx->state: %d\n",
__func__, bt->rx->state, bt->tx->state);
goto irq_handler_exit;
}
control = *bt->bt_reg_ctl;
packet_type = (control >> 18) & 0x7;
if (((control >> 31) & 1) == 0) {
dev_warn(bt->dev, "%s(), ((control >> 31) & 1) == 0, control 0x%x\n",
__func__, control);
goto irq_handler_exit;
}
if (packet_type >= BT_SCO_CVSD_MAX) {
dev_warn(bt->dev, "%s(), invalid packet_type %u, exit\n",
__func__, packet_type);
goto irq_handler_exit;
}
packet_length = btsco_packet_info[packet_type][0];
packet_num = btsco_packet_info[packet_type][1];
buf_cnt_tx = btsco_packet_info[packet_type][2];
buf_cnt_rx = btsco_packet_info[packet_type][3];
if (bt->tx->state == BT_SCO_STATE_LOOPBACK) {
u8 *src, *dst;
unsigned long connsys_addr_rx, ap_addr_rx;
unsigned long connsys_addr_tx, ap_addr_tx;
connsys_addr_rx = *bt->bt_reg_pkt_r;
ap_addr_rx = (unsigned long)bt->bt_sram_bank2_base +
(connsys_addr_rx & 0xFFFF);
connsys_addr_tx = *bt->bt_reg_pkt_w;
ap_addr_tx = (unsigned long)bt->bt_sram_bank2_base +
(connsys_addr_tx & 0xFFFF);
if (connsys_addr_tx == 0xdeadfeed ||
connsys_addr_rx == 0xdeadfeed) {
/* bt return 0xdeadfeed if read reg during bt sleep */
dev_warn(bt->dev, "%s(), connsys_addr_tx == 0xdeadfeed\n",
__func__);
goto irq_handler_exit;
}
src = (u8 *)ap_addr_rx;
dst = (u8 *)ap_addr_tx;
mtk_btcvsd_snd_data_transfer(BT_SCO_DIRECT_BT2ARM, src,
bt->tx->temp_packet_buf,
packet_length,
packet_num);
mtk_btcvsd_snd_data_transfer(BT_SCO_DIRECT_ARM2BT,
bt->tx->temp_packet_buf, dst,
packet_length,
packet_num);
bt->rx->rw_cnt++;
bt->tx->rw_cnt++;
}
if (bt->rx->state == BT_SCO_STATE_RUNNING ||
bt->rx->state == BT_SCO_STATE_ENDING) {
if (bt->rx->xrun) {
if (bt->rx->packet_w - bt->rx->packet_r <=
SCO_RX_PACKER_BUF_NUM - 2 * buf_cnt_rx) {
/*
* free space is larger then
* twice interrupt rx data size
*/
bt->rx->xrun = 0;
dev_warn(bt->dev, "%s(), rx->xrun 0!\n",
__func__);
}
}
if (!bt->rx->xrun &&
(bt->rx->packet_w - bt->rx->packet_r <=
SCO_RX_PACKER_BUF_NUM - buf_cnt_rx)) {
mtk_btcvsd_read_from_bt(bt,
packet_type,
packet_length,
packet_num,
buf_cnt_rx,
control);
bt->rx->rw_cnt++;
} else {
bt->rx->xrun = 1;
dev_warn(bt->dev, "%s(), rx->xrun 1\n", __func__);
}
}
/* tx */
bt->tx->timeout = 0;
if ((bt->tx->state == BT_SCO_STATE_RUNNING ||
bt->tx->state == BT_SCO_STATE_ENDING) &&
bt->tx->trigger_start) {
if (bt->tx->xrun) {
/* prepared data is larger then twice
* interrupt tx data size
*/
if (bt->tx->packet_w - bt->tx->packet_r >=
2 * buf_cnt_tx) {
bt->tx->xrun = 0;
dev_warn(bt->dev, "%s(), tx->xrun 0\n",
__func__);
}
}
if ((!bt->tx->xrun &&
(bt->tx->packet_w - bt->tx->packet_r >= buf_cnt_tx)) ||
bt->tx->state == BT_SCO_STATE_ENDING) {
mtk_btcvsd_write_to_bt(bt,
packet_type,
packet_length,
packet_num,
buf_cnt_tx);
bt->tx->rw_cnt++;
} else {
bt->tx->xrun = 1;
dev_warn(bt->dev, "%s(), tx->xrun 1\n", __func__);
}
}
*bt->bt_reg_ctl &= ~BT_CVSD_CLEAR;
if (bt->rx->state == BT_SCO_STATE_RUNNING ||
bt->rx->state == BT_SCO_STATE_ENDING) {
bt->rx->wait_flag = 1;
wake_up_interruptible(&bt->rx_wait);
snd_pcm_period_elapsed(bt->rx->substream);
}
if (bt->tx->state == BT_SCO_STATE_RUNNING ||
bt->tx->state == BT_SCO_STATE_ENDING) {
bt->tx->wait_flag = 1;
wake_up_interruptible(&bt->tx_wait);
snd_pcm_period_elapsed(bt->tx->substream);
}
return IRQ_HANDLED;
irq_handler_exit:
*bt->bt_reg_ctl &= ~BT_CVSD_CLEAR;
return IRQ_HANDLED;
}
static int wait_for_bt_irq(struct mtk_btcvsd_snd *bt,
struct mtk_btcvsd_snd_stream *bt_stream)
{
unsigned long long t1, t2;
/* one interrupt period = 22.5ms */
unsigned long long timeout_limit = 22500000;
int max_timeout_trial = 2;
int ret;
bt_stream->wait_flag = 0;
while (max_timeout_trial && !bt_stream->wait_flag) {
t1 = sched_clock();
if (bt_stream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
ret = wait_event_interruptible_timeout(bt->tx_wait,
bt_stream->wait_flag,
nsecs_to_jiffies(timeout_limit));
} else {
ret = wait_event_interruptible_timeout(bt->rx_wait,
bt_stream->wait_flag,
nsecs_to_jiffies(timeout_limit));
}
t2 = sched_clock();
t2 = t2 - t1; /* in ns (10^9) */
if (t2 > timeout_limit) {
dev_warn(bt->dev, "%s(), stream %d, timeout %llu, limit %llu, ret %d, flag %d\n",
__func__, bt_stream->stream,
t2, timeout_limit, ret,
bt_stream->wait_flag);
}
if (ret < 0) {
/*
* error, -ERESTARTSYS if it was interrupted by
* a signal
*/
dev_warn(bt->dev, "%s(), stream %d, error, trial left %d\n",
__func__,
bt_stream->stream, max_timeout_trial);
bt_stream->timeout = 1;
return ret;
} else if (ret == 0) {
/* conidtion is false after timeout */
max_timeout_trial--;
dev_warn(bt->dev, "%s(), stream %d, error, timeout, condition is false, trial left %d\n",
__func__,
bt_stream->stream, max_timeout_trial);
if (max_timeout_trial <= 0) {
bt_stream->timeout = 1;
return -ETIME;
}
}
}
return 0;
}
static ssize_t mtk_btcvsd_snd_read(struct mtk_btcvsd_snd *bt,
struct iov_iter *buf,
size_t count)
{
ssize_t read_size = 0, read_count = 0, cur_read_idx, cont;
unsigned long avail;
unsigned long flags;
unsigned int packet_size = bt->rx->packet_size;
while (count) {
spin_lock_irqsave(&bt->rx_lock, flags);
/* available data in RX packet buffer */
avail = (bt->rx->packet_w - bt->rx->packet_r) * packet_size;
cur_read_idx = (bt->rx->packet_r & SCO_RX_PACKET_MASK) *
packet_size;
spin_unlock_irqrestore(&bt->rx_lock, flags);
if (!avail) {
int ret = wait_for_bt_irq(bt, bt->rx);
if (ret)
return read_count;
continue;
}
/* count must be multiple of packet_size */
if (count % packet_size != 0 ||
avail % packet_size != 0) {
dev_warn(bt->dev, "%s(), count %zu or d %lu is not multiple of packet_size %dd\n",
__func__, count, avail, packet_size);
count -= count % packet_size;
avail -= avail % packet_size;
}
if (count > avail)
read_size = avail;
else
read_size = count;
/* calculate continue space */
cont = bt->rx->buf_size - cur_read_idx;
if (read_size > cont)
read_size = cont;
if (copy_to_iter(bt->rx_packet_buf + cur_read_idx,
read_size, buf) != read_size) {
dev_warn(bt->dev, "%s(), copy_to_iter fail\n",
__func__);
return -EFAULT;
}
spin_lock_irqsave(&bt->rx_lock, flags);
bt->rx->packet_r += read_size / packet_size;
spin_unlock_irqrestore(&bt->rx_lock, flags);
read_count += read_size;
count -= read_size;
}
/*
* save current timestamp & buffer time in times_tamp and
* buf_data_equivalent_time
*/
bt->rx->time_stamp = sched_clock();
bt->rx->buf_data_equivalent_time =
(unsigned long long)(bt->rx->packet_w - bt->rx->packet_r) *
SCO_RX_PLC_SIZE * 16 * 1000 / 2 / 64;
bt->rx->buf_data_equivalent_time += read_count * SCO_RX_PLC_SIZE *
16 * 1000 / packet_size / 2 / 64;
/* return equivalent time(us) to data count */
bt->rx->buf_data_equivalent_time *= 1000;
return read_count;
}
static ssize_t mtk_btcvsd_snd_write(struct mtk_btcvsd_snd *bt,
struct iov_iter *buf,
size_t count)
{
int written_size = count, avail, cur_write_idx, write_size, cont;
unsigned long flags;
unsigned int packet_size = bt->tx->packet_size;
/*
* save current timestamp & buffer time in time_stamp and
* buf_data_equivalent_time
*/
bt->tx->time_stamp = sched_clock();
bt->tx->buf_data_equivalent_time =
(unsigned long long)(bt->tx->packet_w - bt->tx->packet_r) *
packet_size * 16 * 1000 / 2 / 64;
/* return equivalent time(us) to data count */
bt->tx->buf_data_equivalent_time *= 1000;
while (count) {
spin_lock_irqsave(&bt->tx_lock, flags);
/* free space of TX packet buffer */
avail = bt->tx->buf_size -
(bt->tx->packet_w - bt->tx->packet_r) * packet_size;
cur_write_idx = (bt->tx->packet_w % SCO_TX_PACKER_BUF_NUM) *
packet_size;
spin_unlock_irqrestore(&bt->tx_lock, flags);
if (!avail) {
int ret = wait_for_bt_irq(bt, bt->tx);
if (ret)
return written_size;
continue;
}
/* count must be multiple of bt->tx->packet_size */
if (count % packet_size != 0 ||
avail % packet_size != 0) {
dev_warn(bt->dev, "%s(), count %zu or avail %d is not multiple of packet_size %d\n",
__func__, count, avail, packet_size);
count -= count % packet_size;
avail -= avail % packet_size;
}
if (count > avail)
write_size = avail;
else
write_size = count;
/* calculate continue space */
cont = bt->tx->buf_size - cur_write_idx;
if (write_size > cont)
write_size = cont;
if (copy_from_iter(bt->tx_packet_buf + cur_write_idx,
write_size, buf) != write_size) {
dev_warn(bt->dev, "%s(), copy_from_iter fail\n",
__func__);
return -EFAULT;
}
spin_lock_irqsave(&bt->tx_lock, flags);
bt->tx->packet_w += write_size / packet_size;
spin_unlock_irqrestore(&bt->tx_lock, flags);
count -= write_size;
}
return written_size;
}
static struct mtk_btcvsd_snd_stream *get_bt_stream
(struct mtk_btcvsd_snd *bt, struct snd_pcm_substream *substream)
{
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
return bt->tx;
else
return bt->rx;
}
/* pcm ops */
static const struct snd_pcm_hardware mtk_btcvsd_hardware = {
.info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_RESUME),
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.buffer_bytes_max = 24 * 1024,
.period_bytes_max = 24 * 1024,
.periods_min = 2,
.periods_max = 16,
.fifo_size = 0,
};
static int mtk_pcm_btcvsd_open(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct mtk_btcvsd_snd *bt = snd_soc_component_get_drvdata(component);
int ret;
dev_dbg(bt->dev, "%s(), stream %d, substream %p\n",
__func__, substream->stream, substream);
snd_soc_set_runtime_hwparams(substream, &mtk_btcvsd_hardware);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
ret = mtk_btcvsd_snd_tx_init(bt);
bt->tx->substream = substream;
} else {
ret = mtk_btcvsd_snd_rx_init(bt);
bt->rx->substream = substream;
}
return ret;
}
static int mtk_pcm_btcvsd_close(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct mtk_btcvsd_snd *bt = snd_soc_component_get_drvdata(component);
struct mtk_btcvsd_snd_stream *bt_stream = get_bt_stream(bt, substream);
dev_dbg(bt->dev, "%s(), stream %d\n", __func__, substream->stream);
mtk_btcvsd_snd_set_state(bt, bt_stream, BT_SCO_STATE_IDLE);
bt_stream->substream = NULL;
return 0;
}
static int mtk_pcm_btcvsd_hw_params(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *hw_params)
{
struct mtk_btcvsd_snd *bt = snd_soc_component_get_drvdata(component);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK &&
params_buffer_bytes(hw_params) % bt->tx->packet_size != 0) {
dev_warn(bt->dev, "%s(), error, buffer size %d not valid\n",
__func__,
params_buffer_bytes(hw_params));
return -EINVAL;
}
substream->runtime->dma_bytes = params_buffer_bytes(hw_params);
return 0;
}
static int mtk_pcm_btcvsd_hw_free(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct mtk_btcvsd_snd *bt = snd_soc_component_get_drvdata(component);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
btcvsd_tx_clean_buffer(bt);
return 0;
}
static int mtk_pcm_btcvsd_prepare(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct mtk_btcvsd_snd *bt = snd_soc_component_get_drvdata(component);
struct mtk_btcvsd_snd_stream *bt_stream = get_bt_stream(bt, substream);
dev_dbg(bt->dev, "%s(), stream %d\n", __func__, substream->stream);
mtk_btcvsd_snd_set_state(bt, bt_stream, BT_SCO_STATE_RUNNING);
return 0;
}
static int mtk_pcm_btcvsd_trigger(struct snd_soc_component *component,
struct snd_pcm_substream *substream, int cmd)
{
struct mtk_btcvsd_snd *bt = snd_soc_component_get_drvdata(component);
struct mtk_btcvsd_snd_stream *bt_stream = get_bt_stream(bt, substream);
int stream = substream->stream;
int hw_packet_ptr;
dev_dbg(bt->dev, "%s(), stream %d, cmd %d\n",
__func__, substream->stream, cmd);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
hw_packet_ptr = stream == SNDRV_PCM_STREAM_PLAYBACK ?
bt_stream->packet_r : bt_stream->packet_w;
bt_stream->prev_packet_idx = hw_packet_ptr;
bt_stream->prev_frame = 0;
bt_stream->trigger_start = 1;
return 0;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
bt_stream->trigger_start = 0;
mtk_btcvsd_snd_set_state(bt, bt_stream, BT_SCO_STATE_ENDING);
return 0;
default:
return -EINVAL;
}
}
static snd_pcm_uframes_t mtk_pcm_btcvsd_pointer(
struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct mtk_btcvsd_snd *bt = snd_soc_component_get_drvdata(component);
struct mtk_btcvsd_snd_stream *bt_stream;
snd_pcm_uframes_t frame = 0;
int byte = 0;
int hw_packet_ptr;
int packet_diff;
spinlock_t *lock; /* spinlock for bt stream control */
unsigned long flags;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
lock = &bt->tx_lock;
bt_stream = bt->tx;
} else {
lock = &bt->rx_lock;
bt_stream = bt->rx;
}
spin_lock_irqsave(lock, flags);
hw_packet_ptr = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
bt->tx->packet_r : bt->rx->packet_w;
/* get packet diff from last time */
if (hw_packet_ptr >= bt_stream->prev_packet_idx) {
packet_diff = hw_packet_ptr - bt_stream->prev_packet_idx;
} else {
/* integer overflow */
packet_diff = (INT_MAX - bt_stream->prev_packet_idx) +
(hw_packet_ptr - INT_MIN) + 1;
}
bt_stream->prev_packet_idx = hw_packet_ptr;
/* increased bytes */
byte = packet_diff * bt_stream->packet_size;
frame = btcvsd_bytes_to_frame(substream, byte);
frame += bt_stream->prev_frame;
frame %= substream->runtime->buffer_size;
bt_stream->prev_frame = frame;
spin_unlock_irqrestore(lock, flags);
return frame;
}
static int mtk_pcm_btcvsd_copy(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
int channel, unsigned long pos,
struct iov_iter *buf, unsigned long count)
{
struct mtk_btcvsd_snd *bt = snd_soc_component_get_drvdata(component);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
return mtk_btcvsd_snd_write(bt, buf, count);
else
return mtk_btcvsd_snd_read(bt, buf, count);
}
/* kcontrol */
static const char *const btsco_band_str[] = {"NB", "WB"};
static const struct soc_enum btcvsd_enum[] = {
SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(btsco_band_str), btsco_band_str),
};
static int btcvsd_band_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_btcvsd_snd *bt = snd_soc_component_get_drvdata(cmpnt);
ucontrol->value.integer.value[0] = bt->band;
return 0;
}
static int btcvsd_band_set(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_btcvsd_snd *bt = snd_soc_component_get_drvdata(cmpnt);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
if (ucontrol->value.enumerated.item[0] >= e->items)
return -EINVAL;
bt->band = ucontrol->value.integer.value[0];
dev_dbg(bt->dev, "%s(), band %d\n", __func__, bt->band);
return 0;
}
static int btcvsd_loopback_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_btcvsd_snd *bt = snd_soc_component_get_drvdata(cmpnt);
bool lpbk_en = bt->tx->state == BT_SCO_STATE_LOOPBACK;
ucontrol->value.integer.value[0] = lpbk_en;
return 0;
}
static int btcvsd_loopback_set(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_btcvsd_snd *bt = snd_soc_component_get_drvdata(cmpnt);
if (ucontrol->value.integer.value[0]) {
mtk_btcvsd_snd_set_state(bt, bt->tx, BT_SCO_STATE_LOOPBACK);
mtk_btcvsd_snd_set_state(bt, bt->rx, BT_SCO_STATE_LOOPBACK);
} else {
mtk_btcvsd_snd_set_state(bt, bt->tx, BT_SCO_STATE_RUNNING);
mtk_btcvsd_snd_set_state(bt, bt->rx, BT_SCO_STATE_RUNNING);
}
return 0;
}
static int btcvsd_tx_mute_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_btcvsd_snd *bt = snd_soc_component_get_drvdata(cmpnt);
if (!bt->tx) {
ucontrol->value.integer.value[0] = 0;
return 0;
}
ucontrol->value.integer.value[0] = bt->tx->mute;
return 0;
}
static int btcvsd_tx_mute_set(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_btcvsd_snd *bt = snd_soc_component_get_drvdata(cmpnt);
if (!bt->tx)
return 0;
bt->tx->mute = ucontrol->value.integer.value[0];
return 0;
}
static int btcvsd_rx_irq_received_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_btcvsd_snd *bt = snd_soc_component_get_drvdata(cmpnt);
if (!bt->rx)
return 0;
ucontrol->value.integer.value[0] = bt->rx->rw_cnt ? 1 : 0;
return 0;
}
static int btcvsd_rx_timeout_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_btcvsd_snd *bt = snd_soc_component_get_drvdata(cmpnt);
if (!bt->rx)
return 0;
ucontrol->value.integer.value[0] = bt->rx->timeout;
bt->rx->timeout = 0;
return 0;
}
static int btcvsd_rx_timestamp_get(struct snd_kcontrol *kcontrol,
unsigned int __user *data, unsigned int size)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_btcvsd_snd *bt = snd_soc_component_get_drvdata(cmpnt);
int ret = 0;
struct mtk_btcvsd_snd_time_buffer_info time_buffer_info_rx;
if (size > sizeof(struct mtk_btcvsd_snd_time_buffer_info))
return -EINVAL;
get_rx_time_stamp(bt, &time_buffer_info_rx);
dev_dbg(bt->dev, "%s(), time_stamp_us %llu, data_count_equi_time %llu",
__func__,
time_buffer_info_rx.time_stamp_us,
time_buffer_info_rx.data_count_equi_time);
if (copy_to_user(data, &time_buffer_info_rx,
sizeof(struct mtk_btcvsd_snd_time_buffer_info))) {
dev_warn(bt->dev, "%s(), copy_to_user fail", __func__);
ret = -EFAULT;
}
return ret;
}
static int btcvsd_tx_irq_received_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_btcvsd_snd *bt = snd_soc_component_get_drvdata(cmpnt);
if (!bt->tx)
return 0;
ucontrol->value.integer.value[0] = bt->tx->rw_cnt ? 1 : 0;
return 0;
}
static int btcvsd_tx_timeout_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_btcvsd_snd *bt = snd_soc_component_get_drvdata(cmpnt);
ucontrol->value.integer.value[0] = bt->tx->timeout;
return 0;
}
static int btcvsd_tx_timestamp_get(struct snd_kcontrol *kcontrol,
unsigned int __user *data, unsigned int size)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_btcvsd_snd *bt = snd_soc_component_get_drvdata(cmpnt);
int ret = 0;
struct mtk_btcvsd_snd_time_buffer_info time_buffer_info_tx;
if (size > sizeof(struct mtk_btcvsd_snd_time_buffer_info))
return -EINVAL;
get_tx_time_stamp(bt, &time_buffer_info_tx);
dev_dbg(bt->dev, "%s(), time_stamp_us %llu, data_count_equi_time %llu",
__func__,
time_buffer_info_tx.time_stamp_us,
time_buffer_info_tx.data_count_equi_time);
if (copy_to_user(data, &time_buffer_info_tx,
sizeof(struct mtk_btcvsd_snd_time_buffer_info))) {
dev_warn(bt->dev, "%s(), copy_to_user fail", __func__);
ret = -EFAULT;
}
return ret;
}
static const struct snd_kcontrol_new mtk_btcvsd_snd_controls[] = {
SOC_ENUM_EXT("BTCVSD Band", btcvsd_enum[0],
btcvsd_band_get, btcvsd_band_set),
SOC_SINGLE_BOOL_EXT("BTCVSD Loopback Switch", 0,
btcvsd_loopback_get, btcvsd_loopback_set),
SOC_SINGLE_BOOL_EXT("BTCVSD Tx Mute Switch", 0,
btcvsd_tx_mute_get, btcvsd_tx_mute_set),
SOC_SINGLE_BOOL_EXT("BTCVSD Tx Irq Received Switch", 0,
btcvsd_tx_irq_received_get, NULL),
SOC_SINGLE_BOOL_EXT("BTCVSD Tx Timeout Switch", 0,
btcvsd_tx_timeout_get, NULL),
SOC_SINGLE_BOOL_EXT("BTCVSD Rx Irq Received Switch", 0,
btcvsd_rx_irq_received_get, NULL),
SOC_SINGLE_BOOL_EXT("BTCVSD Rx Timeout Switch", 0,
btcvsd_rx_timeout_get, NULL),
SND_SOC_BYTES_TLV("BTCVSD Rx Timestamp",
sizeof(struct mtk_btcvsd_snd_time_buffer_info),
btcvsd_rx_timestamp_get, NULL),
SND_SOC_BYTES_TLV("BTCVSD Tx Timestamp",
sizeof(struct mtk_btcvsd_snd_time_buffer_info),
btcvsd_tx_timestamp_get, NULL),
};
static int mtk_btcvsd_snd_component_probe(struct snd_soc_component *component)
{
return snd_soc_add_component_controls(component,
mtk_btcvsd_snd_controls,
ARRAY_SIZE(mtk_btcvsd_snd_controls));
}
static const struct snd_soc_component_driver mtk_btcvsd_snd_platform = {
.name = BTCVSD_SND_NAME,
.probe = mtk_btcvsd_snd_component_probe,
.open = mtk_pcm_btcvsd_open,
.close = mtk_pcm_btcvsd_close,
.hw_params = mtk_pcm_btcvsd_hw_params,
.hw_free = mtk_pcm_btcvsd_hw_free,
.prepare = mtk_pcm_btcvsd_prepare,
.trigger = mtk_pcm_btcvsd_trigger,
.pointer = mtk_pcm_btcvsd_pointer,
.copy = mtk_pcm_btcvsd_copy,
};
static int mtk_btcvsd_snd_probe(struct platform_device *pdev)
{
int ret;
int irq_id;
u32 offset[5] = {0, 0, 0, 0, 0};
struct mtk_btcvsd_snd *btcvsd;
struct device *dev = &pdev->dev;
/* init btcvsd private data */
btcvsd = devm_kzalloc(dev, sizeof(*btcvsd), GFP_KERNEL);
if (!btcvsd)
return -ENOMEM;
platform_set_drvdata(pdev, btcvsd);
btcvsd->dev = dev;
/* init tx/rx */
btcvsd->rx = devm_kzalloc(btcvsd->dev, sizeof(*btcvsd->rx), GFP_KERNEL);
if (!btcvsd->rx)
return -ENOMEM;
btcvsd->tx = devm_kzalloc(btcvsd->dev, sizeof(*btcvsd->tx), GFP_KERNEL);
if (!btcvsd->tx)
return -ENOMEM;
spin_lock_init(&btcvsd->tx_lock);
spin_lock_init(&btcvsd->rx_lock);
init_waitqueue_head(&btcvsd->tx_wait);
init_waitqueue_head(&btcvsd->rx_wait);
mtk_btcvsd_snd_tx_init(btcvsd);
mtk_btcvsd_snd_rx_init(btcvsd);
/* irq */
irq_id = platform_get_irq(pdev, 0);
if (irq_id <= 0)
return irq_id < 0 ? irq_id : -ENXIO;
ret = devm_request_irq(dev, irq_id, mtk_btcvsd_snd_irq_handler,
IRQF_TRIGGER_LOW, "BTCVSD_ISR_Handle",
(void *)btcvsd);
if (ret) {
dev_err(dev, "could not request_irq for BTCVSD_ISR_Handle\n");
return ret;
}
btcvsd->irq_id = irq_id;
/* iomap */
btcvsd->bt_pkv_base = of_iomap(dev->of_node, 0);
if (!btcvsd->bt_pkv_base) {
dev_err(dev, "iomap bt_pkv_base fail\n");
return -EIO;
}
btcvsd->bt_sram_bank2_base = of_iomap(dev->of_node, 1);
if (!btcvsd->bt_sram_bank2_base) {
dev_err(dev, "iomap bt_sram_bank2_base fail\n");
ret = -EIO;
goto unmap_pkv_err;
}
btcvsd->infra = syscon_regmap_lookup_by_phandle(dev->of_node,
"mediatek,infracfg");
if (IS_ERR(btcvsd->infra)) {
dev_err(dev, "cannot find infra controller: %ld\n",
PTR_ERR(btcvsd->infra));
ret = PTR_ERR(btcvsd->infra);
goto unmap_bank2_err;
}
/* get offset */
ret = of_property_read_u32_array(dev->of_node, "mediatek,offset",
offset,
ARRAY_SIZE(offset));
if (ret) {
dev_warn(dev, "%s(), get offset fail, ret %d\n", __func__, ret);
goto unmap_bank2_err;
}
btcvsd->infra_misc_offset = offset[0];
btcvsd->conn_bt_cvsd_mask = offset[1];
btcvsd->cvsd_mcu_read_offset = offset[2];
btcvsd->cvsd_mcu_write_offset = offset[3];
btcvsd->cvsd_packet_indicator = offset[4];
btcvsd->bt_reg_pkt_r = btcvsd->bt_pkv_base +
btcvsd->cvsd_mcu_read_offset;
btcvsd->bt_reg_pkt_w = btcvsd->bt_pkv_base +
btcvsd->cvsd_mcu_write_offset;
btcvsd->bt_reg_ctl = btcvsd->bt_pkv_base +
btcvsd->cvsd_packet_indicator;
/* init state */
mtk_btcvsd_snd_set_state(btcvsd, btcvsd->tx, BT_SCO_STATE_IDLE);
mtk_btcvsd_snd_set_state(btcvsd, btcvsd->rx, BT_SCO_STATE_IDLE);
ret = devm_snd_soc_register_component(dev, &mtk_btcvsd_snd_platform,
NULL, 0);
if (ret)
goto unmap_bank2_err;
return 0;
unmap_bank2_err:
iounmap(btcvsd->bt_sram_bank2_base);
unmap_pkv_err:
iounmap(btcvsd->bt_pkv_base);
return ret;
}
static void mtk_btcvsd_snd_remove(struct platform_device *pdev)
{
struct mtk_btcvsd_snd *btcvsd = dev_get_drvdata(&pdev->dev);
iounmap(btcvsd->bt_pkv_base);
iounmap(btcvsd->bt_sram_bank2_base);
}
static const struct of_device_id mtk_btcvsd_snd_dt_match[] = {
{ .compatible = "mediatek,mtk-btcvsd-snd", },
{},
};
MODULE_DEVICE_TABLE(of, mtk_btcvsd_snd_dt_match);
static struct platform_driver mtk_btcvsd_snd_driver = {
.driver = {
.name = "mtk-btcvsd-snd",
.of_match_table = mtk_btcvsd_snd_dt_match,
},
.probe = mtk_btcvsd_snd_probe,
.remove_new = mtk_btcvsd_snd_remove,
};
module_platform_driver(mtk_btcvsd_snd_driver);
MODULE_DESCRIPTION("Mediatek ALSA BT SCO CVSD/MSBC Driver");
MODULE_AUTHOR("KaiChieh Chuang <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/mediatek/common/mtk-btcvsd.c |
// SPDX-License-Identifier: GPL-2.0
/*
* mtk-soundcard-driver.c -- MediaTek soundcard driver common
*
* Copyright (c) 2022 MediaTek Inc.
* Author: Trevor Wu <[email protected]>
*/
#include <linux/module.h>
#include <linux/of.h>
#include <sound/soc.h>
#include "mtk-soundcard-driver.h"
static int set_card_codec_info(struct snd_soc_card *card,
struct device_node *sub_node,
struct snd_soc_dai_link *dai_link)
{
struct device *dev = card->dev;
struct device_node *codec_node;
int ret;
codec_node = of_get_child_by_name(sub_node, "codec");
if (!codec_node) {
dev_dbg(dev, "%s no specified codec\n", dai_link->name);
return 0;
}
/* set card codec info */
ret = snd_soc_of_get_dai_link_codecs(dev, codec_node, dai_link);
of_node_put(codec_node);
if (ret < 0)
return dev_err_probe(dev, ret, "%s: codec dai not found\n",
dai_link->name);
return 0;
}
static int set_dailink_daifmt(struct snd_soc_card *card,
struct device_node *sub_node,
struct snd_soc_dai_link *dai_link)
{
unsigned int daifmt;
const char *str;
int ret;
struct {
char *name;
unsigned int val;
} of_clk_table[] = {
{ "cpu", SND_SOC_DAIFMT_CBC_CFC },
{ "codec", SND_SOC_DAIFMT_CBP_CFP },
};
daifmt = snd_soc_daifmt_parse_format(sub_node, NULL);
if (daifmt) {
dai_link->dai_fmt &= SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK;
dai_link->dai_fmt |= daifmt;
}
/*
* check "mediatek,clk-provider = xxx"
* SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK area
*/
ret = of_property_read_string(sub_node, "mediatek,clk-provider", &str);
if (ret == 0) {
int i;
for (i = 0; i < ARRAY_SIZE(of_clk_table); i++) {
if (strcmp(str, of_clk_table[i].name) == 0) {
dai_link->dai_fmt &= ~SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK;
dai_link->dai_fmt |= of_clk_table[i].val;
break;
}
}
}
return 0;
}
int parse_dai_link_info(struct snd_soc_card *card)
{
struct device *dev = card->dev;
struct device_node *sub_node;
struct snd_soc_dai_link *dai_link;
const char *dai_link_name;
int ret, i;
/* Loop over all the dai link sub nodes */
for_each_available_child_of_node(dev->of_node, sub_node) {
if (of_property_read_string(sub_node, "link-name",
&dai_link_name)) {
of_node_put(sub_node);
return -EINVAL;
}
for_each_card_prelinks(card, i, dai_link) {
if (!strcmp(dai_link_name, dai_link->name))
break;
}
if (i >= card->num_links) {
of_node_put(sub_node);
return -EINVAL;
}
ret = set_card_codec_info(card, sub_node, dai_link);
if (ret < 0) {
of_node_put(sub_node);
return ret;
}
ret = set_dailink_daifmt(card, sub_node, dai_link);
if (ret < 0) {
of_node_put(sub_node);
return ret;
}
}
return 0;
}
EXPORT_SYMBOL_GPL(parse_dai_link_info);
void clean_card_reference(struct snd_soc_card *card)
{
struct snd_soc_dai_link *dai_link;
int i;
/* release codec reference gotten by set_card_codec_info */
for_each_card_prelinks(card, i, dai_link)
snd_soc_of_put_dai_link_codecs(dai_link);
}
EXPORT_SYMBOL_GPL(clean_card_reference);
| linux-master | sound/soc/mediatek/common/mtk-soundcard-driver.c |
// SPDX-License-Identifier: GPL-2.0
/*
* mt7986-wm8960.c -- MT7986-WM8960 ALSA SoC machine driver
*
* Copyright (c) 2023 MediaTek Inc.
* Authors: Vic Wu <[email protected]>
* Maso Huang <[email protected]>
*/
#include <linux/module.h>
#include <sound/soc.h>
#include "mt7986-afe-common.h"
struct mt7986_wm8960_priv {
struct device_node *platform_node;
struct device_node *codec_node;
};
static const struct snd_soc_dapm_widget mt7986_wm8960_widgets[] = {
SND_SOC_DAPM_HP("Headphone", NULL),
SND_SOC_DAPM_MIC("AMIC", NULL),
};
static const struct snd_kcontrol_new mt7986_wm8960_controls[] = {
SOC_DAPM_PIN_SWITCH("Headphone"),
SOC_DAPM_PIN_SWITCH("AMIC"),
};
SND_SOC_DAILINK_DEFS(playback,
DAILINK_COMP_ARRAY(COMP_CPU("DL1")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture,
DAILINK_COMP_ARRAY(COMP_CPU("UL1")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(codec,
DAILINK_COMP_ARRAY(COMP_CPU("ETDM")),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "wm8960-hifi")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
static struct snd_soc_dai_link mt7986_wm8960_dai_links[] = {
/* FE */
{
.name = "wm8960-playback",
.stream_name = "wm8960-playback",
.trigger = {SND_SOC_DPCM_TRIGGER_POST,
SND_SOC_DPCM_TRIGGER_POST},
.dynamic = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(playback),
},
{
.name = "wm8960-capture",
.stream_name = "wm8960-capture",
.trigger = {SND_SOC_DPCM_TRIGGER_POST,
SND_SOC_DPCM_TRIGGER_POST},
.dynamic = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(capture),
},
/* BE */
{
.name = "wm8960-codec",
.no_pcm = 1,
.dai_fmt = SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS |
SND_SOC_DAIFMT_GATED,
.dpcm_playback = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(codec),
},
};
static struct snd_soc_card mt7986_wm8960_card = {
.name = "mt7986-wm8960",
.owner = THIS_MODULE,
.dai_link = mt7986_wm8960_dai_links,
.num_links = ARRAY_SIZE(mt7986_wm8960_dai_links),
.controls = mt7986_wm8960_controls,
.num_controls = ARRAY_SIZE(mt7986_wm8960_controls),
.dapm_widgets = mt7986_wm8960_widgets,
.num_dapm_widgets = ARRAY_SIZE(mt7986_wm8960_widgets),
};
static int mt7986_wm8960_machine_probe(struct platform_device *pdev)
{
struct snd_soc_card *card = &mt7986_wm8960_card;
struct snd_soc_dai_link *dai_link;
struct device_node *platform, *codec;
struct mt7986_wm8960_priv *priv;
int ret, i;
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
platform = of_get_child_by_name(pdev->dev.of_node, "platform");
if (platform) {
priv->platform_node = of_parse_phandle(platform, "sound-dai", 0);
of_node_put(platform);
if (!priv->platform_node) {
dev_err(&pdev->dev, "Failed to parse platform/sound-dai property\n");
return -EINVAL;
}
} else {
dev_err(&pdev->dev, "Property 'platform' missing or invalid\n");
return -EINVAL;
}
for_each_card_prelinks(card, i, dai_link) {
if (dai_link->platforms->name)
continue;
dai_link->platforms->of_node = priv->platform_node;
}
card->dev = &pdev->dev;
codec = of_get_child_by_name(pdev->dev.of_node, "codec");
if (codec) {
priv->codec_node = of_parse_phandle(codec, "sound-dai", 0);
of_node_put(codec);
if (!priv->codec_node) {
of_node_put(priv->platform_node);
dev_err(&pdev->dev, "Failed to parse codec/sound-dai property\n");
return -EINVAL;
}
} else {
of_node_put(priv->platform_node);
dev_err(&pdev->dev, "Property 'codec' missing or invalid\n");
return -EINVAL;
}
for_each_card_prelinks(card, i, dai_link) {
if (dai_link->codecs->name)
continue;
dai_link->codecs->of_node = priv->codec_node;
}
ret = snd_soc_of_parse_audio_routing(card, "audio-routing");
if (ret) {
dev_err(&pdev->dev, "Failed to parse audio-routing: %d\n", ret);
goto err_of_node_put;
}
ret = devm_snd_soc_register_card(&pdev->dev, card);
if (ret) {
dev_err(&pdev->dev, "%s snd_soc_register_card fail: %d\n", __func__, ret);
goto err_of_node_put;
}
err_of_node_put:
of_node_put(priv->codec_node);
of_node_put(priv->platform_node);
return ret;
}
static void mt7986_wm8960_machine_remove(struct platform_device *pdev)
{
struct snd_soc_card *card = platform_get_drvdata(pdev);
struct mt7986_wm8960_priv *priv = snd_soc_card_get_drvdata(card);
of_node_put(priv->codec_node);
of_node_put(priv->platform_node);
}
static const struct of_device_id mt7986_wm8960_machine_dt_match[] = {
{.compatible = "mediatek,mt7986-wm8960-sound"},
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mt7986_wm8960_machine_dt_match);
static struct platform_driver mt7986_wm8960_machine = {
.driver = {
.name = "mt7986-wm8960",
.of_match_table = mt7986_wm8960_machine_dt_match,
},
.probe = mt7986_wm8960_machine_probe,
.remove_new = mt7986_wm8960_machine_remove,
};
module_platform_driver(mt7986_wm8960_machine);
/* Module information */
MODULE_DESCRIPTION("MT7986 WM8960 ALSA SoC machine driver");
MODULE_AUTHOR("Vic Wu <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("mt7986 wm8960 soc card");
| linux-master | sound/soc/mediatek/mt7986/mt7986-wm8960.c |
// SPDX-License-Identifier: GPL-2.0
/*
* MediaTek ALSA SoC Audio DAI eTDM Control
*
* Copyright (c) 2023 MediaTek Inc.
* Authors: Vic Wu <[email protected]>
* Maso Huang <[email protected]>
*/
#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/regmap.h>
#include <sound/pcm_params.h>
#include "mt7986-afe-common.h"
#include "mt7986-reg.h"
#define HOPPING_CLK 0
#define APLL_CLK 1
#define MTK_DAI_ETDM_FORMAT_I2S 0
#define MTK_DAI_ETDM_FORMAT_DSPA 4
#define MTK_DAI_ETDM_FORMAT_DSPB 5
enum {
MTK_ETDM_RATE_8K = 0,
MTK_ETDM_RATE_12K = 1,
MTK_ETDM_RATE_16K = 2,
MTK_ETDM_RATE_24K = 3,
MTK_ETDM_RATE_32K = 4,
MTK_ETDM_RATE_48K = 5,
MTK_ETDM_RATE_96K = 7,
MTK_ETDM_RATE_192K = 9,
MTK_ETDM_RATE_11K = 16,
MTK_ETDM_RATE_22K = 17,
MTK_ETDM_RATE_44K = 18,
MTK_ETDM_RATE_88K = 19,
MTK_ETDM_RATE_176K = 20,
};
struct mtk_dai_etdm_priv {
bool bck_inv;
bool lrck_inv;
bool slave_mode;
unsigned int format;
};
static unsigned int mt7986_etdm_rate_transform(struct device *dev, unsigned int rate)
{
switch (rate) {
case 8000:
return MTK_ETDM_RATE_8K;
case 11025:
return MTK_ETDM_RATE_11K;
case 12000:
return MTK_ETDM_RATE_12K;
case 16000:
return MTK_ETDM_RATE_16K;
case 22050:
return MTK_ETDM_RATE_22K;
case 24000:
return MTK_ETDM_RATE_24K;
case 32000:
return MTK_ETDM_RATE_32K;
case 44100:
return MTK_ETDM_RATE_44K;
case 48000:
return MTK_ETDM_RATE_48K;
case 88200:
return MTK_ETDM_RATE_88K;
case 96000:
return MTK_ETDM_RATE_96K;
case 176400:
return MTK_ETDM_RATE_176K;
case 192000:
return MTK_ETDM_RATE_192K;
default:
dev_warn(dev, "%s(), rate %u invalid, using %d!!!\n",
__func__, rate, MTK_ETDM_RATE_48K);
return MTK_ETDM_RATE_48K;
}
}
static int get_etdm_wlen(unsigned int bitwidth)
{
return bitwidth <= 16 ? 16 : 32;
}
/* dai component */
/* interconnection */
static const struct snd_kcontrol_new o124_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I032_Switch", AFE_CONN124_1, 0, 1, 0),
};
static const struct snd_kcontrol_new o125_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I033_Switch", AFE_CONN125_1, 1, 1, 0),
};
static const struct snd_soc_dapm_widget mtk_dai_etdm_widgets[] = {
/* DL */
SND_SOC_DAPM_MIXER("I150", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I151", SND_SOC_NOPM, 0, 0, NULL, 0),
/* UL */
SND_SOC_DAPM_MIXER("O124", SND_SOC_NOPM, 0, 0, o124_mix, ARRAY_SIZE(o124_mix)),
SND_SOC_DAPM_MIXER("O125", SND_SOC_NOPM, 0, 0, o125_mix, ARRAY_SIZE(o125_mix)),
};
static const struct snd_soc_dapm_route mtk_dai_etdm_routes[] = {
{"I150", NULL, "ETDM Capture"},
{"I151", NULL, "ETDM Capture"},
{"ETDM Playback", NULL, "O124"},
{"ETDM Playback", NULL, "O125"},
{"O124", "I032_Switch", "I032"},
{"O125", "I033_Switch", "I033"},
};
/* dai ops */
static int mtk_dai_etdm_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt7986_afe_private *afe_priv = afe->platform_priv;
int ret;
ret = clk_bulk_prepare_enable(afe_priv->num_clks, afe_priv->clks);
if (ret)
return dev_err_probe(afe->dev, ret, "Failed to enable clocks\n");
regmap_update_bits(afe->regmap, AUDIO_TOP_CON2, CLK_OUT5_PDN_MASK, 0);
regmap_update_bits(afe->regmap, AUDIO_TOP_CON2, CLK_IN5_PDN_MASK, 0);
return 0;
}
static void mtk_dai_etdm_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt7986_afe_private *afe_priv = afe->platform_priv;
regmap_update_bits(afe->regmap, AUDIO_TOP_CON2, CLK_OUT5_PDN_MASK,
CLK_OUT5_PDN);
regmap_update_bits(afe->regmap, AUDIO_TOP_CON2, CLK_IN5_PDN_MASK,
CLK_IN5_PDN);
clk_bulk_disable_unprepare(afe_priv->num_clks, afe_priv->clks);
}
static unsigned int get_etdm_ch_fixup(unsigned int channels)
{
if (channels > 16)
return 24;
else if (channels > 8)
return 16;
else if (channels > 4)
return 8;
else if (channels > 2)
return 4;
else
return 2;
}
static int mtk_dai_etdm_config(struct mtk_base_afe *afe,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai,
int stream)
{
struct mt7986_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai->id];
unsigned int rate = params_rate(params);
unsigned int etdm_rate = mt7986_etdm_rate_transform(afe->dev, rate);
unsigned int afe_rate = mt7986_afe_rate_transform(afe->dev, rate);
unsigned int channels = params_channels(params);
unsigned int bit_width = params_width(params);
unsigned int wlen = get_etdm_wlen(bit_width);
unsigned int val = 0;
unsigned int mask = 0;
dev_dbg(afe->dev, "%s(), stream %d, rate %u, bitwidth %u\n",
__func__, stream, rate, bit_width);
/* CON0 */
mask |= ETDM_BIT_LEN_MASK;
val |= FIELD_PREP(ETDM_BIT_LEN_MASK, bit_width - 1);
mask |= ETDM_WRD_LEN_MASK;
val |= FIELD_PREP(ETDM_WRD_LEN_MASK, wlen - 1);
mask |= ETDM_FMT_MASK;
val |= FIELD_PREP(ETDM_FMT_MASK, etdm_data->format);
mask |= ETDM_CH_NUM_MASK;
val |= FIELD_PREP(ETDM_CH_NUM_MASK, get_etdm_ch_fixup(channels) - 1);
mask |= RELATCH_SRC_MASK;
val |= FIELD_PREP(RELATCH_SRC_MASK, APLL_CLK);
switch (stream) {
case SNDRV_PCM_STREAM_PLAYBACK:
/* set ETDM_OUT5_CON0 */
regmap_update_bits(afe->regmap, ETDM_OUT5_CON0, mask, val);
/* set ETDM_OUT5_CON4 */
regmap_update_bits(afe->regmap, ETDM_OUT5_CON4,
OUT_RELATCH_MASK, OUT_RELATCH(afe_rate));
regmap_update_bits(afe->regmap, ETDM_OUT5_CON4,
OUT_CLK_SRC_MASK, OUT_CLK_SRC(APLL_CLK));
regmap_update_bits(afe->regmap, ETDM_OUT5_CON4,
OUT_SEL_FS_MASK, OUT_SEL_FS(etdm_rate));
/* set ETDM_OUT5_CON5 */
regmap_update_bits(afe->regmap, ETDM_OUT5_CON5,
ETDM_CLK_DIV_MASK, ETDM_CLK_DIV);
break;
case SNDRV_PCM_STREAM_CAPTURE:
/* set ETDM_IN5_CON0 */
regmap_update_bits(afe->regmap, ETDM_IN5_CON0, mask, val);
regmap_update_bits(afe->regmap, ETDM_IN5_CON0,
ETDM_SYNC_MASK, ETDM_SYNC);
/* set ETDM_IN5_CON2 */
regmap_update_bits(afe->regmap, ETDM_IN5_CON2,
IN_CLK_SRC_MASK, IN_CLK_SRC(APLL_CLK));
/* set ETDM_IN5_CON3 */
regmap_update_bits(afe->regmap, ETDM_IN5_CON3,
IN_SEL_FS_MASK, IN_SEL_FS(etdm_rate));
/* set ETDM_IN5_CON4 */
regmap_update_bits(afe->regmap, ETDM_IN5_CON4,
IN_RELATCH_MASK, IN_RELATCH(afe_rate));
break;
default:
break;
}
return 0;
}
static int mtk_dai_etdm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_PLAYBACK);
mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_CAPTURE);
return 0;
}
static int mtk_dai_etdm_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
dev_dbg(afe->dev, "%s(), cmd %d, dai id %d\n", __func__, cmd, dai->id);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
regmap_update_bits(afe->regmap, ETDM_IN5_CON0, ETDM_EN_MASK,
ETDM_EN);
regmap_update_bits(afe->regmap, ETDM_OUT5_CON0, ETDM_EN_MASK,
ETDM_EN);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
regmap_update_bits(afe->regmap, ETDM_IN5_CON0, ETDM_EN_MASK,
0);
regmap_update_bits(afe->regmap, ETDM_OUT5_CON0, ETDM_EN_MASK,
0);
break;
default:
break;
}
return 0;
}
static int mtk_dai_etdm_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt7986_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_etdm_priv *etdm_data;
void *priv_data;
switch (dai->id) {
case MT7986_DAI_ETDM:
break;
default:
dev_warn(afe->dev, "%s(), id %d not support\n",
__func__, dai->id);
return -EINVAL;
}
priv_data = devm_kzalloc(afe->dev, sizeof(struct mtk_dai_etdm_priv),
GFP_KERNEL);
if (!priv_data)
return -ENOMEM;
afe_priv->dai_priv[dai->id] = priv_data;
etdm_data = afe_priv->dai_priv[dai->id];
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
etdm_data->format = MTK_DAI_ETDM_FORMAT_I2S;
break;
case SND_SOC_DAIFMT_DSP_A:
etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPA;
break;
case SND_SOC_DAIFMT_DSP_B:
etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPB;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
etdm_data->bck_inv = false;
etdm_data->lrck_inv = false;
break;
case SND_SOC_DAIFMT_NB_IF:
etdm_data->bck_inv = false;
etdm_data->lrck_inv = true;
break;
case SND_SOC_DAIFMT_IB_NF:
etdm_data->bck_inv = true;
etdm_data->lrck_inv = false;
break;
case SND_SOC_DAIFMT_IB_IF:
etdm_data->bck_inv = true;
etdm_data->lrck_inv = true;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
etdm_data->slave_mode = true;
break;
case SND_SOC_DAIFMT_CBS_CFS:
etdm_data->slave_mode = false;
break;
default:
return -EINVAL;
}
return 0;
}
static const struct snd_soc_dai_ops mtk_dai_etdm_ops = {
.startup = mtk_dai_etdm_startup,
.shutdown = mtk_dai_etdm_shutdown,
.hw_params = mtk_dai_etdm_hw_params,
.trigger = mtk_dai_etdm_trigger,
.set_fmt = mtk_dai_etdm_set_fmt,
};
/* dai driver */
#define MTK_ETDM_RATES (SNDRV_PCM_RATE_8000_48000 |\
SNDRV_PCM_RATE_88200 |\
SNDRV_PCM_RATE_96000 |\
SNDRV_PCM_RATE_176400 |\
SNDRV_PCM_RATE_192000)
#define MTK_ETDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver mtk_dai_etdm_driver[] = {
{
.name = "ETDM",
.id = MT7986_DAI_ETDM,
.capture = {
.stream_name = "ETDM Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_ETDM_RATES,
.formats = MTK_ETDM_FORMATS,
},
.playback = {
.stream_name = "ETDM Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_ETDM_RATES,
.formats = MTK_ETDM_FORMATS,
},
.ops = &mtk_dai_etdm_ops,
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
},
};
int mt7986_dai_etdm_register(struct mtk_base_afe *afe)
{
struct mtk_base_afe_dai *dai;
dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
if (!dai)
return -ENOMEM;
list_add(&dai->list, &afe->sub_dais);
dai->dai_drivers = mtk_dai_etdm_driver;
dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_etdm_driver);
dai->dapm_widgets = mtk_dai_etdm_widgets;
dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_etdm_widgets);
dai->dapm_routes = mtk_dai_etdm_routes;
dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_etdm_routes);
return 0;
}
| linux-master | sound/soc/mediatek/mt7986/mt7986-dai-etdm.c |
// SPDX-License-Identifier: GPL-2.0
/*
* MediaTek ALSA SoC AFE platform driver for MT7986
*
* Copyright (c) 2023 MediaTek Inc.
* Authors: Vic Wu <[email protected]>
* Maso Huang <[email protected]>
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/pm_runtime.h>
#include "mt7986-afe-common.h"
#include "mt7986-reg.h"
#include "../common/mtk-afe-platform-driver.h"
#include "../common/mtk-afe-fe-dai.h"
enum {
MTK_AFE_RATE_8K = 0,
MTK_AFE_RATE_11K = 1,
MTK_AFE_RATE_12K = 2,
MTK_AFE_RATE_16K = 4,
MTK_AFE_RATE_22K = 5,
MTK_AFE_RATE_24K = 6,
MTK_AFE_RATE_32K = 8,
MTK_AFE_RATE_44K = 9,
MTK_AFE_RATE_48K = 10,
MTK_AFE_RATE_88K = 13,
MTK_AFE_RATE_96K = 14,
MTK_AFE_RATE_176K = 17,
MTK_AFE_RATE_192K = 18,
};
enum {
CLK_INFRA_AUD_BUS_CK = 0,
CLK_INFRA_AUD_26M_CK,
CLK_INFRA_AUD_L_CK,
CLK_INFRA_AUD_AUD_CK,
CLK_INFRA_AUD_EG2_CK,
CLK_NUM
};
static const char *aud_clks[CLK_NUM] = {
[CLK_INFRA_AUD_BUS_CK] = "aud_bus_ck",
[CLK_INFRA_AUD_26M_CK] = "aud_26m_ck",
[CLK_INFRA_AUD_L_CK] = "aud_l_ck",
[CLK_INFRA_AUD_AUD_CK] = "aud_aud_ck",
[CLK_INFRA_AUD_EG2_CK] = "aud_eg2_ck",
};
unsigned int mt7986_afe_rate_transform(struct device *dev, unsigned int rate)
{
switch (rate) {
case 8000:
return MTK_AFE_RATE_8K;
case 11025:
return MTK_AFE_RATE_11K;
case 12000:
return MTK_AFE_RATE_12K;
case 16000:
return MTK_AFE_RATE_16K;
case 22050:
return MTK_AFE_RATE_22K;
case 24000:
return MTK_AFE_RATE_24K;
case 32000:
return MTK_AFE_RATE_32K;
case 44100:
return MTK_AFE_RATE_44K;
case 48000:
return MTK_AFE_RATE_48K;
case 88200:
return MTK_AFE_RATE_88K;
case 96000:
return MTK_AFE_RATE_96K;
case 176400:
return MTK_AFE_RATE_176K;
case 192000:
return MTK_AFE_RATE_192K;
default:
dev_warn(dev, "%s(), rate %u invalid, using %d!!!\n",
__func__, rate, MTK_AFE_RATE_48K);
return MTK_AFE_RATE_48K;
}
}
static const struct snd_pcm_hardware mt7986_afe_hardware = {
.info = SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_MMAP_VALID,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE |
SNDRV_PCM_FMTBIT_S32_LE,
.period_bytes_min = 256,
.period_bytes_max = 4 * 48 * 1024,
.periods_min = 2,
.periods_max = 256,
.buffer_bytes_max = 8 * 48 * 1024,
.fifo_size = 0,
};
static int mt7986_memif_fs(struct snd_pcm_substream *substream,
unsigned int rate)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
return mt7986_afe_rate_transform(afe->dev, rate);
}
static int mt7986_irq_fs(struct snd_pcm_substream *substream,
unsigned int rate)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
return mt7986_afe_rate_transform(afe->dev, rate);
}
#define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\
SNDRV_PCM_RATE_88200 |\
SNDRV_PCM_RATE_96000 |\
SNDRV_PCM_RATE_176400 |\
SNDRV_PCM_RATE_192000)
#define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver mt7986_memif_dai_driver[] = {
/* FE DAIs: memory intefaces to CPU */
{
.name = "DL1",
.id = MT7986_MEMIF_DL1,
.playback = {
.stream_name = "DL1",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_afe_fe_ops,
},
{
.name = "UL1",
.id = MT7986_MEMIF_VUL12,
.capture = {
.stream_name = "UL1",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_afe_fe_ops,
},
};
static const struct snd_kcontrol_new o018_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I150_Switch", AFE_CONN018_4, 22, 1, 0),
};
static const struct snd_kcontrol_new o019_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I151_Switch", AFE_CONN019_4, 23, 1, 0),
};
static const struct snd_soc_dapm_widget mt7986_memif_widgets[] = {
/* DL */
SND_SOC_DAPM_MIXER("I032", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I033", SND_SOC_NOPM, 0, 0, NULL, 0),
/* UL */
SND_SOC_DAPM_MIXER("O018", SND_SOC_NOPM, 0, 0,
o018_mix, ARRAY_SIZE(o018_mix)),
SND_SOC_DAPM_MIXER("O019", SND_SOC_NOPM, 0, 0,
o019_mix, ARRAY_SIZE(o019_mix)),
};
static const struct snd_soc_dapm_route mt7986_memif_routes[] = {
{"I032", NULL, "DL1"},
{"I033", NULL, "DL1"},
{"UL1", NULL, "O018"},
{"UL1", NULL, "O019"},
{"O018", "I150_Switch", "I150"},
{"O019", "I151_Switch", "I151"},
};
static const struct snd_soc_component_driver mt7986_afe_pcm_dai_component = {
.name = "mt7986-afe-pcm-dai",
};
static const struct mtk_base_memif_data memif_data[MT7986_MEMIF_NUM] = {
[MT7986_MEMIF_DL1] = {
.name = "DL1",
.id = MT7986_MEMIF_DL1,
.reg_ofs_base = AFE_DL0_BASE,
.reg_ofs_cur = AFE_DL0_CUR,
.reg_ofs_end = AFE_DL0_END,
.reg_ofs_base_msb = AFE_DL0_BASE_MSB,
.reg_ofs_cur_msb = AFE_DL0_CUR_MSB,
.reg_ofs_end_msb = AFE_DL0_END_MSB,
.fs_reg = AFE_DL0_CON0,
.fs_shift = DL0_MODE_SFT,
.fs_maskbit = DL0_MODE_MASK,
.mono_reg = AFE_DL0_CON0,
.mono_shift = DL0_MONO_SFT,
.enable_reg = AFE_DL0_CON0,
.enable_shift = DL0_ON_SFT,
.hd_reg = AFE_DL0_CON0,
.hd_shift = DL0_HD_MODE_SFT,
.hd_align_reg = AFE_DL0_CON0,
.hd_align_mshift = DL0_HALIGN_SFT,
.pbuf_reg = AFE_DL0_CON0,
.pbuf_shift = DL0_PBUF_SIZE_SFT,
.minlen_reg = AFE_DL0_CON0,
.minlen_shift = DL0_MINLEN_SFT,
},
[MT7986_MEMIF_VUL12] = {
.name = "VUL12",
.id = MT7986_MEMIF_VUL12,
.reg_ofs_base = AFE_VUL0_BASE,
.reg_ofs_cur = AFE_VUL0_CUR,
.reg_ofs_end = AFE_VUL0_END,
.reg_ofs_base_msb = AFE_VUL0_BASE_MSB,
.reg_ofs_cur_msb = AFE_VUL0_CUR_MSB,
.reg_ofs_end_msb = AFE_VUL0_END_MSB,
.fs_reg = AFE_VUL0_CON0,
.fs_shift = VUL0_MODE_SFT,
.fs_maskbit = VUL0_MODE_MASK,
.mono_reg = AFE_VUL0_CON0,
.mono_shift = VUL0_MONO_SFT,
.enable_reg = AFE_VUL0_CON0,
.enable_shift = VUL0_ON_SFT,
.hd_reg = AFE_VUL0_CON0,
.hd_shift = VUL0_HD_MODE_SFT,
.hd_align_reg = AFE_VUL0_CON0,
.hd_align_mshift = VUL0_HALIGN_SFT,
},
};
static const struct mtk_base_irq_data irq_data[MT7986_IRQ_NUM] = {
[MT7986_IRQ_0] = {
.id = MT7986_IRQ_0,
.irq_cnt_reg = AFE_IRQ0_MCU_CFG1,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ0_MCU_CFG0,
.irq_fs_shift = IRQ_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ0_MCU_CFG0,
.irq_en_shift = IRQ_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ0_MCU_CLR_SFT,
},
[MT7986_IRQ_1] = {
.id = MT7986_IRQ_1,
.irq_cnt_reg = AFE_IRQ1_MCU_CFG1,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ1_MCU_CFG0,
.irq_fs_shift = IRQ_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ1_MCU_CFG0,
.irq_en_shift = IRQ_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ1_MCU_CLR_SFT,
},
[MT7986_IRQ_2] = {
.id = MT7986_IRQ_2,
.irq_cnt_reg = AFE_IRQ2_MCU_CFG1,
.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
.irq_fs_reg = AFE_IRQ2_MCU_CFG0,
.irq_fs_shift = IRQ_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ2_MCU_CFG0,
.irq_en_shift = IRQ_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ2_MCU_CLR_SFT,
},
};
static bool mt7986_is_volatile_reg(struct device *dev, unsigned int reg)
{
/*
* Those auto-gen regs are read-only, so put it as volatile because
* volatile registers cannot be cached, which means that they cannot
* be set when power is off
*/
switch (reg) {
case AFE_DL0_CUR_MSB:
case AFE_DL0_CUR:
case AFE_DL0_RCH_MON:
case AFE_DL0_LCH_MON:
case AFE_VUL0_CUR_MSB:
case AFE_VUL0_CUR:
case AFE_IRQ_MCU_STATUS:
case AFE_MEMIF_RD_MON:
case AFE_MEMIF_WR_MON:
return true;
default:
return false;
};
}
static const struct regmap_config mt7986_afe_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.volatile_reg = mt7986_is_volatile_reg,
.max_register = AFE_MAX_REGISTER,
.num_reg_defaults_raw = ((AFE_MAX_REGISTER / 4) + 1),
};
static int mt7986_init_clock(struct mtk_base_afe *afe)
{
struct mt7986_afe_private *afe_priv = afe->platform_priv;
int ret, i;
afe_priv->clks = devm_kcalloc(afe->dev, CLK_NUM,
sizeof(*afe_priv->clks), GFP_KERNEL);
if (!afe_priv->clks)
return -ENOMEM;
afe_priv->num_clks = CLK_NUM;
for (i = 0; i < afe_priv->num_clks; i++)
afe_priv->clks[i].id = aud_clks[i];
ret = devm_clk_bulk_get(afe->dev, afe_priv->num_clks, afe_priv->clks);
if (ret)
return dev_err_probe(afe->dev, ret, "Failed to get clocks\n");
return 0;
}
static irqreturn_t mt7986_afe_irq_handler(int irq_id, void *dev)
{
struct mtk_base_afe *afe = dev;
struct mtk_base_afe_irq *irq;
u32 mcu_en, status, status_mcu;
int i, ret;
irqreturn_t irq_ret = IRQ_HANDLED;
/* get irq that is sent to MCU */
regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &mcu_en);
ret = regmap_read(afe->regmap, AFE_IRQ_MCU_STATUS, &status);
/* only care IRQ which is sent to MCU */
status_mcu = status & mcu_en & AFE_IRQ_STATUS_BITS;
if (ret || status_mcu == 0) {
dev_err(afe->dev, "%s(), irq status err, ret %d, status 0x%x, mcu_en 0x%x\n",
__func__, ret, status, mcu_en);
irq_ret = IRQ_NONE;
goto err_irq;
}
for (i = 0; i < MT7986_MEMIF_NUM; i++) {
struct mtk_base_afe_memif *memif = &afe->memif[i];
if (!memif->substream)
continue;
if (memif->irq_usage < 0)
continue;
irq = &afe->irqs[memif->irq_usage];
if (status_mcu & (1 << irq->irq_data->irq_en_shift))
snd_pcm_period_elapsed(memif->substream);
}
err_irq:
/* clear irq */
regmap_write(afe->regmap, AFE_IRQ_MCU_CLR, status_mcu);
return irq_ret;
}
static int mt7986_afe_runtime_suspend(struct device *dev)
{
struct mtk_base_afe *afe = dev_get_drvdata(dev);
struct mt7986_afe_private *afe_priv = afe->platform_priv;
if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
goto skip_regmap;
/* disable clk*/
regmap_update_bits(afe->regmap, AUDIO_TOP_CON4, 0x3fff, 0x3fff);
regmap_update_bits(afe->regmap, AUDIO_ENGEN_CON0, AUD_APLL2_EN_MASK, 0);
regmap_update_bits(afe->regmap, AUDIO_ENGEN_CON0, AUD_26M_EN_MASK, 0);
/* make sure all irq status are cleared, twice intended */
regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CLR, 0xffff, 0xffff);
skip_regmap:
clk_bulk_disable_unprepare(afe_priv->num_clks, afe_priv->clks);
return 0;
}
static int mt7986_afe_runtime_resume(struct device *dev)
{
struct mtk_base_afe *afe = dev_get_drvdata(dev);
struct mt7986_afe_private *afe_priv = afe->platform_priv;
int ret;
ret = clk_bulk_prepare_enable(afe_priv->num_clks, afe_priv->clks);
if (ret)
return dev_err_probe(afe->dev, ret, "Failed to enable clocks\n");
if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
return 0;
/* enable clk*/
regmap_update_bits(afe->regmap, AUDIO_TOP_CON4, 0x3fff, 0);
regmap_update_bits(afe->regmap, AUDIO_ENGEN_CON0, AUD_APLL2_EN_MASK,
AUD_APLL2_EN);
regmap_update_bits(afe->regmap, AUDIO_ENGEN_CON0, AUD_26M_EN_MASK,
AUD_26M_EN);
return 0;
}
static int mt7986_afe_component_probe(struct snd_soc_component *component)
{
return mtk_afe_add_sub_dai_control(component);
}
static const struct snd_soc_component_driver mt7986_afe_component = {
.name = AFE_PCM_NAME,
.probe = mt7986_afe_component_probe,
.pointer = mtk_afe_pcm_pointer,
.pcm_construct = mtk_afe_pcm_new,
};
static int mt7986_dai_memif_register(struct mtk_base_afe *afe)
{
struct mtk_base_afe_dai *dai;
dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
if (!dai)
return -ENOMEM;
list_add(&dai->list, &afe->sub_dais);
dai->dai_drivers = mt7986_memif_dai_driver;
dai->num_dai_drivers = ARRAY_SIZE(mt7986_memif_dai_driver);
dai->dapm_widgets = mt7986_memif_widgets;
dai->num_dapm_widgets = ARRAY_SIZE(mt7986_memif_widgets);
dai->dapm_routes = mt7986_memif_routes;
dai->num_dapm_routes = ARRAY_SIZE(mt7986_memif_routes);
return 0;
}
typedef int (*dai_register_cb)(struct mtk_base_afe *);
static const dai_register_cb dai_register_cbs[] = {
mt7986_dai_etdm_register,
mt7986_dai_memif_register,
};
static int mt7986_afe_pcm_dev_probe(struct platform_device *pdev)
{
struct mtk_base_afe *afe;
struct mt7986_afe_private *afe_priv;
struct device *dev;
int i, irq_id, ret;
afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
if (!afe)
return -ENOMEM;
platform_set_drvdata(pdev, afe);
afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),
GFP_KERNEL);
if (!afe->platform_priv)
return -ENOMEM;
afe_priv = afe->platform_priv;
afe->dev = &pdev->dev;
dev = afe->dev;
afe->base_addr = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(afe->base_addr))
return PTR_ERR(afe->base_addr);
/* initial audio related clock */
ret = mt7986_init_clock(afe);
if (ret)
return dev_err_probe(dev, ret, "Cannot initialize clocks\n");
ret = devm_pm_runtime_enable(dev);
if (ret)
return ret;
/* enable clock for regcache get default value from hw */
afe_priv->pm_runtime_bypass_reg_ctl = true;
pm_runtime_get_sync(&pdev->dev);
afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr,
&mt7986_afe_regmap_config);
pm_runtime_put_sync(&pdev->dev);
if (IS_ERR(afe->regmap))
return PTR_ERR(afe->regmap);
afe_priv->pm_runtime_bypass_reg_ctl = false;
/* init memif */
afe->memif_size = MT7986_MEMIF_NUM;
afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),
GFP_KERNEL);
if (!afe->memif)
return -ENOMEM;
for (i = 0; i < afe->memif_size; i++) {
afe->memif[i].data = &memif_data[i];
afe->memif[i].irq_usage = -1;
}
mutex_init(&afe->irq_alloc_lock);
/* irq initialize */
afe->irqs_size = MT7986_IRQ_NUM;
afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
GFP_KERNEL);
if (!afe->irqs)
return -ENOMEM;
for (i = 0; i < afe->irqs_size; i++)
afe->irqs[i].irq_data = &irq_data[i];
/* request irq */
irq_id = platform_get_irq(pdev, 0);
if (irq_id < 0) {
ret = irq_id;
return dev_err_probe(dev, ret, "No irq found\n");
}
ret = devm_request_irq(dev, irq_id, mt7986_afe_irq_handler,
IRQF_TRIGGER_NONE, "asys-isr", (void *)afe);
if (ret)
return dev_err_probe(dev, ret, "Failed to request irq for asys-isr\n");
/* init sub_dais */
INIT_LIST_HEAD(&afe->sub_dais);
for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) {
ret = dai_register_cbs[i](afe);
if (ret)
return dev_err_probe(dev, ret, "DAI register failed, i: %d\n", i);
}
/* init dai_driver and component_driver */
ret = mtk_afe_combine_sub_dai(afe);
if (ret)
return dev_err_probe(dev, ret, "mtk_afe_combine_sub_dai fail\n");
afe->mtk_afe_hardware = &mt7986_afe_hardware;
afe->memif_fs = mt7986_memif_fs;
afe->irq_fs = mt7986_irq_fs;
afe->runtime_resume = mt7986_afe_runtime_resume;
afe->runtime_suspend = mt7986_afe_runtime_suspend;
/* register component */
ret = devm_snd_soc_register_component(&pdev->dev,
&mt7986_afe_component,
NULL, 0);
if (ret)
return dev_err_probe(dev, ret, "Cannot register AFE component\n");
ret = devm_snd_soc_register_component(afe->dev,
&mt7986_afe_pcm_dai_component,
afe->dai_drivers,
afe->num_dai_drivers);
if (ret)
return dev_err_probe(dev, ret, "Cannot register PCM DAI component\n");
return 0;
}
static void mt7986_afe_pcm_dev_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
if (!pm_runtime_status_suspended(&pdev->dev))
mt7986_afe_runtime_suspend(&pdev->dev);
}
static const struct of_device_id mt7986_afe_pcm_dt_match[] = {
{ .compatible = "mediatek,mt7986-afe" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mt7986_afe_pcm_dt_match);
static const struct dev_pm_ops mt7986_afe_pm_ops = {
SET_RUNTIME_PM_OPS(mt7986_afe_runtime_suspend,
mt7986_afe_runtime_resume, NULL)
};
static struct platform_driver mt7986_afe_pcm_driver = {
.driver = {
.name = "mt7986-audio",
.of_match_table = mt7986_afe_pcm_dt_match,
.pm = &mt7986_afe_pm_ops,
},
.probe = mt7986_afe_pcm_dev_probe,
.remove_new = mt7986_afe_pcm_dev_remove,
};
module_platform_driver(mt7986_afe_pcm_driver);
MODULE_DESCRIPTION("MediaTek SoC AFE platform driver for ALSA MT7986");
MODULE_AUTHOR("Vic Wu <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/mediatek/mt7986/mt7986-afe-pcm.c |
// SPDX-License-Identifier: GPL-2.0
//
// mt8183-mt6358.c --
// MT8183-MT6358-TS3A227-MAX98357 ALSA SoC machine driver
//
// Copyright (c) 2018 MediaTek Inc.
// Author: Shunli Wang <[email protected]>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/pinctrl/consumer.h>
#include <sound/jack.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include "../../codecs/rt1015.h"
#include "../../codecs/ts3a227e.h"
#include "../common/mtk-afe-platform-driver.h"
#include "mt8183-afe-common.h"
#define RT1015_CODEC_DAI "rt1015-aif"
#define RT1015_DEV0_NAME "rt1015.6-0028"
#define RT1015_DEV1_NAME "rt1015.6-0029"
enum PINCTRL_PIN_STATE {
PIN_STATE_DEFAULT = 0,
PIN_TDM_OUT_ON,
PIN_TDM_OUT_OFF,
PIN_WOV,
PIN_STATE_MAX
};
static const char * const mt8183_pin_str[PIN_STATE_MAX] = {
"default", "aud_tdm_out_on", "aud_tdm_out_off", "wov",
};
struct mt8183_mt6358_ts3a227_max98357_priv {
struct pinctrl *pinctrl;
struct pinctrl_state *pin_states[PIN_STATE_MAX];
struct snd_soc_jack headset_jack, hdmi_jack;
};
static int mt8183_mt6358_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
unsigned int rate = params_rate(params);
unsigned int mclk_fs_ratio = 128;
unsigned int mclk_fs = rate * mclk_fs_ratio;
return snd_soc_dai_set_sysclk(asoc_rtd_to_cpu(rtd, 0),
0, mclk_fs, SND_SOC_CLOCK_OUT);
}
static const struct snd_soc_ops mt8183_mt6358_i2s_ops = {
.hw_params = mt8183_mt6358_i2s_hw_params,
};
static int
mt8183_mt6358_rt1015_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
unsigned int rate = params_rate(params);
unsigned int mclk_fs_ratio = 128;
unsigned int mclk_fs = rate * mclk_fs_ratio;
struct snd_soc_card *card = rtd->card;
struct snd_soc_dai *codec_dai;
int ret, i;
for_each_rtd_codec_dais(rtd, i, codec_dai) {
ret = snd_soc_dai_set_pll(codec_dai, 0, RT1015_PLL_S_BCLK,
rate * 64, rate * 256);
if (ret < 0) {
dev_err(card->dev, "failed to set pll\n");
return ret;
}
ret = snd_soc_dai_set_sysclk(codec_dai, RT1015_SCLK_S_PLL,
rate * 256, SND_SOC_CLOCK_IN);
if (ret < 0) {
dev_err(card->dev, "failed to set sysclk\n");
return ret;
}
}
return snd_soc_dai_set_sysclk(asoc_rtd_to_cpu(rtd, 0),
0, mclk_fs, SND_SOC_CLOCK_OUT);
}
static const struct snd_soc_ops mt8183_mt6358_rt1015_i2s_ops = {
.hw_params = mt8183_mt6358_rt1015_i2s_hw_params,
};
static int mt8183_i2s_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
struct snd_pcm_hw_params *params)
{
dev_dbg(rtd->dev, "%s(), fix format to S32_LE\n", __func__);
/* fix BE i2s format to S32_LE, clean param mask first */
snd_mask_reset_range(hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT),
0, (__force unsigned int)SNDRV_PCM_FORMAT_LAST);
params_set_format(params, SNDRV_PCM_FORMAT_S32_LE);
return 0;
}
static int mt8183_rt1015_i2s_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
struct snd_pcm_hw_params *params)
{
dev_dbg(rtd->dev, "%s(), fix format to S24_LE\n", __func__);
/* fix BE i2s format to S24_LE, clean param mask first */
snd_mask_reset_range(hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT),
0, (__force unsigned int)SNDRV_PCM_FORMAT_LAST);
params_set_format(params, SNDRV_PCM_FORMAT_S24_LE);
return 0;
}
static int
mt8183_mt6358_startup(struct snd_pcm_substream *substream)
{
static const unsigned int rates[] = {
48000,
};
static const struct snd_pcm_hw_constraint_list constraints_rates = {
.count = ARRAY_SIZE(rates),
.list = rates,
.mask = 0,
};
static const unsigned int channels[] = {
2,
};
static const struct snd_pcm_hw_constraint_list constraints_channels = {
.count = ARRAY_SIZE(channels),
.list = channels,
.mask = 0,
};
struct snd_pcm_runtime *runtime = substream->runtime;
snd_pcm_hw_constraint_list(runtime, 0,
SNDRV_PCM_HW_PARAM_RATE, &constraints_rates);
runtime->hw.channels_max = 2;
snd_pcm_hw_constraint_list(runtime, 0,
SNDRV_PCM_HW_PARAM_CHANNELS,
&constraints_channels);
runtime->hw.formats = SNDRV_PCM_FMTBIT_S16_LE;
snd_pcm_hw_constraint_msbits(runtime, 0, 16, 16);
return 0;
}
static const struct snd_soc_ops mt8183_mt6358_ops = {
.startup = mt8183_mt6358_startup,
};
static int
mt8183_mt6358_ts3a227_max98357_bt_sco_startup(
struct snd_pcm_substream *substream)
{
static const unsigned int rates[] = {
8000, 16000
};
static const struct snd_pcm_hw_constraint_list constraints_rates = {
.count = ARRAY_SIZE(rates),
.list = rates,
.mask = 0,
};
static const unsigned int channels[] = {
1,
};
static const struct snd_pcm_hw_constraint_list constraints_channels = {
.count = ARRAY_SIZE(channels),
.list = channels,
.mask = 0,
};
struct snd_pcm_runtime *runtime = substream->runtime;
snd_pcm_hw_constraint_list(runtime, 0,
SNDRV_PCM_HW_PARAM_RATE, &constraints_rates);
runtime->hw.channels_max = 1;
snd_pcm_hw_constraint_list(runtime, 0,
SNDRV_PCM_HW_PARAM_CHANNELS,
&constraints_channels);
runtime->hw.formats = SNDRV_PCM_FMTBIT_S16_LE;
snd_pcm_hw_constraint_msbits(runtime, 0, 16, 16);
return 0;
}
static const struct snd_soc_ops mt8183_mt6358_ts3a227_max98357_bt_sco_ops = {
.startup = mt8183_mt6358_ts3a227_max98357_bt_sco_startup,
};
/* FE */
SND_SOC_DAILINK_DEFS(playback1,
DAILINK_COMP_ARRAY(COMP_CPU("DL1")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(playback2,
DAILINK_COMP_ARRAY(COMP_CPU("DL2")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(playback3,
DAILINK_COMP_ARRAY(COMP_CPU("DL3")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture1,
DAILINK_COMP_ARRAY(COMP_CPU("UL1")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture2,
DAILINK_COMP_ARRAY(COMP_CPU("UL2")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture3,
DAILINK_COMP_ARRAY(COMP_CPU("UL3")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture_mono,
DAILINK_COMP_ARRAY(COMP_CPU("UL_MONO_1")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(playback_hdmi,
DAILINK_COMP_ARRAY(COMP_CPU("HDMI")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(wake_on_voice,
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
/* BE */
SND_SOC_DAILINK_DEFS(primary_codec,
DAILINK_COMP_ARRAY(COMP_CPU("ADDA")),
DAILINK_COMP_ARRAY(COMP_CODEC("mt6358-sound", "mt6358-snd-codec-aif1")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(pcm1,
DAILINK_COMP_ARRAY(COMP_CPU("PCM 1")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(pcm2,
DAILINK_COMP_ARRAY(COMP_CPU("PCM 2")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(i2s0,
DAILINK_COMP_ARRAY(COMP_CPU("I2S0")),
DAILINK_COMP_ARRAY(COMP_CODEC("bt-sco", "bt-sco-pcm-wb")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(i2s1,
DAILINK_COMP_ARRAY(COMP_CPU("I2S1")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(i2s2,
DAILINK_COMP_ARRAY(COMP_CPU("I2S2")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(i2s3_max98357a,
DAILINK_COMP_ARRAY(COMP_CPU("I2S3")),
DAILINK_COMP_ARRAY(COMP_CODEC("max98357a", "HiFi")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(i2s3_rt1015,
DAILINK_COMP_ARRAY(COMP_CPU("I2S3")),
DAILINK_COMP_ARRAY(COMP_CODEC(RT1015_DEV0_NAME, RT1015_CODEC_DAI),
COMP_CODEC(RT1015_DEV1_NAME, RT1015_CODEC_DAI)),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(i2s3_rt1015p,
DAILINK_COMP_ARRAY(COMP_CPU("I2S3")),
DAILINK_COMP_ARRAY(COMP_CODEC("rt1015p", "HiFi")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(i2s5,
DAILINK_COMP_ARRAY(COMP_CPU("I2S5")),
DAILINK_COMP_ARRAY(COMP_CODEC("bt-sco", "bt-sco-pcm-wb")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(tdm,
DAILINK_COMP_ARRAY(COMP_CPU("TDM")),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "i2s-hifi")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
static int mt8183_mt6358_tdm_startup(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct mt8183_mt6358_ts3a227_max98357_priv *priv =
snd_soc_card_get_drvdata(rtd->card);
int ret;
if (IS_ERR(priv->pin_states[PIN_TDM_OUT_ON]))
return PTR_ERR(priv->pin_states[PIN_TDM_OUT_ON]);
ret = pinctrl_select_state(priv->pinctrl,
priv->pin_states[PIN_TDM_OUT_ON]);
if (ret)
dev_err(rtd->card->dev, "%s failed to select state %d\n",
__func__, ret);
return ret;
}
static void mt8183_mt6358_tdm_shutdown(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct mt8183_mt6358_ts3a227_max98357_priv *priv =
snd_soc_card_get_drvdata(rtd->card);
int ret;
if (IS_ERR(priv->pin_states[PIN_TDM_OUT_OFF]))
return;
ret = pinctrl_select_state(priv->pinctrl,
priv->pin_states[PIN_TDM_OUT_OFF]);
if (ret)
dev_err(rtd->card->dev, "%s failed to select state %d\n",
__func__, ret);
}
static const struct snd_soc_ops mt8183_mt6358_tdm_ops = {
.startup = mt8183_mt6358_tdm_startup,
.shutdown = mt8183_mt6358_tdm_shutdown,
};
static int
mt8183_mt6358_ts3a227_max98357_wov_startup(
struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_card *card = rtd->card;
struct mt8183_mt6358_ts3a227_max98357_priv *priv =
snd_soc_card_get_drvdata(card);
return pinctrl_select_state(priv->pinctrl,
priv->pin_states[PIN_WOV]);
}
static void
mt8183_mt6358_ts3a227_max98357_wov_shutdown(
struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_card *card = rtd->card;
struct mt8183_mt6358_ts3a227_max98357_priv *priv =
snd_soc_card_get_drvdata(card);
int ret;
ret = pinctrl_select_state(priv->pinctrl,
priv->pin_states[PIN_STATE_DEFAULT]);
if (ret)
dev_err(card->dev, "%s failed to select state %d\n",
__func__, ret);
}
static const struct snd_soc_ops mt8183_mt6358_ts3a227_max98357_wov_ops = {
.startup = mt8183_mt6358_ts3a227_max98357_wov_startup,
.shutdown = mt8183_mt6358_ts3a227_max98357_wov_shutdown,
};
static int
mt8183_mt6358_ts3a227_max98357_hdmi_init(struct snd_soc_pcm_runtime *rtd)
{
struct mt8183_mt6358_ts3a227_max98357_priv *priv =
snd_soc_card_get_drvdata(rtd->card);
int ret;
ret = snd_soc_card_jack_new(rtd->card, "HDMI Jack", SND_JACK_LINEOUT,
&priv->hdmi_jack);
if (ret)
return ret;
return snd_soc_component_set_jack(asoc_rtd_to_codec(rtd, 0)->component,
&priv->hdmi_jack, NULL);
}
static int mt8183_bt_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_component *cmpnt_afe =
snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt_afe);
int ret;
ret = mt8183_dai_i2s_set_share(afe, "I2S5", "I2S0");
if (ret) {
dev_err(rtd->dev, "Failed to set up shared clocks\n");
return ret;
}
return 0;
}
static int mt8183_i2s2_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_component *cmpnt_afe =
snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt_afe);
int ret;
ret = mt8183_dai_i2s_set_share(afe, "I2S2", "I2S3");
if (ret) {
dev_err(rtd->dev, "Failed to set up shared clocks\n");
return ret;
}
return 0;
}
static struct snd_soc_dai_link mt8183_mt6358_ts3a227_dai_links[] = {
/* FE */
{
.name = "Playback_1",
.stream_name = "Playback_1",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
.ops = &mt8183_mt6358_ops,
SND_SOC_DAILINK_REG(playback1),
},
{
.name = "Playback_2",
.stream_name = "Playback_2",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
.ops = &mt8183_mt6358_ts3a227_max98357_bt_sco_ops,
SND_SOC_DAILINK_REG(playback2),
},
{
.name = "Playback_3",
.stream_name = "Playback_3",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(playback3),
},
{
.name = "Capture_1",
.stream_name = "Capture_1",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_capture = 1,
.ops = &mt8183_mt6358_ts3a227_max98357_bt_sco_ops,
SND_SOC_DAILINK_REG(capture1),
},
{
.name = "Capture_2",
.stream_name = "Capture_2",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(capture2),
},
{
.name = "Capture_3",
.stream_name = "Capture_3",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_capture = 1,
.ops = &mt8183_mt6358_ops,
SND_SOC_DAILINK_REG(capture3),
},
{
.name = "Capture_Mono_1",
.stream_name = "Capture_Mono_1",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(capture_mono),
},
{
.name = "Playback_HDMI",
.stream_name = "Playback_HDMI",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(playback_hdmi),
},
{
.name = "Wake on Voice",
.stream_name = "Wake on Voice",
.ignore_suspend = 1,
.ignore = 1,
SND_SOC_DAILINK_REG(wake_on_voice),
.ops = &mt8183_mt6358_ts3a227_max98357_wov_ops,
},
/* BE */
{
.name = "Primary Codec",
.no_pcm = 1,
.dpcm_playback = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(primary_codec),
},
{
.name = "PCM 1",
.no_pcm = 1,
.dpcm_playback = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(pcm1),
},
{
.name = "PCM 2",
.no_pcm = 1,
.dpcm_playback = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(pcm2),
},
{
.name = "I2S0",
.no_pcm = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
.ops = &mt8183_mt6358_i2s_ops,
SND_SOC_DAILINK_REG(i2s0),
},
{
.name = "I2S1",
.no_pcm = 1,
.dpcm_playback = 1,
.ignore_suspend = 1,
.be_hw_params_fixup = mt8183_i2s_hw_params_fixup,
.ops = &mt8183_mt6358_i2s_ops,
SND_SOC_DAILINK_REG(i2s1),
},
{
.name = "I2S2",
.no_pcm = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
.be_hw_params_fixup = mt8183_i2s_hw_params_fixup,
.ops = &mt8183_mt6358_i2s_ops,
.init = &mt8183_i2s2_init,
SND_SOC_DAILINK_REG(i2s2),
},
{
.name = "I2S3",
.no_pcm = 1,
.dpcm_playback = 1,
.ignore_suspend = 1,
},
{
.name = "I2S5",
.no_pcm = 1,
.dpcm_playback = 1,
.ignore_suspend = 1,
.ops = &mt8183_mt6358_i2s_ops,
.init = &mt8183_bt_init,
SND_SOC_DAILINK_REG(i2s5),
},
{
.name = "TDM",
.no_pcm = 1,
.dai_fmt = SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_IB_IF |
SND_SOC_DAIFMT_CBM_CFM,
.dpcm_playback = 1,
.ignore_suspend = 1,
.be_hw_params_fixup = mt8183_i2s_hw_params_fixup,
.ops = &mt8183_mt6358_tdm_ops,
.ignore = 1,
.init = mt8183_mt6358_ts3a227_max98357_hdmi_init,
SND_SOC_DAILINK_REG(tdm),
},
};
static const
struct snd_kcontrol_new mt8183_mt6358_ts3a227_max98357_snd_controls[] = {
SOC_DAPM_PIN_SWITCH("Headphone"),
SOC_DAPM_PIN_SWITCH("Headset Mic"),
};
static const
struct snd_soc_dapm_widget mt8183_mt6358_ts3a227_max98357_dapm_widgets[] = {
SND_SOC_DAPM_HP("Headphone", NULL),
SND_SOC_DAPM_MIC("Headset Mic", NULL),
};
static struct snd_soc_jack_pin mt8183_mt6358_ts3a227_max98357_jack_pins[] = {
{
.pin = "Headphone",
.mask = SND_JACK_HEADPHONE,
},
{
.pin = "Headset Mic",
.mask = SND_JACK_MICROPHONE,
},
};
static struct snd_soc_card mt8183_mt6358_ts3a227_max98357_card = {
.name = "mt8183_mt6358_ts3a227_max98357",
.owner = THIS_MODULE,
.dai_link = mt8183_mt6358_ts3a227_dai_links,
.num_links = ARRAY_SIZE(mt8183_mt6358_ts3a227_dai_links),
.controls = mt8183_mt6358_ts3a227_max98357_snd_controls,
.num_controls = ARRAY_SIZE(mt8183_mt6358_ts3a227_max98357_snd_controls),
.dapm_widgets = mt8183_mt6358_ts3a227_max98357_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(mt8183_mt6358_ts3a227_max98357_dapm_widgets),
};
static struct snd_soc_card mt8183_mt6358_ts3a227_max98357b_card = {
.name = "mt8183_mt6358_ts3a227_max98357b",
.owner = THIS_MODULE,
.dai_link = mt8183_mt6358_ts3a227_dai_links,
.num_links = ARRAY_SIZE(mt8183_mt6358_ts3a227_dai_links),
.controls = mt8183_mt6358_ts3a227_max98357_snd_controls,
.num_controls = ARRAY_SIZE(mt8183_mt6358_ts3a227_max98357_snd_controls),
.dapm_widgets = mt8183_mt6358_ts3a227_max98357_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(mt8183_mt6358_ts3a227_max98357_dapm_widgets),
};
static struct snd_soc_codec_conf mt8183_mt6358_ts3a227_rt1015_amp_conf[] = {
{
.dlc = COMP_CODEC_CONF(RT1015_DEV0_NAME),
.name_prefix = "Left",
},
{
.dlc = COMP_CODEC_CONF(RT1015_DEV1_NAME),
.name_prefix = "Right",
},
};
static struct snd_soc_card mt8183_mt6358_ts3a227_rt1015_card = {
.name = "mt8183_mt6358_ts3a227_rt1015",
.owner = THIS_MODULE,
.dai_link = mt8183_mt6358_ts3a227_dai_links,
.num_links = ARRAY_SIZE(mt8183_mt6358_ts3a227_dai_links),
.codec_conf = mt8183_mt6358_ts3a227_rt1015_amp_conf,
.num_configs = ARRAY_SIZE(mt8183_mt6358_ts3a227_rt1015_amp_conf),
.controls = mt8183_mt6358_ts3a227_max98357_snd_controls,
.num_controls = ARRAY_SIZE(mt8183_mt6358_ts3a227_max98357_snd_controls),
.dapm_widgets = mt8183_mt6358_ts3a227_max98357_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(mt8183_mt6358_ts3a227_max98357_dapm_widgets),
};
static struct snd_soc_card mt8183_mt6358_ts3a227_rt1015p_card = {
.name = "mt8183_mt6358_ts3a227_rt1015p",
.owner = THIS_MODULE,
.dai_link = mt8183_mt6358_ts3a227_dai_links,
.num_links = ARRAY_SIZE(mt8183_mt6358_ts3a227_dai_links),
.controls = mt8183_mt6358_ts3a227_max98357_snd_controls,
.num_controls = ARRAY_SIZE(mt8183_mt6358_ts3a227_max98357_snd_controls),
.dapm_widgets = mt8183_mt6358_ts3a227_max98357_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(mt8183_mt6358_ts3a227_max98357_dapm_widgets),
};
static int
mt8183_mt6358_ts3a227_max98357_headset_init(struct snd_soc_component *component)
{
int ret;
struct mt8183_mt6358_ts3a227_max98357_priv *priv =
snd_soc_card_get_drvdata(component->card);
/* Enable Headset and 4 Buttons Jack detection */
ret = snd_soc_card_jack_new_pins(component->card,
"Headset Jack",
SND_JACK_HEADSET |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3,
&priv->headset_jack,
mt8183_mt6358_ts3a227_max98357_jack_pins,
ARRAY_SIZE(mt8183_mt6358_ts3a227_max98357_jack_pins));
if (ret)
return ret;
ret = ts3a227e_enable_jack_detect(component, &priv->headset_jack);
return ret;
}
static struct snd_soc_aux_dev mt8183_mt6358_ts3a227_max98357_headset_dev = {
.dlc = COMP_EMPTY(),
.init = mt8183_mt6358_ts3a227_max98357_headset_init,
};
static int
mt8183_mt6358_ts3a227_max98357_dev_probe(struct platform_device *pdev)
{
struct snd_soc_card *card;
struct device_node *platform_node, *ec_codec, *hdmi_codec;
struct snd_soc_dai_link *dai_link;
struct mt8183_mt6358_ts3a227_max98357_priv *priv;
int ret, i;
platform_node = of_parse_phandle(pdev->dev.of_node,
"mediatek,platform", 0);
if (!platform_node) {
dev_err(&pdev->dev, "Property 'platform' missing or invalid\n");
return -EINVAL;
}
card = (struct snd_soc_card *)of_device_get_match_data(&pdev->dev);
if (!card) {
of_node_put(platform_node);
return -EINVAL;
}
card->dev = &pdev->dev;
ec_codec = of_parse_phandle(pdev->dev.of_node, "mediatek,ec-codec", 0);
hdmi_codec = of_parse_phandle(pdev->dev.of_node,
"mediatek,hdmi-codec", 0);
for_each_card_prelinks(card, i, dai_link) {
if (ec_codec && strcmp(dai_link->name, "Wake on Voice") == 0) {
dai_link->cpus[0].name = NULL;
dai_link->cpus[0].of_node = ec_codec;
dai_link->cpus[0].dai_name = NULL;
dai_link->codecs[0].name = NULL;
dai_link->codecs[0].of_node = ec_codec;
dai_link->codecs[0].dai_name = "Wake on Voice";
dai_link->platforms[0].of_node = ec_codec;
dai_link->ignore = 0;
}
if (strcmp(dai_link->name, "I2S3") == 0) {
if (card == &mt8183_mt6358_ts3a227_max98357_card ||
card == &mt8183_mt6358_ts3a227_max98357b_card) {
dai_link->be_hw_params_fixup =
mt8183_i2s_hw_params_fixup;
dai_link->ops = &mt8183_mt6358_i2s_ops;
dai_link->cpus = i2s3_max98357a_cpus;
dai_link->num_cpus =
ARRAY_SIZE(i2s3_max98357a_cpus);
dai_link->codecs = i2s3_max98357a_codecs;
dai_link->num_codecs =
ARRAY_SIZE(i2s3_max98357a_codecs);
dai_link->platforms = i2s3_max98357a_platforms;
dai_link->num_platforms =
ARRAY_SIZE(i2s3_max98357a_platforms);
} else if (card == &mt8183_mt6358_ts3a227_rt1015_card) {
dai_link->be_hw_params_fixup =
mt8183_rt1015_i2s_hw_params_fixup;
dai_link->ops = &mt8183_mt6358_rt1015_i2s_ops;
dai_link->cpus = i2s3_rt1015_cpus;
dai_link->num_cpus =
ARRAY_SIZE(i2s3_rt1015_cpus);
dai_link->codecs = i2s3_rt1015_codecs;
dai_link->num_codecs =
ARRAY_SIZE(i2s3_rt1015_codecs);
dai_link->platforms = i2s3_rt1015_platforms;
dai_link->num_platforms =
ARRAY_SIZE(i2s3_rt1015_platforms);
} else if (card == &mt8183_mt6358_ts3a227_rt1015p_card) {
dai_link->be_hw_params_fixup =
mt8183_rt1015_i2s_hw_params_fixup;
dai_link->ops = &mt8183_mt6358_i2s_ops;
dai_link->cpus = i2s3_rt1015p_cpus;
dai_link->num_cpus =
ARRAY_SIZE(i2s3_rt1015p_cpus);
dai_link->codecs = i2s3_rt1015p_codecs;
dai_link->num_codecs =
ARRAY_SIZE(i2s3_rt1015p_codecs);
dai_link->platforms = i2s3_rt1015p_platforms;
dai_link->num_platforms =
ARRAY_SIZE(i2s3_rt1015p_platforms);
}
}
if (card == &mt8183_mt6358_ts3a227_max98357b_card) {
if (strcmp(dai_link->name, "I2S2") == 0 ||
strcmp(dai_link->name, "I2S3") == 0)
dai_link->dai_fmt = SND_SOC_DAIFMT_LEFT_J |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBM_CFM;
}
if (hdmi_codec && strcmp(dai_link->name, "TDM") == 0) {
dai_link->codecs->of_node = hdmi_codec;
dai_link->ignore = 0;
}
if (!dai_link->platforms->name)
dai_link->platforms->of_node = platform_node;
}
mt8183_mt6358_ts3a227_max98357_headset_dev.dlc.of_node =
of_parse_phandle(pdev->dev.of_node,
"mediatek,headset-codec", 0);
if (mt8183_mt6358_ts3a227_max98357_headset_dev.dlc.of_node) {
card->aux_dev = &mt8183_mt6358_ts3a227_max98357_headset_dev;
card->num_aux_devs = 1;
}
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv) {
ret = -ENOMEM;
goto out;
}
snd_soc_card_set_drvdata(card, priv);
priv->pinctrl = devm_pinctrl_get(&pdev->dev);
if (IS_ERR(priv->pinctrl)) {
dev_err(&pdev->dev, "%s devm_pinctrl_get failed\n",
__func__);
ret = PTR_ERR(priv->pinctrl);
goto out;
}
for (i = 0; i < PIN_STATE_MAX; i++) {
priv->pin_states[i] = pinctrl_lookup_state(priv->pinctrl,
mt8183_pin_str[i]);
if (IS_ERR(priv->pin_states[i])) {
ret = PTR_ERR(priv->pin_states[i]);
dev_info(&pdev->dev, "%s Can't find pin state %s %d\n",
__func__, mt8183_pin_str[i], ret);
}
}
if (!IS_ERR(priv->pin_states[PIN_TDM_OUT_OFF])) {
ret = pinctrl_select_state(priv->pinctrl,
priv->pin_states[PIN_TDM_OUT_OFF]);
if (ret)
dev_info(&pdev->dev,
"%s failed to select state %d\n",
__func__, ret);
}
if (!IS_ERR(priv->pin_states[PIN_STATE_DEFAULT])) {
ret = pinctrl_select_state(priv->pinctrl,
priv->pin_states[PIN_STATE_DEFAULT]);
if (ret)
dev_info(&pdev->dev,
"%s failed to select state %d\n",
__func__, ret);
}
ret = devm_snd_soc_register_card(&pdev->dev, card);
out:
of_node_put(platform_node);
of_node_put(ec_codec);
of_node_put(hdmi_codec);
return ret;
}
#ifdef CONFIG_OF
static const struct of_device_id mt8183_mt6358_ts3a227_max98357_dt_match[] = {
{
.compatible = "mediatek,mt8183_mt6358_ts3a227_max98357",
.data = &mt8183_mt6358_ts3a227_max98357_card,
},
{
.compatible = "mediatek,mt8183_mt6358_ts3a227_max98357b",
.data = &mt8183_mt6358_ts3a227_max98357b_card,
},
{
.compatible = "mediatek,mt8183_mt6358_ts3a227_rt1015",
.data = &mt8183_mt6358_ts3a227_rt1015_card,
},
{
.compatible = "mediatek,mt8183_mt6358_ts3a227_rt1015p",
.data = &mt8183_mt6358_ts3a227_rt1015p_card,
},
{}
};
MODULE_DEVICE_TABLE(of, mt8183_mt6358_ts3a227_max98357_dt_match);
#endif
static struct platform_driver mt8183_mt6358_ts3a227_max98357_driver = {
.driver = {
.name = "mt8183_mt6358_ts3a227",
#ifdef CONFIG_OF
.of_match_table = mt8183_mt6358_ts3a227_max98357_dt_match,
#endif
.pm = &snd_soc_pm_ops,
},
.probe = mt8183_mt6358_ts3a227_max98357_dev_probe,
};
module_platform_driver(mt8183_mt6358_ts3a227_max98357_driver);
/* Module information */
MODULE_DESCRIPTION("MT8183-MT6358-TS3A227-MAX98357 ALSA SoC machine driver");
MODULE_AUTHOR("Shunli Wang <[email protected]>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("mt8183_mt6358_ts3a227_max98357 soc card");
| linux-master | sound/soc/mediatek/mt8183/mt8183-mt6358-ts3a227-max98357.c |
// SPDX-License-Identifier: GPL-2.0
//
// MediaTek ALSA SoC Audio DAI I2S Control
//
// Copyright (c) 2018 MediaTek Inc.
// Author: KaiChieh Chuang <[email protected]>
#include <linux/bitops.h>
#include <linux/regmap.h>
#include <sound/pcm_params.h>
#include "mt8183-afe-clk.h"
#include "mt8183-afe-common.h"
#include "mt8183-interconnection.h"
#include "mt8183-reg.h"
enum {
I2S_FMT_EIAJ = 0,
I2S_FMT_I2S = 1,
};
enum {
I2S_WLEN_16_BIT = 0,
I2S_WLEN_32_BIT = 1,
};
enum {
I2S_HD_NORMAL = 0,
I2S_HD_LOW_JITTER = 1,
};
enum {
I2S1_SEL_O28_O29 = 0,
I2S1_SEL_O03_O04 = 1,
};
enum {
I2S_IN_PAD_CONNSYS = 0,
I2S_IN_PAD_IO_MUX = 1,
};
struct mtk_afe_i2s_priv {
int id;
int rate; /* for determine which apll to use */
int low_jitter_en;
int share_i2s_id;
int mclk_id;
int mclk_rate;
int mclk_apll;
int use_eiaj;
};
static unsigned int get_i2s_wlen(snd_pcm_format_t format)
{
return snd_pcm_format_physical_width(format) <= 16 ?
I2S_WLEN_16_BIT : I2S_WLEN_32_BIT;
}
#define MTK_AFE_I2S0_KCONTROL_NAME "I2S0_HD_Mux"
#define MTK_AFE_I2S1_KCONTROL_NAME "I2S1_HD_Mux"
#define MTK_AFE_I2S2_KCONTROL_NAME "I2S2_HD_Mux"
#define MTK_AFE_I2S3_KCONTROL_NAME "I2S3_HD_Mux"
#define MTK_AFE_I2S5_KCONTROL_NAME "I2S5_HD_Mux"
#define I2S0_HD_EN_W_NAME "I2S0_HD_EN"
#define I2S1_HD_EN_W_NAME "I2S1_HD_EN"
#define I2S2_HD_EN_W_NAME "I2S2_HD_EN"
#define I2S3_HD_EN_W_NAME "I2S3_HD_EN"
#define I2S5_HD_EN_W_NAME "I2S5_HD_EN"
#define I2S0_MCLK_EN_W_NAME "I2S0_MCLK_EN"
#define I2S1_MCLK_EN_W_NAME "I2S1_MCLK_EN"
#define I2S2_MCLK_EN_W_NAME "I2S2_MCLK_EN"
#define I2S3_MCLK_EN_W_NAME "I2S3_MCLK_EN"
#define I2S5_MCLK_EN_W_NAME "I2S5_MCLK_EN"
static int get_i2s_id_by_name(struct mtk_base_afe *afe,
const char *name)
{
if (strncmp(name, "I2S0", 4) == 0)
return MT8183_DAI_I2S_0;
else if (strncmp(name, "I2S1", 4) == 0)
return MT8183_DAI_I2S_1;
else if (strncmp(name, "I2S2", 4) == 0)
return MT8183_DAI_I2S_2;
else if (strncmp(name, "I2S3", 4) == 0)
return MT8183_DAI_I2S_3;
else if (strncmp(name, "I2S5", 4) == 0)
return MT8183_DAI_I2S_5;
else
return -EINVAL;
}
static struct mtk_afe_i2s_priv *get_i2s_priv_by_name(struct mtk_base_afe *afe,
const char *name)
{
struct mt8183_afe_private *afe_priv = afe->platform_priv;
int dai_id = get_i2s_id_by_name(afe, name);
if (dai_id < 0)
return NULL;
return afe_priv->dai_priv[dai_id];
}
/* low jitter control */
static const char * const mt8183_i2s_hd_str[] = {
"Normal", "Low_Jitter"
};
static const struct soc_enum mt8183_i2s_enum[] = {
SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt8183_i2s_hd_str),
mt8183_i2s_hd_str),
};
static int mt8183_i2s_hd_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mtk_afe_i2s_priv *i2s_priv;
i2s_priv = get_i2s_priv_by_name(afe, kcontrol->id.name);
if (!i2s_priv) {
dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__);
return -EINVAL;
}
ucontrol->value.integer.value[0] = i2s_priv->low_jitter_en;
return 0;
}
static int mt8183_i2s_hd_set(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mtk_afe_i2s_priv *i2s_priv;
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
int hd_en, change;
if (ucontrol->value.enumerated.item[0] >= e->items)
return -EINVAL;
hd_en = ucontrol->value.integer.value[0];
i2s_priv = get_i2s_priv_by_name(afe, kcontrol->id.name);
if (!i2s_priv) {
dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__);
return -EINVAL;
}
change = i2s_priv->low_jitter_en != hd_en;
i2s_priv->low_jitter_en = hd_en;
return change;
}
static const struct snd_kcontrol_new mtk_dai_i2s_controls[] = {
SOC_ENUM_EXT(MTK_AFE_I2S0_KCONTROL_NAME, mt8183_i2s_enum[0],
mt8183_i2s_hd_get, mt8183_i2s_hd_set),
SOC_ENUM_EXT(MTK_AFE_I2S1_KCONTROL_NAME, mt8183_i2s_enum[0],
mt8183_i2s_hd_get, mt8183_i2s_hd_set),
SOC_ENUM_EXT(MTK_AFE_I2S2_KCONTROL_NAME, mt8183_i2s_enum[0],
mt8183_i2s_hd_get, mt8183_i2s_hd_set),
SOC_ENUM_EXT(MTK_AFE_I2S3_KCONTROL_NAME, mt8183_i2s_enum[0],
mt8183_i2s_hd_get, mt8183_i2s_hd_set),
SOC_ENUM_EXT(MTK_AFE_I2S5_KCONTROL_NAME, mt8183_i2s_enum[0],
mt8183_i2s_hd_get, mt8183_i2s_hd_set),
};
/* dai component */
/* interconnection */
static const struct snd_kcontrol_new mtk_i2s3_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN0, I_DL1_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN0, I_DL2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN0, I_DL3_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN0,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN0,
I_PCM_1_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN0,
I_PCM_2_CAP_CH1, 1, 0),
};
static const struct snd_kcontrol_new mtk_i2s3_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN1, I_DL1_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN1, I_DL2_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN1, I_DL3_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN1,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN1,
I_PCM_1_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN1,
I_PCM_2_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN1,
I_PCM_1_CAP_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN1,
I_PCM_2_CAP_CH2, 1, 0),
};
static const struct snd_kcontrol_new mtk_i2s1_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN28, I_DL1_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN28, I_DL2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN28, I_DL3_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN28,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN28,
I_PCM_1_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN28,
I_PCM_2_CAP_CH1, 1, 0),
};
static const struct snd_kcontrol_new mtk_i2s1_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN29, I_DL1_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN29, I_DL2_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN29, I_DL3_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN29,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN29,
I_PCM_1_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN29,
I_PCM_2_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN29,
I_PCM_1_CAP_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN29,
I_PCM_2_CAP_CH2, 1, 0),
};
static const struct snd_kcontrol_new mtk_i2s5_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN30, I_DL1_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN30, I_DL2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN30, I_DL3_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN30,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN30,
I_PCM_1_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN30,
I_PCM_2_CAP_CH1, 1, 0),
};
static const struct snd_kcontrol_new mtk_i2s5_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN31, I_DL1_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN31, I_DL2_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN31, I_DL3_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN31,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN31,
I_PCM_1_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN31,
I_PCM_2_CAP_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN31,
I_PCM_1_CAP_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN31,
I_PCM_2_CAP_CH2, 1, 0),
};
enum {
SUPPLY_SEQ_APLL,
SUPPLY_SEQ_I2S_MCLK_EN,
SUPPLY_SEQ_I2S_HD_EN,
SUPPLY_SEQ_I2S_EN,
};
static int mtk_apll_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
if (strcmp(w->name, APLL1_W_NAME) == 0)
mt8183_apll1_enable(afe);
else
mt8183_apll2_enable(afe);
break;
case SND_SOC_DAPM_POST_PMD:
if (strcmp(w->name, APLL1_W_NAME) == 0)
mt8183_apll1_disable(afe);
else
mt8183_apll2_disable(afe);
break;
default:
break;
}
return 0;
}
static int mtk_mclk_en_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mtk_afe_i2s_priv *i2s_priv;
i2s_priv = get_i2s_priv_by_name(afe, w->name);
if (!i2s_priv) {
dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__);
return -EINVAL;
}
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
mt8183_mck_enable(afe, i2s_priv->mclk_id, i2s_priv->mclk_rate);
break;
case SND_SOC_DAPM_POST_PMD:
i2s_priv->mclk_rate = 0;
mt8183_mck_disable(afe, i2s_priv->mclk_id);
break;
default:
break;
}
return 0;
}
static const struct snd_soc_dapm_widget mtk_dai_i2s_widgets[] = {
SND_SOC_DAPM_MIXER("I2S1_CH1", SND_SOC_NOPM, 0, 0,
mtk_i2s1_ch1_mix,
ARRAY_SIZE(mtk_i2s1_ch1_mix)),
SND_SOC_DAPM_MIXER("I2S1_CH2", SND_SOC_NOPM, 0, 0,
mtk_i2s1_ch2_mix,
ARRAY_SIZE(mtk_i2s1_ch2_mix)),
SND_SOC_DAPM_MIXER("I2S3_CH1", SND_SOC_NOPM, 0, 0,
mtk_i2s3_ch1_mix,
ARRAY_SIZE(mtk_i2s3_ch1_mix)),
SND_SOC_DAPM_MIXER("I2S3_CH2", SND_SOC_NOPM, 0, 0,
mtk_i2s3_ch2_mix,
ARRAY_SIZE(mtk_i2s3_ch2_mix)),
SND_SOC_DAPM_MIXER("I2S5_CH1", SND_SOC_NOPM, 0, 0,
mtk_i2s5_ch1_mix,
ARRAY_SIZE(mtk_i2s5_ch1_mix)),
SND_SOC_DAPM_MIXER("I2S5_CH2", SND_SOC_NOPM, 0, 0,
mtk_i2s5_ch2_mix,
ARRAY_SIZE(mtk_i2s5_ch2_mix)),
/* i2s en*/
SND_SOC_DAPM_SUPPLY_S("I2S0_EN", SUPPLY_SEQ_I2S_EN,
AFE_I2S_CON, I2S_EN_SFT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY_S("I2S1_EN", SUPPLY_SEQ_I2S_EN,
AFE_I2S_CON1, I2S_EN_SFT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY_S("I2S2_EN", SUPPLY_SEQ_I2S_EN,
AFE_I2S_CON2, I2S_EN_SFT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY_S("I2S3_EN", SUPPLY_SEQ_I2S_EN,
AFE_I2S_CON3, I2S_EN_SFT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY_S("I2S5_EN", SUPPLY_SEQ_I2S_EN,
AFE_I2S_CON4, I2S5_EN_SFT, 0,
NULL, 0),
/* i2s hd en */
SND_SOC_DAPM_SUPPLY_S(I2S0_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
AFE_I2S_CON, I2S1_HD_EN_SFT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY_S(I2S1_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
AFE_I2S_CON1, I2S2_HD_EN_SFT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY_S(I2S2_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
AFE_I2S_CON2, I2S3_HD_EN_SFT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY_S(I2S3_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
AFE_I2S_CON3, I2S4_HD_EN_SFT, 0,
NULL, 0),
SND_SOC_DAPM_SUPPLY_S(I2S5_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
AFE_I2S_CON4, I2S5_HD_EN_SFT, 0,
NULL, 0),
/* i2s mclk en */
SND_SOC_DAPM_SUPPLY_S(I2S0_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
SND_SOC_NOPM, 0, 0,
mtk_mclk_en_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S(I2S1_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
SND_SOC_NOPM, 0, 0,
mtk_mclk_en_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S(I2S2_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
SND_SOC_NOPM, 0, 0,
mtk_mclk_en_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S(I2S3_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
SND_SOC_NOPM, 0, 0,
mtk_mclk_en_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S(I2S5_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
SND_SOC_NOPM, 0, 0,
mtk_mclk_en_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
/* apll */
SND_SOC_DAPM_SUPPLY_S(APLL1_W_NAME, SUPPLY_SEQ_APLL,
SND_SOC_NOPM, 0, 0,
mtk_apll_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S(APLL2_W_NAME, SUPPLY_SEQ_APLL,
SND_SOC_NOPM, 0, 0,
mtk_apll_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
};
static int mtk_afe_i2s_share_connect(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_dapm_widget *w = sink;
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mtk_afe_i2s_priv *i2s_priv;
i2s_priv = get_i2s_priv_by_name(afe, sink->name);
if (!i2s_priv) {
dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__);
return 0;
}
if (i2s_priv->share_i2s_id < 0)
return 0;
return i2s_priv->share_i2s_id == get_i2s_id_by_name(afe, source->name);
}
static int mtk_afe_i2s_hd_connect(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_dapm_widget *w = sink;
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mtk_afe_i2s_priv *i2s_priv;
i2s_priv = get_i2s_priv_by_name(afe, sink->name);
if (!i2s_priv) {
dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__);
return 0;
}
if (get_i2s_id_by_name(afe, sink->name) ==
get_i2s_id_by_name(afe, source->name))
return i2s_priv->low_jitter_en;
/* check if share i2s need hd en */
if (i2s_priv->share_i2s_id < 0)
return 0;
if (i2s_priv->share_i2s_id == get_i2s_id_by_name(afe, source->name))
return i2s_priv->low_jitter_en;
return 0;
}
static int mtk_afe_i2s_apll_connect(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_dapm_widget *w = sink;
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mtk_afe_i2s_priv *i2s_priv;
int cur_apll;
int i2s_need_apll;
i2s_priv = get_i2s_priv_by_name(afe, w->name);
if (!i2s_priv) {
dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__);
return 0;
}
/* which apll */
cur_apll = mt8183_get_apll_by_name(afe, source->name);
/* choose APLL from i2s rate */
i2s_need_apll = mt8183_get_apll_by_rate(afe, i2s_priv->rate);
return (i2s_need_apll == cur_apll) ? 1 : 0;
}
static int mtk_afe_i2s_mclk_connect(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_dapm_widget *w = sink;
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mtk_afe_i2s_priv *i2s_priv;
i2s_priv = get_i2s_priv_by_name(afe, sink->name);
if (!i2s_priv) {
dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__);
return 0;
}
if (get_i2s_id_by_name(afe, sink->name) ==
get_i2s_id_by_name(afe, source->name))
return (i2s_priv->mclk_rate > 0) ? 1 : 0;
/* check if share i2s need mclk */
if (i2s_priv->share_i2s_id < 0)
return 0;
if (i2s_priv->share_i2s_id == get_i2s_id_by_name(afe, source->name))
return (i2s_priv->mclk_rate > 0) ? 1 : 0;
return 0;
}
static int mtk_afe_mclk_apll_connect(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_dapm_widget *w = sink;
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mtk_afe_i2s_priv *i2s_priv;
int cur_apll;
i2s_priv = get_i2s_priv_by_name(afe, w->name);
if (!i2s_priv) {
dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__);
return 0;
}
/* which apll */
cur_apll = mt8183_get_apll_by_name(afe, source->name);
return (i2s_priv->mclk_apll == cur_apll) ? 1 : 0;
}
static const struct snd_soc_dapm_route mtk_dai_i2s_routes[] = {
/* i2s0 */
{"I2S0", NULL, "I2S0_EN"},
{"I2S0", NULL, "I2S1_EN", mtk_afe_i2s_share_connect},
{"I2S0", NULL, "I2S2_EN", mtk_afe_i2s_share_connect},
{"I2S0", NULL, "I2S3_EN", mtk_afe_i2s_share_connect},
{"I2S0", NULL, "I2S5_EN", mtk_afe_i2s_share_connect},
{"I2S0", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S0", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S0", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S0", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S0", NULL, I2S5_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{I2S0_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
{I2S0_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
{"I2S0", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S0", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S0", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S0", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S0", NULL, I2S5_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{I2S0_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
{I2S0_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
/* i2s1 */
{"I2S1_CH1", "DL1_CH1", "DL1"},
{"I2S1_CH2", "DL1_CH2", "DL1"},
{"I2S1_CH1", "DL2_CH1", "DL2"},
{"I2S1_CH2", "DL2_CH2", "DL2"},
{"I2S1_CH1", "DL3_CH1", "DL3"},
{"I2S1_CH2", "DL3_CH2", "DL3"},
{"I2S1", NULL, "I2S1_CH1"},
{"I2S1", NULL, "I2S1_CH2"},
{"I2S1", NULL, "I2S0_EN", mtk_afe_i2s_share_connect},
{"I2S1", NULL, "I2S1_EN"},
{"I2S1", NULL, "I2S2_EN", mtk_afe_i2s_share_connect},
{"I2S1", NULL, "I2S3_EN", mtk_afe_i2s_share_connect},
{"I2S1", NULL, "I2S5_EN", mtk_afe_i2s_share_connect},
{"I2S1", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S1", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S1", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S1", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S1", NULL, I2S5_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{I2S1_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
{I2S1_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
{"I2S1", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S1", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S1", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S1", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S1", NULL, I2S5_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{I2S1_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
{I2S1_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
/* i2s2 */
{"I2S2", NULL, "I2S0_EN", mtk_afe_i2s_share_connect},
{"I2S2", NULL, "I2S1_EN", mtk_afe_i2s_share_connect},
{"I2S2", NULL, "I2S2_EN"},
{"I2S2", NULL, "I2S3_EN", mtk_afe_i2s_share_connect},
{"I2S2", NULL, "I2S5_EN", mtk_afe_i2s_share_connect},
{"I2S2", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S2", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S2", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S2", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S2", NULL, I2S5_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{I2S2_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
{I2S2_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
{"I2S2", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S2", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S2", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S2", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S2", NULL, I2S5_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{I2S2_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
{I2S2_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
/* i2s3 */
{"I2S3_CH1", "DL1_CH1", "DL1"},
{"I2S3_CH2", "DL1_CH2", "DL1"},
{"I2S3_CH1", "DL2_CH1", "DL2"},
{"I2S3_CH2", "DL2_CH2", "DL2"},
{"I2S3_CH1", "DL3_CH1", "DL3"},
{"I2S3_CH2", "DL3_CH2", "DL3"},
{"I2S3", NULL, "I2S3_CH1"},
{"I2S3", NULL, "I2S3_CH2"},
{"I2S3", NULL, "I2S0_EN", mtk_afe_i2s_share_connect},
{"I2S3", NULL, "I2S1_EN", mtk_afe_i2s_share_connect},
{"I2S3", NULL, "I2S2_EN", mtk_afe_i2s_share_connect},
{"I2S3", NULL, "I2S3_EN"},
{"I2S3", NULL, "I2S5_EN", mtk_afe_i2s_share_connect},
{"I2S3", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S3", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S3", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S3", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S3", NULL, I2S5_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{I2S3_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
{I2S3_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
{"I2S3", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S3", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S3", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S3", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S3", NULL, I2S5_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{I2S3_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
{I2S3_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
/* i2s5 */
{"I2S5_CH1", "DL1_CH1", "DL1"},
{"I2S5_CH2", "DL1_CH2", "DL1"},
{"I2S5_CH1", "DL2_CH1", "DL2"},
{"I2S5_CH2", "DL2_CH2", "DL2"},
{"I2S5_CH1", "DL3_CH1", "DL3"},
{"I2S5_CH2", "DL3_CH2", "DL3"},
{"I2S5", NULL, "I2S5_CH1"},
{"I2S5", NULL, "I2S5_CH2"},
{"I2S5", NULL, "I2S0_EN", mtk_afe_i2s_share_connect},
{"I2S5", NULL, "I2S1_EN", mtk_afe_i2s_share_connect},
{"I2S5", NULL, "I2S2_EN", mtk_afe_i2s_share_connect},
{"I2S5", NULL, "I2S3_EN", mtk_afe_i2s_share_connect},
{"I2S5", NULL, "I2S5_EN"},
{"I2S5", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S5", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S5", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S5", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{"I2S5", NULL, I2S5_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
{I2S5_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
{I2S5_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
{"I2S5", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S5", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S5", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S5", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{"I2S5", NULL, I2S5_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
{I2S5_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
{I2S5_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
};
/* dai ops */
static int mtk_dai_i2s_config(struct mtk_base_afe *afe,
struct snd_pcm_hw_params *params,
int i2s_id)
{
struct mt8183_afe_private *afe_priv = afe->platform_priv;
struct mtk_afe_i2s_priv *i2s_priv = afe_priv->dai_priv[i2s_id];
unsigned int rate = params_rate(params);
unsigned int rate_reg = mt8183_rate_transform(afe->dev,
rate, i2s_id);
snd_pcm_format_t format = params_format(params);
unsigned int i2s_con = 0, fmt_con = I2S_FMT_I2S << I2S_FMT_SFT;
int ret = 0;
if (i2s_priv) {
i2s_priv->rate = rate;
if (i2s_priv->use_eiaj)
fmt_con = I2S_FMT_EIAJ << I2S_FMT_SFT;
} else {
dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__);
}
switch (i2s_id) {
case MT8183_DAI_I2S_0:
regmap_update_bits(afe->regmap, AFE_DAC_CON1,
I2S_MODE_MASK_SFT, rate_reg << I2S_MODE_SFT);
i2s_con = I2S_IN_PAD_IO_MUX << I2SIN_PAD_SEL_SFT;
i2s_con |= fmt_con;
i2s_con |= get_i2s_wlen(format) << I2S_WLEN_SFT;
regmap_update_bits(afe->regmap, AFE_I2S_CON,
0xffffeffe, i2s_con);
break;
case MT8183_DAI_I2S_1:
i2s_con = I2S1_SEL_O28_O29 << I2S2_SEL_O03_O04_SFT;
i2s_con |= rate_reg << I2S2_OUT_MODE_SFT;
i2s_con |= fmt_con;
i2s_con |= get_i2s_wlen(format) << I2S2_WLEN_SFT;
regmap_update_bits(afe->regmap, AFE_I2S_CON1,
0xffffeffe, i2s_con);
break;
case MT8183_DAI_I2S_2:
i2s_con = 8 << I2S3_UPDATE_WORD_SFT;
i2s_con |= rate_reg << I2S3_OUT_MODE_SFT;
i2s_con |= fmt_con;
i2s_con |= get_i2s_wlen(format) << I2S3_WLEN_SFT;
regmap_update_bits(afe->regmap, AFE_I2S_CON2,
0xffffeffe, i2s_con);
break;
case MT8183_DAI_I2S_3:
i2s_con = rate_reg << I2S4_OUT_MODE_SFT;
i2s_con |= fmt_con;
i2s_con |= get_i2s_wlen(format) << I2S4_WLEN_SFT;
regmap_update_bits(afe->regmap, AFE_I2S_CON3,
0xffffeffe, i2s_con);
break;
case MT8183_DAI_I2S_5:
i2s_con = rate_reg << I2S5_OUT_MODE_SFT;
i2s_con |= fmt_con;
i2s_con |= get_i2s_wlen(format) << I2S5_WLEN_SFT;
regmap_update_bits(afe->regmap, AFE_I2S_CON4,
0xffffeffe, i2s_con);
break;
default:
dev_warn(afe->dev, "%s(), id %d not support\n",
__func__, i2s_id);
return -EINVAL;
}
/* set share i2s */
if (i2s_priv && i2s_priv->share_i2s_id >= 0)
ret = mtk_dai_i2s_config(afe, params, i2s_priv->share_i2s_id);
return ret;
}
static int mtk_dai_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
return mtk_dai_i2s_config(afe, params, dai->id);
}
static int mtk_dai_i2s_set_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct mtk_base_afe *afe = dev_get_drvdata(dai->dev);
struct mt8183_afe_private *afe_priv = afe->platform_priv;
struct mtk_afe_i2s_priv *i2s_priv = afe_priv->dai_priv[dai->id];
int apll;
int apll_rate;
if (!i2s_priv) {
dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__);
return -EINVAL;
}
if (dir != SND_SOC_CLOCK_OUT) {
dev_warn(afe->dev, "%s(), dir != SND_SOC_CLOCK_OUT", __func__);
return -EINVAL;
}
apll = mt8183_get_apll_by_rate(afe, freq);
apll_rate = mt8183_get_apll_rate(afe, apll);
if (freq > apll_rate) {
dev_warn(afe->dev, "%s(), freq > apll rate", __func__);
return -EINVAL;
}
if (apll_rate % freq != 0) {
dev_warn(afe->dev, "%s(), APLL cannot generate freq Hz",
__func__);
return -EINVAL;
}
i2s_priv->mclk_rate = freq;
i2s_priv->mclk_apll = apll;
if (i2s_priv->share_i2s_id > 0) {
struct mtk_afe_i2s_priv *share_i2s_priv;
share_i2s_priv = afe_priv->dai_priv[i2s_priv->share_i2s_id];
if (!share_i2s_priv) {
dev_warn(afe->dev, "%s(), share_i2s_priv == NULL",
__func__);
return -EINVAL;
}
share_i2s_priv->mclk_rate = i2s_priv->mclk_rate;
share_i2s_priv->mclk_apll = i2s_priv->mclk_apll;
}
return 0;
}
static int mtk_dai_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8183_afe_private *afe_priv = afe->platform_priv;
struct mtk_afe_i2s_priv *i2s_priv;
switch (dai->id) {
case MT8183_DAI_I2S_0:
case MT8183_DAI_I2S_1:
case MT8183_DAI_I2S_2:
case MT8183_DAI_I2S_3:
case MT8183_DAI_I2S_5:
break;
default:
dev_warn(afe->dev, "%s(), id %d not support\n",
__func__, dai->id);
return -EINVAL;
}
i2s_priv = afe_priv->dai_priv[dai->id];
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_LEFT_J:
i2s_priv->use_eiaj = 1;
break;
case SND_SOC_DAIFMT_I2S:
i2s_priv->use_eiaj = 0;
break;
default:
dev_warn(afe->dev, "%s(), DAI format %d not support\n",
__func__, fmt & SND_SOC_DAIFMT_FORMAT_MASK);
return -EINVAL;
}
return 0;
}
static const struct snd_soc_dai_ops mtk_dai_i2s_ops = {
.hw_params = mtk_dai_i2s_hw_params,
.set_sysclk = mtk_dai_i2s_set_sysclk,
.set_fmt = mtk_dai_i2s_set_fmt,
};
/* dai driver */
#define MTK_I2S_RATES (SNDRV_PCM_RATE_8000_48000 |\
SNDRV_PCM_RATE_88200 |\
SNDRV_PCM_RATE_96000 |\
SNDRV_PCM_RATE_176400 |\
SNDRV_PCM_RATE_192000)
#define MTK_I2S_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver mtk_dai_i2s_driver[] = {
{
.name = "I2S0",
.id = MT8183_DAI_I2S_0,
.capture = {
.stream_name = "I2S0",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_I2S_RATES,
.formats = MTK_I2S_FORMATS,
},
.ops = &mtk_dai_i2s_ops,
},
{
.name = "I2S1",
.id = MT8183_DAI_I2S_1,
.playback = {
.stream_name = "I2S1",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_I2S_RATES,
.formats = MTK_I2S_FORMATS,
},
.ops = &mtk_dai_i2s_ops,
},
{
.name = "I2S2",
.id = MT8183_DAI_I2S_2,
.capture = {
.stream_name = "I2S2",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_I2S_RATES,
.formats = MTK_I2S_FORMATS,
},
.ops = &mtk_dai_i2s_ops,
},
{
.name = "I2S3",
.id = MT8183_DAI_I2S_3,
.playback = {
.stream_name = "I2S3",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_I2S_RATES,
.formats = MTK_I2S_FORMATS,
},
.ops = &mtk_dai_i2s_ops,
},
{
.name = "I2S5",
.id = MT8183_DAI_I2S_5,
.playback = {
.stream_name = "I2S5",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_I2S_RATES,
.formats = MTK_I2S_FORMATS,
},
.ops = &mtk_dai_i2s_ops,
},
};
/* this enum is merely for mtk_afe_i2s_priv declare */
enum {
DAI_I2S0 = 0,
DAI_I2S1,
DAI_I2S2,
DAI_I2S3,
DAI_I2S5,
DAI_I2S_NUM,
};
static const struct mtk_afe_i2s_priv mt8183_i2s_priv[DAI_I2S_NUM] = {
[DAI_I2S0] = {
.id = MT8183_DAI_I2S_0,
.mclk_id = MT8183_I2S0_MCK,
.share_i2s_id = -1,
},
[DAI_I2S1] = {
.id = MT8183_DAI_I2S_1,
.mclk_id = MT8183_I2S1_MCK,
.share_i2s_id = -1,
},
[DAI_I2S2] = {
.id = MT8183_DAI_I2S_2,
.mclk_id = MT8183_I2S2_MCK,
.share_i2s_id = -1,
},
[DAI_I2S3] = {
.id = MT8183_DAI_I2S_3,
.mclk_id = MT8183_I2S3_MCK,
.share_i2s_id = -1,
},
[DAI_I2S5] = {
.id = MT8183_DAI_I2S_5,
.mclk_id = MT8183_I2S5_MCK,
.share_i2s_id = -1,
},
};
/**
* mt8183_dai_i2s_set_share() - Set up I2S ports to share a single clock.
* @afe: Pointer to &struct mtk_base_afe
* @main_i2s_name: The name of the I2S port that will provide the clock
* @secondary_i2s_name: The name of the I2S port that will use this clock
*/
int mt8183_dai_i2s_set_share(struct mtk_base_afe *afe, const char *main_i2s_name,
const char *secondary_i2s_name)
{
struct mtk_afe_i2s_priv *secondary_i2s_priv;
int main_i2s_id;
secondary_i2s_priv = get_i2s_priv_by_name(afe, secondary_i2s_name);
if (!secondary_i2s_priv)
return -EINVAL;
main_i2s_id = get_i2s_id_by_name(afe, main_i2s_name);
if (main_i2s_id < 0)
return main_i2s_id;
secondary_i2s_priv->share_i2s_id = main_i2s_id;
return 0;
}
EXPORT_SYMBOL_GPL(mt8183_dai_i2s_set_share);
static int mt8183_dai_i2s_set_priv(struct mtk_base_afe *afe)
{
struct mt8183_afe_private *afe_priv = afe->platform_priv;
struct mtk_afe_i2s_priv *i2s_priv;
int i;
for (i = 0; i < DAI_I2S_NUM; i++) {
i2s_priv = devm_kzalloc(afe->dev,
sizeof(struct mtk_afe_i2s_priv),
GFP_KERNEL);
if (!i2s_priv)
return -ENOMEM;
memcpy(i2s_priv, &mt8183_i2s_priv[i],
sizeof(struct mtk_afe_i2s_priv));
afe_priv->dai_priv[mt8183_i2s_priv[i].id] = i2s_priv;
}
return 0;
}
int mt8183_dai_i2s_register(struct mtk_base_afe *afe)
{
struct mtk_base_afe_dai *dai;
int ret;
dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
if (!dai)
return -ENOMEM;
list_add(&dai->list, &afe->sub_dais);
dai->dai_drivers = mtk_dai_i2s_driver;
dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_i2s_driver);
dai->controls = mtk_dai_i2s_controls;
dai->num_controls = ARRAY_SIZE(mtk_dai_i2s_controls);
dai->dapm_widgets = mtk_dai_i2s_widgets;
dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_i2s_widgets);
dai->dapm_routes = mtk_dai_i2s_routes;
dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_i2s_routes);
/* set all dai i2s private data */
ret = mt8183_dai_i2s_set_priv(afe);
if (ret)
return ret;
return 0;
}
| linux-master | sound/soc/mediatek/mt8183/mt8183-dai-i2s.c |
// SPDX-License-Identifier: GPL-2.0
//
// Mediatek ALSA SoC AFE platform driver for 8183
//
// Copyright (c) 2018 MediaTek Inc.
// Author: KaiChieh Chuang <[email protected]>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/pm_runtime.h>
#include <linux/reset.h>
#include "mt8183-afe-common.h"
#include "mt8183-afe-clk.h"
#include "mt8183-interconnection.h"
#include "mt8183-reg.h"
#include "../common/mtk-afe-platform-driver.h"
#include "../common/mtk-afe-fe-dai.h"
enum {
MTK_AFE_RATE_8K = 0,
MTK_AFE_RATE_11K = 1,
MTK_AFE_RATE_12K = 2,
MTK_AFE_RATE_384K = 3,
MTK_AFE_RATE_16K = 4,
MTK_AFE_RATE_22K = 5,
MTK_AFE_RATE_24K = 6,
MTK_AFE_RATE_130K = 7,
MTK_AFE_RATE_32K = 8,
MTK_AFE_RATE_44K = 9,
MTK_AFE_RATE_48K = 10,
MTK_AFE_RATE_88K = 11,
MTK_AFE_RATE_96K = 12,
MTK_AFE_RATE_176K = 13,
MTK_AFE_RATE_192K = 14,
MTK_AFE_RATE_260K = 15,
};
enum {
MTK_AFE_DAI_MEMIF_RATE_8K = 0,
MTK_AFE_DAI_MEMIF_RATE_16K = 1,
MTK_AFE_DAI_MEMIF_RATE_32K = 2,
MTK_AFE_DAI_MEMIF_RATE_48K = 3,
};
enum {
MTK_AFE_PCM_RATE_8K = 0,
MTK_AFE_PCM_RATE_16K = 1,
MTK_AFE_PCM_RATE_32K = 2,
MTK_AFE_PCM_RATE_48K = 3,
};
unsigned int mt8183_general_rate_transform(struct device *dev,
unsigned int rate)
{
switch (rate) {
case 8000:
return MTK_AFE_RATE_8K;
case 11025:
return MTK_AFE_RATE_11K;
case 12000:
return MTK_AFE_RATE_12K;
case 16000:
return MTK_AFE_RATE_16K;
case 22050:
return MTK_AFE_RATE_22K;
case 24000:
return MTK_AFE_RATE_24K;
case 32000:
return MTK_AFE_RATE_32K;
case 44100:
return MTK_AFE_RATE_44K;
case 48000:
return MTK_AFE_RATE_48K;
case 88200:
return MTK_AFE_RATE_88K;
case 96000:
return MTK_AFE_RATE_96K;
case 130000:
return MTK_AFE_RATE_130K;
case 176400:
return MTK_AFE_RATE_176K;
case 192000:
return MTK_AFE_RATE_192K;
case 260000:
return MTK_AFE_RATE_260K;
default:
dev_warn(dev, "%s(), rate %u invalid, use %d!!!\n",
__func__, rate, MTK_AFE_RATE_48K);
return MTK_AFE_RATE_48K;
}
}
static unsigned int dai_memif_rate_transform(struct device *dev,
unsigned int rate)
{
switch (rate) {
case 8000:
return MTK_AFE_DAI_MEMIF_RATE_8K;
case 16000:
return MTK_AFE_DAI_MEMIF_RATE_16K;
case 32000:
return MTK_AFE_DAI_MEMIF_RATE_32K;
case 48000:
return MTK_AFE_DAI_MEMIF_RATE_48K;
default:
dev_warn(dev, "%s(), rate %u invalid, use %d!!!\n",
__func__, rate, MTK_AFE_DAI_MEMIF_RATE_16K);
return MTK_AFE_DAI_MEMIF_RATE_16K;
}
}
unsigned int mt8183_rate_transform(struct device *dev,
unsigned int rate, int aud_blk)
{
switch (aud_blk) {
case MT8183_MEMIF_MOD_DAI:
return dai_memif_rate_transform(dev, rate);
default:
return mt8183_general_rate_transform(dev, rate);
}
}
static const struct snd_pcm_hardware mt8183_afe_hardware = {
.info = SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_MMAP_VALID,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE |
SNDRV_PCM_FMTBIT_S32_LE,
.period_bytes_min = 256,
.period_bytes_max = 4 * 48 * 1024,
.periods_min = 2,
.periods_max = 256,
.buffer_bytes_max = 8 * 48 * 1024,
.fifo_size = 0,
};
static int mt8183_memif_fs(struct snd_pcm_substream *substream,
unsigned int rate)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_component *component =
snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
int id = asoc_rtd_to_cpu(rtd, 0)->id;
return mt8183_rate_transform(afe->dev, rate, id);
}
static int mt8183_irq_fs(struct snd_pcm_substream *substream, unsigned int rate)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_component *component =
snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
return mt8183_general_rate_transform(afe->dev, rate);
}
#define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\
SNDRV_PCM_RATE_88200 |\
SNDRV_PCM_RATE_96000 |\
SNDRV_PCM_RATE_176400 |\
SNDRV_PCM_RATE_192000)
#define MTK_PCM_DAI_RATES (SNDRV_PCM_RATE_8000 |\
SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 |\
SNDRV_PCM_RATE_48000)
#define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver mt8183_memif_dai_driver[] = {
/* FE DAIs: memory intefaces to CPU */
{
.name = "DL1",
.id = MT8183_MEMIF_DL1,
.playback = {
.stream_name = "DL1",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_afe_fe_ops,
},
{
.name = "DL2",
.id = MT8183_MEMIF_DL2,
.playback = {
.stream_name = "DL2",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_afe_fe_ops,
},
{
.name = "DL3",
.id = MT8183_MEMIF_DL3,
.playback = {
.stream_name = "DL3",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_afe_fe_ops,
},
{
.name = "UL1",
.id = MT8183_MEMIF_VUL12,
.capture = {
.stream_name = "UL1",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_afe_fe_ops,
},
{
.name = "UL2",
.id = MT8183_MEMIF_AWB,
.capture = {
.stream_name = "UL2",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_afe_fe_ops,
},
{
.name = "UL3",
.id = MT8183_MEMIF_VUL2,
.capture = {
.stream_name = "UL3",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_afe_fe_ops,
},
{
.name = "UL4",
.id = MT8183_MEMIF_AWB2,
.capture = {
.stream_name = "UL4",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_afe_fe_ops,
},
{
.name = "UL_MONO_1",
.id = MT8183_MEMIF_MOD_DAI,
.capture = {
.stream_name = "UL_MONO_1",
.channels_min = 1,
.channels_max = 1,
.rates = MTK_PCM_DAI_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_afe_fe_ops,
},
{
.name = "HDMI",
.id = MT8183_MEMIF_HDMI,
.playback = {
.stream_name = "HDMI",
.channels_min = 2,
.channels_max = 8,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_afe_fe_ops,
},
};
/* dma widget & routes*/
static const struct snd_kcontrol_new memif_ul1_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN21,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1", AFE_CONN21,
I_I2S0_CH1, 1, 0),
};
static const struct snd_kcontrol_new memif_ul1_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN22,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2", AFE_CONN21,
I_I2S0_CH2, 1, 0),
};
static const struct snd_kcontrol_new memif_ul2_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN5,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN5,
I_DL1_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN5,
I_DL2_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN5,
I_DL3_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1", AFE_CONN5,
I_I2S2_CH1, 1, 0),
};
static const struct snd_kcontrol_new memif_ul2_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN6,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN6,
I_DL1_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN6,
I_DL2_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN6,
I_DL3_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2", AFE_CONN6,
I_I2S2_CH2, 1, 0),
};
static const struct snd_kcontrol_new memif_ul3_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN32,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1", AFE_CONN32,
I_I2S2_CH1, 1, 0),
};
static const struct snd_kcontrol_new memif_ul3_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN33,
I_ADDA_UL_CH2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2", AFE_CONN33,
I_I2S2_CH2, 1, 0),
};
static const struct snd_kcontrol_new memif_ul4_ch1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN38,
I_ADDA_UL_CH1, 1, 0),
};
static const struct snd_kcontrol_new memif_ul4_ch2_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN39,
I_ADDA_UL_CH2, 1, 0),
};
static const struct snd_kcontrol_new memif_ul_mono_1_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN12,
I_ADDA_UL_CH1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN12,
I_ADDA_UL_CH2, 1, 0),
};
static const struct snd_soc_dapm_widget mt8183_memif_widgets[] = {
/* memif */
SND_SOC_DAPM_MIXER("UL1_CH1", SND_SOC_NOPM, 0, 0,
memif_ul1_ch1_mix, ARRAY_SIZE(memif_ul1_ch1_mix)),
SND_SOC_DAPM_MIXER("UL1_CH2", SND_SOC_NOPM, 0, 0,
memif_ul1_ch2_mix, ARRAY_SIZE(memif_ul1_ch2_mix)),
SND_SOC_DAPM_MIXER("UL2_CH1", SND_SOC_NOPM, 0, 0,
memif_ul2_ch1_mix, ARRAY_SIZE(memif_ul2_ch1_mix)),
SND_SOC_DAPM_MIXER("UL2_CH2", SND_SOC_NOPM, 0, 0,
memif_ul2_ch2_mix, ARRAY_SIZE(memif_ul2_ch2_mix)),
SND_SOC_DAPM_MIXER("UL3_CH1", SND_SOC_NOPM, 0, 0,
memif_ul3_ch1_mix, ARRAY_SIZE(memif_ul3_ch1_mix)),
SND_SOC_DAPM_MIXER("UL3_CH2", SND_SOC_NOPM, 0, 0,
memif_ul3_ch2_mix, ARRAY_SIZE(memif_ul3_ch2_mix)),
SND_SOC_DAPM_MIXER("UL4_CH1", SND_SOC_NOPM, 0, 0,
memif_ul4_ch1_mix, ARRAY_SIZE(memif_ul4_ch1_mix)),
SND_SOC_DAPM_MIXER("UL4_CH2", SND_SOC_NOPM, 0, 0,
memif_ul4_ch2_mix, ARRAY_SIZE(memif_ul4_ch2_mix)),
SND_SOC_DAPM_MIXER("UL_MONO_1_CH1", SND_SOC_NOPM, 0, 0,
memif_ul_mono_1_mix,
ARRAY_SIZE(memif_ul_mono_1_mix)),
};
static const struct snd_soc_dapm_route mt8183_memif_routes[] = {
/* capture */
{"UL1", NULL, "UL1_CH1"},
{"UL1", NULL, "UL1_CH2"},
{"UL1_CH1", "ADDA_UL_CH1", "ADDA Capture"},
{"UL1_CH2", "ADDA_UL_CH2", "ADDA Capture"},
{"UL1_CH1", "I2S0_CH1", "I2S0"},
{"UL1_CH2", "I2S0_CH2", "I2S0"},
{"UL2", NULL, "UL2_CH1"},
{"UL2", NULL, "UL2_CH2"},
{"UL2_CH1", "ADDA_UL_CH1", "ADDA Capture"},
{"UL2_CH2", "ADDA_UL_CH2", "ADDA Capture"},
{"UL2_CH1", "I2S2_CH1", "I2S2"},
{"UL2_CH2", "I2S2_CH2", "I2S2"},
{"UL3", NULL, "UL3_CH1"},
{"UL3", NULL, "UL3_CH2"},
{"UL3_CH1", "ADDA_UL_CH1", "ADDA Capture"},
{"UL3_CH2", "ADDA_UL_CH2", "ADDA Capture"},
{"UL3_CH1", "I2S2_CH1", "I2S2"},
{"UL3_CH2", "I2S2_CH2", "I2S2"},
{"UL4", NULL, "UL4_CH1"},
{"UL4", NULL, "UL4_CH2"},
{"UL4_CH1", "ADDA_UL_CH1", "ADDA Capture"},
{"UL4_CH2", "ADDA_UL_CH2", "ADDA Capture"},
{"UL_MONO_1", NULL, "UL_MONO_1_CH1"},
{"UL_MONO_1_CH1", "ADDA_UL_CH1", "ADDA Capture"},
{"UL_MONO_1_CH1", "ADDA_UL_CH2", "ADDA Capture"},
};
static const struct snd_soc_component_driver mt8183_afe_pcm_dai_component = {
.name = "mt8183-afe-pcm-dai",
};
static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = {
[MT8183_MEMIF_DL1] = {
.name = "DL1",
.id = MT8183_MEMIF_DL1,
.reg_ofs_base = AFE_DL1_BASE,
.reg_ofs_cur = AFE_DL1_CUR,
.fs_reg = AFE_DAC_CON1,
.fs_shift = DL1_MODE_SFT,
.fs_maskbit = DL1_MODE_MASK,
.mono_reg = AFE_DAC_CON1,
.mono_shift = DL1_DATA_SFT,
.enable_reg = AFE_DAC_CON0,
.enable_shift = DL1_ON_SFT,
.hd_reg = AFE_MEMIF_HD_MODE,
.hd_align_reg = AFE_MEMIF_HDALIGN,
.hd_shift = DL1_HD_SFT,
.hd_align_mshift = DL1_HD_ALIGN_SFT,
.agent_disable_reg = -1,
.agent_disable_shift = -1,
.msb_reg = -1,
.msb_shift = -1,
},
[MT8183_MEMIF_DL2] = {
.name = "DL2",
.id = MT8183_MEMIF_DL2,
.reg_ofs_base = AFE_DL2_BASE,
.reg_ofs_cur = AFE_DL2_CUR,
.fs_reg = AFE_DAC_CON1,
.fs_shift = DL2_MODE_SFT,
.fs_maskbit = DL2_MODE_MASK,
.mono_reg = AFE_DAC_CON1,
.mono_shift = DL2_DATA_SFT,
.enable_reg = AFE_DAC_CON0,
.enable_shift = DL2_ON_SFT,
.hd_reg = AFE_MEMIF_HD_MODE,
.hd_align_reg = AFE_MEMIF_HDALIGN,
.hd_shift = DL2_HD_SFT,
.hd_align_mshift = DL2_HD_ALIGN_SFT,
.agent_disable_reg = -1,
.agent_disable_shift = -1,
.msb_reg = -1,
.msb_shift = -1,
},
[MT8183_MEMIF_DL3] = {
.name = "DL3",
.id = MT8183_MEMIF_DL3,
.reg_ofs_base = AFE_DL3_BASE,
.reg_ofs_cur = AFE_DL3_CUR,
.fs_reg = AFE_DAC_CON2,
.fs_shift = DL3_MODE_SFT,
.fs_maskbit = DL3_MODE_MASK,
.mono_reg = AFE_DAC_CON1,
.mono_shift = DL3_DATA_SFT,
.enable_reg = AFE_DAC_CON0,
.enable_shift = DL3_ON_SFT,
.hd_reg = AFE_MEMIF_HD_MODE,
.hd_align_reg = AFE_MEMIF_HDALIGN,
.hd_shift = DL3_HD_SFT,
.hd_align_mshift = DL3_HD_ALIGN_SFT,
.agent_disable_reg = -1,
.agent_disable_shift = -1,
.msb_reg = -1,
.msb_shift = -1,
},
[MT8183_MEMIF_VUL2] = {
.name = "VUL2",
.id = MT8183_MEMIF_VUL2,
.reg_ofs_base = AFE_VUL2_BASE,
.reg_ofs_cur = AFE_VUL2_CUR,
.fs_reg = AFE_DAC_CON2,
.fs_shift = VUL2_MODE_SFT,
.fs_maskbit = VUL2_MODE_MASK,
.mono_reg = AFE_DAC_CON2,
.mono_shift = VUL2_DATA_SFT,
.enable_reg = AFE_DAC_CON0,
.enable_shift = VUL2_ON_SFT,
.hd_reg = AFE_MEMIF_HD_MODE,
.hd_align_reg = AFE_MEMIF_HDALIGN,
.hd_shift = VUL2_HD_SFT,
.hd_align_mshift = VUL2_HD_ALIGN_SFT,
.agent_disable_reg = -1,
.agent_disable_shift = -1,
.msb_reg = -1,
.msb_shift = -1,
},
[MT8183_MEMIF_AWB] = {
.name = "AWB",
.id = MT8183_MEMIF_AWB,
.reg_ofs_base = AFE_AWB_BASE,
.reg_ofs_cur = AFE_AWB_CUR,
.fs_reg = AFE_DAC_CON1,
.fs_shift = AWB_MODE_SFT,
.fs_maskbit = AWB_MODE_MASK,
.mono_reg = AFE_DAC_CON1,
.mono_shift = AWB_DATA_SFT,
.enable_reg = AFE_DAC_CON0,
.enable_shift = AWB_ON_SFT,
.hd_reg = AFE_MEMIF_HD_MODE,
.hd_align_reg = AFE_MEMIF_HDALIGN,
.hd_shift = AWB_HD_SFT,
.hd_align_mshift = AWB_HD_ALIGN_SFT,
.agent_disable_reg = -1,
.agent_disable_shift = -1,
.msb_reg = -1,
.msb_shift = -1,
},
[MT8183_MEMIF_AWB2] = {
.name = "AWB2",
.id = MT8183_MEMIF_AWB2,
.reg_ofs_base = AFE_AWB2_BASE,
.reg_ofs_cur = AFE_AWB2_CUR,
.fs_reg = AFE_DAC_CON2,
.fs_shift = AWB2_MODE_SFT,
.fs_maskbit = AWB2_MODE_MASK,
.mono_reg = AFE_DAC_CON2,
.mono_shift = AWB2_DATA_SFT,
.enable_reg = AFE_DAC_CON0,
.enable_shift = AWB2_ON_SFT,
.hd_reg = AFE_MEMIF_HD_MODE,
.hd_align_reg = AFE_MEMIF_HDALIGN,
.hd_shift = AWB2_HD_SFT,
.hd_align_mshift = AWB2_ALIGN_SFT,
.agent_disable_reg = -1,
.agent_disable_shift = -1,
.msb_reg = -1,
.msb_shift = -1,
},
[MT8183_MEMIF_VUL12] = {
.name = "VUL12",
.id = MT8183_MEMIF_VUL12,
.reg_ofs_base = AFE_VUL_D2_BASE,
.reg_ofs_cur = AFE_VUL_D2_CUR,
.fs_reg = AFE_DAC_CON0,
.fs_shift = VUL12_MODE_SFT,
.fs_maskbit = VUL12_MODE_MASK,
.mono_reg = AFE_DAC_CON0,
.mono_shift = VUL12_MONO_SFT,
.enable_reg = AFE_DAC_CON0,
.enable_shift = VUL12_ON_SFT,
.hd_reg = AFE_MEMIF_HD_MODE,
.hd_align_reg = AFE_MEMIF_HDALIGN,
.hd_shift = VUL12_HD_SFT,
.hd_align_mshift = VUL12_HD_ALIGN_SFT,
.agent_disable_reg = -1,
.agent_disable_shift = -1,
.msb_reg = -1,
.msb_shift = -1,
},
[MT8183_MEMIF_MOD_DAI] = {
.name = "MOD_DAI",
.id = MT8183_MEMIF_MOD_DAI,
.reg_ofs_base = AFE_MOD_DAI_BASE,
.reg_ofs_cur = AFE_MOD_DAI_CUR,
.fs_reg = AFE_DAC_CON1,
.fs_shift = MOD_DAI_MODE_SFT,
.fs_maskbit = MOD_DAI_MODE_MASK,
.mono_reg = -1,
.mono_shift = 0,
.enable_reg = AFE_DAC_CON0,
.enable_shift = MOD_DAI_ON_SFT,
.hd_reg = AFE_MEMIF_HD_MODE,
.hd_align_reg = AFE_MEMIF_HDALIGN,
.hd_shift = MOD_DAI_HD_SFT,
.hd_align_mshift = MOD_DAI_HD_ALIGN_SFT,
.agent_disable_reg = -1,
.agent_disable_shift = -1,
.msb_reg = -1,
.msb_shift = -1,
},
[MT8183_MEMIF_HDMI] = {
.name = "HDMI",
.id = MT8183_MEMIF_HDMI,
.reg_ofs_base = AFE_HDMI_OUT_BASE,
.reg_ofs_cur = AFE_HDMI_OUT_CUR,
.fs_reg = -1,
.fs_shift = -1,
.fs_maskbit = -1,
.mono_reg = -1,
.mono_shift = -1,
.enable_reg = -1, /* control in tdm for sync start */
.enable_shift = -1,
.hd_reg = AFE_MEMIF_HD_MODE,
.hd_align_reg = AFE_MEMIF_HDALIGN,
.hd_shift = HDMI_HD_SFT,
.hd_align_mshift = HDMI_HD_ALIGN_SFT,
.agent_disable_reg = -1,
.agent_disable_shift = -1,
.msb_reg = -1,
.msb_shift = -1,
},
};
static const struct mtk_base_irq_data irq_data[MT8183_IRQ_NUM] = {
[MT8183_IRQ_0] = {
.id = MT8183_IRQ_0,
.irq_cnt_reg = AFE_IRQ_MCU_CNT0,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0x3ffff,
.irq_fs_reg = AFE_IRQ_MCU_CON1,
.irq_fs_shift = IRQ0_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ0_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ0_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ0_MCU_CLR_SFT,
},
[MT8183_IRQ_1] = {
.id = MT8183_IRQ_1,
.irq_cnt_reg = AFE_IRQ_MCU_CNT1,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0x3ffff,
.irq_fs_reg = AFE_IRQ_MCU_CON1,
.irq_fs_shift = IRQ1_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ1_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ1_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ1_MCU_CLR_SFT,
},
[MT8183_IRQ_2] = {
.id = MT8183_IRQ_2,
.irq_cnt_reg = AFE_IRQ_MCU_CNT2,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0x3ffff,
.irq_fs_reg = AFE_IRQ_MCU_CON1,
.irq_fs_shift = IRQ2_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ2_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ2_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ2_MCU_CLR_SFT,
},
[MT8183_IRQ_3] = {
.id = MT8183_IRQ_3,
.irq_cnt_reg = AFE_IRQ_MCU_CNT3,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0x3ffff,
.irq_fs_reg = AFE_IRQ_MCU_CON1,
.irq_fs_shift = IRQ3_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ3_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ3_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ3_MCU_CLR_SFT,
},
[MT8183_IRQ_4] = {
.id = MT8183_IRQ_4,
.irq_cnt_reg = AFE_IRQ_MCU_CNT4,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0x3ffff,
.irq_fs_reg = AFE_IRQ_MCU_CON1,
.irq_fs_shift = IRQ4_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ4_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ4_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ4_MCU_CLR_SFT,
},
[MT8183_IRQ_5] = {
.id = MT8183_IRQ_5,
.irq_cnt_reg = AFE_IRQ_MCU_CNT5,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0x3ffff,
.irq_fs_reg = AFE_IRQ_MCU_CON1,
.irq_fs_shift = IRQ5_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ5_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ5_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ5_MCU_CLR_SFT,
},
[MT8183_IRQ_6] = {
.id = MT8183_IRQ_6,
.irq_cnt_reg = AFE_IRQ_MCU_CNT6,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0x3ffff,
.irq_fs_reg = AFE_IRQ_MCU_CON1,
.irq_fs_shift = IRQ6_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ6_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ6_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ6_MCU_CLR_SFT,
},
[MT8183_IRQ_7] = {
.id = MT8183_IRQ_7,
.irq_cnt_reg = AFE_IRQ_MCU_CNT7,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0x3ffff,
.irq_fs_reg = AFE_IRQ_MCU_CON1,
.irq_fs_shift = IRQ7_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ7_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ7_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ7_MCU_CLR_SFT,
},
[MT8183_IRQ_8] = {
.id = MT8183_IRQ_8,
.irq_cnt_reg = AFE_IRQ_MCU_CNT8,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0x3ffff,
.irq_fs_reg = -1,
.irq_fs_shift = -1,
.irq_fs_maskbit = -1,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ8_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ8_MCU_CLR_SFT,
},
[MT8183_IRQ_11] = {
.id = MT8183_IRQ_11,
.irq_cnt_reg = AFE_IRQ_MCU_CNT11,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0x3ffff,
.irq_fs_reg = AFE_IRQ_MCU_CON2,
.irq_fs_shift = IRQ11_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ11_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ11_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ11_MCU_CLR_SFT,
},
[MT8183_IRQ_12] = {
.id = MT8183_IRQ_12,
.irq_cnt_reg = AFE_IRQ_MCU_CNT12,
.irq_cnt_shift = 0,
.irq_cnt_maskbit = 0x3ffff,
.irq_fs_reg = AFE_IRQ_MCU_CON2,
.irq_fs_shift = IRQ12_MCU_MODE_SFT,
.irq_fs_maskbit = IRQ12_MCU_MODE_MASK,
.irq_en_reg = AFE_IRQ_MCU_CON0,
.irq_en_shift = IRQ12_MCU_ON_SFT,
.irq_clr_reg = AFE_IRQ_MCU_CLR,
.irq_clr_shift = IRQ12_MCU_CLR_SFT,
},
};
static bool mt8183_is_volatile_reg(struct device *dev, unsigned int reg)
{
/* these auto-gen reg has read-only bit, so put it as volatile */
/* volatile reg cannot be cached, so cannot be set when power off */
switch (reg) {
case AUDIO_TOP_CON0: /* reg bit controlled by CCF */
case AUDIO_TOP_CON1: /* reg bit controlled by CCF */
case AUDIO_TOP_CON3:
case AFE_DL1_CUR:
case AFE_DL1_END:
case AFE_DL2_CUR:
case AFE_DL2_END:
case AFE_AWB_END:
case AFE_AWB_CUR:
case AFE_VUL_END:
case AFE_VUL_CUR:
case AFE_MEMIF_MON0:
case AFE_MEMIF_MON1:
case AFE_MEMIF_MON2:
case AFE_MEMIF_MON3:
case AFE_MEMIF_MON4:
case AFE_MEMIF_MON5:
case AFE_MEMIF_MON6:
case AFE_MEMIF_MON7:
case AFE_MEMIF_MON8:
case AFE_MEMIF_MON9:
case AFE_ADDA_SRC_DEBUG_MON0:
case AFE_ADDA_SRC_DEBUG_MON1:
case AFE_ADDA_UL_SRC_MON0:
case AFE_ADDA_UL_SRC_MON1:
case AFE_SIDETONE_MON:
case AFE_SIDETONE_CON0:
case AFE_SIDETONE_COEFF:
case AFE_BUS_MON0:
case AFE_MRGIF_MON0:
case AFE_MRGIF_MON1:
case AFE_MRGIF_MON2:
case AFE_I2S_MON:
case AFE_DAC_MON:
case AFE_VUL2_END:
case AFE_VUL2_CUR:
case AFE_IRQ0_MCU_CNT_MON:
case AFE_IRQ6_MCU_CNT_MON:
case AFE_MOD_DAI_END:
case AFE_MOD_DAI_CUR:
case AFE_VUL_D2_END:
case AFE_VUL_D2_CUR:
case AFE_DL3_CUR:
case AFE_DL3_END:
case AFE_HDMI_OUT_CON0:
case AFE_HDMI_OUT_CUR:
case AFE_HDMI_OUT_END:
case AFE_IRQ3_MCU_CNT_MON:
case AFE_IRQ4_MCU_CNT_MON:
case AFE_IRQ_MCU_STATUS:
case AFE_IRQ_MCU_CLR:
case AFE_IRQ_MCU_MON2:
case AFE_IRQ1_MCU_CNT_MON:
case AFE_IRQ2_MCU_CNT_MON:
case AFE_IRQ1_MCU_EN_CNT_MON:
case AFE_IRQ5_MCU_CNT_MON:
case AFE_IRQ7_MCU_CNT_MON:
case AFE_GAIN1_CUR:
case AFE_GAIN2_CUR:
case AFE_SRAM_DELSEL_CON0:
case AFE_SRAM_DELSEL_CON2:
case AFE_SRAM_DELSEL_CON3:
case AFE_ASRC_2CH_CON12:
case AFE_ASRC_2CH_CON13:
case PCM_INTF_CON2:
case FPGA_CFG0:
case FPGA_CFG1:
case FPGA_CFG2:
case FPGA_CFG3:
case AUDIO_TOP_DBG_MON0:
case AUDIO_TOP_DBG_MON1:
case AFE_IRQ8_MCU_CNT_MON:
case AFE_IRQ11_MCU_CNT_MON:
case AFE_IRQ12_MCU_CNT_MON:
case AFE_CBIP_MON0:
case AFE_CBIP_SLV_MUX_MON0:
case AFE_CBIP_SLV_DECODER_MON0:
case AFE_ADDA6_SRC_DEBUG_MON0:
case AFE_ADD6A_UL_SRC_MON0:
case AFE_ADDA6_UL_SRC_MON1:
case AFE_DL1_CUR_MSB:
case AFE_DL2_CUR_MSB:
case AFE_AWB_CUR_MSB:
case AFE_VUL_CUR_MSB:
case AFE_VUL2_CUR_MSB:
case AFE_MOD_DAI_CUR_MSB:
case AFE_VUL_D2_CUR_MSB:
case AFE_DL3_CUR_MSB:
case AFE_HDMI_OUT_CUR_MSB:
case AFE_AWB2_END:
case AFE_AWB2_CUR:
case AFE_AWB2_CUR_MSB:
case AFE_ADDA_DL_SDM_FIFO_MON:
case AFE_ADDA_DL_SRC_LCH_MON:
case AFE_ADDA_DL_SRC_RCH_MON:
case AFE_ADDA_DL_SDM_OUT_MON:
case AFE_CONNSYS_I2S_MON:
case AFE_ASRC_2CH_CON0:
case AFE_ASRC_2CH_CON2:
case AFE_ASRC_2CH_CON3:
case AFE_ASRC_2CH_CON4:
case AFE_ASRC_2CH_CON5:
case AFE_ASRC_2CH_CON7:
case AFE_ASRC_2CH_CON8:
case AFE_MEMIF_MON12:
case AFE_MEMIF_MON13:
case AFE_MEMIF_MON14:
case AFE_MEMIF_MON15:
case AFE_MEMIF_MON16:
case AFE_MEMIF_MON17:
case AFE_MEMIF_MON18:
case AFE_MEMIF_MON19:
case AFE_MEMIF_MON20:
case AFE_MEMIF_MON21:
case AFE_MEMIF_MON22:
case AFE_MEMIF_MON23:
case AFE_MEMIF_MON24:
case AFE_ADDA_MTKAIF_MON0:
case AFE_ADDA_MTKAIF_MON1:
case AFE_AUD_PAD_TOP:
case AFE_GENERAL1_ASRC_2CH_CON0:
case AFE_GENERAL1_ASRC_2CH_CON2:
case AFE_GENERAL1_ASRC_2CH_CON3:
case AFE_GENERAL1_ASRC_2CH_CON4:
case AFE_GENERAL1_ASRC_2CH_CON5:
case AFE_GENERAL1_ASRC_2CH_CON7:
case AFE_GENERAL1_ASRC_2CH_CON8:
case AFE_GENERAL1_ASRC_2CH_CON12:
case AFE_GENERAL1_ASRC_2CH_CON13:
case AFE_GENERAL2_ASRC_2CH_CON0:
case AFE_GENERAL2_ASRC_2CH_CON2:
case AFE_GENERAL2_ASRC_2CH_CON3:
case AFE_GENERAL2_ASRC_2CH_CON4:
case AFE_GENERAL2_ASRC_2CH_CON5:
case AFE_GENERAL2_ASRC_2CH_CON7:
case AFE_GENERAL2_ASRC_2CH_CON8:
case AFE_GENERAL2_ASRC_2CH_CON12:
case AFE_GENERAL2_ASRC_2CH_CON13:
return true;
default:
return false;
};
}
static const struct regmap_config mt8183_afe_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.volatile_reg = mt8183_is_volatile_reg,
.max_register = AFE_MAX_REGISTER,
.num_reg_defaults_raw = AFE_MAX_REGISTER,
.cache_type = REGCACHE_FLAT,
};
static irqreturn_t mt8183_afe_irq_handler(int irq_id, void *dev)
{
struct mtk_base_afe *afe = dev;
struct mtk_base_afe_irq *irq;
unsigned int status;
unsigned int status_mcu;
unsigned int mcu_en;
int ret;
int i;
irqreturn_t irq_ret = IRQ_HANDLED;
/* get irq that is sent to MCU */
regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &mcu_en);
ret = regmap_read(afe->regmap, AFE_IRQ_MCU_STATUS, &status);
/* only care IRQ which is sent to MCU */
status_mcu = status & mcu_en & AFE_IRQ_STATUS_BITS;
if (ret || status_mcu == 0) {
dev_err(afe->dev, "%s(), irq status err, ret %d, status 0x%x, mcu_en 0x%x\n",
__func__, ret, status, mcu_en);
irq_ret = IRQ_NONE;
goto err_irq;
}
for (i = 0; i < MT8183_MEMIF_NUM; i++) {
struct mtk_base_afe_memif *memif = &afe->memif[i];
if (!memif->substream)
continue;
if (memif->irq_usage < 0)
continue;
irq = &afe->irqs[memif->irq_usage];
if (status_mcu & (1 << irq->irq_data->irq_en_shift))
snd_pcm_period_elapsed(memif->substream);
}
err_irq:
/* clear irq */
regmap_write(afe->regmap,
AFE_IRQ_MCU_CLR,
status_mcu);
return irq_ret;
}
static int mt8183_afe_runtime_suspend(struct device *dev)
{
struct mtk_base_afe *afe = dev_get_drvdata(dev);
struct mt8183_afe_private *afe_priv = afe->platform_priv;
unsigned int value;
int ret;
if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
goto skip_regmap;
/* disable AFE */
regmap_update_bits(afe->regmap, AFE_DAC_CON0, AFE_ON_MASK_SFT, 0x0);
ret = regmap_read_poll_timeout(afe->regmap,
AFE_DAC_MON,
value,
(value & AFE_ON_RETM_MASK_SFT) == 0,
20,
1 * 1000 * 1000);
if (ret)
dev_warn(afe->dev, "%s(), ret %d\n", __func__, ret);
/* make sure all irq status are cleared, twice intended */
regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CLR, 0xffff, 0xffff);
regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CLR, 0xffff, 0xffff);
/* cache only */
regcache_cache_only(afe->regmap, true);
regcache_mark_dirty(afe->regmap);
skip_regmap:
return mt8183_afe_disable_clock(afe);
}
static int mt8183_afe_runtime_resume(struct device *dev)
{
struct mtk_base_afe *afe = dev_get_drvdata(dev);
struct mt8183_afe_private *afe_priv = afe->platform_priv;
int ret;
ret = mt8183_afe_enable_clock(afe);
if (ret)
return ret;
if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
goto skip_regmap;
regcache_cache_only(afe->regmap, false);
regcache_sync(afe->regmap);
/* enable audio sys DCM for power saving */
regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, 0x1 << 29, 0x1 << 29);
/* force cpu use 8_24 format when writing 32bit data */
regmap_update_bits(afe->regmap, AFE_MEMIF_MSB,
CPU_HD_ALIGN_MASK_SFT, 0 << CPU_HD_ALIGN_SFT);
/* set all output port to 24bit */
regmap_write(afe->regmap, AFE_CONN_24BIT, 0xffffffff);
regmap_write(afe->regmap, AFE_CONN_24BIT_1, 0xffffffff);
/* enable AFE */
regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1);
skip_regmap:
return 0;
}
static int mt8183_afe_component_probe(struct snd_soc_component *component)
{
return mtk_afe_add_sub_dai_control(component);
}
static const struct snd_soc_component_driver mt8183_afe_component = {
.name = AFE_PCM_NAME,
.probe = mt8183_afe_component_probe,
.pointer = mtk_afe_pcm_pointer,
.pcm_construct = mtk_afe_pcm_new,
};
static int mt8183_dai_memif_register(struct mtk_base_afe *afe)
{
struct mtk_base_afe_dai *dai;
dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
if (!dai)
return -ENOMEM;
list_add(&dai->list, &afe->sub_dais);
dai->dai_drivers = mt8183_memif_dai_driver;
dai->num_dai_drivers = ARRAY_SIZE(mt8183_memif_dai_driver);
dai->dapm_widgets = mt8183_memif_widgets;
dai->num_dapm_widgets = ARRAY_SIZE(mt8183_memif_widgets);
dai->dapm_routes = mt8183_memif_routes;
dai->num_dapm_routes = ARRAY_SIZE(mt8183_memif_routes);
return 0;
}
typedef int (*dai_register_cb)(struct mtk_base_afe *);
static const dai_register_cb dai_register_cbs[] = {
mt8183_dai_adda_register,
mt8183_dai_i2s_register,
mt8183_dai_pcm_register,
mt8183_dai_tdm_register,
mt8183_dai_hostless_register,
mt8183_dai_memif_register,
};
static int mt8183_afe_pcm_dev_probe(struct platform_device *pdev)
{
struct mtk_base_afe *afe;
struct mt8183_afe_private *afe_priv;
struct device *dev;
struct reset_control *rstc;
int i, irq_id, ret;
afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
if (!afe)
return -ENOMEM;
platform_set_drvdata(pdev, afe);
afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),
GFP_KERNEL);
if (!afe->platform_priv)
return -ENOMEM;
afe_priv = afe->platform_priv;
afe->dev = &pdev->dev;
dev = afe->dev;
/* initial audio related clock */
ret = mt8183_init_clock(afe);
if (ret) {
dev_err(dev, "init clock error\n");
return ret;
}
pm_runtime_enable(dev);
/* regmap init */
afe->regmap = syscon_node_to_regmap(dev->parent->of_node);
if (IS_ERR(afe->regmap)) {
dev_err(dev, "could not get regmap from parent\n");
ret = PTR_ERR(afe->regmap);
goto err_pm_disable;
}
ret = regmap_attach_dev(dev, afe->regmap, &mt8183_afe_regmap_config);
if (ret) {
dev_warn(dev, "regmap_attach_dev fail, ret %d\n", ret);
goto err_pm_disable;
}
rstc = devm_reset_control_get(dev, "audiosys");
if (IS_ERR(rstc)) {
ret = PTR_ERR(rstc);
dev_err(dev, "could not get audiosys reset:%d\n", ret);
goto err_pm_disable;
}
ret = reset_control_reset(rstc);
if (ret) {
dev_err(dev, "failed to trigger audio reset:%d\n", ret);
goto err_pm_disable;
}
/* enable clock for regcache get default value from hw */
afe_priv->pm_runtime_bypass_reg_ctl = true;
pm_runtime_get_sync(&pdev->dev);
ret = regmap_reinit_cache(afe->regmap, &mt8183_afe_regmap_config);
if (ret) {
dev_err(dev, "regmap_reinit_cache fail, ret %d\n", ret);
goto err_pm_disable;
}
pm_runtime_put_sync(&pdev->dev);
afe_priv->pm_runtime_bypass_reg_ctl = false;
regcache_cache_only(afe->regmap, true);
regcache_mark_dirty(afe->regmap);
/* init memif */
afe->memif_size = MT8183_MEMIF_NUM;
afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),
GFP_KERNEL);
if (!afe->memif) {
ret = -ENOMEM;
goto err_pm_disable;
}
for (i = 0; i < afe->memif_size; i++) {
afe->memif[i].data = &memif_data[i];
afe->memif[i].irq_usage = -1;
}
afe->memif[MT8183_MEMIF_HDMI].irq_usage = MT8183_IRQ_8;
afe->memif[MT8183_MEMIF_HDMI].const_irq = 1;
mutex_init(&afe->irq_alloc_lock);
/* init memif */
/* irq initialize */
afe->irqs_size = MT8183_IRQ_NUM;
afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
GFP_KERNEL);
if (!afe->irqs) {
ret = -ENOMEM;
goto err_pm_disable;
}
for (i = 0; i < afe->irqs_size; i++)
afe->irqs[i].irq_data = &irq_data[i];
/* request irq */
irq_id = platform_get_irq(pdev, 0);
if (irq_id < 0) {
ret = irq_id;
goto err_pm_disable;
}
ret = devm_request_irq(dev, irq_id, mt8183_afe_irq_handler,
IRQF_TRIGGER_NONE, "asys-isr", (void *)afe);
if (ret) {
dev_err(dev, "could not request_irq for asys-isr\n");
goto err_pm_disable;
}
/* init sub_dais */
INIT_LIST_HEAD(&afe->sub_dais);
for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) {
ret = dai_register_cbs[i](afe);
if (ret) {
dev_warn(afe->dev, "dai register i %d fail, ret %d\n",
i, ret);
goto err_pm_disable;
}
}
/* init dai_driver and component_driver */
ret = mtk_afe_combine_sub_dai(afe);
if (ret) {
dev_warn(afe->dev, "mtk_afe_combine_sub_dai fail, ret %d\n",
ret);
goto err_pm_disable;
}
afe->mtk_afe_hardware = &mt8183_afe_hardware;
afe->memif_fs = mt8183_memif_fs;
afe->irq_fs = mt8183_irq_fs;
afe->runtime_resume = mt8183_afe_runtime_resume;
afe->runtime_suspend = mt8183_afe_runtime_suspend;
/* register component */
ret = devm_snd_soc_register_component(&pdev->dev,
&mt8183_afe_component,
NULL, 0);
if (ret) {
dev_warn(dev, "err_platform\n");
goto err_pm_disable;
}
ret = devm_snd_soc_register_component(afe->dev,
&mt8183_afe_pcm_dai_component,
afe->dai_drivers,
afe->num_dai_drivers);
if (ret) {
dev_warn(dev, "err_dai_component\n");
goto err_pm_disable;
}
return ret;
err_pm_disable:
pm_runtime_disable(&pdev->dev);
return ret;
}
static void mt8183_afe_pcm_dev_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
if (!pm_runtime_status_suspended(&pdev->dev))
mt8183_afe_runtime_suspend(&pdev->dev);
}
static const struct of_device_id mt8183_afe_pcm_dt_match[] = {
{ .compatible = "mediatek,mt8183-audio", },
{},
};
MODULE_DEVICE_TABLE(of, mt8183_afe_pcm_dt_match);
static const struct dev_pm_ops mt8183_afe_pm_ops = {
SET_RUNTIME_PM_OPS(mt8183_afe_runtime_suspend,
mt8183_afe_runtime_resume, NULL)
};
static struct platform_driver mt8183_afe_pcm_driver = {
.driver = {
.name = "mt8183-audio",
.of_match_table = mt8183_afe_pcm_dt_match,
.pm = &mt8183_afe_pm_ops,
},
.probe = mt8183_afe_pcm_dev_probe,
.remove_new = mt8183_afe_pcm_dev_remove,
};
module_platform_driver(mt8183_afe_pcm_driver);
MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 8183");
MODULE_AUTHOR("KaiChieh Chuang <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/mediatek/mt8183/mt8183-afe-pcm.c |
// SPDX-License-Identifier: GPL-2.0
//
// mt8183-da7219-max98357.c
// -- MT8183-DA7219-MAX98357 ALSA SoC machine driver
//
// Copyright (c) 2018 MediaTek Inc.
// Author: Shunli Wang <[email protected]>
#include <linux/input.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/pinctrl/consumer.h>
#include <sound/jack.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include "../../codecs/da7219.h"
#include "../../codecs/rt1015.h"
#include "../common/mtk-afe-platform-driver.h"
#include "mt8183-afe-common.h"
#define DA7219_CODEC_DAI "da7219-hifi"
#define DA7219_DEV_NAME "da7219.5-001a"
#define RT1015_CODEC_DAI "rt1015-aif"
#define RT1015_DEV0_NAME "rt1015.6-0028"
#define RT1015_DEV1_NAME "rt1015.6-0029"
struct mt8183_da7219_max98357_priv {
struct snd_soc_jack headset_jack, hdmi_jack;
};
static struct snd_soc_jack_pin mt8183_da7219_max98357_jack_pins[] = {
{
.pin = "Headphone",
.mask = SND_JACK_HEADPHONE,
},
{
.pin = "Headset Mic",
.mask = SND_JACK_MICROPHONE,
},
{
.pin = "Line Out",
.mask = SND_JACK_LINEOUT,
},
};
static int mt8183_mt6358_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
unsigned int rate = params_rate(params);
unsigned int mclk_fs_ratio = 128;
unsigned int mclk_fs = rate * mclk_fs_ratio;
return snd_soc_dai_set_sysclk(asoc_rtd_to_cpu(rtd, 0),
0, mclk_fs, SND_SOC_CLOCK_OUT);
}
static const struct snd_soc_ops mt8183_mt6358_i2s_ops = {
.hw_params = mt8183_mt6358_i2s_hw_params,
};
static int mt8183_da7219_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai *codec_dai;
unsigned int rate = params_rate(params);
unsigned int mclk_fs_ratio = 256;
unsigned int mclk_fs = rate * mclk_fs_ratio;
unsigned int freq;
int ret = 0, j;
ret = snd_soc_dai_set_sysclk(asoc_rtd_to_cpu(rtd, 0), 0,
mclk_fs, SND_SOC_CLOCK_OUT);
if (ret < 0)
dev_err(rtd->dev, "failed to set cpu dai sysclk\n");
for_each_rtd_codec_dais(rtd, j, codec_dai) {
if (!strcmp(codec_dai->component->name, DA7219_DEV_NAME)) {
ret = snd_soc_dai_set_sysclk(codec_dai,
DA7219_CLKSRC_MCLK,
mclk_fs,
SND_SOC_CLOCK_IN);
if (ret < 0)
dev_err(rtd->dev, "failed to set sysclk\n");
if ((rate % 8000) == 0)
freq = DA7219_PLL_FREQ_OUT_98304;
else
freq = DA7219_PLL_FREQ_OUT_90316;
ret = snd_soc_dai_set_pll(codec_dai, 0,
DA7219_SYSCLK_PLL_SRM,
0, freq);
if (ret)
dev_err(rtd->dev, "failed to start PLL: %d\n",
ret);
}
}
return ret;
}
static int mt8183_da7219_hw_free(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai *codec_dai;
int ret = 0, j;
for_each_rtd_codec_dais(rtd, j, codec_dai) {
if (!strcmp(codec_dai->component->name, DA7219_DEV_NAME)) {
ret = snd_soc_dai_set_pll(codec_dai,
0, DA7219_SYSCLK_MCLK, 0, 0);
if (ret < 0) {
dev_err(rtd->dev, "failed to stop PLL: %d\n",
ret);
break;
}
}
}
return ret;
}
static const struct snd_soc_ops mt8183_da7219_i2s_ops = {
.hw_params = mt8183_da7219_i2s_hw_params,
.hw_free = mt8183_da7219_hw_free,
};
static int
mt8183_da7219_rt1015_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
unsigned int rate = params_rate(params);
struct snd_soc_dai *codec_dai;
int ret = 0, i;
for_each_rtd_codec_dais(rtd, i, codec_dai) {
if (!strcmp(codec_dai->component->name, RT1015_DEV0_NAME) ||
!strcmp(codec_dai->component->name, RT1015_DEV1_NAME)) {
ret = snd_soc_dai_set_pll(codec_dai, 0,
RT1015_PLL_S_BCLK,
rate * 64, rate * 256);
if (ret) {
dev_err(rtd->dev, "failed to set pll\n");
return ret;
}
ret = snd_soc_dai_set_sysclk(codec_dai,
RT1015_SCLK_S_PLL,
rate * 256,
SND_SOC_CLOCK_IN);
if (ret) {
dev_err(rtd->dev, "failed to set sysclk\n");
return ret;
}
}
}
return mt8183_da7219_i2s_hw_params(substream, params);
}
static const struct snd_soc_ops mt8183_da7219_rt1015_i2s_ops = {
.hw_params = mt8183_da7219_rt1015_i2s_hw_params,
.hw_free = mt8183_da7219_hw_free,
};
static int mt8183_i2s_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
struct snd_pcm_hw_params *params)
{
/* fix BE i2s format to S32_LE, clean param mask first */
snd_mask_reset_range(hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT),
0, (__force unsigned int)SNDRV_PCM_FORMAT_LAST);
params_set_format(params, SNDRV_PCM_FORMAT_S32_LE);
return 0;
}
static int mt8183_rt1015_i2s_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
struct snd_pcm_hw_params *params)
{
/* fix BE i2s format to S24_LE, clean param mask first */
snd_mask_reset_range(hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT),
0, (__force unsigned int)SNDRV_PCM_FORMAT_LAST);
params_set_format(params, SNDRV_PCM_FORMAT_S24_LE);
return 0;
}
static int
mt8183_da7219_max98357_startup(
struct snd_pcm_substream *substream)
{
static const unsigned int rates[] = {
48000,
};
static const struct snd_pcm_hw_constraint_list constraints_rates = {
.count = ARRAY_SIZE(rates),
.list = rates,
.mask = 0,
};
static const unsigned int channels[] = {
2,
};
static const struct snd_pcm_hw_constraint_list constraints_channels = {
.count = ARRAY_SIZE(channels),
.list = channels,
.mask = 0,
};
struct snd_pcm_runtime *runtime = substream->runtime;
snd_pcm_hw_constraint_list(runtime, 0,
SNDRV_PCM_HW_PARAM_RATE, &constraints_rates);
runtime->hw.channels_max = 2;
snd_pcm_hw_constraint_list(runtime, 0,
SNDRV_PCM_HW_PARAM_CHANNELS,
&constraints_channels);
runtime->hw.formats = SNDRV_PCM_FMTBIT_S16_LE;
snd_pcm_hw_constraint_msbits(runtime, 0, 16, 16);
return 0;
}
static const struct snd_soc_ops mt8183_da7219_max98357_ops = {
.startup = mt8183_da7219_max98357_startup,
};
static int
mt8183_da7219_max98357_bt_sco_startup(
struct snd_pcm_substream *substream)
{
static const unsigned int rates[] = {
8000, 16000
};
static const struct snd_pcm_hw_constraint_list constraints_rates = {
.count = ARRAY_SIZE(rates),
.list = rates,
.mask = 0,
};
static const unsigned int channels[] = {
1,
};
static const struct snd_pcm_hw_constraint_list constraints_channels = {
.count = ARRAY_SIZE(channels),
.list = channels,
.mask = 0,
};
struct snd_pcm_runtime *runtime = substream->runtime;
snd_pcm_hw_constraint_list(runtime, 0,
SNDRV_PCM_HW_PARAM_RATE, &constraints_rates);
runtime->hw.channels_max = 1;
snd_pcm_hw_constraint_list(runtime, 0,
SNDRV_PCM_HW_PARAM_CHANNELS,
&constraints_channels);
runtime->hw.formats = SNDRV_PCM_FMTBIT_S16_LE;
snd_pcm_hw_constraint_msbits(runtime, 0, 16, 16);
return 0;
}
static const struct snd_soc_ops mt8183_da7219_max98357_bt_sco_ops = {
.startup = mt8183_da7219_max98357_bt_sco_startup,
};
/* FE */
SND_SOC_DAILINK_DEFS(playback1,
DAILINK_COMP_ARRAY(COMP_CPU("DL1")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(playback2,
DAILINK_COMP_ARRAY(COMP_CPU("DL2")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(playback3,
DAILINK_COMP_ARRAY(COMP_CPU("DL3")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture1,
DAILINK_COMP_ARRAY(COMP_CPU("UL1")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture2,
DAILINK_COMP_ARRAY(COMP_CPU("UL2")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture3,
DAILINK_COMP_ARRAY(COMP_CPU("UL3")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(capture_mono,
DAILINK_COMP_ARRAY(COMP_CPU("UL_MONO_1")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(playback_hdmi,
DAILINK_COMP_ARRAY(COMP_CPU("HDMI")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
/* BE */
SND_SOC_DAILINK_DEFS(primary_codec,
DAILINK_COMP_ARRAY(COMP_CPU("ADDA")),
DAILINK_COMP_ARRAY(COMP_CODEC("mt6358-sound", "mt6358-snd-codec-aif1")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(pcm1,
DAILINK_COMP_ARRAY(COMP_CPU("PCM 1")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(pcm2,
DAILINK_COMP_ARRAY(COMP_CPU("PCM 2")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(i2s0,
DAILINK_COMP_ARRAY(COMP_CPU("I2S0")),
DAILINK_COMP_ARRAY(COMP_CODEC("bt-sco", "bt-sco-pcm")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(i2s1,
DAILINK_COMP_ARRAY(COMP_CPU("I2S1")),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(i2s2,
DAILINK_COMP_ARRAY(COMP_CPU("I2S2")),
DAILINK_COMP_ARRAY(COMP_CODEC(DA7219_DEV_NAME, DA7219_CODEC_DAI)),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(i2s3_max98357a,
DAILINK_COMP_ARRAY(COMP_CPU("I2S3")),
DAILINK_COMP_ARRAY(COMP_CODEC("max98357a", "HiFi"),
COMP_CODEC(DA7219_DEV_NAME, DA7219_CODEC_DAI)),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(i2s3_rt1015,
DAILINK_COMP_ARRAY(COMP_CPU("I2S3")),
DAILINK_COMP_ARRAY(COMP_CODEC(RT1015_DEV0_NAME, RT1015_CODEC_DAI),
COMP_CODEC(RT1015_DEV1_NAME, RT1015_CODEC_DAI),
COMP_CODEC(DA7219_DEV_NAME, DA7219_CODEC_DAI)),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(i2s3_rt1015p,
DAILINK_COMP_ARRAY(COMP_CPU("I2S3")),
DAILINK_COMP_ARRAY(COMP_CODEC("rt1015p", "HiFi"),
COMP_CODEC(DA7219_DEV_NAME, DA7219_CODEC_DAI)),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(i2s5,
DAILINK_COMP_ARRAY(COMP_CPU("I2S5")),
DAILINK_COMP_ARRAY(COMP_CODEC("bt-sco", "bt-sco-pcm")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(tdm,
DAILINK_COMP_ARRAY(COMP_CPU("TDM")),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "i2s-hifi")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
static int mt8183_da7219_max98357_hdmi_init(struct snd_soc_pcm_runtime *rtd)
{
struct mt8183_da7219_max98357_priv *priv =
snd_soc_card_get_drvdata(rtd->card);
int ret;
ret = snd_soc_card_jack_new(rtd->card, "HDMI Jack", SND_JACK_LINEOUT,
&priv->hdmi_jack);
if (ret)
return ret;
return snd_soc_component_set_jack(asoc_rtd_to_codec(rtd, 0)->component,
&priv->hdmi_jack, NULL);
}
static int mt8183_bt_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_component *cmpnt_afe =
snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt_afe);
int ret;
ret = mt8183_dai_i2s_set_share(afe, "I2S5", "I2S0");
if (ret) {
dev_err(rtd->dev, "Failed to set up shared clocks\n");
return ret;
}
return 0;
}
static int mt8183_da7219_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_component *cmpnt_afe =
snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt_afe);
int ret;
ret = mt8183_dai_i2s_set_share(afe, "I2S2", "I2S3");
if (ret) {
dev_err(rtd->dev, "Failed to set up shared clocks\n");
return ret;
}
return 0;
}
static struct snd_soc_dai_link mt8183_da7219_dai_links[] = {
/* FE */
{
.name = "Playback_1",
.stream_name = "Playback_1",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
.ops = &mt8183_da7219_max98357_ops,
SND_SOC_DAILINK_REG(playback1),
},
{
.name = "Playback_2",
.stream_name = "Playback_2",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
.ops = &mt8183_da7219_max98357_bt_sco_ops,
SND_SOC_DAILINK_REG(playback2),
},
{
.name = "Playback_3",
.stream_name = "Playback_3",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(playback3),
},
{
.name = "Capture_1",
.stream_name = "Capture_1",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_capture = 1,
.ops = &mt8183_da7219_max98357_bt_sco_ops,
SND_SOC_DAILINK_REG(capture1),
},
{
.name = "Capture_2",
.stream_name = "Capture_2",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(capture2),
},
{
.name = "Capture_3",
.stream_name = "Capture_3",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_capture = 1,
.ops = &mt8183_da7219_max98357_ops,
SND_SOC_DAILINK_REG(capture3),
},
{
.name = "Capture_Mono_1",
.stream_name = "Capture_Mono_1",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_capture = 1,
SND_SOC_DAILINK_REG(capture_mono),
},
{
.name = "Playback_HDMI",
.stream_name = "Playback_HDMI",
.trigger = {SND_SOC_DPCM_TRIGGER_PRE,
SND_SOC_DPCM_TRIGGER_PRE},
.dynamic = 1,
.dpcm_playback = 1,
SND_SOC_DAILINK_REG(playback_hdmi),
},
/* BE */
{
.name = "Primary Codec",
.no_pcm = 1,
.dpcm_playback = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(primary_codec),
},
{
.name = "PCM 1",
.no_pcm = 1,
.dpcm_playback = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(pcm1),
},
{
.name = "PCM 2",
.no_pcm = 1,
.dpcm_playback = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
SND_SOC_DAILINK_REG(pcm2),
},
{
.name = "I2S0",
.no_pcm = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
.be_hw_params_fixup = mt8183_i2s_hw_params_fixup,
.ops = &mt8183_mt6358_i2s_ops,
SND_SOC_DAILINK_REG(i2s0),
},
{
.name = "I2S1",
.no_pcm = 1,
.dpcm_playback = 1,
.ignore_suspend = 1,
.be_hw_params_fixup = mt8183_i2s_hw_params_fixup,
.ops = &mt8183_mt6358_i2s_ops,
SND_SOC_DAILINK_REG(i2s1),
},
{
.name = "I2S2",
.no_pcm = 1,
.dpcm_capture = 1,
.ignore_suspend = 1,
.be_hw_params_fixup = mt8183_i2s_hw_params_fixup,
.ops = &mt8183_da7219_i2s_ops,
.init = &mt8183_da7219_init,
SND_SOC_DAILINK_REG(i2s2),
},
{
.name = "I2S3",
.no_pcm = 1,
.dpcm_playback = 1,
.ignore_suspend = 1,
},
{
.name = "I2S5",
.no_pcm = 1,
.dpcm_playback = 1,
.ignore_suspend = 1,
.be_hw_params_fixup = mt8183_i2s_hw_params_fixup,
.ops = &mt8183_mt6358_i2s_ops,
.init = &mt8183_bt_init,
SND_SOC_DAILINK_REG(i2s5),
},
{
.name = "TDM",
.no_pcm = 1,
.dai_fmt = SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_IB_IF |
SND_SOC_DAIFMT_CBM_CFM,
.dpcm_playback = 1,
.ignore_suspend = 1,
.be_hw_params_fixup = mt8183_i2s_hw_params_fixup,
.ignore = 1,
.init = mt8183_da7219_max98357_hdmi_init,
SND_SOC_DAILINK_REG(tdm),
},
};
static int
mt8183_da7219_max98357_headset_init(struct snd_soc_component *component)
{
int ret;
struct mt8183_da7219_max98357_priv *priv =
snd_soc_card_get_drvdata(component->card);
/* Enable Headset and 4 Buttons Jack detection */
ret = snd_soc_card_jack_new_pins(component->card,
"Headset Jack",
SND_JACK_HEADSET |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3 |
SND_JACK_LINEOUT,
&priv->headset_jack,
mt8183_da7219_max98357_jack_pins,
ARRAY_SIZE(mt8183_da7219_max98357_jack_pins));
if (ret)
return ret;
snd_jack_set_key(
priv->headset_jack.jack, SND_JACK_BTN_0, KEY_PLAYPAUSE);
snd_jack_set_key(
priv->headset_jack.jack, SND_JACK_BTN_1, KEY_VOLUMEUP);
snd_jack_set_key(
priv->headset_jack.jack, SND_JACK_BTN_2, KEY_VOLUMEDOWN);
snd_jack_set_key(
priv->headset_jack.jack, SND_JACK_BTN_3, KEY_VOICECOMMAND);
snd_soc_component_set_jack(component, &priv->headset_jack, NULL);
return 0;
}
static struct snd_soc_aux_dev mt8183_da7219_max98357_headset_dev = {
.dlc = COMP_EMPTY(),
.init = mt8183_da7219_max98357_headset_init,
};
static struct snd_soc_codec_conf mt6358_codec_conf[] = {
{
.dlc = COMP_CODEC_CONF("mt6358-sound"),
.name_prefix = "Mt6358",
},
};
static const struct snd_kcontrol_new mt8183_da7219_max98357_snd_controls[] = {
SOC_DAPM_PIN_SWITCH("Headphone"),
SOC_DAPM_PIN_SWITCH("Headset Mic"),
SOC_DAPM_PIN_SWITCH("Speakers"),
SOC_DAPM_PIN_SWITCH("Line Out"),
};
static const
struct snd_soc_dapm_widget mt8183_da7219_max98357_dapm_widgets[] = {
SND_SOC_DAPM_HP("Headphone", NULL),
SND_SOC_DAPM_MIC("Headset Mic", NULL),
SND_SOC_DAPM_SPK("Speakers", NULL),
SND_SOC_DAPM_SPK("Line Out", NULL),
SND_SOC_DAPM_PINCTRL("TDM_OUT_PINCTRL",
"aud_tdm_out_on", "aud_tdm_out_off"),
};
static const struct snd_soc_dapm_route mt8183_da7219_max98357_dapm_routes[] = {
{"Speakers", NULL, "Speaker"},
{"I2S Playback", NULL, "TDM_OUT_PINCTRL"},
};
static struct snd_soc_card mt8183_da7219_max98357_card = {
.name = "mt8183_da7219_max98357",
.owner = THIS_MODULE,
.controls = mt8183_da7219_max98357_snd_controls,
.num_controls = ARRAY_SIZE(mt8183_da7219_max98357_snd_controls),
.dapm_widgets = mt8183_da7219_max98357_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(mt8183_da7219_max98357_dapm_widgets),
.dapm_routes = mt8183_da7219_max98357_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(mt8183_da7219_max98357_dapm_routes),
.dai_link = mt8183_da7219_dai_links,
.num_links = ARRAY_SIZE(mt8183_da7219_dai_links),
.aux_dev = &mt8183_da7219_max98357_headset_dev,
.num_aux_devs = 1,
.codec_conf = mt6358_codec_conf,
.num_configs = ARRAY_SIZE(mt6358_codec_conf),
};
static struct snd_soc_codec_conf mt8183_da7219_rt1015_codec_conf[] = {
{
.dlc = COMP_CODEC_CONF("mt6358-sound"),
.name_prefix = "Mt6358",
},
{
.dlc = COMP_CODEC_CONF(RT1015_DEV0_NAME),
.name_prefix = "Left",
},
{
.dlc = COMP_CODEC_CONF(RT1015_DEV1_NAME),
.name_prefix = "Right",
},
};
static const struct snd_kcontrol_new mt8183_da7219_rt1015_snd_controls[] = {
SOC_DAPM_PIN_SWITCH("Headphone"),
SOC_DAPM_PIN_SWITCH("Headset Mic"),
SOC_DAPM_PIN_SWITCH("Left Spk"),
SOC_DAPM_PIN_SWITCH("Right Spk"),
SOC_DAPM_PIN_SWITCH("Line Out"),
};
static const
struct snd_soc_dapm_widget mt8183_da7219_rt1015_dapm_widgets[] = {
SND_SOC_DAPM_HP("Headphone", NULL),
SND_SOC_DAPM_MIC("Headset Mic", NULL),
SND_SOC_DAPM_SPK("Left Spk", NULL),
SND_SOC_DAPM_SPK("Right Spk", NULL),
SND_SOC_DAPM_LINE("Line Out", NULL),
SND_SOC_DAPM_PINCTRL("TDM_OUT_PINCTRL",
"aud_tdm_out_on", "aud_tdm_out_off"),
};
static const struct snd_soc_dapm_route mt8183_da7219_rt1015_dapm_routes[] = {
{"Left Spk", NULL, "Left SPO"},
{"Right Spk", NULL, "Right SPO"},
{"I2S Playback", NULL, "TDM_OUT_PINCTRL"},
};
static struct snd_soc_card mt8183_da7219_rt1015_card = {
.name = "mt8183_da7219_rt1015",
.owner = THIS_MODULE,
.controls = mt8183_da7219_rt1015_snd_controls,
.num_controls = ARRAY_SIZE(mt8183_da7219_rt1015_snd_controls),
.dapm_widgets = mt8183_da7219_rt1015_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(mt8183_da7219_rt1015_dapm_widgets),
.dapm_routes = mt8183_da7219_rt1015_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(mt8183_da7219_rt1015_dapm_routes),
.dai_link = mt8183_da7219_dai_links,
.num_links = ARRAY_SIZE(mt8183_da7219_dai_links),
.aux_dev = &mt8183_da7219_max98357_headset_dev,
.num_aux_devs = 1,
.codec_conf = mt8183_da7219_rt1015_codec_conf,
.num_configs = ARRAY_SIZE(mt8183_da7219_rt1015_codec_conf),
};
static struct snd_soc_card mt8183_da7219_rt1015p_card = {
.name = "mt8183_da7219_rt1015p",
.owner = THIS_MODULE,
.controls = mt8183_da7219_max98357_snd_controls,
.num_controls = ARRAY_SIZE(mt8183_da7219_max98357_snd_controls),
.dapm_widgets = mt8183_da7219_max98357_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(mt8183_da7219_max98357_dapm_widgets),
.dapm_routes = mt8183_da7219_max98357_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(mt8183_da7219_max98357_dapm_routes),
.dai_link = mt8183_da7219_dai_links,
.num_links = ARRAY_SIZE(mt8183_da7219_dai_links),
.aux_dev = &mt8183_da7219_max98357_headset_dev,
.num_aux_devs = 1,
.codec_conf = mt6358_codec_conf,
.num_configs = ARRAY_SIZE(mt6358_codec_conf),
};
static int mt8183_da7219_max98357_dev_probe(struct platform_device *pdev)
{
struct snd_soc_card *card;
struct device_node *platform_node, *hdmi_codec;
struct snd_soc_dai_link *dai_link;
struct mt8183_da7219_max98357_priv *priv;
struct pinctrl *pinctrl;
int ret, i;
platform_node = of_parse_phandle(pdev->dev.of_node,
"mediatek,platform", 0);
if (!platform_node) {
dev_err(&pdev->dev, "Property 'platform' missing or invalid\n");
return -EINVAL;
}
card = (struct snd_soc_card *)of_device_get_match_data(&pdev->dev);
if (!card) {
ret = -EINVAL;
goto put_platform_node;
}
card->dev = &pdev->dev;
hdmi_codec = of_parse_phandle(pdev->dev.of_node,
"mediatek,hdmi-codec", 0);
for_each_card_prelinks(card, i, dai_link) {
if (strcmp(dai_link->name, "I2S3") == 0) {
if (card == &mt8183_da7219_max98357_card) {
dai_link->be_hw_params_fixup =
mt8183_i2s_hw_params_fixup;
dai_link->ops = &mt8183_da7219_i2s_ops;
dai_link->cpus = i2s3_max98357a_cpus;
dai_link->num_cpus =
ARRAY_SIZE(i2s3_max98357a_cpus);
dai_link->codecs = i2s3_max98357a_codecs;
dai_link->num_codecs =
ARRAY_SIZE(i2s3_max98357a_codecs);
dai_link->platforms = i2s3_max98357a_platforms;
dai_link->num_platforms =
ARRAY_SIZE(i2s3_max98357a_platforms);
} else if (card == &mt8183_da7219_rt1015_card) {
dai_link->be_hw_params_fixup =
mt8183_rt1015_i2s_hw_params_fixup;
dai_link->ops = &mt8183_da7219_rt1015_i2s_ops;
dai_link->cpus = i2s3_rt1015_cpus;
dai_link->num_cpus =
ARRAY_SIZE(i2s3_rt1015_cpus);
dai_link->codecs = i2s3_rt1015_codecs;
dai_link->num_codecs =
ARRAY_SIZE(i2s3_rt1015_codecs);
dai_link->platforms = i2s3_rt1015_platforms;
dai_link->num_platforms =
ARRAY_SIZE(i2s3_rt1015_platforms);
} else if (card == &mt8183_da7219_rt1015p_card) {
dai_link->be_hw_params_fixup =
mt8183_rt1015_i2s_hw_params_fixup;
dai_link->ops = &mt8183_da7219_i2s_ops;
dai_link->cpus = i2s3_rt1015p_cpus;
dai_link->num_cpus =
ARRAY_SIZE(i2s3_rt1015p_cpus);
dai_link->codecs = i2s3_rt1015p_codecs;
dai_link->num_codecs =
ARRAY_SIZE(i2s3_rt1015p_codecs);
dai_link->platforms = i2s3_rt1015p_platforms;
dai_link->num_platforms =
ARRAY_SIZE(i2s3_rt1015p_platforms);
}
}
if (hdmi_codec && strcmp(dai_link->name, "TDM") == 0) {
dai_link->codecs->of_node = hdmi_codec;
dai_link->ignore = 0;
}
if (!dai_link->platforms->name)
dai_link->platforms->of_node = platform_node;
}
mt8183_da7219_max98357_headset_dev.dlc.of_node =
of_parse_phandle(pdev->dev.of_node,
"mediatek,headset-codec", 0);
if (!mt8183_da7219_max98357_headset_dev.dlc.of_node) {
dev_err(&pdev->dev,
"Property 'mediatek,headset-codec' missing/invalid\n");
ret = -EINVAL;
goto put_hdmi_codec;
}
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv) {
ret = -ENOMEM;
goto put_hdmi_codec;
}
snd_soc_card_set_drvdata(card, priv);
pinctrl = devm_pinctrl_get_select(&pdev->dev, PINCTRL_STATE_DEFAULT);
if (IS_ERR(pinctrl)) {
ret = PTR_ERR(pinctrl);
dev_err(&pdev->dev, "%s failed to select default state %d\n",
__func__, ret);
goto put_hdmi_codec;
}
ret = devm_snd_soc_register_card(&pdev->dev, card);
put_hdmi_codec:
of_node_put(hdmi_codec);
put_platform_node:
of_node_put(platform_node);
return ret;
}
#ifdef CONFIG_OF
static const struct of_device_id mt8183_da7219_max98357_dt_match[] = {
{
.compatible = "mediatek,mt8183_da7219_max98357",
.data = &mt8183_da7219_max98357_card,
},
{
.compatible = "mediatek,mt8183_da7219_rt1015",
.data = &mt8183_da7219_rt1015_card,
},
{
.compatible = "mediatek,mt8183_da7219_rt1015p",
.data = &mt8183_da7219_rt1015p_card,
},
{}
};
MODULE_DEVICE_TABLE(of, mt8183_da7219_max98357_dt_match);
#endif
static struct platform_driver mt8183_da7219_max98357_driver = {
.driver = {
.name = "mt8183_da7219",
#ifdef CONFIG_OF
.of_match_table = mt8183_da7219_max98357_dt_match,
#endif
.pm = &snd_soc_pm_ops,
},
.probe = mt8183_da7219_max98357_dev_probe,
};
module_platform_driver(mt8183_da7219_max98357_driver);
/* Module information */
MODULE_DESCRIPTION("MT8183-DA7219-MAX98357 ALSA SoC machine driver");
MODULE_AUTHOR("Shunli Wang <[email protected]>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("mt8183_da7219_max98357 soc card");
| linux-master | sound/soc/mediatek/mt8183/mt8183-da7219-max98357.c |
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