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// SPDX-License-Identifier: GPL-2.0
//
// sgtl5000.c -- SGTL5000 ALSA SoC Audio driver
//
// Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/clk.h>
#include <linux/log2.h>
#include <linux/regmap.h>
#include <linux/regulator/driver.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/consumer.h>
#include <linux/of_device.h>
#include <sound/core.h>
#include <sound/tlv.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include "sgtl5000.h"
#define SGTL5000_DAP_REG_OFFSET 0x0100
#define SGTL5000_MAX_REG_OFFSET 0x013A
/* Delay for the VAG ramp up */
#define SGTL5000_VAG_POWERUP_DELAY 500 /* ms */
/* Delay for the VAG ramp down */
#define SGTL5000_VAG_POWERDOWN_DELAY 500 /* ms */
#define SGTL5000_OUTPUTS_MUTE (SGTL5000_HP_MUTE | SGTL5000_LINE_OUT_MUTE)
/* default value of sgtl5000 registers */
static const struct reg_default sgtl5000_reg_defaults[] = {
{ SGTL5000_CHIP_DIG_POWER, 0x0000 },
{ SGTL5000_CHIP_I2S_CTRL, 0x0010 },
{ SGTL5000_CHIP_SSS_CTRL, 0x0010 },
{ SGTL5000_CHIP_ADCDAC_CTRL, 0x020c },
{ SGTL5000_CHIP_DAC_VOL, 0x3c3c },
{ SGTL5000_CHIP_PAD_STRENGTH, 0x015f },
{ SGTL5000_CHIP_ANA_ADC_CTRL, 0x0000 },
{ SGTL5000_CHIP_ANA_HP_CTRL, 0x1818 },
{ SGTL5000_CHIP_ANA_CTRL, 0x0111 },
{ SGTL5000_CHIP_REF_CTRL, 0x0000 },
{ SGTL5000_CHIP_MIC_CTRL, 0x0000 },
{ SGTL5000_CHIP_LINE_OUT_CTRL, 0x0000 },
{ SGTL5000_CHIP_LINE_OUT_VOL, 0x0404 },
{ SGTL5000_CHIP_PLL_CTRL, 0x5000 },
{ SGTL5000_CHIP_CLK_TOP_CTRL, 0x0000 },
{ SGTL5000_CHIP_ANA_STATUS, 0x0000 },
{ SGTL5000_CHIP_SHORT_CTRL, 0x0000 },
{ SGTL5000_CHIP_ANA_TEST2, 0x0000 },
{ SGTL5000_DAP_CTRL, 0x0000 },
{ SGTL5000_DAP_PEQ, 0x0000 },
{ SGTL5000_DAP_BASS_ENHANCE, 0x0040 },
{ SGTL5000_DAP_BASS_ENHANCE_CTRL, 0x051f },
{ SGTL5000_DAP_AUDIO_EQ, 0x0000 },
{ SGTL5000_DAP_SURROUND, 0x0040 },
{ SGTL5000_DAP_EQ_BASS_BAND0, 0x002f },
{ SGTL5000_DAP_EQ_BASS_BAND1, 0x002f },
{ SGTL5000_DAP_EQ_BASS_BAND2, 0x002f },
{ SGTL5000_DAP_EQ_BASS_BAND3, 0x002f },
{ SGTL5000_DAP_EQ_BASS_BAND4, 0x002f },
{ SGTL5000_DAP_MAIN_CHAN, 0x8000 },
{ SGTL5000_DAP_MIX_CHAN, 0x0000 },
{ SGTL5000_DAP_AVC_CTRL, 0x5100 },
{ SGTL5000_DAP_AVC_THRESHOLD, 0x1473 },
{ SGTL5000_DAP_AVC_ATTACK, 0x0028 },
{ SGTL5000_DAP_AVC_DECAY, 0x0050 },
};
/* AVC: Threshold dB -> register: pre-calculated values */
static const u16 avc_thr_db2reg[97] = {
0x5168, 0x488E, 0x40AA, 0x39A1, 0x335D, 0x2DC7, 0x28CC, 0x245D, 0x2068,
0x1CE2, 0x19BE, 0x16F1, 0x1472, 0x1239, 0x103E, 0x0E7A, 0x0CE6, 0x0B7F,
0x0A3F, 0x0922, 0x0824, 0x0741, 0x0677, 0x05C3, 0x0522, 0x0493, 0x0414,
0x03A2, 0x033D, 0x02E3, 0x0293, 0x024B, 0x020B, 0x01D2, 0x019F, 0x0172,
0x014A, 0x0126, 0x0106, 0x00E9, 0x00D0, 0x00B9, 0x00A5, 0x0093, 0x0083,
0x0075, 0x0068, 0x005D, 0x0052, 0x0049, 0x0041, 0x003A, 0x0034, 0x002E,
0x0029, 0x0025, 0x0021, 0x001D, 0x001A, 0x0017, 0x0014, 0x0012, 0x0010,
0x000E, 0x000D, 0x000B, 0x000A, 0x0009, 0x0008, 0x0007, 0x0006, 0x0005,
0x0005, 0x0004, 0x0004, 0x0003, 0x0003, 0x0002, 0x0002, 0x0002, 0x0002,
0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000};
/* regulator supplies for sgtl5000, VDDD is an optional external supply */
enum sgtl5000_regulator_supplies {
VDDA,
VDDIO,
VDDD,
SGTL5000_SUPPLY_NUM
};
/* vddd is optional supply */
static const char *supply_names[SGTL5000_SUPPLY_NUM] = {
"VDDA",
"VDDIO",
"VDDD"
};
#define LDO_VOLTAGE 1200000
#define LINREG_VDDD ((1600 - LDO_VOLTAGE / 1000) / 50)
enum sgtl5000_micbias_resistor {
SGTL5000_MICBIAS_OFF = 0,
SGTL5000_MICBIAS_2K = 2,
SGTL5000_MICBIAS_4K = 4,
SGTL5000_MICBIAS_8K = 8,
};
enum {
I2S_LRCLK_STRENGTH_DISABLE,
I2S_LRCLK_STRENGTH_LOW,
I2S_LRCLK_STRENGTH_MEDIUM,
I2S_LRCLK_STRENGTH_HIGH,
};
enum {
I2S_SCLK_STRENGTH_DISABLE,
I2S_SCLK_STRENGTH_LOW,
I2S_SCLK_STRENGTH_MEDIUM,
I2S_SCLK_STRENGTH_HIGH,
};
enum {
HP_POWER_EVENT,
DAC_POWER_EVENT,
ADC_POWER_EVENT,
LAST_POWER_EVENT = ADC_POWER_EVENT
};
/* sgtl5000 private structure in codec */
struct sgtl5000_priv {
int sysclk; /* sysclk rate */
int master; /* i2s master or not */
int fmt; /* i2s data format */
struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM];
int num_supplies;
struct regmap *regmap;
struct clk *mclk;
int revision;
u8 micbias_resistor;
u8 micbias_voltage;
u8 lrclk_strength;
u8 sclk_strength;
u16 mute_state[LAST_POWER_EVENT + 1];
};
static inline int hp_sel_input(struct snd_soc_component *component)
{
return (snd_soc_component_read(component, SGTL5000_CHIP_ANA_CTRL) &
SGTL5000_HP_SEL_MASK) >> SGTL5000_HP_SEL_SHIFT;
}
static inline u16 mute_output(struct snd_soc_component *component,
u16 mute_mask)
{
u16 mute_reg = snd_soc_component_read(component,
SGTL5000_CHIP_ANA_CTRL);
snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_CTRL,
mute_mask, mute_mask);
return mute_reg;
}
static inline void restore_output(struct snd_soc_component *component,
u16 mute_mask, u16 mute_reg)
{
snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_CTRL,
mute_mask, mute_reg);
}
static void vag_power_on(struct snd_soc_component *component, u32 source)
{
if (snd_soc_component_read(component, SGTL5000_CHIP_ANA_POWER) &
SGTL5000_VAG_POWERUP)
return;
snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,
SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP);
/* When VAG powering on to get local loop from Line-In, the sleep
* is required to avoid loud pop.
*/
if (hp_sel_input(component) == SGTL5000_HP_SEL_LINE_IN &&
source == HP_POWER_EVENT)
msleep(SGTL5000_VAG_POWERUP_DELAY);
}
static int vag_power_consumers(struct snd_soc_component *component,
u16 ana_pwr_reg, u32 source)
{
int consumers = 0;
/* count dac/adc consumers unconditional */
if (ana_pwr_reg & SGTL5000_DAC_POWERUP)
consumers++;
if (ana_pwr_reg & SGTL5000_ADC_POWERUP)
consumers++;
/*
* If the event comes from HP and Line-In is selected,
* current action is 'DAC to be powered down'.
* As HP_POWERUP is not set when HP muxed to line-in,
* we need to keep VAG power ON.
*/
if (source == HP_POWER_EVENT) {
if (hp_sel_input(component) == SGTL5000_HP_SEL_LINE_IN)
consumers++;
} else {
if (ana_pwr_reg & SGTL5000_HP_POWERUP)
consumers++;
}
return consumers;
}
static void vag_power_off(struct snd_soc_component *component, u32 source)
{
u16 ana_pwr = snd_soc_component_read(component,
SGTL5000_CHIP_ANA_POWER);
if (!(ana_pwr & SGTL5000_VAG_POWERUP))
return;
/*
* This function calls when any of VAG power consumers is disappearing.
* Thus, if there is more than one consumer at the moment, as minimum
* one consumer will definitely stay after the end of the current
* event.
* Don't clear VAG_POWERUP if 2 or more consumers of VAG present:
* - LINE_IN (for HP events) / HP (for DAC/ADC events)
* - DAC
* - ADC
* (the current consumer is disappearing right now)
*/
if (vag_power_consumers(component, ana_pwr, source) >= 2)
return;
snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,
SGTL5000_VAG_POWERUP, 0);
/* In power down case, we need wait 400-1000 ms
* when VAG fully ramped down.
* As longer we wait, as smaller pop we've got.
*/
msleep(SGTL5000_VAG_POWERDOWN_DELAY);
}
/*
* mic_bias power on/off share the same register bits with
* output impedance of mic bias, when power on mic bias, we
* need reclaim it to impedance value.
* 0x0 = Powered off
* 0x1 = 2Kohm
* 0x2 = 4Kohm
* 0x3 = 8Kohm
*/
static int mic_bias_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
/* change mic bias resistor */
snd_soc_component_update_bits(component, SGTL5000_CHIP_MIC_CTRL,
SGTL5000_BIAS_R_MASK,
sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_component_update_bits(component, SGTL5000_CHIP_MIC_CTRL,
SGTL5000_BIAS_R_MASK, 0);
break;
}
return 0;
}
static int vag_and_mute_control(struct snd_soc_component *component,
int event, int event_source)
{
static const u16 mute_mask[] = {
/*
* Mask for HP_POWER_EVENT.
* Muxing Headphones have to be wrapped with mute/unmute
* headphones only.
*/
SGTL5000_HP_MUTE,
/*
* Masks for DAC_POWER_EVENT/ADC_POWER_EVENT.
* Muxing DAC or ADC block have to wrapped with mute/unmute
* both headphones and line-out.
*/
SGTL5000_OUTPUTS_MUTE,
SGTL5000_OUTPUTS_MUTE
};
struct sgtl5000_priv *sgtl5000 =
snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
sgtl5000->mute_state[event_source] =
mute_output(component, mute_mask[event_source]);
break;
case SND_SOC_DAPM_POST_PMU:
vag_power_on(component, event_source);
restore_output(component, mute_mask[event_source],
sgtl5000->mute_state[event_source]);
break;
case SND_SOC_DAPM_PRE_PMD:
sgtl5000->mute_state[event_source] =
mute_output(component, mute_mask[event_source]);
vag_power_off(component, event_source);
break;
case SND_SOC_DAPM_POST_PMD:
restore_output(component, mute_mask[event_source],
sgtl5000->mute_state[event_source]);
break;
default:
break;
}
return 0;
}
/*
* Mute Headphone when power it up/down.
* Control VAG power on HP power path.
*/
static int headphone_pga_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
return vag_and_mute_control(component, event, HP_POWER_EVENT);
}
/* As manual describes, ADC/DAC powering up/down requires
* to mute outputs to avoid pops.
* Control VAG power on ADC/DAC power path.
*/
static int adc_updown_depop(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
return vag_and_mute_control(component, event, ADC_POWER_EVENT);
}
static int dac_updown_depop(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
return vag_and_mute_control(component, event, DAC_POWER_EVENT);
}
/* input sources for ADC */
static const char *adc_mux_text[] = {
"MIC_IN", "LINE_IN"
};
static SOC_ENUM_SINGLE_DECL(adc_enum,
SGTL5000_CHIP_ANA_CTRL, 2,
adc_mux_text);
static const struct snd_kcontrol_new adc_mux =
SOC_DAPM_ENUM("Capture Mux", adc_enum);
/* input sources for headphone */
static const char *hp_mux_text[] = {
"DAC", "LINE_IN"
};
static SOC_ENUM_SINGLE_DECL(hp_enum,
SGTL5000_CHIP_ANA_CTRL, 6,
hp_mux_text);
static const struct snd_kcontrol_new hp_mux =
SOC_DAPM_ENUM("Headphone Mux", hp_enum);
/* input sources for DAC */
static const char *dac_mux_text[] = {
"ADC", "I2S", "Rsvrd", "DAP"
};
static SOC_ENUM_SINGLE_DECL(dac_enum,
SGTL5000_CHIP_SSS_CTRL, SGTL5000_DAC_SEL_SHIFT,
dac_mux_text);
static const struct snd_kcontrol_new dac_mux =
SOC_DAPM_ENUM("Digital Input Mux", dac_enum);
/* input sources for DAP */
static const char *dap_mux_text[] = {
"ADC", "I2S"
};
static SOC_ENUM_SINGLE_DECL(dap_enum,
SGTL5000_CHIP_SSS_CTRL, SGTL5000_DAP_SEL_SHIFT,
dap_mux_text);
static const struct snd_kcontrol_new dap_mux =
SOC_DAPM_ENUM("DAP Mux", dap_enum);
/* input sources for DAP mix */
static const char *dapmix_mux_text[] = {
"ADC", "I2S"
};
static SOC_ENUM_SINGLE_DECL(dapmix_enum,
SGTL5000_CHIP_SSS_CTRL, SGTL5000_DAP_MIX_SEL_SHIFT,
dapmix_mux_text);
static const struct snd_kcontrol_new dapmix_mux =
SOC_DAPM_ENUM("DAP MIX Mux", dapmix_enum);
static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("LINE_IN"),
SND_SOC_DAPM_INPUT("MIC_IN"),
SND_SOC_DAPM_OUTPUT("HP_OUT"),
SND_SOC_DAPM_OUTPUT("LINE_OUT"),
SND_SOC_DAPM_SUPPLY("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0,
mic_bias_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_PGA_E("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0,
headphone_pga_event,
SND_SOC_DAPM_PRE_POST_PMU |
SND_SOC_DAPM_PRE_POST_PMD),
SND_SOC_DAPM_PGA("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0),
SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux),
SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &hp_mux),
SND_SOC_DAPM_MUX("Digital Input Mux", SND_SOC_NOPM, 0, 0, &dac_mux),
SND_SOC_DAPM_MUX("DAP Mux", SGTL5000_DAP_CTRL, 0, 0, &dap_mux),
SND_SOC_DAPM_MUX("DAP MIX Mux", SGTL5000_DAP_CTRL, 4, 0, &dapmix_mux),
SND_SOC_DAPM_MIXER("DAP", SGTL5000_CHIP_DIG_POWER, 4, 0, NULL, 0),
/* aif for i2s input */
SND_SOC_DAPM_AIF_IN("AIFIN", "Playback",
0, SGTL5000_CHIP_DIG_POWER,
0, 0),
/* aif for i2s output */
SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture",
0, SGTL5000_CHIP_DIG_POWER,
1, 0),
SND_SOC_DAPM_ADC_E("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0,
adc_updown_depop, SND_SOC_DAPM_PRE_POST_PMU |
SND_SOC_DAPM_PRE_POST_PMD),
SND_SOC_DAPM_DAC_E("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0,
dac_updown_depop, SND_SOC_DAPM_PRE_POST_PMU |
SND_SOC_DAPM_PRE_POST_PMD),
};
/* routes for sgtl5000 */
static const struct snd_soc_dapm_route sgtl5000_dapm_routes[] = {
{"Capture Mux", "LINE_IN", "LINE_IN"}, /* line_in --> adc_mux */
{"Capture Mux", "MIC_IN", "MIC_IN"}, /* mic_in --> adc_mux */
{"ADC", NULL, "Capture Mux"}, /* adc_mux --> adc */
{"AIFOUT", NULL, "ADC"}, /* adc --> i2s_out */
{"DAP Mux", "ADC", "ADC"}, /* adc --> DAP mux */
{"DAP Mux", NULL, "AIFIN"}, /* i2s --> DAP mux */
{"DAP", NULL, "DAP Mux"}, /* DAP mux --> dap */
{"DAP MIX Mux", "ADC", "ADC"}, /* adc --> DAP MIX mux */
{"DAP MIX Mux", NULL, "AIFIN"}, /* i2s --> DAP MIX mux */
{"DAP", NULL, "DAP MIX Mux"}, /* DAP MIX mux --> dap */
{"Digital Input Mux", "ADC", "ADC"}, /* adc --> audio mux */
{"Digital Input Mux", NULL, "AIFIN"}, /* i2s --> audio mux */
{"Digital Input Mux", NULL, "DAP"}, /* dap --> audio mux */
{"DAC", NULL, "Digital Input Mux"}, /* audio mux --> dac */
{"Headphone Mux", "DAC", "DAC"}, /* dac --> hp_mux */
{"LO", NULL, "DAC"}, /* dac --> line_out */
{"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */
{"HP", NULL, "Headphone Mux"}, /* hp_mux --> hp */
{"LINE_OUT", NULL, "LO"},
{"HP_OUT", NULL, "HP"},
};
/* custom function to fetch info of PCM playback volume */
static int dac_info_volsw(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
uinfo->count = 2;
uinfo->value.integer.min = 0;
uinfo->value.integer.max = 0xfc - 0x3c;
return 0;
}
/*
* custom function to get of PCM playback volume
*
* dac volume register
* 15-------------8-7--------------0
* | R channel vol | L channel vol |
* -------------------------------
*
* PCM volume with 0.5017 dB steps from 0 to -90 dB
*
* register values map to dB
* 0x3B and less = Reserved
* 0x3C = 0 dB
* 0x3D = -0.5 dB
* 0xF0 = -90 dB
* 0xFC and greater = Muted
*
* register value map to userspace value
*
* register value 0x3c(0dB) 0xf0(-90dB)0xfc
* ------------------------------
* userspace value 0xc0 0
*/
static int dac_get_volsw(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
int reg;
int l;
int r;
reg = snd_soc_component_read(component, SGTL5000_CHIP_DAC_VOL);
/* get left channel volume */
l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT;
/* get right channel volume */
r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT;
/* make sure value fall in (0x3c,0xfc) */
l = clamp(l, 0x3c, 0xfc);
r = clamp(r, 0x3c, 0xfc);
/* invert it and map to userspace value */
l = 0xfc - l;
r = 0xfc - r;
ucontrol->value.integer.value[0] = l;
ucontrol->value.integer.value[1] = r;
return 0;
}
/*
* custom function to put of PCM playback volume
*
* dac volume register
* 15-------------8-7--------------0
* | R channel vol | L channel vol |
* -------------------------------
*
* PCM volume with 0.5017 dB steps from 0 to -90 dB
*
* register values map to dB
* 0x3B and less = Reserved
* 0x3C = 0 dB
* 0x3D = -0.5 dB
* 0xF0 = -90 dB
* 0xFC and greater = Muted
*
* userspace value map to register value
*
* userspace value 0xc0 0
* ------------------------------
* register value 0x3c(0dB) 0xf0(-90dB)0xfc
*/
static int dac_put_volsw(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
int reg;
int l;
int r;
l = ucontrol->value.integer.value[0];
r = ucontrol->value.integer.value[1];
/* make sure userspace volume fall in (0, 0xfc-0x3c) */
l = clamp(l, 0, 0xfc - 0x3c);
r = clamp(r, 0, 0xfc - 0x3c);
/* invert it, get the value can be set to register */
l = 0xfc - l;
r = 0xfc - r;
/* shift to get the register value */
reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT |
r << SGTL5000_DAC_VOL_RIGHT_SHIFT;
snd_soc_component_write(component, SGTL5000_CHIP_DAC_VOL, reg);
return 0;
}
/*
* custom function to get AVC threshold
*
* The threshold dB is calculated by rearranging the calculation from the
* avc_put_threshold function: register_value = 10^(dB/20) * 0.636 * 2^15 ==>
* dB = ( fls(register_value) - 14.347 ) * 6.02
*
* As this calculation is expensive and the threshold dB values may not exceed
* 0 to 96 we use pre-calculated values.
*/
static int avc_get_threshold(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
int db, i;
u16 reg = snd_soc_component_read(component, SGTL5000_DAP_AVC_THRESHOLD);
/* register value 0 => -96dB */
if (!reg) {
ucontrol->value.integer.value[0] = 96;
ucontrol->value.integer.value[1] = 96;
return 0;
}
/* get dB from register value (rounded down) */
for (i = 0; avc_thr_db2reg[i] > reg; i++)
;
db = i;
ucontrol->value.integer.value[0] = db;
ucontrol->value.integer.value[1] = db;
return 0;
}
/*
* custom function to put AVC threshold
*
* The register value is calculated by following formula:
* register_value = 10^(dB/20) * 0.636 * 2^15
* As this calculation is expensive and the threshold dB values may not exceed
* 0 to 96 we use pre-calculated values.
*/
static int avc_put_threshold(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
int db;
u16 reg;
db = (int)ucontrol->value.integer.value[0];
if (db < 0 || db > 96)
return -EINVAL;
reg = avc_thr_db2reg[db];
snd_soc_component_write(component, SGTL5000_DAP_AVC_THRESHOLD, reg);
return 0;
}
static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0);
/* tlv for mic gain, 0db 20db 30db 40db */
static const DECLARE_TLV_DB_RANGE(mic_gain_tlv,
0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0)
);
/* tlv for DAP channels, 0% - 100% - 200% */
static const DECLARE_TLV_DB_SCALE(dap_volume, 0, 1, 0);
/* tlv for bass bands, -11.75db to 12.0db, step .25db */
static const DECLARE_TLV_DB_SCALE(bass_band, -1175, 25, 0);
/* tlv for hp volume, -51.5db to 12.0db, step .5db */
static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0);
/* tlv for lineout volume, 31 steps of .5db each */
static const DECLARE_TLV_DB_SCALE(lineout_volume, -1550, 50, 0);
/* tlv for dap avc max gain, 0db, 6db, 12db */
static const DECLARE_TLV_DB_SCALE(avc_max_gain, 0, 600, 0);
/* tlv for dap avc threshold, */
static const DECLARE_TLV_DB_MINMAX(avc_threshold, 0, 9600);
static const struct snd_kcontrol_new sgtl5000_snd_controls[] = {
/* SOC_DOUBLE_S8_TLV with invert */
{
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
.name = "PCM Playback Volume",
.access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |
SNDRV_CTL_ELEM_ACCESS_READWRITE,
.info = dac_info_volsw,
.get = dac_get_volsw,
.put = dac_put_volsw,
},
SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0),
SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)",
SGTL5000_CHIP_ANA_ADC_CTRL,
8, 1, 0, capture_6db_attenuate),
SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0),
SOC_SINGLE("Capture Switch", SGTL5000_CHIP_ANA_CTRL, 0, 1, 1),
SOC_DOUBLE_TLV("Headphone Playback Volume",
SGTL5000_CHIP_ANA_HP_CTRL,
0, 8,
0x7f, 1,
headphone_volume),
SOC_SINGLE("Headphone Playback Switch", SGTL5000_CHIP_ANA_CTRL,
4, 1, 1),
SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL,
5, 1, 0),
SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL,
0, 3, 0, mic_gain_tlv),
SOC_DOUBLE_TLV("Lineout Playback Volume",
SGTL5000_CHIP_LINE_OUT_VOL,
SGTL5000_LINE_OUT_VOL_LEFT_SHIFT,
SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT,
0x1f, 1,
lineout_volume),
SOC_SINGLE("Lineout Playback Switch", SGTL5000_CHIP_ANA_CTRL, 8, 1, 1),
SOC_SINGLE_TLV("DAP Main channel", SGTL5000_DAP_MAIN_CHAN,
0, 0xffff, 0, dap_volume),
SOC_SINGLE_TLV("DAP Mix channel", SGTL5000_DAP_MIX_CHAN,
0, 0xffff, 0, dap_volume),
/* Automatic Volume Control (DAP AVC) */
SOC_SINGLE("AVC Switch", SGTL5000_DAP_AVC_CTRL, 0, 1, 0),
SOC_SINGLE("AVC Hard Limiter Switch", SGTL5000_DAP_AVC_CTRL, 5, 1, 0),
SOC_SINGLE_TLV("AVC Max Gain Volume", SGTL5000_DAP_AVC_CTRL, 12, 2, 0,
avc_max_gain),
SOC_SINGLE("AVC Integrator Response", SGTL5000_DAP_AVC_CTRL, 8, 3, 0),
SOC_SINGLE_EXT_TLV("AVC Threshold Volume", SGTL5000_DAP_AVC_THRESHOLD,
0, 96, 0, avc_get_threshold, avc_put_threshold,
avc_threshold),
SOC_SINGLE_TLV("BASS 0", SGTL5000_DAP_EQ_BASS_BAND0,
0, 0x5F, 0, bass_band),
SOC_SINGLE_TLV("BASS 1", SGTL5000_DAP_EQ_BASS_BAND1,
0, 0x5F, 0, bass_band),
SOC_SINGLE_TLV("BASS 2", SGTL5000_DAP_EQ_BASS_BAND2,
0, 0x5F, 0, bass_band),
SOC_SINGLE_TLV("BASS 3", SGTL5000_DAP_EQ_BASS_BAND3,
0, 0x5F, 0, bass_band),
SOC_SINGLE_TLV("BASS 4", SGTL5000_DAP_EQ_BASS_BAND4,
0, 0x5F, 0, bass_band),
};
/* mute the codec used by alsa core */
static int sgtl5000_mute_stream(struct snd_soc_dai *codec_dai, int mute, int direction)
{
struct snd_soc_component *component = codec_dai->component;
u16 i2s_pwr = SGTL5000_I2S_IN_POWERUP;
/*
* During 'digital mute' do not mute DAC
* because LINE_IN would be muted aswell. We want to mute
* only I2S block - this can be done by powering it off
*/
snd_soc_component_update_bits(component, SGTL5000_CHIP_DIG_POWER,
i2s_pwr, mute ? 0 : i2s_pwr);
return 0;
}
/* set codec format */
static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component);
u16 i2sctl = 0;
sgtl5000->master = 0;
/*
* i2s clock and frame master setting.
* ONLY support:
* - clock and frame slave,
* - clock and frame master
*/
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFS:
break;
case SND_SOC_DAIFMT_CBM_CFM:
i2sctl |= SGTL5000_I2S_MASTER;
sgtl5000->master = 1;
break;
default:
return -EINVAL;
}
/* setting i2s data format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT;
break;
case SND_SOC_DAIFMT_DSP_B:
i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT;
i2sctl |= SGTL5000_I2S_LRALIGN;
break;
case SND_SOC_DAIFMT_I2S:
i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT;
break;
case SND_SOC_DAIFMT_RIGHT_J:
i2sctl |= SGTL5000_I2S_MODE_RJ << SGTL5000_I2S_MODE_SHIFT;
i2sctl |= SGTL5000_I2S_LRPOL;
break;
case SND_SOC_DAIFMT_LEFT_J:
i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT;
i2sctl |= SGTL5000_I2S_LRALIGN;
break;
default:
return -EINVAL;
}
sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
/* Clock inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
i2sctl |= SGTL5000_I2S_SCLK_INV;
break;
default:
return -EINVAL;
}
snd_soc_component_write(component, SGTL5000_CHIP_I2S_CTRL, i2sctl);
return 0;
}
/* set codec sysclk */
static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component);
switch (clk_id) {
case SGTL5000_SYSCLK:
sgtl5000->sysclk = freq;
break;
default:
return -EINVAL;
}
return 0;
}
/*
* set clock according to i2s frame clock,
* sgtl5000 provides 2 clock sources:
* 1. sys_mclk: sample freq can only be configured to
* 1/256, 1/384, 1/512 of sys_mclk.
* 2. pll: can derive any audio clocks.
*
* clock setting rules:
* 1. in slave mode, only sys_mclk can be used
* 2. as constraint by sys_mclk, sample freq should be set to 32 kHz, 44.1 kHz
* and above.
* 3. usage of sys_mclk is preferred over pll to save power.
*/
static int sgtl5000_set_clock(struct snd_soc_component *component, int frame_rate)
{
struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component);
int clk_ctl = 0;
int sys_fs; /* sample freq */
/*
* sample freq should be divided by frame clock,
* if frame clock is lower than 44.1 kHz, sample freq should be set to
* 32 kHz or 44.1 kHz.
*/
switch (frame_rate) {
case 8000:
case 16000:
sys_fs = 32000;
break;
case 11025:
case 22050:
sys_fs = 44100;
break;
default:
sys_fs = frame_rate;
break;
}
/* set divided factor of frame clock */
switch (sys_fs / frame_rate) {
case 4:
clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT;
break;
case 2:
clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT;
break;
case 1:
clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT;
break;
default:
return -EINVAL;
}
/* set the sys_fs according to frame rate */
switch (sys_fs) {
case 32000:
clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT;
break;
case 44100:
clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT;
break;
case 48000:
clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT;
break;
case 96000:
clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT;
break;
default:
dev_err(component->dev, "frame rate %d not supported\n",
frame_rate);
return -EINVAL;
}
/*
* calculate the divider of mclk/sample_freq,
* factor of freq = 96 kHz can only be 256, since mclk is in the range
* of 8 MHz - 27 MHz
*/
switch (sgtl5000->sysclk / frame_rate) {
case 256:
clk_ctl |= SGTL5000_MCLK_FREQ_256FS <<
SGTL5000_MCLK_FREQ_SHIFT;
break;
case 384:
clk_ctl |= SGTL5000_MCLK_FREQ_384FS <<
SGTL5000_MCLK_FREQ_SHIFT;
break;
case 512:
clk_ctl |= SGTL5000_MCLK_FREQ_512FS <<
SGTL5000_MCLK_FREQ_SHIFT;
break;
default:
/* if mclk does not satisfy the divider, use pll */
if (sgtl5000->master) {
clk_ctl |= SGTL5000_MCLK_FREQ_PLL <<
SGTL5000_MCLK_FREQ_SHIFT;
} else {
dev_err(component->dev,
"PLL not supported in slave mode\n");
dev_err(component->dev, "%d ratio is not supported. "
"SYS_MCLK needs to be 256, 384 or 512 * fs\n",
sgtl5000->sysclk / frame_rate);
return -EINVAL;
}
}
/* if using pll, please check manual 6.4.2 for detail */
if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) {
u64 out, t;
int div2;
int pll_ctl;
unsigned int in, int_div, frac_div;
if (sgtl5000->sysclk > 17000000) {
div2 = 1;
in = sgtl5000->sysclk / 2;
} else {
div2 = 0;
in = sgtl5000->sysclk;
}
if (sys_fs == 44100)
out = 180633600;
else
out = 196608000;
t = do_div(out, in);
int_div = out;
t *= 2048;
do_div(t, in);
frac_div = t;
pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT |
frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT;
snd_soc_component_write(component, SGTL5000_CHIP_PLL_CTRL, pll_ctl);
if (div2)
snd_soc_component_update_bits(component,
SGTL5000_CHIP_CLK_TOP_CTRL,
SGTL5000_INPUT_FREQ_DIV2,
SGTL5000_INPUT_FREQ_DIV2);
else
snd_soc_component_update_bits(component,
SGTL5000_CHIP_CLK_TOP_CTRL,
SGTL5000_INPUT_FREQ_DIV2,
0);
/* power up pll */
snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,
SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP);
/* if using pll, clk_ctrl must be set after pll power up */
snd_soc_component_write(component, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
} else {
/* otherwise, clk_ctrl must be set before pll power down */
snd_soc_component_write(component, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
/* power down pll */
snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,
SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
0);
}
return 0;
}
/*
* Set PCM DAI bit size and sample rate.
* input: params_rate, params_fmt
*/
static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component);
int channels = params_channels(params);
int i2s_ctl = 0;
int stereo;
int ret;
/* sysclk should already set */
if (!sgtl5000->sysclk) {
dev_err(component->dev, "%s: set sysclk first!\n", __func__);
return -EFAULT;
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
stereo = SGTL5000_DAC_STEREO;
else
stereo = SGTL5000_ADC_STEREO;
/* set mono to save power */
snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER, stereo,
channels == 1 ? 0 : stereo);
/* set codec clock base on lrclk */
ret = sgtl5000_set_clock(component, params_rate(params));
if (ret)
return ret;
/* set i2s data format */
switch (params_width(params)) {
case 16:
if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
return -EINVAL;
i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT;
i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS <<
SGTL5000_I2S_SCLKFREQ_SHIFT;
break;
case 20:
i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT;
i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
SGTL5000_I2S_SCLKFREQ_SHIFT;
break;
case 24:
i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT;
i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
SGTL5000_I2S_SCLKFREQ_SHIFT;
break;
case 32:
if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
return -EINVAL;
i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT;
i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
SGTL5000_I2S_SCLKFREQ_SHIFT;
break;
default:
return -EINVAL;
}
snd_soc_component_update_bits(component, SGTL5000_CHIP_I2S_CTRL,
SGTL5000_I2S_DLEN_MASK | SGTL5000_I2S_SCLKFREQ_MASK,
i2s_ctl);
return 0;
}
/*
* set dac bias
* common state changes:
* startup:
* off --> standby --> prepare --> on
* standby --> prepare --> on
*
* stop:
* on --> prepare --> standby
*/
static int sgtl5000_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct sgtl5000_priv *sgtl = snd_soc_component_get_drvdata(component);
int ret;
switch (level) {
case SND_SOC_BIAS_ON:
case SND_SOC_BIAS_PREPARE:
case SND_SOC_BIAS_STANDBY:
regcache_cache_only(sgtl->regmap, false);
ret = regcache_sync(sgtl->regmap);
if (ret) {
regcache_cache_only(sgtl->regmap, true);
return ret;
}
snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,
SGTL5000_REFTOP_POWERUP,
SGTL5000_REFTOP_POWERUP);
break;
case SND_SOC_BIAS_OFF:
regcache_cache_only(sgtl->regmap, true);
snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,
SGTL5000_REFTOP_POWERUP, 0);
break;
}
return 0;
}
#define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S20_3LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops sgtl5000_ops = {
.hw_params = sgtl5000_pcm_hw_params,
.mute_stream = sgtl5000_mute_stream,
.set_fmt = sgtl5000_set_dai_fmt,
.set_sysclk = sgtl5000_set_dai_sysclk,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver sgtl5000_dai = {
.name = "sgtl5000",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
/*
* only support 8~48K + 96K,
* TODO modify hw_param to support more
*/
.rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
.formats = SGTL5000_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
.formats = SGTL5000_FORMATS,
},
.ops = &sgtl5000_ops,
.symmetric_rate = 1,
};
static bool sgtl5000_volatile(struct device *dev, unsigned int reg)
{
switch (reg) {
case SGTL5000_CHIP_ID:
case SGTL5000_CHIP_ADCDAC_CTRL:
case SGTL5000_CHIP_ANA_STATUS:
return true;
}
return false;
}
static bool sgtl5000_readable(struct device *dev, unsigned int reg)
{
switch (reg) {
case SGTL5000_CHIP_ID:
case SGTL5000_CHIP_DIG_POWER:
case SGTL5000_CHIP_CLK_CTRL:
case SGTL5000_CHIP_I2S_CTRL:
case SGTL5000_CHIP_SSS_CTRL:
case SGTL5000_CHIP_ADCDAC_CTRL:
case SGTL5000_CHIP_DAC_VOL:
case SGTL5000_CHIP_PAD_STRENGTH:
case SGTL5000_CHIP_ANA_ADC_CTRL:
case SGTL5000_CHIP_ANA_HP_CTRL:
case SGTL5000_CHIP_ANA_CTRL:
case SGTL5000_CHIP_LINREG_CTRL:
case SGTL5000_CHIP_REF_CTRL:
case SGTL5000_CHIP_MIC_CTRL:
case SGTL5000_CHIP_LINE_OUT_CTRL:
case SGTL5000_CHIP_LINE_OUT_VOL:
case SGTL5000_CHIP_ANA_POWER:
case SGTL5000_CHIP_PLL_CTRL:
case SGTL5000_CHIP_CLK_TOP_CTRL:
case SGTL5000_CHIP_ANA_STATUS:
case SGTL5000_CHIP_SHORT_CTRL:
case SGTL5000_CHIP_ANA_TEST2:
case SGTL5000_DAP_CTRL:
case SGTL5000_DAP_PEQ:
case SGTL5000_DAP_BASS_ENHANCE:
case SGTL5000_DAP_BASS_ENHANCE_CTRL:
case SGTL5000_DAP_AUDIO_EQ:
case SGTL5000_DAP_SURROUND:
case SGTL5000_DAP_FLT_COEF_ACCESS:
case SGTL5000_DAP_COEF_WR_B0_MSB:
case SGTL5000_DAP_COEF_WR_B0_LSB:
case SGTL5000_DAP_EQ_BASS_BAND0:
case SGTL5000_DAP_EQ_BASS_BAND1:
case SGTL5000_DAP_EQ_BASS_BAND2:
case SGTL5000_DAP_EQ_BASS_BAND3:
case SGTL5000_DAP_EQ_BASS_BAND4:
case SGTL5000_DAP_MAIN_CHAN:
case SGTL5000_DAP_MIX_CHAN:
case SGTL5000_DAP_AVC_CTRL:
case SGTL5000_DAP_AVC_THRESHOLD:
case SGTL5000_DAP_AVC_ATTACK:
case SGTL5000_DAP_AVC_DECAY:
case SGTL5000_DAP_COEF_WR_B1_MSB:
case SGTL5000_DAP_COEF_WR_B1_LSB:
case SGTL5000_DAP_COEF_WR_B2_MSB:
case SGTL5000_DAP_COEF_WR_B2_LSB:
case SGTL5000_DAP_COEF_WR_A1_MSB:
case SGTL5000_DAP_COEF_WR_A1_LSB:
case SGTL5000_DAP_COEF_WR_A2_MSB:
case SGTL5000_DAP_COEF_WR_A2_LSB:
return true;
default:
return false;
}
}
/*
* This precalculated table contains all (vag_val * 100 / lo_calcntrl) results
* to select an appropriate lo_vol_* in SGTL5000_CHIP_LINE_OUT_VOL
* The calculatation was done for all possible register values which
* is the array index and the following formula: 10^((idx−15)/40) * 100
*/
static const u8 vol_quot_table[] = {
42, 45, 47, 50, 53, 56, 60, 63,
67, 71, 75, 79, 84, 89, 94, 100,
106, 112, 119, 126, 133, 141, 150, 158,
168, 178, 188, 200, 211, 224, 237, 251
};
/*
* sgtl5000 has 3 internal power supplies:
* 1. VAG, normally set to vdda/2
* 2. charge pump, set to different value
* according to voltage of vdda and vddio
* 3. line out VAG, normally set to vddio/2
*
* and should be set according to:
* 1. vddd provided by external or not
* 2. vdda and vddio voltage value. > 3.1v or not
*/
static int sgtl5000_set_power_regs(struct snd_soc_component *component)
{
int vddd;
int vdda;
int vddio;
u16 ana_pwr;
u16 lreg_ctrl;
int vag;
int lo_vag;
int vol_quot;
int lo_vol;
size_t i;
struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component);
vdda = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer);
vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer);
vddd = (sgtl5000->num_supplies > VDDD)
? regulator_get_voltage(sgtl5000->supplies[VDDD].consumer)
: LDO_VOLTAGE;
vdda = vdda / 1000;
vddio = vddio / 1000;
vddd = vddd / 1000;
if (vdda <= 0 || vddio <= 0 || vddd < 0) {
dev_err(component->dev, "regulator voltage not set correctly\n");
return -EINVAL;
}
/* according to datasheet, maximum voltage of supplies */
if (vdda > 3600 || vddio > 3600 || vddd > 1980) {
dev_err(component->dev,
"exceed max voltage vdda %dmV vddio %dmV vddd %dmV\n",
vdda, vddio, vddd);
return -EINVAL;
}
/* reset value */
ana_pwr = snd_soc_component_read(component, SGTL5000_CHIP_ANA_POWER);
ana_pwr |= SGTL5000_DAC_STEREO |
SGTL5000_ADC_STEREO |
SGTL5000_REFTOP_POWERUP;
lreg_ctrl = snd_soc_component_read(component, SGTL5000_CHIP_LINREG_CTRL);
if (vddio < 3100 && vdda < 3100) {
/* enable internal oscillator used for charge pump */
snd_soc_component_update_bits(component, SGTL5000_CHIP_CLK_TOP_CTRL,
SGTL5000_INT_OSC_EN,
SGTL5000_INT_OSC_EN);
/* Enable VDDC charge pump */
ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP;
} else {
ana_pwr &= ~SGTL5000_VDDC_CHRGPMP_POWERUP;
/*
* if vddio == vdda the source of charge pump should be
* assigned manually to VDDIO
*/
if (regulator_is_equal(sgtl5000->supplies[VDDA].consumer,
sgtl5000->supplies[VDDIO].consumer)) {
lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD;
lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO <<
SGTL5000_VDDC_MAN_ASSN_SHIFT;
}
}
snd_soc_component_write(component, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl);
snd_soc_component_write(component, SGTL5000_CHIP_ANA_POWER, ana_pwr);
/*
* set ADC/DAC VAG to vdda / 2,
* should stay in range (0.8v, 1.575v)
*/
vag = vdda / 2;
if (vag <= SGTL5000_ANA_GND_BASE)
vag = 0;
else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP *
(SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT))
vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT;
else
vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP;
snd_soc_component_update_bits(component, SGTL5000_CHIP_REF_CTRL,
SGTL5000_ANA_GND_MASK, vag << SGTL5000_ANA_GND_SHIFT);
/* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */
lo_vag = vddio / 2;
if (lo_vag <= SGTL5000_LINE_OUT_GND_BASE)
lo_vag = 0;
else if (lo_vag >= SGTL5000_LINE_OUT_GND_BASE +
SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX)
lo_vag = SGTL5000_LINE_OUT_GND_MAX;
else
lo_vag = (lo_vag - SGTL5000_LINE_OUT_GND_BASE) /
SGTL5000_LINE_OUT_GND_STP;
snd_soc_component_update_bits(component, SGTL5000_CHIP_LINE_OUT_CTRL,
SGTL5000_LINE_OUT_CURRENT_MASK |
SGTL5000_LINE_OUT_GND_MASK,
lo_vag << SGTL5000_LINE_OUT_GND_SHIFT |
SGTL5000_LINE_OUT_CURRENT_360u <<
SGTL5000_LINE_OUT_CURRENT_SHIFT);
/*
* Set lineout output level in range (0..31)
* the same value is used for right and left channel
*
* Searching for a suitable index solving this formula:
* idx = 40 * log10(vag_val / lo_cagcntrl) + 15
*/
vol_quot = lo_vag ? (vag * 100) / lo_vag : 0;
lo_vol = 0;
for (i = 0; i < ARRAY_SIZE(vol_quot_table); i++) {
if (vol_quot >= vol_quot_table[i])
lo_vol = i;
else
break;
}
snd_soc_component_update_bits(component, SGTL5000_CHIP_LINE_OUT_VOL,
SGTL5000_LINE_OUT_VOL_RIGHT_MASK |
SGTL5000_LINE_OUT_VOL_LEFT_MASK,
lo_vol << SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT |
lo_vol << SGTL5000_LINE_OUT_VOL_LEFT_SHIFT);
return 0;
}
static int sgtl5000_enable_regulators(struct i2c_client *client)
{
int ret;
int i;
int external_vddd = 0;
struct regulator *vddd;
struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++)
sgtl5000->supplies[i].supply = supply_names[i];
vddd = regulator_get_optional(&client->dev, "VDDD");
if (IS_ERR(vddd)) {
/* See if it's just not registered yet */
if (PTR_ERR(vddd) == -EPROBE_DEFER)
return -EPROBE_DEFER;
} else {
external_vddd = 1;
regulator_put(vddd);
}
sgtl5000->num_supplies = ARRAY_SIZE(sgtl5000->supplies)
- 1 + external_vddd;
ret = regulator_bulk_get(&client->dev, sgtl5000->num_supplies,
sgtl5000->supplies);
if (ret)
return ret;
ret = regulator_bulk_enable(sgtl5000->num_supplies,
sgtl5000->supplies);
if (!ret)
usleep_range(10, 20);
else
regulator_bulk_free(sgtl5000->num_supplies,
sgtl5000->supplies);
return ret;
}
static int sgtl5000_probe(struct snd_soc_component *component)
{
int ret;
u16 reg;
struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component);
unsigned int zcd_mask = SGTL5000_HP_ZCD_EN | SGTL5000_ADC_ZCD_EN;
/* power up sgtl5000 */
ret = sgtl5000_set_power_regs(component);
if (ret)
goto err;
/* enable small pop, introduce 400ms delay in turning off */
snd_soc_component_update_bits(component, SGTL5000_CHIP_REF_CTRL,
SGTL5000_SMALL_POP, SGTL5000_SMALL_POP);
/* disable short cut detector */
snd_soc_component_write(component, SGTL5000_CHIP_SHORT_CTRL, 0);
snd_soc_component_write(component, SGTL5000_CHIP_DIG_POWER,
SGTL5000_ADC_EN | SGTL5000_DAC_EN);
/* enable dac volume ramp by default */
snd_soc_component_write(component, SGTL5000_CHIP_ADCDAC_CTRL,
SGTL5000_DAC_VOL_RAMP_EN |
SGTL5000_DAC_MUTE_RIGHT |
SGTL5000_DAC_MUTE_LEFT);
reg = ((sgtl5000->lrclk_strength) << SGTL5000_PAD_I2S_LRCLK_SHIFT |
(sgtl5000->sclk_strength) << SGTL5000_PAD_I2S_SCLK_SHIFT |
0x1f);
snd_soc_component_write(component, SGTL5000_CHIP_PAD_STRENGTH, reg);
snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_CTRL,
zcd_mask, zcd_mask);
snd_soc_component_update_bits(component, SGTL5000_CHIP_MIC_CTRL,
SGTL5000_BIAS_R_MASK,
sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT);
snd_soc_component_update_bits(component, SGTL5000_CHIP_MIC_CTRL,
SGTL5000_BIAS_VOLT_MASK,
sgtl5000->micbias_voltage << SGTL5000_BIAS_VOLT_SHIFT);
/*
* enable DAP Graphic EQ
* TODO:
* Add control for changing between PEQ/Tone Control/GEQ
*/
snd_soc_component_write(component, SGTL5000_DAP_AUDIO_EQ, SGTL5000_DAP_SEL_GEQ);
/* Unmute DAC after start */
snd_soc_component_update_bits(component, SGTL5000_CHIP_ADCDAC_CTRL,
SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT, 0);
return 0;
err:
return ret;
}
static int sgtl5000_of_xlate_dai_id(struct snd_soc_component *component,
struct device_node *endpoint)
{
/* return dai id 0, whatever the endpoint index */
return 0;
}
static const struct snd_soc_component_driver sgtl5000_driver = {
.probe = sgtl5000_probe,
.set_bias_level = sgtl5000_set_bias_level,
.controls = sgtl5000_snd_controls,
.num_controls = ARRAY_SIZE(sgtl5000_snd_controls),
.dapm_widgets = sgtl5000_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(sgtl5000_dapm_widgets),
.dapm_routes = sgtl5000_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(sgtl5000_dapm_routes),
.of_xlate_dai_id = sgtl5000_of_xlate_dai_id,
.suspend_bias_off = 1,
.idle_bias_on = 1,
.use_pmdown_time = 1,
.endianness = 1,
};
static const struct regmap_config sgtl5000_regmap = {
.reg_bits = 16,
.val_bits = 16,
.reg_stride = 2,
.max_register = SGTL5000_MAX_REG_OFFSET,
.volatile_reg = sgtl5000_volatile,
.readable_reg = sgtl5000_readable,
.cache_type = REGCACHE_RBTREE,
.reg_defaults = sgtl5000_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(sgtl5000_reg_defaults),
};
/*
* Write all the default values from sgtl5000_reg_defaults[] array into the
* sgtl5000 registers, to make sure we always start with the sane registers
* values as stated in the datasheet.
*
* Since sgtl5000 does not have a reset line, nor a reset command in software,
* we follow this approach to guarantee we always start from the default values
* and avoid problems like, not being able to probe after an audio playback
* followed by a system reset or a 'reboot' command in Linux
*/
static void sgtl5000_fill_defaults(struct i2c_client *client)
{
struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
int i, ret, val, index;
for (i = 0; i < ARRAY_SIZE(sgtl5000_reg_defaults); i++) {
val = sgtl5000_reg_defaults[i].def;
index = sgtl5000_reg_defaults[i].reg;
ret = regmap_write(sgtl5000->regmap, index, val);
if (ret)
dev_err(&client->dev,
"%s: error %d setting reg 0x%02x to 0x%04x\n",
__func__, ret, index, val);
}
}
static int sgtl5000_i2c_probe(struct i2c_client *client)
{
struct sgtl5000_priv *sgtl5000;
int ret, reg, rev;
struct device_node *np = client->dev.of_node;
u32 value;
u16 ana_pwr;
sgtl5000 = devm_kzalloc(&client->dev, sizeof(*sgtl5000), GFP_KERNEL);
if (!sgtl5000)
return -ENOMEM;
i2c_set_clientdata(client, sgtl5000);
ret = sgtl5000_enable_regulators(client);
if (ret)
return ret;
sgtl5000->regmap = devm_regmap_init_i2c(client, &sgtl5000_regmap);
if (IS_ERR(sgtl5000->regmap)) {
ret = PTR_ERR(sgtl5000->regmap);
dev_err(&client->dev, "Failed to allocate regmap: %d\n", ret);
goto disable_regs;
}
sgtl5000->mclk = devm_clk_get(&client->dev, NULL);
if (IS_ERR(sgtl5000->mclk)) {
ret = PTR_ERR(sgtl5000->mclk);
/* Defer the probe to see if the clk will be provided later */
if (ret == -ENOENT)
ret = -EPROBE_DEFER;
dev_err_probe(&client->dev, ret, "Failed to get mclock\n");
goto disable_regs;
}
ret = clk_prepare_enable(sgtl5000->mclk);
if (ret) {
dev_err(&client->dev, "Error enabling clock %d\n", ret);
goto disable_regs;
}
/* Need 8 clocks before I2C accesses */
udelay(1);
/* read chip information */
ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, ®);
if (ret) {
dev_err(&client->dev, "Error reading chip id %d\n", ret);
goto disable_clk;
}
if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) !=
SGTL5000_PARTID_PART_ID) {
dev_err(&client->dev,
"Device with ID register %x is not a sgtl5000\n", reg);
ret = -ENODEV;
goto disable_clk;
}
rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT;
dev_info(&client->dev, "sgtl5000 revision 0x%x\n", rev);
sgtl5000->revision = rev;
/* reconfigure the clocks in case we're using the PLL */
ret = regmap_write(sgtl5000->regmap,
SGTL5000_CHIP_CLK_CTRL,
SGTL5000_CHIP_CLK_CTRL_DEFAULT);
if (ret)
dev_err(&client->dev,
"Error %d initializing CHIP_CLK_CTRL\n", ret);
/* Mute everything to avoid pop from the following power-up */
ret = regmap_write(sgtl5000->regmap, SGTL5000_CHIP_ANA_CTRL,
SGTL5000_CHIP_ANA_CTRL_DEFAULT);
if (ret) {
dev_err(&client->dev,
"Error %d muting outputs via CHIP_ANA_CTRL\n", ret);
goto disable_clk;
}
/*
* If VAG is powered-on (e.g. from previous boot), it would be disabled
* by the write to ANA_POWER in later steps of the probe code. This
* may create a loud pop even with all outputs muted. The proper way
* to circumvent this is disabling the bit first and waiting the proper
* cool-down time.
*/
ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ANA_POWER, &value);
if (ret) {
dev_err(&client->dev, "Failed to read ANA_POWER: %d\n", ret);
goto disable_clk;
}
if (value & SGTL5000_VAG_POWERUP) {
ret = regmap_update_bits(sgtl5000->regmap,
SGTL5000_CHIP_ANA_POWER,
SGTL5000_VAG_POWERUP,
0);
if (ret) {
dev_err(&client->dev, "Error %d disabling VAG\n", ret);
goto disable_clk;
}
msleep(SGTL5000_VAG_POWERDOWN_DELAY);
}
/* Follow section 2.2.1.1 of AN3663 */
ana_pwr = SGTL5000_ANA_POWER_DEFAULT;
if (sgtl5000->num_supplies <= VDDD) {
/* internal VDDD at 1.2V */
ret = regmap_update_bits(sgtl5000->regmap,
SGTL5000_CHIP_LINREG_CTRL,
SGTL5000_LINREG_VDDD_MASK,
LINREG_VDDD);
if (ret)
dev_err(&client->dev,
"Error %d setting LINREG_VDDD\n", ret);
ana_pwr |= SGTL5000_LINEREG_D_POWERUP;
dev_info(&client->dev,
"Using internal LDO instead of VDDD: check ER1 erratum\n");
} else {
/* using external LDO for VDDD
* Clear startup powerup and simple powerup
* bits to save power
*/
ana_pwr &= ~(SGTL5000_STARTUP_POWERUP
| SGTL5000_LINREG_SIMPLE_POWERUP);
dev_dbg(&client->dev, "Using external VDDD\n");
}
ret = regmap_write(sgtl5000->regmap, SGTL5000_CHIP_ANA_POWER, ana_pwr);
if (ret)
dev_err(&client->dev,
"Error %d setting CHIP_ANA_POWER to %04x\n",
ret, ana_pwr);
if (np) {
if (!of_property_read_u32(np,
"micbias-resistor-k-ohms", &value)) {
switch (value) {
case SGTL5000_MICBIAS_OFF:
sgtl5000->micbias_resistor = 0;
break;
case SGTL5000_MICBIAS_2K:
sgtl5000->micbias_resistor = 1;
break;
case SGTL5000_MICBIAS_4K:
sgtl5000->micbias_resistor = 2;
break;
case SGTL5000_MICBIAS_8K:
sgtl5000->micbias_resistor = 3;
break;
default:
sgtl5000->micbias_resistor = 2;
dev_err(&client->dev,
"Unsuitable MicBias resistor\n");
}
} else {
/* default is 4Kohms */
sgtl5000->micbias_resistor = 2;
}
if (!of_property_read_u32(np,
"micbias-voltage-m-volts", &value)) {
/* 1250mV => 0 */
/* steps of 250mV */
if ((value >= 1250) && (value <= 3000))
sgtl5000->micbias_voltage = (value / 250) - 5;
else {
sgtl5000->micbias_voltage = 0;
dev_err(&client->dev,
"Unsuitable MicBias voltage\n");
}
} else {
sgtl5000->micbias_voltage = 0;
}
}
sgtl5000->lrclk_strength = I2S_LRCLK_STRENGTH_LOW;
if (!of_property_read_u32(np, "lrclk-strength", &value)) {
if (value > I2S_LRCLK_STRENGTH_HIGH)
value = I2S_LRCLK_STRENGTH_LOW;
sgtl5000->lrclk_strength = value;
}
sgtl5000->sclk_strength = I2S_SCLK_STRENGTH_LOW;
if (!of_property_read_u32(np, "sclk-strength", &value)) {
if (value > I2S_SCLK_STRENGTH_HIGH)
value = I2S_SCLK_STRENGTH_LOW;
sgtl5000->sclk_strength = value;
}
/* Ensure sgtl5000 will start with sane register values */
sgtl5000_fill_defaults(client);
ret = devm_snd_soc_register_component(&client->dev,
&sgtl5000_driver, &sgtl5000_dai, 1);
if (ret)
goto disable_clk;
return 0;
disable_clk:
clk_disable_unprepare(sgtl5000->mclk);
disable_regs:
regulator_bulk_disable(sgtl5000->num_supplies, sgtl5000->supplies);
regulator_bulk_free(sgtl5000->num_supplies, sgtl5000->supplies);
return ret;
}
static void sgtl5000_i2c_remove(struct i2c_client *client)
{
struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
regmap_write(sgtl5000->regmap, SGTL5000_CHIP_CLK_CTRL, SGTL5000_CHIP_CLK_CTRL_DEFAULT);
regmap_write(sgtl5000->regmap, SGTL5000_CHIP_DIG_POWER, SGTL5000_DIG_POWER_DEFAULT);
regmap_write(sgtl5000->regmap, SGTL5000_CHIP_ANA_POWER, SGTL5000_ANA_POWER_DEFAULT);
clk_disable_unprepare(sgtl5000->mclk);
regulator_bulk_disable(sgtl5000->num_supplies, sgtl5000->supplies);
regulator_bulk_free(sgtl5000->num_supplies, sgtl5000->supplies);
}
static void sgtl5000_i2c_shutdown(struct i2c_client *client)
{
sgtl5000_i2c_remove(client);
}
static const struct i2c_device_id sgtl5000_id[] = {
{"sgtl5000", 0},
{},
};
MODULE_DEVICE_TABLE(i2c, sgtl5000_id);
static const struct of_device_id sgtl5000_dt_ids[] = {
{ .compatible = "fsl,sgtl5000", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, sgtl5000_dt_ids);
static struct i2c_driver sgtl5000_i2c_driver = {
.driver = {
.name = "sgtl5000",
.of_match_table = sgtl5000_dt_ids,
},
.probe = sgtl5000_i2c_probe,
.remove = sgtl5000_i2c_remove,
.shutdown = sgtl5000_i2c_shutdown,
.id_table = sgtl5000_id,
};
module_i2c_driver(sgtl5000_i2c_driver);
MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver");
MODULE_AUTHOR("Zeng Zhaoming <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/sgtl5000.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* ADAV803 audio driver
*
* Copyright 2014 Analog Devices Inc.
*/
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include "adav80x.h"
static const struct i2c_device_id adav803_id[] = {
{ "adav803", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, adav803_id);
static int adav803_probe(struct i2c_client *client)
{
return adav80x_bus_probe(&client->dev,
devm_regmap_init_i2c(client, &adav80x_regmap_config));
}
static struct i2c_driver adav803_driver = {
.driver = {
.name = "adav803",
},
.probe = adav803_probe,
.id_table = adav803_id,
};
module_i2c_driver(adav803_driver);
MODULE_DESCRIPTION("ASoC ADAV803 driver");
MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
MODULE_AUTHOR("Yi Li <[email protected]>>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/adav803.c |
// SPDX-License-Identifier: GPL-2.0
//
// TI SRC4xxx Audio Codec driver
//
// Copyright 2021-2022 Deqx Pty Ltd
// Author: Matt Flax <[email protected]>
#include <linux/module.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include "src4xxx.h"
struct src4xxx {
struct regmap *regmap;
bool master[2];
int mclk_hz;
struct device *dev;
};
enum {SRC4XXX_PORTA, SRC4XXX_PORTB};
/* SRC attenuation */
static const DECLARE_TLV_DB_SCALE(src_tlv, -12750, 50, 0);
static const struct snd_kcontrol_new src4xxx_controls[] = {
SOC_DOUBLE_R_TLV("SRC Volume",
SRC4XXX_SCR_CTL_30, SRC4XXX_SCR_CTL_31, 0, 255, 1, src_tlv),
};
/* I2S port control */
static const char * const port_out_src_text[] = {
"loopback", "other_port", "DIR", "SRC"
};
static SOC_ENUM_SINGLE_DECL(porta_out_src_enum, SRC4XXX_PORTA_CTL_03, 4,
port_out_src_text);
static SOC_ENUM_SINGLE_DECL(portb_out_src_enum, SRC4XXX_PORTB_CTL_05, 4,
port_out_src_text);
static const struct snd_kcontrol_new porta_out_control =
SOC_DAPM_ENUM("Port A source select", porta_out_src_enum);
static const struct snd_kcontrol_new portb_out_control =
SOC_DAPM_ENUM("Port B source select", portb_out_src_enum);
/* Digital audio transmitter control */
static const char * const dit_mux_text[] = {"Port A", "Port B", "DIR", "SRC"};
static SOC_ENUM_SINGLE_DECL(dit_mux_enum, SRC4XXX_TX_CTL_07, 3, dit_mux_text);
static const struct snd_kcontrol_new dit_mux_control =
SOC_DAPM_ENUM("DIT source", dit_mux_enum);
/* SRC control */
static const char * const src_in_text[] = {"Port A", "Port B", "DIR"};
static SOC_ENUM_SINGLE_DECL(src_in_enum, SRC4XXX_SCR_CTL_2D, 0, src_in_text);
static const struct snd_kcontrol_new src_in_control =
SOC_DAPM_ENUM("SRC source select", src_in_enum);
/* DIR control */
static const char * const dir_in_text[] = {"Ch 1", "Ch 2", "Ch 3", "Ch 4"};
static SOC_ENUM_SINGLE_DECL(dir_in_enum, SRC4XXX_RCV_CTL_0D, 0, dir_in_text);
static const struct snd_kcontrol_new dir_in_control =
SOC_DAPM_ENUM("Digital Input", dir_in_enum);
static const struct snd_soc_dapm_widget src4xxx_dapm_widgets[] = {
SND_SOC_DAPM_INPUT("loopback_A"),
SND_SOC_DAPM_INPUT("other_port_A"),
SND_SOC_DAPM_INPUT("DIR_A"),
SND_SOC_DAPM_INPUT("SRC_A"),
SND_SOC_DAPM_MUX("Port A source",
SND_SOC_NOPM, 0, 0, &porta_out_control),
SND_SOC_DAPM_INPUT("loopback_B"),
SND_SOC_DAPM_INPUT("other_port_B"),
SND_SOC_DAPM_INPUT("DIR_B"),
SND_SOC_DAPM_INPUT("SRC_B"),
SND_SOC_DAPM_MUX("Port B source",
SND_SOC_NOPM, 0, 0, &portb_out_control),
SND_SOC_DAPM_INPUT("Port_A"),
SND_SOC_DAPM_INPUT("Port_B"),
SND_SOC_DAPM_INPUT("DIR_"),
/* Digital audio receivers and transmitters */
SND_SOC_DAPM_OUTPUT("DIR_OUT"),
SND_SOC_DAPM_OUTPUT("SRC_OUT"),
SND_SOC_DAPM_MUX("DIT Out Src", SRC4XXX_PWR_RST_01,
SRC4XXX_ENABLE_DIT_SHIFT, 1, &dit_mux_control),
/* Audio Interface */
SND_SOC_DAPM_AIF_IN("AIF_A_RX", "Playback A", 0,
SRC4XXX_PWR_RST_01, SRC4XXX_ENABLE_PORT_A_SHIFT, 1),
SND_SOC_DAPM_AIF_OUT("AIF_A_TX", "Capture A", 0,
SRC4XXX_PWR_RST_01, SRC4XXX_ENABLE_PORT_A_SHIFT, 1),
SND_SOC_DAPM_AIF_IN("AIF_B_RX", "Playback B", 0,
SRC4XXX_PWR_RST_01, SRC4XXX_ENABLE_PORT_B_SHIFT, 1),
SND_SOC_DAPM_AIF_OUT("AIF_B_TX", "Capture B", 0,
SRC4XXX_PWR_RST_01, SRC4XXX_ENABLE_PORT_B_SHIFT, 1),
SND_SOC_DAPM_MUX("SRC source", SND_SOC_NOPM, 0, 0, &src_in_control),
SND_SOC_DAPM_INPUT("MCLK"),
SND_SOC_DAPM_INPUT("RXMCLKI"),
SND_SOC_DAPM_INPUT("RXMCLKO"),
SND_SOC_DAPM_INPUT("RX1"),
SND_SOC_DAPM_INPUT("RX2"),
SND_SOC_DAPM_INPUT("RX3"),
SND_SOC_DAPM_INPUT("RX4"),
SND_SOC_DAPM_MUX("Digital Input", SRC4XXX_PWR_RST_01,
SRC4XXX_ENABLE_DIR_SHIFT, 1, &dir_in_control),
};
static const struct snd_soc_dapm_route src4xxx_audio_routes[] = {
/* I2S Input to Output Routing */
{"Port A source", "loopback", "loopback_A"},
{"Port A source", "other_port", "other_port_A"},
{"Port A source", "DIR", "DIR_A"},
{"Port A source", "SRC", "SRC_A"},
{"Port B source", "loopback", "loopback_B"},
{"Port B source", "other_port", "other_port_B"},
{"Port B source", "DIR", "DIR_B"},
{"Port B source", "SRC", "SRC_B"},
/* DIT muxing */
{"DIT Out Src", "Port A", "Capture A"},
{"DIT Out Src", "Port B", "Capture B"},
{"DIT Out Src", "DIR", "DIR_OUT"},
{"DIT Out Src", "SRC", "SRC_OUT"},
/* SRC input selection */
{"SRC source", "Port A", "Port_A"},
{"SRC source", "Port B", "Port_B"},
{"SRC source", "DIR", "DIR_"},
/* SRC mclk selection */
{"SRC mclk source", "Master (MCLK)", "MCLK"},
{"SRC mclk source", "Master (RXCLKI)", "RXMCLKI"},
{"SRC mclk source", "Recovered receiver clk", "RXMCLKO"},
/* DIR input selection */
{"Digital Input", "Ch 1", "RX1"},
{"Digital Input", "Ch 2", "RX2"},
{"Digital Input", "Ch 3", "RX3"},
{"Digital Input", "Ch 4", "RX4"},
};
static const struct snd_soc_component_driver src4xxx_driver = {
.controls = src4xxx_controls,
.num_controls = ARRAY_SIZE(src4xxx_controls),
.dapm_widgets = src4xxx_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(src4xxx_dapm_widgets),
.dapm_routes = src4xxx_audio_routes,
.num_dapm_routes = ARRAY_SIZE(src4xxx_audio_routes),
};
static int src4xxx_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
struct src4xxx *src4xxx = snd_soc_component_get_drvdata(component);
unsigned int ctrl;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
ctrl = SRC4XXX_BUS_MASTER;
src4xxx->master[dai->id] = true;
break;
case SND_SOC_DAIFMT_CBS_CFS:
ctrl = 0;
src4xxx->master[dai->id] = false;
break;
default:
return -EINVAL;
break;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
ctrl |= SRC4XXX_BUS_I2S;
break;
case SND_SOC_DAIFMT_LEFT_J:
ctrl |= SRC4XXX_BUS_LEFT_J;
break;
case SND_SOC_DAIFMT_RIGHT_J:
ctrl |= SRC4XXX_BUS_RIGHT_J_24;
break;
default:
return -EINVAL;
break;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
default:
return -EINVAL;
break;
}
regmap_update_bits(src4xxx->regmap, SRC4XXX_BUS_FMT(dai->id),
SRC4XXX_BUS_FMT_MS_MASK, ctrl);
return 0;
}
static int src4xxx_set_mclk_hz(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = codec_dai->component;
struct src4xxx *src4xxx = snd_soc_component_get_drvdata(component);
dev_info(component->dev, "changing mclk rate from %d to %d Hz\n",
src4xxx->mclk_hz, freq);
src4xxx->mclk_hz = freq;
return 0;
}
static int src4xxx_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct src4xxx *src4xxx = snd_soc_component_get_drvdata(component);
unsigned int mclk_div;
int val, pj, jd, d;
int reg;
int ret;
switch (dai->id) {
case SRC4XXX_PORTB:
reg = SRC4XXX_PORTB_CTL_06;
break;
default:
reg = SRC4XXX_PORTA_CTL_04;
break;
}
if (src4xxx->master[dai->id]) {
mclk_div = src4xxx->mclk_hz/params_rate(params);
if (src4xxx->mclk_hz != mclk_div*params_rate(params)) {
dev_err(component->dev,
"mclk %d / rate %d has a remainder.\n",
src4xxx->mclk_hz, params_rate(params));
return -EINVAL;
}
val = ((int)mclk_div - 128) / 128;
if ((val < 0) | (val > 3)) {
dev_err(component->dev,
"div register setting %d is out of range\n",
val);
dev_err(component->dev,
"unsupported sample rate %d Hz for the master clock of %d Hz\n",
params_rate(params), src4xxx->mclk_hz);
return -EINVAL;
}
/* set the TX DIV */
ret = regmap_update_bits(src4xxx->regmap,
SRC4XXX_TX_CTL_07, SRC4XXX_TX_MCLK_DIV_MASK,
val<<SRC4XXX_TX_MCLK_DIV_SHIFT);
if (ret) {
dev_err(component->dev,
"Couldn't set the TX's div register to %d << %d = 0x%x\n",
val, SRC4XXX_TX_MCLK_DIV_SHIFT,
val<<SRC4XXX_TX_MCLK_DIV_SHIFT);
return ret;
}
/* set the PLL for the digital receiver */
switch (src4xxx->mclk_hz) {
case 24576000:
pj = 0x22;
jd = 0x00;
d = 0x00;
break;
case 22579200:
pj = 0x22;
jd = 0x1b;
d = 0xa3;
break;
default:
/* don't error out here,
* other parts of the chip are still functional
* Dummy initialize variables to avoid
* -Wsometimes-uninitialized from clang.
*/
dev_info(component->dev,
"Couldn't set the RCV PLL as this master clock rate is unknown. Chosen regmap values may not match real world values.\n");
pj = 0x0;
jd = 0xff;
d = 0xff;
break;
}
ret = regmap_write(src4xxx->regmap, SRC4XXX_RCV_PLL_0F, pj);
if (ret < 0)
dev_err(component->dev,
"Failed to update PLL register 0x%x\n",
SRC4XXX_RCV_PLL_0F);
ret = regmap_write(src4xxx->regmap, SRC4XXX_RCV_PLL_10, jd);
if (ret < 0)
dev_err(component->dev,
"Failed to update PLL register 0x%x\n",
SRC4XXX_RCV_PLL_10);
ret = regmap_write(src4xxx->regmap, SRC4XXX_RCV_PLL_11, d);
if (ret < 0)
dev_err(component->dev,
"Failed to update PLL register 0x%x\n",
SRC4XXX_RCV_PLL_11);
ret = regmap_update_bits(src4xxx->regmap,
SRC4XXX_TX_CTL_07, SRC4XXX_TX_MCLK_DIV_MASK,
val<<SRC4XXX_TX_MCLK_DIV_SHIFT);
if (ret < 0) {
dev_err(component->dev,
"Couldn't set the TX's div register to %d << %d = 0x%x\n",
val, SRC4XXX_TX_MCLK_DIV_SHIFT,
val<<SRC4XXX_TX_MCLK_DIV_SHIFT);
return ret;
}
return regmap_update_bits(src4xxx->regmap, reg,
SRC4XXX_MCLK_DIV_MASK, val);
} else {
dev_info(dai->dev, "not setting up MCLK as not master\n");
}
return 0;
};
static const struct snd_soc_dai_ops src4xxx_dai_ops = {
.hw_params = src4xxx_hw_params,
.set_sysclk = src4xxx_set_mclk_hz,
.set_fmt = src4xxx_set_dai_fmt,
};
#define SRC4XXX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
#define SRC4XXX_RATES (SNDRV_PCM_RATE_44100|SNDRV_PCM_RATE_48000|\
SNDRV_PCM_RATE_88200|\
SNDRV_PCM_RATE_96000|\
SNDRV_PCM_RATE_176400|\
SNDRV_PCM_RATE_192000)
static struct snd_soc_dai_driver src4xxx_dai_driver[] = {
{
.id = SRC4XXX_PORTA,
.name = "src4xxx-portA",
.playback = {
.stream_name = "Playback A",
.channels_min = 2,
.channels_max = 2,
.rates = SRC4XXX_RATES,
.formats = SRC4XXX_FORMATS,
},
.capture = {
.stream_name = "Capture A",
.channels_min = 2,
.channels_max = 2,
.rates = SRC4XXX_RATES,
.formats = SRC4XXX_FORMATS,
},
.ops = &src4xxx_dai_ops,
},
{
.id = SRC4XXX_PORTB,
.name = "src4xxx-portB",
.playback = {
.stream_name = "Playback B",
.channels_min = 2,
.channels_max = 2,
.rates = SRC4XXX_RATES,
.formats = SRC4XXX_FORMATS,
},
.capture = {
.stream_name = "Capture B",
.channels_min = 2,
.channels_max = 2,
.rates = SRC4XXX_RATES,
.formats = SRC4XXX_FORMATS,
},
.ops = &src4xxx_dai_ops,
},
};
static const struct reg_default src4xxx_reg_defaults[] = {
{ SRC4XXX_PWR_RST_01, 0x00 }, /* all powered down intially */
{ SRC4XXX_PORTA_CTL_03, 0x00 },
{ SRC4XXX_PORTA_CTL_04, 0x00 },
{ SRC4XXX_PORTB_CTL_05, 0x00 },
{ SRC4XXX_PORTB_CTL_06, 0x00 },
{ SRC4XXX_TX_CTL_07, 0x00 },
{ SRC4XXX_TX_CTL_08, 0x00 },
{ SRC4XXX_TX_CTL_09, 0x00 },
{ SRC4XXX_SRC_DIT_IRQ_MSK_0B, 0x00 },
{ SRC4XXX_SRC_DIT_IRQ_MODE_0C, 0x00 },
{ SRC4XXX_RCV_CTL_0D, 0x00 },
{ SRC4XXX_RCV_CTL_0E, 0x00 },
{ SRC4XXX_RCV_PLL_0F, 0x00 }, /* not spec. in the datasheet */
{ SRC4XXX_RCV_PLL_10, 0xff }, /* not spec. in the datasheet */
{ SRC4XXX_RCV_PLL_11, 0xff }, /* not spec. in the datasheet */
{ SRC4XXX_RVC_IRQ_MSK_16, 0x00 },
{ SRC4XXX_RVC_IRQ_MSK_17, 0x00 },
{ SRC4XXX_RVC_IRQ_MODE_18, 0x00 },
{ SRC4XXX_RVC_IRQ_MODE_19, 0x00 },
{ SRC4XXX_RVC_IRQ_MODE_1A, 0x00 },
{ SRC4XXX_GPIO_1_1B, 0x00 },
{ SRC4XXX_GPIO_2_1C, 0x00 },
{ SRC4XXX_GPIO_3_1D, 0x00 },
{ SRC4XXX_GPIO_4_1E, 0x00 },
{ SRC4XXX_SCR_CTL_2D, 0x00 },
{ SRC4XXX_SCR_CTL_2E, 0x00 },
{ SRC4XXX_SCR_CTL_2F, 0x00 },
{ SRC4XXX_SCR_CTL_30, 0x00 },
{ SRC4XXX_SCR_CTL_31, 0x00 },
};
int src4xxx_probe(struct device *dev, struct regmap *regmap,
void (*switch_mode)(struct device *dev))
{
struct src4xxx *src4xxx;
int ret;
if (IS_ERR(regmap))
return PTR_ERR(regmap);
src4xxx = devm_kzalloc(dev, sizeof(*src4xxx), GFP_KERNEL);
if (!src4xxx)
return -ENOMEM;
src4xxx->regmap = regmap;
src4xxx->dev = dev;
src4xxx->mclk_hz = 0; /* mclk has not been configured yet */
dev_set_drvdata(dev, src4xxx);
ret = regmap_write(regmap, SRC4XXX_PWR_RST_01, SRC4XXX_RESET);
if (ret < 0)
dev_err(dev, "Failed to issue reset: %d\n", ret);
usleep_range(1, 500); /* sleep for more then 500 ns */
ret = regmap_write(regmap, SRC4XXX_PWR_RST_01, SRC4XXX_POWER_DOWN);
if (ret < 0)
dev_err(dev, "Failed to decommission reset: %d\n", ret);
usleep_range(500, 1000); /* sleep for 500 us or more */
ret = regmap_update_bits(src4xxx->regmap, SRC4XXX_PWR_RST_01,
SRC4XXX_POWER_ENABLE, SRC4XXX_POWER_ENABLE);
if (ret < 0)
dev_err(dev, "Failed to port A and B : %d\n", ret);
/* set receiver to use master clock (rcv mclk is most likely jittery) */
ret = regmap_update_bits(src4xxx->regmap, SRC4XXX_RCV_CTL_0D,
SRC4XXX_RXCLK_MCLK, SRC4XXX_RXCLK_MCLK);
if (ret < 0)
dev_err(dev,
"Failed to enable mclk as the PLL1 DIR reference : %d\n", ret);
/* default to leaving the PLL2 running on loss of lock, divide by 8 */
ret = regmap_update_bits(src4xxx->regmap, SRC4XXX_RCV_CTL_0E,
SRC4XXX_PLL2_DIV_8 | SRC4XXX_REC_MCLK_EN | SRC4XXX_PLL2_LOL,
SRC4XXX_PLL2_DIV_8 | SRC4XXX_REC_MCLK_EN | SRC4XXX_PLL2_LOL);
if (ret < 0)
dev_err(dev, "Failed to enable mclk rec and div : %d\n", ret);
ret = devm_snd_soc_register_component(dev, &src4xxx_driver,
src4xxx_dai_driver, ARRAY_SIZE(src4xxx_dai_driver));
if (ret == 0)
dev_info(dev, "src4392 probe ok %d\n", ret);
return ret;
}
EXPORT_SYMBOL_GPL(src4xxx_probe);
static bool src4xxx_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case SRC4XXX_RES_00:
case SRC4XXX_GLOBAL_ITR_STS_02:
case SRC4XXX_SRC_DIT_STS_0A:
case SRC4XXX_NON_AUDIO_D_12:
case SRC4XXX_RVC_STS_13:
case SRC4XXX_RVC_STS_14:
case SRC4XXX_RVC_STS_15:
case SRC4XXX_SUB_CODE_1F:
case SRC4XXX_SUB_CODE_20:
case SRC4XXX_SUB_CODE_21:
case SRC4XXX_SUB_CODE_22:
case SRC4XXX_SUB_CODE_23:
case SRC4XXX_SUB_CODE_24:
case SRC4XXX_SUB_CODE_25:
case SRC4XXX_SUB_CODE_26:
case SRC4XXX_SUB_CODE_27:
case SRC4XXX_SUB_CODE_28:
case SRC4XXX_PC_PREAMBLE_HI_29:
case SRC4XXX_PC_PREAMBLE_LO_2A:
case SRC4XXX_PD_PREAMBLE_HI_2B:
case SRC4XXX_PC_PREAMBLE_LO_2C:
case SRC4XXX_IO_RATIO_32:
case SRC4XXX_IO_RATIO_33:
return true;
}
if (reg > SRC4XXX_IO_RATIO_33 && reg < SRC4XXX_PAGE_SEL_7F)
return true;
return false;
}
const struct regmap_config src4xxx_regmap_config = {
.val_bits = 8,
.reg_bits = 8,
.max_register = SRC4XXX_IO_RATIO_33,
.reg_defaults = src4xxx_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(src4xxx_reg_defaults),
.volatile_reg = src4xxx_volatile_register,
.cache_type = REGCACHE_RBTREE,
};
EXPORT_SYMBOL_GPL(src4xxx_regmap_config);
MODULE_DESCRIPTION("ASoC SRC4XXX CODEC driver");
MODULE_AUTHOR("Matt Flax <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/src4xxx.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* PCM3168A codec i2c driver
*
* Copyright (C) 2015 Imagination Technologies Ltd.
*
* Author: Damien Horsley <[email protected]>
*/
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/module.h>
#include <sound/soc.h>
#include "pcm3168a.h"
static int pcm3168a_i2c_probe(struct i2c_client *i2c)
{
struct regmap *regmap;
regmap = devm_regmap_init_i2c(i2c, &pcm3168a_regmap);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
return pcm3168a_probe(&i2c->dev, regmap);
}
static void pcm3168a_i2c_remove(struct i2c_client *i2c)
{
pcm3168a_remove(&i2c->dev);
}
static const struct i2c_device_id pcm3168a_i2c_id[] = {
{ "pcm3168a", },
{ }
};
MODULE_DEVICE_TABLE(i2c, pcm3168a_i2c_id);
static const struct of_device_id pcm3168a_of_match[] = {
{ .compatible = "ti,pcm3168a", },
{ }
};
MODULE_DEVICE_TABLE(of, pcm3168a_of_match);
static struct i2c_driver pcm3168a_i2c_driver = {
.probe = pcm3168a_i2c_probe,
.remove = pcm3168a_i2c_remove,
.id_table = pcm3168a_i2c_id,
.driver = {
.name = "pcm3168a",
.of_match_table = pcm3168a_of_match,
.pm = &pcm3168a_pm_ops,
},
};
module_i2c_driver(pcm3168a_i2c_driver);
MODULE_DESCRIPTION("PCM3168A I2C codec driver");
MODULE_AUTHOR("Damien Horsley <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/pcm3168a-i2c.c |
// SPDX-License-Identifier: GPL-2.0
//
// Driver for SRC4XXX codecs
//
// Copyright 2021-2022 Deqx Pty Ltd
// Author: Matt Flax <[email protected]>
#include <linux/i2c.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include "src4xxx.h"
static int src4xxx_i2c_probe(struct i2c_client *i2c)
{
return src4xxx_probe(&i2c->dev,
devm_regmap_init_i2c(i2c, &src4xxx_regmap_config), NULL);
}
static const struct i2c_device_id src4xxx_i2c_ids[] = {
{ "src4392", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, src4xxx_i2c_ids);
static const struct of_device_id src4xxx_of_match[] __maybe_unused = {
{ .compatible = "ti,src4392", },
{ }
};
MODULE_DEVICE_TABLE(of, src4xxx_of_match);
static struct i2c_driver src4xxx_i2c_driver = {
.driver = {
.name = "src4xxx",
.of_match_table = of_match_ptr(src4xxx_of_match),
},
.probe = src4xxx_i2c_probe,
.id_table = src4xxx_i2c_ids,
};
module_i2c_driver(src4xxx_i2c_driver);
MODULE_DESCRIPTION("ASoC SRC4392 CODEC I2C driver");
MODULE_AUTHOR("Matt Flax <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/codecs/src4xxx-i2c.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Codec driver for Microsemi ZL38060 Connected Home Audio Processor.
//
// Copyright(c) 2020 Sven Van Asbroeck
// The ZL38060 is very flexible and configurable. This driver implements only a
// tiny subset of the chip's possible configurations:
//
// - DSP block bypassed: DAI routed straight to DACs
// microphone routed straight to DAI
// - chip's internal clock is driven by a 12 MHz external crystal
// - chip's DAI connected to CPU is I2S, and bit + frame clock master
// - chip must be strapped for "host boot": in this mode, firmware will be
// provided by this driver.
#include <linux/gpio/consumer.h>
#include <linux/gpio/driver.h>
#include <linux/property.h>
#include <linux/spi/spi.h>
#include <linux/regmap.h>
#include <linux/module.h>
#include <linux/ihex.h>
#include <sound/pcm_params.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/soc.h>
#define DRV_NAME "zl38060"
#define ZL38_RATES (SNDRV_PCM_RATE_8000 |\
SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_48000)
#define ZL38_FORMATS SNDRV_PCM_FMTBIT_S16_LE
#define HBI_FIRMWARE_PAGE 0xFF
#define ZL38_MAX_RAW_XFER 0x100
#define REG_TDMA_CFG_CLK 0x0262
#define CFG_CLK_PCLK_SHIFT 4
#define CFG_CLK_PCLK_MASK (0x7ff << CFG_CLK_PCLK_SHIFT)
#define CFG_CLK_PCLK(bits) ((bits - 1) << CFG_CLK_PCLK_SHIFT)
#define CFG_CLK_MASTER BIT(15)
#define CFG_CLK_FSRATE_MASK 0x7
#define CFG_CLK_FSRATE_8KHZ 0x1
#define CFG_CLK_FSRATE_16KHZ 0x2
#define CFG_CLK_FSRATE_48KHZ 0x6
#define REG_CLK_CFG 0x0016
#define CLK_CFG_SOURCE_XTAL BIT(15)
#define REG_CLK_STATUS 0x0014
#define CLK_STATUS_HWRST BIT(0)
#define REG_PARAM_RESULT 0x0034
#define PARAM_RESULT_READY 0xD3D3
#define REG_PG255_BASE_HI 0x000C
#define REG_PG255_OFFS(addr) ((HBI_FIRMWARE_PAGE << 8) | (addr & 0xFF))
#define REG_FWR_EXEC 0x012C
#define REG_CMD 0x0032
#define REG_HW_REV 0x0020
#define REG_FW_PROD 0x0022
#define REG_FW_REV 0x0024
#define REG_SEMA_FLAGS 0x0006
#define SEMA_FLAGS_BOOT_CMD BIT(0)
#define SEMA_FLAGS_APP_REBOOT BIT(1)
#define REG_HW_REV 0x0020
#define REG_FW_PROD 0x0022
#define REG_FW_REV 0x0024
#define REG_GPIO_DIR 0x02DC
#define REG_GPIO_DAT 0x02DA
#define BOOTCMD_LOAD_COMPLETE 0x000D
#define BOOTCMD_FW_GO 0x0008
#define FIRMWARE_MAJOR 2
#define FIRMWARE_MINOR 2
struct zl38_codec_priv {
struct device *dev;
struct regmap *regmap;
bool is_stream_in_use[2];
struct gpio_chip *gpio_chip;
};
static int zl38_fw_issue_command(struct regmap *regmap, u16 cmd)
{
unsigned int val;
int err;
err = regmap_read_poll_timeout(regmap, REG_SEMA_FLAGS, val,
!(val & SEMA_FLAGS_BOOT_CMD), 10000,
10000 * 100);
if (err)
return err;
err = regmap_write(regmap, REG_CMD, cmd);
if (err)
return err;
err = regmap_update_bits(regmap, REG_SEMA_FLAGS, SEMA_FLAGS_BOOT_CMD,
SEMA_FLAGS_BOOT_CMD);
if (err)
return err;
return regmap_read_poll_timeout(regmap, REG_CMD, val, !val, 10000,
10000 * 100);
}
static int zl38_fw_go(struct regmap *regmap)
{
int err;
err = zl38_fw_issue_command(regmap, BOOTCMD_LOAD_COMPLETE);
if (err)
return err;
return zl38_fw_issue_command(regmap, BOOTCMD_FW_GO);
}
static int zl38_fw_enter_boot_mode(struct regmap *regmap)
{
unsigned int val;
int err;
err = regmap_update_bits(regmap, REG_CLK_STATUS, CLK_STATUS_HWRST,
CLK_STATUS_HWRST);
if (err)
return err;
return regmap_read_poll_timeout(regmap, REG_PARAM_RESULT, val,
val == PARAM_RESULT_READY, 1000, 50000);
}
static int
zl38_fw_send_data(struct regmap *regmap, u32 addr, const void *data, u16 len)
{
__be32 addr_base = cpu_to_be32(addr & ~0xFF);
int err;
err = regmap_raw_write(regmap, REG_PG255_BASE_HI, &addr_base,
sizeof(addr_base));
if (err)
return err;
return regmap_raw_write(regmap, REG_PG255_OFFS(addr), data, len);
}
static int zl38_fw_send_xaddr(struct regmap *regmap, const void *data)
{
/* execution address from ihex: 32-bit little endian.
* device register expects 32-bit big endian.
*/
u32 addr = le32_to_cpup(data);
__be32 baddr = cpu_to_be32(addr);
return regmap_raw_write(regmap, REG_FWR_EXEC, &baddr, sizeof(baddr));
}
static int zl38_load_firmware(struct device *dev, struct regmap *regmap)
{
const struct ihex_binrec *rec;
const struct firmware *fw;
u32 addr;
u16 len;
int err;
/* how to get this firmware:
* 1. request and download chip firmware from Microsemi
* (provided by Microsemi in srec format)
* 2. convert downloaded firmware from srec to ihex. Simple tool:
* https://gitlab.com/TheSven73/s3-to-irec
* 3. convert ihex to binary (.fw) using ihex2fw tool which is included
* with the Linux kernel sources
*/
err = request_ihex_firmware(&fw, "zl38060.fw", dev);
if (err)
return err;
err = zl38_fw_enter_boot_mode(regmap);
if (err)
goto out;
rec = (const struct ihex_binrec *)fw->data;
while (rec) {
addr = be32_to_cpu(rec->addr);
len = be16_to_cpu(rec->len);
if (addr) {
/* regular data ihex record */
err = zl38_fw_send_data(regmap, addr, rec->data, len);
} else if (len == 4) {
/* execution address ihex record */
err = zl38_fw_send_xaddr(regmap, rec->data);
} else {
err = -EINVAL;
}
if (err)
goto out;
/* next ! */
rec = ihex_next_binrec(rec);
}
err = zl38_fw_go(regmap);
out:
release_firmware(fw);
return err;
}
static int zl38_software_reset(struct regmap *regmap)
{
unsigned int val;
int err;
err = regmap_update_bits(regmap, REG_SEMA_FLAGS, SEMA_FLAGS_APP_REBOOT,
SEMA_FLAGS_APP_REBOOT);
if (err)
return err;
/* wait for host bus interface to settle.
* Not sure if this is required: Microsemi's vendor driver does this,
* but the firmware manual does not mention it. Leave it in, there's
* little downside, apart from a slower reset.
*/
msleep(50);
return regmap_read_poll_timeout(regmap, REG_SEMA_FLAGS, val,
!(val & SEMA_FLAGS_APP_REBOOT), 10000,
10000 * 100);
}
static int zl38_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct zl38_codec_priv *priv = snd_soc_dai_get_drvdata(dai);
int err;
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
/* firmware default is normal i2s */
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
/* firmware default is normal bitclock and frame */
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
/* always 32 bits per frame (= 16 bits/channel, 2 channels) */
err = regmap_update_bits(priv->regmap, REG_TDMA_CFG_CLK,
CFG_CLK_MASTER | CFG_CLK_PCLK_MASK,
CFG_CLK_MASTER | CFG_CLK_PCLK(32));
if (err)
return err;
break;
default:
return -EINVAL;
}
return 0;
}
static int zl38_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct zl38_codec_priv *priv = snd_soc_dai_get_drvdata(dai);
bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
unsigned int fsrate;
int err;
/* We cannot change hw_params while the dai is already in use - the
* software reset will corrupt the audio. However, this is not required,
* as the chip's TDM buses are fully symmetric, which mandates identical
* rates, channels, and samplebits for record and playback.
*/
if (priv->is_stream_in_use[!tx])
goto skip_setup;
switch (params_rate(params)) {
case 8000:
fsrate = CFG_CLK_FSRATE_8KHZ;
break;
case 16000:
fsrate = CFG_CLK_FSRATE_16KHZ;
break;
case 48000:
fsrate = CFG_CLK_FSRATE_48KHZ;
break;
default:
return -EINVAL;
}
err = regmap_update_bits(priv->regmap, REG_TDMA_CFG_CLK,
CFG_CLK_FSRATE_MASK, fsrate);
if (err)
return err;
/* chip requires a software reset to apply audio register changes */
err = zl38_software_reset(priv->regmap);
if (err)
return err;
skip_setup:
priv->is_stream_in_use[tx] = true;
return 0;
}
static int zl38_hw_free(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct zl38_codec_priv *priv = snd_soc_dai_get_drvdata(dai);
bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
priv->is_stream_in_use[tx] = false;
return 0;
}
/* stereo bypass with no AEC */
static const struct reg_sequence cp_config_stereo_bypass[] = {
/* interconnects must be programmed first */
{ 0x0210, 0x0005 }, /* DAC1 in <= I2S1-L */
{ 0x0212, 0x0006 }, /* DAC2 in <= I2S1-R */
{ 0x0214, 0x0001 }, /* I2S1-L in <= MIC1 */
{ 0x0216, 0x0001 }, /* I2S1-R in <= MIC1 */
{ 0x0224, 0x0000 }, /* AEC-S in <= n/a */
{ 0x0226, 0x0000 }, /* AEC-R in <= n/a */
/* output enables must be programmed next */
{ 0x0202, 0x000F }, /* enable I2S1 + DAC */
};
static const struct snd_soc_dai_ops zl38_dai_ops = {
.set_fmt = zl38_set_fmt,
.hw_params = zl38_hw_params,
.hw_free = zl38_hw_free,
};
static struct snd_soc_dai_driver zl38_dai = {
.name = "zl38060-tdma",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = ZL38_RATES,
.formats = ZL38_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 2,
.rates = ZL38_RATES,
.formats = ZL38_FORMATS,
},
.ops = &zl38_dai_ops,
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
.symmetric_channels = 1,
};
static const struct snd_soc_dapm_widget zl38_dapm_widgets[] = {
SND_SOC_DAPM_OUTPUT("DAC1"),
SND_SOC_DAPM_OUTPUT("DAC2"),
SND_SOC_DAPM_INPUT("DMICL"),
};
static const struct snd_soc_dapm_route zl38_dapm_routes[] = {
{ "DAC1", NULL, "Playback" },
{ "DAC2", NULL, "Playback" },
{ "Capture", NULL, "DMICL" },
};
static const struct snd_soc_component_driver zl38_component_dev = {
.dapm_widgets = zl38_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(zl38_dapm_widgets),
.dapm_routes = zl38_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(zl38_dapm_routes),
.endianness = 1,
};
static void chip_gpio_set(struct gpio_chip *c, unsigned int offset, int val)
{
struct regmap *regmap = gpiochip_get_data(c);
unsigned int mask = BIT(offset);
regmap_update_bits(regmap, REG_GPIO_DAT, mask, val ? mask : 0);
}
static int chip_gpio_get(struct gpio_chip *c, unsigned int offset)
{
struct regmap *regmap = gpiochip_get_data(c);
unsigned int mask = BIT(offset);
unsigned int val;
int err;
err = regmap_read(regmap, REG_GPIO_DAT, &val);
if (err)
return err;
return !!(val & mask);
}
static int chip_direction_input(struct gpio_chip *c, unsigned int offset)
{
struct regmap *regmap = gpiochip_get_data(c);
unsigned int mask = BIT(offset);
return regmap_update_bits(regmap, REG_GPIO_DIR, mask, 0);
}
static int
chip_direction_output(struct gpio_chip *c, unsigned int offset, int val)
{
struct regmap *regmap = gpiochip_get_data(c);
unsigned int mask = BIT(offset);
chip_gpio_set(c, offset, val);
return regmap_update_bits(regmap, REG_GPIO_DIR, mask, mask);
}
static const struct gpio_chip template_chip = {
.owner = THIS_MODULE,
.label = DRV_NAME,
.base = -1,
.ngpio = 14,
.direction_input = chip_direction_input,
.direction_output = chip_direction_output,
.get = chip_gpio_get,
.set = chip_gpio_set,
.can_sleep = true,
};
static int zl38_check_revision(struct device *dev, struct regmap *regmap)
{
unsigned int hwrev, fwprod, fwrev;
int fw_major, fw_minor, fw_micro;
int err;
err = regmap_read(regmap, REG_HW_REV, &hwrev);
if (err)
return err;
err = regmap_read(regmap, REG_FW_PROD, &fwprod);
if (err)
return err;
err = regmap_read(regmap, REG_FW_REV, &fwrev);
if (err)
return err;
fw_major = (fwrev >> 12) & 0xF;
fw_minor = (fwrev >> 8) & 0xF;
fw_micro = fwrev & 0xFF;
dev_info(dev, "hw rev 0x%x, fw product code %d, firmware rev %d.%d.%d",
hwrev & 0x1F, fwprod, fw_major, fw_minor, fw_micro);
if (fw_major != FIRMWARE_MAJOR || fw_minor < FIRMWARE_MINOR) {
dev_err(dev, "unsupported firmware. driver supports %d.%d",
FIRMWARE_MAJOR, FIRMWARE_MINOR);
return -EINVAL;
}
return 0;
}
static int zl38_bus_read(void *context,
const void *reg_buf, size_t reg_size,
void *val_buf, size_t val_size)
{
struct spi_device *spi = context;
const u8 *reg_buf8 = reg_buf;
size_t len = 0;
u8 offs, page;
u8 txbuf[4];
if (reg_size != 2 || val_size > ZL38_MAX_RAW_XFER)
return -EINVAL;
offs = reg_buf8[1] >> 1;
page = reg_buf8[0];
if (page) {
txbuf[len++] = 0xFE;
txbuf[len++] = page == HBI_FIRMWARE_PAGE ? 0xFF : page - 1;
txbuf[len++] = offs;
txbuf[len++] = val_size / 2 - 1;
} else {
txbuf[len++] = offs | 0x80;
txbuf[len++] = val_size / 2 - 1;
}
return spi_write_then_read(spi, txbuf, len, val_buf, val_size);
}
static int zl38_bus_write(void *context, const void *data, size_t count)
{
struct spi_device *spi = context;
u8 buf[4 + ZL38_MAX_RAW_XFER];
size_t val_len, len = 0;
const u8 *data8 = data;
u8 offs, page;
if (count > (2 + ZL38_MAX_RAW_XFER) || count < 4)
return -EINVAL;
val_len = count - 2;
offs = data8[1] >> 1;
page = data8[0];
if (page) {
buf[len++] = 0xFE;
buf[len++] = page == HBI_FIRMWARE_PAGE ? 0xFF : page - 1;
buf[len++] = offs;
buf[len++] = (val_len / 2 - 1) | 0x80;
} else {
buf[len++] = offs | 0x80;
buf[len++] = (val_len / 2 - 1) | 0x80;
}
memcpy(buf + len, data8 + 2, val_len);
len += val_len;
return spi_write(spi, buf, len);
}
static const struct regmap_bus zl38_regmap_bus = {
.read = zl38_bus_read,
.write = zl38_bus_write,
.max_raw_write = ZL38_MAX_RAW_XFER,
.max_raw_read = ZL38_MAX_RAW_XFER,
};
static const struct regmap_config zl38_regmap_conf = {
.reg_bits = 16,
.val_bits = 16,
.reg_stride = 2,
.use_single_read = true,
.use_single_write = true,
};
static int zl38_spi_probe(struct spi_device *spi)
{
struct device *dev = &spi->dev;
struct zl38_codec_priv *priv;
struct gpio_desc *reset_gpio;
int err;
/* get the chip to a known state by putting it in reset */
reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
if (IS_ERR(reset_gpio))
return PTR_ERR(reset_gpio);
if (reset_gpio) {
/* datasheet: need > 10us for a digital + analog reset */
usleep_range(15, 50);
/* take the chip out of reset */
gpiod_set_value_cansleep(reset_gpio, 0);
/* datasheet: need > 3ms for digital section to become stable */
usleep_range(3000, 10000);
}
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->dev = dev;
dev_set_drvdata(dev, priv);
priv->regmap = devm_regmap_init(dev, &zl38_regmap_bus, spi,
&zl38_regmap_conf);
if (IS_ERR(priv->regmap))
return PTR_ERR(priv->regmap);
err = zl38_load_firmware(dev, priv->regmap);
if (err)
return err;
err = zl38_check_revision(dev, priv->regmap);
if (err)
return err;
priv->gpio_chip = devm_kmemdup(dev, &template_chip,
sizeof(template_chip), GFP_KERNEL);
if (!priv->gpio_chip)
return -ENOMEM;
priv->gpio_chip->parent = dev;
err = devm_gpiochip_add_data(dev, priv->gpio_chip, priv->regmap);
if (err)
return err;
/* setup the cross-point switch for stereo bypass */
err = regmap_multi_reg_write(priv->regmap, cp_config_stereo_bypass,
ARRAY_SIZE(cp_config_stereo_bypass));
if (err)
return err;
/* setup for 12MHz crystal connected to the chip */
err = regmap_update_bits(priv->regmap, REG_CLK_CFG, CLK_CFG_SOURCE_XTAL,
CLK_CFG_SOURCE_XTAL);
if (err)
return err;
return devm_snd_soc_register_component(dev, &zl38_component_dev,
&zl38_dai, 1);
}
static const struct of_device_id zl38_dt_ids[] __maybe_unused = {
{ .compatible = "mscc,zl38060", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, zl38_dt_ids);
static const struct spi_device_id zl38_spi_ids[] = {
{ "zl38060", 0 },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(spi, zl38_spi_ids);
static struct spi_driver zl38060_spi_driver = {
.driver = {
.name = DRV_NAME,
.of_match_table = of_match_ptr(zl38_dt_ids),
},
.probe = zl38_spi_probe,
.id_table = zl38_spi_ids,
};
module_spi_driver(zl38060_spi_driver);
MODULE_DESCRIPTION("ASoC ZL38060 driver");
MODULE_AUTHOR("Sven Van Asbroeck <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/zl38060.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// aw88395_device.c -- AW88395 function for ALSA Audio Driver
//
// Copyright (c) 2022-2023 AWINIC Technology CO., LTD
//
// Author: Bruce zhao <[email protected]>
// Author: Ben Yi <[email protected]>
//
#include <linux/crc32.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include "aw88395_device.h"
#include "aw88395_reg.h"
static int aw_dev_dsp_write_16bit(struct aw_device *aw_dev,
unsigned short dsp_addr, unsigned int dsp_data)
{
int ret;
ret = regmap_write(aw_dev->regmap, AW88395_DSPMADD_REG, dsp_addr);
if (ret) {
dev_err(aw_dev->dev, "%s write addr error, ret=%d", __func__, ret);
return ret;
}
ret = regmap_write(aw_dev->regmap, AW88395_DSPMDAT_REG, (u16)dsp_data);
if (ret) {
dev_err(aw_dev->dev, "%s write data error, ret=%d", __func__, ret);
return ret;
}
return 0;
}
static int aw_dev_dsp_write_32bit(struct aw_device *aw_dev,
unsigned short dsp_addr, unsigned int dsp_data)
{
u16 temp_data;
int ret;
ret = regmap_write(aw_dev->regmap, AW88395_DSPMADD_REG, dsp_addr);
if (ret) {
dev_err(aw_dev->dev, "%s write addr error, ret=%d", __func__, ret);
return ret;
}
temp_data = dsp_data & AW88395_DSP_16_DATA_MASK;
ret = regmap_write(aw_dev->regmap, AW88395_DSPMDAT_REG, (u16)temp_data);
if (ret) {
dev_err(aw_dev->dev, "%s write datal error, ret=%d", __func__, ret);
return ret;
}
temp_data = dsp_data >> 16;
ret = regmap_write(aw_dev->regmap, AW88395_DSPMDAT_REG, (u16)temp_data);
if (ret) {
dev_err(aw_dev->dev, "%s write datah error, ret=%d", __func__, ret);
return ret;
}
return 0;
}
static int aw_dev_dsp_write(struct aw_device *aw_dev,
unsigned short dsp_addr, unsigned int dsp_data, unsigned char data_type)
{
u32 reg_value;
int ret;
mutex_lock(&aw_dev->dsp_lock);
switch (data_type) {
case AW88395_DSP_16_DATA:
ret = aw_dev_dsp_write_16bit(aw_dev, dsp_addr, dsp_data);
if (ret)
dev_err(aw_dev->dev, "write dsp_addr[0x%x] 16-bit dsp_data[0x%x] failed",
(u32)dsp_addr, dsp_data);
break;
case AW88395_DSP_32_DATA:
ret = aw_dev_dsp_write_32bit(aw_dev, dsp_addr, dsp_data);
if (ret)
dev_err(aw_dev->dev, "write dsp_addr[0x%x] 32-bit dsp_data[0x%x] failed",
(u32)dsp_addr, dsp_data);
break;
default:
dev_err(aw_dev->dev, "data type[%d] unsupported", data_type);
ret = -EINVAL;
break;
}
/* clear dsp chip select state*/
if (regmap_read(aw_dev->regmap, AW88395_ID_REG, ®_value))
dev_err(aw_dev->dev, "%s fail to clear chip state. Err=%d\n", __func__, ret);
mutex_unlock(&aw_dev->dsp_lock);
return ret;
}
static int aw_dev_dsp_read_16bit(struct aw_device *aw_dev,
unsigned short dsp_addr, unsigned int *dsp_data)
{
unsigned int temp_data;
int ret;
ret = regmap_write(aw_dev->regmap, AW88395_DSPMADD_REG, dsp_addr);
if (ret) {
dev_err(aw_dev->dev, "%s write error, ret=%d", __func__, ret);
return ret;
}
ret = regmap_read(aw_dev->regmap, AW88395_DSPMDAT_REG, &temp_data);
if (ret) {
dev_err(aw_dev->dev, "%s read error, ret=%d", __func__, ret);
return ret;
}
*dsp_data = temp_data;
return 0;
}
static int aw_dev_dsp_read_32bit(struct aw_device *aw_dev,
unsigned short dsp_addr, unsigned int *dsp_data)
{
unsigned int temp_data;
int ret;
ret = regmap_write(aw_dev->regmap, AW88395_DSPMADD_REG, dsp_addr);
if (ret) {
dev_err(aw_dev->dev, "%s write error, ret=%d", __func__, ret);
return ret;
}
ret = regmap_read(aw_dev->regmap, AW88395_DSPMDAT_REG, &temp_data);
if (ret) {
dev_err(aw_dev->dev, "%s read error, ret=%d", __func__, ret);
return ret;
}
*dsp_data = temp_data;
ret = regmap_read(aw_dev->regmap, AW88395_DSPMDAT_REG, &temp_data);
if (ret) {
dev_err(aw_dev->dev, "%s read error, ret=%d", __func__, ret);
return ret;
}
*dsp_data |= (temp_data << 16);
return 0;
}
static int aw_dev_dsp_read(struct aw_device *aw_dev,
unsigned short dsp_addr, unsigned int *dsp_data, unsigned char data_type)
{
u32 reg_value;
int ret;
mutex_lock(&aw_dev->dsp_lock);
switch (data_type) {
case AW88395_DSP_16_DATA:
ret = aw_dev_dsp_read_16bit(aw_dev, dsp_addr, dsp_data);
if (ret)
dev_err(aw_dev->dev, "read dsp_addr[0x%x] 16-bit dsp_data[0x%x] failed",
(u32)dsp_addr, *dsp_data);
break;
case AW88395_DSP_32_DATA:
ret = aw_dev_dsp_read_32bit(aw_dev, dsp_addr, dsp_data);
if (ret)
dev_err(aw_dev->dev, "read dsp_addr[0x%x] 32r-bit dsp_data[0x%x] failed",
(u32)dsp_addr, *dsp_data);
break;
default:
dev_err(aw_dev->dev, "data type[%d] unsupported", data_type);
ret = -EINVAL;
break;
}
/* clear dsp chip select state*/
if (regmap_read(aw_dev->regmap, AW88395_ID_REG, ®_value))
dev_err(aw_dev->dev, "%s fail to clear chip state. Err=%d\n", __func__, ret);
mutex_unlock(&aw_dev->dsp_lock);
return ret;
}
static int aw_dev_read_chipid(struct aw_device *aw_dev, u16 *chip_id)
{
int reg_val;
int ret;
ret = regmap_read(aw_dev->regmap, AW88395_CHIP_ID_REG, ®_val);
if (ret) {
dev_err(aw_dev->dev, "%s read chipid error. ret = %d", __func__, ret);
return ret;
}
dev_info(aw_dev->dev, "chip id = %x\n", reg_val);
*chip_id = reg_val;
return 0;
}
static unsigned int reg_val_to_db(unsigned int value)
{
return (((value >> AW88395_VOL_6DB_START) * AW88395_VOLUME_STEP_DB) +
((value & 0x3f) % AW88395_VOLUME_STEP_DB));
}
static unsigned short db_to_reg_val(unsigned short value)
{
return (((value / AW88395_VOLUME_STEP_DB) << AW88395_VOL_6DB_START) +
(value % AW88395_VOLUME_STEP_DB));
}
static int aw_dev_dsp_fw_check(struct aw_device *aw_dev)
{
struct aw_sec_data_desc *dsp_fw_desc;
struct aw_prof_desc *set_prof_desc;
u16 base_addr = AW88395_DSP_FW_ADDR;
u16 addr = base_addr;
u32 dsp_val;
u16 bin_val;
int ret, i;
ret = aw88395_dev_get_prof_data(aw_dev, aw_dev->prof_cur, &set_prof_desc);
if (ret)
return ret;
/* update reg */
dsp_fw_desc = &set_prof_desc->sec_desc[AW88395_DATA_TYPE_DSP_FW];
for (i = 0; i < AW88395_FW_CHECK_PART; i++) {
ret = aw_dev_dsp_read(aw_dev, addr, &dsp_val, AW88395_DSP_16_DATA);
if (ret) {
dev_err(aw_dev->dev, "dsp read failed");
return ret;
}
bin_val = be16_to_cpup((void *)&dsp_fw_desc->data[2 * (addr - base_addr)]);
if (dsp_val != bin_val) {
dev_err(aw_dev->dev, "fw check failed, addr[0x%x], read[0x%x] != bindata[0x%x]",
addr, dsp_val, bin_val);
return -EINVAL;
}
addr += (dsp_fw_desc->len / 2) / AW88395_FW_CHECK_PART;
if ((addr - base_addr) > dsp_fw_desc->len) {
dev_err(aw_dev->dev, "fw check failed, addr[0x%x] too large", addr);
return -EINVAL;
}
}
return 0;
}
static int aw_dev_set_volume(struct aw_device *aw_dev, unsigned int value)
{
struct aw_volume_desc *vol_desc = &aw_dev->volume_desc;
unsigned int reg_value;
u16 real_value, volume;
int ret;
volume = min((value + vol_desc->init_volume), (unsigned int)AW88395_MUTE_VOL);
real_value = db_to_reg_val(volume);
/* cal real value */
ret = regmap_read(aw_dev->regmap, AW88395_SYSCTRL2_REG, ®_value);
if (ret)
return ret;
dev_dbg(aw_dev->dev, "value 0x%x , reg:0x%x", value, real_value);
/* [15 : 6] volume */
real_value = (real_value << AW88395_VOL_START_BIT) | (reg_value & AW88395_VOL_MASK);
/* write value */
ret = regmap_write(aw_dev->regmap, AW88395_SYSCTRL2_REG, real_value);
return ret;
}
void aw88395_dev_set_volume(struct aw_device *aw_dev, unsigned short set_vol)
{
int ret;
ret = aw_dev_set_volume(aw_dev, set_vol);
if (ret)
dev_dbg(aw_dev->dev, "set volume failed");
}
EXPORT_SYMBOL_GPL(aw88395_dev_set_volume);
static void aw_dev_fade_in(struct aw_device *aw_dev)
{
struct aw_volume_desc *desc = &aw_dev->volume_desc;
u16 fade_in_vol = desc->ctl_volume;
int fade_step = aw_dev->fade_step;
int i;
if (!aw_dev->fade_en)
return;
if (fade_step == 0 || aw_dev->fade_in_time == 0) {
aw_dev_set_volume(aw_dev, fade_in_vol);
return;
}
for (i = AW88395_MUTE_VOL; i >= fade_in_vol; i -= fade_step) {
aw_dev_set_volume(aw_dev, i);
usleep_range(aw_dev->fade_in_time, aw_dev->fade_in_time + 10);
}
if (i != fade_in_vol)
aw_dev_set_volume(aw_dev, fade_in_vol);
}
static void aw_dev_fade_out(struct aw_device *aw_dev)
{
struct aw_volume_desc *desc = &aw_dev->volume_desc;
int fade_step = aw_dev->fade_step;
int i;
if (!aw_dev->fade_en)
return;
if (fade_step == 0 || aw_dev->fade_out_time == 0) {
aw_dev_set_volume(aw_dev, AW88395_MUTE_VOL);
return;
}
for (i = desc->ctl_volume; i <= AW88395_MUTE_VOL; i += fade_step) {
aw_dev_set_volume(aw_dev, i);
usleep_range(aw_dev->fade_out_time, aw_dev->fade_out_time + 10);
}
if (i != AW88395_MUTE_VOL) {
aw_dev_set_volume(aw_dev, AW88395_MUTE_VOL);
usleep_range(aw_dev->fade_out_time, aw_dev->fade_out_time + 10);
}
}
static int aw_dev_modify_dsp_cfg(struct aw_device *aw_dev,
unsigned int addr, unsigned int dsp_data, unsigned char data_type)
{
struct aw_sec_data_desc *crc_dsp_cfg = &aw_dev->crc_dsp_cfg;
unsigned int addr_offset;
__le16 data1;
__le32 data2;
dev_dbg(aw_dev->dev, "addr:0x%x, dsp_data:0x%x", addr, dsp_data);
addr_offset = (addr - AW88395_DSP_CFG_ADDR) * 2;
if (addr_offset > crc_dsp_cfg->len) {
dev_err(aw_dev->dev, "addr_offset[%d] > crc_dsp_cfg->len[%d]",
addr_offset, crc_dsp_cfg->len);
return -EINVAL;
}
switch (data_type) {
case AW88395_DSP_16_DATA:
data1 = cpu_to_le16((u16)dsp_data);
memcpy(crc_dsp_cfg->data + addr_offset, (u8 *)&data1, 2);
break;
case AW88395_DSP_32_DATA:
data2 = cpu_to_le32(dsp_data);
memcpy(crc_dsp_cfg->data + addr_offset, (u8 *)&data2, 4);
break;
default:
dev_err(aw_dev->dev, "data type[%d] unsupported", data_type);
return -EINVAL;
}
return 0;
}
static int aw_dev_dsp_set_cali_re(struct aw_device *aw_dev)
{
u32 cali_re;
int ret;
cali_re = AW88395_SHOW_RE_TO_DSP_RE((aw_dev->cali_desc.cali_re +
aw_dev->cali_desc.ra), AW88395_DSP_RE_SHIFT);
/* set cali re to device */
ret = aw_dev_dsp_write(aw_dev,
AW88395_DSP_REG_CFG_ADPZ_RE, cali_re, AW88395_DSP_32_DATA);
if (ret) {
dev_err(aw_dev->dev, "set cali re error");
return ret;
}
ret = aw_dev_modify_dsp_cfg(aw_dev, AW88395_DSP_REG_CFG_ADPZ_RE,
cali_re, AW88395_DSP_32_DATA);
if (ret)
dev_err(aw_dev->dev, "modify dsp cfg failed");
return ret;
}
static void aw_dev_i2s_tx_enable(struct aw_device *aw_dev, bool flag)
{
int ret;
if (flag) {
ret = regmap_update_bits(aw_dev->regmap, AW88395_I2SCFG1_REG,
~AW88395_I2STXEN_MASK, AW88395_I2STXEN_ENABLE_VALUE);
} else {
ret = regmap_update_bits(aw_dev->regmap, AW88395_I2SCFG1_REG,
~AW88395_I2STXEN_MASK, AW88395_I2STXEN_DISABLE_VALUE);
}
if (ret)
dev_dbg(aw_dev->dev, "%s failed", __func__);
}
static int aw_dev_dsp_set_crc32(struct aw_device *aw_dev)
{
struct aw_sec_data_desc *crc_dsp_cfg = &aw_dev->crc_dsp_cfg;
u32 crc_value, crc_data_len;
/* get crc data len */
crc_data_len = (AW88395_DSP_REG_CRC_ADDR - AW88395_DSP_CFG_ADDR) * 2;
if (crc_data_len > crc_dsp_cfg->len) {
dev_err(aw_dev->dev, "crc data len :%d > cfg_data len:%d",
crc_data_len, crc_dsp_cfg->len);
return -EINVAL;
}
if (crc_data_len & 0x11) {
dev_err(aw_dev->dev, "The crc data len :%d unsupport", crc_data_len);
return -EINVAL;
}
crc_value = __crc32c_le(0xFFFFFFFF, crc_dsp_cfg->data, crc_data_len) ^ 0xFFFFFFFF;
return aw_dev_dsp_write(aw_dev, AW88395_DSP_REG_CRC_ADDR, crc_value,
AW88395_DSP_32_DATA);
}
static void aw_dev_dsp_check_crc_enable(struct aw_device *aw_dev, bool flag)
{
int ret;
if (flag) {
ret = regmap_update_bits(aw_dev->regmap, AW88395_HAGCCFG7_REG,
~AW88395_AGC_DSP_CTL_MASK, AW88395_AGC_DSP_CTL_ENABLE_VALUE);
} else {
ret = regmap_update_bits(aw_dev->regmap, AW88395_HAGCCFG7_REG,
~AW88395_AGC_DSP_CTL_MASK, AW88395_AGC_DSP_CTL_DISABLE_VALUE);
}
if (ret)
dev_dbg(aw_dev->dev, "%s failed", __func__);
}
static int aw_dev_dsp_check_st(struct aw_device *aw_dev)
{
unsigned int reg_val;
int ret;
int i;
for (i = 0; i < AW88395_DSP_ST_CHECK_MAX; i++) {
ret = regmap_read(aw_dev->regmap, AW88395_SYSST_REG, ®_val);
if (ret) {
dev_err(aw_dev->dev, "read reg0x%x failed", AW88395_SYSST_REG);
continue;
}
if ((reg_val & (~AW88395_DSPS_MASK)) != AW88395_DSPS_NORMAL_VALUE) {
dev_err(aw_dev->dev, "check dsp st fail,reg_val:0x%04x", reg_val);
ret = -EPERM;
continue;
} else {
dev_dbg(aw_dev->dev, "dsp st check ok, reg_val:0x%04x", reg_val);
return 0;
}
}
return ret;
}
static void aw_dev_dsp_enable(struct aw_device *aw_dev, bool is_enable)
{
int ret;
if (is_enable) {
ret = regmap_update_bits(aw_dev->regmap, AW88395_SYSCTRL_REG,
~AW88395_DSPBY_MASK, AW88395_DSPBY_WORKING_VALUE);
if (ret)
dev_dbg(aw_dev->dev, "enable dsp failed");
} else {
ret = regmap_update_bits(aw_dev->regmap, AW88395_SYSCTRL_REG,
~AW88395_DSPBY_MASK, AW88395_DSPBY_BYPASS_VALUE);
if (ret)
dev_dbg(aw_dev->dev, "disable dsp failed");
}
}
static int aw_dev_dsp_check_crc32(struct aw_device *aw_dev)
{
int ret;
if (aw_dev->dsp_cfg == AW88395_DEV_DSP_BYPASS) {
dev_info(aw_dev->dev, "dsp bypass");
return 0;
}
ret = aw_dev_dsp_set_crc32(aw_dev);
if (ret) {
dev_err(aw_dev->dev, "set dsp crc32 failed");
return ret;
}
aw_dev_dsp_check_crc_enable(aw_dev, true);
/* dsp enable */
aw_dev_dsp_enable(aw_dev, true);
usleep_range(AW88395_5000_US, AW88395_5000_US + 100);
ret = aw_dev_dsp_check_st(aw_dev);
if (ret) {
dev_err(aw_dev->dev, "check crc32 fail");
} else {
aw_dev_dsp_check_crc_enable(aw_dev, false);
aw_dev->dsp_crc_st = AW88395_DSP_CRC_OK;
}
return ret;
}
static void aw_dev_pwd(struct aw_device *aw_dev, bool pwd)
{
int ret;
if (pwd) {
ret = regmap_update_bits(aw_dev->regmap, AW88395_SYSCTRL_REG,
~AW88395_PWDN_MASK, AW88395_PWDN_POWER_DOWN_VALUE);
} else {
ret = regmap_update_bits(aw_dev->regmap, AW88395_SYSCTRL_REG,
~AW88395_PWDN_MASK, AW88395_PWDN_WORKING_VALUE);
}
if (ret)
dev_dbg(aw_dev->dev, "%s failed", __func__);
}
static void aw_dev_amppd(struct aw_device *aw_dev, bool amppd)
{
int ret;
if (amppd) {
ret = regmap_update_bits(aw_dev->regmap, AW88395_SYSCTRL_REG,
~AW88395_AMPPD_MASK, AW88395_AMPPD_POWER_DOWN_VALUE);
} else {
ret = regmap_update_bits(aw_dev->regmap, AW88395_SYSCTRL_REG,
~AW88395_AMPPD_MASK, AW88395_AMPPD_WORKING_VALUE);
}
if (ret)
dev_dbg(aw_dev->dev, "%s failed", __func__);
}
void aw88395_dev_mute(struct aw_device *aw_dev, bool is_mute)
{
int ret;
if (is_mute) {
aw_dev_fade_out(aw_dev);
ret = regmap_update_bits(aw_dev->regmap, AW88395_SYSCTRL_REG,
~AW88395_HMUTE_MASK, AW88395_HMUTE_ENABLE_VALUE);
} else {
ret = regmap_update_bits(aw_dev->regmap, AW88395_SYSCTRL_REG,
~AW88395_HMUTE_MASK, AW88395_HMUTE_DISABLE_VALUE);
aw_dev_fade_in(aw_dev);
}
if (ret)
dev_dbg(aw_dev->dev, "%s failed", __func__);
}
EXPORT_SYMBOL_GPL(aw88395_dev_mute);
static int aw_dev_get_icalk(struct aw_device *aw_dev, int16_t *icalk)
{
unsigned int reg_val;
u16 reg_icalk;
int ret;
ret = regmap_read(aw_dev->regmap, AW88395_EFRM2_REG, ®_val);
if (ret)
return ret;
reg_icalk = reg_val & (~AW88395_EF_ISN_GESLP_MASK);
if (reg_icalk & (~AW88395_EF_ISN_GESLP_SIGN_MASK))
reg_icalk = reg_icalk | AW88395_EF_ISN_GESLP_SIGN_NEG;
*icalk = (int16_t)reg_icalk;
return ret;
}
static int aw_dev_get_vcalk(struct aw_device *aw_dev, int16_t *vcalk)
{
unsigned int reg_val;
u16 reg_vcalk;
int ret;
ret = regmap_read(aw_dev->regmap, AW88395_EFRH_REG, ®_val);
if (ret)
return ret;
reg_val = reg_val >> AW88395_EF_VSENSE_GAIN_SHIFT;
reg_vcalk = (u16)reg_val & (~AW88395_EF_VSN_GESLP_MASK);
if (reg_vcalk & (~AW88395_EF_VSN_GESLP_SIGN_MASK))
reg_vcalk = reg_vcalk | AW88395_EF_VSN_GESLP_SIGN_NEG;
*vcalk = (int16_t)reg_vcalk;
return ret;
}
static int aw_dev_get_vcalk_dac(struct aw_device *aw_dev, int16_t *vcalk)
{
unsigned int reg_val;
u16 reg_vcalk;
int ret;
ret = regmap_read(aw_dev->regmap, AW88395_EFRM2_REG, ®_val);
if (ret)
return ret;
reg_vcalk = reg_val >> AW88395_EF_DAC_GESLP_SHIFT;
if (reg_vcalk & AW88395_EF_DAC_GESLP_SIGN_MASK)
reg_vcalk = reg_vcalk | AW88395_EF_DAC_GESLP_SIGN_NEG;
*vcalk = (int16_t)reg_vcalk;
return ret;
}
static int aw_dev_vsense_select(struct aw_device *aw_dev, int *vsense_select)
{
unsigned int vsense_reg_val;
int ret;
ret = regmap_read(aw_dev->regmap, AW88395_I2SCFG3_REG, &vsense_reg_val);
if (ret) {
dev_err(aw_dev->dev, "read vsense_reg_val failed");
return ret;
}
dev_dbg(aw_dev->dev, "vsense_reg = 0x%x", vsense_reg_val);
if (vsense_reg_val & (~AW88395_VDSEL_MASK)) {
*vsense_select = AW88395_DEV_VDSEL_VSENSE;
dev_dbg(aw_dev->dev, "vsense outside");
} else {
*vsense_select = AW88395_DEV_VDSEL_DAC;
dev_dbg(aw_dev->dev, "vsense inside");
}
return 0;
}
static int aw_dev_set_vcalb(struct aw_device *aw_dev)
{
int16_t icalk_val, vcalk_val;
int icalk, vsense_select;
u32 vcalb_adj, reg_val;
int vcalb, vcalk;
int ret;
ret = aw_dev_dsp_read(aw_dev, AW88395_DSP_REG_VCALB, &vcalb_adj, AW88395_DSP_16_DATA);
if (ret) {
dev_err(aw_dev->dev, "read vcalb_adj failed");
return ret;
}
ret = aw_dev_vsense_select(aw_dev, &vsense_select);
if (ret)
return ret;
dev_dbg(aw_dev->dev, "vsense_select = %d", vsense_select);
ret = aw_dev_get_icalk(aw_dev, &icalk_val);
if (ret)
return ret;
icalk = AW88395_CABL_BASE_VALUE + AW88395_ICABLK_FACTOR * icalk_val;
switch (vsense_select) {
case AW88395_DEV_VDSEL_VSENSE:
ret = aw_dev_get_vcalk(aw_dev, &vcalk_val);
if (ret)
return ret;
vcalk = AW88395_CABL_BASE_VALUE + AW88395_VCABLK_FACTOR * vcalk_val;
vcalb = AW88395_VCAL_FACTOR * AW88395_VSCAL_FACTOR /
AW88395_ISCAL_FACTOR * icalk / vcalk * vcalb_adj;
dev_dbg(aw_dev->dev, "vcalk_factor=%d, vscal_factor=%d, icalk=%d, vcalk=%d",
AW88395_VCABLK_FACTOR, AW88395_VSCAL_FACTOR, icalk, vcalk);
break;
case AW88395_DEV_VDSEL_DAC:
ret = aw_dev_get_vcalk_dac(aw_dev, &vcalk_val);
if (ret)
return ret;
vcalk = AW88395_CABL_BASE_VALUE + AW88395_VCABLK_FACTOR_DAC * vcalk_val;
vcalb = AW88395_VCAL_FACTOR * AW88395_VSCAL_FACTOR_DAC /
AW88395_ISCAL_FACTOR * icalk / vcalk * vcalb_adj;
dev_dbg(aw_dev->dev, "vcalk_dac_factor=%d, vscal_dac_factor=%d, icalk=%d, vcalk=%d",
AW88395_VCABLK_FACTOR_DAC,
AW88395_VSCAL_FACTOR_DAC, icalk, vcalk);
break;
default:
dev_err(aw_dev->dev, "unsupport vsense status");
return -EINVAL;
}
if ((vcalk == 0) || (AW88395_ISCAL_FACTOR == 0)) {
dev_err(aw_dev->dev, "vcalk:%d or desc->iscal_factor:%d unsupported",
vcalk, AW88395_ISCAL_FACTOR);
return -EINVAL;
}
vcalb = vcalb >> AW88395_VCALB_ADJ_FACTOR;
reg_val = (u32)vcalb;
dev_dbg(aw_dev->dev, "vcalb=%d, reg_val=0x%x, vcalb_adj =0x%x",
vcalb, reg_val, vcalb_adj);
ret = aw_dev_dsp_write(aw_dev, AW88395_DSP_REG_VCALB, reg_val, AW88395_DSP_16_DATA);
if (ret) {
dev_err(aw_dev->dev, "write vcalb failed");
return ret;
}
ret = aw_dev_modify_dsp_cfg(aw_dev, AW88395_DSP_REG_VCALB,
(u32)reg_val, AW88395_DSP_16_DATA);
if (ret)
dev_err(aw_dev->dev, "modify dsp cfg failed");
return ret;
}
static int aw_dev_get_cali_f0_delay(struct aw_device *aw_dev)
{
struct aw_cali_delay_desc *desc = &aw_dev->cali_delay_desc;
u32 cali_delay;
int ret;
ret = aw_dev_dsp_read(aw_dev,
AW88395_DSP_CALI_F0_DELAY, &cali_delay, AW88395_DSP_16_DATA);
if (ret)
dev_err(aw_dev->dev, "read cali delay failed, ret=%d", ret);
else
desc->delay = AW88395_CALI_DELAY_CACL(cali_delay);
dev_dbg(aw_dev->dev, "read cali delay: %d ms", desc->delay);
return ret;
}
static void aw_dev_get_int_status(struct aw_device *aw_dev, unsigned short *int_status)
{
unsigned int reg_val;
int ret;
ret = regmap_read(aw_dev->regmap, AW88395_SYSINT_REG, ®_val);
if (ret)
dev_err(aw_dev->dev, "read interrupt reg fail, ret=%d", ret);
else
*int_status = reg_val;
dev_dbg(aw_dev->dev, "read interrupt reg = 0x%04x", *int_status);
}
static void aw_dev_clear_int_status(struct aw_device *aw_dev)
{
u16 int_status;
/* read int status and clear */
aw_dev_get_int_status(aw_dev, &int_status);
/* make sure int status is clear */
aw_dev_get_int_status(aw_dev, &int_status);
if (int_status)
dev_info(aw_dev->dev, "int status(%d) is not cleaned.\n", int_status);
}
static int aw_dev_get_iis_status(struct aw_device *aw_dev)
{
unsigned int reg_val;
int ret;
ret = regmap_read(aw_dev->regmap, AW88395_SYSST_REG, ®_val);
if (ret)
return -EIO;
if ((reg_val & AW88395_BIT_PLL_CHECK) != AW88395_BIT_PLL_CHECK) {
dev_err(aw_dev->dev, "check pll lock fail,reg_val:0x%04x", reg_val);
return -EINVAL;
}
return 0;
}
static int aw_dev_check_mode1_pll(struct aw_device *aw_dev)
{
int ret, i;
for (i = 0; i < AW88395_DEV_SYSST_CHECK_MAX; i++) {
ret = aw_dev_get_iis_status(aw_dev);
if (ret < 0) {
dev_err(aw_dev->dev, "mode1 iis signal check error");
usleep_range(AW88395_2000_US, AW88395_2000_US + 10);
} else {
return 0;
}
}
return -EPERM;
}
static int aw_dev_check_mode2_pll(struct aw_device *aw_dev)
{
unsigned int reg_val;
int ret, i;
ret = regmap_read(aw_dev->regmap, AW88395_PLLCTRL1_REG, ®_val);
if (ret)
return ret;
reg_val &= (~AW88395_CCO_MUX_MASK);
if (reg_val == AW88395_CCO_MUX_DIVIDED_VALUE) {
dev_dbg(aw_dev->dev, "CCO_MUX is already divider");
return -EPERM;
}
/* change mode2 */
ret = regmap_update_bits(aw_dev->regmap, AW88395_PLLCTRL1_REG,
~AW88395_CCO_MUX_MASK, AW88395_CCO_MUX_DIVIDED_VALUE);
if (ret)
return ret;
for (i = 0; i < AW88395_DEV_SYSST_CHECK_MAX; i++) {
ret = aw_dev_get_iis_status(aw_dev);
if (ret) {
dev_err(aw_dev->dev, "mode2 iis signal check error");
usleep_range(AW88395_2000_US, AW88395_2000_US + 10);
} else {
break;
}
}
/* change mode1 */
ret = regmap_update_bits(aw_dev->regmap, AW88395_PLLCTRL1_REG,
~AW88395_CCO_MUX_MASK, AW88395_CCO_MUX_BYPASS_VALUE);
if (ret == 0) {
usleep_range(AW88395_2000_US, AW88395_2000_US + 10);
for (i = 0; i < AW88395_DEV_SYSST_CHECK_MAX; i++) {
ret = aw_dev_check_mode1_pll(aw_dev);
if (ret < 0) {
dev_err(aw_dev->dev, "mode2 switch to mode1, iis signal check error");
usleep_range(AW88395_2000_US, AW88395_2000_US + 10);
} else {
break;
}
}
}
return ret;
}
static int aw_dev_check_syspll(struct aw_device *aw_dev)
{
int ret;
ret = aw_dev_check_mode1_pll(aw_dev);
if (ret) {
dev_dbg(aw_dev->dev, "mode1 check iis failed try switch to mode2 check");
ret = aw_dev_check_mode2_pll(aw_dev);
if (ret) {
dev_err(aw_dev->dev, "mode2 check iis failed");
return ret;
}
}
return ret;
}
static int aw_dev_check_sysst(struct aw_device *aw_dev)
{
unsigned int check_val;
unsigned int reg_val;
int ret, i;
for (i = 0; i < AW88395_DEV_SYSST_CHECK_MAX; i++) {
ret = regmap_read(aw_dev->regmap, AW88395_SYSST_REG, ®_val);
if (ret)
return ret;
check_val = reg_val & (~AW88395_BIT_SYSST_CHECK_MASK)
& AW88395_BIT_SYSST_CHECK;
if (check_val != AW88395_BIT_SYSST_CHECK) {
dev_err(aw_dev->dev, "check sysst fail, cnt=%d, reg_val=0x%04x, check:0x%x",
i, reg_val, AW88395_BIT_SYSST_CHECK);
usleep_range(AW88395_2000_US, AW88395_2000_US + 10);
} else {
return 0;
}
}
return -EPERM;
}
static int aw_dev_check_sysint(struct aw_device *aw_dev)
{
u16 reg_val;
aw_dev_get_int_status(aw_dev, ®_val);
if (reg_val & AW88395_BIT_SYSINT_CHECK) {
dev_err(aw_dev->dev, "pa stop check fail:0x%04x", reg_val);
return -EINVAL;
}
return 0;
}
static void aw_dev_get_cur_mode_st(struct aw_device *aw_dev)
{
struct aw_profctrl_desc *profctrl_desc = &aw_dev->profctrl_desc;
unsigned int reg_val;
int ret;
ret = regmap_read(aw_dev->regmap, AW88395_SYSCTRL_REG, ®_val);
if (ret) {
dev_dbg(aw_dev->dev, "%s failed", __func__);
return;
}
if ((reg_val & (~AW88395_RCV_MODE_MASK)) == AW88395_RCV_MODE_RECEIVER_VALUE)
profctrl_desc->cur_mode = AW88395_RCV_MODE;
else
profctrl_desc->cur_mode = AW88395_NOT_RCV_MODE;
}
static void aw_dev_get_dsp_config(struct aw_device *aw_dev, unsigned char *dsp_cfg)
{
unsigned int reg_val = 0;
int ret;
ret = regmap_read(aw_dev->regmap, AW88395_SYSCTRL_REG, ®_val);
if (ret) {
dev_dbg(aw_dev->dev, "%s failed", __func__);
return;
}
if (reg_val & (~AW88395_DSPBY_MASK))
*dsp_cfg = AW88395_DEV_DSP_BYPASS;
else
*dsp_cfg = AW88395_DEV_DSP_WORK;
}
static void aw_dev_select_memclk(struct aw_device *aw_dev, unsigned char flag)
{
int ret;
switch (flag) {
case AW88395_DEV_MEMCLK_PLL:
ret = regmap_update_bits(aw_dev->regmap, AW88395_DBGCTRL_REG,
~AW88395_MEM_CLKSEL_MASK,
AW88395_MEM_CLKSEL_DAP_HCLK_VALUE);
if (ret)
dev_err(aw_dev->dev, "memclk select pll failed");
break;
case AW88395_DEV_MEMCLK_OSC:
ret = regmap_update_bits(aw_dev->regmap, AW88395_DBGCTRL_REG,
~AW88395_MEM_CLKSEL_MASK,
AW88395_MEM_CLKSEL_OSC_CLK_VALUE);
if (ret)
dev_err(aw_dev->dev, "memclk select OSC failed");
break;
default:
dev_err(aw_dev->dev, "unknown memclk config, flag=0x%x", flag);
break;
}
}
static int aw_dev_get_dsp_status(struct aw_device *aw_dev)
{
unsigned int reg_val;
int ret;
ret = regmap_read(aw_dev->regmap, AW88395_WDT_REG, ®_val);
if (ret)
return ret;
if (!(reg_val & (~AW88395_WDT_CNT_MASK)))
ret = -EPERM;
return ret;
}
static int aw_dev_get_vmax(struct aw_device *aw_dev, unsigned int *vmax)
{
return aw_dev_dsp_read(aw_dev, AW88395_DSP_REG_VMAX, vmax, AW88395_DSP_16_DATA);
}
static int aw_dev_update_reg_container(struct aw_device *aw_dev,
unsigned char *data, unsigned int len)
{
struct aw_volume_desc *vol_desc = &aw_dev->volume_desc;
unsigned int read_val;
int16_t *reg_data;
int data_len;
u16 read_vol;
u16 reg_val;
u8 reg_addr;
int i, ret;
reg_data = (int16_t *)data;
data_len = len >> 1;
if (data_len & 0x1) {
dev_err(aw_dev->dev, "data len:%d unsupported", data_len);
return -EINVAL;
}
for (i = 0; i < data_len; i += 2) {
reg_addr = reg_data[i];
reg_val = reg_data[i + 1];
if (reg_addr == AW88395_SYSCTRL_REG) {
ret = regmap_read(aw_dev->regmap, reg_addr, &read_val);
if (ret)
break;
read_val &= (~AW88395_HMUTE_MASK);
reg_val &= AW88395_HMUTE_MASK;
reg_val |= read_val;
}
if (reg_addr == AW88395_HAGCCFG7_REG)
reg_val &= AW88395_AGC_DSP_CTL_MASK;
if (reg_addr == AW88395_I2SCFG1_REG) {
/* close tx */
reg_val &= AW88395_I2STXEN_MASK;
reg_val |= AW88395_I2STXEN_DISABLE_VALUE;
}
if (reg_addr == AW88395_SYSCTRL2_REG) {
read_vol = (reg_val & (~AW88395_VOL_MASK)) >>
AW88395_VOL_START_BIT;
aw_dev->volume_desc.init_volume =
reg_val_to_db(read_vol);
}
ret = regmap_write(aw_dev->regmap, reg_addr, reg_val);
if (ret)
break;
}
aw_dev_get_cur_mode_st(aw_dev);
if (aw_dev->prof_cur != aw_dev->prof_index) {
/* clear control volume when PA change profile */
vol_desc->ctl_volume = 0;
} else {
/* keep control volume when PA start with sync mode */
aw_dev_set_volume(aw_dev, vol_desc->ctl_volume);
}
/* keep min volume */
if (aw_dev->fade_en)
aw_dev_set_volume(aw_dev, AW88395_MUTE_VOL);
aw_dev_get_dsp_config(aw_dev, &aw_dev->dsp_cfg);
return ret;
}
static int aw_dev_reg_update(struct aw_device *aw_dev,
unsigned char *data, unsigned int len)
{
int ret;
if (!len || !data) {
dev_err(aw_dev->dev, "reg data is null or len is 0");
return -EINVAL;
}
ret = aw_dev_update_reg_container(aw_dev, data, len);
if (ret) {
dev_err(aw_dev->dev, "reg update failed");
return ret;
}
return 0;
}
static int aw_dev_get_ra(struct aw_cali_desc *cali_desc)
{
struct aw_device *aw_dev =
container_of(cali_desc, struct aw_device, cali_desc);
u32 dsp_ra;
int ret;
ret = aw_dev_dsp_read(aw_dev, AW88395_DSP_REG_CFG_ADPZ_RA,
&dsp_ra, AW88395_DSP_32_DATA);
if (ret) {
dev_err(aw_dev->dev, "read ra error");
return ret;
}
cali_desc->ra = AW88395_DSP_RE_TO_SHOW_RE(dsp_ra,
AW88395_DSP_RE_SHIFT);
return ret;
}
static int aw_dev_dsp_update_container(struct aw_device *aw_dev,
unsigned char *data, unsigned int len, unsigned short base)
{
int i, ret;
#ifdef AW88395_DSP_I2C_WRITES
u32 tmp_len;
mutex_lock(&aw_dev->dsp_lock);
ret = regmap_write(aw_dev->regmap, AW88395_DSPMADD_REG, base);
if (ret)
goto error_operation;
for (i = 0; i < len; i += AW88395_MAX_RAM_WRITE_BYTE_SIZE) {
if ((len - i) < AW88395_MAX_RAM_WRITE_BYTE_SIZE)
tmp_len = len - i;
else
tmp_len = AW88395_MAX_RAM_WRITE_BYTE_SIZE;
ret = regmap_raw_write(aw_dev->regmap, AW88395_DSPMDAT_REG,
&data[i], tmp_len);
if (ret)
goto error_operation;
}
mutex_unlock(&aw_dev->dsp_lock);
#else
__be16 reg_val;
mutex_lock(&aw_dev->dsp_lock);
/* i2c write */
ret = regmap_write(aw_dev->regmap, AW88395_DSPMADD_REG, base);
if (ret)
goto error_operation;
for (i = 0; i < len; i += 2) {
reg_val = cpu_to_be16p((u16 *)(data + i));
ret = regmap_write(aw_dev->regmap, AW88395_DSPMDAT_REG,
(u16)reg_val);
if (ret)
goto error_operation;
}
mutex_unlock(&aw_dev->dsp_lock);
#endif
return 0;
error_operation:
mutex_unlock(&aw_dev->dsp_lock);
return ret;
}
static int aw_dev_dsp_update_fw(struct aw_device *aw_dev,
unsigned char *data, unsigned int len)
{
dev_dbg(aw_dev->dev, "dsp firmware len:%d", len);
if (!len || !data) {
dev_err(aw_dev->dev, "dsp firmware data is null or len is 0");
return -EINVAL;
}
aw_dev_dsp_update_container(aw_dev, data, len, AW88395_DSP_FW_ADDR);
aw_dev->dsp_fw_len = len;
return 0;
}
static int aw_dev_copy_to_crc_dsp_cfg(struct aw_device *aw_dev,
unsigned char *data, unsigned int size)
{
struct aw_sec_data_desc *crc_dsp_cfg = &aw_dev->crc_dsp_cfg;
if (!crc_dsp_cfg->data) {
crc_dsp_cfg->data = devm_kzalloc(aw_dev->dev, size, GFP_KERNEL);
if (!crc_dsp_cfg->data)
return -ENOMEM;
crc_dsp_cfg->len = size;
} else if (crc_dsp_cfg->len < size) {
devm_kfree(aw_dev->dev, crc_dsp_cfg->data);
crc_dsp_cfg->data = devm_kzalloc(aw_dev->dev, size, GFP_KERNEL);
if (!crc_dsp_cfg->data)
return -ENOMEM;
crc_dsp_cfg->len = size;
}
memcpy(crc_dsp_cfg->data, data, size);
swab16_array((u16 *)crc_dsp_cfg->data, size >> 1);
return 0;
}
static int aw_dev_dsp_update_cfg(struct aw_device *aw_dev,
unsigned char *data, unsigned int len)
{
int ret;
dev_dbg(aw_dev->dev, "dsp config len:%d", len);
if (!len || !data) {
dev_err(aw_dev->dev, "dsp config data is null or len is 0");
return -EINVAL;
}
aw_dev_dsp_update_container(aw_dev, data, len, AW88395_DSP_CFG_ADDR);
aw_dev->dsp_cfg_len = len;
ret = aw_dev_copy_to_crc_dsp_cfg(aw_dev, data, len);
if (ret)
return ret;
ret = aw_dev_set_vcalb(aw_dev);
if (ret)
return ret;
ret = aw_dev_get_ra(&aw_dev->cali_desc);
if (ret)
return ret;
ret = aw_dev_get_cali_f0_delay(aw_dev);
if (ret)
return ret;
ret = aw_dev_get_vmax(aw_dev, &aw_dev->vmax_desc.init_vmax);
if (ret) {
dev_err(aw_dev->dev, "get vmax failed");
return ret;
}
dev_dbg(aw_dev->dev, "get init vmax:0x%x", aw_dev->vmax_desc.init_vmax);
aw_dev->dsp_crc_st = AW88395_DSP_CRC_NA;
return 0;
}
static int aw_dev_check_sram(struct aw_device *aw_dev)
{
unsigned int reg_val;
mutex_lock(&aw_dev->dsp_lock);
/* check the odd bits of reg 0x40 */
regmap_write(aw_dev->regmap, AW88395_DSPMADD_REG, AW88395_DSP_ODD_NUM_BIT_TEST);
regmap_read(aw_dev->regmap, AW88395_DSPMADD_REG, ®_val);
if (reg_val != AW88395_DSP_ODD_NUM_BIT_TEST) {
dev_err(aw_dev->dev, "check reg 0x40 odd bit failed, read[0x%x] != write[0x%x]",
reg_val, AW88395_DSP_ODD_NUM_BIT_TEST);
goto error;
}
/* check the even bits of reg 0x40 */
regmap_write(aw_dev->regmap, AW88395_DSPMADD_REG, AW88395_DSP_EVEN_NUM_BIT_TEST);
regmap_read(aw_dev->regmap, AW88395_DSPMADD_REG, ®_val);
if (reg_val != AW88395_DSP_EVEN_NUM_BIT_TEST) {
dev_err(aw_dev->dev, "check reg 0x40 even bit failed, read[0x%x] != write[0x%x]",
reg_val, AW88395_DSP_EVEN_NUM_BIT_TEST);
goto error;
}
/* check dsp_fw_base_addr */
aw_dev_dsp_write_16bit(aw_dev, AW88395_DSP_FW_ADDR, AW88395_DSP_EVEN_NUM_BIT_TEST);
aw_dev_dsp_read_16bit(aw_dev, AW88395_DSP_FW_ADDR, ®_val);
if (reg_val != AW88395_DSP_EVEN_NUM_BIT_TEST) {
dev_err(aw_dev->dev, "check dsp fw addr failed, read[0x%x] != write[0x%x]",
reg_val, AW88395_DSP_EVEN_NUM_BIT_TEST);
goto error;
}
/* check dsp_cfg_base_addr */
aw_dev_dsp_write_16bit(aw_dev, AW88395_DSP_CFG_ADDR, AW88395_DSP_ODD_NUM_BIT_TEST);
aw_dev_dsp_read_16bit(aw_dev, AW88395_DSP_CFG_ADDR, ®_val);
if (reg_val != AW88395_DSP_ODD_NUM_BIT_TEST) {
dev_err(aw_dev->dev, "check dsp cfg failed, read[0x%x] != write[0x%x]",
reg_val, AW88395_DSP_ODD_NUM_BIT_TEST);
goto error;
}
mutex_unlock(&aw_dev->dsp_lock);
return 0;
error:
mutex_unlock(&aw_dev->dsp_lock);
return -EPERM;
}
int aw88395_dev_fw_update(struct aw_device *aw_dev, bool up_dsp_fw_en, bool force_up_en)
{
struct aw_prof_desc *prof_index_desc;
struct aw_sec_data_desc *sec_desc;
char *prof_name;
int ret;
if ((aw_dev->prof_cur == aw_dev->prof_index) &&
(force_up_en == AW88395_FORCE_UPDATE_OFF)) {
dev_dbg(aw_dev->dev, "scene no change, not update");
return 0;
}
if (aw_dev->fw_status == AW88395_DEV_FW_FAILED) {
dev_err(aw_dev->dev, "fw status[%d] error", aw_dev->fw_status);
return -EPERM;
}
prof_name = aw88395_dev_get_prof_name(aw_dev, aw_dev->prof_index);
dev_dbg(aw_dev->dev, "start update %s", prof_name);
ret = aw88395_dev_get_prof_data(aw_dev, aw_dev->prof_index, &prof_index_desc);
if (ret)
return ret;
/* update reg */
sec_desc = prof_index_desc->sec_desc;
ret = aw_dev_reg_update(aw_dev, sec_desc[AW88395_DATA_TYPE_REG].data,
sec_desc[AW88395_DATA_TYPE_REG].len);
if (ret) {
dev_err(aw_dev->dev, "update reg failed");
return ret;
}
aw88395_dev_mute(aw_dev, true);
if (aw_dev->dsp_cfg == AW88395_DEV_DSP_WORK)
aw_dev_dsp_enable(aw_dev, false);
aw_dev_select_memclk(aw_dev, AW88395_DEV_MEMCLK_OSC);
if (up_dsp_fw_en) {
ret = aw_dev_check_sram(aw_dev);
if (ret) {
dev_err(aw_dev->dev, "check sram failed");
goto error;
}
/* update dsp firmware */
dev_dbg(aw_dev->dev, "fw_ver: [%x]", prof_index_desc->fw_ver);
ret = aw_dev_dsp_update_fw(aw_dev, sec_desc[AW88395_DATA_TYPE_DSP_FW].data,
sec_desc[AW88395_DATA_TYPE_DSP_FW].len);
if (ret) {
dev_err(aw_dev->dev, "update dsp fw failed");
goto error;
}
}
/* update dsp config */
ret = aw_dev_dsp_update_cfg(aw_dev, sec_desc[AW88395_DATA_TYPE_DSP_CFG].data,
sec_desc[AW88395_DATA_TYPE_DSP_CFG].len);
if (ret) {
dev_err(aw_dev->dev, "update dsp cfg failed");
goto error;
}
aw_dev_select_memclk(aw_dev, AW88395_DEV_MEMCLK_PLL);
aw_dev->prof_cur = aw_dev->prof_index;
return 0;
error:
aw_dev_select_memclk(aw_dev, AW88395_DEV_MEMCLK_PLL);
return ret;
}
EXPORT_SYMBOL_GPL(aw88395_dev_fw_update);
static int aw_dev_dsp_check(struct aw_device *aw_dev)
{
int ret, i;
switch (aw_dev->dsp_cfg) {
case AW88395_DEV_DSP_BYPASS:
dev_dbg(aw_dev->dev, "dsp bypass");
ret = 0;
break;
case AW88395_DEV_DSP_WORK:
aw_dev_dsp_enable(aw_dev, false);
aw_dev_dsp_enable(aw_dev, true);
usleep_range(AW88395_1000_US, AW88395_1000_US + 10);
for (i = 0; i < AW88395_DEV_DSP_CHECK_MAX; i++) {
ret = aw_dev_get_dsp_status(aw_dev);
if (ret) {
dev_err(aw_dev->dev, "dsp wdt status error=%d", ret);
usleep_range(AW88395_2000_US, AW88395_2000_US + 10);
}
}
break;
default:
dev_err(aw_dev->dev, "unknown dsp cfg=%d", aw_dev->dsp_cfg);
ret = -EINVAL;
break;
}
return ret;
}
static void aw_dev_update_cali_re(struct aw_cali_desc *cali_desc)
{
struct aw_device *aw_dev =
container_of(cali_desc, struct aw_device, cali_desc);
int ret;
if ((aw_dev->cali_desc.cali_re < AW88395_CALI_RE_MAX) &&
(aw_dev->cali_desc.cali_re > AW88395_CALI_RE_MIN)) {
ret = aw_dev_dsp_set_cali_re(aw_dev);
if (ret)
dev_err(aw_dev->dev, "set cali re failed");
}
}
int aw88395_dev_start(struct aw_device *aw_dev)
{
int ret;
if (aw_dev->status == AW88395_DEV_PW_ON) {
dev_info(aw_dev->dev, "already power on");
return 0;
}
/* power on */
aw_dev_pwd(aw_dev, false);
usleep_range(AW88395_2000_US, AW88395_2000_US + 10);
ret = aw_dev_check_syspll(aw_dev);
if (ret) {
dev_err(aw_dev->dev, "pll check failed cannot start");
goto pll_check_fail;
}
/* amppd on */
aw_dev_amppd(aw_dev, false);
usleep_range(AW88395_1000_US, AW88395_1000_US + 50);
/* check i2s status */
ret = aw_dev_check_sysst(aw_dev);
if (ret) {
dev_err(aw_dev->dev, "sysst check failed");
goto sysst_check_fail;
}
if (aw_dev->dsp_cfg == AW88395_DEV_DSP_WORK) {
/* dsp bypass */
aw_dev_dsp_enable(aw_dev, false);
ret = aw_dev_dsp_fw_check(aw_dev);
if (ret)
goto dev_dsp_fw_check_fail;
aw_dev_update_cali_re(&aw_dev->cali_desc);
if (aw_dev->dsp_crc_st != AW88395_DSP_CRC_OK) {
ret = aw_dev_dsp_check_crc32(aw_dev);
if (ret) {
dev_err(aw_dev->dev, "dsp crc check failed");
goto crc_check_fail;
}
}
ret = aw_dev_dsp_check(aw_dev);
if (ret) {
dev_err(aw_dev->dev, "dsp status check failed");
goto dsp_check_fail;
}
} else {
dev_dbg(aw_dev->dev, "start pa with dsp bypass");
}
/* enable tx feedback */
aw_dev_i2s_tx_enable(aw_dev, true);
/* close mute */
aw88395_dev_mute(aw_dev, false);
/* clear inturrupt */
aw_dev_clear_int_status(aw_dev);
aw_dev->status = AW88395_DEV_PW_ON;
return 0;
dsp_check_fail:
crc_check_fail:
aw_dev_dsp_enable(aw_dev, false);
dev_dsp_fw_check_fail:
sysst_check_fail:
aw_dev_clear_int_status(aw_dev);
aw_dev_amppd(aw_dev, true);
pll_check_fail:
aw_dev_pwd(aw_dev, true);
aw_dev->status = AW88395_DEV_PW_OFF;
return ret;
}
EXPORT_SYMBOL_GPL(aw88395_dev_start);
int aw88395_dev_stop(struct aw_device *aw_dev)
{
struct aw_sec_data_desc *dsp_cfg =
&aw_dev->prof_info.prof_desc[aw_dev->prof_cur].sec_desc[AW88395_DATA_TYPE_DSP_CFG];
struct aw_sec_data_desc *dsp_fw =
&aw_dev->prof_info.prof_desc[aw_dev->prof_cur].sec_desc[AW88395_DATA_TYPE_DSP_FW];
int int_st = 0;
int ret;
if (aw_dev->status == AW88395_DEV_PW_OFF) {
dev_info(aw_dev->dev, "already power off");
return 0;
}
aw_dev->status = AW88395_DEV_PW_OFF;
/* set mute */
aw88395_dev_mute(aw_dev, true);
usleep_range(AW88395_4000_US, AW88395_4000_US + 100);
/* close tx feedback */
aw_dev_i2s_tx_enable(aw_dev, false);
usleep_range(AW88395_1000_US, AW88395_1000_US + 100);
/* check sysint state */
int_st = aw_dev_check_sysint(aw_dev);
/* close dsp */
aw_dev_dsp_enable(aw_dev, false);
/* enable amppd */
aw_dev_amppd(aw_dev, true);
if (int_st < 0) {
/* system status anomaly */
aw_dev_select_memclk(aw_dev, AW88395_DEV_MEMCLK_OSC);
ret = aw_dev_dsp_update_fw(aw_dev, dsp_fw->data, dsp_fw->len);
if (ret)
dev_err(aw_dev->dev, "update dsp fw failed");
ret = aw_dev_dsp_update_cfg(aw_dev, dsp_cfg->data, dsp_cfg->len);
if (ret)
dev_err(aw_dev->dev, "update dsp cfg failed");
aw_dev_select_memclk(aw_dev, AW88395_DEV_MEMCLK_PLL);
}
/* set power down */
aw_dev_pwd(aw_dev, true);
return 0;
}
EXPORT_SYMBOL_GPL(aw88395_dev_stop);
int aw88395_dev_init(struct aw_device *aw_dev, struct aw_container *aw_cfg)
{
int ret;
if ((!aw_dev) || (!aw_cfg)) {
pr_err("aw_dev is NULL or aw_cfg is NULL");
return -ENOMEM;
}
ret = aw88395_dev_cfg_load(aw_dev, aw_cfg);
if (ret) {
dev_err(aw_dev->dev, "aw_dev acf parse failed");
return -EINVAL;
}
aw_dev->fade_in_time = AW88395_1000_US / 10;
aw_dev->fade_out_time = AW88395_1000_US >> 1;
aw_dev->prof_cur = aw_dev->prof_info.prof_desc[0].id;
aw_dev->prof_index = aw_dev->prof_info.prof_desc[0].id;
ret = aw88395_dev_fw_update(aw_dev, AW88395_FORCE_UPDATE_ON, AW88395_DSP_FW_UPDATE_ON);
if (ret) {
dev_err(aw_dev->dev, "fw update failed ret = %d\n", ret);
return ret;
}
/* set mute */
aw88395_dev_mute(aw_dev, true);
usleep_range(AW88395_4000_US, AW88395_4000_US + 100);
/* close tx feedback */
aw_dev_i2s_tx_enable(aw_dev, false);
usleep_range(AW88395_1000_US, AW88395_1000_US + 100);
/* close dsp */
aw_dev_dsp_enable(aw_dev, false);
/* enable amppd */
aw_dev_amppd(aw_dev, true);
/* set power down */
aw_dev_pwd(aw_dev, true);
return 0;
}
EXPORT_SYMBOL_GPL(aw88395_dev_init);
static void aw88395_parse_channel_dt(struct aw_device *aw_dev)
{
struct device_node *np = aw_dev->dev->of_node;
u32 channel_value;
int ret;
ret = of_property_read_u32(np, "sound-channel", &channel_value);
if (ret) {
dev_dbg(aw_dev->dev,
"read sound-channel failed,use default 0");
aw_dev->channel = AW88395_DEV_DEFAULT_CH;
return;
}
dev_dbg(aw_dev->dev, "read sound-channel value is: %d",
channel_value);
aw_dev->channel = channel_value;
}
static void aw88395_parse_fade_enable_dt(struct aw_device *aw_dev)
{
struct device_node *np = aw_dev->dev->of_node;
u32 fade_en;
int ret;
ret = of_property_read_u32(np, "fade-enable", &fade_en);
if (ret) {
dev_dbg(aw_dev->dev,
"read fade-enable failed, close fade_in_out");
fade_en = AW88395_FADE_IN_OUT_DEFAULT;
}
dev_dbg(aw_dev->dev, "read fade-enable value is: %d", fade_en);
aw_dev->fade_en = fade_en;
}
static int aw_dev_init(struct aw_device *aw_dev)
{
aw_dev->chip_id = AW88395_CHIP_ID;
/* call aw device init func */
aw_dev->acf = NULL;
aw_dev->prof_info.prof_desc = NULL;
aw_dev->prof_info.count = 0;
aw_dev->prof_info.prof_type = AW88395_DEV_NONE_TYPE_ID;
aw_dev->channel = 0;
aw_dev->fw_status = AW88395_DEV_FW_FAILED;
aw_dev->fade_step = AW88395_VOLUME_STEP_DB;
aw_dev->volume_desc.ctl_volume = AW88395_VOL_DEFAULT_VALUE;
aw88395_parse_channel_dt(aw_dev);
aw88395_parse_fade_enable_dt(aw_dev);
return 0;
}
int aw88395_dev_get_profile_count(struct aw_device *aw_dev)
{
return aw_dev->prof_info.count;
}
EXPORT_SYMBOL_GPL(aw88395_dev_get_profile_count);
int aw88395_dev_get_profile_index(struct aw_device *aw_dev)
{
return aw_dev->prof_index;
}
EXPORT_SYMBOL_GPL(aw88395_dev_get_profile_index);
int aw88395_dev_set_profile_index(struct aw_device *aw_dev, int index)
{
/* check the index whether is valid */
if ((index >= aw_dev->prof_info.count) || (index < 0))
return -EINVAL;
/* check the index whether change */
if (aw_dev->prof_index == index)
return -EINVAL;
aw_dev->prof_index = index;
dev_dbg(aw_dev->dev, "set prof[%s]",
aw_dev->prof_info.prof_name_list[aw_dev->prof_info.prof_desc[index].id]);
return 0;
}
EXPORT_SYMBOL_GPL(aw88395_dev_set_profile_index);
char *aw88395_dev_get_prof_name(struct aw_device *aw_dev, int index)
{
struct aw_prof_info *prof_info = &aw_dev->prof_info;
struct aw_prof_desc *prof_desc;
if ((index >= aw_dev->prof_info.count) || (index < 0)) {
dev_err(aw_dev->dev, "index[%d] overflow count[%d]",
index, aw_dev->prof_info.count);
return NULL;
}
prof_desc = &aw_dev->prof_info.prof_desc[index];
return prof_info->prof_name_list[prof_desc->id];
}
EXPORT_SYMBOL_GPL(aw88395_dev_get_prof_name);
int aw88395_dev_get_prof_data(struct aw_device *aw_dev, int index,
struct aw_prof_desc **prof_desc)
{
if ((index >= aw_dev->prof_info.count) || (index < 0)) {
dev_err(aw_dev->dev, "%s: index[%d] overflow count[%d]\n",
__func__, index, aw_dev->prof_info.count);
return -EINVAL;
}
*prof_desc = &aw_dev->prof_info.prof_desc[index];
return 0;
}
EXPORT_SYMBOL_GPL(aw88395_dev_get_prof_data);
int aw88395_init(struct aw_device **aw_dev, struct i2c_client *i2c, struct regmap *regmap)
{
u16 chip_id;
int ret;
if (*aw_dev) {
dev_info(&i2c->dev, "it should be initialized here.\n");
} else {
*aw_dev = devm_kzalloc(&i2c->dev, sizeof(struct aw_device), GFP_KERNEL);
if (!(*aw_dev))
return -ENOMEM;
}
(*aw_dev)->i2c = i2c;
(*aw_dev)->dev = &i2c->dev;
(*aw_dev)->regmap = regmap;
mutex_init(&(*aw_dev)->dsp_lock);
/* read chip id */
ret = aw_dev_read_chipid((*aw_dev), &chip_id);
if (ret) {
dev_err(&i2c->dev, "dev_read_chipid failed ret=%d", ret);
return ret;
}
switch (chip_id) {
case AW88395_CHIP_ID:
ret = aw_dev_init((*aw_dev));
break;
default:
ret = -EINVAL;
dev_err((*aw_dev)->dev, "unsupported device");
break;
}
return ret;
}
EXPORT_SYMBOL_GPL(aw88395_init);
MODULE_DESCRIPTION("AW88395 device lib");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/aw88395/aw88395_device.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// aw88395_lib.c -- ACF bin parsing and check library file for aw88395
//
// Copyright (c) 2022-2023 AWINIC Technology CO., LTD
//
// Author: Bruce zhao <[email protected]>
//
#include <linux/crc8.h>
#include <linux/i2c.h>
#include "aw88395_lib.h"
#include "aw88395_device.h"
#include "aw88395_reg.h"
#define AW88395_CRC8_POLYNOMIAL 0x8C
DECLARE_CRC8_TABLE(aw_crc8_table);
static char *profile_name[AW88395_PROFILE_MAX] = {
"Music", "Voice", "Voip", "Ringtone",
"Ringtone_hs", "Lowpower", "Bypass",
"Mmi", "Fm", "Notification", "Receiver"
};
static int aw_parse_bin_header(struct aw_device *aw_dev, struct aw_bin *bin);
static int aw_check_sum(struct aw_device *aw_dev, struct aw_bin *bin, int bin_num)
{
unsigned char *p_check_sum;
unsigned int sum_data = 0;
unsigned int check_sum;
unsigned int i, len;
p_check_sum = &(bin->info.data[(bin->header_info[bin_num].valid_data_addr -
bin->header_info[bin_num].header_len)]);
len = bin->header_info[bin_num].bin_data_len + bin->header_info[bin_num].header_len;
check_sum = le32_to_cpup((void *)p_check_sum);
for (i = 4; i < len; i++)
sum_data += *(p_check_sum + i);
dev_dbg(aw_dev->dev, "%s -- check_sum = %p, check_sum = 0x%x, sum_data = 0x%x",
__func__, p_check_sum, check_sum, sum_data);
if (sum_data != check_sum) {
dev_err(aw_dev->dev, "%s. CheckSum Fail.bin_num=%d, CheckSum:0x%x, SumData:0x%x",
__func__, bin_num, check_sum, sum_data);
return -EINVAL;
}
return 0;
}
static int aw_check_data_version(struct aw_device *aw_dev, struct aw_bin *bin, int bin_num)
{
if (bin->header_info[bin_num].bin_data_ver < DATA_VERSION_V1 ||
bin->header_info[bin_num].bin_data_ver > DATA_VERSION_MAX) {
dev_err(aw_dev->dev, "aw_bin_parse Unrecognized this bin data version\n");
return -EINVAL;
}
return 0;
}
static int aw_check_register_num(struct aw_device *aw_dev, struct aw_bin *bin, int bin_num)
{
struct bin_header_info temp_info = bin->header_info[bin_num];
unsigned int check_register_num, parse_register_num;
unsigned char *p_check_sum;
p_check_sum = &(bin->info.data[(temp_info.valid_data_addr)]);
parse_register_num = le32_to_cpup((void *)p_check_sum);
check_register_num = (bin->header_info[bin_num].bin_data_len - CHECK_REGISTER_NUM_OFFSET) /
(bin->header_info[bin_num].reg_byte_len +
bin->header_info[bin_num].data_byte_len);
dev_dbg(aw_dev->dev, "%s,parse_register_num = 0x%x,check_register_num = 0x%x\n",
__func__, parse_register_num, check_register_num);
if (parse_register_num != check_register_num) {
dev_err(aw_dev->dev, "%s parse_register_num = 0x%x,check_register_num = 0x%x\n",
__func__, parse_register_num, check_register_num);
return -EINVAL;
}
bin->header_info[bin_num].reg_num = parse_register_num;
bin->header_info[bin_num].valid_data_len = temp_info.bin_data_len - VALID_DATA_LEN;
bin->header_info[bin_num].valid_data_addr = temp_info.valid_data_addr + VALID_DATA_ADDR;
return 0;
}
static int aw_check_dsp_reg_num(struct aw_device *aw_dev, struct aw_bin *bin, int bin_num)
{
struct bin_header_info temp_info = bin->header_info[bin_num];
unsigned int check_dsp_reg_num, parse_dsp_reg_num;
unsigned char *p_check_sum;
p_check_sum = &(bin->info.data[(temp_info.valid_data_addr)]);
parse_dsp_reg_num = le32_to_cpup((void *)(p_check_sum + PARSE_DSP_REG_NUM));
bin->header_info[bin_num].reg_data_byte_len =
le32_to_cpup((void *)(p_check_sum + REG_DATA_BYTP_LEN));
check_dsp_reg_num = (bin->header_info[bin_num].bin_data_len - CHECK_DSP_REG_NUM) /
bin->header_info[bin_num].reg_data_byte_len;
dev_dbg(aw_dev->dev, "%s bin_num = %d, parse_dsp_reg_num = 0x%x, check_dsp_reg_num = 0x%x",
__func__, bin_num, check_dsp_reg_num, check_dsp_reg_num);
if (parse_dsp_reg_num != check_dsp_reg_num) {
dev_err(aw_dev->dev, "aw_bin_parse check dsp reg num error\n");
dev_err(aw_dev->dev, "%s parse_dsp_reg_num = 0x%x, check_dsp_reg_num = 0x%x",
__func__, check_dsp_reg_num, check_dsp_reg_num);
return -EINVAL;
}
bin->header_info[bin_num].download_addr = le32_to_cpup((void *)p_check_sum);
bin->header_info[bin_num].reg_num = parse_dsp_reg_num;
bin->header_info[bin_num].valid_data_len = temp_info.bin_data_len - DSP_VALID_DATA_LEN;
bin->header_info[bin_num].valid_data_addr = temp_info.valid_data_addr +
DSP_VALID_DATA_ADDR;
return 0;
}
static int aw_check_soc_app_num(struct aw_device *aw_dev, struct aw_bin *bin, int bin_num)
{
struct bin_header_info temp_info = bin->header_info[bin_num];
unsigned int check_soc_app_num, parse_soc_app_num;
unsigned char *p_check_sum;
p_check_sum = &(bin->info.data[(temp_info.valid_data_addr)]);
bin->header_info[bin_num].app_version = le32_to_cpup((void *)p_check_sum);
parse_soc_app_num = le32_to_cpup((void *)(p_check_sum + PARSE_SOC_APP_NUM));
check_soc_app_num = bin->header_info[bin_num].bin_data_len - CHECK_SOC_APP_NUM;
dev_dbg(aw_dev->dev, "%s bin_num = %d, parse_soc_app_num=0x%x, check_soc_app_num = 0x%x\n",
__func__, bin_num, parse_soc_app_num, check_soc_app_num);
if (parse_soc_app_num != check_soc_app_num) {
dev_err(aw_dev->dev, "%s parse_soc_app_num=0x%x, check_soc_app_num = 0x%x\n",
__func__, parse_soc_app_num, check_soc_app_num);
return -EINVAL;
}
bin->header_info[bin_num].reg_num = parse_soc_app_num;
bin->header_info[bin_num].download_addr = le32_to_cpup((void *)(p_check_sum +
APP_DOWNLOAD_ADDR));
bin->header_info[bin_num].valid_data_len = temp_info.bin_data_len - APP_VALID_DATA_LEN;
bin->header_info[bin_num].valid_data_addr = temp_info.valid_data_addr +
APP_VALID_DATA_ADDR;
return 0;
}
static void aw_get_single_bin_header(struct aw_bin *bin)
{
memcpy((void *)&bin->header_info[bin->all_bin_parse_num], bin->p_addr, DATA_LEN);
bin->header_info[bin->all_bin_parse_num].header_len = HEADER_LEN;
bin->all_bin_parse_num += 1;
}
static int aw_parse_one_of_multi_bins(struct aw_device *aw_dev, unsigned int bin_num,
int bin_serial_num, struct aw_bin *bin)
{
struct bin_header_info aw_bin_header_info;
unsigned int bin_start_addr;
unsigned int valid_data_len;
if (bin->info.len < sizeof(struct bin_header_info)) {
dev_err(aw_dev->dev, "bin_header_info size[%d] overflow file size[%d]\n",
(int)sizeof(struct bin_header_info), bin->info.len);
return -EINVAL;
}
aw_bin_header_info = bin->header_info[bin->all_bin_parse_num - 1];
if (!bin_serial_num) {
bin_start_addr = le32_to_cpup((void *)(bin->p_addr + START_ADDR_OFFSET));
bin->p_addr += (HEADER_LEN + bin_start_addr);
bin->header_info[bin->all_bin_parse_num].valid_data_addr =
aw_bin_header_info.valid_data_addr + VALID_DATA_ADDR + 8 * bin_num +
VALID_DATA_ADDR_OFFSET;
} else {
valid_data_len = aw_bin_header_info.bin_data_len;
bin->p_addr += (HDADER_LEN + valid_data_len);
bin->header_info[bin->all_bin_parse_num].valid_data_addr =
aw_bin_header_info.valid_data_addr + aw_bin_header_info.bin_data_len +
VALID_DATA_ADDR_OFFSET;
}
return aw_parse_bin_header(aw_dev, bin);
}
static int aw_get_multi_bin_header(struct aw_device *aw_dev, struct aw_bin *bin)
{
unsigned int bin_num, i;
int ret;
bin_num = le32_to_cpup((void *)(bin->p_addr + VALID_DATA_ADDR_OFFSET));
if (bin->multi_bin_parse_num == 1)
bin->header_info[bin->all_bin_parse_num].valid_data_addr =
VALID_DATA_ADDR_OFFSET;
aw_get_single_bin_header(bin);
for (i = 0; i < bin_num; i++) {
dev_dbg(aw_dev->dev, "aw_bin_parse enter multi bin for is %d\n", i);
ret = aw_parse_one_of_multi_bins(aw_dev, bin_num, i, bin);
if (ret < 0)
return ret;
}
return 0;
}
static int aw_parse_bin_header(struct aw_device *aw_dev, struct aw_bin *bin)
{
unsigned int bin_data_type;
if (bin->info.len < sizeof(struct bin_header_info)) {
dev_err(aw_dev->dev, "bin_header_info size[%d] overflow file size[%d]\n",
(int)sizeof(struct bin_header_info), bin->info.len);
return -EINVAL;
}
bin_data_type = le32_to_cpup((void *)(bin->p_addr + BIN_DATA_TYPE_OFFSET));
dev_dbg(aw_dev->dev, "aw_bin_parse bin_data_type 0x%x\n", bin_data_type);
switch (bin_data_type) {
case DATA_TYPE_REGISTER:
case DATA_TYPE_DSP_REG:
case DATA_TYPE_SOC_APP:
bin->single_bin_parse_num += 1;
dev_dbg(aw_dev->dev, "%s bin->single_bin_parse_num is %d\n", __func__,
bin->single_bin_parse_num);
if (!bin->multi_bin_parse_num)
bin->header_info[bin->all_bin_parse_num].valid_data_addr =
VALID_DATA_ADDR_OFFSET;
aw_get_single_bin_header(bin);
return 0;
case DATA_TYPE_MULTI_BINS:
bin->multi_bin_parse_num += 1;
dev_dbg(aw_dev->dev, "%s bin->multi_bin_parse_num is %d\n", __func__,
bin->multi_bin_parse_num);
return aw_get_multi_bin_header(aw_dev, bin);
default:
dev_dbg(aw_dev->dev, "%s There is no corresponding type\n", __func__);
return 0;
}
}
static int aw_check_bin_header_version(struct aw_device *aw_dev, struct aw_bin *bin)
{
unsigned int header_version;
header_version = le32_to_cpup((void *)(bin->p_addr + HEADER_VERSION_OFFSET));
dev_dbg(aw_dev->dev, "aw_bin_parse header_version 0x%x\n", header_version);
switch (header_version) {
case HEADER_VERSION_V1:
return aw_parse_bin_header(aw_dev, bin);
default:
dev_err(aw_dev->dev, "aw_bin_parse Unrecognized this bin header version\n");
return -EINVAL;
}
}
static int aw_parsing_bin_file(struct aw_device *aw_dev, struct aw_bin *bin)
{
int ret = -EINVAL;
int i;
if (!bin) {
dev_err(aw_dev->dev, "aw_bin_parse bin is NULL\n");
return ret;
}
bin->p_addr = bin->info.data;
bin->all_bin_parse_num = 0;
bin->multi_bin_parse_num = 0;
bin->single_bin_parse_num = 0;
ret = aw_check_bin_header_version(aw_dev, bin);
if (ret < 0) {
dev_err(aw_dev->dev, "aw_bin_parse check bin header version error\n");
return ret;
}
for (i = 0; i < bin->all_bin_parse_num; i++) {
ret = aw_check_sum(aw_dev, bin, i);
if (ret < 0) {
dev_err(aw_dev->dev, "aw_bin_parse check sum data error\n");
return ret;
}
ret = aw_check_data_version(aw_dev, bin, i);
if (ret < 0) {
dev_err(aw_dev->dev, "aw_bin_parse check data version error\n");
return ret;
}
if (bin->header_info[i].bin_data_ver == DATA_VERSION_V1) {
switch (bin->header_info[i].bin_data_type) {
case DATA_TYPE_REGISTER:
ret = aw_check_register_num(aw_dev, bin, i);
break;
case DATA_TYPE_DSP_REG:
ret = aw_check_dsp_reg_num(aw_dev, bin, i);
break;
case DATA_TYPE_SOC_APP:
ret = aw_check_soc_app_num(aw_dev, bin, i);
break;
default:
bin->header_info[i].valid_data_len =
bin->header_info[i].bin_data_len;
ret = 0;
break;
}
if (ret < 0)
return ret;
}
}
return 0;
}
static int aw_dev_parse_raw_reg(unsigned char *data, unsigned int data_len,
struct aw_prof_desc *prof_desc)
{
prof_desc->sec_desc[AW88395_DATA_TYPE_REG].data = data;
prof_desc->sec_desc[AW88395_DATA_TYPE_REG].len = data_len;
prof_desc->prof_st = AW88395_PROFILE_OK;
return 0;
}
static int aw_dev_parse_raw_dsp_cfg(unsigned char *data, unsigned int data_len,
struct aw_prof_desc *prof_desc)
{
if (data_len & 0x01)
return -EINVAL;
swab16_array((u16 *)data, data_len >> 1);
prof_desc->sec_desc[AW88395_DATA_TYPE_DSP_CFG].data = data;
prof_desc->sec_desc[AW88395_DATA_TYPE_DSP_CFG].len = data_len;
prof_desc->prof_st = AW88395_PROFILE_OK;
return 0;
}
static int aw_dev_parse_raw_dsp_fw(unsigned char *data, unsigned int data_len,
struct aw_prof_desc *prof_desc)
{
if (data_len & 0x01)
return -EINVAL;
swab16_array((u16 *)data, data_len >> 1);
prof_desc->sec_desc[AW88395_DATA_TYPE_DSP_FW].data = data;
prof_desc->sec_desc[AW88395_DATA_TYPE_DSP_FW].len = data_len;
prof_desc->prof_st = AW88395_PROFILE_OK;
return 0;
}
static int aw_dev_prof_parse_multi_bin(struct aw_device *aw_dev, unsigned char *data,
unsigned int data_len, struct aw_prof_desc *prof_desc)
{
struct aw_bin *aw_bin;
int ret;
int i;
aw_bin = devm_kzalloc(aw_dev->dev, data_len + sizeof(struct aw_bin), GFP_KERNEL);
if (!aw_bin)
return -ENOMEM;
aw_bin->info.len = data_len;
memcpy(aw_bin->info.data, data, data_len);
ret = aw_parsing_bin_file(aw_dev, aw_bin);
if (ret < 0) {
dev_err(aw_dev->dev, "parse bin failed");
goto parse_bin_failed;
}
for (i = 0; i < aw_bin->all_bin_parse_num; i++) {
switch (aw_bin->header_info[i].bin_data_type) {
case DATA_TYPE_REGISTER:
prof_desc->sec_desc[AW88395_DATA_TYPE_REG].len =
aw_bin->header_info[i].valid_data_len;
prof_desc->sec_desc[AW88395_DATA_TYPE_REG].data =
data + aw_bin->header_info[i].valid_data_addr;
break;
case DATA_TYPE_DSP_REG:
if (aw_bin->header_info[i].valid_data_len & 0x01) {
ret = -EINVAL;
goto parse_bin_failed;
}
swab16_array((u16 *)(data + aw_bin->header_info[i].valid_data_addr),
aw_bin->header_info[i].valid_data_len >> 1);
prof_desc->sec_desc[AW88395_DATA_TYPE_DSP_CFG].len =
aw_bin->header_info[i].valid_data_len;
prof_desc->sec_desc[AW88395_DATA_TYPE_DSP_CFG].data =
data + aw_bin->header_info[i].valid_data_addr;
break;
case DATA_TYPE_DSP_FW:
case DATA_TYPE_SOC_APP:
if (aw_bin->header_info[i].valid_data_len & 0x01) {
ret = -EINVAL;
goto parse_bin_failed;
}
swab16_array((u16 *)(data + aw_bin->header_info[i].valid_data_addr),
aw_bin->header_info[i].valid_data_len >> 1);
prof_desc->fw_ver = aw_bin->header_info[i].app_version;
prof_desc->sec_desc[AW88395_DATA_TYPE_DSP_FW].len =
aw_bin->header_info[i].valid_data_len;
prof_desc->sec_desc[AW88395_DATA_TYPE_DSP_FW].data =
data + aw_bin->header_info[i].valid_data_addr;
break;
default:
dev_dbg(aw_dev->dev, "bin_data_type not found");
break;
}
}
prof_desc->prof_st = AW88395_PROFILE_OK;
ret = 0;
parse_bin_failed:
devm_kfree(aw_dev->dev, aw_bin);
return ret;
}
static int aw_dev_parse_reg_bin_with_hdr(struct aw_device *aw_dev,
uint8_t *data, uint32_t data_len, struct aw_prof_desc *prof_desc)
{
struct aw_bin *aw_bin;
int ret;
aw_bin = devm_kzalloc(aw_dev->dev, data_len + sizeof(*aw_bin), GFP_KERNEL);
if (!aw_bin)
return -ENOMEM;
aw_bin->info.len = data_len;
memcpy(aw_bin->info.data, data, data_len);
ret = aw_parsing_bin_file(aw_dev, aw_bin);
if (ret < 0) {
dev_err(aw_dev->dev, "parse bin failed");
goto parse_bin_failed;
}
if ((aw_bin->all_bin_parse_num != 1) ||
(aw_bin->header_info[0].bin_data_type != DATA_TYPE_REGISTER)) {
dev_err(aw_dev->dev, "bin num or type error");
ret = -EINVAL;
goto parse_bin_failed;
}
if (aw_bin->header_info[0].valid_data_len % 4) {
dev_err(aw_dev->dev, "bin data len get error!");
ret = -EINVAL;
goto parse_bin_failed;
}
prof_desc->sec_desc[AW88395_DATA_TYPE_REG].data =
data + aw_bin->header_info[0].valid_data_addr;
prof_desc->sec_desc[AW88395_DATA_TYPE_REG].len =
aw_bin->header_info[0].valid_data_len;
prof_desc->prof_st = AW88395_PROFILE_OK;
devm_kfree(aw_dev->dev, aw_bin);
aw_bin = NULL;
return 0;
parse_bin_failed:
devm_kfree(aw_dev->dev, aw_bin);
aw_bin = NULL;
return ret;
}
static int aw_dev_parse_data_by_sec_type(struct aw_device *aw_dev, struct aw_cfg_hdr *cfg_hdr,
struct aw_cfg_dde *cfg_dde, struct aw_prof_desc *scene_prof_desc)
{
switch (cfg_dde->data_type) {
case ACF_SEC_TYPE_REG:
return aw_dev_parse_raw_reg((u8 *)cfg_hdr + cfg_dde->data_offset,
cfg_dde->data_size, scene_prof_desc);
case ACF_SEC_TYPE_DSP_CFG:
return aw_dev_parse_raw_dsp_cfg((u8 *)cfg_hdr + cfg_dde->data_offset,
cfg_dde->data_size, scene_prof_desc);
case ACF_SEC_TYPE_DSP_FW:
return aw_dev_parse_raw_dsp_fw(
(u8 *)cfg_hdr + cfg_dde->data_offset,
cfg_dde->data_size, scene_prof_desc);
case ACF_SEC_TYPE_MULTIPLE_BIN:
return aw_dev_prof_parse_multi_bin(
aw_dev, (u8 *)cfg_hdr + cfg_dde->data_offset,
cfg_dde->data_size, scene_prof_desc);
case ACF_SEC_TYPE_HDR_REG:
return aw_dev_parse_reg_bin_with_hdr(aw_dev, (u8 *)cfg_hdr + cfg_dde->data_offset,
cfg_dde->data_size, scene_prof_desc);
default:
dev_err(aw_dev->dev, "%s cfg_dde->data_type = %d\n", __func__, cfg_dde->data_type);
break;
}
return 0;
}
static int aw_dev_parse_dev_type(struct aw_device *aw_dev,
struct aw_cfg_hdr *prof_hdr, struct aw_all_prof_info *all_prof_info)
{
struct aw_cfg_dde *cfg_dde =
(struct aw_cfg_dde *)((char *)prof_hdr + prof_hdr->hdr_offset);
int sec_num = 0;
int ret, i;
for (i = 0; i < prof_hdr->ddt_num; i++) {
if ((aw_dev->i2c->adapter->nr == cfg_dde[i].dev_bus) &&
(aw_dev->i2c->addr == cfg_dde[i].dev_addr) &&
(cfg_dde[i].type == AW88395_DEV_TYPE_ID) &&
(cfg_dde[i].data_type != ACF_SEC_TYPE_MONITOR)) {
if (cfg_dde[i].dev_profile >= AW88395_PROFILE_MAX) {
dev_err(aw_dev->dev, "dev_profile [%d] overflow",
cfg_dde[i].dev_profile);
return -EINVAL;
}
ret = aw_dev_parse_data_by_sec_type(aw_dev, prof_hdr, &cfg_dde[i],
&all_prof_info->prof_desc[cfg_dde[i].dev_profile]);
if (ret < 0) {
dev_err(aw_dev->dev, "parse failed");
return ret;
}
sec_num++;
}
}
if (sec_num == 0) {
dev_dbg(aw_dev->dev, "get dev type num is %d, please use default", sec_num);
return AW88395_DEV_TYPE_NONE;
}
return AW88395_DEV_TYPE_OK;
}
static int aw_dev_parse_dev_default_type(struct aw_device *aw_dev,
struct aw_cfg_hdr *prof_hdr, struct aw_all_prof_info *all_prof_info)
{
struct aw_cfg_dde *cfg_dde =
(struct aw_cfg_dde *)((char *)prof_hdr + prof_hdr->hdr_offset);
int sec_num = 0;
int ret, i;
for (i = 0; i < prof_hdr->ddt_num; i++) {
if ((aw_dev->channel == cfg_dde[i].dev_index) &&
(cfg_dde[i].type == AW88395_DEV_DEFAULT_TYPE_ID) &&
(cfg_dde[i].data_type != ACF_SEC_TYPE_MONITOR)) {
if (cfg_dde[i].dev_profile >= AW88395_PROFILE_MAX) {
dev_err(aw_dev->dev, "dev_profile [%d] overflow",
cfg_dde[i].dev_profile);
return -EINVAL;
}
ret = aw_dev_parse_data_by_sec_type(aw_dev, prof_hdr, &cfg_dde[i],
&all_prof_info->prof_desc[cfg_dde[i].dev_profile]);
if (ret < 0) {
dev_err(aw_dev->dev, "parse failed");
return ret;
}
sec_num++;
}
}
if (sec_num == 0) {
dev_err(aw_dev->dev, "get dev default type failed, get num[%d]", sec_num);
return -EINVAL;
}
return 0;
}
static int aw88261_dev_cfg_get_valid_prof(struct aw_device *aw_dev,
struct aw_all_prof_info all_prof_info)
{
struct aw_prof_desc *prof_desc = all_prof_info.prof_desc;
struct aw_prof_info *prof_info = &aw_dev->prof_info;
int num = 0;
int i;
for (i = 0; i < AW88395_PROFILE_MAX; i++) {
if (prof_desc[i].prof_st == AW88395_PROFILE_OK)
prof_info->count++;
}
dev_dbg(aw_dev->dev, "get valid profile:%d", aw_dev->prof_info.count);
if (!prof_info->count) {
dev_err(aw_dev->dev, "no profile data");
return -EPERM;
}
prof_info->prof_desc = devm_kcalloc(aw_dev->dev,
prof_info->count, sizeof(struct aw_prof_desc),
GFP_KERNEL);
if (!prof_info->prof_desc)
return -ENOMEM;
for (i = 0; i < AW88395_PROFILE_MAX; i++) {
if (prof_desc[i].prof_st == AW88395_PROFILE_OK) {
if (num >= prof_info->count) {
dev_err(aw_dev->dev, "overflow count[%d]",
prof_info->count);
return -EINVAL;
}
prof_info->prof_desc[num] = prof_desc[i];
prof_info->prof_desc[num].id = i;
num++;
}
}
return 0;
}
static int aw88395_dev_cfg_get_valid_prof(struct aw_device *aw_dev,
struct aw_all_prof_info all_prof_info)
{
struct aw_prof_desc *prof_desc = all_prof_info.prof_desc;
struct aw_prof_info *prof_info = &aw_dev->prof_info;
struct aw_sec_data_desc *sec_desc;
int num = 0;
int i;
for (i = 0; i < AW88395_PROFILE_MAX; i++) {
if (prof_desc[i].prof_st == AW88395_PROFILE_OK) {
sec_desc = prof_desc[i].sec_desc;
if ((sec_desc[AW88395_DATA_TYPE_REG].data != NULL) &&
(sec_desc[AW88395_DATA_TYPE_REG].len != 0) &&
(sec_desc[AW88395_DATA_TYPE_DSP_CFG].data != NULL) &&
(sec_desc[AW88395_DATA_TYPE_DSP_CFG].len != 0) &&
(sec_desc[AW88395_DATA_TYPE_DSP_FW].data != NULL) &&
(sec_desc[AW88395_DATA_TYPE_DSP_FW].len != 0))
prof_info->count++;
}
}
dev_dbg(aw_dev->dev, "get valid profile:%d", aw_dev->prof_info.count);
if (!prof_info->count) {
dev_err(aw_dev->dev, "no profile data");
return -EPERM;
}
prof_info->prof_desc = devm_kcalloc(aw_dev->dev,
prof_info->count, sizeof(struct aw_prof_desc),
GFP_KERNEL);
if (!prof_info->prof_desc)
return -ENOMEM;
for (i = 0; i < AW88395_PROFILE_MAX; i++) {
if (prof_desc[i].prof_st == AW88395_PROFILE_OK) {
sec_desc = prof_desc[i].sec_desc;
if ((sec_desc[AW88395_DATA_TYPE_REG].data != NULL) &&
(sec_desc[AW88395_DATA_TYPE_REG].len != 0) &&
(sec_desc[AW88395_DATA_TYPE_DSP_CFG].data != NULL) &&
(sec_desc[AW88395_DATA_TYPE_DSP_CFG].len != 0) &&
(sec_desc[AW88395_DATA_TYPE_DSP_FW].data != NULL) &&
(sec_desc[AW88395_DATA_TYPE_DSP_FW].len != 0)) {
if (num >= prof_info->count) {
dev_err(aw_dev->dev, "overflow count[%d]",
prof_info->count);
return -EINVAL;
}
prof_info->prof_desc[num] = prof_desc[i];
prof_info->prof_desc[num].id = i;
num++;
}
}
}
return 0;
}
static int aw_dev_load_cfg_by_hdr(struct aw_device *aw_dev,
struct aw_cfg_hdr *prof_hdr)
{
struct aw_all_prof_info *all_prof_info;
int ret;
all_prof_info = devm_kzalloc(aw_dev->dev, sizeof(struct aw_all_prof_info), GFP_KERNEL);
if (!all_prof_info)
return -ENOMEM;
ret = aw_dev_parse_dev_type(aw_dev, prof_hdr, all_prof_info);
if (ret < 0) {
goto exit;
} else if (ret == AW88395_DEV_TYPE_NONE) {
dev_dbg(aw_dev->dev, "get dev type num is 0, parse default dev");
ret = aw_dev_parse_dev_default_type(aw_dev, prof_hdr, all_prof_info);
if (ret < 0)
goto exit;
}
switch (aw_dev->chip_id) {
case AW88395_CHIP_ID:
ret = aw88395_dev_cfg_get_valid_prof(aw_dev, *all_prof_info);
if (ret < 0)
goto exit;
break;
case AW88261_CHIP_ID:
ret = aw88261_dev_cfg_get_valid_prof(aw_dev, *all_prof_info);
if (ret < 0)
goto exit;
break;
default:
dev_err(aw_dev->dev, "valid prof unsupported");
ret = -EINVAL;
break;
}
aw_dev->prof_info.prof_name_list = profile_name;
exit:
devm_kfree(aw_dev->dev, all_prof_info);
return ret;
}
static int aw_dev_create_prof_name_list_v1(struct aw_device *aw_dev)
{
struct aw_prof_info *prof_info = &aw_dev->prof_info;
struct aw_prof_desc *prof_desc = prof_info->prof_desc;
int i;
if (!prof_desc) {
dev_err(aw_dev->dev, "prof_desc is NULL");
return -EINVAL;
}
prof_info->prof_name_list = devm_kzalloc(aw_dev->dev,
prof_info->count * PROFILE_STR_MAX,
GFP_KERNEL);
if (!prof_info->prof_name_list)
return -ENOMEM;
for (i = 0; i < prof_info->count; i++) {
prof_desc[i].id = i;
prof_info->prof_name_list[i] = prof_desc[i].prf_str;
dev_dbg(aw_dev->dev, "prof name is %s", prof_info->prof_name_list[i]);
}
return 0;
}
static int aw_get_dde_type_info(struct aw_device *aw_dev, struct aw_container *aw_cfg)
{
struct aw_cfg_hdr *cfg_hdr = (struct aw_cfg_hdr *)aw_cfg->data;
struct aw_cfg_dde_v1 *cfg_dde =
(struct aw_cfg_dde_v1 *)(aw_cfg->data + cfg_hdr->hdr_offset);
int default_num = 0;
int dev_num = 0;
unsigned int i;
for (i = 0; i < cfg_hdr->ddt_num; i++) {
if (cfg_dde[i].type == AW88395_DEV_TYPE_ID)
dev_num++;
if (cfg_dde[i].type == AW88395_DEV_DEFAULT_TYPE_ID)
default_num++;
}
if (dev_num != 0) {
aw_dev->prof_info.prof_type = AW88395_DEV_TYPE_ID;
} else if (default_num != 0) {
aw_dev->prof_info.prof_type = AW88395_DEV_DEFAULT_TYPE_ID;
} else {
dev_err(aw_dev->dev, "can't find scene");
return -EINVAL;
}
return 0;
}
static int aw_get_dev_scene_count_v1(struct aw_device *aw_dev, struct aw_container *aw_cfg,
unsigned int *scene_num)
{
struct aw_cfg_hdr *cfg_hdr = (struct aw_cfg_hdr *)aw_cfg->data;
struct aw_cfg_dde_v1 *cfg_dde =
(struct aw_cfg_dde_v1 *)(aw_cfg->data + cfg_hdr->hdr_offset);
unsigned int i;
int ret;
switch (aw_dev->chip_id) {
case AW88395_CHIP_ID:
for (i = 0; i < cfg_hdr->ddt_num; ++i) {
if ((cfg_dde[i].data_type == ACF_SEC_TYPE_MULTIPLE_BIN) &&
(aw_dev->chip_id == cfg_dde[i].chip_id) &&
(aw_dev->i2c->adapter->nr == cfg_dde[i].dev_bus) &&
(aw_dev->i2c->addr == cfg_dde[i].dev_addr))
(*scene_num)++;
}
ret = 0;
break;
case AW88261_CHIP_ID:
for (i = 0; i < cfg_hdr->ddt_num; ++i) {
if (((cfg_dde[i].data_type == ACF_SEC_TYPE_REG) ||
(cfg_dde[i].data_type == ACF_SEC_TYPE_HDR_REG)) &&
(aw_dev->chip_id == cfg_dde[i].chip_id) &&
(aw_dev->i2c->adapter->nr == cfg_dde[i].dev_bus) &&
(aw_dev->i2c->addr == cfg_dde[i].dev_addr))
(*scene_num)++;
}
ret = 0;
break;
default:
dev_err(aw_dev->dev, "unsupported device");
ret = -EINVAL;
break;
}
return ret;
}
static int aw_get_default_scene_count_v1(struct aw_device *aw_dev,
struct aw_container *aw_cfg,
unsigned int *scene_num)
{
struct aw_cfg_hdr *cfg_hdr = (struct aw_cfg_hdr *)aw_cfg->data;
struct aw_cfg_dde_v1 *cfg_dde =
(struct aw_cfg_dde_v1 *)(aw_cfg->data + cfg_hdr->hdr_offset);
unsigned int i;
int ret;
switch (aw_dev->chip_id) {
case AW88395_CHIP_ID:
for (i = 0; i < cfg_hdr->ddt_num; ++i) {
if ((cfg_dde[i].data_type == ACF_SEC_TYPE_MULTIPLE_BIN) &&
(aw_dev->chip_id == cfg_dde[i].chip_id) &&
(aw_dev->channel == cfg_dde[i].dev_index))
(*scene_num)++;
}
ret = 0;
break;
case AW88261_CHIP_ID:
for (i = 0; i < cfg_hdr->ddt_num; ++i) {
if (((cfg_dde[i].data_type == ACF_SEC_TYPE_REG) ||
(cfg_dde[i].data_type == ACF_SEC_TYPE_HDR_REG)) &&
(aw_dev->chip_id == cfg_dde[i].chip_id) &&
(aw_dev->channel == cfg_dde[i].dev_index))
(*scene_num)++;
}
ret = 0;
break;
default:
dev_err(aw_dev->dev, "unsupported device");
ret = -EINVAL;
break;
}
return ret;
}
static int aw_dev_parse_scene_count_v1(struct aw_device *aw_dev,
struct aw_container *aw_cfg,
unsigned int *count)
{
int ret;
ret = aw_get_dde_type_info(aw_dev, aw_cfg);
if (ret < 0)
return ret;
switch (aw_dev->prof_info.prof_type) {
case AW88395_DEV_TYPE_ID:
ret = aw_get_dev_scene_count_v1(aw_dev, aw_cfg, count);
break;
case AW88395_DEV_DEFAULT_TYPE_ID:
ret = aw_get_default_scene_count_v1(aw_dev, aw_cfg, count);
break;
default:
dev_err(aw_dev->dev, "unsupported prof_type[%x]", aw_dev->prof_info.prof_type);
ret = -EINVAL;
break;
}
return ret;
}
static int aw_dev_parse_data_by_sec_type_v1(struct aw_device *aw_dev,
struct aw_cfg_hdr *prof_hdr,
struct aw_cfg_dde_v1 *cfg_dde,
int *cur_scene_id)
{
struct aw_prof_info *prof_info = &aw_dev->prof_info;
int ret;
switch (cfg_dde->data_type) {
case ACF_SEC_TYPE_MULTIPLE_BIN:
ret = aw_dev_prof_parse_multi_bin(aw_dev, (u8 *)prof_hdr + cfg_dde->data_offset,
cfg_dde->data_size, &prof_info->prof_desc[*cur_scene_id]);
if (ret < 0) {
dev_err(aw_dev->dev, "parse multi bin failed");
return ret;
}
prof_info->prof_desc[*cur_scene_id].prf_str = cfg_dde->dev_profile_str;
prof_info->prof_desc[*cur_scene_id].id = cfg_dde->dev_profile;
(*cur_scene_id)++;
break;
case ACF_SEC_TYPE_HDR_REG:
ret = aw_dev_parse_reg_bin_with_hdr(aw_dev,
(uint8_t *)prof_hdr + cfg_dde->data_offset,
cfg_dde->data_size, &prof_info->prof_desc[*cur_scene_id]);
if (ret < 0) {
dev_err(aw_dev->dev, "parse reg bin with hdr failed");
return ret;
}
prof_info->prof_desc[*cur_scene_id].prf_str = cfg_dde->dev_profile_str;
prof_info->prof_desc[*cur_scene_id].id = cfg_dde->dev_profile;
(*cur_scene_id)++;
break;
default:
dev_err(aw_dev->dev, "unsupported SEC_TYPE [%d]", cfg_dde->data_type);
return -EINVAL;
}
return 0;
}
static int aw_dev_parse_dev_type_v1(struct aw_device *aw_dev,
struct aw_cfg_hdr *prof_hdr)
{
struct aw_cfg_dde_v1 *cfg_dde =
(struct aw_cfg_dde_v1 *)((char *)prof_hdr + prof_hdr->hdr_offset);
int cur_scene_id = 0;
unsigned int i;
int ret;
for (i = 0; i < prof_hdr->ddt_num; i++) {
if ((aw_dev->i2c->adapter->nr == cfg_dde[i].dev_bus) &&
(aw_dev->i2c->addr == cfg_dde[i].dev_addr) &&
(aw_dev->chip_id == cfg_dde[i].chip_id)) {
ret = aw_dev_parse_data_by_sec_type_v1(aw_dev, prof_hdr,
&cfg_dde[i], &cur_scene_id);
if (ret < 0) {
dev_err(aw_dev->dev, "parse failed");
return ret;
}
}
}
if (cur_scene_id == 0) {
dev_err(aw_dev->dev, "get dev type failed, get num [%d]", cur_scene_id);
return -EINVAL;
}
return 0;
}
static int aw_dev_parse_default_type_v1(struct aw_device *aw_dev,
struct aw_cfg_hdr *prof_hdr)
{
struct aw_cfg_dde_v1 *cfg_dde =
(struct aw_cfg_dde_v1 *)((char *)prof_hdr + prof_hdr->hdr_offset);
int cur_scene_id = 0;
unsigned int i;
int ret;
for (i = 0; i < prof_hdr->ddt_num; i++) {
if ((aw_dev->channel == cfg_dde[i].dev_index) &&
(aw_dev->chip_id == cfg_dde[i].chip_id)) {
ret = aw_dev_parse_data_by_sec_type_v1(aw_dev, prof_hdr,
&cfg_dde[i], &cur_scene_id);
if (ret < 0) {
dev_err(aw_dev->dev, "parse failed");
return ret;
}
}
}
if (cur_scene_id == 0) {
dev_err(aw_dev->dev, "get dev default type failed, get num[%d]", cur_scene_id);
return -EINVAL;
}
return 0;
}
static int aw_dev_parse_by_hdr_v1(struct aw_device *aw_dev,
struct aw_cfg_hdr *cfg_hdr)
{
int ret;
switch (aw_dev->prof_info.prof_type) {
case AW88395_DEV_TYPE_ID:
ret = aw_dev_parse_dev_type_v1(aw_dev, cfg_hdr);
break;
case AW88395_DEV_DEFAULT_TYPE_ID:
ret = aw_dev_parse_default_type_v1(aw_dev, cfg_hdr);
break;
default:
dev_err(aw_dev->dev, "prof type matched failed, get num[%d]",
aw_dev->prof_info.prof_type);
ret = -EINVAL;
break;
}
return ret;
}
static int aw_dev_load_cfg_by_hdr_v1(struct aw_device *aw_dev,
struct aw_container *aw_cfg)
{
struct aw_cfg_hdr *cfg_hdr = (struct aw_cfg_hdr *)aw_cfg->data;
struct aw_prof_info *prof_info = &aw_dev->prof_info;
int ret;
ret = aw_dev_parse_scene_count_v1(aw_dev, aw_cfg, &prof_info->count);
if (ret < 0) {
dev_err(aw_dev->dev, "get scene count failed");
return ret;
}
prof_info->prof_desc = devm_kcalloc(aw_dev->dev,
prof_info->count, sizeof(struct aw_prof_desc),
GFP_KERNEL);
if (!prof_info->prof_desc)
return -ENOMEM;
ret = aw_dev_parse_by_hdr_v1(aw_dev, cfg_hdr);
if (ret < 0) {
dev_err(aw_dev->dev, "parse hdr failed");
return ret;
}
ret = aw_dev_create_prof_name_list_v1(aw_dev);
if (ret < 0) {
dev_err(aw_dev->dev, "create prof name list failed");
return ret;
}
return 0;
}
int aw88395_dev_cfg_load(struct aw_device *aw_dev, struct aw_container *aw_cfg)
{
struct aw_cfg_hdr *cfg_hdr;
int ret;
cfg_hdr = (struct aw_cfg_hdr *)aw_cfg->data;
switch (cfg_hdr->hdr_version) {
case AW88395_CFG_HDR_VER:
ret = aw_dev_load_cfg_by_hdr(aw_dev, cfg_hdr);
if (ret < 0) {
dev_err(aw_dev->dev, "hdr_version[0x%x] parse failed",
cfg_hdr->hdr_version);
return ret;
}
break;
case AW88395_CFG_HDR_VER_V1:
ret = aw_dev_load_cfg_by_hdr_v1(aw_dev, aw_cfg);
if (ret < 0) {
dev_err(aw_dev->dev, "hdr_version[0x%x] parse failed",
cfg_hdr->hdr_version);
return ret;
}
break;
default:
dev_err(aw_dev->dev, "unsupported hdr_version [0x%x]", cfg_hdr->hdr_version);
return -EINVAL;
}
aw_dev->fw_status = AW88395_DEV_FW_OK;
return 0;
}
EXPORT_SYMBOL_GPL(aw88395_dev_cfg_load);
static int aw_dev_check_cfg_by_hdr(struct aw_device *aw_dev, struct aw_container *aw_cfg)
{
unsigned int end_data_offset;
struct aw_cfg_hdr *cfg_hdr;
struct aw_cfg_dde *cfg_dde;
unsigned int act_data = 0;
unsigned int hdr_ddt_len;
unsigned int i;
u8 act_crc8;
cfg_hdr = (struct aw_cfg_hdr *)aw_cfg->data;
/* check file type id is awinic acf file */
if (cfg_hdr->id != ACF_FILE_ID) {
dev_err(aw_dev->dev, "not acf type file");
return -EINVAL;
}
hdr_ddt_len = cfg_hdr->hdr_offset + cfg_hdr->ddt_size;
if (hdr_ddt_len > aw_cfg->len) {
dev_err(aw_dev->dev, "hdr_len with ddt_len [%d] overflow file size[%d]",
cfg_hdr->hdr_offset, aw_cfg->len);
return -EINVAL;
}
/* check data size */
cfg_dde = (struct aw_cfg_dde *)((char *)aw_cfg->data + cfg_hdr->hdr_offset);
act_data += hdr_ddt_len;
for (i = 0; i < cfg_hdr->ddt_num; i++)
act_data += cfg_dde[i].data_size;
if (act_data != aw_cfg->len) {
dev_err(aw_dev->dev, "act_data[%d] not equal to file size[%d]!",
act_data, aw_cfg->len);
return -EINVAL;
}
for (i = 0; i < cfg_hdr->ddt_num; i++) {
/* data check */
end_data_offset = cfg_dde[i].data_offset + cfg_dde[i].data_size;
if (end_data_offset > aw_cfg->len) {
dev_err(aw_dev->dev, "ddt_num[%d] end_data_offset[%d] overflow size[%d]",
i, end_data_offset, aw_cfg->len);
return -EINVAL;
}
/* crc check */
act_crc8 = crc8(aw_crc8_table, aw_cfg->data + cfg_dde[i].data_offset,
cfg_dde[i].data_size, 0);
if (act_crc8 != cfg_dde[i].data_crc) {
dev_err(aw_dev->dev, "ddt_num[%d] act_crc8:0x%x != data_crc:0x%x",
i, (u32)act_crc8, cfg_dde[i].data_crc);
return -EINVAL;
}
}
return 0;
}
static int aw_dev_check_acf_by_hdr_v1(struct aw_device *aw_dev, struct aw_container *aw_cfg)
{
struct aw_cfg_dde_v1 *cfg_dde;
unsigned int end_data_offset;
struct aw_cfg_hdr *cfg_hdr;
unsigned int act_data = 0;
unsigned int hdr_ddt_len;
u8 act_crc8;
int i;
cfg_hdr = (struct aw_cfg_hdr *)aw_cfg->data;
/* check file type id is awinic acf file */
if (cfg_hdr->id != ACF_FILE_ID) {
dev_err(aw_dev->dev, "not acf type file");
return -EINVAL;
}
hdr_ddt_len = cfg_hdr->hdr_offset + cfg_hdr->ddt_size;
if (hdr_ddt_len > aw_cfg->len) {
dev_err(aw_dev->dev, "hdrlen with ddt_len [%d] overflow file size[%d]",
cfg_hdr->hdr_offset, aw_cfg->len);
return -EINVAL;
}
/* check data size */
cfg_dde = (struct aw_cfg_dde_v1 *)((char *)aw_cfg->data + cfg_hdr->hdr_offset);
act_data += hdr_ddt_len;
for (i = 0; i < cfg_hdr->ddt_num; i++)
act_data += cfg_dde[i].data_size;
if (act_data != aw_cfg->len) {
dev_err(aw_dev->dev, "act_data[%d] not equal to file size[%d]!",
act_data, aw_cfg->len);
return -EINVAL;
}
for (i = 0; i < cfg_hdr->ddt_num; i++) {
/* data check */
end_data_offset = cfg_dde[i].data_offset + cfg_dde[i].data_size;
if (end_data_offset > aw_cfg->len) {
dev_err(aw_dev->dev, "ddt_num[%d] end_data_offset[%d] overflow size[%d]",
i, end_data_offset, aw_cfg->len);
return -EINVAL;
}
/* crc check */
act_crc8 = crc8(aw_crc8_table, aw_cfg->data + cfg_dde[i].data_offset,
cfg_dde[i].data_size, 0);
if (act_crc8 != cfg_dde[i].data_crc) {
dev_err(aw_dev->dev, "ddt_num[%d] act_crc8:0x%x != data_crc 0x%x",
i, (u32)act_crc8, cfg_dde[i].data_crc);
return -EINVAL;
}
}
return 0;
}
int aw88395_dev_load_acf_check(struct aw_device *aw_dev, struct aw_container *aw_cfg)
{
struct aw_cfg_hdr *cfg_hdr;
if (!aw_cfg) {
dev_err(aw_dev->dev, "aw_prof is NULL");
return -EINVAL;
}
if (aw_cfg->len < sizeof(struct aw_cfg_hdr)) {
dev_err(aw_dev->dev, "cfg hdr size[%d] overflow file size[%d]",
aw_cfg->len, (int)sizeof(struct aw_cfg_hdr));
return -EINVAL;
}
crc8_populate_lsb(aw_crc8_table, AW88395_CRC8_POLYNOMIAL);
cfg_hdr = (struct aw_cfg_hdr *)aw_cfg->data;
switch (cfg_hdr->hdr_version) {
case AW88395_CFG_HDR_VER:
return aw_dev_check_cfg_by_hdr(aw_dev, aw_cfg);
case AW88395_CFG_HDR_VER_V1:
return aw_dev_check_acf_by_hdr_v1(aw_dev, aw_cfg);
default:
dev_err(aw_dev->dev, "unsupported hdr_version [0x%x]", cfg_hdr->hdr_version);
return -EINVAL;
}
return 0;
}
EXPORT_SYMBOL_GPL(aw88395_dev_load_acf_check);
MODULE_DESCRIPTION("AW88395 ACF File Parsing Lib");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/aw88395/aw88395_lib.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// aw88395.c -- ALSA SoC AW88395 codec support
//
// Copyright (c) 2022-2023 AWINIC Technology CO., LTD
//
// Author: Bruce zhao <[email protected]>
// Author: Weidong Wang <[email protected]>
//
#include <linux/i2c.h>
#include <linux/firmware.h>
#include <linux/of_gpio.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include "aw88395.h"
#include "aw88395_device.h"
#include "aw88395_lib.h"
#include "aw88395_reg.h"
static const struct regmap_config aw88395_remap_config = {
.val_bits = 16,
.reg_bits = 8,
.max_register = AW88395_REG_MAX - 1,
.reg_format_endian = REGMAP_ENDIAN_LITTLE,
.val_format_endian = REGMAP_ENDIAN_BIG,
};
static void aw88395_start_pa(struct aw88395 *aw88395)
{
int ret, i;
for (i = 0; i < AW88395_START_RETRIES; i++) {
ret = aw88395_dev_start(aw88395->aw_pa);
if (ret) {
dev_err(aw88395->aw_pa->dev, "aw88395 device start failed. retry = %d", i);
ret = aw88395_dev_fw_update(aw88395->aw_pa, AW88395_DSP_FW_UPDATE_ON, true);
if (ret < 0) {
dev_err(aw88395->aw_pa->dev, "fw update failed");
continue;
}
} else {
dev_info(aw88395->aw_pa->dev, "start success\n");
break;
}
}
}
static void aw88395_startup_work(struct work_struct *work)
{
struct aw88395 *aw88395 =
container_of(work, struct aw88395, start_work.work);
mutex_lock(&aw88395->lock);
aw88395_start_pa(aw88395);
mutex_unlock(&aw88395->lock);
}
static void aw88395_start(struct aw88395 *aw88395, bool sync_start)
{
int ret;
if (aw88395->aw_pa->fw_status != AW88395_DEV_FW_OK)
return;
if (aw88395->aw_pa->status == AW88395_DEV_PW_ON)
return;
ret = aw88395_dev_fw_update(aw88395->aw_pa, AW88395_DSP_FW_UPDATE_OFF, true);
if (ret < 0) {
dev_err(aw88395->aw_pa->dev, "fw update failed.");
return;
}
if (sync_start == AW88395_SYNC_START)
aw88395_start_pa(aw88395);
else
queue_delayed_work(system_wq,
&aw88395->start_work,
AW88395_START_WORK_DELAY_MS);
}
static struct snd_soc_dai_driver aw88395_dai[] = {
{
.name = "aw88395-aif",
.id = 1,
.playback = {
.stream_name = "Speaker_Playback",
.channels_min = 1,
.channels_max = 2,
.rates = AW88395_RATES,
.formats = AW88395_FORMATS,
},
.capture = {
.stream_name = "Speaker_Capture",
.channels_min = 1,
.channels_max = 2,
.rates = AW88395_RATES,
.formats = AW88395_FORMATS,
},
},
};
static int aw88395_get_fade_in_time(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct aw88395 *aw88395 = snd_soc_component_get_drvdata(component);
struct aw_device *aw_dev = aw88395->aw_pa;
ucontrol->value.integer.value[0] = aw_dev->fade_in_time;
return 0;
}
static int aw88395_set_fade_in_time(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct aw88395 *aw88395 = snd_soc_component_get_drvdata(component);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
struct aw_device *aw_dev = aw88395->aw_pa;
int time;
time = ucontrol->value.integer.value[0];
if (time < mc->min || time > mc->max)
return -EINVAL;
if (time != aw_dev->fade_in_time) {
aw_dev->fade_in_time = time;
return 1;
}
return 0;
}
static int aw88395_get_fade_out_time(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct aw88395 *aw88395 = snd_soc_component_get_drvdata(component);
struct aw_device *aw_dev = aw88395->aw_pa;
ucontrol->value.integer.value[0] = aw_dev->fade_out_time;
return 0;
}
static int aw88395_set_fade_out_time(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
struct aw88395 *aw88395 = snd_soc_component_get_drvdata(component);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
struct aw_device *aw_dev = aw88395->aw_pa;
int time;
time = ucontrol->value.integer.value[0];
if (time < mc->min || time > mc->max)
return -EINVAL;
if (time != aw_dev->fade_out_time) {
aw_dev->fade_out_time = time;
return 1;
}
return 0;
}
static int aw88395_profile_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
struct aw88395 *aw88395 = snd_soc_component_get_drvdata(codec);
const char *prof_name;
char *name;
int count;
uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
uinfo->count = 1;
count = aw88395_dev_get_profile_count(aw88395->aw_pa);
if (count <= 0) {
uinfo->value.enumerated.items = 0;
return 0;
}
uinfo->value.enumerated.items = count;
if (uinfo->value.enumerated.item >= count)
uinfo->value.enumerated.item = count - 1;
name = uinfo->value.enumerated.name;
count = uinfo->value.enumerated.item;
prof_name = aw88395_dev_get_prof_name(aw88395->aw_pa, count);
if (!prof_name) {
strscpy(uinfo->value.enumerated.name, "null",
strlen("null") + 1);
return 0;
}
strscpy(name, prof_name, sizeof(uinfo->value.enumerated.name));
return 0;
}
static int aw88395_profile_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
struct aw88395 *aw88395 = snd_soc_component_get_drvdata(codec);
ucontrol->value.integer.value[0] = aw88395_dev_get_profile_index(aw88395->aw_pa);
return 0;
}
static int aw88395_profile_set(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
struct aw88395 *aw88395 = snd_soc_component_get_drvdata(codec);
int ret;
/* pa stop or stopping just set profile */
mutex_lock(&aw88395->lock);
ret = aw88395_dev_set_profile_index(aw88395->aw_pa, ucontrol->value.integer.value[0]);
if (ret < 0) {
dev_dbg(codec->dev, "profile index does not change");
mutex_unlock(&aw88395->lock);
return 0;
}
if (aw88395->aw_pa->status) {
aw88395_dev_stop(aw88395->aw_pa);
aw88395_start(aw88395, AW88395_SYNC_START);
}
mutex_unlock(&aw88395->lock);
return 1;
}
static int aw88395_volume_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
struct aw88395 *aw88395 = snd_soc_component_get_drvdata(codec);
struct aw_volume_desc *vol_desc = &aw88395->aw_pa->volume_desc;
ucontrol->value.integer.value[0] = vol_desc->ctl_volume;
return 0;
}
static int aw88395_volume_set(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
struct aw88395 *aw88395 = snd_soc_component_get_drvdata(codec);
struct aw_volume_desc *vol_desc = &aw88395->aw_pa->volume_desc;
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
int value;
value = ucontrol->value.integer.value[0];
if (value < mc->min || value > mc->max)
return -EINVAL;
if (vol_desc->ctl_volume != value) {
vol_desc->ctl_volume = value;
aw88395_dev_set_volume(aw88395->aw_pa, vol_desc->ctl_volume);
return 1;
}
return 0;
}
static int aw88395_get_fade_step(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
struct aw88395 *aw88395 = snd_soc_component_get_drvdata(codec);
ucontrol->value.integer.value[0] = aw88395->aw_pa->fade_step;
return 0;
}
static int aw88395_set_fade_step(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
struct aw88395 *aw88395 = snd_soc_component_get_drvdata(codec);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
int value;
value = ucontrol->value.integer.value[0];
if (value < mc->min || value > mc->max)
return -EINVAL;
if (aw88395->aw_pa->fade_step != value) {
aw88395->aw_pa->fade_step = value;
return 1;
}
return 0;
}
static int aw88395_re_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
struct aw88395 *aw88395 = snd_soc_component_get_drvdata(codec);
struct aw_device *aw_dev = aw88395->aw_pa;
ucontrol->value.integer.value[0] = aw_dev->cali_desc.cali_re;
return 0;
}
static int aw88395_re_set(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
struct aw88395 *aw88395 = snd_soc_component_get_drvdata(codec);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
struct aw_device *aw_dev = aw88395->aw_pa;
int value;
value = ucontrol->value.integer.value[0];
if (value < mc->min || value > mc->max)
return -EINVAL;
if (aw_dev->cali_desc.cali_re != value) {
aw_dev->cali_desc.cali_re = value;
return 1;
}
return 0;
}
static const struct snd_kcontrol_new aw88395_controls[] = {
SOC_SINGLE_EXT("PCM Playback Volume", AW88395_SYSCTRL2_REG,
6, AW88395_MUTE_VOL, 0, aw88395_volume_get,
aw88395_volume_set),
SOC_SINGLE_EXT("Fade Step", 0, 0, AW88395_MUTE_VOL, 0,
aw88395_get_fade_step, aw88395_set_fade_step),
SOC_SINGLE_EXT("Volume Ramp Up Step", 0, 0, FADE_TIME_MAX, FADE_TIME_MIN,
aw88395_get_fade_in_time, aw88395_set_fade_in_time),
SOC_SINGLE_EXT("Volume Ramp Down Step", 0, 0, FADE_TIME_MAX, FADE_TIME_MIN,
aw88395_get_fade_out_time, aw88395_set_fade_out_time),
SOC_SINGLE_EXT("Calib", 0, 0, 100, 0,
aw88395_re_get, aw88395_re_set),
AW88395_PROFILE_EXT("Profile Set", aw88395_profile_info,
aw88395_profile_get, aw88395_profile_set),
};
static int aw88395_playback_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *k, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct aw88395 *aw88395 = snd_soc_component_get_drvdata(component);
mutex_lock(&aw88395->lock);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
aw88395_start(aw88395, AW88395_ASYNC_START);
break;
case SND_SOC_DAPM_POST_PMD:
aw88395_dev_stop(aw88395->aw_pa);
break;
default:
break;
}
mutex_unlock(&aw88395->lock);
return 0;
}
static const struct snd_soc_dapm_widget aw88395_dapm_widgets[] = {
/* playback */
SND_SOC_DAPM_AIF_IN_E("AIF_RX", "Speaker_Playback", 0, 0, 0, 0,
aw88395_playback_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_OUTPUT("DAC Output"),
/* capture */
SND_SOC_DAPM_AIF_OUT("AIF_TX", "Speaker_Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_INPUT("ADC Input"),
};
static const struct snd_soc_dapm_route aw88395_audio_map[] = {
{"DAC Output", NULL, "AIF_RX"},
{"AIF_TX", NULL, "ADC Input"},
};
static int aw88395_codec_probe(struct snd_soc_component *component)
{
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
struct aw88395 *aw88395 = snd_soc_component_get_drvdata(component);
int ret;
INIT_DELAYED_WORK(&aw88395->start_work, aw88395_startup_work);
/* add widgets */
ret = snd_soc_dapm_new_controls(dapm, aw88395_dapm_widgets,
ARRAY_SIZE(aw88395_dapm_widgets));
if (ret < 0)
return ret;
/* add route */
ret = snd_soc_dapm_add_routes(dapm, aw88395_audio_map,
ARRAY_SIZE(aw88395_audio_map));
if (ret < 0)
return ret;
ret = snd_soc_add_component_controls(component, aw88395_controls,
ARRAY_SIZE(aw88395_controls));
return ret;
}
static void aw88395_codec_remove(struct snd_soc_component *aw_codec)
{
struct aw88395 *aw88395 = snd_soc_component_get_drvdata(aw_codec);
cancel_delayed_work_sync(&aw88395->start_work);
}
static const struct snd_soc_component_driver soc_codec_dev_aw88395 = {
.probe = aw88395_codec_probe,
.remove = aw88395_codec_remove,
};
static struct aw88395 *aw88395_malloc_init(struct i2c_client *i2c)
{
struct aw88395 *aw88395 = devm_kzalloc(&i2c->dev,
sizeof(struct aw88395), GFP_KERNEL);
if (!aw88395)
return NULL;
mutex_init(&aw88395->lock);
return aw88395;
}
static void aw88395_hw_reset(struct aw88395 *aw88395)
{
if (aw88395->reset_gpio) {
gpiod_set_value_cansleep(aw88395->reset_gpio, 0);
usleep_range(AW88395_1000_US, AW88395_1000_US + 10);
gpiod_set_value_cansleep(aw88395->reset_gpio, 1);
usleep_range(AW88395_1000_US, AW88395_1000_US + 10);
} else {
dev_err(aw88395->aw_pa->dev, "%s failed", __func__);
}
}
static int aw88395_request_firmware_file(struct aw88395 *aw88395)
{
const struct firmware *cont = NULL;
int ret;
aw88395->aw_pa->fw_status = AW88395_DEV_FW_FAILED;
ret = request_firmware(&cont, AW88395_ACF_FILE, aw88395->aw_pa->dev);
if ((ret < 0) || (!cont)) {
dev_err(aw88395->aw_pa->dev, "load [%s] failed!", AW88395_ACF_FILE);
return ret;
}
dev_info(aw88395->aw_pa->dev, "loaded %s - size: %zu\n",
AW88395_ACF_FILE, cont ? cont->size : 0);
aw88395->aw_cfg = devm_kzalloc(aw88395->aw_pa->dev, cont->size + sizeof(int), GFP_KERNEL);
if (!aw88395->aw_cfg) {
release_firmware(cont);
return -ENOMEM;
}
aw88395->aw_cfg->len = (int)cont->size;
memcpy(aw88395->aw_cfg->data, cont->data, cont->size);
release_firmware(cont);
ret = aw88395_dev_load_acf_check(aw88395->aw_pa, aw88395->aw_cfg);
if (ret < 0) {
dev_err(aw88395->aw_pa->dev, "Load [%s] failed ....!", AW88395_ACF_FILE);
return ret;
}
dev_dbg(aw88395->aw_pa->dev, "%s : bin load success\n", __func__);
mutex_lock(&aw88395->lock);
/* aw device init */
ret = aw88395_dev_init(aw88395->aw_pa, aw88395->aw_cfg);
if (ret < 0)
dev_err(aw88395->aw_pa->dev, "dev init failed");
mutex_unlock(&aw88395->lock);
return ret;
}
static int aw88395_i2c_probe(struct i2c_client *i2c)
{
struct aw88395 *aw88395;
int ret;
if (!i2c_check_functionality(i2c->adapter, I2C_FUNC_I2C)) {
dev_err(&i2c->dev, "check_functionality failed");
return -EIO;
}
aw88395 = aw88395_malloc_init(i2c);
if (!aw88395) {
dev_err(&i2c->dev, "malloc aw88395 failed");
return -ENOMEM;
}
i2c_set_clientdata(i2c, aw88395);
aw88395->reset_gpio = devm_gpiod_get_optional(&i2c->dev, "reset", GPIOD_OUT_LOW);
if (IS_ERR(aw88395->reset_gpio))
dev_info(&i2c->dev, "reset gpio not defined\n");
/* hardware reset */
aw88395_hw_reset(aw88395);
aw88395->regmap = devm_regmap_init_i2c(i2c, &aw88395_remap_config);
if (IS_ERR(aw88395->regmap)) {
ret = PTR_ERR(aw88395->regmap);
dev_err(&i2c->dev, "Failed to init regmap: %d\n", ret);
return ret;
}
/* aw pa init */
ret = aw88395_init(&aw88395->aw_pa, i2c, aw88395->regmap);
if (ret < 0)
return ret;
ret = aw88395_request_firmware_file(aw88395);
if (ret < 0) {
dev_err(&i2c->dev, "%s failed\n", __func__);
return ret;
}
ret = devm_snd_soc_register_component(&i2c->dev,
&soc_codec_dev_aw88395,
aw88395_dai, ARRAY_SIZE(aw88395_dai));
if (ret < 0) {
dev_err(&i2c->dev, "failed to register aw88395: %d", ret);
return ret;
}
return 0;
}
static const struct i2c_device_id aw88395_i2c_id[] = {
{ AW88395_I2C_NAME, 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, aw88395_i2c_id);
static struct i2c_driver aw88395_i2c_driver = {
.driver = {
.name = AW88395_I2C_NAME,
},
.probe = aw88395_i2c_probe,
.id_table = aw88395_i2c_id,
};
module_i2c_driver(aw88395_i2c_driver);
MODULE_DESCRIPTION("ASoC AW88395 Smart PA Driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/codecs/aw88395/aw88395.c |
// SPDX-License-Identifier: GPL-2.0
//
// Xilinx ASoC audio formatter support
//
// Copyright (C) 2018 Xilinx, Inc.
//
// Author: Maruthi Srinivas Bayyavarapu <[email protected]>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/sizes.h>
#include <sound/asoundef.h>
#include <sound/soc.h>
#include <sound/pcm_params.h>
#define DRV_NAME "xlnx_formatter_pcm"
#define XLNX_S2MM_OFFSET 0
#define XLNX_MM2S_OFFSET 0x100
#define XLNX_AUD_CORE_CONFIG 0x4
#define XLNX_AUD_CTRL 0x10
#define XLNX_AUD_STS 0x14
#define AUD_CTRL_RESET_MASK BIT(1)
#define AUD_CFG_MM2S_MASK BIT(15)
#define AUD_CFG_S2MM_MASK BIT(31)
#define XLNX_AUD_FS_MULTIPLIER 0x18
#define XLNX_AUD_PERIOD_CONFIG 0x1C
#define XLNX_AUD_BUFF_ADDR_LSB 0x20
#define XLNX_AUD_BUFF_ADDR_MSB 0x24
#define XLNX_AUD_XFER_COUNT 0x28
#define XLNX_AUD_CH_STS_START 0x2C
#define XLNX_BYTES_PER_CH 0x44
#define XLNX_AUD_ALIGN_BYTES 64
#define AUD_STS_IOC_IRQ_MASK BIT(31)
#define AUD_STS_CH_STS_MASK BIT(29)
#define AUD_CTRL_IOC_IRQ_MASK BIT(13)
#define AUD_CTRL_TOUT_IRQ_MASK BIT(14)
#define AUD_CTRL_DMA_EN_MASK BIT(0)
#define CFG_MM2S_CH_MASK GENMASK(11, 8)
#define CFG_MM2S_CH_SHIFT 8
#define CFG_MM2S_XFER_MASK GENMASK(14, 13)
#define CFG_MM2S_XFER_SHIFT 13
#define CFG_MM2S_PKG_MASK BIT(12)
#define CFG_S2MM_CH_MASK GENMASK(27, 24)
#define CFG_S2MM_CH_SHIFT 24
#define CFG_S2MM_XFER_MASK GENMASK(30, 29)
#define CFG_S2MM_XFER_SHIFT 29
#define CFG_S2MM_PKG_MASK BIT(28)
#define AUD_CTRL_DATA_WIDTH_SHIFT 16
#define AUD_CTRL_ACTIVE_CH_SHIFT 19
#define PERIOD_CFG_PERIODS_SHIFT 16
#define PERIODS_MIN 2
#define PERIODS_MAX 6
#define PERIOD_BYTES_MIN 192
#define PERIOD_BYTES_MAX (50 * 1024)
#define XLNX_PARAM_UNKNOWN 0
enum bit_depth {
BIT_DEPTH_8,
BIT_DEPTH_16,
BIT_DEPTH_20,
BIT_DEPTH_24,
BIT_DEPTH_32,
};
struct xlnx_pcm_drv_data {
void __iomem *mmio;
bool s2mm_presence;
bool mm2s_presence;
int s2mm_irq;
int mm2s_irq;
struct snd_pcm_substream *play_stream;
struct snd_pcm_substream *capture_stream;
struct clk *axi_clk;
unsigned int sysclk;
};
/*
* struct xlnx_pcm_stream_param - stream configuration
* @mmio: base address offset
* @interleaved: audio channels arrangement in buffer
* @xfer_mode: data formatting mode during transfer
* @ch_limit: Maximum channels supported
* @buffer_size: stream ring buffer size
*/
struct xlnx_pcm_stream_param {
void __iomem *mmio;
bool interleaved;
u32 xfer_mode;
u32 ch_limit;
u64 buffer_size;
};
static const struct snd_pcm_hardware xlnx_pcm_hardware = {
.info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER |
SNDRV_PCM_INFO_BATCH | SNDRV_PCM_INFO_PAUSE |
SNDRV_PCM_INFO_RESUME,
.formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_192000,
.rate_min = 8000,
.rate_max = 192000,
.buffer_bytes_max = PERIODS_MAX * PERIOD_BYTES_MAX,
.period_bytes_min = PERIOD_BYTES_MIN,
.period_bytes_max = PERIOD_BYTES_MAX,
.periods_min = PERIODS_MIN,
.periods_max = PERIODS_MAX,
};
enum {
AES_TO_AES,
AES_TO_PCM,
PCM_TO_PCM,
PCM_TO_AES
};
static void xlnx_parse_aes_params(u32 chsts_reg1_val, u32 chsts_reg2_val,
struct device *dev)
{
u32 padded, srate, bit_depth, status[2];
if (chsts_reg1_val & IEC958_AES0_PROFESSIONAL) {
status[0] = chsts_reg1_val & 0xff;
status[1] = (chsts_reg1_val >> 16) & 0xff;
switch (status[0] & IEC958_AES0_PRO_FS) {
case IEC958_AES0_PRO_FS_44100:
srate = 44100;
break;
case IEC958_AES0_PRO_FS_48000:
srate = 48000;
break;
case IEC958_AES0_PRO_FS_32000:
srate = 32000;
break;
case IEC958_AES0_PRO_FS_NOTID:
default:
srate = XLNX_PARAM_UNKNOWN;
break;
}
switch (status[1] & IEC958_AES2_PRO_SBITS) {
case IEC958_AES2_PRO_WORDLEN_NOTID:
case IEC958_AES2_PRO_SBITS_20:
padded = 0;
break;
case IEC958_AES2_PRO_SBITS_24:
padded = 4;
break;
default:
bit_depth = XLNX_PARAM_UNKNOWN;
goto log_params;
}
switch (status[1] & IEC958_AES2_PRO_WORDLEN) {
case IEC958_AES2_PRO_WORDLEN_20_16:
bit_depth = 16 + padded;
break;
case IEC958_AES2_PRO_WORDLEN_22_18:
bit_depth = 18 + padded;
break;
case IEC958_AES2_PRO_WORDLEN_23_19:
bit_depth = 19 + padded;
break;
case IEC958_AES2_PRO_WORDLEN_24_20:
bit_depth = 20 + padded;
break;
case IEC958_AES2_PRO_WORDLEN_NOTID:
default:
bit_depth = XLNX_PARAM_UNKNOWN;
break;
}
} else {
status[0] = (chsts_reg1_val >> 24) & 0xff;
status[1] = chsts_reg2_val & 0xff;
switch (status[0] & IEC958_AES3_CON_FS) {
case IEC958_AES3_CON_FS_44100:
srate = 44100;
break;
case IEC958_AES3_CON_FS_48000:
srate = 48000;
break;
case IEC958_AES3_CON_FS_32000:
srate = 32000;
break;
default:
srate = XLNX_PARAM_UNKNOWN;
break;
}
if (status[1] & IEC958_AES4_CON_MAX_WORDLEN_24)
padded = 4;
else
padded = 0;
switch (status[1] & IEC958_AES4_CON_WORDLEN) {
case IEC958_AES4_CON_WORDLEN_20_16:
bit_depth = 16 + padded;
break;
case IEC958_AES4_CON_WORDLEN_22_18:
bit_depth = 18 + padded;
break;
case IEC958_AES4_CON_WORDLEN_23_19:
bit_depth = 19 + padded;
break;
case IEC958_AES4_CON_WORDLEN_24_20:
bit_depth = 20 + padded;
break;
case IEC958_AES4_CON_WORDLEN_21_17:
bit_depth = 17 + padded;
break;
case IEC958_AES4_CON_WORDLEN_NOTID:
default:
bit_depth = XLNX_PARAM_UNKNOWN;
break;
}
}
log_params:
if (srate != XLNX_PARAM_UNKNOWN)
dev_info(dev, "sample rate = %d\n", srate);
else
dev_info(dev, "sample rate = unknown\n");
if (bit_depth != XLNX_PARAM_UNKNOWN)
dev_info(dev, "bit_depth = %d\n", bit_depth);
else
dev_info(dev, "bit_depth = unknown\n");
}
static int xlnx_formatter_pcm_reset(void __iomem *mmio_base)
{
u32 val, retries = 0;
val = readl(mmio_base + XLNX_AUD_CTRL);
val |= AUD_CTRL_RESET_MASK;
writel(val, mmio_base + XLNX_AUD_CTRL);
val = readl(mmio_base + XLNX_AUD_CTRL);
/* Poll for maximum timeout of approximately 100ms (1 * 100)*/
while ((val & AUD_CTRL_RESET_MASK) && (retries < 100)) {
mdelay(1);
retries++;
val = readl(mmio_base + XLNX_AUD_CTRL);
}
if (val & AUD_CTRL_RESET_MASK)
return -ENODEV;
return 0;
}
static void xlnx_formatter_disable_irqs(void __iomem *mmio_base, int stream)
{
u32 val;
val = readl(mmio_base + XLNX_AUD_CTRL);
val &= ~AUD_CTRL_IOC_IRQ_MASK;
if (stream == SNDRV_PCM_STREAM_CAPTURE)
val &= ~AUD_CTRL_TOUT_IRQ_MASK;
writel(val, mmio_base + XLNX_AUD_CTRL);
}
static irqreturn_t xlnx_mm2s_irq_handler(int irq, void *arg)
{
u32 val;
void __iomem *reg;
struct device *dev = arg;
struct xlnx_pcm_drv_data *adata = dev_get_drvdata(dev);
reg = adata->mmio + XLNX_MM2S_OFFSET + XLNX_AUD_STS;
val = readl(reg);
if (val & AUD_STS_IOC_IRQ_MASK) {
writel(val & AUD_STS_IOC_IRQ_MASK, reg);
if (adata->play_stream)
snd_pcm_period_elapsed(adata->play_stream);
return IRQ_HANDLED;
}
return IRQ_NONE;
}
static irqreturn_t xlnx_s2mm_irq_handler(int irq, void *arg)
{
u32 val;
void __iomem *reg;
struct device *dev = arg;
struct xlnx_pcm_drv_data *adata = dev_get_drvdata(dev);
reg = adata->mmio + XLNX_S2MM_OFFSET + XLNX_AUD_STS;
val = readl(reg);
if (val & AUD_STS_IOC_IRQ_MASK) {
writel(val & AUD_STS_IOC_IRQ_MASK, reg);
if (adata->capture_stream)
snd_pcm_period_elapsed(adata->capture_stream);
return IRQ_HANDLED;
}
return IRQ_NONE;
}
static int xlnx_formatter_set_sysclk(struct snd_soc_component *component,
int clk_id, int source, unsigned int freq, int dir)
{
struct xlnx_pcm_drv_data *adata = dev_get_drvdata(component->dev);
adata->sysclk = freq;
return 0;
}
static int xlnx_formatter_pcm_open(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
int err;
u32 val, data_format_mode;
u32 ch_count_mask, ch_count_shift, data_xfer_mode, data_xfer_shift;
struct xlnx_pcm_stream_param *stream_data;
struct snd_pcm_runtime *runtime = substream->runtime;
struct xlnx_pcm_drv_data *adata = dev_get_drvdata(component->dev);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK &&
!adata->mm2s_presence)
return -ENODEV;
else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE &&
!adata->s2mm_presence)
return -ENODEV;
stream_data = kzalloc(sizeof(*stream_data), GFP_KERNEL);
if (!stream_data)
return -ENOMEM;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
ch_count_mask = CFG_MM2S_CH_MASK;
ch_count_shift = CFG_MM2S_CH_SHIFT;
data_xfer_mode = CFG_MM2S_XFER_MASK;
data_xfer_shift = CFG_MM2S_XFER_SHIFT;
data_format_mode = CFG_MM2S_PKG_MASK;
stream_data->mmio = adata->mmio + XLNX_MM2S_OFFSET;
adata->play_stream = substream;
} else {
ch_count_mask = CFG_S2MM_CH_MASK;
ch_count_shift = CFG_S2MM_CH_SHIFT;
data_xfer_mode = CFG_S2MM_XFER_MASK;
data_xfer_shift = CFG_S2MM_XFER_SHIFT;
data_format_mode = CFG_S2MM_PKG_MASK;
stream_data->mmio = adata->mmio + XLNX_S2MM_OFFSET;
adata->capture_stream = substream;
}
val = readl(adata->mmio + XLNX_AUD_CORE_CONFIG);
if (!(val & data_format_mode))
stream_data->interleaved = true;
stream_data->xfer_mode = (val & data_xfer_mode) >> data_xfer_shift;
stream_data->ch_limit = (val & ch_count_mask) >> ch_count_shift;
dev_info(component->dev,
"stream %d : format = %d mode = %d ch_limit = %d\n",
substream->stream, stream_data->interleaved,
stream_data->xfer_mode, stream_data->ch_limit);
snd_soc_set_runtime_hwparams(substream, &xlnx_pcm_hardware);
runtime->private_data = stream_data;
/* Resize the period bytes as divisible by 64 */
err = snd_pcm_hw_constraint_step(runtime, 0,
SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
XLNX_AUD_ALIGN_BYTES);
if (err) {
dev_err(component->dev,
"Unable to set constraint on period bytes\n");
return err;
}
/* Resize the buffer bytes as divisible by 64 */
err = snd_pcm_hw_constraint_step(runtime, 0,
SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
XLNX_AUD_ALIGN_BYTES);
if (err) {
dev_err(component->dev,
"Unable to set constraint on buffer bytes\n");
return err;
}
/* Set periods as integer multiple */
err = snd_pcm_hw_constraint_integer(runtime,
SNDRV_PCM_HW_PARAM_PERIODS);
if (err < 0) {
dev_err(component->dev,
"Unable to set constraint on periods to be integer\n");
return err;
}
/* enable DMA IOC irq */
val = readl(stream_data->mmio + XLNX_AUD_CTRL);
val |= AUD_CTRL_IOC_IRQ_MASK;
writel(val, stream_data->mmio + XLNX_AUD_CTRL);
return 0;
}
static int xlnx_formatter_pcm_close(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
int ret;
struct xlnx_pcm_stream_param *stream_data =
substream->runtime->private_data;
ret = xlnx_formatter_pcm_reset(stream_data->mmio);
if (ret) {
dev_err(component->dev, "audio formatter reset failed\n");
goto err_reset;
}
xlnx_formatter_disable_irqs(stream_data->mmio, substream->stream);
err_reset:
kfree(stream_data);
return 0;
}
static snd_pcm_uframes_t
xlnx_formatter_pcm_pointer(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
u32 pos;
struct snd_pcm_runtime *runtime = substream->runtime;
struct xlnx_pcm_stream_param *stream_data = runtime->private_data;
pos = readl(stream_data->mmio + XLNX_AUD_XFER_COUNT);
if (pos >= stream_data->buffer_size)
pos = 0;
return bytes_to_frames(runtime, pos);
}
static int xlnx_formatter_pcm_hw_params(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
u32 low, high, active_ch, val, bytes_per_ch, bits_per_sample;
u32 aes_reg1_val, aes_reg2_val;
u64 size;
struct snd_pcm_runtime *runtime = substream->runtime;
struct xlnx_pcm_stream_param *stream_data = runtime->private_data;
struct xlnx_pcm_drv_data *adata = dev_get_drvdata(component->dev);
active_ch = params_channels(params);
if (active_ch > stream_data->ch_limit)
return -EINVAL;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK &&
adata->sysclk) {
unsigned int mclk_fs = adata->sysclk / params_rate(params);
if (adata->sysclk % params_rate(params) != 0) {
dev_warn(component->dev, "sysclk %u not divisible by rate %u\n",
adata->sysclk, params_rate(params));
return -EINVAL;
}
writel(mclk_fs, stream_data->mmio + XLNX_AUD_FS_MULTIPLIER);
}
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE &&
stream_data->xfer_mode == AES_TO_PCM) {
val = readl(stream_data->mmio + XLNX_AUD_STS);
if (val & AUD_STS_CH_STS_MASK) {
aes_reg1_val = readl(stream_data->mmio +
XLNX_AUD_CH_STS_START);
aes_reg2_val = readl(stream_data->mmio +
XLNX_AUD_CH_STS_START + 0x4);
xlnx_parse_aes_params(aes_reg1_val, aes_reg2_val,
component->dev);
}
}
size = params_buffer_bytes(params);
stream_data->buffer_size = size;
low = lower_32_bits(runtime->dma_addr);
high = upper_32_bits(runtime->dma_addr);
writel(low, stream_data->mmio + XLNX_AUD_BUFF_ADDR_LSB);
writel(high, stream_data->mmio + XLNX_AUD_BUFF_ADDR_MSB);
val = readl(stream_data->mmio + XLNX_AUD_CTRL);
bits_per_sample = params_width(params);
switch (bits_per_sample) {
case 8:
val |= (BIT_DEPTH_8 << AUD_CTRL_DATA_WIDTH_SHIFT);
break;
case 16:
val |= (BIT_DEPTH_16 << AUD_CTRL_DATA_WIDTH_SHIFT);
break;
case 20:
val |= (BIT_DEPTH_20 << AUD_CTRL_DATA_WIDTH_SHIFT);
break;
case 24:
val |= (BIT_DEPTH_24 << AUD_CTRL_DATA_WIDTH_SHIFT);
break;
case 32:
val |= (BIT_DEPTH_32 << AUD_CTRL_DATA_WIDTH_SHIFT);
break;
default:
return -EINVAL;
}
val |= active_ch << AUD_CTRL_ACTIVE_CH_SHIFT;
writel(val, stream_data->mmio + XLNX_AUD_CTRL);
val = (params_periods(params) << PERIOD_CFG_PERIODS_SHIFT)
| params_period_bytes(params);
writel(val, stream_data->mmio + XLNX_AUD_PERIOD_CONFIG);
bytes_per_ch = DIV_ROUND_UP(params_period_bytes(params), active_ch);
writel(bytes_per_ch, stream_data->mmio + XLNX_BYTES_PER_CH);
return 0;
}
static int xlnx_formatter_pcm_trigger(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
int cmd)
{
u32 val;
struct xlnx_pcm_stream_param *stream_data =
substream->runtime->private_data;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
case SNDRV_PCM_TRIGGER_RESUME:
val = readl(stream_data->mmio + XLNX_AUD_CTRL);
val |= AUD_CTRL_DMA_EN_MASK;
writel(val, stream_data->mmio + XLNX_AUD_CTRL);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
case SNDRV_PCM_TRIGGER_SUSPEND:
val = readl(stream_data->mmio + XLNX_AUD_CTRL);
val &= ~AUD_CTRL_DMA_EN_MASK;
writel(val, stream_data->mmio + XLNX_AUD_CTRL);
break;
}
return 0;
}
static int xlnx_formatter_pcm_new(struct snd_soc_component *component,
struct snd_soc_pcm_runtime *rtd)
{
snd_pcm_set_managed_buffer_all(rtd->pcm,
SNDRV_DMA_TYPE_DEV, component->dev,
xlnx_pcm_hardware.buffer_bytes_max,
xlnx_pcm_hardware.buffer_bytes_max);
return 0;
}
static const struct snd_soc_component_driver xlnx_asoc_component = {
.name = DRV_NAME,
.set_sysclk = xlnx_formatter_set_sysclk,
.open = xlnx_formatter_pcm_open,
.close = xlnx_formatter_pcm_close,
.hw_params = xlnx_formatter_pcm_hw_params,
.trigger = xlnx_formatter_pcm_trigger,
.pointer = xlnx_formatter_pcm_pointer,
.pcm_construct = xlnx_formatter_pcm_new,
};
static int xlnx_formatter_pcm_probe(struct platform_device *pdev)
{
int ret;
u32 val;
struct xlnx_pcm_drv_data *aud_drv_data;
struct device *dev = &pdev->dev;
aud_drv_data = devm_kzalloc(dev, sizeof(*aud_drv_data), GFP_KERNEL);
if (!aud_drv_data)
return -ENOMEM;
aud_drv_data->axi_clk = devm_clk_get(dev, "s_axi_lite_aclk");
if (IS_ERR(aud_drv_data->axi_clk)) {
ret = PTR_ERR(aud_drv_data->axi_clk);
dev_err(dev, "failed to get s_axi_lite_aclk(%d)\n", ret);
return ret;
}
ret = clk_prepare_enable(aud_drv_data->axi_clk);
if (ret) {
dev_err(dev,
"failed to enable s_axi_lite_aclk(%d)\n", ret);
return ret;
}
aud_drv_data->mmio = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(aud_drv_data->mmio)) {
dev_err(dev, "audio formatter ioremap failed\n");
ret = PTR_ERR(aud_drv_data->mmio);
goto clk_err;
}
val = readl(aud_drv_data->mmio + XLNX_AUD_CORE_CONFIG);
if (val & AUD_CFG_MM2S_MASK) {
aud_drv_data->mm2s_presence = true;
ret = xlnx_formatter_pcm_reset(aud_drv_data->mmio +
XLNX_MM2S_OFFSET);
if (ret) {
dev_err(dev, "audio formatter reset failed\n");
goto clk_err;
}
xlnx_formatter_disable_irqs(aud_drv_data->mmio +
XLNX_MM2S_OFFSET,
SNDRV_PCM_STREAM_PLAYBACK);
aud_drv_data->mm2s_irq = platform_get_irq_byname(pdev,
"irq_mm2s");
if (aud_drv_data->mm2s_irq < 0) {
ret = aud_drv_data->mm2s_irq;
goto clk_err;
}
ret = devm_request_irq(dev, aud_drv_data->mm2s_irq,
xlnx_mm2s_irq_handler, 0,
"xlnx_formatter_pcm_mm2s_irq", dev);
if (ret) {
dev_err(dev, "xlnx audio mm2s irq request failed\n");
goto clk_err;
}
}
if (val & AUD_CFG_S2MM_MASK) {
aud_drv_data->s2mm_presence = true;
ret = xlnx_formatter_pcm_reset(aud_drv_data->mmio +
XLNX_S2MM_OFFSET);
if (ret) {
dev_err(dev, "audio formatter reset failed\n");
goto clk_err;
}
xlnx_formatter_disable_irqs(aud_drv_data->mmio +
XLNX_S2MM_OFFSET,
SNDRV_PCM_STREAM_CAPTURE);
aud_drv_data->s2mm_irq = platform_get_irq_byname(pdev,
"irq_s2mm");
if (aud_drv_data->s2mm_irq < 0) {
ret = aud_drv_data->s2mm_irq;
goto clk_err;
}
ret = devm_request_irq(dev, aud_drv_data->s2mm_irq,
xlnx_s2mm_irq_handler, 0,
"xlnx_formatter_pcm_s2mm_irq",
dev);
if (ret) {
dev_err(dev, "xlnx audio s2mm irq request failed\n");
goto clk_err;
}
}
dev_set_drvdata(dev, aud_drv_data);
ret = devm_snd_soc_register_component(dev, &xlnx_asoc_component,
NULL, 0);
if (ret) {
dev_err(dev, "pcm platform device register failed\n");
goto clk_err;
}
return 0;
clk_err:
clk_disable_unprepare(aud_drv_data->axi_clk);
return ret;
}
static void xlnx_formatter_pcm_remove(struct platform_device *pdev)
{
int ret = 0;
struct xlnx_pcm_drv_data *adata = dev_get_drvdata(&pdev->dev);
if (adata->s2mm_presence)
ret = xlnx_formatter_pcm_reset(adata->mmio + XLNX_S2MM_OFFSET);
/* Try MM2S reset, even if S2MM reset fails */
if (adata->mm2s_presence)
ret = xlnx_formatter_pcm_reset(adata->mmio + XLNX_MM2S_OFFSET);
if (ret)
dev_err(&pdev->dev, "audio formatter reset failed\n");
clk_disable_unprepare(adata->axi_clk);
}
static const struct of_device_id xlnx_formatter_pcm_of_match[] = {
{ .compatible = "xlnx,audio-formatter-1.0"},
{},
};
MODULE_DEVICE_TABLE(of, xlnx_formatter_pcm_of_match);
static struct platform_driver xlnx_formatter_pcm_driver = {
.probe = xlnx_formatter_pcm_probe,
.remove_new = xlnx_formatter_pcm_remove,
.driver = {
.name = DRV_NAME,
.of_match_table = xlnx_formatter_pcm_of_match,
},
};
module_platform_driver(xlnx_formatter_pcm_driver);
MODULE_AUTHOR("Maruthi Srinivas Bayyavarapu <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/xilinx/xlnx_formatter_pcm.c |
// SPDX-License-Identifier: GPL-2.0
//
// Xilinx ASoC I2S audio support
//
// Copyright (C) 2018 Xilinx, Inc.
//
// Author: Praveen Vuppala <[email protected]>
// Author: Maruthi Srinivas Bayyavarapu <[email protected]>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#define DRV_NAME "xlnx_i2s"
#define I2S_CORE_CTRL_OFFSET 0x08
#define I2S_CORE_CTRL_32BIT_LRCLK BIT(3)
#define I2S_CORE_CTRL_ENABLE BIT(0)
#define I2S_I2STIM_OFFSET 0x20
#define I2S_CH0_OFFSET 0x30
#define I2S_I2STIM_VALID_MASK GENMASK(7, 0)
struct xlnx_i2s_drv_data {
struct snd_soc_dai_driver dai_drv;
void __iomem *base;
unsigned int sysclk;
u32 data_width;
u32 channels;
bool is_32bit_lrclk;
struct snd_ratnum ratnum;
struct snd_pcm_hw_constraint_ratnums rate_constraints;
};
static int xlnx_i2s_set_sclkout_div(struct snd_soc_dai *cpu_dai,
int div_id, int div)
{
struct xlnx_i2s_drv_data *drv_data = snd_soc_dai_get_drvdata(cpu_dai);
if (!div || (div & ~I2S_I2STIM_VALID_MASK))
return -EINVAL;
drv_data->sysclk = 0;
writel(div, drv_data->base + I2S_I2STIM_OFFSET);
return 0;
}
static int xlnx_i2s_set_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct xlnx_i2s_drv_data *drv_data = snd_soc_dai_get_drvdata(dai);
drv_data->sysclk = freq;
if (freq) {
unsigned int bits_per_sample;
if (drv_data->is_32bit_lrclk)
bits_per_sample = 32;
else
bits_per_sample = drv_data->data_width;
drv_data->ratnum.num = freq / (bits_per_sample * drv_data->channels) / 2;
drv_data->ratnum.den_step = 1;
drv_data->ratnum.den_min = 1;
drv_data->ratnum.den_max = 255;
drv_data->rate_constraints.rats = &drv_data->ratnum;
drv_data->rate_constraints.nrats = 1;
}
return 0;
}
static int xlnx_i2s_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct xlnx_i2s_drv_data *drv_data = snd_soc_dai_get_drvdata(dai);
if (drv_data->sysclk)
return snd_pcm_hw_constraint_ratnums(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
&drv_data->rate_constraints);
return 0;
}
static int xlnx_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *i2s_dai)
{
u32 reg_off, chan_id;
struct xlnx_i2s_drv_data *drv_data = snd_soc_dai_get_drvdata(i2s_dai);
if (drv_data->sysclk) {
unsigned int bits_per_sample, sclk, sclk_div;
if (drv_data->is_32bit_lrclk)
bits_per_sample = 32;
else
bits_per_sample = drv_data->data_width;
sclk = params_rate(params) * bits_per_sample * params_channels(params);
sclk_div = drv_data->sysclk / sclk / 2;
if ((drv_data->sysclk % sclk != 0) ||
!sclk_div || (sclk_div & ~I2S_I2STIM_VALID_MASK)) {
dev_warn(i2s_dai->dev, "invalid SCLK divisor for sysclk %u and sclk %u\n",
drv_data->sysclk, sclk);
return -EINVAL;
}
writel(sclk_div, drv_data->base + I2S_I2STIM_OFFSET);
}
chan_id = params_channels(params) / 2;
while (chan_id > 0) {
reg_off = I2S_CH0_OFFSET + ((chan_id - 1) * 4);
writel(chan_id, drv_data->base + reg_off);
chan_id--;
}
return 0;
}
static int xlnx_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *i2s_dai)
{
struct xlnx_i2s_drv_data *drv_data = snd_soc_dai_get_drvdata(i2s_dai);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
writel(I2S_CORE_CTRL_ENABLE, drv_data->base + I2S_CORE_CTRL_OFFSET);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
writel(0, drv_data->base + I2S_CORE_CTRL_OFFSET);
break;
default:
return -EINVAL;
}
return 0;
}
static const struct snd_soc_dai_ops xlnx_i2s_dai_ops = {
.trigger = xlnx_i2s_trigger,
.set_sysclk = xlnx_i2s_set_sysclk,
.set_clkdiv = xlnx_i2s_set_sclkout_div,
.startup = xlnx_i2s_startup,
.hw_params = xlnx_i2s_hw_params
};
static const struct snd_soc_component_driver xlnx_i2s_component = {
.name = DRV_NAME,
.legacy_dai_naming = 1,
};
static const struct of_device_id xlnx_i2s_of_match[] = {
{ .compatible = "xlnx,i2s-transmitter-1.0", },
{ .compatible = "xlnx,i2s-receiver-1.0", },
{},
};
MODULE_DEVICE_TABLE(of, xlnx_i2s_of_match);
static int xlnx_i2s_probe(struct platform_device *pdev)
{
struct xlnx_i2s_drv_data *drv_data;
int ret;
u32 format;
struct device *dev = &pdev->dev;
struct device_node *node = dev->of_node;
drv_data = devm_kzalloc(&pdev->dev, sizeof(*drv_data), GFP_KERNEL);
if (!drv_data)
return -ENOMEM;
drv_data->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(drv_data->base))
return PTR_ERR(drv_data->base);
ret = of_property_read_u32(node, "xlnx,num-channels", &drv_data->channels);
if (ret < 0) {
dev_err(dev, "cannot get supported channels\n");
return ret;
}
drv_data->channels *= 2;
ret = of_property_read_u32(node, "xlnx,dwidth", &drv_data->data_width);
if (ret < 0) {
dev_err(dev, "cannot get data width\n");
return ret;
}
switch (drv_data->data_width) {
case 16:
format = SNDRV_PCM_FMTBIT_S16_LE;
break;
case 24:
format = SNDRV_PCM_FMTBIT_S24_LE;
break;
default:
return -EINVAL;
}
if (of_device_is_compatible(node, "xlnx,i2s-transmitter-1.0")) {
drv_data->dai_drv.name = "xlnx_i2s_playback";
drv_data->dai_drv.playback.stream_name = "Playback";
drv_data->dai_drv.playback.formats = format;
drv_data->dai_drv.playback.channels_min = drv_data->channels;
drv_data->dai_drv.playback.channels_max = drv_data->channels;
drv_data->dai_drv.playback.rates = SNDRV_PCM_RATE_8000_192000;
drv_data->dai_drv.ops = &xlnx_i2s_dai_ops;
} else if (of_device_is_compatible(node, "xlnx,i2s-receiver-1.0")) {
drv_data->dai_drv.name = "xlnx_i2s_capture";
drv_data->dai_drv.capture.stream_name = "Capture";
drv_data->dai_drv.capture.formats = format;
drv_data->dai_drv.capture.channels_min = drv_data->channels;
drv_data->dai_drv.capture.channels_max = drv_data->channels;
drv_data->dai_drv.capture.rates = SNDRV_PCM_RATE_8000_192000;
drv_data->dai_drv.ops = &xlnx_i2s_dai_ops;
} else {
return -ENODEV;
}
drv_data->is_32bit_lrclk = readl(drv_data->base + I2S_CORE_CTRL_OFFSET) &
I2S_CORE_CTRL_32BIT_LRCLK;
dev_set_drvdata(&pdev->dev, drv_data);
ret = devm_snd_soc_register_component(&pdev->dev, &xlnx_i2s_component,
&drv_data->dai_drv, 1);
if (ret) {
dev_err(&pdev->dev, "i2s component registration failed\n");
return ret;
}
dev_info(&pdev->dev, "%s DAI registered\n", drv_data->dai_drv.name);
return ret;
}
static struct platform_driver xlnx_i2s_aud_driver = {
.driver = {
.name = DRV_NAME,
.of_match_table = xlnx_i2s_of_match,
},
.probe = xlnx_i2s_probe,
};
module_platform_driver(xlnx_i2s_aud_driver);
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Praveen Vuppala <[email protected]>");
MODULE_AUTHOR("Maruthi Srinivas Bayyavarapu <[email protected]>");
| linux-master | sound/soc/xilinx/xlnx_i2s.c |
// SPDX-License-Identifier: GPL-2.0
//
// Xilinx ASoC SPDIF audio support
//
// Copyright (C) 2018 Xilinx, Inc.
//
// Author: Maruthi Srinivas Bayyavarapu <[email protected]>
//
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#define XLNX_SPDIF_RATES \
(SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \
SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | \
SNDRV_PCM_RATE_192000)
#define XLNX_SPDIF_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
#define XSPDIF_IRQ_STS_REG 0x20
#define XSPDIF_IRQ_ENABLE_REG 0x28
#define XSPDIF_SOFT_RESET_REG 0x40
#define XSPDIF_CONTROL_REG 0x44
#define XSPDIF_CHAN_0_STS_REG 0x4C
#define XSPDIF_GLOBAL_IRQ_ENABLE_REG 0x1C
#define XSPDIF_CH_A_USER_DATA_REG_0 0x64
#define XSPDIF_CORE_ENABLE_MASK BIT(0)
#define XSPDIF_FIFO_FLUSH_MASK BIT(1)
#define XSPDIF_CH_STS_MASK BIT(5)
#define XSPDIF_GLOBAL_IRQ_ENABLE BIT(31)
#define XSPDIF_CLOCK_CONFIG_BITS_MASK GENMASK(5, 2)
#define XSPDIF_CLOCK_CONFIG_BITS_SHIFT 2
#define XSPDIF_SOFT_RESET_VALUE 0xA
#define MAX_CHANNELS 2
#define AES_SAMPLE_WIDTH 32
#define CH_STATUS_UPDATE_TIMEOUT 40
struct spdif_dev_data {
u32 mode;
u32 aclk;
bool rx_chsts_updated;
void __iomem *base;
struct clk *axi_clk;
wait_queue_head_t chsts_q;
};
static irqreturn_t xlnx_spdifrx_irq_handler(int irq, void *arg)
{
u32 val;
struct spdif_dev_data *ctx = arg;
val = readl(ctx->base + XSPDIF_IRQ_STS_REG);
if (val & XSPDIF_CH_STS_MASK) {
writel(val & XSPDIF_CH_STS_MASK,
ctx->base + XSPDIF_IRQ_STS_REG);
val = readl(ctx->base +
XSPDIF_IRQ_ENABLE_REG);
writel(val & ~XSPDIF_CH_STS_MASK,
ctx->base + XSPDIF_IRQ_ENABLE_REG);
ctx->rx_chsts_updated = true;
wake_up_interruptible(&ctx->chsts_q);
return IRQ_HANDLED;
}
return IRQ_NONE;
}
static int xlnx_spdif_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
u32 val;
struct spdif_dev_data *ctx = dev_get_drvdata(dai->dev);
val = readl(ctx->base + XSPDIF_CONTROL_REG);
val |= XSPDIF_FIFO_FLUSH_MASK;
writel(val, ctx->base + XSPDIF_CONTROL_REG);
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
writel(XSPDIF_CH_STS_MASK,
ctx->base + XSPDIF_IRQ_ENABLE_REG);
writel(XSPDIF_GLOBAL_IRQ_ENABLE,
ctx->base + XSPDIF_GLOBAL_IRQ_ENABLE_REG);
}
return 0;
}
static void xlnx_spdif_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct spdif_dev_data *ctx = dev_get_drvdata(dai->dev);
writel(XSPDIF_SOFT_RESET_VALUE, ctx->base + XSPDIF_SOFT_RESET_REG);
}
static int xlnx_spdif_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
u32 val, clk_div, clk_cfg;
struct spdif_dev_data *ctx = dev_get_drvdata(dai->dev);
clk_div = DIV_ROUND_CLOSEST(ctx->aclk, MAX_CHANNELS * AES_SAMPLE_WIDTH *
params_rate(params));
switch (clk_div) {
case 4:
clk_cfg = 0;
break;
case 8:
clk_cfg = 1;
break;
case 16:
clk_cfg = 2;
break;
case 24:
clk_cfg = 3;
break;
case 32:
clk_cfg = 4;
break;
case 48:
clk_cfg = 5;
break;
case 64:
clk_cfg = 6;
break;
default:
return -EINVAL;
}
val = readl(ctx->base + XSPDIF_CONTROL_REG);
val &= ~XSPDIF_CLOCK_CONFIG_BITS_MASK;
val |= clk_cfg << XSPDIF_CLOCK_CONFIG_BITS_SHIFT;
writel(val, ctx->base + XSPDIF_CONTROL_REG);
return 0;
}
static int rx_stream_detect(struct snd_soc_dai *dai)
{
int err;
struct spdif_dev_data *ctx = dev_get_drvdata(dai->dev);
unsigned long jiffies = msecs_to_jiffies(CH_STATUS_UPDATE_TIMEOUT);
/* start capture only if stream is detected within 40ms timeout */
err = wait_event_interruptible_timeout(ctx->chsts_q,
ctx->rx_chsts_updated,
jiffies);
if (!err) {
dev_err(dai->dev, "No streaming audio detected!\n");
return -EINVAL;
}
ctx->rx_chsts_updated = false;
return 0;
}
static int xlnx_spdif_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
u32 val;
int ret = 0;
struct spdif_dev_data *ctx = dev_get_drvdata(dai->dev);
val = readl(ctx->base + XSPDIF_CONTROL_REG);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
val |= XSPDIF_CORE_ENABLE_MASK;
writel(val, ctx->base + XSPDIF_CONTROL_REG);
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
ret = rx_stream_detect(dai);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
val &= ~XSPDIF_CORE_ENABLE_MASK;
writel(val, ctx->base + XSPDIF_CONTROL_REG);
break;
default:
ret = -EINVAL;
}
return ret;
}
static const struct snd_soc_dai_ops xlnx_spdif_dai_ops = {
.startup = xlnx_spdif_startup,
.shutdown = xlnx_spdif_shutdown,
.trigger = xlnx_spdif_trigger,
.hw_params = xlnx_spdif_hw_params,
};
static struct snd_soc_dai_driver xlnx_spdif_tx_dai = {
.name = "xlnx_spdif_tx",
.playback = {
.channels_min = 2,
.channels_max = 2,
.rates = XLNX_SPDIF_RATES,
.formats = XLNX_SPDIF_FORMATS,
},
.ops = &xlnx_spdif_dai_ops,
};
static struct snd_soc_dai_driver xlnx_spdif_rx_dai = {
.name = "xlnx_spdif_rx",
.capture = {
.channels_min = 2,
.channels_max = 2,
.rates = XLNX_SPDIF_RATES,
.formats = XLNX_SPDIF_FORMATS,
},
.ops = &xlnx_spdif_dai_ops,
};
static const struct snd_soc_component_driver xlnx_spdif_component = {
.name = "xlnx-spdif",
.legacy_dai_naming = 1,
};
static const struct of_device_id xlnx_spdif_of_match[] = {
{ .compatible = "xlnx,spdif-2.0", },
{},
};
MODULE_DEVICE_TABLE(of, xlnx_spdif_of_match);
static int xlnx_spdif_probe(struct platform_device *pdev)
{
int ret;
struct snd_soc_dai_driver *dai_drv;
struct spdif_dev_data *ctx;
struct device *dev = &pdev->dev;
struct device_node *node = dev->of_node;
ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
if (!ctx)
return -ENOMEM;
ctx->axi_clk = devm_clk_get(dev, "s_axi_aclk");
if (IS_ERR(ctx->axi_clk)) {
ret = PTR_ERR(ctx->axi_clk);
dev_err(dev, "failed to get s_axi_aclk(%d)\n", ret);
return ret;
}
ret = clk_prepare_enable(ctx->axi_clk);
if (ret) {
dev_err(dev, "failed to enable s_axi_aclk(%d)\n", ret);
return ret;
}
ctx->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(ctx->base)) {
ret = PTR_ERR(ctx->base);
goto clk_err;
}
ret = of_property_read_u32(node, "xlnx,spdif-mode", &ctx->mode);
if (ret < 0) {
dev_err(dev, "cannot get SPDIF mode\n");
goto clk_err;
}
if (ctx->mode) {
dai_drv = &xlnx_spdif_tx_dai;
} else {
ret = platform_get_irq(pdev, 0);
if (ret < 0)
goto clk_err;
ret = devm_request_irq(dev, ret,
xlnx_spdifrx_irq_handler,
0, "XLNX_SPDIF_RX", ctx);
if (ret) {
dev_err(dev, "spdif rx irq request failed\n");
ret = -ENODEV;
goto clk_err;
}
init_waitqueue_head(&ctx->chsts_q);
dai_drv = &xlnx_spdif_rx_dai;
}
ret = of_property_read_u32(node, "xlnx,aud_clk_i", &ctx->aclk);
if (ret < 0) {
dev_err(dev, "cannot get aud_clk_i value\n");
goto clk_err;
}
dev_set_drvdata(dev, ctx);
ret = devm_snd_soc_register_component(dev, &xlnx_spdif_component,
dai_drv, 1);
if (ret) {
dev_err(dev, "SPDIF component registration failed\n");
goto clk_err;
}
writel(XSPDIF_SOFT_RESET_VALUE, ctx->base + XSPDIF_SOFT_RESET_REG);
dev_info(dev, "%s DAI registered\n", dai_drv->name);
clk_err:
clk_disable_unprepare(ctx->axi_clk);
return ret;
}
static void xlnx_spdif_remove(struct platform_device *pdev)
{
struct spdif_dev_data *ctx = dev_get_drvdata(&pdev->dev);
clk_disable_unprepare(ctx->axi_clk);
}
static struct platform_driver xlnx_spdif_driver = {
.driver = {
.name = "xlnx-spdif",
.of_match_table = xlnx_spdif_of_match,
},
.probe = xlnx_spdif_probe,
.remove_new = xlnx_spdif_remove,
};
module_platform_driver(xlnx_spdif_driver);
MODULE_AUTHOR("Maruthi Srinivas Bayyavarapu <[email protected]>");
MODULE_DESCRIPTION("XILINX SPDIF driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/xilinx/xlnx_spdif.c |
// SPDX-License-Identifier: GPL-2.0-only
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <sound/soc.h>
/*
* The I2S interface consists of two ring buffers - one for RX and one for
* TX. A ring buffer has a producer index and a consumer index. Depending
* on which way the data is flowing, either the software or the hardware
* writes data and updates the producer index, and the other end reads data
* and updates the consumer index.
*
* The pointer managed by software is updated using the .ack callback
* (see chv3_dma_ack). This seems to be the only way to reliably obtain
* the appl_ptr from within the driver and pass it to hardware.
*
* Because of the two pointer design, the ring buffer can never be full. With
* capture this isn't a problem, because the hardware being the producer
* will wait for the consumer index to move out of the way. With playback,
* however, this is problematic, because ALSA wants to fill up the buffer
* completely when waiting for hardware. In the .ack callback, the driver
* would have to wait for the consumer index to move out of the way by
* busy-waiting, which would keep stalling the kernel for quite a long time.
*
* The workaround to this problem is to "lie" to ALSA that the hw_pointer
* is one frame behind what it actually is (see chv3_dma_pointer). This
* way, ALSA will not try to fill up the entire buffer, and all callbacks
* are wait-free.
*/
#define I2S_TX_ENABLE 0x00
#define I2S_TX_BASE_ADDR 0x04
#define I2S_TX_BUFFER_SIZE 0x08
#define I2S_TX_PRODUCER_IDX 0x0c
#define I2S_TX_CONSUMER_IDX 0x10
#define I2S_RX_ENABLE 0x14
#define I2S_RX_BASE_ADDR 0x18
#define I2S_RX_BUFFER_SIZE 0x1c
#define I2S_RX_PRODUCER_IDX 0x20
#define I2S_RX_CONSUMER_IDX 0x24
#define I2S_SOFT_RESET 0x2c
#define I2S_SOFT_RESET_RX_BIT 0x1
#define I2S_SOFT_RESET_TX_BIT 0x2
#define I2S_RX_IRQ 0x4c
#define I2S_RX_IRQ_CONST 0x50
#define I2S_TX_IRQ 0x54
#define I2S_TX_IRQ_CONST 0x58
#define I2S_IRQ_MASK 0x8
#define I2S_IRQ_CLR 0xc
#define I2S_IRQ_RX_BIT 0x1
#define I2S_IRQ_TX_BIT 0x2
#define I2S_MAX_BUFFER_SIZE 0x200000
struct chv3_i2s_dev {
struct device *dev;
void __iomem *iobase;
void __iomem *iobase_irq;
struct snd_pcm_substream *rx_substream;
struct snd_pcm_substream *tx_substream;
int tx_bytes_to_fetch;
};
static struct snd_soc_dai_driver chv3_i2s_dai = {
.name = "chv3-i2s",
.capture = {
.channels_min = 1,
.channels_max = 128,
.rates = SNDRV_PCM_RATE_CONTINUOUS,
.rate_min = 8000,
.rate_max = 96000,
.formats = SNDRV_PCM_FMTBIT_S32_LE,
},
.playback = {
.channels_min = 1,
.channels_max = 128,
.rates = SNDRV_PCM_RATE_CONTINUOUS,
.rate_min = 8000,
.rate_max = 96000,
.formats = SNDRV_PCM_FMTBIT_S32_LE,
},
};
static const struct snd_pcm_hardware chv3_dma_hw = {
.info = SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_BLOCK_TRANSFER,
.buffer_bytes_max = I2S_MAX_BUFFER_SIZE,
.period_bytes_min = 64,
.period_bytes_max = 8192,
.periods_min = 4,
.periods_max = 256,
};
static inline void chv3_i2s_wr(struct chv3_i2s_dev *i2s, int offset, u32 val)
{
writel(val, i2s->iobase + offset);
}
static inline u32 chv3_i2s_rd(struct chv3_i2s_dev *i2s, int offset)
{
return readl(i2s->iobase + offset);
}
static irqreturn_t chv3_i2s_isr(int irq, void *data)
{
struct chv3_i2s_dev *i2s = data;
u32 reg;
reg = readl(i2s->iobase_irq + I2S_IRQ_CLR);
if (!reg)
return IRQ_NONE;
if (reg & I2S_IRQ_RX_BIT)
snd_pcm_period_elapsed(i2s->rx_substream);
if (reg & I2S_IRQ_TX_BIT)
snd_pcm_period_elapsed(i2s->tx_substream);
writel(reg, i2s->iobase_irq + I2S_IRQ_CLR);
return IRQ_HANDLED;
}
static int chv3_dma_open(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct chv3_i2s_dev *i2s = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
int res;
snd_soc_set_runtime_hwparams(substream, &chv3_dma_hw);
res = snd_pcm_hw_constraint_pow2(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_BUFFER_BYTES);
if (res)
return res;
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
i2s->rx_substream = substream;
else
i2s->tx_substream = substream;
return 0;
}
static int chv3_dma_close(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct chv3_i2s_dev *i2s = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
chv3_i2s_wr(i2s, I2S_RX_ENABLE, 0);
else
chv3_i2s_wr(i2s, I2S_TX_ENABLE, 0);
return 0;
}
static int chv3_dma_pcm_construct(struct snd_soc_component *component,
struct snd_soc_pcm_runtime *rtd)
{
struct chv3_i2s_dev *i2s = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
struct snd_pcm_substream *substream;
int res;
substream = rtd->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
if (substream) {
res = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, i2s->dev,
I2S_MAX_BUFFER_SIZE, &substream->dma_buffer);
if (res)
return res;
}
substream = rtd->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream;
if (substream) {
res = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, i2s->dev,
I2S_MAX_BUFFER_SIZE, &substream->dma_buffer);
if (res)
return res;
}
return 0;
}
static int chv3_dma_hw_params(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
return 0;
}
static int chv3_dma_prepare(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct chv3_i2s_dev *i2s = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
unsigned int buffer_bytes, period_bytes, period_size;
buffer_bytes = snd_pcm_lib_buffer_bytes(substream);
period_bytes = snd_pcm_lib_period_bytes(substream);
period_size = substream->runtime->period_size;
if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE) {
chv3_i2s_wr(i2s, I2S_SOFT_RESET, I2S_SOFT_RESET_RX_BIT);
chv3_i2s_wr(i2s, I2S_RX_BASE_ADDR, substream->dma_buffer.addr);
chv3_i2s_wr(i2s, I2S_RX_BUFFER_SIZE, buffer_bytes);
chv3_i2s_wr(i2s, I2S_RX_IRQ, (period_size << 8) | 1);
chv3_i2s_wr(i2s, I2S_RX_ENABLE, 1);
} else {
chv3_i2s_wr(i2s, I2S_SOFT_RESET, I2S_SOFT_RESET_TX_BIT);
chv3_i2s_wr(i2s, I2S_TX_BASE_ADDR, substream->dma_buffer.addr);
chv3_i2s_wr(i2s, I2S_TX_BUFFER_SIZE, buffer_bytes);
chv3_i2s_wr(i2s, I2S_TX_IRQ, ((period_bytes / i2s->tx_bytes_to_fetch) << 8) | 1);
chv3_i2s_wr(i2s, I2S_TX_ENABLE, 1);
}
writel(I2S_IRQ_RX_BIT | I2S_IRQ_TX_BIT, i2s->iobase_irq + I2S_IRQ_MASK);
return 0;
}
static snd_pcm_uframes_t chv3_dma_pointer(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct chv3_i2s_dev *i2s = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
u32 frame_bytes, buffer_bytes;
u32 idx_bytes;
frame_bytes = substream->runtime->frame_bits * 8;
buffer_bytes = snd_pcm_lib_buffer_bytes(substream);
if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE) {
idx_bytes = chv3_i2s_rd(i2s, I2S_RX_PRODUCER_IDX);
} else {
idx_bytes = chv3_i2s_rd(i2s, I2S_TX_CONSUMER_IDX);
/* lag the pointer by one frame */
idx_bytes = (idx_bytes - frame_bytes) & (buffer_bytes - 1);
}
return bytes_to_frames(substream->runtime, idx_bytes);
}
static int chv3_dma_ack(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct chv3_i2s_dev *i2s = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
unsigned int bytes, idx;
bytes = frames_to_bytes(runtime, runtime->control->appl_ptr);
idx = bytes & (snd_pcm_lib_buffer_bytes(substream) - 1);
if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
chv3_i2s_wr(i2s, I2S_RX_CONSUMER_IDX, idx);
else
chv3_i2s_wr(i2s, I2S_TX_PRODUCER_IDX, idx);
return 0;
}
static const struct snd_soc_component_driver chv3_i2s_comp = {
.name = "chv3-i2s-comp",
.open = chv3_dma_open,
.close = chv3_dma_close,
.pcm_construct = chv3_dma_pcm_construct,
.hw_params = chv3_dma_hw_params,
.prepare = chv3_dma_prepare,
.pointer = chv3_dma_pointer,
.ack = chv3_dma_ack,
};
static int chv3_i2s_probe(struct platform_device *pdev)
{
struct chv3_i2s_dev *i2s;
int res;
int irq;
i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
if (!i2s)
return -ENOMEM;
i2s->iobase = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(i2s->iobase))
return PTR_ERR(i2s->iobase);
i2s->iobase_irq = devm_platform_ioremap_resource(pdev, 1);
if (IS_ERR(i2s->iobase_irq))
return PTR_ERR(i2s->iobase_irq);
i2s->tx_bytes_to_fetch = (chv3_i2s_rd(i2s, I2S_TX_IRQ_CONST) >> 8) & 0xffff;
i2s->dev = &pdev->dev;
dev_set_drvdata(&pdev->dev, i2s);
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return -ENXIO;
res = devm_request_irq(i2s->dev, irq, chv3_i2s_isr, 0, "chv3-i2s", i2s);
if (res)
return res;
res = devm_snd_soc_register_component(&pdev->dev, &chv3_i2s_comp,
&chv3_i2s_dai, 1);
if (res) {
dev_err(&pdev->dev, "couldn't register component: %d\n", res);
return res;
}
return 0;
}
static const struct of_device_id chv3_i2s_of_match[] = {
{ .compatible = "google,chv3-i2s" },
{},
};
static struct platform_driver chv3_i2s_driver = {
.probe = chv3_i2s_probe,
.driver = {
.name = "chv3-i2s",
.of_match_table = chv3_i2s_of_match,
},
};
module_platform_driver(chv3_i2s_driver);
MODULE_AUTHOR("Pawel Anikiel <[email protected]>");
MODULE_DESCRIPTION("Chameleon v3 I2S interface");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/google/chv3-i2s.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021 The Linux Foundation. All rights reserved.
*
* lpass-cdc-dma.c -- ALSA SoC CDC DMA CPU DAI driver for QTi LPASS
*/
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/export.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include "lpass-lpaif-reg.h"
#include "lpass.h"
#define CODEC_MEM_HZ_NORMAL 153600000
enum codec_dma_interfaces {
LPASS_CDC_DMA_INTERFACE1 = 1,
LPASS_CDC_DMA_INTERFACE2,
LPASS_CDC_DMA_INTERFACE3,
LPASS_CDC_DMA_INTERFACE4,
LPASS_CDC_DMA_INTERFACE5,
LPASS_CDC_DMA_INTERFACE6,
LPASS_CDC_DMA_INTERFACE7,
LPASS_CDC_DMA_INTERFACE8,
LPASS_CDC_DMA_INTERFACE9,
LPASS_CDC_DMA_INTERFACE10,
};
static void __lpass_get_dmactl_handle(struct snd_pcm_substream *substream, struct snd_soc_dai *dai,
struct lpaif_dmactl **dmactl, int *id)
{
struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
struct snd_pcm_runtime *rt = substream->runtime;
struct lpass_pcm_data *pcm_data = rt->private_data;
struct lpass_variant *v = drvdata->variant;
unsigned int dai_id = cpu_dai->driver->id;
switch (dai_id) {
case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9:
*dmactl = drvdata->rxtx_rd_dmactl;
*id = pcm_data->dma_ch;
break;
case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8:
*dmactl = drvdata->rxtx_wr_dmactl;
*id = pcm_data->dma_ch - v->rxtx_wrdma_channel_start;
break;
case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8:
*dmactl = drvdata->va_wr_dmactl;
*id = pcm_data->dma_ch - v->va_wrdma_channel_start;
break;
default:
dev_err(soc_runtime->dev, "invalid dai id for dma ctl: %d\n", dai_id);
break;
}
}
static int __lpass_get_codec_dma_intf_type(int dai_id)
{
int ret;
switch (dai_id) {
case LPASS_CDC_DMA_RX0:
case LPASS_CDC_DMA_TX0:
case LPASS_CDC_DMA_VA_TX0:
ret = LPASS_CDC_DMA_INTERFACE1;
break;
case LPASS_CDC_DMA_RX1:
case LPASS_CDC_DMA_TX1:
case LPASS_CDC_DMA_VA_TX1:
ret = LPASS_CDC_DMA_INTERFACE2;
break;
case LPASS_CDC_DMA_RX2:
case LPASS_CDC_DMA_TX2:
case LPASS_CDC_DMA_VA_TX2:
ret = LPASS_CDC_DMA_INTERFACE3;
break;
case LPASS_CDC_DMA_RX3:
case LPASS_CDC_DMA_TX3:
case LPASS_CDC_DMA_VA_TX3:
ret = LPASS_CDC_DMA_INTERFACE4;
break;
case LPASS_CDC_DMA_RX4:
case LPASS_CDC_DMA_TX4:
case LPASS_CDC_DMA_VA_TX4:
ret = LPASS_CDC_DMA_INTERFACE5;
break;
case LPASS_CDC_DMA_RX5:
case LPASS_CDC_DMA_TX5:
case LPASS_CDC_DMA_VA_TX5:
ret = LPASS_CDC_DMA_INTERFACE6;
break;
case LPASS_CDC_DMA_RX6:
case LPASS_CDC_DMA_TX6:
case LPASS_CDC_DMA_VA_TX6:
ret = LPASS_CDC_DMA_INTERFACE7;
break;
case LPASS_CDC_DMA_RX7:
case LPASS_CDC_DMA_TX7:
case LPASS_CDC_DMA_VA_TX7:
ret = LPASS_CDC_DMA_INTERFACE8;
break;
case LPASS_CDC_DMA_RX8:
case LPASS_CDC_DMA_TX8:
case LPASS_CDC_DMA_VA_TX8:
ret = LPASS_CDC_DMA_INTERFACE9;
break;
case LPASS_CDC_DMA_RX9:
ret = LPASS_CDC_DMA_INTERFACE10;
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
static int __lpass_platform_codec_intf_init(struct snd_soc_dai *dai,
struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
struct lpaif_dmactl *dmactl = NULL;
struct device *dev = soc_runtime->dev;
int ret, id, codec_intf;
unsigned int dai_id = cpu_dai->driver->id;
codec_intf = __lpass_get_codec_dma_intf_type(dai_id);
if (codec_intf < 0) {
dev_err(dev, "failed to get codec_intf: %d\n", codec_intf);
return codec_intf;
}
__lpass_get_dmactl_handle(substream, dai, &dmactl, &id);
if (!dmactl)
return -EINVAL;
ret = regmap_fields_write(dmactl->codec_intf, id, codec_intf);
if (ret) {
dev_err(dev, "error writing to dmactl codec_intf reg field: %d\n", ret);
return ret;
}
ret = regmap_fields_write(dmactl->codec_fs_sel, id, 0x0);
if (ret) {
dev_err(dev, "error writing to dmactl codec_fs_sel reg field: %d\n", ret);
return ret;
}
ret = regmap_fields_write(dmactl->codec_fs_delay, id, 0x0);
if (ret) {
dev_err(dev, "error writing to dmactl codec_fs_delay reg field: %d\n", ret);
return ret;
}
ret = regmap_fields_write(dmactl->codec_pack, id, 0x1);
if (ret) {
dev_err(dev, "error writing to dmactl codec_pack reg field: %d\n", ret);
return ret;
}
ret = regmap_fields_write(dmactl->codec_enable, id, LPAIF_DMACTL_ENABLE_ON);
if (ret) {
dev_err(dev, "error writing to dmactl codec_enable reg field: %d\n", ret);
return ret;
}
return 0;
}
static int lpass_cdc_dma_daiops_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
switch (dai->id) {
case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9:
case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8:
clk_set_rate(drvdata->codec_mem0, CODEC_MEM_HZ_NORMAL);
clk_prepare_enable(drvdata->codec_mem0);
break;
case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX0:
clk_set_rate(drvdata->va_mem0, CODEC_MEM_HZ_NORMAL);
clk_prepare_enable(drvdata->va_mem0);
break;
default:
dev_err(soc_runtime->dev, "%s: invalid interface: %d\n", __func__, dai->id);
break;
}
return 0;
}
static void lpass_cdc_dma_daiops_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
switch (dai->id) {
case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9:
case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8:
clk_disable_unprepare(drvdata->codec_mem0);
break;
case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX0:
clk_disable_unprepare(drvdata->va_mem0);
break;
default:
dev_err(soc_runtime->dev, "%s: invalid interface: %d\n", __func__, dai->id);
break;
}
}
static int lpass_cdc_dma_daiops_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
struct lpaif_dmactl *dmactl = NULL;
unsigned int ret, regval;
unsigned int channels = params_channels(params);
int id;
switch (channels) {
case 1:
regval = LPASS_CDC_DMA_INTF_ONE_CHANNEL;
break;
case 2:
regval = LPASS_CDC_DMA_INTF_TWO_CHANNEL;
break;
case 4:
regval = LPASS_CDC_DMA_INTF_FOUR_CHANNEL;
break;
case 6:
regval = LPASS_CDC_DMA_INTF_SIX_CHANNEL;
break;
case 8:
regval = LPASS_CDC_DMA_INTF_EIGHT_CHANNEL;
break;
default:
dev_err(soc_runtime->dev, "invalid PCM config\n");
return -EINVAL;
}
__lpass_get_dmactl_handle(substream, dai, &dmactl, &id);
if (!dmactl)
return -EINVAL;
ret = regmap_fields_write(dmactl->codec_channel, id, regval);
if (ret) {
dev_err(soc_runtime->dev,
"error writing to dmactl codec_channel reg field: %d\n", ret);
return ret;
}
return 0;
}
static int lpass_cdc_dma_daiops_trigger(struct snd_pcm_substream *substream,
int cmd, struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
struct lpaif_dmactl *dmactl;
int ret = 0, id;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
__lpass_platform_codec_intf_init(dai, substream);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
__lpass_get_dmactl_handle(substream, dai, &dmactl, &id);
if (!dmactl)
return -EINVAL;
ret = regmap_fields_write(dmactl->codec_enable, id, LPAIF_DMACTL_ENABLE_OFF);
if (ret) {
dev_err(soc_runtime->dev,
"error writing to dmactl codec_enable reg: %d\n", ret);
return ret;
}
break;
default:
ret = -EINVAL;
dev_err(soc_runtime->dev, "%s: invalid %d interface\n", __func__, cmd);
break;
}
return ret;
}
const struct snd_soc_dai_ops asoc_qcom_lpass_cdc_dma_dai_ops = {
.startup = lpass_cdc_dma_daiops_startup,
.shutdown = lpass_cdc_dma_daiops_shutdown,
.hw_params = lpass_cdc_dma_daiops_hw_params,
.trigger = lpass_cdc_dma_daiops_trigger,
};
EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cdc_dma_dai_ops);
MODULE_DESCRIPTION("QTi LPASS CDC DMA Driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/qcom/lpass-cdc-dma.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2018, Linaro Limited.
// Copyright (c) 2018, The Linux Foundation. All rights reserved.
#include <linux/module.h>
#include <sound/jack.h>
#include <linux/input-event-codes.h>
#include "qdsp6/q6afe.h"
#include "common.h"
static const struct snd_soc_dapm_widget qcom_jack_snd_widgets[] = {
SND_SOC_DAPM_HP("Headphone Jack", NULL),
SND_SOC_DAPM_MIC("Mic Jack", NULL),
};
int qcom_snd_parse_of(struct snd_soc_card *card)
{
struct device_node *np;
struct device_node *codec = NULL;
struct device_node *platform = NULL;
struct device_node *cpu = NULL;
struct device *dev = card->dev;
struct snd_soc_dai_link *link;
struct of_phandle_args args;
struct snd_soc_dai_link_component *dlc;
int ret, num_links;
ret = snd_soc_of_parse_card_name(card, "model");
if (ret == 0 && !card->name)
/* Deprecated, only for compatibility with old device trees */
ret = snd_soc_of_parse_card_name(card, "qcom,model");
if (ret) {
dev_err(dev, "Error parsing card name: %d\n", ret);
return ret;
}
if (of_property_read_bool(dev->of_node, "widgets")) {
ret = snd_soc_of_parse_audio_simple_widgets(card, "widgets");
if (ret)
return ret;
}
/* DAPM routes */
if (of_property_read_bool(dev->of_node, "audio-routing")) {
ret = snd_soc_of_parse_audio_routing(card, "audio-routing");
if (ret)
return ret;
}
/* Deprecated, only for compatibility with old device trees */
if (of_property_read_bool(dev->of_node, "qcom,audio-routing")) {
ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
if (ret)
return ret;
}
ret = snd_soc_of_parse_pin_switches(card, "pin-switches");
if (ret)
return ret;
ret = snd_soc_of_parse_aux_devs(card, "aux-devs");
if (ret)
return ret;
/* Populate links */
num_links = of_get_available_child_count(dev->of_node);
/* Allocate the DAI link array */
card->dai_link = devm_kcalloc(dev, num_links, sizeof(*link), GFP_KERNEL);
if (!card->dai_link)
return -ENOMEM;
card->num_links = num_links;
link = card->dai_link;
for_each_available_child_of_node(dev->of_node, np) {
dlc = devm_kzalloc(dev, 2 * sizeof(*dlc), GFP_KERNEL);
if (!dlc) {
ret = -ENOMEM;
goto err_put_np;
}
link->cpus = &dlc[0];
link->platforms = &dlc[1];
link->num_cpus = 1;
link->num_platforms = 1;
ret = of_property_read_string(np, "link-name", &link->name);
if (ret) {
dev_err(card->dev, "error getting codec dai_link name\n");
goto err_put_np;
}
cpu = of_get_child_by_name(np, "cpu");
platform = of_get_child_by_name(np, "platform");
codec = of_get_child_by_name(np, "codec");
if (!cpu) {
dev_err(dev, "%s: Can't find cpu DT node\n", link->name);
ret = -EINVAL;
goto err;
}
ret = snd_soc_of_get_dlc(cpu, &args, link->cpus, 0);
if (ret) {
dev_err_probe(card->dev, ret,
"%s: error getting cpu dai name\n", link->name);
goto err;
}
link->id = args.args[0];
if (platform) {
link->platforms->of_node = of_parse_phandle(platform,
"sound-dai",
0);
if (!link->platforms->of_node) {
dev_err(card->dev, "%s: platform dai not found\n", link->name);
ret = -EINVAL;
goto err;
}
} else {
link->platforms->of_node = link->cpus->of_node;
}
if (codec) {
ret = snd_soc_of_get_dai_link_codecs(dev, codec, link);
if (ret < 0) {
dev_err_probe(card->dev, ret,
"%s: codec dai not found\n", link->name);
goto err;
}
if (platform) {
/* DPCM backend */
link->no_pcm = 1;
link->ignore_pmdown_time = 1;
}
} else {
/* DPCM frontend */
link->codecs = &asoc_dummy_dlc;
link->num_codecs = 1;
link->dynamic = 1;
}
if (platform || !codec) {
/* DPCM */
snd_soc_dai_link_set_capabilities(link);
link->ignore_suspend = 1;
link->nonatomic = 1;
}
link->stream_name = link->name;
link++;
of_node_put(cpu);
of_node_put(codec);
of_node_put(platform);
}
if (!card->dapm_widgets) {
card->dapm_widgets = qcom_jack_snd_widgets;
card->num_dapm_widgets = ARRAY_SIZE(qcom_jack_snd_widgets);
}
return 0;
err:
of_node_put(cpu);
of_node_put(codec);
of_node_put(platform);
err_put_np:
of_node_put(np);
return ret;
}
EXPORT_SYMBOL_GPL(qcom_snd_parse_of);
static struct snd_soc_jack_pin qcom_headset_jack_pins[] = {
/* Headset */
{
.pin = "Mic Jack",
.mask = SND_JACK_MICROPHONE,
},
{
.pin = "Headphone Jack",
.mask = SND_JACK_HEADPHONE,
},
};
int qcom_snd_wcd_jack_setup(struct snd_soc_pcm_runtime *rtd,
struct snd_soc_jack *jack, bool *jack_setup)
{
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
struct snd_soc_card *card = rtd->card;
int rval, i;
if (!*jack_setup) {
rval = snd_soc_card_jack_new_pins(card, "Headset Jack",
SND_JACK_HEADSET | SND_JACK_LINEOUT |
SND_JACK_MECHANICAL |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3 |
SND_JACK_BTN_4 | SND_JACK_BTN_5,
jack, qcom_headset_jack_pins,
ARRAY_SIZE(qcom_headset_jack_pins));
if (rval < 0) {
dev_err(card->dev, "Unable to add Headphone Jack\n");
return rval;
}
snd_jack_set_key(jack->jack, SND_JACK_BTN_0, KEY_MEDIA);
snd_jack_set_key(jack->jack, SND_JACK_BTN_1, KEY_VOICECOMMAND);
snd_jack_set_key(jack->jack, SND_JACK_BTN_2, KEY_VOLUMEUP);
snd_jack_set_key(jack->jack, SND_JACK_BTN_3, KEY_VOLUMEDOWN);
*jack_setup = true;
}
switch (cpu_dai->id) {
case TX_CODEC_DMA_TX_0:
case TX_CODEC_DMA_TX_1:
case TX_CODEC_DMA_TX_2:
case TX_CODEC_DMA_TX_3:
for_each_rtd_codec_dais(rtd, i, codec_dai) {
rval = snd_soc_component_set_jack(codec_dai->component,
jack, NULL);
if (rval != 0 && rval != -ENOTSUPP) {
dev_warn(card->dev, "Failed to set jack: %d\n", rval);
return rval;
}
}
break;
default:
break;
}
return 0;
}
EXPORT_SYMBOL_GPL(qcom_snd_wcd_jack_setup);
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/qcom/common.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2018, Linaro Limited.
// Copyright (c) 2018, The Linux Foundation. All rights reserved.
#include <linux/module.h>
#include <sound/soc.h>
#include "qdsp6/q6afe.h"
#include "sdw.h"
int qcom_snd_sdw_prepare(struct snd_pcm_substream *substream,
struct sdw_stream_runtime *sruntime,
bool *stream_prepared)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
int ret;
if (!sruntime)
return 0;
switch (cpu_dai->id) {
case WSA_CODEC_DMA_RX_0:
case WSA_CODEC_DMA_RX_1:
case RX_CODEC_DMA_RX_0:
case RX_CODEC_DMA_RX_1:
case TX_CODEC_DMA_TX_0:
case TX_CODEC_DMA_TX_1:
case TX_CODEC_DMA_TX_2:
case TX_CODEC_DMA_TX_3:
break;
default:
return 0;
}
if (*stream_prepared)
return 0;
ret = sdw_prepare_stream(sruntime);
if (ret)
return ret;
/**
* NOTE: there is a strict hw requirement about the ordering of port
* enables and actual WSA881x PA enable. PA enable should only happen
* after soundwire ports are enabled if not DC on the line is
* accumulated resulting in Click/Pop Noise
* PA enable/mute are handled as part of codec DAPM and digital mute.
*/
ret = sdw_enable_stream(sruntime);
if (ret) {
sdw_deprepare_stream(sruntime);
return ret;
}
*stream_prepared = true;
return ret;
}
EXPORT_SYMBOL_GPL(qcom_snd_sdw_prepare);
int qcom_snd_sdw_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct sdw_stream_runtime **psruntime)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *codec_dai;
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct sdw_stream_runtime *sruntime;
int i;
switch (cpu_dai->id) {
case WSA_CODEC_DMA_RX_0:
case RX_CODEC_DMA_RX_0:
case RX_CODEC_DMA_RX_1:
case TX_CODEC_DMA_TX_0:
case TX_CODEC_DMA_TX_1:
case TX_CODEC_DMA_TX_2:
case TX_CODEC_DMA_TX_3:
for_each_rtd_codec_dais(rtd, i, codec_dai) {
sruntime = snd_soc_dai_get_stream(codec_dai, substream->stream);
if (sruntime != ERR_PTR(-ENOTSUPP))
*psruntime = sruntime;
}
break;
}
return 0;
}
EXPORT_SYMBOL_GPL(qcom_snd_sdw_hw_params);
int qcom_snd_sdw_hw_free(struct snd_pcm_substream *substream,
struct sdw_stream_runtime *sruntime, bool *stream_prepared)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
switch (cpu_dai->id) {
case WSA_CODEC_DMA_RX_0:
case WSA_CODEC_DMA_RX_1:
case RX_CODEC_DMA_RX_0:
case RX_CODEC_DMA_RX_1:
case TX_CODEC_DMA_TX_0:
case TX_CODEC_DMA_TX_1:
case TX_CODEC_DMA_TX_2:
case TX_CODEC_DMA_TX_3:
if (sruntime && *stream_prepared) {
sdw_disable_stream(sruntime);
sdw_deprepare_stream(sruntime);
*stream_prepared = false;
}
break;
default:
break;
}
return 0;
}
EXPORT_SYMBOL_GPL(qcom_snd_sdw_hw_free);
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/qcom/sdw.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
//
// ALSA SoC Machine driver for sc7280
#include <linux/input.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <sound/core.h>
#include <sound/jack.h>
#include <sound/pcm.h>
#include <sound/soc.h>
#include <sound/rt5682s.h>
#include <linux/soundwire/sdw.h>
#include <sound/pcm_params.h>
#include "../codecs/rt5682.h"
#include "../codecs/rt5682s.h"
#include "common.h"
#include "lpass.h"
#include "qdsp6/q6afe.h"
#define DEFAULT_MCLK_RATE 19200000
#define RT5682_PLL_FREQ (48000 * 512)
#define MI2S_BCLK_RATE 1536000
struct sc7280_snd_data {
struct snd_soc_card card;
struct sdw_stream_runtime *sruntime[LPASS_MAX_PORTS];
u32 pri_mi2s_clk_count;
struct snd_soc_jack hs_jack;
struct snd_soc_jack hdmi_jack;
bool jack_setup;
bool stream_prepared[LPASS_MAX_PORTS];
};
static void sc7280_jack_free(struct snd_jack *jack)
{
struct snd_soc_component *component = jack->private_data;
snd_soc_component_set_jack(component, NULL, NULL);
}
static struct snd_soc_jack_pin sc7280_jack_pins[] = {
{
.pin = "Headphone Jack",
.mask = SND_JACK_HEADPHONE,
},
{
.pin = "Headset Mic",
.mask = SND_JACK_MICROPHONE,
},
};
static int sc7280_headset_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_card *card = rtd->card;
struct sc7280_snd_data *pdata = snd_soc_card_get_drvdata(card);
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct snd_soc_component *component = codec_dai->component;
struct snd_jack *jack;
int rval, i;
if (!pdata->jack_setup) {
rval = snd_soc_card_jack_new_pins(card, "Headset Jack",
SND_JACK_HEADSET | SND_JACK_LINEOUT |
SND_JACK_MECHANICAL |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3 |
SND_JACK_BTN_4 | SND_JACK_BTN_5,
&pdata->hs_jack,
sc7280_jack_pins,
ARRAY_SIZE(sc7280_jack_pins));
if (rval < 0) {
dev_err(card->dev, "Unable to add Headset Jack\n");
return rval;
}
jack = pdata->hs_jack.jack;
snd_jack_set_key(jack, SND_JACK_BTN_0, KEY_PLAYPAUSE);
snd_jack_set_key(jack, SND_JACK_BTN_1, KEY_VOICECOMMAND);
snd_jack_set_key(jack, SND_JACK_BTN_2, KEY_VOLUMEUP);
snd_jack_set_key(jack, SND_JACK_BTN_3, KEY_VOLUMEDOWN);
jack->private_data = component;
jack->private_free = sc7280_jack_free;
pdata->jack_setup = true;
}
switch (cpu_dai->id) {
case MI2S_PRIMARY:
case LPASS_CDC_DMA_RX0:
case LPASS_CDC_DMA_TX3:
case TX_CODEC_DMA_TX_3:
for_each_rtd_codec_dais(rtd, i, codec_dai) {
rval = snd_soc_component_set_jack(component, &pdata->hs_jack, NULL);
if (rval != 0 && rval != -ENOTSUPP) {
dev_err(card->dev, "Failed to set jack: %d\n", rval);
return rval;
}
}
break;
default:
break;
}
return 0;
}
static int sc7280_hdmi_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_card *card = rtd->card;
struct sc7280_snd_data *pdata = snd_soc_card_get_drvdata(card);
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
struct snd_soc_component *component = codec_dai->component;
struct snd_jack *jack;
int rval;
rval = snd_soc_card_jack_new(card, "HDMI Jack", SND_JACK_LINEOUT,
&pdata->hdmi_jack);
if (rval < 0) {
dev_err(card->dev, "Unable to add HDMI Jack\n");
return rval;
}
jack = pdata->hdmi_jack.jack;
jack->private_data = component;
jack->private_free = sc7280_jack_free;
return snd_soc_component_set_jack(component, &pdata->hdmi_jack, NULL);
}
static int sc7280_rt5682_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
struct snd_soc_card *card = rtd->card;
struct sc7280_snd_data *data = snd_soc_card_get_drvdata(card);
int ret;
if (++data->pri_mi2s_clk_count == 1) {
snd_soc_dai_set_sysclk(cpu_dai,
LPASS_MCLK0,
DEFAULT_MCLK_RATE,
SNDRV_PCM_STREAM_PLAYBACK);
}
snd_soc_dai_set_fmt(codec_dai,
SND_SOC_DAIFMT_CBC_CFC |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_I2S);
ret = snd_soc_dai_set_pll(codec_dai, RT5682S_PLL2, RT5682S_PLL_S_MCLK,
DEFAULT_MCLK_RATE, RT5682_PLL_FREQ);
if (ret) {
dev_err(rtd->dev, "can't set codec pll: %d\n", ret);
return ret;
}
ret = snd_soc_dai_set_sysclk(codec_dai, RT5682S_SCLK_S_PLL2,
RT5682_PLL_FREQ,
SND_SOC_CLOCK_IN);
if (ret) {
dev_err(rtd->dev, "snd_soc_dai_set_sysclk err = %d\n",
ret);
return ret;
}
return 0;
}
static int sc7280_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
switch (cpu_dai->id) {
case MI2S_PRIMARY:
case LPASS_CDC_DMA_TX3:
case TX_CODEC_DMA_TX_3:
return sc7280_headset_init(rtd);
case LPASS_CDC_DMA_RX0:
case LPASS_CDC_DMA_VA_TX0:
case MI2S_SECONDARY:
case RX_CODEC_DMA_RX_0:
case SECONDARY_MI2S_RX:
case VA_CODEC_DMA_TX_0:
return 0;
case LPASS_DP_RX:
return sc7280_hdmi_init(rtd);
default:
dev_err(rtd->dev, "%s: invalid dai id 0x%x\n", __func__, cpu_dai->id);
}
return -EINVAL;
}
static int sc7280_snd_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *codec_dai;
const struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct sc7280_snd_data *pdata = snd_soc_card_get_drvdata(rtd->card);
struct sdw_stream_runtime *sruntime;
int i;
if (!rtd->dai_link->no_pcm) {
snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_CHANNELS, 2, 2);
snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_RATE, 48000, 48000);
}
switch (cpu_dai->id) {
case LPASS_CDC_DMA_TX3:
case LPASS_CDC_DMA_RX0:
case RX_CODEC_DMA_RX_0:
case SECONDARY_MI2S_RX:
case TX_CODEC_DMA_TX_3:
case VA_CODEC_DMA_TX_0:
for_each_rtd_codec_dais(rtd, i, codec_dai) {
sruntime = snd_soc_dai_get_stream(codec_dai, substream->stream);
if (sruntime != ERR_PTR(-ENOTSUPP))
pdata->sruntime[cpu_dai->id] = sruntime;
}
break;
}
return 0;
}
static int sc7280_snd_swr_prepare(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
const struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct sc7280_snd_data *data = snd_soc_card_get_drvdata(rtd->card);
struct sdw_stream_runtime *sruntime = data->sruntime[cpu_dai->id];
int ret;
if (!sruntime)
return 0;
if (data->stream_prepared[cpu_dai->id]) {
sdw_disable_stream(sruntime);
sdw_deprepare_stream(sruntime);
data->stream_prepared[cpu_dai->id] = false;
}
ret = sdw_prepare_stream(sruntime);
if (ret)
return ret;
ret = sdw_enable_stream(sruntime);
if (ret) {
sdw_deprepare_stream(sruntime);
return ret;
}
data->stream_prepared[cpu_dai->id] = true;
return ret;
}
static int sc7280_snd_prepare(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
const struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
switch (cpu_dai->id) {
case LPASS_CDC_DMA_RX0:
case LPASS_CDC_DMA_TX3:
case RX_CODEC_DMA_RX_0:
case TX_CODEC_DMA_TX_3:
case VA_CODEC_DMA_TX_0:
return sc7280_snd_swr_prepare(substream);
default:
break;
}
return 0;
}
static int sc7280_snd_hw_free(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct sc7280_snd_data *data = snd_soc_card_get_drvdata(rtd->card);
const struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct sdw_stream_runtime *sruntime = data->sruntime[cpu_dai->id];
switch (cpu_dai->id) {
case LPASS_CDC_DMA_RX0:
case LPASS_CDC_DMA_TX3:
case RX_CODEC_DMA_RX_0:
case TX_CODEC_DMA_TX_3:
case VA_CODEC_DMA_TX_0:
if (sruntime && data->stream_prepared[cpu_dai->id]) {
sdw_disable_stream(sruntime);
sdw_deprepare_stream(sruntime);
data->stream_prepared[cpu_dai->id] = false;
}
break;
default:
break;
}
return 0;
}
static void sc7280_snd_shutdown(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_card *card = rtd->card;
struct sc7280_snd_data *data = snd_soc_card_get_drvdata(card);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
switch (cpu_dai->id) {
case MI2S_PRIMARY:
if (--data->pri_mi2s_clk_count == 0) {
snd_soc_dai_set_sysclk(cpu_dai,
LPASS_MCLK0,
0,
SNDRV_PCM_STREAM_PLAYBACK);
}
break;
case SECONDARY_MI2S_RX:
snd_soc_dai_set_sysclk(cpu_dai, Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
0, SNDRV_PCM_STREAM_PLAYBACK);
break;
default:
break;
}
}
static int sc7280_snd_startup(struct snd_pcm_substream *substream)
{
unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
unsigned int codec_dai_fmt = SND_SOC_DAIFMT_CBS_CFS;
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
int ret = 0;
switch (cpu_dai->id) {
case MI2S_PRIMARY:
ret = sc7280_rt5682_init(rtd);
break;
case SECONDARY_MI2S_RX:
codec_dai_fmt |= SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_I2S;
snd_soc_dai_set_sysclk(cpu_dai, Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
MI2S_BCLK_RATE, SNDRV_PCM_STREAM_PLAYBACK);
snd_soc_dai_set_fmt(cpu_dai, fmt);
snd_soc_dai_set_fmt(codec_dai, codec_dai_fmt);
break;
default:
break;
}
return ret;
}
static const struct snd_soc_ops sc7280_ops = {
.startup = sc7280_snd_startup,
.hw_params = sc7280_snd_hw_params,
.hw_free = sc7280_snd_hw_free,
.prepare = sc7280_snd_prepare,
.shutdown = sc7280_snd_shutdown,
};
static const struct snd_soc_dapm_widget sc7280_snd_widgets[] = {
SND_SOC_DAPM_HP("Headphone Jack", NULL),
SND_SOC_DAPM_MIC("Headset Mic", NULL),
};
static const struct snd_kcontrol_new sc7280_snd_controls[] = {
SOC_DAPM_PIN_SWITCH("Headphone Jack"),
SOC_DAPM_PIN_SWITCH("Headset Mic"),
};
static int sc7280_snd_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
struct snd_pcm_hw_params *params)
{
struct snd_interval *rate = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
struct snd_interval *channels = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
rate->min = rate->max = 48000;
channels->min = channels->max = 2;
snd_mask_set_format(fmt, SNDRV_PCM_FORMAT_S16_LE);
return 0;
}
static int sc7280_snd_platform_probe(struct platform_device *pdev)
{
struct snd_soc_card *card;
struct sc7280_snd_data *data;
struct device *dev = &pdev->dev;
struct snd_soc_dai_link *link;
int ret, i;
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
card = &data->card;
snd_soc_card_set_drvdata(card, data);
card->owner = THIS_MODULE;
card->driver_name = "SC7280";
card->dev = dev;
card->dapm_widgets = sc7280_snd_widgets;
card->num_dapm_widgets = ARRAY_SIZE(sc7280_snd_widgets);
card->controls = sc7280_snd_controls;
card->num_controls = ARRAY_SIZE(sc7280_snd_controls);
ret = qcom_snd_parse_of(card);
if (ret)
return ret;
for_each_card_prelinks(card, i, link) {
link->init = sc7280_init;
link->ops = &sc7280_ops;
if (link->no_pcm == 1)
link->be_hw_params_fixup = sc7280_snd_be_hw_params_fixup;
}
return devm_snd_soc_register_card(dev, card);
}
static const struct of_device_id sc7280_snd_device_id[] = {
{ .compatible = "google,sc7280-herobrine" },
{}
};
MODULE_DEVICE_TABLE(of, sc7280_snd_device_id);
static struct platform_driver sc7280_snd_driver = {
.probe = sc7280_snd_platform_probe,
.driver = {
.name = "msm-snd-sc7280",
.of_match_table = sc7280_snd_device_id,
.pm = &snd_soc_pm_ops,
},
};
module_platform_driver(sc7280_snd_driver);
MODULE_DESCRIPTION("sc7280 ASoC Machine Driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/qcom/sc7280.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2020, The Linux Foundation. All rights reserved.
//
// sc7180.c -- ALSA SoC Machine driver for SC7180
#include <dt-bindings/sound/sc7180-lpass.h>
#include <linux/gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <sound/core.h>
#include <sound/jack.h>
#include <sound/pcm.h>
#include <sound/soc.h>
#include <uapi/linux/input-event-codes.h>
#include "../codecs/rt5682.h"
#include "../codecs/rt5682s.h"
#include "common.h"
#include "lpass.h"
#define DEFAULT_MCLK_RATE 19200000
#define RT5682_PLL1_FREQ (48000 * 512)
#define DRIVER_NAME "SC7180"
struct sc7180_snd_data {
struct snd_soc_card card;
u32 pri_mi2s_clk_count;
struct snd_soc_jack hs_jack;
struct snd_soc_jack hdmi_jack;
struct gpio_desc *dmic_sel;
int dmic_switch;
};
static void sc7180_jack_free(struct snd_jack *jack)
{
struct snd_soc_component *component = jack->private_data;
snd_soc_component_set_jack(component, NULL, NULL);
}
static struct snd_soc_jack_pin sc7180_jack_pins[] = {
{
.pin = "Headphone Jack",
.mask = SND_JACK_HEADPHONE,
},
{
.pin = "Headset Mic",
.mask = SND_JACK_MICROPHONE,
},
};
static int sc7180_headset_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_card *card = rtd->card;
struct sc7180_snd_data *pdata = snd_soc_card_get_drvdata(card);
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
struct snd_soc_component *component = codec_dai->component;
struct snd_jack *jack;
int rval;
rval = snd_soc_card_jack_new_pins(card, "Headset Jack",
SND_JACK_HEADSET |
SND_JACK_HEADPHONE |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3,
&pdata->hs_jack,
sc7180_jack_pins,
ARRAY_SIZE(sc7180_jack_pins));
if (rval < 0) {
dev_err(card->dev, "Unable to add Headset Jack\n");
return rval;
}
jack = pdata->hs_jack.jack;
snd_jack_set_key(jack, SND_JACK_BTN_0, KEY_PLAYPAUSE);
snd_jack_set_key(jack, SND_JACK_BTN_1, KEY_VOICECOMMAND);
snd_jack_set_key(jack, SND_JACK_BTN_2, KEY_VOLUMEUP);
snd_jack_set_key(jack, SND_JACK_BTN_3, KEY_VOLUMEDOWN);
jack->private_data = component;
jack->private_free = sc7180_jack_free;
return snd_soc_component_set_jack(component, &pdata->hs_jack, NULL);
}
static int sc7180_hdmi_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_card *card = rtd->card;
struct sc7180_snd_data *pdata = snd_soc_card_get_drvdata(card);
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
struct snd_soc_component *component = codec_dai->component;
struct snd_jack *jack;
int rval;
rval = snd_soc_card_jack_new(
card, "HDMI Jack",
SND_JACK_LINEOUT,
&pdata->hdmi_jack);
if (rval < 0) {
dev_err(card->dev, "Unable to add HDMI Jack\n");
return rval;
}
jack = pdata->hdmi_jack.jack;
jack->private_data = component;
jack->private_free = sc7180_jack_free;
return snd_soc_component_set_jack(component, &pdata->hdmi_jack, NULL);
}
static int sc7180_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
switch (cpu_dai->id) {
case MI2S_PRIMARY:
return sc7180_headset_init(rtd);
case MI2S_SECONDARY:
return 0;
case LPASS_DP_RX:
return sc7180_hdmi_init(rtd);
default:
dev_err(rtd->dev, "%s: invalid dai id 0x%x\n", __func__,
cpu_dai->id);
return -EINVAL;
}
return 0;
}
static int sc7180_snd_startup(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_card *card = rtd->card;
struct sc7180_snd_data *data = snd_soc_card_get_drvdata(card);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
int pll_id, pll_source, pll_in, pll_out, clk_id, ret;
if (!strcmp(codec_dai->name, "rt5682-aif1")) {
pll_source = RT5682_PLL1_S_MCLK;
pll_id = 0;
clk_id = RT5682_SCLK_S_PLL1;
pll_out = RT5682_PLL1_FREQ;
pll_in = DEFAULT_MCLK_RATE;
} else if (!strcmp(codec_dai->name, "rt5682s-aif1")) {
pll_source = RT5682S_PLL_S_MCLK;
pll_id = RT5682S_PLL2;
clk_id = RT5682S_SCLK_S_PLL2;
pll_out = RT5682_PLL1_FREQ;
pll_in = DEFAULT_MCLK_RATE;
}
switch (cpu_dai->id) {
case MI2S_PRIMARY:
if (++data->pri_mi2s_clk_count == 1) {
snd_soc_dai_set_sysclk(cpu_dai,
LPASS_MCLK0,
DEFAULT_MCLK_RATE,
SNDRV_PCM_STREAM_PLAYBACK);
}
snd_soc_dai_set_fmt(codec_dai,
SND_SOC_DAIFMT_BC_FC |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_I2S);
/* Configure PLL1 for codec */
ret = snd_soc_dai_set_pll(codec_dai, pll_id, pll_source,
pll_in, pll_out);
if (ret) {
dev_err(rtd->dev, "can't set codec pll: %d\n", ret);
return ret;
}
/* Configure sysclk for codec */
ret = snd_soc_dai_set_sysclk(codec_dai, clk_id, pll_out,
SND_SOC_CLOCK_IN);
if (ret)
dev_err(rtd->dev, "snd_soc_dai_set_sysclk err = %d\n",
ret);
break;
case MI2S_SECONDARY:
break;
case LPASS_DP_RX:
break;
default:
dev_err(rtd->dev, "%s: invalid dai id 0x%x\n", __func__,
cpu_dai->id);
return -EINVAL;
}
return 0;
}
static int dmic_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kcontrol);
struct sc7180_snd_data *data = snd_soc_card_get_drvdata(dapm->card);
ucontrol->value.integer.value[0] = data->dmic_switch;
return 0;
}
static int dmic_set(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kcontrol);
struct sc7180_snd_data *data = snd_soc_card_get_drvdata(dapm->card);
data->dmic_switch = ucontrol->value.integer.value[0];
gpiod_set_value(data->dmic_sel, data->dmic_switch);
return 0;
}
static void sc7180_snd_shutdown(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_card *card = rtd->card;
struct sc7180_snd_data *data = snd_soc_card_get_drvdata(card);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
switch (cpu_dai->id) {
case MI2S_PRIMARY:
if (--data->pri_mi2s_clk_count == 0) {
snd_soc_dai_set_sysclk(cpu_dai,
LPASS_MCLK0,
0,
SNDRV_PCM_STREAM_PLAYBACK);
}
break;
case MI2S_SECONDARY:
break;
case LPASS_DP_RX:
break;
default:
dev_err(rtd->dev, "%s: invalid dai id 0x%x\n", __func__,
cpu_dai->id);
break;
}
}
static int sc7180_adau7002_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
switch (cpu_dai->id) {
case MI2S_PRIMARY:
return 0;
case MI2S_SECONDARY:
return 0;
case LPASS_DP_RX:
return sc7180_hdmi_init(rtd);
default:
dev_err(rtd->dev, "%s: invalid dai id 0x%x\n", __func__,
cpu_dai->id);
return -EINVAL;
}
return 0;
}
static int sc7180_adau7002_snd_startup(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
struct snd_pcm_runtime *runtime = substream->runtime;
switch (cpu_dai->id) {
case MI2S_PRIMARY:
snd_soc_dai_set_fmt(codec_dai,
SND_SOC_DAIFMT_CBS_CFS |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_I2S);
runtime->hw.formats = SNDRV_PCM_FMTBIT_S32_LE;
snd_pcm_hw_constraint_msbits(runtime, 0, 32, 32);
break;
case MI2S_SECONDARY:
break;
case LPASS_DP_RX:
break;
default:
dev_err(rtd->dev, "%s: invalid dai id 0x%x\n", __func__,
cpu_dai->id);
return -EINVAL;
}
return 0;
}
static const struct snd_soc_ops sc7180_ops = {
.startup = sc7180_snd_startup,
.shutdown = sc7180_snd_shutdown,
};
static const struct snd_soc_ops sc7180_adau7002_ops = {
.startup = sc7180_adau7002_snd_startup,
};
static const struct snd_soc_dapm_widget sc7180_snd_widgets[] = {
SND_SOC_DAPM_HP("Headphone Jack", NULL),
SND_SOC_DAPM_MIC("Headset Mic", NULL),
};
static const struct snd_kcontrol_new sc7180_snd_controls[] = {
SOC_DAPM_PIN_SWITCH("Headphone Jack"),
SOC_DAPM_PIN_SWITCH("Headset Mic"),
};
static const struct snd_soc_dapm_widget sc7180_adau7002_snd_widgets[] = {
SND_SOC_DAPM_MIC("DMIC", NULL),
};
static const char * const dmic_mux_text[] = {
"Front Mic",
"Rear Mic",
};
static SOC_ENUM_SINGLE_DECL(sc7180_dmic_enum,
SND_SOC_NOPM, 0, dmic_mux_text);
static const struct snd_kcontrol_new sc7180_dmic_mux_control =
SOC_DAPM_ENUM_EXT("DMIC Select Mux", sc7180_dmic_enum,
dmic_get, dmic_set);
static const struct snd_soc_dapm_widget sc7180_snd_dual_mic_widgets[] = {
SND_SOC_DAPM_HP("Headphone Jack", NULL),
SND_SOC_DAPM_MIC("Headset Mic", NULL),
SND_SOC_DAPM_MIC("DMIC", NULL),
SND_SOC_DAPM_MUX("Dmic Mux", SND_SOC_NOPM, 0, 0, &sc7180_dmic_mux_control),
};
static const struct snd_kcontrol_new sc7180_snd_dual_mic_controls[] = {
SOC_DAPM_PIN_SWITCH("Headphone Jack"),
SOC_DAPM_PIN_SWITCH("Headset Mic"),
};
static const struct snd_soc_dapm_route sc7180_snd_dual_mic_audio_route[] = {
{"Dmic Mux", "Front Mic", "DMIC"},
{"Dmic Mux", "Rear Mic", "DMIC"},
};
static int sc7180_snd_platform_probe(struct platform_device *pdev)
{
struct snd_soc_card *card;
struct sc7180_snd_data *data;
struct device *dev = &pdev->dev;
struct snd_soc_dai_link *link;
int ret;
int i;
bool no_headphone = false;
/* Allocate the private data */
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
card = &data->card;
snd_soc_card_set_drvdata(card, data);
card->owner = THIS_MODULE;
card->driver_name = DRIVER_NAME;
card->dev = dev;
card->dapm_widgets = sc7180_snd_widgets;
card->num_dapm_widgets = ARRAY_SIZE(sc7180_snd_widgets);
card->controls = sc7180_snd_controls;
card->num_controls = ARRAY_SIZE(sc7180_snd_controls);
if (of_property_read_bool(dev->of_node, "dmic-gpios")) {
card->dapm_widgets = sc7180_snd_dual_mic_widgets,
card->num_dapm_widgets = ARRAY_SIZE(sc7180_snd_dual_mic_widgets),
card->controls = sc7180_snd_dual_mic_controls,
card->num_controls = ARRAY_SIZE(sc7180_snd_dual_mic_controls),
card->dapm_routes = sc7180_snd_dual_mic_audio_route,
card->num_dapm_routes = ARRAY_SIZE(sc7180_snd_dual_mic_audio_route),
data->dmic_sel = devm_gpiod_get(&pdev->dev, "dmic", GPIOD_OUT_LOW);
if (IS_ERR(data->dmic_sel)) {
dev_err(&pdev->dev, "DMIC gpio failed err=%ld\n", PTR_ERR(data->dmic_sel));
return PTR_ERR(data->dmic_sel);
}
}
if (of_device_is_compatible(dev->of_node, "google,sc7180-coachz")) {
no_headphone = true;
card->dapm_widgets = sc7180_adau7002_snd_widgets;
card->num_dapm_widgets = ARRAY_SIZE(sc7180_adau7002_snd_widgets);
}
ret = qcom_snd_parse_of(card);
if (ret)
return ret;
for_each_card_prelinks(card, i, link) {
if (no_headphone) {
link->ops = &sc7180_adau7002_ops;
link->init = sc7180_adau7002_init;
} else {
link->ops = &sc7180_ops;
link->init = sc7180_init;
}
}
return devm_snd_soc_register_card(dev, card);
}
static const struct of_device_id sc7180_snd_device_id[] = {
{.compatible = "google,sc7180-trogdor"},
{.compatible = "google,sc7180-coachz"},
{},
};
MODULE_DEVICE_TABLE(of, sc7180_snd_device_id);
static struct platform_driver sc7180_snd_driver = {
.probe = sc7180_snd_platform_probe,
.driver = {
.name = "msm-snd-sc7180",
.of_match_table = sc7180_snd_device_id,
.pm = &snd_soc_pm_ops,
},
};
module_platform_driver(sc7180_snd_driver);
MODULE_DESCRIPTION("sc7180 ASoC Machine Driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/qcom/sc7180.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2022, Linaro Limited
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of_device.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/pcm.h>
#include <linux/soundwire/sdw.h>
#include <sound/jack.h>
#include <linux/input-event-codes.h>
#include "qdsp6/q6afe.h"
#include "common.h"
#include "sdw.h"
#define DRIVER_NAME "sc8280xp"
struct sc8280xp_snd_data {
bool stream_prepared[AFE_PORT_MAX];
struct snd_soc_card *card;
struct sdw_stream_runtime *sruntime[AFE_PORT_MAX];
struct snd_soc_jack jack;
bool jack_setup;
};
static int sc8280xp_snd_init(struct snd_soc_pcm_runtime *rtd)
{
struct sc8280xp_snd_data *data = snd_soc_card_get_drvdata(rtd->card);
return qcom_snd_wcd_jack_setup(rtd, &data->jack, &data->jack_setup);
}
static int sc8280xp_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
struct snd_pcm_hw_params *params)
{
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct snd_interval *rate = hw_param_interval(params,
SNDRV_PCM_HW_PARAM_RATE);
struct snd_interval *channels = hw_param_interval(params,
SNDRV_PCM_HW_PARAM_CHANNELS);
rate->min = rate->max = 48000;
channels->min = 2;
channels->max = 2;
switch (cpu_dai->id) {
case TX_CODEC_DMA_TX_0:
case TX_CODEC_DMA_TX_1:
case TX_CODEC_DMA_TX_2:
case TX_CODEC_DMA_TX_3:
channels->min = 1;
break;
default:
break;
}
return 0;
}
static int sc8280xp_snd_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct sc8280xp_snd_data *pdata = snd_soc_card_get_drvdata(rtd->card);
return qcom_snd_sdw_hw_params(substream, params, &pdata->sruntime[cpu_dai->id]);
}
static int sc8280xp_snd_prepare(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct sc8280xp_snd_data *data = snd_soc_card_get_drvdata(rtd->card);
struct sdw_stream_runtime *sruntime = data->sruntime[cpu_dai->id];
return qcom_snd_sdw_prepare(substream, sruntime,
&data->stream_prepared[cpu_dai->id]);
}
static int sc8280xp_snd_hw_free(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct sc8280xp_snd_data *data = snd_soc_card_get_drvdata(rtd->card);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct sdw_stream_runtime *sruntime = data->sruntime[cpu_dai->id];
return qcom_snd_sdw_hw_free(substream, sruntime,
&data->stream_prepared[cpu_dai->id]);
}
static const struct snd_soc_ops sc8280xp_be_ops = {
.hw_params = sc8280xp_snd_hw_params,
.hw_free = sc8280xp_snd_hw_free,
.prepare = sc8280xp_snd_prepare,
};
static void sc8280xp_add_be_ops(struct snd_soc_card *card)
{
struct snd_soc_dai_link *link;
int i;
for_each_card_prelinks(card, i, link) {
if (link->no_pcm == 1) {
link->init = sc8280xp_snd_init;
link->be_hw_params_fixup = sc8280xp_be_hw_params_fixup;
link->ops = &sc8280xp_be_ops;
}
}
}
static int sc8280xp_platform_probe(struct platform_device *pdev)
{
struct snd_soc_card *card;
struct sc8280xp_snd_data *data;
struct device *dev = &pdev->dev;
int ret;
card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
if (!card)
return -ENOMEM;
card->owner = THIS_MODULE;
/* Allocate the private data */
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
card->dev = dev;
dev_set_drvdata(dev, card);
snd_soc_card_set_drvdata(card, data);
ret = qcom_snd_parse_of(card);
if (ret)
return ret;
card->driver_name = DRIVER_NAME;
sc8280xp_add_be_ops(card);
return devm_snd_soc_register_card(dev, card);
}
static const struct of_device_id snd_sc8280xp_dt_match[] = {
{.compatible = "qcom,sc8280xp-sndcard",},
{}
};
MODULE_DEVICE_TABLE(of, snd_sc8280xp_dt_match);
static struct platform_driver snd_sc8280xp_driver = {
.probe = sc8280xp_platform_probe,
.driver = {
.name = "snd-sc8280xp",
.of_match_table = snd_sc8280xp_dt_match,
},
};
module_platform_driver(snd_sc8280xp_driver);
MODULE_AUTHOR("Srinivas Kandagatla <[email protected]");
MODULE_DESCRIPTION("SC8280XP ASoC Machine Driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/qcom/sc8280xp.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2020 The Linux Foundation. All rights reserved.
*
* lpass-hdmi.c -- ALSA SoC HDMI-CPU DAI driver for QTi LPASS HDMI
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <sound/pcm_params.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include <dt-bindings/sound/sc7180-lpass.h>
#include "lpass-lpaif-reg.h"
#include "lpass.h"
static int lpass_hdmi_daiops_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
snd_pcm_format_t format = params_format(params);
unsigned int rate = params_rate(params);
unsigned int channels = params_channels(params);
unsigned int ret;
int bitwidth;
unsigned int word_length;
unsigned int ch_sts_buf0;
unsigned int ch_sts_buf1;
unsigned int data_format;
unsigned int sampling_freq;
unsigned int ch = 0;
struct lpass_dp_metadata_ctl *meta_ctl = drvdata->meta_ctl;
struct lpass_sstream_ctl *sstream_ctl = drvdata->sstream_ctl;
bitwidth = snd_pcm_format_width(format);
if (bitwidth < 0) {
dev_err(dai->dev, "%s invalid bit width given : %d\n",
__func__, bitwidth);
return bitwidth;
}
switch (bitwidth) {
case 16:
word_length = LPASS_DP_AUDIO_BITWIDTH16;
break;
case 24:
word_length = LPASS_DP_AUDIO_BITWIDTH24;
break;
default:
dev_err(dai->dev, "%s invalid bit width given : %d\n",
__func__, bitwidth);
return -EINVAL;
}
switch (rate) {
case 32000:
sampling_freq = LPASS_SAMPLING_FREQ32;
break;
case 44100:
sampling_freq = LPASS_SAMPLING_FREQ44;
break;
case 48000:
sampling_freq = LPASS_SAMPLING_FREQ48;
break;
default:
dev_err(dai->dev, "%s invalid bit width given : %d\n",
__func__, bitwidth);
return -EINVAL;
}
data_format = LPASS_DATA_FORMAT_LINEAR;
ch_sts_buf0 = (((data_format << LPASS_DATA_FORMAT_SHIFT) & LPASS_DATA_FORMAT_MASK)
| ((sampling_freq << LPASS_FREQ_BIT_SHIFT) & LPASS_FREQ_BIT_MASK));
ch_sts_buf1 = (word_length) & LPASS_WORDLENGTH_MASK;
ret = regmap_field_write(drvdata->tx_ctl->soft_reset, LPASS_TX_CTL_RESET);
if (ret)
return ret;
ret = regmap_field_write(drvdata->tx_ctl->soft_reset, LPASS_TX_CTL_CLEAR);
if (ret)
return ret;
ret = regmap_field_write(drvdata->hdmitx_legacy_en, LPASS_HDMITX_LEGACY_DISABLE);
if (ret)
return ret;
ret = regmap_field_write(drvdata->hdmitx_parity_calc_en, HDMITX_PARITY_CALC_EN);
if (ret)
return ret;
ret = regmap_field_write(drvdata->vbit_ctl->replace_vbit, REPLACE_VBIT);
if (ret)
return ret;
ret = regmap_field_write(drvdata->vbit_ctl->vbit_stream, LINEAR_PCM_DATA);
if (ret)
return ret;
ret = regmap_field_write(drvdata->hdmitx_ch_msb[0], ch_sts_buf1);
if (ret)
return ret;
ret = regmap_field_write(drvdata->hdmitx_ch_lsb[0], ch_sts_buf0);
if (ret)
return ret;
ret = regmap_field_write(drvdata->hdmi_tx_dmactl[0]->use_hw_chs, HW_MODE);
if (ret)
return ret;
ret = regmap_field_write(drvdata->hdmi_tx_dmactl[0]->hw_chs_sel, SW_MODE);
if (ret)
return ret;
ret = regmap_field_write(drvdata->hdmi_tx_dmactl[0]->use_hw_usr, HW_MODE);
if (ret)
return ret;
ret = regmap_field_write(drvdata->hdmi_tx_dmactl[0]->hw_usr_sel, SW_MODE);
if (ret)
return ret;
ret = regmap_field_write(meta_ctl->mute, LPASS_MUTE_ENABLE);
if (ret)
return ret;
ret = regmap_field_write(meta_ctl->as_sdp_cc, channels - 1);
if (ret)
return ret;
ret = regmap_field_write(meta_ctl->as_sdp_ct, LPASS_META_DEFAULT_VAL);
if (ret)
return ret;
ret = regmap_field_write(meta_ctl->aif_db4, LPASS_META_DEFAULT_VAL);
if (ret)
return ret;
ret = regmap_field_write(meta_ctl->frequency, sampling_freq);
if (ret)
return ret;
ret = regmap_field_write(meta_ctl->mst_index, LPASS_META_DEFAULT_VAL);
if (ret)
return ret;
ret = regmap_field_write(meta_ctl->dptx_index, LPASS_META_DEFAULT_VAL);
if (ret)
return ret;
ret = regmap_field_write(sstream_ctl->sstream_en, LPASS_SSTREAM_DISABLE);
if (ret)
return ret;
ret = regmap_field_write(sstream_ctl->dma_sel, ch);
if (ret)
return ret;
ret = regmap_field_write(sstream_ctl->auto_bbit_en, LPASS_SSTREAM_DEFAULT_ENABLE);
if (ret)
return ret;
ret = regmap_field_write(sstream_ctl->layout, LPASS_SSTREAM_DEFAULT_DISABLE);
if (ret)
return ret;
ret = regmap_field_write(sstream_ctl->layout_sp, LPASS_LAYOUT_SP_DEFAULT);
if (ret)
return ret;
ret = regmap_field_write(sstream_ctl->dp_audio, LPASS_SSTREAM_DEFAULT_ENABLE);
if (ret)
return ret;
ret = regmap_field_write(sstream_ctl->set_sp_on_en, LPASS_SSTREAM_DEFAULT_ENABLE);
if (ret)
return ret;
ret = regmap_field_write(sstream_ctl->dp_sp_b_hw_en, LPASS_SSTREAM_DEFAULT_ENABLE);
if (ret)
return ret;
ret = regmap_field_write(sstream_ctl->dp_staffing_en, LPASS_SSTREAM_DEFAULT_ENABLE);
return ret;
}
static int lpass_hdmi_daiops_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
int ret;
struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
ret = regmap_field_write(drvdata->sstream_ctl->sstream_en, LPASS_SSTREAM_ENABLE);
if (ret)
return ret;
ret = regmap_field_write(drvdata->meta_ctl->mute, LPASS_MUTE_DISABLE);
return ret;
}
static int lpass_hdmi_daiops_trigger(struct snd_pcm_substream *substream,
int cmd, struct snd_soc_dai *dai)
{
struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
struct lpass_dp_metadata_ctl *meta_ctl = drvdata->meta_ctl;
struct lpass_sstream_ctl *sstream_ctl = drvdata->sstream_ctl;
int ret = -EINVAL;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
ret = regmap_field_write(sstream_ctl->sstream_en, LPASS_SSTREAM_ENABLE);
if (ret)
return ret;
ret = regmap_field_write(meta_ctl->mute, LPASS_MUTE_DISABLE);
if (ret)
return ret;
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
ret = regmap_field_write(sstream_ctl->sstream_en, LPASS_SSTREAM_DISABLE);
if (ret)
return ret;
ret = regmap_field_write(meta_ctl->mute, LPASS_MUTE_ENABLE);
if (ret)
return ret;
ret = regmap_field_write(sstream_ctl->dp_audio, 0);
if (ret)
return ret;
break;
}
return ret;
}
const struct snd_soc_dai_ops asoc_qcom_lpass_hdmi_dai_ops = {
.hw_params = lpass_hdmi_daiops_hw_params,
.prepare = lpass_hdmi_daiops_prepare,
.trigger = lpass_hdmi_daiops_trigger,
};
EXPORT_SYMBOL_GPL(asoc_qcom_lpass_hdmi_dai_ops);
MODULE_DESCRIPTION("QTi LPASS HDMI Driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/qcom/lpass-hdmi.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of_device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/jack.h>
#include <sound/soc.h>
#include <linux/soundwire/sdw.h>
#include <uapi/linux/input-event-codes.h>
#include "common.h"
#include "qdsp6/q6afe.h"
#include "../codecs/rt5663.h"
#define DRIVER_NAME "sdm845"
#define DEFAULT_SAMPLE_RATE_48K 48000
#define DEFAULT_MCLK_RATE 24576000
#define TDM_BCLK_RATE 6144000
#define MI2S_BCLK_RATE 1536000
#define LEFT_SPK_TDM_TX_MASK 0x30
#define RIGHT_SPK_TDM_TX_MASK 0xC0
#define SPK_TDM_RX_MASK 0x03
#define NUM_TDM_SLOTS 8
#define SLIM_MAX_TX_PORTS 16
#define SLIM_MAX_RX_PORTS 13
#define WCD934X_DEFAULT_MCLK_RATE 9600000
struct sdm845_snd_data {
struct snd_soc_jack jack;
bool jack_setup;
bool slim_port_setup;
bool stream_prepared[AFE_PORT_MAX];
struct snd_soc_card *card;
uint32_t pri_mi2s_clk_count;
uint32_t sec_mi2s_clk_count;
uint32_t quat_tdm_clk_count;
struct sdw_stream_runtime *sruntime[AFE_PORT_MAX];
};
static struct snd_soc_jack_pin sdm845_jack_pins[] = {
{
.pin = "Headphone Jack",
.mask = SND_JACK_HEADPHONE,
},
{
.pin = "Headset Mic",
.mask = SND_JACK_MICROPHONE,
},
};
static unsigned int tdm_slot_offset[8] = {0, 4, 8, 12, 16, 20, 24, 28};
static int sdm845_slim_snd_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct snd_soc_dai *codec_dai;
struct sdm845_snd_data *pdata = snd_soc_card_get_drvdata(rtd->card);
u32 rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS];
struct sdw_stream_runtime *sruntime;
u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
int ret = 0, i;
for_each_rtd_codec_dais(rtd, i, codec_dai) {
sruntime = snd_soc_dai_get_stream(codec_dai,
substream->stream);
if (sruntime != ERR_PTR(-ENOTSUPP))
pdata->sruntime[cpu_dai->id] = sruntime;
ret = snd_soc_dai_get_channel_map(codec_dai,
&tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
if (ret != 0 && ret != -ENOTSUPP) {
pr_err("failed to get codec chan map, err:%d\n", ret);
return ret;
} else if (ret == -ENOTSUPP) {
/* Ignore unsupported */
continue;
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
ret = snd_soc_dai_set_channel_map(cpu_dai, 0, NULL,
rx_ch_cnt, rx_ch);
else
ret = snd_soc_dai_set_channel_map(cpu_dai, tx_ch_cnt,
tx_ch, 0, NULL);
}
return 0;
}
static int sdm845_tdm_snd_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct snd_soc_dai *codec_dai;
int ret = 0, j;
int channels, slot_width;
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
slot_width = 16;
break;
default:
dev_err(rtd->dev, "%s: invalid param format 0x%x\n",
__func__, params_format(params));
return -EINVAL;
}
channels = params_channels(params);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, 0x3,
8, slot_width);
if (ret < 0) {
dev_err(rtd->dev, "%s: failed to set tdm slot, err:%d\n",
__func__, ret);
goto end;
}
ret = snd_soc_dai_set_channel_map(cpu_dai, 0, NULL,
channels, tdm_slot_offset);
if (ret < 0) {
dev_err(rtd->dev, "%s: failed to set channel map, err:%d\n",
__func__, ret);
goto end;
}
} else {
ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0xf, 0,
8, slot_width);
if (ret < 0) {
dev_err(rtd->dev, "%s: failed to set tdm slot, err:%d\n",
__func__, ret);
goto end;
}
ret = snd_soc_dai_set_channel_map(cpu_dai, channels,
tdm_slot_offset, 0, NULL);
if (ret < 0) {
dev_err(rtd->dev, "%s: failed to set channel map, err:%d\n",
__func__, ret);
goto end;
}
}
for_each_rtd_codec_dais(rtd, j, codec_dai) {
if (!strcmp(codec_dai->component->name_prefix, "Left")) {
ret = snd_soc_dai_set_tdm_slot(
codec_dai, LEFT_SPK_TDM_TX_MASK,
SPK_TDM_RX_MASK, NUM_TDM_SLOTS,
slot_width);
if (ret < 0) {
dev_err(rtd->dev,
"DEV0 TDM slot err:%d\n", ret);
return ret;
}
}
if (!strcmp(codec_dai->component->name_prefix, "Right")) {
ret = snd_soc_dai_set_tdm_slot(
codec_dai, RIGHT_SPK_TDM_TX_MASK,
SPK_TDM_RX_MASK, NUM_TDM_SLOTS,
slot_width);
if (ret < 0) {
dev_err(rtd->dev,
"DEV1 TDM slot err:%d\n", ret);
return ret;
}
}
}
end:
return ret;
}
static int sdm845_snd_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
int ret = 0;
switch (cpu_dai->id) {
case PRIMARY_MI2S_RX:
case PRIMARY_MI2S_TX:
/*
* Use ASRC for internal clocks, as PLL rate isn't multiple
* of BCLK.
*/
rt5663_sel_asrc_clk_src(
codec_dai->component,
RT5663_DA_STEREO_FILTER | RT5663_AD_STEREO_FILTER,
RT5663_CLK_SEL_I2S1_ASRC);
ret = snd_soc_dai_set_sysclk(
codec_dai, RT5663_SCLK_S_MCLK, DEFAULT_MCLK_RATE,
SND_SOC_CLOCK_IN);
if (ret < 0)
dev_err(rtd->dev,
"snd_soc_dai_set_sysclk err = %d\n", ret);
break;
case QUATERNARY_TDM_RX_0:
case QUATERNARY_TDM_TX_0:
ret = sdm845_tdm_snd_hw_params(substream, params);
break;
case SLIMBUS_0_RX...SLIMBUS_6_TX:
ret = sdm845_slim_snd_hw_params(substream, params);
break;
case QUATERNARY_MI2S_RX:
break;
default:
pr_err("%s: invalid dai id 0x%x\n", __func__, cpu_dai->id);
break;
}
return ret;
}
static void sdm845_jack_free(struct snd_jack *jack)
{
struct snd_soc_component *component = jack->private_data;
snd_soc_component_set_jack(component, NULL, NULL);
}
static int sdm845_dai_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_component *component;
struct snd_soc_card *card = rtd->card;
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct sdm845_snd_data *pdata = snd_soc_card_get_drvdata(card);
struct snd_soc_dai_link *link = rtd->dai_link;
struct snd_jack *jack;
/*
* Codec SLIMBUS configuration
* RX1, RX2, RX3, RX4, RX5, RX6, RX7, RX8, RX9, RX10, RX11, RX12, RX13
* TX1, TX2, TX3, TX4, TX5, TX6, TX7, TX8, TX9, TX10, TX11, TX12, TX13
* TX14, TX15, TX16
*/
unsigned int rx_ch[SLIM_MAX_RX_PORTS] = {144, 145, 146, 147, 148, 149,
150, 151, 152, 153, 154, 155, 156};
unsigned int tx_ch[SLIM_MAX_TX_PORTS] = {128, 129, 130, 131, 132, 133,
134, 135, 136, 137, 138, 139,
140, 141, 142, 143};
int rval, i;
if (!pdata->jack_setup) {
rval = snd_soc_card_jack_new_pins(card, "Headset Jack",
SND_JACK_HEADSET |
SND_JACK_HEADPHONE |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3,
&pdata->jack,
sdm845_jack_pins,
ARRAY_SIZE(sdm845_jack_pins));
if (rval < 0) {
dev_err(card->dev, "Unable to add Headphone Jack\n");
return rval;
}
jack = pdata->jack.jack;
snd_jack_set_key(jack, SND_JACK_BTN_0, KEY_PLAYPAUSE);
snd_jack_set_key(jack, SND_JACK_BTN_1, KEY_VOICECOMMAND);
snd_jack_set_key(jack, SND_JACK_BTN_2, KEY_VOLUMEUP);
snd_jack_set_key(jack, SND_JACK_BTN_3, KEY_VOLUMEDOWN);
pdata->jack_setup = true;
}
switch (cpu_dai->id) {
case PRIMARY_MI2S_RX:
jack = pdata->jack.jack;
component = codec_dai->component;
jack->private_data = component;
jack->private_free = sdm845_jack_free;
rval = snd_soc_component_set_jack(component,
&pdata->jack, NULL);
if (rval != 0 && rval != -ENOTSUPP) {
dev_warn(card->dev, "Failed to set jack: %d\n", rval);
return rval;
}
break;
case SLIMBUS_0_RX...SLIMBUS_6_TX:
/* setting up wcd multiple times for slim port is redundant */
if (pdata->slim_port_setup || !link->no_pcm)
return 0;
for_each_rtd_codec_dais(rtd, i, codec_dai) {
rval = snd_soc_dai_set_channel_map(codec_dai,
ARRAY_SIZE(tx_ch),
tx_ch,
ARRAY_SIZE(rx_ch),
rx_ch);
if (rval != 0 && rval != -ENOTSUPP)
return rval;
snd_soc_dai_set_sysclk(codec_dai, 0,
WCD934X_DEFAULT_MCLK_RATE,
SNDRV_PCM_STREAM_PLAYBACK);
rval = snd_soc_component_set_jack(codec_dai->component,
&pdata->jack, NULL);
if (rval != 0 && rval != -ENOTSUPP) {
dev_warn(card->dev, "Failed to set jack: %d\n", rval);
return rval;
}
}
pdata->slim_port_setup = true;
break;
default:
break;
}
return 0;
}
static int sdm845_snd_startup(struct snd_pcm_substream *substream)
{
unsigned int fmt = SND_SOC_DAIFMT_BP_FP;
unsigned int codec_dai_fmt = SND_SOC_DAIFMT_BC_FC;
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_card *card = rtd->card;
struct sdm845_snd_data *data = snd_soc_card_get_drvdata(card);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
int j;
int ret;
switch (cpu_dai->id) {
case PRIMARY_MI2S_RX:
case PRIMARY_MI2S_TX:
codec_dai_fmt |= SND_SOC_DAIFMT_NB_NF;
if (++(data->pri_mi2s_clk_count) == 1) {
snd_soc_dai_set_sysclk(cpu_dai,
Q6AFE_LPASS_CLK_ID_MCLK_1,
DEFAULT_MCLK_RATE, SNDRV_PCM_STREAM_PLAYBACK);
snd_soc_dai_set_sysclk(cpu_dai,
Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
MI2S_BCLK_RATE, SNDRV_PCM_STREAM_PLAYBACK);
}
snd_soc_dai_set_fmt(cpu_dai, fmt);
snd_soc_dai_set_fmt(codec_dai, codec_dai_fmt);
break;
case SECONDARY_MI2S_TX:
codec_dai_fmt |= SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_I2S;
if (++(data->sec_mi2s_clk_count) == 1) {
snd_soc_dai_set_sysclk(cpu_dai,
Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
MI2S_BCLK_RATE, SNDRV_PCM_STREAM_CAPTURE);
}
snd_soc_dai_set_fmt(cpu_dai, fmt);
snd_soc_dai_set_fmt(codec_dai, codec_dai_fmt);
break;
case QUATERNARY_MI2S_RX:
snd_soc_dai_set_sysclk(cpu_dai,
Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
MI2S_BCLK_RATE, SNDRV_PCM_STREAM_PLAYBACK);
snd_soc_dai_set_fmt(cpu_dai, fmt);
break;
case QUATERNARY_TDM_RX_0:
case QUATERNARY_TDM_TX_0:
if (++(data->quat_tdm_clk_count) == 1) {
snd_soc_dai_set_sysclk(cpu_dai,
Q6AFE_LPASS_CLK_ID_QUAD_TDM_IBIT,
TDM_BCLK_RATE, SNDRV_PCM_STREAM_PLAYBACK);
}
codec_dai_fmt |= SND_SOC_DAIFMT_IB_NF | SND_SOC_DAIFMT_DSP_B;
for_each_rtd_codec_dais(rtd, j, codec_dai) {
if (!strcmp(codec_dai->component->name_prefix,
"Left")) {
ret = snd_soc_dai_set_fmt(
codec_dai, codec_dai_fmt);
if (ret < 0) {
dev_err(rtd->dev,
"Left TDM fmt err:%d\n", ret);
return ret;
}
}
if (!strcmp(codec_dai->component->name_prefix,
"Right")) {
ret = snd_soc_dai_set_fmt(
codec_dai, codec_dai_fmt);
if (ret < 0) {
dev_err(rtd->dev,
"Right TDM slot err:%d\n", ret);
return ret;
}
}
}
break;
case SLIMBUS_0_RX...SLIMBUS_6_TX:
break;
default:
pr_err("%s: invalid dai id 0x%x\n", __func__, cpu_dai->id);
break;
}
return 0;
}
static void sdm845_snd_shutdown(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_card *card = rtd->card;
struct sdm845_snd_data *data = snd_soc_card_get_drvdata(card);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
switch (cpu_dai->id) {
case PRIMARY_MI2S_RX:
case PRIMARY_MI2S_TX:
if (--(data->pri_mi2s_clk_count) == 0) {
snd_soc_dai_set_sysclk(cpu_dai,
Q6AFE_LPASS_CLK_ID_MCLK_1,
0, SNDRV_PCM_STREAM_PLAYBACK);
snd_soc_dai_set_sysclk(cpu_dai,
Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
0, SNDRV_PCM_STREAM_PLAYBACK);
}
break;
case SECONDARY_MI2S_TX:
if (--(data->sec_mi2s_clk_count) == 0) {
snd_soc_dai_set_sysclk(cpu_dai,
Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
0, SNDRV_PCM_STREAM_CAPTURE);
}
break;
case QUATERNARY_TDM_RX_0:
case QUATERNARY_TDM_TX_0:
if (--(data->quat_tdm_clk_count) == 0) {
snd_soc_dai_set_sysclk(cpu_dai,
Q6AFE_LPASS_CLK_ID_QUAD_TDM_IBIT,
0, SNDRV_PCM_STREAM_PLAYBACK);
}
break;
case SLIMBUS_0_RX...SLIMBUS_6_TX:
case QUATERNARY_MI2S_RX:
break;
default:
pr_err("%s: invalid dai id 0x%x\n", __func__, cpu_dai->id);
break;
}
}
static int sdm845_snd_prepare(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct sdm845_snd_data *data = snd_soc_card_get_drvdata(rtd->card);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct sdw_stream_runtime *sruntime = data->sruntime[cpu_dai->id];
int ret;
if (!sruntime)
return 0;
if (data->stream_prepared[cpu_dai->id]) {
sdw_disable_stream(sruntime);
sdw_deprepare_stream(sruntime);
data->stream_prepared[cpu_dai->id] = false;
}
ret = sdw_prepare_stream(sruntime);
if (ret)
return ret;
/**
* NOTE: there is a strict hw requirement about the ordering of port
* enables and actual WSA881x PA enable. PA enable should only happen
* after soundwire ports are enabled if not DC on the line is
* accumulated resulting in Click/Pop Noise
* PA enable/mute are handled as part of codec DAPM and digital mute.
*/
ret = sdw_enable_stream(sruntime);
if (ret) {
sdw_deprepare_stream(sruntime);
return ret;
}
data->stream_prepared[cpu_dai->id] = true;
return ret;
}
static int sdm845_snd_hw_free(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct sdm845_snd_data *data = snd_soc_card_get_drvdata(rtd->card);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct sdw_stream_runtime *sruntime = data->sruntime[cpu_dai->id];
if (sruntime && data->stream_prepared[cpu_dai->id]) {
sdw_disable_stream(sruntime);
sdw_deprepare_stream(sruntime);
data->stream_prepared[cpu_dai->id] = false;
}
return 0;
}
static const struct snd_soc_ops sdm845_be_ops = {
.hw_params = sdm845_snd_hw_params,
.hw_free = sdm845_snd_hw_free,
.prepare = sdm845_snd_prepare,
.startup = sdm845_snd_startup,
.shutdown = sdm845_snd_shutdown,
};
static int sdm845_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
struct snd_pcm_hw_params *params)
{
struct snd_interval *rate = hw_param_interval(params,
SNDRV_PCM_HW_PARAM_RATE);
struct snd_interval *channels = hw_param_interval(params,
SNDRV_PCM_HW_PARAM_CHANNELS);
struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
rate->min = rate->max = DEFAULT_SAMPLE_RATE_48K;
channels->min = channels->max = 2;
snd_mask_set_format(fmt, SNDRV_PCM_FORMAT_S16_LE);
return 0;
}
static const struct snd_soc_dapm_widget sdm845_snd_widgets[] = {
SND_SOC_DAPM_HP("Headphone Jack", NULL),
SND_SOC_DAPM_MIC("Headset Mic", NULL),
SND_SOC_DAPM_SPK("Left Spk", NULL),
SND_SOC_DAPM_SPK("Right Spk", NULL),
SND_SOC_DAPM_MIC("Int Mic", NULL),
};
static const struct snd_kcontrol_new sdm845_snd_controls[] = {
SOC_DAPM_PIN_SWITCH("Headphone Jack"),
SOC_DAPM_PIN_SWITCH("Headset Mic"),
};
static void sdm845_add_ops(struct snd_soc_card *card)
{
struct snd_soc_dai_link *link;
int i;
for_each_card_prelinks(card, i, link) {
if (link->no_pcm == 1) {
link->ops = &sdm845_be_ops;
link->be_hw_params_fixup = sdm845_be_hw_params_fixup;
}
link->init = sdm845_dai_init;
}
}
static int sdm845_snd_platform_probe(struct platform_device *pdev)
{
struct snd_soc_card *card;
struct sdm845_snd_data *data;
struct device *dev = &pdev->dev;
int ret;
card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
if (!card)
return -ENOMEM;
/* Allocate the private data */
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
card->driver_name = DRIVER_NAME;
card->dapm_widgets = sdm845_snd_widgets;
card->num_dapm_widgets = ARRAY_SIZE(sdm845_snd_widgets);
card->controls = sdm845_snd_controls;
card->num_controls = ARRAY_SIZE(sdm845_snd_controls);
card->dev = dev;
card->owner = THIS_MODULE;
dev_set_drvdata(dev, card);
ret = qcom_snd_parse_of(card);
if (ret)
return ret;
data->card = card;
snd_soc_card_set_drvdata(card, data);
sdm845_add_ops(card);
return devm_snd_soc_register_card(dev, card);
}
static const struct of_device_id sdm845_snd_device_id[] = {
{ .compatible = "qcom,sdm845-sndcard" },
/* Do not grow the list for compatible devices */
{ .compatible = "qcom,db845c-sndcard" },
{ .compatible = "lenovo,yoga-c630-sndcard" },
{},
};
MODULE_DEVICE_TABLE(of, sdm845_snd_device_id);
static struct platform_driver sdm845_snd_driver = {
.probe = sdm845_snd_platform_probe,
.driver = {
.name = "msm-snd-sdm845",
.of_match_table = sdm845_snd_device_id,
},
};
module_platform_driver(sdm845_snd_driver);
MODULE_DESCRIPTION("sdm845 ASoC Machine Driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/qcom/sdm845.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
*
* lpass-sc7180.c -- ALSA SoC platform-machine driver for QTi LPASS
*/
#include <linux/module.h>
#include <sound/pcm.h>
#include <sound/soc.h>
#include <linux/pm.h>
#include <dt-bindings/sound/sc7180-lpass.h>
#include "lpass-lpaif-reg.h"
#include "lpass.h"
static struct snd_soc_dai_driver sc7280_lpass_cpu_dai_driver[] = {
{
.id = MI2S_PRIMARY,
.name = "Primary MI2S",
.playback = {
.stream_name = "Primary Playback",
.formats = SNDRV_PCM_FMTBIT_S16,
.rates = SNDRV_PCM_RATE_48000,
.rate_min = 48000,
.rate_max = 48000,
.channels_min = 2,
.channels_max = 2,
},
.capture = {
.stream_name = "Primary Capture",
.formats = SNDRV_PCM_FMTBIT_S16 |
SNDRV_PCM_FMTBIT_S32,
.rates = SNDRV_PCM_RATE_48000,
.rate_min = 48000,
.rate_max = 48000,
.channels_min = 2,
.channels_max = 2,
},
.ops = &asoc_qcom_lpass_cpu_dai_ops,
}, {
.id = MI2S_SECONDARY,
.name = "Secondary MI2S",
.playback = {
.stream_name = "Secondary MI2S Playback",
.formats = SNDRV_PCM_FMTBIT_S16,
.rates = SNDRV_PCM_RATE_48000,
.rate_min = 48000,
.rate_max = 48000,
.channels_min = 2,
.channels_max = 2,
},
.ops = &asoc_qcom_lpass_cpu_dai_ops,
}, {
.id = LPASS_DP_RX,
.name = "Hdmi",
.playback = {
.stream_name = "DP Playback",
.formats = SNDRV_PCM_FMTBIT_S24,
.rates = SNDRV_PCM_RATE_48000,
.rate_min = 48000,
.rate_max = 48000,
.channels_min = 2,
.channels_max = 2,
},
.ops = &asoc_qcom_lpass_hdmi_dai_ops,
}, {
.id = LPASS_CDC_DMA_RX0,
.name = "CDC DMA RX",
.playback = {
.stream_name = "WCD Playback",
.formats = SNDRV_PCM_FMTBIT_S16,
.rates = SNDRV_PCM_RATE_48000,
.rate_min = 48000,
.rate_max = 48000,
.channels_min = 2,
.channels_max = 2,
},
.ops = &asoc_qcom_lpass_cdc_dma_dai_ops,
}, {
.id = LPASS_CDC_DMA_TX3,
.name = "CDC DMA TX",
.capture = {
.stream_name = "WCD Capture",
.formats = SNDRV_PCM_FMTBIT_S16,
.rates = SNDRV_PCM_RATE_48000,
.rate_min = 48000,
.rate_max = 48000,
.channels_min = 1,
.channels_max = 1,
},
.ops = &asoc_qcom_lpass_cdc_dma_dai_ops,
}, {
.id = LPASS_CDC_DMA_VA_TX0,
.name = "CDC DMA VA",
.capture = {
.stream_name = "DMIC Capture",
.formats = SNDRV_PCM_FMTBIT_S16,
.rates = SNDRV_PCM_RATE_48000,
.rate_min = 48000,
.rate_max = 48000,
.channels_min = 2,
.channels_max = 4,
},
.ops = &asoc_qcom_lpass_cdc_dma_dai_ops,
},
};
static int sc7280_lpass_alloc_dma_channel(struct lpass_data *drvdata,
int direction, unsigned int dai_id)
{
struct lpass_variant *v = drvdata->variant;
int chan = 0;
switch (dai_id) {
case MI2S_PRIMARY ... MI2S_QUINARY:
if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
chan = find_first_zero_bit(&drvdata->dma_ch_bit_map,
v->rdma_channels);
if (chan >= v->rdma_channels)
return -EBUSY;
} else {
chan = find_next_zero_bit(&drvdata->dma_ch_bit_map,
v->wrdma_channel_start +
v->wrdma_channels,
v->wrdma_channel_start);
if (chan >= v->wrdma_channel_start + v->wrdma_channels)
return -EBUSY;
}
set_bit(chan, &drvdata->dma_ch_bit_map);
break;
case LPASS_DP_RX:
chan = find_first_zero_bit(&drvdata->hdmi_dma_ch_bit_map,
v->hdmi_rdma_channels);
if (chan >= v->hdmi_rdma_channels)
return -EBUSY;
set_bit(chan, &drvdata->hdmi_dma_ch_bit_map);
break;
case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9:
chan = find_first_zero_bit(&drvdata->rxtx_dma_ch_bit_map,
v->rxtx_rdma_channels);
if (chan >= v->rxtx_rdma_channels)
return -EBUSY;
break;
case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8:
chan = find_next_zero_bit(&drvdata->rxtx_dma_ch_bit_map,
v->rxtx_wrdma_channel_start +
v->rxtx_wrdma_channels,
v->rxtx_wrdma_channel_start);
if (chan >= v->rxtx_wrdma_channel_start + v->rxtx_wrdma_channels)
return -EBUSY;
set_bit(chan, &drvdata->rxtx_dma_ch_bit_map);
break;
case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8:
chan = find_next_zero_bit(&drvdata->va_dma_ch_bit_map,
v->va_wrdma_channel_start +
v->va_wrdma_channels,
v->va_wrdma_channel_start);
if (chan >= v->va_wrdma_channel_start + v->va_wrdma_channels)
return -EBUSY;
set_bit(chan, &drvdata->va_dma_ch_bit_map);
break;
default:
break;
}
return chan;
}
static int sc7280_lpass_free_dma_channel(struct lpass_data *drvdata, int chan, unsigned int dai_id)
{
switch (dai_id) {
case MI2S_PRIMARY ... MI2S_QUINARY:
clear_bit(chan, &drvdata->dma_ch_bit_map);
break;
case LPASS_DP_RX:
clear_bit(chan, &drvdata->hdmi_dma_ch_bit_map);
break;
case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9:
case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8:
clear_bit(chan, &drvdata->rxtx_dma_ch_bit_map);
break;
case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8:
clear_bit(chan, &drvdata->va_dma_ch_bit_map);
break;
default:
break;
}
return 0;
}
static int sc7280_lpass_init(struct platform_device *pdev)
{
struct lpass_data *drvdata = platform_get_drvdata(pdev);
struct lpass_variant *variant = drvdata->variant;
struct device *dev = &pdev->dev;
int ret, i;
drvdata->clks = devm_kcalloc(dev, variant->num_clks,
sizeof(*drvdata->clks), GFP_KERNEL);
if (!drvdata->clks)
return -ENOMEM;
drvdata->num_clks = variant->num_clks;
for (i = 0; i < drvdata->num_clks; i++)
drvdata->clks[i].id = variant->clk_name[i];
ret = devm_clk_bulk_get(dev, drvdata->num_clks, drvdata->clks);
if (ret) {
dev_err(dev, "Failed to get clocks %d\n", ret);
return ret;
}
ret = clk_bulk_prepare_enable(drvdata->num_clks, drvdata->clks);
if (ret) {
dev_err(dev, "sc7280 clk_enable failed\n");
return ret;
}
return 0;
}
static int sc7280_lpass_exit(struct platform_device *pdev)
{
struct lpass_data *drvdata = platform_get_drvdata(pdev);
clk_bulk_disable_unprepare(drvdata->num_clks, drvdata->clks);
return 0;
}
static int __maybe_unused sc7280_lpass_dev_resume(struct device *dev)
{
struct lpass_data *drvdata = dev_get_drvdata(dev);
return clk_bulk_prepare_enable(drvdata->num_clks, drvdata->clks);
}
static int __maybe_unused sc7280_lpass_dev_suspend(struct device *dev)
{
struct lpass_data *drvdata = dev_get_drvdata(dev);
clk_bulk_disable_unprepare(drvdata->num_clks, drvdata->clks);
return 0;
}
static const struct dev_pm_ops sc7280_lpass_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(sc7280_lpass_dev_suspend, sc7280_lpass_dev_resume)
};
static struct lpass_variant sc7280_data = {
.i2sctrl_reg_base = 0x1000,
.i2sctrl_reg_stride = 0x1000,
.i2s_ports = 3,
.irq_reg_base = 0x9000,
.irq_reg_stride = 0x1000,
.irq_ports = 3,
.rdma_reg_base = 0xC000,
.rdma_reg_stride = 0x1000,
.rdma_channels = 5,
.rxtx_rdma_reg_base = 0xC000,
.rxtx_rdma_reg_stride = 0x1000,
.rxtx_rdma_channels = 8,
.hdmi_rdma_reg_base = 0x64000,
.hdmi_rdma_reg_stride = 0x1000,
.hdmi_rdma_channels = 4,
.dmactl_audif_start = 1,
.wrdma_reg_base = 0x18000,
.wrdma_reg_stride = 0x1000,
.wrdma_channel_start = 5,
.wrdma_channels = 4,
.rxtx_irq_reg_base = 0x9000,
.rxtx_irq_reg_stride = 0x1000,
.rxtx_irq_ports = 3,
.rxtx_wrdma_reg_base = 0x18000,
.rxtx_wrdma_reg_stride = 0x1000,
.rxtx_wrdma_channel_start = 5,
.rxtx_wrdma_channels = 6,
.va_wrdma_reg_base = 0x18000,
.va_wrdma_reg_stride = 0x1000,
.va_wrdma_channel_start = 5,
.va_wrdma_channels = 3,
.va_irq_reg_base = 0x9000,
.va_irq_reg_stride = 0x1000,
.va_irq_ports = 3,
.loopback = REG_FIELD_ID(0x1000, 17, 17, 3, 0x1000),
.spken = REG_FIELD_ID(0x1000, 16, 16, 3, 0x1000),
.spkmode = REG_FIELD_ID(0x1000, 11, 15, 3, 0x1000),
.spkmono = REG_FIELD_ID(0x1000, 10, 10, 3, 0x1000),
.micen = REG_FIELD_ID(0x1000, 9, 9, 3, 0x1000),
.micmode = REG_FIELD_ID(0x1000, 4, 8, 3, 0x1000),
.micmono = REG_FIELD_ID(0x1000, 3, 3, 3, 0x1000),
.wssrc = REG_FIELD_ID(0x1000, 2, 2, 3, 0x1000),
.bitwidth = REG_FIELD_ID(0x1000, 0, 1, 3, 0x1000),
.rdma_dyncclk = REG_FIELD_ID(0xC000, 21, 21, 5, 0x1000),
.rdma_bursten = REG_FIELD_ID(0xC000, 20, 20, 5, 0x1000),
.rdma_wpscnt = REG_FIELD_ID(0xC000, 16, 19, 5, 0x1000),
.rdma_intf = REG_FIELD_ID(0xC000, 12, 15, 5, 0x1000),
.rdma_fifowm = REG_FIELD_ID(0xC000, 1, 5, 5, 0x1000),
.rdma_enable = REG_FIELD_ID(0xC000, 0, 0, 5, 0x1000),
.wrdma_dyncclk = REG_FIELD_ID(0x18000, 22, 22, 4, 0x1000),
.wrdma_bursten = REG_FIELD_ID(0x18000, 21, 21, 4, 0x1000),
.wrdma_wpscnt = REG_FIELD_ID(0x18000, 17, 20, 4, 0x1000),
.wrdma_intf = REG_FIELD_ID(0x18000, 12, 16, 4, 0x1000),
.wrdma_fifowm = REG_FIELD_ID(0x18000, 1, 5, 4, 0x1000),
.wrdma_enable = REG_FIELD_ID(0x18000, 0, 0, 4, 0x1000),
.rxtx_rdma_enable = REG_FIELD_ID(0xC000, 0, 0, 7, 0x1000),
.rxtx_rdma_fifowm = REG_FIELD_ID(0xC000, 1, 11, 7, 0x1000),
.rxtx_rdma_intf = REG_FIELD_ID(0xC000, 12, 15, 7, 0x1000),
.rxtx_rdma_wpscnt = REG_FIELD_ID(0xC000, 16, 19, 7, 0x1000),
.rxtx_rdma_bursten = REG_FIELD_ID(0xC000, 20, 20, 7, 0x1000),
.rxtx_rdma_dyncclk = REG_FIELD_ID(0xC000, 21, 21, 7, 0x1000),
.rxtx_rdma_codec_ch = REG_FIELD_ID(0xC050, 0, 7, 7, 0x1000),
.rxtx_rdma_codec_intf = REG_FIELD_ID(0xC050, 16, 19, 7, 0x1000),
.rxtx_rdma_codec_fs_delay = REG_FIELD_ID(0xC050, 21, 24, 7, 0x1000),
.rxtx_rdma_codec_fs_sel = REG_FIELD_ID(0xC050, 25, 27, 7, 0x1000),
.rxtx_rdma_codec_pack = REG_FIELD_ID(0xC050, 29, 29, 5, 0x1000),
.rxtx_rdma_codec_enable = REG_FIELD_ID(0xC050, 30, 30, 7, 0x1000),
.rxtx_wrdma_enable = REG_FIELD_ID(0x18000, 0, 0, 5, 0x1000),
.rxtx_wrdma_fifowm = REG_FIELD_ID(0x18000, 1, 11, 5, 0x1000),
.rxtx_wrdma_intf = REG_FIELD_ID(0x18000, 12, 16, 5, 0x1000),
.rxtx_wrdma_wpscnt = REG_FIELD_ID(0x18000, 17, 20, 5, 0x1000),
.rxtx_wrdma_bursten = REG_FIELD_ID(0x18000, 21, 21, 5, 0x1000),
.rxtx_wrdma_dyncclk = REG_FIELD_ID(0x18000, 22, 22, 5, 0x1000),
.rxtx_wrdma_codec_ch = REG_FIELD_ID(0x18050, 0, 7, 5, 0x1000),
.rxtx_wrdma_codec_intf = REG_FIELD_ID(0x18050, 16, 19, 5, 0x1000),
.rxtx_wrdma_codec_fs_delay = REG_FIELD_ID(0x18050, 21, 24, 5, 0x1000),
.rxtx_wrdma_codec_fs_sel = REG_FIELD_ID(0x18050, 25, 27, 5, 0x1000),
.rxtx_wrdma_codec_pack = REG_FIELD_ID(0x18050, 29, 29, 5, 0x1000),
.rxtx_wrdma_codec_enable = REG_FIELD_ID(0x18050, 30, 30, 5, 0x1000),
.va_wrdma_enable = REG_FIELD_ID(0x18000, 0, 0, 5, 0x1000),
.va_wrdma_fifowm = REG_FIELD_ID(0x18000, 1, 11, 5, 0x1000),
.va_wrdma_intf = REG_FIELD_ID(0x18000, 12, 16, 5, 0x1000),
.va_wrdma_wpscnt = REG_FIELD_ID(0x18000, 17, 20, 5, 0x1000),
.va_wrdma_bursten = REG_FIELD_ID(0x18000, 21, 21, 5, 0x1000),
.va_wrdma_dyncclk = REG_FIELD_ID(0x18000, 22, 22, 5, 0x1000),
.va_wrdma_codec_ch = REG_FIELD_ID(0x18050, 0, 7, 5, 0x1000),
.va_wrdma_codec_intf = REG_FIELD_ID(0x18050, 16, 19, 5, 0x1000),
.va_wrdma_codec_fs_delay = REG_FIELD_ID(0x18050, 21, 24, 5, 0x1000),
.va_wrdma_codec_fs_sel = REG_FIELD_ID(0x18050, 25, 27, 5, 0x1000),
.va_wrdma_codec_pack = REG_FIELD_ID(0x18050, 29, 29, 5, 0x1000),
.va_wrdma_codec_enable = REG_FIELD_ID(0x18050, 30, 30, 5, 0x1000),
.hdmi_tx_ctl_addr = 0x1000,
.hdmi_legacy_addr = 0x1008,
.hdmi_vbit_addr = 0x610c0,
.hdmi_ch_lsb_addr = 0x61048,
.hdmi_ch_msb_addr = 0x6104c,
.ch_stride = 0x8,
.hdmi_parity_addr = 0x61034,
.hdmi_dmactl_addr = 0x61038,
.hdmi_dma_stride = 0x4,
.hdmi_DP_addr = 0x610c8,
.hdmi_sstream_addr = 0x6101c,
.hdmi_irq_reg_base = 0x63000,
.hdmi_irq_ports = 1,
.hdmi_rdma_dyncclk = REG_FIELD_ID(0x64000, 14, 14, 4, 0x1000),
.hdmi_rdma_bursten = REG_FIELD_ID(0x64000, 13, 13, 4, 0x1000),
.hdmi_rdma_burst8 = REG_FIELD_ID(0x64000, 15, 15, 4, 0x1000),
.hdmi_rdma_burst16 = REG_FIELD_ID(0x64000, 16, 16, 4, 0x1000),
.hdmi_rdma_dynburst = REG_FIELD_ID(0x64000, 18, 18, 4, 0x1000),
.hdmi_rdma_wpscnt = REG_FIELD_ID(0x64000, 10, 12, 4, 0x1000),
.hdmi_rdma_fifowm = REG_FIELD_ID(0x64000, 1, 5, 4, 0x1000),
.hdmi_rdma_enable = REG_FIELD_ID(0x64000, 0, 0, 4, 0x1000),
.sstream_en = REG_FIELD(0x6101c, 0, 0),
.dma_sel = REG_FIELD(0x6101c, 1, 2),
.auto_bbit_en = REG_FIELD(0x6101c, 3, 3),
.layout = REG_FIELD(0x6101c, 4, 4),
.layout_sp = REG_FIELD(0x6101c, 5, 8),
.set_sp_on_en = REG_FIELD(0x6101c, 10, 10),
.dp_audio = REG_FIELD(0x6101c, 11, 11),
.dp_staffing_en = REG_FIELD(0x6101c, 12, 12),
.dp_sp_b_hw_en = REG_FIELD(0x6101c, 13, 13),
.mute = REG_FIELD(0x610c8, 0, 0),
.as_sdp_cc = REG_FIELD(0x610c8, 1, 3),
.as_sdp_ct = REG_FIELD(0x610c8, 4, 7),
.aif_db4 = REG_FIELD(0x610c8, 8, 15),
.frequency = REG_FIELD(0x610c8, 16, 21),
.mst_index = REG_FIELD(0x610c8, 28, 29),
.dptx_index = REG_FIELD(0x610c8, 30, 31),
.soft_reset = REG_FIELD(0x1000, 31, 31),
.force_reset = REG_FIELD(0x1000, 30, 30),
.use_hw_chs = REG_FIELD(0x61038, 0, 0),
.use_hw_usr = REG_FIELD(0x61038, 1, 1),
.hw_chs_sel = REG_FIELD(0x61038, 2, 4),
.hw_usr_sel = REG_FIELD(0x61038, 5, 6),
.replace_vbit = REG_FIELD(0x610c0, 0, 0),
.vbit_stream = REG_FIELD(0x610c0, 1, 1),
.legacy_en = REG_FIELD(0x1008, 0, 0),
.calc_en = REG_FIELD(0x61034, 0, 0),
.lsb_bits = REG_FIELD(0x61048, 0, 31),
.msb_bits = REG_FIELD(0x6104c, 0, 31),
.clk_name = (const char*[]) {
"core_cc_sysnoc_mport_core"
},
.num_clks = 1,
.dai_driver = sc7280_lpass_cpu_dai_driver,
.num_dai = ARRAY_SIZE(sc7280_lpass_cpu_dai_driver),
.dai_osr_clk_names = (const char *[]) {
"audio_cc_ext_mclk0",
"null"
},
.dai_bit_clk_names = (const char *[]) {
"core_cc_ext_if0_ibit",
"core_cc_ext_if1_ibit"
},
.init = sc7280_lpass_init,
.exit = sc7280_lpass_exit,
.alloc_dma_channel = sc7280_lpass_alloc_dma_channel,
.free_dma_channel = sc7280_lpass_free_dma_channel,
};
static const struct of_device_id sc7280_lpass_cpu_device_id[] = {
{.compatible = "qcom,sc7280-lpass-cpu", .data = &sc7280_data},
{}
};
MODULE_DEVICE_TABLE(of, sc7280_lpass_cpu_device_id);
static struct platform_driver sc7280_lpass_cpu_platform_driver = {
.driver = {
.name = "sc7280-lpass-cpu",
.of_match_table = of_match_ptr(sc7280_lpass_cpu_device_id),
.pm = &sc7280_lpass_pm_ops,
},
.probe = asoc_qcom_lpass_cpu_platform_probe,
.remove = asoc_qcom_lpass_cpu_platform_remove,
.shutdown = asoc_qcom_lpass_cpu_platform_shutdown,
};
module_platform_driver(sc7280_lpass_cpu_platform_driver);
MODULE_DESCRIPTION("SC7280 LPASS CPU DRIVER");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/qcom/lpass-sc7280.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
*
* lpass-ipq806x.c -- ALSA SoC CPU DAI driver for QTi LPASS
* Splited out the IPQ8064 soc specific from lpass-cpu.c
*/
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <sound/pcm.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include "lpass-lpaif-reg.h"
#include "lpass.h"
enum lpaif_i2s_ports {
IPQ806X_LPAIF_I2S_PORT_CODEC_SPK,
IPQ806X_LPAIF_I2S_PORT_CODEC_MIC,
IPQ806X_LPAIF_I2S_PORT_SEC_SPK,
IPQ806X_LPAIF_I2S_PORT_SEC_MIC,
IPQ806X_LPAIF_I2S_PORT_MI2S,
};
enum lpaif_dma_channels {
IPQ806X_LPAIF_RDMA_CHAN_MI2S,
IPQ806X_LPAIF_RDMA_CHAN_PCM0,
IPQ806X_LPAIF_RDMA_CHAN_PCM1,
};
static struct snd_soc_dai_driver ipq806x_lpass_cpu_dai_driver = {
.id = IPQ806X_LPAIF_I2S_PORT_MI2S,
.playback = {
.stream_name = "lpass-cpu-playback",
.formats = SNDRV_PCM_FMTBIT_S16 |
SNDRV_PCM_FMTBIT_S24 |
SNDRV_PCM_FMTBIT_S32,
.rates = SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 |
SNDRV_PCM_RATE_32000 |
SNDRV_PCM_RATE_48000 |
SNDRV_PCM_RATE_96000,
.rate_min = 8000,
.rate_max = 96000,
.channels_min = 1,
.channels_max = 8,
},
.ops = &asoc_qcom_lpass_cpu_dai_ops,
};
static int ipq806x_lpass_init(struct platform_device *pdev)
{
struct lpass_data *drvdata = platform_get_drvdata(pdev);
struct device *dev = &pdev->dev;
int ret;
drvdata->ahbix_clk = devm_clk_get(dev, "ahbix-clk");
if (IS_ERR(drvdata->ahbix_clk)) {
dev_err(dev, "error getting ahbix-clk: %ld\n",
PTR_ERR(drvdata->ahbix_clk));
ret = PTR_ERR(drvdata->ahbix_clk);
goto err_ahbix_clk;
}
ret = clk_set_rate(drvdata->ahbix_clk, LPASS_AHBIX_CLOCK_FREQUENCY);
if (ret) {
dev_err(dev, "error setting rate on ahbix_clk: %d\n", ret);
goto err_ahbix_clk;
}
dev_dbg(dev, "set ahbix_clk rate to %lu\n",
clk_get_rate(drvdata->ahbix_clk));
ret = clk_prepare_enable(drvdata->ahbix_clk);
if (ret) {
dev_err(dev, "error enabling ahbix_clk: %d\n", ret);
goto err_ahbix_clk;
}
err_ahbix_clk:
return ret;
}
static int ipq806x_lpass_exit(struct platform_device *pdev)
{
struct lpass_data *drvdata = platform_get_drvdata(pdev);
clk_disable_unprepare(drvdata->ahbix_clk);
return 0;
}
static int ipq806x_lpass_alloc_dma_channel(struct lpass_data *drvdata, int dir, unsigned int dai_id)
{
if (dir == SNDRV_PCM_STREAM_PLAYBACK)
return IPQ806X_LPAIF_RDMA_CHAN_MI2S;
else /* Capture currently not implemented */
return -EINVAL;
}
static int ipq806x_lpass_free_dma_channel(struct lpass_data *drvdata, int chan, unsigned int dai_id)
{
return 0;
}
static struct lpass_variant ipq806x_data = {
.i2sctrl_reg_base = 0x0010,
.i2sctrl_reg_stride = 0x04,
.i2s_ports = 5,
.irq_reg_base = 0x3000,
.irq_reg_stride = 0x1000,
.irq_ports = 3,
.rdma_reg_base = 0x6000,
.rdma_reg_stride = 0x1000,
.rdma_channels = 4,
.wrdma_reg_base = 0xB000,
.wrdma_reg_stride = 0x1000,
.wrdma_channel_start = 5,
.wrdma_channels = 4,
.loopback = REG_FIELD_ID(0x0010, 15, 15, 5, 0x4),
.spken = REG_FIELD_ID(0x0010, 14, 14, 5, 0x4),
.spkmode = REG_FIELD_ID(0x0010, 10, 13, 5, 0x4),
.spkmono = REG_FIELD_ID(0x0010, 9, 9, 5, 0x4),
.micen = REG_FIELD_ID(0x0010, 8, 8, 5, 0x4),
.micmode = REG_FIELD_ID(0x0010, 4, 7, 5, 0x4),
.micmono = REG_FIELD_ID(0x0010, 3, 3, 5, 0x4),
.wssrc = REG_FIELD_ID(0x0010, 2, 2, 5, 0x4),
.bitwidth = REG_FIELD_ID(0x0010, 0, 1, 5, 0x4),
.rdma_dyncclk = REG_FIELD_ID(0x6000, 12, 12, 4, 0x1000),
.rdma_bursten = REG_FIELD_ID(0x6000, 11, 11, 4, 0x1000),
.rdma_wpscnt = REG_FIELD_ID(0x6000, 8, 10, 4, 0x1000),
.rdma_intf = REG_FIELD_ID(0x6000, 4, 7, 4, 0x1000),
.rdma_fifowm = REG_FIELD_ID(0x6000, 1, 3, 4, 0x1000),
.rdma_enable = REG_FIELD_ID(0x6000, 0, 0, 4, 0x1000),
.wrdma_dyncclk = REG_FIELD_ID(0xB000, 12, 12, 4, 0x1000),
.wrdma_bursten = REG_FIELD_ID(0xB000, 11, 11, 4, 0x1000),
.wrdma_wpscnt = REG_FIELD_ID(0xB000, 8, 10, 4, 0x1000),
.wrdma_intf = REG_FIELD_ID(0xB000, 4, 7, 4, 0x1000),
.wrdma_fifowm = REG_FIELD_ID(0xB000, 1, 3, 4, 0x1000),
.wrdma_enable = REG_FIELD_ID(0xB000, 0, 0, 4, 0x1000),
.dai_driver = &ipq806x_lpass_cpu_dai_driver,
.num_dai = 1,
.dai_osr_clk_names = (const char *[]) {
"mi2s-osr-clk",
},
.dai_bit_clk_names = (const char *[]) {
"mi2s-bit-clk",
},
.init = ipq806x_lpass_init,
.exit = ipq806x_lpass_exit,
.alloc_dma_channel = ipq806x_lpass_alloc_dma_channel,
.free_dma_channel = ipq806x_lpass_free_dma_channel,
};
static const struct of_device_id ipq806x_lpass_cpu_device_id[] __maybe_unused = {
{ .compatible = "qcom,lpass-cpu", .data = &ipq806x_data },
{}
};
MODULE_DEVICE_TABLE(of, ipq806x_lpass_cpu_device_id);
static struct platform_driver ipq806x_lpass_cpu_platform_driver = {
.driver = {
.name = "lpass-cpu",
.of_match_table = of_match_ptr(ipq806x_lpass_cpu_device_id),
},
.probe = asoc_qcom_lpass_cpu_platform_probe,
.remove = asoc_qcom_lpass_cpu_platform_remove,
};
module_platform_driver(ipq806x_lpass_cpu_platform_driver);
MODULE_DESCRIPTION("QTi LPASS CPU Driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/qcom/lpass-ipq806x.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* lpass-sc7180.c -- ALSA SoC platform-machine driver for QTi LPASS
*/
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <dt-bindings/sound/sc7180-lpass.h>
#include <sound/pcm.h>
#include <sound/soc.h>
#include "lpass-lpaif-reg.h"
#include "lpass.h"
static struct snd_soc_dai_driver sc7180_lpass_cpu_dai_driver[] = {
{
.id = MI2S_PRIMARY,
.name = "Primary MI2S",
.playback = {
.stream_name = "Primary Playback",
.formats = SNDRV_PCM_FMTBIT_S16,
.rates = SNDRV_PCM_RATE_48000,
.rate_min = 48000,
.rate_max = 48000,
.channels_min = 2,
.channels_max = 2,
},
.capture = {
.stream_name = "Primary Capture",
.formats = SNDRV_PCM_FMTBIT_S16 |
SNDRV_PCM_FMTBIT_S32,
.rates = SNDRV_PCM_RATE_48000,
.rate_min = 48000,
.rate_max = 48000,
.channels_min = 2,
.channels_max = 2,
},
.ops = &asoc_qcom_lpass_cpu_dai_ops,
}, {
.id = MI2S_SECONDARY,
.name = "Secondary MI2S",
.playback = {
.stream_name = "Secondary Playback",
.formats = SNDRV_PCM_FMTBIT_S16,
.rates = SNDRV_PCM_RATE_48000,
.rate_min = 48000,
.rate_max = 48000,
.channels_min = 2,
.channels_max = 2,
},
.ops = &asoc_qcom_lpass_cpu_dai_ops2,
}, {
.id = LPASS_DP_RX,
.name = "Hdmi",
.playback = {
.stream_name = "Hdmi Playback",
.formats = SNDRV_PCM_FMTBIT_S24,
.rates = SNDRV_PCM_RATE_48000,
.rate_min = 48000,
.rate_max = 48000,
.channels_min = 2,
.channels_max = 2,
},
.ops = &asoc_qcom_lpass_hdmi_dai_ops,
},
};
static int sc7180_lpass_alloc_dma_channel(struct lpass_data *drvdata,
int direction, unsigned int dai_id)
{
struct lpass_variant *v = drvdata->variant;
int chan = 0;
if (dai_id == LPASS_DP_RX) {
if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
chan = find_first_zero_bit(&drvdata->hdmi_dma_ch_bit_map,
v->hdmi_rdma_channels);
if (chan >= v->hdmi_rdma_channels)
return -EBUSY;
}
set_bit(chan, &drvdata->hdmi_dma_ch_bit_map);
} else {
if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
chan = find_first_zero_bit(&drvdata->dma_ch_bit_map,
v->rdma_channels);
if (chan >= v->rdma_channels)
return -EBUSY;
} else {
chan = find_next_zero_bit(&drvdata->dma_ch_bit_map,
v->wrdma_channel_start +
v->wrdma_channels,
v->wrdma_channel_start);
if (chan >= v->wrdma_channel_start + v->wrdma_channels)
return -EBUSY;
}
set_bit(chan, &drvdata->dma_ch_bit_map);
}
return chan;
}
static int sc7180_lpass_free_dma_channel(struct lpass_data *drvdata, int chan, unsigned int dai_id)
{
if (dai_id == LPASS_DP_RX)
clear_bit(chan, &drvdata->hdmi_dma_ch_bit_map);
else
clear_bit(chan, &drvdata->dma_ch_bit_map);
return 0;
}
static int sc7180_lpass_init(struct platform_device *pdev)
{
struct lpass_data *drvdata = platform_get_drvdata(pdev);
struct lpass_variant *variant = drvdata->variant;
struct device *dev = &pdev->dev;
int ret, i;
drvdata->clks = devm_kcalloc(dev, variant->num_clks,
sizeof(*drvdata->clks), GFP_KERNEL);
if (!drvdata->clks)
return -ENOMEM;
drvdata->num_clks = variant->num_clks;
for (i = 0; i < drvdata->num_clks; i++)
drvdata->clks[i].id = variant->clk_name[i];
ret = devm_clk_bulk_get(dev, drvdata->num_clks, drvdata->clks);
if (ret) {
dev_err(dev, "Failed to get clocks %d\n", ret);
return ret;
}
ret = clk_bulk_prepare_enable(drvdata->num_clks, drvdata->clks);
if (ret) {
dev_err(dev, "sc7180 clk_enable failed\n");
return ret;
}
return 0;
}
static int sc7180_lpass_exit(struct platform_device *pdev)
{
struct lpass_data *drvdata = platform_get_drvdata(pdev);
clk_bulk_disable_unprepare(drvdata->num_clks, drvdata->clks);
return 0;
}
static int __maybe_unused sc7180_lpass_dev_resume(struct device *dev)
{
struct lpass_data *drvdata = dev_get_drvdata(dev);
return clk_bulk_prepare_enable(drvdata->num_clks, drvdata->clks);
}
static int __maybe_unused sc7180_lpass_dev_suspend(struct device *dev)
{
struct lpass_data *drvdata = dev_get_drvdata(dev);
clk_bulk_disable_unprepare(drvdata->num_clks, drvdata->clks);
return 0;
}
static const struct dev_pm_ops sc7180_lpass_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(sc7180_lpass_dev_suspend, sc7180_lpass_dev_resume)
};
static struct lpass_variant sc7180_data = {
.i2sctrl_reg_base = 0x1000,
.i2sctrl_reg_stride = 0x1000,
.i2s_ports = 3,
.irq_reg_base = 0x9000,
.irq_reg_stride = 0x1000,
.irq_ports = 3,
.rdma_reg_base = 0xC000,
.rdma_reg_stride = 0x1000,
.rdma_channels = 5,
.hdmi_rdma_reg_base = 0x64000,
.hdmi_rdma_reg_stride = 0x1000,
.hdmi_rdma_channels = 4,
.dmactl_audif_start = 1,
.wrdma_reg_base = 0x18000,
.wrdma_reg_stride = 0x1000,
.wrdma_channel_start = 5,
.wrdma_channels = 4,
.loopback = REG_FIELD_ID(0x1000, 17, 17, 3, 0x1000),
.spken = REG_FIELD_ID(0x1000, 16, 16, 3, 0x1000),
.spkmode = REG_FIELD_ID(0x1000, 11, 15, 3, 0x1000),
.spkmono = REG_FIELD_ID(0x1000, 10, 10, 3, 0x1000),
.micen = REG_FIELD_ID(0x1000, 9, 9, 3, 0x1000),
.micmode = REG_FIELD_ID(0x1000, 4, 8, 3, 0x1000),
.micmono = REG_FIELD_ID(0x1000, 3, 3, 3, 0x1000),
.wssrc = REG_FIELD_ID(0x1000, 2, 2, 3, 0x1000),
.bitwidth = REG_FIELD_ID(0x1000, 0, 1, 3, 0x1000),
.rdma_dyncclk = REG_FIELD_ID(0xC000, 21, 21, 5, 0x1000),
.rdma_bursten = REG_FIELD_ID(0xC000, 20, 20, 5, 0x1000),
.rdma_wpscnt = REG_FIELD_ID(0xC000, 16, 19, 5, 0x1000),
.rdma_intf = REG_FIELD_ID(0xC000, 12, 15, 5, 0x1000),
.rdma_fifowm = REG_FIELD_ID(0xC000, 1, 5, 5, 0x1000),
.rdma_enable = REG_FIELD_ID(0xC000, 0, 0, 5, 0x1000),
.wrdma_dyncclk = REG_FIELD_ID(0x18000, 22, 22, 4, 0x1000),
.wrdma_bursten = REG_FIELD_ID(0x18000, 21, 21, 4, 0x1000),
.wrdma_wpscnt = REG_FIELD_ID(0x18000, 17, 20, 4, 0x1000),
.wrdma_intf = REG_FIELD_ID(0x18000, 12, 16, 4, 0x1000),
.wrdma_fifowm = REG_FIELD_ID(0x18000, 1, 5, 4, 0x1000),
.wrdma_enable = REG_FIELD_ID(0x18000, 0, 0, 4, 0x1000),
.hdmi_tx_ctl_addr = 0x1000,
.hdmi_legacy_addr = 0x1008,
.hdmi_vbit_addr = 0x610c0,
.hdmi_ch_lsb_addr = 0x61048,
.hdmi_ch_msb_addr = 0x6104c,
.ch_stride = 0x8,
.hdmi_parity_addr = 0x61034,
.hdmi_dmactl_addr = 0x61038,
.hdmi_dma_stride = 0x4,
.hdmi_DP_addr = 0x610c8,
.hdmi_sstream_addr = 0x6101c,
.hdmi_irq_reg_base = 0x63000,
.hdmi_irq_ports = 1,
.hdmi_rdma_dyncclk = REG_FIELD_ID(0x64000, 14, 14, 4, 0x1000),
.hdmi_rdma_bursten = REG_FIELD_ID(0x64000, 13, 13, 4, 0x1000),
.hdmi_rdma_burst8 = REG_FIELD_ID(0x64000, 15, 15, 4, 0x1000),
.hdmi_rdma_burst16 = REG_FIELD_ID(0x64000, 16, 16, 4, 0x1000),
.hdmi_rdma_dynburst = REG_FIELD_ID(0x64000, 18, 18, 4, 0x1000),
.hdmi_rdma_wpscnt = REG_FIELD_ID(0x64000, 10, 12, 4, 0x1000),
.hdmi_rdma_fifowm = REG_FIELD_ID(0x64000, 1, 5, 4, 0x1000),
.hdmi_rdma_enable = REG_FIELD_ID(0x64000, 0, 0, 4, 0x1000),
.sstream_en = REG_FIELD(0x6101c, 0, 0),
.dma_sel = REG_FIELD(0x6101c, 1, 2),
.auto_bbit_en = REG_FIELD(0x6101c, 3, 3),
.layout = REG_FIELD(0x6101c, 4, 4),
.layout_sp = REG_FIELD(0x6101c, 5, 8),
.set_sp_on_en = REG_FIELD(0x6101c, 10, 10),
.dp_audio = REG_FIELD(0x6101c, 11, 11),
.dp_staffing_en = REG_FIELD(0x6101c, 12, 12),
.dp_sp_b_hw_en = REG_FIELD(0x6101c, 13, 13),
.mute = REG_FIELD(0x610c8, 0, 0),
.as_sdp_cc = REG_FIELD(0x610c8, 1, 3),
.as_sdp_ct = REG_FIELD(0x610c8, 4, 7),
.aif_db4 = REG_FIELD(0x610c8, 8, 15),
.frequency = REG_FIELD(0x610c8, 16, 21),
.mst_index = REG_FIELD(0x610c8, 28, 29),
.dptx_index = REG_FIELD(0x610c8, 30, 31),
.soft_reset = REG_FIELD(0x1000, 31, 31),
.force_reset = REG_FIELD(0x1000, 30, 30),
.use_hw_chs = REG_FIELD(0x61038, 0, 0),
.use_hw_usr = REG_FIELD(0x61038, 1, 1),
.hw_chs_sel = REG_FIELD(0x61038, 2, 4),
.hw_usr_sel = REG_FIELD(0x61038, 5, 6),
.replace_vbit = REG_FIELD(0x610c0, 0, 0),
.vbit_stream = REG_FIELD(0x610c0, 1, 1),
.legacy_en = REG_FIELD(0x1008, 0, 0),
.calc_en = REG_FIELD(0x61034, 0, 0),
.lsb_bits = REG_FIELD(0x61048, 0, 31),
.msb_bits = REG_FIELD(0x6104c, 0, 31),
.clk_name = (const char*[]) {
"pcnoc-sway-clk",
"audio-core",
"pcnoc-mport-clk",
},
.num_clks = 3,
.dai_driver = sc7180_lpass_cpu_dai_driver,
.num_dai = ARRAY_SIZE(sc7180_lpass_cpu_dai_driver),
.dai_osr_clk_names = (const char *[]) {
"mclk0",
"null",
},
.dai_bit_clk_names = (const char *[]) {
"mi2s-bit-clk0",
"mi2s-bit-clk1",
},
.init = sc7180_lpass_init,
.exit = sc7180_lpass_exit,
.alloc_dma_channel = sc7180_lpass_alloc_dma_channel,
.free_dma_channel = sc7180_lpass_free_dma_channel,
};
static const struct of_device_id sc7180_lpass_cpu_device_id[] __maybe_unused = {
{.compatible = "qcom,sc7180-lpass-cpu", .data = &sc7180_data},
{}
};
MODULE_DEVICE_TABLE(of, sc7180_lpass_cpu_device_id);
static struct platform_driver sc7180_lpass_cpu_platform_driver = {
.driver = {
.name = "sc7180-lpass-cpu",
.of_match_table = of_match_ptr(sc7180_lpass_cpu_device_id),
.pm = &sc7180_lpass_pm_ops,
},
.probe = asoc_qcom_lpass_cpu_platform_probe,
.remove = asoc_qcom_lpass_cpu_platform_remove,
.shutdown = asoc_qcom_lpass_cpu_platform_shutdown,
};
module_platform_driver(sc7180_lpass_cpu_platform_driver);
MODULE_DESCRIPTION("SC7180 LPASS CPU DRIVER");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/qcom/lpass-sc7180.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2018, Linaro Limited
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of_device.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/pcm.h>
#include "common.h"
#define SLIM_MAX_TX_PORTS 16
#define SLIM_MAX_RX_PORTS 16
#define WCD9335_DEFAULT_MCLK_RATE 9600000
static int apq8096_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
struct snd_pcm_hw_params *params)
{
struct snd_interval *rate = hw_param_interval(params,
SNDRV_PCM_HW_PARAM_RATE);
struct snd_interval *channels = hw_param_interval(params,
SNDRV_PCM_HW_PARAM_CHANNELS);
rate->min = rate->max = 48000;
channels->min = channels->max = 2;
return 0;
}
static int msm_snd_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
u32 rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS];
u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
int ret = 0;
ret = snd_soc_dai_get_channel_map(codec_dai,
&tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
if (ret != 0 && ret != -ENOTSUPP) {
pr_err("failed to get codec chan map, err:%d\n", ret);
goto end;
} else if (ret == -ENOTSUPP) {
return 0;
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
ret = snd_soc_dai_set_channel_map(cpu_dai, 0, NULL,
rx_ch_cnt, rx_ch);
else
ret = snd_soc_dai_set_channel_map(cpu_dai, tx_ch_cnt, tx_ch,
0, NULL);
if (ret != 0 && ret != -ENOTSUPP)
pr_err("Failed to set cpu chan map, err:%d\n", ret);
else if (ret == -ENOTSUPP)
ret = 0;
end:
return ret;
}
static const struct snd_soc_ops apq8096_ops = {
.hw_params = msm_snd_hw_params,
};
static int apq8096_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
/*
* Codec SLIMBUS configuration
* RX1, RX2, RX3, RX4, RX5, RX6, RX7, RX8, RX9, RX10, RX11, RX12, RX13
* TX1, TX2, TX3, TX4, TX5, TX6, TX7, TX8, TX9, TX10, TX11, TX12, TX13
* TX14, TX15, TX16
*/
unsigned int rx_ch[SLIM_MAX_RX_PORTS] = {144, 145, 146, 147, 148, 149,
150, 151, 152, 153, 154, 155, 156};
unsigned int tx_ch[SLIM_MAX_TX_PORTS] = {128, 129, 130, 131, 132, 133,
134, 135, 136, 137, 138, 139,
140, 141, 142, 143};
snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
snd_soc_dai_set_sysclk(codec_dai, 0, WCD9335_DEFAULT_MCLK_RATE,
SNDRV_PCM_STREAM_PLAYBACK);
return 0;
}
static void apq8096_add_be_ops(struct snd_soc_card *card)
{
struct snd_soc_dai_link *link;
int i;
for_each_card_prelinks(card, i, link) {
if (link->no_pcm == 1) {
link->be_hw_params_fixup = apq8096_be_hw_params_fixup;
link->init = apq8096_init;
link->ops = &apq8096_ops;
}
}
}
static int apq8096_platform_probe(struct platform_device *pdev)
{
struct snd_soc_card *card;
struct device *dev = &pdev->dev;
int ret;
card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
if (!card)
return -ENOMEM;
card->driver_name = "apq8096";
card->dev = dev;
card->owner = THIS_MODULE;
dev_set_drvdata(dev, card);
ret = qcom_snd_parse_of(card);
if (ret)
return ret;
apq8096_add_be_ops(card);
return devm_snd_soc_register_card(dev, card);
}
static const struct of_device_id msm_snd_apq8096_dt_match[] = {
{.compatible = "qcom,apq8096-sndcard"},
{}
};
MODULE_DEVICE_TABLE(of, msm_snd_apq8096_dt_match);
static struct platform_driver msm_snd_apq8096_driver = {
.probe = apq8096_platform_probe,
.driver = {
.name = "msm-snd-apq8096",
.of_match_table = msm_snd_apq8096_dt_match,
},
};
module_platform_driver(msm_snd_apq8096_driver);
MODULE_AUTHOR("Srinivas Kandagatla <[email protected]");
MODULE_DESCRIPTION("APQ8096 ASoC Machine Driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/qcom/apq8096.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
*
* lpass-cpu.c -- ALSA SoC CPU DAI driver for QTi LPASS
*/
#include <linux/clk.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include "lpass-lpaif-reg.h"
#include "lpass.h"
#define LPASS_CPU_MAX_MI2S_LINES 4
#define LPASS_CPU_I2S_SD0_MASK BIT(0)
#define LPASS_CPU_I2S_SD1_MASK BIT(1)
#define LPASS_CPU_I2S_SD2_MASK BIT(2)
#define LPASS_CPU_I2S_SD3_MASK BIT(3)
#define LPASS_CPU_I2S_SD0_1_MASK GENMASK(1, 0)
#define LPASS_CPU_I2S_SD2_3_MASK GENMASK(3, 2)
#define LPASS_CPU_I2S_SD0_1_2_MASK GENMASK(2, 0)
#define LPASS_CPU_I2S_SD0_1_2_3_MASK GENMASK(3, 0)
#define LPASS_REG_READ 1
#define LPASS_REG_WRITE 0
/*
* Channel maps for Quad channel playbacks on MI2S Secondary
*/
static struct snd_pcm_chmap_elem lpass_quad_chmaps[] = {
{ .channels = 4,
.map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_RL,
SNDRV_CHMAP_FR, SNDRV_CHMAP_RR } },
{ }
};
static int lpass_cpu_init_i2sctl_bitfields(struct device *dev,
struct lpaif_i2sctl *i2sctl, struct regmap *map)
{
struct lpass_data *drvdata = dev_get_drvdata(dev);
struct lpass_variant *v = drvdata->variant;
i2sctl->loopback = devm_regmap_field_alloc(dev, map, v->loopback);
i2sctl->spken = devm_regmap_field_alloc(dev, map, v->spken);
i2sctl->spkmode = devm_regmap_field_alloc(dev, map, v->spkmode);
i2sctl->spkmono = devm_regmap_field_alloc(dev, map, v->spkmono);
i2sctl->micen = devm_regmap_field_alloc(dev, map, v->micen);
i2sctl->micmode = devm_regmap_field_alloc(dev, map, v->micmode);
i2sctl->micmono = devm_regmap_field_alloc(dev, map, v->micmono);
i2sctl->wssrc = devm_regmap_field_alloc(dev, map, v->wssrc);
i2sctl->bitwidth = devm_regmap_field_alloc(dev, map, v->bitwidth);
if (IS_ERR(i2sctl->loopback) || IS_ERR(i2sctl->spken) ||
IS_ERR(i2sctl->spkmode) || IS_ERR(i2sctl->spkmono) ||
IS_ERR(i2sctl->micen) || IS_ERR(i2sctl->micmode) ||
IS_ERR(i2sctl->micmono) || IS_ERR(i2sctl->wssrc) ||
IS_ERR(i2sctl->bitwidth))
return -EINVAL;
return 0;
}
static int lpass_cpu_daiops_set_sysclk(struct snd_soc_dai *dai, int clk_id,
unsigned int freq, int dir)
{
struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
int ret;
ret = clk_set_rate(drvdata->mi2s_osr_clk[dai->driver->id], freq);
if (ret)
dev_err(dai->dev, "error setting mi2s osrclk to %u: %d\n",
freq, ret);
return ret;
}
static int lpass_cpu_daiops_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
int ret;
ret = clk_prepare_enable(drvdata->mi2s_osr_clk[dai->driver->id]);
if (ret) {
dev_err(dai->dev, "error in enabling mi2s osr clk: %d\n", ret);
return ret;
}
ret = clk_prepare(drvdata->mi2s_bit_clk[dai->driver->id]);
if (ret) {
dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret);
clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]);
return ret;
}
return 0;
}
static void lpass_cpu_daiops_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
struct lpaif_i2sctl *i2sctl = drvdata->i2sctl;
unsigned int id = dai->driver->id;
clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]);
/*
* Ensure LRCLK is disabled even in device node validation.
* Will not impact if disabled in lpass_cpu_daiops_trigger()
* suspend.
*/
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
regmap_fields_write(i2sctl->spken, id, LPAIF_I2SCTL_SPKEN_DISABLE);
else
regmap_fields_write(i2sctl->micen, id, LPAIF_I2SCTL_MICEN_DISABLE);
/*
* BCLK may not be enabled if lpass_cpu_daiops_prepare is called before
* lpass_cpu_daiops_shutdown. It's paired with the clk_enable in
* lpass_cpu_daiops_prepare.
*/
if (drvdata->mi2s_was_prepared[dai->driver->id]) {
drvdata->mi2s_was_prepared[dai->driver->id] = false;
clk_disable(drvdata->mi2s_bit_clk[dai->driver->id]);
}
clk_unprepare(drvdata->mi2s_bit_clk[dai->driver->id]);
}
static int lpass_cpu_daiops_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
struct lpaif_i2sctl *i2sctl = drvdata->i2sctl;
unsigned int id = dai->driver->id;
snd_pcm_format_t format = params_format(params);
unsigned int channels = params_channels(params);
unsigned int rate = params_rate(params);
unsigned int mode;
unsigned int regval;
int bitwidth, ret;
bitwidth = snd_pcm_format_width(format);
if (bitwidth < 0) {
dev_err(dai->dev, "invalid bit width given: %d\n", bitwidth);
return bitwidth;
}
ret = regmap_fields_write(i2sctl->loopback, id,
LPAIF_I2SCTL_LOOPBACK_DISABLE);
if (ret) {
dev_err(dai->dev, "error updating loopback field: %d\n", ret);
return ret;
}
ret = regmap_fields_write(i2sctl->wssrc, id,
LPAIF_I2SCTL_WSSRC_INTERNAL);
if (ret) {
dev_err(dai->dev, "error updating wssrc field: %d\n", ret);
return ret;
}
switch (bitwidth) {
case 16:
regval = LPAIF_I2SCTL_BITWIDTH_16;
break;
case 24:
regval = LPAIF_I2SCTL_BITWIDTH_24;
break;
case 32:
regval = LPAIF_I2SCTL_BITWIDTH_32;
break;
default:
dev_err(dai->dev, "invalid bitwidth given: %d\n", bitwidth);
return -EINVAL;
}
ret = regmap_fields_write(i2sctl->bitwidth, id, regval);
if (ret) {
dev_err(dai->dev, "error updating bitwidth field: %d\n", ret);
return ret;
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
mode = drvdata->mi2s_playback_sd_mode[id];
else
mode = drvdata->mi2s_capture_sd_mode[id];
if (!mode) {
dev_err(dai->dev, "no line is assigned\n");
return -EINVAL;
}
switch (channels) {
case 1:
case 2:
switch (mode) {
case LPAIF_I2SCTL_MODE_QUAD01:
case LPAIF_I2SCTL_MODE_6CH:
case LPAIF_I2SCTL_MODE_8CH:
mode = LPAIF_I2SCTL_MODE_SD0;
break;
case LPAIF_I2SCTL_MODE_QUAD23:
mode = LPAIF_I2SCTL_MODE_SD2;
break;
}
break;
case 4:
if (mode < LPAIF_I2SCTL_MODE_QUAD01) {
dev_err(dai->dev, "cannot configure 4 channels with mode %d\n",
mode);
return -EINVAL;
}
switch (mode) {
case LPAIF_I2SCTL_MODE_6CH:
case LPAIF_I2SCTL_MODE_8CH:
mode = LPAIF_I2SCTL_MODE_QUAD01;
break;
}
break;
case 6:
if (mode < LPAIF_I2SCTL_MODE_6CH) {
dev_err(dai->dev, "cannot configure 6 channels with mode %d\n",
mode);
return -EINVAL;
}
switch (mode) {
case LPAIF_I2SCTL_MODE_8CH:
mode = LPAIF_I2SCTL_MODE_6CH;
break;
}
break;
case 8:
if (mode < LPAIF_I2SCTL_MODE_8CH) {
dev_err(dai->dev, "cannot configure 8 channels with mode %d\n",
mode);
return -EINVAL;
}
break;
default:
dev_err(dai->dev, "invalid channels given: %u\n", channels);
return -EINVAL;
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
ret = regmap_fields_write(i2sctl->spkmode, id,
LPAIF_I2SCTL_SPKMODE(mode));
if (ret) {
dev_err(dai->dev, "error writing to i2sctl spkr mode: %d\n",
ret);
return ret;
}
if (channels >= 2)
ret = regmap_fields_write(i2sctl->spkmono, id,
LPAIF_I2SCTL_SPKMONO_STEREO);
else
ret = regmap_fields_write(i2sctl->spkmono, id,
LPAIF_I2SCTL_SPKMONO_MONO);
} else {
ret = regmap_fields_write(i2sctl->micmode, id,
LPAIF_I2SCTL_MICMODE(mode));
if (ret) {
dev_err(dai->dev, "error writing to i2sctl mic mode: %d\n",
ret);
return ret;
}
if (channels >= 2)
ret = regmap_fields_write(i2sctl->micmono, id,
LPAIF_I2SCTL_MICMONO_STEREO);
else
ret = regmap_fields_write(i2sctl->micmono, id,
LPAIF_I2SCTL_MICMONO_MONO);
}
if (ret) {
dev_err(dai->dev, "error writing to i2sctl channels mode: %d\n",
ret);
return ret;
}
ret = clk_set_rate(drvdata->mi2s_bit_clk[id],
rate * bitwidth * 2);
if (ret) {
dev_err(dai->dev, "error setting mi2s bitclk to %u: %d\n",
rate * bitwidth * 2, ret);
return ret;
}
return 0;
}
static int lpass_cpu_daiops_trigger(struct snd_pcm_substream *substream,
int cmd, struct snd_soc_dai *dai)
{
struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
struct lpaif_i2sctl *i2sctl = drvdata->i2sctl;
unsigned int id = dai->driver->id;
int ret = -EINVAL;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
/*
* Ensure lpass BCLK/LRCLK is enabled during
* device resume as lpass_cpu_daiops_prepare() is not called
* after the device resumes. We don't check mi2s_was_prepared before
* enable/disable BCLK in trigger events because:
* 1. These trigger events are paired, so the BCLK
* enable_count is balanced.
* 2. the BCLK can be shared (ex: headset and headset mic),
* we need to increase the enable_count so that we don't
* turn off the shared BCLK while other devices are using
* it.
*/
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
ret = regmap_fields_write(i2sctl->spken, id,
LPAIF_I2SCTL_SPKEN_ENABLE);
} else {
ret = regmap_fields_write(i2sctl->micen, id,
LPAIF_I2SCTL_MICEN_ENABLE);
}
if (ret)
dev_err(dai->dev, "error writing to i2sctl reg: %d\n",
ret);
ret = clk_enable(drvdata->mi2s_bit_clk[id]);
if (ret) {
dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret);
clk_disable(drvdata->mi2s_osr_clk[id]);
return ret;
}
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
/*
* To ensure lpass BCLK/LRCLK is disabled during
* device suspend.
*/
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
ret = regmap_fields_write(i2sctl->spken, id,
LPAIF_I2SCTL_SPKEN_DISABLE);
} else {
ret = regmap_fields_write(i2sctl->micen, id,
LPAIF_I2SCTL_MICEN_DISABLE);
}
if (ret)
dev_err(dai->dev, "error writing to i2sctl reg: %d\n",
ret);
clk_disable(drvdata->mi2s_bit_clk[dai->driver->id]);
break;
}
return ret;
}
static int lpass_cpu_daiops_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
struct lpaif_i2sctl *i2sctl = drvdata->i2sctl;
unsigned int id = dai->driver->id;
int ret;
/*
* Ensure lpass BCLK/LRCLK is enabled bit before playback/capture
* data flow starts. This allows other codec to have some delay before
* the data flow.
* (ex: to drop start up pop noise before capture starts).
*/
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
ret = regmap_fields_write(i2sctl->spken, id, LPAIF_I2SCTL_SPKEN_ENABLE);
else
ret = regmap_fields_write(i2sctl->micen, id, LPAIF_I2SCTL_MICEN_ENABLE);
if (ret) {
dev_err(dai->dev, "error writing to i2sctl reg: %d\n", ret);
return ret;
}
/*
* Check mi2s_was_prepared before enabling BCLK as lpass_cpu_daiops_prepare can
* be called multiple times. It's paired with the clk_disable in
* lpass_cpu_daiops_shutdown.
*/
if (!drvdata->mi2s_was_prepared[dai->driver->id]) {
ret = clk_enable(drvdata->mi2s_bit_clk[id]);
if (ret) {
dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret);
return ret;
}
drvdata->mi2s_was_prepared[dai->driver->id] = true;
}
return 0;
}
static int lpass_cpu_daiops_pcm_new(struct snd_soc_pcm_runtime *rtd, struct snd_soc_dai *dai)
{
int ret;
struct snd_soc_dai_driver *drv = dai->driver;
struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
if (drvdata->mi2s_playback_sd_mode[dai->id] == LPAIF_I2SCTL_MODE_QUAD01) {
ret = snd_pcm_add_chmap_ctls(rtd->pcm, SNDRV_PCM_STREAM_PLAYBACK,
lpass_quad_chmaps, drv->playback.channels_max, 0,
NULL);
if (ret < 0)
return ret;
}
return 0;
}
static int lpass_cpu_daiops_probe(struct snd_soc_dai *dai)
{
struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
int ret;
/* ensure audio hardware is disabled */
ret = regmap_write(drvdata->lpaif_map,
LPAIF_I2SCTL_REG(drvdata->variant, dai->driver->id), 0);
if (ret)
dev_err(dai->dev, "error writing to i2sctl reg: %d\n", ret);
return ret;
}
const struct snd_soc_dai_ops asoc_qcom_lpass_cpu_dai_ops = {
.probe = lpass_cpu_daiops_probe,
.set_sysclk = lpass_cpu_daiops_set_sysclk,
.startup = lpass_cpu_daiops_startup,
.shutdown = lpass_cpu_daiops_shutdown,
.hw_params = lpass_cpu_daiops_hw_params,
.trigger = lpass_cpu_daiops_trigger,
.prepare = lpass_cpu_daiops_prepare,
};
EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_dai_ops);
const struct snd_soc_dai_ops asoc_qcom_lpass_cpu_dai_ops2 = {
.pcm_new = lpass_cpu_daiops_pcm_new,
.probe = lpass_cpu_daiops_probe,
.set_sysclk = lpass_cpu_daiops_set_sysclk,
.startup = lpass_cpu_daiops_startup,
.shutdown = lpass_cpu_daiops_shutdown,
.hw_params = lpass_cpu_daiops_hw_params,
.trigger = lpass_cpu_daiops_trigger,
.prepare = lpass_cpu_daiops_prepare,
};
EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_dai_ops2);
static int asoc_qcom_of_xlate_dai_name(struct snd_soc_component *component,
const struct of_phandle_args *args,
const char **dai_name)
{
struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
struct lpass_variant *variant = drvdata->variant;
int id = args->args[0];
int ret = -EINVAL;
int i;
for (i = 0; i < variant->num_dai; i++) {
if (variant->dai_driver[i].id == id) {
*dai_name = variant->dai_driver[i].name;
ret = 0;
break;
}
}
return ret;
}
static const struct snd_soc_component_driver lpass_cpu_comp_driver = {
.name = "lpass-cpu",
.of_xlate_dai_name = asoc_qcom_of_xlate_dai_name,
.legacy_dai_naming = 1,
};
static bool lpass_cpu_regmap_writeable(struct device *dev, unsigned int reg)
{
struct lpass_data *drvdata = dev_get_drvdata(dev);
struct lpass_variant *v = drvdata->variant;
int i;
for (i = 0; i < v->i2s_ports; ++i)
if (reg == LPAIF_I2SCTL_REG(v, i))
return true;
for (i = 0; i < v->irq_ports; ++i) {
if (reg == LPAIF_IRQEN_REG(v, i))
return true;
if (reg == LPAIF_IRQCLEAR_REG(v, i))
return true;
}
for (i = 0; i < v->rdma_channels; ++i) {
if (reg == LPAIF_RDMACTL_REG(v, i))
return true;
if (reg == LPAIF_RDMABASE_REG(v, i))
return true;
if (reg == LPAIF_RDMABUFF_REG(v, i))
return true;
if (reg == LPAIF_RDMAPER_REG(v, i))
return true;
}
for (i = 0; i < v->wrdma_channels; ++i) {
if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start))
return true;
if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start))
return true;
if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start))
return true;
if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start))
return true;
}
return false;
}
static bool lpass_cpu_regmap_readable(struct device *dev, unsigned int reg)
{
struct lpass_data *drvdata = dev_get_drvdata(dev);
struct lpass_variant *v = drvdata->variant;
int i;
for (i = 0; i < v->i2s_ports; ++i)
if (reg == LPAIF_I2SCTL_REG(v, i))
return true;
for (i = 0; i < v->irq_ports; ++i) {
if (reg == LPAIF_IRQCLEAR_REG(v, i))
return true;
if (reg == LPAIF_IRQEN_REG(v, i))
return true;
if (reg == LPAIF_IRQSTAT_REG(v, i))
return true;
}
for (i = 0; i < v->rdma_channels; ++i) {
if (reg == LPAIF_RDMACTL_REG(v, i))
return true;
if (reg == LPAIF_RDMABASE_REG(v, i))
return true;
if (reg == LPAIF_RDMABUFF_REG(v, i))
return true;
if (reg == LPAIF_RDMACURR_REG(v, i))
return true;
if (reg == LPAIF_RDMAPER_REG(v, i))
return true;
}
for (i = 0; i < v->wrdma_channels; ++i) {
if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start))
return true;
if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start))
return true;
if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start))
return true;
if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start))
return true;
if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start))
return true;
}
return false;
}
static bool lpass_cpu_regmap_volatile(struct device *dev, unsigned int reg)
{
struct lpass_data *drvdata = dev_get_drvdata(dev);
struct lpass_variant *v = drvdata->variant;
int i;
for (i = 0; i < v->irq_ports; ++i) {
if (reg == LPAIF_IRQCLEAR_REG(v, i))
return true;
if (reg == LPAIF_IRQSTAT_REG(v, i))
return true;
}
for (i = 0; i < v->rdma_channels; ++i)
if (reg == LPAIF_RDMACURR_REG(v, i))
return true;
for (i = 0; i < v->wrdma_channels; ++i)
if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start))
return true;
return false;
}
static struct regmap_config lpass_cpu_regmap_config = {
.name = "lpass_cpu",
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.writeable_reg = lpass_cpu_regmap_writeable,
.readable_reg = lpass_cpu_regmap_readable,
.volatile_reg = lpass_cpu_regmap_volatile,
.cache_type = REGCACHE_FLAT,
};
static int lpass_hdmi_init_bitfields(struct device *dev, struct regmap *map)
{
struct lpass_data *drvdata = dev_get_drvdata(dev);
struct lpass_variant *v = drvdata->variant;
unsigned int i;
struct lpass_hdmi_tx_ctl *tx_ctl;
struct regmap_field *legacy_en;
struct lpass_vbit_ctrl *vbit_ctl;
struct regmap_field *tx_parity;
struct lpass_dp_metadata_ctl *meta_ctl;
struct lpass_sstream_ctl *sstream_ctl;
struct regmap_field *ch_msb;
struct regmap_field *ch_lsb;
struct lpass_hdmitx_dmactl *tx_dmactl;
int rval;
tx_ctl = devm_kzalloc(dev, sizeof(*tx_ctl), GFP_KERNEL);
if (!tx_ctl)
return -ENOMEM;
QCOM_REGMAP_FIELD_ALLOC(dev, map, v->soft_reset, tx_ctl->soft_reset);
QCOM_REGMAP_FIELD_ALLOC(dev, map, v->force_reset, tx_ctl->force_reset);
drvdata->tx_ctl = tx_ctl;
QCOM_REGMAP_FIELD_ALLOC(dev, map, v->legacy_en, legacy_en);
drvdata->hdmitx_legacy_en = legacy_en;
vbit_ctl = devm_kzalloc(dev, sizeof(*vbit_ctl), GFP_KERNEL);
if (!vbit_ctl)
return -ENOMEM;
QCOM_REGMAP_FIELD_ALLOC(dev, map, v->replace_vbit, vbit_ctl->replace_vbit);
QCOM_REGMAP_FIELD_ALLOC(dev, map, v->vbit_stream, vbit_ctl->vbit_stream);
drvdata->vbit_ctl = vbit_ctl;
QCOM_REGMAP_FIELD_ALLOC(dev, map, v->calc_en, tx_parity);
drvdata->hdmitx_parity_calc_en = tx_parity;
meta_ctl = devm_kzalloc(dev, sizeof(*meta_ctl), GFP_KERNEL);
if (!meta_ctl)
return -ENOMEM;
rval = devm_regmap_field_bulk_alloc(dev, map, &meta_ctl->mute, &v->mute, 7);
if (rval)
return rval;
drvdata->meta_ctl = meta_ctl;
sstream_ctl = devm_kzalloc(dev, sizeof(*sstream_ctl), GFP_KERNEL);
if (!sstream_ctl)
return -ENOMEM;
rval = devm_regmap_field_bulk_alloc(dev, map, &sstream_ctl->sstream_en, &v->sstream_en, 9);
if (rval)
return rval;
drvdata->sstream_ctl = sstream_ctl;
for (i = 0; i < LPASS_MAX_HDMI_DMA_CHANNELS; i++) {
QCOM_REGMAP_FIELD_ALLOC(dev, map, v->msb_bits, ch_msb);
drvdata->hdmitx_ch_msb[i] = ch_msb;
QCOM_REGMAP_FIELD_ALLOC(dev, map, v->lsb_bits, ch_lsb);
drvdata->hdmitx_ch_lsb[i] = ch_lsb;
tx_dmactl = devm_kzalloc(dev, sizeof(*tx_dmactl), GFP_KERNEL);
if (!tx_dmactl)
return -ENOMEM;
QCOM_REGMAP_FIELD_ALLOC(dev, map, v->use_hw_chs, tx_dmactl->use_hw_chs);
QCOM_REGMAP_FIELD_ALLOC(dev, map, v->use_hw_usr, tx_dmactl->use_hw_usr);
QCOM_REGMAP_FIELD_ALLOC(dev, map, v->hw_chs_sel, tx_dmactl->hw_chs_sel);
QCOM_REGMAP_FIELD_ALLOC(dev, map, v->hw_usr_sel, tx_dmactl->hw_usr_sel);
drvdata->hdmi_tx_dmactl[i] = tx_dmactl;
}
return 0;
}
static bool lpass_hdmi_regmap_writeable(struct device *dev, unsigned int reg)
{
struct lpass_data *drvdata = dev_get_drvdata(dev);
struct lpass_variant *v = drvdata->variant;
int i;
if (reg == LPASS_HDMI_TX_CTL_ADDR(v))
return true;
if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v))
return true;
if (reg == LPASS_HDMI_TX_VBIT_CTL_ADDR(v))
return true;
if (reg == LPASS_HDMI_TX_PARITY_ADDR(v))
return true;
if (reg == LPASS_HDMI_TX_DP_ADDR(v))
return true;
if (reg == LPASS_HDMI_TX_SSTREAM_ADDR(v))
return true;
if (reg == LPASS_HDMITX_APP_IRQEN_REG(v))
return true;
if (reg == LPASS_HDMITX_APP_IRQCLEAR_REG(v))
return true;
for (i = 0; i < v->hdmi_rdma_channels; i++) {
if (reg == LPASS_HDMI_TX_CH_LSB_ADDR(v, i))
return true;
if (reg == LPASS_HDMI_TX_CH_MSB_ADDR(v, i))
return true;
if (reg == LPASS_HDMI_TX_DMA_ADDR(v, i))
return true;
}
for (i = 0; i < v->hdmi_rdma_channels; ++i) {
if (reg == LPAIF_HDMI_RDMACTL_REG(v, i))
return true;
if (reg == LPAIF_HDMI_RDMABASE_REG(v, i))
return true;
if (reg == LPAIF_HDMI_RDMABUFF_REG(v, i))
return true;
if (reg == LPAIF_HDMI_RDMAPER_REG(v, i))
return true;
}
return false;
}
static bool lpass_hdmi_regmap_readable(struct device *dev, unsigned int reg)
{
struct lpass_data *drvdata = dev_get_drvdata(dev);
struct lpass_variant *v = drvdata->variant;
int i;
if (reg == LPASS_HDMI_TX_CTL_ADDR(v))
return true;
if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v))
return true;
if (reg == LPASS_HDMI_TX_VBIT_CTL_ADDR(v))
return true;
for (i = 0; i < v->hdmi_rdma_channels; i++) {
if (reg == LPASS_HDMI_TX_CH_LSB_ADDR(v, i))
return true;
if (reg == LPASS_HDMI_TX_CH_MSB_ADDR(v, i))
return true;
if (reg == LPASS_HDMI_TX_DMA_ADDR(v, i))
return true;
}
if (reg == LPASS_HDMI_TX_PARITY_ADDR(v))
return true;
if (reg == LPASS_HDMI_TX_DP_ADDR(v))
return true;
if (reg == LPASS_HDMI_TX_SSTREAM_ADDR(v))
return true;
if (reg == LPASS_HDMITX_APP_IRQEN_REG(v))
return true;
if (reg == LPASS_HDMITX_APP_IRQSTAT_REG(v))
return true;
for (i = 0; i < v->hdmi_rdma_channels; ++i) {
if (reg == LPAIF_HDMI_RDMACTL_REG(v, i))
return true;
if (reg == LPAIF_HDMI_RDMABASE_REG(v, i))
return true;
if (reg == LPAIF_HDMI_RDMABUFF_REG(v, i))
return true;
if (reg == LPAIF_HDMI_RDMAPER_REG(v, i))
return true;
if (reg == LPAIF_HDMI_RDMACURR_REG(v, i))
return true;
}
return false;
}
static bool lpass_hdmi_regmap_volatile(struct device *dev, unsigned int reg)
{
struct lpass_data *drvdata = dev_get_drvdata(dev);
struct lpass_variant *v = drvdata->variant;
int i;
if (reg == LPASS_HDMITX_APP_IRQSTAT_REG(v))
return true;
if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v))
return true;
if (reg == LPASS_HDMI_TX_VBIT_CTL_ADDR(v))
return true;
if (reg == LPASS_HDMI_TX_PARITY_ADDR(v))
return true;
for (i = 0; i < v->hdmi_rdma_channels; ++i) {
if (reg == LPAIF_HDMI_RDMACURR_REG(v, i))
return true;
if (reg == LPASS_HDMI_TX_DMA_ADDR(v, i))
return true;
if (reg == LPASS_HDMI_TX_CH_LSB_ADDR(v, i))
return true;
if (reg == LPASS_HDMI_TX_CH_MSB_ADDR(v, i))
return true;
}
return false;
}
static struct regmap_config lpass_hdmi_regmap_config = {
.name = "lpass_hdmi",
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.writeable_reg = lpass_hdmi_regmap_writeable,
.readable_reg = lpass_hdmi_regmap_readable,
.volatile_reg = lpass_hdmi_regmap_volatile,
.cache_type = REGCACHE_FLAT,
};
static bool __lpass_rxtx_regmap_accessible(struct device *dev, unsigned int reg, bool rw)
{
struct lpass_data *drvdata = dev_get_drvdata(dev);
struct lpass_variant *v = drvdata->variant;
int i;
for (i = 0; i < v->rxtx_irq_ports; ++i) {
if (reg == LPAIF_RXTX_IRQCLEAR_REG(v, i))
return true;
if (reg == LPAIF_RXTX_IRQEN_REG(v, i))
return true;
if (reg == LPAIF_RXTX_IRQSTAT_REG(v, i))
return true;
}
for (i = 0; i < v->rxtx_rdma_channels; ++i) {
if (reg == LPAIF_CDC_RXTX_RDMACTL_REG(v, i, LPASS_CDC_DMA_RX0))
return true;
if (reg == LPAIF_CDC_RXTX_RDMABASE_REG(v, i, LPASS_CDC_DMA_RX0))
return true;
if (reg == LPAIF_CDC_RXTX_RDMABUFF_REG(v, i, LPASS_CDC_DMA_RX0))
return true;
if (rw == LPASS_REG_READ) {
if (reg == LPAIF_CDC_RXTX_RDMACURR_REG(v, i, LPASS_CDC_DMA_RX0))
return true;
}
if (reg == LPAIF_CDC_RXTX_RDMAPER_REG(v, i, LPASS_CDC_DMA_RX0))
return true;
if (reg == LPAIF_CDC_RXTX_RDMA_INTF_REG(v, i, LPASS_CDC_DMA_RX0))
return true;
}
for (i = 0; i < v->rxtx_wrdma_channels; ++i) {
if (reg == LPAIF_CDC_RXTX_WRDMACTL_REG(v, i + v->rxtx_wrdma_channel_start,
LPASS_CDC_DMA_TX3))
return true;
if (reg == LPAIF_CDC_RXTX_WRDMABASE_REG(v, i + v->rxtx_wrdma_channel_start,
LPASS_CDC_DMA_TX3))
return true;
if (reg == LPAIF_CDC_RXTX_WRDMABUFF_REG(v, i + v->rxtx_wrdma_channel_start,
LPASS_CDC_DMA_TX3))
return true;
if (rw == LPASS_REG_READ) {
if (reg == LPAIF_CDC_RXTX_WRDMACURR_REG(v, i, LPASS_CDC_DMA_RX0))
return true;
}
if (reg == LPAIF_CDC_RXTX_WRDMAPER_REG(v, i + v->rxtx_wrdma_channel_start,
LPASS_CDC_DMA_TX3))
return true;
if (reg == LPAIF_CDC_RXTX_WRDMA_INTF_REG(v, i + v->rxtx_wrdma_channel_start,
LPASS_CDC_DMA_TX3))
return true;
}
return false;
}
static bool lpass_rxtx_regmap_writeable(struct device *dev, unsigned int reg)
{
return __lpass_rxtx_regmap_accessible(dev, reg, LPASS_REG_WRITE);
}
static bool lpass_rxtx_regmap_readable(struct device *dev, unsigned int reg)
{
return __lpass_rxtx_regmap_accessible(dev, reg, LPASS_REG_READ);
}
static bool lpass_rxtx_regmap_volatile(struct device *dev, unsigned int reg)
{
struct lpass_data *drvdata = dev_get_drvdata(dev);
struct lpass_variant *v = drvdata->variant;
int i;
for (i = 0; i < v->rxtx_irq_ports; ++i) {
if (reg == LPAIF_RXTX_IRQCLEAR_REG(v, i))
return true;
if (reg == LPAIF_RXTX_IRQSTAT_REG(v, i))
return true;
}
for (i = 0; i < v->rxtx_rdma_channels; ++i)
if (reg == LPAIF_CDC_RXTX_RDMACURR_REG(v, i, LPASS_CDC_DMA_RX0))
return true;
for (i = 0; i < v->rxtx_wrdma_channels; ++i)
if (reg == LPAIF_CDC_RXTX_WRDMACURR_REG(v, i + v->rxtx_wrdma_channel_start,
LPASS_CDC_DMA_TX3))
return true;
return false;
}
static bool __lpass_va_regmap_accessible(struct device *dev, unsigned int reg, bool rw)
{
struct lpass_data *drvdata = dev_get_drvdata(dev);
struct lpass_variant *v = drvdata->variant;
int i;
for (i = 0; i < v->va_irq_ports; ++i) {
if (reg == LPAIF_VA_IRQCLEAR_REG(v, i))
return true;
if (reg == LPAIF_VA_IRQEN_REG(v, i))
return true;
if (reg == LPAIF_VA_IRQSTAT_REG(v, i))
return true;
}
for (i = 0; i < v->va_wrdma_channels; ++i) {
if (reg == LPAIF_CDC_VA_WRDMACTL_REG(v, i + v->va_wrdma_channel_start,
LPASS_CDC_DMA_VA_TX0))
return true;
if (reg == LPAIF_CDC_VA_WRDMABASE_REG(v, i + v->va_wrdma_channel_start,
LPASS_CDC_DMA_VA_TX0))
return true;
if (reg == LPAIF_CDC_VA_WRDMABUFF_REG(v, i + v->va_wrdma_channel_start,
LPASS_CDC_DMA_VA_TX0))
return true;
if (rw == LPASS_REG_READ) {
if (reg == LPAIF_CDC_VA_WRDMACURR_REG(v, i + v->va_wrdma_channel_start,
LPASS_CDC_DMA_VA_TX0))
return true;
}
if (reg == LPAIF_CDC_VA_WRDMAPER_REG(v, i + v->va_wrdma_channel_start,
LPASS_CDC_DMA_VA_TX0))
return true;
if (reg == LPAIF_CDC_VA_WRDMA_INTF_REG(v, i + v->va_wrdma_channel_start,
LPASS_CDC_DMA_VA_TX0))
return true;
}
return false;
}
static bool lpass_va_regmap_writeable(struct device *dev, unsigned int reg)
{
return __lpass_va_regmap_accessible(dev, reg, LPASS_REG_WRITE);
}
static bool lpass_va_regmap_readable(struct device *dev, unsigned int reg)
{
return __lpass_va_regmap_accessible(dev, reg, LPASS_REG_READ);
}
static bool lpass_va_regmap_volatile(struct device *dev, unsigned int reg)
{
struct lpass_data *drvdata = dev_get_drvdata(dev);
struct lpass_variant *v = drvdata->variant;
int i;
for (i = 0; i < v->va_irq_ports; ++i) {
if (reg == LPAIF_VA_IRQCLEAR_REG(v, i))
return true;
if (reg == LPAIF_VA_IRQSTAT_REG(v, i))
return true;
}
for (i = 0; i < v->va_wrdma_channels; ++i) {
if (reg == LPAIF_CDC_VA_WRDMACURR_REG(v, i + v->va_wrdma_channel_start,
LPASS_CDC_DMA_VA_TX0))
return true;
}
return false;
}
static struct regmap_config lpass_rxtx_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.writeable_reg = lpass_rxtx_regmap_writeable,
.readable_reg = lpass_rxtx_regmap_readable,
.volatile_reg = lpass_rxtx_regmap_volatile,
.cache_type = REGCACHE_FLAT,
};
static struct regmap_config lpass_va_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.writeable_reg = lpass_va_regmap_writeable,
.readable_reg = lpass_va_regmap_readable,
.volatile_reg = lpass_va_regmap_volatile,
.cache_type = REGCACHE_FLAT,
};
static unsigned int of_lpass_cpu_parse_sd_lines(struct device *dev,
struct device_node *node,
const char *name)
{
unsigned int lines[LPASS_CPU_MAX_MI2S_LINES];
unsigned int sd_line_mask = 0;
int num_lines, i;
num_lines = of_property_read_variable_u32_array(node, name, lines, 0,
LPASS_CPU_MAX_MI2S_LINES);
if (num_lines < 0)
return LPAIF_I2SCTL_MODE_NONE;
for (i = 0; i < num_lines; i++)
sd_line_mask |= BIT(lines[i]);
switch (sd_line_mask) {
case LPASS_CPU_I2S_SD0_MASK:
return LPAIF_I2SCTL_MODE_SD0;
case LPASS_CPU_I2S_SD1_MASK:
return LPAIF_I2SCTL_MODE_SD1;
case LPASS_CPU_I2S_SD2_MASK:
return LPAIF_I2SCTL_MODE_SD2;
case LPASS_CPU_I2S_SD3_MASK:
return LPAIF_I2SCTL_MODE_SD3;
case LPASS_CPU_I2S_SD0_1_MASK:
return LPAIF_I2SCTL_MODE_QUAD01;
case LPASS_CPU_I2S_SD2_3_MASK:
return LPAIF_I2SCTL_MODE_QUAD23;
case LPASS_CPU_I2S_SD0_1_2_MASK:
return LPAIF_I2SCTL_MODE_6CH;
case LPASS_CPU_I2S_SD0_1_2_3_MASK:
return LPAIF_I2SCTL_MODE_8CH;
default:
dev_err(dev, "Unsupported SD line mask: %#x\n", sd_line_mask);
return LPAIF_I2SCTL_MODE_NONE;
}
}
static void of_lpass_cpu_parse_dai_data(struct device *dev,
struct lpass_data *data)
{
struct device_node *node;
int ret, i, id;
/* Allow all channels by default for backwards compatibility */
for (i = 0; i < data->variant->num_dai; i++) {
id = data->variant->dai_driver[i].id;
data->mi2s_playback_sd_mode[id] = LPAIF_I2SCTL_MODE_8CH;
data->mi2s_capture_sd_mode[id] = LPAIF_I2SCTL_MODE_8CH;
}
for_each_child_of_node(dev->of_node, node) {
ret = of_property_read_u32(node, "reg", &id);
if (ret || id < 0) {
dev_err(dev, "valid dai id not found: %d\n", ret);
continue;
}
if (id == LPASS_DP_RX) {
data->hdmi_port_enable = 1;
} else if (is_cdc_dma_port(id)) {
data->codec_dma_enable = 1;
} else {
data->mi2s_playback_sd_mode[id] =
of_lpass_cpu_parse_sd_lines(dev, node,
"qcom,playback-sd-lines");
data->mi2s_capture_sd_mode[id] =
of_lpass_cpu_parse_sd_lines(dev, node,
"qcom,capture-sd-lines");
}
}
}
static int of_lpass_cdc_dma_clks_parse(struct device *dev,
struct lpass_data *data)
{
data->codec_mem0 = devm_clk_get(dev, "audio_cc_codec_mem0");
if (IS_ERR(data->codec_mem0))
return PTR_ERR(data->codec_mem0);
data->codec_mem1 = devm_clk_get(dev, "audio_cc_codec_mem1");
if (IS_ERR(data->codec_mem1))
return PTR_ERR(data->codec_mem1);
data->codec_mem2 = devm_clk_get(dev, "audio_cc_codec_mem2");
if (IS_ERR(data->codec_mem2))
return PTR_ERR(data->codec_mem2);
data->va_mem0 = devm_clk_get(dev, "aon_cc_va_mem0");
if (IS_ERR(data->va_mem0))
return PTR_ERR(data->va_mem0);
return 0;
}
int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev)
{
struct lpass_data *drvdata;
struct device_node *dsp_of_node;
struct resource *res;
struct lpass_variant *variant;
struct device *dev = &pdev->dev;
const struct of_device_id *match;
int ret, i, dai_id;
dsp_of_node = of_parse_phandle(pdev->dev.of_node, "qcom,adsp", 0);
if (dsp_of_node) {
dev_err(dev, "DSP exists and holds audio resources\n");
of_node_put(dsp_of_node);
return -EBUSY;
}
drvdata = devm_kzalloc(dev, sizeof(struct lpass_data), GFP_KERNEL);
if (!drvdata)
return -ENOMEM;
platform_set_drvdata(pdev, drvdata);
match = of_match_device(dev->driver->of_match_table, dev);
if (!match || !match->data)
return -EINVAL;
if (of_device_is_compatible(dev->of_node, "qcom,lpass-cpu-apq8016")) {
dev_warn(dev, "%s compatible is deprecated\n",
match->compatible);
}
drvdata->variant = (struct lpass_variant *)match->data;
variant = drvdata->variant;
of_lpass_cpu_parse_dai_data(dev, drvdata);
if (drvdata->codec_dma_enable) {
drvdata->rxtx_lpaif =
devm_platform_ioremap_resource_byname(pdev, "lpass-rxtx-lpaif");
if (IS_ERR(drvdata->rxtx_lpaif))
return PTR_ERR(drvdata->rxtx_lpaif);
drvdata->va_lpaif = devm_platform_ioremap_resource_byname(pdev, "lpass-va-lpaif");
if (IS_ERR(drvdata->va_lpaif))
return PTR_ERR(drvdata->va_lpaif);
lpass_rxtx_regmap_config.max_register = LPAIF_CDC_RXTX_WRDMAPER_REG(variant,
variant->rxtx_wrdma_channels +
variant->rxtx_wrdma_channel_start, LPASS_CDC_DMA_TX3);
drvdata->rxtx_lpaif_map = devm_regmap_init_mmio(dev, drvdata->rxtx_lpaif,
&lpass_rxtx_regmap_config);
if (IS_ERR(drvdata->rxtx_lpaif_map))
return PTR_ERR(drvdata->rxtx_lpaif_map);
lpass_va_regmap_config.max_register = LPAIF_CDC_VA_WRDMAPER_REG(variant,
variant->va_wrdma_channels +
variant->va_wrdma_channel_start, LPASS_CDC_DMA_VA_TX0);
drvdata->va_lpaif_map = devm_regmap_init_mmio(dev, drvdata->va_lpaif,
&lpass_va_regmap_config);
if (IS_ERR(drvdata->va_lpaif_map))
return PTR_ERR(drvdata->va_lpaif_map);
ret = of_lpass_cdc_dma_clks_parse(dev, drvdata);
if (ret) {
dev_err(dev, "failed to get cdc dma clocks %d\n", ret);
return ret;
}
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpass-rxtx-cdc-dma-lpm");
drvdata->rxtx_cdc_dma_lpm_buf = res->start;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpass-va-cdc-dma-lpm");
drvdata->va_cdc_dma_lpm_buf = res->start;
}
drvdata->lpaif = devm_platform_ioremap_resource_byname(pdev, "lpass-lpaif");
if (IS_ERR(drvdata->lpaif))
return PTR_ERR(drvdata->lpaif);
lpass_cpu_regmap_config.max_register = LPAIF_WRDMAPER_REG(variant,
variant->wrdma_channels +
variant->wrdma_channel_start);
drvdata->lpaif_map = devm_regmap_init_mmio(dev, drvdata->lpaif,
&lpass_cpu_regmap_config);
if (IS_ERR(drvdata->lpaif_map)) {
dev_err(dev, "error initializing regmap: %ld\n",
PTR_ERR(drvdata->lpaif_map));
return PTR_ERR(drvdata->lpaif_map);
}
if (drvdata->hdmi_port_enable) {
drvdata->hdmiif = devm_platform_ioremap_resource_byname(pdev, "lpass-hdmiif");
if (IS_ERR(drvdata->hdmiif))
return PTR_ERR(drvdata->hdmiif);
lpass_hdmi_regmap_config.max_register = LPAIF_HDMI_RDMAPER_REG(variant,
variant->hdmi_rdma_channels - 1);
drvdata->hdmiif_map = devm_regmap_init_mmio(dev, drvdata->hdmiif,
&lpass_hdmi_regmap_config);
if (IS_ERR(drvdata->hdmiif_map)) {
dev_err(dev, "error initializing regmap: %ld\n",
PTR_ERR(drvdata->hdmiif_map));
return PTR_ERR(drvdata->hdmiif_map);
}
}
if (variant->init) {
ret = variant->init(pdev);
if (ret) {
dev_err(dev, "error initializing variant: %d\n", ret);
return ret;
}
}
for (i = 0; i < variant->num_dai; i++) {
dai_id = variant->dai_driver[i].id;
if (dai_id == LPASS_DP_RX || is_cdc_dma_port(dai_id))
continue;
drvdata->mi2s_osr_clk[dai_id] = devm_clk_get_optional(dev,
variant->dai_osr_clk_names[i]);
drvdata->mi2s_bit_clk[dai_id] = devm_clk_get(dev,
variant->dai_bit_clk_names[i]);
if (IS_ERR(drvdata->mi2s_bit_clk[dai_id])) {
dev_err(dev,
"error getting %s: %ld\n",
variant->dai_bit_clk_names[i],
PTR_ERR(drvdata->mi2s_bit_clk[dai_id]));
return PTR_ERR(drvdata->mi2s_bit_clk[dai_id]);
}
if (drvdata->mi2s_playback_sd_mode[dai_id] ==
LPAIF_I2SCTL_MODE_QUAD01) {
variant->dai_driver[dai_id].playback.channels_min = 4;
variant->dai_driver[dai_id].playback.channels_max = 4;
}
}
/* Allocation for i2sctl regmap fields */
drvdata->i2sctl = devm_kzalloc(&pdev->dev, sizeof(struct lpaif_i2sctl),
GFP_KERNEL);
/* Initialize bitfields for dai I2SCTL register */
ret = lpass_cpu_init_i2sctl_bitfields(dev, drvdata->i2sctl,
drvdata->lpaif_map);
if (ret) {
dev_err(dev, "error init i2sctl field: %d\n", ret);
return ret;
}
if (drvdata->hdmi_port_enable) {
ret = lpass_hdmi_init_bitfields(dev, drvdata->hdmiif_map);
if (ret) {
dev_err(dev, "%s error hdmi init failed\n", __func__);
return ret;
}
}
ret = devm_snd_soc_register_component(dev,
&lpass_cpu_comp_driver,
variant->dai_driver,
variant->num_dai);
if (ret) {
dev_err(dev, "error registering cpu driver: %d\n", ret);
goto err;
}
ret = asoc_qcom_lpass_platform_register(pdev);
if (ret) {
dev_err(dev, "error registering platform driver: %d\n", ret);
goto err;
}
err:
return ret;
}
EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_probe);
int asoc_qcom_lpass_cpu_platform_remove(struct platform_device *pdev)
{
struct lpass_data *drvdata = platform_get_drvdata(pdev);
if (drvdata->variant->exit)
drvdata->variant->exit(pdev);
return 0;
}
EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_remove);
void asoc_qcom_lpass_cpu_platform_shutdown(struct platform_device *pdev)
{
struct lpass_data *drvdata = platform_get_drvdata(pdev);
if (drvdata->variant->exit)
drvdata->variant->exit(pdev);
}
EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_shutdown);
MODULE_DESCRIPTION("QTi LPASS CPU Driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/qcom/lpass-cpu.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2015 The Linux Foundation. All rights reserved.
*/
#include <linux/device.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/clk.h>
#include <linux/platform_device.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/jack.h>
#include <sound/soc.h>
#include <uapi/linux/input-event-codes.h>
#include <dt-bindings/sound/apq8016-lpass.h>
#include "common.h"
#include "qdsp6/q6afe.h"
#define MI2S_COUNT (MI2S_QUATERNARY + 1)
struct apq8016_sbc_data {
struct snd_soc_card card;
void __iomem *mic_iomux;
void __iomem *spkr_iomux;
struct snd_soc_jack jack;
bool jack_setup;
int mi2s_clk_count[MI2S_COUNT];
};
#define MIC_CTRL_TER_WS_SLAVE_SEL BIT(21)
#define MIC_CTRL_QUA_WS_SLAVE_SEL_10 BIT(17)
#define MIC_CTRL_TLMM_SCLK_EN BIT(1)
#define SPKR_CTL_PRI_WS_SLAVE_SEL_11 (BIT(17) | BIT(16))
#define SPKR_CTL_TLMM_MCLK_EN BIT(1)
#define SPKR_CTL_TLMM_SCLK_EN BIT(2)
#define SPKR_CTL_TLMM_DATA1_EN BIT(3)
#define SPKR_CTL_TLMM_WS_OUT_SEL_MASK GENMASK(7, 6)
#define SPKR_CTL_TLMM_WS_OUT_SEL_SEC BIT(6)
#define SPKR_CTL_TLMM_WS_EN_SEL_MASK GENMASK(19, 18)
#define SPKR_CTL_TLMM_WS_EN_SEL_SEC BIT(18)
#define DEFAULT_MCLK_RATE 9600000
#define MI2S_BCLK_RATE 1536000
static struct snd_soc_jack_pin apq8016_sbc_jack_pins[] = {
{
.pin = "Mic Jack",
.mask = SND_JACK_MICROPHONE,
},
{
.pin = "Headphone Jack",
.mask = SND_JACK_HEADPHONE,
},
};
static int apq8016_dai_init(struct snd_soc_pcm_runtime *rtd, int mi2s)
{
struct snd_soc_dai *codec_dai;
struct snd_soc_component *component;
struct snd_soc_card *card = rtd->card;
struct apq8016_sbc_data *pdata = snd_soc_card_get_drvdata(card);
int i, rval;
u32 value;
switch (mi2s) {
case MI2S_PRIMARY:
writel(readl(pdata->spkr_iomux) | SPKR_CTL_PRI_WS_SLAVE_SEL_11,
pdata->spkr_iomux);
break;
case MI2S_QUATERNARY:
/* Configure the Quat MI2S to TLMM */
writel(readl(pdata->mic_iomux) | MIC_CTRL_QUA_WS_SLAVE_SEL_10 |
MIC_CTRL_TLMM_SCLK_EN,
pdata->mic_iomux);
break;
case MI2S_SECONDARY:
/* Clear TLMM_WS_OUT_SEL and TLMM_WS_EN_SEL fields */
value = readl(pdata->spkr_iomux) &
~(SPKR_CTL_TLMM_WS_OUT_SEL_MASK | SPKR_CTL_TLMM_WS_EN_SEL_MASK);
/* Configure the Sec MI2S to TLMM */
writel(value | SPKR_CTL_TLMM_MCLK_EN | SPKR_CTL_TLMM_SCLK_EN |
SPKR_CTL_TLMM_DATA1_EN | SPKR_CTL_TLMM_WS_OUT_SEL_SEC |
SPKR_CTL_TLMM_WS_EN_SEL_SEC, pdata->spkr_iomux);
break;
case MI2S_TERTIARY:
writel(readl(pdata->mic_iomux) | MIC_CTRL_TER_WS_SLAVE_SEL |
MIC_CTRL_TLMM_SCLK_EN,
pdata->mic_iomux);
break;
default:
dev_err(card->dev, "unsupported cpu dai configuration\n");
return -EINVAL;
}
if (!pdata->jack_setup) {
struct snd_jack *jack;
rval = snd_soc_card_jack_new_pins(card, "Headset Jack",
SND_JACK_HEADSET |
SND_JACK_HEADPHONE |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3 |
SND_JACK_BTN_4,
&pdata->jack,
apq8016_sbc_jack_pins,
ARRAY_SIZE(apq8016_sbc_jack_pins));
if (rval < 0) {
dev_err(card->dev, "Unable to add Headphone Jack\n");
return rval;
}
jack = pdata->jack.jack;
snd_jack_set_key(jack, SND_JACK_BTN_0, KEY_PLAYPAUSE);
snd_jack_set_key(jack, SND_JACK_BTN_1, KEY_VOICECOMMAND);
snd_jack_set_key(jack, SND_JACK_BTN_2, KEY_VOLUMEUP);
snd_jack_set_key(jack, SND_JACK_BTN_3, KEY_VOLUMEDOWN);
pdata->jack_setup = true;
}
for_each_rtd_codec_dais(rtd, i, codec_dai) {
component = codec_dai->component;
/* Set default mclk for internal codec */
rval = snd_soc_component_set_sysclk(component, 0, 0, DEFAULT_MCLK_RATE,
SND_SOC_CLOCK_IN);
if (rval != 0 && rval != -ENOTSUPP) {
dev_warn(card->dev, "Failed to set mclk: %d\n", rval);
return rval;
}
rval = snd_soc_component_set_jack(component, &pdata->jack, NULL);
if (rval != 0 && rval != -ENOTSUPP) {
dev_warn(card->dev, "Failed to set jack: %d\n", rval);
return rval;
}
}
return 0;
}
static int apq8016_sbc_dai_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
return apq8016_dai_init(rtd, cpu_dai->id);
}
static void apq8016_sbc_add_ops(struct snd_soc_card *card)
{
struct snd_soc_dai_link *link;
int i;
for_each_card_prelinks(card, i, link)
link->init = apq8016_sbc_dai_init;
}
static int qdsp6_dai_get_lpass_id(struct snd_soc_dai *cpu_dai)
{
switch (cpu_dai->id) {
case PRIMARY_MI2S_RX:
case PRIMARY_MI2S_TX:
return MI2S_PRIMARY;
case SECONDARY_MI2S_RX:
case SECONDARY_MI2S_TX:
return MI2S_SECONDARY;
case TERTIARY_MI2S_RX:
case TERTIARY_MI2S_TX:
return MI2S_TERTIARY;
case QUATERNARY_MI2S_RX:
case QUATERNARY_MI2S_TX:
return MI2S_QUATERNARY;
default:
return -EINVAL;
}
}
static int msm8916_qdsp6_dai_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_BP_FP);
return apq8016_dai_init(rtd, qdsp6_dai_get_lpass_id(cpu_dai));
}
static int msm8916_qdsp6_startup(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_card *card = rtd->card;
struct apq8016_sbc_data *data = snd_soc_card_get_drvdata(card);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
int mi2s, ret;
mi2s = qdsp6_dai_get_lpass_id(cpu_dai);
if (mi2s < 0)
return mi2s;
if (++data->mi2s_clk_count[mi2s] > 1)
return 0;
ret = snd_soc_dai_set_sysclk(cpu_dai, LPAIF_BIT_CLK, MI2S_BCLK_RATE, 0);
if (ret)
dev_err(card->dev, "Failed to enable LPAIF bit clk: %d\n", ret);
return ret;
}
static void msm8916_qdsp6_shutdown(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_card *card = rtd->card;
struct apq8016_sbc_data *data = snd_soc_card_get_drvdata(card);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
int mi2s, ret;
mi2s = qdsp6_dai_get_lpass_id(cpu_dai);
if (mi2s < 0)
return;
if (--data->mi2s_clk_count[mi2s] > 0)
return;
ret = snd_soc_dai_set_sysclk(cpu_dai, LPAIF_BIT_CLK, 0, 0);
if (ret)
dev_err(card->dev, "Failed to disable LPAIF bit clk: %d\n", ret);
}
static const struct snd_soc_ops msm8916_qdsp6_be_ops = {
.startup = msm8916_qdsp6_startup,
.shutdown = msm8916_qdsp6_shutdown,
};
static int msm8916_qdsp6_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
struct snd_pcm_hw_params *params)
{
struct snd_interval *rate = hw_param_interval(params,
SNDRV_PCM_HW_PARAM_RATE);
struct snd_interval *channels = hw_param_interval(params,
SNDRV_PCM_HW_PARAM_CHANNELS);
struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
rate->min = rate->max = 48000;
channels->min = channels->max = 2;
snd_mask_set_format(fmt, SNDRV_PCM_FORMAT_S16_LE);
return 0;
}
static void msm8916_qdsp6_add_ops(struct snd_soc_card *card)
{
struct snd_soc_dai_link *link;
int i;
/* Make it obvious to userspace that QDSP6 is used */
card->components = "qdsp6";
for_each_card_prelinks(card, i, link) {
if (link->no_pcm) {
link->init = msm8916_qdsp6_dai_init;
link->ops = &msm8916_qdsp6_be_ops;
link->be_hw_params_fixup = msm8916_qdsp6_be_hw_params_fixup;
}
}
}
static const struct snd_kcontrol_new apq8016_sbc_snd_controls[] = {
SOC_DAPM_PIN_SWITCH("Headphone Jack"),
SOC_DAPM_PIN_SWITCH("Mic Jack"),
};
static const struct snd_soc_dapm_widget apq8016_sbc_dapm_widgets[] = {
SND_SOC_DAPM_HP("Headphone Jack", NULL),
SND_SOC_DAPM_MIC("Mic Jack", NULL),
SND_SOC_DAPM_MIC("Handset Mic", NULL),
SND_SOC_DAPM_MIC("Headset Mic", NULL),
SND_SOC_DAPM_MIC("Secondary Mic", NULL),
SND_SOC_DAPM_MIC("Digital Mic1", NULL),
SND_SOC_DAPM_MIC("Digital Mic2", NULL),
};
static int apq8016_sbc_platform_probe(struct platform_device *pdev)
{
void (*add_ops)(struct snd_soc_card *card);
struct device *dev = &pdev->dev;
struct snd_soc_card *card;
struct apq8016_sbc_data *data;
int ret;
add_ops = device_get_match_data(&pdev->dev);
if (!add_ops)
return -EINVAL;
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
card = &data->card;
card->dev = dev;
card->owner = THIS_MODULE;
card->dapm_widgets = apq8016_sbc_dapm_widgets;
card->num_dapm_widgets = ARRAY_SIZE(apq8016_sbc_dapm_widgets);
card->controls = apq8016_sbc_snd_controls;
card->num_controls = ARRAY_SIZE(apq8016_sbc_snd_controls);
ret = qcom_snd_parse_of(card);
if (ret)
return ret;
data->mic_iomux = devm_platform_ioremap_resource_byname(pdev, "mic-iomux");
if (IS_ERR(data->mic_iomux))
return PTR_ERR(data->mic_iomux);
data->spkr_iomux = devm_platform_ioremap_resource_byname(pdev, "spkr-iomux");
if (IS_ERR(data->spkr_iomux))
return PTR_ERR(data->spkr_iomux);
snd_soc_card_set_drvdata(card, data);
add_ops(card);
return devm_snd_soc_register_card(&pdev->dev, card);
}
static const struct of_device_id apq8016_sbc_device_id[] __maybe_unused = {
{ .compatible = "qcom,apq8016-sbc-sndcard", .data = apq8016_sbc_add_ops },
{ .compatible = "qcom,msm8916-qdsp6-sndcard", .data = msm8916_qdsp6_add_ops },
{},
};
MODULE_DEVICE_TABLE(of, apq8016_sbc_device_id);
static struct platform_driver apq8016_sbc_platform_driver = {
.driver = {
.name = "qcom-apq8016-sbc",
.of_match_table = of_match_ptr(apq8016_sbc_device_id),
},
.probe = apq8016_sbc_platform_probe,
};
module_platform_driver(apq8016_sbc_platform_driver);
MODULE_AUTHOR("Srinivas Kandagatla <[email protected]");
MODULE_DESCRIPTION("APQ8016 ASoC Machine Driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/qcom/apq8016_sbc.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
*
* storm.c -- ALSA SoC machine driver for QTi ipq806x-based Storm board
*/
#include <linux/device.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#define STORM_SYSCLK_MULT 4
static int storm_ops_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
struct snd_soc_card *card = soc_runtime->card;
snd_pcm_format_t format = params_format(params);
unsigned int rate = params_rate(params);
unsigned int sysclk_freq;
int bitwidth, ret;
bitwidth = snd_pcm_format_width(format);
if (bitwidth < 0) {
dev_err(card->dev, "invalid bit width given: %d\n", bitwidth);
return bitwidth;
}
/*
* as the CPU DAI is the I2S bus master and no system clock is needed by
* the MAX98357a DAC, simply set the system clock to be a constant
* multiple of the bit clock for the clock divider
*/
sysclk_freq = rate * bitwidth * 2 * STORM_SYSCLK_MULT;
ret = snd_soc_dai_set_sysclk(asoc_rtd_to_cpu(soc_runtime, 0), 0, sysclk_freq, 0);
if (ret) {
dev_err(card->dev, "error setting sysclk to %u: %d\n",
sysclk_freq, ret);
return ret;
}
return 0;
}
static const struct snd_soc_ops storm_soc_ops = {
.hw_params = storm_ops_hw_params,
};
SND_SOC_DAILINK_DEFS(hifi,
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "HiFi")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
static struct snd_soc_dai_link storm_dai_link = {
.name = "Primary",
.stream_name = "Primary",
.ops = &storm_soc_ops,
SND_SOC_DAILINK_REG(hifi),
};
static int storm_parse_of(struct snd_soc_card *card)
{
struct snd_soc_dai_link *dai_link = card->dai_link;
struct device_node *np = card->dev->of_node;
dai_link->cpus->of_node = of_parse_phandle(np, "cpu", 0);
if (!dai_link->cpus->of_node) {
dev_err(card->dev, "error getting cpu phandle\n");
return -EINVAL;
}
dai_link->platforms->of_node = dai_link->cpus->of_node;
dai_link->codecs->of_node = of_parse_phandle(np, "codec", 0);
if (!dai_link->codecs->of_node) {
dev_err(card->dev, "error getting codec phandle\n");
return -EINVAL;
}
return 0;
}
static int storm_platform_probe(struct platform_device *pdev)
{
struct snd_soc_card *card;
int ret;
card = devm_kzalloc(&pdev->dev, sizeof(*card), GFP_KERNEL);
if (!card)
return -ENOMEM;
card->dev = &pdev->dev;
card->owner = THIS_MODULE;
ret = snd_soc_of_parse_card_name(card, "qcom,model");
if (ret) {
dev_err(&pdev->dev, "error parsing card name: %d\n", ret);
return ret;
}
card->dai_link = &storm_dai_link;
card->num_links = 1;
ret = storm_parse_of(card);
if (ret) {
dev_err(&pdev->dev, "error resolving dai links: %d\n", ret);
return ret;
}
ret = devm_snd_soc_register_card(&pdev->dev, card);
if (ret)
dev_err(&pdev->dev, "error registering soundcard: %d\n", ret);
return ret;
}
#ifdef CONFIG_OF
static const struct of_device_id storm_device_id[] = {
{ .compatible = "google,storm-audio" },
{},
};
MODULE_DEVICE_TABLE(of, storm_device_id);
#endif
static struct platform_driver storm_platform_driver = {
.driver = {
.name = "storm-audio",
.of_match_table =
of_match_ptr(storm_device_id),
},
.probe = storm_platform_probe,
};
module_platform_driver(storm_platform_driver);
MODULE_DESCRIPTION("QTi IPQ806x-based Storm Machine Driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/qcom/storm.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
*
* lpass-platform.c -- ALSA SoC platform driver for QTi LPASS
*/
#include <linux/dma-mapping.h>
#include <linux/export.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <sound/pcm_params.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include "lpass-lpaif-reg.h"
#include "lpass.h"
#define DRV_NAME "lpass-platform"
#define LPASS_PLATFORM_BUFFER_SIZE (24 * 2 * 1024)
#define LPASS_PLATFORM_PERIODS 2
#define LPASS_RXTX_CDC_DMA_LPM_BUFF_SIZE (8 * 1024)
#define LPASS_VA_CDC_DMA_LPM_BUFF_SIZE (12 * 1024)
#define LPASS_CDC_DMA_REGISTER_FIELDS_MAX 15
static const struct snd_pcm_hardware lpass_platform_pcm_hardware = {
.info = SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_PAUSE |
SNDRV_PCM_INFO_RESUME,
.formats = SNDRV_PCM_FMTBIT_S16 |
SNDRV_PCM_FMTBIT_S24 |
SNDRV_PCM_FMTBIT_S32,
.rates = SNDRV_PCM_RATE_8000_192000,
.rate_min = 8000,
.rate_max = 192000,
.channels_min = 1,
.channels_max = 8,
.buffer_bytes_max = LPASS_PLATFORM_BUFFER_SIZE,
.period_bytes_max = LPASS_PLATFORM_BUFFER_SIZE /
LPASS_PLATFORM_PERIODS,
.period_bytes_min = LPASS_PLATFORM_BUFFER_SIZE /
LPASS_PLATFORM_PERIODS,
.periods_min = LPASS_PLATFORM_PERIODS,
.periods_max = LPASS_PLATFORM_PERIODS,
.fifo_size = 0,
};
static const struct snd_pcm_hardware lpass_platform_rxtx_hardware = {
.info = SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_PAUSE |
SNDRV_PCM_INFO_RESUME,
.formats = SNDRV_PCM_FMTBIT_S16 |
SNDRV_PCM_FMTBIT_S24 |
SNDRV_PCM_FMTBIT_S32,
.rates = SNDRV_PCM_RATE_8000_192000,
.rate_min = 8000,
.rate_max = 192000,
.channels_min = 1,
.channels_max = 8,
.buffer_bytes_max = LPASS_RXTX_CDC_DMA_LPM_BUFF_SIZE,
.period_bytes_max = LPASS_RXTX_CDC_DMA_LPM_BUFF_SIZE /
LPASS_PLATFORM_PERIODS,
.period_bytes_min = LPASS_RXTX_CDC_DMA_LPM_BUFF_SIZE /
LPASS_PLATFORM_PERIODS,
.periods_min = LPASS_PLATFORM_PERIODS,
.periods_max = LPASS_PLATFORM_PERIODS,
.fifo_size = 0,
};
static const struct snd_pcm_hardware lpass_platform_va_hardware = {
.info = SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_PAUSE |
SNDRV_PCM_INFO_RESUME,
.formats = SNDRV_PCM_FMTBIT_S16 |
SNDRV_PCM_FMTBIT_S24 |
SNDRV_PCM_FMTBIT_S32,
.rates = SNDRV_PCM_RATE_8000_192000,
.rate_min = 8000,
.rate_max = 192000,
.channels_min = 1,
.channels_max = 8,
.buffer_bytes_max = LPASS_VA_CDC_DMA_LPM_BUFF_SIZE,
.period_bytes_max = LPASS_VA_CDC_DMA_LPM_BUFF_SIZE /
LPASS_PLATFORM_PERIODS,
.period_bytes_min = LPASS_VA_CDC_DMA_LPM_BUFF_SIZE /
LPASS_PLATFORM_PERIODS,
.periods_min = LPASS_PLATFORM_PERIODS,
.periods_max = LPASS_PLATFORM_PERIODS,
.fifo_size = 0,
};
static int lpass_platform_alloc_rxtx_dmactl_fields(struct device *dev,
struct regmap *map)
{
struct lpass_data *drvdata = dev_get_drvdata(dev);
struct lpass_variant *v = drvdata->variant;
struct lpaif_dmactl *rd_dmactl, *wr_dmactl;
int rval;
rd_dmactl = devm_kzalloc(dev, sizeof(*rd_dmactl), GFP_KERNEL);
if (!rd_dmactl)
return -ENOMEM;
wr_dmactl = devm_kzalloc(dev, sizeof(*wr_dmactl), GFP_KERNEL);
if (!wr_dmactl)
return -ENOMEM;
drvdata->rxtx_rd_dmactl = rd_dmactl;
drvdata->rxtx_wr_dmactl = wr_dmactl;
rval = devm_regmap_field_bulk_alloc(dev, map, &rd_dmactl->intf,
&v->rxtx_rdma_intf, LPASS_CDC_DMA_REGISTER_FIELDS_MAX);
if (rval)
return rval;
return devm_regmap_field_bulk_alloc(dev, map, &wr_dmactl->intf,
&v->rxtx_wrdma_intf, LPASS_CDC_DMA_REGISTER_FIELDS_MAX);
}
static int lpass_platform_alloc_va_dmactl_fields(struct device *dev,
struct regmap *map)
{
struct lpass_data *drvdata = dev_get_drvdata(dev);
struct lpass_variant *v = drvdata->variant;
struct lpaif_dmactl *wr_dmactl;
wr_dmactl = devm_kzalloc(dev, sizeof(*wr_dmactl), GFP_KERNEL);
if (!wr_dmactl)
return -ENOMEM;
drvdata->va_wr_dmactl = wr_dmactl;
return devm_regmap_field_bulk_alloc(dev, map, &wr_dmactl->intf,
&v->va_wrdma_intf, LPASS_CDC_DMA_REGISTER_FIELDS_MAX);
}
static int lpass_platform_alloc_dmactl_fields(struct device *dev,
struct regmap *map)
{
struct lpass_data *drvdata = dev_get_drvdata(dev);
struct lpass_variant *v = drvdata->variant;
struct lpaif_dmactl *rd_dmactl, *wr_dmactl;
int rval;
drvdata->rd_dmactl = devm_kzalloc(dev, sizeof(struct lpaif_dmactl),
GFP_KERNEL);
if (drvdata->rd_dmactl == NULL)
return -ENOMEM;
drvdata->wr_dmactl = devm_kzalloc(dev, sizeof(struct lpaif_dmactl),
GFP_KERNEL);
if (drvdata->wr_dmactl == NULL)
return -ENOMEM;
rd_dmactl = drvdata->rd_dmactl;
wr_dmactl = drvdata->wr_dmactl;
rval = devm_regmap_field_bulk_alloc(dev, map, &rd_dmactl->intf,
&v->rdma_intf, 6);
if (rval)
return rval;
return devm_regmap_field_bulk_alloc(dev, map, &wr_dmactl->intf,
&v->wrdma_intf, 6);
}
static int lpass_platform_alloc_hdmidmactl_fields(struct device *dev,
struct regmap *map)
{
struct lpass_data *drvdata = dev_get_drvdata(dev);
struct lpass_variant *v = drvdata->variant;
struct lpaif_dmactl *rd_dmactl;
rd_dmactl = devm_kzalloc(dev, sizeof(struct lpaif_dmactl), GFP_KERNEL);
if (rd_dmactl == NULL)
return -ENOMEM;
drvdata->hdmi_rd_dmactl = rd_dmactl;
return devm_regmap_field_bulk_alloc(dev, map, &rd_dmactl->bursten,
&v->hdmi_rdma_bursten, 8);
}
static int lpass_platform_pcmops_open(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
struct lpass_variant *v = drvdata->variant;
int ret, dma_ch, dir = substream->stream;
struct lpass_pcm_data *data;
struct regmap *map;
unsigned int dai_id = cpu_dai->driver->id;
component->id = dai_id;
data = kzalloc(sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->i2s_port = cpu_dai->driver->id;
runtime->private_data = data;
if (v->alloc_dma_channel)
dma_ch = v->alloc_dma_channel(drvdata, dir, dai_id);
else
dma_ch = 0;
if (dma_ch < 0) {
kfree(data);
return dma_ch;
}
switch (dai_id) {
case MI2S_PRIMARY ... MI2S_QUINARY:
map = drvdata->lpaif_map;
drvdata->substream[dma_ch] = substream;
break;
case LPASS_DP_RX:
map = drvdata->hdmiif_map;
drvdata->hdmi_substream[dma_ch] = substream;
break;
case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9:
case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8:
map = drvdata->rxtx_lpaif_map;
drvdata->rxtx_substream[dma_ch] = substream;
break;
case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8:
map = drvdata->va_lpaif_map;
drvdata->va_substream[dma_ch] = substream;
break;
default:
break;
}
data->dma_ch = dma_ch;
switch (dai_id) {
case MI2S_PRIMARY ... MI2S_QUINARY:
case LPASS_DP_RX:
ret = regmap_write(map, LPAIF_DMACTL_REG(v, dma_ch, dir, data->i2s_port), 0);
if (ret) {
kfree(data);
dev_err(soc_runtime->dev, "error writing to rdmactl reg: %d\n", ret);
return ret;
}
snd_soc_set_runtime_hwparams(substream, &lpass_platform_pcm_hardware);
runtime->dma_bytes = lpass_platform_pcm_hardware.buffer_bytes_max;
break;
case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9:
case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8:
snd_soc_set_runtime_hwparams(substream, &lpass_platform_rxtx_hardware);
runtime->dma_bytes = lpass_platform_rxtx_hardware.buffer_bytes_max;
snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
break;
case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8:
snd_soc_set_runtime_hwparams(substream, &lpass_platform_va_hardware);
runtime->dma_bytes = lpass_platform_va_hardware.buffer_bytes_max;
snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
break;
default:
break;
}
ret = snd_pcm_hw_constraint_integer(runtime,
SNDRV_PCM_HW_PARAM_PERIODS);
if (ret < 0) {
kfree(data);
dev_err(soc_runtime->dev, "setting constraints failed: %d\n",
ret);
return -EINVAL;
}
return 0;
}
static int lpass_platform_pcmops_close(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
struct lpass_variant *v = drvdata->variant;
struct lpass_pcm_data *data;
unsigned int dai_id = cpu_dai->driver->id;
data = runtime->private_data;
switch (dai_id) {
case MI2S_PRIMARY ... MI2S_QUINARY:
drvdata->substream[data->dma_ch] = NULL;
break;
case LPASS_DP_RX:
drvdata->hdmi_substream[data->dma_ch] = NULL;
break;
case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9:
case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8:
drvdata->rxtx_substream[data->dma_ch] = NULL;
break;
case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8:
drvdata->va_substream[data->dma_ch] = NULL;
break;
default:
break;
}
if (v->free_dma_channel)
v->free_dma_channel(drvdata, data->dma_ch, dai_id);
kfree(data);
return 0;
}
static struct lpaif_dmactl *__lpass_get_dmactl_handle(const struct snd_pcm_substream *substream,
struct snd_soc_component *component)
{
struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
struct lpaif_dmactl *dmactl = NULL;
switch (cpu_dai->driver->id) {
case MI2S_PRIMARY ... MI2S_QUINARY:
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
dmactl = drvdata->rd_dmactl;
else
dmactl = drvdata->wr_dmactl;
break;
case LPASS_DP_RX:
dmactl = drvdata->hdmi_rd_dmactl;
break;
case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9:
dmactl = drvdata->rxtx_rd_dmactl;
break;
case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8:
dmactl = drvdata->rxtx_wr_dmactl;
break;
case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8:
dmactl = drvdata->va_wr_dmactl;
break;
}
return dmactl;
}
static int __lpass_get_id(const struct snd_pcm_substream *substream,
struct snd_soc_component *component)
{
struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
struct snd_pcm_runtime *rt = substream->runtime;
struct lpass_pcm_data *pcm_data = rt->private_data;
struct lpass_variant *v = drvdata->variant;
int id;
switch (cpu_dai->driver->id) {
case MI2S_PRIMARY ... MI2S_QUINARY:
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
id = pcm_data->dma_ch;
else
id = pcm_data->dma_ch - v->wrdma_channel_start;
break;
case LPASS_DP_RX:
id = pcm_data->dma_ch;
break;
case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9:
id = pcm_data->dma_ch;
break;
case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8:
id = pcm_data->dma_ch - v->rxtx_wrdma_channel_start;
break;
case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8:
id = pcm_data->dma_ch - v->va_wrdma_channel_start;
break;
}
return id;
}
static struct regmap *__lpass_get_regmap_handle(const struct snd_pcm_substream *substream,
struct snd_soc_component *component)
{
struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
struct regmap *map = NULL;
switch (cpu_dai->driver->id) {
case MI2S_PRIMARY ... MI2S_QUINARY:
map = drvdata->lpaif_map;
break;
case LPASS_DP_RX:
map = drvdata->hdmiif_map;
break;
case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9:
case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8:
map = drvdata->rxtx_lpaif_map;
break;
case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8:
map = drvdata->va_lpaif_map;
break;
}
return map;
}
static int lpass_platform_pcmops_hw_params(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
struct snd_pcm_runtime *rt = substream->runtime;
struct lpass_pcm_data *pcm_data = rt->private_data;
struct lpass_variant *v = drvdata->variant;
snd_pcm_format_t format = params_format(params);
unsigned int channels = params_channels(params);
unsigned int regval;
struct lpaif_dmactl *dmactl;
int id;
int bitwidth;
int ret, dma_port = pcm_data->i2s_port + v->dmactl_audif_start;
unsigned int dai_id = cpu_dai->driver->id;
dmactl = __lpass_get_dmactl_handle(substream, component);
id = __lpass_get_id(substream, component);
bitwidth = snd_pcm_format_width(format);
if (bitwidth < 0) {
dev_err(soc_runtime->dev, "invalid bit width given: %d\n",
bitwidth);
return bitwidth;
}
ret = regmap_fields_write(dmactl->bursten, id, LPAIF_DMACTL_BURSTEN_INCR4);
if (ret) {
dev_err(soc_runtime->dev, "error updating bursten field: %d\n", ret);
return ret;
}
ret = regmap_fields_write(dmactl->fifowm, id, LPAIF_DMACTL_FIFOWM_8);
if (ret) {
dev_err(soc_runtime->dev, "error updating fifowm field: %d\n", ret);
return ret;
}
switch (dai_id) {
case LPASS_DP_RX:
ret = regmap_fields_write(dmactl->burst8, id,
LPAIF_DMACTL_BURSTEN_INCR4);
if (ret) {
dev_err(soc_runtime->dev, "error updating burst8en field: %d\n", ret);
return ret;
}
ret = regmap_fields_write(dmactl->burst16, id,
LPAIF_DMACTL_BURSTEN_INCR4);
if (ret) {
dev_err(soc_runtime->dev, "error updating burst16en field: %d\n", ret);
return ret;
}
ret = regmap_fields_write(dmactl->dynburst, id,
LPAIF_DMACTL_BURSTEN_INCR4);
if (ret) {
dev_err(soc_runtime->dev, "error updating dynbursten field: %d\n", ret);
return ret;
}
break;
case MI2S_PRIMARY:
case MI2S_SECONDARY:
case MI2S_TERTIARY:
case MI2S_QUATERNARY:
case MI2S_QUINARY:
ret = regmap_fields_write(dmactl->intf, id,
LPAIF_DMACTL_AUDINTF(dma_port));
if (ret) {
dev_err(soc_runtime->dev, "error updating audio interface field: %d\n",
ret);
return ret;
}
break;
case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9:
case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8:
case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX0:
break;
default:
dev_err(soc_runtime->dev, "%s: invalid interface: %d\n", __func__, dai_id);
break;
}
switch (bitwidth) {
case 16:
switch (channels) {
case 1:
case 2:
regval = LPAIF_DMACTL_WPSCNT_ONE;
break;
case 4:
regval = LPAIF_DMACTL_WPSCNT_TWO;
break;
case 6:
regval = LPAIF_DMACTL_WPSCNT_THREE;
break;
case 8:
regval = LPAIF_DMACTL_WPSCNT_FOUR;
break;
default:
dev_err(soc_runtime->dev, "invalid PCM config given: bw=%d, ch=%u\n",
bitwidth, channels);
return -EINVAL;
}
break;
case 24:
case 32:
switch (channels) {
case 1:
regval = LPAIF_DMACTL_WPSCNT_ONE;
break;
case 2:
regval = (dai_id == LPASS_DP_RX ?
LPAIF_DMACTL_WPSCNT_ONE :
LPAIF_DMACTL_WPSCNT_TWO);
break;
case 4:
regval = (dai_id == LPASS_DP_RX ?
LPAIF_DMACTL_WPSCNT_TWO :
LPAIF_DMACTL_WPSCNT_FOUR);
break;
case 6:
regval = (dai_id == LPASS_DP_RX ?
LPAIF_DMACTL_WPSCNT_THREE :
LPAIF_DMACTL_WPSCNT_SIX);
break;
case 8:
regval = (dai_id == LPASS_DP_RX ?
LPAIF_DMACTL_WPSCNT_FOUR :
LPAIF_DMACTL_WPSCNT_EIGHT);
break;
default:
dev_err(soc_runtime->dev, "invalid PCM config given: bw=%d, ch=%u\n",
bitwidth, channels);
return -EINVAL;
}
break;
default:
dev_err(soc_runtime->dev, "invalid PCM config given: bw=%d, ch=%u\n",
bitwidth, channels);
return -EINVAL;
}
ret = regmap_fields_write(dmactl->wpscnt, id, regval);
if (ret) {
dev_err(soc_runtime->dev, "error writing to dmactl reg: %d\n",
ret);
return ret;
}
return 0;
}
static int lpass_platform_pcmops_hw_free(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
struct snd_pcm_runtime *rt = substream->runtime;
struct lpass_pcm_data *pcm_data = rt->private_data;
struct lpass_variant *v = drvdata->variant;
unsigned int reg;
int ret;
struct regmap *map;
unsigned int dai_id = cpu_dai->driver->id;
if (is_cdc_dma_port(dai_id))
return 0;
map = __lpass_get_regmap_handle(substream, component);
reg = LPAIF_DMACTL_REG(v, pcm_data->dma_ch, substream->stream, dai_id);
ret = regmap_write(map, reg, 0);
if (ret)
dev_err(soc_runtime->dev, "error writing to rdmactl reg: %d\n",
ret);
return ret;
}
static int lpass_platform_pcmops_prepare(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
struct snd_pcm_runtime *rt = substream->runtime;
struct lpass_pcm_data *pcm_data = rt->private_data;
struct lpass_variant *v = drvdata->variant;
struct lpaif_dmactl *dmactl;
struct regmap *map;
int ret, id, ch, dir = substream->stream;
unsigned int dai_id = cpu_dai->driver->id;
ch = pcm_data->dma_ch;
dmactl = __lpass_get_dmactl_handle(substream, component);
id = __lpass_get_id(substream, component);
map = __lpass_get_regmap_handle(substream, component);
ret = regmap_write(map, LPAIF_DMABASE_REG(v, ch, dir, dai_id),
runtime->dma_addr);
if (ret) {
dev_err(soc_runtime->dev, "error writing to rdmabase reg: %d\n",
ret);
return ret;
}
ret = regmap_write(map, LPAIF_DMABUFF_REG(v, ch, dir, dai_id),
(snd_pcm_lib_buffer_bytes(substream) >> 2) - 1);
if (ret) {
dev_err(soc_runtime->dev, "error writing to rdmabuff reg: %d\n",
ret);
return ret;
}
ret = regmap_write(map, LPAIF_DMAPER_REG(v, ch, dir, dai_id),
(snd_pcm_lib_period_bytes(substream) >> 2) - 1);
if (ret) {
dev_err(soc_runtime->dev, "error writing to rdmaper reg: %d\n",
ret);
return ret;
}
if (is_cdc_dma_port(dai_id)) {
ret = regmap_fields_write(dmactl->fifowm, id, LPAIF_DMACTL_FIFOWM_8);
if (ret) {
dev_err(soc_runtime->dev, "error writing fifowm field to dmactl reg: %d, id: %d\n",
ret, id);
return ret;
}
}
ret = regmap_fields_write(dmactl->enable, id, LPAIF_DMACTL_ENABLE_ON);
if (ret) {
dev_err(soc_runtime->dev, "error writing to rdmactl reg: %d\n",
ret);
return ret;
}
return 0;
}
static int lpass_platform_pcmops_trigger(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
int cmd)
{
struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
struct snd_pcm_runtime *rt = substream->runtime;
struct lpass_pcm_data *pcm_data = rt->private_data;
struct lpass_variant *v = drvdata->variant;
struct lpaif_dmactl *dmactl;
struct regmap *map;
int ret, ch, id;
unsigned int reg_irqclr = 0, val_irqclr = 0;
unsigned int reg_irqen = 0, val_irqen = 0, val_mask = 0;
unsigned int dai_id = cpu_dai->driver->id;
ch = pcm_data->dma_ch;
dmactl = __lpass_get_dmactl_handle(substream, component);
id = __lpass_get_id(substream, component);
map = __lpass_get_regmap_handle(substream, component);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
ret = regmap_fields_write(dmactl->enable, id,
LPAIF_DMACTL_ENABLE_ON);
if (ret) {
dev_err(soc_runtime->dev,
"error writing to rdmactl reg: %d\n", ret);
return ret;
}
switch (dai_id) {
case LPASS_DP_RX:
ret = regmap_fields_write(dmactl->dyncclk, id,
LPAIF_DMACTL_DYNCLK_ON);
if (ret) {
dev_err(soc_runtime->dev,
"error writing to rdmactl reg: %d\n", ret);
return ret;
}
reg_irqclr = LPASS_HDMITX_APP_IRQCLEAR_REG(v);
val_irqclr = (LPAIF_IRQ_ALL(ch) |
LPAIF_IRQ_HDMI_REQ_ON_PRELOAD(ch) |
LPAIF_IRQ_HDMI_METADONE |
LPAIF_IRQ_HDMI_SDEEP_AUD_DIS(ch));
reg_irqen = LPASS_HDMITX_APP_IRQEN_REG(v);
val_mask = (LPAIF_IRQ_ALL(ch) |
LPAIF_IRQ_HDMI_REQ_ON_PRELOAD(ch) |
LPAIF_IRQ_HDMI_METADONE |
LPAIF_IRQ_HDMI_SDEEP_AUD_DIS(ch));
val_irqen = (LPAIF_IRQ_ALL(ch) |
LPAIF_IRQ_HDMI_REQ_ON_PRELOAD(ch) |
LPAIF_IRQ_HDMI_METADONE |
LPAIF_IRQ_HDMI_SDEEP_AUD_DIS(ch));
break;
case MI2S_PRIMARY:
case MI2S_SECONDARY:
case MI2S_TERTIARY:
case MI2S_QUATERNARY:
case MI2S_QUINARY:
reg_irqclr = LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST);
val_irqclr = LPAIF_IRQ_ALL(ch);
reg_irqen = LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST);
val_mask = LPAIF_IRQ_ALL(ch);
val_irqen = LPAIF_IRQ_ALL(ch);
break;
case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9:
case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8:
ret = regmap_fields_write(dmactl->dyncclk, id, LPAIF_DMACTL_DYNCLK_ON);
if (ret) {
dev_err(soc_runtime->dev,
"error writing to rdmactl reg field: %d\n", ret);
return ret;
}
reg_irqclr = LPAIF_RXTX_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST);
val_irqclr = LPAIF_IRQ_ALL(ch);
reg_irqen = LPAIF_RXTX_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST);
val_mask = LPAIF_IRQ_ALL(ch);
val_irqen = LPAIF_IRQ_ALL(ch);
break;
case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8:
ret = regmap_fields_write(dmactl->dyncclk, id, LPAIF_DMACTL_DYNCLK_ON);
if (ret) {
dev_err(soc_runtime->dev,
"error writing to rdmactl reg field: %d\n", ret);
return ret;
}
reg_irqclr = LPAIF_VA_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST);
val_irqclr = LPAIF_IRQ_ALL(ch);
reg_irqen = LPAIF_VA_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST);
val_mask = LPAIF_IRQ_ALL(ch);
val_irqen = LPAIF_IRQ_ALL(ch);
break;
default:
dev_err(soc_runtime->dev, "%s: invalid %d interface\n", __func__, dai_id);
return -EINVAL;
}
ret = regmap_write_bits(map, reg_irqclr, val_irqclr, val_irqclr);
if (ret) {
dev_err(soc_runtime->dev, "error writing to irqclear reg: %d\n", ret);
return ret;
}
ret = regmap_update_bits(map, reg_irqen, val_mask, val_irqen);
if (ret) {
dev_err(soc_runtime->dev, "error writing to irqen reg: %d\n", ret);
return ret;
}
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
ret = regmap_fields_write(dmactl->enable, id,
LPAIF_DMACTL_ENABLE_OFF);
if (ret) {
dev_err(soc_runtime->dev,
"error writing to rdmactl reg: %d\n", ret);
return ret;
}
switch (dai_id) {
case LPASS_DP_RX:
ret = regmap_fields_write(dmactl->dyncclk, id,
LPAIF_DMACTL_DYNCLK_OFF);
if (ret) {
dev_err(soc_runtime->dev,
"error writing to rdmactl reg: %d\n", ret);
return ret;
}
reg_irqen = LPASS_HDMITX_APP_IRQEN_REG(v);
val_mask = (LPAIF_IRQ_ALL(ch) |
LPAIF_IRQ_HDMI_REQ_ON_PRELOAD(ch) |
LPAIF_IRQ_HDMI_METADONE |
LPAIF_IRQ_HDMI_SDEEP_AUD_DIS(ch));
val_irqen = 0;
break;
case MI2S_PRIMARY:
case MI2S_SECONDARY:
case MI2S_TERTIARY:
case MI2S_QUATERNARY:
case MI2S_QUINARY:
reg_irqen = LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST);
val_mask = LPAIF_IRQ_ALL(ch);
val_irqen = 0;
break;
case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9:
case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8:
ret = regmap_fields_write(dmactl->dyncclk, id, LPAIF_DMACTL_DYNCLK_OFF);
if (ret) {
dev_err(soc_runtime->dev,
"error writing to rdmactl reg field: %d\n", ret);
return ret;
}
reg_irqclr = LPAIF_RXTX_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST);
val_irqclr = LPAIF_IRQ_ALL(ch);
reg_irqen = LPAIF_RXTX_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST);
val_mask = LPAIF_IRQ_ALL(ch);
val_irqen = LPAIF_IRQ_ALL(ch);
break;
case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8:
ret = regmap_fields_write(dmactl->dyncclk, id, LPAIF_DMACTL_DYNCLK_OFF);
if (ret) {
dev_err(soc_runtime->dev,
"error writing to rdmactl reg field: %d\n", ret);
return ret;
}
reg_irqclr = LPAIF_VA_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST);
val_irqclr = LPAIF_IRQ_ALL(ch);
reg_irqen = LPAIF_VA_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST);
val_mask = LPAIF_IRQ_ALL(ch);
val_irqen = LPAIF_IRQ_ALL(ch);
break;
default:
dev_err(soc_runtime->dev, "%s: invalid %d interface\n", __func__, dai_id);
return -EINVAL;
}
ret = regmap_update_bits(map, reg_irqen, val_mask, val_irqen);
if (ret) {
dev_err(soc_runtime->dev,
"error writing to irqen reg: %d\n", ret);
return ret;
}
break;
}
return 0;
}
static snd_pcm_uframes_t lpass_platform_pcmops_pointer(
struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
struct snd_pcm_runtime *rt = substream->runtime;
struct lpass_pcm_data *pcm_data = rt->private_data;
struct lpass_variant *v = drvdata->variant;
unsigned int base_addr, curr_addr;
int ret, ch, dir = substream->stream;
struct regmap *map;
unsigned int dai_id = cpu_dai->driver->id;
map = __lpass_get_regmap_handle(substream, component);
ch = pcm_data->dma_ch;
ret = regmap_read(map,
LPAIF_DMABASE_REG(v, ch, dir, dai_id), &base_addr);
if (ret) {
dev_err(soc_runtime->dev,
"error reading from rdmabase reg: %d\n", ret);
return ret;
}
ret = regmap_read(map,
LPAIF_DMACURR_REG(v, ch, dir, dai_id), &curr_addr);
if (ret) {
dev_err(soc_runtime->dev,
"error reading from rdmacurr reg: %d\n", ret);
return ret;
}
return bytes_to_frames(substream->runtime, curr_addr - base_addr);
}
static int lpass_platform_cdc_dma_mmap(struct snd_pcm_substream *substream,
struct vm_area_struct *vma)
{
struct snd_pcm_runtime *runtime = substream->runtime;
unsigned long size, offset;
vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
size = vma->vm_end - vma->vm_start;
offset = vma->vm_pgoff << PAGE_SHIFT;
return io_remap_pfn_range(vma, vma->vm_start,
(runtime->dma_addr + offset) >> PAGE_SHIFT,
size, vma->vm_page_prot);
}
static int lpass_platform_pcmops_mmap(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct vm_area_struct *vma)
{
struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
unsigned int dai_id = cpu_dai->driver->id;
if (is_cdc_dma_port(dai_id))
return lpass_platform_cdc_dma_mmap(substream, vma);
return snd_pcm_lib_default_mmap(substream, vma);
}
static irqreturn_t lpass_dma_interrupt_handler(
struct snd_pcm_substream *substream,
struct lpass_data *drvdata,
int chan, u32 interrupts)
{
struct snd_soc_pcm_runtime *soc_runtime = asoc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
struct lpass_variant *v = drvdata->variant;
irqreturn_t ret = IRQ_NONE;
int rv;
unsigned int reg, val, mask;
struct regmap *map;
unsigned int dai_id = cpu_dai->driver->id;
mask = LPAIF_IRQ_ALL(chan);
switch (dai_id) {
case LPASS_DP_RX:
map = drvdata->hdmiif_map;
reg = LPASS_HDMITX_APP_IRQCLEAR_REG(v);
val = (LPAIF_IRQ_HDMI_REQ_ON_PRELOAD(chan) |
LPAIF_IRQ_HDMI_METADONE |
LPAIF_IRQ_HDMI_SDEEP_AUD_DIS(chan));
break;
case MI2S_PRIMARY:
case MI2S_SECONDARY:
case MI2S_TERTIARY:
case MI2S_QUATERNARY:
case MI2S_QUINARY:
map = drvdata->lpaif_map;
reg = LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST);
val = 0;
break;
case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9:
case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8:
map = drvdata->rxtx_lpaif_map;
reg = LPAIF_RXTX_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST);
val = 0;
break;
case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8:
map = drvdata->va_lpaif_map;
reg = LPAIF_VA_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST);
val = 0;
break;
default:
dev_err(soc_runtime->dev, "%s: invalid %d interface\n", __func__, dai_id);
return -EINVAL;
}
if (interrupts & LPAIF_IRQ_PER(chan)) {
rv = regmap_write_bits(map, reg, mask, (LPAIF_IRQ_PER(chan) | val));
if (rv) {
dev_err(soc_runtime->dev,
"error writing to irqclear reg: %d\n", rv);
return IRQ_NONE;
}
snd_pcm_period_elapsed(substream);
ret = IRQ_HANDLED;
}
if (interrupts & LPAIF_IRQ_XRUN(chan)) {
rv = regmap_write_bits(map, reg, mask, (LPAIF_IRQ_XRUN(chan) | val));
if (rv) {
dev_err(soc_runtime->dev,
"error writing to irqclear reg: %d\n", rv);
return IRQ_NONE;
}
dev_warn_ratelimited(soc_runtime->dev, "xrun warning\n");
snd_pcm_stop_xrun(substream);
ret = IRQ_HANDLED;
}
if (interrupts & LPAIF_IRQ_ERR(chan)) {
rv = regmap_write_bits(map, reg, mask, (LPAIF_IRQ_ERR(chan) | val));
if (rv) {
dev_err(soc_runtime->dev,
"error writing to irqclear reg: %d\n", rv);
return IRQ_NONE;
}
dev_err(soc_runtime->dev, "bus access error\n");
snd_pcm_stop(substream, SNDRV_PCM_STATE_DISCONNECTED);
ret = IRQ_HANDLED;
}
if (interrupts & val) {
rv = regmap_write(map, reg, val);
if (rv) {
dev_err(soc_runtime->dev,
"error writing to irqclear reg: %d\n", rv);
return IRQ_NONE;
}
ret = IRQ_HANDLED;
}
return ret;
}
static irqreturn_t lpass_platform_lpaif_irq(int irq, void *data)
{
struct lpass_data *drvdata = data;
struct lpass_variant *v = drvdata->variant;
unsigned int irqs;
int rv, chan;
rv = regmap_read(drvdata->lpaif_map,
LPAIF_IRQSTAT_REG(v, LPAIF_IRQ_PORT_HOST), &irqs);
if (rv) {
pr_err("error reading from irqstat reg: %d\n", rv);
return IRQ_NONE;
}
/* Handle per channel interrupts */
for (chan = 0; chan < LPASS_MAX_DMA_CHANNELS; chan++) {
if (irqs & LPAIF_IRQ_ALL(chan) && drvdata->substream[chan]) {
rv = lpass_dma_interrupt_handler(
drvdata->substream[chan],
drvdata, chan, irqs);
if (rv != IRQ_HANDLED)
return rv;
}
}
return IRQ_HANDLED;
}
static irqreturn_t lpass_platform_hdmiif_irq(int irq, void *data)
{
struct lpass_data *drvdata = data;
struct lpass_variant *v = drvdata->variant;
unsigned int irqs;
int rv, chan;
rv = regmap_read(drvdata->hdmiif_map,
LPASS_HDMITX_APP_IRQSTAT_REG(v), &irqs);
if (rv) {
pr_err("error reading from irqstat reg: %d\n", rv);
return IRQ_NONE;
}
/* Handle per channel interrupts */
for (chan = 0; chan < LPASS_MAX_HDMI_DMA_CHANNELS; chan++) {
if (irqs & (LPAIF_IRQ_ALL(chan) | LPAIF_IRQ_HDMI_REQ_ON_PRELOAD(chan) |
LPAIF_IRQ_HDMI_METADONE |
LPAIF_IRQ_HDMI_SDEEP_AUD_DIS(chan))
&& drvdata->hdmi_substream[chan]) {
rv = lpass_dma_interrupt_handler(
drvdata->hdmi_substream[chan],
drvdata, chan, irqs);
if (rv != IRQ_HANDLED)
return rv;
}
}
return IRQ_HANDLED;
}
static irqreturn_t lpass_platform_rxtxif_irq(int irq, void *data)
{
struct lpass_data *drvdata = data;
struct lpass_variant *v = drvdata->variant;
unsigned int irqs;
irqreturn_t rv;
int chan;
rv = regmap_read(drvdata->rxtx_lpaif_map,
LPAIF_RXTX_IRQSTAT_REG(v, LPAIF_IRQ_PORT_HOST), &irqs);
/* Handle per channel interrupts */
for (chan = 0; chan < LPASS_MAX_CDC_DMA_CHANNELS; chan++) {
if (irqs & LPAIF_IRQ_ALL(chan) && drvdata->rxtx_substream[chan]) {
rv = lpass_dma_interrupt_handler(
drvdata->rxtx_substream[chan],
drvdata, chan, irqs);
if (rv != IRQ_HANDLED)
return rv;
}
}
return IRQ_HANDLED;
}
static irqreturn_t lpass_platform_vaif_irq(int irq, void *data)
{
struct lpass_data *drvdata = data;
struct lpass_variant *v = drvdata->variant;
unsigned int irqs;
irqreturn_t rv;
int chan;
rv = regmap_read(drvdata->va_lpaif_map,
LPAIF_VA_IRQSTAT_REG(v, LPAIF_IRQ_PORT_HOST), &irqs);
/* Handle per channel interrupts */
for (chan = 0; chan < LPASS_MAX_VA_CDC_DMA_CHANNELS; chan++) {
if (irqs & LPAIF_IRQ_ALL(chan) && drvdata->va_substream[chan]) {
rv = lpass_dma_interrupt_handler(
drvdata->va_substream[chan],
drvdata, chan, irqs);
if (rv != IRQ_HANDLED)
return rv;
}
}
return IRQ_HANDLED;
}
static int lpass_platform_prealloc_cdc_dma_buffer(struct snd_soc_component *component,
struct snd_pcm *pcm, int dai_id)
{
struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
struct snd_pcm_substream *substream;
struct snd_dma_buffer *buf;
if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream)
substream = pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
else
substream = pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream;
buf = &substream->dma_buffer;
buf->dev.dev = pcm->card->dev;
buf->private_data = NULL;
/* Assign Codec DMA buffer pointers */
buf->dev.type = SNDRV_DMA_TYPE_CONTINUOUS;
switch (dai_id) {
case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9:
buf->bytes = lpass_platform_rxtx_hardware.buffer_bytes_max;
buf->addr = drvdata->rxtx_cdc_dma_lpm_buf;
break;
case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8:
buf->bytes = lpass_platform_rxtx_hardware.buffer_bytes_max;
buf->addr = drvdata->rxtx_cdc_dma_lpm_buf + LPASS_RXTX_CDC_DMA_LPM_BUFF_SIZE;
break;
case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8:
buf->bytes = lpass_platform_va_hardware.buffer_bytes_max;
buf->addr = drvdata->va_cdc_dma_lpm_buf;
break;
default:
break;
}
buf->area = (unsigned char * __force)memremap(buf->addr, buf->bytes, MEMREMAP_WC);
return 0;
}
static int lpass_platform_pcm_new(struct snd_soc_component *component,
struct snd_soc_pcm_runtime *soc_runtime)
{
struct snd_pcm *pcm = soc_runtime->pcm;
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_runtime, 0);
unsigned int dai_id = cpu_dai->driver->id;
size_t size = lpass_platform_pcm_hardware.buffer_bytes_max;
/*
* Lpass codec dma can access only lpass lpm hardware memory.
* ioremap is for HLOS to access hardware memory.
*/
if (is_cdc_dma_port(dai_id))
return lpass_platform_prealloc_cdc_dma_buffer(component, pcm, dai_id);
return snd_pcm_set_fixed_buffer_all(pcm, SNDRV_DMA_TYPE_NONCOHERENT,
component->dev, size);
}
static int lpass_platform_pcmops_suspend(struct snd_soc_component *component)
{
struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
struct regmap *map;
unsigned int dai_id = component->id;
if (dai_id == LPASS_DP_RX)
map = drvdata->hdmiif_map;
else
map = drvdata->lpaif_map;
regcache_cache_only(map, true);
regcache_mark_dirty(map);
return 0;
}
static int lpass_platform_pcmops_resume(struct snd_soc_component *component)
{
struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
struct regmap *map;
unsigned int dai_id = component->id;
if (dai_id == LPASS_DP_RX)
map = drvdata->hdmiif_map;
else
map = drvdata->lpaif_map;
regcache_cache_only(map, false);
return regcache_sync(map);
}
static int lpass_platform_copy(struct snd_soc_component *component,
struct snd_pcm_substream *substream, int channel,
unsigned long pos, struct iov_iter *buf,
unsigned long bytes)
{
struct snd_pcm_runtime *rt = substream->runtime;
unsigned int dai_id = component->id;
int ret = 0;
void __iomem *dma_buf = (void __iomem *) (rt->dma_area + pos +
channel * (rt->dma_bytes / rt->channels));
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
if (is_cdc_dma_port(dai_id)) {
ret = copy_from_iter_toio(dma_buf, buf, bytes);
} else {
if (copy_from_iter((void __force *)dma_buf, bytes, buf) != bytes)
ret = -EFAULT;
}
} else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
if (is_cdc_dma_port(dai_id)) {
ret = copy_to_iter_fromio(buf, dma_buf, bytes);
} else {
if (copy_to_iter((void __force *)dma_buf, bytes, buf) != bytes)
ret = -EFAULT;
}
}
return ret;
}
static const struct snd_soc_component_driver lpass_component_driver = {
.name = DRV_NAME,
.open = lpass_platform_pcmops_open,
.close = lpass_platform_pcmops_close,
.hw_params = lpass_platform_pcmops_hw_params,
.hw_free = lpass_platform_pcmops_hw_free,
.prepare = lpass_platform_pcmops_prepare,
.trigger = lpass_platform_pcmops_trigger,
.pointer = lpass_platform_pcmops_pointer,
.mmap = lpass_platform_pcmops_mmap,
.pcm_construct = lpass_platform_pcm_new,
.suspend = lpass_platform_pcmops_suspend,
.resume = lpass_platform_pcmops_resume,
.copy = lpass_platform_copy,
};
int asoc_qcom_lpass_platform_register(struct platform_device *pdev)
{
struct lpass_data *drvdata = platform_get_drvdata(pdev);
struct lpass_variant *v = drvdata->variant;
int ret;
drvdata->lpaif_irq = platform_get_irq_byname(pdev, "lpass-irq-lpaif");
if (drvdata->lpaif_irq < 0)
return -ENODEV;
/* ensure audio hardware is disabled */
ret = regmap_write(drvdata->lpaif_map,
LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST), 0);
if (ret) {
dev_err(&pdev->dev, "error writing to irqen reg: %d\n", ret);
return ret;
}
ret = devm_request_irq(&pdev->dev, drvdata->lpaif_irq,
lpass_platform_lpaif_irq, IRQF_TRIGGER_RISING,
"lpass-irq-lpaif", drvdata);
if (ret) {
dev_err(&pdev->dev, "irq request failed: %d\n", ret);
return ret;
}
ret = lpass_platform_alloc_dmactl_fields(&pdev->dev,
drvdata->lpaif_map);
if (ret) {
dev_err(&pdev->dev,
"error initializing dmactl fields: %d\n", ret);
return ret;
}
if (drvdata->codec_dma_enable) {
ret = regmap_write(drvdata->rxtx_lpaif_map,
LPAIF_RXTX_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST), 0x0);
if (ret) {
dev_err(&pdev->dev, "error writing to rxtx irqen reg: %d\n", ret);
return ret;
}
ret = regmap_write(drvdata->va_lpaif_map,
LPAIF_VA_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST), 0x0);
if (ret) {
dev_err(&pdev->dev, "error writing to rxtx irqen reg: %d\n", ret);
return ret;
}
drvdata->rxtxif_irq = platform_get_irq_byname(pdev, "lpass-irq-rxtxif");
if (drvdata->rxtxif_irq < 0)
return -ENODEV;
ret = devm_request_irq(&pdev->dev, drvdata->rxtxif_irq,
lpass_platform_rxtxif_irq, 0, "lpass-irq-rxtxif", drvdata);
if (ret) {
dev_err(&pdev->dev, "rxtx irq request failed: %d\n", ret);
return ret;
}
ret = lpass_platform_alloc_rxtx_dmactl_fields(&pdev->dev,
drvdata->rxtx_lpaif_map);
if (ret) {
dev_err(&pdev->dev,
"error initializing rxtx dmactl fields: %d\n", ret);
return ret;
}
drvdata->vaif_irq = platform_get_irq_byname(pdev, "lpass-irq-vaif");
if (drvdata->vaif_irq < 0)
return -ENODEV;
ret = devm_request_irq(&pdev->dev, drvdata->vaif_irq,
lpass_platform_vaif_irq, 0, "lpass-irq-vaif", drvdata);
if (ret) {
dev_err(&pdev->dev, "va irq request failed: %d\n", ret);
return ret;
}
ret = lpass_platform_alloc_va_dmactl_fields(&pdev->dev,
drvdata->va_lpaif_map);
if (ret) {
dev_err(&pdev->dev,
"error initializing va dmactl fields: %d\n", ret);
return ret;
}
}
if (drvdata->hdmi_port_enable) {
drvdata->hdmiif_irq = platform_get_irq_byname(pdev, "lpass-irq-hdmi");
if (drvdata->hdmiif_irq < 0)
return -ENODEV;
ret = devm_request_irq(&pdev->dev, drvdata->hdmiif_irq,
lpass_platform_hdmiif_irq, 0, "lpass-irq-hdmi", drvdata);
if (ret) {
dev_err(&pdev->dev, "irq hdmi request failed: %d\n", ret);
return ret;
}
ret = regmap_write(drvdata->hdmiif_map,
LPASS_HDMITX_APP_IRQEN_REG(v), 0);
if (ret) {
dev_err(&pdev->dev, "error writing to hdmi irqen reg: %d\n", ret);
return ret;
}
ret = lpass_platform_alloc_hdmidmactl_fields(&pdev->dev,
drvdata->hdmiif_map);
if (ret) {
dev_err(&pdev->dev,
"error initializing hdmidmactl fields: %d\n", ret);
return ret;
}
}
return devm_snd_soc_register_component(&pdev->dev,
&lpass_component_driver, NULL, 0);
}
EXPORT_SYMBOL_GPL(asoc_qcom_lpass_platform_register);
MODULE_DESCRIPTION("QTi LPASS Platform Driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/qcom/lpass-platform.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2020, Linaro Limited
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of_device.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/pcm.h>
#include <linux/soundwire/sdw.h>
#include <sound/jack.h>
#include <linux/input-event-codes.h>
#include "qdsp6/q6afe.h"
#include "common.h"
#include "sdw.h"
#define DRIVER_NAME "sm8250"
#define MI2S_BCLK_RATE 1536000
struct sm8250_snd_data {
bool stream_prepared[AFE_PORT_MAX];
struct snd_soc_card *card;
struct sdw_stream_runtime *sruntime[AFE_PORT_MAX];
struct snd_soc_jack jack;
bool jack_setup;
};
static int sm8250_snd_init(struct snd_soc_pcm_runtime *rtd)
{
struct sm8250_snd_data *data = snd_soc_card_get_drvdata(rtd->card);
return qcom_snd_wcd_jack_setup(rtd, &data->jack, &data->jack_setup);
}
static int sm8250_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
struct snd_pcm_hw_params *params)
{
struct snd_interval *rate = hw_param_interval(params,
SNDRV_PCM_HW_PARAM_RATE);
struct snd_interval *channels = hw_param_interval(params,
SNDRV_PCM_HW_PARAM_CHANNELS);
rate->min = rate->max = 48000;
channels->min = channels->max = 2;
return 0;
}
static int sm8250_snd_startup(struct snd_pcm_substream *substream)
{
unsigned int fmt = SND_SOC_DAIFMT_BP_FP;
unsigned int codec_dai_fmt = SND_SOC_DAIFMT_BC_FC;
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
switch (cpu_dai->id) {
case TERTIARY_MI2S_RX:
codec_dai_fmt |= SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_I2S;
snd_soc_dai_set_sysclk(cpu_dai,
Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
MI2S_BCLK_RATE, SNDRV_PCM_STREAM_PLAYBACK);
snd_soc_dai_set_fmt(cpu_dai, fmt);
snd_soc_dai_set_fmt(codec_dai, codec_dai_fmt);
break;
default:
break;
}
return 0;
}
static int sm8250_snd_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct sm8250_snd_data *pdata = snd_soc_card_get_drvdata(rtd->card);
return qcom_snd_sdw_hw_params(substream, params, &pdata->sruntime[cpu_dai->id]);
}
static int sm8250_snd_prepare(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct sm8250_snd_data *data = snd_soc_card_get_drvdata(rtd->card);
struct sdw_stream_runtime *sruntime = data->sruntime[cpu_dai->id];
return qcom_snd_sdw_prepare(substream, sruntime,
&data->stream_prepared[cpu_dai->id]);
}
static int sm8250_snd_hw_free(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct sm8250_snd_data *data = snd_soc_card_get_drvdata(rtd->card);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct sdw_stream_runtime *sruntime = data->sruntime[cpu_dai->id];
return qcom_snd_sdw_hw_free(substream, sruntime,
&data->stream_prepared[cpu_dai->id]);
}
static const struct snd_soc_ops sm8250_be_ops = {
.startup = sm8250_snd_startup,
.hw_params = sm8250_snd_hw_params,
.hw_free = sm8250_snd_hw_free,
.prepare = sm8250_snd_prepare,
};
static void sm8250_add_be_ops(struct snd_soc_card *card)
{
struct snd_soc_dai_link *link;
int i;
for_each_card_prelinks(card, i, link) {
if (link->no_pcm == 1) {
link->init = sm8250_snd_init;
link->be_hw_params_fixup = sm8250_be_hw_params_fixup;
link->ops = &sm8250_be_ops;
}
}
}
static int sm8250_platform_probe(struct platform_device *pdev)
{
struct snd_soc_card *card;
struct sm8250_snd_data *data;
struct device *dev = &pdev->dev;
int ret;
card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
if (!card)
return -ENOMEM;
card->owner = THIS_MODULE;
/* Allocate the private data */
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
card->dev = dev;
dev_set_drvdata(dev, card);
snd_soc_card_set_drvdata(card, data);
ret = qcom_snd_parse_of(card);
if (ret)
return ret;
card->driver_name = DRIVER_NAME;
sm8250_add_be_ops(card);
return devm_snd_soc_register_card(dev, card);
}
static const struct of_device_id snd_sm8250_dt_match[] = {
{.compatible = "qcom,sm8250-sndcard"},
{.compatible = "qcom,qrb5165-rb5-sndcard"},
{}
};
MODULE_DEVICE_TABLE(of, snd_sm8250_dt_match);
static struct platform_driver snd_sm8250_driver = {
.probe = sm8250_platform_probe,
.driver = {
.name = "snd-sm8250",
.of_match_table = snd_sm8250_dt_match,
},
};
module_platform_driver(snd_sm8250_driver);
MODULE_AUTHOR("Srinivas Kandagatla <[email protected]");
MODULE_DESCRIPTION("SM8250 ASoC Machine Driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/qcom/sm8250.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
*
* lpass-apq8016.c -- ALSA SoC CPU DAI driver for APQ8016 LPASS
*/
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include <dt-bindings/sound/apq8016-lpass.h>
#include "lpass-lpaif-reg.h"
#include "lpass.h"
static struct snd_soc_dai_driver apq8016_lpass_cpu_dai_driver[] = {
[MI2S_PRIMARY] = {
.id = MI2S_PRIMARY,
.name = "Primary MI2S",
.playback = {
.stream_name = "Primary Playback",
.formats = SNDRV_PCM_FMTBIT_S16 |
SNDRV_PCM_FMTBIT_S24 |
SNDRV_PCM_FMTBIT_S32,
.rates = SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 |
SNDRV_PCM_RATE_32000 |
SNDRV_PCM_RATE_48000 |
SNDRV_PCM_RATE_96000,
.rate_min = 8000,
.rate_max = 96000,
.channels_min = 1,
.channels_max = 8,
},
.ops = &asoc_qcom_lpass_cpu_dai_ops,
},
[MI2S_SECONDARY] = {
.id = MI2S_SECONDARY,
.name = "Secondary MI2S",
.playback = {
.stream_name = "Secondary Playback",
.formats = SNDRV_PCM_FMTBIT_S16 |
SNDRV_PCM_FMTBIT_S24 |
SNDRV_PCM_FMTBIT_S32,
.rates = SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 |
SNDRV_PCM_RATE_32000 |
SNDRV_PCM_RATE_48000 |
SNDRV_PCM_RATE_96000,
.rate_min = 8000,
.rate_max = 96000,
.channels_min = 1,
.channels_max = 8,
},
.ops = &asoc_qcom_lpass_cpu_dai_ops,
},
[MI2S_TERTIARY] = {
.id = MI2S_TERTIARY,
.name = "Tertiary MI2S",
.capture = {
.stream_name = "Tertiary Capture",
.formats = SNDRV_PCM_FMTBIT_S16 |
SNDRV_PCM_FMTBIT_S24 |
SNDRV_PCM_FMTBIT_S32,
.rates = SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 |
SNDRV_PCM_RATE_32000 |
SNDRV_PCM_RATE_48000 |
SNDRV_PCM_RATE_96000,
.rate_min = 8000,
.rate_max = 96000,
.channels_min = 1,
.channels_max = 8,
},
.ops = &asoc_qcom_lpass_cpu_dai_ops,
},
[MI2S_QUATERNARY] = {
.id = MI2S_QUATERNARY,
.name = "Quatenary MI2S",
.playback = {
.stream_name = "Quatenary Playback",
.formats = SNDRV_PCM_FMTBIT_S16 |
SNDRV_PCM_FMTBIT_S24 |
SNDRV_PCM_FMTBIT_S32,
.rates = SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 |
SNDRV_PCM_RATE_32000 |
SNDRV_PCM_RATE_48000 |
SNDRV_PCM_RATE_96000,
.rate_min = 8000,
.rate_max = 96000,
.channels_min = 1,
.channels_max = 8,
},
.capture = {
.stream_name = "Quatenary Capture",
.formats = SNDRV_PCM_FMTBIT_S16 |
SNDRV_PCM_FMTBIT_S24 |
SNDRV_PCM_FMTBIT_S32,
.rates = SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 |
SNDRV_PCM_RATE_32000 |
SNDRV_PCM_RATE_48000 |
SNDRV_PCM_RATE_96000,
.rate_min = 8000,
.rate_max = 96000,
.channels_min = 1,
.channels_max = 8,
},
.ops = &asoc_qcom_lpass_cpu_dai_ops,
},
};
static int apq8016_lpass_alloc_dma_channel(struct lpass_data *drvdata,
int direction, unsigned int dai_id)
{
struct lpass_variant *v = drvdata->variant;
int chan = 0;
if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
chan = find_first_zero_bit(&drvdata->dma_ch_bit_map,
v->rdma_channels);
if (chan >= v->rdma_channels)
return -EBUSY;
} else {
chan = find_next_zero_bit(&drvdata->dma_ch_bit_map,
v->wrdma_channel_start +
v->wrdma_channels,
v->wrdma_channel_start);
if (chan >= v->wrdma_channel_start + v->wrdma_channels)
return -EBUSY;
}
set_bit(chan, &drvdata->dma_ch_bit_map);
return chan;
}
static int apq8016_lpass_free_dma_channel(struct lpass_data *drvdata, int chan, unsigned int dai_id)
{
clear_bit(chan, &drvdata->dma_ch_bit_map);
return 0;
}
static int apq8016_lpass_init(struct platform_device *pdev)
{
struct lpass_data *drvdata = platform_get_drvdata(pdev);
struct lpass_variant *variant = drvdata->variant;
struct device *dev = &pdev->dev;
int ret, i;
drvdata->clks = devm_kcalloc(dev, variant->num_clks,
sizeof(*drvdata->clks), GFP_KERNEL);
if (!drvdata->clks)
return -ENOMEM;
drvdata->num_clks = variant->num_clks;
for (i = 0; i < drvdata->num_clks; i++)
drvdata->clks[i].id = variant->clk_name[i];
ret = devm_clk_bulk_get(dev, drvdata->num_clks, drvdata->clks);
if (ret) {
dev_err(dev, "Failed to get clocks %d\n", ret);
return ret;
}
ret = clk_bulk_prepare_enable(drvdata->num_clks, drvdata->clks);
if (ret) {
dev_err(dev, "apq8016 clk_enable failed\n");
return ret;
}
drvdata->ahbix_clk = devm_clk_get(dev, "ahbix-clk");
if (IS_ERR(drvdata->ahbix_clk)) {
dev_err(dev, "error getting ahbix-clk: %ld\n",
PTR_ERR(drvdata->ahbix_clk));
ret = PTR_ERR(drvdata->ahbix_clk);
goto err_ahbix_clk;
}
ret = clk_set_rate(drvdata->ahbix_clk, LPASS_AHBIX_CLOCK_FREQUENCY);
if (ret) {
dev_err(dev, "error setting rate on ahbix_clk: %d\n", ret);
goto err_ahbix_clk;
}
dev_dbg(dev, "set ahbix_clk rate to %lu\n",
clk_get_rate(drvdata->ahbix_clk));
ret = clk_prepare_enable(drvdata->ahbix_clk);
if (ret) {
dev_err(dev, "error enabling ahbix_clk: %d\n", ret);
goto err_ahbix_clk;
}
return 0;
err_ahbix_clk:
clk_bulk_disable_unprepare(drvdata->num_clks, drvdata->clks);
return ret;
}
static int apq8016_lpass_exit(struct platform_device *pdev)
{
struct lpass_data *drvdata = platform_get_drvdata(pdev);
clk_bulk_disable_unprepare(drvdata->num_clks, drvdata->clks);
clk_disable_unprepare(drvdata->ahbix_clk);
return 0;
}
static struct lpass_variant apq8016_data = {
.i2sctrl_reg_base = 0x1000,
.i2sctrl_reg_stride = 0x1000,
.i2s_ports = 4,
.irq_reg_base = 0x6000,
.irq_reg_stride = 0x1000,
.irq_ports = 3,
.rdma_reg_base = 0x8400,
.rdma_reg_stride = 0x1000,
.rdma_channels = 2,
.dmactl_audif_start = 1,
.wrdma_reg_base = 0xB000,
.wrdma_reg_stride = 0x1000,
.wrdma_channel_start = 5,
.wrdma_channels = 2,
.loopback = REG_FIELD_ID(0x1000, 15, 15, 4, 0x1000),
.spken = REG_FIELD_ID(0x1000, 14, 14, 4, 0x1000),
.spkmode = REG_FIELD_ID(0x1000, 10, 13, 4, 0x1000),
.spkmono = REG_FIELD_ID(0x1000, 9, 9, 4, 0x1000),
.micen = REG_FIELD_ID(0x1000, 8, 8, 4, 0x1000),
.micmode = REG_FIELD_ID(0x1000, 4, 7, 4, 0x1000),
.micmono = REG_FIELD_ID(0x1000, 3, 3, 4, 0x1000),
.wssrc = REG_FIELD_ID(0x1000, 2, 2, 4, 0x1000),
.bitwidth = REG_FIELD_ID(0x1000, 0, 1, 4, 0x1000),
.rdma_dyncclk = REG_FIELD_ID(0x8400, 12, 12, 2, 0x1000),
.rdma_bursten = REG_FIELD_ID(0x8400, 11, 11, 2, 0x1000),
.rdma_wpscnt = REG_FIELD_ID(0x8400, 8, 10, 2, 0x1000),
.rdma_intf = REG_FIELD_ID(0x8400, 4, 7, 2, 0x1000),
.rdma_fifowm = REG_FIELD_ID(0x8400, 1, 3, 2, 0x1000),
.rdma_enable = REG_FIELD_ID(0x8400, 0, 0, 2, 0x1000),
.wrdma_dyncclk = REG_FIELD_ID(0xB000, 12, 12, 2, 0x1000),
.wrdma_bursten = REG_FIELD_ID(0xB000, 11, 11, 2, 0x1000),
.wrdma_wpscnt = REG_FIELD_ID(0xB000, 8, 10, 2, 0x1000),
.wrdma_intf = REG_FIELD_ID(0xB000, 4, 7, 2, 0x1000),
.wrdma_fifowm = REG_FIELD_ID(0xB000, 1, 3, 2, 0x1000),
.wrdma_enable = REG_FIELD_ID(0xB000, 0, 0, 2, 0x1000),
.clk_name = (const char*[]) {
"pcnoc-mport-clk",
"pcnoc-sway-clk",
},
.num_clks = 2,
.dai_driver = apq8016_lpass_cpu_dai_driver,
.num_dai = ARRAY_SIZE(apq8016_lpass_cpu_dai_driver),
.dai_osr_clk_names = (const char *[]) {
"mi2s-osr-clk0",
"mi2s-osr-clk1",
"mi2s-osr-clk2",
"mi2s-osr-clk3",
},
.dai_bit_clk_names = (const char *[]) {
"mi2s-bit-clk0",
"mi2s-bit-clk1",
"mi2s-bit-clk2",
"mi2s-bit-clk3",
},
.init = apq8016_lpass_init,
.exit = apq8016_lpass_exit,
.alloc_dma_channel = apq8016_lpass_alloc_dma_channel,
.free_dma_channel = apq8016_lpass_free_dma_channel,
};
static const struct of_device_id apq8016_lpass_cpu_device_id[] __maybe_unused = {
{ .compatible = "qcom,lpass-cpu-apq8016", .data = &apq8016_data },
{ .compatible = "qcom,apq8016-lpass-cpu", .data = &apq8016_data },
{}
};
MODULE_DEVICE_TABLE(of, apq8016_lpass_cpu_device_id);
static struct platform_driver apq8016_lpass_cpu_platform_driver = {
.driver = {
.name = "apq8016-lpass-cpu",
.of_match_table = of_match_ptr(apq8016_lpass_cpu_device_id),
},
.probe = asoc_qcom_lpass_cpu_platform_probe,
.remove = asoc_qcom_lpass_cpu_platform_remove,
};
module_platform_driver(apq8016_lpass_cpu_platform_driver);
MODULE_DESCRIPTION("APQ8016 LPASS CPU Driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/qcom/lpass-apq8016.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2021, Linaro Limited
#include <linux/err.h>
#include <linux/init.h>
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
#include "q6dsp-lpass-clocks.h"
#include "q6prm.h"
#define Q6PRM_CLK(id) { \
.clk_id = id, \
.q6dsp_clk_id = Q6PRM_##id, \
.name = #id, \
.rate = 19200000, \
}
static const struct q6dsp_clk_init q6prm_clks[] = {
Q6PRM_CLK(LPASS_CLK_ID_PRI_MI2S_IBIT),
Q6PRM_CLK(LPASS_CLK_ID_PRI_MI2S_EBIT),
Q6PRM_CLK(LPASS_CLK_ID_SEC_MI2S_IBIT),
Q6PRM_CLK(LPASS_CLK_ID_SEC_MI2S_EBIT),
Q6PRM_CLK(LPASS_CLK_ID_TER_MI2S_IBIT),
Q6PRM_CLK(LPASS_CLK_ID_TER_MI2S_EBIT),
Q6PRM_CLK(LPASS_CLK_ID_QUAD_MI2S_IBIT),
Q6PRM_CLK(LPASS_CLK_ID_QUAD_MI2S_EBIT),
Q6PRM_CLK(LPASS_CLK_ID_SPEAKER_I2S_IBIT),
Q6PRM_CLK(LPASS_CLK_ID_SPEAKER_I2S_EBIT),
Q6PRM_CLK(LPASS_CLK_ID_SPEAKER_I2S_OSR),
Q6PRM_CLK(LPASS_CLK_ID_QUI_MI2S_IBIT),
Q6PRM_CLK(LPASS_CLK_ID_QUI_MI2S_EBIT),
Q6PRM_CLK(LPASS_CLK_ID_SEN_MI2S_IBIT),
Q6PRM_CLK(LPASS_CLK_ID_SEN_MI2S_EBIT),
Q6PRM_CLK(LPASS_CLK_ID_INT0_MI2S_IBIT),
Q6PRM_CLK(LPASS_CLK_ID_INT1_MI2S_IBIT),
Q6PRM_CLK(LPASS_CLK_ID_INT2_MI2S_IBIT),
Q6PRM_CLK(LPASS_CLK_ID_INT3_MI2S_IBIT),
Q6PRM_CLK(LPASS_CLK_ID_INT4_MI2S_IBIT),
Q6PRM_CLK(LPASS_CLK_ID_INT5_MI2S_IBIT),
Q6PRM_CLK(LPASS_CLK_ID_INT6_MI2S_IBIT),
Q6PRM_CLK(LPASS_CLK_ID_QUI_MI2S_OSR),
Q6PRM_CLK(LPASS_CLK_ID_WSA_CORE_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_WSA_CORE_NPL_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_VA_CORE_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_TX_CORE_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_TX_CORE_NPL_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_RX_CORE_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_RX_CORE_NPL_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_VA_CORE_2X_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_WSA2_CORE_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_WSA2_CORE_2X_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_RX_CORE_TX_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_RX_CORE_TX_2X_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_WSA_CORE_TX_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_WSA2_CORE_TX_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK),
Q6DSP_VOTE_CLK(LPASS_HW_MACRO_VOTE, Q6PRM_HW_CORE_ID_LPASS,
"LPASS_HW_MACRO"),
Q6DSP_VOTE_CLK(LPASS_HW_DCODEC_VOTE, Q6PRM_HW_CORE_ID_DCODEC,
"LPASS_HW_DCODEC"),
};
static const struct q6dsp_clk_desc q6dsp_clk_q6prm __maybe_unused = {
.clks = q6prm_clks,
.num_clks = ARRAY_SIZE(q6prm_clks),
.lpass_set_clk = q6prm_set_lpass_clock,
.lpass_vote_clk = q6prm_vote_lpass_core_hw,
.lpass_unvote_clk = q6prm_unvote_lpass_core_hw,
};
#ifdef CONFIG_OF
static const struct of_device_id q6prm_clock_device_id[] = {
{ .compatible = "qcom,q6prm-lpass-clocks", .data = &q6dsp_clk_q6prm },
{},
};
MODULE_DEVICE_TABLE(of, q6prm_clock_device_id);
#endif
static struct platform_driver q6prm_clock_platform_driver = {
.driver = {
.name = "q6prm-lpass-clock",
.of_match_table = of_match_ptr(q6prm_clock_device_id),
},
.probe = q6dsp_clock_dev_probe,
};
module_platform_driver(q6prm_clock_platform_driver);
MODULE_DESCRIPTION("Q6 Proxy Resource Manager LPASS clock driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/qcom/qdsp6/q6prm-clocks.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2020, Linaro Limited
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/soc/qcom/apr.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <dt-bindings/soc/qcom,gpr.h>
#include "q6apm.h"
#include "audioreach.h"
/* SubGraph Config */
struct apm_sub_graph_data {
struct apm_sub_graph_cfg sub_graph_cfg;
struct apm_prop_data perf_data;
struct apm_sg_prop_id_perf_mode perf;
struct apm_prop_data dir_data;
struct apm_sg_prop_id_direction dir;
struct apm_prop_data sid_data;
struct apm_sg_prop_id_scenario_id sid;
} __packed;
#define APM_SUB_GRAPH_CFG_NPROP 3
struct apm_sub_graph_params {
struct apm_module_param_data param_data;
uint32_t num_sub_graphs;
struct apm_sub_graph_data sg_cfg[];
} __packed;
#define APM_SUB_GRAPH_PSIZE(p, n) ALIGN(struct_size(p, sg_cfg, n), 8)
/* container config */
struct apm_container_obj {
struct apm_container_cfg container_cfg;
/* Capability ID list */
struct apm_prop_data cap_data;
uint32_t num_capability_id;
uint32_t capability_id;
/* Container graph Position */
struct apm_prop_data pos_data;
struct apm_cont_prop_id_graph_pos pos;
/* Container Stack size */
struct apm_prop_data stack_data;
struct apm_cont_prop_id_stack_size stack;
/* Container proc domain id */
struct apm_prop_data domain_data;
struct apm_cont_prop_id_domain domain;
} __packed;
struct apm_container_params {
struct apm_module_param_data param_data;
uint32_t num_containers;
struct apm_container_obj cont_obj[];
} __packed;
#define APM_CONTAINER_PSIZE(p, n) ALIGN(struct_size(p, cont_obj, n), 8)
/* Module List config */
struct apm_mod_list_obj {
/* Modules list cfg */
uint32_t sub_graph_id;
uint32_t container_id;
uint32_t num_modules;
struct apm_module_obj mod_cfg[];
} __packed;
#define APM_MOD_LIST_OBJ_PSIZE(p, n) struct_size(p, mod_cfg, n)
struct apm_module_list_params {
struct apm_module_param_data param_data;
uint32_t num_modules_list;
/* Module list config array */
struct apm_mod_list_obj mod_list_obj[];
} __packed;
/* Module Properties */
struct apm_mod_prop_obj {
u32 instance_id;
u32 num_props;
struct apm_prop_data prop_data_1;
struct apm_module_prop_id_port_info prop_id_port;
} __packed;
struct apm_prop_list_params {
struct apm_module_param_data param_data;
u32 num_modules_prop_cfg;
struct apm_mod_prop_obj mod_prop_obj[];
} __packed;
#define APM_MOD_PROP_PSIZE(p, n) ALIGN(struct_size(p, mod_prop_obj, n), 8)
/* Module Connections */
struct apm_mod_conn_list_params {
struct apm_module_param_data param_data;
u32 num_connections;
struct apm_module_conn_obj conn_obj[];
} __packed;
#define APM_MOD_CONN_PSIZE(p, n) ALIGN(struct_size(p, conn_obj, n), 8)
struct apm_graph_open_params {
struct apm_cmd_header *cmd_header;
struct apm_sub_graph_params *sg_data;
struct apm_container_params *cont_data;
struct apm_module_list_params *mod_list_data;
struct apm_prop_list_params *mod_prop_data;
struct apm_mod_conn_list_params *mod_conn_list_data;
} __packed;
struct apm_pcm_module_media_fmt_cmd {
struct apm_module_param_data param_data;
struct param_id_pcm_output_format_cfg header;
struct payload_pcm_output_format_cfg media_cfg;
} __packed;
struct apm_rd_shmem_module_config_cmd {
struct apm_module_param_data param_data;
struct param_id_rd_sh_mem_cfg cfg;
} __packed;
struct apm_sh_module_media_fmt_cmd {
struct media_format header;
struct payload_media_fmt_pcm cfg;
} __packed;
#define APM_SHMEM_FMT_CFG_PSIZE(ch) ALIGN( \
sizeof(struct apm_sh_module_media_fmt_cmd) + \
ch * sizeof(uint8_t), 8)
/* num of channels as argument */
#define APM_PCM_MODULE_FMT_CMD_PSIZE(ch) ALIGN( \
sizeof(struct apm_pcm_module_media_fmt_cmd) + \
ch * sizeof(uint8_t), 8)
#define APM_PCM_OUT_FMT_CFG_PSIZE(p, n) ALIGN(struct_size(p, channel_mapping, n), 4)
struct apm_i2s_module_intf_cfg {
struct apm_module_param_data param_data;
struct param_id_i2s_intf_cfg cfg;
} __packed;
#define APM_I2S_INTF_CFG_PSIZE ALIGN(sizeof(struct apm_i2s_module_intf_cfg), 8)
struct apm_module_hw_ep_mf_cfg {
struct apm_module_param_data param_data;
struct param_id_hw_ep_mf mf;
} __packed;
#define APM_HW_EP_CFG_PSIZE ALIGN(sizeof(struct apm_module_hw_ep_mf_cfg), 8)
#define APM_MFC_CFG_PSIZE(p, n) ALIGN(struct_size(p, channel_mapping, n), 4)
struct apm_module_frame_size_factor_cfg {
struct apm_module_param_data param_data;
uint32_t frame_size_factor;
} __packed;
#define APM_FS_CFG_PSIZE ALIGN(sizeof(struct apm_module_frame_size_factor_cfg), 8)
struct apm_module_hw_ep_power_mode_cfg {
struct apm_module_param_data param_data;
struct param_id_hw_ep_power_mode_cfg power_mode;
} __packed;
#define APM_HW_EP_PMODE_CFG_PSIZE ALIGN(sizeof(struct apm_module_hw_ep_power_mode_cfg), 8)
struct apm_module_hw_ep_dma_data_align_cfg {
struct apm_module_param_data param_data;
struct param_id_hw_ep_dma_data_align align;
} __packed;
#define APM_HW_EP_DALIGN_CFG_PSIZE ALIGN(sizeof(struct apm_module_hw_ep_dma_data_align_cfg), 8)
struct apm_gain_module_cfg {
struct apm_module_param_data param_data;
struct param_id_gain_cfg gain_cfg;
} __packed;
#define APM_GAIN_CFG_PSIZE ALIGN(sizeof(struct apm_gain_module_cfg), 8)
struct apm_codec_dma_module_intf_cfg {
struct apm_module_param_data param_data;
struct param_id_codec_dma_intf_cfg cfg;
} __packed;
#define APM_CDMA_INTF_CFG_PSIZE ALIGN(sizeof(struct apm_codec_dma_module_intf_cfg), 8)
struct apm_display_port_module_intf_cfg {
struct apm_module_param_data param_data;
struct param_id_display_port_intf_cfg cfg;
} __packed;
#define APM_DP_INTF_CFG_PSIZE ALIGN(sizeof(struct apm_display_port_module_intf_cfg), 8)
static void *__audioreach_alloc_pkt(int payload_size, uint32_t opcode, uint32_t token,
uint32_t src_port, uint32_t dest_port, bool has_cmd_hdr)
{
struct gpr_pkt *pkt;
void *p;
int pkt_size = GPR_HDR_SIZE + payload_size;
if (has_cmd_hdr)
pkt_size += APM_CMD_HDR_SIZE;
p = kzalloc(pkt_size, GFP_KERNEL);
if (!p)
return ERR_PTR(-ENOMEM);
pkt = p;
pkt->hdr.version = GPR_PKT_VER;
pkt->hdr.hdr_size = GPR_PKT_HEADER_WORD_SIZE;
pkt->hdr.pkt_size = pkt_size;
pkt->hdr.dest_port = dest_port;
pkt->hdr.src_port = src_port;
pkt->hdr.dest_domain = GPR_DOMAIN_ID_ADSP;
pkt->hdr.src_domain = GPR_DOMAIN_ID_APPS;
pkt->hdr.token = token;
pkt->hdr.opcode = opcode;
if (has_cmd_hdr) {
struct apm_cmd_header *cmd_header;
p = p + GPR_HDR_SIZE;
cmd_header = p;
cmd_header->payload_size = payload_size;
}
return pkt;
}
void *audioreach_alloc_pkt(int payload_size, uint32_t opcode, uint32_t token,
uint32_t src_port, uint32_t dest_port)
{
return __audioreach_alloc_pkt(payload_size, opcode, token, src_port, dest_port, false);
}
EXPORT_SYMBOL_GPL(audioreach_alloc_pkt);
void *audioreach_alloc_apm_pkt(int pkt_size, uint32_t opcode, uint32_t token, uint32_t src_port)
{
return __audioreach_alloc_pkt(pkt_size, opcode, token, src_port, APM_MODULE_INSTANCE_ID,
false);
}
EXPORT_SYMBOL_GPL(audioreach_alloc_apm_pkt);
void *audioreach_alloc_cmd_pkt(int payload_size, uint32_t opcode, uint32_t token,
uint32_t src_port, uint32_t dest_port)
{
return __audioreach_alloc_pkt(payload_size, opcode, token, src_port, dest_port, true);
}
EXPORT_SYMBOL_GPL(audioreach_alloc_cmd_pkt);
void *audioreach_alloc_apm_cmd_pkt(int pkt_size, uint32_t opcode, uint32_t token)
{
return __audioreach_alloc_pkt(pkt_size, opcode, token, GPR_APM_MODULE_IID,
APM_MODULE_INSTANCE_ID, true);
}
EXPORT_SYMBOL_GPL(audioreach_alloc_apm_cmd_pkt);
static void apm_populate_container_config(struct apm_container_obj *cfg,
struct audioreach_container *cont)
{
/* Container Config */
cfg->container_cfg.container_id = cont->container_id;
cfg->container_cfg.num_prop = 4;
/* Capability list */
cfg->cap_data.prop_id = APM_CONTAINER_PROP_ID_CAPABILITY_LIST;
cfg->cap_data.prop_size = APM_CONTAINER_PROP_ID_CAPABILITY_SIZE;
cfg->num_capability_id = 1;
cfg->capability_id = cont->capability_id;
/* Graph Position */
cfg->pos_data.prop_id = APM_CONTAINER_PROP_ID_GRAPH_POS;
cfg->pos_data.prop_size = sizeof(struct apm_cont_prop_id_graph_pos);
cfg->pos.graph_pos = cont->graph_pos;
/* Stack size */
cfg->stack_data.prop_id = APM_CONTAINER_PROP_ID_STACK_SIZE;
cfg->stack_data.prop_size = sizeof(struct apm_cont_prop_id_stack_size);
cfg->stack.stack_size = cont->stack_size;
/* Proc domain */
cfg->domain_data.prop_id = APM_CONTAINER_PROP_ID_PROC_DOMAIN;
cfg->domain_data.prop_size = sizeof(struct apm_cont_prop_id_domain);
cfg->domain.proc_domain = cont->proc_domain;
}
static void apm_populate_sub_graph_config(struct apm_sub_graph_data *cfg,
struct audioreach_sub_graph *sg)
{
cfg->sub_graph_cfg.sub_graph_id = sg->sub_graph_id;
cfg->sub_graph_cfg.num_sub_graph_prop = APM_SUB_GRAPH_CFG_NPROP;
/* Perf Mode */
cfg->perf_data.prop_id = APM_SUB_GRAPH_PROP_ID_PERF_MODE;
cfg->perf_data.prop_size = APM_SG_PROP_ID_PERF_MODE_SIZE;
cfg->perf.perf_mode = sg->perf_mode;
/* Direction */
cfg->dir_data.prop_id = APM_SUB_GRAPH_PROP_ID_DIRECTION;
cfg->dir_data.prop_size = APM_SG_PROP_ID_DIR_SIZE;
cfg->dir.direction = sg->direction;
/* Scenario ID */
cfg->sid_data.prop_id = APM_SUB_GRAPH_PROP_ID_SCENARIO_ID;
cfg->sid_data.prop_size = APM_SG_PROP_ID_SID_SIZE;
cfg->sid.scenario_id = sg->scenario_id;
}
static void apm_populate_module_prop_obj(struct apm_mod_prop_obj *obj,
struct audioreach_module *module)
{
obj->instance_id = module->instance_id;
obj->num_props = 1;
obj->prop_data_1.prop_id = APM_MODULE_PROP_ID_PORT_INFO;
obj->prop_data_1.prop_size = APM_MODULE_PROP_ID_PORT_INFO_SZ;
obj->prop_id_port.max_ip_port = module->max_ip_port;
obj->prop_id_port.max_op_port = module->max_op_port;
}
static void apm_populate_module_list_obj(struct apm_mod_list_obj *obj,
struct audioreach_container *container,
int sub_graph_id)
{
struct audioreach_module *module;
int i;
obj->sub_graph_id = sub_graph_id;
obj->container_id = container->container_id;
obj->num_modules = container->num_modules;
i = 0;
list_for_each_entry(module, &container->modules_list, node) {
obj->mod_cfg[i].module_id = module->module_id;
obj->mod_cfg[i].instance_id = module->instance_id;
i++;
}
}
static void audioreach_populate_graph(struct q6apm *apm, struct audioreach_graph_info *info,
struct apm_graph_open_params *open,
struct list_head *sg_list,
int num_sub_graphs)
{
struct apm_mod_conn_list_params *mc_data = open->mod_conn_list_data;
struct apm_module_list_params *ml_data = open->mod_list_data;
struct apm_prop_list_params *mp_data = open->mod_prop_data;
struct apm_container_params *c_data = open->cont_data;
struct apm_sub_graph_params *sg_data = open->sg_data;
int ncontainer = 0, nmodule = 0, nconn = 0;
struct apm_mod_prop_obj *module_prop_obj;
struct audioreach_container *container;
struct apm_module_conn_obj *conn_obj;
struct audioreach_module *module;
struct audioreach_sub_graph *sg;
struct apm_container_obj *cobj;
struct apm_mod_list_obj *mlobj;
int i = 0;
mlobj = &ml_data->mod_list_obj[0];
if (info->dst_mod_inst_id && info->src_mod_inst_id) {
conn_obj = &mc_data->conn_obj[nconn];
conn_obj->src_mod_inst_id = info->src_mod_inst_id;
conn_obj->src_mod_op_port_id = info->src_mod_op_port_id;
conn_obj->dst_mod_inst_id = info->dst_mod_inst_id;
conn_obj->dst_mod_ip_port_id = info->dst_mod_ip_port_id;
nconn++;
}
list_for_each_entry(sg, sg_list, node) {
struct apm_sub_graph_data *sg_cfg = &sg_data->sg_cfg[i++];
apm_populate_sub_graph_config(sg_cfg, sg);
list_for_each_entry(container, &sg->container_list, node) {
cobj = &c_data->cont_obj[ncontainer];
apm_populate_container_config(cobj, container);
apm_populate_module_list_obj(mlobj, container, sg->sub_graph_id);
list_for_each_entry(module, &container->modules_list, node) {
int pn;
module_prop_obj = &mp_data->mod_prop_obj[nmodule++];
apm_populate_module_prop_obj(module_prop_obj, module);
if (!module->max_op_port)
continue;
for (pn = 0; pn < module->max_op_port; pn++) {
if (module->dst_mod_inst_id[pn]) {
conn_obj = &mc_data->conn_obj[nconn];
conn_obj->src_mod_inst_id = module->instance_id;
conn_obj->src_mod_op_port_id =
module->src_mod_op_port_id[pn];
conn_obj->dst_mod_inst_id =
module->dst_mod_inst_id[pn];
conn_obj->dst_mod_ip_port_id =
module->dst_mod_ip_port_id[pn];
nconn++;
}
}
}
mlobj = (void *) mlobj + APM_MOD_LIST_OBJ_PSIZE(mlobj,
container->num_modules);
ncontainer++;
}
}
}
void *audioreach_alloc_graph_pkt(struct q6apm *apm, struct audioreach_graph_info *info)
{
int payload_size, sg_sz, cont_sz, ml_sz, mp_sz, mc_sz;
struct apm_module_param_data *param_data;
struct apm_container_params *cont_params;
struct audioreach_container *container;
struct apm_sub_graph_params *sg_params;
struct apm_mod_conn_list_params *mcon;
struct apm_graph_open_params params;
struct apm_prop_list_params *mprop;
struct audioreach_module *module;
struct audioreach_sub_graph *sgs;
struct apm_mod_list_obj *mlobj;
struct list_head *sg_list;
int num_connections = 0;
int num_containers = 0;
int num_sub_graphs = 0;
int num_modules = 0;
int num_modules_list;
struct gpr_pkt *pkt;
void *p;
sg_list = &info->sg_list;
ml_sz = 0;
/* add FE-BE connections */
if (info->dst_mod_inst_id && info->src_mod_inst_id)
num_connections++;
list_for_each_entry(sgs, sg_list, node) {
num_sub_graphs++;
list_for_each_entry(container, &sgs->container_list, node) {
num_containers++;
num_modules += container->num_modules;
ml_sz = ml_sz + sizeof(struct apm_module_list_params) +
APM_MOD_LIST_OBJ_PSIZE(mlobj, container->num_modules);
list_for_each_entry(module, &container->modules_list, node) {
num_connections += module->num_connections;
}
}
}
num_modules_list = num_containers;
sg_sz = APM_SUB_GRAPH_PSIZE(sg_params, num_sub_graphs);
cont_sz = APM_CONTAINER_PSIZE(cont_params, num_containers);
ml_sz = ALIGN(ml_sz, 8);
mp_sz = APM_MOD_PROP_PSIZE(mprop, num_modules);
mc_sz = APM_MOD_CONN_PSIZE(mcon, num_connections);
payload_size = sg_sz + cont_sz + ml_sz + mp_sz + mc_sz;
pkt = audioreach_alloc_apm_cmd_pkt(payload_size, APM_CMD_GRAPH_OPEN, 0);
if (IS_ERR(pkt))
return pkt;
p = (void *)pkt + GPR_HDR_SIZE + APM_CMD_HDR_SIZE;
/* SubGraph */
params.sg_data = p;
param_data = ¶ms.sg_data->param_data;
param_data->module_instance_id = APM_MODULE_INSTANCE_ID;
param_data->param_id = APM_PARAM_ID_SUB_GRAPH_CONFIG;
param_data->param_size = sg_sz - APM_MODULE_PARAM_DATA_SIZE;
params.sg_data->num_sub_graphs = num_sub_graphs;
p += sg_sz;
/* Container */
params.cont_data = p;
param_data = ¶ms.cont_data->param_data;
param_data->module_instance_id = APM_MODULE_INSTANCE_ID;
param_data->param_id = APM_PARAM_ID_CONTAINER_CONFIG;
param_data->param_size = cont_sz - APM_MODULE_PARAM_DATA_SIZE;
params.cont_data->num_containers = num_containers;
p += cont_sz;
/* Module List*/
params.mod_list_data = p;
param_data = ¶ms.mod_list_data->param_data;
param_data->module_instance_id = APM_MODULE_INSTANCE_ID;
param_data->param_id = APM_PARAM_ID_MODULE_LIST;
param_data->param_size = ml_sz - APM_MODULE_PARAM_DATA_SIZE;
params.mod_list_data->num_modules_list = num_modules_list;
p += ml_sz;
/* Module Properties */
params.mod_prop_data = p;
param_data = ¶ms.mod_prop_data->param_data;
param_data->module_instance_id = APM_MODULE_INSTANCE_ID;
param_data->param_id = APM_PARAM_ID_MODULE_PROP;
param_data->param_size = mp_sz - APM_MODULE_PARAM_DATA_SIZE;
params.mod_prop_data->num_modules_prop_cfg = num_modules;
p += mp_sz;
/* Module Connections */
params.mod_conn_list_data = p;
param_data = ¶ms.mod_conn_list_data->param_data;
param_data->module_instance_id = APM_MODULE_INSTANCE_ID;
param_data->param_id = APM_PARAM_ID_MODULE_CONN;
param_data->param_size = mc_sz - APM_MODULE_PARAM_DATA_SIZE;
params.mod_conn_list_data->num_connections = num_connections;
p += mc_sz;
audioreach_populate_graph(apm, info, ¶ms, sg_list, num_sub_graphs);
return pkt;
}
EXPORT_SYMBOL_GPL(audioreach_alloc_graph_pkt);
int audioreach_send_cmd_sync(struct device *dev, gpr_device_t *gdev,
struct gpr_ibasic_rsp_result_t *result, struct mutex *cmd_lock,
gpr_port_t *port, wait_queue_head_t *cmd_wait,
struct gpr_pkt *pkt, uint32_t rsp_opcode)
{
struct gpr_hdr *hdr = &pkt->hdr;
int rc;
mutex_lock(cmd_lock);
result->opcode = 0;
result->status = 0;
if (port)
rc = gpr_send_port_pkt(port, pkt);
else if (gdev)
rc = gpr_send_pkt(gdev, pkt);
else
rc = -EINVAL;
if (rc < 0)
goto err;
if (rsp_opcode)
rc = wait_event_timeout(*cmd_wait, (result->opcode == hdr->opcode) ||
(result->opcode == rsp_opcode), 5 * HZ);
else
rc = wait_event_timeout(*cmd_wait, (result->opcode == hdr->opcode), 5 * HZ);
if (!rc) {
dev_err(dev, "CMD timeout for [%x] opcode\n", hdr->opcode);
rc = -ETIMEDOUT;
} else if (result->status > 0) {
dev_err(dev, "DSP returned error[%x] %x\n", hdr->opcode, result->status);
rc = -EINVAL;
} else {
/* DSP successfully finished the command */
rc = 0;
}
err:
mutex_unlock(cmd_lock);
return rc;
}
EXPORT_SYMBOL_GPL(audioreach_send_cmd_sync);
int audioreach_graph_send_cmd_sync(struct q6apm_graph *graph, struct gpr_pkt *pkt,
uint32_t rsp_opcode)
{
return audioreach_send_cmd_sync(graph->dev, NULL, &graph->result, &graph->lock,
graph->port, &graph->cmd_wait, pkt, rsp_opcode);
}
EXPORT_SYMBOL_GPL(audioreach_graph_send_cmd_sync);
static int audioreach_display_port_set_media_format(struct q6apm_graph *graph,
struct audioreach_module *module,
struct audioreach_module_config *cfg)
{
struct apm_display_port_module_intf_cfg *intf_cfg;
struct apm_module_frame_size_factor_cfg *fs_cfg;
struct apm_module_param_data *param_data;
struct apm_module_hw_ep_mf_cfg *hw_cfg;
int ic_sz, ep_sz, fs_sz, dl_sz;
int rc, payload_size;
struct gpr_pkt *pkt;
void *p;
ic_sz = APM_DP_INTF_CFG_PSIZE;
ep_sz = APM_HW_EP_CFG_PSIZE;
fs_sz = APM_FS_CFG_PSIZE;
dl_sz = 0;
payload_size = ic_sz + ep_sz + fs_sz + dl_sz;
pkt = audioreach_alloc_apm_cmd_pkt(payload_size, APM_CMD_SET_CFG, 0);
if (IS_ERR(pkt))
return PTR_ERR(pkt);
p = (void *)pkt + GPR_HDR_SIZE + APM_CMD_HDR_SIZE;
hw_cfg = p;
param_data = &hw_cfg->param_data;
param_data->module_instance_id = module->instance_id;
param_data->error_code = 0;
param_data->param_id = PARAM_ID_HW_EP_MF_CFG;
param_data->param_size = ep_sz - APM_MODULE_PARAM_DATA_SIZE;
hw_cfg->mf.sample_rate = cfg->sample_rate;
hw_cfg->mf.bit_width = cfg->bit_width;
hw_cfg->mf.num_channels = cfg->num_channels;
hw_cfg->mf.data_format = module->data_format;
p += ep_sz;
fs_cfg = p;
param_data = &fs_cfg->param_data;
param_data->module_instance_id = module->instance_id;
param_data->error_code = 0;
param_data->param_id = PARAM_ID_HW_EP_FRAME_SIZE_FACTOR;
param_data->param_size = fs_sz - APM_MODULE_PARAM_DATA_SIZE;
fs_cfg->frame_size_factor = 1;
p += fs_sz;
intf_cfg = p;
param_data = &intf_cfg->param_data;
param_data->module_instance_id = module->instance_id;
param_data->error_code = 0;
param_data->param_id = PARAM_ID_DISPLAY_PORT_INTF_CFG;
param_data->param_size = ic_sz - APM_MODULE_PARAM_DATA_SIZE;
intf_cfg->cfg.channel_allocation = cfg->channel_allocation;
intf_cfg->cfg.mst_idx = 0;
intf_cfg->cfg.dptx_idx = cfg->dp_idx;
rc = q6apm_send_cmd_sync(graph->apm, pkt, 0);
kfree(pkt);
return rc;
}
/* LPASS Codec DMA port Module Media Format Setup */
static int audioreach_codec_dma_set_media_format(struct q6apm_graph *graph,
struct audioreach_module *module,
struct audioreach_module_config *cfg)
{
struct apm_codec_dma_module_intf_cfg *intf_cfg;
struct apm_module_frame_size_factor_cfg *fs_cfg;
struct apm_module_hw_ep_power_mode_cfg *pm_cfg;
struct apm_module_param_data *param_data;
struct apm_module_hw_ep_mf_cfg *hw_cfg;
int ic_sz, ep_sz, fs_sz, pm_sz, dl_sz;
int rc, payload_size;
struct gpr_pkt *pkt;
void *p;
ic_sz = APM_CDMA_INTF_CFG_PSIZE;
ep_sz = APM_HW_EP_CFG_PSIZE;
fs_sz = APM_FS_CFG_PSIZE;
pm_sz = APM_HW_EP_PMODE_CFG_PSIZE;
dl_sz = 0;
payload_size = ic_sz + ep_sz + fs_sz + pm_sz + dl_sz;
pkt = audioreach_alloc_apm_cmd_pkt(payload_size, APM_CMD_SET_CFG, 0);
if (IS_ERR(pkt))
return PTR_ERR(pkt);
p = (void *)pkt + GPR_HDR_SIZE + APM_CMD_HDR_SIZE;
hw_cfg = p;
param_data = &hw_cfg->param_data;
param_data->module_instance_id = module->instance_id;
param_data->error_code = 0;
param_data->param_id = PARAM_ID_HW_EP_MF_CFG;
param_data->param_size = ep_sz - APM_MODULE_PARAM_DATA_SIZE;
hw_cfg->mf.sample_rate = cfg->sample_rate;
hw_cfg->mf.bit_width = cfg->bit_width;
hw_cfg->mf.num_channels = cfg->num_channels;
hw_cfg->mf.data_format = module->data_format;
p += ep_sz;
fs_cfg = p;
param_data = &fs_cfg->param_data;
param_data->module_instance_id = module->instance_id;
param_data->error_code = 0;
param_data->param_id = PARAM_ID_HW_EP_FRAME_SIZE_FACTOR;
param_data->param_size = fs_sz - APM_MODULE_PARAM_DATA_SIZE;
fs_cfg->frame_size_factor = 1;
p += fs_sz;
intf_cfg = p;
param_data = &intf_cfg->param_data;
param_data->module_instance_id = module->instance_id;
param_data->error_code = 0;
param_data->param_id = PARAM_ID_CODEC_DMA_INTF_CFG;
param_data->param_size = ic_sz - APM_MODULE_PARAM_DATA_SIZE;
intf_cfg->cfg.lpaif_type = module->hw_interface_type;
intf_cfg->cfg.intf_index = module->hw_interface_idx;
intf_cfg->cfg.active_channels_mask = (1 << cfg->num_channels) - 1;
p += ic_sz;
pm_cfg = p;
param_data = &pm_cfg->param_data;
param_data->module_instance_id = module->instance_id;
param_data->error_code = 0;
param_data->param_id = PARAM_ID_HW_EP_POWER_MODE_CFG;
param_data->param_size = pm_sz - APM_MODULE_PARAM_DATA_SIZE;
pm_cfg->power_mode.power_mode = 0;
rc = q6apm_send_cmd_sync(graph->apm, pkt, 0);
kfree(pkt);
return rc;
}
int audioreach_send_u32_param(struct q6apm_graph *graph, struct audioreach_module *module,
uint32_t param_id, uint32_t param_val)
{
struct apm_module_param_data *param_data;
struct gpr_pkt *pkt;
uint32_t *param;
int rc, payload_size;
void *p;
payload_size = sizeof(uint32_t) + APM_MODULE_PARAM_DATA_SIZE;
p = audioreach_alloc_apm_cmd_pkt(payload_size, APM_CMD_SET_CFG, 0);
if (IS_ERR(p))
return -ENOMEM;
pkt = p;
p = p + GPR_HDR_SIZE + APM_CMD_HDR_SIZE;
param_data = p;
param_data->module_instance_id = module->instance_id;
param_data->error_code = 0;
param_data->param_id = param_id;
param_data->param_size = sizeof(uint32_t);
p = p + APM_MODULE_PARAM_DATA_SIZE;
param = p;
*param = param_val;
rc = q6apm_send_cmd_sync(graph->apm, pkt, 0);
kfree(pkt);
return rc;
}
EXPORT_SYMBOL_GPL(audioreach_send_u32_param);
static int audioreach_sal_limiter_enable(struct q6apm_graph *graph,
struct audioreach_module *module, bool enable)
{
return audioreach_send_u32_param(graph, module, PARAM_ID_SAL_LIMITER_ENABLE, enable);
}
static int audioreach_sal_set_media_format(struct q6apm_graph *graph,
struct audioreach_module *module,
struct audioreach_module_config *cfg)
{
return audioreach_send_u32_param(graph, module, PARAM_ID_SAL_OUTPUT_CFG, cfg->bit_width);
}
static int audioreach_module_enable(struct q6apm_graph *graph,
struct audioreach_module *module,
bool enable)
{
return audioreach_send_u32_param(graph, module, PARAM_ID_MODULE_ENABLE, enable);
}
static int audioreach_gapless_set_media_format(struct q6apm_graph *graph,
struct audioreach_module *module,
struct audioreach_module_config *cfg)
{
return audioreach_send_u32_param(graph, module, PARAM_ID_EARLY_EOS_DELAY,
EARLY_EOS_DELAY_MS);
}
static int audioreach_mfc_set_media_format(struct q6apm_graph *graph,
struct audioreach_module *module,
struct audioreach_module_config *cfg)
{
struct apm_module_param_data *param_data;
struct param_id_mfc_media_format *media_format;
uint32_t num_channels = cfg->num_channels;
int payload_size;
struct gpr_pkt *pkt;
int rc;
void *p;
payload_size = APM_MFC_CFG_PSIZE(media_format, num_channels) +
APM_MODULE_PARAM_DATA_SIZE;
pkt = audioreach_alloc_apm_cmd_pkt(payload_size, APM_CMD_SET_CFG, 0);
if (IS_ERR(pkt))
return PTR_ERR(pkt);
p = (void *)pkt + GPR_HDR_SIZE + APM_CMD_HDR_SIZE;
param_data = p;
param_data->module_instance_id = module->instance_id;
param_data->error_code = 0;
param_data->param_id = PARAM_ID_MFC_OUTPUT_MEDIA_FORMAT;
param_data->param_size = APM_MFC_CFG_PSIZE(media_format, num_channels);
p = p + APM_MODULE_PARAM_DATA_SIZE;
media_format = p;
media_format->sample_rate = cfg->sample_rate;
media_format->bit_width = cfg->bit_width;
media_format->num_channels = cfg->num_channels;
if (num_channels == 1) {
media_format->channel_mapping[0] = PCM_CHANNEL_L;
} else if (num_channels == 2) {
media_format->channel_mapping[0] = PCM_CHANNEL_L;
media_format->channel_mapping[1] = PCM_CHANNEL_R;
}
rc = q6apm_send_cmd_sync(graph->apm, pkt, 0);
kfree(pkt);
return rc;
}
static int audioreach_set_compr_media_format(struct media_format *media_fmt_hdr,
void *p, struct audioreach_module_config *mcfg)
{
struct payload_media_fmt_aac_t *aac_cfg;
struct payload_media_fmt_pcm *mp3_cfg;
struct payload_media_fmt_flac_t *flac_cfg;
switch (mcfg->fmt) {
case SND_AUDIOCODEC_MP3:
media_fmt_hdr->data_format = DATA_FORMAT_RAW_COMPRESSED;
media_fmt_hdr->fmt_id = MEDIA_FMT_ID_MP3;
media_fmt_hdr->payload_size = 0;
p = p + sizeof(*media_fmt_hdr);
mp3_cfg = p;
mp3_cfg->sample_rate = mcfg->sample_rate;
mp3_cfg->bit_width = mcfg->bit_width;
mp3_cfg->alignment = PCM_LSB_ALIGNED;
mp3_cfg->bits_per_sample = mcfg->bit_width;
mp3_cfg->q_factor = mcfg->bit_width - 1;
mp3_cfg->endianness = PCM_LITTLE_ENDIAN;
mp3_cfg->num_channels = mcfg->num_channels;
if (mcfg->num_channels == 1) {
mp3_cfg->channel_mapping[0] = PCM_CHANNEL_L;
} else if (mcfg->num_channels == 2) {
mp3_cfg->channel_mapping[0] = PCM_CHANNEL_L;
mp3_cfg->channel_mapping[1] = PCM_CHANNEL_R;
}
break;
case SND_AUDIOCODEC_AAC:
media_fmt_hdr->data_format = DATA_FORMAT_RAW_COMPRESSED;
media_fmt_hdr->fmt_id = MEDIA_FMT_ID_AAC;
media_fmt_hdr->payload_size = sizeof(struct payload_media_fmt_aac_t);
p = p + sizeof(*media_fmt_hdr);
aac_cfg = p;
aac_cfg->aac_fmt_flag = 0;
aac_cfg->audio_obj_type = 5;
aac_cfg->num_channels = mcfg->num_channels;
aac_cfg->total_size_of_PCE_bits = 0;
aac_cfg->sample_rate = mcfg->sample_rate;
break;
case SND_AUDIOCODEC_FLAC:
media_fmt_hdr->data_format = DATA_FORMAT_RAW_COMPRESSED;
media_fmt_hdr->fmt_id = MEDIA_FMT_ID_FLAC;
media_fmt_hdr->payload_size = sizeof(struct payload_media_fmt_flac_t);
p = p + sizeof(*media_fmt_hdr);
flac_cfg = p;
flac_cfg->sample_size = mcfg->codec.options.flac_d.sample_size;
flac_cfg->num_channels = mcfg->num_channels;
flac_cfg->min_blk_size = mcfg->codec.options.flac_d.min_blk_size;
flac_cfg->max_blk_size = mcfg->codec.options.flac_d.max_blk_size;
flac_cfg->sample_rate = mcfg->sample_rate;
flac_cfg->min_frame_size = mcfg->codec.options.flac_d.min_frame_size;
flac_cfg->max_frame_size = mcfg->codec.options.flac_d.max_frame_size;
break;
default:
return -EINVAL;
}
return 0;
}
int audioreach_compr_set_param(struct q6apm_graph *graph, struct audioreach_module_config *mcfg)
{
struct media_format *header;
struct gpr_pkt *pkt;
int iid, payload_size, rc;
void *p;
payload_size = sizeof(struct apm_sh_module_media_fmt_cmd);
iid = q6apm_graph_get_rx_shmem_module_iid(graph);
pkt = audioreach_alloc_cmd_pkt(payload_size, DATA_CMD_WR_SH_MEM_EP_MEDIA_FORMAT,
0, graph->port->id, iid);
if (IS_ERR(pkt))
return -ENOMEM;
p = (void *)pkt + GPR_HDR_SIZE;
header = p;
rc = audioreach_set_compr_media_format(header, p, mcfg);
if (rc) {
kfree(pkt);
return rc;
}
rc = gpr_send_port_pkt(graph->port, pkt);
kfree(pkt);
return rc;
}
EXPORT_SYMBOL_GPL(audioreach_compr_set_param);
static int audioreach_i2s_set_media_format(struct q6apm_graph *graph,
struct audioreach_module *module,
struct audioreach_module_config *cfg)
{
struct apm_module_frame_size_factor_cfg *fs_cfg;
struct apm_module_param_data *param_data;
struct apm_i2s_module_intf_cfg *intf_cfg;
struct apm_module_hw_ep_mf_cfg *hw_cfg;
int ic_sz, ep_sz, fs_sz;
int rc, payload_size;
struct gpr_pkt *pkt;
void *p;
ic_sz = APM_I2S_INTF_CFG_PSIZE;
ep_sz = APM_HW_EP_CFG_PSIZE;
fs_sz = APM_FS_CFG_PSIZE;
payload_size = ic_sz + ep_sz + fs_sz;
pkt = audioreach_alloc_apm_cmd_pkt(payload_size, APM_CMD_SET_CFG, 0);
if (IS_ERR(pkt))
return PTR_ERR(pkt);
p = (void *)pkt + GPR_HDR_SIZE + APM_CMD_HDR_SIZE;
intf_cfg = p;
param_data = &intf_cfg->param_data;
param_data->module_instance_id = module->instance_id;
param_data->error_code = 0;
param_data->param_id = PARAM_ID_I2S_INTF_CFG;
param_data->param_size = ic_sz - APM_MODULE_PARAM_DATA_SIZE;
intf_cfg->cfg.intf_idx = module->hw_interface_idx;
intf_cfg->cfg.sd_line_idx = module->sd_line_idx;
switch (cfg->fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BP_FP:
intf_cfg->cfg.ws_src = CONFIG_I2S_WS_SRC_INTERNAL;
break;
case SND_SOC_DAIFMT_BC_FC:
/* CPU is slave */
intf_cfg->cfg.ws_src = CONFIG_I2S_WS_SRC_EXTERNAL;
break;
default:
break;
}
p += ic_sz;
hw_cfg = p;
param_data = &hw_cfg->param_data;
param_data->module_instance_id = module->instance_id;
param_data->error_code = 0;
param_data->param_id = PARAM_ID_HW_EP_MF_CFG;
param_data->param_size = ep_sz - APM_MODULE_PARAM_DATA_SIZE;
hw_cfg->mf.sample_rate = cfg->sample_rate;
hw_cfg->mf.bit_width = cfg->bit_width;
hw_cfg->mf.num_channels = cfg->num_channels;
hw_cfg->mf.data_format = module->data_format;
p += ep_sz;
fs_cfg = p;
param_data = &fs_cfg->param_data;
param_data->module_instance_id = module->instance_id;
param_data->error_code = 0;
param_data->param_id = PARAM_ID_HW_EP_FRAME_SIZE_FACTOR;
param_data->param_size = fs_sz - APM_MODULE_PARAM_DATA_SIZE;
fs_cfg->frame_size_factor = 1;
rc = q6apm_send_cmd_sync(graph->apm, pkt, 0);
kfree(pkt);
return rc;
}
static int audioreach_logging_set_media_format(struct q6apm_graph *graph,
struct audioreach_module *module)
{
struct apm_module_param_data *param_data;
struct data_logging_config *cfg;
int rc, payload_size;
struct gpr_pkt *pkt;
void *p;
payload_size = sizeof(*cfg) + APM_MODULE_PARAM_DATA_SIZE;
pkt = audioreach_alloc_apm_cmd_pkt(payload_size, APM_CMD_SET_CFG, 0);
if (IS_ERR(pkt))
return PTR_ERR(pkt);
p = (void *)pkt + GPR_HDR_SIZE + APM_CMD_HDR_SIZE;
param_data = p;
param_data->module_instance_id = module->instance_id;
param_data->error_code = 0;
param_data->param_id = PARAM_ID_DATA_LOGGING_CONFIG;
param_data->param_size = payload_size - APM_MODULE_PARAM_DATA_SIZE;
p = p + APM_MODULE_PARAM_DATA_SIZE;
cfg = p;
cfg->log_code = module->log_code;
cfg->log_tap_point_id = module->log_tap_point_id;
cfg->mode = module->log_mode;
rc = q6apm_send_cmd_sync(graph->apm, pkt, 0);
kfree(pkt);
return rc;
}
static int audioreach_pcm_set_media_format(struct q6apm_graph *graph,
struct audioreach_module *module,
struct audioreach_module_config *mcfg)
{
struct payload_pcm_output_format_cfg *media_cfg;
uint32_t num_channels = mcfg->num_channels;
struct apm_pcm_module_media_fmt_cmd *cfg;
struct apm_module_param_data *param_data;
int rc, payload_size;
struct gpr_pkt *pkt;
if (num_channels > 2) {
dev_err(graph->dev, "Error: Invalid channels (%d)!\n", num_channels);
return -EINVAL;
}
payload_size = APM_PCM_MODULE_FMT_CMD_PSIZE(num_channels);
pkt = audioreach_alloc_apm_cmd_pkt(payload_size, APM_CMD_SET_CFG, 0);
if (IS_ERR(pkt))
return PTR_ERR(pkt);
cfg = (void *)pkt + GPR_HDR_SIZE + APM_CMD_HDR_SIZE;
param_data = &cfg->param_data;
param_data->module_instance_id = module->instance_id;
param_data->error_code = 0;
param_data->param_id = PARAM_ID_PCM_OUTPUT_FORMAT_CFG;
param_data->param_size = payload_size - APM_MODULE_PARAM_DATA_SIZE;
cfg->header.data_format = DATA_FORMAT_FIXED_POINT;
cfg->header.fmt_id = MEDIA_FMT_ID_PCM;
cfg->header.payload_size = APM_PCM_OUT_FMT_CFG_PSIZE(media_cfg, num_channels);
media_cfg = &cfg->media_cfg;
media_cfg->alignment = PCM_LSB_ALIGNED;
media_cfg->bit_width = mcfg->bit_width;
media_cfg->endianness = PCM_LITTLE_ENDIAN;
media_cfg->interleaved = module->interleave_type;
media_cfg->num_channels = mcfg->num_channels;
media_cfg->q_factor = mcfg->bit_width - 1;
media_cfg->bits_per_sample = mcfg->bit_width;
if (num_channels == 1) {
media_cfg->channel_mapping[0] = PCM_CHANNEL_L;
} else if (num_channels == 2) {
media_cfg->channel_mapping[0] = PCM_CHANNEL_L;
media_cfg->channel_mapping[1] = PCM_CHANNEL_R;
}
rc = q6apm_send_cmd_sync(graph->apm, pkt, 0);
kfree(pkt);
return rc;
}
static int audioreach_shmem_set_media_format(struct q6apm_graph *graph,
struct audioreach_module *module,
struct audioreach_module_config *mcfg)
{
uint32_t num_channels = mcfg->num_channels;
struct apm_module_param_data *param_data;
struct payload_media_fmt_pcm *cfg;
struct media_format *header;
int rc, payload_size;
struct gpr_pkt *pkt;
void *p;
if (num_channels > 2) {
dev_err(graph->dev, "Error: Invalid channels (%d)!\n", num_channels);
return -EINVAL;
}
payload_size = APM_SHMEM_FMT_CFG_PSIZE(num_channels) + APM_MODULE_PARAM_DATA_SIZE;
pkt = audioreach_alloc_cmd_pkt(payload_size, APM_CMD_SET_CFG, 0,
graph->port->id, module->instance_id);
if (IS_ERR(pkt))
return PTR_ERR(pkt);
p = (void *)pkt + GPR_HDR_SIZE + APM_CMD_HDR_SIZE;
param_data = p;
param_data->module_instance_id = module->instance_id;
param_data->error_code = 0;
param_data->param_id = PARAM_ID_MEDIA_FORMAT;
param_data->param_size = payload_size - APM_MODULE_PARAM_DATA_SIZE;
p = p + APM_MODULE_PARAM_DATA_SIZE;
header = p;
if (mcfg->fmt == SND_AUDIOCODEC_PCM) {
header->data_format = DATA_FORMAT_FIXED_POINT;
header->fmt_id = MEDIA_FMT_ID_PCM;
header->payload_size = payload_size - sizeof(*header);
p = p + sizeof(*header);
cfg = p;
cfg->sample_rate = mcfg->sample_rate;
cfg->bit_width = mcfg->bit_width;
cfg->alignment = PCM_LSB_ALIGNED;
cfg->bits_per_sample = mcfg->bit_width;
cfg->q_factor = mcfg->bit_width - 1;
cfg->endianness = PCM_LITTLE_ENDIAN;
cfg->num_channels = mcfg->num_channels;
if (mcfg->num_channels == 1)
cfg->channel_mapping[0] = PCM_CHANNEL_L;
else if (num_channels == 2) {
cfg->channel_mapping[0] = PCM_CHANNEL_L;
cfg->channel_mapping[1] = PCM_CHANNEL_R;
}
} else {
rc = audioreach_set_compr_media_format(header, p, mcfg);
if (rc) {
kfree(pkt);
return rc;
}
}
rc = audioreach_graph_send_cmd_sync(graph, pkt, 0);
kfree(pkt);
return rc;
}
int audioreach_gain_set_vol_ctrl(struct q6apm *apm, struct audioreach_module *module, int vol)
{
struct param_id_vol_ctrl_master_gain *cfg;
struct apm_module_param_data *param_data;
int rc, payload_size;
struct gpr_pkt *pkt;
void *p;
payload_size = sizeof(*cfg) + APM_MODULE_PARAM_DATA_SIZE;
pkt = audioreach_alloc_apm_cmd_pkt(payload_size, APM_CMD_SET_CFG, 0);
if (IS_ERR(pkt))
return PTR_ERR(pkt);
p = (void *)pkt + GPR_HDR_SIZE + APM_CMD_HDR_SIZE;
param_data = p;
param_data->module_instance_id = module->instance_id;
param_data->error_code = 0;
param_data->param_id = PARAM_ID_VOL_CTRL_MASTER_GAIN;
param_data->param_size = payload_size - APM_MODULE_PARAM_DATA_SIZE;
p = p + APM_MODULE_PARAM_DATA_SIZE;
cfg = p;
cfg->master_gain = vol;
rc = q6apm_send_cmd_sync(apm, pkt, 0);
kfree(pkt);
return rc;
}
EXPORT_SYMBOL_GPL(audioreach_gain_set_vol_ctrl);
static int audioreach_gain_set(struct q6apm_graph *graph, struct audioreach_module *module)
{
struct apm_module_param_data *param_data;
struct apm_gain_module_cfg *cfg;
int rc, payload_size;
struct gpr_pkt *pkt;
payload_size = APM_GAIN_CFG_PSIZE;
pkt = audioreach_alloc_apm_cmd_pkt(payload_size, APM_CMD_SET_CFG, 0);
if (IS_ERR(pkt))
return PTR_ERR(pkt);
cfg = (void *)pkt + GPR_HDR_SIZE + APM_CMD_HDR_SIZE;
param_data = &cfg->param_data;
param_data->module_instance_id = module->instance_id;
param_data->error_code = 0;
param_data->param_id = APM_PARAM_ID_GAIN;
param_data->param_size = payload_size - APM_MODULE_PARAM_DATA_SIZE;
cfg->gain_cfg.gain = module->gain;
rc = q6apm_send_cmd_sync(graph->apm, pkt, 0);
kfree(pkt);
return rc;
}
int audioreach_set_media_format(struct q6apm_graph *graph, struct audioreach_module *module,
struct audioreach_module_config *cfg)
{
int rc;
switch (module->module_id) {
case MODULE_ID_DATA_LOGGING:
rc = audioreach_module_enable(graph, module, true);
if (!rc)
rc = audioreach_logging_set_media_format(graph, module);
break;
case MODULE_ID_PCM_DEC:
case MODULE_ID_PCM_ENC:
case MODULE_ID_PCM_CNV:
case MODULE_ID_PLACEHOLDER_DECODER:
case MODULE_ID_PLACEHOLDER_ENCODER:
rc = audioreach_pcm_set_media_format(graph, module, cfg);
break;
case MODULE_ID_DISPLAY_PORT_SINK:
rc = audioreach_display_port_set_media_format(graph, module, cfg);
break;
case MODULE_ID_I2S_SOURCE:
case MODULE_ID_I2S_SINK:
rc = audioreach_i2s_set_media_format(graph, module, cfg);
break;
case MODULE_ID_WR_SHARED_MEM_EP:
rc = audioreach_shmem_set_media_format(graph, module, cfg);
break;
case MODULE_ID_GAIN:
rc = audioreach_gain_set(graph, module);
break;
case MODULE_ID_CODEC_DMA_SINK:
case MODULE_ID_CODEC_DMA_SOURCE:
rc = audioreach_codec_dma_set_media_format(graph, module, cfg);
break;
case MODULE_ID_SAL:
rc = audioreach_sal_set_media_format(graph, module, cfg);
if (!rc)
rc = audioreach_sal_limiter_enable(graph, module, true);
break;
case MODULE_ID_MFC:
rc = audioreach_mfc_set_media_format(graph, module, cfg);
break;
case MODULE_ID_GAPLESS:
rc = audioreach_gapless_set_media_format(graph, module, cfg);
break;
default:
rc = 0;
}
return rc;
}
EXPORT_SYMBOL_GPL(audioreach_set_media_format);
void audioreach_graph_free_buf(struct q6apm_graph *graph)
{
struct audioreach_graph_data *port;
mutex_lock(&graph->lock);
port = &graph->rx_data;
port->num_periods = 0;
kfree(port->buf);
port->buf = NULL;
port = &graph->tx_data;
port->num_periods = 0;
kfree(port->buf);
port->buf = NULL;
mutex_unlock(&graph->lock);
}
EXPORT_SYMBOL_GPL(audioreach_graph_free_buf);
int audioreach_map_memory_regions(struct q6apm_graph *graph, unsigned int dir, size_t period_sz,
unsigned int periods, bool is_contiguous)
{
struct apm_shared_map_region_payload *mregions;
struct apm_cmd_shared_mem_map_regions *cmd;
uint32_t num_regions, buf_sz, payload_size;
struct audioreach_graph_data *data;
struct gpr_pkt *pkt;
void *p;
int rc, i;
if (dir == SNDRV_PCM_STREAM_PLAYBACK)
data = &graph->rx_data;
else
data = &graph->tx_data;
if (is_contiguous) {
num_regions = 1;
buf_sz = period_sz * periods;
} else {
buf_sz = period_sz;
num_regions = periods;
}
/* DSP expects size should be aligned to 4K */
buf_sz = ALIGN(buf_sz, 4096);
payload_size = sizeof(*cmd) + (sizeof(*mregions) * num_regions);
pkt = audioreach_alloc_apm_pkt(payload_size, APM_CMD_SHARED_MEM_MAP_REGIONS, dir,
graph->port->id);
if (IS_ERR(pkt))
return PTR_ERR(pkt);
p = (void *)pkt + GPR_HDR_SIZE;
cmd = p;
cmd->mem_pool_id = APM_MEMORY_MAP_SHMEM8_4K_POOL;
cmd->num_regions = num_regions;
cmd->property_flag = 0x0;
mregions = p + sizeof(*cmd);
mutex_lock(&graph->lock);
for (i = 0; i < num_regions; i++) {
struct audio_buffer *ab;
ab = &data->buf[i];
mregions->shm_addr_lsw = lower_32_bits(ab->phys);
mregions->shm_addr_msw = upper_32_bits(ab->phys);
mregions->mem_size_bytes = buf_sz;
++mregions;
}
mutex_unlock(&graph->lock);
rc = audioreach_graph_send_cmd_sync(graph, pkt, APM_CMD_RSP_SHARED_MEM_MAP_REGIONS);
kfree(pkt);
return rc;
}
EXPORT_SYMBOL_GPL(audioreach_map_memory_regions);
int audioreach_shared_memory_send_eos(struct q6apm_graph *graph)
{
struct data_cmd_wr_sh_mem_ep_eos *eos;
struct gpr_pkt *pkt;
int rc = 0, iid;
iid = q6apm_graph_get_rx_shmem_module_iid(graph);
pkt = audioreach_alloc_cmd_pkt(sizeof(*eos), DATA_CMD_WR_SH_MEM_EP_EOS, 0,
graph->port->id, iid);
if (IS_ERR(pkt))
return PTR_ERR(pkt);
eos = (void *)pkt + GPR_HDR_SIZE + APM_CMD_HDR_SIZE;
eos->policy = WR_SH_MEM_EP_EOS_POLICY_LAST;
rc = gpr_send_port_pkt(graph->port, pkt);
kfree(pkt);
return rc;
}
EXPORT_SYMBOL_GPL(audioreach_shared_memory_send_eos);
| linux-master | sound/soc/qcom/qdsp6/audioreach.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2021, Linaro Limited
#include <linux/init.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <linux/spinlock.h>
#include <sound/pcm.h>
#include <asm/dma.h>
#include <linux/dma-mapping.h>
#include <linux/of_device.h>
#include <sound/pcm_params.h>
#include "q6apm.h"
#define DRV_NAME "q6apm-dai"
#define PLAYBACK_MIN_NUM_PERIODS 2
#define PLAYBACK_MAX_NUM_PERIODS 8
#define PLAYBACK_MAX_PERIOD_SIZE 65536
#define PLAYBACK_MIN_PERIOD_SIZE 128
#define CAPTURE_MIN_NUM_PERIODS 2
#define CAPTURE_MAX_NUM_PERIODS 8
#define CAPTURE_MAX_PERIOD_SIZE 4096
#define CAPTURE_MIN_PERIOD_SIZE 320
#define BUFFER_BYTES_MAX (PLAYBACK_MAX_NUM_PERIODS * PLAYBACK_MAX_PERIOD_SIZE)
#define BUFFER_BYTES_MIN (PLAYBACK_MIN_NUM_PERIODS * PLAYBACK_MIN_PERIOD_SIZE)
#define COMPR_PLAYBACK_MAX_FRAGMENT_SIZE (128 * 1024)
#define COMPR_PLAYBACK_MAX_NUM_FRAGMENTS (16 * 4)
#define COMPR_PLAYBACK_MIN_FRAGMENT_SIZE (8 * 1024)
#define COMPR_PLAYBACK_MIN_NUM_FRAGMENTS (4)
#define SID_MASK_DEFAULT 0xF
static const struct snd_compr_codec_caps q6apm_compr_caps = {
.num_descriptors = 1,
.descriptor[0].max_ch = 2,
.descriptor[0].sample_rates = { 8000, 11025, 12000, 16000, 22050,
24000, 32000, 44100, 48000, 88200,
96000, 176400, 192000 },
.descriptor[0].num_sample_rates = 13,
.descriptor[0].bit_rate[0] = 320,
.descriptor[0].bit_rate[1] = 128,
.descriptor[0].num_bitrates = 2,
.descriptor[0].profiles = 0,
.descriptor[0].modes = SND_AUDIOCHANMODE_MP3_STEREO,
.descriptor[0].formats = 0,
};
enum stream_state {
Q6APM_STREAM_IDLE = 0,
Q6APM_STREAM_STOPPED,
Q6APM_STREAM_RUNNING,
};
struct q6apm_dai_rtd {
struct snd_pcm_substream *substream;
struct snd_compr_stream *cstream;
struct snd_codec codec;
struct snd_compr_params codec_param;
struct snd_dma_buffer dma_buffer;
phys_addr_t phys;
unsigned int pcm_size;
unsigned int pcm_count;
unsigned int pos; /* Buffer position */
unsigned int periods;
unsigned int bytes_sent;
unsigned int bytes_received;
unsigned int copied_total;
uint16_t bits_per_sample;
uint16_t source; /* Encoding source bit mask */
uint16_t session_id;
bool next_track;
enum stream_state state;
struct q6apm_graph *graph;
spinlock_t lock;
uint32_t initial_samples_drop;
uint32_t trailing_samples_drop;
bool notify_on_drain;
};
struct q6apm_dai_data {
long long sid;
};
static struct snd_pcm_hardware q6apm_dai_hardware_capture = {
.info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_BLOCK_TRANSFER |
SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME |
SNDRV_PCM_INFO_BATCH),
.formats = (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE),
.rates = SNDRV_PCM_RATE_8000_48000,
.rate_min = 8000,
.rate_max = 48000,
.channels_min = 2,
.channels_max = 4,
.buffer_bytes_max = CAPTURE_MAX_NUM_PERIODS * CAPTURE_MAX_PERIOD_SIZE,
.period_bytes_min = CAPTURE_MIN_PERIOD_SIZE,
.period_bytes_max = CAPTURE_MAX_PERIOD_SIZE,
.periods_min = CAPTURE_MIN_NUM_PERIODS,
.periods_max = CAPTURE_MAX_NUM_PERIODS,
.fifo_size = 0,
};
static struct snd_pcm_hardware q6apm_dai_hardware_playback = {
.info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_BLOCK_TRANSFER |
SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME |
SNDRV_PCM_INFO_BATCH),
.formats = (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE),
.rates = SNDRV_PCM_RATE_8000_192000,
.rate_min = 8000,
.rate_max = 192000,
.channels_min = 2,
.channels_max = 8,
.buffer_bytes_max = (PLAYBACK_MAX_NUM_PERIODS * PLAYBACK_MAX_PERIOD_SIZE),
.period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE,
.period_bytes_max = PLAYBACK_MAX_PERIOD_SIZE,
.periods_min = PLAYBACK_MIN_NUM_PERIODS,
.periods_max = PLAYBACK_MAX_NUM_PERIODS,
.fifo_size = 0,
};
static void event_handler(uint32_t opcode, uint32_t token, uint32_t *payload, void *priv)
{
struct q6apm_dai_rtd *prtd = priv;
struct snd_pcm_substream *substream = prtd->substream;
unsigned long flags;
switch (opcode) {
case APM_CLIENT_EVENT_CMD_EOS_DONE:
prtd->state = Q6APM_STREAM_STOPPED;
break;
case APM_CLIENT_EVENT_DATA_WRITE_DONE:
spin_lock_irqsave(&prtd->lock, flags);
prtd->pos += prtd->pcm_count;
spin_unlock_irqrestore(&prtd->lock, flags);
snd_pcm_period_elapsed(substream);
if (prtd->state == Q6APM_STREAM_RUNNING)
q6apm_write_async(prtd->graph, prtd->pcm_count, 0, 0, 0);
break;
case APM_CLIENT_EVENT_DATA_READ_DONE:
spin_lock_irqsave(&prtd->lock, flags);
prtd->pos += prtd->pcm_count;
spin_unlock_irqrestore(&prtd->lock, flags);
snd_pcm_period_elapsed(substream);
if (prtd->state == Q6APM_STREAM_RUNNING)
q6apm_read(prtd->graph);
break;
default:
break;
}
}
static void event_handler_compr(uint32_t opcode, uint32_t token,
uint32_t *payload, void *priv)
{
struct q6apm_dai_rtd *prtd = priv;
struct snd_compr_stream *substream = prtd->cstream;
unsigned long flags;
uint32_t wflags = 0;
uint64_t avail;
uint32_t bytes_written, bytes_to_write;
bool is_last_buffer = false;
switch (opcode) {
case APM_CLIENT_EVENT_CMD_EOS_DONE:
spin_lock_irqsave(&prtd->lock, flags);
if (prtd->notify_on_drain) {
snd_compr_drain_notify(prtd->cstream);
prtd->notify_on_drain = false;
} else {
prtd->state = Q6APM_STREAM_STOPPED;
}
spin_unlock_irqrestore(&prtd->lock, flags);
break;
case APM_CLIENT_EVENT_DATA_WRITE_DONE:
spin_lock_irqsave(&prtd->lock, flags);
bytes_written = token >> APM_WRITE_TOKEN_LEN_SHIFT;
prtd->copied_total += bytes_written;
snd_compr_fragment_elapsed(substream);
if (prtd->state != Q6APM_STREAM_RUNNING) {
spin_unlock_irqrestore(&prtd->lock, flags);
break;
}
avail = prtd->bytes_received - prtd->bytes_sent;
if (avail > prtd->pcm_count) {
bytes_to_write = prtd->pcm_count;
} else {
if (substream->partial_drain || prtd->notify_on_drain)
is_last_buffer = true;
bytes_to_write = avail;
}
if (bytes_to_write) {
if (substream->partial_drain && is_last_buffer)
wflags |= APM_LAST_BUFFER_FLAG;
q6apm_write_async(prtd->graph,
bytes_to_write, 0, 0, wflags);
prtd->bytes_sent += bytes_to_write;
if (prtd->notify_on_drain && is_last_buffer)
audioreach_shared_memory_send_eos(prtd->graph);
}
spin_unlock_irqrestore(&prtd->lock, flags);
break;
default:
break;
}
}
static int q6apm_dai_prepare(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct q6apm_dai_rtd *prtd = runtime->private_data;
struct audioreach_module_config cfg;
struct device *dev = component->dev;
struct q6apm_dai_data *pdata;
int ret;
pdata = snd_soc_component_get_drvdata(component);
if (!pdata)
return -EINVAL;
if (!prtd || !prtd->graph) {
dev_err(dev, "%s: private data null or audio client freed\n", __func__);
return -EINVAL;
}
cfg.direction = substream->stream;
cfg.sample_rate = runtime->rate;
cfg.num_channels = runtime->channels;
cfg.bit_width = prtd->bits_per_sample;
cfg.fmt = SND_AUDIOCODEC_PCM;
if (prtd->state) {
/* clear the previous setup if any */
q6apm_graph_stop(prtd->graph);
q6apm_unmap_memory_regions(prtd->graph, substream->stream);
}
prtd->pcm_count = snd_pcm_lib_period_bytes(substream);
prtd->pos = 0;
/* rate and channels are sent to audio driver */
ret = q6apm_graph_media_format_shmem(prtd->graph, &cfg);
if (ret < 0) {
dev_err(dev, "%s: q6apm_open_write failed\n", __func__);
return ret;
}
ret = q6apm_graph_media_format_pcm(prtd->graph, &cfg);
if (ret < 0)
dev_err(dev, "%s: CMD Format block failed\n", __func__);
ret = q6apm_map_memory_regions(prtd->graph, substream->stream, prtd->phys,
(prtd->pcm_size / prtd->periods), prtd->periods);
if (ret < 0) {
dev_err(dev, "Audio Start: Buffer Allocation failed rc = %d\n", ret);
return -ENOMEM;
}
ret = q6apm_graph_prepare(prtd->graph);
if (ret) {
dev_err(dev, "Failed to prepare Graph %d\n", ret);
return ret;
}
ret = q6apm_graph_start(prtd->graph);
if (ret) {
dev_err(dev, "Failed to Start Graph %d\n", ret);
return ret;
}
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
int i;
/* Queue the buffers for Capture ONLY after graph is started */
for (i = 0; i < runtime->periods; i++)
q6apm_read(prtd->graph);
}
/* Now that graph as been prepared and started update the internal state accordingly */
prtd->state = Q6APM_STREAM_RUNNING;
return 0;
}
static int q6apm_dai_trigger(struct snd_soc_component *component,
struct snd_pcm_substream *substream, int cmd)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct q6apm_dai_rtd *prtd = runtime->private_data;
int ret = 0;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
/* start writing buffers for playback only as we already queued capture buffers */
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
ret = q6apm_write_async(prtd->graph, prtd->pcm_count, 0, 0, 0);
break;
case SNDRV_PCM_TRIGGER_STOP:
/* TODO support be handled via SoftPause Module */
prtd->state = Q6APM_STREAM_STOPPED;
break;
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
static int q6apm_dai_open(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_pcm_runtime *soc_prtd = substream->private_data;
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_prtd, 0);
struct device *dev = component->dev;
struct q6apm_dai_data *pdata;
struct q6apm_dai_rtd *prtd;
int graph_id, ret;
graph_id = cpu_dai->driver->id;
pdata = snd_soc_component_get_drvdata(component);
if (!pdata) {
dev_err(dev, "Drv data not found ..\n");
return -EINVAL;
}
prtd = kzalloc(sizeof(*prtd), GFP_KERNEL);
if (prtd == NULL)
return -ENOMEM;
spin_lock_init(&prtd->lock);
prtd->substream = substream;
prtd->graph = q6apm_graph_open(dev, (q6apm_cb)event_handler, prtd, graph_id);
if (IS_ERR(prtd->graph)) {
dev_err(dev, "%s: Could not allocate memory\n", __func__);
ret = PTR_ERR(prtd->graph);
goto err;
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
runtime->hw = q6apm_dai_hardware_playback;
else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
runtime->hw = q6apm_dai_hardware_capture;
/* Ensure that buffer size is a multiple of period size */
ret = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
if (ret < 0) {
dev_err(dev, "snd_pcm_hw_constraint_integer failed\n");
goto err;
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
ret = snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
BUFFER_BYTES_MIN, BUFFER_BYTES_MAX);
if (ret < 0) {
dev_err(dev, "constraint for buffer bytes min max ret = %d\n", ret);
goto err;
}
}
ret = snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 32);
if (ret < 0) {
dev_err(dev, "constraint for period bytes step ret = %d\n", ret);
goto err;
}
ret = snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 32);
if (ret < 0) {
dev_err(dev, "constraint for buffer bytes step ret = %d\n", ret);
goto err;
}
runtime->private_data = prtd;
runtime->dma_bytes = BUFFER_BYTES_MAX;
if (pdata->sid < 0)
prtd->phys = substream->dma_buffer.addr;
else
prtd->phys = substream->dma_buffer.addr | (pdata->sid << 32);
return 0;
err:
kfree(prtd);
return ret;
}
static int q6apm_dai_close(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct q6apm_dai_rtd *prtd = runtime->private_data;
if (prtd->state) { /* only stop graph that is started */
q6apm_graph_stop(prtd->graph);
q6apm_unmap_memory_regions(prtd->graph, substream->stream);
}
q6apm_graph_close(prtd->graph);
prtd->graph = NULL;
kfree(prtd);
runtime->private_data = NULL;
return 0;
}
static snd_pcm_uframes_t q6apm_dai_pointer(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct q6apm_dai_rtd *prtd = runtime->private_data;
snd_pcm_uframes_t ptr;
unsigned long flags;
spin_lock_irqsave(&prtd->lock, flags);
if (prtd->pos == prtd->pcm_size)
prtd->pos = 0;
ptr = bytes_to_frames(runtime, prtd->pos);
spin_unlock_irqrestore(&prtd->lock, flags);
return ptr;
}
static int q6apm_dai_hw_params(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct q6apm_dai_rtd *prtd = runtime->private_data;
prtd->pcm_size = params_buffer_bytes(params);
prtd->periods = params_periods(params);
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
prtd->bits_per_sample = 16;
break;
case SNDRV_PCM_FORMAT_S24_LE:
prtd->bits_per_sample = 24;
break;
default:
return -EINVAL;
}
return 0;
}
static int q6apm_dai_pcm_new(struct snd_soc_component *component, struct snd_soc_pcm_runtime *rtd)
{
int size = BUFFER_BYTES_MAX;
return snd_pcm_set_fixed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV, component->dev, size);
}
static int q6apm_dai_compr_open(struct snd_soc_component *component,
struct snd_compr_stream *stream)
{
struct snd_soc_pcm_runtime *rtd = stream->private_data;
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct snd_compr_runtime *runtime = stream->runtime;
struct q6apm_dai_rtd *prtd;
struct q6apm_dai_data *pdata;
struct device *dev = component->dev;
int ret, size;
int graph_id;
graph_id = cpu_dai->driver->id;
pdata = snd_soc_component_get_drvdata(component);
if (!pdata)
return -EINVAL;
prtd = kzalloc(sizeof(*prtd), GFP_KERNEL);
if (prtd == NULL)
return -ENOMEM;
prtd->cstream = stream;
prtd->graph = q6apm_graph_open(dev, (q6apm_cb)event_handler_compr, prtd, graph_id);
if (IS_ERR(prtd->graph)) {
ret = PTR_ERR(prtd->graph);
kfree(prtd);
return ret;
}
runtime->private_data = prtd;
runtime->dma_bytes = BUFFER_BYTES_MAX;
size = COMPR_PLAYBACK_MAX_FRAGMENT_SIZE * COMPR_PLAYBACK_MAX_NUM_FRAGMENTS;
ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, dev, size, &prtd->dma_buffer);
if (ret)
return ret;
if (pdata->sid < 0)
prtd->phys = prtd->dma_buffer.addr;
else
prtd->phys = prtd->dma_buffer.addr | (pdata->sid << 32);
snd_compr_set_runtime_buffer(stream, &prtd->dma_buffer);
spin_lock_init(&prtd->lock);
q6apm_enable_compress_module(dev, prtd->graph, true);
return 0;
}
static int q6apm_dai_compr_free(struct snd_soc_component *component,
struct snd_compr_stream *stream)
{
struct snd_compr_runtime *runtime = stream->runtime;
struct q6apm_dai_rtd *prtd = runtime->private_data;
q6apm_graph_stop(prtd->graph);
q6apm_unmap_memory_regions(prtd->graph, SNDRV_PCM_STREAM_PLAYBACK);
q6apm_graph_close(prtd->graph);
snd_dma_free_pages(&prtd->dma_buffer);
prtd->graph = NULL;
kfree(prtd);
runtime->private_data = NULL;
return 0;
}
static int q6apm_dai_compr_get_caps(struct snd_soc_component *component,
struct snd_compr_stream *stream,
struct snd_compr_caps *caps)
{
caps->direction = SND_COMPRESS_PLAYBACK;
caps->min_fragment_size = COMPR_PLAYBACK_MIN_FRAGMENT_SIZE;
caps->max_fragment_size = COMPR_PLAYBACK_MAX_FRAGMENT_SIZE;
caps->min_fragments = COMPR_PLAYBACK_MIN_NUM_FRAGMENTS;
caps->max_fragments = COMPR_PLAYBACK_MAX_NUM_FRAGMENTS;
caps->num_codecs = 3;
caps->codecs[0] = SND_AUDIOCODEC_MP3;
caps->codecs[1] = SND_AUDIOCODEC_AAC;
caps->codecs[2] = SND_AUDIOCODEC_FLAC;
return 0;
}
static int q6apm_dai_compr_get_codec_caps(struct snd_soc_component *component,
struct snd_compr_stream *stream,
struct snd_compr_codec_caps *codec)
{
switch (codec->codec) {
case SND_AUDIOCODEC_MP3:
*codec = q6apm_compr_caps;
break;
default:
break;
}
return 0;
}
static int q6apm_dai_compr_pointer(struct snd_soc_component *component,
struct snd_compr_stream *stream,
struct snd_compr_tstamp *tstamp)
{
struct snd_compr_runtime *runtime = stream->runtime;
struct q6apm_dai_rtd *prtd = runtime->private_data;
unsigned long flags;
spin_lock_irqsave(&prtd->lock, flags);
tstamp->copied_total = prtd->copied_total;
tstamp->byte_offset = prtd->copied_total % prtd->pcm_size;
spin_unlock_irqrestore(&prtd->lock, flags);
return 0;
}
static int q6apm_dai_compr_trigger(struct snd_soc_component *component,
struct snd_compr_stream *stream, int cmd)
{
struct snd_compr_runtime *runtime = stream->runtime;
struct q6apm_dai_rtd *prtd = runtime->private_data;
int ret = 0;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
ret = q6apm_write_async(prtd->graph, prtd->pcm_count, 0, 0, NO_TIMESTAMP);
break;
case SNDRV_PCM_TRIGGER_STOP:
break;
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
break;
case SND_COMPR_TRIGGER_NEXT_TRACK:
prtd->next_track = true;
break;
case SND_COMPR_TRIGGER_DRAIN:
case SND_COMPR_TRIGGER_PARTIAL_DRAIN:
prtd->notify_on_drain = true;
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
static int q6apm_dai_compr_ack(struct snd_soc_component *component, struct snd_compr_stream *stream,
size_t count)
{
struct snd_compr_runtime *runtime = stream->runtime;
struct q6apm_dai_rtd *prtd = runtime->private_data;
unsigned long flags;
spin_lock_irqsave(&prtd->lock, flags);
prtd->bytes_received += count;
spin_unlock_irqrestore(&prtd->lock, flags);
return count;
}
static int q6apm_dai_compr_set_params(struct snd_soc_component *component,
struct snd_compr_stream *stream,
struct snd_compr_params *params)
{
struct snd_compr_runtime *runtime = stream->runtime;
struct q6apm_dai_rtd *prtd = runtime->private_data;
struct q6apm_dai_data *pdata;
struct audioreach_module_config cfg;
struct snd_codec *codec = ¶ms->codec;
int dir = stream->direction;
int ret;
pdata = snd_soc_component_get_drvdata(component);
if (!pdata)
return -EINVAL;
prtd->periods = runtime->fragments;
prtd->pcm_count = runtime->fragment_size;
prtd->pcm_size = runtime->fragments * runtime->fragment_size;
prtd->bits_per_sample = 16;
prtd->pos = 0;
if (prtd->next_track != true) {
memcpy(&prtd->codec, codec, sizeof(*codec));
ret = q6apm_set_real_module_id(component->dev, prtd->graph, codec->id);
if (ret)
return ret;
cfg.direction = dir;
cfg.sample_rate = codec->sample_rate;
cfg.num_channels = 2;
cfg.bit_width = prtd->bits_per_sample;
cfg.fmt = codec->id;
memcpy(&cfg.codec, codec, sizeof(*codec));
ret = q6apm_graph_media_format_shmem(prtd->graph, &cfg);
if (ret < 0)
return ret;
ret = q6apm_graph_media_format_pcm(prtd->graph, &cfg);
if (ret)
return ret;
ret = q6apm_map_memory_regions(prtd->graph, SNDRV_PCM_STREAM_PLAYBACK,
prtd->phys, (prtd->pcm_size / prtd->periods),
prtd->periods);
if (ret < 0)
return -ENOMEM;
ret = q6apm_graph_prepare(prtd->graph);
if (ret)
return ret;
ret = q6apm_graph_start(prtd->graph);
if (ret)
return ret;
} else {
cfg.direction = dir;
cfg.sample_rate = codec->sample_rate;
cfg.num_channels = 2;
cfg.bit_width = prtd->bits_per_sample;
cfg.fmt = codec->id;
memcpy(&cfg.codec, codec, sizeof(*codec));
ret = audioreach_compr_set_param(prtd->graph, &cfg);
if (ret < 0)
return ret;
}
prtd->state = Q6APM_STREAM_RUNNING;
return 0;
}
static int q6apm_dai_compr_set_metadata(struct snd_soc_component *component,
struct snd_compr_stream *stream,
struct snd_compr_metadata *metadata)
{
struct snd_compr_runtime *runtime = stream->runtime;
struct q6apm_dai_rtd *prtd = runtime->private_data;
int ret = 0;
switch (metadata->key) {
case SNDRV_COMPRESS_ENCODER_PADDING:
prtd->trailing_samples_drop = metadata->value[0];
q6apm_remove_trailing_silence(component->dev, prtd->graph,
prtd->trailing_samples_drop);
break;
case SNDRV_COMPRESS_ENCODER_DELAY:
prtd->initial_samples_drop = metadata->value[0];
q6apm_remove_initial_silence(component->dev, prtd->graph,
prtd->initial_samples_drop);
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
static int q6apm_dai_compr_mmap(struct snd_soc_component *component,
struct snd_compr_stream *stream,
struct vm_area_struct *vma)
{
struct snd_compr_runtime *runtime = stream->runtime;
struct q6apm_dai_rtd *prtd = runtime->private_data;
struct device *dev = component->dev;
return dma_mmap_coherent(dev, vma, prtd->dma_buffer.area, prtd->dma_buffer.addr,
prtd->dma_buffer.bytes);
}
static int q6apm_compr_copy(struct snd_soc_component *component,
struct snd_compr_stream *stream, char __user *buf,
size_t count)
{
struct snd_compr_runtime *runtime = stream->runtime;
struct q6apm_dai_rtd *prtd = runtime->private_data;
void *dstn;
unsigned long flags;
size_t copy;
u32 wflags = 0;
u32 app_pointer;
u32 bytes_received;
uint32_t bytes_to_write;
int avail, bytes_in_flight = 0;
bytes_received = prtd->bytes_received;
/**
* Make sure that next track data pointer is aligned at 32 bit boundary
* This is a Mandatory requirement from DSP data buffers alignment
*/
if (prtd->next_track)
bytes_received = ALIGN(prtd->bytes_received, prtd->pcm_count);
app_pointer = bytes_received/prtd->pcm_size;
app_pointer = bytes_received - (app_pointer * prtd->pcm_size);
dstn = prtd->dma_buffer.area + app_pointer;
if (count < prtd->pcm_size - app_pointer) {
if (copy_from_user(dstn, buf, count))
return -EFAULT;
} else {
copy = prtd->pcm_size - app_pointer;
if (copy_from_user(dstn, buf, copy))
return -EFAULT;
if (copy_from_user(prtd->dma_buffer.area, buf + copy, count - copy))
return -EFAULT;
}
spin_lock_irqsave(&prtd->lock, flags);
bytes_in_flight = prtd->bytes_received - prtd->copied_total;
if (prtd->next_track) {
prtd->next_track = false;
prtd->copied_total = ALIGN(prtd->copied_total, prtd->pcm_count);
prtd->bytes_sent = ALIGN(prtd->bytes_sent, prtd->pcm_count);
}
prtd->bytes_received = bytes_received + count;
/* Kick off the data to dsp if its starving!! */
if (prtd->state == Q6APM_STREAM_RUNNING && (bytes_in_flight == 0)) {
bytes_to_write = prtd->pcm_count;
avail = prtd->bytes_received - prtd->bytes_sent;
if (avail < prtd->pcm_count)
bytes_to_write = avail;
q6apm_write_async(prtd->graph, bytes_to_write, 0, 0, wflags);
prtd->bytes_sent += bytes_to_write;
}
spin_unlock_irqrestore(&prtd->lock, flags);
return count;
}
static const struct snd_compress_ops q6apm_dai_compress_ops = {
.open = q6apm_dai_compr_open,
.free = q6apm_dai_compr_free,
.get_caps = q6apm_dai_compr_get_caps,
.get_codec_caps = q6apm_dai_compr_get_codec_caps,
.pointer = q6apm_dai_compr_pointer,
.trigger = q6apm_dai_compr_trigger,
.ack = q6apm_dai_compr_ack,
.set_params = q6apm_dai_compr_set_params,
.set_metadata = q6apm_dai_compr_set_metadata,
.mmap = q6apm_dai_compr_mmap,
.copy = q6apm_compr_copy,
};
static const struct snd_soc_component_driver q6apm_fe_dai_component = {
.name = DRV_NAME,
.open = q6apm_dai_open,
.close = q6apm_dai_close,
.prepare = q6apm_dai_prepare,
.pcm_construct = q6apm_dai_pcm_new,
.hw_params = q6apm_dai_hw_params,
.pointer = q6apm_dai_pointer,
.trigger = q6apm_dai_trigger,
.compress_ops = &q6apm_dai_compress_ops,
.use_dai_pcm_id = true,
};
static int q6apm_dai_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *node = dev->of_node;
struct q6apm_dai_data *pdata;
struct of_phandle_args args;
int rc;
pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
if (!pdata)
return -ENOMEM;
rc = of_parse_phandle_with_fixed_args(node, "iommus", 1, 0, &args);
if (rc < 0)
pdata->sid = -1;
else
pdata->sid = args.args[0] & SID_MASK_DEFAULT;
dev_set_drvdata(dev, pdata);
return devm_snd_soc_register_component(dev, &q6apm_fe_dai_component, NULL, 0);
}
#ifdef CONFIG_OF
static const struct of_device_id q6apm_dai_device_id[] = {
{ .compatible = "qcom,q6apm-dais" },
{},
};
MODULE_DEVICE_TABLE(of, q6apm_dai_device_id);
#endif
static struct platform_driver q6apm_dai_platform_driver = {
.driver = {
.name = "q6apm-dai",
.of_match_table = of_match_ptr(q6apm_dai_device_id),
},
.probe = q6apm_dai_probe,
};
module_platform_driver(q6apm_dai_platform_driver);
MODULE_DESCRIPTION("Q6APM dai driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/qcom/qdsp6/q6apm-dai.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2011-2017, The Linux Foundation. All rights reserved.
// Copyright (c) 2018, Linaro Limited
#include <linux/slab.h>
#include <linux/kernel.h>
#include <linux/uaccess.h>
#include <linux/wait.h>
#include <linux/jiffies.h>
#include <linux/sched.h>
#include <linux/module.h>
#include <linux/kref.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/spinlock.h>
#include <linux/delay.h>
#include <linux/soc/qcom/apr.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include "q6dsp-errno.h"
#include "q6core.h"
#include "q6afe.h"
/* AFE CMDs */
#define AFE_PORT_CMD_DEVICE_START 0x000100E5
#define AFE_PORT_CMD_DEVICE_STOP 0x000100E6
#define AFE_PORT_CMD_SET_PARAM_V2 0x000100EF
#define AFE_SVC_CMD_SET_PARAM 0x000100f3
#define AFE_PORT_CMDRSP_GET_PARAM_V2 0x00010106
#define AFE_PARAM_ID_HDMI_CONFIG 0x00010210
#define AFE_MODULE_AUDIO_DEV_INTERFACE 0x0001020C
#define AFE_MODULE_TDM 0x0001028A
#define AFE_PARAM_ID_CDC_SLIMBUS_SLAVE_CFG 0x00010235
#define AFE_PARAM_ID_LPAIF_CLK_CONFIG 0x00010238
#define AFE_PARAM_ID_INT_DIGITAL_CDC_CLK_CONFIG 0x00010239
#define AFE_PARAM_ID_SLIMBUS_CONFIG 0x00010212
#define AFE_PARAM_ID_I2S_CONFIG 0x0001020D
#define AFE_PARAM_ID_TDM_CONFIG 0x0001029D
#define AFE_PARAM_ID_PORT_SLOT_MAPPING_CONFIG 0x00010297
#define AFE_PARAM_ID_CODEC_DMA_CONFIG 0x000102B8
#define AFE_CMD_REMOTE_LPASS_CORE_HW_VOTE_REQUEST 0x000100f4
#define AFE_CMD_RSP_REMOTE_LPASS_CORE_HW_VOTE_REQUEST 0x000100f5
#define AFE_CMD_REMOTE_LPASS_CORE_HW_DEVOTE_REQUEST 0x000100f6
/* I2S config specific */
#define AFE_API_VERSION_I2S_CONFIG 0x1
#define AFE_PORT_I2S_SD0 0x1
#define AFE_PORT_I2S_SD1 0x2
#define AFE_PORT_I2S_SD2 0x3
#define AFE_PORT_I2S_SD3 0x4
#define AFE_PORT_I2S_SD0_MASK BIT(0x0)
#define AFE_PORT_I2S_SD1_MASK BIT(0x1)
#define AFE_PORT_I2S_SD2_MASK BIT(0x2)
#define AFE_PORT_I2S_SD3_MASK BIT(0x3)
#define AFE_PORT_I2S_SD0_1_MASK GENMASK(1, 0)
#define AFE_PORT_I2S_SD2_3_MASK GENMASK(3, 2)
#define AFE_PORT_I2S_SD0_1_2_MASK GENMASK(2, 0)
#define AFE_PORT_I2S_SD0_1_2_3_MASK GENMASK(3, 0)
#define AFE_PORT_I2S_QUAD01 0x5
#define AFE_PORT_I2S_QUAD23 0x6
#define AFE_PORT_I2S_6CHS 0x7
#define AFE_PORT_I2S_8CHS 0x8
#define AFE_PORT_I2S_MONO 0x0
#define AFE_PORT_I2S_STEREO 0x1
#define AFE_PORT_CONFIG_I2S_WS_SRC_EXTERNAL 0x0
#define AFE_PORT_CONFIG_I2S_WS_SRC_INTERNAL 0x1
#define AFE_LINEAR_PCM_DATA 0x0
/* Port IDs */
#define AFE_API_VERSION_HDMI_CONFIG 0x1
#define AFE_PORT_ID_MULTICHAN_HDMI_RX 0x100E
#define AFE_PORT_ID_HDMI_OVER_DP_RX 0x6020
#define AFE_API_VERSION_SLIMBUS_CONFIG 0x1
/* Clock set API version */
#define AFE_API_VERSION_CLOCK_SET 1
#define Q6AFE_LPASS_CLK_CONFIG_API_VERSION 0x1
#define AFE_MODULE_CLOCK_SET 0x0001028F
#define AFE_PARAM_ID_CLOCK_SET 0x00010290
/* SLIMbus Rx port on channel 0. */
#define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_RX 0x4000
/* SLIMbus Tx port on channel 0. */
#define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_TX 0x4001
/* SLIMbus Rx port on channel 1. */
#define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_RX 0x4002
/* SLIMbus Tx port on channel 1. */
#define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_TX 0x4003
/* SLIMbus Rx port on channel 2. */
#define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_RX 0x4004
/* SLIMbus Tx port on channel 2. */
#define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_TX 0x4005
/* SLIMbus Rx port on channel 3. */
#define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_RX 0x4006
/* SLIMbus Tx port on channel 3. */
#define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_TX 0x4007
/* SLIMbus Rx port on channel 4. */
#define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_RX 0x4008
/* SLIMbus Tx port on channel 4. */
#define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_TX 0x4009
/* SLIMbus Rx port on channel 5. */
#define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_RX 0x400a
/* SLIMbus Tx port on channel 5. */
#define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_TX 0x400b
/* SLIMbus Rx port on channel 6. */
#define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_RX 0x400c
/* SLIMbus Tx port on channel 6. */
#define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_TX 0x400d
#define AFE_PORT_ID_PRIMARY_MI2S_RX 0x1000
#define AFE_PORT_ID_PRIMARY_MI2S_TX 0x1001
#define AFE_PORT_ID_SECONDARY_MI2S_RX 0x1002
#define AFE_PORT_ID_SECONDARY_MI2S_TX 0x1003
#define AFE_PORT_ID_TERTIARY_MI2S_RX 0x1004
#define AFE_PORT_ID_TERTIARY_MI2S_TX 0x1005
#define AFE_PORT_ID_QUATERNARY_MI2S_RX 0x1006
#define AFE_PORT_ID_QUATERNARY_MI2S_TX 0x1007
#define AFE_PORT_ID_QUINARY_MI2S_RX 0x1016
#define AFE_PORT_ID_QUINARY_MI2S_TX 0x1017
/* Start of the range of port IDs for TDM devices. */
#define AFE_PORT_ID_TDM_PORT_RANGE_START 0x9000
/* End of the range of port IDs for TDM devices. */
#define AFE_PORT_ID_TDM_PORT_RANGE_END \
(AFE_PORT_ID_TDM_PORT_RANGE_START+0x50-1)
/* Size of the range of port IDs for TDM ports. */
#define AFE_PORT_ID_TDM_PORT_RANGE_SIZE \
(AFE_PORT_ID_TDM_PORT_RANGE_END - \
AFE_PORT_ID_TDM_PORT_RANGE_START+1)
#define AFE_PORT_ID_PRIMARY_TDM_RX \
(AFE_PORT_ID_TDM_PORT_RANGE_START + 0x00)
#define AFE_PORT_ID_PRIMARY_TDM_RX_1 \
(AFE_PORT_ID_PRIMARY_TDM_RX + 0x02)
#define AFE_PORT_ID_PRIMARY_TDM_RX_2 \
(AFE_PORT_ID_PRIMARY_TDM_RX + 0x04)
#define AFE_PORT_ID_PRIMARY_TDM_RX_3 \
(AFE_PORT_ID_PRIMARY_TDM_RX + 0x06)
#define AFE_PORT_ID_PRIMARY_TDM_RX_4 \
(AFE_PORT_ID_PRIMARY_TDM_RX + 0x08)
#define AFE_PORT_ID_PRIMARY_TDM_RX_5 \
(AFE_PORT_ID_PRIMARY_TDM_RX + 0x0A)
#define AFE_PORT_ID_PRIMARY_TDM_RX_6 \
(AFE_PORT_ID_PRIMARY_TDM_RX + 0x0C)
#define AFE_PORT_ID_PRIMARY_TDM_RX_7 \
(AFE_PORT_ID_PRIMARY_TDM_RX + 0x0E)
#define AFE_PORT_ID_PRIMARY_TDM_TX \
(AFE_PORT_ID_TDM_PORT_RANGE_START + 0x01)
#define AFE_PORT_ID_PRIMARY_TDM_TX_1 \
(AFE_PORT_ID_PRIMARY_TDM_TX + 0x02)
#define AFE_PORT_ID_PRIMARY_TDM_TX_2 \
(AFE_PORT_ID_PRIMARY_TDM_TX + 0x04)
#define AFE_PORT_ID_PRIMARY_TDM_TX_3 \
(AFE_PORT_ID_PRIMARY_TDM_TX + 0x06)
#define AFE_PORT_ID_PRIMARY_TDM_TX_4 \
(AFE_PORT_ID_PRIMARY_TDM_TX + 0x08)
#define AFE_PORT_ID_PRIMARY_TDM_TX_5 \
(AFE_PORT_ID_PRIMARY_TDM_TX + 0x0A)
#define AFE_PORT_ID_PRIMARY_TDM_TX_6 \
(AFE_PORT_ID_PRIMARY_TDM_TX + 0x0C)
#define AFE_PORT_ID_PRIMARY_TDM_TX_7 \
(AFE_PORT_ID_PRIMARY_TDM_TX + 0x0E)
#define AFE_PORT_ID_SECONDARY_TDM_RX \
(AFE_PORT_ID_TDM_PORT_RANGE_START + 0x10)
#define AFE_PORT_ID_SECONDARY_TDM_RX_1 \
(AFE_PORT_ID_SECONDARY_TDM_RX + 0x02)
#define AFE_PORT_ID_SECONDARY_TDM_RX_2 \
(AFE_PORT_ID_SECONDARY_TDM_RX + 0x04)
#define AFE_PORT_ID_SECONDARY_TDM_RX_3 \
(AFE_PORT_ID_SECONDARY_TDM_RX + 0x06)
#define AFE_PORT_ID_SECONDARY_TDM_RX_4 \
(AFE_PORT_ID_SECONDARY_TDM_RX + 0x08)
#define AFE_PORT_ID_SECONDARY_TDM_RX_5 \
(AFE_PORT_ID_SECONDARY_TDM_RX + 0x0A)
#define AFE_PORT_ID_SECONDARY_TDM_RX_6 \
(AFE_PORT_ID_SECONDARY_TDM_RX + 0x0C)
#define AFE_PORT_ID_SECONDARY_TDM_RX_7 \
(AFE_PORT_ID_SECONDARY_TDM_RX + 0x0E)
#define AFE_PORT_ID_SECONDARY_TDM_TX \
(AFE_PORT_ID_TDM_PORT_RANGE_START + 0x11)
#define AFE_PORT_ID_SECONDARY_TDM_TX_1 \
(AFE_PORT_ID_SECONDARY_TDM_TX + 0x02)
#define AFE_PORT_ID_SECONDARY_TDM_TX_2 \
(AFE_PORT_ID_SECONDARY_TDM_TX + 0x04)
#define AFE_PORT_ID_SECONDARY_TDM_TX_3 \
(AFE_PORT_ID_SECONDARY_TDM_TX + 0x06)
#define AFE_PORT_ID_SECONDARY_TDM_TX_4 \
(AFE_PORT_ID_SECONDARY_TDM_TX + 0x08)
#define AFE_PORT_ID_SECONDARY_TDM_TX_5 \
(AFE_PORT_ID_SECONDARY_TDM_TX + 0x0A)
#define AFE_PORT_ID_SECONDARY_TDM_TX_6 \
(AFE_PORT_ID_SECONDARY_TDM_TX + 0x0C)
#define AFE_PORT_ID_SECONDARY_TDM_TX_7 \
(AFE_PORT_ID_SECONDARY_TDM_TX + 0x0E)
#define AFE_PORT_ID_TERTIARY_TDM_RX \
(AFE_PORT_ID_TDM_PORT_RANGE_START + 0x20)
#define AFE_PORT_ID_TERTIARY_TDM_RX_1 \
(AFE_PORT_ID_TERTIARY_TDM_RX + 0x02)
#define AFE_PORT_ID_TERTIARY_TDM_RX_2 \
(AFE_PORT_ID_TERTIARY_TDM_RX + 0x04)
#define AFE_PORT_ID_TERTIARY_TDM_RX_3 \
(AFE_PORT_ID_TERTIARY_TDM_RX + 0x06)
#define AFE_PORT_ID_TERTIARY_TDM_RX_4 \
(AFE_PORT_ID_TERTIARY_TDM_RX + 0x08)
#define AFE_PORT_ID_TERTIARY_TDM_RX_5 \
(AFE_PORT_ID_TERTIARY_TDM_RX + 0x0A)
#define AFE_PORT_ID_TERTIARY_TDM_RX_6 \
(AFE_PORT_ID_TERTIARY_TDM_RX + 0x0C)
#define AFE_PORT_ID_TERTIARY_TDM_RX_7 \
(AFE_PORT_ID_TERTIARY_TDM_RX + 0x0E)
#define AFE_PORT_ID_TERTIARY_TDM_TX \
(AFE_PORT_ID_TDM_PORT_RANGE_START + 0x21)
#define AFE_PORT_ID_TERTIARY_TDM_TX_1 \
(AFE_PORT_ID_TERTIARY_TDM_TX + 0x02)
#define AFE_PORT_ID_TERTIARY_TDM_TX_2 \
(AFE_PORT_ID_TERTIARY_TDM_TX + 0x04)
#define AFE_PORT_ID_TERTIARY_TDM_TX_3 \
(AFE_PORT_ID_TERTIARY_TDM_TX + 0x06)
#define AFE_PORT_ID_TERTIARY_TDM_TX_4 \
(AFE_PORT_ID_TERTIARY_TDM_TX + 0x08)
#define AFE_PORT_ID_TERTIARY_TDM_TX_5 \
(AFE_PORT_ID_TERTIARY_TDM_TX + 0x0A)
#define AFE_PORT_ID_TERTIARY_TDM_TX_6 \
(AFE_PORT_ID_TERTIARY_TDM_TX + 0x0C)
#define AFE_PORT_ID_TERTIARY_TDM_TX_7 \
(AFE_PORT_ID_TERTIARY_TDM_TX + 0x0E)
#define AFE_PORT_ID_QUATERNARY_TDM_RX \
(AFE_PORT_ID_TDM_PORT_RANGE_START + 0x30)
#define AFE_PORT_ID_QUATERNARY_TDM_RX_1 \
(AFE_PORT_ID_QUATERNARY_TDM_RX + 0x02)
#define AFE_PORT_ID_QUATERNARY_TDM_RX_2 \
(AFE_PORT_ID_QUATERNARY_TDM_RX + 0x04)
#define AFE_PORT_ID_QUATERNARY_TDM_RX_3 \
(AFE_PORT_ID_QUATERNARY_TDM_RX + 0x06)
#define AFE_PORT_ID_QUATERNARY_TDM_RX_4 \
(AFE_PORT_ID_QUATERNARY_TDM_RX + 0x08)
#define AFE_PORT_ID_QUATERNARY_TDM_RX_5 \
(AFE_PORT_ID_QUATERNARY_TDM_RX + 0x0A)
#define AFE_PORT_ID_QUATERNARY_TDM_RX_6 \
(AFE_PORT_ID_QUATERNARY_TDM_RX + 0x0C)
#define AFE_PORT_ID_QUATERNARY_TDM_RX_7 \
(AFE_PORT_ID_QUATERNARY_TDM_RX + 0x0E)
#define AFE_PORT_ID_QUATERNARY_TDM_TX \
(AFE_PORT_ID_TDM_PORT_RANGE_START + 0x31)
#define AFE_PORT_ID_QUATERNARY_TDM_TX_1 \
(AFE_PORT_ID_QUATERNARY_TDM_TX + 0x02)
#define AFE_PORT_ID_QUATERNARY_TDM_TX_2 \
(AFE_PORT_ID_QUATERNARY_TDM_TX + 0x04)
#define AFE_PORT_ID_QUATERNARY_TDM_TX_3 \
(AFE_PORT_ID_QUATERNARY_TDM_TX + 0x06)
#define AFE_PORT_ID_QUATERNARY_TDM_TX_4 \
(AFE_PORT_ID_QUATERNARY_TDM_TX + 0x08)
#define AFE_PORT_ID_QUATERNARY_TDM_TX_5 \
(AFE_PORT_ID_QUATERNARY_TDM_TX + 0x0A)
#define AFE_PORT_ID_QUATERNARY_TDM_TX_6 \
(AFE_PORT_ID_QUATERNARY_TDM_TX + 0x0C)
#define AFE_PORT_ID_QUATERNARY_TDM_TX_7 \
(AFE_PORT_ID_QUATERNARY_TDM_TX + 0x0E)
#define AFE_PORT_ID_QUINARY_TDM_RX \
(AFE_PORT_ID_TDM_PORT_RANGE_START + 0x40)
#define AFE_PORT_ID_QUINARY_TDM_RX_1 \
(AFE_PORT_ID_QUINARY_TDM_RX + 0x02)
#define AFE_PORT_ID_QUINARY_TDM_RX_2 \
(AFE_PORT_ID_QUINARY_TDM_RX + 0x04)
#define AFE_PORT_ID_QUINARY_TDM_RX_3 \
(AFE_PORT_ID_QUINARY_TDM_RX + 0x06)
#define AFE_PORT_ID_QUINARY_TDM_RX_4 \
(AFE_PORT_ID_QUINARY_TDM_RX + 0x08)
#define AFE_PORT_ID_QUINARY_TDM_RX_5 \
(AFE_PORT_ID_QUINARY_TDM_RX + 0x0A)
#define AFE_PORT_ID_QUINARY_TDM_RX_6 \
(AFE_PORT_ID_QUINARY_TDM_RX + 0x0C)
#define AFE_PORT_ID_QUINARY_TDM_RX_7 \
(AFE_PORT_ID_QUINARY_TDM_RX + 0x0E)
#define AFE_PORT_ID_QUINARY_TDM_TX \
(AFE_PORT_ID_TDM_PORT_RANGE_START + 0x41)
#define AFE_PORT_ID_QUINARY_TDM_TX_1 \
(AFE_PORT_ID_QUINARY_TDM_TX + 0x02)
#define AFE_PORT_ID_QUINARY_TDM_TX_2 \
(AFE_PORT_ID_QUINARY_TDM_TX + 0x04)
#define AFE_PORT_ID_QUINARY_TDM_TX_3 \
(AFE_PORT_ID_QUINARY_TDM_TX + 0x06)
#define AFE_PORT_ID_QUINARY_TDM_TX_4 \
(AFE_PORT_ID_QUINARY_TDM_TX + 0x08)
#define AFE_PORT_ID_QUINARY_TDM_TX_5 \
(AFE_PORT_ID_QUINARY_TDM_TX + 0x0A)
#define AFE_PORT_ID_QUINARY_TDM_TX_6 \
(AFE_PORT_ID_QUINARY_TDM_TX + 0x0C)
#define AFE_PORT_ID_QUINARY_TDM_TX_7 \
(AFE_PORT_ID_QUINARY_TDM_TX + 0x0E)
/* AFE WSA Codec DMA Rx port 0 */
#define AFE_PORT_ID_WSA_CODEC_DMA_RX_0 0xB000
/* AFE WSA Codec DMA Tx port 0 */
#define AFE_PORT_ID_WSA_CODEC_DMA_TX_0 0xB001
/* AFE WSA Codec DMA Rx port 1 */
#define AFE_PORT_ID_WSA_CODEC_DMA_RX_1 0xB002
/* AFE WSA Codec DMA Tx port 1 */
#define AFE_PORT_ID_WSA_CODEC_DMA_TX_1 0xB003
/* AFE WSA Codec DMA Tx port 2 */
#define AFE_PORT_ID_WSA_CODEC_DMA_TX_2 0xB005
/* AFE VA Codec DMA Tx port 0 */
#define AFE_PORT_ID_VA_CODEC_DMA_TX_0 0xB021
/* AFE VA Codec DMA Tx port 1 */
#define AFE_PORT_ID_VA_CODEC_DMA_TX_1 0xB023
/* AFE VA Codec DMA Tx port 2 */
#define AFE_PORT_ID_VA_CODEC_DMA_TX_2 0xB025
/* AFE Rx Codec DMA Rx port 0 */
#define AFE_PORT_ID_RX_CODEC_DMA_RX_0 0xB030
/* AFE Tx Codec DMA Tx port 0 */
#define AFE_PORT_ID_TX_CODEC_DMA_TX_0 0xB031
/* AFE Rx Codec DMA Rx port 1 */
#define AFE_PORT_ID_RX_CODEC_DMA_RX_1 0xB032
/* AFE Tx Codec DMA Tx port 1 */
#define AFE_PORT_ID_TX_CODEC_DMA_TX_1 0xB033
/* AFE Rx Codec DMA Rx port 2 */
#define AFE_PORT_ID_RX_CODEC_DMA_RX_2 0xB034
/* AFE Tx Codec DMA Tx port 2 */
#define AFE_PORT_ID_TX_CODEC_DMA_TX_2 0xB035
/* AFE Rx Codec DMA Rx port 3 */
#define AFE_PORT_ID_RX_CODEC_DMA_RX_3 0xB036
/* AFE Tx Codec DMA Tx port 3 */
#define AFE_PORT_ID_TX_CODEC_DMA_TX_3 0xB037
/* AFE Rx Codec DMA Rx port 4 */
#define AFE_PORT_ID_RX_CODEC_DMA_RX_4 0xB038
/* AFE Tx Codec DMA Tx port 4 */
#define AFE_PORT_ID_TX_CODEC_DMA_TX_4 0xB039
/* AFE Rx Codec DMA Rx port 5 */
#define AFE_PORT_ID_RX_CODEC_DMA_RX_5 0xB03A
/* AFE Tx Codec DMA Tx port 5 */
#define AFE_PORT_ID_TX_CODEC_DMA_TX_5 0xB03B
/* AFE Rx Codec DMA Rx port 6 */
#define AFE_PORT_ID_RX_CODEC_DMA_RX_6 0xB03C
/* AFE Rx Codec DMA Rx port 7 */
#define AFE_PORT_ID_RX_CODEC_DMA_RX_7 0xB03E
#define Q6AFE_LPASS_MODE_CLK1_VALID 1
#define Q6AFE_LPASS_MODE_CLK2_VALID 2
#define Q6AFE_LPASS_CLK_SRC_INTERNAL 1
#define Q6AFE_LPASS_CLK_ROOT_DEFAULT 0
#define AFE_API_VERSION_TDM_CONFIG 1
#define AFE_API_VERSION_SLOT_MAPPING_CONFIG 1
#define AFE_API_VERSION_CODEC_DMA_CONFIG 1
#define TIMEOUT_MS 1000
#define AFE_CMD_RESP_AVAIL 0
#define AFE_CMD_RESP_NONE 1
#define AFE_CLK_TOKEN 1024
struct q6afe {
struct apr_device *apr;
struct device *dev;
struct q6core_svc_api_info ainfo;
struct mutex lock;
struct aprv2_ibasic_rsp_result_t result;
wait_queue_head_t wait;
struct list_head port_list;
spinlock_t port_list_lock;
};
struct afe_port_cmd_device_start {
u16 port_id;
u16 reserved;
} __packed;
struct afe_port_cmd_device_stop {
u16 port_id;
u16 reserved;
/* Reserved for 32-bit alignment. This field must be set to 0.*/
} __packed;
struct afe_port_param_data_v2 {
u32 module_id;
u32 param_id;
u16 param_size;
u16 reserved;
} __packed;
struct afe_svc_cmd_set_param {
uint32_t payload_size;
uint32_t payload_address_lsw;
uint32_t payload_address_msw;
uint32_t mem_map_handle;
} __packed;
struct afe_port_cmd_set_param_v2 {
u16 port_id;
u16 payload_size;
u32 payload_address_lsw;
u32 payload_address_msw;
u32 mem_map_handle;
} __packed;
struct afe_param_id_hdmi_multi_chan_audio_cfg {
u32 hdmi_cfg_minor_version;
u16 datatype;
u16 channel_allocation;
u32 sample_rate;
u16 bit_width;
u16 reserved;
} __packed;
struct afe_param_id_slimbus_cfg {
u32 sb_cfg_minor_version;
/* Minor version used for tracking the version of the SLIMBUS
* configuration interface.
* Supported values: #AFE_API_VERSION_SLIMBUS_CONFIG
*/
u16 slimbus_dev_id;
/* SLIMbus hardware device ID, which is required to handle
* multiple SLIMbus hardware blocks.
* Supported values: - #AFE_SLIMBUS_DEVICE_1 - #AFE_SLIMBUS_DEVICE_2
*/
u16 bit_width;
/* Bit width of the sample.
* Supported values: 16, 24
*/
u16 data_format;
/* Data format supported by the SLIMbus hardware. The default is
* 0 (#AFE_SB_DATA_FORMAT_NOT_INDICATED), which indicates the
* hardware does not perform any format conversions before the data
* transfer.
*/
u16 num_channels;
/* Number of channels.
* Supported values: 1 to #AFE_PORT_MAX_AUDIO_CHAN_CNT
*/
u8 shared_ch_mapping[AFE_PORT_MAX_AUDIO_CHAN_CNT];
/* Mapping of shared channel IDs (128 to 255) to which the
* master port is to be connected.
* Shared_channel_mapping[i] represents the shared channel assigned
* for audio channel i in multichannel audio data.
*/
u32 sample_rate;
/* Sampling rate of the port.
* Supported values:
* - #AFE_PORT_SAMPLE_RATE_8K
* - #AFE_PORT_SAMPLE_RATE_16K
* - #AFE_PORT_SAMPLE_RATE_48K
* - #AFE_PORT_SAMPLE_RATE_96K
* - #AFE_PORT_SAMPLE_RATE_192K
*/
} __packed;
struct afe_clk_cfg {
u32 i2s_cfg_minor_version;
u32 clk_val1;
u32 clk_val2;
u16 clk_src;
u16 clk_root;
u16 clk_set_mode;
u16 reserved;
} __packed;
struct afe_digital_clk_cfg {
u32 i2s_cfg_minor_version;
u32 clk_val;
u16 clk_root;
u16 reserved;
} __packed;
struct afe_param_id_i2s_cfg {
u32 i2s_cfg_minor_version;
u16 bit_width;
u16 channel_mode;
u16 mono_stereo;
u16 ws_src;
u32 sample_rate;
u16 data_format;
u16 reserved;
} __packed;
struct afe_param_id_tdm_cfg {
u32 tdm_cfg_minor_version;
u32 num_channels;
u32 sample_rate;
u32 bit_width;
u16 data_format;
u16 sync_mode;
u16 sync_src;
u16 nslots_per_frame;
u16 ctrl_data_out_enable;
u16 ctrl_invert_sync_pulse;
u16 ctrl_sync_data_delay;
u16 slot_width;
u32 slot_mask;
} __packed;
struct afe_param_id_cdc_dma_cfg {
u32 cdc_dma_cfg_minor_version;
u32 sample_rate;
u16 bit_width;
u16 data_format;
u16 num_channels;
u16 active_channels_mask;
} __packed;
union afe_port_config {
struct afe_param_id_hdmi_multi_chan_audio_cfg hdmi_multi_ch;
struct afe_param_id_slimbus_cfg slim_cfg;
struct afe_param_id_i2s_cfg i2s_cfg;
struct afe_param_id_tdm_cfg tdm_cfg;
struct afe_param_id_cdc_dma_cfg dma_cfg;
} __packed;
struct afe_clk_set {
uint32_t clk_set_minor_version;
uint32_t clk_id;
uint32_t clk_freq_in_hz;
uint16_t clk_attri;
uint16_t clk_root;
uint32_t enable;
};
struct afe_param_id_slot_mapping_cfg {
u32 minor_version;
u16 num_channels;
u16 bitwidth;
u32 data_align_type;
u16 ch_mapping[AFE_PORT_MAX_AUDIO_CHAN_CNT];
} __packed;
struct q6afe_port {
wait_queue_head_t wait;
union afe_port_config port_cfg;
struct afe_param_id_slot_mapping_cfg *scfg;
struct aprv2_ibasic_rsp_result_t result;
int token;
int id;
int cfg_type;
struct q6afe *afe;
struct kref refcount;
struct list_head node;
};
struct afe_cmd_remote_lpass_core_hw_vote_request {
uint32_t hw_block_id;
char client_name[8];
} __packed;
struct afe_cmd_remote_lpass_core_hw_devote_request {
uint32_t hw_block_id;
uint32_t client_handle;
} __packed;
struct afe_port_map {
int port_id;
int token;
int is_rx;
int is_dig_pcm;
};
/*
* Mapping between Virtual Port IDs to DSP AFE Port ID
* On B Family SoCs DSP Port IDs are consistent across multiple SoCs
* on A Family SoCs DSP port IDs are same as virtual Port IDs.
*/
static struct afe_port_map port_maps[AFE_PORT_MAX] = {
[HDMI_RX] = { AFE_PORT_ID_MULTICHAN_HDMI_RX, HDMI_RX, 1, 1},
[SLIMBUS_0_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_RX,
SLIMBUS_0_RX, 1, 1},
[SLIMBUS_1_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_RX,
SLIMBUS_1_RX, 1, 1},
[SLIMBUS_2_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_RX,
SLIMBUS_2_RX, 1, 1},
[SLIMBUS_3_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_RX,
SLIMBUS_3_RX, 1, 1},
[SLIMBUS_4_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_RX,
SLIMBUS_4_RX, 1, 1},
[SLIMBUS_5_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_RX,
SLIMBUS_5_RX, 1, 1},
[SLIMBUS_6_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_RX,
SLIMBUS_6_RX, 1, 1},
[SLIMBUS_0_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_TX,
SLIMBUS_0_TX, 0, 1},
[SLIMBUS_1_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_TX,
SLIMBUS_1_TX, 0, 1},
[SLIMBUS_2_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_TX,
SLIMBUS_2_TX, 0, 1},
[SLIMBUS_3_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_TX,
SLIMBUS_3_TX, 0, 1},
[SLIMBUS_4_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_TX,
SLIMBUS_4_TX, 0, 1},
[SLIMBUS_5_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_TX,
SLIMBUS_5_TX, 0, 1},
[SLIMBUS_6_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_TX,
SLIMBUS_6_TX, 0, 1},
[PRIMARY_MI2S_RX] = { AFE_PORT_ID_PRIMARY_MI2S_RX,
PRIMARY_MI2S_RX, 1, 1},
[PRIMARY_MI2S_TX] = { AFE_PORT_ID_PRIMARY_MI2S_TX,
PRIMARY_MI2S_RX, 0, 1},
[SECONDARY_MI2S_RX] = { AFE_PORT_ID_SECONDARY_MI2S_RX,
SECONDARY_MI2S_RX, 1, 1},
[SECONDARY_MI2S_TX] = { AFE_PORT_ID_SECONDARY_MI2S_TX,
SECONDARY_MI2S_TX, 0, 1},
[TERTIARY_MI2S_RX] = { AFE_PORT_ID_TERTIARY_MI2S_RX,
TERTIARY_MI2S_RX, 1, 1},
[TERTIARY_MI2S_TX] = { AFE_PORT_ID_TERTIARY_MI2S_TX,
TERTIARY_MI2S_TX, 0, 1},
[QUATERNARY_MI2S_RX] = { AFE_PORT_ID_QUATERNARY_MI2S_RX,
QUATERNARY_MI2S_RX, 1, 1},
[QUATERNARY_MI2S_TX] = { AFE_PORT_ID_QUATERNARY_MI2S_TX,
QUATERNARY_MI2S_TX, 0, 1},
[QUINARY_MI2S_RX] = { AFE_PORT_ID_QUINARY_MI2S_RX,
QUINARY_MI2S_RX, 1, 1},
[QUINARY_MI2S_TX] = { AFE_PORT_ID_QUINARY_MI2S_TX,
QUINARY_MI2S_TX, 0, 1},
[PRIMARY_TDM_RX_0] = { AFE_PORT_ID_PRIMARY_TDM_RX,
PRIMARY_TDM_RX_0, 1, 1},
[PRIMARY_TDM_TX_0] = { AFE_PORT_ID_PRIMARY_TDM_TX,
PRIMARY_TDM_TX_0, 0, 1},
[PRIMARY_TDM_RX_1] = { AFE_PORT_ID_PRIMARY_TDM_RX_1,
PRIMARY_TDM_RX_1, 1, 1},
[PRIMARY_TDM_TX_1] = { AFE_PORT_ID_PRIMARY_TDM_TX_1,
PRIMARY_TDM_TX_1, 0, 1},
[PRIMARY_TDM_RX_2] = { AFE_PORT_ID_PRIMARY_TDM_RX_2,
PRIMARY_TDM_RX_2, 1, 1},
[PRIMARY_TDM_TX_2] = { AFE_PORT_ID_PRIMARY_TDM_TX_2,
PRIMARY_TDM_TX_2, 0, 1},
[PRIMARY_TDM_RX_3] = { AFE_PORT_ID_PRIMARY_TDM_RX_3,
PRIMARY_TDM_RX_3, 1, 1},
[PRIMARY_TDM_TX_3] = { AFE_PORT_ID_PRIMARY_TDM_TX_3,
PRIMARY_TDM_TX_3, 0, 1},
[PRIMARY_TDM_RX_4] = { AFE_PORT_ID_PRIMARY_TDM_RX_4,
PRIMARY_TDM_RX_4, 1, 1},
[PRIMARY_TDM_TX_4] = { AFE_PORT_ID_PRIMARY_TDM_TX_4,
PRIMARY_TDM_TX_4, 0, 1},
[PRIMARY_TDM_RX_5] = { AFE_PORT_ID_PRIMARY_TDM_RX_5,
PRIMARY_TDM_RX_5, 1, 1},
[PRIMARY_TDM_TX_5] = { AFE_PORT_ID_PRIMARY_TDM_TX_5,
PRIMARY_TDM_TX_5, 0, 1},
[PRIMARY_TDM_RX_6] = { AFE_PORT_ID_PRIMARY_TDM_RX_6,
PRIMARY_TDM_RX_6, 1, 1},
[PRIMARY_TDM_TX_6] = { AFE_PORT_ID_PRIMARY_TDM_TX_6,
PRIMARY_TDM_TX_6, 0, 1},
[PRIMARY_TDM_RX_7] = { AFE_PORT_ID_PRIMARY_TDM_RX_7,
PRIMARY_TDM_RX_7, 1, 1},
[PRIMARY_TDM_TX_7] = { AFE_PORT_ID_PRIMARY_TDM_TX_7,
PRIMARY_TDM_TX_7, 0, 1},
[SECONDARY_TDM_RX_0] = { AFE_PORT_ID_SECONDARY_TDM_RX,
SECONDARY_TDM_RX_0, 1, 1},
[SECONDARY_TDM_TX_0] = { AFE_PORT_ID_SECONDARY_TDM_TX,
SECONDARY_TDM_TX_0, 0, 1},
[SECONDARY_TDM_RX_1] = { AFE_PORT_ID_SECONDARY_TDM_RX_1,
SECONDARY_TDM_RX_1, 1, 1},
[SECONDARY_TDM_TX_1] = { AFE_PORT_ID_SECONDARY_TDM_TX_1,
SECONDARY_TDM_TX_1, 0, 1},
[SECONDARY_TDM_RX_2] = { AFE_PORT_ID_SECONDARY_TDM_RX_2,
SECONDARY_TDM_RX_2, 1, 1},
[SECONDARY_TDM_TX_2] = { AFE_PORT_ID_SECONDARY_TDM_TX_2,
SECONDARY_TDM_TX_2, 0, 1},
[SECONDARY_TDM_RX_3] = { AFE_PORT_ID_SECONDARY_TDM_RX_3,
SECONDARY_TDM_RX_3, 1, 1},
[SECONDARY_TDM_TX_3] = { AFE_PORT_ID_SECONDARY_TDM_TX_3,
SECONDARY_TDM_TX_3, 0, 1},
[SECONDARY_TDM_RX_4] = { AFE_PORT_ID_SECONDARY_TDM_RX_4,
SECONDARY_TDM_RX_4, 1, 1},
[SECONDARY_TDM_TX_4] = { AFE_PORT_ID_SECONDARY_TDM_TX_4,
SECONDARY_TDM_TX_4, 0, 1},
[SECONDARY_TDM_RX_5] = { AFE_PORT_ID_SECONDARY_TDM_RX_5,
SECONDARY_TDM_RX_5, 1, 1},
[SECONDARY_TDM_TX_5] = { AFE_PORT_ID_SECONDARY_TDM_TX_5,
SECONDARY_TDM_TX_5, 0, 1},
[SECONDARY_TDM_RX_6] = { AFE_PORT_ID_SECONDARY_TDM_RX_6,
SECONDARY_TDM_RX_6, 1, 1},
[SECONDARY_TDM_TX_6] = { AFE_PORT_ID_SECONDARY_TDM_TX_6,
SECONDARY_TDM_TX_6, 0, 1},
[SECONDARY_TDM_RX_7] = { AFE_PORT_ID_SECONDARY_TDM_RX_7,
SECONDARY_TDM_RX_7, 1, 1},
[SECONDARY_TDM_TX_7] = { AFE_PORT_ID_SECONDARY_TDM_TX_7,
SECONDARY_TDM_TX_7, 0, 1},
[TERTIARY_TDM_RX_0] = { AFE_PORT_ID_TERTIARY_TDM_RX,
TERTIARY_TDM_RX_0, 1, 1},
[TERTIARY_TDM_TX_0] = { AFE_PORT_ID_TERTIARY_TDM_TX,
TERTIARY_TDM_TX_0, 0, 1},
[TERTIARY_TDM_RX_1] = { AFE_PORT_ID_TERTIARY_TDM_RX_1,
TERTIARY_TDM_RX_1, 1, 1},
[TERTIARY_TDM_TX_1] = { AFE_PORT_ID_TERTIARY_TDM_TX_1,
TERTIARY_TDM_TX_1, 0, 1},
[TERTIARY_TDM_RX_2] = { AFE_PORT_ID_TERTIARY_TDM_RX_2,
TERTIARY_TDM_RX_2, 1, 1},
[TERTIARY_TDM_TX_2] = { AFE_PORT_ID_TERTIARY_TDM_TX_2,
TERTIARY_TDM_TX_2, 0, 1},
[TERTIARY_TDM_RX_3] = { AFE_PORT_ID_TERTIARY_TDM_RX_3,
TERTIARY_TDM_RX_3, 1, 1},
[TERTIARY_TDM_TX_3] = { AFE_PORT_ID_TERTIARY_TDM_TX_3,
TERTIARY_TDM_TX_3, 0, 1},
[TERTIARY_TDM_RX_4] = { AFE_PORT_ID_TERTIARY_TDM_RX_4,
TERTIARY_TDM_RX_4, 1, 1},
[TERTIARY_TDM_TX_4] = { AFE_PORT_ID_TERTIARY_TDM_TX_4,
TERTIARY_TDM_TX_4, 0, 1},
[TERTIARY_TDM_RX_5] = { AFE_PORT_ID_TERTIARY_TDM_RX_5,
TERTIARY_TDM_RX_5, 1, 1},
[TERTIARY_TDM_TX_5] = { AFE_PORT_ID_TERTIARY_TDM_TX_5,
TERTIARY_TDM_TX_5, 0, 1},
[TERTIARY_TDM_RX_6] = { AFE_PORT_ID_TERTIARY_TDM_RX_6,
TERTIARY_TDM_RX_6, 1, 1},
[TERTIARY_TDM_TX_6] = { AFE_PORT_ID_TERTIARY_TDM_TX_6,
TERTIARY_TDM_TX_6, 0, 1},
[TERTIARY_TDM_RX_7] = { AFE_PORT_ID_TERTIARY_TDM_RX_7,
TERTIARY_TDM_RX_7, 1, 1},
[TERTIARY_TDM_TX_7] = { AFE_PORT_ID_TERTIARY_TDM_TX_7,
TERTIARY_TDM_TX_7, 0, 1},
[QUATERNARY_TDM_RX_0] = { AFE_PORT_ID_QUATERNARY_TDM_RX,
QUATERNARY_TDM_RX_0, 1, 1},
[QUATERNARY_TDM_TX_0] = { AFE_PORT_ID_QUATERNARY_TDM_TX,
QUATERNARY_TDM_TX_0, 0, 1},
[QUATERNARY_TDM_RX_1] = { AFE_PORT_ID_QUATERNARY_TDM_RX_1,
QUATERNARY_TDM_RX_1, 1, 1},
[QUATERNARY_TDM_TX_1] = { AFE_PORT_ID_QUATERNARY_TDM_TX_1,
QUATERNARY_TDM_TX_1, 0, 1},
[QUATERNARY_TDM_RX_2] = { AFE_PORT_ID_QUATERNARY_TDM_RX_2,
QUATERNARY_TDM_RX_2, 1, 1},
[QUATERNARY_TDM_TX_2] = { AFE_PORT_ID_QUATERNARY_TDM_TX_2,
QUATERNARY_TDM_TX_2, 0, 1},
[QUATERNARY_TDM_RX_3] = { AFE_PORT_ID_QUATERNARY_TDM_RX_3,
QUATERNARY_TDM_RX_3, 1, 1},
[QUATERNARY_TDM_TX_3] = { AFE_PORT_ID_QUATERNARY_TDM_TX_3,
QUATERNARY_TDM_TX_3, 0, 1},
[QUATERNARY_TDM_RX_4] = { AFE_PORT_ID_QUATERNARY_TDM_RX_4,
QUATERNARY_TDM_RX_4, 1, 1},
[QUATERNARY_TDM_TX_4] = { AFE_PORT_ID_QUATERNARY_TDM_TX_4,
QUATERNARY_TDM_TX_4, 0, 1},
[QUATERNARY_TDM_RX_5] = { AFE_PORT_ID_QUATERNARY_TDM_RX_5,
QUATERNARY_TDM_RX_5, 1, 1},
[QUATERNARY_TDM_TX_5] = { AFE_PORT_ID_QUATERNARY_TDM_TX_5,
QUATERNARY_TDM_TX_5, 0, 1},
[QUATERNARY_TDM_RX_6] = { AFE_PORT_ID_QUATERNARY_TDM_RX_6,
QUATERNARY_TDM_RX_6, 1, 1},
[QUATERNARY_TDM_TX_6] = { AFE_PORT_ID_QUATERNARY_TDM_TX_6,
QUATERNARY_TDM_TX_6, 0, 1},
[QUATERNARY_TDM_RX_7] = { AFE_PORT_ID_QUATERNARY_TDM_RX_7,
QUATERNARY_TDM_RX_7, 1, 1},
[QUATERNARY_TDM_TX_7] = { AFE_PORT_ID_QUATERNARY_TDM_TX_7,
QUATERNARY_TDM_TX_7, 0, 1},
[QUINARY_TDM_RX_0] = { AFE_PORT_ID_QUINARY_TDM_RX,
QUINARY_TDM_RX_0, 1, 1},
[QUINARY_TDM_TX_0] = { AFE_PORT_ID_QUINARY_TDM_TX,
QUINARY_TDM_TX_0, 0, 1},
[QUINARY_TDM_RX_1] = { AFE_PORT_ID_QUINARY_TDM_RX_1,
QUINARY_TDM_RX_1, 1, 1},
[QUINARY_TDM_TX_1] = { AFE_PORT_ID_QUINARY_TDM_TX_1,
QUINARY_TDM_TX_1, 0, 1},
[QUINARY_TDM_RX_2] = { AFE_PORT_ID_QUINARY_TDM_RX_2,
QUINARY_TDM_RX_2, 1, 1},
[QUINARY_TDM_TX_2] = { AFE_PORT_ID_QUINARY_TDM_TX_2,
QUINARY_TDM_TX_2, 0, 1},
[QUINARY_TDM_RX_3] = { AFE_PORT_ID_QUINARY_TDM_RX_3,
QUINARY_TDM_RX_3, 1, 1},
[QUINARY_TDM_TX_3] = { AFE_PORT_ID_QUINARY_TDM_TX_3,
QUINARY_TDM_TX_3, 0, 1},
[QUINARY_TDM_RX_4] = { AFE_PORT_ID_QUINARY_TDM_RX_4,
QUINARY_TDM_RX_4, 1, 1},
[QUINARY_TDM_TX_4] = { AFE_PORT_ID_QUINARY_TDM_TX_4,
QUINARY_TDM_TX_4, 0, 1},
[QUINARY_TDM_RX_5] = { AFE_PORT_ID_QUINARY_TDM_RX_5,
QUINARY_TDM_RX_5, 1, 1},
[QUINARY_TDM_TX_5] = { AFE_PORT_ID_QUINARY_TDM_TX_5,
QUINARY_TDM_TX_5, 0, 1},
[QUINARY_TDM_RX_6] = { AFE_PORT_ID_QUINARY_TDM_RX_6,
QUINARY_TDM_RX_6, 1, 1},
[QUINARY_TDM_TX_6] = { AFE_PORT_ID_QUINARY_TDM_TX_6,
QUINARY_TDM_TX_6, 0, 1},
[QUINARY_TDM_RX_7] = { AFE_PORT_ID_QUINARY_TDM_RX_7,
QUINARY_TDM_RX_7, 1, 1},
[QUINARY_TDM_TX_7] = { AFE_PORT_ID_QUINARY_TDM_TX_7,
QUINARY_TDM_TX_7, 0, 1},
[DISPLAY_PORT_RX] = { AFE_PORT_ID_HDMI_OVER_DP_RX,
DISPLAY_PORT_RX, 1, 1},
[WSA_CODEC_DMA_RX_0] = { AFE_PORT_ID_WSA_CODEC_DMA_RX_0,
WSA_CODEC_DMA_RX_0, 1, 1},
[WSA_CODEC_DMA_TX_0] = { AFE_PORT_ID_WSA_CODEC_DMA_TX_0,
WSA_CODEC_DMA_TX_0, 0, 1},
[WSA_CODEC_DMA_RX_1] = { AFE_PORT_ID_WSA_CODEC_DMA_RX_1,
WSA_CODEC_DMA_RX_1, 1, 1},
[WSA_CODEC_DMA_TX_1] = { AFE_PORT_ID_WSA_CODEC_DMA_TX_1,
WSA_CODEC_DMA_TX_1, 0, 1},
[WSA_CODEC_DMA_TX_2] = { AFE_PORT_ID_WSA_CODEC_DMA_TX_2,
WSA_CODEC_DMA_TX_2, 0, 1},
[VA_CODEC_DMA_TX_0] = { AFE_PORT_ID_VA_CODEC_DMA_TX_0,
VA_CODEC_DMA_TX_0, 0, 1},
[VA_CODEC_DMA_TX_1] = { AFE_PORT_ID_VA_CODEC_DMA_TX_1,
VA_CODEC_DMA_TX_1, 0, 1},
[VA_CODEC_DMA_TX_2] = { AFE_PORT_ID_VA_CODEC_DMA_TX_2,
VA_CODEC_DMA_TX_2, 0, 1},
[RX_CODEC_DMA_RX_0] = { AFE_PORT_ID_RX_CODEC_DMA_RX_0,
RX_CODEC_DMA_RX_0, 1, 1},
[TX_CODEC_DMA_TX_0] = { AFE_PORT_ID_TX_CODEC_DMA_TX_0,
TX_CODEC_DMA_TX_0, 0, 1},
[RX_CODEC_DMA_RX_1] = { AFE_PORT_ID_RX_CODEC_DMA_RX_1,
RX_CODEC_DMA_RX_1, 1, 1},
[TX_CODEC_DMA_TX_1] = { AFE_PORT_ID_TX_CODEC_DMA_TX_1,
TX_CODEC_DMA_TX_1, 0, 1},
[RX_CODEC_DMA_RX_2] = { AFE_PORT_ID_RX_CODEC_DMA_RX_2,
RX_CODEC_DMA_RX_2, 1, 1},
[TX_CODEC_DMA_TX_2] = { AFE_PORT_ID_TX_CODEC_DMA_TX_2,
TX_CODEC_DMA_TX_2, 0, 1},
[RX_CODEC_DMA_RX_3] = { AFE_PORT_ID_RX_CODEC_DMA_RX_3,
RX_CODEC_DMA_RX_3, 1, 1},
[TX_CODEC_DMA_TX_3] = { AFE_PORT_ID_TX_CODEC_DMA_TX_3,
TX_CODEC_DMA_TX_3, 0, 1},
[RX_CODEC_DMA_RX_4] = { AFE_PORT_ID_RX_CODEC_DMA_RX_4,
RX_CODEC_DMA_RX_4, 1, 1},
[TX_CODEC_DMA_TX_4] = { AFE_PORT_ID_TX_CODEC_DMA_TX_4,
TX_CODEC_DMA_TX_4, 0, 1},
[RX_CODEC_DMA_RX_5] = { AFE_PORT_ID_RX_CODEC_DMA_RX_5,
RX_CODEC_DMA_RX_5, 1, 1},
[TX_CODEC_DMA_TX_5] = { AFE_PORT_ID_TX_CODEC_DMA_TX_5,
TX_CODEC_DMA_TX_5, 0, 1},
[RX_CODEC_DMA_RX_6] = { AFE_PORT_ID_RX_CODEC_DMA_RX_6,
RX_CODEC_DMA_RX_6, 1, 1},
[RX_CODEC_DMA_RX_7] = { AFE_PORT_ID_RX_CODEC_DMA_RX_7,
RX_CODEC_DMA_RX_7, 1, 1},
};
static void q6afe_port_free(struct kref *ref)
{
struct q6afe_port *port;
struct q6afe *afe;
unsigned long flags;
port = container_of(ref, struct q6afe_port, refcount);
afe = port->afe;
spin_lock_irqsave(&afe->port_list_lock, flags);
list_del(&port->node);
spin_unlock_irqrestore(&afe->port_list_lock, flags);
kfree(port->scfg);
kfree(port);
}
static struct q6afe_port *q6afe_find_port(struct q6afe *afe, int token)
{
struct q6afe_port *p;
struct q6afe_port *ret = NULL;
unsigned long flags;
spin_lock_irqsave(&afe->port_list_lock, flags);
list_for_each_entry(p, &afe->port_list, node)
if (p->token == token) {
ret = p;
kref_get(&p->refcount);
break;
}
spin_unlock_irqrestore(&afe->port_list_lock, flags);
return ret;
}
static int q6afe_callback(struct apr_device *adev, struct apr_resp_pkt *data)
{
struct q6afe *afe = dev_get_drvdata(&adev->dev);
struct aprv2_ibasic_rsp_result_t *res;
struct apr_hdr *hdr = &data->hdr;
struct q6afe_port *port;
if (!data->payload_size)
return 0;
res = data->payload;
switch (hdr->opcode) {
case APR_BASIC_RSP_RESULT: {
if (res->status) {
dev_err(afe->dev, "cmd = 0x%x returned error = 0x%x\n",
res->opcode, res->status);
}
switch (res->opcode) {
case AFE_PORT_CMD_SET_PARAM_V2:
case AFE_PORT_CMD_DEVICE_STOP:
case AFE_PORT_CMD_DEVICE_START:
case AFE_SVC_CMD_SET_PARAM:
port = q6afe_find_port(afe, hdr->token);
if (port) {
port->result = *res;
wake_up(&port->wait);
kref_put(&port->refcount, q6afe_port_free);
} else if (hdr->token == AFE_CLK_TOKEN) {
afe->result = *res;
wake_up(&afe->wait);
}
break;
default:
dev_err(afe->dev, "Unknown cmd 0x%x\n", res->opcode);
break;
}
}
break;
case AFE_CMD_RSP_REMOTE_LPASS_CORE_HW_VOTE_REQUEST:
afe->result.opcode = hdr->opcode;
afe->result.status = res->status;
wake_up(&afe->wait);
break;
default:
break;
}
return 0;
}
/**
* q6afe_get_port_id() - Get port id from a given port index
*
* @index: port index
*
* Return: Will be an negative on error or valid port_id on success
*/
int q6afe_get_port_id(int index)
{
if (index < 0 || index >= AFE_PORT_MAX)
return -EINVAL;
return port_maps[index].port_id;
}
EXPORT_SYMBOL_GPL(q6afe_get_port_id);
static int afe_apr_send_pkt(struct q6afe *afe, struct apr_pkt *pkt,
struct q6afe_port *port, uint32_t rsp_opcode)
{
wait_queue_head_t *wait;
struct aprv2_ibasic_rsp_result_t *result;
int ret;
mutex_lock(&afe->lock);
if (port) {
wait = &port->wait;
result = &port->result;
} else {
result = &afe->result;
wait = &afe->wait;
}
result->opcode = 0;
result->status = 0;
ret = apr_send_pkt(afe->apr, pkt);
if (ret < 0) {
dev_err(afe->dev, "packet not transmitted (%d)\n", ret);
ret = -EINVAL;
goto err;
}
ret = wait_event_timeout(*wait, (result->opcode == rsp_opcode),
msecs_to_jiffies(TIMEOUT_MS));
if (!ret) {
ret = -ETIMEDOUT;
} else if (result->status > 0) {
dev_err(afe->dev, "DSP returned error[%x]\n",
result->status);
ret = -EINVAL;
} else {
ret = 0;
}
err:
mutex_unlock(&afe->lock);
return ret;
}
static int q6afe_set_param(struct q6afe *afe, struct q6afe_port *port,
void *data, int param_id, int module_id, int psize,
int token)
{
struct afe_svc_cmd_set_param *param;
struct afe_port_param_data_v2 *pdata;
struct apr_pkt *pkt;
int ret, pkt_size;
void *p, *pl;
pkt_size = APR_HDR_SIZE + sizeof(*param) + sizeof(*pdata) + psize;
p = kzalloc(pkt_size, GFP_KERNEL);
if (!p)
return -ENOMEM;
pkt = p;
param = p + APR_HDR_SIZE;
pdata = p + APR_HDR_SIZE + sizeof(*param);
pl = p + APR_HDR_SIZE + sizeof(*param) + sizeof(*pdata);
memcpy(pl, data, psize);
pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD,
APR_HDR_LEN(APR_HDR_SIZE),
APR_PKT_VER);
pkt->hdr.pkt_size = pkt_size;
pkt->hdr.src_port = 0;
pkt->hdr.dest_port = 0;
pkt->hdr.token = token;
pkt->hdr.opcode = AFE_SVC_CMD_SET_PARAM;
param->payload_size = sizeof(*pdata) + psize;
param->payload_address_lsw = 0x00;
param->payload_address_msw = 0x00;
param->mem_map_handle = 0x00;
pdata->module_id = module_id;
pdata->param_id = param_id;
pdata->param_size = psize;
ret = afe_apr_send_pkt(afe, pkt, port, AFE_SVC_CMD_SET_PARAM);
if (ret)
dev_err(afe->dev, "AFE set params failed %d\n", ret);
kfree(pkt);
return ret;
}
static int q6afe_port_set_param(struct q6afe_port *port, void *data,
int param_id, int module_id, int psize)
{
return q6afe_set_param(port->afe, port, data, param_id, module_id,
psize, port->token);
}
static int q6afe_port_set_param_v2(struct q6afe_port *port, void *data,
int param_id, int module_id, int psize)
{
struct afe_port_cmd_set_param_v2 *param;
struct afe_port_param_data_v2 *pdata;
struct q6afe *afe = port->afe;
struct apr_pkt *pkt;
u16 port_id = port->id;
int ret, pkt_size;
void *p, *pl;
pkt_size = APR_HDR_SIZE + sizeof(*param) + sizeof(*pdata) + psize;
p = kzalloc(pkt_size, GFP_KERNEL);
if (!p)
return -ENOMEM;
pkt = p;
param = p + APR_HDR_SIZE;
pdata = p + APR_HDR_SIZE + sizeof(*param);
pl = p + APR_HDR_SIZE + sizeof(*param) + sizeof(*pdata);
memcpy(pl, data, psize);
pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD,
APR_HDR_LEN(APR_HDR_SIZE),
APR_PKT_VER);
pkt->hdr.pkt_size = pkt_size;
pkt->hdr.src_port = 0;
pkt->hdr.dest_port = 0;
pkt->hdr.token = port->token;
pkt->hdr.opcode = AFE_PORT_CMD_SET_PARAM_V2;
param->port_id = port_id;
param->payload_size = sizeof(*pdata) + psize;
param->payload_address_lsw = 0x00;
param->payload_address_msw = 0x00;
param->mem_map_handle = 0x00;
pdata->module_id = module_id;
pdata->param_id = param_id;
pdata->param_size = psize;
ret = afe_apr_send_pkt(afe, pkt, port, AFE_PORT_CMD_SET_PARAM_V2);
if (ret)
dev_err(afe->dev, "AFE enable for port 0x%x failed %d\n",
port_id, ret);
kfree(pkt);
return ret;
}
static int q6afe_port_set_lpass_clock(struct q6afe_port *port,
struct afe_clk_cfg *cfg)
{
return q6afe_port_set_param_v2(port, cfg,
AFE_PARAM_ID_LPAIF_CLK_CONFIG,
AFE_MODULE_AUDIO_DEV_INTERFACE,
sizeof(*cfg));
}
static int q6afe_set_lpass_clock_v2(struct q6afe_port *port,
struct afe_clk_set *cfg)
{
return q6afe_port_set_param(port, cfg, AFE_PARAM_ID_CLOCK_SET,
AFE_MODULE_CLOCK_SET, sizeof(*cfg));
}
static int q6afe_set_digital_codec_core_clock(struct q6afe_port *port,
struct afe_digital_clk_cfg *cfg)
{
return q6afe_port_set_param_v2(port, cfg,
AFE_PARAM_ID_INT_DIGITAL_CDC_CLK_CONFIG,
AFE_MODULE_AUDIO_DEV_INTERFACE,
sizeof(*cfg));
}
int q6afe_set_lpass_clock(struct device *dev, int clk_id, int attri,
int clk_root, unsigned int freq)
{
struct q6afe *afe = dev_get_drvdata(dev->parent);
struct afe_clk_set cset = {0,};
cset.clk_set_minor_version = AFE_API_VERSION_CLOCK_SET;
cset.clk_id = clk_id;
cset.clk_freq_in_hz = freq;
cset.clk_attri = attri;
cset.clk_root = clk_root;
cset.enable = !!freq;
return q6afe_set_param(afe, NULL, &cset, AFE_PARAM_ID_CLOCK_SET,
AFE_MODULE_CLOCK_SET, sizeof(cset),
AFE_CLK_TOKEN);
}
EXPORT_SYMBOL_GPL(q6afe_set_lpass_clock);
int q6afe_port_set_sysclk(struct q6afe_port *port, int clk_id,
int clk_src, int clk_root,
unsigned int freq, int dir)
{
struct afe_clk_cfg ccfg = {0,};
struct afe_clk_set cset = {0,};
struct afe_digital_clk_cfg dcfg = {0,};
int ret;
switch (clk_id) {
case LPAIF_DIG_CLK:
dcfg.i2s_cfg_minor_version = AFE_API_VERSION_I2S_CONFIG;
dcfg.clk_val = freq;
dcfg.clk_root = clk_root;
ret = q6afe_set_digital_codec_core_clock(port, &dcfg);
break;
case LPAIF_BIT_CLK:
ccfg.i2s_cfg_minor_version = AFE_API_VERSION_I2S_CONFIG;
ccfg.clk_val1 = freq;
ccfg.clk_src = clk_src;
ccfg.clk_root = clk_root;
ccfg.clk_set_mode = Q6AFE_LPASS_MODE_CLK1_VALID;
ret = q6afe_port_set_lpass_clock(port, &ccfg);
break;
case LPAIF_OSR_CLK:
ccfg.i2s_cfg_minor_version = AFE_API_VERSION_I2S_CONFIG;
ccfg.clk_val2 = freq;
ccfg.clk_src = clk_src;
ccfg.clk_root = clk_root;
ccfg.clk_set_mode = Q6AFE_LPASS_MODE_CLK2_VALID;
ret = q6afe_port_set_lpass_clock(port, &ccfg);
break;
case Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT ... Q6AFE_LPASS_CLK_ID_QUI_MI2S_OSR:
case Q6AFE_LPASS_CLK_ID_MCLK_1 ... Q6AFE_LPASS_CLK_ID_INT_MCLK_1:
case Q6AFE_LPASS_CLK_ID_PRI_TDM_IBIT ... Q6AFE_LPASS_CLK_ID_QUIN_TDM_EBIT:
case Q6AFE_LPASS_CLK_ID_WSA_CORE_MCLK ... Q6AFE_LPASS_CLK_ID_VA_CORE_2X_MCLK:
cset.clk_set_minor_version = AFE_API_VERSION_CLOCK_SET;
cset.clk_id = clk_id;
cset.clk_freq_in_hz = freq;
cset.clk_attri = clk_src;
cset.clk_root = clk_root;
cset.enable = !!freq;
ret = q6afe_set_lpass_clock_v2(port, &cset);
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
EXPORT_SYMBOL_GPL(q6afe_port_set_sysclk);
/**
* q6afe_port_stop() - Stop a afe port
*
* @port: Instance of port to stop
*
* Return: Will be an negative on packet size on success.
*/
int q6afe_port_stop(struct q6afe_port *port)
{
struct afe_port_cmd_device_stop *stop;
struct q6afe *afe = port->afe;
struct apr_pkt *pkt;
int port_id = port->id;
int ret = 0;
int index, pkt_size;
void *p;
index = port->token;
if (index < 0 || index >= AFE_PORT_MAX) {
dev_err(afe->dev, "AFE port index[%d] invalid!\n", index);
return -EINVAL;
}
pkt_size = APR_HDR_SIZE + sizeof(*stop);
p = kzalloc(pkt_size, GFP_KERNEL);
if (!p)
return -ENOMEM;
pkt = p;
stop = p + APR_HDR_SIZE;
pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD,
APR_HDR_LEN(APR_HDR_SIZE),
APR_PKT_VER);
pkt->hdr.pkt_size = pkt_size;
pkt->hdr.src_port = 0;
pkt->hdr.dest_port = 0;
pkt->hdr.token = index;
pkt->hdr.opcode = AFE_PORT_CMD_DEVICE_STOP;
stop->port_id = port_id;
stop->reserved = 0;
ret = afe_apr_send_pkt(afe, pkt, port, AFE_PORT_CMD_DEVICE_STOP);
if (ret)
dev_err(afe->dev, "AFE close failed %d\n", ret);
kfree(pkt);
return ret;
}
EXPORT_SYMBOL_GPL(q6afe_port_stop);
/**
* q6afe_slim_port_prepare() - Prepare slim afe port.
*
* @port: Instance of afe port
* @cfg: SLIM configuration for the afe port
*
*/
void q6afe_slim_port_prepare(struct q6afe_port *port,
struct q6afe_slim_cfg *cfg)
{
union afe_port_config *pcfg = &port->port_cfg;
pcfg->slim_cfg.sb_cfg_minor_version = AFE_API_VERSION_SLIMBUS_CONFIG;
pcfg->slim_cfg.sample_rate = cfg->sample_rate;
pcfg->slim_cfg.bit_width = cfg->bit_width;
pcfg->slim_cfg.num_channels = cfg->num_channels;
pcfg->slim_cfg.data_format = cfg->data_format;
pcfg->slim_cfg.shared_ch_mapping[0] = cfg->ch_mapping[0];
pcfg->slim_cfg.shared_ch_mapping[1] = cfg->ch_mapping[1];
pcfg->slim_cfg.shared_ch_mapping[2] = cfg->ch_mapping[2];
pcfg->slim_cfg.shared_ch_mapping[3] = cfg->ch_mapping[3];
}
EXPORT_SYMBOL_GPL(q6afe_slim_port_prepare);
/**
* q6afe_tdm_port_prepare() - Prepare tdm afe port.
*
* @port: Instance of afe port
* @cfg: TDM configuration for the afe port
*
*/
void q6afe_tdm_port_prepare(struct q6afe_port *port,
struct q6afe_tdm_cfg *cfg)
{
union afe_port_config *pcfg = &port->port_cfg;
pcfg->tdm_cfg.tdm_cfg_minor_version = AFE_API_VERSION_TDM_CONFIG;
pcfg->tdm_cfg.num_channels = cfg->num_channels;
pcfg->tdm_cfg.sample_rate = cfg->sample_rate;
pcfg->tdm_cfg.bit_width = cfg->bit_width;
pcfg->tdm_cfg.data_format = cfg->data_format;
pcfg->tdm_cfg.sync_mode = cfg->sync_mode;
pcfg->tdm_cfg.sync_src = cfg->sync_src;
pcfg->tdm_cfg.nslots_per_frame = cfg->nslots_per_frame;
pcfg->tdm_cfg.slot_width = cfg->slot_width;
pcfg->tdm_cfg.slot_mask = cfg->slot_mask;
port->scfg = kzalloc(sizeof(*port->scfg), GFP_KERNEL);
if (!port->scfg)
return;
port->scfg->minor_version = AFE_API_VERSION_SLOT_MAPPING_CONFIG;
port->scfg->num_channels = cfg->num_channels;
port->scfg->bitwidth = cfg->bit_width;
port->scfg->data_align_type = cfg->data_align_type;
memcpy(port->scfg->ch_mapping, cfg->ch_mapping,
sizeof(u16) * AFE_PORT_MAX_AUDIO_CHAN_CNT);
}
EXPORT_SYMBOL_GPL(q6afe_tdm_port_prepare);
/**
* q6afe_hdmi_port_prepare() - Prepare hdmi afe port.
*
* @port: Instance of afe port
* @cfg: HDMI configuration for the afe port
*
*/
void q6afe_hdmi_port_prepare(struct q6afe_port *port,
struct q6afe_hdmi_cfg *cfg)
{
union afe_port_config *pcfg = &port->port_cfg;
pcfg->hdmi_multi_ch.hdmi_cfg_minor_version =
AFE_API_VERSION_HDMI_CONFIG;
pcfg->hdmi_multi_ch.datatype = cfg->datatype;
pcfg->hdmi_multi_ch.channel_allocation = cfg->channel_allocation;
pcfg->hdmi_multi_ch.sample_rate = cfg->sample_rate;
pcfg->hdmi_multi_ch.bit_width = cfg->bit_width;
}
EXPORT_SYMBOL_GPL(q6afe_hdmi_port_prepare);
/**
* q6afe_i2s_port_prepare() - Prepare i2s afe port.
*
* @port: Instance of afe port
* @cfg: I2S configuration for the afe port
* Return: Will be an negative on error and zero on success.
*/
int q6afe_i2s_port_prepare(struct q6afe_port *port, struct q6afe_i2s_cfg *cfg)
{
union afe_port_config *pcfg = &port->port_cfg;
struct device *dev = port->afe->dev;
int num_sd_lines;
pcfg->i2s_cfg.i2s_cfg_minor_version = AFE_API_VERSION_I2S_CONFIG;
pcfg->i2s_cfg.sample_rate = cfg->sample_rate;
pcfg->i2s_cfg.bit_width = cfg->bit_width;
pcfg->i2s_cfg.data_format = AFE_LINEAR_PCM_DATA;
switch (cfg->fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BP_FP:
pcfg->i2s_cfg.ws_src = AFE_PORT_CONFIG_I2S_WS_SRC_INTERNAL;
break;
case SND_SOC_DAIFMT_BC_FC:
/* CPU is slave */
pcfg->i2s_cfg.ws_src = AFE_PORT_CONFIG_I2S_WS_SRC_EXTERNAL;
break;
default:
break;
}
num_sd_lines = hweight_long(cfg->sd_line_mask);
switch (num_sd_lines) {
case 0:
dev_err(dev, "no line is assigned\n");
return -EINVAL;
case 1:
switch (cfg->sd_line_mask) {
case AFE_PORT_I2S_SD0_MASK:
pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD0;
break;
case AFE_PORT_I2S_SD1_MASK:
pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD1;
break;
case AFE_PORT_I2S_SD2_MASK:
pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD2;
break;
case AFE_PORT_I2S_SD3_MASK:
pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD3;
break;
default:
dev_err(dev, "Invalid SD lines\n");
return -EINVAL;
}
break;
case 2:
switch (cfg->sd_line_mask) {
case AFE_PORT_I2S_SD0_1_MASK:
pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_QUAD01;
break;
case AFE_PORT_I2S_SD2_3_MASK:
pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_QUAD23;
break;
default:
dev_err(dev, "Invalid SD lines\n");
return -EINVAL;
}
break;
case 3:
switch (cfg->sd_line_mask) {
case AFE_PORT_I2S_SD0_1_2_MASK:
pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_6CHS;
break;
default:
dev_err(dev, "Invalid SD lines\n");
return -EINVAL;
}
break;
case 4:
switch (cfg->sd_line_mask) {
case AFE_PORT_I2S_SD0_1_2_3_MASK:
pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_8CHS;
break;
default:
dev_err(dev, "Invalid SD lines\n");
return -EINVAL;
}
break;
default:
dev_err(dev, "Invalid SD lines\n");
return -EINVAL;
}
switch (cfg->num_channels) {
case 1:
case 2:
switch (pcfg->i2s_cfg.channel_mode) {
case AFE_PORT_I2S_QUAD01:
case AFE_PORT_I2S_6CHS:
case AFE_PORT_I2S_8CHS:
pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD0;
break;
case AFE_PORT_I2S_QUAD23:
pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD2;
break;
}
if (cfg->num_channels == 2)
pcfg->i2s_cfg.mono_stereo = AFE_PORT_I2S_STEREO;
else
pcfg->i2s_cfg.mono_stereo = AFE_PORT_I2S_MONO;
break;
case 3:
case 4:
if (pcfg->i2s_cfg.channel_mode < AFE_PORT_I2S_QUAD01) {
dev_err(dev, "Invalid Channel mode\n");
return -EINVAL;
}
break;
case 5:
case 6:
if (pcfg->i2s_cfg.channel_mode < AFE_PORT_I2S_6CHS) {
dev_err(dev, "Invalid Channel mode\n");
return -EINVAL;
}
break;
case 7:
case 8:
if (pcfg->i2s_cfg.channel_mode < AFE_PORT_I2S_8CHS) {
dev_err(dev, "Invalid Channel mode\n");
return -EINVAL;
}
break;
default:
break;
}
return 0;
}
EXPORT_SYMBOL_GPL(q6afe_i2s_port_prepare);
/**
* q6afe_cdc_dma_port_prepare() - Prepare dma afe port.
*
* @port: Instance of afe port
* @cfg: DMA configuration for the afe port
*
*/
void q6afe_cdc_dma_port_prepare(struct q6afe_port *port,
struct q6afe_cdc_dma_cfg *cfg)
{
union afe_port_config *pcfg = &port->port_cfg;
struct afe_param_id_cdc_dma_cfg *dma_cfg = &pcfg->dma_cfg;
dma_cfg->cdc_dma_cfg_minor_version = AFE_API_VERSION_CODEC_DMA_CONFIG;
dma_cfg->sample_rate = cfg->sample_rate;
dma_cfg->bit_width = cfg->bit_width;
dma_cfg->data_format = cfg->data_format;
dma_cfg->num_channels = cfg->num_channels;
if (!cfg->active_channels_mask)
dma_cfg->active_channels_mask = (1 << cfg->num_channels) - 1;
}
EXPORT_SYMBOL_GPL(q6afe_cdc_dma_port_prepare);
/**
* q6afe_port_start() - Start a afe port
*
* @port: Instance of port to start
*
* Return: Will be an negative on packet size on success.
*/
int q6afe_port_start(struct q6afe_port *port)
{
struct afe_port_cmd_device_start *start;
struct q6afe *afe = port->afe;
int port_id = port->id;
int ret, param_id = port->cfg_type;
struct apr_pkt *pkt;
int pkt_size;
void *p;
ret = q6afe_port_set_param_v2(port, &port->port_cfg, param_id,
AFE_MODULE_AUDIO_DEV_INTERFACE,
sizeof(port->port_cfg));
if (ret) {
dev_err(afe->dev, "AFE enable for port 0x%x failed %d\n",
port_id, ret);
return ret;
}
if (port->scfg) {
ret = q6afe_port_set_param_v2(port, port->scfg,
AFE_PARAM_ID_PORT_SLOT_MAPPING_CONFIG,
AFE_MODULE_TDM, sizeof(*port->scfg));
if (ret) {
dev_err(afe->dev, "AFE enable for port 0x%x failed %d\n",
port_id, ret);
return ret;
}
}
pkt_size = APR_HDR_SIZE + sizeof(*start);
p = kzalloc(pkt_size, GFP_KERNEL);
if (!p)
return -ENOMEM;
pkt = p;
start = p + APR_HDR_SIZE;
pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD,
APR_HDR_LEN(APR_HDR_SIZE),
APR_PKT_VER);
pkt->hdr.pkt_size = pkt_size;
pkt->hdr.src_port = 0;
pkt->hdr.dest_port = 0;
pkt->hdr.token = port->token;
pkt->hdr.opcode = AFE_PORT_CMD_DEVICE_START;
start->port_id = port_id;
ret = afe_apr_send_pkt(afe, pkt, port, AFE_PORT_CMD_DEVICE_START);
if (ret)
dev_err(afe->dev, "AFE enable for port 0x%x failed %d\n",
port_id, ret);
kfree(pkt);
return ret;
}
EXPORT_SYMBOL_GPL(q6afe_port_start);
/**
* q6afe_port_get_from_id() - Get port instance from a port id
*
* @dev: Pointer to afe child device.
* @id: port id
*
* Return: Will be an error pointer on error or a valid afe port
* on success.
*/
struct q6afe_port *q6afe_port_get_from_id(struct device *dev, int id)
{
int port_id;
struct q6afe *afe = dev_get_drvdata(dev->parent);
struct q6afe_port *port;
unsigned long flags;
int cfg_type;
if (id < 0 || id >= AFE_PORT_MAX) {
dev_err(dev, "AFE port token[%d] invalid!\n", id);
return ERR_PTR(-EINVAL);
}
/* if port is multiple times bind/unbind before callback finishes */
port = q6afe_find_port(afe, id);
if (port) {
dev_err(dev, "AFE Port already open\n");
return port;
}
port_id = port_maps[id].port_id;
switch (port_id) {
case AFE_PORT_ID_MULTICHAN_HDMI_RX:
case AFE_PORT_ID_HDMI_OVER_DP_RX:
cfg_type = AFE_PARAM_ID_HDMI_CONFIG;
break;
case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_TX:
case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_TX:
case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_TX:
case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_TX:
case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_TX:
case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_TX:
case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_TX:
case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_RX:
case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_RX:
case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_RX:
case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_RX:
case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_RX:
case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_RX:
case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_RX:
cfg_type = AFE_PARAM_ID_SLIMBUS_CONFIG;
break;
case AFE_PORT_ID_PRIMARY_MI2S_RX:
case AFE_PORT_ID_PRIMARY_MI2S_TX:
case AFE_PORT_ID_SECONDARY_MI2S_RX:
case AFE_PORT_ID_SECONDARY_MI2S_TX:
case AFE_PORT_ID_TERTIARY_MI2S_RX:
case AFE_PORT_ID_TERTIARY_MI2S_TX:
case AFE_PORT_ID_QUATERNARY_MI2S_RX:
case AFE_PORT_ID_QUATERNARY_MI2S_TX:
case AFE_PORT_ID_QUINARY_MI2S_RX:
case AFE_PORT_ID_QUINARY_MI2S_TX:
cfg_type = AFE_PARAM_ID_I2S_CONFIG;
break;
case AFE_PORT_ID_PRIMARY_TDM_RX ... AFE_PORT_ID_QUINARY_TDM_TX_7:
cfg_type = AFE_PARAM_ID_TDM_CONFIG;
break;
case AFE_PORT_ID_WSA_CODEC_DMA_RX_0 ... AFE_PORT_ID_RX_CODEC_DMA_RX_7:
cfg_type = AFE_PARAM_ID_CODEC_DMA_CONFIG;
break;
default:
dev_err(dev, "Invalid port id 0x%x\n", port_id);
return ERR_PTR(-EINVAL);
}
port = kzalloc(sizeof(*port), GFP_KERNEL);
if (!port)
return ERR_PTR(-ENOMEM);
init_waitqueue_head(&port->wait);
port->token = id;
port->id = port_id;
port->afe = afe;
port->cfg_type = cfg_type;
kref_init(&port->refcount);
spin_lock_irqsave(&afe->port_list_lock, flags);
list_add_tail(&port->node, &afe->port_list);
spin_unlock_irqrestore(&afe->port_list_lock, flags);
return port;
}
EXPORT_SYMBOL_GPL(q6afe_port_get_from_id);
/**
* q6afe_port_put() - Release port reference
*
* @port: Instance of port to put
*/
void q6afe_port_put(struct q6afe_port *port)
{
kref_put(&port->refcount, q6afe_port_free);
}
EXPORT_SYMBOL_GPL(q6afe_port_put);
int q6afe_unvote_lpass_core_hw(struct device *dev, uint32_t hw_block_id,
uint32_t client_handle)
{
struct q6afe *afe = dev_get_drvdata(dev->parent);
struct afe_cmd_remote_lpass_core_hw_devote_request *vote_cfg;
struct apr_pkt *pkt;
int ret = 0;
int pkt_size;
void *p;
pkt_size = APR_HDR_SIZE + sizeof(*vote_cfg);
p = kzalloc(pkt_size, GFP_KERNEL);
if (!p)
return -ENOMEM;
pkt = p;
vote_cfg = p + APR_HDR_SIZE;
pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD,
APR_HDR_LEN(APR_HDR_SIZE),
APR_PKT_VER);
pkt->hdr.pkt_size = pkt_size;
pkt->hdr.src_port = 0;
pkt->hdr.dest_port = 0;
pkt->hdr.token = hw_block_id;
pkt->hdr.opcode = AFE_CMD_REMOTE_LPASS_CORE_HW_DEVOTE_REQUEST;
vote_cfg->hw_block_id = hw_block_id;
vote_cfg->client_handle = client_handle;
ret = apr_send_pkt(afe->apr, pkt);
if (ret < 0)
dev_err(afe->dev, "AFE failed to unvote (%d)\n", hw_block_id);
kfree(pkt);
return ret;
}
EXPORT_SYMBOL(q6afe_unvote_lpass_core_hw);
int q6afe_vote_lpass_core_hw(struct device *dev, uint32_t hw_block_id,
const char *client_name, uint32_t *client_handle)
{
struct q6afe *afe = dev_get_drvdata(dev->parent);
struct afe_cmd_remote_lpass_core_hw_vote_request *vote_cfg;
struct apr_pkt *pkt;
int ret = 0;
int pkt_size;
void *p;
pkt_size = APR_HDR_SIZE + sizeof(*vote_cfg);
p = kzalloc(pkt_size, GFP_KERNEL);
if (!p)
return -ENOMEM;
pkt = p;
vote_cfg = p + APR_HDR_SIZE;
pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD,
APR_HDR_LEN(APR_HDR_SIZE),
APR_PKT_VER);
pkt->hdr.pkt_size = pkt_size;
pkt->hdr.src_port = 0;
pkt->hdr.dest_port = 0;
pkt->hdr.token = hw_block_id;
pkt->hdr.opcode = AFE_CMD_REMOTE_LPASS_CORE_HW_VOTE_REQUEST;
vote_cfg->hw_block_id = hw_block_id;
strscpy(vote_cfg->client_name, client_name,
sizeof(vote_cfg->client_name));
ret = afe_apr_send_pkt(afe, pkt, NULL,
AFE_CMD_RSP_REMOTE_LPASS_CORE_HW_VOTE_REQUEST);
if (ret)
dev_err(afe->dev, "AFE failed to vote (%d)\n", hw_block_id);
kfree(pkt);
return ret;
}
EXPORT_SYMBOL(q6afe_vote_lpass_core_hw);
static int q6afe_probe(struct apr_device *adev)
{
struct q6afe *afe;
struct device *dev = &adev->dev;
afe = devm_kzalloc(dev, sizeof(*afe), GFP_KERNEL);
if (!afe)
return -ENOMEM;
q6core_get_svc_api_info(adev->svc_id, &afe->ainfo);
afe->apr = adev;
mutex_init(&afe->lock);
init_waitqueue_head(&afe->wait);
afe->dev = dev;
INIT_LIST_HEAD(&afe->port_list);
spin_lock_init(&afe->port_list_lock);
dev_set_drvdata(dev, afe);
return devm_of_platform_populate(dev);
}
#ifdef CONFIG_OF
static const struct of_device_id q6afe_device_id[] = {
{ .compatible = "qcom,q6afe" },
{},
};
MODULE_DEVICE_TABLE(of, q6afe_device_id);
#endif
static struct apr_driver qcom_q6afe_driver = {
.probe = q6afe_probe,
.callback = q6afe_callback,
.driver = {
.name = "qcom-q6afe",
.of_match_table = of_match_ptr(q6afe_device_id),
},
};
module_apr_driver(qcom_q6afe_driver);
MODULE_DESCRIPTION("Q6 Audio Front End");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/qcom/qdsp6/q6afe.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2011-2017, The Linux Foundation. All rights reserved.
// Copyright (c) 2018, Linaro Limited
#include "q6dsp-common.h"
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/errno.h>
int q6dsp_map_channels(u8 ch_map[PCM_MAX_NUM_CHANNEL], int ch)
{
memset(ch_map, 0, PCM_MAX_NUM_CHANNEL);
switch (ch) {
case 1:
ch_map[0] = PCM_CHANNEL_FC;
break;
case 2:
ch_map[0] = PCM_CHANNEL_FL;
ch_map[1] = PCM_CHANNEL_FR;
break;
case 3:
ch_map[0] = PCM_CHANNEL_FL;
ch_map[1] = PCM_CHANNEL_FR;
ch_map[2] = PCM_CHANNEL_FC;
break;
case 4:
ch_map[0] = PCM_CHANNEL_FL;
ch_map[1] = PCM_CHANNEL_FR;
ch_map[2] = PCM_CHANNEL_LS;
ch_map[3] = PCM_CHANNEL_RS;
break;
case 5:
ch_map[0] = PCM_CHANNEL_FL;
ch_map[1] = PCM_CHANNEL_FR;
ch_map[2] = PCM_CHANNEL_FC;
ch_map[3] = PCM_CHANNEL_LS;
ch_map[4] = PCM_CHANNEL_RS;
break;
case 6:
ch_map[0] = PCM_CHANNEL_FL;
ch_map[1] = PCM_CHANNEL_FR;
ch_map[2] = PCM_CHANNEL_LFE;
ch_map[3] = PCM_CHANNEL_FC;
ch_map[4] = PCM_CHANNEL_LS;
ch_map[5] = PCM_CHANNEL_RS;
break;
case 8:
ch_map[0] = PCM_CHANNEL_FL;
ch_map[1] = PCM_CHANNEL_FR;
ch_map[2] = PCM_CHANNEL_LFE;
ch_map[3] = PCM_CHANNEL_FC;
ch_map[4] = PCM_CHANNEL_LS;
ch_map[5] = PCM_CHANNEL_RS;
ch_map[6] = PCM_CHANNEL_LB;
ch_map[7] = PCM_CHANNEL_RB;
break;
default:
return -EINVAL;
}
return 0;
}
EXPORT_SYMBOL_GPL(q6dsp_map_channels);
int q6dsp_get_channel_allocation(int channels)
{
int channel_allocation;
/* HDMI spec CEA-861-E: Table 28 Audio InfoFrame Data Byte 4 */
switch (channels) {
case 2:
channel_allocation = 0;
break;
case 3:
channel_allocation = 0x02;
break;
case 4:
channel_allocation = 0x06;
break;
case 5:
channel_allocation = 0x0A;
break;
case 6:
channel_allocation = 0x0B;
break;
case 7:
channel_allocation = 0x12;
break;
case 8:
channel_allocation = 0x13;
break;
default:
return -EINVAL;
}
return channel_allocation;
}
EXPORT_SYMBOL_GPL(q6dsp_get_channel_allocation);
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/qcom/qdsp6/q6dsp-common.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2021, Linaro Limited
#include <linux/slab.h>
#include <linux/wait.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/delay.h>
#include <linux/of_platform.h>
#include <linux/jiffies.h>
#include <linux/soc/qcom/apr.h>
#include <dt-bindings/soc/qcom,gpr.h>
#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
#include "q6apm.h"
#include "q6prm.h"
#include "audioreach.h"
struct q6prm {
struct device *dev;
gpr_device_t *gdev;
wait_queue_head_t wait;
struct gpr_ibasic_rsp_result_t result;
struct mutex lock;
};
#define PRM_CMD_REQUEST_HW_RSC 0x0100100F
#define PRM_CMD_RSP_REQUEST_HW_RSC 0x02001002
#define PRM_CMD_RELEASE_HW_RSC 0x01001010
#define PRM_CMD_RSP_RELEASE_HW_RSC 0x02001003
#define PARAM_ID_RSC_HW_CORE 0x08001032
#define PARAM_ID_RSC_LPASS_CORE 0x0800102B
#define PARAM_ID_RSC_AUDIO_HW_CLK 0x0800102C
struct prm_cmd_request_hw_core {
struct apm_module_param_data param_data;
uint32_t hw_clk_id;
} __packed;
struct prm_cmd_request_rsc {
struct apm_module_param_data param_data;
uint32_t num_clk_id;
struct audio_hw_clk_cfg clock_id;
} __packed;
struct prm_cmd_release_rsc {
struct apm_module_param_data param_data;
uint32_t num_clk_id;
struct audio_hw_clk_rel_cfg clock_id;
} __packed;
static int q6prm_send_cmd_sync(struct q6prm *prm, struct gpr_pkt *pkt, uint32_t rsp_opcode)
{
return audioreach_send_cmd_sync(prm->dev, prm->gdev, &prm->result, &prm->lock,
NULL, &prm->wait, pkt, rsp_opcode);
}
static int q6prm_set_hw_core_req(struct device *dev, uint32_t hw_block_id, bool enable)
{
struct q6prm *prm = dev_get_drvdata(dev->parent);
struct apm_module_param_data *param_data;
struct prm_cmd_request_hw_core *req;
gpr_device_t *gdev = prm->gdev;
uint32_t opcode, rsp_opcode;
struct gpr_pkt *pkt;
int rc;
if (enable) {
opcode = PRM_CMD_REQUEST_HW_RSC;
rsp_opcode = PRM_CMD_RSP_REQUEST_HW_RSC;
} else {
opcode = PRM_CMD_RELEASE_HW_RSC;
rsp_opcode = PRM_CMD_RSP_RELEASE_HW_RSC;
}
pkt = audioreach_alloc_cmd_pkt(sizeof(*req), opcode, 0, gdev->svc.id, GPR_PRM_MODULE_IID);
if (IS_ERR(pkt))
return PTR_ERR(pkt);
req = (void *)pkt + GPR_HDR_SIZE + APM_CMD_HDR_SIZE;
param_data = &req->param_data;
param_data->module_instance_id = GPR_PRM_MODULE_IID;
param_data->error_code = 0;
param_data->param_id = PARAM_ID_RSC_HW_CORE;
param_data->param_size = sizeof(*req) - APM_MODULE_PARAM_DATA_SIZE;
req->hw_clk_id = hw_block_id;
rc = q6prm_send_cmd_sync(prm, pkt, rsp_opcode);
kfree(pkt);
return rc;
}
int q6prm_vote_lpass_core_hw(struct device *dev, uint32_t hw_block_id,
const char *client_name, uint32_t *client_handle)
{
return q6prm_set_hw_core_req(dev, hw_block_id, true);
}
EXPORT_SYMBOL_GPL(q6prm_vote_lpass_core_hw);
int q6prm_unvote_lpass_core_hw(struct device *dev, uint32_t hw_block_id, uint32_t client_handle)
{
return q6prm_set_hw_core_req(dev, hw_block_id, false);
}
EXPORT_SYMBOL_GPL(q6prm_unvote_lpass_core_hw);
static int q6prm_request_lpass_clock(struct device *dev, int clk_id, int clk_attr, int clk_root,
unsigned int freq)
{
struct q6prm *prm = dev_get_drvdata(dev->parent);
struct apm_module_param_data *param_data;
struct prm_cmd_request_rsc *req;
gpr_device_t *gdev = prm->gdev;
struct gpr_pkt *pkt;
int rc;
pkt = audioreach_alloc_cmd_pkt(sizeof(*req), PRM_CMD_REQUEST_HW_RSC, 0, gdev->svc.id,
GPR_PRM_MODULE_IID);
if (IS_ERR(pkt))
return PTR_ERR(pkt);
req = (void *)pkt + GPR_HDR_SIZE + APM_CMD_HDR_SIZE;
param_data = &req->param_data;
param_data->module_instance_id = GPR_PRM_MODULE_IID;
param_data->error_code = 0;
param_data->param_id = PARAM_ID_RSC_AUDIO_HW_CLK;
param_data->param_size = sizeof(*req) - APM_MODULE_PARAM_DATA_SIZE;
req->num_clk_id = 1;
req->clock_id.clock_id = clk_id;
req->clock_id.clock_freq = freq;
req->clock_id.clock_attri = clk_attr;
req->clock_id.clock_root = clk_root;
rc = q6prm_send_cmd_sync(prm, pkt, PRM_CMD_RSP_REQUEST_HW_RSC);
kfree(pkt);
return rc;
}
static int q6prm_release_lpass_clock(struct device *dev, int clk_id, int clk_attr, int clk_root,
unsigned int freq)
{
struct q6prm *prm = dev_get_drvdata(dev->parent);
struct apm_module_param_data *param_data;
struct prm_cmd_release_rsc *rel;
gpr_device_t *gdev = prm->gdev;
struct gpr_pkt *pkt;
int rc;
pkt = audioreach_alloc_cmd_pkt(sizeof(*rel), PRM_CMD_RELEASE_HW_RSC, 0, gdev->svc.id,
GPR_PRM_MODULE_IID);
if (IS_ERR(pkt))
return PTR_ERR(pkt);
rel = (void *)pkt + GPR_HDR_SIZE + APM_CMD_HDR_SIZE;
param_data = &rel->param_data;
param_data->module_instance_id = GPR_PRM_MODULE_IID;
param_data->error_code = 0;
param_data->param_id = PARAM_ID_RSC_AUDIO_HW_CLK;
param_data->param_size = sizeof(*rel) - APM_MODULE_PARAM_DATA_SIZE;
rel->num_clk_id = 1;
rel->clock_id.clock_id = clk_id;
rc = q6prm_send_cmd_sync(prm, pkt, PRM_CMD_RSP_RELEASE_HW_RSC);
kfree(pkt);
return rc;
}
int q6prm_set_lpass_clock(struct device *dev, int clk_id, int clk_attr, int clk_root,
unsigned int freq)
{
if (freq)
return q6prm_request_lpass_clock(dev, clk_id, clk_attr, clk_root, freq);
return q6prm_release_lpass_clock(dev, clk_id, clk_attr, clk_root, freq);
}
EXPORT_SYMBOL_GPL(q6prm_set_lpass_clock);
static int prm_callback(struct gpr_resp_pkt *data, void *priv, int op)
{
gpr_device_t *gdev = priv;
struct q6prm *prm = dev_get_drvdata(&gdev->dev);
struct gpr_ibasic_rsp_result_t *result;
struct gpr_hdr *hdr = &data->hdr;
switch (hdr->opcode) {
case PRM_CMD_RSP_REQUEST_HW_RSC:
case PRM_CMD_RSP_RELEASE_HW_RSC:
result = data->payload;
prm->result.opcode = hdr->opcode;
prm->result.status = result->status;
wake_up(&prm->wait);
break;
default:
break;
}
return 0;
}
static int prm_probe(gpr_device_t *gdev)
{
struct device *dev = &gdev->dev;
struct q6prm *cc;
cc = devm_kzalloc(dev, sizeof(*cc), GFP_KERNEL);
if (!cc)
return -ENOMEM;
cc->dev = dev;
cc->gdev = gdev;
mutex_init(&cc->lock);
init_waitqueue_head(&cc->wait);
dev_set_drvdata(dev, cc);
if (!q6apm_is_adsp_ready())
return -EPROBE_DEFER;
return devm_of_platform_populate(dev);
}
#ifdef CONFIG_OF
static const struct of_device_id prm_device_id[] = {
{ .compatible = "qcom,q6prm" },
{},
};
MODULE_DEVICE_TABLE(of, prm_device_id);
#endif
static gpr_driver_t prm_driver = {
.probe = prm_probe,
.gpr_callback = prm_callback,
.driver = {
.name = "qcom-prm",
.of_match_table = of_match_ptr(prm_device_id),
},
};
module_gpr_driver(prm_driver);
MODULE_DESCRIPTION("Q6 Proxy Resource Manager");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/qcom/qdsp6/q6prm.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2020, Linaro Limited
#include <sound/pcm.h>
#include <sound/soc.h>
#include <sound/pcm_params.h>
#include <dt-bindings/sound/qcom,q6afe.h>
#include "q6dsp-lpass-ports.h"
#define Q6AFE_TDM_PB_DAI(pre, num, did) { \
.playback = { \
.stream_name = pre" TDM"#num" Playback", \
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
SNDRV_PCM_RATE_176400, \
.formats = SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE, \
.channels_min = 1, \
.channels_max = 8, \
.rate_min = 8000, \
.rate_max = 176400, \
}, \
.name = #did, \
.id = did, \
}
#define Q6AFE_TDM_CAP_DAI(pre, num, did) { \
.capture = { \
.stream_name = pre" TDM"#num" Capture", \
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
SNDRV_PCM_RATE_176400, \
.formats = SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE, \
.channels_min = 1, \
.channels_max = 8, \
.rate_min = 8000, \
.rate_max = 176400, \
}, \
.name = #did, \
.id = did, \
}
#define Q6AFE_CDC_DMA_RX_DAI(did) { \
.playback = { \
.stream_name = #did" Playback", \
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
SNDRV_PCM_RATE_176400, \
.formats = SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE, \
.channels_min = 1, \
.channels_max = 8, \
.rate_min = 8000, \
.rate_max = 176400, \
}, \
.name = #did, \
.id = did, \
}
#define Q6AFE_CDC_DMA_TX_DAI(did) { \
.capture = { \
.stream_name = #did" Capture", \
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
SNDRV_PCM_RATE_176400, \
.formats = SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE, \
.channels_min = 1, \
.channels_max = 8, \
.rate_min = 8000, \
.rate_max = 176400, \
}, \
.name = #did, \
.id = did, \
}
#define Q6AFE_DP_RX_DAI(did) { \
.playback = { \
.stream_name = #did" Playback", \
.rates = SNDRV_PCM_RATE_48000 | \
SNDRV_PCM_RATE_96000 | \
SNDRV_PCM_RATE_192000, \
.formats = SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE, \
.channels_min = 2, \
.channels_max = 8, \
.rate_min = 48000, \
.rate_max = 192000, \
}, \
.name = #did, \
.id = did, \
}
static struct snd_soc_dai_driver q6dsp_audio_fe_dais[] = {
{
.playback = {
.stream_name = "HDMI Playback",
.rates = SNDRV_PCM_RATE_48000 |
SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 2,
.channels_max = 8,
.rate_max = 192000,
.rate_min = 48000,
},
.id = HDMI_RX,
.name = "HDMI",
}, {
.name = "SLIMBUS_0_RX",
.id = SLIMBUS_0_RX,
.playback = {
.stream_name = "Slimbus Playback",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 192000,
},
}, {
.name = "SLIMBUS_0_TX",
.id = SLIMBUS_0_TX,
.capture = {
.stream_name = "Slimbus Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 192000,
},
}, {
.playback = {
.stream_name = "Slimbus1 Playback",
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 192000,
},
.name = "SLIMBUS_1_RX",
.id = SLIMBUS_1_RX,
}, {
.name = "SLIMBUS_1_TX",
.id = SLIMBUS_1_TX,
.capture = {
.stream_name = "Slimbus1 Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 192000,
},
}, {
.playback = {
.stream_name = "Slimbus2 Playback",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 192000,
},
.name = "SLIMBUS_2_RX",
.id = SLIMBUS_2_RX,
}, {
.name = "SLIMBUS_2_TX",
.id = SLIMBUS_2_TX,
.capture = {
.stream_name = "Slimbus2 Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 192000,
},
}, {
.playback = {
.stream_name = "Slimbus3 Playback",
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 192000,
},
.name = "SLIMBUS_3_RX",
.id = SLIMBUS_3_RX,
}, {
.name = "SLIMBUS_3_TX",
.id = SLIMBUS_3_TX,
.capture = {
.stream_name = "Slimbus3 Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 192000,
},
}, {
.playback = {
.stream_name = "Slimbus4 Playback",
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 192000,
},
.name = "SLIMBUS_4_RX",
.id = SLIMBUS_4_RX,
}, {
.name = "SLIMBUS_4_TX",
.id = SLIMBUS_4_TX,
.capture = {
.stream_name = "Slimbus4 Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 192000,
},
}, {
.playback = {
.stream_name = "Slimbus5 Playback",
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 192000,
},
.name = "SLIMBUS_5_RX",
.id = SLIMBUS_5_RX,
}, {
.name = "SLIMBUS_5_TX",
.id = SLIMBUS_5_TX,
.capture = {
.stream_name = "Slimbus5 Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 192000,
},
}, {
.playback = {
.stream_name = "Slimbus6 Playback",
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 2,
.rate_min = 8000,
.rate_max = 192000,
},
.name = "SLIMBUS_6_RX",
.id = SLIMBUS_6_RX,
}, {
.name = "SLIMBUS_6_TX",
.id = SLIMBUS_6_TX,
.capture = {
.stream_name = "Slimbus6 Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 192000,
},
}, {
.playback = {
.stream_name = "Primary MI2S Playback",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 48000,
},
.id = PRIMARY_MI2S_RX,
.name = "PRI_MI2S_RX",
}, {
.capture = {
.stream_name = "Primary MI2S Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 48000,
},
.id = PRIMARY_MI2S_TX,
.name = "PRI_MI2S_TX",
}, {
.playback = {
.stream_name = "Secondary MI2S Playback",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 48000,
},
.name = "SEC_MI2S_RX",
.id = SECONDARY_MI2S_RX,
}, {
.capture = {
.stream_name = "Secondary MI2S Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 48000,
},
.id = SECONDARY_MI2S_TX,
.name = "SEC_MI2S_TX",
}, {
.playback = {
.stream_name = "Tertiary MI2S Playback",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 48000,
},
.name = "TERT_MI2S_RX",
.id = TERTIARY_MI2S_RX,
}, {
.capture = {
.stream_name = "Tertiary MI2S Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 48000,
},
.id = TERTIARY_MI2S_TX,
.name = "TERT_MI2S_TX",
}, {
.playback = {
.stream_name = "Quaternary MI2S Playback",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 48000,
},
.name = "QUAT_MI2S_RX",
.id = QUATERNARY_MI2S_RX,
}, {
.capture = {
.stream_name = "Quaternary MI2S Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 48000,
},
.id = QUATERNARY_MI2S_TX,
.name = "QUAT_MI2S_TX",
}, {
.playback = {
.stream_name = "Quinary MI2S Playback",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 192000,
},
.id = QUINARY_MI2S_RX,
.name = "QUIN_MI2S_RX",
}, {
.capture = {
.stream_name = "Quinary MI2S Capture",
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 |
SNDRV_PCM_RATE_16000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.channels_min = 1,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 48000,
},
.id = QUINARY_MI2S_TX,
.name = "QUIN_MI2S_TX",
},
Q6AFE_TDM_PB_DAI("Primary", 0, PRIMARY_TDM_RX_0),
Q6AFE_TDM_PB_DAI("Primary", 1, PRIMARY_TDM_RX_1),
Q6AFE_TDM_PB_DAI("Primary", 2, PRIMARY_TDM_RX_2),
Q6AFE_TDM_PB_DAI("Primary", 3, PRIMARY_TDM_RX_3),
Q6AFE_TDM_PB_DAI("Primary", 4, PRIMARY_TDM_RX_4),
Q6AFE_TDM_PB_DAI("Primary", 5, PRIMARY_TDM_RX_5),
Q6AFE_TDM_PB_DAI("Primary", 6, PRIMARY_TDM_RX_6),
Q6AFE_TDM_PB_DAI("Primary", 7, PRIMARY_TDM_RX_7),
Q6AFE_TDM_CAP_DAI("Primary", 0, PRIMARY_TDM_TX_0),
Q6AFE_TDM_CAP_DAI("Primary", 1, PRIMARY_TDM_TX_1),
Q6AFE_TDM_CAP_DAI("Primary", 2, PRIMARY_TDM_TX_2),
Q6AFE_TDM_CAP_DAI("Primary", 3, PRIMARY_TDM_TX_3),
Q6AFE_TDM_CAP_DAI("Primary", 4, PRIMARY_TDM_TX_4),
Q6AFE_TDM_CAP_DAI("Primary", 5, PRIMARY_TDM_TX_5),
Q6AFE_TDM_CAP_DAI("Primary", 6, PRIMARY_TDM_TX_6),
Q6AFE_TDM_CAP_DAI("Primary", 7, PRIMARY_TDM_TX_7),
Q6AFE_TDM_PB_DAI("Secondary", 0, SECONDARY_TDM_RX_0),
Q6AFE_TDM_PB_DAI("Secondary", 1, SECONDARY_TDM_RX_1),
Q6AFE_TDM_PB_DAI("Secondary", 2, SECONDARY_TDM_RX_2),
Q6AFE_TDM_PB_DAI("Secondary", 3, SECONDARY_TDM_RX_3),
Q6AFE_TDM_PB_DAI("Secondary", 4, SECONDARY_TDM_RX_4),
Q6AFE_TDM_PB_DAI("Secondary", 5, SECONDARY_TDM_RX_5),
Q6AFE_TDM_PB_DAI("Secondary", 6, SECONDARY_TDM_RX_6),
Q6AFE_TDM_PB_DAI("Secondary", 7, SECONDARY_TDM_RX_7),
Q6AFE_TDM_CAP_DAI("Secondary", 0, SECONDARY_TDM_TX_0),
Q6AFE_TDM_CAP_DAI("Secondary", 1, SECONDARY_TDM_TX_1),
Q6AFE_TDM_CAP_DAI("Secondary", 2, SECONDARY_TDM_TX_2),
Q6AFE_TDM_CAP_DAI("Secondary", 3, SECONDARY_TDM_TX_3),
Q6AFE_TDM_CAP_DAI("Secondary", 4, SECONDARY_TDM_TX_4),
Q6AFE_TDM_CAP_DAI("Secondary", 5, SECONDARY_TDM_TX_5),
Q6AFE_TDM_CAP_DAI("Secondary", 6, SECONDARY_TDM_TX_6),
Q6AFE_TDM_CAP_DAI("Secondary", 7, SECONDARY_TDM_TX_7),
Q6AFE_TDM_PB_DAI("Tertiary", 0, TERTIARY_TDM_RX_0),
Q6AFE_TDM_PB_DAI("Tertiary", 1, TERTIARY_TDM_RX_1),
Q6AFE_TDM_PB_DAI("Tertiary", 2, TERTIARY_TDM_RX_2),
Q6AFE_TDM_PB_DAI("Tertiary", 3, TERTIARY_TDM_RX_3),
Q6AFE_TDM_PB_DAI("Tertiary", 4, TERTIARY_TDM_RX_4),
Q6AFE_TDM_PB_DAI("Tertiary", 5, TERTIARY_TDM_RX_5),
Q6AFE_TDM_PB_DAI("Tertiary", 6, TERTIARY_TDM_RX_6),
Q6AFE_TDM_PB_DAI("Tertiary", 7, TERTIARY_TDM_RX_7),
Q6AFE_TDM_CAP_DAI("Tertiary", 0, TERTIARY_TDM_TX_0),
Q6AFE_TDM_CAP_DAI("Tertiary", 1, TERTIARY_TDM_TX_1),
Q6AFE_TDM_CAP_DAI("Tertiary", 2, TERTIARY_TDM_TX_2),
Q6AFE_TDM_CAP_DAI("Tertiary", 3, TERTIARY_TDM_TX_3),
Q6AFE_TDM_CAP_DAI("Tertiary", 4, TERTIARY_TDM_TX_4),
Q6AFE_TDM_CAP_DAI("Tertiary", 5, TERTIARY_TDM_TX_5),
Q6AFE_TDM_CAP_DAI("Tertiary", 6, TERTIARY_TDM_TX_6),
Q6AFE_TDM_CAP_DAI("Tertiary", 7, TERTIARY_TDM_TX_7),
Q6AFE_TDM_PB_DAI("Quaternary", 0, QUATERNARY_TDM_RX_0),
Q6AFE_TDM_PB_DAI("Quaternary", 1, QUATERNARY_TDM_RX_1),
Q6AFE_TDM_PB_DAI("Quaternary", 2, QUATERNARY_TDM_RX_2),
Q6AFE_TDM_PB_DAI("Quaternary", 3, QUATERNARY_TDM_RX_3),
Q6AFE_TDM_PB_DAI("Quaternary", 4, QUATERNARY_TDM_RX_4),
Q6AFE_TDM_PB_DAI("Quaternary", 5, QUATERNARY_TDM_RX_5),
Q6AFE_TDM_PB_DAI("Quaternary", 6, QUATERNARY_TDM_RX_6),
Q6AFE_TDM_PB_DAI("Quaternary", 7, QUATERNARY_TDM_RX_7),
Q6AFE_TDM_CAP_DAI("Quaternary", 0, QUATERNARY_TDM_TX_0),
Q6AFE_TDM_CAP_DAI("Quaternary", 1, QUATERNARY_TDM_TX_1),
Q6AFE_TDM_CAP_DAI("Quaternary", 2, QUATERNARY_TDM_TX_2),
Q6AFE_TDM_CAP_DAI("Quaternary", 3, QUATERNARY_TDM_TX_3),
Q6AFE_TDM_CAP_DAI("Quaternary", 4, QUATERNARY_TDM_TX_4),
Q6AFE_TDM_CAP_DAI("Quaternary", 5, QUATERNARY_TDM_TX_5),
Q6AFE_TDM_CAP_DAI("Quaternary", 6, QUATERNARY_TDM_TX_6),
Q6AFE_TDM_CAP_DAI("Quaternary", 7, QUATERNARY_TDM_TX_7),
Q6AFE_TDM_PB_DAI("Quinary", 0, QUINARY_TDM_RX_0),
Q6AFE_TDM_PB_DAI("Quinary", 1, QUINARY_TDM_RX_1),
Q6AFE_TDM_PB_DAI("Quinary", 2, QUINARY_TDM_RX_2),
Q6AFE_TDM_PB_DAI("Quinary", 3, QUINARY_TDM_RX_3),
Q6AFE_TDM_PB_DAI("Quinary", 4, QUINARY_TDM_RX_4),
Q6AFE_TDM_PB_DAI("Quinary", 5, QUINARY_TDM_RX_5),
Q6AFE_TDM_PB_DAI("Quinary", 6, QUINARY_TDM_RX_6),
Q6AFE_TDM_PB_DAI("Quinary", 7, QUINARY_TDM_RX_7),
Q6AFE_TDM_CAP_DAI("Quinary", 0, QUINARY_TDM_TX_0),
Q6AFE_TDM_CAP_DAI("Quinary", 1, QUINARY_TDM_TX_1),
Q6AFE_TDM_CAP_DAI("Quinary", 2, QUINARY_TDM_TX_2),
Q6AFE_TDM_CAP_DAI("Quinary", 3, QUINARY_TDM_TX_3),
Q6AFE_TDM_CAP_DAI("Quinary", 4, QUINARY_TDM_TX_4),
Q6AFE_TDM_CAP_DAI("Quinary", 5, QUINARY_TDM_TX_5),
Q6AFE_TDM_CAP_DAI("Quinary", 6, QUINARY_TDM_TX_6),
Q6AFE_TDM_CAP_DAI("Quinary", 7, QUINARY_TDM_TX_7),
Q6AFE_DP_RX_DAI(DISPLAY_PORT_RX_0),
Q6AFE_DP_RX_DAI(DISPLAY_PORT_RX_1),
Q6AFE_DP_RX_DAI(DISPLAY_PORT_RX_2),
Q6AFE_DP_RX_DAI(DISPLAY_PORT_RX_3),
Q6AFE_DP_RX_DAI(DISPLAY_PORT_RX_4),
Q6AFE_DP_RX_DAI(DISPLAY_PORT_RX_5),
Q6AFE_DP_RX_DAI(DISPLAY_PORT_RX_6),
Q6AFE_DP_RX_DAI(DISPLAY_PORT_RX_7),
Q6AFE_CDC_DMA_RX_DAI(WSA_CODEC_DMA_RX_0),
Q6AFE_CDC_DMA_TX_DAI(WSA_CODEC_DMA_TX_0),
Q6AFE_CDC_DMA_RX_DAI(WSA_CODEC_DMA_RX_1),
Q6AFE_CDC_DMA_TX_DAI(WSA_CODEC_DMA_TX_1),
Q6AFE_CDC_DMA_TX_DAI(WSA_CODEC_DMA_TX_2),
Q6AFE_CDC_DMA_TX_DAI(VA_CODEC_DMA_TX_0),
Q6AFE_CDC_DMA_TX_DAI(VA_CODEC_DMA_TX_1),
Q6AFE_CDC_DMA_TX_DAI(VA_CODEC_DMA_TX_2),
Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_0),
Q6AFE_CDC_DMA_TX_DAI(TX_CODEC_DMA_TX_0),
Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_1),
Q6AFE_CDC_DMA_TX_DAI(TX_CODEC_DMA_TX_1),
Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_2),
Q6AFE_CDC_DMA_TX_DAI(TX_CODEC_DMA_TX_2),
Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_3),
Q6AFE_CDC_DMA_TX_DAI(TX_CODEC_DMA_TX_3),
Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_4),
Q6AFE_CDC_DMA_TX_DAI(TX_CODEC_DMA_TX_4),
Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_5),
Q6AFE_CDC_DMA_TX_DAI(TX_CODEC_DMA_TX_5),
Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_6),
Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_7),
};
int q6dsp_audio_ports_of_xlate_dai_name(struct snd_soc_component *component,
const struct of_phandle_args *args,
const char **dai_name)
{
int id = args->args[0];
int ret = -EINVAL;
int i;
for (i = 0; i < ARRAY_SIZE(q6dsp_audio_fe_dais); i++) {
if (q6dsp_audio_fe_dais[i].id == id) {
*dai_name = q6dsp_audio_fe_dais[i].name;
ret = 0;
break;
}
}
return ret;
}
EXPORT_SYMBOL_GPL(q6dsp_audio_ports_of_xlate_dai_name);
struct snd_soc_dai_driver *q6dsp_audio_ports_set_config(struct device *dev,
struct q6dsp_audio_port_dai_driver_config *cfg,
int *num_dais)
{
int i;
for (i = 0; i < ARRAY_SIZE(q6dsp_audio_fe_dais); i++) {
switch (q6dsp_audio_fe_dais[i].id) {
case HDMI_RX:
case DISPLAY_PORT_RX:
q6dsp_audio_fe_dais[i].ops = cfg->q6hdmi_ops;
break;
case DISPLAY_PORT_RX_1 ... DISPLAY_PORT_RX_7:
q6dsp_audio_fe_dais[i].ops = cfg->q6hdmi_ops;
break;
case SLIMBUS_0_RX ... SLIMBUS_6_TX:
q6dsp_audio_fe_dais[i].ops = cfg->q6slim_ops;
break;
case QUINARY_MI2S_RX ... QUINARY_MI2S_TX:
case PRIMARY_MI2S_RX ... QUATERNARY_MI2S_TX:
q6dsp_audio_fe_dais[i].ops = cfg->q6i2s_ops;
break;
case PRIMARY_TDM_RX_0 ... QUINARY_TDM_TX_7:
q6dsp_audio_fe_dais[i].ops = cfg->q6tdm_ops;
break;
case WSA_CODEC_DMA_RX_0 ... RX_CODEC_DMA_RX_7:
q6dsp_audio_fe_dais[i].ops = cfg->q6dma_ops;
break;
default:
break;
}
}
*num_dais = ARRAY_SIZE(q6dsp_audio_fe_dais);
return q6dsp_audio_fe_dais;
}
EXPORT_SYMBOL_GPL(q6dsp_audio_ports_set_config);
| linux-master | sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2011-2017, The Linux Foundation. All rights reserved.
// Copyright (c) 2018, Linaro Limited
#include <linux/mutex.h>
#include <linux/wait.h>
#include <linux/module.h>
#include <linux/soc/qcom/apr.h>
#include <linux/device.h>
#include <linux/of_platform.h>
#include <linux/spinlock.h>
#include <linux/kref.h>
#include <linux/of.h>
#include <uapi/sound/asound.h>
#include <uapi/sound/compress_params.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/mm.h>
#include "q6asm.h"
#include "q6core.h"
#include "q6dsp-errno.h"
#include "q6dsp-common.h"
#define ASM_STREAM_CMD_CLOSE 0x00010BCD
#define ASM_STREAM_CMD_FLUSH 0x00010BCE
#define ASM_SESSION_CMD_PAUSE 0x00010BD3
#define ASM_DATA_CMD_EOS 0x00010BDB
#define ASM_DATA_EVENT_RENDERED_EOS 0x00010C1C
#define ASM_NULL_POPP_TOPOLOGY 0x00010C68
#define ASM_STREAM_CMD_FLUSH_READBUFS 0x00010C09
#define ASM_STREAM_CMD_SET_ENCDEC_PARAM 0x00010C10
#define ASM_STREAM_POSTPROC_TOPO_ID_NONE 0x00010C68
#define ASM_CMD_SHARED_MEM_MAP_REGIONS 0x00010D92
#define ASM_CMDRSP_SHARED_MEM_MAP_REGIONS 0x00010D93
#define ASM_CMD_SHARED_MEM_UNMAP_REGIONS 0x00010D94
#define ASM_DATA_CMD_MEDIA_FMT_UPDATE_V2 0x00010D98
#define ASM_DATA_EVENT_WRITE_DONE_V2 0x00010D99
#define ASM_PARAM_ID_ENCDEC_ENC_CFG_BLK_V2 0x00010DA3
#define ASM_SESSION_CMD_RUN_V2 0x00010DAA
#define ASM_MEDIA_FMT_MULTI_CHANNEL_PCM_V2 0x00010DA5
#define ASM_MEDIA_FMT_MP3 0x00010BE9
#define ASM_MEDIA_FMT_FLAC 0x00010C16
#define ASM_MEDIA_FMT_WMA_V9 0x00010DA8
#define ASM_MEDIA_FMT_WMA_V10 0x00010DA7
#define ASM_DATA_CMD_WRITE_V2 0x00010DAB
#define ASM_DATA_CMD_READ_V2 0x00010DAC
#define ASM_SESSION_CMD_SUSPEND 0x00010DEC
#define ASM_STREAM_CMD_OPEN_WRITE_V3 0x00010DB3
#define ASM_STREAM_CMD_OPEN_READ_V3 0x00010DB4
#define ASM_DATA_EVENT_READ_DONE_V2 0x00010D9A
#define ASM_STREAM_CMD_OPEN_READWRITE_V2 0x00010D8D
#define ASM_MEDIA_FMT_ALAC 0x00012f31
#define ASM_MEDIA_FMT_APE 0x00012f32
#define ASM_DATA_CMD_REMOVE_INITIAL_SILENCE 0x00010D67
#define ASM_DATA_CMD_REMOVE_TRAILING_SILENCE 0x00010D68
#define ASM_LEGACY_STREAM_SESSION 0
/* Bit shift for the stream_perf_mode subfield. */
#define ASM_SHIFT_STREAM_PERF_MODE_FLAG_IN_OPEN_READ 29
#define ASM_END_POINT_DEVICE_MATRIX 0
#define ASM_DEFAULT_APP_TYPE 0
#define ASM_SYNC_IO_MODE 0x0001
#define ASM_ASYNC_IO_MODE 0x0002
#define ASM_TUN_READ_IO_MODE 0x0004 /* tunnel read write mode */
#define ASM_TUN_WRITE_IO_MODE 0x0008 /* tunnel read write mode */
#define ASM_SHIFT_GAPLESS_MODE_FLAG 31
#define ADSP_MEMORY_MAP_SHMEM8_4K_POOL 3
struct avs_cmd_shared_mem_map_regions {
u16 mem_pool_id;
u16 num_regions;
u32 property_flag;
} __packed;
struct avs_shared_map_region_payload {
u32 shm_addr_lsw;
u32 shm_addr_msw;
u32 mem_size_bytes;
} __packed;
struct avs_cmd_shared_mem_unmap_regions {
u32 mem_map_handle;
} __packed;
struct asm_data_cmd_media_fmt_update_v2 {
u32 fmt_blk_size;
} __packed;
struct asm_multi_channel_pcm_fmt_blk_v2 {
struct asm_data_cmd_media_fmt_update_v2 fmt_blk;
u16 num_channels;
u16 bits_per_sample;
u32 sample_rate;
u16 is_signed;
u16 reserved;
u8 channel_mapping[PCM_MAX_NUM_CHANNEL];
} __packed;
struct asm_flac_fmt_blk_v2 {
struct asm_data_cmd_media_fmt_update_v2 fmt_blk;
u16 is_stream_info_present;
u16 num_channels;
u16 min_blk_size;
u16 max_blk_size;
u16 md5_sum[8];
u32 sample_rate;
u32 min_frame_size;
u32 max_frame_size;
u16 sample_size;
u16 reserved;
} __packed;
struct asm_wmastdv9_fmt_blk_v2 {
struct asm_data_cmd_media_fmt_update_v2 fmt_blk;
u16 fmtag;
u16 num_channels;
u32 sample_rate;
u32 bytes_per_sec;
u16 blk_align;
u16 bits_per_sample;
u32 channel_mask;
u16 enc_options;
u16 reserved;
} __packed;
struct asm_wmaprov10_fmt_blk_v2 {
struct asm_data_cmd_media_fmt_update_v2 fmt_blk;
u16 fmtag;
u16 num_channels;
u32 sample_rate;
u32 bytes_per_sec;
u16 blk_align;
u16 bits_per_sample;
u32 channel_mask;
u16 enc_options;
u16 advanced_enc_options1;
u32 advanced_enc_options2;
} __packed;
struct asm_alac_fmt_blk_v2 {
struct asm_data_cmd_media_fmt_update_v2 fmt_blk;
u32 frame_length;
u8 compatible_version;
u8 bit_depth;
u8 pb;
u8 mb;
u8 kb;
u8 num_channels;
u16 max_run;
u32 max_frame_bytes;
u32 avg_bit_rate;
u32 sample_rate;
u32 channel_layout_tag;
} __packed;
struct asm_ape_fmt_blk_v2 {
struct asm_data_cmd_media_fmt_update_v2 fmt_blk;
u16 compatible_version;
u16 compression_level;
u32 format_flags;
u32 blocks_per_frame;
u32 final_frame_blocks;
u32 total_frames;
u16 bits_per_sample;
u16 num_channels;
u32 sample_rate;
u32 seek_table_present;
} __packed;
struct asm_stream_cmd_set_encdec_param {
u32 param_id;
u32 param_size;
} __packed;
struct asm_enc_cfg_blk_param_v2 {
u32 frames_per_buf;
u32 enc_cfg_blk_size;
} __packed;
struct asm_multi_channel_pcm_enc_cfg_v2 {
struct asm_stream_cmd_set_encdec_param encdec;
struct asm_enc_cfg_blk_param_v2 encblk;
uint16_t num_channels;
uint16_t bits_per_sample;
uint32_t sample_rate;
uint16_t is_signed;
uint16_t reserved;
uint8_t channel_mapping[8];
} __packed;
struct asm_data_cmd_read_v2 {
u32 buf_addr_lsw;
u32 buf_addr_msw;
u32 mem_map_handle;
u32 buf_size;
u32 seq_id;
} __packed;
struct asm_data_cmd_read_v2_done {
u32 status;
u32 buf_addr_lsw;
u32 buf_addr_msw;
};
struct asm_stream_cmd_open_read_v3 {
u32 mode_flags;
u32 src_endpointype;
u32 preprocopo_id;
u32 enc_cfg_id;
u16 bits_per_sample;
u16 reserved;
} __packed;
struct asm_data_cmd_write_v2 {
u32 buf_addr_lsw;
u32 buf_addr_msw;
u32 mem_map_handle;
u32 buf_size;
u32 seq_id;
u32 timestamp_lsw;
u32 timestamp_msw;
u32 flags;
} __packed;
struct asm_stream_cmd_open_write_v3 {
uint32_t mode_flags;
uint16_t sink_endpointype;
uint16_t bits_per_sample;
uint32_t postprocopo_id;
uint32_t dec_fmt_id;
} __packed;
struct asm_session_cmd_run_v2 {
u32 flags;
u32 time_lsw;
u32 time_msw;
} __packed;
struct audio_buffer {
phys_addr_t phys;
uint32_t size; /* size of buffer */
};
struct audio_port_data {
struct audio_buffer *buf;
uint32_t num_periods;
uint32_t dsp_buf;
uint32_t mem_map_handle;
};
struct q6asm {
struct apr_device *adev;
struct device *dev;
struct q6core_svc_api_info ainfo;
wait_queue_head_t mem_wait;
spinlock_t slock;
struct audio_client *session[MAX_SESSIONS + 1];
};
struct audio_client {
int session;
q6asm_cb cb;
void *priv;
uint32_t io_mode;
struct apr_device *adev;
struct mutex cmd_lock;
spinlock_t lock;
struct kref refcount;
/* idx:1 out port, 0: in port */
struct audio_port_data port[2];
wait_queue_head_t cmd_wait;
struct aprv2_ibasic_rsp_result_t result;
int perf_mode;
struct q6asm *q6asm;
struct device *dev;
};
static inline void q6asm_add_hdr(struct audio_client *ac, struct apr_hdr *hdr,
uint32_t pkt_size, bool cmd_flg,
uint32_t stream_id)
{
hdr->hdr_field = APR_SEQ_CMD_HDR_FIELD;
hdr->src_port = ((ac->session << 8) & 0xFF00) | (stream_id);
hdr->dest_port = ((ac->session << 8) & 0xFF00) | (stream_id);
hdr->pkt_size = pkt_size;
if (cmd_flg)
hdr->token = ac->session;
}
static int q6asm_apr_send_session_pkt(struct q6asm *a, struct audio_client *ac,
struct apr_pkt *pkt, uint32_t rsp_opcode)
{
struct apr_hdr *hdr = &pkt->hdr;
int rc;
mutex_lock(&ac->cmd_lock);
ac->result.opcode = 0;
ac->result.status = 0;
rc = apr_send_pkt(a->adev, pkt);
if (rc < 0)
goto err;
if (rsp_opcode)
rc = wait_event_timeout(a->mem_wait,
(ac->result.opcode == hdr->opcode) ||
(ac->result.opcode == rsp_opcode),
5 * HZ);
else
rc = wait_event_timeout(a->mem_wait,
(ac->result.opcode == hdr->opcode),
5 * HZ);
if (!rc) {
dev_err(a->dev, "CMD %x timeout\n", hdr->opcode);
rc = -ETIMEDOUT;
} else if (ac->result.status > 0) {
dev_err(a->dev, "DSP returned error[%x]\n",
ac->result.status);
rc = -EINVAL;
}
err:
mutex_unlock(&ac->cmd_lock);
return rc;
}
static int __q6asm_memory_unmap(struct audio_client *ac,
phys_addr_t buf_add, int dir)
{
struct avs_cmd_shared_mem_unmap_regions *mem_unmap;
struct q6asm *a = dev_get_drvdata(ac->dev->parent);
struct apr_pkt *pkt;
int rc, pkt_size;
void *p;
if (ac->port[dir].mem_map_handle == 0) {
dev_err(ac->dev, "invalid mem handle\n");
return -EINVAL;
}
pkt_size = APR_HDR_SIZE + sizeof(*mem_unmap);
p = kzalloc(pkt_size, GFP_KERNEL);
if (!p)
return -ENOMEM;
pkt = p;
mem_unmap = p + APR_HDR_SIZE;
pkt->hdr.hdr_field = APR_SEQ_CMD_HDR_FIELD;
pkt->hdr.src_port = 0;
pkt->hdr.dest_port = 0;
pkt->hdr.pkt_size = pkt_size;
pkt->hdr.token = ((ac->session << 8) | dir);
pkt->hdr.opcode = ASM_CMD_SHARED_MEM_UNMAP_REGIONS;
mem_unmap->mem_map_handle = ac->port[dir].mem_map_handle;
rc = q6asm_apr_send_session_pkt(a, ac, pkt, 0);
if (rc < 0) {
kfree(pkt);
return rc;
}
ac->port[dir].mem_map_handle = 0;
kfree(pkt);
return 0;
}
static void q6asm_audio_client_free_buf(struct audio_client *ac,
struct audio_port_data *port)
{
unsigned long flags;
spin_lock_irqsave(&ac->lock, flags);
port->num_periods = 0;
kfree(port->buf);
port->buf = NULL;
spin_unlock_irqrestore(&ac->lock, flags);
}
/**
* q6asm_unmap_memory_regions() - unmap memory regions in the dsp.
*
* @dir: direction of audio stream
* @ac: audio client instanace
*
* Return: Will be an negative value on failure or zero on success
*/
int q6asm_unmap_memory_regions(unsigned int dir, struct audio_client *ac)
{
struct audio_port_data *port;
int cnt = 0;
int rc = 0;
port = &ac->port[dir];
if (!port->buf) {
rc = -EINVAL;
goto err;
}
cnt = port->num_periods - 1;
if (cnt >= 0) {
rc = __q6asm_memory_unmap(ac, port->buf[dir].phys, dir);
if (rc < 0) {
dev_err(ac->dev, "%s: Memory_unmap_regions failed %d\n",
__func__, rc);
goto err;
}
}
q6asm_audio_client_free_buf(ac, port);
err:
return rc;
}
EXPORT_SYMBOL_GPL(q6asm_unmap_memory_regions);
static int __q6asm_memory_map_regions(struct audio_client *ac, int dir,
size_t period_sz, unsigned int periods,
bool is_contiguous)
{
struct avs_cmd_shared_mem_map_regions *cmd = NULL;
struct avs_shared_map_region_payload *mregions = NULL;
struct q6asm *a = dev_get_drvdata(ac->dev->parent);
struct audio_port_data *port = NULL;
struct audio_buffer *ab = NULL;
struct apr_pkt *pkt;
void *p;
unsigned long flags;
uint32_t num_regions, buf_sz;
int rc, i, pkt_size;
if (is_contiguous) {
num_regions = 1;
buf_sz = period_sz * periods;
} else {
buf_sz = period_sz;
num_regions = periods;
}
/* DSP expects size should be aligned to 4K */
buf_sz = ALIGN(buf_sz, 4096);
pkt_size = APR_HDR_SIZE + sizeof(*cmd) +
(sizeof(*mregions) * num_regions);
p = kzalloc(pkt_size, GFP_KERNEL);
if (!p)
return -ENOMEM;
pkt = p;
cmd = p + APR_HDR_SIZE;
mregions = p + APR_HDR_SIZE + sizeof(*cmd);
pkt->hdr.hdr_field = APR_SEQ_CMD_HDR_FIELD;
pkt->hdr.src_port = 0;
pkt->hdr.dest_port = 0;
pkt->hdr.pkt_size = pkt_size;
pkt->hdr.token = ((ac->session << 8) | dir);
pkt->hdr.opcode = ASM_CMD_SHARED_MEM_MAP_REGIONS;
cmd->mem_pool_id = ADSP_MEMORY_MAP_SHMEM8_4K_POOL;
cmd->num_regions = num_regions;
cmd->property_flag = 0x00;
spin_lock_irqsave(&ac->lock, flags);
port = &ac->port[dir];
for (i = 0; i < num_regions; i++) {
ab = &port->buf[i];
mregions->shm_addr_lsw = lower_32_bits(ab->phys);
mregions->shm_addr_msw = upper_32_bits(ab->phys);
mregions->mem_size_bytes = buf_sz;
++mregions;
}
spin_unlock_irqrestore(&ac->lock, flags);
rc = q6asm_apr_send_session_pkt(a, ac, pkt,
ASM_CMDRSP_SHARED_MEM_MAP_REGIONS);
kfree(pkt);
return rc;
}
/**
* q6asm_map_memory_regions() - map memory regions in the dsp.
*
* @dir: direction of audio stream
* @ac: audio client instanace
* @phys: physical address that needs mapping.
* @period_sz: audio period size
* @periods: number of periods
*
* Return: Will be an negative value on failure or zero on success
*/
int q6asm_map_memory_regions(unsigned int dir, struct audio_client *ac,
phys_addr_t phys,
size_t period_sz, unsigned int periods)
{
struct audio_buffer *buf;
unsigned long flags;
int cnt;
int rc;
spin_lock_irqsave(&ac->lock, flags);
if (ac->port[dir].buf) {
dev_err(ac->dev, "Buffer already allocated\n");
spin_unlock_irqrestore(&ac->lock, flags);
return 0;
}
buf = kcalloc(periods, sizeof(*buf), GFP_ATOMIC);
if (!buf) {
spin_unlock_irqrestore(&ac->lock, flags);
return -ENOMEM;
}
ac->port[dir].buf = buf;
buf[0].phys = phys;
buf[0].size = period_sz;
for (cnt = 1; cnt < periods; cnt++) {
if (period_sz > 0) {
buf[cnt].phys = buf[0].phys + (cnt * period_sz);
buf[cnt].size = period_sz;
}
}
ac->port[dir].num_periods = periods;
spin_unlock_irqrestore(&ac->lock, flags);
rc = __q6asm_memory_map_regions(ac, dir, period_sz, periods, 1);
if (rc < 0) {
dev_err(ac->dev, "Memory_map_regions failed\n");
q6asm_audio_client_free_buf(ac, &ac->port[dir]);
}
return rc;
}
EXPORT_SYMBOL_GPL(q6asm_map_memory_regions);
static void q6asm_audio_client_release(struct kref *ref)
{
struct audio_client *ac;
struct q6asm *a;
unsigned long flags;
ac = container_of(ref, struct audio_client, refcount);
a = ac->q6asm;
spin_lock_irqsave(&a->slock, flags);
a->session[ac->session] = NULL;
spin_unlock_irqrestore(&a->slock, flags);
kfree(ac);
}
/**
* q6asm_audio_client_free() - Freee allocated audio client
*
* @ac: audio client to free
*/
void q6asm_audio_client_free(struct audio_client *ac)
{
kref_put(&ac->refcount, q6asm_audio_client_release);
}
EXPORT_SYMBOL_GPL(q6asm_audio_client_free);
static struct audio_client *q6asm_get_audio_client(struct q6asm *a,
int session_id)
{
struct audio_client *ac = NULL;
unsigned long flags;
spin_lock_irqsave(&a->slock, flags);
if ((session_id <= 0) || (session_id > MAX_SESSIONS)) {
dev_err(a->dev, "invalid session: %d\n", session_id);
goto err;
}
/* check for valid session */
if (!a->session[session_id])
goto err;
else if (a->session[session_id]->session != session_id)
goto err;
ac = a->session[session_id];
kref_get(&ac->refcount);
err:
spin_unlock_irqrestore(&a->slock, flags);
return ac;
}
static int32_t q6asm_stream_callback(struct apr_device *adev,
struct apr_resp_pkt *data,
int session_id)
{
struct q6asm *q6asm = dev_get_drvdata(&adev->dev);
struct aprv2_ibasic_rsp_result_t *result;
struct apr_hdr *hdr = &data->hdr;
struct audio_port_data *port;
struct audio_client *ac;
uint32_t client_event = 0;
int ret = 0;
ac = q6asm_get_audio_client(q6asm, session_id);
if (!ac)/* Audio client might already be freed by now */
return 0;
result = data->payload;
switch (hdr->opcode) {
case APR_BASIC_RSP_RESULT:
switch (result->opcode) {
case ASM_SESSION_CMD_PAUSE:
client_event = ASM_CLIENT_EVENT_CMD_PAUSE_DONE;
break;
case ASM_SESSION_CMD_SUSPEND:
client_event = ASM_CLIENT_EVENT_CMD_SUSPEND_DONE;
break;
case ASM_STREAM_CMD_FLUSH:
client_event = ASM_CLIENT_EVENT_CMD_FLUSH_DONE;
break;
case ASM_SESSION_CMD_RUN_V2:
client_event = ASM_CLIENT_EVENT_CMD_RUN_DONE;
break;
case ASM_STREAM_CMD_CLOSE:
client_event = ASM_CLIENT_EVENT_CMD_CLOSE_DONE;
break;
case ASM_STREAM_CMD_FLUSH_READBUFS:
client_event = ASM_CLIENT_EVENT_CMD_OUT_FLUSH_DONE;
break;
case ASM_STREAM_CMD_OPEN_WRITE_V3:
case ASM_STREAM_CMD_OPEN_READ_V3:
case ASM_STREAM_CMD_OPEN_READWRITE_V2:
case ASM_STREAM_CMD_SET_ENCDEC_PARAM:
case ASM_DATA_CMD_MEDIA_FMT_UPDATE_V2:
case ASM_DATA_CMD_REMOVE_INITIAL_SILENCE:
case ASM_DATA_CMD_REMOVE_TRAILING_SILENCE:
if (result->status != 0) {
dev_err(ac->dev,
"cmd = 0x%x returned error = 0x%x\n",
result->opcode, result->status);
ac->result = *result;
wake_up(&ac->cmd_wait);
ret = 0;
goto done;
}
break;
default:
dev_err(ac->dev, "command[0x%x] not expecting rsp\n",
result->opcode);
break;
}
ac->result = *result;
wake_up(&ac->cmd_wait);
if (ac->cb)
ac->cb(client_event, hdr->token,
data->payload, ac->priv);
ret = 0;
goto done;
case ASM_DATA_EVENT_WRITE_DONE_V2:
client_event = ASM_CLIENT_EVENT_DATA_WRITE_DONE;
if (ac->io_mode & ASM_SYNC_IO_MODE) {
phys_addr_t phys;
unsigned long flags;
int token = hdr->token & ASM_WRITE_TOKEN_MASK;
spin_lock_irqsave(&ac->lock, flags);
port = &ac->port[SNDRV_PCM_STREAM_PLAYBACK];
if (!port->buf) {
spin_unlock_irqrestore(&ac->lock, flags);
ret = 0;
goto done;
}
phys = port->buf[token].phys;
if (lower_32_bits(phys) != result->opcode ||
upper_32_bits(phys) != result->status) {
dev_err(ac->dev, "Expected addr %pa\n",
&port->buf[token].phys);
spin_unlock_irqrestore(&ac->lock, flags);
ret = -EINVAL;
goto done;
}
spin_unlock_irqrestore(&ac->lock, flags);
}
break;
case ASM_DATA_EVENT_READ_DONE_V2:
client_event = ASM_CLIENT_EVENT_DATA_READ_DONE;
if (ac->io_mode & ASM_SYNC_IO_MODE) {
struct asm_data_cmd_read_v2_done *done = data->payload;
unsigned long flags;
phys_addr_t phys;
spin_lock_irqsave(&ac->lock, flags);
port = &ac->port[SNDRV_PCM_STREAM_CAPTURE];
if (!port->buf) {
spin_unlock_irqrestore(&ac->lock, flags);
ret = 0;
goto done;
}
phys = port->buf[hdr->token].phys;
if (upper_32_bits(phys) != done->buf_addr_msw ||
lower_32_bits(phys) != done->buf_addr_lsw) {
dev_err(ac->dev, "Expected addr %pa %08x-%08x\n",
&port->buf[hdr->token].phys,
done->buf_addr_lsw,
done->buf_addr_msw);
spin_unlock_irqrestore(&ac->lock, flags);
ret = -EINVAL;
goto done;
}
spin_unlock_irqrestore(&ac->lock, flags);
}
break;
case ASM_DATA_EVENT_RENDERED_EOS:
client_event = ASM_CLIENT_EVENT_CMD_EOS_DONE;
break;
}
if (ac->cb)
ac->cb(client_event, hdr->token, data->payload, ac->priv);
done:
kref_put(&ac->refcount, q6asm_audio_client_release);
return ret;
}
static int q6asm_srvc_callback(struct apr_device *adev,
struct apr_resp_pkt *data)
{
struct q6asm *q6asm = dev_get_drvdata(&adev->dev);
struct aprv2_ibasic_rsp_result_t *result;
struct audio_port_data *port;
struct audio_client *ac = NULL;
struct apr_hdr *hdr = &data->hdr;
struct q6asm *a;
uint32_t sid = 0;
uint32_t dir = 0;
int session_id;
session_id = (hdr->dest_port >> 8) & 0xFF;
if (session_id)
return q6asm_stream_callback(adev, data, session_id);
sid = (hdr->token >> 8) & 0x0F;
ac = q6asm_get_audio_client(q6asm, sid);
if (!ac) {
dev_err(&adev->dev, "Audio Client not active\n");
return 0;
}
a = dev_get_drvdata(ac->dev->parent);
dir = (hdr->token & 0x0F);
port = &ac->port[dir];
result = data->payload;
switch (hdr->opcode) {
case APR_BASIC_RSP_RESULT:
switch (result->opcode) {
case ASM_CMD_SHARED_MEM_MAP_REGIONS:
case ASM_CMD_SHARED_MEM_UNMAP_REGIONS:
ac->result = *result;
wake_up(&a->mem_wait);
break;
default:
dev_err(&adev->dev, "command[0x%x] not expecting rsp\n",
result->opcode);
break;
}
goto done;
case ASM_CMDRSP_SHARED_MEM_MAP_REGIONS:
ac->result.status = 0;
ac->result.opcode = hdr->opcode;
port->mem_map_handle = result->opcode;
wake_up(&a->mem_wait);
break;
case ASM_CMD_SHARED_MEM_UNMAP_REGIONS:
ac->result.opcode = hdr->opcode;
ac->result.status = 0;
port->mem_map_handle = 0;
wake_up(&a->mem_wait);
break;
default:
dev_dbg(&adev->dev, "command[0x%x]success [0x%x]\n",
result->opcode, result->status);
break;
}
if (ac->cb)
ac->cb(hdr->opcode, hdr->token, data->payload, ac->priv);
done:
kref_put(&ac->refcount, q6asm_audio_client_release);
return 0;
}
/**
* q6asm_get_session_id() - get session id for audio client
*
* @c: audio client pointer
*
* Return: Will be an session id of the audio client.
*/
int q6asm_get_session_id(struct audio_client *c)
{
return c->session;
}
EXPORT_SYMBOL_GPL(q6asm_get_session_id);
/**
* q6asm_audio_client_alloc() - Allocate a new audio client
*
* @dev: Pointer to asm child device.
* @cb: event callback.
* @priv: private data associated with this client.
* @session_id: session id
* @perf_mode: performace mode for this client
*
* Return: Will be an error pointer on error or a valid audio client
* on success.
*/
struct audio_client *q6asm_audio_client_alloc(struct device *dev, q6asm_cb cb,
void *priv, int session_id,
int perf_mode)
{
struct q6asm *a = dev_get_drvdata(dev->parent);
struct audio_client *ac;
unsigned long flags;
ac = q6asm_get_audio_client(a, session_id + 1);
if (ac) {
dev_err(dev, "Audio Client already active\n");
return ac;
}
ac = kzalloc(sizeof(*ac), GFP_KERNEL);
if (!ac)
return ERR_PTR(-ENOMEM);
spin_lock_irqsave(&a->slock, flags);
a->session[session_id + 1] = ac;
spin_unlock_irqrestore(&a->slock, flags);
ac->session = session_id + 1;
ac->cb = cb;
ac->dev = dev;
ac->q6asm = a;
ac->priv = priv;
ac->io_mode = ASM_SYNC_IO_MODE;
ac->perf_mode = perf_mode;
ac->adev = a->adev;
kref_init(&ac->refcount);
init_waitqueue_head(&ac->cmd_wait);
mutex_init(&ac->cmd_lock);
spin_lock_init(&ac->lock);
return ac;
}
EXPORT_SYMBOL_GPL(q6asm_audio_client_alloc);
static int q6asm_ac_send_cmd_sync(struct audio_client *ac, struct apr_pkt *pkt)
{
struct apr_hdr *hdr = &pkt->hdr;
int rc;
mutex_lock(&ac->cmd_lock);
ac->result.opcode = 0;
ac->result.status = 0;
rc = apr_send_pkt(ac->adev, pkt);
if (rc < 0)
goto err;
rc = wait_event_timeout(ac->cmd_wait,
(ac->result.opcode == hdr->opcode), 5 * HZ);
if (!rc) {
dev_err(ac->dev, "CMD %x timeout\n", hdr->opcode);
rc = -ETIMEDOUT;
goto err;
}
if (ac->result.status > 0) {
dev_err(ac->dev, "DSP returned error[%x]\n",
ac->result.status);
rc = -EINVAL;
} else {
rc = 0;
}
err:
mutex_unlock(&ac->cmd_lock);
return rc;
}
/**
* q6asm_open_write() - Open audio client for writing
* @ac: audio client pointer
* @stream_id: stream id of q6asm session
* @format: audio sample format
* @codec_profile: compressed format profile
* @bits_per_sample: bits per sample
* @is_gapless: flag to indicate if this is a gapless stream
*
* Return: Will be an negative value on error or zero on success
*/
int q6asm_open_write(struct audio_client *ac, uint32_t stream_id,
uint32_t format, u32 codec_profile,
uint16_t bits_per_sample, bool is_gapless)
{
struct asm_stream_cmd_open_write_v3 *open;
struct apr_pkt *pkt;
void *p;
int rc, pkt_size;
pkt_size = APR_HDR_SIZE + sizeof(*open);
p = kzalloc(pkt_size, GFP_KERNEL);
if (!p)
return -ENOMEM;
pkt = p;
open = p + APR_HDR_SIZE;
q6asm_add_hdr(ac, &pkt->hdr, pkt_size, true, stream_id);
pkt->hdr.opcode = ASM_STREAM_CMD_OPEN_WRITE_V3;
open->mode_flags = 0x00;
open->mode_flags |= ASM_LEGACY_STREAM_SESSION;
if (is_gapless)
open->mode_flags |= BIT(ASM_SHIFT_GAPLESS_MODE_FLAG);
/* source endpoint : matrix */
open->sink_endpointype = ASM_END_POINT_DEVICE_MATRIX;
open->bits_per_sample = bits_per_sample;
open->postprocopo_id = ASM_NULL_POPP_TOPOLOGY;
switch (format) {
case SND_AUDIOCODEC_MP3:
open->dec_fmt_id = ASM_MEDIA_FMT_MP3;
break;
case FORMAT_LINEAR_PCM:
open->dec_fmt_id = ASM_MEDIA_FMT_MULTI_CHANNEL_PCM_V2;
break;
case SND_AUDIOCODEC_FLAC:
open->dec_fmt_id = ASM_MEDIA_FMT_FLAC;
break;
case SND_AUDIOCODEC_WMA:
switch (codec_profile) {
case SND_AUDIOPROFILE_WMA9:
open->dec_fmt_id = ASM_MEDIA_FMT_WMA_V9;
break;
case SND_AUDIOPROFILE_WMA10:
case SND_AUDIOPROFILE_WMA9_PRO:
case SND_AUDIOPROFILE_WMA9_LOSSLESS:
case SND_AUDIOPROFILE_WMA10_LOSSLESS:
open->dec_fmt_id = ASM_MEDIA_FMT_WMA_V10;
break;
default:
dev_err(ac->dev, "Invalid codec profile 0x%x\n",
codec_profile);
rc = -EINVAL;
goto err;
}
break;
case SND_AUDIOCODEC_ALAC:
open->dec_fmt_id = ASM_MEDIA_FMT_ALAC;
break;
case SND_AUDIOCODEC_APE:
open->dec_fmt_id = ASM_MEDIA_FMT_APE;
break;
default:
dev_err(ac->dev, "Invalid format 0x%x\n", format);
rc = -EINVAL;
goto err;
}
rc = q6asm_ac_send_cmd_sync(ac, pkt);
if (rc < 0)
goto err;
ac->io_mode |= ASM_TUN_WRITE_IO_MODE;
err:
kfree(pkt);
return rc;
}
EXPORT_SYMBOL_GPL(q6asm_open_write);
static int __q6asm_run(struct audio_client *ac, uint32_t stream_id,
uint32_t flags, uint32_t msw_ts, uint32_t lsw_ts,
bool wait)
{
struct asm_session_cmd_run_v2 *run;
struct apr_pkt *pkt;
int pkt_size, rc;
void *p;
pkt_size = APR_HDR_SIZE + sizeof(*run);
p = kzalloc(pkt_size, GFP_ATOMIC);
if (!p)
return -ENOMEM;
pkt = p;
run = p + APR_HDR_SIZE;
q6asm_add_hdr(ac, &pkt->hdr, pkt_size, true, stream_id);
pkt->hdr.opcode = ASM_SESSION_CMD_RUN_V2;
run->flags = flags;
run->time_lsw = lsw_ts;
run->time_msw = msw_ts;
if (wait) {
rc = q6asm_ac_send_cmd_sync(ac, pkt);
} else {
rc = apr_send_pkt(ac->adev, pkt);
if (rc == pkt_size)
rc = 0;
}
kfree(pkt);
return rc;
}
/**
* q6asm_run() - start the audio client
*
* @ac: audio client pointer
* @stream_id: stream id of q6asm session
* @flags: flags associated with write
* @msw_ts: timestamp msw
* @lsw_ts: timestamp lsw
*
* Return: Will be an negative value on error or zero on success
*/
int q6asm_run(struct audio_client *ac, uint32_t stream_id, uint32_t flags,
uint32_t msw_ts, uint32_t lsw_ts)
{
return __q6asm_run(ac, stream_id, flags, msw_ts, lsw_ts, true);
}
EXPORT_SYMBOL_GPL(q6asm_run);
/**
* q6asm_run_nowait() - start the audio client withou blocking
*
* @ac: audio client pointer
* @stream_id: stream id
* @flags: flags associated with write
* @msw_ts: timestamp msw
* @lsw_ts: timestamp lsw
*
* Return: Will be an negative value on error or zero on success
*/
int q6asm_run_nowait(struct audio_client *ac, uint32_t stream_id,
uint32_t flags, uint32_t msw_ts, uint32_t lsw_ts)
{
return __q6asm_run(ac, stream_id, flags, msw_ts, lsw_ts, false);
}
EXPORT_SYMBOL_GPL(q6asm_run_nowait);
/**
* q6asm_media_format_block_multi_ch_pcm() - setup pcm configuration
*
* @ac: audio client pointer
* @stream_id: stream id
* @rate: audio sample rate
* @channels: number of audio channels.
* @channel_map: channel map pointer
* @bits_per_sample: bits per sample
*
* Return: Will be an negative value on error or zero on success
*/
int q6asm_media_format_block_multi_ch_pcm(struct audio_client *ac,
uint32_t stream_id,
uint32_t rate, uint32_t channels,
u8 channel_map[PCM_MAX_NUM_CHANNEL],
uint16_t bits_per_sample)
{
struct asm_multi_channel_pcm_fmt_blk_v2 *fmt;
struct apr_pkt *pkt;
u8 *channel_mapping;
void *p;
int rc, pkt_size;
pkt_size = APR_HDR_SIZE + sizeof(*fmt);
p = kzalloc(pkt_size, GFP_KERNEL);
if (!p)
return -ENOMEM;
pkt = p;
fmt = p + APR_HDR_SIZE;
q6asm_add_hdr(ac, &pkt->hdr, pkt_size, true, stream_id);
pkt->hdr.opcode = ASM_DATA_CMD_MEDIA_FMT_UPDATE_V2;
fmt->fmt_blk.fmt_blk_size = sizeof(*fmt) - sizeof(fmt->fmt_blk);
fmt->num_channels = channels;
fmt->bits_per_sample = bits_per_sample;
fmt->sample_rate = rate;
fmt->is_signed = 1;
channel_mapping = fmt->channel_mapping;
if (channel_map) {
memcpy(channel_mapping, channel_map, PCM_MAX_NUM_CHANNEL);
} else {
if (q6dsp_map_channels(channel_mapping, channels)) {
dev_err(ac->dev, " map channels failed %d\n", channels);
rc = -EINVAL;
goto err;
}
}
rc = q6asm_ac_send_cmd_sync(ac, pkt);
err:
kfree(pkt);
return rc;
}
EXPORT_SYMBOL_GPL(q6asm_media_format_block_multi_ch_pcm);
int q6asm_stream_media_format_block_flac(struct audio_client *ac,
uint32_t stream_id,
struct q6asm_flac_cfg *cfg)
{
struct asm_flac_fmt_blk_v2 *fmt;
struct apr_pkt *pkt;
void *p;
int rc, pkt_size;
pkt_size = APR_HDR_SIZE + sizeof(*fmt);
p = kzalloc(pkt_size, GFP_KERNEL);
if (!p)
return -ENOMEM;
pkt = p;
fmt = p + APR_HDR_SIZE;
q6asm_add_hdr(ac, &pkt->hdr, pkt_size, true, stream_id);
pkt->hdr.opcode = ASM_DATA_CMD_MEDIA_FMT_UPDATE_V2;
fmt->fmt_blk.fmt_blk_size = sizeof(*fmt) - sizeof(fmt->fmt_blk);
fmt->is_stream_info_present = cfg->stream_info_present;
fmt->num_channels = cfg->ch_cfg;
fmt->min_blk_size = cfg->min_blk_size;
fmt->max_blk_size = cfg->max_blk_size;
fmt->sample_rate = cfg->sample_rate;
fmt->min_frame_size = cfg->min_frame_size;
fmt->max_frame_size = cfg->max_frame_size;
fmt->sample_size = cfg->sample_size;
rc = q6asm_ac_send_cmd_sync(ac, pkt);
kfree(pkt);
return rc;
}
EXPORT_SYMBOL_GPL(q6asm_stream_media_format_block_flac);
int q6asm_stream_media_format_block_wma_v9(struct audio_client *ac,
uint32_t stream_id,
struct q6asm_wma_cfg *cfg)
{
struct asm_wmastdv9_fmt_blk_v2 *fmt;
struct apr_pkt *pkt;
void *p;
int rc, pkt_size;
pkt_size = APR_HDR_SIZE + sizeof(*fmt);
p = kzalloc(pkt_size, GFP_KERNEL);
if (!p)
return -ENOMEM;
pkt = p;
fmt = p + APR_HDR_SIZE;
q6asm_add_hdr(ac, &pkt->hdr, pkt_size, true, stream_id);
pkt->hdr.opcode = ASM_DATA_CMD_MEDIA_FMT_UPDATE_V2;
fmt->fmt_blk.fmt_blk_size = sizeof(*fmt) - sizeof(fmt->fmt_blk);
fmt->fmtag = cfg->fmtag;
fmt->num_channels = cfg->num_channels;
fmt->sample_rate = cfg->sample_rate;
fmt->bytes_per_sec = cfg->bytes_per_sec;
fmt->blk_align = cfg->block_align;
fmt->bits_per_sample = cfg->bits_per_sample;
fmt->channel_mask = cfg->channel_mask;
fmt->enc_options = cfg->enc_options;
fmt->reserved = 0;
rc = q6asm_ac_send_cmd_sync(ac, pkt);
kfree(pkt);
return rc;
}
EXPORT_SYMBOL_GPL(q6asm_stream_media_format_block_wma_v9);
int q6asm_stream_media_format_block_wma_v10(struct audio_client *ac,
uint32_t stream_id,
struct q6asm_wma_cfg *cfg)
{
struct asm_wmaprov10_fmt_blk_v2 *fmt;
struct apr_pkt *pkt;
void *p;
int rc, pkt_size;
pkt_size = APR_HDR_SIZE + sizeof(*fmt);
p = kzalloc(pkt_size, GFP_KERNEL);
if (!p)
return -ENOMEM;
pkt = p;
fmt = p + APR_HDR_SIZE;
q6asm_add_hdr(ac, &pkt->hdr, pkt_size, true, stream_id);
pkt->hdr.opcode = ASM_DATA_CMD_MEDIA_FMT_UPDATE_V2;
fmt->fmt_blk.fmt_blk_size = sizeof(*fmt) - sizeof(fmt->fmt_blk);
fmt->fmtag = cfg->fmtag;
fmt->num_channels = cfg->num_channels;
fmt->sample_rate = cfg->sample_rate;
fmt->bytes_per_sec = cfg->bytes_per_sec;
fmt->blk_align = cfg->block_align;
fmt->bits_per_sample = cfg->bits_per_sample;
fmt->channel_mask = cfg->channel_mask;
fmt->enc_options = cfg->enc_options;
fmt->advanced_enc_options1 = cfg->adv_enc_options;
fmt->advanced_enc_options2 = cfg->adv_enc_options2;
rc = q6asm_ac_send_cmd_sync(ac, pkt);
kfree(pkt);
return rc;
}
EXPORT_SYMBOL_GPL(q6asm_stream_media_format_block_wma_v10);
int q6asm_stream_media_format_block_alac(struct audio_client *ac,
uint32_t stream_id,
struct q6asm_alac_cfg *cfg)
{
struct asm_alac_fmt_blk_v2 *fmt;
struct apr_pkt *pkt;
void *p;
int rc, pkt_size;
pkt_size = APR_HDR_SIZE + sizeof(*fmt);
p = kzalloc(pkt_size, GFP_KERNEL);
if (!p)
return -ENOMEM;
pkt = p;
fmt = p + APR_HDR_SIZE;
q6asm_add_hdr(ac, &pkt->hdr, pkt_size, true, stream_id);
pkt->hdr.opcode = ASM_DATA_CMD_MEDIA_FMT_UPDATE_V2;
fmt->fmt_blk.fmt_blk_size = sizeof(*fmt) - sizeof(fmt->fmt_blk);
fmt->frame_length = cfg->frame_length;
fmt->compatible_version = cfg->compatible_version;
fmt->bit_depth = cfg->bit_depth;
fmt->num_channels = cfg->num_channels;
fmt->max_run = cfg->max_run;
fmt->max_frame_bytes = cfg->max_frame_bytes;
fmt->avg_bit_rate = cfg->avg_bit_rate;
fmt->sample_rate = cfg->sample_rate;
fmt->channel_layout_tag = cfg->channel_layout_tag;
fmt->pb = cfg->pb;
fmt->mb = cfg->mb;
fmt->kb = cfg->kb;
rc = q6asm_ac_send_cmd_sync(ac, pkt);
kfree(pkt);
return rc;
}
EXPORT_SYMBOL_GPL(q6asm_stream_media_format_block_alac);
int q6asm_stream_media_format_block_ape(struct audio_client *ac,
uint32_t stream_id,
struct q6asm_ape_cfg *cfg)
{
struct asm_ape_fmt_blk_v2 *fmt;
struct apr_pkt *pkt;
void *p;
int rc, pkt_size;
pkt_size = APR_HDR_SIZE + sizeof(*fmt);
p = kzalloc(pkt_size, GFP_KERNEL);
if (!p)
return -ENOMEM;
pkt = p;
fmt = p + APR_HDR_SIZE;
q6asm_add_hdr(ac, &pkt->hdr, pkt_size, true, stream_id);
pkt->hdr.opcode = ASM_DATA_CMD_MEDIA_FMT_UPDATE_V2;
fmt->fmt_blk.fmt_blk_size = sizeof(*fmt) - sizeof(fmt->fmt_blk);
fmt->compatible_version = cfg->compatible_version;
fmt->compression_level = cfg->compression_level;
fmt->format_flags = cfg->format_flags;
fmt->blocks_per_frame = cfg->blocks_per_frame;
fmt->final_frame_blocks = cfg->final_frame_blocks;
fmt->total_frames = cfg->total_frames;
fmt->bits_per_sample = cfg->bits_per_sample;
fmt->num_channels = cfg->num_channels;
fmt->sample_rate = cfg->sample_rate;
fmt->seek_table_present = cfg->seek_table_present;
rc = q6asm_ac_send_cmd_sync(ac, pkt);
kfree(pkt);
return rc;
}
EXPORT_SYMBOL_GPL(q6asm_stream_media_format_block_ape);
static int q6asm_stream_remove_silence(struct audio_client *ac, uint32_t stream_id,
uint32_t cmd,
uint32_t num_samples)
{
uint32_t *samples;
struct apr_pkt *pkt;
void *p;
int rc, pkt_size;
pkt_size = APR_HDR_SIZE + sizeof(uint32_t);
p = kzalloc(pkt_size, GFP_ATOMIC);
if (!p)
return -ENOMEM;
pkt = p;
samples = p + APR_HDR_SIZE;
q6asm_add_hdr(ac, &pkt->hdr, pkt_size, true, stream_id);
pkt->hdr.opcode = cmd;
*samples = num_samples;
rc = apr_send_pkt(ac->adev, pkt);
if (rc == pkt_size)
rc = 0;
kfree(pkt);
return rc;
}
int q6asm_stream_remove_initial_silence(struct audio_client *ac,
uint32_t stream_id,
uint32_t initial_samples)
{
return q6asm_stream_remove_silence(ac, stream_id,
ASM_DATA_CMD_REMOVE_INITIAL_SILENCE,
initial_samples);
}
EXPORT_SYMBOL_GPL(q6asm_stream_remove_initial_silence);
int q6asm_stream_remove_trailing_silence(struct audio_client *ac, uint32_t stream_id,
uint32_t trailing_samples)
{
return q6asm_stream_remove_silence(ac, stream_id,
ASM_DATA_CMD_REMOVE_TRAILING_SILENCE,
trailing_samples);
}
EXPORT_SYMBOL_GPL(q6asm_stream_remove_trailing_silence);
/**
* q6asm_enc_cfg_blk_pcm_format_support() - setup pcm configuration for capture
*
* @ac: audio client pointer
* @stream_id: stream id
* @rate: audio sample rate
* @channels: number of audio channels.
* @bits_per_sample: bits per sample
*
* Return: Will be an negative value on error or zero on success
*/
int q6asm_enc_cfg_blk_pcm_format_support(struct audio_client *ac,
uint32_t stream_id, uint32_t rate,
uint32_t channels,
uint16_t bits_per_sample)
{
struct asm_multi_channel_pcm_enc_cfg_v2 *enc_cfg;
struct apr_pkt *pkt;
u8 *channel_mapping;
u32 frames_per_buf = 0;
int pkt_size, rc;
void *p;
pkt_size = APR_HDR_SIZE + sizeof(*enc_cfg);
p = kzalloc(pkt_size, GFP_KERNEL);
if (!p)
return -ENOMEM;
pkt = p;
enc_cfg = p + APR_HDR_SIZE;
q6asm_add_hdr(ac, &pkt->hdr, pkt_size, true, stream_id);
pkt->hdr.opcode = ASM_STREAM_CMD_SET_ENCDEC_PARAM;
enc_cfg->encdec.param_id = ASM_PARAM_ID_ENCDEC_ENC_CFG_BLK_V2;
enc_cfg->encdec.param_size = sizeof(*enc_cfg) - sizeof(enc_cfg->encdec);
enc_cfg->encblk.frames_per_buf = frames_per_buf;
enc_cfg->encblk.enc_cfg_blk_size = enc_cfg->encdec.param_size -
sizeof(struct asm_enc_cfg_blk_param_v2);
enc_cfg->num_channels = channels;
enc_cfg->bits_per_sample = bits_per_sample;
enc_cfg->sample_rate = rate;
enc_cfg->is_signed = 1;
channel_mapping = enc_cfg->channel_mapping;
if (q6dsp_map_channels(channel_mapping, channels)) {
rc = -EINVAL;
goto err;
}
rc = q6asm_ac_send_cmd_sync(ac, pkt);
err:
kfree(pkt);
return rc;
}
EXPORT_SYMBOL_GPL(q6asm_enc_cfg_blk_pcm_format_support);
/**
* q6asm_read() - read data of period size from audio client
*
* @ac: audio client pointer
* @stream_id: stream id
*
* Return: Will be an negative value on error or zero on success
*/
int q6asm_read(struct audio_client *ac, uint32_t stream_id)
{
struct asm_data_cmd_read_v2 *read;
struct audio_port_data *port;
struct audio_buffer *ab;
struct apr_pkt *pkt;
unsigned long flags;
int pkt_size;
int rc = 0;
void *p;
pkt_size = APR_HDR_SIZE + sizeof(*read);
p = kzalloc(pkt_size, GFP_ATOMIC);
if (!p)
return -ENOMEM;
pkt = p;
read = p + APR_HDR_SIZE;
spin_lock_irqsave(&ac->lock, flags);
port = &ac->port[SNDRV_PCM_STREAM_CAPTURE];
q6asm_add_hdr(ac, &pkt->hdr, pkt_size, false, stream_id);
ab = &port->buf[port->dsp_buf];
pkt->hdr.opcode = ASM_DATA_CMD_READ_V2;
read->buf_addr_lsw = lower_32_bits(ab->phys);
read->buf_addr_msw = upper_32_bits(ab->phys);
read->mem_map_handle = port->mem_map_handle;
read->buf_size = ab->size;
read->seq_id = port->dsp_buf;
pkt->hdr.token = port->dsp_buf;
port->dsp_buf++;
if (port->dsp_buf >= port->num_periods)
port->dsp_buf = 0;
spin_unlock_irqrestore(&ac->lock, flags);
rc = apr_send_pkt(ac->adev, pkt);
if (rc == pkt_size)
rc = 0;
else
pr_err("read op[0x%x]rc[%d]\n", pkt->hdr.opcode, rc);
kfree(pkt);
return rc;
}
EXPORT_SYMBOL_GPL(q6asm_read);
static int __q6asm_open_read(struct audio_client *ac, uint32_t stream_id,
uint32_t format, uint16_t bits_per_sample)
{
struct asm_stream_cmd_open_read_v3 *open;
struct apr_pkt *pkt;
int pkt_size, rc;
void *p;
pkt_size = APR_HDR_SIZE + sizeof(*open);
p = kzalloc(pkt_size, GFP_KERNEL);
if (!p)
return -ENOMEM;
pkt = p;
open = p + APR_HDR_SIZE;
q6asm_add_hdr(ac, &pkt->hdr, pkt_size, true, stream_id);
pkt->hdr.opcode = ASM_STREAM_CMD_OPEN_READ_V3;
/* Stream prio : High, provide meta info with encoded frames */
open->src_endpointype = ASM_END_POINT_DEVICE_MATRIX;
open->preprocopo_id = ASM_STREAM_POSTPROC_TOPO_ID_NONE;
open->bits_per_sample = bits_per_sample;
open->mode_flags = 0x0;
open->mode_flags |= ASM_LEGACY_STREAM_SESSION <<
ASM_SHIFT_STREAM_PERF_MODE_FLAG_IN_OPEN_READ;
switch (format) {
case FORMAT_LINEAR_PCM:
open->mode_flags |= 0x00;
open->enc_cfg_id = ASM_MEDIA_FMT_MULTI_CHANNEL_PCM_V2;
break;
default:
pr_err("Invalid format[%d]\n", format);
}
rc = q6asm_ac_send_cmd_sync(ac, pkt);
kfree(pkt);
return rc;
}
/**
* q6asm_open_read() - Open audio client for reading
*
* @ac: audio client pointer
* @stream_id: stream id
* @format: audio sample format
* @bits_per_sample: bits per sample
*
* Return: Will be an negative value on error or zero on success
*/
int q6asm_open_read(struct audio_client *ac, uint32_t stream_id,
uint32_t format, uint16_t bits_per_sample)
{
return __q6asm_open_read(ac, stream_id, format, bits_per_sample);
}
EXPORT_SYMBOL_GPL(q6asm_open_read);
/**
* q6asm_write_async() - non blocking write
*
* @ac: audio client pointer
* @stream_id: stream id
* @len: length in bytes
* @msw_ts: timestamp msw
* @lsw_ts: timestamp lsw
* @wflags: flags associated with write
*
* Return: Will be an negative value on error or zero on success
*/
int q6asm_write_async(struct audio_client *ac, uint32_t stream_id, uint32_t len,
uint32_t msw_ts, uint32_t lsw_ts, uint32_t wflags)
{
struct asm_data_cmd_write_v2 *write;
struct audio_port_data *port;
struct audio_buffer *ab;
unsigned long flags;
struct apr_pkt *pkt;
int pkt_size;
int rc = 0;
void *p;
pkt_size = APR_HDR_SIZE + sizeof(*write);
p = kzalloc(pkt_size, GFP_ATOMIC);
if (!p)
return -ENOMEM;
pkt = p;
write = p + APR_HDR_SIZE;
spin_lock_irqsave(&ac->lock, flags);
port = &ac->port[SNDRV_PCM_STREAM_PLAYBACK];
q6asm_add_hdr(ac, &pkt->hdr, pkt_size, false, stream_id);
ab = &port->buf[port->dsp_buf];
pkt->hdr.token = port->dsp_buf | (len << ASM_WRITE_TOKEN_LEN_SHIFT);
pkt->hdr.opcode = ASM_DATA_CMD_WRITE_V2;
write->buf_addr_lsw = lower_32_bits(ab->phys);
write->buf_addr_msw = upper_32_bits(ab->phys);
write->buf_size = len;
write->seq_id = port->dsp_buf;
write->timestamp_lsw = lsw_ts;
write->timestamp_msw = msw_ts;
write->mem_map_handle =
ac->port[SNDRV_PCM_STREAM_PLAYBACK].mem_map_handle;
write->flags = wflags;
port->dsp_buf++;
if (port->dsp_buf >= port->num_periods)
port->dsp_buf = 0;
spin_unlock_irqrestore(&ac->lock, flags);
rc = apr_send_pkt(ac->adev, pkt);
if (rc == pkt_size)
rc = 0;
kfree(pkt);
return rc;
}
EXPORT_SYMBOL_GPL(q6asm_write_async);
static void q6asm_reset_buf_state(struct audio_client *ac)
{
struct audio_port_data *port;
unsigned long flags;
spin_lock_irqsave(&ac->lock, flags);
port = &ac->port[SNDRV_PCM_STREAM_PLAYBACK];
port->dsp_buf = 0;
port = &ac->port[SNDRV_PCM_STREAM_CAPTURE];
port->dsp_buf = 0;
spin_unlock_irqrestore(&ac->lock, flags);
}
static int __q6asm_cmd(struct audio_client *ac, uint32_t stream_id, int cmd,
bool wait)
{
struct apr_pkt pkt;
int rc;
q6asm_add_hdr(ac, &pkt.hdr, APR_HDR_SIZE, true, stream_id);
switch (cmd) {
case CMD_PAUSE:
pkt.hdr.opcode = ASM_SESSION_CMD_PAUSE;
break;
case CMD_SUSPEND:
pkt.hdr.opcode = ASM_SESSION_CMD_SUSPEND;
break;
case CMD_FLUSH:
pkt.hdr.opcode = ASM_STREAM_CMD_FLUSH;
break;
case CMD_OUT_FLUSH:
pkt.hdr.opcode = ASM_STREAM_CMD_FLUSH_READBUFS;
break;
case CMD_EOS:
pkt.hdr.opcode = ASM_DATA_CMD_EOS;
break;
case CMD_CLOSE:
pkt.hdr.opcode = ASM_STREAM_CMD_CLOSE;
break;
default:
return -EINVAL;
}
if (wait)
rc = q6asm_ac_send_cmd_sync(ac, &pkt);
else
return apr_send_pkt(ac->adev, &pkt);
if (rc < 0)
return rc;
if (cmd == CMD_FLUSH)
q6asm_reset_buf_state(ac);
return 0;
}
/**
* q6asm_cmd() - run cmd on audio client
*
* @ac: audio client pointer
* @stream_id: stream id
* @cmd: command to run on audio client.
*
* Return: Will be an negative value on error or zero on success
*/
int q6asm_cmd(struct audio_client *ac, uint32_t stream_id, int cmd)
{
return __q6asm_cmd(ac, stream_id, cmd, true);
}
EXPORT_SYMBOL_GPL(q6asm_cmd);
/**
* q6asm_cmd_nowait() - non blocking, run cmd on audio client
*
* @ac: audio client pointer
* @stream_id: stream id
* @cmd: command to run on audio client.
*
* Return: Will be an negative value on error or zero on success
*/
int q6asm_cmd_nowait(struct audio_client *ac, uint32_t stream_id, int cmd)
{
return __q6asm_cmd(ac, stream_id, cmd, false);
}
EXPORT_SYMBOL_GPL(q6asm_cmd_nowait);
static int q6asm_probe(struct apr_device *adev)
{
struct device *dev = &adev->dev;
struct q6asm *q6asm;
q6asm = devm_kzalloc(dev, sizeof(*q6asm), GFP_KERNEL);
if (!q6asm)
return -ENOMEM;
q6core_get_svc_api_info(adev->svc_id, &q6asm->ainfo);
q6asm->dev = dev;
q6asm->adev = adev;
init_waitqueue_head(&q6asm->mem_wait);
spin_lock_init(&q6asm->slock);
dev_set_drvdata(dev, q6asm);
return devm_of_platform_populate(dev);
}
#ifdef CONFIG_OF
static const struct of_device_id q6asm_device_id[] = {
{ .compatible = "qcom,q6asm" },
{},
};
MODULE_DEVICE_TABLE(of, q6asm_device_id);
#endif
static struct apr_driver qcom_q6asm_driver = {
.probe = q6asm_probe,
.callback = q6asm_srvc_callback,
.driver = {
.name = "qcom-q6asm",
.of_match_table = of_match_ptr(q6asm_device_id),
},
};
module_apr_driver(qcom_q6asm_driver);
MODULE_DESCRIPTION("Q6 Audio Stream Manager driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/qcom/qdsp6/q6asm.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2020, Linaro Limited
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/pcm.h>
#include <sound/control.h>
#include <sound/asound.h>
#include <linux/firmware.h>
#include <sound/soc-topology.h>
#include <sound/soc-dpcm.h>
#include <uapi/sound/snd_ar_tokens.h>
#include <linux/kernel.h>
#include <linux/wait.h>
#include "q6apm.h"
#include "audioreach.h"
struct snd_ar_control {
u32 graph_id; /* Graph ID */
u32 sgid; /* Sub Graph ID */
u32 module_instance_id; /* Connected Module Instance ID */
struct snd_soc_dapm_widget *w;
struct list_head node;
struct snd_soc_component *scomp;
};
static struct audioreach_graph_info *audioreach_tplg_alloc_graph_info(struct q6apm *apm,
uint32_t graph_id,
bool *found)
{
struct audioreach_graph_info *info;
int ret;
mutex_lock(&apm->lock);
info = idr_find(&apm->graph_info_idr, graph_id);
mutex_unlock(&apm->lock);
if (info) {
*found = true;
return info;
}
*found = false;
info = kzalloc(sizeof(*info), GFP_KERNEL);
if (!info)
return ERR_PTR(-ENOMEM);
INIT_LIST_HEAD(&info->sg_list);
mutex_lock(&apm->lock);
ret = idr_alloc_u32(&apm->graph_info_idr, info, &graph_id, graph_id, GFP_KERNEL);
mutex_unlock(&apm->lock);
if (ret < 0) {
dev_err(apm->dev, "Failed to allocate Graph ID (%x)\n", graph_id);
kfree(info);
return ERR_PTR(ret);
}
info->id = graph_id;
return info;
}
static void audioreach_tplg_add_sub_graph(struct audioreach_sub_graph *sg,
struct audioreach_graph_info *info)
{
list_add_tail(&sg->node, &info->sg_list);
sg->info = info;
info->num_sub_graphs++;
}
static struct audioreach_sub_graph *audioreach_tplg_alloc_sub_graph(struct q6apm *apm,
uint32_t sub_graph_id,
bool *found)
{
struct audioreach_sub_graph *sg;
int ret;
if (!sub_graph_id)
return ERR_PTR(-EINVAL);
/* Find if there is already a matching sub-graph */
mutex_lock(&apm->lock);
sg = idr_find(&apm->sub_graphs_idr, sub_graph_id);
mutex_unlock(&apm->lock);
if (sg) {
*found = true;
return sg;
}
*found = false;
sg = kzalloc(sizeof(*sg), GFP_KERNEL);
if (!sg)
return ERR_PTR(-ENOMEM);
INIT_LIST_HEAD(&sg->container_list);
mutex_lock(&apm->lock);
ret = idr_alloc_u32(&apm->sub_graphs_idr, sg, &sub_graph_id, sub_graph_id, GFP_KERNEL);
mutex_unlock(&apm->lock);
if (ret < 0) {
dev_err(apm->dev, "Failed to allocate Sub-Graph Instance ID (%x)\n", sub_graph_id);
kfree(sg);
return ERR_PTR(ret);
}
sg->sub_graph_id = sub_graph_id;
return sg;
}
static struct audioreach_container *audioreach_tplg_alloc_container(struct q6apm *apm,
struct audioreach_sub_graph *sg,
uint32_t container_id,
bool *found)
{
struct audioreach_container *cont;
int ret;
if (!container_id)
return ERR_PTR(-EINVAL);
mutex_lock(&apm->lock);
cont = idr_find(&apm->containers_idr, container_id);
mutex_unlock(&apm->lock);
if (cont) {
*found = true;
return cont;
}
*found = false;
cont = kzalloc(sizeof(*cont), GFP_KERNEL);
if (!cont)
return ERR_PTR(-ENOMEM);
INIT_LIST_HEAD(&cont->modules_list);
mutex_lock(&apm->lock);
ret = idr_alloc_u32(&apm->containers_idr, cont, &container_id, container_id, GFP_KERNEL);
mutex_unlock(&apm->lock);
if (ret < 0) {
dev_err(apm->dev, "Failed to allocate Container Instance ID (%x)\n", container_id);
kfree(cont);
return ERR_PTR(ret);
}
cont->container_id = container_id;
cont->sub_graph = sg;
/* add to container list */
list_add_tail(&cont->node, &sg->container_list);
sg->num_containers++;
return cont;
}
static struct audioreach_module *audioreach_tplg_alloc_module(struct q6apm *apm,
struct audioreach_container *cont,
struct snd_soc_dapm_widget *w,
uint32_t module_id, bool *found)
{
struct audioreach_module *mod;
int ret;
mutex_lock(&apm->lock);
mod = idr_find(&apm->modules_idr, module_id);
mutex_unlock(&apm->lock);
if (mod) {
*found = true;
return mod;
}
*found = false;
mod = kzalloc(sizeof(*mod), GFP_KERNEL);
if (!mod)
return ERR_PTR(-ENOMEM);
mutex_lock(&apm->lock);
if (!module_id) { /* alloc module id dynamically */
ret = idr_alloc_cyclic(&apm->modules_idr, mod,
AR_MODULE_DYNAMIC_INSTANCE_ID_START,
AR_MODULE_DYNAMIC_INSTANCE_ID_END, GFP_KERNEL);
} else {
ret = idr_alloc_u32(&apm->modules_idr, mod, &module_id, module_id, GFP_KERNEL);
}
mutex_unlock(&apm->lock);
if (ret < 0) {
dev_err(apm->dev, "Failed to allocate Module Instance ID (%x)\n", module_id);
kfree(mod);
return ERR_PTR(ret);
}
mod->instance_id = module_id;
/* add to module list */
list_add_tail(&mod->node, &cont->modules_list);
mod->container = cont;
mod->widget = w;
cont->num_modules++;
return mod;
}
static struct snd_soc_tplg_vendor_array *audioreach_get_sg_array(
struct snd_soc_tplg_private *private)
{
struct snd_soc_tplg_vendor_array *sg_array = NULL;
bool found = false;
int sz;
for (sz = 0; !found && (sz < le32_to_cpu(private->size)); ) {
struct snd_soc_tplg_vendor_value_elem *sg_elem;
int tkn_count = 0;
sg_array = (struct snd_soc_tplg_vendor_array *)((u8 *)private->array + sz);
sg_elem = sg_array->value;
sz = sz + le32_to_cpu(sg_array->size);
while (!found && tkn_count <= (le32_to_cpu(sg_array->num_elems) - 1)) {
switch (le32_to_cpu(sg_elem->token)) {
case AR_TKN_U32_SUB_GRAPH_INSTANCE_ID:
found = true;
break;
default:
break;
}
tkn_count++;
sg_elem++;
}
}
if (found)
return sg_array;
return NULL;
}
static struct snd_soc_tplg_vendor_array *audioreach_get_cont_array(
struct snd_soc_tplg_private *private)
{
struct snd_soc_tplg_vendor_array *cont_array = NULL;
bool found = false;
int sz;
for (sz = 0; !found && (sz < le32_to_cpu(private->size)); ) {
struct snd_soc_tplg_vendor_value_elem *cont_elem;
int tkn_count = 0;
cont_array = (struct snd_soc_tplg_vendor_array *)((u8 *)private->array + sz);
cont_elem = cont_array->value;
sz = sz + le32_to_cpu(cont_array->size);
while (!found && tkn_count <= (le32_to_cpu(cont_array->num_elems) - 1)) {
switch (le32_to_cpu(cont_elem->token)) {
case AR_TKN_U32_CONTAINER_INSTANCE_ID:
found = true;
break;
default:
break;
}
tkn_count++;
cont_elem++;
}
}
if (found)
return cont_array;
return NULL;
}
static struct snd_soc_tplg_vendor_array *audioreach_get_module_array(
struct snd_soc_tplg_private *private)
{
struct snd_soc_tplg_vendor_array *mod_array = NULL;
bool found = false;
int sz = 0;
for (sz = 0; !found && (sz < le32_to_cpu(private->size)); ) {
struct snd_soc_tplg_vendor_value_elem *mod_elem;
int tkn_count = 0;
mod_array = (struct snd_soc_tplg_vendor_array *)((u8 *)private->array + sz);
mod_elem = mod_array->value;
sz = sz + le32_to_cpu(mod_array->size);
while (!found && tkn_count <= (le32_to_cpu(mod_array->num_elems) - 1)) {
switch (le32_to_cpu(mod_elem->token)) {
case AR_TKN_U32_MODULE_INSTANCE_ID:
found = true;
break;
default:
break;
}
tkn_count++;
mod_elem++;
}
}
if (found)
return mod_array;
return NULL;
}
static struct audioreach_sub_graph *audioreach_parse_sg_tokens(struct q6apm *apm,
struct snd_soc_tplg_private *private)
{
struct snd_soc_tplg_vendor_value_elem *sg_elem;
struct snd_soc_tplg_vendor_array *sg_array;
struct audioreach_graph_info *info = NULL;
int graph_id, sub_graph_id, tkn_count = 0;
struct audioreach_sub_graph *sg;
bool found;
sg_array = audioreach_get_sg_array(private);
sg_elem = sg_array->value;
while (tkn_count <= (le32_to_cpu(sg_array->num_elems) - 1)) {
switch (le32_to_cpu(sg_elem->token)) {
case AR_TKN_U32_SUB_GRAPH_INSTANCE_ID:
sub_graph_id = le32_to_cpu(sg_elem->value);
sg = audioreach_tplg_alloc_sub_graph(apm, sub_graph_id, &found);
if (IS_ERR(sg)) {
return sg;
} else if (found) {
/* Already parsed data for this sub-graph */
return sg;
}
break;
case AR_TKN_DAI_INDEX:
/* Sub graph is associated with predefined graph */
graph_id = le32_to_cpu(sg_elem->value);
info = audioreach_tplg_alloc_graph_info(apm, graph_id, &found);
if (IS_ERR(info))
return ERR_CAST(info);
break;
case AR_TKN_U32_SUB_GRAPH_PERF_MODE:
sg->perf_mode = le32_to_cpu(sg_elem->value);
break;
case AR_TKN_U32_SUB_GRAPH_DIRECTION:
sg->direction = le32_to_cpu(sg_elem->value);
break;
case AR_TKN_U32_SUB_GRAPH_SCENARIO_ID:
sg->scenario_id = le32_to_cpu(sg_elem->value);
break;
default:
dev_err(apm->dev, "Not a valid token %d for graph\n", sg_elem->token);
break;
}
tkn_count++;
sg_elem++;
}
/* Sub graph is associated with predefined graph */
if (info)
audioreach_tplg_add_sub_graph(sg, info);
return sg;
}
static struct audioreach_container *audioreach_parse_cont_tokens(struct q6apm *apm,
struct audioreach_sub_graph *sg,
struct snd_soc_tplg_private *private)
{
struct snd_soc_tplg_vendor_value_elem *cont_elem;
struct snd_soc_tplg_vendor_array *cont_array;
struct audioreach_container *cont;
int container_id, tkn_count = 0;
bool found = false;
cont_array = audioreach_get_cont_array(private);
cont_elem = cont_array->value;
while (tkn_count <= (le32_to_cpu(cont_array->num_elems) - 1)) {
switch (le32_to_cpu(cont_elem->token)) {
case AR_TKN_U32_CONTAINER_INSTANCE_ID:
container_id = le32_to_cpu(cont_elem->value);
cont = audioreach_tplg_alloc_container(apm, sg, container_id, &found);
if (IS_ERR(cont) || found)/* Error or Already parsed container data */
return cont;
break;
case AR_TKN_U32_CONTAINER_CAPABILITY_ID:
cont->capability_id = le32_to_cpu(cont_elem->value);
break;
case AR_TKN_U32_CONTAINER_STACK_SIZE:
cont->stack_size = le32_to_cpu(cont_elem->value);
break;
case AR_TKN_U32_CONTAINER_GRAPH_POS:
cont->graph_pos = le32_to_cpu(cont_elem->value);
break;
case AR_TKN_U32_CONTAINER_PROC_DOMAIN:
cont->proc_domain = le32_to_cpu(cont_elem->value);
break;
default:
dev_err(apm->dev, "Not a valid token %d for graph\n", cont_elem->token);
break;
}
tkn_count++;
cont_elem++;
}
return cont;
}
static struct audioreach_module *audioreach_parse_common_tokens(struct q6apm *apm,
struct audioreach_container *cont,
struct snd_soc_tplg_private *private,
struct snd_soc_dapm_widget *w)
{
uint32_t max_ip_port = 0, max_op_port = 0, in_port = 0, out_port = 0;
uint32_t src_mod_op_port_id[AR_MAX_MOD_LINKS] = { 0, };
uint32_t dst_mod_inst_id[AR_MAX_MOD_LINKS] = { 0, };
uint32_t dst_mod_ip_port_id[AR_MAX_MOD_LINKS] = { 0, };
uint32_t src_mod_inst_id = 0;
int module_id = 0, instance_id = 0, tkn_count = 0;
struct snd_soc_tplg_vendor_value_elem *mod_elem;
struct snd_soc_tplg_vendor_array *mod_array;
struct audioreach_module *mod = NULL;
uint32_t token;
bool found;
int max_tokens;
mod_array = audioreach_get_module_array(private);
mod_elem = mod_array->value;
max_tokens = le32_to_cpu(mod_array->num_elems);
while (tkn_count <= (max_tokens - 1)) {
token = le32_to_cpu(mod_elem->token);
switch (token) {
/* common module info */
case AR_TKN_U32_MODULE_ID:
module_id = le32_to_cpu(mod_elem->value);
break;
case AR_TKN_U32_MODULE_INSTANCE_ID:
instance_id = le32_to_cpu(mod_elem->value);
mod = audioreach_tplg_alloc_module(apm, cont, w,
instance_id, &found);
if (IS_ERR(mod)) {
return mod;
} else if (found) {
dev_err(apm->dev, "Duplicate Module Instance ID 0x%08x found\n",
instance_id);
return ERR_PTR(-EINVAL);
}
break;
case AR_TKN_U32_MODULE_MAX_IP_PORTS:
max_ip_port = le32_to_cpu(mod_elem->value);
break;
case AR_TKN_U32_MODULE_MAX_OP_PORTS:
max_op_port = le32_to_cpu(mod_elem->value);
break;
case AR_TKN_U32_MODULE_IN_PORTS:
in_port = le32_to_cpu(mod_elem->value);
break;
case AR_TKN_U32_MODULE_OUT_PORTS:
out_port = le32_to_cpu(mod_elem->value);
break;
case AR_TKN_U32_MODULE_SRC_INSTANCE_ID:
src_mod_inst_id = le32_to_cpu(mod_elem->value);
break;
case AR_TKN_U32_MODULE_SRC_OP_PORT_ID:
src_mod_op_port_id[0] = le32_to_cpu(mod_elem->value);
break;
case AR_TKN_U32_MODULE_SRC_OP_PORT_ID1:
src_mod_op_port_id[1] = le32_to_cpu(mod_elem->value);
break;
case AR_TKN_U32_MODULE_SRC_OP_PORT_ID2:
src_mod_op_port_id[2] = le32_to_cpu(mod_elem->value);
break;
case AR_TKN_U32_MODULE_SRC_OP_PORT_ID3:
src_mod_op_port_id[3] = le32_to_cpu(mod_elem->value);
break;
case AR_TKN_U32_MODULE_SRC_OP_PORT_ID4:
src_mod_op_port_id[4] = le32_to_cpu(mod_elem->value);
break;
case AR_TKN_U32_MODULE_SRC_OP_PORT_ID5:
src_mod_op_port_id[5] = le32_to_cpu(mod_elem->value);
break;
case AR_TKN_U32_MODULE_SRC_OP_PORT_ID6:
src_mod_op_port_id[6] = le32_to_cpu(mod_elem->value);
break;
case AR_TKN_U32_MODULE_SRC_OP_PORT_ID7:
src_mod_op_port_id[7] = le32_to_cpu(mod_elem->value);
break;
case AR_TKN_U32_MODULE_DST_INSTANCE_ID:
dst_mod_inst_id[0] = le32_to_cpu(mod_elem->value);
break;
case AR_TKN_U32_MODULE_DST_INSTANCE_ID1:
dst_mod_inst_id[1] = le32_to_cpu(mod_elem->value);
break;
case AR_TKN_U32_MODULE_DST_INSTANCE_ID2:
dst_mod_inst_id[2] = le32_to_cpu(mod_elem->value);
break;
case AR_TKN_U32_MODULE_DST_INSTANCE_ID3:
dst_mod_inst_id[3] = le32_to_cpu(mod_elem->value);
break;
case AR_TKN_U32_MODULE_DST_INSTANCE_ID4:
dst_mod_inst_id[4] = le32_to_cpu(mod_elem->value);
break;
case AR_TKN_U32_MODULE_DST_INSTANCE_ID5:
dst_mod_inst_id[5] = le32_to_cpu(mod_elem->value);
break;
case AR_TKN_U32_MODULE_DST_INSTANCE_ID6:
dst_mod_inst_id[6] = le32_to_cpu(mod_elem->value);
break;
case AR_TKN_U32_MODULE_DST_INSTANCE_ID7:
dst_mod_inst_id[7] = le32_to_cpu(mod_elem->value);
break;
case AR_TKN_U32_MODULE_DST_IN_PORT_ID:
dst_mod_ip_port_id[0] = le32_to_cpu(mod_elem->value);
break;
case AR_TKN_U32_MODULE_DST_IN_PORT_ID1:
dst_mod_ip_port_id[1] = le32_to_cpu(mod_elem->value);
break;
case AR_TKN_U32_MODULE_DST_IN_PORT_ID2:
dst_mod_ip_port_id[2] = le32_to_cpu(mod_elem->value);
break;
case AR_TKN_U32_MODULE_DST_IN_PORT_ID3:
dst_mod_ip_port_id[3] = le32_to_cpu(mod_elem->value);
break;
case AR_TKN_U32_MODULE_DST_IN_PORT_ID4:
dst_mod_ip_port_id[4] = le32_to_cpu(mod_elem->value);
break;
case AR_TKN_U32_MODULE_DST_IN_PORT_ID5:
dst_mod_ip_port_id[5] = le32_to_cpu(mod_elem->value);
break;
case AR_TKN_U32_MODULE_DST_IN_PORT_ID6:
dst_mod_ip_port_id[6] = le32_to_cpu(mod_elem->value);
break;
case AR_TKN_U32_MODULE_DST_IN_PORT_ID7:
dst_mod_ip_port_id[7] = le32_to_cpu(mod_elem->value);
break;
default:
break;
}
tkn_count++;
mod_elem++;
}
if (mod) {
int pn, id = 0;
mod->module_id = module_id;
mod->max_ip_port = max_ip_port;
mod->max_op_port = max_op_port;
mod->in_port = in_port;
mod->out_port = out_port;
mod->src_mod_inst_id = src_mod_inst_id;
for (pn = 0; pn < mod->max_op_port; pn++) {
if (src_mod_op_port_id[pn] && dst_mod_inst_id[pn] &&
dst_mod_ip_port_id[pn]) {
mod->src_mod_op_port_id[id] = src_mod_op_port_id[pn];
mod->dst_mod_inst_id[id] = dst_mod_inst_id[pn];
mod->dst_mod_ip_port_id[id] = dst_mod_ip_port_id[pn];
id++;
mod->num_connections = id;
}
}
}
return mod;
}
static int audioreach_widget_load_module_common(struct snd_soc_component *component,
int index, struct snd_soc_dapm_widget *w,
struct snd_soc_tplg_dapm_widget *tplg_w)
{
struct q6apm *apm = dev_get_drvdata(component->dev);
struct audioreach_container *cont;
struct audioreach_sub_graph *sg;
struct audioreach_module *mod;
struct snd_soc_dobj *dobj;
sg = audioreach_parse_sg_tokens(apm, &tplg_w->priv);
if (IS_ERR(sg))
return PTR_ERR(sg);
cont = audioreach_parse_cont_tokens(apm, sg, &tplg_w->priv);
if (IS_ERR(cont))
return PTR_ERR(cont);
mod = audioreach_parse_common_tokens(apm, cont, &tplg_w->priv, w);
if (IS_ERR(mod))
return PTR_ERR(mod);
dobj = &w->dobj;
dobj->private = mod;
return 0;
}
static int audioreach_widget_load_enc_dec_cnv(struct snd_soc_component *component,
int index, struct snd_soc_dapm_widget *w,
struct snd_soc_tplg_dapm_widget *tplg_w)
{
struct snd_soc_tplg_vendor_value_elem *mod_elem;
struct snd_soc_tplg_vendor_array *mod_array;
struct audioreach_module *mod;
struct snd_soc_dobj *dobj;
int tkn_count = 0;
int ret;
ret = audioreach_widget_load_module_common(component, index, w, tplg_w);
if (ret)
return ret;
dobj = &w->dobj;
mod = dobj->private;
mod_array = audioreach_get_module_array(&tplg_w->priv);
mod_elem = mod_array->value;
while (tkn_count <= (le32_to_cpu(mod_array->num_elems) - 1)) {
switch (le32_to_cpu(mod_elem->token)) {
case AR_TKN_U32_MODULE_FMT_INTERLEAVE:
mod->interleave_type = le32_to_cpu(mod_elem->value);
break;
case AR_TKN_U32_MODULE_FMT_SAMPLE_RATE:
mod->rate = le32_to_cpu(mod_elem->value);
break;
case AR_TKN_U32_MODULE_FMT_BIT_DEPTH:
mod->bit_depth = le32_to_cpu(mod_elem->value);
break;
default:
break;
}
tkn_count++;
mod_elem++;
}
return 0;
}
static int audioreach_widget_log_module_load(struct audioreach_module *mod,
struct snd_soc_tplg_vendor_array *mod_array)
{
struct snd_soc_tplg_vendor_value_elem *mod_elem;
int tkn_count = 0;
mod_elem = mod_array->value;
while (tkn_count <= (le32_to_cpu(mod_array->num_elems) - 1)) {
switch (le32_to_cpu(mod_elem->token)) {
case AR_TKN_U32_MODULE_LOG_CODE:
mod->log_code = le32_to_cpu(mod_elem->value);
break;
case AR_TKN_U32_MODULE_LOG_TAP_POINT_ID:
mod->log_tap_point_id = le32_to_cpu(mod_elem->value);
break;
case AR_TKN_U32_MODULE_LOG_MODE:
mod->log_mode = le32_to_cpu(mod_elem->value);
break;
default:
break;
}
tkn_count++;
mod_elem++;
}
return 0;
}
static int audioreach_widget_dma_module_load(struct audioreach_module *mod,
struct snd_soc_tplg_vendor_array *mod_array)
{
struct snd_soc_tplg_vendor_value_elem *mod_elem;
int tkn_count = 0;
mod_elem = mod_array->value;
while (tkn_count <= (le32_to_cpu(mod_array->num_elems) - 1)) {
switch (le32_to_cpu(mod_elem->token)) {
case AR_TKN_U32_MODULE_HW_IF_IDX:
mod->hw_interface_idx = le32_to_cpu(mod_elem->value);
break;
case AR_TKN_U32_MODULE_FMT_DATA:
mod->data_format = le32_to_cpu(mod_elem->value);
break;
case AR_TKN_U32_MODULE_HW_IF_TYPE:
mod->hw_interface_type = le32_to_cpu(mod_elem->value);
break;
default:
break;
}
tkn_count++;
mod_elem++;
}
return 0;
}
static int audioreach_widget_i2s_module_load(struct audioreach_module *mod,
struct snd_soc_tplg_vendor_array *mod_array)
{
struct snd_soc_tplg_vendor_value_elem *mod_elem;
int tkn_count = 0;
mod_elem = mod_array->value;
while (tkn_count <= (le32_to_cpu(mod_array->num_elems) - 1)) {
switch (le32_to_cpu(mod_elem->token)) {
case AR_TKN_U32_MODULE_HW_IF_IDX:
mod->hw_interface_idx = le32_to_cpu(mod_elem->value);
break;
case AR_TKN_U32_MODULE_FMT_DATA:
mod->data_format = le32_to_cpu(mod_elem->value);
break;
case AR_TKN_U32_MODULE_HW_IF_TYPE:
mod->hw_interface_type = le32_to_cpu(mod_elem->value);
break;
case AR_TKN_U32_MODULE_SD_LINE_IDX:
mod->sd_line_idx = le32_to_cpu(mod_elem->value);
break;
case AR_TKN_U32_MODULE_WS_SRC:
mod->ws_src = le32_to_cpu(mod_elem->value);
break;
default:
break;
}
tkn_count++;
mod_elem++;
}
return 0;
}
static int audioreach_widget_load_buffer(struct snd_soc_component *component,
int index, struct snd_soc_dapm_widget *w,
struct snd_soc_tplg_dapm_widget *tplg_w)
{
struct snd_soc_tplg_vendor_array *mod_array;
struct audioreach_module *mod;
struct snd_soc_dobj *dobj;
int ret;
ret = audioreach_widget_load_module_common(component, index, w, tplg_w);
if (ret)
return ret;
dobj = &w->dobj;
mod = dobj->private;
mod_array = audioreach_get_module_array(&tplg_w->priv);
switch (mod->module_id) {
case MODULE_ID_CODEC_DMA_SINK:
case MODULE_ID_CODEC_DMA_SOURCE:
audioreach_widget_dma_module_load(mod, mod_array);
break;
case MODULE_ID_DATA_LOGGING:
audioreach_widget_log_module_load(mod, mod_array);
break;
case MODULE_ID_I2S_SINK:
case MODULE_ID_I2S_SOURCE:
audioreach_widget_i2s_module_load(mod, mod_array);
break;
default:
return -EINVAL;
}
return 0;
}
static int audioreach_widget_load_mixer(struct snd_soc_component *component,
int index, struct snd_soc_dapm_widget *w,
struct snd_soc_tplg_dapm_widget *tplg_w)
{
struct snd_soc_tplg_vendor_value_elem *w_elem;
struct snd_soc_tplg_vendor_array *w_array;
struct snd_ar_control *scontrol;
struct q6apm *data = dev_get_drvdata(component->dev);
struct snd_soc_dobj *dobj;
int tkn_count = 0;
w_array = &tplg_w->priv.array[0];
scontrol = kzalloc(sizeof(*scontrol), GFP_KERNEL);
if (!scontrol)
return -ENOMEM;
scontrol->scomp = component;
dobj = &w->dobj;
dobj->private = scontrol;
w_elem = w_array->value;
while (tkn_count <= (le32_to_cpu(w_array->num_elems) - 1)) {
switch (le32_to_cpu(w_elem->token)) {
case AR_TKN_U32_SUB_GRAPH_INSTANCE_ID:
scontrol->sgid = le32_to_cpu(w_elem->value);
break;
case AR_TKN_DAI_INDEX:
scontrol->graph_id = le32_to_cpu(w_elem->value);
break;
default: /* ignore other tokens */
break;
}
tkn_count++;
w_elem++;
}
scontrol->w = w;
list_add_tail(&scontrol->node, &data->widget_list);
return 0;
}
static int audioreach_pga_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_dapm_context *dapm = w->dapm;
struct snd_soc_component *c = snd_soc_dapm_to_component(dapm);
struct audioreach_module *mod = w->dobj.private;
struct q6apm *apm = dev_get_drvdata(c->dev);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
/* apply gain after power up of widget */
audioreach_gain_set_vol_ctrl(apm, mod, mod->gain);
break;
default:
break;
}
return 0;
}
static const struct snd_soc_tplg_widget_events audioreach_widget_ops[] = {
{ AR_PGA_DAPM_EVENT, audioreach_pga_event },
};
static int audioreach_widget_load_pga(struct snd_soc_component *component,
int index, struct snd_soc_dapm_widget *w,
struct snd_soc_tplg_dapm_widget *tplg_w)
{
struct audioreach_module *mod;
struct snd_soc_dobj *dobj;
int ret;
ret = audioreach_widget_load_module_common(component, index, w, tplg_w);
if (ret)
return ret;
dobj = &w->dobj;
mod = dobj->private;
mod->gain = VOL_CTRL_DEFAULT_GAIN;
ret = snd_soc_tplg_widget_bind_event(w, audioreach_widget_ops,
ARRAY_SIZE(audioreach_widget_ops),
le16_to_cpu(tplg_w->event_type));
if (ret) {
dev_err(component->dev, "matching event handlers NOT found for %d\n",
le16_to_cpu(tplg_w->event_type));
return -EINVAL;
}
return 0;
}
static int audioreach_widget_ready(struct snd_soc_component *component,
int index, struct snd_soc_dapm_widget *w,
struct snd_soc_tplg_dapm_widget *tplg_w)
{
switch (w->id) {
case snd_soc_dapm_aif_in:
case snd_soc_dapm_aif_out:
audioreach_widget_load_buffer(component, index, w, tplg_w);
break;
case snd_soc_dapm_decoder:
case snd_soc_dapm_encoder:
case snd_soc_dapm_src:
audioreach_widget_load_enc_dec_cnv(component, index, w, tplg_w);
break;
case snd_soc_dapm_buffer:
audioreach_widget_load_buffer(component, index, w, tplg_w);
break;
case snd_soc_dapm_mixer:
return audioreach_widget_load_mixer(component, index, w, tplg_w);
case snd_soc_dapm_pga:
return audioreach_widget_load_pga(component, index, w, tplg_w);
case snd_soc_dapm_dai_link:
case snd_soc_dapm_scheduler:
case snd_soc_dapm_out_drv:
default:
dev_err(component->dev, "Widget type (0x%x) not yet supported\n", w->id);
break;
}
return 0;
}
static int audioreach_widget_unload(struct snd_soc_component *scomp,
struct snd_soc_dobj *dobj)
{
struct snd_soc_dapm_widget *w = container_of(dobj, struct snd_soc_dapm_widget, dobj);
struct q6apm *apm = dev_get_drvdata(scomp->dev);
struct audioreach_container *cont;
struct audioreach_module *mod;
mod = dobj->private;
cont = mod->container;
if (w->id == snd_soc_dapm_mixer) {
/* virtual widget */
struct snd_ar_control *scontrol = dobj->private;
list_del(&scontrol->node);
kfree(scontrol);
return 0;
}
mutex_lock(&apm->lock);
idr_remove(&apm->modules_idr, mod->instance_id);
cont->num_modules--;
list_del(&mod->node);
kfree(mod);
/* Graph Info has N sub-graphs, sub-graph has N containers, Container has N Modules */
if (list_empty(&cont->modules_list)) { /* if no modules in the container then remove it */
struct audioreach_sub_graph *sg = cont->sub_graph;
idr_remove(&apm->containers_idr, cont->container_id);
list_del(&cont->node);
sg->num_containers--;
kfree(cont);
/* check if there are no more containers in the sub graph and remove it */
if (list_empty(&sg->container_list)) {
struct audioreach_graph_info *info = sg->info;
idr_remove(&apm->sub_graphs_idr, sg->sub_graph_id);
list_del(&sg->node);
info->num_sub_graphs--;
kfree(sg);
/* Check if there are no more sub-graphs left then remove graph info */
if (list_empty(&info->sg_list)) {
idr_remove(&apm->graph_info_idr, info->id);
kfree(info);
}
}
}
mutex_unlock(&apm->lock);
return 0;
}
static struct snd_ar_control *audioreach_find_widget(struct snd_soc_component *comp,
const char *name)
{
struct q6apm *apm = dev_get_drvdata(comp->dev);
struct snd_ar_control *control;
list_for_each_entry(control, &apm->widget_list, node) {
if (control->w && !strcmp(name, control->w->name))
return control;
}
return NULL;
}
static struct audioreach_module *audioreach_find_module(struct snd_soc_component *comp,
const char *name)
{
struct q6apm *apm = dev_get_drvdata(comp->dev);
struct audioreach_module *module;
int id;
idr_for_each_entry(&apm->modules_idr, module, id) {
if (!strcmp(name, module->widget->name))
return module;
}
return NULL;
}
static int audioreach_route_load(struct snd_soc_component *scomp, int index,
struct snd_soc_dapm_route *route)
{
struct audioreach_module *src_module, *sink_module;
struct snd_ar_control *control;
struct snd_soc_dapm_widget *w;
int i;
/* check if these are actual modules */
src_module = audioreach_find_module(scomp, route->source);
sink_module = audioreach_find_module(scomp, route->sink);
if (sink_module && !src_module) {
control = audioreach_find_widget(scomp, route->source);
if (control)
control->module_instance_id = sink_module->instance_id;
} else if (!sink_module && src_module && route->control) {
/* check if this is a virtual mixer */
control = audioreach_find_widget(scomp, route->sink);
if (!control || !control->w)
return 0;
w = control->w;
for (i = 0; i < w->num_kcontrols; i++) {
if (!strcmp(route->control, w->kcontrol_news[i].name)) {
struct soc_mixer_control *sm;
struct snd_soc_dobj *dobj;
struct snd_ar_control *scontrol;
sm = (struct soc_mixer_control *)w->kcontrol_news[i].private_value;
dobj = &sm->dobj;
scontrol = dobj->private;
scontrol->module_instance_id = src_module->instance_id;
}
}
}
return 0;
}
static int audioreach_route_unload(struct snd_soc_component *scomp,
struct snd_soc_dobj *dobj)
{
return 0;
}
static int audioreach_tplg_complete(struct snd_soc_component *component)
{
/* TBD */
return 0;
}
/* DAI link - used for any driver specific init */
static int audioreach_link_load(struct snd_soc_component *component, int index,
struct snd_soc_dai_link *link,
struct snd_soc_tplg_link_config *cfg)
{
link->nonatomic = true;
link->dynamic = true;
link->platforms->name = NULL;
link->platforms->of_node = of_get_compatible_child(component->dev->of_node,
"qcom,q6apm-dais");
return 0;
}
static void audioreach_connect_sub_graphs(struct q6apm *apm,
struct snd_ar_control *m1,
struct snd_ar_control *m2,
bool connect)
{
struct audioreach_graph_info *info;
mutex_lock(&apm->lock);
info = idr_find(&apm->graph_info_idr, m2->graph_id);
mutex_unlock(&apm->lock);
if (connect) {
info->src_mod_inst_id = m1->module_instance_id;
info->src_mod_op_port_id = 1;
info->dst_mod_inst_id = m2->module_instance_id;
info->dst_mod_ip_port_id = 2;
} else {
info->src_mod_inst_id = 0;
info->src_mod_op_port_id = 0;
info->dst_mod_inst_id = 0;
info->dst_mod_ip_port_id = 0;
}
}
static bool audioreach_is_vmixer_connected(struct q6apm *apm,
struct snd_ar_control *m1,
struct snd_ar_control *m2)
{
struct audioreach_graph_info *info;
mutex_lock(&apm->lock);
info = idr_find(&apm->graph_info_idr, m2->graph_id);
mutex_unlock(&apm->lock);
if (info->dst_mod_inst_id == m2->module_instance_id &&
info->src_mod_inst_id == m1->module_instance_id)
return true;
return false;
}
static int audioreach_get_audio_mixer(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value;
struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kcontrol);
struct snd_soc_dapm_widget *dw = snd_soc_dapm_kcontrol_widget(kcontrol);
struct snd_soc_component *c = snd_soc_dapm_to_component(dapm);
struct snd_ar_control *dapm_scontrol = dw->dobj.private;
struct snd_ar_control *scontrol = mc->dobj.private;
struct q6apm *data = dev_get_drvdata(c->dev);
bool connected;
connected = audioreach_is_vmixer_connected(data, scontrol, dapm_scontrol);
if (connected)
ucontrol->value.integer.value[0] = 1;
else
ucontrol->value.integer.value[0] = 0;
return 0;
}
static int audioreach_put_audio_mixer(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value;
struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kcontrol);
struct snd_soc_dapm_widget *dw = snd_soc_dapm_kcontrol_widget(kcontrol);
struct snd_soc_component *c = snd_soc_dapm_to_component(dapm);
struct snd_ar_control *dapm_scontrol = dw->dobj.private;
struct snd_ar_control *scontrol = mc->dobj.private;
struct q6apm *data = dev_get_drvdata(c->dev);
if (ucontrol->value.integer.value[0]) {
audioreach_connect_sub_graphs(data, scontrol, dapm_scontrol, true);
snd_soc_dapm_mixer_update_power(dapm, kcontrol, 1, NULL);
} else {
audioreach_connect_sub_graphs(data, scontrol, dapm_scontrol, false);
snd_soc_dapm_mixer_update_power(dapm, kcontrol, 0, NULL);
}
return 0;
}
static int audioreach_get_vol_ctrl_audio_mixer(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dapm_widget *dw = snd_soc_dapm_kcontrol_widget(kcontrol);
struct audioreach_module *mod = dw->dobj.private;
ucontrol->value.integer.value[0] = mod->gain;
return 0;
}
static int audioreach_put_vol_ctrl_audio_mixer(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dapm_widget *dw = snd_soc_dapm_kcontrol_widget(kcontrol);
struct audioreach_module *mod = dw->dobj.private;
mod->gain = ucontrol->value.integer.value[0];
return 1;
}
static int audioreach_control_load_mix(struct snd_soc_component *scomp,
struct snd_ar_control *scontrol,
struct snd_kcontrol_new *kc,
struct snd_soc_tplg_ctl_hdr *hdr)
{
struct snd_soc_tplg_vendor_value_elem *c_elem;
struct snd_soc_tplg_vendor_array *c_array;
struct snd_soc_tplg_mixer_control *mc;
int tkn_count = 0;
mc = container_of(hdr, struct snd_soc_tplg_mixer_control, hdr);
c_array = (struct snd_soc_tplg_vendor_array *)mc->priv.data;
c_elem = c_array->value;
while (tkn_count <= (le32_to_cpu(c_array->num_elems) - 1)) {
switch (le32_to_cpu(c_elem->token)) {
case AR_TKN_U32_SUB_GRAPH_INSTANCE_ID:
scontrol->sgid = le32_to_cpu(c_elem->value);
break;
case AR_TKN_DAI_INDEX:
scontrol->graph_id = le32_to_cpu(c_elem->value);
break;
default:
/* Ignore other tokens */
break;
}
c_elem++;
tkn_count++;
}
return 0;
}
static int audioreach_control_load(struct snd_soc_component *scomp, int index,
struct snd_kcontrol_new *kc,
struct snd_soc_tplg_ctl_hdr *hdr)
{
struct snd_ar_control *scontrol;
struct soc_mixer_control *sm;
struct snd_soc_dobj *dobj;
int ret = 0;
scontrol = kzalloc(sizeof(*scontrol), GFP_KERNEL);
if (!scontrol)
return -ENOMEM;
scontrol->scomp = scomp;
switch (le32_to_cpu(hdr->ops.get)) {
case SND_SOC_AR_TPLG_FE_BE_GRAPH_CTL_MIX:
sm = (struct soc_mixer_control *)kc->private_value;
dobj = &sm->dobj;
ret = audioreach_control_load_mix(scomp, scontrol, kc, hdr);
break;
case SND_SOC_AR_TPLG_VOL_CTL:
sm = (struct soc_mixer_control *)kc->private_value;
dobj = &sm->dobj;
break;
default:
dev_warn(scomp->dev, "control type not supported %d:%d:%d\n",
hdr->ops.get, hdr->ops.put, hdr->ops.info);
kfree(scontrol);
return -EINVAL;
}
dobj->private = scontrol;
return ret;
}
static int audioreach_control_unload(struct snd_soc_component *scomp,
struct snd_soc_dobj *dobj)
{
struct snd_ar_control *scontrol = dobj->private;
kfree(scontrol);
return 0;
}
static const struct snd_soc_tplg_kcontrol_ops audioreach_io_ops[] = {
{SND_SOC_AR_TPLG_FE_BE_GRAPH_CTL_MIX, audioreach_get_audio_mixer,
audioreach_put_audio_mixer, snd_soc_info_volsw},
{SND_SOC_AR_TPLG_VOL_CTL, audioreach_get_vol_ctrl_audio_mixer,
audioreach_put_vol_ctrl_audio_mixer, snd_soc_info_volsw},
};
static struct snd_soc_tplg_ops audioreach_tplg_ops = {
.io_ops = audioreach_io_ops,
.io_ops_count = ARRAY_SIZE(audioreach_io_ops),
.control_load = audioreach_control_load,
.control_unload = audioreach_control_unload,
.widget_ready = audioreach_widget_ready,
.widget_unload = audioreach_widget_unload,
.complete = audioreach_tplg_complete,
.link_load = audioreach_link_load,
.dapm_route_load = audioreach_route_load,
.dapm_route_unload = audioreach_route_unload,
};
int audioreach_tplg_init(struct snd_soc_component *component)
{
struct snd_soc_card *card = component->card;
struct device *dev = component->dev;
const struct firmware *fw;
char *tplg_fw_name;
int ret;
/* Inline with Qualcomm UCM configs and linux-firmware path */
tplg_fw_name = kasprintf(GFP_KERNEL, "qcom/%s/%s-tplg.bin", card->driver_name, card->name);
if (!tplg_fw_name)
return -ENOMEM;
ret = request_firmware(&fw, tplg_fw_name, dev);
if (ret < 0) {
dev_err(dev, "tplg firmware loading %s failed %d \n", tplg_fw_name, ret);
goto err;
}
ret = snd_soc_tplg_component_load(component, &audioreach_tplg_ops, fw);
if (ret < 0) {
if (ret != -EPROBE_DEFER)
dev_err(dev, "tplg component load failed: %d\n", ret);
}
release_firmware(fw);
err:
kfree(tplg_fw_name);
return ret;
}
EXPORT_SYMBOL_GPL(audioreach_tplg_init);
| linux-master | sound/soc/qcom/qdsp6/topology.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2011-2017, The Linux Foundation. All rights reserved.
// Copyright (c) 2018, Linaro Limited
#include <linux/slab.h>
#include <linux/wait.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/jiffies.h>
#include <linux/soc/qcom/apr.h>
#include "q6core.h"
#include "q6dsp-errno.h"
#define ADSP_STATE_READY_TIMEOUT_MS 3000
#define Q6_READY_TIMEOUT_MS 100
#define AVCS_CMD_ADSP_EVENT_GET_STATE 0x0001290C
#define AVCS_CMDRSP_ADSP_EVENT_GET_STATE 0x0001290D
#define AVCS_GET_VERSIONS 0x00012905
#define AVCS_GET_VERSIONS_RSP 0x00012906
#define AVCS_CMD_GET_FWK_VERSION 0x001292c
#define AVCS_CMDRSP_GET_FWK_VERSION 0x001292d
struct avcs_svc_info {
uint32_t service_id;
uint32_t version;
} __packed;
struct avcs_cmdrsp_get_version {
uint32_t build_id;
uint32_t num_services;
struct avcs_svc_info svc_api_info[];
} __packed;
/* for ADSP2.8 and above */
struct avcs_svc_api_info {
uint32_t service_id;
uint32_t api_version;
uint32_t api_branch_version;
} __packed;
struct avcs_cmdrsp_get_fwk_version {
uint32_t build_major_version;
uint32_t build_minor_version;
uint32_t build_branch_version;
uint32_t build_subbranch_version;
uint32_t num_services;
struct avcs_svc_api_info svc_api_info[];
} __packed;
struct q6core {
struct apr_device *adev;
wait_queue_head_t wait;
uint32_t avcs_state;
struct mutex lock;
bool resp_received;
uint32_t num_services;
struct avcs_cmdrsp_get_fwk_version *fwk_version;
struct avcs_cmdrsp_get_version *svc_version;
bool fwk_version_supported;
bool get_state_supported;
bool get_version_supported;
bool is_version_requested;
};
static struct q6core *g_core;
static int q6core_callback(struct apr_device *adev, struct apr_resp_pkt *data)
{
struct q6core *core = dev_get_drvdata(&adev->dev);
struct aprv2_ibasic_rsp_result_t *result;
struct apr_hdr *hdr = &data->hdr;
result = data->payload;
switch (hdr->opcode) {
case APR_BASIC_RSP_RESULT:{
result = data->payload;
switch (result->opcode) {
case AVCS_GET_VERSIONS:
if (result->status == ADSP_EUNSUPPORTED)
core->get_version_supported = false;
core->resp_received = true;
break;
case AVCS_CMD_GET_FWK_VERSION:
if (result->status == ADSP_EUNSUPPORTED)
core->fwk_version_supported = false;
core->resp_received = true;
break;
case AVCS_CMD_ADSP_EVENT_GET_STATE:
if (result->status == ADSP_EUNSUPPORTED)
core->get_state_supported = false;
core->resp_received = true;
break;
}
break;
}
case AVCS_CMDRSP_GET_FWK_VERSION: {
struct avcs_cmdrsp_get_fwk_version *fwk;
fwk = data->payload;
core->fwk_version = kmemdup(data->payload,
struct_size(fwk, svc_api_info,
fwk->num_services),
GFP_ATOMIC);
if (!core->fwk_version)
return -ENOMEM;
core->fwk_version_supported = true;
core->resp_received = true;
break;
}
case AVCS_GET_VERSIONS_RSP: {
struct avcs_cmdrsp_get_version *v;
v = data->payload;
core->svc_version = kmemdup(data->payload,
struct_size(v, svc_api_info,
v->num_services),
GFP_ATOMIC);
if (!core->svc_version)
return -ENOMEM;
core->get_version_supported = true;
core->resp_received = true;
break;
}
case AVCS_CMDRSP_ADSP_EVENT_GET_STATE:
core->get_state_supported = true;
core->avcs_state = result->opcode;
core->resp_received = true;
break;
default:
dev_err(&adev->dev, "Message id from adsp core svc: 0x%x\n",
hdr->opcode);
break;
}
if (core->resp_received)
wake_up(&core->wait);
return 0;
}
static int q6core_get_fwk_versions(struct q6core *core)
{
struct apr_device *adev = core->adev;
struct apr_pkt pkt;
int rc;
pkt.hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD,
APR_HDR_LEN(APR_HDR_SIZE), APR_PKT_VER);
pkt.hdr.pkt_size = APR_HDR_SIZE;
pkt.hdr.opcode = AVCS_CMD_GET_FWK_VERSION;
rc = apr_send_pkt(adev, &pkt);
if (rc < 0)
return rc;
rc = wait_event_timeout(core->wait, (core->resp_received),
msecs_to_jiffies(Q6_READY_TIMEOUT_MS));
if (rc > 0 && core->resp_received) {
core->resp_received = false;
if (!core->fwk_version_supported)
return -ENOTSUPP;
else
return 0;
}
return rc;
}
static int q6core_get_svc_versions(struct q6core *core)
{
struct apr_device *adev = core->adev;
struct apr_pkt pkt;
int rc;
pkt.hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD,
APR_HDR_LEN(APR_HDR_SIZE), APR_PKT_VER);
pkt.hdr.pkt_size = APR_HDR_SIZE;
pkt.hdr.opcode = AVCS_GET_VERSIONS;
rc = apr_send_pkt(adev, &pkt);
if (rc < 0)
return rc;
rc = wait_event_timeout(core->wait, (core->resp_received),
msecs_to_jiffies(Q6_READY_TIMEOUT_MS));
if (rc > 0 && core->resp_received) {
core->resp_received = false;
return 0;
}
return rc;
}
static bool __q6core_is_adsp_ready(struct q6core *core)
{
struct apr_device *adev = core->adev;
struct apr_pkt pkt;
int rc;
core->get_state_supported = false;
pkt.hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD,
APR_HDR_LEN(APR_HDR_SIZE), APR_PKT_VER);
pkt.hdr.pkt_size = APR_HDR_SIZE;
pkt.hdr.opcode = AVCS_CMD_ADSP_EVENT_GET_STATE;
rc = apr_send_pkt(adev, &pkt);
if (rc < 0)
return false;
rc = wait_event_timeout(core->wait, (core->resp_received),
msecs_to_jiffies(Q6_READY_TIMEOUT_MS));
if (rc > 0 && core->resp_received) {
core->resp_received = false;
if (core->avcs_state)
return true;
}
/* assume that the adsp is up if we not support this command */
if (!core->get_state_supported)
return true;
return false;
}
/**
* q6core_get_svc_api_info() - Get version number of a service.
*
* @svc_id: service id of the service.
* @ainfo: Valid struct pointer to fill svc api information.
*
* Return: zero on success and error code on failure or unsupported
*/
int q6core_get_svc_api_info(int svc_id, struct q6core_svc_api_info *ainfo)
{
int i;
int ret = -ENOTSUPP;
if (!g_core || !ainfo)
return 0;
mutex_lock(&g_core->lock);
if (!g_core->is_version_requested) {
if (q6core_get_fwk_versions(g_core) == -ENOTSUPP)
q6core_get_svc_versions(g_core);
g_core->is_version_requested = true;
}
if (g_core->fwk_version_supported) {
for (i = 0; i < g_core->fwk_version->num_services; i++) {
struct avcs_svc_api_info *info;
info = &g_core->fwk_version->svc_api_info[i];
if (svc_id != info->service_id)
continue;
ainfo->api_version = info->api_version;
ainfo->api_branch_version = info->api_branch_version;
ret = 0;
break;
}
} else if (g_core->get_version_supported) {
for (i = 0; i < g_core->svc_version->num_services; i++) {
struct avcs_svc_info *info;
info = &g_core->svc_version->svc_api_info[i];
if (svc_id != info->service_id)
continue;
ainfo->api_version = info->version;
ainfo->api_branch_version = 0;
ret = 0;
break;
}
}
mutex_unlock(&g_core->lock);
return ret;
}
EXPORT_SYMBOL_GPL(q6core_get_svc_api_info);
/**
* q6core_is_adsp_ready() - Get status of adsp
*
* Return: Will be an true if adsp is ready and false if not.
*/
bool q6core_is_adsp_ready(void)
{
unsigned long timeout;
bool ret = false;
if (!g_core)
return false;
mutex_lock(&g_core->lock);
timeout = jiffies + msecs_to_jiffies(ADSP_STATE_READY_TIMEOUT_MS);
for (;;) {
if (__q6core_is_adsp_ready(g_core)) {
ret = true;
break;
}
if (!time_after(timeout, jiffies)) {
ret = false;
break;
}
}
mutex_unlock(&g_core->lock);
return ret;
}
EXPORT_SYMBOL_GPL(q6core_is_adsp_ready);
static int q6core_probe(struct apr_device *adev)
{
g_core = kzalloc(sizeof(*g_core), GFP_KERNEL);
if (!g_core)
return -ENOMEM;
dev_set_drvdata(&adev->dev, g_core);
mutex_init(&g_core->lock);
g_core->adev = adev;
init_waitqueue_head(&g_core->wait);
return 0;
}
static void q6core_exit(struct apr_device *adev)
{
struct q6core *core = dev_get_drvdata(&adev->dev);
if (core->fwk_version_supported)
kfree(core->fwk_version);
if (core->get_version_supported)
kfree(core->svc_version);
g_core = NULL;
kfree(core);
}
#ifdef CONFIG_OF
static const struct of_device_id q6core_device_id[] = {
{ .compatible = "qcom,q6core" },
{},
};
MODULE_DEVICE_TABLE(of, q6core_device_id);
#endif
static struct apr_driver qcom_q6core_driver = {
.probe = q6core_probe,
.remove = q6core_exit,
.callback = q6core_callback,
.driver = {
.name = "qcom-q6core",
.of_match_table = of_match_ptr(q6core_device_id),
},
};
module_apr_driver(qcom_q6core_driver);
MODULE_DESCRIPTION("q6 core");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/qcom/qdsp6/q6core.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2011-2017, The Linux Foundation. All rights reserved.
// Copyright (c) 2018, Linaro Limited
#include <linux/device.h>
#include <linux/jiffies.h>
#include <linux/kernel.h>
#include <linux/kref.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/soc/qcom/apr.h>
#include <linux/wait.h>
#include <sound/asound.h>
#include "q6adm.h"
#include "q6afe.h"
#include "q6core.h"
#include "q6dsp-common.h"
#include "q6dsp-errno.h"
#define ADM_CMD_DEVICE_OPEN_V5 0x00010326
#define ADM_CMDRSP_DEVICE_OPEN_V5 0x00010329
#define ADM_CMD_DEVICE_CLOSE_V5 0x00010327
#define ADM_CMD_MATRIX_MAP_ROUTINGS_V5 0x00010325
#define TIMEOUT_MS 1000
#define RESET_COPP_ID 99
#define INVALID_COPP_ID 0xFF
/* Definition for a legacy device session. */
#define ADM_LEGACY_DEVICE_SESSION 0
#define ADM_MATRIX_ID_AUDIO_RX 0
#define ADM_MATRIX_ID_AUDIO_TX 1
struct q6copp {
int afe_port;
int copp_idx;
int id;
int topology;
int mode;
int rate;
int bit_width;
int channels;
int app_type;
int acdb_id;
struct aprv2_ibasic_rsp_result_t result;
struct kref refcount;
wait_queue_head_t wait;
struct list_head node;
struct q6adm *adm;
};
struct q6adm {
struct apr_device *apr;
struct device *dev;
struct q6core_svc_api_info ainfo;
unsigned long copp_bitmap[AFE_MAX_PORTS];
struct list_head copps_list;
spinlock_t copps_list_lock;
struct aprv2_ibasic_rsp_result_t result;
struct mutex lock;
wait_queue_head_t matrix_map_wait;
};
struct q6adm_cmd_device_open_v5 {
u16 flags;
u16 mode_of_operation;
u16 endpoint_id_1;
u16 endpoint_id_2;
u32 topology_id;
u16 dev_num_channel;
u16 bit_width;
u32 sample_rate;
u8 dev_channel_mapping[8];
} __packed;
struct q6adm_cmd_matrix_map_routings_v5 {
u32 matrix_id;
u32 num_sessions;
} __packed;
struct q6adm_session_map_node_v5 {
u16 session_id;
u16 num_copps;
} __packed;
static struct q6copp *q6adm_find_copp(struct q6adm *adm, int port_idx,
int copp_idx)
{
struct q6copp *c;
struct q6copp *ret = NULL;
unsigned long flags;
spin_lock_irqsave(&adm->copps_list_lock, flags);
list_for_each_entry(c, &adm->copps_list, node) {
if ((port_idx == c->afe_port) && (copp_idx == c->copp_idx)) {
ret = c;
kref_get(&c->refcount);
break;
}
}
spin_unlock_irqrestore(&adm->copps_list_lock, flags);
return ret;
}
static void q6adm_free_copp(struct kref *ref)
{
struct q6copp *c = container_of(ref, struct q6copp, refcount);
struct q6adm *adm = c->adm;
unsigned long flags;
spin_lock_irqsave(&adm->copps_list_lock, flags);
clear_bit(c->copp_idx, &adm->copp_bitmap[c->afe_port]);
list_del(&c->node);
spin_unlock_irqrestore(&adm->copps_list_lock, flags);
kfree(c);
}
static int q6adm_callback(struct apr_device *adev, struct apr_resp_pkt *data)
{
struct aprv2_ibasic_rsp_result_t *result = data->payload;
int port_idx, copp_idx;
struct apr_hdr *hdr = &data->hdr;
struct q6copp *copp;
struct q6adm *adm = dev_get_drvdata(&adev->dev);
if (!data->payload_size)
return 0;
copp_idx = (hdr->token) & 0XFF;
port_idx = ((hdr->token) >> 16) & 0xFF;
if (port_idx < 0 || port_idx >= AFE_MAX_PORTS) {
dev_err(&adev->dev, "Invalid port idx %d token %d\n",
port_idx, hdr->token);
return 0;
}
if (copp_idx < 0 || copp_idx >= MAX_COPPS_PER_PORT) {
dev_err(&adev->dev, "Invalid copp idx %d token %d\n",
copp_idx, hdr->token);
return 0;
}
switch (hdr->opcode) {
case APR_BASIC_RSP_RESULT: {
if (result->status != 0) {
dev_err(&adev->dev, "cmd = 0x%x return error = 0x%x\n",
result->opcode, result->status);
}
switch (result->opcode) {
case ADM_CMD_DEVICE_OPEN_V5:
case ADM_CMD_DEVICE_CLOSE_V5:
copp = q6adm_find_copp(adm, port_idx, copp_idx);
if (!copp)
return 0;
copp->result = *result;
wake_up(&copp->wait);
kref_put(&copp->refcount, q6adm_free_copp);
break;
case ADM_CMD_MATRIX_MAP_ROUTINGS_V5:
adm->result = *result;
wake_up(&adm->matrix_map_wait);
break;
default:
dev_err(&adev->dev, "Unknown Cmd: 0x%x\n",
result->opcode);
break;
}
return 0;
}
case ADM_CMDRSP_DEVICE_OPEN_V5: {
struct adm_cmd_rsp_device_open_v5 {
u32 status;
u16 copp_id;
u16 reserved;
} __packed *open = data->payload;
copp = q6adm_find_copp(adm, port_idx, copp_idx);
if (!copp)
return 0;
if (open->copp_id == INVALID_COPP_ID) {
dev_err(&adev->dev, "Invalid coppid rxed %d\n",
open->copp_id);
copp->result.status = ADSP_EBADPARAM;
wake_up(&copp->wait);
kref_put(&copp->refcount, q6adm_free_copp);
break;
}
copp->result.opcode = hdr->opcode;
copp->id = open->copp_id;
wake_up(&copp->wait);
kref_put(&copp->refcount, q6adm_free_copp);
}
break;
default:
dev_err(&adev->dev, "Unknown cmd:0x%x\n",
hdr->opcode);
break;
}
return 0;
}
static struct q6copp *q6adm_alloc_copp(struct q6adm *adm, int port_idx)
{
struct q6copp *c;
int idx;
idx = find_first_zero_bit(&adm->copp_bitmap[port_idx],
MAX_COPPS_PER_PORT);
if (idx >= MAX_COPPS_PER_PORT)
return ERR_PTR(-EBUSY);
c = kzalloc(sizeof(*c), GFP_ATOMIC);
if (!c)
return ERR_PTR(-ENOMEM);
set_bit(idx, &adm->copp_bitmap[port_idx]);
c->copp_idx = idx;
c->afe_port = port_idx;
c->adm = adm;
init_waitqueue_head(&c->wait);
return c;
}
static int q6adm_apr_send_copp_pkt(struct q6adm *adm, struct q6copp *copp,
struct apr_pkt *pkt, uint32_t rsp_opcode)
{
struct device *dev = adm->dev;
uint32_t opcode = pkt->hdr.opcode;
int ret;
mutex_lock(&adm->lock);
copp->result.opcode = 0;
copp->result.status = 0;
ret = apr_send_pkt(adm->apr, pkt);
if (ret < 0) {
dev_err(dev, "Failed to send APR packet\n");
ret = -EINVAL;
goto err;
}
/* Wait for the callback with copp id */
if (rsp_opcode)
ret = wait_event_timeout(copp->wait,
(copp->result.opcode == opcode) ||
(copp->result.opcode == rsp_opcode),
msecs_to_jiffies(TIMEOUT_MS));
else
ret = wait_event_timeout(copp->wait,
(copp->result.opcode == opcode),
msecs_to_jiffies(TIMEOUT_MS));
if (!ret) {
dev_err(dev, "ADM copp cmd timedout\n");
ret = -ETIMEDOUT;
} else if (copp->result.status > 0) {
dev_err(dev, "DSP returned error[%d]\n",
copp->result.status);
ret = -EINVAL;
}
err:
mutex_unlock(&adm->lock);
return ret;
}
static int q6adm_device_close(struct q6adm *adm, struct q6copp *copp,
int port_id, int copp_idx)
{
struct apr_pkt close;
close.hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD,
APR_HDR_LEN(APR_HDR_SIZE),
APR_PKT_VER);
close.hdr.pkt_size = sizeof(close);
close.hdr.src_port = port_id;
close.hdr.dest_port = copp->id;
close.hdr.token = port_id << 16 | copp_idx;
close.hdr.opcode = ADM_CMD_DEVICE_CLOSE_V5;
return q6adm_apr_send_copp_pkt(adm, copp, &close, 0);
}
static struct q6copp *q6adm_find_matching_copp(struct q6adm *adm,
int port_id, int topology,
int mode, int rate,
int channel_mode, int bit_width,
int app_type)
{
struct q6copp *c;
struct q6copp *ret = NULL;
unsigned long flags;
spin_lock_irqsave(&adm->copps_list_lock, flags);
list_for_each_entry(c, &adm->copps_list, node) {
if ((port_id == c->afe_port) && (topology == c->topology) &&
(mode == c->mode) && (rate == c->rate) &&
(bit_width == c->bit_width) && (app_type == c->app_type)) {
ret = c;
kref_get(&c->refcount);
}
}
spin_unlock_irqrestore(&adm->copps_list_lock, flags);
return ret;
}
static int q6adm_device_open(struct q6adm *adm, struct q6copp *copp,
int port_id, int path, int topology,
int channel_mode, int bit_width, int rate)
{
struct q6adm_cmd_device_open_v5 *open;
int afe_port = q6afe_get_port_id(port_id);
struct apr_pkt *pkt;
void *p;
int ret, pkt_size;
pkt_size = APR_HDR_SIZE + sizeof(*open);
p = kzalloc(pkt_size, GFP_KERNEL);
if (!p)
return -ENOMEM;
pkt = p;
open = p + APR_HDR_SIZE;
pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD,
APR_HDR_LEN(APR_HDR_SIZE),
APR_PKT_VER);
pkt->hdr.pkt_size = pkt_size;
pkt->hdr.src_port = afe_port;
pkt->hdr.dest_port = afe_port;
pkt->hdr.token = port_id << 16 | copp->copp_idx;
pkt->hdr.opcode = ADM_CMD_DEVICE_OPEN_V5;
open->flags = ADM_LEGACY_DEVICE_SESSION;
open->mode_of_operation = path;
open->endpoint_id_1 = afe_port;
open->topology_id = topology;
open->dev_num_channel = channel_mode & 0x00FF;
open->bit_width = bit_width;
open->sample_rate = rate;
ret = q6dsp_map_channels(&open->dev_channel_mapping[0],
channel_mode);
if (ret)
goto err;
ret = q6adm_apr_send_copp_pkt(adm, copp, pkt,
ADM_CMDRSP_DEVICE_OPEN_V5);
err:
kfree(pkt);
return ret;
}
/**
* q6adm_open() - open adm and grab a free copp
*
* @dev: Pointer to adm child device.
* @port_id: port id
* @path: playback or capture path.
* @rate: rate at which copp is required.
* @channel_mode: channel mode
* @topology: adm topology id
* @perf_mode: performace mode.
* @bit_width: audio sample bit width
* @app_type: Application type.
* @acdb_id: ACDB id
*
* Return: Will be an negative on error or a valid copp pointer on success.
*/
struct q6copp *q6adm_open(struct device *dev, int port_id, int path, int rate,
int channel_mode, int topology, int perf_mode,
uint16_t bit_width, int app_type, int acdb_id)
{
struct q6adm *adm = dev_get_drvdata(dev->parent);
struct q6copp *copp;
unsigned long flags;
int ret = 0;
if (port_id < 0) {
dev_err(dev, "Invalid port_id %d\n", port_id);
return ERR_PTR(-EINVAL);
}
copp = q6adm_find_matching_copp(adm, port_id, topology, perf_mode,
rate, channel_mode, bit_width, app_type);
if (copp) {
dev_err(dev, "Found Matching Copp 0x%x\n", copp->copp_idx);
return copp;
}
spin_lock_irqsave(&adm->copps_list_lock, flags);
copp = q6adm_alloc_copp(adm, port_id);
if (IS_ERR(copp)) {
spin_unlock_irqrestore(&adm->copps_list_lock, flags);
return ERR_CAST(copp);
}
list_add_tail(&copp->node, &adm->copps_list);
spin_unlock_irqrestore(&adm->copps_list_lock, flags);
kref_init(&copp->refcount);
copp->topology = topology;
copp->mode = perf_mode;
copp->rate = rate;
copp->channels = channel_mode;
copp->bit_width = bit_width;
copp->app_type = app_type;
ret = q6adm_device_open(adm, copp, port_id, path, topology,
channel_mode, bit_width, rate);
if (ret < 0) {
kref_put(&copp->refcount, q6adm_free_copp);
return ERR_PTR(ret);
}
return copp;
}
EXPORT_SYMBOL_GPL(q6adm_open);
/**
* q6adm_get_copp_id() - get copp index
*
* @copp: Pointer to valid copp
*
* Return: Will be an negative on error or a valid copp index on success.
**/
int q6adm_get_copp_id(struct q6copp *copp)
{
if (!copp)
return -EINVAL;
return copp->copp_idx;
}
EXPORT_SYMBOL_GPL(q6adm_get_copp_id);
/**
* q6adm_matrix_map() - Map asm streams and afe ports using payload
*
* @dev: Pointer to adm child device.
* @path: playback or capture path.
* @payload_map: map between session id and afe ports.
* @perf_mode: Performace mode.
*
* Return: Will be an negative on error or a zero on success.
*/
int q6adm_matrix_map(struct device *dev, int path,
struct route_payload payload_map, int perf_mode)
{
struct q6adm *adm = dev_get_drvdata(dev->parent);
struct q6adm_cmd_matrix_map_routings_v5 *route;
struct q6adm_session_map_node_v5 *node;
struct apr_pkt *pkt;
uint16_t *copps_list;
int pkt_size, ret, i, copp_idx;
void *matrix_map;
struct q6copp *copp;
/* Assumes port_ids have already been validated during adm_open */
pkt_size = (APR_HDR_SIZE + sizeof(*route) + sizeof(*node) +
(sizeof(uint32_t) * payload_map.num_copps));
matrix_map = kzalloc(pkt_size, GFP_KERNEL);
if (!matrix_map)
return -ENOMEM;
pkt = matrix_map;
route = matrix_map + APR_HDR_SIZE;
node = matrix_map + APR_HDR_SIZE + sizeof(*route);
copps_list = matrix_map + APR_HDR_SIZE + sizeof(*route) + sizeof(*node);
pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD,
APR_HDR_LEN(APR_HDR_SIZE),
APR_PKT_VER);
pkt->hdr.pkt_size = pkt_size;
pkt->hdr.token = 0;
pkt->hdr.opcode = ADM_CMD_MATRIX_MAP_ROUTINGS_V5;
route->num_sessions = 1;
switch (path) {
case ADM_PATH_PLAYBACK:
route->matrix_id = ADM_MATRIX_ID_AUDIO_RX;
break;
case ADM_PATH_LIVE_REC:
route->matrix_id = ADM_MATRIX_ID_AUDIO_TX;
break;
default:
dev_err(dev, "Wrong path set[%d]\n", path);
break;
}
node->session_id = payload_map.session_id;
node->num_copps = payload_map.num_copps;
for (i = 0; i < payload_map.num_copps; i++) {
int port_idx = payload_map.port_id[i];
if (port_idx < 0) {
dev_err(dev, "Invalid port_id %d\n",
payload_map.port_id[i]);
kfree(pkt);
return -EINVAL;
}
copp_idx = payload_map.copp_idx[i];
copp = q6adm_find_copp(adm, port_idx, copp_idx);
if (!copp) {
kfree(pkt);
return -EINVAL;
}
copps_list[i] = copp->id;
kref_put(&copp->refcount, q6adm_free_copp);
}
mutex_lock(&adm->lock);
adm->result.status = 0;
adm->result.opcode = 0;
ret = apr_send_pkt(adm->apr, pkt);
if (ret < 0) {
dev_err(dev, "routing for stream %d failed ret %d\n",
payload_map.session_id, ret);
goto fail_cmd;
}
ret = wait_event_timeout(adm->matrix_map_wait,
adm->result.opcode == pkt->hdr.opcode,
msecs_to_jiffies(TIMEOUT_MS));
if (!ret) {
dev_err(dev, "routing for stream %d failed\n",
payload_map.session_id);
ret = -ETIMEDOUT;
goto fail_cmd;
} else if (adm->result.status > 0) {
dev_err(dev, "DSP returned error[%d]\n",
adm->result.status);
ret = -EINVAL;
goto fail_cmd;
}
fail_cmd:
mutex_unlock(&adm->lock);
kfree(pkt);
return ret;
}
EXPORT_SYMBOL_GPL(q6adm_matrix_map);
/**
* q6adm_close() - Close adm copp
*
* @dev: Pointer to adm child device.
* @copp: pointer to previously opened copp
*
* Return: Will be an negative on error or a zero on success.
*/
int q6adm_close(struct device *dev, struct q6copp *copp)
{
struct q6adm *adm = dev_get_drvdata(dev->parent);
int ret = 0;
ret = q6adm_device_close(adm, copp, copp->afe_port, copp->copp_idx);
if (ret < 0) {
dev_err(adm->dev, "Failed to close copp %d\n", ret);
return ret;
}
kref_put(&copp->refcount, q6adm_free_copp);
return 0;
}
EXPORT_SYMBOL_GPL(q6adm_close);
static int q6adm_probe(struct apr_device *adev)
{
struct device *dev = &adev->dev;
struct q6adm *adm;
adm = devm_kzalloc(dev, sizeof(*adm), GFP_KERNEL);
if (!adm)
return -ENOMEM;
adm->apr = adev;
dev_set_drvdata(dev, adm);
adm->dev = dev;
q6core_get_svc_api_info(adev->svc_id, &adm->ainfo);
mutex_init(&adm->lock);
init_waitqueue_head(&adm->matrix_map_wait);
INIT_LIST_HEAD(&adm->copps_list);
spin_lock_init(&adm->copps_list_lock);
return devm_of_platform_populate(dev);
}
#ifdef CONFIG_OF
static const struct of_device_id q6adm_device_id[] = {
{ .compatible = "qcom,q6adm" },
{},
};
MODULE_DEVICE_TABLE(of, q6adm_device_id);
#endif
static struct apr_driver qcom_q6adm_driver = {
.probe = q6adm_probe,
.callback = q6adm_callback,
.driver = {
.name = "qcom-q6adm",
.of_match_table = of_match_ptr(q6adm_device_id),
},
};
module_apr_driver(qcom_q6adm_driver);
MODULE_DESCRIPTION("Q6 Audio Device Manager");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/qcom/qdsp6/q6adm.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2020, Linaro Limited
#include <linux/err.h>
#include <linux/init.h>
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/slab.h>
#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
#include "q6dsp-lpass-clocks.h"
#define Q6DSP_MAX_CLK_ID 104
#define Q6DSP_LPASS_CLK_ROOT_DEFAULT 0
struct q6dsp_clk {
struct device *dev;
int q6dsp_clk_id;
int attributes;
int rate;
uint32_t handle;
struct clk_hw hw;
};
#define to_q6dsp_clk(_hw) container_of(_hw, struct q6dsp_clk, hw)
struct q6dsp_cc {
struct device *dev;
struct q6dsp_clk *clks[Q6DSP_MAX_CLK_ID];
const struct q6dsp_clk_desc *desc;
};
static int clk_q6dsp_prepare(struct clk_hw *hw)
{
struct q6dsp_clk *clk = to_q6dsp_clk(hw);
struct q6dsp_cc *cc = dev_get_drvdata(clk->dev);
return cc->desc->lpass_set_clk(clk->dev, clk->q6dsp_clk_id, clk->attributes,
Q6DSP_LPASS_CLK_ROOT_DEFAULT, clk->rate);
}
static void clk_q6dsp_unprepare(struct clk_hw *hw)
{
struct q6dsp_clk *clk = to_q6dsp_clk(hw);
struct q6dsp_cc *cc = dev_get_drvdata(clk->dev);
cc->desc->lpass_set_clk(clk->dev, clk->q6dsp_clk_id, clk->attributes,
Q6DSP_LPASS_CLK_ROOT_DEFAULT, 0);
}
static int clk_q6dsp_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct q6dsp_clk *clk = to_q6dsp_clk(hw);
clk->rate = rate;
return 0;
}
static unsigned long clk_q6dsp_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct q6dsp_clk *clk = to_q6dsp_clk(hw);
return clk->rate;
}
static long clk_q6dsp_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{
return rate;
}
static const struct clk_ops clk_q6dsp_ops = {
.prepare = clk_q6dsp_prepare,
.unprepare = clk_q6dsp_unprepare,
.set_rate = clk_q6dsp_set_rate,
.round_rate = clk_q6dsp_round_rate,
.recalc_rate = clk_q6dsp_recalc_rate,
};
static int clk_vote_q6dsp_block(struct clk_hw *hw)
{
struct q6dsp_clk *clk = to_q6dsp_clk(hw);
struct q6dsp_cc *cc = dev_get_drvdata(clk->dev);
return cc->desc->lpass_vote_clk(clk->dev, clk->q6dsp_clk_id,
clk_hw_get_name(&clk->hw), &clk->handle);
}
static void clk_unvote_q6dsp_block(struct clk_hw *hw)
{
struct q6dsp_clk *clk = to_q6dsp_clk(hw);
struct q6dsp_cc *cc = dev_get_drvdata(clk->dev);
cc->desc->lpass_unvote_clk(clk->dev, clk->q6dsp_clk_id, clk->handle);
}
static const struct clk_ops clk_vote_q6dsp_ops = {
.prepare = clk_vote_q6dsp_block,
.unprepare = clk_unvote_q6dsp_block,
};
static struct clk_hw *q6dsp_of_clk_hw_get(struct of_phandle_args *clkspec,
void *data)
{
struct q6dsp_cc *cc = data;
unsigned int idx = clkspec->args[0];
unsigned int attr = clkspec->args[1];
if (idx >= Q6DSP_MAX_CLK_ID || attr > LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR) {
dev_err(cc->dev, "Invalid clk specifier (%d, %d)\n", idx, attr);
return ERR_PTR(-EINVAL);
}
if (cc->clks[idx]) {
cc->clks[idx]->attributes = attr;
return &cc->clks[idx]->hw;
}
return ERR_PTR(-ENOENT);
}
int q6dsp_clock_dev_probe(struct platform_device *pdev)
{
struct q6dsp_cc *cc;
struct device *dev = &pdev->dev;
const struct q6dsp_clk_init *q6dsp_clks;
const struct q6dsp_clk_desc *desc;
int i, ret;
cc = devm_kzalloc(dev, sizeof(*cc), GFP_KERNEL);
if (!cc)
return -ENOMEM;
desc = of_device_get_match_data(&pdev->dev);
if (!desc)
return -EINVAL;
cc->desc = desc;
cc->dev = dev;
q6dsp_clks = desc->clks;
for (i = 0; i < desc->num_clks; i++) {
unsigned int id = q6dsp_clks[i].clk_id;
struct clk_init_data init = {
.name = q6dsp_clks[i].name,
};
struct q6dsp_clk *clk;
clk = devm_kzalloc(dev, sizeof(*clk), GFP_KERNEL);
if (!clk)
return -ENOMEM;
clk->dev = dev;
clk->q6dsp_clk_id = q6dsp_clks[i].q6dsp_clk_id;
clk->rate = q6dsp_clks[i].rate;
clk->hw.init = &init;
if (clk->rate)
init.ops = &clk_q6dsp_ops;
else
init.ops = &clk_vote_q6dsp_ops;
cc->clks[id] = clk;
ret = devm_clk_hw_register(dev, &clk->hw);
if (ret)
return ret;
}
ret = devm_of_clk_add_hw_provider(dev, q6dsp_of_clk_hw_get, cc);
if (ret)
return ret;
dev_set_drvdata(dev, cc);
return 0;
}
EXPORT_SYMBOL_GPL(q6dsp_clock_dev_probe);
| linux-master | sound/soc/qcom/qdsp6/q6dsp-lpass-clocks.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2011-2017, The Linux Foundation. All rights reserved.
// Copyright (c) 2018, Linaro Limited
#include <linux/init.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of_platform.h>
#include <linux/bitops.h>
#include <linux/mutex.h>
#include <linux/of_device.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/pcm.h>
#include <sound/control.h>
#include <sound/asound.h>
#include <sound/pcm_params.h>
#include "q6afe.h"
#include "q6asm.h"
#include "q6adm.h"
#include "q6routing.h"
#define DRV_NAME "q6routing-component"
#define Q6ROUTING_RX_MIXERS(id) \
SOC_SINGLE_EXT("MultiMedia1", id, \
MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer,\
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("MultiMedia2", id, \
MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer,\
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("MultiMedia3", id, \
MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer,\
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("MultiMedia4", id, \
MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer,\
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("MultiMedia5", id, \
MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer,\
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("MultiMedia6", id, \
MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer,\
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("MultiMedia7", id, \
MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer,\
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("MultiMedia8", id, \
MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer,\
msm_routing_put_audio_mixer),
#define Q6ROUTING_RX_DAPM_ROUTE(mix_name, s) \
{ mix_name, "MultiMedia1", "MM_DL1" }, \
{ mix_name, "MultiMedia2", "MM_DL2" }, \
{ mix_name, "MultiMedia3", "MM_DL3" }, \
{ mix_name, "MultiMedia4", "MM_DL4" }, \
{ mix_name, "MultiMedia5", "MM_DL5" }, \
{ mix_name, "MultiMedia6", "MM_DL6" }, \
{ mix_name, "MultiMedia7", "MM_DL7" }, \
{ mix_name, "MultiMedia8", "MM_DL8" }, \
{ s, NULL, mix_name }
#define Q6ROUTING_TX_DAPM_ROUTE(mix_name) \
{ mix_name, "PRI_MI2S_TX", "PRI_MI2S_TX" }, \
{ mix_name, "SEC_MI2S_TX", "SEC_MI2S_TX" }, \
{ mix_name, "QUAT_MI2S_TX", "QUAT_MI2S_TX" }, \
{ mix_name, "QUIN_MI2S_TX", "QUIN_MI2S_TX" }, \
{ mix_name, "TERT_MI2S_TX", "TERT_MI2S_TX" }, \
{ mix_name, "SLIMBUS_0_TX", "SLIMBUS_0_TX" }, \
{ mix_name, "SLIMBUS_1_TX", "SLIMBUS_1_TX" }, \
{ mix_name, "SLIMBUS_2_TX", "SLIMBUS_2_TX" }, \
{ mix_name, "SLIMBUS_3_TX", "SLIMBUS_3_TX" }, \
{ mix_name, "SLIMBUS_4_TX", "SLIMBUS_4_TX" }, \
{ mix_name, "SLIMBUS_5_TX", "SLIMBUS_5_TX" }, \
{ mix_name, "SLIMBUS_6_TX", "SLIMBUS_6_TX" }, \
{ mix_name, "PRIMARY_TDM_TX_0", "PRIMARY_TDM_TX_0"}, \
{ mix_name, "PRIMARY_TDM_TX_1", "PRIMARY_TDM_TX_1"}, \
{ mix_name, "PRIMARY_TDM_TX_2", "PRIMARY_TDM_TX_2"}, \
{ mix_name, "PRIMARY_TDM_TX_3", "PRIMARY_TDM_TX_3"}, \
{ mix_name, "PRIMARY_TDM_TX_4", "PRIMARY_TDM_TX_4"}, \
{ mix_name, "PRIMARY_TDM_TX_5", "PRIMARY_TDM_TX_5"}, \
{ mix_name, "PRIMARY_TDM_TX_6", "PRIMARY_TDM_TX_6"}, \
{ mix_name, "PRIMARY_TDM_TX_7", "PRIMARY_TDM_TX_7"}, \
{ mix_name, "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, \
{ mix_name, "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, \
{ mix_name, "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, \
{ mix_name, "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, \
{ mix_name, "SEC_TDM_TX_4", "SEC_TDM_TX_4"}, \
{ mix_name, "SEC_TDM_TX_5", "SEC_TDM_TX_5"}, \
{ mix_name, "SEC_TDM_TX_6", "SEC_TDM_TX_6"}, \
{ mix_name, "SEC_TDM_TX_7", "SEC_TDM_TX_7"}, \
{ mix_name, "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, \
{ mix_name, "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, \
{ mix_name, "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, \
{ mix_name, "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, \
{ mix_name, "TERT_TDM_TX_4", "TERT_TDM_TX_4"}, \
{ mix_name, "TERT_TDM_TX_5", "TERT_TDM_TX_5"}, \
{ mix_name, "TERT_TDM_TX_6", "TERT_TDM_TX_6"}, \
{ mix_name, "TERT_TDM_TX_7", "TERT_TDM_TX_7"}, \
{ mix_name, "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, \
{ mix_name, "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, \
{ mix_name, "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, \
{ mix_name, "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, \
{ mix_name, "QUAT_TDM_TX_4", "QUAT_TDM_TX_4"}, \
{ mix_name, "QUAT_TDM_TX_5", "QUAT_TDM_TX_5"}, \
{ mix_name, "QUAT_TDM_TX_6", "QUAT_TDM_TX_6"}, \
{ mix_name, "QUAT_TDM_TX_7", "QUAT_TDM_TX_7"}, \
{ mix_name, "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, \
{ mix_name, "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, \
{ mix_name, "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, \
{ mix_name, "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, \
{ mix_name, "QUIN_TDM_TX_4", "QUIN_TDM_TX_4"}, \
{ mix_name, "QUIN_TDM_TX_5", "QUIN_TDM_TX_5"}, \
{ mix_name, "QUIN_TDM_TX_6", "QUIN_TDM_TX_6"}, \
{ mix_name, "QUIN_TDM_TX_7", "QUIN_TDM_TX_7"}, \
{ mix_name, "WSA_CODEC_DMA_TX_0", "WSA_CODEC_DMA_TX_0"}, \
{ mix_name, "WSA_CODEC_DMA_TX_1", "WSA_CODEC_DMA_TX_1"}, \
{ mix_name, "WSA_CODEC_DMA_TX_2", "WSA_CODEC_DMA_TX_2"}, \
{ mix_name, "VA_CODEC_DMA_TX_0", "VA_CODEC_DMA_TX_0"}, \
{ mix_name, "VA_CODEC_DMA_TX_1", "VA_CODEC_DMA_TX_1"}, \
{ mix_name, "VA_CODEC_DMA_TX_2", "VA_CODEC_DMA_TX_2"}, \
{ mix_name, "TX_CODEC_DMA_TX_0", "TX_CODEC_DMA_TX_0"}, \
{ mix_name, "TX_CODEC_DMA_TX_1", "TX_CODEC_DMA_TX_1"}, \
{ mix_name, "TX_CODEC_DMA_TX_2", "TX_CODEC_DMA_TX_2"}, \
{ mix_name, "TX_CODEC_DMA_TX_3", "TX_CODEC_DMA_TX_3"}, \
{ mix_name, "TX_CODEC_DMA_TX_4", "TX_CODEC_DMA_TX_4"}, \
{ mix_name, "TX_CODEC_DMA_TX_5", "TX_CODEC_DMA_TX_5"}
#define Q6ROUTING_TX_MIXERS(id) \
SOC_SINGLE_EXT("PRI_MI2S_TX", PRIMARY_MI2S_TX, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("SEC_MI2S_TX", SECONDARY_MI2S_TX, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("TERT_MI2S_TX", TERTIARY_MI2S_TX, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("QUAT_MI2S_TX", QUATERNARY_MI2S_TX, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("QUIN_MI2S_TX", QUINARY_MI2S_TX, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("SLIMBUS_0_TX", SLIMBUS_0_TX, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("SLIMBUS_1_TX", SLIMBUS_1_TX, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("SLIMBUS_2_TX", SLIMBUS_2_TX, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("SLIMBUS_3_TX", SLIMBUS_3_TX, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("SLIMBUS_4_TX", SLIMBUS_4_TX, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("SLIMBUS_5_TX", SLIMBUS_5_TX, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("SLIMBUS_6_TX", SLIMBUS_6_TX, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("PRIMARY_TDM_TX_0", PRIMARY_TDM_TX_0, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("PRIMARY_TDM_TX_1", PRIMARY_TDM_TX_1, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("PRIMARY_TDM_TX_2", PRIMARY_TDM_TX_2, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("PRIMARY_TDM_TX_3", PRIMARY_TDM_TX_3, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("PRIMARY_TDM_TX_4", PRIMARY_TDM_TX_4, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("PRIMARY_TDM_TX_5", PRIMARY_TDM_TX_5, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("PRIMARY_TDM_TX_6", PRIMARY_TDM_TX_6, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("PRIMARY_TDM_TX_7", PRIMARY_TDM_TX_7, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("SEC_TDM_TX_0", SECONDARY_TDM_TX_0, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("SEC_TDM_TX_1", SECONDARY_TDM_TX_1, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("SEC_TDM_TX_2", SECONDARY_TDM_TX_2, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("SEC_TDM_TX_3", SECONDARY_TDM_TX_3, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("SEC_TDM_TX_4", SECONDARY_TDM_TX_4, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("SEC_TDM_TX_5", SECONDARY_TDM_TX_5, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("SEC_TDM_TX_6", SECONDARY_TDM_TX_6, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("SEC_TDM_TX_7", SECONDARY_TDM_TX_7, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("TERT_TDM_TX_0", TERTIARY_TDM_TX_0, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("TERT_TDM_TX_1", TERTIARY_TDM_TX_1, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("TERT_TDM_TX_2", TERTIARY_TDM_TX_2, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("TERT_TDM_TX_3", TERTIARY_TDM_TX_3, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("TERT_TDM_TX_4", TERTIARY_TDM_TX_4, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("TERT_TDM_TX_5", TERTIARY_TDM_TX_5, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("TERT_TDM_TX_6", TERTIARY_TDM_TX_6, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("TERT_TDM_TX_7", TERTIARY_TDM_TX_7, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("QUAT_TDM_TX_0", QUATERNARY_TDM_TX_0, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("QUAT_TDM_TX_1", QUATERNARY_TDM_TX_1, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("QUAT_TDM_TX_2", QUATERNARY_TDM_TX_2, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("QUAT_TDM_TX_3", QUATERNARY_TDM_TX_3, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("QUAT_TDM_TX_4", QUATERNARY_TDM_TX_4, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("QUAT_TDM_TX_5", QUATERNARY_TDM_TX_5, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("QUAT_TDM_TX_6", QUATERNARY_TDM_TX_6, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("QUAT_TDM_TX_7", QUATERNARY_TDM_TX_7, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("QUIN_TDM_TX_0", QUINARY_TDM_TX_0, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("QUIN_TDM_TX_1", QUINARY_TDM_TX_1, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("QUIN_TDM_TX_2", QUINARY_TDM_TX_2, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("QUIN_TDM_TX_3", QUINARY_TDM_TX_3, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("QUIN_TDM_TX_4", QUINARY_TDM_TX_4, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("QUIN_TDM_TX_5", QUINARY_TDM_TX_5, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("QUIN_TDM_TX_6", QUINARY_TDM_TX_6, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("QUIN_TDM_TX_7", QUINARY_TDM_TX_7, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("WSA_CODEC_DMA_TX_0", WSA_CODEC_DMA_TX_0, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("WSA_CODEC_DMA_TX_1", WSA_CODEC_DMA_TX_1, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("WSA_CODEC_DMA_TX_2", WSA_CODEC_DMA_TX_2, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("VA_CODEC_DMA_TX_0", VA_CODEC_DMA_TX_0, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("VA_CODEC_DMA_TX_1", VA_CODEC_DMA_TX_1, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("VA_CODEC_DMA_TX_2", VA_CODEC_DMA_TX_2, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("TX_CODEC_DMA_TX_0", TX_CODEC_DMA_TX_0, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("TX_CODEC_DMA_TX_1", TX_CODEC_DMA_TX_1, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("TX_CODEC_DMA_TX_2", TX_CODEC_DMA_TX_2, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("TX_CODEC_DMA_TX_3", TX_CODEC_DMA_TX_3, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("TX_CODEC_DMA_TX_4", TX_CODEC_DMA_TX_4, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer), \
SOC_SINGLE_EXT("TX_CODEC_DMA_TX_5", TX_CODEC_DMA_TX_5, \
id, 1, 0, msm_routing_get_audio_mixer, \
msm_routing_put_audio_mixer),
struct session_data {
int state;
int port_id;
int path_type;
int app_type;
int acdb_id;
int sample_rate;
int bits_per_sample;
int channels;
int perf_mode;
int numcopps;
int fedai_id;
unsigned long copp_map;
struct q6copp *copps[MAX_COPPS_PER_PORT];
};
struct msm_routing_data {
struct session_data sessions[MAX_SESSIONS];
struct session_data port_data[AFE_MAX_PORTS];
struct device *dev;
struct mutex lock;
};
static struct msm_routing_data *routing_data;
/**
* q6routing_stream_open() - Register a new stream for route setup
*
* @fedai_id: Frontend dai id.
* @perf_mode: Performance mode.
* @stream_id: ASM stream id to map.
* @stream_type: Direction of stream
*
* Return: Will be an negative on error or a zero on success.
*/
int q6routing_stream_open(int fedai_id, int perf_mode,
int stream_id, int stream_type)
{
int j, topology, num_copps = 0;
struct route_payload payload;
struct q6copp *copp;
int copp_idx;
struct session_data *session, *pdata;
if (!routing_data) {
pr_err("Routing driver not yet ready\n");
return -EINVAL;
}
session = &routing_data->sessions[stream_id - 1];
if (session->port_id < 0) {
dev_err(routing_data->dev, "Routing not setup for MultiMedia%d Session\n",
session->fedai_id);
return -EINVAL;
}
pdata = &routing_data->port_data[session->port_id];
mutex_lock(&routing_data->lock);
session->fedai_id = fedai_id;
session->path_type = pdata->path_type;
session->sample_rate = pdata->sample_rate;
session->channels = pdata->channels;
session->bits_per_sample = pdata->bits_per_sample;
payload.num_copps = 0; /* only RX needs to use payload */
topology = NULL_COPP_TOPOLOGY;
copp = q6adm_open(routing_data->dev, session->port_id,
session->path_type, session->sample_rate,
session->channels, topology, perf_mode,
session->bits_per_sample, 0, 0);
if (IS_ERR_OR_NULL(copp)) {
mutex_unlock(&routing_data->lock);
return -EINVAL;
}
copp_idx = q6adm_get_copp_id(copp);
set_bit(copp_idx, &session->copp_map);
session->copps[copp_idx] = copp;
for_each_set_bit(j, &session->copp_map, MAX_COPPS_PER_PORT) {
payload.port_id[num_copps] = session->port_id;
payload.copp_idx[num_copps] = j;
num_copps++;
}
if (num_copps) {
payload.num_copps = num_copps;
payload.session_id = stream_id;
q6adm_matrix_map(routing_data->dev, session->path_type,
payload, perf_mode);
}
mutex_unlock(&routing_data->lock);
return 0;
}
EXPORT_SYMBOL_GPL(q6routing_stream_open);
static struct session_data *get_session_from_id(struct msm_routing_data *data,
int fedai_id)
{
int i;
for (i = 0; i < MAX_SESSIONS; i++) {
if (fedai_id == data->sessions[i].fedai_id)
return &data->sessions[i];
}
return NULL;
}
/**
* q6routing_stream_close() - Deregister a stream
*
* @fedai_id: Frontend dai id.
* @stream_type: Direction of stream
*
* Return: Will be an negative on error or a zero on success.
*/
void q6routing_stream_close(int fedai_id, int stream_type)
{
struct session_data *session;
int idx;
session = get_session_from_id(routing_data, fedai_id);
if (!session)
return;
for_each_set_bit(idx, &session->copp_map, MAX_COPPS_PER_PORT) {
if (session->copps[idx]) {
q6adm_close(routing_data->dev, session->copps[idx]);
session->copps[idx] = NULL;
}
}
session->fedai_id = -1;
session->copp_map = 0;
}
EXPORT_SYMBOL_GPL(q6routing_stream_close);
static int msm_routing_get_audio_mixer(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dapm_context *dapm =
snd_soc_dapm_kcontrol_dapm(kcontrol);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
int session_id = mc->shift;
struct snd_soc_component *c = snd_soc_dapm_to_component(dapm);
struct msm_routing_data *priv = dev_get_drvdata(c->dev);
struct session_data *session = &priv->sessions[session_id];
if (session->port_id == mc->reg)
ucontrol->value.integer.value[0] = 1;
else
ucontrol->value.integer.value[0] = 0;
return 0;
}
static int msm_routing_put_audio_mixer(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dapm_context *dapm =
snd_soc_dapm_kcontrol_dapm(kcontrol);
struct snd_soc_component *c = snd_soc_dapm_to_component(dapm);
struct msm_routing_data *data = dev_get_drvdata(c->dev);
struct soc_mixer_control *mc =
(struct soc_mixer_control *)kcontrol->private_value;
struct snd_soc_dapm_update *update = NULL;
int be_id = mc->reg;
int session_id = mc->shift;
struct session_data *session = &data->sessions[session_id];
if (ucontrol->value.integer.value[0]) {
if (session->port_id == be_id)
return 0;
session->port_id = be_id;
snd_soc_dapm_mixer_update_power(dapm, kcontrol, 1, update);
} else {
if (session->port_id == -1 || session->port_id != be_id)
return 0;
session->port_id = -1;
snd_soc_dapm_mixer_update_power(dapm, kcontrol, 0, update);
}
return 1;
}
static const struct snd_kcontrol_new hdmi_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(HDMI_RX) };
static const struct snd_kcontrol_new display_port_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(DISPLAY_PORT_RX) };
static const struct snd_kcontrol_new primary_mi2s_rx_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(PRIMARY_MI2S_RX) };
static const struct snd_kcontrol_new secondary_mi2s_rx_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(SECONDARY_MI2S_RX) };
static const struct snd_kcontrol_new quaternary_mi2s_rx_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(QUATERNARY_MI2S_RX) };
static const struct snd_kcontrol_new quinary_mi2s_rx_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(QUINARY_MI2S_RX) };
static const struct snd_kcontrol_new tertiary_mi2s_rx_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(TERTIARY_MI2S_RX) };
static const struct snd_kcontrol_new slimbus_rx_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(SLIMBUS_0_RX) };
static const struct snd_kcontrol_new slimbus_1_rx_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(SLIMBUS_1_RX) };
static const struct snd_kcontrol_new slimbus_2_rx_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(SLIMBUS_2_RX) };
static const struct snd_kcontrol_new slimbus_3_rx_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(SLIMBUS_3_RX) };
static const struct snd_kcontrol_new slimbus_4_rx_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(SLIMBUS_4_RX) };
static const struct snd_kcontrol_new slimbus_5_rx_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(SLIMBUS_5_RX) };
static const struct snd_kcontrol_new slimbus_6_rx_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(SLIMBUS_6_RX) };
static const struct snd_kcontrol_new pri_tdm_rx_0_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(PRIMARY_TDM_RX_0) };
static const struct snd_kcontrol_new pri_tdm_rx_1_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(PRIMARY_TDM_RX_1) };
static const struct snd_kcontrol_new pri_tdm_rx_2_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(PRIMARY_TDM_RX_2) };
static const struct snd_kcontrol_new pri_tdm_rx_3_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(PRIMARY_TDM_RX_3) };
static const struct snd_kcontrol_new pri_tdm_rx_4_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(PRIMARY_TDM_RX_4) };
static const struct snd_kcontrol_new pri_tdm_rx_5_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(PRIMARY_TDM_RX_5) };
static const struct snd_kcontrol_new pri_tdm_rx_6_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(PRIMARY_TDM_RX_6) };
static const struct snd_kcontrol_new pri_tdm_rx_7_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(PRIMARY_TDM_RX_7) };
static const struct snd_kcontrol_new sec_tdm_rx_0_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(SECONDARY_TDM_RX_0) };
static const struct snd_kcontrol_new sec_tdm_rx_1_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(SECONDARY_TDM_RX_1) };
static const struct snd_kcontrol_new sec_tdm_rx_2_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(SECONDARY_TDM_RX_2) };
static const struct snd_kcontrol_new sec_tdm_rx_3_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(SECONDARY_TDM_RX_3) };
static const struct snd_kcontrol_new sec_tdm_rx_4_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(SECONDARY_TDM_RX_4) };
static const struct snd_kcontrol_new sec_tdm_rx_5_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(SECONDARY_TDM_RX_5) };
static const struct snd_kcontrol_new sec_tdm_rx_6_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(SECONDARY_TDM_RX_6) };
static const struct snd_kcontrol_new sec_tdm_rx_7_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(SECONDARY_TDM_RX_7) };
static const struct snd_kcontrol_new tert_tdm_rx_0_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(TERTIARY_TDM_RX_0) };
static const struct snd_kcontrol_new tert_tdm_rx_1_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(TERTIARY_TDM_RX_1) };
static const struct snd_kcontrol_new tert_tdm_rx_2_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(TERTIARY_TDM_RX_2) };
static const struct snd_kcontrol_new tert_tdm_rx_3_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(TERTIARY_TDM_RX_3) };
static const struct snd_kcontrol_new tert_tdm_rx_4_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(TERTIARY_TDM_RX_4) };
static const struct snd_kcontrol_new tert_tdm_rx_5_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(TERTIARY_TDM_RX_5) };
static const struct snd_kcontrol_new tert_tdm_rx_6_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(TERTIARY_TDM_RX_6) };
static const struct snd_kcontrol_new tert_tdm_rx_7_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(TERTIARY_TDM_RX_7) };
static const struct snd_kcontrol_new quat_tdm_rx_0_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(QUATERNARY_TDM_RX_0) };
static const struct snd_kcontrol_new quat_tdm_rx_1_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(QUATERNARY_TDM_RX_1) };
static const struct snd_kcontrol_new quat_tdm_rx_2_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(QUATERNARY_TDM_RX_2) };
static const struct snd_kcontrol_new quat_tdm_rx_3_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(QUATERNARY_TDM_RX_3) };
static const struct snd_kcontrol_new quat_tdm_rx_4_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(QUATERNARY_TDM_RX_4) };
static const struct snd_kcontrol_new quat_tdm_rx_5_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(QUATERNARY_TDM_RX_5) };
static const struct snd_kcontrol_new quat_tdm_rx_6_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(QUATERNARY_TDM_RX_6) };
static const struct snd_kcontrol_new quat_tdm_rx_7_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(QUATERNARY_TDM_RX_7) };
static const struct snd_kcontrol_new quin_tdm_rx_0_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(QUINARY_TDM_RX_0) };
static const struct snd_kcontrol_new quin_tdm_rx_1_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(QUINARY_TDM_RX_1) };
static const struct snd_kcontrol_new quin_tdm_rx_2_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(QUINARY_TDM_RX_2) };
static const struct snd_kcontrol_new quin_tdm_rx_3_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(QUINARY_TDM_RX_3) };
static const struct snd_kcontrol_new quin_tdm_rx_4_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(QUINARY_TDM_RX_4) };
static const struct snd_kcontrol_new quin_tdm_rx_5_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(QUINARY_TDM_RX_5) };
static const struct snd_kcontrol_new quin_tdm_rx_6_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(QUINARY_TDM_RX_6) };
static const struct snd_kcontrol_new quin_tdm_rx_7_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(QUINARY_TDM_RX_7) };
static const struct snd_kcontrol_new wsa_codec_dma_rx_0_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(WSA_CODEC_DMA_RX_0) };
static const struct snd_kcontrol_new wsa_codec_dma_rx_1_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(WSA_CODEC_DMA_RX_1) };
static const struct snd_kcontrol_new rx_codec_dma_rx_0_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(RX_CODEC_DMA_RX_0) };
static const struct snd_kcontrol_new rx_codec_dma_rx_1_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(RX_CODEC_DMA_RX_1) };
static const struct snd_kcontrol_new rx_codec_dma_rx_2_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(RX_CODEC_DMA_RX_2) };
static const struct snd_kcontrol_new rx_codec_dma_rx_3_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(RX_CODEC_DMA_RX_3) };
static const struct snd_kcontrol_new rx_codec_dma_rx_4_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(RX_CODEC_DMA_RX_4) };
static const struct snd_kcontrol_new rx_codec_dma_rx_5_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(RX_CODEC_DMA_RX_5) };
static const struct snd_kcontrol_new rxcodec_dma_rx_6_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(RX_CODEC_DMA_RX_6) };
static const struct snd_kcontrol_new rx_codec_dma_rx_7_mixer_controls[] = {
Q6ROUTING_RX_MIXERS(RX_CODEC_DMA_RX_7) };
static const struct snd_kcontrol_new mmul1_mixer_controls[] = {
Q6ROUTING_TX_MIXERS(MSM_FRONTEND_DAI_MULTIMEDIA1) };
static const struct snd_kcontrol_new mmul2_mixer_controls[] = {
Q6ROUTING_TX_MIXERS(MSM_FRONTEND_DAI_MULTIMEDIA2) };
static const struct snd_kcontrol_new mmul3_mixer_controls[] = {
Q6ROUTING_TX_MIXERS(MSM_FRONTEND_DAI_MULTIMEDIA3) };
static const struct snd_kcontrol_new mmul4_mixer_controls[] = {
Q6ROUTING_TX_MIXERS(MSM_FRONTEND_DAI_MULTIMEDIA4) };
static const struct snd_kcontrol_new mmul5_mixer_controls[] = {
Q6ROUTING_TX_MIXERS(MSM_FRONTEND_DAI_MULTIMEDIA5) };
static const struct snd_kcontrol_new mmul6_mixer_controls[] = {
Q6ROUTING_TX_MIXERS(MSM_FRONTEND_DAI_MULTIMEDIA6) };
static const struct snd_kcontrol_new mmul7_mixer_controls[] = {
Q6ROUTING_TX_MIXERS(MSM_FRONTEND_DAI_MULTIMEDIA7) };
static const struct snd_kcontrol_new mmul8_mixer_controls[] = {
Q6ROUTING_TX_MIXERS(MSM_FRONTEND_DAI_MULTIMEDIA8) };
static const struct snd_soc_dapm_widget msm_qdsp6_widgets[] = {
/* Mixer definitions */
SND_SOC_DAPM_MIXER("HDMI Mixer", SND_SOC_NOPM, 0, 0,
hdmi_mixer_controls,
ARRAY_SIZE(hdmi_mixer_controls)),
SND_SOC_DAPM_MIXER("DISPLAY_PORT_RX Audio Mixer", SND_SOC_NOPM, 0, 0,
display_port_mixer_controls,
ARRAY_SIZE(display_port_mixer_controls)),
SND_SOC_DAPM_MIXER("SLIMBUS_0_RX Audio Mixer", SND_SOC_NOPM, 0, 0,
slimbus_rx_mixer_controls,
ARRAY_SIZE(slimbus_rx_mixer_controls)),
SND_SOC_DAPM_MIXER("SLIMBUS_1_RX Audio Mixer", SND_SOC_NOPM, 0, 0,
slimbus_1_rx_mixer_controls,
ARRAY_SIZE(slimbus_1_rx_mixer_controls)),
SND_SOC_DAPM_MIXER("SLIMBUS_2_RX Audio Mixer", SND_SOC_NOPM, 0, 0,
slimbus_2_rx_mixer_controls,
ARRAY_SIZE(slimbus_2_rx_mixer_controls)),
SND_SOC_DAPM_MIXER("SLIMBUS_3_RX Audio Mixer", SND_SOC_NOPM, 0, 0,
slimbus_3_rx_mixer_controls,
ARRAY_SIZE(slimbus_3_rx_mixer_controls)),
SND_SOC_DAPM_MIXER("SLIMBUS_4_RX Audio Mixer", SND_SOC_NOPM, 0, 0,
slimbus_4_rx_mixer_controls,
ARRAY_SIZE(slimbus_4_rx_mixer_controls)),
SND_SOC_DAPM_MIXER("SLIMBUS_5_RX Audio Mixer", SND_SOC_NOPM, 0, 0,
slimbus_5_rx_mixer_controls,
ARRAY_SIZE(slimbus_5_rx_mixer_controls)),
SND_SOC_DAPM_MIXER("SLIMBUS_6_RX Audio Mixer", SND_SOC_NOPM, 0, 0,
slimbus_6_rx_mixer_controls,
ARRAY_SIZE(slimbus_6_rx_mixer_controls)),
SND_SOC_DAPM_MIXER("PRI_MI2S_RX Audio Mixer", SND_SOC_NOPM, 0, 0,
primary_mi2s_rx_mixer_controls,
ARRAY_SIZE(primary_mi2s_rx_mixer_controls)),
SND_SOC_DAPM_MIXER("SEC_MI2S_RX Audio Mixer", SND_SOC_NOPM, 0, 0,
secondary_mi2s_rx_mixer_controls,
ARRAY_SIZE(secondary_mi2s_rx_mixer_controls)),
SND_SOC_DAPM_MIXER("QUAT_MI2S_RX Audio Mixer", SND_SOC_NOPM, 0, 0,
quaternary_mi2s_rx_mixer_controls,
ARRAY_SIZE(quaternary_mi2s_rx_mixer_controls)),
SND_SOC_DAPM_MIXER("QUIN_MI2S_RX Audio Mixer", SND_SOC_NOPM, 0, 0,
quinary_mi2s_rx_mixer_controls,
ARRAY_SIZE(quinary_mi2s_rx_mixer_controls)),
SND_SOC_DAPM_MIXER("TERT_MI2S_RX Audio Mixer", SND_SOC_NOPM, 0, 0,
tertiary_mi2s_rx_mixer_controls,
ARRAY_SIZE(tertiary_mi2s_rx_mixer_controls)),
SND_SOC_DAPM_MIXER("PRIMARY_TDM_RX_0 Audio Mixer", SND_SOC_NOPM, 0, 0,
pri_tdm_rx_0_mixer_controls,
ARRAY_SIZE(pri_tdm_rx_0_mixer_controls)),
SND_SOC_DAPM_MIXER("PRIMARY_TDM_RX_1 Audio Mixer", SND_SOC_NOPM, 0, 0,
pri_tdm_rx_1_mixer_controls,
ARRAY_SIZE(pri_tdm_rx_1_mixer_controls)),
SND_SOC_DAPM_MIXER("PRIMARY_TDM_RX_2 Audio Mixer", SND_SOC_NOPM, 0, 0,
pri_tdm_rx_2_mixer_controls,
ARRAY_SIZE(pri_tdm_rx_2_mixer_controls)),
SND_SOC_DAPM_MIXER("PRIMARY_TDM_RX_3 Audio Mixer", SND_SOC_NOPM, 0, 0,
pri_tdm_rx_3_mixer_controls,
ARRAY_SIZE(pri_tdm_rx_3_mixer_controls)),
SND_SOC_DAPM_MIXER("PRIMARY_TDM_RX_4 Audio Mixer", SND_SOC_NOPM, 0, 0,
pri_tdm_rx_4_mixer_controls,
ARRAY_SIZE(pri_tdm_rx_4_mixer_controls)),
SND_SOC_DAPM_MIXER("PRIMARY_TDM_RX_5 Audio Mixer", SND_SOC_NOPM, 0, 0,
pri_tdm_rx_5_mixer_controls,
ARRAY_SIZE(pri_tdm_rx_5_mixer_controls)),
SND_SOC_DAPM_MIXER("PRIMARY_TDM_RX_6 Audio Mixer", SND_SOC_NOPM, 0, 0,
pri_tdm_rx_6_mixer_controls,
ARRAY_SIZE(pri_tdm_rx_6_mixer_controls)),
SND_SOC_DAPM_MIXER("PRIMARY_TDM_RX_7 Audio Mixer", SND_SOC_NOPM, 0, 0,
pri_tdm_rx_7_mixer_controls,
ARRAY_SIZE(pri_tdm_rx_7_mixer_controls)),
SND_SOC_DAPM_MIXER("SEC_TDM_RX_0 Audio Mixer", SND_SOC_NOPM, 0, 0,
sec_tdm_rx_0_mixer_controls,
ARRAY_SIZE(sec_tdm_rx_0_mixer_controls)),
SND_SOC_DAPM_MIXER("SEC_TDM_RX_1 Audio Mixer", SND_SOC_NOPM, 0, 0,
sec_tdm_rx_1_mixer_controls,
ARRAY_SIZE(sec_tdm_rx_1_mixer_controls)),
SND_SOC_DAPM_MIXER("SEC_TDM_RX_2 Audio Mixer", SND_SOC_NOPM, 0, 0,
sec_tdm_rx_2_mixer_controls,
ARRAY_SIZE(sec_tdm_rx_2_mixer_controls)),
SND_SOC_DAPM_MIXER("SEC_TDM_RX_3 Audio Mixer", SND_SOC_NOPM, 0, 0,
sec_tdm_rx_3_mixer_controls,
ARRAY_SIZE(sec_tdm_rx_3_mixer_controls)),
SND_SOC_DAPM_MIXER("SEC_TDM_RX_4 Audio Mixer", SND_SOC_NOPM, 0, 0,
sec_tdm_rx_4_mixer_controls,
ARRAY_SIZE(sec_tdm_rx_4_mixer_controls)),
SND_SOC_DAPM_MIXER("SEC_TDM_RX_5 Audio Mixer", SND_SOC_NOPM, 0, 0,
sec_tdm_rx_5_mixer_controls,
ARRAY_SIZE(sec_tdm_rx_5_mixer_controls)),
SND_SOC_DAPM_MIXER("SEC_TDM_RX_6 Audio Mixer", SND_SOC_NOPM, 0, 0,
sec_tdm_rx_6_mixer_controls,
ARRAY_SIZE(sec_tdm_rx_6_mixer_controls)),
SND_SOC_DAPM_MIXER("SEC_TDM_RX_7 Audio Mixer", SND_SOC_NOPM, 0, 0,
sec_tdm_rx_7_mixer_controls,
ARRAY_SIZE(sec_tdm_rx_7_mixer_controls)),
SND_SOC_DAPM_MIXER("TERT_TDM_RX_0 Audio Mixer", SND_SOC_NOPM, 0, 0,
tert_tdm_rx_0_mixer_controls,
ARRAY_SIZE(tert_tdm_rx_0_mixer_controls)),
SND_SOC_DAPM_MIXER("TERT_TDM_RX_1 Audio Mixer", SND_SOC_NOPM, 0, 0,
tert_tdm_rx_1_mixer_controls,
ARRAY_SIZE(tert_tdm_rx_1_mixer_controls)),
SND_SOC_DAPM_MIXER("TERT_TDM_RX_2 Audio Mixer", SND_SOC_NOPM, 0, 0,
tert_tdm_rx_2_mixer_controls,
ARRAY_SIZE(tert_tdm_rx_2_mixer_controls)),
SND_SOC_DAPM_MIXER("TERT_TDM_RX_3 Audio Mixer", SND_SOC_NOPM, 0, 0,
tert_tdm_rx_3_mixer_controls,
ARRAY_SIZE(tert_tdm_rx_3_mixer_controls)),
SND_SOC_DAPM_MIXER("TERT_TDM_RX_4 Audio Mixer", SND_SOC_NOPM, 0, 0,
tert_tdm_rx_4_mixer_controls,
ARRAY_SIZE(tert_tdm_rx_4_mixer_controls)),
SND_SOC_DAPM_MIXER("TERT_TDM_RX_5 Audio Mixer", SND_SOC_NOPM, 0, 0,
tert_tdm_rx_5_mixer_controls,
ARRAY_SIZE(tert_tdm_rx_5_mixer_controls)),
SND_SOC_DAPM_MIXER("TERT_TDM_RX_6 Audio Mixer", SND_SOC_NOPM, 0, 0,
tert_tdm_rx_6_mixer_controls,
ARRAY_SIZE(tert_tdm_rx_6_mixer_controls)),
SND_SOC_DAPM_MIXER("TERT_TDM_RX_7 Audio Mixer", SND_SOC_NOPM, 0, 0,
tert_tdm_rx_7_mixer_controls,
ARRAY_SIZE(tert_tdm_rx_7_mixer_controls)),
SND_SOC_DAPM_MIXER("QUAT_TDM_RX_0 Audio Mixer", SND_SOC_NOPM, 0, 0,
quat_tdm_rx_0_mixer_controls,
ARRAY_SIZE(quat_tdm_rx_0_mixer_controls)),
SND_SOC_DAPM_MIXER("QUAT_TDM_RX_1 Audio Mixer", SND_SOC_NOPM, 0, 0,
quat_tdm_rx_1_mixer_controls,
ARRAY_SIZE(quat_tdm_rx_1_mixer_controls)),
SND_SOC_DAPM_MIXER("QUAT_TDM_RX_2 Audio Mixer", SND_SOC_NOPM, 0, 0,
quat_tdm_rx_2_mixer_controls,
ARRAY_SIZE(quat_tdm_rx_2_mixer_controls)),
SND_SOC_DAPM_MIXER("QUAT_TDM_RX_3 Audio Mixer", SND_SOC_NOPM, 0, 0,
quat_tdm_rx_3_mixer_controls,
ARRAY_SIZE(quat_tdm_rx_3_mixer_controls)),
SND_SOC_DAPM_MIXER("QUAT_TDM_RX_4 Audio Mixer", SND_SOC_NOPM, 0, 0,
quat_tdm_rx_4_mixer_controls,
ARRAY_SIZE(quat_tdm_rx_4_mixer_controls)),
SND_SOC_DAPM_MIXER("QUAT_TDM_RX_5 Audio Mixer", SND_SOC_NOPM, 0, 0,
quat_tdm_rx_5_mixer_controls,
ARRAY_SIZE(quat_tdm_rx_5_mixer_controls)),
SND_SOC_DAPM_MIXER("QUAT_TDM_RX_6 Audio Mixer", SND_SOC_NOPM, 0, 0,
quat_tdm_rx_6_mixer_controls,
ARRAY_SIZE(quat_tdm_rx_6_mixer_controls)),
SND_SOC_DAPM_MIXER("QUAT_TDM_RX_7 Audio Mixer", SND_SOC_NOPM, 0, 0,
quat_tdm_rx_7_mixer_controls,
ARRAY_SIZE(quat_tdm_rx_7_mixer_controls)),
SND_SOC_DAPM_MIXER("QUIN_TDM_RX_0 Audio Mixer", SND_SOC_NOPM, 0, 0,
quin_tdm_rx_0_mixer_controls,
ARRAY_SIZE(quin_tdm_rx_0_mixer_controls)),
SND_SOC_DAPM_MIXER("QUIN_TDM_RX_1 Audio Mixer", SND_SOC_NOPM, 0, 0,
quin_tdm_rx_1_mixer_controls,
ARRAY_SIZE(quin_tdm_rx_1_mixer_controls)),
SND_SOC_DAPM_MIXER("QUIN_TDM_RX_2 Audio Mixer", SND_SOC_NOPM, 0, 0,
quin_tdm_rx_2_mixer_controls,
ARRAY_SIZE(quin_tdm_rx_2_mixer_controls)),
SND_SOC_DAPM_MIXER("QUIN_TDM_RX_3 Audio Mixer", SND_SOC_NOPM, 0, 0,
quin_tdm_rx_3_mixer_controls,
ARRAY_SIZE(quin_tdm_rx_3_mixer_controls)),
SND_SOC_DAPM_MIXER("QUIN_TDM_RX_4 Audio Mixer", SND_SOC_NOPM, 0, 0,
quin_tdm_rx_4_mixer_controls,
ARRAY_SIZE(quin_tdm_rx_4_mixer_controls)),
SND_SOC_DAPM_MIXER("QUIN_TDM_RX_5 Audio Mixer", SND_SOC_NOPM, 0, 0,
quin_tdm_rx_5_mixer_controls,
ARRAY_SIZE(quin_tdm_rx_5_mixer_controls)),
SND_SOC_DAPM_MIXER("QUIN_TDM_RX_6 Audio Mixer", SND_SOC_NOPM, 0, 0,
quin_tdm_rx_6_mixer_controls,
ARRAY_SIZE(quin_tdm_rx_6_mixer_controls)),
SND_SOC_DAPM_MIXER("QUIN_TDM_RX_7 Audio Mixer", SND_SOC_NOPM, 0, 0,
quin_tdm_rx_7_mixer_controls,
ARRAY_SIZE(quin_tdm_rx_7_mixer_controls)),
SND_SOC_DAPM_MIXER("WSA_CODEC_DMA_RX_0 Audio Mixer", SND_SOC_NOPM, 0, 0,
wsa_codec_dma_rx_0_mixer_controls,
ARRAY_SIZE(wsa_codec_dma_rx_0_mixer_controls)),
SND_SOC_DAPM_MIXER("WSA_CODEC_DMA_RX_1 Audio Mixer", SND_SOC_NOPM, 0, 0,
wsa_codec_dma_rx_1_mixer_controls,
ARRAY_SIZE(wsa_codec_dma_rx_1_mixer_controls)),
SND_SOC_DAPM_MIXER("RX_CODEC_DMA_RX_0 Audio Mixer", SND_SOC_NOPM, 0, 0,
rx_codec_dma_rx_0_mixer_controls,
ARRAY_SIZE(rx_codec_dma_rx_0_mixer_controls)),
SND_SOC_DAPM_MIXER("RX_CODEC_DMA_RX_1 Audio Mixer", SND_SOC_NOPM, 0, 0,
rx_codec_dma_rx_1_mixer_controls,
ARRAY_SIZE(rx_codec_dma_rx_1_mixer_controls)),
SND_SOC_DAPM_MIXER("RX_CODEC_DMA_RX_2 Audio Mixer", SND_SOC_NOPM, 0, 0,
rx_codec_dma_rx_2_mixer_controls,
ARRAY_SIZE(rx_codec_dma_rx_2_mixer_controls)),
SND_SOC_DAPM_MIXER("RX_CODEC_DMA_RX_3 Audio Mixer", SND_SOC_NOPM, 0, 0,
rx_codec_dma_rx_3_mixer_controls,
ARRAY_SIZE(rx_codec_dma_rx_3_mixer_controls)),
SND_SOC_DAPM_MIXER("RX_CODEC_DMA_RX_4 Audio Mixer", SND_SOC_NOPM, 0, 0,
rx_codec_dma_rx_4_mixer_controls,
ARRAY_SIZE(rx_codec_dma_rx_4_mixer_controls)),
SND_SOC_DAPM_MIXER("RX_CODEC_DMA_RX_5 Audio Mixer", SND_SOC_NOPM, 0, 0,
rx_codec_dma_rx_5_mixer_controls,
ARRAY_SIZE(rx_codec_dma_rx_5_mixer_controls)),
SND_SOC_DAPM_MIXER("RX_CODEC_DMA_RX_6 Audio Mixer", SND_SOC_NOPM, 0, 0,
rxcodec_dma_rx_6_mixer_controls,
ARRAY_SIZE(rxcodec_dma_rx_6_mixer_controls)),
SND_SOC_DAPM_MIXER("RX_CODEC_DMA_RX_7 Audio Mixer", SND_SOC_NOPM, 0, 0,
rx_codec_dma_rx_7_mixer_controls,
ARRAY_SIZE(rx_codec_dma_rx_7_mixer_controls)),
SND_SOC_DAPM_MIXER("MultiMedia1 Mixer", SND_SOC_NOPM, 0, 0,
mmul1_mixer_controls, ARRAY_SIZE(mmul1_mixer_controls)),
SND_SOC_DAPM_MIXER("MultiMedia2 Mixer", SND_SOC_NOPM, 0, 0,
mmul2_mixer_controls, ARRAY_SIZE(mmul2_mixer_controls)),
SND_SOC_DAPM_MIXER("MultiMedia3 Mixer", SND_SOC_NOPM, 0, 0,
mmul3_mixer_controls, ARRAY_SIZE(mmul3_mixer_controls)),
SND_SOC_DAPM_MIXER("MultiMedia4 Mixer", SND_SOC_NOPM, 0, 0,
mmul4_mixer_controls, ARRAY_SIZE(mmul4_mixer_controls)),
SND_SOC_DAPM_MIXER("MultiMedia5 Mixer", SND_SOC_NOPM, 0, 0,
mmul5_mixer_controls, ARRAY_SIZE(mmul5_mixer_controls)),
SND_SOC_DAPM_MIXER("MultiMedia6 Mixer", SND_SOC_NOPM, 0, 0,
mmul6_mixer_controls, ARRAY_SIZE(mmul6_mixer_controls)),
SND_SOC_DAPM_MIXER("MultiMedia7 Mixer", SND_SOC_NOPM, 0, 0,
mmul7_mixer_controls, ARRAY_SIZE(mmul7_mixer_controls)),
SND_SOC_DAPM_MIXER("MultiMedia8 Mixer", SND_SOC_NOPM, 0, 0,
mmul8_mixer_controls, ARRAY_SIZE(mmul8_mixer_controls)),
};
static const struct snd_soc_dapm_route intercon[] = {
Q6ROUTING_RX_DAPM_ROUTE("HDMI Mixer", "HDMI_RX"),
Q6ROUTING_RX_DAPM_ROUTE("DISPLAY_PORT_RX Audio Mixer",
"DISPLAY_PORT_RX"),
Q6ROUTING_RX_DAPM_ROUTE("SLIMBUS_0_RX Audio Mixer", "SLIMBUS_0_RX"),
Q6ROUTING_RX_DAPM_ROUTE("SLIMBUS_1_RX Audio Mixer", "SLIMBUS_1_RX"),
Q6ROUTING_RX_DAPM_ROUTE("SLIMBUS_2_RX Audio Mixer", "SLIMBUS_2_RX"),
Q6ROUTING_RX_DAPM_ROUTE("SLIMBUS_3_RX Audio Mixer", "SLIMBUS_3_RX"),
Q6ROUTING_RX_DAPM_ROUTE("SLIMBUS_4_RX Audio Mixer", "SLIMBUS_4_RX"),
Q6ROUTING_RX_DAPM_ROUTE("SLIMBUS_5_RX Audio Mixer", "SLIMBUS_5_RX"),
Q6ROUTING_RX_DAPM_ROUTE("SLIMBUS_6_RX Audio Mixer", "SLIMBUS_6_RX"),
Q6ROUTING_RX_DAPM_ROUTE("QUAT_MI2S_RX Audio Mixer", "QUAT_MI2S_RX"),
Q6ROUTING_RX_DAPM_ROUTE("QUIN_MI2S_RX Audio Mixer", "QUIN_MI2S_RX"),
Q6ROUTING_RX_DAPM_ROUTE("TERT_MI2S_RX Audio Mixer", "TERT_MI2S_RX"),
Q6ROUTING_RX_DAPM_ROUTE("SEC_MI2S_RX Audio Mixer", "SEC_MI2S_RX"),
Q6ROUTING_RX_DAPM_ROUTE("PRI_MI2S_RX Audio Mixer", "PRI_MI2S_RX"),
Q6ROUTING_RX_DAPM_ROUTE("PRIMARY_TDM_RX_0 Audio Mixer",
"PRIMARY_TDM_RX_0"),
Q6ROUTING_RX_DAPM_ROUTE("PRIMARY_TDM_RX_1 Audio Mixer",
"PRIMARY_TDM_RX_1"),
Q6ROUTING_RX_DAPM_ROUTE("PRIMARY_TDM_RX_2 Audio Mixer",
"PRIMARY_TDM_RX_2"),
Q6ROUTING_RX_DAPM_ROUTE("PRIMARY_TDM_RX_3 Audio Mixer",
"PRIMARY_TDM_RX_3"),
Q6ROUTING_RX_DAPM_ROUTE("PRIMARY_TDM_RX_4 Audio Mixer",
"PRIMARY_TDM_RX_4"),
Q6ROUTING_RX_DAPM_ROUTE("PRIMARY_TDM_RX_5 Audio Mixer",
"PRIMARY_TDM_RX_5"),
Q6ROUTING_RX_DAPM_ROUTE("PRIMARY_TDM_RX_6 Audio Mixer",
"PRIMARY_TDM_RX_6"),
Q6ROUTING_RX_DAPM_ROUTE("PRIMARY_TDM_RX_7 Audio Mixer",
"PRIMARY_TDM_RX_7"),
Q6ROUTING_RX_DAPM_ROUTE("SEC_TDM_RX_0 Audio Mixer", "SEC_TDM_RX_0"),
Q6ROUTING_RX_DAPM_ROUTE("SEC_TDM_RX_1 Audio Mixer", "SEC_TDM_RX_1"),
Q6ROUTING_RX_DAPM_ROUTE("SEC_TDM_RX_2 Audio Mixer", "SEC_TDM_RX_2"),
Q6ROUTING_RX_DAPM_ROUTE("SEC_TDM_RX_3 Audio Mixer", "SEC_TDM_RX_3"),
Q6ROUTING_RX_DAPM_ROUTE("SEC_TDM_RX_4 Audio Mixer", "SEC_TDM_RX_4"),
Q6ROUTING_RX_DAPM_ROUTE("SEC_TDM_RX_5 Audio Mixer", "SEC_TDM_RX_5"),
Q6ROUTING_RX_DAPM_ROUTE("SEC_TDM_RX_6 Audio Mixer", "SEC_TDM_RX_6"),
Q6ROUTING_RX_DAPM_ROUTE("SEC_TDM_RX_7 Audio Mixer", "SEC_TDM_RX_7"),
Q6ROUTING_RX_DAPM_ROUTE("TERT_TDM_RX_0 Audio Mixer", "TERT_TDM_RX_0"),
Q6ROUTING_RX_DAPM_ROUTE("TERT_TDM_RX_1 Audio Mixer", "TERT_TDM_RX_1"),
Q6ROUTING_RX_DAPM_ROUTE("TERT_TDM_RX_2 Audio Mixer", "TERT_TDM_RX_2"),
Q6ROUTING_RX_DAPM_ROUTE("TERT_TDM_RX_3 Audio Mixer", "TERT_TDM_RX_3"),
Q6ROUTING_RX_DAPM_ROUTE("TERT_TDM_RX_4 Audio Mixer", "TERT_TDM_RX_4"),
Q6ROUTING_RX_DAPM_ROUTE("TERT_TDM_RX_5 Audio Mixer", "TERT_TDM_RX_5"),
Q6ROUTING_RX_DAPM_ROUTE("TERT_TDM_RX_6 Audio Mixer", "TERT_TDM_RX_6"),
Q6ROUTING_RX_DAPM_ROUTE("TERT_TDM_RX_7 Audio Mixer", "TERT_TDM_RX_7"),
Q6ROUTING_RX_DAPM_ROUTE("QUAT_TDM_RX_0 Audio Mixer", "QUAT_TDM_RX_0"),
Q6ROUTING_RX_DAPM_ROUTE("QUAT_TDM_RX_1 Audio Mixer", "QUAT_TDM_RX_1"),
Q6ROUTING_RX_DAPM_ROUTE("QUAT_TDM_RX_2 Audio Mixer", "QUAT_TDM_RX_2"),
Q6ROUTING_RX_DAPM_ROUTE("QUAT_TDM_RX_3 Audio Mixer", "QUAT_TDM_RX_3"),
Q6ROUTING_RX_DAPM_ROUTE("QUAT_TDM_RX_4 Audio Mixer", "QUAT_TDM_RX_4"),
Q6ROUTING_RX_DAPM_ROUTE("QUAT_TDM_RX_5 Audio Mixer", "QUAT_TDM_RX_5"),
Q6ROUTING_RX_DAPM_ROUTE("QUAT_TDM_RX_6 Audio Mixer", "QUAT_TDM_RX_6"),
Q6ROUTING_RX_DAPM_ROUTE("QUAT_TDM_RX_7 Audio Mixer", "QUAT_TDM_RX_7"),
Q6ROUTING_RX_DAPM_ROUTE("QUIN_TDM_RX_0 Audio Mixer", "QUIN_TDM_RX_0"),
Q6ROUTING_RX_DAPM_ROUTE("QUIN_TDM_RX_1 Audio Mixer", "QUIN_TDM_RX_1"),
Q6ROUTING_RX_DAPM_ROUTE("QUIN_TDM_RX_2 Audio Mixer", "QUIN_TDM_RX_2"),
Q6ROUTING_RX_DAPM_ROUTE("QUIN_TDM_RX_3 Audio Mixer", "QUIN_TDM_RX_3"),
Q6ROUTING_RX_DAPM_ROUTE("QUIN_TDM_RX_4 Audio Mixer", "QUIN_TDM_RX_4"),
Q6ROUTING_RX_DAPM_ROUTE("QUIN_TDM_RX_5 Audio Mixer", "QUIN_TDM_RX_5"),
Q6ROUTING_RX_DAPM_ROUTE("QUIN_TDM_RX_6 Audio Mixer", "QUIN_TDM_RX_6"),
Q6ROUTING_RX_DAPM_ROUTE("QUIN_TDM_RX_7 Audio Mixer", "QUIN_TDM_RX_7"),
Q6ROUTING_RX_DAPM_ROUTE("WSA_CODEC_DMA_RX_0 Audio Mixer", "WSA_CODEC_DMA_RX_0"),
Q6ROUTING_RX_DAPM_ROUTE("WSA_CODEC_DMA_RX_1 Audio Mixer", "WSA_CODEC_DMA_RX_1"),
Q6ROUTING_RX_DAPM_ROUTE("RX_CODEC_DMA_RX_0 Audio Mixer", "RX_CODEC_DMA_RX_0"),
Q6ROUTING_RX_DAPM_ROUTE("RX_CODEC_DMA_RX_1 Audio Mixer", "RX_CODEC_DMA_RX_1"),
Q6ROUTING_RX_DAPM_ROUTE("RX_CODEC_DMA_RX_2 Audio Mixer", "RX_CODEC_DMA_RX_2"),
Q6ROUTING_RX_DAPM_ROUTE("RX_CODEC_DMA_RX_3 Audio Mixer", "RX_CODEC_DMA_RX_3"),
Q6ROUTING_RX_DAPM_ROUTE("RX_CODEC_DMA_RX_4 Audio Mixer", "RX_CODEC_DMA_RX_4"),
Q6ROUTING_RX_DAPM_ROUTE("RX_CODEC_DMA_RX_5 Audio Mixer", "RX_CODEC_DMA_RX_5"),
Q6ROUTING_RX_DAPM_ROUTE("RX_CODEC_DMA_RX_6 Audio Mixer", "RX_CODEC_DMA_RX_6"),
Q6ROUTING_RX_DAPM_ROUTE("RX_CODEC_DMA_RX_7 Audio Mixer", "RX_CODEC_DMA_RX_7"),
Q6ROUTING_TX_DAPM_ROUTE("MultiMedia1 Mixer"),
Q6ROUTING_TX_DAPM_ROUTE("MultiMedia2 Mixer"),
Q6ROUTING_TX_DAPM_ROUTE("MultiMedia3 Mixer"),
Q6ROUTING_TX_DAPM_ROUTE("MultiMedia4 Mixer"),
Q6ROUTING_TX_DAPM_ROUTE("MultiMedia5 Mixer"),
Q6ROUTING_TX_DAPM_ROUTE("MultiMedia6 Mixer"),
Q6ROUTING_TX_DAPM_ROUTE("MultiMedia7 Mixer"),
Q6ROUTING_TX_DAPM_ROUTE("MultiMedia8 Mixer"),
{"MM_UL1", NULL, "MultiMedia1 Mixer"},
{"MM_UL2", NULL, "MultiMedia2 Mixer"},
{"MM_UL3", NULL, "MultiMedia3 Mixer"},
{"MM_UL4", NULL, "MultiMedia4 Mixer"},
{"MM_UL5", NULL, "MultiMedia5 Mixer"},
{"MM_UL6", NULL, "MultiMedia6 Mixer"},
{"MM_UL7", NULL, "MultiMedia7 Mixer"},
{"MM_UL8", NULL, "MultiMedia8 Mixer"},
};
static int routing_hw_params(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct msm_routing_data *data = dev_get_drvdata(component->dev);
unsigned int be_id = asoc_rtd_to_cpu(rtd, 0)->id;
struct session_data *session;
int path_type;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
path_type = ADM_PATH_PLAYBACK;
else
path_type = ADM_PATH_LIVE_REC;
if (be_id >= AFE_MAX_PORTS)
return -EINVAL;
session = &data->port_data[be_id];
mutex_lock(&data->lock);
session->path_type = path_type;
session->sample_rate = params_rate(params);
session->channels = params_channels(params);
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
session->bits_per_sample = 16;
break;
case SNDRV_PCM_FORMAT_S24_LE:
session->bits_per_sample = 24;
break;
default:
break;
}
mutex_unlock(&data->lock);
return 0;
}
static int msm_routing_probe(struct snd_soc_component *c)
{
int i;
for (i = 0; i < MAX_SESSIONS; i++) {
routing_data->sessions[i].port_id = -1;
routing_data->sessions[i].fedai_id = -1;
}
return 0;
}
static unsigned int q6routing_reg_read(struct snd_soc_component *component,
unsigned int reg)
{
/* default value */
return 0;
}
static int q6routing_reg_write(struct snd_soc_component *component,
unsigned int reg, unsigned int val)
{
/* dummy */
return 0;
}
static const struct snd_soc_component_driver msm_soc_routing_component = {
.probe = msm_routing_probe,
.name = DRV_NAME,
.hw_params = routing_hw_params,
.dapm_widgets = msm_qdsp6_widgets,
.num_dapm_widgets = ARRAY_SIZE(msm_qdsp6_widgets),
.dapm_routes = intercon,
.num_dapm_routes = ARRAY_SIZE(intercon),
.read = q6routing_reg_read,
.write = q6routing_reg_write,
};
static int q6pcm_routing_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
routing_data = kzalloc(sizeof(*routing_data), GFP_KERNEL);
if (!routing_data)
return -ENOMEM;
routing_data->dev = dev;
mutex_init(&routing_data->lock);
dev_set_drvdata(dev, routing_data);
return devm_snd_soc_register_component(dev, &msm_soc_routing_component,
NULL, 0);
}
static void q6pcm_routing_remove(struct platform_device *pdev)
{
kfree(routing_data);
routing_data = NULL;
}
#ifdef CONFIG_OF
static const struct of_device_id q6pcm_routing_device_id[] = {
{ .compatible = "qcom,q6adm-routing" },
{},
};
MODULE_DEVICE_TABLE(of, q6pcm_routing_device_id);
#endif
static struct platform_driver q6pcm_routing_platform_driver = {
.driver = {
.name = "q6routing",
.of_match_table = of_match_ptr(q6pcm_routing_device_id),
},
.probe = q6pcm_routing_probe,
.remove_new = q6pcm_routing_remove,
};
module_platform_driver(q6pcm_routing_platform_driver);
MODULE_DESCRIPTION("Q6 Routing platform");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/qcom/qdsp6/q6routing.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2021, Linaro Limited
#include <linux/err.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <sound/pcm.h>
#include <sound/soc.h>
#include <sound/pcm_params.h>
#include "q6dsp-lpass-ports.h"
#include "q6dsp-common.h"
#include "audioreach.h"
#include "q6apm.h"
#define AUDIOREACH_BE_PCM_BASE 16
struct q6apm_lpass_dai_data {
struct q6apm_graph *graph[APM_PORT_MAX];
bool is_port_started[APM_PORT_MAX];
struct audioreach_module_config module_config[APM_PORT_MAX];
};
static int q6dma_set_channel_map(struct snd_soc_dai *dai,
unsigned int tx_num, unsigned int *tx_ch_mask,
unsigned int rx_num, unsigned int *rx_ch_mask)
{
struct q6apm_lpass_dai_data *dai_data = dev_get_drvdata(dai->dev);
struct audioreach_module_config *cfg = &dai_data->module_config[dai->id];
int ch_mask;
switch (dai->id) {
case WSA_CODEC_DMA_TX_0:
case WSA_CODEC_DMA_TX_1:
case WSA_CODEC_DMA_TX_2:
case VA_CODEC_DMA_TX_0:
case VA_CODEC_DMA_TX_1:
case VA_CODEC_DMA_TX_2:
case TX_CODEC_DMA_TX_0:
case TX_CODEC_DMA_TX_1:
case TX_CODEC_DMA_TX_2:
case TX_CODEC_DMA_TX_3:
case TX_CODEC_DMA_TX_4:
case TX_CODEC_DMA_TX_5:
if (!tx_ch_mask) {
dev_err(dai->dev, "tx slot not found\n");
return -EINVAL;
}
if (tx_num > AR_PCM_MAX_NUM_CHANNEL) {
dev_err(dai->dev, "invalid tx num %d\n",
tx_num);
return -EINVAL;
}
ch_mask = *tx_ch_mask;
break;
case WSA_CODEC_DMA_RX_0:
case WSA_CODEC_DMA_RX_1:
case RX_CODEC_DMA_RX_0:
case RX_CODEC_DMA_RX_1:
case RX_CODEC_DMA_RX_2:
case RX_CODEC_DMA_RX_3:
case RX_CODEC_DMA_RX_4:
case RX_CODEC_DMA_RX_5:
case RX_CODEC_DMA_RX_6:
case RX_CODEC_DMA_RX_7:
/* rx */
if (!rx_ch_mask) {
dev_err(dai->dev, "rx slot not found\n");
return -EINVAL;
}
if (rx_num > APM_PORT_MAX_AUDIO_CHAN_CNT) {
dev_err(dai->dev, "invalid rx num %d\n",
rx_num);
return -EINVAL;
}
ch_mask = *rx_ch_mask;
break;
default:
dev_err(dai->dev, "%s: invalid dai id 0x%x\n",
__func__, dai->id);
return -EINVAL;
}
cfg->active_channels_mask = ch_mask;
return 0;
}
static int q6hdmi_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct q6apm_lpass_dai_data *dai_data = dev_get_drvdata(dai->dev);
struct audioreach_module_config *cfg = &dai_data->module_config[dai->id];
int channels = params_channels(params);
int ret;
cfg->bit_width = params_width(params);
cfg->sample_rate = params_rate(params);
cfg->num_channels = channels;
switch (dai->id) {
case DISPLAY_PORT_RX_0:
cfg->dp_idx = 0;
break;
case DISPLAY_PORT_RX_1 ... DISPLAY_PORT_RX_7:
cfg->dp_idx = dai->id - DISPLAY_PORT_RX_1 + 1;
break;
}
ret = q6dsp_get_channel_allocation(channels);
if (ret < 0)
return ret;
cfg->channel_allocation = ret;
return 0;
}
static int q6dma_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct q6apm_lpass_dai_data *dai_data = dev_get_drvdata(dai->dev);
struct audioreach_module_config *cfg = &dai_data->module_config[dai->id];
cfg->bit_width = params_width(params);
cfg->sample_rate = params_rate(params);
cfg->num_channels = params_channels(params);
return 0;
}
static void q6apm_lpass_dai_shutdown(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
{
struct q6apm_lpass_dai_data *dai_data = dev_get_drvdata(dai->dev);
int rc;
if (!dai_data->is_port_started[dai->id])
return;
rc = q6apm_graph_stop(dai_data->graph[dai->id]);
if (rc < 0)
dev_err(dai->dev, "fail to close APM port (%d)\n", rc);
q6apm_graph_close(dai_data->graph[dai->id]);
dai_data->is_port_started[dai->id] = false;
}
static int q6apm_lpass_dai_prepare(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
{
struct q6apm_lpass_dai_data *dai_data = dev_get_drvdata(dai->dev);
struct audioreach_module_config *cfg = &dai_data->module_config[dai->id];
struct q6apm_graph *graph;
int graph_id = dai->id;
int rc;
if (dai_data->is_port_started[dai->id]) {
q6apm_graph_stop(dai_data->graph[dai->id]);
dai_data->is_port_started[dai->id] = false;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
q6apm_graph_close(dai_data->graph[dai->id]);
}
/**
* It is recommend to load DSP with source graph first and then sink
* graph, so sequence for playback and capture will be different
*/
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
graph = q6apm_graph_open(dai->dev, NULL, dai->dev, graph_id);
if (IS_ERR(graph)) {
dev_err(dai->dev, "Failed to open graph (%d)\n", graph_id);
rc = PTR_ERR(graph);
return rc;
}
dai_data->graph[graph_id] = graph;
}
cfg->direction = substream->stream;
rc = q6apm_graph_media_format_pcm(dai_data->graph[dai->id], cfg);
if (rc) {
dev_err(dai->dev, "Failed to set media format %d\n", rc);
return rc;
}
rc = q6apm_graph_prepare(dai_data->graph[dai->id]);
if (rc) {
dev_err(dai->dev, "Failed to prepare Graph %d\n", rc);
return rc;
}
rc = q6apm_graph_start(dai_data->graph[dai->id]);
if (rc < 0) {
dev_err(dai->dev, "fail to start APM port %x\n", dai->id);
return rc;
}
dai_data->is_port_started[dai->id] = true;
return 0;
}
static int q6apm_lpass_dai_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
{
struct q6apm_lpass_dai_data *dai_data = dev_get_drvdata(dai->dev);
struct q6apm_graph *graph;
int graph_id = dai->id;
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
graph = q6apm_graph_open(dai->dev, NULL, dai->dev, graph_id);
if (IS_ERR(graph)) {
dev_err(dai->dev, "Failed to open graph (%d)\n", graph_id);
return PTR_ERR(graph);
}
dai_data->graph[graph_id] = graph;
}
return 0;
}
static int q6i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct q6apm_lpass_dai_data *dai_data = dev_get_drvdata(dai->dev);
struct audioreach_module_config *cfg = &dai_data->module_config[dai->id];
cfg->fmt = fmt;
return 0;
}
static const struct snd_soc_dai_ops q6dma_ops = {
.prepare = q6apm_lpass_dai_prepare,
.startup = q6apm_lpass_dai_startup,
.shutdown = q6apm_lpass_dai_shutdown,
.set_channel_map = q6dma_set_channel_map,
.hw_params = q6dma_hw_params,
};
static const struct snd_soc_dai_ops q6i2s_ops = {
.prepare = q6apm_lpass_dai_prepare,
.startup = q6apm_lpass_dai_startup,
.shutdown = q6apm_lpass_dai_shutdown,
.set_channel_map = q6dma_set_channel_map,
.hw_params = q6dma_hw_params,
};
static const struct snd_soc_dai_ops q6hdmi_ops = {
.prepare = q6apm_lpass_dai_prepare,
.startup = q6apm_lpass_dai_startup,
.shutdown = q6apm_lpass_dai_shutdown,
.hw_params = q6hdmi_hw_params,
.set_fmt = q6i2s_set_fmt,
};
static const struct snd_soc_component_driver q6apm_lpass_dai_component = {
.name = "q6apm-be-dai-component",
.of_xlate_dai_name = q6dsp_audio_ports_of_xlate_dai_name,
.be_pcm_base = AUDIOREACH_BE_PCM_BASE,
.use_dai_pcm_id = true,
};
static int q6apm_lpass_dai_dev_probe(struct platform_device *pdev)
{
struct q6dsp_audio_port_dai_driver_config cfg;
struct q6apm_lpass_dai_data *dai_data;
struct snd_soc_dai_driver *dais;
struct device *dev = &pdev->dev;
int num_dais;
dai_data = devm_kzalloc(dev, sizeof(*dai_data), GFP_KERNEL);
if (!dai_data)
return -ENOMEM;
dev_set_drvdata(dev, dai_data);
memset(&cfg, 0, sizeof(cfg));
cfg.q6i2s_ops = &q6i2s_ops;
cfg.q6dma_ops = &q6dma_ops;
cfg.q6hdmi_ops = &q6hdmi_ops;
dais = q6dsp_audio_ports_set_config(dev, &cfg, &num_dais);
return devm_snd_soc_register_component(dev, &q6apm_lpass_dai_component, dais, num_dais);
}
#ifdef CONFIG_OF
static const struct of_device_id q6apm_lpass_dai_device_id[] = {
{ .compatible = "qcom,q6apm-lpass-dais" },
{},
};
MODULE_DEVICE_TABLE(of, q6apm_lpass_dai_device_id);
#endif
static struct platform_driver q6apm_lpass_dai_platform_driver = {
.driver = {
.name = "q6apm-lpass-dais",
.of_match_table = of_match_ptr(q6apm_lpass_dai_device_id),
},
.probe = q6apm_lpass_dai_dev_probe,
};
module_platform_driver(q6apm_lpass_dai_platform_driver);
MODULE_DESCRIPTION("AUDIOREACH APM LPASS dai driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/qcom/qdsp6/q6apm-lpass-dais.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2011-2017, The Linux Foundation. All rights reserved.
// Copyright (c) 2018, Linaro Limited
#include <linux/init.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/pcm.h>
#include <linux/spinlock.h>
#include <sound/compress_driver.h>
#include <asm/dma.h>
#include <linux/dma-mapping.h>
#include <linux/of_device.h>
#include <sound/pcm_params.h>
#include "q6asm.h"
#include "q6routing.h"
#include "q6dsp-errno.h"
#define DRV_NAME "q6asm-fe-dai"
#define PLAYBACK_MIN_NUM_PERIODS 2
#define PLAYBACK_MAX_NUM_PERIODS 8
#define PLAYBACK_MAX_PERIOD_SIZE 65536
#define PLAYBACK_MIN_PERIOD_SIZE 128
#define CAPTURE_MIN_NUM_PERIODS 2
#define CAPTURE_MAX_NUM_PERIODS 8
#define CAPTURE_MAX_PERIOD_SIZE 4096
#define CAPTURE_MIN_PERIOD_SIZE 320
#define SID_MASK_DEFAULT 0xF
/* Default values used if user space does not set */
#define COMPR_PLAYBACK_MIN_FRAGMENT_SIZE (8 * 1024)
#define COMPR_PLAYBACK_MAX_FRAGMENT_SIZE (128 * 1024)
#define COMPR_PLAYBACK_MIN_NUM_FRAGMENTS (4)
#define COMPR_PLAYBACK_MAX_NUM_FRAGMENTS (16 * 4)
#define ALAC_CH_LAYOUT_MONO ((101 << 16) | 1)
#define ALAC_CH_LAYOUT_STEREO ((101 << 16) | 2)
enum stream_state {
Q6ASM_STREAM_IDLE = 0,
Q6ASM_STREAM_STOPPED,
Q6ASM_STREAM_RUNNING,
};
struct q6asm_dai_rtd {
struct snd_pcm_substream *substream;
struct snd_compr_stream *cstream;
struct snd_codec codec;
struct snd_dma_buffer dma_buffer;
spinlock_t lock;
phys_addr_t phys;
unsigned int pcm_size;
unsigned int pcm_count;
unsigned int pcm_irq_pos; /* IRQ position */
unsigned int periods;
unsigned int bytes_sent;
unsigned int bytes_received;
unsigned int copied_total;
uint16_t bits_per_sample;
uint16_t source; /* Encoding source bit mask */
struct audio_client *audio_client;
uint32_t next_track_stream_id;
bool next_track;
uint32_t stream_id;
uint16_t session_id;
enum stream_state state;
uint32_t initial_samples_drop;
uint32_t trailing_samples_drop;
bool notify_on_drain;
};
struct q6asm_dai_data {
struct snd_soc_dai_driver *dais;
int num_dais;
long long int sid;
};
static const struct snd_pcm_hardware q6asm_dai_hardware_capture = {
.info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_BATCH |
SNDRV_PCM_INFO_BLOCK_TRANSFER |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME),
.formats = (SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE),
.rates = SNDRV_PCM_RATE_8000_48000,
.rate_min = 8000,
.rate_max = 48000,
.channels_min = 1,
.channels_max = 4,
.buffer_bytes_max = CAPTURE_MAX_NUM_PERIODS *
CAPTURE_MAX_PERIOD_SIZE,
.period_bytes_min = CAPTURE_MIN_PERIOD_SIZE,
.period_bytes_max = CAPTURE_MAX_PERIOD_SIZE,
.periods_min = CAPTURE_MIN_NUM_PERIODS,
.periods_max = CAPTURE_MAX_NUM_PERIODS,
.fifo_size = 0,
};
static struct snd_pcm_hardware q6asm_dai_hardware_playback = {
.info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_BATCH |
SNDRV_PCM_INFO_BLOCK_TRANSFER |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME),
.formats = (SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE),
.rates = SNDRV_PCM_RATE_8000_192000,
.rate_min = 8000,
.rate_max = 192000,
.channels_min = 1,
.channels_max = 8,
.buffer_bytes_max = (PLAYBACK_MAX_NUM_PERIODS *
PLAYBACK_MAX_PERIOD_SIZE),
.period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE,
.period_bytes_max = PLAYBACK_MAX_PERIOD_SIZE,
.periods_min = PLAYBACK_MIN_NUM_PERIODS,
.periods_max = PLAYBACK_MAX_NUM_PERIODS,
.fifo_size = 0,
};
#define Q6ASM_FEDAI_DRIVER(num) { \
.playback = { \
.stream_name = "MultiMedia"#num" Playback", \
.rates = (SNDRV_PCM_RATE_8000_192000| \
SNDRV_PCM_RATE_KNOT), \
.formats = (SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE), \
.channels_min = 1, \
.channels_max = 8, \
.rate_min = 8000, \
.rate_max = 192000, \
}, \
.capture = { \
.stream_name = "MultiMedia"#num" Capture", \
.rates = (SNDRV_PCM_RATE_8000_48000| \
SNDRV_PCM_RATE_KNOT), \
.formats = (SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE), \
.channels_min = 1, \
.channels_max = 4, \
.rate_min = 8000, \
.rate_max = 48000, \
}, \
.name = "MultiMedia"#num, \
.id = MSM_FRONTEND_DAI_MULTIMEDIA##num, \
}
/* Conventional and unconventional sample rate supported */
static unsigned int supported_sample_rates[] = {
8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000,
88200, 96000, 176400, 192000
};
static struct snd_pcm_hw_constraint_list constraints_sample_rates = {
.count = ARRAY_SIZE(supported_sample_rates),
.list = supported_sample_rates,
.mask = 0,
};
static const struct snd_compr_codec_caps q6asm_compr_caps = {
.num_descriptors = 1,
.descriptor[0].max_ch = 2,
.descriptor[0].sample_rates = { 8000, 11025, 12000, 16000, 22050,
24000, 32000, 44100, 48000, 88200,
96000, 176400, 192000 },
.descriptor[0].num_sample_rates = 13,
.descriptor[0].bit_rate[0] = 320,
.descriptor[0].bit_rate[1] = 128,
.descriptor[0].num_bitrates = 2,
.descriptor[0].profiles = 0,
.descriptor[0].modes = SND_AUDIOCHANMODE_MP3_STEREO,
.descriptor[0].formats = 0,
};
static void event_handler(uint32_t opcode, uint32_t token,
void *payload, void *priv)
{
struct q6asm_dai_rtd *prtd = priv;
struct snd_pcm_substream *substream = prtd->substream;
switch (opcode) {
case ASM_CLIENT_EVENT_CMD_RUN_DONE:
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
q6asm_write_async(prtd->audio_client, prtd->stream_id,
prtd->pcm_count, 0, 0, 0);
break;
case ASM_CLIENT_EVENT_CMD_EOS_DONE:
prtd->state = Q6ASM_STREAM_STOPPED;
break;
case ASM_CLIENT_EVENT_DATA_WRITE_DONE: {
prtd->pcm_irq_pos += prtd->pcm_count;
snd_pcm_period_elapsed(substream);
if (prtd->state == Q6ASM_STREAM_RUNNING)
q6asm_write_async(prtd->audio_client, prtd->stream_id,
prtd->pcm_count, 0, 0, 0);
break;
}
case ASM_CLIENT_EVENT_DATA_READ_DONE:
prtd->pcm_irq_pos += prtd->pcm_count;
snd_pcm_period_elapsed(substream);
if (prtd->state == Q6ASM_STREAM_RUNNING)
q6asm_read(prtd->audio_client, prtd->stream_id);
break;
default:
break;
}
}
static int q6asm_dai_prepare(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_pcm_runtime *soc_prtd = asoc_substream_to_rtd(substream);
struct q6asm_dai_rtd *prtd = runtime->private_data;
struct q6asm_dai_data *pdata;
struct device *dev = component->dev;
int ret, i;
pdata = snd_soc_component_get_drvdata(component);
if (!pdata)
return -EINVAL;
if (!prtd || !prtd->audio_client) {
dev_err(dev, "%s: private data null or audio client freed\n",
__func__);
return -EINVAL;
}
prtd->pcm_count = snd_pcm_lib_period_bytes(substream);
prtd->pcm_irq_pos = 0;
/* rate and channels are sent to audio driver */
if (prtd->state) {
/* clear the previous setup if any */
q6asm_cmd(prtd->audio_client, prtd->stream_id, CMD_CLOSE);
q6asm_unmap_memory_regions(substream->stream,
prtd->audio_client);
q6routing_stream_close(soc_prtd->dai_link->id,
substream->stream);
}
ret = q6asm_map_memory_regions(substream->stream, prtd->audio_client,
prtd->phys,
(prtd->pcm_size / prtd->periods),
prtd->periods);
if (ret < 0) {
dev_err(dev, "Audio Start: Buffer Allocation failed rc = %d\n",
ret);
return -ENOMEM;
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
ret = q6asm_open_write(prtd->audio_client, prtd->stream_id,
FORMAT_LINEAR_PCM,
0, prtd->bits_per_sample, false);
} else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
ret = q6asm_open_read(prtd->audio_client, prtd->stream_id,
FORMAT_LINEAR_PCM,
prtd->bits_per_sample);
}
if (ret < 0) {
dev_err(dev, "%s: q6asm_open_write failed\n", __func__);
goto open_err;
}
prtd->session_id = q6asm_get_session_id(prtd->audio_client);
ret = q6routing_stream_open(soc_prtd->dai_link->id, LEGACY_PCM_MODE,
prtd->session_id, substream->stream);
if (ret) {
dev_err(dev, "%s: stream reg failed ret:%d\n", __func__, ret);
goto routing_err;
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
ret = q6asm_media_format_block_multi_ch_pcm(
prtd->audio_client, prtd->stream_id,
runtime->rate, runtime->channels, NULL,
prtd->bits_per_sample);
} else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
ret = q6asm_enc_cfg_blk_pcm_format_support(prtd->audio_client,
prtd->stream_id,
runtime->rate,
runtime->channels,
prtd->bits_per_sample);
/* Queue the buffers */
for (i = 0; i < runtime->periods; i++)
q6asm_read(prtd->audio_client, prtd->stream_id);
}
if (ret < 0)
dev_info(dev, "%s: CMD Format block failed\n", __func__);
else
prtd->state = Q6ASM_STREAM_RUNNING;
return ret;
routing_err:
q6asm_cmd(prtd->audio_client, prtd->stream_id, CMD_CLOSE);
open_err:
q6asm_unmap_memory_regions(substream->stream, prtd->audio_client);
q6asm_audio_client_free(prtd->audio_client);
prtd->audio_client = NULL;
return ret;
}
static int q6asm_dai_trigger(struct snd_soc_component *component,
struct snd_pcm_substream *substream, int cmd)
{
int ret = 0;
struct snd_pcm_runtime *runtime = substream->runtime;
struct q6asm_dai_rtd *prtd = runtime->private_data;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
ret = q6asm_run_nowait(prtd->audio_client, prtd->stream_id,
0, 0, 0);
break;
case SNDRV_PCM_TRIGGER_STOP:
prtd->state = Q6ASM_STREAM_STOPPED;
ret = q6asm_cmd_nowait(prtd->audio_client, prtd->stream_id,
CMD_EOS);
break;
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
ret = q6asm_cmd_nowait(prtd->audio_client, prtd->stream_id,
CMD_PAUSE);
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
static int q6asm_dai_open(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_pcm_runtime *soc_prtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_prtd, 0);
struct q6asm_dai_rtd *prtd;
struct q6asm_dai_data *pdata;
struct device *dev = component->dev;
int ret = 0;
int stream_id;
stream_id = cpu_dai->driver->id;
pdata = snd_soc_component_get_drvdata(component);
if (!pdata) {
dev_err(dev, "Drv data not found ..\n");
return -EINVAL;
}
prtd = kzalloc(sizeof(struct q6asm_dai_rtd), GFP_KERNEL);
if (prtd == NULL)
return -ENOMEM;
prtd->substream = substream;
prtd->audio_client = q6asm_audio_client_alloc(dev,
(q6asm_cb)event_handler, prtd, stream_id,
LEGACY_PCM_MODE);
if (IS_ERR(prtd->audio_client)) {
dev_info(dev, "%s: Could not allocate memory\n", __func__);
ret = PTR_ERR(prtd->audio_client);
kfree(prtd);
return ret;
}
/* DSP expects stream id from 1 */
prtd->stream_id = 1;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
runtime->hw = q6asm_dai_hardware_playback;
else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
runtime->hw = q6asm_dai_hardware_capture;
ret = snd_pcm_hw_constraint_list(runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
&constraints_sample_rates);
if (ret < 0)
dev_info(dev, "snd_pcm_hw_constraint_list failed\n");
/* Ensure that buffer size is a multiple of period size */
ret = snd_pcm_hw_constraint_integer(runtime,
SNDRV_PCM_HW_PARAM_PERIODS);
if (ret < 0)
dev_info(dev, "snd_pcm_hw_constraint_integer failed\n");
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
ret = snd_pcm_hw_constraint_minmax(runtime,
SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
PLAYBACK_MIN_NUM_PERIODS * PLAYBACK_MIN_PERIOD_SIZE,
PLAYBACK_MAX_NUM_PERIODS * PLAYBACK_MAX_PERIOD_SIZE);
if (ret < 0) {
dev_err(dev, "constraint for buffer bytes min max ret = %d\n",
ret);
}
}
ret = snd_pcm_hw_constraint_step(runtime, 0,
SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 32);
if (ret < 0) {
dev_err(dev, "constraint for period bytes step ret = %d\n",
ret);
}
ret = snd_pcm_hw_constraint_step(runtime, 0,
SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 32);
if (ret < 0) {
dev_err(dev, "constraint for buffer bytes step ret = %d\n",
ret);
}
runtime->private_data = prtd;
snd_soc_set_runtime_hwparams(substream, &q6asm_dai_hardware_playback);
runtime->dma_bytes = q6asm_dai_hardware_playback.buffer_bytes_max;
if (pdata->sid < 0)
prtd->phys = substream->dma_buffer.addr;
else
prtd->phys = substream->dma_buffer.addr | (pdata->sid << 32);
return 0;
}
static int q6asm_dai_close(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_pcm_runtime *soc_prtd = asoc_substream_to_rtd(substream);
struct q6asm_dai_rtd *prtd = runtime->private_data;
if (prtd->audio_client) {
if (prtd->state)
q6asm_cmd(prtd->audio_client, prtd->stream_id,
CMD_CLOSE);
q6asm_unmap_memory_regions(substream->stream,
prtd->audio_client);
q6asm_audio_client_free(prtd->audio_client);
prtd->audio_client = NULL;
}
q6routing_stream_close(soc_prtd->dai_link->id,
substream->stream);
kfree(prtd);
return 0;
}
static snd_pcm_uframes_t q6asm_dai_pointer(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct q6asm_dai_rtd *prtd = runtime->private_data;
if (prtd->pcm_irq_pos >= prtd->pcm_size)
prtd->pcm_irq_pos = 0;
return bytes_to_frames(runtime, (prtd->pcm_irq_pos));
}
static int q6asm_dai_hw_params(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct q6asm_dai_rtd *prtd = runtime->private_data;
prtd->pcm_size = params_buffer_bytes(params);
prtd->periods = params_periods(params);
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
prtd->bits_per_sample = 16;
break;
case SNDRV_PCM_FORMAT_S24_LE:
prtd->bits_per_sample = 24;
break;
}
return 0;
}
static void compress_event_handler(uint32_t opcode, uint32_t token,
void *payload, void *priv)
{
struct q6asm_dai_rtd *prtd = priv;
struct snd_compr_stream *substream = prtd->cstream;
unsigned long flags;
u32 wflags = 0;
uint64_t avail;
uint32_t bytes_written, bytes_to_write;
bool is_last_buffer = false;
switch (opcode) {
case ASM_CLIENT_EVENT_CMD_RUN_DONE:
spin_lock_irqsave(&prtd->lock, flags);
if (!prtd->bytes_sent) {
q6asm_stream_remove_initial_silence(prtd->audio_client,
prtd->stream_id,
prtd->initial_samples_drop);
q6asm_write_async(prtd->audio_client, prtd->stream_id,
prtd->pcm_count, 0, 0, 0);
prtd->bytes_sent += prtd->pcm_count;
}
spin_unlock_irqrestore(&prtd->lock, flags);
break;
case ASM_CLIENT_EVENT_CMD_EOS_DONE:
spin_lock_irqsave(&prtd->lock, flags);
if (prtd->notify_on_drain) {
if (substream->partial_drain) {
/*
* Close old stream and make it stale, switch
* the active stream now!
*/
q6asm_cmd_nowait(prtd->audio_client,
prtd->stream_id,
CMD_CLOSE);
/*
* vaild stream ids start from 1, So we are
* toggling this between 1 and 2.
*/
prtd->stream_id = (prtd->stream_id == 1 ? 2 : 1);
}
snd_compr_drain_notify(prtd->cstream);
prtd->notify_on_drain = false;
} else {
prtd->state = Q6ASM_STREAM_STOPPED;
}
spin_unlock_irqrestore(&prtd->lock, flags);
break;
case ASM_CLIENT_EVENT_DATA_WRITE_DONE:
spin_lock_irqsave(&prtd->lock, flags);
bytes_written = token >> ASM_WRITE_TOKEN_LEN_SHIFT;
prtd->copied_total += bytes_written;
snd_compr_fragment_elapsed(substream);
if (prtd->state != Q6ASM_STREAM_RUNNING) {
spin_unlock_irqrestore(&prtd->lock, flags);
break;
}
avail = prtd->bytes_received - prtd->bytes_sent;
if (avail > prtd->pcm_count) {
bytes_to_write = prtd->pcm_count;
} else {
if (substream->partial_drain || prtd->notify_on_drain)
is_last_buffer = true;
bytes_to_write = avail;
}
if (bytes_to_write) {
if (substream->partial_drain && is_last_buffer) {
wflags |= ASM_LAST_BUFFER_FLAG;
q6asm_stream_remove_trailing_silence(prtd->audio_client,
prtd->stream_id,
prtd->trailing_samples_drop);
}
q6asm_write_async(prtd->audio_client, prtd->stream_id,
bytes_to_write, 0, 0, wflags);
prtd->bytes_sent += bytes_to_write;
}
if (prtd->notify_on_drain && is_last_buffer)
q6asm_cmd_nowait(prtd->audio_client,
prtd->stream_id, CMD_EOS);
spin_unlock_irqrestore(&prtd->lock, flags);
break;
default:
break;
}
}
static int q6asm_dai_compr_open(struct snd_soc_component *component,
struct snd_compr_stream *stream)
{
struct snd_soc_pcm_runtime *rtd = stream->private_data;
struct snd_compr_runtime *runtime = stream->runtime;
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct q6asm_dai_data *pdata;
struct device *dev = component->dev;
struct q6asm_dai_rtd *prtd;
int stream_id, size, ret;
stream_id = cpu_dai->driver->id;
pdata = snd_soc_component_get_drvdata(component);
if (!pdata) {
dev_err(dev, "Drv data not found ..\n");
return -EINVAL;
}
prtd = kzalloc(sizeof(*prtd), GFP_KERNEL);
if (!prtd)
return -ENOMEM;
/* DSP expects stream id from 1 */
prtd->stream_id = 1;
prtd->cstream = stream;
prtd->audio_client = q6asm_audio_client_alloc(dev,
(q6asm_cb)compress_event_handler,
prtd, stream_id, LEGACY_PCM_MODE);
if (IS_ERR(prtd->audio_client)) {
dev_err(dev, "Could not allocate memory\n");
ret = PTR_ERR(prtd->audio_client);
goto free_prtd;
}
size = COMPR_PLAYBACK_MAX_FRAGMENT_SIZE *
COMPR_PLAYBACK_MAX_NUM_FRAGMENTS;
ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, dev, size,
&prtd->dma_buffer);
if (ret) {
dev_err(dev, "Cannot allocate buffer(s)\n");
goto free_client;
}
if (pdata->sid < 0)
prtd->phys = prtd->dma_buffer.addr;
else
prtd->phys = prtd->dma_buffer.addr | (pdata->sid << 32);
snd_compr_set_runtime_buffer(stream, &prtd->dma_buffer);
spin_lock_init(&prtd->lock);
runtime->private_data = prtd;
return 0;
free_client:
q6asm_audio_client_free(prtd->audio_client);
free_prtd:
kfree(prtd);
return ret;
}
static int q6asm_dai_compr_free(struct snd_soc_component *component,
struct snd_compr_stream *stream)
{
struct snd_compr_runtime *runtime = stream->runtime;
struct q6asm_dai_rtd *prtd = runtime->private_data;
struct snd_soc_pcm_runtime *rtd = stream->private_data;
if (prtd->audio_client) {
if (prtd->state) {
q6asm_cmd(prtd->audio_client, prtd->stream_id,
CMD_CLOSE);
if (prtd->next_track_stream_id) {
q6asm_cmd(prtd->audio_client,
prtd->next_track_stream_id,
CMD_CLOSE);
}
}
snd_dma_free_pages(&prtd->dma_buffer);
q6asm_unmap_memory_regions(stream->direction,
prtd->audio_client);
q6asm_audio_client_free(prtd->audio_client);
prtd->audio_client = NULL;
}
q6routing_stream_close(rtd->dai_link->id, stream->direction);
kfree(prtd);
return 0;
}
static int __q6asm_dai_compr_set_codec_params(struct snd_soc_component *component,
struct snd_compr_stream *stream,
struct snd_codec *codec,
int stream_id)
{
struct snd_compr_runtime *runtime = stream->runtime;
struct q6asm_dai_rtd *prtd = runtime->private_data;
struct q6asm_flac_cfg flac_cfg;
struct q6asm_wma_cfg wma_cfg;
struct q6asm_alac_cfg alac_cfg;
struct q6asm_ape_cfg ape_cfg;
unsigned int wma_v9 = 0;
struct device *dev = component->dev;
int ret;
union snd_codec_options *codec_options;
struct snd_dec_flac *flac;
struct snd_dec_wma *wma;
struct snd_dec_alac *alac;
struct snd_dec_ape *ape;
codec_options = &(prtd->codec.options);
memcpy(&prtd->codec, codec, sizeof(*codec));
switch (codec->id) {
case SND_AUDIOCODEC_FLAC:
memset(&flac_cfg, 0x0, sizeof(struct q6asm_flac_cfg));
flac = &codec_options->flac_d;
flac_cfg.ch_cfg = codec->ch_in;
flac_cfg.sample_rate = codec->sample_rate;
flac_cfg.stream_info_present = 1;
flac_cfg.sample_size = flac->sample_size;
flac_cfg.min_blk_size = flac->min_blk_size;
flac_cfg.max_blk_size = flac->max_blk_size;
flac_cfg.max_frame_size = flac->max_frame_size;
flac_cfg.min_frame_size = flac->min_frame_size;
ret = q6asm_stream_media_format_block_flac(prtd->audio_client,
stream_id,
&flac_cfg);
if (ret < 0) {
dev_err(dev, "FLAC CMD Format block failed:%d\n", ret);
return -EIO;
}
break;
case SND_AUDIOCODEC_WMA:
wma = &codec_options->wma_d;
memset(&wma_cfg, 0x0, sizeof(struct q6asm_wma_cfg));
wma_cfg.sample_rate = codec->sample_rate;
wma_cfg.num_channels = codec->ch_in;
wma_cfg.bytes_per_sec = codec->bit_rate / 8;
wma_cfg.block_align = codec->align;
wma_cfg.bits_per_sample = prtd->bits_per_sample;
wma_cfg.enc_options = wma->encoder_option;
wma_cfg.adv_enc_options = wma->adv_encoder_option;
wma_cfg.adv_enc_options2 = wma->adv_encoder_option2;
if (wma_cfg.num_channels == 1)
wma_cfg.channel_mask = 4; /* Mono Center */
else if (wma_cfg.num_channels == 2)
wma_cfg.channel_mask = 3; /* Stereo FL/FR */
else
return -EINVAL;
/* check the codec profile */
switch (codec->profile) {
case SND_AUDIOPROFILE_WMA9:
wma_cfg.fmtag = 0x161;
wma_v9 = 1;
break;
case SND_AUDIOPROFILE_WMA10:
wma_cfg.fmtag = 0x166;
break;
case SND_AUDIOPROFILE_WMA9_PRO:
wma_cfg.fmtag = 0x162;
break;
case SND_AUDIOPROFILE_WMA9_LOSSLESS:
wma_cfg.fmtag = 0x163;
break;
case SND_AUDIOPROFILE_WMA10_LOSSLESS:
wma_cfg.fmtag = 0x167;
break;
default:
dev_err(dev, "Unknown WMA profile:%x\n",
codec->profile);
return -EIO;
}
if (wma_v9)
ret = q6asm_stream_media_format_block_wma_v9(
prtd->audio_client, stream_id,
&wma_cfg);
else
ret = q6asm_stream_media_format_block_wma_v10(
prtd->audio_client, stream_id,
&wma_cfg);
if (ret < 0) {
dev_err(dev, "WMA9 CMD failed:%d\n", ret);
return -EIO;
}
break;
case SND_AUDIOCODEC_ALAC:
memset(&alac_cfg, 0x0, sizeof(alac_cfg));
alac = &codec_options->alac_d;
alac_cfg.sample_rate = codec->sample_rate;
alac_cfg.avg_bit_rate = codec->bit_rate;
alac_cfg.bit_depth = prtd->bits_per_sample;
alac_cfg.num_channels = codec->ch_in;
alac_cfg.frame_length = alac->frame_length;
alac_cfg.pb = alac->pb;
alac_cfg.mb = alac->mb;
alac_cfg.kb = alac->kb;
alac_cfg.max_run = alac->max_run;
alac_cfg.compatible_version = alac->compatible_version;
alac_cfg.max_frame_bytes = alac->max_frame_bytes;
switch (codec->ch_in) {
case 1:
alac_cfg.channel_layout_tag = ALAC_CH_LAYOUT_MONO;
break;
case 2:
alac_cfg.channel_layout_tag = ALAC_CH_LAYOUT_STEREO;
break;
}
ret = q6asm_stream_media_format_block_alac(prtd->audio_client,
stream_id,
&alac_cfg);
if (ret < 0) {
dev_err(dev, "ALAC CMD Format block failed:%d\n", ret);
return -EIO;
}
break;
case SND_AUDIOCODEC_APE:
memset(&ape_cfg, 0x0, sizeof(ape_cfg));
ape = &codec_options->ape_d;
ape_cfg.sample_rate = codec->sample_rate;
ape_cfg.num_channels = codec->ch_in;
ape_cfg.bits_per_sample = prtd->bits_per_sample;
ape_cfg.compatible_version = ape->compatible_version;
ape_cfg.compression_level = ape->compression_level;
ape_cfg.format_flags = ape->format_flags;
ape_cfg.blocks_per_frame = ape->blocks_per_frame;
ape_cfg.final_frame_blocks = ape->final_frame_blocks;
ape_cfg.total_frames = ape->total_frames;
ape_cfg.seek_table_present = ape->seek_table_present;
ret = q6asm_stream_media_format_block_ape(prtd->audio_client,
stream_id,
&ape_cfg);
if (ret < 0) {
dev_err(dev, "APE CMD Format block failed:%d\n", ret);
return -EIO;
}
break;
default:
break;
}
return 0;
}
static int q6asm_dai_compr_set_params(struct snd_soc_component *component,
struct snd_compr_stream *stream,
struct snd_compr_params *params)
{
struct snd_compr_runtime *runtime = stream->runtime;
struct q6asm_dai_rtd *prtd = runtime->private_data;
struct snd_soc_pcm_runtime *rtd = stream->private_data;
int dir = stream->direction;
struct q6asm_dai_data *pdata;
struct device *dev = component->dev;
int ret;
pdata = snd_soc_component_get_drvdata(component);
if (!pdata)
return -EINVAL;
if (!prtd || !prtd->audio_client) {
dev_err(dev, "private data null or audio client freed\n");
return -EINVAL;
}
prtd->periods = runtime->fragments;
prtd->pcm_count = runtime->fragment_size;
prtd->pcm_size = runtime->fragments * runtime->fragment_size;
prtd->bits_per_sample = 16;
if (dir == SND_COMPRESS_PLAYBACK) {
ret = q6asm_open_write(prtd->audio_client, prtd->stream_id, params->codec.id,
params->codec.profile, prtd->bits_per_sample,
true);
if (ret < 0) {
dev_err(dev, "q6asm_open_write failed\n");
q6asm_audio_client_free(prtd->audio_client);
prtd->audio_client = NULL;
return ret;
}
}
prtd->session_id = q6asm_get_session_id(prtd->audio_client);
ret = q6routing_stream_open(rtd->dai_link->id, LEGACY_PCM_MODE,
prtd->session_id, dir);
if (ret) {
dev_err(dev, "Stream reg failed ret:%d\n", ret);
return ret;
}
ret = __q6asm_dai_compr_set_codec_params(component, stream,
¶ms->codec,
prtd->stream_id);
if (ret) {
dev_err(dev, "codec param setup failed ret:%d\n", ret);
return ret;
}
ret = q6asm_map_memory_regions(dir, prtd->audio_client, prtd->phys,
(prtd->pcm_size / prtd->periods),
prtd->periods);
if (ret < 0) {
dev_err(dev, "Buffer Mapping failed ret:%d\n", ret);
return -ENOMEM;
}
prtd->state = Q6ASM_STREAM_RUNNING;
return 0;
}
static int q6asm_dai_compr_set_metadata(struct snd_soc_component *component,
struct snd_compr_stream *stream,
struct snd_compr_metadata *metadata)
{
struct snd_compr_runtime *runtime = stream->runtime;
struct q6asm_dai_rtd *prtd = runtime->private_data;
int ret = 0;
switch (metadata->key) {
case SNDRV_COMPRESS_ENCODER_PADDING:
prtd->trailing_samples_drop = metadata->value[0];
break;
case SNDRV_COMPRESS_ENCODER_DELAY:
prtd->initial_samples_drop = metadata->value[0];
if (prtd->next_track_stream_id) {
ret = q6asm_open_write(prtd->audio_client,
prtd->next_track_stream_id,
prtd->codec.id,
prtd->codec.profile,
prtd->bits_per_sample,
true);
if (ret < 0) {
dev_err(component->dev, "q6asm_open_write failed\n");
return ret;
}
ret = __q6asm_dai_compr_set_codec_params(component, stream,
&prtd->codec,
prtd->next_track_stream_id);
if (ret < 0) {
dev_err(component->dev, "q6asm_open_write failed\n");
return ret;
}
ret = q6asm_stream_remove_initial_silence(prtd->audio_client,
prtd->next_track_stream_id,
prtd->initial_samples_drop);
prtd->next_track_stream_id = 0;
}
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
static int q6asm_dai_compr_trigger(struct snd_soc_component *component,
struct snd_compr_stream *stream, int cmd)
{
struct snd_compr_runtime *runtime = stream->runtime;
struct q6asm_dai_rtd *prtd = runtime->private_data;
int ret = 0;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
ret = q6asm_run_nowait(prtd->audio_client, prtd->stream_id,
0, 0, 0);
break;
case SNDRV_PCM_TRIGGER_STOP:
prtd->state = Q6ASM_STREAM_STOPPED;
ret = q6asm_cmd_nowait(prtd->audio_client, prtd->stream_id,
CMD_EOS);
break;
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
ret = q6asm_cmd_nowait(prtd->audio_client, prtd->stream_id,
CMD_PAUSE);
break;
case SND_COMPR_TRIGGER_NEXT_TRACK:
prtd->next_track = true;
prtd->next_track_stream_id = (prtd->stream_id == 1 ? 2 : 1);
break;
case SND_COMPR_TRIGGER_DRAIN:
case SND_COMPR_TRIGGER_PARTIAL_DRAIN:
prtd->notify_on_drain = true;
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
static int q6asm_dai_compr_pointer(struct snd_soc_component *component,
struct snd_compr_stream *stream,
struct snd_compr_tstamp *tstamp)
{
struct snd_compr_runtime *runtime = stream->runtime;
struct q6asm_dai_rtd *prtd = runtime->private_data;
unsigned long flags;
spin_lock_irqsave(&prtd->lock, flags);
tstamp->copied_total = prtd->copied_total;
tstamp->byte_offset = prtd->copied_total % prtd->pcm_size;
spin_unlock_irqrestore(&prtd->lock, flags);
return 0;
}
static int q6asm_compr_copy(struct snd_soc_component *component,
struct snd_compr_stream *stream, char __user *buf,
size_t count)
{
struct snd_compr_runtime *runtime = stream->runtime;
struct q6asm_dai_rtd *prtd = runtime->private_data;
unsigned long flags;
u32 wflags = 0;
int avail, bytes_in_flight = 0;
void *dstn;
size_t copy;
u32 app_pointer;
u32 bytes_received;
bytes_received = prtd->bytes_received;
/**
* Make sure that next track data pointer is aligned at 32 bit boundary
* This is a Mandatory requirement from DSP data buffers alignment
*/
if (prtd->next_track)
bytes_received = ALIGN(prtd->bytes_received, prtd->pcm_count);
app_pointer = bytes_received/prtd->pcm_size;
app_pointer = bytes_received - (app_pointer * prtd->pcm_size);
dstn = prtd->dma_buffer.area + app_pointer;
if (count < prtd->pcm_size - app_pointer) {
if (copy_from_user(dstn, buf, count))
return -EFAULT;
} else {
copy = prtd->pcm_size - app_pointer;
if (copy_from_user(dstn, buf, copy))
return -EFAULT;
if (copy_from_user(prtd->dma_buffer.area, buf + copy,
count - copy))
return -EFAULT;
}
spin_lock_irqsave(&prtd->lock, flags);
bytes_in_flight = prtd->bytes_received - prtd->copied_total;
if (prtd->next_track) {
prtd->next_track = false;
prtd->copied_total = ALIGN(prtd->copied_total, prtd->pcm_count);
prtd->bytes_sent = ALIGN(prtd->bytes_sent, prtd->pcm_count);
}
prtd->bytes_received = bytes_received + count;
/* Kick off the data to dsp if its starving!! */
if (prtd->state == Q6ASM_STREAM_RUNNING && (bytes_in_flight == 0)) {
uint32_t bytes_to_write = prtd->pcm_count;
avail = prtd->bytes_received - prtd->bytes_sent;
if (avail < prtd->pcm_count)
bytes_to_write = avail;
q6asm_write_async(prtd->audio_client, prtd->stream_id,
bytes_to_write, 0, 0, wflags);
prtd->bytes_sent += bytes_to_write;
}
spin_unlock_irqrestore(&prtd->lock, flags);
return count;
}
static int q6asm_dai_compr_mmap(struct snd_soc_component *component,
struct snd_compr_stream *stream,
struct vm_area_struct *vma)
{
struct snd_compr_runtime *runtime = stream->runtime;
struct q6asm_dai_rtd *prtd = runtime->private_data;
struct device *dev = component->dev;
return dma_mmap_coherent(dev, vma,
prtd->dma_buffer.area, prtd->dma_buffer.addr,
prtd->dma_buffer.bytes);
}
static int q6asm_dai_compr_get_caps(struct snd_soc_component *component,
struct snd_compr_stream *stream,
struct snd_compr_caps *caps)
{
caps->direction = SND_COMPRESS_PLAYBACK;
caps->min_fragment_size = COMPR_PLAYBACK_MIN_FRAGMENT_SIZE;
caps->max_fragment_size = COMPR_PLAYBACK_MAX_FRAGMENT_SIZE;
caps->min_fragments = COMPR_PLAYBACK_MIN_NUM_FRAGMENTS;
caps->max_fragments = COMPR_PLAYBACK_MAX_NUM_FRAGMENTS;
caps->num_codecs = 5;
caps->codecs[0] = SND_AUDIOCODEC_MP3;
caps->codecs[1] = SND_AUDIOCODEC_FLAC;
caps->codecs[2] = SND_AUDIOCODEC_WMA;
caps->codecs[3] = SND_AUDIOCODEC_ALAC;
caps->codecs[4] = SND_AUDIOCODEC_APE;
return 0;
}
static int q6asm_dai_compr_get_codec_caps(struct snd_soc_component *component,
struct snd_compr_stream *stream,
struct snd_compr_codec_caps *codec)
{
switch (codec->codec) {
case SND_AUDIOCODEC_MP3:
*codec = q6asm_compr_caps;
break;
default:
break;
}
return 0;
}
static const struct snd_compress_ops q6asm_dai_compress_ops = {
.open = q6asm_dai_compr_open,
.free = q6asm_dai_compr_free,
.set_params = q6asm_dai_compr_set_params,
.set_metadata = q6asm_dai_compr_set_metadata,
.pointer = q6asm_dai_compr_pointer,
.trigger = q6asm_dai_compr_trigger,
.get_caps = q6asm_dai_compr_get_caps,
.get_codec_caps = q6asm_dai_compr_get_codec_caps,
.mmap = q6asm_dai_compr_mmap,
.copy = q6asm_compr_copy,
};
static int q6asm_dai_pcm_new(struct snd_soc_component *component,
struct snd_soc_pcm_runtime *rtd)
{
struct snd_pcm *pcm = rtd->pcm;
size_t size = q6asm_dai_hardware_playback.buffer_bytes_max;
return snd_pcm_set_fixed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
component->dev, size);
}
static const struct snd_soc_dapm_widget q6asm_dapm_widgets[] = {
SND_SOC_DAPM_AIF_IN("MM_DL1", "MultiMedia1 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("MM_DL2", "MultiMedia2 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("MM_DL3", "MultiMedia3 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("MM_DL4", "MultiMedia4 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("MM_DL5", "MultiMedia5 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("MM_DL6", "MultiMedia6 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("MM_DL7", "MultiMedia7 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("MM_DL8", "MultiMedia8 Playback", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("MM_UL1", "MultiMedia1 Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("MM_UL2", "MultiMedia2 Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("MM_UL3", "MultiMedia3 Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("MM_UL4", "MultiMedia4 Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("MM_UL5", "MultiMedia5 Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("MM_UL6", "MultiMedia6 Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("MM_UL7", "MultiMedia7 Capture", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("MM_UL8", "MultiMedia8 Capture", 0, SND_SOC_NOPM, 0, 0),
};
static const struct snd_soc_component_driver q6asm_fe_dai_component = {
.name = DRV_NAME,
.open = q6asm_dai_open,
.hw_params = q6asm_dai_hw_params,
.close = q6asm_dai_close,
.prepare = q6asm_dai_prepare,
.trigger = q6asm_dai_trigger,
.pointer = q6asm_dai_pointer,
.pcm_construct = q6asm_dai_pcm_new,
.compress_ops = &q6asm_dai_compress_ops,
.dapm_widgets = q6asm_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(q6asm_dapm_widgets),
.legacy_dai_naming = 1,
};
static struct snd_soc_dai_driver q6asm_fe_dais_template[] = {
Q6ASM_FEDAI_DRIVER(1),
Q6ASM_FEDAI_DRIVER(2),
Q6ASM_FEDAI_DRIVER(3),
Q6ASM_FEDAI_DRIVER(4),
Q6ASM_FEDAI_DRIVER(5),
Q6ASM_FEDAI_DRIVER(6),
Q6ASM_FEDAI_DRIVER(7),
Q6ASM_FEDAI_DRIVER(8),
};
static const struct snd_soc_dai_ops q6asm_dai_ops = {
.compress_new = snd_soc_new_compress,
};
static int of_q6asm_parse_dai_data(struct device *dev,
struct q6asm_dai_data *pdata)
{
struct snd_soc_dai_driver *dai_drv;
struct snd_soc_pcm_stream empty_stream;
struct device_node *node;
int ret, id, dir, idx = 0;
pdata->num_dais = of_get_child_count(dev->of_node);
if (!pdata->num_dais) {
dev_err(dev, "No dais found in DT\n");
return -EINVAL;
}
pdata->dais = devm_kcalloc(dev, pdata->num_dais, sizeof(*dai_drv),
GFP_KERNEL);
if (!pdata->dais)
return -ENOMEM;
memset(&empty_stream, 0, sizeof(empty_stream));
for_each_child_of_node(dev->of_node, node) {
ret = of_property_read_u32(node, "reg", &id);
if (ret || id >= MAX_SESSIONS || id < 0) {
dev_err(dev, "valid dai id not found:%d\n", ret);
continue;
}
dai_drv = &pdata->dais[idx++];
*dai_drv = q6asm_fe_dais_template[id];
ret = of_property_read_u32(node, "direction", &dir);
if (ret)
continue;
if (dir == Q6ASM_DAI_RX)
dai_drv->capture = empty_stream;
else if (dir == Q6ASM_DAI_TX)
dai_drv->playback = empty_stream;
if (of_property_read_bool(node, "is-compress-dai"))
dai_drv->ops = &q6asm_dai_ops;
}
return 0;
}
static int q6asm_dai_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *node = dev->of_node;
struct of_phandle_args args;
struct q6asm_dai_data *pdata;
int rc;
pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
if (!pdata)
return -ENOMEM;
rc = of_parse_phandle_with_fixed_args(node, "iommus", 1, 0, &args);
if (rc < 0)
pdata->sid = -1;
else
pdata->sid = args.args[0] & SID_MASK_DEFAULT;
dev_set_drvdata(dev, pdata);
rc = of_q6asm_parse_dai_data(dev, pdata);
if (rc)
return rc;
return devm_snd_soc_register_component(dev, &q6asm_fe_dai_component,
pdata->dais, pdata->num_dais);
}
#ifdef CONFIG_OF
static const struct of_device_id q6asm_dai_device_id[] = {
{ .compatible = "qcom,q6asm-dais" },
{},
};
MODULE_DEVICE_TABLE(of, q6asm_dai_device_id);
#endif
static struct platform_driver q6asm_dai_platform_driver = {
.driver = {
.name = "q6asm-dai",
.of_match_table = of_match_ptr(q6asm_dai_device_id),
},
.probe = q6asm_dai_probe,
};
module_platform_driver(q6asm_dai_platform_driver);
MODULE_DESCRIPTION("Q6ASM dai driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/qcom/qdsp6/q6asm-dai.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2020, Linaro Limited
#include <linux/err.h>
#include <linux/init.h>
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include "q6dsp-lpass-clocks.h"
#include "q6afe.h"
#define Q6AFE_CLK(id) { \
.clk_id = id, \
.q6dsp_clk_id = Q6AFE_##id, \
.name = #id, \
.rate = 19200000, \
}
static const struct q6dsp_clk_init q6afe_clks[] = {
Q6AFE_CLK(LPASS_CLK_ID_PRI_MI2S_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_PRI_MI2S_EBIT),
Q6AFE_CLK(LPASS_CLK_ID_SEC_MI2S_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_SEC_MI2S_EBIT),
Q6AFE_CLK(LPASS_CLK_ID_TER_MI2S_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_TER_MI2S_EBIT),
Q6AFE_CLK(LPASS_CLK_ID_QUAD_MI2S_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_QUAD_MI2S_EBIT),
Q6AFE_CLK(LPASS_CLK_ID_SPEAKER_I2S_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_SPEAKER_I2S_EBIT),
Q6AFE_CLK(LPASS_CLK_ID_SPEAKER_I2S_OSR),
Q6AFE_CLK(LPASS_CLK_ID_QUI_MI2S_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_QUI_MI2S_EBIT),
Q6AFE_CLK(LPASS_CLK_ID_SEN_MI2S_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_SEN_MI2S_EBIT),
Q6AFE_CLK(LPASS_CLK_ID_INT0_MI2S_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_INT1_MI2S_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_INT2_MI2S_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_INT3_MI2S_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_INT4_MI2S_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_INT5_MI2S_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_INT6_MI2S_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_QUI_MI2S_OSR),
Q6AFE_CLK(LPASS_CLK_ID_PRI_PCM_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_PRI_PCM_EBIT),
Q6AFE_CLK(LPASS_CLK_ID_SEC_PCM_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_SEC_PCM_EBIT),
Q6AFE_CLK(LPASS_CLK_ID_TER_PCM_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_TER_PCM_EBIT),
Q6AFE_CLK(LPASS_CLK_ID_QUAD_PCM_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_QUAD_PCM_EBIT),
Q6AFE_CLK(LPASS_CLK_ID_QUIN_PCM_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_QUIN_PCM_EBIT),
Q6AFE_CLK(LPASS_CLK_ID_QUI_PCM_OSR),
Q6AFE_CLK(LPASS_CLK_ID_PRI_TDM_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_PRI_TDM_EBIT),
Q6AFE_CLK(LPASS_CLK_ID_SEC_TDM_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_SEC_TDM_EBIT),
Q6AFE_CLK(LPASS_CLK_ID_TER_TDM_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_TER_TDM_EBIT),
Q6AFE_CLK(LPASS_CLK_ID_QUAD_TDM_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_QUAD_TDM_EBIT),
Q6AFE_CLK(LPASS_CLK_ID_QUIN_TDM_IBIT),
Q6AFE_CLK(LPASS_CLK_ID_QUIN_TDM_EBIT),
Q6AFE_CLK(LPASS_CLK_ID_QUIN_TDM_OSR),
Q6AFE_CLK(LPASS_CLK_ID_MCLK_1),
Q6AFE_CLK(LPASS_CLK_ID_MCLK_2),
Q6AFE_CLK(LPASS_CLK_ID_MCLK_3),
Q6AFE_CLK(LPASS_CLK_ID_MCLK_4),
Q6AFE_CLK(LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE),
Q6AFE_CLK(LPASS_CLK_ID_INT_MCLK_0),
Q6AFE_CLK(LPASS_CLK_ID_INT_MCLK_1),
Q6AFE_CLK(LPASS_CLK_ID_WSA_CORE_MCLK),
Q6AFE_CLK(LPASS_CLK_ID_WSA_CORE_NPL_MCLK),
Q6AFE_CLK(LPASS_CLK_ID_VA_CORE_MCLK),
Q6AFE_CLK(LPASS_CLK_ID_TX_CORE_MCLK),
Q6AFE_CLK(LPASS_CLK_ID_TX_CORE_NPL_MCLK),
Q6AFE_CLK(LPASS_CLK_ID_RX_CORE_MCLK),
Q6AFE_CLK(LPASS_CLK_ID_RX_CORE_NPL_MCLK),
Q6AFE_CLK(LPASS_CLK_ID_VA_CORE_2X_MCLK),
Q6DSP_VOTE_CLK(LPASS_HW_AVTIMER_VOTE,
Q6AFE_LPASS_CORE_AVTIMER_BLOCK,
"LPASS_AVTIMER_MACRO"),
Q6DSP_VOTE_CLK(LPASS_HW_MACRO_VOTE,
Q6AFE_LPASS_CORE_HW_MACRO_BLOCK,
"LPASS_HW_MACRO"),
Q6DSP_VOTE_CLK(LPASS_HW_DCODEC_VOTE,
Q6AFE_LPASS_CORE_HW_DCODEC_BLOCK,
"LPASS_HW_DCODEC"),
};
static const struct q6dsp_clk_desc q6dsp_clk_q6afe __maybe_unused = {
.clks = q6afe_clks,
.num_clks = ARRAY_SIZE(q6afe_clks),
.lpass_set_clk = q6afe_set_lpass_clock,
.lpass_vote_clk = q6afe_vote_lpass_core_hw,
.lpass_unvote_clk = q6afe_unvote_lpass_core_hw,
};
#ifdef CONFIG_OF
static const struct of_device_id q6afe_clock_device_id[] = {
{ .compatible = "qcom,q6afe-clocks", .data = &q6dsp_clk_q6afe },
{},
};
MODULE_DEVICE_TABLE(of, q6afe_clock_device_id);
#endif
static struct platform_driver q6afe_clock_platform_driver = {
.driver = {
.name = "q6afe-clock",
.of_match_table = of_match_ptr(q6afe_clock_device_id),
},
.probe = q6dsp_clock_dev_probe,
};
module_platform_driver(q6afe_clock_platform_driver);
MODULE_DESCRIPTION("Q6 Audio Frontend clock driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/qcom/qdsp6/q6afe-clocks.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2020, Linaro Limited
#include <dt-bindings/soc/qcom,gpr.h>
#include <linux/delay.h>
#include <linux/jiffies.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/soc/qcom/apr.h>
#include <linux/wait.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/pcm.h>
#include "audioreach.h"
#include "q6apm.h"
/* Graph Management */
struct apm_graph_mgmt_cmd {
struct apm_module_param_data param_data;
uint32_t num_sub_graphs;
uint32_t sub_graph_id_list[];
} __packed;
#define APM_GRAPH_MGMT_PSIZE(p, n) ALIGN(struct_size(p, sub_graph_id_list, n), 8)
static struct q6apm *g_apm;
int q6apm_send_cmd_sync(struct q6apm *apm, struct gpr_pkt *pkt, uint32_t rsp_opcode)
{
gpr_device_t *gdev = apm->gdev;
return audioreach_send_cmd_sync(&gdev->dev, gdev, &apm->result, &apm->lock,
NULL, &apm->wait, pkt, rsp_opcode);
}
static struct audioreach_graph *q6apm_get_audioreach_graph(struct q6apm *apm, uint32_t graph_id)
{
struct audioreach_graph_info *info;
struct audioreach_graph *graph;
int id;
mutex_lock(&apm->lock);
graph = idr_find(&apm->graph_idr, graph_id);
mutex_unlock(&apm->lock);
if (graph) {
kref_get(&graph->refcount);
return graph;
}
info = idr_find(&apm->graph_info_idr, graph_id);
if (!info)
return ERR_PTR(-ENODEV);
graph = kzalloc(sizeof(*graph), GFP_KERNEL);
if (!graph)
return ERR_PTR(-ENOMEM);
graph->apm = apm;
graph->info = info;
graph->id = graph_id;
graph->graph = audioreach_alloc_graph_pkt(apm, info);
if (IS_ERR(graph->graph)) {
void *err = graph->graph;
kfree(graph);
return ERR_CAST(err);
}
mutex_lock(&apm->lock);
id = idr_alloc(&apm->graph_idr, graph, graph_id, graph_id + 1, GFP_KERNEL);
if (id < 0) {
dev_err(apm->dev, "Unable to allocate graph id (%d)\n", graph_id);
kfree(graph->graph);
kfree(graph);
mutex_unlock(&apm->lock);
return ERR_PTR(id);
}
mutex_unlock(&apm->lock);
kref_init(&graph->refcount);
q6apm_send_cmd_sync(apm, graph->graph, 0);
return graph;
}
static int audioreach_graph_mgmt_cmd(struct audioreach_graph *graph, uint32_t opcode)
{
struct audioreach_graph_info *info = graph->info;
int num_sub_graphs = info->num_sub_graphs;
struct apm_module_param_data *param_data;
struct apm_graph_mgmt_cmd *mgmt_cmd;
struct audioreach_sub_graph *sg;
struct q6apm *apm = graph->apm;
int i = 0, rc, payload_size;
struct gpr_pkt *pkt;
payload_size = APM_GRAPH_MGMT_PSIZE(mgmt_cmd, num_sub_graphs);
pkt = audioreach_alloc_apm_cmd_pkt(payload_size, opcode, 0);
if (IS_ERR(pkt))
return PTR_ERR(pkt);
mgmt_cmd = (void *)pkt + GPR_HDR_SIZE + APM_CMD_HDR_SIZE;
mgmt_cmd->num_sub_graphs = num_sub_graphs;
param_data = &mgmt_cmd->param_data;
param_data->module_instance_id = APM_MODULE_INSTANCE_ID;
param_data->param_id = APM_PARAM_ID_SUB_GRAPH_LIST;
param_data->param_size = payload_size - APM_MODULE_PARAM_DATA_SIZE;
list_for_each_entry(sg, &info->sg_list, node)
mgmt_cmd->sub_graph_id_list[i++] = sg->sub_graph_id;
rc = q6apm_send_cmd_sync(apm, pkt, 0);
kfree(pkt);
return rc;
}
static void q6apm_put_audioreach_graph(struct kref *ref)
{
struct audioreach_graph *graph;
struct q6apm *apm;
graph = container_of(ref, struct audioreach_graph, refcount);
apm = graph->apm;
audioreach_graph_mgmt_cmd(graph, APM_CMD_GRAPH_CLOSE);
mutex_lock(&apm->lock);
graph = idr_remove(&apm->graph_idr, graph->id);
mutex_unlock(&apm->lock);
kfree(graph->graph);
kfree(graph);
}
static int q6apm_get_apm_state(struct q6apm *apm)
{
struct gpr_pkt *pkt;
pkt = audioreach_alloc_apm_cmd_pkt(0, APM_CMD_GET_SPF_STATE, 0);
if (IS_ERR(pkt))
return PTR_ERR(pkt);
q6apm_send_cmd_sync(apm, pkt, APM_CMD_RSP_GET_SPF_STATE);
kfree(pkt);
return apm->state;
}
bool q6apm_is_adsp_ready(void)
{
if (g_apm)
return q6apm_get_apm_state(g_apm);
return false;
}
EXPORT_SYMBOL_GPL(q6apm_is_adsp_ready);
static struct audioreach_module *__q6apm_find_module_by_mid(struct q6apm *apm,
struct audioreach_graph_info *info,
uint32_t mid)
{
struct audioreach_container *container;
struct audioreach_sub_graph *sgs;
struct audioreach_module *module;
list_for_each_entry(sgs, &info->sg_list, node) {
list_for_each_entry(container, &sgs->container_list, node) {
list_for_each_entry(module, &container->modules_list, node) {
if (mid == module->module_id)
return module;
}
}
}
return NULL;
}
int q6apm_graph_media_format_shmem(struct q6apm_graph *graph,
struct audioreach_module_config *cfg)
{
struct audioreach_module *module;
if (cfg->direction == SNDRV_PCM_STREAM_CAPTURE)
module = q6apm_find_module_by_mid(graph, MODULE_ID_RD_SHARED_MEM_EP);
else
module = q6apm_find_module_by_mid(graph, MODULE_ID_WR_SHARED_MEM_EP);
if (!module)
return -ENODEV;
audioreach_set_media_format(graph, module, cfg);
return 0;
}
EXPORT_SYMBOL_GPL(q6apm_graph_media_format_shmem);
int q6apm_map_memory_regions(struct q6apm_graph *graph, unsigned int dir, phys_addr_t phys,
size_t period_sz, unsigned int periods)
{
struct audioreach_graph_data *data;
struct audio_buffer *buf;
int cnt;
int rc;
if (dir == SNDRV_PCM_STREAM_PLAYBACK)
data = &graph->rx_data;
else
data = &graph->tx_data;
mutex_lock(&graph->lock);
if (data->buf) {
mutex_unlock(&graph->lock);
return 0;
}
buf = kzalloc(((sizeof(struct audio_buffer)) * periods), GFP_KERNEL);
if (!buf) {
mutex_unlock(&graph->lock);
return -ENOMEM;
}
if (dir == SNDRV_PCM_STREAM_PLAYBACK)
data = &graph->rx_data;
else
data = &graph->tx_data;
data->buf = buf;
buf[0].phys = phys;
buf[0].size = period_sz;
for (cnt = 1; cnt < periods; cnt++) {
if (period_sz > 0) {
buf[cnt].phys = buf[0].phys + (cnt * period_sz);
buf[cnt].size = period_sz;
}
}
data->num_periods = periods;
mutex_unlock(&graph->lock);
rc = audioreach_map_memory_regions(graph, dir, period_sz, periods, 1);
if (rc < 0) {
dev_err(graph->dev, "Memory_map_regions failed\n");
audioreach_graph_free_buf(graph);
}
return rc;
}
EXPORT_SYMBOL_GPL(q6apm_map_memory_regions);
int q6apm_unmap_memory_regions(struct q6apm_graph *graph, unsigned int dir)
{
struct apm_cmd_shared_mem_unmap_regions *cmd;
struct audioreach_graph_data *data;
struct gpr_pkt *pkt;
int rc;
if (dir == SNDRV_PCM_STREAM_PLAYBACK)
data = &graph->rx_data;
else
data = &graph->tx_data;
if (!data->mem_map_handle)
return 0;
pkt = audioreach_alloc_apm_pkt(sizeof(*cmd), APM_CMD_SHARED_MEM_UNMAP_REGIONS, dir,
graph->port->id);
if (IS_ERR(pkt))
return PTR_ERR(pkt);
cmd = (void *)pkt + GPR_HDR_SIZE;
cmd->mem_map_handle = data->mem_map_handle;
rc = audioreach_graph_send_cmd_sync(graph, pkt, APM_CMD_SHARED_MEM_UNMAP_REGIONS);
kfree(pkt);
audioreach_graph_free_buf(graph);
return rc;
}
EXPORT_SYMBOL_GPL(q6apm_unmap_memory_regions);
int q6apm_remove_initial_silence(struct device *dev, struct q6apm_graph *graph, uint32_t samples)
{
struct audioreach_module *module;
module = q6apm_find_module_by_mid(graph, MODULE_ID_PLACEHOLDER_DECODER);
if (!module)
return -ENODEV;
return audioreach_send_u32_param(graph, module, PARAM_ID_REMOVE_INITIAL_SILENCE, samples);
}
EXPORT_SYMBOL_GPL(q6apm_remove_initial_silence);
int q6apm_remove_trailing_silence(struct device *dev, struct q6apm_graph *graph, uint32_t samples)
{
struct audioreach_module *module;
module = q6apm_find_module_by_mid(graph, MODULE_ID_PLACEHOLDER_DECODER);
if (!module)
return -ENODEV;
return audioreach_send_u32_param(graph, module, PARAM_ID_REMOVE_TRAILING_SILENCE, samples);
}
EXPORT_SYMBOL_GPL(q6apm_remove_trailing_silence);
int q6apm_enable_compress_module(struct device *dev, struct q6apm_graph *graph, bool en)
{
struct audioreach_module *module;
module = q6apm_find_module_by_mid(graph, MODULE_ID_PLACEHOLDER_DECODER);
if (!module)
return -ENODEV;
return audioreach_send_u32_param(graph, module, PARAM_ID_MODULE_ENABLE, en);
}
EXPORT_SYMBOL_GPL(q6apm_enable_compress_module);
int q6apm_set_real_module_id(struct device *dev, struct q6apm_graph *graph,
uint32_t codec_id)
{
struct audioreach_module *module;
uint32_t module_id;
module = q6apm_find_module_by_mid(graph, MODULE_ID_PLACEHOLDER_DECODER);
if (!module)
return -ENODEV;
switch (codec_id) {
case SND_AUDIOCODEC_MP3:
module_id = MODULE_ID_MP3_DECODE;
break;
case SND_AUDIOCODEC_AAC:
module_id = MODULE_ID_AAC_DEC;
break;
case SND_AUDIOCODEC_FLAC:
module_id = MODULE_ID_FLAC_DEC;
break;
default:
return -EINVAL;
}
return audioreach_send_u32_param(graph, module, PARAM_ID_REAL_MODULE_ID,
module_id);
}
EXPORT_SYMBOL_GPL(q6apm_set_real_module_id);
int q6apm_graph_media_format_pcm(struct q6apm_graph *graph, struct audioreach_module_config *cfg)
{
struct audioreach_graph_info *info = graph->info;
struct audioreach_sub_graph *sgs;
struct audioreach_container *container;
struct audioreach_module *module;
list_for_each_entry(sgs, &info->sg_list, node) {
list_for_each_entry(container, &sgs->container_list, node) {
list_for_each_entry(module, &container->modules_list, node) {
if ((module->module_id == MODULE_ID_WR_SHARED_MEM_EP) ||
(module->module_id == MODULE_ID_RD_SHARED_MEM_EP))
continue;
audioreach_set_media_format(graph, module, cfg);
}
}
}
return 0;
}
EXPORT_SYMBOL_GPL(q6apm_graph_media_format_pcm);
static int q6apm_graph_get_tx_shmem_module_iid(struct q6apm_graph *graph)
{
struct audioreach_module *module;
module = q6apm_find_module_by_mid(graph, MODULE_ID_RD_SHARED_MEM_EP);
if (!module)
return -ENODEV;
return module->instance_id;
}
int q6apm_graph_get_rx_shmem_module_iid(struct q6apm_graph *graph)
{
struct audioreach_module *module;
module = q6apm_find_module_by_mid(graph, MODULE_ID_WR_SHARED_MEM_EP);
if (!module)
return -ENODEV;
return module->instance_id;
}
EXPORT_SYMBOL_GPL(q6apm_graph_get_rx_shmem_module_iid);
int q6apm_write_async(struct q6apm_graph *graph, uint32_t len, uint32_t msw_ts,
uint32_t lsw_ts, uint32_t wflags)
{
struct apm_data_cmd_wr_sh_mem_ep_data_buffer_v2 *write_buffer;
struct audio_buffer *ab;
struct gpr_pkt *pkt;
int rc, iid;
iid = q6apm_graph_get_rx_shmem_module_iid(graph);
pkt = audioreach_alloc_pkt(sizeof(*write_buffer), DATA_CMD_WR_SH_MEM_EP_DATA_BUFFER_V2,
graph->rx_data.dsp_buf | (len << APM_WRITE_TOKEN_LEN_SHIFT),
graph->port->id, iid);
if (IS_ERR(pkt))
return PTR_ERR(pkt);
write_buffer = (void *)pkt + GPR_HDR_SIZE;
mutex_lock(&graph->lock);
ab = &graph->rx_data.buf[graph->rx_data.dsp_buf];
write_buffer->buf_addr_lsw = lower_32_bits(ab->phys);
write_buffer->buf_addr_msw = upper_32_bits(ab->phys);
write_buffer->buf_size = len;
write_buffer->timestamp_lsw = lsw_ts;
write_buffer->timestamp_msw = msw_ts;
write_buffer->mem_map_handle = graph->rx_data.mem_map_handle;
write_buffer->flags = wflags;
graph->rx_data.dsp_buf++;
if (graph->rx_data.dsp_buf >= graph->rx_data.num_periods)
graph->rx_data.dsp_buf = 0;
mutex_unlock(&graph->lock);
rc = gpr_send_port_pkt(graph->port, pkt);
kfree(pkt);
return rc;
}
EXPORT_SYMBOL_GPL(q6apm_write_async);
int q6apm_read(struct q6apm_graph *graph)
{
struct data_cmd_rd_sh_mem_ep_data_buffer_v2 *read_buffer;
struct audioreach_graph_data *port;
struct audio_buffer *ab;
struct gpr_pkt *pkt;
int rc, iid;
iid = q6apm_graph_get_tx_shmem_module_iid(graph);
pkt = audioreach_alloc_pkt(sizeof(*read_buffer), DATA_CMD_RD_SH_MEM_EP_DATA_BUFFER_V2,
graph->tx_data.dsp_buf, graph->port->id, iid);
if (IS_ERR(pkt))
return PTR_ERR(pkt);
read_buffer = (void *)pkt + GPR_HDR_SIZE;
mutex_lock(&graph->lock);
port = &graph->tx_data;
ab = &port->buf[port->dsp_buf];
read_buffer->buf_addr_lsw = lower_32_bits(ab->phys);
read_buffer->buf_addr_msw = upper_32_bits(ab->phys);
read_buffer->mem_map_handle = port->mem_map_handle;
read_buffer->buf_size = ab->size;
port->dsp_buf++;
if (port->dsp_buf >= port->num_periods)
port->dsp_buf = 0;
mutex_unlock(&graph->lock);
rc = gpr_send_port_pkt(graph->port, pkt);
kfree(pkt);
return rc;
}
EXPORT_SYMBOL_GPL(q6apm_read);
static int graph_callback(struct gpr_resp_pkt *data, void *priv, int op)
{
struct data_cmd_rsp_rd_sh_mem_ep_data_buffer_done_v2 *rd_done;
struct data_cmd_rsp_wr_sh_mem_ep_data_buffer_done_v2 *done;
struct apm_cmd_rsp_shared_mem_map_regions *rsp;
struct gpr_ibasic_rsp_result_t *result;
struct q6apm_graph *graph = priv;
struct gpr_hdr *hdr = &data->hdr;
struct device *dev = graph->dev;
uint32_t client_event;
phys_addr_t phys;
int token;
result = data->payload;
switch (hdr->opcode) {
case DATA_CMD_RSP_WR_SH_MEM_EP_DATA_BUFFER_DONE_V2:
if (!graph->ar_graph)
break;
client_event = APM_CLIENT_EVENT_DATA_WRITE_DONE;
mutex_lock(&graph->lock);
token = hdr->token & APM_WRITE_TOKEN_MASK;
done = data->payload;
phys = graph->rx_data.buf[token].phys;
mutex_unlock(&graph->lock);
if (lower_32_bits(phys) == done->buf_addr_lsw &&
upper_32_bits(phys) == done->buf_addr_msw) {
graph->result.opcode = hdr->opcode;
graph->result.status = done->status;
if (graph->cb)
graph->cb(client_event, hdr->token, data->payload, graph->priv);
} else {
dev_err(dev, "WR BUFF Unexpected addr %08x-%08x\n", done->buf_addr_lsw,
done->buf_addr_msw);
}
break;
case APM_CMD_RSP_SHARED_MEM_MAP_REGIONS:
graph->result.opcode = hdr->opcode;
graph->result.status = 0;
rsp = data->payload;
if (hdr->token == SNDRV_PCM_STREAM_PLAYBACK)
graph->rx_data.mem_map_handle = rsp->mem_map_handle;
else
graph->tx_data.mem_map_handle = rsp->mem_map_handle;
wake_up(&graph->cmd_wait);
break;
case DATA_CMD_RSP_RD_SH_MEM_EP_DATA_BUFFER_V2:
if (!graph->ar_graph)
break;
client_event = APM_CLIENT_EVENT_DATA_READ_DONE;
mutex_lock(&graph->lock);
rd_done = data->payload;
phys = graph->tx_data.buf[hdr->token].phys;
mutex_unlock(&graph->lock);
if (upper_32_bits(phys) == rd_done->buf_addr_msw &&
lower_32_bits(phys) == rd_done->buf_addr_lsw) {
graph->result.opcode = hdr->opcode;
graph->result.status = rd_done->status;
if (graph->cb)
graph->cb(client_event, hdr->token, data->payload, graph->priv);
} else {
dev_err(dev, "RD BUFF Unexpected addr %08x-%08x\n", rd_done->buf_addr_lsw,
rd_done->buf_addr_msw);
}
break;
case DATA_CMD_WR_SH_MEM_EP_EOS_RENDERED:
client_event = APM_CLIENT_EVENT_CMD_EOS_DONE;
if (graph->cb)
graph->cb(client_event, hdr->token, data->payload, graph->priv);
break;
case GPR_BASIC_RSP_RESULT:
switch (result->opcode) {
case APM_CMD_SHARED_MEM_UNMAP_REGIONS:
graph->result.opcode = result->opcode;
graph->result.status = 0;
if (hdr->token == SNDRV_PCM_STREAM_PLAYBACK)
graph->rx_data.mem_map_handle = 0;
else
graph->tx_data.mem_map_handle = 0;
wake_up(&graph->cmd_wait);
break;
case APM_CMD_SHARED_MEM_MAP_REGIONS:
case DATA_CMD_WR_SH_MEM_EP_MEDIA_FORMAT:
case APM_CMD_SET_CFG:
graph->result.opcode = result->opcode;
graph->result.status = result->status;
if (result->status)
dev_err(dev, "Error (%d) Processing 0x%08x cmd\n",
result->status, result->opcode);
wake_up(&graph->cmd_wait);
break;
default:
break;
}
break;
default:
break;
}
return 0;
}
struct q6apm_graph *q6apm_graph_open(struct device *dev, q6apm_cb cb,
void *priv, int graph_id)
{
struct q6apm *apm = dev_get_drvdata(dev->parent);
struct audioreach_graph *ar_graph;
struct q6apm_graph *graph;
int ret;
ar_graph = q6apm_get_audioreach_graph(apm, graph_id);
if (IS_ERR(ar_graph)) {
dev_err(dev, "No graph found with id %d\n", graph_id);
return ERR_CAST(ar_graph);
}
graph = kzalloc(sizeof(*graph), GFP_KERNEL);
if (!graph) {
ret = -ENOMEM;
goto put_ar_graph;
}
graph->apm = apm;
graph->priv = priv;
graph->cb = cb;
graph->info = ar_graph->info;
graph->ar_graph = ar_graph;
graph->id = ar_graph->id;
graph->dev = dev;
mutex_init(&graph->lock);
init_waitqueue_head(&graph->cmd_wait);
graph->port = gpr_alloc_port(apm->gdev, dev, graph_callback, graph);
if (IS_ERR(graph->port)) {
ret = PTR_ERR(graph->port);
goto free_graph;
}
return graph;
free_graph:
kfree(graph);
put_ar_graph:
kref_put(&ar_graph->refcount, q6apm_put_audioreach_graph);
return ERR_PTR(ret);
}
EXPORT_SYMBOL_GPL(q6apm_graph_open);
int q6apm_graph_close(struct q6apm_graph *graph)
{
struct audioreach_graph *ar_graph = graph->ar_graph;
graph->ar_graph = NULL;
kref_put(&ar_graph->refcount, q6apm_put_audioreach_graph);
gpr_free_port(graph->port);
kfree(graph);
return 0;
}
EXPORT_SYMBOL_GPL(q6apm_graph_close);
int q6apm_graph_prepare(struct q6apm_graph *graph)
{
return audioreach_graph_mgmt_cmd(graph->ar_graph, APM_CMD_GRAPH_PREPARE);
}
EXPORT_SYMBOL_GPL(q6apm_graph_prepare);
int q6apm_graph_start(struct q6apm_graph *graph)
{
struct audioreach_graph *ar_graph = graph->ar_graph;
int ret = 0;
if (ar_graph->start_count == 0)
ret = audioreach_graph_mgmt_cmd(ar_graph, APM_CMD_GRAPH_START);
ar_graph->start_count++;
return ret;
}
EXPORT_SYMBOL_GPL(q6apm_graph_start);
int q6apm_graph_stop(struct q6apm_graph *graph)
{
struct audioreach_graph *ar_graph = graph->ar_graph;
if (--ar_graph->start_count > 0)
return 0;
return audioreach_graph_mgmt_cmd(ar_graph, APM_CMD_GRAPH_STOP);
}
EXPORT_SYMBOL_GPL(q6apm_graph_stop);
int q6apm_graph_flush(struct q6apm_graph *graph)
{
return audioreach_graph_mgmt_cmd(graph->ar_graph, APM_CMD_GRAPH_FLUSH);
}
EXPORT_SYMBOL_GPL(q6apm_graph_flush);
static int q6apm_audio_probe(struct snd_soc_component *component)
{
return audioreach_tplg_init(component);
}
static void q6apm_audio_remove(struct snd_soc_component *component)
{
/* remove topology */
snd_soc_tplg_component_remove(component);
}
#define APM_AUDIO_DRV_NAME "q6apm-audio"
static const struct snd_soc_component_driver q6apm_audio_component = {
.name = APM_AUDIO_DRV_NAME,
.probe = q6apm_audio_probe,
.remove = q6apm_audio_remove,
};
static int apm_probe(gpr_device_t *gdev)
{
struct device *dev = &gdev->dev;
struct q6apm *apm;
int ret;
apm = devm_kzalloc(dev, sizeof(*apm), GFP_KERNEL);
if (!apm)
return -ENOMEM;
dev_set_drvdata(dev, apm);
mutex_init(&apm->lock);
apm->dev = dev;
apm->gdev = gdev;
init_waitqueue_head(&apm->wait);
INIT_LIST_HEAD(&apm->widget_list);
idr_init(&apm->graph_idr);
idr_init(&apm->graph_info_idr);
idr_init(&apm->sub_graphs_idr);
idr_init(&apm->containers_idr);
idr_init(&apm->modules_idr);
g_apm = apm;
q6apm_get_apm_state(apm);
ret = devm_snd_soc_register_component(dev, &q6apm_audio_component, NULL, 0);
if (ret < 0) {
dev_err(dev, "failed to register q6apm: %d\n", ret);
return ret;
}
return of_platform_populate(dev->of_node, NULL, NULL, dev);
}
struct audioreach_module *q6apm_find_module_by_mid(struct q6apm_graph *graph, uint32_t mid)
{
struct audioreach_graph_info *info = graph->info;
struct q6apm *apm = graph->apm;
return __q6apm_find_module_by_mid(apm, info, mid);
}
static int apm_callback(struct gpr_resp_pkt *data, void *priv, int op)
{
gpr_device_t *gdev = priv;
struct q6apm *apm = dev_get_drvdata(&gdev->dev);
struct device *dev = &gdev->dev;
struct gpr_ibasic_rsp_result_t *result;
struct gpr_hdr *hdr = &data->hdr;
result = data->payload;
switch (hdr->opcode) {
case APM_CMD_RSP_GET_SPF_STATE:
apm->result.opcode = hdr->opcode;
apm->result.status = 0;
/* First word of result it state */
apm->state = result->opcode;
wake_up(&apm->wait);
break;
case GPR_BASIC_RSP_RESULT:
switch (result->opcode) {
case APM_CMD_GRAPH_START:
case APM_CMD_GRAPH_OPEN:
case APM_CMD_GRAPH_PREPARE:
case APM_CMD_GRAPH_CLOSE:
case APM_CMD_GRAPH_FLUSH:
case APM_CMD_GRAPH_STOP:
case APM_CMD_SET_CFG:
apm->result.opcode = result->opcode;
apm->result.status = result->status;
if (result->status)
dev_err(dev, "Error (%d) Processing 0x%08x cmd\n", result->status,
result->opcode);
wake_up(&apm->wait);
break;
default:
break;
}
break;
default:
break;
}
return 0;
}
#ifdef CONFIG_OF
static const struct of_device_id apm_device_id[] = {
{ .compatible = "qcom,q6apm" },
{},
};
MODULE_DEVICE_TABLE(of, apm_device_id);
#endif
static gpr_driver_t apm_driver = {
.probe = apm_probe,
.gpr_callback = apm_callback,
.driver = {
.name = "qcom-apm",
.of_match_table = of_match_ptr(apm_device_id),
},
};
module_gpr_driver(apm_driver);
MODULE_DESCRIPTION("Audio Process Manager");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/qcom/qdsp6/q6apm.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2011-2017, The Linux Foundation. All rights reserved.
// Copyright (c) 2018, Linaro Limited
#include <linux/err.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <sound/pcm.h>
#include <sound/soc.h>
#include <sound/pcm_params.h>
#include "q6dsp-lpass-ports.h"
#include "q6dsp-common.h"
#include "q6afe.h"
struct q6afe_dai_priv_data {
uint32_t sd_line_mask;
uint32_t sync_mode;
uint32_t sync_src;
uint32_t data_out_enable;
uint32_t invert_sync;
uint32_t data_delay;
uint32_t data_align;
};
struct q6afe_dai_data {
struct q6afe_port *port[AFE_PORT_MAX];
struct q6afe_port_config port_config[AFE_PORT_MAX];
bool is_port_started[AFE_PORT_MAX];
struct q6afe_dai_priv_data priv[AFE_PORT_MAX];
};
static int q6slim_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct q6afe_dai_data *dai_data = dev_get_drvdata(dai->dev);
struct q6afe_slim_cfg *slim = &dai_data->port_config[dai->id].slim;
slim->sample_rate = params_rate(params);
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
case SNDRV_PCM_FORMAT_SPECIAL:
slim->bit_width = 16;
break;
case SNDRV_PCM_FORMAT_S24_LE:
slim->bit_width = 24;
break;
case SNDRV_PCM_FORMAT_S32_LE:
slim->bit_width = 32;
break;
default:
pr_err("%s: format %d\n",
__func__, params_format(params));
return -EINVAL;
}
return 0;
}
static int q6hdmi_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct q6afe_dai_data *dai_data = dev_get_drvdata(dai->dev);
int channels = params_channels(params);
struct q6afe_hdmi_cfg *hdmi = &dai_data->port_config[dai->id].hdmi;
int ret;
hdmi->sample_rate = params_rate(params);
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
hdmi->bit_width = 16;
break;
case SNDRV_PCM_FORMAT_S24_LE:
hdmi->bit_width = 24;
break;
}
ret = q6dsp_get_channel_allocation(channels);
if (ret < 0)
return ret;
hdmi->channel_allocation = (u16) ret;
return 0;
}
static int q6i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct q6afe_dai_data *dai_data = dev_get_drvdata(dai->dev);
struct q6afe_i2s_cfg *i2s = &dai_data->port_config[dai->id].i2s_cfg;
i2s->sample_rate = params_rate(params);
i2s->bit_width = params_width(params);
i2s->num_channels = params_channels(params);
i2s->sd_line_mask = dai_data->priv[dai->id].sd_line_mask;
return 0;
}
static int q6i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct q6afe_dai_data *dai_data = dev_get_drvdata(dai->dev);
struct q6afe_i2s_cfg *i2s = &dai_data->port_config[dai->id].i2s_cfg;
i2s->fmt = fmt;
return 0;
}
static int q6tdm_set_tdm_slot(struct snd_soc_dai *dai,
unsigned int tx_mask,
unsigned int rx_mask,
int slots, int slot_width)
{
struct q6afe_dai_data *dai_data = dev_get_drvdata(dai->dev);
struct q6afe_tdm_cfg *tdm = &dai_data->port_config[dai->id].tdm;
unsigned int cap_mask;
int rc = 0;
/* HW only supports 16 and 32 bit slot width configuration */
if ((slot_width != 16) && (slot_width != 32)) {
dev_err(dai->dev, "%s: invalid slot_width %d\n",
__func__, slot_width);
return -EINVAL;
}
/* HW supports 1-32 slots configuration. Typical: 1, 2, 4, 8, 16, 32 */
switch (slots) {
case 2:
cap_mask = 0x03;
break;
case 4:
cap_mask = 0x0F;
break;
case 8:
cap_mask = 0xFF;
break;
case 16:
cap_mask = 0xFFFF;
break;
default:
dev_err(dai->dev, "%s: invalid slots %d\n",
__func__, slots);
return -EINVAL;
}
switch (dai->id) {
case PRIMARY_TDM_RX_0 ... QUINARY_TDM_TX_7:
tdm->nslots_per_frame = slots;
tdm->slot_width = slot_width;
/* TDM RX dais ids are even and tx are odd */
tdm->slot_mask = ((dai->id & 0x1) ? tx_mask : rx_mask) & cap_mask;
break;
default:
dev_err(dai->dev, "%s: invalid dai id 0x%x\n",
__func__, dai->id);
return -EINVAL;
}
return rc;
}
static int q6tdm_set_channel_map(struct snd_soc_dai *dai,
unsigned int tx_num, unsigned int *tx_slot,
unsigned int rx_num, unsigned int *rx_slot)
{
struct q6afe_dai_data *dai_data = dev_get_drvdata(dai->dev);
struct q6afe_tdm_cfg *tdm = &dai_data->port_config[dai->id].tdm;
int rc = 0;
int i = 0;
switch (dai->id) {
case PRIMARY_TDM_RX_0 ... QUINARY_TDM_TX_7:
if (dai->id & 0x1) {
if (!tx_slot) {
dev_err(dai->dev, "tx slot not found\n");
return -EINVAL;
}
if (tx_num > AFE_PORT_MAX_AUDIO_CHAN_CNT) {
dev_err(dai->dev, "invalid tx num %d\n",
tx_num);
return -EINVAL;
}
for (i = 0; i < tx_num; i++)
tdm->ch_mapping[i] = tx_slot[i];
for (i = tx_num; i < AFE_PORT_MAX_AUDIO_CHAN_CNT; i++)
tdm->ch_mapping[i] = Q6AFE_CMAP_INVALID;
tdm->num_channels = tx_num;
} else {
/* rx */
if (!rx_slot) {
dev_err(dai->dev, "rx slot not found\n");
return -EINVAL;
}
if (rx_num > AFE_PORT_MAX_AUDIO_CHAN_CNT) {
dev_err(dai->dev, "invalid rx num %d\n",
rx_num);
return -EINVAL;
}
for (i = 0; i < rx_num; i++)
tdm->ch_mapping[i] = rx_slot[i];
for (i = rx_num; i < AFE_PORT_MAX_AUDIO_CHAN_CNT; i++)
tdm->ch_mapping[i] = Q6AFE_CMAP_INVALID;
tdm->num_channels = rx_num;
}
break;
default:
dev_err(dai->dev, "%s: invalid dai id 0x%x\n",
__func__, dai->id);
return -EINVAL;
}
return rc;
}
static int q6tdm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct q6afe_dai_data *dai_data = dev_get_drvdata(dai->dev);
struct q6afe_tdm_cfg *tdm = &dai_data->port_config[dai->id].tdm;
tdm->bit_width = params_width(params);
tdm->sample_rate = params_rate(params);
tdm->num_channels = params_channels(params);
tdm->data_align_type = dai_data->priv[dai->id].data_align;
tdm->sync_src = dai_data->priv[dai->id].sync_src;
tdm->sync_mode = dai_data->priv[dai->id].sync_mode;
return 0;
}
static int q6dma_set_channel_map(struct snd_soc_dai *dai,
unsigned int tx_num, unsigned int *tx_ch_mask,
unsigned int rx_num, unsigned int *rx_ch_mask)
{
struct q6afe_dai_data *dai_data = dev_get_drvdata(dai->dev);
struct q6afe_cdc_dma_cfg *cfg = &dai_data->port_config[dai->id].dma_cfg;
int ch_mask;
int rc = 0;
switch (dai->id) {
case WSA_CODEC_DMA_TX_0:
case WSA_CODEC_DMA_TX_1:
case WSA_CODEC_DMA_TX_2:
case VA_CODEC_DMA_TX_0:
case VA_CODEC_DMA_TX_1:
case VA_CODEC_DMA_TX_2:
case TX_CODEC_DMA_TX_0:
case TX_CODEC_DMA_TX_1:
case TX_CODEC_DMA_TX_2:
case TX_CODEC_DMA_TX_3:
case TX_CODEC_DMA_TX_4:
case TX_CODEC_DMA_TX_5:
if (!tx_ch_mask) {
dev_err(dai->dev, "tx slot not found\n");
return -EINVAL;
}
if (tx_num > AFE_PORT_MAX_AUDIO_CHAN_CNT) {
dev_err(dai->dev, "invalid tx num %d\n",
tx_num);
return -EINVAL;
}
ch_mask = *tx_ch_mask;
break;
case WSA_CODEC_DMA_RX_0:
case WSA_CODEC_DMA_RX_1:
case RX_CODEC_DMA_RX_0:
case RX_CODEC_DMA_RX_1:
case RX_CODEC_DMA_RX_2:
case RX_CODEC_DMA_RX_3:
case RX_CODEC_DMA_RX_4:
case RX_CODEC_DMA_RX_5:
case RX_CODEC_DMA_RX_6:
case RX_CODEC_DMA_RX_7:
/* rx */
if (!rx_ch_mask) {
dev_err(dai->dev, "rx slot not found\n");
return -EINVAL;
}
if (rx_num > AFE_PORT_MAX_AUDIO_CHAN_CNT) {
dev_err(dai->dev, "invalid rx num %d\n",
rx_num);
return -EINVAL;
}
ch_mask = *rx_ch_mask;
break;
default:
dev_err(dai->dev, "%s: invalid dai id 0x%x\n",
__func__, dai->id);
return -EINVAL;
}
cfg->active_channels_mask = ch_mask;
return rc;
}
static int q6dma_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct q6afe_dai_data *dai_data = dev_get_drvdata(dai->dev);
struct q6afe_cdc_dma_cfg *cfg = &dai_data->port_config[dai->id].dma_cfg;
cfg->bit_width = params_width(params);
cfg->sample_rate = params_rate(params);
cfg->num_channels = params_channels(params);
return 0;
}
static void q6afe_dai_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct q6afe_dai_data *dai_data = dev_get_drvdata(dai->dev);
int rc;
if (!dai_data->is_port_started[dai->id])
return;
rc = q6afe_port_stop(dai_data->port[dai->id]);
if (rc < 0)
dev_err(dai->dev, "fail to close AFE port (%d)\n", rc);
dai_data->is_port_started[dai->id] = false;
}
static int q6afe_dai_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct q6afe_dai_data *dai_data = dev_get_drvdata(dai->dev);
int rc;
if (dai_data->is_port_started[dai->id]) {
/* stop the port and restart with new port config */
rc = q6afe_port_stop(dai_data->port[dai->id]);
if (rc < 0) {
dev_err(dai->dev, "fail to close AFE port (%d)\n", rc);
return rc;
}
}
switch (dai->id) {
case HDMI_RX:
case DISPLAY_PORT_RX:
q6afe_hdmi_port_prepare(dai_data->port[dai->id],
&dai_data->port_config[dai->id].hdmi);
break;
case SLIMBUS_0_RX ... SLIMBUS_6_TX:
q6afe_slim_port_prepare(dai_data->port[dai->id],
&dai_data->port_config[dai->id].slim);
break;
case QUINARY_MI2S_RX ... QUINARY_MI2S_TX:
case PRIMARY_MI2S_RX ... QUATERNARY_MI2S_TX:
rc = q6afe_i2s_port_prepare(dai_data->port[dai->id],
&dai_data->port_config[dai->id].i2s_cfg);
if (rc < 0) {
dev_err(dai->dev, "fail to prepare AFE port %x\n",
dai->id);
return rc;
}
break;
case PRIMARY_TDM_RX_0 ... QUINARY_TDM_TX_7:
q6afe_tdm_port_prepare(dai_data->port[dai->id],
&dai_data->port_config[dai->id].tdm);
break;
case WSA_CODEC_DMA_RX_0 ... RX_CODEC_DMA_RX_7:
q6afe_cdc_dma_port_prepare(dai_data->port[dai->id],
&dai_data->port_config[dai->id].dma_cfg);
break;
default:
return -EINVAL;
}
rc = q6afe_port_start(dai_data->port[dai->id]);
if (rc < 0) {
dev_err(dai->dev, "fail to start AFE port %x\n", dai->id);
return rc;
}
dai_data->is_port_started[dai->id] = true;
return 0;
}
static int q6slim_set_channel_map(struct snd_soc_dai *dai,
unsigned int tx_num, unsigned int *tx_slot,
unsigned int rx_num, unsigned int *rx_slot)
{
struct q6afe_dai_data *dai_data = dev_get_drvdata(dai->dev);
struct q6afe_port_config *pcfg = &dai_data->port_config[dai->id];
int i;
if (dai->id & 0x1) {
/* TX */
if (!tx_slot) {
pr_err("%s: tx slot not found\n", __func__);
return -EINVAL;
}
for (i = 0; i < tx_num; i++)
pcfg->slim.ch_mapping[i] = tx_slot[i];
pcfg->slim.num_channels = tx_num;
} else {
if (!rx_slot) {
pr_err("%s: rx slot not found\n", __func__);
return -EINVAL;
}
for (i = 0; i < rx_num; i++)
pcfg->slim.ch_mapping[i] = rx_slot[i];
pcfg->slim.num_channels = rx_num;
}
return 0;
}
static int q6afe_mi2s_set_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct q6afe_dai_data *dai_data = dev_get_drvdata(dai->dev);
struct q6afe_port *port = dai_data->port[dai->id];
switch (clk_id) {
case LPAIF_DIG_CLK:
return q6afe_port_set_sysclk(port, clk_id, 0, 5, freq, dir);
case LPAIF_BIT_CLK:
case LPAIF_OSR_CLK:
return q6afe_port_set_sysclk(port, clk_id,
Q6AFE_LPASS_CLK_SRC_INTERNAL,
Q6AFE_LPASS_CLK_ROOT_DEFAULT,
freq, dir);
case Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT ... Q6AFE_LPASS_CLK_ID_QUI_MI2S_OSR:
case Q6AFE_LPASS_CLK_ID_MCLK_1 ... Q6AFE_LPASS_CLK_ID_INT_MCLK_1:
case Q6AFE_LPASS_CLK_ID_WSA_CORE_MCLK ... Q6AFE_LPASS_CLK_ID_VA_CORE_2X_MCLK:
return q6afe_port_set_sysclk(port, clk_id,
Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
Q6AFE_LPASS_CLK_ROOT_DEFAULT,
freq, dir);
case Q6AFE_LPASS_CLK_ID_PRI_TDM_IBIT ... Q6AFE_LPASS_CLK_ID_QUIN_TDM_EBIT:
return q6afe_port_set_sysclk(port, clk_id,
Q6AFE_LPASS_CLK_ATTRIBUTE_INVERT_COUPLE_NO,
Q6AFE_LPASS_CLK_ROOT_DEFAULT,
freq, dir);
}
return 0;
}
static const struct snd_soc_dapm_route q6afe_dapm_routes[] = {
{"HDMI Playback", NULL, "HDMI_RX"},
{"DISPLAY_PORT_RX_0 Playback", NULL, "DISPLAY_PORT_RX"},
{"Slimbus Playback", NULL, "SLIMBUS_0_RX"},
{"Slimbus1 Playback", NULL, "SLIMBUS_1_RX"},
{"Slimbus2 Playback", NULL, "SLIMBUS_2_RX"},
{"Slimbus3 Playback", NULL, "SLIMBUS_3_RX"},
{"Slimbus4 Playback", NULL, "SLIMBUS_4_RX"},
{"Slimbus5 Playback", NULL, "SLIMBUS_5_RX"},
{"Slimbus6 Playback", NULL, "SLIMBUS_6_RX"},
{"SLIMBUS_0_TX", NULL, "Slimbus Capture"},
{"SLIMBUS_1_TX", NULL, "Slimbus1 Capture"},
{"SLIMBUS_2_TX", NULL, "Slimbus2 Capture"},
{"SLIMBUS_3_TX", NULL, "Slimbus3 Capture"},
{"SLIMBUS_4_TX", NULL, "Slimbus4 Capture"},
{"SLIMBUS_5_TX", NULL, "Slimbus5 Capture"},
{"SLIMBUS_6_TX", NULL, "Slimbus6 Capture"},
{"Primary MI2S Playback", NULL, "PRI_MI2S_RX"},
{"Secondary MI2S Playback", NULL, "SEC_MI2S_RX"},
{"Tertiary MI2S Playback", NULL, "TERT_MI2S_RX"},
{"Quaternary MI2S Playback", NULL, "QUAT_MI2S_RX"},
{"Quinary MI2S Playback", NULL, "QUIN_MI2S_RX"},
{"Primary TDM0 Playback", NULL, "PRIMARY_TDM_RX_0"},
{"Primary TDM1 Playback", NULL, "PRIMARY_TDM_RX_1"},
{"Primary TDM2 Playback", NULL, "PRIMARY_TDM_RX_2"},
{"Primary TDM3 Playback", NULL, "PRIMARY_TDM_RX_3"},
{"Primary TDM4 Playback", NULL, "PRIMARY_TDM_RX_4"},
{"Primary TDM5 Playback", NULL, "PRIMARY_TDM_RX_5"},
{"Primary TDM6 Playback", NULL, "PRIMARY_TDM_RX_6"},
{"Primary TDM7 Playback", NULL, "PRIMARY_TDM_RX_7"},
{"Secondary TDM0 Playback", NULL, "SEC_TDM_RX_0"},
{"Secondary TDM1 Playback", NULL, "SEC_TDM_RX_1"},
{"Secondary TDM2 Playback", NULL, "SEC_TDM_RX_2"},
{"Secondary TDM3 Playback", NULL, "SEC_TDM_RX_3"},
{"Secondary TDM4 Playback", NULL, "SEC_TDM_RX_4"},
{"Secondary TDM5 Playback", NULL, "SEC_TDM_RX_5"},
{"Secondary TDM6 Playback", NULL, "SEC_TDM_RX_6"},
{"Secondary TDM7 Playback", NULL, "SEC_TDM_RX_7"},
{"Tertiary TDM0 Playback", NULL, "TERT_TDM_RX_0"},
{"Tertiary TDM1 Playback", NULL, "TERT_TDM_RX_1"},
{"Tertiary TDM2 Playback", NULL, "TERT_TDM_RX_2"},
{"Tertiary TDM3 Playback", NULL, "TERT_TDM_RX_3"},
{"Tertiary TDM4 Playback", NULL, "TERT_TDM_RX_4"},
{"Tertiary TDM5 Playback", NULL, "TERT_TDM_RX_5"},
{"Tertiary TDM6 Playback", NULL, "TERT_TDM_RX_6"},
{"Tertiary TDM7 Playback", NULL, "TERT_TDM_RX_7"},
{"Quaternary TDM0 Playback", NULL, "QUAT_TDM_RX_0"},
{"Quaternary TDM1 Playback", NULL, "QUAT_TDM_RX_1"},
{"Quaternary TDM2 Playback", NULL, "QUAT_TDM_RX_2"},
{"Quaternary TDM3 Playback", NULL, "QUAT_TDM_RX_3"},
{"Quaternary TDM4 Playback", NULL, "QUAT_TDM_RX_4"},
{"Quaternary TDM5 Playback", NULL, "QUAT_TDM_RX_5"},
{"Quaternary TDM6 Playback", NULL, "QUAT_TDM_RX_6"},
{"Quaternary TDM7 Playback", NULL, "QUAT_TDM_RX_7"},
{"Quinary TDM0 Playback", NULL, "QUIN_TDM_RX_0"},
{"Quinary TDM1 Playback", NULL, "QUIN_TDM_RX_1"},
{"Quinary TDM2 Playback", NULL, "QUIN_TDM_RX_2"},
{"Quinary TDM3 Playback", NULL, "QUIN_TDM_RX_3"},
{"Quinary TDM4 Playback", NULL, "QUIN_TDM_RX_4"},
{"Quinary TDM5 Playback", NULL, "QUIN_TDM_RX_5"},
{"Quinary TDM6 Playback", NULL, "QUIN_TDM_RX_6"},
{"Quinary TDM7 Playback", NULL, "QUIN_TDM_RX_7"},
{"PRIMARY_TDM_TX_0", NULL, "Primary TDM0 Capture"},
{"PRIMARY_TDM_TX_1", NULL, "Primary TDM1 Capture"},
{"PRIMARY_TDM_TX_2", NULL, "Primary TDM2 Capture"},
{"PRIMARY_TDM_TX_3", NULL, "Primary TDM3 Capture"},
{"PRIMARY_TDM_TX_4", NULL, "Primary TDM4 Capture"},
{"PRIMARY_TDM_TX_5", NULL, "Primary TDM5 Capture"},
{"PRIMARY_TDM_TX_6", NULL, "Primary TDM6 Capture"},
{"PRIMARY_TDM_TX_7", NULL, "Primary TDM7 Capture"},
{"SEC_TDM_TX_0", NULL, "Secondary TDM0 Capture"},
{"SEC_TDM_TX_1", NULL, "Secondary TDM1 Capture"},
{"SEC_TDM_TX_2", NULL, "Secondary TDM2 Capture"},
{"SEC_TDM_TX_3", NULL, "Secondary TDM3 Capture"},
{"SEC_TDM_TX_4", NULL, "Secondary TDM4 Capture"},
{"SEC_TDM_TX_5", NULL, "Secondary TDM5 Capture"},
{"SEC_TDM_TX_6", NULL, "Secondary TDM6 Capture"},
{"SEC_TDM_TX_7", NULL, "Secondary TDM7 Capture"},
{"TERT_TDM_TX_0", NULL, "Tertiary TDM0 Capture"},
{"TERT_TDM_TX_1", NULL, "Tertiary TDM1 Capture"},
{"TERT_TDM_TX_2", NULL, "Tertiary TDM2 Capture"},
{"TERT_TDM_TX_3", NULL, "Tertiary TDM3 Capture"},
{"TERT_TDM_TX_4", NULL, "Tertiary TDM4 Capture"},
{"TERT_TDM_TX_5", NULL, "Tertiary TDM5 Capture"},
{"TERT_TDM_TX_6", NULL, "Tertiary TDM6 Capture"},
{"TERT_TDM_TX_7", NULL, "Tertiary TDM7 Capture"},
{"QUAT_TDM_TX_0", NULL, "Quaternary TDM0 Capture"},
{"QUAT_TDM_TX_1", NULL, "Quaternary TDM1 Capture"},
{"QUAT_TDM_TX_2", NULL, "Quaternary TDM2 Capture"},
{"QUAT_TDM_TX_3", NULL, "Quaternary TDM3 Capture"},
{"QUAT_TDM_TX_4", NULL, "Quaternary TDM4 Capture"},
{"QUAT_TDM_TX_5", NULL, "Quaternary TDM5 Capture"},
{"QUAT_TDM_TX_6", NULL, "Quaternary TDM6 Capture"},
{"QUAT_TDM_TX_7", NULL, "Quaternary TDM7 Capture"},
{"QUIN_TDM_TX_0", NULL, "Quinary TDM0 Capture"},
{"QUIN_TDM_TX_1", NULL, "Quinary TDM1 Capture"},
{"QUIN_TDM_TX_2", NULL, "Quinary TDM2 Capture"},
{"QUIN_TDM_TX_3", NULL, "Quinary TDM3 Capture"},
{"QUIN_TDM_TX_4", NULL, "Quinary TDM4 Capture"},
{"QUIN_TDM_TX_5", NULL, "Quinary TDM5 Capture"},
{"QUIN_TDM_TX_6", NULL, "Quinary TDM6 Capture"},
{"QUIN_TDM_TX_7", NULL, "Quinary TDM7 Capture"},
{"TERT_MI2S_TX", NULL, "Tertiary MI2S Capture"},
{"PRI_MI2S_TX", NULL, "Primary MI2S Capture"},
{"SEC_MI2S_TX", NULL, "Secondary MI2S Capture"},
{"QUAT_MI2S_TX", NULL, "Quaternary MI2S Capture"},
{"QUIN_MI2S_TX", NULL, "Quinary MI2S Capture"},
{"WSA_CODEC_DMA_RX_0 Playback", NULL, "WSA_CODEC_DMA_RX_0"},
{"WSA_CODEC_DMA_TX_0", NULL, "WSA_CODEC_DMA_TX_0 Capture"},
{"WSA_CODEC_DMA_RX_1 Playback", NULL, "WSA_CODEC_DMA_RX_1"},
{"WSA_CODEC_DMA_TX_1", NULL, "WSA_CODEC_DMA_TX_1 Capture"},
{"WSA_CODEC_DMA_TX_2", NULL, "WSA_CODEC_DMA_TX_2 Capture"},
{"VA_CODEC_DMA_TX_0", NULL, "VA_CODEC_DMA_TX_0 Capture"},
{"VA_CODEC_DMA_TX_1", NULL, "VA_CODEC_DMA_TX_1 Capture"},
{"VA_CODEC_DMA_TX_2", NULL, "VA_CODEC_DMA_TX_2 Capture"},
{"RX_CODEC_DMA_RX_0 Playback", NULL, "RX_CODEC_DMA_RX_0"},
{"TX_CODEC_DMA_TX_0", NULL, "TX_CODEC_DMA_TX_0 Capture"},
{"RX_CODEC_DMA_RX_1 Playback", NULL, "RX_CODEC_DMA_RX_1"},
{"TX_CODEC_DMA_TX_1", NULL, "TX_CODEC_DMA_TX_1 Capture"},
{"RX_CODEC_DMA_RX_2 Playback", NULL, "RX_CODEC_DMA_RX_2"},
{"TX_CODEC_DMA_TX_2", NULL, "TX_CODEC_DMA_TX_2 Capture"},
{"RX_CODEC_DMA_RX_3 Playback", NULL, "RX_CODEC_DMA_RX_3"},
{"TX_CODEC_DMA_TX_3", NULL, "TX_CODEC_DMA_TX_3 Capture"},
{"RX_CODEC_DMA_RX_4 Playback", NULL, "RX_CODEC_DMA_RX_4"},
{"TX_CODEC_DMA_TX_4", NULL, "TX_CODEC_DMA_TX_4 Capture"},
{"RX_CODEC_DMA_RX_5 Playback", NULL, "RX_CODEC_DMA_RX_5"},
{"TX_CODEC_DMA_TX_5", NULL, "TX_CODEC_DMA_TX_5 Capture"},
{"RX_CODEC_DMA_RX_6 Playback", NULL, "RX_CODEC_DMA_RX_6"},
{"RX_CODEC_DMA_RX_7 Playback", NULL, "RX_CODEC_DMA_RX_7"},
};
static int msm_dai_q6_dai_probe(struct snd_soc_dai *dai)
{
struct q6afe_dai_data *dai_data = dev_get_drvdata(dai->dev);
struct q6afe_port *port;
port = q6afe_port_get_from_id(dai->dev, dai->id);
if (IS_ERR(port)) {
dev_err(dai->dev, "Unable to get afe port\n");
return -EINVAL;
}
dai_data->port[dai->id] = port;
return 0;
}
static int msm_dai_q6_dai_remove(struct snd_soc_dai *dai)
{
struct q6afe_dai_data *dai_data = dev_get_drvdata(dai->dev);
q6afe_port_put(dai_data->port[dai->id]);
dai_data->port[dai->id] = NULL;
return 0;
}
static const struct snd_soc_dai_ops q6hdmi_ops = {
.probe = msm_dai_q6_dai_probe,
.remove = msm_dai_q6_dai_remove,
.prepare = q6afe_dai_prepare,
.hw_params = q6hdmi_hw_params,
.shutdown = q6afe_dai_shutdown,
};
static const struct snd_soc_dai_ops q6i2s_ops = {
.probe = msm_dai_q6_dai_probe,
.remove = msm_dai_q6_dai_remove,
.prepare = q6afe_dai_prepare,
.hw_params = q6i2s_hw_params,
.set_fmt = q6i2s_set_fmt,
.shutdown = q6afe_dai_shutdown,
.set_sysclk = q6afe_mi2s_set_sysclk,
};
static const struct snd_soc_dai_ops q6slim_ops = {
.probe = msm_dai_q6_dai_probe,
.remove = msm_dai_q6_dai_remove,
.prepare = q6afe_dai_prepare,
.hw_params = q6slim_hw_params,
.shutdown = q6afe_dai_shutdown,
.set_channel_map = q6slim_set_channel_map,
};
static const struct snd_soc_dai_ops q6tdm_ops = {
.probe = msm_dai_q6_dai_probe,
.remove = msm_dai_q6_dai_remove,
.prepare = q6afe_dai_prepare,
.shutdown = q6afe_dai_shutdown,
.set_sysclk = q6afe_mi2s_set_sysclk,
.set_tdm_slot = q6tdm_set_tdm_slot,
.set_channel_map = q6tdm_set_channel_map,
.hw_params = q6tdm_hw_params,
};
static const struct snd_soc_dai_ops q6dma_ops = {
.probe = msm_dai_q6_dai_probe,
.remove = msm_dai_q6_dai_remove,
.prepare = q6afe_dai_prepare,
.shutdown = q6afe_dai_shutdown,
.set_sysclk = q6afe_mi2s_set_sysclk,
.set_channel_map = q6dma_set_channel_map,
.hw_params = q6dma_hw_params,
};
static const struct snd_soc_dapm_widget q6afe_dai_widgets[] = {
SND_SOC_DAPM_AIF_IN("HDMI_RX", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("SLIMBUS_0_RX", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("SLIMBUS_1_RX", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("SLIMBUS_2_RX", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("SLIMBUS_3_RX", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("SLIMBUS_4_RX", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("SLIMBUS_5_RX", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("SLIMBUS_6_RX", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("SLIMBUS_0_TX", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("SLIMBUS_1_TX", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("SLIMBUS_2_TX", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("SLIMBUS_3_TX", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("SLIMBUS_4_TX", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("SLIMBUS_5_TX", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("SLIMBUS_6_TX", NULL, 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("QUIN_MI2S_RX", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("QUIN_MI2S_TX", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("QUAT_MI2S_RX", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("QUAT_MI2S_TX", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("TERT_MI2S_RX", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("TERT_MI2S_TX", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("SEC_MI2S_RX", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("SEC_MI2S_TX", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("SEC_MI2S_RX_SD1",
"Secondary MI2S Playback SD1",
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("PRI_MI2S_RX", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("PRI_MI2S_TX", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("PRIMARY_TDM_RX_0", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("PRIMARY_TDM_RX_1", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("PRIMARY_TDM_RX_2", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("PRIMARY_TDM_RX_3", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("PRIMARY_TDM_RX_4", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("PRIMARY_TDM_RX_5", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("PRIMARY_TDM_RX_6", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("PRIMARY_TDM_RX_7", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("PRIMARY_TDM_TX_0", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("PRIMARY_TDM_TX_1", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("PRIMARY_TDM_TX_2", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("PRIMARY_TDM_TX_3", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("PRIMARY_TDM_TX_4", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("PRIMARY_TDM_TX_5", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("PRIMARY_TDM_TX_6", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("PRIMARY_TDM_TX_7", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("SEC_TDM_RX_0", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("SEC_TDM_RX_1", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("SEC_TDM_RX_2", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("SEC_TDM_RX_3", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("SEC_TDM_RX_4", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("SEC_TDM_RX_5", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("SEC_TDM_RX_6", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("SEC_TDM_RX_7", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("SEC_TDM_TX_0", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("SEC_TDM_TX_1", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("SEC_TDM_TX_2", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("SEC_TDM_TX_3", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("SEC_TDM_TX_4", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("SEC_TDM_TX_5", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("SEC_TDM_TX_6", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("SEC_TDM_TX_7", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("TERT_TDM_RX_0", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("TERT_TDM_RX_1", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("TERT_TDM_RX_2", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("TERT_TDM_RX_3", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("TERT_TDM_RX_4", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("TERT_TDM_RX_5", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("TERT_TDM_RX_6", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("TERT_TDM_RX_7", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("TERT_TDM_TX_0", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("TERT_TDM_TX_1", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("TERT_TDM_TX_2", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("TERT_TDM_TX_3", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("TERT_TDM_TX_4", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("TERT_TDM_TX_5", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("TERT_TDM_TX_6", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("TERT_TDM_TX_7", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("QUAT_TDM_RX_0", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("QUAT_TDM_RX_1", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("QUAT_TDM_RX_2", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("QUAT_TDM_RX_3", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("QUAT_TDM_RX_4", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("QUAT_TDM_RX_5", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("QUAT_TDM_RX_6", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("QUAT_TDM_RX_7", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("QUAT_TDM_TX_0", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("QUAT_TDM_TX_1", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("QUAT_TDM_TX_2", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("QUAT_TDM_TX_3", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("QUAT_TDM_TX_4", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("QUAT_TDM_TX_5", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("QUAT_TDM_TX_6", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("QUAT_TDM_TX_7", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("QUIN_TDM_RX_0", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("QUIN_TDM_RX_1", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("QUIN_TDM_RX_2", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("QUIN_TDM_RX_3", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("QUIN_TDM_RX_4", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("QUIN_TDM_RX_5", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("QUIN_TDM_RX_6", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("QUIN_TDM_RX_7", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("QUIN_TDM_TX_0", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("QUIN_TDM_TX_1", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("QUIN_TDM_TX_2", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("QUIN_TDM_TX_3", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("QUIN_TDM_TX_4", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("QUIN_TDM_TX_5", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("QUIN_TDM_TX_6", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("QUIN_TDM_TX_7", NULL,
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("DISPLAY_PORT_RX", "NULL", 0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("WSA_CODEC_DMA_RX_0", "NULL",
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("WSA_CODEC_DMA_TX_0", "NULL",
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("WSA_CODEC_DMA_RX_1", "NULL",
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("WSA_CODEC_DMA_TX_1", "NULL",
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("WSA_CODEC_DMA_TX_2", "NULL",
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("VA_CODEC_DMA_TX_0", "NULL",
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("VA_CODEC_DMA_TX_1", "NULL",
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("VA_CODEC_DMA_TX_2", "NULL",
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("RX_CODEC_DMA_RX_0", "NULL",
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("TX_CODEC_DMA_TX_0", "NULL",
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("RX_CODEC_DMA_RX_1", "NULL",
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("TX_CODEC_DMA_TX_1", "NULL",
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("RX_CODEC_DMA_RX_2", "NULL",
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("TX_CODEC_DMA_TX_2", "NULL",
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("RX_CODEC_DMA_RX_3", "NULL",
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("TX_CODEC_DMA_TX_3", "NULL",
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("RX_CODEC_DMA_RX_4", "NULL",
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("TX_CODEC_DMA_TX_4", "NULL",
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("RX_CODEC_DMA_RX_5", "NULL",
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_OUT("TX_CODEC_DMA_TX_5", "NULL",
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("RX_CODEC_DMA_RX_6", "NULL",
0, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_AIF_IN("RX_CODEC_DMA_RX_7", "NULL",
0, SND_SOC_NOPM, 0, 0),
};
static const struct snd_soc_component_driver q6afe_dai_component = {
.name = "q6afe-dai-component",
.dapm_widgets = q6afe_dai_widgets,
.num_dapm_widgets = ARRAY_SIZE(q6afe_dai_widgets),
.dapm_routes = q6afe_dapm_routes,
.num_dapm_routes = ARRAY_SIZE(q6afe_dapm_routes),
.of_xlate_dai_name = q6dsp_audio_ports_of_xlate_dai_name,
};
static void of_q6afe_parse_dai_data(struct device *dev,
struct q6afe_dai_data *data)
{
struct device_node *node;
int ret;
for_each_child_of_node(dev->of_node, node) {
unsigned int lines[Q6AFE_MAX_MI2S_LINES];
struct q6afe_dai_priv_data *priv;
int id, i, num_lines;
ret = of_property_read_u32(node, "reg", &id);
if (ret || id < 0 || id >= AFE_PORT_MAX) {
dev_err(dev, "valid dai id not found:%d\n", ret);
continue;
}
switch (id) {
/* MI2S specific properties */
case QUINARY_MI2S_RX ... QUINARY_MI2S_TX:
case PRIMARY_MI2S_RX ... QUATERNARY_MI2S_TX:
priv = &data->priv[id];
ret = of_property_read_variable_u32_array(node,
"qcom,sd-lines",
lines, 0,
Q6AFE_MAX_MI2S_LINES);
if (ret < 0)
num_lines = 0;
else
num_lines = ret;
priv->sd_line_mask = 0;
for (i = 0; i < num_lines; i++)
priv->sd_line_mask |= BIT(lines[i]);
break;
case PRIMARY_TDM_RX_0 ... QUINARY_TDM_TX_7:
priv = &data->priv[id];
ret = of_property_read_u32(node, "qcom,tdm-sync-mode",
&priv->sync_mode);
if (ret) {
dev_err(dev, "No Sync mode from DT\n");
break;
}
ret = of_property_read_u32(node, "qcom,tdm-sync-src",
&priv->sync_src);
if (ret) {
dev_err(dev, "No Sync Src from DT\n");
break;
}
ret = of_property_read_u32(node, "qcom,tdm-data-out",
&priv->data_out_enable);
if (ret) {
dev_err(dev, "No Data out enable from DT\n");
break;
}
ret = of_property_read_u32(node, "qcom,tdm-invert-sync",
&priv->invert_sync);
if (ret) {
dev_err(dev, "No Invert sync from DT\n");
break;
}
ret = of_property_read_u32(node, "qcom,tdm-data-delay",
&priv->data_delay);
if (ret) {
dev_err(dev, "No Data Delay from DT\n");
break;
}
ret = of_property_read_u32(node, "qcom,tdm-data-align",
&priv->data_align);
if (ret) {
dev_err(dev, "No Data align from DT\n");
break;
}
break;
default:
break;
}
}
}
static int q6afe_dai_dev_probe(struct platform_device *pdev)
{
struct q6dsp_audio_port_dai_driver_config cfg;
struct snd_soc_dai_driver *dais;
struct q6afe_dai_data *dai_data;
struct device *dev = &pdev->dev;
int num_dais;
dai_data = devm_kzalloc(dev, sizeof(*dai_data), GFP_KERNEL);
if (!dai_data)
return -ENOMEM;
dev_set_drvdata(dev, dai_data);
of_q6afe_parse_dai_data(dev, dai_data);
cfg.q6hdmi_ops = &q6hdmi_ops;
cfg.q6slim_ops = &q6slim_ops;
cfg.q6i2s_ops = &q6i2s_ops;
cfg.q6tdm_ops = &q6tdm_ops;
cfg.q6dma_ops = &q6dma_ops;
dais = q6dsp_audio_ports_set_config(dev, &cfg, &num_dais);
return devm_snd_soc_register_component(dev, &q6afe_dai_component, dais, num_dais);
}
#ifdef CONFIG_OF
static const struct of_device_id q6afe_dai_device_id[] = {
{ .compatible = "qcom,q6afe-dais" },
{},
};
MODULE_DEVICE_TABLE(of, q6afe_dai_device_id);
#endif
static struct platform_driver q6afe_dai_platform_driver = {
.driver = {
.name = "q6afe-dai",
.of_match_table = of_match_ptr(q6afe_dai_device_id),
},
.probe = q6afe_dai_dev_probe,
};
module_platform_driver(q6afe_dai_platform_driver);
MODULE_DESCRIPTION("Q6 Audio Frontend dai driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/qcom/qdsp6/q6afe-dai.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Au12x0/Au1550 PSC ALSA ASoC audio support.
*
* (c) 2007-2008 MSC Vertriebsges.m.b.H.,
* Manuel Lauss <[email protected]>
*
* DMA glue for Au1x-PSC audio.
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/dma-mapping.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/au1xxx_dbdma.h>
#include <asm/mach-au1x00/au1xxx_psc.h>
#include "psc.h"
/*#define PCM_DEBUG*/
#define DRV_NAME "dbdma2"
#define MSG(x...) printk(KERN_INFO "au1xpsc_pcm: " x)
#ifdef PCM_DEBUG
#define DBG MSG
#else
#define DBG(x...) do {} while (0)
#endif
struct au1xpsc_audio_dmadata {
/* DDMA control data */
unsigned int ddma_id; /* DDMA direction ID for this PSC */
u32 ddma_chan; /* DDMA context */
/* PCM context (for irq handlers) */
struct snd_pcm_substream *substream;
unsigned long curr_period; /* current segment DDMA is working on */
unsigned long q_period; /* queue period(s) */
dma_addr_t dma_area; /* address of queued DMA area */
dma_addr_t dma_area_s; /* start address of DMA area */
unsigned long pos; /* current byte position being played */
unsigned long periods; /* number of SG segments in total */
unsigned long period_bytes; /* size in bytes of one SG segment */
/* runtime data */
int msbits;
};
/*
* These settings are somewhat okay, at least on my machine audio plays
* almost skip-free. Especially the 64kB buffer seems to help a LOT.
*/
#define AU1XPSC_PERIOD_MIN_BYTES 1024
#define AU1XPSC_BUFFER_MIN_BYTES 65536
/* PCM hardware DMA capabilities - platform specific */
static const struct snd_pcm_hardware au1xpsc_pcm_hardware = {
.info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BATCH,
.period_bytes_min = AU1XPSC_PERIOD_MIN_BYTES,
.period_bytes_max = 4096 * 1024 - 1,
.periods_min = 2,
.periods_max = 4096, /* 2 to as-much-as-you-like */
.buffer_bytes_max = 4096 * 1024 - 1,
.fifo_size = 16, /* fifo entries of AC97/I2S PSC */
};
static void au1x_pcm_queue_tx(struct au1xpsc_audio_dmadata *cd)
{
au1xxx_dbdma_put_source(cd->ddma_chan, cd->dma_area,
cd->period_bytes, DDMA_FLAGS_IE);
/* update next-to-queue period */
++cd->q_period;
cd->dma_area += cd->period_bytes;
if (cd->q_period >= cd->periods) {
cd->q_period = 0;
cd->dma_area = cd->dma_area_s;
}
}
static void au1x_pcm_queue_rx(struct au1xpsc_audio_dmadata *cd)
{
au1xxx_dbdma_put_dest(cd->ddma_chan, cd->dma_area,
cd->period_bytes, DDMA_FLAGS_IE);
/* update next-to-queue period */
++cd->q_period;
cd->dma_area += cd->period_bytes;
if (cd->q_period >= cd->periods) {
cd->q_period = 0;
cd->dma_area = cd->dma_area_s;
}
}
static void au1x_pcm_dmatx_cb(int irq, void *dev_id)
{
struct au1xpsc_audio_dmadata *cd = dev_id;
cd->pos += cd->period_bytes;
if (++cd->curr_period >= cd->periods) {
cd->pos = 0;
cd->curr_period = 0;
}
snd_pcm_period_elapsed(cd->substream);
au1x_pcm_queue_tx(cd);
}
static void au1x_pcm_dmarx_cb(int irq, void *dev_id)
{
struct au1xpsc_audio_dmadata *cd = dev_id;
cd->pos += cd->period_bytes;
if (++cd->curr_period >= cd->periods) {
cd->pos = 0;
cd->curr_period = 0;
}
snd_pcm_period_elapsed(cd->substream);
au1x_pcm_queue_rx(cd);
}
static void au1x_pcm_dbdma_free(struct au1xpsc_audio_dmadata *pcd)
{
if (pcd->ddma_chan) {
au1xxx_dbdma_stop(pcd->ddma_chan);
au1xxx_dbdma_reset(pcd->ddma_chan);
au1xxx_dbdma_chan_free(pcd->ddma_chan);
pcd->ddma_chan = 0;
pcd->msbits = 0;
}
}
/* in case of missing DMA ring or changed TX-source / RX-dest bit widths,
* allocate (or reallocate) a 2-descriptor DMA ring with bit depth according
* to ALSA-supplied sample depth. This is due to limitations in the dbdma api
* (cannot adjust source/dest widths of already allocated descriptor ring).
*/
static int au1x_pcm_dbdma_realloc(struct au1xpsc_audio_dmadata *pcd,
int stype, int msbits)
{
/* DMA only in 8/16/32 bit widths */
if (msbits == 24)
msbits = 32;
/* check current config: correct bits and descriptors allocated? */
if ((pcd->ddma_chan) && (msbits == pcd->msbits))
goto out; /* all ok! */
au1x_pcm_dbdma_free(pcd);
if (stype == SNDRV_PCM_STREAM_CAPTURE)
pcd->ddma_chan = au1xxx_dbdma_chan_alloc(pcd->ddma_id,
DSCR_CMD0_ALWAYS,
au1x_pcm_dmarx_cb, (void *)pcd);
else
pcd->ddma_chan = au1xxx_dbdma_chan_alloc(DSCR_CMD0_ALWAYS,
pcd->ddma_id,
au1x_pcm_dmatx_cb, (void *)pcd);
if (!pcd->ddma_chan)
return -ENOMEM;
au1xxx_dbdma_set_devwidth(pcd->ddma_chan, msbits);
au1xxx_dbdma_ring_alloc(pcd->ddma_chan, 2);
pcd->msbits = msbits;
au1xxx_dbdma_stop(pcd->ddma_chan);
au1xxx_dbdma_reset(pcd->ddma_chan);
out:
return 0;
}
static inline struct au1xpsc_audio_dmadata *to_dmadata(struct snd_pcm_substream *ss,
struct snd_soc_component *component)
{
struct au1xpsc_audio_dmadata *pcd = snd_soc_component_get_drvdata(component);
return &pcd[ss->stream];
}
static int au1xpsc_pcm_hw_params(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct au1xpsc_audio_dmadata *pcd;
int stype, ret;
stype = substream->stream;
pcd = to_dmadata(substream, component);
DBG("runtime->dma_area = 0x%08lx dma_addr_t = 0x%08lx dma_size = %zu "
"runtime->min_align %lu\n",
(unsigned long)runtime->dma_area,
(unsigned long)runtime->dma_addr, runtime->dma_bytes,
runtime->min_align);
DBG("bits %d frags %d frag_bytes %d is_rx %d\n", params->msbits,
params_periods(params), params_period_bytes(params), stype);
ret = au1x_pcm_dbdma_realloc(pcd, stype, params->msbits);
if (ret) {
MSG("DDMA channel (re)alloc failed!\n");
goto out;
}
pcd->substream = substream;
pcd->period_bytes = params_period_bytes(params);
pcd->periods = params_periods(params);
pcd->dma_area_s = pcd->dma_area = runtime->dma_addr;
pcd->q_period = 0;
pcd->curr_period = 0;
pcd->pos = 0;
ret = 0;
out:
return ret;
}
static int au1xpsc_pcm_prepare(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct au1xpsc_audio_dmadata *pcd = to_dmadata(substream, component);
au1xxx_dbdma_reset(pcd->ddma_chan);
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
au1x_pcm_queue_rx(pcd);
au1x_pcm_queue_rx(pcd);
} else {
au1x_pcm_queue_tx(pcd);
au1x_pcm_queue_tx(pcd);
}
return 0;
}
static int au1xpsc_pcm_trigger(struct snd_soc_component *component,
struct snd_pcm_substream *substream, int cmd)
{
u32 c = to_dmadata(substream, component)->ddma_chan;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
au1xxx_dbdma_start(c);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
au1xxx_dbdma_stop(c);
break;
default:
return -EINVAL;
}
return 0;
}
static snd_pcm_uframes_t
au1xpsc_pcm_pointer(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
return bytes_to_frames(substream->runtime,
to_dmadata(substream, component)->pos);
}
static int au1xpsc_pcm_open(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct au1xpsc_audio_dmadata *pcd = to_dmadata(substream, component);
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
int stype = substream->stream, *dmaids;
dmaids = snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(rtd, 0), substream);
if (!dmaids)
return -ENODEV; /* whoa, has ordering changed? */
pcd->ddma_id = dmaids[stype];
snd_soc_set_runtime_hwparams(substream, &au1xpsc_pcm_hardware);
return 0;
}
static int au1xpsc_pcm_close(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
au1x_pcm_dbdma_free(to_dmadata(substream, component));
return 0;
}
static int au1xpsc_pcm_new(struct snd_soc_component *component,
struct snd_soc_pcm_runtime *rtd)
{
struct snd_card *card = rtd->card->snd_card;
struct snd_pcm *pcm = rtd->pcm;
snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
card->dev, AU1XPSC_BUFFER_MIN_BYTES, (4096 * 1024) - 1);
return 0;
}
/* au1xpsc audio platform */
static struct snd_soc_component_driver au1xpsc_soc_component = {
.name = DRV_NAME,
.open = au1xpsc_pcm_open,
.close = au1xpsc_pcm_close,
.hw_params = au1xpsc_pcm_hw_params,
.prepare = au1xpsc_pcm_prepare,
.trigger = au1xpsc_pcm_trigger,
.pointer = au1xpsc_pcm_pointer,
.pcm_construct = au1xpsc_pcm_new,
};
static int au1xpsc_pcm_drvprobe(struct platform_device *pdev)
{
struct au1xpsc_audio_dmadata *dmadata;
dmadata = devm_kcalloc(&pdev->dev,
2, sizeof(struct au1xpsc_audio_dmadata),
GFP_KERNEL);
if (!dmadata)
return -ENOMEM;
platform_set_drvdata(pdev, dmadata);
return devm_snd_soc_register_component(&pdev->dev,
&au1xpsc_soc_component, NULL, 0);
}
static struct platform_driver au1xpsc_pcm_driver = {
.driver = {
.name = "au1xpsc-pcm",
},
.probe = au1xpsc_pcm_drvprobe,
};
module_platform_driver(au1xpsc_pcm_driver);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Au12x0/Au1550 PSC Audio DMA driver");
MODULE_AUTHOR("Manuel Lauss");
| linux-master | sound/soc/au1x/dbdma2.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* DB1000/DB1500/DB1100 ASoC audio fabric support code.
*
* (c) 2011 Manuel Lauss <[email protected]>
*
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/timer.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/soc.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-db1x00/bcsr.h>
#include "psc.h"
SND_SOC_DAILINK_DEFS(hifi,
DAILINK_COMP_ARRAY(COMP_CPU("alchemy-ac97c")),
DAILINK_COMP_ARRAY(COMP_CODEC("ac97-codec", "ac97-hifi")),
DAILINK_COMP_ARRAY(COMP_PLATFORM("alchemy-pcm-dma.0")));
static struct snd_soc_dai_link db1000_ac97_dai = {
.name = "AC97",
.stream_name = "AC97 HiFi",
SND_SOC_DAILINK_REG(hifi),
};
static struct snd_soc_card db1000_ac97 = {
.name = "DB1000_AC97",
.owner = THIS_MODULE,
.dai_link = &db1000_ac97_dai,
.num_links = 1,
};
static int db1000_audio_probe(struct platform_device *pdev)
{
struct snd_soc_card *card = &db1000_ac97;
card->dev = &pdev->dev;
return devm_snd_soc_register_card(&pdev->dev, card);
}
static struct platform_driver db1000_audio_driver = {
.driver = {
.name = "db1000-audio",
.pm = &snd_soc_pm_ops,
},
.probe = db1000_audio_probe,
};
module_platform_driver(db1000_audio_driver);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("DB1000/DB1500/DB1100 ASoC audio");
MODULE_AUTHOR("Manuel Lauss");
| linux-master | sound/soc/au1x/db1000.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* DB1200/DB1300/DB1550 ASoC audio fabric support code.
*
* (c) 2008-2011 Manuel Lauss <[email protected]>
*
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/timer.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/soc.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/au1xxx_psc.h>
#include <asm/mach-au1x00/au1xxx_dbdma.h>
#include <asm/mach-db1x00/bcsr.h>
#include "../codecs/wm8731.h"
#include "psc.h"
static const struct platform_device_id db1200_pids[] = {
{
.name = "db1200-ac97",
.driver_data = 0,
}, {
.name = "db1200-i2s",
.driver_data = 1,
}, {
.name = "db1300-ac97",
.driver_data = 2,
}, {
.name = "db1300-i2s",
.driver_data = 3,
}, {
.name = "db1550-ac97",
.driver_data = 4,
}, {
.name = "db1550-i2s",
.driver_data = 5,
},
{},
};
/*------------------------- AC97 PART ---------------------------*/
SND_SOC_DAILINK_DEFS(db1200_ac97,
DAILINK_COMP_ARRAY(COMP_CPU("au1xpsc_ac97.1")),
DAILINK_COMP_ARRAY(COMP_CODEC("ac97-codec.1", "ac97-hifi")),
DAILINK_COMP_ARRAY(COMP_PLATFORM("au1xpsc-pcm.1")));
static struct snd_soc_dai_link db1200_ac97_dai = {
.name = "AC97",
.stream_name = "AC97 HiFi",
SND_SOC_DAILINK_REG(db1200_ac97),
};
static struct snd_soc_card db1200_ac97_machine = {
.name = "DB1200_AC97",
.owner = THIS_MODULE,
.dai_link = &db1200_ac97_dai,
.num_links = 1,
};
SND_SOC_DAILINK_DEFS(db1300_ac97,
DAILINK_COMP_ARRAY(COMP_CPU("au1xpsc_ac97.1")),
DAILINK_COMP_ARRAY(COMP_CODEC("wm9712-codec.1", "wm9712-hifi")),
DAILINK_COMP_ARRAY(COMP_PLATFORM("au1xpsc-pcm.1")));
static struct snd_soc_dai_link db1300_ac97_dai = {
.name = "AC97",
.stream_name = "AC97 HiFi",
SND_SOC_DAILINK_REG(db1300_ac97),
};
static struct snd_soc_card db1300_ac97_machine = {
.name = "DB1300_AC97",
.owner = THIS_MODULE,
.dai_link = &db1300_ac97_dai,
.num_links = 1,
};
static struct snd_soc_card db1550_ac97_machine = {
.name = "DB1550_AC97",
.owner = THIS_MODULE,
.dai_link = &db1200_ac97_dai,
.num_links = 1,
};
/*------------------------- I2S PART ---------------------------*/
static int db1200_i2s_startup(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
/* WM8731 has its own 12MHz crystal */
snd_soc_dai_set_sysclk(codec_dai, WM8731_SYSCLK_XTAL,
12000000, SND_SOC_CLOCK_IN);
return 0;
}
static const struct snd_soc_ops db1200_i2s_wm8731_ops = {
.startup = db1200_i2s_startup,
};
SND_SOC_DAILINK_DEFS(db1200_i2s,
DAILINK_COMP_ARRAY(COMP_CPU("au1xpsc_i2s.1")),
DAILINK_COMP_ARRAY(COMP_CODEC("wm8731.0-001b", "wm8731-hifi")),
DAILINK_COMP_ARRAY(COMP_PLATFORM("au1xpsc-pcm.1")));
static struct snd_soc_dai_link db1200_i2s_dai = {
.name = "WM8731",
.stream_name = "WM8731 PCM",
.dai_fmt = SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBP_CFP,
.ops = &db1200_i2s_wm8731_ops,
SND_SOC_DAILINK_REG(db1200_i2s),
};
static struct snd_soc_card db1200_i2s_machine = {
.name = "DB1200_I2S",
.owner = THIS_MODULE,
.dai_link = &db1200_i2s_dai,
.num_links = 1,
};
SND_SOC_DAILINK_DEFS(db1300_i2s,
DAILINK_COMP_ARRAY(COMP_CPU("au1xpsc_i2s.2")),
DAILINK_COMP_ARRAY(COMP_CODEC("wm8731.0-001b", "wm8731-hifi")),
DAILINK_COMP_ARRAY(COMP_PLATFORM("au1xpsc-pcm.2")));
static struct snd_soc_dai_link db1300_i2s_dai = {
.name = "WM8731",
.stream_name = "WM8731 PCM",
.dai_fmt = SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBP_CFP,
.ops = &db1200_i2s_wm8731_ops,
SND_SOC_DAILINK_REG(db1300_i2s),
};
static struct snd_soc_card db1300_i2s_machine = {
.name = "DB1300_I2S",
.owner = THIS_MODULE,
.dai_link = &db1300_i2s_dai,
.num_links = 1,
};
SND_SOC_DAILINK_DEFS(db1550_i2s,
DAILINK_COMP_ARRAY(COMP_CPU("au1xpsc_i2s.3")),
DAILINK_COMP_ARRAY(COMP_CODEC("wm8731.0-001b", "wm8731-hifi")),
DAILINK_COMP_ARRAY(COMP_PLATFORM("au1xpsc-pcm.3")));
static struct snd_soc_dai_link db1550_i2s_dai = {
.name = "WM8731",
.stream_name = "WM8731 PCM",
.dai_fmt = SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBP_CFP,
.ops = &db1200_i2s_wm8731_ops,
SND_SOC_DAILINK_REG(db1550_i2s),
};
static struct snd_soc_card db1550_i2s_machine = {
.name = "DB1550_I2S",
.owner = THIS_MODULE,
.dai_link = &db1550_i2s_dai,
.num_links = 1,
};
/*------------------------- COMMON PART ---------------------------*/
static struct snd_soc_card *db1200_cards[] = {
&db1200_ac97_machine,
&db1200_i2s_machine,
&db1300_ac97_machine,
&db1300_i2s_machine,
&db1550_ac97_machine,
&db1550_i2s_machine,
};
static int db1200_audio_probe(struct platform_device *pdev)
{
const struct platform_device_id *pid = platform_get_device_id(pdev);
struct snd_soc_card *card;
card = db1200_cards[pid->driver_data];
card->dev = &pdev->dev;
return devm_snd_soc_register_card(&pdev->dev, card);
}
static struct platform_driver db1200_audio_driver = {
.driver = {
.name = "db1200-ac97",
.pm = &snd_soc_pm_ops,
},
.id_table = db1200_pids,
.probe = db1200_audio_probe,
};
module_platform_driver(db1200_audio_driver);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("DB1200/DB1300/DB1550 ASoC audio support");
MODULE_AUTHOR("Manuel Lauss");
| linux-master | sound/soc/au1x/db1200.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Au1000/Au1500/Au1100 Audio DMA support.
*
* (c) 2011 Manuel Lauss <[email protected]>
*
* copied almost verbatim from the old ALSA driver, written by
* Charles Eidsness <[email protected]>
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/dma-mapping.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/au1000_dma.h>
#include "psc.h"
#define DRV_NAME "au1x_dma"
struct pcm_period {
u32 start;
u32 relative_end; /* relative to start of buffer */
struct pcm_period *next;
};
struct audio_stream {
struct snd_pcm_substream *substream;
int dma;
struct pcm_period *buffer;
unsigned int period_size;
unsigned int periods;
};
struct alchemy_pcm_ctx {
struct audio_stream stream[2]; /* playback & capture */
};
static void au1000_release_dma_link(struct audio_stream *stream)
{
struct pcm_period *pointer;
struct pcm_period *pointer_next;
stream->period_size = 0;
stream->periods = 0;
pointer = stream->buffer;
if (!pointer)
return;
do {
pointer_next = pointer->next;
kfree(pointer);
pointer = pointer_next;
} while (pointer != stream->buffer);
stream->buffer = NULL;
}
static int au1000_setup_dma_link(struct audio_stream *stream,
unsigned int period_bytes,
unsigned int periods)
{
struct snd_pcm_substream *substream = stream->substream;
struct snd_pcm_runtime *runtime = substream->runtime;
struct pcm_period *pointer;
unsigned long dma_start;
int i;
dma_start = virt_to_phys(runtime->dma_area);
if (stream->period_size == period_bytes &&
stream->periods == periods)
return 0; /* not changed */
au1000_release_dma_link(stream);
stream->period_size = period_bytes;
stream->periods = periods;
stream->buffer = kmalloc(sizeof(struct pcm_period), GFP_KERNEL);
if (!stream->buffer)
return -ENOMEM;
pointer = stream->buffer;
for (i = 0; i < periods; i++) {
pointer->start = (u32)(dma_start + (i * period_bytes));
pointer->relative_end = (u32) (((i+1) * period_bytes) - 0x1);
if (i < periods - 1) {
pointer->next = kmalloc(sizeof(struct pcm_period),
GFP_KERNEL);
if (!pointer->next) {
au1000_release_dma_link(stream);
return -ENOMEM;
}
pointer = pointer->next;
}
}
pointer->next = stream->buffer;
return 0;
}
static void au1000_dma_stop(struct audio_stream *stream)
{
if (stream->buffer)
disable_dma(stream->dma);
}
static void au1000_dma_start(struct audio_stream *stream)
{
if (!stream->buffer)
return;
init_dma(stream->dma);
if (get_dma_active_buffer(stream->dma) == 0) {
clear_dma_done0(stream->dma);
set_dma_addr0(stream->dma, stream->buffer->start);
set_dma_count0(stream->dma, stream->period_size >> 1);
set_dma_addr1(stream->dma, stream->buffer->next->start);
set_dma_count1(stream->dma, stream->period_size >> 1);
} else {
clear_dma_done1(stream->dma);
set_dma_addr1(stream->dma, stream->buffer->start);
set_dma_count1(stream->dma, stream->period_size >> 1);
set_dma_addr0(stream->dma, stream->buffer->next->start);
set_dma_count0(stream->dma, stream->period_size >> 1);
}
enable_dma_buffers(stream->dma);
start_dma(stream->dma);
}
static irqreturn_t au1000_dma_interrupt(int irq, void *ptr)
{
struct audio_stream *stream = (struct audio_stream *)ptr;
struct snd_pcm_substream *substream = stream->substream;
switch (get_dma_buffer_done(stream->dma)) {
case DMA_D0:
stream->buffer = stream->buffer->next;
clear_dma_done0(stream->dma);
set_dma_addr0(stream->dma, stream->buffer->next->start);
set_dma_count0(stream->dma, stream->period_size >> 1);
enable_dma_buffer0(stream->dma);
break;
case DMA_D1:
stream->buffer = stream->buffer->next;
clear_dma_done1(stream->dma);
set_dma_addr1(stream->dma, stream->buffer->next->start);
set_dma_count1(stream->dma, stream->period_size >> 1);
enable_dma_buffer1(stream->dma);
break;
case (DMA_D0 | DMA_D1):
pr_debug("DMA %d missed interrupt.\n", stream->dma);
au1000_dma_stop(stream);
au1000_dma_start(stream);
break;
case (~DMA_D0 & ~DMA_D1):
pr_debug("DMA %d empty irq.\n", stream->dma);
}
snd_pcm_period_elapsed(substream);
return IRQ_HANDLED;
}
static const struct snd_pcm_hardware alchemy_pcm_hardware = {
.info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BATCH,
.period_bytes_min = 1024,
.period_bytes_max = 16 * 1024 - 1,
.periods_min = 4,
.periods_max = 255,
.buffer_bytes_max = 128 * 1024,
.fifo_size = 16,
};
static inline struct alchemy_pcm_ctx *ss_to_ctx(struct snd_pcm_substream *ss,
struct snd_soc_component *component)
{
return snd_soc_component_get_drvdata(component);
}
static inline struct audio_stream *ss_to_as(struct snd_pcm_substream *ss,
struct snd_soc_component *component)
{
struct alchemy_pcm_ctx *ctx = ss_to_ctx(ss, component);
return &(ctx->stream[ss->stream]);
}
static int alchemy_pcm_open(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct alchemy_pcm_ctx *ctx = ss_to_ctx(substream, component);
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
int *dmaids, s = substream->stream;
char *name;
dmaids = snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(rtd, 0), substream);
if (!dmaids)
return -ENODEV; /* whoa, has ordering changed? */
/* DMA setup */
name = (s == SNDRV_PCM_STREAM_PLAYBACK) ? "audio-tx" : "audio-rx";
ctx->stream[s].dma = request_au1000_dma(dmaids[s], name,
au1000_dma_interrupt, 0,
&ctx->stream[s]);
set_dma_mode(ctx->stream[s].dma,
get_dma_mode(ctx->stream[s].dma) & ~DMA_NC);
ctx->stream[s].substream = substream;
ctx->stream[s].buffer = NULL;
snd_soc_set_runtime_hwparams(substream, &alchemy_pcm_hardware);
return 0;
}
static int alchemy_pcm_close(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct alchemy_pcm_ctx *ctx = ss_to_ctx(substream, component);
int stype = substream->stream;
ctx->stream[stype].substream = NULL;
free_au1000_dma(ctx->stream[stype].dma);
return 0;
}
static int alchemy_pcm_hw_params(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *hw_params)
{
struct audio_stream *stream = ss_to_as(substream, component);
return au1000_setup_dma_link(stream,
params_period_bytes(hw_params),
params_periods(hw_params));
}
static int alchemy_pcm_hw_free(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct audio_stream *stream = ss_to_as(substream, component);
au1000_release_dma_link(stream);
return 0;
}
static int alchemy_pcm_trigger(struct snd_soc_component *component,
struct snd_pcm_substream *substream, int cmd)
{
struct audio_stream *stream = ss_to_as(substream, component);
int err = 0;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
au1000_dma_start(stream);
break;
case SNDRV_PCM_TRIGGER_STOP:
au1000_dma_stop(stream);
break;
default:
err = -EINVAL;
break;
}
return err;
}
static snd_pcm_uframes_t alchemy_pcm_pointer(struct snd_soc_component *component,
struct snd_pcm_substream *ss)
{
struct audio_stream *stream = ss_to_as(ss, component);
long location;
location = get_dma_residue(stream->dma);
location = stream->buffer->relative_end - location;
if (location == -1)
location = 0;
return bytes_to_frames(ss->runtime, location);
}
static int alchemy_pcm_new(struct snd_soc_component *component,
struct snd_soc_pcm_runtime *rtd)
{
struct snd_pcm *pcm = rtd->pcm;
snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS,
NULL, 65536, (4096 * 1024) - 1);
return 0;
}
static struct snd_soc_component_driver alchemy_pcm_soc_component = {
.name = DRV_NAME,
.open = alchemy_pcm_open,
.close = alchemy_pcm_close,
.hw_params = alchemy_pcm_hw_params,
.hw_free = alchemy_pcm_hw_free,
.trigger = alchemy_pcm_trigger,
.pointer = alchemy_pcm_pointer,
.pcm_construct = alchemy_pcm_new,
};
static int alchemy_pcm_drvprobe(struct platform_device *pdev)
{
struct alchemy_pcm_ctx *ctx;
ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
if (!ctx)
return -ENOMEM;
platform_set_drvdata(pdev, ctx);
return devm_snd_soc_register_component(&pdev->dev,
&alchemy_pcm_soc_component, NULL, 0);
}
static struct platform_driver alchemy_pcmdma_driver = {
.driver = {
.name = "alchemy-pcm-dma",
},
.probe = alchemy_pcm_drvprobe,
};
module_platform_driver(alchemy_pcmdma_driver);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Au1000/Au1500/Au1100 Audio DMA driver");
MODULE_AUTHOR("Manuel Lauss");
| linux-master | sound/soc/au1x/dma.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Au12x0/Au1550 PSC ALSA ASoC audio support.
*
* (c) 2007-2009 MSC Vertriebsges.m.b.H.,
* Manuel Lauss <[email protected]>
*
* Au1xxx-PSC AC97 glue.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/mutex.h>
#include <linux/suspend.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/initval.h>
#include <sound/soc.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/au1xxx_psc.h>
#include "psc.h"
/* how often to retry failed codec register reads/writes */
#define AC97_RW_RETRIES 5
#define AC97_DIR \
(SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE)
#define AC97_RATES \
SNDRV_PCM_RATE_8000_48000
#define AC97_FMTS \
(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3BE)
#define AC97PCR_START(stype) \
((stype) == SNDRV_PCM_STREAM_PLAYBACK ? PSC_AC97PCR_TS : PSC_AC97PCR_RS)
#define AC97PCR_STOP(stype) \
((stype) == SNDRV_PCM_STREAM_PLAYBACK ? PSC_AC97PCR_TP : PSC_AC97PCR_RP)
#define AC97PCR_CLRFIFO(stype) \
((stype) == SNDRV_PCM_STREAM_PLAYBACK ? PSC_AC97PCR_TC : PSC_AC97PCR_RC)
#define AC97STAT_BUSY(stype) \
((stype) == SNDRV_PCM_STREAM_PLAYBACK ? PSC_AC97STAT_TB : PSC_AC97STAT_RB)
/* instance data. There can be only one, MacLeod!!!! */
static struct au1xpsc_audio_data *au1xpsc_ac97_workdata;
#if 0
/* this could theoretically work, but ac97->bus->card->private_data can be NULL
* when snd_ac97_mixer() is called; I don't know if the rest further down the
* chain are always valid either.
*/
static inline struct au1xpsc_audio_data *ac97_to_pscdata(struct snd_ac97 *x)
{
struct snd_soc_card *c = x->bus->card->private_data;
return snd_soc_dai_get_drvdata(c->asoc_rtd_to_cpu(rtd, 0));
}
#else
#define ac97_to_pscdata(x) au1xpsc_ac97_workdata
#endif
/* AC97 controller reads codec register */
static unsigned short au1xpsc_ac97_read(struct snd_ac97 *ac97,
unsigned short reg)
{
struct au1xpsc_audio_data *pscdata = ac97_to_pscdata(ac97);
unsigned short retry, tmo;
unsigned long data;
__raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
wmb(); /* drain writebuffer */
retry = AC97_RW_RETRIES;
do {
mutex_lock(&pscdata->lock);
__raw_writel(PSC_AC97CDC_RD | PSC_AC97CDC_INDX(reg),
AC97_CDC(pscdata));
wmb(); /* drain writebuffer */
tmo = 20;
do {
udelay(21);
if (__raw_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD)
break;
} while (--tmo);
data = __raw_readl(AC97_CDC(pscdata));
__raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
wmb(); /* drain writebuffer */
mutex_unlock(&pscdata->lock);
if (reg != ((data >> 16) & 0x7f))
tmo = 1; /* wrong register, try again */
} while (--retry && !tmo);
return retry ? data & 0xffff : 0xffff;
}
/* AC97 controller writes to codec register */
static void au1xpsc_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
unsigned short val)
{
struct au1xpsc_audio_data *pscdata = ac97_to_pscdata(ac97);
unsigned int tmo, retry;
__raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
wmb(); /* drain writebuffer */
retry = AC97_RW_RETRIES;
do {
mutex_lock(&pscdata->lock);
__raw_writel(PSC_AC97CDC_INDX(reg) | (val & 0xffff),
AC97_CDC(pscdata));
wmb(); /* drain writebuffer */
tmo = 20;
do {
udelay(21);
if (__raw_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD)
break;
} while (--tmo);
__raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata));
wmb(); /* drain writebuffer */
mutex_unlock(&pscdata->lock);
} while (--retry && !tmo);
}
/* AC97 controller asserts a warm reset */
static void au1xpsc_ac97_warm_reset(struct snd_ac97 *ac97)
{
struct au1xpsc_audio_data *pscdata = ac97_to_pscdata(ac97);
__raw_writel(PSC_AC97RST_SNC, AC97_RST(pscdata));
wmb(); /* drain writebuffer */
msleep(10);
__raw_writel(0, AC97_RST(pscdata));
wmb(); /* drain writebuffer */
}
static void au1xpsc_ac97_cold_reset(struct snd_ac97 *ac97)
{
struct au1xpsc_audio_data *pscdata = ac97_to_pscdata(ac97);
int i;
/* disable PSC during cold reset */
__raw_writel(0, AC97_CFG(au1xpsc_ac97_workdata));
wmb(); /* drain writebuffer */
__raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(pscdata));
wmb(); /* drain writebuffer */
/* issue cold reset */
__raw_writel(PSC_AC97RST_RST, AC97_RST(pscdata));
wmb(); /* drain writebuffer */
msleep(500);
__raw_writel(0, AC97_RST(pscdata));
wmb(); /* drain writebuffer */
/* enable PSC */
__raw_writel(PSC_CTRL_ENABLE, PSC_CTRL(pscdata));
wmb(); /* drain writebuffer */
/* wait for PSC to indicate it's ready */
i = 1000;
while (!((__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_SR)) && (--i))
msleep(1);
if (i == 0) {
printk(KERN_ERR "au1xpsc-ac97: PSC not ready!\n");
return;
}
/* enable the ac97 function */
__raw_writel(pscdata->cfg | PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
wmb(); /* drain writebuffer */
/* wait for AC97 core to become ready */
i = 1000;
while (!((__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)) && (--i))
msleep(1);
if (i == 0)
printk(KERN_ERR "au1xpsc-ac97: AC97 ctrl not ready\n");
}
/* AC97 controller operations */
static struct snd_ac97_bus_ops psc_ac97_ops = {
.read = au1xpsc_ac97_read,
.write = au1xpsc_ac97_write,
.reset = au1xpsc_ac97_cold_reset,
.warm_reset = au1xpsc_ac97_warm_reset,
};
static int au1xpsc_ac97_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct au1xpsc_audio_data *pscdata = snd_soc_dai_get_drvdata(dai);
unsigned long r, ro, stat;
int chans, t, stype = substream->stream;
chans = params_channels(params);
r = ro = __raw_readl(AC97_CFG(pscdata));
stat = __raw_readl(AC97_STAT(pscdata));
/* already active? */
if (stat & (PSC_AC97STAT_TB | PSC_AC97STAT_RB)) {
/* reject parameters not currently set up */
if ((PSC_AC97CFG_GET_LEN(r) != params->msbits) ||
(pscdata->rate != params_rate(params)))
return -EINVAL;
} else {
/* set sample bitdepth: REG[24:21]=(BITS-2)/2 */
r &= ~PSC_AC97CFG_LEN_MASK;
r |= PSC_AC97CFG_SET_LEN(params->msbits);
/* channels: enable slots for front L/R channel */
if (stype == SNDRV_PCM_STREAM_PLAYBACK) {
r &= ~PSC_AC97CFG_TXSLOT_MASK;
r |= PSC_AC97CFG_TXSLOT_ENA(3);
r |= PSC_AC97CFG_TXSLOT_ENA(4);
} else {
r &= ~PSC_AC97CFG_RXSLOT_MASK;
r |= PSC_AC97CFG_RXSLOT_ENA(3);
r |= PSC_AC97CFG_RXSLOT_ENA(4);
}
/* do we need to poke the hardware? */
if (!(r ^ ro))
goto out;
/* ac97 engine is about to be disabled */
mutex_lock(&pscdata->lock);
/* disable AC97 device controller first... */
__raw_writel(r & ~PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
wmb(); /* drain writebuffer */
/* ...wait for it... */
t = 100;
while ((__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR) && --t)
msleep(1);
if (!t)
printk(KERN_ERR "PSC-AC97: can't disable!\n");
/* ...write config... */
__raw_writel(r, AC97_CFG(pscdata));
wmb(); /* drain writebuffer */
/* ...enable the AC97 controller again... */
__raw_writel(r | PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata));
wmb(); /* drain writebuffer */
/* ...and wait for ready bit */
t = 100;
while ((!(__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)) && --t)
msleep(1);
if (!t)
printk(KERN_ERR "PSC-AC97: can't enable!\n");
mutex_unlock(&pscdata->lock);
pscdata->cfg = r;
pscdata->rate = params_rate(params);
}
out:
return 0;
}
static int au1xpsc_ac97_trigger(struct snd_pcm_substream *substream,
int cmd, struct snd_soc_dai *dai)
{
struct au1xpsc_audio_data *pscdata = snd_soc_dai_get_drvdata(dai);
int ret, stype = substream->stream;
ret = 0;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
__raw_writel(AC97PCR_CLRFIFO(stype), AC97_PCR(pscdata));
wmb(); /* drain writebuffer */
__raw_writel(AC97PCR_START(stype), AC97_PCR(pscdata));
wmb(); /* drain writebuffer */
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
__raw_writel(AC97PCR_STOP(stype), AC97_PCR(pscdata));
wmb(); /* drain writebuffer */
while (__raw_readl(AC97_STAT(pscdata)) & AC97STAT_BUSY(stype))
asm volatile ("nop");
__raw_writel(AC97PCR_CLRFIFO(stype), AC97_PCR(pscdata));
wmb(); /* drain writebuffer */
break;
default:
ret = -EINVAL;
}
return ret;
}
static int au1xpsc_ac97_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct au1xpsc_audio_data *pscdata = snd_soc_dai_get_drvdata(dai);
snd_soc_dai_set_dma_data(dai, substream, &pscdata->dmaids[0]);
return 0;
}
static int au1xpsc_ac97_probe(struct snd_soc_dai *dai)
{
return au1xpsc_ac97_workdata ? 0 : -ENODEV;
}
static const struct snd_soc_dai_ops au1xpsc_ac97_dai_ops = {
.probe = au1xpsc_ac97_probe,
.startup = au1xpsc_ac97_startup,
.trigger = au1xpsc_ac97_trigger,
.hw_params = au1xpsc_ac97_hw_params,
};
static const struct snd_soc_dai_driver au1xpsc_ac97_dai_template = {
.playback = {
.rates = AC97_RATES,
.formats = AC97_FMTS,
.channels_min = 2,
.channels_max = 2,
},
.capture = {
.rates = AC97_RATES,
.formats = AC97_FMTS,
.channels_min = 2,
.channels_max = 2,
},
.ops = &au1xpsc_ac97_dai_ops,
};
static const struct snd_soc_component_driver au1xpsc_ac97_component = {
.name = "au1xpsc-ac97",
.legacy_dai_naming = 1,
};
static int au1xpsc_ac97_drvprobe(struct platform_device *pdev)
{
int ret;
struct resource *dmares;
unsigned long sel;
struct au1xpsc_audio_data *wd;
wd = devm_kzalloc(&pdev->dev, sizeof(struct au1xpsc_audio_data),
GFP_KERNEL);
if (!wd)
return -ENOMEM;
mutex_init(&wd->lock);
wd->mmio = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(wd->mmio))
return PTR_ERR(wd->mmio);
dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
if (!dmares)
return -EBUSY;
wd->dmaids[SNDRV_PCM_STREAM_PLAYBACK] = dmares->start;
dmares = platform_get_resource(pdev, IORESOURCE_DMA, 1);
if (!dmares)
return -EBUSY;
wd->dmaids[SNDRV_PCM_STREAM_CAPTURE] = dmares->start;
/* configuration: max dma trigger threshold, enable ac97 */
wd->cfg = PSC_AC97CFG_RT_FIFO8 | PSC_AC97CFG_TT_FIFO8 |
PSC_AC97CFG_DE_ENABLE;
/* preserve PSC clock source set up by platform */
sel = __raw_readl(PSC_SEL(wd)) & PSC_SEL_CLK_MASK;
__raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
wmb(); /* drain writebuffer */
__raw_writel(0, PSC_SEL(wd));
wmb(); /* drain writebuffer */
__raw_writel(PSC_SEL_PS_AC97MODE | sel, PSC_SEL(wd));
wmb(); /* drain writebuffer */
/* name the DAI like this device instance ("au1xpsc-ac97.PSCINDEX") */
memcpy(&wd->dai_drv, &au1xpsc_ac97_dai_template,
sizeof(struct snd_soc_dai_driver));
wd->dai_drv.name = dev_name(&pdev->dev);
platform_set_drvdata(pdev, wd);
ret = snd_soc_set_ac97_ops(&psc_ac97_ops);
if (ret)
return ret;
ret = snd_soc_register_component(&pdev->dev, &au1xpsc_ac97_component,
&wd->dai_drv, 1);
if (ret)
return ret;
au1xpsc_ac97_workdata = wd;
return 0;
}
static void au1xpsc_ac97_drvremove(struct platform_device *pdev)
{
struct au1xpsc_audio_data *wd = platform_get_drvdata(pdev);
snd_soc_unregister_component(&pdev->dev);
/* disable PSC completely */
__raw_writel(0, AC97_CFG(wd));
wmb(); /* drain writebuffer */
__raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
wmb(); /* drain writebuffer */
au1xpsc_ac97_workdata = NULL; /* MDEV */
}
#ifdef CONFIG_PM
static int au1xpsc_ac97_drvsuspend(struct device *dev)
{
struct au1xpsc_audio_data *wd = dev_get_drvdata(dev);
/* save interesting registers and disable PSC */
wd->pm[0] = __raw_readl(PSC_SEL(wd));
__raw_writel(0, AC97_CFG(wd));
wmb(); /* drain writebuffer */
__raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
wmb(); /* drain writebuffer */
return 0;
}
static int au1xpsc_ac97_drvresume(struct device *dev)
{
struct au1xpsc_audio_data *wd = dev_get_drvdata(dev);
/* restore PSC clock config */
__raw_writel(wd->pm[0] | PSC_SEL_PS_AC97MODE, PSC_SEL(wd));
wmb(); /* drain writebuffer */
/* after this point the ac97 core will cold-reset the codec.
* During cold-reset the PSC is reinitialized and the last
* configuration set up in hw_params() is restored.
*/
return 0;
}
static const struct dev_pm_ops au1xpscac97_pmops = {
.suspend = au1xpsc_ac97_drvsuspend,
.resume = au1xpsc_ac97_drvresume,
};
#define AU1XPSCAC97_PMOPS &au1xpscac97_pmops
#else
#define AU1XPSCAC97_PMOPS NULL
#endif
static struct platform_driver au1xpsc_ac97_driver = {
.driver = {
.name = "au1xpsc_ac97",
.pm = AU1XPSCAC97_PMOPS,
},
.probe = au1xpsc_ac97_drvprobe,
.remove_new = au1xpsc_ac97_drvremove,
};
module_platform_driver(au1xpsc_ac97_driver);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Au12x0/Au1550 PSC AC97 ALSA ASoC audio driver");
MODULE_AUTHOR("Manuel Lauss");
| linux-master | sound/soc/au1x/psc-ac97.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Au1000/Au1500/Au1100 I2S controller driver for ASoC
*
* (c) 2011 Manuel Lauss <[email protected]>
*
* Note: clock supplied to the I2S controller must be 256x samplerate.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/suspend.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/initval.h>
#include <sound/soc.h>
#include <asm/mach-au1x00/au1000.h>
#include "psc.h"
#define I2S_RXTX 0x00
#define I2S_CFG 0x04
#define I2S_ENABLE 0x08
#define CFG_XU (1 << 25) /* tx underflow */
#define CFG_XO (1 << 24)
#define CFG_RU (1 << 23)
#define CFG_RO (1 << 22)
#define CFG_TR (1 << 21)
#define CFG_TE (1 << 20)
#define CFG_TF (1 << 19)
#define CFG_RR (1 << 18)
#define CFG_RF (1 << 17)
#define CFG_ICK (1 << 12) /* clock invert */
#define CFG_PD (1 << 11) /* set to make I2SDIO INPUT */
#define CFG_LB (1 << 10) /* loopback */
#define CFG_IC (1 << 9) /* word select invert */
#define CFG_FM_I2S (0 << 7) /* I2S format */
#define CFG_FM_LJ (1 << 7) /* left-justified */
#define CFG_FM_RJ (2 << 7) /* right-justified */
#define CFG_FM_MASK (3 << 7)
#define CFG_TN (1 << 6) /* tx fifo en */
#define CFG_RN (1 << 5) /* rx fifo en */
#define CFG_SZ_8 (0x08)
#define CFG_SZ_16 (0x10)
#define CFG_SZ_18 (0x12)
#define CFG_SZ_20 (0x14)
#define CFG_SZ_24 (0x18)
#define CFG_SZ_MASK (0x1f)
#define EN_D (1 << 1) /* DISable */
#define EN_CE (1 << 0) /* clock enable */
/* only limited by clock generator and board design */
#define AU1XI2SC_RATES \
SNDRV_PCM_RATE_CONTINUOUS
#define AU1XI2SC_FMTS \
(SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 | \
SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE | \
SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE | \
SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_U18_3LE | \
SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_U18_3BE | \
SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_U20_3LE | \
SNDRV_PCM_FMTBIT_S20_3BE | SNDRV_PCM_FMTBIT_U20_3BE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE | \
SNDRV_PCM_FMTBIT_U24_LE | SNDRV_PCM_FMTBIT_U24_BE | \
0)
static inline unsigned long RD(struct au1xpsc_audio_data *ctx, int reg)
{
return __raw_readl(ctx->mmio + reg);
}
static inline void WR(struct au1xpsc_audio_data *ctx, int reg, unsigned long v)
{
__raw_writel(v, ctx->mmio + reg);
wmb();
}
static int au1xi2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
{
struct au1xpsc_audio_data *ctx = snd_soc_dai_get_drvdata(cpu_dai);
unsigned long c;
int ret;
ret = -EINVAL;
c = ctx->cfg;
c &= ~CFG_FM_MASK;
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
c |= CFG_FM_I2S;
break;
case SND_SOC_DAIFMT_MSB:
c |= CFG_FM_RJ;
break;
case SND_SOC_DAIFMT_LSB:
c |= CFG_FM_LJ;
break;
default:
goto out;
}
c &= ~(CFG_IC | CFG_ICK); /* IB-IF */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
c |= CFG_IC | CFG_ICK;
break;
case SND_SOC_DAIFMT_NB_IF:
c |= CFG_IC;
break;
case SND_SOC_DAIFMT_IB_NF:
c |= CFG_ICK;
break;
case SND_SOC_DAIFMT_IB_IF:
break;
default:
goto out;
}
/* I2S controller only supports provider */
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BP_FP: /* CODEC consumer */
break;
default:
goto out;
}
ret = 0;
ctx->cfg = c;
out:
return ret;
}
static int au1xi2s_trigger(struct snd_pcm_substream *substream,
int cmd, struct snd_soc_dai *dai)
{
struct au1xpsc_audio_data *ctx = snd_soc_dai_get_drvdata(dai);
int stype = SUBSTREAM_TYPE(substream);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
/* power up */
WR(ctx, I2S_ENABLE, EN_D | EN_CE);
WR(ctx, I2S_ENABLE, EN_CE);
ctx->cfg |= (stype == PCM_TX) ? CFG_TN : CFG_RN;
WR(ctx, I2S_CFG, ctx->cfg);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
ctx->cfg &= ~((stype == PCM_TX) ? CFG_TN : CFG_RN);
WR(ctx, I2S_CFG, ctx->cfg);
WR(ctx, I2S_ENABLE, EN_D); /* power off */
break;
default:
return -EINVAL;
}
return 0;
}
static unsigned long msbits_to_reg(int msbits)
{
switch (msbits) {
case 8:
return CFG_SZ_8;
case 16:
return CFG_SZ_16;
case 18:
return CFG_SZ_18;
case 20:
return CFG_SZ_20;
case 24:
return CFG_SZ_24;
}
return 0;
}
static int au1xi2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct au1xpsc_audio_data *ctx = snd_soc_dai_get_drvdata(dai);
unsigned long v;
v = msbits_to_reg(params->msbits);
if (!v)
return -EINVAL;
ctx->cfg &= ~CFG_SZ_MASK;
ctx->cfg |= v;
return 0;
}
static int au1xi2s_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct au1xpsc_audio_data *ctx = snd_soc_dai_get_drvdata(dai);
snd_soc_dai_set_dma_data(dai, substream, &ctx->dmaids[0]);
return 0;
}
static const struct snd_soc_dai_ops au1xi2s_dai_ops = {
.startup = au1xi2s_startup,
.trigger = au1xi2s_trigger,
.hw_params = au1xi2s_hw_params,
.set_fmt = au1xi2s_set_fmt,
};
static struct snd_soc_dai_driver au1xi2s_dai_driver = {
.symmetric_rate = 1,
.playback = {
.rates = AU1XI2SC_RATES,
.formats = AU1XI2SC_FMTS,
.channels_min = 2,
.channels_max = 2,
},
.capture = {
.rates = AU1XI2SC_RATES,
.formats = AU1XI2SC_FMTS,
.channels_min = 2,
.channels_max = 2,
},
.ops = &au1xi2s_dai_ops,
};
static const struct snd_soc_component_driver au1xi2s_component = {
.name = "au1xi2s",
.legacy_dai_naming = 1,
};
static int au1xi2s_drvprobe(struct platform_device *pdev)
{
struct resource *iores, *dmares;
struct au1xpsc_audio_data *ctx;
ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
if (!ctx)
return -ENOMEM;
iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!iores)
return -ENODEV;
if (!devm_request_mem_region(&pdev->dev, iores->start,
resource_size(iores),
pdev->name))
return -EBUSY;
ctx->mmio = devm_ioremap(&pdev->dev, iores->start,
resource_size(iores));
if (!ctx->mmio)
return -EBUSY;
dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
if (!dmares)
return -EBUSY;
ctx->dmaids[SNDRV_PCM_STREAM_PLAYBACK] = dmares->start;
dmares = platform_get_resource(pdev, IORESOURCE_DMA, 1);
if (!dmares)
return -EBUSY;
ctx->dmaids[SNDRV_PCM_STREAM_CAPTURE] = dmares->start;
platform_set_drvdata(pdev, ctx);
return snd_soc_register_component(&pdev->dev, &au1xi2s_component,
&au1xi2s_dai_driver, 1);
}
static void au1xi2s_drvremove(struct platform_device *pdev)
{
struct au1xpsc_audio_data *ctx = platform_get_drvdata(pdev);
snd_soc_unregister_component(&pdev->dev);
WR(ctx, I2S_ENABLE, EN_D); /* clock off, disable */
}
#ifdef CONFIG_PM
static int au1xi2s_drvsuspend(struct device *dev)
{
struct au1xpsc_audio_data *ctx = dev_get_drvdata(dev);
WR(ctx, I2S_ENABLE, EN_D); /* clock off, disable */
return 0;
}
static int au1xi2s_drvresume(struct device *dev)
{
return 0;
}
static const struct dev_pm_ops au1xi2sc_pmops = {
.suspend = au1xi2s_drvsuspend,
.resume = au1xi2s_drvresume,
};
#define AU1XI2SC_PMOPS (&au1xi2sc_pmops)
#else
#define AU1XI2SC_PMOPS NULL
#endif
static struct platform_driver au1xi2s_driver = {
.driver = {
.name = "alchemy-i2sc",
.pm = AU1XI2SC_PMOPS,
},
.probe = au1xi2s_drvprobe,
.remove_new = au1xi2s_drvremove,
};
module_platform_driver(au1xi2s_driver);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Au1000/1500/1100 I2S ASoC driver");
MODULE_AUTHOR("Manuel Lauss");
| linux-master | sound/soc/au1x/i2sc.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Au12x0/Au1550 PSC ALSA ASoC audio support.
*
* (c) 2007-2008 MSC Vertriebsges.m.b.H.,
* Manuel Lauss <[email protected]>
*
* Au1xxx-PSC I2S glue.
*
* NOTE: so far only PSC slave mode (bit- and frameclock) is supported.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/suspend.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/initval.h>
#include <sound/soc.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/au1xxx_psc.h>
#include "psc.h"
/* supported I2S DAI hardware formats */
#define AU1XPSC_I2S_DAIFMT \
(SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_LEFT_J | \
SND_SOC_DAIFMT_NB_NF)
/* supported I2S direction */
#define AU1XPSC_I2S_DIR \
(SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE)
#define AU1XPSC_I2S_RATES \
SNDRV_PCM_RATE_8000_192000
#define AU1XPSC_I2S_FMTS \
(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
#define I2SSTAT_BUSY(stype) \
((stype) == SNDRV_PCM_STREAM_PLAYBACK ? PSC_I2SSTAT_TB : PSC_I2SSTAT_RB)
#define I2SPCR_START(stype) \
((stype) == SNDRV_PCM_STREAM_PLAYBACK ? PSC_I2SPCR_TS : PSC_I2SPCR_RS)
#define I2SPCR_STOP(stype) \
((stype) == SNDRV_PCM_STREAM_PLAYBACK ? PSC_I2SPCR_TP : PSC_I2SPCR_RP)
#define I2SPCR_CLRFIFO(stype) \
((stype) == SNDRV_PCM_STREAM_PLAYBACK ? PSC_I2SPCR_TC : PSC_I2SPCR_RC)
static int au1xpsc_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
unsigned int fmt)
{
struct au1xpsc_audio_data *pscdata = snd_soc_dai_get_drvdata(cpu_dai);
unsigned long ct;
int ret;
ret = -EINVAL;
ct = pscdata->cfg;
ct &= ~(PSC_I2SCFG_XM | PSC_I2SCFG_MLJ); /* left-justified */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
ct |= PSC_I2SCFG_XM; /* enable I2S mode */
break;
case SND_SOC_DAIFMT_MSB:
break;
case SND_SOC_DAIFMT_LSB:
ct |= PSC_I2SCFG_MLJ; /* LSB (right-) justified */
break;
default:
goto out;
}
ct &= ~(PSC_I2SCFG_BI | PSC_I2SCFG_WI); /* IB-IF */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
ct |= PSC_I2SCFG_BI | PSC_I2SCFG_WI;
break;
case SND_SOC_DAIFMT_NB_IF:
ct |= PSC_I2SCFG_BI;
break;
case SND_SOC_DAIFMT_IB_NF:
ct |= PSC_I2SCFG_WI;
break;
case SND_SOC_DAIFMT_IB_IF:
break;
default:
goto out;
}
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BC_FC: /* CODEC provider */
ct |= PSC_I2SCFG_MS; /* PSC I2S consumer mode */
break;
case SND_SOC_DAIFMT_BP_FP: /* CODEC consumer */
ct &= ~PSC_I2SCFG_MS; /* PSC I2S provider mode */
break;
default:
goto out;
}
pscdata->cfg = ct;
ret = 0;
out:
return ret;
}
static int au1xpsc_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct au1xpsc_audio_data *pscdata = snd_soc_dai_get_drvdata(dai);
int cfgbits;
unsigned long stat;
/* check if the PSC is already streaming data */
stat = __raw_readl(I2S_STAT(pscdata));
if (stat & (PSC_I2SSTAT_TB | PSC_I2SSTAT_RB)) {
/* reject parameters not currently set up in hardware */
cfgbits = __raw_readl(I2S_CFG(pscdata));
if ((PSC_I2SCFG_GET_LEN(cfgbits) != params->msbits) ||
(params_rate(params) != pscdata->rate))
return -EINVAL;
} else {
/* set sample bitdepth */
pscdata->cfg &= ~(0x1f << 4);
pscdata->cfg |= PSC_I2SCFG_SET_LEN(params->msbits);
/* remember current rate for other stream */
pscdata->rate = params_rate(params);
}
return 0;
}
/* Configure PSC late: on my devel systems the codec is I2S master and
* supplies the i2sbitclock __AND__ i2sMclk (!) to the PSC unit. ASoC
* uses aggressive PM and switches the codec off when it is not in use
* which also means the PSC unit doesn't get any clocks and is therefore
* dead. That's why this chunk here gets called from the trigger callback
* because I can be reasonably certain the codec is driving the clocks.
*/
static int au1xpsc_i2s_configure(struct au1xpsc_audio_data *pscdata)
{
unsigned long tmo;
/* bring PSC out of sleep, and configure I2S unit */
__raw_writel(PSC_CTRL_ENABLE, PSC_CTRL(pscdata));
wmb(); /* drain writebuffer */
tmo = 1000000;
while (!(__raw_readl(I2S_STAT(pscdata)) & PSC_I2SSTAT_SR) && tmo)
tmo--;
if (!tmo)
goto psc_err;
__raw_writel(0, I2S_CFG(pscdata));
wmb(); /* drain writebuffer */
__raw_writel(pscdata->cfg | PSC_I2SCFG_DE_ENABLE, I2S_CFG(pscdata));
wmb(); /* drain writebuffer */
/* wait for I2S controller to become ready */
tmo = 1000000;
while (!(__raw_readl(I2S_STAT(pscdata)) & PSC_I2SSTAT_DR) && tmo)
tmo--;
if (tmo)
return 0;
psc_err:
__raw_writel(0, I2S_CFG(pscdata));
__raw_writel(PSC_CTRL_SUSPEND, PSC_CTRL(pscdata));
wmb(); /* drain writebuffer */
return -ETIMEDOUT;
}
static int au1xpsc_i2s_start(struct au1xpsc_audio_data *pscdata, int stype)
{
unsigned long tmo, stat;
int ret;
ret = 0;
/* if both TX and RX are idle, configure the PSC */
stat = __raw_readl(I2S_STAT(pscdata));
if (!(stat & (PSC_I2SSTAT_TB | PSC_I2SSTAT_RB))) {
ret = au1xpsc_i2s_configure(pscdata);
if (ret)
goto out;
}
__raw_writel(I2SPCR_CLRFIFO(stype), I2S_PCR(pscdata));
wmb(); /* drain writebuffer */
__raw_writel(I2SPCR_START(stype), I2S_PCR(pscdata));
wmb(); /* drain writebuffer */
/* wait for start confirmation */
tmo = 1000000;
while (!(__raw_readl(I2S_STAT(pscdata)) & I2SSTAT_BUSY(stype)) && tmo)
tmo--;
if (!tmo) {
__raw_writel(I2SPCR_STOP(stype), I2S_PCR(pscdata));
wmb(); /* drain writebuffer */
ret = -ETIMEDOUT;
}
out:
return ret;
}
static int au1xpsc_i2s_stop(struct au1xpsc_audio_data *pscdata, int stype)
{
unsigned long tmo, stat;
__raw_writel(I2SPCR_STOP(stype), I2S_PCR(pscdata));
wmb(); /* drain writebuffer */
/* wait for stop confirmation */
tmo = 1000000;
while ((__raw_readl(I2S_STAT(pscdata)) & I2SSTAT_BUSY(stype)) && tmo)
tmo--;
/* if both TX and RX are idle, disable PSC */
stat = __raw_readl(I2S_STAT(pscdata));
if (!(stat & (PSC_I2SSTAT_TB | PSC_I2SSTAT_RB))) {
__raw_writel(0, I2S_CFG(pscdata));
wmb(); /* drain writebuffer */
__raw_writel(PSC_CTRL_SUSPEND, PSC_CTRL(pscdata));
wmb(); /* drain writebuffer */
}
return 0;
}
static int au1xpsc_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct au1xpsc_audio_data *pscdata = snd_soc_dai_get_drvdata(dai);
int ret, stype = substream->stream;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
ret = au1xpsc_i2s_start(pscdata, stype);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
ret = au1xpsc_i2s_stop(pscdata, stype);
break;
default:
ret = -EINVAL;
}
return ret;
}
static int au1xpsc_i2s_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct au1xpsc_audio_data *pscdata = snd_soc_dai_get_drvdata(dai);
snd_soc_dai_set_dma_data(dai, substream, &pscdata->dmaids[0]);
return 0;
}
static const struct snd_soc_dai_ops au1xpsc_i2s_dai_ops = {
.startup = au1xpsc_i2s_startup,
.trigger = au1xpsc_i2s_trigger,
.hw_params = au1xpsc_i2s_hw_params,
.set_fmt = au1xpsc_i2s_set_fmt,
};
static const struct snd_soc_dai_driver au1xpsc_i2s_dai_template = {
.playback = {
.rates = AU1XPSC_I2S_RATES,
.formats = AU1XPSC_I2S_FMTS,
.channels_min = 2,
.channels_max = 8, /* 2 without external help */
},
.capture = {
.rates = AU1XPSC_I2S_RATES,
.formats = AU1XPSC_I2S_FMTS,
.channels_min = 2,
.channels_max = 8, /* 2 without external help */
},
.ops = &au1xpsc_i2s_dai_ops,
};
static const struct snd_soc_component_driver au1xpsc_i2s_component = {
.name = "au1xpsc-i2s",
.legacy_dai_naming = 1,
};
static int au1xpsc_i2s_drvprobe(struct platform_device *pdev)
{
struct resource *dmares;
unsigned long sel;
struct au1xpsc_audio_data *wd;
wd = devm_kzalloc(&pdev->dev, sizeof(struct au1xpsc_audio_data),
GFP_KERNEL);
if (!wd)
return -ENOMEM;
wd->mmio = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(wd->mmio))
return PTR_ERR(wd->mmio);
dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
if (!dmares)
return -EBUSY;
wd->dmaids[SNDRV_PCM_STREAM_PLAYBACK] = dmares->start;
dmares = platform_get_resource(pdev, IORESOURCE_DMA, 1);
if (!dmares)
return -EBUSY;
wd->dmaids[SNDRV_PCM_STREAM_CAPTURE] = dmares->start;
/* preserve PSC clock source set up by platform (dev.platform_data
* is already occupied by soc layer)
*/
sel = __raw_readl(PSC_SEL(wd)) & PSC_SEL_CLK_MASK;
__raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
wmb(); /* drain writebuffer */
__raw_writel(PSC_SEL_PS_I2SMODE | sel, PSC_SEL(wd));
__raw_writel(0, I2S_CFG(wd));
wmb(); /* drain writebuffer */
/* preconfigure: set max rx/tx fifo depths */
wd->cfg |= PSC_I2SCFG_RT_FIFO8 | PSC_I2SCFG_TT_FIFO8;
/* don't wait for I2S core to become ready now; clocks may not
* be running yet; depending on clock input for PSC a wait might
* time out.
*/
/* name the DAI like this device instance ("au1xpsc-i2s.PSCINDEX") */
memcpy(&wd->dai_drv, &au1xpsc_i2s_dai_template,
sizeof(struct snd_soc_dai_driver));
wd->dai_drv.name = dev_name(&pdev->dev);
platform_set_drvdata(pdev, wd);
return devm_snd_soc_register_component(&pdev->dev,
&au1xpsc_i2s_component, &wd->dai_drv, 1);
}
static void au1xpsc_i2s_drvremove(struct platform_device *pdev)
{
struct au1xpsc_audio_data *wd = platform_get_drvdata(pdev);
__raw_writel(0, I2S_CFG(wd));
wmb(); /* drain writebuffer */
__raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
wmb(); /* drain writebuffer */
}
#ifdef CONFIG_PM
static int au1xpsc_i2s_drvsuspend(struct device *dev)
{
struct au1xpsc_audio_data *wd = dev_get_drvdata(dev);
/* save interesting register and disable PSC */
wd->pm[0] = __raw_readl(PSC_SEL(wd));
__raw_writel(0, I2S_CFG(wd));
wmb(); /* drain writebuffer */
__raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
wmb(); /* drain writebuffer */
return 0;
}
static int au1xpsc_i2s_drvresume(struct device *dev)
{
struct au1xpsc_audio_data *wd = dev_get_drvdata(dev);
/* select I2S mode and PSC clock */
__raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd));
wmb(); /* drain writebuffer */
__raw_writel(0, PSC_SEL(wd));
wmb(); /* drain writebuffer */
__raw_writel(wd->pm[0], PSC_SEL(wd));
wmb(); /* drain writebuffer */
return 0;
}
static const struct dev_pm_ops au1xpsci2s_pmops = {
.suspend = au1xpsc_i2s_drvsuspend,
.resume = au1xpsc_i2s_drvresume,
};
#define AU1XPSCI2S_PMOPS &au1xpsci2s_pmops
#else
#define AU1XPSCI2S_PMOPS NULL
#endif
static struct platform_driver au1xpsc_i2s_driver = {
.driver = {
.name = "au1xpsc_i2s",
.pm = AU1XPSCI2S_PMOPS,
},
.probe = au1xpsc_i2s_drvprobe,
.remove_new = au1xpsc_i2s_drvremove,
};
module_platform_driver(au1xpsc_i2s_driver);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Au12x0/Au1550 PSC I2S ALSA ASoC audio driver");
MODULE_AUTHOR("Manuel Lauss");
| linux-master | sound/soc/au1x/psc-i2s.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Au1000/Au1500/Au1100 AC97C controller driver for ASoC
*
* (c) 2011 Manuel Lauss <[email protected]>
*
* based on the old ALSA driver originally written by
* Charles Eidsness <[email protected]>
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/mutex.h>
#include <linux/platform_device.h>
#include <linux/suspend.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/initval.h>
#include <sound/soc.h>
#include <asm/mach-au1x00/au1000.h>
#include "psc.h"
/* register offsets and bits */
#define AC97_CONFIG 0x00
#define AC97_STATUS 0x04
#define AC97_DATA 0x08
#define AC97_CMDRESP 0x0c
#define AC97_ENABLE 0x10
#define CFG_RC(x) (((x) & 0x3ff) << 13) /* valid rx slots mask */
#define CFG_XS(x) (((x) & 0x3ff) << 3) /* valid tx slots mask */
#define CFG_SG (1 << 2) /* sync gate */
#define CFG_SN (1 << 1) /* sync control */
#define CFG_RS (1 << 0) /* acrst# control */
#define STAT_XU (1 << 11) /* tx underflow */
#define STAT_XO (1 << 10) /* tx overflow */
#define STAT_RU (1 << 9) /* rx underflow */
#define STAT_RO (1 << 8) /* rx overflow */
#define STAT_RD (1 << 7) /* codec ready */
#define STAT_CP (1 << 6) /* command pending */
#define STAT_TE (1 << 4) /* tx fifo empty */
#define STAT_TF (1 << 3) /* tx fifo full */
#define STAT_RE (1 << 1) /* rx fifo empty */
#define STAT_RF (1 << 0) /* rx fifo full */
#define CMD_SET_DATA(x) (((x) & 0xffff) << 16)
#define CMD_GET_DATA(x) ((x) & 0xffff)
#define CMD_READ (1 << 7)
#define CMD_WRITE (0 << 7)
#define CMD_IDX(x) ((x) & 0x7f)
#define EN_D (1 << 1) /* DISable bit */
#define EN_CE (1 << 0) /* clock enable bit */
/* how often to retry failed codec register reads/writes */
#define AC97_RW_RETRIES 5
#define AC97_RATES \
SNDRV_PCM_RATE_CONTINUOUS
#define AC97_FMTS \
(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE)
/* instance data. There can be only one, MacLeod!!!!, fortunately there IS only
* once AC97C on early Alchemy chips. The newer ones aren't so lucky.
*/
static struct au1xpsc_audio_data *ac97c_workdata;
#define ac97_to_ctx(x) ac97c_workdata
static inline unsigned long RD(struct au1xpsc_audio_data *ctx, int reg)
{
return __raw_readl(ctx->mmio + reg);
}
static inline void WR(struct au1xpsc_audio_data *ctx, int reg, unsigned long v)
{
__raw_writel(v, ctx->mmio + reg);
wmb();
}
static unsigned short au1xac97c_ac97_read(struct snd_ac97 *ac97,
unsigned short r)
{
struct au1xpsc_audio_data *ctx = ac97_to_ctx(ac97);
unsigned int tmo, retry;
unsigned long data;
data = ~0;
retry = AC97_RW_RETRIES;
do {
mutex_lock(&ctx->lock);
tmo = 6;
while ((RD(ctx, AC97_STATUS) & STAT_CP) && --tmo)
udelay(21); /* wait an ac97 frame time */
if (!tmo) {
pr_debug("ac97rd timeout #1\n");
goto next;
}
WR(ctx, AC97_CMDRESP, CMD_IDX(r) | CMD_READ);
/* stupid errata: data is only valid for 21us, so
* poll, Forrest, poll...
*/
tmo = 0x10000;
while ((RD(ctx, AC97_STATUS) & STAT_CP) && --tmo)
asm volatile ("nop");
data = RD(ctx, AC97_CMDRESP);
if (!tmo)
pr_debug("ac97rd timeout #2\n");
next:
mutex_unlock(&ctx->lock);
} while (--retry && !tmo);
pr_debug("AC97RD %04x %04lx %d\n", r, data, retry);
return retry ? data & 0xffff : 0xffff;
}
static void au1xac97c_ac97_write(struct snd_ac97 *ac97, unsigned short r,
unsigned short v)
{
struct au1xpsc_audio_data *ctx = ac97_to_ctx(ac97);
unsigned int tmo, retry;
retry = AC97_RW_RETRIES;
do {
mutex_lock(&ctx->lock);
for (tmo = 5; (RD(ctx, AC97_STATUS) & STAT_CP) && tmo; tmo--)
udelay(21);
if (!tmo) {
pr_debug("ac97wr timeout #1\n");
goto next;
}
WR(ctx, AC97_CMDRESP, CMD_WRITE | CMD_IDX(r) | CMD_SET_DATA(v));
for (tmo = 10; (RD(ctx, AC97_STATUS) & STAT_CP) && tmo; tmo--)
udelay(21);
if (!tmo)
pr_debug("ac97wr timeout #2\n");
next:
mutex_unlock(&ctx->lock);
} while (--retry && !tmo);
pr_debug("AC97WR %04x %04x %d\n", r, v, retry);
}
static void au1xac97c_ac97_warm_reset(struct snd_ac97 *ac97)
{
struct au1xpsc_audio_data *ctx = ac97_to_ctx(ac97);
WR(ctx, AC97_CONFIG, ctx->cfg | CFG_SG | CFG_SN);
msleep(20);
WR(ctx, AC97_CONFIG, ctx->cfg | CFG_SG);
WR(ctx, AC97_CONFIG, ctx->cfg);
}
static void au1xac97c_ac97_cold_reset(struct snd_ac97 *ac97)
{
struct au1xpsc_audio_data *ctx = ac97_to_ctx(ac97);
int i;
WR(ctx, AC97_CONFIG, ctx->cfg | CFG_RS);
msleep(500);
WR(ctx, AC97_CONFIG, ctx->cfg);
/* wait for codec ready */
i = 50;
while (((RD(ctx, AC97_STATUS) & STAT_RD) == 0) && --i)
msleep(20);
if (!i)
printk(KERN_ERR "ac97c: codec not ready after cold reset\n");
}
/* AC97 controller operations */
static struct snd_ac97_bus_ops ac97c_bus_ops = {
.read = au1xac97c_ac97_read,
.write = au1xac97c_ac97_write,
.reset = au1xac97c_ac97_cold_reset,
.warm_reset = au1xac97c_ac97_warm_reset,
};
static int alchemy_ac97c_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct au1xpsc_audio_data *ctx = snd_soc_dai_get_drvdata(dai);
snd_soc_dai_set_dma_data(dai, substream, &ctx->dmaids[0]);
return 0;
}
static int au1xac97c_dai_probe(struct snd_soc_dai *dai)
{
return ac97c_workdata ? 0 : -ENODEV;
}
static const struct snd_soc_dai_ops alchemy_ac97c_ops = {
.probe = au1xac97c_dai_probe,
.startup = alchemy_ac97c_startup,
};
static struct snd_soc_dai_driver au1xac97c_dai_driver = {
.name = "alchemy-ac97c",
.playback = {
.rates = AC97_RATES,
.formats = AC97_FMTS,
.channels_min = 2,
.channels_max = 2,
},
.capture = {
.rates = AC97_RATES,
.formats = AC97_FMTS,
.channels_min = 2,
.channels_max = 2,
},
.ops = &alchemy_ac97c_ops,
};
static const struct snd_soc_component_driver au1xac97c_component = {
.name = "au1xac97c",
.legacy_dai_naming = 1,
};
static int au1xac97c_drvprobe(struct platform_device *pdev)
{
int ret;
struct resource *iores, *dmares;
struct au1xpsc_audio_data *ctx;
ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
if (!ctx)
return -ENOMEM;
mutex_init(&ctx->lock);
iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!iores)
return -ENODEV;
if (!devm_request_mem_region(&pdev->dev, iores->start,
resource_size(iores),
pdev->name))
return -EBUSY;
ctx->mmio = devm_ioremap(&pdev->dev, iores->start,
resource_size(iores));
if (!ctx->mmio)
return -EBUSY;
dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
if (!dmares)
return -EBUSY;
ctx->dmaids[SNDRV_PCM_STREAM_PLAYBACK] = dmares->start;
dmares = platform_get_resource(pdev, IORESOURCE_DMA, 1);
if (!dmares)
return -EBUSY;
ctx->dmaids[SNDRV_PCM_STREAM_CAPTURE] = dmares->start;
/* switch it on */
WR(ctx, AC97_ENABLE, EN_D | EN_CE);
WR(ctx, AC97_ENABLE, EN_CE);
ctx->cfg = CFG_RC(3) | CFG_XS(3);
WR(ctx, AC97_CONFIG, ctx->cfg);
platform_set_drvdata(pdev, ctx);
ret = snd_soc_set_ac97_ops(&ac97c_bus_ops);
if (ret)
return ret;
ret = snd_soc_register_component(&pdev->dev, &au1xac97c_component,
&au1xac97c_dai_driver, 1);
if (ret)
return ret;
ac97c_workdata = ctx;
return 0;
}
static void au1xac97c_drvremove(struct platform_device *pdev)
{
struct au1xpsc_audio_data *ctx = platform_get_drvdata(pdev);
snd_soc_unregister_component(&pdev->dev);
WR(ctx, AC97_ENABLE, EN_D); /* clock off, disable */
ac97c_workdata = NULL; /* MDEV */
}
#ifdef CONFIG_PM
static int au1xac97c_drvsuspend(struct device *dev)
{
struct au1xpsc_audio_data *ctx = dev_get_drvdata(dev);
WR(ctx, AC97_ENABLE, EN_D); /* clock off, disable */
return 0;
}
static int au1xac97c_drvresume(struct device *dev)
{
struct au1xpsc_audio_data *ctx = dev_get_drvdata(dev);
WR(ctx, AC97_ENABLE, EN_D | EN_CE);
WR(ctx, AC97_ENABLE, EN_CE);
WR(ctx, AC97_CONFIG, ctx->cfg);
return 0;
}
static const struct dev_pm_ops au1xpscac97_pmops = {
.suspend = au1xac97c_drvsuspend,
.resume = au1xac97c_drvresume,
};
#define AU1XPSCAC97_PMOPS (&au1xpscac97_pmops)
#else
#define AU1XPSCAC97_PMOPS NULL
#endif
static struct platform_driver au1xac97c_driver = {
.driver = {
.name = "alchemy-ac97c",
.pm = AU1XPSCAC97_PMOPS,
},
.probe = au1xac97c_drvprobe,
.remove_new = au1xac97c_drvremove,
};
module_platform_driver(au1xac97c_driver);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Au1000/1500/1100 AC97C ASoC driver");
MODULE_AUTHOR("Manuel Lauss");
| linux-master | sound/soc/au1x/ac97c.c |
// SPDX-License-Identifier: GPL-2.0
//
// Freescale S/PDIF ALSA SoC Digital Audio Interface (DAI) driver
//
// Copyright (C) 2013 Freescale Semiconductor, Inc.
//
// Based on stmp3xxx_spdif_dai.c
// Vladimir Barinov <[email protected]>
// Copyright 2008 SigmaTel, Inc
// Copyright 2008 Embedded Alley Solutions, Inc
#include <linux/bitrev.h>
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/regmap.h>
#include <linux/pm_runtime.h>
#include <sound/asoundef.h>
#include <sound/dmaengine_pcm.h>
#include <sound/soc.h>
#include "fsl_spdif.h"
#include "fsl_utils.h"
#include "imx-pcm.h"
#define FSL_SPDIF_TXFIFO_WML 0x8
#define FSL_SPDIF_RXFIFO_WML 0x8
#define INTR_FOR_PLAYBACK (INT_TXFIFO_RESYNC)
#define INTR_FOR_CAPTURE (INT_SYM_ERR | INT_BIT_ERR | INT_URX_FUL |\
INT_URX_OV | INT_QRX_FUL | INT_QRX_OV |\
INT_UQ_SYNC | INT_UQ_ERR | INT_RXFIFO_RESYNC |\
INT_LOSS_LOCK | INT_DPLL_LOCKED)
#define SIE_INTR_FOR(tx) (tx ? INTR_FOR_PLAYBACK : INTR_FOR_CAPTURE)
/* Index list for the values that has if (DPLL Locked) condition */
static u8 srpc_dpll_locked[] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0xa, 0xb };
#define SRPC_NODPLL_START1 0x5
#define SRPC_NODPLL_START2 0xc
#define DEFAULT_RXCLK_SRC 1
#define RX_SAMPLE_RATE_KCONTROL "RX Sample Rate"
/**
* struct fsl_spdif_soc_data: soc specific data
*
* @imx: for imx platform
* @shared_root_clock: flag of sharing a clock source with others;
* so the driver shouldn't set root clock rate
* @raw_capture_mode: if raw capture mode support
* @cchannel_192b: if there are registers for 192bits C channel data
* @interrupts: interrupt number
* @tx_burst: tx maxburst size
* @rx_burst: rx maxburst size
* @tx_formats: tx supported data format
*/
struct fsl_spdif_soc_data {
bool imx;
bool shared_root_clock;
bool raw_capture_mode;
bool cchannel_192b;
u32 interrupts;
u32 tx_burst;
u32 rx_burst;
u64 tx_formats;
};
/*
* SPDIF control structure
* Defines channel status, subcode and Q sub
*/
struct spdif_mixer_control {
/* spinlock to access control data */
spinlock_t ctl_lock;
/* IEC958 channel tx status bit */
unsigned char ch_status[4];
/* User bits */
unsigned char subcode[2 * SPDIF_UBITS_SIZE];
/* Q subcode part of user bits */
unsigned char qsub[2 * SPDIF_QSUB_SIZE];
/* Buffer offset for U/Q */
u32 upos;
u32 qpos;
/* Ready buffer index of the two buffers */
u32 ready_buf;
};
/**
* struct fsl_spdif_priv - Freescale SPDIF private data
* @soc: SPDIF soc data
* @fsl_spdif_control: SPDIF control data
* @cpu_dai_drv: cpu dai driver
* @snd_card: sound card pointer
* @rxrate_kcontrol: kcontrol for RX Sample Rate
* @pdev: platform device pointer
* @regmap: regmap handler
* @dpll_locked: dpll lock flag
* @txrate: the best rates for playback
* @txclk_df: STC_TXCLK_DF dividers value for playback
* @sysclk_df: STC_SYSCLK_DF dividers value for playback
* @txclk_src: STC_TXCLK_SRC values for playback
* @rxclk_src: SRPC_CLKSRC_SEL values for capture
* @txclk: tx clock sources for playback
* @rxclk: rx clock sources for capture
* @coreclk: core clock for register access via DMA
* @sysclk: system clock for rx clock rate measurement
* @spbaclk: SPBA clock (optional, depending on SoC design)
* @dma_params_tx: DMA parameters for transmit channel
* @dma_params_rx: DMA parameters for receive channel
* @regcache_srpc: regcache for SRPC
* @bypass: status of bypass input to output
* @pll8k_clk: PLL clock for the rate of multiply of 8kHz
* @pll11k_clk: PLL clock for the rate of multiply of 11kHz
*/
struct fsl_spdif_priv {
const struct fsl_spdif_soc_data *soc;
struct spdif_mixer_control fsl_spdif_control;
struct snd_soc_dai_driver cpu_dai_drv;
struct snd_card *snd_card;
struct snd_kcontrol *rxrate_kcontrol;
struct platform_device *pdev;
struct regmap *regmap;
bool dpll_locked;
u32 txrate[SPDIF_TXRATE_MAX];
u8 txclk_df[SPDIF_TXRATE_MAX];
u16 sysclk_df[SPDIF_TXRATE_MAX];
u8 txclk_src[SPDIF_TXRATE_MAX];
u8 rxclk_src;
struct clk *txclk[STC_TXCLK_SRC_MAX];
struct clk *rxclk;
struct clk *coreclk;
struct clk *sysclk;
struct clk *spbaclk;
struct snd_dmaengine_dai_dma_data dma_params_tx;
struct snd_dmaengine_dai_dma_data dma_params_rx;
/* regcache for SRPC */
u32 regcache_srpc;
bool bypass;
struct clk *pll8k_clk;
struct clk *pll11k_clk;
};
static struct fsl_spdif_soc_data fsl_spdif_vf610 = {
.imx = false,
.shared_root_clock = false,
.raw_capture_mode = false,
.interrupts = 1,
.tx_burst = FSL_SPDIF_TXFIFO_WML,
.rx_burst = FSL_SPDIF_RXFIFO_WML,
.tx_formats = FSL_SPDIF_FORMATS_PLAYBACK,
};
static struct fsl_spdif_soc_data fsl_spdif_imx35 = {
.imx = true,
.shared_root_clock = false,
.raw_capture_mode = false,
.interrupts = 1,
.tx_burst = FSL_SPDIF_TXFIFO_WML,
.rx_burst = FSL_SPDIF_RXFIFO_WML,
.tx_formats = FSL_SPDIF_FORMATS_PLAYBACK,
};
static struct fsl_spdif_soc_data fsl_spdif_imx6sx = {
.imx = true,
.shared_root_clock = true,
.raw_capture_mode = false,
.interrupts = 1,
.tx_burst = FSL_SPDIF_TXFIFO_WML,
.rx_burst = FSL_SPDIF_RXFIFO_WML,
.tx_formats = FSL_SPDIF_FORMATS_PLAYBACK,
};
static struct fsl_spdif_soc_data fsl_spdif_imx8qm = {
.imx = true,
.shared_root_clock = true,
.raw_capture_mode = false,
.interrupts = 2,
.tx_burst = 2, /* Applied for EDMA */
.rx_burst = 2, /* Applied for EDMA */
.tx_formats = SNDRV_PCM_FMTBIT_S24_LE, /* Applied for EDMA */
};
static struct fsl_spdif_soc_data fsl_spdif_imx8mm = {
.imx = true,
.shared_root_clock = false,
.raw_capture_mode = true,
.interrupts = 1,
.tx_burst = FSL_SPDIF_TXFIFO_WML,
.rx_burst = FSL_SPDIF_RXFIFO_WML,
.tx_formats = FSL_SPDIF_FORMATS_PLAYBACK,
};
static struct fsl_spdif_soc_data fsl_spdif_imx8ulp = {
.imx = true,
.shared_root_clock = true,
.raw_capture_mode = false,
.interrupts = 1,
.tx_burst = 2, /* Applied for EDMA */
.rx_burst = 2, /* Applied for EDMA */
.tx_formats = SNDRV_PCM_FMTBIT_S24_LE, /* Applied for EDMA */
.cchannel_192b = true,
};
/* Check if clk is a root clock that does not share clock source with others */
static inline bool fsl_spdif_can_set_clk_rate(struct fsl_spdif_priv *spdif, int clk)
{
return (clk == STC_TXCLK_SPDIF_ROOT) && !spdif->soc->shared_root_clock;
}
/* DPLL locked and lock loss interrupt handler */
static void spdif_irq_dpll_lock(struct fsl_spdif_priv *spdif_priv)
{
struct regmap *regmap = spdif_priv->regmap;
struct platform_device *pdev = spdif_priv->pdev;
u32 locked;
regmap_read(regmap, REG_SPDIF_SRPC, &locked);
locked &= SRPC_DPLL_LOCKED;
dev_dbg(&pdev->dev, "isr: Rx dpll %s \n",
locked ? "locked" : "loss lock");
spdif_priv->dpll_locked = locked ? true : false;
if (spdif_priv->snd_card && spdif_priv->rxrate_kcontrol) {
snd_ctl_notify(spdif_priv->snd_card,
SNDRV_CTL_EVENT_MASK_VALUE,
&spdif_priv->rxrate_kcontrol->id);
}
}
/* Receiver found illegal symbol interrupt handler */
static void spdif_irq_sym_error(struct fsl_spdif_priv *spdif_priv)
{
struct regmap *regmap = spdif_priv->regmap;
struct platform_device *pdev = spdif_priv->pdev;
dev_dbg(&pdev->dev, "isr: receiver found illegal symbol\n");
/* Clear illegal symbol if DPLL unlocked since no audio stream */
if (!spdif_priv->dpll_locked)
regmap_update_bits(regmap, REG_SPDIF_SIE, INT_SYM_ERR, 0);
}
/* U/Q Channel receive register full */
static void spdif_irq_uqrx_full(struct fsl_spdif_priv *spdif_priv, char name)
{
struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
struct regmap *regmap = spdif_priv->regmap;
struct platform_device *pdev = spdif_priv->pdev;
u32 *pos, size, val, reg;
switch (name) {
case 'U':
pos = &ctrl->upos;
size = SPDIF_UBITS_SIZE;
reg = REG_SPDIF_SRU;
break;
case 'Q':
pos = &ctrl->qpos;
size = SPDIF_QSUB_SIZE;
reg = REG_SPDIF_SRQ;
break;
default:
dev_err(&pdev->dev, "unsupported channel name\n");
return;
}
dev_dbg(&pdev->dev, "isr: %c Channel receive register full\n", name);
if (*pos >= size * 2) {
*pos = 0;
} else if (unlikely((*pos % size) + 3 > size)) {
dev_err(&pdev->dev, "User bit receive buffer overflow\n");
return;
}
regmap_read(regmap, reg, &val);
ctrl->subcode[*pos++] = val >> 16;
ctrl->subcode[*pos++] = val >> 8;
ctrl->subcode[*pos++] = val;
}
/* U/Q Channel sync found */
static void spdif_irq_uq_sync(struct fsl_spdif_priv *spdif_priv)
{
struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
struct platform_device *pdev = spdif_priv->pdev;
dev_dbg(&pdev->dev, "isr: U/Q Channel sync found\n");
/* U/Q buffer reset */
if (ctrl->qpos == 0)
return;
/* Set ready to this buffer */
ctrl->ready_buf = (ctrl->qpos - 1) / SPDIF_QSUB_SIZE + 1;
}
/* U/Q Channel framing error */
static void spdif_irq_uq_err(struct fsl_spdif_priv *spdif_priv)
{
struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
struct regmap *regmap = spdif_priv->regmap;
struct platform_device *pdev = spdif_priv->pdev;
u32 val;
dev_dbg(&pdev->dev, "isr: U/Q Channel framing error\n");
/* Read U/Q data to clear the irq and do buffer reset */
regmap_read(regmap, REG_SPDIF_SRU, &val);
regmap_read(regmap, REG_SPDIF_SRQ, &val);
/* Drop this U/Q buffer */
ctrl->ready_buf = 0;
ctrl->upos = 0;
ctrl->qpos = 0;
}
/* Get spdif interrupt status and clear the interrupt */
static u32 spdif_intr_status_clear(struct fsl_spdif_priv *spdif_priv)
{
struct regmap *regmap = spdif_priv->regmap;
u32 val, val2;
regmap_read(regmap, REG_SPDIF_SIS, &val);
regmap_read(regmap, REG_SPDIF_SIE, &val2);
regmap_write(regmap, REG_SPDIF_SIC, val & val2);
return val;
}
static irqreturn_t spdif_isr(int irq, void *devid)
{
struct fsl_spdif_priv *spdif_priv = (struct fsl_spdif_priv *)devid;
struct platform_device *pdev = spdif_priv->pdev;
u32 sis;
sis = spdif_intr_status_clear(spdif_priv);
if (sis & INT_DPLL_LOCKED)
spdif_irq_dpll_lock(spdif_priv);
if (sis & INT_TXFIFO_UNOV)
dev_dbg(&pdev->dev, "isr: Tx FIFO under/overrun\n");
if (sis & INT_TXFIFO_RESYNC)
dev_dbg(&pdev->dev, "isr: Tx FIFO resync\n");
if (sis & INT_CNEW)
dev_dbg(&pdev->dev, "isr: cstatus new\n");
if (sis & INT_VAL_NOGOOD)
dev_dbg(&pdev->dev, "isr: validity flag no good\n");
if (sis & INT_SYM_ERR)
spdif_irq_sym_error(spdif_priv);
if (sis & INT_BIT_ERR)
dev_dbg(&pdev->dev, "isr: receiver found parity bit error\n");
if (sis & INT_URX_FUL)
spdif_irq_uqrx_full(spdif_priv, 'U');
if (sis & INT_URX_OV)
dev_dbg(&pdev->dev, "isr: U Channel receive register overrun\n");
if (sis & INT_QRX_FUL)
spdif_irq_uqrx_full(spdif_priv, 'Q');
if (sis & INT_QRX_OV)
dev_dbg(&pdev->dev, "isr: Q Channel receive register overrun\n");
if (sis & INT_UQ_SYNC)
spdif_irq_uq_sync(spdif_priv);
if (sis & INT_UQ_ERR)
spdif_irq_uq_err(spdif_priv);
if (sis & INT_RXFIFO_UNOV)
dev_dbg(&pdev->dev, "isr: Rx FIFO under/overrun\n");
if (sis & INT_RXFIFO_RESYNC)
dev_dbg(&pdev->dev, "isr: Rx FIFO resync\n");
if (sis & INT_LOSS_LOCK)
spdif_irq_dpll_lock(spdif_priv);
/* FIXME: Write Tx FIFO to clear TxEm */
if (sis & INT_TX_EM)
dev_dbg(&pdev->dev, "isr: Tx FIFO empty\n");
/* FIXME: Read Rx FIFO to clear RxFIFOFul */
if (sis & INT_RXFIFO_FUL)
dev_dbg(&pdev->dev, "isr: Rx FIFO full\n");
return IRQ_HANDLED;
}
static int spdif_softreset(struct fsl_spdif_priv *spdif_priv)
{
struct regmap *regmap = spdif_priv->regmap;
u32 val, cycle = 1000;
regcache_cache_bypass(regmap, true);
regmap_write(regmap, REG_SPDIF_SCR, SCR_SOFT_RESET);
/*
* RESET bit would be cleared after finishing its reset procedure,
* which typically lasts 8 cycles. 1000 cycles will keep it safe.
*/
do {
regmap_read(regmap, REG_SPDIF_SCR, &val);
} while ((val & SCR_SOFT_RESET) && cycle--);
regcache_cache_bypass(regmap, false);
regcache_mark_dirty(regmap);
regcache_sync(regmap);
if (cycle)
return 0;
else
return -EBUSY;
}
static void spdif_set_cstatus(struct spdif_mixer_control *ctrl,
u8 mask, u8 cstatus)
{
ctrl->ch_status[3] &= ~mask;
ctrl->ch_status[3] |= cstatus & mask;
}
static void spdif_write_channel_status(struct fsl_spdif_priv *spdif_priv)
{
struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
struct regmap *regmap = spdif_priv->regmap;
struct platform_device *pdev = spdif_priv->pdev;
u32 ch_status;
ch_status = (bitrev8(ctrl->ch_status[0]) << 16) |
(bitrev8(ctrl->ch_status[1]) << 8) |
bitrev8(ctrl->ch_status[2]);
regmap_write(regmap, REG_SPDIF_STCSCH, ch_status);
dev_dbg(&pdev->dev, "STCSCH: 0x%06x\n", ch_status);
ch_status = bitrev8(ctrl->ch_status[3]) << 16;
regmap_write(regmap, REG_SPDIF_STCSCL, ch_status);
dev_dbg(&pdev->dev, "STCSCL: 0x%06x\n", ch_status);
if (spdif_priv->soc->cchannel_192b) {
ch_status = (bitrev8(ctrl->ch_status[0]) << 24) |
(bitrev8(ctrl->ch_status[1]) << 16) |
(bitrev8(ctrl->ch_status[2]) << 8) |
bitrev8(ctrl->ch_status[3]);
regmap_update_bits(regmap, REG_SPDIF_SCR, 0x1000000, 0x1000000);
/*
* The first 32bit should be in REG_SPDIF_STCCA_31_0 register,
* but here we need to set REG_SPDIF_STCCA_191_160 on 8ULP
* then can get correct result with HDMI analyzer capture.
* There is a hardware bug here.
*/
regmap_write(regmap, REG_SPDIF_STCCA_191_160, ch_status);
}
}
/* Set SPDIF PhaseConfig register for rx clock */
static int spdif_set_rx_clksrc(struct fsl_spdif_priv *spdif_priv,
enum spdif_gainsel gainsel, int dpll_locked)
{
struct regmap *regmap = spdif_priv->regmap;
u8 clksrc = spdif_priv->rxclk_src;
if (clksrc >= SRPC_CLKSRC_MAX || gainsel >= GAINSEL_MULTI_MAX)
return -EINVAL;
regmap_update_bits(regmap, REG_SPDIF_SRPC,
SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK,
SRPC_CLKSRC_SEL_SET(clksrc) | SRPC_GAINSEL_SET(gainsel));
return 0;
}
static int fsl_spdif_probe_txclk(struct fsl_spdif_priv *spdif_priv, enum spdif_txrate index);
static int spdif_set_sample_rate(struct snd_pcm_substream *substream,
int sample_rate)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
struct regmap *regmap = spdif_priv->regmap;
struct platform_device *pdev = spdif_priv->pdev;
unsigned long csfs = 0;
u32 stc, mask, rate;
u16 sysclk_df;
u8 clk, txclk_df;
int ret;
switch (sample_rate) {
case 22050:
rate = SPDIF_TXRATE_22050;
csfs = IEC958_AES3_CON_FS_22050;
break;
case 32000:
rate = SPDIF_TXRATE_32000;
csfs = IEC958_AES3_CON_FS_32000;
break;
case 44100:
rate = SPDIF_TXRATE_44100;
csfs = IEC958_AES3_CON_FS_44100;
break;
case 48000:
rate = SPDIF_TXRATE_48000;
csfs = IEC958_AES3_CON_FS_48000;
break;
case 88200:
rate = SPDIF_TXRATE_88200;
csfs = IEC958_AES3_CON_FS_88200;
break;
case 96000:
rate = SPDIF_TXRATE_96000;
csfs = IEC958_AES3_CON_FS_96000;
break;
case 176400:
rate = SPDIF_TXRATE_176400;
csfs = IEC958_AES3_CON_FS_176400;
break;
case 192000:
rate = SPDIF_TXRATE_192000;
csfs = IEC958_AES3_CON_FS_192000;
break;
default:
dev_err(&pdev->dev, "unsupported sample rate %d\n", sample_rate);
return -EINVAL;
}
ret = fsl_spdif_probe_txclk(spdif_priv, rate);
if (ret)
return ret;
clk = spdif_priv->txclk_src[rate];
if (clk >= STC_TXCLK_SRC_MAX) {
dev_err(&pdev->dev, "tx clock source is out of range\n");
return -EINVAL;
}
txclk_df = spdif_priv->txclk_df[rate];
if (txclk_df == 0) {
dev_err(&pdev->dev, "the txclk_df can't be zero\n");
return -EINVAL;
}
sysclk_df = spdif_priv->sysclk_df[rate];
if (!fsl_spdif_can_set_clk_rate(spdif_priv, clk))
goto clk_set_bypass;
/* The S/PDIF block needs a clock of 64 * fs * txclk_df */
ret = clk_set_rate(spdif_priv->txclk[clk],
64 * sample_rate * txclk_df);
if (ret) {
dev_err(&pdev->dev, "failed to set tx clock rate\n");
return ret;
}
clk_set_bypass:
dev_dbg(&pdev->dev, "expected clock rate = %d\n",
(64 * sample_rate * txclk_df * sysclk_df));
dev_dbg(&pdev->dev, "actual clock rate = %ld\n",
clk_get_rate(spdif_priv->txclk[clk]));
/* set fs field in consumer channel status */
spdif_set_cstatus(ctrl, IEC958_AES3_CON_FS, csfs);
/* select clock source and divisor */
stc = STC_TXCLK_ALL_EN | STC_TXCLK_SRC_SET(clk) |
STC_TXCLK_DF(txclk_df) | STC_SYSCLK_DF(sysclk_df);
mask = STC_TXCLK_ALL_EN_MASK | STC_TXCLK_SRC_MASK |
STC_TXCLK_DF_MASK | STC_SYSCLK_DF_MASK;
regmap_update_bits(regmap, REG_SPDIF_STC, mask, stc);
dev_dbg(&pdev->dev, "set sample rate to %dHz for %dHz playback\n",
spdif_priv->txrate[rate], sample_rate);
return 0;
}
static int fsl_spdif_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *cpu_dai)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
struct platform_device *pdev = spdif_priv->pdev;
struct regmap *regmap = spdif_priv->regmap;
u32 scr, mask;
int ret;
/* Reset module and interrupts only for first initialization */
if (!snd_soc_dai_active(cpu_dai)) {
ret = spdif_softreset(spdif_priv);
if (ret) {
dev_err(&pdev->dev, "failed to soft reset\n");
return ret;
}
/* Disable all the interrupts */
regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0);
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
scr = SCR_TXFIFO_AUTOSYNC | SCR_TXFIFO_CTRL_NORMAL |
SCR_TXSEL_NORMAL | SCR_USRC_SEL_CHIP |
SCR_TXFIFO_FSEL_IF8;
mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
SCR_TXFIFO_FSEL_MASK;
} else {
scr = SCR_RXFIFO_FSEL_IF8 | SCR_RXFIFO_AUTOSYNC;
mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
}
regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
/* Power up SPDIF module */
regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER, 0);
return 0;
}
static void fsl_spdif_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *cpu_dai)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
struct regmap *regmap = spdif_priv->regmap;
u32 scr, mask;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
scr = 0;
mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
SCR_TXFIFO_FSEL_MASK;
/* Disable TX clock */
regmap_update_bits(regmap, REG_SPDIF_STC, STC_TXCLK_ALL_EN_MASK, 0);
} else {
scr = SCR_RXFIFO_OFF | SCR_RXFIFO_CTL_ZERO;
mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
}
regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
/* Power down SPDIF module only if tx&rx are both inactive */
if (!snd_soc_dai_active(cpu_dai)) {
spdif_intr_status_clear(spdif_priv);
regmap_update_bits(regmap, REG_SPDIF_SCR,
SCR_LOW_POWER, SCR_LOW_POWER);
}
}
static int spdif_reparent_rootclk(struct fsl_spdif_priv *spdif_priv, unsigned int sample_rate)
{
struct platform_device *pdev = spdif_priv->pdev;
struct clk *clk;
int ret;
/* Reparent clock if required condition is true */
if (!fsl_spdif_can_set_clk_rate(spdif_priv, STC_TXCLK_SPDIF_ROOT))
return 0;
/* Get root clock */
clk = spdif_priv->txclk[STC_TXCLK_SPDIF_ROOT];
/* Disable clock first, for it was enabled by pm_runtime */
clk_disable_unprepare(clk);
fsl_asoc_reparent_pll_clocks(&pdev->dev, clk, spdif_priv->pll8k_clk,
spdif_priv->pll11k_clk, sample_rate);
ret = clk_prepare_enable(clk);
if (ret)
return ret;
return 0;
}
static int fsl_spdif_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
struct platform_device *pdev = spdif_priv->pdev;
u32 sample_rate = params_rate(params);
int ret = 0;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
ret = spdif_reparent_rootclk(spdif_priv, sample_rate);
if (ret) {
dev_err(&pdev->dev, "%s: reparent root clk failed: %d\n",
__func__, sample_rate);
return ret;
}
ret = spdif_set_sample_rate(substream, sample_rate);
if (ret) {
dev_err(&pdev->dev, "%s: set sample rate failed: %d\n",
__func__, sample_rate);
return ret;
}
spdif_set_cstatus(ctrl, IEC958_AES3_CON_CLOCK,
IEC958_AES3_CON_CLOCK_1000PPM);
spdif_write_channel_status(spdif_priv);
} else {
/* Setup rx clock source */
ret = spdif_set_rx_clksrc(spdif_priv, SPDIF_DEFAULT_GAINSEL, 1);
}
return ret;
}
static int fsl_spdif_trigger(struct snd_pcm_substream *substream,
int cmd, struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
struct regmap *regmap = spdif_priv->regmap;
bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
u32 intr = SIE_INTR_FOR(tx);
u32 dmaen = SCR_DMA_xX_EN(tx);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
regmap_update_bits(regmap, REG_SPDIF_SIE, intr, intr);
regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, dmaen);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, 0);
regmap_update_bits(regmap, REG_SPDIF_SIE, intr, 0);
regmap_write(regmap, REG_SPDIF_STL, 0x0);
regmap_write(regmap, REG_SPDIF_STR, 0x0);
break;
default:
return -EINVAL;
}
return 0;
}
/*
* FSL SPDIF IEC958 controller(mixer) functions
*
* Channel status get/put control
* User bit value get/put control
* Valid bit value get control
* DPLL lock status get control
* User bit sync mode selection control
*/
static int fsl_spdif_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
uinfo->count = 1;
return 0;
}
static int fsl_spdif_pb_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *uvalue)
{
struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
uvalue->value.iec958.status[0] = ctrl->ch_status[0];
uvalue->value.iec958.status[1] = ctrl->ch_status[1];
uvalue->value.iec958.status[2] = ctrl->ch_status[2];
uvalue->value.iec958.status[3] = ctrl->ch_status[3];
return 0;
}
static int fsl_spdif_pb_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *uvalue)
{
struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
ctrl->ch_status[0] = uvalue->value.iec958.status[0];
ctrl->ch_status[1] = uvalue->value.iec958.status[1];
ctrl->ch_status[2] = uvalue->value.iec958.status[2];
ctrl->ch_status[3] = uvalue->value.iec958.status[3];
spdif_write_channel_status(spdif_priv);
return 0;
}
/* Get channel status from SPDIF_RX_CCHAN register */
static int fsl_spdif_capture_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
struct regmap *regmap = spdif_priv->regmap;
u32 cstatus, val;
regmap_read(regmap, REG_SPDIF_SIS, &val);
if (!(val & INT_CNEW))
return -EAGAIN;
regmap_read(regmap, REG_SPDIF_SRCSH, &cstatus);
ucontrol->value.iec958.status[0] = (cstatus >> 16) & 0xFF;
ucontrol->value.iec958.status[1] = (cstatus >> 8) & 0xFF;
ucontrol->value.iec958.status[2] = cstatus & 0xFF;
regmap_read(regmap, REG_SPDIF_SRCSL, &cstatus);
ucontrol->value.iec958.status[3] = (cstatus >> 16) & 0xFF;
ucontrol->value.iec958.status[4] = (cstatus >> 8) & 0xFF;
ucontrol->value.iec958.status[5] = cstatus & 0xFF;
/* Clear intr */
regmap_write(regmap, REG_SPDIF_SIC, INT_CNEW);
return 0;
}
/*
* Get User bits (subcode) from chip value which readed out
* in UChannel register.
*/
static int fsl_spdif_subcode_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
unsigned long flags;
int ret = -EAGAIN;
spin_lock_irqsave(&ctrl->ctl_lock, flags);
if (ctrl->ready_buf) {
int idx = (ctrl->ready_buf - 1) * SPDIF_UBITS_SIZE;
memcpy(&ucontrol->value.iec958.subcode[0],
&ctrl->subcode[idx], SPDIF_UBITS_SIZE);
ret = 0;
}
spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
return ret;
}
/* Q-subcode information. The byte size is SPDIF_UBITS_SIZE/8 */
static int fsl_spdif_qinfo(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
uinfo->count = SPDIF_QSUB_SIZE;
return 0;
}
/* Get Q subcode from chip value which readed out in QChannel register */
static int fsl_spdif_qget(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
unsigned long flags;
int ret = -EAGAIN;
spin_lock_irqsave(&ctrl->ctl_lock, flags);
if (ctrl->ready_buf) {
int idx = (ctrl->ready_buf - 1) * SPDIF_QSUB_SIZE;
memcpy(&ucontrol->value.bytes.data[0],
&ctrl->qsub[idx], SPDIF_QSUB_SIZE);
ret = 0;
}
spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
return ret;
}
/* Get valid good bit from interrupt status register */
static int fsl_spdif_rx_vbit_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
struct regmap *regmap = spdif_priv->regmap;
u32 val;
regmap_read(regmap, REG_SPDIF_SIS, &val);
ucontrol->value.integer.value[0] = (val & INT_VAL_NOGOOD) != 0;
regmap_write(regmap, REG_SPDIF_SIC, INT_VAL_NOGOOD);
return 0;
}
static int fsl_spdif_tx_vbit_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
struct regmap *regmap = spdif_priv->regmap;
u32 val;
regmap_read(regmap, REG_SPDIF_SCR, &val);
val = (val & SCR_VAL_MASK) >> SCR_VAL_OFFSET;
val = 1 - val;
ucontrol->value.integer.value[0] = val;
return 0;
}
static int fsl_spdif_tx_vbit_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
struct regmap *regmap = spdif_priv->regmap;
u32 val = (1 - ucontrol->value.integer.value[0]) << SCR_VAL_OFFSET;
regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_VAL_MASK, val);
return 0;
}
static int fsl_spdif_rx_rcm_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
struct regmap *regmap = spdif_priv->regmap;
u32 val;
regmap_read(regmap, REG_SPDIF_SCR, &val);
val = (val & SCR_RAW_CAPTURE_MODE) ? 1 : 0;
ucontrol->value.integer.value[0] = val;
return 0;
}
static int fsl_spdif_rx_rcm_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
struct regmap *regmap = spdif_priv->regmap;
u32 val = (ucontrol->value.integer.value[0] ? SCR_RAW_CAPTURE_MODE : 0);
if (val)
cpu_dai->driver->capture.formats |= SNDRV_PCM_FMTBIT_S32_LE;
else
cpu_dai->driver->capture.formats &= ~SNDRV_PCM_FMTBIT_S32_LE;
regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_RAW_CAPTURE_MODE, val);
return 0;
}
static int fsl_spdif_bypass_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
struct fsl_spdif_priv *priv = snd_soc_dai_get_drvdata(dai);
ucontrol->value.integer.value[0] = priv->bypass ? 1 : 0;
return 0;
}
static int fsl_spdif_bypass_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
struct fsl_spdif_priv *priv = snd_soc_dai_get_drvdata(dai);
struct snd_soc_card *card = dai->component->card;
bool set = (ucontrol->value.integer.value[0] != 0);
struct regmap *regmap = priv->regmap;
struct snd_soc_pcm_runtime *rtd;
u32 scr, mask;
int stream;
rtd = snd_soc_get_pcm_runtime(card, card->dai_link);
if (priv->bypass == set)
return 0; /* nothing to do */
if (snd_soc_dai_active(dai)) {
dev_err(dai->dev, "Cannot change BYPASS mode while stream is running.\n");
return -EBUSY;
}
pm_runtime_get_sync(dai->dev);
if (set) {
/* Disable interrupts */
regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0);
/* Configure BYPASS mode */
scr = SCR_TXSEL_RX | SCR_RXFIFO_OFF;
mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK |
SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK | SCR_TXSEL_MASK;
/* Power up SPDIF module */
mask |= SCR_LOW_POWER;
} else {
/* Power down SPDIF module, disable TX */
scr = SCR_LOW_POWER | SCR_TXSEL_OFF;
mask = SCR_LOW_POWER | SCR_TXSEL_MASK;
}
regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
/* Disable playback & capture if BYPASS mode is enabled, enable otherwise */
for_each_pcm_streams(stream)
rtd->pcm->streams[stream].substream_count = (set ? 0 : 1);
priv->bypass = set;
pm_runtime_put_sync(dai->dev);
return 0;
}
/* DPLL lock information */
static int fsl_spdif_rxrate_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
uinfo->count = 1;
uinfo->value.integer.min = 16000;
uinfo->value.integer.max = 192000;
return 0;
}
static u32 gainsel_multi[GAINSEL_MULTI_MAX] = {
24, 16, 12, 8, 6, 4, 3,
};
/* Get RX data clock rate given the SPDIF bus_clk */
static int spdif_get_rxclk_rate(struct fsl_spdif_priv *spdif_priv,
enum spdif_gainsel gainsel)
{
struct regmap *regmap = spdif_priv->regmap;
struct platform_device *pdev = spdif_priv->pdev;
u64 tmpval64, busclk_freq = 0;
u32 freqmeas, phaseconf;
u8 clksrc;
regmap_read(regmap, REG_SPDIF_SRFM, &freqmeas);
regmap_read(regmap, REG_SPDIF_SRPC, &phaseconf);
clksrc = (phaseconf >> SRPC_CLKSRC_SEL_OFFSET) & 0xf;
/* Get bus clock from system */
if (srpc_dpll_locked[clksrc] && (phaseconf & SRPC_DPLL_LOCKED))
busclk_freq = clk_get_rate(spdif_priv->sysclk);
/* FreqMeas_CLK = (BUS_CLK * FreqMeas) / 2 ^ 10 / GAINSEL / 128 */
tmpval64 = (u64) busclk_freq * freqmeas;
do_div(tmpval64, gainsel_multi[gainsel] * 1024);
do_div(tmpval64, 128 * 1024);
dev_dbg(&pdev->dev, "FreqMeas: %d\n", freqmeas);
dev_dbg(&pdev->dev, "BusclkFreq: %lld\n", busclk_freq);
dev_dbg(&pdev->dev, "RxRate: %lld\n", tmpval64);
return (int)tmpval64;
}
/*
* Get DPLL lock or not info from stable interrupt status register.
* User application must use this control to get locked,
* then can do next PCM operation
*/
static int fsl_spdif_rxrate_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
int rate = 0;
if (spdif_priv->dpll_locked)
rate = spdif_get_rxclk_rate(spdif_priv, SPDIF_DEFAULT_GAINSEL);
ucontrol->value.integer.value[0] = rate;
return 0;
}
/*
* User bit sync mode:
* 1 CD User channel subcode
* 0 Non-CD data
*/
static int fsl_spdif_usync_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
struct regmap *regmap = spdif_priv->regmap;
u32 val;
regmap_read(regmap, REG_SPDIF_SRCD, &val);
ucontrol->value.integer.value[0] = (val & SRCD_CD_USER) != 0;
return 0;
}
/*
* User bit sync mode:
* 1 CD User channel subcode
* 0 Non-CD data
*/
static int fsl_spdif_usync_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
struct regmap *regmap = spdif_priv->regmap;
u32 val = ucontrol->value.integer.value[0] << SRCD_CD_USER_OFFSET;
regmap_update_bits(regmap, REG_SPDIF_SRCD, SRCD_CD_USER, val);
return 0;
}
/* FSL SPDIF IEC958 controller defines */
static struct snd_kcontrol_new fsl_spdif_ctrls[] = {
/* Status cchanel controller */
{
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
.name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
.access = SNDRV_CTL_ELEM_ACCESS_READ |
SNDRV_CTL_ELEM_ACCESS_WRITE |
SNDRV_CTL_ELEM_ACCESS_VOLATILE,
.info = fsl_spdif_info,
.get = fsl_spdif_pb_get,
.put = fsl_spdif_pb_put,
},
{
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
.name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
.access = SNDRV_CTL_ELEM_ACCESS_READ |
SNDRV_CTL_ELEM_ACCESS_VOLATILE,
.info = fsl_spdif_info,
.get = fsl_spdif_capture_get,
},
/* User bits controller */
{
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
.name = "IEC958 Subcode Capture Default",
.access = SNDRV_CTL_ELEM_ACCESS_READ |
SNDRV_CTL_ELEM_ACCESS_VOLATILE,
.info = fsl_spdif_info,
.get = fsl_spdif_subcode_get,
},
{
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
.name = "IEC958 Q-subcode Capture Default",
.access = SNDRV_CTL_ELEM_ACCESS_READ |
SNDRV_CTL_ELEM_ACCESS_VOLATILE,
.info = fsl_spdif_qinfo,
.get = fsl_spdif_qget,
},
/* Valid bit error controller */
{
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
.name = "IEC958 RX V-Bit Errors",
.access = SNDRV_CTL_ELEM_ACCESS_READ |
SNDRV_CTL_ELEM_ACCESS_VOLATILE,
.info = snd_ctl_boolean_mono_info,
.get = fsl_spdif_rx_vbit_get,
},
{
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
.name = "IEC958 TX V-Bit",
.access = SNDRV_CTL_ELEM_ACCESS_READ |
SNDRV_CTL_ELEM_ACCESS_WRITE |
SNDRV_CTL_ELEM_ACCESS_VOLATILE,
.info = snd_ctl_boolean_mono_info,
.get = fsl_spdif_tx_vbit_get,
.put = fsl_spdif_tx_vbit_put,
},
/* DPLL lock info get controller */
{
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
.name = RX_SAMPLE_RATE_KCONTROL,
.access = SNDRV_CTL_ELEM_ACCESS_READ |
SNDRV_CTL_ELEM_ACCESS_VOLATILE,
.info = fsl_spdif_rxrate_info,
.get = fsl_spdif_rxrate_get,
},
/* RX bypass controller */
{
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
.name = "Bypass Mode",
.access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
.info = snd_ctl_boolean_mono_info,
.get = fsl_spdif_bypass_get,
.put = fsl_spdif_bypass_put,
},
/* User bit sync mode set/get controller */
{
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
.name = "IEC958 USyncMode CDText",
.access = SNDRV_CTL_ELEM_ACCESS_READ |
SNDRV_CTL_ELEM_ACCESS_WRITE |
SNDRV_CTL_ELEM_ACCESS_VOLATILE,
.info = snd_ctl_boolean_mono_info,
.get = fsl_spdif_usync_get,
.put = fsl_spdif_usync_put,
},
};
static struct snd_kcontrol_new fsl_spdif_ctrls_rcm[] = {
{
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
.name = "IEC958 Raw Capture Mode",
.access = SNDRV_CTL_ELEM_ACCESS_READ |
SNDRV_CTL_ELEM_ACCESS_WRITE |
SNDRV_CTL_ELEM_ACCESS_VOLATILE,
.info = snd_ctl_boolean_mono_info,
.get = fsl_spdif_rx_rcm_get,
.put = fsl_spdif_rx_rcm_put,
},
};
static int fsl_spdif_dai_probe(struct snd_soc_dai *dai)
{
struct fsl_spdif_priv *spdif_private = snd_soc_dai_get_drvdata(dai);
snd_soc_dai_init_dma_data(dai, &spdif_private->dma_params_tx,
&spdif_private->dma_params_rx);
snd_soc_add_dai_controls(dai, fsl_spdif_ctrls, ARRAY_SIZE(fsl_spdif_ctrls));
if (spdif_private->soc->raw_capture_mode)
snd_soc_add_dai_controls(dai, fsl_spdif_ctrls_rcm,
ARRAY_SIZE(fsl_spdif_ctrls_rcm));
spdif_private->snd_card = dai->component->card->snd_card;
spdif_private->rxrate_kcontrol = snd_soc_card_get_kcontrol(dai->component->card,
RX_SAMPLE_RATE_KCONTROL);
if (!spdif_private->rxrate_kcontrol)
dev_err(&spdif_private->pdev->dev, "failed to get %s kcontrol\n",
RX_SAMPLE_RATE_KCONTROL);
/*Clear the val bit for Tx*/
regmap_update_bits(spdif_private->regmap, REG_SPDIF_SCR,
SCR_VAL_MASK, SCR_VAL_CLEAR);
return 0;
}
static const struct snd_soc_dai_ops fsl_spdif_dai_ops = {
.probe = fsl_spdif_dai_probe,
.startup = fsl_spdif_startup,
.hw_params = fsl_spdif_hw_params,
.trigger = fsl_spdif_trigger,
.shutdown = fsl_spdif_shutdown,
};
static struct snd_soc_dai_driver fsl_spdif_dai = {
.playback = {
.stream_name = "CPU-Playback",
.channels_min = 2,
.channels_max = 2,
.rates = FSL_SPDIF_RATES_PLAYBACK,
.formats = FSL_SPDIF_FORMATS_PLAYBACK,
},
.capture = {
.stream_name = "CPU-Capture",
.channels_min = 2,
.channels_max = 2,
.rates = FSL_SPDIF_RATES_CAPTURE,
.formats = FSL_SPDIF_FORMATS_CAPTURE,
},
.ops = &fsl_spdif_dai_ops,
};
static const struct snd_soc_component_driver fsl_spdif_component = {
.name = "fsl-spdif",
.legacy_dai_naming = 1,
};
/* FSL SPDIF REGMAP */
static const struct reg_default fsl_spdif_reg_defaults[] = {
{REG_SPDIF_SCR, 0x00000400},
{REG_SPDIF_SRCD, 0x00000000},
{REG_SPDIF_SIE, 0x00000000},
{REG_SPDIF_STL, 0x00000000},
{REG_SPDIF_STR, 0x00000000},
{REG_SPDIF_STCSCH, 0x00000000},
{REG_SPDIF_STCSCL, 0x00000000},
{REG_SPDIF_STCSPH, 0x00000000},
{REG_SPDIF_STCSPL, 0x00000000},
{REG_SPDIF_STC, 0x00020f00},
};
static bool fsl_spdif_readable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case REG_SPDIF_SCR:
case REG_SPDIF_SRCD:
case REG_SPDIF_SRPC:
case REG_SPDIF_SIE:
case REG_SPDIF_SIS:
case REG_SPDIF_SRL:
case REG_SPDIF_SRR:
case REG_SPDIF_SRCSH:
case REG_SPDIF_SRCSL:
case REG_SPDIF_SRU:
case REG_SPDIF_SRQ:
case REG_SPDIF_STCSCH:
case REG_SPDIF_STCSCL:
case REG_SPDIF_STCSPH:
case REG_SPDIF_STCSPL:
case REG_SPDIF_SRFM:
case REG_SPDIF_STC:
case REG_SPDIF_SRCCA_31_0:
case REG_SPDIF_SRCCA_63_32:
case REG_SPDIF_SRCCA_95_64:
case REG_SPDIF_SRCCA_127_96:
case REG_SPDIF_SRCCA_159_128:
case REG_SPDIF_SRCCA_191_160:
case REG_SPDIF_STCCA_31_0:
case REG_SPDIF_STCCA_63_32:
case REG_SPDIF_STCCA_95_64:
case REG_SPDIF_STCCA_127_96:
case REG_SPDIF_STCCA_159_128:
case REG_SPDIF_STCCA_191_160:
return true;
default:
return false;
}
}
static bool fsl_spdif_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case REG_SPDIF_SRPC:
case REG_SPDIF_SIS:
case REG_SPDIF_SRL:
case REG_SPDIF_SRR:
case REG_SPDIF_SRCSH:
case REG_SPDIF_SRCSL:
case REG_SPDIF_SRU:
case REG_SPDIF_SRQ:
case REG_SPDIF_SRFM:
case REG_SPDIF_SRCCA_31_0:
case REG_SPDIF_SRCCA_63_32:
case REG_SPDIF_SRCCA_95_64:
case REG_SPDIF_SRCCA_127_96:
case REG_SPDIF_SRCCA_159_128:
case REG_SPDIF_SRCCA_191_160:
return true;
default:
return false;
}
}
static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case REG_SPDIF_SCR:
case REG_SPDIF_SRCD:
case REG_SPDIF_SRPC:
case REG_SPDIF_SIE:
case REG_SPDIF_SIC:
case REG_SPDIF_STL:
case REG_SPDIF_STR:
case REG_SPDIF_STCSCH:
case REG_SPDIF_STCSCL:
case REG_SPDIF_STCSPH:
case REG_SPDIF_STCSPL:
case REG_SPDIF_STC:
case REG_SPDIF_STCCA_31_0:
case REG_SPDIF_STCCA_63_32:
case REG_SPDIF_STCCA_95_64:
case REG_SPDIF_STCCA_127_96:
case REG_SPDIF_STCCA_159_128:
case REG_SPDIF_STCCA_191_160:
return true;
default:
return false;
}
}
static const struct regmap_config fsl_spdif_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = REG_SPDIF_STCCA_191_160,
.reg_defaults = fsl_spdif_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(fsl_spdif_reg_defaults),
.readable_reg = fsl_spdif_readable_reg,
.volatile_reg = fsl_spdif_volatile_reg,
.writeable_reg = fsl_spdif_writeable_reg,
.cache_type = REGCACHE_FLAT,
};
static u32 fsl_spdif_txclk_caldiv(struct fsl_spdif_priv *spdif_priv,
struct clk *clk, u64 savesub,
enum spdif_txrate index, bool round)
{
static const u32 rate[] = { 22050, 32000, 44100, 48000, 88200, 96000, 176400,
192000, };
bool is_sysclk = clk_is_match(clk, spdif_priv->sysclk);
u64 rate_ideal, rate_actual, sub;
u32 arate;
u16 sysclk_dfmin, sysclk_dfmax, sysclk_df;
u8 txclk_df;
/* The sysclk has an extra divisor [2, 512] */
sysclk_dfmin = is_sysclk ? 2 : 1;
sysclk_dfmax = is_sysclk ? 512 : 1;
for (sysclk_df = sysclk_dfmin; sysclk_df <= sysclk_dfmax; sysclk_df++) {
for (txclk_df = 1; txclk_df <= 128; txclk_df++) {
rate_ideal = rate[index] * txclk_df * 64ULL;
if (round)
rate_actual = clk_round_rate(clk, rate_ideal);
else
rate_actual = clk_get_rate(clk);
arate = rate_actual / 64;
arate /= txclk_df * sysclk_df;
if (arate == rate[index]) {
/* We are lucky */
savesub = 0;
spdif_priv->txclk_df[index] = txclk_df;
spdif_priv->sysclk_df[index] = sysclk_df;
spdif_priv->txrate[index] = arate;
goto out;
} else if (arate / rate[index] == 1) {
/* A little bigger than expect */
sub = (u64)(arate - rate[index]) * 100000;
do_div(sub, rate[index]);
if (sub >= savesub)
continue;
savesub = sub;
spdif_priv->txclk_df[index] = txclk_df;
spdif_priv->sysclk_df[index] = sysclk_df;
spdif_priv->txrate[index] = arate;
} else if (rate[index] / arate == 1) {
/* A little smaller than expect */
sub = (u64)(rate[index] - arate) * 100000;
do_div(sub, rate[index]);
if (sub >= savesub)
continue;
savesub = sub;
spdif_priv->txclk_df[index] = txclk_df;
spdif_priv->sysclk_df[index] = sysclk_df;
spdif_priv->txrate[index] = arate;
}
}
}
out:
return savesub;
}
static int fsl_spdif_probe_txclk(struct fsl_spdif_priv *spdif_priv,
enum spdif_txrate index)
{
static const u32 rate[] = { 22050, 32000, 44100, 48000, 88200, 96000, 176400,
192000, };
struct platform_device *pdev = spdif_priv->pdev;
struct device *dev = &pdev->dev;
u64 savesub = 100000, ret;
struct clk *clk;
int i;
for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {
clk = spdif_priv->txclk[i];
if (IS_ERR(clk)) {
dev_err(dev, "no rxtx%d clock in devicetree\n", i);
return PTR_ERR(clk);
}
if (!clk_get_rate(clk))
continue;
ret = fsl_spdif_txclk_caldiv(spdif_priv, clk, savesub, index,
fsl_spdif_can_set_clk_rate(spdif_priv, i));
if (savesub == ret)
continue;
savesub = ret;
spdif_priv->txclk_src[index] = i;
/* To quick catch a divisor, we allow a 0.1% deviation */
if (savesub < 100)
break;
}
dev_dbg(dev, "use rxtx%d as tx clock source for %dHz sample rate\n",
spdif_priv->txclk_src[index], rate[index]);
dev_dbg(dev, "use txclk df %d for %dHz sample rate\n",
spdif_priv->txclk_df[index], rate[index]);
if (clk_is_match(spdif_priv->txclk[spdif_priv->txclk_src[index]], spdif_priv->sysclk))
dev_dbg(dev, "use sysclk df %d for %dHz sample rate\n",
spdif_priv->sysclk_df[index], rate[index]);
dev_dbg(dev, "the best rate for %dHz sample rate is %dHz\n",
rate[index], spdif_priv->txrate[index]);
return 0;
}
static int fsl_spdif_probe(struct platform_device *pdev)
{
struct fsl_spdif_priv *spdif_priv;
struct spdif_mixer_control *ctrl;
struct resource *res;
void __iomem *regs;
int irq, ret, i;
char tmp[16];
spdif_priv = devm_kzalloc(&pdev->dev, sizeof(*spdif_priv), GFP_KERNEL);
if (!spdif_priv)
return -ENOMEM;
spdif_priv->pdev = pdev;
spdif_priv->soc = of_device_get_match_data(&pdev->dev);
/* Initialize this copy of the CPU DAI driver structure */
memcpy(&spdif_priv->cpu_dai_drv, &fsl_spdif_dai, sizeof(fsl_spdif_dai));
spdif_priv->cpu_dai_drv.name = dev_name(&pdev->dev);
spdif_priv->cpu_dai_drv.playback.formats =
spdif_priv->soc->tx_formats;
/* Get the addresses and IRQ */
regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(regs))
return PTR_ERR(regs);
spdif_priv->regmap = devm_regmap_init_mmio(&pdev->dev, regs, &fsl_spdif_regmap_config);
if (IS_ERR(spdif_priv->regmap)) {
dev_err(&pdev->dev, "regmap init failed\n");
return PTR_ERR(spdif_priv->regmap);
}
for (i = 0; i < spdif_priv->soc->interrupts; i++) {
irq = platform_get_irq(pdev, i);
if (irq < 0)
return irq;
ret = devm_request_irq(&pdev->dev, irq, spdif_isr, 0,
dev_name(&pdev->dev), spdif_priv);
if (ret) {
dev_err(&pdev->dev, "could not claim irq %u\n", irq);
return ret;
}
}
for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {
sprintf(tmp, "rxtx%d", i);
spdif_priv->txclk[i] = devm_clk_get(&pdev->dev, tmp);
if (IS_ERR(spdif_priv->txclk[i])) {
dev_err(&pdev->dev, "no rxtx%d clock in devicetree\n", i);
return PTR_ERR(spdif_priv->txclk[i]);
}
}
/* Get system clock for rx clock rate calculation */
spdif_priv->sysclk = spdif_priv->txclk[5];
if (IS_ERR(spdif_priv->sysclk)) {
dev_err(&pdev->dev, "no sys clock (rxtx5) in devicetree\n");
return PTR_ERR(spdif_priv->sysclk);
}
/* Get core clock for data register access via DMA */
spdif_priv->coreclk = devm_clk_get(&pdev->dev, "core");
if (IS_ERR(spdif_priv->coreclk)) {
dev_err(&pdev->dev, "no core clock in devicetree\n");
return PTR_ERR(spdif_priv->coreclk);
}
spdif_priv->spbaclk = devm_clk_get(&pdev->dev, "spba");
if (IS_ERR(spdif_priv->spbaclk))
dev_warn(&pdev->dev, "no spba clock in devicetree\n");
/* Select clock source for rx/tx clock */
spdif_priv->rxclk = spdif_priv->txclk[1];
if (IS_ERR(spdif_priv->rxclk)) {
dev_err(&pdev->dev, "no rxtx1 clock in devicetree\n");
return PTR_ERR(spdif_priv->rxclk);
}
spdif_priv->rxclk_src = DEFAULT_RXCLK_SRC;
fsl_asoc_get_pll_clocks(&pdev->dev, &spdif_priv->pll8k_clk,
&spdif_priv->pll11k_clk);
/* Initial spinlock for control data */
ctrl = &spdif_priv->fsl_spdif_control;
spin_lock_init(&ctrl->ctl_lock);
/* Init tx channel status default value */
ctrl->ch_status[0] = IEC958_AES0_CON_NOT_COPYRIGHT |
IEC958_AES0_CON_EMPHASIS_5015;
ctrl->ch_status[1] = IEC958_AES1_CON_DIGDIGCONV_ID;
ctrl->ch_status[2] = 0x00;
ctrl->ch_status[3] = IEC958_AES3_CON_FS_44100 |
IEC958_AES3_CON_CLOCK_1000PPM;
spdif_priv->dpll_locked = false;
spdif_priv->dma_params_tx.maxburst = spdif_priv->soc->tx_burst;
spdif_priv->dma_params_rx.maxburst = spdif_priv->soc->rx_burst;
spdif_priv->dma_params_tx.addr = res->start + REG_SPDIF_STL;
spdif_priv->dma_params_rx.addr = res->start + REG_SPDIF_SRL;
/* Register with ASoC */
dev_set_drvdata(&pdev->dev, spdif_priv);
pm_runtime_enable(&pdev->dev);
regcache_cache_only(spdif_priv->regmap, true);
/*
* Register platform component before registering cpu dai for there
* is not defer probe for platform component in snd_soc_add_pcm_runtime().
*/
ret = imx_pcm_dma_init(pdev);
if (ret) {
dev_err_probe(&pdev->dev, ret, "imx_pcm_dma_init failed\n");
goto err_pm_disable;
}
ret = devm_snd_soc_register_component(&pdev->dev, &fsl_spdif_component,
&spdif_priv->cpu_dai_drv, 1);
if (ret) {
dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
goto err_pm_disable;
}
return ret;
err_pm_disable:
pm_runtime_disable(&pdev->dev);
return ret;
}
static void fsl_spdif_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
}
#ifdef CONFIG_PM
static int fsl_spdif_runtime_suspend(struct device *dev)
{
struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev);
int i;
/* Disable all the interrupts */
regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SIE, 0xffffff, 0);
regmap_read(spdif_priv->regmap, REG_SPDIF_SRPC,
&spdif_priv->regcache_srpc);
regcache_cache_only(spdif_priv->regmap, true);
for (i = 0; i < STC_TXCLK_SRC_MAX; i++)
clk_disable_unprepare(spdif_priv->txclk[i]);
if (!IS_ERR(spdif_priv->spbaclk))
clk_disable_unprepare(spdif_priv->spbaclk);
clk_disable_unprepare(spdif_priv->coreclk);
return 0;
}
static int fsl_spdif_runtime_resume(struct device *dev)
{
struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev);
int ret;
int i;
ret = clk_prepare_enable(spdif_priv->coreclk);
if (ret) {
dev_err(dev, "failed to enable core clock\n");
return ret;
}
if (!IS_ERR(spdif_priv->spbaclk)) {
ret = clk_prepare_enable(spdif_priv->spbaclk);
if (ret) {
dev_err(dev, "failed to enable spba clock\n");
goto disable_core_clk;
}
}
for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {
ret = clk_prepare_enable(spdif_priv->txclk[i]);
if (ret)
goto disable_tx_clk;
}
regcache_cache_only(spdif_priv->regmap, false);
regcache_mark_dirty(spdif_priv->regmap);
regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SRPC,
SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK,
spdif_priv->regcache_srpc);
ret = regcache_sync(spdif_priv->regmap);
if (ret)
goto disable_tx_clk;
return 0;
disable_tx_clk:
for (i--; i >= 0; i--)
clk_disable_unprepare(spdif_priv->txclk[i]);
if (!IS_ERR(spdif_priv->spbaclk))
clk_disable_unprepare(spdif_priv->spbaclk);
disable_core_clk:
clk_disable_unprepare(spdif_priv->coreclk);
return ret;
}
#endif /* CONFIG_PM */
static const struct dev_pm_ops fsl_spdif_pm = {
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
SET_RUNTIME_PM_OPS(fsl_spdif_runtime_suspend, fsl_spdif_runtime_resume,
NULL)
};
static const struct of_device_id fsl_spdif_dt_ids[] = {
{ .compatible = "fsl,imx35-spdif", .data = &fsl_spdif_imx35, },
{ .compatible = "fsl,vf610-spdif", .data = &fsl_spdif_vf610, },
{ .compatible = "fsl,imx6sx-spdif", .data = &fsl_spdif_imx6sx, },
{ .compatible = "fsl,imx8qm-spdif", .data = &fsl_spdif_imx8qm, },
{ .compatible = "fsl,imx8mm-spdif", .data = &fsl_spdif_imx8mm, },
{ .compatible = "fsl,imx8ulp-spdif", .data = &fsl_spdif_imx8ulp, },
{}
};
MODULE_DEVICE_TABLE(of, fsl_spdif_dt_ids);
static struct platform_driver fsl_spdif_driver = {
.driver = {
.name = "fsl-spdif-dai",
.of_match_table = fsl_spdif_dt_ids,
.pm = &fsl_spdif_pm,
},
.probe = fsl_spdif_probe,
.remove_new = fsl_spdif_remove,
};
module_platform_driver(fsl_spdif_driver);
MODULE_AUTHOR("Freescale Semiconductor, Inc.");
MODULE_DESCRIPTION("Freescale S/PDIF CPU DAI Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:fsl-spdif-dai");
| linux-master | sound/soc/fsl/fsl_spdif.c |
// SPDX-License-Identifier: GPL-2.0
//
// Freescale MPC8610HPCD ALSA SoC Machine driver
//
// Author: Timur Tabi <[email protected]>
//
// Copyright 2007-2010 Freescale Semiconductor, Inc.
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/fsl/guts.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/slab.h>
#include <sound/soc.h>
#include "fsl_dma.h"
#include "fsl_ssi.h"
#include "fsl_utils.h"
/* There's only one global utilities register */
static phys_addr_t guts_phys;
/**
* mpc8610_hpcd_data: machine-specific ASoC device data
*
* This structure contains data for a single sound platform device on an
* MPC8610 HPCD. Some of the data is taken from the device tree.
*/
struct mpc8610_hpcd_data {
struct snd_soc_dai_link dai[2];
struct snd_soc_card card;
unsigned int dai_format;
unsigned int codec_clk_direction;
unsigned int cpu_clk_direction;
unsigned int clk_frequency;
unsigned int ssi_id; /* 0 = SSI1, 1 = SSI2, etc */
unsigned int dma_id[2]; /* 0 = DMA1, 1 = DMA2, etc */
unsigned int dma_channel_id[2]; /* 0 = ch 0, 1 = ch 1, etc*/
char codec_dai_name[DAI_NAME_SIZE];
char platform_name[2][DAI_NAME_SIZE]; /* One for each DMA channel */
};
/**
* mpc8610_hpcd_machine_probe: initialize the board
*
* This function is used to initialize the board-specific hardware.
*
* Here we program the DMACR and PMUXCR registers.
*/
static int mpc8610_hpcd_machine_probe(struct snd_soc_card *card)
{
struct mpc8610_hpcd_data *machine_data =
container_of(card, struct mpc8610_hpcd_data, card);
struct ccsr_guts __iomem *guts;
guts = ioremap(guts_phys, sizeof(struct ccsr_guts));
if (!guts) {
dev_err(card->dev, "could not map global utilities\n");
return -ENOMEM;
}
/* Program the signal routing between the SSI and the DMA */
guts_set_dmacr(guts, machine_data->dma_id[0],
machine_data->dma_channel_id[0],
CCSR_GUTS_DMACR_DEV_SSI);
guts_set_dmacr(guts, machine_data->dma_id[1],
machine_data->dma_channel_id[1],
CCSR_GUTS_DMACR_DEV_SSI);
guts_set_pmuxcr_dma(guts, machine_data->dma_id[0],
machine_data->dma_channel_id[0], 0);
guts_set_pmuxcr_dma(guts, machine_data->dma_id[1],
machine_data->dma_channel_id[1], 0);
switch (machine_data->ssi_id) {
case 0:
clrsetbits_be32(&guts->pmuxcr,
CCSR_GUTS_PMUXCR_SSI1_MASK, CCSR_GUTS_PMUXCR_SSI1_SSI);
break;
case 1:
clrsetbits_be32(&guts->pmuxcr,
CCSR_GUTS_PMUXCR_SSI2_MASK, CCSR_GUTS_PMUXCR_SSI2_SSI);
break;
}
iounmap(guts);
return 0;
}
/**
* mpc8610_hpcd_startup: program the board with various hardware parameters
*
* This function takes board-specific information, like clock frequencies
* and serial data formats, and passes that information to the codec and
* transport drivers.
*/
static int mpc8610_hpcd_startup(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct mpc8610_hpcd_data *machine_data =
container_of(rtd->card, struct mpc8610_hpcd_data, card);
struct device *dev = rtd->card->dev;
int ret = 0;
/* Tell the codec driver what the serial protocol is. */
ret = snd_soc_dai_set_fmt(asoc_rtd_to_codec(rtd, 0), machine_data->dai_format);
if (ret < 0) {
dev_err(dev, "could not set codec driver audio format\n");
return ret;
}
/*
* Tell the codec driver what the MCLK frequency is, and whether it's
* a slave or master.
*/
ret = snd_soc_dai_set_sysclk(asoc_rtd_to_codec(rtd, 0), 0,
machine_data->clk_frequency,
machine_data->codec_clk_direction);
if (ret < 0) {
dev_err(dev, "could not set codec driver clock params\n");
return ret;
}
return 0;
}
/**
* mpc8610_hpcd_machine_remove: Remove the sound device
*
* This function is called to remove the sound device for one SSI. We
* de-program the DMACR and PMUXCR register.
*/
static int mpc8610_hpcd_machine_remove(struct snd_soc_card *card)
{
struct mpc8610_hpcd_data *machine_data =
container_of(card, struct mpc8610_hpcd_data, card);
struct ccsr_guts __iomem *guts;
guts = ioremap(guts_phys, sizeof(struct ccsr_guts));
if (!guts) {
dev_err(card->dev, "could not map global utilities\n");
return -ENOMEM;
}
/* Restore the signal routing */
guts_set_dmacr(guts, machine_data->dma_id[0],
machine_data->dma_channel_id[0], 0);
guts_set_dmacr(guts, machine_data->dma_id[1],
machine_data->dma_channel_id[1], 0);
switch (machine_data->ssi_id) {
case 0:
clrsetbits_be32(&guts->pmuxcr,
CCSR_GUTS_PMUXCR_SSI1_MASK, CCSR_GUTS_PMUXCR_SSI1_LA);
break;
case 1:
clrsetbits_be32(&guts->pmuxcr,
CCSR_GUTS_PMUXCR_SSI2_MASK, CCSR_GUTS_PMUXCR_SSI2_LA);
break;
}
iounmap(guts);
return 0;
}
/**
* mpc8610_hpcd_ops: ASoC machine driver operations
*/
static const struct snd_soc_ops mpc8610_hpcd_ops = {
.startup = mpc8610_hpcd_startup,
};
/**
* mpc8610_hpcd_probe: platform probe function for the machine driver
*
* Although this is a machine driver, the SSI node is the "master" node with
* respect to audio hardware connections. Therefore, we create a new ASoC
* device for each new SSI node that has a codec attached.
*/
static int mpc8610_hpcd_probe(struct platform_device *pdev)
{
struct device *dev = pdev->dev.parent;
/* ssi_pdev is the platform device for the SSI node that probed us */
struct platform_device *ssi_pdev = to_platform_device(dev);
struct device_node *np = ssi_pdev->dev.of_node;
struct device_node *codec_np = NULL;
struct mpc8610_hpcd_data *machine_data;
struct snd_soc_dai_link_component *comp;
int ret;
const char *sprop;
const u32 *iprop;
/* Find the codec node for this SSI. */
codec_np = of_parse_phandle(np, "codec-handle", 0);
if (!codec_np) {
dev_err(dev, "invalid codec node\n");
return -EINVAL;
}
machine_data = kzalloc(sizeof(struct mpc8610_hpcd_data), GFP_KERNEL);
if (!machine_data) {
ret = -ENOMEM;
goto error_alloc;
}
comp = devm_kzalloc(&pdev->dev, 6 * sizeof(*comp), GFP_KERNEL);
if (!comp) {
ret = -ENOMEM;
goto error_alloc;
}
machine_data->dai[0].cpus = &comp[0];
machine_data->dai[0].codecs = &comp[1];
machine_data->dai[0].platforms = &comp[2];
machine_data->dai[0].num_cpus = 1;
machine_data->dai[0].num_codecs = 1;
machine_data->dai[0].num_platforms = 1;
machine_data->dai[1].cpus = &comp[3];
machine_data->dai[1].codecs = &comp[4];
machine_data->dai[1].platforms = &comp[5];
machine_data->dai[1].num_cpus = 1;
machine_data->dai[1].num_codecs = 1;
machine_data->dai[1].num_platforms = 1;
machine_data->dai[0].cpus->dai_name = dev_name(&ssi_pdev->dev);
machine_data->dai[0].ops = &mpc8610_hpcd_ops;
/* ASoC core can match codec with device node */
machine_data->dai[0].codecs->of_node = codec_np;
/* The DAI name from the codec (snd_soc_dai_driver.name) */
machine_data->dai[0].codecs->dai_name = "cs4270-hifi";
/* We register two DAIs per SSI, one for playback and the other for
* capture. Currently, we only support codecs that have one DAI for
* both playback and capture.
*/
memcpy(&machine_data->dai[1], &machine_data->dai[0],
sizeof(struct snd_soc_dai_link));
/* Get the device ID */
iprop = of_get_property(np, "cell-index", NULL);
if (!iprop) {
dev_err(&pdev->dev, "cell-index property not found\n");
ret = -EINVAL;
goto error;
}
machine_data->ssi_id = be32_to_cpup(iprop);
/* Get the serial format and clock direction. */
sprop = of_get_property(np, "fsl,mode", NULL);
if (!sprop) {
dev_err(&pdev->dev, "fsl,mode property not found\n");
ret = -EINVAL;
goto error;
}
if (strcasecmp(sprop, "i2s-slave") == 0) {
machine_data->dai_format =
SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBP_CFP;
machine_data->codec_clk_direction = SND_SOC_CLOCK_OUT;
machine_data->cpu_clk_direction = SND_SOC_CLOCK_IN;
/* In i2s-slave mode, the codec has its own clock source, so we
* need to get the frequency from the device tree and pass it to
* the codec driver.
*/
iprop = of_get_property(codec_np, "clock-frequency", NULL);
if (!iprop || !*iprop) {
dev_err(&pdev->dev, "codec bus-frequency "
"property is missing or invalid\n");
ret = -EINVAL;
goto error;
}
machine_data->clk_frequency = be32_to_cpup(iprop);
} else if (strcasecmp(sprop, "i2s-master") == 0) {
machine_data->dai_format =
SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBC_CFC;
machine_data->codec_clk_direction = SND_SOC_CLOCK_IN;
machine_data->cpu_clk_direction = SND_SOC_CLOCK_OUT;
} else if (strcasecmp(sprop, "lj-slave") == 0) {
machine_data->dai_format =
SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_CBP_CFP;
machine_data->codec_clk_direction = SND_SOC_CLOCK_OUT;
machine_data->cpu_clk_direction = SND_SOC_CLOCK_IN;
} else if (strcasecmp(sprop, "lj-master") == 0) {
machine_data->dai_format =
SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_CBC_CFC;
machine_data->codec_clk_direction = SND_SOC_CLOCK_IN;
machine_data->cpu_clk_direction = SND_SOC_CLOCK_OUT;
} else if (strcasecmp(sprop, "rj-slave") == 0) {
machine_data->dai_format =
SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_CBP_CFP;
machine_data->codec_clk_direction = SND_SOC_CLOCK_OUT;
machine_data->cpu_clk_direction = SND_SOC_CLOCK_IN;
} else if (strcasecmp(sprop, "rj-master") == 0) {
machine_data->dai_format =
SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_CBC_CFC;
machine_data->codec_clk_direction = SND_SOC_CLOCK_IN;
machine_data->cpu_clk_direction = SND_SOC_CLOCK_OUT;
} else if (strcasecmp(sprop, "ac97-slave") == 0) {
machine_data->dai_format =
SND_SOC_DAIFMT_AC97 | SND_SOC_DAIFMT_CBP_CFP;
machine_data->codec_clk_direction = SND_SOC_CLOCK_OUT;
machine_data->cpu_clk_direction = SND_SOC_CLOCK_IN;
} else if (strcasecmp(sprop, "ac97-master") == 0) {
machine_data->dai_format =
SND_SOC_DAIFMT_AC97 | SND_SOC_DAIFMT_CBC_CFC;
machine_data->codec_clk_direction = SND_SOC_CLOCK_IN;
machine_data->cpu_clk_direction = SND_SOC_CLOCK_OUT;
} else {
dev_err(&pdev->dev,
"unrecognized fsl,mode property '%s'\n", sprop);
ret = -EINVAL;
goto error;
}
if (!machine_data->clk_frequency) {
dev_err(&pdev->dev, "unknown clock frequency\n");
ret = -EINVAL;
goto error;
}
/* Find the playback DMA channel to use. */
machine_data->dai[0].platforms->name = machine_data->platform_name[0];
ret = fsl_asoc_get_dma_channel(np, "fsl,playback-dma",
&machine_data->dai[0],
&machine_data->dma_channel_id[0],
&machine_data->dma_id[0]);
if (ret) {
dev_err(&pdev->dev, "missing/invalid playback DMA phandle\n");
goto error;
}
/* Find the capture DMA channel to use. */
machine_data->dai[1].platforms->name = machine_data->platform_name[1];
ret = fsl_asoc_get_dma_channel(np, "fsl,capture-dma",
&machine_data->dai[1],
&machine_data->dma_channel_id[1],
&machine_data->dma_id[1]);
if (ret) {
dev_err(&pdev->dev, "missing/invalid capture DMA phandle\n");
goto error;
}
/* Initialize our DAI data structure. */
machine_data->dai[0].stream_name = "playback";
machine_data->dai[1].stream_name = "capture";
machine_data->dai[0].name = machine_data->dai[0].stream_name;
machine_data->dai[1].name = machine_data->dai[1].stream_name;
machine_data->card.probe = mpc8610_hpcd_machine_probe;
machine_data->card.remove = mpc8610_hpcd_machine_remove;
machine_data->card.name = pdev->name; /* The platform driver name */
machine_data->card.owner = THIS_MODULE;
machine_data->card.dev = &pdev->dev;
machine_data->card.num_links = 2;
machine_data->card.dai_link = machine_data->dai;
/* Register with ASoC */
ret = snd_soc_register_card(&machine_data->card);
if (ret) {
dev_err(&pdev->dev, "could not register card\n");
goto error;
}
of_node_put(codec_np);
return 0;
error:
kfree(machine_data);
error_alloc:
of_node_put(codec_np);
return ret;
}
/**
* mpc8610_hpcd_remove: remove the platform device
*
* This function is called when the platform device is removed.
*/
static void mpc8610_hpcd_remove(struct platform_device *pdev)
{
struct snd_soc_card *card = platform_get_drvdata(pdev);
struct mpc8610_hpcd_data *machine_data =
container_of(card, struct mpc8610_hpcd_data, card);
snd_soc_unregister_card(card);
kfree(machine_data);
}
static struct platform_driver mpc8610_hpcd_driver = {
.probe = mpc8610_hpcd_probe,
.remove_new = mpc8610_hpcd_remove,
.driver = {
/* The name must match 'compatible' property in the device tree,
* in lowercase letters.
*/
.name = "snd-soc-mpc8610hpcd",
},
};
/**
* mpc8610_hpcd_init: machine driver initialization.
*
* This function is called when this module is loaded.
*/
static int __init mpc8610_hpcd_init(void)
{
struct device_node *guts_np;
struct resource res;
pr_info("Freescale MPC8610 HPCD ALSA SoC machine driver\n");
/* Get the physical address of the global utilities registers */
guts_np = of_find_compatible_node(NULL, NULL, "fsl,mpc8610-guts");
if (of_address_to_resource(guts_np, 0, &res)) {
pr_err("mpc8610-hpcd: missing/invalid global utilities node\n");
of_node_put(guts_np);
return -EINVAL;
}
guts_phys = res.start;
of_node_put(guts_np);
return platform_driver_register(&mpc8610_hpcd_driver);
}
/**
* mpc8610_hpcd_exit: machine driver exit
*
* This function is called when this driver is unloaded.
*/
static void __exit mpc8610_hpcd_exit(void)
{
platform_driver_unregister(&mpc8610_hpcd_driver);
}
module_init(mpc8610_hpcd_init);
module_exit(mpc8610_hpcd_exit);
MODULE_AUTHOR("Timur Tabi <[email protected]>");
MODULE_DESCRIPTION("Freescale MPC8610 HPCD ALSA SoC machine driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/fsl/mpc8610_hpcd.c |
// SPDX-License-Identifier: GPL-2.0+
// Copyright 2017-2020 NXP
#include <linux/module.h>
#include <linux/rpmsg.h>
#include "imx-pcm-rpmsg.h"
/*
* struct imx_audio_rpmsg: private data
*
* @rpmsg_pdev: pointer of platform device
*/
struct imx_audio_rpmsg {
struct platform_device *rpmsg_pdev;
};
static int imx_audio_rpmsg_cb(struct rpmsg_device *rpdev, void *data, int len,
void *priv, u32 src)
{
struct imx_audio_rpmsg *rpmsg = dev_get_drvdata(&rpdev->dev);
struct rpmsg_r_msg *r_msg = (struct rpmsg_r_msg *)data;
struct rpmsg_info *info;
struct rpmsg_msg *msg;
unsigned long flags;
if (!rpmsg->rpmsg_pdev)
return 0;
info = platform_get_drvdata(rpmsg->rpmsg_pdev);
dev_dbg(&rpdev->dev, "get from%d: cmd:%d. %d\n",
src, r_msg->header.cmd, r_msg->param.resp);
switch (r_msg->header.type) {
case MSG_TYPE_C:
/* TYPE C is notification from M core */
switch (r_msg->header.cmd) {
case TX_PERIOD_DONE:
spin_lock_irqsave(&info->lock[TX], flags);
msg = &info->msg[TX_PERIOD_DONE + MSG_TYPE_A_NUM];
msg->r_msg.param.buffer_tail =
r_msg->param.buffer_tail;
msg->r_msg.param.buffer_tail %= info->num_period[TX];
spin_unlock_irqrestore(&info->lock[TX], flags);
info->callback[TX](info->callback_param[TX]);
break;
case RX_PERIOD_DONE:
spin_lock_irqsave(&info->lock[RX], flags);
msg = &info->msg[RX_PERIOD_DONE + MSG_TYPE_A_NUM];
msg->r_msg.param.buffer_tail =
r_msg->param.buffer_tail;
msg->r_msg.param.buffer_tail %= info->num_period[1];
spin_unlock_irqrestore(&info->lock[RX], flags);
info->callback[RX](info->callback_param[RX]);
break;
default:
dev_warn(&rpdev->dev, "unknown msg command\n");
break;
}
break;
case MSG_TYPE_B:
/* TYPE B is response msg */
memcpy(&info->r_msg, r_msg, sizeof(struct rpmsg_r_msg));
complete(&info->cmd_complete);
break;
default:
dev_warn(&rpdev->dev, "unknown msg type\n");
break;
}
return 0;
}
static int imx_audio_rpmsg_probe(struct rpmsg_device *rpdev)
{
struct imx_audio_rpmsg *data;
int ret = 0;
dev_info(&rpdev->dev, "new channel: 0x%x -> 0x%x!\n",
rpdev->src, rpdev->dst);
data = devm_kzalloc(&rpdev->dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
dev_set_drvdata(&rpdev->dev, data);
/* Register platform driver for rpmsg routine */
data->rpmsg_pdev = platform_device_register_data(&rpdev->dev,
IMX_PCM_DRV_NAME,
PLATFORM_DEVID_AUTO,
NULL, 0);
if (IS_ERR(data->rpmsg_pdev)) {
dev_err(&rpdev->dev, "failed to register rpmsg platform.\n");
ret = PTR_ERR(data->rpmsg_pdev);
}
return ret;
}
static void imx_audio_rpmsg_remove(struct rpmsg_device *rpdev)
{
struct imx_audio_rpmsg *data = dev_get_drvdata(&rpdev->dev);
if (data->rpmsg_pdev)
platform_device_unregister(data->rpmsg_pdev);
dev_info(&rpdev->dev, "audio rpmsg driver is removed\n");
}
static struct rpmsg_device_id imx_audio_rpmsg_id_table[] = {
{ .name = "rpmsg-audio-channel" },
{ .name = "rpmsg-micfil-channel" },
{ },
};
static struct rpmsg_driver imx_audio_rpmsg_driver = {
.drv.name = "imx_audio_rpmsg",
.id_table = imx_audio_rpmsg_id_table,
.probe = imx_audio_rpmsg_probe,
.callback = imx_audio_rpmsg_cb,
.remove = imx_audio_rpmsg_remove,
};
module_rpmsg_driver(imx_audio_rpmsg_driver);
MODULE_DESCRIPTION("Freescale SoC Audio RPMSG interface");
MODULE_AUTHOR("Shengjiu Wang <[email protected]>");
MODULE_ALIAS("platform:imx_audio_rpmsg");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/fsl/imx-audio-rpmsg.c |
// SPDX-License-Identifier: GPL-2.0
//
// Freescale ASRC ALSA SoC Digital Audio Interface (DAI) driver
//
// Copyright (C) 2014 Freescale Semiconductor, Inc.
//
// Author: Nicolin Chen <[email protected]>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/dma/imx-dma.h>
#include <linux/pm_runtime.h>
#include <sound/dmaengine_pcm.h>
#include <sound/pcm_params.h>
#include "fsl_asrc.h"
#define IDEAL_RATIO_DECIMAL_DEPTH 26
#define DIVIDER_NUM 64
#define INIT_RETRY_NUM 50
#define pair_err(fmt, ...) \
dev_err(&asrc->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
#define pair_dbg(fmt, ...) \
dev_dbg(&asrc->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
#define pair_warn(fmt, ...) \
dev_warn(&asrc->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
/* Corresponding to process_option */
static unsigned int supported_asrc_rate[] = {
5512, 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000,
64000, 88200, 96000, 128000, 176400, 192000,
};
static struct snd_pcm_hw_constraint_list fsl_asrc_rate_constraints = {
.count = ARRAY_SIZE(supported_asrc_rate),
.list = supported_asrc_rate,
};
/*
* The following tables map the relationship between asrc_inclk/asrc_outclk in
* fsl_asrc.h and the registers of ASRCSR
*/
static unsigned char input_clk_map_imx35[ASRC_CLK_MAP_LEN] = {
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
};
static unsigned char output_clk_map_imx35[ASRC_CLK_MAP_LEN] = {
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
};
/* i.MX53 uses the same map for input and output */
static unsigned char input_clk_map_imx53[ASRC_CLK_MAP_LEN] = {
/* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */
0x0, 0x1, 0x2, 0x7, 0x4, 0x5, 0x6, 0x3, 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0xe, 0xd,
0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7,
0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7,
};
static unsigned char output_clk_map_imx53[ASRC_CLK_MAP_LEN] = {
/* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */
0x8, 0x9, 0xa, 0x7, 0xc, 0x5, 0x6, 0xb, 0x0, 0x1, 0x2, 0x3, 0x4, 0xf, 0xe, 0xd,
0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7,
0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7,
};
/*
* i.MX8QM/i.MX8QXP uses the same map for input and output.
* clk_map_imx8qm[0] is for i.MX8QM asrc0
* clk_map_imx8qm[1] is for i.MX8QM asrc1
* clk_map_imx8qxp[0] is for i.MX8QXP asrc0
* clk_map_imx8qxp[1] is for i.MX8QXP asrc1
*/
static unsigned char clk_map_imx8qm[2][ASRC_CLK_MAP_LEN] = {
{
0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0,
0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
},
{
0xf, 0xf, 0xf, 0xf, 0xf, 0x7, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0,
0x0, 0x1, 0x2, 0x3, 0xb, 0xc, 0xf, 0xf, 0xd, 0xe, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
0x4, 0x5, 0x6, 0xf, 0x8, 0x9, 0xa, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
},
};
static unsigned char clk_map_imx8qxp[2][ASRC_CLK_MAP_LEN] = {
{
0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0,
0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0xf, 0x7, 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0xf,
0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
},
{
0xf, 0xf, 0xf, 0xf, 0xf, 0x7, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0,
0x0, 0x1, 0x2, 0x3, 0x7, 0x8, 0xf, 0xf, 0x9, 0xa, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
0xf, 0xf, 0x6, 0xf, 0xf, 0xf, 0xa, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
},
};
/*
* According to RM, the divider range is 1 ~ 8,
* prescaler is power of 2 from 1 ~ 128.
*/
static int asrc_clk_divider[DIVIDER_NUM] = {
1, 2, 4, 8, 16, 32, 64, 128, /* divider = 1 */
2, 4, 8, 16, 32, 64, 128, 256, /* divider = 2 */
3, 6, 12, 24, 48, 96, 192, 384, /* divider = 3 */
4, 8, 16, 32, 64, 128, 256, 512, /* divider = 4 */
5, 10, 20, 40, 80, 160, 320, 640, /* divider = 5 */
6, 12, 24, 48, 96, 192, 384, 768, /* divider = 6 */
7, 14, 28, 56, 112, 224, 448, 896, /* divider = 7 */
8, 16, 32, 64, 128, 256, 512, 1024, /* divider = 8 */
};
/*
* Check if the divider is available for internal ratio mode
*/
static bool fsl_asrc_divider_avail(int clk_rate, int rate, int *div)
{
u32 rem, i;
u64 n;
if (div)
*div = 0;
if (clk_rate == 0 || rate == 0)
return false;
n = clk_rate;
rem = do_div(n, rate);
if (div)
*div = n;
if (rem != 0)
return false;
for (i = 0; i < DIVIDER_NUM; i++) {
if (n == asrc_clk_divider[i])
break;
}
if (i == DIVIDER_NUM)
return false;
return true;
}
/**
* fsl_asrc_sel_proc - Select the pre-processing and post-processing options
* @inrate: input sample rate
* @outrate: output sample rate
* @pre_proc: return value for pre-processing option
* @post_proc: return value for post-processing option
*
* Make sure to exclude following unsupported cases before
* calling this function:
* 1) inrate > 8.125 * outrate
* 2) inrate > 16.125 * outrate
*
*/
static void fsl_asrc_sel_proc(int inrate, int outrate,
int *pre_proc, int *post_proc)
{
bool post_proc_cond2;
bool post_proc_cond0;
/* select pre_proc between [0, 2] */
if (inrate * 8 > 33 * outrate)
*pre_proc = 2;
else if (inrate * 8 > 15 * outrate) {
if (inrate > 152000)
*pre_proc = 2;
else
*pre_proc = 1;
} else if (inrate < 76000)
*pre_proc = 0;
else if (inrate > 152000)
*pre_proc = 2;
else
*pre_proc = 1;
/* Condition for selection of post-processing */
post_proc_cond2 = (inrate * 15 > outrate * 16 && outrate < 56000) ||
(inrate > 56000 && outrate < 56000);
post_proc_cond0 = inrate * 23 < outrate * 8;
if (post_proc_cond2)
*post_proc = 2;
else if (post_proc_cond0)
*post_proc = 0;
else
*post_proc = 1;
}
/**
* fsl_asrc_request_pair - Request ASRC pair
* @channels: number of channels
* @pair: pointer to pair
*
* It assigns pair by the order of A->C->B because allocation of pair B,
* within range [ANCA, ANCA+ANCB-1], depends on the channels of pair A
* while pair A and pair C are comparatively independent.
*/
static int fsl_asrc_request_pair(int channels, struct fsl_asrc_pair *pair)
{
enum asrc_pair_index index = ASRC_INVALID_PAIR;
struct fsl_asrc *asrc = pair->asrc;
struct device *dev = &asrc->pdev->dev;
unsigned long lock_flags;
int i, ret = 0;
spin_lock_irqsave(&asrc->lock, lock_flags);
for (i = ASRC_PAIR_A; i < ASRC_PAIR_MAX_NUM; i++) {
if (asrc->pair[i] != NULL)
continue;
index = i;
if (i != ASRC_PAIR_B)
break;
}
if (index == ASRC_INVALID_PAIR) {
dev_err(dev, "all pairs are busy now\n");
ret = -EBUSY;
} else if (asrc->channel_avail < channels) {
dev_err(dev, "can't afford required channels: %d\n", channels);
ret = -EINVAL;
} else {
asrc->channel_avail -= channels;
asrc->pair[index] = pair;
pair->channels = channels;
pair->index = index;
}
spin_unlock_irqrestore(&asrc->lock, lock_flags);
return ret;
}
/**
* fsl_asrc_release_pair - Release ASRC pair
* @pair: pair to release
*
* It clears the resource from asrc and releases the occupied channels.
*/
static void fsl_asrc_release_pair(struct fsl_asrc_pair *pair)
{
struct fsl_asrc *asrc = pair->asrc;
enum asrc_pair_index index = pair->index;
unsigned long lock_flags;
/* Make sure the pair is disabled */
regmap_update_bits(asrc->regmap, REG_ASRCTR,
ASRCTR_ASRCEi_MASK(index), 0);
spin_lock_irqsave(&asrc->lock, lock_flags);
asrc->channel_avail += pair->channels;
asrc->pair[index] = NULL;
pair->error = 0;
spin_unlock_irqrestore(&asrc->lock, lock_flags);
}
/**
* fsl_asrc_set_watermarks- configure input and output thresholds
* @pair: pointer to pair
* @in: input threshold
* @out: output threshold
*/
static void fsl_asrc_set_watermarks(struct fsl_asrc_pair *pair, u32 in, u32 out)
{
struct fsl_asrc *asrc = pair->asrc;
enum asrc_pair_index index = pair->index;
regmap_update_bits(asrc->regmap, REG_ASRMCR(index),
ASRMCRi_EXTTHRSHi_MASK |
ASRMCRi_INFIFO_THRESHOLD_MASK |
ASRMCRi_OUTFIFO_THRESHOLD_MASK,
ASRMCRi_EXTTHRSHi |
ASRMCRi_INFIFO_THRESHOLD(in) |
ASRMCRi_OUTFIFO_THRESHOLD(out));
}
/**
* fsl_asrc_cal_asrck_divisor - Calculate the total divisor between asrck clock rate and sample rate
* @pair: pointer to pair
* @div: divider
*
* It follows the formula clk_rate = samplerate * (2 ^ prescaler) * divider
*/
static u32 fsl_asrc_cal_asrck_divisor(struct fsl_asrc_pair *pair, u32 div)
{
u32 ps;
/* Calculate the divisors: prescaler [2^0, 2^7], divder [1, 8] */
for (ps = 0; div > 8; ps++)
div >>= 1;
return ((div - 1) << ASRCDRi_AxCPi_WIDTH) | ps;
}
/**
* fsl_asrc_set_ideal_ratio - Calculate and set the ratio for Ideal Ratio mode only
* @pair: pointer to pair
* @inrate: input rate
* @outrate: output rate
*
* The ratio is a 32-bit fixed point value with 26 fractional bits.
*/
static int fsl_asrc_set_ideal_ratio(struct fsl_asrc_pair *pair,
int inrate, int outrate)
{
struct fsl_asrc *asrc = pair->asrc;
enum asrc_pair_index index = pair->index;
unsigned long ratio;
int i;
if (!outrate) {
pair_err("output rate should not be zero\n");
return -EINVAL;
}
/* Calculate the intergal part of the ratio */
ratio = (inrate / outrate) << IDEAL_RATIO_DECIMAL_DEPTH;
/* ... and then the 26 depth decimal part */
inrate %= outrate;
for (i = 1; i <= IDEAL_RATIO_DECIMAL_DEPTH; i++) {
inrate <<= 1;
if (inrate < outrate)
continue;
ratio |= 1 << (IDEAL_RATIO_DECIMAL_DEPTH - i);
inrate -= outrate;
if (!inrate)
break;
}
regmap_write(asrc->regmap, REG_ASRIDRL(index), ratio);
regmap_write(asrc->regmap, REG_ASRIDRH(index), ratio >> 24);
return 0;
}
/**
* fsl_asrc_config_pair - Configure the assigned ASRC pair
* @pair: pointer to pair
* @use_ideal_rate: boolean configuration
*
* It configures those ASRC registers according to a configuration instance
* of struct asrc_config which includes in/output sample rate, width, channel
* and clock settings.
*
* Note:
* The ideal ratio configuration can work with a flexible clock rate setting.
* Using IDEAL_RATIO_RATE gives a faster converting speed but overloads ASRC.
* For a regular audio playback, the clock rate should not be slower than an
* clock rate aligning with the output sample rate; For a use case requiring
* faster conversion, set use_ideal_rate to have the faster speed.
*/
static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair, bool use_ideal_rate)
{
struct fsl_asrc_pair_priv *pair_priv = pair->private;
struct asrc_config *config = pair_priv->config;
struct fsl_asrc *asrc = pair->asrc;
struct fsl_asrc_priv *asrc_priv = asrc->private;
enum asrc_pair_index index = pair->index;
enum asrc_word_width input_word_width;
enum asrc_word_width output_word_width;
u32 inrate, outrate, indiv, outdiv;
u32 clk_index[2], div[2];
u64 clk_rate;
int in, out, channels;
int pre_proc, post_proc;
struct clk *clk;
bool ideal, div_avail;
if (!config) {
pair_err("invalid pair config\n");
return -EINVAL;
}
/* Validate channels */
if (config->channel_num < 1 || config->channel_num > 10) {
pair_err("does not support %d channels\n", config->channel_num);
return -EINVAL;
}
switch (snd_pcm_format_width(config->input_format)) {
case 8:
input_word_width = ASRC_WIDTH_8_BIT;
break;
case 16:
input_word_width = ASRC_WIDTH_16_BIT;
break;
case 24:
input_word_width = ASRC_WIDTH_24_BIT;
break;
default:
pair_err("does not support this input format, %d\n",
config->input_format);
return -EINVAL;
}
switch (snd_pcm_format_width(config->output_format)) {
case 16:
output_word_width = ASRC_WIDTH_16_BIT;
break;
case 24:
output_word_width = ASRC_WIDTH_24_BIT;
break;
default:
pair_err("does not support this output format, %d\n",
config->output_format);
return -EINVAL;
}
inrate = config->input_sample_rate;
outrate = config->output_sample_rate;
ideal = config->inclk == INCLK_NONE;
/* Validate input and output sample rates */
for (in = 0; in < ARRAY_SIZE(supported_asrc_rate); in++)
if (inrate == supported_asrc_rate[in])
break;
if (in == ARRAY_SIZE(supported_asrc_rate)) {
pair_err("unsupported input sample rate: %dHz\n", inrate);
return -EINVAL;
}
for (out = 0; out < ARRAY_SIZE(supported_asrc_rate); out++)
if (outrate == supported_asrc_rate[out])
break;
if (out == ARRAY_SIZE(supported_asrc_rate)) {
pair_err("unsupported output sample rate: %dHz\n", outrate);
return -EINVAL;
}
if ((outrate >= 5512 && outrate <= 30000) &&
(outrate > 24 * inrate || inrate > 8 * outrate)) {
pair_err("exceed supported ratio range [1/24, 8] for \
inrate/outrate: %d/%d\n", inrate, outrate);
return -EINVAL;
}
/* Validate input and output clock sources */
clk_index[IN] = asrc_priv->clk_map[IN][config->inclk];
clk_index[OUT] = asrc_priv->clk_map[OUT][config->outclk];
/* We only have output clock for ideal ratio mode */
clk = asrc_priv->asrck_clk[clk_index[ideal ? OUT : IN]];
clk_rate = clk_get_rate(clk);
div_avail = fsl_asrc_divider_avail(clk_rate, inrate, &div[IN]);
/*
* The divider range is [1, 1024], defined by the hardware. For non-
* ideal ratio configuration, clock rate has to be strictly aligned
* with the sample rate. For ideal ratio configuration, clock rates
* only result in different converting speeds. So remainder does not
* matter, as long as we keep the divider within its valid range.
*/
if (div[IN] == 0 || (!ideal && !div_avail)) {
pair_err("failed to support input sample rate %dHz by asrck_%x\n",
inrate, clk_index[ideal ? OUT : IN]);
return -EINVAL;
}
div[IN] = min_t(u32, 1024, div[IN]);
clk = asrc_priv->asrck_clk[clk_index[OUT]];
clk_rate = clk_get_rate(clk);
if (ideal && use_ideal_rate)
div_avail = fsl_asrc_divider_avail(clk_rate, IDEAL_RATIO_RATE, &div[OUT]);
else
div_avail = fsl_asrc_divider_avail(clk_rate, outrate, &div[OUT]);
/* Output divider has the same limitation as the input one */
if (div[OUT] == 0 || (!ideal && !div_avail)) {
pair_err("failed to support output sample rate %dHz by asrck_%x\n",
outrate, clk_index[OUT]);
return -EINVAL;
}
div[OUT] = min_t(u32, 1024, div[OUT]);
/* Set the channel number */
channels = config->channel_num;
if (asrc_priv->soc->channel_bits < 4)
channels /= 2;
/* Update channels for current pair */
regmap_update_bits(asrc->regmap, REG_ASRCNCR,
ASRCNCR_ANCi_MASK(index, asrc_priv->soc->channel_bits),
ASRCNCR_ANCi(index, channels, asrc_priv->soc->channel_bits));
/* Default setting: Automatic selection for processing mode */
regmap_update_bits(asrc->regmap, REG_ASRCTR,
ASRCTR_ATSi_MASK(index), ASRCTR_ATS(index));
regmap_update_bits(asrc->regmap, REG_ASRCTR,
ASRCTR_USRi_MASK(index), 0);
/* Set the input and output clock sources */
regmap_update_bits(asrc->regmap, REG_ASRCSR,
ASRCSR_AICSi_MASK(index) | ASRCSR_AOCSi_MASK(index),
ASRCSR_AICS(index, clk_index[IN]) |
ASRCSR_AOCS(index, clk_index[OUT]));
/* Calculate the input clock divisors */
indiv = fsl_asrc_cal_asrck_divisor(pair, div[IN]);
outdiv = fsl_asrc_cal_asrck_divisor(pair, div[OUT]);
/* Suppose indiv and outdiv includes prescaler, so add its MASK too */
regmap_update_bits(asrc->regmap, REG_ASRCDR(index),
ASRCDRi_AOCPi_MASK(index) | ASRCDRi_AICPi_MASK(index) |
ASRCDRi_AOCDi_MASK(index) | ASRCDRi_AICDi_MASK(index),
ASRCDRi_AOCP(index, outdiv) | ASRCDRi_AICP(index, indiv));
/* Implement word_width configurations */
regmap_update_bits(asrc->regmap, REG_ASRMCR1(index),
ASRMCR1i_OW16_MASK | ASRMCR1i_IWD_MASK,
ASRMCR1i_OW16(output_word_width) |
ASRMCR1i_IWD(input_word_width));
/* Enable BUFFER STALL */
regmap_update_bits(asrc->regmap, REG_ASRMCR(index),
ASRMCRi_BUFSTALLi_MASK, ASRMCRi_BUFSTALLi);
/* Set default thresholds for input and output FIFO */
fsl_asrc_set_watermarks(pair, ASRC_INPUTFIFO_THRESHOLD,
ASRC_INPUTFIFO_THRESHOLD);
/* Configure the following only for Ideal Ratio mode */
if (!ideal)
return 0;
/* Clear ASTSx bit to use Ideal Ratio mode */
regmap_update_bits(asrc->regmap, REG_ASRCTR,
ASRCTR_ATSi_MASK(index), 0);
/* Enable Ideal Ratio mode */
regmap_update_bits(asrc->regmap, REG_ASRCTR,
ASRCTR_IDRi_MASK(index) | ASRCTR_USRi_MASK(index),
ASRCTR_IDR(index) | ASRCTR_USR(index));
fsl_asrc_sel_proc(inrate, outrate, &pre_proc, &post_proc);
/* Apply configurations for pre- and post-processing */
regmap_update_bits(asrc->regmap, REG_ASRCFG,
ASRCFG_PREMODi_MASK(index) | ASRCFG_POSTMODi_MASK(index),
ASRCFG_PREMOD(index, pre_proc) |
ASRCFG_POSTMOD(index, post_proc));
return fsl_asrc_set_ideal_ratio(pair, inrate, outrate);
}
/**
* fsl_asrc_start_pair - Start the assigned ASRC pair
* @pair: pointer to pair
*
* It enables the assigned pair and makes it stopped at the stall level.
*/
static void fsl_asrc_start_pair(struct fsl_asrc_pair *pair)
{
struct fsl_asrc *asrc = pair->asrc;
enum asrc_pair_index index = pair->index;
int reg, retry = INIT_RETRY_NUM, i;
/* Enable the current pair */
regmap_update_bits(asrc->regmap, REG_ASRCTR,
ASRCTR_ASRCEi_MASK(index), ASRCTR_ASRCE(index));
/* Wait for status of initialization */
do {
udelay(5);
regmap_read(asrc->regmap, REG_ASRCFG, ®);
reg &= ASRCFG_INIRQi_MASK(index);
} while (!reg && --retry);
/* NOTE: Doesn't treat initialization timeout as an error */
if (!retry)
pair_warn("initialization isn't finished\n");
/* Make the input fifo to ASRC STALL level */
regmap_read(asrc->regmap, REG_ASRCNCR, ®);
for (i = 0; i < pair->channels * 4; i++)
regmap_write(asrc->regmap, REG_ASRDI(index), 0);
/* Enable overload interrupt */
regmap_write(asrc->regmap, REG_ASRIER, ASRIER_AOLIE);
}
/**
* fsl_asrc_stop_pair - Stop the assigned ASRC pair
* @pair: pointer to pair
*/
static void fsl_asrc_stop_pair(struct fsl_asrc_pair *pair)
{
struct fsl_asrc *asrc = pair->asrc;
enum asrc_pair_index index = pair->index;
/* Stop the current pair */
regmap_update_bits(asrc->regmap, REG_ASRCTR,
ASRCTR_ASRCEi_MASK(index), 0);
}
/**
* fsl_asrc_get_dma_channel- Get DMA channel according to the pair and direction.
* @pair: pointer to pair
* @dir: DMA direction
*/
static struct dma_chan *fsl_asrc_get_dma_channel(struct fsl_asrc_pair *pair,
bool dir)
{
struct fsl_asrc *asrc = pair->asrc;
enum asrc_pair_index index = pair->index;
char name[4];
sprintf(name, "%cx%c", dir == IN ? 'r' : 't', index + 'a');
return dma_request_slave_channel(&asrc->pdev->dev, name);
}
static int fsl_asrc_dai_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct fsl_asrc *asrc = snd_soc_dai_get_drvdata(dai);
struct fsl_asrc_priv *asrc_priv = asrc->private;
/* Odd channel number is not valid for older ASRC (channel_bits==3) */
if (asrc_priv->soc->channel_bits == 3)
snd_pcm_hw_constraint_step(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_CHANNELS, 2);
return snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE, &fsl_asrc_rate_constraints);
}
/* Select proper clock source for internal ratio mode */
static void fsl_asrc_select_clk(struct fsl_asrc_priv *asrc_priv,
struct fsl_asrc_pair *pair,
int in_rate,
int out_rate)
{
struct fsl_asrc_pair_priv *pair_priv = pair->private;
struct asrc_config *config = pair_priv->config;
int rate[2], select_clk[2]; /* Array size 2 means IN and OUT */
int clk_rate, clk_index;
int i, j;
rate[IN] = in_rate;
rate[OUT] = out_rate;
/* Select proper clock source for internal ratio mode */
for (j = 0; j < 2; j++) {
for (i = 0; i < ASRC_CLK_MAP_LEN; i++) {
clk_index = asrc_priv->clk_map[j][i];
clk_rate = clk_get_rate(asrc_priv->asrck_clk[clk_index]);
/* Only match a perfect clock source with no remainder */
if (fsl_asrc_divider_avail(clk_rate, rate[j], NULL))
break;
}
select_clk[j] = i;
}
/* Switch to ideal ratio mode if there is no proper clock source */
if (select_clk[IN] == ASRC_CLK_MAP_LEN || select_clk[OUT] == ASRC_CLK_MAP_LEN) {
select_clk[IN] = INCLK_NONE;
select_clk[OUT] = OUTCLK_ASRCK1_CLK;
}
config->inclk = select_clk[IN];
config->outclk = select_clk[OUT];
}
static int fsl_asrc_dai_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct fsl_asrc *asrc = snd_soc_dai_get_drvdata(dai);
struct fsl_asrc_priv *asrc_priv = asrc->private;
struct snd_pcm_runtime *runtime = substream->runtime;
struct fsl_asrc_pair *pair = runtime->private_data;
struct fsl_asrc_pair_priv *pair_priv = pair->private;
unsigned int channels = params_channels(params);
unsigned int rate = params_rate(params);
struct asrc_config config;
int ret;
ret = fsl_asrc_request_pair(channels, pair);
if (ret) {
dev_err(dai->dev, "fail to request asrc pair\n");
return ret;
}
pair_priv->config = &config;
config.pair = pair->index;
config.channel_num = channels;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
config.input_format = params_format(params);
config.output_format = asrc->asrc_format;
config.input_sample_rate = rate;
config.output_sample_rate = asrc->asrc_rate;
} else {
config.input_format = asrc->asrc_format;
config.output_format = params_format(params);
config.input_sample_rate = asrc->asrc_rate;
config.output_sample_rate = rate;
}
fsl_asrc_select_clk(asrc_priv, pair,
config.input_sample_rate,
config.output_sample_rate);
ret = fsl_asrc_config_pair(pair, false);
if (ret) {
dev_err(dai->dev, "fail to config asrc pair\n");
return ret;
}
return 0;
}
static int fsl_asrc_dai_hw_free(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct fsl_asrc_pair *pair = runtime->private_data;
if (pair)
fsl_asrc_release_pair(pair);
return 0;
}
static int fsl_asrc_dai_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct fsl_asrc_pair *pair = runtime->private_data;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
fsl_asrc_start_pair(pair);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
fsl_asrc_stop_pair(pair);
break;
default:
return -EINVAL;
}
return 0;
}
static int fsl_asrc_dai_probe(struct snd_soc_dai *dai)
{
struct fsl_asrc *asrc = snd_soc_dai_get_drvdata(dai);
snd_soc_dai_init_dma_data(dai, &asrc->dma_params_tx,
&asrc->dma_params_rx);
return 0;
}
static const struct snd_soc_dai_ops fsl_asrc_dai_ops = {
.probe = fsl_asrc_dai_probe,
.startup = fsl_asrc_dai_startup,
.hw_params = fsl_asrc_dai_hw_params,
.hw_free = fsl_asrc_dai_hw_free,
.trigger = fsl_asrc_dai_trigger,
};
#define FSL_ASRC_FORMATS (SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_3LE)
static struct snd_soc_dai_driver fsl_asrc_dai = {
.playback = {
.stream_name = "ASRC-Playback",
.channels_min = 1,
.channels_max = 10,
.rate_min = 5512,
.rate_max = 192000,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = FSL_ASRC_FORMATS |
SNDRV_PCM_FMTBIT_S8,
},
.capture = {
.stream_name = "ASRC-Capture",
.channels_min = 1,
.channels_max = 10,
.rate_min = 5512,
.rate_max = 192000,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = FSL_ASRC_FORMATS,
},
.ops = &fsl_asrc_dai_ops,
};
static bool fsl_asrc_readable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case REG_ASRCTR:
case REG_ASRIER:
case REG_ASRCNCR:
case REG_ASRCFG:
case REG_ASRCSR:
case REG_ASRCDR1:
case REG_ASRCDR2:
case REG_ASRSTR:
case REG_ASRPM1:
case REG_ASRPM2:
case REG_ASRPM3:
case REG_ASRPM4:
case REG_ASRPM5:
case REG_ASRTFR1:
case REG_ASRCCR:
case REG_ASRDOA:
case REG_ASRDOB:
case REG_ASRDOC:
case REG_ASRIDRHA:
case REG_ASRIDRLA:
case REG_ASRIDRHB:
case REG_ASRIDRLB:
case REG_ASRIDRHC:
case REG_ASRIDRLC:
case REG_ASR76K:
case REG_ASR56K:
case REG_ASRMCRA:
case REG_ASRFSTA:
case REG_ASRMCRB:
case REG_ASRFSTB:
case REG_ASRMCRC:
case REG_ASRFSTC:
case REG_ASRMCR1A:
case REG_ASRMCR1B:
case REG_ASRMCR1C:
return true;
default:
return false;
}
}
static bool fsl_asrc_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case REG_ASRSTR:
case REG_ASRDIA:
case REG_ASRDIB:
case REG_ASRDIC:
case REG_ASRDOA:
case REG_ASRDOB:
case REG_ASRDOC:
case REG_ASRFSTA:
case REG_ASRFSTB:
case REG_ASRFSTC:
case REG_ASRCFG:
return true;
default:
return false;
}
}
static bool fsl_asrc_writeable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case REG_ASRCTR:
case REG_ASRIER:
case REG_ASRCNCR:
case REG_ASRCFG:
case REG_ASRCSR:
case REG_ASRCDR1:
case REG_ASRCDR2:
case REG_ASRSTR:
case REG_ASRPM1:
case REG_ASRPM2:
case REG_ASRPM3:
case REG_ASRPM4:
case REG_ASRPM5:
case REG_ASRTFR1:
case REG_ASRCCR:
case REG_ASRDIA:
case REG_ASRDIB:
case REG_ASRDIC:
case REG_ASRIDRHA:
case REG_ASRIDRLA:
case REG_ASRIDRHB:
case REG_ASRIDRLB:
case REG_ASRIDRHC:
case REG_ASRIDRLC:
case REG_ASR76K:
case REG_ASR56K:
case REG_ASRMCRA:
case REG_ASRMCRB:
case REG_ASRMCRC:
case REG_ASRMCR1A:
case REG_ASRMCR1B:
case REG_ASRMCR1C:
return true;
default:
return false;
}
}
static struct reg_default fsl_asrc_reg[] = {
{ REG_ASRCTR, 0x0000 }, { REG_ASRIER, 0x0000 },
{ REG_ASRCNCR, 0x0000 }, { REG_ASRCFG, 0x0000 },
{ REG_ASRCSR, 0x0000 }, { REG_ASRCDR1, 0x0000 },
{ REG_ASRCDR2, 0x0000 }, { REG_ASRSTR, 0x0000 },
{ REG_ASRRA, 0x0000 }, { REG_ASRRB, 0x0000 },
{ REG_ASRRC, 0x0000 }, { REG_ASRPM1, 0x0000 },
{ REG_ASRPM2, 0x0000 }, { REG_ASRPM3, 0x0000 },
{ REG_ASRPM4, 0x0000 }, { REG_ASRPM5, 0x0000 },
{ REG_ASRTFR1, 0x0000 }, { REG_ASRCCR, 0x0000 },
{ REG_ASRDIA, 0x0000 }, { REG_ASRDOA, 0x0000 },
{ REG_ASRDIB, 0x0000 }, { REG_ASRDOB, 0x0000 },
{ REG_ASRDIC, 0x0000 }, { REG_ASRDOC, 0x0000 },
{ REG_ASRIDRHA, 0x0000 }, { REG_ASRIDRLA, 0x0000 },
{ REG_ASRIDRHB, 0x0000 }, { REG_ASRIDRLB, 0x0000 },
{ REG_ASRIDRHC, 0x0000 }, { REG_ASRIDRLC, 0x0000 },
{ REG_ASR76K, 0x0A47 }, { REG_ASR56K, 0x0DF3 },
{ REG_ASRMCRA, 0x0000 }, { REG_ASRFSTA, 0x0000 },
{ REG_ASRMCRB, 0x0000 }, { REG_ASRFSTB, 0x0000 },
{ REG_ASRMCRC, 0x0000 }, { REG_ASRFSTC, 0x0000 },
{ REG_ASRMCR1A, 0x0000 }, { REG_ASRMCR1B, 0x0000 },
{ REG_ASRMCR1C, 0x0000 },
};
static const struct regmap_config fsl_asrc_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = REG_ASRMCR1C,
.reg_defaults = fsl_asrc_reg,
.num_reg_defaults = ARRAY_SIZE(fsl_asrc_reg),
.readable_reg = fsl_asrc_readable_reg,
.volatile_reg = fsl_asrc_volatile_reg,
.writeable_reg = fsl_asrc_writeable_reg,
.cache_type = REGCACHE_FLAT,
};
/**
* fsl_asrc_init - Initialize ASRC registers with a default configuration
* @asrc: ASRC context
*/
static int fsl_asrc_init(struct fsl_asrc *asrc)
{
unsigned long ipg_rate;
/* Halt ASRC internal FP when input FIFO needs data for pair A, B, C */
regmap_write(asrc->regmap, REG_ASRCTR, ASRCTR_ASRCEN);
/* Disable interrupt by default */
regmap_write(asrc->regmap, REG_ASRIER, 0x0);
/* Apply recommended settings for parameters from Reference Manual */
regmap_write(asrc->regmap, REG_ASRPM1, 0x7fffff);
regmap_write(asrc->regmap, REG_ASRPM2, 0x255555);
regmap_write(asrc->regmap, REG_ASRPM3, 0xff7280);
regmap_write(asrc->regmap, REG_ASRPM4, 0xff7280);
regmap_write(asrc->regmap, REG_ASRPM5, 0xff7280);
/* Base address for task queue FIFO. Set to 0x7C */
regmap_update_bits(asrc->regmap, REG_ASRTFR1,
ASRTFR1_TF_BASE_MASK, ASRTFR1_TF_BASE(0xfc));
/*
* Set the period of the 76KHz and 56KHz sampling clocks based on
* the ASRC processing clock.
* On iMX6, ipg_clk = 133MHz, REG_ASR76K = 0x06D6, REG_ASR56K = 0x0947
*/
ipg_rate = clk_get_rate(asrc->ipg_clk);
regmap_write(asrc->regmap, REG_ASR76K, ipg_rate / 76000);
return regmap_write(asrc->regmap, REG_ASR56K, ipg_rate / 56000);
}
/**
* fsl_asrc_isr- Interrupt handler for ASRC
* @irq: irq number
* @dev_id: ASRC context
*/
static irqreturn_t fsl_asrc_isr(int irq, void *dev_id)
{
struct fsl_asrc *asrc = (struct fsl_asrc *)dev_id;
struct device *dev = &asrc->pdev->dev;
enum asrc_pair_index index;
u32 status;
regmap_read(asrc->regmap, REG_ASRSTR, &status);
/* Clean overload error */
regmap_write(asrc->regmap, REG_ASRSTR, ASRSTR_AOLE);
/*
* We here use dev_dbg() for all exceptions because ASRC itself does
* not care if FIFO overflowed or underrun while a warning in the
* interrupt would result a ridged conversion.
*/
for (index = ASRC_PAIR_A; index < ASRC_PAIR_MAX_NUM; index++) {
if (!asrc->pair[index])
continue;
if (status & ASRSTR_ATQOL) {
asrc->pair[index]->error |= ASRC_TASK_Q_OVERLOAD;
dev_dbg(dev, "ASRC Task Queue FIFO overload\n");
}
if (status & ASRSTR_AOOL(index)) {
asrc->pair[index]->error |= ASRC_OUTPUT_TASK_OVERLOAD;
pair_dbg("Output Task Overload\n");
}
if (status & ASRSTR_AIOL(index)) {
asrc->pair[index]->error |= ASRC_INPUT_TASK_OVERLOAD;
pair_dbg("Input Task Overload\n");
}
if (status & ASRSTR_AODO(index)) {
asrc->pair[index]->error |= ASRC_OUTPUT_BUFFER_OVERFLOW;
pair_dbg("Output Data Buffer has overflowed\n");
}
if (status & ASRSTR_AIDU(index)) {
asrc->pair[index]->error |= ASRC_INPUT_BUFFER_UNDERRUN;
pair_dbg("Input Data Buffer has underflowed\n");
}
}
return IRQ_HANDLED;
}
static int fsl_asrc_get_fifo_addr(u8 dir, enum asrc_pair_index index)
{
return REG_ASRDx(dir, index);
}
static int fsl_asrc_runtime_resume(struct device *dev);
static int fsl_asrc_runtime_suspend(struct device *dev);
static int fsl_asrc_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct fsl_asrc_priv *asrc_priv;
struct fsl_asrc *asrc;
struct resource *res;
void __iomem *regs;
int irq, ret, i;
u32 asrc_fmt = 0;
u32 map_idx;
char tmp[16];
u32 width;
asrc = devm_kzalloc(&pdev->dev, sizeof(*asrc), GFP_KERNEL);
if (!asrc)
return -ENOMEM;
asrc_priv = devm_kzalloc(&pdev->dev, sizeof(*asrc_priv), GFP_KERNEL);
if (!asrc_priv)
return -ENOMEM;
asrc->pdev = pdev;
asrc->private = asrc_priv;
/* Get the addresses and IRQ */
regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(regs))
return PTR_ERR(regs);
asrc->paddr = res->start;
asrc->regmap = devm_regmap_init_mmio(&pdev->dev, regs, &fsl_asrc_regmap_config);
if (IS_ERR(asrc->regmap)) {
dev_err(&pdev->dev, "failed to init regmap\n");
return PTR_ERR(asrc->regmap);
}
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
ret = devm_request_irq(&pdev->dev, irq, fsl_asrc_isr, 0,
dev_name(&pdev->dev), asrc);
if (ret) {
dev_err(&pdev->dev, "failed to claim irq %u: %d\n", irq, ret);
return ret;
}
asrc->mem_clk = devm_clk_get(&pdev->dev, "mem");
if (IS_ERR(asrc->mem_clk)) {
dev_err(&pdev->dev, "failed to get mem clock\n");
return PTR_ERR(asrc->mem_clk);
}
asrc->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
if (IS_ERR(asrc->ipg_clk)) {
dev_err(&pdev->dev, "failed to get ipg clock\n");
return PTR_ERR(asrc->ipg_clk);
}
asrc->spba_clk = devm_clk_get(&pdev->dev, "spba");
if (IS_ERR(asrc->spba_clk))
dev_warn(&pdev->dev, "failed to get spba clock\n");
for (i = 0; i < ASRC_CLK_MAX_NUM; i++) {
sprintf(tmp, "asrck_%x", i);
asrc_priv->asrck_clk[i] = devm_clk_get(&pdev->dev, tmp);
if (IS_ERR(asrc_priv->asrck_clk[i])) {
dev_err(&pdev->dev, "failed to get %s clock\n", tmp);
return PTR_ERR(asrc_priv->asrck_clk[i]);
}
}
asrc_priv->soc = of_device_get_match_data(&pdev->dev);
asrc->use_edma = asrc_priv->soc->use_edma;
asrc->get_dma_channel = fsl_asrc_get_dma_channel;
asrc->request_pair = fsl_asrc_request_pair;
asrc->release_pair = fsl_asrc_release_pair;
asrc->get_fifo_addr = fsl_asrc_get_fifo_addr;
asrc->pair_priv_size = sizeof(struct fsl_asrc_pair_priv);
if (of_device_is_compatible(np, "fsl,imx35-asrc")) {
asrc_priv->clk_map[IN] = input_clk_map_imx35;
asrc_priv->clk_map[OUT] = output_clk_map_imx35;
} else if (of_device_is_compatible(np, "fsl,imx53-asrc")) {
asrc_priv->clk_map[IN] = input_clk_map_imx53;
asrc_priv->clk_map[OUT] = output_clk_map_imx53;
} else if (of_device_is_compatible(np, "fsl,imx8qm-asrc") ||
of_device_is_compatible(np, "fsl,imx8qxp-asrc")) {
ret = of_property_read_u32(np, "fsl,asrc-clk-map", &map_idx);
if (ret) {
dev_err(&pdev->dev, "failed to get clk map index\n");
return ret;
}
if (map_idx > 1) {
dev_err(&pdev->dev, "unsupported clk map index\n");
return -EINVAL;
}
if (of_device_is_compatible(np, "fsl,imx8qm-asrc")) {
asrc_priv->clk_map[IN] = clk_map_imx8qm[map_idx];
asrc_priv->clk_map[OUT] = clk_map_imx8qm[map_idx];
} else {
asrc_priv->clk_map[IN] = clk_map_imx8qxp[map_idx];
asrc_priv->clk_map[OUT] = clk_map_imx8qxp[map_idx];
}
}
asrc->channel_avail = 10;
ret = of_property_read_u32(np, "fsl,asrc-rate",
&asrc->asrc_rate);
if (ret) {
dev_err(&pdev->dev, "failed to get output rate\n");
return ret;
}
ret = of_property_read_u32(np, "fsl,asrc-format", &asrc_fmt);
asrc->asrc_format = (__force snd_pcm_format_t)asrc_fmt;
if (ret) {
ret = of_property_read_u32(np, "fsl,asrc-width", &width);
if (ret) {
dev_err(&pdev->dev, "failed to decide output format\n");
return ret;
}
switch (width) {
case 16:
asrc->asrc_format = SNDRV_PCM_FORMAT_S16_LE;
break;
case 24:
asrc->asrc_format = SNDRV_PCM_FORMAT_S24_LE;
break;
default:
dev_warn(&pdev->dev,
"unsupported width, use default S24_LE\n");
asrc->asrc_format = SNDRV_PCM_FORMAT_S24_LE;
break;
}
}
if (!(FSL_ASRC_FORMATS & pcm_format_to_bits(asrc->asrc_format))) {
dev_warn(&pdev->dev, "unsupported width, use default S24_LE\n");
asrc->asrc_format = SNDRV_PCM_FORMAT_S24_LE;
}
platform_set_drvdata(pdev, asrc);
spin_lock_init(&asrc->lock);
pm_runtime_enable(&pdev->dev);
if (!pm_runtime_enabled(&pdev->dev)) {
ret = fsl_asrc_runtime_resume(&pdev->dev);
if (ret)
goto err_pm_disable;
}
ret = pm_runtime_resume_and_get(&pdev->dev);
if (ret < 0)
goto err_pm_get_sync;
ret = fsl_asrc_init(asrc);
if (ret) {
dev_err(&pdev->dev, "failed to init asrc %d\n", ret);
goto err_pm_get_sync;
}
ret = pm_runtime_put_sync(&pdev->dev);
if (ret < 0 && ret != -ENOSYS)
goto err_pm_get_sync;
ret = devm_snd_soc_register_component(&pdev->dev, &fsl_asrc_component,
&fsl_asrc_dai, 1);
if (ret) {
dev_err(&pdev->dev, "failed to register ASoC DAI\n");
goto err_pm_get_sync;
}
return 0;
err_pm_get_sync:
if (!pm_runtime_status_suspended(&pdev->dev))
fsl_asrc_runtime_suspend(&pdev->dev);
err_pm_disable:
pm_runtime_disable(&pdev->dev);
return ret;
}
static void fsl_asrc_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
if (!pm_runtime_status_suspended(&pdev->dev))
fsl_asrc_runtime_suspend(&pdev->dev);
}
static int fsl_asrc_runtime_resume(struct device *dev)
{
struct fsl_asrc *asrc = dev_get_drvdata(dev);
struct fsl_asrc_priv *asrc_priv = asrc->private;
int reg, retry = INIT_RETRY_NUM;
int i, ret;
u32 asrctr;
ret = clk_prepare_enable(asrc->mem_clk);
if (ret)
return ret;
ret = clk_prepare_enable(asrc->ipg_clk);
if (ret)
goto disable_mem_clk;
if (!IS_ERR(asrc->spba_clk)) {
ret = clk_prepare_enable(asrc->spba_clk);
if (ret)
goto disable_ipg_clk;
}
for (i = 0; i < ASRC_CLK_MAX_NUM; i++) {
ret = clk_prepare_enable(asrc_priv->asrck_clk[i]);
if (ret)
goto disable_asrck_clk;
}
/* Stop all pairs provisionally */
regmap_read(asrc->regmap, REG_ASRCTR, &asrctr);
regmap_update_bits(asrc->regmap, REG_ASRCTR,
ASRCTR_ASRCEi_ALL_MASK, 0);
/* Restore all registers */
regcache_cache_only(asrc->regmap, false);
regcache_mark_dirty(asrc->regmap);
regcache_sync(asrc->regmap);
regmap_update_bits(asrc->regmap, REG_ASRCFG,
ASRCFG_NDPRi_ALL_MASK | ASRCFG_POSTMODi_ALL_MASK |
ASRCFG_PREMODi_ALL_MASK, asrc_priv->regcache_cfg);
/* Restart enabled pairs */
regmap_update_bits(asrc->regmap, REG_ASRCTR,
ASRCTR_ASRCEi_ALL_MASK, asrctr);
/* Wait for status of initialization for all enabled pairs */
do {
udelay(5);
regmap_read(asrc->regmap, REG_ASRCFG, ®);
reg = (reg >> ASRCFG_INIRQi_SHIFT(0)) & 0x7;
} while ((reg != ((asrctr >> ASRCTR_ASRCEi_SHIFT(0)) & 0x7)) && --retry);
/*
* NOTE: Doesn't treat initialization timeout as an error
* Some of the pairs may success, then still can continue.
*/
if (!retry) {
for (i = ASRC_PAIR_A; i < ASRC_PAIR_MAX_NUM; i++) {
if ((asrctr & ASRCTR_ASRCEi_MASK(i)) && !(reg & (1 << i)))
dev_warn(dev, "Pair %c initialization isn't finished\n", 'A' + i);
}
}
return 0;
disable_asrck_clk:
for (i--; i >= 0; i--)
clk_disable_unprepare(asrc_priv->asrck_clk[i]);
if (!IS_ERR(asrc->spba_clk))
clk_disable_unprepare(asrc->spba_clk);
disable_ipg_clk:
clk_disable_unprepare(asrc->ipg_clk);
disable_mem_clk:
clk_disable_unprepare(asrc->mem_clk);
return ret;
}
static int fsl_asrc_runtime_suspend(struct device *dev)
{
struct fsl_asrc *asrc = dev_get_drvdata(dev);
struct fsl_asrc_priv *asrc_priv = asrc->private;
int i;
regmap_read(asrc->regmap, REG_ASRCFG,
&asrc_priv->regcache_cfg);
regcache_cache_only(asrc->regmap, true);
for (i = 0; i < ASRC_CLK_MAX_NUM; i++)
clk_disable_unprepare(asrc_priv->asrck_clk[i]);
if (!IS_ERR(asrc->spba_clk))
clk_disable_unprepare(asrc->spba_clk);
clk_disable_unprepare(asrc->ipg_clk);
clk_disable_unprepare(asrc->mem_clk);
return 0;
}
static const struct dev_pm_ops fsl_asrc_pm = {
SET_RUNTIME_PM_OPS(fsl_asrc_runtime_suspend, fsl_asrc_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
};
static const struct fsl_asrc_soc_data fsl_asrc_imx35_data = {
.use_edma = false,
.channel_bits = 3,
};
static const struct fsl_asrc_soc_data fsl_asrc_imx53_data = {
.use_edma = false,
.channel_bits = 4,
};
static const struct fsl_asrc_soc_data fsl_asrc_imx8qm_data = {
.use_edma = true,
.channel_bits = 4,
};
static const struct fsl_asrc_soc_data fsl_asrc_imx8qxp_data = {
.use_edma = true,
.channel_bits = 4,
};
static const struct of_device_id fsl_asrc_ids[] = {
{ .compatible = "fsl,imx35-asrc", .data = &fsl_asrc_imx35_data },
{ .compatible = "fsl,imx53-asrc", .data = &fsl_asrc_imx53_data },
{ .compatible = "fsl,imx8qm-asrc", .data = &fsl_asrc_imx8qm_data },
{ .compatible = "fsl,imx8qxp-asrc", .data = &fsl_asrc_imx8qxp_data },
{}
};
MODULE_DEVICE_TABLE(of, fsl_asrc_ids);
static struct platform_driver fsl_asrc_driver = {
.probe = fsl_asrc_probe,
.remove_new = fsl_asrc_remove,
.driver = {
.name = "fsl-asrc",
.of_match_table = fsl_asrc_ids,
.pm = &fsl_asrc_pm,
},
};
module_platform_driver(fsl_asrc_driver);
MODULE_DESCRIPTION("Freescale ASRC ASoC driver");
MODULE_AUTHOR("Nicolin Chen <[email protected]>");
MODULE_ALIAS("platform:fsl-asrc");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/fsl/fsl_asrc.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright 2019 NXP
#include <linux/atomic.h>
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/firmware.h>
#include <linux/interrupt.h>
#include <linux/kobject.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/miscdevice.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/sched/signal.h>
#include <linux/sysfs.h>
#include <linux/types.h>
#include <linux/gcd.h>
#include <sound/dmaengine_pcm.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include <sound/core.h>
#include "fsl_easrc.h"
#include "imx-pcm.h"
#define FSL_EASRC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_U16_LE | \
SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S24_3LE | \
SNDRV_PCM_FMTBIT_U24_LE | \
SNDRV_PCM_FMTBIT_U24_3LE | \
SNDRV_PCM_FMTBIT_S32_LE | \
SNDRV_PCM_FMTBIT_U32_LE | \
SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_U20_3LE | \
SNDRV_PCM_FMTBIT_FLOAT_LE)
static int fsl_easrc_iec958_put_bits(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
struct fsl_asrc *easrc = snd_soc_component_get_drvdata(comp);
struct fsl_easrc_priv *easrc_priv = easrc->private;
struct soc_mreg_control *mc =
(struct soc_mreg_control *)kcontrol->private_value;
unsigned int regval = ucontrol->value.integer.value[0];
easrc_priv->bps_iec958[mc->regbase] = regval;
return 0;
}
static int fsl_easrc_iec958_get_bits(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
struct fsl_asrc *easrc = snd_soc_component_get_drvdata(comp);
struct fsl_easrc_priv *easrc_priv = easrc->private;
struct soc_mreg_control *mc =
(struct soc_mreg_control *)kcontrol->private_value;
ucontrol->value.enumerated.item[0] = easrc_priv->bps_iec958[mc->regbase];
return 0;
}
static int fsl_easrc_get_reg(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct soc_mreg_control *mc =
(struct soc_mreg_control *)kcontrol->private_value;
unsigned int regval;
regval = snd_soc_component_read(component, mc->regbase);
ucontrol->value.integer.value[0] = regval;
return 0;
}
static int fsl_easrc_set_reg(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct soc_mreg_control *mc =
(struct soc_mreg_control *)kcontrol->private_value;
unsigned int regval = ucontrol->value.integer.value[0];
int ret;
ret = snd_soc_component_write(component, mc->regbase, regval);
if (ret < 0)
return ret;
return 0;
}
#define SOC_SINGLE_REG_RW(xname, xreg) \
{ .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = (xname), \
.access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \
.info = snd_soc_info_xr_sx, .get = fsl_easrc_get_reg, \
.put = fsl_easrc_set_reg, \
.private_value = (unsigned long)&(struct soc_mreg_control) \
{ .regbase = xreg, .regcount = 1, .nbits = 32, \
.invert = 0, .min = 0, .max = 0xffffffff, } }
#define SOC_SINGLE_VAL_RW(xname, xreg) \
{ .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = (xname), \
.access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \
.info = snd_soc_info_xr_sx, .get = fsl_easrc_iec958_get_bits, \
.put = fsl_easrc_iec958_put_bits, \
.private_value = (unsigned long)&(struct soc_mreg_control) \
{ .regbase = xreg, .regcount = 1, .nbits = 32, \
.invert = 0, .min = 0, .max = 2, } }
static const struct snd_kcontrol_new fsl_easrc_snd_controls[] = {
SOC_SINGLE("Context 0 Dither Switch", REG_EASRC_COC(0), 0, 1, 0),
SOC_SINGLE("Context 1 Dither Switch", REG_EASRC_COC(1), 0, 1, 0),
SOC_SINGLE("Context 2 Dither Switch", REG_EASRC_COC(2), 0, 1, 0),
SOC_SINGLE("Context 3 Dither Switch", REG_EASRC_COC(3), 0, 1, 0),
SOC_SINGLE("Context 0 IEC958 Validity", REG_EASRC_COC(0), 2, 1, 0),
SOC_SINGLE("Context 1 IEC958 Validity", REG_EASRC_COC(1), 2, 1, 0),
SOC_SINGLE("Context 2 IEC958 Validity", REG_EASRC_COC(2), 2, 1, 0),
SOC_SINGLE("Context 3 IEC958 Validity", REG_EASRC_COC(3), 2, 1, 0),
SOC_SINGLE_VAL_RW("Context 0 IEC958 Bits Per Sample", 0),
SOC_SINGLE_VAL_RW("Context 1 IEC958 Bits Per Sample", 1),
SOC_SINGLE_VAL_RW("Context 2 IEC958 Bits Per Sample", 2),
SOC_SINGLE_VAL_RW("Context 3 IEC958 Bits Per Sample", 3),
SOC_SINGLE_REG_RW("Context 0 IEC958 CS0", REG_EASRC_CS0(0)),
SOC_SINGLE_REG_RW("Context 1 IEC958 CS0", REG_EASRC_CS0(1)),
SOC_SINGLE_REG_RW("Context 2 IEC958 CS0", REG_EASRC_CS0(2)),
SOC_SINGLE_REG_RW("Context 3 IEC958 CS0", REG_EASRC_CS0(3)),
SOC_SINGLE_REG_RW("Context 0 IEC958 CS1", REG_EASRC_CS1(0)),
SOC_SINGLE_REG_RW("Context 1 IEC958 CS1", REG_EASRC_CS1(1)),
SOC_SINGLE_REG_RW("Context 2 IEC958 CS1", REG_EASRC_CS1(2)),
SOC_SINGLE_REG_RW("Context 3 IEC958 CS1", REG_EASRC_CS1(3)),
SOC_SINGLE_REG_RW("Context 0 IEC958 CS2", REG_EASRC_CS2(0)),
SOC_SINGLE_REG_RW("Context 1 IEC958 CS2", REG_EASRC_CS2(1)),
SOC_SINGLE_REG_RW("Context 2 IEC958 CS2", REG_EASRC_CS2(2)),
SOC_SINGLE_REG_RW("Context 3 IEC958 CS2", REG_EASRC_CS2(3)),
SOC_SINGLE_REG_RW("Context 0 IEC958 CS3", REG_EASRC_CS3(0)),
SOC_SINGLE_REG_RW("Context 1 IEC958 CS3", REG_EASRC_CS3(1)),
SOC_SINGLE_REG_RW("Context 2 IEC958 CS3", REG_EASRC_CS3(2)),
SOC_SINGLE_REG_RW("Context 3 IEC958 CS3", REG_EASRC_CS3(3)),
SOC_SINGLE_REG_RW("Context 0 IEC958 CS4", REG_EASRC_CS4(0)),
SOC_SINGLE_REG_RW("Context 1 IEC958 CS4", REG_EASRC_CS4(1)),
SOC_SINGLE_REG_RW("Context 2 IEC958 CS4", REG_EASRC_CS4(2)),
SOC_SINGLE_REG_RW("Context 3 IEC958 CS4", REG_EASRC_CS4(3)),
SOC_SINGLE_REG_RW("Context 0 IEC958 CS5", REG_EASRC_CS5(0)),
SOC_SINGLE_REG_RW("Context 1 IEC958 CS5", REG_EASRC_CS5(1)),
SOC_SINGLE_REG_RW("Context 2 IEC958 CS5", REG_EASRC_CS5(2)),
SOC_SINGLE_REG_RW("Context 3 IEC958 CS5", REG_EASRC_CS5(3)),
};
/*
* fsl_easrc_set_rs_ratio
*
* According to the resample taps, calculate the resample ratio
* ratio = in_rate / out_rate
*/
static int fsl_easrc_set_rs_ratio(struct fsl_asrc_pair *ctx)
{
struct fsl_asrc *easrc = ctx->asrc;
struct fsl_easrc_priv *easrc_priv = easrc->private;
struct fsl_easrc_ctx_priv *ctx_priv = ctx->private;
unsigned int in_rate = ctx_priv->in_params.norm_rate;
unsigned int out_rate = ctx_priv->out_params.norm_rate;
unsigned int frac_bits;
u64 val;
u32 *r;
switch (easrc_priv->rs_num_taps) {
case EASRC_RS_32_TAPS:
/* integer bits = 5; */
frac_bits = 39;
break;
case EASRC_RS_64_TAPS:
/* integer bits = 6; */
frac_bits = 38;
break;
case EASRC_RS_128_TAPS:
/* integer bits = 7; */
frac_bits = 37;
break;
default:
return -EINVAL;
}
val = (u64)in_rate << frac_bits;
do_div(val, out_rate);
r = (uint32_t *)&val;
if (r[1] & 0xFFFFF000) {
dev_err(&easrc->pdev->dev, "ratio exceed range\n");
return -EINVAL;
}
regmap_write(easrc->regmap, REG_EASRC_RRL(ctx->index),
EASRC_RRL_RS_RL(r[0]));
regmap_write(easrc->regmap, REG_EASRC_RRH(ctx->index),
EASRC_RRH_RS_RH(r[1]));
return 0;
}
/* Normalize input and output sample rates */
static void fsl_easrc_normalize_rates(struct fsl_asrc_pair *ctx)
{
struct fsl_easrc_ctx_priv *ctx_priv;
int a, b;
if (!ctx)
return;
ctx_priv = ctx->private;
a = ctx_priv->in_params.sample_rate;
b = ctx_priv->out_params.sample_rate;
a = gcd(a, b);
/* Divide by gcd to normalize the rate */
ctx_priv->in_params.norm_rate = ctx_priv->in_params.sample_rate / a;
ctx_priv->out_params.norm_rate = ctx_priv->out_params.sample_rate / a;
}
/* Resets the pointer of the coeff memory pointers */
static int fsl_easrc_coeff_mem_ptr_reset(struct fsl_asrc *easrc,
unsigned int ctx_id, int mem_type)
{
struct device *dev;
u32 reg, mask, val;
if (!easrc)
return -ENODEV;
dev = &easrc->pdev->dev;
switch (mem_type) {
case EASRC_PF_COEFF_MEM:
/* This resets the prefilter memory pointer addr */
if (ctx_id >= EASRC_CTX_MAX_NUM) {
dev_err(dev, "Invalid context id[%d]\n", ctx_id);
return -EINVAL;
}
reg = REG_EASRC_CCE1(ctx_id);
mask = EASRC_CCE1_COEF_MEM_RST_MASK;
val = EASRC_CCE1_COEF_MEM_RST;
break;
case EASRC_RS_COEFF_MEM:
/* This resets the resampling memory pointer addr */
reg = REG_EASRC_CRCC;
mask = EASRC_CRCC_RS_CPR_MASK;
val = EASRC_CRCC_RS_CPR;
break;
default:
dev_err(dev, "Unknown memory type\n");
return -EINVAL;
}
/*
* To reset the write pointer back to zero, the register field
* ASRC_CTX_CTRL_EXT1x[PF_COEFF_MEM_RST] can be toggled from
* 0x0 to 0x1 to 0x0.
*/
regmap_update_bits(easrc->regmap, reg, mask, 0);
regmap_update_bits(easrc->regmap, reg, mask, val);
regmap_update_bits(easrc->regmap, reg, mask, 0);
return 0;
}
static inline uint32_t bits_taps_to_val(unsigned int t)
{
switch (t) {
case EASRC_RS_32_TAPS:
return 32;
case EASRC_RS_64_TAPS:
return 64;
case EASRC_RS_128_TAPS:
return 128;
}
return 0;
}
static int fsl_easrc_resampler_config(struct fsl_asrc *easrc)
{
struct device *dev = &easrc->pdev->dev;
struct fsl_easrc_priv *easrc_priv = easrc->private;
struct asrc_firmware_hdr *hdr = easrc_priv->firmware_hdr;
struct interp_params *interp = easrc_priv->interp;
struct interp_params *selected_interp = NULL;
unsigned int num_coeff;
unsigned int i;
u64 *coef;
u32 *r;
int ret;
if (!hdr) {
dev_err(dev, "firmware not loaded!\n");
return -ENODEV;
}
for (i = 0; i < hdr->interp_scen; i++) {
if ((interp[i].num_taps - 1) !=
bits_taps_to_val(easrc_priv->rs_num_taps))
continue;
coef = interp[i].coeff;
selected_interp = &interp[i];
dev_dbg(dev, "Selected interp_filter: %u taps - %u phases\n",
selected_interp->num_taps,
selected_interp->num_phases);
break;
}
if (!selected_interp) {
dev_err(dev, "failed to get interpreter configuration\n");
return -EINVAL;
}
/*
* RS_LOW - first half of center tap of the sinc function
* RS_HIGH - second half of center tap of the sinc function
* This is due to the fact the resampling function must be
* symetrical - i.e. odd number of taps
*/
r = (uint32_t *)&selected_interp->center_tap;
regmap_write(easrc->regmap, REG_EASRC_RCTCL, EASRC_RCTCL_RS_CL(r[0]));
regmap_write(easrc->regmap, REG_EASRC_RCTCH, EASRC_RCTCH_RS_CH(r[1]));
/*
* Write Number of Resampling Coefficient Taps
* 00b - 32-Tap Resampling Filter
* 01b - 64-Tap Resampling Filter
* 10b - 128-Tap Resampling Filter
* 11b - N/A
*/
regmap_update_bits(easrc->regmap, REG_EASRC_CRCC,
EASRC_CRCC_RS_TAPS_MASK,
EASRC_CRCC_RS_TAPS(easrc_priv->rs_num_taps));
/* Reset prefilter coefficient pointer back to 0 */
ret = fsl_easrc_coeff_mem_ptr_reset(easrc, 0, EASRC_RS_COEFF_MEM);
if (ret)
return ret;
/*
* When the filter is programmed to run in:
* 32-tap mode, 16-taps, 128-phases 4-coefficients per phase
* 64-tap mode, 32-taps, 64-phases 4-coefficients per phase
* 128-tap mode, 64-taps, 32-phases 4-coefficients per phase
* This means the number of writes is constant no matter
* the mode we are using
*/
num_coeff = 16 * 128 * 4;
for (i = 0; i < num_coeff; i++) {
r = (uint32_t *)&coef[i];
regmap_write(easrc->regmap, REG_EASRC_CRCM,
EASRC_CRCM_RS_CWD(r[0]));
regmap_write(easrc->regmap, REG_EASRC_CRCM,
EASRC_CRCM_RS_CWD(r[1]));
}
return 0;
}
/**
* fsl_easrc_normalize_filter - Scale filter coefficients (64 bits float)
* For input float32 normalized range (1.0,-1.0) -> output int[16,24,32]:
* scale it by multiplying filter coefficients by 2^31
* For input int[16, 24, 32] -> output float32
* scale it by multiplying filter coefficients by 2^-15, 2^-23, 2^-31
* input:
* @easrc: Structure pointer of fsl_asrc
* @infilter : Pointer to non-scaled input filter
* @shift: The multiply factor
* output:
* @outfilter: scaled filter
*/
static int fsl_easrc_normalize_filter(struct fsl_asrc *easrc,
u64 *infilter,
u64 *outfilter,
int shift)
{
struct device *dev = &easrc->pdev->dev;
u64 coef = *infilter;
s64 exp = (coef & 0x7ff0000000000000ll) >> 52;
u64 outcoef;
/*
* If exponent is zero (value == 0), or 7ff (value == NaNs)
* dont touch the content
*/
if (exp == 0 || exp == 0x7ff) {
*outfilter = coef;
return 0;
}
/* coef * 2^shift ==> exp + shift */
exp += shift;
if ((shift > 0 && exp >= 0x7ff) || (shift < 0 && exp <= 0)) {
dev_err(dev, "coef out of range\n");
return -EINVAL;
}
outcoef = (u64)(coef & 0x800FFFFFFFFFFFFFll) + ((u64)exp << 52);
*outfilter = outcoef;
return 0;
}
static int fsl_easrc_write_pf_coeff_mem(struct fsl_asrc *easrc, int ctx_id,
u64 *coef, int n_taps, int shift)
{
struct device *dev = &easrc->pdev->dev;
int ret = 0;
int i;
u32 *r;
u64 tmp;
/* If STx_NUM_TAPS is set to 0x0 then return */
if (!n_taps)
return 0;
if (!coef) {
dev_err(dev, "coef table is NULL\n");
return -EINVAL;
}
/*
* When switching between stages, the address pointer
* should be reset back to 0x0 before performing a write
*/
ret = fsl_easrc_coeff_mem_ptr_reset(easrc, ctx_id, EASRC_PF_COEFF_MEM);
if (ret)
return ret;
for (i = 0; i < (n_taps + 1) / 2; i++) {
ret = fsl_easrc_normalize_filter(easrc, &coef[i], &tmp, shift);
if (ret)
return ret;
r = (uint32_t *)&tmp;
regmap_write(easrc->regmap, REG_EASRC_PCF(ctx_id),
EASRC_PCF_CD(r[0]));
regmap_write(easrc->regmap, REG_EASRC_PCF(ctx_id),
EASRC_PCF_CD(r[1]));
}
return 0;
}
static int fsl_easrc_prefilter_config(struct fsl_asrc *easrc,
unsigned int ctx_id)
{
struct prefil_params *prefil, *selected_prefil = NULL;
struct fsl_easrc_ctx_priv *ctx_priv;
struct fsl_easrc_priv *easrc_priv;
struct asrc_firmware_hdr *hdr;
struct fsl_asrc_pair *ctx;
struct device *dev;
u32 inrate, outrate, offset = 0;
u32 in_s_rate, out_s_rate;
snd_pcm_format_t in_s_fmt, out_s_fmt;
int ret, i;
if (!easrc)
return -ENODEV;
dev = &easrc->pdev->dev;
if (ctx_id >= EASRC_CTX_MAX_NUM) {
dev_err(dev, "Invalid context id[%d]\n", ctx_id);
return -EINVAL;
}
easrc_priv = easrc->private;
ctx = easrc->pair[ctx_id];
ctx_priv = ctx->private;
in_s_rate = ctx_priv->in_params.sample_rate;
out_s_rate = ctx_priv->out_params.sample_rate;
in_s_fmt = ctx_priv->in_params.sample_format;
out_s_fmt = ctx_priv->out_params.sample_format;
ctx_priv->in_filled_sample = bits_taps_to_val(easrc_priv->rs_num_taps) / 2;
ctx_priv->out_missed_sample = ctx_priv->in_filled_sample * out_s_rate / in_s_rate;
ctx_priv->st1_num_taps = 0;
ctx_priv->st2_num_taps = 0;
regmap_write(easrc->regmap, REG_EASRC_CCE1(ctx_id), 0);
regmap_write(easrc->regmap, REG_EASRC_CCE2(ctx_id), 0);
/*
* The audio float point data range is (-1, 1), the asrc would output
* all zero for float point input and integer output case, that is to
* drop the fractional part of the data directly.
*
* In order to support float to int conversion or int to float
* conversion we need to do special operation on the coefficient to
* enlarge/reduce the data to the expected range.
*
* For float to int case:
* Up sampling:
* 1. Create a 1 tap filter with center tap (only tap) of 2^31
* in 64 bits floating point.
* double value = (double)(((uint64_t)1) << 31)
* 2. Program 1 tap prefilter with center tap above.
*
* Down sampling,
* 1. If the filter is single stage filter, add "shift" to the exponent
* of stage 1 coefficients.
* 2. If the filter is two stage filter , add "shift" to the exponent
* of stage 2 coefficients.
*
* The "shift" is 31, same for int16, int24, int32 case.
*
* For int to float case:
* Up sampling:
* 1. Create a 1 tap filter with center tap (only tap) of 2^-31
* in 64 bits floating point.
* 2. Program 1 tap prefilter with center tap above.
*
* Down sampling,
* 1. If the filter is single stage filter, subtract "shift" to the
* exponent of stage 1 coefficients.
* 2. If the filter is two stage filter , subtract "shift" to the
* exponent of stage 2 coefficients.
*
* The "shift" is 15,23,31, different for int16, int24, int32 case.
*
*/
if (out_s_rate >= in_s_rate) {
if (out_s_rate == in_s_rate)
regmap_update_bits(easrc->regmap,
REG_EASRC_CCE1(ctx_id),
EASRC_CCE1_RS_BYPASS_MASK,
EASRC_CCE1_RS_BYPASS);
ctx_priv->st1_num_taps = 1;
ctx_priv->st1_coeff = &easrc_priv->const_coeff;
ctx_priv->st1_num_exp = 1;
ctx_priv->st2_num_taps = 0;
if (in_s_fmt == SNDRV_PCM_FORMAT_FLOAT_LE &&
out_s_fmt != SNDRV_PCM_FORMAT_FLOAT_LE)
ctx_priv->st1_addexp = 31;
else if (in_s_fmt != SNDRV_PCM_FORMAT_FLOAT_LE &&
out_s_fmt == SNDRV_PCM_FORMAT_FLOAT_LE)
ctx_priv->st1_addexp -= ctx_priv->in_params.fmt.addexp;
} else {
inrate = ctx_priv->in_params.norm_rate;
outrate = ctx_priv->out_params.norm_rate;
hdr = easrc_priv->firmware_hdr;
prefil = easrc_priv->prefil;
for (i = 0; i < hdr->prefil_scen; i++) {
if (inrate == prefil[i].insr &&
outrate == prefil[i].outsr) {
selected_prefil = &prefil[i];
dev_dbg(dev, "Selected prefilter: %u insr, %u outsr, %u st1_taps, %u st2_taps\n",
selected_prefil->insr,
selected_prefil->outsr,
selected_prefil->st1_taps,
selected_prefil->st2_taps);
break;
}
}
if (!selected_prefil) {
dev_err(dev, "Conversion from in ratio %u(%u) to out ratio %u(%u) is not supported\n",
in_s_rate, inrate,
out_s_rate, outrate);
return -EINVAL;
}
/*
* In prefilter coeff array, first st1_num_taps represent the
* stage1 prefilter coefficients followed by next st2_num_taps
* representing stage 2 coefficients
*/
ctx_priv->st1_num_taps = selected_prefil->st1_taps;
ctx_priv->st1_coeff = selected_prefil->coeff;
ctx_priv->st1_num_exp = selected_prefil->st1_exp;
offset = ((selected_prefil->st1_taps + 1) / 2);
ctx_priv->st2_num_taps = selected_prefil->st2_taps;
ctx_priv->st2_coeff = selected_prefil->coeff + offset;
if (in_s_fmt == SNDRV_PCM_FORMAT_FLOAT_LE &&
out_s_fmt != SNDRV_PCM_FORMAT_FLOAT_LE) {
/* only change stage2 coefficient for 2 stage case */
if (ctx_priv->st2_num_taps > 0)
ctx_priv->st2_addexp = 31;
else
ctx_priv->st1_addexp = 31;
} else if (in_s_fmt != SNDRV_PCM_FORMAT_FLOAT_LE &&
out_s_fmt == SNDRV_PCM_FORMAT_FLOAT_LE) {
if (ctx_priv->st2_num_taps > 0)
ctx_priv->st2_addexp -= ctx_priv->in_params.fmt.addexp;
else
ctx_priv->st1_addexp -= ctx_priv->in_params.fmt.addexp;
}
}
ctx_priv->in_filled_sample += (ctx_priv->st1_num_taps / 2) * ctx_priv->st1_num_exp +
ctx_priv->st2_num_taps / 2;
ctx_priv->out_missed_sample = ctx_priv->in_filled_sample * out_s_rate / in_s_rate;
if (ctx_priv->in_filled_sample * out_s_rate % in_s_rate != 0)
ctx_priv->out_missed_sample += 1;
/*
* To modify the value of a prefilter coefficient, the user must
* perform a write to the register ASRC_PRE_COEFF_FIFOn[COEFF_DATA]
* while the respective context RUN_EN bit is set to 0b0
*/
regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx_id),
EASRC_CC_EN_MASK, 0);
if (ctx_priv->st1_num_taps > EASRC_MAX_PF_TAPS) {
dev_err(dev, "ST1 taps [%d] mus be lower than %d\n",
ctx_priv->st1_num_taps, EASRC_MAX_PF_TAPS);
ret = -EINVAL;
goto ctx_error;
}
/* Update ctx ST1_NUM_TAPS in Context Control Extended 2 register */
regmap_update_bits(easrc->regmap, REG_EASRC_CCE2(ctx_id),
EASRC_CCE2_ST1_TAPS_MASK,
EASRC_CCE2_ST1_TAPS(ctx_priv->st1_num_taps - 1));
/* Prefilter Coefficient Write Select to write in ST1 coeff */
regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id),
EASRC_CCE1_COEF_WS_MASK,
EASRC_PF_ST1_COEFF_WR << EASRC_CCE1_COEF_WS_SHIFT);
ret = fsl_easrc_write_pf_coeff_mem(easrc, ctx_id,
ctx_priv->st1_coeff,
ctx_priv->st1_num_taps,
ctx_priv->st1_addexp);
if (ret)
goto ctx_error;
if (ctx_priv->st2_num_taps > 0) {
if (ctx_priv->st2_num_taps + ctx_priv->st1_num_taps > EASRC_MAX_PF_TAPS) {
dev_err(dev, "ST2 taps [%d] mus be lower than %d\n",
ctx_priv->st2_num_taps, EASRC_MAX_PF_TAPS);
ret = -EINVAL;
goto ctx_error;
}
regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id),
EASRC_CCE1_PF_TSEN_MASK,
EASRC_CCE1_PF_TSEN);
/*
* Enable prefilter stage1 writeback floating point
* which is used for FLOAT_LE case
*/
regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id),
EASRC_CCE1_PF_ST1_WBFP_MASK,
EASRC_CCE1_PF_ST1_WBFP);
regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id),
EASRC_CCE1_PF_EXP_MASK,
EASRC_CCE1_PF_EXP(ctx_priv->st1_num_exp - 1));
/* Update ctx ST2_NUM_TAPS in Context Control Extended 2 reg */
regmap_update_bits(easrc->regmap, REG_EASRC_CCE2(ctx_id),
EASRC_CCE2_ST2_TAPS_MASK,
EASRC_CCE2_ST2_TAPS(ctx_priv->st2_num_taps - 1));
/* Prefilter Coefficient Write Select to write in ST2 coeff */
regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id),
EASRC_CCE1_COEF_WS_MASK,
EASRC_PF_ST2_COEFF_WR << EASRC_CCE1_COEF_WS_SHIFT);
ret = fsl_easrc_write_pf_coeff_mem(easrc, ctx_id,
ctx_priv->st2_coeff,
ctx_priv->st2_num_taps,
ctx_priv->st2_addexp);
if (ret)
goto ctx_error;
}
return 0;
ctx_error:
return ret;
}
static int fsl_easrc_max_ch_for_slot(struct fsl_asrc_pair *ctx,
struct fsl_easrc_slot *slot)
{
struct fsl_easrc_ctx_priv *ctx_priv = ctx->private;
int st1_mem_alloc = 0, st2_mem_alloc = 0;
int pf_mem_alloc = 0;
int max_channels = 8 - slot->num_channel;
int channels = 0;
if (ctx_priv->st1_num_taps > 0) {
if (ctx_priv->st2_num_taps > 0)
st1_mem_alloc =
(ctx_priv->st1_num_taps - 1) * ctx_priv->st1_num_exp + 1;
else
st1_mem_alloc = ctx_priv->st1_num_taps;
}
if (ctx_priv->st2_num_taps > 0)
st2_mem_alloc = ctx_priv->st2_num_taps;
pf_mem_alloc = st1_mem_alloc + st2_mem_alloc;
if (pf_mem_alloc != 0)
channels = (6144 - slot->pf_mem_used) / pf_mem_alloc;
else
channels = 8;
if (channels < max_channels)
max_channels = channels;
return max_channels;
}
static int fsl_easrc_config_one_slot(struct fsl_asrc_pair *ctx,
struct fsl_easrc_slot *slot,
unsigned int slot_ctx_idx,
unsigned int *req_channels,
unsigned int *start_channel,
unsigned int *avail_channel)
{
struct fsl_asrc *easrc = ctx->asrc;
struct fsl_easrc_ctx_priv *ctx_priv = ctx->private;
int st1_chanxexp, st1_mem_alloc = 0, st2_mem_alloc;
unsigned int reg0, reg1, reg2, reg3;
unsigned int addr;
if (slot->slot_index == 0) {
reg0 = REG_EASRC_DPCS0R0(slot_ctx_idx);
reg1 = REG_EASRC_DPCS0R1(slot_ctx_idx);
reg2 = REG_EASRC_DPCS0R2(slot_ctx_idx);
reg3 = REG_EASRC_DPCS0R3(slot_ctx_idx);
} else {
reg0 = REG_EASRC_DPCS1R0(slot_ctx_idx);
reg1 = REG_EASRC_DPCS1R1(slot_ctx_idx);
reg2 = REG_EASRC_DPCS1R2(slot_ctx_idx);
reg3 = REG_EASRC_DPCS1R3(slot_ctx_idx);
}
if (*req_channels <= *avail_channel) {
slot->num_channel = *req_channels;
*req_channels = 0;
} else {
slot->num_channel = *avail_channel;
*req_channels -= *avail_channel;
}
slot->min_channel = *start_channel;
slot->max_channel = *start_channel + slot->num_channel - 1;
slot->ctx_index = ctx->index;
slot->busy = true;
*start_channel += slot->num_channel;
regmap_update_bits(easrc->regmap, reg0,
EASRC_DPCS0R0_MAXCH_MASK,
EASRC_DPCS0R0_MAXCH(slot->max_channel));
regmap_update_bits(easrc->regmap, reg0,
EASRC_DPCS0R0_MINCH_MASK,
EASRC_DPCS0R0_MINCH(slot->min_channel));
regmap_update_bits(easrc->regmap, reg0,
EASRC_DPCS0R0_NUMCH_MASK,
EASRC_DPCS0R0_NUMCH(slot->num_channel - 1));
regmap_update_bits(easrc->regmap, reg0,
EASRC_DPCS0R0_CTXNUM_MASK,
EASRC_DPCS0R0_CTXNUM(slot->ctx_index));
if (ctx_priv->st1_num_taps > 0) {
if (ctx_priv->st2_num_taps > 0)
st1_mem_alloc =
(ctx_priv->st1_num_taps - 1) * slot->num_channel *
ctx_priv->st1_num_exp + slot->num_channel;
else
st1_mem_alloc = ctx_priv->st1_num_taps * slot->num_channel;
slot->pf_mem_used = st1_mem_alloc;
regmap_update_bits(easrc->regmap, reg2,
EASRC_DPCS0R2_ST1_MA_MASK,
EASRC_DPCS0R2_ST1_MA(st1_mem_alloc));
if (slot->slot_index == 1)
addr = PREFILTER_MEM_LEN - st1_mem_alloc;
else
addr = 0;
regmap_update_bits(easrc->regmap, reg2,
EASRC_DPCS0R2_ST1_SA_MASK,
EASRC_DPCS0R2_ST1_SA(addr));
}
if (ctx_priv->st2_num_taps > 0) {
st1_chanxexp = slot->num_channel * (ctx_priv->st1_num_exp - 1);
regmap_update_bits(easrc->regmap, reg1,
EASRC_DPCS0R1_ST1_EXP_MASK,
EASRC_DPCS0R1_ST1_EXP(st1_chanxexp));
st2_mem_alloc = slot->num_channel * ctx_priv->st2_num_taps;
slot->pf_mem_used += st2_mem_alloc;
regmap_update_bits(easrc->regmap, reg3,
EASRC_DPCS0R3_ST2_MA_MASK,
EASRC_DPCS0R3_ST2_MA(st2_mem_alloc));
if (slot->slot_index == 1)
addr = PREFILTER_MEM_LEN - st1_mem_alloc - st2_mem_alloc;
else
addr = st1_mem_alloc;
regmap_update_bits(easrc->regmap, reg3,
EASRC_DPCS0R3_ST2_SA_MASK,
EASRC_DPCS0R3_ST2_SA(addr));
}
regmap_update_bits(easrc->regmap, reg0,
EASRC_DPCS0R0_EN_MASK, EASRC_DPCS0R0_EN);
return 0;
}
/*
* fsl_easrc_config_slot
*
* A single context can be split amongst any of the 4 context processing pipes
* in the design.
* The total number of channels consumed within the context processor must be
* less than or equal to 8. if a single context is configured to contain more
* than 8 channels then it must be distributed across multiple context
* processing pipe slots.
*
*/
static int fsl_easrc_config_slot(struct fsl_asrc *easrc, unsigned int ctx_id)
{
struct fsl_easrc_priv *easrc_priv = easrc->private;
struct fsl_asrc_pair *ctx = easrc->pair[ctx_id];
int req_channels = ctx->channels;
int start_channel = 0, avail_channel;
struct fsl_easrc_slot *slot0, *slot1;
struct fsl_easrc_slot *slota, *slotb;
int i, ret;
if (req_channels <= 0)
return -EINVAL;
for (i = 0; i < EASRC_CTX_MAX_NUM; i++) {
slot0 = &easrc_priv->slot[i][0];
slot1 = &easrc_priv->slot[i][1];
if (slot0->busy && slot1->busy) {
continue;
} else if ((slot0->busy && slot0->ctx_index == ctx->index) ||
(slot1->busy && slot1->ctx_index == ctx->index)) {
continue;
} else if (!slot0->busy) {
slota = slot0;
slotb = slot1;
slota->slot_index = 0;
} else if (!slot1->busy) {
slota = slot1;
slotb = slot0;
slota->slot_index = 1;
}
if (!slota || !slotb)
continue;
avail_channel = fsl_easrc_max_ch_for_slot(ctx, slotb);
if (avail_channel <= 0)
continue;
ret = fsl_easrc_config_one_slot(ctx, slota, i, &req_channels,
&start_channel, &avail_channel);
if (ret)
return ret;
if (req_channels > 0)
continue;
else
break;
}
if (req_channels > 0) {
dev_err(&easrc->pdev->dev, "no avail slot.\n");
return -EINVAL;
}
return 0;
}
/*
* fsl_easrc_release_slot
*
* Clear the slot configuration
*/
static int fsl_easrc_release_slot(struct fsl_asrc *easrc, unsigned int ctx_id)
{
struct fsl_easrc_priv *easrc_priv = easrc->private;
struct fsl_asrc_pair *ctx = easrc->pair[ctx_id];
int i;
for (i = 0; i < EASRC_CTX_MAX_NUM; i++) {
if (easrc_priv->slot[i][0].busy &&
easrc_priv->slot[i][0].ctx_index == ctx->index) {
easrc_priv->slot[i][0].busy = false;
easrc_priv->slot[i][0].num_channel = 0;
easrc_priv->slot[i][0].pf_mem_used = 0;
/* set registers */
regmap_write(easrc->regmap, REG_EASRC_DPCS0R0(i), 0);
regmap_write(easrc->regmap, REG_EASRC_DPCS0R1(i), 0);
regmap_write(easrc->regmap, REG_EASRC_DPCS0R2(i), 0);
regmap_write(easrc->regmap, REG_EASRC_DPCS0R3(i), 0);
}
if (easrc_priv->slot[i][1].busy &&
easrc_priv->slot[i][1].ctx_index == ctx->index) {
easrc_priv->slot[i][1].busy = false;
easrc_priv->slot[i][1].num_channel = 0;
easrc_priv->slot[i][1].pf_mem_used = 0;
/* set registers */
regmap_write(easrc->regmap, REG_EASRC_DPCS1R0(i), 0);
regmap_write(easrc->regmap, REG_EASRC_DPCS1R1(i), 0);
regmap_write(easrc->regmap, REG_EASRC_DPCS1R2(i), 0);
regmap_write(easrc->regmap, REG_EASRC_DPCS1R3(i), 0);
}
}
return 0;
}
/*
* fsl_easrc_config_context
*
* Configure the register relate with context.
*/
static int fsl_easrc_config_context(struct fsl_asrc *easrc, unsigned int ctx_id)
{
struct fsl_easrc_ctx_priv *ctx_priv;
struct fsl_asrc_pair *ctx;
struct device *dev;
unsigned long lock_flags;
int ret;
if (!easrc)
return -ENODEV;
dev = &easrc->pdev->dev;
if (ctx_id >= EASRC_CTX_MAX_NUM) {
dev_err(dev, "Invalid context id[%d]\n", ctx_id);
return -EINVAL;
}
ctx = easrc->pair[ctx_id];
ctx_priv = ctx->private;
fsl_easrc_normalize_rates(ctx);
ret = fsl_easrc_set_rs_ratio(ctx);
if (ret)
return ret;
/* Initialize the context coeficients */
ret = fsl_easrc_prefilter_config(easrc, ctx->index);
if (ret)
return ret;
spin_lock_irqsave(&easrc->lock, lock_flags);
ret = fsl_easrc_config_slot(easrc, ctx->index);
spin_unlock_irqrestore(&easrc->lock, lock_flags);
if (ret)
return ret;
/*
* Both prefilter and resampling filters can use following
* initialization modes:
* 2 - zero-fil mode
* 1 - replication mode
* 0 - software control
*/
regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id),
EASRC_CCE1_RS_INIT_MASK,
EASRC_CCE1_RS_INIT(ctx_priv->rs_init_mode));
regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id),
EASRC_CCE1_PF_INIT_MASK,
EASRC_CCE1_PF_INIT(ctx_priv->pf_init_mode));
/*
* Context Input FIFO Watermark
* DMA request is generated when input FIFO < FIFO_WTMK
*/
regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx_id),
EASRC_CC_FIFO_WTMK_MASK,
EASRC_CC_FIFO_WTMK(ctx_priv->in_params.fifo_wtmk));
/*
* Context Output FIFO Watermark
* DMA request is generated when output FIFO > FIFO_WTMK
* So we set fifo_wtmk -1 to register.
*/
regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx_id),
EASRC_COC_FIFO_WTMK_MASK,
EASRC_COC_FIFO_WTMK(ctx_priv->out_params.fifo_wtmk - 1));
/* Number of channels */
regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx_id),
EASRC_CC_CHEN_MASK,
EASRC_CC_CHEN(ctx->channels - 1));
return 0;
}
static int fsl_easrc_process_format(struct fsl_asrc_pair *ctx,
struct fsl_easrc_data_fmt *fmt,
snd_pcm_format_t raw_fmt)
{
struct fsl_asrc *easrc = ctx->asrc;
struct fsl_easrc_priv *easrc_priv = easrc->private;
int ret;
if (!fmt)
return -EINVAL;
/*
* Context Input Floating Point Format
* 0 - Integer Format
* 1 - Single Precision FP Format
*/
fmt->floating_point = !snd_pcm_format_linear(raw_fmt);
fmt->sample_pos = 0;
fmt->iec958 = 0;
/* Get the data width */
switch (snd_pcm_format_width(raw_fmt)) {
case 16:
fmt->width = EASRC_WIDTH_16_BIT;
fmt->addexp = 15;
break;
case 20:
fmt->width = EASRC_WIDTH_20_BIT;
fmt->addexp = 19;
break;
case 24:
fmt->width = EASRC_WIDTH_24_BIT;
fmt->addexp = 23;
break;
case 32:
fmt->width = EASRC_WIDTH_32_BIT;
fmt->addexp = 31;
break;
default:
return -EINVAL;
}
switch (raw_fmt) {
case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE:
fmt->width = easrc_priv->bps_iec958[ctx->index];
fmt->iec958 = 1;
fmt->floating_point = 0;
if (fmt->width == EASRC_WIDTH_16_BIT) {
fmt->sample_pos = 12;
fmt->addexp = 15;
} else if (fmt->width == EASRC_WIDTH_20_BIT) {
fmt->sample_pos = 8;
fmt->addexp = 19;
} else if (fmt->width == EASRC_WIDTH_24_BIT) {
fmt->sample_pos = 4;
fmt->addexp = 23;
}
break;
default:
break;
}
/*
* Data Endianness
* 0 - Little-Endian
* 1 - Big-Endian
*/
ret = snd_pcm_format_big_endian(raw_fmt);
if (ret < 0)
return ret;
fmt->endianness = ret;
/*
* Input Data sign
* 0b - Signed Format
* 1b - Unsigned Format
*/
fmt->unsign = snd_pcm_format_unsigned(raw_fmt) > 0 ? 1 : 0;
return 0;
}
static int fsl_easrc_set_ctx_format(struct fsl_asrc_pair *ctx,
snd_pcm_format_t *in_raw_format,
snd_pcm_format_t *out_raw_format)
{
struct fsl_asrc *easrc = ctx->asrc;
struct fsl_easrc_ctx_priv *ctx_priv = ctx->private;
struct fsl_easrc_data_fmt *in_fmt = &ctx_priv->in_params.fmt;
struct fsl_easrc_data_fmt *out_fmt = &ctx_priv->out_params.fmt;
int ret = 0;
/* Get the bitfield values for input data format */
if (in_raw_format && out_raw_format) {
ret = fsl_easrc_process_format(ctx, in_fmt, *in_raw_format);
if (ret)
return ret;
}
regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
EASRC_CC_BPS_MASK,
EASRC_CC_BPS(in_fmt->width));
regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
EASRC_CC_ENDIANNESS_MASK,
in_fmt->endianness << EASRC_CC_ENDIANNESS_SHIFT);
regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
EASRC_CC_FMT_MASK,
in_fmt->floating_point << EASRC_CC_FMT_SHIFT);
regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
EASRC_CC_INSIGN_MASK,
in_fmt->unsign << EASRC_CC_INSIGN_SHIFT);
/* In Sample Position */
regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
EASRC_CC_SAMPLE_POS_MASK,
EASRC_CC_SAMPLE_POS(in_fmt->sample_pos));
/* Get the bitfield values for input data format */
if (in_raw_format && out_raw_format) {
ret = fsl_easrc_process_format(ctx, out_fmt, *out_raw_format);
if (ret)
return ret;
}
regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
EASRC_COC_BPS_MASK,
EASRC_COC_BPS(out_fmt->width));
regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
EASRC_COC_ENDIANNESS_MASK,
out_fmt->endianness << EASRC_COC_ENDIANNESS_SHIFT);
regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
EASRC_COC_FMT_MASK,
out_fmt->floating_point << EASRC_COC_FMT_SHIFT);
regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
EASRC_COC_OUTSIGN_MASK,
out_fmt->unsign << EASRC_COC_OUTSIGN_SHIFT);
/* Out Sample Position */
regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
EASRC_COC_SAMPLE_POS_MASK,
EASRC_COC_SAMPLE_POS(out_fmt->sample_pos));
regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
EASRC_COC_IEC_EN_MASK,
out_fmt->iec958 << EASRC_COC_IEC_EN_SHIFT);
return ret;
}
/*
* The ASRC provides interleaving support in hardware to ensure that a
* variety of sample sources can be internally combined
* to conform with this format. Interleaving parameters are accessed
* through the ASRC_CTRL_IN_ACCESSa and ASRC_CTRL_OUT_ACCESSa registers
*/
static int fsl_easrc_set_ctx_organziation(struct fsl_asrc_pair *ctx)
{
struct fsl_easrc_ctx_priv *ctx_priv;
struct fsl_asrc *easrc;
if (!ctx)
return -ENODEV;
easrc = ctx->asrc;
ctx_priv = ctx->private;
/* input interleaving parameters */
regmap_update_bits(easrc->regmap, REG_EASRC_CIA(ctx->index),
EASRC_CIA_ITER_MASK,
EASRC_CIA_ITER(ctx_priv->in_params.iterations));
regmap_update_bits(easrc->regmap, REG_EASRC_CIA(ctx->index),
EASRC_CIA_GRLEN_MASK,
EASRC_CIA_GRLEN(ctx_priv->in_params.group_len));
regmap_update_bits(easrc->regmap, REG_EASRC_CIA(ctx->index),
EASRC_CIA_ACCLEN_MASK,
EASRC_CIA_ACCLEN(ctx_priv->in_params.access_len));
/* output interleaving parameters */
regmap_update_bits(easrc->regmap, REG_EASRC_COA(ctx->index),
EASRC_COA_ITER_MASK,
EASRC_COA_ITER(ctx_priv->out_params.iterations));
regmap_update_bits(easrc->regmap, REG_EASRC_COA(ctx->index),
EASRC_COA_GRLEN_MASK,
EASRC_COA_GRLEN(ctx_priv->out_params.group_len));
regmap_update_bits(easrc->regmap, REG_EASRC_COA(ctx->index),
EASRC_COA_ACCLEN_MASK,
EASRC_COA_ACCLEN(ctx_priv->out_params.access_len));
return 0;
}
/*
* Request one of the available contexts
*
* Returns a negative number on error and >=0 as context id
* on success
*/
static int fsl_easrc_request_context(int channels, struct fsl_asrc_pair *ctx)
{
enum asrc_pair_index index = ASRC_INVALID_PAIR;
struct fsl_asrc *easrc = ctx->asrc;
struct device *dev;
unsigned long lock_flags;
int ret = 0;
int i;
dev = &easrc->pdev->dev;
spin_lock_irqsave(&easrc->lock, lock_flags);
for (i = ASRC_PAIR_A; i < EASRC_CTX_MAX_NUM; i++) {
if (easrc->pair[i])
continue;
index = i;
break;
}
if (index == ASRC_INVALID_PAIR) {
dev_err(dev, "all contexts are busy\n");
ret = -EBUSY;
} else if (channels > easrc->channel_avail) {
dev_err(dev, "can't give the required channels: %d\n",
channels);
ret = -EINVAL;
} else {
ctx->index = index;
ctx->channels = channels;
easrc->pair[index] = ctx;
easrc->channel_avail -= channels;
}
spin_unlock_irqrestore(&easrc->lock, lock_flags);
return ret;
}
/*
* Release the context
*
* This funciton is mainly doing the revert thing in request context
*/
static void fsl_easrc_release_context(struct fsl_asrc_pair *ctx)
{
unsigned long lock_flags;
struct fsl_asrc *easrc;
if (!ctx)
return;
easrc = ctx->asrc;
spin_lock_irqsave(&easrc->lock, lock_flags);
fsl_easrc_release_slot(easrc, ctx->index);
easrc->channel_avail += ctx->channels;
easrc->pair[ctx->index] = NULL;
spin_unlock_irqrestore(&easrc->lock, lock_flags);
}
/*
* Start the context
*
* Enable the DMA request and context
*/
static int fsl_easrc_start_context(struct fsl_asrc_pair *ctx)
{
struct fsl_asrc *easrc = ctx->asrc;
regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
EASRC_CC_FWMDE_MASK, EASRC_CC_FWMDE);
regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
EASRC_COC_FWMDE_MASK, EASRC_COC_FWMDE);
regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
EASRC_CC_EN_MASK, EASRC_CC_EN);
return 0;
}
/*
* Stop the context
*
* Disable the DMA request and context
*/
static int fsl_easrc_stop_context(struct fsl_asrc_pair *ctx)
{
struct fsl_asrc *easrc = ctx->asrc;
int val, i;
int size;
int retry = 200;
regmap_read(easrc->regmap, REG_EASRC_CC(ctx->index), &val);
if (val & EASRC_CC_EN_MASK) {
regmap_update_bits(easrc->regmap,
REG_EASRC_CC(ctx->index),
EASRC_CC_STOP_MASK, EASRC_CC_STOP);
do {
regmap_read(easrc->regmap, REG_EASRC_SFS(ctx->index), &val);
val &= EASRC_SFS_NSGO_MASK;
size = val >> EASRC_SFS_NSGO_SHIFT;
/* Read FIFO, drop the data */
for (i = 0; i < size * ctx->channels; i++)
regmap_read(easrc->regmap, REG_EASRC_RDFIFO(ctx->index), &val);
/* Check RUN_STOP_DONE */
regmap_read(easrc->regmap, REG_EASRC_IRQF, &val);
if (val & EASRC_IRQF_RSD(1 << ctx->index)) {
/*Clear RUN_STOP_DONE*/
regmap_write_bits(easrc->regmap,
REG_EASRC_IRQF,
EASRC_IRQF_RSD(1 << ctx->index),
EASRC_IRQF_RSD(1 << ctx->index));
break;
}
udelay(100);
} while (--retry);
if (retry == 0)
dev_warn(&easrc->pdev->dev, "RUN STOP fail\n");
}
regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
EASRC_CC_EN_MASK | EASRC_CC_STOP_MASK, 0);
regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index),
EASRC_CC_FWMDE_MASK, 0);
regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index),
EASRC_COC_FWMDE_MASK, 0);
return 0;
}
static struct dma_chan *fsl_easrc_get_dma_channel(struct fsl_asrc_pair *ctx,
bool dir)
{
struct fsl_asrc *easrc = ctx->asrc;
enum asrc_pair_index index = ctx->index;
char name[8];
/* Example of dma name: ctx0_rx */
sprintf(name, "ctx%c_%cx", index + '0', dir == IN ? 'r' : 't');
return dma_request_slave_channel(&easrc->pdev->dev, name);
};
static const unsigned int easrc_rates[] = {
8000, 11025, 12000, 16000,
22050, 24000, 32000, 44100,
48000, 64000, 88200, 96000,
128000, 176400, 192000, 256000,
352800, 384000, 705600, 768000,
};
static const struct snd_pcm_hw_constraint_list easrc_rate_constraints = {
.count = ARRAY_SIZE(easrc_rates),
.list = easrc_rates,
};
static int fsl_easrc_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
return snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
&easrc_rate_constraints);
}
static int fsl_easrc_trigger(struct snd_pcm_substream *substream,
int cmd, struct snd_soc_dai *dai)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct fsl_asrc_pair *ctx = runtime->private_data;
int ret;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
ret = fsl_easrc_start_context(ctx);
if (ret)
return ret;
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
ret = fsl_easrc_stop_context(ctx);
if (ret)
return ret;
break;
default:
return -EINVAL;
}
return 0;
}
static int fsl_easrc_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct fsl_asrc *easrc = snd_soc_dai_get_drvdata(dai);
struct snd_pcm_runtime *runtime = substream->runtime;
struct device *dev = &easrc->pdev->dev;
struct fsl_asrc_pair *ctx = runtime->private_data;
struct fsl_easrc_ctx_priv *ctx_priv = ctx->private;
unsigned int channels = params_channels(params);
unsigned int rate = params_rate(params);
snd_pcm_format_t format = params_format(params);
int ret;
ret = fsl_easrc_request_context(channels, ctx);
if (ret) {
dev_err(dev, "failed to request context\n");
return ret;
}
ctx_priv->ctx_streams |= BIT(substream->stream);
/*
* Set the input and output ratio so we can compute
* the resampling ratio in RS_LOW/HIGH
*/
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
ctx_priv->in_params.sample_rate = rate;
ctx_priv->in_params.sample_format = format;
ctx_priv->out_params.sample_rate = easrc->asrc_rate;
ctx_priv->out_params.sample_format = easrc->asrc_format;
} else {
ctx_priv->out_params.sample_rate = rate;
ctx_priv->out_params.sample_format = format;
ctx_priv->in_params.sample_rate = easrc->asrc_rate;
ctx_priv->in_params.sample_format = easrc->asrc_format;
}
ctx->channels = channels;
ctx_priv->in_params.fifo_wtmk = 0x20;
ctx_priv->out_params.fifo_wtmk = 0x20;
/*
* Do only rate conversion and keep the same format for input
* and output data
*/
ret = fsl_easrc_set_ctx_format(ctx,
&ctx_priv->in_params.sample_format,
&ctx_priv->out_params.sample_format);
if (ret) {
dev_err(dev, "failed to set format %d", ret);
return ret;
}
ret = fsl_easrc_config_context(easrc, ctx->index);
if (ret) {
dev_err(dev, "failed to config context\n");
return ret;
}
ctx_priv->in_params.iterations = 1;
ctx_priv->in_params.group_len = ctx->channels;
ctx_priv->in_params.access_len = ctx->channels;
ctx_priv->out_params.iterations = 1;
ctx_priv->out_params.group_len = ctx->channels;
ctx_priv->out_params.access_len = ctx->channels;
ret = fsl_easrc_set_ctx_organziation(ctx);
if (ret) {
dev_err(dev, "failed to set fifo organization\n");
return ret;
}
return 0;
}
static int fsl_easrc_hw_free(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct fsl_asrc_pair *ctx = runtime->private_data;
struct fsl_easrc_ctx_priv *ctx_priv;
if (!ctx)
return -EINVAL;
ctx_priv = ctx->private;
if (ctx_priv->ctx_streams & BIT(substream->stream)) {
ctx_priv->ctx_streams &= ~BIT(substream->stream);
fsl_easrc_release_context(ctx);
}
return 0;
}
static int fsl_easrc_dai_probe(struct snd_soc_dai *cpu_dai)
{
struct fsl_asrc *easrc = dev_get_drvdata(cpu_dai->dev);
snd_soc_dai_init_dma_data(cpu_dai,
&easrc->dma_params_tx,
&easrc->dma_params_rx);
return 0;
}
static const struct snd_soc_dai_ops fsl_easrc_dai_ops = {
.probe = fsl_easrc_dai_probe,
.startup = fsl_easrc_startup,
.trigger = fsl_easrc_trigger,
.hw_params = fsl_easrc_hw_params,
.hw_free = fsl_easrc_hw_free,
};
static struct snd_soc_dai_driver fsl_easrc_dai = {
.playback = {
.stream_name = "ASRC-Playback",
.channels_min = 1,
.channels_max = 32,
.rate_min = 8000,
.rate_max = 768000,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = FSL_EASRC_FORMATS,
},
.capture = {
.stream_name = "ASRC-Capture",
.channels_min = 1,
.channels_max = 32,
.rate_min = 8000,
.rate_max = 768000,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = FSL_EASRC_FORMATS |
SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
},
.ops = &fsl_easrc_dai_ops,
};
static const struct snd_soc_component_driver fsl_easrc_component = {
.name = "fsl-easrc-dai",
.controls = fsl_easrc_snd_controls,
.num_controls = ARRAY_SIZE(fsl_easrc_snd_controls),
.legacy_dai_naming = 1,
};
static const struct reg_default fsl_easrc_reg_defaults[] = {
{REG_EASRC_WRFIFO(0), 0x00000000},
{REG_EASRC_WRFIFO(1), 0x00000000},
{REG_EASRC_WRFIFO(2), 0x00000000},
{REG_EASRC_WRFIFO(3), 0x00000000},
{REG_EASRC_RDFIFO(0), 0x00000000},
{REG_EASRC_RDFIFO(1), 0x00000000},
{REG_EASRC_RDFIFO(2), 0x00000000},
{REG_EASRC_RDFIFO(3), 0x00000000},
{REG_EASRC_CC(0), 0x00000000},
{REG_EASRC_CC(1), 0x00000000},
{REG_EASRC_CC(2), 0x00000000},
{REG_EASRC_CC(3), 0x00000000},
{REG_EASRC_CCE1(0), 0x00000000},
{REG_EASRC_CCE1(1), 0x00000000},
{REG_EASRC_CCE1(2), 0x00000000},
{REG_EASRC_CCE1(3), 0x00000000},
{REG_EASRC_CCE2(0), 0x00000000},
{REG_EASRC_CCE2(1), 0x00000000},
{REG_EASRC_CCE2(2), 0x00000000},
{REG_EASRC_CCE2(3), 0x00000000},
{REG_EASRC_CIA(0), 0x00000000},
{REG_EASRC_CIA(1), 0x00000000},
{REG_EASRC_CIA(2), 0x00000000},
{REG_EASRC_CIA(3), 0x00000000},
{REG_EASRC_DPCS0R0(0), 0x00000000},
{REG_EASRC_DPCS0R0(1), 0x00000000},
{REG_EASRC_DPCS0R0(2), 0x00000000},
{REG_EASRC_DPCS0R0(3), 0x00000000},
{REG_EASRC_DPCS0R1(0), 0x00000000},
{REG_EASRC_DPCS0R1(1), 0x00000000},
{REG_EASRC_DPCS0R1(2), 0x00000000},
{REG_EASRC_DPCS0R1(3), 0x00000000},
{REG_EASRC_DPCS0R2(0), 0x00000000},
{REG_EASRC_DPCS0R2(1), 0x00000000},
{REG_EASRC_DPCS0R2(2), 0x00000000},
{REG_EASRC_DPCS0R2(3), 0x00000000},
{REG_EASRC_DPCS0R3(0), 0x00000000},
{REG_EASRC_DPCS0R3(1), 0x00000000},
{REG_EASRC_DPCS0R3(2), 0x00000000},
{REG_EASRC_DPCS0R3(3), 0x00000000},
{REG_EASRC_DPCS1R0(0), 0x00000000},
{REG_EASRC_DPCS1R0(1), 0x00000000},
{REG_EASRC_DPCS1R0(2), 0x00000000},
{REG_EASRC_DPCS1R0(3), 0x00000000},
{REG_EASRC_DPCS1R1(0), 0x00000000},
{REG_EASRC_DPCS1R1(1), 0x00000000},
{REG_EASRC_DPCS1R1(2), 0x00000000},
{REG_EASRC_DPCS1R1(3), 0x00000000},
{REG_EASRC_DPCS1R2(0), 0x00000000},
{REG_EASRC_DPCS1R2(1), 0x00000000},
{REG_EASRC_DPCS1R2(2), 0x00000000},
{REG_EASRC_DPCS1R2(3), 0x00000000},
{REG_EASRC_DPCS1R3(0), 0x00000000},
{REG_EASRC_DPCS1R3(1), 0x00000000},
{REG_EASRC_DPCS1R3(2), 0x00000000},
{REG_EASRC_DPCS1R3(3), 0x00000000},
{REG_EASRC_COC(0), 0x00000000},
{REG_EASRC_COC(1), 0x00000000},
{REG_EASRC_COC(2), 0x00000000},
{REG_EASRC_COC(3), 0x00000000},
{REG_EASRC_COA(0), 0x00000000},
{REG_EASRC_COA(1), 0x00000000},
{REG_EASRC_COA(2), 0x00000000},
{REG_EASRC_COA(3), 0x00000000},
{REG_EASRC_SFS(0), 0x00000000},
{REG_EASRC_SFS(1), 0x00000000},
{REG_EASRC_SFS(2), 0x00000000},
{REG_EASRC_SFS(3), 0x00000000},
{REG_EASRC_RRL(0), 0x00000000},
{REG_EASRC_RRL(1), 0x00000000},
{REG_EASRC_RRL(2), 0x00000000},
{REG_EASRC_RRL(3), 0x00000000},
{REG_EASRC_RRH(0), 0x00000000},
{REG_EASRC_RRH(1), 0x00000000},
{REG_EASRC_RRH(2), 0x00000000},
{REG_EASRC_RRH(3), 0x00000000},
{REG_EASRC_RUC(0), 0x00000000},
{REG_EASRC_RUC(1), 0x00000000},
{REG_EASRC_RUC(2), 0x00000000},
{REG_EASRC_RUC(3), 0x00000000},
{REG_EASRC_RUR(0), 0x7FFFFFFF},
{REG_EASRC_RUR(1), 0x7FFFFFFF},
{REG_EASRC_RUR(2), 0x7FFFFFFF},
{REG_EASRC_RUR(3), 0x7FFFFFFF},
{REG_EASRC_RCTCL, 0x00000000},
{REG_EASRC_RCTCH, 0x00000000},
{REG_EASRC_PCF(0), 0x00000000},
{REG_EASRC_PCF(1), 0x00000000},
{REG_EASRC_PCF(2), 0x00000000},
{REG_EASRC_PCF(3), 0x00000000},
{REG_EASRC_CRCM, 0x00000000},
{REG_EASRC_CRCC, 0x00000000},
{REG_EASRC_IRQC, 0x00000FFF},
{REG_EASRC_IRQF, 0x00000000},
{REG_EASRC_CS0(0), 0x00000000},
{REG_EASRC_CS0(1), 0x00000000},
{REG_EASRC_CS0(2), 0x00000000},
{REG_EASRC_CS0(3), 0x00000000},
{REG_EASRC_CS1(0), 0x00000000},
{REG_EASRC_CS1(1), 0x00000000},
{REG_EASRC_CS1(2), 0x00000000},
{REG_EASRC_CS1(3), 0x00000000},
{REG_EASRC_CS2(0), 0x00000000},
{REG_EASRC_CS2(1), 0x00000000},
{REG_EASRC_CS2(2), 0x00000000},
{REG_EASRC_CS2(3), 0x00000000},
{REG_EASRC_CS3(0), 0x00000000},
{REG_EASRC_CS3(1), 0x00000000},
{REG_EASRC_CS3(2), 0x00000000},
{REG_EASRC_CS3(3), 0x00000000},
{REG_EASRC_CS4(0), 0x00000000},
{REG_EASRC_CS4(1), 0x00000000},
{REG_EASRC_CS4(2), 0x00000000},
{REG_EASRC_CS4(3), 0x00000000},
{REG_EASRC_CS5(0), 0x00000000},
{REG_EASRC_CS5(1), 0x00000000},
{REG_EASRC_CS5(2), 0x00000000},
{REG_EASRC_CS5(3), 0x00000000},
{REG_EASRC_DBGC, 0x00000000},
{REG_EASRC_DBGS, 0x00000000},
};
static const struct regmap_range fsl_easrc_readable_ranges[] = {
regmap_reg_range(REG_EASRC_RDFIFO(0), REG_EASRC_RCTCH),
regmap_reg_range(REG_EASRC_PCF(0), REG_EASRC_PCF(3)),
regmap_reg_range(REG_EASRC_CRCC, REG_EASRC_DBGS),
};
static const struct regmap_access_table fsl_easrc_readable_table = {
.yes_ranges = fsl_easrc_readable_ranges,
.n_yes_ranges = ARRAY_SIZE(fsl_easrc_readable_ranges),
};
static const struct regmap_range fsl_easrc_writeable_ranges[] = {
regmap_reg_range(REG_EASRC_WRFIFO(0), REG_EASRC_WRFIFO(3)),
regmap_reg_range(REG_EASRC_CC(0), REG_EASRC_COA(3)),
regmap_reg_range(REG_EASRC_RRL(0), REG_EASRC_RCTCH),
regmap_reg_range(REG_EASRC_PCF(0), REG_EASRC_DBGC),
};
static const struct regmap_access_table fsl_easrc_writeable_table = {
.yes_ranges = fsl_easrc_writeable_ranges,
.n_yes_ranges = ARRAY_SIZE(fsl_easrc_writeable_ranges),
};
static const struct regmap_range fsl_easrc_volatileable_ranges[] = {
regmap_reg_range(REG_EASRC_RDFIFO(0), REG_EASRC_RDFIFO(3)),
regmap_reg_range(REG_EASRC_SFS(0), REG_EASRC_SFS(3)),
regmap_reg_range(REG_EASRC_IRQF, REG_EASRC_IRQF),
regmap_reg_range(REG_EASRC_DBGS, REG_EASRC_DBGS),
};
static const struct regmap_access_table fsl_easrc_volatileable_table = {
.yes_ranges = fsl_easrc_volatileable_ranges,
.n_yes_ranges = ARRAY_SIZE(fsl_easrc_volatileable_ranges),
};
static const struct regmap_config fsl_easrc_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = REG_EASRC_DBGS,
.reg_defaults = fsl_easrc_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(fsl_easrc_reg_defaults),
.rd_table = &fsl_easrc_readable_table,
.wr_table = &fsl_easrc_writeable_table,
.volatile_table = &fsl_easrc_volatileable_table,
.cache_type = REGCACHE_RBTREE,
};
#ifdef DEBUG
static void fsl_easrc_dump_firmware(struct fsl_asrc *easrc)
{
struct fsl_easrc_priv *easrc_priv = easrc->private;
struct asrc_firmware_hdr *firm = easrc_priv->firmware_hdr;
struct interp_params *interp = easrc_priv->interp;
struct prefil_params *prefil = easrc_priv->prefil;
struct device *dev = &easrc->pdev->dev;
int i;
if (firm->magic != FIRMWARE_MAGIC) {
dev_err(dev, "Wrong magic. Something went wrong!");
return;
}
dev_dbg(dev, "Firmware v%u dump:\n", firm->firmware_version);
dev_dbg(dev, "Num prefilter scenarios: %u\n", firm->prefil_scen);
dev_dbg(dev, "Num interpolation scenarios: %u\n", firm->interp_scen);
dev_dbg(dev, "\nInterpolation scenarios:\n");
for (i = 0; i < firm->interp_scen; i++) {
if (interp[i].magic != FIRMWARE_MAGIC) {
dev_dbg(dev, "%d. wrong interp magic: %x\n",
i, interp[i].magic);
continue;
}
dev_dbg(dev, "%d. taps: %u, phases: %u, center: %llu\n", i,
interp[i].num_taps, interp[i].num_phases,
interp[i].center_tap);
}
for (i = 0; i < firm->prefil_scen; i++) {
if (prefil[i].magic != FIRMWARE_MAGIC) {
dev_dbg(dev, "%d. wrong prefil magic: %x\n",
i, prefil[i].magic);
continue;
}
dev_dbg(dev, "%d. insr: %u, outsr: %u, st1: %u, st2: %u\n", i,
prefil[i].insr, prefil[i].outsr,
prefil[i].st1_taps, prefil[i].st2_taps);
}
dev_dbg(dev, "end of firmware dump\n");
}
#endif
static int fsl_easrc_get_firmware(struct fsl_asrc *easrc)
{
struct fsl_easrc_priv *easrc_priv;
const struct firmware **fw_p;
u32 pnum, inum, offset;
const u8 *data;
int ret;
if (!easrc)
return -EINVAL;
easrc_priv = easrc->private;
fw_p = &easrc_priv->fw;
ret = request_firmware(fw_p, easrc_priv->fw_name, &easrc->pdev->dev);
if (ret)
return ret;
data = easrc_priv->fw->data;
easrc_priv->firmware_hdr = (struct asrc_firmware_hdr *)data;
pnum = easrc_priv->firmware_hdr->prefil_scen;
inum = easrc_priv->firmware_hdr->interp_scen;
if (inum) {
offset = sizeof(struct asrc_firmware_hdr);
easrc_priv->interp = (struct interp_params *)(data + offset);
}
if (pnum) {
offset = sizeof(struct asrc_firmware_hdr) +
inum * sizeof(struct interp_params);
easrc_priv->prefil = (struct prefil_params *)(data + offset);
}
#ifdef DEBUG
fsl_easrc_dump_firmware(easrc);
#endif
return 0;
}
static irqreturn_t fsl_easrc_isr(int irq, void *dev_id)
{
struct fsl_asrc *easrc = (struct fsl_asrc *)dev_id;
struct device *dev = &easrc->pdev->dev;
int val;
regmap_read(easrc->regmap, REG_EASRC_IRQF, &val);
if (val & EASRC_IRQF_OER_MASK)
dev_dbg(dev, "output FIFO underflow\n");
if (val & EASRC_IRQF_IFO_MASK)
dev_dbg(dev, "input FIFO overflow\n");
return IRQ_HANDLED;
}
static int fsl_easrc_get_fifo_addr(u8 dir, enum asrc_pair_index index)
{
return REG_EASRC_FIFO(dir, index);
}
static const struct of_device_id fsl_easrc_dt_ids[] = {
{ .compatible = "fsl,imx8mn-easrc",},
{}
};
MODULE_DEVICE_TABLE(of, fsl_easrc_dt_ids);
static int fsl_easrc_probe(struct platform_device *pdev)
{
struct fsl_easrc_priv *easrc_priv;
struct device *dev = &pdev->dev;
struct fsl_asrc *easrc;
struct resource *res;
struct device_node *np;
void __iomem *regs;
u32 asrc_fmt = 0;
int ret, irq;
easrc = devm_kzalloc(dev, sizeof(*easrc), GFP_KERNEL);
if (!easrc)
return -ENOMEM;
easrc_priv = devm_kzalloc(dev, sizeof(*easrc_priv), GFP_KERNEL);
if (!easrc_priv)
return -ENOMEM;
easrc->pdev = pdev;
easrc->private = easrc_priv;
np = dev->of_node;
regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(regs))
return PTR_ERR(regs);
easrc->paddr = res->start;
easrc->regmap = devm_regmap_init_mmio(dev, regs, &fsl_easrc_regmap_config);
if (IS_ERR(easrc->regmap)) {
dev_err(dev, "failed to init regmap");
return PTR_ERR(easrc->regmap);
}
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
ret = devm_request_irq(&pdev->dev, irq, fsl_easrc_isr, 0,
dev_name(dev), easrc);
if (ret) {
dev_err(dev, "failed to claim irq %u: %d\n", irq, ret);
return ret;
}
easrc->mem_clk = devm_clk_get(dev, "mem");
if (IS_ERR(easrc->mem_clk)) {
dev_err(dev, "failed to get mem clock\n");
return PTR_ERR(easrc->mem_clk);
}
/* Set default value */
easrc->channel_avail = 32;
easrc->get_dma_channel = fsl_easrc_get_dma_channel;
easrc->request_pair = fsl_easrc_request_context;
easrc->release_pair = fsl_easrc_release_context;
easrc->get_fifo_addr = fsl_easrc_get_fifo_addr;
easrc->pair_priv_size = sizeof(struct fsl_easrc_ctx_priv);
easrc_priv->rs_num_taps = EASRC_RS_32_TAPS;
easrc_priv->const_coeff = 0x3FF0000000000000;
ret = of_property_read_u32(np, "fsl,asrc-rate", &easrc->asrc_rate);
if (ret) {
dev_err(dev, "failed to asrc rate\n");
return ret;
}
ret = of_property_read_u32(np, "fsl,asrc-format", &asrc_fmt);
easrc->asrc_format = (__force snd_pcm_format_t)asrc_fmt;
if (ret) {
dev_err(dev, "failed to asrc format\n");
return ret;
}
if (!(FSL_EASRC_FORMATS & (pcm_format_to_bits(easrc->asrc_format)))) {
dev_warn(dev, "unsupported format, switching to S24_LE\n");
easrc->asrc_format = SNDRV_PCM_FORMAT_S24_LE;
}
ret = of_property_read_string(np, "firmware-name",
&easrc_priv->fw_name);
if (ret) {
dev_err(dev, "failed to get firmware name\n");
return ret;
}
platform_set_drvdata(pdev, easrc);
pm_runtime_enable(dev);
spin_lock_init(&easrc->lock);
regcache_cache_only(easrc->regmap, true);
ret = devm_snd_soc_register_component(dev, &fsl_easrc_component,
&fsl_easrc_dai, 1);
if (ret) {
dev_err(dev, "failed to register ASoC DAI\n");
return ret;
}
ret = devm_snd_soc_register_component(dev, &fsl_asrc_component,
NULL, 0);
if (ret) {
dev_err(&pdev->dev, "failed to register ASoC platform\n");
return ret;
}
return 0;
}
static void fsl_easrc_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
}
static __maybe_unused int fsl_easrc_runtime_suspend(struct device *dev)
{
struct fsl_asrc *easrc = dev_get_drvdata(dev);
struct fsl_easrc_priv *easrc_priv = easrc->private;
unsigned long lock_flags;
regcache_cache_only(easrc->regmap, true);
clk_disable_unprepare(easrc->mem_clk);
spin_lock_irqsave(&easrc->lock, lock_flags);
easrc_priv->firmware_loaded = 0;
spin_unlock_irqrestore(&easrc->lock, lock_flags);
return 0;
}
static __maybe_unused int fsl_easrc_runtime_resume(struct device *dev)
{
struct fsl_asrc *easrc = dev_get_drvdata(dev);
struct fsl_easrc_priv *easrc_priv = easrc->private;
struct fsl_easrc_ctx_priv *ctx_priv;
struct fsl_asrc_pair *ctx;
unsigned long lock_flags;
int ret;
int i;
ret = clk_prepare_enable(easrc->mem_clk);
if (ret)
return ret;
regcache_cache_only(easrc->regmap, false);
regcache_mark_dirty(easrc->regmap);
regcache_sync(easrc->regmap);
spin_lock_irqsave(&easrc->lock, lock_flags);
if (easrc_priv->firmware_loaded) {
spin_unlock_irqrestore(&easrc->lock, lock_flags);
goto skip_load;
}
easrc_priv->firmware_loaded = 1;
spin_unlock_irqrestore(&easrc->lock, lock_flags);
ret = fsl_easrc_get_firmware(easrc);
if (ret) {
dev_err(dev, "failed to get firmware\n");
goto disable_mem_clk;
}
/*
* Write Resampling Coefficients
* The coefficient RAM must be configured prior to beginning of
* any context processing within the ASRC
*/
ret = fsl_easrc_resampler_config(easrc);
if (ret) {
dev_err(dev, "resampler config failed\n");
goto disable_mem_clk;
}
for (i = ASRC_PAIR_A; i < EASRC_CTX_MAX_NUM; i++) {
ctx = easrc->pair[i];
if (!ctx)
continue;
ctx_priv = ctx->private;
fsl_easrc_set_rs_ratio(ctx);
ctx_priv->out_missed_sample = ctx_priv->in_filled_sample *
ctx_priv->out_params.sample_rate /
ctx_priv->in_params.sample_rate;
if (ctx_priv->in_filled_sample * ctx_priv->out_params.sample_rate
% ctx_priv->in_params.sample_rate != 0)
ctx_priv->out_missed_sample += 1;
ret = fsl_easrc_write_pf_coeff_mem(easrc, i,
ctx_priv->st1_coeff,
ctx_priv->st1_num_taps,
ctx_priv->st1_addexp);
if (ret)
goto disable_mem_clk;
ret = fsl_easrc_write_pf_coeff_mem(easrc, i,
ctx_priv->st2_coeff,
ctx_priv->st2_num_taps,
ctx_priv->st2_addexp);
if (ret)
goto disable_mem_clk;
}
skip_load:
return 0;
disable_mem_clk:
clk_disable_unprepare(easrc->mem_clk);
return ret;
}
static const struct dev_pm_ops fsl_easrc_pm_ops = {
SET_RUNTIME_PM_OPS(fsl_easrc_runtime_suspend,
fsl_easrc_runtime_resume,
NULL)
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
};
static struct platform_driver fsl_easrc_driver = {
.probe = fsl_easrc_probe,
.remove_new = fsl_easrc_remove,
.driver = {
.name = "fsl-easrc",
.pm = &fsl_easrc_pm_ops,
.of_match_table = fsl_easrc_dt_ids,
},
};
module_platform_driver(fsl_easrc_driver);
MODULE_DESCRIPTION("NXP Enhanced Asynchronous Sample Rate (eASRC) driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/fsl/fsl_easrc.c |
// SPDX-License-Identifier: GPL-2.0+
//
// Freescale ALSA SoC Digital Audio Interface (SAI) driver.
//
// Copyright 2012-2015 Freescale Semiconductor, Inc.
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/dmaengine.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pm_qos.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/time.h>
#include <sound/core.h>
#include <sound/dmaengine_pcm.h>
#include <sound/pcm_params.h>
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
#include "fsl_sai.h"
#include "fsl_utils.h"
#include "imx-pcm.h"
#define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\
FSL_SAI_CSR_FEIE)
static const unsigned int fsl_sai_rates[] = {
8000, 11025, 12000, 16000, 22050,
24000, 32000, 44100, 48000, 64000,
88200, 96000, 176400, 192000, 352800,
384000, 705600, 768000, 1411200, 2822400,
};
static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = {
.count = ARRAY_SIZE(fsl_sai_rates),
.list = fsl_sai_rates,
};
/**
* fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream
*
* SAI supports synchronous mode using bit/frame clocks of either Transmitter's
* or Receiver's for both streams. This function is used to check if clocks of
* the stream's are synced by the opposite stream.
*
* @sai: SAI context
* @dir: stream direction
*/
static inline bool fsl_sai_dir_is_synced(struct fsl_sai *sai, int dir)
{
int adir = (dir == TX) ? RX : TX;
/* current dir in async mode while opposite dir in sync mode */
return !sai->synchronous[dir] && sai->synchronous[adir];
}
static struct pinctrl_state *fsl_sai_get_pins_state(struct fsl_sai *sai, u32 bclk)
{
struct pinctrl_state *state = NULL;
if (sai->is_pdm_mode) {
/* [email protected], DSD512@48kHz */
if (bclk >= 22579200)
state = pinctrl_lookup_state(sai->pinctrl, "dsd512");
/* Get default DSD state */
if (IS_ERR_OR_NULL(state))
state = pinctrl_lookup_state(sai->pinctrl, "dsd");
} else {
/* 706k32b2c, 768k32b2c, etc */
if (bclk >= 45158400)
state = pinctrl_lookup_state(sai->pinctrl, "pcm_b2m");
}
/* Get default state */
if (IS_ERR_OR_NULL(state))
state = pinctrl_lookup_state(sai->pinctrl, "default");
return state;
}
static irqreturn_t fsl_sai_isr(int irq, void *devid)
{
struct fsl_sai *sai = (struct fsl_sai *)devid;
unsigned int ofs = sai->soc_data->reg_offset;
struct device *dev = &sai->pdev->dev;
u32 flags, xcsr, mask;
irqreturn_t iret = IRQ_NONE;
/*
* Both IRQ status bits and IRQ mask bits are in the xCSR but
* different shifts. And we here create a mask only for those
* IRQs that we activated.
*/
mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT;
/* Tx IRQ */
regmap_read(sai->regmap, FSL_SAI_TCSR(ofs), &xcsr);
flags = xcsr & mask;
if (flags)
iret = IRQ_HANDLED;
else
goto irq_rx;
if (flags & FSL_SAI_CSR_WSF)
dev_dbg(dev, "isr: Start of Tx word detected\n");
if (flags & FSL_SAI_CSR_SEF)
dev_dbg(dev, "isr: Tx Frame sync error detected\n");
if (flags & FSL_SAI_CSR_FEF)
dev_dbg(dev, "isr: Transmit underrun detected\n");
if (flags & FSL_SAI_CSR_FWF)
dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n");
if (flags & FSL_SAI_CSR_FRF)
dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n");
flags &= FSL_SAI_CSR_xF_W_MASK;
xcsr &= ~FSL_SAI_CSR_xF_MASK;
if (flags)
regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), flags | xcsr);
irq_rx:
/* Rx IRQ */
regmap_read(sai->regmap, FSL_SAI_RCSR(ofs), &xcsr);
flags = xcsr & mask;
if (flags)
iret = IRQ_HANDLED;
else
goto out;
if (flags & FSL_SAI_CSR_WSF)
dev_dbg(dev, "isr: Start of Rx word detected\n");
if (flags & FSL_SAI_CSR_SEF)
dev_dbg(dev, "isr: Rx Frame sync error detected\n");
if (flags & FSL_SAI_CSR_FEF)
dev_dbg(dev, "isr: Receive overflow detected\n");
if (flags & FSL_SAI_CSR_FWF)
dev_dbg(dev, "isr: Enabled receive FIFO is full\n");
if (flags & FSL_SAI_CSR_FRF)
dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n");
flags &= FSL_SAI_CSR_xF_W_MASK;
xcsr &= ~FSL_SAI_CSR_xF_MASK;
if (flags)
regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), flags | xcsr);
out:
return iret;
}
static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
u32 rx_mask, int slots, int slot_width)
{
struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
sai->slots = slots;
sai->slot_width = slot_width;
return 0;
}
static int fsl_sai_set_dai_bclk_ratio(struct snd_soc_dai *dai,
unsigned int ratio)
{
struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
sai->bclk_ratio = ratio;
return 0;
}
static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai,
int clk_id, unsigned int freq, bool tx)
{
struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
unsigned int ofs = sai->soc_data->reg_offset;
u32 val_cr2 = 0;
switch (clk_id) {
case FSL_SAI_CLK_BUS:
val_cr2 |= FSL_SAI_CR2_MSEL_BUS;
break;
case FSL_SAI_CLK_MAST1:
val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1;
break;
case FSL_SAI_CLK_MAST2:
val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2;
break;
case FSL_SAI_CLK_MAST3:
val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3;
break;
default:
return -EINVAL;
}
regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
FSL_SAI_CR2_MSEL_MASK, val_cr2);
return 0;
}
static int fsl_sai_set_mclk_rate(struct snd_soc_dai *dai, int clk_id, unsigned int freq)
{
struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
int ret;
fsl_asoc_reparent_pll_clocks(dai->dev, sai->mclk_clk[clk_id],
sai->pll8k_clk, sai->pll11k_clk, freq);
ret = clk_set_rate(sai->mclk_clk[clk_id], freq);
if (ret < 0)
dev_err(dai->dev, "failed to set clock rate (%u): %d\n", freq, ret);
return ret;
}
static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
int clk_id, unsigned int freq, int dir)
{
struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
int ret;
if (dir == SND_SOC_CLOCK_IN)
return 0;
if (freq > 0 && clk_id != FSL_SAI_CLK_BUS) {
if (clk_id < 0 || clk_id >= FSL_SAI_MCLK_MAX) {
dev_err(cpu_dai->dev, "Unknown clock id: %d\n", clk_id);
return -EINVAL;
}
if (IS_ERR_OR_NULL(sai->mclk_clk[clk_id])) {
dev_err(cpu_dai->dev, "Unassigned clock: %d\n", clk_id);
return -EINVAL;
}
if (sai->mclk_streams == 0) {
ret = fsl_sai_set_mclk_rate(cpu_dai, clk_id, freq);
if (ret < 0)
return ret;
}
}
ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, true);
if (ret) {
dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret);
return ret;
}
ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, false);
if (ret)
dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret);
return ret;
}
static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
unsigned int fmt, bool tx)
{
struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
unsigned int ofs = sai->soc_data->reg_offset;
u32 val_cr2 = 0, val_cr4 = 0;
if (!sai->is_lsb_first)
val_cr4 |= FSL_SAI_CR4_MF;
sai->is_pdm_mode = false;
sai->is_dsp_mode = false;
/* DAI mode */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
/*
* Frame low, 1clk before data, one word length for frame sync,
* frame sync starts one serial clock cycle earlier,
* that is, together with the last bit of the previous
* data word.
*/
val_cr2 |= FSL_SAI_CR2_BCP;
val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP;
break;
case SND_SOC_DAIFMT_LEFT_J:
/*
* Frame high, one word length for frame sync,
* frame sync asserts with the first bit of the frame.
*/
val_cr2 |= FSL_SAI_CR2_BCP;
break;
case SND_SOC_DAIFMT_DSP_A:
/*
* Frame high, 1clk before data, one bit for frame sync,
* frame sync starts one serial clock cycle earlier,
* that is, together with the last bit of the previous
* data word.
*/
val_cr2 |= FSL_SAI_CR2_BCP;
val_cr4 |= FSL_SAI_CR4_FSE;
sai->is_dsp_mode = true;
break;
case SND_SOC_DAIFMT_DSP_B:
/*
* Frame high, one bit for frame sync,
* frame sync asserts with the first bit of the frame.
*/
val_cr2 |= FSL_SAI_CR2_BCP;
sai->is_dsp_mode = true;
break;
case SND_SOC_DAIFMT_PDM:
val_cr2 |= FSL_SAI_CR2_BCP;
val_cr4 &= ~FSL_SAI_CR4_MF;
sai->is_pdm_mode = true;
break;
case SND_SOC_DAIFMT_RIGHT_J:
/* To be done */
default:
return -EINVAL;
}
/* DAI clock inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_IB_IF:
/* Invert both clocks */
val_cr2 ^= FSL_SAI_CR2_BCP;
val_cr4 ^= FSL_SAI_CR4_FSP;
break;
case SND_SOC_DAIFMT_IB_NF:
/* Invert bit clock */
val_cr2 ^= FSL_SAI_CR2_BCP;
break;
case SND_SOC_DAIFMT_NB_IF:
/* Invert frame clock */
val_cr4 ^= FSL_SAI_CR4_FSP;
break;
case SND_SOC_DAIFMT_NB_NF:
/* Nothing to do for both normal cases */
break;
default:
return -EINVAL;
}
/* DAI clock provider masks */
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BP_FP:
val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
sai->is_consumer_mode = false;
break;
case SND_SOC_DAIFMT_BC_FC:
sai->is_consumer_mode = true;
break;
case SND_SOC_DAIFMT_BP_FC:
val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
sai->is_consumer_mode = false;
break;
case SND_SOC_DAIFMT_BC_FP:
val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
sai->is_consumer_mode = true;
break;
default:
return -EINVAL;
}
regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2);
regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE |
FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4);
return 0;
}
static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
{
int ret;
ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, true);
if (ret) {
dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret);
return ret;
}
ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, false);
if (ret)
dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret);
return ret;
}
static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
{
struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
unsigned int reg, ofs = sai->soc_data->reg_offset;
unsigned long clk_rate;
u32 savediv = 0, ratio, bestdiff = freq;
int adir = tx ? RX : TX;
int dir = tx ? TX : RX;
u32 id;
bool support_1_1_ratio = sai->verid.version >= 0x0301;
/* Don't apply to consumer mode */
if (sai->is_consumer_mode)
return 0;
/*
* There is no point in polling MCLK0 if it is identical to MCLK1.
* And given that MQS use case has to use MCLK1 though two clocks
* are the same, we simply skip MCLK0 and start to find from MCLK1.
*/
id = sai->soc_data->mclk0_is_mclk1 ? 1 : 0;
for (; id < FSL_SAI_MCLK_MAX; id++) {
int diff;
clk_rate = clk_get_rate(sai->mclk_clk[id]);
if (!clk_rate)
continue;
ratio = DIV_ROUND_CLOSEST(clk_rate, freq);
if (!ratio || ratio > 512)
continue;
if (ratio == 1 && !support_1_1_ratio)
continue;
if ((ratio & 1) && ratio > 1)
continue;
diff = abs((long)clk_rate - ratio * freq);
/*
* Drop the source that can not be
* divided into the required rate.
*/
if (diff != 0 && clk_rate / diff < 1000)
continue;
dev_dbg(dai->dev,
"ratio %d for freq %dHz based on clock %ldHz\n",
ratio, freq, clk_rate);
if (diff < bestdiff) {
savediv = ratio;
sai->mclk_id[tx] = id;
bestdiff = diff;
}
if (diff == 0)
break;
}
if (savediv == 0) {
dev_err(dai->dev, "failed to derive required %cx rate: %d\n",
tx ? 'T' : 'R', freq);
return -EINVAL;
}
dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n",
sai->mclk_id[tx], savediv, bestdiff);
/*
* 1) For Asynchronous mode, we must set RCR2 register for capture, and
* set TCR2 register for playback.
* 2) For Tx sync with Rx clock, we must set RCR2 register for playback
* and capture.
* 3) For Rx sync with Tx clock, we must set TCR2 register for playback
* and capture.
* 4) For Tx and Rx are both Synchronous with another SAI, we just
* ignore it.
*/
if (fsl_sai_dir_is_synced(sai, adir))
reg = FSL_SAI_xCR2(!tx, ofs);
else if (!sai->synchronous[dir])
reg = FSL_SAI_xCR2(tx, ofs);
else
return 0;
regmap_update_bits(sai->regmap, reg, FSL_SAI_CR2_MSEL_MASK,
FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
if (savediv == 1) {
regmap_update_bits(sai->regmap, reg,
FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP,
FSL_SAI_CR2_BYP);
if (fsl_sai_dir_is_synced(sai, adir))
regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
FSL_SAI_CR2_BCI, FSL_SAI_CR2_BCI);
else
regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
FSL_SAI_CR2_BCI, 0);
} else {
regmap_update_bits(sai->regmap, reg,
FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP,
savediv / 2 - 1);
}
return 0;
}
static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *cpu_dai)
{
struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
unsigned int ofs = sai->soc_data->reg_offset;
bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
unsigned int channels = params_channels(params);
struct snd_dmaengine_dai_dma_data *dma_params;
struct fsl_sai_dl_cfg *dl_cfg = sai->dl_cfg;
u32 word_width = params_width(params);
int trce_mask = 0, dl_cfg_idx = 0;
int dl_cfg_cnt = sai->dl_cfg_cnt;
u32 dl_type = FSL_SAI_DL_I2S;
u32 val_cr4 = 0, val_cr5 = 0;
u32 slots = (channels == 1) ? 2 : channels;
u32 slot_width = word_width;
int adir = tx ? RX : TX;
u32 pins, bclk;
u32 watermark;
int ret, i;
if (sai->slot_width)
slot_width = sai->slot_width;
if (sai->slots)
slots = sai->slots;
else if (sai->bclk_ratio)
slots = sai->bclk_ratio / slot_width;
pins = DIV_ROUND_UP(channels, slots);
/*
* PDM mode, channels are independent
* each channels are on one dataline/FIFO.
*/
if (sai->is_pdm_mode) {
pins = channels;
dl_type = FSL_SAI_DL_PDM;
}
for (i = 0; i < dl_cfg_cnt; i++) {
if (dl_cfg[i].type == dl_type && dl_cfg[i].pins[tx] == pins) {
dl_cfg_idx = i;
break;
}
}
if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) < pins) {
dev_err(cpu_dai->dev, "channel not supported\n");
return -EINVAL;
}
bclk = params_rate(params) * (sai->bclk_ratio ? sai->bclk_ratio : slots * slot_width);
if (!IS_ERR_OR_NULL(sai->pinctrl)) {
sai->pins_state = fsl_sai_get_pins_state(sai, bclk);
if (!IS_ERR_OR_NULL(sai->pins_state)) {
ret = pinctrl_select_state(sai->pinctrl, sai->pins_state);
if (ret) {
dev_err(cpu_dai->dev, "failed to set proper pins state: %d\n", ret);
return ret;
}
}
}
if (!sai->is_consumer_mode) {
ret = fsl_sai_set_bclk(cpu_dai, tx, bclk);
if (ret)
return ret;
/* Do not enable the clock if it is already enabled */
if (!(sai->mclk_streams & BIT(substream->stream))) {
ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]);
if (ret)
return ret;
sai->mclk_streams |= BIT(substream->stream);
}
}
if (!sai->is_dsp_mode && !sai->is_pdm_mode)
val_cr4 |= FSL_SAI_CR4_SYWD(slot_width);
val_cr5 |= FSL_SAI_CR5_WNW(slot_width);
val_cr5 |= FSL_SAI_CR5_W0W(slot_width);
if (sai->is_lsb_first || sai->is_pdm_mode)
val_cr5 |= FSL_SAI_CR5_FBT(0);
else
val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1);
val_cr4 |= FSL_SAI_CR4_FRSZ(slots);
/* Set to output mode to avoid tri-stated data pins */
if (tx)
val_cr4 |= FSL_SAI_CR4_CHMOD;
/*
* For SAI provider mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will
* generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4),
* RCR5(TCR5) for playback(capture), or there will be sync error.
*/
if (!sai->is_consumer_mode && fsl_sai_dir_is_synced(sai, adir)) {
regmap_update_bits(sai->regmap, FSL_SAI_xCR4(!tx, ofs),
FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK |
FSL_SAI_CR4_CHMOD_MASK,
val_cr4);
regmap_update_bits(sai->regmap, FSL_SAI_xCR5(!tx, ofs),
FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
FSL_SAI_CR5_FBT_MASK, val_cr5);
}
/*
* Combine mode has limation:
* - Can't used for singel dataline/FIFO case except the FIFO0
* - Can't used for multi dataline/FIFO case except the enabled FIFOs
* are successive and start from FIFO0
*
* So for common usage, all multi fifo case disable the combine mode.
*/
if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) <= 1 || sai->is_multi_fifo_dma)
regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
FSL_SAI_CR4_FCOMB_MASK, 0);
else
regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
FSL_SAI_CR4_FCOMB_MASK, FSL_SAI_CR4_FCOMB_SOFT);
dma_params = tx ? &sai->dma_params_tx : &sai->dma_params_rx;
dma_params->addr = sai->res->start + FSL_SAI_xDR0(tx) +
dl_cfg[dl_cfg_idx].start_off[tx] * 0x4;
if (sai->is_multi_fifo_dma) {
sai->audio_config[tx].words_per_fifo = min(slots, channels);
if (tx) {
sai->audio_config[tx].n_fifos_dst = pins;
sai->audio_config[tx].stride_fifos_dst = dl_cfg[dl_cfg_idx].next_off[tx];
} else {
sai->audio_config[tx].n_fifos_src = pins;
sai->audio_config[tx].stride_fifos_src = dl_cfg[dl_cfg_idx].next_off[tx];
}
dma_params->maxburst = sai->audio_config[tx].words_per_fifo * pins;
dma_params->peripheral_config = &sai->audio_config[tx];
dma_params->peripheral_size = sizeof(sai->audio_config[tx]);
watermark = tx ? (sai->soc_data->fifo_depth - dma_params->maxburst) :
(dma_params->maxburst - 1);
regmap_update_bits(sai->regmap, FSL_SAI_xCR1(tx, ofs),
FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth),
watermark);
}
/* Find a proper tcre setting */
for (i = 0; i < sai->soc_data->pins; i++) {
trce_mask = (1 << (i + 1)) - 1;
if (hweight8(dl_cfg[dl_cfg_idx].mask[tx] & trce_mask) == pins)
break;
}
regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs),
FSL_SAI_CR3_TRCE_MASK,
FSL_SAI_CR3_TRCE((dl_cfg[dl_cfg_idx].mask[tx] & trce_mask)));
regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK |
FSL_SAI_CR4_CHMOD_MASK,
val_cr4);
regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, ofs),
FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
FSL_SAI_CR5_FBT_MASK, val_cr5);
regmap_write(sai->regmap, FSL_SAI_xMR(tx),
~0UL - ((1 << min(channels, slots)) - 1));
return 0;
}
static int fsl_sai_hw_free(struct snd_pcm_substream *substream,
struct snd_soc_dai *cpu_dai)
{
struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
unsigned int ofs = sai->soc_data->reg_offset;
regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs),
FSL_SAI_CR3_TRCE_MASK, 0);
if (!sai->is_consumer_mode &&
sai->mclk_streams & BIT(substream->stream)) {
clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]);
sai->mclk_streams &= ~BIT(substream->stream);
}
return 0;
}
static void fsl_sai_config_disable(struct fsl_sai *sai, int dir)
{
unsigned int ofs = sai->soc_data->reg_offset;
bool tx = dir == TX;
u32 xcsr, count = 100;
regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
FSL_SAI_CSR_TERE | FSL_SAI_CSR_BCE, 0);
/* TERE will remain set till the end of current frame */
do {
udelay(10);
regmap_read(sai->regmap, FSL_SAI_xCSR(tx, ofs), &xcsr);
} while (--count && xcsr & FSL_SAI_CSR_TERE);
regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
/*
* For sai master mode, after several open/close sai,
* there will be no frame clock, and can't recover
* anymore. Add software reset to fix this issue.
* This is a hardware bug, and will be fix in the
* next sai version.
*/
if (!sai->is_consumer_mode) {
/* Software Reset */
regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_SR);
/* Clear SR bit to finish the reset */
regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), 0);
}
}
static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *cpu_dai)
{
struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
unsigned int ofs = sai->soc_data->reg_offset;
bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
int adir = tx ? RX : TX;
int dir = tx ? TX : RX;
u32 xcsr;
/*
* Asynchronous mode: Clear SYNC for both Tx and Rx.
* Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx.
* Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx.
*/
regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs), FSL_SAI_CR2_SYNC,
sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0);
regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs), FSL_SAI_CR2_SYNC,
sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0);
/*
* It is recommended that the transmitter is the last enabled
* and the first disabled.
*/
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE);
regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
/*
* Enable the opposite direction for synchronous mode
* 1. Tx sync with Rx: only set RE for Rx; set TE & RE for Tx
* 2. Rx sync with Tx: only set TE for Tx; set RE & TE for Rx
*
* RM recommends to enable RE after TE for case 1 and to enable
* TE after RE for case 2, but we here may not always guarantee
* that happens: "arecord 1.wav; aplay 2.wav" in case 1 enables
* TE after RE, which is against what RM recommends but should
* be safe to do, judging by years of testing results.
*/
if (fsl_sai_dir_is_synced(sai, adir))
regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx), ofs),
FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
FSL_SAI_CSR_FRDE, 0);
regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
FSL_SAI_CSR_xIE_MASK, 0);
/* Check if the opposite FRDE is also disabled */
regmap_read(sai->regmap, FSL_SAI_xCSR(!tx, ofs), &xcsr);
/*
* If opposite stream provides clocks for synchronous mode and
* it is inactive, disable it before disabling the current one
*/
if (fsl_sai_dir_is_synced(sai, adir) && !(xcsr & FSL_SAI_CSR_FRDE))
fsl_sai_config_disable(sai, adir);
/*
* Disable current stream if either of:
* 1. current stream doesn't provide clocks for synchronous mode
* 2. current stream provides clocks for synchronous mode but no
* more stream is active.
*/
if (!fsl_sai_dir_is_synced(sai, dir) || !(xcsr & FSL_SAI_CSR_FRDE))
fsl_sai_config_disable(sai, dir);
break;
default:
return -EINVAL;
}
return 0;
}
static int fsl_sai_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *cpu_dai)
{
struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
int ret;
/*
* EDMA controller needs period size to be a multiple of
* tx/rx maxburst
*/
if (sai->soc_data->use_edma)
snd_pcm_hw_constraint_step(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
tx ? sai->dma_params_tx.maxburst :
sai->dma_params_rx.maxburst);
ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints);
return ret;
}
static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai)
{
struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev);
unsigned int ofs = sai->soc_data->reg_offset;
/* Software Reset for both Tx and Rx */
regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR);
regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR);
/* Clear SR bit to finish the reset */
regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0);
regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0);
regmap_update_bits(sai->regmap, FSL_SAI_TCR1(ofs),
FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth),
sai->soc_data->fifo_depth - sai->dma_params_tx.maxburst);
regmap_update_bits(sai->regmap, FSL_SAI_RCR1(ofs),
FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth),
sai->dma_params_rx.maxburst - 1);
snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx,
&sai->dma_params_rx);
return 0;
}
static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
.probe = fsl_sai_dai_probe,
.set_bclk_ratio = fsl_sai_set_dai_bclk_ratio,
.set_sysclk = fsl_sai_set_dai_sysclk,
.set_fmt = fsl_sai_set_dai_fmt,
.set_tdm_slot = fsl_sai_set_dai_tdm_slot,
.hw_params = fsl_sai_hw_params,
.hw_free = fsl_sai_hw_free,
.trigger = fsl_sai_trigger,
.startup = fsl_sai_startup,
};
static int fsl_sai_dai_resume(struct snd_soc_component *component)
{
struct fsl_sai *sai = snd_soc_component_get_drvdata(component);
struct device *dev = &sai->pdev->dev;
int ret;
if (!IS_ERR_OR_NULL(sai->pinctrl) && !IS_ERR_OR_NULL(sai->pins_state)) {
ret = pinctrl_select_state(sai->pinctrl, sai->pins_state);
if (ret) {
dev_err(dev, "failed to set proper pins state: %d\n", ret);
return ret;
}
}
return 0;
}
static struct snd_soc_dai_driver fsl_sai_dai_template = {
.playback = {
.stream_name = "CPU-Playback",
.channels_min = 1,
.channels_max = 32,
.rate_min = 8000,
.rate_max = 2822400,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = FSL_SAI_FORMATS,
},
.capture = {
.stream_name = "CPU-Capture",
.channels_min = 1,
.channels_max = 32,
.rate_min = 8000,
.rate_max = 2822400,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = FSL_SAI_FORMATS,
},
.ops = &fsl_sai_pcm_dai_ops,
};
static const struct snd_soc_component_driver fsl_component = {
.name = "fsl-sai",
.resume = fsl_sai_dai_resume,
.legacy_dai_naming = 1,
};
static struct reg_default fsl_sai_reg_defaults_ofs0[] = {
{FSL_SAI_TCR1(0), 0},
{FSL_SAI_TCR2(0), 0},
{FSL_SAI_TCR3(0), 0},
{FSL_SAI_TCR4(0), 0},
{FSL_SAI_TCR5(0), 0},
{FSL_SAI_TDR0, 0},
{FSL_SAI_TDR1, 0},
{FSL_SAI_TDR2, 0},
{FSL_SAI_TDR3, 0},
{FSL_SAI_TDR4, 0},
{FSL_SAI_TDR5, 0},
{FSL_SAI_TDR6, 0},
{FSL_SAI_TDR7, 0},
{FSL_SAI_TMR, 0},
{FSL_SAI_RCR1(0), 0},
{FSL_SAI_RCR2(0), 0},
{FSL_SAI_RCR3(0), 0},
{FSL_SAI_RCR4(0), 0},
{FSL_SAI_RCR5(0), 0},
{FSL_SAI_RMR, 0},
};
static struct reg_default fsl_sai_reg_defaults_ofs8[] = {
{FSL_SAI_TCR1(8), 0},
{FSL_SAI_TCR2(8), 0},
{FSL_SAI_TCR3(8), 0},
{FSL_SAI_TCR4(8), 0},
{FSL_SAI_TCR5(8), 0},
{FSL_SAI_TDR0, 0},
{FSL_SAI_TDR1, 0},
{FSL_SAI_TDR2, 0},
{FSL_SAI_TDR3, 0},
{FSL_SAI_TDR4, 0},
{FSL_SAI_TDR5, 0},
{FSL_SAI_TDR6, 0},
{FSL_SAI_TDR7, 0},
{FSL_SAI_TMR, 0},
{FSL_SAI_RCR1(8), 0},
{FSL_SAI_RCR2(8), 0},
{FSL_SAI_RCR3(8), 0},
{FSL_SAI_RCR4(8), 0},
{FSL_SAI_RCR5(8), 0},
{FSL_SAI_RMR, 0},
{FSL_SAI_MCTL, 0},
{FSL_SAI_MDIV, 0},
};
static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
{
struct fsl_sai *sai = dev_get_drvdata(dev);
unsigned int ofs = sai->soc_data->reg_offset;
if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs))
return true;
if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs))
return true;
switch (reg) {
case FSL_SAI_TFR0:
case FSL_SAI_TFR1:
case FSL_SAI_TFR2:
case FSL_SAI_TFR3:
case FSL_SAI_TFR4:
case FSL_SAI_TFR5:
case FSL_SAI_TFR6:
case FSL_SAI_TFR7:
case FSL_SAI_TMR:
case FSL_SAI_RDR0:
case FSL_SAI_RDR1:
case FSL_SAI_RDR2:
case FSL_SAI_RDR3:
case FSL_SAI_RDR4:
case FSL_SAI_RDR5:
case FSL_SAI_RDR6:
case FSL_SAI_RDR7:
case FSL_SAI_RFR0:
case FSL_SAI_RFR1:
case FSL_SAI_RFR2:
case FSL_SAI_RFR3:
case FSL_SAI_RFR4:
case FSL_SAI_RFR5:
case FSL_SAI_RFR6:
case FSL_SAI_RFR7:
case FSL_SAI_RMR:
case FSL_SAI_MCTL:
case FSL_SAI_MDIV:
case FSL_SAI_VERID:
case FSL_SAI_PARAM:
case FSL_SAI_TTCTN:
case FSL_SAI_RTCTN:
case FSL_SAI_TTCTL:
case FSL_SAI_TBCTN:
case FSL_SAI_TTCAP:
case FSL_SAI_RTCTL:
case FSL_SAI_RBCTN:
case FSL_SAI_RTCAP:
return true;
default:
return false;
}
}
static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg)
{
struct fsl_sai *sai = dev_get_drvdata(dev);
unsigned int ofs = sai->soc_data->reg_offset;
if (reg == FSL_SAI_TCSR(ofs) || reg == FSL_SAI_RCSR(ofs))
return true;
/* Set VERID and PARAM be volatile for reading value in probe */
if (ofs == 8 && (reg == FSL_SAI_VERID || reg == FSL_SAI_PARAM))
return true;
switch (reg) {
case FSL_SAI_TFR0:
case FSL_SAI_TFR1:
case FSL_SAI_TFR2:
case FSL_SAI_TFR3:
case FSL_SAI_TFR4:
case FSL_SAI_TFR5:
case FSL_SAI_TFR6:
case FSL_SAI_TFR7:
case FSL_SAI_RFR0:
case FSL_SAI_RFR1:
case FSL_SAI_RFR2:
case FSL_SAI_RFR3:
case FSL_SAI_RFR4:
case FSL_SAI_RFR5:
case FSL_SAI_RFR6:
case FSL_SAI_RFR7:
case FSL_SAI_RDR0:
case FSL_SAI_RDR1:
case FSL_SAI_RDR2:
case FSL_SAI_RDR3:
case FSL_SAI_RDR4:
case FSL_SAI_RDR5:
case FSL_SAI_RDR6:
case FSL_SAI_RDR7:
return true;
default:
return false;
}
}
static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg)
{
struct fsl_sai *sai = dev_get_drvdata(dev);
unsigned int ofs = sai->soc_data->reg_offset;
if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs))
return true;
if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs))
return true;
switch (reg) {
case FSL_SAI_TDR0:
case FSL_SAI_TDR1:
case FSL_SAI_TDR2:
case FSL_SAI_TDR3:
case FSL_SAI_TDR4:
case FSL_SAI_TDR5:
case FSL_SAI_TDR6:
case FSL_SAI_TDR7:
case FSL_SAI_TMR:
case FSL_SAI_RMR:
case FSL_SAI_MCTL:
case FSL_SAI_MDIV:
case FSL_SAI_TTCTL:
case FSL_SAI_RTCTL:
return true;
default:
return false;
}
}
static struct regmap_config fsl_sai_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.fast_io = true,
.max_register = FSL_SAI_RMR,
.reg_defaults = fsl_sai_reg_defaults_ofs0,
.num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults_ofs0),
.readable_reg = fsl_sai_readable_reg,
.volatile_reg = fsl_sai_volatile_reg,
.writeable_reg = fsl_sai_writeable_reg,
.cache_type = REGCACHE_FLAT,
};
static int fsl_sai_check_version(struct device *dev)
{
struct fsl_sai *sai = dev_get_drvdata(dev);
unsigned char ofs = sai->soc_data->reg_offset;
unsigned int val;
int ret;
if (FSL_SAI_TCSR(ofs) == FSL_SAI_VERID)
return 0;
ret = regmap_read(sai->regmap, FSL_SAI_VERID, &val);
if (ret < 0)
return ret;
dev_dbg(dev, "VERID: 0x%016X\n", val);
sai->verid.version = val &
(FSL_SAI_VERID_MAJOR_MASK | FSL_SAI_VERID_MINOR_MASK);
sai->verid.version >>= FSL_SAI_VERID_MINOR_SHIFT;
sai->verid.feature = val & FSL_SAI_VERID_FEATURE_MASK;
ret = regmap_read(sai->regmap, FSL_SAI_PARAM, &val);
if (ret < 0)
return ret;
dev_dbg(dev, "PARAM: 0x%016X\n", val);
/* Max slots per frame, power of 2 */
sai->param.slot_num = 1 <<
((val & FSL_SAI_PARAM_SPF_MASK) >> FSL_SAI_PARAM_SPF_SHIFT);
/* Words per fifo, power of 2 */
sai->param.fifo_depth = 1 <<
((val & FSL_SAI_PARAM_WPF_MASK) >> FSL_SAI_PARAM_WPF_SHIFT);
/* Number of datalines implemented */
sai->param.dataline = val & FSL_SAI_PARAM_DLN_MASK;
return 0;
}
/*
* Calculate the offset between first two datalines, don't
* different offset in one case.
*/
static unsigned int fsl_sai_calc_dl_off(unsigned long dl_mask)
{
int fbidx, nbidx, offset;
fbidx = find_first_bit(&dl_mask, FSL_SAI_DL_NUM);
nbidx = find_next_bit(&dl_mask, FSL_SAI_DL_NUM, fbidx + 1);
offset = nbidx - fbidx - 1;
return (offset < 0 || offset >= (FSL_SAI_DL_NUM - 1) ? 0 : offset);
}
/*
* read the fsl,dataline property from dts file.
* It has 3 value for each configuration, first one means the type:
* I2S(1) or PDM(2), second one is dataline mask for 'rx', third one is
* dataline mask for 'tx'. for example
*
* fsl,dataline = <1 0xff 0xff 2 0xff 0x11>,
*
* It means I2S type rx mask is 0xff, tx mask is 0xff, PDM type
* rx mask is 0xff, tx mask is 0x11 (dataline 1 and 4 enabled).
*
*/
static int fsl_sai_read_dlcfg(struct fsl_sai *sai)
{
struct platform_device *pdev = sai->pdev;
struct device_node *np = pdev->dev.of_node;
struct device *dev = &pdev->dev;
int ret, elems, i, index, num_cfg;
char *propname = "fsl,dataline";
struct fsl_sai_dl_cfg *cfg;
unsigned long dl_mask;
unsigned int soc_dl;
u32 rx, tx, type;
elems = of_property_count_u32_elems(np, propname);
if (elems <= 0) {
elems = 0;
} else if (elems % 3) {
dev_err(dev, "Number of elements must be divisible to 3.\n");
return -EINVAL;
}
num_cfg = elems / 3;
/* Add one more for default value */
cfg = devm_kzalloc(&pdev->dev, (num_cfg + 1) * sizeof(*cfg), GFP_KERNEL);
if (!cfg)
return -ENOMEM;
/* Consider default value "0 0xFF 0xFF" if property is missing */
soc_dl = BIT(sai->soc_data->pins) - 1;
cfg[0].type = FSL_SAI_DL_DEFAULT;
cfg[0].pins[0] = sai->soc_data->pins;
cfg[0].mask[0] = soc_dl;
cfg[0].start_off[0] = 0;
cfg[0].next_off[0] = 0;
cfg[0].pins[1] = sai->soc_data->pins;
cfg[0].mask[1] = soc_dl;
cfg[0].start_off[1] = 0;
cfg[0].next_off[1] = 0;
for (i = 1, index = 0; i < num_cfg + 1; i++) {
/*
* type of dataline
* 0 means default mode
* 1 means I2S mode
* 2 means PDM mode
*/
ret = of_property_read_u32_index(np, propname, index++, &type);
if (ret)
return -EINVAL;
ret = of_property_read_u32_index(np, propname, index++, &rx);
if (ret)
return -EINVAL;
ret = of_property_read_u32_index(np, propname, index++, &tx);
if (ret)
return -EINVAL;
if ((rx & ~soc_dl) || (tx & ~soc_dl)) {
dev_err(dev, "dataline cfg[%d] setting error, mask is 0x%x\n", i, soc_dl);
return -EINVAL;
}
rx = rx & soc_dl;
tx = tx & soc_dl;
cfg[i].type = type;
cfg[i].pins[0] = hweight8(rx);
cfg[i].mask[0] = rx;
dl_mask = rx;
cfg[i].start_off[0] = find_first_bit(&dl_mask, FSL_SAI_DL_NUM);
cfg[i].next_off[0] = fsl_sai_calc_dl_off(rx);
cfg[i].pins[1] = hweight8(tx);
cfg[i].mask[1] = tx;
dl_mask = tx;
cfg[i].start_off[1] = find_first_bit(&dl_mask, FSL_SAI_DL_NUM);
cfg[i].next_off[1] = fsl_sai_calc_dl_off(tx);
}
sai->dl_cfg = cfg;
sai->dl_cfg_cnt = num_cfg + 1;
return 0;
}
static int fsl_sai_runtime_suspend(struct device *dev);
static int fsl_sai_runtime_resume(struct device *dev);
static int fsl_sai_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct device *dev = &pdev->dev;
struct fsl_sai *sai;
struct regmap *gpr;
void __iomem *base;
char tmp[8];
int irq, ret, i;
int index;
u32 dmas[4];
sai = devm_kzalloc(dev, sizeof(*sai), GFP_KERNEL);
if (!sai)
return -ENOMEM;
sai->pdev = pdev;
sai->soc_data = of_device_get_match_data(dev);
sai->is_lsb_first = of_property_read_bool(np, "lsb-first");
base = devm_platform_get_and_ioremap_resource(pdev, 0, &sai->res);
if (IS_ERR(base))
return PTR_ERR(base);
if (sai->soc_data->reg_offset == 8) {
fsl_sai_regmap_config.reg_defaults = fsl_sai_reg_defaults_ofs8;
fsl_sai_regmap_config.max_register = FSL_SAI_MDIV;
fsl_sai_regmap_config.num_reg_defaults =
ARRAY_SIZE(fsl_sai_reg_defaults_ofs8);
}
sai->regmap = devm_regmap_init_mmio(dev, base, &fsl_sai_regmap_config);
if (IS_ERR(sai->regmap)) {
dev_err(dev, "regmap init failed\n");
return PTR_ERR(sai->regmap);
}
sai->bus_clk = devm_clk_get(dev, "bus");
/* Compatible with old DTB cases */
if (IS_ERR(sai->bus_clk) && PTR_ERR(sai->bus_clk) != -EPROBE_DEFER)
sai->bus_clk = devm_clk_get(dev, "sai");
if (IS_ERR(sai->bus_clk)) {
dev_err(dev, "failed to get bus clock: %ld\n",
PTR_ERR(sai->bus_clk));
/* -EPROBE_DEFER */
return PTR_ERR(sai->bus_clk);
}
for (i = 1; i < FSL_SAI_MCLK_MAX; i++) {
sprintf(tmp, "mclk%d", i);
sai->mclk_clk[i] = devm_clk_get(dev, tmp);
if (IS_ERR(sai->mclk_clk[i])) {
dev_err(dev, "failed to get mclk%d clock: %ld\n",
i, PTR_ERR(sai->mclk_clk[i]));
sai->mclk_clk[i] = NULL;
}
}
if (sai->soc_data->mclk0_is_mclk1)
sai->mclk_clk[0] = sai->mclk_clk[1];
else
sai->mclk_clk[0] = sai->bus_clk;
fsl_asoc_get_pll_clocks(&pdev->dev, &sai->pll8k_clk,
&sai->pll11k_clk);
/* Use Multi FIFO mode depending on the support from SDMA script */
ret = of_property_read_u32_array(np, "dmas", dmas, 4);
if (!sai->soc_data->use_edma && !ret && dmas[2] == IMX_DMATYPE_MULTI_SAI)
sai->is_multi_fifo_dma = true;
/* read dataline mask for rx and tx*/
ret = fsl_sai_read_dlcfg(sai);
if (ret < 0) {
dev_err(dev, "failed to read dlcfg %d\n", ret);
return ret;
}
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
ret = devm_request_irq(dev, irq, fsl_sai_isr, IRQF_SHARED,
np->name, sai);
if (ret) {
dev_err(dev, "failed to claim irq %u\n", irq);
return ret;
}
memcpy(&sai->cpu_dai_drv, &fsl_sai_dai_template,
sizeof(fsl_sai_dai_template));
/* Sync Tx with Rx as default by following old DT binding */
sai->synchronous[RX] = true;
sai->synchronous[TX] = false;
sai->cpu_dai_drv.symmetric_rate = 1;
sai->cpu_dai_drv.symmetric_channels = 1;
sai->cpu_dai_drv.symmetric_sample_bits = 1;
if (of_property_read_bool(np, "fsl,sai-synchronous-rx") &&
of_property_read_bool(np, "fsl,sai-asynchronous")) {
/* error out if both synchronous and asynchronous are present */
dev_err(dev, "invalid binding for synchronous mode\n");
return -EINVAL;
}
if (of_property_read_bool(np, "fsl,sai-synchronous-rx")) {
/* Sync Rx with Tx */
sai->synchronous[RX] = false;
sai->synchronous[TX] = true;
} else if (of_property_read_bool(np, "fsl,sai-asynchronous")) {
/* Discard all settings for asynchronous mode */
sai->synchronous[RX] = false;
sai->synchronous[TX] = false;
sai->cpu_dai_drv.symmetric_rate = 0;
sai->cpu_dai_drv.symmetric_channels = 0;
sai->cpu_dai_drv.symmetric_sample_bits = 0;
}
sai->mclk_direction_output = of_property_read_bool(np, "fsl,sai-mclk-direction-output");
if (sai->mclk_direction_output &&
of_device_is_compatible(np, "fsl,imx6ul-sai")) {
gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr");
if (IS_ERR(gpr)) {
dev_err(dev, "cannot find iomuxc registers\n");
return PTR_ERR(gpr);
}
index = of_alias_get_id(np, "sai");
if (index < 0)
return index;
regmap_update_bits(gpr, IOMUXC_GPR1, MCLK_DIR(index),
MCLK_DIR(index));
}
sai->dma_params_rx.addr = sai->res->start + FSL_SAI_RDR0;
sai->dma_params_tx.addr = sai->res->start + FSL_SAI_TDR0;
sai->dma_params_rx.maxburst =
sai->soc_data->max_burst[RX] ? sai->soc_data->max_burst[RX] : FSL_SAI_MAXBURST_RX;
sai->dma_params_tx.maxburst =
sai->soc_data->max_burst[TX] ? sai->soc_data->max_burst[TX] : FSL_SAI_MAXBURST_TX;
sai->pinctrl = devm_pinctrl_get(&pdev->dev);
platform_set_drvdata(pdev, sai);
pm_runtime_enable(dev);
if (!pm_runtime_enabled(dev)) {
ret = fsl_sai_runtime_resume(dev);
if (ret)
goto err_pm_disable;
}
ret = pm_runtime_resume_and_get(dev);
if (ret < 0)
goto err_pm_get_sync;
/* Get sai version */
ret = fsl_sai_check_version(dev);
if (ret < 0)
dev_warn(dev, "Error reading SAI version: %d\n", ret);
/* Select MCLK direction */
if (sai->mclk_direction_output &&
sai->soc_data->max_register >= FSL_SAI_MCTL) {
regmap_update_bits(sai->regmap, FSL_SAI_MCTL,
FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN);
}
ret = pm_runtime_put_sync(dev);
if (ret < 0 && ret != -ENOSYS)
goto err_pm_get_sync;
/*
* Register platform component before registering cpu dai for there
* is not defer probe for platform component in snd_soc_add_pcm_runtime().
*/
if (sai->soc_data->use_imx_pcm) {
ret = imx_pcm_dma_init(pdev);
if (ret) {
dev_err_probe(dev, ret, "PCM DMA init failed\n");
if (!IS_ENABLED(CONFIG_SND_SOC_IMX_PCM_DMA))
dev_err(dev, "Error: You must enable the imx-pcm-dma support!\n");
goto err_pm_get_sync;
}
} else {
ret = devm_snd_dmaengine_pcm_register(dev, NULL, 0);
if (ret) {
dev_err_probe(dev, ret, "Registering PCM dmaengine failed\n");
goto err_pm_get_sync;
}
}
ret = devm_snd_soc_register_component(dev, &fsl_component,
&sai->cpu_dai_drv, 1);
if (ret)
goto err_pm_get_sync;
return ret;
err_pm_get_sync:
if (!pm_runtime_status_suspended(dev))
fsl_sai_runtime_suspend(dev);
err_pm_disable:
pm_runtime_disable(dev);
return ret;
}
static void fsl_sai_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
if (!pm_runtime_status_suspended(&pdev->dev))
fsl_sai_runtime_suspend(&pdev->dev);
}
static const struct fsl_sai_soc_data fsl_sai_vf610_data = {
.use_imx_pcm = false,
.use_edma = false,
.fifo_depth = 32,
.pins = 1,
.reg_offset = 0,
.mclk0_is_mclk1 = false,
.flags = 0,
.max_register = FSL_SAI_RMR,
};
static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = {
.use_imx_pcm = true,
.use_edma = false,
.fifo_depth = 32,
.pins = 1,
.reg_offset = 0,
.mclk0_is_mclk1 = true,
.flags = 0,
.max_register = FSL_SAI_RMR,
};
static const struct fsl_sai_soc_data fsl_sai_imx7ulp_data = {
.use_imx_pcm = true,
.use_edma = false,
.fifo_depth = 16,
.pins = 2,
.reg_offset = 8,
.mclk0_is_mclk1 = false,
.flags = PMQOS_CPU_LATENCY,
.max_register = FSL_SAI_RMR,
};
static const struct fsl_sai_soc_data fsl_sai_imx8mq_data = {
.use_imx_pcm = true,
.use_edma = false,
.fifo_depth = 128,
.pins = 8,
.reg_offset = 8,
.mclk0_is_mclk1 = false,
.flags = 0,
.max_register = FSL_SAI_RMR,
};
static const struct fsl_sai_soc_data fsl_sai_imx8qm_data = {
.use_imx_pcm = true,
.use_edma = true,
.fifo_depth = 64,
.pins = 4,
.reg_offset = 0,
.mclk0_is_mclk1 = false,
.flags = 0,
.max_register = FSL_SAI_RMR,
};
static const struct fsl_sai_soc_data fsl_sai_imx8mm_data = {
.use_imx_pcm = true,
.use_edma = false,
.fifo_depth = 128,
.reg_offset = 8,
.mclk0_is_mclk1 = false,
.pins = 8,
.flags = 0,
.max_register = FSL_SAI_MCTL,
};
static const struct fsl_sai_soc_data fsl_sai_imx8mn_data = {
.use_imx_pcm = true,
.use_edma = false,
.fifo_depth = 128,
.reg_offset = 8,
.mclk0_is_mclk1 = false,
.pins = 8,
.flags = 0,
.max_register = FSL_SAI_MDIV,
};
static const struct fsl_sai_soc_data fsl_sai_imx8mp_data = {
.use_imx_pcm = true,
.use_edma = false,
.fifo_depth = 128,
.reg_offset = 8,
.mclk0_is_mclk1 = false,
.pins = 8,
.flags = 0,
.max_register = FSL_SAI_MDIV,
.mclk_with_tere = true,
};
static const struct fsl_sai_soc_data fsl_sai_imx8ulp_data = {
.use_imx_pcm = true,
.use_edma = true,
.fifo_depth = 16,
.reg_offset = 8,
.mclk0_is_mclk1 = false,
.pins = 4,
.flags = PMQOS_CPU_LATENCY,
.max_register = FSL_SAI_RTCAP,
};
static const struct fsl_sai_soc_data fsl_sai_imx93_data = {
.use_imx_pcm = true,
.use_edma = true,
.fifo_depth = 128,
.reg_offset = 8,
.mclk0_is_mclk1 = false,
.pins = 4,
.flags = 0,
.max_register = FSL_SAI_MCTL,
.max_burst = {8, 8},
};
static const struct of_device_id fsl_sai_ids[] = {
{ .compatible = "fsl,vf610-sai", .data = &fsl_sai_vf610_data },
{ .compatible = "fsl,imx6sx-sai", .data = &fsl_sai_imx6sx_data },
{ .compatible = "fsl,imx6ul-sai", .data = &fsl_sai_imx6sx_data },
{ .compatible = "fsl,imx7ulp-sai", .data = &fsl_sai_imx7ulp_data },
{ .compatible = "fsl,imx8mq-sai", .data = &fsl_sai_imx8mq_data },
{ .compatible = "fsl,imx8qm-sai", .data = &fsl_sai_imx8qm_data },
{ .compatible = "fsl,imx8mm-sai", .data = &fsl_sai_imx8mm_data },
{ .compatible = "fsl,imx8mp-sai", .data = &fsl_sai_imx8mp_data },
{ .compatible = "fsl,imx8ulp-sai", .data = &fsl_sai_imx8ulp_data },
{ .compatible = "fsl,imx8mn-sai", .data = &fsl_sai_imx8mn_data },
{ .compatible = "fsl,imx93-sai", .data = &fsl_sai_imx93_data },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, fsl_sai_ids);
static int fsl_sai_runtime_suspend(struct device *dev)
{
struct fsl_sai *sai = dev_get_drvdata(dev);
if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE))
clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]);
if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK))
clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]);
clk_disable_unprepare(sai->bus_clk);
if (sai->soc_data->flags & PMQOS_CPU_LATENCY)
cpu_latency_qos_remove_request(&sai->pm_qos_req);
regcache_cache_only(sai->regmap, true);
return 0;
}
static int fsl_sai_runtime_resume(struct device *dev)
{
struct fsl_sai *sai = dev_get_drvdata(dev);
unsigned int ofs = sai->soc_data->reg_offset;
int ret;
ret = clk_prepare_enable(sai->bus_clk);
if (ret) {
dev_err(dev, "failed to enable bus clock: %d\n", ret);
return ret;
}
if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) {
ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[1]]);
if (ret)
goto disable_bus_clk;
}
if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) {
ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[0]]);
if (ret)
goto disable_tx_clk;
}
if (sai->soc_data->flags & PMQOS_CPU_LATENCY)
cpu_latency_qos_add_request(&sai->pm_qos_req, 0);
regcache_cache_only(sai->regmap, false);
regcache_mark_dirty(sai->regmap);
regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR);
regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR);
usleep_range(1000, 2000);
regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0);
regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0);
ret = regcache_sync(sai->regmap);
if (ret)
goto disable_rx_clk;
if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output)
regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs),
FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
return 0;
disable_rx_clk:
if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE))
clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]);
disable_tx_clk:
if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK))
clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]);
disable_bus_clk:
clk_disable_unprepare(sai->bus_clk);
return ret;
}
static const struct dev_pm_ops fsl_sai_pm_ops = {
SET_RUNTIME_PM_OPS(fsl_sai_runtime_suspend,
fsl_sai_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
};
static struct platform_driver fsl_sai_driver = {
.probe = fsl_sai_probe,
.remove_new = fsl_sai_remove,
.driver = {
.name = "fsl-sai",
.pm = &fsl_sai_pm_ops,
.of_match_table = fsl_sai_ids,
},
};
module_platform_driver(fsl_sai_driver);
MODULE_DESCRIPTION("Freescale Soc SAI Interface");
MODULE_AUTHOR("Xiubo Li, <[email protected]>");
MODULE_ALIAS("platform:fsl-sai");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/fsl/fsl_sai.c |
// SPDX-License-Identifier: GPL-2.0
//
// linux/sound/mpc5200-ac97.c -- AC97 support for the Freescale MPC52xx chip.
//
// Copyright (C) 2009 Jon Smirl, Digispeaker
// Author: Jon Smirl <[email protected]>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/of_platform.h>
#include <linux/delay.h>
#include <linux/time.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <asm/time.h>
#include <asm/delay.h>
#include <asm/mpc52xx.h>
#include <asm/mpc52xx_psc.h>
#include "mpc5200_dma.h"
#define DRV_NAME "mpc5200-psc-ac97"
/* ALSA only supports a single AC97 device so static is recommend here */
static struct psc_dma *psc_dma;
static unsigned short psc_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
{
int status;
unsigned int val;
mutex_lock(&psc_dma->mutex);
/* Wait for command send status zero = ready */
status = spin_event_timeout(!(in_be16(&psc_dma->psc_regs->sr_csr.status) &
MPC52xx_PSC_SR_CMDSEND), 100, 0);
if (status == 0) {
pr_err("timeout on ac97 bus (rdy)\n");
mutex_unlock(&psc_dma->mutex);
return -ENODEV;
}
/* Force clear the data valid bit */
in_be32(&psc_dma->psc_regs->ac97_data);
/* Send the read */
out_be32(&psc_dma->psc_regs->ac97_cmd, (1<<31) | ((reg & 0x7f) << 24));
/* Wait for the answer */
status = spin_event_timeout((in_be16(&psc_dma->psc_regs->sr_csr.status) &
MPC52xx_PSC_SR_DATA_VAL), 100, 0);
if (status == 0) {
pr_err("timeout on ac97 read (val) %x\n",
in_be16(&psc_dma->psc_regs->sr_csr.status));
mutex_unlock(&psc_dma->mutex);
return -ENODEV;
}
/* Get the data */
val = in_be32(&psc_dma->psc_regs->ac97_data);
if (((val >> 24) & 0x7f) != reg) {
pr_err("reg echo error on ac97 read\n");
mutex_unlock(&psc_dma->mutex);
return -ENODEV;
}
val = (val >> 8) & 0xffff;
mutex_unlock(&psc_dma->mutex);
return (unsigned short) val;
}
static void psc_ac97_write(struct snd_ac97 *ac97,
unsigned short reg, unsigned short val)
{
int status;
mutex_lock(&psc_dma->mutex);
/* Wait for command status zero = ready */
status = spin_event_timeout(!(in_be16(&psc_dma->psc_regs->sr_csr.status) &
MPC52xx_PSC_SR_CMDSEND), 100, 0);
if (status == 0) {
pr_err("timeout on ac97 bus (write)\n");
goto out;
}
/* Write data */
out_be32(&psc_dma->psc_regs->ac97_cmd,
((reg & 0x7f) << 24) | (val << 8));
out:
mutex_unlock(&psc_dma->mutex);
}
static void psc_ac97_warm_reset(struct snd_ac97 *ac97)
{
struct mpc52xx_psc __iomem *regs = psc_dma->psc_regs;
mutex_lock(&psc_dma->mutex);
out_be32(®s->sicr, psc_dma->sicr | MPC52xx_PSC_SICR_AWR);
udelay(3);
out_be32(®s->sicr, psc_dma->sicr);
mutex_unlock(&psc_dma->mutex);
}
static void psc_ac97_cold_reset(struct snd_ac97 *ac97)
{
struct mpc52xx_psc __iomem *regs = psc_dma->psc_regs;
mutex_lock(&psc_dma->mutex);
dev_dbg(psc_dma->dev, "cold reset\n");
mpc5200_psc_ac97_gpio_reset(psc_dma->id);
/* Notify the PSC that a reset has occurred */
out_be32(®s->sicr, psc_dma->sicr | MPC52xx_PSC_SICR_ACRB);
/* Re-enable RX and TX */
out_8(®s->command, MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);
mutex_unlock(&psc_dma->mutex);
usleep_range(1000, 2000);
psc_ac97_warm_reset(ac97);
}
static struct snd_ac97_bus_ops psc_ac97_ops = {
.read = psc_ac97_read,
.write = psc_ac97_write,
.reset = psc_ac97_cold_reset,
.warm_reset = psc_ac97_warm_reset,
};
static int psc_ac97_hw_analog_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *cpu_dai)
{
struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(cpu_dai);
struct psc_dma_stream *s = to_psc_dma_stream(substream, psc_dma);
dev_dbg(psc_dma->dev, "%s(substream=%p) p_size=%i p_bytes=%i"
" periods=%i buffer_size=%i buffer_bytes=%i channels=%i"
" rate=%i format=%i\n",
__func__, substream, params_period_size(params),
params_period_bytes(params), params_periods(params),
params_buffer_size(params), params_buffer_bytes(params),
params_channels(params), params_rate(params),
params_format(params));
/* Determine the set of enable bits to turn on */
s->ac97_slot_bits = (params_channels(params) == 1) ? 0x100 : 0x300;
if (substream->pstr->stream != SNDRV_PCM_STREAM_CAPTURE)
s->ac97_slot_bits <<= 16;
return 0;
}
static int psc_ac97_hw_digital_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *cpu_dai)
{
struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(cpu_dai);
dev_dbg(psc_dma->dev, "%s(substream=%p)\n", __func__, substream);
if (params_channels(params) == 1)
out_be32(&psc_dma->psc_regs->ac97_slots, 0x01000000);
else
out_be32(&psc_dma->psc_regs->ac97_slots, 0x03000000);
return 0;
}
static int psc_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(dai);
struct psc_dma_stream *s = to_psc_dma_stream(substream, psc_dma);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
dev_dbg(psc_dma->dev, "AC97 START: stream=%i\n",
substream->pstr->stream);
/* Set the slot enable bits */
psc_dma->slots |= s->ac97_slot_bits;
out_be32(&psc_dma->psc_regs->ac97_slots, psc_dma->slots);
break;
case SNDRV_PCM_TRIGGER_STOP:
dev_dbg(psc_dma->dev, "AC97 STOP: stream=%i\n",
substream->pstr->stream);
/* Clear the slot enable bits */
psc_dma->slots &= ~(s->ac97_slot_bits);
out_be32(&psc_dma->psc_regs->ac97_slots, psc_dma->slots);
break;
}
return 0;
}
static int psc_ac97_probe(struct snd_soc_dai *cpu_dai)
{
struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(cpu_dai);
struct mpc52xx_psc __iomem *regs = psc_dma->psc_regs;
/* Go */
out_8(®s->command, MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);
return 0;
}
/* ---------------------------------------------------------------------
* ALSA SoC Bindings
*
* - Digital Audio Interface (DAI) template
* - create/destroy dai hooks
*/
/**
* psc_ac97_dai_template: template CPU Digital Audio Interface
*/
static const struct snd_soc_dai_ops psc_ac97_analog_ops = {
.probe = psc_ac97_probe,
.hw_params = psc_ac97_hw_analog_params,
.trigger = psc_ac97_trigger,
};
static const struct snd_soc_dai_ops psc_ac97_digital_ops = {
.hw_params = psc_ac97_hw_digital_params,
};
static struct snd_soc_dai_driver psc_ac97_dai[] = {
{
.name = "mpc5200-psc-ac97.0",
.playback = {
.stream_name = "AC97 Playback",
.channels_min = 1,
.channels_max = 6,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S32_BE,
},
.capture = {
.stream_name = "AC97 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S32_BE,
},
.ops = &psc_ac97_analog_ops,
},
{
.name = "mpc5200-psc-ac97.1",
.playback = {
.stream_name = "AC97 SPDIF",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_32000 | \
SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
.formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_BE,
},
.ops = &psc_ac97_digital_ops,
} };
static const struct snd_soc_component_driver psc_ac97_component = {
.name = DRV_NAME,
};
/* ---------------------------------------------------------------------
* OF platform bus binding code:
* - Probe/remove operations
* - OF device match table
*/
static int psc_ac97_of_probe(struct platform_device *op)
{
int rc;
struct mpc52xx_psc __iomem *regs;
rc = mpc5200_audio_dma_create(op);
if (rc != 0)
return rc;
rc = snd_soc_set_ac97_ops(&psc_ac97_ops);
if (rc != 0) {
dev_err(&op->dev, "Failed to set AC'97 ops: %d\n", rc);
return rc;
}
rc = snd_soc_register_component(&op->dev, &psc_ac97_component,
psc_ac97_dai, ARRAY_SIZE(psc_ac97_dai));
if (rc != 0) {
dev_err(&op->dev, "Failed to register DAI\n");
return rc;
}
psc_dma = dev_get_drvdata(&op->dev);
regs = psc_dma->psc_regs;
psc_dma->imr = 0;
out_be16(&psc_dma->psc_regs->isr_imr.imr, psc_dma->imr);
/* Configure the serial interface mode to AC97 */
psc_dma->sicr = MPC52xx_PSC_SICR_SIM_AC97 | MPC52xx_PSC_SICR_ENAC97;
out_be32(®s->sicr, psc_dma->sicr);
/* No slots active */
out_be32(®s->ac97_slots, 0x00000000);
return 0;
}
static void psc_ac97_of_remove(struct platform_device *op)
{
mpc5200_audio_dma_destroy(op);
snd_soc_unregister_component(&op->dev);
snd_soc_set_ac97_ops(NULL);
}
/* Match table for of_platform binding */
static const struct of_device_id psc_ac97_match[] = {
{ .compatible = "fsl,mpc5200-psc-ac97", },
{ .compatible = "fsl,mpc5200b-psc-ac97", },
{}
};
MODULE_DEVICE_TABLE(of, psc_ac97_match);
static struct platform_driver psc_ac97_driver = {
.probe = psc_ac97_of_probe,
.remove_new = psc_ac97_of_remove,
.driver = {
.name = "mpc5200-psc-ac97",
.of_match_table = psc_ac97_match,
},
};
module_platform_driver(psc_ac97_driver);
MODULE_AUTHOR("Jon Smirl <[email protected]>");
MODULE_DESCRIPTION("mpc5200 AC97 module");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/fsl/mpc5200_psc_ac97.c |
// SPDX-License-Identifier: GPL-2.0
//
// Freescale ALSA SoC Machine driver utility
//
// Author: Timur Tabi <[email protected]>
//
// Copyright 2010 Freescale Semiconductor, Inc.
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <sound/soc.h>
#include "fsl_utils.h"
/**
* fsl_asoc_get_dma_channel - determine the dma channel for a SSI node
*
* @ssi_np: pointer to the SSI device tree node
* @name: name of the phandle pointing to the dma channel
* @dai: ASoC DAI link pointer to be filled with platform_name
* @dma_channel_id: dma channel id to be returned
* @dma_id: dma id to be returned
*
* This function determines the dma and channel id for given SSI node. It
* also discovers the platform_name for the ASoC DAI link.
*/
int fsl_asoc_get_dma_channel(struct device_node *ssi_np,
const char *name,
struct snd_soc_dai_link *dai,
unsigned int *dma_channel_id,
unsigned int *dma_id)
{
struct resource res;
struct device_node *dma_channel_np, *dma_np;
const __be32 *iprop;
int ret;
dma_channel_np = of_parse_phandle(ssi_np, name, 0);
if (!dma_channel_np)
return -EINVAL;
if (!of_device_is_compatible(dma_channel_np, "fsl,ssi-dma-channel")) {
of_node_put(dma_channel_np);
return -EINVAL;
}
/* Determine the dev_name for the device_node. This code mimics the
* behavior of of_device_make_bus_id(). We need this because ASoC uses
* the dev_name() of the device to match the platform (DMA) device with
* the CPU (SSI) device. It's all ugly and hackish, but it works (for
* now).
*
* dai->platform name should already point to an allocated buffer.
*/
ret = of_address_to_resource(dma_channel_np, 0, &res);
if (ret) {
of_node_put(dma_channel_np);
return ret;
}
snprintf((char *)dai->platforms->name, DAI_NAME_SIZE, "%llx.%pOFn",
(unsigned long long) res.start, dma_channel_np);
iprop = of_get_property(dma_channel_np, "cell-index", NULL);
if (!iprop) {
of_node_put(dma_channel_np);
return -EINVAL;
}
*dma_channel_id = be32_to_cpup(iprop);
dma_np = of_get_parent(dma_channel_np);
iprop = of_get_property(dma_np, "cell-index", NULL);
if (!iprop) {
of_node_put(dma_np);
of_node_put(dma_channel_np);
return -EINVAL;
}
*dma_id = be32_to_cpup(iprop);
of_node_put(dma_np);
of_node_put(dma_channel_np);
return 0;
}
EXPORT_SYMBOL(fsl_asoc_get_dma_channel);
/**
* fsl_asoc_get_pll_clocks - get two PLL clock source
*
* @dev: device pointer
* @pll8k_clk: PLL clock pointer for 8kHz
* @pll11k_clk: PLL clock pointer for 11kHz
*
* This function get two PLL clock source
*/
void fsl_asoc_get_pll_clocks(struct device *dev, struct clk **pll8k_clk,
struct clk **pll11k_clk)
{
*pll8k_clk = devm_clk_get(dev, "pll8k");
if (IS_ERR(*pll8k_clk))
*pll8k_clk = NULL;
*pll11k_clk = devm_clk_get(dev, "pll11k");
if (IS_ERR(*pll11k_clk))
*pll11k_clk = NULL;
}
EXPORT_SYMBOL(fsl_asoc_get_pll_clocks);
/**
* fsl_asoc_reparent_pll_clocks - set clock parent if necessary
*
* @dev: device pointer
* @clk: root clock pointer
* @pll8k_clk: PLL clock pointer for 8kHz
* @pll11k_clk: PLL clock pointer for 11kHz
* @ratio: target requency for root clock
*
* This function set root clock parent according to the target ratio
*/
void fsl_asoc_reparent_pll_clocks(struct device *dev, struct clk *clk,
struct clk *pll8k_clk,
struct clk *pll11k_clk, u64 ratio)
{
struct clk *p, *pll = NULL, *npll = NULL;
bool reparent = false;
int ret;
if (!clk || !pll8k_clk || !pll11k_clk)
return;
p = clk;
while (p && pll8k_clk && pll11k_clk) {
struct clk *pp = clk_get_parent(p);
if (clk_is_match(pp, pll8k_clk) ||
clk_is_match(pp, pll11k_clk)) {
pll = pp;
break;
}
p = pp;
}
npll = (do_div(ratio, 8000) ? pll11k_clk : pll8k_clk);
reparent = (pll && !clk_is_match(pll, npll));
if (reparent) {
ret = clk_set_parent(p, npll);
if (ret < 0)
dev_warn(dev, "failed to set parent:%d\n", ret);
}
}
EXPORT_SYMBOL(fsl_asoc_reparent_pll_clocks);
MODULE_AUTHOR("Timur Tabi <[email protected]>");
MODULE_DESCRIPTION("Freescale ASoC utility code");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/fsl/fsl_utils.c |
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2012 Freescale Semiconductor, Inc.
// Copyright 2012 Linaro Ltd.
#include <linux/gpio.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/i2c.h>
#include <linux/of_gpio.h>
#include <sound/soc.h>
#include <sound/jack.h>
#include "imx-audmux.h"
#define DAI_NAME_SIZE 32
#define MUX_PORT_MAX 7
struct imx_es8328_data {
struct device *dev;
struct snd_soc_dai_link dai;
struct snd_soc_card card;
char codec_dai_name[DAI_NAME_SIZE];
char platform_name[DAI_NAME_SIZE];
int jack_gpio;
};
static struct snd_soc_jack_gpio headset_jack_gpios[] = {
{
.gpio = -1,
.name = "headset-gpio",
.report = SND_JACK_HEADSET,
.invert = 0,
.debounce_time = 200,
},
};
static struct snd_soc_jack headset_jack;
static struct snd_soc_jack_pin headset_jack_pins[] = {
{
.pin = "Headphone",
.mask = SND_JACK_HEADPHONE,
},
{
.pin = "Mic Jack",
.mask = SND_JACK_MICROPHONE,
},
};
static int imx_es8328_dai_init(struct snd_soc_pcm_runtime *rtd)
{
struct imx_es8328_data *data = container_of(rtd->card,
struct imx_es8328_data, card);
int ret = 0;
/* Headphone jack detection */
if (gpio_is_valid(data->jack_gpio)) {
ret = snd_soc_card_jack_new_pins(rtd->card, "Headphone",
SND_JACK_HEADSET | SND_JACK_BTN_0,
&headset_jack,
headset_jack_pins,
ARRAY_SIZE(headset_jack_pins));
if (ret)
return ret;
headset_jack_gpios[0].gpio = data->jack_gpio;
ret = snd_soc_jack_add_gpios(&headset_jack,
ARRAY_SIZE(headset_jack_gpios),
headset_jack_gpios);
}
return ret;
}
static const struct snd_soc_dapm_widget imx_es8328_dapm_widgets[] = {
SND_SOC_DAPM_MIC("Mic Jack", NULL),
SND_SOC_DAPM_HP("Headphone", NULL),
SND_SOC_DAPM_SPK("Speaker", NULL),
SND_SOC_DAPM_REGULATOR_SUPPLY("audio-amp", 1, 0),
};
static const struct snd_kcontrol_new imx_es8328_controls[] = {
SOC_DAPM_PIN_SWITCH("Headphone"),
SOC_DAPM_PIN_SWITCH("Mic Jack"),
};
static int imx_es8328_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct device_node *ssi_np = NULL, *codec_np = NULL;
struct platform_device *ssi_pdev;
struct imx_es8328_data *data;
struct snd_soc_dai_link_component *comp;
u32 int_port, ext_port;
int ret;
struct device *dev = &pdev->dev;
ret = of_property_read_u32(np, "mux-int-port", &int_port);
if (ret) {
dev_err(dev, "mux-int-port missing or invalid\n");
goto fail;
}
if (int_port > MUX_PORT_MAX || int_port == 0) {
dev_err(dev, "mux-int-port: hardware only has %d mux ports\n",
MUX_PORT_MAX);
ret = -EINVAL;
goto fail;
}
ret = of_property_read_u32(np, "mux-ext-port", &ext_port);
if (ret) {
dev_err(dev, "mux-ext-port missing or invalid\n");
goto fail;
}
if (ext_port > MUX_PORT_MAX || ext_port == 0) {
dev_err(dev, "mux-ext-port: hardware only has %d mux ports\n",
MUX_PORT_MAX);
ret = -EINVAL;
goto fail;
}
/*
* The port numbering in the hardware manual starts at 1, while
* the audmux API expects it starts at 0.
*/
int_port--;
ext_port--;
ret = imx_audmux_v2_configure_port(int_port,
IMX_AUDMUX_V2_PTCR_SYN |
IMX_AUDMUX_V2_PTCR_TFSEL(ext_port) |
IMX_AUDMUX_V2_PTCR_TCSEL(ext_port) |
IMX_AUDMUX_V2_PTCR_TFSDIR |
IMX_AUDMUX_V2_PTCR_TCLKDIR,
IMX_AUDMUX_V2_PDCR_RXDSEL(ext_port));
if (ret) {
dev_err(dev, "audmux internal port setup failed\n");
return ret;
}
ret = imx_audmux_v2_configure_port(ext_port,
IMX_AUDMUX_V2_PTCR_SYN,
IMX_AUDMUX_V2_PDCR_RXDSEL(int_port));
if (ret) {
dev_err(dev, "audmux external port setup failed\n");
return ret;
}
ssi_np = of_parse_phandle(pdev->dev.of_node, "ssi-controller", 0);
codec_np = of_parse_phandle(pdev->dev.of_node, "audio-codec", 0);
if (!ssi_np || !codec_np) {
dev_err(dev, "phandle missing or invalid\n");
ret = -EINVAL;
goto fail;
}
ssi_pdev = of_find_device_by_node(ssi_np);
if (!ssi_pdev) {
dev_err(dev, "failed to find SSI platform device\n");
ret = -EINVAL;
goto fail;
}
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data) {
ret = -ENOMEM;
goto put_device;
}
comp = devm_kzalloc(dev, 2 * sizeof(*comp), GFP_KERNEL);
if (!comp) {
ret = -ENOMEM;
goto put_device;
}
data->dev = dev;
data->jack_gpio = of_get_named_gpio(pdev->dev.of_node, "jack-gpio", 0);
/*
* CPU == Platform
* platform is using soc-generic-dmaengine-pcm
*/
data->dai.cpus =
data->dai.platforms = &comp[0];
data->dai.codecs = &comp[1];
data->dai.num_cpus = 1;
data->dai.num_codecs = 1;
data->dai.num_platforms = 1;
data->dai.name = "hifi";
data->dai.stream_name = "hifi";
data->dai.codecs->dai_name = "es8328-hifi-analog";
data->dai.codecs->of_node = codec_np;
data->dai.cpus->of_node = ssi_np;
data->dai.init = &imx_es8328_dai_init;
data->dai.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBP_CFP;
data->card.dev = dev;
data->card.dapm_widgets = imx_es8328_dapm_widgets;
data->card.num_dapm_widgets = ARRAY_SIZE(imx_es8328_dapm_widgets);
data->card.controls = imx_es8328_controls;
data->card.num_controls = ARRAY_SIZE(imx_es8328_controls);
ret = snd_soc_of_parse_card_name(&data->card, "model");
if (ret) {
dev_err(dev, "Unable to parse card name\n");
goto put_device;
}
ret = snd_soc_of_parse_audio_routing(&data->card, "audio-routing");
if (ret) {
dev_err(dev, "Unable to parse routing: %d\n", ret);
goto put_device;
}
data->card.num_links = 1;
data->card.owner = THIS_MODULE;
data->card.dai_link = &data->dai;
ret = devm_snd_soc_register_card(&pdev->dev, &data->card);
if (ret) {
dev_err(dev, "Unable to register: %d\n", ret);
goto put_device;
}
platform_set_drvdata(pdev, data);
put_device:
put_device(&ssi_pdev->dev);
fail:
of_node_put(ssi_np);
of_node_put(codec_np);
return ret;
}
static const struct of_device_id imx_es8328_dt_ids[] = {
{ .compatible = "fsl,imx-audio-es8328", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx_es8328_dt_ids);
static struct platform_driver imx_es8328_driver = {
.driver = {
.name = "imx-es8328",
.of_match_table = imx_es8328_dt_ids,
},
.probe = imx_es8328_probe,
};
module_platform_driver(imx_es8328_driver);
MODULE_AUTHOR("Sean Cross <[email protected]>");
MODULE_DESCRIPTION("Kosagi i.MX6 ES8328 ASoC machine driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:imx-audio-es8328");
| linux-master | sound/soc/fsl/imx-es8328.c |
// SPDX-License-Identifier: GPL-2.0
//
// Freescale DMA ALSA SoC PCM driver
//
// Author: Timur Tabi <[email protected]>
//
// Copyright 2007-2010 Freescale Semiconductor, Inc.
//
// This driver implements ASoC support for the Elo DMA controller, which is
// the DMA controller on Freescale 83xx, 85xx, and 86xx SOCs. In ALSA terms,
// the PCM driver is what handles the DMA buffer.
#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/gfp.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/list.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <asm/io.h>
#include "fsl_dma.h"
#include "fsl_ssi.h" /* For the offset of stx0 and srx0 */
#define DRV_NAME "fsl_dma"
/*
* The formats that the DMA controller supports, which is anything
* that is 8, 16, or 32 bits.
*/
#define FSLDMA_PCM_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
SNDRV_PCM_FMTBIT_U8 | \
SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S16_BE | \
SNDRV_PCM_FMTBIT_U16_LE | \
SNDRV_PCM_FMTBIT_U16_BE | \
SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S24_BE | \
SNDRV_PCM_FMTBIT_U24_LE | \
SNDRV_PCM_FMTBIT_U24_BE | \
SNDRV_PCM_FMTBIT_S32_LE | \
SNDRV_PCM_FMTBIT_S32_BE | \
SNDRV_PCM_FMTBIT_U32_LE | \
SNDRV_PCM_FMTBIT_U32_BE)
struct dma_object {
struct snd_soc_component_driver dai;
dma_addr_t ssi_stx_phys;
dma_addr_t ssi_srx_phys;
unsigned int ssi_fifo_depth;
struct ccsr_dma_channel __iomem *channel;
unsigned int irq;
bool assigned;
};
/*
* The number of DMA links to use. Two is the bare minimum, but if you
* have really small links you might need more.
*/
#define NUM_DMA_LINKS 2
/** fsl_dma_private: p-substream DMA data
*
* Each substream has a 1-to-1 association with a DMA channel.
*
* The link[] array is first because it needs to be aligned on a 32-byte
* boundary, so putting it first will ensure alignment without padding the
* structure.
*
* @link[]: array of link descriptors
* @dma_channel: pointer to the DMA channel's registers
* @irq: IRQ for this DMA channel
* @substream: pointer to the substream object, needed by the ISR
* @ssi_sxx_phys: bus address of the STX or SRX register to use
* @ld_buf_phys: physical address of the LD buffer
* @current_link: index into link[] of the link currently being processed
* @dma_buf_phys: physical address of the DMA buffer
* @dma_buf_next: physical address of the next period to process
* @dma_buf_end: physical address of the byte after the end of the DMA
* @buffer period_size: the size of a single period
* @num_periods: the number of periods in the DMA buffer
*/
struct fsl_dma_private {
struct fsl_dma_link_descriptor link[NUM_DMA_LINKS];
struct ccsr_dma_channel __iomem *dma_channel;
unsigned int irq;
struct snd_pcm_substream *substream;
dma_addr_t ssi_sxx_phys;
unsigned int ssi_fifo_depth;
dma_addr_t ld_buf_phys;
unsigned int current_link;
dma_addr_t dma_buf_phys;
dma_addr_t dma_buf_next;
dma_addr_t dma_buf_end;
size_t period_size;
unsigned int num_periods;
};
/**
* fsl_dma_hardare: define characteristics of the PCM hardware.
*
* The PCM hardware is the Freescale DMA controller. This structure defines
* the capabilities of that hardware.
*
* Since the sampling rate and data format are not controlled by the DMA
* controller, we specify no limits for those values. The only exception is
* period_bytes_min, which is set to a reasonably low value to prevent the
* DMA controller from generating too many interrupts per second.
*
* Since each link descriptor has a 32-bit byte count field, we set
* period_bytes_max to the largest 32-bit number. We also have no maximum
* number of periods.
*
* Note that we specify SNDRV_PCM_INFO_JOINT_DUPLEX here, but only because a
* limitation in the SSI driver requires the sample rates for playback and
* capture to be the same.
*/
static const struct snd_pcm_hardware fsl_dma_hardware = {
.info = SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_JOINT_DUPLEX |
SNDRV_PCM_INFO_PAUSE,
.formats = FSLDMA_PCM_FORMATS,
.period_bytes_min = 512, /* A reasonable limit */
.period_bytes_max = (u32) -1,
.periods_min = NUM_DMA_LINKS,
.periods_max = (unsigned int) -1,
.buffer_bytes_max = 128 * 1024, /* A reasonable limit */
};
/**
* fsl_dma_abort_stream: tell ALSA that the DMA transfer has aborted
*
* This function should be called by the ISR whenever the DMA controller
* halts data transfer.
*/
static void fsl_dma_abort_stream(struct snd_pcm_substream *substream)
{
snd_pcm_stop_xrun(substream);
}
/**
* fsl_dma_update_pointers - update LD pointers to point to the next period
*
* As each period is completed, this function changes the link
* descriptor pointers for that period to point to the next period.
*/
static void fsl_dma_update_pointers(struct fsl_dma_private *dma_private)
{
struct fsl_dma_link_descriptor *link =
&dma_private->link[dma_private->current_link];
/* Update our link descriptors to point to the next period. On a 36-bit
* system, we also need to update the ESAD bits. We also set (keep) the
* snoop bits. See the comments in fsl_dma_hw_params() about snooping.
*/
if (dma_private->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
link->source_addr = cpu_to_be32(dma_private->dma_buf_next);
#ifdef CONFIG_PHYS_64BIT
link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP |
upper_32_bits(dma_private->dma_buf_next));
#endif
} else {
link->dest_addr = cpu_to_be32(dma_private->dma_buf_next);
#ifdef CONFIG_PHYS_64BIT
link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP |
upper_32_bits(dma_private->dma_buf_next));
#endif
}
/* Update our variables for next time */
dma_private->dma_buf_next += dma_private->period_size;
if (dma_private->dma_buf_next >= dma_private->dma_buf_end)
dma_private->dma_buf_next = dma_private->dma_buf_phys;
if (++dma_private->current_link >= NUM_DMA_LINKS)
dma_private->current_link = 0;
}
/**
* fsl_dma_isr: interrupt handler for the DMA controller
*
* @irq: IRQ of the DMA channel
* @dev_id: pointer to the dma_private structure for this DMA channel
*/
static irqreturn_t fsl_dma_isr(int irq, void *dev_id)
{
struct fsl_dma_private *dma_private = dev_id;
struct snd_pcm_substream *substream = dma_private->substream;
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct device *dev = rtd->dev;
struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel;
irqreturn_t ret = IRQ_NONE;
u32 sr, sr2 = 0;
/* We got an interrupt, so read the status register to see what we
were interrupted for.
*/
sr = in_be32(&dma_channel->sr);
if (sr & CCSR_DMA_SR_TE) {
dev_err(dev, "dma transmit error\n");
fsl_dma_abort_stream(substream);
sr2 |= CCSR_DMA_SR_TE;
ret = IRQ_HANDLED;
}
if (sr & CCSR_DMA_SR_CH)
ret = IRQ_HANDLED;
if (sr & CCSR_DMA_SR_PE) {
dev_err(dev, "dma programming error\n");
fsl_dma_abort_stream(substream);
sr2 |= CCSR_DMA_SR_PE;
ret = IRQ_HANDLED;
}
if (sr & CCSR_DMA_SR_EOLNI) {
sr2 |= CCSR_DMA_SR_EOLNI;
ret = IRQ_HANDLED;
}
if (sr & CCSR_DMA_SR_CB)
ret = IRQ_HANDLED;
if (sr & CCSR_DMA_SR_EOSI) {
/* Tell ALSA we completed a period. */
snd_pcm_period_elapsed(substream);
/*
* Update our link descriptors to point to the next period. We
* only need to do this if the number of periods is not equal to
* the number of links.
*/
if (dma_private->num_periods != NUM_DMA_LINKS)
fsl_dma_update_pointers(dma_private);
sr2 |= CCSR_DMA_SR_EOSI;
ret = IRQ_HANDLED;
}
if (sr & CCSR_DMA_SR_EOLSI) {
sr2 |= CCSR_DMA_SR_EOLSI;
ret = IRQ_HANDLED;
}
/* Clear the bits that we set */
if (sr2)
out_be32(&dma_channel->sr, sr2);
return ret;
}
/**
* fsl_dma_new: initialize this PCM driver.
*
* This function is called when the codec driver calls snd_soc_new_pcms(),
* once for each .dai_link in the machine driver's snd_soc_card
* structure.
*
* snd_dma_alloc_pages() is just a front-end to dma_alloc_coherent(), which
* (currently) always allocates the DMA buffer in lowmem, even if GFP_HIGHMEM
* is specified. Therefore, any DMA buffers we allocate will always be in low
* memory, but we support for 36-bit physical addresses anyway.
*
* Regardless of where the memory is actually allocated, since the device can
* technically DMA to any 36-bit address, we do need to set the DMA mask to 36.
*/
static int fsl_dma_new(struct snd_soc_component *component,
struct snd_soc_pcm_runtime *rtd)
{
struct snd_card *card = rtd->card->snd_card;
struct snd_pcm *pcm = rtd->pcm;
int ret;
ret = dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(36));
if (ret)
return ret;
return snd_pcm_set_fixed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
card->dev,
fsl_dma_hardware.buffer_bytes_max);
}
/**
* fsl_dma_open: open a new substream.
*
* Each substream has its own DMA buffer.
*
* ALSA divides the DMA buffer into N periods. We create NUM_DMA_LINKS link
* descriptors that ping-pong from one period to the next. For example, if
* there are six periods and two link descriptors, this is how they look
* before playback starts:
*
* The last link descriptor
* ____________ points back to the first
* | |
* V |
* ___ ___ |
* | |->| |->|
* |___| |___|
* | |
* | |
* V V
* _________________________________________
* | | | | | | | The DMA buffer is
* | | | | | | | divided into 6 parts
* |______|______|______|______|______|______|
*
* and here's how they look after the first period is finished playing:
*
* ____________
* | |
* V |
* ___ ___ |
* | |->| |->|
* |___| |___|
* | |
* |______________
* | |
* V V
* _________________________________________
* | | | | | | |
* | | | | | | |
* |______|______|______|______|______|______|
*
* The first link descriptor now points to the third period. The DMA
* controller is currently playing the second period. When it finishes, it
* will jump back to the first descriptor and play the third period.
*
* There are four reasons we do this:
*
* 1. The only way to get the DMA controller to automatically restart the
* transfer when it gets to the end of the buffer is to use chaining
* mode. Basic direct mode doesn't offer that feature.
* 2. We need to receive an interrupt at the end of every period. The DMA
* controller can generate an interrupt at the end of every link transfer
* (aka segment). Making each period into a DMA segment will give us the
* interrupts we need.
* 3. By creating only two link descriptors, regardless of the number of
* periods, we do not need to reallocate the link descriptors if the
* number of periods changes.
* 4. All of the audio data is still stored in a single, contiguous DMA
* buffer, which is what ALSA expects. We're just dividing it into
* contiguous parts, and creating a link descriptor for each one.
*/
static int fsl_dma_open(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct device *dev = component->dev;
struct dma_object *dma =
container_of(component->driver, struct dma_object, dai);
struct fsl_dma_private *dma_private;
struct ccsr_dma_channel __iomem *dma_channel;
dma_addr_t ld_buf_phys;
u64 temp_link; /* Pointer to next link descriptor */
u32 mr;
int ret = 0;
unsigned int i;
/*
* Reject any DMA buffer whose size is not a multiple of the period
* size. We need to make sure that the DMA buffer can be evenly divided
* into periods.
*/
ret = snd_pcm_hw_constraint_integer(runtime,
SNDRV_PCM_HW_PARAM_PERIODS);
if (ret < 0) {
dev_err(dev, "invalid buffer size\n");
return ret;
}
if (dma->assigned) {
dev_err(dev, "dma channel already assigned\n");
return -EBUSY;
}
dma_private = dma_alloc_coherent(dev, sizeof(struct fsl_dma_private),
&ld_buf_phys, GFP_KERNEL);
if (!dma_private) {
dev_err(dev, "can't allocate dma private data\n");
return -ENOMEM;
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
dma_private->ssi_sxx_phys = dma->ssi_stx_phys;
else
dma_private->ssi_sxx_phys = dma->ssi_srx_phys;
dma_private->ssi_fifo_depth = dma->ssi_fifo_depth;
dma_private->dma_channel = dma->channel;
dma_private->irq = dma->irq;
dma_private->substream = substream;
dma_private->ld_buf_phys = ld_buf_phys;
dma_private->dma_buf_phys = substream->dma_buffer.addr;
ret = request_irq(dma_private->irq, fsl_dma_isr, 0, "fsldma-audio",
dma_private);
if (ret) {
dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n",
dma_private->irq, ret);
dma_free_coherent(dev, sizeof(struct fsl_dma_private),
dma_private, dma_private->ld_buf_phys);
return ret;
}
dma->assigned = true;
snd_soc_set_runtime_hwparams(substream, &fsl_dma_hardware);
runtime->private_data = dma_private;
/* Program the fixed DMA controller parameters */
dma_channel = dma_private->dma_channel;
temp_link = dma_private->ld_buf_phys +
sizeof(struct fsl_dma_link_descriptor);
for (i = 0; i < NUM_DMA_LINKS; i++) {
dma_private->link[i].next = cpu_to_be64(temp_link);
temp_link += sizeof(struct fsl_dma_link_descriptor);
}
/* The last link descriptor points to the first */
dma_private->link[i - 1].next = cpu_to_be64(dma_private->ld_buf_phys);
/* Tell the DMA controller where the first link descriptor is */
out_be32(&dma_channel->clndar,
CCSR_DMA_CLNDAR_ADDR(dma_private->ld_buf_phys));
out_be32(&dma_channel->eclndar,
CCSR_DMA_ECLNDAR_ADDR(dma_private->ld_buf_phys));
/* The manual says the BCR must be clear before enabling EMP */
out_be32(&dma_channel->bcr, 0);
/*
* Program the mode register for interrupts, external master control,
* and source/destination hold. Also clear the Channel Abort bit.
*/
mr = in_be32(&dma_channel->mr) &
~(CCSR_DMA_MR_CA | CCSR_DMA_MR_DAHE | CCSR_DMA_MR_SAHE);
/*
* We want External Master Start and External Master Pause enabled,
* because the SSI is controlling the DMA controller. We want the DMA
* controller to be set up in advance, and then we signal only the SSI
* to start transferring.
*
* We want End-Of-Segment Interrupts enabled, because this will generate
* an interrupt at the end of each segment (each link descriptor
* represents one segment). Each DMA segment is the same thing as an
* ALSA period, so this is how we get an interrupt at the end of every
* period.
*
* We want Error Interrupt enabled, so that we can get an error if
* the DMA controller is mis-programmed somehow.
*/
mr |= CCSR_DMA_MR_EOSIE | CCSR_DMA_MR_EIE | CCSR_DMA_MR_EMP_EN |
CCSR_DMA_MR_EMS_EN;
/* For playback, we want the destination address to be held. For
capture, set the source address to be held. */
mr |= (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
CCSR_DMA_MR_DAHE : CCSR_DMA_MR_SAHE;
out_be32(&dma_channel->mr, mr);
return 0;
}
/**
* fsl_dma_hw_params: continue initializing the DMA links
*
* This function obtains hardware parameters about the opened stream and
* programs the DMA controller accordingly.
*
* One drawback of big-endian is that when copying integers of different
* sizes to a fixed-sized register, the address to which the integer must be
* copied is dependent on the size of the integer.
*
* For example, if P is the address of a 32-bit register, and X is a 32-bit
* integer, then X should be copied to address P. However, if X is a 16-bit
* integer, then it should be copied to P+2. If X is an 8-bit register,
* then it should be copied to P+3.
*
* So for playback of 8-bit samples, the DMA controller must transfer single
* bytes from the DMA buffer to the last byte of the STX0 register, i.e.
* offset by 3 bytes. For 16-bit samples, the offset is two bytes.
*
* For 24-bit samples, the offset is 1 byte. However, the DMA controller
* does not support 3-byte copies (the DAHTS register supports only 1, 2, 4,
* and 8 bytes at a time). So we do not support packed 24-bit samples.
* 24-bit data must be padded to 32 bits.
*/
static int fsl_dma_hw_params(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *hw_params)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct fsl_dma_private *dma_private = runtime->private_data;
struct device *dev = component->dev;
/* Number of bits per sample */
unsigned int sample_bits =
snd_pcm_format_physical_width(params_format(hw_params));
/* Number of bytes per frame */
unsigned int sample_bytes = sample_bits / 8;
/* Bus address of SSI STX register */
dma_addr_t ssi_sxx_phys = dma_private->ssi_sxx_phys;
/* Size of the DMA buffer, in bytes */
size_t buffer_size = params_buffer_bytes(hw_params);
/* Number of bytes per period */
size_t period_size = params_period_bytes(hw_params);
/* Pointer to next period */
dma_addr_t temp_addr = substream->dma_buffer.addr;
/* Pointer to DMA controller */
struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel;
u32 mr; /* DMA Mode Register */
unsigned int i;
/* Initialize our DMA tracking variables */
dma_private->period_size = period_size;
dma_private->num_periods = params_periods(hw_params);
dma_private->dma_buf_end = dma_private->dma_buf_phys + buffer_size;
dma_private->dma_buf_next = dma_private->dma_buf_phys +
(NUM_DMA_LINKS * period_size);
if (dma_private->dma_buf_next >= dma_private->dma_buf_end)
/* This happens if the number of periods == NUM_DMA_LINKS */
dma_private->dma_buf_next = dma_private->dma_buf_phys;
mr = in_be32(&dma_channel->mr) & ~(CCSR_DMA_MR_BWC_MASK |
CCSR_DMA_MR_SAHTS_MASK | CCSR_DMA_MR_DAHTS_MASK);
/* Due to a quirk of the SSI's STX register, the target address
* for the DMA operations depends on the sample size. So we calculate
* that offset here. While we're at it, also tell the DMA controller
* how much data to transfer per sample.
*/
switch (sample_bits) {
case 8:
mr |= CCSR_DMA_MR_DAHTS_1 | CCSR_DMA_MR_SAHTS_1;
ssi_sxx_phys += 3;
break;
case 16:
mr |= CCSR_DMA_MR_DAHTS_2 | CCSR_DMA_MR_SAHTS_2;
ssi_sxx_phys += 2;
break;
case 32:
mr |= CCSR_DMA_MR_DAHTS_4 | CCSR_DMA_MR_SAHTS_4;
break;
default:
/* We should never get here */
dev_err(dev, "unsupported sample size %u\n", sample_bits);
return -EINVAL;
}
/*
* BWC determines how many bytes are sent/received before the DMA
* controller checks the SSI to see if it needs to stop. BWC should
* always be a multiple of the frame size, so that we always transmit
* whole frames. Each frame occupies two slots in the FIFO. The
* parameter for CCSR_DMA_MR_BWC() is rounded down the next power of two
* (MR[BWC] can only represent even powers of two).
*
* To simplify the process, we set BWC to the largest value that is
* less than or equal to the FIFO watermark. For playback, this ensures
* that we transfer the maximum amount without overrunning the FIFO.
* For capture, this ensures that we transfer the maximum amount without
* underrunning the FIFO.
*
* f = SSI FIFO depth
* w = SSI watermark value (which equals f - 2)
* b = DMA bandwidth count (in bytes)
* s = sample size (in bytes, which equals frame_size * 2)
*
* For playback, we never transmit more than the transmit FIFO
* watermark, otherwise we might write more data than the FIFO can hold.
* The watermark is equal to the FIFO depth minus two.
*
* For capture, two equations must hold:
* w > f - (b / s)
* w >= b / s
*
* So, b > 2 * s, but b must also be <= s * w. To simplify, we set
* b = s * w, which is equal to
* (dma_private->ssi_fifo_depth - 2) * sample_bytes.
*/
mr |= CCSR_DMA_MR_BWC((dma_private->ssi_fifo_depth - 2) * sample_bytes);
out_be32(&dma_channel->mr, mr);
for (i = 0; i < NUM_DMA_LINKS; i++) {
struct fsl_dma_link_descriptor *link = &dma_private->link[i];
link->count = cpu_to_be32(period_size);
/* The snoop bit tells the DMA controller whether it should tell
* the ECM to snoop during a read or write to an address. For
* audio, we use DMA to transfer data between memory and an I/O
* device (the SSI's STX0 or SRX0 register). Snooping is only
* needed if there is a cache, so we need to snoop memory
* addresses only. For playback, that means we snoop the source
* but not the destination. For capture, we snoop the
* destination but not the source.
*
* Note that failing to snoop properly is unlikely to cause
* cache incoherency if the period size is larger than the
* size of L1 cache. This is because filling in one period will
* flush out the data for the previous period. So if you
* increased period_bytes_min to a large enough size, you might
* get more performance by not snooping, and you'll still be
* okay. You'll need to update fsl_dma_update_pointers() also.
*/
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
link->source_addr = cpu_to_be32(temp_addr);
link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP |
upper_32_bits(temp_addr));
link->dest_addr = cpu_to_be32(ssi_sxx_phys);
link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP |
upper_32_bits(ssi_sxx_phys));
} else {
link->source_addr = cpu_to_be32(ssi_sxx_phys);
link->source_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP |
upper_32_bits(ssi_sxx_phys));
link->dest_addr = cpu_to_be32(temp_addr);
link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP |
upper_32_bits(temp_addr));
}
temp_addr += period_size;
}
return 0;
}
/**
* fsl_dma_pointer: determine the current position of the DMA transfer
*
* This function is called by ALSA when ALSA wants to know where in the
* stream buffer the hardware currently is.
*
* For playback, the SAR register contains the physical address of the most
* recent DMA transfer. For capture, the value is in the DAR register.
*
* The base address of the buffer is stored in the source_addr field of the
* first link descriptor.
*/
static snd_pcm_uframes_t fsl_dma_pointer(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct fsl_dma_private *dma_private = runtime->private_data;
struct device *dev = component->dev;
struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel;
dma_addr_t position;
snd_pcm_uframes_t frames;
/* Obtain the current DMA pointer, but don't read the ESAD bits if we
* only have 32-bit DMA addresses. This function is typically called
* in interrupt context, so we need to optimize it.
*/
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
position = in_be32(&dma_channel->sar);
#ifdef CONFIG_PHYS_64BIT
position |= (u64)(in_be32(&dma_channel->satr) &
CCSR_DMA_ATR_ESAD_MASK) << 32;
#endif
} else {
position = in_be32(&dma_channel->dar);
#ifdef CONFIG_PHYS_64BIT
position |= (u64)(in_be32(&dma_channel->datr) &
CCSR_DMA_ATR_ESAD_MASK) << 32;
#endif
}
/*
* When capture is started, the SSI immediately starts to fill its FIFO.
* This means that the DMA controller is not started until the FIFO is
* full. However, ALSA calls this function before that happens, when
* MR.DAR is still zero. In this case, just return zero to indicate
* that nothing has been received yet.
*/
if (!position)
return 0;
if ((position < dma_private->dma_buf_phys) ||
(position > dma_private->dma_buf_end)) {
dev_err(dev, "dma pointer is out of range, halting stream\n");
return SNDRV_PCM_POS_XRUN;
}
frames = bytes_to_frames(runtime, position - dma_private->dma_buf_phys);
/*
* If the current address is just past the end of the buffer, wrap it
* around.
*/
if (frames == runtime->buffer_size)
frames = 0;
return frames;
}
/**
* fsl_dma_hw_free: release resources allocated in fsl_dma_hw_params()
*
* Release the resources allocated in fsl_dma_hw_params() and de-program the
* registers.
*
* This function can be called multiple times.
*/
static int fsl_dma_hw_free(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct fsl_dma_private *dma_private = runtime->private_data;
if (dma_private) {
struct ccsr_dma_channel __iomem *dma_channel;
dma_channel = dma_private->dma_channel;
/* Stop the DMA */
out_be32(&dma_channel->mr, CCSR_DMA_MR_CA);
out_be32(&dma_channel->mr, 0);
/* Reset all the other registers */
out_be32(&dma_channel->sr, -1);
out_be32(&dma_channel->clndar, 0);
out_be32(&dma_channel->eclndar, 0);
out_be32(&dma_channel->satr, 0);
out_be32(&dma_channel->sar, 0);
out_be32(&dma_channel->datr, 0);
out_be32(&dma_channel->dar, 0);
out_be32(&dma_channel->bcr, 0);
out_be32(&dma_channel->nlndar, 0);
out_be32(&dma_channel->enlndar, 0);
}
return 0;
}
/**
* fsl_dma_close: close the stream.
*/
static int fsl_dma_close(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct fsl_dma_private *dma_private = runtime->private_data;
struct device *dev = component->dev;
struct dma_object *dma =
container_of(component->driver, struct dma_object, dai);
if (dma_private) {
if (dma_private->irq)
free_irq(dma_private->irq, dma_private);
/* Deallocate the fsl_dma_private structure */
dma_free_coherent(dev, sizeof(struct fsl_dma_private),
dma_private, dma_private->ld_buf_phys);
substream->runtime->private_data = NULL;
}
dma->assigned = false;
return 0;
}
/**
* find_ssi_node -- returns the SSI node that points to its DMA channel node
*
* Although this DMA driver attempts to operate independently of the other
* devices, it still needs to determine some information about the SSI device
* that it's working with. Unfortunately, the device tree does not contain
* a pointer from the DMA channel node to the SSI node -- the pointer goes the
* other way. So we need to scan the device tree for SSI nodes until we find
* the one that points to the given DMA channel node. It's ugly, but at least
* it's contained in this one function.
*/
static struct device_node *find_ssi_node(struct device_node *dma_channel_np)
{
struct device_node *ssi_np, *np;
for_each_compatible_node(ssi_np, NULL, "fsl,mpc8610-ssi") {
/* Check each DMA phandle to see if it points to us. We
* assume that device_node pointers are a valid comparison.
*/
np = of_parse_phandle(ssi_np, "fsl,playback-dma", 0);
of_node_put(np);
if (np == dma_channel_np)
return ssi_np;
np = of_parse_phandle(ssi_np, "fsl,capture-dma", 0);
of_node_put(np);
if (np == dma_channel_np)
return ssi_np;
}
return NULL;
}
static int fsl_soc_dma_probe(struct platform_device *pdev)
{
struct dma_object *dma;
struct device_node *np = pdev->dev.of_node;
struct device_node *ssi_np;
struct resource res;
const uint32_t *iprop;
int ret;
/* Find the SSI node that points to us. */
ssi_np = find_ssi_node(np);
if (!ssi_np) {
dev_err(&pdev->dev, "cannot find parent SSI node\n");
return -ENODEV;
}
ret = of_address_to_resource(ssi_np, 0, &res);
if (ret) {
dev_err(&pdev->dev, "could not determine resources for %pOF\n",
ssi_np);
of_node_put(ssi_np);
return ret;
}
dma = kzalloc(sizeof(*dma), GFP_KERNEL);
if (!dma) {
of_node_put(ssi_np);
return -ENOMEM;
}
dma->dai.name = DRV_NAME;
dma->dai.open = fsl_dma_open;
dma->dai.close = fsl_dma_close;
dma->dai.hw_params = fsl_dma_hw_params;
dma->dai.hw_free = fsl_dma_hw_free;
dma->dai.pointer = fsl_dma_pointer;
dma->dai.pcm_construct = fsl_dma_new;
/* Store the SSI-specific information that we need */
dma->ssi_stx_phys = res.start + REG_SSI_STX0;
dma->ssi_srx_phys = res.start + REG_SSI_SRX0;
iprop = of_get_property(ssi_np, "fsl,fifo-depth", NULL);
if (iprop)
dma->ssi_fifo_depth = be32_to_cpup(iprop);
else
/* Older 8610 DTs didn't have the fifo-depth property */
dma->ssi_fifo_depth = 8;
of_node_put(ssi_np);
ret = devm_snd_soc_register_component(&pdev->dev, &dma->dai, NULL, 0);
if (ret) {
dev_err(&pdev->dev, "could not register platform\n");
kfree(dma);
return ret;
}
dma->channel = of_iomap(np, 0);
dma->irq = irq_of_parse_and_map(np, 0);
dev_set_drvdata(&pdev->dev, dma);
return 0;
}
static void fsl_soc_dma_remove(struct platform_device *pdev)
{
struct dma_object *dma = dev_get_drvdata(&pdev->dev);
iounmap(dma->channel);
irq_dispose_mapping(dma->irq);
kfree(dma);
}
static const struct of_device_id fsl_soc_dma_ids[] = {
{ .compatible = "fsl,ssi-dma-channel", },
{}
};
MODULE_DEVICE_TABLE(of, fsl_soc_dma_ids);
static struct platform_driver fsl_soc_dma_driver = {
.driver = {
.name = "fsl-pcm-audio",
.of_match_table = fsl_soc_dma_ids,
},
.probe = fsl_soc_dma_probe,
.remove_new = fsl_soc_dma_remove,
};
module_platform_driver(fsl_soc_dma_driver);
MODULE_AUTHOR("Timur Tabi <[email protected]>");
MODULE_DESCRIPTION("Freescale Elo DMA ASoC PCM Driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/fsl/fsl_dma.c |
// SPDX-License-Identifier: GPL-2.0
/*
* NXP AUDMIX ALSA SoC Digital Audio Interface (DAI) driver
*
* Copyright 2017 NXP
*/
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/pm_runtime.h>
#include <sound/soc.h>
#include <sound/pcm_params.h>
#include "fsl_audmix.h"
#define SOC_ENUM_SINGLE_S(xreg, xshift, xtexts) \
SOC_ENUM_SINGLE(xreg, xshift, ARRAY_SIZE(xtexts), xtexts)
static const char
*tdm_sel[] = { "TDM1", "TDM2", },
*mode_sel[] = { "Disabled", "TDM1", "TDM2", "Mixed", },
*width_sel[] = { "16b", "18b", "20b", "24b", "32b", },
*endis_sel[] = { "Disabled", "Enabled", },
*updn_sel[] = { "Downward", "Upward", },
*mask_sel[] = { "Unmask", "Mask", };
static const struct soc_enum fsl_audmix_enum[] = {
/* FSL_AUDMIX_CTR enums */
SOC_ENUM_SINGLE_S(FSL_AUDMIX_CTR, FSL_AUDMIX_CTR_MIXCLK_SHIFT, tdm_sel),
SOC_ENUM_SINGLE_S(FSL_AUDMIX_CTR, FSL_AUDMIX_CTR_OUTSRC_SHIFT, mode_sel),
SOC_ENUM_SINGLE_S(FSL_AUDMIX_CTR, FSL_AUDMIX_CTR_OUTWIDTH_SHIFT, width_sel),
SOC_ENUM_SINGLE_S(FSL_AUDMIX_CTR, FSL_AUDMIX_CTR_MASKRTDF_SHIFT, mask_sel),
SOC_ENUM_SINGLE_S(FSL_AUDMIX_CTR, FSL_AUDMIX_CTR_MASKCKDF_SHIFT, mask_sel),
SOC_ENUM_SINGLE_S(FSL_AUDMIX_CTR, FSL_AUDMIX_CTR_SYNCMODE_SHIFT, endis_sel),
SOC_ENUM_SINGLE_S(FSL_AUDMIX_CTR, FSL_AUDMIX_CTR_SYNCSRC_SHIFT, tdm_sel),
/* FSL_AUDMIX_ATCR0 enums */
SOC_ENUM_SINGLE_S(FSL_AUDMIX_ATCR0, 0, endis_sel),
SOC_ENUM_SINGLE_S(FSL_AUDMIX_ATCR0, 1, updn_sel),
/* FSL_AUDMIX_ATCR1 enums */
SOC_ENUM_SINGLE_S(FSL_AUDMIX_ATCR1, 0, endis_sel),
SOC_ENUM_SINGLE_S(FSL_AUDMIX_ATCR1, 1, updn_sel),
};
struct fsl_audmix_state {
u8 tdms;
u8 clk;
char msg[64];
};
static const struct fsl_audmix_state prms[4][4] = {{
/* DIS->DIS, do nothing */
{ .tdms = 0, .clk = 0, .msg = "" },
/* DIS->TDM1*/
{ .tdms = 1, .clk = 1, .msg = "DIS->TDM1: TDM1 not started!\n" },
/* DIS->TDM2*/
{ .tdms = 2, .clk = 2, .msg = "DIS->TDM2: TDM2 not started!\n" },
/* DIS->MIX */
{ .tdms = 3, .clk = 0, .msg = "DIS->MIX: Please start both TDMs!\n" }
}, { /* TDM1->DIS */
{ .tdms = 1, .clk = 0, .msg = "TDM1->DIS: TDM1 not started!\n" },
/* TDM1->TDM1, do nothing */
{ .tdms = 0, .clk = 0, .msg = "" },
/* TDM1->TDM2 */
{ .tdms = 3, .clk = 2, .msg = "TDM1->TDM2: Please start both TDMs!\n" },
/* TDM1->MIX */
{ .tdms = 3, .clk = 0, .msg = "TDM1->MIX: Please start both TDMs!\n" }
}, { /* TDM2->DIS */
{ .tdms = 2, .clk = 0, .msg = "TDM2->DIS: TDM2 not started!\n" },
/* TDM2->TDM1 */
{ .tdms = 3, .clk = 1, .msg = "TDM2->TDM1: Please start both TDMs!\n" },
/* TDM2->TDM2, do nothing */
{ .tdms = 0, .clk = 0, .msg = "" },
/* TDM2->MIX */
{ .tdms = 3, .clk = 0, .msg = "TDM2->MIX: Please start both TDMs!\n" }
}, { /* MIX->DIS */
{ .tdms = 3, .clk = 0, .msg = "MIX->DIS: Please start both TDMs!\n" },
/* MIX->TDM1 */
{ .tdms = 3, .clk = 1, .msg = "MIX->TDM1: Please start both TDMs!\n" },
/* MIX->TDM2 */
{ .tdms = 3, .clk = 2, .msg = "MIX->TDM2: Please start both TDMs!\n" },
/* MIX->MIX, do nothing */
{ .tdms = 0, .clk = 0, .msg = "" }
}, };
static int fsl_audmix_state_trans(struct snd_soc_component *comp,
unsigned int *mask, unsigned int *ctr,
const struct fsl_audmix_state prm)
{
struct fsl_audmix *priv = snd_soc_component_get_drvdata(comp);
/* Enforce all required TDMs are started */
if ((priv->tdms & prm.tdms) != prm.tdms) {
dev_dbg(comp->dev, "%s", prm.msg);
return -EINVAL;
}
switch (prm.clk) {
case 1:
case 2:
/* Set mix clock */
(*mask) |= FSL_AUDMIX_CTR_MIXCLK_MASK;
(*ctr) |= FSL_AUDMIX_CTR_MIXCLK(prm.clk - 1);
break;
default:
break;
}
return 0;
}
static int fsl_audmix_put_mix_clk_src(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
struct fsl_audmix *priv = snd_soc_component_get_drvdata(comp);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned int *item = ucontrol->value.enumerated.item;
unsigned int reg_val, val, mix_clk;
/* Get current state */
reg_val = snd_soc_component_read(comp, FSL_AUDMIX_CTR);
mix_clk = ((reg_val & FSL_AUDMIX_CTR_MIXCLK_MASK)
>> FSL_AUDMIX_CTR_MIXCLK_SHIFT);
val = snd_soc_enum_item_to_val(e, item[0]);
dev_dbg(comp->dev, "TDMs=x%08x, val=x%08x\n", priv->tdms, val);
/**
* Ensure the current selected mixer clock is available
* for configuration propagation
*/
if (!(priv->tdms & BIT(mix_clk))) {
dev_err(comp->dev,
"Started TDM%d needed for config propagation!\n",
mix_clk + 1);
return -EINVAL;
}
if (!(priv->tdms & BIT(val))) {
dev_err(comp->dev,
"The selected clock source has no TDM%d enabled!\n",
val + 1);
return -EINVAL;
}
return snd_soc_put_enum_double(kcontrol, ucontrol);
}
static int fsl_audmix_put_out_src(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
struct fsl_audmix *priv = snd_soc_component_get_drvdata(comp);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned int *item = ucontrol->value.enumerated.item;
u32 out_src, mix_clk;
unsigned int reg_val, val, mask = 0, ctr = 0;
int ret;
/* Get current state */
reg_val = snd_soc_component_read(comp, FSL_AUDMIX_CTR);
/* "From" state */
out_src = ((reg_val & FSL_AUDMIX_CTR_OUTSRC_MASK)
>> FSL_AUDMIX_CTR_OUTSRC_SHIFT);
mix_clk = ((reg_val & FSL_AUDMIX_CTR_MIXCLK_MASK)
>> FSL_AUDMIX_CTR_MIXCLK_SHIFT);
/* "To" state */
val = snd_soc_enum_item_to_val(e, item[0]);
dev_dbg(comp->dev, "TDMs=x%08x, val=x%08x\n", priv->tdms, val);
/* Check if state is changing ... */
if (out_src == val)
return 0;
/**
* Ensure the current selected mixer clock is available
* for configuration propagation
*/
if (!(priv->tdms & BIT(mix_clk))) {
dev_err(comp->dev,
"Started TDM%d needed for config propagation!\n",
mix_clk + 1);
return -EINVAL;
}
/* Check state transition constraints */
ret = fsl_audmix_state_trans(comp, &mask, &ctr, prms[out_src][val]);
if (ret)
return ret;
/* Complete transition to new state */
mask |= FSL_AUDMIX_CTR_OUTSRC_MASK;
ctr |= FSL_AUDMIX_CTR_OUTSRC(val);
return snd_soc_component_update_bits(comp, FSL_AUDMIX_CTR, mask, ctr);
}
static const struct snd_kcontrol_new fsl_audmix_snd_controls[] = {
/* FSL_AUDMIX_CTR controls */
SOC_ENUM_EXT("Mixing Clock Source", fsl_audmix_enum[0],
snd_soc_get_enum_double, fsl_audmix_put_mix_clk_src),
SOC_ENUM_EXT("Output Source", fsl_audmix_enum[1],
snd_soc_get_enum_double, fsl_audmix_put_out_src),
SOC_ENUM("Output Width", fsl_audmix_enum[2]),
SOC_ENUM("Frame Rate Diff Error", fsl_audmix_enum[3]),
SOC_ENUM("Clock Freq Diff Error", fsl_audmix_enum[4]),
SOC_ENUM("Sync Mode Config", fsl_audmix_enum[5]),
SOC_ENUM("Sync Mode Clk Source", fsl_audmix_enum[6]),
/* TDM1 Attenuation controls */
SOC_ENUM("TDM1 Attenuation", fsl_audmix_enum[7]),
SOC_ENUM("TDM1 Attenuation Direction", fsl_audmix_enum[8]),
SOC_SINGLE("TDM1 Attenuation Step Divider", FSL_AUDMIX_ATCR0,
2, 0x00fff, 0),
SOC_SINGLE("TDM1 Attenuation Initial Value", FSL_AUDMIX_ATIVAL0,
0, 0x3ffff, 0),
SOC_SINGLE("TDM1 Attenuation Step Up Factor", FSL_AUDMIX_ATSTPUP0,
0, 0x3ffff, 0),
SOC_SINGLE("TDM1 Attenuation Step Down Factor", FSL_AUDMIX_ATSTPDN0,
0, 0x3ffff, 0),
SOC_SINGLE("TDM1 Attenuation Step Target", FSL_AUDMIX_ATSTPTGT0,
0, 0x3ffff, 0),
/* TDM2 Attenuation controls */
SOC_ENUM("TDM2 Attenuation", fsl_audmix_enum[9]),
SOC_ENUM("TDM2 Attenuation Direction", fsl_audmix_enum[10]),
SOC_SINGLE("TDM2 Attenuation Step Divider", FSL_AUDMIX_ATCR1,
2, 0x00fff, 0),
SOC_SINGLE("TDM2 Attenuation Initial Value", FSL_AUDMIX_ATIVAL1,
0, 0x3ffff, 0),
SOC_SINGLE("TDM2 Attenuation Step Up Factor", FSL_AUDMIX_ATSTPUP1,
0, 0x3ffff, 0),
SOC_SINGLE("TDM2 Attenuation Step Down Factor", FSL_AUDMIX_ATSTPDN1,
0, 0x3ffff, 0),
SOC_SINGLE("TDM2 Attenuation Step Target", FSL_AUDMIX_ATSTPTGT1,
0, 0x3ffff, 0),
};
static int fsl_audmix_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *comp = dai->component;
u32 mask = 0, ctr = 0;
/* AUDMIX is working in DSP_A format only */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
break;
default:
return -EINVAL;
}
/* For playback the AUDMIX is consumer, and for record is provider */
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BC_FC:
case SND_SOC_DAIFMT_BP_FP:
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_IB_NF:
/* Output data will be written on positive edge of the clock */
ctr |= FSL_AUDMIX_CTR_OUTCKPOL(0);
break;
case SND_SOC_DAIFMT_NB_NF:
/* Output data will be written on negative edge of the clock */
ctr |= FSL_AUDMIX_CTR_OUTCKPOL(1);
break;
default:
return -EINVAL;
}
mask |= FSL_AUDMIX_CTR_OUTCKPOL_MASK;
return snd_soc_component_update_bits(comp, FSL_AUDMIX_CTR, mask, ctr);
}
static int fsl_audmix_dai_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct fsl_audmix *priv = snd_soc_dai_get_drvdata(dai);
unsigned long lock_flags;
/* Capture stream shall not be handled */
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
return 0;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
spin_lock_irqsave(&priv->lock, lock_flags);
priv->tdms |= BIT(dai->driver->id);
spin_unlock_irqrestore(&priv->lock, lock_flags);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
spin_lock_irqsave(&priv->lock, lock_flags);
priv->tdms &= ~BIT(dai->driver->id);
spin_unlock_irqrestore(&priv->lock, lock_flags);
break;
default:
return -EINVAL;
}
return 0;
}
static const struct snd_soc_dai_ops fsl_audmix_dai_ops = {
.set_fmt = fsl_audmix_dai_set_fmt,
.trigger = fsl_audmix_dai_trigger,
};
static struct snd_soc_dai_driver fsl_audmix_dai[] = {
{
.id = 0,
.name = "audmix-0",
.playback = {
.stream_name = "AUDMIX-Playback-0",
.channels_min = 8,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 96000,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = FSL_AUDMIX_FORMATS,
},
.capture = {
.stream_name = "AUDMIX-Capture-0",
.channels_min = 8,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 96000,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = FSL_AUDMIX_FORMATS,
},
.ops = &fsl_audmix_dai_ops,
},
{
.id = 1,
.name = "audmix-1",
.playback = {
.stream_name = "AUDMIX-Playback-1",
.channels_min = 8,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 96000,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = FSL_AUDMIX_FORMATS,
},
.capture = {
.stream_name = "AUDMIX-Capture-1",
.channels_min = 8,
.channels_max = 8,
.rate_min = 8000,
.rate_max = 96000,
.rates = SNDRV_PCM_RATE_8000_96000,
.formats = FSL_AUDMIX_FORMATS,
},
.ops = &fsl_audmix_dai_ops,
},
};
static const struct snd_soc_component_driver fsl_audmix_component = {
.name = "fsl-audmix-dai",
.controls = fsl_audmix_snd_controls,
.num_controls = ARRAY_SIZE(fsl_audmix_snd_controls),
};
static bool fsl_audmix_readable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case FSL_AUDMIX_CTR:
case FSL_AUDMIX_STR:
case FSL_AUDMIX_ATCR0:
case FSL_AUDMIX_ATIVAL0:
case FSL_AUDMIX_ATSTPUP0:
case FSL_AUDMIX_ATSTPDN0:
case FSL_AUDMIX_ATSTPTGT0:
case FSL_AUDMIX_ATTNVAL0:
case FSL_AUDMIX_ATSTP0:
case FSL_AUDMIX_ATCR1:
case FSL_AUDMIX_ATIVAL1:
case FSL_AUDMIX_ATSTPUP1:
case FSL_AUDMIX_ATSTPDN1:
case FSL_AUDMIX_ATSTPTGT1:
case FSL_AUDMIX_ATTNVAL1:
case FSL_AUDMIX_ATSTP1:
return true;
default:
return false;
}
}
static bool fsl_audmix_writeable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case FSL_AUDMIX_CTR:
case FSL_AUDMIX_ATCR0:
case FSL_AUDMIX_ATIVAL0:
case FSL_AUDMIX_ATSTPUP0:
case FSL_AUDMIX_ATSTPDN0:
case FSL_AUDMIX_ATSTPTGT0:
case FSL_AUDMIX_ATCR1:
case FSL_AUDMIX_ATIVAL1:
case FSL_AUDMIX_ATSTPUP1:
case FSL_AUDMIX_ATSTPDN1:
case FSL_AUDMIX_ATSTPTGT1:
return true;
default:
return false;
}
}
static const struct reg_default fsl_audmix_reg[] = {
{ FSL_AUDMIX_CTR, 0x00060 },
{ FSL_AUDMIX_STR, 0x00003 },
{ FSL_AUDMIX_ATCR0, 0x00000 },
{ FSL_AUDMIX_ATIVAL0, 0x3FFFF },
{ FSL_AUDMIX_ATSTPUP0, 0x2AAAA },
{ FSL_AUDMIX_ATSTPDN0, 0x30000 },
{ FSL_AUDMIX_ATSTPTGT0, 0x00010 },
{ FSL_AUDMIX_ATTNVAL0, 0x00000 },
{ FSL_AUDMIX_ATSTP0, 0x00000 },
{ FSL_AUDMIX_ATCR1, 0x00000 },
{ FSL_AUDMIX_ATIVAL1, 0x3FFFF },
{ FSL_AUDMIX_ATSTPUP1, 0x2AAAA },
{ FSL_AUDMIX_ATSTPDN1, 0x30000 },
{ FSL_AUDMIX_ATSTPTGT1, 0x00010 },
{ FSL_AUDMIX_ATTNVAL1, 0x00000 },
{ FSL_AUDMIX_ATSTP1, 0x00000 },
};
static const struct regmap_config fsl_audmix_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = FSL_AUDMIX_ATSTP1,
.reg_defaults = fsl_audmix_reg,
.num_reg_defaults = ARRAY_SIZE(fsl_audmix_reg),
.readable_reg = fsl_audmix_readable_reg,
.writeable_reg = fsl_audmix_writeable_reg,
.cache_type = REGCACHE_FLAT,
};
static const struct of_device_id fsl_audmix_ids[] = {
{
.compatible = "fsl,imx8qm-audmix",
},
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, fsl_audmix_ids);
static int fsl_audmix_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct fsl_audmix *priv;
void __iomem *regs;
int ret;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
/* Get the addresses */
regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(regs))
return PTR_ERR(regs);
priv->regmap = devm_regmap_init_mmio(dev, regs, &fsl_audmix_regmap_config);
if (IS_ERR(priv->regmap)) {
dev_err(dev, "failed to init regmap\n");
return PTR_ERR(priv->regmap);
}
priv->ipg_clk = devm_clk_get(dev, "ipg");
if (IS_ERR(priv->ipg_clk)) {
dev_err(dev, "failed to get ipg clock\n");
return PTR_ERR(priv->ipg_clk);
}
spin_lock_init(&priv->lock);
platform_set_drvdata(pdev, priv);
pm_runtime_enable(dev);
ret = devm_snd_soc_register_component(dev, &fsl_audmix_component,
fsl_audmix_dai,
ARRAY_SIZE(fsl_audmix_dai));
if (ret) {
dev_err(dev, "failed to register ASoC DAI\n");
goto err_disable_pm;
}
priv->pdev = platform_device_register_data(dev, "imx-audmix", 0, NULL, 0);
if (IS_ERR(priv->pdev)) {
ret = PTR_ERR(priv->pdev);
dev_err(dev, "failed to register platform: %d\n", ret);
goto err_disable_pm;
}
return 0;
err_disable_pm:
pm_runtime_disable(dev);
return ret;
}
static void fsl_audmix_remove(struct platform_device *pdev)
{
struct fsl_audmix *priv = dev_get_drvdata(&pdev->dev);
pm_runtime_disable(&pdev->dev);
if (priv->pdev)
platform_device_unregister(priv->pdev);
}
#ifdef CONFIG_PM
static int fsl_audmix_runtime_resume(struct device *dev)
{
struct fsl_audmix *priv = dev_get_drvdata(dev);
int ret;
ret = clk_prepare_enable(priv->ipg_clk);
if (ret) {
dev_err(dev, "Failed to enable IPG clock: %d\n", ret);
return ret;
}
regcache_cache_only(priv->regmap, false);
regcache_mark_dirty(priv->regmap);
return regcache_sync(priv->regmap);
}
static int fsl_audmix_runtime_suspend(struct device *dev)
{
struct fsl_audmix *priv = dev_get_drvdata(dev);
regcache_cache_only(priv->regmap, true);
clk_disable_unprepare(priv->ipg_clk);
return 0;
}
#endif /* CONFIG_PM */
static const struct dev_pm_ops fsl_audmix_pm = {
SET_RUNTIME_PM_OPS(fsl_audmix_runtime_suspend,
fsl_audmix_runtime_resume,
NULL)
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
};
static struct platform_driver fsl_audmix_driver = {
.probe = fsl_audmix_probe,
.remove_new = fsl_audmix_remove,
.driver = {
.name = "fsl-audmix",
.of_match_table = fsl_audmix_ids,
.pm = &fsl_audmix_pm,
},
};
module_platform_driver(fsl_audmix_driver);
MODULE_DESCRIPTION("NXP AUDMIX ASoC DAI driver");
MODULE_AUTHOR("Viorel Suman <[email protected]>");
MODULE_ALIAS("platform:fsl-audmix");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/fsl/fsl_audmix.c |
/*
* Efika driver for the PSC of the Freescale MPC52xx
* configured as AC97 interface
*
* Copyright 2008 Jon Smirl, Digispeaker
* Author: Jon Smirl <[email protected]>
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/of_device.h>
#include <linux/of_platform.h>
#include <linux/dma-mapping.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/initval.h>
#include <sound/soc.h>
#include "mpc5200_dma.h"
#define DRV_NAME "efika-audio-fabric"
SND_SOC_DAILINK_DEFS(analog,
DAILINK_COMP_ARRAY(COMP_CPU("mpc5200-psc-ac97.0")),
DAILINK_COMP_ARRAY(COMP_CODEC("stac9766-codec",
"stac9766-hifi-analog")),
DAILINK_COMP_ARRAY(COMP_PLATFORM("mpc5200-pcm-audio")));
SND_SOC_DAILINK_DEFS(iec958,
DAILINK_COMP_ARRAY(COMP_CPU("mpc5200-psc-ac97.1")),
DAILINK_COMP_ARRAY(COMP_CODEC("stac9766-codec",
"stac9766-hifi-IEC958")),
DAILINK_COMP_ARRAY(COMP_PLATFORM("mpc5200-pcm-audio")));
static struct snd_soc_dai_link efika_fabric_dai[] = {
{
.name = "AC97",
.stream_name = "AC97 Analog",
SND_SOC_DAILINK_REG(analog),
},
{
.name = "AC97",
.stream_name = "AC97 IEC958",
SND_SOC_DAILINK_REG(iec958),
},
};
static struct snd_soc_card card = {
.name = "Efika",
.owner = THIS_MODULE,
.dai_link = efika_fabric_dai,
.num_links = ARRAY_SIZE(efika_fabric_dai),
};
static __init int efika_fabric_init(void)
{
struct platform_device *pdev;
int rc;
if (!of_machine_is_compatible("bplan,efika"))
return -ENODEV;
pdev = platform_device_alloc("soc-audio", 1);
if (!pdev) {
pr_err("efika_fabric_init: platform_device_alloc() failed\n");
return -ENODEV;
}
platform_set_drvdata(pdev, &card);
rc = platform_device_add(pdev);
if (rc) {
pr_err("efika_fabric_init: platform_device_add() failed\n");
platform_device_put(pdev);
return -ENODEV;
}
return 0;
}
module_init(efika_fabric_init);
MODULE_AUTHOR("Jon Smirl <[email protected]>");
MODULE_DESCRIPTION(DRV_NAME ": mpc5200 Efika fabric driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/fsl/efika-audio-fabric.c |
// SPDX-License-Identifier: GPL-2.0+
//
// eukrea-tlv320.c -- SoC audio for eukrea_cpuimxXX in I2S mode
//
// Copyright 2010 Eric Bénard, Eukréa Electromatique <[email protected]>
//
// based on sound/soc/s3c24xx/s3c24xx_simtec_tlv320aic23.c
// which is Copyright 2009 Simtec Electronics
// and on sound/soc/imx/phycore-ac97.c which is
// Copyright 2009 Sascha Hauer, Pengutronix <[email protected]>
#include <linux/errno.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/device.h>
#include <linux/i2c.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/soc.h>
#include <asm/mach-types.h>
#include "../codecs/tlv320aic23.h"
#include "imx-ssi.h"
#include "imx-audmux.h"
#define CODEC_CLOCK 12000000
static int eukrea_tlv320_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
int ret;
ret = snd_soc_dai_set_sysclk(codec_dai, 0,
CODEC_CLOCK, SND_SOC_CLOCK_OUT);
if (ret) {
dev_err(cpu_dai->dev,
"Failed to set the codec sysclk.\n");
return ret;
}
snd_soc_dai_set_tdm_slot(cpu_dai, 0x3, 0x3, 2, 0);
ret = snd_soc_dai_set_sysclk(cpu_dai, IMX_SSP_SYS_CLK, 0,
SND_SOC_CLOCK_IN);
/* fsl_ssi lacks the set_sysclk ops */
if (ret && ret != -EINVAL) {
dev_err(cpu_dai->dev,
"Can't set the IMX_SSP_SYS_CLK CPU system clock.\n");
return ret;
}
return 0;
}
static const struct snd_soc_ops eukrea_tlv320_snd_ops = {
.hw_params = eukrea_tlv320_hw_params,
};
SND_SOC_DAILINK_DEFS(hifi,
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "tlv320aic23-hifi")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
static struct snd_soc_dai_link eukrea_tlv320_dai = {
.name = "tlv320aic23",
.stream_name = "TLV320AIC23",
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBP_CFP,
.ops = &eukrea_tlv320_snd_ops,
SND_SOC_DAILINK_REG(hifi),
};
static struct snd_soc_card eukrea_tlv320 = {
.owner = THIS_MODULE,
.dai_link = &eukrea_tlv320_dai,
.num_links = 1,
};
static int eukrea_tlv320_probe(struct platform_device *pdev)
{
int ret;
int int_port = 0, ext_port;
struct device_node *np = pdev->dev.of_node;
struct device_node *ssi_np = NULL, *codec_np = NULL, *tmp_np = NULL;
eukrea_tlv320.dev = &pdev->dev;
if (np) {
ret = snd_soc_of_parse_card_name(&eukrea_tlv320,
"eukrea,model");
if (ret) {
dev_err(&pdev->dev,
"eukrea,model node missing or invalid.\n");
goto err;
}
ssi_np = of_parse_phandle(pdev->dev.of_node,
"ssi-controller", 0);
if (!ssi_np) {
dev_err(&pdev->dev,
"ssi-controller missing or invalid.\n");
ret = -ENODEV;
goto err;
}
codec_np = of_parse_phandle(ssi_np, "codec-handle", 0);
if (codec_np)
eukrea_tlv320_dai.codecs->of_node = codec_np;
else
dev_err(&pdev->dev, "codec-handle node missing or invalid.\n");
ret = of_property_read_u32(np, "fsl,mux-int-port", &int_port);
if (ret) {
dev_err(&pdev->dev,
"fsl,mux-int-port node missing or invalid.\n");
goto err;
}
ret = of_property_read_u32(np, "fsl,mux-ext-port", &ext_port);
if (ret) {
dev_err(&pdev->dev,
"fsl,mux-ext-port node missing or invalid.\n");
goto err;
}
/*
* The port numbering in the hardware manual starts at 1, while
* the audmux API expects it starts at 0.
*/
int_port--;
ext_port--;
eukrea_tlv320_dai.cpus->of_node = ssi_np;
eukrea_tlv320_dai.platforms->of_node = ssi_np;
} else {
eukrea_tlv320_dai.cpus->dai_name = "imx-ssi.0";
eukrea_tlv320_dai.platforms->name = "imx-ssi.0";
eukrea_tlv320_dai.codecs->name = "tlv320aic23-codec.0-001a";
eukrea_tlv320.name = "cpuimx-audio";
}
if (machine_is_eukrea_cpuimx27() ||
(tmp_np = of_find_compatible_node(NULL, NULL, "fsl,imx21-audmux"))) {
imx_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
IMX_AUDMUX_V1_PCR_SYN |
IMX_AUDMUX_V1_PCR_TFSDIR |
IMX_AUDMUX_V1_PCR_TCLKDIR |
IMX_AUDMUX_V1_PCR_RFSDIR |
IMX_AUDMUX_V1_PCR_RCLKDIR |
IMX_AUDMUX_V1_PCR_TFCSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4) |
IMX_AUDMUX_V1_PCR_RFCSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4) |
IMX_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4)
);
imx_audmux_v1_configure_port(MX27_AUDMUX_HPCR3_SSI_PINS_4,
IMX_AUDMUX_V1_PCR_SYN |
IMX_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR1_SSI0)
);
of_node_put(tmp_np);
} else if (machine_is_eukrea_cpuimx25sd() ||
machine_is_eukrea_cpuimx35sd() ||
machine_is_eukrea_cpuimx51sd() ||
(tmp_np = of_find_compatible_node(NULL, NULL, "fsl,imx31-audmux"))) {
if (!np)
ext_port = machine_is_eukrea_cpuimx25sd() ?
4 : 3;
imx_audmux_v2_configure_port(int_port,
IMX_AUDMUX_V2_PTCR_SYN |
IMX_AUDMUX_V2_PTCR_TFSDIR |
IMX_AUDMUX_V2_PTCR_TFSEL(ext_port) |
IMX_AUDMUX_V2_PTCR_TCLKDIR |
IMX_AUDMUX_V2_PTCR_TCSEL(ext_port),
IMX_AUDMUX_V2_PDCR_RXDSEL(ext_port)
);
imx_audmux_v2_configure_port(ext_port,
IMX_AUDMUX_V2_PTCR_SYN,
IMX_AUDMUX_V2_PDCR_RXDSEL(int_port)
);
of_node_put(tmp_np);
} else {
if (np) {
/* The eukrea,asoc-tlv320 driver was explicitly
* requested (through the device tree).
*/
dev_err(&pdev->dev,
"Missing or invalid audmux DT node.\n");
return -ENODEV;
} else {
/* Return happy.
* We might run on a totally different machine.
*/
return 0;
}
}
ret = snd_soc_register_card(&eukrea_tlv320);
err:
if (ret)
dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret);
of_node_put(ssi_np);
return ret;
}
static void eukrea_tlv320_remove(struct platform_device *pdev)
{
snd_soc_unregister_card(&eukrea_tlv320);
}
static const struct of_device_id imx_tlv320_dt_ids[] = {
{ .compatible = "eukrea,asoc-tlv320"},
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx_tlv320_dt_ids);
static struct platform_driver eukrea_tlv320_driver = {
.driver = {
.name = "eukrea_tlv320",
.of_match_table = imx_tlv320_dt_ids,
},
.probe = eukrea_tlv320_probe,
.remove_new = eukrea_tlv320_remove,
};
module_platform_driver(eukrea_tlv320_driver);
MODULE_AUTHOR("Eric Bénard <[email protected]>");
MODULE_DESCRIPTION("CPUIMX ALSA SoC driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:eukrea_tlv320");
| linux-master | sound/soc/fsl/eukrea-tlv320.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright 2019 NXP
#include <linux/bitrev.h>
#include <linux/clk.h>
#include <linux/firmware.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <sound/dmaengine_pcm.h>
#include <sound/pcm_iec958.h>
#include <sound/pcm_params.h>
#include "fsl_xcvr.h"
#include "imx-pcm.h"
#define FSL_XCVR_CAPDS_SIZE 256
struct fsl_xcvr_soc_data {
const char *fw_name;
bool spdif_only;
bool use_edma;
};
struct fsl_xcvr {
const struct fsl_xcvr_soc_data *soc_data;
struct platform_device *pdev;
struct regmap *regmap;
struct clk *ipg_clk;
struct clk *pll_ipg_clk;
struct clk *phy_clk;
struct clk *spba_clk;
struct reset_control *reset;
u8 streams;
u32 mode;
u32 arc_mode;
void __iomem *ram_addr;
struct snd_dmaengine_dai_dma_data dma_prms_rx;
struct snd_dmaengine_dai_dma_data dma_prms_tx;
struct snd_aes_iec958 rx_iec958;
struct snd_aes_iec958 tx_iec958;
u8 cap_ds[FSL_XCVR_CAPDS_SIZE];
};
static const struct fsl_xcvr_pll_conf {
u8 mfi; /* min=0x18, max=0x38 */
u32 mfn; /* signed int, 2's compl., min=0x3FFF0000, max=0x00010000 */
u32 mfd; /* unsigned int */
u32 fout; /* Fout = Fref*(MFI + MFN/MFD), Fref is 24MHz */
} fsl_xcvr_pll_cfg[] = {
{ .mfi = 54, .mfn = 1, .mfd = 6, .fout = 1300000000, }, /* 1.3 GHz */
{ .mfi = 32, .mfn = 96, .mfd = 125, .fout = 786432000, }, /* 8000 Hz */
{ .mfi = 30, .mfn = 66, .mfd = 625, .fout = 722534400, }, /* 11025 Hz */
{ .mfi = 29, .mfn = 1, .mfd = 6, .fout = 700000000, }, /* 700 MHz */
};
/*
* HDMI2.1 spec defines 6- and 12-channels layout for one bit audio
* stream. Todo: to check how this case can be considered below
*/
static const u32 fsl_xcvr_earc_channels[] = { 1, 2, 8, 16, 32, };
static const struct snd_pcm_hw_constraint_list fsl_xcvr_earc_channels_constr = {
.count = ARRAY_SIZE(fsl_xcvr_earc_channels),
.list = fsl_xcvr_earc_channels,
};
static const u32 fsl_xcvr_earc_rates[] = {
32000, 44100, 48000, 64000, 88200, 96000,
128000, 176400, 192000, 256000, 352800, 384000,
512000, 705600, 768000, 1024000, 1411200, 1536000,
};
static const struct snd_pcm_hw_constraint_list fsl_xcvr_earc_rates_constr = {
.count = ARRAY_SIZE(fsl_xcvr_earc_rates),
.list = fsl_xcvr_earc_rates,
};
static const u32 fsl_xcvr_spdif_channels[] = { 2, };
static const struct snd_pcm_hw_constraint_list fsl_xcvr_spdif_channels_constr = {
.count = ARRAY_SIZE(fsl_xcvr_spdif_channels),
.list = fsl_xcvr_spdif_channels,
};
static const u32 fsl_xcvr_spdif_rates[] = {
32000, 44100, 48000, 88200, 96000, 176400, 192000,
};
static const struct snd_pcm_hw_constraint_list fsl_xcvr_spdif_rates_constr = {
.count = ARRAY_SIZE(fsl_xcvr_spdif_rates),
.list = fsl_xcvr_spdif_rates,
};
static int fsl_xcvr_arc_mode_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned int *item = ucontrol->value.enumerated.item;
xcvr->arc_mode = snd_soc_enum_item_to_val(e, item[0]);
return 0;
}
static int fsl_xcvr_arc_mode_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
ucontrol->value.enumerated.item[0] = xcvr->arc_mode;
return 0;
}
static const u32 fsl_xcvr_phy_arc_cfg[] = {
FSL_XCVR_PHY_CTRL_ARC_MODE_SE_EN, FSL_XCVR_PHY_CTRL_ARC_MODE_CM_EN,
};
static const char * const fsl_xcvr_arc_mode[] = { "Single Ended", "Common", };
static const struct soc_enum fsl_xcvr_arc_mode_enum =
SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(fsl_xcvr_arc_mode), fsl_xcvr_arc_mode);
static struct snd_kcontrol_new fsl_xcvr_arc_mode_kctl =
SOC_ENUM_EXT("ARC Mode", fsl_xcvr_arc_mode_enum,
fsl_xcvr_arc_mode_get, fsl_xcvr_arc_mode_put);
/* Capabilities data structure, bytes */
static int fsl_xcvr_type_capds_bytes_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
uinfo->count = FSL_XCVR_CAPDS_SIZE;
return 0;
}
static int fsl_xcvr_capds_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
memcpy(ucontrol->value.bytes.data, xcvr->cap_ds, FSL_XCVR_CAPDS_SIZE);
return 0;
}
static int fsl_xcvr_capds_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
memcpy(xcvr->cap_ds, ucontrol->value.bytes.data, FSL_XCVR_CAPDS_SIZE);
return 0;
}
static struct snd_kcontrol_new fsl_xcvr_earc_capds_kctl = {
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
.name = "Capabilities Data Structure",
.access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
.info = fsl_xcvr_type_capds_bytes_info,
.get = fsl_xcvr_capds_get,
.put = fsl_xcvr_capds_put,
};
static int fsl_xcvr_activate_ctl(struct snd_soc_dai *dai, const char *name,
bool active)
{
struct snd_soc_card *card = dai->component->card;
struct snd_kcontrol *kctl;
bool enabled;
kctl = snd_soc_card_get_kcontrol(card, name);
if (kctl == NULL)
return -ENOENT;
enabled = ((kctl->vd[0].access & SNDRV_CTL_ELEM_ACCESS_WRITE) != 0);
if (active == enabled)
return 0; /* nothing to do */
if (active)
kctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
else
kctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_WRITE;
snd_ctl_notify(card->snd_card, SNDRV_CTL_EVENT_MASK_INFO, &kctl->id);
return 1;
}
static int fsl_xcvr_mode_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned int *item = ucontrol->value.enumerated.item;
struct snd_soc_card *card = dai->component->card;
struct snd_soc_pcm_runtime *rtd;
xcvr->mode = snd_soc_enum_item_to_val(e, item[0]);
fsl_xcvr_activate_ctl(dai, fsl_xcvr_arc_mode_kctl.name,
(xcvr->mode == FSL_XCVR_MODE_ARC));
fsl_xcvr_activate_ctl(dai, fsl_xcvr_earc_capds_kctl.name,
(xcvr->mode == FSL_XCVR_MODE_EARC));
/* Allow playback for SPDIF only */
rtd = snd_soc_get_pcm_runtime(card, card->dai_link);
rtd->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream_count =
(xcvr->mode == FSL_XCVR_MODE_SPDIF ? 1 : 0);
return 0;
}
static int fsl_xcvr_mode_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
ucontrol->value.enumerated.item[0] = xcvr->mode;
return 0;
}
static const char * const fsl_xcvr_mode[] = { "SPDIF", "ARC RX", "eARC", };
static const struct soc_enum fsl_xcvr_mode_enum =
SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(fsl_xcvr_mode), fsl_xcvr_mode);
static struct snd_kcontrol_new fsl_xcvr_mode_kctl =
SOC_ENUM_EXT("XCVR Mode", fsl_xcvr_mode_enum,
fsl_xcvr_mode_get, fsl_xcvr_mode_put);
/** phy: true => phy, false => pll */
static int fsl_xcvr_ai_write(struct fsl_xcvr *xcvr, u8 reg, u32 data, bool phy)
{
struct device *dev = &xcvr->pdev->dev;
u32 val, idx, tidx;
int ret;
idx = BIT(phy ? 26 : 24);
tidx = BIT(phy ? 27 : 25);
regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_CLR, 0xFF);
regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, reg);
regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_WDATA, data);
regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_TOG, idx);
ret = regmap_read_poll_timeout(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL, val,
(val & idx) == ((val & tidx) >> 1),
10, 10000);
if (ret)
dev_err(dev, "AI timeout: failed to set %s reg 0x%02x=0x%08x\n",
phy ? "PHY" : "PLL", reg, data);
return ret;
}
static int fsl_xcvr_en_phy_pll(struct fsl_xcvr *xcvr, u32 freq, bool tx)
{
struct device *dev = &xcvr->pdev->dev;
u32 i, div = 0, log2;
int ret;
if (xcvr->soc_data->spdif_only)
return 0;
for (i = 0; i < ARRAY_SIZE(fsl_xcvr_pll_cfg); i++) {
if (fsl_xcvr_pll_cfg[i].fout % freq == 0) {
div = fsl_xcvr_pll_cfg[i].fout / freq;
break;
}
}
if (!div || i >= ARRAY_SIZE(fsl_xcvr_pll_cfg))
return -EINVAL;
log2 = ilog2(div);
/* Release AI interface from reset */
ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET,
FSL_XCVR_PHY_AI_CTRL_AI_RESETN);
if (ret < 0) {
dev_err(dev, "Error while setting IER0: %d\n", ret);
return ret;
}
/* PLL: BANDGAP_SET: EN_VBG (enable bandgap) */
fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_BANDGAP_SET,
FSL_XCVR_PLL_BANDGAP_EN_VBG, 0);
/* PLL: CTRL0: DIV_INTEGER */
fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0, fsl_xcvr_pll_cfg[i].mfi, 0);
/* PLL: NUMERATOR: MFN */
fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_NUM, fsl_xcvr_pll_cfg[i].mfn, 0);
/* PLL: DENOMINATOR: MFD */
fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_DEN, fsl_xcvr_pll_cfg[i].mfd, 0);
/* PLL: CTRL0_SET: HOLD_RING_OFF, POWER_UP */
fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET,
FSL_XCVR_PLL_CTRL0_HROFF | FSL_XCVR_PLL_CTRL0_PWP, 0);
udelay(25);
/* PLL: CTRL0: Clear Hold Ring Off */
fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_CLR,
FSL_XCVR_PLL_CTRL0_HROFF, 0);
udelay(100);
if (tx) { /* TX is enabled for SPDIF only */
/* PLL: POSTDIV: PDIV0 */
fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV,
FSL_XCVR_PLL_PDIVx(log2, 0), 0);
/* PLL: CTRL_SET: CLKMUX0_EN */
fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET,
FSL_XCVR_PLL_CTRL0_CM0_EN, 0);
} else if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC RX */
/* PLL: POSTDIV: PDIV1 */
fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV,
FSL_XCVR_PLL_PDIVx(log2, 1), 0);
/* PLL: CTRL_SET: CLKMUX1_EN */
fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET,
FSL_XCVR_PLL_CTRL0_CM1_EN, 0);
} else { /* SPDIF / ARC RX */
/* PLL: POSTDIV: PDIV2 */
fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV,
FSL_XCVR_PLL_PDIVx(log2, 2), 0);
/* PLL: CTRL_SET: CLKMUX2_EN */
fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET,
FSL_XCVR_PLL_CTRL0_CM2_EN, 0);
}
if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC mode */
/* PHY: CTRL_SET: TX_DIFF_OE, PHY_EN */
fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET,
FSL_XCVR_PHY_CTRL_TSDIFF_OE |
FSL_XCVR_PHY_CTRL_PHY_EN, 1);
/* PHY: CTRL2_SET: EARC_TX_MODE */
fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL2_SET,
FSL_XCVR_PHY_CTRL2_EARC_TXMS, 1);
} else if (!tx) { /* SPDIF / ARC RX mode */
if (xcvr->mode == FSL_XCVR_MODE_SPDIF)
/* PHY: CTRL_SET: SPDIF_EN */
fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET,
FSL_XCVR_PHY_CTRL_SPDIF_EN, 1);
else /* PHY: CTRL_SET: ARC RX setup */
fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET,
FSL_XCVR_PHY_CTRL_PHY_EN |
FSL_XCVR_PHY_CTRL_RX_CM_EN |
fsl_xcvr_phy_arc_cfg[xcvr->arc_mode], 1);
}
dev_dbg(dev, "PLL Fexp: %u, Fout: %u, mfi: %u, mfn: %u, mfd: %d, div: %u, pdiv0: %u\n",
freq, fsl_xcvr_pll_cfg[i].fout, fsl_xcvr_pll_cfg[i].mfi,
fsl_xcvr_pll_cfg[i].mfn, fsl_xcvr_pll_cfg[i].mfd, div, log2);
return 0;
}
static int fsl_xcvr_en_aud_pll(struct fsl_xcvr *xcvr, u32 freq)
{
struct device *dev = &xcvr->pdev->dev;
int ret;
freq = xcvr->soc_data->spdif_only ? freq / 10 : freq;
clk_disable_unprepare(xcvr->phy_clk);
ret = clk_set_rate(xcvr->phy_clk, freq);
if (ret < 0) {
dev_err(dev, "Error while setting AUD PLL rate: %d\n", ret);
return ret;
}
ret = clk_prepare_enable(xcvr->phy_clk);
if (ret) {
dev_err(dev, "failed to start PHY clock: %d\n", ret);
return ret;
}
if (xcvr->soc_data->spdif_only)
return 0;
/* Release AI interface from reset */
ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET,
FSL_XCVR_PHY_AI_CTRL_AI_RESETN);
if (ret < 0) {
dev_err(dev, "Error while setting IER0: %d\n", ret);
return ret;
}
if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC mode */
/* PHY: CTRL_SET: TX_DIFF_OE, PHY_EN */
fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET,
FSL_XCVR_PHY_CTRL_TSDIFF_OE |
FSL_XCVR_PHY_CTRL_PHY_EN, 1);
/* PHY: CTRL2_SET: EARC_TX_MODE */
fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL2_SET,
FSL_XCVR_PHY_CTRL2_EARC_TXMS, 1);
} else { /* SPDIF mode */
/* PHY: CTRL_SET: TX_CLK_AUD_SS | SPDIF_EN */
fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET,
FSL_XCVR_PHY_CTRL_TX_CLK_AUD_SS |
FSL_XCVR_PHY_CTRL_SPDIF_EN, 1);
}
dev_dbg(dev, "PLL Fexp: %u\n", freq);
return 0;
}
#define FSL_XCVR_SPDIF_RX_FREQ 175000000
static int fsl_xcvr_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
u32 m_ctl = 0, v_ctl = 0;
u32 r = substream->runtime->rate, ch = substream->runtime->channels;
u32 fout = 32 * r * ch * 10 * 2;
int ret = 0;
switch (xcvr->mode) {
case FSL_XCVR_MODE_SPDIF:
case FSL_XCVR_MODE_ARC:
if (tx) {
ret = fsl_xcvr_en_aud_pll(xcvr, fout);
if (ret < 0) {
dev_err(dai->dev, "Failed to set TX freq %u: %d\n",
fout, ret);
return ret;
}
ret = regmap_write(xcvr->regmap, FSL_XCVR_TX_DPTH_CTRL_SET,
FSL_XCVR_TX_DPTH_CTRL_FRM_FMT);
if (ret < 0) {
dev_err(dai->dev, "Failed to set TX_DPTH: %d\n", ret);
return ret;
}
/**
* set SPDIF MODE - this flag is used to gate
* SPDIF output, useless for SPDIF RX
*/
m_ctl |= FSL_XCVR_EXT_CTRL_SPDIF_MODE;
v_ctl |= FSL_XCVR_EXT_CTRL_SPDIF_MODE;
} else {
/**
* Clear RX FIFO, flip RX FIFO bits,
* disable eARC related HW mode detects
*/
ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_SET,
FSL_XCVR_RX_DPTH_CTRL_STORE_FMT |
FSL_XCVR_RX_DPTH_CTRL_CLR_RX_FIFO |
FSL_XCVR_RX_DPTH_CTRL_COMP |
FSL_XCVR_RX_DPTH_CTRL_LAYB_CTRL);
if (ret < 0) {
dev_err(dai->dev, "Failed to set RX_DPTH: %d\n", ret);
return ret;
}
ret = fsl_xcvr_en_phy_pll(xcvr, FSL_XCVR_SPDIF_RX_FREQ, tx);
if (ret < 0) {
dev_err(dai->dev, "Failed to set RX freq %u: %d\n",
FSL_XCVR_SPDIF_RX_FREQ, ret);
return ret;
}
}
break;
case FSL_XCVR_MODE_EARC:
if (!tx) {
/** Clear RX FIFO, flip RX FIFO bits */
ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_SET,
FSL_XCVR_RX_DPTH_CTRL_STORE_FMT |
FSL_XCVR_RX_DPTH_CTRL_CLR_RX_FIFO);
if (ret < 0) {
dev_err(dai->dev, "Failed to set RX_DPTH: %d\n", ret);
return ret;
}
/** Enable eARC related HW mode detects */
ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_CLR,
FSL_XCVR_RX_DPTH_CTRL_COMP |
FSL_XCVR_RX_DPTH_CTRL_LAYB_CTRL);
if (ret < 0) {
dev_err(dai->dev, "Failed to clr TX_DPTH: %d\n", ret);
return ret;
}
}
/* clear CMDC RESET */
m_ctl |= FSL_XCVR_EXT_CTRL_CMDC_RESET(tx);
/* set TX_RX_MODE */
m_ctl |= FSL_XCVR_EXT_CTRL_TX_RX_MODE;
v_ctl |= (tx ? FSL_XCVR_EXT_CTRL_TX_RX_MODE : 0);
break;
}
ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0,
FSL_XCVR_IRQ_EARC_ALL, FSL_XCVR_IRQ_EARC_ALL);
if (ret < 0) {
dev_err(dai->dev, "Error while setting IER0: %d\n", ret);
return ret;
}
/* set DPATH RESET */
m_ctl |= FSL_XCVR_EXT_CTRL_DPTH_RESET(tx);
v_ctl |= FSL_XCVR_EXT_CTRL_DPTH_RESET(tx);
ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, m_ctl, v_ctl);
if (ret < 0) {
dev_err(dai->dev, "Error while setting EXT_CTRL: %d\n", ret);
return ret;
}
return 0;
}
static int fsl_xcvr_constr(const struct snd_pcm_substream *substream,
const struct snd_pcm_hw_constraint_list *channels,
const struct snd_pcm_hw_constraint_list *rates)
{
struct snd_pcm_runtime *rt = substream->runtime;
int ret;
ret = snd_pcm_hw_constraint_list(rt, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
channels);
if (ret < 0)
return ret;
ret = snd_pcm_hw_constraint_list(rt, 0, SNDRV_PCM_HW_PARAM_RATE,
rates);
if (ret < 0)
return ret;
return 0;
}
static int fsl_xcvr_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
int ret = 0;
if (xcvr->streams & BIT(substream->stream)) {
dev_err(dai->dev, "%sX busy\n", tx ? "T" : "R");
return -EBUSY;
}
/*
* EDMA controller needs period size to be a multiple of
* tx/rx maxburst
*/
if (xcvr->soc_data->use_edma)
snd_pcm_hw_constraint_step(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
tx ? xcvr->dma_prms_tx.maxburst :
xcvr->dma_prms_rx.maxburst);
switch (xcvr->mode) {
case FSL_XCVR_MODE_SPDIF:
case FSL_XCVR_MODE_ARC:
ret = fsl_xcvr_constr(substream, &fsl_xcvr_spdif_channels_constr,
&fsl_xcvr_spdif_rates_constr);
break;
case FSL_XCVR_MODE_EARC:
ret = fsl_xcvr_constr(substream, &fsl_xcvr_earc_channels_constr,
&fsl_xcvr_earc_rates_constr);
break;
}
if (ret < 0)
return ret;
xcvr->streams |= BIT(substream->stream);
if (!xcvr->soc_data->spdif_only) {
/* Disable XCVR controls if there is stream started */
fsl_xcvr_activate_ctl(dai, fsl_xcvr_mode_kctl.name, false);
fsl_xcvr_activate_ctl(dai, fsl_xcvr_arc_mode_kctl.name, false);
fsl_xcvr_activate_ctl(dai, fsl_xcvr_earc_capds_kctl.name, false);
}
return 0;
}
static void fsl_xcvr_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
u32 mask = 0, val = 0;
int ret;
xcvr->streams &= ~BIT(substream->stream);
/* Enable XCVR controls if there is no stream started */
if (!xcvr->streams) {
if (!xcvr->soc_data->spdif_only) {
fsl_xcvr_activate_ctl(dai, fsl_xcvr_mode_kctl.name, true);
fsl_xcvr_activate_ctl(dai, fsl_xcvr_arc_mode_kctl.name,
(xcvr->mode == FSL_XCVR_MODE_ARC));
fsl_xcvr_activate_ctl(dai, fsl_xcvr_earc_capds_kctl.name,
(xcvr->mode == FSL_XCVR_MODE_EARC));
}
ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0,
FSL_XCVR_IRQ_EARC_ALL, 0);
if (ret < 0) {
dev_err(dai->dev, "Failed to set IER0: %d\n", ret);
return;
}
/* clear SPDIF MODE */
if (xcvr->mode == FSL_XCVR_MODE_SPDIF)
mask |= FSL_XCVR_EXT_CTRL_SPDIF_MODE;
}
if (xcvr->mode == FSL_XCVR_MODE_EARC) {
/* set CMDC RESET */
mask |= FSL_XCVR_EXT_CTRL_CMDC_RESET(tx);
val |= FSL_XCVR_EXT_CTRL_CMDC_RESET(tx);
}
ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, mask, val);
if (ret < 0) {
dev_err(dai->dev, "Err setting DPATH RESET: %d\n", ret);
return;
}
}
static int fsl_xcvr_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
int ret;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
if (tx) {
switch (xcvr->mode) {
case FSL_XCVR_MODE_EARC:
/* set isr_cmdc_tx_en, w1c */
ret = regmap_write(xcvr->regmap,
FSL_XCVR_ISR_SET,
FSL_XCVR_ISR_CMDC_TX_EN);
if (ret < 0) {
dev_err(dai->dev, "err updating isr %d\n", ret);
return ret;
}
fallthrough;
case FSL_XCVR_MODE_SPDIF:
ret = regmap_write(xcvr->regmap,
FSL_XCVR_TX_DPTH_CTRL_SET,
FSL_XCVR_TX_DPTH_CTRL_STRT_DATA_TX);
if (ret < 0) {
dev_err(dai->dev, "Failed to start DATA_TX: %d\n", ret);
return ret;
}
break;
}
}
/* enable DMA RD/WR */
ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
FSL_XCVR_EXT_CTRL_DMA_DIS(tx), 0);
if (ret < 0) {
dev_err(dai->dev, "Failed to enable DMA: %d\n", ret);
return ret;
}
/* clear DPATH RESET */
ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
FSL_XCVR_EXT_CTRL_DPTH_RESET(tx),
0);
if (ret < 0) {
dev_err(dai->dev, "Failed to clear DPATH RESET: %d\n", ret);
return ret;
}
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
/* disable DMA RD/WR */
ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
FSL_XCVR_EXT_CTRL_DMA_DIS(tx),
FSL_XCVR_EXT_CTRL_DMA_DIS(tx));
if (ret < 0) {
dev_err(dai->dev, "Failed to disable DMA: %d\n", ret);
return ret;
}
if (tx) {
switch (xcvr->mode) {
case FSL_XCVR_MODE_SPDIF:
ret = regmap_write(xcvr->regmap,
FSL_XCVR_TX_DPTH_CTRL_CLR,
FSL_XCVR_TX_DPTH_CTRL_STRT_DATA_TX);
if (ret < 0) {
dev_err(dai->dev, "Failed to stop DATA_TX: %d\n", ret);
return ret;
}
if (xcvr->soc_data->spdif_only)
break;
else
fallthrough;
case FSL_XCVR_MODE_EARC:
/* clear ISR_CMDC_TX_EN, W1C */
ret = regmap_write(xcvr->regmap,
FSL_XCVR_ISR_CLR,
FSL_XCVR_ISR_CMDC_TX_EN);
if (ret < 0) {
dev_err(dai->dev,
"Err updating ISR %d\n", ret);
return ret;
}
break;
}
}
break;
default:
return -EINVAL;
}
return 0;
}
static int fsl_xcvr_load_firmware(struct fsl_xcvr *xcvr)
{
struct device *dev = &xcvr->pdev->dev;
const struct firmware *fw;
int ret = 0, rem, off, out, page = 0, size = FSL_XCVR_REG_OFFSET;
u32 mask, val;
ret = request_firmware(&fw, xcvr->soc_data->fw_name, dev);
if (ret) {
dev_err(dev, "failed to request firmware.\n");
return ret;
}
rem = fw->size;
/* RAM is 20KiB = 16KiB code + 4KiB data => max 10 pages 2KiB each */
if (rem > 16384) {
dev_err(dev, "FW size %d is bigger than 16KiB.\n", rem);
release_firmware(fw);
return -ENOMEM;
}
for (page = 0; page < 10; page++) {
ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
FSL_XCVR_EXT_CTRL_PAGE_MASK,
FSL_XCVR_EXT_CTRL_PAGE(page));
if (ret < 0) {
dev_err(dev, "FW: failed to set page %d, err=%d\n",
page, ret);
goto err_firmware;
}
off = page * size;
out = min(rem, size);
/* IPG clock is assumed to be running, otherwise it will hang */
if (out > 0) {
/* write firmware into code memory */
memcpy_toio(xcvr->ram_addr, fw->data + off, out);
rem -= out;
if (rem == 0) {
/* last part of firmware written */
/* clean remaining part of code memory page */
memset_io(xcvr->ram_addr + out, 0, size - out);
}
} else {
/* clean current page, including data memory */
memset_io(xcvr->ram_addr, 0, size);
}
}
err_firmware:
release_firmware(fw);
if (ret < 0)
return ret;
/* configure watermarks */
mask = FSL_XCVR_EXT_CTRL_RX_FWM_MASK | FSL_XCVR_EXT_CTRL_TX_FWM_MASK;
val = FSL_XCVR_EXT_CTRL_RX_FWM(FSL_XCVR_FIFO_WMK_RX);
val |= FSL_XCVR_EXT_CTRL_TX_FWM(FSL_XCVR_FIFO_WMK_TX);
/* disable DMA RD/WR */
mask |= FSL_XCVR_EXT_CTRL_DMA_RD_DIS | FSL_XCVR_EXT_CTRL_DMA_WR_DIS;
val |= FSL_XCVR_EXT_CTRL_DMA_RD_DIS | FSL_XCVR_EXT_CTRL_DMA_WR_DIS;
/* Data RAM is 4KiB, last two pages: 8 and 9. Select page 8. */
mask |= FSL_XCVR_EXT_CTRL_PAGE_MASK;
val |= FSL_XCVR_EXT_CTRL_PAGE(8);
ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, mask, val);
if (ret < 0) {
dev_err(dev, "Failed to set watermarks: %d\n", ret);
return ret;
}
/* Store Capabilities Data Structure into Data RAM */
memcpy_toio(xcvr->ram_addr + FSL_XCVR_CAP_DATA_STR, xcvr->cap_ds,
FSL_XCVR_CAPDS_SIZE);
return 0;
}
static int fsl_xcvr_type_iec958_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
uinfo->count = 1;
return 0;
}
static int fsl_xcvr_type_iec958_bytes_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
uinfo->count = sizeof_field(struct snd_aes_iec958, status);
return 0;
}
static int fsl_xcvr_rx_cs_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
memcpy(ucontrol->value.iec958.status, xcvr->rx_iec958.status, 24);
return 0;
}
static int fsl_xcvr_tx_cs_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
memcpy(ucontrol->value.iec958.status, xcvr->tx_iec958.status, 24);
return 0;
}
static int fsl_xcvr_tx_cs_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
memcpy(xcvr->tx_iec958.status, ucontrol->value.iec958.status, 24);
return 0;
}
static struct snd_kcontrol_new fsl_xcvr_rx_ctls[] = {
/* Channel status controller */
{
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
.name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
.access = SNDRV_CTL_ELEM_ACCESS_READ,
.info = fsl_xcvr_type_iec958_info,
.get = fsl_xcvr_rx_cs_get,
},
/* Capture channel status, bytes */
{
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
.name = "Capture Channel Status",
.access = SNDRV_CTL_ELEM_ACCESS_READ,
.info = fsl_xcvr_type_iec958_bytes_info,
.get = fsl_xcvr_rx_cs_get,
},
};
static struct snd_kcontrol_new fsl_xcvr_tx_ctls[] = {
/* Channel status controller */
{
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
.name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
.access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
.info = fsl_xcvr_type_iec958_info,
.get = fsl_xcvr_tx_cs_get,
.put = fsl_xcvr_tx_cs_put,
},
/* Playback channel status, bytes */
{
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
.name = "Playback Channel Status",
.access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
.info = fsl_xcvr_type_iec958_bytes_info,
.get = fsl_xcvr_tx_cs_get,
.put = fsl_xcvr_tx_cs_put,
},
};
static int fsl_xcvr_dai_probe(struct snd_soc_dai *dai)
{
struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
snd_soc_dai_init_dma_data(dai, &xcvr->dma_prms_tx, &xcvr->dma_prms_rx);
if (xcvr->soc_data->spdif_only)
xcvr->mode = FSL_XCVR_MODE_SPDIF;
else {
snd_soc_add_dai_controls(dai, &fsl_xcvr_mode_kctl, 1);
snd_soc_add_dai_controls(dai, &fsl_xcvr_arc_mode_kctl, 1);
snd_soc_add_dai_controls(dai, &fsl_xcvr_earc_capds_kctl, 1);
}
snd_soc_add_dai_controls(dai, fsl_xcvr_tx_ctls,
ARRAY_SIZE(fsl_xcvr_tx_ctls));
snd_soc_add_dai_controls(dai, fsl_xcvr_rx_ctls,
ARRAY_SIZE(fsl_xcvr_rx_ctls));
return 0;
}
static const struct snd_soc_dai_ops fsl_xcvr_dai_ops = {
.probe = fsl_xcvr_dai_probe,
.prepare = fsl_xcvr_prepare,
.startup = fsl_xcvr_startup,
.shutdown = fsl_xcvr_shutdown,
.trigger = fsl_xcvr_trigger,
};
static struct snd_soc_dai_driver fsl_xcvr_dai = {
.ops = &fsl_xcvr_dai_ops,
.playback = {
.stream_name = "CPU-Playback",
.channels_min = 1,
.channels_max = 32,
.rate_min = 32000,
.rate_max = 1536000,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
},
.capture = {
.stream_name = "CPU-Capture",
.channels_min = 1,
.channels_max = 32,
.rate_min = 32000,
.rate_max = 1536000,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
},
};
static const struct snd_soc_component_driver fsl_xcvr_comp = {
.name = "fsl-xcvr-dai",
.legacy_dai_naming = 1,
};
static const struct reg_default fsl_xcvr_reg_defaults[] = {
{ FSL_XCVR_VERSION, 0x00000000 },
{ FSL_XCVR_EXT_CTRL, 0xF8204040 },
{ FSL_XCVR_EXT_STATUS, 0x00000000 },
{ FSL_XCVR_EXT_IER0, 0x00000000 },
{ FSL_XCVR_EXT_IER1, 0x00000000 },
{ FSL_XCVR_EXT_ISR, 0x00000000 },
{ FSL_XCVR_EXT_ISR_SET, 0x00000000 },
{ FSL_XCVR_EXT_ISR_CLR, 0x00000000 },
{ FSL_XCVR_EXT_ISR_TOG, 0x00000000 },
{ FSL_XCVR_IER, 0x00000000 },
{ FSL_XCVR_ISR, 0x00000000 },
{ FSL_XCVR_ISR_SET, 0x00000000 },
{ FSL_XCVR_ISR_CLR, 0x00000000 },
{ FSL_XCVR_ISR_TOG, 0x00000000 },
{ FSL_XCVR_CLK_CTRL, 0x0000018F },
{ FSL_XCVR_RX_DPTH_CTRL, 0x00040CC1 },
{ FSL_XCVR_RX_DPTH_CTRL_SET, 0x00040CC1 },
{ FSL_XCVR_RX_DPTH_CTRL_CLR, 0x00040CC1 },
{ FSL_XCVR_RX_DPTH_CTRL_TOG, 0x00040CC1 },
{ FSL_XCVR_RX_DPTH_CNTR_CTRL, 0x00000000 },
{ FSL_XCVR_RX_DPTH_CNTR_CTRL_SET, 0x00000000 },
{ FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR, 0x00000000 },
{ FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG, 0x00000000 },
{ FSL_XCVR_RX_DPTH_TSCR, 0x00000000 },
{ FSL_XCVR_RX_DPTH_BCR, 0x00000000 },
{ FSL_XCVR_RX_DPTH_BCTR, 0x00000000 },
{ FSL_XCVR_RX_DPTH_BCRR, 0x00000000 },
{ FSL_XCVR_TX_DPTH_CTRL, 0x00000000 },
{ FSL_XCVR_TX_DPTH_CTRL_SET, 0x00000000 },
{ FSL_XCVR_TX_DPTH_CTRL_CLR, 0x00000000 },
{ FSL_XCVR_TX_DPTH_CTRL_TOG, 0x00000000 },
{ FSL_XCVR_TX_CS_DATA_0, 0x00000000 },
{ FSL_XCVR_TX_CS_DATA_1, 0x00000000 },
{ FSL_XCVR_TX_CS_DATA_2, 0x00000000 },
{ FSL_XCVR_TX_CS_DATA_3, 0x00000000 },
{ FSL_XCVR_TX_CS_DATA_4, 0x00000000 },
{ FSL_XCVR_TX_CS_DATA_5, 0x00000000 },
{ FSL_XCVR_TX_DPTH_CNTR_CTRL, 0x00000000 },
{ FSL_XCVR_TX_DPTH_CNTR_CTRL_SET, 0x00000000 },
{ FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR, 0x00000000 },
{ FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG, 0x00000000 },
{ FSL_XCVR_TX_DPTH_TSCR, 0x00000000 },
{ FSL_XCVR_TX_DPTH_BCR, 0x00000000 },
{ FSL_XCVR_TX_DPTH_BCTR, 0x00000000 },
{ FSL_XCVR_TX_DPTH_BCRR, 0x00000000 },
{ FSL_XCVR_DEBUG_REG_0, 0x00000000 },
{ FSL_XCVR_DEBUG_REG_1, 0x00000000 },
};
static bool fsl_xcvr_readable_reg(struct device *dev, unsigned int reg)
{
struct fsl_xcvr *xcvr = dev_get_drvdata(dev);
if (xcvr->soc_data->spdif_only)
if ((reg >= FSL_XCVR_IER && reg <= FSL_XCVR_PHY_AI_RDATA) ||
reg > FSL_XCVR_TX_DPTH_BCRR)
return false;
switch (reg) {
case FSL_XCVR_VERSION:
case FSL_XCVR_EXT_CTRL:
case FSL_XCVR_EXT_STATUS:
case FSL_XCVR_EXT_IER0:
case FSL_XCVR_EXT_IER1:
case FSL_XCVR_EXT_ISR:
case FSL_XCVR_EXT_ISR_SET:
case FSL_XCVR_EXT_ISR_CLR:
case FSL_XCVR_EXT_ISR_TOG:
case FSL_XCVR_IER:
case FSL_XCVR_ISR:
case FSL_XCVR_ISR_SET:
case FSL_XCVR_ISR_CLR:
case FSL_XCVR_ISR_TOG:
case FSL_XCVR_PHY_AI_CTRL:
case FSL_XCVR_PHY_AI_CTRL_SET:
case FSL_XCVR_PHY_AI_CTRL_CLR:
case FSL_XCVR_PHY_AI_CTRL_TOG:
case FSL_XCVR_PHY_AI_RDATA:
case FSL_XCVR_CLK_CTRL:
case FSL_XCVR_RX_DPTH_CTRL:
case FSL_XCVR_RX_DPTH_CTRL_SET:
case FSL_XCVR_RX_DPTH_CTRL_CLR:
case FSL_XCVR_RX_DPTH_CTRL_TOG:
case FSL_XCVR_RX_CS_DATA_0:
case FSL_XCVR_RX_CS_DATA_1:
case FSL_XCVR_RX_CS_DATA_2:
case FSL_XCVR_RX_CS_DATA_3:
case FSL_XCVR_RX_CS_DATA_4:
case FSL_XCVR_RX_CS_DATA_5:
case FSL_XCVR_RX_DPTH_CNTR_CTRL:
case FSL_XCVR_RX_DPTH_CNTR_CTRL_SET:
case FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR:
case FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG:
case FSL_XCVR_RX_DPTH_TSCR:
case FSL_XCVR_RX_DPTH_BCR:
case FSL_XCVR_RX_DPTH_BCTR:
case FSL_XCVR_RX_DPTH_BCRR:
case FSL_XCVR_TX_DPTH_CTRL:
case FSL_XCVR_TX_DPTH_CTRL_SET:
case FSL_XCVR_TX_DPTH_CTRL_CLR:
case FSL_XCVR_TX_DPTH_CTRL_TOG:
case FSL_XCVR_TX_CS_DATA_0:
case FSL_XCVR_TX_CS_DATA_1:
case FSL_XCVR_TX_CS_DATA_2:
case FSL_XCVR_TX_CS_DATA_3:
case FSL_XCVR_TX_CS_DATA_4:
case FSL_XCVR_TX_CS_DATA_5:
case FSL_XCVR_TX_DPTH_CNTR_CTRL:
case FSL_XCVR_TX_DPTH_CNTR_CTRL_SET:
case FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR:
case FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG:
case FSL_XCVR_TX_DPTH_TSCR:
case FSL_XCVR_TX_DPTH_BCR:
case FSL_XCVR_TX_DPTH_BCTR:
case FSL_XCVR_TX_DPTH_BCRR:
case FSL_XCVR_DEBUG_REG_0:
case FSL_XCVR_DEBUG_REG_1:
return true;
default:
return false;
}
}
static bool fsl_xcvr_writeable_reg(struct device *dev, unsigned int reg)
{
struct fsl_xcvr *xcvr = dev_get_drvdata(dev);
if (xcvr->soc_data->spdif_only)
if (reg >= FSL_XCVR_IER && reg <= FSL_XCVR_PHY_AI_RDATA)
return false;
switch (reg) {
case FSL_XCVR_EXT_CTRL:
case FSL_XCVR_EXT_IER0:
case FSL_XCVR_EXT_IER1:
case FSL_XCVR_EXT_ISR:
case FSL_XCVR_EXT_ISR_SET:
case FSL_XCVR_EXT_ISR_CLR:
case FSL_XCVR_EXT_ISR_TOG:
case FSL_XCVR_IER:
case FSL_XCVR_ISR_SET:
case FSL_XCVR_ISR_CLR:
case FSL_XCVR_ISR_TOG:
case FSL_XCVR_PHY_AI_CTRL:
case FSL_XCVR_PHY_AI_CTRL_SET:
case FSL_XCVR_PHY_AI_CTRL_CLR:
case FSL_XCVR_PHY_AI_CTRL_TOG:
case FSL_XCVR_PHY_AI_WDATA:
case FSL_XCVR_CLK_CTRL:
case FSL_XCVR_RX_DPTH_CTRL:
case FSL_XCVR_RX_DPTH_CTRL_SET:
case FSL_XCVR_RX_DPTH_CTRL_CLR:
case FSL_XCVR_RX_DPTH_CTRL_TOG:
case FSL_XCVR_RX_DPTH_CNTR_CTRL:
case FSL_XCVR_RX_DPTH_CNTR_CTRL_SET:
case FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR:
case FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG:
case FSL_XCVR_TX_DPTH_CTRL_SET:
case FSL_XCVR_TX_DPTH_CTRL_CLR:
case FSL_XCVR_TX_DPTH_CTRL_TOG:
case FSL_XCVR_TX_CS_DATA_0:
case FSL_XCVR_TX_CS_DATA_1:
case FSL_XCVR_TX_CS_DATA_2:
case FSL_XCVR_TX_CS_DATA_3:
case FSL_XCVR_TX_CS_DATA_4:
case FSL_XCVR_TX_CS_DATA_5:
case FSL_XCVR_TX_DPTH_CNTR_CTRL:
case FSL_XCVR_TX_DPTH_CNTR_CTRL_SET:
case FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR:
case FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG:
return true;
default:
return false;
}
}
static bool fsl_xcvr_volatile_reg(struct device *dev, unsigned int reg)
{
return fsl_xcvr_readable_reg(dev, reg);
}
static const struct regmap_config fsl_xcvr_regmap_cfg = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = FSL_XCVR_MAX_REG,
.reg_defaults = fsl_xcvr_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(fsl_xcvr_reg_defaults),
.readable_reg = fsl_xcvr_readable_reg,
.volatile_reg = fsl_xcvr_volatile_reg,
.writeable_reg = fsl_xcvr_writeable_reg,
.cache_type = REGCACHE_FLAT,
};
static irqreturn_t irq0_isr(int irq, void *devid)
{
struct fsl_xcvr *xcvr = (struct fsl_xcvr *)devid;
struct device *dev = &xcvr->pdev->dev;
struct regmap *regmap = xcvr->regmap;
void __iomem *reg_ctrl, *reg_buff;
u32 isr, isr_clr = 0, val, i;
regmap_read(regmap, FSL_XCVR_EXT_ISR, &isr);
if (isr & FSL_XCVR_IRQ_NEW_CS) {
dev_dbg(dev, "Received new CS block\n");
isr_clr |= FSL_XCVR_IRQ_NEW_CS;
if (!xcvr->soc_data->spdif_only) {
/* Data RAM is 4KiB, last two pages: 8 and 9. Select page 8. */
regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
FSL_XCVR_EXT_CTRL_PAGE_MASK,
FSL_XCVR_EXT_CTRL_PAGE(8));
/* Find updated CS buffer */
reg_ctrl = xcvr->ram_addr + FSL_XCVR_RX_CS_CTRL_0;
reg_buff = xcvr->ram_addr + FSL_XCVR_RX_CS_BUFF_0;
memcpy_fromio(&val, reg_ctrl, sizeof(val));
if (!val) {
reg_ctrl = xcvr->ram_addr + FSL_XCVR_RX_CS_CTRL_1;
reg_buff = xcvr->ram_addr + FSL_XCVR_RX_CS_BUFF_1;
memcpy_fromio(&val, reg_ctrl, sizeof(val));
}
if (val) {
/* copy CS buffer */
memcpy_fromio(&xcvr->rx_iec958.status, reg_buff,
sizeof(xcvr->rx_iec958.status));
for (i = 0; i < 6; i++) {
val = *(u32 *)(xcvr->rx_iec958.status + i*4);
*(u32 *)(xcvr->rx_iec958.status + i*4) =
bitrev32(val);
}
/* clear CS control register */
memset_io(reg_ctrl, 0, sizeof(val));
}
}
}
if (isr & FSL_XCVR_IRQ_NEW_UD) {
dev_dbg(dev, "Received new UD block\n");
isr_clr |= FSL_XCVR_IRQ_NEW_UD;
}
if (isr & FSL_XCVR_IRQ_MUTE) {
dev_dbg(dev, "HW mute bit detected\n");
isr_clr |= FSL_XCVR_IRQ_MUTE;
}
if (isr & FSL_XCVR_IRQ_FIFO_UOFL_ERR) {
dev_dbg(dev, "RX/TX FIFO full/empty\n");
isr_clr |= FSL_XCVR_IRQ_FIFO_UOFL_ERR;
}
if (isr & FSL_XCVR_IRQ_ARC_MODE) {
dev_dbg(dev, "CMDC SM falls out of eARC mode\n");
isr_clr |= FSL_XCVR_IRQ_ARC_MODE;
}
if (isr & FSL_XCVR_IRQ_DMA_RD_REQ) {
dev_dbg(dev, "DMA read request\n");
isr_clr |= FSL_XCVR_IRQ_DMA_RD_REQ;
}
if (isr & FSL_XCVR_IRQ_DMA_WR_REQ) {
dev_dbg(dev, "DMA write request\n");
isr_clr |= FSL_XCVR_IRQ_DMA_WR_REQ;
}
if (isr_clr) {
regmap_write(regmap, FSL_XCVR_EXT_ISR_CLR, isr_clr);
return IRQ_HANDLED;
}
return IRQ_NONE;
}
static const struct fsl_xcvr_soc_data fsl_xcvr_imx8mp_data = {
.fw_name = "imx/xcvr/xcvr-imx8mp.bin",
};
static const struct fsl_xcvr_soc_data fsl_xcvr_imx93_data = {
.spdif_only = true,
.use_edma = true,
};
static const struct of_device_id fsl_xcvr_dt_ids[] = {
{ .compatible = "fsl,imx8mp-xcvr", .data = &fsl_xcvr_imx8mp_data },
{ .compatible = "fsl,imx93-xcvr", .data = &fsl_xcvr_imx93_data},
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, fsl_xcvr_dt_ids);
static int fsl_xcvr_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct fsl_xcvr *xcvr;
struct resource *rx_res, *tx_res;
void __iomem *regs;
int ret, irq;
xcvr = devm_kzalloc(dev, sizeof(*xcvr), GFP_KERNEL);
if (!xcvr)
return -ENOMEM;
xcvr->pdev = pdev;
xcvr->soc_data = of_device_get_match_data(&pdev->dev);
xcvr->ipg_clk = devm_clk_get(dev, "ipg");
if (IS_ERR(xcvr->ipg_clk)) {
dev_err(dev, "failed to get ipg clock\n");
return PTR_ERR(xcvr->ipg_clk);
}
xcvr->phy_clk = devm_clk_get(dev, "phy");
if (IS_ERR(xcvr->phy_clk)) {
dev_err(dev, "failed to get phy clock\n");
return PTR_ERR(xcvr->phy_clk);
}
xcvr->spba_clk = devm_clk_get(dev, "spba");
if (IS_ERR(xcvr->spba_clk)) {
dev_err(dev, "failed to get spba clock\n");
return PTR_ERR(xcvr->spba_clk);
}
xcvr->pll_ipg_clk = devm_clk_get(dev, "pll_ipg");
if (IS_ERR(xcvr->pll_ipg_clk)) {
dev_err(dev, "failed to get pll_ipg clock\n");
return PTR_ERR(xcvr->pll_ipg_clk);
}
xcvr->ram_addr = devm_platform_ioremap_resource_byname(pdev, "ram");
if (IS_ERR(xcvr->ram_addr))
return PTR_ERR(xcvr->ram_addr);
regs = devm_platform_ioremap_resource_byname(pdev, "regs");
if (IS_ERR(regs))
return PTR_ERR(regs);
xcvr->regmap = devm_regmap_init_mmio_clk(dev, NULL, regs,
&fsl_xcvr_regmap_cfg);
if (IS_ERR(xcvr->regmap)) {
dev_err(dev, "failed to init XCVR regmap: %ld\n",
PTR_ERR(xcvr->regmap));
return PTR_ERR(xcvr->regmap);
}
xcvr->reset = devm_reset_control_get_optional_exclusive(dev, NULL);
if (IS_ERR(xcvr->reset)) {
dev_err(dev, "failed to get XCVR reset control\n");
return PTR_ERR(xcvr->reset);
}
/* get IRQs */
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
ret = devm_request_irq(dev, irq, irq0_isr, 0, pdev->name, xcvr);
if (ret) {
dev_err(dev, "failed to claim IRQ0: %i\n", ret);
return ret;
}
rx_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rxfifo");
tx_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "txfifo");
if (!rx_res || !tx_res) {
dev_err(dev, "could not find rxfifo or txfifo resource\n");
return -EINVAL;
}
xcvr->dma_prms_rx.chan_name = "rx";
xcvr->dma_prms_tx.chan_name = "tx";
xcvr->dma_prms_rx.addr = rx_res->start;
xcvr->dma_prms_tx.addr = tx_res->start;
xcvr->dma_prms_rx.maxburst = FSL_XCVR_MAXBURST_RX;
xcvr->dma_prms_tx.maxburst = FSL_XCVR_MAXBURST_TX;
platform_set_drvdata(pdev, xcvr);
pm_runtime_enable(dev);
regcache_cache_only(xcvr->regmap, true);
/*
* Register platform component before registering cpu dai for there
* is not defer probe for platform component in snd_soc_add_pcm_runtime().
*/
ret = devm_snd_dmaengine_pcm_register(dev, NULL, 0);
if (ret) {
pm_runtime_disable(dev);
dev_err(dev, "failed to pcm register\n");
return ret;
}
ret = devm_snd_soc_register_component(dev, &fsl_xcvr_comp,
&fsl_xcvr_dai, 1);
if (ret) {
pm_runtime_disable(dev);
dev_err(dev, "failed to register component %s\n",
fsl_xcvr_comp.name);
}
return ret;
}
static void fsl_xcvr_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
}
static __maybe_unused int fsl_xcvr_runtime_suspend(struct device *dev)
{
struct fsl_xcvr *xcvr = dev_get_drvdata(dev);
int ret;
/*
* Clear interrupts, when streams starts or resumes after
* suspend, interrupts are enabled in prepare(), so no need
* to enable interrupts in resume().
*/
ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0,
FSL_XCVR_IRQ_EARC_ALL, 0);
if (ret < 0)
dev_err(dev, "Failed to clear IER0: %d\n", ret);
if (!xcvr->soc_data->spdif_only) {
/* Assert M0+ reset */
ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
FSL_XCVR_EXT_CTRL_CORE_RESET,
FSL_XCVR_EXT_CTRL_CORE_RESET);
if (ret < 0)
dev_err(dev, "Failed to assert M0+ core: %d\n", ret);
}
regcache_cache_only(xcvr->regmap, true);
clk_disable_unprepare(xcvr->spba_clk);
clk_disable_unprepare(xcvr->phy_clk);
clk_disable_unprepare(xcvr->pll_ipg_clk);
clk_disable_unprepare(xcvr->ipg_clk);
return 0;
}
static __maybe_unused int fsl_xcvr_runtime_resume(struct device *dev)
{
struct fsl_xcvr *xcvr = dev_get_drvdata(dev);
int ret;
ret = reset_control_assert(xcvr->reset);
if (ret < 0) {
dev_err(dev, "Failed to assert M0+ reset: %d\n", ret);
return ret;
}
ret = clk_prepare_enable(xcvr->ipg_clk);
if (ret) {
dev_err(dev, "failed to start IPG clock.\n");
return ret;
}
ret = clk_prepare_enable(xcvr->pll_ipg_clk);
if (ret) {
dev_err(dev, "failed to start PLL IPG clock.\n");
goto stop_ipg_clk;
}
ret = clk_prepare_enable(xcvr->phy_clk);
if (ret) {
dev_err(dev, "failed to start PHY clock: %d\n", ret);
goto stop_pll_ipg_clk;
}
ret = clk_prepare_enable(xcvr->spba_clk);
if (ret) {
dev_err(dev, "failed to start SPBA clock.\n");
goto stop_phy_clk;
}
regcache_cache_only(xcvr->regmap, false);
regcache_mark_dirty(xcvr->regmap);
ret = regcache_sync(xcvr->regmap);
if (ret) {
dev_err(dev, "failed to sync regcache.\n");
goto stop_spba_clk;
}
if (xcvr->soc_data->spdif_only)
return 0;
ret = reset_control_deassert(xcvr->reset);
if (ret) {
dev_err(dev, "failed to deassert M0+ reset.\n");
goto stop_spba_clk;
}
ret = fsl_xcvr_load_firmware(xcvr);
if (ret) {
dev_err(dev, "failed to load firmware.\n");
goto stop_spba_clk;
}
/* Release M0+ reset */
ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
FSL_XCVR_EXT_CTRL_CORE_RESET, 0);
if (ret < 0) {
dev_err(dev, "M0+ core release failed: %d\n", ret);
goto stop_spba_clk;
}
/* Let M0+ core complete firmware initialization */
msleep(50);
return 0;
stop_spba_clk:
clk_disable_unprepare(xcvr->spba_clk);
stop_phy_clk:
clk_disable_unprepare(xcvr->phy_clk);
stop_pll_ipg_clk:
clk_disable_unprepare(xcvr->pll_ipg_clk);
stop_ipg_clk:
clk_disable_unprepare(xcvr->ipg_clk);
return ret;
}
static const struct dev_pm_ops fsl_xcvr_pm_ops = {
SET_RUNTIME_PM_OPS(fsl_xcvr_runtime_suspend,
fsl_xcvr_runtime_resume,
NULL)
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
};
static struct platform_driver fsl_xcvr_driver = {
.probe = fsl_xcvr_probe,
.driver = {
.name = "fsl,imx8mp-audio-xcvr",
.pm = &fsl_xcvr_pm_ops,
.of_match_table = fsl_xcvr_dt_ids,
},
.remove_new = fsl_xcvr_remove,
};
module_platform_driver(fsl_xcvr_driver);
MODULE_AUTHOR("Viorel Suman <[email protected]>");
MODULE_DESCRIPTION("NXP Audio Transceiver (XCVR) driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/fsl/fsl_xcvr.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright 2017-2020 NXP
#include <linux/module.h>
#include <linux/of_platform.h>
#include <sound/jack.h>
#include <sound/pcm_params.h>
#include <sound/hdmi-codec.h>
#include "fsl_sai.h"
/**
* struct cpu_priv - CPU private data
* @sysclk_id: SYSCLK ids for set_sysclk()
* @slot_width: Slot width of each frame
*
* Note: [1] for tx and [0] for rx
*/
struct cpu_priv {
u32 sysclk_id[2];
u32 slot_width;
};
struct imx_hdmi_data {
struct snd_soc_dai_link dai;
struct snd_soc_card card;
struct snd_soc_jack hdmi_jack;
struct snd_soc_jack_pin hdmi_jack_pin;
struct cpu_priv cpu_priv;
u32 dai_fmt;
};
static int imx_hdmi_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct imx_hdmi_data *data = snd_soc_card_get_drvdata(rtd->card);
bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct snd_soc_card *card = rtd->card;
struct device *dev = card->dev;
u32 slot_width = data->cpu_priv.slot_width;
int ret;
/* MCLK always is (256 or 192) * rate. */
ret = snd_soc_dai_set_sysclk(cpu_dai, data->cpu_priv.sysclk_id[tx],
8 * slot_width * params_rate(params),
tx ? SND_SOC_CLOCK_OUT : SND_SOC_CLOCK_IN);
if (ret && ret != -ENOTSUPP) {
dev_err(dev, "failed to set cpu sysclk: %d\n", ret);
return ret;
}
ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, 0, 2, slot_width);
if (ret && ret != -ENOTSUPP) {
dev_err(dev, "failed to set cpu dai tdm slot: %d\n", ret);
return ret;
}
return 0;
}
static const struct snd_soc_ops imx_hdmi_ops = {
.hw_params = imx_hdmi_hw_params,
};
static const struct snd_soc_dapm_widget imx_hdmi_widgets[] = {
SND_SOC_DAPM_LINE("HDMI Jack", NULL),
};
static int imx_hdmi_init(struct snd_soc_pcm_runtime *rtd)
{
struct snd_soc_card *card = rtd->card;
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
struct snd_soc_component *component = codec_dai->component;
struct imx_hdmi_data *data = snd_soc_card_get_drvdata(card);
int ret;
data->hdmi_jack_pin.pin = "HDMI Jack";
data->hdmi_jack_pin.mask = SND_JACK_LINEOUT;
/* enable jack detection */
ret = snd_soc_card_jack_new_pins(card, "HDMI Jack", SND_JACK_LINEOUT,
&data->hdmi_jack,
&data->hdmi_jack_pin, 1);
if (ret) {
dev_err(card->dev, "Can't new HDMI Jack %d\n", ret);
return ret;
}
ret = snd_soc_component_set_jack(component, &data->hdmi_jack, NULL);
if (ret && ret != -ENOTSUPP) {
dev_err(card->dev, "Can't set HDMI Jack %d\n", ret);
return ret;
}
return 0;
};
static int imx_hdmi_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
bool hdmi_out = of_property_read_bool(np, "hdmi-out");
bool hdmi_in = of_property_read_bool(np, "hdmi-in");
struct snd_soc_dai_link_component *dlc;
struct platform_device *cpu_pdev;
struct device_node *cpu_np;
struct imx_hdmi_data *data;
int ret;
dlc = devm_kzalloc(&pdev->dev, 3 * sizeof(*dlc), GFP_KERNEL);
if (!dlc)
return -ENOMEM;
cpu_np = of_parse_phandle(np, "audio-cpu", 0);
if (!cpu_np) {
dev_err(&pdev->dev, "cpu dai phandle missing or invalid\n");
ret = -EINVAL;
goto fail;
}
cpu_pdev = of_find_device_by_node(cpu_np);
if (!cpu_pdev) {
dev_err(&pdev->dev, "failed to find SAI platform device\n");
ret = -EINVAL;
goto fail;
}
data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
if (!data) {
ret = -ENOMEM;
put_device(&cpu_pdev->dev);
goto fail;
}
data->dai.cpus = &dlc[0];
data->dai.num_cpus = 1;
data->dai.platforms = &dlc[1];
data->dai.num_platforms = 1;
data->dai.codecs = &dlc[2];
data->dai.num_codecs = 1;
data->dai.name = "i.MX HDMI";
data->dai.stream_name = "i.MX HDMI";
data->dai.cpus->dai_name = dev_name(&cpu_pdev->dev);
data->dai.platforms->of_node = cpu_np;
data->dai.ops = &imx_hdmi_ops;
data->dai.playback_only = true;
data->dai.capture_only = false;
data->dai.init = imx_hdmi_init;
put_device(&cpu_pdev->dev);
if (of_node_name_eq(cpu_np, "sai")) {
data->cpu_priv.sysclk_id[1] = FSL_SAI_CLK_MAST1;
data->cpu_priv.sysclk_id[0] = FSL_SAI_CLK_MAST1;
}
if (of_device_is_compatible(np, "fsl,imx-audio-sii902x")) {
data->dai_fmt = SND_SOC_DAIFMT_LEFT_J;
data->cpu_priv.slot_width = 24;
} else {
data->dai_fmt = SND_SOC_DAIFMT_I2S;
data->cpu_priv.slot_width = 32;
}
if ((hdmi_out && hdmi_in) || (!hdmi_out && !hdmi_in)) {
dev_err(&pdev->dev, "Invalid HDMI DAI link\n");
ret = -EINVAL;
goto fail;
}
if (hdmi_out) {
data->dai.playback_only = true;
data->dai.capture_only = false;
data->dai.codecs->dai_name = "i2s-hifi";
data->dai.codecs->name = "hdmi-audio-codec.1";
data->dai.dai_fmt = data->dai_fmt |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBC_CFC;
}
if (hdmi_in) {
data->dai.playback_only = false;
data->dai.capture_only = true;
data->dai.codecs->dai_name = "i2s-hifi";
data->dai.codecs->name = "hdmi-audio-codec.2";
data->dai.dai_fmt = data->dai_fmt |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBP_CFP;
}
data->card.dapm_widgets = imx_hdmi_widgets;
data->card.num_dapm_widgets = ARRAY_SIZE(imx_hdmi_widgets);
data->card.dev = &pdev->dev;
data->card.owner = THIS_MODULE;
ret = snd_soc_of_parse_card_name(&data->card, "model");
if (ret)
goto fail;
data->card.num_links = 1;
data->card.dai_link = &data->dai;
snd_soc_card_set_drvdata(&data->card, data);
ret = devm_snd_soc_register_card(&pdev->dev, &data->card);
if (ret) {
dev_err_probe(&pdev->dev, ret, "snd_soc_register_card failed\n");
goto fail;
}
fail:
of_node_put(cpu_np);
return ret;
}
static const struct of_device_id imx_hdmi_dt_ids[] = {
{ .compatible = "fsl,imx-audio-hdmi", },
{ .compatible = "fsl,imx-audio-sii902x", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx_hdmi_dt_ids);
static struct platform_driver imx_hdmi_driver = {
.driver = {
.name = "imx-hdmi",
.pm = &snd_soc_pm_ops,
.of_match_table = imx_hdmi_dt_ids,
},
.probe = imx_hdmi_probe,
};
module_platform_driver(imx_hdmi_driver);
MODULE_AUTHOR("Freescale Semiconductor, Inc.");
MODULE_DESCRIPTION("Freescale i.MX hdmi audio ASoC machine driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:imx-hdmi");
| linux-master | sound/soc/fsl/imx-hdmi.c |
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
// Copyright 2018 NXP
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/kobject.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/sysfs.h>
#include <linux/types.h>
#include <linux/dma/imx-dma.h>
#include <sound/dmaengine_pcm.h>
#include <sound/pcm.h>
#include <sound/soc.h>
#include <sound/tlv.h>
#include <sound/core.h>
#include "fsl_micfil.h"
#include "fsl_utils.h"
#define MICFIL_OSR_DEFAULT 16
enum quality {
QUALITY_HIGH,
QUALITY_MEDIUM,
QUALITY_LOW,
QUALITY_VLOW0,
QUALITY_VLOW1,
QUALITY_VLOW2,
};
struct fsl_micfil {
struct platform_device *pdev;
struct regmap *regmap;
const struct fsl_micfil_soc_data *soc;
struct clk *busclk;
struct clk *mclk;
struct clk *pll8k_clk;
struct clk *pll11k_clk;
struct snd_dmaengine_dai_dma_data dma_params_rx;
struct sdma_peripheral_config sdmacfg;
struct snd_soc_card *card;
unsigned int dataline;
char name[32];
int irq[MICFIL_IRQ_LINES];
enum quality quality;
int dc_remover;
int vad_init_mode;
int vad_enabled;
int vad_detected;
struct fsl_micfil_verid verid;
struct fsl_micfil_param param;
};
struct fsl_micfil_soc_data {
unsigned int fifos;
unsigned int fifo_depth;
unsigned int dataline;
bool imx;
bool use_edma;
bool use_verid;
u64 formats;
};
static struct fsl_micfil_soc_data fsl_micfil_imx8mm = {
.imx = true,
.fifos = 8,
.fifo_depth = 8,
.dataline = 0xf,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
};
static struct fsl_micfil_soc_data fsl_micfil_imx8mp = {
.imx = true,
.fifos = 8,
.fifo_depth = 32,
.dataline = 0xf,
.formats = SNDRV_PCM_FMTBIT_S32_LE,
};
static struct fsl_micfil_soc_data fsl_micfil_imx93 = {
.imx = true,
.fifos = 8,
.fifo_depth = 32,
.dataline = 0xf,
.formats = SNDRV_PCM_FMTBIT_S32_LE,
.use_edma = true,
.use_verid = true,
};
static const struct of_device_id fsl_micfil_dt_ids[] = {
{ .compatible = "fsl,imx8mm-micfil", .data = &fsl_micfil_imx8mm },
{ .compatible = "fsl,imx8mp-micfil", .data = &fsl_micfil_imx8mp },
{ .compatible = "fsl,imx93-micfil", .data = &fsl_micfil_imx93 },
{}
};
MODULE_DEVICE_TABLE(of, fsl_micfil_dt_ids);
static const char * const micfil_quality_select_texts[] = {
[QUALITY_HIGH] = "High",
[QUALITY_MEDIUM] = "Medium",
[QUALITY_LOW] = "Low",
[QUALITY_VLOW0] = "VLow0",
[QUALITY_VLOW1] = "Vlow1",
[QUALITY_VLOW2] = "Vlow2",
};
static const struct soc_enum fsl_micfil_quality_enum =
SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_quality_select_texts),
micfil_quality_select_texts);
static DECLARE_TLV_DB_SCALE(gain_tlv, 0, 100, 0);
static int micfil_set_quality(struct fsl_micfil *micfil)
{
u32 qsel;
switch (micfil->quality) {
case QUALITY_HIGH:
qsel = MICFIL_QSEL_HIGH_QUALITY;
break;
case QUALITY_MEDIUM:
qsel = MICFIL_QSEL_MEDIUM_QUALITY;
break;
case QUALITY_LOW:
qsel = MICFIL_QSEL_LOW_QUALITY;
break;
case QUALITY_VLOW0:
qsel = MICFIL_QSEL_VLOW0_QUALITY;
break;
case QUALITY_VLOW1:
qsel = MICFIL_QSEL_VLOW1_QUALITY;
break;
case QUALITY_VLOW2:
qsel = MICFIL_QSEL_VLOW2_QUALITY;
break;
}
return regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
MICFIL_CTRL2_QSEL,
FIELD_PREP(MICFIL_CTRL2_QSEL, qsel));
}
static int micfil_quality_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt);
ucontrol->value.integer.value[0] = micfil->quality;
return 0;
}
static int micfil_quality_set(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt);
micfil->quality = ucontrol->value.integer.value[0];
return micfil_set_quality(micfil);
}
static const char * const micfil_hwvad_enable[] = {
"Disable (Record only)",
"Enable (Record with Vad)",
};
static const char * const micfil_hwvad_init_mode[] = {
"Envelope mode", "Energy mode",
};
static const char * const micfil_hwvad_hpf_texts[] = {
"Filter bypass",
"Cut-off @1750Hz",
"Cut-off @215Hz",
"Cut-off @102Hz",
};
/*
* DC Remover Control
* Filter Bypassed 1 1
* Cut-off @21Hz 0 0
* Cut-off @83Hz 0 1
* Cut-off @152HZ 1 0
*/
static const char * const micfil_dc_remover_texts[] = {
"Cut-off @21Hz", "Cut-off @83Hz",
"Cut-off @152Hz", "Bypass",
};
static const struct soc_enum hwvad_enable_enum =
SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_hwvad_enable),
micfil_hwvad_enable);
static const struct soc_enum hwvad_init_mode_enum =
SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_hwvad_init_mode),
micfil_hwvad_init_mode);
static const struct soc_enum hwvad_hpf_enum =
SOC_ENUM_SINGLE(REG_MICFIL_VAD0_CTRL2, 0,
ARRAY_SIZE(micfil_hwvad_hpf_texts),
micfil_hwvad_hpf_texts);
static const struct soc_enum fsl_micfil_dc_remover_enum =
SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_dc_remover_texts),
micfil_dc_remover_texts);
static int micfil_put_dc_remover_state(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
unsigned int *item = ucontrol->value.enumerated.item;
int val = snd_soc_enum_item_to_val(e, item[0]);
int i = 0, ret = 0;
u32 reg_val = 0;
if (val < 0 || val > 3)
return -EINVAL;
micfil->dc_remover = val;
/* Calculate total value for all channels */
for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++)
reg_val |= val << MICFIL_DC_CHX_SHIFT(i);
/* Update DC Remover mode for all channels */
ret = snd_soc_component_update_bits(comp, REG_MICFIL_DC_CTRL,
MICFIL_DC_CTRL_CONFIG, reg_val);
if (ret < 0)
return ret;
return 0;
}
static int micfil_get_dc_remover_state(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
ucontrol->value.enumerated.item[0] = micfil->dc_remover;
return 0;
}
static int hwvad_put_enable(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned int *item = ucontrol->value.enumerated.item;
struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
int val = snd_soc_enum_item_to_val(e, item[0]);
micfil->vad_enabled = val;
return 0;
}
static int hwvad_get_enable(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
ucontrol->value.enumerated.item[0] = micfil->vad_enabled;
return 0;
}
static int hwvad_put_init_mode(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
unsigned int *item = ucontrol->value.enumerated.item;
struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
int val = snd_soc_enum_item_to_val(e, item[0]);
/* 0 - Envelope-based Mode
* 1 - Energy-based Mode
*/
micfil->vad_init_mode = val;
return 0;
}
static int hwvad_get_init_mode(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
ucontrol->value.enumerated.item[0] = micfil->vad_init_mode;
return 0;
}
static int hwvad_detected(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
ucontrol->value.enumerated.item[0] = micfil->vad_detected;
return 0;
}
static const struct snd_kcontrol_new fsl_micfil_snd_controls[] = {
SOC_SINGLE_SX_TLV("CH0 Volume", REG_MICFIL_OUT_CTRL,
MICFIL_OUTGAIN_CHX_SHIFT(0), 0x8, 0xF, gain_tlv),
SOC_SINGLE_SX_TLV("CH1 Volume", REG_MICFIL_OUT_CTRL,
MICFIL_OUTGAIN_CHX_SHIFT(1), 0x8, 0xF, gain_tlv),
SOC_SINGLE_SX_TLV("CH2 Volume", REG_MICFIL_OUT_CTRL,
MICFIL_OUTGAIN_CHX_SHIFT(2), 0x8, 0xF, gain_tlv),
SOC_SINGLE_SX_TLV("CH3 Volume", REG_MICFIL_OUT_CTRL,
MICFIL_OUTGAIN_CHX_SHIFT(3), 0x8, 0xF, gain_tlv),
SOC_SINGLE_SX_TLV("CH4 Volume", REG_MICFIL_OUT_CTRL,
MICFIL_OUTGAIN_CHX_SHIFT(4), 0x8, 0xF, gain_tlv),
SOC_SINGLE_SX_TLV("CH5 Volume", REG_MICFIL_OUT_CTRL,
MICFIL_OUTGAIN_CHX_SHIFT(5), 0x8, 0xF, gain_tlv),
SOC_SINGLE_SX_TLV("CH6 Volume", REG_MICFIL_OUT_CTRL,
MICFIL_OUTGAIN_CHX_SHIFT(6), 0x8, 0xF, gain_tlv),
SOC_SINGLE_SX_TLV("CH7 Volume", REG_MICFIL_OUT_CTRL,
MICFIL_OUTGAIN_CHX_SHIFT(7), 0x8, 0xF, gain_tlv),
SOC_ENUM_EXT("MICFIL Quality Select",
fsl_micfil_quality_enum,
micfil_quality_get, micfil_quality_set),
SOC_ENUM_EXT("HWVAD Enablement Switch", hwvad_enable_enum,
hwvad_get_enable, hwvad_put_enable),
SOC_ENUM_EXT("HWVAD Initialization Mode", hwvad_init_mode_enum,
hwvad_get_init_mode, hwvad_put_init_mode),
SOC_ENUM("HWVAD High-Pass Filter", hwvad_hpf_enum),
SOC_SINGLE("HWVAD ZCD Switch", REG_MICFIL_VAD0_ZCD, 0, 1, 0),
SOC_SINGLE("HWVAD ZCD Auto Threshold Switch",
REG_MICFIL_VAD0_ZCD, 2, 1, 0),
SOC_ENUM_EXT("MICFIL DC Remover Control", fsl_micfil_dc_remover_enum,
micfil_get_dc_remover_state, micfil_put_dc_remover_state),
SOC_SINGLE("HWVAD Input Gain", REG_MICFIL_VAD0_CTRL2, 8, 15, 0),
SOC_SINGLE("HWVAD Sound Gain", REG_MICFIL_VAD0_SCONFIG, 0, 15, 0),
SOC_SINGLE("HWVAD Noise Gain", REG_MICFIL_VAD0_NCONFIG, 0, 15, 0),
SOC_SINGLE_RANGE("HWVAD Detector Frame Time", REG_MICFIL_VAD0_CTRL2, 16, 0, 63, 0),
SOC_SINGLE("HWVAD Detector Initialization Time", REG_MICFIL_VAD0_CTRL1, 8, 31, 0),
SOC_SINGLE("HWVAD Noise Filter Adjustment", REG_MICFIL_VAD0_NCONFIG, 8, 31, 0),
SOC_SINGLE("HWVAD ZCD Threshold", REG_MICFIL_VAD0_ZCD, 16, 1023, 0),
SOC_SINGLE("HWVAD ZCD Adjustment", REG_MICFIL_VAD0_ZCD, 8, 15, 0),
SOC_SINGLE("HWVAD ZCD And Behavior Switch",
REG_MICFIL_VAD0_ZCD, 4, 1, 0),
SOC_SINGLE_BOOL_EXT("VAD Detected", 0, hwvad_detected, NULL),
};
static int fsl_micfil_use_verid(struct device *dev)
{
struct fsl_micfil *micfil = dev_get_drvdata(dev);
unsigned int val;
int ret;
if (!micfil->soc->use_verid)
return 0;
ret = regmap_read(micfil->regmap, REG_MICFIL_VERID, &val);
if (ret < 0)
return ret;
dev_dbg(dev, "VERID: 0x%016X\n", val);
micfil->verid.version = val &
(MICFIL_VERID_MAJOR_MASK | MICFIL_VERID_MINOR_MASK);
micfil->verid.version >>= MICFIL_VERID_MINOR_SHIFT;
micfil->verid.feature = val & MICFIL_VERID_FEATURE_MASK;
ret = regmap_read(micfil->regmap, REG_MICFIL_PARAM, &val);
if (ret < 0)
return ret;
dev_dbg(dev, "PARAM: 0x%016X\n", val);
micfil->param.hwvad_num = (val & MICFIL_PARAM_NUM_HWVAD_MASK) >>
MICFIL_PARAM_NUM_HWVAD_SHIFT;
micfil->param.hwvad_zcd = val & MICFIL_PARAM_HWVAD_ZCD;
micfil->param.hwvad_energy_mode = val & MICFIL_PARAM_HWVAD_ENERGY_MODE;
micfil->param.hwvad = val & MICFIL_PARAM_HWVAD;
micfil->param.dc_out_bypass = val & MICFIL_PARAM_DC_OUT_BYPASS;
micfil->param.dc_in_bypass = val & MICFIL_PARAM_DC_IN_BYPASS;
micfil->param.low_power = val & MICFIL_PARAM_LOW_POWER;
micfil->param.fil_out_width = val & MICFIL_PARAM_FIL_OUT_WIDTH;
micfil->param.fifo_ptrwid = (val & MICFIL_PARAM_FIFO_PTRWID_MASK) >>
MICFIL_PARAM_FIFO_PTRWID_SHIFT;
micfil->param.npair = (val & MICFIL_PARAM_NPAIR_MASK) >>
MICFIL_PARAM_NPAIR_SHIFT;
return 0;
}
/* The SRES is a self-negated bit which provides the CPU with the
* capability to initialize the PDM Interface module through the
* slave-bus interface. This bit always reads as zero, and this
* bit is only effective when MDIS is cleared
*/
static int fsl_micfil_reset(struct device *dev)
{
struct fsl_micfil *micfil = dev_get_drvdata(dev);
int ret;
ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
MICFIL_CTRL1_MDIS);
if (ret)
return ret;
ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1,
MICFIL_CTRL1_SRES);
if (ret)
return ret;
/*
* SRES is self-cleared bit, but REG_MICFIL_CTRL1 is defined
* as non-volatile register, so SRES still remain in regmap
* cache after set, that every update of REG_MICFIL_CTRL1,
* software reset happens. so clear it explicitly.
*/
ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
MICFIL_CTRL1_SRES);
if (ret)
return ret;
/*
* Set SRES should clear CHnF flags, But even add delay here
* the CHnF may not be cleared sometimes, so clear CHnF explicitly.
*/
ret = regmap_write_bits(micfil->regmap, REG_MICFIL_STAT, 0xFF, 0xFF);
if (ret)
return ret;
return 0;
}
static int fsl_micfil_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
if (!micfil) {
dev_err(dai->dev, "micfil dai priv_data not set\n");
return -EINVAL;
}
return 0;
}
/* Enable/disable hwvad interrupts */
static int fsl_micfil_configure_hwvad_interrupts(struct fsl_micfil *micfil, int enable)
{
u32 vadie_reg = enable ? MICFIL_VAD0_CTRL1_IE : 0;
u32 vaderie_reg = enable ? MICFIL_VAD0_CTRL1_ERIE : 0;
/* Voice Activity Detector Error Interruption */
regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
MICFIL_VAD0_CTRL1_ERIE, vaderie_reg);
/* Voice Activity Detector Interruption */
regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
MICFIL_VAD0_CTRL1_IE, vadie_reg);
return 0;
}
/* Configuration done only in energy-based initialization mode */
static int fsl_micfil_init_hwvad_energy_mode(struct fsl_micfil *micfil)
{
/* Keep the VADFRENDIS bitfield cleared. */
regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2,
MICFIL_VAD0_CTRL2_FRENDIS);
/* Keep the VADPREFEN bitfield cleared. */
regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2,
MICFIL_VAD0_CTRL2_PREFEN);
/* Keep the VADSFILEN bitfield cleared. */
regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG,
MICFIL_VAD0_SCONFIG_SFILEN);
/* Keep the VADSMAXEN bitfield cleared. */
regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG,
MICFIL_VAD0_SCONFIG_SMAXEN);
/* Keep the VADNFILAUTO bitfield asserted. */
regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
MICFIL_VAD0_NCONFIG_NFILAUT);
/* Keep the VADNMINEN bitfield cleared. */
regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
MICFIL_VAD0_NCONFIG_NMINEN);
/* Keep the VADNDECEN bitfield cleared. */
regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
MICFIL_VAD0_NCONFIG_NDECEN);
/* Keep the VADNOREN bitfield cleared. */
regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
MICFIL_VAD0_NCONFIG_NOREN);
return 0;
}
/* Configuration done only in envelope-based initialization mode */
static int fsl_micfil_init_hwvad_envelope_mode(struct fsl_micfil *micfil)
{
/* Assert the VADFRENDIS bitfield */
regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2,
MICFIL_VAD0_CTRL2_FRENDIS);
/* Assert the VADPREFEN bitfield. */
regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2,
MICFIL_VAD0_CTRL2_PREFEN);
/* Assert the VADSFILEN bitfield. */
regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG,
MICFIL_VAD0_SCONFIG_SFILEN);
/* Assert the VADSMAXEN bitfield. */
regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG,
MICFIL_VAD0_SCONFIG_SMAXEN);
/* Clear the VADNFILAUTO bitfield */
regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
MICFIL_VAD0_NCONFIG_NFILAUT);
/* Assert the VADNMINEN bitfield. */
regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
MICFIL_VAD0_NCONFIG_NMINEN);
/* Assert the VADNDECEN bitfield. */
regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
MICFIL_VAD0_NCONFIG_NDECEN);
/* Assert VADNOREN bitfield. */
regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,
MICFIL_VAD0_NCONFIG_NOREN);
return 0;
}
/*
* Hardware Voice Active Detection: The HWVAD takes data from the input
* of a selected PDM microphone to detect if there is any
* voice activity. When a voice activity is detected, an interrupt could
* be delivered to the system. Initialization in section 8.4:
* Can work in two modes:
* -> Eneveope-based mode (section 8.4.1)
* -> Energy-based mode (section 8.4.2)
*
* It is important to remark that the HWVAD detector could be enabled
* or reset only when the MICFIL isn't running i.e. when the BSY_FIL
* bit in STAT register is cleared
*/
static int fsl_micfil_hwvad_enable(struct fsl_micfil *micfil)
{
int ret;
micfil->vad_detected = 0;
/* envelope-based specific initialization */
if (micfil->vad_init_mode == MICFIL_HWVAD_ENVELOPE_MODE)
ret = fsl_micfil_init_hwvad_envelope_mode(micfil);
else
ret = fsl_micfil_init_hwvad_energy_mode(micfil);
if (ret)
return ret;
/* Voice Activity Detector Internal Filters Initialization*/
regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
MICFIL_VAD0_CTRL1_ST10);
/* Voice Activity Detector Internal Filter */
regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
MICFIL_VAD0_CTRL1_ST10);
/* Enable Interrupts */
ret = fsl_micfil_configure_hwvad_interrupts(micfil, 1);
if (ret)
return ret;
/* Voice Activity Detector Reset */
regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
MICFIL_VAD0_CTRL1_RST);
/* Voice Activity Detector Enabled */
regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
MICFIL_VAD0_CTRL1_EN);
return 0;
}
static int fsl_micfil_hwvad_disable(struct fsl_micfil *micfil)
{
struct device *dev = &micfil->pdev->dev;
int ret = 0;
/* Disable HWVAD */
regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
MICFIL_VAD0_CTRL1_EN);
/* Disable hwvad interrupts */
ret = fsl_micfil_configure_hwvad_interrupts(micfil, 0);
if (ret)
dev_err(dev, "Failed to disable interrupts\n");
return ret;
}
static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
struct device *dev = &micfil->pdev->dev;
int ret;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
ret = fsl_micfil_reset(dev);
if (ret) {
dev_err(dev, "failed to soft reset\n");
return ret;
}
/* DMA Interrupt Selection - DISEL bits
* 00 - DMA and IRQ disabled
* 01 - DMA req enabled
* 10 - IRQ enabled
* 11 - reserved
*/
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
MICFIL_CTRL1_DISEL,
FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DMA));
if (ret)
return ret;
/* Enable the module */
ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1,
MICFIL_CTRL1_PDMIEN);
if (ret)
return ret;
if (micfil->vad_enabled)
fsl_micfil_hwvad_enable(micfil);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
if (micfil->vad_enabled)
fsl_micfil_hwvad_disable(micfil);
/* Disable the module */
ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
MICFIL_CTRL1_PDMIEN);
if (ret)
return ret;
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
MICFIL_CTRL1_DISEL,
FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DISABLE));
if (ret)
return ret;
break;
default:
return -EINVAL;
}
return 0;
}
static int fsl_micfil_reparent_rootclk(struct fsl_micfil *micfil, unsigned int sample_rate)
{
struct device *dev = &micfil->pdev->dev;
u64 ratio = sample_rate;
struct clk *clk;
int ret;
/* Get root clock */
clk = micfil->mclk;
/* Disable clock first, for it was enabled by pm_runtime */
clk_disable_unprepare(clk);
fsl_asoc_reparent_pll_clocks(dev, clk, micfil->pll8k_clk,
micfil->pll11k_clk, ratio);
ret = clk_prepare_enable(clk);
if (ret)
return ret;
return 0;
}
static int fsl_micfil_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
unsigned int channels = params_channels(params);
unsigned int rate = params_rate(params);
int clk_div = 8;
int osr = MICFIL_OSR_DEFAULT;
int ret;
/* 1. Disable the module */
ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
MICFIL_CTRL1_PDMIEN);
if (ret)
return ret;
/* enable channels */
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
0xFF, ((1 << channels) - 1));
if (ret)
return ret;
ret = fsl_micfil_reparent_rootclk(micfil, rate);
if (ret)
return ret;
ret = clk_set_rate(micfil->mclk, rate * clk_div * osr * 8);
if (ret)
return ret;
ret = micfil_set_quality(micfil);
if (ret)
return ret;
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
MICFIL_CTRL2_CLKDIV | MICFIL_CTRL2_CICOSR,
FIELD_PREP(MICFIL_CTRL2_CLKDIV, clk_div) |
FIELD_PREP(MICFIL_CTRL2_CICOSR, 16 - osr));
/* Configure CIC OSR in VADCICOSR */
regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
MICFIL_VAD0_CTRL1_CICOSR,
FIELD_PREP(MICFIL_VAD0_CTRL1_CICOSR, 16 - osr));
/* Configure source channel in VADCHSEL */
regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,
MICFIL_VAD0_CTRL1_CHSEL,
FIELD_PREP(MICFIL_VAD0_CTRL1_CHSEL, (channels - 1)));
micfil->dma_params_rx.peripheral_config = &micfil->sdmacfg;
micfil->dma_params_rx.peripheral_size = sizeof(micfil->sdmacfg);
micfil->sdmacfg.n_fifos_src = channels;
micfil->sdmacfg.sw_done = true;
micfil->dma_params_rx.maxburst = channels * MICFIL_DMA_MAXBURST_RX;
if (micfil->soc->use_edma)
micfil->dma_params_rx.maxburst = channels;
return 0;
}
static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai)
{
struct fsl_micfil *micfil = dev_get_drvdata(cpu_dai->dev);
struct device *dev = cpu_dai->dev;
unsigned int val = 0;
int ret, i;
micfil->quality = QUALITY_VLOW0;
micfil->card = cpu_dai->component->card;
/* set default gain to 2 */
regmap_write(micfil->regmap, REG_MICFIL_OUT_CTRL, 0x22222222);
/* set DC Remover in bypass mode*/
for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++)
val |= MICFIL_DC_BYPASS << MICFIL_DC_CHX_SHIFT(i);
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_DC_CTRL,
MICFIL_DC_CTRL_CONFIG, val);
if (ret) {
dev_err(dev, "failed to set DC Remover mode bits\n");
return ret;
}
micfil->dc_remover = MICFIL_DC_BYPASS;
snd_soc_dai_init_dma_data(cpu_dai, NULL,
&micfil->dma_params_rx);
/* FIFO Watermark Control - FIFOWMK*/
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_FIFO_CTRL,
MICFIL_FIFO_CTRL_FIFOWMK,
FIELD_PREP(MICFIL_FIFO_CTRL_FIFOWMK, micfil->soc->fifo_depth - 1));
if (ret)
return ret;
return 0;
}
static const struct snd_soc_dai_ops fsl_micfil_dai_ops = {
.probe = fsl_micfil_dai_probe,
.startup = fsl_micfil_startup,
.trigger = fsl_micfil_trigger,
.hw_params = fsl_micfil_hw_params,
};
static struct snd_soc_dai_driver fsl_micfil_dai = {
.capture = {
.stream_name = "CPU-Capture",
.channels_min = 1,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.ops = &fsl_micfil_dai_ops,
};
static const struct snd_soc_component_driver fsl_micfil_component = {
.name = "fsl-micfil-dai",
.controls = fsl_micfil_snd_controls,
.num_controls = ARRAY_SIZE(fsl_micfil_snd_controls),
.legacy_dai_naming = 1,
};
/* REGMAP */
static const struct reg_default fsl_micfil_reg_defaults[] = {
{REG_MICFIL_CTRL1, 0x00000000},
{REG_MICFIL_CTRL2, 0x00000000},
{REG_MICFIL_STAT, 0x00000000},
{REG_MICFIL_FIFO_CTRL, 0x00000007},
{REG_MICFIL_FIFO_STAT, 0x00000000},
{REG_MICFIL_DATACH0, 0x00000000},
{REG_MICFIL_DATACH1, 0x00000000},
{REG_MICFIL_DATACH2, 0x00000000},
{REG_MICFIL_DATACH3, 0x00000000},
{REG_MICFIL_DATACH4, 0x00000000},
{REG_MICFIL_DATACH5, 0x00000000},
{REG_MICFIL_DATACH6, 0x00000000},
{REG_MICFIL_DATACH7, 0x00000000},
{REG_MICFIL_DC_CTRL, 0x00000000},
{REG_MICFIL_OUT_CTRL, 0x00000000},
{REG_MICFIL_OUT_STAT, 0x00000000},
{REG_MICFIL_VAD0_CTRL1, 0x00000000},
{REG_MICFIL_VAD0_CTRL2, 0x000A0000},
{REG_MICFIL_VAD0_STAT, 0x00000000},
{REG_MICFIL_VAD0_SCONFIG, 0x00000000},
{REG_MICFIL_VAD0_NCONFIG, 0x80000000},
{REG_MICFIL_VAD0_NDATA, 0x00000000},
{REG_MICFIL_VAD0_ZCD, 0x00000004},
};
static bool fsl_micfil_readable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case REG_MICFIL_CTRL1:
case REG_MICFIL_CTRL2:
case REG_MICFIL_STAT:
case REG_MICFIL_FIFO_CTRL:
case REG_MICFIL_FIFO_STAT:
case REG_MICFIL_DATACH0:
case REG_MICFIL_DATACH1:
case REG_MICFIL_DATACH2:
case REG_MICFIL_DATACH3:
case REG_MICFIL_DATACH4:
case REG_MICFIL_DATACH5:
case REG_MICFIL_DATACH6:
case REG_MICFIL_DATACH7:
case REG_MICFIL_DC_CTRL:
case REG_MICFIL_OUT_CTRL:
case REG_MICFIL_OUT_STAT:
case REG_MICFIL_FSYNC_CTRL:
case REG_MICFIL_VERID:
case REG_MICFIL_PARAM:
case REG_MICFIL_VAD0_CTRL1:
case REG_MICFIL_VAD0_CTRL2:
case REG_MICFIL_VAD0_STAT:
case REG_MICFIL_VAD0_SCONFIG:
case REG_MICFIL_VAD0_NCONFIG:
case REG_MICFIL_VAD0_NDATA:
case REG_MICFIL_VAD0_ZCD:
return true;
default:
return false;
}
}
static bool fsl_micfil_writeable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case REG_MICFIL_CTRL1:
case REG_MICFIL_CTRL2:
case REG_MICFIL_STAT: /* Write 1 to Clear */
case REG_MICFIL_FIFO_CTRL:
case REG_MICFIL_FIFO_STAT: /* Write 1 to Clear */
case REG_MICFIL_DC_CTRL:
case REG_MICFIL_OUT_CTRL:
case REG_MICFIL_OUT_STAT: /* Write 1 to Clear */
case REG_MICFIL_FSYNC_CTRL:
case REG_MICFIL_VAD0_CTRL1:
case REG_MICFIL_VAD0_CTRL2:
case REG_MICFIL_VAD0_STAT: /* Write 1 to Clear */
case REG_MICFIL_VAD0_SCONFIG:
case REG_MICFIL_VAD0_NCONFIG:
case REG_MICFIL_VAD0_ZCD:
return true;
default:
return false;
}
}
static bool fsl_micfil_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case REG_MICFIL_STAT:
case REG_MICFIL_DATACH0:
case REG_MICFIL_DATACH1:
case REG_MICFIL_DATACH2:
case REG_MICFIL_DATACH3:
case REG_MICFIL_DATACH4:
case REG_MICFIL_DATACH5:
case REG_MICFIL_DATACH6:
case REG_MICFIL_DATACH7:
case REG_MICFIL_VERID:
case REG_MICFIL_PARAM:
case REG_MICFIL_VAD0_STAT:
case REG_MICFIL_VAD0_NDATA:
return true;
default:
return false;
}
}
static const struct regmap_config fsl_micfil_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = REG_MICFIL_VAD0_ZCD,
.reg_defaults = fsl_micfil_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(fsl_micfil_reg_defaults),
.readable_reg = fsl_micfil_readable_reg,
.volatile_reg = fsl_micfil_volatile_reg,
.writeable_reg = fsl_micfil_writeable_reg,
.cache_type = REGCACHE_RBTREE,
};
/* END OF REGMAP */
static irqreturn_t micfil_isr(int irq, void *devid)
{
struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
struct platform_device *pdev = micfil->pdev;
u32 stat_reg;
u32 fifo_stat_reg;
u32 ctrl1_reg;
bool dma_enabled;
int i;
regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg);
regmap_read(micfil->regmap, REG_MICFIL_CTRL1, &ctrl1_reg);
regmap_read(micfil->regmap, REG_MICFIL_FIFO_STAT, &fifo_stat_reg);
dma_enabled = FIELD_GET(MICFIL_CTRL1_DISEL, ctrl1_reg) == MICFIL_CTRL1_DISEL_DMA;
/* Channel 0-7 Output Data Flags */
for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) {
if (stat_reg & MICFIL_STAT_CHXF(i))
dev_dbg(&pdev->dev,
"Data available in Data Channel %d\n", i);
/* if DMA is not enabled, field must be written with 1
* to clear
*/
if (!dma_enabled)
regmap_write_bits(micfil->regmap,
REG_MICFIL_STAT,
MICFIL_STAT_CHXF(i),
1);
}
for (i = 0; i < MICFIL_FIFO_NUM; i++) {
if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_OVER(i))
dev_dbg(&pdev->dev,
"FIFO Overflow Exception flag for channel %d\n",
i);
if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_UNDER(i))
dev_dbg(&pdev->dev,
"FIFO Underflow Exception flag for channel %d\n",
i);
}
return IRQ_HANDLED;
}
static irqreturn_t micfil_err_isr(int irq, void *devid)
{
struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
struct platform_device *pdev = micfil->pdev;
u32 stat_reg;
regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg);
if (stat_reg & MICFIL_STAT_BSY_FIL)
dev_dbg(&pdev->dev, "isr: Decimation Filter is running\n");
if (stat_reg & MICFIL_STAT_FIR_RDY)
dev_dbg(&pdev->dev, "isr: FIR Filter Data ready\n");
if (stat_reg & MICFIL_STAT_LOWFREQF) {
dev_dbg(&pdev->dev, "isr: ipg_clk_app is too low\n");
regmap_write_bits(micfil->regmap, REG_MICFIL_STAT,
MICFIL_STAT_LOWFREQF, 1);
}
return IRQ_HANDLED;
}
static irqreturn_t voice_detected_fn(int irq, void *devid)
{
struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
struct snd_kcontrol *kctl;
if (!micfil->card)
return IRQ_HANDLED;
kctl = snd_soc_card_get_kcontrol(micfil->card, "VAD Detected");
if (!kctl)
return IRQ_HANDLED;
if (micfil->vad_detected)
snd_ctl_notify(micfil->card->snd_card,
SNDRV_CTL_EVENT_MASK_VALUE,
&kctl->id);
return IRQ_HANDLED;
}
static irqreturn_t hwvad_isr(int irq, void *devid)
{
struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
struct device *dev = &micfil->pdev->dev;
u32 vad0_reg;
int ret;
regmap_read(micfil->regmap, REG_MICFIL_VAD0_STAT, &vad0_reg);
/*
* The only difference between MICFIL_VAD0_STAT_EF and
* MICFIL_VAD0_STAT_IF is that the former requires Write
* 1 to Clear. Since both flags are set, it is enough
* to only read one of them
*/
if (vad0_reg & MICFIL_VAD0_STAT_IF) {
/* Write 1 to clear */
regmap_write_bits(micfil->regmap, REG_MICFIL_VAD0_STAT,
MICFIL_VAD0_STAT_IF,
MICFIL_VAD0_STAT_IF);
micfil->vad_detected = 1;
}
ret = fsl_micfil_hwvad_disable(micfil);
if (ret)
dev_err(dev, "Failed to disable hwvad\n");
return IRQ_WAKE_THREAD;
}
static irqreturn_t hwvad_err_isr(int irq, void *devid)
{
struct fsl_micfil *micfil = (struct fsl_micfil *)devid;
struct device *dev = &micfil->pdev->dev;
u32 vad0_reg;
regmap_read(micfil->regmap, REG_MICFIL_VAD0_STAT, &vad0_reg);
if (vad0_reg & MICFIL_VAD0_STAT_INSATF)
dev_dbg(dev, "voice activity input overflow/underflow detected\n");
return IRQ_HANDLED;
}
static int fsl_micfil_runtime_suspend(struct device *dev);
static int fsl_micfil_runtime_resume(struct device *dev);
static int fsl_micfil_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct fsl_micfil *micfil;
struct resource *res;
void __iomem *regs;
int ret, i;
micfil = devm_kzalloc(&pdev->dev, sizeof(*micfil), GFP_KERNEL);
if (!micfil)
return -ENOMEM;
micfil->pdev = pdev;
strscpy(micfil->name, np->name, sizeof(micfil->name));
micfil->soc = of_device_get_match_data(&pdev->dev);
/* ipg_clk is used to control the registers
* ipg_clk_app is used to operate the filter
*/
micfil->mclk = devm_clk_get(&pdev->dev, "ipg_clk_app");
if (IS_ERR(micfil->mclk)) {
dev_err(&pdev->dev, "failed to get core clock: %ld\n",
PTR_ERR(micfil->mclk));
return PTR_ERR(micfil->mclk);
}
micfil->busclk = devm_clk_get(&pdev->dev, "ipg_clk");
if (IS_ERR(micfil->busclk)) {
dev_err(&pdev->dev, "failed to get ipg clock: %ld\n",
PTR_ERR(micfil->busclk));
return PTR_ERR(micfil->busclk);
}
fsl_asoc_get_pll_clocks(&pdev->dev, &micfil->pll8k_clk,
&micfil->pll11k_clk);
/* init regmap */
regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(regs))
return PTR_ERR(regs);
micfil->regmap = devm_regmap_init_mmio(&pdev->dev,
regs,
&fsl_micfil_regmap_config);
if (IS_ERR(micfil->regmap)) {
dev_err(&pdev->dev, "failed to init MICFIL regmap: %ld\n",
PTR_ERR(micfil->regmap));
return PTR_ERR(micfil->regmap);
}
/* dataline mask for RX */
ret = of_property_read_u32_index(np,
"fsl,dataline",
0,
&micfil->dataline);
if (ret)
micfil->dataline = 1;
if (micfil->dataline & ~micfil->soc->dataline) {
dev_err(&pdev->dev, "dataline setting error, Mask is 0x%X\n",
micfil->soc->dataline);
return -EINVAL;
}
/* get IRQs */
for (i = 0; i < MICFIL_IRQ_LINES; i++) {
micfil->irq[i] = platform_get_irq(pdev, i);
if (micfil->irq[i] < 0)
return micfil->irq[i];
}
/* Digital Microphone interface interrupt */
ret = devm_request_irq(&pdev->dev, micfil->irq[0],
micfil_isr, IRQF_SHARED,
micfil->name, micfil);
if (ret) {
dev_err(&pdev->dev, "failed to claim mic interface irq %u\n",
micfil->irq[0]);
return ret;
}
/* Digital Microphone interface error interrupt */
ret = devm_request_irq(&pdev->dev, micfil->irq[1],
micfil_err_isr, IRQF_SHARED,
micfil->name, micfil);
if (ret) {
dev_err(&pdev->dev, "failed to claim mic interface error irq %u\n",
micfil->irq[1]);
return ret;
}
/* Digital Microphone interface voice activity detector event */
ret = devm_request_threaded_irq(&pdev->dev, micfil->irq[2],
hwvad_isr, voice_detected_fn,
IRQF_SHARED, micfil->name, micfil);
if (ret) {
dev_err(&pdev->dev, "failed to claim hwvad event irq %u\n",
micfil->irq[0]);
return ret;
}
/* Digital Microphone interface voice activity detector error */
ret = devm_request_irq(&pdev->dev, micfil->irq[3],
hwvad_err_isr, IRQF_SHARED,
micfil->name, micfil);
if (ret) {
dev_err(&pdev->dev, "failed to claim hwvad error irq %u\n",
micfil->irq[1]);
return ret;
}
micfil->dma_params_rx.chan_name = "rx";
micfil->dma_params_rx.addr = res->start + REG_MICFIL_DATACH0;
micfil->dma_params_rx.maxburst = MICFIL_DMA_MAXBURST_RX;
platform_set_drvdata(pdev, micfil);
pm_runtime_enable(&pdev->dev);
if (!pm_runtime_enabled(&pdev->dev)) {
ret = fsl_micfil_runtime_resume(&pdev->dev);
if (ret)
goto err_pm_disable;
}
ret = pm_runtime_resume_and_get(&pdev->dev);
if (ret < 0)
goto err_pm_get_sync;
/* Get micfil version */
ret = fsl_micfil_use_verid(&pdev->dev);
if (ret < 0)
dev_warn(&pdev->dev, "Error reading MICFIL version: %d\n", ret);
ret = pm_runtime_put_sync(&pdev->dev);
if (ret < 0 && ret != -ENOSYS)
goto err_pm_get_sync;
regcache_cache_only(micfil->regmap, true);
/*
* Register platform component before registering cpu dai for there
* is not defer probe for platform component in snd_soc_add_pcm_runtime().
*/
ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
if (ret) {
dev_err(&pdev->dev, "failed to pcm register\n");
goto err_pm_disable;
}
fsl_micfil_dai.capture.formats = micfil->soc->formats;
ret = devm_snd_soc_register_component(&pdev->dev, &fsl_micfil_component,
&fsl_micfil_dai, 1);
if (ret) {
dev_err(&pdev->dev, "failed to register component %s\n",
fsl_micfil_component.name);
goto err_pm_disable;
}
return ret;
err_pm_get_sync:
if (!pm_runtime_status_suspended(&pdev->dev))
fsl_micfil_runtime_suspend(&pdev->dev);
err_pm_disable:
pm_runtime_disable(&pdev->dev);
return ret;
}
static void fsl_micfil_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
}
static int fsl_micfil_runtime_suspend(struct device *dev)
{
struct fsl_micfil *micfil = dev_get_drvdata(dev);
regcache_cache_only(micfil->regmap, true);
clk_disable_unprepare(micfil->mclk);
clk_disable_unprepare(micfil->busclk);
return 0;
}
static int fsl_micfil_runtime_resume(struct device *dev)
{
struct fsl_micfil *micfil = dev_get_drvdata(dev);
int ret;
ret = clk_prepare_enable(micfil->busclk);
if (ret < 0)
return ret;
ret = clk_prepare_enable(micfil->mclk);
if (ret < 0) {
clk_disable_unprepare(micfil->busclk);
return ret;
}
regcache_cache_only(micfil->regmap, false);
regcache_mark_dirty(micfil->regmap);
regcache_sync(micfil->regmap);
return 0;
}
static const struct dev_pm_ops fsl_micfil_pm_ops = {
SET_RUNTIME_PM_OPS(fsl_micfil_runtime_suspend,
fsl_micfil_runtime_resume,
NULL)
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
};
static struct platform_driver fsl_micfil_driver = {
.probe = fsl_micfil_probe,
.remove_new = fsl_micfil_remove,
.driver = {
.name = "fsl-micfil-dai",
.pm = &fsl_micfil_pm_ops,
.of_match_table = fsl_micfil_dt_ids,
},
};
module_platform_driver(fsl_micfil_driver);
MODULE_AUTHOR("Cosmin-Gabriel Samoila <[email protected]>");
MODULE_DESCRIPTION("NXP PDM Microphone Interface (MICFIL) driver");
MODULE_LICENSE("Dual BSD/GPL");
| linux-master | sound/soc/fsl/fsl_micfil.c |
// SPDX-License-Identifier: GPL-2.0
//
// Phytec pcm030 driver for the PSC of the Freescale MPC52xx
// configured as AC97 interface
//
// Copyright 2008 Jon Smirl, Digispeaker
// Author: Jon Smirl <[email protected]>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/of_device.h>
#include <linux/of_platform.h>
#include <sound/soc.h>
#include "mpc5200_dma.h"
#define DRV_NAME "pcm030-audio-fabric"
struct pcm030_audio_data {
struct snd_soc_card *card;
struct platform_device *codec_device;
};
SND_SOC_DAILINK_DEFS(analog,
DAILINK_COMP_ARRAY(COMP_CPU("mpc5200-psc-ac97.0")),
DAILINK_COMP_ARRAY(COMP_CODEC("wm9712-codec", "wm9712-hifi")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(iec958,
DAILINK_COMP_ARRAY(COMP_CPU("mpc5200-psc-ac97.1")),
DAILINK_COMP_ARRAY(COMP_CODEC("wm9712-codec", "wm9712-aux")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
static struct snd_soc_dai_link pcm030_fabric_dai[] = {
{
.name = "AC97.0",
.stream_name = "AC97 Analog",
SND_SOC_DAILINK_REG(analog),
},
{
.name = "AC97.1",
.stream_name = "AC97 IEC958",
SND_SOC_DAILINK_REG(iec958),
},
};
static struct snd_soc_card pcm030_card = {
.name = "pcm030",
.owner = THIS_MODULE,
.dai_link = pcm030_fabric_dai,
.num_links = ARRAY_SIZE(pcm030_fabric_dai),
};
static int pcm030_fabric_probe(struct platform_device *op)
{
struct device_node *np = op->dev.of_node;
struct device_node *platform_np;
struct snd_soc_card *card = &pcm030_card;
struct pcm030_audio_data *pdata;
struct snd_soc_dai_link *dai_link;
int ret;
int i;
if (!of_machine_is_compatible("phytec,pcm030"))
return -ENODEV;
pdata = devm_kzalloc(&op->dev, sizeof(struct pcm030_audio_data),
GFP_KERNEL);
if (!pdata)
return -ENOMEM;
card->dev = &op->dev;
pdata->card = card;
platform_np = of_parse_phandle(np, "asoc-platform", 0);
if (!platform_np) {
dev_err(&op->dev, "ac97 not registered\n");
return -ENODEV;
}
for_each_card_prelinks(card, i, dai_link)
dai_link->platforms->of_node = platform_np;
ret = request_module("snd-soc-wm9712");
if (ret)
dev_err(&op->dev, "request_module returned: %d\n", ret);
pdata->codec_device = platform_device_alloc("wm9712-codec", -1);
if (!pdata->codec_device)
dev_err(&op->dev, "platform_device_alloc() failed\n");
ret = platform_device_add(pdata->codec_device);
if (ret) {
dev_err(&op->dev, "platform_device_add() failed: %d\n", ret);
platform_device_put(pdata->codec_device);
}
ret = snd_soc_register_card(card);
if (ret) {
dev_err(&op->dev, "snd_soc_register_card() failed: %d\n", ret);
platform_device_unregister(pdata->codec_device);
}
platform_set_drvdata(op, pdata);
return ret;
}
static void pcm030_fabric_remove(struct platform_device *op)
{
struct pcm030_audio_data *pdata = platform_get_drvdata(op);
snd_soc_unregister_card(pdata->card);
platform_device_unregister(pdata->codec_device);
}
static const struct of_device_id pcm030_audio_match[] = {
{ .compatible = "phytec,pcm030-audio-fabric", },
{}
};
MODULE_DEVICE_TABLE(of, pcm030_audio_match);
static struct platform_driver pcm030_fabric_driver = {
.probe = pcm030_fabric_probe,
.remove_new = pcm030_fabric_remove,
.driver = {
.name = DRV_NAME,
.of_match_table = pcm030_audio_match,
},
};
module_platform_driver(pcm030_fabric_driver);
MODULE_AUTHOR("Jon Smirl <[email protected]>");
MODULE_DESCRIPTION(DRV_NAME ": mpc5200 pcm030 fabric driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/fsl/pcm030-audio-fabric.c |
// SPDX-License-Identifier: GPL-2.0
/*
* ALSA SoC using the QUICC Multichannel Controller (QMC)
*
* Copyright 2022 CS GROUP France
*
* Author: Herve Codina <[email protected]>
*/
#include <linux/dma-mapping.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <soc/fsl/qe/qmc.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
struct qmc_dai {
char *name;
int id;
struct device *dev;
struct qmc_chan *qmc_chan;
unsigned int nb_tx_ts;
unsigned int nb_rx_ts;
};
struct qmc_audio {
struct device *dev;
unsigned int num_dais;
struct qmc_dai *dais;
struct snd_soc_dai_driver *dai_drivers;
};
struct qmc_dai_prtd {
struct qmc_dai *qmc_dai;
dma_addr_t dma_buffer_start;
dma_addr_t period_ptr_submitted;
dma_addr_t period_ptr_ended;
dma_addr_t dma_buffer_end;
size_t period_size;
struct snd_pcm_substream *substream;
};
static int qmc_audio_pcm_construct(struct snd_soc_component *component,
struct snd_soc_pcm_runtime *rtd)
{
struct snd_card *card = rtd->card->snd_card;
int ret;
ret = dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(32));
if (ret)
return ret;
snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV, card->dev,
64*1024, 64*1024);
return 0;
}
static int qmc_audio_pcm_hw_params(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct qmc_dai_prtd *prtd = substream->runtime->private_data;
prtd->dma_buffer_start = runtime->dma_addr;
prtd->dma_buffer_end = runtime->dma_addr + params_buffer_bytes(params);
prtd->period_size = params_period_bytes(params);
prtd->period_ptr_submitted = prtd->dma_buffer_start;
prtd->period_ptr_ended = prtd->dma_buffer_start;
prtd->substream = substream;
return 0;
}
static void qmc_audio_pcm_write_complete(void *context)
{
struct qmc_dai_prtd *prtd = context;
int ret;
prtd->period_ptr_ended += prtd->period_size;
if (prtd->period_ptr_ended >= prtd->dma_buffer_end)
prtd->period_ptr_ended = prtd->dma_buffer_start;
prtd->period_ptr_submitted += prtd->period_size;
if (prtd->period_ptr_submitted >= prtd->dma_buffer_end)
prtd->period_ptr_submitted = prtd->dma_buffer_start;
ret = qmc_chan_write_submit(prtd->qmc_dai->qmc_chan,
prtd->period_ptr_submitted, prtd->period_size,
qmc_audio_pcm_write_complete, prtd);
if (ret) {
dev_err(prtd->qmc_dai->dev, "write_submit failed %d\n",
ret);
}
snd_pcm_period_elapsed(prtd->substream);
}
static void qmc_audio_pcm_read_complete(void *context, size_t length)
{
struct qmc_dai_prtd *prtd = context;
int ret;
if (length != prtd->period_size) {
dev_err(prtd->qmc_dai->dev, "read complete length = %zu, exp %zu\n",
length, prtd->period_size);
}
prtd->period_ptr_ended += prtd->period_size;
if (prtd->period_ptr_ended >= prtd->dma_buffer_end)
prtd->period_ptr_ended = prtd->dma_buffer_start;
prtd->period_ptr_submitted += prtd->period_size;
if (prtd->period_ptr_submitted >= prtd->dma_buffer_end)
prtd->period_ptr_submitted = prtd->dma_buffer_start;
ret = qmc_chan_read_submit(prtd->qmc_dai->qmc_chan,
prtd->period_ptr_submitted, prtd->period_size,
qmc_audio_pcm_read_complete, prtd);
if (ret) {
dev_err(prtd->qmc_dai->dev, "read_submit failed %d\n",
ret);
}
snd_pcm_period_elapsed(prtd->substream);
}
static int qmc_audio_pcm_trigger(struct snd_soc_component *component,
struct snd_pcm_substream *substream, int cmd)
{
struct qmc_dai_prtd *prtd = substream->runtime->private_data;
int ret;
if (!prtd->qmc_dai) {
dev_err(component->dev, "qmc_dai is not set\n");
return -EINVAL;
}
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
/* Submit first chunk ... */
ret = qmc_chan_write_submit(prtd->qmc_dai->qmc_chan,
prtd->period_ptr_submitted, prtd->period_size,
qmc_audio_pcm_write_complete, prtd);
if (ret) {
dev_err(component->dev, "write_submit failed %d\n",
ret);
return ret;
}
/* ... prepare next one ... */
prtd->period_ptr_submitted += prtd->period_size;
if (prtd->period_ptr_submitted >= prtd->dma_buffer_end)
prtd->period_ptr_submitted = prtd->dma_buffer_start;
/* ... and send it */
ret = qmc_chan_write_submit(prtd->qmc_dai->qmc_chan,
prtd->period_ptr_submitted, prtd->period_size,
qmc_audio_pcm_write_complete, prtd);
if (ret) {
dev_err(component->dev, "write_submit failed %d\n",
ret);
return ret;
}
} else {
/* Submit first chunk ... */
ret = qmc_chan_read_submit(prtd->qmc_dai->qmc_chan,
prtd->period_ptr_submitted, prtd->period_size,
qmc_audio_pcm_read_complete, prtd);
if (ret) {
dev_err(component->dev, "read_submit failed %d\n",
ret);
return ret;
}
/* ... prepare next one ... */
prtd->period_ptr_submitted += prtd->period_size;
if (prtd->period_ptr_submitted >= prtd->dma_buffer_end)
prtd->period_ptr_submitted = prtd->dma_buffer_start;
/* ... and send it */
ret = qmc_chan_read_submit(prtd->qmc_dai->qmc_chan,
prtd->period_ptr_submitted, prtd->period_size,
qmc_audio_pcm_read_complete, prtd);
if (ret) {
dev_err(component->dev, "write_submit failed %d\n",
ret);
return ret;
}
}
break;
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
break;
default:
return -EINVAL;
}
return 0;
}
static snd_pcm_uframes_t qmc_audio_pcm_pointer(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct qmc_dai_prtd *prtd = substream->runtime->private_data;
return bytes_to_frames(substream->runtime,
prtd->period_ptr_ended - prtd->dma_buffer_start);
}
static int qmc_audio_of_xlate_dai_name(struct snd_soc_component *component,
const struct of_phandle_args *args,
const char **dai_name)
{
struct qmc_audio *qmc_audio = dev_get_drvdata(component->dev);
struct snd_soc_dai_driver *dai_driver;
int id = args->args[0];
int i;
for (i = 0; i < qmc_audio->num_dais; i++) {
dai_driver = qmc_audio->dai_drivers + i;
if (dai_driver->id == id) {
*dai_name = dai_driver->name;
return 0;
}
}
return -EINVAL;
}
static const struct snd_pcm_hardware qmc_audio_pcm_hardware = {
.info = SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_PAUSE,
.period_bytes_min = 32,
.period_bytes_max = 64*1024,
.periods_min = 2,
.periods_max = 2*1024,
.buffer_bytes_max = 64*1024,
};
static int qmc_audio_pcm_open(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct qmc_dai_prtd *prtd;
int ret;
snd_soc_set_runtime_hwparams(substream, &qmc_audio_pcm_hardware);
/* ensure that buffer size is a multiple of period size */
ret = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
if (ret < 0)
return ret;
prtd = kzalloc(sizeof(*prtd), GFP_KERNEL);
if (prtd == NULL)
return -ENOMEM;
runtime->private_data = prtd;
return 0;
}
static int qmc_audio_pcm_close(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct qmc_dai_prtd *prtd = substream->runtime->private_data;
kfree(prtd);
return 0;
}
static const struct snd_soc_component_driver qmc_audio_soc_platform = {
.open = qmc_audio_pcm_open,
.close = qmc_audio_pcm_close,
.hw_params = qmc_audio_pcm_hw_params,
.trigger = qmc_audio_pcm_trigger,
.pointer = qmc_audio_pcm_pointer,
.pcm_construct = qmc_audio_pcm_construct,
.of_xlate_dai_name = qmc_audio_of_xlate_dai_name,
};
static unsigned int qmc_dai_get_index(struct snd_soc_dai *dai)
{
struct qmc_audio *qmc_audio = snd_soc_dai_get_drvdata(dai);
return dai->driver - qmc_audio->dai_drivers;
}
static struct qmc_dai *qmc_dai_get_data(struct snd_soc_dai *dai)
{
struct qmc_audio *qmc_audio = snd_soc_dai_get_drvdata(dai);
unsigned int index;
index = qmc_dai_get_index(dai);
if (index > qmc_audio->num_dais)
return NULL;
return qmc_audio->dais + index;
}
/*
* The constraints for format/channel is to match with the number of 8bit
* time-slots available.
*/
static int qmc_dai_hw_rule_channels_by_format(struct qmc_dai *qmc_dai,
struct snd_pcm_hw_params *params,
unsigned int nb_ts)
{
struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
snd_pcm_format_t format = params_format(params);
struct snd_interval ch = {0};
switch (snd_pcm_format_physical_width(format)) {
case 8:
ch.max = nb_ts;
break;
case 16:
ch.max = nb_ts/2;
break;
case 32:
ch.max = nb_ts/4;
break;
case 64:
ch.max = nb_ts/8;
break;
default:
dev_err(qmc_dai->dev, "format physical width %u not supported\n",
snd_pcm_format_physical_width(format));
return -EINVAL;
}
ch.min = ch.max ? 1 : 0;
return snd_interval_refine(c, &ch);
}
static int qmc_dai_hw_rule_playback_channels_by_format(struct snd_pcm_hw_params *params,
struct snd_pcm_hw_rule *rule)
{
struct qmc_dai *qmc_dai = rule->private;
return qmc_dai_hw_rule_channels_by_format(qmc_dai, params, qmc_dai->nb_tx_ts);
}
static int qmc_dai_hw_rule_capture_channels_by_format(
struct snd_pcm_hw_params *params,
struct snd_pcm_hw_rule *rule)
{
struct qmc_dai *qmc_dai = rule->private;
return qmc_dai_hw_rule_channels_by_format(qmc_dai, params, qmc_dai->nb_rx_ts);
}
static int qmc_dai_hw_rule_format_by_channels(struct qmc_dai *qmc_dai,
struct snd_pcm_hw_params *params,
unsigned int nb_ts)
{
struct snd_mask *f_old = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
unsigned int channels = params_channels(params);
unsigned int slot_width;
snd_pcm_format_t format;
struct snd_mask f_new;
if (!channels || channels > nb_ts) {
dev_err(qmc_dai->dev, "channels %u not supported\n",
nb_ts);
return -EINVAL;
}
slot_width = (nb_ts / channels) * 8;
snd_mask_none(&f_new);
pcm_for_each_format(format) {
if (snd_mask_test_format(f_old, format)) {
if (snd_pcm_format_physical_width(format) <= slot_width)
snd_mask_set_format(&f_new, format);
}
}
return snd_mask_refine(f_old, &f_new);
}
static int qmc_dai_hw_rule_playback_format_by_channels(
struct snd_pcm_hw_params *params,
struct snd_pcm_hw_rule *rule)
{
struct qmc_dai *qmc_dai = rule->private;
return qmc_dai_hw_rule_format_by_channels(qmc_dai, params, qmc_dai->nb_tx_ts);
}
static int qmc_dai_hw_rule_capture_format_by_channels(
struct snd_pcm_hw_params *params,
struct snd_pcm_hw_rule *rule)
{
struct qmc_dai *qmc_dai = rule->private;
return qmc_dai_hw_rule_format_by_channels(qmc_dai, params, qmc_dai->nb_rx_ts);
}
static int qmc_dai_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct qmc_dai_prtd *prtd = substream->runtime->private_data;
snd_pcm_hw_rule_func_t hw_rule_channels_by_format;
snd_pcm_hw_rule_func_t hw_rule_format_by_channels;
struct qmc_dai *qmc_dai;
unsigned int frame_bits;
int ret;
qmc_dai = qmc_dai_get_data(dai);
if (!qmc_dai) {
dev_err(dai->dev, "Invalid dai\n");
return -EINVAL;
}
prtd->qmc_dai = qmc_dai;
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
hw_rule_channels_by_format = qmc_dai_hw_rule_capture_channels_by_format;
hw_rule_format_by_channels = qmc_dai_hw_rule_capture_format_by_channels;
frame_bits = qmc_dai->nb_rx_ts * 8;
} else {
hw_rule_channels_by_format = qmc_dai_hw_rule_playback_channels_by_format;
hw_rule_format_by_channels = qmc_dai_hw_rule_playback_format_by_channels;
frame_bits = qmc_dai->nb_tx_ts * 8;
}
ret = snd_pcm_hw_rule_add(substream->runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
hw_rule_channels_by_format, qmc_dai,
SNDRV_PCM_HW_PARAM_FORMAT, -1);
if (ret) {
dev_err(dai->dev, "Failed to add channels rule (%d)\n", ret);
return ret;
}
ret = snd_pcm_hw_rule_add(substream->runtime, 0, SNDRV_PCM_HW_PARAM_FORMAT,
hw_rule_format_by_channels, qmc_dai,
SNDRV_PCM_HW_PARAM_CHANNELS, -1);
if (ret) {
dev_err(dai->dev, "Failed to add format rule (%d)\n", ret);
return ret;
}
ret = snd_pcm_hw_constraint_single(substream->runtime,
SNDRV_PCM_HW_PARAM_FRAME_BITS,
frame_bits);
if (ret < 0) {
dev_err(dai->dev, "Failed to add frame_bits constraint (%d)\n", ret);
return ret;
}
return 0;
}
static int qmc_dai_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct qmc_chan_param chan_param = {0};
struct qmc_dai *qmc_dai;
int ret;
qmc_dai = qmc_dai_get_data(dai);
if (!qmc_dai) {
dev_err(dai->dev, "Invalid dai\n");
return -EINVAL;
}
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
chan_param.mode = QMC_TRANSPARENT;
chan_param.transp.max_rx_buf_size = params_period_bytes(params);
ret = qmc_chan_set_param(qmc_dai->qmc_chan, &chan_param);
if (ret) {
dev_err(dai->dev, "set param failed %d\n",
ret);
return ret;
}
}
return 0;
}
static int qmc_dai_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct qmc_dai *qmc_dai;
int direction;
int ret;
qmc_dai = qmc_dai_get_data(dai);
if (!qmc_dai) {
dev_err(dai->dev, "Invalid dai\n");
return -EINVAL;
}
direction = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
QMC_CHAN_WRITE : QMC_CHAN_READ;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
ret = qmc_chan_start(qmc_dai->qmc_chan, direction);
if (ret)
return ret;
break;
case SNDRV_PCM_TRIGGER_STOP:
ret = qmc_chan_stop(qmc_dai->qmc_chan, direction);
if (ret)
return ret;
ret = qmc_chan_reset(qmc_dai->qmc_chan, direction);
if (ret)
return ret;
break;
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
ret = qmc_chan_stop(qmc_dai->qmc_chan, direction);
if (ret)
return ret;
break;
default:
return -EINVAL;
}
return 0;
}
static const struct snd_soc_dai_ops qmc_dai_ops = {
.startup = qmc_dai_startup,
.trigger = qmc_dai_trigger,
.hw_params = qmc_dai_hw_params,
};
static u64 qmc_audio_formats(u8 nb_ts)
{
unsigned int format_width;
unsigned int chan_width;
snd_pcm_format_t format;
u64 formats_mask;
if (!nb_ts)
return 0;
formats_mask = 0;
chan_width = nb_ts * 8;
pcm_for_each_format(format) {
/*
* Support format other than little-endian (ie big-endian or
* without endianness such as 8bit formats)
*/
if (snd_pcm_format_little_endian(format) == 1)
continue;
/* Support physical width multiple of 8bit */
format_width = snd_pcm_format_physical_width(format);
if (format_width == 0 || format_width % 8)
continue;
/*
* And support physical width that can fit N times in the
* channel
*/
if (format_width > chan_width || chan_width % format_width)
continue;
formats_mask |= pcm_format_to_bits(format);
}
return formats_mask;
}
static int qmc_audio_dai_parse(struct qmc_audio *qmc_audio, struct device_node *np,
struct qmc_dai *qmc_dai, struct snd_soc_dai_driver *qmc_soc_dai_driver)
{
struct qmc_chan_info info;
u32 val;
int ret;
qmc_dai->dev = qmc_audio->dev;
ret = of_property_read_u32(np, "reg", &val);
if (ret) {
dev_err(qmc_audio->dev, "%pOF: failed to read reg\n", np);
return ret;
}
qmc_dai->id = val;
qmc_dai->name = devm_kasprintf(qmc_audio->dev, GFP_KERNEL, "%s.%d",
np->parent->name, qmc_dai->id);
qmc_dai->qmc_chan = devm_qmc_chan_get_byphandle(qmc_audio->dev, np,
"fsl,qmc-chan");
if (IS_ERR(qmc_dai->qmc_chan)) {
ret = PTR_ERR(qmc_dai->qmc_chan);
return dev_err_probe(qmc_audio->dev, ret,
"dai %d get QMC channel failed\n", qmc_dai->id);
}
qmc_soc_dai_driver->id = qmc_dai->id;
qmc_soc_dai_driver->name = qmc_dai->name;
ret = qmc_chan_get_info(qmc_dai->qmc_chan, &info);
if (ret) {
dev_err(qmc_audio->dev, "dai %d get QMC channel info failed %d\n",
qmc_dai->id, ret);
return ret;
}
dev_info(qmc_audio->dev, "dai %d QMC channel mode %d, nb_tx_ts %u, nb_rx_ts %u\n",
qmc_dai->id, info.mode, info.nb_tx_ts, info.nb_rx_ts);
if (info.mode != QMC_TRANSPARENT) {
dev_err(qmc_audio->dev, "dai %d QMC chan mode %d is not QMC_TRANSPARENT\n",
qmc_dai->id, info.mode);
return -EINVAL;
}
qmc_dai->nb_tx_ts = info.nb_tx_ts;
qmc_dai->nb_rx_ts = info.nb_rx_ts;
qmc_soc_dai_driver->playback.channels_min = 0;
qmc_soc_dai_driver->playback.channels_max = 0;
if (qmc_dai->nb_tx_ts) {
qmc_soc_dai_driver->playback.channels_min = 1;
qmc_soc_dai_driver->playback.channels_max = qmc_dai->nb_tx_ts;
}
qmc_soc_dai_driver->playback.formats = qmc_audio_formats(qmc_dai->nb_tx_ts);
qmc_soc_dai_driver->capture.channels_min = 0;
qmc_soc_dai_driver->capture.channels_max = 0;
if (qmc_dai->nb_rx_ts) {
qmc_soc_dai_driver->capture.channels_min = 1;
qmc_soc_dai_driver->capture.channels_max = qmc_dai->nb_rx_ts;
}
qmc_soc_dai_driver->capture.formats = qmc_audio_formats(qmc_dai->nb_rx_ts);
qmc_soc_dai_driver->playback.rates = snd_pcm_rate_to_rate_bit(info.tx_fs_rate);
qmc_soc_dai_driver->playback.rate_min = info.tx_fs_rate;
qmc_soc_dai_driver->playback.rate_max = info.tx_fs_rate;
qmc_soc_dai_driver->capture.rates = snd_pcm_rate_to_rate_bit(info.rx_fs_rate);
qmc_soc_dai_driver->capture.rate_min = info.rx_fs_rate;
qmc_soc_dai_driver->capture.rate_max = info.rx_fs_rate;
qmc_soc_dai_driver->ops = &qmc_dai_ops;
return 0;
}
static int qmc_audio_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct qmc_audio *qmc_audio;
struct device_node *child;
unsigned int i;
int ret;
qmc_audio = devm_kzalloc(&pdev->dev, sizeof(*qmc_audio), GFP_KERNEL);
if (!qmc_audio)
return -ENOMEM;
qmc_audio->dev = &pdev->dev;
qmc_audio->num_dais = of_get_available_child_count(np);
if (qmc_audio->num_dais) {
qmc_audio->dais = devm_kcalloc(&pdev->dev, qmc_audio->num_dais,
sizeof(*qmc_audio->dais),
GFP_KERNEL);
if (!qmc_audio->dais)
return -ENOMEM;
qmc_audio->dai_drivers = devm_kcalloc(&pdev->dev, qmc_audio->num_dais,
sizeof(*qmc_audio->dai_drivers),
GFP_KERNEL);
if (!qmc_audio->dai_drivers)
return -ENOMEM;
}
i = 0;
for_each_available_child_of_node(np, child) {
ret = qmc_audio_dai_parse(qmc_audio, child,
qmc_audio->dais + i,
qmc_audio->dai_drivers + i);
if (ret) {
of_node_put(child);
return ret;
}
i++;
}
platform_set_drvdata(pdev, qmc_audio);
ret = devm_snd_soc_register_component(qmc_audio->dev,
&qmc_audio_soc_platform,
qmc_audio->dai_drivers,
qmc_audio->num_dais);
if (ret)
return ret;
return 0;
}
static const struct of_device_id qmc_audio_id_table[] = {
{ .compatible = "fsl,qmc-audio" },
{} /* sentinel */
};
MODULE_DEVICE_TABLE(of, qmc_audio_id_table);
static struct platform_driver qmc_audio_driver = {
.driver = {
.name = "fsl-qmc-audio",
.of_match_table = of_match_ptr(qmc_audio_id_table),
},
.probe = qmc_audio_probe,
};
module_platform_driver(qmc_audio_driver);
MODULE_AUTHOR("Herve Codina <[email protected]>");
MODULE_DESCRIPTION("CPM/QE QMC audio driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/fsl/fsl_qmc_audio.c |
// SPDX-License-Identifier: GPL-2.0
//
// Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
//
// Author: Timur Tabi <[email protected]>
//
// Copyright 2007-2010 Freescale Semiconductor, Inc.
//
// Some notes why imx-pcm-fiq is used instead of DMA on some boards:
//
// The i.MX SSI core has some nasty limitations in AC97 mode. While most
// sane processor vendors have a FIFO per AC97 slot, the i.MX has only
// one FIFO which combines all valid receive slots. We cannot even select
// which slots we want to receive. The WM9712 with which this driver
// was developed with always sends GPIO status data in slot 12 which
// we receive in our (PCM-) data stream. The only chance we have is to
// manually skip this data in the FIQ handler. With sampling rates different
// from 48000Hz not every frame has valid receive data, so the ratio
// between pcm data and GPIO status data changes. Our FIQ handler is not
// able to handle this, hence this driver only works with 48000Hz sampling
// rate.
// Reading and writing AC97 registers is another challenge. The core
// provides us status bits when the read register is updated with *another*
// value. When we read the same register two times (and the register still
// contains the same value) these status bits are not set. We work
// around this by not polling these bits but only wait a fixed delay.
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/clk.h>
#include <linux/ctype.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/mutex.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/dma/imx-dma.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/initval.h>
#include <sound/soc.h>
#include <sound/dmaengine_pcm.h>
#include "fsl_ssi.h"
#include "imx-pcm.h"
/* Define RX and TX to index ssi->regvals array; Can be 0 or 1 only */
#define RX 0
#define TX 1
/**
* FSLSSI_I2S_FORMATS: audio formats supported by the SSI
*
* The SSI has a limitation in that the samples must be in the same byte
* order as the host CPU. This is because when multiple bytes are written
* to the STX register, the bytes and bits must be written in the same
* order. The STX is a shift register, so all the bits need to be aligned
* (bit-endianness must match byte-endianness). Processors typically write
* the bits within a byte in the same order that the bytes of a word are
* written in. So if the host CPU is big-endian, then only big-endian
* samples will be written to STX properly.
*/
#ifdef __BIG_ENDIAN
#define FSLSSI_I2S_FORMATS \
(SNDRV_PCM_FMTBIT_S8 | \
SNDRV_PCM_FMTBIT_S16_BE | \
SNDRV_PCM_FMTBIT_S18_3BE | \
SNDRV_PCM_FMTBIT_S20_3BE | \
SNDRV_PCM_FMTBIT_S24_3BE | \
SNDRV_PCM_FMTBIT_S24_BE)
#else
#define FSLSSI_I2S_FORMATS \
(SNDRV_PCM_FMTBIT_S8 | \
SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S18_3LE | \
SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_3LE | \
SNDRV_PCM_FMTBIT_S24_LE)
#endif
/*
* In AC97 mode, TXDIR bit is forced to 0 and TFDIR bit is forced to 1:
* - SSI inputs external bit clock and outputs frame sync clock -- CBM_CFS
* - Also have NB_NF to mark these two clocks will not be inverted
*/
#define FSLSSI_AC97_DAIFMT \
(SND_SOC_DAIFMT_AC97 | \
SND_SOC_DAIFMT_BC_FP | \
SND_SOC_DAIFMT_NB_NF)
#define FSLSSI_SIER_DBG_RX_FLAGS \
(SSI_SIER_RFF0_EN | \
SSI_SIER_RLS_EN | \
SSI_SIER_RFS_EN | \
SSI_SIER_ROE0_EN | \
SSI_SIER_RFRC_EN)
#define FSLSSI_SIER_DBG_TX_FLAGS \
(SSI_SIER_TFE0_EN | \
SSI_SIER_TLS_EN | \
SSI_SIER_TFS_EN | \
SSI_SIER_TUE0_EN | \
SSI_SIER_TFRC_EN)
enum fsl_ssi_type {
FSL_SSI_MCP8610,
FSL_SSI_MX21,
FSL_SSI_MX35,
FSL_SSI_MX51,
};
struct fsl_ssi_regvals {
u32 sier;
u32 srcr;
u32 stcr;
u32 scr;
};
static bool fsl_ssi_readable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case REG_SSI_SACCEN:
case REG_SSI_SACCDIS:
return false;
default:
return true;
}
}
static bool fsl_ssi_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case REG_SSI_STX0:
case REG_SSI_STX1:
case REG_SSI_SRX0:
case REG_SSI_SRX1:
case REG_SSI_SISR:
case REG_SSI_SFCSR:
case REG_SSI_SACNT:
case REG_SSI_SACADD:
case REG_SSI_SACDAT:
case REG_SSI_SATAG:
case REG_SSI_SACCST:
case REG_SSI_SOR:
return true;
default:
return false;
}
}
static bool fsl_ssi_precious_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case REG_SSI_SRX0:
case REG_SSI_SRX1:
case REG_SSI_SISR:
case REG_SSI_SACADD:
case REG_SSI_SACDAT:
case REG_SSI_SATAG:
return true;
default:
return false;
}
}
static bool fsl_ssi_writeable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case REG_SSI_SRX0:
case REG_SSI_SRX1:
case REG_SSI_SACCST:
return false;
default:
return true;
}
}
static const struct regmap_config fsl_ssi_regconfig = {
.max_register = REG_SSI_SACCDIS,
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.val_format_endian = REGMAP_ENDIAN_NATIVE,
.num_reg_defaults_raw = REG_SSI_SACCDIS / sizeof(uint32_t) + 1,
.readable_reg = fsl_ssi_readable_reg,
.volatile_reg = fsl_ssi_volatile_reg,
.precious_reg = fsl_ssi_precious_reg,
.writeable_reg = fsl_ssi_writeable_reg,
.cache_type = REGCACHE_FLAT,
};
struct fsl_ssi_soc_data {
bool imx;
bool imx21regs; /* imx21-class SSI - no SACC{ST,EN,DIS} regs */
bool offline_config;
u32 sisr_write_mask;
};
/**
* struct fsl_ssi - per-SSI private data
* @regs: Pointer to the regmap registers
* @irq: IRQ of this SSI
* @cpu_dai_drv: CPU DAI driver for this device
* @dai_fmt: DAI configuration this device is currently used with
* @streams: Mask of current active streams: BIT(TX) and BIT(RX)
* @i2s_net: I2S and Network mode configurations of SCR register
* (this is the initial settings based on the DAI format)
* @synchronous: Use synchronous mode - both of TX and RX use STCK and SFCK
* @use_dma: DMA is used or FIQ with stream filter
* @use_dual_fifo: DMA with support for dual FIFO mode
* @use_dyna_fifo: DMA with support for multi FIFO script
* @has_ipg_clk_name: If "ipg" is in the clock name list of device tree
* @fifo_depth: Depth of the SSI FIFOs
* @slot_width: Width of each DAI slot
* @slots: Number of slots
* @regvals: Specific RX/TX register settings
* @clk: Clock source to access register
* @baudclk: Clock source to generate bit and frame-sync clocks
* @baudclk_streams: Active streams that are using baudclk
* @regcache_sfcsr: Cache sfcsr register value during suspend and resume
* @regcache_sacnt: Cache sacnt register value during suspend and resume
* @dma_params_tx: DMA transmit parameters
* @dma_params_rx: DMA receive parameters
* @ssi_phys: physical address of the SSI registers
* @fiq_params: FIQ stream filtering parameters
* @card_pdev: Platform_device pointer to register a sound card for PowerPC or
* to register a CODEC platform device for AC97
* @card_name: Platform_device name to register a sound card for PowerPC or
* to register a CODEC platform device for AC97
* @card_idx: The index of SSI to register a sound card for PowerPC or
* to register a CODEC platform device for AC97
* @dbg_stats: Debugging statistics
* @soc: SoC specific data
* @dev: Pointer to &pdev->dev
* @fifo_watermark: The FIFO watermark setting. Notifies DMA when there are
* @fifo_watermark or fewer words in TX fifo or
* @fifo_watermark or more empty words in RX fifo.
* @dma_maxburst: Max number of words to transfer in one go. So far,
* this is always the same as fifo_watermark.
* @ac97_reg_lock: Mutex lock to serialize AC97 register access operations
* @audio_config: configure for dma multi fifo script
*/
struct fsl_ssi {
struct regmap *regs;
int irq;
struct snd_soc_dai_driver cpu_dai_drv;
unsigned int dai_fmt;
u8 streams;
u8 i2s_net;
bool synchronous;
bool use_dma;
bool use_dual_fifo;
bool use_dyna_fifo;
bool has_ipg_clk_name;
unsigned int fifo_depth;
unsigned int slot_width;
unsigned int slots;
struct fsl_ssi_regvals regvals[2];
struct clk *clk;
struct clk *baudclk;
unsigned int baudclk_streams;
u32 regcache_sfcsr;
u32 regcache_sacnt;
struct snd_dmaengine_dai_dma_data dma_params_tx;
struct snd_dmaengine_dai_dma_data dma_params_rx;
dma_addr_t ssi_phys;
struct imx_pcm_fiq_params fiq_params;
struct platform_device *card_pdev;
char card_name[32];
u32 card_idx;
struct fsl_ssi_dbg dbg_stats;
const struct fsl_ssi_soc_data *soc;
struct device *dev;
u32 fifo_watermark;
u32 dma_maxburst;
struct mutex ac97_reg_lock;
struct sdma_peripheral_config audio_config[2];
};
/*
* SoC specific data
*
* Notes:
* 1) SSI in earlier SoCS has critical bits in control registers that
* cannot be changed after SSI starts running -- a software reset
* (set SSIEN to 0) is required to change their values. So adding
* an offline_config flag for these SoCs.
* 2) SDMA is available since imx35. However, imx35 does not support
* DMA bits changing when SSI is running, so set offline_config.
* 3) imx51 and later versions support register configurations when
* SSI is running (SSIEN); For these versions, DMA needs to be
* configured before SSI sends DMA request to avoid an undefined
* DMA request on the SDMA side.
*/
static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = {
.imx = false,
.offline_config = true,
.sisr_write_mask = SSI_SISR_RFRC | SSI_SISR_TFRC |
SSI_SISR_ROE0 | SSI_SISR_ROE1 |
SSI_SISR_TUE0 | SSI_SISR_TUE1,
};
static struct fsl_ssi_soc_data fsl_ssi_imx21 = {
.imx = true,
.imx21regs = true,
.offline_config = true,
.sisr_write_mask = 0,
};
static struct fsl_ssi_soc_data fsl_ssi_imx35 = {
.imx = true,
.offline_config = true,
.sisr_write_mask = SSI_SISR_RFRC | SSI_SISR_TFRC |
SSI_SISR_ROE0 | SSI_SISR_ROE1 |
SSI_SISR_TUE0 | SSI_SISR_TUE1,
};
static struct fsl_ssi_soc_data fsl_ssi_imx51 = {
.imx = true,
.offline_config = false,
.sisr_write_mask = SSI_SISR_ROE0 | SSI_SISR_ROE1 |
SSI_SISR_TUE0 | SSI_SISR_TUE1,
};
static const struct of_device_id fsl_ssi_ids[] = {
{ .compatible = "fsl,mpc8610-ssi", .data = &fsl_ssi_mpc8610 },
{ .compatible = "fsl,imx51-ssi", .data = &fsl_ssi_imx51 },
{ .compatible = "fsl,imx35-ssi", .data = &fsl_ssi_imx35 },
{ .compatible = "fsl,imx21-ssi", .data = &fsl_ssi_imx21 },
{}
};
MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
static bool fsl_ssi_is_ac97(struct fsl_ssi *ssi)
{
return (ssi->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
SND_SOC_DAIFMT_AC97;
}
static bool fsl_ssi_is_i2s_clock_provider(struct fsl_ssi *ssi)
{
return (ssi->dai_fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) ==
SND_SOC_DAIFMT_BP_FP;
}
static bool fsl_ssi_is_i2s_bc_fp(struct fsl_ssi *ssi)
{
return (ssi->dai_fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) ==
SND_SOC_DAIFMT_BC_FP;
}
/**
* fsl_ssi_isr - Interrupt handler to gather states
* @irq: irq number
* @dev_id: context
*/
static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
{
struct fsl_ssi *ssi = dev_id;
struct regmap *regs = ssi->regs;
u32 sisr, sisr2;
regmap_read(regs, REG_SSI_SISR, &sisr);
sisr2 = sisr & ssi->soc->sisr_write_mask;
/* Clear the bits that we set */
if (sisr2)
regmap_write(regs, REG_SSI_SISR, sisr2);
fsl_ssi_dbg_isr(&ssi->dbg_stats, sisr);
return IRQ_HANDLED;
}
/**
* fsl_ssi_config_enable - Set SCR, SIER, STCR and SRCR registers with
* cached values in regvals
* @ssi: SSI context
* @tx: direction
*
* Notes:
* 1) For offline_config SoCs, enable all necessary bits of both streams
* when 1st stream starts, even if the opposite stream will not start
* 2) It also clears FIFO before setting regvals; SOR is safe to set online
*/
static void fsl_ssi_config_enable(struct fsl_ssi *ssi, bool tx)
{
struct fsl_ssi_regvals *vals = ssi->regvals;
int dir = tx ? TX : RX;
u32 sier, srcr, stcr;
/* Clear dirty data in the FIFO; It also prevents channel slipping */
regmap_update_bits(ssi->regs, REG_SSI_SOR,
SSI_SOR_xX_CLR(tx), SSI_SOR_xX_CLR(tx));
/*
* On offline_config SoCs, SxCR and SIER are already configured when
* the previous stream started. So skip all SxCR and SIER settings
* to prevent online reconfigurations, then jump to set SCR directly
*/
if (ssi->soc->offline_config && ssi->streams)
goto enable_scr;
if (ssi->soc->offline_config) {
/*
* Online reconfiguration not supported, so enable all bits for
* both streams at once to avoid necessity of reconfigurations
*/
srcr = vals[RX].srcr | vals[TX].srcr;
stcr = vals[RX].stcr | vals[TX].stcr;
sier = vals[RX].sier | vals[TX].sier;
} else {
/* Otherwise, only set bits for the current stream */
srcr = vals[dir].srcr;
stcr = vals[dir].stcr;
sier = vals[dir].sier;
}
/* Configure SRCR, STCR and SIER at once */
regmap_update_bits(ssi->regs, REG_SSI_SRCR, srcr, srcr);
regmap_update_bits(ssi->regs, REG_SSI_STCR, stcr, stcr);
regmap_update_bits(ssi->regs, REG_SSI_SIER, sier, sier);
enable_scr:
/*
* Start DMA before setting TE to avoid FIFO underrun
* which may cause a channel slip or a channel swap
*
* TODO: FIQ cases might also need this upon testing
*/
if (ssi->use_dma && tx) {
int try = 100;
u32 sfcsr;
/* Enable SSI first to send TX DMA request */
regmap_update_bits(ssi->regs, REG_SSI_SCR,
SSI_SCR_SSIEN, SSI_SCR_SSIEN);
/* Busy wait until TX FIFO not empty -- DMA working */
do {
regmap_read(ssi->regs, REG_SSI_SFCSR, &sfcsr);
if (SSI_SFCSR_TFCNT0(sfcsr))
break;
} while (--try);
/* FIFO still empty -- something might be wrong */
if (!SSI_SFCSR_TFCNT0(sfcsr))
dev_warn(ssi->dev, "Timeout waiting TX FIFO filling\n");
}
/* Enable all remaining bits in SCR */
regmap_update_bits(ssi->regs, REG_SSI_SCR,
vals[dir].scr, vals[dir].scr);
/* Log the enabled stream to the mask */
ssi->streams |= BIT(dir);
}
/*
* Exclude bits that are used by the opposite stream
*
* When both streams are active, disabling some bits for the current stream
* might break the other stream if these bits are used by it.
*
* @vals : regvals of the current stream
* @avals: regvals of the opposite stream
* @aactive: active state of the opposite stream
*
* 1) XOR vals and avals to get the differences if the other stream is active;
* Otherwise, return current vals if the other stream is not active
* 2) AND the result of 1) with the current vals
*/
#define _ssi_xor_shared_bits(vals, avals, aactive) \
((vals) ^ ((avals) * (aactive)))
#define ssi_excl_shared_bits(vals, avals, aactive) \
((vals) & _ssi_xor_shared_bits(vals, avals, aactive))
/**
* fsl_ssi_config_disable - Unset SCR, SIER, STCR and SRCR registers
* with cached values in regvals
* @ssi: SSI context
* @tx: direction
*
* Notes:
* 1) For offline_config SoCs, to avoid online reconfigurations, disable all
* bits of both streams at once when the last stream is abort to end
* 2) It also clears FIFO after unsetting regvals; SOR is safe to set online
*/
static void fsl_ssi_config_disable(struct fsl_ssi *ssi, bool tx)
{
struct fsl_ssi_regvals *vals, *avals;
u32 sier, srcr, stcr, scr;
int adir = tx ? RX : TX;
int dir = tx ? TX : RX;
bool aactive;
/* Check if the opposite stream is active */
aactive = ssi->streams & BIT(adir);
vals = &ssi->regvals[dir];
/* Get regvals of the opposite stream to keep opposite stream safe */
avals = &ssi->regvals[adir];
/*
* To keep the other stream safe, exclude shared bits between
* both streams, and get safe bits to disable current stream
*/
scr = ssi_excl_shared_bits(vals->scr, avals->scr, aactive);
/* Disable safe bits of SCR register for the current stream */
regmap_update_bits(ssi->regs, REG_SSI_SCR, scr, 0);
/* Log the disabled stream to the mask */
ssi->streams &= ~BIT(dir);
/*
* On offline_config SoCs, if the other stream is active, skip
* SxCR and SIER settings to prevent online reconfigurations
*/
if (ssi->soc->offline_config && aactive)
goto fifo_clear;
if (ssi->soc->offline_config) {
/* Now there is only current stream active, disable all bits */
srcr = vals->srcr | avals->srcr;
stcr = vals->stcr | avals->stcr;
sier = vals->sier | avals->sier;
} else {
/*
* To keep the other stream safe, exclude shared bits between
* both streams, and get safe bits to disable current stream
*/
sier = ssi_excl_shared_bits(vals->sier, avals->sier, aactive);
srcr = ssi_excl_shared_bits(vals->srcr, avals->srcr, aactive);
stcr = ssi_excl_shared_bits(vals->stcr, avals->stcr, aactive);
}
/* Clear configurations of SRCR, STCR and SIER at once */
regmap_update_bits(ssi->regs, REG_SSI_SRCR, srcr, 0);
regmap_update_bits(ssi->regs, REG_SSI_STCR, stcr, 0);
regmap_update_bits(ssi->regs, REG_SSI_SIER, sier, 0);
fifo_clear:
/* Clear remaining data in the FIFO */
regmap_update_bits(ssi->regs, REG_SSI_SOR,
SSI_SOR_xX_CLR(tx), SSI_SOR_xX_CLR(tx));
}
static void fsl_ssi_tx_ac97_saccst_setup(struct fsl_ssi *ssi)
{
struct regmap *regs = ssi->regs;
/* no SACC{ST,EN,DIS} regs on imx21-class SSI */
if (!ssi->soc->imx21regs) {
/* Disable all channel slots */
regmap_write(regs, REG_SSI_SACCDIS, 0xff);
/* Enable slots 3 & 4 -- PCM Playback Left & Right channels */
regmap_write(regs, REG_SSI_SACCEN, 0x300);
}
}
/**
* fsl_ssi_setup_regvals - Cache critical bits of SIER, SRCR, STCR and
* SCR to later set them safely
* @ssi: SSI context
*/
static void fsl_ssi_setup_regvals(struct fsl_ssi *ssi)
{
struct fsl_ssi_regvals *vals = ssi->regvals;
vals[RX].sier = SSI_SIER_RFF0_EN | FSLSSI_SIER_DBG_RX_FLAGS;
vals[RX].srcr = SSI_SRCR_RFEN0;
vals[RX].scr = SSI_SCR_SSIEN | SSI_SCR_RE;
vals[TX].sier = SSI_SIER_TFE0_EN | FSLSSI_SIER_DBG_TX_FLAGS;
vals[TX].stcr = SSI_STCR_TFEN0;
vals[TX].scr = SSI_SCR_SSIEN | SSI_SCR_TE;
/* AC97 has already enabled SSIEN, RE and TE, so ignore them */
if (fsl_ssi_is_ac97(ssi))
vals[RX].scr = vals[TX].scr = 0;
if (ssi->use_dual_fifo) {
vals[RX].srcr |= SSI_SRCR_RFEN1;
vals[TX].stcr |= SSI_STCR_TFEN1;
}
if (ssi->use_dma) {
vals[RX].sier |= SSI_SIER_RDMAE;
vals[TX].sier |= SSI_SIER_TDMAE;
} else {
vals[RX].sier |= SSI_SIER_RIE;
vals[TX].sier |= SSI_SIER_TIE;
}
}
static void fsl_ssi_setup_ac97(struct fsl_ssi *ssi)
{
struct regmap *regs = ssi->regs;
/* Setup the clock control register */
regmap_write(regs, REG_SSI_STCCR, SSI_SxCCR_WL(17) | SSI_SxCCR_DC(13));
regmap_write(regs, REG_SSI_SRCCR, SSI_SxCCR_WL(17) | SSI_SxCCR_DC(13));
/* Enable AC97 mode and startup the SSI */
regmap_write(regs, REG_SSI_SACNT, SSI_SACNT_AC97EN | SSI_SACNT_FV);
/* AC97 has to communicate with codec before starting a stream */
regmap_update_bits(regs, REG_SSI_SCR,
SSI_SCR_SSIEN | SSI_SCR_TE | SSI_SCR_RE,
SSI_SCR_SSIEN | SSI_SCR_TE | SSI_SCR_RE);
regmap_write(regs, REG_SSI_SOR, SSI_SOR_WAIT(3));
}
static int fsl_ssi_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
int ret;
ret = clk_prepare_enable(ssi->clk);
if (ret)
return ret;
/*
* When using dual fifo mode, it is safer to ensure an even period
* size. If appearing to an odd number while DMA always starts its
* task from fifo0, fifo1 would be neglected at the end of each
* period. But SSI would still access fifo1 with an invalid data.
*/
if (ssi->use_dual_fifo || ssi->use_dyna_fifo)
snd_pcm_hw_constraint_step(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
return 0;
}
static void fsl_ssi_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
clk_disable_unprepare(ssi->clk);
}
/**
* fsl_ssi_set_bclk - Configure Digital Audio Interface bit clock
* @substream: ASoC substream
* @dai: pointer to DAI
* @hw_params: pointers to hw_params
*
* Notes: This function can be only called when using SSI as DAI master
*
* Quick instruction for parameters:
* freq: Output BCLK frequency = samplerate * slots * slot_width
* (In 2-channel I2S Master mode, slot_width is fixed 32)
*/
static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai,
struct snd_pcm_hw_params *hw_params)
{
bool tx2, tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
struct regmap *regs = ssi->regs;
u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i;
unsigned long clkrate, baudrate, tmprate;
unsigned int channels = params_channels(hw_params);
unsigned int slot_width = params_width(hw_params);
unsigned int slots = 2;
u64 sub, savesub = 100000;
unsigned int freq;
bool baudclk_is_used;
int ret;
/* Override slots and slot_width if being specifically set... */
if (ssi->slots)
slots = ssi->slots;
if (ssi->slot_width)
slot_width = ssi->slot_width;
/* ...but force 32 bits for stereo audio using I2S Master Mode */
if (channels == 2 &&
(ssi->i2s_net & SSI_SCR_I2S_MODE_MASK) == SSI_SCR_I2S_MODE_MASTER)
slot_width = 32;
/* Generate bit clock based on the slot number and slot width */
freq = slots * slot_width * params_rate(hw_params);
/* Don't apply it to any non-baudclk circumstance */
if (IS_ERR(ssi->baudclk))
return -EINVAL;
/*
* Hardware limitation: The bclk rate must be
* never greater than 1/5 IPG clock rate
*/
if (freq * 5 > clk_get_rate(ssi->clk)) {
dev_err(dai->dev, "bitclk > ipgclk / 5\n");
return -EINVAL;
}
baudclk_is_used = ssi->baudclk_streams & ~(BIT(substream->stream));
/* It should be already enough to divide clock by setting pm alone */
psr = 0;
div2 = 0;
factor = (div2 + 1) * (7 * psr + 1) * 2;
for (i = 0; i < 255; i++) {
tmprate = freq * factor * (i + 1);
if (baudclk_is_used)
clkrate = clk_get_rate(ssi->baudclk);
else
clkrate = clk_round_rate(ssi->baudclk, tmprate);
clkrate /= factor;
afreq = clkrate / (i + 1);
if (freq == afreq)
sub = 0;
else if (freq / afreq == 1)
sub = freq - afreq;
else if (afreq / freq == 1)
sub = afreq - freq;
else
continue;
/* Calculate the fraction */
sub *= 100000;
do_div(sub, freq);
if (sub < savesub && !(i == 0)) {
baudrate = tmprate;
savesub = sub;
pm = i;
}
/* We are lucky */
if (savesub == 0)
break;
}
/* No proper pm found if it is still remaining the initial value */
if (pm == 999) {
dev_err(dai->dev, "failed to handle the required sysclk\n");
return -EINVAL;
}
stccr = SSI_SxCCR_PM(pm + 1);
mask = SSI_SxCCR_PM_MASK | SSI_SxCCR_DIV2 | SSI_SxCCR_PSR;
/* STCCR is used for RX in synchronous mode */
tx2 = tx || ssi->synchronous;
regmap_update_bits(regs, REG_SSI_SxCCR(tx2), mask, stccr);
if (!baudclk_is_used) {
ret = clk_set_rate(ssi->baudclk, baudrate);
if (ret) {
dev_err(dai->dev, "failed to set baudclk rate\n");
return -EINVAL;
}
}
return 0;
}
/**
* fsl_ssi_hw_params - Configure SSI based on PCM hardware parameters
* @substream: ASoC substream
* @hw_params: pointers to hw_params
* @dai: pointer to DAI
*
* Notes:
* 1) SxCCR.WL bits are critical bits that require SSI to be temporarily
* disabled on offline_config SoCs. Even for online configurable SoCs
* running in synchronous mode (both TX and RX use STCCR), it is not
* safe to re-configure them when both two streams start running.
* 2) SxCCR.PM, SxCCR.DIV2 and SxCCR.PSR bits will be configured in the
* fsl_ssi_set_bclk() if SSI is the DAI clock master.
*/
static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *hw_params,
struct snd_soc_dai *dai)
{
bool tx2, tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
struct fsl_ssi_regvals *vals = ssi->regvals;
struct regmap *regs = ssi->regs;
unsigned int channels = params_channels(hw_params);
unsigned int sample_size = params_width(hw_params);
u32 wl = SSI_SxCCR_WL(sample_size);
int ret;
if (fsl_ssi_is_i2s_clock_provider(ssi)) {
ret = fsl_ssi_set_bclk(substream, dai, hw_params);
if (ret)
return ret;
/* Do not enable the clock if it is already enabled */
if (!(ssi->baudclk_streams & BIT(substream->stream))) {
ret = clk_prepare_enable(ssi->baudclk);
if (ret)
return ret;
ssi->baudclk_streams |= BIT(substream->stream);
}
}
/*
* SSI is properly configured if it is enabled and running in
* the synchronous mode; Note that AC97 mode is an exception
* that should set separate configurations for STCCR and SRCCR
* despite running in the synchronous mode.
*/
if (ssi->streams && ssi->synchronous)
return 0;
if (!fsl_ssi_is_ac97(ssi)) {
/*
* Keep the ssi->i2s_net intact while having a local variable
* to override settings for special use cases. Otherwise, the
* ssi->i2s_net will lose the settings for regular use cases.
*/
u8 i2s_net = ssi->i2s_net;
/* Normal + Network mode to send 16-bit data in 32-bit frames */
if (fsl_ssi_is_i2s_bc_fp(ssi) && sample_size == 16)
i2s_net = SSI_SCR_I2S_MODE_NORMAL | SSI_SCR_NET;
/* Use Normal mode to send mono data at 1st slot of 2 slots */
if (channels == 1)
i2s_net = SSI_SCR_I2S_MODE_NORMAL;
regmap_update_bits(regs, REG_SSI_SCR,
SSI_SCR_I2S_NET_MASK, i2s_net);
}
/* In synchronous mode, the SSI uses STCCR for capture */
tx2 = tx || ssi->synchronous;
regmap_update_bits(regs, REG_SSI_SxCCR(tx2), SSI_SxCCR_WL_MASK, wl);
if (ssi->use_dyna_fifo) {
if (channels == 1) {
ssi->audio_config[0].n_fifos_dst = 1;
ssi->audio_config[1].n_fifos_src = 1;
vals[RX].srcr &= ~SSI_SRCR_RFEN1;
vals[TX].stcr &= ~SSI_STCR_TFEN1;
vals[RX].scr &= ~SSI_SCR_TCH_EN;
vals[TX].scr &= ~SSI_SCR_TCH_EN;
} else {
ssi->audio_config[0].n_fifos_dst = 2;
ssi->audio_config[1].n_fifos_src = 2;
vals[RX].srcr |= SSI_SRCR_RFEN1;
vals[TX].stcr |= SSI_STCR_TFEN1;
vals[RX].scr |= SSI_SCR_TCH_EN;
vals[TX].scr |= SSI_SCR_TCH_EN;
}
ssi->dma_params_tx.peripheral_config = &ssi->audio_config[0];
ssi->dma_params_tx.peripheral_size = sizeof(ssi->audio_config[0]);
ssi->dma_params_rx.peripheral_config = &ssi->audio_config[1];
ssi->dma_params_rx.peripheral_size = sizeof(ssi->audio_config[1]);
}
return 0;
}
static int fsl_ssi_hw_free(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
if (fsl_ssi_is_i2s_clock_provider(ssi) &&
ssi->baudclk_streams & BIT(substream->stream)) {
clk_disable_unprepare(ssi->baudclk);
ssi->baudclk_streams &= ~BIT(substream->stream);
}
return 0;
}
static int _fsl_ssi_set_dai_fmt(struct fsl_ssi *ssi, unsigned int fmt)
{
u32 strcr = 0, scr = 0, stcr, srcr, mask;
unsigned int slots;
ssi->dai_fmt = fmt;
/* Synchronize frame sync clock for TE to avoid data slipping */
scr |= SSI_SCR_SYNC_TX_FS;
/* Set to default shifting settings: LSB_ALIGNED */
strcr |= SSI_STCR_TXBIT0;
/* Use Network mode as default */
ssi->i2s_net = SSI_SCR_NET;
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BP_FP:
if (IS_ERR(ssi->baudclk)) {
dev_err(ssi->dev,
"missing baudclk for master mode\n");
return -EINVAL;
}
fallthrough;
case SND_SOC_DAIFMT_BC_FP:
ssi->i2s_net |= SSI_SCR_I2S_MODE_MASTER;
break;
case SND_SOC_DAIFMT_BC_FC:
ssi->i2s_net |= SSI_SCR_I2S_MODE_SLAVE;
break;
default:
return -EINVAL;
}
slots = ssi->slots ? : 2;
regmap_update_bits(ssi->regs, REG_SSI_STCCR,
SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots));
regmap_update_bits(ssi->regs, REG_SSI_SRCCR,
SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots));
/* Data on rising edge of bclk, frame low, 1clk before data */
strcr |= SSI_STCR_TFSI | SSI_STCR_TSCKP | SSI_STCR_TEFS;
break;
case SND_SOC_DAIFMT_LEFT_J:
/* Data on rising edge of bclk, frame high */
strcr |= SSI_STCR_TSCKP;
break;
case SND_SOC_DAIFMT_DSP_A:
/* Data on rising edge of bclk, frame high, 1clk before data */
strcr |= SSI_STCR_TFSL | SSI_STCR_TSCKP | SSI_STCR_TEFS;
break;
case SND_SOC_DAIFMT_DSP_B:
/* Data on rising edge of bclk, frame high */
strcr |= SSI_STCR_TFSL | SSI_STCR_TSCKP;
break;
case SND_SOC_DAIFMT_AC97:
/* Data on falling edge of bclk, frame high, 1clk before data */
strcr |= SSI_STCR_TEFS;
break;
default:
return -EINVAL;
}
scr |= ssi->i2s_net;
/* DAI clock inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
/* Nothing to do for both normal cases */
break;
case SND_SOC_DAIFMT_IB_NF:
/* Invert bit clock */
strcr ^= SSI_STCR_TSCKP;
break;
case SND_SOC_DAIFMT_NB_IF:
/* Invert frame clock */
strcr ^= SSI_STCR_TFSI;
break;
case SND_SOC_DAIFMT_IB_IF:
/* Invert both clocks */
strcr ^= SSI_STCR_TSCKP;
strcr ^= SSI_STCR_TFSI;
break;
default:
return -EINVAL;
}
/* DAI clock provider masks */
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BP_FP:
/* Output bit and frame sync clocks */
strcr |= SSI_STCR_TFDIR | SSI_STCR_TXDIR;
scr |= SSI_SCR_SYS_CLK_EN;
break;
case SND_SOC_DAIFMT_BC_FC:
/* Input bit or frame sync clocks */
break;
case SND_SOC_DAIFMT_BC_FP:
/* Input bit clock but output frame sync clock */
strcr |= SSI_STCR_TFDIR;
break;
default:
return -EINVAL;
}
stcr = strcr;
srcr = strcr;
/* Set SYN mode and clear RXDIR bit when using SYN or AC97 mode */
if (ssi->synchronous || fsl_ssi_is_ac97(ssi)) {
srcr &= ~SSI_SRCR_RXDIR;
scr |= SSI_SCR_SYN;
}
mask = SSI_STCR_TFDIR | SSI_STCR_TXDIR | SSI_STCR_TSCKP |
SSI_STCR_TFSL | SSI_STCR_TFSI | SSI_STCR_TEFS | SSI_STCR_TXBIT0;
regmap_update_bits(ssi->regs, REG_SSI_STCR, mask, stcr);
regmap_update_bits(ssi->regs, REG_SSI_SRCR, mask, srcr);
mask = SSI_SCR_SYNC_TX_FS | SSI_SCR_I2S_MODE_MASK |
SSI_SCR_SYS_CLK_EN | SSI_SCR_SYN;
regmap_update_bits(ssi->regs, REG_SSI_SCR, mask, scr);
return 0;
}
/**
* fsl_ssi_set_dai_fmt - Configure Digital Audio Interface (DAI) Format
* @dai: pointer to DAI
* @fmt: format mask
*/
static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
/* AC97 configured DAIFMT earlier in the probe() */
if (fsl_ssi_is_ac97(ssi))
return 0;
return _fsl_ssi_set_dai_fmt(ssi, fmt);
}
/**
* fsl_ssi_set_dai_tdm_slot - Set TDM slot number and slot width
* @dai: pointer to DAI
* @tx_mask: mask for TX
* @rx_mask: mask for RX
* @slots: number of slots
* @slot_width: number of bits per slot
*/
static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask,
u32 rx_mask, int slots, int slot_width)
{
struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
struct regmap *regs = ssi->regs;
u32 val;
/* The word length should be 8, 10, 12, 16, 18, 20, 22 or 24 */
if (slot_width & 1 || slot_width < 8 || slot_width > 24) {
dev_err(dai->dev, "invalid slot width: %d\n", slot_width);
return -EINVAL;
}
/* The slot number should be >= 2 if using Network mode or I2S mode */
if (ssi->i2s_net && slots < 2) {
dev_err(dai->dev, "slot number should be >= 2 in I2S or NET\n");
return -EINVAL;
}
regmap_update_bits(regs, REG_SSI_STCCR,
SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots));
regmap_update_bits(regs, REG_SSI_SRCCR,
SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots));
/* Save the SCR register value */
regmap_read(regs, REG_SSI_SCR, &val);
/* Temporarily enable SSI to allow SxMSKs to be configurable */
regmap_update_bits(regs, REG_SSI_SCR, SSI_SCR_SSIEN, SSI_SCR_SSIEN);
regmap_write(regs, REG_SSI_STMSK, ~tx_mask);
regmap_write(regs, REG_SSI_SRMSK, ~rx_mask);
/* Restore the value of SSIEN bit */
regmap_update_bits(regs, REG_SSI_SCR, SSI_SCR_SSIEN, val);
ssi->slot_width = slot_width;
ssi->slots = slots;
return 0;
}
/**
* fsl_ssi_trigger - Start or stop SSI and corresponding DMA transaction.
* @substream: ASoC substream
* @cmd: trigger command
* @dai: pointer to DAI
*
* The DMA channel is in external master start and pause mode, which
* means the SSI completely controls the flow of data.
*/
static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
/*
* SACCST might be modified via AC Link by a CODEC if it sends
* extra bits in their SLOTREQ requests, which'll accidentally
* send valid data to slots other than normal playback slots.
*
* To be safe, configure SACCST right before TX starts.
*/
if (tx && fsl_ssi_is_ac97(ssi))
fsl_ssi_tx_ac97_saccst_setup(ssi);
fsl_ssi_config_enable(ssi, tx);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
fsl_ssi_config_disable(ssi, tx);
break;
default:
return -EINVAL;
}
return 0;
}
static int fsl_ssi_dai_probe(struct snd_soc_dai *dai)
{
struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
if (ssi->soc->imx && ssi->use_dma)
snd_soc_dai_init_dma_data(dai, &ssi->dma_params_tx,
&ssi->dma_params_rx);
return 0;
}
static const struct snd_soc_dai_ops fsl_ssi_dai_ops = {
.probe = fsl_ssi_dai_probe,
.startup = fsl_ssi_startup,
.shutdown = fsl_ssi_shutdown,
.hw_params = fsl_ssi_hw_params,
.hw_free = fsl_ssi_hw_free,
.set_fmt = fsl_ssi_set_dai_fmt,
.set_tdm_slot = fsl_ssi_set_dai_tdm_slot,
.trigger = fsl_ssi_trigger,
};
static struct snd_soc_dai_driver fsl_ssi_dai_template = {
.playback = {
.stream_name = "CPU-Playback",
.channels_min = 1,
.channels_max = 32,
.rates = SNDRV_PCM_RATE_CONTINUOUS,
.formats = FSLSSI_I2S_FORMATS,
},
.capture = {
.stream_name = "CPU-Capture",
.channels_min = 1,
.channels_max = 32,
.rates = SNDRV_PCM_RATE_CONTINUOUS,
.formats = FSLSSI_I2S_FORMATS,
},
.ops = &fsl_ssi_dai_ops,
};
static const struct snd_soc_component_driver fsl_ssi_component = {
.name = "fsl-ssi",
.legacy_dai_naming = 1,
};
static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
.symmetric_channels = 1,
.playback = {
.stream_name = "CPU AC97 Playback",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16 | SNDRV_PCM_FMTBIT_S20,
},
.capture = {
.stream_name = "CPU AC97 Capture",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_48000,
/* 16-bit capture is broken (errata ERR003778) */
.formats = SNDRV_PCM_FMTBIT_S20,
},
.ops = &fsl_ssi_dai_ops,
};
static struct fsl_ssi *fsl_ac97_data;
static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
unsigned short val)
{
struct regmap *regs = fsl_ac97_data->regs;
unsigned int lreg;
unsigned int lval;
int ret;
if (reg > 0x7f)
return;
mutex_lock(&fsl_ac97_data->ac97_reg_lock);
ret = clk_prepare_enable(fsl_ac97_data->clk);
if (ret) {
pr_err("ac97 write clk_prepare_enable failed: %d\n",
ret);
goto ret_unlock;
}
lreg = reg << 12;
regmap_write(regs, REG_SSI_SACADD, lreg);
lval = val << 4;
regmap_write(regs, REG_SSI_SACDAT, lval);
regmap_update_bits(regs, REG_SSI_SACNT,
SSI_SACNT_RDWR_MASK, SSI_SACNT_WR);
udelay(100);
clk_disable_unprepare(fsl_ac97_data->clk);
ret_unlock:
mutex_unlock(&fsl_ac97_data->ac97_reg_lock);
}
static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
unsigned short reg)
{
struct regmap *regs = fsl_ac97_data->regs;
unsigned short val = 0;
u32 reg_val;
unsigned int lreg;
int ret;
mutex_lock(&fsl_ac97_data->ac97_reg_lock);
ret = clk_prepare_enable(fsl_ac97_data->clk);
if (ret) {
pr_err("ac97 read clk_prepare_enable failed: %d\n", ret);
goto ret_unlock;
}
lreg = (reg & 0x7f) << 12;
regmap_write(regs, REG_SSI_SACADD, lreg);
regmap_update_bits(regs, REG_SSI_SACNT,
SSI_SACNT_RDWR_MASK, SSI_SACNT_RD);
udelay(100);
regmap_read(regs, REG_SSI_SACDAT, ®_val);
val = (reg_val >> 4) & 0xffff;
clk_disable_unprepare(fsl_ac97_data->clk);
ret_unlock:
mutex_unlock(&fsl_ac97_data->ac97_reg_lock);
return val;
}
static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = {
.read = fsl_ssi_ac97_read,
.write = fsl_ssi_ac97_write,
};
/**
* fsl_ssi_hw_init - Initialize SSI registers
* @ssi: SSI context
*/
static int fsl_ssi_hw_init(struct fsl_ssi *ssi)
{
u32 wm = ssi->fifo_watermark;
/* Initialize regvals */
fsl_ssi_setup_regvals(ssi);
/* Set watermarks */
regmap_write(ssi->regs, REG_SSI_SFCSR,
SSI_SFCSR_TFWM0(wm) | SSI_SFCSR_RFWM0(wm) |
SSI_SFCSR_TFWM1(wm) | SSI_SFCSR_RFWM1(wm));
/* Enable Dual FIFO mode */
if (ssi->use_dual_fifo)
regmap_update_bits(ssi->regs, REG_SSI_SCR,
SSI_SCR_TCH_EN, SSI_SCR_TCH_EN);
/* AC97 should start earlier to communicate with CODECs */
if (fsl_ssi_is_ac97(ssi)) {
_fsl_ssi_set_dai_fmt(ssi, ssi->dai_fmt);
fsl_ssi_setup_ac97(ssi);
}
return 0;
}
/**
* fsl_ssi_hw_clean - Clear SSI registers
* @ssi: SSI context
*/
static void fsl_ssi_hw_clean(struct fsl_ssi *ssi)
{
/* Disable registers for AC97 */
if (fsl_ssi_is_ac97(ssi)) {
/* Disable TE and RE bits first */
regmap_update_bits(ssi->regs, REG_SSI_SCR,
SSI_SCR_TE | SSI_SCR_RE, 0);
/* Disable AC97 mode */
regmap_write(ssi->regs, REG_SSI_SACNT, 0);
/* Unset WAIT bits */
regmap_write(ssi->regs, REG_SSI_SOR, 0);
/* Disable SSI -- software reset */
regmap_update_bits(ssi->regs, REG_SSI_SCR, SSI_SCR_SSIEN, 0);
}
}
/*
* Make every character in a string lower-case
*/
static void make_lowercase(char *s)
{
if (!s)
return;
for (; *s; s++)
*s = tolower(*s);
}
static int fsl_ssi_imx_probe(struct platform_device *pdev,
struct fsl_ssi *ssi, void __iomem *iomem)
{
struct device *dev = &pdev->dev;
int ret;
/* Backward compatible for a DT without ipg clock name assigned */
if (ssi->has_ipg_clk_name)
ssi->clk = devm_clk_get(dev, "ipg");
else
ssi->clk = devm_clk_get(dev, NULL);
if (IS_ERR(ssi->clk)) {
ret = PTR_ERR(ssi->clk);
dev_err(dev, "failed to get clock: %d\n", ret);
return ret;
}
/* Enable the clock since regmap will not handle it in this case */
if (!ssi->has_ipg_clk_name) {
ret = clk_prepare_enable(ssi->clk);
if (ret) {
dev_err(dev, "clk_prepare_enable failed: %d\n", ret);
return ret;
}
}
/* Do not error out for consumer cases that live without a baud clock */
ssi->baudclk = devm_clk_get(dev, "baud");
if (IS_ERR(ssi->baudclk))
dev_dbg(dev, "failed to get baud clock: %ld\n",
PTR_ERR(ssi->baudclk));
ssi->dma_params_tx.maxburst = ssi->dma_maxburst;
ssi->dma_params_rx.maxburst = ssi->dma_maxburst;
ssi->dma_params_tx.addr = ssi->ssi_phys + REG_SSI_STX0;
ssi->dma_params_rx.addr = ssi->ssi_phys + REG_SSI_SRX0;
/* Use even numbers to avoid channel swap due to SDMA script design */
if (ssi->use_dual_fifo || ssi->use_dyna_fifo) {
ssi->dma_params_tx.maxburst &= ~0x1;
ssi->dma_params_rx.maxburst &= ~0x1;
}
if (!ssi->use_dma) {
/*
* Some boards use an incompatible codec. Use imx-fiq-pcm-audio
* to get it working, as DMA is not possible in this situation.
*/
ssi->fiq_params.irq = ssi->irq;
ssi->fiq_params.base = iomem;
ssi->fiq_params.dma_params_rx = &ssi->dma_params_rx;
ssi->fiq_params.dma_params_tx = &ssi->dma_params_tx;
ret = imx_pcm_fiq_init(pdev, &ssi->fiq_params);
if (ret)
goto error_pcm;
} else {
ret = imx_pcm_dma_init(pdev);
if (ret)
goto error_pcm;
}
return 0;
error_pcm:
if (!ssi->has_ipg_clk_name)
clk_disable_unprepare(ssi->clk);
return ret;
}
static void fsl_ssi_imx_clean(struct platform_device *pdev, struct fsl_ssi *ssi)
{
if (!ssi->use_dma)
imx_pcm_fiq_exit(pdev);
if (!ssi->has_ipg_clk_name)
clk_disable_unprepare(ssi->clk);
}
static int fsl_ssi_probe_from_dt(struct fsl_ssi *ssi)
{
struct device *dev = ssi->dev;
struct device_node *np = dev->of_node;
const char *p, *sprop;
const __be32 *iprop;
u32 dmas[4];
int ret;
ret = of_property_match_string(np, "clock-names", "ipg");
/* Get error code if not found */
ssi->has_ipg_clk_name = ret >= 0;
/* Check if being used in AC97 mode */
sprop = of_get_property(np, "fsl,mode", NULL);
if (sprop && !strcmp(sprop, "ac97-slave")) {
ssi->dai_fmt = FSLSSI_AC97_DAIFMT;
ret = of_property_read_u32(np, "cell-index", &ssi->card_idx);
if (ret) {
dev_err(dev, "failed to get SSI index property\n");
return -EINVAL;
}
strcpy(ssi->card_name, "ac97-codec");
} else if (!of_property_read_bool(np, "fsl,ssi-asynchronous")) {
/*
* In synchronous mode, STCK and STFS ports are used by RX
* as well. So the software should limit the sample rates,
* sample bits and channels to be symmetric.
*
* This is exclusive with FSLSSI_AC97_FORMATS as AC97 runs
* in the SSI synchronous mode however it does not have to
* limit symmetric sample rates and sample bits.
*/
ssi->synchronous = true;
}
/* Select DMA or FIQ */
ssi->use_dma = !of_property_read_bool(np, "fsl,fiq-stream-filter");
/* Fetch FIFO depth; Set to 8 for older DT without this property */
iprop = of_get_property(np, "fsl,fifo-depth", NULL);
if (iprop)
ssi->fifo_depth = be32_to_cpup(iprop);
else
ssi->fifo_depth = 8;
/* Use dual FIFO mode depending on the support from SDMA script */
ret = of_property_read_u32_array(np, "dmas", dmas, 4);
if (ssi->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL)
ssi->use_dual_fifo = true;
if (ssi->use_dma && !ret && dmas[2] == IMX_DMATYPE_MULTI_SAI)
ssi->use_dyna_fifo = true;
/*
* Backward compatible for older bindings by manually triggering the
* machine driver's probe(). Use /compatible property, including the
* address of CPU DAI driver structure, as the name of machine driver
*
* If card_name is set by AC97 earlier, bypass here since it uses a
* different name to register the device.
*/
if (!ssi->card_name[0] && of_get_property(np, "codec-handle", NULL)) {
struct device_node *root = of_find_node_by_path("/");
sprop = of_get_property(root, "compatible", NULL);
of_node_put(root);
/* Strip "fsl," in the compatible name if applicable */
p = strrchr(sprop, ',');
if (p)
sprop = p + 1;
snprintf(ssi->card_name, sizeof(ssi->card_name),
"snd-soc-%s", sprop);
make_lowercase(ssi->card_name);
ssi->card_idx = 0;
}
return 0;
}
static int fsl_ssi_probe(struct platform_device *pdev)
{
struct regmap_config regconfig = fsl_ssi_regconfig;
struct device *dev = &pdev->dev;
struct fsl_ssi *ssi;
struct resource *res;
void __iomem *iomem;
int ret = 0;
ssi = devm_kzalloc(dev, sizeof(*ssi), GFP_KERNEL);
if (!ssi)
return -ENOMEM;
ssi->dev = dev;
ssi->soc = of_device_get_match_data(&pdev->dev);
/* Probe from DT */
ret = fsl_ssi_probe_from_dt(ssi);
if (ret)
return ret;
if (fsl_ssi_is_ac97(ssi)) {
memcpy(&ssi->cpu_dai_drv, &fsl_ssi_ac97_dai,
sizeof(fsl_ssi_ac97_dai));
fsl_ac97_data = ssi;
} else {
memcpy(&ssi->cpu_dai_drv, &fsl_ssi_dai_template,
sizeof(fsl_ssi_dai_template));
}
ssi->cpu_dai_drv.name = dev_name(dev);
iomem = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(iomem))
return PTR_ERR(iomem);
ssi->ssi_phys = res->start;
if (ssi->soc->imx21regs) {
/* No SACC{ST,EN,DIS} regs in imx21-class SSI */
regconfig.max_register = REG_SSI_SRMSK;
regconfig.num_reg_defaults_raw =
REG_SSI_SRMSK / sizeof(uint32_t) + 1;
}
if (ssi->has_ipg_clk_name)
ssi->regs = devm_regmap_init_mmio_clk(dev, "ipg", iomem,
®config);
else
ssi->regs = devm_regmap_init_mmio(dev, iomem, ®config);
if (IS_ERR(ssi->regs)) {
dev_err(dev, "failed to init register map\n");
return PTR_ERR(ssi->regs);
}
ssi->irq = platform_get_irq(pdev, 0);
if (ssi->irq < 0)
return ssi->irq;
/* Set software limitations for synchronous mode except AC97 */
if (ssi->synchronous && !fsl_ssi_is_ac97(ssi)) {
ssi->cpu_dai_drv.symmetric_rate = 1;
ssi->cpu_dai_drv.symmetric_channels = 1;
ssi->cpu_dai_drv.symmetric_sample_bits = 1;
}
/*
* Configure TX and RX DMA watermarks -- when to send a DMA request
*
* Values should be tested to avoid FIFO under/over run. Set maxburst
* to fifo_watermark to maxiumize DMA transaction to reduce overhead.
*/
switch (ssi->fifo_depth) {
case 15:
/*
* Set to 8 as a balanced configuration -- When TX FIFO has 8
* empty slots, send a DMA request to fill these 8 slots. The
* remaining 7 slots should be able to allow DMA to finish the
* transaction before TX FIFO underruns; Same applies to RX.
*
* Tested with cases running at 48kHz @ 16 bits x 16 channels
*/
ssi->fifo_watermark = 8;
ssi->dma_maxburst = 8;
break;
case 8:
default:
/* Safely use old watermark configurations for older chips */
ssi->fifo_watermark = ssi->fifo_depth - 2;
ssi->dma_maxburst = ssi->fifo_depth - 2;
break;
}
dev_set_drvdata(dev, ssi);
if (ssi->soc->imx) {
ret = fsl_ssi_imx_probe(pdev, ssi, iomem);
if (ret)
return ret;
}
if (fsl_ssi_is_ac97(ssi)) {
mutex_init(&ssi->ac97_reg_lock);
ret = snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev);
if (ret) {
dev_err(dev, "failed to set AC'97 ops\n");
goto error_ac97_ops;
}
}
ret = devm_snd_soc_register_component(dev, &fsl_ssi_component,
&ssi->cpu_dai_drv, 1);
if (ret) {
dev_err(dev, "failed to register DAI: %d\n", ret);
goto error_asoc_register;
}
if (ssi->use_dma) {
ret = devm_request_irq(dev, ssi->irq, fsl_ssi_isr, 0,
dev_name(dev), ssi);
if (ret < 0) {
dev_err(dev, "failed to claim irq %u\n", ssi->irq);
goto error_asoc_register;
}
}
fsl_ssi_debugfs_create(&ssi->dbg_stats, dev);
/* Initially configures SSI registers */
fsl_ssi_hw_init(ssi);
/* Register a platform device for older bindings or AC97 */
if (ssi->card_name[0]) {
struct device *parent = dev;
/*
* Do not set SSI dev as the parent of AC97 CODEC device since
* it does not have a DT node. Otherwise ASoC core will assume
* CODEC has the same DT node as the SSI, so it may bypass the
* dai_probe() of SSI and then cause NULL DMA data pointers.
*/
if (fsl_ssi_is_ac97(ssi))
parent = NULL;
ssi->card_pdev = platform_device_register_data(parent,
ssi->card_name, ssi->card_idx, NULL, 0);
if (IS_ERR(ssi->card_pdev)) {
ret = PTR_ERR(ssi->card_pdev);
dev_err(dev, "failed to register %s: %d\n",
ssi->card_name, ret);
goto error_sound_card;
}
}
return 0;
error_sound_card:
fsl_ssi_debugfs_remove(&ssi->dbg_stats);
error_asoc_register:
if (fsl_ssi_is_ac97(ssi))
snd_soc_set_ac97_ops(NULL);
error_ac97_ops:
if (fsl_ssi_is_ac97(ssi))
mutex_destroy(&ssi->ac97_reg_lock);
if (ssi->soc->imx)
fsl_ssi_imx_clean(pdev, ssi);
return ret;
}
static void fsl_ssi_remove(struct platform_device *pdev)
{
struct fsl_ssi *ssi = dev_get_drvdata(&pdev->dev);
fsl_ssi_debugfs_remove(&ssi->dbg_stats);
if (ssi->card_pdev)
platform_device_unregister(ssi->card_pdev);
/* Clean up SSI registers */
fsl_ssi_hw_clean(ssi);
if (ssi->soc->imx)
fsl_ssi_imx_clean(pdev, ssi);
if (fsl_ssi_is_ac97(ssi)) {
snd_soc_set_ac97_ops(NULL);
mutex_destroy(&ssi->ac97_reg_lock);
}
}
#ifdef CONFIG_PM_SLEEP
static int fsl_ssi_suspend(struct device *dev)
{
struct fsl_ssi *ssi = dev_get_drvdata(dev);
struct regmap *regs = ssi->regs;
regmap_read(regs, REG_SSI_SFCSR, &ssi->regcache_sfcsr);
regmap_read(regs, REG_SSI_SACNT, &ssi->regcache_sacnt);
regcache_cache_only(regs, true);
regcache_mark_dirty(regs);
return 0;
}
static int fsl_ssi_resume(struct device *dev)
{
struct fsl_ssi *ssi = dev_get_drvdata(dev);
struct regmap *regs = ssi->regs;
regcache_cache_only(regs, false);
regmap_update_bits(regs, REG_SSI_SFCSR,
SSI_SFCSR_RFWM1_MASK | SSI_SFCSR_TFWM1_MASK |
SSI_SFCSR_RFWM0_MASK | SSI_SFCSR_TFWM0_MASK,
ssi->regcache_sfcsr);
regmap_write(regs, REG_SSI_SACNT, ssi->regcache_sacnt);
return regcache_sync(regs);
}
#endif /* CONFIG_PM_SLEEP */
static const struct dev_pm_ops fsl_ssi_pm = {
SET_SYSTEM_SLEEP_PM_OPS(fsl_ssi_suspend, fsl_ssi_resume)
};
static struct platform_driver fsl_ssi_driver = {
.driver = {
.name = "fsl-ssi-dai",
.of_match_table = fsl_ssi_ids,
.pm = &fsl_ssi_pm,
},
.probe = fsl_ssi_probe,
.remove_new = fsl_ssi_remove,
};
module_platform_driver(fsl_ssi_driver);
MODULE_ALIAS("platform:fsl-ssi-dai");
MODULE_AUTHOR("Timur Tabi <[email protected]>");
MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/fsl/fsl_ssi.c |
// SPDX-License-Identifier: GPL-2.0+
// Copyright 2017-2021 NXP
#include <linux/dma-mapping.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/rpmsg.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/dmaengine_pcm.h>
#include <sound/soc.h>
#include "imx-pcm.h"
#include "fsl_rpmsg.h"
#include "imx-pcm-rpmsg.h"
static struct snd_pcm_hardware imx_rpmsg_pcm_hardware = {
.info = SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_BLOCK_TRANSFER |
SNDRV_PCM_INFO_BATCH |
SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_NO_PERIOD_WAKEUP |
SNDRV_PCM_INFO_PAUSE |
SNDRV_PCM_INFO_RESUME,
.buffer_bytes_max = IMX_DEFAULT_DMABUF_SIZE,
.period_bytes_min = 512,
.period_bytes_max = 65536,
.periods_min = 2,
.periods_max = 6000,
.fifo_size = 0,
};
static int imx_rpmsg_pcm_send_message(struct rpmsg_msg *msg,
struct rpmsg_info *info)
{
struct rpmsg_device *rpdev = info->rpdev;
int ret = 0;
mutex_lock(&info->msg_lock);
if (!rpdev) {
dev_err(info->dev, "rpmsg channel not ready\n");
mutex_unlock(&info->msg_lock);
return -EINVAL;
}
dev_dbg(&rpdev->dev, "send cmd %d\n", msg->s_msg.header.cmd);
if (!(msg->s_msg.header.type == MSG_TYPE_C))
reinit_completion(&info->cmd_complete);
ret = rpmsg_send(rpdev->ept, (void *)&msg->s_msg,
sizeof(struct rpmsg_s_msg));
if (ret) {
dev_err(&rpdev->dev, "rpmsg_send failed: %d\n", ret);
mutex_unlock(&info->msg_lock);
return ret;
}
/* No receive msg for TYPE_C command */
if (msg->s_msg.header.type == MSG_TYPE_C) {
mutex_unlock(&info->msg_lock);
return 0;
}
/* wait response from rpmsg */
ret = wait_for_completion_timeout(&info->cmd_complete,
msecs_to_jiffies(RPMSG_TIMEOUT));
if (!ret) {
dev_err(&rpdev->dev, "rpmsg_send cmd %d timeout!\n",
msg->s_msg.header.cmd);
mutex_unlock(&info->msg_lock);
return -ETIMEDOUT;
}
memcpy(&msg->r_msg, &info->r_msg, sizeof(struct rpmsg_r_msg));
memcpy(&info->msg[msg->r_msg.header.cmd].r_msg,
&msg->r_msg, sizeof(struct rpmsg_r_msg));
/*
* Reset the buffer pointer to be zero, actully we have
* set the buffer pointer to be zero in imx_rpmsg_terminate_all
* But if there is timer task queued in queue, after it is
* executed the buffer pointer will be changed, so need to
* reset it again with TERMINATE command.
*/
switch (msg->s_msg.header.cmd) {
case TX_TERMINATE:
info->msg[TX_POINTER].r_msg.param.buffer_offset = 0;
break;
case RX_TERMINATE:
info->msg[RX_POINTER].r_msg.param.buffer_offset = 0;
break;
default:
break;
}
dev_dbg(&rpdev->dev, "cmd:%d, resp %d\n", msg->s_msg.header.cmd,
info->r_msg.param.resp);
mutex_unlock(&info->msg_lock);
return 0;
}
static int imx_rpmsg_insert_workqueue(struct snd_pcm_substream *substream,
struct rpmsg_msg *msg,
struct rpmsg_info *info)
{
unsigned long flags;
int ret = 0;
/*
* Queue the work to workqueue.
* If the queue is full, drop the message.
*/
spin_lock_irqsave(&info->wq_lock, flags);
if (info->work_write_index != info->work_read_index) {
int index = info->work_write_index;
memcpy(&info->work_list[index].msg, msg,
sizeof(struct rpmsg_s_msg));
queue_work(info->rpmsg_wq, &info->work_list[index].work);
info->work_write_index++;
info->work_write_index %= WORK_MAX_NUM;
} else {
info->msg_drop_count[substream->stream]++;
ret = -EPIPE;
}
spin_unlock_irqrestore(&info->wq_lock, flags);
return ret;
}
static int imx_rpmsg_pcm_hw_params(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct rpmsg_info *info = dev_get_drvdata(component->dev);
struct rpmsg_msg *msg;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
msg = &info->msg[TX_HW_PARAM];
msg->s_msg.header.cmd = TX_HW_PARAM;
} else {
msg = &info->msg[RX_HW_PARAM];
msg->s_msg.header.cmd = RX_HW_PARAM;
}
msg->s_msg.param.rate = params_rate(params);
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
msg->s_msg.param.format = RPMSG_S16_LE;
break;
case SNDRV_PCM_FORMAT_S24_LE:
msg->s_msg.param.format = RPMSG_S24_LE;
break;
case SNDRV_PCM_FORMAT_DSD_U16_LE:
msg->s_msg.param.format = RPMSG_DSD_U16_LE;
break;
case SNDRV_PCM_FORMAT_DSD_U32_LE:
msg->s_msg.param.format = RPMSG_DSD_U32_LE;
break;
default:
msg->s_msg.param.format = RPMSG_S32_LE;
break;
}
switch (params_channels(params)) {
case 1:
msg->s_msg.param.channels = RPMSG_CH_LEFT;
break;
case 2:
msg->s_msg.param.channels = RPMSG_CH_STEREO;
break;
default:
msg->s_msg.param.channels = params_channels(params);
break;
}
info->send_message(msg, info);
return 0;
}
static snd_pcm_uframes_t imx_rpmsg_pcm_pointer(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct rpmsg_info *info = dev_get_drvdata(component->dev);
struct rpmsg_msg *msg;
unsigned int pos = 0;
int buffer_tail = 0;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
msg = &info->msg[TX_PERIOD_DONE + MSG_TYPE_A_NUM];
else
msg = &info->msg[RX_PERIOD_DONE + MSG_TYPE_A_NUM];
buffer_tail = msg->r_msg.param.buffer_tail;
pos = buffer_tail * snd_pcm_lib_period_bytes(substream);
return bytes_to_frames(substream->runtime, pos);
}
static void imx_rpmsg_timer_callback(struct timer_list *t)
{
struct stream_timer *stream_timer =
from_timer(stream_timer, t, timer);
struct snd_pcm_substream *substream = stream_timer->substream;
struct rpmsg_info *info = stream_timer->info;
struct rpmsg_msg *msg;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
msg = &info->msg[TX_PERIOD_DONE + MSG_TYPE_A_NUM];
msg->s_msg.header.cmd = TX_PERIOD_DONE;
} else {
msg = &info->msg[RX_PERIOD_DONE + MSG_TYPE_A_NUM];
msg->s_msg.header.cmd = RX_PERIOD_DONE;
}
imx_rpmsg_insert_workqueue(substream, msg, info);
}
static int imx_rpmsg_pcm_open(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct rpmsg_info *info = dev_get_drvdata(component->dev);
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct fsl_rpmsg *rpmsg = dev_get_drvdata(cpu_dai->dev);
struct snd_pcm_hardware pcm_hardware;
struct rpmsg_msg *msg;
int ret = 0;
int cmd;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
msg = &info->msg[TX_OPEN];
msg->s_msg.header.cmd = TX_OPEN;
/* reinitialize buffer counter*/
cmd = TX_PERIOD_DONE + MSG_TYPE_A_NUM;
info->msg[cmd].s_msg.param.buffer_tail = 0;
info->msg[cmd].r_msg.param.buffer_tail = 0;
info->msg[TX_POINTER].r_msg.param.buffer_offset = 0;
} else {
msg = &info->msg[RX_OPEN];
msg->s_msg.header.cmd = RX_OPEN;
/* reinitialize buffer counter*/
cmd = RX_PERIOD_DONE + MSG_TYPE_A_NUM;
info->msg[cmd].s_msg.param.buffer_tail = 0;
info->msg[cmd].r_msg.param.buffer_tail = 0;
info->msg[RX_POINTER].r_msg.param.buffer_offset = 0;
}
info->send_message(msg, info);
pcm_hardware = imx_rpmsg_pcm_hardware;
pcm_hardware.buffer_bytes_max = rpmsg->buffer_size;
pcm_hardware.period_bytes_max = pcm_hardware.buffer_bytes_max / 2;
snd_soc_set_runtime_hwparams(substream, &pcm_hardware);
ret = snd_pcm_hw_constraint_integer(substream->runtime,
SNDRV_PCM_HW_PARAM_PERIODS);
if (ret < 0)
return ret;
info->msg_drop_count[substream->stream] = 0;
/* Create timer*/
info->stream_timer[substream->stream].info = info;
info->stream_timer[substream->stream].substream = substream;
timer_setup(&info->stream_timer[substream->stream].timer,
imx_rpmsg_timer_callback, 0);
return ret;
}
static int imx_rpmsg_pcm_close(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct rpmsg_info *info = dev_get_drvdata(component->dev);
struct rpmsg_msg *msg;
/* Flush work in workqueue to make TX_CLOSE is the last message */
flush_workqueue(info->rpmsg_wq);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
msg = &info->msg[TX_CLOSE];
msg->s_msg.header.cmd = TX_CLOSE;
} else {
msg = &info->msg[RX_CLOSE];
msg->s_msg.header.cmd = RX_CLOSE;
}
info->send_message(msg, info);
del_timer(&info->stream_timer[substream->stream].timer);
rtd->dai_link->ignore_suspend = 0;
if (info->msg_drop_count[substream->stream])
dev_warn(rtd->dev, "Msg is dropped!, number is %d\n",
info->msg_drop_count[substream->stream]);
return 0;
}
static int imx_rpmsg_pcm_prepare(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct fsl_rpmsg *rpmsg = dev_get_drvdata(cpu_dai->dev);
/*
* NON-MMAP mode, NONBLOCK, Version 2, enable lpa in dts
* four conditions to determine the lpa is enabled.
*/
if ((runtime->access == SNDRV_PCM_ACCESS_RW_INTERLEAVED ||
runtime->access == SNDRV_PCM_ACCESS_RW_NONINTERLEAVED) &&
rpmsg->enable_lpa) {
/*
* Ignore suspend operation in low power mode
* M core will continue playback music on A core suspend.
*/
rtd->dai_link->ignore_suspend = 1;
rpmsg->force_lpa = 1;
} else {
rpmsg->force_lpa = 0;
}
return 0;
}
static void imx_rpmsg_pcm_dma_complete(void *arg)
{
struct snd_pcm_substream *substream = arg;
snd_pcm_period_elapsed(substream);
}
static int imx_rpmsg_prepare_and_submit(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct rpmsg_info *info = dev_get_drvdata(component->dev);
struct rpmsg_msg *msg;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
msg = &info->msg[TX_BUFFER];
msg->s_msg.header.cmd = TX_BUFFER;
} else {
msg = &info->msg[RX_BUFFER];
msg->s_msg.header.cmd = RX_BUFFER;
}
/* Send buffer address and buffer size */
msg->s_msg.param.buffer_addr = substream->runtime->dma_addr;
msg->s_msg.param.buffer_size = snd_pcm_lib_buffer_bytes(substream);
msg->s_msg.param.period_size = snd_pcm_lib_period_bytes(substream);
msg->s_msg.param.buffer_tail = 0;
info->num_period[substream->stream] = msg->s_msg.param.buffer_size /
msg->s_msg.param.period_size;
info->callback[substream->stream] = imx_rpmsg_pcm_dma_complete;
info->callback_param[substream->stream] = substream;
return imx_rpmsg_insert_workqueue(substream, msg, info);
}
static int imx_rpmsg_async_issue_pending(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct rpmsg_info *info = dev_get_drvdata(component->dev);
struct rpmsg_msg *msg;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
msg = &info->msg[TX_START];
msg->s_msg.header.cmd = TX_START;
} else {
msg = &info->msg[RX_START];
msg->s_msg.header.cmd = RX_START;
}
return imx_rpmsg_insert_workqueue(substream, msg, info);
}
static int imx_rpmsg_restart(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct rpmsg_info *info = dev_get_drvdata(component->dev);
struct rpmsg_msg *msg;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
msg = &info->msg[TX_RESTART];
msg->s_msg.header.cmd = TX_RESTART;
} else {
msg = &info->msg[RX_RESTART];
msg->s_msg.header.cmd = RX_RESTART;
}
return imx_rpmsg_insert_workqueue(substream, msg, info);
}
static int imx_rpmsg_pause(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct rpmsg_info *info = dev_get_drvdata(component->dev);
struct rpmsg_msg *msg;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
msg = &info->msg[TX_PAUSE];
msg->s_msg.header.cmd = TX_PAUSE;
} else {
msg = &info->msg[RX_PAUSE];
msg->s_msg.header.cmd = RX_PAUSE;
}
return imx_rpmsg_insert_workqueue(substream, msg, info);
}
static int imx_rpmsg_terminate_all(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct rpmsg_info *info = dev_get_drvdata(component->dev);
struct rpmsg_msg *msg;
int cmd;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
msg = &info->msg[TX_TERMINATE];
msg->s_msg.header.cmd = TX_TERMINATE;
/* Clear buffer count*/
cmd = TX_PERIOD_DONE + MSG_TYPE_A_NUM;
info->msg[cmd].s_msg.param.buffer_tail = 0;
info->msg[cmd].r_msg.param.buffer_tail = 0;
info->msg[TX_POINTER].r_msg.param.buffer_offset = 0;
} else {
msg = &info->msg[RX_TERMINATE];
msg->s_msg.header.cmd = RX_TERMINATE;
/* Clear buffer count*/
cmd = RX_PERIOD_DONE + MSG_TYPE_A_NUM;
info->msg[cmd].s_msg.param.buffer_tail = 0;
info->msg[cmd].r_msg.param.buffer_tail = 0;
info->msg[RX_POINTER].r_msg.param.buffer_offset = 0;
}
del_timer(&info->stream_timer[substream->stream].timer);
return imx_rpmsg_insert_workqueue(substream, msg, info);
}
static int imx_rpmsg_pcm_trigger(struct snd_soc_component *component,
struct snd_pcm_substream *substream, int cmd)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct fsl_rpmsg *rpmsg = dev_get_drvdata(cpu_dai->dev);
int ret = 0;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
ret = imx_rpmsg_prepare_and_submit(component, substream);
if (ret)
return ret;
ret = imx_rpmsg_async_issue_pending(component, substream);
break;
case SNDRV_PCM_TRIGGER_RESUME:
if (rpmsg->force_lpa)
break;
fallthrough;
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
ret = imx_rpmsg_restart(component, substream);
break;
case SNDRV_PCM_TRIGGER_SUSPEND:
if (!rpmsg->force_lpa) {
if (runtime->info & SNDRV_PCM_INFO_PAUSE)
ret = imx_rpmsg_pause(component, substream);
else
ret = imx_rpmsg_terminate_all(component, substream);
}
break;
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
ret = imx_rpmsg_pause(component, substream);
break;
case SNDRV_PCM_TRIGGER_STOP:
ret = imx_rpmsg_terminate_all(component, substream);
break;
default:
return -EINVAL;
}
if (ret)
return ret;
return 0;
}
/*
* imx_rpmsg_pcm_ack
*
* Send the period index to M core through rpmsg, but not send
* all the period index to M core, reduce some unnessesary msg
* to reduce the pressure of rpmsg bandwidth.
*/
static int imx_rpmsg_pcm_ack(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct fsl_rpmsg *rpmsg = dev_get_drvdata(cpu_dai->dev);
struct rpmsg_info *info = dev_get_drvdata(component->dev);
snd_pcm_uframes_t period_size = runtime->period_size;
snd_pcm_sframes_t avail;
struct timer_list *timer;
struct rpmsg_msg *msg;
unsigned long flags;
int buffer_tail = 0;
int written_num;
if (!rpmsg->force_lpa)
return 0;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
msg = &info->msg[TX_PERIOD_DONE + MSG_TYPE_A_NUM];
msg->s_msg.header.cmd = TX_PERIOD_DONE;
} else {
msg = &info->msg[RX_PERIOD_DONE + MSG_TYPE_A_NUM];
msg->s_msg.header.cmd = RX_PERIOD_DONE;
}
msg->s_msg.header.type = MSG_TYPE_C;
buffer_tail = (frames_to_bytes(runtime, runtime->control->appl_ptr) %
snd_pcm_lib_buffer_bytes(substream));
buffer_tail = buffer_tail / snd_pcm_lib_period_bytes(substream);
/* There is update for period index */
if (buffer_tail != msg->s_msg.param.buffer_tail) {
written_num = buffer_tail - msg->s_msg.param.buffer_tail;
if (written_num < 0)
written_num += runtime->periods;
msg->s_msg.param.buffer_tail = buffer_tail;
/* The notification message is updated to latest */
spin_lock_irqsave(&info->lock[substream->stream], flags);
memcpy(&info->notify[substream->stream], msg,
sizeof(struct rpmsg_s_msg));
info->notify_updated[substream->stream] = true;
spin_unlock_irqrestore(&info->lock[substream->stream], flags);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
avail = snd_pcm_playback_hw_avail(runtime);
else
avail = snd_pcm_capture_hw_avail(runtime);
timer = &info->stream_timer[substream->stream].timer;
/*
* If the data in the buffer is less than one period before
* this fill, which means the data may not enough on M
* core side, we need to send message immediately to let
* M core know the pointer is updated.
* if there is more than one period data in the buffer before
* this fill, which means the data is enough on M core side,
* we can delay one period (using timer) to send the message
* for reduce the message number in workqueue, because the
* pointer may be updated by ack function later, we can
* send latest pointer to M core side.
*/
if ((avail - written_num * period_size) <= period_size) {
imx_rpmsg_insert_workqueue(substream, msg, info);
} else if (rpmsg->force_lpa && !timer_pending(timer)) {
int time_msec;
time_msec = (int)(runtime->period_size * 1000 / runtime->rate);
mod_timer(timer, jiffies + msecs_to_jiffies(time_msec));
}
}
return 0;
}
static int imx_rpmsg_pcm_new(struct snd_soc_component *component,
struct snd_soc_pcm_runtime *rtd)
{
struct snd_card *card = rtd->card->snd_card;
struct snd_pcm *pcm = rtd->pcm;
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct fsl_rpmsg *rpmsg = dev_get_drvdata(cpu_dai->dev);
int ret;
ret = dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(32));
if (ret)
return ret;
return snd_pcm_set_fixed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV_WC,
pcm->card->dev, rpmsg->buffer_size);
}
static const struct snd_soc_component_driver imx_rpmsg_soc_component = {
.name = IMX_PCM_DRV_NAME,
.pcm_construct = imx_rpmsg_pcm_new,
.open = imx_rpmsg_pcm_open,
.close = imx_rpmsg_pcm_close,
.hw_params = imx_rpmsg_pcm_hw_params,
.trigger = imx_rpmsg_pcm_trigger,
.pointer = imx_rpmsg_pcm_pointer,
.ack = imx_rpmsg_pcm_ack,
.prepare = imx_rpmsg_pcm_prepare,
};
static void imx_rpmsg_pcm_work(struct work_struct *work)
{
struct work_of_rpmsg *work_of_rpmsg;
bool is_notification = false;
struct rpmsg_info *info;
struct rpmsg_msg msg;
unsigned long flags;
work_of_rpmsg = container_of(work, struct work_of_rpmsg, work);
info = work_of_rpmsg->info;
/*
* Every work in the work queue, first we check if there
* is update for period is filled, because there may be not
* enough data in M core side, need to let M core know
* data is updated immediately.
*/
spin_lock_irqsave(&info->lock[TX], flags);
if (info->notify_updated[TX]) {
memcpy(&msg, &info->notify[TX], sizeof(struct rpmsg_s_msg));
info->notify_updated[TX] = false;
spin_unlock_irqrestore(&info->lock[TX], flags);
info->send_message(&msg, info);
} else {
spin_unlock_irqrestore(&info->lock[TX], flags);
}
spin_lock_irqsave(&info->lock[RX], flags);
if (info->notify_updated[RX]) {
memcpy(&msg, &info->notify[RX], sizeof(struct rpmsg_s_msg));
info->notify_updated[RX] = false;
spin_unlock_irqrestore(&info->lock[RX], flags);
info->send_message(&msg, info);
} else {
spin_unlock_irqrestore(&info->lock[RX], flags);
}
/* Skip the notification message for it has been processed above */
if (work_of_rpmsg->msg.s_msg.header.type == MSG_TYPE_C &&
(work_of_rpmsg->msg.s_msg.header.cmd == TX_PERIOD_DONE ||
work_of_rpmsg->msg.s_msg.header.cmd == RX_PERIOD_DONE))
is_notification = true;
if (!is_notification)
info->send_message(&work_of_rpmsg->msg, info);
/* update read index */
spin_lock_irqsave(&info->wq_lock, flags);
info->work_read_index++;
info->work_read_index %= WORK_MAX_NUM;
spin_unlock_irqrestore(&info->wq_lock, flags);
}
static int imx_rpmsg_pcm_probe(struct platform_device *pdev)
{
struct snd_soc_component *component;
struct rpmsg_info *info;
int ret, i;
info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
if (!info)
return -ENOMEM;
platform_set_drvdata(pdev, info);
info->rpdev = container_of(pdev->dev.parent, struct rpmsg_device, dev);
info->dev = &pdev->dev;
/* Setup work queue */
info->rpmsg_wq = alloc_ordered_workqueue(info->rpdev->id.name,
WQ_HIGHPRI |
WQ_UNBOUND |
WQ_FREEZABLE);
if (!info->rpmsg_wq) {
dev_err(&pdev->dev, "workqueue create failed\n");
return -ENOMEM;
}
/* Write index initialize 1, make it differ with the read index */
info->work_write_index = 1;
info->send_message = imx_rpmsg_pcm_send_message;
for (i = 0; i < WORK_MAX_NUM; i++) {
INIT_WORK(&info->work_list[i].work, imx_rpmsg_pcm_work);
info->work_list[i].info = info;
}
/* Initialize msg */
for (i = 0; i < MSG_MAX_NUM; i++) {
info->msg[i].s_msg.header.cate = IMX_RPMSG_AUDIO;
info->msg[i].s_msg.header.major = IMX_RMPSG_MAJOR;
info->msg[i].s_msg.header.minor = IMX_RMPSG_MINOR;
info->msg[i].s_msg.header.type = MSG_TYPE_A;
info->msg[i].s_msg.param.audioindex = 0;
}
init_completion(&info->cmd_complete);
mutex_init(&info->msg_lock);
spin_lock_init(&info->lock[TX]);
spin_lock_init(&info->lock[RX]);
spin_lock_init(&info->wq_lock);
ret = devm_snd_soc_register_component(&pdev->dev,
&imx_rpmsg_soc_component,
NULL, 0);
if (ret)
goto fail;
component = snd_soc_lookup_component(&pdev->dev, NULL);
if (!component) {
ret = -EINVAL;
goto fail;
}
/* platform component name is used by machine driver to link with */
component->name = info->rpdev->id.name;
#ifdef CONFIG_DEBUG_FS
component->debugfs_prefix = "rpmsg";
#endif
return 0;
fail:
if (info->rpmsg_wq)
destroy_workqueue(info->rpmsg_wq);
return ret;
}
static void imx_rpmsg_pcm_remove(struct platform_device *pdev)
{
struct rpmsg_info *info = platform_get_drvdata(pdev);
if (info->rpmsg_wq)
destroy_workqueue(info->rpmsg_wq);
}
#ifdef CONFIG_PM
static int imx_rpmsg_pcm_runtime_resume(struct device *dev)
{
struct rpmsg_info *info = dev_get_drvdata(dev);
cpu_latency_qos_add_request(&info->pm_qos_req, 0);
return 0;
}
static int imx_rpmsg_pcm_runtime_suspend(struct device *dev)
{
struct rpmsg_info *info = dev_get_drvdata(dev);
cpu_latency_qos_remove_request(&info->pm_qos_req);
return 0;
}
#endif
#ifdef CONFIG_PM_SLEEP
static int imx_rpmsg_pcm_suspend(struct device *dev)
{
struct rpmsg_info *info = dev_get_drvdata(dev);
struct rpmsg_msg *rpmsg_tx;
struct rpmsg_msg *rpmsg_rx;
rpmsg_tx = &info->msg[TX_SUSPEND];
rpmsg_rx = &info->msg[RX_SUSPEND];
rpmsg_tx->s_msg.header.cmd = TX_SUSPEND;
info->send_message(rpmsg_tx, info);
rpmsg_rx->s_msg.header.cmd = RX_SUSPEND;
info->send_message(rpmsg_rx, info);
return 0;
}
static int imx_rpmsg_pcm_resume(struct device *dev)
{
struct rpmsg_info *info = dev_get_drvdata(dev);
struct rpmsg_msg *rpmsg_tx;
struct rpmsg_msg *rpmsg_rx;
rpmsg_tx = &info->msg[TX_RESUME];
rpmsg_rx = &info->msg[RX_RESUME];
rpmsg_tx->s_msg.header.cmd = TX_RESUME;
info->send_message(rpmsg_tx, info);
rpmsg_rx->s_msg.header.cmd = RX_RESUME;
info->send_message(rpmsg_rx, info);
return 0;
}
#endif /* CONFIG_PM_SLEEP */
static const struct dev_pm_ops imx_rpmsg_pcm_pm_ops = {
SET_RUNTIME_PM_OPS(imx_rpmsg_pcm_runtime_suspend,
imx_rpmsg_pcm_runtime_resume,
NULL)
SET_SYSTEM_SLEEP_PM_OPS(imx_rpmsg_pcm_suspend,
imx_rpmsg_pcm_resume)
};
static struct platform_driver imx_pcm_rpmsg_driver = {
.probe = imx_rpmsg_pcm_probe,
.remove_new = imx_rpmsg_pcm_remove,
.driver = {
.name = IMX_PCM_DRV_NAME,
.pm = &imx_rpmsg_pcm_pm_ops,
},
};
module_platform_driver(imx_pcm_rpmsg_driver);
MODULE_DESCRIPTION("Freescale SoC Audio RPMSG PCM interface");
MODULE_AUTHOR("Shengjiu Wang <[email protected]>");
MODULE_ALIAS("platform:" IMX_PCM_DRV_NAME);
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/fsl/imx-pcm-rpmsg.c |
// SPDX-License-Identifier: GPL-2.0+
// Copyright 2020 NXP
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/dmaengine.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/of_address.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/time.h>
#include <linux/pm_qos.h>
#include <sound/core.h>
#include <sound/dmaengine_pcm.h>
#include <sound/pcm_params.h>
#include <linux/dma-mapping.h>
#include "fsl_aud2htx.h"
#include "imx-pcm.h"
static int fsl_aud2htx_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct fsl_aud2htx *aud2htx = snd_soc_dai_get_drvdata(dai);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
regmap_update_bits(aud2htx->regmap, AUD2HTX_CTRL,
AUD2HTX_CTRL_EN, AUD2HTX_CTRL_EN);
regmap_update_bits(aud2htx->regmap, AUD2HTX_CTRL_EXT,
AUD2HTX_CTRE_DE, AUD2HTX_CTRE_DE);
break;
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
regmap_update_bits(aud2htx->regmap, AUD2HTX_CTRL_EXT,
AUD2HTX_CTRE_DE, 0);
regmap_update_bits(aud2htx->regmap, AUD2HTX_CTRL,
AUD2HTX_CTRL_EN, 0);
break;
default:
return -EINVAL;
}
return 0;
}
static int fsl_aud2htx_dai_probe(struct snd_soc_dai *cpu_dai)
{
struct fsl_aud2htx *aud2htx = dev_get_drvdata(cpu_dai->dev);
/* DMA request when number of entries < WTMK_LOW */
regmap_update_bits(aud2htx->regmap, AUD2HTX_CTRL_EXT,
AUD2HTX_CTRE_DT_MASK, 0);
/* Disable interrupts*/
regmap_update_bits(aud2htx->regmap, AUD2HTX_IRQ_MASK,
AUD2HTX_WM_HIGH_IRQ_MASK |
AUD2HTX_WM_LOW_IRQ_MASK |
AUD2HTX_OVF_MASK,
AUD2HTX_WM_HIGH_IRQ_MASK |
AUD2HTX_WM_LOW_IRQ_MASK |
AUD2HTX_OVF_MASK);
/* Configure watermark */
regmap_update_bits(aud2htx->regmap, AUD2HTX_CTRL_EXT,
AUD2HTX_CTRE_WL_MASK,
AUD2HTX_WTMK_LOW << AUD2HTX_CTRE_WL_SHIFT);
regmap_update_bits(aud2htx->regmap, AUD2HTX_CTRL_EXT,
AUD2HTX_CTRE_WH_MASK,
AUD2HTX_WTMK_HIGH << AUD2HTX_CTRE_WH_SHIFT);
snd_soc_dai_init_dma_data(cpu_dai, &aud2htx->dma_params_tx,
&aud2htx->dma_params_rx);
return 0;
}
static const struct snd_soc_dai_ops fsl_aud2htx_dai_ops = {
.probe = fsl_aud2htx_dai_probe,
.trigger = fsl_aud2htx_trigger,
};
static struct snd_soc_dai_driver fsl_aud2htx_dai = {
.playback = {
.stream_name = "CPU-Playback",
.channels_min = 1,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_32000 |
SNDRV_PCM_RATE_44100 |
SNDRV_PCM_RATE_48000 |
SNDRV_PCM_RATE_88200 |
SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_176400 |
SNDRV_PCM_RATE_192000,
.formats = FSL_AUD2HTX_FORMATS,
},
.ops = &fsl_aud2htx_dai_ops,
};
static const struct snd_soc_component_driver fsl_aud2htx_component = {
.name = "fsl-aud2htx",
.legacy_dai_naming = 1,
};
static const struct reg_default fsl_aud2htx_reg_defaults[] = {
{AUD2HTX_CTRL, 0x00000000},
{AUD2HTX_CTRL_EXT, 0x00000000},
{AUD2HTX_WR, 0x00000000},
{AUD2HTX_STATUS, 0x00000000},
{AUD2HTX_IRQ_NOMASK, 0x00000000},
{AUD2HTX_IRQ_MASKED, 0x00000000},
{AUD2HTX_IRQ_MASK, 0x00000000},
};
static bool fsl_aud2htx_readable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case AUD2HTX_CTRL:
case AUD2HTX_CTRL_EXT:
case AUD2HTX_STATUS:
case AUD2HTX_IRQ_NOMASK:
case AUD2HTX_IRQ_MASKED:
case AUD2HTX_IRQ_MASK:
return true;
default:
return false;
}
}
static bool fsl_aud2htx_writeable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case AUD2HTX_CTRL:
case AUD2HTX_CTRL_EXT:
case AUD2HTX_WR:
case AUD2HTX_IRQ_NOMASK:
case AUD2HTX_IRQ_MASKED:
case AUD2HTX_IRQ_MASK:
return true;
default:
return false;
}
}
static bool fsl_aud2htx_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case AUD2HTX_STATUS:
case AUD2HTX_IRQ_NOMASK:
case AUD2HTX_IRQ_MASKED:
return true;
default:
return false;
}
}
static const struct regmap_config fsl_aud2htx_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = AUD2HTX_IRQ_MASK,
.reg_defaults = fsl_aud2htx_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(fsl_aud2htx_reg_defaults),
.readable_reg = fsl_aud2htx_readable_reg,
.volatile_reg = fsl_aud2htx_volatile_reg,
.writeable_reg = fsl_aud2htx_writeable_reg,
.cache_type = REGCACHE_RBTREE,
};
static const struct of_device_id fsl_aud2htx_dt_ids[] = {
{ .compatible = "fsl,imx8mp-aud2htx",},
{}
};
MODULE_DEVICE_TABLE(of, fsl_aud2htx_dt_ids);
static irqreturn_t fsl_aud2htx_isr(int irq, void *dev_id)
{
return IRQ_HANDLED;
}
static int fsl_aud2htx_probe(struct platform_device *pdev)
{
struct fsl_aud2htx *aud2htx;
struct resource *res;
void __iomem *regs;
int ret, irq;
aud2htx = devm_kzalloc(&pdev->dev, sizeof(*aud2htx), GFP_KERNEL);
if (!aud2htx)
return -ENOMEM;
aud2htx->pdev = pdev;
regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(regs))
return PTR_ERR(regs);
aud2htx->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
&fsl_aud2htx_regmap_config);
if (IS_ERR(aud2htx->regmap)) {
dev_err(&pdev->dev, "failed to init regmap");
return PTR_ERR(aud2htx->regmap);
}
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
ret = devm_request_irq(&pdev->dev, irq, fsl_aud2htx_isr, 0,
dev_name(&pdev->dev), aud2htx);
if (ret) {
dev_err(&pdev->dev, "failed to claim irq %u: %d\n", irq, ret);
return ret;
}
aud2htx->bus_clk = devm_clk_get(&pdev->dev, "bus");
if (IS_ERR(aud2htx->bus_clk)) {
dev_err(&pdev->dev, "failed to get mem clock\n");
return PTR_ERR(aud2htx->bus_clk);
}
aud2htx->dma_params_tx.chan_name = "tx";
aud2htx->dma_params_tx.maxburst = AUD2HTX_MAXBURST;
aud2htx->dma_params_tx.addr = res->start + AUD2HTX_WR;
platform_set_drvdata(pdev, aud2htx);
pm_runtime_enable(&pdev->dev);
regcache_cache_only(aud2htx->regmap, true);
/*
* Register platform component before registering cpu dai for there
* is not defer probe for platform component in snd_soc_add_pcm_runtime().
*/
ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
if (ret) {
dev_err(&pdev->dev, "failed to pcm register\n");
pm_runtime_disable(&pdev->dev);
return ret;
}
ret = devm_snd_soc_register_component(&pdev->dev,
&fsl_aud2htx_component,
&fsl_aud2htx_dai, 1);
if (ret) {
dev_err(&pdev->dev, "failed to register ASoC DAI\n");
pm_runtime_disable(&pdev->dev);
return ret;
}
return ret;
}
static void fsl_aud2htx_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
}
static int __maybe_unused fsl_aud2htx_runtime_suspend(struct device *dev)
{
struct fsl_aud2htx *aud2htx = dev_get_drvdata(dev);
regcache_cache_only(aud2htx->regmap, true);
clk_disable_unprepare(aud2htx->bus_clk);
return 0;
}
static int __maybe_unused fsl_aud2htx_runtime_resume(struct device *dev)
{
struct fsl_aud2htx *aud2htx = dev_get_drvdata(dev);
int ret;
ret = clk_prepare_enable(aud2htx->bus_clk);
if (ret)
return ret;
regcache_cache_only(aud2htx->regmap, false);
regcache_mark_dirty(aud2htx->regmap);
regcache_sync(aud2htx->regmap);
return 0;
}
static const struct dev_pm_ops fsl_aud2htx_pm_ops = {
SET_RUNTIME_PM_OPS(fsl_aud2htx_runtime_suspend,
fsl_aud2htx_runtime_resume,
NULL)
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
};
static struct platform_driver fsl_aud2htx_driver = {
.probe = fsl_aud2htx_probe,
.remove_new = fsl_aud2htx_remove,
.driver = {
.name = "fsl-aud2htx",
.pm = &fsl_aud2htx_pm_ops,
.of_match_table = fsl_aud2htx_dt_ids,
},
};
module_platform_driver(fsl_aud2htx_driver);
MODULE_AUTHOR("Shengjiu Wang <[email protected]>");
MODULE_DESCRIPTION("NXP AUD2HTX driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/fsl/fsl_aud2htx.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* imx-pcm-dma-mx2.c -- ALSA Soc Audio Layer
*
* Copyright 2009 Sascha Hauer <[email protected]>
*
* This code is based on code copyrighted by Freescale,
* Liam Girdwood, Javier Martin and probably others.
*/
#include <linux/platform_device.h>
#include <linux/dmaengine.h>
#include <linux/types.h>
#include <linux/module.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/soc.h>
#include <sound/dmaengine_pcm.h>
#include "imx-pcm.h"
static bool filter(struct dma_chan *chan, void *param)
{
if (!imx_dma_is_general_purpose(chan))
return false;
chan->private = param;
return true;
}
static const struct snd_dmaengine_pcm_config imx_dmaengine_pcm_config = {
.prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
.compat_filter_fn = filter,
};
int imx_pcm_dma_init(struct platform_device *pdev)
{
struct snd_dmaengine_pcm_config *config;
config = devm_kzalloc(&pdev->dev,
sizeof(struct snd_dmaengine_pcm_config), GFP_KERNEL);
if (!config)
return -ENOMEM;
*config = imx_dmaengine_pcm_config;
return devm_snd_dmaengine_pcm_register(&pdev->dev,
config,
SND_DMAENGINE_PCM_FLAG_COMPAT);
}
EXPORT_SYMBOL_GPL(imx_pcm_dma_init);
MODULE_LICENSE("GPL");
| linux-master | sound/soc/fsl/imx-pcm-dma.c |
// SPDX-License-Identifier: GPL-2.0
//
// Freescale P1022DS ALSA SoC Machine driver
//
// Author: Timur Tabi <[email protected]>
//
// Copyright 2010 Freescale Semiconductor, Inc.
#include <linux/module.h>
#include <linux/fsl/guts.h>
#include <linux/interrupt.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/slab.h>
#include <sound/soc.h>
#include "fsl_dma.h"
#include "fsl_ssi.h"
#include "fsl_utils.h"
/* P1022-specific PMUXCR and DMUXCR bit definitions */
#define CCSR_GUTS_PMUXCR_UART0_I2C1_MASK 0x0001c000
#define CCSR_GUTS_PMUXCR_UART0_I2C1_UART0_SSI 0x00010000
#define CCSR_GUTS_PMUXCR_UART0_I2C1_SSI 0x00018000
#define CCSR_GUTS_PMUXCR_SSI_DMA_TDM_MASK 0x00000c00
#define CCSR_GUTS_PMUXCR_SSI_DMA_TDM_SSI 0x00000000
#define CCSR_GUTS_DMUXCR_PAD 1 /* DMA controller/channel set to pad */
#define CCSR_GUTS_DMUXCR_SSI 2 /* DMA controller/channel set to SSI */
/*
* Set the DMACR register in the GUTS
*
* The DMACR register determines the source of initiated transfers for each
* channel on each DMA controller. Rather than have a bunch of repetitive
* macros for the bit patterns, we just have a function that calculates
* them.
*
* guts: Pointer to GUTS structure
* co: The DMA controller (0 or 1)
* ch: The channel on the DMA controller (0, 1, 2, or 3)
* device: The device to set as the target (CCSR_GUTS_DMUXCR_xxx)
*/
static inline void guts_set_dmuxcr(struct ccsr_guts __iomem *guts,
unsigned int co, unsigned int ch, unsigned int device)
{
unsigned int shift = 16 + (8 * (1 - co) + 2 * (3 - ch));
clrsetbits_be32(&guts->dmuxcr, 3 << shift, device << shift);
}
/* There's only one global utilities register */
static phys_addr_t guts_phys;
/**
* machine_data: machine-specific ASoC device data
*
* This structure contains data for a single sound platform device on an
* P1022 DS. Some of the data is taken from the device tree.
*/
struct machine_data {
struct snd_soc_dai_link dai[2];
struct snd_soc_card card;
unsigned int dai_format;
unsigned int codec_clk_direction;
unsigned int cpu_clk_direction;
unsigned int clk_frequency;
unsigned int ssi_id; /* 0 = SSI1, 1 = SSI2, etc */
unsigned int dma_id[2]; /* 0 = DMA1, 1 = DMA2, etc */
unsigned int dma_channel_id[2]; /* 0 = ch 0, 1 = ch 1, etc*/
char platform_name[2][DAI_NAME_SIZE]; /* One for each DMA channel */
};
/**
* p1022_ds_machine_probe: initialize the board
*
* This function is used to initialize the board-specific hardware.
*
* Here we program the DMACR and PMUXCR registers.
*/
static int p1022_ds_machine_probe(struct snd_soc_card *card)
{
struct machine_data *mdata =
container_of(card, struct machine_data, card);
struct ccsr_guts __iomem *guts;
guts = ioremap(guts_phys, sizeof(struct ccsr_guts));
if (!guts) {
dev_err(card->dev, "could not map global utilities\n");
return -ENOMEM;
}
/* Enable SSI Tx signal */
clrsetbits_be32(&guts->pmuxcr, CCSR_GUTS_PMUXCR_UART0_I2C1_MASK,
CCSR_GUTS_PMUXCR_UART0_I2C1_UART0_SSI);
/* Enable SSI Rx signal */
clrsetbits_be32(&guts->pmuxcr, CCSR_GUTS_PMUXCR_SSI_DMA_TDM_MASK,
CCSR_GUTS_PMUXCR_SSI_DMA_TDM_SSI);
/* Enable DMA Channel for SSI */
guts_set_dmuxcr(guts, mdata->dma_id[0], mdata->dma_channel_id[0],
CCSR_GUTS_DMUXCR_SSI);
guts_set_dmuxcr(guts, mdata->dma_id[1], mdata->dma_channel_id[1],
CCSR_GUTS_DMUXCR_SSI);
iounmap(guts);
return 0;
}
/**
* p1022_ds_startup: program the board with various hardware parameters
*
* This function takes board-specific information, like clock frequencies
* and serial data formats, and passes that information to the codec and
* transport drivers.
*/
static int p1022_ds_startup(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct machine_data *mdata =
container_of(rtd->card, struct machine_data, card);
struct device *dev = rtd->card->dev;
int ret = 0;
/* Tell the codec driver what the serial protocol is. */
ret = snd_soc_dai_set_fmt(asoc_rtd_to_codec(rtd, 0), mdata->dai_format);
if (ret < 0) {
dev_err(dev, "could not set codec driver audio format\n");
return ret;
}
/*
* Tell the codec driver what the MCLK frequency is, and whether it's
* a slave or master.
*/
ret = snd_soc_dai_set_sysclk(asoc_rtd_to_codec(rtd, 0), 0, mdata->clk_frequency,
mdata->codec_clk_direction);
if (ret < 0) {
dev_err(dev, "could not set codec driver clock params\n");
return ret;
}
return 0;
}
/**
* p1022_ds_machine_remove: Remove the sound device
*
* This function is called to remove the sound device for one SSI. We
* de-program the DMACR and PMUXCR register.
*/
static int p1022_ds_machine_remove(struct snd_soc_card *card)
{
struct machine_data *mdata =
container_of(card, struct machine_data, card);
struct ccsr_guts __iomem *guts;
guts = ioremap(guts_phys, sizeof(struct ccsr_guts));
if (!guts) {
dev_err(card->dev, "could not map global utilities\n");
return -ENOMEM;
}
/* Restore the signal routing */
clrbits32(&guts->pmuxcr, CCSR_GUTS_PMUXCR_UART0_I2C1_MASK);
clrbits32(&guts->pmuxcr, CCSR_GUTS_PMUXCR_SSI_DMA_TDM_MASK);
guts_set_dmuxcr(guts, mdata->dma_id[0], mdata->dma_channel_id[0], 0);
guts_set_dmuxcr(guts, mdata->dma_id[1], mdata->dma_channel_id[1], 0);
iounmap(guts);
return 0;
}
/**
* p1022_ds_ops: ASoC machine driver operations
*/
static const struct snd_soc_ops p1022_ds_ops = {
.startup = p1022_ds_startup,
};
/**
* p1022_ds_probe: platform probe function for the machine driver
*
* Although this is a machine driver, the SSI node is the "master" node with
* respect to audio hardware connections. Therefore, we create a new ASoC
* device for each new SSI node that has a codec attached.
*/
static int p1022_ds_probe(struct platform_device *pdev)
{
struct device *dev = pdev->dev.parent;
/* ssi_pdev is the platform device for the SSI node that probed us */
struct platform_device *ssi_pdev = to_platform_device(dev);
struct device_node *np = ssi_pdev->dev.of_node;
struct device_node *codec_np = NULL;
struct machine_data *mdata;
struct snd_soc_dai_link_component *comp;
int ret;
const char *sprop;
const u32 *iprop;
/* Find the codec node for this SSI. */
codec_np = of_parse_phandle(np, "codec-handle", 0);
if (!codec_np) {
dev_err(dev, "could not find codec node\n");
return -EINVAL;
}
mdata = kzalloc(sizeof(struct machine_data), GFP_KERNEL);
if (!mdata) {
ret = -ENOMEM;
goto error_put;
}
comp = devm_kzalloc(&pdev->dev, 6 * sizeof(*comp), GFP_KERNEL);
if (!comp) {
ret = -ENOMEM;
goto error_put;
}
mdata->dai[0].cpus = &comp[0];
mdata->dai[0].codecs = &comp[1];
mdata->dai[0].platforms = &comp[2];
mdata->dai[0].num_cpus = 1;
mdata->dai[0].num_codecs = 1;
mdata->dai[0].num_platforms = 1;
mdata->dai[1].cpus = &comp[3];
mdata->dai[1].codecs = &comp[4];
mdata->dai[1].platforms = &comp[5];
mdata->dai[1].num_cpus = 1;
mdata->dai[1].num_codecs = 1;
mdata->dai[1].num_platforms = 1;
mdata->dai[0].cpus->dai_name = dev_name(&ssi_pdev->dev);
mdata->dai[0].ops = &p1022_ds_ops;
/* ASoC core can match codec with device node */
mdata->dai[0].codecs->of_node = codec_np;
/* We register two DAIs per SSI, one for playback and the other for
* capture. We support codecs that have separate DAIs for both playback
* and capture.
*/
memcpy(&mdata->dai[1], &mdata->dai[0], sizeof(struct snd_soc_dai_link));
/* The DAI names from the codec (snd_soc_dai_driver.name) */
mdata->dai[0].codecs->dai_name = "wm8776-hifi-playback";
mdata->dai[1].codecs->dai_name = "wm8776-hifi-capture";
/* Get the device ID */
iprop = of_get_property(np, "cell-index", NULL);
if (!iprop) {
dev_err(&pdev->dev, "cell-index property not found\n");
ret = -EINVAL;
goto error;
}
mdata->ssi_id = be32_to_cpup(iprop);
/* Get the serial format and clock direction. */
sprop = of_get_property(np, "fsl,mode", NULL);
if (!sprop) {
dev_err(&pdev->dev, "fsl,mode property not found\n");
ret = -EINVAL;
goto error;
}
if (strcasecmp(sprop, "i2s-slave") == 0) {
mdata->dai_format = SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBP_CFP;
mdata->codec_clk_direction = SND_SOC_CLOCK_OUT;
mdata->cpu_clk_direction = SND_SOC_CLOCK_IN;
/* In i2s-slave mode, the codec has its own clock source, so we
* need to get the frequency from the device tree and pass it to
* the codec driver.
*/
iprop = of_get_property(codec_np, "clock-frequency", NULL);
if (!iprop || !*iprop) {
dev_err(&pdev->dev, "codec bus-frequency "
"property is missing or invalid\n");
ret = -EINVAL;
goto error;
}
mdata->clk_frequency = be32_to_cpup(iprop);
} else if (strcasecmp(sprop, "i2s-master") == 0) {
mdata->dai_format = SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBC_CFC;
mdata->codec_clk_direction = SND_SOC_CLOCK_IN;
mdata->cpu_clk_direction = SND_SOC_CLOCK_OUT;
} else if (strcasecmp(sprop, "lj-slave") == 0) {
mdata->dai_format = SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_CBP_CFP;
mdata->codec_clk_direction = SND_SOC_CLOCK_OUT;
mdata->cpu_clk_direction = SND_SOC_CLOCK_IN;
} else if (strcasecmp(sprop, "lj-master") == 0) {
mdata->dai_format = SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_CBC_CFC;
mdata->codec_clk_direction = SND_SOC_CLOCK_IN;
mdata->cpu_clk_direction = SND_SOC_CLOCK_OUT;
} else if (strcasecmp(sprop, "rj-slave") == 0) {
mdata->dai_format = SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_CBP_CFP;
mdata->codec_clk_direction = SND_SOC_CLOCK_OUT;
mdata->cpu_clk_direction = SND_SOC_CLOCK_IN;
} else if (strcasecmp(sprop, "rj-master") == 0) {
mdata->dai_format = SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_CBC_CFC;
mdata->codec_clk_direction = SND_SOC_CLOCK_IN;
mdata->cpu_clk_direction = SND_SOC_CLOCK_OUT;
} else if (strcasecmp(sprop, "ac97-slave") == 0) {
mdata->dai_format = SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_AC97 | SND_SOC_DAIFMT_CBP_CFP;
mdata->codec_clk_direction = SND_SOC_CLOCK_OUT;
mdata->cpu_clk_direction = SND_SOC_CLOCK_IN;
} else if (strcasecmp(sprop, "ac97-master") == 0) {
mdata->dai_format = SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_AC97 | SND_SOC_DAIFMT_CBC_CFC;
mdata->codec_clk_direction = SND_SOC_CLOCK_IN;
mdata->cpu_clk_direction = SND_SOC_CLOCK_OUT;
} else {
dev_err(&pdev->dev,
"unrecognized fsl,mode property '%s'\n", sprop);
ret = -EINVAL;
goto error;
}
if (!mdata->clk_frequency) {
dev_err(&pdev->dev, "unknown clock frequency\n");
ret = -EINVAL;
goto error;
}
/* Find the playback DMA channel to use. */
mdata->dai[0].platforms->name = mdata->platform_name[0];
ret = fsl_asoc_get_dma_channel(np, "fsl,playback-dma", &mdata->dai[0],
&mdata->dma_channel_id[0],
&mdata->dma_id[0]);
if (ret) {
dev_err(&pdev->dev, "missing/invalid playback DMA phandle\n");
goto error;
}
/* Find the capture DMA channel to use. */
mdata->dai[1].platforms->name = mdata->platform_name[1];
ret = fsl_asoc_get_dma_channel(np, "fsl,capture-dma", &mdata->dai[1],
&mdata->dma_channel_id[1],
&mdata->dma_id[1]);
if (ret) {
dev_err(&pdev->dev, "missing/invalid capture DMA phandle\n");
goto error;
}
/* Initialize our DAI data structure. */
mdata->dai[0].stream_name = "playback";
mdata->dai[1].stream_name = "capture";
mdata->dai[0].name = mdata->dai[0].stream_name;
mdata->dai[1].name = mdata->dai[1].stream_name;
mdata->card.probe = p1022_ds_machine_probe;
mdata->card.remove = p1022_ds_machine_remove;
mdata->card.name = pdev->name; /* The platform driver name */
mdata->card.owner = THIS_MODULE;
mdata->card.dev = &pdev->dev;
mdata->card.num_links = 2;
mdata->card.dai_link = mdata->dai;
/* Register with ASoC */
ret = snd_soc_register_card(&mdata->card);
if (ret) {
dev_err(&pdev->dev, "could not register card\n");
goto error;
}
of_node_put(codec_np);
return 0;
error:
kfree(mdata);
error_put:
of_node_put(codec_np);
return ret;
}
/**
* p1022_ds_remove: remove the platform device
*
* This function is called when the platform device is removed.
*/
static void p1022_ds_remove(struct platform_device *pdev)
{
struct snd_soc_card *card = platform_get_drvdata(pdev);
struct machine_data *mdata =
container_of(card, struct machine_data, card);
snd_soc_unregister_card(card);
kfree(mdata);
}
static struct platform_driver p1022_ds_driver = {
.probe = p1022_ds_probe,
.remove_new = p1022_ds_remove,
.driver = {
/*
* The name must match 'compatible' property in the device tree,
* in lowercase letters.
*/
.name = "snd-soc-p1022ds",
},
};
/**
* p1022_ds_init: machine driver initialization.
*
* This function is called when this module is loaded.
*/
static int __init p1022_ds_init(void)
{
struct device_node *guts_np;
struct resource res;
/* Get the physical address of the global utilities registers */
guts_np = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts");
if (of_address_to_resource(guts_np, 0, &res)) {
pr_err("snd-soc-p1022ds: missing/invalid global utils node\n");
of_node_put(guts_np);
return -EINVAL;
}
guts_phys = res.start;
of_node_put(guts_np);
return platform_driver_register(&p1022_ds_driver);
}
/**
* p1022_ds_exit: machine driver exit
*
* This function is called when this driver is unloaded.
*/
static void __exit p1022_ds_exit(void)
{
platform_driver_unregister(&p1022_ds_driver);
}
module_init(p1022_ds_init);
module_exit(p1022_ds_exit);
MODULE_AUTHOR("Timur Tabi <[email protected]>");
MODULE_DESCRIPTION("Freescale P1022 DS ALSA SoC machine driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/fsl/p1022_ds.c |
// SPDX-License-Identifier: GPL-2.0+
// Copyright 2017-2020 NXP
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/of_reserved_mem.h>
#include <linux/i2c.h>
#include <linux/of_gpio.h>
#include <linux/slab.h>
#include <linux/gpio.h>
#include <linux/clk.h>
#include <sound/soc.h>
#include <sound/jack.h>
#include <sound/control.h>
#include <sound/pcm_params.h>
#include <sound/soc-dapm.h>
#include "imx-pcm-rpmsg.h"
struct imx_rpmsg {
struct snd_soc_dai_link dai;
struct snd_soc_card card;
unsigned long sysclk;
};
static const struct snd_soc_dapm_widget imx_rpmsg_dapm_widgets[] = {
SND_SOC_DAPM_HP("Headphone Jack", NULL),
SND_SOC_DAPM_SPK("Ext Spk", NULL),
SND_SOC_DAPM_MIC("Mic Jack", NULL),
SND_SOC_DAPM_MIC("Main MIC", NULL),
};
static int imx_rpmsg_late_probe(struct snd_soc_card *card)
{
struct imx_rpmsg *data = snd_soc_card_get_drvdata(card);
struct snd_soc_pcm_runtime *rtd = list_first_entry(&card->rtd_list,
struct snd_soc_pcm_runtime, list);
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
struct device *dev = card->dev;
int ret;
if (!data->sysclk)
return 0;
ret = snd_soc_dai_set_sysclk(codec_dai, 0, data->sysclk, SND_SOC_CLOCK_IN);
if (ret && ret != -ENOTSUPP) {
dev_err(dev, "failed to set sysclk in %s\n", __func__);
return ret;
}
return 0;
}
static int imx_rpmsg_probe(struct platform_device *pdev)
{
struct snd_soc_dai_link_component *dlc;
struct device *dev = pdev->dev.parent;
/* rpmsg_pdev is the platform device for the rpmsg node that probed us */
struct platform_device *rpmsg_pdev = to_platform_device(dev);
struct device_node *np = rpmsg_pdev->dev.of_node;
struct of_phandle_args args;
const char *platform_name;
struct imx_rpmsg *data;
int ret = 0;
dlc = devm_kzalloc(&pdev->dev, 3 * sizeof(*dlc), GFP_KERNEL);
if (!dlc)
return -ENOMEM;
data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
if (!data) {
ret = -ENOMEM;
goto fail;
}
ret = of_reserved_mem_device_init_by_idx(&pdev->dev, np, 0);
if (ret)
dev_warn(&pdev->dev, "no reserved DMA memory\n");
data->dai.cpus = &dlc[0];
data->dai.num_cpus = 1;
data->dai.platforms = &dlc[1];
data->dai.num_platforms = 1;
data->dai.codecs = &dlc[2];
data->dai.num_codecs = 1;
data->dai.name = "rpmsg hifi";
data->dai.stream_name = "rpmsg hifi";
data->dai.dai_fmt = SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBC_CFC;
/*
* i.MX rpmsg sound cards work on codec slave mode. MCLK will be
* disabled by CPU DAI driver in hw_free(). Some codec requires MCLK
* present at power up/down sequence. So need to set ignore_pmdown_time
* to power down codec immediately before MCLK is turned off.
*/
data->dai.ignore_pmdown_time = 1;
/* Optional codec node */
ret = of_parse_phandle_with_fixed_args(np, "audio-codec", 0, 0, &args);
if (ret) {
*data->dai.codecs = asoc_dummy_dlc;
} else {
struct clk *clk;
ret = snd_soc_get_dlc(&args, data->dai.codecs);
if (ret) {
dev_err(&pdev->dev, "Unable to get codec_dai_name\n");
goto fail;
}
clk = devm_get_clk_from_child(&pdev->dev, args.np, NULL);
if (!IS_ERR(clk))
data->sysclk = clk_get_rate(clk);
}
data->dai.cpus->dai_name = dev_name(&rpmsg_pdev->dev);
if (!of_property_read_string(np, "fsl,rpmsg-channel-name", &platform_name))
data->dai.platforms->name = platform_name;
else
data->dai.platforms->name = "rpmsg-audio-channel";
data->dai.playback_only = true;
data->dai.capture_only = true;
data->card.num_links = 1;
data->card.dai_link = &data->dai;
if (of_property_read_bool(np, "fsl,rpmsg-out"))
data->dai.capture_only = false;
if (of_property_read_bool(np, "fsl,rpmsg-in"))
data->dai.playback_only = false;
if (data->dai.playback_only && data->dai.capture_only) {
dev_err(&pdev->dev, "no enabled rpmsg DAI link\n");
ret = -EINVAL;
goto fail;
}
data->card.dev = &pdev->dev;
data->card.owner = THIS_MODULE;
data->card.dapm_widgets = imx_rpmsg_dapm_widgets;
data->card.num_dapm_widgets = ARRAY_SIZE(imx_rpmsg_dapm_widgets);
data->card.late_probe = imx_rpmsg_late_probe;
/*
* Inoder to use common api to get card name and audio routing.
* Use parent of_node for this device, revert it after finishing using
*/
data->card.dev->of_node = np;
ret = snd_soc_of_parse_card_name(&data->card, "model");
if (ret)
goto fail;
if (of_property_read_bool(np, "audio-routing")) {
ret = snd_soc_of_parse_audio_routing(&data->card, "audio-routing");
if (ret) {
dev_err(&pdev->dev, "failed to parse audio-routing: %d\n", ret);
goto fail;
}
}
platform_set_drvdata(pdev, &data->card);
snd_soc_card_set_drvdata(&data->card, data);
ret = devm_snd_soc_register_card(&pdev->dev, &data->card);
if (ret) {
dev_err_probe(&pdev->dev, ret, "snd_soc_register_card failed\n");
goto fail;
}
fail:
pdev->dev.of_node = NULL;
return ret;
}
static struct platform_driver imx_rpmsg_driver = {
.driver = {
.name = "imx-audio-rpmsg",
.pm = &snd_soc_pm_ops,
},
.probe = imx_rpmsg_probe,
};
module_platform_driver(imx_rpmsg_driver);
MODULE_DESCRIPTION("Freescale SoC Audio RPMSG Machine Driver");
MODULE_AUTHOR("Shengjiu Wang <[email protected]>");
MODULE_ALIAS("platform:imx-audio-rpmsg");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/fsl/imx-rpmsg.c |
// SPDX-License-Identifier: GPL-2.0+
// Copyright 2018-2021 NXP
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/dmaengine.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/of_address.h>
#include <linux/pm_runtime.h>
#include <linux/rpmsg.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/dmaengine_pcm.h>
#include <sound/pcm_params.h>
#include "fsl_rpmsg.h"
#include "imx-pcm.h"
#define FSL_RPMSG_RATES (SNDRV_PCM_RATE_8000 | \
SNDRV_PCM_RATE_16000 | \
SNDRV_PCM_RATE_48000)
#define FSL_RPMSG_FORMATS SNDRV_PCM_FMTBIT_S16_LE
/* 192kHz/32bit/2ch/60s size is 0x574e00 */
#define LPA_LARGE_BUFFER_SIZE (0x6000000)
static const unsigned int fsl_rpmsg_rates[] = {
8000, 11025, 16000, 22050, 44100,
32000, 48000, 96000, 88200, 176400, 192000,
352800, 384000, 705600, 768000, 1411200, 2822400,
};
static const struct snd_pcm_hw_constraint_list fsl_rpmsg_rate_constraints = {
.count = ARRAY_SIZE(fsl_rpmsg_rates),
.list = fsl_rpmsg_rates,
};
static int fsl_rpmsg_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct fsl_rpmsg *rpmsg = snd_soc_dai_get_drvdata(dai);
struct clk *p = rpmsg->mclk, *pll = NULL, *npll = NULL;
u64 rate = params_rate(params);
int ret = 0;
/* Get current pll parent */
while (p && rpmsg->pll8k && rpmsg->pll11k) {
struct clk *pp = clk_get_parent(p);
if (clk_is_match(pp, rpmsg->pll8k) ||
clk_is_match(pp, rpmsg->pll11k)) {
pll = pp;
break;
}
p = pp;
}
/* Switch to another pll parent if needed. */
if (pll) {
npll = (do_div(rate, 8000) ? rpmsg->pll11k : rpmsg->pll8k);
if (!clk_is_match(pll, npll)) {
ret = clk_set_parent(p, npll);
if (ret < 0)
dev_warn(dai->dev, "failed to set parent %s: %d\n",
__clk_get_name(npll), ret);
}
}
if (!(rpmsg->mclk_streams & BIT(substream->stream))) {
ret = clk_prepare_enable(rpmsg->mclk);
if (ret) {
dev_err(dai->dev, "failed to enable mclk: %d\n", ret);
return ret;
}
rpmsg->mclk_streams |= BIT(substream->stream);
}
return ret;
}
static int fsl_rpmsg_hw_free(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct fsl_rpmsg *rpmsg = snd_soc_dai_get_drvdata(dai);
if (rpmsg->mclk_streams & BIT(substream->stream)) {
clk_disable_unprepare(rpmsg->mclk);
rpmsg->mclk_streams &= ~BIT(substream->stream);
}
return 0;
}
static int fsl_rpmsg_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *cpu_dai)
{
int ret;
ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
&fsl_rpmsg_rate_constraints);
return ret;
}
static const struct snd_soc_dai_ops fsl_rpmsg_dai_ops = {
.startup = fsl_rpmsg_startup,
.hw_params = fsl_rpmsg_hw_params,
.hw_free = fsl_rpmsg_hw_free,
};
static struct snd_soc_dai_driver fsl_rpmsg_dai = {
.playback = {
.stream_name = "CPU-Playback",
.channels_min = 2,
.channels_max = 32,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = FSL_RPMSG_FORMATS,
},
.capture = {
.stream_name = "CPU-Capture",
.channels_min = 2,
.channels_max = 32,
.rates = SNDRV_PCM_RATE_KNOT,
.formats = FSL_RPMSG_FORMATS,
},
.symmetric_rate = 1,
.symmetric_channels = 1,
.symmetric_sample_bits = 1,
.ops = &fsl_rpmsg_dai_ops,
};
static const struct snd_soc_component_driver fsl_component = {
.name = "fsl-rpmsg",
.legacy_dai_naming = 1,
};
static const struct fsl_rpmsg_soc_data imx7ulp_data = {
.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |
SNDRV_PCM_RATE_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
};
static const struct fsl_rpmsg_soc_data imx8mm_data = {
.rates = SNDRV_PCM_RATE_KNOT,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_DSD_U8 |
SNDRV_PCM_FMTBIT_DSD_U16_LE | SNDRV_PCM_FMTBIT_DSD_U32_LE,
};
static const struct fsl_rpmsg_soc_data imx8mn_data = {
.rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
SNDRV_PCM_FMTBIT_S32_LE,
};
static const struct fsl_rpmsg_soc_data imx8mp_data = {
.rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
SNDRV_PCM_FMTBIT_S32_LE,
};
static const struct fsl_rpmsg_soc_data imx93_data = {
.rates = SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_32000 |
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
SNDRV_PCM_FMTBIT_S32_LE,
};
static const struct of_device_id fsl_rpmsg_ids[] = {
{ .compatible = "fsl,imx7ulp-rpmsg-audio", .data = &imx7ulp_data},
{ .compatible = "fsl,imx8mm-rpmsg-audio", .data = &imx8mm_data},
{ .compatible = "fsl,imx8mn-rpmsg-audio", .data = &imx8mn_data},
{ .compatible = "fsl,imx8mp-rpmsg-audio", .data = &imx8mp_data},
{ .compatible = "fsl,imx8ulp-rpmsg-audio", .data = &imx7ulp_data},
{ .compatible = "fsl,imx93-rpmsg-audio", .data = &imx93_data},
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, fsl_rpmsg_ids);
static int fsl_rpmsg_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct fsl_rpmsg *rpmsg;
int ret;
rpmsg = devm_kzalloc(&pdev->dev, sizeof(struct fsl_rpmsg), GFP_KERNEL);
if (!rpmsg)
return -ENOMEM;
rpmsg->soc_data = of_device_get_match_data(&pdev->dev);
fsl_rpmsg_dai.playback.rates = rpmsg->soc_data->rates;
fsl_rpmsg_dai.capture.rates = rpmsg->soc_data->rates;
fsl_rpmsg_dai.playback.formats = rpmsg->soc_data->formats;
fsl_rpmsg_dai.capture.formats = rpmsg->soc_data->formats;
if (of_property_read_bool(np, "fsl,enable-lpa")) {
rpmsg->enable_lpa = 1;
rpmsg->buffer_size = LPA_LARGE_BUFFER_SIZE;
} else {
rpmsg->buffer_size = IMX_DEFAULT_DMABUF_SIZE;
}
/* Get the optional clocks */
rpmsg->ipg = devm_clk_get_optional(&pdev->dev, "ipg");
if (IS_ERR(rpmsg->ipg))
return PTR_ERR(rpmsg->ipg);
rpmsg->mclk = devm_clk_get_optional(&pdev->dev, "mclk");
if (IS_ERR(rpmsg->mclk))
return PTR_ERR(rpmsg->mclk);
rpmsg->dma = devm_clk_get_optional(&pdev->dev, "dma");
if (IS_ERR(rpmsg->dma))
return PTR_ERR(rpmsg->dma);
rpmsg->pll8k = devm_clk_get_optional(&pdev->dev, "pll8k");
if (IS_ERR(rpmsg->pll8k))
return PTR_ERR(rpmsg->pll8k);
rpmsg->pll11k = devm_clk_get_optional(&pdev->dev, "pll11k");
if (IS_ERR(rpmsg->pll11k))
return PTR_ERR(rpmsg->pll11k);
platform_set_drvdata(pdev, rpmsg);
pm_runtime_enable(&pdev->dev);
ret = devm_snd_soc_register_component(&pdev->dev, &fsl_component,
&fsl_rpmsg_dai, 1);
if (ret)
return ret;
rpmsg->card_pdev = platform_device_register_data(&pdev->dev,
"imx-audio-rpmsg",
PLATFORM_DEVID_AUTO,
NULL,
0);
if (IS_ERR(rpmsg->card_pdev)) {
dev_err(&pdev->dev, "failed to register rpmsg card\n");
ret = PTR_ERR(rpmsg->card_pdev);
return ret;
}
return 0;
}
static void fsl_rpmsg_remove(struct platform_device *pdev)
{
struct fsl_rpmsg *rpmsg = platform_get_drvdata(pdev);
if (rpmsg->card_pdev)
platform_device_unregister(rpmsg->card_pdev);
}
#ifdef CONFIG_PM
static int fsl_rpmsg_runtime_resume(struct device *dev)
{
struct fsl_rpmsg *rpmsg = dev_get_drvdata(dev);
int ret;
ret = clk_prepare_enable(rpmsg->ipg);
if (ret) {
dev_err(dev, "failed to enable ipg clock: %d\n", ret);
goto ipg_err;
}
ret = clk_prepare_enable(rpmsg->dma);
if (ret) {
dev_err(dev, "Failed to enable dma clock %d\n", ret);
goto dma_err;
}
return 0;
dma_err:
clk_disable_unprepare(rpmsg->ipg);
ipg_err:
return ret;
}
static int fsl_rpmsg_runtime_suspend(struct device *dev)
{
struct fsl_rpmsg *rpmsg = dev_get_drvdata(dev);
clk_disable_unprepare(rpmsg->dma);
clk_disable_unprepare(rpmsg->ipg);
return 0;
}
#endif
static const struct dev_pm_ops fsl_rpmsg_pm_ops = {
SET_RUNTIME_PM_OPS(fsl_rpmsg_runtime_suspend,
fsl_rpmsg_runtime_resume,
NULL)
};
static struct platform_driver fsl_rpmsg_driver = {
.probe = fsl_rpmsg_probe,
.remove_new = fsl_rpmsg_remove,
.driver = {
.name = "fsl_rpmsg",
.pm = &fsl_rpmsg_pm_ops,
.of_match_table = fsl_rpmsg_ids,
},
};
module_platform_driver(fsl_rpmsg_driver);
MODULE_DESCRIPTION("Freescale SoC Audio PRMSG CPU Interface");
MODULE_AUTHOR("Shengjiu Wang <[email protected]>");
MODULE_ALIAS("platform:fsl_rpmsg");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/fsl/fsl_rpmsg.c |
// SPDX-License-Identifier: GPL-2.0
//
// Freescale P1022RDK ALSA SoC Machine driver
//
// Author: Timur Tabi <[email protected]>
//
// Copyright 2012 Freescale Semiconductor, Inc.
//
// Note: in order for audio to work correctly, the output controls need
// to be enabled, because they control the clock. So for playback, for
// example:
//
// amixer sset 'Left Output Mixer PCM' on
// amixer sset 'Right Output Mixer PCM' on
#include <linux/module.h>
#include <linux/fsl/guts.h>
#include <linux/interrupt.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/slab.h>
#include <sound/soc.h>
#include "fsl_dma.h"
#include "fsl_ssi.h"
#include "fsl_utils.h"
/* P1022-specific PMUXCR and DMUXCR bit definitions */
#define CCSR_GUTS_PMUXCR_UART0_I2C1_MASK 0x0001c000
#define CCSR_GUTS_PMUXCR_UART0_I2C1_UART0_SSI 0x00010000
#define CCSR_GUTS_PMUXCR_UART0_I2C1_SSI 0x00018000
#define CCSR_GUTS_PMUXCR_SSI_DMA_TDM_MASK 0x00000c00
#define CCSR_GUTS_PMUXCR_SSI_DMA_TDM_SSI 0x00000000
#define CCSR_GUTS_DMUXCR_PAD 1 /* DMA controller/channel set to pad */
#define CCSR_GUTS_DMUXCR_SSI 2 /* DMA controller/channel set to SSI */
/*
* Set the DMACR register in the GUTS
*
* The DMACR register determines the source of initiated transfers for each
* channel on each DMA controller. Rather than have a bunch of repetitive
* macros for the bit patterns, we just have a function that calculates
* them.
*
* guts: Pointer to GUTS structure
* co: The DMA controller (0 or 1)
* ch: The channel on the DMA controller (0, 1, 2, or 3)
* device: The device to set as the target (CCSR_GUTS_DMUXCR_xxx)
*/
static inline void guts_set_dmuxcr(struct ccsr_guts __iomem *guts,
unsigned int co, unsigned int ch, unsigned int device)
{
unsigned int shift = 16 + (8 * (1 - co) + 2 * (3 - ch));
clrsetbits_be32(&guts->dmuxcr, 3 << shift, device << shift);
}
/* There's only one global utilities register */
static phys_addr_t guts_phys;
/**
* machine_data: machine-specific ASoC device data
*
* This structure contains data for a single sound platform device on an
* P1022 RDK. Some of the data is taken from the device tree.
*/
struct machine_data {
struct snd_soc_dai_link dai[2];
struct snd_soc_card card;
unsigned int dai_format;
unsigned int codec_clk_direction;
unsigned int cpu_clk_direction;
unsigned int clk_frequency;
unsigned int dma_id[2]; /* 0 = DMA1, 1 = DMA2, etc */
unsigned int dma_channel_id[2]; /* 0 = ch 0, 1 = ch 1, etc*/
char platform_name[2][DAI_NAME_SIZE]; /* One for each DMA channel */
};
/**
* p1022_rdk_machine_probe: initialize the board
*
* This function is used to initialize the board-specific hardware.
*
* Here we program the DMACR and PMUXCR registers.
*/
static int p1022_rdk_machine_probe(struct snd_soc_card *card)
{
struct machine_data *mdata =
container_of(card, struct machine_data, card);
struct ccsr_guts __iomem *guts;
guts = ioremap(guts_phys, sizeof(struct ccsr_guts));
if (!guts) {
dev_err(card->dev, "could not map global utilities\n");
return -ENOMEM;
}
/* Enable SSI Tx signal */
clrsetbits_be32(&guts->pmuxcr, CCSR_GUTS_PMUXCR_UART0_I2C1_MASK,
CCSR_GUTS_PMUXCR_UART0_I2C1_UART0_SSI);
/* Enable SSI Rx signal */
clrsetbits_be32(&guts->pmuxcr, CCSR_GUTS_PMUXCR_SSI_DMA_TDM_MASK,
CCSR_GUTS_PMUXCR_SSI_DMA_TDM_SSI);
/* Enable DMA Channel for SSI */
guts_set_dmuxcr(guts, mdata->dma_id[0], mdata->dma_channel_id[0],
CCSR_GUTS_DMUXCR_SSI);
guts_set_dmuxcr(guts, mdata->dma_id[1], mdata->dma_channel_id[1],
CCSR_GUTS_DMUXCR_SSI);
iounmap(guts);
return 0;
}
/**
* p1022_rdk_startup: program the board with various hardware parameters
*
* This function takes board-specific information, like clock frequencies
* and serial data formats, and passes that information to the codec and
* transport drivers.
*/
static int p1022_rdk_startup(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct machine_data *mdata =
container_of(rtd->card, struct machine_data, card);
struct device *dev = rtd->card->dev;
int ret = 0;
/* Tell the codec driver what the serial protocol is. */
ret = snd_soc_dai_set_fmt(asoc_rtd_to_codec(rtd, 0), mdata->dai_format);
if (ret < 0) {
dev_err(dev, "could not set codec driver audio format (ret=%i)\n",
ret);
return ret;
}
ret = snd_soc_dai_set_pll(asoc_rtd_to_codec(rtd, 0), 0, 0, mdata->clk_frequency,
mdata->clk_frequency);
if (ret < 0) {
dev_err(dev, "could not set codec PLL frequency (ret=%i)\n",
ret);
return ret;
}
return 0;
}
/**
* p1022_rdk_machine_remove: Remove the sound device
*
* This function is called to remove the sound device for one SSI. We
* de-program the DMACR and PMUXCR register.
*/
static int p1022_rdk_machine_remove(struct snd_soc_card *card)
{
struct machine_data *mdata =
container_of(card, struct machine_data, card);
struct ccsr_guts __iomem *guts;
guts = ioremap(guts_phys, sizeof(struct ccsr_guts));
if (!guts) {
dev_err(card->dev, "could not map global utilities\n");
return -ENOMEM;
}
/* Restore the signal routing */
clrbits32(&guts->pmuxcr, CCSR_GUTS_PMUXCR_UART0_I2C1_MASK);
clrbits32(&guts->pmuxcr, CCSR_GUTS_PMUXCR_SSI_DMA_TDM_MASK);
guts_set_dmuxcr(guts, mdata->dma_id[0], mdata->dma_channel_id[0], 0);
guts_set_dmuxcr(guts, mdata->dma_id[1], mdata->dma_channel_id[1], 0);
iounmap(guts);
return 0;
}
/**
* p1022_rdk_ops: ASoC machine driver operations
*/
static const struct snd_soc_ops p1022_rdk_ops = {
.startup = p1022_rdk_startup,
};
/**
* p1022_rdk_probe: platform probe function for the machine driver
*
* Although this is a machine driver, the SSI node is the "master" node with
* respect to audio hardware connections. Therefore, we create a new ASoC
* device for each new SSI node that has a codec attached.
*/
static int p1022_rdk_probe(struct platform_device *pdev)
{
struct device *dev = pdev->dev.parent;
/* ssi_pdev is the platform device for the SSI node that probed us */
struct platform_device *ssi_pdev = to_platform_device(dev);
struct device_node *np = ssi_pdev->dev.of_node;
struct device_node *codec_np = NULL;
struct machine_data *mdata;
struct snd_soc_dai_link_component *comp;
const u32 *iprop;
int ret;
/* Find the codec node for this SSI. */
codec_np = of_parse_phandle(np, "codec-handle", 0);
if (!codec_np) {
dev_err(dev, "could not find codec node\n");
return -EINVAL;
}
mdata = kzalloc(sizeof(struct machine_data), GFP_KERNEL);
if (!mdata) {
ret = -ENOMEM;
goto error_put;
}
comp = devm_kzalloc(&pdev->dev, 6 * sizeof(*comp), GFP_KERNEL);
if (!comp) {
ret = -ENOMEM;
goto error_put;
}
mdata->dai[0].cpus = &comp[0];
mdata->dai[0].codecs = &comp[1];
mdata->dai[0].platforms = &comp[2];
mdata->dai[0].num_cpus = 1;
mdata->dai[0].num_codecs = 1;
mdata->dai[0].num_platforms = 1;
mdata->dai[1].cpus = &comp[3];
mdata->dai[1].codecs = &comp[4];
mdata->dai[1].platforms = &comp[5];
mdata->dai[1].num_cpus = 1;
mdata->dai[1].num_codecs = 1;
mdata->dai[1].num_platforms = 1;
mdata->dai[0].cpus->dai_name = dev_name(&ssi_pdev->dev);
mdata->dai[0].ops = &p1022_rdk_ops;
/* ASoC core can match codec with device node */
mdata->dai[0].codecs->of_node = codec_np;
/*
* We register two DAIs per SSI, one for playback and the other for
* capture. We support codecs that have separate DAIs for both playback
* and capture.
*/
memcpy(&mdata->dai[1], &mdata->dai[0], sizeof(struct snd_soc_dai_link));
/* The DAI names from the codec (snd_soc_dai_driver.name) */
mdata->dai[0].codecs->dai_name = "wm8960-hifi";
mdata->dai[1].codecs->dai_name = mdata->dai[0].codecs->dai_name;
/*
* Configure the SSI for I2S slave mode. Older device trees have
* an fsl,mode property, but we ignore that since there's really
* only one way to configure the SSI.
*/
mdata->dai_format = SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBP_CFP;
mdata->codec_clk_direction = SND_SOC_CLOCK_OUT;
mdata->cpu_clk_direction = SND_SOC_CLOCK_IN;
/*
* In i2s-slave mode, the codec has its own clock source, so we
* need to get the frequency from the device tree and pass it to
* the codec driver.
*/
iprop = of_get_property(codec_np, "clock-frequency", NULL);
if (!iprop || !*iprop) {
dev_err(&pdev->dev, "codec bus-frequency property is missing or invalid\n");
ret = -EINVAL;
goto error;
}
mdata->clk_frequency = be32_to_cpup(iprop);
if (!mdata->clk_frequency) {
dev_err(&pdev->dev, "unknown clock frequency\n");
ret = -EINVAL;
goto error;
}
/* Find the playback DMA channel to use. */
mdata->dai[0].platforms->name = mdata->platform_name[0];
ret = fsl_asoc_get_dma_channel(np, "fsl,playback-dma", &mdata->dai[0],
&mdata->dma_channel_id[0],
&mdata->dma_id[0]);
if (ret) {
dev_err(&pdev->dev, "missing/invalid playback DMA phandle (ret=%i)\n",
ret);
goto error;
}
/* Find the capture DMA channel to use. */
mdata->dai[1].platforms->name = mdata->platform_name[1];
ret = fsl_asoc_get_dma_channel(np, "fsl,capture-dma", &mdata->dai[1],
&mdata->dma_channel_id[1],
&mdata->dma_id[1]);
if (ret) {
dev_err(&pdev->dev, "missing/invalid capture DMA phandle (ret=%i)\n",
ret);
goto error;
}
/* Initialize our DAI data structure. */
mdata->dai[0].stream_name = "playback";
mdata->dai[1].stream_name = "capture";
mdata->dai[0].name = mdata->dai[0].stream_name;
mdata->dai[1].name = mdata->dai[1].stream_name;
mdata->card.probe = p1022_rdk_machine_probe;
mdata->card.remove = p1022_rdk_machine_remove;
mdata->card.name = pdev->name; /* The platform driver name */
mdata->card.owner = THIS_MODULE;
mdata->card.dev = &pdev->dev;
mdata->card.num_links = 2;
mdata->card.dai_link = mdata->dai;
/* Register with ASoC */
ret = snd_soc_register_card(&mdata->card);
if (ret) {
dev_err(&pdev->dev, "could not register card (ret=%i)\n", ret);
goto error;
}
return 0;
error:
kfree(mdata);
error_put:
of_node_put(codec_np);
return ret;
}
/**
* p1022_rdk_remove: remove the platform device
*
* This function is called when the platform device is removed.
*/
static void p1022_rdk_remove(struct platform_device *pdev)
{
struct snd_soc_card *card = platform_get_drvdata(pdev);
struct machine_data *mdata =
container_of(card, struct machine_data, card);
snd_soc_unregister_card(card);
kfree(mdata);
}
static struct platform_driver p1022_rdk_driver = {
.probe = p1022_rdk_probe,
.remove_new = p1022_rdk_remove,
.driver = {
/*
* The name must match 'compatible' property in the device tree,
* in lowercase letters.
*/
.name = "snd-soc-p1022rdk",
},
};
/**
* p1022_rdk_init: machine driver initialization.
*
* This function is called when this module is loaded.
*/
static int __init p1022_rdk_init(void)
{
struct device_node *guts_np;
struct resource res;
/* Get the physical address of the global utilities registers */
guts_np = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts");
if (of_address_to_resource(guts_np, 0, &res)) {
pr_err("snd-soc-p1022rdk: missing/invalid global utils node\n");
of_node_put(guts_np);
return -EINVAL;
}
guts_phys = res.start;
of_node_put(guts_np);
return platform_driver_register(&p1022_rdk_driver);
}
/**
* p1022_rdk_exit: machine driver exit
*
* This function is called when this driver is unloaded.
*/
static void __exit p1022_rdk_exit(void)
{
platform_driver_unregister(&p1022_rdk_driver);
}
late_initcall(p1022_rdk_init);
module_exit(p1022_rdk_exit);
MODULE_AUTHOR("Timur Tabi <[email protected]>");
MODULE_DESCRIPTION("Freescale / iVeia P1022 RDK ALSA SoC machine driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/fsl/p1022_rdk.c |
// SPDX-License-Identifier: GPL-2.0+
// Copyright 2017-2021 NXP
#include <linux/module.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/gpio/consumer.h>
#include <linux/of_device.h>
#include <linux/i2c.h>
#include <linux/of_gpio.h>
#include <linux/clk.h>
#include <sound/soc.h>
#include <sound/pcm_params.h>
#include <sound/pcm.h>
#include <sound/soc-dapm.h>
#include <sound/simple_card_utils.h>
#include "fsl_sai.h"
#define IMX_CARD_MCLK_22P5792MHZ 22579200
#define IMX_CARD_MCLK_24P576MHZ 24576000
enum codec_type {
CODEC_DUMMY = 0,
CODEC_AK5558 = 1,
CODEC_AK4458,
CODEC_AK4497,
CODEC_AK5552,
};
/*
* Mapping LRCK fs and frame width, table 3 & 4 in datasheet
* @rmin: min rate
* @rmax: max rate
* @wmin: min frame ratio
* @wmax: max frame ratio
*/
struct imx_akcodec_fs_mul {
unsigned int rmin;
unsigned int rmax;
unsigned int wmin;
unsigned int wmax;
};
/*
* Mapping TDM mode and frame width
*/
struct imx_akcodec_tdm_fs_mul {
unsigned int min;
unsigned int max;
unsigned int mul;
};
/*
* struct imx_card_plat_data - specific info for codecs
*
* @fs_mul: ratio of mclk/fs for normal mode
* @tdm_fs_mul: ratio of mclk/fs for tdm mode
* @support_rates: supported sample rate
* @support_tdm_rates: supported sample rate for tdm mode
* @support_channels: supported channels
* @support_tdm_channels: supported channels for tdm mode
* @num_fs_mul: ARRAY_SIZE of fs_mul
* @num_tdm_fs_mul: ARRAY_SIZE of tdm_fs_mul
* @num_rates: ARRAY_SIZE of support_rates
* @num_tdm_rates: ARRAY_SIZE of support_tdm_rates
* @num_channels: ARRAY_SIZE of support_channels
* @num_tdm_channels: ARRAY_SIZE of support_tdm_channels
* @type: codec type
*/
struct imx_card_plat_data {
struct imx_akcodec_fs_mul *fs_mul;
struct imx_akcodec_tdm_fs_mul *tdm_fs_mul;
const u32 *support_rates;
const u32 *support_tdm_rates;
const u32 *support_channels;
const u32 *support_tdm_channels;
unsigned int num_fs_mul;
unsigned int num_tdm_fs_mul;
unsigned int num_rates;
unsigned int num_tdm_rates;
unsigned int num_channels;
unsigned int num_tdm_channels;
unsigned int num_codecs;
enum codec_type type;
};
/*
* struct dai_link_data - specific info for dai link
*
* @slots: slot number
* @slot_width: slot width value
* @cpu_sysclk_id: sysclk id for cpu dai
* @one2one_ratio: true if mclk equal to bclk
*/
struct dai_link_data {
unsigned int slots;
unsigned int slot_width;
unsigned int cpu_sysclk_id;
bool one2one_ratio;
};
/*
* struct imx_card_data - platform device data
*
* @plat_data: pointer of imx_card_plat_data
* @dapm_routes: pointer of dapm_routes
* @link_data: private data for dai link
* @card: card instance
* @num_dapm_routes: number of dapm_routes
* @asrc_rate: asrc rates
* @asrc_format: asrc format
*/
struct imx_card_data {
struct imx_card_plat_data *plat_data;
struct snd_soc_dapm_route *dapm_routes;
struct dai_link_data *link_data;
struct snd_soc_card card;
int num_dapm_routes;
u32 asrc_rate;
snd_pcm_format_t asrc_format;
};
static struct imx_akcodec_fs_mul ak4458_fs_mul[] = {
/* Normal, < 32kHz */
{ .rmin = 8000, .rmax = 24000, .wmin = 256, .wmax = 1024, },
/* Normal, 32kHz */
{ .rmin = 32000, .rmax = 32000, .wmin = 256, .wmax = 1024, },
/* Normal */
{ .rmin = 44100, .rmax = 48000, .wmin = 256, .wmax = 768, },
/* Double */
{ .rmin = 88200, .rmax = 96000, .wmin = 256, .wmax = 512, },
/* Quad */
{ .rmin = 176400, .rmax = 192000, .wmin = 128, .wmax = 256, },
/* Oct */
{ .rmin = 352800, .rmax = 384000, .wmin = 32, .wmax = 128, },
/* Hex */
{ .rmin = 705600, .rmax = 768000, .wmin = 16, .wmax = 64, },
};
static struct imx_akcodec_tdm_fs_mul ak4458_tdm_fs_mul[] = {
/*
* Table 13 - Audio Interface Format
* For TDM mode, MCLK should is set to
* obtained from 2 * slots * slot_width
*/
{ .min = 128, .max = 128, .mul = 256 }, /* TDM128 */
{ .min = 256, .max = 256, .mul = 512 }, /* TDM256 */
{ .min = 512, .max = 512, .mul = 1024 }, /* TDM512 */
};
static struct imx_akcodec_fs_mul ak4497_fs_mul[] = {
/**
* Table 7 - mapping multiplier and speed mode
* Tables 8 & 9 - mapping speed mode and LRCK fs
*/
{ .rmin = 8000, .rmax = 32000, .wmin = 256, .wmax = 1024, }, /* Normal, <= 32kHz */
{ .rmin = 44100, .rmax = 48000, .wmin = 256, .wmax = 512, }, /* Normal */
{ .rmin = 88200, .rmax = 96000, .wmin = 256, .wmax = 256, }, /* Double */
{ .rmin = 176400, .rmax = 192000, .wmin = 128, .wmax = 128, }, /* Quad */
{ .rmin = 352800, .rmax = 384000, .wmin = 128, .wmax = 128, }, /* Oct */
{ .rmin = 705600, .rmax = 768000, .wmin = 64, .wmax = 64, }, /* Hex */
};
/*
* Auto MCLK selection based on LRCK for Normal Mode
* (Table 4 from datasheet)
*/
static struct imx_akcodec_fs_mul ak5558_fs_mul[] = {
{ .rmin = 8000, .rmax = 32000, .wmin = 512, .wmax = 1024, },
{ .rmin = 44100, .rmax = 48000, .wmin = 512, .wmax = 512, },
{ .rmin = 88200, .rmax = 96000, .wmin = 256, .wmax = 256, },
{ .rmin = 176400, .rmax = 192000, .wmin = 128, .wmax = 128, },
{ .rmin = 352800, .rmax = 384000, .wmin = 64, .wmax = 64, },
{ .rmin = 705600, .rmax = 768000, .wmin = 32, .wmax = 32, },
};
/*
* MCLK and BCLK selection based on TDM mode
* because of SAI we also add the restriction: MCLK >= 2 * BCLK
* (Table 9 from datasheet)
*/
static struct imx_akcodec_tdm_fs_mul ak5558_tdm_fs_mul[] = {
{ .min = 128, .max = 128, .mul = 256 },
{ .min = 256, .max = 256, .mul = 512 },
{ .min = 512, .max = 512, .mul = 1024 },
};
static const u32 akcodec_rates[] = {
8000, 11025, 16000, 22050, 32000, 44100, 48000, 88200,
96000, 176400, 192000, 352800, 384000, 705600, 768000,
};
static const u32 akcodec_tdm_rates[] = {
8000, 16000, 32000, 48000, 96000,
};
static const u32 ak4458_channels[] = {
1, 2, 4, 6, 8, 10, 12, 14, 16,
};
static const u32 ak4458_tdm_channels[] = {
1, 2, 3, 4, 5, 6, 7, 8, 16,
};
static const u32 ak5558_channels[] = {
1, 2, 4, 6, 8,
};
static const u32 ak5558_tdm_channels[] = {
1, 2, 3, 4, 5, 6, 7, 8,
};
static bool format_is_dsd(struct snd_pcm_hw_params *params)
{
snd_pcm_format_t format = params_format(params);
switch (format) {
case SNDRV_PCM_FORMAT_DSD_U8:
case SNDRV_PCM_FORMAT_DSD_U16_LE:
case SNDRV_PCM_FORMAT_DSD_U16_BE:
case SNDRV_PCM_FORMAT_DSD_U32_LE:
case SNDRV_PCM_FORMAT_DSD_U32_BE:
return true;
default:
return false;
}
}
static bool format_is_tdm(struct dai_link_data *link_data)
{
if (link_data->slots > 2)
return true;
else
return false;
}
static bool codec_is_akcodec(unsigned int type)
{
switch (type) {
case CODEC_AK4458:
case CODEC_AK4497:
case CODEC_AK5558:
case CODEC_AK5552:
return true;
default:
break;
}
return false;
}
static unsigned long akcodec_get_mclk_rate(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
int slots, int slot_width)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct imx_card_data *data = snd_soc_card_get_drvdata(rtd->card);
const struct imx_card_plat_data *plat_data = data->plat_data;
struct dai_link_data *link_data = &data->link_data[rtd->num];
unsigned int width = slots * slot_width;
unsigned int rate = params_rate(params);
int i;
if (format_is_tdm(link_data)) {
for (i = 0; i < plat_data->num_tdm_fs_mul; i++) {
/* min = max = slots * slots_width */
if (width != plat_data->tdm_fs_mul[i].min)
continue;
return rate * plat_data->tdm_fs_mul[i].mul;
}
} else {
for (i = 0; i < plat_data->num_fs_mul; i++) {
if (rate >= plat_data->fs_mul[i].rmin &&
rate <= plat_data->fs_mul[i].rmax) {
width = max(width, plat_data->fs_mul[i].wmin);
width = min(width, plat_data->fs_mul[i].wmax);
/* Adjust SAI bclk:mclk ratio */
width *= link_data->one2one_ratio ? 1 : 2;
return rate * width;
}
}
}
/* Let DAI manage clk frequency by default */
return 0;
}
static int imx_aif_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct snd_soc_card *card = rtd->card;
struct imx_card_data *data = snd_soc_card_get_drvdata(card);
struct dai_link_data *link_data = &data->link_data[rtd->num];
struct imx_card_plat_data *plat_data = data->plat_data;
struct device *dev = card->dev;
struct snd_soc_dai *codec_dai;
unsigned long mclk_freq;
unsigned int fmt = rtd->dai_link->dai_fmt;
unsigned int slots, slot_width;
int ret, i;
slots = link_data->slots;
slot_width = link_data->slot_width;
if (!format_is_tdm(link_data)) {
if (format_is_dsd(params)) {
slots = 1;
slot_width = params_width(params);
fmt = (rtd->dai_link->dai_fmt & ~SND_SOC_DAIFMT_FORMAT_MASK) |
SND_SOC_DAIFMT_PDM;
} else {
slots = 2;
slot_width = params_physical_width(params);
fmt = (rtd->dai_link->dai_fmt & ~SND_SOC_DAIFMT_FORMAT_MASK) |
SND_SOC_DAIFMT_I2S;
}
}
ret = snd_soc_dai_set_fmt(cpu_dai, snd_soc_daifmt_clock_provider_flipped(fmt));
if (ret && ret != -ENOTSUPP) {
dev_err(dev, "failed to set cpu dai fmt: %d\n", ret);
return ret;
}
ret = snd_soc_dai_set_tdm_slot(cpu_dai,
BIT(slots) - 1,
BIT(slots) - 1,
slots, slot_width);
if (ret && ret != -ENOTSUPP) {
dev_err(dev, "failed to set cpu dai tdm slot: %d\n", ret);
return ret;
}
for_each_rtd_codec_dais(rtd, i, codec_dai) {
ret = snd_soc_dai_set_fmt(codec_dai, fmt);
if (ret && ret != -ENOTSUPP) {
dev_err(dev, "failed to set codec dai[%d] fmt: %d\n", i, ret);
return ret;
}
ret = snd_soc_dai_set_tdm_slot(codec_dai,
BIT(slots) - 1,
BIT(slots) - 1,
slots, slot_width);
if (ret && ret != -ENOTSUPP) {
dev_err(dev, "failed to set codec dai[%d] tdm slot: %d\n", i, ret);
return ret;
}
}
/* Set MCLK freq */
if (codec_is_akcodec(plat_data->type))
mclk_freq = akcodec_get_mclk_rate(substream, params, slots, slot_width);
else
mclk_freq = params_rate(params) * slots * slot_width;
if (format_is_dsd(params)) {
/* Use the maximum freq from DSD512 (512*44100 = 22579200) */
if (!(params_rate(params) % 11025))
mclk_freq = IMX_CARD_MCLK_22P5792MHZ;
else
mclk_freq = IMX_CARD_MCLK_24P576MHZ;
}
ret = snd_soc_dai_set_sysclk(cpu_dai, link_data->cpu_sysclk_id, mclk_freq,
SND_SOC_CLOCK_OUT);
if (ret && ret != -ENOTSUPP) {
dev_err(dev, "failed to set cpui dai mclk1 rate (%lu): %d\n", mclk_freq, ret);
return ret;
}
return 0;
}
static int ak5558_hw_rule_rate(struct snd_pcm_hw_params *p, struct snd_pcm_hw_rule *r)
{
struct dai_link_data *link_data = r->private;
struct snd_interval t = { .min = 8000, .max = 8000, };
unsigned long mclk_freq;
unsigned int fs;
int i;
fs = hw_param_interval(p, SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
fs *= link_data->slots;
/* Identify maximum supported rate */
for (i = 0; i < ARRAY_SIZE(akcodec_rates); i++) {
mclk_freq = fs * akcodec_rates[i];
/* Adjust SAI bclk:mclk ratio */
mclk_freq *= link_data->one2one_ratio ? 1 : 2;
/* Skip rates for which MCLK is beyond supported value */
if (mclk_freq > 36864000)
continue;
if (t.max < akcodec_rates[i])
t.max = akcodec_rates[i];
}
return snd_interval_refine(hw_param_interval(p, r->var), &t);
}
static int imx_aif_startup(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_card *card = rtd->card;
struct imx_card_data *data = snd_soc_card_get_drvdata(card);
struct dai_link_data *link_data = &data->link_data[rtd->num];
static struct snd_pcm_hw_constraint_list constraint_rates;
static struct snd_pcm_hw_constraint_list constraint_channels;
int ret = 0;
if (format_is_tdm(link_data)) {
constraint_channels.list = data->plat_data->support_tdm_channels;
constraint_channels.count = data->plat_data->num_tdm_channels;
constraint_rates.list = data->plat_data->support_tdm_rates;
constraint_rates.count = data->plat_data->num_tdm_rates;
} else {
constraint_channels.list = data->plat_data->support_channels;
constraint_channels.count = data->plat_data->num_channels;
constraint_rates.list = data->plat_data->support_rates;
constraint_rates.count = data->plat_data->num_rates;
}
if (constraint_channels.count) {
ret = snd_pcm_hw_constraint_list(runtime, 0,
SNDRV_PCM_HW_PARAM_CHANNELS,
&constraint_channels);
if (ret)
return ret;
}
if (constraint_rates.count) {
ret = snd_pcm_hw_constraint_list(runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
&constraint_rates);
if (ret)
return ret;
}
if (data->plat_data->type == CODEC_AK5558)
ret = snd_pcm_hw_rule_add(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
ak5558_hw_rule_rate, link_data,
SNDRV_PCM_HW_PARAM_SAMPLE_BITS, -1);
return ret;
}
static const struct snd_soc_ops imx_aif_ops = {
.hw_params = imx_aif_hw_params,
.startup = imx_aif_startup,
};
static const struct snd_soc_ops imx_aif_ops_be = {
.hw_params = imx_aif_hw_params,
};
static int be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
struct snd_pcm_hw_params *params)
{
struct snd_soc_card *card = rtd->card;
struct imx_card_data *data = snd_soc_card_get_drvdata(card);
struct snd_interval *rate;
struct snd_mask *mask;
rate = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
rate->max = data->asrc_rate;
rate->min = data->asrc_rate;
mask = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
snd_mask_none(mask);
snd_mask_set(mask, (__force unsigned int)data->asrc_format);
return 0;
}
static int imx_card_parse_of(struct imx_card_data *data)
{
struct imx_card_plat_data *plat_data = data->plat_data;
struct snd_soc_card *card = &data->card;
struct snd_soc_dai_link_component *dlc;
struct device_node *platform = NULL;
struct device_node *codec = NULL;
struct device_node *cpu = NULL;
struct device_node *np;
struct device *dev = card->dev;
struct snd_soc_dai_link *link;
struct dai_link_data *link_data;
struct of_phandle_args args;
int ret, num_links;
u32 asrc_fmt = 0;
u32 width;
ret = snd_soc_of_parse_card_name(card, "model");
if (ret) {
dev_err(dev, "Error parsing card name: %d\n", ret);
return ret;
}
/* DAPM routes */
if (of_property_read_bool(dev->of_node, "audio-routing")) {
ret = snd_soc_of_parse_audio_routing(card, "audio-routing");
if (ret)
return ret;
}
/* Populate links */
num_links = of_get_child_count(dev->of_node);
/* Allocate the DAI link array */
card->dai_link = devm_kcalloc(dev, num_links, sizeof(*link), GFP_KERNEL);
if (!card->dai_link)
return -ENOMEM;
data->link_data = devm_kcalloc(dev, num_links, sizeof(*link), GFP_KERNEL);
if (!data->link_data)
return -ENOMEM;
card->num_links = num_links;
link = card->dai_link;
link_data = data->link_data;
for_each_child_of_node(dev->of_node, np) {
dlc = devm_kzalloc(dev, 2 * sizeof(*dlc), GFP_KERNEL);
if (!dlc) {
ret = -ENOMEM;
goto err_put_np;
}
link->cpus = &dlc[0];
link->platforms = &dlc[1];
link->num_cpus = 1;
link->num_platforms = 1;
ret = of_property_read_string(np, "link-name", &link->name);
if (ret) {
dev_err(card->dev, "error getting codec dai_link name\n");
goto err_put_np;
}
cpu = of_get_child_by_name(np, "cpu");
if (!cpu) {
dev_err(dev, "%s: Can't find cpu DT node\n", link->name);
ret = -EINVAL;
goto err;
}
ret = snd_soc_of_get_dlc(cpu, &args, link->cpus, 0);
if (ret) {
dev_err_probe(card->dev, ret,
"%s: error getting cpu dai info\n", link->name);
goto err;
}
if (of_node_name_eq(args.np, "sai")) {
/* sai sysclk id */
link_data->cpu_sysclk_id = FSL_SAI_CLK_MAST1;
/* sai may support mclk/bclk = 1 */
if (of_property_read_bool(np, "fsl,mclk-equal-bclk")) {
link_data->one2one_ratio = true;
} else {
int i;
/*
* i.MX8MQ don't support one2one ratio, then
* with ak4497 only 16bit case is supported.
*/
for (i = 0; i < ARRAY_SIZE(ak4497_fs_mul); i++) {
if (ak4497_fs_mul[i].rmin == 705600 &&
ak4497_fs_mul[i].rmax == 768000) {
ak4497_fs_mul[i].wmin = 32;
ak4497_fs_mul[i].wmax = 32;
}
}
}
}
link->platforms->of_node = link->cpus->of_node;
link->id = args.args[0];
codec = of_get_child_by_name(np, "codec");
if (codec) {
ret = snd_soc_of_get_dai_link_codecs(dev, codec, link);
if (ret < 0) {
dev_err_probe(dev, ret, "%s: codec dai not found\n",
link->name);
goto err;
}
plat_data->num_codecs = link->num_codecs;
/* Check the akcodec type */
if (!strcmp(link->codecs->dai_name, "ak4458-aif"))
plat_data->type = CODEC_AK4458;
else if (!strcmp(link->codecs->dai_name, "ak4497-aif"))
plat_data->type = CODEC_AK4497;
else if (!strcmp(link->codecs->dai_name, "ak5558-aif"))
plat_data->type = CODEC_AK5558;
else if (!strcmp(link->codecs->dai_name, "ak5552-aif"))
plat_data->type = CODEC_AK5552;
} else {
link->codecs = &asoc_dummy_dlc;
link->num_codecs = 1;
}
if (!strncmp(link->name, "HiFi-ASRC-FE", 12)) {
/* DPCM frontend */
link->dynamic = 1;
link->dpcm_merged_chan = 1;
ret = of_property_read_u32(args.np, "fsl,asrc-rate", &data->asrc_rate);
if (ret) {
dev_err(dev, "failed to get output rate\n");
ret = -EINVAL;
goto err;
}
ret = of_property_read_u32(args.np, "fsl,asrc-format", &asrc_fmt);
data->asrc_format = (__force snd_pcm_format_t)asrc_fmt;
if (ret) {
/* Fallback to old binding; translate to asrc_format */
ret = of_property_read_u32(args.np, "fsl,asrc-width", &width);
if (ret) {
dev_err(dev,
"failed to decide output format\n");
goto err;
}
if (width == 24)
data->asrc_format = SNDRV_PCM_FORMAT_S24_LE;
else
data->asrc_format = SNDRV_PCM_FORMAT_S16_LE;
}
} else if (!strncmp(link->name, "HiFi-ASRC-BE", 12)) {
/* DPCM backend */
link->no_pcm = 1;
link->platforms->of_node = NULL;
link->platforms->name = "snd-soc-dummy";
link->be_hw_params_fixup = be_hw_params_fixup;
link->ops = &imx_aif_ops_be;
} else {
link->ops = &imx_aif_ops;
}
if (link->no_pcm || link->dynamic)
snd_soc_dai_link_set_capabilities(link);
/* Get dai fmt */
ret = asoc_simple_parse_daifmt(dev, np, codec,
NULL, &link->dai_fmt);
if (ret)
link->dai_fmt = SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBC_CFC |
SND_SOC_DAIFMT_I2S;
/* Get tdm slot */
snd_soc_of_parse_tdm_slot(np, NULL, NULL,
&link_data->slots,
&link_data->slot_width);
/* default value */
if (!link_data->slots)
link_data->slots = 2;
if (!link_data->slot_width)
link_data->slot_width = 32;
link->ignore_pmdown_time = 1;
link->stream_name = link->name;
link++;
link_data++;
of_node_put(cpu);
of_node_put(codec);
of_node_put(platform);
cpu = NULL;
codec = NULL;
platform = NULL;
}
return 0;
err:
of_node_put(cpu);
of_node_put(codec);
of_node_put(platform);
err_put_np:
of_node_put(np);
return ret;
}
static int imx_card_probe(struct platform_device *pdev)
{
struct snd_soc_dai_link *link_be = NULL, *link;
struct imx_card_plat_data *plat_data;
struct imx_card_data *data;
int ret, i;
data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
plat_data = devm_kzalloc(&pdev->dev, sizeof(*plat_data), GFP_KERNEL);
if (!plat_data)
return -ENOMEM;
data->plat_data = plat_data;
data->card.dev = &pdev->dev;
dev_set_drvdata(&pdev->dev, &data->card);
snd_soc_card_set_drvdata(&data->card, data);
ret = imx_card_parse_of(data);
if (ret)
return ret;
data->num_dapm_routes = plat_data->num_codecs + 1;
data->dapm_routes = devm_kcalloc(&pdev->dev, data->num_dapm_routes,
sizeof(struct snd_soc_dapm_route),
GFP_KERNEL);
if (!data->dapm_routes)
return -ENOMEM;
/* configure the dapm routes */
switch (plat_data->type) {
case CODEC_AK4458:
case CODEC_AK4497:
if (plat_data->num_codecs == 1) {
data->dapm_routes[0].sink = "Playback";
data->dapm_routes[0].source = "CPU-Playback";
i = 1;
} else {
for (i = 0; i < plat_data->num_codecs; i++) {
data->dapm_routes[i].sink =
devm_kasprintf(&pdev->dev, GFP_KERNEL, "%d %s",
i + 1, "Playback");
data->dapm_routes[i].source = "CPU-Playback";
}
}
data->dapm_routes[i].sink = "CPU-Playback";
data->dapm_routes[i].source = "ASRC-Playback";
break;
case CODEC_AK5558:
case CODEC_AK5552:
if (plat_data->num_codecs == 1) {
data->dapm_routes[0].sink = "CPU-Capture";
data->dapm_routes[0].source = "Capture";
i = 1;
} else {
for (i = 0; i < plat_data->num_codecs; i++) {
data->dapm_routes[i].source =
devm_kasprintf(&pdev->dev, GFP_KERNEL, "%d %s",
i + 1, "Capture");
data->dapm_routes[i].sink = "CPU-Capture";
}
}
data->dapm_routes[i].sink = "ASRC-Capture";
data->dapm_routes[i].source = "CPU-Capture";
break;
default:
break;
}
/* default platform data for akcodecs */
if (codec_is_akcodec(plat_data->type)) {
plat_data->support_rates = akcodec_rates;
plat_data->num_rates = ARRAY_SIZE(akcodec_rates);
plat_data->support_tdm_rates = akcodec_tdm_rates;
plat_data->num_tdm_rates = ARRAY_SIZE(akcodec_tdm_rates);
switch (plat_data->type) {
case CODEC_AK4458:
plat_data->fs_mul = ak4458_fs_mul;
plat_data->num_fs_mul = ARRAY_SIZE(ak4458_fs_mul);
plat_data->tdm_fs_mul = ak4458_tdm_fs_mul;
plat_data->num_tdm_fs_mul = ARRAY_SIZE(ak4458_tdm_fs_mul);
plat_data->support_channels = ak4458_channels;
plat_data->num_channels = ARRAY_SIZE(ak4458_channels);
plat_data->support_tdm_channels = ak4458_tdm_channels;
plat_data->num_tdm_channels = ARRAY_SIZE(ak4458_tdm_channels);
break;
case CODEC_AK4497:
plat_data->fs_mul = ak4497_fs_mul;
plat_data->num_fs_mul = ARRAY_SIZE(ak4497_fs_mul);
plat_data->support_channels = ak4458_channels;
plat_data->num_channels = ARRAY_SIZE(ak4458_channels);
break;
case CODEC_AK5558:
case CODEC_AK5552:
plat_data->fs_mul = ak5558_fs_mul;
plat_data->num_fs_mul = ARRAY_SIZE(ak5558_fs_mul);
plat_data->tdm_fs_mul = ak5558_tdm_fs_mul;
plat_data->num_tdm_fs_mul = ARRAY_SIZE(ak5558_tdm_fs_mul);
plat_data->support_channels = ak5558_channels;
plat_data->num_channels = ARRAY_SIZE(ak5558_channels);
plat_data->support_tdm_channels = ak5558_tdm_channels;
plat_data->num_tdm_channels = ARRAY_SIZE(ak5558_tdm_channels);
break;
default:
break;
}
}
/* with asrc as front end */
if (data->card.num_links == 3) {
data->card.dapm_routes = data->dapm_routes;
data->card.num_dapm_routes = data->num_dapm_routes;
for_each_card_prelinks(&data->card, i, link) {
if (link->no_pcm == 1)
link_be = link;
}
for_each_card_prelinks(&data->card, i, link) {
if (link->dynamic == 1 && link_be) {
link->dpcm_playback = link_be->dpcm_playback;
link->dpcm_capture = link_be->dpcm_capture;
}
}
}
ret = devm_snd_soc_register_card(&pdev->dev, &data->card);
if (ret)
return dev_err_probe(&pdev->dev, ret, "snd_soc_register_card failed\n");
return 0;
}
static const struct of_device_id imx_card_dt_ids[] = {
{ .compatible = "fsl,imx-audio-card", },
{ },
};
MODULE_DEVICE_TABLE(of, imx_card_dt_ids);
static struct platform_driver imx_card_driver = {
.driver = {
.name = "imx-card",
.pm = &snd_soc_pm_ops,
.of_match_table = imx_card_dt_ids,
},
.probe = imx_card_probe,
};
module_platform_driver(imx_card_driver);
MODULE_DESCRIPTION("Freescale i.MX ASoC Machine Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:imx-card");
| linux-master | sound/soc/fsl/imx-card.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Freescale MPC5200 PSC in I2S mode
// ALSA SoC Digital Audio Interface (DAI) driver
//
// Copyright (C) 2008 Secret Lab Technologies Ltd.
// Copyright (C) 2009 Jon Smirl, Digispeaker
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/of_platform.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <asm/mpc52xx_psc.h>
#include "mpc5200_dma.h"
/**
* PSC_I2S_RATES: sample rates supported by the I2S
*
* This driver currently only supports the PSC running in I2S slave mode,
* which means the codec determines the sample rate. Therefore, we tell
* ALSA that we support all rates and let the codec driver decide what rates
* are really supported.
*/
#define PSC_I2S_RATES SNDRV_PCM_RATE_CONTINUOUS
/**
* PSC_I2S_FORMATS: audio formats supported by the PSC I2S mode
*/
#define PSC_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \
SNDRV_PCM_FMTBIT_S24_BE | SNDRV_PCM_FMTBIT_S32_BE)
static int psc_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
u32 mode;
dev_dbg(psc_dma->dev, "%s(substream=%p) p_size=%i p_bytes=%i"
" periods=%i buffer_size=%i buffer_bytes=%i\n",
__func__, substream, params_period_size(params),
params_period_bytes(params), params_periods(params),
params_buffer_size(params), params_buffer_bytes(params));
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S8:
mode = MPC52xx_PSC_SICR_SIM_CODEC_8;
break;
case SNDRV_PCM_FORMAT_S16_BE:
mode = MPC52xx_PSC_SICR_SIM_CODEC_16;
break;
case SNDRV_PCM_FORMAT_S24_BE:
mode = MPC52xx_PSC_SICR_SIM_CODEC_24;
break;
case SNDRV_PCM_FORMAT_S32_BE:
mode = MPC52xx_PSC_SICR_SIM_CODEC_32;
break;
default:
dev_dbg(psc_dma->dev, "invalid format\n");
return -EINVAL;
}
out_be32(&psc_dma->psc_regs->sicr, psc_dma->sicr | mode);
return 0;
}
/**
* psc_i2s_set_sysclk: set the clock frequency and direction
*
* This function is called by the machine driver to tell us what the clock
* frequency and direction are.
*
* Currently, we only support operating as a clock slave (SND_SOC_CLOCK_IN),
* and we don't care about the frequency. Return an error if the direction
* is not SND_SOC_CLOCK_IN.
*
* @clk_id: reserved, should be zero
* @freq: the frequency of the given clock ID, currently ignored
* @dir: SND_SOC_CLOCK_IN (clock slave) or SND_SOC_CLOCK_OUT (clock master)
*/
static int psc_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
int clk_id, unsigned int freq, int dir)
{
struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(cpu_dai);
dev_dbg(psc_dma->dev, "psc_i2s_set_sysclk(cpu_dai=%p, dir=%i)\n",
cpu_dai, dir);
return (dir == SND_SOC_CLOCK_IN) ? 0 : -EINVAL;
}
/**
* psc_i2s_set_fmt: set the serial format.
*
* This function is called by the machine driver to tell us what serial
* format to use.
*
* This driver only supports I2S mode. Return an error if the format is
* not SND_SOC_DAIFMT_I2S.
*
* @format: one of SND_SOC_DAIFMT_xxx
*/
static int psc_i2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int format)
{
struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(cpu_dai);
dev_dbg(psc_dma->dev, "psc_i2s_set_fmt(cpu_dai=%p, format=%i)\n",
cpu_dai, format);
return (format == SND_SOC_DAIFMT_I2S) ? 0 : -EINVAL;
}
/* ---------------------------------------------------------------------
* ALSA SoC Bindings
*
* - Digital Audio Interface (DAI) template
* - create/destroy dai hooks
*/
/**
* psc_i2s_dai_template: template CPU Digital Audio Interface
*/
static const struct snd_soc_dai_ops psc_i2s_dai_ops = {
.hw_params = psc_i2s_hw_params,
.set_sysclk = psc_i2s_set_sysclk,
.set_fmt = psc_i2s_set_fmt,
};
static struct snd_soc_dai_driver psc_i2s_dai[] = {{
.name = "mpc5200-psc-i2s.0",
.playback = {
.stream_name = "I2S Playback",
.channels_min = 2,
.channels_max = 2,
.rates = PSC_I2S_RATES,
.formats = PSC_I2S_FORMATS,
},
.capture = {
.stream_name = "I2S Capture",
.channels_min = 2,
.channels_max = 2,
.rates = PSC_I2S_RATES,
.formats = PSC_I2S_FORMATS,
},
.ops = &psc_i2s_dai_ops,
} };
static const struct snd_soc_component_driver psc_i2s_component = {
.name = "mpc5200-i2s",
.legacy_dai_naming = 1,
};
/* ---------------------------------------------------------------------
* OF platform bus binding code:
* - Probe/remove operations
* - OF device match table
*/
static int psc_i2s_of_probe(struct platform_device *op)
{
int rc;
struct psc_dma *psc_dma;
struct mpc52xx_psc __iomem *regs;
rc = mpc5200_audio_dma_create(op);
if (rc != 0)
return rc;
rc = snd_soc_register_component(&op->dev, &psc_i2s_component,
psc_i2s_dai, ARRAY_SIZE(psc_i2s_dai));
if (rc != 0) {
pr_err("Failed to register DAI\n");
return rc;
}
psc_dma = dev_get_drvdata(&op->dev);
regs = psc_dma->psc_regs;
/* Configure the serial interface mode; defaulting to CODEC8 mode */
psc_dma->sicr = MPC52xx_PSC_SICR_DTS1 | MPC52xx_PSC_SICR_I2S |
MPC52xx_PSC_SICR_CLKPOL;
out_be32(&psc_dma->psc_regs->sicr,
psc_dma->sicr | MPC52xx_PSC_SICR_SIM_CODEC_8);
/* Check for the codec handle. If it is not present then we
* are done */
if (!of_get_property(op->dev.of_node, "codec-handle", NULL))
return 0;
/* Due to errata in the dma mode; need to line up enabling
* the transmitter with a transition on the frame sync
* line */
/* first make sure it is low */
while ((in_8(®s->ipcr_acr.ipcr) & 0x80) != 0)
;
/* then wait for the transition to high */
while ((in_8(®s->ipcr_acr.ipcr) & 0x80) == 0)
;
/* Finally, enable the PSC.
* Receiver must always be enabled; even when we only want
* transmit. (see 15.3.2.3 of MPC5200B User's Guide) */
/* Go */
out_8(&psc_dma->psc_regs->command,
MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);
return 0;
}
static void psc_i2s_of_remove(struct platform_device *op)
{
mpc5200_audio_dma_destroy(op);
snd_soc_unregister_component(&op->dev);
}
/* Match table for of_platform binding */
static const struct of_device_id psc_i2s_match[] = {
{ .compatible = "fsl,mpc5200-psc-i2s", },
{ .compatible = "fsl,mpc5200b-psc-i2s", },
{}
};
MODULE_DEVICE_TABLE(of, psc_i2s_match);
static struct platform_driver psc_i2s_driver = {
.probe = psc_i2s_of_probe,
.remove_new = psc_i2s_of_remove,
.driver = {
.name = "mpc5200-psc-i2s",
.of_match_table = psc_i2s_match,
},
};
module_platform_driver(psc_i2s_driver);
MODULE_AUTHOR("Grant Likely <[email protected]>");
MODULE_DESCRIPTION("Freescale MPC5200 PSC in I2S mode ASoC Driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/fsl/mpc5200_psc_i2s.c |
// SPDX-License-Identifier: GPL-2.0
//
// Freescale Generic ASoC Sound Card driver with ASRC
//
// Copyright (C) 2014 Freescale Semiconductor, Inc.
//
// Author: Nicolin Chen <[email protected]>
#include <linux/clk.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#if IS_ENABLED(CONFIG_SND_AC97_CODEC)
#include <sound/ac97_codec.h>
#endif
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/jack.h>
#include <sound/simple_card_utils.h>
#include "fsl_esai.h"
#include "fsl_sai.h"
#include "imx-audmux.h"
#include "../codecs/sgtl5000.h"
#include "../codecs/wm8962.h"
#include "../codecs/wm8960.h"
#include "../codecs/wm8994.h"
#include "../codecs/tlv320aic31xx.h"
#include "../codecs/nau8822.h"
#define DRIVER_NAME "fsl-asoc-card"
#define CS427x_SYSCLK_MCLK 0
#define RX 0
#define TX 1
/* Default DAI format without Master and Slave flag */
#define DAI_FMT_BASE (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF)
/**
* struct codec_priv - CODEC private data
* @mclk_freq: Clock rate of MCLK
* @free_freq: Clock rate of MCLK for hw_free()
* @mclk_id: MCLK (or main clock) id for set_sysclk()
* @fll_id: FLL (or secordary clock) id for set_sysclk()
* @pll_id: PLL id for set_pll()
*/
struct codec_priv {
struct clk *mclk;
unsigned long mclk_freq;
unsigned long free_freq;
u32 mclk_id;
u32 fll_id;
u32 pll_id;
};
/**
* struct cpu_priv - CPU private data
* @sysclk_freq: SYSCLK rates for set_sysclk()
* @sysclk_dir: SYSCLK directions for set_sysclk()
* @sysclk_id: SYSCLK ids for set_sysclk()
* @slot_width: Slot width of each frame
* @slot_num: Number of slots of each frame
*
* Note: [1] for tx and [0] for rx
*/
struct cpu_priv {
unsigned long sysclk_freq[2];
u32 sysclk_dir[2];
u32 sysclk_id[2];
u32 slot_width;
u32 slot_num;
};
/**
* struct fsl_asoc_card_priv - Freescale Generic ASOC card private data
* @dai_link: DAI link structure including normal one and DPCM link
* @hp_jack: Headphone Jack structure
* @mic_jack: Microphone Jack structure
* @pdev: platform device pointer
* @codec_priv: CODEC private data
* @cpu_priv: CPU private data
* @card: ASoC card structure
* @streams: Mask of current active streams
* @sample_rate: Current sample rate
* @sample_format: Current sample format
* @asrc_rate: ASRC sample rate used by Back-Ends
* @asrc_format: ASRC sample format used by Back-Ends
* @dai_fmt: DAI format between CPU and CODEC
* @name: Card name
*/
struct fsl_asoc_card_priv {
struct snd_soc_dai_link dai_link[3];
struct asoc_simple_jack hp_jack;
struct asoc_simple_jack mic_jack;
struct platform_device *pdev;
struct codec_priv codec_priv;
struct cpu_priv cpu_priv;
struct snd_soc_card card;
u8 streams;
u32 sample_rate;
snd_pcm_format_t sample_format;
u32 asrc_rate;
snd_pcm_format_t asrc_format;
u32 dai_fmt;
char name[32];
};
/*
* This dapm route map exists for DPCM link only.
* The other routes shall go through Device Tree.
*
* Note: keep all ASRC routes in the second half
* to drop them easily for non-ASRC cases.
*/
static const struct snd_soc_dapm_route audio_map[] = {
/* 1st half -- Normal DAPM routes */
{"Playback", NULL, "CPU-Playback"},
{"CPU-Capture", NULL, "Capture"},
/* 2nd half -- ASRC DAPM routes */
{"CPU-Playback", NULL, "ASRC-Playback"},
{"ASRC-Capture", NULL, "CPU-Capture"},
};
static const struct snd_soc_dapm_route audio_map_ac97[] = {
/* 1st half -- Normal DAPM routes */
{"AC97 Playback", NULL, "CPU AC97 Playback"},
{"CPU AC97 Capture", NULL, "AC97 Capture"},
/* 2nd half -- ASRC DAPM routes */
{"CPU AC97 Playback", NULL, "ASRC-Playback"},
{"ASRC-Capture", NULL, "CPU AC97 Capture"},
};
static const struct snd_soc_dapm_route audio_map_tx[] = {
/* 1st half -- Normal DAPM routes */
{"Playback", NULL, "CPU-Playback"},
/* 2nd half -- ASRC DAPM routes */
{"CPU-Playback", NULL, "ASRC-Playback"},
};
static const struct snd_soc_dapm_route audio_map_rx[] = {
/* 1st half -- Normal DAPM routes */
{"CPU-Capture", NULL, "Capture"},
/* 2nd half -- ASRC DAPM routes */
{"ASRC-Capture", NULL, "CPU-Capture"},
};
/* Add all possible widgets into here without being redundant */
static const struct snd_soc_dapm_widget fsl_asoc_card_dapm_widgets[] = {
SND_SOC_DAPM_LINE("Line Out Jack", NULL),
SND_SOC_DAPM_LINE("Line In Jack", NULL),
SND_SOC_DAPM_HP("Headphone Jack", NULL),
SND_SOC_DAPM_SPK("Ext Spk", NULL),
SND_SOC_DAPM_MIC("Mic Jack", NULL),
SND_SOC_DAPM_MIC("AMIC", NULL),
SND_SOC_DAPM_MIC("DMIC", NULL),
};
static bool fsl_asoc_card_is_ac97(struct fsl_asoc_card_priv *priv)
{
return priv->dai_fmt == SND_SOC_DAIFMT_AC97;
}
static int fsl_asoc_card_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct fsl_asoc_card_priv *priv = snd_soc_card_get_drvdata(rtd->card);
bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
struct codec_priv *codec_priv = &priv->codec_priv;
struct cpu_priv *cpu_priv = &priv->cpu_priv;
struct device *dev = rtd->card->dev;
unsigned int pll_out;
int ret;
priv->sample_rate = params_rate(params);
priv->sample_format = params_format(params);
priv->streams |= BIT(substream->stream);
if (fsl_asoc_card_is_ac97(priv))
return 0;
/* Specific configurations of DAIs starts from here */
ret = snd_soc_dai_set_sysclk(asoc_rtd_to_cpu(rtd, 0), cpu_priv->sysclk_id[tx],
cpu_priv->sysclk_freq[tx],
cpu_priv->sysclk_dir[tx]);
if (ret && ret != -ENOTSUPP) {
dev_err(dev, "failed to set sysclk for cpu dai\n");
goto fail;
}
if (cpu_priv->slot_width) {
if (!cpu_priv->slot_num)
cpu_priv->slot_num = 2;
ret = snd_soc_dai_set_tdm_slot(asoc_rtd_to_cpu(rtd, 0), 0x3, 0x3,
cpu_priv->slot_num,
cpu_priv->slot_width);
if (ret && ret != -ENOTSUPP) {
dev_err(dev, "failed to set TDM slot for cpu dai\n");
goto fail;
}
}
/* Specific configuration for PLL */
if (codec_priv->pll_id && codec_priv->fll_id) {
if (priv->sample_format == SNDRV_PCM_FORMAT_S24_LE)
pll_out = priv->sample_rate * 384;
else
pll_out = priv->sample_rate * 256;
ret = snd_soc_dai_set_pll(asoc_rtd_to_codec(rtd, 0),
codec_priv->pll_id,
codec_priv->mclk_id,
codec_priv->mclk_freq, pll_out);
if (ret) {
dev_err(dev, "failed to start FLL: %d\n", ret);
goto fail;
}
ret = snd_soc_dai_set_sysclk(asoc_rtd_to_codec(rtd, 0),
codec_priv->fll_id,
pll_out, SND_SOC_CLOCK_IN);
if (ret && ret != -ENOTSUPP) {
dev_err(dev, "failed to set SYSCLK: %d\n", ret);
goto fail;
}
}
return 0;
fail:
priv->streams &= ~BIT(substream->stream);
return ret;
}
static int fsl_asoc_card_hw_free(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct fsl_asoc_card_priv *priv = snd_soc_card_get_drvdata(rtd->card);
struct codec_priv *codec_priv = &priv->codec_priv;
struct device *dev = rtd->card->dev;
int ret;
priv->streams &= ~BIT(substream->stream);
if (!priv->streams && codec_priv->pll_id && codec_priv->fll_id) {
/* Force freq to be free_freq to avoid error message in codec */
ret = snd_soc_dai_set_sysclk(asoc_rtd_to_codec(rtd, 0),
codec_priv->mclk_id,
codec_priv->free_freq,
SND_SOC_CLOCK_IN);
if (ret) {
dev_err(dev, "failed to switch away from FLL: %d\n", ret);
return ret;
}
ret = snd_soc_dai_set_pll(asoc_rtd_to_codec(rtd, 0),
codec_priv->pll_id, 0, 0, 0);
if (ret && ret != -ENOTSUPP) {
dev_err(dev, "failed to stop FLL: %d\n", ret);
return ret;
}
}
return 0;
}
static const struct snd_soc_ops fsl_asoc_card_ops = {
.hw_params = fsl_asoc_card_hw_params,
.hw_free = fsl_asoc_card_hw_free,
};
static int be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
struct snd_pcm_hw_params *params)
{
struct fsl_asoc_card_priv *priv = snd_soc_card_get_drvdata(rtd->card);
struct snd_interval *rate;
struct snd_mask *mask;
rate = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
rate->max = rate->min = priv->asrc_rate;
mask = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
snd_mask_none(mask);
snd_mask_set_format(mask, priv->asrc_format);
return 0;
}
SND_SOC_DAILINK_DEFS(hifi,
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(hifi_fe,
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_DUMMY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(hifi_be,
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_DUMMY()));
static const struct snd_soc_dai_link fsl_asoc_card_dai[] = {
/* Default ASoC DAI Link*/
{
.name = "HiFi",
.stream_name = "HiFi",
.ops = &fsl_asoc_card_ops,
SND_SOC_DAILINK_REG(hifi),
},
/* DPCM Link between Front-End and Back-End (Optional) */
{
.name = "HiFi-ASRC-FE",
.stream_name = "HiFi-ASRC-FE",
.dpcm_playback = 1,
.dpcm_capture = 1,
.dynamic = 1,
SND_SOC_DAILINK_REG(hifi_fe),
},
{
.name = "HiFi-ASRC-BE",
.stream_name = "HiFi-ASRC-BE",
.be_hw_params_fixup = be_hw_params_fixup,
.ops = &fsl_asoc_card_ops,
.dpcm_playback = 1,
.dpcm_capture = 1,
.no_pcm = 1,
SND_SOC_DAILINK_REG(hifi_be),
},
};
static int fsl_asoc_card_audmux_init(struct device_node *np,
struct fsl_asoc_card_priv *priv)
{
struct device *dev = &priv->pdev->dev;
u32 int_ptcr = 0, ext_ptcr = 0;
int int_port, ext_port;
int ret;
ret = of_property_read_u32(np, "mux-int-port", &int_port);
if (ret) {
dev_err(dev, "mux-int-port missing or invalid\n");
return ret;
}
ret = of_property_read_u32(np, "mux-ext-port", &ext_port);
if (ret) {
dev_err(dev, "mux-ext-port missing or invalid\n");
return ret;
}
/*
* The port numbering in the hardware manual starts at 1, while
* the AUDMUX API expects it starts at 0.
*/
int_port--;
ext_port--;
/*
* Use asynchronous mode (6 wires) for all cases except AC97.
* If only 4 wires are needed, just set SSI into
* synchronous mode and enable 4 PADs in IOMUX.
*/
switch (priv->dai_fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBP_CFP:
int_ptcr = IMX_AUDMUX_V2_PTCR_RFSEL(8 | ext_port) |
IMX_AUDMUX_V2_PTCR_RCSEL(8 | ext_port) |
IMX_AUDMUX_V2_PTCR_TFSEL(ext_port) |
IMX_AUDMUX_V2_PTCR_TCSEL(ext_port) |
IMX_AUDMUX_V2_PTCR_RFSDIR |
IMX_AUDMUX_V2_PTCR_RCLKDIR |
IMX_AUDMUX_V2_PTCR_TFSDIR |
IMX_AUDMUX_V2_PTCR_TCLKDIR;
break;
case SND_SOC_DAIFMT_CBP_CFC:
int_ptcr = IMX_AUDMUX_V2_PTCR_RCSEL(8 | ext_port) |
IMX_AUDMUX_V2_PTCR_TCSEL(ext_port) |
IMX_AUDMUX_V2_PTCR_RCLKDIR |
IMX_AUDMUX_V2_PTCR_TCLKDIR;
ext_ptcr = IMX_AUDMUX_V2_PTCR_RFSEL(8 | int_port) |
IMX_AUDMUX_V2_PTCR_TFSEL(int_port) |
IMX_AUDMUX_V2_PTCR_RFSDIR |
IMX_AUDMUX_V2_PTCR_TFSDIR;
break;
case SND_SOC_DAIFMT_CBC_CFP:
int_ptcr = IMX_AUDMUX_V2_PTCR_RFSEL(8 | ext_port) |
IMX_AUDMUX_V2_PTCR_TFSEL(ext_port) |
IMX_AUDMUX_V2_PTCR_RFSDIR |
IMX_AUDMUX_V2_PTCR_TFSDIR;
ext_ptcr = IMX_AUDMUX_V2_PTCR_RCSEL(8 | int_port) |
IMX_AUDMUX_V2_PTCR_TCSEL(int_port) |
IMX_AUDMUX_V2_PTCR_RCLKDIR |
IMX_AUDMUX_V2_PTCR_TCLKDIR;
break;
case SND_SOC_DAIFMT_CBC_CFC:
ext_ptcr = IMX_AUDMUX_V2_PTCR_RFSEL(8 | int_port) |
IMX_AUDMUX_V2_PTCR_RCSEL(8 | int_port) |
IMX_AUDMUX_V2_PTCR_TFSEL(int_port) |
IMX_AUDMUX_V2_PTCR_TCSEL(int_port) |
IMX_AUDMUX_V2_PTCR_RFSDIR |
IMX_AUDMUX_V2_PTCR_RCLKDIR |
IMX_AUDMUX_V2_PTCR_TFSDIR |
IMX_AUDMUX_V2_PTCR_TCLKDIR;
break;
default:
if (!fsl_asoc_card_is_ac97(priv))
return -EINVAL;
}
if (fsl_asoc_card_is_ac97(priv)) {
int_ptcr = IMX_AUDMUX_V2_PTCR_SYN |
IMX_AUDMUX_V2_PTCR_TCSEL(ext_port) |
IMX_AUDMUX_V2_PTCR_TCLKDIR;
ext_ptcr = IMX_AUDMUX_V2_PTCR_SYN |
IMX_AUDMUX_V2_PTCR_TFSEL(int_port) |
IMX_AUDMUX_V2_PTCR_TFSDIR;
}
/* Asynchronous mode can not be set along with RCLKDIR */
if (!fsl_asoc_card_is_ac97(priv)) {
unsigned int pdcr =
IMX_AUDMUX_V2_PDCR_RXDSEL(ext_port);
ret = imx_audmux_v2_configure_port(int_port, 0,
pdcr);
if (ret) {
dev_err(dev, "audmux internal port setup failed\n");
return ret;
}
}
ret = imx_audmux_v2_configure_port(int_port, int_ptcr,
IMX_AUDMUX_V2_PDCR_RXDSEL(ext_port));
if (ret) {
dev_err(dev, "audmux internal port setup failed\n");
return ret;
}
if (!fsl_asoc_card_is_ac97(priv)) {
unsigned int pdcr =
IMX_AUDMUX_V2_PDCR_RXDSEL(int_port);
ret = imx_audmux_v2_configure_port(ext_port, 0,
pdcr);
if (ret) {
dev_err(dev, "audmux external port setup failed\n");
return ret;
}
}
ret = imx_audmux_v2_configure_port(ext_port, ext_ptcr,
IMX_AUDMUX_V2_PDCR_RXDSEL(int_port));
if (ret) {
dev_err(dev, "audmux external port setup failed\n");
return ret;
}
return 0;
}
static int hp_jack_event(struct notifier_block *nb, unsigned long event,
void *data)
{
struct snd_soc_jack *jack = (struct snd_soc_jack *)data;
struct snd_soc_dapm_context *dapm = &jack->card->dapm;
if (event & SND_JACK_HEADPHONE)
/* Disable speaker if headphone is plugged in */
return snd_soc_dapm_disable_pin(dapm, "Ext Spk");
else
return snd_soc_dapm_enable_pin(dapm, "Ext Spk");
}
static struct notifier_block hp_jack_nb = {
.notifier_call = hp_jack_event,
};
static int mic_jack_event(struct notifier_block *nb, unsigned long event,
void *data)
{
struct snd_soc_jack *jack = (struct snd_soc_jack *)data;
struct snd_soc_dapm_context *dapm = &jack->card->dapm;
if (event & SND_JACK_MICROPHONE)
/* Disable dmic if microphone is plugged in */
return snd_soc_dapm_disable_pin(dapm, "DMIC");
else
return snd_soc_dapm_enable_pin(dapm, "DMIC");
}
static struct notifier_block mic_jack_nb = {
.notifier_call = mic_jack_event,
};
static int fsl_asoc_card_late_probe(struct snd_soc_card *card)
{
struct fsl_asoc_card_priv *priv = snd_soc_card_get_drvdata(card);
struct snd_soc_pcm_runtime *rtd = list_first_entry(
&card->rtd_list, struct snd_soc_pcm_runtime, list);
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
struct codec_priv *codec_priv = &priv->codec_priv;
struct device *dev = card->dev;
int ret;
if (fsl_asoc_card_is_ac97(priv)) {
#if IS_ENABLED(CONFIG_SND_AC97_CODEC)
struct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component;
struct snd_ac97 *ac97 = snd_soc_component_get_drvdata(component);
/*
* Use slots 3/4 for S/PDIF so SSI won't try to enable
* other slots and send some samples there
* due to SLOTREQ bits for S/PDIF received from codec
*/
snd_ac97_update_bits(ac97, AC97_EXTENDED_STATUS,
AC97_EA_SPSA_SLOT_MASK, AC97_EA_SPSA_3_4);
#endif
return 0;
}
ret = snd_soc_dai_set_sysclk(codec_dai, codec_priv->mclk_id,
codec_priv->mclk_freq, SND_SOC_CLOCK_IN);
if (ret && ret != -ENOTSUPP) {
dev_err(dev, "failed to set sysclk in %s\n", __func__);
return ret;
}
if (!IS_ERR_OR_NULL(codec_priv->mclk))
clk_prepare_enable(codec_priv->mclk);
return 0;
}
static int fsl_asoc_card_probe(struct platform_device *pdev)
{
struct device_node *cpu_np, *codec_np, *asrc_np;
struct device_node *np = pdev->dev.of_node;
struct platform_device *asrc_pdev = NULL;
struct device_node *bitclkprovider = NULL;
struct device_node *frameprovider = NULL;
struct platform_device *cpu_pdev;
struct fsl_asoc_card_priv *priv;
struct device *codec_dev = NULL;
const char *codec_dai_name;
const char *codec_dev_name;
u32 asrc_fmt = 0;
u32 width;
int ret;
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
cpu_np = of_parse_phandle(np, "audio-cpu", 0);
/* Give a chance to old DT binding */
if (!cpu_np)
cpu_np = of_parse_phandle(np, "ssi-controller", 0);
if (!cpu_np) {
dev_err(&pdev->dev, "CPU phandle missing or invalid\n");
ret = -EINVAL;
goto fail;
}
cpu_pdev = of_find_device_by_node(cpu_np);
if (!cpu_pdev) {
dev_err(&pdev->dev, "failed to find CPU DAI device\n");
ret = -EINVAL;
goto fail;
}
codec_np = of_parse_phandle(np, "audio-codec", 0);
if (codec_np) {
struct platform_device *codec_pdev;
struct i2c_client *codec_i2c;
codec_i2c = of_find_i2c_device_by_node(codec_np);
if (codec_i2c) {
codec_dev = &codec_i2c->dev;
codec_dev_name = codec_i2c->name;
}
if (!codec_dev) {
codec_pdev = of_find_device_by_node(codec_np);
if (codec_pdev) {
codec_dev = &codec_pdev->dev;
codec_dev_name = codec_pdev->name;
}
}
}
asrc_np = of_parse_phandle(np, "audio-asrc", 0);
if (asrc_np)
asrc_pdev = of_find_device_by_node(asrc_np);
/* Get the MCLK rate only, and leave it controlled by CODEC drivers */
if (codec_dev) {
struct clk *codec_clk = clk_get(codec_dev, NULL);
if (!IS_ERR(codec_clk)) {
priv->codec_priv.mclk_freq = clk_get_rate(codec_clk);
clk_put(codec_clk);
}
}
/* Default sample rate and format, will be updated in hw_params() */
priv->sample_rate = 44100;
priv->sample_format = SNDRV_PCM_FORMAT_S16_LE;
/* Assign a default DAI format, and allow each card to overwrite it */
priv->dai_fmt = DAI_FMT_BASE;
memcpy(priv->dai_link, fsl_asoc_card_dai,
sizeof(struct snd_soc_dai_link) * ARRAY_SIZE(priv->dai_link));
priv->card.dapm_routes = audio_map;
priv->card.num_dapm_routes = ARRAY_SIZE(audio_map);
priv->card.driver_name = DRIVER_NAME;
/* Diversify the card configurations */
if (of_device_is_compatible(np, "fsl,imx-audio-cs42888")) {
codec_dai_name = "cs42888";
priv->cpu_priv.sysclk_freq[TX] = priv->codec_priv.mclk_freq;
priv->cpu_priv.sysclk_freq[RX] = priv->codec_priv.mclk_freq;
priv->cpu_priv.sysclk_dir[TX] = SND_SOC_CLOCK_OUT;
priv->cpu_priv.sysclk_dir[RX] = SND_SOC_CLOCK_OUT;
priv->cpu_priv.slot_width = 32;
priv->dai_fmt |= SND_SOC_DAIFMT_CBC_CFC;
} else if (of_device_is_compatible(np, "fsl,imx-audio-cs427x")) {
codec_dai_name = "cs4271-hifi";
priv->codec_priv.mclk_id = CS427x_SYSCLK_MCLK;
priv->dai_fmt |= SND_SOC_DAIFMT_CBP_CFP;
} else if (of_device_is_compatible(np, "fsl,imx-audio-sgtl5000")) {
codec_dai_name = "sgtl5000";
priv->codec_priv.mclk_id = SGTL5000_SYSCLK;
priv->dai_fmt |= SND_SOC_DAIFMT_CBP_CFP;
} else if (of_device_is_compatible(np, "fsl,imx-audio-tlv320aic32x4")) {
codec_dai_name = "tlv320aic32x4-hifi";
priv->dai_fmt |= SND_SOC_DAIFMT_CBP_CFP;
} else if (of_device_is_compatible(np, "fsl,imx-audio-tlv320aic31xx")) {
codec_dai_name = "tlv320dac31xx-hifi";
priv->dai_fmt |= SND_SOC_DAIFMT_CBS_CFS;
priv->dai_link[1].dpcm_capture = 0;
priv->dai_link[2].dpcm_capture = 0;
priv->cpu_priv.sysclk_dir[TX] = SND_SOC_CLOCK_OUT;
priv->cpu_priv.sysclk_dir[RX] = SND_SOC_CLOCK_OUT;
priv->card.dapm_routes = audio_map_tx;
priv->card.num_dapm_routes = ARRAY_SIZE(audio_map_tx);
} else if (of_device_is_compatible(np, "fsl,imx-audio-wm8962")) {
codec_dai_name = "wm8962";
priv->codec_priv.mclk_id = WM8962_SYSCLK_MCLK;
priv->codec_priv.fll_id = WM8962_SYSCLK_FLL;
priv->codec_priv.pll_id = WM8962_FLL;
priv->dai_fmt |= SND_SOC_DAIFMT_CBP_CFP;
} else if (of_device_is_compatible(np, "fsl,imx-audio-wm8960")) {
codec_dai_name = "wm8960-hifi";
priv->codec_priv.fll_id = WM8960_SYSCLK_AUTO;
priv->codec_priv.pll_id = WM8960_SYSCLK_AUTO;
priv->dai_fmt |= SND_SOC_DAIFMT_CBP_CFP;
} else if (of_device_is_compatible(np, "fsl,imx-audio-ac97")) {
codec_dai_name = "ac97-hifi";
priv->dai_fmt = SND_SOC_DAIFMT_AC97;
priv->card.dapm_routes = audio_map_ac97;
priv->card.num_dapm_routes = ARRAY_SIZE(audio_map_ac97);
} else if (of_device_is_compatible(np, "fsl,imx-audio-mqs")) {
codec_dai_name = "fsl-mqs-dai";
priv->dai_fmt = SND_SOC_DAIFMT_LEFT_J |
SND_SOC_DAIFMT_CBC_CFC |
SND_SOC_DAIFMT_NB_NF;
priv->dai_link[1].dpcm_capture = 0;
priv->dai_link[2].dpcm_capture = 0;
priv->card.dapm_routes = audio_map_tx;
priv->card.num_dapm_routes = ARRAY_SIZE(audio_map_tx);
} else if (of_device_is_compatible(np, "fsl,imx-audio-wm8524")) {
codec_dai_name = "wm8524-hifi";
priv->dai_fmt |= SND_SOC_DAIFMT_CBC_CFC;
priv->dai_link[1].dpcm_capture = 0;
priv->dai_link[2].dpcm_capture = 0;
priv->cpu_priv.slot_width = 32;
priv->card.dapm_routes = audio_map_tx;
priv->card.num_dapm_routes = ARRAY_SIZE(audio_map_tx);
} else if (of_device_is_compatible(np, "fsl,imx-audio-si476x")) {
codec_dai_name = "si476x-codec";
priv->dai_fmt |= SND_SOC_DAIFMT_CBC_CFC;
priv->card.dapm_routes = audio_map_rx;
priv->card.num_dapm_routes = ARRAY_SIZE(audio_map_rx);
} else if (of_device_is_compatible(np, "fsl,imx-audio-wm8958")) {
codec_dai_name = "wm8994-aif1";
priv->dai_fmt |= SND_SOC_DAIFMT_CBP_CFP;
priv->codec_priv.mclk_id = WM8994_FLL_SRC_MCLK1;
priv->codec_priv.fll_id = WM8994_SYSCLK_FLL1;
priv->codec_priv.pll_id = WM8994_FLL1;
priv->codec_priv.free_freq = priv->codec_priv.mclk_freq;
priv->card.dapm_routes = NULL;
priv->card.num_dapm_routes = 0;
} else if (of_device_is_compatible(np, "fsl,imx-audio-nau8822")) {
codec_dai_name = "nau8822-hifi";
priv->codec_priv.mclk_id = NAU8822_CLK_MCLK;
priv->codec_priv.fll_id = NAU8822_CLK_PLL;
priv->codec_priv.pll_id = NAU8822_CLK_PLL;
priv->dai_fmt |= SND_SOC_DAIFMT_CBM_CFM;
if (codec_dev)
priv->codec_priv.mclk = devm_clk_get(codec_dev, NULL);
} else {
dev_err(&pdev->dev, "unknown Device Tree compatible\n");
ret = -EINVAL;
goto asrc_fail;
}
/*
* Allow setting mclk-id from the device-tree node. Otherwise, the
* default value for each card configuration is used.
*/
of_property_read_u32(np, "mclk-id", &priv->codec_priv.mclk_id);
/* Format info from DT is optional. */
snd_soc_daifmt_parse_clock_provider_as_phandle(np, NULL, &bitclkprovider, &frameprovider);
if (bitclkprovider || frameprovider) {
unsigned int daifmt = snd_soc_daifmt_parse_format(np, NULL);
if (codec_np == bitclkprovider)
daifmt |= (codec_np == frameprovider) ?
SND_SOC_DAIFMT_CBP_CFP : SND_SOC_DAIFMT_CBP_CFC;
else
daifmt |= (codec_np == frameprovider) ?
SND_SOC_DAIFMT_CBC_CFP : SND_SOC_DAIFMT_CBC_CFC;
/* Override dai_fmt with value from DT */
priv->dai_fmt = daifmt;
}
/* Change direction according to format */
if (priv->dai_fmt & SND_SOC_DAIFMT_CBP_CFP) {
priv->cpu_priv.sysclk_dir[TX] = SND_SOC_CLOCK_IN;
priv->cpu_priv.sysclk_dir[RX] = SND_SOC_CLOCK_IN;
}
of_node_put(bitclkprovider);
of_node_put(frameprovider);
if (!fsl_asoc_card_is_ac97(priv) && !codec_dev) {
dev_dbg(&pdev->dev, "failed to find codec device\n");
ret = -EPROBE_DEFER;
goto asrc_fail;
}
/* Common settings for corresponding Freescale CPU DAI driver */
if (of_node_name_eq(cpu_np, "ssi")) {
/* Only SSI needs to configure AUDMUX */
ret = fsl_asoc_card_audmux_init(np, priv);
if (ret) {
dev_err(&pdev->dev, "failed to init audmux\n");
goto asrc_fail;
}
} else if (of_node_name_eq(cpu_np, "esai")) {
struct clk *esai_clk = clk_get(&cpu_pdev->dev, "extal");
if (!IS_ERR(esai_clk)) {
priv->cpu_priv.sysclk_freq[TX] = clk_get_rate(esai_clk);
priv->cpu_priv.sysclk_freq[RX] = clk_get_rate(esai_clk);
clk_put(esai_clk);
} else if (PTR_ERR(esai_clk) == -EPROBE_DEFER) {
ret = -EPROBE_DEFER;
goto asrc_fail;
}
priv->cpu_priv.sysclk_id[1] = ESAI_HCKT_EXTAL;
priv->cpu_priv.sysclk_id[0] = ESAI_HCKR_EXTAL;
} else if (of_node_name_eq(cpu_np, "sai")) {
priv->cpu_priv.sysclk_id[1] = FSL_SAI_CLK_MAST1;
priv->cpu_priv.sysclk_id[0] = FSL_SAI_CLK_MAST1;
}
/* Initialize sound card */
priv->pdev = pdev;
priv->card.dev = &pdev->dev;
priv->card.owner = THIS_MODULE;
ret = snd_soc_of_parse_card_name(&priv->card, "model");
if (ret) {
snprintf(priv->name, sizeof(priv->name), "%s-audio",
fsl_asoc_card_is_ac97(priv) ? "ac97" : codec_dev_name);
priv->card.name = priv->name;
}
priv->card.dai_link = priv->dai_link;
priv->card.late_probe = fsl_asoc_card_late_probe;
priv->card.dapm_widgets = fsl_asoc_card_dapm_widgets;
priv->card.num_dapm_widgets = ARRAY_SIZE(fsl_asoc_card_dapm_widgets);
/* Drop the second half of DAPM routes -- ASRC */
if (!asrc_pdev)
priv->card.num_dapm_routes /= 2;
if (of_property_read_bool(np, "audio-routing")) {
ret = snd_soc_of_parse_audio_routing(&priv->card, "audio-routing");
if (ret) {
dev_err(&pdev->dev, "failed to parse audio-routing: %d\n", ret);
goto asrc_fail;
}
}
/* Normal DAI Link */
priv->dai_link[0].cpus->of_node = cpu_np;
priv->dai_link[0].codecs->dai_name = codec_dai_name;
if (!fsl_asoc_card_is_ac97(priv))
priv->dai_link[0].codecs->of_node = codec_np;
else {
u32 idx;
ret = of_property_read_u32(cpu_np, "cell-index", &idx);
if (ret) {
dev_err(&pdev->dev,
"cannot get CPU index property\n");
goto asrc_fail;
}
priv->dai_link[0].codecs->name =
devm_kasprintf(&pdev->dev, GFP_KERNEL,
"ac97-codec.%u",
(unsigned int)idx);
if (!priv->dai_link[0].codecs->name) {
ret = -ENOMEM;
goto asrc_fail;
}
}
priv->dai_link[0].platforms->of_node = cpu_np;
priv->dai_link[0].dai_fmt = priv->dai_fmt;
priv->card.num_links = 1;
if (asrc_pdev) {
/* DPCM DAI Links only if ASRC exists */
priv->dai_link[1].cpus->of_node = asrc_np;
priv->dai_link[1].platforms->of_node = asrc_np;
priv->dai_link[2].codecs->dai_name = codec_dai_name;
priv->dai_link[2].codecs->of_node = codec_np;
priv->dai_link[2].codecs->name =
priv->dai_link[0].codecs->name;
priv->dai_link[2].cpus->of_node = cpu_np;
priv->dai_link[2].dai_fmt = priv->dai_fmt;
priv->card.num_links = 3;
ret = of_property_read_u32(asrc_np, "fsl,asrc-rate",
&priv->asrc_rate);
if (ret) {
dev_err(&pdev->dev, "failed to get output rate\n");
ret = -EINVAL;
goto asrc_fail;
}
ret = of_property_read_u32(asrc_np, "fsl,asrc-format", &asrc_fmt);
priv->asrc_format = (__force snd_pcm_format_t)asrc_fmt;
if (ret) {
/* Fallback to old binding; translate to asrc_format */
ret = of_property_read_u32(asrc_np, "fsl,asrc-width",
&width);
if (ret) {
dev_err(&pdev->dev,
"failed to decide output format\n");
goto asrc_fail;
}
if (width == 24)
priv->asrc_format = SNDRV_PCM_FORMAT_S24_LE;
else
priv->asrc_format = SNDRV_PCM_FORMAT_S16_LE;
}
}
/* Finish card registering */
platform_set_drvdata(pdev, priv);
snd_soc_card_set_drvdata(&priv->card, priv);
ret = devm_snd_soc_register_card(&pdev->dev, &priv->card);
if (ret) {
dev_err_probe(&pdev->dev, ret, "snd_soc_register_card failed\n");
goto asrc_fail;
}
/*
* Properties "hp-det-gpio" and "mic-det-gpio" are optional, and
* asoc_simple_init_jack uses these properties for creating
* Headphone Jack and Microphone Jack.
*
* The notifier is initialized in snd_soc_card_jack_new(), then
* snd_soc_jack_notifier_register can be called.
*/
if (of_property_read_bool(np, "hp-det-gpio")) {
ret = asoc_simple_init_jack(&priv->card, &priv->hp_jack,
1, NULL, "Headphone Jack");
if (ret)
goto asrc_fail;
snd_soc_jack_notifier_register(&priv->hp_jack.jack, &hp_jack_nb);
}
if (of_property_read_bool(np, "mic-det-gpio")) {
ret = asoc_simple_init_jack(&priv->card, &priv->mic_jack,
0, NULL, "Mic Jack");
if (ret)
goto asrc_fail;
snd_soc_jack_notifier_register(&priv->mic_jack.jack, &mic_jack_nb);
}
asrc_fail:
of_node_put(asrc_np);
of_node_put(codec_np);
put_device(&cpu_pdev->dev);
fail:
of_node_put(cpu_np);
return ret;
}
static const struct of_device_id fsl_asoc_card_dt_ids[] = {
{ .compatible = "fsl,imx-audio-ac97", },
{ .compatible = "fsl,imx-audio-cs42888", },
{ .compatible = "fsl,imx-audio-cs427x", },
{ .compatible = "fsl,imx-audio-tlv320aic32x4", },
{ .compatible = "fsl,imx-audio-tlv320aic31xx", },
{ .compatible = "fsl,imx-audio-sgtl5000", },
{ .compatible = "fsl,imx-audio-wm8962", },
{ .compatible = "fsl,imx-audio-wm8960", },
{ .compatible = "fsl,imx-audio-mqs", },
{ .compatible = "fsl,imx-audio-wm8524", },
{ .compatible = "fsl,imx-audio-si476x", },
{ .compatible = "fsl,imx-audio-wm8958", },
{ .compatible = "fsl,imx-audio-nau8822", },
{}
};
MODULE_DEVICE_TABLE(of, fsl_asoc_card_dt_ids);
static struct platform_driver fsl_asoc_card_driver = {
.probe = fsl_asoc_card_probe,
.driver = {
.name = DRIVER_NAME,
.pm = &snd_soc_pm_ops,
.of_match_table = fsl_asoc_card_dt_ids,
},
};
module_platform_driver(fsl_asoc_card_driver);
MODULE_DESCRIPTION("Freescale Generic ASoC Sound Card driver with ASRC");
MODULE_AUTHOR("Nicolin Chen <[email protected]>");
MODULE_ALIAS("platform:" DRIVER_NAME);
MODULE_LICENSE("GPL");
| linux-master | sound/soc/fsl/fsl-asoc-card.c |
// SPDX-License-Identifier: GPL-2.0+
// imx-pcm-fiq.c -- ALSA Soc Audio Layer
//
// Copyright 2009 Sascha Hauer <[email protected]>
//
// This code is based on code copyrighted by Freescale,
// Liam Girdwood, Javier Martin and probably others.
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/dmaengine_pcm.h>
#include <sound/initval.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <asm/fiq.h>
#include <linux/platform_data/asoc-imx-ssi.h>
#include "imx-ssi.h"
#include "imx-pcm.h"
struct imx_pcm_runtime_data {
unsigned int period;
int periods;
unsigned long offset;
struct hrtimer hrt;
int poll_time_ns;
struct snd_pcm_substream *substream;
atomic_t playing;
atomic_t capturing;
};
static enum hrtimer_restart snd_hrtimer_callback(struct hrtimer *hrt)
{
struct imx_pcm_runtime_data *iprtd =
container_of(hrt, struct imx_pcm_runtime_data, hrt);
struct snd_pcm_substream *substream = iprtd->substream;
struct pt_regs regs;
if (!atomic_read(&iprtd->playing) && !atomic_read(&iprtd->capturing))
return HRTIMER_NORESTART;
get_fiq_regs(®s);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
iprtd->offset = regs.ARM_r8 & 0xffff;
else
iprtd->offset = regs.ARM_r9 & 0xffff;
snd_pcm_period_elapsed(substream);
hrtimer_forward_now(hrt, ns_to_ktime(iprtd->poll_time_ns));
return HRTIMER_RESTART;
}
static struct fiq_handler fh = {
.name = DRV_NAME,
};
static int snd_imx_pcm_hw_params(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct imx_pcm_runtime_data *iprtd = runtime->private_data;
iprtd->periods = params_periods(params);
iprtd->period = params_period_bytes(params);
iprtd->offset = 0;
iprtd->poll_time_ns = 1000000000 / params_rate(params) *
params_period_size(params);
return 0;
}
static int snd_imx_pcm_prepare(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct imx_pcm_runtime_data *iprtd = runtime->private_data;
struct pt_regs regs;
get_fiq_regs(®s);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
regs.ARM_r8 = (iprtd->period * iprtd->periods - 1) << 16;
else
regs.ARM_r9 = (iprtd->period * iprtd->periods - 1) << 16;
set_fiq_regs(®s);
return 0;
}
static int imx_pcm_fiq;
static int snd_imx_pcm_trigger(struct snd_soc_component *component,
struct snd_pcm_substream *substream, int cmd)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct imx_pcm_runtime_data *iprtd = runtime->private_data;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
atomic_set(&iprtd->playing, 1);
else
atomic_set(&iprtd->capturing, 1);
hrtimer_start(&iprtd->hrt, ns_to_ktime(iprtd->poll_time_ns),
HRTIMER_MODE_REL);
enable_fiq(imx_pcm_fiq);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
atomic_set(&iprtd->playing, 0);
else
atomic_set(&iprtd->capturing, 0);
if (!atomic_read(&iprtd->playing) &&
!atomic_read(&iprtd->capturing))
disable_fiq(imx_pcm_fiq);
break;
default:
return -EINVAL;
}
return 0;
}
static snd_pcm_uframes_t
snd_imx_pcm_pointer(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct imx_pcm_runtime_data *iprtd = runtime->private_data;
return bytes_to_frames(substream->runtime, iprtd->offset);
}
static const struct snd_pcm_hardware snd_imx_hardware = {
.info = SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_BLOCK_TRANSFER |
SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_PAUSE |
SNDRV_PCM_INFO_RESUME,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.buffer_bytes_max = IMX_SSI_DMABUF_SIZE,
.period_bytes_min = 128,
.period_bytes_max = 16 * 1024,
.periods_min = 4,
.periods_max = 255,
.fifo_size = 0,
};
static int snd_imx_open(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct imx_pcm_runtime_data *iprtd;
int ret;
iprtd = kzalloc(sizeof(*iprtd), GFP_KERNEL);
if (iprtd == NULL)
return -ENOMEM;
runtime->private_data = iprtd;
iprtd->substream = substream;
atomic_set(&iprtd->playing, 0);
atomic_set(&iprtd->capturing, 0);
hrtimer_init(&iprtd->hrt, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
iprtd->hrt.function = snd_hrtimer_callback;
ret = snd_pcm_hw_constraint_integer(substream->runtime,
SNDRV_PCM_HW_PARAM_PERIODS);
if (ret < 0) {
kfree(iprtd);
return ret;
}
snd_soc_set_runtime_hwparams(substream, &snd_imx_hardware);
return 0;
}
static int snd_imx_close(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct imx_pcm_runtime_data *iprtd = runtime->private_data;
hrtimer_cancel(&iprtd->hrt);
kfree(iprtd);
return 0;
}
static int imx_pcm_new(struct snd_soc_pcm_runtime *rtd)
{
struct snd_card *card = rtd->card->snd_card;
struct snd_pcm *pcm = rtd->pcm;
int ret;
ret = dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(32));
if (ret)
return ret;
return snd_pcm_set_fixed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV_WC,
pcm->card->dev,
IMX_SSI_DMABUF_SIZE);
}
static int ssi_irq;
static int snd_imx_pcm_new(struct snd_soc_component *component,
struct snd_soc_pcm_runtime *rtd)
{
struct snd_pcm *pcm = rtd->pcm;
struct snd_pcm_substream *substream;
int ret;
ret = imx_pcm_new(rtd);
if (ret)
return ret;
substream = pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
if (substream) {
struct snd_dma_buffer *buf = &substream->dma_buffer;
imx_ssi_fiq_tx_buffer = (unsigned long)buf->area;
}
substream = pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream;
if (substream) {
struct snd_dma_buffer *buf = &substream->dma_buffer;
imx_ssi_fiq_rx_buffer = (unsigned long)buf->area;
}
set_fiq_handler(&imx_ssi_fiq_start,
&imx_ssi_fiq_end - &imx_ssi_fiq_start);
return 0;
}
static void snd_imx_pcm_free(struct snd_soc_component *component,
struct snd_pcm *pcm)
{
mxc_set_irq_fiq(ssi_irq, 0);
release_fiq(&fh);
}
static const struct snd_soc_component_driver imx_soc_component_fiq = {
.open = snd_imx_open,
.close = snd_imx_close,
.hw_params = snd_imx_pcm_hw_params,
.prepare = snd_imx_pcm_prepare,
.trigger = snd_imx_pcm_trigger,
.pointer = snd_imx_pcm_pointer,
.pcm_construct = snd_imx_pcm_new,
.pcm_destruct = snd_imx_pcm_free,
};
int imx_pcm_fiq_init(struct platform_device *pdev,
struct imx_pcm_fiq_params *params)
{
int ret;
ret = claim_fiq(&fh);
if (ret) {
dev_err(&pdev->dev, "failed to claim fiq: %d", ret);
return ret;
}
mxc_set_irq_fiq(params->irq, 1);
ssi_irq = params->irq;
imx_pcm_fiq = params->irq;
imx_ssi_fiq_base = (unsigned long)params->base;
params->dma_params_tx->maxburst = 4;
params->dma_params_rx->maxburst = 6;
ret = devm_snd_soc_register_component(&pdev->dev, &imx_soc_component_fiq,
NULL, 0);
if (ret)
goto failed_register;
return 0;
failed_register:
mxc_set_irq_fiq(ssi_irq, 0);
release_fiq(&fh);
return ret;
}
EXPORT_SYMBOL_GPL(imx_pcm_fiq_init);
void imx_pcm_fiq_exit(struct platform_device *pdev)
{
}
EXPORT_SYMBOL_GPL(imx_pcm_fiq_exit);
MODULE_LICENSE("GPL");
| linux-master | sound/soc/fsl/imx-pcm-fiq.c |
// SPDX-License-Identifier: GPL-2.0-only
//
// Freescale MPC5200 PSC DMA
// ALSA SoC Platform driver
//
// Copyright (C) 2008 Secret Lab Technologies Ltd.
// Copyright (C) 2009 Jon Smirl, Digispeaker
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/dma-mapping.h>
#include <linux/slab.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <sound/soc.h>
#include <linux/fsl/bestcomm/bestcomm.h>
#include <linux/fsl/bestcomm/gen_bd.h>
#include <asm/mpc52xx_psc.h>
#include "mpc5200_dma.h"
#define DRV_NAME "mpc5200_dma"
/*
* Interrupt handlers
*/
static irqreturn_t psc_dma_status_irq(int irq, void *_psc_dma)
{
struct psc_dma *psc_dma = _psc_dma;
struct mpc52xx_psc __iomem *regs = psc_dma->psc_regs;
u16 isr;
isr = in_be16(®s->mpc52xx_psc_isr);
/* Playback underrun error */
if (psc_dma->playback.active && (isr & MPC52xx_PSC_IMR_TXEMP))
psc_dma->stats.underrun_count++;
/* Capture overrun error */
if (psc_dma->capture.active && (isr & MPC52xx_PSC_IMR_ORERR))
psc_dma->stats.overrun_count++;
out_8(®s->command, MPC52xx_PSC_RST_ERR_STAT);
return IRQ_HANDLED;
}
/**
* psc_dma_bcom_enqueue_next_buffer - Enqueue another audio buffer
* @s: pointer to stream private data structure
*
* Enqueues another audio period buffer into the bestcomm queue.
*
* Note: The routine must only be called when there is space available in
* the queue. Otherwise the enqueue will fail and the audio ring buffer
* will get out of sync
*/
static void psc_dma_bcom_enqueue_next_buffer(struct psc_dma_stream *s)
{
struct bcom_bd *bd;
/* Prepare and enqueue the next buffer descriptor */
bd = bcom_prepare_next_buffer(s->bcom_task);
bd->status = s->period_bytes;
bd->data[0] = s->runtime->dma_addr + (s->period_next * s->period_bytes);
bcom_submit_next_buffer(s->bcom_task, NULL);
/* Update for next period */
s->period_next = (s->period_next + 1) % s->runtime->periods;
}
/* Bestcomm DMA irq handler */
static irqreturn_t psc_dma_bcom_irq(int irq, void *_psc_dma_stream)
{
struct psc_dma_stream *s = _psc_dma_stream;
spin_lock(&s->psc_dma->lock);
/* For each finished period, dequeue the completed period buffer
* and enqueue a new one in it's place. */
while (bcom_buffer_done(s->bcom_task)) {
bcom_retrieve_buffer(s->bcom_task, NULL, NULL);
s->period_current = (s->period_current+1) % s->runtime->periods;
s->period_count++;
psc_dma_bcom_enqueue_next_buffer(s);
}
spin_unlock(&s->psc_dma->lock);
/* If the stream is active, then also inform the PCM middle layer
* of the period finished event. */
if (s->active)
snd_pcm_period_elapsed(s->stream);
return IRQ_HANDLED;
}
/**
* psc_dma_trigger: start and stop the DMA transfer.
*
* This function is called by ALSA to start, stop, pause, and resume the DMA
* transfer of data.
*/
static int psc_dma_trigger(struct snd_soc_component *component,
struct snd_pcm_substream *substream, int cmd)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
struct snd_pcm_runtime *runtime = substream->runtime;
struct psc_dma_stream *s = to_psc_dma_stream(substream, psc_dma);
struct mpc52xx_psc __iomem *regs = psc_dma->psc_regs;
u16 imr;
unsigned long flags;
int i;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
dev_dbg(psc_dma->dev, "START: stream=%i fbits=%u ps=%u #p=%u\n",
substream->pstr->stream, runtime->frame_bits,
(int)runtime->period_size, runtime->periods);
s->period_bytes = frames_to_bytes(runtime,
runtime->period_size);
s->period_next = 0;
s->period_current = 0;
s->active = 1;
s->period_count = 0;
s->runtime = runtime;
/* Fill up the bestcomm bd queue and enable DMA.
* This will begin filling the PSC's fifo.
*/
spin_lock_irqsave(&psc_dma->lock, flags);
if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
bcom_gen_bd_rx_reset(s->bcom_task);
else
bcom_gen_bd_tx_reset(s->bcom_task);
for (i = 0; i < runtime->periods; i++)
if (!bcom_queue_full(s->bcom_task))
psc_dma_bcom_enqueue_next_buffer(s);
bcom_enable(s->bcom_task);
spin_unlock_irqrestore(&psc_dma->lock, flags);
out_8(®s->command, MPC52xx_PSC_RST_ERR_STAT);
break;
case SNDRV_PCM_TRIGGER_STOP:
dev_dbg(psc_dma->dev, "STOP: stream=%i periods_count=%i\n",
substream->pstr->stream, s->period_count);
s->active = 0;
spin_lock_irqsave(&psc_dma->lock, flags);
bcom_disable(s->bcom_task);
if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
bcom_gen_bd_rx_reset(s->bcom_task);
else
bcom_gen_bd_tx_reset(s->bcom_task);
spin_unlock_irqrestore(&psc_dma->lock, flags);
break;
default:
dev_dbg(psc_dma->dev, "unhandled trigger: stream=%i cmd=%i\n",
substream->pstr->stream, cmd);
return -EINVAL;
}
/* Update interrupt enable settings */
imr = 0;
if (psc_dma->playback.active)
imr |= MPC52xx_PSC_IMR_TXEMP;
if (psc_dma->capture.active)
imr |= MPC52xx_PSC_IMR_ORERR;
out_be16(®s->isr_imr.imr, psc_dma->imr | imr);
return 0;
}
/* ---------------------------------------------------------------------
* The PSC DMA 'ASoC platform' driver
*
* Can be referenced by an 'ASoC machine' driver
* This driver only deals with the audio bus; it doesn't have any
* interaction with the attached codec
*/
static const struct snd_pcm_hardware psc_dma_hardware = {
.info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID |
SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER |
SNDRV_PCM_INFO_BATCH,
.formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE |
SNDRV_PCM_FMTBIT_S24_BE | SNDRV_PCM_FMTBIT_S32_BE,
.period_bytes_max = 1024 * 1024,
.period_bytes_min = 32,
.periods_min = 2,
.periods_max = 256,
.buffer_bytes_max = 2 * 1024 * 1024,
.fifo_size = 512,
};
static int psc_dma_open(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
struct psc_dma_stream *s;
int rc;
dev_dbg(psc_dma->dev, "psc_dma_open(substream=%p)\n", substream);
if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
s = &psc_dma->capture;
else
s = &psc_dma->playback;
snd_soc_set_runtime_hwparams(substream, &psc_dma_hardware);
rc = snd_pcm_hw_constraint_integer(runtime,
SNDRV_PCM_HW_PARAM_PERIODS);
if (rc < 0) {
dev_err(substream->pcm->card->dev, "invalid buffer size\n");
return rc;
}
s->stream = substream;
return 0;
}
static int psc_dma_close(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
struct psc_dma_stream *s;
dev_dbg(psc_dma->dev, "psc_dma_close(substream=%p)\n", substream);
if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
s = &psc_dma->capture;
else
s = &psc_dma->playback;
if (!psc_dma->playback.active &&
!psc_dma->capture.active) {
/* Disable all interrupts and reset the PSC */
out_be16(&psc_dma->psc_regs->isr_imr.imr, psc_dma->imr);
out_8(&psc_dma->psc_regs->command, 4 << 4); /* reset error */
}
s->stream = NULL;
return 0;
}
static snd_pcm_uframes_t
psc_dma_pointer(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
struct psc_dma_stream *s;
dma_addr_t count;
if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
s = &psc_dma->capture;
else
s = &psc_dma->playback;
count = s->period_current * s->period_bytes;
return bytes_to_frames(substream->runtime, count);
}
static int psc_dma_new(struct snd_soc_component *component,
struct snd_soc_pcm_runtime *rtd)
{
struct snd_card *card = rtd->card->snd_card;
struct snd_soc_dai *dai = asoc_rtd_to_cpu(rtd, 0);
struct snd_pcm *pcm = rtd->pcm;
size_t size = psc_dma_hardware.buffer_bytes_max;
int rc;
dev_dbg(component->dev, "psc_dma_new(card=%p, dai=%p, pcm=%p)\n",
card, dai, pcm);
rc = dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(32));
if (rc)
return rc;
return snd_pcm_set_fixed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, card->dev,
size);
}
static const struct snd_soc_component_driver mpc5200_audio_dma_component = {
.name = DRV_NAME,
.open = psc_dma_open,
.close = psc_dma_close,
.pointer = psc_dma_pointer,
.trigger = psc_dma_trigger,
.pcm_construct = psc_dma_new,
};
int mpc5200_audio_dma_create(struct platform_device *op)
{
phys_addr_t fifo;
struct psc_dma *psc_dma;
struct resource res;
int size, irq, rc;
const __be32 *prop;
void __iomem *regs;
int ret;
/* Fetch the registers and IRQ of the PSC */
irq = irq_of_parse_and_map(op->dev.of_node, 0);
if (of_address_to_resource(op->dev.of_node, 0, &res)) {
dev_err(&op->dev, "Missing reg property\n");
return -ENODEV;
}
regs = ioremap(res.start, resource_size(&res));
if (!regs) {
dev_err(&op->dev, "Could not map registers\n");
return -ENODEV;
}
/* Allocate and initialize the driver private data */
psc_dma = kzalloc(sizeof *psc_dma, GFP_KERNEL);
if (!psc_dma) {
ret = -ENOMEM;
goto out_unmap;
}
/* Get the PSC ID */
prop = of_get_property(op->dev.of_node, "cell-index", &size);
if (!prop || size < sizeof *prop) {
ret = -ENODEV;
goto out_free;
}
spin_lock_init(&psc_dma->lock);
mutex_init(&psc_dma->mutex);
psc_dma->id = be32_to_cpu(*prop);
psc_dma->irq = irq;
psc_dma->psc_regs = regs;
psc_dma->fifo_regs = regs + sizeof *psc_dma->psc_regs;
psc_dma->dev = &op->dev;
psc_dma->playback.psc_dma = psc_dma;
psc_dma->capture.psc_dma = psc_dma;
snprintf(psc_dma->name, sizeof(psc_dma->name), "PSC%d", psc_dma->id);
/* Find the address of the fifo data registers and setup the
* DMA tasks */
fifo = res.start + offsetof(struct mpc52xx_psc, buffer.buffer_32);
psc_dma->capture.bcom_task =
bcom_psc_gen_bd_rx_init(psc_dma->id, 10, fifo, 512);
psc_dma->playback.bcom_task =
bcom_psc_gen_bd_tx_init(psc_dma->id, 10, fifo);
if (!psc_dma->capture.bcom_task ||
!psc_dma->playback.bcom_task) {
dev_err(&op->dev, "Could not allocate bestcomm tasks\n");
ret = -ENODEV;
goto out_free;
}
/* Disable all interrupts and reset the PSC */
out_be16(&psc_dma->psc_regs->isr_imr.imr, psc_dma->imr);
/* reset receiver */
out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_RST_RX);
/* reset transmitter */
out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_RST_TX);
/* reset error */
out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_RST_ERR_STAT);
/* reset mode */
out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_SEL_MODE_REG_1);
/* Set up mode register;
* First write: RxRdy (FIFO Alarm) generates rx FIFO irq
* Second write: register Normal mode for non loopback
*/
out_8(&psc_dma->psc_regs->mode, 0);
out_8(&psc_dma->psc_regs->mode, 0);
/* Set the TX and RX fifo alarm thresholds */
out_be16(&psc_dma->fifo_regs->rfalarm, 0x100);
out_8(&psc_dma->fifo_regs->rfcntl, 0x4);
out_be16(&psc_dma->fifo_regs->tfalarm, 0x100);
out_8(&psc_dma->fifo_regs->tfcntl, 0x7);
/* Lookup the IRQ numbers */
psc_dma->playback.irq =
bcom_get_task_irq(psc_dma->playback.bcom_task);
psc_dma->capture.irq =
bcom_get_task_irq(psc_dma->capture.bcom_task);
rc = request_irq(psc_dma->irq, &psc_dma_status_irq, IRQF_SHARED,
"psc-dma-status", psc_dma);
rc |= request_irq(psc_dma->capture.irq, &psc_dma_bcom_irq, IRQF_SHARED,
"psc-dma-capture", &psc_dma->capture);
rc |= request_irq(psc_dma->playback.irq, &psc_dma_bcom_irq, IRQF_SHARED,
"psc-dma-playback", &psc_dma->playback);
if (rc) {
ret = -ENODEV;
goto out_irq;
}
/* Save what we've done so it can be found again later */
dev_set_drvdata(&op->dev, psc_dma);
/* Tell the ASoC OF helpers about it */
return devm_snd_soc_register_component(&op->dev,
&mpc5200_audio_dma_component, NULL, 0);
out_irq:
free_irq(psc_dma->irq, psc_dma);
free_irq(psc_dma->capture.irq, &psc_dma->capture);
free_irq(psc_dma->playback.irq, &psc_dma->playback);
out_free:
kfree(psc_dma);
out_unmap:
iounmap(regs);
return ret;
}
EXPORT_SYMBOL_GPL(mpc5200_audio_dma_create);
int mpc5200_audio_dma_destroy(struct platform_device *op)
{
struct psc_dma *psc_dma = dev_get_drvdata(&op->dev);
dev_dbg(&op->dev, "mpc5200_audio_dma_destroy()\n");
bcom_gen_bd_rx_release(psc_dma->capture.bcom_task);
bcom_gen_bd_tx_release(psc_dma->playback.bcom_task);
/* Release irqs */
free_irq(psc_dma->irq, psc_dma);
free_irq(psc_dma->capture.irq, &psc_dma->capture);
free_irq(psc_dma->playback.irq, &psc_dma->playback);
iounmap(psc_dma->psc_regs);
kfree(psc_dma);
dev_set_drvdata(&op->dev, NULL);
return 0;
}
EXPORT_SYMBOL_GPL(mpc5200_audio_dma_destroy);
MODULE_AUTHOR("Grant Likely <[email protected]>");
MODULE_DESCRIPTION("Freescale MPC5200 PSC in DMA mode ASoC Driver");
MODULE_LICENSE("GPL");
| linux-master | sound/soc/fsl/mpc5200_dma.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2017 NXP
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* https://www.opensource.org/licenses/gpl-license.html
* https://www.gnu.org/copyleft/gpl.html
*/
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/clk.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include "fsl_sai.h"
#include "fsl_audmix.h"
struct imx_audmix {
struct platform_device *pdev;
struct snd_soc_card card;
struct platform_device *audmix_pdev;
struct platform_device *out_pdev;
struct clk *cpu_mclk;
int num_dai;
struct snd_soc_dai_link *dai;
int num_dai_conf;
struct snd_soc_codec_conf *dai_conf;
int num_dapm_routes;
struct snd_soc_dapm_route *dapm_routes;
};
static const u32 imx_audmix_rates[] = {
8000, 12000, 16000, 24000, 32000, 48000, 64000, 96000,
};
static const struct snd_pcm_hw_constraint_list imx_audmix_rate_constraints = {
.count = ARRAY_SIZE(imx_audmix_rates),
.list = imx_audmix_rates,
};
static int imx_audmix_fe_startup(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct imx_audmix *priv = snd_soc_card_get_drvdata(rtd->card);
struct snd_pcm_runtime *runtime = substream->runtime;
struct device *dev = rtd->card->dev;
unsigned long clk_rate = clk_get_rate(priv->cpu_mclk);
int ret;
if (clk_rate % 24576000 == 0) {
ret = snd_pcm_hw_constraint_list(runtime, 0,
SNDRV_PCM_HW_PARAM_RATE,
&imx_audmix_rate_constraints);
if (ret < 0)
return ret;
} else {
dev_warn(dev, "mclk may be not supported %lu\n", clk_rate);
}
ret = snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_CHANNELS,
1, 8);
if (ret < 0)
return ret;
return snd_pcm_hw_constraint_mask64(runtime, SNDRV_PCM_HW_PARAM_FORMAT,
FSL_AUDMIX_FORMATS);
}
static int imx_audmix_fe_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct device *dev = rtd->card->dev;
bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
unsigned int fmt = SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_NB_NF;
u32 channels = params_channels(params);
int ret, dir;
/* For playback the AUDMIX is consumer, and for record is provider */
fmt |= tx ? SND_SOC_DAIFMT_BP_FP : SND_SOC_DAIFMT_BC_FC;
dir = tx ? SND_SOC_CLOCK_OUT : SND_SOC_CLOCK_IN;
/* set DAI configuration */
ret = snd_soc_dai_set_fmt(asoc_rtd_to_cpu(rtd, 0), fmt);
if (ret) {
dev_err(dev, "failed to set cpu dai fmt: %d\n", ret);
return ret;
}
ret = snd_soc_dai_set_sysclk(asoc_rtd_to_cpu(rtd, 0), FSL_SAI_CLK_MAST1, 0, dir);
if (ret) {
dev_err(dev, "failed to set cpu sysclk: %d\n", ret);
return ret;
}
/*
* Per datasheet, AUDMIX expects 8 slots and 32 bits
* for every slot in TDM mode.
*/
ret = snd_soc_dai_set_tdm_slot(asoc_rtd_to_cpu(rtd, 0), BIT(channels) - 1,
BIT(channels) - 1, 8, 32);
if (ret)
dev_err(dev, "failed to set cpu dai tdm slot: %d\n", ret);
return ret;
}
static int imx_audmix_be_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct device *dev = rtd->card->dev;
bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
unsigned int fmt = SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_NB_NF;
int ret;
if (!tx)
return 0;
/* For playback the AUDMIX is consumer */
fmt |= SND_SOC_DAIFMT_BC_FC;
/* set AUDMIX DAI configuration */
ret = snd_soc_dai_set_fmt(asoc_rtd_to_cpu(rtd, 0), fmt);
if (ret)
dev_err(dev, "failed to set AUDMIX DAI fmt: %d\n", ret);
return ret;
}
static const struct snd_soc_ops imx_audmix_fe_ops = {
.startup = imx_audmix_fe_startup,
.hw_params = imx_audmix_fe_hw_params,
};
static const struct snd_soc_ops imx_audmix_be_ops = {
.hw_params = imx_audmix_be_hw_params,
};
static int imx_audmix_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct device_node *audmix_np = NULL, *out_cpu_np = NULL;
struct platform_device *audmix_pdev = NULL;
struct platform_device *cpu_pdev;
struct of_phandle_args args;
struct imx_audmix *priv;
int i, num_dai, ret;
const char *fe_name_pref = "HiFi-AUDMIX-FE-";
char *be_name, *be_pb, *be_cp, *dai_name, *capture_dai_name;
if (pdev->dev.parent) {
audmix_np = pdev->dev.parent->of_node;
} else {
dev_err(&pdev->dev, "Missing parent device.\n");
return -EINVAL;
}
if (!audmix_np) {
dev_err(&pdev->dev, "Missing DT node for parent device.\n");
return -EINVAL;
}
audmix_pdev = of_find_device_by_node(audmix_np);
if (!audmix_pdev) {
dev_err(&pdev->dev, "Missing AUDMIX platform device for %s\n",
np->full_name);
return -EINVAL;
}
put_device(&audmix_pdev->dev);
num_dai = of_count_phandle_with_args(audmix_np, "dais", NULL);
if (num_dai != FSL_AUDMIX_MAX_DAIS) {
dev_err(&pdev->dev, "Need 2 dais to be provided for %s\n",
audmix_np->full_name);
return -EINVAL;
}
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->num_dai = 2 * num_dai;
priv->dai = devm_kcalloc(&pdev->dev, priv->num_dai,
sizeof(struct snd_soc_dai_link), GFP_KERNEL);
if (!priv->dai)
return -ENOMEM;
priv->num_dai_conf = num_dai;
priv->dai_conf = devm_kcalloc(&pdev->dev, priv->num_dai_conf,
sizeof(struct snd_soc_codec_conf),
GFP_KERNEL);
if (!priv->dai_conf)
return -ENOMEM;
priv->num_dapm_routes = 3 * num_dai;
priv->dapm_routes = devm_kcalloc(&pdev->dev, priv->num_dapm_routes,
sizeof(struct snd_soc_dapm_route),
GFP_KERNEL);
if (!priv->dapm_routes)
return -ENOMEM;
for (i = 0; i < num_dai; i++) {
struct snd_soc_dai_link_component *dlc;
/* for CPU x 2 */
dlc = devm_kcalloc(&pdev->dev, 2, sizeof(*dlc), GFP_KERNEL);
if (!dlc)
return -ENOMEM;
ret = of_parse_phandle_with_args(audmix_np, "dais", NULL, i,
&args);
if (ret < 0) {
dev_err(&pdev->dev, "of_parse_phandle_with_args failed\n");
return ret;
}
cpu_pdev = of_find_device_by_node(args.np);
if (!cpu_pdev) {
dev_err(&pdev->dev, "failed to find SAI platform device\n");
return -EINVAL;
}
put_device(&cpu_pdev->dev);
dai_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s%s",
fe_name_pref, args.np->full_name + 1);
if (!dai_name)
return -ENOMEM;
dev_info(pdev->dev.parent, "DAI FE name:%s\n", dai_name);
if (i == 0) {
out_cpu_np = args.np;
capture_dai_name =
devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s %s",
dai_name, "CPU-Capture");
if (!capture_dai_name)
return -ENOMEM;
}
/*
* CPU == Platform
* platform is using soc-generic-dmaengine-pcm
*/
priv->dai[i].cpus =
priv->dai[i].platforms = &dlc[0];
priv->dai[i].codecs = &asoc_dummy_dlc;
priv->dai[i].num_cpus = 1;
priv->dai[i].num_codecs = 1;
priv->dai[i].num_platforms = 1;
priv->dai[i].name = dai_name;
priv->dai[i].stream_name = "HiFi-AUDMIX-FE";
priv->dai[i].cpus->of_node = args.np;
priv->dai[i].cpus->dai_name = dev_name(&cpu_pdev->dev);
priv->dai[i].dynamic = 1;
priv->dai[i].dpcm_playback = 1;
priv->dai[i].dpcm_capture = (i == 0 ? 1 : 0);
priv->dai[i].ignore_pmdown_time = 1;
priv->dai[i].ops = &imx_audmix_fe_ops;
/* Add AUDMIX Backend */
be_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
"audmix-%d", i);
be_pb = devm_kasprintf(&pdev->dev, GFP_KERNEL,
"AUDMIX-Playback-%d", i);
be_cp = devm_kasprintf(&pdev->dev, GFP_KERNEL,
"AUDMIX-Capture-%d", i);
if (!be_name || !be_pb || !be_cp)
return -ENOMEM;
priv->dai[num_dai + i].cpus = &dlc[1];
priv->dai[num_dai + i].codecs = &asoc_dummy_dlc;
priv->dai[num_dai + i].num_cpus = 1;
priv->dai[num_dai + i].num_codecs = 1;
priv->dai[num_dai + i].name = be_name;
priv->dai[num_dai + i].cpus->of_node = audmix_np;
priv->dai[num_dai + i].cpus->dai_name = be_name;
priv->dai[num_dai + i].no_pcm = 1;
priv->dai[num_dai + i].dpcm_playback = 1;
priv->dai[num_dai + i].dpcm_capture = 1;
priv->dai[num_dai + i].ignore_pmdown_time = 1;
priv->dai[num_dai + i].ops = &imx_audmix_be_ops;
priv->dai_conf[i].dlc.of_node = args.np;
priv->dai_conf[i].name_prefix = dai_name;
priv->dapm_routes[i].source =
devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s %s",
dai_name, "CPU-Playback");
if (!priv->dapm_routes[i].source)
return -ENOMEM;
priv->dapm_routes[i].sink = be_pb;
priv->dapm_routes[num_dai + i].source = be_pb;
priv->dapm_routes[num_dai + i].sink = be_cp;
priv->dapm_routes[2 * num_dai + i].source = be_cp;
priv->dapm_routes[2 * num_dai + i].sink = capture_dai_name;
}
cpu_pdev = of_find_device_by_node(out_cpu_np);
if (!cpu_pdev) {
dev_err(&pdev->dev, "failed to find SAI platform device\n");
return -EINVAL;
}
put_device(&cpu_pdev->dev);
priv->cpu_mclk = devm_clk_get(&cpu_pdev->dev, "mclk1");
if (IS_ERR(priv->cpu_mclk)) {
ret = PTR_ERR(priv->cpu_mclk);
dev_err(&cpu_pdev->dev, "failed to get DAI mclk1: %d\n", ret);
return ret;
}
priv->audmix_pdev = audmix_pdev;
priv->out_pdev = cpu_pdev;
priv->card.dai_link = priv->dai;
priv->card.num_links = priv->num_dai;
priv->card.codec_conf = priv->dai_conf;
priv->card.num_configs = priv->num_dai_conf;
priv->card.dapm_routes = priv->dapm_routes;
priv->card.num_dapm_routes = priv->num_dapm_routes;
priv->card.dev = &pdev->dev;
priv->card.owner = THIS_MODULE;
priv->card.name = "imx-audmix";
platform_set_drvdata(pdev, &priv->card);
snd_soc_card_set_drvdata(&priv->card, priv);
ret = devm_snd_soc_register_card(&pdev->dev, &priv->card);
if (ret) {
dev_err(&pdev->dev, "snd_soc_register_card failed\n");
return ret;
}
return ret;
}
static struct platform_driver imx_audmix_driver = {
.probe = imx_audmix_probe,
.driver = {
.name = "imx-audmix",
.pm = &snd_soc_pm_ops,
},
};
module_platform_driver(imx_audmix_driver);
MODULE_DESCRIPTION("NXP AUDMIX ASoC machine driver");
MODULE_AUTHOR("Viorel Suman <[email protected]>");
MODULE_ALIAS("platform:imx-audmix");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/fsl/imx-audmix.c |
// SPDX-License-Identifier: GPL-2.0
//
// ALSA SoC IMX MQS driver
//
// Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
// Copyright 2019 NXP
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
#include <linux/of_device.h>
#include <linux/pm_runtime.h>
#include <linux/of.h>
#include <linux/pm.h>
#include <linux/slab.h>
#include <sound/soc.h>
#include <sound/pcm.h>
#include <sound/initval.h>
#define REG_MQS_CTRL 0x00
#define MQS_EN_MASK (0x1 << 28)
#define MQS_EN_SHIFT (28)
#define MQS_SW_RST_MASK (0x1 << 24)
#define MQS_SW_RST_SHIFT (24)
#define MQS_OVERSAMPLE_MASK (0x1 << 20)
#define MQS_OVERSAMPLE_SHIFT (20)
#define MQS_CLK_DIV_MASK (0xFF << 0)
#define MQS_CLK_DIV_SHIFT (0)
/**
* struct fsl_mqs_soc_data - soc specific data
*
* @use_gpr: control register is in General Purpose Register group
* @ctrl_off: control register offset
* @en_mask: enable bit mask
* @en_shift: enable bit shift
* @rst_mask: reset bit mask
* @rst_shift: reset bit shift
* @osr_mask: oversample bit mask
* @osr_shift: oversample bit shift
* @div_mask: clock divider mask
* @div_shift: clock divider bit shift
*/
struct fsl_mqs_soc_data {
bool use_gpr;
int ctrl_off;
int en_mask;
int en_shift;
int rst_mask;
int rst_shift;
int osr_mask;
int osr_shift;
int div_mask;
int div_shift;
};
/* codec private data */
struct fsl_mqs {
struct regmap *regmap;
struct clk *mclk;
struct clk *ipg;
const struct fsl_mqs_soc_data *soc;
unsigned int reg_mqs_ctrl;
};
#define FSL_MQS_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
#define FSL_MQS_FORMATS SNDRV_PCM_FMTBIT_S16_LE
static int fsl_mqs_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct fsl_mqs *mqs_priv = snd_soc_component_get_drvdata(component);
unsigned long mclk_rate;
int div, res;
int lrclk;
mclk_rate = clk_get_rate(mqs_priv->mclk);
lrclk = params_rate(params);
/*
* mclk_rate / (oversample(32,64) * FS * 2 * divider ) = repeat_rate;
* if repeat_rate is 8, mqs can achieve better quality.
* oversample rate is fix to 32 currently.
*/
div = mclk_rate / (32 * lrclk * 2 * 8);
res = mclk_rate % (32 * lrclk * 2 * 8);
if (res == 0 && div > 0 && div <= 256) {
regmap_update_bits(mqs_priv->regmap, mqs_priv->soc->ctrl_off,
mqs_priv->soc->div_mask,
(div - 1) << mqs_priv->soc->div_shift);
regmap_update_bits(mqs_priv->regmap, mqs_priv->soc->ctrl_off,
mqs_priv->soc->osr_mask, 0);
} else {
dev_err(component->dev, "can't get proper divider\n");
}
return 0;
}
static int fsl_mqs_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
/* Only LEFT_J & SLAVE mode is supported. */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_LEFT_J:
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_CBC_CFC:
break;
default:
return -EINVAL;
}
return 0;
}
static int fsl_mqs_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct fsl_mqs *mqs_priv = snd_soc_component_get_drvdata(component);
regmap_update_bits(mqs_priv->regmap, mqs_priv->soc->ctrl_off,
mqs_priv->soc->en_mask,
1 << mqs_priv->soc->en_shift);
return 0;
}
static void fsl_mqs_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct fsl_mqs *mqs_priv = snd_soc_component_get_drvdata(component);
regmap_update_bits(mqs_priv->regmap, mqs_priv->soc->ctrl_off,
mqs_priv->soc->en_mask, 0);
}
static const struct snd_soc_component_driver soc_codec_fsl_mqs = {
.idle_bias_on = 1,
};
static const struct snd_soc_dai_ops fsl_mqs_dai_ops = {
.startup = fsl_mqs_startup,
.shutdown = fsl_mqs_shutdown,
.hw_params = fsl_mqs_hw_params,
.set_fmt = fsl_mqs_set_dai_fmt,
};
static struct snd_soc_dai_driver fsl_mqs_dai = {
.name = "fsl-mqs-dai",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = FSL_MQS_RATES,
.formats = FSL_MQS_FORMATS,
},
.ops = &fsl_mqs_dai_ops,
};
static const struct regmap_config fsl_mqs_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = REG_MQS_CTRL,
.cache_type = REGCACHE_NONE,
};
static int fsl_mqs_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct device_node *gpr_np = NULL;
struct fsl_mqs *mqs_priv;
void __iomem *regs;
int ret;
mqs_priv = devm_kzalloc(&pdev->dev, sizeof(*mqs_priv), GFP_KERNEL);
if (!mqs_priv)
return -ENOMEM;
/* On i.MX6sx the MQS control register is in GPR domain
* But in i.MX8QM/i.MX8QXP the control register is moved
* to its own domain.
*/
mqs_priv->soc = of_device_get_match_data(&pdev->dev);
if (mqs_priv->soc->use_gpr) {
gpr_np = of_parse_phandle(np, "gpr", 0);
if (!gpr_np) {
dev_err(&pdev->dev, "failed to get gpr node by phandle\n");
return -EINVAL;
}
mqs_priv->regmap = syscon_node_to_regmap(gpr_np);
of_node_put(gpr_np);
if (IS_ERR(mqs_priv->regmap)) {
dev_err(&pdev->dev, "failed to get gpr regmap\n");
return PTR_ERR(mqs_priv->regmap);
}
} else {
regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(regs))
return PTR_ERR(regs);
mqs_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
"core",
regs,
&fsl_mqs_regmap_config);
if (IS_ERR(mqs_priv->regmap)) {
dev_err(&pdev->dev, "failed to init regmap: %ld\n",
PTR_ERR(mqs_priv->regmap));
return PTR_ERR(mqs_priv->regmap);
}
mqs_priv->ipg = devm_clk_get(&pdev->dev, "core");
if (IS_ERR(mqs_priv->ipg)) {
dev_err(&pdev->dev, "failed to get the clock: %ld\n",
PTR_ERR(mqs_priv->ipg));
return PTR_ERR(mqs_priv->ipg);
}
}
mqs_priv->mclk = devm_clk_get(&pdev->dev, "mclk");
if (IS_ERR(mqs_priv->mclk)) {
dev_err(&pdev->dev, "failed to get the clock: %ld\n",
PTR_ERR(mqs_priv->mclk));
return PTR_ERR(mqs_priv->mclk);
}
dev_set_drvdata(&pdev->dev, mqs_priv);
pm_runtime_enable(&pdev->dev);
ret = devm_snd_soc_register_component(&pdev->dev, &soc_codec_fsl_mqs,
&fsl_mqs_dai, 1);
if (ret)
return ret;
return 0;
}
static void fsl_mqs_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
}
#ifdef CONFIG_PM
static int fsl_mqs_runtime_resume(struct device *dev)
{
struct fsl_mqs *mqs_priv = dev_get_drvdata(dev);
int ret;
ret = clk_prepare_enable(mqs_priv->ipg);
if (ret) {
dev_err(dev, "failed to enable ipg clock\n");
return ret;
}
ret = clk_prepare_enable(mqs_priv->mclk);
if (ret) {
dev_err(dev, "failed to enable mclk clock\n");
clk_disable_unprepare(mqs_priv->ipg);
return ret;
}
regmap_write(mqs_priv->regmap, mqs_priv->soc->ctrl_off, mqs_priv->reg_mqs_ctrl);
return 0;
}
static int fsl_mqs_runtime_suspend(struct device *dev)
{
struct fsl_mqs *mqs_priv = dev_get_drvdata(dev);
regmap_read(mqs_priv->regmap, mqs_priv->soc->ctrl_off, &mqs_priv->reg_mqs_ctrl);
clk_disable_unprepare(mqs_priv->mclk);
clk_disable_unprepare(mqs_priv->ipg);
return 0;
}
#endif
static const struct dev_pm_ops fsl_mqs_pm_ops = {
SET_RUNTIME_PM_OPS(fsl_mqs_runtime_suspend,
fsl_mqs_runtime_resume,
NULL)
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
};
static const struct fsl_mqs_soc_data fsl_mqs_imx8qm_data = {
.use_gpr = false,
.ctrl_off = REG_MQS_CTRL,
.en_mask = MQS_EN_MASK,
.en_shift = MQS_EN_SHIFT,
.rst_mask = MQS_SW_RST_MASK,
.rst_shift = MQS_SW_RST_SHIFT,
.osr_mask = MQS_OVERSAMPLE_MASK,
.osr_shift = MQS_OVERSAMPLE_SHIFT,
.div_mask = MQS_CLK_DIV_MASK,
.div_shift = MQS_CLK_DIV_SHIFT,
};
static const struct fsl_mqs_soc_data fsl_mqs_imx6sx_data = {
.use_gpr = true,
.ctrl_off = IOMUXC_GPR2,
.en_mask = IMX6SX_GPR2_MQS_EN_MASK,
.en_shift = IMX6SX_GPR2_MQS_EN_SHIFT,
.rst_mask = IMX6SX_GPR2_MQS_SW_RST_MASK,
.rst_shift = IMX6SX_GPR2_MQS_SW_RST_SHIFT,
.osr_mask = IMX6SX_GPR2_MQS_OVERSAMPLE_MASK,
.osr_shift = IMX6SX_GPR2_MQS_OVERSAMPLE_SHIFT,
.div_mask = IMX6SX_GPR2_MQS_CLK_DIV_MASK,
.div_shift = IMX6SX_GPR2_MQS_CLK_DIV_SHIFT,
};
static const struct fsl_mqs_soc_data fsl_mqs_imx93_data = {
.use_gpr = true,
.ctrl_off = 0x20,
.en_mask = BIT(1),
.en_shift = 1,
.rst_mask = BIT(2),
.rst_shift = 2,
.osr_mask = BIT(3),
.osr_shift = 3,
.div_mask = GENMASK(15, 8),
.div_shift = 8,
};
static const struct of_device_id fsl_mqs_dt_ids[] = {
{ .compatible = "fsl,imx8qm-mqs", .data = &fsl_mqs_imx8qm_data },
{ .compatible = "fsl,imx6sx-mqs", .data = &fsl_mqs_imx6sx_data },
{ .compatible = "fsl,imx93-mqs", .data = &fsl_mqs_imx93_data },
{}
};
MODULE_DEVICE_TABLE(of, fsl_mqs_dt_ids);
static struct platform_driver fsl_mqs_driver = {
.probe = fsl_mqs_probe,
.remove_new = fsl_mqs_remove,
.driver = {
.name = "fsl-mqs",
.of_match_table = fsl_mqs_dt_ids,
.pm = &fsl_mqs_pm_ops,
},
};
module_platform_driver(fsl_mqs_driver);
MODULE_AUTHOR("Shengjiu Wang <[email protected]>");
MODULE_DESCRIPTION("MQS codec driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:fsl-mqs");
| linux-master | sound/soc/fsl/fsl_mqs.c |
// SPDX-License-Identifier: GPL-2.0
//
// Freescale ESAI ALSA SoC Digital Audio Interface (DAI) driver
//
// Copyright (C) 2014 Freescale Semiconductor, Inc.
#include <linux/clk.h>
#include <linux/dmaengine.h>
#include <linux/module.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/pm_runtime.h>
#include <sound/dmaengine_pcm.h>
#include <sound/pcm_params.h>
#include "fsl_esai.h"
#include "imx-pcm.h"
#define FSL_ESAI_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE)
/**
* struct fsl_esai_soc_data - soc specific data
* @reset_at_xrun: flags for enable reset operaton
*/
struct fsl_esai_soc_data {
bool reset_at_xrun;
};
/**
* struct fsl_esai - ESAI private data
* @dma_params_rx: DMA parameters for receive channel
* @dma_params_tx: DMA parameters for transmit channel
* @pdev: platform device pointer
* @regmap: regmap handler
* @coreclk: clock source to access register
* @extalclk: esai clock source to derive HCK, SCK and FS
* @fsysclk: system clock source to derive HCK, SCK and FS
* @spbaclk: SPBA clock (optional, depending on SoC design)
* @work: work to handle the reset operation
* @soc: soc specific data
* @lock: spin lock between hw_reset() and trigger()
* @fifo_depth: depth of tx/rx FIFO
* @slot_width: width of each DAI slot
* @slots: number of slots
* @tx_mask: slot mask for TX
* @rx_mask: slot mask for RX
* @channels: channel num for tx or rx
* @hck_rate: clock rate of desired HCKx clock
* @sck_rate: clock rate of desired SCKx clock
* @hck_dir: the direction of HCKx pads
* @sck_div: if using PSR/PM dividers for SCKx clock
* @consumer_mode: if fully using DAI clock consumer mode
* @synchronous: if using tx/rx synchronous mode
* @name: driver name
*/
struct fsl_esai {
struct snd_dmaengine_dai_dma_data dma_params_rx;
struct snd_dmaengine_dai_dma_data dma_params_tx;
struct platform_device *pdev;
struct regmap *regmap;
struct clk *coreclk;
struct clk *extalclk;
struct clk *fsysclk;
struct clk *spbaclk;
struct work_struct work;
const struct fsl_esai_soc_data *soc;
spinlock_t lock; /* Protect hw_reset and trigger */
u32 fifo_depth;
u32 slot_width;
u32 slots;
u32 tx_mask;
u32 rx_mask;
u32 channels[2];
u32 hck_rate[2];
u32 sck_rate[2];
bool hck_dir[2];
bool sck_div[2];
bool consumer_mode;
bool synchronous;
char name[32];
};
static struct fsl_esai_soc_data fsl_esai_vf610 = {
.reset_at_xrun = true,
};
static struct fsl_esai_soc_data fsl_esai_imx35 = {
.reset_at_xrun = true,
};
static struct fsl_esai_soc_data fsl_esai_imx6ull = {
.reset_at_xrun = false,
};
static irqreturn_t esai_isr(int irq, void *devid)
{
struct fsl_esai *esai_priv = (struct fsl_esai *)devid;
struct platform_device *pdev = esai_priv->pdev;
u32 esr;
u32 saisr;
regmap_read(esai_priv->regmap, REG_ESAI_ESR, &esr);
regmap_read(esai_priv->regmap, REG_ESAI_SAISR, &saisr);
if ((saisr & (ESAI_SAISR_TUE | ESAI_SAISR_ROE)) &&
esai_priv->soc->reset_at_xrun) {
dev_dbg(&pdev->dev, "reset module for xrun\n");
regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR,
ESAI_xCR_xEIE_MASK, 0);
regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR,
ESAI_xCR_xEIE_MASK, 0);
schedule_work(&esai_priv->work);
}
if (esr & ESAI_ESR_TINIT_MASK)
dev_dbg(&pdev->dev, "isr: Transmission Initialized\n");
if (esr & ESAI_ESR_RFF_MASK)
dev_warn(&pdev->dev, "isr: Receiving overrun\n");
if (esr & ESAI_ESR_TFE_MASK)
dev_warn(&pdev->dev, "isr: Transmission underrun\n");
if (esr & ESAI_ESR_TLS_MASK)
dev_dbg(&pdev->dev, "isr: Just transmitted the last slot\n");
if (esr & ESAI_ESR_TDE_MASK)
dev_dbg(&pdev->dev, "isr: Transmission data exception\n");
if (esr & ESAI_ESR_TED_MASK)
dev_dbg(&pdev->dev, "isr: Transmitting even slots\n");
if (esr & ESAI_ESR_TD_MASK)
dev_dbg(&pdev->dev, "isr: Transmitting data\n");
if (esr & ESAI_ESR_RLS_MASK)
dev_dbg(&pdev->dev, "isr: Just received the last slot\n");
if (esr & ESAI_ESR_RDE_MASK)
dev_dbg(&pdev->dev, "isr: Receiving data exception\n");
if (esr & ESAI_ESR_RED_MASK)
dev_dbg(&pdev->dev, "isr: Receiving even slots\n");
if (esr & ESAI_ESR_RD_MASK)
dev_dbg(&pdev->dev, "isr: Receiving data\n");
return IRQ_HANDLED;
}
/**
* fsl_esai_divisor_cal - This function is used to calculate the
* divisors of psr, pm, fp and it is supposed to be called in
* set_dai_sysclk() and set_bclk().
*
* @dai: pointer to DAI
* @tx: current setting is for playback or capture
* @ratio: desired overall ratio for the paticipating dividers
* @usefp: for HCK setting, there is no need to set fp divider
* @fp: bypass other dividers by setting fp directly if fp != 0
*/
static int fsl_esai_divisor_cal(struct snd_soc_dai *dai, bool tx, u32 ratio,
bool usefp, u32 fp)
{
struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
u32 psr, pm = 999, maxfp, prod, sub, savesub, i, j;
maxfp = usefp ? 16 : 1;
if (usefp && fp)
goto out_fp;
if (ratio > 2 * 8 * 256 * maxfp || ratio < 2) {
dev_err(dai->dev, "the ratio is out of range (2 ~ %d)\n",
2 * 8 * 256 * maxfp);
return -EINVAL;
} else if (ratio % 2) {
dev_err(dai->dev, "the raio must be even if using upper divider\n");
return -EINVAL;
}
ratio /= 2;
psr = ratio <= 256 * maxfp ? ESAI_xCCR_xPSR_BYPASS : ESAI_xCCR_xPSR_DIV8;
/* Do not loop-search if PM (1 ~ 256) alone can serve the ratio */
if (ratio <= 256) {
pm = ratio;
fp = 1;
goto out;
}
/* Set the max fluctuation -- 0.1% of the max devisor */
savesub = (psr ? 1 : 8) * 256 * maxfp / 1000;
/* Find the best value for PM */
for (i = 1; i <= 256; i++) {
for (j = 1; j <= maxfp; j++) {
/* PSR (1 or 8) * PM (1 ~ 256) * FP (1 ~ 16) */
prod = (psr ? 1 : 8) * i * j;
if (prod == ratio)
sub = 0;
else if (prod / ratio == 1)
sub = prod - ratio;
else if (ratio / prod == 1)
sub = ratio - prod;
else
continue;
/* Calculate the fraction */
sub = sub * 1000 / ratio;
if (sub < savesub) {
savesub = sub;
pm = i;
fp = j;
}
/* We are lucky */
if (savesub == 0)
goto out;
}
}
if (pm == 999) {
dev_err(dai->dev, "failed to calculate proper divisors\n");
return -EINVAL;
}
out:
regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
ESAI_xCCR_xPSR_MASK | ESAI_xCCR_xPM_MASK,
psr | ESAI_xCCR_xPM(pm));
out_fp:
/* Bypass fp if not being required */
if (maxfp <= 1)
return 0;
regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
ESAI_xCCR_xFP_MASK, ESAI_xCCR_xFP(fp));
return 0;
}
/**
* fsl_esai_set_dai_sysclk - configure the clock frequency of MCLK (HCKT/HCKR)
* @dai: pointer to DAI
* @clk_id: The clock source of HCKT/HCKR
* (Input from outside; output from inside, FSYS or EXTAL)
* @freq: The required clock rate of HCKT/HCKR
* @dir: The clock direction of HCKT/HCKR
*
* Note: If the direction is input, we do not care about clk_id.
*/
static int fsl_esai_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
unsigned int freq, int dir)
{
struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
struct clk *clksrc = esai_priv->extalclk;
bool tx = (clk_id <= ESAI_HCKT_EXTAL || esai_priv->synchronous);
bool in = dir == SND_SOC_CLOCK_IN;
u32 ratio, ecr = 0;
unsigned long clk_rate;
int ret;
if (freq == 0) {
dev_err(dai->dev, "%sput freq of HCK%c should not be 0Hz\n",
in ? "in" : "out", tx ? 'T' : 'R');
return -EINVAL;
}
/* Bypass divider settings if the requirement doesn't change */
if (freq == esai_priv->hck_rate[tx] && dir == esai_priv->hck_dir[tx])
return 0;
/* sck_div can be only bypassed if ETO/ERO=0 and SNC_SOC_CLOCK_OUT */
esai_priv->sck_div[tx] = true;
/* Set the direction of HCKT/HCKR pins */
regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
ESAI_xCCR_xHCKD, in ? 0 : ESAI_xCCR_xHCKD);
if (in)
goto out;
switch (clk_id) {
case ESAI_HCKT_FSYS:
case ESAI_HCKR_FSYS:
clksrc = esai_priv->fsysclk;
break;
case ESAI_HCKT_EXTAL:
ecr |= ESAI_ECR_ETI;
break;
case ESAI_HCKR_EXTAL:
ecr |= esai_priv->synchronous ? ESAI_ECR_ETI : ESAI_ECR_ERI;
break;
default:
return -EINVAL;
}
if (IS_ERR(clksrc)) {
dev_err(dai->dev, "no assigned %s clock\n",
(clk_id % 2) ? "extal" : "fsys");
return PTR_ERR(clksrc);
}
clk_rate = clk_get_rate(clksrc);
ratio = clk_rate / freq;
if (ratio * freq > clk_rate)
ret = ratio * freq - clk_rate;
else if (ratio * freq < clk_rate)
ret = clk_rate - ratio * freq;
else
ret = 0;
/* Block if clock source can not be divided into the required rate */
if (ret != 0 && clk_rate / ret < 1000) {
dev_err(dai->dev, "failed to derive required HCK%c rate\n",
tx ? 'T' : 'R');
return -EINVAL;
}
/* Only EXTAL source can be output directly without using PSR and PM */
if (ratio == 1 && clksrc == esai_priv->extalclk) {
/* Bypass all the dividers if not being needed */
ecr |= tx ? ESAI_ECR_ETO : ESAI_ECR_ERO;
goto out;
} else if (ratio < 2) {
/* The ratio should be no less than 2 if using other sources */
dev_err(dai->dev, "failed to derive required HCK%c rate\n",
tx ? 'T' : 'R');
return -EINVAL;
}
ret = fsl_esai_divisor_cal(dai, tx, ratio, false, 0);
if (ret)
return ret;
esai_priv->sck_div[tx] = false;
out:
esai_priv->hck_dir[tx] = dir;
esai_priv->hck_rate[tx] = freq;
regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR,
tx ? ESAI_ECR_ETI | ESAI_ECR_ETO :
ESAI_ECR_ERI | ESAI_ECR_ERO, ecr);
return 0;
}
/**
* fsl_esai_set_bclk - configure the related dividers according to the bclk rate
* @dai: pointer to DAI
* @tx: direction boolean
* @freq: bclk freq
*/
static int fsl_esai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
{
struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
u32 hck_rate = esai_priv->hck_rate[tx];
u32 sub, ratio = hck_rate / freq;
int ret;
/* Don't apply for fully consumer mode or unchanged bclk */
if (esai_priv->consumer_mode || esai_priv->sck_rate[tx] == freq)
return 0;
if (ratio * freq > hck_rate)
sub = ratio * freq - hck_rate;
else if (ratio * freq < hck_rate)
sub = hck_rate - ratio * freq;
else
sub = 0;
/* Block if clock source can not be divided into the required rate */
if (sub != 0 && hck_rate / sub < 1000) {
dev_err(dai->dev, "failed to derive required SCK%c rate\n",
tx ? 'T' : 'R');
return -EINVAL;
}
/* The ratio should be contented by FP alone if bypassing PM and PSR */
if (!esai_priv->sck_div[tx] && (ratio > 16 || ratio == 0)) {
dev_err(dai->dev, "the ratio is out of range (1 ~ 16)\n");
return -EINVAL;
}
ret = fsl_esai_divisor_cal(dai, tx, ratio, true,
esai_priv->sck_div[tx] ? 0 : ratio);
if (ret)
return ret;
/* Save current bclk rate */
esai_priv->sck_rate[tx] = freq;
return 0;
}
static int fsl_esai_set_dai_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask,
u32 rx_mask, int slots, int slot_width)
{
struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR,
ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots));
regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR,
ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots));
esai_priv->slot_width = slot_width;
esai_priv->slots = slots;
esai_priv->tx_mask = tx_mask;
esai_priv->rx_mask = rx_mask;
return 0;
}
static int fsl_esai_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
u32 xcr = 0, xccr = 0, mask;
/* DAI mode */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
/* Data on rising edge of bclk, frame low, 1clk before data */
xcr |= ESAI_xCR_xFSR;
xccr |= ESAI_xCCR_xFSP | ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
break;
case SND_SOC_DAIFMT_LEFT_J:
/* Data on rising edge of bclk, frame high */
xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
break;
case SND_SOC_DAIFMT_RIGHT_J:
/* Data on rising edge of bclk, frame high, right aligned */
xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
xcr |= ESAI_xCR_xWA;
break;
case SND_SOC_DAIFMT_DSP_A:
/* Data on rising edge of bclk, frame high, 1clk before data */
xcr |= ESAI_xCR_xFSL | ESAI_xCR_xFSR;
xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
break;
case SND_SOC_DAIFMT_DSP_B:
/* Data on rising edge of bclk, frame high */
xcr |= ESAI_xCR_xFSL;
xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
break;
default:
return -EINVAL;
}
/* DAI clock inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
/* Nothing to do for both normal cases */
break;
case SND_SOC_DAIFMT_IB_NF:
/* Invert bit clock */
xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
break;
case SND_SOC_DAIFMT_NB_IF:
/* Invert frame clock */
xccr ^= ESAI_xCCR_xFSP;
break;
case SND_SOC_DAIFMT_IB_IF:
/* Invert both clocks */
xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP;
break;
default:
return -EINVAL;
}
esai_priv->consumer_mode = false;
/* DAI clock provider masks */
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BC_FC:
esai_priv->consumer_mode = true;
break;
case SND_SOC_DAIFMT_BP_FC:
xccr |= ESAI_xCCR_xCKD;
break;
case SND_SOC_DAIFMT_BC_FP:
xccr |= ESAI_xCCR_xFSD;
break;
case SND_SOC_DAIFMT_BP_FP:
xccr |= ESAI_xCCR_xFSD | ESAI_xCCR_xCKD;
break;
default:
return -EINVAL;
}
mask = ESAI_xCR_xFSL | ESAI_xCR_xFSR | ESAI_xCR_xWA;
regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, mask, xcr);
regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR, mask, xcr);
mask = ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP |
ESAI_xCCR_xFSD | ESAI_xCCR_xCKD;
regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR, mask, xccr);
regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR, mask, xccr);
return 0;
}
static int fsl_esai_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
if (!snd_soc_dai_active(dai)) {
/* Set synchronous mode */
regmap_update_bits(esai_priv->regmap, REG_ESAI_SAICR,
ESAI_SAICR_SYNC, esai_priv->synchronous ?
ESAI_SAICR_SYNC : 0);
/* Set slots count */
regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR,
ESAI_xCCR_xDC_MASK,
ESAI_xCCR_xDC(esai_priv->slots));
regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR,
ESAI_xCCR_xDC_MASK,
ESAI_xCCR_xDC(esai_priv->slots));
}
return 0;
}
static int fsl_esai_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
u32 width = params_width(params);
u32 channels = params_channels(params);
u32 pins = DIV_ROUND_UP(channels, esai_priv->slots);
u32 slot_width = width;
u32 bclk, mask, val;
int ret;
/* Override slot_width if being specifically set */
if (esai_priv->slot_width)
slot_width = esai_priv->slot_width;
bclk = params_rate(params) * slot_width * esai_priv->slots;
ret = fsl_esai_set_bclk(dai, esai_priv->synchronous || tx, bclk);
if (ret)
return ret;
mask = ESAI_xCR_xSWS_MASK;
val = ESAI_xCR_xSWS(slot_width, width);
regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), mask, val);
/* Recording in synchronous mode needs to set TCR also */
if (!tx && esai_priv->synchronous)
regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, mask, val);
/* Use Normal mode to support monaural audio */
regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
ESAI_xCR_xMOD_MASK, params_channels(params) > 1 ?
ESAI_xCR_xMOD_NETWORK : 0);
regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
ESAI_xFCR_xFR_MASK, ESAI_xFCR_xFR);
mask = ESAI_xFCR_xFR_MASK | ESAI_xFCR_xWA_MASK | ESAI_xFCR_xFWM_MASK |
(tx ? ESAI_xFCR_TE_MASK | ESAI_xFCR_TIEN : ESAI_xFCR_RE_MASK);
val = ESAI_xFCR_xWA(width) | ESAI_xFCR_xFWM(esai_priv->fifo_depth) |
(tx ? ESAI_xFCR_TE(pins) | ESAI_xFCR_TIEN : ESAI_xFCR_RE(pins));
regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), mask, val);
if (tx)
regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR,
ESAI_xCR_PADC, ESAI_xCR_PADC);
/* Remove ESAI personal reset by configuring ESAI_PCRC and ESAI_PRRC */
regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC,
ESAI_PRRC_PDC_MASK, ESAI_PRRC_PDC(ESAI_GPIO));
regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC,
ESAI_PCRC_PC_MASK, ESAI_PCRC_PC(ESAI_GPIO));
return 0;
}
static int fsl_esai_hw_init(struct fsl_esai *esai_priv)
{
struct platform_device *pdev = esai_priv->pdev;
int ret;
/* Reset ESAI unit */
ret = regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR,
ESAI_ECR_ESAIEN_MASK | ESAI_ECR_ERST_MASK,
ESAI_ECR_ESAIEN | ESAI_ECR_ERST);
if (ret) {
dev_err(&pdev->dev, "failed to reset ESAI: %d\n", ret);
return ret;
}
/*
* We need to enable ESAI so as to access some of its registers.
* Otherwise, we would fail to dump regmap from user space.
*/
ret = regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR,
ESAI_ECR_ESAIEN_MASK | ESAI_ECR_ERST_MASK,
ESAI_ECR_ESAIEN);
if (ret) {
dev_err(&pdev->dev, "failed to enable ESAI: %d\n", ret);
return ret;
}
regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC,
ESAI_PRRC_PDC_MASK, 0);
regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC,
ESAI_PCRC_PC_MASK, 0);
return 0;
}
static int fsl_esai_register_restore(struct fsl_esai *esai_priv)
{
int ret;
/* FIFO reset for safety */
regmap_update_bits(esai_priv->regmap, REG_ESAI_TFCR,
ESAI_xFCR_xFR, ESAI_xFCR_xFR);
regmap_update_bits(esai_priv->regmap, REG_ESAI_RFCR,
ESAI_xFCR_xFR, ESAI_xFCR_xFR);
regcache_mark_dirty(esai_priv->regmap);
ret = regcache_sync(esai_priv->regmap);
if (ret)
return ret;
/* FIFO reset done */
regmap_update_bits(esai_priv->regmap, REG_ESAI_TFCR, ESAI_xFCR_xFR, 0);
regmap_update_bits(esai_priv->regmap, REG_ESAI_RFCR, ESAI_xFCR_xFR, 0);
return 0;
}
static void fsl_esai_trigger_start(struct fsl_esai *esai_priv, bool tx)
{
u8 i, channels = esai_priv->channels[tx];
u32 pins = DIV_ROUND_UP(channels, esai_priv->slots);
u32 mask;
regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
ESAI_xFCR_xFEN_MASK, ESAI_xFCR_xFEN);
/* Write initial words reqiured by ESAI as normal procedure */
for (i = 0; tx && i < channels; i++)
regmap_write(esai_priv->regmap, REG_ESAI_ETDR, 0x0);
/*
* When set the TE/RE in the end of enablement flow, there
* will be channel swap issue for multi data line case.
* In order to workaround this issue, we switch the bit
* enablement sequence to below sequence
* 1) clear the xSMB & xSMA: which is done in probe and
* stop state.
* 2) set TE/RE
* 3) set xSMB
* 4) set xSMA: xSMA is the last one in this flow, which
* will trigger esai to start.
*/
regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK,
tx ? ESAI_xCR_TE(pins) : ESAI_xCR_RE(pins));
mask = tx ? esai_priv->tx_mask : esai_priv->rx_mask;
regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx),
ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(mask));
regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx),
ESAI_xSMA_xS_MASK, ESAI_xSMA_xS(mask));
/* Enable Exception interrupt */
regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
ESAI_xCR_xEIE_MASK, ESAI_xCR_xEIE);
}
static void fsl_esai_trigger_stop(struct fsl_esai *esai_priv, bool tx)
{
regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
ESAI_xCR_xEIE_MASK, 0);
regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK, 0);
regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx),
ESAI_xSMA_xS_MASK, 0);
regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx),
ESAI_xSMB_xS_MASK, 0);
/* Disable and reset FIFO */
regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
ESAI_xFCR_xFR | ESAI_xFCR_xFEN, ESAI_xFCR_xFR);
regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
ESAI_xFCR_xFR, 0);
}
static void fsl_esai_hw_reset(struct work_struct *work)
{
struct fsl_esai *esai_priv = container_of(work, struct fsl_esai, work);
bool tx = true, rx = false, enabled[2];
unsigned long lock_flags;
u32 tfcr, rfcr;
spin_lock_irqsave(&esai_priv->lock, lock_flags);
/* Save the registers */
regmap_read(esai_priv->regmap, REG_ESAI_TFCR, &tfcr);
regmap_read(esai_priv->regmap, REG_ESAI_RFCR, &rfcr);
enabled[tx] = tfcr & ESAI_xFCR_xFEN;
enabled[rx] = rfcr & ESAI_xFCR_xFEN;
/* Stop the tx & rx */
fsl_esai_trigger_stop(esai_priv, tx);
fsl_esai_trigger_stop(esai_priv, rx);
/* Reset the esai, and ignore return value */
fsl_esai_hw_init(esai_priv);
/* Enforce ESAI personal resets for both TX and RX */
regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR,
ESAI_xCR_xPR_MASK, ESAI_xCR_xPR);
regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR,
ESAI_xCR_xPR_MASK, ESAI_xCR_xPR);
/* Restore registers by regcache_sync, and ignore return value */
fsl_esai_register_restore(esai_priv);
/* Remove ESAI personal resets by configuring PCRC and PRRC also */
regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR,
ESAI_xCR_xPR_MASK, 0);
regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR,
ESAI_xCR_xPR_MASK, 0);
regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC,
ESAI_PRRC_PDC_MASK, ESAI_PRRC_PDC(ESAI_GPIO));
regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC,
ESAI_PCRC_PC_MASK, ESAI_PCRC_PC(ESAI_GPIO));
/* Restart tx / rx, if they already enabled */
if (enabled[tx])
fsl_esai_trigger_start(esai_priv, tx);
if (enabled[rx])
fsl_esai_trigger_start(esai_priv, rx);
spin_unlock_irqrestore(&esai_priv->lock, lock_flags);
}
static int fsl_esai_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
unsigned long lock_flags;
esai_priv->channels[tx] = substream->runtime->channels;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
spin_lock_irqsave(&esai_priv->lock, lock_flags);
fsl_esai_trigger_start(esai_priv, tx);
spin_unlock_irqrestore(&esai_priv->lock, lock_flags);
break;
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
spin_lock_irqsave(&esai_priv->lock, lock_flags);
fsl_esai_trigger_stop(esai_priv, tx);
spin_unlock_irqrestore(&esai_priv->lock, lock_flags);
break;
default:
return -EINVAL;
}
return 0;
}
static int fsl_esai_dai_probe(struct snd_soc_dai *dai)
{
struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
snd_soc_dai_init_dma_data(dai, &esai_priv->dma_params_tx,
&esai_priv->dma_params_rx);
return 0;
}
static const struct snd_soc_dai_ops fsl_esai_dai_ops = {
.probe = fsl_esai_dai_probe,
.startup = fsl_esai_startup,
.trigger = fsl_esai_trigger,
.hw_params = fsl_esai_hw_params,
.set_sysclk = fsl_esai_set_dai_sysclk,
.set_fmt = fsl_esai_set_dai_fmt,
.set_tdm_slot = fsl_esai_set_dai_tdm_slot,
};
static struct snd_soc_dai_driver fsl_esai_dai = {
.playback = {
.stream_name = "CPU-Playback",
.channels_min = 1,
.channels_max = 12,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = FSL_ESAI_FORMATS,
},
.capture = {
.stream_name = "CPU-Capture",
.channels_min = 1,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = FSL_ESAI_FORMATS,
},
.ops = &fsl_esai_dai_ops,
};
static const struct snd_soc_component_driver fsl_esai_component = {
.name = "fsl-esai",
.legacy_dai_naming = 1,
};
static const struct reg_default fsl_esai_reg_defaults[] = {
{REG_ESAI_ETDR, 0x00000000},
{REG_ESAI_ECR, 0x00000000},
{REG_ESAI_TFCR, 0x00000000},
{REG_ESAI_RFCR, 0x00000000},
{REG_ESAI_TX0, 0x00000000},
{REG_ESAI_TX1, 0x00000000},
{REG_ESAI_TX2, 0x00000000},
{REG_ESAI_TX3, 0x00000000},
{REG_ESAI_TX4, 0x00000000},
{REG_ESAI_TX5, 0x00000000},
{REG_ESAI_TSR, 0x00000000},
{REG_ESAI_SAICR, 0x00000000},
{REG_ESAI_TCR, 0x00000000},
{REG_ESAI_TCCR, 0x00000000},
{REG_ESAI_RCR, 0x00000000},
{REG_ESAI_RCCR, 0x00000000},
{REG_ESAI_TSMA, 0x0000ffff},
{REG_ESAI_TSMB, 0x0000ffff},
{REG_ESAI_RSMA, 0x0000ffff},
{REG_ESAI_RSMB, 0x0000ffff},
{REG_ESAI_PRRC, 0x00000000},
{REG_ESAI_PCRC, 0x00000000},
};
static bool fsl_esai_readable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case REG_ESAI_ERDR:
case REG_ESAI_ECR:
case REG_ESAI_ESR:
case REG_ESAI_TFCR:
case REG_ESAI_TFSR:
case REG_ESAI_RFCR:
case REG_ESAI_RFSR:
case REG_ESAI_RX0:
case REG_ESAI_RX1:
case REG_ESAI_RX2:
case REG_ESAI_RX3:
case REG_ESAI_SAISR:
case REG_ESAI_SAICR:
case REG_ESAI_TCR:
case REG_ESAI_TCCR:
case REG_ESAI_RCR:
case REG_ESAI_RCCR:
case REG_ESAI_TSMA:
case REG_ESAI_TSMB:
case REG_ESAI_RSMA:
case REG_ESAI_RSMB:
case REG_ESAI_PRRC:
case REG_ESAI_PCRC:
return true;
default:
return false;
}
}
static bool fsl_esai_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case REG_ESAI_ERDR:
case REG_ESAI_ESR:
case REG_ESAI_TFSR:
case REG_ESAI_RFSR:
case REG_ESAI_RX0:
case REG_ESAI_RX1:
case REG_ESAI_RX2:
case REG_ESAI_RX3:
case REG_ESAI_SAISR:
return true;
default:
return false;
}
}
static bool fsl_esai_writeable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case REG_ESAI_ETDR:
case REG_ESAI_ECR:
case REG_ESAI_TFCR:
case REG_ESAI_RFCR:
case REG_ESAI_TX0:
case REG_ESAI_TX1:
case REG_ESAI_TX2:
case REG_ESAI_TX3:
case REG_ESAI_TX4:
case REG_ESAI_TX5:
case REG_ESAI_TSR:
case REG_ESAI_SAICR:
case REG_ESAI_TCR:
case REG_ESAI_TCCR:
case REG_ESAI_RCR:
case REG_ESAI_RCCR:
case REG_ESAI_TSMA:
case REG_ESAI_TSMB:
case REG_ESAI_RSMA:
case REG_ESAI_RSMB:
case REG_ESAI_PRRC:
case REG_ESAI_PCRC:
return true;
default:
return false;
}
}
static const struct regmap_config fsl_esai_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = REG_ESAI_PCRC,
.reg_defaults = fsl_esai_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(fsl_esai_reg_defaults),
.readable_reg = fsl_esai_readable_reg,
.volatile_reg = fsl_esai_volatile_reg,
.writeable_reg = fsl_esai_writeable_reg,
.cache_type = REGCACHE_FLAT,
};
static int fsl_esai_runtime_resume(struct device *dev);
static int fsl_esai_runtime_suspend(struct device *dev);
static int fsl_esai_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct fsl_esai *esai_priv;
struct resource *res;
const __be32 *iprop;
void __iomem *regs;
int irq, ret;
esai_priv = devm_kzalloc(&pdev->dev, sizeof(*esai_priv), GFP_KERNEL);
if (!esai_priv)
return -ENOMEM;
esai_priv->pdev = pdev;
snprintf(esai_priv->name, sizeof(esai_priv->name), "%pOFn", np);
esai_priv->soc = of_device_get_match_data(&pdev->dev);
/* Get the addresses and IRQ */
regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(regs))
return PTR_ERR(regs);
esai_priv->regmap = devm_regmap_init_mmio(&pdev->dev, regs, &fsl_esai_regmap_config);
if (IS_ERR(esai_priv->regmap)) {
dev_err(&pdev->dev, "failed to init regmap: %ld\n",
PTR_ERR(esai_priv->regmap));
return PTR_ERR(esai_priv->regmap);
}
esai_priv->coreclk = devm_clk_get(&pdev->dev, "core");
if (IS_ERR(esai_priv->coreclk)) {
dev_err(&pdev->dev, "failed to get core clock: %ld\n",
PTR_ERR(esai_priv->coreclk));
return PTR_ERR(esai_priv->coreclk);
}
esai_priv->extalclk = devm_clk_get(&pdev->dev, "extal");
if (IS_ERR(esai_priv->extalclk))
dev_warn(&pdev->dev, "failed to get extal clock: %ld\n",
PTR_ERR(esai_priv->extalclk));
esai_priv->fsysclk = devm_clk_get(&pdev->dev, "fsys");
if (IS_ERR(esai_priv->fsysclk))
dev_warn(&pdev->dev, "failed to get fsys clock: %ld\n",
PTR_ERR(esai_priv->fsysclk));
esai_priv->spbaclk = devm_clk_get(&pdev->dev, "spba");
if (IS_ERR(esai_priv->spbaclk))
dev_warn(&pdev->dev, "failed to get spba clock: %ld\n",
PTR_ERR(esai_priv->spbaclk));
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
ret = devm_request_irq(&pdev->dev, irq, esai_isr, IRQF_SHARED,
esai_priv->name, esai_priv);
if (ret) {
dev_err(&pdev->dev, "failed to claim irq %u\n", irq);
return ret;
}
/* Set a default slot number */
esai_priv->slots = 2;
/* Set a default clock provider state */
esai_priv->consumer_mode = true;
/* Determine the FIFO depth */
iprop = of_get_property(np, "fsl,fifo-depth", NULL);
if (iprop)
esai_priv->fifo_depth = be32_to_cpup(iprop);
else
esai_priv->fifo_depth = 64;
esai_priv->dma_params_tx.maxburst = 16;
esai_priv->dma_params_rx.maxburst = 16;
esai_priv->dma_params_tx.addr = res->start + REG_ESAI_ETDR;
esai_priv->dma_params_rx.addr = res->start + REG_ESAI_ERDR;
esai_priv->synchronous =
of_property_read_bool(np, "fsl,esai-synchronous");
/* Implement full symmetry for synchronous mode */
if (esai_priv->synchronous) {
fsl_esai_dai.symmetric_rate = 1;
fsl_esai_dai.symmetric_channels = 1;
fsl_esai_dai.symmetric_sample_bits = 1;
}
dev_set_drvdata(&pdev->dev, esai_priv);
spin_lock_init(&esai_priv->lock);
pm_runtime_enable(&pdev->dev);
if (!pm_runtime_enabled(&pdev->dev)) {
ret = fsl_esai_runtime_resume(&pdev->dev);
if (ret)
goto err_pm_disable;
}
ret = pm_runtime_resume_and_get(&pdev->dev);
if (ret < 0)
goto err_pm_get_sync;
ret = fsl_esai_hw_init(esai_priv);
if (ret)
goto err_pm_get_sync;
esai_priv->tx_mask = 0xFFFFFFFF;
esai_priv->rx_mask = 0xFFFFFFFF;
/* Clear the TSMA, TSMB, RSMA, RSMB */
regmap_write(esai_priv->regmap, REG_ESAI_TSMA, 0);
regmap_write(esai_priv->regmap, REG_ESAI_TSMB, 0);
regmap_write(esai_priv->regmap, REG_ESAI_RSMA, 0);
regmap_write(esai_priv->regmap, REG_ESAI_RSMB, 0);
ret = pm_runtime_put_sync(&pdev->dev);
if (ret < 0 && ret != -ENOSYS)
goto err_pm_get_sync;
/*
* Register platform component before registering cpu dai for there
* is not defer probe for platform component in snd_soc_add_pcm_runtime().
*/
ret = imx_pcm_dma_init(pdev);
if (ret) {
dev_err(&pdev->dev, "failed to init imx pcm dma: %d\n", ret);
goto err_pm_get_sync;
}
ret = devm_snd_soc_register_component(&pdev->dev, &fsl_esai_component,
&fsl_esai_dai, 1);
if (ret) {
dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
goto err_pm_get_sync;
}
INIT_WORK(&esai_priv->work, fsl_esai_hw_reset);
return ret;
err_pm_get_sync:
if (!pm_runtime_status_suspended(&pdev->dev))
fsl_esai_runtime_suspend(&pdev->dev);
err_pm_disable:
pm_runtime_disable(&pdev->dev);
return ret;
}
static void fsl_esai_remove(struct platform_device *pdev)
{
struct fsl_esai *esai_priv = platform_get_drvdata(pdev);
pm_runtime_disable(&pdev->dev);
if (!pm_runtime_status_suspended(&pdev->dev))
fsl_esai_runtime_suspend(&pdev->dev);
cancel_work_sync(&esai_priv->work);
}
static const struct of_device_id fsl_esai_dt_ids[] = {
{ .compatible = "fsl,imx35-esai", .data = &fsl_esai_imx35 },
{ .compatible = "fsl,vf610-esai", .data = &fsl_esai_vf610 },
{ .compatible = "fsl,imx6ull-esai", .data = &fsl_esai_imx6ull },
{}
};
MODULE_DEVICE_TABLE(of, fsl_esai_dt_ids);
static int fsl_esai_runtime_resume(struct device *dev)
{
struct fsl_esai *esai = dev_get_drvdata(dev);
int ret;
/*
* Some platforms might use the same bit to gate all three or two of
* clocks, so keep all clocks open/close at the same time for safety
*/
ret = clk_prepare_enable(esai->coreclk);
if (ret)
return ret;
if (!IS_ERR(esai->spbaclk)) {
ret = clk_prepare_enable(esai->spbaclk);
if (ret)
goto err_spbaclk;
}
if (!IS_ERR(esai->extalclk)) {
ret = clk_prepare_enable(esai->extalclk);
if (ret)
goto err_extalclk;
}
if (!IS_ERR(esai->fsysclk)) {
ret = clk_prepare_enable(esai->fsysclk);
if (ret)
goto err_fsysclk;
}
regcache_cache_only(esai->regmap, false);
ret = fsl_esai_register_restore(esai);
if (ret)
goto err_regcache_sync;
return 0;
err_regcache_sync:
if (!IS_ERR(esai->fsysclk))
clk_disable_unprepare(esai->fsysclk);
err_fsysclk:
if (!IS_ERR(esai->extalclk))
clk_disable_unprepare(esai->extalclk);
err_extalclk:
if (!IS_ERR(esai->spbaclk))
clk_disable_unprepare(esai->spbaclk);
err_spbaclk:
clk_disable_unprepare(esai->coreclk);
return ret;
}
static int fsl_esai_runtime_suspend(struct device *dev)
{
struct fsl_esai *esai = dev_get_drvdata(dev);
regcache_cache_only(esai->regmap, true);
if (!IS_ERR(esai->fsysclk))
clk_disable_unprepare(esai->fsysclk);
if (!IS_ERR(esai->extalclk))
clk_disable_unprepare(esai->extalclk);
if (!IS_ERR(esai->spbaclk))
clk_disable_unprepare(esai->spbaclk);
clk_disable_unprepare(esai->coreclk);
return 0;
}
static const struct dev_pm_ops fsl_esai_pm_ops = {
SET_RUNTIME_PM_OPS(fsl_esai_runtime_suspend,
fsl_esai_runtime_resume,
NULL)
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
};
static struct platform_driver fsl_esai_driver = {
.probe = fsl_esai_probe,
.remove_new = fsl_esai_remove,
.driver = {
.name = "fsl-esai-dai",
.pm = &fsl_esai_pm_ops,
.of_match_table = fsl_esai_dt_ids,
},
};
module_platform_driver(fsl_esai_driver);
MODULE_AUTHOR("Freescale Semiconductor, Inc.");
MODULE_DESCRIPTION("Freescale ESAI CPU DAI driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:fsl-esai-dai");
| linux-master | sound/soc/fsl/fsl_esai.c |
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2013 Freescale Semiconductor, Inc.
#include <linux/module.h>
#include <linux/of_platform.h>
#include <sound/soc.h>
struct imx_spdif_data {
struct snd_soc_dai_link dai;
struct snd_soc_card card;
};
static int imx_spdif_audio_probe(struct platform_device *pdev)
{
struct device_node *spdif_np, *np = pdev->dev.of_node;
struct imx_spdif_data *data;
struct snd_soc_dai_link_component *comp;
int ret = 0;
spdif_np = of_parse_phandle(np, "spdif-controller", 0);
if (!spdif_np) {
dev_err(&pdev->dev, "failed to find spdif-controller\n");
ret = -EINVAL;
goto end;
}
data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
comp = devm_kzalloc(&pdev->dev, sizeof(*comp), GFP_KERNEL);
if (!data || !comp) {
ret = -ENOMEM;
goto end;
}
/*
* CPU == Platform
* platform is using soc-generic-dmaengine-pcm
*/
data->dai.cpus =
data->dai.platforms = comp;
data->dai.codecs = &asoc_dummy_dlc;
data->dai.num_cpus = 1;
data->dai.num_codecs = 1;
data->dai.num_platforms = 1;
data->dai.name = "S/PDIF PCM";
data->dai.stream_name = "S/PDIF PCM";
data->dai.cpus->of_node = spdif_np;
data->dai.playback_only = true;
data->dai.capture_only = true;
if (of_property_read_bool(np, "spdif-out"))
data->dai.capture_only = false;
if (of_property_read_bool(np, "spdif-in"))
data->dai.playback_only = false;
if (data->dai.playback_only && data->dai.capture_only) {
dev_err(&pdev->dev, "no enabled S/PDIF DAI link\n");
goto end;
}
data->card.dev = &pdev->dev;
data->card.dai_link = &data->dai;
data->card.num_links = 1;
data->card.owner = THIS_MODULE;
ret = snd_soc_of_parse_card_name(&data->card, "model");
if (ret)
goto end;
ret = devm_snd_soc_register_card(&pdev->dev, &data->card);
if (ret)
dev_err_probe(&pdev->dev, ret, "snd_soc_register_card failed\n");
end:
of_node_put(spdif_np);
return ret;
}
static const struct of_device_id imx_spdif_dt_ids[] = {
{ .compatible = "fsl,imx-audio-spdif", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx_spdif_dt_ids);
static struct platform_driver imx_spdif_driver = {
.driver = {
.name = "imx-spdif",
.pm = &snd_soc_pm_ops,
.of_match_table = imx_spdif_dt_ids,
},
.probe = imx_spdif_audio_probe,
};
module_platform_driver(imx_spdif_driver);
MODULE_AUTHOR("Freescale Semiconductor, Inc.");
MODULE_DESCRIPTION("Freescale i.MX S/PDIF machine driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:imx-spdif");
| linux-master | sound/soc/fsl/imx-spdif.c |
// SPDX-License-Identifier: GPL-2.0
//
// Freescale SSI ALSA SoC Digital Audio Interface (DAI) debugging functions
//
// Copyright 2014 Markus Pargmann <[email protected]>, Pengutronix
//
// Split from fsl_ssi.c
#include <linux/debugfs.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include "fsl_ssi.h"
void fsl_ssi_dbg_isr(struct fsl_ssi_dbg *dbg, u32 sisr)
{
if (sisr & SSI_SISR_RFRC)
dbg->stats.rfrc++;
if (sisr & SSI_SISR_TFRC)
dbg->stats.tfrc++;
if (sisr & SSI_SISR_CMDAU)
dbg->stats.cmdau++;
if (sisr & SSI_SISR_CMDDU)
dbg->stats.cmddu++;
if (sisr & SSI_SISR_RXT)
dbg->stats.rxt++;
if (sisr & SSI_SISR_RDR1)
dbg->stats.rdr1++;
if (sisr & SSI_SISR_RDR0)
dbg->stats.rdr0++;
if (sisr & SSI_SISR_TDE1)
dbg->stats.tde1++;
if (sisr & SSI_SISR_TDE0)
dbg->stats.tde0++;
if (sisr & SSI_SISR_ROE1)
dbg->stats.roe1++;
if (sisr & SSI_SISR_ROE0)
dbg->stats.roe0++;
if (sisr & SSI_SISR_TUE1)
dbg->stats.tue1++;
if (sisr & SSI_SISR_TUE0)
dbg->stats.tue0++;
if (sisr & SSI_SISR_TFS)
dbg->stats.tfs++;
if (sisr & SSI_SISR_RFS)
dbg->stats.rfs++;
if (sisr & SSI_SISR_TLS)
dbg->stats.tls++;
if (sisr & SSI_SISR_RLS)
dbg->stats.rls++;
if (sisr & SSI_SISR_RFF1)
dbg->stats.rff1++;
if (sisr & SSI_SISR_RFF0)
dbg->stats.rff0++;
if (sisr & SSI_SISR_TFE1)
dbg->stats.tfe1++;
if (sisr & SSI_SISR_TFE0)
dbg->stats.tfe0++;
}
/*
* Show the statistics of a flag only if its interrupt is enabled
*
* Compilers will optimize it to a no-op if the interrupt is disabled
*/
#define SIER_SHOW(flag, name) \
do { \
if (SSI_SIER_##flag) \
seq_printf(s, #name "=%u\n", ssi_dbg->stats.name); \
} while (0)
/*
* Display the statistics for the current SSI device
*
* To avoid confusion, only show those counts that are enabled
*/
static int fsl_ssi_stats_show(struct seq_file *s, void *unused)
{
struct fsl_ssi_dbg *ssi_dbg = s->private;
SIER_SHOW(RFRC_EN, rfrc);
SIER_SHOW(TFRC_EN, tfrc);
SIER_SHOW(CMDAU_EN, cmdau);
SIER_SHOW(CMDDU_EN, cmddu);
SIER_SHOW(RXT_EN, rxt);
SIER_SHOW(RDR1_EN, rdr1);
SIER_SHOW(RDR0_EN, rdr0);
SIER_SHOW(TDE1_EN, tde1);
SIER_SHOW(TDE0_EN, tde0);
SIER_SHOW(ROE1_EN, roe1);
SIER_SHOW(ROE0_EN, roe0);
SIER_SHOW(TUE1_EN, tue1);
SIER_SHOW(TUE0_EN, tue0);
SIER_SHOW(TFS_EN, tfs);
SIER_SHOW(RFS_EN, rfs);
SIER_SHOW(TLS_EN, tls);
SIER_SHOW(RLS_EN, rls);
SIER_SHOW(RFF1_EN, rff1);
SIER_SHOW(RFF0_EN, rff0);
SIER_SHOW(TFE1_EN, tfe1);
SIER_SHOW(TFE0_EN, tfe0);
return 0;
}
DEFINE_SHOW_ATTRIBUTE(fsl_ssi_stats);
void fsl_ssi_debugfs_create(struct fsl_ssi_dbg *ssi_dbg, struct device *dev)
{
ssi_dbg->dbg_dir = debugfs_create_dir(dev_name(dev), NULL);
debugfs_create_file("stats", 0444, ssi_dbg->dbg_dir, ssi_dbg,
&fsl_ssi_stats_fops);
}
void fsl_ssi_debugfs_remove(struct fsl_ssi_dbg *ssi_dbg)
{
debugfs_remove_recursive(ssi_dbg->dbg_dir);
}
| linux-master | sound/soc/fsl/fsl_ssi_dbg.c |
// SPDX-License-Identifier: GPL-2.0
//
// Freescale ASRC ALSA SoC Platform (DMA) driver
//
// Copyright (C) 2014 Freescale Semiconductor, Inc.
//
// Author: Nicolin Chen <[email protected]>
#include <linux/dma-mapping.h>
#include <linux/module.h>
#include <linux/dma/imx-dma.h>
#include <sound/dmaengine_pcm.h>
#include <sound/pcm_params.h>
#include "fsl_asrc_common.h"
#define FSL_ASRC_DMABUF_SIZE (256 * 1024)
static struct snd_pcm_hardware snd_imx_hardware = {
.info = SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_BLOCK_TRANSFER |
SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_MMAP_VALID,
.buffer_bytes_max = FSL_ASRC_DMABUF_SIZE,
.period_bytes_min = 128,
.period_bytes_max = 65535, /* Limited by SDMA engine */
.periods_min = 2,
.periods_max = 255,
.fifo_size = 0,
};
static bool filter(struct dma_chan *chan, void *param)
{
if (!imx_dma_is_general_purpose(chan))
return false;
chan->private = param;
return true;
}
static void fsl_asrc_dma_complete(void *arg)
{
struct snd_pcm_substream *substream = arg;
struct snd_pcm_runtime *runtime = substream->runtime;
struct fsl_asrc_pair *pair = runtime->private_data;
pair->pos += snd_pcm_lib_period_bytes(substream);
if (pair->pos >= snd_pcm_lib_buffer_bytes(substream))
pair->pos = 0;
snd_pcm_period_elapsed(substream);
}
static int fsl_asrc_dma_prepare_and_submit(struct snd_pcm_substream *substream,
struct snd_soc_component *component)
{
u8 dir = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? OUT : IN;
struct snd_pcm_runtime *runtime = substream->runtime;
struct fsl_asrc_pair *pair = runtime->private_data;
struct device *dev = component->dev;
unsigned long flags = DMA_CTRL_ACK;
/* Prepare and submit Front-End DMA channel */
if (!substream->runtime->no_period_wakeup)
flags |= DMA_PREP_INTERRUPT;
pair->pos = 0;
pair->desc[!dir] = dmaengine_prep_dma_cyclic(
pair->dma_chan[!dir], runtime->dma_addr,
snd_pcm_lib_buffer_bytes(substream),
snd_pcm_lib_period_bytes(substream),
dir == OUT ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, flags);
if (!pair->desc[!dir]) {
dev_err(dev, "failed to prepare slave DMA for Front-End\n");
return -ENOMEM;
}
pair->desc[!dir]->callback = fsl_asrc_dma_complete;
pair->desc[!dir]->callback_param = substream;
dmaengine_submit(pair->desc[!dir]);
/* Prepare and submit Back-End DMA channel */
pair->desc[dir] = dmaengine_prep_dma_cyclic(
pair->dma_chan[dir], 0xffff, 64, 64, DMA_DEV_TO_DEV, 0);
if (!pair->desc[dir]) {
dev_err(dev, "failed to prepare slave DMA for Back-End\n");
return -ENOMEM;
}
dmaengine_submit(pair->desc[dir]);
return 0;
}
static int fsl_asrc_dma_trigger(struct snd_soc_component *component,
struct snd_pcm_substream *substream, int cmd)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct fsl_asrc_pair *pair = runtime->private_data;
int ret;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
ret = fsl_asrc_dma_prepare_and_submit(substream, component);
if (ret)
return ret;
dma_async_issue_pending(pair->dma_chan[IN]);
dma_async_issue_pending(pair->dma_chan[OUT]);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
dmaengine_terminate_async(pair->dma_chan[OUT]);
dmaengine_terminate_async(pair->dma_chan[IN]);
break;
default:
return -EINVAL;
}
return 0;
}
static int fsl_asrc_dma_hw_params(struct snd_soc_component *component,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
enum dma_slave_buswidth buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
enum sdma_peripheral_type be_peripheral_type = IMX_DMATYPE_SSI;
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
struct snd_dmaengine_dai_dma_data *dma_params_fe = NULL;
struct snd_dmaengine_dai_dma_data *dma_params_be = NULL;
struct snd_pcm_runtime *runtime = substream->runtime;
struct fsl_asrc_pair *pair = runtime->private_data;
struct dma_chan *tmp_chan = NULL, *be_chan = NULL;
struct snd_soc_component *component_be = NULL;
struct fsl_asrc *asrc = pair->asrc;
struct dma_slave_config config_fe = {}, config_be = {};
struct sdma_peripheral_config audio_config;
enum asrc_pair_index index = pair->index;
struct device *dev = component->dev;
struct device_node *of_dma_node;
int stream = substream->stream;
struct imx_dma_data *tmp_data;
struct snd_soc_dpcm *dpcm;
struct device *dev_be;
u8 dir = tx ? OUT : IN;
dma_cap_mask_t mask;
int ret, width;
/* Fetch the Back-End dma_data from DPCM */
for_each_dpcm_be(rtd, stream, dpcm) {
struct snd_soc_pcm_runtime *be = dpcm->be;
struct snd_pcm_substream *substream_be;
struct snd_soc_dai *dai = asoc_rtd_to_cpu(be, 0);
if (dpcm->fe != rtd)
continue;
substream_be = snd_soc_dpcm_get_substream(be, stream);
dma_params_be = snd_soc_dai_get_dma_data(dai, substream_be);
dev_be = dai->dev;
break;
}
if (!dma_params_be) {
dev_err(dev, "failed to get the substream of Back-End\n");
return -EINVAL;
}
/* Override dma_data of the Front-End and config its dmaengine */
dma_params_fe = snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(rtd, 0), substream);
dma_params_fe->addr = asrc->paddr + asrc->get_fifo_addr(!dir, index);
dma_params_fe->maxburst = dma_params_be->maxburst;
pair->dma_chan[!dir] = asrc->get_dma_channel(pair, !dir);
if (!pair->dma_chan[!dir]) {
dev_err(dev, "failed to request DMA channel\n");
return -EINVAL;
}
ret = snd_dmaengine_pcm_prepare_slave_config(substream, params, &config_fe);
if (ret) {
dev_err(dev, "failed to prepare DMA config for Front-End\n");
return ret;
}
ret = dmaengine_slave_config(pair->dma_chan[!dir], &config_fe);
if (ret) {
dev_err(dev, "failed to config DMA channel for Front-End\n");
return ret;
}
/* Request and config DMA channel for Back-End */
dma_cap_zero(mask);
dma_cap_set(DMA_SLAVE, mask);
dma_cap_set(DMA_CYCLIC, mask);
/*
* The Back-End device might have already requested a DMA channel,
* so try to reuse it first, and then request a new one upon NULL.
*/
component_be = snd_soc_lookup_component_nolocked(dev_be, SND_DMAENGINE_PCM_DRV_NAME);
if (component_be) {
be_chan = soc_component_to_pcm(component_be)->chan[substream->stream];
tmp_chan = be_chan;
}
if (!tmp_chan) {
tmp_chan = dma_request_chan(dev_be, tx ? "tx" : "rx");
if (IS_ERR(tmp_chan)) {
dev_err(dev, "failed to request DMA channel for Back-End\n");
return -EINVAL;
}
}
/*
* An EDMA DEV_TO_DEV channel is fixed and bound with DMA event of each
* peripheral, unlike SDMA channel that is allocated dynamically. So no
* need to configure dma_request and dma_request2, but get dma_chan of
* Back-End device directly via dma_request_chan.
*/
if (!asrc->use_edma) {
/* Get DMA request of Back-End */
tmp_data = tmp_chan->private;
pair->dma_data.dma_request = tmp_data->dma_request;
be_peripheral_type = tmp_data->peripheral_type;
if (!be_chan)
dma_release_channel(tmp_chan);
/* Get DMA request of Front-End */
tmp_chan = asrc->get_dma_channel(pair, dir);
tmp_data = tmp_chan->private;
pair->dma_data.dma_request2 = tmp_data->dma_request;
pair->dma_data.peripheral_type = tmp_data->peripheral_type;
pair->dma_data.priority = tmp_data->priority;
dma_release_channel(tmp_chan);
of_dma_node = pair->dma_chan[!dir]->device->dev->of_node;
pair->dma_chan[dir] =
__dma_request_channel(&mask, filter, &pair->dma_data,
of_dma_node);
pair->req_dma_chan = true;
} else {
pair->dma_chan[dir] = tmp_chan;
/* Do not flag to release if we are reusing the Back-End one */
pair->req_dma_chan = !be_chan;
}
if (!pair->dma_chan[dir]) {
dev_err(dev, "failed to request DMA channel for Back-End\n");
return -EINVAL;
}
width = snd_pcm_format_physical_width(asrc->asrc_format);
if (width < 8 || width > 64)
return -EINVAL;
else if (width == 8)
buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
else if (width == 16)
buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
else if (width == 24)
buswidth = DMA_SLAVE_BUSWIDTH_3_BYTES;
else if (width <= 32)
buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
else
buswidth = DMA_SLAVE_BUSWIDTH_8_BYTES;
config_be.direction = DMA_DEV_TO_DEV;
config_be.src_addr_width = buswidth;
config_be.src_maxburst = dma_params_be->maxburst;
config_be.dst_addr_width = buswidth;
config_be.dst_maxburst = dma_params_be->maxburst;
memset(&audio_config, 0, sizeof(audio_config));
config_be.peripheral_config = &audio_config;
config_be.peripheral_size = sizeof(audio_config);
if (tx && (be_peripheral_type == IMX_DMATYPE_SSI_DUAL ||
be_peripheral_type == IMX_DMATYPE_SPDIF))
audio_config.n_fifos_dst = 2;
if (!tx && (be_peripheral_type == IMX_DMATYPE_SSI_DUAL ||
be_peripheral_type == IMX_DMATYPE_SPDIF))
audio_config.n_fifos_src = 2;
if (tx) {
config_be.src_addr = asrc->paddr + asrc->get_fifo_addr(OUT, index);
config_be.dst_addr = dma_params_be->addr;
} else {
config_be.dst_addr = asrc->paddr + asrc->get_fifo_addr(IN, index);
config_be.src_addr = dma_params_be->addr;
}
ret = dmaengine_slave_config(pair->dma_chan[dir], &config_be);
if (ret) {
dev_err(dev, "failed to config DMA channel for Back-End\n");
if (pair->req_dma_chan)
dma_release_channel(pair->dma_chan[dir]);
return ret;
}
return 0;
}
static int fsl_asrc_dma_hw_free(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
struct snd_pcm_runtime *runtime = substream->runtime;
struct fsl_asrc_pair *pair = runtime->private_data;
u8 dir = tx ? OUT : IN;
if (pair->dma_chan[!dir])
dma_release_channel(pair->dma_chan[!dir]);
/* release dev_to_dev chan if we aren't reusing the Back-End one */
if (pair->dma_chan[dir] && pair->req_dma_chan)
dma_release_channel(pair->dma_chan[dir]);
pair->dma_chan[!dir] = NULL;
pair->dma_chan[dir] = NULL;
return 0;
}
static int fsl_asrc_dma_startup(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_dmaengine_dai_dma_data *dma_data;
struct device *dev = component->dev;
struct fsl_asrc *asrc = dev_get_drvdata(dev);
struct fsl_asrc_pair *pair;
struct dma_chan *tmp_chan = NULL;
u8 dir = tx ? OUT : IN;
bool release_pair = true;
int ret = 0;
ret = snd_pcm_hw_constraint_integer(substream->runtime,
SNDRV_PCM_HW_PARAM_PERIODS);
if (ret < 0) {
dev_err(dev, "failed to set pcm hw params periods\n");
return ret;
}
pair = kzalloc(sizeof(*pair) + asrc->pair_priv_size, GFP_KERNEL);
if (!pair)
return -ENOMEM;
pair->asrc = asrc;
pair->private = (void *)pair + sizeof(struct fsl_asrc_pair);
runtime->private_data = pair;
/* Request a dummy pair, which will be released later.
* Request pair function needs channel num as input, for this
* dummy pair, we just request "1" channel temporarily.
*/
ret = asrc->request_pair(1, pair);
if (ret < 0) {
dev_err(dev, "failed to request asrc pair\n");
goto req_pair_err;
}
/* Request a dummy dma channel, which will be released later. */
tmp_chan = asrc->get_dma_channel(pair, dir);
if (!tmp_chan) {
dev_err(dev, "failed to get dma channel\n");
ret = -EINVAL;
goto dma_chan_err;
}
dma_data = snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(rtd, 0), substream);
/* Refine the snd_imx_hardware according to caps of DMA. */
ret = snd_dmaengine_pcm_refine_runtime_hwparams(substream,
dma_data,
&snd_imx_hardware,
tmp_chan);
if (ret < 0) {
dev_err(dev, "failed to refine runtime hwparams\n");
goto out;
}
release_pair = false;
snd_soc_set_runtime_hwparams(substream, &snd_imx_hardware);
out:
dma_release_channel(tmp_chan);
dma_chan_err:
asrc->release_pair(pair);
req_pair_err:
if (release_pair)
kfree(pair);
return ret;
}
static int fsl_asrc_dma_shutdown(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct fsl_asrc_pair *pair = runtime->private_data;
struct fsl_asrc *asrc;
if (!pair)
return 0;
asrc = pair->asrc;
if (asrc->pair[pair->index] == pair)
asrc->pair[pair->index] = NULL;
kfree(pair);
return 0;
}
static snd_pcm_uframes_t
fsl_asrc_dma_pcm_pointer(struct snd_soc_component *component,
struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct fsl_asrc_pair *pair = runtime->private_data;
return bytes_to_frames(substream->runtime, pair->pos);
}
static int fsl_asrc_dma_pcm_new(struct snd_soc_component *component,
struct snd_soc_pcm_runtime *rtd)
{
struct snd_card *card = rtd->card->snd_card;
struct snd_pcm *pcm = rtd->pcm;
int ret;
ret = dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(32));
if (ret) {
dev_err(card->dev, "failed to set DMA mask\n");
return ret;
}
return snd_pcm_set_fixed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
card->dev, FSL_ASRC_DMABUF_SIZE);
}
struct snd_soc_component_driver fsl_asrc_component = {
.name = DRV_NAME,
.hw_params = fsl_asrc_dma_hw_params,
.hw_free = fsl_asrc_dma_hw_free,
.trigger = fsl_asrc_dma_trigger,
.open = fsl_asrc_dma_startup,
.close = fsl_asrc_dma_shutdown,
.pointer = fsl_asrc_dma_pcm_pointer,
.pcm_construct = fsl_asrc_dma_pcm_new,
.legacy_dai_naming = 1,
};
EXPORT_SYMBOL_GPL(fsl_asrc_component);
| linux-master | sound/soc/fsl/fsl_asrc_dma.c |
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2012 Freescale Semiconductor, Inc.
// Copyright 2012 Linaro Ltd.
// Copyright 2009 Pengutronix, Sascha Hauer <[email protected]>
//
// Initial development of this code was funded by
// Phytec Messtechnik GmbH, https://www.phytec.de
#include <linux/clk.h>
#include <linux/debugfs.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include "imx-audmux.h"
#define DRIVER_NAME "imx-audmux"
static struct clk *audmux_clk;
static void __iomem *audmux_base;
static u32 *regcache;
static u32 reg_max;
#define IMX_AUDMUX_V2_PTCR(x) ((x) * 8)
#define IMX_AUDMUX_V2_PDCR(x) ((x) * 8 + 4)
#ifdef CONFIG_DEBUG_FS
static struct dentry *audmux_debugfs_root;
/* There is an annoying discontinuity in the SSI numbering with regard
* to the Linux number of the devices */
static const char *audmux_port_string(int port)
{
switch (port) {
case MX31_AUDMUX_PORT1_SSI0:
return "imx-ssi.0";
case MX31_AUDMUX_PORT2_SSI1:
return "imx-ssi.1";
case MX31_AUDMUX_PORT3_SSI_PINS_3:
return "SSI3";
case MX31_AUDMUX_PORT4_SSI_PINS_4:
return "SSI4";
case MX31_AUDMUX_PORT5_SSI_PINS_5:
return "SSI5";
case MX31_AUDMUX_PORT6_SSI_PINS_6:
return "SSI6";
default:
return "UNKNOWN";
}
}
static ssize_t audmux_read_file(struct file *file, char __user *user_buf,
size_t count, loff_t *ppos)
{
ssize_t ret;
char *buf;
uintptr_t port = (uintptr_t)file->private_data;
u32 pdcr, ptcr;
ret = clk_prepare_enable(audmux_clk);
if (ret)
return ret;
ptcr = readl(audmux_base + IMX_AUDMUX_V2_PTCR(port));
pdcr = readl(audmux_base + IMX_AUDMUX_V2_PDCR(port));
clk_disable_unprepare(audmux_clk);
buf = kmalloc(PAGE_SIZE, GFP_KERNEL);
if (!buf)
return -ENOMEM;
ret = sysfs_emit(buf, "PDCR: %08x\nPTCR: %08x\n", pdcr, ptcr);
if (ptcr & IMX_AUDMUX_V2_PTCR_TFSDIR)
ret += scnprintf(buf + ret, PAGE_SIZE - ret,
"TxFS output from %s, ",
audmux_port_string((ptcr >> 27) & 0x7));
else
ret += scnprintf(buf + ret, PAGE_SIZE - ret,
"TxFS input, ");
if (ptcr & IMX_AUDMUX_V2_PTCR_TCLKDIR)
ret += scnprintf(buf + ret, PAGE_SIZE - ret,
"TxClk output from %s",
audmux_port_string((ptcr >> 22) & 0x7));
else
ret += scnprintf(buf + ret, PAGE_SIZE - ret,
"TxClk input");
ret += scnprintf(buf + ret, PAGE_SIZE - ret, "\n");
if (ptcr & IMX_AUDMUX_V2_PTCR_SYN) {
ret += scnprintf(buf + ret, PAGE_SIZE - ret,
"Port is symmetric");
} else {
if (ptcr & IMX_AUDMUX_V2_PTCR_RFSDIR)
ret += scnprintf(buf + ret, PAGE_SIZE - ret,
"RxFS output from %s, ",
audmux_port_string((ptcr >> 17) & 0x7));
else
ret += scnprintf(buf + ret, PAGE_SIZE - ret,
"RxFS input, ");
if (ptcr & IMX_AUDMUX_V2_PTCR_RCLKDIR)
ret += scnprintf(buf + ret, PAGE_SIZE - ret,
"RxClk output from %s",
audmux_port_string((ptcr >> 12) & 0x7));
else
ret += scnprintf(buf + ret, PAGE_SIZE - ret,
"RxClk input");
}
ret += scnprintf(buf + ret, PAGE_SIZE - ret,
"\nData received from %s\n",
audmux_port_string((pdcr >> 13) & 0x7));
ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
kfree(buf);
return ret;
}
static const struct file_operations audmux_debugfs_fops = {
.open = simple_open,
.read = audmux_read_file,
.llseek = default_llseek,
};
static void audmux_debugfs_init(void)
{
uintptr_t i;
char buf[20];
audmux_debugfs_root = debugfs_create_dir("audmux", NULL);
for (i = 0; i < MX31_AUDMUX_PORT7_SSI_PINS_7 + 1; i++) {
snprintf(buf, sizeof(buf), "ssi%lu", i);
debugfs_create_file(buf, 0444, audmux_debugfs_root,
(void *)i, &audmux_debugfs_fops);
}
}
static void audmux_debugfs_remove(void)
{
debugfs_remove_recursive(audmux_debugfs_root);
}
#else
static inline void audmux_debugfs_init(void)
{
}
static inline void audmux_debugfs_remove(void)
{
}
#endif
static enum imx_audmux_type {
IMX21_AUDMUX,
IMX31_AUDMUX,
} audmux_type;
static const struct of_device_id imx_audmux_dt_ids[] = {
{ .compatible = "fsl,imx21-audmux", .data = (void *)IMX21_AUDMUX, },
{ .compatible = "fsl,imx31-audmux", .data = (void *)IMX31_AUDMUX, },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx_audmux_dt_ids);
static const uint8_t port_mapping[] = {
0x0, 0x4, 0x8, 0x10, 0x14, 0x1c,
};
int imx_audmux_v1_configure_port(unsigned int port, unsigned int pcr)
{
if (audmux_type != IMX21_AUDMUX)
return -EINVAL;
if (!audmux_base)
return -ENOSYS;
if (port >= ARRAY_SIZE(port_mapping))
return -EINVAL;
writel(pcr, audmux_base + port_mapping[port]);
return 0;
}
EXPORT_SYMBOL_GPL(imx_audmux_v1_configure_port);
int imx_audmux_v2_configure_port(unsigned int port, unsigned int ptcr,
unsigned int pdcr)
{
int ret;
if (audmux_type != IMX31_AUDMUX)
return -EINVAL;
if (!audmux_base)
return -ENOSYS;
ret = clk_prepare_enable(audmux_clk);
if (ret)
return ret;
writel(ptcr, audmux_base + IMX_AUDMUX_V2_PTCR(port));
writel(pdcr, audmux_base + IMX_AUDMUX_V2_PDCR(port));
clk_disable_unprepare(audmux_clk);
return 0;
}
EXPORT_SYMBOL_GPL(imx_audmux_v2_configure_port);
static int imx_audmux_parse_dt_defaults(struct platform_device *pdev,
struct device_node *of_node)
{
struct device_node *child;
for_each_available_child_of_node(of_node, child) {
unsigned int port;
unsigned int ptcr = 0;
unsigned int pdcr = 0;
unsigned int pcr = 0;
unsigned int val;
int ret;
int i = 0;
ret = of_property_read_u32(child, "fsl,audmux-port", &port);
if (ret) {
dev_warn(&pdev->dev, "Failed to get fsl,audmux-port of child node \"%pOF\"\n",
child);
continue;
}
if (!of_property_read_bool(child, "fsl,port-config")) {
dev_warn(&pdev->dev, "child node \"%pOF\" does not have property fsl,port-config\n",
child);
continue;
}
for (i = 0; (ret = of_property_read_u32_index(child,
"fsl,port-config", i, &val)) == 0;
++i) {
if (audmux_type == IMX31_AUDMUX) {
if (i % 2)
pdcr |= val;
else
ptcr |= val;
} else {
pcr |= val;
}
}
if (ret != -EOVERFLOW) {
dev_err(&pdev->dev, "Failed to read u32 at index %d of child %pOF\n",
i, child);
continue;
}
if (audmux_type == IMX31_AUDMUX) {
if (i % 2) {
dev_err(&pdev->dev, "One pdcr value is missing in child node %pOF\n",
child);
continue;
}
imx_audmux_v2_configure_port(port, ptcr, pdcr);
} else {
imx_audmux_v1_configure_port(port, pcr);
}
}
return 0;
}
static int imx_audmux_probe(struct platform_device *pdev)
{
audmux_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(audmux_base))
return PTR_ERR(audmux_base);
audmux_clk = devm_clk_get(&pdev->dev, "audmux");
if (IS_ERR(audmux_clk)) {
dev_dbg(&pdev->dev, "cannot get clock: %ld\n",
PTR_ERR(audmux_clk));
audmux_clk = NULL;
}
audmux_type = (uintptr_t)of_device_get_match_data(&pdev->dev);
switch (audmux_type) {
case IMX31_AUDMUX:
audmux_debugfs_init();
reg_max = 14;
break;
case IMX21_AUDMUX:
reg_max = 6;
break;
default:
dev_err(&pdev->dev, "unsupported version!\n");
return -EINVAL;
}
regcache = devm_kzalloc(&pdev->dev, sizeof(u32) * reg_max, GFP_KERNEL);
if (!regcache)
return -ENOMEM;
imx_audmux_parse_dt_defaults(pdev, pdev->dev.of_node);
return 0;
}
static void imx_audmux_remove(struct platform_device *pdev)
{
if (audmux_type == IMX31_AUDMUX)
audmux_debugfs_remove();
}
#ifdef CONFIG_PM_SLEEP
static int imx_audmux_suspend(struct device *dev)
{
int i;
clk_prepare_enable(audmux_clk);
for (i = 0; i < reg_max; i++)
regcache[i] = readl(audmux_base + i * 4);
clk_disable_unprepare(audmux_clk);
return 0;
}
static int imx_audmux_resume(struct device *dev)
{
int i;
clk_prepare_enable(audmux_clk);
for (i = 0; i < reg_max; i++)
writel(regcache[i], audmux_base + i * 4);
clk_disable_unprepare(audmux_clk);
return 0;
}
#endif /* CONFIG_PM_SLEEP */
static const struct dev_pm_ops imx_audmux_pm = {
SET_SYSTEM_SLEEP_PM_OPS(imx_audmux_suspend, imx_audmux_resume)
};
static struct platform_driver imx_audmux_driver = {
.probe = imx_audmux_probe,
.remove_new = imx_audmux_remove,
.driver = {
.name = DRIVER_NAME,
.pm = &imx_audmux_pm,
.of_match_table = imx_audmux_dt_ids,
}
};
static int __init imx_audmux_init(void)
{
return platform_driver_register(&imx_audmux_driver);
}
subsys_initcall(imx_audmux_init);
static void __exit imx_audmux_exit(void)
{
platform_driver_unregister(&imx_audmux_driver);
}
module_exit(imx_audmux_exit);
MODULE_DESCRIPTION("Freescale i.MX AUDMUX driver");
MODULE_AUTHOR("Sascha Hauer <[email protected]>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRIVER_NAME);
| linux-master | sound/soc/fsl/imx-audmux.c |
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2012 Freescale Semiconductor, Inc.
// Copyright 2012 Linaro Ltd.
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/i2c.h>
#include <linux/clk.h>
#include <sound/soc.h>
#include "../codecs/sgtl5000.h"
#include "imx-audmux.h"
#define DAI_NAME_SIZE 32
struct imx_sgtl5000_data {
struct snd_soc_dai_link dai;
struct snd_soc_card card;
char codec_dai_name[DAI_NAME_SIZE];
char platform_name[DAI_NAME_SIZE];
struct clk *codec_clk;
unsigned int clk_frequency;
};
static int imx_sgtl5000_dai_init(struct snd_soc_pcm_runtime *rtd)
{
struct imx_sgtl5000_data *data = snd_soc_card_get_drvdata(rtd->card);
struct device *dev = rtd->card->dev;
int ret;
ret = snd_soc_dai_set_sysclk(asoc_rtd_to_codec(rtd, 0), SGTL5000_SYSCLK,
data->clk_frequency, SND_SOC_CLOCK_IN);
if (ret) {
dev_err(dev, "could not set codec driver clock params\n");
return ret;
}
return 0;
}
static const struct snd_soc_dapm_widget imx_sgtl5000_dapm_widgets[] = {
SND_SOC_DAPM_MIC("Mic Jack", NULL),
SND_SOC_DAPM_LINE("Line In Jack", NULL),
SND_SOC_DAPM_HP("Headphone Jack", NULL),
SND_SOC_DAPM_SPK("Line Out Jack", NULL),
SND_SOC_DAPM_SPK("Ext Spk", NULL),
};
static int imx_sgtl5000_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct device_node *ssi_np, *codec_np;
struct platform_device *ssi_pdev;
struct i2c_client *codec_dev;
struct imx_sgtl5000_data *data = NULL;
struct snd_soc_dai_link_component *comp;
int int_port, ext_port;
int ret;
ret = of_property_read_u32(np, "mux-int-port", &int_port);
if (ret) {
dev_err(&pdev->dev, "mux-int-port missing or invalid\n");
return ret;
}
ret = of_property_read_u32(np, "mux-ext-port", &ext_port);
if (ret) {
dev_err(&pdev->dev, "mux-ext-port missing or invalid\n");
return ret;
}
/*
* The port numbering in the hardware manual starts at 1, while
* the audmux API expects it starts at 0.
*/
int_port--;
ext_port--;
ret = imx_audmux_v2_configure_port(int_port,
IMX_AUDMUX_V2_PTCR_SYN |
IMX_AUDMUX_V2_PTCR_TFSEL(ext_port) |
IMX_AUDMUX_V2_PTCR_TCSEL(ext_port) |
IMX_AUDMUX_V2_PTCR_TFSDIR |
IMX_AUDMUX_V2_PTCR_TCLKDIR,
IMX_AUDMUX_V2_PDCR_RXDSEL(ext_port));
if (ret) {
dev_err(&pdev->dev, "audmux internal port setup failed\n");
return ret;
}
ret = imx_audmux_v2_configure_port(ext_port,
IMX_AUDMUX_V2_PTCR_SYN,
IMX_AUDMUX_V2_PDCR_RXDSEL(int_port));
if (ret) {
dev_err(&pdev->dev, "audmux external port setup failed\n");
return ret;
}
ssi_np = of_parse_phandle(pdev->dev.of_node, "ssi-controller", 0);
codec_np = of_parse_phandle(pdev->dev.of_node, "audio-codec", 0);
if (!ssi_np || !codec_np) {
dev_err(&pdev->dev, "phandle missing or invalid\n");
ret = -EINVAL;
goto fail;
}
ssi_pdev = of_find_device_by_node(ssi_np);
if (!ssi_pdev) {
dev_dbg(&pdev->dev, "failed to find SSI platform device\n");
ret = -EPROBE_DEFER;
goto fail;
}
put_device(&ssi_pdev->dev);
codec_dev = of_find_i2c_device_by_node(codec_np);
if (!codec_dev) {
dev_dbg(&pdev->dev, "failed to find codec platform device\n");
ret = -EPROBE_DEFER;
goto fail;
}
data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
if (!data) {
ret = -ENOMEM;
goto put_device;
}
comp = devm_kzalloc(&pdev->dev, 3 * sizeof(*comp), GFP_KERNEL);
if (!comp) {
ret = -ENOMEM;
goto put_device;
}
data->codec_clk = clk_get(&codec_dev->dev, NULL);
if (IS_ERR(data->codec_clk)) {
ret = PTR_ERR(data->codec_clk);
goto put_device;
}
data->clk_frequency = clk_get_rate(data->codec_clk);
data->dai.cpus = &comp[0];
data->dai.codecs = &comp[1];
data->dai.platforms = &comp[2];
data->dai.num_cpus = 1;
data->dai.num_codecs = 1;
data->dai.num_platforms = 1;
data->dai.name = "HiFi";
data->dai.stream_name = "HiFi";
data->dai.codecs->dai_name = "sgtl5000";
data->dai.codecs->of_node = codec_np;
data->dai.cpus->of_node = ssi_np;
data->dai.platforms->of_node = ssi_np;
data->dai.init = &imx_sgtl5000_dai_init;
data->dai.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBP_CFP;
data->card.dev = &pdev->dev;
ret = snd_soc_of_parse_card_name(&data->card, "model");
if (ret)
goto put_device;
ret = snd_soc_of_parse_audio_routing(&data->card, "audio-routing");
if (ret)
goto put_device;
data->card.num_links = 1;
data->card.owner = THIS_MODULE;
data->card.dai_link = &data->dai;
data->card.dapm_widgets = imx_sgtl5000_dapm_widgets;
data->card.num_dapm_widgets = ARRAY_SIZE(imx_sgtl5000_dapm_widgets);
platform_set_drvdata(pdev, &data->card);
snd_soc_card_set_drvdata(&data->card, data);
ret = devm_snd_soc_register_card(&pdev->dev, &data->card);
if (ret) {
dev_err_probe(&pdev->dev, ret, "snd_soc_register_card failed\n");
goto put_device;
}
of_node_put(ssi_np);
of_node_put(codec_np);
return 0;
put_device:
put_device(&codec_dev->dev);
fail:
if (data && !IS_ERR(data->codec_clk))
clk_put(data->codec_clk);
of_node_put(ssi_np);
of_node_put(codec_np);
return ret;
}
static void imx_sgtl5000_remove(struct platform_device *pdev)
{
struct snd_soc_card *card = platform_get_drvdata(pdev);
struct imx_sgtl5000_data *data = snd_soc_card_get_drvdata(card);
clk_put(data->codec_clk);
}
static const struct of_device_id imx_sgtl5000_dt_ids[] = {
{ .compatible = "fsl,imx-audio-sgtl5000", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx_sgtl5000_dt_ids);
static struct platform_driver imx_sgtl5000_driver = {
.driver = {
.name = "imx-sgtl5000",
.pm = &snd_soc_pm_ops,
.of_match_table = imx_sgtl5000_dt_ids,
},
.probe = imx_sgtl5000_probe,
.remove_new = imx_sgtl5000_remove,
};
module_platform_driver(imx_sgtl5000_driver);
MODULE_AUTHOR("Shawn Guo <[email protected]>");
MODULE_DESCRIPTION("Freescale i.MX SGTL5000 ASoC machine driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:imx-sgtl5000");
| linux-master | sound/soc/fsl/imx-sgtl5000.c |
// SPDX-License-Identifier: GPL-2.0-only
/* sound/soc/rockchip/rockchip_i2s.c
*
* ALSA SoC Audio Layer - Rockchip I2S Controller driver
*
* Copyright (c) 2014 Rockchip Electronics Co. Ltd.
* Author: Jianqun <[email protected]>
*/
#include <linux/module.h>
#include <linux/mfd/syscon.h>
#include <linux/delay.h>
#include <linux/of_gpio.h>
#include <linux/of_device.h>
#include <linux/clk.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/spinlock.h>
#include <sound/pcm_params.h>
#include <sound/dmaengine_pcm.h>
#include "rockchip_i2s.h"
#define DRV_NAME "rockchip-i2s"
struct rk_i2s_pins {
u32 reg_offset;
u32 shift;
};
struct rk_i2s_dev {
struct device *dev;
struct clk *hclk;
struct clk *mclk;
struct snd_dmaengine_dai_dma_data capture_dma_data;
struct snd_dmaengine_dai_dma_data playback_dma_data;
struct regmap *regmap;
struct regmap *grf;
bool has_capture;
bool has_playback;
/*
* Used to indicate the tx/rx status.
* I2S controller hopes to start the tx and rx together,
* also to stop them when they are both try to stop.
*/
bool tx_start;
bool rx_start;
bool is_master_mode;
const struct rk_i2s_pins *pins;
unsigned int bclk_ratio;
spinlock_t lock; /* tx/rx lock */
struct pinctrl *pinctrl;
struct pinctrl_state *bclk_on;
struct pinctrl_state *bclk_off;
};
static int i2s_pinctrl_select_bclk_on(struct rk_i2s_dev *i2s)
{
int ret = 0;
if (!IS_ERR(i2s->pinctrl) && !IS_ERR_OR_NULL(i2s->bclk_on))
ret = pinctrl_select_state(i2s->pinctrl, i2s->bclk_on);
if (ret)
dev_err(i2s->dev, "bclk enable failed %d\n", ret);
return ret;
}
static int i2s_pinctrl_select_bclk_off(struct rk_i2s_dev *i2s)
{
int ret = 0;
if (!IS_ERR(i2s->pinctrl) && !IS_ERR_OR_NULL(i2s->bclk_off))
ret = pinctrl_select_state(i2s->pinctrl, i2s->bclk_off);
if (ret)
dev_err(i2s->dev, "bclk disable failed %d\n", ret);
return ret;
}
static int i2s_runtime_suspend(struct device *dev)
{
struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
regcache_cache_only(i2s->regmap, true);
clk_disable_unprepare(i2s->mclk);
return 0;
}
static int i2s_runtime_resume(struct device *dev)
{
struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
int ret;
ret = clk_prepare_enable(i2s->mclk);
if (ret) {
dev_err(i2s->dev, "clock enable failed %d\n", ret);
return ret;
}
regcache_cache_only(i2s->regmap, false);
regcache_mark_dirty(i2s->regmap);
ret = regcache_sync(i2s->regmap);
if (ret)
clk_disable_unprepare(i2s->mclk);
return ret;
}
static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai)
{
return snd_soc_dai_get_drvdata(dai);
}
static int rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
{
unsigned int val = 0;
int ret = 0;
spin_lock(&i2s->lock);
if (on) {
ret = regmap_update_bits(i2s->regmap, I2S_DMACR,
I2S_DMACR_TDE_ENABLE,
I2S_DMACR_TDE_ENABLE);
if (ret < 0)
goto end;
ret = regmap_update_bits(i2s->regmap, I2S_XFER,
I2S_XFER_TXS_START | I2S_XFER_RXS_START,
I2S_XFER_TXS_START | I2S_XFER_RXS_START);
if (ret < 0)
goto end;
i2s->tx_start = true;
} else {
i2s->tx_start = false;
ret = regmap_update_bits(i2s->regmap, I2S_DMACR,
I2S_DMACR_TDE_ENABLE,
I2S_DMACR_TDE_DISABLE);
if (ret < 0)
goto end;
if (!i2s->rx_start) {
ret = regmap_update_bits(i2s->regmap, I2S_XFER,
I2S_XFER_TXS_START | I2S_XFER_RXS_START,
I2S_XFER_TXS_STOP | I2S_XFER_RXS_STOP);
if (ret < 0)
goto end;
udelay(150);
ret = regmap_update_bits(i2s->regmap, I2S_CLR,
I2S_CLR_TXC | I2S_CLR_RXC,
I2S_CLR_TXC | I2S_CLR_RXC);
if (ret < 0)
goto end;
ret = regmap_read_poll_timeout_atomic(i2s->regmap,
I2S_CLR,
val,
val == 0,
20,
200);
if (ret < 0)
dev_warn(i2s->dev, "fail to clear: %d\n", ret);
}
}
end:
spin_unlock(&i2s->lock);
if (ret < 0)
dev_err(i2s->dev, "lrclk update failed\n");
return ret;
}
static int rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
{
unsigned int val = 0;
int ret = 0;
spin_lock(&i2s->lock);
if (on) {
ret = regmap_update_bits(i2s->regmap, I2S_DMACR,
I2S_DMACR_RDE_ENABLE,
I2S_DMACR_RDE_ENABLE);
if (ret < 0)
goto end;
ret = regmap_update_bits(i2s->regmap, I2S_XFER,
I2S_XFER_TXS_START | I2S_XFER_RXS_START,
I2S_XFER_TXS_START | I2S_XFER_RXS_START);
if (ret < 0)
goto end;
i2s->rx_start = true;
} else {
i2s->rx_start = false;
ret = regmap_update_bits(i2s->regmap, I2S_DMACR,
I2S_DMACR_RDE_ENABLE,
I2S_DMACR_RDE_DISABLE);
if (ret < 0)
goto end;
if (!i2s->tx_start) {
ret = regmap_update_bits(i2s->regmap, I2S_XFER,
I2S_XFER_TXS_START | I2S_XFER_RXS_START,
I2S_XFER_TXS_STOP | I2S_XFER_RXS_STOP);
if (ret < 0)
goto end;
udelay(150);
ret = regmap_update_bits(i2s->regmap, I2S_CLR,
I2S_CLR_TXC | I2S_CLR_RXC,
I2S_CLR_TXC | I2S_CLR_RXC);
if (ret < 0)
goto end;
ret = regmap_read_poll_timeout_atomic(i2s->regmap,
I2S_CLR,
val,
val == 0,
20,
200);
if (ret < 0)
dev_warn(i2s->dev, "fail to clear: %d\n", ret);
}
}
end:
spin_unlock(&i2s->lock);
if (ret < 0)
dev_err(i2s->dev, "lrclk update failed\n");
return ret;
}
static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
unsigned int fmt)
{
struct rk_i2s_dev *i2s = to_info(cpu_dai);
unsigned int mask = 0, val = 0;
int ret = 0;
pm_runtime_get_sync(cpu_dai->dev);
mask = I2S_CKR_MSS_MASK;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BP_FP:
/* Set source clock in Master mode */
val = I2S_CKR_MSS_MASTER;
i2s->is_master_mode = true;
break;
case SND_SOC_DAIFMT_BC_FC:
val = I2S_CKR_MSS_SLAVE;
i2s->is_master_mode = false;
break;
default:
ret = -EINVAL;
goto err_pm_put;
}
regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
mask = I2S_CKR_CKP_MASK | I2S_CKR_TLP_MASK | I2S_CKR_RLP_MASK;
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
val = I2S_CKR_CKP_NORMAL |
I2S_CKR_TLP_NORMAL |
I2S_CKR_RLP_NORMAL;
break;
case SND_SOC_DAIFMT_NB_IF:
val = I2S_CKR_CKP_NORMAL |
I2S_CKR_TLP_INVERTED |
I2S_CKR_RLP_INVERTED;
break;
case SND_SOC_DAIFMT_IB_NF:
val = I2S_CKR_CKP_INVERTED |
I2S_CKR_TLP_NORMAL |
I2S_CKR_RLP_NORMAL;
break;
case SND_SOC_DAIFMT_IB_IF:
val = I2S_CKR_CKP_INVERTED |
I2S_CKR_TLP_INVERTED |
I2S_CKR_RLP_INVERTED;
break;
default:
ret = -EINVAL;
goto err_pm_put;
}
regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK;
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_RIGHT_J:
val = I2S_TXCR_IBM_RSJM;
break;
case SND_SOC_DAIFMT_LEFT_J:
val = I2S_TXCR_IBM_LSJM;
break;
case SND_SOC_DAIFMT_I2S:
val = I2S_TXCR_IBM_NORMAL;
break;
case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 bit mode */
val = I2S_TXCR_TFS_PCM | I2S_TXCR_PBM_MODE(1);
break;
case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */
val = I2S_TXCR_TFS_PCM;
break;
default:
ret = -EINVAL;
goto err_pm_put;
}
regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);
mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK;
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_RIGHT_J:
val = I2S_RXCR_IBM_RSJM;
break;
case SND_SOC_DAIFMT_LEFT_J:
val = I2S_RXCR_IBM_LSJM;
break;
case SND_SOC_DAIFMT_I2S:
val = I2S_RXCR_IBM_NORMAL;
break;
case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 bit mode */
val = I2S_RXCR_TFS_PCM | I2S_RXCR_PBM_MODE(1);
break;
case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */
val = I2S_RXCR_TFS_PCM;
break;
default:
ret = -EINVAL;
goto err_pm_put;
}
regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);
err_pm_put:
pm_runtime_put(cpu_dai->dev);
return ret;
}
static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct rk_i2s_dev *i2s = to_info(dai);
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
unsigned int val = 0;
unsigned int mclk_rate, bclk_rate, div_bclk, div_lrck;
if (i2s->is_master_mode) {
mclk_rate = clk_get_rate(i2s->mclk);
bclk_rate = i2s->bclk_ratio * params_rate(params);
if (!bclk_rate)
return -EINVAL;
div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
div_lrck = bclk_rate / params_rate(params);
regmap_update_bits(i2s->regmap, I2S_CKR,
I2S_CKR_MDIV_MASK,
I2S_CKR_MDIV(div_bclk));
regmap_update_bits(i2s->regmap, I2S_CKR,
I2S_CKR_TSD_MASK |
I2S_CKR_RSD_MASK,
I2S_CKR_TSD(div_lrck) |
I2S_CKR_RSD(div_lrck));
}
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S8:
val |= I2S_TXCR_VDW(8);
break;
case SNDRV_PCM_FORMAT_S16_LE:
val |= I2S_TXCR_VDW(16);
break;
case SNDRV_PCM_FORMAT_S20_3LE:
val |= I2S_TXCR_VDW(20);
break;
case SNDRV_PCM_FORMAT_S24_LE:
val |= I2S_TXCR_VDW(24);
break;
case SNDRV_PCM_FORMAT_S32_LE:
val |= I2S_TXCR_VDW(32);
break;
default:
return -EINVAL;
}
switch (params_channels(params)) {
case 8:
val |= I2S_CHN_8;
break;
case 6:
val |= I2S_CHN_6;
break;
case 4:
val |= I2S_CHN_4;
break;
case 2:
val |= I2S_CHN_2;
break;
default:
dev_err(i2s->dev, "invalid channel: %d\n",
params_channels(params));
return -EINVAL;
}
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
regmap_update_bits(i2s->regmap, I2S_RXCR,
I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
val);
else
regmap_update_bits(i2s->regmap, I2S_TXCR,
I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
val);
if (!IS_ERR(i2s->grf) && i2s->pins) {
regmap_read(i2s->regmap, I2S_TXCR, &val);
val &= I2S_TXCR_CSR_MASK;
switch (val) {
case I2S_CHN_4:
val = I2S_IO_4CH_OUT_6CH_IN;
break;
case I2S_CHN_6:
val = I2S_IO_6CH_OUT_4CH_IN;
break;
case I2S_CHN_8:
val = I2S_IO_8CH_OUT_2CH_IN;
break;
default:
val = I2S_IO_2CH_OUT_8CH_IN;
break;
}
val <<= i2s->pins->shift;
val |= (I2S_IO_DIRECTION_MASK << i2s->pins->shift) << 16;
regmap_write(i2s->grf, i2s->pins->reg_offset, val);
}
regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
I2S_DMACR_TDL(16));
regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
I2S_DMACR_RDL(16));
val = I2S_CKR_TRCM_TXRX;
if (dai->driver->symmetric_rate && rtd->dai_link->symmetric_rate)
val = I2S_CKR_TRCM_TXONLY;
regmap_update_bits(i2s->regmap, I2S_CKR,
I2S_CKR_TRCM_MASK,
val);
return 0;
}
static int rockchip_i2s_trigger(struct snd_pcm_substream *substream,
int cmd, struct snd_soc_dai *dai)
{
struct rk_i2s_dev *i2s = to_info(dai);
int ret = 0;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
ret = rockchip_snd_rxctrl(i2s, 1);
else
ret = rockchip_snd_txctrl(i2s, 1);
if (ret < 0)
return ret;
i2s_pinctrl_select_bclk_on(i2s);
break;
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
if (!i2s->tx_start)
i2s_pinctrl_select_bclk_off(i2s);
ret = rockchip_snd_rxctrl(i2s, 0);
} else {
if (!i2s->rx_start)
i2s_pinctrl_select_bclk_off(i2s);
ret = rockchip_snd_txctrl(i2s, 0);
}
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
static int rockchip_i2s_set_bclk_ratio(struct snd_soc_dai *dai,
unsigned int ratio)
{
struct rk_i2s_dev *i2s = to_info(dai);
i2s->bclk_ratio = ratio;
return 0;
}
static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
unsigned int freq, int dir)
{
struct rk_i2s_dev *i2s = to_info(cpu_dai);
int ret;
if (freq == 0)
return 0;
ret = clk_set_rate(i2s->mclk, freq);
if (ret)
dev_err(i2s->dev, "Fail to set mclk %d\n", ret);
return ret;
}
static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai)
{
struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
snd_soc_dai_init_dma_data(dai,
i2s->has_playback ? &i2s->playback_dma_data : NULL,
i2s->has_capture ? &i2s->capture_dma_data : NULL);
return 0;
}
static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
.probe = rockchip_i2s_dai_probe,
.hw_params = rockchip_i2s_hw_params,
.set_bclk_ratio = rockchip_i2s_set_bclk_ratio,
.set_sysclk = rockchip_i2s_set_sysclk,
.set_fmt = rockchip_i2s_set_fmt,
.trigger = rockchip_i2s_trigger,
};
static struct snd_soc_dai_driver rockchip_i2s_dai = {
.ops = &rockchip_i2s_dai_ops,
.symmetric_rate = 1,
};
static const struct snd_soc_component_driver rockchip_i2s_component = {
.name = DRV_NAME,
.legacy_dai_naming = 1,
};
static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case I2S_TXCR:
case I2S_RXCR:
case I2S_CKR:
case I2S_DMACR:
case I2S_INTCR:
case I2S_XFER:
case I2S_CLR:
case I2S_TXDR:
return true;
default:
return false;
}
}
static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case I2S_TXCR:
case I2S_RXCR:
case I2S_CKR:
case I2S_DMACR:
case I2S_INTCR:
case I2S_XFER:
case I2S_CLR:
case I2S_TXDR:
case I2S_RXDR:
case I2S_FIFOLR:
case I2S_INTSR:
return true;
default:
return false;
}
}
static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case I2S_INTSR:
case I2S_CLR:
case I2S_FIFOLR:
case I2S_TXDR:
case I2S_RXDR:
return true;
default:
return false;
}
}
static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case I2S_RXDR:
return true;
default:
return false;
}
}
static const struct reg_default rockchip_i2s_reg_defaults[] = {
{0x00, 0x0000000f},
{0x04, 0x0000000f},
{0x08, 0x00071f1f},
{0x10, 0x001f0000},
{0x14, 0x01f00000},
};
static const struct regmap_config rockchip_i2s_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = I2S_RXDR,
.reg_defaults = rockchip_i2s_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(rockchip_i2s_reg_defaults),
.writeable_reg = rockchip_i2s_wr_reg,
.readable_reg = rockchip_i2s_rd_reg,
.volatile_reg = rockchip_i2s_volatile_reg,
.precious_reg = rockchip_i2s_precious_reg,
.cache_type = REGCACHE_FLAT,
};
static const struct rk_i2s_pins rk3399_i2s_pins = {
.reg_offset = 0xe220,
.shift = 11,
};
static const struct of_device_id rockchip_i2s_match[] __maybe_unused = {
{ .compatible = "rockchip,px30-i2s", },
{ .compatible = "rockchip,rk1808-i2s", },
{ .compatible = "rockchip,rk3036-i2s", },
{ .compatible = "rockchip,rk3066-i2s", },
{ .compatible = "rockchip,rk3128-i2s", },
{ .compatible = "rockchip,rk3188-i2s", },
{ .compatible = "rockchip,rk3228-i2s", },
{ .compatible = "rockchip,rk3288-i2s", },
{ .compatible = "rockchip,rk3308-i2s", },
{ .compatible = "rockchip,rk3328-i2s", },
{ .compatible = "rockchip,rk3366-i2s", },
{ .compatible = "rockchip,rk3368-i2s", },
{ .compatible = "rockchip,rk3399-i2s", .data = &rk3399_i2s_pins },
{ .compatible = "rockchip,rk3588-i2s", },
{ .compatible = "rockchip,rv1126-i2s", },
{},
};
static int rockchip_i2s_init_dai(struct rk_i2s_dev *i2s, struct resource *res,
struct snd_soc_dai_driver **dp)
{
struct device_node *node = i2s->dev->of_node;
struct snd_soc_dai_driver *dai;
struct property *dma_names;
const char *dma_name;
unsigned int val;
of_property_for_each_string(node, "dma-names", dma_names, dma_name) {
if (!strcmp(dma_name, "tx"))
i2s->has_playback = true;
if (!strcmp(dma_name, "rx"))
i2s->has_capture = true;
}
dai = devm_kmemdup(i2s->dev, &rockchip_i2s_dai,
sizeof(*dai), GFP_KERNEL);
if (!dai)
return -ENOMEM;
if (i2s->has_playback) {
dai->playback.stream_name = "Playback";
dai->playback.channels_min = 2;
dai->playback.channels_max = 8;
dai->playback.rates = SNDRV_PCM_RATE_8000_192000;
dai->playback.formats = SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S20_3LE |
SNDRV_PCM_FMTBIT_S24_LE |
SNDRV_PCM_FMTBIT_S32_LE;
i2s->playback_dma_data.addr = res->start + I2S_TXDR;
i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
i2s->playback_dma_data.maxburst = 8;
if (!of_property_read_u32(node, "rockchip,playback-channels", &val)) {
if (val >= 2 && val <= 8)
dai->playback.channels_max = val;
}
}
if (i2s->has_capture) {
dai->capture.stream_name = "Capture";
dai->capture.channels_min = 2;
dai->capture.channels_max = 8;
dai->capture.rates = SNDRV_PCM_RATE_8000_192000;
dai->capture.formats = SNDRV_PCM_FMTBIT_S8 |
SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S20_3LE |
SNDRV_PCM_FMTBIT_S24_LE |
SNDRV_PCM_FMTBIT_S32_LE;
i2s->capture_dma_data.addr = res->start + I2S_RXDR;
i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
i2s->capture_dma_data.maxburst = 8;
if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) {
if (val >= 2 && val <= 8)
dai->capture.channels_max = val;
}
}
if (dp)
*dp = dai;
return 0;
}
static int rockchip_i2s_probe(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
const struct of_device_id *of_id;
struct rk_i2s_dev *i2s;
struct snd_soc_dai_driver *dai;
struct resource *res;
void __iomem *regs;
int ret;
i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
if (!i2s)
return -ENOMEM;
spin_lock_init(&i2s->lock);
i2s->dev = &pdev->dev;
i2s->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
if (!IS_ERR(i2s->grf)) {
of_id = of_match_device(rockchip_i2s_match, &pdev->dev);
if (!of_id || !of_id->data)
return -EINVAL;
i2s->pins = of_id->data;
}
/* try to prepare related clocks */
i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
if (IS_ERR(i2s->hclk)) {
dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
return PTR_ERR(i2s->hclk);
}
ret = clk_prepare_enable(i2s->hclk);
if (ret) {
dev_err(i2s->dev, "hclock enable failed %d\n", ret);
return ret;
}
i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
if (IS_ERR(i2s->mclk)) {
dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
ret = PTR_ERR(i2s->mclk);
goto err_clk;
}
regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(regs)) {
ret = PTR_ERR(regs);
goto err_clk;
}
i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
&rockchip_i2s_regmap_config);
if (IS_ERR(i2s->regmap)) {
dev_err(&pdev->dev,
"Failed to initialise managed register map\n");
ret = PTR_ERR(i2s->regmap);
goto err_clk;
}
i2s->bclk_ratio = 64;
i2s->pinctrl = devm_pinctrl_get(&pdev->dev);
if (!IS_ERR(i2s->pinctrl)) {
i2s->bclk_on = pinctrl_lookup_state(i2s->pinctrl, "bclk_on");
if (!IS_ERR_OR_NULL(i2s->bclk_on)) {
i2s->bclk_off = pinctrl_lookup_state(i2s->pinctrl, "bclk_off");
if (IS_ERR_OR_NULL(i2s->bclk_off)) {
dev_err(&pdev->dev, "failed to find i2s bclk_off\n");
ret = -EINVAL;
goto err_clk;
}
}
} else {
dev_dbg(&pdev->dev, "failed to find i2s pinctrl\n");
}
i2s_pinctrl_select_bclk_off(i2s);
dev_set_drvdata(&pdev->dev, i2s);
pm_runtime_enable(&pdev->dev);
if (!pm_runtime_enabled(&pdev->dev)) {
ret = i2s_runtime_resume(&pdev->dev);
if (ret)
goto err_pm_disable;
}
ret = rockchip_i2s_init_dai(i2s, res, &dai);
if (ret)
goto err_pm_disable;
ret = devm_snd_soc_register_component(&pdev->dev,
&rockchip_i2s_component,
dai, 1);
if (ret) {
dev_err(&pdev->dev, "Could not register DAI\n");
goto err_suspend;
}
ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
if (ret) {
dev_err(&pdev->dev, "Could not register PCM\n");
goto err_suspend;
}
return 0;
err_suspend:
if (!pm_runtime_status_suspended(&pdev->dev))
i2s_runtime_suspend(&pdev->dev);
err_pm_disable:
pm_runtime_disable(&pdev->dev);
err_clk:
clk_disable_unprepare(i2s->hclk);
return ret;
}
static void rockchip_i2s_remove(struct platform_device *pdev)
{
struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);
pm_runtime_disable(&pdev->dev);
if (!pm_runtime_status_suspended(&pdev->dev))
i2s_runtime_suspend(&pdev->dev);
clk_disable_unprepare(i2s->hclk);
}
static const struct dev_pm_ops rockchip_i2s_pm_ops = {
SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,
NULL)
};
static struct platform_driver rockchip_i2s_driver = {
.probe = rockchip_i2s_probe,
.remove_new = rockchip_i2s_remove,
.driver = {
.name = DRV_NAME,
.of_match_table = of_match_ptr(rockchip_i2s_match),
.pm = &rockchip_i2s_pm_ops,
},
};
module_platform_driver(rockchip_i2s_driver);
MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface");
MODULE_AUTHOR("jianqun <[email protected]>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRV_NAME);
MODULE_DEVICE_TABLE(of, rockchip_i2s_match);
| linux-master | sound/soc/rockchip/rockchip_i2s.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Rockchip machine ASoC driver for boards using a MAX90809 CODEC.
*
* Copyright (c) 2014, ROCKCHIP CORPORATION. All rights reserved.
*/
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/gpio.h>
#include <linux/of_gpio.h>
#include <sound/core.h>
#include <sound/jack.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include "rockchip_i2s.h"
#include "../codecs/ts3a227e.h"
#define DRV_NAME "rockchip-snd-max98090"
static struct snd_soc_jack headset_jack;
/* Headset jack detection DAPM pins */
static struct snd_soc_jack_pin headset_jack_pins[] = {
{
.pin = "Headphone",
.mask = SND_JACK_HEADPHONE,
},
{
.pin = "Headset Mic",
.mask = SND_JACK_MICROPHONE,
},
};
#define RK_MAX98090_WIDGETS \
SND_SOC_DAPM_HP("Headphone", NULL), \
SND_SOC_DAPM_MIC("Headset Mic", NULL), \
SND_SOC_DAPM_MIC("Int Mic", NULL), \
SND_SOC_DAPM_SPK("Speaker", NULL)
#define RK_HDMI_WIDGETS \
SND_SOC_DAPM_LINE("HDMI", NULL)
static const struct snd_soc_dapm_widget rk_max98090_dapm_widgets[] = {
RK_MAX98090_WIDGETS,
};
static const struct snd_soc_dapm_widget rk_hdmi_dapm_widgets[] = {
RK_HDMI_WIDGETS,
};
static const struct snd_soc_dapm_widget rk_max98090_hdmi_dapm_widgets[] = {
RK_MAX98090_WIDGETS,
RK_HDMI_WIDGETS,
};
#define RK_MAX98090_AUDIO_MAP \
{"IN34", NULL, "Headset Mic"}, \
{"Headset Mic", NULL, "MICBIAS"}, \
{"DMICL", NULL, "Int Mic"}, \
{"Headphone", NULL, "HPL"}, \
{"Headphone", NULL, "HPR"}, \
{"Speaker", NULL, "SPKL"}, \
{"Speaker", NULL, "SPKR"}
#define RK_HDMI_AUDIO_MAP \
{"HDMI", NULL, "TX"}
static const struct snd_soc_dapm_route rk_max98090_audio_map[] = {
RK_MAX98090_AUDIO_MAP,
};
static const struct snd_soc_dapm_route rk_hdmi_audio_map[] = {
RK_HDMI_AUDIO_MAP,
};
static const struct snd_soc_dapm_route rk_max98090_hdmi_audio_map[] = {
RK_MAX98090_AUDIO_MAP,
RK_HDMI_AUDIO_MAP,
};
#define RK_MAX98090_CONTROLS \
SOC_DAPM_PIN_SWITCH("Headphone"), \
SOC_DAPM_PIN_SWITCH("Headset Mic"), \
SOC_DAPM_PIN_SWITCH("Int Mic"), \
SOC_DAPM_PIN_SWITCH("Speaker")
#define RK_HDMI_CONTROLS \
SOC_DAPM_PIN_SWITCH("HDMI")
static const struct snd_kcontrol_new rk_max98090_controls[] = {
RK_MAX98090_CONTROLS,
};
static const struct snd_kcontrol_new rk_hdmi_controls[] = {
RK_HDMI_CONTROLS,
};
static const struct snd_kcontrol_new rk_max98090_hdmi_controls[] = {
RK_MAX98090_CONTROLS,
RK_HDMI_CONTROLS,
};
static int rk_jack_event(struct notifier_block *nb, unsigned long event,
void *data)
{
struct snd_soc_jack *jack = (struct snd_soc_jack *)data;
struct snd_soc_dapm_context *dapm = &jack->card->dapm;
if (event & SND_JACK_MICROPHONE) {
snd_soc_dapm_force_enable_pin(dapm, "MICBIAS");
snd_soc_dapm_force_enable_pin(dapm, "SHDN");
} else {
snd_soc_dapm_disable_pin(dapm, "MICBIAS");
snd_soc_dapm_disable_pin(dapm, "SHDN");
}
snd_soc_dapm_sync(dapm);
return 0;
}
static struct notifier_block rk_jack_nb = {
.notifier_call = rk_jack_event,
};
static int rk_init(struct snd_soc_pcm_runtime *runtime)
{
/*
* The jack has already been created in the rk_98090_headset_init()
* function.
*/
snd_soc_jack_notifier_register(&headset_jack, &rk_jack_nb);
return 0;
}
static int rk_aif1_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
int ret = 0;
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
int mclk;
switch (params_rate(params)) {
case 8000:
case 16000:
case 24000:
case 32000:
case 48000:
case 64000:
case 96000:
mclk = 12288000;
break;
case 11025:
case 22050:
case 44100:
case 88200:
mclk = 11289600;
break;
default:
return -EINVAL;
}
ret = snd_soc_dai_set_sysclk(cpu_dai, 0, mclk,
SND_SOC_CLOCK_OUT);
if (ret) {
dev_err(cpu_dai->dev, "Can't set cpu dai clock %d\n", ret);
return ret;
}
ret = snd_soc_dai_set_sysclk(codec_dai, 0, mclk,
SND_SOC_CLOCK_IN);
/* HDMI codec dai does not need to set sysclk. */
if (!strcmp(rtd->dai_link->name, "HDMI"))
return 0;
if (ret) {
dev_err(codec_dai->dev, "Can't set codec dai clock %d\n", ret);
return ret;
}
return ret;
}
static int rk_aif1_startup(struct snd_pcm_substream *substream)
{
/*
* Set period size to 240 because pl330 has issue
* dealing with larger period in stress testing.
*/
return snd_pcm_hw_constraint_minmax(substream->runtime,
SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 240, 240);
}
static const struct snd_soc_ops rk_aif1_ops = {
.hw_params = rk_aif1_hw_params,
.startup = rk_aif1_startup,
};
SND_SOC_DAILINK_DEFS(analog,
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "HiFi")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
SND_SOC_DAILINK_DEFS(hdmi,
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "i2s-hifi")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
enum {
DAILINK_MAX98090,
DAILINK_HDMI,
};
static struct snd_soc_jack rk_hdmi_jack;
static int rk_hdmi_init(struct snd_soc_pcm_runtime *runtime)
{
struct snd_soc_card *card = runtime->card;
struct snd_soc_component *component = asoc_rtd_to_codec(runtime, 0)->component;
int ret;
/* enable jack detection */
ret = snd_soc_card_jack_new(card, "HDMI Jack", SND_JACK_LINEOUT,
&rk_hdmi_jack);
if (ret) {
dev_err(card->dev, "Can't new HDMI Jack %d\n", ret);
return ret;
}
return snd_soc_component_set_jack(component, &rk_hdmi_jack, NULL);
}
/* max98090 dai_link */
static struct snd_soc_dai_link rk_max98090_dailinks[] = {
{
.name = "max98090",
.stream_name = "Analog",
.init = rk_init,
.ops = &rk_aif1_ops,
/* set max98090 as slave */
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS,
SND_SOC_DAILINK_REG(analog),
},
};
/* HDMI codec dai_link */
static struct snd_soc_dai_link rk_hdmi_dailinks[] = {
{
.name = "HDMI",
.stream_name = "HDMI",
.init = rk_hdmi_init,
.ops = &rk_aif1_ops,
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS,
SND_SOC_DAILINK_REG(hdmi),
}
};
/* max98090 and HDMI codec dai_link */
static struct snd_soc_dai_link rk_max98090_hdmi_dailinks[] = {
[DAILINK_MAX98090] = {
.name = "max98090",
.stream_name = "Analog",
.init = rk_init,
.ops = &rk_aif1_ops,
/* set max98090 as slave */
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS,
SND_SOC_DAILINK_REG(analog),
},
[DAILINK_HDMI] = {
.name = "HDMI",
.stream_name = "HDMI",
.init = rk_hdmi_init,
.ops = &rk_aif1_ops,
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS,
SND_SOC_DAILINK_REG(hdmi),
}
};
static int rk_98090_headset_init(struct snd_soc_component *component);
static struct snd_soc_aux_dev rk_98090_headset_dev = {
.dlc = COMP_EMPTY(),
.init = rk_98090_headset_init,
};
static struct snd_soc_card rockchip_max98090_card = {
.name = "ROCKCHIP-I2S",
.owner = THIS_MODULE,
.dai_link = rk_max98090_dailinks,
.num_links = ARRAY_SIZE(rk_max98090_dailinks),
.aux_dev = &rk_98090_headset_dev,
.num_aux_devs = 1,
.dapm_widgets = rk_max98090_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rk_max98090_dapm_widgets),
.dapm_routes = rk_max98090_audio_map,
.num_dapm_routes = ARRAY_SIZE(rk_max98090_audio_map),
.controls = rk_max98090_controls,
.num_controls = ARRAY_SIZE(rk_max98090_controls),
};
static struct snd_soc_card rockchip_hdmi_card = {
.name = "ROCKCHIP-HDMI",
.owner = THIS_MODULE,
.dai_link = rk_hdmi_dailinks,
.num_links = ARRAY_SIZE(rk_hdmi_dailinks),
.dapm_widgets = rk_hdmi_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rk_hdmi_dapm_widgets),
.dapm_routes = rk_hdmi_audio_map,
.num_dapm_routes = ARRAY_SIZE(rk_hdmi_audio_map),
.controls = rk_hdmi_controls,
.num_controls = ARRAY_SIZE(rk_hdmi_controls),
};
static struct snd_soc_card rockchip_max98090_hdmi_card = {
.name = "ROCKCHIP-MAX98090-HDMI",
.owner = THIS_MODULE,
.dai_link = rk_max98090_hdmi_dailinks,
.num_links = ARRAY_SIZE(rk_max98090_hdmi_dailinks),
.aux_dev = &rk_98090_headset_dev,
.num_aux_devs = 1,
.dapm_widgets = rk_max98090_hdmi_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rk_max98090_hdmi_dapm_widgets),
.dapm_routes = rk_max98090_hdmi_audio_map,
.num_dapm_routes = ARRAY_SIZE(rk_max98090_hdmi_audio_map),
.controls = rk_max98090_hdmi_controls,
.num_controls = ARRAY_SIZE(rk_max98090_hdmi_controls),
};
static int rk_98090_headset_init(struct snd_soc_component *component)
{
int ret;
/* Enable Headset and 4 Buttons Jack detection */
ret = snd_soc_card_jack_new_pins(component->card, "Headset Jack",
SND_JACK_HEADSET |
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3,
&headset_jack,
headset_jack_pins,
ARRAY_SIZE(headset_jack_pins));
if (ret)
return ret;
ret = ts3a227e_enable_jack_detect(component, &headset_jack);
return ret;
}
static int rk_parse_headset_from_of(struct device *dev, struct device_node *np)
{
rk_98090_headset_dev.dlc.of_node = of_parse_phandle(
np, "rockchip,headset-codec", 0);
if (!rk_98090_headset_dev.dlc.of_node) {
dev_err(dev,
"Property 'rockchip,headset-codec' missing/invalid\n");
return -EINVAL;
}
return 0;
}
static int snd_rk_mc_probe(struct platform_device *pdev)
{
int ret = 0;
struct snd_soc_card *card;
struct device *dev = &pdev->dev;
struct device_node *np = pdev->dev.of_node;
struct device_node *np_cpu;
struct device_node *np_audio, *np_hdmi;
/* Parse DTS for I2S controller. */
np_cpu = of_parse_phandle(np, "rockchip,i2s-controller", 0);
if (!np_cpu) {
dev_err(&pdev->dev,
"Property 'rockchip,i2s-controller missing or invalid\n");
return -EINVAL;
}
/*
* Find the card to use based on the presences of audio codec
* and hdmi codec in device property. Set their of_node accordingly.
*/
np_audio = of_parse_phandle(np, "rockchip,audio-codec", 0);
np_hdmi = of_parse_phandle(np, "rockchip,hdmi-codec", 0);
if (np_audio && np_hdmi) {
card = &rockchip_max98090_hdmi_card;
card->dai_link[DAILINK_MAX98090].codecs->of_node = np_audio;
card->dai_link[DAILINK_HDMI].codecs->of_node = np_hdmi;
card->dai_link[DAILINK_MAX98090].cpus->of_node = np_cpu;
card->dai_link[DAILINK_MAX98090].platforms->of_node = np_cpu;
card->dai_link[DAILINK_HDMI].cpus->of_node = np_cpu;
card->dai_link[DAILINK_HDMI].platforms->of_node = np_cpu;
} else if (np_audio) {
card = &rockchip_max98090_card;
card->dai_link[0].codecs->of_node = np_audio;
card->dai_link[0].cpus->of_node = np_cpu;
card->dai_link[0].platforms->of_node = np_cpu;
} else if (np_hdmi) {
card = &rockchip_hdmi_card;
card->dai_link[0].codecs->of_node = np_hdmi;
card->dai_link[0].cpus->of_node = np_cpu;
card->dai_link[0].platforms->of_node = np_cpu;
} else {
dev_err(dev, "At least one of codecs should be specified\n");
return -EINVAL;
}
card->dev = dev;
/* Parse headset detection codec. */
if (np_audio) {
ret = rk_parse_headset_from_of(dev, np);
if (ret)
return ret;
}
/* Parse card name. */
ret = snd_soc_of_parse_card_name(card, "rockchip,model");
if (ret) {
dev_err(&pdev->dev,
"Soc parse card name failed %d\n", ret);
return ret;
}
/* register the soc card */
ret = devm_snd_soc_register_card(&pdev->dev, card);
if (ret) {
dev_err(&pdev->dev,
"Soc register card failed %d\n", ret);
return ret;
}
return ret;
}
static const struct of_device_id rockchip_max98090_of_match[] = {
{ .compatible = "rockchip,rockchip-audio-max98090", },
{},
};
MODULE_DEVICE_TABLE(of, rockchip_max98090_of_match);
static struct platform_driver snd_rk_mc_driver = {
.probe = snd_rk_mc_probe,
.driver = {
.name = DRV_NAME,
.pm = &snd_soc_pm_ops,
.of_match_table = rockchip_max98090_of_match,
},
};
module_platform_driver(snd_rk_mc_driver);
MODULE_AUTHOR("jianqun <[email protected]>");
MODULE_DESCRIPTION("Rockchip max98090 machine ASoC driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRV_NAME);
| linux-master | sound/soc/rockchip/rockchip_max98090.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Rockchip PDM ALSA SoC Digital Audio Interface(DAI) driver
*
* Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd
*/
#include <linux/module.h>
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pm_runtime.h>
#include <linux/rational.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <sound/dmaengine_pcm.h>
#include <sound/pcm_params.h>
#include "rockchip_pdm.h"
#define PDM_DMA_BURST_SIZE (8) /* size * width: 8*4 = 32 bytes */
#define PDM_SIGNOFF_CLK_RATE (100000000)
#define PDM_PATH_MAX (4)
enum rk_pdm_version {
RK_PDM_RK3229,
RK_PDM_RK3308,
RK_PDM_RV1126,
};
struct rk_pdm_dev {
struct device *dev;
struct clk *clk;
struct clk *hclk;
struct regmap *regmap;
struct snd_dmaengine_dai_dma_data capture_dma_data;
struct reset_control *reset;
enum rk_pdm_version version;
};
struct rk_pdm_clkref {
unsigned int sr;
unsigned int clk;
unsigned int clk_out;
};
struct rk_pdm_ds_ratio {
unsigned int ratio;
unsigned int sr;
};
static struct rk_pdm_clkref clkref[] = {
{ 8000, 40960000, 2048000 },
{ 11025, 56448000, 2822400 },
{ 12000, 61440000, 3072000 },
{ 8000, 98304000, 2048000 },
{ 12000, 98304000, 3072000 },
};
static struct rk_pdm_ds_ratio ds_ratio[] = {
{ 0, 192000 },
{ 0, 176400 },
{ 0, 128000 },
{ 1, 96000 },
{ 1, 88200 },
{ 1, 64000 },
{ 2, 48000 },
{ 2, 44100 },
{ 2, 32000 },
{ 3, 24000 },
{ 3, 22050 },
{ 3, 16000 },
{ 4, 12000 },
{ 4, 11025 },
{ 4, 8000 },
};
static unsigned int get_pdm_clk(struct rk_pdm_dev *pdm, unsigned int sr,
unsigned int *clk_src, unsigned int *clk_out)
{
unsigned int i, count, clk, div, rate;
clk = 0;
if (!sr)
return clk;
count = ARRAY_SIZE(clkref);
for (i = 0; i < count; i++) {
if (sr % clkref[i].sr)
continue;
div = sr / clkref[i].sr;
if ((div & (div - 1)) == 0) {
*clk_out = clkref[i].clk_out;
rate = clk_round_rate(pdm->clk, clkref[i].clk);
if (rate != clkref[i].clk)
continue;
clk = clkref[i].clk;
*clk_src = clkref[i].clk;
break;
}
}
if (!clk) {
clk = clk_round_rate(pdm->clk, PDM_SIGNOFF_CLK_RATE);
*clk_src = clk;
}
return clk;
}
static unsigned int get_pdm_ds_ratio(unsigned int sr)
{
unsigned int i, count, ratio;
ratio = 0;
if (!sr)
return ratio;
count = ARRAY_SIZE(ds_ratio);
for (i = 0; i < count; i++) {
if (sr == ds_ratio[i].sr)
ratio = ds_ratio[i].ratio;
}
return ratio;
}
static unsigned int get_pdm_cic_ratio(unsigned int clk)
{
switch (clk) {
case 4096000:
case 5644800:
case 6144000:
return 0;
case 2048000:
case 2822400:
case 3072000:
return 1;
case 1024000:
case 1411200:
case 1536000:
return 2;
default:
return 1;
}
}
static unsigned int samplerate_to_bit(unsigned int samplerate)
{
switch (samplerate) {
case 8000:
case 11025:
case 12000:
return 0;
case 16000:
case 22050:
case 24000:
return 1;
case 32000:
return 2;
case 44100:
case 48000:
return 3;
case 64000:
case 88200:
case 96000:
return 4;
case 128000:
case 176400:
case 192000:
return 5;
default:
return 1;
}
}
static inline struct rk_pdm_dev *to_info(struct snd_soc_dai *dai)
{
return snd_soc_dai_get_drvdata(dai);
}
static void rockchip_pdm_rxctrl(struct rk_pdm_dev *pdm, int on)
{
if (on) {
regmap_update_bits(pdm->regmap, PDM_DMA_CTRL,
PDM_DMA_RD_MSK, PDM_DMA_RD_EN);
regmap_update_bits(pdm->regmap, PDM_SYSCONFIG,
PDM_RX_MASK, PDM_RX_START);
} else {
regmap_update_bits(pdm->regmap, PDM_DMA_CTRL,
PDM_DMA_RD_MSK, PDM_DMA_RD_DIS);
regmap_update_bits(pdm->regmap, PDM_SYSCONFIG,
PDM_RX_MASK | PDM_RX_CLR_MASK,
PDM_RX_STOP | PDM_RX_CLR_WR);
}
}
static int rockchip_pdm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct rk_pdm_dev *pdm = to_info(dai);
unsigned int val = 0;
unsigned int clk_rate, clk_div, samplerate;
unsigned int clk_src, clk_out = 0;
unsigned long m, n;
bool change;
int ret;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
return 0;
samplerate = params_rate(params);
clk_rate = get_pdm_clk(pdm, samplerate, &clk_src, &clk_out);
if (!clk_rate)
return -EINVAL;
ret = clk_set_rate(pdm->clk, clk_src);
if (ret)
return -EINVAL;
if (pdm->version == RK_PDM_RK3308 ||
pdm->version == RK_PDM_RV1126) {
rational_best_approximation(clk_out, clk_src,
GENMASK(16 - 1, 0),
GENMASK(16 - 1, 0),
&m, &n);
val = (m << PDM_FD_NUMERATOR_SFT) |
(n << PDM_FD_DENOMINATOR_SFT);
regmap_update_bits_check(pdm->regmap, PDM_CTRL1,
PDM_FD_NUMERATOR_MSK |
PDM_FD_DENOMINATOR_MSK,
val, &change);
if (change) {
reset_control_assert(pdm->reset);
reset_control_deassert(pdm->reset);
rockchip_pdm_rxctrl(pdm, 0);
}
clk_div = n / m;
if (clk_div >= 40)
val = PDM_CLK_FD_RATIO_40;
else if (clk_div <= 35)
val = PDM_CLK_FD_RATIO_35;
else
return -EINVAL;
regmap_update_bits(pdm->regmap, PDM_CLK_CTRL,
PDM_CLK_FD_RATIO_MSK,
val);
}
if (pdm->version == RK_PDM_RV1126) {
val = get_pdm_cic_ratio(clk_out);
regmap_update_bits(pdm->regmap, PDM_CLK_CTRL, PDM_CIC_RATIO_MSK, val);
val = samplerate_to_bit(samplerate);
regmap_update_bits(pdm->regmap, PDM_CTRL0,
PDM_SAMPLERATE_MSK, PDM_SAMPLERATE(val));
} else {
val = get_pdm_ds_ratio(samplerate);
regmap_update_bits(pdm->regmap, PDM_CLK_CTRL, PDM_DS_RATIO_MSK, val);
}
regmap_update_bits(pdm->regmap, PDM_HPF_CTRL,
PDM_HPF_CF_MSK, PDM_HPF_60HZ);
regmap_update_bits(pdm->regmap, PDM_HPF_CTRL,
PDM_HPF_LE | PDM_HPF_RE, PDM_HPF_LE | PDM_HPF_RE);
regmap_update_bits(pdm->regmap, PDM_CLK_CTRL, PDM_CLK_EN, PDM_CLK_EN);
if (pdm->version != RK_PDM_RK3229)
regmap_update_bits(pdm->regmap, PDM_CTRL0,
PDM_MODE_MSK, PDM_MODE_LJ);
val = 0;
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S8:
val |= PDM_VDW(8);
break;
case SNDRV_PCM_FORMAT_S16_LE:
val |= PDM_VDW(16);
break;
case SNDRV_PCM_FORMAT_S20_3LE:
val |= PDM_VDW(20);
break;
case SNDRV_PCM_FORMAT_S24_LE:
val |= PDM_VDW(24);
break;
case SNDRV_PCM_FORMAT_S32_LE:
val |= PDM_VDW(32);
break;
default:
return -EINVAL;
}
switch (params_channels(params)) {
case 8:
val |= PDM_PATH3_EN;
fallthrough;
case 6:
val |= PDM_PATH2_EN;
fallthrough;
case 4:
val |= PDM_PATH1_EN;
fallthrough;
case 2:
val |= PDM_PATH0_EN;
break;
default:
dev_err(pdm->dev, "invalid channel: %d\n",
params_channels(params));
return -EINVAL;
}
regmap_update_bits(pdm->regmap, PDM_CTRL0,
PDM_PATH_MSK | PDM_VDW_MSK,
val);
/* all channels share the single FIFO */
regmap_update_bits(pdm->regmap, PDM_DMA_CTRL, PDM_DMA_RDL_MSK,
PDM_DMA_RDL(8 * params_channels(params)));
return 0;
}
static int rockchip_pdm_set_fmt(struct snd_soc_dai *cpu_dai,
unsigned int fmt)
{
struct rk_pdm_dev *pdm = to_info(cpu_dai);
unsigned int mask = 0, val = 0;
mask = PDM_CKP_MSK;
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
val = PDM_CKP_NORMAL;
break;
case SND_SOC_DAIFMT_IB_NF:
val = PDM_CKP_INVERTED;
break;
default:
return -EINVAL;
}
pm_runtime_get_sync(cpu_dai->dev);
regmap_update_bits(pdm->regmap, PDM_CLK_CTRL, mask, val);
pm_runtime_put(cpu_dai->dev);
return 0;
}
static int rockchip_pdm_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct rk_pdm_dev *pdm = to_info(dai);
int ret = 0;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
rockchip_pdm_rxctrl(pdm, 1);
break;
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
rockchip_pdm_rxctrl(pdm, 0);
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
static int rockchip_pdm_dai_probe(struct snd_soc_dai *dai)
{
struct rk_pdm_dev *pdm = to_info(dai);
snd_soc_dai_dma_data_set_capture(dai, &pdm->capture_dma_data);
return 0;
}
static const struct snd_soc_dai_ops rockchip_pdm_dai_ops = {
.probe = rockchip_pdm_dai_probe,
.set_fmt = rockchip_pdm_set_fmt,
.trigger = rockchip_pdm_trigger,
.hw_params = rockchip_pdm_hw_params,
};
#define ROCKCHIP_PDM_RATES SNDRV_PCM_RATE_8000_192000
#define ROCKCHIP_PDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver rockchip_pdm_dai = {
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 8,
.rates = ROCKCHIP_PDM_RATES,
.formats = ROCKCHIP_PDM_FORMATS,
},
.ops = &rockchip_pdm_dai_ops,
.symmetric_rate = 1,
};
static const struct snd_soc_component_driver rockchip_pdm_component = {
.name = "rockchip-pdm",
.legacy_dai_naming = 1,
};
static int rockchip_pdm_runtime_suspend(struct device *dev)
{
struct rk_pdm_dev *pdm = dev_get_drvdata(dev);
clk_disable_unprepare(pdm->clk);
clk_disable_unprepare(pdm->hclk);
return 0;
}
static int rockchip_pdm_runtime_resume(struct device *dev)
{
struct rk_pdm_dev *pdm = dev_get_drvdata(dev);
int ret;
ret = clk_prepare_enable(pdm->clk);
if (ret) {
dev_err(pdm->dev, "clock enable failed %d\n", ret);
return ret;
}
ret = clk_prepare_enable(pdm->hclk);
if (ret) {
clk_disable_unprepare(pdm->clk);
dev_err(pdm->dev, "hclock enable failed %d\n", ret);
return ret;
}
return 0;
}
static bool rockchip_pdm_wr_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case PDM_SYSCONFIG:
case PDM_CTRL0:
case PDM_CTRL1:
case PDM_CLK_CTRL:
case PDM_HPF_CTRL:
case PDM_FIFO_CTRL:
case PDM_DMA_CTRL:
case PDM_INT_EN:
case PDM_INT_CLR:
case PDM_DATA_VALID:
return true;
default:
return false;
}
}
static bool rockchip_pdm_rd_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case PDM_SYSCONFIG:
case PDM_CTRL0:
case PDM_CTRL1:
case PDM_CLK_CTRL:
case PDM_HPF_CTRL:
case PDM_FIFO_CTRL:
case PDM_DMA_CTRL:
case PDM_INT_EN:
case PDM_INT_CLR:
case PDM_INT_ST:
case PDM_DATA_VALID:
case PDM_RXFIFO_DATA:
case PDM_VERSION:
return true;
default:
return false;
}
}
static bool rockchip_pdm_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case PDM_SYSCONFIG:
case PDM_FIFO_CTRL:
case PDM_INT_CLR:
case PDM_INT_ST:
case PDM_RXFIFO_DATA:
return true;
default:
return false;
}
}
static bool rockchip_pdm_precious_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case PDM_RXFIFO_DATA:
return true;
default:
return false;
}
}
static const struct reg_default rockchip_pdm_reg_defaults[] = {
{ PDM_CTRL0, 0x78000017 },
{ PDM_CTRL1, 0x0bb8ea60 },
{ PDM_CLK_CTRL, 0x0000e401 },
{ PDM_DMA_CTRL, 0x0000001f },
};
static const struct regmap_config rockchip_pdm_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = PDM_VERSION,
.reg_defaults = rockchip_pdm_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(rockchip_pdm_reg_defaults),
.writeable_reg = rockchip_pdm_wr_reg,
.readable_reg = rockchip_pdm_rd_reg,
.volatile_reg = rockchip_pdm_volatile_reg,
.precious_reg = rockchip_pdm_precious_reg,
.cache_type = REGCACHE_FLAT,
};
static const struct of_device_id rockchip_pdm_match[] __maybe_unused = {
{ .compatible = "rockchip,pdm",
.data = (void *)RK_PDM_RK3229 },
{ .compatible = "rockchip,px30-pdm",
.data = (void *)RK_PDM_RK3308 },
{ .compatible = "rockchip,rk1808-pdm",
.data = (void *)RK_PDM_RK3308 },
{ .compatible = "rockchip,rk3308-pdm",
.data = (void *)RK_PDM_RK3308 },
{ .compatible = "rockchip,rk3568-pdm",
.data = (void *)RK_PDM_RV1126 },
{ .compatible = "rockchip,rv1126-pdm",
.data = (void *)RK_PDM_RV1126 },
{},
};
MODULE_DEVICE_TABLE(of, rockchip_pdm_match);
static int rockchip_pdm_path_parse(struct rk_pdm_dev *pdm, struct device_node *node)
{
unsigned int path[PDM_PATH_MAX];
int cnt = 0, ret = 0, i = 0, val = 0, msk = 0;
cnt = of_count_phandle_with_args(node, "rockchip,path-map",
NULL);
if (cnt != PDM_PATH_MAX)
return cnt;
ret = of_property_read_u32_array(node, "rockchip,path-map",
path, cnt);
if (ret)
return ret;
for (i = 0; i < cnt; i++) {
if (path[i] >= PDM_PATH_MAX)
return -EINVAL;
msk |= PDM_PATH_MASK(i);
val |= PDM_PATH(i, path[i]);
}
regmap_update_bits(pdm->regmap, PDM_CLK_CTRL, msk, val);
return 0;
}
static int rockchip_pdm_probe(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
const struct of_device_id *match;
struct rk_pdm_dev *pdm;
struct resource *res;
void __iomem *regs;
int ret;
pdm = devm_kzalloc(&pdev->dev, sizeof(*pdm), GFP_KERNEL);
if (!pdm)
return -ENOMEM;
match = of_match_device(rockchip_pdm_match, &pdev->dev);
if (match)
pdm->version = (uintptr_t)match->data;
if (pdm->version == RK_PDM_RK3308) {
pdm->reset = devm_reset_control_get(&pdev->dev, "pdm-m");
if (IS_ERR(pdm->reset))
return PTR_ERR(pdm->reset);
}
regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(regs))
return PTR_ERR(regs);
pdm->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
&rockchip_pdm_regmap_config);
if (IS_ERR(pdm->regmap))
return PTR_ERR(pdm->regmap);
pdm->capture_dma_data.addr = res->start + PDM_RXFIFO_DATA;
pdm->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
pdm->capture_dma_data.maxburst = PDM_DMA_BURST_SIZE;
pdm->dev = &pdev->dev;
dev_set_drvdata(&pdev->dev, pdm);
pdm->clk = devm_clk_get(&pdev->dev, "pdm_clk");
if (IS_ERR(pdm->clk))
return PTR_ERR(pdm->clk);
pdm->hclk = devm_clk_get(&pdev->dev, "pdm_hclk");
if (IS_ERR(pdm->hclk))
return PTR_ERR(pdm->hclk);
ret = clk_prepare_enable(pdm->hclk);
if (ret)
return ret;
pm_runtime_enable(&pdev->dev);
if (!pm_runtime_enabled(&pdev->dev)) {
ret = rockchip_pdm_runtime_resume(&pdev->dev);
if (ret)
goto err_pm_disable;
}
ret = devm_snd_soc_register_component(&pdev->dev,
&rockchip_pdm_component,
&rockchip_pdm_dai, 1);
if (ret) {
dev_err(&pdev->dev, "could not register dai: %d\n", ret);
goto err_suspend;
}
rockchip_pdm_rxctrl(pdm, 0);
ret = rockchip_pdm_path_parse(pdm, node);
if (ret != 0 && ret != -ENOENT)
goto err_suspend;
ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
if (ret) {
dev_err(&pdev->dev, "could not register pcm: %d\n", ret);
goto err_suspend;
}
return 0;
err_suspend:
if (!pm_runtime_status_suspended(&pdev->dev))
rockchip_pdm_runtime_suspend(&pdev->dev);
err_pm_disable:
pm_runtime_disable(&pdev->dev);
clk_disable_unprepare(pdm->hclk);
return ret;
}
static void rockchip_pdm_remove(struct platform_device *pdev)
{
struct rk_pdm_dev *pdm = dev_get_drvdata(&pdev->dev);
pm_runtime_disable(&pdev->dev);
if (!pm_runtime_status_suspended(&pdev->dev))
rockchip_pdm_runtime_suspend(&pdev->dev);
clk_disable_unprepare(pdm->clk);
clk_disable_unprepare(pdm->hclk);
}
#ifdef CONFIG_PM_SLEEP
static int rockchip_pdm_suspend(struct device *dev)
{
struct rk_pdm_dev *pdm = dev_get_drvdata(dev);
regcache_mark_dirty(pdm->regmap);
return 0;
}
static int rockchip_pdm_resume(struct device *dev)
{
struct rk_pdm_dev *pdm = dev_get_drvdata(dev);
int ret;
ret = pm_runtime_resume_and_get(dev);
if (ret < 0)
return ret;
ret = regcache_sync(pdm->regmap);
pm_runtime_put(dev);
return ret;
}
#endif
static const struct dev_pm_ops rockchip_pdm_pm_ops = {
SET_RUNTIME_PM_OPS(rockchip_pdm_runtime_suspend,
rockchip_pdm_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(rockchip_pdm_suspend, rockchip_pdm_resume)
};
static struct platform_driver rockchip_pdm_driver = {
.probe = rockchip_pdm_probe,
.remove_new = rockchip_pdm_remove,
.driver = {
.name = "rockchip-pdm",
.of_match_table = of_match_ptr(rockchip_pdm_match),
.pm = &rockchip_pdm_pm_ops,
},
};
module_platform_driver(rockchip_pdm_driver);
MODULE_AUTHOR("Sugar <[email protected]>");
MODULE_DESCRIPTION("Rockchip PDM Controller Driver");
MODULE_LICENSE("GPL v2");
| linux-master | sound/soc/rockchip/rockchip_pdm.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Rockchip machine ASoC driver for RK3288 boards that have an HDMI and analog
* audio output
*
* Copyright (c) 2016, Collabora Ltd.
*
* Authors: Sjoerd Simons <[email protected]>,
* Romain Perier <[email protected]>
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/gpio.h>
#include <linux/of_gpio.h>
#include <sound/core.h>
#include <sound/jack.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include "rockchip_i2s.h"
#define DRV_NAME "rk3288-snd-hdmi-analog"
struct rk_drvdata {
int gpio_hp_en;
int gpio_hp_det;
};
static int rk_hp_power(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *k, int event)
{
struct rk_drvdata *machine = snd_soc_card_get_drvdata(w->dapm->card);
if (!gpio_is_valid(machine->gpio_hp_en))
return 0;
gpio_set_value_cansleep(machine->gpio_hp_en,
SND_SOC_DAPM_EVENT_ON(event));
return 0;
}
static struct snd_soc_jack headphone_jack;
static struct snd_soc_jack_pin headphone_jack_pins[] = {
{
.pin = "Analog",
.mask = SND_JACK_HEADPHONE
},
};
static const struct snd_soc_dapm_widget rk_dapm_widgets[] = {
SND_SOC_DAPM_HP("Analog", rk_hp_power),
SND_SOC_DAPM_LINE("HDMI", NULL),
};
static const struct snd_kcontrol_new rk_mc_controls[] = {
SOC_DAPM_PIN_SWITCH("Analog"),
SOC_DAPM_PIN_SWITCH("HDMI"),
};
static int rk_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
int ret = 0;
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
int mclk;
switch (params_rate(params)) {
case 8000:
case 16000:
case 24000:
case 32000:
case 48000:
case 64000:
case 96000:
mclk = 12288000;
break;
case 192000:
mclk = 24576000;
break;
case 11025:
case 22050:
case 44100:
case 88200:
mclk = 11289600;
break;
default:
return -EINVAL;
}
ret = snd_soc_dai_set_sysclk(cpu_dai, 0, mclk,
SND_SOC_CLOCK_OUT);
if (ret && ret != -ENOTSUPP) {
dev_err(codec_dai->dev, "Can't set cpu clock %d\n", ret);
return ret;
}
ret = snd_soc_dai_set_sysclk(codec_dai, 0, mclk,
SND_SOC_CLOCK_IN);
if (ret && ret != -ENOTSUPP) {
dev_err(codec_dai->dev, "Can't set codec clock %d\n", ret);
return ret;
}
return 0;
}
static struct snd_soc_jack_gpio rk_hp_jack_gpio = {
.name = "Headphone detection",
.report = SND_JACK_HEADPHONE,
.debounce_time = 150
};
static int rk_init(struct snd_soc_pcm_runtime *runtime)
{
struct rk_drvdata *machine = snd_soc_card_get_drvdata(runtime->card);
/* Enable Headset Jack detection */
if (gpio_is_valid(machine->gpio_hp_det)) {
snd_soc_card_jack_new_pins(runtime->card, "Headphone Jack",
SND_JACK_HEADPHONE, &headphone_jack,
headphone_jack_pins,
ARRAY_SIZE(headphone_jack_pins));
rk_hp_jack_gpio.gpio = machine->gpio_hp_det;
snd_soc_jack_add_gpios(&headphone_jack, 1, &rk_hp_jack_gpio);
}
return 0;
}
static const struct snd_soc_ops rk_ops = {
.hw_params = rk_hw_params,
};
SND_SOC_DAILINK_DEFS(audio,
DAILINK_COMP_ARRAY(COMP_EMPTY()),
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, NULL),
COMP_CODEC("hdmi-audio-codec.2.auto", "i2s-hifi")),
DAILINK_COMP_ARRAY(COMP_EMPTY()));
static struct snd_soc_dai_link rk_dailink = {
.name = "Codecs",
.stream_name = "Audio",
.init = rk_init,
.ops = &rk_ops,
/* Set codecs as slave */
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS,
SND_SOC_DAILINK_REG(audio),
};
static struct snd_soc_card snd_soc_card_rk = {
.name = "ROCKCHIP-I2S",
.dai_link = &rk_dailink,
.num_links = 1,
.num_aux_devs = 0,
.dapm_widgets = rk_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(rk_dapm_widgets),
.controls = rk_mc_controls,
.num_controls = ARRAY_SIZE(rk_mc_controls),
};
static int snd_rk_mc_probe(struct platform_device *pdev)
{
int ret;
struct snd_soc_card *card = &snd_soc_card_rk;
struct device_node *np = pdev->dev.of_node;
struct rk_drvdata *machine;
struct of_phandle_args args;
machine = devm_kzalloc(&pdev->dev, sizeof(struct rk_drvdata),
GFP_KERNEL);
if (!machine)
return -ENOMEM;
card->dev = &pdev->dev;
machine->gpio_hp_det = of_get_named_gpio(np,
"rockchip,hp-det-gpios", 0);
if (!gpio_is_valid(machine->gpio_hp_det) && machine->gpio_hp_det != -ENODEV)
return machine->gpio_hp_det;
machine->gpio_hp_en = of_get_named_gpio(np,
"rockchip,hp-en-gpios", 0);
if (!gpio_is_valid(machine->gpio_hp_en) && machine->gpio_hp_en != -ENODEV)
return machine->gpio_hp_en;
if (gpio_is_valid(machine->gpio_hp_en)) {
ret = devm_gpio_request_one(&pdev->dev, machine->gpio_hp_en,
GPIOF_OUT_INIT_LOW, "hp_en");
if (ret) {
dev_err(card->dev, "cannot get hp_en gpio\n");
return ret;
}
}
ret = snd_soc_of_parse_card_name(card, "rockchip,model");
if (ret) {
dev_err(card->dev, "SoC parse card name failed %d\n", ret);
return ret;
}
rk_dailink.codecs[0].of_node = of_parse_phandle(np,
"rockchip,audio-codec",
0);
if (!rk_dailink.codecs[0].of_node) {
dev_err(&pdev->dev,
"Property 'rockchip,audio-codec' missing or invalid\n");
return -EINVAL;
}
ret = of_parse_phandle_with_fixed_args(np, "rockchip,audio-codec",
0, 0, &args);
if (ret) {
dev_err(&pdev->dev,
"Unable to parse property 'rockchip,audio-codec'\n");
return ret;
}
ret = snd_soc_get_dai_name(&args, &rk_dailink.codecs[0].dai_name);
if (ret) {
dev_err(&pdev->dev, "Unable to get codec_dai_name\n");
return ret;
}
rk_dailink.cpus->of_node = of_parse_phandle(np, "rockchip,i2s-controller",
0);
if (!rk_dailink.cpus->of_node) {
dev_err(&pdev->dev,
"Property 'rockchip,i2s-controller' missing or invalid\n");
return -EINVAL;
}
rk_dailink.platforms->of_node = rk_dailink.cpus->of_node;
ret = snd_soc_of_parse_audio_routing(card, "rockchip,routing");
if (ret) {
dev_err(&pdev->dev,
"Unable to parse 'rockchip,routing' property\n");
return ret;
}
snd_soc_card_set_drvdata(card, machine);
ret = devm_snd_soc_register_card(&pdev->dev, card);
if (ret)
return dev_err_probe(&pdev->dev, ret,
"Soc register card failed\n");
return 0;
}
static const struct of_device_id rockchip_sound_of_match[] = {
{ .compatible = "rockchip,rk3288-hdmi-analog", },
{},
};
MODULE_DEVICE_TABLE(of, rockchip_sound_of_match);
static struct platform_driver rockchip_sound_driver = {
.probe = snd_rk_mc_probe,
.driver = {
.name = DRV_NAME,
.pm = &snd_soc_pm_ops,
.of_match_table = rockchip_sound_of_match,
},
};
module_platform_driver(rockchip_sound_driver);
MODULE_AUTHOR("Sjoerd Simons <[email protected]>");
MODULE_DESCRIPTION("Rockchip RK3288 machine ASoC driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRV_NAME);
| linux-master | sound/soc/rockchip/rk3288_hdmi_analog.c |
Subsets and Splits